1388 files changed, 162246 insertions, 385771 deletions
diff --git a/os/common/ports/ARMCMx/compilers/GCC/crt0.c b/os/common/ports/ARMCMx/compilers/GCC/crt0.c
new file mode 100644
index 000000000..31437a35e
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/crt0.c
@@ -0,0 +1,354 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/GCC/crt0.c
+ * @brief   Generic GCC Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP
+ * @{
+ */
+
+#include <stdint.h>
+
+#if !defined(FALSE)
+#define FALSE       0
+#endif
+
+#if !defined(TRUE)
+#define TRUE        (!FALSE)
+#endif
+
+#define SCB_CPACR               *((uint32_t *)0xE000ED88U)
+#define SCB_FPCCR               *((uint32_t *)0xE000EF34U)
+#define SCB_FPDSCR              *((uint32_t *)0xE000EF3CU)
+#define FPCCR_ASPEN             (0x1U << 31)
+#define FPCCR_LSPEN             (0x1U << 30)
+
+typedef void (*funcp_t)(void);
+typedef funcp_t * funcpp_t;
+
+#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
+
+/*
+ * Area fill code, it is a macro because here functions cannot be called
+ * until stacks are initialized.
+ */
+#define fill32(start, end, filler) {                                        \
+  uint32_t *p1 = (start);                                                   \
+  uint32_t *p2 = (end);                                                     \
+  while (p1 < p2)                                                           \
+    *p1++ = (filler);                                                       \
+}
+
+/*===========================================================================*/
+/**
+ * @name    Startup settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Control special register initialization value.
+ * @details The system is setup to run in privileged mode using the PSP
+ *          stack (dual stack mode).
+ */
+#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
+#define CRT0_CONTROL_INIT           0x00000002
+#endif
+
+/**
+ * @brief   Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN    0x55555555
+#endif
+
+/**
+ * @brief   Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS            TRUE
+#endif
+
+/**
+ * @brief   DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA              TRUE
+#endif
+
+/**
+ * @brief   BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS               TRUE
+#endif
+
+/**
+ * @brief   Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS      TRUE
+#endif
+
+/**
+ * @brief   Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS       TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name    Symbols from the scatter file
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Main stack lower boundary.
+ * @details This symbol must be exported by the linker script and represents
+ *          the main stack lower boundary.
+ */
+extern uint32_t __main_stack_base__;
+
+/**
+ *
+ * @brief   Main stack initial position.
+ * @details This symbol must be exported by the linker script and represents
+ *          the main stack initial position.
+ */
+extern uint32_t __main_stack_end__;
+
+/**
+ * @brief   Process stack lower boundary.
+ * @details This symbol must be exported by the linker script and represents
+ *          the process stack lower boundary.
+ */
+extern uint32_t __process_stack_base__;
+
+/**
+ * @brief   Process stack initial position.
+ * @details This symbol must be exported by the linker script and represents
+ *          the process stack initial position.
+ */
+extern uint32_t __process_stack_end__;
+
+/**
+ * @brief   ROM image of the data segment start.
+ * @pre     The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _textdata;
+
+/**
+ * @brief   Data segment start.
+ * @pre     The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _data;
+
+/**
+ * @brief   Data segment end.
+ * @pre     The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _edata;
+
+/**
+ * @brief   BSS segment start.
+ * @pre     The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _bss_start;
+
+/**
+ * @brief   BSS segment end.
+ * @pre     The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _bss_end;
+
+/**
+ * @brief   Constructors table start.
+ * @pre     The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __init_array_start;
+
+/**
+ * @brief   Constructors table end.
+ * @pre     The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __init_array_end;
+
+/**
+ * @brief   Destructors table start.
+ * @pre     The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __fini_array_start;
+
+/**
+ * @brief   Destructors table end.
+ * @pre     The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __fini_array_end;
+
+/** @} */
+
+/**
+ * @brief   Application @p main() function.
+ */
+extern void main(void);
+
+/**
+ * @brief   Early initialization.
+ * @details This hook is invoked immediately after the stack initialization
+ *          and before the DATA and BSS segments initialization. The
+ *          default behavior is to do nothing.
+ * @note    This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+void __early_init(void) {}
+
+/**
+ * @brief   Late initialization.
+ * @details This hook is invoked after the DATA and BSS segments
+ *          initialization and before any static constructor. The
+ *          default behavior is to do nothing.
+ * @note    This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+void __late_init(void) {}
+
+/**
+ * @brief   Default @p main() function exit handler.
+ * @details This handler is invoked or the @p main() function exit. The
+ *          default behavior is to enter an infinite loop.
+ * @note    This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((noreturn, weak))
+#endif
+void _default_exit(void) {
+  while (1)
+    ;
+}
+
+/**
+ * @brief   Reset vector.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((naked))
+#endif
+void Reset_Handler(void) {
+  uint32_t psp, reg;
+
+  /* Process Stack initialization, it is allocated starting from the
+     symbol __process_stack_end__ and its lower limit is the symbol
+     __process_stack_base__.*/
+  asm volatile ("cpsid   i");
+  psp = SYMVAL(__process_stack_end__);
+  asm volatile ("msr     PSP, %0" : : "r" (psp));
+
+#if CORTEX_USE_FPU
+  /* Initializing the FPU context save in lazy mode.*/
+  SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
+
+  /* CP10 and CP11 set to full access.*/
+  SCB_CPACR |= 0x00F00000;
+
+  /* FPSCR and FPDSCR initially zero.*/
+  reg = 0;
+  asm volatile ("vmsr    FPSCR, %0" : : "r" (reg) : "memory");
+  SCB_FPDSCR = reg;
+
+  /* CPU mode initialization, enforced FPCA bit.*/
+  reg = CRT0_CONTROL_INIT | 4;
+#else
+  /* CPU mode initialization.*/
+  reg = CRT0_CONTROL_INIT;
+#endif
+  asm volatile ("msr     CONTROL, %0" : : "r" (reg));
+  asm volatile ("isb");
+
+#if CRT0_INIT_STACKS
+  /* Main and Process stacks initialization.*/
+  fill32(&__main_stack_base__,
+         &__main_stack_end__,
+         CRT0_STACKS_FILL_PATTERN);
+  fill32(&__process_stack_base__,
+         &__process_stack_end__,
+         CRT0_STACKS_FILL_PATTERN);
+#endif
+
+  /* Early initialization hook invocation.*/
+  __early_init();
+
+#if CRT0_INIT_DATA
+  /* DATA segment initialization.*/
+  {
+    uint32_t *tp, *dp;
+
+    tp = &_textdata;
+    dp = &_data;
+    while (dp < &_edata)
+      *dp++ = *tp++;
+  }
+#endif
+
+#if CRT0_INIT_BSS
+  /* BSS segment initialization.*/
+  fill32(&_bss_start, &_bss_end, 0);
+#endif
+
+  /* Late initialization hook invocation.*/
+  __late_init();
+
+#if CRT0_CALL_CONSTRUCTORS
+  /* Constructors invocation.*/
+  {
+    funcpp_t fpp = &__init_array_start;
+    while (fpp < &__init_array_end) {
+      (*fpp)();
+      fpp++;
+    }
+  }
+#endif
+
+  /* Invoking application main() function.*/
+  main();
+
+#if CRT0_CALL_DESTRUCTORS
+  /* Destructors invocation.*/
+  {
+    funcpp_t fpp = &__fini_array_start;
+    while (fpp < &__fini_array_end) {
+      (*fpp)();
+      fpp++;
+    }
+  }
+#endif
+
+  /* Invoking the exit handler.*/
+  _default_exit();
+}
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld
new file mode 100644
index 000000000..8e359d55d
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32F051x8 memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 64k
+    ram : org = 0x20000000, len = 8k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F100xB.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F100xB.ld
new file mode 100644
index 000000000..8cc0980b3
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F100xB.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * ST32F100xB memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 128k
+    ram : org = 0x20000000, len = 8k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xB.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xB.ld
new file mode 100644
index 000000000..f5b69dae1
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xB.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * ST32F103xB memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 128k
+    ram : org = 0x20000000, len = 20k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xD.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xD.ld
new file mode 100644
index 000000000..030dab33c
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xD.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * ST32F103xE memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 384k
+    ram : org = 0x20000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE.ld
new file mode 100644
index 000000000..96e2fea12
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * ST32F103xE memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 512k
+    ram : org = 0x20000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xG.ld
new file mode 100644
index 000000000..091c95471
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xG.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * ST32F103xG memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 1m
+    ram : org = 0x20000000, len = 96k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F107xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F107xC.ld
new file mode 100644
index 000000000..f4292b894
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F107xC.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * ST32F107xC memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 256k
+    ram : org = 0x20000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld
new file mode 100644
index 000000000..efa0d6250
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld
@@ -0,0 +1,27 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32F303xC memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 256k
+    ram : org = 0x20000000, len = 40k
+    ccmram : org = 0x10000000, len = 8k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld
new file mode 100644
index 000000000..82f8b38aa
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32F373xC memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 256k
+    ram : org = 0x20000000, len = 32k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld
new file mode 100644
index 000000000..1433b8269
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld
@@ -0,0 +1,28 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32F405xG memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 1M
+    ram : org = 0x20000000, len = 112k
+    ethram : org = 0x2001C000, len = 16k
+    ccmram : org = 0x10000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld
new file mode 100644
index 000000000..610c3e1f8
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld
@@ -0,0 +1,28 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32F407xG memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 1M
+    ram : org = 0x20000000, len = 112k
+    ethram : org = 0x2001C000, len = 16k
+    ccmram : org = 0x10000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld
new file mode 100644
index 000000000..d918b6f0f
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld
@@ -0,0 +1,27 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * ST32F429xI memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 2M
+    ram : org = 0x20000000, len = 192k
+    ccmram : org = 0x10000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld
new file mode 100644
index 000000000..a09ef86fa
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32L152xB memory setup.
+ */
+MEMORY
+{
+    flash : org = 0x08000000, len = 128k
+    ram : org = 0x20000000, len = 16k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/rules.ld b/os/common/ports/ARMCMx/compilers/GCC/rules.ld
new file mode 100644
index 000000000..f06c4ae6b
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/rules.ld
@@ -0,0 +1,137 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+__ram_start__           = ORIGIN(ram);
+__ram_size__            = LENGTH(ram);
+__ram_end__             = __ram_start__ + __ram_size__;
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    . = 0;
+    _text = .;
+
+    startup : ALIGN(16) SUBALIGN(16)
+    {
+        KEEP(*(vectors))
+    } > flash
+
+    constructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+    } > flash
+
+    destructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(.fini_array))
+        KEEP(*(SORT(.fini_array.*)))
+        PROVIDE(__fini_array_end = .);
+    } > flash
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text.startup.*)
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+    } > flash
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr :
+    {
+        *(.eh_frame_hdr)
+    } > flash
+
+    .eh_frame : ONLY_IF_RO
+    {
+        *(.eh_frame)
+    } > flash
+    
+    .textalign : ONLY_IF_RO
+    {
+        . = ALIGN(8);
+    } > flash
+
+    . = ALIGN(4);
+    _etext = .;
+    _textdata = _etext;
+
+    .stacks :
+    {
+        . = ALIGN(8);
+        __main_stack_base__ = .;
+        . += __main_stack_size__;
+        . = ALIGN(8);
+        __main_stack_end__ = .;
+        __process_stack_base__ = .;
+        __main_thread_stack_base__ = .;
+        . += __process_stack_size__;
+        . = ALIGN(8);
+        __process_stack_end__ = .;
+        __main_thread_stack_end__ = .;
+    } > ram
+
+    .data :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > ram AT > flash
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+    } > ram    
+}
+
+PROVIDE(end = .);
+_end            = .;
+
+__heap_base__   = _end;
+__heap_end__    = __ram_end__;
diff --git a/os/common/ports/ARMCMx/compilers/GCC/rules.mk b/os/common/ports/ARMCMx/compilers/GCC/rules.mk
new file mode 100644
index 000000000..e0eaf343d
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/rules.mk
@@ -0,0 +1,266 @@
+# ARM Cortex-Mx common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+  OPT += -ffunction-sections -fdata-sections -fno-common
+  LDOPT := ,--gc-sections
+else
+  LDOPT :=
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+  LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+  OPT += -flto
+endif
+
+# FPU-related options
+ifeq ($(USE_FPU),)
+  USE_FPU = no
+endif
+ifneq ($(USE_FPU),no)
+  OPT += -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+  DDEFS += -DCORTEX_USE_FPU=TRUE
+  DADEFS += -DCORTEX_USE_FPU=TRUE
+else
+  DDEFS += -DCORTEX_USE_FPU=FALSE
+  DADEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
+# Process stack size
+ifeq ($(USE_PROCESS_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
+else
+  LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
+endif
+
+# Exceptions stack size
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__main_stack_size__=0x400
+else
+  LDOPT := $(LDOPT),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+  BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+  BUILDDIR = build
+endif
+OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
+           $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp
+
+# Source files groups and paths
+ifeq ($(USE_THUMB),yes)
+  TCSRC += $(CSRC)
+  TCPPSRC += $(CPPSRC)
+else
+  ACSRC += $(CSRC)
+  ACPPSRC += $(CPPSRC)
+endif
+ASRC	  = $(ACSRC)$(ACPPSRC)
+TSRC	  = $(TCSRC)$(TCPPSRC)
+SRCPATHS  = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
+
+# Various directories
+OBJDIR    = $(BUILDDIR)/obj
+LSTDIR    = $(BUILDDIR)/lst
+
+# Object files groups
+ACOBJS    = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
+ACPPOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
+TCOBJS    = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
+TCPPOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
+ASMOBJS   = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS	  = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+
+# Paths
+IINCDIR   = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR   = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS      = $(DDEFS) $(UDEFS)
+ADEFS 	  = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS      = $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS   = -mcpu=$(MCU)
+ODFLAGS	  = -x --syms
+ASFLAGS   = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS  = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS    = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS  = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS   = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT)
+
+# Thumb interwork enabled only if needed because it kills performance.
+ifneq ($(TSRC),)
+  CFLAGS   += -DTHUMB_PRESENT
+  CPPFLAGS += -DTHUMB_PRESENT
+  ASFLAGS  += -DTHUMB_PRESENT
+  ifneq ($(ASRC),)
+    # Mixed ARM and THUMB mode.
+    CFLAGS   += -mthumb-interwork
+    CPPFLAGS += -mthumb-interwork
+    ASFLAGS  += -mthumb-interwork
+    LDFLAGS  += -mthumb-interwork
+  else
+    # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
+    CFLAGS   += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
+    CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
+    ASFLAGS  += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
+    LDFLAGS  += -mno-thumb-interwork -mthumb
+  endif
+else
+  # Pure ARM mode
+  CFLAGS   += -mno-thumb-interwork
+  CPPFLAGS += -mno-thumb-interwork
+  ASFLAGS  += -mno-thumb-interwork
+  LDFLAGS  += -mno-thumb-interwork
+endif
+
+# Generate dependency information
+CFLAGS   += -MD -MP -MF .dep/$(@F).d
+CPPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+# Paths where to search for sources
+VPATH     = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK
+
+MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | $(BUILDDIR)
+
+$(BUILDDIR) $(OBJDIR) $(LSTDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+	@echo Compiler Options
+	@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+	@echo
+endif
+	mkdir -p $(OBJDIR)
+	mkdir -p $(LSTDIR)
+
+$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+%.elf: $(OBJS) $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+	@echo Linking $@
+	@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(HEX) $< $@
+else
+	@echo Creating $@
+	@$(HEX) $< $@
+endif
+
+%.bin: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(BIN) $< $@
+else
+	@echo Creating $@
+	@$(BIN) $< $@
+endif
+
+%.dmp: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(OD) $(ODFLAGS) $< > $@
+else
+	@echo Creating $@
+	@$(OD) $(ODFLAGS) $< > $@
+	@echo
+	@$(SZ) $<
+	@echo
+	@echo Done
+endif
+
+clean:
+	@echo Cleaning
+	-rm -fR .dep $(BUILDDIR)
+	@echo
+	@echo Done
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
diff --git a/os/common/ports/ARMCMx/compilers/GCC/vectors.c b/os/common/ports/ARMCMx/compilers/GCC/vectors.c
new file mode 100644
index 000000000..252071854
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/vectors.c
@@ -0,0 +1,653 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/GCC/vectors.c
+ * @brief   Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "cmparams.h"
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+/**
+ * @brief   Type of an IRQ vector.
+ */
+typedef void  (*irq_vector_t)(void);
+
+/**
+ * @brief   Type of a structure representing the whole vectors table.
+ */
+typedef struct {
+  uint32_t      *init_stack;
+  irq_vector_t  reset_handler;
+  irq_vector_t  nmi_handler;
+  irq_vector_t  hardfault_handler;
+  irq_vector_t  memmanage_handler;
+  irq_vector_t  busfault_handler;
+  irq_vector_t  usagefault_handler;
+  irq_vector_t  vector1c;
+  irq_vector_t  vector20;
+  irq_vector_t  vector24;
+  irq_vector_t  vector28;
+  irq_vector_t  svc_handler;
+  irq_vector_t  debugmonitor_handler;
+  irq_vector_t  vector34;
+  irq_vector_t  pendsv_handler;
+  irq_vector_t  systick_handler;
+  irq_vector_t  vectors[CORTEX_NUM_VECTORS];
+} vectors_t;
+
+/**
+ * @brief   Unhandled exceptions handler.
+ * @details Any undefined exception vector points to this function by default.
+ *          This function simply stops the system into an infinite loop.
+ *
+ * @notapi
+ */
+void _unhandled_exception(void) {
+
+  while (true)
+    ;
+}
+
+#if !defined(__DOXYGEN__)
+extern uint32_t __main_stack_end__;
+void Reset_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void NMI_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void HardFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void MemManage_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void BusFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void UsageFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
+void SVC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void DebugMon_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
+void PendSV_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void SysTick_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
+#if CORTEX_NUM_VECTORS > 4
+void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 8
+void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 12
+void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 16
+void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 20
+void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 24
+void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 28
+void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 32
+void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 36
+void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 40
+void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 44
+void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 48
+void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 52
+void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 56
+void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 60
+void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 64
+void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 68
+void Vector150(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector154(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector158(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector15C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 72
+void Vector160(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector164(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector168(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector16C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 76
+void Vector170(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector174(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 80
+void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector184(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector188(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector18C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 84
+void Vector190(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector194(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector198(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector19C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 88
+void Vector1A0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1A4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1A8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1AC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 92
+void Vector1B0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1B4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1B8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1BC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 96
+void Vector1C0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1C4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1C8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1CC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 100
+void Vector1D0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1D4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1D8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1DC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 104
+void Vector1E0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1E4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1E8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1EC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 108
+void Vector1F0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1F4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1F8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1FC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 112
+void Vector200(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector204(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector208(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector20C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 116
+void Vector210(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector214(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector218(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector21C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 120
+void Vector220(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector224(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector228(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector22C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 124
+void Vector230(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector234(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector238(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector23C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 128
+void Vector240(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector244(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector248(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector24C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 132
+void Vector250(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector254(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector258(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector25C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 136
+void Vector260(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector264(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector268(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector26C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 140
+void Vector270(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector274(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector278(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector27C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 144
+void Vector280(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector284(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector288(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector28C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 148
+void Vector290(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector294(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector298(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector29C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 152
+void Vector2A0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2A4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2A8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2AC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 156
+void Vector2B0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2B4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2B8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2BC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 160
+void Vector2C0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2C4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2C8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2CC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 164
+void Vector2D0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2D4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2D8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2DC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 168
+void Vector2E0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2E4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2E8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2EC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 172
+void Vector2F0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2F4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2F8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2FC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 176
+void Vector300(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector304(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector308(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector30C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 180
+void Vector310(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector314(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector318(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector31C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 184
+void Vector320(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector324(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector328(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector32C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 188
+void Vector330(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector334(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector338(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector33C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 192
+void Vector340(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector344(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector348(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector34C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 196
+void Vector350(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector354(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector358(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector35C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 200
+void Vector360(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector364(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector368(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector36C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 204
+void Vector370(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector374(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector378(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector37C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 208
+void Vector380(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector384(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector388(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector38C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 212
+void Vector390(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector394(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector398(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector39C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 216
+void Vector3A0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3A4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3A8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3AC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 220
+void Vector3B0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3B4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3B8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3BC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 224
+void Vector3C0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3C4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3C8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3CC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 228
+void Vector3D0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3D4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3D8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3DC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 232
+void Vector3E0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3E4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3E8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3EC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 236
+void Vector3F0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3F4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3F8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3FC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#endif /* !defined(__DOXYGEN__) */
+
+/**
+ * @brief   STM32 vectors table.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__ ((used, section("vectors")))
+#endif
+vectors_t _vectors = {
+  &__main_stack_end__,Reset_Handler,      NMI_Handler,        HardFault_Handler,
+  MemManage_Handler,  BusFault_Handler,   UsageFault_Handler, Vector1C,
+  Vector20,           Vector24,           Vector28,           SVC_Handler,
+  DebugMon_Handler,   Vector34,           PendSV_Handler,     SysTick_Handler,
+  {
+    Vector40,           Vector44,           Vector48,           Vector4C,
+#if CORTEX_NUM_VECTORS > 4
+    Vector50,           Vector54,           Vector58,           Vector5C,
+#endif
+#if CORTEX_NUM_VECTORS > 8
+    Vector60,           Vector64,           Vector68,           Vector6C,
+#endif
+#if CORTEX_NUM_VECTORS > 12
+    Vector70,           Vector74,           Vector78,           Vector7C,
+#endif
+#if CORTEX_NUM_VECTORS > 16
+    Vector80,           Vector84,           Vector88,           Vector8C,
+#endif
+#if CORTEX_NUM_VECTORS > 20
+    Vector90,           Vector94,           Vector98,           Vector9C,
+#endif
+#if CORTEX_NUM_VECTORS > 24
+    VectorA0,           VectorA4,           VectorA8,           VectorAC,
+#endif
+#if CORTEX_NUM_VECTORS > 28
+    VectorB0,           VectorB4,           VectorB8,           VectorBC,
+#endif
+#if CORTEX_NUM_VECTORS > 32
+    VectorC0,           VectorC4,           VectorC8,           VectorCC,
+#endif
+#if CORTEX_NUM_VECTORS > 36
+    VectorD0,           VectorD4,           VectorD8,           VectorDC,
+#endif
+#if CORTEX_NUM_VECTORS > 40
+    VectorE0,           VectorE4,           VectorE8,           VectorEC,
+#endif
+#if CORTEX_NUM_VECTORS > 44
+    VectorF0,           VectorF4,           VectorF8,           VectorFC,
+#endif
+#if CORTEX_NUM_VECTORS > 48
+    Vector100,          Vector104,          Vector108,          Vector10C,
+#endif
+#if CORTEX_NUM_VECTORS > 52
+    Vector110,          Vector114,          Vector118,          Vector11C,
+#endif
+#if CORTEX_NUM_VECTORS > 56
+    Vector120,          Vector124,          Vector128,          Vector12C,
+#endif
+#if CORTEX_NUM_VECTORS > 60
+    Vector130,          Vector134,          Vector138,          Vector13C,
+#endif
+#if CORTEX_NUM_VECTORS > 64
+    Vector140,          Vector144,          Vector148,          Vector14C,
+#endif
+#if CORTEX_NUM_VECTORS > 68
+    Vector150,          Vector154,          Vector158,          Vector15C,
+#endif
+#if CORTEX_NUM_VECTORS > 72
+    Vector160,          Vector164,          Vector168,          Vector16C,
+#endif
+#if CORTEX_NUM_VECTORS > 76
+    Vector170,          Vector174,          Vector178,          Vector17C,
+#endif
+#if CORTEX_NUM_VECTORS > 80
+    Vector180,          Vector184,          Vector188,          Vector17C,
+#endif
+#if CORTEX_NUM_VECTORS > 84
+    Vector190,          Vector194,          Vector198,          Vector19C,
+#endif
+#if CORTEX_NUM_VECTORS > 88
+    Vector1A0,          Vector1A4,          Vector1A8,          Vector1AC,
+#endif
+#if CORTEX_NUM_VECTORS > 92
+    Vector1B0,          Vector1B4,          Vector1B8,          Vector1BC,
+#endif
+#if CORTEX_NUM_VECTORS > 96
+    Vector1C0,          Vector1C4,          Vector1C8,          Vector1CC,
+#endif
+#if CORTEX_NUM_VECTORS > 100
+    Vector1D0,          Vector1D4,          Vector1D8,          Vector1DC,
+#endif
+#if CORTEX_NUM_VECTORS > 104
+    Vector1E0,          Vector1E4,          Vector1E8,          Vector1EC,
+#endif
+#if CORTEX_NUM_VECTORS > 108
+    Vector1F0,          Vector1F4,          Vector1F8,          Vector1FC,
+#endif
+#if CORTEX_NUM_VECTORS > 112
+    Vector200,          Vector204,          Vector208,          Vector20C,
+#endif
+#if CORTEX_NUM_VECTORS > 116
+    Vector210,          Vector214,          Vector218,          Vector21C,
+#endif
+#if CORTEX_NUM_VECTORS > 120
+    Vector220,          Vector224,          Vector228,          Vector22C,
+#endif
+#if CORTEX_NUM_VECTORS > 124
+    Vector230,          Vector234,          Vector238,          Vector23C,
+#endif
+#if CORTEX_NUM_VECTORS > 128
+    Vector240,          Vector244,          Vector248,          Vector24C,
+#endif
+#if CORTEX_NUM_VECTORS > 132
+    Vector250,          Vector254,          Vector258,          Vector25C,
+#endif
+#if CORTEX_NUM_VECTORS > 136
+    Vector260,          Vector264,          Vector268,          Vector26C,
+#endif
+#if CORTEX_NUM_VECTORS > 140
+    Vector270,          Vector274,          Vector278,          Vector27C,
+#endif
+#if CORTEX_NUM_VECTORS > 144
+    Vector280,          Vector284,          Vector288,          Vector28C,
+#endif
+#if CORTEX_NUM_VECTORS > 148
+    Vector290,          Vector294,          Vector298,          Vector29C,
+#endif
+#if CORTEX_NUM_VECTORS > 152
+    Vector2A0,          Vector2A4,          Vector2A8,          Vector2AC,
+#endif
+#if CORTEX_NUM_VECTORS > 156
+    Vector2B0,          Vector2B4,          Vector2B8,          Vector2BC,
+#endif
+#if CORTEX_NUM_VECTORS > 160
+    Vector2C0,          Vector2C4,          Vector2C8,          Vector2CC,
+#endif
+#if CORTEX_NUM_VECTORS > 164
+    Vector2D0,          Vector2D4,          Vector2D8,          Vector2DC,
+#endif
+#if CORTEX_NUM_VECTORS > 168
+    Vector2E0,          Vector2E4,          Vector2E8,          Vector2EC,
+#endif
+#if CORTEX_NUM_VECTORS > 172
+    Vector2F0,          Vector2F4,          Vector2F8,          Vector2FC,
+#endif
+#if CORTEX_NUM_VECTORS > 176
+    Vector300,          Vector304,          Vector308,          Vector30C,
+#endif
+#if CORTEX_NUM_VECTORS > 180
+    Vector310,          Vector314,          Vector318,          Vector31C,
+#endif
+#if CORTEX_NUM_VECTORS > 184
+    Vector320,          Vector324,          Vector328,          Vector32C,
+#endif
+#if CORTEX_NUM_VECTORS > 188
+    Vector330,          Vector334,          Vector338,          Vector33C,
+#endif
+#if CORTEX_NUM_VECTORS > 192
+    Vector340,          Vector344,          Vector348,          Vector34C,
+#endif
+#if CORTEX_NUM_VECTORS > 196
+    Vector350,          Vector354,          Vector358,          Vector35C,
+#endif
+#if CORTEX_NUM_VECTORS > 200
+    Vector360,          Vector364,          Vector368,          Vector36C,
+#endif
+#if CORTEX_NUM_VECTORS > 204
+    Vector370,          Vector374,          Vector378,          Vector37C,
+#endif
+#if CORTEX_NUM_VECTORS > 208
+    Vector380,          Vector384,          Vector388,          Vector38C,
+#endif
+#if CORTEX_NUM_VECTORS > 212
+    Vector390,          Vector394,          Vector398,          Vector39C,
+#endif
+#if CORTEX_NUM_VECTORS > 216
+    Vector3A0,          Vector3A4,          Vector3A8,          Vector3AC,
+#endif
+#if CORTEX_NUM_VECTORS > 220
+    Vector3B0,          Vector3B4,          Vector3B8,          Vector3BC,
+#endif
+#if CORTEX_NUM_VECTORS > 224
+    Vector3C0,          Vector3C4,          Vector3C8,          Vector3CC,
+#endif
+#if CORTEX_NUM_VECTORS > 228
+    Vector3D0,          Vector3D4,          Vector3D8,          Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+    Vector3E0,          Vector3E4,          Vector3E8,          Vector3EC
+#endif
+#if CORTEX_NUM_VECTORS > 236
+    Vector3F0,          Vector3F4,          Vector3F8,          Vector3FC
+#endif
+  }
+};
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/compilers/IAR/cstartup.s b/os/common/ports/ARMCMx/compilers/IAR/cstartup.s
new file mode 100644
index 000000000..b64f7e2a1
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/IAR/cstartup.s
@@ -0,0 +1,82 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/IAR/cstartup.s
+ * @brief   Generic IAR Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_IAR_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+        MODULE  ?cstartup
+
+CONTROL_MODE_PRIVILEGED SET 0
+CONTROL_MODE_UNPRIVILEGED SET 1
+CONTROL_USE_MSP SET 0
+CONTROL_USE_PSP SET 2
+
+        AAPCS INTERWORK, VFP_COMPATIBLE, ROPI
+        PRESERVE8
+
+        SECTION .intvec:CODE:NOROOT(3)
+
+        SECTION CSTACK:DATA:NOROOT(3)
+        PUBLIC  __main_thread_stack_base__
+__main_thread_stack_base__:
+        PUBLIC  __heap_end__
+__heap_end__:
+
+        SECTION SYSHEAP:DATA:NOROOT(3)
+        PUBLIC  __heap_base__
+__heap_base__:
+
+        PUBLIC  __iar_program_start
+        EXTERN  __vector_table
+        EXTWEAK __iar_init_core
+        EXTWEAK __iar_init_vfp
+        EXTERN  __cmain
+
+        SECTION .text:CODE:REORDER(2)
+        REQUIRE __vector_table
+        THUMB
+__iar_program_start:
+        cpsid   i
+        ldr     r0, =SFE(CSTACK)
+        msr     PSP, r0
+        movs    r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
+        msr     CONTROL, r0
+        isb
+        bl      __early_init
+        bl      __iar_init_core
+        bl      __iar_init_vfp
+        b       __cmain
+
+        PUBWEAK __early_init
+__early_init:
+        bx      lr
+
+        END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/os/common/ports/ARMCMx/compilers/IAR/vectors.s b/os/common/ports/ARMCMx/compilers/IAR/vectors.s
new file mode 100644
index 000000000..133f63217
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/IAR/vectors.s
@@ -0,0 +1,1010 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/IAR/vectors.c
+ * @brief   Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_IAR_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "cmparams.h"
+
+#if !defined(__DOXYGEN__)
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+        MODULE  ?vectors
+
+        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
+        PRESERVE8
+
+        SECTION IRQSTACK:DATA:NOROOT(3)
+        SECTION .intvec:CODE:NOROOT(3)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+
+        DATA
+
+__vector_table:
+        DCD     SFE(IRQSTACK)
+        DCD     __iar_program_start
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+        DCD     Vector1C
+        DCD     Vector20
+        DCD     Vector24
+        DCD     Vector28
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     Vector34
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+        DCD     Vector40
+        DCD     Vector44
+        DCD     Vector48
+        DCD     Vector4C
+        DCD     Vector50
+        DCD     Vector54
+        DCD     Vector58
+        DCD     Vector5C
+#if CORTEX_NUM_VECTORS > 8
+        DCD     Vector60
+        DCD     Vector64
+        DCD     Vector68
+        DCD     Vector6C
+        DCD     Vector70
+        DCD     Vector74
+        DCD     Vector78
+        DCD     Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+        DCD     Vector80
+        DCD     Vector84
+        DCD     Vector88
+        DCD     Vector8C
+        DCD     Vector90
+        DCD     Vector94
+        DCD     Vector98
+        DCD     Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+        DCD     VectorA0
+        DCD     VectorA4
+        DCD     VectorA8
+        DCD     VectorAC
+        DCD     VectorB0
+        DCD     VectorB4
+        DCD     VectorB8
+        DCD     VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+        DCD     VectorC0
+        DCD     VectorC4
+        DCD     VectorC8
+        DCD     VectorCC
+        DCD     VectorD0
+        DCD     VectorD4
+        DCD     VectorD8
+        DCD     VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+        DCD     VectorE0
+        DCD     VectorE4
+        DCD     VectorE8
+        DCD     VectorEC
+        DCD     VectorF0
+        DCD     VectorF4
+        DCD     VectorF8
+        DCD     VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+        DCD     Vector100
+        DCD     Vector104
+        DCD     Vector108
+        DCD     Vector10C
+        DCD     Vector110
+        DCD     Vector114
+        DCD     Vector118
+        DCD     Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+        DCD     Vector120
+        DCD     Vector124
+        DCD     Vector128
+        DCD     Vector12C
+        DCD     Vector130
+        DCD     Vector134
+        DCD     Vector138
+        DCD     Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+        DCD     Vector140
+        DCD     Vector144
+        DCD     Vector148
+        DCD     Vector14C
+        DCD     Vector150
+        DCD     Vector154
+        DCD     Vector158
+        DCD     Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+        DCD     Vector160
+        DCD     Vector164
+        DCD     Vector168
+        DCD     Vector16C
+        DCD     Vector170
+        DCD     Vector174
+        DCD     Vector178
+        DCD     Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+        DCD     Vector180
+        DCD     Vector184
+        DCD     Vector188
+        DCD     Vector18C
+        DCD     Vector190
+        DCD     Vector194
+        DCD     Vector198
+        DCD     Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+        DCD     Vector1A0
+        DCD     Vector1A4
+        DCD     Vector1A8
+        DCD     Vector1AC
+        DCD     Vector1B0
+        DCD     Vector1B4
+        DCD     Vector1B8
+        DCD     Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+        DCD     Vector1C0
+        DCD     Vector1C4
+        DCD     Vector1C8
+        DCD     Vector1CC
+        DCD     Vector1D0
+        DCD     Vector1D4
+        DCD     Vector1D8
+        DCD     Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+        DCD     Vector1E0
+        DCD     Vector1E4
+        DCD     Vector1E8
+        DCD     Vector1EC
+        DCD     Vector1F0
+        DCD     Vector1F4
+        DCD     Vector1F8
+        DCD     Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+        DCD     Vector200
+        DCD     Vector204
+        DCD     Vector208
+        DCD     Vector20C
+        DCD     Vector210
+        DCD     Vector214
+        DCD     Vector218
+        DCD     Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+        DCD     Vector220
+        DCD     Vector224
+        DCD     Vector228
+        DCD     Vector22C
+        DCD     Vector230
+        DCD     Vector234
+        DCD     Vector238
+        DCD     Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+        DCD     Vector240
+        DCD     Vector244
+        DCD     Vector248
+        DCD     Vector24C
+        DCD     Vector250
+        DCD     Vector254
+        DCD     Vector258
+        DCD     Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+        DCD     Vector260
+        DCD     Vector264
+        DCD     Vector268
+        DCD     Vector26C
+        DCD     Vector270
+        DCD     Vector274
+        DCD     Vector278
+        DCD     Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+        DCD     Vector280
+        DCD     Vector284
+        DCD     Vector288
+        DCD     Vector28C
+        DCD     Vector290
+        DCD     Vector294
+        DCD     Vector298
+        DCD     Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+        DCD     Vector2A0
+        DCD     Vector2A4
+        DCD     Vector2A8
+        DCD     Vector2AC
+        DCD     Vector2B0
+        DCD     Vector2B4
+        DCD     Vector2B8
+        DCD     Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+        DCD     Vector2C0
+        DCD     Vector2C4
+        DCD     Vector2C8
+        DCD     Vector2CC
+        DCD     Vector2D0
+        DCD     Vector2D4
+        DCD     Vector2D8
+        DCD     Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+        DCD     Vector2E0
+        DCD     Vector2E4
+        DCD     Vector2E8
+        DCD     Vector2EC
+        DCD     Vector2F0
+        DCD     Vector2F4
+        DCD     Vector2F8
+        DCD     Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+        DCD     Vector300
+        DCD     Vector304
+        DCD     Vector308
+        DCD     Vector30C
+        DCD     Vector310
+        DCD     Vector314
+        DCD     Vector318
+        DCD     Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+        DCD     Vector320
+        DCD     Vector324
+        DCD     Vector328
+        DCD     Vector32C
+        DCD     Vector330
+        DCD     Vector334
+        DCD     Vector338
+        DCD     Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+        DCD     Vector340
+        DCD     Vector344
+        DCD     Vector348
+        DCD     Vector34C
+        DCD     Vector350
+        DCD     Vector354
+        DCD     Vector358
+        DCD     Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+        DCD     Vector360
+        DCD     Vector364
+        DCD     Vector368
+        DCD     Vector36C
+        DCD     Vector370
+        DCD     Vector374
+        DCD     Vector378
+        DCD     Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+        DCD     Vector380
+        DCD     Vector384
+        DCD     Vector388
+        DCD     Vector38C
+        DCD     Vector390
+        DCD     Vector394
+        DCD     Vector398
+        DCD     Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+        DCD     Vector3A0
+        DCD     Vector3A4
+        DCD     Vector3A8
+        DCD     Vector3AC
+        DCD     Vector3B0
+        DCD     Vector3B4
+        DCD     Vector3B8
+        DCD     Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+        DCD     Vector3C0
+        DCD     Vector3C4
+        DCD     Vector3C8
+        DCD     Vector3CC
+        DCD     Vector3D0
+        DCD     Vector3D4
+        DCD     Vector3D8
+        DCD     Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+        DCD     Vector3E0
+        DCD     Vector3E4
+        DCD     Vector3E8
+        DCD     Vector3EC
+        DCD     Vector3F0
+        DCD     Vector3F4
+        DCD     Vector3F8
+        DCD     Vector3FC
+#endif
+
+/*
+ * Default interrupt handlers.
+ */
+        PUBWEAK NMI_Handler
+        PUBWEAK HardFault_Handler
+        PUBWEAK MemManage_Handler
+        PUBWEAK BusFault_Handler
+        PUBWEAK UsageFault_Handler
+        PUBWEAK Vector1C
+        PUBWEAK Vector20
+        PUBWEAK Vector24
+        PUBWEAK Vector28
+        PUBWEAK SVC_Handler
+        PUBWEAK DebugMon_Handler
+        PUBWEAK Vector34
+        PUBWEAK PendSV_Handler
+        PUBWEAK SysTick_Handler
+        PUBWEAK Vector40
+        PUBWEAK Vector44
+        PUBWEAK Vector48
+        PUBWEAK Vector4C
+        PUBWEAK Vector50
+        PUBWEAK Vector54
+        PUBWEAK Vector58
+        PUBWEAK Vector5C
+#if CORTEX_NUM_VECTORS > 8
+        PUBWEAK Vector60
+        PUBWEAK Vector64
+        PUBWEAK Vector68
+        PUBWEAK Vector6C
+        PUBWEAK Vector70
+        PUBWEAK Vector74
+        PUBWEAK Vector78
+        PUBWEAK Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+        PUBWEAK Vector80
+        PUBWEAK Vector84
+        PUBWEAK Vector88
+        PUBWEAK Vector8C
+        PUBWEAK Vector90
+        PUBWEAK Vector94
+        PUBWEAK Vector98
+        PUBWEAK Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+        PUBWEAK VectorA0
+        PUBWEAK VectorA4
+        PUBWEAK VectorA8
+        PUBWEAK VectorAC
+        PUBWEAK VectorB0
+        PUBWEAK VectorB4
+        PUBWEAK VectorB8
+        PUBWEAK VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+        PUBWEAK VectorC0
+        PUBWEAK VectorC4
+        PUBWEAK VectorC8
+        PUBWEAK VectorCC
+        PUBWEAK VectorD0
+        PUBWEAK VectorD4
+        PUBWEAK VectorD8
+        PUBWEAK VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+        PUBWEAK VectorE0
+        PUBWEAK VectorE4
+        PUBWEAK VectorE8
+        PUBWEAK VectorEC
+        PUBWEAK VectorF0
+        PUBWEAK VectorF4
+        PUBWEAK VectorF8
+        PUBWEAK VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+        PUBWEAK Vector100
+        PUBWEAK Vector104
+        PUBWEAK Vector108
+        PUBWEAK Vector10C
+        PUBWEAK Vector110
+        PUBWEAK Vector114
+        PUBWEAK Vector118
+        PUBWEAK Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+        PUBWEAK Vector120
+        PUBWEAK Vector124
+        PUBWEAK Vector128
+        PUBWEAK Vector12C
+        PUBWEAK Vector130
+        PUBWEAK Vector134
+        PUBWEAK Vector138
+        PUBWEAK Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+        PUBWEAK Vector140
+        PUBWEAK Vector144
+        PUBWEAK Vector148
+        PUBWEAK Vector14C
+        PUBWEAK Vector150
+        PUBWEAK Vector154
+        PUBWEAK Vector158
+        PUBWEAK Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+        PUBWEAK Vector160
+        PUBWEAK Vector164
+        PUBWEAK Vector168
+        PUBWEAK Vector16C
+        PUBWEAK Vector170
+        PUBWEAK Vector174
+        PUBWEAK Vector178
+        PUBWEAK Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+        PUBWEAK Vector180
+        PUBWEAK Vector184
+        PUBWEAK Vector188
+        PUBWEAK Vector18C
+        PUBWEAK Vector190
+        PUBWEAK Vector194
+        PUBWEAK Vector198
+        PUBWEAK Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+        PUBWEAK Vector1A0
+        PUBWEAK Vector1A4
+        PUBWEAK Vector1A8
+        PUBWEAK Vector1AC
+        PUBWEAK Vector1B0
+        PUBWEAK Vector1B4
+        PUBWEAK Vector1B8
+        PUBWEAK Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+        PUBWEAK Vector1C0
+        PUBWEAK Vector1C4
+        PUBWEAK Vector1C8
+        PUBWEAK Vector1CC
+        PUBWEAK Vector1D0
+        PUBWEAK Vector1D4
+        PUBWEAK Vector1D8
+        PUBWEAK Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+        PUBWEAK Vector1E0
+        PUBWEAK Vector1E4
+        PUBWEAK Vector1E8
+        PUBWEAK Vector1EC
+        PUBWEAK Vector1F0
+        PUBWEAK Vector1F4
+        PUBWEAK Vector1F8
+        PUBWEAK Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+        PUBWEAK Vector200
+        PUBWEAK Vector204
+        PUBWEAK Vector208
+        PUBWEAK Vector20C
+        PUBWEAK Vector210
+        PUBWEAK Vector214
+        PUBWEAK Vector218
+        PUBWEAK Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+        PUBWEAK Vector220
+        PUBWEAK Vector224
+        PUBWEAK Vector228
+        PUBWEAK Vector22C
+        PUBWEAK Vector230
+        PUBWEAK Vector234
+        PUBWEAK Vector238
+        PUBWEAK Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+        PUBWEAK Vector240
+        PUBWEAK Vector244
+        PUBWEAK Vector248
+        PUBWEAK Vector24C
+        PUBWEAK Vector250
+        PUBWEAK Vector254
+        PUBWEAK Vector258
+        PUBWEAK Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+        PUBWEAK Vector260
+        PUBWEAK Vector264
+        PUBWEAK Vector268
+        PUBWEAK Vector26C
+        PUBWEAK Vector270
+        PUBWEAK Vector274
+        PUBWEAK Vector278
+        PUBWEAK Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+        PUBWEAK Vector280
+        PUBWEAK Vector284
+        PUBWEAK Vector288
+        PUBWEAK Vector28C
+        PUBWEAK Vector290
+        PUBWEAK Vector294
+        PUBWEAK Vector298
+        PUBWEAK Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+        PUBWEAK Vector2A0
+        PUBWEAK Vector2A4
+        PUBWEAK Vector2A8
+        PUBWEAK Vector2AC
+        PUBWEAK Vector2B0
+        PUBWEAK Vector2B4
+        PUBWEAK Vector2B8
+        PUBWEAK Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+        PUBWEAK Vector2C0
+        PUBWEAK Vector2C4
+        PUBWEAK Vector2C8
+        PUBWEAK Vector2CC
+        PUBWEAK Vector2D0
+        PUBWEAK Vector2D4
+        PUBWEAK Vector2D8
+        PUBWEAK Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+        PUBWEAK Vector2E0
+        PUBWEAK Vector2E4
+        PUBWEAK Vector2E8
+        PUBWEAK Vector2EC
+        PUBWEAK Vector2F0
+        PUBWEAK Vector2F4
+        PUBWEAK Vector2F8
+        PUBWEAK Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+        PUBWEAK Vector300
+        PUBWEAK Vector304
+        PUBWEAK Vector308
+        PUBWEAK Vector30C
+        PUBWEAK Vector310
+        PUBWEAK Vector314
+        PUBWEAK Vector318
+        PUBWEAK Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+        PUBWEAK Vector320
+        PUBWEAK Vector324
+        PUBWEAK Vector328
+        PUBWEAK Vector32C
+        PUBWEAK Vector330
+        PUBWEAK Vector334
+        PUBWEAK Vector338
+        PUBWEAK Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+        PUBWEAK Vector340
+        PUBWEAK Vector344
+        PUBWEAK Vector348
+        PUBWEAK Vector34C
+        PUBWEAK Vector350
+        PUBWEAK Vector354
+        PUBWEAK Vector358
+        PUBWEAK Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+        PUBWEAK Vector360
+        PUBWEAK Vector364
+        PUBWEAK Vector368
+        PUBWEAK Vector36C
+        PUBWEAK Vector370
+        PUBWEAK Vector374
+        PUBWEAK Vector378
+        PUBWEAK Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+        PUBWEAK Vector380
+        PUBWEAK Vector384
+        PUBWEAK Vector388
+        PUBWEAK Vector38C
+        PUBWEAK Vector390
+        PUBWEAK Vector394
+        PUBWEAK Vector398
+        PUBWEAK Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+        PUBWEAK Vector3A0
+        PUBWEAK Vector3A4
+        PUBWEAK Vector3A8
+        PUBWEAK Vector3AC
+        PUBWEAK Vector3B0
+        PUBWEAK Vector3B4
+        PUBWEAK Vector3B8
+        PUBWEAK Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+        PUBWEAK Vector3C0
+        PUBWEAK Vector3C4
+        PUBWEAK Vector3C8
+        PUBWEAK Vector3CC
+        PUBWEAK Vector3D0
+        PUBWEAK Vector3D4
+        PUBWEAK Vector3D8
+        PUBWEAK Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+        PUBWEAK Vector3E0
+        PUBWEAK Vector3E4
+        PUBWEAK Vector3E8
+        PUBWEAK Vector3EC
+        PUBWEAK Vector3F0
+        PUBWEAK Vector3F4
+        PUBWEAK Vector3F8
+        PUBWEAK Vector3FC
+#endif
+        PUBLIC  _unhandled_exception
+
+        SECTION .text:CODE:REORDER(1)
+        THUMB
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+Vector1C
+Vector20
+Vector24
+Vector28
+SVC_Handler
+DebugMon_Handler
+Vector34
+PendSV_Handler
+SysTick_Handler
+Vector40
+Vector44
+Vector48
+Vector4C
+Vector50
+Vector54
+Vector58
+Vector5C
+#if CORTEX_NUM_VECTORS > 8
+Vector60
+Vector64
+Vector68
+Vector6C
+Vector70
+Vector74
+Vector78
+Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+Vector80
+Vector84
+Vector88
+Vector8C
+Vector90
+Vector94
+Vector98
+Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+VectorA0
+VectorA4
+VectorA8
+VectorAC
+VectorB0
+VectorB4
+VectorB8
+VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+VectorC0
+VectorC4
+VectorC8
+VectorCC
+VectorD0
+VectorD4
+VectorD8
+VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+VectorE0
+VectorE4
+VectorE8
+VectorEC
+VectorF0
+VectorF4
+VectorF8
+VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+Vector100
+Vector104
+Vector108
+Vector10C
+Vector110
+Vector114
+Vector118
+Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+Vector120
+Vector124
+Vector128
+Vector12C
+Vector130
+Vector134
+Vector138
+Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+Vector140
+Vector144
+Vector148
+Vector14C
+Vector150
+Vector154
+Vector158
+Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+Vector160
+Vector164
+Vector168
+Vector16C
+Vector170
+Vector174
+Vector178
+Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+Vector180
+Vector184
+Vector188
+Vector18C
+Vector190
+Vector194
+Vector198
+Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+Vector1A0
+Vector1A4
+Vector1A8
+Vector1AC
+Vector1B0
+Vector1B4
+Vector1B8
+Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+Vector1C0
+Vector1C4
+Vector1C8
+Vector1CC
+Vector1D0
+Vector1D4
+Vector1D8
+Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+Vector1E0
+Vector1E4
+Vector1E8
+Vector1EC
+Vector1F0
+Vector1F4
+Vector1F8
+Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+Vector200
+Vector204
+Vector208
+Vector20C
+Vector210
+Vector214
+Vector218
+Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+Vector220
+Vector224
+Vector228
+Vector22C
+Vector230
+Vector234
+Vector238
+Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+Vector240
+Vector244
+Vector248
+Vector24C
+Vector250
+Vector254
+Vector258
+Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+Vector260
+Vector264
+Vector268
+Vector26C
+Vector270
+Vector274
+Vector278
+Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+Vector280
+Vector284
+Vector288
+Vector28C
+Vector290
+Vector294
+Vector298
+Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+Vector2A0
+Vector2A4
+Vector2A8
+Vector2AC
+Vector2B0
+Vector2B4
+Vector2B8
+Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+Vector2C0
+Vector2C4
+Vector2C8
+Vector2CC
+Vector2D0
+Vector2D4
+Vector2D8
+Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+Vector2E0
+Vector2E4
+Vector2E8
+Vector2EC
+Vector2F0
+Vector2F4
+Vector2F8
+Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+Vector300
+Vector304
+Vector308
+Vector30C
+Vector310
+Vector314
+Vector318
+Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+Vector320
+Vector324
+Vector328
+Vector32C
+Vector330
+Vector334
+Vector338
+Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+Vector340
+Vector344
+Vector348
+Vector34C
+Vector350
+Vector354
+Vector358
+Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+Vector360
+Vector364
+Vector368
+Vector36C
+Vector370
+Vector374
+Vector378
+Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+Vector380
+Vector384
+Vector388
+Vector38C
+Vector390
+Vector394
+Vector398
+Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+Vector3A0
+Vector3A4
+Vector3A8
+Vector3AC
+Vector3B0
+Vector3B4
+Vector3B8
+Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+Vector3C0
+Vector3C4
+Vector3C8
+Vector3CC
+Vector3D0
+Vector3D4
+Vector3D8
+Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+Vector3E0
+Vector3E4
+Vector3E8
+Vector3EC
+Vector3F0
+Vector3F4
+Vector3F8
+Vector3FC
+#endif
+_unhandled_exception
+        b       _unhandled_exception
+
+        END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/os/common/ports/ARMCMx/compilers/RVCT/cstartup.s b/os/common/ports/ARMCMx/compilers/RVCT/cstartup.s
new file mode 100644
index 000000000..aa97ca5ab
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/RVCT/cstartup.s
@@ -0,0 +1,135 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/RVCT/cstartup.s
+ * @brief   Generic RVCT Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_RVCT_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+;/* <<< Use Configuration Wizard in Context Menu >>> */
+
+;// <h> Main Stack Configuration (IRQ Stack)
+;//   <o> Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// </h>
+main_stack_size EQU     0x00000400
+
+;// <h> Process Stack Configuration
+;//   <o> Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// </h>
+proc_stack_size EQU     0x00000400
+
+;// <h> C-runtime heap size
+;//   <o> C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// </h>
+heap_size       EQU     0x00000400
+
+                AREA    MSTACK, NOINIT, READWRITE, ALIGN=3
+main_stack_mem  SPACE   main_stack_size
+                EXPORT  __initial_msp
+__initial_msp
+
+                AREA    CSTACK, NOINIT, READWRITE, ALIGN=3
+__main_thread_stack_base__
+                EXPORT  __main_thread_stack_base__
+proc_stack_mem  SPACE   proc_stack_size
+                EXPORT  __initial_sp
+__initial_sp
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   heap_size
+__heap_limit
+
+CONTROL_MODE_PRIVILEGED     EQU     0
+CONTROL_MODE_UNPRIVILEGED   EQU     1
+CONTROL_USE_MSP             EQU     0
+CONTROL_USE_PSP             EQU     2
+
+                PRESERVE8
+                THUMB
+
+                AREA    |.text|, CODE, READONLY
+
+/*
+ * Reset handler.
+ */
+                IMPORT  __main
+                EXPORT  Reset_Handler
+Reset_Handler   PROC
+                cpsid   i
+                ldr     r0, =__initial_sp
+                msr     PSP, r0
+                movs    r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP
+                msr     CONTROL, r0
+                isb
+                bl      __early_init
+
+                IF      {CPU} = "Cortex-M4.fp"
+                LDR     R0, =0xE000ED88           ; Enable CP10,CP11
+                LDR     R1, [R0]
+                ORR     R1, R1, #(0xF << 20)
+                STR     R1, [R0]
+                ENDIF
+
+                ldr     r0, =__main
+                bx      r0
+                ENDP
+
+__early_init    PROC
+                EXPORT  __early_init            [WEAK]
+                bx      lr
+                ENDP
+
+                ALIGN
+
+/*
+ * User Initial Stack & Heap.
+ */
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+                ldr     r0, =Heap_Mem
+                ldr     r1, =(proc_stack_mem + proc_stack_size)
+                ldr     r2, =(Heap_Mem + heap_size)
+                ldr     r3, =proc_stack_mem
+                bx      lr
+
+                ALIGN
+
+                ENDIF
+
+                END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/os/common/ports/ARMCMx/compilers/RVCT/vectors.s b/os/common/ports/ARMCMx/compilers/RVCT/vectors.s
new file mode 100644
index 000000000..03e4e6196
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/RVCT/vectors.s
@@ -0,0 +1,1006 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/RVCT/vectors.c
+ * @brief   Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_RVCT_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "cmparams.h"
+
+#if !defined(__DOXYGEN__)
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+                PRESERVE8
+
+                AREA    RESET, DATA, READONLY
+
+                IMPORT  __initial_msp
+                IMPORT  Reset_Handler
+                EXPORT  __Vectors
+
+__Vectors
+                DCD     __initial_msp
+                DCD     Reset_Handler
+                DCD     NMI_Handler
+                DCD     HardFault_Handler
+                DCD     MemManage_Handler
+                DCD     BusFault_Handler
+                DCD     UsageFault_Handler
+                DCD     Vector1C
+                DCD     Vector20
+                DCD     Vector24
+                DCD     Vector28
+                DCD     SVC_Handler
+                DCD     DebugMon_Handler
+                DCD     Vector34
+                DCD     PendSV_Handler
+                DCD     SysTick_Handler
+                DCD     Vector40
+                DCD     Vector44
+                DCD     Vector48
+                DCD     Vector4C
+                DCD     Vector50
+                DCD     Vector54
+                DCD     Vector58
+                DCD     Vector5C
+#if CORTEX_NUM_VECTORS > 8
+                DCD     Vector60
+                DCD     Vector64
+                DCD     Vector68
+                DCD     Vector6C
+                DCD     Vector70
+                DCD     Vector74
+                DCD     Vector78
+                DCD     Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+                DCD     Vector80
+                DCD     Vector84
+                DCD     Vector88
+                DCD     Vector8C
+                DCD     Vector90
+                DCD     Vector94
+                DCD     Vector98
+                DCD     Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+                DCD     VectorA0
+                DCD     VectorA4
+                DCD     VectorA8
+                DCD     VectorAC
+                DCD     VectorB0
+                DCD     VectorB4
+                DCD     VectorB8
+                DCD     VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+                DCD     VectorC0
+                DCD     VectorC4
+                DCD     VectorC8
+                DCD     VectorCC
+                DCD     VectorD0
+                DCD     VectorD4
+                DCD     VectorD8
+                DCD     VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+                DCD     VectorE0
+                DCD     VectorE4
+                DCD     VectorE8
+                DCD     VectorEC
+                DCD     VectorF0
+                DCD     VectorF4
+                DCD     VectorF8
+                DCD     VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+                DCD     Vector100
+                DCD     Vector104
+                DCD     Vector108
+                DCD     Vector10C
+                DCD     Vector110
+                DCD     Vector114
+                DCD     Vector118
+                DCD     Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+                DCD     Vector120
+                DCD     Vector124
+                DCD     Vector128
+                DCD     Vector12C
+                DCD     Vector130
+                DCD     Vector134
+                DCD     Vector138
+                DCD     Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+                DCD     Vector140
+                DCD     Vector144
+                DCD     Vector148
+                DCD     Vector14C
+                DCD     Vector150
+                DCD     Vector154
+                DCD     Vector158
+                DCD     Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+                DCD     Vector160
+                DCD     Vector164
+                DCD     Vector168
+                DCD     Vector16C
+                DCD     Vector170
+                DCD     Vector174
+                DCD     Vector178
+                DCD     Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+                DCD     Vector180
+                DCD     Vector184
+                DCD     Vector188
+                DCD     Vector18C
+                DCD     Vector190
+                DCD     Vector194
+                DCD     Vector198
+                DCD     Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+                DCD     Vector1A0
+                DCD     Vector1A4
+                DCD     Vector1A8
+                DCD     Vector1AC
+                DCD     Vector1B0
+                DCD     Vector1B4
+                DCD     Vector1B8
+                DCD     Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+                DCD     Vector1C0
+                DCD     Vector1C4
+                DCD     Vector1C8
+                DCD     Vector1CC
+                DCD     Vector1D0
+                DCD     Vector1D4
+                DCD     Vector1D8
+                DCD     Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+                DCD     Vector1E0
+                DCD     Vector1E4
+                DCD     Vector1E8
+                DCD     Vector1EC
+                DCD     Vector1F0
+                DCD     Vector1F4
+                DCD     Vector1F8
+                DCD     Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+                DCD     Vector200
+                DCD     Vector204
+                DCD     Vector208
+                DCD     Vector20C
+                DCD     Vector210
+                DCD     Vector214
+                DCD     Vector218
+                DCD     Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+                DCD     Vector220
+                DCD     Vector224
+                DCD     Vector228
+                DCD     Vector22C
+                DCD     Vector230
+                DCD     Vector234
+                DCD     Vector238
+                DCD     Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+                DCD     Vector240
+                DCD     Vector244
+                DCD     Vector248
+                DCD     Vector24C
+                DCD     Vector250
+                DCD     Vector254
+                DCD     Vector258
+                DCD     Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+                DCD     Vector260
+                DCD     Vector264
+                DCD     Vector268
+                DCD     Vector26C
+                DCD     Vector270
+                DCD     Vector274
+                DCD     Vector278
+                DCD     Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+                DCD     Vector280
+                DCD     Vector284
+                DCD     Vector288
+                DCD     Vector28C
+                DCD     Vector290
+                DCD     Vector294
+                DCD     Vector298
+                DCD     Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+                DCD     Vector2A0
+                DCD     Vector2A4
+                DCD     Vector2A8
+                DCD     Vector2AC
+                DCD     Vector2B0
+                DCD     Vector2B4
+                DCD     Vector2B8
+                DCD     Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+                DCD     Vector2C0
+                DCD     Vector2C4
+                DCD     Vector2C8
+                DCD     Vector2CC
+                DCD     Vector2D0
+                DCD     Vector2D4
+                DCD     Vector2D8
+                DCD     Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+                DCD     Vector2E0
+                DCD     Vector2E4
+                DCD     Vector2E8
+                DCD     Vector2EC
+                DCD     Vector2F0
+                DCD     Vector2F4
+                DCD     Vector2F8
+                DCD     Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+                DCD     Vector300
+                DCD     Vector304
+                DCD     Vector308
+                DCD     Vector30C
+                DCD     Vector310
+                DCD     Vector314
+                DCD     Vector318
+                DCD     Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+                DCD     Vector320
+                DCD     Vector324
+                DCD     Vector328
+                DCD     Vector32C
+                DCD     Vector330
+                DCD     Vector334
+                DCD     Vector338
+                DCD     Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+                DCD     Vector340
+                DCD     Vector344
+                DCD     Vector348
+                DCD     Vector34C
+                DCD     Vector350
+                DCD     Vector354
+                DCD     Vector358
+                DCD     Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+                DCD     Vector360
+                DCD     Vector364
+                DCD     Vector368
+                DCD     Vector36C
+                DCD     Vector370
+                DCD     Vector374
+                DCD     Vector378
+                DCD     Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+                DCD     Vector380
+                DCD     Vector384
+                DCD     Vector388
+                DCD     Vector38C
+                DCD     Vector390
+                DCD     Vector394
+                DCD     Vector398
+                DCD     Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+                DCD     Vector3A0
+                DCD     Vector3A4
+                DCD     Vector3A8
+                DCD     Vector3AC
+                DCD     Vector3B0
+                DCD     Vector3B4
+                DCD     Vector3B8
+                DCD     Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+                DCD     Vector3C0
+                DCD     Vector3C4
+                DCD     Vector3C8
+                DCD     Vector3CC
+                DCD     Vector3D0
+                DCD     Vector3D4
+                DCD     Vector3D8
+                DCD     Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+                DCD     Vector3E0
+                DCD     Vector3E4
+                DCD     Vector3E8
+                DCD     Vector3EC
+                DCD     Vector3F0
+                DCD     Vector3F4
+                DCD     Vector3F8
+                DCD     Vector3FC
+#endif
+
+                AREA    |.text|, CODE, READONLY
+                THUMB
+
+/*
+ * Default interrupt handlers.
+ */
+                EXPORT  _unhandled_exception
+_unhandled_exception PROC 
+                EXPORT  NMI_Handler             [WEAK]
+                EXPORT  HardFault_Handler       [WEAK]
+                EXPORT  MemManage_Handler       [WEAK]
+                EXPORT  BusFault_Handler        [WEAK]
+                EXPORT  UsageFault_Handler      [WEAK]
+                EXPORT  Vector1C                [WEAK]
+                EXPORT  Vector20                [WEAK]
+                EXPORT  Vector24                [WEAK]
+                EXPORT  Vector28                [WEAK]
+                EXPORT  SVC_Handler             [WEAK]
+                EXPORT  DebugMon_Handler        [WEAK]
+                EXPORT  Vector34                [WEAK]
+                EXPORT  PendSV_Handler          [WEAK]
+                EXPORT  SysTick_Handler         [WEAK]
+                EXPORT  Vector40                [WEAK]
+                EXPORT  Vector44                [WEAK]
+                EXPORT  Vector48                [WEAK]
+                EXPORT  Vector4C                [WEAK]
+                EXPORT  Vector50                [WEAK]
+                EXPORT  Vector54                [WEAK]
+                EXPORT  Vector58                [WEAK]
+                EXPORT  Vector5C                [WEAK]
+#if CORTEX_NUM_VECTORS > 8
+                EXPORT  Vector60                [WEAK]
+                EXPORT  Vector64                [WEAK]
+                EXPORT  Vector68                [WEAK]
+                EXPORT  Vector6C                [WEAK]
+                EXPORT  Vector70                [WEAK]
+                EXPORT  Vector74                [WEAK]
+                EXPORT  Vector78                [WEAK]
+                EXPORT  Vector7C                [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 16
+                EXPORT  Vector80                [WEAK]
+                EXPORT  Vector84                [WEAK]
+                EXPORT  Vector88                [WEAK]
+                EXPORT  Vector8C                [WEAK]
+                EXPORT  Vector90                [WEAK]
+                EXPORT  Vector94                [WEAK]
+                EXPORT  Vector98                [WEAK]
+                EXPORT  Vector9C                [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 24
+                EXPORT  VectorA0                [WEAK]
+                EXPORT  VectorA4                [WEAK]
+                EXPORT  VectorA8                [WEAK]
+                EXPORT  VectorAC                [WEAK]
+                EXPORT  VectorB0                [WEAK]
+                EXPORT  VectorB4                [WEAK]
+                EXPORT  VectorB8                [WEAK]
+                EXPORT  VectorBC                [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 32
+                EXPORT  VectorC0                [WEAK]
+                EXPORT  VectorC4                [WEAK]
+                EXPORT  VectorC8                [WEAK]
+                EXPORT  VectorCC                [WEAK]
+                EXPORT  VectorD0                [WEAK]
+                EXPORT  VectorD4                [WEAK]
+                EXPORT  VectorD8                [WEAK]
+                EXPORT  VectorDC                [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 40
+                EXPORT  VectorE0                [WEAK]
+                EXPORT  VectorE4                [WEAK]
+                EXPORT  VectorE8                [WEAK]
+                EXPORT  VectorEC                [WEAK]
+                EXPORT  VectorF0                [WEAK]
+                EXPORT  VectorF4                [WEAK]
+                EXPORT  VectorF8                [WEAK]
+                EXPORT  VectorFC                [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 48
+                EXPORT  Vector100               [WEAK]
+                EXPORT  Vector104               [WEAK]
+                EXPORT  Vector108               [WEAK]
+                EXPORT  Vector10C               [WEAK]
+                EXPORT  Vector110               [WEAK]
+                EXPORT  Vector114               [WEAK]
+                EXPORT  Vector118               [WEAK]
+                EXPORT  Vector11C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 56
+                EXPORT  Vector120               [WEAK]
+                EXPORT  Vector124               [WEAK]
+                EXPORT  Vector128               [WEAK]
+                EXPORT  Vector12C               [WEAK]
+                EXPORT  Vector130               [WEAK]
+                EXPORT  Vector134               [WEAK]
+                EXPORT  Vector138               [WEAK]
+                EXPORT  Vector13C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 64
+                EXPORT  Vector140               [WEAK]
+                EXPORT  Vector144               [WEAK]
+                EXPORT  Vector148               [WEAK]
+                EXPORT  Vector14C               [WEAK]
+                EXPORT  Vector150               [WEAK]
+                EXPORT  Vector154               [WEAK]
+                EXPORT  Vector158               [WEAK]
+                EXPORT  Vector15C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 72
+                EXPORT  Vector160               [WEAK]
+                EXPORT  Vector164               [WEAK]
+                EXPORT  Vector168               [WEAK]
+                EXPORT  Vector16C               [WEAK]
+                EXPORT  Vector170               [WEAK]
+                EXPORT  Vector174               [WEAK]
+                EXPORT  Vector178               [WEAK]
+                EXPORT  Vector17C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 80
+                EXPORT  Vector180               [WEAK]
+                EXPORT  Vector184               [WEAK]
+                EXPORT  Vector188               [WEAK]
+                EXPORT  Vector18C               [WEAK]
+                EXPORT  Vector190               [WEAK]
+                EXPORT  Vector194               [WEAK]
+                EXPORT  Vector198               [WEAK]
+                EXPORT  Vector19C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 88
+                EXPORT  Vector1A0               [WEAK]
+                EXPORT  Vector1A4               [WEAK]
+                EXPORT  Vector1A8               [WEAK]
+                EXPORT  Vector1AC               [WEAK]
+                EXPORT  Vector1B0               [WEAK]
+                EXPORT  Vector1B4               [WEAK]
+                EXPORT  Vector1B8               [WEAK]
+                EXPORT  Vector1BC               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 96
+                EXPORT  Vector1C0               [WEAK]
+                EXPORT  Vector1C4               [WEAK]
+                EXPORT  Vector1C8               [WEAK]
+                EXPORT  Vector1CC               [WEAK]
+                EXPORT  Vector1D0               [WEAK]
+                EXPORT  Vector1D4               [WEAK]
+                EXPORT  Vector1D8               [WEAK]
+                EXPORT  Vector1DC               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 104
+                EXPORT  Vector1E0               [WEAK]
+                EXPORT  Vector1E4               [WEAK]
+                EXPORT  Vector1E8               [WEAK]
+                EXPORT  Vector1EC               [WEAK]
+                EXPORT  Vector1F0               [WEAK]
+                EXPORT  Vector1F4               [WEAK]
+                EXPORT  Vector1F8               [WEAK]
+                EXPORT  Vector1FC               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 112
+                EXPORT  Vector200               [WEAK]
+                EXPORT  Vector204               [WEAK]
+                EXPORT  Vector208               [WEAK]
+                EXPORT  Vector20C               [WEAK]
+                EXPORT  Vector210               [WEAK]
+                EXPORT  Vector214               [WEAK]
+                EXPORT  Vector218               [WEAK]
+                EXPORT  Vector21C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 120
+                EXPORT  Vector220               [WEAK]
+                EXPORT  Vector224               [WEAK]
+                EXPORT  Vector228               [WEAK]
+                EXPORT  Vector22C               [WEAK]
+                EXPORT  Vector230               [WEAK]
+                EXPORT  Vector234               [WEAK]
+                EXPORT  Vector238               [WEAK]
+                EXPORT  Vector23C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 128
+                EXPORT  Vector240               [WEAK]
+                EXPORT  Vector244               [WEAK]
+                EXPORT  Vector248               [WEAK]
+                EXPORT  Vector24C               [WEAK]
+                EXPORT  Vector250               [WEAK]
+                EXPORT  Vector254               [WEAK]
+                EXPORT  Vector258               [WEAK]
+                EXPORT  Vector25C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 136
+                EXPORT  Vector260               [WEAK]
+                EXPORT  Vector264               [WEAK]
+                EXPORT  Vector268               [WEAK]
+                EXPORT  Vector26C               [WEAK]
+                EXPORT  Vector270               [WEAK]
+                EXPORT  Vector274               [WEAK]
+                EXPORT  Vector278               [WEAK]
+                EXPORT  Vector27C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 144
+                EXPORT  Vector280               [WEAK]
+                EXPORT  Vector284               [WEAK]
+                EXPORT  Vector288               [WEAK]
+                EXPORT  Vector28C               [WEAK]
+                EXPORT  Vector290               [WEAK]
+                EXPORT  Vector294               [WEAK]
+                EXPORT  Vector298               [WEAK]
+                EXPORT  Vector29C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 152
+                EXPORT  Vector2A0               [WEAK]
+                EXPORT  Vector2A4               [WEAK]
+                EXPORT  Vector2A8               [WEAK]
+                EXPORT  Vector2AC               [WEAK]
+                EXPORT  Vector2B0               [WEAK]
+                EXPORT  Vector2B4               [WEAK]
+                EXPORT  Vector2B8               [WEAK]
+                EXPORT  Vector2BC               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 160
+                EXPORT  Vector2C0               [WEAK]
+                EXPORT  Vector2C4               [WEAK]
+                EXPORT  Vector2C8               [WEAK]
+                EXPORT  Vector2CC               [WEAK]
+                EXPORT  Vector2D0               [WEAK]
+                EXPORT  Vector2D4               [WEAK]
+                EXPORT  Vector2D8               [WEAK]
+                EXPORT  Vector2DC               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 168
+                EXPORT  Vector2E0               [WEAK]
+                EXPORT  Vector2E4               [WEAK]
+                EXPORT  Vector2E8               [WEAK]
+                EXPORT  Vector2EC               [WEAK]
+                EXPORT  Vector2F0               [WEAK]
+                EXPORT  Vector2F4               [WEAK]
+                EXPORT  Vector2F8               [WEAK]
+                EXPORT  Vector2FC               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 176
+                EXPORT  Vector300               [WEAK]
+                EXPORT  Vector304               [WEAK]
+                EXPORT  Vector308               [WEAK]
+                EXPORT  Vector30C               [WEAK]
+                EXPORT  Vector310               [WEAK]
+                EXPORT  Vector314               [WEAK]
+                EXPORT  Vector318               [WEAK]
+                EXPORT  Vector31C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 184
+                EXPORT  Vector320               [WEAK]
+                EXPORT  Vector324               [WEAK]
+                EXPORT  Vector328               [WEAK]
+                EXPORT  Vector32C               [WEAK]
+                EXPORT  Vector330               [WEAK]
+                EXPORT  Vector334               [WEAK]
+                EXPORT  Vector338               [WEAK]
+                EXPORT  Vector33C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 192
+                EXPORT  Vector340               [WEAK]
+                EXPORT  Vector344               [WEAK]
+                EXPORT  Vector348               [WEAK]
+                EXPORT  Vector34C               [WEAK]
+                EXPORT  Vector350               [WEAK]
+                EXPORT  Vector354               [WEAK]
+                EXPORT  Vector358               [WEAK]
+                EXPORT  Vector35C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 200
+                EXPORT  Vector360               [WEAK]
+                EXPORT  Vector364               [WEAK]
+                EXPORT  Vector368               [WEAK]
+                EXPORT  Vector36C               [WEAK]
+                EXPORT  Vector370               [WEAK]
+                EXPORT  Vector374               [WEAK]
+                EXPORT  Vector378               [WEAK]
+                EXPORT  Vector37C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 208
+                EXPORT  Vector380               [WEAK]
+                EXPORT  Vector384               [WEAK]
+                EXPORT  Vector388               [WEAK]
+                EXPORT  Vector38C               [WEAK]
+                EXPORT  Vector390               [WEAK]
+                EXPORT  Vector394               [WEAK]
+                EXPORT  Vector398               [WEAK]
+                EXPORT  Vector39C               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 216
+                EXPORT  Vector3A0               [WEAK]
+                EXPORT  Vector3A4               [WEAK]
+                EXPORT  Vector3A8               [WEAK]
+                EXPORT  Vector3AC               [WEAK]
+                EXPORT  Vector3B0               [WEAK]
+                EXPORT  Vector3B4               [WEAK]
+                EXPORT  Vector3B8               [WEAK]
+                EXPORT  Vector3BC               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 224
+                EXPORT  Vector3C0               [WEAK]
+                EXPORT  Vector3C4               [WEAK]
+                EXPORT  Vector3C8               [WEAK]
+                EXPORT  Vector3CC               [WEAK]
+                EXPORT  Vector3D0               [WEAK]
+                EXPORT  Vector3D4               [WEAK]
+                EXPORT  Vector3D8               [WEAK]
+                EXPORT  Vector3DC               [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 232
+                EXPORT  Vector3E0               [WEAK]
+                EXPORT  Vector3E4               [WEAK]
+                EXPORT  Vector3E8               [WEAK]
+                EXPORT  Vector3EC               [WEAK]
+                EXPORT  Vector3F0               [WEAK]
+                EXPORT  Vector3F4               [WEAK]
+                EXPORT  Vector3F8               [WEAK]
+                EXPORT  Vector3FC               [WEAK]
+#endif
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+Vector1C
+Vector20
+Vector24
+Vector28
+SVC_Handler
+DebugMon_Handler
+Vector34
+PendSV_Handler
+SysTick_Handler
+Vector40
+Vector44
+Vector48
+Vector4C
+Vector50
+Vector54
+Vector58
+Vector5C
+#if CORTEX_NUM_VECTORS > 8
+Vector60
+Vector64
+Vector68
+Vector6C
+Vector70
+Vector74
+Vector78
+Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+Vector80
+Vector84
+Vector88
+Vector8C
+Vector90
+Vector94
+Vector98
+Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+VectorA0
+VectorA4
+VectorA8
+VectorAC
+VectorB0
+VectorB4
+VectorB8
+VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+VectorC0
+VectorC4
+VectorC8
+VectorCC
+VectorD0
+VectorD4
+VectorD8
+VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+VectorE0
+VectorE4
+VectorE8
+VectorEC
+VectorF0
+VectorF4
+VectorF8
+VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+Vector100
+Vector104
+Vector108
+Vector10C
+Vector110
+Vector114
+Vector118
+Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+Vector120
+Vector124
+Vector128
+Vector12C
+Vector130
+Vector134
+Vector138
+Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+Vector140
+Vector144
+Vector148
+Vector14C
+Vector150
+Vector154
+Vector158
+Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+Vector160
+Vector164
+Vector168
+Vector16C
+Vector170
+Vector174
+Vector178
+Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+Vector180
+Vector184
+Vector188
+Vector18C
+Vector190
+Vector194
+Vector198
+Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+Vector1A0
+Vector1A4
+Vector1A8
+Vector1AC
+Vector1B0
+Vector1B4
+Vector1B8
+Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+Vector1C0
+Vector1C4
+Vector1C8
+Vector1CC
+Vector1D0
+Vector1D4
+Vector1D8
+Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+Vector1E0
+Vector1E4
+Vector1E8
+Vector1EC
+Vector1F0
+Vector1F4
+Vector1F8
+Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+Vector200
+Vector204
+Vector208
+Vector20C
+Vector210
+Vector214
+Vector218
+Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+Vector220
+Vector224
+Vector228
+Vector22C
+Vector230
+Vector234
+Vector238
+Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+Vector240
+Vector244
+Vector248
+Vector24C
+Vector250
+Vector254
+Vector258
+Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+Vector260
+Vector264
+Vector268
+Vector26C
+Vector270
+Vector274
+Vector278
+Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+Vector280
+Vector284
+Vector288
+Vector28C
+Vector290
+Vector294
+Vector298
+Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+Vector2A0
+Vector2A4
+Vector2A8
+Vector2AC
+Vector2B0
+Vector2B4
+Vector2B8
+Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+Vector2C0
+Vector2C4
+Vector2C8
+Vector2CC
+Vector2D0
+Vector2D4
+Vector2D8
+Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+Vector2E0
+Vector2E4
+Vector2E8
+Vector2EC
+Vector2F0
+Vector2F4
+Vector2F8
+Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+Vector300
+Vector304
+Vector308
+Vector30C
+Vector310
+Vector314
+Vector318
+Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+Vector320
+Vector324
+Vector328
+Vector32C
+Vector330
+Vector334
+Vector338
+Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+Vector340
+Vector344
+Vector348
+Vector34C
+Vector350
+Vector354
+Vector358
+Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+Vector360
+Vector364
+Vector368
+Vector36C
+Vector370
+Vector374
+Vector378
+Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+Vector380
+Vector384
+Vector388
+Vector38C
+Vector390
+Vector394
+Vector398
+Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+Vector3A0
+Vector3A4
+Vector3A8
+Vector3AC
+Vector3B0
+Vector3B4
+Vector3B8
+Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+Vector3C0
+Vector3C4
+Vector3C8
+Vector3CC
+Vector3D0
+Vector3D4
+Vector3D8
+Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+Vector3E0
+Vector3E4
+Vector3E8
+Vector3EC
+Vector3F0
+Vector3F4
+Vector3F8
+Vector3FC
+#endif
+                b       _unhandled_exception
+                ENDP
+
+                END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h
new file mode 100644
index 000000000..8def2c0e0
--- /dev/null
+++ b/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h
@@ -0,0 +1,90 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/cmparams.h
+ * @brief   ARM Cortex-M0 parameters for the STM32F0xx.
+ *
+ * @defgroup ARMCMx_STM32F0xx STM32F0xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0 specific parameters for the
+ *          STM32F0xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            CORTEX_M0
+
+/**
+ * @brief   Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU          0
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          0
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    2
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      32
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+   then a file named board.h is included. This file must contain a device
+   definition compatible with the vendor include file.*/
+#if !defined(STM32F0030) && !defined(STM32F0XX_LD) && !defined(STM32F0XX_MD)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "stm32f0xx.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h
new file mode 100644
index 000000000..282f26602
--- /dev/null
+++ b/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h
@@ -0,0 +1,113 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F1xx/cmparams.h
+ * @brief   ARM Cortex-M3 parameters for the STM32F1xx.
+ *
+ * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          STM32F1xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            CORTEX_M3
+
+/**
+ * @brief   Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU          0
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          0
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    4
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      __NVECTORS
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+   then a file named board.h is included. This file must contain a device
+   definition compatible with the vendor include file.*/
+#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) &&                  \
+    !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) &&                  \
+    !defined(STM32F10X_HD) && !defined(STM32F10X_HD_VL) &&                  \
+    !defined(STM32F10X_XL) && !defined(STM32F10X_CL)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "stm32f10x.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#if defined(STM32F10X_CL)
+#define __NVECTORS              72
+#elif defined(STM32F10X_XL)
+#define __NVECTORS              64
+#elif defined(STM32F10X_LD_VL) ||                                           \
+      defined(STM32F10X_MD_VL) ||                                           \
+      defined(STM32F10X_HD_VL)
+#define __NVECTORS              64
+#elif defined(STM32F10X_LD) ||                                              \
+      defined(STM32F10X_MD) ||                                              \
+      defined(STM32F10X_HD)
+#define __NVECTORS              64
+#else
+#error "STM32F1xx device not defined or not recognized"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h
new file mode 100644
index 000000000..28e8051c6
--- /dev/null
+++ b/os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h
@@ -0,0 +1,94 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F3xx/cmparams.h
+ * @brief   ARM Cortex-M4 parameters for the STM32F3xx.
+ *
+ * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          STM32F3xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            CORTEX_M4
+
+/**
+ * @brief   Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU          1
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          1
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    4
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      88
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+   then a file named board.h is included. This file must contain a device
+   definition compatible with the vendor include file.*/
+#if !defined (STM32F30X)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "stm32f30x.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h
new file mode 100644
index 000000000..274e54193
--- /dev/null
+++ b/os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h
@@ -0,0 +1,94 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F37x/cmparams.h
+ * @brief   ARM Cortex-M4 parameters for the STM32F37x.
+ *
+ * @defgroup ARMCMx_STM32F37x STM32F37x Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          STM32F37x platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            CORTEX_M4
+
+/**
+ * @brief   Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU          1
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          1
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    4
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      88
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+   then a file named board.h is included. This file must contain a device
+   definition compatible with the vendor include file.*/
+#if !defined (STM32F37X)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "stm32f37x.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h
new file mode 100644
index 000000000..e742a7e66
--- /dev/null
+++ b/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h
@@ -0,0 +1,95 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F4xx/cmparams.h
+ * @brief   ARM Cortex-M4 parameters for the STM32F4xx.
+ *
+ * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          STM32F4xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            CORTEX_M4
+
+/**
+ * @brief   Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU          1
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          1
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    4
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      96
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+   then a file named board.h is included. This file must contain a device
+   definition compatible with the vendor include file.*/
+#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) &&                \
+    !defined(STM32F429_439xx) && !defined(STM32F401xx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "stm32f4xx.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h
new file mode 100644
index 000000000..76dcb200e
--- /dev/null
+++ b/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h
@@ -0,0 +1,94 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32L1xx/cmparams.h
+ * @brief   ARM Cortex-M4 parameters for the STM32L1xx.
+ *
+ * @defgroup ARMCMx_STM32L1xx STM32L1xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          STM32L1xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            CORTEX_M3
+
+/**
+ * @brief   Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU          1
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          0
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    4
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      64
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+   then a file named board.h is included. This file must contain a device
+   definition compatible with the vendor include file.*/
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_MDP) && !defined(STM32L1XX_HD)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "stm32l1xx.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/ports/GCC/PPC/crt0.s b/os/common/ports/e200/compilers/GCC/crt0.s
index 07e870451..07e870451 100644
--- a/os/ports/GCC/PPC/crt0.s
+++ b/os/common/ports/e200/compilers/GCC/crt0.s
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld
new file mode 100644
index 000000000..04cf9f9a3
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld
@@ -0,0 +1,27 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC560B50 memory setup.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 512k
+    dataflash : org = 0x00800000, len = 64k
+    ram       : org = 0x40000000, len = 32k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560B60.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560B60.ld
new file mode 100644
index 000000000..21f266177
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC560B60.ld
@@ -0,0 +1,27 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC560B60 memory setup.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 1024k
+    dataflash : org = 0x00800000, len = 64k
+    ram       : org = 0x40000000, len = 80k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld
new file mode 100644
index 000000000..b0f96746f
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld
@@ -0,0 +1,27 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC560B64 memory setup.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 1536k
+    dataflash : org = 0x00800000, len = 64k
+    ram       : org = 0x40000000, len = 96k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld
new file mode 100644
index 000000000..9e4e3b861
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld
@@ -0,0 +1,27 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC560D40 memory setup.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 256k
+    dataflash : org = 0x00800000, len = 64k
+    ram       : org = 0x40000000, len = 16k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560P50.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560P50.ld
new file mode 100644
index 000000000..c1f78abd5
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC560P50.ld
@@ -0,0 +1,27 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC560P50 memory setup.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 512k
+    dataflash : org = 0x00800000, len = 64k
+    ram       : org = 0x40000000, len = 40k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld b/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld
new file mode 100644
index 000000000..a065dd32d
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC563M64 memory setup.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 1536k
+    ram       : org = 0x40000000, len = 94k
+}
+
+INCLUDE rules_z3.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld b/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld
new file mode 100644
index 000000000..1f002c807
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC563A70 memory setup.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 2M
+    ram       : org = 0x40000000, len = 128k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld b/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld
new file mode 100644
index 000000000..5d61ef5b9
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC563A80 memory setup.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 4M
+    ram       : org = 0x40000000, len = 192k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld b/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld
new file mode 100644
index 000000000..8ab1fa6c4
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld
@@ -0,0 +1,27 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC56EC74 memory setup.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 3M
+    dataflash : org = 0x00800000, len = 64k
+    ram       : org = 0x40000000, len = 256k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC56EL54_LSM.ld b/os/common/ports/e200/compilers/GCC/ld/SPC56EL54_LSM.ld
new file mode 100644
index 000000000..e8ed5092d
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC56EL54_LSM.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC56EL54 memory setup in LSM mode.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 768k
+    ram       : org = 0x40000000, len = 128k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC56EL60_LSM.ld b/os/common/ports/e200/compilers/GCC/ld/SPC56EL60_LSM.ld
new file mode 100644
index 000000000..13fe240f3
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC56EL60_LSM.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC56EL60 memory setup in LSM mode.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 1M
+    ram       : org = 0x40000000, len = 128k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC56EL70_LSM.ld b/os/common/ports/e200/compilers/GCC/ld/SPC56EL70_LSM.ld
new file mode 100644
index 000000000..2642b4ce2
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/ld/SPC56EL70_LSM.ld
@@ -0,0 +1,26 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC56EL70 memory setup in LSM mode.
+ */
+MEMORY
+{
+    flash     : org = 0x00000000, len = 2M
+    ram       : org = 0x40000000, len = 192k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/rules.mk b/os/common/ports/e200/compilers/GCC/rules.mk
new file mode 100644
index 000000000..8ca82cac1
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/rules.mk
@@ -0,0 +1,218 @@
+# e200z common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+  OPT += -ffunction-sections -fdata-sections -fno-common
+  LDOPT := --gc-sections
+else
+  LDOPT :=
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+  LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+  OPT += -flto
+endif
+
+# VLE option handling.
+ifeq ($(USE_VLE),yes)
+  DDEFS += -DPPC_USE_VLE=1
+  DADEFS += -DPPC_USE_VLE=1
+  MCU += -mvle
+else
+  DDEFS += -DPPC_USE_VLE=0
+  DADEFS += -DPPC_USE_VLE=0
+endif
+
+# Process stack size
+ifeq ($(USE_PROCESS_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
+else
+  LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
+endif
+
+# Exceptions stack size
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400
+else
+  LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+  BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+  BUILDDIR = build
+endif
+OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
+           $(BUILDDIR)/$(PROJECT).mot $(BUILDDIR)/$(PROJECT).bin \
+           $(BUILDDIR)/$(PROJECT).dmp
+
+# Source files groups and paths
+SRC	      = $(CSRC)$(CPPSRC)
+SRCPATHS  = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC)))
+
+# Various directories
+OBJDIR    = $(BUILDDIR)/obj
+LSTDIR    = $(BUILDDIR)/lst
+
+# Object files groups
+COBJS     = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o)))
+CPPOBJS   = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o)))
+ASMOBJS   = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS	  = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS)
+
+# Paths
+IINCDIR   = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR   = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS      = $(DDEFS) $(UDEFS)
+ADEFS 	  = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS      = $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS   = -mcpu=$(MCU)
+ODFLAGS	  = -x --syms
+ASFLAGS   = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS  = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS    = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS  = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS   = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),$(LDOPT),--script=$(LDSCRIPT)
+
+# Generate dependency information
+CFLAGS   += -MD -MP -MF .dep/$(@F).d
+CPPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+# Paths where to search for sources
+VPATH     = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK
+
+MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | $(BUILDDIR)
+
+$(BUILDDIR) $(OBJDIR) $(LSTDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+	@echo Compiler Options
+	@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+	@echo
+endif
+	mkdir -p $(OBJDIR)
+	mkdir -p $(LSTDIR)
+
+$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(COBJS) : $(OBJDIR)/%.o : %.c Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+%.elf: $(OBJS) $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+	@echo Linking $@
+	@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(HEX) $< $@
+else
+	@echo Creating $@
+	@$(HEX) $< $@
+endif
+
+%.mot: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(MOT) $< $@
+else
+	@echo Creating $@
+	@$(MOT) $< $@
+endif
+
+%.bin: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(BIN) $< $@
+else
+	@echo Creating $@
+	@$(BIN) $< $@
+endif
+
+%.dmp: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(OD) $(ODFLAGS) $< > $@
+else
+	@echo Creating $@
+	@$(OD) $(ODFLAGS) $< > $@
+	@echo
+	@$(SZ) $<
+	@echo
+	@echo Done
+endif
+
+clean:
+	@echo Cleaning
+	-rm -fR .dep $(BUILDDIR)
+	@echo
+	@echo Done
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
diff --git a/os/common/ports/e200/compilers/GCC/rules_z0.ld b/os/common/ports/e200/compilers/GCC/rules_z0.ld
new file mode 100644
index 000000000..ad44243e3
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/rules_z0.ld
@@ -0,0 +1,159 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+__ram_size__            = LENGTH(ram);
+__ram_start__           = ORIGIN(ram);
+__ram_end__             = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(_reset_address)
+
+SECTIONS
+{
+    . = ORIGIN(flash);
+    .boot0 : ALIGN(16) SUBALIGN(16)
+    {
+        KEEP(*(.boot))
+    } > flash
+
+    .boot1 : ALIGN(16) SUBALIGN(16)
+    {
+        KEEP(*(.handlers))
+        KEEP(*(.crt0))
+        /* The vectors table requires a 2kB alignment.*/
+        . = ALIGN(0x800);
+        KEEP(*(.vectors))
+        /* The IVPR register requires a 4kB alignment.*/
+        . = ALIGN(0x1000);
+        __ivpr_base__ = .;
+        KEEP(*(.ivors))
+    } > flash
+
+    constructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+    } > flash
+
+    destructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(.fini_array))
+        KEEP(*(SORT(.fini_array.*)))
+        PROVIDE(__fini_array_end = .);
+    } > flash
+
+    .text_vle : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text_vle)
+        *(.text_vle.*)
+        *(.gnu.linkonce.t_vle.*)
+    } > flash
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text)
+        *(.text.*)
+        *(.gnu.linkonce.t.*)
+    } > flash
+
+    .rodata : ALIGN(16) SUBALIGN(16)
+    {
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.rodata1)
+    } > flash
+
+    .sdata2 : ALIGN(16) SUBALIGN(16)
+    {
+        __sdata2_start__ = . + 0x8000;
+        *(.sdata2)
+        *(.sdata2.*)
+        *(.gnu.linkonce.s2.*)
+        *(.sbss2)
+        *(.sbss2.*)
+        *(.gnu.linkonce.sb2.*)
+    } > flash
+
+    .eh_frame_hdr :
+    {
+        *(.eh_frame_hdr)
+    } > flash
+
+    .eh_frame : ONLY_IF_RO
+    {
+        *(.eh_frame)
+    } > flash
+
+    .romdata : ALIGN(16) SUBALIGN(16)
+    {
+        __romdata_start__ = .;
+    } > flash
+
+    .stacks : ALIGN(16) SUBALIGN(16)
+    {
+        . = ALIGN(8);
+        __irq_stack_base__ = .;
+        . += __irq_stack_size__;
+        . = ALIGN(8);
+        __irq_stack_end__ = .;
+        __process_stack_base__ = .;
+        __main_thread_stack_base__ = .;
+        . += __process_stack_size__;
+        . = ALIGN(8);
+        __process_stack_end__ = .;
+        __main_thread_stack_end__ = .;
+    } > ram
+
+    .data : AT(__romdata_start__)
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d.*)
+        __sdata_start__ = . + 0x8000;
+        *(.sdata)
+        *(.sdata.*)
+        *(.gnu.linkonce.s.*)
+        __data_end__ = .;
+    } > ram
+
+    .sbss :
+    {
+        __bss_start__ = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.gnu.linkonce.sb.*)
+        *(.scommon)
+    } > ram
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > ram
+
+    __heap_base__   = __bss_end__;
+    __heap_end__    = __ram_end__;
+}
diff --git a/os/common/ports/e200/compilers/GCC/rules_z3.ld b/os/common/ports/e200/compilers/GCC/rules_z3.ld
new file mode 100644
index 000000000..38177f3b5
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/rules_z3.ld
@@ -0,0 +1,156 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+__ram_size__            = LENGTH(ram);
+__ram_start__           = ORIGIN(ram);
+__ram_end__             = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(_reset_address)
+
+SECTIONS
+{
+    . = ORIGIN(flash);
+    .boot0 : ALIGN(16) SUBALIGN(16)
+    {
+        __ivpr_base__ = .;
+        KEEP(*(.boot))
+    } > flash
+
+    .boot1 : ALIGN(16) SUBALIGN(16)
+    {
+        KEEP(*(.handlers))
+        KEEP(*(.crt0))
+        /* The vectors table requires a 2kB alignment.*/
+        . = ALIGN(0x800);
+        KEEP(*(.vectors))
+    } > flash
+
+    constructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+    } > flash
+
+    destructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(.fini_array))
+        KEEP(*(SORT(.fini_array.*)))
+        PROVIDE(__fini_array_end = .);
+    } > flash
+
+    .text_vle : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text_vle)
+        *(.text_vle.*)
+        *(.gnu.linkonce.t_vle.*)
+    } > flash
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text)
+        *(.text.*)
+        *(.gnu.linkonce.t.*)
+    } > flash
+
+    .rodata : ALIGN(16) SUBALIGN(16)
+    {
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.rodata1)
+    } > flash
+
+    .sdata2 : ALIGN(16) SUBALIGN(16)
+    {
+        __sdata2_start__ = . + 0x8000;
+        *(.sdata2)
+        *(.sdata2.*)
+        *(.gnu.linkonce.s2.*)
+        *(.sbss2)
+        *(.sbss2.*)
+        *(.gnu.linkonce.sb2.*)
+    } > flash
+
+    .eh_frame_hdr :
+    {
+        *(.eh_frame_hdr)
+    } > flash
+
+    .eh_frame : ONLY_IF_RO
+    {
+        *(.eh_frame)
+    } > flash
+
+    .romdata : ALIGN(16) SUBALIGN(16)
+    {
+        __romdata_start__ = .;
+    } > flash
+
+    .stacks : ALIGN(16) SUBALIGN(16)
+    {
+        . = ALIGN(8);
+        __irq_stack_base__ = .;
+        . += __irq_stack_size__;
+        . = ALIGN(8);
+        __irq_stack_end__ = .;
+        __process_stack_base__ = .;
+        __main_thread_stack_base__ = .;
+        . += __process_stack_size__;
+        . = ALIGN(8);
+        __process_stack_end__ = .;
+        __main_thread_stack_end__ = .;
+    } > ram
+
+    .data : AT(__romdata_start__)
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d.*)
+        __sdata_start__ = . + 0x8000;
+        *(.sdata)
+        *(.sdata.*)
+        *(.gnu.linkonce.s.*)
+        __data_end__ = .;
+    } > ram
+
+    .sbss :
+    {
+        __bss_start__ = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.gnu.linkonce.sb.*)
+        *(.scommon)
+    } > ram
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > ram
+
+    __heap_base__   = __bss_end__;
+    __heap_end__    = __ram_end__;
+}
diff --git a/os/common/ports/e200/compilers/GCC/rules_z4.ld b/os/common/ports/e200/compilers/GCC/rules_z4.ld
new file mode 100644
index 000000000..38177f3b5
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/rules_z4.ld
@@ -0,0 +1,156 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+__ram_size__            = LENGTH(ram);
+__ram_start__           = ORIGIN(ram);
+__ram_end__             = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(_reset_address)
+
+SECTIONS
+{
+    . = ORIGIN(flash);
+    .boot0 : ALIGN(16) SUBALIGN(16)
+    {
+        __ivpr_base__ = .;
+        KEEP(*(.boot))
+    } > flash
+
+    .boot1 : ALIGN(16) SUBALIGN(16)
+    {
+        KEEP(*(.handlers))
+        KEEP(*(.crt0))
+        /* The vectors table requires a 2kB alignment.*/
+        . = ALIGN(0x800);
+        KEEP(*(.vectors))
+    } > flash
+
+    constructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+    } > flash
+
+    destructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(.fini_array))
+        KEEP(*(SORT(.fini_array.*)))
+        PROVIDE(__fini_array_end = .);
+    } > flash
+
+    .text_vle : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text_vle)
+        *(.text_vle.*)
+        *(.gnu.linkonce.t_vle.*)
+    } > flash
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text)
+        *(.text.*)
+        *(.gnu.linkonce.t.*)
+    } > flash
+
+    .rodata : ALIGN(16) SUBALIGN(16)
+    {
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.rodata1)
+    } > flash
+
+    .sdata2 : ALIGN(16) SUBALIGN(16)
+    {
+        __sdata2_start__ = . + 0x8000;
+        *(.sdata2)
+        *(.sdata2.*)
+        *(.gnu.linkonce.s2.*)
+        *(.sbss2)
+        *(.sbss2.*)
+        *(.gnu.linkonce.sb2.*)
+    } > flash
+
+    .eh_frame_hdr :
+    {
+        *(.eh_frame_hdr)
+    } > flash
+
+    .eh_frame : ONLY_IF_RO
+    {
+        *(.eh_frame)
+    } > flash
+
+    .romdata : ALIGN(16) SUBALIGN(16)
+    {
+        __romdata_start__ = .;
+    } > flash
+
+    .stacks : ALIGN(16) SUBALIGN(16)
+    {
+        . = ALIGN(8);
+        __irq_stack_base__ = .;
+        . += __irq_stack_size__;
+        . = ALIGN(8);
+        __irq_stack_end__ = .;
+        __process_stack_base__ = .;
+        __main_thread_stack_base__ = .;
+        . += __process_stack_size__;
+        . = ALIGN(8);
+        __process_stack_end__ = .;
+        __main_thread_stack_end__ = .;
+    } > ram
+
+    .data : AT(__romdata_start__)
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d.*)
+        __sdata_start__ = . + 0x8000;
+        *(.sdata)
+        *(.sdata.*)
+        *(.gnu.linkonce.s.*)
+        __data_end__ = .;
+    } > ram
+
+    .sbss :
+    {
+        __bss_start__ = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.gnu.linkonce.sb.*)
+        *(.scommon)
+    } > ram
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > ram
+
+    __heap_base__   = __bss_end__;
+    __heap_end__    = __ram_end__;
+}
diff --git a/os/common/ports/e200/compilers/GCC/vectors.h b/os/common/ports/e200/compilers/GCC/vectors.h
new file mode 100644
index 000000000..60241864e
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/vectors.h
@@ -0,0 +1,105 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    vectors.h
+ * @brief   ISR vector module header.
+ *
+ * @addtogroup VECTORS
+ * @{
+ */
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+#include "ppcparams.h"
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+#define INTC_MCR        *((volatile uint32_t *)0xfff48000)
+#define INTC_CPR        *((volatile uint32_t *)0xfff48008)
+#define INTC_IACKR      *((volatile uint32_t *)0xfff48010)
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+#if !defined(__DOXYGEN__)
+extern uint32_t _vectors[PPC_NUM_VECTORS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _unhandled_irq(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+static inline void intc_init(void) {
+
+  INTC_MCR   = 0;
+  INTC_CPR   = 0;
+  INTC_IACKR = (uint32_t)_vectors;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _VECTORS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/compilers/GCC/vectors.s b/os/common/ports/e200/compilers/GCC/vectors.s
new file mode 100644
index 000000000..bf6c2adf6
--- /dev/null
+++ b/os/common/ports/e200/compilers/GCC/vectors.s
@@ -0,0 +1,1076 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    vectors.s
+ * @brief   SPC56x vectors table.
+ *
+ * @addtogroup PPC_CORE
+ * @{
+ */
+
+#include "ppcparams.h"
+
+#if !defined(__DOXYGEN__)
+
+        /* Software vectors table. The vectors are accessed from the IVOR4
+           handler only. In order to declare an interrupt handler just create
+           a function withe the same name of a vector, the symbol will
+           override the weak symbol declared here.*/
+        .section    .vectors, "ax"
+        .align		4
+        .globl      _vectors
+_vectors:
+        .long       vector0,    vector1,    vector2,    vector3
+#if PPC_NUM_VECTORS > 4
+        .long       vector4,    vector5,    vector6,    vector7
+#endif
+#if PPC_NUM_VECTORS > 8
+        .long       vector8,    vector9,    vector10,   vector11
+#endif
+#if PPC_NUM_VECTORS > 12
+        .long       vector12,   vector13,   vector14,   vector15
+#endif
+#if PPC_NUM_VECTORS > 16
+        .long       vector16,   vector17,   vector18,   vector19
+#endif
+#if PPC_NUM_VECTORS > 20
+        .long       vector20,   vector21,   vector22,   vector23
+#endif
+#if PPC_NUM_VECTORS > 24
+        .long       vector24,   vector25,   vector26,   vector27
+#endif
+#if PPC_NUM_VECTORS > 28
+        .long       vector28,   vector29,   vector30,   vector31
+#endif
+#if PPC_NUM_VECTORS > 32
+        .long       vector32,   vector33,   vector34,   vector35
+#endif
+#if PPC_NUM_VECTORS > 36
+        .long       vector36,   vector37,   vector38,   vector39
+#endif
+#if PPC_NUM_VECTORS > 40
+        .long       vector40,   vector41,   vector42,   vector43
+#endif
+#if PPC_NUM_VECTORS > 44
+        .long       vector44,   vector45,   vector46,   vector47
+#endif
+#if PPC_NUM_VECTORS > 48
+        .long       vector48,   vector49,   vector50,   vector51
+#endif
+#if PPC_NUM_VECTORS > 52
+        .long       vector52,   vector53,   vector54,   vector55
+#endif
+#if PPC_NUM_VECTORS > 56
+        .long       vector56,   vector57,   vector58,   vector59
+#endif
+#if PPC_NUM_VECTORS > 60
+        .long       vector60,   vector61,   vector62,   vector63
+#endif
+#if PPC_NUM_VECTORS > 64
+        .long       vector64,   vector65,   vector66,   vector67
+#endif
+#if PPC_NUM_VECTORS > 68
+        .long       vector68,   vector69,   vector70,   vector71
+#endif
+#if PPC_NUM_VECTORS > 72
+        .long       vector72,   vector73,   vector74,   vector75
+#endif
+#if PPC_NUM_VECTORS > 76
+        .long       vector76,   vector77,   vector78,   vector79
+#endif
+#if PPC_NUM_VECTORS > 80
+        .long       vector80,   vector81,   vector82,   vector83
+#endif
+#if PPC_NUM_VECTORS > 84
+        .long       vector84,   vector85,   vector86,   vector87
+#endif
+#if PPC_NUM_VECTORS > 88
+        .long       vector88,   vector89,   vector90,   vector91
+#endif
+#if PPC_NUM_VECTORS > 92
+        .long       vector92,   vector93,   vector94,   vector95
+#endif
+#if PPC_NUM_VECTORS > 96
+        .long       vector96,   vector97,   vector98,   vector99
+#endif
+#if PPC_NUM_VECTORS > 100
+        .long       vector100,  vector101,  vector102,  vector103
+#endif
+#if PPC_NUM_VECTORS > 104
+        .long       vector104,  vector105,  vector106,  vector107
+#endif
+#if PPC_NUM_VECTORS > 108
+        .long       vector108,  vector109,  vector110,  vector111
+#endif
+#if PPC_NUM_VECTORS > 112
+        .long       vector112,  vector113,  vector114,  vector115
+#endif
+#if PPC_NUM_VECTORS > 116
+        .long       vector116,  vector117,  vector118,  vector119
+#endif
+#if PPC_NUM_VECTORS > 120
+        .long       vector120,  vector121,  vector122,  vector123
+#endif
+#if PPC_NUM_VECTORS > 124
+        .long       vector124,  vector125,  vector126,  vector127
+#endif
+#if PPC_NUM_VECTORS > 128
+        .long       vector128,  vector129,  vector130,  vector131
+#endif
+#if PPC_NUM_VECTORS > 132
+        .long       vector132,  vector133,  vector134,  vector135
+#endif
+#if PPC_NUM_VECTORS > 136
+        .long       vector136,  vector137,  vector138,  vector139
+#endif
+#if PPC_NUM_VECTORS > 140
+        .long       vector140,  vector141,  vector142,  vector143
+#endif
+#if PPC_NUM_VECTORS > 144
+        .long       vector144,  vector145,  vector146,  vector147
+#endif
+#if PPC_NUM_VECTORS > 148
+        .long       vector148,  vector149,  vector150,  vector151
+#endif
+#if PPC_NUM_VECTORS > 152
+        .long       vector152,  vector153,  vector154,  vector155
+#endif
+#if PPC_NUM_VECTORS > 156
+        .long       vector156,  vector157,  vector158,  vector159
+#endif
+#if PPC_NUM_VECTORS > 160
+        .long       vector160,  vector161,  vector162,  vector163
+#endif
+#if PPC_NUM_VECTORS > 164
+        .long       vector164,  vector165,  vector166,  vector167
+#endif
+#if PPC_NUM_VECTORS > 168
+        .long       vector168,  vector169,  vector170,  vector171
+#endif
+#if PPC_NUM_VECTORS > 172
+        .long       vector172,  vector173,  vector174,  vector175
+#endif
+#if PPC_NUM_VECTORS > 176
+        .long       vector176,  vector177,  vector178,  vector179
+#endif
+#if PPC_NUM_VECTORS > 180
+        .long       vector180,  vector181,  vector182,  vector183
+#endif
+#if PPC_NUM_VECTORS > 184
+        .long       vector184,  vector185,  vector186,  vector187
+#endif
+#if PPC_NUM_VECTORS > 188
+        .long       vector188,  vector189,  vector190,  vector191
+#endif
+#if PPC_NUM_VECTORS > 192
+        .long       vector192,  vector193,  vector194,  vector195
+#endif
+#if PPC_NUM_VECTORS > 196
+        .long       vector196,  vector197,  vector198,  vector199
+#endif
+#if PPC_NUM_VECTORS > 200
+        .long       vector200,  vector201,  vector202,  vector203
+#endif
+#if PPC_NUM_VECTORS > 204
+        .long       vector204,  vector205,  vector206,  vector207
+#endif
+#if PPC_NUM_VECTORS > 208
+        .long       vector208,  vector209,  vector210,  vector211
+#endif
+#if PPC_NUM_VECTORS > 212
+        .long       vector212,  vector213,  vector214,  vector215
+#endif
+#if PPC_NUM_VECTORS > 216
+        .long       vector216,  vector217,  vector218,  vector219
+#endif
+#if PPC_NUM_VECTORS > 220
+        .long       vector220,  vector221,  vector222,  vector223
+#endif
+#if PPC_NUM_VECTORS > 224
+        .long       vector224,  vector225,  vector226,  vector227
+#endif
+#if PPC_NUM_VECTORS > 228
+        .long       vector228,  vector229,  vector230,  vector231
+#endif
+#if PPC_NUM_VECTORS > 232
+        .long       vector232,  vector233,  vector234,  vector235
+#endif
+#if PPC_NUM_VECTORS > 236
+        .long       vector236,  vector237,  vector238,  vector239
+#endif
+#if PPC_NUM_VECTORS > 240
+        .long       vector240,  vector241,  vector242,  vector243
+#endif
+#if PPC_NUM_VECTORS > 244
+        .long       vector244,  vector245,  vector246,  vector247
+#endif
+#if PPC_NUM_VECTORS > 248
+        .long       vector248,  vector249,  vector250,  vector251
+#endif
+#if PPC_NUM_VECTORS > 252
+        .long       vector252,  vector253,  vector254,  vector255
+#endif
+#if PPC_NUM_VECTORS > 256
+        .long       vector256,  vector257,  vector258,  vector259
+#endif
+#if PPC_NUM_VECTORS > 260
+        .long       vector260,  vector261,  vector262,  vector263
+#endif
+#if PPC_NUM_VECTORS > 264
+        .long       vector264,  vector265,  vector266,  vector267
+#endif
+#if PPC_NUM_VECTORS > 268
+        .long       vector268,  vector269,  vector270,  vector271
+#endif
+#if PPC_NUM_VECTORS > 272
+        .long       vector272,  vector273,  vector274,  vector275
+#endif
+#if PPC_NUM_VECTORS > 276
+        .long       vector276,  vector277,  vector278,  vector279
+#endif
+#if PPC_NUM_VECTORS > 280
+        .long       vector280,  vector281,  vector282,  vector283
+#endif
+#if PPC_NUM_VECTORS > 284
+        .long       vector284,  vector285,  vector286,  vector287
+#endif
+#if PPC_NUM_VECTORS > 288
+        .long       vector288,  vector289,  vector290,  vector291
+#endif
+#if PPC_NUM_VECTORS > 292
+        .long       vector292,  vector293,  vector294,  vector295
+#endif
+#if PPC_NUM_VECTORS > 296
+        .long       vector296,  vector297,  vector298,  vector299
+#endif
+#if PPC_NUM_VECTORS > 300
+        .long       vector300,  vector301,  vector302,  vector303
+#endif
+#if PPC_NUM_VECTORS > 304
+        .long       vector304,  vector305,  vector306,  vector307
+#endif
+#if PPC_NUM_VECTORS > 308
+        .long       vector308,  vector309,  vector310,  vector311
+#endif
+#if PPC_NUM_VECTORS > 312
+        .long       vector312,  vector313,  vector314,  vector315
+#endif
+#if PPC_NUM_VECTORS > 316
+        .long       vector316,  vector317,  vector318,  vector319
+#endif
+#if PPC_NUM_VECTORS > 320
+        .long       vector320,  vector321,  vector322,  vector323
+#endif
+#if PPC_NUM_VECTORS > 324
+        .long       vector324,  vector325,  vector326,  vector327
+#endif
+#if PPC_NUM_VECTORS > 328
+        .long       vector328,  vector329,  vector330,  vector331
+#endif
+#if PPC_NUM_VECTORS > 332
+        .long       vector332,  vector333,  vector334,  vector335
+#endif
+#if PPC_NUM_VECTORS > 336
+        .long       vector336,  vector337,  vector338,  vector339
+#endif
+#if PPC_NUM_VECTORS > 340
+        .long       vector340,  vector341,  vector342,  vector343
+#endif
+#if PPC_NUM_VECTORS > 344
+        .long       vector344,  vector345,  vector346,  vector347
+#endif
+#if PPC_NUM_VECTORS > 348
+        .long       vector348,  vector349,  vector350,  vector351
+#endif
+#if PPC_NUM_VECTORS > 352
+        .long       vector352,  vector353,  vector354,  vector355
+#endif
+#if PPC_NUM_VECTORS > 356
+        .long       vector356,  vector357,  vector358,  vector359
+#endif
+#if PPC_NUM_VECTORS > 360
+        .long       vector360,  vector361,  vector362,  vector363
+#endif
+#if PPC_NUM_VECTORS > 364
+        .long       vector364,  vector365,  vector366,  vector367
+#endif
+#if PPC_NUM_VECTORS > 368
+        .long       vector368,  vector369,  vector370,  vector371
+#endif
+#if PPC_NUM_VECTORS > 372
+        .long       vector372,  vector373,  vector374,  vector375
+#endif
+#if PPC_NUM_VECTORS > 376
+        .long       vector376,  vector377,  vector378,  vector379
+#endif
+#if PPC_NUM_VECTORS > 380
+        .long       vector380,  vector381,  vector382,  vector383
+#endif
+#if PPC_NUM_VECTORS > 384
+        .long       vector384,  vector385,  vector386,  vector387
+#endif
+#if PPC_NUM_VECTORS > 388
+        .long       vector388,  vector389,  vector390,  vector391
+#endif
+#if PPC_NUM_VECTORS > 392
+        .long       vector392,  vector393,  vector394,  vector395
+#endif
+#if PPC_NUM_VECTORS > 396
+        .long       vector396,  vector397,  vector398,  vector399
+#endif
+#if PPC_NUM_VECTORS > 400
+        .long       vector400,  vector401,  vector402,  vector403
+#endif
+#if PPC_NUM_VECTORS > 404
+        .long       vector404,  vector405,  vector406,  vector407
+#endif
+#if PPC_NUM_VECTORS > 408
+        .long       vector408,  vector409,  vector410,  vector411
+#endif
+#if PPC_NUM_VECTORS > 412
+        .long       vector412,  vector413,  vector414,  vector415
+#endif
+#if PPC_NUM_VECTORS > 416
+        .long       vector416,  vector417,  vector418,  vector419
+#endif
+#if PPC_NUM_VECTORS > 420
+        .long       vector420,  vector421,  vector422,  vector423
+#endif
+#if PPC_NUM_VECTORS > 424
+        .long       vector424,  vector425,  vector426,  vector427
+#endif
+#if PPC_NUM_VECTORS > 428
+        .long       vector428,  vector429,  vector430,  vector431
+#endif
+#if PPC_NUM_VECTORS > 432
+        .long       vector432,  vector433,  vector434,  vector435
+#endif
+#if PPC_NUM_VECTORS > 436
+        .long       vector436,  vector437,  vector438,  vector439
+#endif
+#if PPC_NUM_VECTORS > 440
+        .long       vector440,  vector441,  vector442,  vector443
+#endif
+#if PPC_NUM_VECTORS > 444
+        .long       vector444,  vector445,  vector446,  vector447
+#endif
+#if PPC_NUM_VECTORS > 448
+        .long       vector448,  vector449,  vector450,  vector451
+#endif
+#if PPC_NUM_VECTORS > 452
+        .long       vector452,  vector453,  vector454,  vector455
+#endif
+#if PPC_NUM_VECTORS > 456
+        .long       vector456,  vector457,  vector458,  vector459
+#endif
+#if PPC_NUM_VECTORS > 460
+        .long       vector460,  vector461,  vector462,  vector463
+#endif
+#if PPC_NUM_VECTORS > 464
+        .long       vector464,  vector465,  vector466,  vector467
+#endif
+#if PPC_NUM_VECTORS > 468
+        .long       vector468,  vector469,  vector470,  vector471
+#endif
+#if PPC_NUM_VECTORS > 472
+        .long       vector472,  vector473,  vector474,  vector475
+#endif
+#if PPC_NUM_VECTORS > 476
+        .long       vector476,  vector477,  vector478,  vector479
+#endif
+#if PPC_NUM_VECTORS > 480
+        .long       vector480,  vector481,  vector482,  vector483
+#endif
+#if PPC_NUM_VECTORS > 484
+        .long       vector484,  vector485,  vector486,  vector487
+#endif
+#if PPC_NUM_VECTORS > 488
+        .long       vector488,  vector489,  vector490,  vector491
+#endif
+#if PPC_NUM_VECTORS > 492
+        .long       vector492,  vector493,  vector494,  vector495
+#endif
+#if PPC_NUM_VECTORS > 496
+        .long       vector496,  vector497,  vector498,  vector499
+#endif
+#if PPC_NUM_VECTORS > 500
+        .long       vector500,  vector501,  vector502,  vector503
+#endif
+#if PPC_NUM_VECTORS > 504
+        .long       vector504,  vector505,  vector506,  vector507
+#endif
+#if PPC_NUM_VECTORS > 508
+        .long       vector508,  vector509,  vector510,  vector511
+#endif
+
+        .text
+        .align      2
+
+        .weak       vector0,    vector1,    vector2,    vector3
+        .weak       vector4,    vector5,    vector6,    vector7
+        .weak       vector8,    vector9,    vector10,   vector11
+        .weak       vector12,   vector13,   vector14,   vector15
+        .weak       vector16,   vector17,   vector18,   vector19
+        .weak       vector20,   vector21,   vector22,   vector23
+        .weak       vector24,   vector25,   vector26,   vector27
+        .weak       vector28,   vector29,   vector30,   vector31
+        .weak       vector32,   vector33,   vector34,   vector35
+        .weak       vector36,   vector37,   vector38,   vector39
+        .weak       vector40,   vector41,   vector42,   vector43
+        .weak       vector44,   vector45,   vector46,   vector47
+        .weak       vector48,   vector49,   vector50,   vector51
+        .weak       vector52,   vector53,   vector54,   vector55
+        .weak       vector56,   vector57,   vector58,   vector59
+        .weak       vector60,   vector61,   vector62,   vector63
+        .weak       vector64,   vector65,   vector66,   vector67
+        .weak       vector68,   vector69,   vector70,   vector71
+        .weak       vector72,   vector73,   vector74,   vector75
+        .weak       vector76,   vector77,   vector78,   vector79
+        .weak       vector80,   vector81,   vector82,   vector83
+        .weak       vector84,   vector85,   vector86,   vector87
+        .weak       vector88,   vector89,   vector90,   vector91
+        .weak       vector92,   vector93,   vector94,   vector95
+        .weak       vector96,   vector97,   vector98,   vector99
+        .weak       vector100,  vector101,  vector102,  vector103
+        .weak       vector104,  vector105,  vector106,  vector107
+        .weak       vector108,  vector109,  vector110,  vector111
+        .weak       vector112,  vector113,  vector114,  vector115
+        .weak       vector116,  vector117,  vector118,  vector119
+        .weak       vector120,  vector121,  vector122,  vector123
+        .weak       vector124,  vector125,  vector126,  vector127
+        .weak       vector128,  vector129,  vector130,  vector131
+        .weak       vector132,  vector133,  vector134,  vector135
+        .weak       vector136,  vector137,  vector138,  vector139
+        .weak       vector140,  vector141,  vector142,  vector143
+        .weak       vector144,  vector145,  vector146,  vector147
+        .weak       vector148,  vector149,  vector150,  vector151
+        .weak       vector152,  vector153,  vector154,  vector155
+        .weak       vector156,  vector157,  vector158,  vector159
+        .weak       vector160,  vector161,  vector162,  vector163
+        .weak       vector164,  vector165,  vector166,  vector167
+        .weak       vector168,  vector169,  vector170,  vector171
+        .weak       vector172,  vector173,  vector174,  vector175
+        .weak       vector176,  vector177,  vector178,  vector179
+        .weak       vector180,  vector181,  vector182,  vector183
+        .weak       vector184,  vector185,  vector186,  vector187
+        .weak       vector188,  vector189,  vector190,  vector191
+        .weak       vector192,  vector193,  vector194,  vector195
+        .weak       vector196,  vector197,  vector198,  vector199
+        .weak       vector200,  vector201,  vector202,  vector203
+        .weak       vector204,  vector205,  vector206,  vector207
+        .weak       vector208,  vector209,  vector210,  vector211
+        .weak       vector212,  vector213,  vector214,  vector215
+        .weak       vector216,  vector217,  vector218,  vector219
+        .weak       vector220,  vector221,  vector222,  vector223
+        .weak       vector224,  vector225,  vector226,  vector227
+        .weak       vector228,  vector229,  vector230,  vector231
+        .weak       vector232,  vector233,  vector234,  vector235
+        .weak       vector236,  vector237,  vector238,  vector239
+        .weak       vector240,  vector241,  vector242,  vector243
+        .weak       vector244,  vector245,  vector246,  vector247
+        .weak       vector248,  vector249,  vector250,  vector251
+        .weak       vector252,  vector253,  vector254,  vector255
+        .weak       vector256,  vector257,  vector258,  vector259
+        .weak       vector260,  vector261,  vector262,  vector263
+        .weak       vector264,  vector265,  vector266,  vector267
+        .weak       vector268,  vector269,  vector270,  vector271
+        .weak       vector272,  vector273,  vector274,  vector275
+        .weak       vector276,  vector277,  vector278,  vector279
+        .weak       vector280,  vector281,  vector282,  vector283
+        .weak       vector284,  vector285,  vector286,  vector287
+        .weak       vector288,  vector289,  vector290,  vector291
+        .weak       vector292,  vector293,  vector294,  vector295
+        .weak       vector296,  vector297,  vector298,  vector299
+        .weak       vector300,  vector301,  vector302,  vector303
+        .weak       vector304,  vector305,  vector306,  vector307
+        .weak       vector308,  vector309,  vector310,  vector311
+        .weak       vector312,  vector313,  vector314,  vector315
+        .weak       vector316,  vector317,  vector318,  vector319
+        .weak       vector320,  vector321,  vector322,  vector323
+        .weak       vector324,  vector325,  vector326,  vector327
+        .weak       vector328,  vector329,  vector330,  vector331
+        .weak       vector332,  vector333,  vector334,  vector335
+        .weak       vector336,  vector337,  vector338,  vector339
+        .weak       vector340,  vector341,  vector342,  vector343
+        .weak       vector344,  vector345,  vector346,  vector347
+        .weak       vector348,  vector349,  vector350,  vector351
+        .weak       vector352,  vector353,  vector354,  vector355
+        .weak       vector356,  vector357,  vector358,  vector359
+        .weak       vector360,  vector361,  vector362,  vector363
+        .weak       vector364,  vector365,  vector366,  vector367
+        .weak       vector368,  vector369,  vector370,  vector371
+        .weak       vector372,  vector373,  vector374,  vector375
+        .weak       vector376,  vector377,  vector378,  vector379
+        .weak       vector380,  vector381,  vector382,  vector383
+        .weak       vector384,  vector385,  vector386,  vector387
+        .weak       vector388,  vector389,  vector390,  vector391
+        .weak       vector392,  vector393,  vector394,  vector395
+        .weak       vector396,  vector397,  vector398,  vector399
+        .weak       vector400,  vector401,  vector402,  vector403
+        .weak       vector404,  vector405,  vector406,  vector407
+        .weak       vector408,  vector409,  vector410,  vector411
+        .weak       vector412,  vector413,  vector414,  vector415
+        .weak       vector416,  vector417,  vector418,  vector419
+        .weak       vector420,  vector421,  vector422,  vector423
+        .weak       vector424,  vector425,  vector426,  vector427
+        .weak       vector428,  vector429,  vector430,  vector431
+        .weak       vector432,  vector433,  vector434,  vector435
+        .weak       vector436,  vector437,  vector438,  vector439
+        .weak       vector440,  vector441,  vector442,  vector443
+        .weak       vector444,  vector445,  vector446,  vector447
+        .weak       vector448,  vector449,  vector450,  vector451
+        .weak       vector452,  vector453,  vector454,  vector455
+        .weak       vector456,  vector457,  vector458,  vector459
+        .weak       vector460,  vector461,  vector462,  vector463
+        .weak       vector464,  vector465,  vector466,  vector467
+        .weak       vector468,  vector469,  vector470,  vector471
+        .weak       vector472,  vector473,  vector474,  vector475
+        .weak       vector476,  vector477,  vector478,  vector479
+        .weak       vector480,  vector481,  vector482,  vector483
+        .weak       vector484,  vector485,  vector486,  vector487
+        .weak       vector488,  vector489,  vector490,  vector491
+        .weak       vector492,  vector493,  vector494,  vector495
+        .weak       vector496,  vector497,  vector498,  vector499
+        .weak       vector500,  vector501,  vector502,  vector503
+        .weak       vector504,  vector505,  vector506,  vector507
+        .weak       vector508,  vector509,  vector510,  vector511
+
+vector0:
+vector1:
+vector2:
+vector3:
+vector4:
+vector5:
+vector6:
+vector7:
+vector8:
+vector9:
+vector10:
+vector11:
+vector12:
+vector13:
+vector14:
+vector15:
+vector16:
+vector17:
+vector18:
+vector19:
+vector20:
+vector21:
+vector22:
+vector23:
+vector24:
+vector25:
+vector26:
+vector27:
+vector28:
+vector29:
+vector30:
+vector31:
+vector32:
+vector33:
+vector34:
+vector35:
+vector36:
+vector37:
+vector38:
+vector39:
+vector40:
+vector41:
+vector42:
+vector43:
+vector44:
+vector45:
+vector46:
+vector47:
+vector48:
+vector49:
+vector50:
+vector51:
+vector52:
+vector53:
+vector54:
+vector55:
+vector56:
+vector57:
+vector58:
+vector59:
+vector60:
+vector61:
+vector62:
+vector63:
+vector64:
+vector65:
+vector66:
+vector67:
+vector68:
+vector69:
+vector70:
+vector71:
+vector72:
+vector73:
+vector74:
+vector75:
+vector76:
+vector77:
+vector78:
+vector79:
+vector80:
+vector81:
+vector82:
+vector83:
+vector84:
+vector85:
+vector86:
+vector87:
+vector88:
+vector89:
+vector90:
+vector91:
+vector92:
+vector93:
+vector94:
+vector95:
+vector96:
+vector97:
+vector98:
+vector99:
+vector100:
+vector101:
+vector102:
+vector103:
+vector104:
+vector105:
+vector106:
+vector107:
+vector108:
+vector109:
+vector110:
+vector111:
+vector112:
+vector113:
+vector114:
+vector115:
+vector116:
+vector117:
+vector118:
+vector119:
+vector120:
+vector121:
+vector122:
+vector123:
+vector124:
+vector125:
+vector126:
+vector127:
+vector128:
+vector129:
+vector130:
+vector131:
+vector132:
+vector133:
+vector134:
+vector135:
+vector136:
+vector137:
+vector138:
+vector139:
+vector140:
+vector141:
+vector142:
+vector143:
+vector144:
+vector145:
+vector146:
+vector147:
+vector148:
+vector149:
+vector150:
+vector151:
+vector152:
+vector153:
+vector154:
+vector155:
+vector156:
+vector157:
+vector158:
+vector159:
+vector160:
+vector161:
+vector162:
+vector163:
+vector164:
+vector165:
+vector166:
+vector167:
+vector168:
+vector169:
+vector170:
+vector171:
+vector172:
+vector173:
+vector174:
+vector175:
+vector176:
+vector177:
+vector178:
+vector179:
+vector180:
+vector181:
+vector182:
+vector183:
+vector184:
+vector185:
+vector186:
+vector187:
+vector188:
+vector189:
+vector190:
+vector191:
+vector192:
+vector193:
+vector194:
+vector195:
+vector196:
+vector197:
+vector198:
+vector199:
+vector200:
+vector201:
+vector202:
+vector203:
+vector204:
+vector205:
+vector206:
+vector207:
+vector208:
+vector209:
+vector210:
+vector211:
+vector212:
+vector213:
+vector214:
+vector215:
+vector216:
+vector217:
+vector218:
+vector219:
+vector220:
+vector221:
+vector222:
+vector223:
+vector224:
+vector225:
+vector226:
+vector227:
+vector228:
+vector229:
+vector230:
+vector231:
+vector232:
+vector233:
+vector234:
+vector235:
+vector236:
+vector237:
+vector238:
+vector239:
+vector240:
+vector241:
+vector242:
+vector243:
+vector244:
+vector245:
+vector246:
+vector247:
+vector248:
+vector249:
+vector250:
+vector251:
+vector252:
+vector253:
+vector254:
+vector255:
+vector256:
+vector257:
+vector258:
+vector259:
+vector260:
+vector261:
+vector262:
+vector263:
+vector264:
+vector265:
+vector266:
+vector267:
+vector268:
+vector269:
+vector270:
+vector271:
+vector272:
+vector273:
+vector274:
+vector275:
+vector276:
+vector277:
+vector278:
+vector279:
+vector280:
+vector281:
+vector282:
+vector283:
+vector284:
+vector285:
+vector286:
+vector287:
+vector288:
+vector289:
+vector290:
+vector291:
+vector292:
+vector293:
+vector294:
+vector295:
+vector296:
+vector297:
+vector298:
+vector299:
+vector300:
+vector301:
+vector302:
+vector303:
+vector304:
+vector305:
+vector306:
+vector307:
+vector308:
+vector309:
+vector310:
+vector311:
+vector312:
+vector313:
+vector314:
+vector315:
+vector316:
+vector317:
+vector318:
+vector319:
+vector320:
+vector321:
+vector322:
+vector323:
+vector324:
+vector325:
+vector326:
+vector327:
+vector328:
+vector329:
+vector330:
+vector331:
+vector332:
+vector333:
+vector334:
+vector335:
+vector336:
+vector337:
+vector338:
+vector339:
+vector340:
+vector341:
+vector342:
+vector343:
+vector344:
+vector345:
+vector346:
+vector347:
+vector348:
+vector349:
+vector350:
+vector351:
+vector352:
+vector353:
+vector354:
+vector355:
+vector356:
+vector357:
+vector358:
+vector359:
+vector360:
+vector361:
+vector362:
+vector363:
+vector364:
+vector365:
+vector366:
+vector367:
+vector368:
+vector369:
+vector370:
+vector371:
+vector372:
+vector373:
+vector374:
+vector375:
+vector376:
+vector377:
+vector378:
+vector379:
+vector380:
+vector381:
+vector382:
+vector383:
+vector384:
+vector385:
+vector386:
+vector387:
+vector388:
+vector389:
+vector390:
+vector391:
+vector392:
+vector393:
+vector394:
+vector395:
+vector396:
+vector397:
+vector398:
+vector399:
+vector400:
+vector401:
+vector402:
+vector403:
+vector404:
+vector405:
+vector406:
+vector407:
+vector408:
+vector409:
+vector410:
+vector411:
+vector412:
+vector413:
+vector414:
+vector415:
+vector416:
+vector417:
+vector418:
+vector419:
+vector420:
+vector421:
+vector422:
+vector423:
+vector424:
+vector425:
+vector426:
+vector427:
+vector428:
+vector429:
+vector430:
+vector431:
+vector432:
+vector433:
+vector434:
+vector435:
+vector436:
+vector437:
+vector438:
+vector439:
+vector440:
+vector441:
+vector442:
+vector443:
+vector444:
+vector445:
+vector446:
+vector447:
+vector448:
+vector449:
+vector450:
+vector451:
+vector452:
+vector453:
+vector454:
+vector455:
+vector456:
+vector457:
+vector458:
+vector459:
+vector460:
+vector461:
+vector462:
+vector463:
+vector464:
+vector465:
+vector466:
+vector467:
+vector468:
+vector469:
+vector470:
+vector471:
+vector472:
+vector473:
+vector474:
+vector475:
+vector476:
+vector477:
+vector478:
+vector479:
+vector480:
+vector481:
+vector482:
+vector483:
+vector484:
+vector485:
+vector486:
+vector487:
+vector488:
+vector489:
+vector490:
+vector491:
+vector492:
+vector493:
+vector494:
+vector495:
+vector496:
+vector497:
+vector498:
+vector499:
+vector500:
+vector501:
+vector502:
+vector503:
+vector504:
+vector505:
+vector506:
+vector507:
+vector508:
+vector509:
+vector510:
+vector511:
+
+        .weak       _unhandled_irq
+        .type       _unhandled_irq, @function
+_unhandled_irq:
+         b          _unhandled_irq
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560BCxx/boot.h b/os/common/ports/e200/devices/SPC560BCxx/boot.h
new file mode 100644
index 000000000..51b2607ae
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560BCxx/boot.h
@@ -0,0 +1,118 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    boot.h
+ * @brief   Boot parameters for the SPC560BCxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN              0x00000001
+#define BUCSR_BALLOC_BFI        0x00000200
+/** @} */
+
+/**
+ * @name   MSR register definitions
+ * @{
+ */
+#define MSR_WE                  0x00040000
+#define MSR_CE                  0x00020000
+#define MSR_EE                  0x00008000
+#define MSR_PR                  0x00004000
+#define MSR_ME                  0x00001000
+#define MSR_DE                  0x00000200
+#define MSR_IS                  0x00000020
+#define MSR_DS                  0x00000010
+#define MSR_RI                  0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT      (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT        (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT  1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE            1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM    0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560BCxx/boot.s b/os/common/ports/e200/devices/SPC560BCxx/boot.s
new file mode 100644
index 000000000..7c8457161
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560BCxx/boot.s
@@ -0,0 +1,214 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    SPC560BCxx/boot.s
+ * @brief   SPC560BCxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+        /* BAM record.*/
+        .section    .boot, "ax"
+
+        .long       0x015A0000
+        .long       _reset_address
+
+        .align      2
+        .globl      _reset_address
+        .type       _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+        bl          _coreinit
+#endif
+        bl          _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+        /*
+         * Image relocation in RAM.
+         */
+        lis         %r4, __ram_reloc_start__@h
+        ori         %r4, %r4, __ram_reloc_start__@l
+        lis         %r5, __ram_reloc_dest__@h
+        ori         %r5, %r5, __ram_reloc_dest__@l
+        lis         %r6, __ram_reloc_end__@h
+        ori         %r6, %r6, __ram_reloc_end__@l
+.relloop:
+        cmpl        cr0, %r4, %r6
+        bge         cr0, .relend
+        lwz         %r7, 0(%r4)
+        addi        %r4, %r4, 4
+        stw         %r7, 0(%r5)
+        addi        %r5, %r5, 4
+        b           .relloop
+.relend:
+        lis         %r3, _boot_address@h
+        ori         %r3, %r3, _boot_address@l
+        mtctr       %r3
+        bctrl
+#else
+        b           _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+        .align      2
+_coreinit:
+        /*
+         * RAM clearing, this device requires a write to all RAM location in
+         * order to initialize the ECC detection hardware, this is going to
+         * slow down the startup but there is no way around.
+         */
+        xor         %r0, %r0, %r0
+        xor         %r1, %r1, %r1
+        xor         %r2, %r2, %r2
+        xor         %r3, %r3, %r3
+        xor         %r4, %r4, %r4
+        xor         %r5, %r5, %r5
+        xor         %r6, %r6, %r6
+        xor         %r7, %r7, %r7
+        xor         %r8, %r8, %r8
+        xor         %r9, %r9, %r9
+        xor         %r10, %r10, %r10
+        xor         %r11, %r11, %r11
+        xor         %r12, %r12, %r12
+        xor         %r13, %r13, %r13
+        xor         %r14, %r14, %r14
+        xor         %r15, %r15, %r15
+        xor         %r16, %r16, %r16
+        xor         %r17, %r17, %r17
+        xor         %r18, %r18, %r18
+        xor         %r19, %r19, %r19
+        xor         %r20, %r20, %r20
+        xor         %r21, %r21, %r21
+        xor         %r22, %r22, %r22
+        xor         %r23, %r23, %r23
+        xor         %r24, %r24, %r24
+        xor         %r25, %r25, %r25
+        xor         %r26, %r26, %r26
+        xor         %r27, %r27, %r27
+        xor         %r28, %r28, %r28
+        xor         %r29, %r29, %r29
+        xor         %r30, %r30, %r30
+        xor         %r31, %r31, %r31
+        lis         %r4, __ram_start__@h
+        ori         %r4, %r4, __ram_start__@l
+        lis         %r5, __ram_end__@h
+        ori         %r5, %r5, __ram_end__@l
+.cleareccloop:
+        cmpl        %cr0, %r4, %r5
+        bge         %cr0, .cleareccend
+        stmw        %r16, 0(%r4)
+        addi        %r4, %r4, 64
+        b           .cleareccloop
+.cleareccend:
+
+        /*
+         * Branch prediction enabled.
+         */
+        li          %r3, BOOT_BUCSR_DEFAULT
+        mtspr       1013, %r3       /* BUCSR */
+
+        blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        /*
+         * Exception vectors initialization.
+         */
+        .align      2
+_ivinit:
+        /* MSR initialization.*/
+        lis         %r3, BOOT_MSR_DEFAULT@h
+        ori         %r3, %r3, BOOT_MSR_DEFAULT@l
+        mtMSR       %r3
+
+        /* IVPR initialization.*/
+        lis         %r3, __ivpr_base__@h
+        ori         %r3, %r3, __ivpr_base__@l
+        mtIVPR      %r3
+
+        blr
+
+        .section    .ivors, "ax"
+
+        .globl      IVORS
+IVORS:
+IVOR0:  b           IVOR0
+        .align      4
+IVOR1:  b           _IVOR1
+        .align      4
+IVOR2:  b           _IVOR2
+        .align      4
+IVOR3:  b           _IVOR3
+        .align      4
+IVOR4:  b           _IVOR4
+        .align      4
+IVOR5:  b           _IVOR5
+        .align      4
+IVOR6:  b           _IVOR6
+        .align      4
+IVOR7:  b           _IVOR7
+        .align      4
+IVOR8:  b           _IVOR8
+        .align      4
+IVOR9:  b           _IVOR9
+        .align      4
+IVOR10: b           _IVOR10
+        .align      4
+IVOR11: b           _IVOR11
+        .align      4
+IVOR12: b           _IVOR12
+        .align      4
+IVOR13: b           _IVOR13
+        .align      4
+IVOR14: b           _IVOR14
+        .align      4
+IVOR15: b           _IVOR15
+
+        .section    .handlers, "ax"
+
+        /*
+         * Default IVOR handlers.
+         */
+        .align      2
+        .weak       _IVOR0,  _IVOR1,  _IVOR2,  _IVOR3,  _IVOR4,  _IVOR5
+        .weak       _IVOR6,  _IVOR7,  _IVOR8,  _IVOR9,  _IVOR10, _IVOR11
+        .weak       _IVOR12, _IVOR13, _IVOR14, _IVOR15
+        .weak       _unhandled_exception
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+_unhandled_exception:
+        b           _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h b/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h
new file mode 100644
index 000000000..5b29a80c8
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC560BCxx/ppcparams.h
+ * @brief   PowerPC parameters for the SPC560BCxx.
+ *
+ * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ *          SPC560BCxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief   PPC core model.
+ */
+#define PPC_VARIANT                 PPC_VARIANT_e200z0
+
+/**
+ * @brief   Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS               20
+
+/**
+ * @brief   IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS          FALSE
+
+/**
+ * @brief   Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE          FALSE
+
+/**
+ * @brief   VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE            TRUE
+
+/**
+ * @brief   Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI      TRUE
+
+/**
+ * @brief   Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER    FALSE
+
+/**
+ * @brief   Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS             217
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Bxx/boot.h b/os/common/ports/e200/devices/SPC560Bxx/boot.h
new file mode 100644
index 000000000..7e60b8f78
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560Bxx/boot.h
@@ -0,0 +1,118 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    boot.h
+ * @brief   Boot parameters for the SPC560Bxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN              0x00000001
+#define BUCSR_BALLOC_BFI        0x00000200
+/** @} */
+
+/**
+ * @name   MSR register definitions
+ * @{
+ */
+#define MSR_WE                  0x00040000
+#define MSR_CE                  0x00020000
+#define MSR_EE                  0x00008000
+#define MSR_PR                  0x00004000
+#define MSR_ME                  0x00001000
+#define MSR_DE                  0x00000200
+#define MSR_IS                  0x00000020
+#define MSR_DS                  0x00000010
+#define MSR_RI                  0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT      (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT        (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT  1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE            1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM    0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Bxx/boot.s b/os/common/ports/e200/devices/SPC560Bxx/boot.s
new file mode 100644
index 000000000..86600aac2
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560Bxx/boot.s
@@ -0,0 +1,214 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    SPC560Bxx/boot.s
+ * @brief   SPC560Bxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+        /* BAM record.*/
+        .section    .boot, "ax"
+
+        .long       0x015A0000
+        .long       _reset_address
+
+        .align      2
+        .globl      _reset_address
+        .type       _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+        bl          _coreinit
+#endif
+        bl          _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+        /*
+         * Image relocation in RAM.
+         */
+        lis         %r4, __ram_reloc_start__@h
+        ori         %r4, %r4, __ram_reloc_start__@l
+        lis         %r5, __ram_reloc_dest__@h
+        ori         %r5, %r5, __ram_reloc_dest__@l
+        lis         %r6, __ram_reloc_end__@h
+        ori         %r6, %r6, __ram_reloc_end__@l
+.relloop:
+        cmpl        cr0, %r4, %r6
+        bge         cr0, .relend
+        lwz         %r7, 0(%r4)
+        addi        %r4, %r4, 4
+        stw         %r7, 0(%r5)
+        addi        %r5, %r5, 4
+        b           .relloop
+.relend:
+        lis         %r3, _boot_address@h
+        ori         %r3, %r3, _boot_address@l
+        mtctr       %r3
+        bctrl
+#else
+        b           _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+        .align      2
+_coreinit:
+        /*
+         * RAM clearing, this device requires a write to all RAM location in
+         * order to initialize the ECC detection hardware, this is going to
+         * slow down the startup but there is no way around.
+         */
+        xor         %r0, %r0, %r0
+        xor         %r1, %r1, %r1
+        xor         %r2, %r2, %r2
+        xor         %r3, %r3, %r3
+        xor         %r4, %r4, %r4
+        xor         %r5, %r5, %r5
+        xor         %r6, %r6, %r6
+        xor         %r7, %r7, %r7
+        xor         %r8, %r8, %r8
+        xor         %r9, %r9, %r9
+        xor         %r10, %r10, %r10
+        xor         %r11, %r11, %r11
+        xor         %r12, %r12, %r12
+        xor         %r13, %r13, %r13
+        xor         %r14, %r14, %r14
+        xor         %r15, %r15, %r15
+        xor         %r16, %r16, %r16
+        xor         %r17, %r17, %r17
+        xor         %r18, %r18, %r18
+        xor         %r19, %r19, %r19
+        xor         %r20, %r20, %r20
+        xor         %r21, %r21, %r21
+        xor         %r22, %r22, %r22
+        xor         %r23, %r23, %r23
+        xor         %r24, %r24, %r24
+        xor         %r25, %r25, %r25
+        xor         %r26, %r26, %r26
+        xor         %r27, %r27, %r27
+        xor         %r28, %r28, %r28
+        xor         %r29, %r29, %r29
+        xor         %r30, %r30, %r30
+        xor         %r31, %r31, %r31
+        lis         %r4, __ram_start__@h
+        ori         %r4, %r4, __ram_start__@l
+        lis         %r5, __ram_end__@h
+        ori         %r5, %r5, __ram_end__@l
+.cleareccloop:
+        cmpl        %cr0, %r4, %r5
+        bge         %cr0, .cleareccend
+        stmw        %r16, 0(%r4)
+        addi        %r4, %r4, 64
+        b           .cleareccloop
+.cleareccend:
+
+        /*
+         * Branch prediction enabled.
+         */
+        li          %r3, BOOT_BUCSR_DEFAULT
+        mtspr       1013, %r3       /* BUCSR */
+
+        blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        /*
+         * Exception vectors initialization.
+         */
+        .align      2
+_ivinit:
+        /* MSR initialization.*/
+        lis         %r3, BOOT_MSR_DEFAULT@h
+        ori         %r3, %r3, BOOT_MSR_DEFAULT@l
+        mtMSR       %r3
+
+        /* IVPR initialization.*/
+        lis         %r3, __ivpr_base__@h
+        ori         %r3, %r3, __ivpr_base__@l
+        mtIVPR      %r3
+
+        blr
+
+        .section    .ivors, "ax"
+
+        .globl      IVORS
+IVORS:
+IVOR0:  b           IVOR0
+        .align      4
+IVOR1:  b           _IVOR1
+        .align      4
+IVOR2:  b           _IVOR2
+        .align      4
+IVOR3:  b           _IVOR3
+        .align      4
+IVOR4:  b           _IVOR4
+        .align      4
+IVOR5:  b           _IVOR5
+        .align      4
+IVOR6:  b           _IVOR6
+        .align      4
+IVOR7:  b           _IVOR7
+        .align      4
+IVOR8:  b           _IVOR8
+        .align      4
+IVOR9:  b           _IVOR9
+        .align      4
+IVOR10: b           _IVOR10
+        .align      4
+IVOR11: b           _IVOR11
+        .align      4
+IVOR12: b           _IVOR12
+        .align      4
+IVOR13: b           _IVOR13
+        .align      4
+IVOR14: b           _IVOR14
+        .align      4
+IVOR15: b           _IVOR15
+
+        .section    .handlers, "ax"
+
+        /*
+         * Default IVOR handlers.
+         */
+        .align      2
+        .weak       _IVOR0,  _IVOR1,  _IVOR2,  _IVOR3,  _IVOR4,  _IVOR5
+        .weak       _IVOR6,  _IVOR7,  _IVOR8,  _IVOR9,  _IVOR10, _IVOR11
+        .weak       _IVOR12, _IVOR13, _IVOR14, _IVOR15
+        .weak       _unhandled_exception
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+_unhandled_exception:
+        b           _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h b/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h
new file mode 100644
index 000000000..451971b61
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC560Bxx/ppcparams.h
+ * @brief   PowerPC parameters for the SPC560Bxx.
+ *
+ * @defgroup PPC_SPC560Bxx SPC560Bxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ *          SPC560Bxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief   PPC core model.
+ */
+#define PPC_VARIANT                 PPC_VARIANT_e200z0
+
+/**
+ * @brief   Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS               20
+
+/**
+ * @brief   IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS          FALSE
+
+/**
+ * @brief   Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE          FALSE
+
+/**
+ * @brief   VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE            TRUE
+
+/**
+ * @brief   Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI      TRUE
+
+/**
+ * @brief   Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER    FALSE
+
+/**
+ * @brief   Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS             234
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Dxx/boot.h b/os/common/ports/e200/devices/SPC560Dxx/boot.h
new file mode 100644
index 000000000..bb51eebda
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560Dxx/boot.h
@@ -0,0 +1,118 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    boot.h
+ * @brief   Boot parameters for the SPC560Dxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN              0x00000001
+#define BUCSR_BALLOC_BFI        0x00000200
+/** @} */
+
+/**
+ * @name   MSR register definitions
+ * @{
+ */
+#define MSR_WE                  0x00040000
+#define MSR_CE                  0x00020000
+#define MSR_EE                  0x00008000
+#define MSR_PR                  0x00004000
+#define MSR_ME                  0x00001000
+#define MSR_DE                  0x00000200
+#define MSR_IS                  0x00000020
+#define MSR_DS                  0x00000010
+#define MSR_RI                  0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT      (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT        (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT  1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE            1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM    0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Dxx/boot.s b/os/common/ports/e200/devices/SPC560Dxx/boot.s
new file mode 100644
index 000000000..520cdf41a
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560Dxx/boot.s
@@ -0,0 +1,214 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    SPC560Dxx/boot.s
+ * @brief   SPC560Dxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+        /* BAM record.*/
+        .section    .boot, "ax"
+
+        .long       0x015A0000
+        .long       _reset_address
+
+        .align      2
+        .globl      _reset_address
+        .type       _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+        bl          _coreinit
+#endif
+        bl          _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+        /*
+         * Image relocation in RAM.
+         */
+        lis         %r4, __ram_reloc_start__@h
+        ori         %r4, %r4, __ram_reloc_start__@l
+        lis         %r5, __ram_reloc_dest__@h
+        ori         %r5, %r5, __ram_reloc_dest__@l
+        lis         %r6, __ram_reloc_end__@h
+        ori         %r6, %r6, __ram_reloc_end__@l
+.relloop:
+        cmpl        cr0, %r4, %r6
+        bge         cr0, .relend
+        lwz         %r7, 0(%r4)
+        addi        %r4, %r4, 4
+        stw         %r7, 0(%r5)
+        addi        %r5, %r5, 4
+        b           .relloop
+.relend:
+        lis         %r3, _boot_address@h
+        ori         %r3, %r3, _boot_address@l
+        mtctr       %r3
+        bctrl
+#else
+        b           _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+        .align      2
+_coreinit:
+        /*
+         * RAM clearing, this device requires a write to all RAM location in
+         * order to initialize the ECC detection hardware, this is going to
+         * slow down the startup but there is no way around.
+         */
+        xor         %r0, %r0, %r0
+        xor         %r1, %r1, %r1
+        xor         %r2, %r2, %r2
+        xor         %r3, %r3, %r3
+        xor         %r4, %r4, %r4
+        xor         %r5, %r5, %r5
+        xor         %r6, %r6, %r6
+        xor         %r7, %r7, %r7
+        xor         %r8, %r8, %r8
+        xor         %r9, %r9, %r9
+        xor         %r10, %r10, %r10
+        xor         %r11, %r11, %r11
+        xor         %r12, %r12, %r12
+        xor         %r13, %r13, %r13
+        xor         %r14, %r14, %r14
+        xor         %r15, %r15, %r15
+        xor         %r16, %r16, %r16
+        xor         %r17, %r17, %r17
+        xor         %r18, %r18, %r18
+        xor         %r19, %r19, %r19
+        xor         %r20, %r20, %r20
+        xor         %r21, %r21, %r21
+        xor         %r22, %r22, %r22
+        xor         %r23, %r23, %r23
+        xor         %r24, %r24, %r24
+        xor         %r25, %r25, %r25
+        xor         %r26, %r26, %r26
+        xor         %r27, %r27, %r27
+        xor         %r28, %r28, %r28
+        xor         %r29, %r29, %r29
+        xor         %r30, %r30, %r30
+        xor         %r31, %r31, %r31
+        lis         %r4, __ram_start__@h
+        ori         %r4, %r4, __ram_start__@l
+        lis         %r5, __ram_end__@h
+        ori         %r5, %r5, __ram_end__@l
+.cleareccloop:
+        cmpl        %cr0, %r4, %r5
+        bge         %cr0, .cleareccend
+        stmw        %r16, 0(%r4)
+        addi        %r4, %r4, 64
+        b           .cleareccloop
+.cleareccend:
+
+        /*
+         * Branch prediction enabled.
+         */
+        li          %r3, BOOT_BUCSR_DEFAULT
+        mtspr       1013, %r3       /* BUCSR */
+
+        blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        /*
+         * Exception vectors initialization.
+         */
+        .align      2
+_ivinit:
+        /* MSR initialization.*/
+        lis         %r3, BOOT_MSR_DEFAULT@h
+        ori         %r3, %r3, BOOT_MSR_DEFAULT@l
+        mtMSR       %r3
+
+        /* IVPR initialization.*/
+        lis         %r3, __ivpr_base__@h
+        ori         %r3, %r3, __ivpr_base__@l
+        mtIVPR      %r3
+
+        blr
+
+        .section    .ivors, "ax"
+
+        .globl      IVORS
+IVORS:
+IVOR0:  b           IVOR0
+        .align      4
+IVOR1:  b           _IVOR1
+        .align      4
+IVOR2:  b           _IVOR2
+        .align      4
+IVOR3:  b           _IVOR3
+        .align      4
+IVOR4:  b           _IVOR4
+        .align      4
+IVOR5:  b           _IVOR5
+        .align      4
+IVOR6:  b           _IVOR6
+        .align      4
+IVOR7:  b           _IVOR7
+        .align      4
+IVOR8:  b           _IVOR8
+        .align      4
+IVOR9:  b           _IVOR9
+        .align      4
+IVOR10: b           _IVOR10
+        .align      4
+IVOR11: b           _IVOR11
+        .align      4
+IVOR12: b           _IVOR12
+        .align      4
+IVOR13: b           _IVOR13
+        .align      4
+IVOR14: b           _IVOR14
+        .align      4
+IVOR15: b           _IVOR15
+
+        .section    .handlers, "ax"
+
+        /*
+         * Default IVOR handlers.
+         */
+        .align      2
+        .weak       _IVOR0,  _IVOR1,  _IVOR2,  _IVOR3,  _IVOR4,  _IVOR5
+        .weak       _IVOR6,  _IVOR7,  _IVOR8,  _IVOR9,  _IVOR10, _IVOR11
+        .weak       _IVOR12, _IVOR13, _IVOR14, _IVOR15
+        .weak       _unhandled_exception
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+_unhandled_exception:
+        b           _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h b/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h
new file mode 100644
index 000000000..51f6824b7
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC560Dxx/ppcparams.h
+ * @brief   PowerPC parameters for the SPC560Dxx.
+ *
+ * @defgroup PPC_SPC560Dxx SPC560Dxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ *          SPC560Dxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief   PPC core model.
+ */
+#define PPC_VARIANT                 PPC_VARIANT_e200z0
+
+/**
+ * @brief   Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS               20
+
+/**
+ * @brief   IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS          FALSE
+
+/**
+ * @brief   Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE          FALSE
+
+/**
+ * @brief   VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE            TRUE
+
+/**
+ * @brief   Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI      TRUE
+
+/**
+ * @brief   Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER    FALSE
+
+/**
+ * @brief   Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS             155
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Pxx/boot.h b/os/common/ports/e200/devices/SPC560Pxx/boot.h
new file mode 100644
index 000000000..56bc4a565
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560Pxx/boot.h
@@ -0,0 +1,118 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    boot.h
+ * @brief   Boot parameters for the SPC560Pxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN              0x00000001
+#define BUCSR_BALLOC_BFI        0x00000200
+/** @} */
+
+/**
+ * @name   MSR register definitions
+ * @{
+ */
+#define MSR_WE                  0x00040000
+#define MSR_CE                  0x00020000
+#define MSR_EE                  0x00008000
+#define MSR_PR                  0x00004000
+#define MSR_ME                  0x00001000
+#define MSR_DE                  0x00000200
+#define MSR_IS                  0x00000020
+#define MSR_DS                  0x00000010
+#define MSR_RI                  0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT      (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT        (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT  1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE            1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM    0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Pxx/boot.s b/os/common/ports/e200/devices/SPC560Pxx/boot.s
new file mode 100644
index 000000000..bbeab7dcd
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560Pxx/boot.s
@@ -0,0 +1,214 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    SPC560Pxx/boot.s
+ * @brief   SPC560Pxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+        /* BAM record.*/
+        .section    .boot, "ax"
+
+        .long       0x015A0000
+        .long       _reset_address
+
+        .align      2
+        .globl      _reset_address
+        .type       _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+        bl          _coreinit
+#endif
+        bl          _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+        /*
+         * Image relocation in RAM.
+         */
+        lis         %r4, __ram_reloc_start__@h
+        ori         %r4, %r4, __ram_reloc_start__@l
+        lis         %r5, __ram_reloc_dest__@h
+        ori         %r5, %r5, __ram_reloc_dest__@l
+        lis         %r6, __ram_reloc_end__@h
+        ori         %r6, %r6, __ram_reloc_end__@l
+.relloop:
+        cmpl        cr0, %r4, %r6
+        bge         cr0, .relend
+        lwz         %r7, 0(%r4)
+        addi        %r4, %r4, 4
+        stw         %r7, 0(%r5)
+        addi        %r5, %r5, 4
+        b           .relloop
+.relend:
+        lis         %r3, _boot_address@h
+        ori         %r3, %r3, _boot_address@l
+        mtctr       %r3
+        bctrl
+#else
+        b           _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+        .align      2
+_coreinit:
+        /*
+         * RAM clearing, this device requires a write to all RAM location in
+         * order to initialize the ECC detection hardware, this is going to
+         * slow down the startup but there is no way around.
+         */
+        xor         %r0, %r0, %r0
+        xor         %r1, %r1, %r1
+        xor         %r2, %r2, %r2
+        xor         %r3, %r3, %r3
+        xor         %r4, %r4, %r4
+        xor         %r5, %r5, %r5
+        xor         %r6, %r6, %r6
+        xor         %r7, %r7, %r7
+        xor         %r8, %r8, %r8
+        xor         %r9, %r9, %r9
+        xor         %r10, %r10, %r10
+        xor         %r11, %r11, %r11
+        xor         %r12, %r12, %r12
+        xor         %r13, %r13, %r13
+        xor         %r14, %r14, %r14
+        xor         %r15, %r15, %r15
+        xor         %r16, %r16, %r16
+        xor         %r17, %r17, %r17
+        xor         %r18, %r18, %r18
+        xor         %r19, %r19, %r19
+        xor         %r20, %r20, %r20
+        xor         %r21, %r21, %r21
+        xor         %r22, %r22, %r22
+        xor         %r23, %r23, %r23
+        xor         %r24, %r24, %r24
+        xor         %r25, %r25, %r25
+        xor         %r26, %r26, %r26
+        xor         %r27, %r27, %r27
+        xor         %r28, %r28, %r28
+        xor         %r29, %r29, %r29
+        xor         %r30, %r30, %r30
+        xor         %r31, %r31, %r31
+        lis         %r4, __ram_start__@h
+        ori         %r4, %r4, __ram_start__@l
+        lis         %r5, __ram_end__@h
+        ori         %r5, %r5, __ram_end__@l
+.cleareccloop:
+        cmpl        %cr0, %r4, %r5
+        bge         %cr0, .cleareccend
+        stmw        %r16, 0(%r4)
+        addi        %r4, %r4, 64
+        b           .cleareccloop
+.cleareccend:
+
+        /*
+         * Branch prediction enabled.
+         */
+        li          %r3, BOOT_BUCSR_DEFAULT
+        mtspr       1013, %r3       /* BUCSR */
+
+        blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        /*
+         * Exception vectors initialization.
+         */
+        .align      2
+_ivinit:
+        /* MSR initialization.*/
+        lis         %r3, BOOT_MSR_DEFAULT@h
+        ori         %r3, %r3, BOOT_MSR_DEFAULT@l
+        mtMSR       %r3
+
+        /* IVPR initialization.*/
+        lis         %r3, __ivpr_base__@h
+        ori         %r3, %r3, __ivpr_base__@l
+        mtIVPR      %r3
+
+        blr
+
+        .section    .ivors, "ax"
+
+        .globl      IVORS
+IVORS:
+IVOR0:  b           IVOR0
+        .align      4
+IVOR1:  b           _IVOR1
+        .align      4
+IVOR2:  b           _IVOR2
+        .align      4
+IVOR3:  b           _IVOR3
+        .align      4
+IVOR4:  b           _IVOR4
+        .align      4
+IVOR5:  b           _IVOR5
+        .align      4
+IVOR6:  b           _IVOR6
+        .align      4
+IVOR7:  b           _IVOR7
+        .align      4
+IVOR8:  b           _IVOR8
+        .align      4
+IVOR9:  b           _IVOR9
+        .align      4
+IVOR10: b           _IVOR10
+        .align      4
+IVOR11: b           _IVOR11
+        .align      4
+IVOR12: b           _IVOR12
+        .align      4
+IVOR13: b           _IVOR13
+        .align      4
+IVOR14: b           _IVOR14
+        .align      4
+IVOR15: b           _IVOR15
+
+        .section    .handlers, "ax"
+
+        /*
+         * Default IVOR handlers.
+         */
+        .align      2
+        .weak       _IVOR0,  _IVOR1,  _IVOR2,  _IVOR3,  _IVOR4,  _IVOR5
+        .weak       _IVOR6,  _IVOR7,  _IVOR8,  _IVOR9,  _IVOR10, _IVOR11
+        .weak       _IVOR12, _IVOR13, _IVOR14, _IVOR15
+        .weak       _unhandled_exception
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+_unhandled_exception:
+        b           _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Pxx/ppcparams.h b/os/common/ports/e200/devices/SPC560Pxx/ppcparams.h
new file mode 100644
index 000000000..83cc43a75
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC560Pxx/ppcparams.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC560Pxx/ppcparams.h
+ * @brief   PowerPC parameters for the SPC560Pxx.
+ *
+ * @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ *          SPC560Pxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief   PPC core model.
+ */
+#define PPC_VARIANT                 PPC_VARIANT_e200z0
+
+/**
+ * @brief   Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS               20
+
+/**
+ * @brief   IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS          FALSE
+
+/**
+ * @brief   Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE          FALSE
+
+/**
+ * @brief   VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE            TRUE
+
+/**
+ * @brief   Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI      TRUE
+
+/**
+ * @brief   Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER    FALSE
+
+/**
+ * @brief   Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS             261
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC563Mxx/boot.h b/os/common/ports/e200/devices/SPC563Mxx/boot.h
new file mode 100644
index 000000000..52bee9f45
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC563Mxx/boot.h
@@ -0,0 +1,119 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    boot.h
+ * @brief   Boot parameters for the SPC563Mxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN              0x00000001
+#define BUCSR_BALLOC_BFI        0x00000200
+/** @} */
+
+/**
+ * @name   MSR register definitions
+ * @{
+ */
+#define MSR_UCLE                0x04000000
+#define MSR_SPE                 0x02000000
+#define MSR_WE                  0x00040000
+#define MSR_CE                  0x00020000
+#define MSR_EE                  0x00008000
+#define MSR_PR                  0x00004000
+#define MSR_FP                  0x00002000
+#define MSR_ME                  0x00001000
+#define MSR_FE0                 0x00000800
+#define MSR_DE                  0x00000200
+#define MSR_FE1                 0x00000100
+#define MSR_IS                  0x00000020
+#define MSR_DS                  0x00000010
+#define MSR_RI                  0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT      (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT        (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT  1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE            1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM    0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC563Mxx/boot.s b/os/common/ports/e200/devices/SPC563Mxx/boot.s
new file mode 100644
index 000000000..7b9dc0e10
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC563Mxx/boot.s
@@ -0,0 +1,188 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    SPC563Mxx/boot.s
+ * @brief   SPC563Mxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+        /* BAM record.*/
+        .section    .boot, "ax"
+
+#if BOOT_USE_VLE
+        .long       0x015A0000
+#else
+        .long       0x005A0000
+#endif
+        .long       _reset_address
+
+        .align      2
+        .globl      _reset_address
+        .type       _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+        bl          _coreinit
+#endif
+        bl          _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+        /*
+         * Image relocation in RAM.
+         */
+        lis         %r4, __ram_reloc_start__@h
+        ori         %r4, %r4, __ram_reloc_start__@l
+        lis         %r5, __ram_reloc_dest__@h
+        ori         %r5, %r5, __ram_reloc_dest__@l
+        lis         %r6, __ram_reloc_end__@h
+        ori         %r6, %r6, __ram_reloc_end__@l
+.relloop:
+        cmpl        cr0, %r4, %r6
+        bge         cr0, .relend
+        lwz         %r7, 0(%r4)
+        addi        %r4, %r4, 4
+        stw         %r7, 0(%r5)
+        addi        %r5, %r5, 4
+        b           .relloop
+.relend:
+        lis         %r3, _boot_address@h
+        ori         %r3, %r3, _boot_address@l
+        mtctr       %r3
+        bctrl
+#else
+        b           _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+        .align      2
+_coreinit:
+        /*
+         * RAM clearing, this device requires a write to all RAM location in
+         * order to initialize the ECC detection hardware, this is going to
+         * slow down the startup but there is no way around.
+         */
+        xor         %r0, %r0, %r0
+        xor         %r1, %r1, %r1
+        xor         %r2, %r2, %r2
+        xor         %r3, %r3, %r3
+        xor         %r4, %r4, %r4
+        xor         %r5, %r5, %r5
+        xor         %r6, %r6, %r6
+        xor         %r7, %r7, %r7
+        xor         %r8, %r8, %r8
+        xor         %r9, %r9, %r9
+        xor         %r10, %r10, %r10
+        xor         %r11, %r11, %r11
+        xor         %r12, %r12, %r12
+        xor         %r13, %r13, %r13
+        xor         %r14, %r14, %r14
+        xor         %r15, %r15, %r15
+        xor         %r16, %r16, %r16
+        xor         %r17, %r17, %r17
+        xor         %r18, %r18, %r18
+        xor         %r19, %r19, %r19
+        xor         %r20, %r20, %r20
+        xor         %r21, %r21, %r21
+        xor         %r22, %r22, %r22
+        xor         %r23, %r23, %r23
+        xor         %r24, %r24, %r24
+        xor         %r25, %r25, %r25
+        xor         %r26, %r26, %r26
+        xor         %r27, %r27, %r27
+        xor         %r28, %r28, %r28
+        xor         %r29, %r29, %r29
+        xor         %r30, %r30, %r30
+        xor         %r31, %r31, %r31
+        lis         %r4, __ram_start__@h
+        ori         %r4, %r4, __ram_start__@l
+        lis         %r5, __ram_end__@h
+        ori         %r5, %r5, __ram_end__@l
+.cleareccloop:
+        cmpl        %cr0, %r4, %r5
+        bge         %cr0, .cleareccend
+        stmw        %r16, 0(%r4)
+        addi        %r4, %r4, 64
+        b           .cleareccloop
+.cleareccend:
+
+        /*
+         * Branch prediction enabled.
+         */
+        li          %r3, BOOT_BUCSR_DEFAULT
+        mtspr       1013, %r3       /* BUCSR */
+
+        blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        /*
+         * Exception vectors initialization.
+         */
+_ivinit:
+        /* MSR initialization.*/
+        lis         %r3, BOOT_MSR_DEFAULT@h
+        ori         %r3, %r3, BOOT_MSR_DEFAULT@l
+        mtMSR       %r3
+
+        /* IVPR initialization.*/
+        lis         %r3, __ivpr_base__@h
+        ori         %r3, %r3, __ivpr_base__@l
+        mtIVPR      %r3
+
+        /* IVORs initialization.*/
+        lis         %r3, _unhandled_exception@h
+        ori         %r3, %r3, _unhandled_exception@l
+
+        mtspr       400, %r3        /* IVOR0-15 */
+        mtspr       401, %r3
+        mtspr       402, %r3
+        mtspr       403, %r3
+        mtspr       404, %r3
+        mtspr       405, %r3
+        mtspr       406, %r3
+        mtspr       407, %r3
+        mtspr       408, %r3
+        mtspr       409, %r3
+        mtspr       410, %r3
+        mtspr       411, %r3
+        mtspr       412, %r3
+        mtspr       413, %r3
+        mtspr       414, %r3
+        mtspr       415, %r3
+        mtspr       528, %r3        /* IVOR32-34 */
+        mtspr       529, %r3
+        mtspr       530, %r3
+
+        blr
+
+        .section    .handlers, "ax"
+
+        /*
+         * Unhandled exceptions handler.
+         */
+        .weak       _unhandled_exception
+        .type       _unhandled_exception, @function
+_unhandled_exception:
+        b           _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h b/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h
new file mode 100644
index 000000000..29bc22eb7
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC563Mxx/ppcparams.h
+ * @brief   PowerPC parameters for the SPC563Mxx.
+ *
+ * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ *          SPC563Mxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief   PPC core model.
+ */
+#define PPC_VARIANT                 PPC_VARIANT_e200z3
+
+/**
+ * @brief   Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS               16
+
+/**
+ * @brief   IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS          TRUE
+
+/**
+ * @brief   Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE          TRUE
+
+/**
+ * @brief   VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE            TRUE
+
+/**
+ * @brief   Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI      TRUE
+
+/**
+ * @brief   Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER    TRUE
+
+/**
+ * @brief   Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS             360
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC564Axx/boot.h b/os/common/ports/e200/devices/SPC564Axx/boot.h
new file mode 100644
index 000000000..7b105153a
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC564Axx/boot.h
@@ -0,0 +1,242 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    boot.h
+ * @brief   Boot parameters for the SPC564Axx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name   MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL         0x10000000
+#define MAS0_ESEL_MASK          0x000F0000
+#define MAS0_ESEL(n)            ((n) << 16)
+
+#define MAS1_VALID              0x80000000
+#define MAS1_IPROT              0x40000000
+#define MAS1_TID_MASK           0x00FF0000
+#define MAS1_TS                 0x00001000
+#define MAS1_TSISE_MASK         0x00000F80
+#define MAS1_TSISE_1K           0x00000000
+#define MAS1_TSISE_2K           0x00000080
+#define MAS1_TSISE_4K           0x00000100
+#define MAS1_TSISE_8K           0x00000180
+#define MAS1_TSISE_16K          0x00000200
+#define MAS1_TSISE_32K          0x00000280
+#define MAS1_TSISE_64K          0x00000300
+#define MAS1_TSISE_128K         0x00000380
+#define MAS1_TSISE_256K         0x00000400
+#define MAS1_TSISE_512K         0x00000480
+#define MAS1_TSISE_1M           0x00000500
+#define MAS1_TSISE_2M           0x00000580
+#define MAS1_TSISE_4M           0x00000600
+#define MAS1_TSISE_8M           0x00000680
+#define MAS1_TSISE_16M          0x00000700
+#define MAS1_TSISE_32M          0x00000780
+#define MAS1_TSISE_64M          0x00000800
+#define MAS1_TSISE_128M         0x00000880
+#define MAS1_TSISE_256M         0x00000900
+#define MAS1_TSISE_512M         0x00000980
+#define MAS1_TSISE_1G           0x00000A00
+#define MAS1_TSISE_2G           0x00000A80
+#define MAS1_TSISE_4G           0x00000B00
+
+#define MAS2_EPN_MASK           0xFFFFFC00
+#define MAS2_EPN(n)             ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK              0x00000000
+#define MAS2_VLE                0x00000020
+#define MAS2_W                  0x00000010
+#define MAS2_I                  0x00000008
+#define MAS2_M                  0x00000004
+#define MAS2_G                  0x00000002
+#define MAS2_E                  0x00000001
+
+#define MAS3_RPN_MASK           0xFFFFFC00
+#define MAS3_RPN(n)             ((n) & MAS3_RPN_MASK)
+#define MAS3_U0                 0x00000200
+#define MAS3_U1                 0x00000100
+#define MAS3_U2                 0x00000080
+#define MAS3_U3                 0x00000040
+#define MAS3_UX                 0x00000020
+#define MAS3_SX                 0x00000010
+#define MAS3_UW                 0x00000008
+#define MAS3_SW                 0x00000004
+#define MAS3_UR                 0x00000002
+#define MAS3_SR                 0x00000001
+/** @} */
+
+/**
+ * @name    BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN              0x00000001
+#define BUCSR_BPRED_MASK        0x00000006
+#define BUCSR_BPRED_0           0x00000000
+#define BUCSR_BPRED_1           0x00000002
+#define BUCSR_BPRED_2           0x00000004
+#define BUCSR_BPRED_3           0x00000006
+#define BUCSR_BALLOC_MASK       0x00000030
+#define BUCSR_BALLOC_0          0x00000000
+#define BUCSR_BALLOC_1          0x00000010
+#define BUCSR_BALLOC_2          0x00000020
+#define BUCSR_BALLOC_3          0x00000030
+#define BUCSR_BALLOC_BFI        0x00000200
+/** @} */
+
+/**
+ * @name    LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE              0x00000001
+#define LICSR1_ICINV            0x00000002
+#define LICSR1_ICORG            0x00000010
+/** @} */
+
+/**
+ * @name   MSR register definitions
+ * @{
+ */
+#define MSR_UCLE                0x04000000
+#define MSR_SPE                 0x02000000
+#define MSR_WE                  0x00040000
+#define MSR_CE                  0x00020000
+#define MSR_EE                  0x00008000
+#define MSR_PR                  0x00004000
+#define MSR_FP                  0x00002000
+#define MSR_ME                  0x00001000
+#define MSR_FE0                 0x00000800
+#define MSR_DE                  0x00000200
+#define MSR_FE1                 0x00000100
+#define MSR_IS                  0x00000020
+#define MSR_DS                  0x00000010
+#define MSR_RI                  0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB0_MAS2               (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB0_MAS3               (MAS3_RPN(0x40000000) |                     \
+                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
+                                 MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
+#define TLB1_MAS2               (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB1_MAS3               (MAS3_RPN(0x00000000) |                     \
+                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
+                                 MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2               (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3               (MAS3_RPN(0xC3F00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2               (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3               (MAS3_RPN(0xFFE00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2               (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB4_MAS3               (MAS3_RPN(0xFFF00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT      (BUCSR_BPEN | BUCSR_BPRED_0 |               \
+                                 BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT     (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT        (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT  1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE            1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM    0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC564Axx/boot.s b/os/common/ports/e200/devices/SPC564Axx/boot.s
new file mode 100644
index 000000000..ef7e4df91
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC564Axx/boot.s
@@ -0,0 +1,353 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    SPC564Axx/boot.s
+ * @brief   SPC564Axx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+        /* BAM record.*/
+        .section    .boot, "ax"
+
+#if BOOT_USE_VLE
+        .long       0x015A0000
+#else
+        .long       0x005A0000
+#endif
+        .long       _reset_address
+
+        .align      2
+        .globl      _reset_address
+        .type       _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+        bl          _coreinit
+#endif
+        bl          _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+        /*
+         * Image relocation in RAM.
+         */
+        lis         %r4, __ram_reloc_start__@h
+        ori         %r4, %r4, __ram_reloc_start__@l
+        lis         %r5, __ram_reloc_dest__@h
+        ori         %r5, %r5, __ram_reloc_dest__@l
+        lis         %r6, __ram_reloc_end__@h
+        ori         %r6, %r6, __ram_reloc_end__@l
+.relloop:
+        cmpl        cr0, %r4, %r6
+        bge         cr0, .relend
+        lwz         %r7, 0(%r4)
+        addi        %r4, %r4, 4
+        stw         %r7, 0(%r5)
+        addi        %r5, %r5, 4
+        b           .relloop
+.relend:
+        lis         %r3, _boot_address@h
+        ori         %r3, %r3, _boot_address@l
+        mtctr       %r3
+        bctrl
+#else
+        b           _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+        .align      2
+_ramcode:
+        tlbwe
+        isync
+        blr
+
+        .align      2
+_coreinit:
+        /*
+         * Invalidating all TLBs except TLB1.
+         */
+        lis         %r3, 0
+        mtspr       625, %r3        /* MAS1 */
+        mtspr       626, %r3        /* MAS2 */
+        mtspr       627, %r3        /* MAS3 */
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+
+        /*
+         * TLB0 allocated to internal RAM.
+         */
+        lis         %r3, TLB0_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB0_MAS1@h
+        ori         %r3, %r3, TLB0_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB0_MAS2@h
+        ori         %r3, %r3, TLB0_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB0_MAS3@h
+        ori         %r3, %r3, TLB0_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB2 allocated to internal Peripherals Bridge A.
+         */
+        lis         %r3, TLB2_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB2_MAS1@h
+        ori         %r3, %r3, TLB2_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB2_MAS2@h
+        ori         %r3, %r3, TLB2_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB2_MAS3@h
+        ori         %r3, %r3, TLB2_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB3 allocated to internal Peripherals Bridge B.
+         */
+        lis         %r3, TLB3_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB3_MAS1@h
+        ori         %r3, %r3, TLB3_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB3_MAS2@h
+        ori         %r3, %r3, TLB3_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB3_MAS3@h
+        ori         %r3, %r3, TLB3_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB4 allocated to on-platform peripherals.
+         */
+        lis         %r3, TLB4_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB4_MAS1@h
+        ori         %r3, %r3, TLB4_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB4_MAS2@h
+        ori         %r3, %r3, TLB4_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB4_MAS3@h
+        ori         %r3, %r3, TLB4_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * RAM clearing, this device requires a write to all RAM location in
+         * order to initialize the ECC detection hardware, this is going to
+         * slow down the startup but there is no way around.
+         */
+        xor         %r0, %r0, %r0
+        xor         %r1, %r1, %r1
+        xor         %r2, %r2, %r2
+        xor         %r3, %r3, %r3
+        xor         %r4, %r4, %r4
+        xor         %r5, %r5, %r5
+        xor         %r6, %r6, %r6
+        xor         %r7, %r7, %r7
+        xor         %r8, %r8, %r8
+        xor         %r9, %r9, %r9
+        xor         %r10, %r10, %r10
+        xor         %r11, %r11, %r11
+        xor         %r12, %r12, %r12
+        xor         %r13, %r13, %r13
+        xor         %r14, %r14, %r14
+        xor         %r15, %r15, %r15
+        xor         %r16, %r16, %r16
+        xor         %r17, %r17, %r17
+        xor         %r18, %r18, %r18
+        xor         %r19, %r19, %r19
+        xor         %r20, %r20, %r20
+        xor         %r21, %r21, %r21
+        xor         %r22, %r22, %r22
+        xor         %r23, %r23, %r23
+        xor         %r24, %r24, %r24
+        xor         %r25, %r25, %r25
+        xor         %r26, %r26, %r26
+        xor         %r27, %r27, %r27
+        xor         %r28, %r28, %r28
+        xor         %r29, %r29, %r29
+        xor         %r30, %r30, %r30
+        xor         %r31, %r31, %r31
+        lis         %r4, __ram_start__@h
+        ori         %r4, %r4, __ram_start__@l
+        lis         %r5, __ram_end__@h
+        ori         %r5, %r5, __ram_end__@l
+.cleareccloop:
+        cmpl        %cr0, %r4, %r5
+        bge         %cr0, .cleareccend
+        stmw        %r16, 0(%r4)
+        addi        %r4, %r4, 64
+        b           .cleareccloop
+.cleareccend:
+
+        /*
+         * *Finally* the TLB1 is re-allocated to flash, note, the final phase
+         * is executed from RAM.
+         */
+        lis         %r3, TLB1_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB1_MAS1@h
+        ori         %r3, %r3, TLB1_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB1_MAS2@h
+        ori         %r3, %r3, TLB1_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB1_MAS3@h
+        ori         %r3, %r3, TLB1_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        mflr        %r4
+        lis         %r6, _ramcode@h
+        ori         %r6, %r6, _ramcode@l
+        lis         %r7, 0x40010000@h
+        mtctr       %r7
+        lwz         %r3, 0(%r6)
+        stw         %r3, 0(%r7)
+        lwz         %r3, 4(%r6)
+        stw         %r3, 4(%r7)
+        lwz         %r3, 8(%r6)
+        stw         %r3, 8(%r7)
+        bctrl
+        mtlr        %r4
+
+        /*
+         * Branch prediction enabled.
+         */
+        li          %r3, BOOT_BUCSR_DEFAULT
+        mtspr       1013, %r3       /* BUCSR */
+
+        /*
+         * Cache invalidated and then enabled.
+         */
+        li          %r3, LICSR1_ICINV
+        mtspr       1011, %r3       /* LICSR1 */
+.inv:   mfspr       %r3, 1011       /* LICSR1 */
+        andi.       %r3, %r3, LICSR1_ICINV
+        bne         .inv
+        lis         %r3, BOOT_LICSR1_DEFAULT@h
+        ori         %r3, %r3, BOOT_LICSR1_DEFAULT@l
+        mtspr       1011, %r3       /* LICSR1 */
+
+        blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        /*
+         * Exception vectors initialization.
+         */
+        .align      2
+_ivinit:
+        /* MSR initialization.*/
+        lis         %r3, BOOT_MSR_DEFAULT@h
+        ori         %r3, %r3, BOOT_MSR_DEFAULT@l
+        mtMSR       %r3
+
+        /* IVPR initialization.*/
+        lis         %r3, __ivpr_base__@h
+        ori         %r3, %r3, __ivpr_base__@l
+        mtIVPR      %r3
+
+        /* IVORs initialization.*/
+        lis         %r3, _unhandled_exception@h
+        ori         %r3, %r3, _unhandled_exception@l
+
+        mtspr       400, %r3        /* IVOR0-15 */
+        mtspr       401, %r3
+        mtspr       402, %r3
+        mtspr       403, %r3
+        mtspr       404, %r3
+        mtspr       405, %r3
+        mtspr       406, %r3
+        mtspr       407, %r3
+        mtspr       408, %r3
+        mtspr       409, %r3
+        mtspr       410, %r3
+        mtspr       411, %r3
+        mtspr       412, %r3
+        mtspr       413, %r3
+        mtspr       414, %r3
+        mtspr       415, %r3
+        mtspr       528, %r3        /* IVOR32-34 */
+        mtspr       529, %r3
+        mtspr       530, %r3
+
+        blr
+
+        .section    .handlers, "ax"
+
+        /*
+         * Unhandled exceptions handler.
+         */
+        .weak       _unhandled_exception
+        .type       _unhandled_exception, @function
+_unhandled_exception:
+        b           _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC564Axx/ppcparams.h b/os/common/ports/e200/devices/SPC564Axx/ppcparams.h
new file mode 100644
index 000000000..badc1a83b
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC564Axx/ppcparams.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC564Axx/ppcparams.h
+ * @brief   PowerPC parameters for the SPC564Axx.
+ *
+ * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ *          SPC564Axx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief   PPC core model.
+ */
+#define PPC_VARIANT                 PPC_VARIANT_e200z4
+
+/**
+ * @brief   Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS               16
+
+/**
+ * @brief   IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS          TRUE
+
+/**
+ * @brief   Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE          TRUE
+
+/**
+ * @brief   VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE            TRUE
+
+/**
+ * @brief   Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI      TRUE
+
+/**
+ * @brief   Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER    TRUE
+
+/**
+ * @brief   Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS             486
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ECxx/boot.h b/os/common/ports/e200/devices/SPC56ECxx/boot.h
new file mode 100644
index 000000000..74d0cfe90
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC56ECxx/boot.h
@@ -0,0 +1,252 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    boot.h
+ * @brief   Boot parameters for the SPC56ECxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name   MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL         0x10000000
+#define MAS0_ESEL_MASK          0x000F0000
+#define MAS0_ESEL(n)            ((n) << 16)
+
+#define MAS1_VALID              0x80000000
+#define MAS1_IPROT              0x40000000
+#define MAS1_TID_MASK           0x00FF0000
+#define MAS1_TS                 0x00001000
+#define MAS1_TSISE_MASK         0x00000F80
+#define MAS1_TSISE_1K           0x00000000
+#define MAS1_TSISE_2K           0x00000080
+#define MAS1_TSISE_4K           0x00000100
+#define MAS1_TSISE_8K           0x00000180
+#define MAS1_TSISE_16K          0x00000200
+#define MAS1_TSISE_32K          0x00000280
+#define MAS1_TSISE_64K          0x00000300
+#define MAS1_TSISE_128K         0x00000380
+#define MAS1_TSISE_256K         0x00000400
+#define MAS1_TSISE_512K         0x00000480
+#define MAS1_TSISE_1M           0x00000500
+#define MAS1_TSISE_2M           0x00000580
+#define MAS1_TSISE_4M           0x00000600
+#define MAS1_TSISE_8M           0x00000680
+#define MAS1_TSISE_16M          0x00000700
+#define MAS1_TSISE_32M          0x00000780
+#define MAS1_TSISE_64M          0x00000800
+#define MAS1_TSISE_128M         0x00000880
+#define MAS1_TSISE_256M         0x00000900
+#define MAS1_TSISE_512M         0x00000980
+#define MAS1_TSISE_1G           0x00000A00
+#define MAS1_TSISE_2G           0x00000A80
+#define MAS1_TSISE_4G           0x00000B00
+
+#define MAS2_EPN_MASK           0xFFFFFC00
+#define MAS2_EPN(n)             ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK              0x00000000
+#define MAS2_VLE                0x00000020
+#define MAS2_W                  0x00000010
+#define MAS2_I                  0x00000008
+#define MAS2_M                  0x00000004
+#define MAS2_G                  0x00000002
+#define MAS2_E                  0x00000001
+
+#define MAS3_RPN_MASK           0xFFFFFC00
+#define MAS3_RPN(n)             ((n) & MAS3_RPN_MASK)
+#define MAS3_U0                 0x00000200
+#define MAS3_U1                 0x00000100
+#define MAS3_U2                 0x00000080
+#define MAS3_U3                 0x00000040
+#define MAS3_UX                 0x00000020
+#define MAS3_SX                 0x00000010
+#define MAS3_UW                 0x00000008
+#define MAS3_SW                 0x00000004
+#define MAS3_UR                 0x00000002
+#define MAS3_SR                 0x00000001
+/** @} */
+
+/**
+ * @name    BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN              0x00000001
+#define BUCSR_BPRED_MASK        0x00000006
+#define BUCSR_BPRED_0           0x00000000
+#define BUCSR_BPRED_1           0x00000002
+#define BUCSR_BPRED_2           0x00000004
+#define BUCSR_BPRED_3           0x00000006
+#define BUCSR_BALLOC_MASK       0x00000030
+#define BUCSR_BALLOC_0          0x00000000
+#define BUCSR_BALLOC_1          0x00000010
+#define BUCSR_BALLOC_2          0x00000020
+#define BUCSR_BALLOC_3          0x00000030
+#define BUCSR_BALLOC_BFI        0x00000200
+/** @} */
+
+/**
+ * @name    LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE              0x00000001
+#define LICSR1_ICINV            0x00000002
+#define LICSR1_ICORG            0x00000010
+/** @} */
+
+/**
+ * @name   MSR register definitions
+ * @{
+ */
+#define MSR_UCLE                0x04000000
+#define MSR_SPE                 0x02000000
+#define MSR_WE                  0x00040000
+#define MSR_CE                  0x00020000
+#define MSR_EE                  0x00008000
+#define MSR_PR                  0x00004000
+#define MSR_FP                  0x00002000
+#define MSR_ME                  0x00001000
+#define MSR_FE0                 0x00000800
+#define MSR_DE                  0x00000200
+#define MSR_FE1                 0x00000100
+#define MSR_IS                  0x00000020
+#define MSR_DS                  0x00000010
+#define MSR_RI                  0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
+#define TLB0_MAS2               (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB0_MAS3               (MAS3_RPN(0x00000000) |                     \
+                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
+                                 MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB1_MAS2               (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB1_MAS3               (MAS3_RPN(0x40000000) |                     \
+                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
+                                 MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2               (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3               (MAS3_RPN(0xC3F00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2               (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3               (MAS3_RPN(0xFFE00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2               (MAS2_EPN(0x8FF00000) | MAS2_I)
+#define TLB4_MAS3               (MAS3_RPN(0x8FF00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB5_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
+#define TLB5_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB5_MAS2               (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB5_MAS3               (MAS3_RPN(0xFFF00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT      (BUCSR_BPEN | BUCSR_BPRED_0 |               \
+                                 BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT     (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT        (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT  1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE            1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM    0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ECxx/boot.s b/os/common/ports/e200/devices/SPC56ECxx/boot.s
new file mode 100644
index 000000000..10319e6e2
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC56ECxx/boot.s
@@ -0,0 +1,407 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC56ECxx/boot.s
+ * @brief   SPC56ECxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+        /* BAM record.*/
+        .section    .boot, "ax"
+
+#if BOOT_USE_VLE
+        .long       0x015A0000
+#else
+        .long       0x005A0000
+#endif
+        .long       _reset_address
+
+        .align      2
+        .globl      _reset_address
+        .type       _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+        bl          _coreinit
+#endif
+        bl          _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+        /*
+         * Image relocation in RAM.
+         */
+        lis         %r4, __ram_reloc_start__@h
+        ori         %r4, %r4, __ram_reloc_start__@l
+        lis         %r5, __ram_reloc_dest__@h
+        ori         %r5, %r5, __ram_reloc_dest__@l
+        lis         %r6, __ram_reloc_end__@h
+        ori         %r6, %r6, __ram_reloc_end__@l
+.relloop:
+        cmpl        cr0, %r4, %r6
+        bge         cr0, .relend
+        lwz         %r7, 0(%r4)
+        addi        %r4, %r4, 4
+        stw         %r7, 0(%r5)
+        addi        %r5, %r5, 4
+        b           .relloop
+.relend:
+        lis         %r3, _boot_address@h
+        ori         %r3, %r3, _boot_address@l
+        mtctr       %r3
+        bctrl
+#else
+        b           _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+        .align      2
+_ramcode:
+        tlbwe
+        isync
+        blr
+
+        .align      2
+_coreinit:
+        /*
+         * Invalidating all TLBs except TLB0.
+         */
+        lis         %r3, 0
+        mtspr       625, %r3        /* MAS1 */
+        mtspr       626, %r3        /* MAS2 */
+        mtspr       627, %r3        /* MAS3 */
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+
+        /*
+         * TLB1 allocated to internal RAM.
+         */
+        lis         %r3, TLB1_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB1_MAS1@h
+        ori         %r3, %r3, TLB1_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB1_MAS2@h
+        ori         %r3, %r3, TLB1_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB1_MAS3@h
+        ori         %r3, %r3, TLB1_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB2 allocated to internal Peripherals Bridge A.
+         */
+        lis         %r3, TLB2_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB2_MAS1@h
+        ori         %r3, %r3, TLB2_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB2_MAS2@h
+        ori         %r3, %r3, TLB2_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB2_MAS3@h
+        ori         %r3, %r3, TLB2_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB3 allocated to internal Peripherals Bridge B.
+         */
+        lis         %r3, TLB3_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB3_MAS1@h
+        ori         %r3, %r3, TLB3_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB3_MAS2@h
+        ori         %r3, %r3, TLB3_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB3_MAS3@h
+        ori         %r3, %r3, TLB3_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB4 allocated to on-platform peripherals.
+         */
+        lis         %r3, TLB4_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB4_MAS1@h
+        ori         %r3, %r3, TLB4_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB4_MAS2@h
+        ori         %r3, %r3, TLB4_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB4_MAS3@h
+        ori         %r3, %r3, TLB4_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB5 allocated to on-platform peripherals.
+         */
+        lis         %r3, TLB5_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB5_MAS1@h
+        ori         %r3, %r3, TLB5_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB5_MAS2@h
+        ori         %r3, %r3, TLB5_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB5_MAS3@h
+        ori         %r3, %r3, TLB5_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * RAM clearing, this device requires a write to all RAM location in
+         * order to initialize the ECC detection hardware, this is going to
+         * slow down the startup but there is no way around.
+         */
+        xor         %r0, %r0, %r0
+        xor         %r1, %r1, %r1
+        xor         %r2, %r2, %r2
+        xor         %r3, %r3, %r3
+        xor         %r4, %r4, %r4
+        xor         %r5, %r5, %r5
+        xor         %r6, %r6, %r6
+        xor         %r7, %r7, %r7
+        xor         %r8, %r8, %r8
+        xor         %r9, %r9, %r9
+        xor         %r10, %r10, %r10
+        xor         %r11, %r11, %r11
+        xor         %r12, %r12, %r12
+        xor         %r13, %r13, %r13
+        xor         %r14, %r14, %r14
+        xor         %r15, %r15, %r15
+        xor         %r16, %r16, %r16
+        xor         %r17, %r17, %r17
+        xor         %r18, %r18, %r18
+        xor         %r19, %r19, %r19
+        xor         %r20, %r20, %r20
+        xor         %r21, %r21, %r21
+        xor         %r22, %r22, %r22
+        xor         %r23, %r23, %r23
+        xor         %r24, %r24, %r24
+        xor         %r25, %r25, %r25
+        xor         %r26, %r26, %r26
+        xor         %r27, %r27, %r27
+        xor         %r28, %r28, %r28
+        xor         %r29, %r29, %r29
+        xor         %r30, %r30, %r30
+        xor         %r31, %r31, %r31
+        lis         %r4, __ram_start__@h
+        ori         %r4, %r4, __ram_start__@l
+        lis         %r5, __ram_end__@h
+        ori         %r5, %r5, __ram_end__@l
+.cleareccloop:
+        cmpl        %cr0, %r4, %r5
+        bge         %cr0, .cleareccend
+        stmw        %r16, 0(%r4)
+        addi        %r4, %r4, 64
+        b           .cleareccloop
+.cleareccend:
+
+        /*
+         * Special function registers clearing, required in order to avoid
+         * possible problems with lockstep mode.
+         */
+        mtcrf       0xFF, %r31
+        mtspr       9, %r31         /* CTR     */
+        mtspr       22, %r31        /* DEC     */
+        mtspr       26, %r31        /* SRR0-1  */
+        mtspr       27, %r31
+        mtspr       54, %r31        /* DECAR   */
+        mtspr       58, %r31        /* CSRR0-1 */
+        mtspr       59, %r31
+        mtspr       61, %r31        /* DEAR    */
+        mtspr       256, %r31       /* USPRG0  */
+        mtspr       272, %r31       /* SPRG1-7 */
+        mtspr       273, %r31
+        mtspr       274, %r31
+        mtspr       275, %r31
+        mtspr       276, %r31
+        mtspr       277, %r31
+        mtspr       278, %r31
+        mtspr       279, %r31
+        mtspr       285, %r31       /* TBU     */
+        mtspr       284, %r31       /* TBL     */
+#if 0
+        mtspr       318, %r31       /* DVC1-2  */
+        mtspr       319, %r31
+#endif
+        mtspr       562, %r31       /* DBCNT */
+        mtspr       570, %r31       /* MCSRR0  */
+        mtspr       571, %r31       /* MCSRR1  */
+        mtspr       604, %r31       /* SPRG8-9 */
+        mtspr       605, %r31
+
+        /*
+         * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+         * is executed from RAM.
+         */
+        lis         %r3, TLB0_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB0_MAS1@h
+        ori         %r3, %r3, TLB0_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB0_MAS2@h
+        ori         %r3, %r3, TLB0_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB0_MAS3@h
+        ori         %r3, %r3, TLB0_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        mflr        %r4
+        lis         %r6, _ramcode@h
+        ori         %r6, %r6, _ramcode@l
+        lis         %r7, 0x40010000@h
+        mtctr       %r7
+        lwz         %r3, 0(%r6)
+        stw         %r3, 0(%r7)
+        lwz         %r3, 4(%r6)
+        stw         %r3, 4(%r7)
+        lwz         %r3, 8(%r6)
+        stw         %r3, 8(%r7)
+        bctrl
+        mtlr        %r4
+
+        /*
+         * Branch prediction enabled.
+         */
+        li          %r3, BOOT_BUCSR_DEFAULT
+        mtspr       1013, %r3       /* BUCSR */
+
+        /*
+         * Cache invalidated and then enabled.
+         */
+        li          %r3, LICSR1_ICINV
+        mtspr       1011, %r3       /* LICSR1 */
+.inv:   mfspr       %r3, 1011       /* LICSR1 */
+        andi.       %r3, %r3, LICSR1_ICINV
+        bne         .inv
+        lis         %r3, BOOT_LICSR1_DEFAULT@h
+        ori         %r3, %r3, BOOT_LICSR1_DEFAULT@l
+        mtspr       1011, %r3       /* LICSR1 */
+
+        blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        /*
+         * Exception vectors initialization.
+         */
+        .align      2
+_ivinit:
+        /* MSR initialization.*/
+        lis         %r3, BOOT_MSR_DEFAULT@h
+        ori         %r3, %r3, BOOT_MSR_DEFAULT@l
+        mtMSR       %r3
+
+        /* IVPR initialization.*/
+        lis         %r3, __ivpr_base__@h
+        ori         %r3, %r3, __ivpr_base__@l
+        mtIVPR      %r3
+
+        /* IVORs initialization.*/
+        lis         %r3, _unhandled_exception@h
+        ori         %r3, %r3, _unhandled_exception@l
+
+        mtspr       400, %r3        /* IVOR0-15 */
+        mtspr       401, %r3
+        mtspr       402, %r3
+        mtspr       403, %r3
+        mtspr       404, %r3
+        mtspr       405, %r3
+        mtspr       406, %r3
+        mtspr       407, %r3
+        mtspr       408, %r3
+        mtspr       409, %r3
+        mtspr       410, %r3
+        mtspr       411, %r3
+        mtspr       412, %r3
+        mtspr       413, %r3
+        mtspr       414, %r3
+        mtspr       415, %r3
+        mtspr       528, %r3        /* IVOR32-34 */
+        mtspr       529, %r3
+        mtspr       530, %r3
+
+        blr
+
+        .section    .handlers, "ax"
+
+        /*
+         * Unhandled exceptions handler.
+         */
+        .weak       _unhandled_exception
+        .type       _unhandled_exception, @function
+_unhandled_exception:
+        b           _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h b/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h
new file mode 100644
index 000000000..d46216e73
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC56ECxx/ppcparams.h
+ * @brief   PowerPC parameters for the SPC56ECxx.
+ *
+ * @defgroup PPC_SPC56ECxx SPC56ECxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ *          SPC56ECxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief   PPC core model.
+ */
+#define PPC_VARIANT                 PPC_VARIANT_e200z4
+
+/**
+ * @brief   Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS               16
+
+/**
+ * @brief   IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS          TRUE
+
+/**
+ * @brief   Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE          TRUE
+
+/**
+ * @brief   VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE            TRUE
+
+/**
+ * @brief   Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI      TRUE
+
+/**
+ * @brief   Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER    TRUE
+
+/**
+ * @brief   Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS             279
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ELxx/boot.h b/os/common/ports/e200/devices/SPC56ELxx/boot.h
new file mode 100644
index 000000000..9bc54e695
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC56ELxx/boot.h
@@ -0,0 +1,252 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    boot.h
+ * @brief   Boot parameters for the SPC56ELxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name   MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL         0x10000000
+#define MAS0_ESEL_MASK          0x000F0000
+#define MAS0_ESEL(n)            ((n) << 16)
+
+#define MAS1_VALID              0x80000000
+#define MAS1_IPROT              0x40000000
+#define MAS1_TID_MASK           0x00FF0000
+#define MAS1_TS                 0x00001000
+#define MAS1_TSISE_MASK         0x00000F80
+#define MAS1_TSISE_1K           0x00000000
+#define MAS1_TSISE_2K           0x00000080
+#define MAS1_TSISE_4K           0x00000100
+#define MAS1_TSISE_8K           0x00000180
+#define MAS1_TSISE_16K          0x00000200
+#define MAS1_TSISE_32K          0x00000280
+#define MAS1_TSISE_64K          0x00000300
+#define MAS1_TSISE_128K         0x00000380
+#define MAS1_TSISE_256K         0x00000400
+#define MAS1_TSISE_512K         0x00000480
+#define MAS1_TSISE_1M           0x00000500
+#define MAS1_TSISE_2M           0x00000580
+#define MAS1_TSISE_4M           0x00000600
+#define MAS1_TSISE_8M           0x00000680
+#define MAS1_TSISE_16M          0x00000700
+#define MAS1_TSISE_32M          0x00000780
+#define MAS1_TSISE_64M          0x00000800
+#define MAS1_TSISE_128M         0x00000880
+#define MAS1_TSISE_256M         0x00000900
+#define MAS1_TSISE_512M         0x00000980
+#define MAS1_TSISE_1G           0x00000A00
+#define MAS1_TSISE_2G           0x00000A80
+#define MAS1_TSISE_4G           0x00000B00
+
+#define MAS2_EPN_MASK           0xFFFFFC00
+#define MAS2_EPN(n)             ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK              0x00000000
+#define MAS2_VLE                0x00000020
+#define MAS2_W                  0x00000010
+#define MAS2_I                  0x00000008
+#define MAS2_M                  0x00000004
+#define MAS2_G                  0x00000002
+#define MAS2_E                  0x00000001
+
+#define MAS3_RPN_MASK           0xFFFFFC00
+#define MAS3_RPN(n)             ((n) & MAS3_RPN_MASK)
+#define MAS3_U0                 0x00000200
+#define MAS3_U1                 0x00000100
+#define MAS3_U2                 0x00000080
+#define MAS3_U3                 0x00000040
+#define MAS3_UX                 0x00000020
+#define MAS3_SX                 0x00000010
+#define MAS3_UW                 0x00000008
+#define MAS3_SW                 0x00000004
+#define MAS3_UR                 0x00000002
+#define MAS3_SR                 0x00000001
+/** @} */
+
+/**
+ * @name    BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN              0x00000001
+#define BUCSR_BPRED_MASK        0x00000006
+#define BUCSR_BPRED_0           0x00000000
+#define BUCSR_BPRED_1           0x00000002
+#define BUCSR_BPRED_2           0x00000004
+#define BUCSR_BPRED_3           0x00000006
+#define BUCSR_BALLOC_MASK       0x00000030
+#define BUCSR_BALLOC_0          0x00000000
+#define BUCSR_BALLOC_1          0x00000010
+#define BUCSR_BALLOC_2          0x00000020
+#define BUCSR_BALLOC_3          0x00000030
+#define BUCSR_BALLOC_BFI        0x00000200
+/** @} */
+
+/**
+ * @name    LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE              0x00000001
+#define LICSR1_ICINV            0x00000002
+#define LICSR1_ICORG            0x00000010
+/** @} */
+
+/**
+ * @name   MSR register definitions
+ * @{
+ */
+#define MSR_UCLE                0x04000000
+#define MSR_SPE                 0x02000000
+#define MSR_WE                  0x00040000
+#define MSR_CE                  0x00020000
+#define MSR_EE                  0x00008000
+#define MSR_PR                  0x00004000
+#define MSR_FP                  0x00002000
+#define MSR_ME                  0x00001000
+#define MSR_FE0                 0x00000800
+#define MSR_DE                  0x00000200
+#define MSR_FE1                 0x00000100
+#define MSR_IS                  0x00000020
+#define MSR_DS                  0x00000010
+#define MSR_RI                  0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
+#define TLB0_MAS2               (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB0_MAS3               (MAS3_RPN(0x00000000) |                     \
+                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
+                                 MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB1_MAS2               (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB1_MAS3               (MAS3_RPN(0x40000000) |                     \
+                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
+                                 MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2               (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3               (MAS3_RPN(0xC3F00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2               (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3               (MAS3_RPN(0xFFE00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2               (MAS2_EPN(0x8FF00000) | MAS2_I)
+#define TLB4_MAS3               (MAS3_RPN(0x8FF00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB5_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
+#define TLB5_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB5_MAS2               (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB5_MAS3               (MAS3_RPN(0xFFF00000) |                     \
+                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT      (BUCSR_BPEN | BUCSR_BPRED_0 |               \
+                                 BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT     (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT        (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT  1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE            1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM    0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ELxx/boot.s b/os/common/ports/e200/devices/SPC56ELxx/boot.s
new file mode 100644
index 000000000..2a6c57f2c
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC56ELxx/boot.s
@@ -0,0 +1,409 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC56ELxx/boot.s
+ * @brief   SPC56ELxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+        /* BAM record.*/
+        .section    .boot, "ax"
+
+#if BOOT_USE_VLE
+        .long       0x015A0000
+#else
+        .long       0x005A0000
+#endif
+        .long       _reset_address
+
+        .align      2
+        .globl      _reset_address
+        .type       _reset_address, @function
+_reset_address:
+        bl          _coreinit
+        bl          _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+        /*
+         * Image relocation in RAM.
+         */
+        lis         %r4, __ram_reloc_start__@h
+        ori         %r4, %r4, __ram_reloc_start__@l
+        lis         %r5, __ram_reloc_dest__@h
+        ori         %r5, %r5, __ram_reloc_dest__@l
+        lis         %r6, __ram_reloc_end__@h
+        ori         %r6, %r6, __ram_reloc_end__@l
+.relloop:
+        cmpl        cr0, %r4, %r6
+        bge         cr0, .relend
+        lwz         %r7, 0(%r4)
+        addi        %r4, %r4, 4
+        stw         %r7, 0(%r5)
+        addi        %r5, %r5, 4
+        b           .relloop
+.relend:
+        lis         %r3, _boot_address@h
+        ori         %r3, %r3, _boot_address@l
+        mtctr       %r3
+        bctrl
+#else
+        b           _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+        .align      2
+_ramcode:
+        tlbwe
+        isync
+        blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        .align      2
+_coreinit:
+#if BOOT_PERFORM_CORE_INIT
+        /*
+         * Invalidating all TLBs except TLB0.
+         */
+        lis         %r3, 0
+        mtspr       625, %r3        /* MAS1 */
+        mtspr       626, %r3        /* MAS2 */
+        mtspr       627, %r3        /* MAS3 */
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+        mtspr       624, %r3        /* MAS0 */
+        tlbwe
+
+        /*
+         * TLB1 allocated to internal RAM.
+         */
+        lis         %r3, TLB1_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB1_MAS1@h
+        ori         %r3, %r3, TLB1_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB1_MAS2@h
+        ori         %r3, %r3, TLB1_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB1_MAS3@h
+        ori         %r3, %r3, TLB1_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB2 allocated to internal Peripherals Bridge A.
+         */
+        lis         %r3, TLB2_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB2_MAS1@h
+        ori         %r3, %r3, TLB2_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB2_MAS2@h
+        ori         %r3, %r3, TLB2_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB2_MAS3@h
+        ori         %r3, %r3, TLB2_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB3 allocated to internal Peripherals Bridge B.
+         */
+        lis         %r3, TLB3_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB3_MAS1@h
+        ori         %r3, %r3, TLB3_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB3_MAS2@h
+        ori         %r3, %r3, TLB3_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB3_MAS3@h
+        ori         %r3, %r3, TLB3_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB4 allocated to on-platform peripherals.
+         */
+        lis         %r3, TLB4_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB4_MAS1@h
+        ori         %r3, %r3, TLB4_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB4_MAS2@h
+        ori         %r3, %r3, TLB4_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB4_MAS3@h
+        ori         %r3, %r3, TLB4_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * TLB5 allocated to on-platform peripherals.
+         */
+        lis         %r3, TLB5_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB5_MAS1@h
+        ori         %r3, %r3, TLB5_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB5_MAS2@h
+        ori         %r3, %r3, TLB5_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB5_MAS3@h
+        ori         %r3, %r3, TLB5_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        tlbwe
+
+        /*
+         * RAM clearing, this device requires a write to all RAM location in
+         * order to initialize the ECC detection hardware, this is going to
+         * slow down the startup but there is no way around.
+         */
+        xor         %r0, %r0, %r0
+        xor         %r1, %r1, %r1
+        xor         %r2, %r2, %r2
+        xor         %r3, %r3, %r3
+        xor         %r4, %r4, %r4
+        xor         %r5, %r5, %r5
+        xor         %r6, %r6, %r6
+        xor         %r7, %r7, %r7
+        xor         %r8, %r8, %r8
+        xor         %r9, %r9, %r9
+        xor         %r10, %r10, %r10
+        xor         %r11, %r11, %r11
+        xor         %r12, %r12, %r12
+        xor         %r13, %r13, %r13
+        xor         %r14, %r14, %r14
+        xor         %r15, %r15, %r15
+        xor         %r16, %r16, %r16
+        xor         %r17, %r17, %r17
+        xor         %r18, %r18, %r18
+        xor         %r19, %r19, %r19
+        xor         %r20, %r20, %r20
+        xor         %r21, %r21, %r21
+        xor         %r22, %r22, %r22
+        xor         %r23, %r23, %r23
+        xor         %r24, %r24, %r24
+        xor         %r25, %r25, %r25
+        xor         %r26, %r26, %r26
+        xor         %r27, %r27, %r27
+        xor         %r28, %r28, %r28
+        xor         %r29, %r29, %r29
+        xor         %r30, %r30, %r30
+        xor         %r31, %r31, %r31
+        lis         %r4, __ram_start__@h
+        ori         %r4, %r4, __ram_start__@l
+        lis         %r5, __ram_end__@h
+        ori         %r5, %r5, __ram_end__@l
+.cleareccloop:
+        cmpl        %cr0, %r4, %r5
+        bge         %cr0, .cleareccend
+        stmw        %r16, 0(%r4)
+        addi        %r4, %r4, 64
+        b           .cleareccloop
+.cleareccend:
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        /*
+         * Special function registers clearing, required in order to avoid
+         * possible problems with lockstep mode.
+         */
+        mtcrf       0xFF, %r31
+        mtspr       9, %r31         /* CTR     */
+        mtspr       22, %r31        /* DEC     */
+        mtspr       26, %r31        /* SRR0-1  */
+        mtspr       27, %r31
+        mtspr       54, %r31        /* DECAR   */
+        mtspr       58, %r31        /* CSRR0-1 */
+        mtspr       59, %r31
+        mtspr       61, %r31        /* DEAR    */
+        mtspr       256, %r31       /* USPRG0  */
+        mtspr       272, %r31       /* SPRG1-7 */
+        mtspr       273, %r31
+        mtspr       274, %r31
+        mtspr       275, %r31
+        mtspr       276, %r31
+        mtspr       277, %r31
+        mtspr       278, %r31
+        mtspr       279, %r31
+        mtspr       285, %r31       /* TBU     */
+        mtspr       284, %r31       /* TBL     */
+#if 0
+        mtspr       318, %r31       /* DVC1-2  */
+        mtspr       319, %r31
+#endif
+        mtspr       562, %r31       /* DBCNT */
+        mtspr       570, %r31       /* MCSRR0  */
+        mtspr       571, %r31       /* MCSRR1  */
+        mtspr       604, %r31       /* SPRG8-9 */
+        mtspr       605, %r31
+
+#if BOOT_PERFORM_CORE_INIT
+        /*
+         * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+         * is executed from RAM.
+         */
+        lis         %r3, TLB0_MAS0@h
+        mtspr       624, %r3        /* MAS0 */
+        lis         %r3, TLB0_MAS1@h
+        ori         %r3, %r3, TLB0_MAS1@l
+        mtspr       625, %r3        /* MAS1 */
+        lis         %r3, TLB0_MAS2@h
+        ori         %r3, %r3, TLB0_MAS2@l
+        mtspr       626, %r3        /* MAS2 */
+        lis         %r3, TLB0_MAS3@h
+        ori         %r3, %r3, TLB0_MAS3@l
+        mtspr       627, %r3        /* MAS3 */
+        mflr        %r4
+        lis         %r6, _ramcode@h
+        ori         %r6, %r6, _ramcode@l
+        lis         %r7, 0x40010000@h
+        mtctr       %r7
+        lwz         %r3, 0(%r6)
+        stw         %r3, 0(%r7)
+        lwz         %r3, 4(%r6)
+        stw         %r3, 4(%r7)
+        lwz         %r3, 8(%r6)
+        stw         %r3, 8(%r7)
+        bctrl
+        mtlr        %r4
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+        /*
+         * Branch prediction enabled.
+         */
+        li          %r3, BOOT_BUCSR_DEFAULT
+        mtspr       1013, %r3       /* BUCSR */
+
+        /*
+         * Cache invalidated and then enabled.
+         */
+        li          %r3, LICSR1_ICINV
+        mtspr       1011, %r3       /* LICSR1 */
+.inv:   mfspr       %r3, 1011       /* LICSR1 */
+        andi.       %r3, %r3, LICSR1_ICINV
+        bne         .inv
+        lis         %r3, BOOT_LICSR1_DEFAULT@h
+        ori         %r3, %r3, BOOT_LICSR1_DEFAULT@l
+        mtspr       1011, %r3       /* LICSR1 */
+
+        blr
+
+        /*
+         * Exception vectors initialization.
+         */
+        .align      2
+_ivinit:
+        /* MSR initialization.*/
+        lis         %r3, BOOT_MSR_DEFAULT@h
+        ori         %r3, %r3, BOOT_MSR_DEFAULT@l
+        mtMSR       %r3
+
+        /* IVPR initialization.*/
+        lis         %r3, __ivpr_base__@h
+        ori         %r3, %r3, __ivpr_base__@l
+        mtIVPR      %r3
+
+        /* IVORs initialization.*/
+        lis         %r3, _unhandled_exception@h
+        ori         %r3, %r3, _unhandled_exception@l
+
+        mtspr       400, %r3        /* IVOR0-15 */
+        mtspr       401, %r3
+        mtspr       402, %r3
+        mtspr       403, %r3
+        mtspr       404, %r3
+        mtspr       405, %r3
+        mtspr       406, %r3
+        mtspr       407, %r3
+        mtspr       408, %r3
+        mtspr       409, %r3
+        mtspr       410, %r3
+        mtspr       411, %r3
+        mtspr       412, %r3
+        mtspr       413, %r3
+        mtspr       414, %r3
+        mtspr       415, %r3
+        mtspr       528, %r3        /* IVOR32-34 */
+        mtspr       529, %r3
+        mtspr       530, %r3
+
+        blr
+
+        .section    .handlers, "ax"
+
+        /*
+         * Unhandled exceptions handler.
+         */
+        .weak       _unhandled_exception
+        .type       _unhandled_exception, @function
+_unhandled_exception:
+        b           _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ELxx/ppcparams.h b/os/common/ports/e200/devices/SPC56ELxx/ppcparams.h
new file mode 100644
index 000000000..c588a1d8e
--- /dev/null
+++ b/os/common/ports/e200/devices/SPC56ELxx/ppcparams.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    SPC56ELxx/ppcparams.h
+ * @brief   PowerPC parameters for the SPC56ELxx.
+ *
+ * @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ *          SPC56ELxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief   PPC core model.
+ */
+#define PPC_VARIANT                 PPC_VARIANT_e200z4
+
+/**
+ * @brief   Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS               16
+
+/**
+ * @brief   IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS          TRUE
+
+/**
+ * @brief   Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE          TRUE
+
+/**
+ * @brief   VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE            TRUE
+
+/**
+ * @brief   Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI      TRUE
+
+/**
+ * @brief   Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER    TRUE
+
+/**
+ * @brief   Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS             256
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/ext/CMSIS/ST/stm32f0xx.h b/os/ext/CMSIS/ST/stm32f0xx.h
new file mode 100644
index 000000000..4f21be891
--- /dev/null
+++ b/os/ext/CMSIS/ST/stm32f0xx.h
@@ -0,0 +1,3292 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx.h
+  * @author  MCD Application Team
+  * @version V1.2.1
+  * @date    22-November-2013
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F0xx devices.  
+  *          
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx
+  * @{
+  */
+    
+#ifndef __STM32F0XX_H
+#define __STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32F0 device used in your 
+   application 
+  */
+
+#if !defined (STM32F0XX_LD)  && !defined (STM32F0XX_MD) && !defined (STM32F030)
+  /* #define STM32F0XX_LD */ /*!< STM32F0xx Low-density devices are STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes */
+  /* #define STM32F0XX_MD */     /*!< STM32F0xx Medium-density devices are STM32F051xx and STM32F061xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes */  
+    #define STM32F030  /*!< STM32F030 devices are STM32F030xx value line microcontrollers */
+#endif
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+/* Old STM32F0XX definition, maintained for legacy purpose */
+#if defined(STM32F0XX)
+  #define STM32F0XX_MD
+#endif /* STM32F0XX */
+
+/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
+#if defined (STM32F030X8) || defined (STM32F030X6)
+  #define    STM32F030
+#endif /* STM32F030X8 or  STM32F030X6 */
+
+#if !defined (STM32F0XX_LD)  && !defined (STM32F0XX_MD) && !defined (STM32F030)
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)     
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
+   Timeout value 
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE) 
+#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI_VALUE */
+
+#if !defined  (HSI14_VALUE) 
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+#if !defined  (LSI_VALUE) 
+#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE) 
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief STM32F0xx Standard Peripheral Library version number V1.2.1
+   */
+#define __STM32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F0XX_STDPERIPH_VERSION        ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief STM32F0xx Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
+#define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
+#if defined (STM32F0XX_MD)
+/******  STM32F0XX_MD  specific Interrupt Numbers ****************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
+  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
+  TS_IRQn                     = 8,      /*!< Touch sense controller Interrupt                        */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
+  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
+  CEC_IRQn                    = 30      /*!< CEC Interrupt                                           */
+#elif defined (STM32F0XX_LD)
+/******  STM32F0XX_LD specific Interrupt Numbers *****************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
+  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
+  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
+  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
+  USART1_IRQn                 = 27      /*!< USART1 Interrupt                                        */
+#elif defined (STM32F030)
+/******  STM32F030 specific Interrupt Numbers ********************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
+  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
+  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
+  USART2_IRQn                 = 28      /*!< USART2 Interrupt                                        */
+#endif /* STM32F0XX_MD */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0.h"
+#include "system_stm32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
+   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+/** 
+  * @brief HDMI-CEC 
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief Comparator 
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x1C */
+} COMP_TypeDef;
+
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;       /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;      /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t   RESERVED0;    /*!< Reserved,                                                    0x05 */
+  uint16_t  RESERVED1;    /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;       /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t  RESERVED2;    /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;     /*!< Initial CRC value register,                  Address offset: 0x10 */
+} CRC_TypeDef;
+
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
+  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
+  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
+  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
+       uint32_t RESERVED[6];  /*!< Reserved,                                                                 0x14 */
+  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
+       uint32_t RESERVED1;    /*!< Reserved,                                                                 0x30 */
+  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+} DMA_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
+  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
+  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
+  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
+  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
+  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/** 
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
+  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
+  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
+  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
+} OB_TypeDef;
+  
+
+/** 
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
+}GPIO_TypeDef;
+
+/** 
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */
+       uint32_t RESERVED;    /*!< Reserved,                                                                  0x04 */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration register,     Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                           Address offset: 0x18 */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/** 
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{                           
+  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
+       uint32_t RESERVED0;  /*!< Reserved,                                                 Address offset: 0x14 */
+       uint32_t RESERVED1;  /*!< Reserved,                                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
+       uint32_t RESERVED2;  /*!< Reserved,                                                 Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CAL;        /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+       uint32_t RESERVED3;  /*!< Reserved,                                                 Address offset: 0x48 */
+       uint32_t RESERVED4;  /*!< Reserved,                                                 Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+  
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
+  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
+} SPI_TypeDef;
+
+
+/** 
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
+  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
+  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
+  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
+  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
+  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
+  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
+  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
+  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
+  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
+  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
+  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
+  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
+  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
+  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
+  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
+  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
+  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
+  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
+  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
+  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
+  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
+  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
+  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
+  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
+  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
+  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
+  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
+  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
+  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
+  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
+  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
+  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
+  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
+} TIM_TypeDef;
+
+/** 
+  * @brief Touch Sensing Controller (TSC)
+  */
+typedef struct
+{
+  __IO uint32_t CR;        /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;       /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;       /*!< TSC interrupt clear register,                             Address offset: 0x08 */ 
+  __IO uint32_t ISR;       /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;     /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  __IO uint32_t RESERVED1; /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;    /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  __IO uint32_t RESERVED2; /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;     /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  __IO uint32_t RESERVED3; /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;     /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  __IO uint32_t RESERVED4; /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;    /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register,                         Address offset: 0x34-48 */
+} TSC_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+  
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
+  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+
+/** 
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
+#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00007400)
+#define CEC_BASE              (APBPERIPH_BASE + 0x00007800)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE             (APBPERIPH_BASE + 0x0001001C)
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE) 
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
+#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
+#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
+#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
+#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
+#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
+#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
+#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
+#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
+#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
+#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
+#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
+#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
+#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
+#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
+#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
+#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
+#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
+#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
+#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
+#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
+#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
+#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
+#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
+#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
+#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
+#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define  ADC_CFGR2_JITOFFDIV4                 ((uint32_t)0x80000000)       /*!< Jitter Off when ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_JITOFFDIV2                 ((uint32_t)0x40000000)       /*!< Jitter Off when ADC clocked by PCLK div2 */
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define  ADC_SMPR1_SMPR                      ((uint32_t)0x00000007)        /*!< SMPR[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR1_SMPR_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMPR_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMPR_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
+#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
+#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
+#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
+#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
+#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
+#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
+#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
+#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
+#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
+#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
+#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
+#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
+#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
+#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
+#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
+#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
+#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
+#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
+#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 HDMI-CEC (CEC)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                         */
+#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message            */
+#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message              */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time               */
+#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                      */
+#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                        */
+#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation    */
+#define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation   */
+#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast no Error generation  */
+#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional      */
+#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                    */
+#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                    */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                        */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                        */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                   */
+#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                   */
+#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                         */
+#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                */
+#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error          */
+#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error           */
+#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge             */
+#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                   */
+#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                    */
+#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                */
+#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                 */
+#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                           */
+#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge             */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable         */
+#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable         */
+#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable               */
+#define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable      */
+#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable*/
+#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable */
+#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable   */
+#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable         */
+#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable         */
+#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable      */
+#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable       */
+#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                 */
+#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL           ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2         ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL              ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST             ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0           ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1           ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT              ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK             ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN               ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE             ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0           ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1           ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL            ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0          ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1          ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2          ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN                ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL           ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0         ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1         ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2         ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL              ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST             ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0           ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1           ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    Digital to Analog Converter (DAC)                       */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA Underrun Interrupt enable */
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!<DAC channel1 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)         /*!<DAC channel1 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!<DAC channel1 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
+
+#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  FLASH Keys  **********************************************/
+#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
+#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
+                                                                                to unlock the write access to the FPEC. */
+                                                               
+#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
+#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                                                unlock the write access to the option byte block */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */
+
+#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
+#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0x0000FFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for OB_WRP0 register  *********************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP1 register  *********************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE configuration */
+#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
+#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADCPRE bit (ADC prescaler) */
+
+#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK divided by 2 */
+#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK divided by 4 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLSRC_HSI_Div2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define  RCC_CFGR_PLLMULL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+
+#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+
+#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO (only for STM32F0XX_LD and STM32FO30X6 devices) */
+
+/*!<******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 clock reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
+#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
+#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSEN                     ((uint32_t)0x01000000)        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/  
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                 ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBL                         ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
+#define  RCC_AHBRSTR_TSRST                   ((uint32_t)0x00100000)         /*!< TS clock reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+/*!< USART1 Clock source selection */
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+/*!< I2C1 Clock source selection */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 
+#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */ 
+#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */ 
+
+/*******************  Bit definition for RCC_CR2 register  ********************/
+#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
+#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
+#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
+#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
+#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_CALSEL                        ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CAL_CALP                         ((uint32_t)0x00008000)
+#define RTC_CAL_CALW8                        ((uint32_t)0x00004000)
+#define RTC_CAL_CALW16                       ((uint32_t)0x00002000)
+#define RTC_CAL_CALM                         ((uint32_t)0x000001FF)
+#define RTC_CAL_CALM_0                       ((uint32_t)0x00000001)
+#define RTC_CAL_CALM_1                       ((uint32_t)0x00000002)
+#define RTC_CAL_CALM_2                       ((uint32_t)0x00000004)
+#define RTC_CAL_CALM_3                       ((uint32_t)0x00000008)
+#define RTC_CAL_CALM_4                       ((uint32_t)0x00000010)
+#define RTC_CAL_CALM_5                       ((uint32_t)0x00000020)
+#define RTC_CAL_CALM_6                       ((uint32_t)0x00000040)
+#define RTC_CAL_CALM_7                       ((uint32_t)0x00000080)
+#define RTC_CAL_CALM_8                       ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0XX_LD and STM32FO30X6 devices) */
+#define SYSCFG_CFGR1_I2C_FMP_PA9            ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F0XX_LD and STM32FO30X6 devices) */
+#define SYSCFG_CFGR1_I2C_FMP_PA10           ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F0XX_LD and STM32FO30X6 devices) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/** 
+  * @brief  EXTI0 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0003) /*!< PF[0] pin */
+
+/** 
+  * @brief  EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0030) /*!< PF[1] pin */
+
+/** 
+  * @brief  EXTI2 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+
+/** 
+  * @brief  EXTI3 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/** 
+  * @brief  EXTI4 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0003) /*!< PF[4] pin */
+
+/** 
+  * @brief  EXTI5 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0030) /*!< PF[5] pin */
+
+/** 
+  * @brief  EXTI6 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0300) /*!< PF[6] pin */
+
+/** 
+  * @brief  EXTI7 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x3000) /*!< PF[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/** 
+  * @brief  EXTI8 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+
+/** 
+  * @brief  EXTI9 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+
+/** 
+  * @brief  EXTI10 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+
+/** 
+  * @brief  EXTI11 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/** 
+  * @brief  EXTI12 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+
+/** 
+  * @brief  EXTI13 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+
+/** 
+  * @brief  EXTI14 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+
+/** 
+  * @brief  EXTI15 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PE                   ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f0xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/stm32f10x.h b/os/ext/CMSIS/ST/stm32f10x.h
new file mode 100644
index 000000000..8ca3fe29b
--- /dev/null
+++ b/os/ext/CMSIS/ST/stm32f10x.h
@@ -0,0 +1,8342 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F10x Connectivity line, 
+  *          High density, High density value line, Medium density, 
+  *          Medium density Value line, Low density, Low density Value line 
+  *          and XL-density devices.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral�s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral�s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x
+  * @{
+  */
+    
+#ifndef __STM32F10x_H
+#define __STM32F10x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) 
+  /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices */
+  /* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */  
+  /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices */
+  /* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */  
+  /* #define STM32F10X_HD */     /*!< STM32F10X_HD: STM32 High density devices */
+  /* #define STM32F10X_HD_VL */  /*!< STM32F10X_HD_VL: STM32 High density value line devices */  
+  /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices */
+  /* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */
+#endif
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+   where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density value line devices are STM32F100xx microcontrollers where the Flash
+   memory density ranges between 16 and 32 Kbytes.
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+   where the Flash memory density ranges between 64 and 128 Kbytes.
+ - Medium-density value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 64 and 128 Kbytes.   
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 256 and 512 Kbytes.   
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+  */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
+ #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
+#endif
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */           
+#if !defined  HSE_VALUE
+ #ifdef STM32F10X_CL   
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #else 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #endif /* STM32F10X_CL */
+#endif /* HSE_VALUE */
+
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
+
+#define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+
+/**
+ * @brief STM32F10x Standard Peripheral Library version number
+   */
+#define __STM32F10X_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:24] main version */                                  
+#define __STM32F10X_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F10X_STDPERIPH_VERSION       ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F10X_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+#ifdef STM32F10X_XL
+ #define __MPU_PRESENT             1 /*!< STM32 XL-density devices provide an MPU */
+#else
+ #define __MPU_PRESENT             0 /*!< Other STM32 devices does not provide an MPU */
+#endif /* STM32F10X_XL */
+#define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
+
+/******  STM32 specific Interrupt Numbers *********************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
+  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
+  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
+
+#ifdef STM32F10X_LD
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */    
+#endif /* STM32F10X_LD */  
+
+#ifdef STM32F10X_LD_VL
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
+  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
+#endif /* STM32F10X_LD_VL */
+
+#ifdef STM32F10X_MD
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */  
+#endif /* STM32F10X_MD */  
+
+#ifdef STM32F10X_MD_VL
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
+  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
+#endif /* STM32F10X_MD_VL */
+
+#ifdef STM32F10X_HD
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+#endif /* STM32F10X_HD */  
+
+#ifdef STM32F10X_HD_VL
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
+  TIM12_IRQn                  = 43,     /*!< TIM12 global Interrupt                               */
+  TIM13_IRQn                  = 44,     /*!< TIM13 global Interrupt                               */
+  TIM14_IRQn                  = 45,     /*!< TIM14 global Interrupt                               */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */  
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
+  TIM7_IRQn                   = 55,     /*!< TIM7 Interrupt                                       */  
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+  DMA2_Channel5_IRQn          = 60      /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is 
+                                             mapped at position 60 only if the MISC_REMAP bit in 
+                                             the AFIO_MAPR2 register is set)                      */       
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_XL
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+#endif /* STM32F10X_XL */  
+
+#ifdef STM32F10X_CL
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  CAN1_TX_IRQn                = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  CAN1_RX0_IRQn               = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                      */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                      */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                            */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt          */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                    */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                   */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                   */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                   */
+  OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */
+#endif /* STM32F10X_CL */     
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm3.h"
+#include "system_stm32f10x.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
+#define HSE_Value            HSE_VALUE
+#define HSI_Value            HSI_VALUE
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;
+  __IO uint32_t CR1;
+  __IO uint32_t CR2;
+  __IO uint32_t SMPR1;
+  __IO uint32_t SMPR2;
+  __IO uint32_t JOFR1;
+  __IO uint32_t JOFR2;
+  __IO uint32_t JOFR3;
+  __IO uint32_t JOFR4;
+  __IO uint32_t HTR;
+  __IO uint32_t LTR;
+  __IO uint32_t SQR1;
+  __IO uint32_t SQR2;
+  __IO uint32_t SQR3;
+  __IO uint32_t JSQR;
+  __IO uint32_t JDR1;
+  __IO uint32_t JDR2;
+  __IO uint32_t JDR3;
+  __IO uint32_t JDR4;
+  __IO uint32_t DR;
+} ADC_TypeDef;
+
+/** 
+  * @brief Backup Registers  
+  */
+
+typedef struct
+{
+  uint32_t  RESERVED0;
+  __IO uint16_t DR1;
+  uint16_t  RESERVED1;
+  __IO uint16_t DR2;
+  uint16_t  RESERVED2;
+  __IO uint16_t DR3;
+  uint16_t  RESERVED3;
+  __IO uint16_t DR4;
+  uint16_t  RESERVED4;
+  __IO uint16_t DR5;
+  uint16_t  RESERVED5;
+  __IO uint16_t DR6;
+  uint16_t  RESERVED6;
+  __IO uint16_t DR7;
+  uint16_t  RESERVED7;
+  __IO uint16_t DR8;
+  uint16_t  RESERVED8;
+  __IO uint16_t DR9;
+  uint16_t  RESERVED9;
+  __IO uint16_t DR10;
+  uint16_t  RESERVED10; 
+  __IO uint16_t RTCCR;
+  uint16_t  RESERVED11;
+  __IO uint16_t CR;
+  uint16_t  RESERVED12;
+  __IO uint16_t CSR;
+  uint16_t  RESERVED13[5];
+  __IO uint16_t DR11;
+  uint16_t  RESERVED14;
+  __IO uint16_t DR12;
+  uint16_t  RESERVED15;
+  __IO uint16_t DR13;
+  uint16_t  RESERVED16;
+  __IO uint16_t DR14;
+  uint16_t  RESERVED17;
+  __IO uint16_t DR15;
+  uint16_t  RESERVED18;
+  __IO uint16_t DR16;
+  uint16_t  RESERVED19;
+  __IO uint16_t DR17;
+  uint16_t  RESERVED20;
+  __IO uint16_t DR18;
+  uint16_t  RESERVED21;
+  __IO uint16_t DR19;
+  uint16_t  RESERVED22;
+  __IO uint16_t DR20;
+  uint16_t  RESERVED23;
+  __IO uint16_t DR21;
+  uint16_t  RESERVED24;
+  __IO uint16_t DR22;
+  uint16_t  RESERVED25;
+  __IO uint16_t DR23;
+  uint16_t  RESERVED26;
+  __IO uint16_t DR24;
+  uint16_t  RESERVED27;
+  __IO uint16_t DR25;
+  uint16_t  RESERVED28;
+  __IO uint16_t DR26;
+  uint16_t  RESERVED29;
+  __IO uint16_t DR27;
+  uint16_t  RESERVED30;
+  __IO uint16_t DR28;
+  uint16_t  RESERVED31;
+  __IO uint16_t DR29;
+  uint16_t  RESERVED32;
+  __IO uint16_t DR30;
+  uint16_t  RESERVED33; 
+  __IO uint16_t DR31;
+  uint16_t  RESERVED34;
+  __IO uint16_t DR32;
+  uint16_t  RESERVED35;
+  __IO uint16_t DR33;
+  uint16_t  RESERVED36;
+  __IO uint16_t DR34;
+  uint16_t  RESERVED37;
+  __IO uint16_t DR35;
+  uint16_t  RESERVED38;
+  __IO uint16_t DR36;
+  uint16_t  RESERVED39;
+  __IO uint16_t DR37;
+  uint16_t  RESERVED40;
+  __IO uint16_t DR38;
+  uint16_t  RESERVED41;
+  __IO uint16_t DR39;
+  uint16_t  RESERVED42;
+  __IO uint16_t DR40;
+  uint16_t  RESERVED43;
+  __IO uint16_t DR41;
+  uint16_t  RESERVED44;
+  __IO uint16_t DR42;
+  uint16_t  RESERVED45;    
+} BKP_TypeDef;
+  
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;
+  __IO uint32_t TDTR;
+  __IO uint32_t TDLR;
+  __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;
+  __IO uint32_t RDTR;
+  __IO uint32_t RDLR;
+  __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1;
+  __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t MCR;
+  __IO uint32_t MSR;
+  __IO uint32_t TSR;
+  __IO uint32_t RF0R;
+  __IO uint32_t RF1R;
+  __IO uint32_t IER;
+  __IO uint32_t ESR;
+  __IO uint32_t BTR;
+  uint32_t  RESERVED0[88];
+  CAN_TxMailBox_TypeDef sTxMailBox[3];
+  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+  uint32_t  RESERVED1[12];
+  __IO uint32_t FMR;
+  __IO uint32_t FM1R;
+  uint32_t  RESERVED2;
+  __IO uint32_t FS1R;
+  uint32_t  RESERVED3;
+  __IO uint32_t FFA1R;
+  uint32_t  RESERVED4;
+  __IO uint32_t FA1R;
+  uint32_t  RESERVED5[8];
+#ifndef STM32F10X_CL
+  CAN_FilterRegister_TypeDef sFilterRegister[14];
+#else
+  CAN_FilterRegister_TypeDef sFilterRegister[28];
+#endif /* STM32F10X_CL */  
+} CAN_TypeDef;
+
+/** 
+  * @brief Consumer Electronics Control (CEC)
+  */
+typedef struct
+{
+  __IO uint32_t CFGR;
+  __IO uint32_t OAR;
+  __IO uint32_t PRES;
+  __IO uint32_t ESR;
+  __IO uint32_t CSR;
+  __IO uint32_t TXD;
+  __IO uint32_t RXD;  
+} CEC_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;
+  __IO uint8_t  IDR;
+  uint8_t   RESERVED0;
+  uint16_t  RESERVED1;
+  __IO uint32_t CR;
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t SWTRIGR;
+  __IO uint32_t DHR12R1;
+  __IO uint32_t DHR12L1;
+  __IO uint32_t DHR8R1;
+  __IO uint32_t DHR12R2;
+  __IO uint32_t DHR12L2;
+  __IO uint32_t DHR8R2;
+  __IO uint32_t DHR12RD;
+  __IO uint32_t DHR12LD;
+  __IO uint32_t DHR8RD;
+  __IO uint32_t DOR1;
+  __IO uint32_t DOR2;
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+  __IO uint32_t SR;
+#endif
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;
+  __IO uint32_t CR;	
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;
+  __IO uint32_t CNDTR;
+  __IO uint32_t CPAR;
+  __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;
+  __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+       uint32_t RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+       uint32_t RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+       uint32_t RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+       uint32_t RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+       uint32_t RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+       uint32_t RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+       uint32_t RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+       uint32_t RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+       uint32_t RESERVED8[567];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+       uint32_t RESERVED9[9];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;
+  __IO uint32_t EMR;
+  __IO uint32_t RTSR;
+  __IO uint32_t FTSR;
+  __IO uint32_t SWIER;
+  __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;
+  __IO uint32_t KEYR;
+  __IO uint32_t OPTKEYR;
+  __IO uint32_t SR;
+  __IO uint32_t CR;
+  __IO uint32_t AR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t OBR;
+  __IO uint32_t WRPR;
+#ifdef STM32F10X_XL
+  uint32_t RESERVED1[8]; 
+  __IO uint32_t KEYR2;
+  uint32_t RESERVED2;   
+  __IO uint32_t SR2;
+  __IO uint32_t CR2;
+  __IO uint32_t AR2; 
+#endif /* STM32F10X_XL */  
+} FLASH_TypeDef;
+
+/** 
+  * @brief Option Bytes Registers
+  */
+  
+typedef struct
+{
+  __IO uint16_t RDP;
+  __IO uint16_t USER;
+  __IO uint16_t Data0;
+  __IO uint16_t Data1;
+  __IO uint16_t WRP0;
+  __IO uint16_t WRP1;
+  __IO uint16_t WRP2;
+  __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];   
+} FSMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;
+  __IO uint32_t SR2;
+  __IO uint32_t PMEM2;
+  __IO uint32_t PATT2;
+  uint32_t  RESERVED0;   
+  __IO uint32_t ECCR2; 
+} FSMC_Bank2_TypeDef;  
+
+/** 
+  * @brief Flexible Static Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR3;
+  __IO uint32_t SR3;
+  __IO uint32_t PMEM3;
+  __IO uint32_t PATT3;
+  uint32_t  RESERVED0;   
+  __IO uint32_t ECCR3; 
+} FSMC_Bank3_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;
+  __IO uint32_t SR4;
+  __IO uint32_t PMEM4;
+  __IO uint32_t PATT4;
+  __IO uint32_t PIO4; 
+} FSMC_Bank4_TypeDef; 
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t CRL;
+  __IO uint32_t CRH;
+  __IO uint32_t IDR;
+  __IO uint32_t ODR;
+  __IO uint32_t BSRR;
+  __IO uint32_t BRR;
+  __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/** 
+  * @brief Alternate Function I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t EVCR;
+  __IO uint32_t MAPR;
+  __IO uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  __IO uint32_t MAPR2;  
+} AFIO_TypeDef;
+/** 
+  * @brief Inter Integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t OAR1;
+  uint16_t  RESERVED2;
+  __IO uint16_t OAR2;
+  uint16_t  RESERVED3;
+  __IO uint16_t DR;
+  uint16_t  RESERVED4;
+  __IO uint16_t SR1;
+  uint16_t  RESERVED5;
+  __IO uint16_t SR2;
+  uint16_t  RESERVED6;
+  __IO uint16_t CCR;
+  uint16_t  RESERVED7;
+  __IO uint16_t TRISE;
+  uint16_t  RESERVED8;
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;
+  __IO uint32_t PR;
+  __IO uint32_t RLR;
+  __IO uint32_t SR;
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CFGR;
+  __IO uint32_t CIR;
+  __IO uint32_t APB2RSTR;
+  __IO uint32_t APB1RSTR;
+  __IO uint32_t AHBENR;
+  __IO uint32_t APB2ENR;
+  __IO uint32_t APB1ENR;
+  __IO uint32_t BDCR;
+  __IO uint32_t CSR;
+
+#ifdef STM32F10X_CL  
+  __IO uint32_t AHBRSTR;
+  __IO uint32_t CFGR2;
+#endif /* STM32F10X_CL */ 
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)   
+  uint32_t RESERVED0;
+  __IO uint32_t CFGR2;
+#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ 
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint16_t CRH;
+  uint16_t  RESERVED0;
+  __IO uint16_t CRL;
+  uint16_t  RESERVED1;
+  __IO uint16_t PRLH;
+  uint16_t  RESERVED2;
+  __IO uint16_t PRLL;
+  uint16_t  RESERVED3;
+  __IO uint16_t DIVH;
+  uint16_t  RESERVED4;
+  __IO uint16_t DIVL;
+  uint16_t  RESERVED5;
+  __IO uint16_t CNTH;
+  uint16_t  RESERVED6;
+  __IO uint16_t CNTL;
+  uint16_t  RESERVED7;
+  __IO uint16_t ALRH;
+  uint16_t  RESERVED8;
+  __IO uint16_t ALRL;
+  uint16_t  RESERVED9;
+} RTC_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;
+  __IO uint32_t CLKCR;
+  __IO uint32_t ARG;
+  __IO uint32_t CMD;
+  __I uint32_t RESPCMD;
+  __I uint32_t RESP1;
+  __I uint32_t RESP2;
+  __I uint32_t RESP3;
+  __I uint32_t RESP4;
+  __IO uint32_t DTIMER;
+  __IO uint32_t DLEN;
+  __IO uint32_t DCTRL;
+  __I uint32_t DCOUNT;
+  __I uint32_t STA;
+  __IO uint32_t ICR;
+  __IO uint32_t MASK;
+  uint32_t  RESERVED0[2];
+  __I uint32_t FIFOCNT;
+  uint32_t  RESERVED1[13];
+  __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t SR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DR;
+  uint16_t  RESERVED3;
+  __IO uint16_t CRCPR;
+  uint16_t  RESERVED4;
+  __IO uint16_t RXCRCR;
+  uint16_t  RESERVED5;
+  __IO uint16_t TXCRCR;
+  uint16_t  RESERVED6;
+  __IO uint16_t I2SCFGR;
+  uint16_t  RESERVED7;
+  __IO uint16_t I2SPR;
+  uint16_t  RESERVED8;  
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t SMCR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DIER;
+  uint16_t  RESERVED3;
+  __IO uint16_t SR;
+  uint16_t  RESERVED4;
+  __IO uint16_t EGR;
+  uint16_t  RESERVED5;
+  __IO uint16_t CCMR1;
+  uint16_t  RESERVED6;
+  __IO uint16_t CCMR2;
+  uint16_t  RESERVED7;
+  __IO uint16_t CCER;
+  uint16_t  RESERVED8;
+  __IO uint16_t CNT;
+  uint16_t  RESERVED9;
+  __IO uint16_t PSC;
+  uint16_t  RESERVED10;
+  __IO uint16_t ARR;
+  uint16_t  RESERVED11;
+  __IO uint16_t RCR;
+  uint16_t  RESERVED12;
+  __IO uint16_t CCR1;
+  uint16_t  RESERVED13;
+  __IO uint16_t CCR2;
+  uint16_t  RESERVED14;
+  __IO uint16_t CCR3;
+  uint16_t  RESERVED15;
+  __IO uint16_t CCR4;
+  uint16_t  RESERVED16;
+  __IO uint16_t BDTR;
+  uint16_t  RESERVED17;
+  __IO uint16_t DCR;
+  uint16_t  RESERVED18;
+  __IO uint16_t DMAR;
+  uint16_t  RESERVED19;
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint16_t SR;
+  uint16_t  RESERVED0;
+  __IO uint16_t DR;
+  uint16_t  RESERVED1;
+  __IO uint16_t BRR;
+  uint16_t  RESERVED2;
+  __IO uint16_t CR1;
+  uint16_t  RESERVED3;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED4;
+  __IO uint16_t CR3;
+  uint16_t  RESERVED5;
+  __IO uint16_t GTPR;
+  uint16_t  RESERVED6;
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CFR;
+  __IO uint32_t SR;
+} WWDG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
+
+#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)
+
+#define SDIO_BASE             (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
+
+#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
+#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define BKP                 ((BKP_TypeDef *) BKP_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE) 
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_2V2                      ((uint16_t)0x0000)     /*!< PVD level 2.2V */
+#define  PWR_CR_PLS_2V3                      ((uint16_t)0x0020)     /*!< PVD level 2.3V */
+#define  PWR_CR_PLS_2V4                      ((uint16_t)0x0040)     /*!< PVD level 2.4V */
+#define  PWR_CR_PLS_2V5                      ((uint16_t)0x0060)     /*!< PVD level 2.5V */
+#define  PWR_CR_PLS_2V6                      ((uint16_t)0x0080)     /*!< PVD level 2.6V */
+#define  PWR_CR_PLS_2V7                      ((uint16_t)0x00A0)     /*!< PVD level 2.7V */
+#define  PWR_CR_PLS_2V8                      ((uint16_t)0x00C0)     /*!< PVD level 2.8V */
+#define  PWR_CR_PLS_2V9                      ((uint16_t)0x00E0)     /*!< PVD level 2.9V */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Backup registers                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BKP_DR1 register  ********************/
+#define  BKP_DR1_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR2 register  ********************/
+#define  BKP_DR2_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR3 register  ********************/
+#define  BKP_DR3_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR4 register  ********************/
+#define  BKP_DR4_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR5 register  ********************/
+#define  BKP_DR5_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR6 register  ********************/
+#define  BKP_DR6_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR7 register  ********************/
+#define  BKP_DR7_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR8 register  ********************/
+#define  BKP_DR8_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR9 register  ********************/
+#define  BKP_DR9_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR10 register  *******************/
+#define  BKP_DR10_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR11 register  *******************/
+#define  BKP_DR11_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR12 register  *******************/
+#define  BKP_DR12_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR13 register  *******************/
+#define  BKP_DR13_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR14 register  *******************/
+#define  BKP_DR14_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR15 register  *******************/
+#define  BKP_DR15_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR16 register  *******************/
+#define  BKP_DR16_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR17 register  *******************/
+#define  BKP_DR17_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/******************  Bit definition for BKP_DR18 register  ********************/
+#define  BKP_DR18_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR19 register  *******************/
+#define  BKP_DR19_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR20 register  *******************/
+#define  BKP_DR20_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR21 register  *******************/
+#define  BKP_DR21_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR22 register  *******************/
+#define  BKP_DR22_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR23 register  *******************/
+#define  BKP_DR23_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR24 register  *******************/
+#define  BKP_DR24_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR25 register  *******************/
+#define  BKP_DR25_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR26 register  *******************/
+#define  BKP_DR26_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR27 register  *******************/
+#define  BKP_DR27_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR28 register  *******************/
+#define  BKP_DR28_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR29 register  *******************/
+#define  BKP_DR29_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR30 register  *******************/
+#define  BKP_DR30_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR31 register  *******************/
+#define  BKP_DR31_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR32 register  *******************/
+#define  BKP_DR32_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR33 register  *******************/
+#define  BKP_DR33_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR34 register  *******************/
+#define  BKP_DR34_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR35 register  *******************/
+#define  BKP_DR35_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR36 register  *******************/
+#define  BKP_DR36_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR37 register  *******************/
+#define  BKP_DR37_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR38 register  *******************/
+#define  BKP_DR38_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR39 register  *******************/
+#define  BKP_DR39_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR40 register  *******************/
+#define  BKP_DR40_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR41 register  *******************/
+#define  BKP_DR41_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR42 register  *******************/
+#define  BKP_DR42_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/******************  Bit definition for BKP_RTCCR register  *******************/
+#define  BKP_RTCCR_CAL                       ((uint16_t)0x007F)     /*!< Calibration value */
+#define  BKP_RTCCR_CCO                       ((uint16_t)0x0080)     /*!< Calibration Clock Output */
+#define  BKP_RTCCR_ASOE                      ((uint16_t)0x0100)     /*!< Alarm or Second Output Enable */
+#define  BKP_RTCCR_ASOS                      ((uint16_t)0x0200)     /*!< Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_CR register  ********************/
+#define  BKP_CR_TPE                          ((uint8_t)0x01)        /*!< TAMPER pin enable */
+#define  BKP_CR_TPAL                         ((uint8_t)0x02)        /*!< TAMPER pin active level */
+
+/*******************  Bit definition for BKP_CSR register  ********************/
+#define  BKP_CSR_CTE                         ((uint16_t)0x0001)     /*!< Clear Tamper event */
+#define  BKP_CSR_CTI                         ((uint16_t)0x0002)     /*!< Clear Tamper Interrupt */
+#define  BKP_CSR_TPIE                        ((uint16_t)0x0004)     /*!< TAMPER Pin interrupt enable */
+#define  BKP_CSR_TEF                         ((uint16_t)0x0100)     /*!< Tamper Event Flag */
+#define  BKP_CSR_TIF                         ((uint16_t)0x0200)     /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+#ifdef STM32F10X_CL
+ #define  RCC_CR_PLL2ON                       ((uint32_t)0x04000000)        /*!< PLL2 enable */
+ #define  RCC_CR_PLL2RDY                      ((uint32_t)0x08000000)        /*!< PLL2 clock ready flag */
+ #define  RCC_CR_PLL3ON                       ((uint32_t)0x10000000)        /*!< PLL3 enable */
+ #define  RCC_CR_PLL3RDY                      ((uint32_t)0x20000000)        /*!< PLL3 clock ready flag */
+#endif /* STM32F10X_CL */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)        /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */
+#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */
+#define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */
+#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#ifdef STM32F10X_CL
+ #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock * 4 */
+ #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock * 5 */
+ #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock * 6 */
+ #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock * 7 */
+ #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock * 8 */
+ #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock * 9 */
+ #define  RCC_CFGR_PLLMULL6_5                ((uint32_t)0x00340000)        /*!< PLL input clock * 6.5 */
+ 
+ #define  RCC_CFGR_OTGFSPRE                  ((uint32_t)0x00400000)        /*!< USB OTG FS prescaler */
+ 
+/*!< MCO configuration */
+ #define  RCC_CFGR_MCO                       ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+ #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+ #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+ #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
+ #define  RCC_CFGR_MCO_3                     ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+ #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source */
+ #define  RCC_CFGR_MCO_PLLCLK_Div2           ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+ #define  RCC_CFGR_MCO_PLL2CLK               ((uint32_t)0x08000000)        /*!< PLL2 clock selected as MCO source*/
+ #define  RCC_CFGR_MCO_PLL3CLK_Div2          ((uint32_t)0x09000000)        /*!< PLL3 clock divided by 2 selected as MCO source*/
+ #define  RCC_CFGR_MCO_Ext_HSE               ((uint32_t)0x0A000000)        /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+ #define  RCC_CFGR_MCO_PLL3CLK               ((uint32_t)0x0B000000)        /*!< PLL3 clock selected as MCO source */
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+ #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+ #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+ #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+ #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+ #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+ #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+ #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+ #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+ #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+ #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+ #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+ #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+ #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+ #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+ #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+ #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+ #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+ #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+ #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+#else
+ #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define  RCC_CFGR_PLLSRC_HSE                ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */
+
+ #define  RCC_CFGR_PLLXTPRE_HSE              ((uint32_t)0x00000000)        /*!< HSE clock not divided for PLL entry */
+ #define  RCC_CFGR_PLLXTPRE_HSE_Div2         ((uint32_t)0x00020000)        /*!< HSE clock divided by 2 for PLL entry */
+
+ #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+ #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+ #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+ #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+ #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+ #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+ #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+ #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+ #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+ #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+ #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+ #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+ #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+ #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+ #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+ #define  RCC_CFGR_USBPRE                    ((uint32_t)0x00400000)        /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+ #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+ #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+ #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+ #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+ #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+#endif /* STM32F10X_CL */
+
+/*!<******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+#ifdef STM32F10X_CL
+ #define  RCC_CIR_PLL2RDYF                    ((uint32_t)0x00000020)        /*!< PLL2 Ready Interrupt flag */
+ #define  RCC_CIR_PLL3RDYF                    ((uint32_t)0x00000040)        /*!< PLL3 Ready Interrupt flag */
+ #define  RCC_CIR_PLL2RDYIE                   ((uint32_t)0x00002000)        /*!< PLL2 Ready Interrupt Enable */
+ #define  RCC_CIR_PLL3RDYIE                   ((uint32_t)0x00004000)        /*!< PLL3 Ready Interrupt Enable */
+ #define  RCC_CIR_PLL2RDYC                    ((uint32_t)0x00200000)        /*!< PLL2 Ready Interrupt Clear */
+ #define  RCC_CIR_PLL3RDYC                    ((uint32_t)0x00400000)        /*!< PLL3 Ready Interrupt Clear */
+#endif /* STM32F10X_CL */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */
+#define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)        /*!< I/O port A reset */
+#define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)        /*!< I/O port B reset */
+#define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)        /*!< I/O port C reset */
+#define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)        /*!< I/O port D reset */
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB2RSTR_ADC2RST                ((uint32_t)0x00000400)        /*!< ADC 2 interface reset */
+#endif
+
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 Timer reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI 1 reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 Timer reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 Timer reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 Timer reset */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB2RSTR_IOPERST               ((uint32_t)0x00000040)        /*!< I/O port E reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
+ #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
+ #define  RCC_APB2RSTR_TIM8RST               ((uint32_t)0x00002000)        /*!< TIM8 Timer reset */
+ #define  RCC_APB2RSTR_ADC3RST               ((uint32_t)0x00008000)        /*!< ADC3 interface reset */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
+ #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
+#endif
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB2RSTR_TIM9RST               ((uint32_t)0x00080000)         /*!< TIM9 Timer reset */
+ #define  RCC_APB2RSTR_TIM10RST              ((uint32_t)0x00100000)         /*!< TIM10 Timer reset */
+ #define  RCC_APB2RSTR_TIM11RST              ((uint32_t)0x00200000)         /*!< TIM11 Timer reset */
+#endif /* STM32F10X_XL */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN1 reset */
+#endif
+
+#define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB1RSTR_TIM4RST               ((uint32_t)0x00000004)        /*!< Timer 4 reset */
+ #define  RCC_APB1RSTR_SPI2RST               ((uint32_t)0x00004000)        /*!< SPI 2 reset */
+ #define  RCC_APB1RSTR_USART3RST             ((uint32_t)0x00040000)        /*!< USART 3 reset */
+ #define  RCC_APB1RSTR_I2C2RST               ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined  (STM32F10X_XL)
+ #define  RCC_APB1RSTR_USBRST                ((uint32_t)0x00800000)        /*!< USB Device reset */
+#endif
+
+#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_XL)
+ #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+ #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+ #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+ #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
+ #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
+ #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
+ #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
+ #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+ #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+ #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
+ #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC interface reset */ 
+#endif
+
+#if defined  (STM32F10X_HD_VL)
+ #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+ #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< TIM12 Timer reset */
+ #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< TIM13 Timer reset */
+ #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< TIM14 Timer reset */
+ #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */ 
+ #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
+ #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */ 
+#endif
+
+#ifdef STM32F10X_CL
+ #define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)        /*!< CAN2 reset */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)         /*!< TIM12 Timer reset */
+ #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)         /*!< TIM13 Timer reset */
+ #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)         /*!< TIM14 Timer reset */
+#endif /* STM32F10X_XL */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMA1EN                   ((uint16_t)0x0001)            /*!< DMA1 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint16_t)0x0004)            /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint16_t)0x0010)            /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint16_t)0x0040)            /*!< CRC clock enable */
+
+/* CHIBIOS FIX */
+//#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL)
+#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL)
+ #define  RCC_AHBENR_DMA2EN                  ((uint16_t)0x0002)            /*!< DMA2 clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
+ #define  RCC_AHBENR_SDIOEN                  ((uint16_t)0x0400)            /*!< SDIO clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
+#endif
+
+#ifdef STM32F10X_CL
+ #define  RCC_AHBENR_OTGFSEN                 ((uint32_t)0x00001000)         /*!< USB OTG FS clock enable */
+ #define  RCC_AHBENR_ETHMACEN                ((uint32_t)0x00004000)         /*!< ETHERNET MAC clock enable */
+ #define  RCC_AHBENR_ETHMACTXEN              ((uint32_t)0x00008000)         /*!< ETHERNET MAC Tx clock enable */
+ #define  RCC_AHBENR_ETHMACRXEN              ((uint32_t)0x00010000)         /*!< ETHERNET MAC Rx clock enable */
+#endif /* STM32F10X_CL */
+
+/******************  Bit definition for RCC_APB2ENR register  *****************/
+#define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)         /*!< Alternate Function I/O clock enable */
+#define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)         /*!< I/O port A clock enable */
+#define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)         /*!< I/O port B clock enable */
+#define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)         /*!< I/O port C clock enable */
+#define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)         /*!< I/O port D clock enable */
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC 1 interface clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000400)         /*!< ADC 2 interface clock enable */
+#endif
+
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)         /*!< TIM1 Timer clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI 1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)         /*!< TIM15 Timer clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)         /*!< TIM16 Timer clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)         /*!< TIM17 Timer clock enable */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB2ENR_IOPEEN                 ((uint32_t)0x00000040)         /*!< I/O port E clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
+ #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
+ #define  RCC_APB2ENR_TIM8EN                 ((uint32_t)0x00002000)         /*!< TIM8 Timer clock enable */
+ #define  RCC_APB2ENR_ADC3EN                 ((uint32_t)0x00008000)         /*!< DMA1 clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
+ #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
+#endif
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB2ENR_TIM9EN                 ((uint32_t)0x00080000)         /*!< TIM9 Timer clock enable  */
+ #define  RCC_APB2ENR_TIM10EN                ((uint32_t)0x00100000)         /*!< TIM10 Timer clock enable  */
+ #define  RCC_APB2ENR_TIM11EN                ((uint32_t)0x00200000)         /*!< TIM11 Timer clock enable */
+#endif
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN1 clock enable */
+#endif
+
+#define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB1ENR_TIM4EN                 ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+ #define  RCC_APB1ENR_SPI2EN                 ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
+ #define  RCC_APB1ENR_USART3EN               ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
+ #define  RCC_APB1ENR_I2C2EN                 ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+/* CHIBIOS FIX */
+//#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)
+#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)
+ #define  RCC_APB1ENR_USBEN                  ((uint32_t)0x00800000)        /*!< USB Device clock enable */
+#endif
+
+/* CHIBIOS FIX */
+//#if defined (STM32F10X_HD) || defined  (STM32F10X_CL)
+#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined  (STM32F10X_CL)
+ #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+ #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+ #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+ #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
+ #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
+ #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
+ #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
+ #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+ #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+ #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+ #define  RCC_APB1ENR_CECEN                  ((uint32_t)0x40000000)        /*!< CEC interface clock enable */ 
+#endif
+
+#ifdef STM32F10X_HD_VL
+ #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+ #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
+ #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
+ #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
+ #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */ 
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_CL
+ #define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)        /*!< CAN2 clock enable */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
+#endif /* STM32F10X_XL */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/  
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+#ifdef STM32F10X_CL
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+ #define  RCC_AHBRSTR_OTGFSRST               ((uint32_t)0x00001000)         /*!< USB OTG FS reset */
+ #define  RCC_AHBRSTR_ETHMACRST              ((uint32_t)0x00004000)         /*!< ETHERNET MAC reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+ #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+ #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+ #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+ #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+ #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+ #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+ #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+ #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+ #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+ #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+ #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+ #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+ #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+ #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+ #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+ #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+ #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/*!< PREDIV2 configuration */
+ #define  RCC_CFGR2_PREDIV2                  ((uint32_t)0x000000F0)        /*!< PREDIV2[3:0] bits */
+ #define  RCC_CFGR2_PREDIV2_0                ((uint32_t)0x00000010)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PREDIV2_1                ((uint32_t)0x00000020)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PREDIV2_2                ((uint32_t)0x00000040)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PREDIV2_3                ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PREDIV2_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV2 input clock not divided */
+ #define  RCC_CFGR2_PREDIV2_DIV2             ((uint32_t)0x00000010)        /*!< PREDIV2 input clock divided by 2 */
+ #define  RCC_CFGR2_PREDIV2_DIV3             ((uint32_t)0x00000020)        /*!< PREDIV2 input clock divided by 3 */
+ #define  RCC_CFGR2_PREDIV2_DIV4             ((uint32_t)0x00000030)        /*!< PREDIV2 input clock divided by 4 */
+ #define  RCC_CFGR2_PREDIV2_DIV5             ((uint32_t)0x00000040)        /*!< PREDIV2 input clock divided by 5 */
+ #define  RCC_CFGR2_PREDIV2_DIV6             ((uint32_t)0x00000050)        /*!< PREDIV2 input clock divided by 6 */
+ #define  RCC_CFGR2_PREDIV2_DIV7             ((uint32_t)0x00000060)        /*!< PREDIV2 input clock divided by 7 */
+ #define  RCC_CFGR2_PREDIV2_DIV8             ((uint32_t)0x00000070)        /*!< PREDIV2 input clock divided by 8 */
+ #define  RCC_CFGR2_PREDIV2_DIV9             ((uint32_t)0x00000080)        /*!< PREDIV2 input clock divided by 9 */
+ #define  RCC_CFGR2_PREDIV2_DIV10            ((uint32_t)0x00000090)        /*!< PREDIV2 input clock divided by 10 */
+ #define  RCC_CFGR2_PREDIV2_DIV11            ((uint32_t)0x000000A0)        /*!< PREDIV2 input clock divided by 11 */
+ #define  RCC_CFGR2_PREDIV2_DIV12            ((uint32_t)0x000000B0)        /*!< PREDIV2 input clock divided by 12 */
+ #define  RCC_CFGR2_PREDIV2_DIV13            ((uint32_t)0x000000C0)        /*!< PREDIV2 input clock divided by 13 */
+ #define  RCC_CFGR2_PREDIV2_DIV14            ((uint32_t)0x000000D0)        /*!< PREDIV2 input clock divided by 14 */
+ #define  RCC_CFGR2_PREDIV2_DIV15            ((uint32_t)0x000000E0)        /*!< PREDIV2 input clock divided by 15 */
+ #define  RCC_CFGR2_PREDIV2_DIV16            ((uint32_t)0x000000F0)        /*!< PREDIV2 input clock divided by 16 */
+
+/*!< PLL2MUL configuration */
+ #define  RCC_CFGR2_PLL2MUL                  ((uint32_t)0x00000F00)        /*!< PLL2MUL[3:0] bits */
+ #define  RCC_CFGR2_PLL2MUL_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PLL2MUL_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PLL2MUL_2                ((uint32_t)0x00000400)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PLL2MUL_3                ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PLL2MUL8                 ((uint32_t)0x00000600)        /*!< PLL2 input clock * 8 */
+ #define  RCC_CFGR2_PLL2MUL9                 ((uint32_t)0x00000700)        /*!< PLL2 input clock * 9 */
+ #define  RCC_CFGR2_PLL2MUL10                ((uint32_t)0x00000800)        /*!< PLL2 input clock * 10 */
+ #define  RCC_CFGR2_PLL2MUL11                ((uint32_t)0x00000900)        /*!< PLL2 input clock * 11 */
+ #define  RCC_CFGR2_PLL2MUL12                ((uint32_t)0x00000A00)        /*!< PLL2 input clock * 12 */
+ #define  RCC_CFGR2_PLL2MUL13                ((uint32_t)0x00000B00)        /*!< PLL2 input clock * 13 */
+ #define  RCC_CFGR2_PLL2MUL14                ((uint32_t)0x00000C00)        /*!< PLL2 input clock * 14 */
+ #define  RCC_CFGR2_PLL2MUL16                ((uint32_t)0x00000E00)        /*!< PLL2 input clock * 16 */
+ #define  RCC_CFGR2_PLL2MUL20                ((uint32_t)0x00000F00)        /*!< PLL2 input clock * 20 */
+
+/*!< PLL3MUL configuration */
+ #define  RCC_CFGR2_PLL3MUL                  ((uint32_t)0x0000F000)        /*!< PLL3MUL[3:0] bits */
+ #define  RCC_CFGR2_PLL3MUL_0                ((uint32_t)0x00001000)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PLL3MUL_1                ((uint32_t)0x00002000)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PLL3MUL_2                ((uint32_t)0x00004000)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PLL3MUL_3                ((uint32_t)0x00008000)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PLL3MUL8                 ((uint32_t)0x00006000)        /*!< PLL3 input clock * 8 */
+ #define  RCC_CFGR2_PLL3MUL9                 ((uint32_t)0x00007000)        /*!< PLL3 input clock * 9 */
+ #define  RCC_CFGR2_PLL3MUL10                ((uint32_t)0x00008000)        /*!< PLL3 input clock * 10 */
+ #define  RCC_CFGR2_PLL3MUL11                ((uint32_t)0x00009000)        /*!< PLL3 input clock * 11 */
+ #define  RCC_CFGR2_PLL3MUL12                ((uint32_t)0x0000A000)        /*!< PLL3 input clock * 12 */
+ #define  RCC_CFGR2_PLL3MUL13                ((uint32_t)0x0000B000)        /*!< PLL3 input clock * 13 */
+ #define  RCC_CFGR2_PLL3MUL14                ((uint32_t)0x0000C000)        /*!< PLL3 input clock * 14 */
+ #define  RCC_CFGR2_PLL3MUL16                ((uint32_t)0x0000E000)        /*!< PLL3 input clock * 16 */
+ #define  RCC_CFGR2_PLL3MUL20                ((uint32_t)0x0000F000)        /*!< PLL3 input clock * 20 */
+
+ #define  RCC_CFGR2_PREDIV1SRC               ((uint32_t)0x00010000)        /*!< PREDIV1 entry clock source */
+ #define  RCC_CFGR2_PREDIV1SRC_PLL2          ((uint32_t)0x00010000)        /*!< PLL2 selected as PREDIV1 entry clock source */
+ #define  RCC_CFGR2_PREDIV1SRC_HSE           ((uint32_t)0x00000000)        /*!< HSE selected as PREDIV1 entry clock source */
+ #define  RCC_CFGR2_I2S2SRC                  ((uint32_t)0x00020000)        /*!< I2S2 entry clock source */
+ #define  RCC_CFGR2_I2S3SRC                  ((uint32_t)0x00040000)        /*!< I2S3 clock source */
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+ #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+ #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+ #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+ #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+ #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+ #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+ #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+ #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+ #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+ #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+ #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+ #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+ #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+ #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+ #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+ #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+ #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+#endif
+ 
+/******************************************************************************/
+/*                                                                            */
+/*                General Purpose and Alternate Function I/O                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CRL register  *******************/
+#define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for GPIO_CRH register  *******************/
+#define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/*!<******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR0                        ((uint16_t)0x0001)            /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1                        ((uint16_t)0x0002)            /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2                        ((uint16_t)0x0004)            /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3                        ((uint16_t)0x0008)            /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4                        ((uint16_t)0x0010)            /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5                        ((uint16_t)0x0020)            /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6                        ((uint16_t)0x0040)            /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7                        ((uint16_t)0x0080)            /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8                        ((uint16_t)0x0100)            /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9                        ((uint16_t)0x0200)            /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10                       ((uint16_t)0x0400)            /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11                       ((uint16_t)0x0800)            /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12                       ((uint16_t)0x1000)            /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13                       ((uint16_t)0x2000)            /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14                       ((uint16_t)0x4000)            /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15                       ((uint16_t)0x8000)            /*!< Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR0                        ((uint16_t)0x0001)            /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1                        ((uint16_t)0x0002)            /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2                        ((uint16_t)0x0004)            /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3                        ((uint16_t)0x0008)            /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4                        ((uint16_t)0x0010)            /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5                        ((uint16_t)0x0020)            /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6                        ((uint16_t)0x0040)            /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7                        ((uint16_t)0x0080)            /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8                        ((uint16_t)0x0100)            /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9                        ((uint16_t)0x0200)            /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10                       ((uint16_t)0x0400)            /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11                       ((uint16_t)0x0800)            /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12                       ((uint16_t)0x1000)            /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13                       ((uint16_t)0x2000)            /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14                       ((uint16_t)0x4000)            /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15                       ((uint16_t)0x8000)            /*!< Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSRR register  *******************/
+#define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BRR register  *******************/
+#define GPIO_BRR_BR0                         ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1                         ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2                         ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3                         ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4                         ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5                         ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6                         ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7                         ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8                         ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9                         ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10                        ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11                        ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12                        ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13                        ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14                        ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15                        ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for AFIO_EVCR register  *******************/
+#define AFIO_EVCR_PIN                        ((uint8_t)0x0F)               /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0                      ((uint8_t)0x01)               /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1                      ((uint8_t)0x02)               /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2                      ((uint8_t)0x04)               /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3                      ((uint8_t)0x08)               /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0                    ((uint8_t)0x00)               /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1                    ((uint8_t)0x01)               /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2                    ((uint8_t)0x02)               /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3                    ((uint8_t)0x03)               /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4                    ((uint8_t)0x04)               /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5                    ((uint8_t)0x05)               /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6                    ((uint8_t)0x06)               /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7                    ((uint8_t)0x07)               /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8                    ((uint8_t)0x08)               /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9                    ((uint8_t)0x09)               /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10                   ((uint8_t)0x0A)               /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11                   ((uint8_t)0x0B)               /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12                   ((uint8_t)0x0C)               /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13                   ((uint8_t)0x0D)               /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14                   ((uint8_t)0x0E)               /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15                   ((uint8_t)0x0F)               /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT                       ((uint8_t)0x70)               /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0                     ((uint8_t)0x10)               /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1                     ((uint8_t)0x20)               /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2                     ((uint8_t)0x40)               /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA                    ((uint8_t)0x00)               /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB                    ((uint8_t)0x10)               /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC                    ((uint8_t)0x20)               /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD                    ((uint8_t)0x30)               /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE                    ((uint8_t)0x40)               /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE                       ((uint8_t)0x80)               /*!< Event Output Enable */
+
+/******************  Bit definition for AFIO_MAPR register  *******************/
+#define AFIO_MAPR_SPI1_REMAP                 ((uint32_t)0x00000001)        /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP               ((uint32_t)0x00000004)        /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP               ((uint32_t)0x00000008)        /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP               ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1             ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP                 ((uint32_t)0x00001000)        /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP                  ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0                ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define AFIO_MAPR_CAN_REMAP_1                ((uint32_t)0x00004000)        /*!< Bit 1 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2           ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3           ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP             ((uint32_t)0x00010000)        /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((uint32_t)0x00020000)        /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((uint32_t)0x00040000)        /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((uint32_t)0x00080000)        /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((uint32_t)0x00100000)        /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+#ifdef STM32F10X_CL
+/*!< ETH_REMAP configuration */
+ #define AFIO_MAPR_ETH_REMAP                  ((uint32_t)0x00200000)        /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
+
+/*!< CAN2_REMAP configuration */
+ #define AFIO_MAPR_CAN2_REMAP                 ((uint32_t)0x00400000)        /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
+
+/*!< MII_RMII_SEL configuration */
+ #define AFIO_MAPR_MII_RMII_SEL               ((uint32_t)0x00800000)        /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
+
+/*!< SPI3_REMAP configuration */
+ #define AFIO_MAPR_SPI3_REMAP                 ((uint32_t)0x10000000)        /*!< SPI3_REMAP bit (SPI3 remapping) */
+
+/*!< TIM2ITR1_IREMAP configuration */
+ #define AFIO_MAPR_TIM2ITR1_IREMAP            ((uint32_t)0x20000000)        /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
+
+/*!< PTP_PPS_REMAP configuration */
+ #define AFIO_MAPR_PTP_PPS_REMAP              ((uint32_t)0x40000000)        /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+#endif
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTICR1_EXTI0                   ((uint16_t)0x000F)            /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1                   ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2                   ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3                   ((uint16_t)0xF000)            /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA                ((uint16_t)0x0000)            /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB                ((uint16_t)0x0001)            /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC                ((uint16_t)0x0002)            /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD                ((uint16_t)0x0003)            /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE                ((uint16_t)0x0004)            /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF                ((uint16_t)0x0005)            /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG                ((uint16_t)0x0006)            /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA                ((uint16_t)0x0000)            /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB                ((uint16_t)0x0010)            /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC                ((uint16_t)0x0020)            /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD                ((uint16_t)0x0030)            /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE                ((uint16_t)0x0040)            /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF                ((uint16_t)0x0050)            /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG                ((uint16_t)0x0060)            /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */  
+#define AFIO_EXTICR1_EXTI2_PA                ((uint16_t)0x0000)            /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB                ((uint16_t)0x0100)            /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC                ((uint16_t)0x0200)            /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD                ((uint16_t)0x0300)            /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE                ((uint16_t)0x0400)            /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF                ((uint16_t)0x0500)            /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG                ((uint16_t)0x0600)            /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA                ((uint16_t)0x0000)            /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB                ((uint16_t)0x1000)            /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC                ((uint16_t)0x2000)            /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD                ((uint16_t)0x3000)            /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE                ((uint16_t)0x4000)            /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF                ((uint16_t)0x5000)            /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG                ((uint16_t)0x6000)            /*!< PG[3] pin */
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTICR2_EXTI4                   ((uint16_t)0x000F)            /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5                   ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6                   ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7                   ((uint16_t)0xF000)            /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA                ((uint16_t)0x0000)            /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB                ((uint16_t)0x0001)            /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC                ((uint16_t)0x0002)            /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD                ((uint16_t)0x0003)            /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE                ((uint16_t)0x0004)            /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF                ((uint16_t)0x0005)            /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG                ((uint16_t)0x0006)            /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA                ((uint16_t)0x0000)            /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB                ((uint16_t)0x0010)            /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC                ((uint16_t)0x0020)            /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD                ((uint16_t)0x0030)            /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE                ((uint16_t)0x0040)            /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF                ((uint16_t)0x0050)            /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG                ((uint16_t)0x0060)            /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */  
+#define AFIO_EXTICR2_EXTI6_PA                ((uint16_t)0x0000)            /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB                ((uint16_t)0x0100)            /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC                ((uint16_t)0x0200)            /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD                ((uint16_t)0x0300)            /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE                ((uint16_t)0x0400)            /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF                ((uint16_t)0x0500)            /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG                ((uint16_t)0x0600)            /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA                ((uint16_t)0x0000)            /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB                ((uint16_t)0x1000)            /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC                ((uint16_t)0x2000)            /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD                ((uint16_t)0x3000)            /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE                ((uint16_t)0x4000)            /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF                ((uint16_t)0x5000)            /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG                ((uint16_t)0x6000)            /*!< PG[7] pin */
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTICR3_EXTI8                   ((uint16_t)0x000F)            /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9                   ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10                  ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11                  ((uint16_t)0xF000)            /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA                ((uint16_t)0x0000)            /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB                ((uint16_t)0x0001)            /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC                ((uint16_t)0x0002)            /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD                ((uint16_t)0x0003)            /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE                ((uint16_t)0x0004)            /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF                ((uint16_t)0x0005)            /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG                ((uint16_t)0x0006)            /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA                ((uint16_t)0x0000)            /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB                ((uint16_t)0x0010)            /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC                ((uint16_t)0x0020)            /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD                ((uint16_t)0x0030)            /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE                ((uint16_t)0x0040)            /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF                ((uint16_t)0x0050)            /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG                ((uint16_t)0x0060)            /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */  
+#define AFIO_EXTICR3_EXTI10_PA               ((uint16_t)0x0000)            /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB               ((uint16_t)0x0100)            /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC               ((uint16_t)0x0200)            /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD               ((uint16_t)0x0300)            /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE               ((uint16_t)0x0400)            /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF               ((uint16_t)0x0500)            /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG               ((uint16_t)0x0600)            /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA               ((uint16_t)0x0000)            /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB               ((uint16_t)0x1000)            /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC               ((uint16_t)0x2000)            /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD               ((uint16_t)0x3000)            /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE               ((uint16_t)0x4000)            /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF               ((uint16_t)0x5000)            /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG               ((uint16_t)0x6000)            /*!< PG[11] pin */
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTICR4_EXTI12                  ((uint16_t)0x000F)            /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13                  ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14                  ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15                  ((uint16_t)0xF000)            /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA               ((uint16_t)0x0000)            /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB               ((uint16_t)0x0001)            /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC               ((uint16_t)0x0002)            /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD               ((uint16_t)0x0003)            /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE               ((uint16_t)0x0004)            /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF               ((uint16_t)0x0005)            /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG               ((uint16_t)0x0006)            /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA               ((uint16_t)0x0000)            /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB               ((uint16_t)0x0010)            /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC               ((uint16_t)0x0020)            /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD               ((uint16_t)0x0030)            /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE               ((uint16_t)0x0040)            /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF               ((uint16_t)0x0050)            /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG               ((uint16_t)0x0060)            /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */  
+#define AFIO_EXTICR4_EXTI14_PA               ((uint16_t)0x0000)            /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB               ((uint16_t)0x0100)            /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC               ((uint16_t)0x0200)            /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD               ((uint16_t)0x0300)            /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE               ((uint16_t)0x0400)            /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF               ((uint16_t)0x0500)            /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG               ((uint16_t)0x0600)            /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA               ((uint16_t)0x0000)            /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB               ((uint16_t)0x1000)            /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC               ((uint16_t)0x2000)            /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD               ((uint16_t)0x3000)            /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE               ((uint16_t)0x4000)            /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF               ((uint16_t)0x5000)            /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG               ((uint16_t)0x6000)            /*!< PG[15] pin */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/******************  Bit definition for AFIO_MAPR2 register  ******************/
+#define AFIO_MAPR2_TIM15_REMAP               ((uint32_t)0x00000001)        /*!< TIM15 remapping */
+#define AFIO_MAPR2_TIM16_REMAP               ((uint32_t)0x00000002)        /*!< TIM16 remapping */
+#define AFIO_MAPR2_TIM17_REMAP               ((uint32_t)0x00000004)        /*!< TIM17 remapping */
+#define AFIO_MAPR2_CEC_REMAP                 ((uint32_t)0x00000008)        /*!< CEC remapping */
+#define AFIO_MAPR2_TIM1_DMA_REMAP            ((uint32_t)0x00000010)        /*!< TIM1_DMA remapping */
+#endif
+
+#ifdef STM32F10X_HD_VL
+#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP       ((uint32_t)0x00000800)        /*!< TIM6/TIM7 and DAC DMA remapping */
+#define AFIO_MAPR2_TIM12_REMAP               ((uint32_t)0x00001000)        /*!< TIM12 remapping */
+#define AFIO_MAPR2_MISC_REMAP                ((uint32_t)0x00002000)        /*!< Miscellaneous remapping */
+#endif
+
+#ifdef STM32F10X_XL 
+/******************  Bit definition for AFIO_MAPR2 register  ******************/
+#define AFIO_MAPR2_TIM9_REMAP                ((uint32_t)0x00000020)        /*!< TIM9 remapping */
+#define AFIO_MAPR2_TIM10_REMAP               ((uint32_t)0x00000040)        /*!< TIM10 remapping */
+#define AFIO_MAPR2_TIM11_REMAP               ((uint32_t)0x00000080)        /*!< TIM11 remapping */
+#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
+#endif
+
+/******************************************************************************/
+/*                                                                            */
+/*                               SystemTick                                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SysTick_CTRL register  *****************/
+#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
+#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
+#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
+#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
+
+/*****************  Bit definition for SysTick_LOAD register  *****************/
+#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/*****************  Bit definition for SysTick_VAL register  ******************/
+#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
+
+/*****************  Bit definition for SysTick_CALIB register  ****************/
+#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
+#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
+#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/*                                                                            */
+/*                  Nested Vectored Interrupt Controller                      */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for NVIC_ISER register  *******************/
+#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
+#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICER register  *******************/
+#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
+#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ISPR register  *******************/
+#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
+#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICPR register  *******************/
+#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
+#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_IABR register  *******************/
+#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
+#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_PRI0 register  *******************/
+#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
+#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
+#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
+#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
+
+/******************  Bit definition for NVIC_PRI1 register  *******************/
+#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
+#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
+#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
+#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
+
+/******************  Bit definition for NVIC_PRI2 register  *******************/
+#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
+#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
+#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
+#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
+
+/******************  Bit definition for NVIC_PRI3 register  *******************/
+#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
+#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
+#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
+#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
+
+/******************  Bit definition for NVIC_PRI4 register  *******************/
+#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
+#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
+#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
+#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
+
+/******************  Bit definition for NVIC_PRI5 register  *******************/
+#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
+#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
+#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
+#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
+
+/******************  Bit definition for NVIC_PRI6 register  *******************/
+#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
+#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
+#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
+#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
+
+/******************  Bit definition for NVIC_PRI7 register  *******************/
+#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
+#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
+#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
+#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
+
+/******************  Bit definition for SCB_CPUID register  *******************/
+#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
+#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
+#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
+#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
+#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
+
+/*******************  Bit definition for SCB_ICSR register  *******************/
+#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
+#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
+#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
+#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
+#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
+#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
+#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
+#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
+
+/*******************  Bit definition for SCB_VTOR register  *******************/
+#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
+#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
+
+/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
+#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
+#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
+#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
+
+#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
+#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
+
+/* prority group configuration */
+#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
+#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/*******************  Bit definition for SCB_SCR register  ********************/
+#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
+#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
+#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
+
+/********************  Bit definition for SCB_CCR register  *******************/
+#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
+#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
+#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
+#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/*******************  Bit definition for SCB_SHPR register ********************/
+#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/******************  Bit definition for SCB_SHCSR register  *******************/
+#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
+#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
+#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
+#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
+#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
+#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
+#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
+#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
+#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
+#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
+#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
+#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
+#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
+#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
+
+/*******************  Bit definition for SCB_CFSR register  *******************/
+/*!< MFSR */
+#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
+#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
+#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
+#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
+#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
+#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
+#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
+#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
+#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
+#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to execute an undefined instruction */
+#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
+#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
+#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
+#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/*******************  Bit definition for SCB_HFSR register  *******************/
+#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occurs because of vector table read on exception processing */
+#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
+
+/*******************  Bit definition for SCB_DFSR register  *******************/
+#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
+#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
+#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
+#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
+#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
+
+/*******************  Bit definition for SCB_MMFAR register  ******************/
+#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
+
+/*******************  Bit definition for SCB_BFAR register  *******************/
+#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
+
+/*******************  Bit definition for SCB_afsr register  *******************/
+#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR1 register  *******************/
+#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
+#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
+#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR2 register  *******************/
+#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR3 register  *******************/
+#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*!<******************  Bit definition for DMA_CCR4 register  *******************/
+#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/******************  Bit definition for DMA_CCR5 register  *******************/
+#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CCR6 register  *******************/
+#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR7 register  *******************/
+#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNDTR1 register  ******************/
+#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR2 register  ******************/
+#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR3 register  ******************/
+#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR4 register  ******************/
+#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR5 register  ******************/
+#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR6 register  ******************/
+#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR7 register  ******************/
+#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CPAR1 register  *******************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR2 register  *******************/
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR3 register  *******************/
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR4 register  *******************/
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR5 register  *******************/
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR6 register  *******************/
+#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR7 register  *******************/
+#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CMAR1 register  *******************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR2 register  *******************/
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR3 register  *******************/
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+
+/******************  Bit definition for DMA_CMAR4 register  *******************/
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR5 register  *******************/
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR6 register  *******************/
+#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR7 register  *******************/
+#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!< Analog watchdog flag */
+#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!< End of conversion */
+#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!< Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!< Injected channel Start flag */
+#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!< Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
+
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  ADC_CR1_DUALMOD                     ((uint32_t)0x000F0000)        /*!< DUALMOD[3:0] bits (Dual mode selection) */
+#define  ADC_CR1_DUALMOD_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  ADC_CR1_DUALMOD_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  ADC_CR1_DUALMOD_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  ADC_CR1_DUALMOD_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
+
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
+#define  ADC_CR2_CAL                         ((uint32_t)0x00000004)        /*!< A/D Calibration */
+#define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)        /*!< Reset Calibration */
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
+
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)        /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)        /*!< External Trigger Conversion mode for injected channels */
+
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+#define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)        /*!< External Trigger Conversion mode for regular channels */
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)        /*!< Start Conversion of injected channels */
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)        /*!< Start Conversion of regular channels */
+#define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!< ADC2 data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    CEC                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CEC_CFGR register  ******************/
+#define  CEC_CFGR_PE              ((uint16_t)0x0001)     /*!<  Peripheral Enable */
+#define  CEC_CFGR_IE              ((uint16_t)0x0002)     /*!<  Interrupt Enable */
+#define  CEC_CFGR_BTEM            ((uint16_t)0x0004)     /*!<  Bit Timing Error Mode */
+#define  CEC_CFGR_BPEM            ((uint16_t)0x0008)     /*!<  Bit Period Error Mode */
+
+/********************  Bit definition for CEC_OAR register  ******************/
+#define  CEC_OAR_OA               ((uint16_t)0x000F)     /*!<  OA[3:0]: Own Address */
+#define  CEC_OAR_OA_0             ((uint16_t)0x0001)     /*!<  Bit 0 */
+#define  CEC_OAR_OA_1             ((uint16_t)0x0002)     /*!<  Bit 1 */
+#define  CEC_OAR_OA_2             ((uint16_t)0x0004)     /*!<  Bit 2 */
+#define  CEC_OAR_OA_3             ((uint16_t)0x0008)     /*!<  Bit 3 */
+
+/********************  Bit definition for CEC_PRES register  ******************/
+#define  CEC_PRES_PRES            ((uint16_t)0x3FFF)   /*!<  Prescaler Counter Value */
+
+/********************  Bit definition for CEC_ESR register  ******************/
+#define  CEC_ESR_BTE              ((uint16_t)0x0001)     /*!<  Bit Timing Error */
+#define  CEC_ESR_BPE              ((uint16_t)0x0002)     /*!<  Bit Period Error */
+#define  CEC_ESR_RBTFE            ((uint16_t)0x0004)     /*!<  Rx Block Transfer Finished Error */
+#define  CEC_ESR_SBE              ((uint16_t)0x0008)     /*!<  Start Bit Error */
+#define  CEC_ESR_ACKE             ((uint16_t)0x0010)     /*!<  Block Acknowledge Error */
+#define  CEC_ESR_LINE             ((uint16_t)0x0020)     /*!<  Line Error */
+#define  CEC_ESR_TBTFE            ((uint16_t)0x0040)     /*!<  Tx Block Transfer Finished Error */
+
+/********************  Bit definition for CEC_CSR register  ******************/
+#define  CEC_CSR_TSOM             ((uint16_t)0x0001)     /*!<  Tx Start Of Message */
+#define  CEC_CSR_TEOM             ((uint16_t)0x0002)     /*!<  Tx End Of Message */
+#define  CEC_CSR_TERR             ((uint16_t)0x0004)     /*!<  Tx Error */
+#define  CEC_CSR_TBTRF            ((uint16_t)0x0008)     /*!<  Tx Byte Transfer Request or Block Transfer Finished */
+#define  CEC_CSR_RSOM             ((uint16_t)0x0010)     /*!<  Rx Start Of Message */
+#define  CEC_CSR_REOM             ((uint16_t)0x0020)     /*!<  Rx End Of Message */
+#define  CEC_CSR_RERR             ((uint16_t)0x0040)     /*!<  Rx Error */
+#define  CEC_CSR_RBTF             ((uint16_t)0x0080)     /*!<  Rx Block Transfer Finished */
+
+/********************  Bit definition for CEC_TXD register  ******************/
+#define  CEC_TXD_TXD              ((uint16_t)0x00FF)     /*!<  Tx Data register */
+
+/********************  Bit definition for CEC_RXD register  ******************/
+#define  CEC_RXD_RXD              ((uint16_t)0x00FF)     /*!<  Rx Data register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!< Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!< Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!< Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!< One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!< Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!< Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!< Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!< Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!< CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!< Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!< Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!< Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!< MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!< TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!< Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!< Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!< Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!< Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!< Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!< Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!< Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!< SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!< TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!< Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!< ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!< Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!< External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!< External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!< Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!< COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!< Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!< Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!< Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!< Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!< Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!< Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!< COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!< Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!< Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!< COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!< Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!< Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!< Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!< Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!< Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!< Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!< Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!< Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!< Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!< Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!< Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!< Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!< Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!< Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!< Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!< Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!< Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!< Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!< Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!< Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!< Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!< Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!< Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!< Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!< Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!< Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!< Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!< Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!< Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!< Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!< Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!< Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!< Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!< Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!< Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!< Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!< Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!< Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!< Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!< Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!< actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!< Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!< LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!< Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!< Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!< Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!< Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!< Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!< Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!< DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!< DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!< Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!< DMA register for burst accesses */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Real-Time Clock                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for RTC_CRH register  ********************/
+#define  RTC_CRH_SECIE                       ((uint8_t)0x01)               /*!< Second Interrupt Enable */
+#define  RTC_CRH_ALRIE                       ((uint8_t)0x02)               /*!< Alarm Interrupt Enable */
+#define  RTC_CRH_OWIE                        ((uint8_t)0x04)               /*!< OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CRL register  ********************/
+#define  RTC_CRL_SECF                        ((uint8_t)0x01)               /*!< Second Flag */
+#define  RTC_CRL_ALRF                        ((uint8_t)0x02)               /*!< Alarm Flag */
+#define  RTC_CRL_OWF                         ((uint8_t)0x04)               /*!< OverfloW Flag */
+#define  RTC_CRL_RSF                         ((uint8_t)0x08)               /*!< Registers Synchronized Flag */
+#define  RTC_CRL_CNF                         ((uint8_t)0x10)               /*!< Configuration Flag */
+#define  RTC_CRL_RTOFF                       ((uint8_t)0x20)               /*!< RTC operation OFF */
+
+/*******************  Bit definition for RTC_PRLH register  *******************/
+#define  RTC_PRLH_PRL                        ((uint16_t)0x000F)            /*!< RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_PRLL register  *******************/
+#define  RTC_PRLL_PRL                        ((uint16_t)0xFFFF)            /*!< RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /*!< RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /*!< RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALRH register  *******************/
+#define  RTC_ALRH_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALRL register  *******************/
+#define  RTC_ALRL_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Flexible Static Memory Controller                    */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for FSMC_BCR1 register  *******************/
+#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR2 register  *******************/
+#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR3 register  *******************/
+#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
+#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR4 register  *******************/
+#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BTR1 register  ******************/
+#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR2 register  *******************/
+#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for FSMC_BTR3 register  *******************/
+#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR4 register  *******************/
+#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR1 register  ******************/
+#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR2 register  ******************/
+#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
+#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR3 register  ******************/
+#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR4 register  ******************/
+#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_PCR2 register  *******************/
+#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[1:0] bits (ECC page size) */
+#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/******************  Bit definition for FSMC_PCR3 register  *******************/
+#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/******************  Bit definition for FSMC_PCR4 register  *******************/
+#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/*******************  Bit definition for FSMC_SR2 register  *******************/
+#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
+
+/*******************  Bit definition for FSMC_SR3 register  *******************/
+#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
+
+/*******************  Bit definition for FSMC_SR4 register  *******************/
+#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
+
+/******************  Bit definition for FSMC_PMEM2 register  ******************/
+#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM3 register  ******************/
+#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM4 register  ******************/
+#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PATT2 register  ******************/
+#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PATT3 register  ******************/
+#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PATT4 register  ******************/
+#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PIO4 register  *******************/
+#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_ECCR2 register  ******************/
+#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
+
+/******************  Bit definition for FSMC_ECCR3 register  ******************/
+#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
+#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
+#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
+#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
+
+#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
+
+#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
+
+#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
+
+#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
+#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
+#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
+#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
+#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
+#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
+#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
+
+#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
+#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
+#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
+#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
+#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
+#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
+#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
+#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
+#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
+#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
+#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
+#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
+#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
+#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
+#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
+#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
+#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
+#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
+#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
+#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
+#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
+#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
+#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
+#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
+#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
+#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
+#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
+#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
+#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
+#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
+#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
+#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
+#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
+#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
+#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
+#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
+#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
+#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
+#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
+#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
+#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   USB Device FS                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+/*******************  Bit definition for USB_EP0R register  *******************/
+#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP1R register  *******************/
+#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP2R register  *******************/
+#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP3R register  *******************/
+#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP4R register  *******************/
+#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP5R register  *******************/
+#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP6R register  *******************/
+#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP7R register  *******************/
+#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/*******************  Bit definition for USB_CNTR register  *******************/
+#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!< Force USB Reset */
+#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!< Power down */
+#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!< Low-power mode */
+#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!< Force suspend */
+#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!< Resume request */
+#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!< Expected Start Of Frame Interrupt Mask */
+#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!< Start Of Frame Interrupt Mask */
+#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!< RESET Interrupt Mask */
+#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!< Suspend mode Interrupt Mask */
+#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!< Wakeup Interrupt Mask */
+#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!< Error Interrupt Mask */
+#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!< Correct Transfer Interrupt Mask */
+
+/*******************  Bit definition for USB_ISTR register  *******************/
+#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!< Endpoint Identifier */
+#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!< Direction of transaction */
+#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!< Expected Start Of Frame */
+#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!< Start Of Frame */
+#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!< USB RESET request */
+#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!< Suspend mode request */
+#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!< Wake up */
+#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!< Error */
+#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun */
+#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!< Correct Transfer */
+
+/*******************  Bit definition for USB_FNR register  ********************/
+#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!< Frame Number */
+#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!< Lost SOF */
+#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!< Locked */
+#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!< Receive Data - Line Status */
+#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!< Receive Data + Line Status */
+
+/******************  Bit definition for USB_DADDR register  *******************/
+#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!< ADD[6:0] bits (Device Address) */
+#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!< Bit 0 */
+#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!< Bit 1 */
+#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!< Bit 2 */
+#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!< Bit 3 */
+#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!< Bit 4 */
+#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!< Bit 5 */
+#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!< Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/    
+#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!< Initialization Request */
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!< Sleep Mode Request */
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!< Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!< Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!< No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!< Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!< Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!< Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!< CAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!< Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!< Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!< Error Interrupt */
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!< Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!< Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!< Transmit Mode */
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!< Receive Mode */
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!< Last Sample Point */
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!< CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!< Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!< Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!< Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!< Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!< Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!< Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!< Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!< Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!< Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!< Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!< Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!< Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!< Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!< Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!< Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!< Mailbox Code */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!< TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!< Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!< Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!< Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!< LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!< Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!< Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!< Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!< FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!< FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!< FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!< Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!< FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!< FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!< FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!< Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!< FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!< FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!< FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!< FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!< FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!< FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!< Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!< Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!< Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!< Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!< Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!< Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!< Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!< Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!< Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!< Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!< LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!< Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!< Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!< Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!< Time Segment 1 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!< Time Segment 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!< Resynchronization Jump Width */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!< Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!< Silent Mode */
+
+/*!< Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!< Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!< Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!< Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!< Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!< Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!< Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!< Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!< Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!< Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!< Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!< Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!< Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!< Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!< Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!< Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!< Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!< Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!< Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!< Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!< Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!< Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!< Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!< Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!< Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!< Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!< Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!< Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!< Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!< Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!< Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!< Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!< Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!< Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!< Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!< Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!< Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!< Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!< Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!< Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!< Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!< Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!< Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!< Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!< Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!< Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!< Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!< Filter Active */
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!< Filter 0 Active */
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!< Filter 1 Active */
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!< Filter 2 Active */
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!< Filter 3 Active */
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!< Filter 4 Active */
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!< Filter 5 Active */
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!< Filter 6 Active */
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!< Filter 7 Active */
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!< Filter 8 Active */
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!< Filter 9 Active */
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!< Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!< Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!< Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!< Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
+#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!< Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!< Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!< Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!< steady state clock polarity */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!< PCM frame synchronization */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!< I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!< I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!< I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!< Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
+#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
+#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
+#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
+#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
+#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
+#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
+#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
+#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
+#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
+#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
+#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
+#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
+
+#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
+#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
+#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
+#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
+#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
+
+#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
+#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
+#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
+
+#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
+#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
+#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
+#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
+#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
+#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
+#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
+#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
+#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
+#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
+#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
+#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
+#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
+#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
+#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
+#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
+#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
+#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
+#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
+#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_SR register  *******************/
+#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
+#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
+#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
+#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
+#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
+#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
+#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
+#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
+#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
+#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
+#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
+#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
+#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
+#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
+#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< USART Oversmapling 8-bits */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
+#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
+
+#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
+#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
+#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One Bit method */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DBGMCU_CR_DBG_IWDG_STOP             ((uint32_t)0x00000100)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_CR_DBG_WWDG_STOP             ((uint32_t)0x00000200)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM1_STOP             ((uint32_t)0x00000400)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM2_STOP             ((uint32_t)0x00000800)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM3_STOP             ((uint32_t)0x00001000)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM4_STOP             ((uint32_t)0x00002000)        /*!< TIM4 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_CAN1_STOP             ((uint32_t)0x00004000)        /*!< Debug CAN1 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)        /*!< SMBUS timeout mode stopped when Core is halted */
+#define  DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)        /*!< SMBUS timeout mode stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM8_STOP             ((uint32_t)0x00020000)        /*!< TIM8 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM5_STOP             ((uint32_t)0x00040000)        /*!< TIM5 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM6_STOP             ((uint32_t)0x00080000)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM7_STOP             ((uint32_t)0x00100000)        /*!< TIM7 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_CAN2_STOP             ((uint32_t)0x00200000)        /*!< Debug CAN2 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM15_STOP            ((uint32_t)0x00400000)        /*!< Debug TIM15 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM16_STOP            ((uint32_t)0x00800000)        /*!< Debug TIM16 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM17_STOP            ((uint32_t)0x01000000)        /*!< Debug TIM17 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM12_STOP            ((uint32_t)0x02000000)        /*!< Debug TIM12 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM13_STOP            ((uint32_t)0x04000000)        /*!< Debug TIM13 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM14_STOP            ((uint32_t)0x08000000)        /*!< Debug TIM14 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM9_STOP             ((uint32_t)0x10000000)        /*!< Debug TIM9 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM10_STOP            ((uint32_t)0x20000000)        /*!< Debug TIM10 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM11_STOP            ((uint32_t)0x40000000)        /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
+#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x00)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x01)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_2                 ((uint8_t)0x02)               /*!< Bit 1 */
+
+#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
+#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)               /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint8_t)0x01)               /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint8_t)0x04)               /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint8_t)0x10)               /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint8_t)0x20)               /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint16_t)0x0001)            /*!< Programming */
+#define  FLASH_CR_PER                        ((uint16_t)0x0002)            /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint16_t)0x0004)            /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint16_t)0x0010)            /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint16_t)0x0020)            /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint16_t)0x0040)            /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint16_t)0x0080)            /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint16_t)0x0200)            /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint16_t)0x0400)            /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint16_t)0x1000)            /*!< End of operation interrupt enable */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint16_t)0x0001)            /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT                     ((uint16_t)0x0002)            /*!< Read protection */
+
+#define  FLASH_OBR_USER                      ((uint16_t)0x03FC)            /*!< User Option Bytes */
+#define  FLASH_OBR_WDG_SW                    ((uint16_t)0x0004)            /*!< WDG_SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint16_t)0x0008)            /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint16_t)0x0010)            /*!< nRST_STDBY */
+#define  FLASH_OBR_BFB2                      ((uint16_t)0x0020)            /*!< BFB2 */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for FLASH_RDP register  *******************/
+#define  FLASH_RDP_RDP                       ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  FLASH_RDP_nRDP                      ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for FLASH_USER register  ******************/
+#define  FLASH_USER_USER                     ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  FLASH_USER_nUSER                    ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for FLASH_Data0 register  *****************/
+#define  FLASH_Data0_Data0                   ((uint32_t)0x000000FF)        /*!< User data storage option byte */
+#define  FLASH_Data0_nData0                  ((uint32_t)0x0000FF00)        /*!< User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_Data1 register  *****************/
+#define  FLASH_Data1_Data1                   ((uint32_t)0x00FF0000)        /*!< User data storage option byte */
+#define  FLASH_Data1_nData1                  ((uint32_t)0xFF000000)        /*!< User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_WRP0 register  ******************/
+#define  FLASH_WRP0_WRP0                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP0_nWRP0                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP1 register  ******************/
+#define  FLASH_WRP1_WRP1                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP1_nWRP1                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP2 register  ******************/
+#define  FLASH_WRP2_WRP2                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP2_nWRP2                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP3 register  ******************/
+#define  FLASH_WRP3_WRP3                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP3_nWRP3                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+#ifdef STM32F10X_CL
+/******************************************************************************/
+/*                Ethernet MAC Registers bits definitions                     */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
+#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
+#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
+  #define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
+#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
+#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
+#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
+#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
+#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
+#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
+#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
+#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM 	  ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
+#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
+#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
+#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
+  
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
+#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
+#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
+#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
+#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
+#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
+#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
+#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
+#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
+#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
+#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
+#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
+#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
+#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
+#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
+#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
+#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+#endif /* STM32F10X_CL */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f10x_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/stm32f30x.h b/os/ext/CMSIS/ST/stm32f30x.h
new file mode 100644
index 000000000..1c1f66f79
--- /dev/null
+++ b/os/ext/CMSIS/ST/stm32f30x.h
@@ -0,0 +1,6213 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    04-September-2012
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral registers definitions, bits 
+  *          definitions and memory mapping for STM32F30x devices.
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral�s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral registers declarations and bits definition
+  *           - Macros to access peripheral registers hardware
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f30x
+  * @{
+  */
+    
+#ifndef __STM32F30x_H
+#define __STM32F30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F30X) 
+/*  #define STM32F30X */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined (STM32F30X)
+ #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)"
+#endif
+
+#if !defined  (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */           
+#if !defined  (HSE_VALUE) 
+ #define HSE_VALUE            ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT) 
+ #define HSE_STARTUP_TIMEOUT  ((uint16_t)0x0500)   /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
+   Timeout value 
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT) 
+ #define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */  
+
+#if !defined  (HSI_VALUE) 
+ #define HSI_VALUE  ((uint32_t)8000000)
+#endif /* HSI_VALUE */                      /*!< Value of the Internal High Speed oscillator in Hz.
+                                            The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)40000)    
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */     
+
+
+/**
+ * @brief STM32F30x Standard Peripherals Library version number V1.0.0
+   */
+#define __STM32F30X_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
+#define __STM32F30X_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32F30X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F30X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F30X_STDPERIPH_VERSION       ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F30X_STDPERIPH_VERSION_RC))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+ */
+#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1         /*!< STM32F30X provide an MPU */
+#define __NVIC_PRIO_BITS          4         /*!< STM32F30X uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             1         /*!< STM32F30X provide an FPU */
+
+
+/**
+ * @brief STM32F30X Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts                                   */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the  lines 17, 19 & 20           */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_TS_IRQn               = 8,      /*!< EXTI Line2 Interrupt and Touch Sense Interrupt                    */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 & ADC2 Interrupts                                            */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts                    */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts                    */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                                   */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                                  */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt                  */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  USBWakeUp_IRQn              = 42,     /*!< USB Wakeup Interrupt                                              */    
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  ADC4_IRQn                   = 61,     /*!< ADC4  global Interrupt                                            */
+  COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 global Interrupt                           */
+  COMP4_5_6_IRQn              = 65,     /*!< COMP5, COMP6 and COMP4 global Interrupt                           */
+  COMP7_IRQn                  = 66,     /*!< COMP7 global Interrupt                                            */
+  USB_HP_IRQn                 = 74,     /*!< USB High Priority global Interrupt remap                          */
+  USB_LP_IRQn                 = 75,     /*!< USB Low Priority global Interrupt  remap                          */
+  USBWakeUp_RMP_IRQn          = 76,     /*!< USB Wakeup Interrupt remap                                        */
+  FPU_IRQn                    = 81      /*!< Floating point Interrupt                                          */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"            /* Cortex-M4 processor and core peripherals */
+/* CHIBIOS FIX */
+/*#include "system_stm32f30x.h"*/    /* STM32F30x System Header */
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                 Address offset: 0x00 */
+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                     Address offset: 0x04 */      
+  __IO uint32_t CR;               /*!< ADC control register,                              Address offset: 0x08 */
+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                        Address offset: 0x0C */
+  uint32_t      RESERVED0;        /*!< Reserved, 0x010                                                         */
+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                        Address offset: 0x14 */
+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                        Address offset: 0x18 */
+  uint32_t      RESERVED1;        /*!< Reserved, 0x01C                                                         */
+  __IO uint32_t TR1;              /*!< ADC watchdog threshold register 1,                 Address offset: 0x20 */
+  __IO uint32_t TR2;              /*!< ADC watchdog threshold register 2,                 Address offset: 0x24 */
+  __IO uint32_t TR3;              /*!< ADC watchdog threshold register 3,                 Address offset: 0x28 */
+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                         */
+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                   Address offset: 0x30 */
+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                   Address offset: 0x34 */
+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                   Address offset: 0x38 */
+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                   Address offset: 0x3C */
+  __IO uint32_t DR;               /*!< ADC regular data register,                         Address offset: 0x40 */
+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                         */
+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                         */
+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                    Address offset: 0x4C */
+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                 */
+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                             Address offset: 0x60 */
+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                             Address offset: 0x64 */
+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                             Address offset: 0x68 */
+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                             Address offset: 0x6C */
+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                 */
+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                      Address offset: 0x80 */
+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                      Address offset: 0x84 */
+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                      Address offset: 0x88 */
+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                      Address offset: 0x8C */
+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                 */  
+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,     Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,     Address offset: 0xA4 */
+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                         */
+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                         */  
+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,         Address offset: 0xB0 */
+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                          Address offset: 0xB4 */
+  
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;            /*!< ADC Common status register,                  Address offset: ADC1/3 base address + 0x300 */
+  uint32_t      RESERVED;       /*!< Reserved, ADC1/3 base address + 0x304                                                    */
+  __IO uint32_t CCR;            /*!< ADC common control register,                 Address offset: ADC1/3 base address + 0x308 */
+  __IO uint32_t CDR;            /*!< ADC common regular data register for dual
+                                     AND triple modes,                            Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+  
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+  
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+
+/** 
+  * @brief Analog Comparators 
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;    /*!< DMA interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t IFCR;   /*!< DMA interrupt clear flag register,  Address offset: 0x04 */
+} DMA_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;        /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
+  __IO uint32_t EMR;        /*!< EXTI Event mask register,                    Address offset: 0x04 */
+  __IO uint32_t RTSR;       /*!< EXTI Rising trigger selection register,      Address offset: 0x08 */
+  __IO uint32_t FTSR;       /*!< EXTI Falling trigger selection register,     Address offset: 0x0C */
+  __IO uint32_t SWIER;      /*!< EXTI Software interrupt event register,      Address offset: 0x10 */
+  __IO uint32_t PR;         /*!< EXTI Pending register,                       Address offset: 0x14 */
+  uint32_t      RESERVED1;  /*!< Reserved, 0x18                                                    */
+  uint32_t      RESERVED2;  /*!< Reserved, 0x1C                                                    */
+  __IO uint32_t IMR2;       /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
+  __IO uint32_t EMR2;       /*!< EXTI Event mask register,                    Address offset: 0x24 */
+  __IO uint32_t RTSR2;      /*!< EXTI Rising trigger selection register,      Address offset: 0x28 */
+  __IO uint32_t FTSR2;      /*!< EXTI Falling trigger selection register,     Address offset: 0x2C */
+  __IO uint32_t SWIER2;     /*!< EXTI Software interrupt event register,      Address offset: 0x30 */
+  __IO uint32_t PR2;        /*!< EXTI Pending register,                       Address offset: 0x34 */
+}EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;          /*!< FLASH access control register,              Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!< FLASH key register,                         Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!< FLASH option key register,                  Address offset: 0x08 */
+  __IO uint32_t SR;           /*!< FLASH status register,                      Address offset: 0x0C */
+  __IO uint32_t CR;           /*!< FLASH control register,                     Address offset: 0x10 */
+  __IO uint32_t AR;           /*!< FLASH address register,                     Address offset: 0x14 */
+  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                   */
+  __IO uint32_t OBR;          /*!< FLASH Option byte register,                 Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!< FLASH Write register,                       Address offset: 0x20 */
+  
+} FLASH_TypeDef;
+
+/** 
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
+  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
+  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
+  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
+  __IO uint16_t WRP2;         /*!<FLASH option byte write protection 2,          Address offset: 0x10 */
+  __IO uint16_t WRP3;         /*!<FLASH option byte write protection 3,          Address offset: 0x12 */
+} OB_TypeDef;
+
+/** 
+  * @brief General Purpose I/O
+  */
+/* CHIBIOS FIX */
+#if 0
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
+}GPIO_TypeDef;
+#endif
+
+/** 
+  * @brief Operational Amplifier (OPAMP)
+  */
+  
+typedef struct
+{
+  __IO uint32_t CSR;        /*!< OPAMP control and status register,            Address offset: 0x00 */
+} OPAMP_TypeDef;
+
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t CFGR1;      /*!< SYSCFG configuration register 1,                   Address offset: 0x00 */
+  __IO uint32_t RCR;        /*!< SYSCFG CCM SRAM protection register,               Address offset: 0x04 */
+  __IO uint32_t EXTICR[4];  /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;     /*!< SYSCFG configuration register 2,                    Address offset: 0x18 */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  
+}I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */ 
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */ 
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+  
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  uint32_t RESERVED0;       /*!< Reserved, 0x18                                                                 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                   Address offset: 0x8C */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+  
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
+  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
+ __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
+  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
+  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,      Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register 4,      Address offset: 0x5C */
+} TIM_TypeDef;
+
+
+/** 
+  * @brief Touch Sensing Controller (TSC)
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+  
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
+  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef; 
+
+/** 
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+#define AHB3PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x00003400)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x00004000)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000)
+#define COMP_BASE             (APB2PERIPH_BASE + 0x0000001C)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0000001C)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x00000020)
+#define COMP3_BASE            (APB2PERIPH_BASE + 0x00000024)
+#define COMP4_BASE            (APB2PERIPH_BASE + 0x00000028)
+#define COMP5_BASE            (APB2PERIPH_BASE + 0x0000002C)
+#define COMP6_BASE            (APB2PERIPH_BASE + 0x00000030)
+#define COMP7_BASE            (APB2PERIPH_BASE + 0x00000034)
+#define OPAMP_BASE            (APB2PERIPH_BASE + 0x00000038)
+#define OPAMP1_BASE           (APB2PERIPH_BASE + 0x00000038)
+#define OPAMP2_BASE           (APB2PERIPH_BASE + 0x0000003C)
+#define OPAMP3_BASE           (APB2PERIPH_BASE + 0x00000040)
+#define OPAMP4_BASE           (APB2PERIPH_BASE + 0x00000044)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x00003400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x00004000)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x00004400)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x00004800)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (AHB1PERIPH_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (AHB1PERIPH_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (AHB1PERIPH_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (AHB1PERIPH_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (AHB1PERIPH_BASE + 0x00000058)
+#define DMA1_Channel6_BASE    (AHB1PERIPH_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE    (AHB1PERIPH_BASE + 0x00000080)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x00000400)
+#define DMA2_Channel1_BASE    (AHB1PERIPH_BASE + 0x00000408)
+#define DMA2_Channel2_BASE    (AHB1PERIPH_BASE + 0x0000041C)
+#define DMA2_Channel3_BASE    (AHB1PERIPH_BASE + 0x00000430)
+#define DMA2_Channel4_BASE    (AHB1PERIPH_BASE + 0x00000444)
+#define DMA2_Channel5_BASE    (AHB1PERIPH_BASE + 0x00000458)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)     /*!< Flash Option Bytes base address */
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x00004000)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400)
+
+/*!< AHB3 peripherals */
+#define ADC1_BASE             (AHB3PERIPH_BASE + 0x0000)
+#define ADC2_BASE             (AHB3PERIPH_BASE + 0x0100)
+#define ADC1_2_BASE           (AHB3PERIPH_BASE + 0x0300)
+#define ADC3_BASE             (AHB3PERIPH_BASE + 0x0400)
+#define ADC4_BASE             (AHB3PERIPH_BASE + 0x0500)
+#define ADC3_4_BASE           (AHB3PERIPH_BASE + 0x0700)
+
+#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP3               ((COMP_TypeDef *) COMP3_BASE)
+#define COMP4               ((COMP_TypeDef *) COMP4_BASE)
+#define COMP5               ((COMP_TypeDef *) COMP5_BASE)
+#define COMP6               ((COMP_TypeDef *) COMP6_BASE)
+#define COMP7               ((COMP_TypeDef *) COMP7_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP3              ((OPAMP_TypeDef *) OPAMP3_BASE)
+#define OPAMP4              ((OPAMP_TypeDef *) OPAMP4_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC4                ((ADC_TypeDef *) ADC4_BASE)
+#define ADC1_2              ((ADC_Common_TypeDef *) ADC1_2_BASE)
+#define ADC3_4              ((ADC_Common_TypeDef *) ADC3_4_BASE)
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter SAR (ADC)               */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_ISR register  ********************/
+/* CHIBIOS FIX */
+//#define ADC_ISR_ADRD         ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag  */
+#define ADC_ISR_ADRDY         ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag  */
+#define ADC_ISR_EOSMP         ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC           ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS           ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR           ((uint32_t)0x00000010) /*!< ADC overrun flag */
+#define ADC_ISR_JEOC          ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS          ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1          ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2          ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3          ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF         ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
+
+/********************  Bit definition for ADC_IER register  ********************/
+#define ADC_IER_RDY           ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMP         ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOC           ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOS           ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVR           ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOC          ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOS          ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1          ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2          ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3          ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVF         ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN          ((uint32_t)0x00000001) /*!< ADC Enable control */
+#define ADC_CR_ADDIS         ((uint32_t)0x00000002) /*!< ADC Disable command */
+#define ADC_CR_ADSTART       ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART      ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP         ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP        ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
+#define ADC_CR_ADVREGEN      ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
+#define ADC_CR_ADVREGEN_0    ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
+#define ADC_CR_ADVREGEN_1    ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
+#define ADC_CR_ADCALDIF      ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL         ((uint32_t)0x80000000) /*!< ADC Calibration */
+
+/********************  Bit definition for ADC_CFGR register  ********************/
+#define ADC_CFGR_DMAEN     ((uint32_t)0x00000001) /*!< ADC DMA Enable */
+#define ADC_CFGR_DMACFG    ((uint32_t)0x00000002) /*!< ADC DMA configuration */
+
+#define ADC_CFGR_RES       ((uint32_t)0x00000018) /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0     ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
+#define ADC_CFGR_RES_1     ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
+
+#define ADC_CFGR_ALIGN     ((uint32_t)0x00000020) /*!< ADC Data Alignement */
+
+#define ADC_CFGR_EXTSEL   ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
+#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
+#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
+#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
+
+#define ADC_CFGR_EXTEN     ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0   ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
+#define ADC_CFGR_EXTEN_1   ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
+
+#define ADC_CFGR_OVRMOD    ((uint32_t)0x00001000) /*!< ADC overrun mode */
+#define ADC_CFGR_CONT      ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY   ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
+#define ADC_CFGR_AUTOFF    ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
+#define ADC_CFGR_DISCEN    ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM   ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
+#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
+#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
+
+#define ADC_CFGR_JDISCEN   ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
+#define ADC_CFGR_JQM       ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL   ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN    ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN   ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO     ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH    ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0  ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
+#define ADC_CFGR_AWD1CH_1  ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1  */
+#define ADC_CFGR_AWD1CH_2  ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2  */
+#define ADC_CFGR_AWD1CH_3  ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3  */
+#define ADC_CFGR_AWD1CH_4  ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4  */
+
+/********************  Bit definition for ADC_SMPR1 register  ********************/
+#define ADC_SMPR1_SMP0     ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection  */
+#define ADC_SMPR1_SMP0_0   ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
+#define ADC_SMPR1_SMP0_1   ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
+#define ADC_SMPR1_SMP0_2   ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
+
+#define ADC_SMPR1_SMP1     ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection  */
+#define ADC_SMPR1_SMP1_0   ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
+#define ADC_SMPR1_SMP1_1   ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
+#define ADC_SMPR1_SMP1_2   ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
+
+#define ADC_SMPR1_SMP2     ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection  */
+#define ADC_SMPR1_SMP2_0   ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
+#define ADC_SMPR1_SMP2_1   ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
+#define ADC_SMPR1_SMP2_2   ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
+
+#define ADC_SMPR1_SMP3     ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection  */
+#define ADC_SMPR1_SMP3_0   ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
+#define ADC_SMPR1_SMP3_1   ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
+#define ADC_SMPR1_SMP3_2   ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
+
+#define ADC_SMPR1_SMP4     ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection  */
+#define ADC_SMPR1_SMP4_0   ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
+#define ADC_SMPR1_SMP4_1   ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
+#define ADC_SMPR1_SMP4_2   ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
+
+#define ADC_SMPR1_SMP5     ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection  */
+#define ADC_SMPR1_SMP5_0   ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
+#define ADC_SMPR1_SMP5_1   ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
+#define ADC_SMPR1_SMP5_2   ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
+
+#define ADC_SMPR1_SMP6     ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection  */
+#define ADC_SMPR1_SMP6_0   ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
+#define ADC_SMPR1_SMP6_1   ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
+#define ADC_SMPR1_SMP6_2   ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
+
+#define ADC_SMPR1_SMP7     ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection  */
+#define ADC_SMPR1_SMP7_0   ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
+#define ADC_SMPR1_SMP7_1   ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
+#define ADC_SMPR1_SMP7_2   ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
+
+#define ADC_SMPR1_SMP8     ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection  */
+#define ADC_SMPR1_SMP8_0   ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
+#define ADC_SMPR1_SMP8_1   ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
+#define ADC_SMPR1_SMP8_2   ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
+
+#define ADC_SMPR1_SMP9     ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection  */
+#define ADC_SMPR1_SMP9_0   ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
+#define ADC_SMPR1_SMP9_1   ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
+#define ADC_SMPR1_SMP9_2   ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
+
+/********************  Bit definition for ADC_SMPR2 register  ********************/
+#define ADC_SMPR2_SMP10     ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection  */
+#define ADC_SMPR2_SMP10_0   ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
+#define ADC_SMPR2_SMP10_1   ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
+#define ADC_SMPR2_SMP10_2   ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
+
+#define ADC_SMPR2_SMP11     ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection  */
+#define ADC_SMPR2_SMP11_0   ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
+#define ADC_SMPR2_SMP11_1   ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
+#define ADC_SMPR2_SMP11_2   ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
+
+#define ADC_SMPR2_SMP12     ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection  */
+#define ADC_SMPR2_SMP12_0   ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
+#define ADC_SMPR2_SMP12_1   ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
+#define ADC_SMPR2_SMP12_2   ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
+
+#define ADC_SMPR2_SMP13     ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection  */
+#define ADC_SMPR2_SMP13_0   ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
+#define ADC_SMPR2_SMP13_1   ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
+#define ADC_SMPR2_SMP13_2   ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
+
+#define ADC_SMPR2_SMP14     ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection  */
+#define ADC_SMPR2_SMP14_0   ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
+#define ADC_SMPR2_SMP14_1   ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
+#define ADC_SMPR2_SMP14_2   ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
+
+#define ADC_SMPR2_SMP15     ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection  */
+#define ADC_SMPR2_SMP15_0   ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
+#define ADC_SMPR2_SMP15_1   ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
+#define ADC_SMPR2_SMP15_2   ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
+
+#define ADC_SMPR2_SMP16     ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection  */
+#define ADC_SMPR2_SMP16_0   ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
+#define ADC_SMPR2_SMP16_1   ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
+#define ADC_SMPR2_SMP16_2   ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
+
+#define ADC_SMPR2_SMP17     ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection  */
+#define ADC_SMPR2_SMP17_0   ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
+#define ADC_SMPR2_SMP17_1   ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
+#define ADC_SMPR2_SMP17_2   ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
+
+#define ADC_SMPR2_SMP18     ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection  */
+#define ADC_SMPR2_SMP18_0   ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
+#define ADC_SMPR2_SMP18_1   ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
+#define ADC_SMPR2_SMP18_2   ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
+
+/********************  Bit definition for ADC_TR1 register  ********************/
+#define ADC_TR1_LT1         ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
+#define ADC_TR1_LT1_0       ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
+#define ADC_TR1_LT1_1       ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
+#define ADC_TR1_LT1_2       ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
+#define ADC_TR1_LT1_3       ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
+#define ADC_TR1_LT1_4       ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
+#define ADC_TR1_LT1_5       ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
+#define ADC_TR1_LT1_6       ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
+#define ADC_TR1_LT1_7       ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
+#define ADC_TR1_LT1_8       ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
+#define ADC_TR1_LT1_9       ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
+#define ADC_TR1_LT1_10      ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
+#define ADC_TR1_LT1_11      ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
+
+#define ADC_TR1_HT1         ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
+#define ADC_TR1_HT1_0       ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
+#define ADC_TR1_HT1_1       ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
+#define ADC_TR1_HT1_2       ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
+#define ADC_TR1_HT1_3       ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
+#define ADC_TR1_HT1_4       ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
+#define ADC_TR1_HT1_5       ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
+#define ADC_TR1_HT1_6       ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
+#define ADC_TR1_HT1_7       ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
+#define ADC_TR1_HT1_8       ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
+#define ADC_TR1_HT1_9       ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
+#define ADC_TR1_HT1_10      ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
+#define ADC_TR1_HT1_11      ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
+
+/********************  Bit definition for ADC_TR2 register  ********************/
+#define ADC_TR2_LT2         ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
+#define ADC_TR2_LT2_0       ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
+#define ADC_TR2_LT2_1       ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
+#define ADC_TR2_LT2_2       ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
+#define ADC_TR2_LT2_3       ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
+#define ADC_TR2_LT2_4       ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
+#define ADC_TR2_LT2_5       ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
+#define ADC_TR2_LT2_6       ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
+#define ADC_TR2_LT2_7       ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
+
+#define ADC_TR2_HT2         ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
+#define ADC_TR2_HT2_0       ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
+#define ADC_TR2_HT2_1       ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
+#define ADC_TR2_HT2_2       ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
+#define ADC_TR2_HT2_3       ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
+#define ADC_TR2_HT2_4       ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
+#define ADC_TR2_HT2_5       ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
+#define ADC_TR2_HT2_6       ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
+#define ADC_TR2_HT2_7       ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
+
+/********************  Bit definition for ADC_TR3 register  ********************/
+#define ADC_TR3_LT3         ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
+#define ADC_TR3_LT3_0       ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
+#define ADC_TR3_LT3_1       ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
+#define ADC_TR3_LT3_2       ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
+#define ADC_TR3_LT3_3       ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
+#define ADC_TR3_LT3_4       ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
+#define ADC_TR3_LT3_5       ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
+#define ADC_TR3_LT3_6       ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
+#define ADC_TR3_LT3_7       ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
+
+#define ADC_TR3_HT3         ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
+#define ADC_TR3_HT3_0       ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
+#define ADC_TR3_HT3_1       ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
+#define ADC_TR3_HT3_2       ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
+#define ADC_TR3_HT3_3       ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
+#define ADC_TR3_HT3_4       ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
+#define ADC_TR3_HT3_5       ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
+#define ADC_TR3_HT3_6       ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
+#define ADC_TR3_HT3_7       ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
+
+/********************  Bit definition for ADC_SQR1 register  ********************/
+#define ADC_SQR1_L          ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0        ((uint32_t)0x00000001) /*!< ADC L bit 0 */
+#define ADC_SQR1_L_1        ((uint32_t)0x00000002) /*!< ADC L bit 1 */
+#define ADC_SQR1_L_2        ((uint32_t)0x00000004) /*!< ADC L bit 2 */
+#define ADC_SQR1_L_3        ((uint32_t)0x00000008) /*!< ADC L bit 3 */
+
+#define ADC_SQR1_SQ1        ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0      ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
+#define ADC_SQR1_SQ1_1      ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
+#define ADC_SQR1_SQ1_2      ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
+#define ADC_SQR1_SQ1_3      ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
+#define ADC_SQR1_SQ1_4      ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
+
+#define ADC_SQR1_SQ2        ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0      ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
+#define ADC_SQR1_SQ2_1      ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
+#define ADC_SQR1_SQ2_2      ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
+#define ADC_SQR1_SQ2_3      ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
+#define ADC_SQR1_SQ2_4      ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
+
+#define ADC_SQR1_SQ3        ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0      ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
+#define ADC_SQR1_SQ3_1      ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
+#define ADC_SQR1_SQ3_2      ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
+#define ADC_SQR1_SQ3_3      ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
+#define ADC_SQR1_SQ3_4      ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
+
+#define ADC_SQR1_SQ4        ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0      ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
+#define ADC_SQR1_SQ4_1      ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
+#define ADC_SQR1_SQ4_2      ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
+#define ADC_SQR1_SQ4_3      ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
+#define ADC_SQR1_SQ4_4      ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
+
+/********************  Bit definition for ADC_SQR2 register  ********************/
+#define ADC_SQR2_SQ5        ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0      ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
+#define ADC_SQR2_SQ5_1      ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
+#define ADC_SQR2_SQ5_2      ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
+#define ADC_SQR2_SQ5_3      ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
+#define ADC_SQR2_SQ5_4      ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
+
+#define ADC_SQR2_SQ6        ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0      ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
+#define ADC_SQR2_SQ6_1      ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
+#define ADC_SQR2_SQ6_2      ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
+#define ADC_SQR2_SQ6_3      ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
+#define ADC_SQR2_SQ6_4      ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
+
+#define ADC_SQR2_SQ7        ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0      ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
+#define ADC_SQR2_SQ7_1      ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
+#define ADC_SQR2_SQ7_2      ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
+#define ADC_SQR2_SQ7_3      ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
+#define ADC_SQR2_SQ7_4      ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
+
+#define ADC_SQR2_SQ8        ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0      ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
+#define ADC_SQR2_SQ8_1      ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
+#define ADC_SQR2_SQ8_2      ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
+#define ADC_SQR2_SQ8_3      ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
+#define ADC_SQR2_SQ8_4      ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
+
+#define ADC_SQR2_SQ9        ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0      ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
+#define ADC_SQR2_SQ9_1      ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
+#define ADC_SQR2_SQ9_2      ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
+#define ADC_SQR2_SQ9_3      ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
+#define ADC_SQR2_SQ9_4      ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
+
+/********************  Bit definition for ADC_SQR3 register  ********************/
+#define ADC_SQR3_SQ10       ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0     ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
+#define ADC_SQR3_SQ10_1     ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
+#define ADC_SQR3_SQ10_2     ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
+#define ADC_SQR3_SQ10_3     ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
+#define ADC_SQR3_SQ10_4     ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
+
+#define ADC_SQR3_SQ11       ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0     ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
+#define ADC_SQR3_SQ11_1     ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
+#define ADC_SQR3_SQ11_2     ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
+#define ADC_SQR3_SQ11_3     ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
+#define ADC_SQR3_SQ11_4     ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
+
+#define ADC_SQR3_SQ12       ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0     ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
+#define ADC_SQR3_SQ12_1     ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
+#define ADC_SQR3_SQ12_2     ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
+#define ADC_SQR3_SQ12_3     ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
+#define ADC_SQR3_SQ12_4     ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
+
+#define ADC_SQR3_SQ13       ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0     ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
+#define ADC_SQR3_SQ13_1     ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
+#define ADC_SQR3_SQ13_2     ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
+#define ADC_SQR3_SQ13_3     ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
+#define ADC_SQR3_SQ13_4     ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
+
+#define ADC_SQR3_SQ14       ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0     ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
+#define ADC_SQR3_SQ14_1     ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
+#define ADC_SQR3_SQ14_2     ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
+#define ADC_SQR3_SQ14_3     ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
+#define ADC_SQR3_SQ14_4     ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
+
+/********************  Bit definition for ADC_SQR4 register  ********************/
+#define ADC_SQR3_SQ15       ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR3_SQ15_0     ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
+#define ADC_SQR3_SQ15_1     ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
+#define ADC_SQR3_SQ15_2     ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
+#define ADC_SQR3_SQ15_3     ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
+#define ADC_SQR3_SQ15_4     ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
+
+#define ADC_SQR3_SQ16       ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR3_SQ16_0     ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
+#define ADC_SQR3_SQ16_1     ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
+#define ADC_SQR3_SQ16_2     ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
+#define ADC_SQR3_SQ16_3     ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
+#define ADC_SQR3_SQ16_4     ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA        ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
+#define ADC_DR_RDATA_0      ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
+#define ADC_DR_RDATA_1      ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
+#define ADC_DR_RDATA_2      ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
+#define ADC_DR_RDATA_3      ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
+#define ADC_DR_RDATA_4      ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
+#define ADC_DR_RDATA_5      ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
+#define ADC_DR_RDATA_6      ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
+#define ADC_DR_RDATA_7      ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
+#define ADC_DR_RDATA_8      ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
+#define ADC_DR_RDATA_9      ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
+#define ADC_DR_RDATA_10     ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
+#define ADC_DR_RDATA_11     ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
+#define ADC_DR_RDATA_12     ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
+#define ADC_DR_RDATA_13     ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
+#define ADC_DR_RDATA_14     ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
+#define ADC_DR_RDATA_15     ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
+
+/********************  Bit definition for ADC_JSQR register  ********************/
+#define ADC_JSQR_JL         ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0       ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
+#define ADC_JSQR_JL_1       ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
+
+#define ADC_JSQR_JEXTSEL    ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0  ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
+#define ADC_JSQR_JEXTSEL_1  ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
+#define ADC_JSQR_JEXTSEL_2  ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
+#define ADC_JSQR_JEXTSEL_3  ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
+
+#define ADC_JSQR_JEXTEN     ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0   ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
+#define ADC_JSQR_JEXTEN_1   ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
+
+#define ADC_JSQR_JSQ1       ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0     ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
+#define ADC_JSQR_JSQ1_1     ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
+#define ADC_JSQR_JSQ1_2     ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
+#define ADC_JSQR_JSQ1_3     ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
+#define ADC_JSQR_JSQ1_4     ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
+
+#define ADC_JSQR_JSQ2       ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0     ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
+#define ADC_JSQR_JSQ2_1     ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
+#define ADC_JSQR_JSQ2_2     ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
+#define ADC_JSQR_JSQ2_3     ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
+#define ADC_JSQR_JSQ2_4     ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
+
+#define ADC_JSQR_JSQ3       ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0     ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
+#define ADC_JSQR_JSQ3_1     ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
+#define ADC_JSQR_JSQ3_2     ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
+#define ADC_JSQR_JSQ3_3     ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
+#define ADC_JSQR_JSQ3_4     ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
+
+#define ADC_JSQR_JSQ4       ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0     ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
+#define ADC_JSQR_JSQ4_1     ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
+#define ADC_JSQR_JSQ4_2     ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
+#define ADC_JSQR_JSQ4_3     ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
+#define ADC_JSQR_JSQ4_4     ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
+
+/********************  Bit definition for ADC_OFR1 register  ********************/
+#define ADC_OFR1_OFFSET1    ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0  ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
+#define ADC_OFR1_OFFSET1_1  ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
+#define ADC_OFR1_OFFSET1_2  ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
+#define ADC_OFR1_OFFSET1_3  ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
+#define ADC_OFR1_OFFSET1_4  ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
+#define ADC_OFR1_OFFSET1_5  ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
+#define ADC_OFR1_OFFSET1_6  ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
+#define ADC_OFR1_OFFSET1_7  ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
+#define ADC_OFR1_OFFSET1_8  ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
+#define ADC_OFR1_OFFSET1_9  ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
+#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
+#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
+
+#define ADC_OFR1_OFFSET1_CH     ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0  ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
+#define ADC_OFR1_OFFSET1_CH_1  ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
+#define ADC_OFR1_OFFSET1_CH_2  ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
+#define ADC_OFR1_OFFSET1_CH_3  ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
+#define ADC_OFR1_OFFSET1_CH_4  ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
+
+#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ********************/
+#define ADC_OFR2_OFFSET2    ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0  ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
+#define ADC_OFR2_OFFSET2_1  ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
+#define ADC_OFR2_OFFSET2_2  ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
+#define ADC_OFR2_OFFSET2_3  ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
+#define ADC_OFR2_OFFSET2_4  ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
+#define ADC_OFR2_OFFSET2_5  ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
+#define ADC_OFR2_OFFSET2_6  ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
+#define ADC_OFR2_OFFSET2_7  ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
+#define ADC_OFR2_OFFSET2_8  ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
+#define ADC_OFR2_OFFSET2_9  ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
+#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
+#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
+
+#define ADC_OFR2_OFFSET2_CH     ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0  ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
+#define ADC_OFR2_OFFSET2_CH_1  ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
+#define ADC_OFR2_OFFSET2_CH_2  ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
+#define ADC_OFR2_OFFSET2_CH_3  ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
+#define ADC_OFR2_OFFSET2_CH_4  ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
+
+#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ********************/
+#define ADC_OFR3_OFFSET3    ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0  ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
+#define ADC_OFR3_OFFSET3_1  ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
+#define ADC_OFR3_OFFSET3_2  ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
+#define ADC_OFR3_OFFSET3_3  ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
+#define ADC_OFR3_OFFSET3_4  ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
+#define ADC_OFR3_OFFSET3_5  ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
+#define ADC_OFR3_OFFSET3_6  ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
+#define ADC_OFR3_OFFSET3_7  ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
+#define ADC_OFR3_OFFSET3_8  ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
+#define ADC_OFR3_OFFSET3_9  ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
+#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
+#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
+
+#define ADC_OFR3_OFFSET3_CH     ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0  ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
+#define ADC_OFR3_OFFSET3_CH_1  ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
+#define ADC_OFR3_OFFSET3_CH_2  ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
+#define ADC_OFR3_OFFSET3_CH_3  ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
+#define ADC_OFR3_OFFSET3_CH_4  ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
+
+#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ********************/
+#define ADC_OFR4_OFFSET4    ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0  ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
+#define ADC_OFR4_OFFSET4_1  ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
+#define ADC_OFR4_OFFSET4_2  ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
+#define ADC_OFR4_OFFSET4_3  ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
+#define ADC_OFR4_OFFSET4_4  ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
+#define ADC_OFR4_OFFSET4_5  ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
+#define ADC_OFR4_OFFSET4_6  ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
+#define ADC_OFR4_OFFSET4_7  ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
+#define ADC_OFR4_OFFSET4_8  ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
+#define ADC_OFR4_OFFSET4_9  ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
+#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
+#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
+
+#define ADC_OFR4_OFFSET4_CH     ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0  ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
+#define ADC_OFR4_OFFSET4_CH_1  ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
+#define ADC_OFR4_OFFSET4_CH_2  ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
+#define ADC_OFR4_OFFSET4_CH_3  ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
+#define ADC_OFR4_OFFSET4_CH_4  ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
+
+#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ********************/
+#define ADC_JDR1_JDATA      ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0    ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR1_JDATA_1    ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR1_JDATA_2    ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR1_JDATA_3    ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR1_JDATA_4    ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR1_JDATA_5    ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR1_JDATA_6    ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR1_JDATA_7    ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR1_JDATA_8    ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR1_JDATA_9    ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR1_JDATA_10   ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR1_JDATA_11   ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR1_JDATA_12   ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR1_JDATA_13   ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR1_JDATA_14   ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR1_JDATA_15   ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA      ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0    ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR2_JDATA_1    ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR2_JDATA_2    ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR2_JDATA_3    ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR2_JDATA_4    ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR2_JDATA_5    ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR2_JDATA_6    ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR2_JDATA_7    ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR2_JDATA_8    ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR2_JDATA_9    ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR2_JDATA_10   ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR2_JDATA_11   ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR2_JDATA_12   ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR2_JDATA_13   ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR2_JDATA_14   ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR2_JDATA_15   ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA      ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0    ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR3_JDATA_1    ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR3_JDATA_2    ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR3_JDATA_3    ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR3_JDATA_4    ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR3_JDATA_5    ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR3_JDATA_6    ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR3_JDATA_7    ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR3_JDATA_8    ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR3_JDATA_9    ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR3_JDATA_10   ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR3_JDATA_11   ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR3_JDATA_12   ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR3_JDATA_13   ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR3_JDATA_14   ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR3_JDATA_15   ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA      ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0    ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR4_JDATA_1    ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR4_JDATA_2    ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR4_JDATA_3    ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR4_JDATA_4    ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR4_JDATA_5    ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR4_JDATA_6    ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR4_JDATA_7    ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR4_JDATA_8    ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR4_JDATA_9    ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR4_JDATA_10   ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR4_JDATA_11   ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR4_JDATA_12   ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR4_JDATA_13   ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR4_JDATA_14   ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR4_JDATA_15   ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/********************  Bit definition for ADC_AWD2CR register  ********************/
+#define ADC_AWD2CR_AWD2CH    ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0  ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
+#define ADC_AWD2CR_AWD2CH_1  ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
+#define ADC_AWD2CR_AWD2CH_2  ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
+#define ADC_AWD2CR_AWD2CH_3  ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
+#define ADC_AWD2CR_AWD2CH_4  ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
+#define ADC_AWD2CR_AWD2CH_5  ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
+#define ADC_AWD2CR_AWD2CH_6  ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
+#define ADC_AWD2CR_AWD2CH_7  ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
+#define ADC_AWD2CR_AWD2CH_8  ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
+#define ADC_AWD2CR_AWD2CH_9  ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
+#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
+#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
+#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
+#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
+#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
+#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
+#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
+#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
+
+/********************  Bit definition for ADC_AWD3CR register  ********************/
+#define ADC_AWD3CR_AWD3CH    ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0  ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
+#define ADC_AWD3CR_AWD3CH_1  ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
+#define ADC_AWD3CR_AWD3CH_2  ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
+#define ADC_AWD3CR_AWD3CH_3  ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
+#define ADC_AWD3CR_AWD3CH_4  ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
+#define ADC_AWD3CR_AWD3CH_5  ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
+#define ADC_AWD3CR_AWD3CH_6  ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
+#define ADC_AWD3CR_AWD3CH_7  ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
+#define ADC_AWD3CR_AWD3CH_8  ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
+#define ADC_AWD3CR_AWD3CH_9  ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
+#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
+#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
+#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
+#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
+#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
+#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
+#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
+#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
+
+/********************  Bit definition for ADC_DIFSEL register  ********************/
+#define ADC_DIFSEL_DIFSEL    ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0  ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
+#define ADC_DIFSEL_DIFSEL_1  ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
+#define ADC_DIFSEL_DIFSEL_2  ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
+#define ADC_DIFSEL_DIFSEL_3  ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
+#define ADC_DIFSEL_DIFSEL_4  ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
+#define ADC_DIFSEL_DIFSEL_5  ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
+#define ADC_DIFSEL_DIFSEL_6  ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
+#define ADC_DIFSEL_DIFSEL_7  ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
+#define ADC_DIFSEL_DIFSEL_8  ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
+#define ADC_DIFSEL_DIFSEL_9  ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
+#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
+#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
+#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
+#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
+#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
+#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
+#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
+#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
+
+/********************  Bit definition for ADC_CALFACT register  ********************/
+#define ADC_CALFACT_CALFACT_S   ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
+#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
+#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
+#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
+#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
+#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
+#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
+#define ADC_CALFACT_CALFACT_D   ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
+#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
+#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
+#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
+#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
+#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
+#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC12_CSR register  ********************/
+#define ADC12_CSR_ADRDY_MST         ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_MST   ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC12_CSR_ADRDY_EOC_MST     ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC12_CSR_ADRDY_EOS_MST     ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC12_CSR_ADRDY_OVR_MST     ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC12_CSR_ADRDY_JEOC_MST    ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC12_CSR_ADRDY_JEOS_MST    ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC12_CSR_AWD1_MST          ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC12_CSR_AWD2_MST          ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC12_CSR_AWD3_MST          ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC12_CSR_JQOVF_MST         ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC12_CSR_ADRDY_SLV         ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_SLV   ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC12_CSR_ADRDY_EOC_SLV     ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_EOS_SLV     ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV     ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOC_SLV    ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOS_SLV    ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC12_CSR_AWD1_SLV          ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC12_CSR_AWD2_SLV          ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC12_CSR_AWD3_SLV          ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC12_CSR_JQOVF_SLV         ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/********************  Bit definition for ADC34_CSR register  ********************/
+#define ADC34_CSR_ADRDY_MST         ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_MST   ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC34_CSR_ADRDY_EOC_MST     ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC34_CSR_ADRDY_EOS_MST     ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC34_CSR_ADRDY_OVR_MST     ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC34_CSR_ADRDY_JEOC_MST    ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC34_CSR_ADRDY_JEOS_MST    ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC34_CSR_AWD1_MST          ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC34_CSR_AWD2_MST          ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC34_CSR_AWD3_MST          ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC34_CSR_JQOVF_MST         ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC34_CSR_ADRDY_SLV         ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_SLV   ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC34_CSR_ADRDY_EOC_SLV     ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_EOS_SLV     ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV     ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOC_SLV    ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOS_SLV    ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC34_CSR_AWD1_SLV          ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC34_CSR_AWD2_SLV          ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC34_CSR_AWD3_SLV          ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC34_CSR_JQOVF_SLV         ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/********************  Bit definition for ADC_CCR register  ********************/
+#define ADC12_CCR_MULTI             ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC12_CCR_MULTI_0           ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC12_CCR_MULTI_1           ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC12_CCR_MULTI_2           ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC12_CCR_MULTI_3           ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC12_CCR_MULTI_4           ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+#define ADC12_CCR_DELAY             ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC12_CCR_DELAY_0           ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC12_CCR_DELAY_1           ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC12_CCR_DELAY_2           ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC12_CCR_DELAY_3           ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+#define ADC12_CCR_DMACFG            ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC12_CCR_MDMA              ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC12_CCR_MDMA_0            ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC12_CCR_MDMA_1            ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+#define ADC12_CCR_CKMODE            ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC12_CCR_CKMODE_0          ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC12_CCR_CKMODE_1          ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+#define ADC12_CCR_VREFEN            ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC12_CCR_TSEN              ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC12_CCR_VBATEN            ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/********************  Bit definition for ADC_CCR register  ********************/
+#define ADC34_CCR_MULTI             ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC34_CCR_MULTI_0           ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC34_CCR_MULTI_1           ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC34_CCR_MULTI_2           ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC34_CCR_MULTI_3           ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC34_CCR_MULTI_4           ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+
+#define ADC34_CCR_DELAY             ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC34_CCR_DELAY_0           ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC34_CCR_DELAY_1           ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC34_CCR_DELAY_2           ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC34_CCR_DELAY_3           ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+
+#define ADC34_CCR_DMACFG            ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC34_CCR_MDMA              ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC34_CCR_MDMA_0            ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC34_CCR_MDMA_1            ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+
+#define ADC34_CCR_CKMODE            ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC34_CCR_CKMODE_0          ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC34_CCR_CKMODE_1          ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+
+#define ADC34_CCR_VREFEN            ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC34_CCR_TSEN              ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC34_CCR_VBATEN            ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/********************  Bit definition for ADC_CDR register  ********************/
+#define ADC12_CDR_RDATA_MST         ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_MST_0       ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC12_CDR_RDATA_MST_1       ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC12_CDR_RDATA_MST_2       ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC12_CDR_RDATA_MST_3       ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC12_CDR_RDATA_MST_4       ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC12_CDR_RDATA_MST_5       ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC12_CDR_RDATA_MST_6       ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC12_CDR_RDATA_MST_7       ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC12_CDR_RDATA_MST_8       ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC12_CDR_RDATA_MST_9       ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC12_CDR_RDATA_MST_10      ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC12_CDR_RDATA_MST_11      ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC12_CDR_RDATA_MST_12      ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC12_CDR_RDATA_MST_13      ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC12_CDR_RDATA_MST_14      ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC12_CDR_RDATA_MST_15      ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC12_CDR_RDATA_SLV         ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_SLV_0       ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC12_CDR_RDATA_SLV_1       ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC12_CDR_RDATA_SLV_2       ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC12_CDR_RDATA_SLV_3       ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC12_CDR_RDATA_SLV_4       ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC12_CDR_RDATA_SLV_5       ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC12_CDR_RDATA_SLV_6       ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC12_CDR_RDATA_SLV_7       ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC12_CDR_RDATA_SLV_8       ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC12_CDR_RDATA_SLV_9       ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC12_CDR_RDATA_SLV_10      ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC12_CDR_RDATA_SLV_11      ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC12_CDR_RDATA_SLV_12      ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC12_CDR_RDATA_SLV_13      ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC12_CDR_RDATA_SLV_14      ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC12_CDR_RDATA_SLV_15      ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/********************  Bit definition for ADC_CDR register  ********************/
+#define ADC34_CDR_RDATA_MST         ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_MST_0       ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC34_CDR_RDATA_MST_1       ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC34_CDR_RDATA_MST_2       ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC34_CDR_RDATA_MST_3       ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC34_CDR_RDATA_MST_4       ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC34_CDR_RDATA_MST_5       ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC34_CDR_RDATA_MST_6       ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC34_CDR_RDATA_MST_7       ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC34_CDR_RDATA_MST_8       ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC34_CDR_RDATA_MST_9       ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC34_CDR_RDATA_MST_10      ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC34_CDR_RDATA_MST_11      ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC34_CDR_RDATA_MST_12      ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC34_CDR_RDATA_MST_13      ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC34_CDR_RDATA_MST_14      ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC34_CDR_RDATA_MST_15      ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC34_CDR_RDATA_SLV         ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_SLV_0       ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC34_CDR_RDATA_SLV_1       ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC34_CDR_RDATA_SLV_2       ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC34_CDR_RDATA_SLV_3       ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC34_CDR_RDATA_SLV_4       ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC34_CDR_RDATA_SLV_5       ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC34_CDR_RDATA_SLV_6       ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC34_CDR_RDATA_SLV_7       ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC34_CDR_RDATA_SLV_8       ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC34_CDR_RDATA_SLV_9       ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC34_CDR_RDATA_SLV_10      ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC34_CDR_RDATA_SLV_11      ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC34_CDR_RDATA_SLV_12      ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC34_CDR_RDATA_SLV_13      ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC34_CDR_RDATA_SLV_14      ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC34_CDR_RDATA_SLV_15      ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/**********************  Bit definition for COMP1_CSR register  ***************/
+#define COMP1_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP1_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
+#define COMP1_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP1_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP1_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP1_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP1_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP1_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP1_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP1_CSR_COMP1NONINSEL         ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */
+#define COMP1_CSR_COMP1OUTSEL           ((uint32_t)0x00003C00) /*!< COMP1 output select */
+#define COMP1_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
+#define COMP1_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
+#define COMP1_CSR_COMP1OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
+#define COMP1_CSR_COMP1POL              ((uint32_t)0x00008000) /*!< COMP1 output polarity */
+#define COMP1_CSR_COMP1HYST             ((uint32_t)0x00030000) /*!< COMP1 hysteresis */
+#define COMP1_CSR_COMP1HYST_0           ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */
+#define COMP1_CSR_COMP1HYST_1           ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */
+#define COMP1_CSR_COMP1BLANKING         ((uint32_t)0x000C0000) /*!< COMP1 blanking */
+#define COMP1_CSR_COMP1BLANKING_0       ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
+#define COMP1_CSR_COMP1BLANKING_1       ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
+#define COMP1_CSR_COMP1BLANKING_2       ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
+#define COMP1_CSR_COMP1OUT              ((uint32_t)0x40000000) /*!< COMP1 output level */
+#define COMP1_CSR_COMP1LOCK             ((uint32_t)0x80000000) /*!< COMP1 lock */
+
+/**********************  Bit definition for COMP2_CSR register  ***************/
+#define COMP2_CSR_COMP2EN               ((uint32_t)0x00000001) /*!< COMP2 enable */
+#define COMP2_CSR_COMP2MODE             ((uint32_t)0x0000000C) /*!< COMP2 power mode */
+#define COMP2_CSR_COMP2MODE_0           ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */
+#define COMP2_CSR_COMP2MODE_1           ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */
+#define COMP2_CSR_COMP2INSEL            ((uint32_t)0x00000070) /*!< COMP2 inverting input select */
+#define COMP2_CSR_COMP2INSEL_0          ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
+#define COMP2_CSR_COMP2INSEL_1          ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
+#define COMP2_CSR_COMP2INSEL_2          ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
+#define COMP2_CSR_COMP2NONINSEL         ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */
+#define COMP2_CSR_COMP2WNDWEN           ((uint32_t)0x00000200) /*!< COMP2 window mode enable */
+#define COMP2_CSR_COMP2OUTSEL           ((uint32_t)0x00003C00) /*!< COMP2 output select */
+#define COMP2_CSR_COMP2OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
+#define COMP2_CSR_COMP2OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
+#define COMP2_CSR_COMP2OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
+#define COMP2_CSR_COMP2OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
+#define COMP2_CSR_COMP2POL              ((uint32_t)0x00008000) /*!< COMP2 output polarity */
+#define COMP2_CSR_COMP2HYST             ((uint32_t)0x00030000) /*!< COMP2 hysteresis */
+#define COMP2_CSR_COMP2HYST_0           ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */
+#define COMP2_CSR_COMP2HYST_1           ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */
+#define COMP2_CSR_COMP2BLANKING         ((uint32_t)0x000C0000) /*!< COMP2 blanking */
+#define COMP2_CSR_COMP2BLANKING_0       ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
+#define COMP2_CSR_COMP2BLANKING_1       ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
+#define COMP2_CSR_COMP2BLANKING_2       ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
+#define COMP2_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP2_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/**********************  Bit definition for COMP3_CSR register  ***************/
+#define COMP3_CSR_COMP3EN               ((uint32_t)0x00000001) /*!< COMP3 enable */
+#define COMP3_CSR_COMP3MODE             ((uint32_t)0x0000000C) /*!< COMP3 power mode */
+#define COMP3_CSR_COMP3MODE_0           ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */
+#define COMP3_CSR_COMP3MODE_1           ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */
+#define COMP3_CSR_COMP3INSEL            ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
+#define COMP3_CSR_COMP3INSEL_0          ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
+#define COMP3_CSR_COMP3INSEL_1          ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
+#define COMP3_CSR_COMP3INSEL_2          ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
+#define COMP3_CSR_COMP3NONINSEL         ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */
+#define COMP3_CSR_COMP3OUTSEL           ((uint32_t)0x00003C00) /*!< COMP3 output select */
+#define COMP3_CSR_COMP3OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
+#define COMP3_CSR_COMP3OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
+#define COMP3_CSR_COMP3OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
+#define COMP3_CSR_COMP3OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
+#define COMP3_CSR_COMP3POL              ((uint32_t)0x00008000) /*!< COMP3 output polarity */
+#define COMP3_CSR_COMP3HYST             ((uint32_t)0x00030000) /*!< COMP3 hysteresis */
+#define COMP3_CSR_COMP3HYST_0           ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */
+#define COMP3_CSR_COMP3HYST_1           ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */
+#define COMP3_CSR_COMP3BLANKING         ((uint32_t)0x000C0000) /*!< COMP3 blanking */
+#define COMP3_CSR_COMP3BLANKING_0       ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
+#define COMP3_CSR_COMP3BLANKING_1       ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
+#define COMP3_CSR_COMP3BLANKING_2       ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
+#define COMP3_CSR_COMP3OUT              ((uint32_t)0x40000000) /*!< COMP3 output level */
+#define COMP3_CSR_COMP3LOCK             ((uint32_t)0x80000000) /*!< COMP3 lock */
+
+/**********************  Bit definition for COMP4_CSR register  ***************/
+#define COMP4_CSR_COMP4EN               ((uint32_t)0x00000001) /*!< COMP4 enable */
+#define COMP4_CSR_COMP4MODE             ((uint32_t)0x0000000C) /*!< COMP4 power mode */
+#define COMP4_CSR_COMP4MODE_0           ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */
+#define COMP4_CSR_COMP4MODE_1           ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */
+#define COMP4_CSR_COMP4INSEL            ((uint32_t)0x00000070) /*!< COMP4 inverting input select */
+#define COMP4_CSR_COMP4INSEL_0          ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
+#define COMP4_CSR_COMP4INSEL_1          ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
+#define COMP4_CSR_COMP4INSEL_2          ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
+#define COMP4_CSR_COMP4NONINSEL         ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */
+#define COMP4_CSR_COMP4WNDWEN           ((uint32_t)0x00000200) /*!< COMP4 window mode enable */
+#define COMP4_CSR_COMP4OUTSEL           ((uint32_t)0x00003C00) /*!< COMP4 output select */
+#define COMP4_CSR_COMP4OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
+#define COMP4_CSR_COMP4OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
+#define COMP4_CSR_COMP4OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
+#define COMP4_CSR_COMP4OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
+#define COMP4_CSR_COMP4POL              ((uint32_t)0x00008000) /*!< COMP4 output polarity */
+#define COMP4_CSR_COMP4HYST             ((uint32_t)0x00030000) /*!< COMP4 hysteresis */
+#define COMP4_CSR_COMP4HYST_0           ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */
+#define COMP4_CSR_COMP4HYST_1           ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */
+#define COMP4_CSR_COMP4BLANKING         ((uint32_t)0x000C0000) /*!< COMP4 blanking */
+#define COMP4_CSR_COMP4BLANKING_0       ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
+#define COMP4_CSR_COMP4BLANKING_1       ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
+#define COMP4_CSR_COMP4BLANKING_2       ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
+#define COMP4_CSR_COMP4OUT              ((uint32_t)0x40000000) /*!< COMP4 output level */
+#define COMP4_CSR_COMP4LOCK             ((uint32_t)0x80000000) /*!< COMP4 lock */
+
+/**********************  Bit definition for COMP5_CSR register  ***************/
+#define COMP5_CSR_COMP5EN               ((uint32_t)0x00000001) /*!< COMP5 enable */
+#define COMP5_CSR_COMP5MODE             ((uint32_t)0x0000000C) /*!< COMP5 power mode */
+#define COMP5_CSR_COMP5MODE_0           ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */
+#define COMP5_CSR_COMP5MODE_1           ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */
+#define COMP5_CSR_COMP5INSEL            ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
+#define COMP5_CSR_COMP5INSEL_0          ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
+#define COMP5_CSR_COMP5INSEL_1          ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
+#define COMP5_CSR_COMP5INSEL_2          ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
+#define COMP5_CSR_COMP5NONINSEL         ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */
+#define COMP5_CSR_COMP5OUTSEL           ((uint32_t)0x00003C00) /*!< COMP5 output select */
+#define COMP5_CSR_COMP5OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
+#define COMP5_CSR_COMP5OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
+#define COMP5_CSR_COMP5OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
+#define COMP5_CSR_COMP5OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
+#define COMP5_CSR_COMP5POL              ((uint32_t)0x00008000) /*!< COMP5 output polarity */
+#define COMP5_CSR_COMP5HYST             ((uint32_t)0x00030000) /*!< COMP5 hysteresis */
+#define COMP5_CSR_COMP5HYST_0           ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */
+#define COMP5_CSR_COMP5HYST_1           ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */
+#define COMP5_CSR_COMP5BLANKING         ((uint32_t)0x000C0000) /*!< COMP5 blanking */
+#define COMP5_CSR_COMP5BLANKING_0       ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
+#define COMP5_CSR_COMP5BLANKING_1       ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
+#define COMP5_CSR_COMP5BLANKING_2       ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
+#define COMP5_CSR_COMP5OUT              ((uint32_t)0x40000000) /*!< COMP5 output level */
+#define COMP5_CSR_COMP5LOCK             ((uint32_t)0x80000000) /*!< COMP5 lock */
+
+/**********************  Bit definition for COMP6_CSR register  ***************/
+#define COMP6_CSR_COMP6EN               ((uint32_t)0x00000001) /*!< COMP6 enable */
+#define COMP6_CSR_COMP6MODE             ((uint32_t)0x0000000C) /*!< COMP6 power mode */
+#define COMP6_CSR_COMP6MODE_0           ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */
+#define COMP6_CSR_COMP6MODE_1           ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */
+#define COMP6_CSR_COMP6INSEL            ((uint32_t)0x00000070) /*!< COMP6 inverting input select */
+#define COMP6_CSR_COMP6INSEL_0          ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
+#define COMP6_CSR_COMP6INSEL_1          ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
+#define COMP6_CSR_COMP6INSEL_2          ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
+#define COMP6_CSR_COMP6NONINSEL         ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */
+#define COMP6_CSR_COMP6WNDWEN           ((uint32_t)0x00000200) /*!< COMP6 window mode enable */
+#define COMP6_CSR_COMP6OUTSEL           ((uint32_t)0x00003C00) /*!< COMP6 output select */
+#define COMP6_CSR_COMP6OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
+#define COMP6_CSR_COMP6OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
+#define COMP6_CSR_COMP6OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
+#define COMP6_CSR_COMP6OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
+#define COMP6_CSR_COMP6POL              ((uint32_t)0x00008000) /*!< COMP6 output polarity */
+#define COMP6_CSR_COMP6HYST             ((uint32_t)0x00030000) /*!< COMP6 hysteresis */
+#define COMP6_CSR_COMP6HYST_0           ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */
+#define COMP6_CSR_COMP6HYST_1           ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */
+#define COMP6_CSR_COMP6BLANKING         ((uint32_t)0x000C0000) /*!< COMP6 blanking */
+#define COMP6_CSR_COMP6BLANKING_0       ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
+#define COMP6_CSR_COMP6BLANKING_1       ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
+#define COMP6_CSR_COMP6BLANKING_2       ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
+#define COMP6_CSR_COMP6OUT              ((uint32_t)0x40000000) /*!< COMP6 output level */
+#define COMP6_CSR_COMP6LOCK             ((uint32_t)0x80000000) /*!< COMP6 lock */
+
+/**********************  Bit definition for COMP7_CSR register  ***************/
+#define COMP7_CSR_COMP7EN               ((uint32_t)0x00000001) /*!< COMP7 enable */
+#define COMP7_CSR_COMP7MODE             ((uint32_t)0x0000000C) /*!< COMP7 power mode */
+#define COMP7_CSR_COMP7MODE_0           ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */
+#define COMP7_CSR_COMP7MODE_1           ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */
+#define COMP7_CSR_COMP7INSEL            ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
+#define COMP7_CSR_COMP7INSEL_0          ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
+#define COMP7_CSR_COMP7INSEL_1          ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
+#define COMP7_CSR_COMP7INSEL_2          ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
+#define COMP7_CSR_COMP7NONINSEL         ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */
+#define COMP7_CSR_COMP7OUTSEL           ((uint32_t)0x00003C00) /*!< COMP7 output select */
+#define COMP7_CSR_COMP7OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
+#define COMP7_CSR_COMP7OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
+#define COMP7_CSR_COMP7OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
+#define COMP7_CSR_COMP7OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
+#define COMP7_CSR_COMP7POL              ((uint32_t)0x00008000) /*!< COMP7 output polarity */
+#define COMP7_CSR_COMP7HYST             ((uint32_t)0x00030000) /*!< COMP7 hysteresis */
+#define COMP7_CSR_COMP7HYST_0           ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */
+#define COMP7_CSR_COMP7HYST_1           ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */
+#define COMP7_CSR_COMP7BLANKING         ((uint32_t)0x000C0000) /*!< COMP7 blanking */
+#define COMP7_CSR_COMP7BLANKING_0       ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
+#define COMP7_CSR_COMP7BLANKING_1       ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
+#define COMP7_CSR_COMP7BLANKING_2       ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
+#define COMP7_CSR_COMP7OUT              ((uint32_t)0x40000000) /*!< COMP7 output level */
+#define COMP7_CSR_COMP7LOCK             ((uint32_t)0x80000000) /*!< COMP7 lock */
+
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_COMPxEN               ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
+#define COMP_CSR_COMPxMODE             ((uint32_t)0x0000000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0           ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1           ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL            ((uint32_t)0x00000070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0          ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1          ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2          ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxNONINSEL         ((uint32_t)0x00000080) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMPxWNDWEN           ((uint32_t)0x00000200) /*!< COMPx window mode enable */
+#define COMP_CSR_COMPxOUTSEL           ((uint32_t)0x00003C00) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0         ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1         ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2         ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxOUTSEL_3         ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
+#define COMP_CSR_COMPxPOL              ((uint32_t)0x00008000) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST             ((uint32_t)0x00030000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0           ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1           ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxBLANKING         ((uint32_t)0x000C0000) /*!< COMPx blanking */
+#define COMP_CSR_COMPxBLANKING_0       ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
+#define COMP_CSR_COMPxBLANKING_1       ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
+#define COMP_CSR_COMPxBLANKING_2       ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
+#define COMP_CSR_COMPxOUT              ((uint32_t)0x40000000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK             ((uint32_t)0x80000000) /*!< COMPx lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Operational Amplifier (OPAMP)                          */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAMP1EN               ((uint32_t)0x00000001) /*!< OPAMP1 enable */
+#define OPAMP1_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP1_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP1_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP1_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP1_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP1_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP1_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP1_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP1_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP1_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP1_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP1_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP1_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP1_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP1_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP1_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP1_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP1_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAMP2EN               ((uint32_t)0x00000001) /*!< OPAMP2 enable */
+#define OPAMP2_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP2_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP2_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP2_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP2_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP2_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP2_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP2_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP2_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP2_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP2_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP2_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP2_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP2_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP2_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP2_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP2_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP2_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/*********************  Bit definition for OPAMP3_CSR register  ***************/
+#define OPAMP3_CSR_OPAMP3EN               ((uint32_t)0x00000001) /*!< OPAMP3 enable */
+#define OPAMP3_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP3_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP3_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP3_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP3_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP3_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP3_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP3_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP3_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP3_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP3_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP3_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP3_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP3_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP3_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP3_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP3_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP3_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP3_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP3_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP3_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/*********************  Bit definition for OPAMP4_CSR register  ***************/
+#define OPAMP4_CSR_OPAMP4EN               ((uint32_t)0x00000001) /*!< OPAMP4 enable */
+#define OPAMP4_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP4_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP4_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP4_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP4_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP4_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP4_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP4_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP4_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP4_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP4_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP4_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP4_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP4_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP4_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP4_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP4_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP4_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP4_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP4_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP4_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN               ((uint32_t)0x00000001) /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Controller Area Network (CAN )                           */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     CRC calculation unit (CRC)                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU (DBGMCU)                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP        ((uint32_t)0x00000004)
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00000004)
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00000008)
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller (DMA)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller (EXTI)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
+#define  EXTI_RTSR_TR24                      ((uint32_t)0x01000000)        /*!< Rising trigger event configuration bit of line 24 */
+#define  EXTI_RTSR_TR25                      ((uint32_t)0x02000000)        /*!< Rising trigger event configuration bit of line 25 */
+#define  EXTI_RTSR_TR26                      ((uint32_t)0x04000000)        /*!< Rising trigger event configuration bit of line 26 */
+#define  EXTI_RTSR_TR27                      ((uint32_t)0x08000000)        /*!< Rising trigger event configuration bit of line 27 */
+#define  EXTI_RTSR_TR28                      ((uint32_t)0x10000000)        /*!< Rising trigger event configuration bit of line 28 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
+#define  EXTI_FTSR_TR24                      ((uint32_t)0x01000000)        /*!< Falling trigger event configuration bit of line 24 */
+#define  EXTI_FTSR_TR25                      ((uint32_t)0x02000000)        /*!< Falling trigger event configuration bit of line 25 */
+#define  EXTI_FTSR_TR26                      ((uint32_t)0x04000000)        /*!< Falling trigger event configuration bit of line 26 */
+#define  EXTI_FTSR_TR27                      ((uint32_t)0x08000000)        /*!< Falling trigger event configuration bit of line 27 */
+#define  EXTI_FTSR_TR28                      ((uint32_t)0x10000000)        /*!< Falling trigger event configuration bit of line 28 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
+#define  EXTI_SWIER_SWIER24                  ((uint32_t)0x01000000)        /*!< Software Interrupt on line 24 */
+#define  EXTI_SWIER_SWIER25                  ((uint32_t)0x02000000)        /*!< Software Interrupt on line 25 */
+#define  EXTI_SWIER_SWIER26                  ((uint32_t)0x04000000)        /*!< Software Interrupt on line 26 */
+#define  EXTI_SWIER_SWIER27                  ((uint32_t)0x08000000)        /*!< Software Interrupt on line 27 */
+#define  EXTI_SWIER_SWIER28                  ((uint32_t)0x10000000)        /*!< Software Interrupt on line 28 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit for line 23 */
+#define  EXTI_PR_PR24                        ((uint32_t)0x01000000)        /*!< Pending bit for line 24 */
+#define  EXTI_PR_PR25                        ((uint32_t)0x02000000)        /*!< Pending bit for line 25 */
+#define  EXTI_PR_PR26                        ((uint32_t)0x04000000)        /*!< Pending bit for line 26 */
+#define  EXTI_PR_PR27                        ((uint32_t)0x08000000)        /*!< Pending bit for line 27 */
+#define  EXTI_PR_PR28                        ((uint32_t)0x10000000)        /*!< Pending bit for line 28 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
+#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x01)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x02)               /*!< Bit 1 */
+
+#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
+#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)  
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+#define  RDP_KEY                             ((uint16_t)0x00A5)            /*!< RDP Key */
+#define  FLASH_KEY1                          ((uint32_t)0x45670123)        /*!< FPEC Key1 */
+#define  FLASH_KEY2                          ((uint32_t)0xCDEF89AB)        /*!< FPEC Key2 */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+#define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
+#define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< OptionBytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */
+
+#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)      /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for FLASH_WRP0 register  ******************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP1 register  ******************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP2 register  ******************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP3 register  ******************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O (GPIO)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)                       
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *****************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *****************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  ********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)        /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG (IWDG)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                       ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
+#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
+#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
+
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLSRC_HSI_Div2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define  RCC_CFGR_PLLMULL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define  RCC_CFGR_USBPRE                     ((uint32_t)0x00400000)        /*!< USB prescaler */
+
+/*!< I2S configuration */
+#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)        /*!< I2S external clock source selection */
+
+/*!< MCO configuration */
+#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+
+#define  RCC_CFGR_MCOF                       ((uint32_t)0x10000000)        /*!< Microcontroller Clock Output Flag */
+
+/*********************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/******************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000200)        /*!< TIM1 reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
+#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000200)        /*!< TIM8 reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 reset */
+
+/******************  Bit definition for RCC_APB1RSTR register  ******************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 reset */
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI3 reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
+#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
+#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR reset */
+#define  RCC_APB1RSTR_DACRST                ((uint32_t)0x20000000)         /*!< DAC reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSEN                     ((uint32_t)0x01000000)        /*!< TS clock enable */
+#define  RCC_AHBENR_ADC12EN                  ((uint32_t)0x10000000)        /*!< ADC1/ ADC2 clock enable */
+#define  RCC_AHBENR_ADC34EN                  ((uint32_t)0x20000000)        /*!< ADC1/ ADC2 clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00002000)        /*!< TIM8 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+
+/******************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI3 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
+/* CHIBIOS FIX */
+#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)        /*!< UART 3 clock enable */
+#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)        /*!< UART 4 clock enable */
+//#define  RCC_APB1ENR_UART3EN                 ((uint32_t)0x00080000)        /*!< UART 3 clock enable */
+//#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00100000)        /*!< UART 4 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF reset */
+#define  RCC_AHBRSTR_TSRST                   ((uint32_t)0x00100000)         /*!< TS reset */
+#define  RCC_AHBRSTR_ADC12RST                ((uint32_t)0x01000000)         /*!< ADC1 & ADC2 reset */
+#define  RCC_AHBRSTR_ADC34RST                ((uint32_t)0x02000000)         /*!< ADC3 & ADC4 reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/*!< ADCPRE12 configuration */
+#define  RCC_CFGR2_ADCPRE12                  ((uint32_t)0x000001F0)        /*!< ADCPRE12[8:4] bits */
+#define  RCC_CFGR2_ADCPRE12_0                ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR2_ADCPRE12_1                ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR2_ADCPRE12_2                ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR2_ADCPRE12_3                ((uint32_t)0x00000080)        /*!< Bit 3 */
+#define  RCC_CFGR2_ADCPRE12_4                ((uint32_t)0x00000100)        /*!< Bit 4 */
+
+#define  RCC_CFGR2_ADCPRE12_NO               ((uint32_t)0x00000000)        /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define  RCC_CFGR2_ADCPRE12_DIV1             ((uint32_t)0x00000100)        /*!< ADC12 PLL clock divided by 1 */
+#define  RCC_CFGR2_ADCPRE12_DIV2             ((uint32_t)0x00000110)        /*!< ADC12 PLL clock divided by 2 */
+#define  RCC_CFGR2_ADCPRE12_DIV4             ((uint32_t)0x00000120)        /*!< ADC12 PLL clock divided by 4 */
+#define  RCC_CFGR2_ADCPRE12_DIV6             ((uint32_t)0x00000130)        /*!< ADC12 PLL clock divided by 6 */
+#define  RCC_CFGR2_ADCPRE12_DIV8             ((uint32_t)0x00000140)        /*!< ADC12 PLL clock divided by 8 */
+#define  RCC_CFGR2_ADCPRE12_DIV10            ((uint32_t)0x00000150)        /*!< ADC12 PLL clock divided by 10 */
+#define  RCC_CFGR2_ADCPRE12_DIV12            ((uint32_t)0x00000160)        /*!< ADC12 PLL clock divided by 12 */
+#define  RCC_CFGR2_ADCPRE12_DIV16            ((uint32_t)0x00000170)        /*!< ADC12 PLL clock divided by 16 */
+#define  RCC_CFGR2_ADCPRE12_DIV32            ((uint32_t)0x00000180)        /*!< ADC12 PLL clock divided by 32 */
+#define  RCC_CFGR2_ADCPRE12_DIV64            ((uint32_t)0x00000190)        /*!< ADC12 PLL clock divided by 64 */
+#define  RCC_CFGR2_ADCPRE12_DIV128           ((uint32_t)0x000001A0)        /*!< ADC12 PLL clock divided by 128 */
+#define  RCC_CFGR2_ADCPRE12_DIV256           ((uint32_t)0x000001B0)        /*!< ADC12 PLL clock divided by 256 */
+
+/*!< ADCPRE34 configuration */
+#define  RCC_CFGR2_ADCPRE34                  ((uint32_t)0x00003E00)        /*!< ADCPRE34[13:5] bits */
+#define  RCC_CFGR2_ADCPRE34_0                ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  RCC_CFGR2_ADCPRE34_1                ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  RCC_CFGR2_ADCPRE34_2                ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  RCC_CFGR2_ADCPRE34_3                ((uint32_t)0x00001000)        /*!< Bit 3 */
+#define  RCC_CFGR2_ADCPRE34_4                ((uint32_t)0x00002000)        /*!< Bit 4 */
+
+#define  RCC_CFGR2_ADCPRE34_NO               ((uint32_t)0x00000000)        /*!< ADC34 clock disabled, ADC34 can use AHB clock */
+#define  RCC_CFGR2_ADCPRE34_DIV1             ((uint32_t)0x00002000)        /*!< ADC34 PLL clock divided by 1 */
+#define  RCC_CFGR2_ADCPRE34_DIV2             ((uint32_t)0x00002200)        /*!< ADC34 PLL clock divided by 2 */
+#define  RCC_CFGR2_ADCPRE34_DIV4             ((uint32_t)0x00002400)        /*!< ADC34 PLL clock divided by 4 */
+#define  RCC_CFGR2_ADCPRE34_DIV6             ((uint32_t)0x00002600)        /*!< ADC34 PLL clock divided by 6 */
+#define  RCC_CFGR2_ADCPRE34_DIV8             ((uint32_t)0x00002800)        /*!< ADC34 PLL clock divided by 8 */
+#define  RCC_CFGR2_ADCPRE34_DIV10            ((uint32_t)0x00002A00)        /*!< ADC34 PLL clock divided by 10 */
+#define  RCC_CFGR2_ADCPRE34_DIV12            ((uint32_t)0x00002C00)        /*!< ADC34 PLL clock divided by 12 */
+#define  RCC_CFGR2_ADCPRE34_DIV16            ((uint32_t)0x00002E00)        /*!< ADC34 PLL clock divided by 16 */
+#define  RCC_CFGR2_ADCPRE34_DIV32            ((uint32_t)0x00003000)        /*!< ADC34 PLL clock divided by 32 */
+#define  RCC_CFGR2_ADCPRE34_DIV64            ((uint32_t)0x00003200)        /*!< ADC34 PLL clock divided by 64 */
+#define  RCC_CFGR2_ADCPRE34_DIV128           ((uint32_t)0x00003400)        /*!< ADC34 PLL clock divided by 128 */
+#define  RCC_CFGR2_ADCPRE34_DIV256           ((uint32_t)0x00003600)        /*!< ADC34 PLL clock divided by 256 */
+
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR3_I2CSW                     ((uint32_t)0x00000030)        /*!< I2CSW bits */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 
+#define  RCC_CFGR3_I2C2SW                    ((uint32_t)0x00000020)        /*!< I2C2SW bits */
+
+#define  RCC_CFGR3_TIMSW                     ((uint32_t)0x00000300)        /*!< TIMSW bits */
+#define  RCC_CFGR3_TIM1SW                    ((uint32_t)0x00000100)        /*!< TIM1SW bits */ 
+#define  RCC_CFGR3_TIM8SW                    ((uint32_t)0x00000200)        /*!< TIM8SW bits */
+
+#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  RCC_CFGR3_UART4SW                   ((uint32_t)0x00300000)        /*!< UART4SW[1:0] bits */
+#define  RCC_CFGR3_UART4SW_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  RCC_CFGR3_UART4SW_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  RCC_CFGR3_UART5SW                   ((uint32_t)0x00C00000)        /*!< UART5SW[1:0] bits */
+#define  RCC_CFGR3_UART5SW_0                 ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  RCC_CFGR3_UART5SW_1                 ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        System Configuration(SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  *****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_CFGR1_USB_IT_RMP             ((uint32_t)0x00000020) /*!< USB interrupt remap */
+#define SYSCFG_CFGR1_TIM1_ITR3_RMP          ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
+#define SYSCFG_CFGR1_DAC_TRIG_RMP           ((uint32_t)0x00000080) /*!< DAC Trigger remap */
+#define SYSCFG_CFGR1_ADC24_DMA_RMP          ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1_DMA_RMP       ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC2_DMA_RMP       ((uint32_t)0x00004000) /*!< Timer 7 / DAC2 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP               ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP               ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_ENCODER_MODE           ((uint32_t)0x00C00000) /*!< Encoder Mode */
+#define SYSCFG_CFGR1_ENCODER_MODE_0         ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
+#define SYSCFG_CFGR1_ENCODER_MODE_1         ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
+#define SYSCFG_CFGR1_FPU_IE                 ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
+#define SYSCFG_CFGR1_FPU_IE_0               ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
+#define SYSCFG_CFGR1_FPU_IE_1               ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
+#define SYSCFG_CFGR1_FPU_IE_2               ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
+#define SYSCFG_CFGR1_FPU_IE_3               ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
+#define SYSCFG_CFGR1_FPU_IE_4               ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
+#define SYSCFG_CFGR1_FPU_IE_5               ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
+
+/*****************  Bit definition for SYSCFG_RCR register  *******************/
+#define SYSCFG_RCR_PAGE0          ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
+#define SYSCFG_RCR_PAGE1          ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
+#define SYSCFG_RCR_PAGE2          ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
+#define SYSCFG_RCR_PAGE3          ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
+#define SYSCFG_RCR_PAGE4          ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
+#define SYSCFG_RCR_PAGE5          ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
+#define SYSCFG_RCR_PAGE6          ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
+#define SYSCFG_RCR_PAGE7          ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/** 
+  * @brief  EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/** 
+  * @brief  EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/** 
+  * @brief  EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/** 
+  * @brief  EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTIRCR_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTIRCR_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTIRCR_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTIRCR_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/** 
+  * @brief  EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTIRCR_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTIRCR_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/** 
+  * @brief  EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTIRCR_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTIRCR_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
+
+/** 
+  * @brief  EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTIRCR_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTIRCR_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/** 
+  * @brief  EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTIRCR_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTIRCR_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTIRCR_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTIRCR_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTIRCR_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/** 
+  * @brief  EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/** 
+  * @brief  EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/** 
+  * @brief  EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/** 
+  * @brief  EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/** 
+  * @brief  EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/** 
+  * @brief  EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/** 
+  * @brief  EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/** 
+  * @brief  EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 */
+#define SYSCFG_CFGR2_BYP_ADDR_PAR              ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
+#define SYSCFG_CFGR2_SRAM_PE                   ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CR1_UIFREMAP                    ((uint16_t)0x0800)            /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint32_t)0x00000001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint32_t)0x00000004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint32_t)0x00000100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint32_t)0x00000200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint32_t)0x00000400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint32_t)0x00000800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint32_t)0x00001000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint32_t)0x00002000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint32_t)0x00004000)            /*!<Output Idle state 4 (OC4 output) */
+#define  TIM_CR2_OIS5                        ((uint32_t)0x00010000)            /*!<Output Idle state 4 (OC4 output) */
+#define  TIM_CR2_OIS6                        ((uint32_t)0x00020000)            /*!<Output Idle state 4 (OC4 output) */
+
+#define  TIM_CR2_MMS2                        ((uint32_t)0x00F00000)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS2_0                      ((uint32_t)0x00100000)            /*!<Bit 0 */
+#define  TIM_CR2_MMS2_1                      ((uint32_t)0x00200000)            /*!<Bit 1 */
+#define  TIM_CR2_MMS2_2                      ((uint32_t)0x00400000)            /*!<Bit 2 */
+#define  TIM_CR2_MMS2_3                      ((uint32_t)0x00800000)            /*!<Bit 2 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint32_t)0x00010007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define  TIM_SMCR_SMS_3                      ((uint32_t)0x00010000)            /*!<Bit 3 */
+
+#define  TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint32_t)0x00000020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint32_t)0x00000080)            /*!<Break interrupt Flag */
+#define  TIM_SR_B2IF                         ((uint32_t)0x00000100)            /*!<Break2 interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */
+#define  TIM_SR_CC5IF                        ((uint32_t)0x00010000)            /*!<Capture/Compare 5 interrupt Flag */
+#define  TIM_SR_CC6IF                        ((uint32_t)0x00020000)            /*!<Capture/Compare 6 interrupt Flag */
+
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint16_t)0x0001)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint16_t)0x0002)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint16_t)0x0004)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint16_t)0x0008)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint16_t)0x0010)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint16_t)0x0020)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint16_t)0x0040)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint16_t)0x0080)               /*!<Break Generation */
+#define  TIM_EGR_B2G                         ((uint16_t)0x0100)               /*!<Break Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint32_t)0x00010070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M_3                    ((uint32_t)0x00010000)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint32_t)0x01007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M_3                    ((uint32_t)0x01000000)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M_3                    ((uint32_t)0x00010000)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M_3                    ((uint32_t)0x00100000)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x00000004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x00000008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x00000010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x00000020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x00000040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x00000080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x00000400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x00000800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x00001000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x00002000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x00004000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x00008000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint32_t)0x00000040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC5E                       ((uint32_t)0x00010000)            /*!<Capture/Compare 5 output enable */
+#define  TIM_CCER_CC5P                       ((uint32_t)0x00020000)            /*!<Capture/Compare 5 output Polarity */
+#define  TIM_CCER_CC6E                       ((uint32_t)0x00100000)            /*!<Capture/Compare 6 output enable */
+#define  TIM_CCER_CC6P                       ((uint32_t)0x00200000)            /*!<Capture/Compare 6 output Polarity */
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFFFFF)            /*!<Counter Value */
+#define  TIM_CNT_UIFCPY                      ((uint32_t)0x80000000)                                        /*!<Update interrupt flag copy */
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define  TIM_CCR5_CCR5                       ((uint32_t)0xFFFFFFFF)        /*!<Capture/Compare 5 Value */
+#define  TIM_CCR5_GC5C1                      ((uint32_t)0x20000000)        /*!<Group Channel 5 and Channel 1 */
+#define  TIM_CCR5_GC5C2                      ((uint32_t)0x40000000)        /*!<Group Channel 5 and Channel 2 */
+#define  TIM_CCR5_GC5C3                      ((uint32_t)0x80000000)        /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint32_t)0x000000FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint32_t)0x00000010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint32_t)0x00000020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint32_t)0x00000040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint32_t)0x00000080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint32_t)0x00000300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x00000100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x00000200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint32_t)0x00000400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint32_t)0x00000800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint32_t)0x00001000)            /*!<Break enable for Break1 */
+#define  TIM_BDTR_BKP                        ((uint32_t)0x00002000)            /*!<Break Polarity for Break1 */
+#define  TIM_BDTR_AOE                        ((uint32_t)0x00004000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint32_t)0x00008000)            /*!<Main Output enable */
+
+#define  TIM_BDTR_BKF                        ((uint32_t)0x000F0000)            /*!<Break Filter for Break1 */
+#define  TIM_BDTR_BK2F                       ((uint32_t)0x00F00000)            /*!<Break Filter for Break2 */
+
+#define  TIM_BDTR_BK2E                       ((uint32_t)0x01000000)            /*!<Break enable for Break2 */
+#define  TIM_BDTR_BK2P                       ((uint32_t)0x02000000)            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM16_OR register  *********************/
+#define TIM16_OR_TI1_RMP                     ((uint16_t)0x00C0)            /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
+#define TIM16_OR_TI1_RMP_0                   ((uint16_t)0x0040)            /*!<Bit 0 */
+#define TIM16_OR_TI1_RMP_1                   ((uint16_t)0x0080)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM1_OR register  *********************/
+#define TIM1_OR_ETR_RMP                      ((uint16_t)0x000F)            /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
+#define TIM1_OR_ETR_RMP_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM1_OR_ETR_RMP_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+#define TIM1_OR_ETR_RMP_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
+#define TIM1_OR_ETR_RMP_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM8_OR register  *********************/
+#define TIM8_OR_ETR_RMP                      ((uint16_t)0x000F)            /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
+#define TIM8_OR_ETR_RMP_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM8_OR_ETR_RMP_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+#define TIM8_OR_ETR_RMP_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
+#define TIM8_OR_ETR_RMP_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define  TIM_CCMR3_OC5FE                     ((uint32_t)0x00000004)            /*!<Output Compare 5 Fast enable */
+#define  TIM_CCMR3_OC5PE                     ((uint32_t)0x00000008)            /*!<Output Compare 5 Preload enable */
+
+#define  TIM_CCMR3_OC5M                      ((uint32_t)0x00000070)            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define  TIM_CCMR3_OC5M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define  TIM_CCMR3_OC5M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define  TIM_CCMR3_OC5M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define  TIM_CCMR3_OC5M_3                    ((uint32_t)0x00010000)            /*!<Bit 3 */
+
+#define  TIM_CCMR3_OC5CE                     ((uint32_t)0x00000080)            /*!<Output Compare 5 Clear Enable */
+
+#define  TIM_CCMR3_OC6FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR3_OC6PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR3_OC6M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR3_OC6M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
+#define  TIM_CCMR3_OC6M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
+#define  TIM_CCMR3_OC6M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
+#define  TIM_CCMR3_OC6M_3                    ((uint32_t)0x00100000)            /*!<Bit 3 */
+
+#define  TIM_CCMR3_OC6CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                     ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                     ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                      ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                     ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                     ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                       ((uint32_t)0x00000004)            /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f30x_conf.h"
+#endif /* USE_STDPERIPH_DRIVER */
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F30x_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/stm32f37x.h b/os/ext/CMSIS/ST/stm32f37x.h
new file mode 100644
index 000000000..33abf3b16
--- /dev/null
+++ b/os/ext/CMSIS/ST/stm32f37x.h
@@ -0,0 +1,5438 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral registers definitions, bits 
+  *          definitions and memory mapping for STM32F37x devices.
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral�s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral registers declarations and bits definition
+  *           - Macros to access peripheral registers hardware
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
+  * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f37x
+  * @{
+  */
+    
+#ifndef __STM32F37x_H
+#define __STM32F37x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F37X) 
+/*  #define STM32F37X */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined (STM32F37X)
+ #error "Please select first the target STM32F37X device used in your application (in stm32f37x.h file)"
+#endif
+
+#if !defined  (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */           
+#if !defined  (HSE_VALUE) 
+ #define HSE_VALUE            ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT) 
+ #define HSE_STARTUP_TIMEOUT  ((uint16_t)0x0500)   /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
+   Timeout value 
+   */
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
+
+#if !defined  (HSI_VALUE) 
+ #define HSI_VALUE  ((uint32_t)8000000)
+#endif /* HSI_VALUE */                      /*!< Value of the Internal High Speed oscillator in Hz.
+                                            The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)40000)    
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */     
+
+/**
+ * @brief STM32F37x Standard Peripherals Library version number V1.0.0
+   */
+#define __STM32F37X_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
+#define __STM32F37X_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32F37X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F37X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F37X_STDPERIPH_VERSION       ( (__STM32F37X_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F37X_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F37X_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F37X_STDPERIPH_VERSION_RC))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+ */
+#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1         /*!< STM32F37X provide an MPU */
+#define __NVIC_PRIO_BITS          4         /*!< STM32F37X uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             1         /*!< STM32F37X provide an FPU */
+
+
+/**
+ * @brief STM32F37X Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line 19          */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line 20                     */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_TS_IRQn               = 8,      /*!< EXTI Line2 Interrupt and Touch Sense Interrupt                    */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
+  ADC1_IRQn                   = 18,     /*!< ADC1 Interrupts                                                   */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                  */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                 */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                 */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                 */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM15_IRQn                  = 24,     /*!< TIM15 global Interrupt                                            */
+  TIM16_IRQn                  = 25,     /*!< TIM16 global Interrupt                                            */
+  TIM17_IRQn                  = 26,     /*!< TIM17 global Interrupt                                            */
+  TIM18_DAC2_IRQn             = 27,     /*!< TIM18 global Interrupt and DAC2 underrun Interrupt                */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  CEC_IRQn                    = 42,     /*!< CEC Interrupt                                                     */    
+  TIM12_IRQn                  = 43,     /*!< TIM12 global interrupt                                            */
+  TIM13_IRQn                  = 44,     /*!< TIM13 global interrupt                                            */
+  TIM14_IRQn                  = 45,     /*!< TIM14 global interrupt                                            */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  TIM6_DAC1_IRQn              = 54,     /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  SDADC1_IRQn                 = 61,     /*!< ADC Sigma Delta 1 global Interrupt                                */
+  SDADC2_IRQn                 = 62,     /*!< ADC Sigma Delta 2 global Interrupt                                */
+  SDADC3_IRQn                 = 63,     /*!< ADC Sigma Delta 1 global Interrupt                                */
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 global Interrupt                                  */
+  USB_HP_IRQn                 = 74,     /*!< USB High Priority global Interrupt                                */
+  USB_LP_IRQn                 = 75,     /*!< USB Low Priority global Interrupt                                 */
+  USBWakeUp_IRQn              = 76,     /*!< USB Wakeup Interrupt                                              */
+  TIM19_IRQn                  = 78,     /*!< TIM19 global Interrupt                                            */
+  FPU_IRQn                    = 81      /*!< Floating point Interrupt                                          */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"            /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f37x.h"    /* STM32F37x System Header */
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;    /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;   /*!< ADC control register 1,                      Address offset: 0x04 */
+  __IO uint32_t CR2;   /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1; /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2; /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;   /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;   /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;  /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;  /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;  /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;  /*!< ADC injected sequence register,              Address offset: 0x38 */
+  __IO uint32_t JDR1;  /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;  /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;  /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;  /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;    /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+  
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+  
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief Consumer Electronics Control     
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
+}CEC_TypeDef;
+
+/** 
+  * @brief Analog Comparators 
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+} DMA_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;          /*!< FLASH access control register,              Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!< FLASH key register,                         Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!< FLASH option key register,                  Address offset: 0x08 */
+  __IO uint32_t SR;           /*!< FLASH status register,                      Address offset: 0x0C */
+  __IO uint32_t CR;           /*!< FLASH control register,                     Address offset: 0x10 */
+  __IO uint32_t AR;           /*!< FLASH address register,                     Address offset: 0x14 */
+  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                   */
+  __IO uint32_t OBR;          /*!< FLASH Option byte register,                 Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!< FLASH Write register,                       Address offset: 0x20 */
+  
+} FLASH_TypeDef;
+
+/** 
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
+  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
+  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
+  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
+  __IO uint16_t WRP2;         /*!<FLASH option byte write protection 2,          Address offset: 0x10 */
+  __IO uint16_t WRP3;         /*!<FLASH option byte write protection 3,          Address offset: 0x12 */
+} OB_TypeDef;
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
+}GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                      Address offset: 0x00 */
+       uint32_t RESERVED;    /*!< Reserved,                                                             0x04 */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG control register,                              Adress offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                      Address offset: 0x18 */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  
+}I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */ 
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */ 
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+  
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  uint32_t RESERVED0;       /*!< Reserved, 0x18                                                                 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                   Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                   Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                   Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                   Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                   Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                   Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                   Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                   Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                   Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                   Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                   Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                   Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                   Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Sigma-Delta Analog to Digital Converter (SDADC)  
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;          /*!< SDADC control register 1,                        Address offset: 0x00 */
+  __IO uint32_t CR2;          /*!< SDADC control register 2,                        Address offset: 0x04 */
+  __IO uint32_t ISR;          /*!< SDADC interrupt and status register,             Address offset: 0x08 */
+  __IO uint32_t CLRISR;       /*!< SDADC clear interrupt and status register,       Address offset: 0x0C */
+  __IO uint32_t RESERVED0;    /*!< Reserved, 0x10                                                        */
+  __IO uint32_t JCHGR;        /*!< SDADC injected channel group selection register, Address offset: 0x14 */
+  __IO uint32_t RESERVED1;    /*!< Reserved, 0x18                                                        */
+  __IO uint32_t RESERVED2;    /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t CONF0R;       /*!< SDADC configuration 0 register,                  Address offset: 0x20 */
+  __IO uint32_t CONF1R;       /*!< SDADC configuration 1 register,                  Address offset: 0x24 */
+  __IO uint32_t CONF2R;       /*!< SDADC configuration 2 register,                  Address offset: 0x28 */
+  __IO uint32_t RESERVED3[5]; /*!< Reserved, 0x2C - 0x3C                                                 */
+  __IO uint32_t CONFCHR1;     /*!< SDADC channel configuration register 1,          Address offset: 0x40 */
+  __IO uint32_t CONFCHR2;     /*!< SDADC channel configuration register 2,          Address offset: 0x44 */
+  __IO uint32_t RESERVED4[6]; /*!< Reserved, 0x48 - 0x5C                                                 */
+  __IO uint32_t JDATAR;       /*!< SDADC data register for injected group,          Address offset: 0x60 */
+  __IO uint32_t RDATAR;       /*!< SDADC data register for the regular channel,     Address offset: 0x64 */
+  __IO uint32_t RESERVED5[2]; /*!< Reserved, 0x68 - 0x6C                                                 */
+  __IO uint32_t JDATA12R;     /*!< SDADC1 and SDADC2 injected data register,        Address offset: 0x70 */
+  __IO uint32_t RDATA12R;     /*!< SDADC1 and SDADC2 regular data register,         Address offset: 0x74 */
+  __IO uint32_t JDATA13R;     /*!< SDADC1 and SDADC3 injected data register,        Address offset: 0x78 */
+  __IO uint32_t RDATA13R;     /*!< SDADC1 and SDADC3 regular data register,         Address offset: 0x7C */
+} SDADC_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+  
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
+  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
+} SPI_TypeDef;
+
+
+/** 
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
+  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
+  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
+  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
+  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
+  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
+  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
+  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
+  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
+  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
+  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
+  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
+} TIM_TypeDef;
+
+/** 
+  * @brief Touch Sensing Controller (TSC)
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+  
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
+  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef; 
+
+/** 
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
+#define DAC2_BASE             (APB1PERIPH_BASE + 0x9800)
+#define TIM18_BASE            (APB1PERIPH_BASE + 0x9C00)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000)
+#define COMP_BASE             (APB2PERIPH_BASE + 0x001C)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM19_BASE            (APB2PERIPH_BASE + 0x5C00)
+#define SDADC1_BASE           (APB2PERIPH_BASE + 0x6000)
+#define SDADC2_BASE           (APB2PERIPH_BASE + 0x6400)
+#define SDADC3_BASE           (APB2PERIPH_BASE + 0x6800)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE    (AHB1PERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (AHB1PERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (AHB1PERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (AHB1PERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (AHB1PERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (AHB1PERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (AHB1PERIPH_BASE + 0x0080)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE    (AHB1PERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE    (AHB1PERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE    (AHB1PERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE    (AHB1PERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE    (AHB1PERIPH_BASE + 0x0458)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)     /*!< Flash Option Bytes base address */
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x00004000)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400)
+
+#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define DAC2                ((DAC_TypeDef *) DAC2_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define TIM18               ((TIM_TypeDef *) TIM18_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM19               ((TIM_TypeDef *) TIM19_BASE)
+#define SDADC1              ((SDADC_TypeDef *) SDADC1_BASE)
+#define SDADC2              ((SDADC_TypeDef *) SDADC2_BASE)
+#define SDADC3              ((SDADC_TypeDef *) SDADC3_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter SAR (ADC)               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint32_t)0x00000001)  /*!< Analog watchdog flag */
+#define  ADC_SR_EOC                          ((uint32_t)0x00000002)  /*!< End of conversion */
+#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)  /*!< Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)  /*!< Injected channel Start flag */
+#define  ADC_SR_STRT                         ((uint32_t)0x00000010)  /*!< Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)  /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)  /*!< Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)  /*!< Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)  /*!< Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)  /*!< Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)  /*!< Bit 4 */
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)  /*!< Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)  /*!< Analog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)  /*!< Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)  /*!< Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)  /*!< Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)  /*!< Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)  /*!< Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)  /*!< Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)  /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)  /*!< Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)  /*!< Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)  /*!< Bit 2 */
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)  /*!< Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)  /*!< Analog watchdog enable on regular channels */
+
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)  /*!< A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)  /*!< Continuous Conversion */
+#define  ADC_CR2_CAL                         ((uint32_t)0x00000004)  /*!< A/D Calibration */
+#define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)  /*!< Reset Calibration */
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)  /*!< Direct Memory access mode */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)  /*!< Data Alignment */
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)  /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)  /*!< Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)  /*!< Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)  /*!< Bit 2 */
+#define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)  /*!< External Trigger Conversion mode for injected channels */
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)  /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)  /*!< Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)  /*!< Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)  /*!< Bit 2 */
+#define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)  /*!< External Trigger Conversion mode for regular channels */
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)  /*!< Start Conversion of injected channels */
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)  /*!< Start Conversion of regular channels */
+#define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)  /*!< Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)  /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)  /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)  /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)  /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)  /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)  /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL           ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2         ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL              ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST             ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0           ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1           ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT              ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK             ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN               ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE             ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0           ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1           ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL            ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0          ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1          ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2          ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN                ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL           ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0         ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1         ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2         ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL              ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST             ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0           ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1           ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Controller Area Network (CAN )                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     CRC calculation unit (CRC)                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU (DBGMCU)                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP        ((uint32_t)0x00000004)
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP        ((uint32_t)0x00000008)
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP       ((uint32_t)0x00000040)
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP       ((uint32_t)0x00000080)
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)
+#define  DBGMCU_APB1_FZ_DBG_TIM18_STOP       ((uint32_t)0x00000200)
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00000004)
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00000008)
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00000010)
+#define  DBGMCU_APB2_FZ_DBG_TIM19_STOP       ((uint32_t)0x00000020)
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller (DMA)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller (EXTI)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
+#define  EXTI_RTSR_TR24                      ((uint32_t)0x01000000)        /*!< Rising trigger event configuration bit of line 24 */
+#define  EXTI_RTSR_TR25                      ((uint32_t)0x02000000)        /*!< Rising trigger event configuration bit of line 25 */
+#define  EXTI_RTSR_TR26                      ((uint32_t)0x04000000)        /*!< Rising trigger event configuration bit of line 26 */
+#define  EXTI_RTSR_TR27                      ((uint32_t)0x08000000)        /*!< Rising trigger event configuration bit of line 27 */
+#define  EXTI_RTSR_TR28                      ((uint32_t)0x10000000)        /*!< Rising trigger event configuration bit of line 28 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
+#define  EXTI_FTSR_TR24                      ((uint32_t)0x01000000)        /*!< Falling trigger event configuration bit of line 24 */
+#define  EXTI_FTSR_TR25                      ((uint32_t)0x02000000)        /*!< Falling trigger event configuration bit of line 25 */
+#define  EXTI_FTSR_TR26                      ((uint32_t)0x04000000)        /*!< Falling trigger event configuration bit of line 26 */
+#define  EXTI_FTSR_TR27                      ((uint32_t)0x08000000)        /*!< Falling trigger event configuration bit of line 27 */
+#define  EXTI_FTSR_TR28                      ((uint32_t)0x10000000)        /*!< Falling trigger event configuration bit of line 28 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
+#define  EXTI_SWIER_SWIER24                  ((uint32_t)0x01000000)        /*!< Software Interrupt on line 24 */
+#define  EXTI_SWIER_SWIER25                  ((uint32_t)0x02000000)        /*!< Software Interrupt on line 25 */
+#define  EXTI_SWIER_SWIER26                  ((uint32_t)0x04000000)        /*!< Software Interrupt on line 26 */
+#define  EXTI_SWIER_SWIER27                  ((uint32_t)0x08000000)        /*!< Software Interrupt on line 27 */
+#define  EXTI_SWIER_SWIER28                  ((uint32_t)0x10000000)        /*!< Software Interrupt on line 28 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit for line 23 */
+#define  EXTI_PR_PR24                        ((uint32_t)0x01000000)        /*!< Pending bit for line 24 */
+#define  EXTI_PR_PR25                        ((uint32_t)0x02000000)        /*!< Pending bit for line 25 */
+#define  EXTI_PR_PR26                        ((uint32_t)0x04000000)        /*!< Pending bit for line 26 */
+#define  EXTI_PR_PR27                        ((uint32_t)0x08000000)        /*!< Pending bit for line 27 */
+#define  EXTI_PR_PR28                        ((uint32_t)0x10000000)        /*!< Pending bit for line 28 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
+#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x01)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x02)               /*!< Bit 1 */
+
+#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
+#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< OptionBytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */
+
+#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)      /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for FLASH_WRP0 register  ******************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP1 register  ******************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP2 register  ******************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP3 register  ******************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O (GPIO)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)        /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG (IWDG)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                       ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          HDMI-CEC (CEC)                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                              */
+#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message                 */
+#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message                   */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time                    */
+#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                           */
+#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                             */
+#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation         */
+#define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation        */
+#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional           */
+#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast No error generation       */
+#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                         */
+#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                         */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                              */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                              */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                      */
+#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                      */
+#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                            */
+#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                   */
+#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error             */
+#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error              */
+#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge                */
+#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                      */
+#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                       */
+#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                   */
+#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                    */
+#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                              */
+#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge                */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable            */
+#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable            */
+#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable                  */
+#define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable         */
+#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable   */
+#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable    */
+#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable            */
+#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable            */
+#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable         */
+#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                    */
+#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+#define  PWR_CR_SDADC1EN                     ((uint16_t)0x0200)     /*!< Enable Analog part of the SDADC1 */
+#define  PWR_CR_SDADC2EN                     ((uint16_t)0x0400)     /*!< Enable Analog part of the SDADC2 */
+#define  PWR_CR_SDADC3EN                     ((uint16_t)0x0800)     /*!< Enable Analog part of the SDADC3 */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
+#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
+#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+/*!< ADCPRE configuration */
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)
+#define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)
+#define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)
+
+#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< ADC CLK divided by 2 */
+#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< ADC CLK divided by 4 */
+#define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< ADC CLK divided by 6 */
+#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< ADC CLK divided by 8 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLSRC_HSI_Div2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define  RCC_CFGR_PLLMULL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define  RCC_CFGR_USBPRE                     ((uint32_t)0x00400000)        /*!< USB prescaler */
+
+/*!< MCO configuration */
+#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!< SDADCPRE configuration */
+#define  RCC_CFGR_SDADCPRE                   ((uint32_t)0xF8000000)        /*!< SDADCPRE[4:0] bits (Sigma Delta ADC prescaler) */
+#define  RCC_CFGR_SDADCPRE_0                 ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  RCC_CFGR_SDADCPRE_1                 ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  RCC_CFGR_SDADCPRE_2                 ((uint32_t)0x20000000)        /*!< Bit 2 */
+#define  RCC_CFGR_SDADCPRE_3                 ((uint32_t)0x40000000)        /*!< Bit 3 */
+#define  RCC_CFGR_SDADCPRE_4                 ((uint32_t)0x80000000)        /*!< Bit 4 */
+
+#define  RCC_CFGR_SDADCPRE_DIV1              ((uint32_t)0x00000000)        /*!< SDADC CLK not divided */
+#define  RCC_CFGR_SDADCPRE_DIV2              ((uint32_t)0x80000000)        /*!< SDADC CLK divided by 2 */
+#define  RCC_CFGR_SDADCPRE_DIV4              ((uint32_t)0x88000000)        /*!< SDADC CLK divided by 4 */
+#define  RCC_CFGR_SDADCPRE_DIV6              ((uint32_t)0x90000000)        /*!< SDADC CLK divided by 6 */
+#define  RCC_CFGR_SDADCPRE_DIV8              ((uint32_t)0x98000000)        /*!< SDADC CLK divided by 8 */
+#define  RCC_CFGR_SDADCPRE_DIV10             ((uint32_t)0xA0000000)        /*!< SDADC CLK divided by 10 */
+#define  RCC_CFGR_SDADCPRE_DIV12             ((uint32_t)0xA8000000)        /*!< SDADC CLK divided by 12 */
+#define  RCC_CFGR_SDADCPRE_DIV14             ((uint32_t)0xB0000000)        /*!< SDADC CLK divided by 14 */
+#define  RCC_CFGR_SDADCPRE_DIV16             ((uint32_t)0xB8000000)        /*!< SDADC CLK divided by 16 */
+#define  RCC_CFGR_SDADCPRE_DIV20             ((uint32_t)0xC0000000)        /*!< SDADC CLK divided by 20 */
+#define  RCC_CFGR_SDADCPRE_DIV24             ((uint32_t)0xC8000000)        /*!< SDADC CLK divided by 24 */
+#define  RCC_CFGR_SDADCPRE_DIV28             ((uint32_t)0xD0000000)        /*!< SDADC CLK divided by 28 */
+#define  RCC_CFGR_SDADCPRE_DIV32             ((uint32_t)0xD8000000)        /*!< SDADC CLK divided by 32 */
+#define  RCC_CFGR_SDADCPRE_DIV36             ((uint32_t)0xE0000000)        /*!< SDADC CLK divided by 36 */
+#define  RCC_CFGR_SDADCPRE_DIV40             ((uint32_t)0xE8000000)        /*!< SDADC CLK divided by 40 */
+#define  RCC_CFGR_SDADCPRE_DIV44             ((uint32_t)0xF0000000)        /*!< SDADC CLK divided by 44 */
+#define  RCC_CFGR_SDADCPRE_DIV48             ((uint32_t)0xF8000000)        /*!< SDADC CLK divided by 48 */
+
+/*********************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/******************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG reset */
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 reset */
+#define  RCC_APB2RSTR_TIM19RST               ((uint32_t)0x00080000)        /*!< TIM19 reset */
+#define  RCC_APB2RSTR_SDADC1RST              ((uint32_t)0x01000000)        /*!< SDADC1 reset */
+#define  RCC_APB2RSTR_SDADC2RST              ((uint32_t)0x02000000)        /*!< SDADC2 reset */
+#define  RCC_APB2RSTR_SDADC3RST              ((uint32_t)0x04000000)        /*!< SDADC3 reset */
+
+/******************  Bit definition for RCC_APB1RSTR register  ******************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
+#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< Timer 12 reset */
+#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< Timer 13 reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 reset */
+#define  RCC_APB1RSTR_TIM18RST               ((uint32_t)0x00000200)        /*!< Timer 18 reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 reset */
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI3 reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN reset */
+#define  RCC_APB1RSTR_DAC2RST                ((uint32_t)0x04000000)        /*!< DAC 2 reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR reset */
+#define  RCC_APB1RSTR_DAC1RST                ((uint32_t)0x20000000)        /*!< DAC 1 reset */
+#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+
+#define  RCC_AHBENR_TSEN                     ((uint32_t)0x01000000)        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_TIM19EN                 ((uint32_t)0x00080000)        /*!< TIM19 clock enable */
+#define  RCC_APB2ENR_SDADC1EN                ((uint32_t)0x01000000)        /*!< SDADC1 clock enable */
+#define  RCC_APB2ENR_SDADC2EN                ((uint32_t)0x02000000)        /*!< SDADC2 clock enable */
+#define  RCC_APB2ENR_SDADC3EN                ((uint32_t)0x04000000)        /*!< SDADC3 clock enable */
+
+/******************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)        /*!< Timer 12 clock enable */
+#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)        /*!< Timer 13 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_TIM18EN                 ((uint32_t)0x00000200)        /*!< Timer 18 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI3 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN clock enable */
+#define  RCC_APB1ENR_DAC2EN                  ((uint32_t)0x04000000)        /*!< DAC 2 clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+#define  RCC_APB1ENR_DAC1EN                  ((uint32_t)0x20000000)        /*!< DAC 1 clock enable */
+#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBL                         ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF reset */
+#define  RCC_AHBRSTR_TSRST                   ((uint32_t)0x00100000)         /*!< TS reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR3_I2CSW                     ((uint32_t)0x00000030)        /*!< I2CSW bits */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 
+#define  RCC_CFGR3_I2C2SW                    ((uint32_t)0x00000020)        /*!< I2C2SW bits */
+#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */ 
+
+#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*             Sigma-Delta Analog to Digital Converter (SDADC)                */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SDADC_CR1 register  ********************/
+#define  SDADC_CR1_EOCALIE                       ((uint32_t)0x00000001)        /*!< End of calibration interrupt enable */
+#define  SDADC_CR1_JEOCIE                        ((uint32_t)0x00000002)        /*!< Injected end of conversion interrupt enable */
+#define  SDADC_CR1_JOVRIE                        ((uint32_t)0x00000004)        /*!< Injected data overrun interrupt enable */
+#define  SDADC_CR1_REOCIE                        ((uint32_t)0x00000008)        /*!< Regular end of conversion interrupt enable */
+#define  SDADC_CR1_ROVRIE                        ((uint32_t)0x00000010)        /*!< Regular data overrun interrupt enable */
+#define  SDADC_CR1_REFV                          ((uint32_t)0x00000300)        /*!< Reference voltage selection */
+#define  SDADC_CR1_REFV_0                        ((uint32_t)0x00000100)        /*!< Reference voltage selection bit 0 */
+#define  SDADC_CR1_REFV_1                        ((uint32_t)0x00000200)        /*!< Reference voltage selection bit 1 */
+#define  SDADC_CR1_SLOWCK                        ((uint32_t)0x00000400)        /*!< Slow clock mode enable */
+#define  SDADC_CR1_SBI                           ((uint32_t)0x00000800)        /*!< Enter standby mode when idle */
+#define  SDADC_CR1_PDI                           ((uint32_t)0x00001000)        /*!< Enter power down mode when idle */
+#define  SDADC_CR1_JSYNC                         ((uint32_t)0x00004000)        /*!< Launch a injected conversion synchronously with SDADC1 */
+#define  SDADC_CR1_RSYNC                         ((uint32_t)0x00008000)        /*!< Launch regular conversion synchronously with SDADC1 */
+#define  SDADC_CR1_JDMAEN                        ((uint32_t)0x00010000)        /*!< DMA channel enabled to read data for the injected channel group */
+#define  SDADC_CR1_RDMAEN                        ((uint32_t)0x00020000)        /*!< DMA channel enabled to read data for the regular channel */
+#define  SDADC_CR1_INIT                          ((uint32_t)0x80000000)        /*!< Initialization mode request */
+
+/*****************  Bit definition for SDADC_CR2 register  ********************/
+#define  SDADC_CR2_ADON                          ((uint32_t)0x00000001)        /*!< SDADC enable */
+#define  SDADC_CR2_CALIBCNT                      ((uint32_t)0x00000006)        /*!< Number of calibration sequences to be performed */
+#define  SDADC_CR2_CALIBCNT_0                    ((uint32_t)0x00000002)        /*!< Number of calibration sequences to be performed bit 0 */
+#define  SDADC_CR2_CALIBCNT_1                    ((uint32_t)0x00000004)        /*!< Number of calibration sequences to be performed bit 1 */
+#define  SDADC_CR2_STARTCALIB                    ((uint32_t)0x00000010)        /*!< Start calibration */
+#define  SDADC_CR2_JCONT                         ((uint32_t)0x00000020)        /*!< Continuous mode selection for injected conversions */
+#define  SDADC_CR2_JDS                           ((uint32_t)0x00000040)        /*!< Delay start of injected conversions */
+#define  SDADC_CR2_JEXTSEL                       ((uint32_t)0x00000F00)        /*!< Trigger signal selection for launching injected conversions */
+#define  SDADC_CR2_JEXTSEL_0                     ((uint32_t)0x00000100)        /*!< Trigger signal selection for launching injected conversions bit 0 */
+#define  SDADC_CR2_JEXTSEL_1                     ((uint32_t)0x00000200)        /*!< Trigger signal selection for launching injected conversions bit 1 */
+#define  SDADC_CR2_JEXTSEL_2                     ((uint32_t)0x00000400)        /*!< Trigger signal selection for launching injected conversions bit 2 */
+#define  SDADC_CR2_JEXTSEL_3                     ((uint32_t)0x00000800)        /*!< Trigger signal selection for launching injected conversions bit 3 */
+#define  SDADC_CR2_JEXTEN                        ((uint32_t)0x00006000)        /*!< Trigger enable and trigger edge selection for injected conversions */
+#define  SDADC_CR2_JEXTEN_0                      ((uint32_t)0x00002000)        /*!< Trigger enable and trigger edge selection for injected conversions bit 0 */
+#define  SDADC_CR2_JEXTEN_1                      ((uint32_t)0x00004000)        /*!< Trigger enable and trigger edge selection for injected conversions bit 1 */
+#define  SDADC_CR2_JSWSTART                      ((uint32_t)0x00008000)        /*!< Start a conversion of the injected group of channels */
+#define  SDADC_CR2_RCH                           ((uint32_t)0x000F0000)        /*!< Regular channel selection */
+#define  SDADC_CR2_RCH_0                         ((uint32_t)0x00010000)        /*!< Regular channel selection bit 0 */
+#define  SDADC_CR2_RCH_1                         ((uint32_t)0x00020000)        /*!< Regular channel selection bit 1 */
+#define  SDADC_CR2_RCH_2                         ((uint32_t)0x00040000)        /*!< Regular channel selection bit 2 */
+#define  SDADC_CR2_RCH_3                         ((uint32_t)0x00080000)        /*!< Regular channel selection bit 3 */
+#define  SDADC_CR2_RCONT                         ((uint32_t)0x00400000)        /*!< Continuous mode selection for regular conversions */
+#define  SDADC_CR2_RSWSTART                      ((uint32_t)0x00800000)        /*!< Software start of a conversion on the regular channel */
+#define  SDADC_CR2_FAST                          ((uint32_t)0x01000000)        /*!< Fast conversion mode selection */
+
+/********************  Bit definition for SDADC_ISR register  *****************/
+#define  SDADC_ISR_EOCALF                        ((uint32_t)0x00000001)        /*!< End of calibration flag */
+#define  SDADC_ISR_JEOCF                         ((uint32_t)0x00000002)        /*!< End of injected conversion flag */
+#define  SDADC_ISR_JOVRF                         ((uint32_t)0x00000004)        /*!< Injected conversion overrun flag */
+#define  SDADC_ISR_REOCF                         ((uint32_t)0x00000010)        /*!< End of regular conversion flag */
+#define  SDADC_ISR_ROVRF                         ((uint32_t)0x00000020)        /*!< Regular conversion overrun flag */
+#define  SDADC_ISR_CALIBIP                       ((uint32_t)0x00001000)        /*!< Calibration in progress status */
+#define  SDADC_ISR_JCIP                          ((uint32_t)0x00002000)        /*!< Injected conversion in progress status */
+#define  SDADC_ISR_RCIP                          ((uint32_t)0x00004000)        /*!< Regular conversion in progress status */
+#define  SDADC_ISR_STABIP                        ((uint32_t)0x00008000)        /*!< Stabilization in progress status */
+#define  SDADC_ISR_INITRDY                       ((uint32_t)0x80000000)        /*!< Initialization mode is ready */
+
+/******************  Bit definition for SDADC_CLRISR register  ****************/
+#define  SDADC_ISR_CLREOCALF                     ((uint32_t)0x00000001)       /*!< Clear the end of calibration flag */
+#define  SDADC_ISR_CLRJOVRF                      ((uint32_t)0x00000004)       /*!< Clear the injected conversion overrun flag */
+#define  SDADC_ISR_CLRROVRF                      ((uint32_t)0x00000010)       /*!< Clear the regular conversion overrun flag */
+
+/******************  Bit definition for SDADC_JCHGR register  *****************/
+#define  SDADC_JCHGR_JCHG                        ((uint32_t)0x000001FF)       /*!< Injected channel group selection */
+#define  SDADC_JCHGR_JCHG_0                      ((uint32_t)0x00000001)       /*!< Injected channel 0 selection */
+#define  SDADC_JCHGR_JCHG_1                      ((uint32_t)0x00000002)       /*!< Injected channel 1 selection */
+#define  SDADC_JCHGR_JCHG_2                      ((uint32_t)0x00000004)       /*!< Injected channel 2 selection */
+#define  SDADC_JCHGR_JCHG_3                      ((uint32_t)0x00000008)       /*!< Injected channel 3 selection */
+#define  SDADC_JCHGR_JCHG_4                      ((uint32_t)0x00000010)       /*!< Injected channel 4 selection */
+#define  SDADC_JCHGR_JCHG_5                      ((uint32_t)0x00000020)       /*!< Injected channel 5 selection */
+#define  SDADC_JCHGR_JCHG_6                      ((uint32_t)0x00000040)       /*!< Injected channel 6 selection */
+#define  SDADC_JCHGR_JCHG_7                      ((uint32_t)0x00000080)       /*!< Injected channel 7 selection */
+#define  SDADC_JCHGR_JCHG_8                      ((uint32_t)0x00000100)       /*!< Injected channel 8 selection */
+
+/******************  Bit definition for SDADC_CONF0R register  ****************/
+#define  SDADC_CONF0R_OFFSET0                    ((uint32_t)0x00000FFF)       /*!< 12-bit calibration offset for configuration 0 */
+#define  SDADC_CONF0R_GAIN0                      ((uint32_t)0x00700000)       /*!< Gain setting for configuration 0 */
+#define  SDADC_CONF0R_GAIN0_0                    ((uint32_t)0x00100000)       /*!< Gain setting for configuration 0 Bit 0*/
+#define  SDADC_CONF0R_GAIN0_1                    ((uint32_t)0x00200000)       /*!< Gain setting for configuration 0 Bit 1 */
+#define  SDADC_CONF0R_GAIN0_2                    ((uint32_t)0x00400000)       /*!< Gain setting for configuration 0 Bit 2 */
+#define  SDADC_CONF0R_SE0                        ((uint32_t)0x0C000000)       /*!< Single ended mode for configuration 0 */
+#define  SDADC_CONF0R_SE0_0                      ((uint32_t)0x04000000)       /*!< Single ended mode for configuration 0 Bit 0 */
+#define  SDADC_CONF0R_SE0_1                      ((uint32_t)0x08000000)       /*!< Single ended mode for configuration 0 Bit 1 */
+#define  SDADC_CONF0R_COMMON0                    ((uint32_t)0xC0000000)       /*!< Common mode for configuration 0 */
+#define  SDADC_CONF0R_COMMON0_0                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 0 Bit 0 */
+#define  SDADC_CONF0R_COMMON0_1                  ((uint32_t)0x80000000)       /*!< Common mode for configuration 0 Bit 1 */
+
+/******************  Bit definition for SDADC_CONF1R register  ****************/
+#define  SDADC_CONF1R_OFFSET1                    ((uint32_t)0x00000FFF)       /*!< 12-bit calibration offset for configuration 1 */
+#define  SDADC_CONF1R_GAIN1                      ((uint32_t)0x00700000)       /*!< Gain setting for configuration 1 */
+#define  SDADC_CONF1R_GAIN1_0                    ((uint32_t)0x00100000)       /*!< Gain setting for configuration 1 Bit 0 */
+#define  SDADC_CONF1R_GAIN1_1                    ((uint32_t)0x00200000)       /*!< Gain setting for configuration 1 Bit 1 */
+#define  SDADC_CONF1R_GAIN1_2                    ((uint32_t)0x00400000)       /*!< Gain setting for configuration 1 Bit 2 */
+#define  SDADC_CONF1R_SE1                        ((uint32_t)0x0C000000)       /*!< Single ended mode for configuration 1 */
+#define  SDADC_CONF1R_SE1_0                      ((uint32_t)0x04000000)       /*!< Single ended mode for configuration 1 Bit 0 */
+#define  SDADC_CONF1R_SE1_1                      ((uint32_t)0x08000000)       /*!< Single ended mode for configuration 1 Bit 1 */
+#define  SDADC_CONF1R_COMMON1                    ((uint32_t)0xC0000000)       /*!< Common mode for configuration 1 */
+#define  SDADC_CONF1R_COMMON1_0                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 1 Bit 0 */
+#define  SDADC_CONF1R_COMMON1_1                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 1 Bit 1 */
+
+/******************  Bit definition for SDADC_CONF2R register  ****************/
+#define  SDADC_CONF2R_OFFSET2                    ((uint32_t)0x00000FFF)       /*!< 12-bit calibration offset for configuration 2 */
+#define  SDADC_CONF2R_GAIN2                      ((uint32_t)0x00700000)       /*!< Gain setting for configuration 2 */
+#define  SDADC_CONF2R_GAIN2_0                    ((uint32_t)0x00100000)       /*!< Gain setting for configuration 2 Bit 0 */
+#define  SDADC_CONF2R_GAIN2_1                    ((uint32_t)0x00200000)       /*!< Gain setting for configuration 2 Bit 1 */
+#define  SDADC_CONF2R_GAIN2_2                    ((uint32_t)0x00400000)       /*!< Gain setting for configuration 2 Bit 2 */
+#define  SDADC_CONF2R_SE2                        ((uint32_t)0x0C000000)       /*!< Single ended mode for configuration 2 */
+#define  SDADC_CONF2R_SE2_0                      ((uint32_t)0x04000000)       /*!< Single ended mode for configuration 2 Bit 0 */
+#define  SDADC_CONF2R_SE2_1                      ((uint32_t)0x08000000)       /*!< Single ended mode for configuration 2 Bit 1 */
+#define  SDADC_CONF2R_COMMON2                    ((uint32_t)0xC0000000)       /*!< Common mode for configuration 2 */
+#define  SDADC_CONF2R_COMMON2_0                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 2 Bit 0 */
+#define  SDADC_CONF2R_COMMON2_1                  ((uint32_t)0x80000000)       /*!< Common mode for configuration 2 Bit 1 */
+
+/*****************  Bit definition for SDADC_CONFCHR1 register  ***************/
+#define  SDADC_CONFCHR1_CONFCH0                  ((uint32_t)0x00000003)      /*!< Channel 0 configuration */
+#define  SDADC_CONFCHR1_CONFCH1                  ((uint32_t)0x00000030)      /*!< Channel 1 configuration */
+#define  SDADC_CONFCHR1_CONFCH2                  ((uint32_t)0x00000300)      /*!< Channel 2 configuration */
+#define  SDADC_CONFCHR1_CONFCH3                  ((uint32_t)0x00003000)      /*!< Channel 3 configuration */
+#define  SDADC_CONFCHR1_CONFCH4                  ((uint32_t)0x00030000)      /*!< Channel 4 configuration */
+#define  SDADC_CONFCHR1_CONFCH5                  ((uint32_t)0x00300000)      /*!< Channel 5 configuration */
+#define  SDADC_CONFCHR1_CONFCH6                  ((uint32_t)0x03000000)      /*!< Channel 6 configuration */
+#define  SDADC_CONFCHR1_CONFCH7                  ((uint32_t)0x30000000)      /*!< Channel 7 configuration */
+
+/*****************  Bit definition for SDADC_CONFCHR2 register  ***************/
+#define  SDADC_CONFCHR2_CONFCH8                  ((uint32_t)0x00000003)      /*!< Channel 8 configuration */
+
+/*****************  Bit definition for SDADC_JDATAR register  ***************/
+#define  SDADC_JDATAR_JDATA                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data */
+#define  SDADC_JDATAR_JDATACH                    ((uint32_t)0x0F000000)      /*!< Injected channel most recently converted */
+#define  SDADC_JDATAR_JDATACH_0                  ((uint32_t)0x01000000)      /*!< Injected channel most recently converted bit 0 */
+#define  SDADC_JDATAR_JDATACH_1                  ((uint32_t)0x02000000)      /*!< Injected channel most recently converted bit 1 */
+#define  SDADC_JDATAR_JDATACH_2                  ((uint32_t)0x04000000)      /*!< Injected channel most recently converted bit 2 */
+#define  SDADC_JDATAR_JDATACH_3                  ((uint32_t)0x08000000)      /*!< Injected channel most recently converted bit 3 */
+
+/*****************  Bit definition for SDADC_RDATAR register  ***************/
+#define  SDADC_RDATAR_RDATA                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data */
+
+/*****************  Bit definition for SDADC_JDATA12R register  ***************/
+#define  SDADC_JDATA12R_JDATA2                      ((uint32_t)0xFFFF0000)      /*!< Injected group conversion data for SDADC2 */
+#define  SDADC_JDATA12R_JDATA1                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data for SDADC1 */
+
+/*****************  Bit definition for SDADC_RDATA12R register  ***************/
+#define  SDADC_RDATA12R_RDATA2                      ((uint32_t)0xFFFF0000)      /*!< Regular conversion data for SDADC2 */
+#define  SDADC_RDATA12R_RDATA1                      ((uint32_t)0x0000FFFF)      /*!< Regular conversion data for SDADC1 */
+
+/*****************  Bit definition for SDADC_JDATA13R register  ***************/
+#define  SDADC_JDATA13R_JDATA3                      ((uint32_t)0xFFFF0000)      /*!< Injected group conversion data for SDADC3 */
+#define  SDADC_JDATA13R_JDATA1                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data for SDADC1 */
+
+/*****************  Bit definition for SDADC_RDATA13R register  ***************/
+#define  SDADC_RDATA13R_RDATA3                      ((uint32_t)0xFFFF0000)      /*!< Regular conversion data for SDADC3 */
+#define  SDADC_RDATA13R_RDATA1                      ((uint32_t)0x0000FFFF)      /*!< Regular conversion data for SDADC1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        System Configuration(SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP    ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP    ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
+#define SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP   ((uint32_t)0x00008000) /*!< Timer 18 / DAC2 Ch1 DMA remap */
+#define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C2           ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_VBAT                   ((uint32_t)0x01000000) /*!< VBAT monitoring */
+#define SYSCFG_CFGR1_FPU_IE                 ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
+#define SYSCFG_CFGR1_FPU_IE_0               ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
+#define SYSCFG_CFGR1_FPU_IE_1               ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
+#define SYSCFG_CFGR1_FPU_IE_2               ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
+#define SYSCFG_CFGR1_FPU_IE_3               ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
+#define SYSCFG_CFGR1_FPU_IE_4               ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
+#define SYSCFG_CFGR1_FPU_IE_5               ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/** 
+  * @brief  EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/** 
+  * @brief  EXTI1 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/** 
+  * @brief  EXTI2 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/** 
+  * @brief  EXTI3 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/** 
+  * @brief  EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/** 
+  * @brief  EXTI5 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+
+/** 
+  * @brief  EXTI6 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/** 
+  * @brief  EXTI7 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/** 
+  * @brief  EXTI8 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/** 
+  * @brief  EXTI9 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/** 
+  * @brief  EXTI10 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/** 
+  * @brief  EXTI11 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/** 
+  * @brief  EXTI12 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/** 
+  * @brief  EXTI13 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/** 
+  * @brief  EXTI14 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/** 
+  * @brief  EXTI15 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PE                   ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x00C0)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                     ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                     ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                      ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                     ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                     ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                       ((uint32_t)0x00000004)            /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f37x_conf.h"
+#endif /* USE_STDPERIPH_DRIVER */
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F37x_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/stm32f4xx.h b/os/ext/CMSIS/ST/stm32f4xx.h
new file mode 100644
index 000000000..4de8a166e
--- /dev/null
+++ b/os/ext/CMSIS/ST/stm32f4xx.h
@@ -0,0 +1,9154 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V1.2.1
+  * @date    19-September-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F4xx devices.            
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral�s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral�s registers hardware
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx
+  * @{
+  */
+    
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx)
+  /* #define STM32F40_41xxx */   /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,  
+                                     STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, 
+                                     STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+
+  /* #define STM32F427_437xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,  
+                                       STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
+                                    
+  /* #define STM32F429_439xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,  
+                                       STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, 
+                                       STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
+                                       STM32F439IG and STM32F439II Devices */
+                                    
+  /* #define STM32F401xx */     /*!< STM32F401CB, STM32F401CC,  STM32F401RB,  STM32F401RC, STM32F401VB and STM32F401VC Devices */  
+  
+#endif
+
+/* Old STM32F40XX definition, maintained for legacy purpose */
+#ifdef STM32F40XX
+  #define STM32F40_41xxx
+#endif /* STM32F40XX */
+
+/* Old STM32F427X definition, maintained for legacy purpose */
+#ifdef STM32F427X
+  #define STM32F427_437xx
+#endif /* STM32F427X */
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx)
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+#if !defined  (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER */
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */           
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+  
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT) 
+  #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x05000)   /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */   
+
+#if !defined  (HSI_VALUE)   
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */   
+
+/**
+ * @brief STM32F4XX Standard Peripherals Library version number V1.2.0
+   */
+#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
+#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F4XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F4XX_STDPERIPH_VERSION_RC))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+ */
+#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1       /*!< STM32F4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+
+#if defined (STM32F40_41xxx)
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
+  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
+  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx)
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
+  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */   
+#endif /* STM32F427_437xx */
+    
+#if defined (STM32F429_439xx)
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
+  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */   
+#endif /* STM32F429_439xx */
+   
+#if defined (STM32F401xx)
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */  
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  FPU_IRQn                    = 81,      /*!< FPU global interrupt                                             */
+  SPI4_IRQn                   = 84       /*!< SPI4 global Interrupt                                            */
+#endif /* STM32F401xx */
+
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
+  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
+  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
+  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+ 
+/** 
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+#if defined (STM32F40_41xxx)
+/** 
+  * @brief Flexible Static Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FSMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FSMC_Bank2_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FSMC_Bank3_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef; 
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+/** 
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FMC_Bank2_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
+} FMC_Bank4_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank5_6
+  */
+  
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef; 
+#endif /* STM32F427_437xx ||  STM32F429_439xx */
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
+  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                   */
+  __IO uint16_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                   */
+  __IO uint16_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                   */
+  __IO uint16_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                   */
+  __IO uint16_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                   */
+  __IO uint16_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                   */
+  __IO uint16_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                   */
+  __IO uint16_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                   */
+  __IO uint16_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                   */
+  __IO uint16_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
+  uint16_t      RESERVED9;  /*!< Reserved, 0x26                                   */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/** 
+  * @brief LCD-TFT Display Controller
+  */
+  
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
+} LTDC_TypeDef;  
+
+/** 
+  * @brief LCD-TFT Display layer x Controller
+  */
+  
+typedef struct
+{  
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
+  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Serial Audio Interface
+  */
+  
+typedef struct
+{
+  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
+  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
+  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
+  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
+  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
+  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
+  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
+  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
+  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
+  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
+  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
+  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
+  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
+  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
+  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
+  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
+  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
+  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
+  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
+  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
+  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
+  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
+  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
+  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
+  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
+  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief Crypto Processor
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
+  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/** 
+  * @brief HASH
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/** 
+  * @brief HASH_DIGEST
+  */
+  
+typedef struct 
+{
+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
+} HASH_DIGEST_TypeDef;
+
+/** 
+  * @brief RNG
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
+#define SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
+
+#if defined (STM32F40_41xxx)
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#define FMC_R_BASE            ((uint32_t)0xA0000000) /*!< FMC registers base address                                                 */
+#endif /* STM32F427_437xx ||  STM32F429_439xx */
+
+#define CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region  */
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */
+#define SRAM2_BB_BASE         ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region                              */
+#define SRAM3_BB_BASE         ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region                              */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */
+#define BKPSRAM_BB_BASE       ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
+#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104) 
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
+#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
+#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
+#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+
+#if defined (STM32F40_41xxx)
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
+#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
+#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104)
+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080)
+#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140)
+#endif /* STM32F427_437xx ||  STM32F429_439xx */
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH                ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+#if defined (STM32F40_41xxx)
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
+#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#endif /* STM32F427_437xx ||  STM32F429_439xx */
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!<Analog watchdog flag               */
+#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!<End of conversion                  */
+#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!<Injected channel Start flag        */
+#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!<Regular channel Start flag         */
+#define  ADC_SR_OVR                          ((uint8_t)0x20)               /*!<Overrun flag                       */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC                              */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable                     */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels                */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode                                             */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode  */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion                   */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels                */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels               */
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count)  */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels           */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels            */
+#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution)                            */
+#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable                              */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF             */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion              */
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode          */
+#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection        */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment                     */
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Crypto Processor                                */
+/*                                                                            */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register  ********************/
+#define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004)
+
+#define CRYP_CR_ALGOMODE                     ((uint32_t)0x00080038)
+#define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018)
+#define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028)
+#define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030)
+#define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038)
+
+#define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0)
+#define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040)
+#define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080)
+#define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300)
+#define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100)
+#define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200)
+#define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000)
+#define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000)
+
+#define CRYP_CR_GCM_CCMPH                    ((uint32_t)0x00030000)
+#define CRYP_CR_GCM_CCMPH_0                  ((uint32_t)0x00010000)
+#define CRYP_CR_GCM_CCMPH_1                  ((uint32_t)0x00020000)
+#define CRYP_CR_ALGOMODE_3                   ((uint32_t)0x00080000) 
+
+/****************** Bits definition for CRYP_SR register  *********************/
+#define CRYP_SR_IFEM                         ((uint32_t)0x00000001)
+#define CRYP_SR_IFNF                         ((uint32_t)0x00000002)
+#define CRYP_SR_OFNE                         ((uint32_t)0x00000004)
+#define CRYP_SR_OFFU                         ((uint32_t)0x00000008)
+#define CRYP_SR_BUSY                         ((uint32_t)0x00000010)
+/****************** Bits definition for CRYP_DMACR register  ******************/
+#define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001)
+#define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002)
+/*****************  Bits definition for CRYP_IMSCR register  ******************/
+#define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001)
+#define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002)
+/****************** Bits definition for CRYP_RISR register  *******************/
+#define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001)
+#define CRYP_RISR_INRIS                      ((uint32_t)0x00000002)
+/****************** Bits definition for CRYP_MISR register  *******************/
+#define CRYP_MISR_INMIS                      ((uint32_t)0x00000001)
+#define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002)
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
+#define DCMI_CR_CM                           ((uint32_t)0x00000002)
+#define DCMI_CR_CROP                         ((uint32_t)0x00000004)
+#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
+#define DCMI_CR_ESS                          ((uint32_t)0x00000010)
+#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
+#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
+#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
+#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
+#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
+#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
+#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
+#define DCMI_CR_CRE                          ((uint32_t)0x00001000)
+#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
+#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
+#define DCMI_SR_FNE                          ((uint32_t)0x00000004)
+
+/********************  Bits definition for DCMI_RISR register  ****************/
+#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
+#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
+#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
+#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
+#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
+#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
+#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
+#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
+#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
+
+/********************  Bits definition for DCMI_MISR register  ****************/
+#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
+#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
+#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
+#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
+#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
+#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
+#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
+#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
+#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/ 
+#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
+#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
+#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
+#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
+#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
+#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
+#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
+#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
+#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
+#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
+#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
+#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
+#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
+#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
+#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
+#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
+#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
+#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
+#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
+#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
+#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START                     ((uint32_t)0x00000001)               /*!< Start transfer */
+#define DMA2D_CR_SUSP                      ((uint32_t)0x00000002)               /*!< Suspend transfer */
+#define DMA2D_CR_ABORT                     ((uint32_t)0x00000004)               /*!< Abort transfer */
+#define DMA2D_CR_TEIE                      ((uint32_t)0x00000100)               /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE                      ((uint32_t)0x00000200)               /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE                      ((uint32_t)0x00000400)               /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800)               /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000)               /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE                      ((uint32_t)0x00002000)               /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE                      ((uint32_t)0x00030000)               /*!< DMA2D Mode */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001)               /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002)               /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004)               /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008)               /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010)               /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020)               /*!< Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_IFSR register  ****************/
+
+#define DMA2D_IFSR_CTEIF                   ((uint32_t)0x00000001)               /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF                   ((uint32_t)0x00000002)               /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF                   ((uint32_t)0x00000004)               /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF                  ((uint32_t)0x00000008)               /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF                  ((uint32_t)0x00000010)               /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF                   ((uint32_t)0x00000020)               /*!< Clears Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
+#define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
+#define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha mode */
+#define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
+#define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */   
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
+#define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
+#define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha Mode */
+#define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
+#define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007)               /*!< Color mode */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FF)               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00)               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000)               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000)               /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0)               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800)               /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0)               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00)               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000)               /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000F)               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0)               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00)               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000)               /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFF)               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFF)               /*!< Number of Lines */
+#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000)               /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFF)               /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001)               /*!< Enable */
+#define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00)               /*!< Dead Time */
+
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+                                                                     
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008)
+#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009)
+#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000A)
+#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000B)
+#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000C)
+#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000D)
+#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000E)
+#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000F)
+
+#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
+#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
+#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG                          ((uint32_t)0x00000001)
+#define FLASH_CR_SER                         ((uint32_t)0x00000002)
+#define FLASH_CR_MER                         ((uint32_t)0x00000004)
+#define FLASH_CR_MER1                        FLASH_CR_MER
+#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4                       ((uint32_t)0x00000040)
+#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
+#define FLASH_CR_MER2                        ((uint32_t)0x00008000)
+#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
+#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010)
+
+#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
+
+#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000) 
+#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000) 
+                                             
+/******************  Bits definition for FLASH_OPTCR1 register  ***************/
+#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
+
+#if defined (STM32F40_41xxx)
+/******************************************************************************/
+/*                                                                            */
+/*                       Flexible Static Memory Controller                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FSMC_BCR1 register  *******************/
+#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
+#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
+#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
+#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
+#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
+#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
+#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
+#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
+
+/******************  Bit definition for FSMC_BCR2 register  *******************/
+#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                */
+#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
+#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
+#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
+#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
+#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
+#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
+#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
+#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
+
+/******************  Bit definition for FSMC_BCR3 register  *******************/
+#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
+#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
+#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
+#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
+#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
+#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
+#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
+#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
+
+/******************  Bit definition for FSMC_BCR4 register  *******************/
+#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
+#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
+#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
+#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
+#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
+#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
+#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
+#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
+#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
+#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
+#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
+
+/******************  Bit definition for FSMC_BTR1 register  ******************/
+#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BTR2 register  *******************/
+#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/*******************  Bit definition for FSMC_BTR3 register  *******************/
+#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BTR4 register  *******************/
+#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR1 register  ******************/
+#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR2 register  ******************/
+#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
+#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR3 register  ******************/
+#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR4 register  ******************/
+#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_PCR2 register  *******************/
+#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
+#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
+
+#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
+
+#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */
+#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/******************  Bit definition for FSMC_PCR3 register  *******************/
+#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
+#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
+
+#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
+
+#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/******************  Bit definition for FSMC_PCR4 register  *******************/
+#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
+#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
+
+#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
+
+#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/*******************  Bit definition for FSMC_SR2 register  *******************/
+#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
+#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
+#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
+#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
+#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
+
+/*******************  Bit definition for FSMC_SR3 register  *******************/
+#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
+#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
+#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
+#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
+#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
+
+/*******************  Bit definition for FSMC_SR4 register  *******************/
+#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                 */
+#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                       */
+#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status                */
+#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit   */
+#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit         */
+#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit  */
+#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
+
+/******************  Bit definition for FSMC_PMEM2 register  ******************/
+#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM3 register  ******************/
+#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM4 register  ******************/
+#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PATT2 register  ******************/
+#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PATT3 register  ******************/
+#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PATT4 register  ******************/
+#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PIO4 register  *******************/
+#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_ECCR2 register  ******************/
+#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+
+/******************  Bit definition for FSMC_ECCR3 register  ******************/
+#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000)        /*!<Continous clock enable     */
+
+/******************  Bit definition for FMC_BCR2 register  *******************/
+#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR3 register  *******************/
+#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR4 register  *******************/
+#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTR1 register  ******************/
+#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR2 register  *******************/
+#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/*******************  Bit definition for FMC_BTR3 register  *******************/
+#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR4 register  *******************/
+#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR1 register  ******************/
+#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR2 register  ******************/
+#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
+#define  FMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR3 register  ******************/
+#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR4 register  ******************/
+#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_PCR2 register  *******************/
+#define  FMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
+#define  FMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
+
+#define  FMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
+
+#define  FMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size)           */
+#define  FMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_PCR3 register  *******************/
+#define  FMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
+#define  FMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
+
+#define  FMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
+
+#define  FMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_PCR4 register  *******************/
+#define  FMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
+#define  FMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
+
+#define  FMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
+
+#define  FMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/*******************  Bit definition for FMC_SR2 register  *******************/
+#define  FMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
+#define  FMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
+
+/*******************  Bit definition for FMC_SR3 register  *******************/
+#define  FMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
+#define  FMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
+
+/*******************  Bit definition for FMC_SR4 register  *******************/
+#define  FMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
+#define  FMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM2 register  ******************/
+#define  FMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PMEM3 register  ******************/
+#define  FMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PMEM4 register  ******************/
+#define  FMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PATT2 register  ******************/
+#define  FMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PATT3 register  ******************/
+#define  FMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PATT4 register  ******************/
+#define  FMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PIO4 register  *******************/
+#define  FMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_ECCR2 register  ******************/
+#define  FMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define  FMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCR1 register  ******************/
+#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
+
+#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
+
+#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
+
+#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
+
+#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000)        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDCR2 register  ******************/
+#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
+
+#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
+
+#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
+
+#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
+
+#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000)        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDTR1 register  ******************/
+#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
+                                            
+#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+
+#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
+
+#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
+
+#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDTR2 register  ******************/
+#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
+                                            
+#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+
+#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
+
+#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
+
+#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007)        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000003)        /*!<Bit 2 */
+                                            
+#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008)        /*!<Command target 2 */
+
+#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010)        /*!<Command target 1 */
+
+#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100)        /*!<Bit 3 */
+
+#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00)        /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001)        /*!<Clear refresh error flag */
+
+#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFE)        /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000)        /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define  FMC_SDSR_RE                        ((uint32_t)0x00000001)        /*!<Refresh error flag */
+
+#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002)        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004)        /*!<Bit 1 */
+
+#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010)        /*!<Bit 1 */
+
+#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020)        /*!<Busy status */
+
+#endif /* STM32F427_437xx ||  STM32F429_439xx */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    HASH                                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for HASH_CR register  ********************/
+#define HASH_CR_INIT                         ((uint32_t)0x00000004)
+#define HASH_CR_DMAE                         ((uint32_t)0x00000008)
+#define HASH_CR_DATATYPE                     ((uint32_t)0x00000030)
+#define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010)
+#define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020)
+#define HASH_CR_MODE                         ((uint32_t)0x00000040)
+#define HASH_CR_ALGO                         ((uint32_t)0x00040080)
+#define HASH_CR_ALGO_0                       ((uint32_t)0x00000080)
+#define HASH_CR_ALGO_1                       ((uint32_t)0x00040000)
+#define HASH_CR_NBW                          ((uint32_t)0x00000F00)
+#define HASH_CR_NBW_0                        ((uint32_t)0x00000100)
+#define HASH_CR_NBW_1                        ((uint32_t)0x00000200)
+#define HASH_CR_NBW_2                        ((uint32_t)0x00000400)
+#define HASH_CR_NBW_3                        ((uint32_t)0x00000800)
+#define HASH_CR_DINNE                        ((uint32_t)0x00001000)
+#define HASH_CR_MDMAT                        ((uint32_t)0x00002000)
+#define HASH_CR_LKEY                         ((uint32_t)0x00010000)
+
+/******************  Bits definition for HASH_STR register  *******************/
+#define HASH_STR_NBW                         ((uint32_t)0x0000001F)
+#define HASH_STR_NBW_0                       ((uint32_t)0x00000001)
+#define HASH_STR_NBW_1                       ((uint32_t)0x00000002)
+#define HASH_STR_NBW_2                       ((uint32_t)0x00000004)
+#define HASH_STR_NBW_3                       ((uint32_t)0x00000008)
+#define HASH_STR_NBW_4                       ((uint32_t)0x00000010)
+#define HASH_STR_DCAL                        ((uint32_t)0x00000100)
+
+/******************  Bits definition for HASH_IMR register  *******************/
+#define HASH_IMR_DINIM                       ((uint32_t)0x00000001)
+#define HASH_IMR_DCIM                        ((uint32_t)0x00000002)
+
+/******************  Bits definition for HASH_SR register  ********************/
+#define HASH_SR_DINIS                        ((uint32_t)0x00000001)
+#define HASH_SR_DCIS                         ((uint32_t)0x00000002)
+#define HASH_SR_DMAS                         ((uint32_t)0x00000004)
+#define HASH_SR_BUSY                         ((uint32_t)0x00000008)
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!<Clock Stretching Disable (Slave mode)         */
+#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!<Software Reset                                */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+
+#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!<DMA Last Transfer       */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!<Interface Address */
+
+#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!<Bit 9 */
+
+#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!<Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!<Interface address           */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!<8-bit Data Register         */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!<Start Bit (Master mode)                         */
+#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!<10-bit header sent (Master mode)                */
+#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!<Stop detection (Slave mode)                     */
+#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!<Data Register not Empty (receivers)             */
+#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!<Data Register Empty (transmitters)              */
+#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!<Arbitration Lost (master mode)                  */
+#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!<SMBus Alert                                     */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!<General Call Address (Slave mode)         */
+#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!<SMBus Host Header (Slave mode)            */
+#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!<Dual Flag (Slave mode)                    */
+#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!<Packet Error Checking Register            */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!<I2C Master Mode Selection                                  */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************  Bit definition for I2C_FLTR register  *******************/
+#define  I2C_FLTR_DNF                     ((uint8_t)0x0F)                  /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                   ((uint8_t)0x10)                  /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH                       ((uint32_t)0x000007FF)              /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000)              /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FF)              /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000)              /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH                       ((uint32_t)0x000007FF)              /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000)              /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FF)              /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000)              /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001)              /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW                        ((uint32_t)0x00000070)              /*!< Dither Blue Width */
+#define LTDC_GCR_DGW                        ((uint32_t)0x00000700)              /*!< Dither Green Width */
+#define LTDC_GCR_DRW                        ((uint32_t)0x00007000)              /*!< Dither Red Width */
+#define LTDC_GCR_DTEN                       ((uint32_t)0x00010000)              /*!< Dither Enable */
+#define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000)              /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000)              /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000)              /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000)              /*!< Horizontal Synchronization Polarity */
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR                      ((uint32_t)0x00000001)               /*!< Immediate Reload */
+#define LTDC_SRCR_VBR                      ((uint32_t)0x00000002)               /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FF)              /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00)              /*!< Background Green value */
+#define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000)              /*!< Background Red value */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE                        ((uint32_t)0x00000001)              /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF                        ((uint32_t)0x00000001)              /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF                       ((uint32_t)0x00000001)              /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002)              /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004)              /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008)              /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FF)              /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFF)              /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000)              /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES                      ((uint32_t)0x00000001)              /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES                      ((uint32_t)0x00000002)              /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004)              /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008)              /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN                       ((uint32_t)0x00000001)              /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002)              /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010)              /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Horizontal Stop Position */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Vertical Stop Position */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FF)              /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00)              /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000)              /*!< Color Key Red value */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007)              /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FF)              /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FF)              /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00)              /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000)              /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000)              /*!< Default Color Alpha */
+                                
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007)              /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700)              /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFF)              /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFF)              /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000)              /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FF)              /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FF)              /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00)              /*!< Green value */
+#define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
+
+#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPUDS                        ((uint32_t)0x00000400)     /*!< Low-Power Regulator in Stop under-drive mode               */
+#define  PWR_CR_MRUDS                        ((uint32_t)0x00000800)     /*!< Main regulator in Stop under-drive mode                    */
+
+#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit */ 
+
+#define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
+
+#define  PWR_CR_ODEN                         ((uint32_t)0x00010000)     /*!< Over Drive enable                   */
+#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000)     /*!< Over Drive switch enabled           */
+#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000)     /*!< Under Drive enable in stop mode     */
+#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000)     /*!< Bit 0                               */
+#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000)     /*!< Bit 1                               */
+
+/* Legacy define */
+#define  PWR_CR_PMODE                        PWR_CR_VOS
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000)     /*!< Over Drive generator ready                       */
+#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000)     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000)     /*!< Under Drive ready                                */
+
+/* Legacy define */
+#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
+#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
+#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
+#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
+#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
+#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000)
+#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000)
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
+#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
+#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
+#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
+#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
+#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
+#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
+
+#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
+#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
+#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
+#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
+#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
+#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
+#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
+#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
+#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
+#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
+
+#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
+#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
+#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
+
+#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
+#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
+#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
+
+#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
+#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
+#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
+#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
+#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
+#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
+#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
+#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
+#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
+#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
+#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
+#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
+
+#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
+
+#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
+#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
+#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
+#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
+
+#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
+#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
+#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
+#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
+
+#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
+#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
+#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
+#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
+#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040)
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
+#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
+#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000)
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
+#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
+#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000)
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
+#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
+#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
+#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
+#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
+#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
+#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
+#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
+#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
+#define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200)
+#define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400)
+#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
+#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
+#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
+#define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000)
+#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
+/* CHIBIOS FIX */
+/*#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x10000000)*/
+#define  RCC_AHB1RSTR_OTGHSRST                ((uint32_t)0x10000000)
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
+#define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010)
+#define  RCC_AHB2RSTR_HASHRST                ((uint32_t)0x00000020)
+ /* maintained for legacy purpose */
+ #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
+#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
+#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#if defined(STM32F40_41xxx)
+#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001)
+#endif /* STM32F427_437xx ||  STM32F429_439xx */
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
+#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
+#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
+#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
+#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
+#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
+#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
+#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
+#define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000)
+#define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
+#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
+#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
+#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
+#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
+#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
+#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
+#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
+#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)
+#define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000)
+#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000)
+#define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000)
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
+#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
+#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
+#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
+#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
+#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
+#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
+#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
+#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
+#define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200)
+#define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400)
+#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
+#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
+#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)
+#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
+#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
+#define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000)
+#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
+#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
+#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
+#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
+#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
+#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
+#define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010)
+#define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020)
+#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
+#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+
+#if defined(STM32F40_41xxx)
+#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001)
+#endif /* STM32F427_437xx ||  STM32F429_439xx */
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
+#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
+#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
+#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
+#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
+#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
+#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
+#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
+#define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000)
+#define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
+#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
+#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
+#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
+#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
+#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
+#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
+#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
+#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
+#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
+#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
+#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000)
+#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000)
+#define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000)
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
+#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
+#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
+#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
+#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
+#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
+#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
+#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
+#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
+#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200)
+#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400)
+#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
+#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
+#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
+#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
+#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000)
+#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
+#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
+#define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000)
+#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
+#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
+#define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010)
+#define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020)
+#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
+#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+#if defined(STM32F40_41xxx)
+#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001)
+#endif /* STM32F427_437xx ||  STM32F429_439xx */
+
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
+#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
+#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
+#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
+#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
+#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
+#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
+#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
+#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
+#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
+#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
+#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
+#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
+#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
+#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
+#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
+#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
+#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
+#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
+#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
+#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
+#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
+#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
+#define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000)
+#define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
+#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
+#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
+#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
+#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
+#define  RCC_APB2LPENR_ADC2PEN               ((uint32_t)0x00000200)
+#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
+#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
+#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
+#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)
+#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
+#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
+#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
+#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
+#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)
+#define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000)
+#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000)
+#define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000)
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
+
+#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
+#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
+#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
+#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
+#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
+#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
+#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
+#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
+#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
+#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
+
+/********************  Bit definition for RCC_PLLSAICFGR register  ************/
+#define  RCC_PLLSAICFGR_PLLI2SN              ((uint32_t)0x00007FC0)
+#define  RCC_PLLSAICFGR_PLLI2SQ              ((uint32_t)0x0F000000)
+#define  RCC_PLLSAICFGR_PLLI2SR              ((uint32_t)0x70000000)
+
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001F)
+#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00)
+#define  RCC_DCKCFGR_PLLSAIDIVR              ((uint32_t)0x00030000)
+#define  RCC_DCKCFGR_SAI1ASRC                ((uint32_t)0x00300000)
+#define  RCC_DCKCFGR_SAI1BSRC                ((uint32_t)0x00C00000)
+#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000)
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
+#define RNG_CR_IE                            ((uint32_t)0x00000008)
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
+#define RNG_SR_CECS                          ((uint32_t)0x00000002)
+#define RNG_SR_SECS                          ((uint32_t)0x00000004)
+#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
+#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003)        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000C)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0)        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080)        /*!<Bit 2 */
+
+#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100)        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200)        /*!<ClocK STRobing edge      */
+
+#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00)        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800)        /*!<Bit 1 */
+
+#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000)        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000)        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000)        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000)        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000)        /*!<No Divider Configuration   */
+
+#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00780000)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00080000)        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00100000)        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00200000)        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00400000)        /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define  SAI_xCR2_FTH                     ((uint32_t)0x00000003)        /*!<FTH[1:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+
+#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008)        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010)        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020)        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040)        /*!<Muate value                      */
+
+#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80)       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080)        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100)        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200)        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400)        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */
+
+#define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */
+
+#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000)        /*!<Bit 1 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FF)        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00)        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000)        /*!<Bit 6 */
+
+#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000)        /*!< Frame Synchronization Definition */
+#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000)        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000)        /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001F)        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010)        /*!<Bit 4 */
+                                     
+#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0)        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080)        /*!<Bit 1 */
+
+#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000)        /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001)        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002)        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004)        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008)        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010)        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020)        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040)        /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001)         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002)         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004)         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008)         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010)         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020)         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040)         /*!<Late frame synchronization detection           */
+
+#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000)         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000)         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00030000)         /*!<Bit 2 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001)        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002)        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004)        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008)        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010)        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020)        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040)        /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFF)        
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!<Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!<Clock divider bypass enable bit */
+
+#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!<Bit 1 */
+
+#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!<Command Index                               */
+
+#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!< Bit 1 */
+
+#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!<CE-ATA command       */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!<Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!<DMA enabled bit                   */
+
+#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!<Master Selection */
+
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!<Bit 2 */
+
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!<SS Output Enable                     */
+#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!<Tx buffer Empty Interrupt Enable     */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!<Channel side             */
+#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!<Mode fault               */
+#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!<Busy flag                */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!<Tx CRC Register         */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity               */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization                 */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
+#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!<Bit 0 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!<Bit 1 */
+#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define SYSCFG_MEMRMP_FB_MODE           ((uint32_t)0x00000100) /*!< User Flash Bank mode */
+
+#define SYSCFG_MEMRMP_SWP_FMC           ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_SWP_FMC_0         ((uint32_t)0x00000400) /*!<Bit 0 */
+#define SYSCFG_MEMRMP_SWP_FMC_1         ((uint32_t)0x00000800) /*!<Bit 1 */
+
+
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit  */
+
+#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!<EXTI 3 configuration */
+/** 
+  * @brief   EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0006) /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0007) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint16_t)0x0008) /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint16_t)0x0009) /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint16_t)0x000A) /*!<PK[0] pin */
+
+/** 
+  * @brief   EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0060) /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0070) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint16_t)0x0080) /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint16_t)0x0090) /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint16_t)0x00A0) /*!<PK[1] pin */
+
+/** 
+  * @brief   EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0600) /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0700) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint16_t)0x0800) /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint16_t)0x0900) /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint16_t)0x0A00) /*!<PK[2] pin */
+
+/** 
+  * @brief   EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x6000) /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint16_t)0x7000) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint16_t)0x8000) /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint16_t)0x9000) /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint16_t)0xA000) /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!<EXTI 7 configuration */
+/** 
+  * @brief   EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0006) /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint16_t)0x0007) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint16_t)0x0008) /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint16_t)0x0009) /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint16_t)0x000A) /*!<PK[4] pin */
+
+/** 
+  * @brief   EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0060) /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint16_t)0x0070) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint16_t)0x0080) /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint16_t)0x0090) /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint16_t)0x00A0) /*!<PK[5] pin */
+
+/** 
+  * @brief   EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0600) /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint16_t)0x0700) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint16_t)0x0800) /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint16_t)0x0900) /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint16_t)0x0A00) /*!<PK[6] pin */
+
+/** 
+  * @brief   EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x6000) /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint16_t)0x7000) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint16_t)0x8000) /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint16_t)0x9000) /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint16_t)0xA000) /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!<EXTI 11 configuration */
+           
+/** 
+  * @brief   EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0006) /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint16_t)0x0007) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint16_t)0x0008) /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint16_t)0x0009) /*!<PJ[8] pin */
+
+/** 
+  * @brief   EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0060) /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint16_t)0x0070) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint16_t)0x0080) /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint16_t)0x0090) /*!<PJ[9] pin */
+
+/** 
+  * @brief   EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0600) /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint16_t)0x0700) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint16_t)0x0800) /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint16_t)0x0900) /*!<PJ[10] pin */
+
+/** 
+  * @brief   EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x6000) /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint16_t)0x7000) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint16_t)0x8000) /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint16_t)0x9000) /*!<PJ[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!<EXTI 15 configuration */
+/** 
+  * @brief   EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0006) /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint16_t)0x0007) /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint16_t)0x0008) /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint16_t)0x0009) /*!<PJ[12] pin */
+
+/** 
+  * @brief   EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0060) /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint16_t)0x0070) /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint16_t)0x0008) /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint16_t)0x0009) /*!<PJ[13] pin */
+
+/** 
+  * @brief   EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0600) /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint16_t)0x0700) /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint16_t)0x0800) /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint16_t)0x0900) /*!<PJ[14] pin */
+
+/** 
+  * @brief   EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x6000) /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint16_t)0x7000) /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint16_t)0x8000) /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint16_t)0x9000) /*!<PJ[15] pin */
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
+#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable        */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction             */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable     */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection            */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode                       */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable           */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation                          */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable              */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable              */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable        */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value            */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value          */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable                */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses                    */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_TI4_RMP                       ((uint16_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      ((uint16_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for USART_SR register  *******************/
+#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!<Parity Error                 */
+#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!<Framing Error                */
+#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!<CTS Flag                     */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!<Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!<Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!<Send Break                             */
+#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!<Wakeup method                          */
+#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!<Word length                            */
+#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!<USART Oversampling by 8 enable         */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!<Clock Enable                         */
+
+#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!<LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!<USART One bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!<Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
+#define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
+#define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
+#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
+#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
+#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
+#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
+#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
+#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
+#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
+#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
+#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
+#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
+#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
+#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
+#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
+#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
+  
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
+#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
+#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
+#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset */
+#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
+#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
+#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
+#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
+#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
+#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
+#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
+#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
+#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
+#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
+#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
+#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
+#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
+#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+
+/**
+  *
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f4xx_conf.h"
+#endif /* USE_STDPERIPH_DRIVER */
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/stm32l1xx.h b/os/ext/CMSIS/ST/stm32l1xx.h
new file mode 100644
index 000000000..62fed8a16
--- /dev/null
+++ b/os/ext/CMSIS/ST/stm32l1xx.h
@@ -0,0 +1,6358 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx.h
+  * @author  MCD Application Team
+  * @version V1.2.0
+  * @date    22-February-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32L1xx High-density, Medium-density
+  *          and Medium-density Plus devices.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral�s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral�s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx
+  * @{
+  */
+    
+#ifndef __STM32L1XX_H
+#define __STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32L device used in your 
+   application 
+  */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+
+/*  #define STM32L1XX_MD */   /*!< - Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx,
+                                     STM32L151xBxx, STM32L152x6xx, STM32L152x8xx and STM32L152xBxx. 
+                                   - Ultra Low Power Medium-density Value Line devices: STM32L100x6xx,
+                                     STM32L100x8xx and STM32L100xBxx.  */
+
+/* #define STM32L1XX_MDP */   /*!< - Ultra Low Power Medium-density Plus devices: STM32L151xCxx, STM32L152xCxx and STM32L162xCxx 
+                                   - Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx  */
+
+/* #define STM32L1XX_HD */    /*!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx */
+#endif
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
+#endif
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#endif
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
+   Timeout value 
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#endif
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE  ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  ((uint32_t)37000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif
+
+/**
+ * @brief STM32L1xx Standard Peripheral Library version number V1.2.0
+   */
+#define __STM32L1XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L1XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32L1XX_STDPERIPH_VERSION       ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32L1XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+#define __CM3_REV                 0x200 /*!< Cortex-M3 Revision r2p0                      */
+#define __MPU_PRESENT             1     /*!< STM32L1 provides MPU                         */
+#define __NVIC_PRIO_BITS          4     /*!< STM32L1 uses 4 Bits for the Priority Levels  */
+#define __Vendor_SysTickConfig    0     /*!< Set to 1 if different SysTick Config is used */
+ 
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
+  /* CHIBIOS FIX */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
+/*  SVC_IRQn                    = -5,*/     /*!< 11 Cortex-M3 SV Call Interrupt                          */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
+
+/******  STM32L specific Interrupt Numbers ***********************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
+  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and Time Stamp through EXTI Line Interrupts      */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
+  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
+  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
+  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
+  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
+  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
+  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
+  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
+  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
+  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
+  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
+#ifdef STM32L1XX_MD
+  TIM7_IRQn                   = 44      /*!< TIM7 global Interrupt                                   */
+#endif /* STM32L1XX_MD */
+
+#ifdef STM32L1XX_MDP
+  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
+  /* CHIBIOS FIX */
+  TIM5_IRQn                   = 45,     /*!< TIM5 global Interrupt                                   */
+  SPI3_IRQn                   = 46,     /*!< SPI3 global Interrupt                                   */
+  DMA2_Channel1_IRQn          = 47,     /*!< DMA2 Channel 1 global Interrupt                         */
+  DMA2_Channel2_IRQn          = 48,     /*!< DMA2 Channel 2 global Interrupt                         */
+  DMA2_Channel3_IRQn          = 49,     /*!< DMA2 Channel 3 global Interrupt                         */
+  DMA2_Channel4_IRQn          = 50,     /*!< DMA2 Channel 4 global Interrupt                         */
+  DMA2_Channel5_IRQn          = 51,     /*!< DMA2 Channel 5 global Interrupt                         */
+  AES_IRQn                    = 52,     /*!< AES global Interrupt                                    */
+  COMP_ACQ_IRQn               = 53      /*!< Comparator Channel Acquisition global Interrupt         */
+#endif /* STM32L1XX_MDP */
+
+#ifdef STM32L1XX_HD
+  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
+  SDIO_IRQn                   = 45,     /*!< SDIO global Interrupt                                   */
+  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
+  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
+  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
+  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
+  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
+  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
+  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
+  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
+  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
+  AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
+  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
+#endif /* STM32L1XX_HD */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm3.h"
+#include "system_stm32l1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/** 
+  * @brief  __RAM_FUNC definition
+  */ 
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options. 
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog. 
+*/
+ #define __RAM_FUNC FLASH_Status 
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
+*/
+ #define __RAM_FUNC __ramfunc FLASH_Status
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+   RAM functions are defined using a specific toolchain attribute 
+   "__attribute__((section(".data")))". 
+*/
+ #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
+
+#elif defined   (  __TASKING__  )
+/* TASKING Compiler
+   ----------------
+   RAM functions are defined using a specific toolchain pragma. This pragma is 
+   defined in the stm32l1xx_flash_ramfunc.c 
+*/
+ #define __RAM_FUNC  FLASH_Status
+
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
+  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
+  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
+  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
+  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
+  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
+  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
+  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
+  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
+  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
+  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
+  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
+  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
+  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
+  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
+  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
+  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief AES hardware accelerator
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
+  __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
+  __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
+  __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
+  __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
+  __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
+  __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
+  __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
+  __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
+  __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
+  __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
+  __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
+} AES_TypeDef;
+
+/** 
+  * @brief Comparator 
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< COMP comparator control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/** 
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t   RESERVED0;        /*!< Reserved,                                    0x05                 */
+  uint16_t  RESERVED1;        /*!< Reserved,                                    0x06                 */
+  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
+  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
+  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
+  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
+  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
+  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
+  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
+  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
+  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
+  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
+  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
+  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
+  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} DMA_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!< EXTI interrupt mask register,                 Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!< EXTI event mask register,                     Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!< EXTI rising edge trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!< EXTI software interrupt event register,       Address offset: 0x10 */
+  __IO uint32_t PR;           /*!< EXTI pending register,                        Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
+  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
+  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
+  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
+  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
+  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
+  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
+  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
+  __IO uint32_t WRPR;         /*!< Write protection register,                   Address offset: 0x20 */
+  uint32_t   RESERVED[23];    /*!< Reserved,                                    0x24                 */
+  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x28 */
+  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x2C */
+} FLASH_TypeDef;
+
+/** 
+  * @brief Option Bytes Registers
+  */
+  
+typedef struct
+{
+  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
+  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
+  __IO uint32_t WRP01;             /*!< write protection register 0 1,          Address offset: 0x08 */
+  __IO uint32_t WRP23;             /*!< write protection register 2 3,          Address offset: 0x0C */
+  __IO uint32_t WRP45;             /*!< write protection register 4 5,          Address offset: 0x10 */
+  __IO uint32_t WRP67;             /*!< write protection register 6 7,          Address offset: 0x14 */
+  __IO uint32_t WRP89;             /*!< write protection register 8 9,          Address offset: 0x18 */
+  __IO uint32_t WRP1011;           /*!< write protection register 10 11,        Address offset: 0x1C */
+} OB_TypeDef;
+
+/** 
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
+  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];      /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];      /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;        
+
+/** 
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
+  uint16_t RESERVED0;         /*!< Reserved,                                    0x06                      */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
+  uint16_t RESERVED1;         /*!< Reserved,                                    0x12                      */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
+  uint16_t RESERVED2;         /*!< Reserved,                                    0x16                      */
+  __IO uint16_t BSRRL;        /*!< GPIO port bit set/reset low registerBSRR,    Address offset: 0x18      */
+  __IO uint16_t BSRRH;        /*!< GPIO port bit set/reset high registerBSRR,   Address offset: 0x1A      */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,        Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
+  uint16_t RESERVED3;         /*!< Reserved,                                    0x2A                      */
+} GPIO_TypeDef;
+
+/** 
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
+  uint16_t  RESERVED0;        /*!< Reserved,                                    0x02                 */
+  __IO uint16_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
+  uint16_t  RESERVED1;        /*!< Reserved,                                    0x06                 */
+  __IO uint16_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
+  uint16_t  RESERVED2;        /*!< Reserved,                                    0x0A                 */
+  __IO uint16_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
+  uint16_t  RESERVED3;        /*!< Reserved,                                    0x0E                 */
+  __IO uint16_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
+  uint16_t  RESERVED4;        /*!< Reserved,                                    0x12                 */
+  __IO uint16_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
+  uint16_t  RESERVED5;        /*!< Reserved,                                    0x16                 */
+  __IO uint16_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
+  uint16_t  RESERVED6;        /*!< Reserved,                                    0x1A                 */
+  __IO uint16_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
+  uint16_t  RESERVED7;        /*!< Reserved,                                    0x1E                 */
+  __IO uint16_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
+  uint16_t  RESERVED8;        /*!< Reserved,                                    0x22                 */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
+  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
+  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
+  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/** 
+  * @brief LCD
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
+  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
+  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
+  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
+  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
+  __IO uint32_t RAM[16];   /*!< LCD display memory,           Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
+  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
+  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
+  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
+  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
+  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
+} RCC_TypeDef;
+
+/** 
+  * @brief Routing Interface 
+  */
+
+typedef struct
+{
+  __IO uint32_t ICR;       /*!< RI input capture register,             Address offset: 0x00 */
+  __IO uint32_t ASCR1;     /*!< RI analog switches control register,   Address offset: 0x04 */
+  __IO uint32_t ASCR2;     /*!< RI analog switch control register 2,   Address offset: 0x08 */
+  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,       Address offset: 0x0C */
+  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,       Address offset: 0x10 */
+  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,       Address offset: 0x14 */
+  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,       Address offset: 0x18 */
+} RI_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
+  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
+  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
+  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
+  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
+  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
+  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
+  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
+  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
+  uint16_t      RESERVED0;    /*!< Reserved, 0x02                                            */
+  __IO uint16_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
+  uint16_t      RESERVED1;    /*!< Reserved, 0x06                                            */
+  __IO uint16_t SMCR;         /*!< TIM slave mode control register,     Address offset: 0x08 */
+  uint16_t      RESERVED2;    /*!< Reserved, 0x0A                                            */
+  __IO uint16_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  uint16_t      RESERVED3;    /*!< Reserved, 0x0E                                            */
+  __IO uint16_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
+  uint16_t      RESERVED4;    /*!< Reserved, 0x12                                            */
+  __IO uint16_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
+  uint16_t      RESERVED5;    /*!< Reserved, 0x16                                            */
+  __IO uint16_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  uint16_t      RESERVED6;    /*!< Reserved, 0x1A                                            */
+  __IO uint16_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  uint16_t      RESERVED7;    /*!< Reserved, 0x1E                                            */
+  __IO uint16_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  uint16_t      RESERVED8;    /*!< Reserved, 0x22                                            */
+  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint16_t PSC;          /*!< TIM prescaler,                       Address offset: 0x28 */
+  uint16_t      RESERVED10;   /*!< Reserved, 0x2A                                            */
+  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
+  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */
+  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */
+  __IO uint16_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
+  uint16_t      RESERVED18;   /*!< Reserved, 0x4A                                            */
+  __IO uint16_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  uint16_t      RESERVED19;   /*!< Reserved, 0x4E                                            */
+  __IO uint16_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
+  uint16_t      RESERVED20;   /*!< Reserved, 0x52                                            */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
+  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
+  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
+  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
+  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
+  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
+  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define LCD_BASE              (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define COMP_BASE             (APB1PERIPH_BASE + 0x7C00)
+#define RI_BASE               (APB1PERIPH_BASE + 0x7C04)
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7C5C)
+
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x0800)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x1000)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2700)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+
+#define GPIOA_BASE            (AHBPERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHBPERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHBPERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHBPERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHBPERIPH_BASE + 0x1000)
+#define GPIOH_BASE            (AHBPERIPH_BASE + 0x1400)
+#define GPIOF_BASE            (AHBPERIPH_BASE + 0x1800)
+#define GPIOG_BASE            (AHBPERIPH_BASE + 0x1C00)
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x3800)
+
+
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FF80000)    /*!< FLASH Option Bytes base address */
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x6000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080)
+
+#define DMA2_BASE             (AHBPERIPH_BASE + 0x6400)
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001C)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058)
+
+#define AES_BASE              ((uint32_t)0x50060000)
+
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+
+#define DBGMCU_BASE           ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define LCD                 ((LCD_TypeDef *) LCD_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define RI                  ((RI_TypeDef *) RI_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE) 
+
+#define AES                 ((AES_TypeDef *) AES_BASE)
+
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!< Analog watchdog flag */
+#define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!< End of conversion */
+#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!< Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!< Injected channel Start flag */
+#define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!< Regular channel Start flag */
+#define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!< Overrun flag */
+#define  ADC_SR_ADONS                        ((uint32_t)0x00000040)        /*!< ADC ON status */
+#define  ADC_SR_RCNR                         ((uint32_t)0x00000100)        /*!< Regular channel not ready flag */
+#define  ADC_SR_JCNR                         ((uint32_t)0x00000200)        /*!< Injected channel not ready flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
+
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  ADC_CR1_PDD                         ((uint32_t)0x00010000)        /*!< Power Down during Delay phase */
+#define  ADC_CR1_PDI                         ((uint32_t)0x00020000)        /*!< Power Down during Idle phase */
+
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
+
+#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)        /*!< Overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
+#define  ADC_CR2_CFG                         ((uint32_t)0x00000004)        /*!< ADC Configuration */
+
+#define  ADC_CR2_DELS                        ((uint32_t)0x00000070)        /*!< DELS[2:0] bits (Delay selection) */
+#define  ADC_CR2_DELS_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  ADC_CR2_DELS_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  ADC_CR2_DELS_2                      ((uint32_t)0x00000040)        /*!< Bit 2 */
+
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
+#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!< DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!< End of conversion selection */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
+
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!< JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
+#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!< Start Conversion of injected channels */
+
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!< Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP20                     ((uint32_t)0x00000007)        /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
+#define  ADC_SMPR1_SMP20_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP20_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP20_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP21                     ((uint32_t)0x00000038)        /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
+#define  ADC_SMPR1_SMP21_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP21_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP21_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP22                     ((uint32_t)0x000001C0)        /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
+#define  ADC_SMPR1_SMP22_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP22_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP22_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP23                     ((uint32_t)0x00000E00)        /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
+#define  ADC_SMPR1_SMP23_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP23_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP23_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP24                     ((uint32_t)0x00007000)        /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
+#define  ADC_SMPR1_SMP24_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP24_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP24_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP25                     ((uint32_t)0x00038000)        /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
+#define  ADC_SMPR1_SMP25_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP25_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP25_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP26                     ((uint32_t)0x001C0000)        /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
+#define  ADC_SMPR1_SMP26_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP26_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP26_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP27                     ((uint32_t)0x00E00000)        /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
+#define  ADC_SMPR1_SMP27_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP27_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP27_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP28                     ((uint32_t)0x07000000)        /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
+#define  ADC_SMPR1_SMP28_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP28_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP28_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP29                     ((uint32_t)0x38000000)        /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
+#define  ADC_SMPR1_SMP29_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP29_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP29_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR2_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR2_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR2_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR2_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR2_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR2_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR2_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP18                     ((uint32_t)0x07000000)        /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR2_SMP18_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP18_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP18_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP19                     ((uint32_t)0x38000000)        /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
+#define  ADC_SMPR2_SMP19_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP19_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP19_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPR3 register  *******************/
+#define  ADC_SMPR3_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR3_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+ 
+#define  ADC_SMPR3_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR3_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR3_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR3_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR3_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR3_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR3_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR3_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR3_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR3_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)         /*!< Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  ADC_SQR1_SQ28                       ((uint32_t)0x000F8000)        /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
+#define  ADC_SQR1_SQ28_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ28_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ28_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ28_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ28_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ27                       ((uint32_t)0x00007C00)        /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
+#define  ADC_SQR1_SQ27_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ27_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ27_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ27_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ27_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ26                       ((uint32_t)0x000003E0)        /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
+#define  ADC_SQR1_SQ26_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ26_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ26_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ26_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ26_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ25                       ((uint32_t)0x0000001F)        /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
+#define  ADC_SQR1_SQ25_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ25_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ25_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ25_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ25_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ19                       ((uint32_t)0x0000001F)        /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
+#define  ADC_SQR2_SQ19_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ19_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ19_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ19_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ19_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ20                       ((uint32_t)0x000003E0)        /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
+#define  ADC_SQR2_SQ20_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ20_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ20_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ20_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ20_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ21                       ((uint32_t)0x00007C00)        /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
+#define  ADC_SQR2_SQ21_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ21_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ21_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ21_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ21_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ22                       ((uint32_t)0x000F8000)        /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
+#define  ADC_SQR2_SQ22_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ22_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ22_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ22_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ22_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ23                       ((uint32_t)0x01F00000)        /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
+#define  ADC_SQR2_SQ23_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ23_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ23_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ23_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ23_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ24                       ((uint32_t)0x3E000000)        /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
+#define  ADC_SQR2_SQ24_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ24_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ24_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ24_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ24_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR3_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR3_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR3_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR3_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ17                       ((uint32_t)0x01F00000)        /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
+#define  ADC_SQR3_SQ17_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ17_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ17_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ17_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ17_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ18                       ((uint32_t)0x3E000000)        /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
+#define  ADC_SQR3_SQ18_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ18_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ18_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ18_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ18_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR4 register  *******************/
+#define  ADC_SQR4_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR4_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR4_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR4_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ10                        ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR4_SQ10_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ10_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ10_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ10_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ10_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ11                        ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR4_SQ11_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ11_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ11_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ11_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ11_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ12                        ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR4_SQ12_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ12_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ12_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ12_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ12_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR5 register  *******************/
+#define  ADC_SQR5_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR5_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR5_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR5_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR5_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR5_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR5_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/******************  Bit definition for ADC_SMPR0 register  *******************/
+#define  ADC_SMPR3_SMP30                     ((uint32_t)0x00000007)        /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
+#define  ADC_SMPR3_SMP30_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP30_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP30_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
+ 
+#define  ADC_SMPR3_SMP31                     ((uint32_t)0x00000038)        /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
+#define  ADC_SMPR3_SMP31_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP31_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP31_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!< ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!< ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!< ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!< ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!< ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020)        /*!< ADC1 overrun  flag */
+#define  ADC_CSR_ADONS1                      ((uint32_t)0x00000040)        /*!< ADON status of ADC1 */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!< ADC prescaler*/
+#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */ 
+#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Advanced Encryption Standard (AES)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for AES_CR register  *********************/
+#define  AES_CR_EN                           ((uint32_t)0x00000001)        /*!< AES Enable */
+#define  AES_CR_DATATYPE                     ((uint32_t)0x00000006)        /*!< Data type selection */
+#define  AES_CR_DATATYPE_0                   ((uint32_t)0x00000002)        /*!< Bit 0 */
+#define  AES_CR_DATATYPE_1                   ((uint32_t)0x00000004)        /*!< Bit 1 */
+
+#define  AES_CR_MODE                         ((uint32_t)0x00000018)        /*!< AES Mode Of Operation */
+#define  AES_CR_MODE_0                       ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  AES_CR_MODE_1                       ((uint32_t)0x00000010)        /*!< Bit 1 */
+
+#define  AES_CR_CHMOD                        ((uint32_t)0x00000060)        /*!< AES Chaining Mode */
+#define  AES_CR_CHMOD_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  AES_CR_CHMOD_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+
+#define  AES_CR_CCFC                         ((uint32_t)0x00000080)        /*!< Computation Complete Flag Clear */
+#define  AES_CR_ERRC                         ((uint32_t)0x00000100)        /*!< Error Clear */
+#define  AES_CR_CCIE                         ((uint32_t)0x00000200)        /*!< Computation Complete Interrupt Enable */
+#define  AES_CR_ERRIE                        ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  AES_CR_DMAINEN                      ((uint32_t)0x00000800)        /*!< DMA ENable managing the data input phase */
+#define  AES_CR_DMAOUTEN                     ((uint32_t)0x00001000)        /*!< DMA Enable managing the data output phase */
+
+/*******************  Bit definition for AES_SR register  *********************/
+#define  AES_SR_CCF                          ((uint32_t)0x00000001)        /*!< Computation Complete Flag */
+#define  AES_SR_RDERR                        ((uint32_t)0x00000002)        /*!< Read Error Flag */
+#define  AES_SR_WRERR                        ((uint32_t)0x00000004)        /*!< Write Error Flag */
+
+/*******************  Bit definition for AES_DINR register  *******************/
+#define  AES_DINR                            ((uint32_t)0x0000FFFF)        /*!< AES Data Input Register */
+
+/*******************  Bit definition for AES_DOUTR register  ******************/
+#define  AES_DOUTR                           ((uint32_t)0x0000FFFF)        /*!< AES Data Output Register */
+
+/*******************  Bit definition for AES_KEYR0 register  ******************/
+#define  AES_KEYR0                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 0 */
+
+/*******************  Bit definition for AES_KEYR1 register  ******************/
+#define  AES_KEYR1                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 1 */
+
+/*******************  Bit definition for AES_KEYR2 register  ******************/
+#define  AES_KEYR2                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 2 */
+
+/*******************  Bit definition for AES_KEYR3 register  ******************/
+#define  AES_KEYR3                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 3 */
+
+/*******************  Bit definition for AES_IVR0 register  *******************/
+#define  AES_IVR0                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 0 */
+
+/*******************  Bit definition for AES_IVR1 register  *******************/
+#define  AES_IVR1                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 1 */
+
+/*******************  Bit definition for AES_IVR2 register  *******************/
+#define  AES_IVR2                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 2 */
+
+/*******************  Bit definition for AES_IVR3 register  *******************/
+#define  AES_IVR3                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for COMP_CSR register  ********************/
+#define  COMP_CSR_10KPU                      ((uint32_t)0x00000001)        /*!< 10K pull-up resistor */
+#define  COMP_CSR_400KPU                     ((uint32_t)0x00000002)        /*!< 400K pull-up resistor */
+#define  COMP_CSR_10KPD                      ((uint32_t)0x00000004)        /*!< 10K pull-down resistor */
+#define  COMP_CSR_400KPD                     ((uint32_t)0x00000008)        /*!< 400K pull-down resistor */
+
+#define  COMP_CSR_CMP1EN                     ((uint32_t)0x00000010)        /*!< Comparator 1 enable */
+#define  COMP_CSR_SW1                        ((uint32_t)0x00000020)        /*!< SW1 analog switch enable */
+#define  COMP_CSR_CMP1OUT                    ((uint32_t)0x00000080)        /*!< Comparator 1 output */
+
+#define  COMP_CSR_SPEED                      ((uint32_t)0x00001000)        /*!< Comparator 2 speed */
+#define  COMP_CSR_CMP2OUT                    ((uint32_t)0x00002000)        /*!< Comparator 2 ouput */
+
+#define  COMP_CSR_VREFOUTEN                  ((uint32_t)0x00010000)        /*!< Comparator Vref Enable */
+#define  COMP_CSR_WNDWE                      ((uint32_t)0x00020000)        /*!< Window mode enable */
+
+#define  COMP_CSR_INSEL                      ((uint32_t)0x001C0000)        /*!< INSEL[2:0] Inversion input Selection */
+#define  COMP_CSR_INSEL_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  COMP_CSR_INSEL_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  COMP_CSR_INSEL_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  COMP_CSR_OUTSEL                     ((uint32_t)0x00E00000)        /*!< OUTSEL[2:0] comparator 2 output redirection */
+#define  COMP_CSR_OUTSEL_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  COMP_CSR_OUTSEL_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  COMP_CSR_OUTSEL_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  COMP_CSR_FCH3                       ((uint32_t)0x04000000)        /*!< Bit 26 */
+#define  COMP_CSR_FCH8                       ((uint32_t)0x08000000)        /*!< Bit 27 */
+#define  COMP_CSR_RCH13                      ((uint32_t)0x10000000)        /*!< Bit 28 */
+
+#define  COMP_CSR_CAIE                       ((uint32_t)0x20000000)        /*!< Bit 29 */
+#define  COMP_CSR_CAIF                       ((uint32_t)0x40000000)        /*!< Bit 30 */
+#define  COMP_CSR_TSUSP                      ((uint32_t)0x80000000)        /*!< Bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for OPAMP_CSR register  ******************/
+#define OPAMP_CSR_OPA1PD                     ((uint32_t)0x00000001)        /*!< OPAMP1 disable */
+#define OPAMP_CSR_S3SEL1                     ((uint32_t)0x00000002)        /*!< Switch 3 for OPAMP1 Enable */
+#define OPAMP_CSR_S4SEL1                     ((uint32_t)0x00000004)        /*!< Switch 4 for OPAMP1 Enable */
+#define OPAMP_CSR_S5SEL1                     ((uint32_t)0x00000008)        /*!< Switch 5 for OPAMP1 Enable */
+#define OPAMP_CSR_S6SEL1                     ((uint32_t)0x00000010)        /*!< Switch 6 for OPAMP1 Enable */
+#define OPAMP_CSR_OPA1CAL_L                  ((uint32_t)0x00000020)        /*!< OPAMP1 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA1CAL_H                  ((uint32_t)0x00000040)        /*!< OPAMP1 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA1LPM                    ((uint32_t)0x00000080)        /*!< OPAMP1 Low power enable */
+#define OPAMP_CSR_OPA2PD                     ((uint32_t)0x00000100)        /*!< OPAMP2 disable */
+#define OPAMP_CSR_S3SEL2                     ((uint32_t)0x00000200)        /*!< Switch 3 for OPAMP2 Enable */
+#define OPAMP_CSR_S4SEL2                     ((uint32_t)0x00000400)        /*!< Switch 4 for OPAMP2 Enable */
+#define OPAMP_CSR_S5SEL2                     ((uint32_t)0x00000800)        /*!< Switch 5 for OPAMP2 Enable */
+#define OPAMP_CSR_S6SEL2                     ((uint32_t)0x00001000)        /*!< Switch 6 for OPAMP2 Enable */
+#define OPAMP_CSR_OPA2CAL_L                  ((uint32_t)0x00002000)        /*!< OPAMP2 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA2CAL_H                  ((uint32_t)0x00004000)        /*!< OPAMP2 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA2LPM                    ((uint32_t)0x00008000)        /*!< OPAMP2 Low power enable */
+#define OPAMP_CSR_OPA3PD                     ((uint32_t)0x00010000)        /*!< OPAMP3 disable */
+#define OPAMP_CSR_S3SEL3                     ((uint32_t)0x00020000)        /*!< Switch 3 for OPAMP3 Enable */
+#define OPAMP_CSR_S4SEL3                     ((uint32_t)0x00040000)        /*!< Switch 4 for OPAMP3 Enable */
+#define OPAMP_CSR_S5SEL3                     ((uint32_t)0x00080000)        /*!< Switch 5 for OPAMP3 Enable */
+#define OPAMP_CSR_S6SEL3                     ((uint32_t)0x00100000)        /*!< Switch 6 for OPAMP3 Enable */
+#define OPAMP_CSR_OPA3CAL_L                  ((uint32_t)0x00200000)        /*!< OPAMP3 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA3CAL_H                  ((uint32_t)0x00400000)        /*!< OPAMP3 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA3LPM                    ((uint32_t)0x00800000)        /*!< OPAMP3 Low power enable */
+#define OPAMP_CSR_ANAWSEL1                   ((uint32_t)0x01000000)        /*!< Switch ANA Enable for OPAMP1 */ 
+#define OPAMP_CSR_ANAWSEL2                   ((uint32_t)0x02000000)        /*!< Switch ANA Enable for OPAMP2 */
+#define OPAMP_CSR_ANAWSEL3                   ((uint32_t)0x04000000)        /*!< Switch ANA Enable for OPAMP3 */
+#define OPAMP_CSR_S7SEL2                     ((uint32_t)0x08000000)        /*!< Switch 7 for OPAMP2 Enable */
+#define OPAMP_CSR_AOP_RANGE                  ((uint32_t)0x10000000)        /*!< Power range selection */
+#define OPAMP_CSR_OPA1CALOUT                 ((uint32_t)0x20000000)        /*!< OPAMP1 calibration output */
+#define OPAMP_CSR_OPA2CALOUT                 ((uint32_t)0x40000000)        /*!< OPAMP2 calibration output */
+#define OPAMP_CSR_OPA3CALOUT                 ((uint32_t)0x80000000)        /*!< OPAMP3 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM        ((uint32_t)0x000003FF)        /*!< Offset trim for OPAMP1 */
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM        ((uint32_t)0x000FFC00)        /*!< Offset trim for OPAMP2 */
+#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM        ((uint32_t)0x3FF00000)        /*!< Offset trim for OPAMP2 */
+#define OPAMP_OTR_OT_USER                    ((uint32_t)0x80000000)        /*!< Switch to OPAMP offset user trimmed values */
+
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/
+#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP  ((uint32_t)0x000003FF)        /*!< Offset trim in low power for OPAMP1 */
+#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP  ((uint32_t)0x000FFC00)        /*!< Offset trim in low power for OPAMP2 */
+#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP  ((uint32_t)0x3FF00000)        /*!< Offset trim in low power for OPAMP3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF)        /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)               /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    Digital to Analog Converter (DAC)                       */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun interrupt enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun interrupt enable */
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP             ((uint32_t)0x00000001)   /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP             ((uint32_t)0x00000002)   /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP             ((uint32_t)0x00000004)   /*!< TIM4 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP             ((uint32_t)0x00000008)   /*!< TIM5 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP             ((uint32_t)0x00000010)   /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP             ((uint32_t)0x00000020)   /*!< TIM7 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP              ((uint32_t)0x00000400)   /*!< RTC Counter stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP             ((uint32_t)0x00000800)   /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP             ((uint32_t)0x00001000)   /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< SMBUS timeout mode stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)   /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP             ((uint32_t)0x00000004)   /*!< TIM9 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP            ((uint32_t)0x00000008)   /*!< TIM10 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP            ((uint32_t)0x00000010)   /*!< TIM11 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clearr */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR1 register  *******************/
+#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
+#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
+#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR2 register  *******************/
+#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< ransfer complete interrupt enable */
+#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR3 register  *******************/
+#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*!<******************  Bit definition for DMA_CCR4 register  *******************/
+#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/******************  Bit definition for DMA_CCR5 register  *******************/
+#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CCR6 register  *******************/
+#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR7 register  *******************/
+#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR7_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNDTR1 register  ******************/
+#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR2 register  ******************/
+#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR3 register  ******************/
+#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR4 register  ******************/
+#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR5 register  ******************/
+#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR6 register  ******************/
+#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR7 register  ******************/
+#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CPAR1 register  *******************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR2 register  *******************/
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR3 register  *******************/
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR4 register  *******************/
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR5 register  *******************/
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR6 register  *******************/
+#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR7 register  *******************/
+#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CMAR1 register  *******************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR2 register  *******************/
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR3 register  *******************/
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+
+/******************  Bit definition for DMA_CMAR4 register  *******************/
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR5 register  *******************/
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR6 register  *******************/
+#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR7 register  *******************/
+#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                  External Interrupt/Event Controller (EXTI)                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
+#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit 23 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                FLASH, DATA EEPROM and Option Bytes Registers               */
+/*                        (FLASH, DATA_EEPROM, OB)                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< Latency */
+#define  FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_ACC64                     ((uint32_t)0x00000004)        /*!< Access 64 bits */
+#define  FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */
+#define  FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */
+
+/*******************  Bit definition for FLASH_PECR register  ******************/
+#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */
+#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */
+#define FLASH_PECR_FTDW                      ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */
+#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_PARALLBANK                ((uint32_t)0x00008000)        /*!< Parallel Bank mode */
+#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */ 
+#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */ 
+#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */ 
+
+/******************  Bit definition for FLASH_PDKEYR register  ******************/
+#define  FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
+
+/******************  Bit definition for FLASH_PEKEYR register  ******************/
+#define  FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
+
+/******************  Bit definition for FLASH_PRGKEYR register  ******************/
+#define  FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */
+
+/******************  Bit definition for FLASH_OPTKEYR register  ******************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/
+#define  FLASH_SR_ENHV                       ((uint32_t)0x00000004)        /*!< End of high voltage */
+#define  FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */
+
+#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protected error */
+#define  FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */
+#define  FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */
+#define  FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option validity error */
+#define  FLASH_SR_OPTVERRUSR                 ((uint32_t)0x00001000)        /*!< Option User validity error */
+#define  FLASH_SR_RDERR                      ((uint32_t)0x00002000)        /*!< Read protected error */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_RDPRT                     ((uint32_t)0x000000AA)        /*!< Read Protection */
+#define  FLASH_OBR_SPRMOD                    ((uint32_t)0x00000100)        /*!< Selection of protection mode of WPRi bits 
+                                                                                (available only in STM32L1xx Medium-density Plus devices) */
+#define  FLASH_OBR_BOR_LEV                   ((uint32_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00100000)        /*!< IWDG_SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00200000)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00400000)        /*!< nRST_STDBY */
+#define  FLASH_OBR_BFB2                      ((uint32_t)0x00800000)        /*!< BFB2(available only in STM32L1xx High-density devices) */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protection bits */
+
+/******************  Bit definition for FLASH_WRPR1 register  *****************/
+#define  FLASH_WRPR1_WRP                     ((uint32_t)0xFFFFFFFF)        /*!< Write Protection bits (available only in STM32L1xx
+                                                                                Medium-density Plus and High-density devices) */
+
+/******************  Bit definition for FLASH_WRPR2 register  *****************/
+#define  FLASH_WRPR2_WRP                     ((uint32_t)0xFFFFFFFF)        /*!< Write Protection bits (available only in STM32L1xx
+                                                                                High-density devices) */
+/******************************************************************************/
+/*                                                                            */
+/*                       Flexible Static Memory Controller                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FSMC_BCR1 register  *******************/
+#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR2 register  *******************/
+#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR3 register  *******************/
+#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
+#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR4 register  *******************/
+#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BTR1 register  ******************/
+#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR2 register  *******************/
+#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for FSMC_BTR3 register  *******************/
+#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR4 register  *******************/
+#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR1 register  ******************/
+#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR2 register  ******************/
+#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
+#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR3 register  ******************/
+#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR4 register  ******************/
+#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      General Purpose IOs (GPIO)                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/  
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_OTYPER register  ****************/   
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/*******************  Bit definition for GPIO_OSPEEDR register  ***************/  
+#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_PUPDR register  *****************/  
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
+
+/*******************  Bit definition for GPIO_BSRR register  ******************/  
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_LCKR register  ******************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/*******************  Bit definition for GPIO_AFRL register  ******************/
+#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
+
+/*******************  Bit definition for GPIO_AFRH register  ******************/
+#define GPIO_AFRH_AFRH8            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH9            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH10           ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH11           ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH12           ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH13           ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH14           ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH15           ((uint32_t)0xF0000000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
+#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
+#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
+#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
+#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
+#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
+#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
+#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
+#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
+#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
+#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
+#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
+#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
+
+#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
+#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
+#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
+#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
+#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
+
+#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
+#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
+#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
+
+#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
+#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
+#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
+#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
+#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
+#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
+#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
+#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
+#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
+#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
+#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
+#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
+#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
+#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
+#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
+#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
+#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
+#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
+#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
+#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          LCD Controller (LCD)                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for LCD_CR register  *********************/
+#define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */
+#define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */
+#define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */
+#define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */
+
+#define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */
+#define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */
+
+#define LCD_CR_MUX_SEG             ((uint32_t)0x00000080)     /*!< Mux Segment Enable Bit */
+
+/*******************  Bit definition for LCD_FCR register  ********************/
+#define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */
+#define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */
+#define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */
+
+#define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */
+#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */
+#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */
+
+#define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */
+#define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */
+#define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */
+
+#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */
+#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */
+#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */
+
+#define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */
+#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */
+
+#define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */
+
+/*******************  Bit definition for LCD_SR register  *********************/
+#define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */
+#define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */
+#define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */
+
+/*******************  Bit definition for LCD_CLR register  ********************/
+#define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */
+
+/*******************  Bit definition for LCD_RAM register  ********************/
+#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+#define  PWR_CR_ULP                          ((uint16_t)0x0200)     /*!< Ultra Low Power mode */
+#define  PWR_CR_FWU                          ((uint16_t)0x0400)     /*!< Fast wakeup */
+
+#define  PWR_CR_VOS                          ((uint16_t)0x1800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define  PWR_CR_VOS_0                        ((uint16_t)0x0800)     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        ((uint16_t)0x1000)     /*!< Bit 1 */
+#define  PWR_CR_LPRUN                        ((uint16_t)0x4000)     /*!< Low power run mode */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
+#define  PWR_CSR_VOSF                        ((uint16_t)0x0010)     /*!< Voltage Scaling select flag */
+#define  PWR_CSR_REGLPF                      ((uint16_t)0x0020)     /*!< Regulator LP flag */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Reset and Clock Control (RCC)                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+
+#define  RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */
+#define  RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */
+
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+#define  RCC_CR_CSSON                        ((uint32_t)0x10000000)        /*!< Clock Security System enable */
+
+#define  RCC_CR_RTCPRE                       ((uint32_t)0x60000000)        /*!< RTC/LCD Prescaler */
+#define  RCC_CR_RTCPRE_0                     ((uint32_t)0x20000000)        /*!< Bit0 */
+#define  RCC_CR_RTCPRE_1                     ((uint32_t)0x40000000)        /*!< Bit1 */
+
+/********************  Bit definition for RCC_ICSCR register  *****************/
+#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */
+#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */
+
+#define  RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */
+#define  RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */
+#define  RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */
+#define  RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */
+#define  RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */
+#define  RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */
+#define  RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */
+#define  RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */
+#define  RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */
+#define  RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+/*!< SW configuration */
+#define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+/*!< PLL entry clock source*/
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */
+
+
+#define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */
+#define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */
+#define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */
+#define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */
+#define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */
+#define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */
+#define  RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */
+#define  RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */
+#define  RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define  RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define  RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */
+#define  RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */
+
+
+/*!< PLLDIV configuration */
+#define  RCC_CFGR_PLLDIV1                    ((uint32_t)0x00000000)        /*!< PLL clock output = CKVCO / 1 */
+#define  RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */
+#define  RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */
+#define  RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */
+
+
+#define  RCC_CFGR_MCOSEL                     ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+/*!< MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */
+#define  RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */
+
+#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000)        /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
+#define  RCC_CFGR_MCOPRE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCOPRE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCOPRE_2                   ((uint32_t)0x40000000)        /*!< Bit 2 */
+
+/*!< MCO Prescaler configuration */
+#define  RCC_CFGR_MCO_DIV1                   ((uint32_t)0x00000000)        /*!< MCO Clock divided by 1 */
+#define  RCC_CFGR_MCO_DIV2                   ((uint32_t)0x10000000)        /*!< MCO Clock divided by 2 */
+#define  RCC_CFGR_MCO_DIV4                   ((uint32_t)0x20000000)        /*!< MCO Clock divided by 4 */
+#define  RCC_CFGR_MCO_DIV8                   ((uint32_t)0x30000000)        /*!< MCO Clock divided by 8 */
+#define  RCC_CFGR_MCO_DIV16                  ((uint32_t)0x40000000)        /*!< MCO Clock divided by 16 */
+
+/*!<******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_MSIRDYF                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */
+#define  RCC_CIR_LSECSS                      ((uint32_t)0x00000040)        /*!< LSE CSS Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_MSIRDYIE                    ((uint32_t)0x00002000)        /*!< MSI Ready Interrupt Enable */
+#define  RCC_CIR_LSECSSIE                    ((uint32_t)0x00004000)        /*!< LSE CSS Interrupt Enable */
+
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_MSIRDYC                     ((uint32_t)0x00200000)        /*!< MSI Ready Interrupt Clear */
+#define  RCC_CIR_LSECSSC                     ((uint32_t)0x00400000)        /*!< LSE CSS Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+
+/*****************  Bit definition for RCC_AHBRSTR register  ******************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */
+#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00000010)        /*!< GPIO port E reset */
+#define  RCC_AHBRSTR_GPIOHRST                ((uint32_t)0x00000020)        /*!< GPIO port H reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00000040)        /*!< GPIO port F reset */
+#define  RCC_AHBRSTR_GPIOGRST                ((uint32_t)0x00000080)        /*!< GPIO port G reset */
+#define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */
+#define  RCC_AHBRSTR_FLITFRST                ((uint32_t)0x00008000)        /*!< FLITF reset */
+#define  RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x01000000)        /*!< DMA1 reset */
+#define  RCC_AHBRSTR_DMA2RST                 ((uint32_t)0x02000000)        /*!< DMA2 reset */
+#define  RCC_AHBRSTR_AESRST                  ((uint32_t)0x08000000)        /*!< AES reset */
+#define  RCC_AHBRSTR_FSMCRST                 ((uint32_t)0x40000000)        /*!< FSMC reset */
+ 
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< System Configuration SYSCFG reset */
+#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00000004)        /*!< TIM9 reset */
+#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00000008)        /*!< TIM10 reset */
+#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00000010)        /*!< TIM11 reset */
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
+#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)        /*!< SDIO reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
+#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+#define  RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI 2 reset */
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
+#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
+#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
+#define  RCC_APB1RSTR_COMPRST                ((uint32_t)0x80000000)        /*!< Comparator interface reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */
+#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00000010)        /*!< GPIO port E clock enable */
+#define  RCC_AHBENR_GPIOHEN                  ((uint32_t)0x00000020)        /*!< GPIO port H clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00000040)        /*!< GPIO port F clock enable */
+#define  RCC_AHBENR_GPIOGEN                  ((uint32_t)0x00000080)        /*!< GPIO port G clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00008000)        /*!< FLITF clock enable (has effect only when
+                                                                                the Flash memory is in power down mode) */
+#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x01000000)        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x02000000)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_AESEN                    ((uint32_t)0x08000000)        /*!< AES clock enable */
+#define  RCC_AHBENR_FSMCEN                   ((uint32_t)0x40000000)        /*!< FSMC clock enable */
+
+
+/******************  Bit definition for RCC_APB2ENR register  *****************/
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enable */
+#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00000004)         /*!< TIM9 interface clock enable */
+#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00000008)         /*!< TIM10 interface clock enable */
+#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enable */
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)         /*!< SDIO clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
+
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
+#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
+#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+#define  RCC_APB1ENR_COMPEN                  ((uint32_t)0x80000000)        /*!< Comparator interface clock enable */
+
+/******************  Bit definition for RCC_AHBLPENR register  ****************/
+#define  RCC_AHBLPENR_GPIOALPEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOBLPEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOCLPEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIODLPEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOELPEN              ((uint32_t)0x00000010)        /*!< GPIO port E clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOHLPEN              ((uint32_t)0x00000020)        /*!< GPIO port H clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOFLPEN              ((uint32_t)0x00000040)        /*!< GPIO port F clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOGLPEN              ((uint32_t)0x00000080)        /*!< GPIO port G clock enabled in sleep mode */
+#define  RCC_AHBLPENR_CRCLPEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */
+#define  RCC_AHBLPENR_FLITFLPEN              ((uint32_t)0x00008000)        /*!< Flash Interface clock enabled in sleep mode
+                                                                                (has effect only when the Flash memory is
+                                                                                 in power down mode) */
+#define  RCC_AHBLPENR_SRAMLPEN               ((uint32_t)0x00010000)        /*!< SRAM clock enabled in sleep mode */
+#define  RCC_AHBLPENR_DMA1LPEN               ((uint32_t)0x01000000)        /*!< DMA1 clock enabled in sleep mode */
+#define  RCC_AHBLPENR_DMA2LPEN               ((uint32_t)0x02000000)        /*!< DMA2 clock enabled in sleep mode */
+#define  RCC_AHBLPENR_AESLPEN                ((uint32_t)0x08000000)        /*!< AES clock enabled in sleep mode */
+#define  RCC_AHBLPENR_FSMCLPEN               ((uint32_t)0x40000000)        /*!< FSMC clock enabled in sleep mode */
+
+/******************  Bit definition for RCC_APB2LPENR register  ***************/
+#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enabled in sleep mode */
+#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00000004)         /*!< TIM9 interface clock enabled in sleep mode */
+#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00000008)         /*!< TIM10 interface clock enabled in sleep mode */
+#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enabled in sleep mode */
+#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000200)         /*!< ADC1 clock enabled in sleep mode */
+#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)         /*!< SDIO clock enabled in sleep mode */
+#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)         /*!< SPI1 clock enabled in sleep mode */
+#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00004000)         /*!< USART1 clock enabled in sleep mode */
+
+/*****************  Bit definition for RCC_APB1LPENR register  ****************/
+#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)        /*!< Timer 3 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)        /*!< Timer 4 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)        /*!< Timer 5 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)        /*!< Timer 7 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_LCDLPEN               ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */
+#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */
+#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)        /*!< SPI 2 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)        /*!< SPI 3 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)        /*!< USART 2 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)        /*!< USART 3 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)        /*!< UART 4 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)        /*!< UART 5 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)        /*!< I2C 1 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)        /*!< I2C 2 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_USBLPEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */
+#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)        /*!< Power interface clock enabled in sleep mode */
+#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)        /*!< DAC interface clock enabled in sleep mode */
+#define  RCC_APB1LPENR_COMPLPEN              ((uint32_t)0x80000000)        /*!< Comparator interface clock enabled in sleep mode*/
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define  RCC_CSR_LSION                      ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                     ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+
+#define  RCC_CSR_LSEON                      ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */
+#define  RCC_CSR_LSERDY                     ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */
+#define  RCC_CSR_LSEBYP                     ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */
+#define  RCC_CSR_LSECSSON                   ((uint32_t)0x00000800)        /*!< External Low Speed oscillator CSS Enable */
+#define  RCC_CSR_LSECSSD                    ((uint32_t)0x00001000)        /*!< External Low Speed oscillator CSS Detected */
+
+#define  RCC_CSR_RTCSEL                     ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_CSR_RTCSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  RCC_CSR_RTCSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define  RCC_CSR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CSR_RTCSEL_LSE                 ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_CSR_RTCSEL_LSI                 ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_CSR_RTCSEL_HSE                 ((uint32_t)0x00030000)        /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
+
+#define  RCC_CSR_RTCEN                      ((uint32_t)0x00400000)        /*!< RTC clock enable */
+#define  RCC_CSR_RTCRST                     ((uint32_t)0x00800000)        /*!< RTC reset  */
+ 
+#define  RCC_CSR_RMVF                       ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                    ((uint32_t)0x02000000)        /*!< Option Bytes Loader reset flag */
+#define  RCC_CSR_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                    ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                    ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                   ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
+#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
+#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
+#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
+
+#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
+
+#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
+
+#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
+
+#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
+#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
+#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
+#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
+#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
+#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
+#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
+
+#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
+#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
+#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
+#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
+#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
+#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
+#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
+#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
+#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
+#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
+#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
+#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
+#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
+#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
+#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
+#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
+#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
+#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
+#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
+#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
+#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
+#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
+#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
+#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
+#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
+#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
+#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
+#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
+#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
+#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
+#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
+#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
+#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
+#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
+#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
+#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
+#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
+#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
+#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
+#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
+#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Serial Peripheral Interface (SPI)                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
+#define  SPI_CR2_FRF                         ((uint8_t)0x08)               /*!< Frame format */
+#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
+#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_MEMRMP_BOOT_MODE         ((uint32_t)0x00000300) /*!< Boot mode Config */
+#define SYSCFG_MEMRMP_BOOT_MODE_0       ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SYSCFG_MEMRMP_BOOT_MODE_1       ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*****************  Bit definition for SYSCFG_PMC register  *******************/
+#define SYSCFG_PMC_USB_PU               ((uint32_t)0x00000001) /*!< SYSCFG PMC */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/** 
+  * @brief  EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0005) /*!< PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0006) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0007) /*!< PG[0] pin */
+
+/** 
+  * @brief  EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0050) /*!< PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0060) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0070) /*!< PG[1] pin */
+
+/** 
+  * @brief  EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0500) /*!< PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0600) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0700) /*!< PG[2] pin */
+
+/** 
+  * @brief  EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x3000) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x4000) /*!< PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/** 
+  * @brief  EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0006) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0007) /*!< PG[4] pin */
+
+/** 
+  * @brief  EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0060) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0070) /*!< PG[5] pin */
+
+/** 
+  * @brief  EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0600) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0700) /*!< PG[6] pin */
+
+/** 
+  * @brief  EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x6000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x7000) /*!< PG[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/** 
+  * @brief  EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0006) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0007) /*!< PG[8] pin */
+
+/** 
+  * @brief  EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0060) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0070) /*!< PG[9] pin */
+
+/** 
+  * @brief  EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0600) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0700) /*!< PG[10] pin */
+
+/** 
+  * @brief  EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x6000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x7000) /*!< PG[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/** 
+  * @brief  EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0006) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0007) /*!< PG[12] pin */
+
+/** 
+  * @brief  EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0060) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0070) /*!< PG[13] pin */
+
+/** 
+  * @brief  EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0600) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0700) /*!< PG[14] pin */
+
+/** 
+  * @brief  EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x6000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x7000) /*!< PG[15] pin */
+ 
+/******************************************************************************/
+/*                                                                            */
+/*                       Routing Interface (RI)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RI_ICR register  ********************/
+#define  RI_ICR_IC1Z                    ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */
+#define  RI_ICR_IC1Z_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_ICR_IC1Z_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_ICR_IC1Z_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_ICR_IC1Z_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define  RI_ICR_IC2Z                    ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
+#define  RI_ICR_IC2Z_0                  ((uint32_t)0x00000010) /*!< Bit 0 */
+#define  RI_ICR_IC2Z_1                  ((uint32_t)0x00000020) /*!< Bit 1 */
+#define  RI_ICR_IC2Z_2                  ((uint32_t)0x00000040) /*!< Bit 2 */
+#define  RI_ICR_IC2Z_3                  ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define  RI_ICR_IC3Z                    ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */
+#define  RI_ICR_IC3Z_0                  ((uint32_t)0x00000100) /*!< Bit 0 */
+#define  RI_ICR_IC3Z_1                  ((uint32_t)0x00000200) /*!< Bit 1 */
+#define  RI_ICR_IC3Z_2                  ((uint32_t)0x00000400) /*!< Bit 2 */
+#define  RI_ICR_IC3Z_3                  ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define  RI_ICR_IC4Z                    ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */
+#define  RI_ICR_IC4Z_0                  ((uint32_t)0x00001000) /*!< Bit 0 */
+#define  RI_ICR_IC4Z_1                  ((uint32_t)0x00002000) /*!< Bit 1 */
+#define  RI_ICR_IC4Z_2                  ((uint32_t)0x00004000) /*!< Bit 2 */
+#define  RI_ICR_IC4Z_3                  ((uint32_t)0x00008000) /*!< Bit 3 */
+
+#define  RI_ICR_TIM                     ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
+#define  RI_ICR_TIM_0                   ((uint32_t)0x00010000) /*!< Bit 0 */
+#define  RI_ICR_TIM_1                   ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define  RI_ICR_IC1                     ((uint32_t)0x00040000) /*!< Input capture 1 */
+#define  RI_ICR_IC2                     ((uint32_t)0x00080000) /*!< Input capture 2 */
+#define  RI_ICR_IC3                     ((uint32_t)0x00100000) /*!< Input capture 3 */
+#define  RI_ICR_IC4                     ((uint32_t)0x00200000) /*!< Input capture 4 */
+
+/********************  Bit definition for RI_ASCR1 register  ********************/
+#define  RI_ASCR1_CH                    ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
+#define  RI_ASCR1_CH_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_ASCR1_CH_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_ASCR1_CH_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_ASCR1_CH_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_ASCR1_CH_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_ASCR1_CH_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_ASCR1_CH_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_ASCR1_CH_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_ASCR1_CH_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_ASCR1_CH_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_ASCR1_CH_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_ASCR1_CH_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_ASCR1_CH_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_ASCR1_CH_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_ASCR1_CH_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_ASCR1_CH_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
+#define  RI_ASCR1_CH_31                 ((uint32_t)0x00010000) /*!< Bit 16 */
+#define  RI_ASCR1_CH_18                 ((uint32_t)0x00040000) /*!< Bit 18 */
+#define  RI_ASCR1_CH_19                 ((uint32_t)0x00080000) /*!< Bit 19 */
+#define  RI_ASCR1_CH_20                 ((uint32_t)0x00100000) /*!< Bit 20 */
+#define  RI_ASCR1_CH_21                 ((uint32_t)0x00200000) /*!< Bit 21 */
+#define  RI_ASCR1_CH_22                 ((uint32_t)0x00400000) /*!< Bit 22 */
+#define  RI_ASCR1_CH_23                 ((uint32_t)0x00800000) /*!< Bit 23 */
+#define  RI_ASCR1_CH_24                 ((uint32_t)0x01000000) /*!< Bit 24 */
+#define  RI_ASCR1_CH_25                 ((uint32_t)0x02000000) /*!< Bit 25 */
+#define  RI_ASCR1_VCOMP                 ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
+#define  RI_ASCR1_CH_27                 ((uint32_t)0x00400000) /*!< Bit 27 */
+#define  RI_ASCR1_CH_28                 ((uint32_t)0x00800000) /*!< Bit 28 */
+#define  RI_ASCR1_CH_29                 ((uint32_t)0x01000000) /*!< Bit 29 */
+#define  RI_ASCR1_CH_30                 ((uint32_t)0x02000000) /*!< Bit 30 */
+#define  RI_ASCR1_SCM                   ((uint32_t)0x80000000) /*!< I/O Switch control mode */
+
+/********************  Bit definition for RI_ASCR2 register  ********************/
+#define  RI_ASCR2_GR10_1                ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
+#define  RI_ASCR2_GR10_2                ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
+#define  RI_ASCR2_GR10_3                ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
+#define  RI_ASCR2_GR10_4                ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
+#define  RI_ASCR2_GR6_1                 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
+#define  RI_ASCR2_GR6_2                 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
+#define  RI_ASCR2_GR5_1                 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
+#define  RI_ASCR2_GR5_2                 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
+#define  RI_ASCR2_GR5_3                 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
+#define  RI_ASCR2_GR4_1                 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
+#define  RI_ASCR2_GR4_2                 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
+#define  RI_ASCR2_GR4_3                 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
+#define  RI_ASCR2_GR4_4                 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
+#define  RI_ASCR2_CH0b                  ((uint32_t)0x00010000) /*!< CH0b selection bit */
+#define  RI_ASCR2_CH1b                  ((uint32_t)0x00020000) /*!< CH1b selection bit */
+#define  RI_ASCR2_CH2b                  ((uint32_t)0x00040000) /*!< CH2b selection bit */
+#define  RI_ASCR2_CH3b                  ((uint32_t)0x00080000) /*!< CH3b selection bit */
+#define  RI_ASCR2_CH6b                  ((uint32_t)0x00100000) /*!< CH6b selection bit */
+#define  RI_ASCR2_CH7b                  ((uint32_t)0x00200000) /*!< CH7b selection bit */
+#define  RI_ASCR2_CH8b                  ((uint32_t)0x00400000) /*!< CH8b selection bit */
+#define  RI_ASCR2_CH9b                  ((uint32_t)0x00800000) /*!< CH9b selection bit */
+#define  RI_ASCR2_CH10b                 ((uint32_t)0x01000000) /*!< CH10b selection bit */
+#define  RI_ASCR2_CH11b                 ((uint32_t)0x02000000) /*!< CH11b selection bit */
+#define  RI_ASCR2_CH12b                 ((uint32_t)0x04000000) /*!< CH12b selection bit */
+#define  RI_ASCR2_GR6_3                 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
+#define  RI_ASCR2_GR6_4                 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
+#define  RI_ASCR2_GR5_4                 ((uint32_t)0x20000000) /*!< GR5-4 selection bit */
+
+/********************  Bit definition for RI_HYSCR1 register  ********************/
+#define  RI_HYSCR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
+#define  RI_HYSCR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_HYSCR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_HYSCR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_HYSCR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_HYSCR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_HYSCR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_HYSCR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_HYSCR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_HYSCR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_HYSCR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_HYSCR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_HYSCR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_HYSCR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_HYSCR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_HYSCR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_HYSCR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define  RI_HYSCR1_PB                   ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
+#define  RI_HYSCR1_PB_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define  RI_HYSCR1_PB_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define  RI_HYSCR1_PB_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define  RI_HYSCR1_PB_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define  RI_HYSCR1_PB_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define  RI_HYSCR1_PB_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define  RI_HYSCR1_PB_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define  RI_HYSCR1_PB_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define  RI_HYSCR1_PB_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define  RI_HYSCR1_PB_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define  RI_HYSCR1_PB_10                ((uint32_t)0x04000000) /*!< Bit 10 */
+#define  RI_HYSCR1_PB_11                ((uint32_t)0x08000000) /*!< Bit 11 */
+#define  RI_HYSCR1_PB_12                ((uint32_t)0x10000000) /*!< Bit 12 */
+#define  RI_HYSCR1_PB_13                ((uint32_t)0x20000000) /*!< Bit 13 */
+#define  RI_HYSCR1_PB_14                ((uint32_t)0x40000000) /*!< Bit 14 */
+#define  RI_HYSCR1_PB_15                ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/********************  Bit definition for RI_HYSCR2 register  ********************/
+#define  RI_HYSCR2_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
+#define  RI_HYSCR2_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_HYSCR2_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_HYSCR2_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_HYSCR2_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_HYSCR2_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_HYSCR2_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_HYSCR2_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_HYSCR2_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_HYSCR2_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_HYSCR2_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_HYSCR2_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_HYSCR2_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_HYSCR2_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_HYSCR2_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_HYSCR2_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_HYSCR2_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define  RI_HYSCR2_PD                   ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
+#define  RI_HYSCR2_PD_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define  RI_HYSCR2_PD_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define  RI_HYSCR2_PD_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define  RI_HYSCR2_PD_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define  RI_HYSCR2_PD_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define  RI_HYSCR2_PD_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define  RI_HYSCR2_PD_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define  RI_HYSCR2_PD_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define  RI_HYSCR2_PD_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define  RI_HYSCR2_PD_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define  RI_HYSCR2_PD_10                ((uint32_t)0x04000000) /*!< Bit 10 */
+#define  RI_HYSCR2_PD_11                ((uint32_t)0x08000000) /*!< Bit 11 */
+#define  RI_HYSCR2_PD_12                ((uint32_t)0x10000000) /*!< Bit 12 */
+#define  RI_HYSCR2_PD_13                ((uint32_t)0x20000000) /*!< Bit 13 */
+#define  RI_HYSCR2_PD_14                ((uint32_t)0x40000000) /*!< Bit 14 */
+#define  RI_HYSCR2_PD_15                ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/********************  Bit definition for RI_HYSCR3 register  ********************/
+#define  RI_HYSCR2_PE                   ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
+#define  RI_HYSCR2_PE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_HYSCR2_PE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_HYSCR2_PE_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_HYSCR2_PE_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_HYSCR2_PE_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_HYSCR2_PE_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_HYSCR2_PE_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_HYSCR2_PE_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_HYSCR2_PE_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_HYSCR2_PE_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_HYSCR2_PE_10                ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_HYSCR2_PE_11                ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_HYSCR2_PE_12                ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_HYSCR2_PE_13                ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_HYSCR2_PE_14                ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_HYSCR2_PE_15                ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define  RI_HYSCR3_PF                   ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
+#define  RI_HYSCR3_PF_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define  RI_HYSCR3_PF_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define  RI_HYSCR3_PF_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define  RI_HYSCR3_PF_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define  RI_HYSCR3_PF_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define  RI_HYSCR3_PF_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define  RI_HYSCR3_PF_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define  RI_HYSCR3_PF_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define  RI_HYSCR3_PF_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define  RI_HYSCR3_PF_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define  RI_HYSCR3_PF_10                ((uint32_t)0x04000000) /*!< Bit 10 */
+#define  RI_HYSCR3_PF_11                ((uint32_t)0x08000000) /*!< Bit 11 */
+#define  RI_HYSCR3_PF_12                ((uint32_t)0x10000000) /*!< Bit 12 */
+#define  RI_HYSCR3_PF_13                ((uint32_t)0x20000000) /*!< Bit 13 */
+#define  RI_HYSCR3_PF_14                ((uint32_t)0x40000000) /*!< Bit 14 */
+#define  RI_HYSCR3_PF_15                ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/********************  Bit definition for RI_HYSCR4 register  ********************/
+#define  RI_HYSCR4_PG                   ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
+#define  RI_HYSCR4_PG_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_HYSCR4_PG_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_HYSCR4_PG_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_HYSCR4_PG_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_HYSCR4_PG_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_HYSCR4_PG_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_HYSCR4_PG_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_HYSCR4_PG_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_HYSCR4_PG_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_HYSCR4_PG_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_HYSCR4_PG_10                ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_HYSCR4_PG_11                ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_HYSCR4_PG_12                ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_HYSCR4_PG_13                ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_HYSCR4_PG_14                ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_HYSCR4_PG_15                ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!<OCCS bits (OCref Clear Selection) */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+                   
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+           
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define  TIM_OR_TI1RMP                       ((uint16_t)0x0003)            /*!<Option register for TI1 Remapping */
+#define  TIM_OR_TI1RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_OR_TI1RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_SR register  *******************/
+#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
+#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
+#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
+#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
+#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
+#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
+#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
+#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
+#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
+#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
+#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
+#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
+#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
+#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
+#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< Oversampling by 8-bit mode */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
+#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
+
+#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
+#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
+#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One sample bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Universal Serial Bus (USB)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*!<Endpoint-specific registers */
+/*******************  Bit definition for USB_EP0R register  *******************/
+#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP1R register  *******************/
+#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP2R register  *******************/
+#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP3R register  *******************/
+#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP4R register  *******************/
+#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP5R register  *******************/
+#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP6R register  *******************/
+#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP7R register  *******************/
+#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*!<Common registers */
+/*******************  Bit definition for USB_CNTR register  *******************/
+#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!<Force USB Reset */
+#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!<Power down */
+#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!<Low-power mode */
+#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!<Force suspend */
+#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!<Resume request */
+#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!<Expected Start Of Frame Interrupt Mask */
+#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!<Start Of Frame Interrupt Mask */
+#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!<RESET Interrupt Mask */
+#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!<Suspend mode Interrupt Mask */
+#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!<Wakeup Interrupt Mask */
+#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!<Error Interrupt Mask */
+#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun Interrupt Mask */
+#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!<Correct Transfer Interrupt Mask */
+
+/*******************  Bit definition for USB_ISTR register  *******************/
+#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!<Endpoint Identifier */
+#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!<Direction of transaction */
+#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!<Expected Start Of Frame */
+#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!<Start Of Frame */
+#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!<USB RESET request */
+#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!<Suspend mode request */
+#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!<Wake up */
+#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!<Error */
+#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun */
+#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!<Correct Transfer */
+
+/*******************  Bit definition for USB_FNR register  ********************/
+#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!<Frame Number */
+#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!<Lost SOF */
+#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!<Locked */
+#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!<Receive Data - Line Status */
+#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!<Receive Data + Line Status */
+
+/******************  Bit definition for USB_DADDR register  *******************/
+#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!<ADD[6:0] bits (Device Address) */
+#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!<Bit 0 */
+#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!<Bit 1 */
+#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!<Bit 2 */
+#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!<Bit 3 */
+#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!<Bit 4 */
+#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!<Bit 5 */
+#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!<Bit 6 */
+
+#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!<Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/    
+#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!<Buffer Table */
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        SystemTick (SysTick)                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SysTick_CTRL register  *****************/
+#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
+#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
+#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
+#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
+
+/*****************  Bit definition for SysTick_LOAD register  *****************/
+#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/*****************  Bit definition for SysTick_VAL register  ******************/
+#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
+
+/*****************  Bit definition for SysTick_CALIB register  ****************/
+#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
+#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
+#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/*                                                                            */
+/*               Nested Vectored Interrupt Controller (NVIC)                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for NVIC_ISER register  *******************/
+#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
+#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICER register  *******************/
+#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
+#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ISPR register  *******************/
+#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
+#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICPR register  *******************/
+#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
+#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_IABR register  *******************/
+#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
+#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_PRI0 register  *******************/
+#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
+#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
+#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
+#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
+
+/******************  Bit definition for NVIC_PRI1 register  *******************/
+#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
+#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
+#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
+#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
+
+/******************  Bit definition for NVIC_PRI2 register  *******************/
+#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
+#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
+#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
+#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
+
+/******************  Bit definition for NVIC_PRI3 register  *******************/
+#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
+#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
+#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
+#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
+
+/******************  Bit definition for NVIC_PRI4 register  *******************/
+#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
+#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
+#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
+#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
+
+/******************  Bit definition for NVIC_PRI5 register  *******************/
+#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
+#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
+#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
+#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
+
+/******************  Bit definition for NVIC_PRI6 register  *******************/
+#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
+#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
+#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
+#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
+
+/******************  Bit definition for NVIC_PRI7 register  *******************/
+#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
+#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
+#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
+#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
+
+/******************  Bit definition for SCB_CPUID register  *******************/
+#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
+#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
+#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
+#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
+#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
+
+/*******************  Bit definition for SCB_ICSR register  *******************/
+#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
+#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
+#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
+#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
+#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
+#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
+#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
+#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
+
+/*******************  Bit definition for SCB_VTOR register  *******************/
+#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
+#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
+
+/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
+#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
+#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
+#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
+
+#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
+#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
+
+/* prority group configuration */
+#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
+#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/*******************  Bit definition for SCB_SCR register  ********************/
+#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
+#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
+#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
+
+/********************  Bit definition for SCB_CCR register  *******************/
+#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
+#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
+#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
+#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/*******************  Bit definition for SCB_SHPR register ********************/
+#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/******************  Bit definition for SCB_SHCSR register  *******************/
+#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
+#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
+#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
+#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
+#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
+#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
+#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
+#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
+#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
+#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
+#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
+#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
+#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
+#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
+
+/*******************  Bit definition for SCB_CFSR register  *******************/
+/*!< MFSR */
+#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
+#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
+#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
+#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
+#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
+#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
+#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
+#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
+#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
+#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */
+#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
+#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
+#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
+#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/*******************  Bit definition for SCB_HFSR register  *******************/
+#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */
+#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
+
+/*******************  Bit definition for SCB_DFSR register  *******************/
+#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
+#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
+#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
+#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
+#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
+
+/*******************  Bit definition for SCB_MMFAR register  ******************/
+#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
+
+/*******************  Bit definition for SCB_BFAR register  *******************/
+#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
+
+/*******************  Bit definition for SCB_afsr register  *******************/
+#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32l1xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1XX_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/system_stm32f0xx.h b/os/ext/CMSIS/ST/system_stm32f0xx.h
new file mode 100644
index 000000000..e9335b9c5
--- /dev/null
+++ b/os/ext/CMSIS/ST/system_stm32f0xx.h
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f0xx.h
+  * @author  MCD Application Team
+  * @version V1.2.1
+  * @date    22-November-2013
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F0xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/system_stm32f10x.h b/os/ext/CMSIS/ST/system_stm32f10x.h
new file mode 100644
index 000000000..739f33283
--- /dev/null
+++ b/os/ext/CMSIS/ST/system_stm32f10x.h
@@ -0,0 +1,98 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F10x_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/system_stm32f30x.h b/os/ext/CMSIS/ST/system_stm32f30x.h
new file mode 100644
index 000000000..797423449
--- /dev/null
+++ b/os/ext/CMSIS/ST/system_stm32f30x.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f30x.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    04-September-2012
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F30x devices.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f30x_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F30X_H
+#define __SYSTEM_STM32F30X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F30x_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F30x_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F30X_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/system_stm32f37x.h b/os/ext/CMSIS/ST/system_stm32f37x.h
new file mode 100644
index 000000000..897183ea5
--- /dev/null
+++ b/os/ext/CMSIS/ST/system_stm32f37x.h
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f37x.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f37x_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F37X_H
+#define __SYSTEM_STM32F37X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F37x_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F37x_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F37X_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/system_stm32f4xx.h b/os/ext/CMSIS/ST/system_stm32f4xx.h
new file mode 100644
index 000000000..000e382dd
--- /dev/null
+++ b/os/ext/CMSIS/ST/system_stm32f4xx.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V1.2.1
+  * @date    19-September-2013
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/system_stm32l1xx.h b/os/ext/CMSIS/ST/system_stm32l1xx.h
new file mode 100644
index 000000000..9772b4f43
--- /dev/null
+++ b/os/ext/CMSIS/ST/system_stm32l1xx.h
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.h
+  * @author  MCD Application Team
+  * @version V1.2.0
+  * @date    22-February-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L1XX_H
+#define __SYSTEM_STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32L1xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L1xx_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L1XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/include/arm_common_tables.h b/os/ext/CMSIS/include/arm_common_tables.h
new file mode 100644
index 000000000..9c37ab4e5
--- /dev/null
+++ b/os/ext/CMSIS/include/arm_common_tables.h
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/os/ext/CMSIS/include/arm_const_structs.h b/os/ext/CMSIS/include/arm_const_structs.h
new file mode 100644
index 000000000..406f737dc
--- /dev/null
+++ b/os/ext/CMSIS/include/arm_const_structs.h
@@ -0,0 +1,85 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
+*
+* Description:  This file has constant structs that are initialized for
+*               user convenience.  For example, some can be given as
+*               arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
+      16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
+      32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
+      64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
+      128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
+      256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
+      512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
+      1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
+      2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
+      4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
+   };
+
+#endif
diff --git a/os/ext/CMSIS/include/arm_math.h b/os/ext/CMSIS/include/arm_math.h
new file mode 100644
index 000000000..59662ae1a
--- /dev/null
+++ b/os/ext/CMSIS/include/arm_math.h
@@ -0,0 +1,7306 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * <b>Using the Library</b>
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * <b>Examples</b>
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * <b>Toolchain Support</b>
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * <b>Building the Library</b>
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * <b>Pre-processor Macros</b>
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) -
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) +
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+#if   defined ( __CC_ARM ) //Keil
+//SMMLAR
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("push")         \
+     _Pragma ("O1")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT \
+     _Pragma ("pop")
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/os/ext/CMSIS/include/core_cm0.h b/os/ext/CMSIS/include/core_cm0.h
new file mode 100644
index 000000000..1b6b54ef4
--- /dev/null
+++ b/os/ext/CMSIS/include/core_cm0.h
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/os/ext/CMSIS/include/core_cm0plus.h b/os/ext/CMSIS/include/core_cm0plus.h
new file mode 100644
index 000000000..d1c392314
--- /dev/null
+++ b/os/ext/CMSIS/include/core_cm0plus.h
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/os/ext/CMSIS/include/core_cm3.h b/os/ext/CMSIS/include/core_cm3.h
new file mode 100644
index 000000000..0e215fc05
--- /dev/null
+++ b/os/ext/CMSIS/include/core_cm3.h
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/os/ext/CMSIS/include/core_cm4.h b/os/ext/CMSIS/include/core_cm4.h
new file mode 100644
index 000000000..2c8b0882c
--- /dev/null
+++ b/os/ext/CMSIS/include/core_cm4.h
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/os/ext/CMSIS/include/core_cm4_simd.h b/os/ext/CMSIS/include/core_cm4_simd.h
new file mode 100644
index 000000000..af1831ee1
--- /dev/null
+++ b/os/ext/CMSIS/include/core_cm4_simd.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/os/ext/CMSIS/include/core_cmFunc.h b/os/ext/CMSIS/include/core_cmFunc.h
new file mode 100644
index 000000000..b5936735e
--- /dev/null
+++ b/os/ext/CMSIS/include/core_cmFunc.h
@@ -0,0 +1,639 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#else
+  /* CHIBIOS FIX */
+  (void)fpscr;
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/os/ext/CMSIS/include/core_cmInstr.h b/os/ext/CMSIS/include/core_cmInstr.h
new file mode 100644
index 000000000..8946c2c49
--- /dev/null
+++ b/os/ext/CMSIS/include/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/os/ext/CMSIS/readme.txt b/os/ext/CMSIS/readme.txt
new file mode 100644
index 000000000..e9d6eb03b
--- /dev/null
+++ b/os/ext/CMSIS/readme.txt
@@ -0,0 +1,6 @@
+CMSIS is Copyright (C) 2011-2013 ARM Limited. All rights reserved.
+
+This directory contains only part of the CMSIS package. If you need the whole
+package please download it from:
+
+http://www.arm.com
diff --git a/os/fs/fatfs/fatfs_fsimpl.cpp b/os/fs/fatfs/fatfs_fsimpl.cpp
deleted file mode 100644
index 567c7544a..000000000
--- a/os/fs/fatfs/fatfs_fsimpl.cpp
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-/**
- * @file    fs_fatfs_impl.cpp
- * @brief   FatFS file system wrapper.
- *
- * @addtogroup fs_fatfs_wrapper
- * @{
- */
-
-#include "ch.hpp"
-#include "fs.hpp"
-#include "fatfs_fsimpl.hpp"
-#include "hal.h"
-
-#define MSG_TERMINATE                   (msg_t)0
-
-#define ERR_OK                          (msg_t)0
-#define ERR_TERMINATING                 (msg_t)1
-#define ERR_UNKNOWN_MSG                 (msg_t)2
-
-using namespace chibios_rt;
-using namespace chibios_fs;
-
-/**
- * @brief   FatFS wrapper-related classes and interfaces.
- */
-namespace chibios_fatfs {
-
-  typedef struct {
-    uint32_t            msg_code;
-    union {
-      struct {
-
-      };
-    } op;
-  } wmsg_t;
-
-  /*------------------------------------------------------------------------*
-   * chibios_fatfs::FatFSFileWrapper                                        *
-   *------------------------------------------------------------------------*/
-  FatFSFileWrapper::FatFSFileWrapper(void) : fs(NULL) {
-
-  }
-
-  FatFSFileWrapper::FatFSFileWrapper(FatFSWrapper *fsref) : fs(fsref) {
-
-  }
-
-  size_t FatFSFileWrapper::write(const uint8_t *bp, size_t n) {
-
-    return 0;
-  }
-
-  size_t FatFSFileWrapper::read(uint8_t *bp, size_t n) {
-
-    return 0;
-  }
-
-  msg_t FatFSFileWrapper::put(uint8_t b) {
-
-    return 0;
-  }
-
-  msg_t FatFSFileWrapper::get(void) {
-
-    return 0;
-  }
-
-  uint32_t FatFSFileWrapper::getAndClearLastError(void) {
-
-    return 0;
-  }
-
-  fileoffset_t FatFSFileWrapper::getSize(void) {
-
-    return 0;
-  }
-
-  fileoffset_t FatFSFileWrapper::getPosition(void) {
-
-    return 0;
-  }
-
-  uint32_t FatFSFileWrapper::setPosition(fileoffset_t offset) {
-
-    return 0;
-  }
-
-  /*------------------------------------------------------------------------*
-   * chibios_fatfs::FatFSFilesPool                                          *
-   *------------------------------------------------------------------------*/
-  FatFSFilesPool::FatFSFilesPool(void) : ObjectsPool<FatFSFileWrapper,
-                                                     FATFS_MAX_FILES>() {
-
-  }
-
-  /*------------------------------------------------------------------------*
-   * chibios_fatfs::FatFSServerThread                                       *
-   *------------------------------------------------------------------------*/
-  FatFSServerThread::FatFSServerThread(void) :
-      BaseStaticThread<FATFS_THREAD_STACK_SIZE>() {
-  }
-
-  msg_t FatFSServerThread::main() {
-    msg_t sts;
-
-    setName("fatfs");
-
-    /* Synchronous messages processing loop.*/
-    while (true) {
-      ThreadReference tr = waitMessage();
-      msg_t msg = tr.getMessage();
-      switch (msg) {
-      case MSG_TERMINATE:
-        /* The server object is being destroyed, terminating.*/
-        tr.releaseMessage(ERR_TERMINATING);
-        return 0;
-      default:
-        sts = ERR_UNKNOWN_MSG;
-      }
-      tr.releaseMessage(sts);
-    }
-  }
-
-  void FatFSServerThread::stop(void) {
-
-    sendMessage(MSG_TERMINATE);
-    wait();
-  }
-
-  /*------------------------------------------------------------------------*
-   * chibios_fatfs::FatFSWrapper                                            *
-   *------------------------------------------------------------------------*/
-  FatFSWrapper::FatFSWrapper(void) {
-
-  }
-
-  void FatFSWrapper::mount(void) {
-
-    server.start(FATFS_THREAD_PRIORITY);
-  }
-
-  void FatFSWrapper::unmount(void) {
-
-    server.stop();
-  }
-
-  uint32_t FatFSWrapper::getAndClearLastError(void) {
-
-    return 0;
-  }
-
-  void FatFSWrapper::synchronize(void) {
-
-  }
-
-  void FatFSWrapper::remove(const char *fname) {
-
-    (void)fname;
-  }
-
-  BaseFileStreamInterface *FatFSWrapper::open(const char *fname) {
-
-    (void)fname;
-    return NULL;
-  }
-
-  BaseFileStreamInterface *FatFSWrapper::openForRead(const char *fname) {
-
-    (void)fname;
-    return NULL;
-  }
-
-  BaseFileStreamInterface *FatFSWrapper::openForWrite(const char *fname) {
-
-    (void)fname;
-    return NULL;
-  }
-
-  BaseFileStreamInterface *FatFSWrapper::create(const char *fname) {
-
-    (void)fname;
-    return NULL;
-  }
-
-  void FatFSWrapper::close(BaseFileStreamInterface *file) {
-
-    (void)file;
-  }
-}
-
-/** @} */
diff --git a/os/fs/fatfs/fatfs_fsimpl.hpp b/os/fs/fatfs/fatfs_fsimpl.hpp
deleted file mode 100644
index 0993a7917..000000000
--- a/os/fs/fatfs/fatfs_fsimpl.hpp
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    fs_fatfs_impl.hpp
- * @brief   FatFS file system wrapper header.
- *
- * @addtogroup cpp_library
- * @{
- */
-
-#include "ch.hpp"
-#include "fs.hpp"
-
-#ifndef _FS_FATFS_IMPL_HPP_
-#define _FS_FATFS_IMPL_HPP_
-
-/**
- * @brief   Stack size for the internal server thread.
- */
-#if !defined(FATFS_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
-#define FATFS_THREAD_STACK_SIZE         1024
-#endif
-
-/**
- * @brief   Priority for the internal server thread.
- */
-#if !defined(FATFS_THREAD_PRIORITY) || defined(__DOXYGEN__)
-#define FATFS_THREAD_PRIORITY           NORMALPRIO
-#endif
-
-/**
- * @brief   Maximum number of open files.
- */
-#if !defined(FATFS_MAX_FILES) || defined(__DOXYGEN__)
-#define FATFS_MAX_FILES                 16
-#endif
-
-using namespace chibios_rt;
-using namespace chibios_fs;
-
-/**
- * @brief   FatFS wrapper-related classes and interfaces.
- */
-namespace chibios_fatfs {
-
-  class FatFSWrapper;
-
-  /*------------------------------------------------------------------------*
-   * chibios_fatfs::FatFSFileWrapper                                        *
-   *------------------------------------------------------------------------*/
-  class FatFSFileWrapper : public BaseFileStreamInterface {
-    friend class FatFSWrapper;
-
-  protected:
-    FatFSWrapper *fs;
-
-  public:
-    FatFSFileWrapper(void);
-    FatFSFileWrapper(FatFSWrapper *fsref);
-
-    virtual size_t write(const uint8_t *bp, size_t n);
-    virtual size_t read(uint8_t *bp, size_t n);
-    virtual msg_t put(uint8_t b);
-    virtual msg_t get(void);
-    virtual uint32_t getAndClearLastError(void);
-    virtual fileoffset_t getSize(void);
-    virtual fileoffset_t getPosition(void);
-    virtual uint32_t setPosition(fileoffset_t offset);
-  };
-
-  /*------------------------------------------------------------------------*
-   * chibios_fatfs::FatFSFilesPool                                          *
-   *------------------------------------------------------------------------*/
-  /**
-   * @brief   Class of memory pool of @p FatFSFileWrapper objects.
-   */
-  class FatFSFilesPool : public ObjectsPool<FatFSFileWrapper,
-                                            FATFS_MAX_FILES> {
-  public:
-    FatFSFilesPool(void);
-  };
-
-  /*------------------------------------------------------------------------*
-   * chibios_fatfs::FatFSServerThread                                       *
-   *------------------------------------------------------------------------*/
-  /**
-   * @brief   Class of the internal server thread.
-   */
-  class FatFSServerThread : public BaseStaticThread<FATFS_THREAD_STACK_SIZE> {
-  private:
-    FatFSFilesPool files;
-  protected:
-    virtual msg_t main(void);
-  public:
-    FatFSServerThread(void);
-    virtual void stop(void);
-  };
-
-  /*------------------------------------------------------------------------*
-   * chibios_fatfs::FatFSWrapper                                            *
-   *------------------------------------------------------------------------*/
-  /**
-   * @brief   Class of the FatFS wrapper.
-   */
-  class FatFSWrapper : public chibios_fs::BaseFileSystemInterface {
-    friend class FatFSFileWrapper;
-
-  protected:
-    FatFSServerThread server;
-
-  public:
-    FatFSWrapper(void);
-    virtual uint32_t getAndClearLastError(void);
-    virtual void synchronize(void);
-    virtual void remove(const char *fname);
-    virtual BaseFileStreamInterface *open(const char *fname);
-    virtual BaseFileStreamInterface *openForRead(const char *fname);
-    virtual BaseFileStreamInterface *openForWrite(const char *fname);
-    virtual BaseFileStreamInterface *create(const char *fname);
-    virtual void close(BaseFileStreamInterface *file);
-
-    /**
-     * @brief   Mounts the file system.
-     */
-    void mount(void);
-
-    /**
-     * @brief   Unmounts the file system.
-     */
-    void unmount(void);
-  };
-}
-
-#endif /* _FS_FATFS_IMPL_HPP_ */
-
-/** @} */
diff --git a/os/fs/fs.hpp b/os/fs/fs.hpp
deleted file mode 100644
index 6a9bd6a5b..000000000
--- a/os/fs/fs.hpp
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    fs.hpp
- * @brief   File System interfaces header.
- *
- * @addtogroup fs_interface
- * @{
- */
-
-#ifndef _FS_HPP_
-#define _FS_HPP_
-
-#include "ch.hpp"
-
-/**
- * @name    Error codes
- * @{
- */
-/**
- * @brief   No error return code.
- */
-#define FILE_OK         0
-
-/**
- * @brief   Error code from the file stream methods.
- */
-#define FILE_ERROR      0xFFFFFFFFUL
-/** @} */
-
-/**
- * @brief   ChibiOS FS-related interfaces.
- */
-namespace chibios_fs {
-
-  /**
-   * @brief   File offset type.
-   */
-  typedef uint32_t fileoffset_t;
-
-  /*------------------------------------------------------------------------*
-   * chibios_fs::BaseFileStreamInterface                                    *
-   *------------------------------------------------------------------------*/
-  /**
-   * @brief   Interface of an abstract file object.
-   */
-  class BaseFileStreamInterface : public chibios_rt::BaseSequentialStreamInterface {
-  public:
-    /**
-     * @brief   Returns an implementation dependent error code.
-     *
-     * @return              An implementation-dependent error code.
-     *
-     * @api
-     */
-    virtual uint32_t getAndClearLastError(void) = 0;
-
-    /**
-     * @brief   Returns the current file size.
-     *
-     * @return              The file size.
-     * @retval FILE_ERROR   if the operation failed.
-     *
-     * @api
-     */
-    virtual fileoffset_t getSize(void) = 0;
-
-    /**
-     * @brief   Returns the current file pointer position.
-     *
-     * @return              The current position inside the file.
-     * @retval FILE_ERROR   if the operation failed.
-     *
-     * @api
-     */
-    virtual fileoffset_t getPosition(void) = 0;
-
-    /**
-     * @brief   sets the current file pointer position.
-     *
-     * @param[in] offset    new absolute position
-     * @return              The operation status.
-     * @retval FILE_OK      if no error.
-     * @retval FILE_ERROR   if the operation failed.
-     *
-     * @api
-     */
-    virtual uint32_t setPosition(fileoffset_t offset) = 0;
-  };
-
-  /*------------------------------------------------------------------------*
-   * chibios_fs::BaseFileSystemInterface                                    *
-   *------------------------------------------------------------------------*/
-  /**
-   * @brief   Interface of an abstract file system object.
-   * @note    The interface only exposes common features, the implementing
-   *          classes can offer an extended interface.
-   */
-  class BaseFileSystemInterface {
-  public:
-    /**
-     * @brief   Returns an implementation dependent error code.
-     *
-     * @return              An implementation-dependent error code.
-     *
-     * @api
-     */
-    virtual uint32_t getAndClearLastError(void) = 0;
-
-    /**
-     * @brief   Synchronizes caches with media device.
-     */
-    virtual void synchronize(void) = 0;
-
-    /**
-     * @brief   Removes a file.
-     *
-     * @param[in] fname     file name
-     *
-     * @api
-     */
-    virtual void remove(const char *fname) = 0;
-
-    /**
-     * @brief   Opens a file for read and write.
-     *
-     * @param[in] fname     file name
-     * @return              An interface of a file object.
-     * @retval NULL         if the operation failed.
-     *
-     * @api
-     */
-    virtual BaseFileStreamInterface *open(const char *fname) = 0;
-
-    /**
-     * @brief   Opens a file for read only.
-     *
-     * @param[in] fname     file name
-     * @return              An interface of a file object.
-     * @retval NULL         if the operation failed.
-     *
-     * @api
-     */
-    virtual BaseFileStreamInterface *openForRead(const char *fname) = 0;
-
-    /**
-     * @brief   Opens a file for write only.
-     *
-     * @param[in] fname     file name
-     * @return              An interface of a file object.
-     * @retval NULL         if the operation failed.
-     *
-     * @api
-     */
-    virtual BaseFileStreamInterface *openForWrite(const char *fname) = 0;
-
-    /**
-     * @brief   Creates a file and opens it for write only.
-     * @details If a file with the same name already exists then it is
-     *          overwritten.
-     *
-     * @param[in] fname     file name
-     * @return              An interface of a file object.
-     * @retval NULL         if the operation failed.
-     *
-     * @api
-     */
-    virtual BaseFileStreamInterface *create(const char *fname) = 0;
-
-    /**
-     * @brief   Closes a file.
-     *
-     * @api
-     */
-    virtual void close(BaseFileStreamInterface *file) = 0;
-  };
-}
-#endif /* _FS_HPP_ */
-
-/** @} */
diff --git a/os/hal/boards/ARDUINO_MEGA/board.c b/os/hal/boards/ARDUINO_MEGA/board.c
new file mode 100644
index 000000000..c3b9957f0
--- /dev/null
+++ b/os/hal/boards/ARDUINO_MEGA/board.c
@@ -0,0 +1,101 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+  {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+  {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+  {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+  {VAL_PORTG, VAL_DDRG},
+#endif
+#if defined(PORTH)
+  {VAL_PORTH, VAL_DDRH},
+#endif
+#if defined(PORTJ)
+  {VAL_PORTJ, VAL_DDRJ},
+#endif
+#if defined(PORTK)
+  {VAL_PORTK, VAL_DDRK},
+#endif
+#if defined(PORTL)
+  {VAL_PORTL, VAL_DDRL},
+#endif
+};
+#endif /* HAL_USE_PAL */
+
+/**
+ * @brief   Timer0 interrupt handler.
+ */
+CH_IRQ_HANDLER(TIMER0_COMPA_vect) {
+
+  CH_IRQ_PROLOGUE();
+
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EICRB  = 0x00;
+  EIMSK  = 0x00;
+
+  /*
+   * Timer 0 setup.
+   */
+  TCCR0A  = (1 << WGM01) | (0 << WGM00) |                /* CTC mode.        */
+            (0 << COM0A1) | (0 << COM0A0) |              /* OC0A disabled.   */
+            (0 << COM0B1) | (0 << COM0B0);               /* OC0B disabled.   */
+  TCCR0B  = (0 << WGM02) |                               /* CTC mode.        */
+            (0 << CS02)  | (1 << CS01)  | (1 << CS00);   /* CLK/64 clock.    */
+  OCR0A   = F_CPU / 64 / CH_FREQUENCY - 1;
+  TCNT0   = 0;                                           /* Reset counter.   */
+  TIFR0   = (1 << OCF0A);                                /* Reset pending.   */
+  TIMSK0  = (1 << OCIE0A);                               /* IRQ on compare.  */
+}
diff --git a/os/hal/boards/ARDUINO_MEGA/board.h b/os/hal/boards/ARDUINO_MEGA/board.h
new file mode 100644
index 000000000..9dc3b09e4
--- /dev/null
+++ b/os/hal/boards/ARDUINO_MEGA/board.h
@@ -0,0 +1,86 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Arduino Mega board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ARDUINO_MEGA
+#define BOARD_NAME "Arduino Mega"
+
+/* All inputs with pull-ups */
+#define VAL_DDRA  0x00
+#define VAL_PORTA 0xFF
+
+/* All inputs except PB7 which has a LED connected */
+#define VAL_DDRB  0x80
+#define VAL_PORTB 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRC  0x00
+#define VAL_PORTC 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRD  0x00
+#define VAL_PORTD 0xFF
+
+/* All inputs except PE1 (Serial TX0) */
+#define VAL_DDRE  0x02
+#define VAL_PORTE 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRF  0x00
+#define VAL_PORTF 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRG  0x00
+#define VAL_PORTG 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRH  0x00
+#define VAL_PORTH 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRJ  0x00
+#define VAL_PORTJ 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRK  0x00
+#define VAL_PORTK 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRL  0x00
+#define VAL_PORTL 0xFF
+
+#define PORTB_LED1        7
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ARDUINO_MEGA/board.mk b/os/hal/boards/ARDUINO_MEGA/board.mk
new file mode 100644
index 000000000..2eab5ef46
--- /dev/null
+++ b/os/hal/boards/ARDUINO_MEGA/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ARDUINO_MEGA/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ARDUINO_MEGA
diff --git a/os/hal/boards/EA_LPCXPRESSO_11C24/board.c b/os/hal/boards/EA_LPCXPRESSO_11C24/board.c
new file mode 100644
index 000000000..117e5252b
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_11C24/board.c
@@ -0,0 +1,53 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+    LPC11C24 EA Board support - Copyright (C) 2013 mike brown
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  lpc111x_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * Extra, board-specific, initializations.
+   */
+  LPC_IOCON->PIO0_7 = 0xC0;             /* Disables pull-up on LED2 output. */
+}
diff --git a/os/hal/boards/EA_LPCXPRESSO_11C24/board.h b/os/hal/boards/EA_LPCXPRESSO_11C24/board.h
new file mode 100644
index 000000000..b8de6f790
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_11C24/board.h
@@ -0,0 +1,82 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+    LPC11C24 EA Board support - Copyright (C) 2013 mike brown
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso LPC11C24
+ * board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC11C24
+#define BOARD_NAME "Embedded Artists LPCXpresso LPC11C24"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+
+/*
+ * SCK0 connection on this board.
+ */
+#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(GPIO0_LED)
+#define VAL_GPIO0DATA           0x00000000
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            0x00000000
+#define VAL_GPIO1DATA           0x00000000
+
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR            0x00000000
+#define VAL_GPIO2DATA           0x00000000
+
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR            0x00000000
+#define VAL_GPIO3DATA           0x00000000
+
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW_ISP            1
+#define GPIO0_LED               7
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_11C24/board.mk b/os/hal/boards/EA_LPCXPRESSO_11C24/board.mk
new file mode 100644
index 000000000..52bba5b94
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_11C24/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_11C24/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_11C24
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c
new file mode 100644
index 000000000..2267e54cc
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c
@@ -0,0 +1,58 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  lpc111x_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * Extra, board-specific, initializations.
+   * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG
+   *       you must comment that line first.
+   */
+  LPC_IOCON->PIO0_7 = 0xC0;             /* Disables pull-up on LED2 output. */
+  LPC_IOCON->R_PIO1_2 = 0xC1;           /* Disables pull-up on LED3B output
+                                           and makes it GPIO1_2.            */
+  LPC_IOCON->PIO1_9 = 0xC0;             /* Disables pull-up on LED3R output.*/
+  LPC_IOCON->PIO1_10 = 0xC0;            /* Disables pull-up on LED3G output.*/
+}
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.h b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.h
new file mode 100644
index 000000000..c27830d28
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.h
@@ -0,0 +1,96 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso Base Board with LPC1114 daughter
+ * board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC1114
+#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1114"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+
+/*
+ * SCK0 connection on this board.
+ */
+#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(GPIO0_OLEDSEL) |               \
+                                PAL_PORT_BIT(GPIO0_LED2)
+#define VAL_GPIO0DATA           PAL_PORT_BIT(GPIO0_OLEDSEL) |               \
+                                PAL_PORT_BIT(GPIO0_LED2)
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(GPIO1_LED3B)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3R)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3G)   |               \
+                                PAL_PORT_BIT(GPIO1_SPI0SEL)
+#define VAL_GPIO1DATA           PAL_PORT_BIT(GPIO1_LED3B)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3R)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3G)   |               \
+                                PAL_PORT_BIT(GPIO1_SPI0SEL)
+
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR            0x00000000
+#define VAL_GPIO2DATA           0x00000000
+
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR            0x00000000
+#define VAL_GPIO3DATA           0x00000000
+
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW3               1
+#define GPIO0_OLEDSEL           2
+#define GPIO0_LED2              7
+
+#define GPIO1_LED3B             2
+#define GPIO1_SW4               4
+#define GPIO1_LED3R             9
+#define GPIO1_LED3G             10
+#define GPIO1_SPI0SEL           11
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.mk b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.mk
new file mode 100644
index 000000000..0c7ddc599
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_1114
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c
new file mode 100644
index 000000000..f1ad1c014
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c
@@ -0,0 +1,65 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+  {VAL_GPIO0DATA, VAL_GPIO0DIR},
+  {VAL_GPIO1DATA, VAL_GPIO1DIR}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  lpc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * Extra, board-specific, initializations.
+   * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG
+   *       you must comment that line first.
+   */
+  LPC_IOCON->PIO0_7 = 0x80;             /* Disables pull-up on LED2 output. */
+  LPC_IOCON->TRST_PIO0_14 = 0x81;       /* Disables pull-up on LED3B output
+                                           and makes it GPIO1_2.            */
+  LPC_IOCON->PIO0_21 = 0x80;            /* Disables pull-up on LED3R output.*/
+  LPC_IOCON->PIO0_22 = 0x80;            /* Disables pull-up on LED3G output.*/
+
+  /* SSP0 mapping.*/
+  LPC_IOCON->PIO1_29 = 0x81;            /* SCK0 without resistors.          */
+  LPC_IOCON->PIO0_8  = 0x81;            /* MISO0 without resistors.         */
+  LPC_IOCON->PIO0_9  = 0x81;            /* MOSI0 without resistors.         */
+
+  /* USART mapping.*/
+  LPC_IOCON->PIO0_18 = 0x81;            /* RDX without resistors.           */
+  LPC_IOCON->PIO0_19 = 0x81;            /* TDX without resistors.           */
+}
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.h b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.h
new file mode 100644
index 000000000..dac011460
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.h
@@ -0,0 +1,88 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso Base Board with LPC1114 daughter
+ * board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC11U14
+#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC11U14"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+
+/*
+ * SCK0 connection on this board.
+ */
+#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(GPIO0_OLEDSEL)   |             \
+                                PAL_PORT_BIT(GPIO0_USB_DPCTL) |             \
+                                PAL_PORT_BIT(GPIO0_LED2)      |             \
+                                PAL_PORT_BIT(GPIO0_LED3B)     |             \
+                                PAL_PORT_BIT(GPIO0_LED3R)     |             \
+                                PAL_PORT_BIT(GPIO0_LED3G)     |             \
+                                PAL_PORT_BIT(GPIO0_SPI0SEL)
+#define VAL_GPIO0DATA           PAL_PORT_BIT(GPIO0_OLEDSEL)   |             \
+                                PAL_PORT_BIT(GPIO0_LED2)      |             \
+                                PAL_PORT_BIT(GPIO0_LED3B)     |             \
+                                PAL_PORT_BIT(GPIO0_LED3R)     |             \
+                                PAL_PORT_BIT(GPIO0_LED3G)     |             \
+                                PAL_PORT_BIT(GPIO0_SPI0SEL)
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            0x00000000
+#define VAL_GPIO1DATA           0x00000000
+
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW3               1
+#define GPIO0_OLEDSEL           2
+#define GPIO0_USB_VBUS          3
+#define GPIO0_USB_DPCTL         6
+#define GPIO0_LED2              7
+#define GPIO0_SW4               16
+#define GPIO0_LED3B             14
+#define GPIO0_LED3R             21
+#define GPIO0_LED3G             22
+#define GPIO0_SPI0SEL           23
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.mk b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.mk
new file mode 100644
index 000000000..47c26c176
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_11U14
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c
new file mode 100644
index 000000000..5061d62ad
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c
@@ -0,0 +1,58 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  LPC13xx_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * Extra, board-specific, initializations.
+   * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG
+   *       you must comment that line first.
+   */
+  LPC_IOCON->PIO0_7 = 0xC0;             /* Disables pull-up on LED2 output. */
+  LPC_IOCON->R_PIO1_2 = 0xC1;           /* Disables pull-up on LED3B output
+                                           and makes it GPIO1_2.            */
+  LPC_IOCON->PIO1_9 = 0xC0;             /* Disables pull-up on LED3R output.*/
+  LPC_IOCON->PIO1_10 = 0xC0;            /* Disables pull-up on LED3G output.*/
+}
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.h b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.h
new file mode 100644
index 000000000..b5ad73dbd
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.h
@@ -0,0 +1,91 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso Base Board with LPC1343 daughter
+ * board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC1343
+#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1343"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(GPIO0_OLEDSEL) |               \
+                                PAL_PORT_BIT(GPIO0_LED2)
+#define VAL_GPIO0DATA           PAL_PORT_BIT(GPIO0_OLEDSEL) |               \
+                                PAL_PORT_BIT(GPIO0_LED2)
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(GPIO1_LED3B)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3R)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3G)   |               \
+                                PAL_PORT_BIT(GPIO1_SPI0SEL)
+#define VAL_GPIO1DATA           PAL_PORT_BIT(GPIO1_LED3B)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3R)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3G)   |               \
+                                PAL_PORT_BIT(GPIO1_SPI0SEL)
+
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR            0x00000000
+#define VAL_GPIO2DATA           0x00000000
+
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR            0x00000000
+#define VAL_GPIO3DATA           0x00000000
+
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW3               1
+#define GPIO0_OLEDSEL           2
+#define GPIO0_LED2              7
+
+#define GPIO1_LED3B             2
+#define GPIO1_SW4               4
+#define GPIO1_LED3R             9
+#define GPIO1_LED3G             10
+#define GPIO1_SPI0SEL           11
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.mk b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.mk
new file mode 100644
index 000000000..84c902422
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_1343
diff --git a/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c
new file mode 100644
index 000000000..053ed1a3e
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c
@@ -0,0 +1,135 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {VAL_GPIO0DATA, VAL_GPIO0DIR};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void){
+
+  lpc8xx_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void){
+
+  /* Enable clocks to IOCON & SWM */
+  LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<18)|(1<<7));
+   
+#if defined VAL_PIO0_0
+  LPC_IOCON->PIO0_0 =  PIN_RSVD|VAL_PIO0_0;
+#endif
+#if defined VAL_PIO0_1
+  LPC_IOCON->PIO0_1 =  PIN_RSVD|VAL_PIO0_1;
+#endif
+#if defined VAL_PIO0_2
+  LPC_IOCON->PIO0_2 =  PIN_RSVD|VAL_PIO0_2;
+#endif
+#if defined VAL_PIO0_3
+  LPC_IOCON->PIO0_3 =  PIN_RSVD|VAL_PIO0_3;
+#endif
+#if defined VAL_PIO0_4
+  LPC_IOCON->PIO0_4 =  PIN_RSVD|VAL_PIO0_4;
+#endif
+#if defined VAL_PIO0_5
+  LPC_IOCON->PIO0_5 =  PIN_RSVD|VAL_PIO0_5;
+#endif
+#if defined VAL_PIO0_6
+  LPC_IOCON->PIO0_6 =  PIN_RSVD|VAL_PIO0_6;
+#endif
+#if defined VAL_PIO0_7
+  LPC_IOCON->PIO0_7 =  PIN_RSVD|VAL_PIO0_7;
+#endif
+#if defined VAL_PIO0_8
+  LPC_IOCON->PIO0_8 =  PIN_RSVD|VAL_PIO0_8;
+#endif
+#if defined VAL_PIO0_9
+  LPC_IOCON->PIO0_9 =  PIN_RSVD|VAL_PIO0_9;
+#endif
+#if defined VAL_PIO0_10
+  LPC_IOCON->PIO0_10 =  PIN_RSVD|VAL_PIO0_10;
+#endif
+#if defined VAL_PIO0_11
+  LPC_IOCON->PIO0_11 =  PIN_RSVD|VAL_PIO0_11;
+#endif
+#if defined VAL_PIO0_12
+  LPC_IOCON->PIO0_12 =  PIN_RSVD|VAL_PIO0_12;
+#endif
+#if defined VAL_PIO0_13
+  LPC_IOCON->PIO0_13 =  PIN_RSVD|VAL_PIO0_13;
+#endif
+#if defined VAL_PIO0_14
+  LPC_IOCON->PIO0_14 =  PIN_RSVD|VAL_PIO0_14;
+#endif
+#if defined VAL_PIO0_15
+  LPC_IOCON->PIO0_15 =  PIN_RSVD|VAL_PIO0_15;
+#endif
+#if defined VAL_PIO0_16
+  LPC_IOCON->PIO0_16 =  PIN_RSVD|VAL_PIO0_16;
+#endif
+#if defined VAL_PIO0_17
+  LPC_IOCON->PIO0_17 =  PIN_RSVD|VAL_PIO0_17;
+#endif
+
+
+#if defined VAL_PINASSIGN0
+  LPC_SWM->PINASSIGN0 = VAL_PINASSIGN0;
+#endif
+#if defined VAL_PINASSIGN1
+  LPC_SWM->PINASSIGN1 = VAL_PINASSIGN1;
+#endif
+#if defined VAL_PINASSIGN2
+  LPC_SWM->PINASSIGN2 = VAL_PINASSIGN2;
+#endif
+#if defined VAL_PINASSIGN3
+  LPC_SWM->PINASSIGN3 = VAL_PINASSIGN3;
+#endif
+#if defined VAL_PINASSIGN4
+  LPC_SWM->PINASSIGN4 = VAL_PINASSIGN4;
+#endif
+#if defined VAL_PINASSIGN5
+  LPC_SWM->PINASSIGN5 = VAL_PINASSIGN5;
+#endif
+#if defined VAL_PINASSIGN6
+  LPC_SWM->PINASSIGN6 = VAL_PINASSIGN6;
+#endif
+#if defined VAL_PINASSIGN7
+  LPC_SWM->PINASSIGN7 = VAL_PINASSIGN7;
+#endif
+#if defined VAL_PINASSIGN8
+  LPC_SWM->PINASSIGN8 = VAL_PINASSIGN8;
+#endif
+
+  /* Disable clocks to IOCON & SWM */
+  LPC_SYSCON->SYSAHBCLKCTRL &= ~((1<<18)|(1<<7));
+
+}
+
+
diff --git a/os/hal/boards/EA_LPCXPRESSO_LPC812/board.h b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.h
new file mode 100644
index 000000000..0a1618292
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.h
@@ -0,0 +1,125 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso LPC812 board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_LPC812
+#define BOARD_NAME "Embedded Artists LPCXpresso LPC812"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the LPC8xx Reference Manual for details.
+ */
+/* Pull-up/down  */
+#define PIN_MODE_NOPULL               (0<<3)
+#define PIN_MODE_PULLDOWN             (1<<3)
+#define PIN_MODE_PULLUP               (2<<3)
+#define PIN_MODE_REPEATER             (3<<3)
+/* Hysteresis */
+#define PIN_HYS_EN                    (1<<5)
+/* Invert Input */
+#define PIN_INV_INPUT                 (1<<6)
+/* Reserved bits */
+#define PIN_RSVD                      (1<<7)
+/* I2C Mode */
+#define PIN_I2CMODE_STD               (0<<8)
+#define PIN_I2CMODE_STDIO             (1<<8)
+#define PIN_I2CMODE_FAST              (2<<8)
+/* Open Drain */
+#define PIN_OPEN_DRAIN                (1<<10)
+/* Input Filter Sample Clocks */
+#define PIN_SMODE_FILTER(n)           ((n)<<11)
+/* Input Filter clock divider */
+#define PIN_CLKDIV_FILTER(n)          ((n)<<13)
+
+/*
+ * Pin definitions.
+ */
+#define LED_RED                        7
+#define LED_BLUE                      16
+#define LED_GREEN                     17
+
+
+/*
+ * GPIO 0 initial setup.
+ */
+/*#define VAL_PIO0_0              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_1              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_2              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_3              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_4              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_5              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_6              PIN_MODE_PULLUP*/
+#define VAL_PIO0_7              PIN_MODE_NOPULL
+/*#define VAL_PIO0_8              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_9              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_10             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_11             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_12             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_13             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_14             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_15             PIN_MODE_PULLUP*/
+#define VAL_PIO0_16             PIN_MODE_NOPULL
+#define VAL_PIO0_17             PIN_MODE_NOPULL
+
+    /* UART0: TXD = P0.4, RXD  = P0.0)*/
+#define VAL_PINASSIGN0            ((0xFFFF0000) | (0<<8) | (4))
+/*#define VAL_PINASSIGN1            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN2            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN3            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN4            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN5            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN6            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN7            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN8            0xFFFFFFFF*/
+
+
+#define VAL_GPIO0DIR            (PAL_PORT_BIT(LED_RED)   |           \
+                                 PAL_PORT_BIT(LED_BLUE)   |          \
+                                 PAL_PORT_BIT(LED_GREEN))
+                                
+#define VAL_GPIO0DATA           (PAL_PORT_BIT(LED_RED)   |           \
+                                 PAL_PORT_BIT(LED_BLUE)   |          \
+                                 PAL_PORT_BIT(LED_GREEN))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_LPC812/board.mk b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.mk
new file mode 100644
index 000000000..05fab9303
--- /dev/null
+++ b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_LPC812
diff --git a/os/hal/boards/MAPLEMINI_STM32_F103/board.c b/os/hal/boards/MAPLEMINI_STM32_F103/board.c
new file mode 100644
index 000000000..bd21d1738
--- /dev/null
+++ b/os/hal/boards/MAPLEMINI_STM32_F103/board.c
@@ -0,0 +1,49 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/MAPLEMINI_STM32_F103/board.h b/os/hal/boards/MAPLEMINI_STM32_F103/board.h
new file mode 100644
index 000000000..977a54bb7
--- /dev/null
+++ b/os/hal/boards/MAPLEMINI_STM32_F103/board.h
@@ -0,0 +1,137 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the LeafLabs Maple Mini.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_MAPLEMINI_STM32_F103
+#define BOARD_NAME              "LeafLabs Maple Mini"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD
+
+/*
+ * IO pins assignments.
+ */
+/* Missing.*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA2  - Alternate output  (USART2 TX).
+ * PA3  - Normal input      (USART2 RX).
+ * PA9  - Alternate output  (USART1 TX).
+ * PA10 - Normal input      (USART1 RX).
+ */
+#define VAL_GPIOACRL            0x88884B88      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x888884B8      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB1  - Push Pull output  (LED).
+ */
+#define VAL_GPIOBCRL            0x88888838      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x88888888      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOCCRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x88888888      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0  - Normal input (XTAL).
+ * PD1  - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL            0x88888844      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x88888888      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x88888888      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/MAPLEMINI_STM32_F103/board.mk b/os/hal/boards/MAPLEMINI_STM32_F103/board.mk
new file mode 100644
index 000000000..b0a16f987
--- /dev/null
+++ b/os/hal/boards/MAPLEMINI_STM32_F103/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/MAPLEMINI_STM32_F103/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/MAPLEMINI_STM32_F103
diff --git a/os/hal/boards/NGX_BB_LPC11U14/board.c b/os/hal/boards/NGX_BB_LPC11U14/board.c
new file mode 100644
index 000000000..690cc0e8b
--- /dev/null
+++ b/os/hal/boards/NGX_BB_LPC11U14/board.c
@@ -0,0 +1,60 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+  {VAL_GPIO0DATA, VAL_GPIO0DIR},
+  {VAL_GPIO1DATA, VAL_GPIO1DIR}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+__inline void __early_init(void) {
+
+  lpc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+__inline void boardInit(void) {
+
+  /* LCD */
+  LPC_IOCON->TMS_PIO0_12  = 0x91;       /* LCD_EN: GPIO - pull-up     */
+  LPC_IOCON->TDO_PIO0_13  = 0x81;       /* LCD_RW: GPIO - No pull-up  */
+  LPC_IOCON->TRST_PIO0_14 = 0x81;       /* LCD_RS: GPIO - No pull-up  */
+
+  /* USART */
+  LPC_IOCON->PIO0_18 = 0x81;            /* RDX: RXD - No pull-up      */
+  LPC_IOCON->PIO0_19 = 0x81;            /* TDX: TXD - No pull-up      */
+
+  /* Test LEDs */
+  LPC_IOCON->PIO0_22 = 0x80;            /* LED_TEST1: GPIO - No pull-up */
+  LPC_IOCON->PIO0_23 = 0x80;            /* LED_TEST2: GPIO - No pull-up */
+
+}
+
diff --git a/os/hal/boards/NGX_BB_LPC11U14/board.h b/os/hal/boards/NGX_BB_LPC11U14/board.h
new file mode 100644
index 000000000..9a59a9c44
--- /dev/null
+++ b/os/hal/boards/NGX_BB_LPC11U14/board.h
@@ -0,0 +1,125 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for NGX BlueBoard LPC11U14.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_NGX_BB_LPC11U14
+#define BOARD_NAME "NGX BlueBoard LPC11U14"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+
+/*
+ * Pin definitions.
+ */
+ 
+/* GPIO Port0 */
+#define BUTTON_ISP_PORT       GPIO0
+#define BUTTON_ISP            1
+
+#define LCD_ERD_PORT          GPIO0
+#define LCD_ERD               12
+
+#define LCD_RWR_PORT          GPIO0
+#define LCD_RWR               13
+
+#define LCD_RS_PORT           GPIO0
+#define LCD_RS                14
+
+#define LED_PORT              GPIO0
+#define LED_TEST1             22
+#define LED_TEST2             23
+
+/* GPIO Port1 */
+#define LCD_RST_PORT          GPIO1
+#define LCD_RST               0
+
+#define LCD_CS_PORT           GPIO1
+#define LCD_CS                13
+
+#define LCD_BL_PORT           GPIO1
+#define LCD_BL                14
+#define LCD_VCCEN_PORT        GPIO1
+#define LCD_VCCEN             14
+
+#define WHEEL_SENSOR_PORT     GPIO0
+#define WHEEL_SENSOR          21
+
+#define LCD_DATA_PORT         GPIO1
+#define LCD_D0                19
+#define LCD_D1                20
+#define LCD_D2                21
+#define LCD_D3                22
+#define LCD_D4                26
+#define LCD_D5                27
+#define LCD_D6                28
+#define LCD_D7                31
+
+#define LCD_DATA_MASK           PAL_PORT_BIT(LCD_D0)  | \
+                                PAL_PORT_BIT(LCD_D1)  | \
+                                PAL_PORT_BIT(LCD_D2)  | \
+                                PAL_PORT_BIT(LCD_D3)  | \
+                                PAL_PORT_BIT(LCD_D4)  | \
+                                PAL_PORT_BIT(LCD_D5)  | \
+                                PAL_PORT_BIT(LCD_D6)  | \
+                                PAL_PORT_BIT(LCD_D7)
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(LCD_ERD)   | \
+                                PAL_PORT_BIT(LCD_RWR)   | \
+                                PAL_PORT_BIT(LCD_RS)    | \
+                                PAL_PORT_BIT(LED_TEST1) | \
+                                PAL_PORT_BIT(LED_TEST2)
+                                
+#define VAL_GPIO0DATA           PAL_PORT_BIT(LCD_ERD)   | \
+                                PAL_PORT_BIT(LCD_RWR)   | \
+                                PAL_PORT_BIT(LED_TEST1) | \
+                                PAL_PORT_BIT(LED_TEST2)
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(LCD_RST) | \
+                                PAL_PORT_BIT(LCD_CS)  | \
+                                PAL_PORT_BIT(LCD_BL)  | \
+                                LCD_DATA_MASK
+                                
+#define VAL_GPIO1DATA           0x00000000
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
diff --git a/os/hal/boards/NGX_BB_LPC11U14/board.mk b/os/hal/boards/NGX_BB_LPC11U14/board.mk
new file mode 100644
index 000000000..6e52eb45d
--- /dev/null
+++ b/os/hal/boards/NGX_BB_LPC11U14/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/NGX_BB_LPC11U14/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/NGX_BB_LPC11U14
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c
new file mode 100644
index 000000000..852598ab5
--- /dev/null
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c
@@ -0,0 +1,82 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
+
+#if HAL_USE_SDC
+/**
+ * @brief   Insertion monitor function.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  return !palReadPad(GPIOE, GPIOE_SDIO_DETECT);
+}
+
+/**
+ * @brief   Protection detection.
+ * @note    Not supported, always not protected.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h
new file mode 100644
index 000000000..a51044f61
--- /dev/null
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h
@@ -0,0 +1,520 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F4-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_NONSTANDARD_STM32F4_BARTHESS1
+#define BOARD_NAME              "Hand made STM32F4x board"
+
+/*
+ * Board frequencies.
+ * NOTE: The LSE crystal is not fitted by default on the board.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD               300
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F40_41xxx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_USART2_CTS        0 /* xbee */
+#define GPIOA_USART2_RTS        1 /* xbee */
+#define GPIOA_USART2_TX         2 /* xbee */
+#define GPIOA_USART2_RX         3 /* xbee */
+#define GPIOA_SPI1_NSS          4
+#define GPIOA_SPI1_SCK          5
+#define GPIOA_SPI1_MISO         6
+#define GPIOA_SPI1_MOSI         7
+#define GPIOA_5V_DOMAIN_EN      8
+#define GPIOA_USART1_TX         9 /* gps */
+#define GPIOA_USART1_RX         10/* gps */
+#define GPIOA_OTG_FS_DM         11
+#define GPIOA_OTG_FS_DP         12
+#define GPIOA_JTMS              13
+#define GPIOA_JTCK              14
+#define GPIOA_JTDI              15
+
+#define GPIOB_RECEIVER_PPM      0
+#define GPIOB_TACHOMETER        1
+#define GPIOB_BOOT1             2
+#define GPIOB_JTDO              3
+#define GPIOB_NJTRST            4
+#define GPIOB_LED_R             6
+#define GPIOB_LED_G             7
+#define GPIOB_LED_B             8
+#define GPIOB_I2C2_SCL          10
+#define GPIOB_I2C2_SDA          11
+
+
+#define GPIOC_AN_CURRENT_SENS   0
+#define GPIOC_AN_SUPPLY_SENS    1
+#define GPIOC_AN_6V_SENS        2
+#define GPIOC_AN33_0            3
+#define GPIOC_AN33_1            4
+#define GPIOC_AN33_2            5
+#define GPIOC_SDIO_D0           8
+#define GPIOC_SDIO_D1           9
+#define GPIOC_SDIO_D2           10
+#define GPIOC_SDIO_D3           11
+#define GPIOC_SDIO_CK           12
+#define GPIOC_TAMPER_RTC        13
+#define GPIOC_OSC32_IN          14
+#define GPIOC_OSC32_OUT         15
+
+#define GPIOD_SDIO_CMD          2
+#define GPIOD_PWM1              12
+#define GPIOD_PWM2              13
+#define GPIOD_PWM3              14
+#define GPIOD_PWM4              15
+
+#define GPIOE_GPS_PPS           0
+#define GPIOE_XBEE_SLEEP        1
+#define GPIOE_XBEE_RESET        2
+#define GPIOE_SDIO_DETECT       3
+#define GPIOE_USB_DISCOVERY     4
+#define GPIOE_GPS_PWR_EN        5
+#define GPIOE_BMP085_EOC        6
+#define GPIOE_MAG_INT           7
+#define GPIOE_MMA8451_INT1      8
+#define GPIOE_PWM5              9
+#define GPIOE_ITG3200_INT       10
+#define GPIOE_PWM6              11
+#define GPIOE_PWM7              13
+#define GPIOE_PWM8              14
+#define GPIOE_MMA8451_INT2      15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ *
+ * 1 for open drain outputs denotes hi-Z state
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUDR_FLOATING(n)        (0U << ((n) * 2))
+#define PIN_PUDR_PULLUP(n)          (1U << ((n) * 2))
+#define PIN_PUDR_PULLDOWN(n)        (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * Port A setup.
+ * All input with pull-up except:
+#define GPIOA_USART2_CTS        0 //xbee
+#define GPIOA_USART2_RTS        1 //xbee
+#define GPIOA_USART2_TX         2 //xbee
+#define GPIOA_USART2_Rx         3 //xbee
+#define GPIOA_SPI1_NSS          4
+#define GPIOA_SPI1_SCK          5
+#define GPIOA_SPI1_MISO         6
+#define GPIOA_SPI1_MOSI         7
+#define GPIOA_5V_DOMAIN_EN      8
+#define GPIOA_USART1_TX         9
+#define GPIOA_USART1_RX         10
+#define GPIOA_OTG_FS_DM         11
+#define GPIOA_OTG_FS_DP         12
+#define GPIOA_JTMS              13
+#define GPIOA_JTCK              14
+#define GPIOA_JTDI              15
+ */
+
+/* default after reset 0xA8000000 */
+#define VAL_GPIOA_MODER        (PIN_MODE_ALTERNATE(GPIOA_USART2_CTS) |        \
+                                PIN_MODE_ALTERNATE(GPIOA_USART2_RTS) |        \
+                                PIN_MODE_ALTERNATE(GPIOA_USART2_TX) |         \
+                                PIN_MODE_ALTERNATE(GPIOA_USART2_RX) |         \
+                                PIN_MODE_ALTERNATE(GPIOA_SPI1_NSS) |          \
+                                PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) |          \
+                                PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) |         \
+                                PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) |         \
+                                PIN_MODE_OUTPUT(GPIOA_5V_DOMAIN_EN) |         \
+                                PIN_MODE_ALTERNATE(GPIOA_USART1_TX) |         \
+                                PIN_MODE_ALTERNATE(GPIOA_USART1_RX) |         \
+                                PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |         \
+                                PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |         \
+                                PIN_MODE_ALTERNATE(GPIOA_JTMS) |              \
+                                PIN_MODE_ALTERNATE(GPIOA_JTCK) |              \
+                                PIN_MODE_ALTERNATE(GPIOA_JTDI))
+/* default 0x00000000 */
+#define VAL_GPIOA_OTYPER        0x00000000
+/* default 0x00000000 */
+#define VAL_GPIOA_OSPEEDR       0x00000000
+/* 0x64000000 */
+#define VAL_GPIOA_PUPDR        (PIN_PUDR_FLOATING(GPIOA_USART2_CTS) |         \
+                                PIN_PUDR_FLOATING(GPIOA_USART2_RTS) |         \
+                                PIN_PUDR_FLOATING(GPIOA_USART2_TX) |          \
+                                PIN_PUDR_FLOATING(GPIOA_USART2_RX) |          \
+                                PIN_PUDR_PULLUP(GPIOA_SPI1_NSS) |             \
+                                PIN_PUDR_PULLUP(GPIOA_SPI1_SCK) |             \
+                                PIN_PUDR_PULLUP(GPIOA_SPI1_MISO) |            \
+                                PIN_PUDR_PULLUP(GPIOA_SPI1_MOSI) |            \
+                                PIN_PUDR_FLOATING(GPIOA_5V_DOMAIN_EN) |       \
+                                PIN_PUDR_FLOATING(GPIOA_USART1_TX) |          \
+                                PIN_PUDR_FLOATING(GPIOA_USART1_RX) |          \
+                                PIN_PUDR_FLOATING(GPIOA_OTG_FS_DM) |          \
+                                PIN_PUDR_FLOATING(GPIOA_OTG_FS_DP) |          \
+                                PIN_PUDR_PULLUP(GPIOA_JTMS) |                 \
+                                PIN_PUDR_PULLDOWN(GPIOA_JTCK) |               \
+                                PIN_PUDR_PULLUP(GPIOA_JTDI))
+/* 0x00000000 */
+#define VAL_GPIOA_ODR           0x00000000
+/* 0x00000000 */
+#define VAL_GPIOA_AFRL         (PIN_AFIO_AF(GPIOA_USART2_CTS, 7) |            \
+                                PIN_AFIO_AF(GPIOA_USART2_RTS, 7) |            \
+                                PIN_AFIO_AF(GPIOA_USART2_TX, 7) |             \
+                                PIN_AFIO_AF(GPIOA_USART2_RX, 7)|              \
+                                PIN_AFIO_AF(GPIOA_SPI1_NSS, 5) |              \
+                                PIN_AFIO_AF(GPIOA_SPI1_SCK, 5) |              \
+                                PIN_AFIO_AF(GPIOA_SPI1_MISO, 5) |             \
+                                PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5))
+/* 0x00000000 */
+#define VAL_GPIOA_AFRH         (PIN_AFIO_AF(GPIOA_USART1_TX, 7) |             \
+                                PIN_AFIO_AF(GPIOA_USART1_RX, 7) |             \
+                                PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) |            \
+                                PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) |            \
+                                PIN_AFIO_AF(GPIOA_JTMS, 0) |                  \
+                                PIN_AFIO_AF(GPIOA_JTCK, 0) |                  \
+                                PIN_AFIO_AF(GPIOA_JTDI, 0))
+
+/*
+ * Port B setup.
+#define GPIOB_RECEIVER_PPM      0
+#define GPIOB_TACHOMETER        1
+#define GPIOB_BOOT1             2
+#define GPIOB_JTDO              3
+#define GPIOB_NJTRST            4
+#define GPIOB_LED_R             6
+#define GPIOB_LED_G             7
+#define GPIOB_LED_B             8
+#define GPIOB_I2C2_SCL          10
+#define GPIOB_I2C2_SDA          11
+ */
+/* 0x00000280 */
+#define VAL_GPIOB_MODER        (PIN_MODE_INPUT(GPIOB_RECEIVER_PPM) |          \
+                                PIN_MODE_INPUT(GPIOB_TACHOMETER) |            \
+                                PIN_MODE_INPUT(GPIOB_BOOT1) |                 \
+                                PIN_MODE_ALTERNATE(GPIOB_JTDO) |              \
+                                PIN_MODE_ALTERNATE(GPIOB_NJTRST) |            \
+                                PIN_MODE_INPUT(5) |                           \
+                                PIN_MODE_OUTPUT(GPIOB_LED_R) |                \
+                                PIN_MODE_OUTPUT(GPIOB_LED_G) |                \
+                                PIN_MODE_OUTPUT(GPIOB_LED_B) |                \
+                                PIN_MODE_INPUT(9) |                           \
+                                PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) |          \
+                                PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) |          \
+                                PIN_MODE_INPUT(12) |                          \
+                                PIN_MODE_INPUT(13) |                          \
+                                PIN_MODE_INPUT(14) |                          \
+                                PIN_MODE_INPUT(15))
+/* 0x00000000 */
+#define VAL_GPIOB_OTYPER       (PIN_OTYPE_OPENDRAIN(GPIOB_LED_R) |            \
+                                PIN_OTYPE_OPENDRAIN(GPIOB_LED_G) |            \
+                                PIN_OTYPE_OPENDRAIN(GPIOB_LED_B) |            \
+                                PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) |         \
+                                PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA))
+/* 0x000000C0 */
+#define VAL_GPIOB_OSPEEDR       0x000000C0//0xAAAAAAEA
+/* 0x00000100 */
+#define VAL_GPIOB_PUPDR        (PIN_PUDR_PULLDOWN(GPIOB_RECEIVER_PPM) |       \
+                                PIN_PUDR_PULLDOWN(GPIOB_TACHOMETER) |         \
+                                PIN_PUDR_FLOATING(GPIOB_BOOT1) |              \
+                                PIN_PUDR_FLOATING(GPIOB_JTDO) |               \
+                                PIN_PUDR_PULLUP(GPIOB_NJTRST) |               \
+                                PIN_PUDR_FLOATING(5) |                        \
+                                PIN_PUDR_FLOATING(GPIOB_LED_R) |              \
+                                PIN_PUDR_FLOATING(GPIOB_LED_G) |              \
+                                PIN_PUDR_FLOATING(GPIOB_LED_B) |              \
+                                PIN_PUDR_FLOATING(9) |                        \
+                                PIN_PUDR_FLOATING(GPIOB_I2C2_SCL) |           \
+                                PIN_PUDR_FLOATING(GPIOB_I2C2_SDA) |           \
+                                PIN_PUDR_PULLUP(12) |                         \
+                                PIN_PUDR_PULLUP(13) |                         \
+                                PIN_PUDR_PULLUP(14) |                         \
+                                PIN_PUDR_PULLUP(15))
+/* 0x00000000 */
+#define VAL_GPIOB_ODR           0x000001C0
+/* 0x00000000 */
+#define VAL_GPIOB_AFRL         (PIN_AFIO_AF(GPIOB_RECEIVER_PPM, 0) |          \
+                                PIN_AFIO_AF(GPIOB_JTDO, 0))
+/* 0x00000000 */
+#define VAL_GPIOB_AFRH         (PIN_AFIO_AF(GPIOB_I2C2_SCL, 4) |              \
+                                PIN_AFIO_AF(GPIOB_I2C2_SDA, 4))
+
+
+/*
+ * Port C setup.
+#define GPIOC_AN_CURRENT_SENS   0
+#define GPIOC_AN_SUPPLY_SENS    1
+#define GPIOC_AN_6V_SENS        2
+#define GPIOC_AN33_0            3
+#define GPIOC_AN33_1            4
+#define GPIOC_AN33_2            5
+
+#define GPIOC_SDIO_D0           8
+#define GPIOC_SDIO_D1           9
+#define GPIOC_SDIO_D2           10
+#define GPIOC_SDIO_D3           11
+#define GPIOC_SDIO_CK           12
+
+#define GPIOC_TAMPER_RTC        13
+#define GPIOC_OSC32_IN          14
+#define GPIOC_OSC32_OUT         15
+ */
+/* 0x00000000 */
+#define VAL_GPIOC_MODER        (PIN_MODE_ANALOG(GPIOC_AN_CURRENT_SENS) |      \
+                                PIN_MODE_ANALOG(GPIOC_AN_SUPPLY_SENS) |       \
+                                PIN_MODE_ANALOG(GPIOC_AN_6V_SENS) |           \
+                                PIN_MODE_ANALOG(GPIOC_AN33_0) |               \
+                                PIN_MODE_ANALOG(GPIOC_AN33_1) |               \
+                                PIN_MODE_ANALOG(GPIOC_AN33_2) |               \
+                                PIN_MODE_INPUT(6) |                           \
+                                PIN_MODE_INPUT(7) |                           \
+                                PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) |           \
+                                PIN_MODE_ALTERNATE(GPIOC_SDIO_D1) |           \
+                                PIN_MODE_ALTERNATE(GPIOC_SDIO_D2) |           \
+                                PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) |           \
+                                PIN_MODE_ALTERNATE(GPIOC_SDIO_CK) |           \
+                                PIN_MODE_INPUT(GPIOC_TAMPER_RTC) |            \
+                                PIN_MODE_INPUT(GPIOC_OSC32_IN) |              \
+                                PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+
+/* 0x00000000 */
+#define VAL_GPIOC_OTYPER        0x00000000
+/* 0x00000000 */
+#define VAL_GPIOC_OSPEEDR      (PIN_OSPEED_25M(GPIOC_SDIO_D0) |               \
+                                PIN_OSPEED_25M(GPIOC_SDIO_D1) |               \
+                                PIN_OSPEED_25M(GPIOC_SDIO_D2) |               \
+                                PIN_OSPEED_25M(GPIOC_SDIO_D3) |               \
+                                PIN_OSPEED_25M(GPIOC_SDIO_CK) |               \
+                                PIN_OSPEED_2M(GPIOC_TAMPER_RTC))
+/* 0x00000000 */
+#define VAL_GPIOC_PUPDR        (PIN_PUDR_FLOATING(GPIOC_AN_CURRENT_SENS) |    \
+                                PIN_PUDR_FLOATING(GPIOC_AN_SUPPLY_SENS) |     \
+                                PIN_PUDR_FLOATING(GPIOC_AN_6V_SENS) |         \
+                                PIN_PUDR_FLOATING(GPIOC_AN33_0) |             \
+                                PIN_PUDR_FLOATING(GPIOC_AN33_1) |             \
+                                PIN_PUDR_FLOATING(GPIOC_AN33_2) |             \
+                                PIN_PUDR_PULLUP(6) |                          \
+                                PIN_PUDR_PULLUP(7) |                          \
+                                PIN_PUDR_PULLUP(GPIOC_SDIO_D0) |              \
+                                PIN_PUDR_PULLUP(GPIOC_SDIO_D1) |              \
+                                PIN_PUDR_PULLUP(GPIOC_SDIO_D2) |              \
+                                PIN_PUDR_PULLUP(GPIOC_SDIO_D3) |              \
+                                PIN_PUDR_PULLUP(GPIOC_SDIO_CK) |              \
+                                PIN_PUDR_FLOATING(GPIOC_TAMPER_RTC) |         \
+                                PIN_PUDR_FLOATING(GPIOC_OSC32_IN) |           \
+                                PIN_PUDR_FLOATING(GPIOC_OSC32_OUT))
+/* 0x00000000 */
+#define VAL_GPIOC_ODR           0x00000000
+/* 0x00000000 */
+#define VAL_GPIOC_AFRL          0x00000000
+/* 0x00000000 */
+#define VAL_GPIOC_AFRH         (PIN_AFIO_AF(GPIOC_SDIO_D0, 12) |              \
+                                PIN_AFIO_AF(GPIOC_SDIO_D1, 12) |              \
+                                PIN_AFIO_AF(GPIOC_SDIO_D2, 12) |              \
+                                PIN_AFIO_AF(GPIOC_SDIO_D3, 12) |              \
+                                PIN_AFIO_AF(GPIOC_SDIO_CK, 12))
+
+/*
+ * Port D setup.
+#define GPIOD_SDIO_CMD          2
+#define GPIOD_PWM1              12
+#define GPIOD_PWM2              13
+#define GPIOD_PWM3              14
+#define GPIOD_PWM4              15
+ */
+/* 0x00000000 */
+#define VAL_GPIOD_MODER        (PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) |          \
+                                PIN_MODE_ALTERNATE(GPIOD_PWM1) |              \
+                                PIN_MODE_ALTERNATE(GPIOD_PWM2) |              \
+                                PIN_MODE_ALTERNATE(GPIOD_PWM3) |              \
+                                PIN_MODE_ALTERNATE(GPIOD_PWM4))
+/* 0x00000000 */
+#define VAL_GPIOD_OTYPER        0x00000000
+/* 0x00000000 */
+#define VAL_GPIOD_OSPEEDR      (PIN_OSPEED_25M(GPIOD_SDIO_CMD))
+/* 0x00000000 */
+#define VAL_GPIOD_PUPDR        (PIN_PUDR_PULLUP(GPIOD_SDIO_CMD) |             \
+                                PIN_PUDR_PULLDOWN(GPIOD_PWM1) |               \
+                                PIN_PUDR_PULLDOWN(GPIOD_PWM2) |               \
+                                PIN_PUDR_PULLDOWN(GPIOD_PWM3) |               \
+                                PIN_PUDR_PULLDOWN(GPIOD_PWM4))
+/* 0x00000000 */
+#define VAL_GPIOD_ODR           0x00000000
+/* 0x00000000 */
+#define VAL_GPIOD_AFRL         (PIN_AFIO_AF(GPIOD_SDIO_CMD, 12))
+/* 0x00000000 */
+#define VAL_GPIOD_AFRH         (PIN_AFIO_AF(GPIOD_PWM1, 2) |                  \
+                                PIN_AFIO_AF(GPIOD_PWM2, 2) |                  \
+                                PIN_AFIO_AF(GPIOD_PWM3, 2) |                  \
+                                PIN_AFIO_AF(GPIOD_PWM4, 2))
+
+
+/*
+ * Port E setup.
+#define GPIOE_GPS_PPS           0
+#define GPIOE_XBEE_SLEEP        1
+#define GPIOE_XBEE_RESET        2
+#define GPIOE_SDIO_DETECT       3
+#define GPIOE_USB_DISCOVERY     4
+#define GPIOE_GPS_EN            5
+#define GPIOE_BMP085_EOC        6
+#define GPIOE_MAG_INT           7
+#define GPIOE_MMA8451_INT1      8
+#define GPIOE_PWM5              9
+#define GPIOE_ITG3200_INT       10
+#define GPIOE_PWM6              11
+#define GPIOE_TACHOMETER        12
+#define GPIOE_PWM7              13
+#define GPIOE_PWM8              14
+#define GPIOE_MMA8451_INT2      15
+ */
+/* 0x00000000 */
+#define VAL_GPIOE_MODER        (PIN_MODE_INPUT(GPIOE_GPS_PPS) |               \
+                                PIN_MODE_OUTPUT(GPIOE_XBEE_SLEEP) |           \
+                                PIN_MODE_OUTPUT(GPIOE_XBEE_RESET) |           \
+                                PIN_MODE_INPUT(GPIOE_SDIO_DETECT) |           \
+                                PIN_MODE_OUTPUT(GPIOE_USB_DISCOVERY) |        \
+                                PIN_MODE_OUTPUT(GPIOE_GPS_PWR_EN) |           \
+                                PIN_MODE_INPUT(GPIOE_BMP085_EOC) |            \
+                                PIN_MODE_INPUT(GPIOE_MAG_INT) |               \
+                                PIN_MODE_INPUT(GPIOE_MMA8451_INT1) |          \
+                                PIN_MODE_ALTERNATE(GPIOE_PWM5) |              \
+                                PIN_MODE_INPUT(GPIOE_ITG3200_INT) |           \
+                                PIN_MODE_ALTERNATE(GPIOE_PWM6) |              \
+                                PIN_MODE_INPUT(12) |                          \
+                                PIN_MODE_ALTERNATE(GPIOE_PWM7) |              \
+                                PIN_MODE_ALTERNATE(GPIOE_PWM8) |              \
+                                PIN_MODE_INPUT(GPIOE_MMA8451_INT2))
+/* 0x00000000 */
+#define VAL_GPIOE_OTYPER       (PIN_OTYPE_PUSHPULL(GPIOE_XBEE_SLEEP) |        \
+                                PIN_OTYPE_PUSHPULL(GPIOE_XBEE_RESET) |        \
+                                PIN_OTYPE_PUSHPULL(GPIOE_USB_DISCOVERY) |     \
+                                PIN_OTYPE_OPENDRAIN(GPIOE_GPS_PWR_EN) |       \
+                                PIN_OTYPE_PUSHPULL(GPIOE_PWM5) |              \
+                                PIN_OTYPE_PUSHPULL(GPIOE_PWM6) |              \
+                                PIN_OTYPE_PUSHPULL(GPIOE_PWM7) |              \
+                                PIN_OTYPE_PUSHPULL(GPIOE_PWM8))
+/* 0x00000000 */
+#define VAL_GPIOE_OSPEEDR       0x00000000
+/* 0x00000000 */
+#define VAL_GPIOE_PUPDR        (PIN_PUDR_PULLDOWN(GPIOE_GPS_PPS) |            \
+                                PIN_PUDR_PULLUP(GPIOE_XBEE_SLEEP) |           \
+                                PIN_PUDR_FLOATING(GPIOE_XBEE_RESET) |         \
+                                PIN_PUDR_PULLUP(GPIOE_SDIO_DETECT) |          \
+                                PIN_PUDR_FLOATING(GPIOE_USB_DISCOVERY) |      \
+                                PIN_PUDR_FLOATING(GPIOE_GPS_PWR_EN) |         \
+                                PIN_PUDR_PULLDOWN(GPIOE_BMP085_EOC) |         \
+                                PIN_PUDR_PULLDOWN(GPIOE_MAG_INT) |            \
+                                PIN_PUDR_PULLDOWN(GPIOE_MMA8451_INT1) |       \
+                                PIN_PUDR_PULLDOWN(GPIOE_PWM5) |               \
+                                PIN_PUDR_PULLDOWN(GPIOE_ITG3200_INT) |        \
+                                PIN_PUDR_PULLDOWN(GPIOE_PWM6) |               \
+                                PIN_PUDR_PULLUP(12) |                         \
+                                PIN_PUDR_PULLDOWN(GPIOE_PWM7) |               \
+                                PIN_PUDR_PULLDOWN(GPIOE_PWM8) |               \
+                                PIN_PUDR_PULLDOWN(GPIOE_MMA8451_INT2))
+/* 0x00000000 */
+#define VAL_GPIOE_ODR           0x30
+/* 0x00000000 */
+#define VAL_GPIOE_AFRL          0x00000000
+/* 0x00000000 */
+#define VAL_GPIOE_AFRH         (PIN_AFIO_AF(GPIOE_PWM5, 1) |                  \
+                                PIN_AFIO_AF(GPIOE_PWM6, 1) |                  \
+                                PIN_AFIO_AF(GPIOE_PWM7, 1) |                  \
+                                PIN_AFIO_AF(GPIOE_PWM8, 1))
+
+/*
+ * Port F setup.
+ */
+#define VAL_GPIOF_MODER             0x00000000
+#define VAL_GPIOF_OTYPER            0x00000000
+#define VAL_GPIOF_OSPEEDR           0x00000000
+#define VAL_GPIOF_PUPDR             0x00000000
+#define VAL_GPIOF_ODR               0x00000000
+#define VAL_GPIOF_AFRL              0x00000000
+#define VAL_GPIOF_AFRH              0x00000000
+
+/*
+ * Port G setup.
+ */
+#define VAL_GPIOG_MODER             0x00000000
+#define VAL_GPIOG_OTYPER            0x00000000
+#define VAL_GPIOG_OSPEEDR           0x00000000
+#define VAL_GPIOG_PUPDR             0x00000000
+#define VAL_GPIOG_ODR               0x00000000
+#define VAL_GPIOG_AFRL              0x00000000
+#define VAL_GPIOG_AFRH              0x00000000
+
+/*
+ * Port H setup.
+ */
+#define VAL_GPIOH_MODER             0x00000000
+#define VAL_GPIOH_OTYPER            0x00000000
+#define VAL_GPIOH_OSPEEDR           0x00000000
+#define VAL_GPIOH_PUPDR             0x00000000
+#define VAL_GPIOH_ODR               0x00000000
+#define VAL_GPIOH_AFRL              0x00000000
+#define VAL_GPIOH_AFRH              0x00000000
+
+/*
+ * Port I setup.
+ */
+#define VAL_GPIOI_MODER             0x00000000
+#define VAL_GPIOI_OTYPER            0x00000000
+#define VAL_GPIOI_OSPEEDR           0x00000000
+#define VAL_GPIOI_PUPDR             0x00000000
+#define VAL_GPIOI_ODR               0x00000000
+#define VAL_GPIOI_AFRL              0x00000000
+#define VAL_GPIOI_AFRH              0x00000000
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk
new file mode 100644
index 000000000..fe33d03fd
--- /dev/null
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1
diff --git a/os/hal/boards/OLIMEX_AVR_CAN/board.c b/os/hal/boards/OLIMEX_AVR_CAN/board.c
new file mode 100644
index 000000000..9d379b08d
--- /dev/null
+++ b/os/hal/boards/OLIMEX_AVR_CAN/board.c
@@ -0,0 +1,89 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+  {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+  {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+  {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+  {VAL_PORTG, VAL_DDRG},
+#endif
+};
+#endif /* HAL_USE_PAL */
+
+CH_IRQ_HANDLER(TIMER0_COMP_vect) {
+
+  CH_IRQ_PROLOGUE();
+
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EICRB  = 0x00;
+  EIMSK  = 0x00;
+
+  /*
+   * Enables Idle mode for SLEEP instruction.
+   */
+  SMCR   = (1 << SE);
+
+  /*
+   * Timer 0 setup.
+   */
+  TCCR0A = (1 << WGM01)  | (0 << WGM00)  |              /* CTC mode.        */
+           (0 << COM0A1) | (0 << COM0A0) |              /* OC0A disabled.   */
+           (0 << CS02)   | (1 << CS01)   | (1 << CS00); /* CLK/64 clock.    */
+  OCR0A  = F_CPU / 64 / CH_FREQUENCY - 1;
+  TCNT0  = 0;                                           /* Reset counter.   */
+  TIFR0  = (1 << OCF0A);                                /* Reset pending.   */
+  TIMSK0 = (1 << OCIE0A);                               /* IRQ on compare.  */
+}
diff --git a/os/hal/boards/OLIMEX_AVR_CAN/board.h b/os/hal/boards/OLIMEX_AVR_CAN/board.h
new file mode 100644
index 000000000..4d674756e
--- /dev/null
+++ b/os/hal/boards/OLIMEX_AVR_CAN/board.h
@@ -0,0 +1,99 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex AVR-CAN proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_AVR_CAN
+#define BOARD_NAME "Olimex AVR-CAN"
+
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRA  0x00
+#define VAL_PORTA 0xFF
+
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRB  0x00
+#define VAL_PORTB 0xFF
+
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRC  0x00
+#define VAL_PORTC 0xFF
+
+/*       PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
+ *        IN  IN OUT  IN OUT  IN  IN  IN
+ * DDRD    0   0   1   0   1   0   0   0
+ *        PU HiZ VAL  PU VAL HiZ HiZ HiZ
+ * PORTD   1   0  ?1   1   1   0   0   0
+ */
+#define VAL_DDRD  0x28
+#define VAL_PORTD 0xB8
+
+/*       PE7 PE6 BUT LED PE3 PE2 PE1 PE0
+ *        IN  IN  IN OUT  IN  IN OUT  IN
+ * DDRE    0   0   0   1   0   0   1   0
+ *        PU  PU HiZ VAL  PU  PU VAL HiZ
+ * PORTE   1   1   0   1   1   1   1   0
+ */
+#define VAL_DDRE  0x12
+#define VAL_PORTE 0xDE
+
+/*       TDI TDO TMS TCK PF3 PF2 PF1 PF0
+ *         x   x   x   x  IN  IN  IN  IN
+ * DDRF    0   0   0   0   0   0   0   0
+ *         x   x   x   x  PU  PU  PU  PU
+ * PORTF   0   0   0   0   1   1   1   1
+ *
+ */
+#define VAL_DDRF  0x00
+#define VAL_PORTF 0x0F
+
+/*         x   x   x   x   x PG2 PG1 PG0
+ *         x   x   x   x   x  IN  IN  IN
+ * DDRG    0   0   0   0   0   0   0   0
+ *         x   x   x   x   x  PU  PU  PU
+ * PORTG   0   0   0   0   0   1   1   1
+ *
+ */
+#define VAL_DDRG  0x00
+#define VAL_PORTG 0x07
+
+#define PORTE_LED               4
+#define PORTE_BUTTON            5
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_AVR_CAN/board.mk b/os/hal/boards/OLIMEX_AVR_CAN/board.mk
new file mode 100644
index 000000000..e80cd2771
--- /dev/null
+++ b/os/hal/boards/OLIMEX_AVR_CAN/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_AVR_CAN/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_AVR_CAN
diff --git a/os/hal/boards/OLIMEX_AVR_MT_128/board.c b/os/hal/boards/OLIMEX_AVR_MT_128/board.c
new file mode 100644
index 000000000..ee181fe75
--- /dev/null
+++ b/os/hal/boards/OLIMEX_AVR_MT_128/board.c
@@ -0,0 +1,92 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+  {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+  {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+  {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+  {VAL_PORTG, VAL_DDRG},
+#endif
+};
+#endif /* HAL_USE_PAL */
+
+/**
+ * @brief   Timer0 interrupt handler.
+ */
+CH_IRQ_HANDLER(TIMER0_COMP_vect) {
+
+  CH_IRQ_PROLOGUE();
+
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EICRB  = 0x00;
+  EIMSK  = 0x00;
+
+  /*
+   * Enables Idle mode for SLEEP instruction.
+   */
+  MCUCR  = (1 << SE);
+
+  /*
+   * Timer 0 setup.
+   */
+  TCCR0  = (1 << WGM01) | (0 << WGM00) |                /* CTC mode.        */
+           (0 << COM01) | (0 << COM00) |                /* OC0A disabled.   */
+           (1 << CS02)  | (0 << CS01)  | (0 << CS00);   /* CLK/64 clock.    */
+  OCR0   = F_CPU / 64 / CH_FREQUENCY - 1;
+  TCNT0  = 0;                                           /* Reset counter.   */
+  TIFR   = (1 << OCF0);                                 /* Reset pending.   */
+  TIMSK  = (1 << OCIE0);                                /* IRQ on compare.  */
+}
diff --git a/os/hal/boards/OLIMEX_AVR_MT_128/board.h b/os/hal/boards/OLIMEX_AVR_MT_128/board.h
new file mode 100644
index 000000000..3c99f9d53
--- /dev/null
+++ b/os/hal/boards/OLIMEX_AVR_MT_128/board.h
@@ -0,0 +1,124 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex AVR-MT-128 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_AVR_MT_128
+#define BOARD_NAME "Olimex AVR-MT-128"
+
+/*       PA7 RLY  DS  B5  B4  B3  B2  B1
+ *        IN OUT  IN  IN  IN  IN  IN  IN
+ * DDRA    0   1   0   0   0   0   0   0
+ *        PU VAL HiZ HiZ HiZ HiZ HiZ HiZ
+ * PORTA   1   0   0   0   0   0   0   0
+ */
+#define VAL_DDRA  0x40
+#define VAL_PORTA 0x80
+
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRB  0x00
+#define VAL_PORTB 0xFF
+
+/*        D7  D6  D5  D4 PC3   E R/W  RS
+ *        OUT OUT OUT OUT IN OUT OUT OUT
+ * DDRC    1   1   1   1   0   1   1   1
+ *        PU  PU  PU  PU  PU VAL VAL VAL
+ * PORTC   0   0   0   0   1   0   0   0
+ */
+#define VAL_DDRC  0xF7
+#define VAL_PORTC 0x08
+
+/*       PD7 PD6 PD5 PD4 TXD RXD PD1 PD0
+ *        IN  IN  IN  IN OUT  IN  IN  IN
+ * DDRD    0   0   0   0   1   0   0   0
+ *        PU  PU  PU  PU VAL HiZ  PU  PU
+ * PORTD   1   1   1   1   1   0   1   1
+ */
+#define VAL_DDRD  0x08
+#define VAL_PORTD 0xFB
+
+/*       PE7 PE6 BZ2 BZ2 PE3 PE2 PE1 PE0
+ *        IN  IN OUT OUT  IN  IN OUT  IN
+ * DDRE    0   0   1   1   0   0   1   0
+ *        PU  PU VAL VAL  PU  PU VAL  PU
+ * PORTE   1   1   1   1   1   1   1   1
+ */
+#define VAL_DDRE  0x32
+#define VAL_PORTE 0xFF
+
+/*       TDI TDO TMS TCK PF3 PF2 PF1 PF0
+ *         x   x   x   x  IN  IN  IN  IN
+ * DDRF    0   0   0   0   0   0   0   0
+ *         x   x   x   x  PU  PU  PU  PU
+ * PORTF   0   0   0   0   1   1   1   1
+ *
+ */
+#define VAL_DDRF  0x00
+#define VAL_PORTF 0x0F
+
+/*         x   x   x   x   x PG2 PG1 PG0
+ *         x   x   x   x   x  IN  IN  IN
+ * DDRG    0   0   0   0   0   0   0   0
+ *         x   x   x   x   x  PU  PU  PU
+ * PORTG   0   0   0   0   0   1   1   1
+ *
+ */
+#define VAL_DDRG  0x00
+#define VAL_PORTG 0x07
+
+
+#define PORTA_BUTTON1           0
+#define PORTA_BUTTON2           1
+#define PORTA_BUTTON3           2
+#define PORTA_BUTTON4           3
+#define PORTA_BUTTON5           4
+#define PORTA_DALLAS            5
+#define PORTA_RELAY             6
+
+#define PORTC_44780_RS_MASK     (1 << 0)
+#define PORTC_44780_RW_MASK     (1 << 1)
+#define PORTC_44780_E_MASK      (1 << 2)
+#define PORTC_44780_D4_MASK     (1 << 4)
+#define PORTC_44780_D5_MASK     (1 << 5)
+#define PORTC_44780_D6_MASK     (1 << 6)
+#define PORTC_44780_D7_MASK     (1 << 7)
+#define PORTC_44780_DATA_MASK   (PORTC_44780_D4_MASK | PORTC_44780_D5_MASK | \
+                                 PORTC_44780_D6_MASK | PORTC_44780_D7_MASK)
+
+#define PORTE_BUZZ1             (1 << 4)
+#define PORTE_BUZZ2             (1 << 5)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_AVR_MT_128/board.mk b/os/hal/boards/OLIMEX_AVR_MT_128/board.mk
new file mode 100644
index 000000000..259dd2730
--- /dev/null
+++ b/os/hal/boards/OLIMEX_AVR_MT_128/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_AVR_MT_128/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_AVR_MT_128
diff --git a/os/hal/boards/OLIMEX_LPC_P1227/board.c b/os/hal/boards/OLIMEX_LPC_P1227/board.c
new file mode 100644
index 000000000..226d696c4
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P1227/board.c
@@ -0,0 +1,53 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  lpc122x_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * Extra, board-specific, initializations.
+   */
+  LPC_IOCON->PIO1_4 = 0x80;             /* Disables pull-up on LED2 output. */
+  LPC_IOCON->PIO1_5 = 0x80;             /* Disables pull-up on LED1 output  */
+  LPC_IOCON->PIO1_6 = 0x80;             /* Disables pull-up on Buzzer output  */
+}
diff --git a/os/hal/boards/OLIMEX_LPC_P1227/board.h b/os/hal/boards/OLIMEX_LPC_P1227/board.h
new file mode 100644
index 000000000..ae2e879a7
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P1227/board.h
@@ -0,0 +1,98 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Olimex LPC-P1227 board.
+ *
+ */
+
+/*
+ * Board identifiers.
+ */
+#define OLIMEX_LPC_P1227
+#define BOARD_NAME "Olimex LPC-P1227"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            0x00000000
+#define VAL_GPIO0DATA           0x00000000
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(GPIO1_LED1)   |                 \
+                                PAL_PORT_BIT(GPIO1_LED2)   |                 \
+                                PAL_PORT_BIT(GPIO1_BUZZER)
+
+#define VAL_GPIO1DATA           PAL_PORT_BIT(GPIO1_LED1)
+
+
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR            PAL_PORT_BIT(GPIO2_LCD_DC)   |               \
+                                PAL_PORT_BIT(GPIO2_LCD_SS)   |               \
+                                PAL_PORT_BIT(GPIO2_LCD_RES)
+#define VAL_GPIO2DATA           PAL_PORT_BIT(GPIO2_LCD_SS)
+
+
+/*
+ * Pin definitions.
+ */
+
+#define GPIO1_LED1              5
+#define GPIO1_LED2              4
+#define GPIO1_SW_WAKEUP         3
+#define GPIO1_BUZZER            6
+
+#define GPIO2_SW_USER1          12
+#define GPIO2_SW_USER2          11
+#define GPIO2_SW_USER3          10
+#define GPIO2_LCD_DC            15
+#define GPIO2_LCD_SS            14
+#define GPIO2_LCD_RES           13
+
+/* LCD3310 pins */
+#define LCD3310_RES_PIN   GPIO2_LCD_RES
+#define LCD3310_RES_PORT  GPIO2
+#define LCD3310_DC_PIN    GPIO2_LCD_DC
+#define LCD3310_DC_PORT   GPIO2
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_LPC_P1227/board.mk b/os/hal/boards/OLIMEX_LPC_P1227/board.mk
new file mode 100644
index 000000000..6d4078802
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P1227/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC-P1227/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC-P1227
diff --git a/os/hal/boards/OLIMEX_LPC_P1343/board.c b/os/hal/boards/OLIMEX_LPC_P1343/board.c
new file mode 100644
index 000000000..8a3ca7dd9
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P1343/board.c
@@ -0,0 +1,51 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  LPC13xx_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * Extra, board-specific, initializations.
+   */
+}
diff --git a/os/hal/boards/OLIMEX_LPC_P1343/board.h b/os/hal/boards/OLIMEX_LPC_P1343/board.h
new file mode 100644
index 000000000..ca7934f4d
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P1343/board.h
@@ -0,0 +1,104 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex LPC-P1343 proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_OLIMEX_LPC_P1343
+#define BOARD_NAME "Olimex LPC-P1343"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            0x00000000
+#define VAL_GPIO0DATA           0x00000000
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(GPIO1_SW2)
+
+#define VAL_GPIO1DATA           PAL_PORT_BIT(GPIO1_SW2)
+
+/*
+ * GPIO 2 initial setup.
+ */
+
+#define VAL_GPIO2DIR            PAL_PORT_BIT(GPIO2_SW1)     | \
+                                PAL_PORT_BIT(GPIO2_LED5)    | \
+                                PAL_PORT_BIT(GPIO2_LED6)    | \
+                                PAL_PORT_BIT(GPIO2_LED7)    | \
+                                PAL_PORT_BIT(GPIO2_LED8)
+
+#define VAL_GPIO2DATA           PAL_PORT_BIT(GPIO2_LED5)    | \
+                                PAL_PORT_BIT(GPIO2_LED6)    | \
+                                PAL_PORT_BIT(GPIO2_LED7)    | \
+                                PAL_PORT_BIT(GPIO2_LED8)
+
+/*
+ * GPIO 3 initial setup.
+ */
+
+#define VAL_GPIO3DIR            PAL_PORT_BIT(GPIO3_LED1)    | \
+                                PAL_PORT_BIT(GPIO3_LED2)    | \
+                                PAL_PORT_BIT(GPIO3_LED3)    | \
+                                PAL_PORT_BIT(GPIO3_LED4)
+
+#define VAL_GPIO3DATA           PAL_PORT_BIT(GPIO3_LED1)    | \
+                                PAL_PORT_BIT(GPIO3_LED2)    | \
+                                PAL_PORT_BIT(GPIO3_LED3)    | \
+                                PAL_PORT_BIT(GPIO3_LED4)
+
+/*
+ * Pin definitions.
+ */
+#define GPIO1_SW2               4
+#define GPIO1_SPI0SEL           11
+
+#define GPIO2_SW1               9
+
+#define GPIO3_LED1              0
+#define GPIO3_LED2              1
+#define GPIO3_LED3              2
+#define GPIO3_LED4              3
+#define GPIO2_LED5              4
+#define GPIO2_LED6              5
+#define GPIO2_LED7              6
+#define GPIO2_LED8              7
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_LPC_P1343/board.mk b/os/hal/boards/OLIMEX_LPC_P1343/board.mk
new file mode 100644
index 000000000..c8ec923d6
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P1343/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC_P1343/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC_P1343
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/board.c b/os/hal/boards/OLIMEX_LPC_P2148/board.c
new file mode 100644
index 000000000..67d6294be
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P2148/board.c
@@ -0,0 +1,94 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#define VAL_TC0_PRESCALER 0
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  VAL_PINSEL0,
+  VAL_PINSEL1,
+  VAL_PINSEL2,
+  {VAL_FIO0PIN, VAL_FIO0DIR},
+  {VAL_FIO1PIN, VAL_FIO1DIR}
+};
+#endif
+
+/*
+ * Timer 0 IRQ handling here.
+ */
+static CH_IRQ_HANDLER(T0IrqHandler) {
+
+  CH_IRQ_PROLOGUE();
+  T0IR = 1;             /* Clear interrupt on match MR0. */
+
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+
+  VICVectAddr = 0;
+  CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  lpc214x_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return !palReadPad(IOPORT2, PB_CP1);
+}
+
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return palReadPad(IOPORT2, PB_WP1);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * System Timer initialization, 1ms intervals.
+   */
+  SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);
+  VICIntEnable = INTMASK(SOURCE_Timer0);
+  TC *timer = T0Base;
+  timer->TC_PR = VAL_TC0_PRESCALER;
+  timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1);
+  timer->TC_MCR = 3;    /* Interrupt and clear TC on match MR0. */
+  timer->TC_TCR = 2;    /* Reset counter and prescaler. */
+  timer->TC_TCR = 1;    /* Timer enabled. */
+}
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/board.h b/os/hal/boards/OLIMEX_LPC_P2148/board.h
new file mode 100644
index 000000000..17651b313
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P2148/board.h
@@ -0,0 +1,92 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex LPC-P2148 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_LPC_P2148
+#define BOARD_NAME "Olimex LPC-P2148"
+
+/*
+ * The following values are implementation dependent. You may change them in
+ * order to match your HW.
+ */
+#define FOSC 12000000
+#define CCLK 48000000
+#define PCLK 12000000
+
+/*
+ * Pins configuration for Olimex LPC-P2148.
+ *
+ * PINSEL0
+ *  P0  P0  P0  P0  P0  P0  RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD
+ *  15  14  13  12  11  10  1   1   L0  I0  O0  0   0   0   0   0
+ *  00  00  00  00  00  00  01  01  01  01  01  01  01  01  01  01
+ * FIO0DIR (15...0)
+ *  IN  IN  OUT OUT OUT OUT --  --  --  --  --  --  --  --  --  --
+ *  0   0   1   1   1   1   0   0   0   0   0   0   0   0   0   0
+ *
+ * PINSEL1
+ *  P0  AD  P0  P0  --  --  AO  --  VB  P0  P0  P0  MOS MIS SCK P0
+ *  31  03  29  28  --  --  UT  --  US  22  21  20  I1  O1  1   16
+ *  00  01  00  00  00  00  10  00  01  00  00  00  10  10  10  00
+ * FIO0DIR (31...16)
+ *  OUT --  OUT OUT --  --  --  --  --  OUT OUT OUT --  --  --  IN
+ *  1   0   1   1   0   0   0   0   0   1   1   1   0   0   0   0
+ *
+ * FIO1DIR (31...16)
+ *  --  --  --  --  --  IN  IN  OUT OUT OUT OUT OUT OUT OUT OUT OUT
+ *  0   0   0   0   0   0   0   1   1   1   1   1   1   1   1   1
+ */
+#define VAL_PINSEL0 0x00055555
+#define VAL_PINSEL1 0x100840A8
+#define VAL_PINSEL2 0x00000004  /* Do not modify */
+#define VAL_FIO0DIR 0xB0703C00
+#define VAL_FIO1DIR 0x01FF0000
+#define VAL_FIO0PIN 0xFFFFFFFF
+#define VAL_FIO1PIN 0xFFFFFFFF
+
+#define PA_LED1         10
+#define PA_LED2         11
+#define PA_BUZZ1        12
+#define PA_BUZZ2        13
+#define PA_BSL          14
+#define PA_BUTTON1      15
+#define PA_BUTTON2      16
+#define PA_SSEL1        20
+#define PA_LEDUSB       31
+
+#define PB_WP1          24
+#define PB_CP1          25
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/board.mk b/os/hal/boards/OLIMEX_LPC_P2148/board.mk
new file mode 100644
index 000000000..29be6a342
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P2148/board.mk
@@ -0,0 +1,5 @@
+# List of all the mandatory board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC_P2148/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC_P2148
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/buzzer.c b/os/hal/boards/OLIMEX_LPC_P2148/buzzer.c
new file mode 100644
index 000000000..a0dede38d
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P2148/buzzer.c
@@ -0,0 +1,110 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * Buzzer driver for Olimex LPC-P2148.
+ * Uses the timer 1 for wave generation and a Virtual Timer for the sound
+ * duration.
+ * The driver also generates an event when the sound is done and the buzzer
+ * goes silent.
+ */
+
+#include "hal.h"
+
+#include "buzzer.h"
+
+EventSource BuzzerSilentEventSource;
+
+#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1)
+#define StopCounter(t)  ((t)->TC_EMR = 0, (t)->TC_TCR = 2)
+
+/**
+ * @brief Buzzer driver initialization.
+ */
+void buzzInit(void) {
+
+  chEvtInit(&BuzzerSilentEventSource);
+
+  /*
+   * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions.
+   * Enables Timer1 clock.
+   */
+  PINSEL0 &= 0xF0FFFFFF;
+  PINSEL0 |= 0x0A000000;
+  PCONP = (PCONP & PCALL) | PCTIM1;
+
+  /*
+   * Timer setup.
+   */
+  TC *tc = T1Base;
+  StopCounter(tc);
+  tc->TC_CTCR = 0;                      /* Clock source is PCLK.        */
+  tc->TC_PR   = 0;                      /* Prescaler disabled.          */
+  tc->TC_MCR  = 2;                      /* Clear TC on match MR0.       */
+}
+
+/**
+ * @brief Stops the sound.
+ *
+ * @param[in] p pointer to the timer
+ */
+static void stop(void *p) {
+
+  StopCounter((TC *)p);
+  chSysLockFromIsr();
+  chEvtBroadcastI(&BuzzerSilentEventSource);
+  chSysUnlockFromIsr();
+}
+
+/**
+ * @brief Plays a tone asynchronously.
+ *
+ * @param[in] freq approximated tone frequency
+ * @param[in] duration tone duration in systicks
+ */
+void buzzPlay(uint32_t freq, systime_t duration) {
+  static VirtualTimer bvt;
+  TC *tc = T1Base;
+
+  chSysLock();
+
+  if (chVTIsArmedI(&bvt)) {             /* If a sound is already being  */
+    chVTResetI(&bvt);                   /* played then aborts it.       */
+    StopCounter(tc);
+  }
+
+  tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2));
+  StartCounter(tc);
+  chVTSetI(&bvt, duration, stop, tc);
+
+  chSysUnlock();
+}
+
+/**
+ * @brief Plays a tone.
+ *
+ * @param[in] freq approximated tone frequency
+ * @param[in] duration tone duration in systicks
+ */
+void buzzPlayWait(uint32_t freq, systime_t duration) {
+  TC *tc = T1Base;
+
+  StopCounter(tc);
+  tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2));
+  StartCounter(tc);
+  chThdSleep(duration);
+  StopCounter(tc);
+}
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/buzzer.h b/os/hal/boards/OLIMEX_LPC_P2148/buzzer.h
new file mode 100644
index 000000000..82f573902
--- /dev/null
+++ b/os/hal/boards/OLIMEX_LPC_P2148/buzzer.h
@@ -0,0 +1,32 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BUZZER_H_
+#define _BUZZER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void buzzInit(void);
+  void buzzPlay(uint32_t freq, systime_t duration);
+  void buzzPlayWait(uint32_t freq, systime_t duration);
+#ifdef __cplusplus
+}
+#endif
+
+extern EventSource BuzzerSilentEventSource;
+
+#endif /* _BUZZER_H_ */
diff --git a/os/hal/boards/OLIMEX_MSP430_P1611/board.c b/os/hal/boards/OLIMEX_MSP430_P1611/board.c
new file mode 100644
index 000000000..58bc4df15
--- /dev/null
+++ b/os/hal/boards/OLIMEX_MSP430_P1611/board.c
@@ -0,0 +1,79 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__)
+  {VAL_P1OUT, VAL_P1DIR},
+#endif
+#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__)
+  {VAL_P2OUT, VAL_P2DIR},
+#endif
+#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__)
+  {VAL_P3OUT, VAL_P3DIR},
+#endif
+#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__)
+  {VAL_P4OUT, VAL_P4DIR},
+#endif
+#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__)
+  {VAL_P5OUT, VAL_P5DIR},
+#endif
+#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__)
+  {VAL_P6OUT, VAL_P6DIR},
+#endif
+};
+#endif
+
+CH_IRQ_HANDLER(TIMERA0) {
+
+  CH_IRQ_PROLOGUE();
+
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+#if USE_MSP430_USART0
+  P3SEL |= (1 << 4) | (1 << 5);
+#endif
+
+#if USE_MSP430_USART1
+  P3SEL |= (1 << 6) | (1 << 7);
+#endif
+
+  /*
+   * Timer 0 setup, uses SMCLK as source.
+   */
+  TACCR0 = SMCLK / 4 / CH_FREQUENCY - 1;/* Counter limit.               */
+  TACTL = TACLR;                        /* Clean start.                 */
+  TACTL = TASSEL_2 | ID_2 | MC_1;       /* Src=SMCLK, ID=4, cmp=TACCR0. */
+  TACCTL0 = CCIE;                       /* Interrupt on compare.        */
+}
diff --git a/os/hal/boards/OLIMEX_MSP430_P1611/board.h b/os/hal/boards/OLIMEX_MSP430_P1611/board.h
new file mode 100644
index 000000000..e28b85bf5
--- /dev/null
+++ b/os/hal/boards/OLIMEX_MSP430_P1611/board.h
@@ -0,0 +1,80 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex MSP430-P1611 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_MSP430_P1611
+#define BOARD_NAME "Olimex MSP430-P1611"
+
+/*
+ * Clock constants.
+ */
+#define LFXT1CLK        32768
+#define XT2CLK          8000000
+#define DCOCLK          750000
+
+/*
+ * Pin definitions for the Olimex MSP430-P1611 board.
+ */
+#define P3_O_TXD0               4
+#define P3_O_TXD0_MASK          (1 << P3_O_TXD0)
+#define P3_I_RXD0               5
+#define P3_I_RXD0_MASK          (1 << P3_I_RXD0)
+#define P6_O_LED                0
+#define P6_O_LED_MASK           (1 << P6_O_LED)
+#define P6_I_BUTTON             1
+#define P6_I_BUTTON_MASK        (1 << P6_I_BUTTON)
+
+/*
+ * Initial I/O ports settings.
+ */
+#define VAL_P1OUT       0x00
+#define VAL_P1DIR       0xFF
+
+#define VAL_P2OUT       0x00
+#define VAL_P2DIR       0xFF
+
+#define VAL_P3OUT       P3_O_TXD0_MASK
+#define VAL_P3DIR       ~P3_I_RXD0_MASK
+
+#define VAL_P4OUT       0x00
+#define VAL_P4DIR       0xFF
+
+#define VAL_P5OUT       0x00
+#define VAL_P5DIR       0xFF
+
+#define VAL_P6OUT       P6_O_LED_MASK
+#define VAL_P6DIR       ~P6_I_BUTTON_MASK
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_MSP430_P1611/board.mk b/os/hal/boards/OLIMEX_MSP430_P1611/board.mk
new file mode 100644
index 000000000..19ab61636
--- /dev/null
+++ b/os/hal/boards/OLIMEX_MSP430_P1611/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_MSP430_P1611/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_MSP430_P1611
diff --git a/os/hal/boards/OLIMEX_SAM7_EX256/board.c b/os/hal/boards/OLIMEX_SAM7_EX256/board.c
new file mode 100644
index 000000000..9909ef37c
--- /dev/null
+++ b/os/hal/boards/OLIMEX_SAM7_EX256/board.c
@@ -0,0 +1,136 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR},
+#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
+    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
+  {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR}
+#endif
+};
+#endif
+
+/*
+ * SYS IRQ handling here.
+ */
+static CH_IRQ_HANDLER(SYSIrqHandler) {
+
+  CH_IRQ_PROLOGUE();
+
+  if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) {
+    (void) AT91C_BASE_PITC->PITC_PIVR;
+    chSysLockFromIsr();
+    chSysTimerHandlerI();
+    chSysUnlockFromIsr();
+  }
+  
+#if USE_SAM7_DBGU_UART
+  if (AT91C_BASE_DBGU->DBGU_CSR &
+      (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME |
+       AT91C_US_OVRE | AT91C_US_RXBRK)) {
+    sd_lld_serve_interrupt(&SDDBG);
+  }
+#endif
+  AT91C_BASE_AIC->AIC_EOICR = 0;
+  CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  
+  /* Watchdog disabled.*/
+  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+  
+  at91sam7_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return !palReadPad(IOPORT2, PIOB_MMC_CP);
+}
+
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return palReadPad(IOPORT2, PIOB_MMC_WP);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * LCD pins setup.
+   */
+  palClearPad(IOPORT2, PIOB_LCD_BL);
+  palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL);
+
+  palSetPad(IOPORT1, PIOA_LCD_RESET);
+  palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL);
+
+  /*
+   * Joystick and buttons setup.
+   */
+  palSetGroupMode(IOPORT1,
+                  PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK |
+                  PIOA_B4_MASK | PIOA_B5_MASK,
+                  0,
+                  PAL_MODE_INPUT);
+  palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, 0, PAL_MODE_INPUT);
+
+  /*
+   * MMC/SD slot setup.
+   */
+  palSetGroupMode(IOPORT2,
+                  PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK,
+                  0,
+                  PAL_MODE_INPUT);
+
+  /*
+   * PIT Initialization.
+   */
+  AIC_ConfigureIT(AT91C_ID_SYS,
+                  AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1),
+                  SYSIrqHandler);
+  AIC_EnableIT(AT91C_ID_SYS);
+  AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1;
+  AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
+
+  /*
+   * RTS/CTS pins enabled for USART0 only.
+   */
+  AT91C_BASE_PIOA->PIO_PDR   = AT91C_PA3_RTS0 | AT91C_PA4_CTS0;
+  AT91C_BASE_PIOA->PIO_ASR   = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+  AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+}
diff --git a/os/hal/boards/OLIMEX_SAM7_EX256/board.h b/os/hal/boards/OLIMEX_SAM7_EX256/board.h
new file mode 100644
index 000000000..efe5ead0c
--- /dev/null
+++ b/os/hal/boards/OLIMEX_SAM7_EX256/board.h
@@ -0,0 +1,101 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex SAM7-EX256 development board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_SAM7_EX256
+#define BOARD_NAME "Olimex SAM7-EX256"
+
+/*
+ * Select your platform by modifying the following line.
+ */
+#if !defined(SAM7_PLATFORM)
+#define SAM7_PLATFORM   SAM7X256
+#endif
+
+#include "at91sam7.h"
+
+#define CLK             18432000
+#define MCK             48054857
+
+/*
+ * Initial I/O setup.
+ */
+#define VAL_PIOA_ODSR           0x00000000      /* Output data. */
+#define VAL_PIOA_OSR            0x00000000      /* Direction. */
+#define VAL_PIOA_PUSR           0xFFFFFFFF      /* Pull-up. */
+
+#define VAL_PIOB_ODSR           0x00000000      /* Output data. */
+#define VAL_PIOB_OSR            0x00000000      /* Direction. */
+#define VAL_PIOB_PUSR           0xFFFFFFFF      /* Pull-up. */
+
+/*
+ * I/O definitions.
+ */
+#define PIOA_LCD_RESET          2
+#define PIOA_LCD_RESET_MASK     (1 << PIOA_LCD_RESET)
+#define PIOA_B1                 7
+#define PIOA_B1_MASK            (1 << PIOA_B1)
+#define PIOA_B2                 8
+#define PIOA_B2_MASK            (1 << PIOA_B2)
+#define PIOA_B3                 9
+#define PIOA_B3_MASK            (1 << PIOA_B3)
+#define PIOA_B4                 14
+#define PIOA_B4_MASK            (1 << PIOA_B4)
+#define PIOA_B5                 15
+#define PIOA_B5_MASK            (1 << PIOA_B5)
+#define PIOA_USB_PUP            25
+#define PIOA_USB_PUP_MASK       (1 << PIOA_USB_PUP)
+#define PIOA_USB_PR             26
+#define PIOA_USB_PR_MASK        (1 << PIOA_USB_PR)
+#define PIOA_CS_MMC             13
+
+#define PIOB_PHY_PD             18
+#define PIOB_PHY_PD_MASK        (1 << PIOB_PHY_PD)
+#define PIOB_AUDIO_OUT          19
+#define PIOB_AUDIO_OUT_MASK     (1 << PIOB_AUDIO_OUT)
+#define PIOB_LCD_BL             20
+#define PIOB_LCD_BL_MASK        (1 << PIOB_LCD_BL)
+#define PIOB_MMC_WP             22
+#define PIOB_MMC_WP_MASK        (1 << PIOB_MMC_WP)
+#define PIOB_MMC_CP             23
+#define PIOB_MMC_CP_MASK        (1 << PIOB_MMC_CP)
+#define PIOB_SW1                24
+#define PIOB_SW1_MASK           (1 << PIOB_SW1)
+#define PIOB_SW2                25
+#define PIOB_SW2_MASK           (1 << PIOB_SW2)
+#define PIOB_PHY_IRQ            26
+#define PIOB_PHY_IRQ_MASK       (1 << PIOB_PHY_IRQ)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_SAM7_EX256/board.mk b/os/hal/boards/OLIMEX_SAM7_EX256/board.mk
new file mode 100644
index 000000000..9c44c0259
--- /dev/null
+++ b/os/hal/boards/OLIMEX_SAM7_EX256/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_SAM7_EX256/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_SAM7_EX256
diff --git a/os/hal/boards/OLIMEX_SAM7_P256/board.c b/os/hal/boards/OLIMEX_SAM7_P256/board.c
new file mode 100644
index 000000000..21b65bc1b
--- /dev/null
+++ b/os/hal/boards/OLIMEX_SAM7_P256/board.c
@@ -0,0 +1,116 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR},
+#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
+    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
+  {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR}
+#endif
+};
+#endif
+
+/*
+ * SYS IRQ handling here.
+ */
+static CH_IRQ_HANDLER(SYSIrqHandler) {
+
+  CH_IRQ_PROLOGUE();
+
+  if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) {
+    (void) AT91C_BASE_PITC->PITC_PIVR;
+    chSysLockFromIsr();
+    chSysTimerHandlerI();
+    chSysUnlockFromIsr();
+  }
+  AT91C_BASE_AIC->AIC_EOICR = 0;
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  
+  /* Watchdog disabled.*/
+  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+  
+  at91sam7_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return !palReadPad(IOPORT1, PIOA_MMC_CP);
+}
+
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return palReadPad(IOPORT1, PIOA_MMC_WP);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * LED pins setup.
+   */
+  palClearPad(IOPORT1, PIOA_LED1);
+  palSetPadMode(IOPORT1, PIOA_LED1, PAL_MODE_OUTPUT_PUSHPULL);
+  palClearPad(IOPORT1, PIOA_LED2);
+  palSetPadMode(IOPORT1, PIOA_LED2, PAL_MODE_OUTPUT_PUSHPULL);
+
+  /*
+   * buttons setup.
+   */
+  palSetGroupMode(IOPORT1, PIOA_B1_MASK | PIOA_B2_MASK, 0, PAL_MODE_INPUT);
+
+  /*
+   * MMC/SD slot setup.
+   */
+  palSetGroupMode(IOPORT1,
+                  PIOA_MMC_WP_MASK | PIOA_MMC_CP_MASK,
+                  0,
+                  PAL_MODE_INPUT);
+
+  /*
+   * PIT Initialization.
+   */
+  AIC_ConfigureIT(AT91C_ID_SYS,
+                  AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1),
+                  SYSIrqHandler);
+  AIC_EnableIT(AT91C_ID_SYS);
+  AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1;
+  AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
+}
diff --git a/os/hal/boards/OLIMEX_SAM7_P256/board.h b/os/hal/boards/OLIMEX_SAM7_P256/board.h
new file mode 100644
index 000000000..d16c13271
--- /dev/null
+++ b/os/hal/boards/OLIMEX_SAM7_P256/board.h
@@ -0,0 +1,81 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex SAM7-P256 development board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_SAM7_P256
+
+/*
+ * Select your platform by modifying the following line.
+ */
+#if !defined(SAM7_PLATFORM)
+#define SAM7_PLATFORM   SAM7S256
+#endif
+
+#include "at91sam7.h"
+
+#define CLK             18432000
+#define MCK             48054857
+
+/*
+ * Initial I/O setup.
+ */
+#define VAL_PIOA_ODSR           0x00000000      /* Output data. */
+#define VAL_PIOA_OSR            0x00000000      /* Direction. */
+#define VAL_PIOA_PUSR           0xFFFFFFFF      /* Pull-up. */
+
+/*
+ * I/O definitions.
+ */
+#define PIOA_LED1               18
+#define PIOA_LED1_MASK          (1 << PIOA_LED1_MASK)
+#define PIOA_LED2               17
+#define PIOA_LED2_MASK          (1 << PIOA_LED2_MASK)
+#define PIOA_B1                 19
+#define PIOA_B1_MASK            (1 << PIOA_B1)
+#define PIOA_B2                 20
+#define PIOA_B2_MASK            (1 << PIOA_B2)
+#define PIOA_DP_PUP             25
+#define PIOA_DD_PUP_MASK        (1 << PIOA_DP_PUP)
+#define PIOA_USB_D              26
+#define PIOA_USB_D_MASK         (1 << PIOA_USB_D)
+
+#define PIOA_MMC_WP             25
+#define PIOA_MMC_WP_MASK        (1 << PIOA_MMC_WP)
+#define PIOA_MMC_CP             15
+#define PIOA_MMC_CP_MASK        (1 << PIOA_MMC_CP)
+#define PIOA_MMC_NPCS0          11
+#define PIOA_MMC_NPCS0_MASK     (1 << PIOA_MMC_NPCS0_MASK)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_SAM7_P256/board.mk b/os/hal/boards/OLIMEX_SAM7_P256/board.mk
new file mode 100644
index 000000000..7555c8c4e
--- /dev/null
+++ b/os/hal/boards/OLIMEX_SAM7_P256/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_SAM7_P256/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_SAM7_P256
diff --git a/os/hal/boards/OLIMEX_STM32_103STK/board.c b/os/hal/boards/OLIMEX_STM32_103STK/board.c
new file mode 100644
index 000000000..bd21d1738
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_103STK/board.c
@@ -0,0 +1,49 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_103STK/board.h b/os/hal/boards/OLIMEX_STM32_103STK/board.h
new file mode 100644
index 000000000..df1b832d2
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_103STK/board.h
@@ -0,0 +1,168 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM32-103STK proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_103STK
+#define BOARD_NAME              "Olimex STM32-103STK"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON_WAKEUP     0
+#define GPIOC_BUTTON_TAMPER     13
+#define GPIOC_JOY               5
+#define GPIOC_JOY_CENTER_BUT    6
+
+#define GPIOA_SPI1NSS           4
+#define GPIOB_SPI2NSS           12
+
+#define GPIOC_MMCWP             2
+#define GPIOC_MMCCP             1
+
+#define GPIOC_USB_P             4
+#define GPIOC_LCD_RES           7
+#define GPIOC_NRF_CE            8
+#define GPIOC_NRF_IRQ           9
+#define GPIOC_LCD_E             10
+
+#define GPIOC_USB_DISC          11
+#define GPIOC_LED               12
+
+#define GPIOB_ACCEL_IRQ         5
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0  - Normal input      (BUTTON).
+ * PA2  - Alternate output  (USART2 TX).
+ * PA3  - Normal input      (USART2 RX).
+ */
+#define VAL_GPIOACRL            0x88884B84      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x88888888      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB6,7   - Alternate open drain (I2C1).
+ * PB10,11 - Alternate open drain (I2C2).
+ * PB12    - Push Pull output  (MMC SPI2 NSS).
+ * PB13    - Alternate output  (MMC SPI2 SCK).
+ * PB14    - Normal input      (MMC SPI2 MISO).
+ * PB15    - Alternate output  (MMC SPI2 MOSI).
+ */
+#define VAL_GPIOBCRL            0xEE888888      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0xB4B3EE88      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC4  - Normal input because there is an external resistor.
+ * PC5  - Analog input (joystick).
+ * PC6  - Normal input because there is an external resistor.
+ * PC7  - Normal input because there is an external resistor.
+ * PC10 - Push Pull output (CAN CNTRL).
+ * PC11 - Push Pull output (USB DISC).
+ * PC12 - Open Drain output (LED).
+ */
+#define VAL_GPIOCCRL            0x44048888      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x88863388      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0  - Normal input (XTAL).
+ * PD1  - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL            0x88888844      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x88888888      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x88888888      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_103STK/board.mk b/os/hal/boards/OLIMEX_STM32_103STK/board.mk
new file mode 100644
index 000000000..9c67b3d22
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_103STK/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_103STK/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_103STK
diff --git a/os/hal/boards/OLIMEX_STM32_E407/board.c b/os/hal/boards/OLIMEX_STM32_E407/board.c
new file mode 100644
index 000000000..2e219171f
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_E407/board.c
@@ -0,0 +1,107 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  static bool last_status = FALSE;
+
+  if (blkIsTransferring(sdcp))
+    return last_status;
+  return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_E407/board.h b/os/hal/boards/OLIMEX_STM32_E407/board.h
new file mode 100644
index 000000000..a9a046a81
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_E407/board.h
@@ -0,0 +1,1300 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Olimex STM32-E407 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_E407
+#define BOARD_NAME                  "Olimex STM32-E407"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID                MII_KS8721_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                12000000
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   330
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F40_41xxx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON_WKUP           0
+#define GPIOA_ETH_RMII_REF_CLK      1
+#define GPIOA_ETH_RMII_MDIO         2
+#define GPIOA_ETH_RMII_MDINT        3
+#define GPIOA_PIN4                  4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_ETH_RMII_CRS_DV       7
+#define GPIOA_USB_HS_BUSON          8
+#define GPIOA_OTG_FS_VBUS           9
+#define GPIOA_OTG_FS_ID             10
+#define GPIOA_OTG_FS_DM             11
+#define GPIOA_OTG_FS_DP             12
+#define GPIOA_JTAG_TMS              13
+#define GPIOA_JTAG_TCK              14
+#define GPIOA_JTAG_TDI              15
+
+#define GPIOB_USB_FS_BUSON          0
+#define GPIOB_USB_HS_FAULT          1
+#define GPIOB_BOOT1                 2
+#define GPIOB_JTAG_TDO              3
+#define GPIOB_JTAG_TRST             4
+#define GPIOB_PIN5                  5
+#define GPIOB_PIN6                  6
+#define GPIOB_PIN7                  7
+#define GPIOB_I2C1_SCL              8
+#define GPIOB_I2C1_SDA              9
+#define GPIOB_SPI2_SCK              10
+#define GPIOB_PIN11                 11
+#define GPIOB_OTG_HS_ID             12
+#define GPIOB_OTG_HS_VBUS           13
+#define GPIOB_OTG_HS_DM             14
+#define GPIOB_OTG_HS_DP             15
+
+#define GPIOC_PIN0                  0
+#define GPIOC_ETH_RMII_MDC          1
+#define GPIOC_SPI2_MISO             2
+#define GPIOC_SPI2_MOSI             3
+#define GPIOC_ETH_RMII_RXD0         4
+#define GPIOC_ETH_RMII_RXD1         5
+#define GPIOC_USART6_TX             6
+#define GPIOC_USART6_RX             7
+#define GPIOC_SD_D0                 8
+#define GPIOC_SD_D1                 9
+#define GPIOC_SD_D2                 10
+#define GPIOC_SD_D3                 11
+#define GPIOC_SD_CLK                12
+#define GPIOC_LED                   13
+#define GPIOC_OSC32_IN              14
+#define GPIOC_OSC32_OUT             15
+
+#define GPIOD_PIN0                  0
+#define GPIOD_PIN1                  1
+#define GPIOD_SD_CMD                2
+#define GPIOD_PIN3                  3
+#define GPIOD_PIN4                  4
+#define GPIOD_PIN5                  5
+#define GPIOD_PIN6                  6
+#define GPIOD_PIN7                  7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_PIN11                 11
+#define GPIOD_PIN12                 12
+#define GPIOD_PIN13                 13
+#define GPIOD_PIN14                 14
+#define GPIOD_PIN15                 15
+
+#define GPIOE_PIN0                  0
+#define GPIOE_PIN1                  1
+#define GPIOE_PIN2                  2
+#define GPIOE_PIN3                  3
+#define GPIOE_PIN4                  4
+#define GPIOE_PIN5                  5
+#define GPIOE_PIN6                  6
+#define GPIOE_PIN7                  7
+#define GPIOE_PIN8                  8
+#define GPIOE_PIN9                  9
+#define GPIOE_PIN10                 10
+#define GPIOE_PIN11                 11
+#define GPIOE_PIN12                 12
+#define GPIOE_PIN13                 13
+#define GPIOE_PIN14                 14
+#define GPIOE_PIN15                 15
+
+#define GPIOF_PIN0                  0
+#define GPIOF_PIN1                  1
+#define GPIOF_PIN2                  2
+#define GPIOF_PIN3                  3
+#define GPIOF_PIN4                  4
+#define GPIOF_PIN5                  5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_PIN9                  9
+#define GPIOF_PIN10                 10
+#define GPIOF_USB_FS_FAULT          11
+#define GPIOF_PIN12                 12
+#define GPIOF_PIN13                 13
+#define GPIOF_PIN14                 14
+#define GPIOF_PIN15                 15
+
+#define GPIOG_PIN0                  0
+#define GPIOG_PIN1                  1
+#define GPIOG_PIN2                  2
+#define GPIOG_PIN3                  3
+#define GPIOG_PIN4                  4
+#define GPIOG_PIN5                  5
+#define GPIOG_PIN6                  6
+#define GPIOG_PIN7                  7
+#define GPIOG_PIN8                  8
+#define GPIOG_PIN9                  9
+#define GPIOG_SPI2_CS               10
+#define GPIOG_ETH_RMII_TXEN         11
+#define GPIOG_PIN12                 12
+#define GPIOG_ETH_RMII_TXD0         13
+#define GPIOG_ETH_RMII_TXD1         14
+#define GPIOG_PIN15                 15
+
+#define GPIOH_OSC_IN                0
+#define GPIOH_OSC_OUT               1
+#define GPIOH_PIN2                  2
+#define GPIOH_PIN3                  3
+#define GPIOH_PIN4                  4
+#define GPIOH_PIN5                  5
+#define GPIOH_PIN6                  6
+#define GPIOH_PIN7                  7
+#define GPIOH_PIN8                  8
+#define GPIOH_PIN9                  9
+#define GPIOH_PIN10                 10
+#define GPIOH_PIN11                 11
+#define GPIOH_PIN12                 12
+#define GPIOH_PIN13                 13
+#define GPIOH_PIN14                 14
+#define GPIOH_PIN15                 15
+
+#define GPIOI_PIN0                  0
+#define GPIOI_PIN1                  1
+#define GPIOI_PIN2                  2
+#define GPIOI_PIN3                  3
+#define GPIOI_PIN4                  4
+#define GPIOI_PIN5                  5
+#define GPIOI_PIN6                  6
+#define GPIOI_PIN7                  7
+#define GPIOI_PIN8                  8
+#define GPIOI_PIN9                  9
+#define GPIOI_PIN10                 10
+#define GPIOI_PIN11                 11
+#define GPIOI_PIN12                 12
+#define GPIOI_PIN13                 13
+#define GPIOI_PIN14                 14
+#define GPIOI_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - BUTTON_WKUP               (input floating).
+ * PA1  - ETH_RMII_REF_CLK          (alternate 11).
+ * PA2  - ETH_RMII_MDIO             (alternate 11).
+ * PA3  - ETH_RMII_MDINT            (input floating).
+ * PA4  - PIN4                      (input pullup).
+ * PA5  - PIN5                      (input pullup).
+ * PA6  - PIN6                      (input pullup).
+ * PA7  - ETH_RMII_CRS_DV           (alternate 11).
+ * PA8  - USB_HS_BUSON              (output pushpull maximum).
+ * PA9  - OTG_FS_VBUS               (input pulldown).
+ * PA10 - OTG_FS_ID                 (alternate 10).
+ * PA11 - OTG_FS_DM                 (alternate 10).
+ * PA12 - OTG_FS_DP                 (alternate 10).
+ * PA13 - JTAG_TMS                  (alternate 0).
+ * PA14 - JTAG_TCK                  (alternate 0).
+ * PA15 - JTAG_TDI                  (alternate 0).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) |    \
+                                     PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) |\
+                                     PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) |\
+                                     PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
+                                     PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\
+                                     PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) |  \
+                                     PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) |    \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) |   \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) |   \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_WKUP) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_REF_CLK) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDIO) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDINT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_100M(GPIOA_BUTTON_WKUP) |   \
+                                     PIN_OSPEED_100M(GPIOA_ETH_RMII_REF_CLK) |\
+                                     PIN_OSPEED_100M(GPIOA_ETH_RMII_MDIO) | \
+                                     PIN_OSPEED_100M(GPIOA_ETH_RMII_MDINT) |\
+                                     PIN_OSPEED_100M(GPIOA_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOA_ETH_RMII_CRS_DV) |\
+                                     PIN_OSPEED_100M(GPIOA_USB_HS_BUSON) |  \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_VBUS) |   \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_ID) |     \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DM) |     \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DP) |     \
+                                     PIN_OSPEED_100M(GPIOA_JTAG_TMS) |      \
+                                     PIN_OSPEED_100M(GPIOA_JTAG_TCK) |      \
+                                     PIN_OSPEED_100M(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_BUTTON_WKUP) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_REF_CLK) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDIO) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDINT) |\
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\
+                                     PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) |   \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) |   \
+                                     PIN_PUPDR_FLOATING(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_BUTTON_WKUP) |      \
+                                     PIN_ODR_HIGH(GPIOA_ETH_RMII_REF_CLK) | \
+                                     PIN_ODR_HIGH(GPIOA_ETH_RMII_MDIO) |    \
+                                     PIN_ODR_HIGH(GPIOA_ETH_RMII_MDINT) |   \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) |  \
+                                     PIN_ODR_HIGH(GPIOA_USB_HS_BUSON) |     \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) |      \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_ID) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DP) |        \
+                                     PIN_ODR_HIGH(GPIOA_JTAG_TMS) |         \
+                                     PIN_ODR_HIGH(GPIOA_JTAG_TCK) |         \
+                                     PIN_ODR_HIGH(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_BUTTON_WKUP, 0) |    \
+                                     PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) |\
+                                     PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \
+                                     PIN_AFIO_AF(GPIOA_ETH_RMII_MDINT, 0) | \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) |   \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) |    \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) |       \
+                                     PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) |       \
+                                     PIN_AFIO_AF(GPIOA_JTAG_TDI, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - USB_FS_BUSON              (output pushpull maximum).
+ * PB1  - USB_HS_FAULT              (input floating).
+ * PB2  - BOOT1                     (input floating).
+ * PB3  - JTAG_TDO                  (alternate 0).
+ * PB4  - JTAG_TRST                 (alternate 0).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - PIN6                      (input pullup).
+ * PB7  - PIN7                      (input pullup).
+ * PB8  - I2C1_SCL                  (alternate 4).
+ * PB9  - I2C1_SDA                  (alternate 4).
+ * PB10 - SPI2_SCK                  (alternate 5).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - OTG_HS_ID                 (alternate 12).
+ * PB13 - OTG_HS_VBUS               (input pulldown).
+ * PB14 - OTG_HS_DM                 (alternate 12).
+ * PB15 - OTG_HS_DP                 (alternate 12).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) |  \
+                                     PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) |   \
+                                     PIN_MODE_INPUT(GPIOB_BOOT1) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) |  \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) |   \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) |  \
+                                     PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) |    \
+                                     PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_BUSON) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) |  \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_100M(GPIOB_USB_FS_BUSON) |  \
+                                     PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) |  \
+                                     PIN_OSPEED_100M(GPIOB_BOOT1) |         \
+                                     PIN_OSPEED_100M(GPIOB_JTAG_TDO) |      \
+                                     PIN_OSPEED_100M(GPIOB_JTAG_TRST) |     \
+                                     PIN_OSPEED_100M(GPIOB_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOB_I2C1_SCL) |      \
+                                     PIN_OSPEED_100M(GPIOB_I2C1_SDA) |      \
+                                     PIN_OSPEED_100M(GPIOB_SPI2_SCK) |      \
+                                     PIN_OSPEED_100M(GPIOB_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_ID) |     \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_VBUS) |   \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_DM) |     \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_FLOATING(GPIOB_USB_FS_BUSON) |\
+                                     PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\
+                                     PIN_PUPDR_FLOATING(GPIOB_BOOT1) |      \
+                                     PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) |  \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) |   \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) |  \
+                                     PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\
+                                     PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_USB_FS_BUSON) |     \
+                                     PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) |     \
+                                     PIN_ODR_HIGH(GPIOB_BOOT1) |            \
+                                     PIN_ODR_HIGH(GPIOB_JTAG_TDO) |         \
+                                     PIN_ODR_HIGH(GPIOB_JTAG_TRST) |        \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_I2C1_SCL) |         \
+                                     PIN_ODR_HIGH(GPIOB_I2C1_SDA) |         \
+                                     PIN_ODR_HIGH(GPIOB_SPI2_SCK) |         \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_ID) |        \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) |      \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0) |   \
+                                     PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) |   \
+                                     PIN_AFIO_AF(GPIOB_BOOT1, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) |       \
+                                     PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) |      \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) |       \
+                                     PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) |       \
+                                     PIN_AFIO_AF(GPIOB_SPI2_SCK, 5) |       \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) |     \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0) |    \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) |     \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - PIN0                      (input pullup).
+ * PC1  - ETH_RMII_MDC              (alternate 11).
+ * PC2  - SPI2_MISO                 (alternate 5).
+ * PC3  - SPI2_MOSI                 (alternate 5).
+ * PC4  - ETH_RMII_RXD0             (alternate 11).
+ * PC5  - ETH_RMII_RXD1             (alternate 11).
+ * PC6  - USART6_TX                 (alternate 8).
+ * PC7  - USART6_RX                 (alternate 8).
+ * PC8  - SD_D0                     (alternate 12).
+ * PC9  - SD_D1                     (alternate 12).
+ * PC10 - SD_D2                     (alternate 12).
+ * PC11 - SD_D3                     (alternate 12).
+ * PC12 - SD_CLK                    (alternate 12).
+ * PC13 - LED                       (output pushpull maximum).
+ * PC14 - OSC32_IN                  (input floating).
+ * PC15 - OSC32_OUT                 (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \
+                                     PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) |\
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI2_MISO) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI2_MOSI) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) |\
+                                     PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) |\
+                                     PIN_MODE_ALTERNATE(GPIOC_USART6_TX) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_USART6_RX) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_D0) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_D1) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_D2) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_D3) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_CLK) |     \
+                                     PIN_MODE_OUTPUT(GPIOC_LED) |           \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_MDC) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MISO) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MOSI) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD0) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD1) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_USART6_TX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_USART6_RX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_LED) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_100M(GPIOC_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOC_ETH_RMII_MDC) |  \
+                                     PIN_OSPEED_100M(GPIOC_SPI2_MISO) |     \
+                                     PIN_OSPEED_100M(GPIOC_SPI2_MOSI) |     \
+                                     PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD0) | \
+                                     PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD1) | \
+                                     PIN_OSPEED_100M(GPIOC_USART6_TX) |     \
+                                     PIN_OSPEED_100M(GPIOC_USART6_RX) |     \
+                                     PIN_OSPEED_100M(GPIOC_SD_D0) |         \
+                                     PIN_OSPEED_100M(GPIOC_SD_D1) |         \
+                                     PIN_OSPEED_100M(GPIOC_SD_D2) |         \
+                                     PIN_OSPEED_100M(GPIOC_SD_D3) |         \
+                                     PIN_OSPEED_100M(GPIOC_SD_CLK) |        \
+                                     PIN_OSPEED_100M(GPIOC_LED) |           \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_IN) |      \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_MDC) |\
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI2_MISO) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI2_MOSI) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD0) |\
+                                     PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD1) |\
+                                     PIN_PUPDR_FLOATING(GPIOC_USART6_TX) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_USART6_RX) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_D0) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_D1) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_D2) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_D3) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_CLK) |     \
+                                     PIN_PUPDR_FLOATING(GPIOC_LED) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOC_ETH_RMII_MDC) |     \
+                                     PIN_ODR_HIGH(GPIOC_SPI2_MISO) |        \
+                                     PIN_ODR_HIGH(GPIOC_SPI2_MOSI) |        \
+                                     PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD0) |    \
+                                     PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD1) |    \
+                                     PIN_ODR_HIGH(GPIOC_USART6_TX) |        \
+                                     PIN_ODR_HIGH(GPIOC_USART6_RX) |        \
+                                     PIN_ODR_HIGH(GPIOC_SD_D0) |            \
+                                     PIN_ODR_HIGH(GPIOC_SD_D1) |            \
+                                     PIN_ODR_HIGH(GPIOC_SD_D2) |            \
+                                     PIN_ODR_HIGH(GPIOC_SD_D3) |            \
+                                     PIN_ODR_HIGH(GPIOC_SD_CLK) |           \
+                                     PIN_ODR_HIGH(GPIOC_LED) |              \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) |  \
+                                     PIN_AFIO_AF(GPIOC_SPI2_MISO, 5) |      \
+                                     PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5) |      \
+                                     PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \
+                                     PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \
+                                     PIN_AFIO_AF(GPIOC_USART6_TX, 8) |      \
+                                     PIN_AFIO_AF(GPIOC_USART6_RX, 8))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_SD_D0, 12) |         \
+                                     PIN_AFIO_AF(GPIOC_SD_D1, 12) |         \
+                                     PIN_AFIO_AF(GPIOC_SD_D2, 12) |         \
+                                     PIN_AFIO_AF(GPIOC_SD_D3, 12) |         \
+                                     PIN_AFIO_AF(GPIOC_SD_CLK, 12) |        \
+                                     PIN_AFIO_AF(GPIOC_LED, 0) |            \
+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0) |       \
+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - SD_CMD                    (alternate 12).
+ * PD3  - PIN3                      (input pullup).
+ * PD4  - PIN4                      (input pullup).
+ * PD5  - PIN5                      (input pullup).
+ * PD6  - PIN6                      (input pullup).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - PIN12                     (input pullup).
+ * PD13 - PIN13                     (input pullup).
+ * PD14 - PIN14                     (input pullup).
+ * PD15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_ALTERNATE(GPIOD_SD_CMD) |     \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_100M(GPIOD_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOD_SD_CMD) |        \
+                                     PIN_OSPEED_100M(GPIOD_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_SD_CMD) |     \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_SD_CMD) |           \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_SD_CMD, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0  - PIN0                      (input pullup).
+ * PE1  - PIN1                      (input pullup).
+ * PE2  - PIN2                      (input pullup).
+ * PE3  - PIN3                      (input pullup).
+ * PE4  - PIN4                      (input pullup).
+ * PE5  - PIN5                      (input pullup).
+ * PE6  - PIN6                      (input pullup).
+ * PE7  - PIN7                      (input pullup).
+ * PE8  - PIN8                      (input pullup).
+ * PE9  - PIN9                      (input pullup).
+ * PE10 - PIN10                     (input pullup).
+ * PE11 - PIN11                     (input pullup).
+ * PE12 - PIN12                     (input pullup).
+ * PE13 - PIN13                     (input pullup).
+ * PE14 - PIN14                     (input pullup).
+ * PE15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_100M(GPIOE_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_PULLUP(GPIOE_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0  - PIN0                      (input pullup).
+ * PF1  - PIN1                      (input pullup).
+ * PF2  - PIN2                      (input pullup).
+ * PF3  - PIN3                      (input pullup).
+ * PF4  - PIN4                      (input pullup).
+ * PF5  - PIN5                      (input pullup).
+ * PF6  - PIN6                      (input pullup).
+ * PF7  - PIN7                      (input pullup).
+ * PF8  - PIN8                      (input pullup).
+ * PF9  - PIN9                      (input pullup).
+ * PF10 - PIN10                     (input pullup).
+ * PF11 - USB_FS_FAULT              (input floating).
+ * PF12 - PIN12                     (input pullup).
+ * PF13 - PIN13                     (input pullup).
+ * PF14 - PIN14                     (input pullup).
+ * PF15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_USB_FS_FAULT) |   \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_100M(GPIOF_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOF_USB_FS_FAULT) |  \
+                                     PIN_OSPEED_100M(GPIOF_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_PULLUP(GPIOF_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \
+                                     PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT) |\
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_USB_FS_FAULT) |     \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_USB_FS_FAULT, 0) |   \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0  - PIN0                      (input pullup).
+ * PG1  - PIN1                      (input pullup).
+ * PG2  - PIN2                      (input pullup).
+ * PG3  - PIN3                      (input pullup).
+ * PG4  - PIN4                      (input pullup).
+ * PG5  - PIN5                      (input pullup).
+ * PG6  - PIN6                      (input pullup).
+ * PG7  - PIN7                      (input pullup).
+ * PG8  - PIN8                      (input pullup).
+ * PG9  - PIN9                      (input pullup).
+ * PG10 - SPI2_CS                   (output pushpull maximum).
+ * PG11 - ETH_RMII_TXEN             (alternate 11).
+ * PG12 - PIN12                     (input pullup).
+ * PG13 - ETH_RMII_TXD0             (alternate 11).
+ * PG14 - ETH_RMII_TXD1             (alternate 11).
+ * PG15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOG_MODER             (PIN_MODE_INPUT(GPIOG_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN9) |           \
+                                     PIN_MODE_OUTPUT(GPIOG_SPI2_CS) |       \
+                                     PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXEN) |\
+                                     PIN_MODE_INPUT(GPIOG_PIN12) |          \
+                                     PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) |\
+                                     PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) |\
+                                     PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_SPI2_CS) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXEN) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD0) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD1) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_100M(GPIOG_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOG_SPI2_CS) |       \
+                                     PIN_OSPEED_100M(GPIOG_ETH_RMII_TXEN) | \
+                                     PIN_OSPEED_100M(GPIOG_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD0) | \
+                                     PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD1) | \
+                                     PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_PULLUP(GPIOG_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN9) |         \
+                                     PIN_PUPDR_FLOATING(GPIOG_SPI2_CS) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXEN) |\
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN12) |        \
+                                     PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD0) |\
+                                     PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD1) |\
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOG_SPI2_CS) |          \
+                                     PIN_ODR_HIGH(GPIOG_ETH_RMII_TXEN) |    \
+                                     PIN_ODR_HIGH(GPIOG_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD0) |    \
+                                     PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD1) |    \
+                                     PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_SPI2_CS, 0) |        \
+                                     PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11) | \
+                                     PIN_AFIO_AF(GPIOG_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \
+                                     PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11) | \
+                                     PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0  - OSC_IN                    (input floating).
+ * PH1  - OSC_OUT                   (input floating).
+ * PH2  - PIN2                      (input pullup).
+ * PH3  - PIN3                      (input pullup).
+ * PH4  - PIN4                      (input pullup).
+ * PH5  - PIN5                      (input pullup).
+ * PH6  - PIN6                      (input pullup).
+ * PH7  - PIN7                      (input pullup).
+ * PH8  - PIN8                      (input pullup).
+ * PH9  - PIN9                      (input pullup).
+ * PH10 - PIN10                     (input pullup).
+ * PH11 - PIN11                     (input pullup).
+ * PH12 - PIN12                     (input pullup).
+ * PH13 - PIN13                     (input pullup).
+ * PH14 - PIN14                     (input pullup).
+ * PH15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_100M(GPIOH_OSC_IN) |        \
+                                     PIN_OSPEED_100M(GPIOH_OSC_OUT) |       \
+                                     PIN_OSPEED_100M(GPIOH_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOH_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0  - PIN0                      (input pullup).
+ * PI1  - PIN1                      (input pullup).
+ * PI2  - PIN2                      (input pullup).
+ * PI3  - PIN3                      (input pullup).
+ * PI4  - PIN4                      (input pullup).
+ * PI5  - PIN5                      (input pullup).
+ * PI6  - PIN6                      (input pullup).
+ * PI7  - PIN7                      (input pullup).
+ * PI8  - PIN8                      (input pullup).
+ * PI9  - PIN9                      (input pullup).
+ * PI10 - PIN10                     (input pullup).
+ * PI11 - PIN11                     (input pullup).
+ * PI12 - PIN12                     (input pullup).
+ * PI13 - PIN13                     (input pullup).
+ * PI14 - PIN14                     (input pullup).
+ * PI15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOI_MODER             (PIN_MODE_INPUT(GPIOI_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR           (PIN_OSPEED_100M(GPIOI_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR             (PIN_PUPDR_PULLUP(GPIOI_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR               (PIN_ODR_HIGH(GPIOI_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL              (PIN_AFIO_AF(GPIOI_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH              (PIN_AFIO_AF(GPIOI_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_E407/board.mk b/os/hal/boards/OLIMEX_STM32_E407/board.mk
new file mode 100644
index 000000000..4c82966b6
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_E407/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_E407/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_E407
diff --git a/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg b/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg
new file mode 100644
index 000000000..ff3ab4e3d
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg
@@ -0,0 +1,341 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F4xx board Template -->
+<board xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+    xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+  <configuration_settings>
+    <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+    <output_path>..</output_path>
+  </configuration_settings>
+    <board_name>Olimex STM32-E407</board_name>
+    <board_id>OLIMEX_STM32_E407</board_id>
+    <board_functions>
+        <sdc_lld_is_card_inserted><![CDATA[  static bool_t last_status = FALSE;
+
+  if (blkIsTransferring(sdcp))
+    return last_status;
+  return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
+        <sdc_lld_is_write_protected>
+<![CDATA[  (void)sdcp;
+  return FALSE;]]></sdc_lld_is_write_protected>
+    </board_functions>
+    <ethernet_phy>
+        <identifier>MII_KS8721_ID</identifier>
+        <bus_type>RMII</bus_type>
+    </ethernet_phy>
+    <subtype>STM32F40_41xxx</subtype>
+    <clocks
+       HSEFrequency="12000000"
+       HSEBypass="false"
+       LSEFrequency="32768"
+       LSEBypass="false"
+       VDD="330"
+    />
+    <ports>
+        <GPIOA>
+            <pin0 ID="BUTTON_WKUP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="ETH_RMII_REF_CLK" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin2 ID="ETH_RMII_MDIO" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin3 ID="ETH_RMII_MDINT" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="ETH_RMII_CRS_DV" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin8 ID="USB_HS_BUSON" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Output" Alternate="0" />
+            <pin9 ID="OTG_FS_VBUS" Type="PushPull" Speed="Maximum" Resistor="PullDown"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="OTG_FS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="10" />
+            <pin11 ID="OTG_FS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="10" />
+            <pin12 ID="OTG_FS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="10" />
+            <pin13 ID="JTAG_TMS" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="0" />
+            <pin14 ID="JTAG_TCK" Type="PushPull" Speed="Maximum" Resistor="PullDown"
+                Level="High" Mode="Alternate" Alternate="0" />
+            <pin15 ID="JTAG_TDI" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="0" />
+        </GPIOA>
+        <GPIOB>
+            <pin0 ID="USB_FS_BUSON" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Output" Alternate="0" />
+            <pin1 ID="USB_HS_FAULT" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="BOOT1" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="JTAG_TDO" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="0" />
+            <pin4 ID="JTAG_TRST" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="I2C1_SCL" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="4" />
+            <pin9 ID="I2C1_SDA" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="4" />
+            <pin10 ID="SPI2_SCK" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="5" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="OTG_HS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin13 ID="OTG_HS_VBUS" Type="PushPull" Speed="Maximum"
+                Resistor="PullDown" Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="OTG_HS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin15 ID="OTG_HS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+        </GPIOB>
+        <GPIOC>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="ETH_RMII_MDC" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin2 ID="SPI2_MISO" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="5" />
+            <pin3 ID="SPI2_MOSI" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="5" />
+            <pin4 ID="ETH_RMII_RXD0" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin5 ID="ETH_RMII_RXD1" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin6 ID="USART6_TX" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="8" />
+            <pin7 ID="USART6_RX" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="8" />
+            <pin8 ID="SD_D0" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin9 ID="SD_D1" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin10 ID="SD_D2" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin11 ID="SD_D3" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin12 ID="SD_CLK" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin13 ID="LED" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Output" Alternate="0" />
+            <pin14 ID="OSC32_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="OSC32_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOC>
+        <GPIOD>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="SD_CMD" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOD>
+        <GPIOE>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOE>
+        <GPIOF>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="USB_FS_FAULT" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOF>
+        <GPIOG>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="SPI2_CS" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Output" Alternate="0" />
+            <pin11 ID="ETH_RMII_TXEN" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="ETH_RMII_TXD0" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin14 ID="ETH_RMII_TXD1" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOG>
+        <GPIOH>
+            <pin0 ID="OSC_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0"></pin0>
+            <pin1 ID="OSC_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOH>
+        <GPIOI>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOI>
+    </ports>
+</board>
diff --git a/os/hal/boards/OLIMEX_STM32_H103/board.c b/os/hal/boards/OLIMEX_STM32_H103/board.c
new file mode 100644
index 000000000..bd21d1738
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_H103/board.c
@@ -0,0 +1,49 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_H103/board.h b/os/hal/boards/OLIMEX_STM32_H103/board.h
new file mode 100644
index 000000000..76c66099d
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_H103/board.h
@@ -0,0 +1,132 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM33-H103 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_H103
+#define BOARD_NAME              "Olimex STM32-H103"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON            0
+
+#define GPIOC_USB_DISC          11
+#define GPIOC_LED               12
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0  - Normal input      (BUTTON).
+ * PA2  - Alternate output  (USART2 TX).
+ * PA3  - Normal input      (USART2 RX).
+ */
+#define VAL_GPIOACRL            0x88884B84      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x88888888      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOBCRL            0x88888888      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x88888888      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC6  - Normal input because there is an external resistor.
+ * PC7  - Normal input because there is an external resistor.
+ * PC11 - Open Drain output (USB disconnect).
+ * PC12 - Push Pull output (LED).
+ */
+#define VAL_GPIOCCRL            0x44888888      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x88837888      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0  - Normal input (XTAL).
+ * PD1  - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL            0x88888844      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x88888888      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x88888888      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_H103/board.mk b/os/hal/boards/OLIMEX_STM32_H103/board.mk
new file mode 100644
index 000000000..5c7d1bf2f
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_H103/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_H103/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_H103
diff --git a/os/hal/boards/OLIMEX_STM32_H407/board.c b/os/hal/boards/OLIMEX_STM32_H407/board.c
new file mode 100644
index 000000000..989888ac0
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_H407/board.c
@@ -0,0 +1,107 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  static bool_t last_status = FALSE;
+
+  if (blkIsTransferring(sdcp))
+    return last_status;
+  return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_H407/board.h b/os/hal/boards/OLIMEX_STM32_H407/board.h
new file mode 100644
index 000000000..ea7734a14
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_H407/board.h
@@ -0,0 +1,1300 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Olimex STM32-H407 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_H407
+#define BOARD_NAME                  "Olimex STM32-H407"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID                MII_KS8721_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                12000000
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   330
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F40_41xxx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON_WKUP           0
+#define GPIOA_ETH_RMII_REF_CLK      1
+#define GPIOA_ETH_RMII_MDIO         2
+#define GPIOA_ETH_RMII_MDINT        3
+#define GPIOA_PIN4                  4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_ETH_RMII_CRS_DV       7
+#define GPIOA_USB_HS_BUSON          8
+#define GPIOA_OTG_FS_VBUS           9
+#define GPIOA_OTG_FS_ID             10
+#define GPIOA_OTG_FS_DM             11
+#define GPIOA_OTG_FS_DP             12
+#define GPIOA_JTAG_TMS              13
+#define GPIOA_JTAG_TCK              14
+#define GPIOA_JTAG_TDI              15
+
+#define GPIOB_USB_FS_BUSON          0
+#define GPIOB_USB_HS_FAULT          1
+#define GPIOB_BOOT1                 2
+#define GPIOB_JTAG_TDO              3
+#define GPIOB_JTAG_TRST             4
+#define GPIOB_PIN5                  5
+#define GPIOB_PIN6                  6
+#define GPIOB_PIN7                  7
+#define GPIOB_I2C1_SCL              8
+#define GPIOB_I2C1_SDA              9
+#define GPIOB_SPI2_SCK              10
+#define GPIOB_PIN11                 11
+#define GPIOB_OTG_HS_ID             12
+#define GPIOB_OTG_HS_VBUS           13
+#define GPIOB_OTG_HS_DM             14
+#define GPIOB_OTG_HS_DP             15
+
+#define GPIOC_PIN0                  0
+#define GPIOC_ETH_RMII_MDC          1
+#define GPIOC_SPI2_MISO             2
+#define GPIOC_SPI2_MOSI             3
+#define GPIOC_ETH_RMII_RXD0         4
+#define GPIOC_ETH_RMII_RXD1         5
+#define GPIOC_USART6_TX             6
+#define GPIOC_USART6_RX             7
+#define GPIOC_SD_D0                 8
+#define GPIOC_SD_D1                 9
+#define GPIOC_SD_D2                 10
+#define GPIOC_SD_D3                 11
+#define GPIOC_SD_CLK                12
+#define GPIOC_LED                   13
+#define GPIOC_OSC32_IN              14
+#define GPIOC_OSC32_OUT             15
+
+#define GPIOD_PIN0                  0
+#define GPIOD_PIN1                  1
+#define GPIOD_SD_CMD                2
+#define GPIOD_PIN3                  3
+#define GPIOD_PIN4                  4
+#define GPIOD_PIN5                  5
+#define GPIOD_PIN6                  6
+#define GPIOD_PIN7                  7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_PIN11                 11
+#define GPIOD_PIN12                 12
+#define GPIOD_PIN13                 13
+#define GPIOD_PIN14                 14
+#define GPIOD_PIN15                 15
+
+#define GPIOE_PIN0                  0
+#define GPIOE_PIN1                  1
+#define GPIOE_PIN2                  2
+#define GPIOE_PIN3                  3
+#define GPIOE_PIN4                  4
+#define GPIOE_PIN5                  5
+#define GPIOE_PIN6                  6
+#define GPIOE_PIN7                  7
+#define GPIOE_PIN8                  8
+#define GPIOE_PIN9                  9
+#define GPIOE_PIN10                 10
+#define GPIOE_PIN11                 11
+#define GPIOE_PIN12                 12
+#define GPIOE_PIN13                 13
+#define GPIOE_PIN14                 14
+#define GPIOE_PIN15                 15
+
+#define GPIOF_PIN0                  0
+#define GPIOF_PIN1                  1
+#define GPIOF_PIN2                  2
+#define GPIOF_PIN3                  3
+#define GPIOF_PIN4                  4
+#define GPIOF_PIN5                  5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_PIN9                  9
+#define GPIOF_PIN10                 10
+#define GPIOF_USB_FS_FAULT          11
+#define GPIOF_PIN12                 12
+#define GPIOF_PIN13                 13
+#define GPIOF_PIN14                 14
+#define GPIOF_PIN15                 15
+
+#define GPIOG_PIN0                  0
+#define GPIOG_PIN1                  1
+#define GPIOG_PIN2                  2
+#define GPIOG_PIN3                  3
+#define GPIOG_PIN4                  4
+#define GPIOG_PIN5                  5
+#define GPIOG_PIN6                  6
+#define GPIOG_PIN7                  7
+#define GPIOG_PIN8                  8
+#define GPIOG_PIN9                  9
+#define GPIOG_SPI2_CS               10
+#define GPIOG_ETH_RMII_TXEN         11
+#define GPIOG_PIN12                 12
+#define GPIOG_ETH_RMII_TXD0         13
+#define GPIOG_ETH_RMII_TXD1         14
+#define GPIOG_PIN15                 15
+
+#define GPIOH_OSC_IN                0
+#define GPIOH_OSC_OUT               1
+#define GPIOH_PIN2                  2
+#define GPIOH_PIN3                  3
+#define GPIOH_PIN4                  4
+#define GPIOH_PIN5                  5
+#define GPIOH_PIN6                  6
+#define GPIOH_PIN7                  7
+#define GPIOH_PIN8                  8
+#define GPIOH_PIN9                  9
+#define GPIOH_PIN10                 10
+#define GPIOH_PIN11                 11
+#define GPIOH_PIN12                 12
+#define GPIOH_PIN13                 13
+#define GPIOH_PIN14                 14
+#define GPIOH_PIN15                 15
+
+#define GPIOI_PIN0                  0
+#define GPIOI_PIN1                  1
+#define GPIOI_PIN2                  2
+#define GPIOI_PIN3                  3
+#define GPIOI_PIN4                  4
+#define GPIOI_PIN5                  5
+#define GPIOI_PIN6                  6
+#define GPIOI_PIN7                  7
+#define GPIOI_PIN8                  8
+#define GPIOI_PIN9                  9
+#define GPIOI_PIN10                 10
+#define GPIOI_PIN11                 11
+#define GPIOI_PIN12                 12
+#define GPIOI_PIN13                 13
+#define GPIOI_PIN14                 14
+#define GPIOI_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - BUTTON_WKUP               (input floating).
+ * PA1  - ETH_RMII_REF_CLK          (alternate 11).
+ * PA2  - ETH_RMII_MDIO             (alternate 11).
+ * PA3  - ETH_RMII_MDINT            (input floating).
+ * PA4  - PIN4                      (input pullup).
+ * PA5  - PIN5                      (input pullup).
+ * PA6  - PIN6                      (input pullup).
+ * PA7  - ETH_RMII_CRS_DV           (alternate 11).
+ * PA8  - USB_HS_BUSON              (output pushpull maximum).
+ * PA9  - OTG_FS_VBUS               (input pulldown).
+ * PA10 - OTG_FS_ID                 (alternate 10).
+ * PA11 - OTG_FS_DM                 (alternate 10).
+ * PA12 - OTG_FS_DP                 (alternate 10).
+ * PA13 - JTAG_TMS                  (alternate 0).
+ * PA14 - JTAG_TCK                  (alternate 0).
+ * PA15 - JTAG_TDI                  (alternate 0).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) |    \
+                                     PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) |\
+                                     PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) |\
+                                     PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
+                                     PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\
+                                     PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) |  \
+                                     PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) |    \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) |   \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) |   \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_WKUP) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_REF_CLK) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDIO) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDINT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_100M(GPIOA_BUTTON_WKUP) |   \
+                                     PIN_OSPEED_100M(GPIOA_ETH_RMII_REF_CLK) |\
+                                     PIN_OSPEED_100M(GPIOA_ETH_RMII_MDIO) | \
+                                     PIN_OSPEED_100M(GPIOA_ETH_RMII_MDINT) |\
+                                     PIN_OSPEED_100M(GPIOA_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOA_ETH_RMII_CRS_DV) |\
+                                     PIN_OSPEED_100M(GPIOA_USB_HS_BUSON) |  \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_VBUS) |   \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_ID) |     \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DM) |     \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DP) |     \
+                                     PIN_OSPEED_100M(GPIOA_JTAG_TMS) |      \
+                                     PIN_OSPEED_100M(GPIOA_JTAG_TCK) |      \
+                                     PIN_OSPEED_100M(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_BUTTON_WKUP) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_REF_CLK) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDIO) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDINT) |\
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\
+                                     PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) |   \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) |   \
+                                     PIN_PUPDR_FLOATING(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_BUTTON_WKUP) |      \
+                                     PIN_ODR_HIGH(GPIOA_ETH_RMII_REF_CLK) | \
+                                     PIN_ODR_HIGH(GPIOA_ETH_RMII_MDIO) |    \
+                                     PIN_ODR_HIGH(GPIOA_ETH_RMII_MDINT) |   \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) |  \
+                                     PIN_ODR_HIGH(GPIOA_USB_HS_BUSON) |     \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) |      \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_ID) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DP) |        \
+                                     PIN_ODR_HIGH(GPIOA_JTAG_TMS) |         \
+                                     PIN_ODR_HIGH(GPIOA_JTAG_TCK) |         \
+                                     PIN_ODR_HIGH(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_BUTTON_WKUP, 0) |    \
+                                     PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) |\
+                                     PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \
+                                     PIN_AFIO_AF(GPIOA_ETH_RMII_MDINT, 0) | \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) |   \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) |    \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) |       \
+                                     PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) |       \
+                                     PIN_AFIO_AF(GPIOA_JTAG_TDI, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - USB_FS_BUSON              (output pushpull maximum).
+ * PB1  - USB_HS_FAULT              (input floating).
+ * PB2  - BOOT1                     (input floating).
+ * PB3  - JTAG_TDO                  (alternate 0).
+ * PB4  - JTAG_TRST                 (alternate 0).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - PIN6                      (input pullup).
+ * PB7  - PIN7                      (input pullup).
+ * PB8  - I2C1_SCL                  (alternate 4).
+ * PB9  - I2C1_SDA                  (alternate 4).
+ * PB10 - SPI2_SCK                  (alternate 5).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - OTG_HS_ID                 (alternate 12).
+ * PB13 - OTG_HS_VBUS               (input pulldown).
+ * PB14 - OTG_HS_DM                 (alternate 12).
+ * PB15 - OTG_HS_DP                 (alternate 12).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) |  \
+                                     PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) |   \
+                                     PIN_MODE_INPUT(GPIOB_BOOT1) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) |  \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) |   \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) |  \
+                                     PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) |    \
+                                     PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_BUSON) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) |  \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_100M(GPIOB_USB_FS_BUSON) |  \
+                                     PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) |  \
+                                     PIN_OSPEED_100M(GPIOB_BOOT1) |         \
+                                     PIN_OSPEED_100M(GPIOB_JTAG_TDO) |      \
+                                     PIN_OSPEED_100M(GPIOB_JTAG_TRST) |     \
+                                     PIN_OSPEED_100M(GPIOB_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOB_I2C1_SCL) |      \
+                                     PIN_OSPEED_100M(GPIOB_I2C1_SDA) |      \
+                                     PIN_OSPEED_100M(GPIOB_SPI2_SCK) |      \
+                                     PIN_OSPEED_100M(GPIOB_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_ID) |     \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_VBUS) |   \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_DM) |     \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_FLOATING(GPIOB_USB_FS_BUSON) |\
+                                     PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\
+                                     PIN_PUPDR_FLOATING(GPIOB_BOOT1) |      \
+                                     PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) |  \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) |   \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) |  \
+                                     PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\
+                                     PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_USB_FS_BUSON) |     \
+                                     PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) |     \
+                                     PIN_ODR_HIGH(GPIOB_BOOT1) |            \
+                                     PIN_ODR_HIGH(GPIOB_JTAG_TDO) |         \
+                                     PIN_ODR_HIGH(GPIOB_JTAG_TRST) |        \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_I2C1_SCL) |         \
+                                     PIN_ODR_HIGH(GPIOB_I2C1_SDA) |         \
+                                     PIN_ODR_HIGH(GPIOB_SPI2_SCK) |         \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_ID) |        \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) |      \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0) |   \
+                                     PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) |   \
+                                     PIN_AFIO_AF(GPIOB_BOOT1, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) |       \
+                                     PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) |      \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) |       \
+                                     PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) |       \
+                                     PIN_AFIO_AF(GPIOB_SPI2_SCK, 5) |       \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) |     \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0) |    \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) |     \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - PIN0                      (input pullup).
+ * PC1  - ETH_RMII_MDC              (alternate 11).
+ * PC2  - SPI2_MISO                 (alternate 5).
+ * PC3  - SPI2_MOSI                 (alternate 5).
+ * PC4  - ETH_RMII_RXD0             (alternate 11).
+ * PC5  - ETH_RMII_RXD1             (alternate 11).
+ * PC6  - USART6_TX                 (alternate 8).
+ * PC7  - USART6_RX                 (alternate 8).
+ * PC8  - SD_D0                     (alternate 12).
+ * PC9  - SD_D1                     (alternate 12).
+ * PC10 - SD_D2                     (alternate 12).
+ * PC11 - SD_D3                     (alternate 12).
+ * PC12 - SD_CLK                    (alternate 12).
+ * PC13 - LED                       (output pushpull maximum).
+ * PC14 - OSC32_IN                  (input floating).
+ * PC15 - OSC32_OUT                 (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \
+                                     PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) |\
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI2_MISO) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI2_MOSI) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) |\
+                                     PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) |\
+                                     PIN_MODE_ALTERNATE(GPIOC_USART6_TX) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_USART6_RX) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_D0) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_D1) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_D2) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_D3) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_SD_CLK) |     \
+                                     PIN_MODE_OUTPUT(GPIOC_LED) |           \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_MDC) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MISO) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MOSI) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD0) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD1) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_USART6_TX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_USART6_RX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_LED) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_100M(GPIOC_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOC_ETH_RMII_MDC) |  \
+                                     PIN_OSPEED_100M(GPIOC_SPI2_MISO) |     \
+                                     PIN_OSPEED_100M(GPIOC_SPI2_MOSI) |     \
+                                     PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD0) | \
+                                     PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD1) | \
+                                     PIN_OSPEED_100M(GPIOC_USART6_TX) |     \
+                                     PIN_OSPEED_100M(GPIOC_USART6_RX) |     \
+                                     PIN_OSPEED_100M(GPIOC_SD_D0) |         \
+                                     PIN_OSPEED_100M(GPIOC_SD_D1) |         \
+                                     PIN_OSPEED_100M(GPIOC_SD_D2) |         \
+                                     PIN_OSPEED_100M(GPIOC_SD_D3) |         \
+                                     PIN_OSPEED_100M(GPIOC_SD_CLK) |        \
+                                     PIN_OSPEED_100M(GPIOC_LED) |           \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_IN) |      \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_MDC) |\
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI2_MISO) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI2_MOSI) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD0) |\
+                                     PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD1) |\
+                                     PIN_PUPDR_FLOATING(GPIOC_USART6_TX) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_USART6_RX) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_D0) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_D1) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_D2) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_D3) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_SD_CLK) |     \
+                                     PIN_PUPDR_FLOATING(GPIOC_LED) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOC_ETH_RMII_MDC) |     \
+                                     PIN_ODR_HIGH(GPIOC_SPI2_MISO) |        \
+                                     PIN_ODR_HIGH(GPIOC_SPI2_MOSI) |        \
+                                     PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD0) |    \
+                                     PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD1) |    \
+                                     PIN_ODR_HIGH(GPIOC_USART6_TX) |        \
+                                     PIN_ODR_HIGH(GPIOC_USART6_RX) |        \
+                                     PIN_ODR_HIGH(GPIOC_SD_D0) |            \
+                                     PIN_ODR_HIGH(GPIOC_SD_D1) |            \
+                                     PIN_ODR_HIGH(GPIOC_SD_D2) |            \
+                                     PIN_ODR_HIGH(GPIOC_SD_D3) |            \
+                                     PIN_ODR_HIGH(GPIOC_SD_CLK) |           \
+                                     PIN_ODR_HIGH(GPIOC_LED) |              \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) |  \
+                                     PIN_AFIO_AF(GPIOC_SPI2_MISO, 5) |      \
+                                     PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5) |      \
+                                     PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \
+                                     PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \
+                                     PIN_AFIO_AF(GPIOC_USART6_TX, 8) |      \
+                                     PIN_AFIO_AF(GPIOC_USART6_RX, 8))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_SD_D0, 12) |         \
+                                     PIN_AFIO_AF(GPIOC_SD_D1, 12) |         \
+                                     PIN_AFIO_AF(GPIOC_SD_D2, 12) |         \
+                                     PIN_AFIO_AF(GPIOC_SD_D3, 12) |         \
+                                     PIN_AFIO_AF(GPIOC_SD_CLK, 12) |        \
+                                     PIN_AFIO_AF(GPIOC_LED, 0) |            \
+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0) |       \
+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - SD_CMD                    (alternate 12).
+ * PD3  - PIN3                      (input pullup).
+ * PD4  - PIN4                      (input pullup).
+ * PD5  - PIN5                      (input pullup).
+ * PD6  - PIN6                      (input pullup).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - PIN12                     (input pullup).
+ * PD13 - PIN13                     (input pullup).
+ * PD14 - PIN14                     (input pullup).
+ * PD15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_ALTERNATE(GPIOD_SD_CMD) |     \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_100M(GPIOD_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOD_SD_CMD) |        \
+                                     PIN_OSPEED_100M(GPIOD_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_SD_CMD) |     \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_SD_CMD) |           \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_SD_CMD, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0  - PIN0                      (input pullup).
+ * PE1  - PIN1                      (input pullup).
+ * PE2  - PIN2                      (input pullup).
+ * PE3  - PIN3                      (input pullup).
+ * PE4  - PIN4                      (input pullup).
+ * PE5  - PIN5                      (input pullup).
+ * PE6  - PIN6                      (input pullup).
+ * PE7  - PIN7                      (input pullup).
+ * PE8  - PIN8                      (input pullup).
+ * PE9  - PIN9                      (input pullup).
+ * PE10 - PIN10                     (input pullup).
+ * PE11 - PIN11                     (input pullup).
+ * PE12 - PIN12                     (input pullup).
+ * PE13 - PIN13                     (input pullup).
+ * PE14 - PIN14                     (input pullup).
+ * PE15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_100M(GPIOE_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_PULLUP(GPIOE_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0  - PIN0                      (input pullup).
+ * PF1  - PIN1                      (input pullup).
+ * PF2  - PIN2                      (input pullup).
+ * PF3  - PIN3                      (input pullup).
+ * PF4  - PIN4                      (input pullup).
+ * PF5  - PIN5                      (input pullup).
+ * PF6  - PIN6                      (input pullup).
+ * PF7  - PIN7                      (input pullup).
+ * PF8  - PIN8                      (input pullup).
+ * PF9  - PIN9                      (input pullup).
+ * PF10 - PIN10                     (input pullup).
+ * PF11 - USB_FS_FAULT              (input floating).
+ * PF12 - PIN12                     (input pullup).
+ * PF13 - PIN13                     (input pullup).
+ * PF14 - PIN14                     (input pullup).
+ * PF15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_USB_FS_FAULT) |   \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_100M(GPIOF_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOF_USB_FS_FAULT) |  \
+                                     PIN_OSPEED_100M(GPIOF_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_PULLUP(GPIOF_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \
+                                     PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT) |\
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_USB_FS_FAULT) |     \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_USB_FS_FAULT, 0) |   \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0  - PIN0                      (input pullup).
+ * PG1  - PIN1                      (input pullup).
+ * PG2  - PIN2                      (input pullup).
+ * PG3  - PIN3                      (input pullup).
+ * PG4  - PIN4                      (input pullup).
+ * PG5  - PIN5                      (input pullup).
+ * PG6  - PIN6                      (input pullup).
+ * PG7  - PIN7                      (input pullup).
+ * PG8  - PIN8                      (input pullup).
+ * PG9  - PIN9                      (input pullup).
+ * PG10 - SPI2_CS                   (output pushpull maximum).
+ * PG11 - ETH_RMII_TXEN             (alternate 11).
+ * PG12 - PIN12                     (input pullup).
+ * PG13 - ETH_RMII_TXD0             (alternate 11).
+ * PG14 - ETH_RMII_TXD1             (alternate 11).
+ * PG15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOG_MODER             (PIN_MODE_INPUT(GPIOG_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN9) |           \
+                                     PIN_MODE_OUTPUT(GPIOG_SPI2_CS) |       \
+                                     PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXEN) |\
+                                     PIN_MODE_INPUT(GPIOG_PIN12) |          \
+                                     PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) |\
+                                     PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) |\
+                                     PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_SPI2_CS) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXEN) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD0) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD1) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_100M(GPIOG_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOG_SPI2_CS) |       \
+                                     PIN_OSPEED_100M(GPIOG_ETH_RMII_TXEN) | \
+                                     PIN_OSPEED_100M(GPIOG_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD0) | \
+                                     PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD1) | \
+                                     PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_PULLUP(GPIOG_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN9) |         \
+                                     PIN_PUPDR_FLOATING(GPIOG_SPI2_CS) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXEN) |\
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN12) |        \
+                                     PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD0) |\
+                                     PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD1) |\
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOG_SPI2_CS) |          \
+                                     PIN_ODR_HIGH(GPIOG_ETH_RMII_TXEN) |    \
+                                     PIN_ODR_HIGH(GPIOG_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD0) |    \
+                                     PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD1) |    \
+                                     PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_SPI2_CS, 0) |        \
+                                     PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11) | \
+                                     PIN_AFIO_AF(GPIOG_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \
+                                     PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11) | \
+                                     PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0  - OSC_IN                    (input floating).
+ * PH1  - OSC_OUT                   (input floating).
+ * PH2  - PIN2                      (input pullup).
+ * PH3  - PIN3                      (input pullup).
+ * PH4  - PIN4                      (input pullup).
+ * PH5  - PIN5                      (input pullup).
+ * PH6  - PIN6                      (input pullup).
+ * PH7  - PIN7                      (input pullup).
+ * PH8  - PIN8                      (input pullup).
+ * PH9  - PIN9                      (input pullup).
+ * PH10 - PIN10                     (input pullup).
+ * PH11 - PIN11                     (input pullup).
+ * PH12 - PIN12                     (input pullup).
+ * PH13 - PIN13                     (input pullup).
+ * PH14 - PIN14                     (input pullup).
+ * PH15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_100M(GPIOH_OSC_IN) |        \
+                                     PIN_OSPEED_100M(GPIOH_OSC_OUT) |       \
+                                     PIN_OSPEED_100M(GPIOH_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOH_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0  - PIN0                      (input pullup).
+ * PI1  - PIN1                      (input pullup).
+ * PI2  - PIN2                      (input pullup).
+ * PI3  - PIN3                      (input pullup).
+ * PI4  - PIN4                      (input pullup).
+ * PI5  - PIN5                      (input pullup).
+ * PI6  - PIN6                      (input pullup).
+ * PI7  - PIN7                      (input pullup).
+ * PI8  - PIN8                      (input pullup).
+ * PI9  - PIN9                      (input pullup).
+ * PI10 - PIN10                     (input pullup).
+ * PI11 - PIN11                     (input pullup).
+ * PI12 - PIN12                     (input pullup).
+ * PI13 - PIN13                     (input pullup).
+ * PI14 - PIN14                     (input pullup).
+ * PI15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOI_MODER             (PIN_MODE_INPUT(GPIOI_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR           (PIN_OSPEED_100M(GPIOI_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR             (PIN_PUPDR_PULLUP(GPIOI_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR               (PIN_ODR_HIGH(GPIOI_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL              (PIN_AFIO_AF(GPIOI_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH              (PIN_AFIO_AF(GPIOI_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_H407/board.mk b/os/hal/boards/OLIMEX_STM32_H407/board.mk
new file mode 100644
index 000000000..8bd37d59d
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_H407/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_H407/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_H407
diff --git a/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg b/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg
new file mode 100644
index 000000000..8b4cda0b9
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg
@@ -0,0 +1,341 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F4xx board Template -->
+<board xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+    xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+  <configuration_settings>
+    <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+    <output_path>..</output_path>
+  </configuration_settings>
+    <board_name>Olimex STM32-H407</board_name>
+    <board_id>OLIMEX_STM32_H407</board_id>
+    <board_functions>
+        <sdc_lld_is_card_inserted><![CDATA[  static bool_t last_status = FALSE;
+
+  if (blkIsTransferring(sdcp))
+    return last_status;
+  return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
+        <sdc_lld_is_write_protected>
+<![CDATA[  (void)sdcp;
+  return FALSE;]]></sdc_lld_is_write_protected>
+    </board_functions>
+    <ethernet_phy>
+        <identifier>MII_KS8721_ID</identifier>
+        <bus_type>RMII</bus_type>
+    </ethernet_phy>
+    <subtype>STM32F40_41xxx</subtype>
+    <clocks
+       HSEFrequency="12000000"
+       HSEBypass="false"
+       LSEFrequency="32768"
+       LSEBypass="false"
+       VDD="330"
+    />
+    <ports>
+        <GPIOA>
+            <pin0 ID="BUTTON_WKUP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="ETH_RMII_REF_CLK" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin2 ID="ETH_RMII_MDIO" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin3 ID="ETH_RMII_MDINT" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="ETH_RMII_CRS_DV" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin8 ID="USB_HS_BUSON" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Output" Alternate="0" />
+            <pin9 ID="OTG_FS_VBUS" Type="PushPull" Speed="Maximum" Resistor="PullDown"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="OTG_FS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="10" />
+            <pin11 ID="OTG_FS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="10" />
+            <pin12 ID="OTG_FS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="10" />
+            <pin13 ID="JTAG_TMS" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="0" />
+            <pin14 ID="JTAG_TCK" Type="PushPull" Speed="Maximum" Resistor="PullDown"
+                Level="High" Mode="Alternate" Alternate="0" />
+            <pin15 ID="JTAG_TDI" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="0" />
+        </GPIOA>
+        <GPIOB>
+            <pin0 ID="USB_FS_BUSON" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Output" Alternate="0" />
+            <pin1 ID="USB_HS_FAULT" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="BOOT1" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="JTAG_TDO" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="0" />
+            <pin4 ID="JTAG_TRST" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="I2C1_SCL" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="4" />
+            <pin9 ID="I2C1_SDA" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="4" />
+            <pin10 ID="SPI2_SCK" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="5" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="OTG_HS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin13 ID="OTG_HS_VBUS" Type="PushPull" Speed="Maximum"
+                Resistor="PullDown" Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="OTG_HS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin15 ID="OTG_HS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+        </GPIOB>
+        <GPIOC>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="ETH_RMII_MDC" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin2 ID="SPI2_MISO" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="5" />
+            <pin3 ID="SPI2_MOSI" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="5" />
+            <pin4 ID="ETH_RMII_RXD0" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin5 ID="ETH_RMII_RXD1" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin6 ID="USART6_TX" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="8" />
+            <pin7 ID="USART6_RX" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="8" />
+            <pin8 ID="SD_D0" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin9 ID="SD_D1" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin10 ID="SD_D2" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin11 ID="SD_D3" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin12 ID="SD_CLK" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin13 ID="LED" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Output" Alternate="0" />
+            <pin14 ID="OSC32_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="OSC32_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOC>
+        <GPIOD>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="SD_CMD" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Alternate" Alternate="12" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOD>
+        <GPIOE>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOE>
+        <GPIOF>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="USB_FS_FAULT" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOF>
+        <GPIOG>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="SPI2_CS" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Output" Alternate="0" />
+            <pin11 ID="ETH_RMII_TXEN" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="ETH_RMII_TXD0" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin14 ID="ETH_RMII_TXD1" Type="PushPull" Speed="Maximum"
+                Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOG>
+        <GPIOH>
+            <pin0 ID="OSC_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0"></pin0>
+            <pin1 ID="OSC_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOH>
+        <GPIOI>
+            <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+            <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+                Level="High" Mode="Input" Alternate="0" />
+        </GPIOI>
+    </ports>
+</board>
diff --git a/os/hal/boards/OLIMEX_STM32_LCD/board.c b/os/hal/boards/OLIMEX_STM32_LCD/board.c
new file mode 100644
index 000000000..c31c076a2
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_LCD/board.c
@@ -0,0 +1,87 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+  {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
+  {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  (void)sdcp;
+
+  return TRUE;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+  (void)sdcp;
+
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+
+  return TRUE;
+}
+
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+
+  return FALSE;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
+
diff --git a/os/hal/boards/OLIMEX_STM32_LCD/board.h b/os/hal/boards/OLIMEX_STM32_LCD/board.h
new file mode 100644
index 000000000..0d510abac
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_LCD/board.h
@@ -0,0 +1,196 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM32-LCD proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_LCD
+#define BOARD_NAME              "Olimex STM32-LCD"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_HD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_SPI1NSS           4
+
+#define GPIOB_SPI2NSS           12
+
+#define GPIOA_USB_P             0
+#define GPIOD_USB_DISC          2
+
+#define GPIOE_TFT_RST			2
+#define GPIOD_TFT_LIGHT			13
+#define GPIOC_TFT_YD			0
+#define GPIOC_TFT_YU			1
+#define GPIOC_TFT_XL			2
+#define GPIOC_TFT_XR			3
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0  - Normal input      (USB P).
+ * PA2  - Alternate output  (USART2 TX).
+ * PA3  - Normal input      (USART2 RX).
+ * PA11 - Normal input      (USB DM).
+ * PA12 - Normal input      (USB DP).
+ */
+#define VAL_GPIOACRL            0x88884B84      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x88844888      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOBCRL            0x88888888      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x88888888      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC0  - Analog Input		(TP_YD).
+ * PC1  - Analog Input		(TP_YU).
+ * PC2  - Analog Input		(TP_XL).
+ * PC3  - Analog Input		(TP_XR).
+ * PC8  - Alternate PP 50M	(SD_D0).
+ * PC9  - Alternate PP 50M	(SD_D1).
+ * PC10 - Alternate PP 50M	(SD_D2).
+ * PC11 - Alternate PP 50M	(SD_D3).
+ * PC12 - Alternate PP 50M	(SD_CLK).
+ * PC14 - Normal input		(XTAL).
+ * PC15 - Normal input		(XTAL).
+ */
+#define VAL_GPIOCCRL            0x88880000      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x448BBBBB	    /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD2  - Alternate PP 50M	(SD_CMD)
+ * PD0  - Alternate PP 50M  (FSMC_D2)
+ * PD1  - Alternate PP 50M  (FSMC_D3)
+ * PD4  - Alternate PP 50M	(TFT_RD)
+ * PD5  - Alternate PP 50M	(TFT_WR)
+ * PD7  - Alternate PP 50M  (TFT_CS)
+ * PD8  - Alternate PP 50M  (FSMC_D13)
+ * PD9  - Alternate PP 50M  (FSMC_D14)
+ * PD10 - Alternate PP 50M  (FSMC_D15)
+ * PD14 - Alternate PP 50M  (FSMC_D0)
+ * PD15 - Alternate PP 50M  (FSMC_D1)
+ */
+#define VAL_GPIODCRL            0xBBBB8BBB      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0xBB388BBB      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ * PE2  - Digital Output	(TFT_RST)
+ * PE3  - Alternate PP 50M  (TFT_RS)
+ * PE7  - Alternate PP 50M	(FSMC_D4)
+ * PE8  - Alternate PP 50M  (FSMC_D5)
+ * PE9  - Alternate PP 50M  (FSMC_D6)
+ * PE10 - Alternate PP 50M  (FSMC_D7)
+ * PE11 - Alternate PP 50M  (FSMC_D8)
+ * PE12 - Alternate PP 50M  (FSMC_D9)
+ * PE13 - Alternate PP 50M  (FSMC_D10)
+ * PE14 - Alternate PP 50M  (FSMC_D11)
+ * PE15 - Alternate PP 50M  (FSMC_D12)
+ */
+#define VAL_GPIOECRL            0xB888B388      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0xBBBBBBBB      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+/*
+ * Port F setup.
+ * Everything input with pull-up expect:
+ */
+#define VAL_GPIOFCRL            0x88888888      /*  PF7...PF0 */
+#define VAL_GPIOFCRH            0x88888888      /* PF15...PF8 */
+#define VAL_GPIOFODR            0xFFFFFFFF
+
+/*
+ * Port G setup.
+ * Everything input with pull-up expect:
+ */
+#define VAL_GPIOGCRL            0x88888888      /*  PG7...PG0 */
+#define VAL_GPIOGCRH            0x88888888      /* PG15...PG8 */
+#define VAL_GPIOGODR            0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOD, GPIOD_USB_DISC)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOD, GPIOD_USB_DISC)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_LCD/board.mk b/os/hal/boards/OLIMEX_STM32_LCD/board.mk
new file mode 100644
index 000000000..f9e41b7de
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_LCD/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_LCD/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_LCD
diff --git a/os/hal/boards/OLIMEX_STM32_P103/board.c b/os/hal/boards/OLIMEX_STM32_P103/board.c
new file mode 100644
index 000000000..9b17ced7f
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_P103/board.c
@@ -0,0 +1,64 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return palReadPad(GPIOC, GPIOC_MMCCP);
+}
+
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return !palReadPad(GPIOC, GPIOC_MMCWP);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_P103/board.h b/os/hal/boards/OLIMEX_STM32_P103/board.h
new file mode 100644
index 000000000..58f020bcc
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_P103/board.h
@@ -0,0 +1,156 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM32-P103 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_P103
+#define BOARD_NAME              "Olimex STM32-P103"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON            0
+#define GPIOA_SPI1NSS           4
+
+#define GPIOB_SPI2NSS           12
+
+#define GPIOC_USB_P             4
+#define GPIOC_MMCWP             6
+#define GPIOC_MMCCP             7
+#define GPIOC_CAN_CNTL          10
+#define GPIOC_USB_DISC          11
+#define GPIOC_LED               12
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0  - Normal input      (BUTTON).
+ * PA2  - Alternate output  (USART2 TX).
+ * PA3  - Normal input      (USART2 RX).
+ * PA11 - Normal input      (USB DM).
+ * PA12 - Normal input      (USB DP).
+ */
+#define VAL_GPIOACRL            0x88884B84      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x88844888      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB13 - Alternate output  (MMC SPI2 SCK).
+ * PB14 - Normal input      (MMC SPI2 MISO).
+ * PB15 - Alternate output  (MMC SPI2 MOSI).
+ */
+#define VAL_GPIOBCRL            0x88888888      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0xB4B88888      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC4  - Normal input because there is an external resistor.
+ * PC6  - Normal input because there is an external resistor.
+ * PC7  - Normal input because there is an external resistor.
+ * PC10 - Push Pull output (CAN CNTRL).
+ * PC11 - Push Pull output (USB DISC).
+ * PC12 - Push Pull output (LED).
+ */
+#define VAL_GPIOCCRL            0x44848888      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x88833388      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0  - Normal input (XTAL).
+ * PD1  - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL            0x88888844      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x88888888      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x88888888      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_P103/board.mk b/os/hal/boards/OLIMEX_STM32_P103/board.mk
new file mode 100644
index 000000000..0b0857ea7
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_P103/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_P103/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_P103
diff --git a/os/hal/boards/OLIMEX_STM32_P107/board.c b/os/hal/boards/OLIMEX_STM32_P107/board.c
new file mode 100644
index 000000000..e2acd00c3
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_P107/board.c
@@ -0,0 +1,83 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/*
+ * Card detection through the card internal pull-up on D3.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  static bool last_status = FALSE;
+
+  (void)mmcp;
+  if ((palReadLatch(GPIOA) & PAL_PORT_BIT(GPIOA_SPI3_CS_MMC)) == 0)
+    return last_status;
+  return last_status = (bool)palReadPad(GPIOA, GPIOA_SPI3_CS_MMC);
+}
+
+/*
+ * Card write protection detection is not possible, the card is always
+ * reported as not protected.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return FALSE;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * Several I/O pins are re-mapped:
+   *   USART3 to the PD8/PD9 pins.
+   *   I2C1 to the PB8/PB9 pins.
+   *   SPI3 to the PC10/PC11/PC12 pins.
+   */
+  AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_FULLREMAP |
+                AFIO_MAPR_I2C1_REMAP |
+                AFIO_MAPR_SPI3_REMAP;
+}
diff --git a/os/hal/boards/OLIMEX_STM32_P107/board.h b/os/hal/boards/OLIMEX_STM32_P107/board.h
new file mode 100644
index 000000000..8bf523d33
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_P107/board.h
@@ -0,0 +1,193 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM32-P107 Rev.A evaluation board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_P107_REV_A
+#define BOARD_NAME              "Olimex STM32-P107 Rev.A"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            25000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_CL
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID            MII_STE101P_ID
+#define BOARD_PHY_RMII
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_SWITCH_WKUP       0
+#define GPIOA_SPI3_CS_MMC       4
+#define GPIOC_LED_STATUS1       6
+#define GPIOC_LED_STATUS2       7
+#define GPIOC_SWITCH_TAMPER     13
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0  - Normal input      (WKUP BUTTON).
+ * PA1  - Normal input      (ETH_RMII_REF_CLK).
+ * PA2  - Alternate output  (ETH_RMII_MDIO).
+ * PA3  - Input with PU     (unconnected).
+ * PA4  - Open Drain output (CS_MMC).
+ * PA5  - Input with PU     (unconnected).
+ * PA6  - Input with PU     (unconnected).
+ * PA7  - Normal input      (ETH_RMII_CRS_DV).
+ * PA8  - Alternate output  (MCO).
+ * PA9  - Normal input      (OTG_VBUS).
+ * PA10 - Normal input      (OTG_ID).
+ * PA11 - Normal input      (OTG_DM).
+ * PA12 - Normal input      (OTG_DP).
+ * PA13 - Normal input      (TMS).
+ * PA14 - Normal input      (TCK).
+ * PA15 - Normal input      (TDI).
+ */
+#define VAL_GPIOACRL            0x48878B44      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x4444444B      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/*
+ * Port B setup:
+ * PB0  - Input with PU     (unconnected).
+ * PB1  - Input with PU     (unconnected).
+ * PB2  - Normal input      (BOOT1).
+ * PB3  - Normal input      (TDO).
+ * PB4  - Normal input      (TRST).
+ * PB5  - Input with PU     (unconnected).
+ * PB6  - Input with PU     (unconnected).
+ * PB7  - Input with PU     (unconnected).
+ * PB8  - Alternate O.D.    (I2C1 SCL, remapped).
+ * PB9  - Alternate O.D.    (I2C1 SDA, remapped).
+ * PB10 - Input with PU     (unconnected).
+ * PB11 - Alternate output  (ETH_RMII_TX_EN).
+ * PB12 - Alternate output  (ETH_RMII_TXD0).
+ * PB13 - Alternate output  (ETH_RMII_TXD1).
+ * PB14 - Input with PU     (unconnected).
+ * PB15 - Push Pull output  (CS_UEXT).
+ */
+#define VAL_GPIOBCRL            0x88844488      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x38BBB8FF      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+
+/*
+ * Port C setup:
+ * PC0  - Input with PU     (unconnected).
+ * PC1  - Alternate output  (ETH_MDC).
+ * PC2  - Input with PU     (unconnected).
+ * PC3  - Input with PU     (unconnected).
+ * PC4  - Normal input      (ETH_RMII_RXD0).
+ * PC5  - Normal input      (ETH_RMII_RXD1).
+ * PC6  - Push Pull output  (STAT1 green LED).
+ * PC7  - Push Pull output  (STAT2 yellow LED).
+ * PC8  - Input with PU     (unconnected).
+ * PC9  - Input with PU     (unconnected).
+ * PC10 - Alternate output  (SPI3 SCK).
+ * PC11 - Input with PU     (SPI3 MISO).
+ * PC12 - Alternate output  (SPI3 MOSI).
+ * PC13 - Normal input      (TAMPER).
+ * PC14 - Normal input      (OSC32 IN).
+ * PC15 - Normal input      (OSC32 OUT).
+ */
+#define VAL_GPIOCCRL            0x334488B8      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x444B8B88      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFF3F
+
+/*
+ * Port D setup:
+ * PD0  - Input with PU     (unconnected).
+ * PD1  - Input with PU     (unconnected).
+ * PD2  - Input with PU     (unconnected).
+ * PD3  - Input with PU     (unconnected).
+ * PD4  - Input with PU     (unconnected).
+ * PD5  - Alternate output  (USART2 TX, UEXT).
+ * PD6  - Input with PU     (USART2 RX, UEXT).
+ * PD7  - Push Pull output  (USB_VBUSON).
+ * PD8  - Alternate output  (USART2 TX, remapped).
+ * PD9  - Normal input      (USART2 RX, remapped).
+ * PD10 - Input with PU     (unconnected).
+ * PD11 - Normal input      (USART2 CTS, remapped).
+ * PD12 - Alternate output  (USART2 RTS, remapped).
+ * PD13 - Input with PU     (unconnected).
+ * PD14 - Input with PU     (unconnected).
+ * PD15 - Input with PU     (unconnected).
+ */
+#define VAL_GPIODCRL            0x38B88888      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x888B484B      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ * PE14 - Normal input      (ETH_RMII_MDINT).
+ * PE15 - Normal input      (USB_FAULT).
+ */
+#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x44888888      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_P107/board.mk b/os/hal/boards/OLIMEX_STM32_P107/board.mk
new file mode 100644
index 000000000..a243091b4
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_P107/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_P107/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_P107
diff --git a/os/hal/boards/OLIMEX_STM32_P407/board.c b/os/hal/boards/OLIMEX_STM32_P407/board.c
new file mode 100644
index 000000000..bb2732da2
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_P407/board.c
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  static bool last_status = FALSE;
+  (void)mmcp;
+
+  if ((palReadLatch(GPIOD) & PAL_PORT_BIT(GPIOD_SPI3_CS)) == 0)
+    return last_status;
+  return last_status = (bool)palReadPad(GPIOD, GPIOD_SPI3_CS);
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_P407/board.h b/os/hal/boards/OLIMEX_STM32_P407/board.h
new file mode 100644
index 000000000..c43368dfd
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_P407/board.h
@@ -0,0 +1,651 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Olimex STM32-P407 board.
+ * NOTE: Part of JTAG signals are used for other functions, this board can be
+ *       used using SWD only.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_P407
+#define BOARD_NAME              "Olimex STM32-P407"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID            MII_KS8721_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board frequencies.
+ * NOTE: The LSE crystal is not fitted by default on the board.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            25000000
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD               330
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F40_41xxx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON_WKUP       0
+#define GPIOA_ETH_RMII_REF_CLK  1
+#define GPIOA_ETH_RMII_MDIO     2
+#define GPIOA_ETH_RMII_MDINT    3
+#define GPIOA_DCMI_HSYNC        4
+#define GPIOA_LCD_SCK           5
+#define GPIOA_DCMI_PIXCLK       6
+#define GPIOA_ETH_RMII_CRS_DV   7
+#define GPIOA_MCO1              8
+#define GPIOA_OTG_FS_VBUS       9
+#define GPIOA_DCMI_D1           10
+#define GPIOA_OTG_FS_DM         11
+#define GPIOA_OTG_FS_DP         12
+#define GPIOA_SWDIO             13
+#define GPIOA_SWCLK             14
+#define GPIOA_I2S3_WS           15
+
+#define GPIOB_LCD_BL            0
+#define GPIOB_BUZ               1
+#define GPIOB_CAM_ENB           2
+#define GPIOB_I2S3_CK           3
+#define GPIOB_LCD_MISO          4
+#define GPIOB_I2S3_SD           5
+#define GPIOB_DCMI_D5           6
+#define GPIOB_DCMI_VSYNC        7
+#define GPIOB_CAN1_RX           8
+#define GPIOB_CAN1_TX           9
+#define GPIOB_USB_FS_FAULT      10
+#define GPIOB_ETH_RMII_TX_EN    11
+#define GPIOB_OTG_HS_ID         12
+#define GPIOB_OTG_HS_VBUS       13
+#define GPIOB_OTG_HS_DM         14
+#define GPIOB_OTG_HS_DP         15
+
+#define GPIOC_TRIM              0
+#define GPIOC_ETH_RMII_MDC      1
+#define GPIOC_USB_FS_VBUSON     2
+#define GPIOC_LCD_MOSI          3
+#define GPIOC_ETH_RMII_RXD0     4
+#define GPIOC_ETH_RMII_RXD1     5
+#define GPIOC_DCMI_D0_US6_TX    6
+#define GPIOC_I2S3_MCK          7
+#define GPIOC_DCMI_D2           8
+#define GPIOC_DCMI_D3           9
+#define GPIOC_SPI3_SCK          10
+#define GPIOC_SPI3_MISO         11
+#define GPIOC_SPI3_MOSI         12
+#define GPIOC_SWITCH_TAMPER     13
+#define GPIOC_OSC32_IN          14
+#define GPIOC_OSC32_OUT         15
+
+#define GPIOD_USELESS0          0
+#define GPIOD_USELESS1          1
+#define GPIOD_SPI3_CS           2
+#define GPIOD_LCD_RST           3
+#define GPIOD_USELESS4          4
+#define GPIOD_USELESS5          5
+#define GPIOD_LCD_CS            6
+#define GPIOD_USELESS7          7
+#define GPIOD_USART3_TX         8
+#define GPIOD_USART3_RX         9
+#define GPIOD_USELESS10         10
+#define GPIOD_USART3_CTS        11
+#define GPIOD_USART3_RTS        12
+#define GPIOD_USB_HS_FAULT      13
+#define GPIOD_USELESS14         14
+#define GPIOD_USELESS15         15
+
+#define GPIOE_0                 0
+#define GPIOE_1                 1
+#define GPIOE_TEMP_ALERT        2
+#define GPIOE_USB_HS_VBUSON     3
+#define GPIOE_4                 4
+#define GPIOE_5                 5
+#define GPIOE_6                 6
+#define GPIOE_7                 7
+#define GPIOE_8                 8
+#define GPIOE_9                 9
+#define GPIOE_10                10
+#define GPIOE_11                11
+#define GPIOE_12                12
+#define GPIOE_13                13
+#define GPIOE_14                14
+#define GPIOE_15                15
+
+#define GPIOF_0                 0
+#define GPIOF_1                 1
+#define GPIOF_2                 2
+#define GPIOF_3                 3
+#define GPIOF_4                 4
+#define GPIOF_5                 5
+#define GPIOF_STAT1             6
+#define GPIOF_STAT2             7
+#define GPIOF_STAT3             8
+#define GPIOF_CAM_PWR           9
+#define GPIOF_10                10
+#define GPIOF_CAM_RS            11
+#define GPIOF_12                12
+#define GPIOF_13                13
+#define GPIOF_14                14
+#define GPIOF_15                15
+
+#define GPIOG_0                 0
+#define GPIOG_1                 1
+#define GPIOG_2                 2
+#define GPIOG_3                 3
+#define GPIOG_4                 4
+#define GPIOG_5                 5
+#define GPIOG_RIGHT             6
+#define GPIOG_UP                7
+#define GPIOG_DOWN              8
+#define GPIOG_USART6_RX         9
+#define GPIOG_10                10
+#define GPIOG_LEFT              11
+#define GPIOG_12                12
+#define GPIOG_ETH_RMII_TXD0     13
+#define GPIOG_ETH_RMII_TXD1     14
+#define GPIOG_CENT              15
+
+#define GPIOH_OSC_IN            0
+#define GPIOH_OSC_OUT           1
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUDR_FLOATING(n)        (0U << ((n) * 2))
+#define PIN_PUDR_PULLUP(n)          (1U << ((n) * 2))
+#define PIN_PUDR_PULLDOWN(n)        (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * Port A setup.
+ *
+ * PA0  - GPIOA_BUTTON_WKUP     (input floating).
+ * PA1  - GPIOA_ETH_RMII_REF_CLK(alternate 11).
+ * PA2  - GPIOA_ETH_RMII_MDIO   (alternate 11).
+ * PA3  - GPIOA_ETH_RMII_MDINT  (input floating).
+ * PA4  - GPIOA_DCMI_HSYNC      (input pull-up).
+ * PA5  - GPIOA_LCD_SCK         (output push-pull).
+ * PA6  - GPIOA_DCMI_PIXCLK     (input pull-up).
+ * PA7  - GPIOA_ETH_RMII_CRS_DV (alternate 11).
+ * PA8  - GPIOA_MCO1            (alternate 0).
+ * PA9  - GPIOA_OTG_FS_VBUS     (input pull-up).
+ * PA10 - GPIOA_DCMI_D1         (input pull-up).
+ * PA11 - GPIOA_OTG_FS_DM       (alternate 10).
+ * PA12 - GPIOA_OTG_FS_DP       (alternate 10).
+ * PA13 - GPIOA_SWDIO           (alternate 0).
+ * PA14 - GPIOA_SWCLK           (alternate 0, pull-down).
+ * PA15 - GPIOA_I2S3_WS         (alternate 6).
+ */
+#define VAL_GPIOA_MODER     (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) |            \
+                             PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) |   \
+                             PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) |      \
+                             PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) |         \
+                             PIN_MODE_INPUT(GPIOA_DCMI_HSYNC) |             \
+                             PIN_MODE_OUTPUT(GPIOA_LCD_SCK) |               \
+                             PIN_MODE_INPUT(GPIOA_DCMI_PIXCLK) |            \
+                             PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |    \
+                             PIN_MODE_ALTERNATE(GPIOA_MCO1) |               \
+                             PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) |            \
+                             PIN_MODE_INPUT(GPIOA_DCMI_D1) |                \
+                             PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |          \
+                             PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |          \
+                             PIN_MODE_ALTERNATE(GPIOA_SWDIO) |              \
+                             PIN_MODE_ALTERNATE(GPIOA_SWCLK) |              \
+                             PIN_MODE_ALTERNATE(GPIOA_I2S3_WS))
+#define VAL_GPIOA_OTYPER    0x00000000
+#define VAL_GPIOA_OSPEEDR   0xFFFFFFFF
+#define VAL_GPIOA_PUPDR     (PIN_PUDR_PULLUP(GPIOA_DCMI_HSYNC) |            \
+                             PIN_PUDR_PULLUP(GPIOA_DCMI_PIXCLK) |           \
+                             PIN_PUDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |         \
+                             PIN_PUDR_PULLUP(GPIOA_DCMI_D1) |               \
+                             PIN_PUDR_PULLDOWN(GPIOA_SWCLK))
+#define VAL_GPIOA_ODR       0xFFFFFFDF
+#define VAL_GPIOA_AFRL      (PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) |      \
+                             PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) |         \
+                             PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
+#define VAL_GPIOA_AFRH      (PIN_AFIO_AF(GPIOA_MCO1, 0) |                   \
+                             PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) |             \
+                             PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) |             \
+                             PIN_AFIO_AF(GPIOA_SWDIO, 0) |                  \
+                             PIN_AFIO_AF(GPIOA_SWCLK, 0) |                  \
+                             PIN_AFIO_AF(GPIOA_I2S3_WS, 6))
+
+/*
+ * Port B setup.
+ *
+ * PB0  - GPIOB_LCD_BL          (output push-pull).
+ * PB1  - GPIOB_BUZ             (output push-pull).
+ * PB2  - GPIOB_CAM_ENB         (input floating).
+ * PB3  - GPIOB_I2S3_CK         (alternate 6).
+ * PB4  - GPIOB_LCD_MISO        (input floating).
+ * PB5  - GPIOB_I2S3_SD         (alternate 6).
+ * PB6  - GPIOB_DCMI_D5         (input pull-up).
+ * PB7  - GPIOB_DCMI_VSYNC      (input pull-up).
+ * PB8  - GPIOB_CAN1_RX         (alternate 9).
+ * PB9  - GPIOB_CAN1_TX         (alternate 9).
+ * PB10 - GPIOB_USB_FS_FAULT    (input floating).
+ * PB11 - GPIOB_ETH_RMII_TX_EN  (alternate 11).
+ * PB12 - GPIOB_OTG_HS_ID       (alternate 12).
+ * PB13 - GPIOB_OTG_HS_VBUS     (input pull-up).
+ * PB14 - GPIOB_OTG_HS_DM       (alternate 12).
+ * PB15 - GPIOB_OTG_HS_DP       (alternate 12).
+ */
+#define VAL_GPIOB_MODER     (PIN_MODE_OUTPUT(GPIOB_LCD_BL) |                \
+                             PIN_MODE_OUTPUT(GPIOB_BUZ) |                   \
+                             PIN_MODE_INPUT(GPIOB_CAM_ENB) |                \
+                             PIN_MODE_ALTERNATE(GPIOB_I2S3_CK) |            \
+                             PIN_MODE_INPUT(GPIOB_LCD_MISO) |               \
+                             PIN_MODE_ALTERNATE(GPIOB_I2S3_SD) |            \
+                             PIN_MODE_INPUT(GPIOB_DCMI_D5) |                \
+                             PIN_MODE_INPUT(GPIOB_DCMI_VSYNC) |             \
+                             PIN_MODE_ALTERNATE(GPIOB_CAN1_RX) |            \
+                             PIN_MODE_ALTERNATE(GPIOB_CAN1_TX) |            \
+                             PIN_MODE_INPUT(GPIOB_USB_FS_FAULT) |           \
+                             PIN_MODE_ALTERNATE(GPIOB_ETH_RMII_TX_EN) |     \
+                             PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) |          \
+                             PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) |            \
+                             PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) |          \
+                             PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OTYPER    0x00000000
+#define VAL_GPIOB_OSPEEDR   0xFFFFFFFF
+#define VAL_GPIOB_PUPDR     (PIN_PUDR_PULLUP(GPIOB_DCMI_D5) |               \
+                             PIN_PUDR_PULLUP(GPIOB_DCMI_VSYNC) |            \
+                             PIN_PUDR_PULLDOWN(GPIOB_OTG_HS_VBUS))
+#define VAL_GPIOB_ODR       0xFFFFFFFC
+#define VAL_GPIOB_AFRL      (PIN_AFIO_AF(GPIOB_I2S3_CK, 6) |                \
+                             PIN_AFIO_AF(GPIOB_I2S3_SD, 6))
+#define VAL_GPIOB_AFRH      (PIN_AFIO_AF(GPIOB_CAN1_RX, 9) |                \
+                             PIN_AFIO_AF(GPIOB_CAN1_TX, 9) |                \
+                             PIN_AFIO_AF(GPIOB_ETH_RMII_TX_EN, 11) |        \
+                             PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) |             \
+                             PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) |             \
+                             PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12))
+
+/*
+ * Port C setup.
+ *
+ * PC0  - GPIOC_TRIM            (input floating).
+ * PC1  - GPIOC_ETH_RMII_MDC    (alternate 11).
+ * PC2  - GPIOC_USB_FS_VBUSON   (output push-pull).
+ * PC3  - GPIOC_LCD_MOSI        (output push-pull).
+ * PC4  - GPIOC_ETH_RMII_RXD0   (alternate 11).
+ * PC5  - GPIOC_ETH_RMII_RXD1   (alternate 11).
+ * PC6  - GPIOC_DCMI_D0_US6_TX  (alternate 8).
+ * PC7  - GPIOC_I2S3_MCK        (alternate 6).
+ * PC8  - GPIOC_DCMI_D2         (input pull-up).
+ * PC9  - GPIOC_DCMI_D3         (input pull-up).
+ * PC10 - GPIOC_SPI3_SCK        (alternate 6).
+ * PC11 - GPIOC_SPI3_MISO       (alternate 6).
+ * PC12 - GPIOC_SPI3_MOSI       (alternate 6).
+ * PC13 - GPIOC_SWITCH_TAMPER   (input floating).
+ * PC14 - GPIOC_OSC32_IN        (input floating).
+ * PC15 - GPIOC_OSC32_OUT       (input floating).
+ */
+#define VAL_GPIOC_MODER     (PIN_MODE_INPUT(GPIOC_TRIM) |                   \
+                             PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) |       \
+                             PIN_MODE_OUTPUT(GPIOC_USB_FS_VBUSON) |         \
+                             PIN_MODE_OUTPUT(GPIOC_LCD_MOSI) |              \
+                             PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) |      \
+                             PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) |      \
+                             PIN_MODE_ALTERNATE(GPIOC_DCMI_D0_US6_TX) |     \
+                             PIN_MODE_ALTERNATE(GPIOC_I2S3_MCK) |           \
+                             PIN_MODE_INPUT(GPIOC_DCMI_D2) |                \
+                             PIN_MODE_INPUT(GPIOC_DCMI_D3) |                \
+                             PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) |           \
+                             PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) |          \
+                             PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) |          \
+                             PIN_MODE_INPUT(GPIOC_SWITCH_TAMPER) |          \
+                             PIN_MODE_INPUT(GPIOC_OSC32_IN) |               \
+                             PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER    0x00000000
+#define VAL_GPIOC_OSPEEDR   0xFFFFFFFF
+#define VAL_GPIOC_PUPDR     (PIN_PUDR_PULLUP(GPIOC_DCMI_D2) |               \
+                             PIN_PUDR_PULLUP(GPIOC_DCMI_D3))
+#define VAL_GPIOC_ODR       0xFFFFFFF3
+#define VAL_GPIOC_AFRL      (PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) |          \
+                             PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) |         \
+                             PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) |         \
+                             PIN_AFIO_AF(GPIOC_DCMI_D0_US6_TX, 8) |         \
+                             PIN_AFIO_AF(GPIOC_I2S3_MCK, 6))
+#define VAL_GPIOC_AFRH      (PIN_AFIO_AF(GPIOC_SPI3_SCK, 6) |               \
+                             PIN_AFIO_AF(GPIOC_SPI3_MISO, 6) |              \
+                             PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6))
+
+/*
+ * Port D setup.
+ *
+ * PD0  - GPIOD_USELESS0        (input pull-up).
+ * PD1  - GPIOD_USELESS1        (input pull-up).
+ * PD2  - GPIOD_SPI3_CS         (output opendrain).
+ * PD3  - GPIOD_LCD_RST         (output push-pull).
+ * PD4  - GPIOD_USELESS4        (input pull-up).
+ * PD5  - GPIOD_USELESS5        (input pull-up).
+ * PD6  - GPIOD_LCD_CS          (output push-pull).
+ * PD7  - GPIOD_USELESS7        (input pull-up).
+ * PD8  - GPIOD_USART3_TX       (alternate 8).
+ * PD9  - GPIOD_USART3_RX       (alternate 8).
+ * PD10 - GPIOD_USELESS10       (input pull-up).
+ * PD11 - GPIOD_USART3_CTS      (alternate 8).
+ * PD12 - GPIOD_USART3_RTS      (alternate 8).
+ * PD13 - GPIOD_USB_HS_FAULT    (input floating).
+ * PD14 - GPIOD_USELESS14       (input pull-up).
+ * PD15 - GPIOD_USELESS15       (input pull-up).
+ */
+#define VAL_GPIOD_MODER     (PIN_MODE_INPUT(GPIOD_USELESS0) |               \
+                             PIN_MODE_INPUT(GPIOD_USELESS1) |               \
+                             PIN_MODE_OUTPUT(GPIOD_SPI3_CS) |               \
+                             PIN_MODE_OUTPUT(GPIOD_LCD_RST) |               \
+                             PIN_MODE_INPUT(GPIOD_USELESS4) |               \
+                             PIN_MODE_INPUT(GPIOD_USELESS5) |               \
+                             PIN_MODE_OUTPUT(GPIOD_LCD_CS) |                \
+                             PIN_MODE_INPUT(GPIOD_USELESS7) |               \
+                             PIN_MODE_ALTERNATE(GPIOD_USART3_TX) |          \
+                             PIN_MODE_ALTERNATE(GPIOD_USART3_RX) |          \
+                             PIN_MODE_INPUT(GPIOD_USELESS10) |              \
+                             PIN_MODE_ALTERNATE(GPIOD_USART3_CTS) |         \
+                             PIN_MODE_ALTERNATE(GPIOD_USART3_RTS) |         \
+                             PIN_MODE_INPUT(GPIOD_USB_HS_FAULT) |           \
+                             PIN_MODE_INPUT(GPIOD_USELESS14) |              \
+                             PIN_MODE_INPUT(GPIOD_USELESS15))
+#define VAL_GPIOD_OTYPER    PIN_OTYPE_OPENDRAIN(GPIOD_SPI3_CS)
+#define VAL_GPIOD_OSPEEDR   0xFFFFFFFF
+#define VAL_GPIOD_PUPDR     (PIN_PUDR_PULLUP(GPIOD_USELESS0) |              \
+                             PIN_PUDR_PULLUP(GPIOD_USELESS1) |              \
+                             PIN_PUDR_PULLUP(GPIOD_USELESS4) |              \
+                             PIN_PUDR_PULLUP(GPIOD_USELESS5) |              \
+                             PIN_PUDR_PULLUP(GPIOD_USELESS7) |              \
+                             PIN_PUDR_PULLUP(GPIOD_USELESS10) |             \
+                             PIN_PUDR_PULLUP(GPIOD_USELESS14) |             \
+                             PIN_PUDR_PULLUP(GPIOD_USELESS15))
+#define VAL_GPIOD_ODR       0xFFFFFFFF
+#define VAL_GPIOD_AFRL      0x00000000
+#define VAL_GPIOD_AFRH      (PIN_AFIO_AF(GPIOD_USART3_TX, 7) |              \
+                             PIN_AFIO_AF(GPIOD_USART3_RX, 7) |              \
+                             PIN_AFIO_AF(GPIOD_USART3_CTS, 7) |             \
+                             PIN_AFIO_AF(GPIOD_USART3_RTS, 7))
+
+/*
+ * Port E setup.
+ *
+ * PE0  - GPIOE_0               (input pull-up).
+ * PE1  - GPIOE_1               (input pull-up).
+ * PE2  - GPIOE_TEMP_ALERT      (input floating).
+ * PE3  - GPIOE_USB_HS_VBUSON   (output push-pull).
+ * PE4  - GPIOE_4               (input pull-up).
+ * PE5  - GPIOE_5               (input pull-up).
+ * PE6  - GPIOE_6               (input pull-up).
+ * PE7  - GPIOE_7               (input pull-up).
+ * PE8  - GPIOE_8               (input pull-up).
+ * PE9  - GPIOE_9               (input pull-up).
+ * PE10 - GPIOE_10              (input pull-up).
+ * PE11 - GPIOE_11              (input pull-up).
+ * PE12 - GPIOE_12              (input pull-up).
+ * PE13 - GPIOE_13              (input pull-up).
+ * PE14 - GPIOE_14              (input pull-up).
+ * PE15 - GPIOE_15              (input pull-up).
+ */
+#define VAL_GPIOE_MODER     (PIN_MODE_INPUT(GPIOE_0) |                      \
+                             PIN_MODE_INPUT(GPIOE_1) |                      \
+                             PIN_MODE_INPUT(GPIOE_TEMP_ALERT) |             \
+                             PIN_MODE_OUTPUT(GPIOE_USB_HS_VBUSON) |         \
+                             PIN_MODE_INPUT(GPIOE_4) |                      \
+                             PIN_MODE_INPUT(GPIOE_5) |                      \
+                             PIN_MODE_INPUT(GPIOE_6) |                      \
+                             PIN_MODE_INPUT(GPIOE_7) |                      \
+                             PIN_MODE_INPUT(GPIOE_8) |                      \
+                             PIN_MODE_INPUT(GPIOE_9) |                      \
+                             PIN_MODE_INPUT(GPIOE_10) |                     \
+                             PIN_MODE_INPUT(GPIOE_11) |                     \
+                             PIN_MODE_INPUT(GPIOE_12) |                     \
+                             PIN_MODE_INPUT(GPIOE_13) |                     \
+                             PIN_MODE_INPUT(GPIOE_14) |                     \
+                             PIN_MODE_INPUT(GPIOE_15))
+#define VAL_GPIOE_OTYPER    0x00000000
+#define VAL_GPIOE_OSPEEDR   0xFFFFFFFF
+#define VAL_GPIOE_PUPDR     (PIN_PUDR_PULLUP(GPIOE_0) |                     \
+                             PIN_PUDR_PULLUP(GPIOE_1) |                     \
+                             PIN_PUDR_PULLUP(GPIOE_4) |                     \
+                             PIN_PUDR_PULLUP(GPIOE_5) |                     \
+                             PIN_PUDR_PULLUP(GPIOE_6) |                     \
+                             PIN_PUDR_PULLUP(GPIOE_7) |                     \
+                             PIN_PUDR_PULLUP(GPIOE_8) |                     \
+                             PIN_PUDR_PULLUP(GPIOE_9) |                     \
+                             PIN_PUDR_PULLUP(GPIOE_10) |                    \
+                             PIN_PUDR_PULLUP(GPIOE_11) |                    \
+                             PIN_PUDR_PULLUP(GPIOE_12) |                    \
+                             PIN_PUDR_PULLUP(GPIOE_13) |                    \
+                             PIN_PUDR_PULLUP(GPIOE_14) |                    \
+                             PIN_PUDR_PULLUP(GPIOE_15))
+#define VAL_GPIOE_ODR       0xFFFFFFF7
+#define VAL_GPIOE_AFRL      0x00000000
+#define VAL_GPIOE_AFRH      0x00000000
+
+/*
+ * Port F setup.
+ *
+ * PF0  - GPIOF_0               (input pull-up).
+ * PF1  - GPIOF_1               (input pull-up).
+ * PF2  - GPIOF_2               (input pull-up).
+ * PF3  - GPIOF_3               (input pull-up).
+ * PF4  - GPIOF_4               (input pull-up).
+ * PF5  - GPIOF_5               (input pull-up).
+ * PF6  - GPIOF_STAT1           (output push-pull).
+ * PF7  - GPIOF_STAT2           (output push-pull).
+ * PF8  - GPIOF_STAT3           (output push-pull).
+ * PF9  - GPIOF_CAM_PWR         (output push-pull).
+ * PF10 - GPIOF_10              (input pull-up).
+ * PF11 - GPIOF_CAM_RS          (output push-pull).
+ * PF12 - GPIOF_12              (input pull-up).
+ * PF13 - GPIOF_13              (input pull-up).
+ * PF14 - GPIOF_14              (input pull-up).
+ * PF15 - GPIOF_15              (input pull-up).
+ */
+#define VAL_GPIOF_MODER     (PIN_MODE_INPUT(GPIOF_0) |                      \
+                             PIN_MODE_INPUT(GPIOF_1) |                      \
+                             PIN_MODE_INPUT(GPIOF_2) |                      \
+                             PIN_MODE_INPUT(GPIOF_3) |                      \
+                             PIN_MODE_INPUT(GPIOF_4) |                      \
+                             PIN_MODE_INPUT(GPIOF_5) |                      \
+                             PIN_MODE_OUTPUT(GPIOF_STAT1) |                 \
+                             PIN_MODE_OUTPUT(GPIOF_STAT2) |                 \
+                             PIN_MODE_OUTPUT(GPIOF_STAT3) |                 \
+                             PIN_MODE_OUTPUT(GPIOF_CAM_PWR) |               \
+                             PIN_MODE_INPUT(GPIOF_10) |                     \
+                             PIN_MODE_OUTPUT(GPIOF_CAM_RS) |                \
+                             PIN_MODE_INPUT(GPIOF_12) |                     \
+                             PIN_MODE_INPUT(GPIOF_13) |                     \
+                             PIN_MODE_INPUT(GPIOF_14) |                     \
+                             PIN_MODE_INPUT(GPIOF_15))
+#define VAL_GPIOF_OTYPER    0x00000000
+#define VAL_GPIOF_OSPEEDR   0xFFFFFFFF
+#define VAL_GPIOF_PUPDR     (PIN_PUDR_PULLUP(GPIOF_0) |                     \
+                             PIN_PUDR_PULLUP(GPIOF_1) |                     \
+                             PIN_PUDR_PULLUP(GPIOF_2) |                     \
+                             PIN_PUDR_PULLUP(GPIOF_3) |                     \
+                             PIN_PUDR_PULLUP(GPIOF_4) |                     \
+                             PIN_PUDR_PULLUP(GPIOF_5) |                     \
+                             PIN_PUDR_PULLUP(GPIOF_10) |                    \
+                             PIN_PUDR_PULLUP(GPIOF_12) |                    \
+                             PIN_PUDR_PULLUP(GPIOF_13) |                    \
+                             PIN_PUDR_PULLUP(GPIOF_14) |                    \
+                             PIN_PUDR_PULLUP(GPIOF_15))
+#define VAL_GPIOF_ODR       0xFFFFFC3F
+#define VAL_GPIOF_AFRL      0x00000000
+#define VAL_GPIOF_AFRH      0x00000000
+
+/*
+ * Port G setup.
+ *
+ * PG0  - GPIOG_0               (input pull-up).
+ * PG1  - GPIOG_1               (input pull-up).
+ * PG2  - GPIOG_2               (input pull-up).
+ * PG3  - GPIOG_3               (input pull-up).
+ * PG4  - GPIOG_4               (input pull-up).
+ * PG5  - GPIOG_5               (input pull-up).
+ * PG6  - GPIOG_RIGHT           (input floating).
+ * PG7  - GPIOG_UP              (input floating).
+ * PG8  - GPIOG_DOWN            (input floating).
+ * PG9  - GPIOG_USART6_RX       (alternate 8).
+ * PG10 - GPIOG_10              (input pull-up).
+ * PG11 - GPIOG_LEFT            (input floating).
+ * PG12 - GPIOG_12              (input pull-up).
+ * PG13 - GPIOG_ETH_RMII_TXD0   (alternate 11).
+ * PG14 - GPIOG_ETH_RMII_TXD1   (alternate 11).
+ * PG15 - GPIOG_CENT            (input pull-up).
+ */
+#define VAL_GPIOG_MODER     (PIN_MODE_INPUT(GPIOG_0) |                      \
+                             PIN_MODE_INPUT(GPIOG_1) |                      \
+                             PIN_MODE_INPUT(GPIOG_2) |                      \
+                             PIN_MODE_INPUT(GPIOG_3) |                      \
+                             PIN_MODE_INPUT(GPIOG_4) |                      \
+                             PIN_MODE_INPUT(GPIOG_5) |                      \
+                             PIN_MODE_INPUT(GPIOG_RIGHT) |                  \
+                             PIN_MODE_INPUT(GPIOG_UP) |                     \
+                             PIN_MODE_INPUT(GPIOG_DOWN) |                   \
+                             PIN_MODE_ALTERNATE(GPIOG_USART6_RX) |          \
+                             PIN_MODE_INPUT(GPIOG_10) |                     \
+                             PIN_MODE_INPUT(GPIOG_LEFT) |                   \
+                             PIN_MODE_INPUT(GPIOG_12) |                     \
+                             PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) |      \
+                             PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) |      \
+                             PIN_MODE_INPUT(GPIOG_CENT))
+#define VAL_GPIOG_OTYPER    0x00000000
+#define VAL_GPIOG_OSPEEDR   0xFFFFFFFF
+#define VAL_GPIOG_PUPDR     (PIN_PUDR_PULLUP(GPIOG_0) |                     \
+                             PIN_PUDR_PULLUP(GPIOG_1) |                     \
+                             PIN_PUDR_PULLUP(GPIOG_2) |                     \
+                             PIN_PUDR_PULLUP(GPIOG_3) |                     \
+                             PIN_PUDR_PULLUP(GPIOG_4) |                     \
+                             PIN_PUDR_PULLUP(GPIOG_5) |                     \
+                             PIN_PUDR_PULLUP(GPIOG_10) |                    \
+                             PIN_PUDR_PULLUP(GPIOG_12))
+#define VAL_GPIOG_ODR       0xFFFFFFFF
+#define VAL_GPIOG_AFRL      0x00000000
+#define VAL_GPIOG_AFRH      (PIN_AFIO_AF(GPIOG_USART6_RX, 8) |              \
+                             PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) |         \
+                             PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11))
+
+/*
+ * Port H setup.
+ * All input with pull-up except:
+ * PH0  - GPIOH_OSC_IN          (input floating).
+ * PH1  - GPIOH_OSC_OUT         (input floating).
+ */
+#define VAL_GPIOH_MODER     (PIN_MODE_INPUT(GPIOH_OSC_IN) |                 \
+                             PIN_MODE_INPUT(GPIOH_OSC_OUT) |                \
+                             PIN_MODE_INPUT(2) |                            \
+                             PIN_MODE_INPUT(3) |                            \
+                             PIN_MODE_INPUT(4) |                            \
+                             PIN_MODE_INPUT(5) |                            \
+                             PIN_MODE_INPUT(6) |                            \
+                             PIN_MODE_INPUT(7) |                            \
+                             PIN_MODE_INPUT(8) |                            \
+                             PIN_MODE_INPUT(9) |                            \
+                             PIN_MODE_INPUT(10) |                           \
+                             PIN_MODE_INPUT(11) |                           \
+                             PIN_MODE_INPUT(12) |                           \
+                             PIN_MODE_INPUT(13) |                           \
+                             PIN_MODE_INPUT(14) |                           \
+                             PIN_MODE_INPUT(15))
+#define VAL_GPIOH_OTYPER    0x00000000
+#define VAL_GPIOH_OSPEEDR   0xFFFFFFFF
+#define VAL_GPIOH_PUPDR     (PIN_PUDR_FLOATING(GPIOH_OSC_IN) |              \
+                             PIN_PUDR_FLOATING(GPIOH_OSC_OUT) |             \
+                             PIN_PUDR_PULLUP(2) |                           \
+                             PIN_PUDR_PULLUP(3) |                           \
+                             PIN_PUDR_PULLUP(4) |                           \
+                             PIN_PUDR_PULLUP(5) |                           \
+                             PIN_PUDR_PULLUP(6) |                           \
+                             PIN_PUDR_PULLUP(7) |                           \
+                             PIN_PUDR_PULLUP(8) |                           \
+                             PIN_PUDR_PULLUP(9) |                           \
+                             PIN_PUDR_PULLUP(10) |                          \
+                             PIN_PUDR_PULLUP(11) |                          \
+                             PIN_PUDR_PULLUP(12) |                          \
+                             PIN_PUDR_PULLUP(13) |                          \
+                             PIN_PUDR_PULLUP(14) |                          \
+                             PIN_PUDR_PULLUP(15))
+#define VAL_GPIOH_ODR       0xFFFFFFFF
+#define VAL_GPIOH_AFRL      0x00000000
+#define VAL_GPIOH_AFRH      0x00000000
+
+/*
+ * Port I setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOI_MODER     0x00000000
+#define VAL_GPIOI_OTYPER    0x00000000
+#define VAL_GPIOI_OSPEEDR   0xFFFFFFFF
+#define VAL_GPIOI_PUPDR     (PIN_PUDR_PULLUP(0) |                           \
+                             PIN_PUDR_PULLUP(1) |                           \
+                             PIN_PUDR_PULLUP(2) |                           \
+                             PIN_PUDR_PULLUP(3) |                           \
+                             PIN_PUDR_PULLUP(4) |                           \
+                             PIN_PUDR_PULLUP(5) |                           \
+                             PIN_PUDR_PULLUP(6) |                           \
+                             PIN_PUDR_PULLUP(7) |                           \
+                             PIN_PUDR_PULLUP(8) |                           \
+                             PIN_PUDR_PULLUP(9) |                           \
+                             PIN_PUDR_PULLUP(10) |                          \
+                             PIN_PUDR_PULLUP(11) |                          \
+                             PIN_PUDR_PULLUP(12) |                          \
+                             PIN_PUDR_PULLUP(13) |                          \
+                             PIN_PUDR_PULLUP(14) |                          \
+                             PIN_PUDR_PULLUP(15))
+#define VAL_GPIOI_ODR       0xFFFFFFFF
+#define VAL_GPIOI_AFRL      0x00000000
+#define VAL_GPIOI_AFRH      0x00000000
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_P407/board.mk b/os/hal/boards/OLIMEX_STM32_P407/board.mk
new file mode 100644
index 000000000..9affc175f
--- /dev/null
+++ b/os/hal/boards/OLIMEX_STM32_P407/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_P407/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_P407
diff --git a/os/hal/boards/RAISONANCE_REVA_STM8S/board.c b/os/hal/boards/RAISONANCE_REVA_STM8S/board.c
new file mode 100644
index 000000000..ee9c9d32f
--- /dev/null
+++ b/os/hal/boards/RAISONANCE_REVA_STM8S/board.c
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+ROMCONST PALConfig pal_default_config =
+{
+  {
+    {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2},
+    {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
+    {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
+    {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
+    {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
+    {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
+    {VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
+  }
+};
+#endif
+
+/*
+ * TIM 2 clock after the prescaler.
+ */
+#define TIM2_CLOCK  (SYSCLK / 16)
+#define TIM2_ARR    ((TIM2_CLOCK / CH_FREQUENCY) - 1)
+
+/*
+ * TIM2 interrupt handler.
+ */
+CH_IRQ_HANDLER(13) {
+
+  CH_IRQ_PROLOGUE();
+
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+
+  TIM2->SR1 = 0;
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * TIM2 initialization as system tick.
+   */
+  CLK->PCKENR1 |= CLK_PCKENR1_TIM2;
+  TIM2->PSCR    = 4;            /* Prescaler divide by 2^4=16.*/
+  TIM2->ARRH    = (uint8_t)(TIM2_ARR >> 8);
+  TIM2->ARRL    = (uint8_t)(TIM2_ARR);
+  TIM2->CNTRH   = 0;
+  TIM2->CNTRL   = 0;
+  TIM2->SR1     = 0;
+  TIM2->IER     = TIM2_IER_UIE;
+  TIM2->CR1     = TIM2_CR1_CEN;
+}
diff --git a/os/hal/boards/RAISONANCE_REVA_STM8S/board.h b/os/hal/boards/RAISONANCE_REVA_STM8S/board.h
new file mode 100644
index 000000000..d61e50513
--- /dev/null
+++ b/os/hal/boards/RAISONANCE_REVA_STM8S/board.h
@@ -0,0 +1,184 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Raisonance REva V3 + STM8S208RB daughter board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_REVA_V3_STM8S208RB
+#define BOARD_NAME      "Raisonance REva V3 + STM8S208RB"
+
+/*
+ * Board frequencies.
+ */
+#define HSECLK          0
+
+/*
+ * MCU model used on the board.
+ */
+#define STM8S208
+
+/*
+ * Pin definitions.
+ */
+#define PA_OSCIN        1
+#define PA_J2_25        2               /* It is also OSCOUT.               */
+#define PA_J2_27        3
+#define PA_RX           4
+#define PA_TX           5
+
+#define PB_LED(n)       (n)
+#define PB_LCD_D0       0
+#define PB_LCD_D1       1
+#define PB_LCD_CSB      2
+#define PB_LCD_RESB     3
+
+#define PC_ADC_ETR      0
+#define PC_J2_51        1
+#define PC_J2_53        2
+#define PC_J2_55        3
+#define PC_J2_57        4
+#define PC_SCK          5
+#define PC_MOSI         6
+#define PC_MISO         7
+
+#define PD_J2_69        0
+#define PD_J2_21        1
+#define PD_J2_67        2
+#define PD_J2_65        3
+#define PD_PWM          4
+#define PD_J2_63        5
+#define PD_J2_61        6
+#define PD_J2_59        7
+
+#define PE_P2_49        0
+#define PE_SCL          1
+#define PE_SDA          2
+#define PE_P2_47        3
+#define PE_P2_45        4
+#define PE_P2_43        5
+#define PE_P2_41        6
+#define PE_P2_39        7
+
+#define PF_J2_37        0
+#define PF_J2_35        1
+#define PF_J2_33        2
+#define PF_J2_31        3
+#define PF_ANA_IN1      4
+#define PF_ANA_IN2      5
+#define PF_ANA_TEMP     6
+#define PF_ANA_POT      7
+
+#define PG_CAN_TX       0
+#define PG_CAN_RX       1
+#define PG_BT5          2
+#define PG_BT6          3
+#define PG_SW4          4
+#define PG_SW3          5
+#define PG_SW2          6
+#define PG_SW1          7
+
+#define PI_J2_71        0
+
+/*
+ * Port A initial setup.
+ */
+#define VAL_GPIOAODR    (1 << PA_TX)    /* PA_TX initially to 1.            */
+#define VAL_GPIOADDR    (1 << PA_TX)    /* PA_TX output, others inputs.     */
+#define VAL_GPIOACR1    0xFF            /* All pull-up or push-pull.        */
+#define VAL_GPIOACR2    0
+
+/*
+ * Port B initial setup.
+ */
+#define VAL_GPIOBODR    0xFF            /* Initially all set to high.       */
+#define VAL_GPIOBDDR    0xFF            /* All outputs.                     */
+#define VAL_GPIOBCR1    0xFF            /* All push-pull.                   */
+#define VAL_GPIOBCR2    0
+
+/*
+ * Port C initial setup.
+ */
+#define VAL_GPIOCODR    0
+#define VAL_GPIOCDDR    0               /* All inputs.                      */
+#define VAL_GPIOCCR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIOCCR2    0
+
+/*
+ * Port D initial setup.
+ */
+#define VAL_GPIODODR    0
+#define VAL_GPIODDDR    0               /* All inputs.                      */
+#define VAL_GPIODCR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIODCR2    0
+
+/*
+ * Port E initial setup.
+ */
+#define VAL_GPIOEODR    0 
+#define VAL_GPIOEDDR    0               /* All inputs.                      */
+#define VAL_GPIOECR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIOECR2    0
+
+/*
+ * Port F initial setup.
+ */
+#define VAL_GPIOFODR    0
+#define VAL_GPIOFDDR    0               /* All inputs.                      */
+#define VAL_GPIOFCR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIOFCR2    0
+
+/*
+ * Port G initial setup.
+ */
+#define VAL_GPIOGODR    (1 << PG_CAN_TX)/* CAN_TX initially to 1.           */
+#define VAL_GPIOGDDR    (1 << PG_CAN_TX)/* CAN_TX output, others inputs.    */
+#define VAL_GPIOGCR1    0xFF            /* All pull-up or push-pull.        */
+#define VAL_GPIOGCR2    0
+
+/*
+ * Port H initial setup (dummy, not present).
+ */
+#define VAL_GPIOHODR    0
+#define VAL_GPIOHDDR    0               /* All inputs.                      */
+#define VAL_GPIOHCR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIOHCR2    0
+
+/*
+ * Port I initial setup.
+ */
+#define VAL_GPIOIODR    0
+#define VAL_GPIOIDDR    0               /* All inputs.                      */
+#define VAL_GPIOICR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIOICR2    0
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.c b/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.c
new file mode 100644
index 000000000..35aaad9ee
--- /dev/null
+++ b/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.c
@@ -0,0 +1,108 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR},
+#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
+    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
+  {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR}
+#endif
+};
+#endif
+
+/*
+ * SYS IRQ handling here.
+ */
+static CH_IRQ_HANDLER(SYSIrqHandler) {
+
+  CH_IRQ_PROLOGUE();
+
+  if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) {
+    (void) AT91C_BASE_PITC->PITC_PIVR;
+    chSysLockFromIsr();
+    chSysTimerHandlerI();
+    chSysUnlockFromIsr();
+  }
+  
+#if USE_SAM7_DBGU_UART
+  if (AT91C_BASE_DBGU->DBGU_CSR & 
+    (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE | AT91C_US_RXBRK)) {
+    sd_lld_serve_interrupt(&SDDBG);
+  }
+#endif  
+  AT91C_BASE_AIC->AIC_EOICR = 0;
+  CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  
+  /* Watchdog disabled.*/
+  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+  
+  at91sam7_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return !palReadPad(IOPORT2, PIOB_MMC_CP);
+}
+
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return palReadPad(IOPORT2, PIOB_MMC_WP);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * PIT Initialization.
+   */
+  AIC_ConfigureIT(AT91C_ID_SYS,
+                  AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1),
+                  SYSIrqHandler);
+  AIC_EnableIT(AT91C_ID_SYS);
+  AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1;
+  AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
+
+  /*
+   * RTS/CTS pins enabled for USART0 only.
+   */
+  AT91C_BASE_PIOA->PIO_PDR   = AT91C_PA3_RTS0 | AT91C_PA4_CTS0;
+  AT91C_BASE_PIOA->PIO_ASR   = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+  AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+}
diff --git a/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.h b/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.h
new file mode 100644
index 000000000..1bb61e40c
--- /dev/null
+++ b/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.h
@@ -0,0 +1,93 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Studiel AT91SAM7A3-EK board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_STUDIEL_AT91SAM7A3_EK
+#define BOARD_NAME "Studiel AT91SAM7A3-EK eval. board"
+
+/*
+ * Select your platform by modifying the following line.
+ */
+#if !defined(SAM7A3_PLATFORM)
+#define SAM7_PLATFORM   SAM7A3
+#endif
+
+#include "at91sam7.h"
+
+#define CLK             18432000
+#define MCK             48054857
+
+/*
+ * I/O definitions.
+ */
+#define PIOA_RXD0               2
+#define PIOA_RXD0_MASK          (1 << PIOA_RXD0)
+#define PIOA_TXD0               3
+#define PIOA_TXD0_MASK          (1 << PIOA_TXD0)
+#define PIOA_LED1               20
+#define PIOA_LED1_MASK          (1 << PIOA_LED1)
+#define PIOA_LED2               21
+#define PIOA_LED2_MASK          (1 << PIOA_LED2)
+#define PIOA_LED3               24
+#define PIOA_LED3_MASK          (1 << PIOA_LED3)
+#define PIOA_LED4               25
+#define PIOA_LED4_MASK          (1 << PIOA_LED4)
+// mmc-spi
+#define PIOA_SPI0_NSS           14
+#define PIOA_SPI0_NSS_MASK      (1 << PIOA_SPI0_NSS)
+#define PIOA_SPI0_MISO          15
+#define PIOA_SPI0_MISO_MASK     (1 << PIOA_SPI0_MISO)
+#define PIOA_SPI0_MOSI          16
+#define PIOA_SPI0_MOSI_MASK     (1 << PIOA_SPI0_MOSI)
+#define PIOA_SPI0_CLK           17
+#define PIOA_SPI0_CLK_MASK      (1 << PIOA_SPI0_CLK)
+
+/*
+ * Initial I/O setup.
+ */
+/* Output data. */
+#define VAL_PIOA_ODSR           0x00000000
+/* Direction. */
+#define VAL_PIOA_OSR            0x00000000 | PIOA_LED1_MASK | PIOA_LED2_MASK | \
+                                             PIOA_LED3_MASK | PIOA_LED4_MASK
+/* Pull-up. */
+#define VAL_PIOA_PUSR           0xFFFFFFFF
+
+#define VAL_PIOB_ODSR           0x00000000      /* Output data. */
+#define VAL_PIOB_OSR            0x00000000      /* Direction. */
+#define VAL_PIOB_PUSR           0xFFFFFFFF      /* Pull-up. */
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC560BC/board.c b/os/hal/boards/ST_EVB_SPC560BC/board.c
new file mode 100644
index 000000000..4ecf10fd9
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC560BC/board.c
@@ -0,0 +1,66 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+  {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON1),  PAL_LOW,  PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON2),  PAL_LOW,  PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON3),  PAL_LOW,  PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON4),  PAL_LOW,  PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_LED1),     PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_E, PE_LED2),     PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_E, PE_LED3),     PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_E, PE_LED4),     PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+  {-1, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/**
+ * @brief   PAL setup.
+ */
+const PALConfig pal_default_config = {
+  PAL_MODE_UNCONNECTED,             /* Default mode for all undefined pads. */
+  spc_siu_init,
+  spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_EVB_SPC560BC/board.h b/os/hal/boards/ST_EVB_SPC560BC/board.h
new file mode 100644
index 000000000..70e3ee548
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC560BC/board.h
@@ -0,0 +1,68 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC560B/Cxx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_GENERIC_SPC560BC
+#define BOARD_NAME                  "Generic SPC560B/Cxx"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK               8000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX     2
+#define PB_LIN0_RDX     3
+
+#define PE_BUTTON1      0
+#define PE_BUTTON2      1
+#define PE_BUTTON3      2
+#define PE_BUTTON4      3
+
+#define PE_LED1         4
+#define PE_LED2         5
+#define PE_LED3         6
+#define PE_LED4         7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin)  (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC560BC/board.mk b/os/hal/boards/ST_EVB_SPC560BC/board.mk
new file mode 100644
index 000000000..02428bd6d
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC560BC/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC560BC/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC560BC
diff --git a/os/hal/boards/ST_EVB_SPC560D/board.c b/os/hal/boards/ST_EVB_SPC560D/board.c
new file mode 100644
index 000000000..f59eed54f
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC560D/board.c
@@ -0,0 +1,71 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+  {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH,   PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH,   PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON1), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON2), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON3), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON4), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_LED1),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_E, PE_LED2),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_E, PE_LED3),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_E, PE_LED4),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {-1, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+  0,   0,   0,   0,   0,   0,   0,   0,
+  0,   0,   0,   0,   0,   0,   0,   0,
+  0,   0,   0,   0,   0,   0,   0,   0,
+  0,   0,   0,   0,   0,   0,   0,   0,
+  0,   0,   0,   0,   0,   0,   0,   0,
+  0,   0,   0,   0,   0,   0,   0,   0,
+  0,   0,   0,   0,   0,   0,   0,   0,
+  0,   0,   0,   0,   0,   0,   0,
+};
+
+/**
+ * @brief   PAL setup.
+ */
+const PALConfig pal_default_config = {
+  PAL_MODE_UNCONNECTED,
+  spc_siu_init,
+  spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_EVB_SPC560D/board.h b/os/hal/boards/ST_EVB_SPC560D/board.h
new file mode 100644
index 000000000..eab91cba8
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC560D/board.h
@@ -0,0 +1,66 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC560Dxx board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_SPC560DXX_EVB
+#define BOARD_NAME                  "EVB with SPC560Dxx Mini Module"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK               8000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX                 2
+#define PB_LIN0_RDX                 3
+#define PE_BUTTON1                  0
+#define PE_BUTTON2                  1
+#define PE_BUTTON3                  2
+#define PE_BUTTON4                  3
+#define PE_LED1                     4
+#define PE_LED2                     5
+#define PE_LED3                     6
+#define PE_LED4                     7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin)  (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC560D/board.mk b/os/hal/boards/ST_EVB_SPC560D/board.mk
new file mode 100644
index 000000000..b2c8e2e91
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC560D/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC560D/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC560D
diff --git a/os/hal/boards/ST_EVB_SPC560P/board.c b/os/hal/boards/ST_EVB_SPC560P/board.c
new file mode 100644
index 000000000..5ad702a70
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC560P/board.c
@@ -0,0 +1,68 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+  {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH,   PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH,   PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON1), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON2), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON3), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON4), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_LED1),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_D, PD_LED2),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_D, PD_LED3),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_D, PD_LED4),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {-1, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   
+};
+
+/**
+ * @brief   PAL setup.
+ */
+const PALConfig pal_default_config = {
+  PAL_MODE_UNCONNECTED,
+  spc_siu_init,
+  spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_EVB_SPC560P/board.h b/os/hal/boards/ST_EVB_SPC560P/board.h
new file mode 100644
index 000000000..9688036d5
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC560P/board.h
@@ -0,0 +1,71 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC560Pxx board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_SPC560PXX_EVB
+#define BOARD_NAME                  "EVB with SPC560Pxx Mini Module"
+
+/*
+ * Device identifier.
+ */
+#define _SPC560P50L5_
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK               40000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX                 2
+#define PB_LIN0_RDX                 3
+#define PD_BUTTON1                  0
+#define PD_BUTTON2                  1
+#define PD_BUTTON3                  2
+#define PD_BUTTON4                  3
+#define PD_LED1                     4
+#define PD_LED2                     5
+#define PD_LED3                     6
+#define PD_LED4                     7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin)  (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC560P/board.mk b/os/hal/boards/ST_EVB_SPC560P/board.mk
new file mode 100644
index 000000000..83d7919d1
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC560P/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC560P/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC560P
diff --git a/os/hal/boards/ST_EVB_SPC563M/board.c b/os/hal/boards/ST_EVB_SPC563M/board.c
new file mode 100644
index 000000000..09a34154b
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC563M/board.c
@@ -0,0 +1,57 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+  {PCR(PORT5, P5_ESCI_A_TX),      PAL_HIGH,   PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT5, P5_ESCI_A_RX),      PAL_HIGH,   PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT11, P11_BUTTON1),      PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT11, P11_BUTTON2),      PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT11, P11_BUTTON3),      PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT11, P11_BUTTON4),      PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT11, P11_LED1),         PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT11, P11_LED2),         PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT11, P11_LED3),         PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT11, P11_LED4),         PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {-1, 0, 0}
+};
+
+/**
+ * @brief   PAL setup.
+ */
+const PALConfig pal_default_config = {
+  spc_siu_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_EVB_SPC563M/board.h b/os/hal/boards/ST_EVB_SPC563M/board.h
new file mode 100644
index 000000000..3074f9a7e
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC563M/board.h
@@ -0,0 +1,66 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC563Mxx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_SPC563MXX_EVB
+#define BOARD_NAME                  "EVB with SPC563Mxx Mini Module"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK               8000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define P5_ESCI_A_TX                9
+#define P5_ESCI_A_RX                10
+#define P11_BUTTON1                 3
+#define P11_BUTTON2                 5
+#define P11_BUTTON3                 7
+#define P11_BUTTON4                 9
+#define P11_LED1                    12
+#define P11_LED2                    13
+#define P11_LED3                    14
+#define P11_LED4                    15
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin)  (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC563M/board.mk b/os/hal/boards/ST_EVB_SPC563M/board.mk
new file mode 100644
index 000000000..cb7a0220a
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC563M/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC563M/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC563M
diff --git a/os/hal/boards/ST_EVB_SPC564A/board.c b/os/hal/boards/ST_EVB_SPC564A/board.c
new file mode 100644
index 000000000..419be6c89
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC564A/board.c
@@ -0,0 +1,58 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+  {PCR(PORT5, P5_ESCI_A_TX),      PAL_HIGH,   PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT5, P5_ESCI_A_RX),      PAL_HIGH,   PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT11, P11_BUTTON1),      PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT11, P11_BUTTON2),      PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT11, P11_BUTTON3),      PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT11, P11_BUTTON4),      PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT11, P11_LED1),         PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT11, P11_LED2),         PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT11, P11_LED3),         PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT11, P11_LED4),         PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {-1, 0, 0}
+};
+
+/**
+ * @brief   PAL setup.
+ */
+const PALConfig pal_default_config = {
+  spc_siu_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  spc_clock_init();
+}
+
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_EVB_SPC564A/board.h b/os/hal/boards/ST_EVB_SPC564A/board.h
new file mode 100644
index 000000000..f21a39067
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC564A/board.h
@@ -0,0 +1,71 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC564Axx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_SPC564AXX_EVB
+#define BOARD_NAME                  "EVB with SPC564Axx Mini Module"
+
+/*
+ * Device identifier.
+ */
+#define _SPC564A80L7_
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK               8000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define P5_ESCI_A_TX                9
+#define P5_ESCI_A_RX                10
+#define P11_BUTTON1                 3
+#define P11_BUTTON2                 5
+#define P11_BUTTON3                 7
+#define P11_BUTTON4                 9
+#define P11_LED1                    12
+#define P11_LED2                    13
+#define P11_LED3                    14
+#define P11_LED4                    15
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin)  (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC564A/board.mk b/os/hal/boards/ST_EVB_SPC564A/board.mk
new file mode 100644
index 000000000..e651b5d76
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC564A/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC564A/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC564A
diff --git a/os/hal/boards/ST_EVB_SPC56EC/board.c b/os/hal/boards/ST_EVB_SPC56EC/board.c
new file mode 100644
index 000000000..a2dafb994
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC56EC/board.c
@@ -0,0 +1,73 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+  {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH,   PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH,   PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON1), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON2), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON3), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_BUTTON4), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_E, PE_LED1),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_E, PE_LED2),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_E, PE_LED3),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_E, PE_LED4),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {-1, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   
+};
+
+/**
+ * @brief   PAL setup.
+ */
+const PALConfig pal_default_config =
+{
+  PAL_MODE_UNCONNECTED,
+  spc_siu_init,
+  spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_EVB_SPC56EC/board.h b/os/hal/boards/ST_EVB_SPC56EC/board.h
new file mode 100644
index 000000000..aef240066
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC56EC/board.h
@@ -0,0 +1,71 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC56ECxx board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_SPC56ECXX_EVB
+#define BOARD_NAME                  "EVB with SPC56ECxx Mini Module"
+
+/*
+ * Device identifier.
+ */
+#define _SPC56EC74L8_
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK               40000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX                 2
+#define PB_LIN0_RDX                 3
+#define PE_BUTTON1                  0
+#define PE_BUTTON2                  1
+#define PE_BUTTON3                  2
+#define PE_BUTTON4                  3
+#define PE_LED1                     4
+#define PE_LED2                     5
+#define PE_LED3                     6
+#define PE_LED4                     7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin)  (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC56EC/board.mk b/os/hal/boards/ST_EVB_SPC56EC/board.mk
new file mode 100644
index 000000000..c0d1627a1
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC56EC/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC56EC/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC56EC
diff --git a/os/hal/boards/ST_EVB_SPC56EL/board.c b/os/hal/boards/ST_EVB_SPC56EL/board.c
new file mode 100644
index 000000000..a6595d7d4
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC56EL/board.c
@@ -0,0 +1,70 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+  {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH,   PAL_MODE_OUTPUT_ALTERNATE(1)},
+  {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH,   PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON1), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON2), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON3), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_BUTTON4), PAL_LOW,    PAL_MODE_INPUT},
+  {PCR(PORT_D, PD_LED1),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_D, PD_LED2),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_D, PD_LED3),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {PCR(PORT_D, PD_LED4),    PAL_HIGH,   PAL_MODE_OUTPUT_PUSHPULL},
+  {-1, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   0,   0,   0,   0,   
+  0,   0,   0,   0,   
+};
+
+/**
+ * @brief   PAL setup.
+ */
+const PALConfig pal_default_config =
+{
+  PAL_MODE_UNCONNECTED,
+  spc_siu_init,
+  spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_EVB_SPC56EL/board.h b/os/hal/boards/ST_EVB_SPC56EL/board.h
new file mode 100644
index 000000000..23815b747
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC56EL/board.h
@@ -0,0 +1,66 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC56ELxx board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_SPC56ELXX_EVB
+#define BOARD_NAME                  "EVB with SPC56ELxx Mini Module"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK               40000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX                 2
+#define PB_LIN0_RDX                 3
+#define PD_BUTTON1                  0
+#define PD_BUTTON2                  1
+#define PD_BUTTON3                  2
+#define PD_BUTTON4                  3
+#define PD_LED1                     4
+#define PD_LED2                     5
+#define PD_LED3                     6
+#define PD_LED4                     7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin)  (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC56EL/board.mk b/os/hal/boards/ST_EVB_SPC56EL/board.mk
new file mode 100644
index 000000000..392be7a01
--- /dev/null
+++ b/os/hal/boards/ST_EVB_SPC56EL/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC56EL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC56EL
diff --git a/os/hal/boards/ST_STM3210C_EVAL/board.c b/os/hal/boards/ST_STM3210C_EVAL/board.c
new file mode 100644
index 000000000..f9e5a24b5
--- /dev/null
+++ b/os/hal/boards/ST_STM3210C_EVAL/board.c
@@ -0,0 +1,54 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * Remap USART2 to the PD5/PD6 pins.
+   */
+  AFIO->MAPR |= AFIO_MAPR_USART2_REMAP;
+}
diff --git a/os/hal/boards/ST_STM3210C_EVAL/board.h b/os/hal/boards/ST_STM3210C_EVAL/board.h
new file mode 100644
index 000000000..2193179b8
--- /dev/null
+++ b/os/hal/boards/ST_STM3210C_EVAL/board.h
@@ -0,0 +1,128 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the STMicroelectronics STM3210C-EVAL evaluation board.
+ */
+
+#define GPIOD_LED1              7
+#define GPIOD_LED2              13
+#define GPIOD_LED3              3
+#define GPIOD_LED4              4
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM3210C_EVAL
+#define BOARD_NAME              "ST STM3210C-EVAL"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            25000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_CL
+
+/*
+ * IO pins assignments.
+ * *********************TO BE COMPLETED*********************
+ */
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input except:
+ */
+#define VAL_GPIOACRL            0x44444444      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x44444444      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input except:
+ */
+#define VAL_GPIOBCRL            0x44444444      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x44444444      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input except:
+ */
+#define VAL_GPIOCCRL            0x44444444      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x44444444      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input except:
+ * PD5 - USART2TX (remapped) AF PP Output
+ * PD6 - USART2RX (remapped) Digital Input
+ * PD7 - LED (LD1) PP Output
+ */
+#define VAL_GPIODCRL            0x34B33444      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x44344444      /* PD15...PD8 */
+#define VAL_GPIODODR            0x0000DF67
+
+/*
+ * Port E setup.
+ * Everything input except:
+ */
+#define VAL_GPIOECRL            0x44444444      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x44344444      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM3210C_EVAL/board.mk b/os/hal/boards/ST_STM3210C_EVAL/board.mk
new file mode 100644
index 000000000..02e3c6151
--- /dev/null
+++ b/os/hal/boards/ST_STM3210C_EVAL/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM3210C_EVAL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM3210C_EVAL
diff --git a/os/hal/boards/ST_STM3210E_EVAL/board.c b/os/hal/boards/ST_STM3210E_EVAL/board.c
new file mode 100644
index 000000000..6cdd8d4fc
--- /dev/null
+++ b/os/hal/boards/ST_STM3210E_EVAL/board.c
@@ -0,0 +1,67 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+  {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
+  {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC
+/* Board-related functions related to the SDC driver.*/
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  return !palReadPad(GPIOF, GPIOF_SD_DETECT);
+}
+
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  return FALSE;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_STM3210E_EVAL/board.h b/os/hal/boards/ST_STM3210E_EVAL/board.h
new file mode 100644
index 000000000..739b3e089
--- /dev/null
+++ b/os/hal/boards/ST_STM3210E_EVAL/board.h
@@ -0,0 +1,251 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the STMicroelectronics STM3210E-EVAL evaluation board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM3210E_EVAL
+#define BOARD_NAME              "ST STM3210E-EVAL"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ * Note: Older board revisions should define STM32F10X_HD instead, please
+ *       verify the STM32 model mounted on your board. The change also
+ *       affects your linker script.
+ */
+#define STM32F10X_XL
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_WAKEUP_BUTTON     0
+
+#define GPIOB_SC_3V_5V          0
+#define GPIOB_SPI1_CS           2
+#define GPIOB_TEMP_INT          5
+#define GPIOB_USB_DISC          14
+
+#define GPIOC_SC_CMDVCC         6
+#define GPIOC_SC_OFF            7
+#define GPIOC_TAMPER_BUTTON     13
+
+#define GPIOD_JOY_DOWN          3
+
+#define GPIOF_LED1              6
+#define GPIOF_LED2              7
+#define GPIOF_LED3              8
+#define GPIOF_LED4              9
+#define GPIOF_SD_DETECT         11
+
+#define GPIOG_JOY_SEL           7
+#define GPIOG_USER_BUTTON       8
+#define GPIOG_JOY_RIGHT         13
+#define GPIOG_JOY_LEFT          14
+#define GPIOG_JOY_UP            15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_ANALOG(n)           (0 << (((n) & 7) * 4))
+#define PIN_OUTPUT_PP_10(n)     (1 << (((n) & 7) * 4))
+#define PIN_OUTPUT_PP_2(n)      (2 << (((n) & 7) * 4))
+#define PIN_OUTPUT_PP_50(n)     (3 << (((n) & 7) * 4))
+#define PIN_INPUT(n)            (4 << (((n) & 7) * 4))
+#define PIN_OUTPUT_OD_10(n)     (5 << (((n) & 7) * 4))
+#define PIN_OUTPUT_OD_2(n)      (6 << (((n) & 7) * 4))
+#define PIN_OUTPUT_OD_50(n)     (7 << (((n) & 7) * 4))
+#define PIN_INPUT_PUD(n)        (8 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_PP_10(n)  (9 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_PP_2(n)   (10 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_PP_50(n)  (11 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_OD_10(n)  (13 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_OD_2(n)   (14 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_OD_50(n)  (15 << (((n) & 7) * 4))
+#define PIN_UNDEFINED(n)        PIN_INPUT_PUD(n)
+
+/*
+ * Port A setup.
+ */
+#define VAL_GPIOACRL    (PIN_INPUT(0)           | /* Wakeup Button.     */  \
+                         PIN_OUTPUT_PP_50(1)    | /* USART2_RTS.        */  \
+                         PIN_ALTERNATE_PP_50(2) | /* USART2_TX.         */  \
+                         PIN_INPUT(3)           | /* USART2_RX.         */  \
+                         PIN_UNDEFINED(4)       |                           \
+                         PIN_ALTERNATE_PP_50(5) | /* SPI1_SCK.          */  \
+                         PIN_INPUT(6)           | /* SPI1_MISO.         */  \
+                         PIN_ALTERNATE_PP_50(7))  /* SPI1_MOSI.         */
+#define VAL_GPIOACRH    (PIN_ALTERNATE_PP_50(8) | /* MCO.               */  \
+                         PIN_ALTERNATE_PP_50(9) | /* USART1_TX.         */  \
+                         PIN_INPUT(10)          | /* USART1_RX.         */  \
+                         PIN_INPUT_PUD(11)      | /* USB_DM.            */  \
+                         PIN_INPUT_PUD(12)      | /* USB_DP.            */  \
+                         PIN_INPUT(13)          | /* TMS.               */  \
+                         PIN_INPUT(14)          | /* TCK.               */  \
+                         PIN_INPUT(15))           /* TDI.               */
+#define VAL_GPIOAODR    0xFFFFFFFF
+
+/*
+ * Port B setup.
+ */
+#define VAL_GPIOBCRL    (PIN_OUTPUT_PP_50(0)    | /* SmartCard_3/5V.    */  \
+                         PIN_INPUT_PUD(1)       | /* Unconnected.       */  \
+                         PIN_OUTPUT_PP_50(2)    | /* SPI1_CS.           */  \
+                         PIN_INPUT(3)           | /* TDO.               */  \
+                         PIN_INPUT(4)           | /* TRST.              */  \
+                         PIN_INPUT_PUD(5)       | /* Temp.Sensor INT.   */  \
+                         PIN_ALTERNATE_OD_50(6) | /* I2C1_SCK.          */  \
+                         PIN_ALTERNATE_OD_50(7))  /* I2C1_SDA.          */
+#define VAL_GPIOBCRH    (PIN_INPUT(8)           | /* CAN_RX.            */  \
+                         PIN_ALTERNATE_PP_50(9) | /* CAN_TX.            */  \
+                         PIN_ALTERNATE_OD_50(10)| /* SmartCard IO.      */  \
+                         PIN_OUTPUT_PP_50(11)   | /* SmartCard RST.     */  \
+                         PIN_ALTERNATE_PP_50(12)| /* SmartCard CLK.     */  \
+                         PIN_UNDEFINED(13)      |                           \
+                         PIN_OUTPUT_PP_50(14)   | /* USB disconnect.    */  \
+                         PIN_UNDEFINED(15))
+#define VAL_GPIOBODR    0xFFFFFFFF
+
+/*
+ * Port C setup.
+ */
+#define VAL_GPIOCCRL    (PIN_UNDEFINED(0)       |                           \
+                         PIN_UNDEFINED(1)       |                           \
+                         PIN_UNDEFINED(2)       |                           \
+                         PIN_UNDEFINED(3)       |                           \
+                         PIN_ANALOG(4)          | /* Potentiometer.     */  \
+                         PIN_UNDEFINED(5)       |                           \
+                         PIN_OUTPUT_PP_50(6)    | /* SmartCard CMDVCC.  */  \
+                         PIN_INPUT(7))            /* SmartCard OFF.     */
+#define VAL_GPIOCCRH    (PIN_ALTERNATE_PP_50(8) | /* SDIO D0.           */  \
+                         PIN_ALTERNATE_PP_50(9) | /* SDIO D1.           */  \
+                         PIN_ALTERNATE_PP_50(10)| /* SDIO D2.           */  \
+                         PIN_ALTERNATE_PP_50(11)| /* SDIO D3.           */  \
+                         PIN_ALTERNATE_PP_50(12)| /* SDIO CLK.          */  \
+                         PIN_INPUT(13)          | /* Tamper Button.     */  \
+                         PIN_INPUT(14)          | /* OSC IN.            */  \
+                         PIN_INPUT(15))           /* OSC OUT.           */
+#define VAL_GPIOCODR    0xFFFFFFFF
+
+/*
+ * Port D setup
+ */
+#define VAL_GPIODCRL    (PIN_ALTERNATE_PP_50(0) | /* FSMC_D2.           */  \
+                         PIN_ALTERNATE_PP_50(1) | /* FSMC_D3.           */  \
+                         PIN_ALTERNATE_PP_50(2) | /* SDIO CMD.          */  \
+                         PIN_INPUT(3)           | /* Joy Down.          */  \
+                         PIN_ALTERNATE_PP_50(4) | /* FSMC_NOE.          */  \
+                         PIN_ALTERNATE_PP_50(5) | /* FSMC_NWE.          */  \
+                         PIN_INPUT(6)           | /* FSMC_NWAIT.        */  \
+                         PIN_ALTERNATE_PP_50(7))  /* FSMC_NCE2.         */
+#define VAL_GPIODCRH    (PIN_ALTERNATE_PP_50(8) | /* FSMC_D13.          */  \
+                         PIN_ALTERNATE_PP_50(9) | /* FSMC_D14.          */  \
+                         PIN_ALTERNATE_PP_50(10)| /* FSMC_D15.          */  \
+                         PIN_ALTERNATE_PP_50(11)| /* FSMC_A16.          */  \
+                         PIN_ALTERNATE_PP_50(12)| /* FSMC_A17.          */  \
+                         PIN_ALTERNATE_PP_50(13)| /* FSMC_A18.          */  \
+                         PIN_ALTERNATE_PP_50(14)| /* FSMC_D0.           */  \
+                         PIN_ALTERNATE_PP_50(15)) /* FSMC_D1.           */
+#define VAL_GPIODODR    0xFFFFFFFF
+
+/*
+ * Port E setup.
+ */
+#define VAL_GPIOECRL    (PIN_ALTERNATE_PP_50(0) | /* FSMC_NBL0.         */  \
+                         PIN_ALTERNATE_PP_50(1) | /* FSMC_NBL1.         */  \
+                         PIN_ALTERNATE_PP_50(2) | /* FSMC_A23.          */  \
+                         PIN_ALTERNATE_PP_50(3) | /* FSMC_A19.          */  \
+                         PIN_ALTERNATE_PP_50(4) | /* FSMC_A20.          */  \
+                         PIN_ALTERNATE_PP_50(5) | /* FSMC_A21.          */  \
+                         PIN_ALTERNATE_PP_50(6) | /* FSMC_A22.          */  \
+                         PIN_ALTERNATE_PP_50(7))  /* FSMC_D4.           */
+#define VAL_GPIOECRH    (PIN_ALTERNATE_PP_50(8) | /* FSMC_D5.           */  \
+                         PIN_ALTERNATE_PP_50(9) | /* FSMC_D6.           */  \
+                         PIN_ALTERNATE_PP_50(10)| /* FSMC_D7.           */  \
+                         PIN_ALTERNATE_PP_50(11)| /* FSMC_D8.           */  \
+                         PIN_ALTERNATE_PP_50(12)| /* FSMC_D9.           */  \
+                         PIN_ALTERNATE_PP_50(13)| /* FSMC_D10.          */  \
+                         PIN_ALTERNATE_PP_50(14)| /* FSMC_D11.          */  \
+                         PIN_ALTERNATE_PP_50(15)) /* FSMC_D12.          */
+#define VAL_GPIOEODR    0xFFFFFFFF
+
+/*
+ * Port F setup.
+ */
+#define VAL_GPIOFCRL    (PIN_ALTERNATE_PP_50(0) | /* FSMC_A0.           */  \
+                         PIN_ALTERNATE_PP_50(1) | /* FSMC_A1.           */  \
+                         PIN_ALTERNATE_PP_50(2) | /* FSMC_A2.           */  \
+                         PIN_ALTERNATE_PP_50(3) | /* FSMC_A3.           */  \
+                         PIN_ALTERNATE_PP_50(4) | /* FSMC_A4.           */  \
+                         PIN_ALTERNATE_PP_50(5) | /* FSMC_A5.           */  \
+                         PIN_OUTPUT_PP_50(6)    | /* LED1.              */  \
+                         PIN_OUTPUT_PP_50(7))     /* LED2.              */
+#define VAL_GPIOFCRH    (PIN_OUTPUT_PP_50(8)    | /* LED3.              */  \
+                         PIN_OUTPUT_PP_50(9)    | /* LED4.              */  \
+                         PIN_UNDEFINED(10)      |                           \
+                         PIN_INPUT_PUD(11)      | /* SDCard detect.     */  \
+                         PIN_ALTERNATE_PP_50(12)| /* FSMC_A6.           */  \
+                         PIN_ALTERNATE_PP_50(13)| /* FSMC_A7.           */  \
+                         PIN_ALTERNATE_PP_50(14)| /* FSMC_A8.           */  \
+                         PIN_ALTERNATE_PP_50(15)) /* FSMC_A9.           */
+#define VAL_GPIOFODR    0xFFFFFC3F
+
+/*
+ * Port G setup.
+ */
+#define VAL_GPIOGCRL    (PIN_ALTERNATE_PP_50(0) | /* FSMC_A10.          */  \
+                         PIN_ALTERNATE_PP_50(1) | /* FSMC_A11.          */  \
+                         PIN_ALTERNATE_PP_50(2) | /* FSMC_A12.          */  \
+                         PIN_ALTERNATE_PP_50(3) | /* FSMC_A13.          */  \
+                         PIN_ALTERNATE_PP_50(4) | /* FSMC_A14.          */  \
+                         PIN_ALTERNATE_PP_50(5) | /* FSMC_A15.          */  \
+                         PIN_INPUT(6)           | /* FSMC_INT2.         */  \
+                         PIN_INPUT(7))            /* Joy Select.        */
+#define VAL_GPIOGCRH    (PIN_INPUT(8)           | /* User Button.       */  \
+                         PIN_ALTERNATE_PP_50(9) | /* FSMC_NE2.          */  \
+                         PIN_ALTERNATE_PP_50(10)| /* FSMC_NE3.          */  \
+                         PIN_OUTPUT_PP_50(11)   | /* Audio PDN.         */  \
+                         PIN_ALTERNATE_PP_50(12)| /* FSMC_NE4.          */  \
+                         PIN_INPUT(13)          | /* Joy Right.         */  \
+                         PIN_INPUT(14)          | /* Joy Left.          */  \
+                         PIN_INPUT(15))           /* Joy Up.            */
+#define VAL_GPIOGODR    0xFFFFF7FF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM3210E_EVAL/board.mk b/os/hal/boards/ST_STM3210E_EVAL/board.mk
new file mode 100644
index 000000000..3ad9f44b1
--- /dev/null
+++ b/os/hal/boards/ST_STM3210E_EVAL/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM3210E_EVAL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM3210E_EVAL
diff --git a/os/hal/boards/ST_STM3220G_EVAL/board.c b/os/hal/boards/ST_STM3220G_EVAL/board.c
new file mode 100644
index 000000000..9eea48d0a
--- /dev/null
+++ b/os/hal/boards/ST_STM3220G_EVAL/board.c
@@ -0,0 +1,53 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM3220G_EVAL/board.h b/os/hal/boards/ST_STM3220G_EVAL/board.h
new file mode 100644
index 000000000..07cfc5dea
--- /dev/null
+++ b/os/hal/boards/ST_STM3220G_EVAL/board.h
@@ -0,0 +1,226 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM3220G-EVAL board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM3220G_EVAL
+#define BOARD_NAME              "ST STM3220G-EVAL"
+
+/*
+ * Board frequencies.
+ * NOTE: The HSE crystal is not fitted by default on the board.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            25000000
+
+/*
+ * MCU type as defined in the ST header file stm32f2xx.h.
+ */
+#define STM32F2XX
+
+/*
+ * IO pins assignments.
+ */
+
+#define GPIOA_WAKEUP_BUTTON     0
+
+#define GPIOB_ETHER_INT         14
+#define GPIOB_NAND_INT          15
+
+#define GPIOC_TAMPER_BUTTON     0
+#define GPIOC_LED4              7
+
+#define GPIOF_POT               9
+
+#define GPIOG_LED1              6
+#define GPIOG_LED2              8
+#define GPIOG_USER_BUTTON       15
+
+#define GPIOH_EXPANDER_INT      12
+#define GPIOH_SD_DETECT         13
+
+#define GPIOI_LED3              9
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0 << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1 << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2 << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3 << ((n) * 2))
+#define PIN_OTYPE_PUSHPULL(n)       (0 << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1 << (n))
+#define PIN_OSPEED_2M(n)            (0 << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1 << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2 << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3 << ((n) * 2))
+#define PIN_PUDR_FLOATING(n)        (0 << ((n) * 2))
+#define PIN_PUDR_PULLUP(n)          (1 << ((n) * 2))
+#define PIN_PUDR_PULLDOWN(n)        (2 << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * Port A setup.
+ * All input with pull-up except:
+ * PA8  - MCO 1         (alternate 0).
+ * PA13 - JTMS/SWDAT    (alternate 0).
+ * PA14 - JTCK/SWCLK    (alternate 0).
+ * PA15 - JTDI          (alternate 0).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_ALTERNATE(8)    | \
+                                     PIN_MODE_ALTERNATE(13)   | \
+                                     PIN_MODE_ALTERNATE(14)   | \
+                                     PIN_MODE_ALTERNATE(15))
+#define VAL_GPIOA_OTYPER            0x00000000
+#define VAL_GPIOA_OSPEEDR           0xFFFFFFFF
+#define VAL_GPIOA_PUPDR             (PIN_PUDR_FLOATING(13)    | \
+                                     PIN_PUDR_FLOATING(14)    | \
+                                     PIN_PUDR_FLOATING(15))
+#define VAL_GPIOA_ODR               0xFFFFFFFF
+#define VAL_GPIOA_AFRL				0x00000000
+#define VAL_GPIOA_AFRH				0x00000000
+
+/*
+ * Port B setup.
+ * All input with pull-up except:
+ * PB3  - JTDO          (alternate 0).
+ * PB4  - JNTRST        (alternate 0).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_ALTERNATE(3)    | \
+                                     PIN_MODE_ALTERNATE(4))
+#define VAL_GPIOB_OTYPER            0x00000000
+#define VAL_GPIOB_OSPEEDR           0xFFFFFFFF
+#define VAL_GPIOB_PUPDR             (~(PIN_PUDR_FLOATING(3)   | \
+                                       PIN_PUDR_FLOATING(4)))
+#define VAL_GPIOB_ODR               0xFFFFFFFF
+#define VAL_GPIOB_AFRL				0x00000000
+#define VAL_GPIOB_AFRH				0x00000000
+
+/*
+ * Port C setup.
+ * All input with pull-up except:
+ * PC9  - MCO2          (alternate 0).
+ * PC10 - USART3_TX     (alternate 7).
+ * PC11 - USART3_RX     (alternate 7).
+ * PC14 - OSC32_INT     (input floating).
+ * PC15 - OSC32_OUT     (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_ALTERNATE(9)    | \
+                                    PIN_MODE_ALTERNATE(10)    | \
+                                    PIN_MODE_ALTERNATE(11))
+#define VAL_GPIOC_OTYPER            0x00000000
+#define VAL_GPIOC_OSPEEDR           0xFFFFFFFF
+#define VAL_GPIOC_PUPDR             (~(PIN_PUDR_PULLUP(11)    | \
+                                       PIN_PUDR_FLOATING(14)  | \
+                                       PIN_PUDR_FLOATING(15)))
+#define VAL_GPIOC_ODR               0xFFFFFFFF
+#define VAL_GPIOC_AFRL				0x00000000
+#define VAL_GPIOC_AFRH				(PIN_AFIO_AF(7, 10)       | \
+                                     PIN_AFIO_AF(7, 11))
+
+/*
+ * Port D setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOD_MODER             0x00000000
+#define VAL_GPIOD_OTYPER            0x00000000
+#define VAL_GPIOD_OSPEEDR           0xFFFFFFFF
+#define VAL_GPIOD_PUPDR             0xFFFFFFFF
+#define VAL_GPIOD_ODR               0xFFFFFFFF
+#define VAL_GPIOD_AFRL				0x00000000
+#define VAL_GPIOD_AFRH				0x00000000
+
+/*
+ * Port E setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOE_MODER             0x00000000
+#define VAL_GPIOE_OTYPER            0x00000000
+#define VAL_GPIOE_OSPEEDR           0xFFFFFFFF
+#define VAL_GPIOE_PUPDR             0xFFFFFFFF
+#define VAL_GPIOE_ODR               0xFFFFFFFF
+#define VAL_GPIOE_AFRL				0x00000000
+#define VAL_GPIOE_AFRH				0x00000000
+
+/*
+ * Port F setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOF_MODER             0x00000000
+#define VAL_GPIOF_OTYPER            0x00000000
+#define VAL_GPIOF_OSPEEDR           0xFFFFFFFF
+#define VAL_GPIOF_PUPDR             0xFFFFFFFF
+#define VAL_GPIOF_ODR               0xFFFFFFFF
+#define VAL_GPIOF_AFRL				0x00000000
+#define VAL_GPIOF_AFRH				0x00000000
+
+/*
+ * Port G setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOG_MODER             (PIN_MODE_OUTPUT(GPIOG_LED1))
+#define VAL_GPIOG_OTYPER            0x00000000
+#define VAL_GPIOG_OSPEEDR           0xFFFFFFFF
+#define VAL_GPIOG_PUPDR             (~(PIN_PUDR_FLOATING(GPIOG_LED1)))
+#define VAL_GPIOG_ODR               0xFFFFFFBF
+#define VAL_GPIOG_AFRL				0x00000000
+#define VAL_GPIOG_AFRH				0x00000000
+
+/*
+ * Port H setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOH_MODER             0x00000000
+#define VAL_GPIOH_OTYPER            0x00000000
+#define VAL_GPIOH_OSPEEDR           0xFFFFFFFF
+#define VAL_GPIOH_PUPDR             0xFFFFFFFF
+#define VAL_GPIOH_ODR               0xFFFFFFFF
+#define VAL_GPIOH_AFRL				0x00000000
+#define VAL_GPIOH_AFRH				0x00000000
+
+/*
+ * Port I setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOI_MODER             0x00000000
+#define VAL_GPIOI_OTYPER            0x00000000
+#define VAL_GPIOI_OSPEEDR           0xFFFFFFFF
+#define VAL_GPIOI_PUPDR             0xFFFFFFFF
+#define VAL_GPIOI_ODR               0xFFFFFFFF
+#define VAL_GPIOI_AFRL				0x00000000
+#define VAL_GPIOI_AFRH				0x00000000
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM3220G_EVAL/board.mk b/os/hal/boards/ST_STM3220G_EVAL/board.mk
new file mode 100644
index 000000000..09c301c79
--- /dev/null
+++ b/os/hal/boards/ST_STM3220G_EVAL/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM3220G_EVAL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM3220G_EVAL
diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.c b/os/hal/boards/ST_STM32373C_EVAL/board.c
new file mode 100644
index 000000000..19756cca7
--- /dev/null
+++ b/os/hal/boards/ST_STM32373C_EVAL/board.c
@@ -0,0 +1,101 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH}
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.h b/os/hal/boards/ST_STM32373C_EVAL/board.h
new file mode 100644
index 000000000..13676e7e6
--- /dev/null
+++ b/os/hal/boards/ST_STM32373C_EVAL/board.h
@@ -0,0 +1,888 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32373C-EVAL board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32373C_EVAL
+#define BOARD_NAME                  "STMicroelectronics STM32373C-EVAL"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                32768
+#endif
+
+#define STM32_LSEDRV                (3 << 3)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                8000000
+#endif
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F37X
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_WKUP_BUTTON           0
+#define GPIOA_LDR_OUT               1
+#define GPIOA_KEY_BUTTON            2
+#define GPIOA_PIN3                  3
+#define GPIOA_PIN4                  4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_COMP2_OUT             7
+#define GPIOA_I2C2_SMB              8
+#define GPIOA_I2C2_SCL              9
+#define GPIOA_I2C2_SDA              10
+#define GPIOA_USB_DM                11
+#define GPIOA_USB_DP                12
+#define GPIOA_SWDIO                 13
+#define GPIOA_SWCLK                 14
+#define GPIOA_JTDI                  15
+
+#define GPIOB_MIC_IN                0
+#define GPIOB_ADC_POT_IN            1
+#define GPIOB_PIN2                  2
+#define GPIOB_SWO                   3
+#define GPIOB_JTRST                 4
+#define GPIOB_PIN5                  5
+#define GPIOB_I2C1_SCL              6
+#define GPIOB_I2C1_SDA              7
+#define GPIOB_PIN8                  8
+#define GPIOB_PIN9                  9
+#define GPIOB_PIN10                 10
+#define GPIOB_PIN11                 11
+#define GPIOB_PIN12                 12
+#define GPIOB_PIN13                 13
+#define GPIOB_PIN14                 14
+#define GPIOB_PIN15                 15
+
+#define GPIOC_LED1                  0
+#define GPIOC_LED2                  1
+#define GPIOC_LED3                  2
+#define GPIOC_LED4                  3
+#define GPIOC_PIN4                  4
+#define GPIOC_USB_DISCONNECT        5
+#define GPIOC_PIN6                  6
+#define GPIOC_PIN7                  7
+#define GPIOC_PIN8                  8
+#define GPIOC_PIN9                  9
+#define GPIOC_SPI3_SCK              10
+#define GPIOC_SPI3_MISO             11
+#define GPIOC_SPI3_MOSI             12
+#define GPIOC_PIN13                 13
+#define GPIOC_OSC32_IN              14
+#define GPIOC_OSC32_OUT             15
+
+#define GPIOD_CAN_RX                0
+#define GPIOD_CAN_TX                1
+#define GPIOD_LCD_CS                2
+#define GPIOD_USART2_CTS            3
+#define GPIOD_USART2_RST            4
+#define GPIOD_USART2_TX             5
+#define GPIOD_USART2_RX             6
+#define GPIOD_PIN7                  7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_AUDIO_RST             11
+#define GPIOD_PIN12                 12
+#define GPIOD_PIN13                 13
+#define GPIOD_PIN14                 14
+#define GPIOD_PIN15                 15
+
+#define GPIOE_PIN0                  0
+#define GPIOE_PIN1                  1
+#define GPIOE_SD_CS                 2
+#define GPIOE_SD_DETECT             3
+#define GPIOE_PIN4                  4
+#define GPIOE_PIN5                  5
+#define GPIOE_JOY_SEL               6
+#define GPIOE_RTD_IN                7
+#define GPIOE_PRESSUREP             8
+#define GPIOE_PRESSUREN             9
+#define GPIOE_PIN10                 10
+#define GPIOE_PIN11                 11
+#define GPIOE_PIN12                 12
+#define GPIOE_PIN13                 13
+#define GPIOE_PRESSURE_TEPM         14
+#define GPIOE_PIN15                 15
+
+#define GPIOF_OSC_IN                0
+#define GPIOF_OSC_OUT               1
+#define GPIOF_JOY_DOWN              2
+#define GPIOF_PIN3                  3
+#define GPIOF_JOY_LEFT              4
+#define GPIOF_PIN5                  5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_JOY_RIGHT             9
+#define GPIOF_JOY_UP                10
+#define GPIOF_PIN11                 11
+#define GPIOF_PIN12                 12
+#define GPIOF_PIN13                 13
+#define GPIOF_PIN14                 14
+#define GPIOF_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - WKUP_BUTTON               (input floating).
+ * PA1  - LDR_OUT                   (analog).
+ * PA2  - KEY_BUTTON                (input floating).
+ * PA3  - PIN3                      (input pullup).
+ * PA4  - PIN4                      (input pullup).
+ * PA5  - PIN5                      (input floating).
+ * PA6  - PIN6                      (input pullup).
+ * PA7  - COMP2_OUT                 (output pushpull maximum).
+ * PA8  - I2C2_SMB                  (input floating).
+ * PA9  - I2C2_SCL                  (alternate 4).
+ * PA10 - I2C2_SDA                  (alternate 4).
+ * PA11 - USB_DM                    (alternate 14).
+ * PA12 - USB_DP                    (alternate 14).
+ * PA13 - SWDIO                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 - JTDI                      (alternate 0).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_WKUP_BUTTON) |    \
+                                     PIN_MODE_ANALOG(GPIOA_LDR_OUT) |       \
+                                     PIN_MODE_INPUT(GPIOA_KEY_BUTTON) |     \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
+                                     PIN_MODE_OUTPUT(GPIOA_COMP2_OUT) |     \
+                                     PIN_MODE_INPUT(GPIOA_I2C2_SMB) |       \
+                                     PIN_MODE_ALTERNATE(GPIOA_I2C2_SCL) |   \
+                                     PIN_MODE_ALTERNATE(GPIOA_I2C2_SDA) |   \
+                                     PIN_MODE_ALTERNATE(GPIOA_USB_DM) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_USB_DP) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTDI))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_WKUP_BUTTON) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_LDR_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_KEY_BUTTON) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_COMP2_OUT) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_I2C2_SMB) |   \
+                                     PIN_OTYPE_OPENDRAIN(GPIOA_I2C2_SCL) |  \
+                                     PIN_OTYPE_OPENDRAIN(GPIOA_I2C2_SDA) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTDI))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_2M(GPIOA_WKUP_BUTTON) |     \
+                                     PIN_OSPEED_2M(GPIOA_LDR_OUT) |         \
+                                     PIN_OSPEED_2M(GPIOA_KEY_BUTTON) |      \
+                                     PIN_OSPEED_2M(GPIOA_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN4) |            \
+                                     PIN_OSPEED_100M(GPIOA_PIN5) |          \
+                                     PIN_OSPEED_2M(GPIOA_PIN6) |            \
+                                     PIN_OSPEED_100M(GPIOA_COMP2_OUT) |     \
+                                     PIN_OSPEED_2M(GPIOA_I2C2_SMB) |        \
+                                     PIN_OSPEED_100M(GPIOA_I2C2_SCL) |      \
+                                     PIN_OSPEED_100M(GPIOA_I2C2_SDA) |      \
+                                     PIN_OSPEED_100M(GPIOA_USB_DM) |        \
+                                     PIN_OSPEED_2M(GPIOA_USB_DP) |          \
+                                     PIN_OSPEED_100M(GPIOA_SWDIO) |         \
+                                     PIN_OSPEED_100M(GPIOA_SWCLK) |         \
+                                     PIN_OSPEED_100M(GPIOA_JTDI))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_WKUP_BUTTON) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_LDR_OUT) |    \
+                                     PIN_PUPDR_FLOATING(GPIOA_KEY_BUTTON) | \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN5) |       \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_COMP2_OUT) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_I2C2_SMB) |   \
+                                     PIN_PUPDR_FLOATING(GPIOA_I2C2_SCL) |   \
+                                     PIN_PUPDR_FLOATING(GPIOA_I2C2_SDA) |   \
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DM) |     \
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DP) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_SWDIO) |        \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \
+                                     PIN_PUPDR_FLOATING(GPIOA_JTDI))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_WKUP_BUTTON) |      \
+                                     PIN_ODR_HIGH(GPIOA_LDR_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOA_KEY_BUTTON) |       \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_LOW(GPIOA_COMP2_OUT) |         \
+                                     PIN_ODR_HIGH(GPIOA_I2C2_SMB) |         \
+                                     PIN_ODR_HIGH(GPIOA_I2C2_SCL) |         \
+                                     PIN_ODR_HIGH(GPIOA_I2C2_SDA) |         \
+                                     PIN_ODR_HIGH(GPIOA_USB_DM) |           \
+                                     PIN_ODR_HIGH(GPIOA_USB_DP) |           \
+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
+                                     PIN_ODR_HIGH(GPIOA_JTDI))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_WKUP_BUTTON, 0) |    \
+                                     PIN_AFIO_AF(GPIOA_LDR_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOA_KEY_BUTTON, 0) |     \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 5) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_COMP2_OUT, 0))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_I2C2_SMB, 0) |       \
+                                     PIN_AFIO_AF(GPIOA_I2C2_SCL, 4) |       \
+                                     PIN_AFIO_AF(GPIOA_I2C2_SDA, 4) |       \
+                                     PIN_AFIO_AF(GPIOA_USB_DM, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_USB_DP, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_JTDI, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - MIC_IN                    (analog).
+ * PB1  - ADC_POT_IN                (analog).
+ * PB2  - PIN2                      (input pullup).
+ * PB3  - SWO                       (alternate 0).
+ * PB4  - JTRST                     (input floating).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - I2C1_SCL                  (alternate 4).
+ * PB7  - I2C1_SDA                  (alternate 4).
+ * PB8  - PIN8                      (input pullup).
+ * PB9  - PIN9                      (input pullup).
+ * PB10 - PIN10                     (input pullup).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - PIN13                     (input pullup).
+ * PB14 - PIN14                     (input pullup).
+ * PB15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_ANALOG(GPIOB_MIC_IN) |        \
+                                     PIN_MODE_ANALOG(GPIOB_ADC_POT_IN) |    \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SWO) |        \
+                                     PIN_MODE_INPUT(GPIOB_JTRST) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) |   \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_MIC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_ADC_POT_IN) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SWO) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_JTRST) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) |  \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_2M(GPIOB_MIC_IN) |          \
+                                     PIN_OSPEED_2M(GPIOB_ADC_POT_IN) |      \
+                                     PIN_OSPEED_2M(GPIOB_PIN2) |            \
+                                     PIN_OSPEED_100M(GPIOB_SWO) |           \
+                                     PIN_OSPEED_100M(GPIOB_JTRST) |         \
+                                     PIN_OSPEED_2M(GPIOB_PIN5) |            \
+                                     PIN_OSPEED_100M(GPIOB_I2C1_SCL) |      \
+                                     PIN_OSPEED_100M(GPIOB_I2C1_SDA) |      \
+                                     PIN_OSPEED_2M(GPIOB_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_FLOATING(GPIOB_MIC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOB_ADC_POT_IN) | \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_SWO) |        \
+                                     PIN_PUPDR_FLOATING(GPIOB_JTRST) |      \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) |   \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_MIC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOB_ADC_POT_IN) |       \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_SWO) |              \
+                                     PIN_ODR_HIGH(GPIOB_JTRST) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_I2C1_SCL) |         \
+                                     PIN_ODR_HIGH(GPIOB_I2C1_SDA) |         \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_MIC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOB_ADC_POT_IN, 0) |     \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SWO, 0) |            \
+                                     PIN_AFIO_AF(GPIOB_JTRST, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) |       \
+                                     PIN_AFIO_AF(GPIOB_I2C1_SDA, 4))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - LED1                      (output opendrain maximum).
+ * PC1  - LED2                      (output opendrain maximum).
+ * PC2  - LED3                      (output opendrain maximum).
+ * PC3  - LED4                      (output opendrain maximum).
+ * PC4  - PIN4                      (input pullup).
+ * PC5  - USB_DISCONNECT            (output pushpull maximum).
+ * PC6  - PIN6                      (input pullup).
+ * PC7  - PIN7                      (input pullup).
+ * PC8  - PIN8                      (input pullup).
+ * PC9  - PIN9                      (input pullup).
+ * PC10 - SPI3_SCK                  (alternate 6).
+ * PC11 - SPI3_MISO                 (alternate 6).
+ * PC12 - SPI3_MOSI                 (alternate 6).
+ * PC13 - PIN13                     (input pullup).
+ * PC14 - OSC32_IN                  (input floating).
+ * PC15 - OSC32_OUT                 (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_OUTPUT(GPIOC_LED1) |          \
+                                     PIN_MODE_OUTPUT(GPIOC_LED2) |          \
+                                     PIN_MODE_OUTPUT(GPIOC_LED3) |          \
+                                     PIN_MODE_OUTPUT(GPIOC_LED4) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_OUTPUT(GPIOC_USB_DISCONNECT) |\
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) |   \
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) |  \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_OPENDRAIN(GPIOC_LED1) |      \
+                                     PIN_OTYPE_OPENDRAIN(GPIOC_LED2) |      \
+                                     PIN_OTYPE_OPENDRAIN(GPIOC_LED3) |      \
+                                     PIN_OTYPE_OPENDRAIN(GPIOC_LED4) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_USB_DISCONNECT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI3_SCK) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MISO) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MOSI) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_100M(GPIOC_LED1) |          \
+                                     PIN_OSPEED_100M(GPIOC_LED2) |          \
+                                     PIN_OSPEED_100M(GPIOC_LED3) |          \
+                                     PIN_OSPEED_100M(GPIOC_LED4) |          \
+                                     PIN_OSPEED_2M(GPIOC_PIN4) |            \
+                                     PIN_OSPEED_100M(GPIOC_USB_DISCONNECT) |\
+                                     PIN_OSPEED_2M(GPIOC_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN9) |            \
+                                     PIN_OSPEED_100M(GPIOC_SPI3_SCK) |      \
+                                     PIN_OSPEED_100M(GPIOC_SPI3_MISO) |     \
+                                     PIN_OSPEED_100M(GPIOC_SPI3_MOSI) |     \
+                                     PIN_OSPEED_2M(GPIOC_PIN13) |           \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_IN) |      \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_FLOATING(GPIOC_LED1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_LED2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_LED3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_LED4) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_USB_DISCONNECT) |\
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN9) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI3_SCK) |   \
+                                     PIN_PUPDR_PULLUP(GPIOC_SPI3_MISO) |    \
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI3_MOSI) |  \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_LED1) |             \
+                                     PIN_ODR_HIGH(GPIOC_LED2) |             \
+                                     PIN_ODR_HIGH(GPIOC_LED3) |             \
+                                     PIN_ODR_HIGH(GPIOC_LED4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_USB_DISCONNECT) |   \
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOC_SPI3_SCK) |         \
+                                     PIN_ODR_HIGH(GPIOC_SPI3_MISO) |        \
+                                     PIN_ODR_HIGH(GPIOC_SPI3_MOSI) |        \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_LED1, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_LED2, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_LED3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_LED4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_USB_DISCONNECT, 0) | \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_SPI3_SCK, 6) |       \
+                                     PIN_AFIO_AF(GPIOC_SPI3_MISO, 6) |      \
+                                     PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6) |      \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0) |       \
+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - CAN_RX                    (alternate 7).
+ * PD1  - CAN_TX                    (alternate 7).
+ * PD2  - LCD_CS                    (output pushpull maximum).
+ * PD3  - USART2_CTS                (alternate 7).
+ * PD4  - USART2_RST                (alternate 7).
+ * PD5  - USART2_TX                 (alternate 7).
+ * PD6  - USART2_RX                 (alternate 7).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - AUDIO_RST                 (output pushpull maximum).
+ * PD12 - PIN12                     (input pullup).
+ * PD13 - PIN13                     (input pullup).
+ * PD14 - PIN14                     (input pullup).
+ * PD15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_ALTERNATE(GPIOD_CAN_RX) |     \
+                                     PIN_MODE_ALTERNATE(GPIOD_CAN_TX) |     \
+                                     PIN_MODE_OUTPUT(GPIOD_LCD_CS) |        \
+                                     PIN_MODE_ALTERNATE(GPIOD_USART2_CTS) | \
+                                     PIN_MODE_ALTERNATE(GPIOD_USART2_RST) | \
+                                     PIN_MODE_ALTERNATE(GPIOD_USART2_TX) |  \
+                                     PIN_MODE_ALTERNATE(GPIOD_USART2_RX) |  \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_AUDIO_RST) |     \
+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_CAN_RX) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_CAN_TX) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LCD_CS) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART2_CTS) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART2_RST) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART2_TX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART2_RX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_AUDIO_RST) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_100M(GPIOD_CAN_RX) |        \
+                                     PIN_OSPEED_100M(GPIOD_CAN_TX) |        \
+                                     PIN_OSPEED_100M(GPIOD_LCD_CS) |        \
+                                     PIN_OSPEED_100M(GPIOD_USART2_CTS) |    \
+                                     PIN_OSPEED_100M(GPIOD_USART2_RST) |    \
+                                     PIN_OSPEED_100M(GPIOD_USART2_TX) |     \
+                                     PIN_OSPEED_100M(GPIOD_USART2_RX) |     \
+                                     PIN_OSPEED_2M(GPIOD_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN10) |           \
+                                     PIN_OSPEED_100M(GPIOD_AUDIO_RST) |     \
+                                     PIN_OSPEED_2M(GPIOD_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_FLOATING(GPIOD_CAN_RX) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_CAN_TX) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_LCD_CS) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_USART2_CTS) | \
+                                     PIN_PUPDR_FLOATING(GPIOD_USART2_RST) | \
+                                     PIN_PUPDR_FLOATING(GPIOD_USART2_TX) |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_USART2_RX) |  \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_FLOATING(GPIOD_AUDIO_RST) |  \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_CAN_RX) |           \
+                                     PIN_ODR_HIGH(GPIOD_CAN_TX) |           \
+                                     PIN_ODR_HIGH(GPIOD_LCD_CS) |           \
+                                     PIN_ODR_HIGH(GPIOD_USART2_CTS) |       \
+                                     PIN_ODR_HIGH(GPIOD_USART2_RST) |       \
+                                     PIN_ODR_HIGH(GPIOD_USART2_TX) |        \
+                                     PIN_ODR_HIGH(GPIOD_USART2_RX) |        \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_LOW(GPIOD_AUDIO_RST) |         \
+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_CAN_RX, 7) |         \
+                                     PIN_AFIO_AF(GPIOD_CAN_TX, 7) |         \
+                                     PIN_AFIO_AF(GPIOD_LCD_CS, 0) |         \
+                                     PIN_AFIO_AF(GPIOD_USART2_CTS, 7) |     \
+                                     PIN_AFIO_AF(GPIOD_USART2_RST, 7) |     \
+                                     PIN_AFIO_AF(GPIOD_USART2_TX, 7) |      \
+                                     PIN_AFIO_AF(GPIOD_USART2_RX, 7) |      \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_AUDIO_RST, 0) |      \
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0  - PIN0                      (input pullup).
+ * PE1  - PIN1                      (input pullup).
+ * PE2  - SD_CS                     (output opendrain maximum).
+ * PE3  - SD_DETECT                 (input pullup).
+ * PE4  - PIN4                      (input pullup).
+ * PE5  - PIN5                      (input pullup).
+ * PE6  - JOY_SEL                   (input pulldown).
+ * PE7  - RTD_IN                    (analog).
+ * PE8  - PRESSUREP                 (analog).
+ * PE9  - PRESSUREN                 (analog).
+ * PE10 - PIN10                     (input pullup).
+ * PE11 - PIN11                     (input pullup).
+ * PE12 - PIN12                     (input pullup).
+ * PE13 - PIN13                     (input pullup).
+ * PE14 - PRESSURE_TEPM             (input floating).
+ * PE15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN1) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_SD_CS) |         \
+                                     PIN_MODE_INPUT(GPIOE_SD_DETECT) |      \
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOE_JOY_SEL) |        \
+                                     PIN_MODE_ANALOG(GPIOE_RTD_IN) |        \
+                                     PIN_MODE_ANALOG(GPIOE_PRESSUREP) |     \
+                                     PIN_MODE_ANALOG(GPIOE_PRESSUREN) |     \
+                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOE_PRESSURE_TEPM) |  \
+                                     PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOE_SD_CS) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_SD_DETECT) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_JOY_SEL) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_RTD_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PRESSUREP) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PRESSUREN) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PRESSURE_TEPM) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_2M(GPIOE_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOE_PIN1) |            \
+                                     PIN_OSPEED_100M(GPIOE_SD_CS) |         \
+                                     PIN_OSPEED_100M(GPIOE_SD_DETECT) |     \
+                                     PIN_OSPEED_2M(GPIOE_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOE_PIN5) |            \
+                                     PIN_OSPEED_100M(GPIOE_JOY_SEL) |       \
+                                     PIN_OSPEED_2M(GPIOE_RTD_IN) |          \
+                                     PIN_OSPEED_100M(GPIOE_PRESSUREP) |     \
+                                     PIN_OSPEED_100M(GPIOE_PRESSUREN) |     \
+                                     PIN_OSPEED_2M(GPIOE_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOE_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOE_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOE_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOE_PRESSURE_TEPM) |   \
+                                     PIN_OSPEED_2M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_PULLUP(GPIOE_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN1) |         \
+                                     PIN_PUPDR_FLOATING(GPIOE_SD_CS) |      \
+                                     PIN_PUPDR_PULLUP(GPIOE_SD_DETECT) |    \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \
+                                     PIN_PUPDR_PULLDOWN(GPIOE_JOY_SEL) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_RTD_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_PRESSUREP) |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PRESSUREN) |  \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN13) |        \
+                                     PIN_PUPDR_FLOATING(GPIOE_PRESSURE_TEPM) |\
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOE_SD_CS) |            \
+                                     PIN_ODR_HIGH(GPIOE_SD_DETECT) |        \
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOE_JOY_SEL) |          \
+                                     PIN_ODR_HIGH(GPIOE_RTD_IN) |           \
+                                     PIN_ODR_HIGH(GPIOE_PRESSUREP) |        \
+                                     PIN_ODR_HIGH(GPIOE_PRESSUREN) |        \
+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \
+                                     PIN_ODR_LOW(GPIOE_PIN13) |             \
+                                     PIN_ODR_LOW(GPIOE_PRESSURE_TEPM) |     \
+                                     PIN_ODR_LOW(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_SD_CS, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_SD_DETECT, 0) |      \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_JOY_SEL, 0) |        \
+                                     PIN_AFIO_AF(GPIOE_RTD_IN, 0))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PRESSUREP, 0) |      \
+                                     PIN_AFIO_AF(GPIOE_PRESSUREN, 0) |      \
+                                     PIN_AFIO_AF(GPIOE_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PRESSURE_TEPM, 0) |  \
+                                     PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0  - OSC_IN                    (input floating).
+ * PF1  - OSC_OUT                   (input floating).
+ * PF2  - JOY_DOWN                  (input pulldown).
+ * PF3  - PIN3                      (input pullup).
+ * PF4  - JOY_LEFT                  (input pulldown).
+ * PF5  - PIN5                      (input pullup).
+ * PF6  - PIN6                      (input pullup).
+ * PF7  - PIN7                      (input pullup).
+ * PF8  - PIN8                      (input pullup).
+ * PF9  - JOY_RIGHT                 (input pulldown).
+ * PF10 - JOY_UP                    (input pulldown).
+ * PF11 - PIN11                     (input pullup).
+ * PF12 - PIN12                     (input pullup).
+ * PF13 - PIN13                     (input pullup).
+ * PF14 - PIN14                     (input pullup).
+ * PF15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOF_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOF_JOY_DOWN) |       \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_JOY_LEFT) |       \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_JOY_RIGHT) |      \
+                                     PIN_MODE_INPUT(GPIOF_JOY_UP) |         \
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_JOY_DOWN) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_JOY_LEFT) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_JOY_RIGHT) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_JOY_UP) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_100M(GPIOF_OSC_IN) |        \
+                                     PIN_OSPEED_100M(GPIOF_OSC_OUT) |       \
+                                     PIN_OSPEED_100M(GPIOF_JOY_DOWN) |      \
+                                     PIN_OSPEED_2M(GPIOF_PIN3) |            \
+                                     PIN_OSPEED_100M(GPIOF_JOY_LEFT) |      \
+                                     PIN_OSPEED_2M(GPIOF_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN8) |            \
+                                     PIN_OSPEED_100M(GPIOF_JOY_RIGHT) |     \
+                                     PIN_OSPEED_100M(GPIOF_JOY_UP) |        \
+                                     PIN_OSPEED_2M(GPIOF_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) |    \
+                                     PIN_PUPDR_PULLDOWN(GPIOF_JOY_DOWN) |   \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \
+                                     PIN_PUPDR_PULLDOWN(GPIOF_JOY_LEFT) |   \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \
+                                     PIN_PUPDR_PULLDOWN(GPIOF_JOY_RIGHT) |  \
+                                     PIN_PUPDR_PULLDOWN(GPIOF_JOY_UP) |     \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOF_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOF_JOY_DOWN) |         \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_JOY_LEFT) |         \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_JOY_RIGHT) |        \
+                                     PIN_ODR_HIGH(GPIOF_JOY_UP) |           \
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOF_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOF_JOY_DOWN, 0) |       \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_JOY_LEFT, 0) |       \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_JOY_RIGHT, 0) |      \
+                                     PIN_AFIO_AF(GPIOF_JOY_UP, 0) |         \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.mk b/os/hal/boards/ST_STM32373C_EVAL/board.mk
new file mode 100644
index 000000000..271a37fd1
--- /dev/null
+++ b/os/hal/boards/ST_STM32373C_EVAL/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32373C_EVAL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32373C_EVAL
diff --git a/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg b/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg
new file mode 100644
index 000000000..85f428ef8
--- /dev/null
+++ b/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg
@@ -0,0 +1,798 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F3xx board Template -->
+<board
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f3xx_board.xsd">
+  <configuration_settings>
+  	<templates_path>resources/gencfg/processors/boards/stm32f3xx/templates</templates_path>
+  	<output_path>..</output_path>
+  </configuration_settings>
+  <board_name>STMicroelectronics STM32373C-EVAL</board_name>
+  <board_id>ST_STM32373C_EVAL</board_id>
+  <board_functions></board_functions>
+  <subtype>STM32F37X</subtype>
+  <clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="32768"
+  	LSEBypass="false" LSEDrive="3 High Drive (default)" />
+  <ports>
+    <GPIOA>
+      <pin0
+        ID="WKUP_BUTTON"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="LDR_OUT"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Analog"
+        Alternate="0" />
+      <pin2
+        ID="KEY_BUTTON"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin2>
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="5" ></pin5>
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID="COMP2_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin8
+        ID="I2C2_SMB"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID="I2C2_SCL"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin10
+        ID="I2C2_SDA"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="4" ></pin10>
+      <pin11
+        ID="USB_DM"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin12
+        ID="USB_DP"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" ></pin12>
+      <pin13
+        ID="SWDIO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin14
+        ID="SWCLK"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin15
+        ID="JTDI"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+    </GPIOA>
+    <GPIOB>
+      <pin0
+        ID="MIC_IN"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Analog"
+        Alternate="0" />
+      <pin1
+        ID="ADC_POT_IN"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Analog"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="SWO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin4
+        ID="JTRST"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin5>
+      <pin6
+        ID="I2C1_SCL"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin7
+        ID="I2C1_SDA"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOB>
+    <GPIOC>
+      <pin0
+        ID="LED1"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin1
+        ID="LED2"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin2
+        ID="LED3"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin3
+        ID="LED4"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" ></pin3>
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID="USB_DISCONNECT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID="SPI3_SCK"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin11
+        ID="SPI3_MISO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin12
+        ID="SPI3_MOSI"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID="OSC32_IN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID="OSC32_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOC>
+    <GPIOD>
+      <pin0
+        ID="CAN_RX"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin1
+        ID="CAN_TX"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin2
+        ID="LCD_CS"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin3
+        ID="USART2_CTS"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="7" ></pin3>
+      <pin4
+        ID="USART2_RST"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin5
+        ID="USART2_TX"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin6
+        ID="USART2_RX"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID="AUDIO_RST"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOD>
+    <GPIOE>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID="SD_CS"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" ></pin2>
+      <pin3
+        ID="SD_DETECT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin3>
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin5>
+      <pin6
+        ID="JOY_SEL"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID="RTD_IN"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Analog"
+        Alternate="0" />
+      <pin8
+        ID="PRESSUREP"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Analog"
+        Alternate="0" />
+      <pin9
+        ID="PRESSUREN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Analog"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin10>
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="Low"
+        Mode="Input"
+        Alternate="0" ></pin13>
+      <pin14
+        ID="PRESSURE_TEPM"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="Low"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOE>
+    <GPIOF>
+      <pin0
+        ID="OSC_IN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="OSC_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin1>
+      <pin2
+        ID="JOY_DOWN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin3>
+      <pin4
+        ID="JOY_LEFT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID="JOY_RIGHT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID="JOY_UP"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOF>
+  </ports>
+</board>
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.c b/os/hal/boards/ST_STM32F0_DISCOVERY/board.c
new file mode 100644
index 000000000..baeb359e2
--- /dev/null
+++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.c
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH}
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.h b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h
new file mode 100644
index 000000000..578aa49b7
--- /dev/null
+++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h
@@ -0,0 +1,757 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for ST STM32F0-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F0_DISCOVERY
+#define BOARD_NAME                  "ST STM32F0-Discovery"
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ * NOTE: HSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                0
+#endif
+
+#define STM32_LSEDRV                (3 << 3)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                0
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F0XX_MD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON                0
+#define GPIOA_PIN1                  1
+#define GPIOA_PIN2                  2
+#define GPIOA_PIN3                  3
+#define GPIOA_PIN4                  4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_PIN7                  7
+#define GPIOA_PIN8                  8
+#define GPIOA_PIN9                  9
+#define GPIOA_PIN10                 10
+#define GPIOA_PIN11                 11
+#define GPIOA_PIN12                 12
+#define GPIOA_SWDAT                 13
+#define GPIOA_SWCLK                 14
+#define GPIOA_PIN15                 15
+
+#define GPIOB_PIN0                  0
+#define GPIOB_PIN1                  1
+#define GPIOB_PIN2                  2
+#define GPIOB_PIN3                  3
+#define GPIOB_PIN4                  4
+#define GPIOB_PIN5                  5
+#define GPIOB_PIN6                  6
+#define GPIOB_PIN7                  7
+#define GPIOB_PIN8                  8
+#define GPIOB_PIN9                  9
+#define GPIOB_PIN10                 10
+#define GPIOB_PIN11                 11
+#define GPIOB_PIN12                 12
+#define GPIOB_PIN13                 13
+#define GPIOB_PIN14                 14
+#define GPIOB_PIN15                 15
+
+#define GPIOC_PIN0                  0
+#define GPIOC_PIN1                  1
+#define GPIOC_PIN2                  2
+#define GPIOC_PIN3                  3
+#define GPIOC_PIN4                  4
+#define GPIOC_PIN5                  5
+#define GPIOC_PIN6                  6
+#define GPIOC_PIN7                  7
+#define GPIOC_LED4                  8
+#define GPIOC_LED3                  9
+#define GPIOC_PIN10                 10
+#define GPIOC_PIN11                 11
+#define GPIOC_PIN12                 12
+#define GPIOC_PIN13                 13
+#define GPIOC_OSC32_IN              14
+#define GPIOC_OSC32_OUT             15
+
+#define GPIOD_PIN0                  0
+#define GPIOD_PIN1                  1
+#define GPIOD_PIN2                  2
+#define GPIOD_PIN3                  3
+#define GPIOD_PIN4                  4
+#define GPIOD_PIN5                  5
+#define GPIOD_PIN6                  6
+#define GPIOD_PIN7                  7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_PIN11                 11
+#define GPIOD_PIN12                 12
+#define GPIOD_PIN13                 13
+#define GPIOD_PIN14                 14
+#define GPIOD_PIN15                 15
+
+#define GPIOF_OSC_IN                0
+#define GPIOF_OSC_OUT               1
+#define GPIOF_PIN2                  2
+#define GPIOF_PIN3                  3
+#define GPIOF_PIN4                  4
+#define GPIOF_PIN5                  5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_PIN9                  9
+#define GPIOF_PIN10                 10
+#define GPIOF_PIN11                 11
+#define GPIOF_PIN12                 12
+#define GPIOF_PIN13                 13
+#define GPIOF_PIN14                 14
+#define GPIOF_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_10M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_40M(n)           (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - BUTTON                    (input floating).
+ * PA1  - PIN1                      (input pullup).
+ * PA2  - PIN2                      (input pullup).
+ * PA3  - PIN3                      (input pullup).
+ * PA4  - PIN4                      (input pullup).
+ * PA5  - PIN5                      (input pullup).
+ * PA6  - PIN6                      (input pullup).
+ * PA7  - PIN7                      (input pullup).
+ * PA8  - PIN8                      (input pullup).
+ * PA9  - PIN9                      (input pullup).
+ * PA10 - PIN10                     (input pullup).
+ * PA11 - PIN11                     (input pullup).
+ * PA12 - PIN12                     (input pullup).
+ * PA13 - SWDAT                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_BUTTON) |         \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOA_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOA_PIN12) |          \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDAT) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
+                                     PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDAT) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_2M(GPIOA_BUTTON) |          \
+                                     PIN_OSPEED_2M(GPIOA_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOA_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOA_PIN12) |           \
+                                     PIN_OSPEED_40M(GPIOA_SWDAT) |          \
+                                     PIN_OSPEED_40M(GPIOA_SWCLK) |          \
+                                     PIN_OSPEED_40M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_BUTTON) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_SWDAT) |        \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_BUTTON) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWDAT) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_BUTTON, 0) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN7, 0))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_SWDAT, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - PIN0                      (input pullup).
+ * PB1  - PIN1                      (input pullup).
+ * PB2  - PIN2                      (input pullup).
+ * PB3  - PIN3                      (input pullup).
+ * PB4  - PIN4                      (input pullup).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - PIN6                      (input pullup).
+ * PB7  - PIN7                      (input pullup).
+ * PB8  - PIN8                      (input pullup).
+ * PB9  - PIN9                      (input pullup).
+ * PB10 - PIN10                     (input pullup).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - PIN13                     (input pullup).
+ * PB14 - PIN14                     (input pullup).
+ * PB15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_2M(GPIOB_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN1) |            \
+                                     PIN_OSPEED_40M(GPIOB_PIN2) |           \
+                                     PIN_OSPEED_40M(GPIOB_PIN3) |           \
+                                     PIN_OSPEED_40M(GPIOB_PIN4) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - PIN0                      (input pullup).
+ * PC1  - PIN1                      (input pullup).
+ * PC2  - PIN2                      (input pullup).
+ * PC3  - PIN3                      (input pullup).
+ * PC4  - PIN4                      (input pullup).
+ * PC5  - PIN5                      (input pullup).
+ * PC6  - PIN6                      (input pullup).
+ * PC7  - PIN7                      (input pullup).
+ * PC8  - LED4                      (output pushpull maximum).
+ * PC9  - LED3                      (output pushpull maximum).
+ * PC10 - PIN10                     (input pullup).
+ * PC11 - PIN11                     (input pullup).
+ * PC12 - PIN12                     (input pullup).
+ * PC13 - PIN13                     (input pullup).
+ * PC14 - OSC32_IN                  (input floating).
+ * PC15 - OSC32_OUT                 (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \
+                                     PIN_MODE_OUTPUT(GPIOC_LED4) |          \
+                                     PIN_MODE_OUTPUT(GPIOC_LED3) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_LED4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_LED3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_2M(GPIOC_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN7) |            \
+                                     PIN_OSPEED_40M(GPIOC_LED4) |           \
+                                     PIN_OSPEED_40M(GPIOC_LED3) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN13) |           \
+                                     PIN_OSPEED_40M(GPIOC_OSC32_IN) |       \
+                                     PIN_OSPEED_40M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_LED4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_LED3) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \
+                                     PIN_ODR_LOW(GPIOC_LED4) |              \
+                                     PIN_ODR_LOW(GPIOC_LED3) |              \
+                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_LED4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_LED3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0) |       \
+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - PIN2                      (input pullup).
+ * PD3  - PIN3                      (input pullup).
+ * PD4  - PIN4                      (input pullup).
+ * PD5  - PIN5                      (input pullup).
+ * PD6  - PIN6                      (input pullup).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - PIN12                     (input pullup).
+ * PD13 - PIN13                     (input pullup).
+ * PD14 - PIN14                     (input pullup).
+ * PD15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_2M(GPIOD_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0  - OSC_IN                    (input floating).
+ * PF1  - OSC_OUT                   (input floating).
+ * PF2  - PIN2                      (input pullup).
+ * PF3  - PIN3                      (input pullup).
+ * PF4  - PIN4                      (input pullup).
+ * PF5  - PIN5                      (input pullup).
+ * PF6  - PIN6                      (input pullup).
+ * PF7  - PIN7                      (input pullup).
+ * PF8  - PIN8                      (input pullup).
+ * PF9  - PIN9                      (input pullup).
+ * PF10 - PIN10                     (input pullup).
+ * PF11 - PIN11                     (input pullup).
+ * PF12 - PIN12                     (input pullup).
+ * PF13 - PIN13                     (input pullup).
+ * PF14 - PIN14                     (input pullup).
+ * PF15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOF_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_2M(GPIOF_OSC_IN) |          \
+                                     PIN_OSPEED_2M(GPIOF_OSC_OUT) |         \
+                                     PIN_OSPEED_2M(GPIOF_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) |    \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOF_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOF_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F0_DISCOVERY/board.mk
new file mode 100644
index 000000000..6e929cc70
--- /dev/null
+++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F0_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F0_DISCOVERY
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg
new file mode 100644
index 000000000..ec85130c7
--- /dev/null
+++ b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg
@@ -0,0 +1,668 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F0xx board Template -->
+<board
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f0xx_board.xsd">
+  <configuration_settings>
+    <templates_path>resources/gencfg/processors/boards/stm32f0xx/templates</templates_path>
+    <output_path>..</output_path>
+  </configuration_settings>
+  <board_name>ST STM32F0-Discovery</board_name>
+  <board_id>ST_STM32F0_DISCOVERY</board_id>
+  <board_functions></board_functions>
+  <subtype>STM32F0XX_MD</subtype>
+  <clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0"
+  	LSEBypass="false" LSEDrive="3 High Drive (default)" />
+  <ports>
+    <GPIOA>
+      <pin0
+        ID="BUTTON"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID="SWDAT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin14
+        ID="SWCLK"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOA>
+    <GPIOB>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOB>
+    <GPIOC>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID="LED4"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin9
+        ID="LED3"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID="OSC32_IN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID="OSC32_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOC>
+    <GPIOD>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOD>
+    <GPIOF>
+      <pin0
+        ID="OSC_IN"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="OSC_OUT"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOF>
+  </ports>
+</board>
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/board.c b/os/hal/boards/ST_STM32F3_DISCOVERY/board.c
new file mode 100644
index 000000000..19756cca7
--- /dev/null
+++ b/os/hal/boards/ST_STM32F3_DISCOVERY/board.c
@@ -0,0 +1,101 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH}
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/board.h b/os/hal/boards/ST_STM32F3_DISCOVERY/board.h
new file mode 100644
index 000000000..147dfb9b1
--- /dev/null
+++ b/os/hal/boards/ST_STM32F3_DISCOVERY/board.h
@@ -0,0 +1,891 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F3-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F3_DISCOVERY
+#define BOARD_NAME                  "STMicroelectronics STM32F3-Discovery"
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                0
+#endif
+
+#define STM32_LSEDRV                (3 << 3)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                8000000
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F30X
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON                0
+#define GPIOA_PIN1                  1
+#define GPIOA_PIN2                  2
+#define GPIOA_PIN3                  3
+#define GPIOA_PIN4                  4
+#define GPIOA_SPI1_SCK              5
+#define GPIOA_SPI1_MISO             6
+#define GPIOA_SPI1_MOSI             7
+#define GPIOA_PIN8                  8
+#define GPIOA_PIN9                  9
+#define GPIOA_PIN10                 10
+#define GPIOA_USB_DM                11
+#define GPIOA_USB_DP                12
+#define GPIOA_SWDIO                 13
+#define GPIOA_SWCLK                 14
+#define GPIOA_PIN15                 15
+
+#define GPIOB_PIN0                  0
+#define GPIOB_PIN1                  1
+#define GPIOB_PIN2                  2
+#define GPIOB_SWO                   3
+#define GPIOB_PIN4                  4
+#define GPIOB_PIN5                  5
+#define GPIOB_I2C1_SCL              6
+#define GPIOB_I2C1_SDA              7
+#define GPIOB_PIN8                  8
+#define GPIOB_PIN9                  9
+#define GPIOB_PIN10                 10
+#define GPIOB_PIN11                 11
+#define GPIOB_PIN12                 12
+#define GPIOB_PIN13                 13
+#define GPIOB_PIN14                 14
+#define GPIOB_PIN15                 15
+
+#define GPIOC_PIN0                  0
+#define GPIOC_PIN1                  1
+#define GPIOC_PIN2                  2
+#define GPIOC_PIN3                  3
+#define GPIOC_PIN4                  4
+#define GPIOC_PIN5                  5
+#define GPIOC_PIN6                  6
+#define GPIOC_PIN7                  7
+#define GPIOC_PIN8                  8
+#define GPIOC_PIN9                  9
+#define GPIOC_PIN10                 10
+#define GPIOC_PIN11                 11
+#define GPIOC_PIN12                 12
+#define GPIOC_PIN13                 13
+#define GPIOC_OSC32_IN              14
+#define GPIOC_OSC32_OUT             15
+
+#define GPIOD_PIN0                  0
+#define GPIOD_PIN1                  1
+#define GPIOD_PIN2                  2
+#define GPIOD_PIN3                  3
+#define GPIOD_PIN4                  4
+#define GPIOD_PIN5                  5
+#define GPIOD_PIN6                  6
+#define GPIOD_PIN7                  7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_PIN11                 11
+#define GPIOD_PIN12                 12
+#define GPIOD_PIN13                 13
+#define GPIOD_PIN14                 14
+#define GPIOD_PIN15                 15
+
+#define GPIOE_L3GD20_INT1           0
+#define GPIOE_L3GD20_INT2           1
+#define GPIOE_LSM303_DRDY           2
+#define GPIOE_SPI1_CS               3
+#define GPIOE_LSM303_INT1           4
+#define GPIOE_LSM303_INT2           5
+#define GPIOE_PIN6                  6
+#define GPIOE_PIN7                  7
+#define GPIOE_LED4_BLUE             8
+#define GPIOE_LED3_RED              9
+#define GPIOE_LED5_ORANGE           10
+#define GPIOE_LED7_GREEN            11
+#define GPIOE_LED9_BLUE             12
+#define GPIOE_LED10_RED             13
+#define GPIOE_LED8_ORANGE           14
+#define GPIOE_LED6_GREEN            15
+
+#define GPIOF_OSC_IN                0
+#define GPIOF_OSC_OUT               1
+#define GPIOF_PIN2                  2
+#define GPIOF_PIN3                  3
+#define GPIOF_PIN4                  4
+#define GPIOF_PIN5                  5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_PIN9                  9
+#define GPIOF_PIN10                 10
+#define GPIOF_PIN11                 11
+#define GPIOF_PIN12                 12
+#define GPIOF_PIN13                 13
+#define GPIOF_PIN14                 14
+#define GPIOF_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - BUTTON                    (input floating).
+ * PA1  - PIN1                      (input pullup).
+ * PA2  - PIN2                      (input pullup).
+ * PA3  - PIN3                      (input pullup).
+ * PA4  - PIN4                      (input pullup).
+ * PA5  - SPI1_SCK                  (alternate 5).
+ * PA6  - SPI1_MISO                 (alternate 5).
+ * PA7  - SPI1_MOSI                 (alternate 5).
+ * PA8  - PIN8                      (input pullup).
+ * PA9  - PIN9                      (input pullup).
+ * PA10 - PIN10                     (input pullup).
+ * PA11 - USB_DM                    (alternate 14).
+ * PA12 - USB_DP                    (alternate 14).
+ * PA13 - SWDIO                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_BUTTON) |         \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) |   \
+                                     PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) |  \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
+                                     PIN_MODE_ALTERNATE(GPIOA_USB_DM) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_USB_DP) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
+                                     PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_2M(GPIOA_BUTTON) |          \
+                                     PIN_OSPEED_2M(GPIOA_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN4) |            \
+                                     PIN_OSPEED_100M(GPIOA_SPI1_SCK) |      \
+                                     PIN_OSPEED_100M(GPIOA_SPI1_MISO) |     \
+                                     PIN_OSPEED_100M(GPIOA_SPI1_MOSI) |     \
+                                     PIN_OSPEED_2M(GPIOA_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN10) |           \
+                                     PIN_OSPEED_100M(GPIOA_USB_DM) |        \
+                                     PIN_OSPEED_2M(GPIOA_USB_DP) |          \
+                                     PIN_OSPEED_100M(GPIOA_SWDIO) |         \
+                                     PIN_OSPEED_100M(GPIOA_SWCLK) |         \
+                                     PIN_OSPEED_2M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_BUTTON) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_SPI1_SCK) |   \
+                                     PIN_PUPDR_PULLUP(GPIOA_SPI1_MISO) |    \
+                                     PIN_PUPDR_FLOATING(GPIOA_SPI1_MOSI) |  \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |        \
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DM) |     \
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DP) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_SWDIO) |        \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_BUTTON) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_SPI1_SCK) |         \
+                                     PIN_ODR_HIGH(GPIOA_SPI1_MISO) |        \
+                                     PIN_ODR_HIGH(GPIOA_SPI1_MOSI) |        \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOA_USB_DM) |           \
+                                     PIN_ODR_HIGH(GPIOA_USB_DP) |           \
+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_BUTTON, 0) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_SPI1_SCK, 5) |       \
+                                     PIN_AFIO_AF(GPIOA_SPI1_MISO, 5) |      \
+                                     PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_USB_DM, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_USB_DP, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - PIN0                      (input pullup).
+ * PB1  - PIN1                      (input pullup).
+ * PB2  - PIN2                      (input pullup).
+ * PB3  - SWO                       (alternate 0).
+ * PB4  - PIN4                      (input pullup).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - I2C1_SCL                  (alternate 4).
+ * PB7  - I2C1_SDA                  (alternate 4).
+ * PB8  - PIN8                      (input pullup).
+ * PB9  - PIN9                      (input pullup).
+ * PB10 - PIN10                     (input pullup).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - PIN13                     (input pullup).
+ * PB14 - PIN14                     (input pullup).
+ * PB15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SWO) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) |   \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SWO) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) |  \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_2M(GPIOB_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN2) |            \
+                                     PIN_OSPEED_100M(GPIOB_SWO) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN5) |            \
+                                     PIN_OSPEED_100M(GPIOB_I2C1_SCL) |      \
+                                     PIN_OSPEED_100M(GPIOB_I2C1_SDA) |      \
+                                     PIN_OSPEED_2M(GPIOB_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_SWO) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) |   \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_SWO) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_I2C1_SCL) |         \
+                                     PIN_ODR_HIGH(GPIOB_I2C1_SDA) |         \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SWO, 0) |            \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) |       \
+                                     PIN_AFIO_AF(GPIOB_I2C1_SDA, 4))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - PIN0                      (input pullup).
+ * PC1  - PIN1                      (input pullup).
+ * PC2  - PIN2                      (input pullup).
+ * PC3  - PIN3                      (input pullup).
+ * PC4  - PIN4                      (input pullup).
+ * PC5  - PIN5                      (input pullup).
+ * PC6  - PIN6                      (input pullup).
+ * PC7  - PIN7                      (input pullup).
+ * PC8  - PIN8                      (input pullup).
+ * PC9  - PIN9                      (input pullup).
+ * PC10 - PIN10                     (input pullup).
+ * PC11 - PIN11                     (input pullup).
+ * PC12 - PIN12                     (input pullup).
+ * PC13 - PIN13                     (input pullup).
+ * PC14 - OSC32_IN                  (input floating).
+ * PC15 - OSC32_OUT                 (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_2M(GPIOC_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN13) |           \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_IN) |      \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0) |       \
+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - PIN2                      (input pullup).
+ * PD3  - PIN3                      (input pullup).
+ * PD4  - PIN4                      (input pullup).
+ * PD5  - PIN5                      (input pullup).
+ * PD6  - PIN6                      (input pullup).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - PIN12                     (input pullup).
+ * PD13 - PIN13                     (input pullup).
+ * PD14 - PIN14                     (input pullup).
+ * PD15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_2M(GPIOD_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0  - L3GD20_INT1               (input pullup).
+ * PE1  - L3GD20_INT2               (input pullup).
+ * PE2  - LSM303_DRDY               (input pullup).
+ * PE3  - SPI1_CS                   (output pushpull maximum).
+ * PE4  - LSM303_INT1               (input pullup).
+ * PE5  - LSM303_INT2               (input pullup).
+ * PE6  - PIN6                      (input pullup).
+ * PE7  - PIN7                      (input pullup).
+ * PE8  - LED4_BLUE                 (output pushpull maximum).
+ * PE9  - LED3_RED                  (output pushpull maximum).
+ * PE10 - LED5_ORANGE               (output pushpull maximum).
+ * PE11 - LED7_GREEN                (output pushpull maximum).
+ * PE12 - LED9_BLUE                 (output pushpull maximum).
+ * PE13 - LED10_RED                 (output pushpull maximum).
+ * PE14 - LED8_ORANGE               (output pushpull maximum).
+ * PE15 - LED6_GREEN                (output pushpull maximum).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_L3GD20_INT1) |    \
+                                     PIN_MODE_INPUT(GPIOE_L3GD20_INT2) |    \
+                                     PIN_MODE_INPUT(GPIOE_LSM303_DRDY) |    \
+                                     PIN_MODE_OUTPUT(GPIOE_SPI1_CS) |       \
+                                     PIN_MODE_INPUT(GPIOE_LSM303_INT1) |    \
+                                     PIN_MODE_INPUT(GPIOE_LSM303_INT2) |    \
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_LED4_BLUE) |     \
+                                     PIN_MODE_OUTPUT(GPIOE_LED3_RED) |      \
+                                     PIN_MODE_OUTPUT(GPIOE_LED5_ORANGE) |   \
+                                     PIN_MODE_OUTPUT(GPIOE_LED7_GREEN) |    \
+                                     PIN_MODE_OUTPUT(GPIOE_LED9_BLUE) |     \
+                                     PIN_MODE_OUTPUT(GPIOE_LED10_RED) |     \
+                                     PIN_MODE_OUTPUT(GPIOE_LED8_ORANGE) |   \
+                                     PIN_MODE_OUTPUT(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT1) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT2) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LSM303_DRDY) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOE_SPI1_CS) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LSM303_INT1) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LSM303_INT2) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED4_BLUE) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED3_RED) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED5_ORANGE) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED7_GREEN) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED9_BLUE) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED10_RED) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED8_ORANGE) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_2M(GPIOE_L3GD20_INT1) |     \
+                                     PIN_OSPEED_2M(GPIOE_L3GD20_INT2) |     \
+                                     PIN_OSPEED_2M(GPIOE_LSM303_DRDY) |     \
+                                     PIN_OSPEED_100M(GPIOE_SPI1_CS) |       \
+                                     PIN_OSPEED_2M(GPIOE_LSM303_INT1) |     \
+                                     PIN_OSPEED_2M(GPIOE_LSM303_INT2) |     \
+                                     PIN_OSPEED_2M(GPIOE_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOE_PIN7) |            \
+                                     PIN_OSPEED_100M(GPIOE_LED4_BLUE) |     \
+                                     PIN_OSPEED_100M(GPIOE_LED3_RED) |      \
+                                     PIN_OSPEED_100M(GPIOE_LED5_ORANGE) |   \
+                                     PIN_OSPEED_100M(GPIOE_LED7_GREEN) |    \
+                                     PIN_OSPEED_100M(GPIOE_LED9_BLUE) |     \
+                                     PIN_OSPEED_100M(GPIOE_LED10_RED) |     \
+                                     PIN_OSPEED_100M(GPIOE_LED8_ORANGE) |   \
+                                     PIN_OSPEED_100M(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT1) |  \
+                                     PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT2) |  \
+                                     PIN_PUPDR_PULLUP(GPIOE_LSM303_DRDY) |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_SPI1_CS) |    \
+                                     PIN_PUPDR_PULLUP(GPIOE_LSM303_INT1) |  \
+                                     PIN_PUPDR_PULLUP(GPIOE_LSM303_INT2) |  \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_LED4_BLUE) |    \
+                                     PIN_PUPDR_PULLUP(GPIOE_LED3_RED) |     \
+                                     PIN_PUPDR_PULLUP(GPIOE_LED5_ORANGE) |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_LED7_GREEN) | \
+                                     PIN_PUPDR_PULLUP(GPIOE_LED9_BLUE) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_LED10_RED) |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_LED8_ORANGE) |\
+                                     PIN_PUPDR_FLOATING(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_L3GD20_INT1) |      \
+                                     PIN_ODR_HIGH(GPIOE_L3GD20_INT2) |      \
+                                     PIN_ODR_HIGH(GPIOE_LSM303_DRDY) |      \
+                                     PIN_ODR_HIGH(GPIOE_SPI1_CS) |          \
+                                     PIN_ODR_HIGH(GPIOE_LSM303_INT1) |      \
+                                     PIN_ODR_HIGH(GPIOE_LSM303_INT2) |      \
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \
+                                     PIN_ODR_LOW(GPIOE_LED4_BLUE) |         \
+                                     PIN_ODR_LOW(GPIOE_LED3_RED) |          \
+                                     PIN_ODR_LOW(GPIOE_LED5_ORANGE) |       \
+                                     PIN_ODR_LOW(GPIOE_LED7_GREEN) |        \
+                                     PIN_ODR_LOW(GPIOE_LED9_BLUE) |         \
+                                     PIN_ODR_LOW(GPIOE_LED10_RED) |         \
+                                     PIN_ODR_LOW(GPIOE_LED8_ORANGE) |       \
+                                     PIN_ODR_LOW(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_L3GD20_INT1, 0) |    \
+                                     PIN_AFIO_AF(GPIOE_L3GD20_INT2, 0) |    \
+                                     PIN_AFIO_AF(GPIOE_LSM303_DRDY, 0) |    \
+                                     PIN_AFIO_AF(GPIOE_SPI1_CS, 0) |        \
+                                     PIN_AFIO_AF(GPIOE_LSM303_INT1, 0) |    \
+                                     PIN_AFIO_AF(GPIOE_LSM303_INT2, 0) |    \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_LED4_BLUE, 0) |      \
+                                     PIN_AFIO_AF(GPIOE_LED3_RED, 0) |       \
+                                     PIN_AFIO_AF(GPIOE_LED5_ORANGE, 0) |    \
+                                     PIN_AFIO_AF(GPIOE_LED7_GREEN, 0) |     \
+                                     PIN_AFIO_AF(GPIOE_LED9_BLUE, 0) |      \
+                                     PIN_AFIO_AF(GPIOE_LED10_RED, 0) |      \
+                                     PIN_AFIO_AF(GPIOE_LED8_ORANGE, 0) |    \
+                                     PIN_AFIO_AF(GPIOE_LED6_GREEN, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0  - OSC_IN                    (input floating).
+ * PF1  - OSC_OUT                   (input floating).
+ * PF2  - PIN2                      (input pullup).
+ * PF3  - PIN3                      (input pullup).
+ * PF4  - PIN4                      (input pullup).
+ * PF5  - PIN5                      (input pullup).
+ * PF6  - PIN6                      (input pullup).
+ * PF7  - PIN7                      (input pullup).
+ * PF8  - PIN8                      (input pullup).
+ * PF9  - PIN9                      (input pullup).
+ * PF10 - PIN10                     (input pullup).
+ * PF11 - PIN11                     (input pullup).
+ * PF12 - PIN12                     (input pullup).
+ * PF13 - PIN13                     (input pullup).
+ * PF14 - PIN14                     (input pullup).
+ * PF15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOF_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_100M(GPIOF_OSC_IN) |        \
+                                     PIN_OSPEED_100M(GPIOF_OSC_OUT) |       \
+                                     PIN_OSPEED_2M(GPIOF_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) |    \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOF_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOF_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
new file mode 100644
index 000000000..766531cee
--- /dev/null
+++ b/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F3_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F3_DISCOVERY
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg
new file mode 100644
index 000000000..cbd264d03
--- /dev/null
+++ b/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg
@@ -0,0 +1,798 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F3xx board Template -->
+<board
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f3xx_board.xsd">
+  <configuration_settings>
+  	<templates_path>resources/gencfg/processors/boards/stm32f3xx/templates</templates_path>
+  	<output_path>..</output_path>
+  </configuration_settings>
+  <board_name>STMicroelectronics STM32F3-Discovery</board_name>
+  <board_id>ST_STM32F3_DISCOVERY</board_id>
+  <board_functions></board_functions>
+  <subtype>STM32F30X</subtype>
+  <clocks HSEFrequency="8000000" HSEBypass="true" LSEFrequency="0"
+  	LSEBypass="false" LSEDrive="3 High Drive (default)" />
+  <ports>
+    <GPIOA>
+      <pin0
+        ID="BUTTON"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID="SPI1_SCK"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="5" ></pin5>
+      <pin6
+        ID="SPI1_MISO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin7
+        ID="SPI1_MOSI"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID="USB_DM"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin12
+        ID="USB_DP"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" ></pin12>
+      <pin13
+        ID="SWDIO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin14
+        ID="SWCLK"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOA>
+    <GPIOB>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="SWO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin5>
+      <pin6
+        ID="I2C1_SCL"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin7
+        ID="I2C1_SDA"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOB>
+    <GPIOC>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID="OSC32_IN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID="OSC32_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOC>
+    <GPIOD>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOD>
+    <GPIOE>
+      <pin0
+        ID="L3GD20_INT1"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="L3GD20_INT2"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID="LSM303_DRDY"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="SPI1_CS"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" ></pin3>
+      <pin4
+        ID="LSM303_INT1"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID="LSM303_INT2"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID="LED4_BLUE"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin9
+        ID="LED3_RED"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin10
+        ID="LED5_ORANGE"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin11
+        ID="LED7_GREEN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin12
+        ID="LED9_BLUE"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin13
+        ID="LED10_RED"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" ></pin13>
+      <pin14
+        ID="LED8_ORANGE"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin15
+        ID="LED6_GREEN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+    </GPIOE>
+    <GPIOF>
+      <pin0
+        ID="OSC_IN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="OSC_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin1>
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin3>
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOF>
+  </ports>
+</board>
diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c
new file mode 100644
index 000000000..c76d97d55
--- /dev/null
+++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c
@@ -0,0 +1,107 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h
new file mode 100644
index 000000000..cde9cdf82
--- /dev/null
+++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h
@@ -0,0 +1,1296 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F429I-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F429I_DISCOVERY
+#define BOARD_NAME                  "STMicroelectronics STM32F429I-Discovery"
+
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                0
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                8000000
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   300
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F429_439xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON                0
+#define GPIOA_MEMS_INT1             1
+#define GPIOA_MEMS_INT2             2
+#define GPIOA_LCD_B5                3
+#define GPIOA_LCD_VSYNC             4
+#define GPIOA_PIN5                  5
+#define GPIOA_LCD_G2                6
+#define GPIOA_ACP_RST               7
+#define GPIOA_I2C3_SCL              8
+#define GPIOA_PIN9                  9
+#define GPIOA_PIN10                 10
+#define GPIOA_LCD_R4                11
+#define GPIOA_LCD_R5                12
+#define GPIOA_SWDIO                 13
+#define GPIOA_SWCLK                 14
+#define GPIOA_TP_INT                15
+
+#define GPIOB_LCD_R3                0
+#define GPIOB_LCD_R6                1
+#define GPIOB_BOOT1                 2
+#define GPIOB_SWO                   3
+#define GPIOB_PIN4                  4
+#define GPIOB_FMC_SDCKE1            5
+#define GPIOB_FMC_SDNE1             6
+#define GPIOB_PIN7                  7
+#define GPIOB_LCD_B6                8
+#define GPIOB_LCD_B7                9
+#define GPIOB_LCD_G4                10
+#define GPIOB_LCD_G5                11
+#define GPIOB_OTG_HS_ID             12
+#define GPIOB_OTG_HS_VBUS           13
+#define GPIOB_OTG_HS_DM             14
+#define GPIOB_OTG_HS_DP             15
+
+#define GPIOC_FMC_SDNWE             0
+#define GPIOC_SPI5_MEMS_CS          1
+#define GPIOC_SPI5_LCD_CS           2
+#define GPIOC_PIN3                  3
+#define GPIOC_OTG_HS_PSO            4
+#define GPIOC_OTG_HS_OC             5
+#define GPIOC_LCD_HSYNC             6
+#define GPIOC_LCD_G6                7
+#define GPIOC_PIN8                  8
+#define GPIOC_I2C3_SDA              9
+#define GPIOC_LCD_R2                10
+#define GPIOC_PIN11                 11
+#define GPIOC_PIN12                 12
+#define GPIOC_PIN13                 13
+#define GPIOC_OSC32_IN              14
+#define GPIOC_OSC32_OUT             15
+
+#define GPIOD_FMC_D2                0
+#define GPIOD_FMC_D3                1
+#define GPIOD_PIN2                  2
+#define GPIOD_LCD_G7                3
+#define GPIOD_PIN4                  4
+#define GPIOD_PIN5                  5
+#define GPIOD_LCD_B2                6
+#define GPIOD_PIN7                  7
+#define GPIOD_FMC_D13               8
+#define GPIOD_FMC_D14               9
+#define GPIOD_FMC_D15               10
+#define GPIOD_LCD_TE                11
+#define GPIOD_LCD_RDX               12
+#define GPIOD_LCD_WRX               13
+#define GPIOD_FMC_D0                14
+#define GPIOD_FMC_D1                15
+
+#define GPIOE_FMC_NBL0              0
+#define GPIOE_FMC_NBL1              1
+#define GPIOE_PIN2                  2
+#define GPIOE_PIN3                  3
+#define GPIOE_PIN4                  4
+#define GPIOE_PIN5                  5
+#define GPIOE_PIN6                  6
+#define GPIOE_FMC_D4                7
+#define GPIOE_FMC_D5                8
+#define GPIOE_FMC_D6                9
+#define GPIOE_FMC_D7                10
+#define GPIOE_FMC_D8                11
+#define GPIOE_FMC_D9                12
+#define GPIOE_FMC_D10               13
+#define GPIOE_FMC_D11               14
+#define GPIOE_FMC_D12               15
+
+#define GPIOF_FMC_A0                0
+#define GPIOF_FMC_A1                1
+#define GPIOF_FMC_A2                2
+#define GPIOF_FMC_A3                3
+#define GPIOF_FMC_A4                4
+#define GPIOF_FMC_A5                5
+#define GPIOF_PIN6                  6
+#define GPIOF_LCD_DCX               7
+#define GPIOF_SPI5_MISO             8
+#define GPIOF_SPI5_MOSI             9
+#define GPIOF_LCD_DE                10
+#define GPIOF_FMC_SDNRAS            11
+#define GPIOF_FMC_A6                12
+#define GPIOF_FMC_A7                13
+#define GPIOF_FMC_A8                14
+#define GPIOF_FMC_A9                15
+
+#define GPIOG_FMC_A10               0
+#define GPIOG_FMC_A11               1
+#define GPIOG_PIN2                  2
+#define GPIOG_PIN3                  3
+#define GPIOG_FMC_BA0               4
+#define GPIOG_FMC_BA1               5
+#define GPIOG_LCD_R7                6
+#define GPIOG_LCD_CLK               7
+#define GPIOG_FMC_SDCLK             8
+#define GPIOG_PIN9                  9
+#define GPIOG_LCD_G3                10
+#define GPIOG_LCD_B3                11
+#define GPIOG_LCD_B4                12
+#define GPIOG_LED3_GREEN            13
+#define GPIOG_LED4_RED              14
+#define GPIOG_FMC_SDNCAS            15
+
+#define GPIOH_OSC_IN                0
+#define GPIOH_OSC_OUT               1
+#define GPIOH_PIN2                  2
+#define GPIOH_PIN3                  3
+#define GPIOH_PIN4                  4
+#define GPIOH_PIN5                  5
+#define GPIOH_PIN6                  6
+#define GPIOH_PIN7                  7
+#define GPIOH_PIN8                  8
+#define GPIOH_PIN9                  9
+#define GPIOH_PIN10                 10
+#define GPIOH_PIN11                 11
+#define GPIOH_PIN12                 12
+#define GPIOH_PIN13                 13
+#define GPIOH_PIN14                 14
+#define GPIOH_PIN15                 15
+
+#define GPIOI_PIN0                  0
+#define GPIOI_PIN1                  1
+#define GPIOI_PIN2                  2
+#define GPIOI_PIN3                  3
+#define GPIOI_PIN4                  4
+#define GPIOI_PIN5                  5
+#define GPIOI_PIN6                  6
+#define GPIOI_PIN7                  7
+#define GPIOI_PIN8                  8
+#define GPIOI_PIN9                  9
+#define GPIOI_PIN10                 10
+#define GPIOI_PIN11                 11
+#define GPIOI_PIN12                 12
+#define GPIOI_PIN13                 13
+#define GPIOI_PIN14                 14
+#define GPIOI_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - BUTTON                    (input floating).
+ * PA1  - MEMS_INT1                 (input floating).
+ * PA2  - MEMS_INT2                 (input floating).
+ * PA3  - LCD_B5                    (alternate 14).
+ * PA4  - LCD_VSYNC                 (alternate 14).
+ * PA5  - PIN5                      (input pullup).
+ * PA6  - LCD_G2                    (alternate 14).
+ * PA7  - ACP_RST                   (input pullup).
+ * PA8  - I2C3_SCL                  (alternate 4).
+ * PA9  - PIN9                      (input pullup).
+ * PA10 - PIN10                     (input pullup).
+ * PA11 - LCD_R4                    (alternate 14).
+ * PA12 - LCD_R5                    (alternate 14).
+ * PA13 - SWDIO                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 - TP_INT                    (input floating).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_BUTTON) |         \
+                                     PIN_MODE_INPUT(GPIOA_MEMS_INT1) |      \
+                                     PIN_MODE_INPUT(GPIOA_MEMS_INT2) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_LCD_B5) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_LCD_VSYNC) |  \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_ALTERNATE(GPIOA_LCD_G2) |     \
+                                     PIN_MODE_INPUT(GPIOA_ACP_RST) |        \
+                                     PIN_MODE_ALTERNATE(GPIOA_I2C3_SCL) |   \
+                                     PIN_MODE_INPUT(GPIOA_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
+                                     PIN_MODE_ALTERNATE(GPIOA_LCD_R4) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_LCD_R5) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
+                                     PIN_MODE_INPUT(GPIOA_TP_INT))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT1) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT2) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_LCD_B5) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_LCD_VSYNC) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_LCD_G2) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_ACP_RST) |    \
+                                     PIN_OTYPE_OPENDRAIN(GPIOA_I2C3_SCL) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_LCD_R4) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_LCD_R5) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_TP_INT))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_2M(GPIOA_BUTTON) |          \
+                                     PIN_OSPEED_2M(GPIOA_MEMS_INT1) |       \
+                                     PIN_OSPEED_2M(GPIOA_MEMS_INT2) |       \
+                                     PIN_OSPEED_100M(GPIOA_LCD_B5) |        \
+                                     PIN_OSPEED_100M(GPIOA_LCD_VSYNC) |     \
+                                     PIN_OSPEED_2M(GPIOA_PIN5) |            \
+                                     PIN_OSPEED_100M(GPIOA_LCD_G2) |        \
+                                     PIN_OSPEED_2M(GPIOA_ACP_RST) |         \
+                                     PIN_OSPEED_100M(GPIOA_I2C3_SCL) |      \
+                                     PIN_OSPEED_2M(GPIOA_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN10) |           \
+                                     PIN_OSPEED_100M(GPIOA_LCD_R4) |        \
+                                     PIN_OSPEED_100M(GPIOA_LCD_R5) |        \
+                                     PIN_OSPEED_100M(GPIOA_SWDIO) |         \
+                                     PIN_OSPEED_100M(GPIOA_SWCLK) |         \
+                                     PIN_OSPEED_2M(GPIOA_TP_INT))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_BUTTON) |     \
+                                     PIN_PUPDR_FLOATING(GPIOA_MEMS_INT1) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_MEMS_INT2) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_LCD_B5) |     \
+                                     PIN_PUPDR_FLOATING(GPIOA_LCD_VSYNC) |  \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_LCD_G2) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_ACP_RST) |      \
+                                     PIN_PUPDR_FLOATING(GPIOA_I2C3_SCL) |   \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |        \
+                                     PIN_PUPDR_FLOATING(GPIOA_LCD_R4) |     \
+                                     PIN_PUPDR_FLOATING(GPIOA_LCD_R5) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_SWDIO) |        \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \
+                                     PIN_PUPDR_FLOATING(GPIOA_TP_INT))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_BUTTON) |           \
+                                     PIN_ODR_HIGH(GPIOA_MEMS_INT1) |        \
+                                     PIN_ODR_HIGH(GPIOA_MEMS_INT2) |        \
+                                     PIN_ODR_HIGH(GPIOA_LCD_B5) |           \
+                                     PIN_ODR_HIGH(GPIOA_LCD_VSYNC) |        \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_LCD_G2) |           \
+                                     PIN_ODR_HIGH(GPIOA_ACP_RST) |          \
+                                     PIN_ODR_HIGH(GPIOA_I2C3_SCL) |         \
+                                     PIN_ODR_HIGH(GPIOA_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOA_LCD_R4) |           \
+                                     PIN_ODR_HIGH(GPIOA_LCD_R5) |           \
+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
+                                     PIN_ODR_HIGH(GPIOA_TP_INT))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_BUTTON, 0) |         \
+                                     PIN_AFIO_AF(GPIOA_MEMS_INT1, 0) |      \
+                                     PIN_AFIO_AF(GPIOA_MEMS_INT2, 0) |      \
+                                     PIN_AFIO_AF(GPIOA_LCD_B5, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_LCD_VSYNC, 14) |     \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_LCD_G2, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_ACP_RST, 0))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_I2C3_SCL, 4) |       \
+                                     PIN_AFIO_AF(GPIOA_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_LCD_R4, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_LCD_R5, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_TP_INT, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - LCD_R3                    (alternate 14).
+ * PB1  - LCD_R6                    (alternate 14).
+ * PB2  - BOOT1                     (input pullup).
+ * PB3  - SWO                       (alternate 0).
+ * PB4  - PIN4                      (input pullup).
+ * PB5  - FMC_SDCKE1                (alternate 12).
+ * PB6  - FMC_SDNE1                 (alternate 12).
+ * PB7  - PIN7                      (input pullup).
+ * PB8  - LCD_B6                    (alternate 14).
+ * PB9  - LCD_B7                    (alternate 14).
+ * PB10 - LCD_G4                    (alternate 14).
+ * PB11 - LCD_G5                    (alternate 14).
+ * PB12 - OTG_HS_ID                 (alternate 12).
+ * PB13 - OTG_HS_VBUS               (input pulldown).
+ * PB14 - OTG_HS_DM                 (alternate 12).
+ * PB15 - OTG_HS_DP                 (alternate 12).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_ALTERNATE(GPIOB_LCD_R3) |     \
+                                     PIN_MODE_ALTERNATE(GPIOB_LCD_R6) |     \
+                                     PIN_MODE_INPUT(GPIOB_BOOT1) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_SWO) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_FMC_SDCKE1) | \
+                                     PIN_MODE_ALTERNATE(GPIOB_FMC_SDNE1) |  \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_LCD_B6) |     \
+                                     PIN_MODE_ALTERNATE(GPIOB_LCD_B7) |     \
+                                     PIN_MODE_ALTERNATE(GPIOB_LCD_G4) |     \
+                                     PIN_MODE_ALTERNATE(GPIOB_LCD_G5) |     \
+                                     PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) |  \
+                                     PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) |    \
+                                     PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_LCD_R3) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_LCD_R6) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SWO) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_FMC_SDCKE1) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_FMC_SDNE1) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_LCD_B6) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_LCD_B7) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_LCD_G4) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_LCD_G5) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_100M(GPIOB_LCD_R3) |        \
+                                     PIN_OSPEED_100M(GPIOB_LCD_R6) |        \
+                                     PIN_OSPEED_100M(GPIOB_BOOT1) |         \
+                                     PIN_OSPEED_100M(GPIOB_SWO) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN4) |            \
+                                     PIN_OSPEED_100M(GPIOB_FMC_SDCKE1) |    \
+                                     PIN_OSPEED_100M(GPIOB_FMC_SDNE1) |     \
+                                     PIN_OSPEED_2M(GPIOB_PIN7) |            \
+                                     PIN_OSPEED_100M(GPIOB_LCD_B6) |        \
+                                     PIN_OSPEED_100M(GPIOB_LCD_B7) |        \
+                                     PIN_OSPEED_100M(GPIOB_LCD_G4) |        \
+                                     PIN_OSPEED_100M(GPIOB_LCD_G5) |        \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_ID) |     \
+                                     PIN_OSPEED_2M(GPIOB_OTG_HS_VBUS) |     \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_DM) |     \
+                                     PIN_OSPEED_100M(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_FLOATING(GPIOB_LCD_R3) |     \
+                                     PIN_PUPDR_FLOATING(GPIOB_LCD_R6) |     \
+                                     PIN_PUPDR_PULLUP(GPIOB_BOOT1) |        \
+                                     PIN_PUPDR_FLOATING(GPIOB_SWO) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_FMC_SDCKE1) | \
+                                     PIN_PUPDR_FLOATING(GPIOB_FMC_SDNE1) |  \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_LCD_B6) |     \
+                                     PIN_PUPDR_FLOATING(GPIOB_LCD_B7) |     \
+                                     PIN_PUPDR_FLOATING(GPIOB_LCD_G4) |     \
+                                     PIN_PUPDR_FLOATING(GPIOB_LCD_G5) |     \
+                                     PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) |  \
+                                     PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\
+                                     PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_LCD_R3) |           \
+                                     PIN_ODR_HIGH(GPIOB_LCD_R6) |           \
+                                     PIN_ODR_HIGH(GPIOB_BOOT1) |            \
+                                     PIN_ODR_HIGH(GPIOB_SWO) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOB_FMC_SDCKE1) |       \
+                                     PIN_ODR_HIGH(GPIOB_FMC_SDNE1) |        \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_LCD_B6) |           \
+                                     PIN_ODR_HIGH(GPIOB_LCD_B7) |           \
+                                     PIN_ODR_HIGH(GPIOB_LCD_G4) |           \
+                                     PIN_ODR_HIGH(GPIOB_LCD_G5) |           \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_ID) |        \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) |      \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_LCD_R3, 14) |        \
+                                     PIN_AFIO_AF(GPIOB_LCD_R6, 14) |        \
+                                     PIN_AFIO_AF(GPIOB_BOOT1, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_SWO, 0) |            \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_FMC_SDCKE1, 12) |    \
+                                     PIN_AFIO_AF(GPIOB_FMC_SDNE1, 12) |     \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_LCD_B6, 14) |        \
+                                     PIN_AFIO_AF(GPIOB_LCD_B7, 14) |        \
+                                     PIN_AFIO_AF(GPIOB_LCD_G4, 14) |        \
+                                     PIN_AFIO_AF(GPIOB_LCD_G5, 14) |        \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) |     \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0) |    \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) |     \
+                                     PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - FMC_SDNWE                 (alternate 12).
+ * PC1  - SPI5_MEMS_CS              (output pushpull maximum).
+ * PC2  - SPI5_LCD_CS               (output pushpull maximum).
+ * PC3  - PIN3                      (input pullup).
+ * PC4  - OTG_HS_PSO                (output pushpull maximum).
+ * PC5  - OTG_HS_OC                 (input floating).
+ * PC6  - LCD_HSYNC                 (alternate 14).
+ * PC7  - LCD_G6                    (alternate 14).
+ * PC8  - PIN8                      (input pullup).
+ * PC9  - I2C3_SDA                  (alternate 4).
+ * PC10 - LCD_R2                    (alternate 14).
+ * PC11 - PIN11                     (input pullup).
+ * PC12 - PIN12                     (input pullup).
+ * PC13 - PIN13                     (input pullup).
+ * PC14 - OSC32_IN                  (input floating).
+ * PC15 - OSC32_OUT                 (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_ALTERNATE(GPIOC_FMC_SDNWE) |  \
+                                     PIN_MODE_OUTPUT(GPIOC_SPI5_MEMS_CS) |  \
+                                     PIN_MODE_OUTPUT(GPIOC_SPI5_LCD_CS) |   \
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
+                                     PIN_MODE_OUTPUT(GPIOC_OTG_HS_PSO) |    \
+                                     PIN_MODE_INPUT(GPIOC_OTG_HS_OC) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_LCD_HSYNC) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_LCD_G6) |     \
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
+                                     PIN_MODE_ALTERNATE(GPIOC_I2C3_SDA) |   \
+                                     PIN_MODE_ALTERNATE(GPIOC_LCD_R2) |     \
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_FMC_SDNWE) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI5_MEMS_CS) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI5_LCD_CS) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_PSO) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_OC) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_LCD_HSYNC) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_LCD_G6) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOC_I2C3_SDA) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_LCD_R2) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_100M(GPIOC_FMC_SDNWE) |     \
+                                     PIN_OSPEED_100M(GPIOC_SPI5_MEMS_CS) |  \
+                                     PIN_OSPEED_100M(GPIOC_SPI5_LCD_CS) |   \
+                                     PIN_OSPEED_2M(GPIOC_PIN3) |            \
+                                     PIN_OSPEED_100M(GPIOC_OTG_HS_PSO) |    \
+                                     PIN_OSPEED_100M(GPIOC_OTG_HS_OC) |     \
+                                     PIN_OSPEED_100M(GPIOC_LCD_HSYNC) |     \
+                                     PIN_OSPEED_100M(GPIOC_LCD_G6) |        \
+                                     PIN_OSPEED_2M(GPIOC_PIN8) |            \
+                                     PIN_OSPEED_100M(GPIOC_I2C3_SDA) |      \
+                                     PIN_OSPEED_100M(GPIOC_LCD_R2) |        \
+                                     PIN_OSPEED_2M(GPIOC_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN13) |           \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_IN) |      \
+                                     PIN_OSPEED_100M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_FLOATING(GPIOC_FMC_SDNWE) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI5_MEMS_CS) |\
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI5_LCD_CS) |\
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_OTG_HS_PSO) | \
+                                     PIN_PUPDR_FLOATING(GPIOC_OTG_HS_OC) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_LCD_HSYNC) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_LCD_G6) |     \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_I2C3_SDA) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_LCD_R2) |     \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_FMC_SDNWE) |        \
+                                     PIN_ODR_HIGH(GPIOC_SPI5_MEMS_CS) |     \
+                                     PIN_ODR_HIGH(GPIOC_SPI5_LCD_CS) |      \
+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOC_OTG_HS_PSO) |       \
+                                     PIN_ODR_HIGH(GPIOC_OTG_HS_OC) |        \
+                                     PIN_ODR_HIGH(GPIOC_LCD_HSYNC) |        \
+                                     PIN_ODR_HIGH(GPIOC_LCD_G6) |           \
+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOC_I2C3_SDA) |         \
+                                     PIN_ODR_HIGH(GPIOC_LCD_R2) |           \
+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_FMC_SDNWE, 12) |     \
+                                     PIN_AFIO_AF(GPIOC_SPI5_MEMS_CS, 0) |   \
+                                     PIN_AFIO_AF(GPIOC_SPI5_LCD_CS, 0) |    \
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_OTG_HS_PSO, 0) |     \
+                                     PIN_AFIO_AF(GPIOC_OTG_HS_OC, 0) |      \
+                                     PIN_AFIO_AF(GPIOC_LCD_HSYNC, 14) |     \
+                                     PIN_AFIO_AF(GPIOC_LCD_G6, 14))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_I2C3_SDA, 4) |       \
+                                     PIN_AFIO_AF(GPIOC_LCD_R2, 14) |        \
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0) |       \
+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - FMC_D2                    (alternate 12).
+ * PD1  - FMC_D3                    (alternate 12).
+ * PD2  - PIN2                      (input pullup).
+ * PD3  - LCD_G7                    (alternate 14).
+ * PD4  - PIN4                      (input pullup).
+ * PD5  - PIN5                      (input pullup).
+ * PD6  - LCD_B2                    (alternate 14).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - FMC_D13                   (alternate 12).
+ * PD9  - FMC_D14                   (alternate 12).
+ * PD10 - FMC_D15                   (alternate 12).
+ * PD11 - LCD_TE                    (input floating).
+ * PD12 - LCD_RDX                   (output pushpull maximum).
+ * PD13 - LCD_WRX                   (output pushpull maximum).
+ * PD14 - FMC_D0                    (alternate 12).
+ * PD15 - FMC_D1                    (alternate 12).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_ALTERNATE(GPIOD_FMC_D2) |     \
+                                     PIN_MODE_ALTERNATE(GPIOD_FMC_D3) |     \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOD_LCD_G7) |     \
+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \
+                                     PIN_MODE_ALTERNATE(GPIOD_LCD_B2) |     \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_ALTERNATE(GPIOD_FMC_D13) |    \
+                                     PIN_MODE_ALTERNATE(GPIOD_FMC_D14) |    \
+                                     PIN_MODE_ALTERNATE(GPIOD_FMC_D15) |    \
+                                     PIN_MODE_INPUT(GPIOD_LCD_TE) |         \
+                                     PIN_MODE_OUTPUT(GPIOD_LCD_RDX) |       \
+                                     PIN_MODE_OUTPUT(GPIOD_LCD_WRX) |       \
+                                     PIN_MODE_ALTERNATE(GPIOD_FMC_D0) |     \
+                                     PIN_MODE_ALTERNATE(GPIOD_FMC_D1))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_FMC_D2) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_FMC_D3) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LCD_G7) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LCD_B2) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_FMC_D13) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_FMC_D14) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_FMC_D15) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LCD_TE) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LCD_RDX) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LCD_WRX) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_FMC_D0) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_FMC_D1))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_100M(GPIOD_FMC_D2) |        \
+                                     PIN_OSPEED_100M(GPIOD_FMC_D3) |        \
+                                     PIN_OSPEED_2M(GPIOD_PIN2) |            \
+                                     PIN_OSPEED_100M(GPIOD_LCD_G7) |        \
+                                     PIN_OSPEED_2M(GPIOD_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN5) |            \
+                                     PIN_OSPEED_100M(GPIOD_LCD_B2) |        \
+                                     PIN_OSPEED_2M(GPIOD_PIN7) |            \
+                                     PIN_OSPEED_100M(GPIOD_FMC_D13) |       \
+                                     PIN_OSPEED_100M(GPIOD_FMC_D14) |       \
+                                     PIN_OSPEED_100M(GPIOD_FMC_D15) |       \
+                                     PIN_OSPEED_100M(GPIOD_LCD_TE) |        \
+                                     PIN_OSPEED_100M(GPIOD_LCD_RDX) |       \
+                                     PIN_OSPEED_100M(GPIOD_LCD_WRX) |       \
+                                     PIN_OSPEED_100M(GPIOD_FMC_D0) |        \
+                                     PIN_OSPEED_100M(GPIOD_FMC_D1))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_FLOATING(GPIOD_FMC_D2) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_FMC_D3) |     \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_LCD_G7) |     \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_LCD_B2) |     \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_FMC_D13) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_FMC_D14) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_FMC_D15) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_LCD_TE) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_LCD_RDX) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_LCD_WRX) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_FMC_D0) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_FMC_D1))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_FMC_D2) |           \
+                                     PIN_ODR_HIGH(GPIOD_FMC_D3) |           \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_LCD_G7) |           \
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOD_LCD_B2) |           \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_FMC_D13) |          \
+                                     PIN_ODR_HIGH(GPIOD_FMC_D14) |          \
+                                     PIN_ODR_HIGH(GPIOD_FMC_D15) |          \
+                                     PIN_ODR_HIGH(GPIOD_LCD_TE) |           \
+                                     PIN_ODR_HIGH(GPIOD_LCD_RDX) |          \
+                                     PIN_ODR_HIGH(GPIOD_LCD_WRX) |          \
+                                     PIN_ODR_HIGH(GPIOD_FMC_D0) |           \
+                                     PIN_ODR_HIGH(GPIOD_FMC_D1))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_FMC_D2, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_FMC_D3, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_LCD_G7, 14) |        \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_LCD_B2, 14) |        \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_FMC_D13, 12) |       \
+                                     PIN_AFIO_AF(GPIOD_FMC_D14, 12) |       \
+                                     PIN_AFIO_AF(GPIOD_FMC_D15, 12) |       \
+                                     PIN_AFIO_AF(GPIOD_LCD_TE, 0) |         \
+                                     PIN_AFIO_AF(GPIOD_LCD_RDX, 0) |        \
+                                     PIN_AFIO_AF(GPIOD_LCD_WRX, 0) |        \
+                                     PIN_AFIO_AF(GPIOD_FMC_D0, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_FMC_D1, 12))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0  - FMC_NBL0                  (alternate 12).
+ * PE1  - FMC_NBL1                  (alternate 12).
+ * PE2  - PIN2                      (input pullup).
+ * PE3  - PIN3                      (input pullup).
+ * PE4  - PIN4                      (input pullup).
+ * PE5  - PIN5                      (input pullup).
+ * PE6  - PIN6                      (input pullup).
+ * PE7  - FMC_D4                    (alternate 12).
+ * PE8  - FMC_D5                    (alternate 12).
+ * PE9  - FMC_D6                    (alternate 12).
+ * PE10 - FMC_D7                    (alternate 12).
+ * PE11 - FMC_D8                    (alternate 12).
+ * PE12 - FMC_D9                    (alternate 12).
+ * PE13 - FMC_D10                   (alternate 12).
+ * PE14 - FMC_D11                   (alternate 12).
+ * PE15 - FMC_D12                   (alternate 12).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) |   \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) |   \
+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_D4) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_D5) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_D6) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_D7) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_D8) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_D9) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_D10) |    \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_D11) |    \
+                                     PIN_MODE_ALTERNATE(GPIOE_FMC_D12))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_D4) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_D5) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_D6) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_D7) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_D8) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_D9) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_D10) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_D11) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_FMC_D12))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_100M(GPIOE_FMC_NBL0) |      \
+                                     PIN_OSPEED_100M(GPIOE_FMC_NBL1) |      \
+                                     PIN_OSPEED_2M(GPIOE_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOE_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOE_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOE_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOE_PIN6) |            \
+                                     PIN_OSPEED_100M(GPIOE_FMC_D4) |        \
+                                     PIN_OSPEED_100M(GPIOE_FMC_D5) |        \
+                                     PIN_OSPEED_100M(GPIOE_FMC_D6) |        \
+                                     PIN_OSPEED_100M(GPIOE_FMC_D7) |        \
+                                     PIN_OSPEED_100M(GPIOE_FMC_D8) |        \
+                                     PIN_OSPEED_100M(GPIOE_FMC_D9) |        \
+                                     PIN_OSPEED_100M(GPIOE_FMC_D10) |       \
+                                     PIN_OSPEED_100M(GPIOE_FMC_D11) |       \
+                                     PIN_OSPEED_100M(GPIOE_FMC_D12))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) |   \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) |   \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_D4) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_D5) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_D6) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_D7) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_D8) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_D9) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_D10) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_D11) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_FMC_D12))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_FMC_NBL0) |         \
+                                     PIN_ODR_HIGH(GPIOE_FMC_NBL1) |         \
+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOE_FMC_D4) |           \
+                                     PIN_ODR_HIGH(GPIOE_FMC_D5) |           \
+                                     PIN_ODR_HIGH(GPIOE_FMC_D6) |           \
+                                     PIN_ODR_HIGH(GPIOE_FMC_D7) |           \
+                                     PIN_ODR_HIGH(GPIOE_FMC_D8) |           \
+                                     PIN_ODR_HIGH(GPIOE_FMC_D9) |           \
+                                     PIN_ODR_HIGH(GPIOE_FMC_D10) |          \
+                                     PIN_ODR_HIGH(GPIOE_FMC_D11) |          \
+                                     PIN_ODR_HIGH(GPIOE_FMC_D12))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12) |      \
+                                     PIN_AFIO_AF(GPIOE_FMC_NBL1, 12) |      \
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_FMC_D4, 12))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_FMC_D5, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_FMC_D6, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_FMC_D7, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_FMC_D8, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_FMC_D9, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_FMC_D10, 12) |       \
+                                     PIN_AFIO_AF(GPIOE_FMC_D11, 12) |       \
+                                     PIN_AFIO_AF(GPIOE_FMC_D12, 12))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0  - FMC_A0                    (alternate 12).
+ * PF1  - FMC_A1                    (alternate 12).
+ * PF2  - FMC_A2                    (alternate 12).
+ * PF3  - FMC_A3                    (alternate 12).
+ * PF4  - FMC_A4                    (alternate 12).
+ * PF5  - FMC_A5                    (alternate 12).
+ * PF6  - PIN6                      (input pullup).
+ * PF7  - LCD_DCX                   (output pushpull maximum).
+ * PF8  - SPI5_MISO                 (alternate 5).
+ * PF9  - SPI5_MOSI                 (alternate 5).
+ * PF10 - LCD_DE                    (output pushpull maximum).
+ * PF11 - FMC_SDNRAS                (alternate 12).
+ * PF12 - FMC_A6                    (alternate 12).
+ * PF13 - FMC_A7                    (alternate 12).
+ * PF14 - FMC_A8                    (alternate 12).
+ * PF15 - FMC_A9                    (alternate 12).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_ALTERNATE(GPIOF_FMC_A0) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_A1) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_A2) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_A3) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_A4) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_A5) |     \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_OUTPUT(GPIOF_LCD_DCX) |       \
+                                     PIN_MODE_ALTERNATE(GPIOF_SPI5_MISO) |  \
+                                     PIN_MODE_ALTERNATE(GPIOF_SPI5_MOSI) |  \
+                                     PIN_MODE_OUTPUT(GPIOF_LCD_DE) |        \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_A6) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_A7) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_A8) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_FMC_A9))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_FMC_A0) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_A1) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_A2) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_A3) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_A4) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_A5) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_LCD_DCX) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MISO) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MOSI) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_LCD_DE) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_SDNRAS) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_A6) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_A7) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_A8) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_FMC_A9))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_100M(GPIOF_FMC_A0) |        \
+                                     PIN_OSPEED_100M(GPIOF_FMC_A1) |        \
+                                     PIN_OSPEED_100M(GPIOF_FMC_A2) |        \
+                                     PIN_OSPEED_100M(GPIOF_FMC_A3) |        \
+                                     PIN_OSPEED_100M(GPIOF_FMC_A4) |        \
+                                     PIN_OSPEED_100M(GPIOF_FMC_A5) |        \
+                                     PIN_OSPEED_2M(GPIOF_PIN6) |            \
+                                     PIN_OSPEED_100M(GPIOF_LCD_DCX) |       \
+                                     PIN_OSPEED_100M(GPIOF_SPI5_MISO) |     \
+                                     PIN_OSPEED_100M(GPIOF_SPI5_MOSI) |     \
+                                     PIN_OSPEED_100M(GPIOF_LCD_DE) |        \
+                                     PIN_OSPEED_100M(GPIOF_FMC_SDNRAS) |    \
+                                     PIN_OSPEED_100M(GPIOF_FMC_A6) |        \
+                                     PIN_OSPEED_100M(GPIOF_FMC_A7) |        \
+                                     PIN_OSPEED_100M(GPIOF_FMC_A8) |        \
+                                     PIN_OSPEED_100M(GPIOF_FMC_A9))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_FMC_A0) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_A1) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_A2) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_A3) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_A4) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_A5) |     \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \
+                                     PIN_PUPDR_FLOATING(GPIOF_LCD_DCX) |    \
+                                     PIN_PUPDR_FLOATING(GPIOF_SPI5_MISO) |  \
+                                     PIN_PUPDR_FLOATING(GPIOF_SPI5_MOSI) |  \
+                                     PIN_PUPDR_FLOATING(GPIOF_LCD_DE) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_SDNRAS) | \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_A6) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_A7) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_A8) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_FMC_A9))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_FMC_A0) |           \
+                                     PIN_ODR_HIGH(GPIOF_FMC_A1) |           \
+                                     PIN_ODR_HIGH(GPIOF_FMC_A2) |           \
+                                     PIN_ODR_HIGH(GPIOF_FMC_A3) |           \
+                                     PIN_ODR_HIGH(GPIOF_FMC_A4) |           \
+                                     PIN_ODR_HIGH(GPIOF_FMC_A5) |           \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_LCD_DCX) |          \
+                                     PIN_ODR_HIGH(GPIOF_SPI5_MISO) |        \
+                                     PIN_ODR_HIGH(GPIOF_SPI5_MOSI) |        \
+                                     PIN_ODR_HIGH(GPIOF_LCD_DE) |           \
+                                     PIN_ODR_HIGH(GPIOF_FMC_SDNRAS) |       \
+                                     PIN_ODR_HIGH(GPIOF_FMC_A6) |           \
+                                     PIN_ODR_HIGH(GPIOF_FMC_A7) |           \
+                                     PIN_ODR_HIGH(GPIOF_FMC_A8) |           \
+                                     PIN_ODR_HIGH(GPIOF_FMC_A9))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_FMC_A0, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_FMC_A1, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_FMC_A2, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_FMC_A3, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_FMC_A4, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_FMC_A5, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_LCD_DCX, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_SPI5_MISO, 5) |      \
+                                     PIN_AFIO_AF(GPIOF_SPI5_MOSI, 5) |      \
+                                     PIN_AFIO_AF(GPIOF_LCD_DE, 0) |         \
+                                     PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12) |    \
+                                     PIN_AFIO_AF(GPIOF_FMC_A6, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_FMC_A7, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_FMC_A8, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_FMC_A9, 12))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0  - FMC_A10                   (alternate 12).
+ * PG1  - FMC_A11                   (alternate 12).
+ * PG2  - PIN2                      (input pullup).
+ * PG3  - PIN3                      (input pullup).
+ * PG4  - FMC_BA0                   (alternate 12).
+ * PG5  - FMC_BA1                   (alternate 12).
+ * PG6  - LCD_R7                    (alternate 14).
+ * PG7  - LCD_CLK                   (alternate 14).
+ * PG8  - FMC_SDCLK                 (alternate 12).
+ * PG9  - PIN9                      (input pullup).
+ * PG10 - LCD_G3                    (alternate 14).
+ * PG11 - LCD_B3                    (alternate 14).
+ * PG12 - LCD_B4                    (alternate 14).
+ * PG13 - LED3_GREEN                (output pushpull maximum).
+ * PG14 - LED4_RED                  (output pushpull maximum).
+ * PG15 - FMC_SDNCAS                (alternate 12).
+ */
+#define VAL_GPIOG_MODER             (PIN_MODE_ALTERNATE(GPIOG_FMC_A10) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_FMC_A11) |    \
+                                     PIN_MODE_INPUT(GPIOG_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN3) |           \
+                                     PIN_MODE_ALTERNATE(GPIOG_FMC_BA0) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_FMC_BA1) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_LCD_R7) |     \
+                                     PIN_MODE_ALTERNATE(GPIOG_LCD_CLK) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_FMC_SDCLK) |  \
+                                     PIN_MODE_INPUT(GPIOG_PIN9) |           \
+                                     PIN_MODE_ALTERNATE(GPIOG_LCD_G3) |     \
+                                     PIN_MODE_ALTERNATE(GPIOG_LCD_B3) |     \
+                                     PIN_MODE_ALTERNATE(GPIOG_LCD_B4) |     \
+                                     PIN_MODE_OUTPUT(GPIOG_LED3_GREEN) |    \
+                                     PIN_MODE_OUTPUT(GPIOG_LED4_RED) |      \
+                                     PIN_MODE_ALTERNATE(GPIOG_FMC_SDNCAS))
+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_FMC_A10) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_FMC_A11) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA0) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA1) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_LCD_R7) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_LCD_CLK) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDCLK) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_LCD_G3) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_LCD_B3) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_LCD_B4) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_LED3_GREEN) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_LED4_RED) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDNCAS))
+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_100M(GPIOG_FMC_A10) |       \
+                                     PIN_OSPEED_100M(GPIOG_FMC_A11) |       \
+                                     PIN_OSPEED_2M(GPIOG_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOG_PIN3) |            \
+                                     PIN_OSPEED_100M(GPIOG_FMC_BA0) |       \
+                                     PIN_OSPEED_100M(GPIOG_FMC_BA1) |       \
+                                     PIN_OSPEED_100M(GPIOG_LCD_R7) |        \
+                                     PIN_OSPEED_100M(GPIOG_LCD_CLK) |       \
+                                     PIN_OSPEED_100M(GPIOG_FMC_SDCLK) |     \
+                                     PIN_OSPEED_2M(GPIOG_PIN9) |            \
+                                     PIN_OSPEED_100M(GPIOG_LCD_G3) |        \
+                                     PIN_OSPEED_100M(GPIOG_LCD_B3) |        \
+                                     PIN_OSPEED_100M(GPIOG_LCD_B4) |        \
+                                     PIN_OSPEED_100M(GPIOG_LED3_GREEN) |    \
+                                     PIN_OSPEED_100M(GPIOG_LED4_RED) |      \
+                                     PIN_OSPEED_100M(GPIOG_FMC_SDNCAS))
+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_FLOATING(GPIOG_FMC_A10) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_FMC_A11) |    \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN3) |         \
+                                     PIN_PUPDR_FLOATING(GPIOG_FMC_BA0) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_FMC_BA1) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_LCD_R7) |     \
+                                     PIN_PUPDR_FLOATING(GPIOG_LCD_CLK) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_FMC_SDCLK) |  \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN9) |         \
+                                     PIN_PUPDR_FLOATING(GPIOG_LCD_G3) |     \
+                                     PIN_PUPDR_FLOATING(GPIOG_LCD_B3) |     \
+                                     PIN_PUPDR_FLOATING(GPIOG_LCD_B4) |     \
+                                     PIN_PUPDR_FLOATING(GPIOG_LED3_GREEN) | \
+                                     PIN_PUPDR_FLOATING(GPIOG_LED4_RED) |   \
+                                     PIN_PUPDR_FLOATING(GPIOG_FMC_SDNCAS))
+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_FMC_A10) |          \
+                                     PIN_ODR_HIGH(GPIOG_FMC_A11) |          \
+                                     PIN_ODR_HIGH(GPIOG_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOG_FMC_BA0) |          \
+                                     PIN_ODR_HIGH(GPIOG_FMC_BA1) |          \
+                                     PIN_ODR_HIGH(GPIOG_LCD_R7) |           \
+                                     PIN_ODR_HIGH(GPIOG_LCD_CLK) |          \
+                                     PIN_ODR_HIGH(GPIOG_FMC_SDCLK) |        \
+                                     PIN_ODR_HIGH(GPIOG_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOG_LCD_G3) |           \
+                                     PIN_ODR_HIGH(GPIOG_LCD_B3) |           \
+                                     PIN_ODR_HIGH(GPIOG_LCD_B4) |           \
+                                     PIN_ODR_LOW(GPIOG_LED3_GREEN) |        \
+                                     PIN_ODR_LOW(GPIOG_LED4_RED) |          \
+                                     PIN_ODR_HIGH(GPIOG_FMC_SDNCAS))
+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_FMC_A10, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_FMC_A11, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_FMC_BA0, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_FMC_BA1, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_LCD_R7, 14) |        \
+                                     PIN_AFIO_AF(GPIOG_LCD_CLK, 14))
+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_FMC_SDCLK, 12) |     \
+                                     PIN_AFIO_AF(GPIOG_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_LCD_G3, 14) |        \
+                                     PIN_AFIO_AF(GPIOG_LCD_B3, 14) |        \
+                                     PIN_AFIO_AF(GPIOG_LCD_B4, 14) |        \
+                                     PIN_AFIO_AF(GPIOG_LED3_GREEN, 0) |     \
+                                     PIN_AFIO_AF(GPIOG_LED4_RED, 0) |       \
+                                     PIN_AFIO_AF(GPIOG_FMC_SDNCAS, 12))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0  - OSC_IN                    (input floating).
+ * PH1  - OSC_OUT                   (input floating).
+ * PH2  - PIN2                      (input pullup).
+ * PH3  - PIN3                      (input pullup).
+ * PH4  - PIN4                      (input pullup).
+ * PH5  - PIN5                      (input pullup).
+ * PH6  - PIN6                      (input pullup).
+ * PH7  - PIN7                      (input pullup).
+ * PH8  - PIN8                      (input pullup).
+ * PH9  - PIN9                      (input pullup).
+ * PH10 - PIN10                     (input pullup).
+ * PH11 - PIN11                     (input pullup).
+ * PH12 - PIN12                     (input pullup).
+ * PH13 - PIN13                     (input pullup).
+ * PH14 - PIN14                     (input pullup).
+ * PH15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_100M(GPIOH_OSC_IN) |        \
+                                     PIN_OSPEED_100M(GPIOH_OSC_OUT) |       \
+                                     PIN_OSPEED_2M(GPIOH_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOH_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOH_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOH_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOH_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOH_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOH_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOH_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOH_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOH_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOH_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOH_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOH_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOH_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0  - PIN0                      (input pullup).
+ * PI1  - PIN1                      (input pullup).
+ * PI2  - PIN2                      (input pullup).
+ * PI3  - PIN3                      (input pullup).
+ * PI4  - PIN4                      (input pullup).
+ * PI5  - PIN5                      (input pullup).
+ * PI6  - PIN6                      (input pullup).
+ * PI7  - PIN7                      (input pullup).
+ * PI8  - PIN8                      (input pullup).
+ * PI9  - PIN9                      (input pullup).
+ * PI10 - PIN10                     (input pullup).
+ * PI11 - PIN11                     (input pullup).
+ * PI12 - PIN12                     (input pullup).
+ * PI13 - PIN13                     (input pullup).
+ * PI14 - PIN14                     (input pullup).
+ * PI15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOI_MODER             (PIN_MODE_INPUT(GPIOI_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR           (PIN_OSPEED_2M(GPIOI_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOI_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOI_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOI_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOI_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOI_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR             (PIN_PUPDR_PULLUP(GPIOI_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR               (PIN_ODR_HIGH(GPIOI_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL              (PIN_AFIO_AF(GPIOI_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH              (PIN_AFIO_AF(GPIOI_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk
new file mode 100644
index 000000000..f927cbb71
--- /dev/null
+++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F429I_DISCOVERY
diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg
new file mode 100644
index 000000000..a4ec62ef3
--- /dev/null
+++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg
@@ -0,0 +1,1192 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F4xx board Template -->
+<board
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+  <configuration_settings>
+  	<templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+  	<output_path>..</output_path>
+  </configuration_settings>
+  <board_name>STMicroelectronics STM32F429I-Discovery</board_name>
+  <board_id>ST_STM32F429I_DISCOVERY</board_id>
+  <board_functions></board_functions>
+  <subtype>STM32F429_439xx</subtype>
+  <clocks
+    HSEFrequency="8000000"
+    HSEBypass="false"
+    LSEFrequency="0"
+    LSEBypass="false"
+    VDD="300" />
+  <ports>
+    <GPIOA>
+      <pin0
+        ID="BUTTON"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="MEMS_INT1"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID="MEMS_INT2"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="LCD_B5"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin4
+        ID="LCD_VSYNC"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID="LCD_G2"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin7
+        ID="ACP_RST"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID="I2C3_SCL"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID="LCD_R4"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin12
+        ID="LCD_R5"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin13
+        ID="SWDIO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin14
+        ID="SWCLK"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin15
+        ID="TP_INT"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOA>
+    <GPIOB>
+      <pin0
+        ID="LCD_R3"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin1
+        ID="LCD_R6"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin2
+        ID="BOOT1"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="SWO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID="FMC_SDCKE1"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin6
+        ID="FMC_SDNE1"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID="LCD_B6"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin9
+        ID="LCD_B7"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin10
+        ID="LCD_G4"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin11
+        ID="LCD_G5"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin12
+        ID="OTG_HS_ID"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin13
+        ID="OTG_HS_VBUS"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID="OTG_HS_DM"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin15
+        ID="OTG_HS_DP"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+    </GPIOB>
+    <GPIOC>
+      <pin0
+        ID="FMC_SDNWE"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin1
+        ID="SPI5_MEMS_CS"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" ></pin1>
+      <pin2
+        ID="SPI5_LCD_CS"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID="OTG_HS_PSO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin5
+        ID="OTG_HS_OC"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID="LCD_HSYNC"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin7
+        ID="LCD_G6"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID="I2C3_SDA"
+        Type="OpenDrain"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin10
+        ID="LCD_R2"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID="OSC32_IN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID="OSC32_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOC>
+    <GPIOD>
+      <pin0
+        ID="FMC_D2"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin1
+        ID="FMC_D3"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="LCD_G7"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID="LCD_B2"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID="FMC_D13"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin9
+        ID="FMC_D14"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin10
+        ID="FMC_D15"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin11
+        ID="LCD_TE"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID="LCD_RDX"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin13
+        ID="LCD_WRX"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin14
+        ID="FMC_D0"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin15
+        ID="FMC_D1"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+    </GPIOD>
+    <GPIOE>
+      <pin0
+        ID="FMC_NBL0"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin1
+        ID="FMC_NBL1"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID="FMC_D4"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin8
+        ID="FMC_D5"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin9
+        ID="FMC_D6"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin10
+        ID="FMC_D7"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin11
+        ID="FMC_D8"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin12
+        ID="FMC_D9"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin13
+        ID="FMC_D10"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin14
+        ID="FMC_D11"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin15
+        ID="FMC_D12"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+    </GPIOE>
+    <GPIOF>
+      <pin0
+        ID="FMC_A0"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin1
+        ID="FMC_A1"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin2
+        ID="FMC_A2"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin3
+        ID="FMC_A3"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin4
+        ID="FMC_A4"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin5
+        ID="FMC_A5"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID="LCD_DCX"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin8
+        ID="SPI5_MISO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin9
+        ID="SPI5_MOSI"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin10
+        ID="LCD_DE"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Output"
+        Alternate="0" />
+      <pin11
+        ID="FMC_SDNRAS"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin12
+        ID="FMC_A6"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin13
+        ID="FMC_A7"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin14
+        ID="FMC_A8"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin15
+        ID="FMC_A9"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+    </GPIOF>
+    <GPIOG>
+      <pin0
+        ID="FMC_A10"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin1
+        ID="FMC_A11"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID="FMC_BA0"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin5
+        ID="FMC_BA1"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin6
+        ID="LCD_R7"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin7
+        ID="LCD_CLK"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin8
+        ID="FMC_SDCLK"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID="LCD_G3"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin11
+        ID="LCD_B3"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin12
+        ID="LCD_B4"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin13
+        ID="LED3_GREEN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin14
+        ID="LED4_RED"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin15
+        ID="FMC_SDNCAS"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="12" />
+    </GPIOG>
+    <GPIOH>
+      <pin0
+        ID="OSC_IN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0"></pin0>
+      <pin1
+        ID="OSC_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOH>
+    <GPIOI>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOI>
+  </ports>
+</board>
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.c b/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
new file mode 100644
index 000000000..e6e81c436
--- /dev/null
+++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
@@ -0,0 +1,107 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.h b/os/hal/boards/ST_STM32F4_DISCOVERY/board.h
new file mode 100644
index 000000000..900416353
--- /dev/null
+++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.h
@@ -0,0 +1,1296 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F4-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F4_DISCOVERY
+#define BOARD_NAME                  "STMicroelectronics STM32F4-Discovery"
+
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                0
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                8000000
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   300
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F40_41xxx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON                0
+#define GPIOA_PIN1                  1
+#define GPIOA_PIN2                  2
+#define GPIOA_PIN3                  3
+#define GPIOA_LRCK                  4
+#define GPIOA_SPC                   5
+#define GPIOA_SDO                   6
+#define GPIOA_SDI                   7
+#define GPIOA_PIN8                  8
+#define GPIOA_VBUS_FS               9
+#define GPIOA_OTG_FS_ID             10
+#define GPIOA_OTG_FS_DM             11
+#define GPIOA_OTG_FS_DP             12
+#define GPIOA_SWDIO                 13
+#define GPIOA_SWCLK                 14
+#define GPIOA_PIN15                 15
+
+#define GPIOB_PIN0                  0
+#define GPIOB_PIN1                  1
+#define GPIOB_PIN2                  2
+#define GPIOB_SWO                   3
+#define GPIOB_PIN4                  4
+#define GPIOB_PIN5                  5
+#define GPIOB_SCL                   6
+#define GPIOB_PIN7                  7
+#define GPIOB_PIN8                  8
+#define GPIOB_SDA                   9
+#define GPIOB_CLK_IN                10
+#define GPIOB_PIN11                 11
+#define GPIOB_PIN12                 12
+#define GPIOB_PIN13                 13
+#define GPIOB_PIN14                 14
+#define GPIOB_PIN15                 15
+
+#define GPIOC_OTG_FS_POWER_ON       0
+#define GPIOC_PIN1                  1
+#define GPIOC_PIN2                  2
+#define GPIOC_PDM_OUT               3
+#define GPIOC_PIN4                  4
+#define GPIOC_PIN5                  5
+#define GPIOC_PIN6                  6
+#define GPIOC_MCLK                  7
+#define GPIOC_PIN8                  8
+#define GPIOC_PIN9                  9
+#define GPIOC_SCLK                  10
+#define GPIOC_PIN11                 11
+#define GPIOC_SDIN                  12
+#define GPIOC_PIN13                 13
+#define GPIOC_PIN14                 14
+#define GPIOC_PIN15                 15
+
+#define GPIOD_PIN0                  0
+#define GPIOD_PIN1                  1
+#define GPIOD_PIN2                  2
+#define GPIOD_PIN3                  3
+#define GPIOD_RESET                 4
+#define GPIOD_OVER_CURRENT          5
+#define GPIOD_PIN6                  6
+#define GPIOD_PIN7                  7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_PIN11                 11
+#define GPIOD_LED4                  12
+#define GPIOD_LED3                  13
+#define GPIOD_LED5                  14
+#define GPIOD_LED6                  15
+
+#define GPIOE_INT1                  0
+#define GPIOE_INT2                  1
+#define GPIOE_PIN2                  2
+#define GPIOE_CS_SPI                3
+#define GPIOE_PIN4                  4
+#define GPIOE_PIN5                  5
+#define GPIOE_PIN6                  6
+#define GPIOE_PIN7                  7
+#define GPIOE_PIN8                  8
+#define GPIOE_PIN9                  9
+#define GPIOE_PIN10                 10
+#define GPIOE_PIN11                 11
+#define GPIOE_PIN12                 12
+#define GPIOE_PIN13                 13
+#define GPIOE_PIN14                 14
+#define GPIOE_PIN15                 15
+
+#define GPIOF_PIN0                  0
+#define GPIOF_PIN1                  1
+#define GPIOF_PIN2                  2
+#define GPIOF_PIN3                  3
+#define GPIOF_PIN4                  4
+#define GPIOF_PIN5                  5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_PIN9                  9
+#define GPIOF_PIN10                 10
+#define GPIOF_PIN11                 11
+#define GPIOF_PIN12                 12
+#define GPIOF_PIN13                 13
+#define GPIOF_PIN14                 14
+#define GPIOF_PIN15                 15
+
+#define GPIOG_PIN0                  0
+#define GPIOG_PIN1                  1
+#define GPIOG_PIN2                  2
+#define GPIOG_PIN3                  3
+#define GPIOG_PIN4                  4
+#define GPIOG_PIN5                  5
+#define GPIOG_PIN6                  6
+#define GPIOG_PIN7                  7
+#define GPIOG_PIN8                  8
+#define GPIOG_PIN9                  9
+#define GPIOG_PIN10                 10
+#define GPIOG_PIN11                 11
+#define GPIOG_PIN12                 12
+#define GPIOG_PIN13                 13
+#define GPIOG_PIN14                 14
+#define GPIOG_PIN15                 15
+
+#define GPIOH_OSC_IN                0
+#define GPIOH_OSC_OUT               1
+#define GPIOH_PIN2                  2
+#define GPIOH_PIN3                  3
+#define GPIOH_PIN4                  4
+#define GPIOH_PIN5                  5
+#define GPIOH_PIN6                  6
+#define GPIOH_PIN7                  7
+#define GPIOH_PIN8                  8
+#define GPIOH_PIN9                  9
+#define GPIOH_PIN10                 10
+#define GPIOH_PIN11                 11
+#define GPIOH_PIN12                 12
+#define GPIOH_PIN13                 13
+#define GPIOH_PIN14                 14
+#define GPIOH_PIN15                 15
+
+#define GPIOI_PIN0                  0
+#define GPIOI_PIN1                  1
+#define GPIOI_PIN2                  2
+#define GPIOI_PIN3                  3
+#define GPIOI_PIN4                  4
+#define GPIOI_PIN5                  5
+#define GPIOI_PIN6                  6
+#define GPIOI_PIN7                  7
+#define GPIOI_PIN8                  8
+#define GPIOI_PIN9                  9
+#define GPIOI_PIN10                 10
+#define GPIOI_PIN11                 11
+#define GPIOI_PIN12                 12
+#define GPIOI_PIN13                 13
+#define GPIOI_PIN14                 14
+#define GPIOI_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - BUTTON                    (input floating).
+ * PA1  - PIN1                      (input pullup).
+ * PA2  - PIN2                      (input pullup).
+ * PA3  - PIN3                      (input pullup).
+ * PA4  - LRCK                      (alternate 6).
+ * PA5  - SPC                       (alternate 5).
+ * PA6  - SDO                       (alternate 5).
+ * PA7  - SDI                       (alternate 5).
+ * PA8  - PIN8                      (input pullup).
+ * PA9  - VBUS_FS                   (input floating).
+ * PA10 - OTG_FS_ID                 (alternate 10).
+ * PA11 - OTG_FS_DM                 (alternate 10).
+ * PA12 - OTG_FS_DP                 (alternate 10).
+ * PA13 - SWDIO                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_BUTTON) |         \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_ALTERNATE(GPIOA_LRCK) |       \
+                                     PIN_MODE_ALTERNATE(GPIOA_SPC) |        \
+                                     PIN_MODE_ALTERNATE(GPIOA_SDO) |        \
+                                     PIN_MODE_ALTERNATE(GPIOA_SDI) |        \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOA_VBUS_FS) |        \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
+                                     PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_LRCK) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SPC) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SDO) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SDI) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_100M(GPIOA_BUTTON) |        \
+                                     PIN_OSPEED_100M(GPIOA_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOA_LRCK) |          \
+                                     PIN_OSPEED_50M(GPIOA_SPC) |            \
+                                     PIN_OSPEED_50M(GPIOA_SDO) |            \
+                                     PIN_OSPEED_50M(GPIOA_SDI) |            \
+                                     PIN_OSPEED_100M(GPIOA_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOA_VBUS_FS) |       \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_ID) |     \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DM) |     \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DP) |     \
+                                     PIN_OSPEED_100M(GPIOA_SWDIO) |         \
+                                     PIN_OSPEED_100M(GPIOA_SWCLK) |         \
+                                     PIN_OSPEED_100M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_BUTTON) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_LRCK) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_SPC) |        \
+                                     PIN_PUPDR_FLOATING(GPIOA_SDO) |        \
+                                     PIN_PUPDR_FLOATING(GPIOA_SDI) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) |    \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_SWDIO) |      \
+                                     PIN_PUPDR_FLOATING(GPIOA_SWCLK) |      \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_BUTTON) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_LRCK) |             \
+                                     PIN_ODR_HIGH(GPIOA_SPC) |              \
+                                     PIN_ODR_HIGH(GPIOA_SDO) |              \
+                                     PIN_ODR_HIGH(GPIOA_SDI) |              \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOA_VBUS_FS) |          \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_ID) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DP) |        \
+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_BUTTON, 0) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_LRCK, 6) |           \
+                                     PIN_AFIO_AF(GPIOA_SPC, 5) |            \
+                                     PIN_AFIO_AF(GPIOA_SDO, 5) |            \
+                                     PIN_AFIO_AF(GPIOA_SDI, 5))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_VBUS_FS, 0) |        \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - PIN0                      (input pullup).
+ * PB1  - PIN1                      (input pullup).
+ * PB2  - PIN2                      (input pullup).
+ * PB3  - SWO                       (alternate 0).
+ * PB4  - PIN4                      (input pullup).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - SCL                       (alternate 4).
+ * PB7  - PIN7                      (input pullup).
+ * PB8  - PIN8                      (input pullup).
+ * PB9  - SDA                       (alternate 4).
+ * PB10 - CLK_IN                    (input pullup).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - PIN13                     (input pullup).
+ * PB14 - PIN14                     (input pullup).
+ * PB15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SWO) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SCL) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SDA) |        \
+                                     PIN_MODE_INPUT(GPIOB_CLK_IN) |         \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SWO) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_SCL) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_SDA) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_CLK_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_100M(GPIOB_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOB_SWO) |           \
+                                     PIN_OSPEED_100M(GPIOB_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOB_SCL) |           \
+                                     PIN_OSPEED_100M(GPIOB_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOB_SDA) |           \
+                                     PIN_OSPEED_100M(GPIOB_CLK_IN) |        \
+                                     PIN_OSPEED_100M(GPIOB_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_SWO) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_SCL) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_SDA) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_CLK_IN) |       \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_SWO) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_SCL) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_SDA) |              \
+                                     PIN_ODR_HIGH(GPIOB_CLK_IN) |           \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SWO, 0) |            \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SCL, 4) |            \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SDA, 4) |            \
+                                     PIN_AFIO_AF(GPIOB_CLK_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - OTG_FS_POWER_ON           (output pushpull maximum).
+ * PC1  - PIN1                      (input pullup).
+ * PC2  - PIN2                      (input pullup).
+ * PC3  - PDM_OUT                   (input pullup).
+ * PC4  - PIN4                      (input pullup).
+ * PC5  - PIN5                      (input pullup).
+ * PC6  - PIN6                      (input pullup).
+ * PC7  - MCLK                      (alternate 6).
+ * PC8  - PIN8                      (input pullup).
+ * PC9  - PIN9                      (input pullup).
+ * PC10 - SCLK                      (alternate 6).
+ * PC11 - PIN11                     (input pullup).
+ * PC12 - SDIN                      (alternate 6).
+ * PC13 - PIN13                     (input pullup).
+ * PC14 - PIN14                     (input pullup).
+ * PC15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PDM_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_ALTERNATE(GPIOC_MCLK) |       \
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \
+                                     PIN_MODE_ALTERNATE(GPIOC_SCLK) |       \
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
+                                     PIN_MODE_ALTERNATE(GPIOC_SDIN) |       \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_MCLK) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SCLK) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SDIN) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\
+                                     PIN_OSPEED_100M(GPIOC_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOC_PDM_OUT) |       \
+                                     PIN_OSPEED_100M(GPIOC_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOC_MCLK) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOC_SCLK) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOC_SDIN) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) |      \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_MCLK) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN9) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_SCLK) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_SDIN) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOC_PDM_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOC_MCLK) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOC_SCLK) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOC_SDIN) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PDM_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_MCLK, 6))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_SCLK, 6) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_SDIN, 6) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - PIN2                      (input pullup).
+ * PD3  - PIN3                      (input pullup).
+ * PD4  - RESET                     (output pushpull maximum).
+ * PD5  - OVER_CURRENT              (input floating).
+ * PD6  - PIN6                      (input pullup).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - LED4                      (output pushpull maximum).
+ * PD13 - LED3                      (output pushpull maximum).
+ * PD14 - LED5                      (output pushpull maximum).
+ * PD15 - LED6                      (output pushpull maximum).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_OUTPUT(GPIOD_RESET) |         \
+                                     PIN_MODE_INPUT(GPIOD_OVER_CURRENT) |   \
+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_LED4) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_LED3) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_LED5) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_LED6))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_RESET) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LED4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LED3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LED5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LED6))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_100M(GPIOD_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOD_RESET) |         \
+                                     PIN_OSPEED_100M(GPIOD_OVER_CURRENT) |  \
+                                     PIN_OSPEED_100M(GPIOD_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOD_LED4) |          \
+                                     PIN_OSPEED_100M(GPIOD_LED3) |          \
+                                     PIN_OSPEED_100M(GPIOD_LED5) |          \
+                                     PIN_OSPEED_100M(GPIOD_LED6))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_RESET) |      \
+                                     PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_FLOATING(GPIOD_LED4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOD_LED3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOD_LED5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOD_LED6))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_RESET) |            \
+                                     PIN_ODR_HIGH(GPIOD_OVER_CURRENT) |     \
+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_LOW(GPIOD_LED4) |              \
+                                     PIN_ODR_LOW(GPIOD_LED3) |              \
+                                     PIN_ODR_LOW(GPIOD_LED5) |              \
+                                     PIN_ODR_LOW(GPIOD_LED6))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_RESET, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) |   \
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_LED4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_LED3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_LED5, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_LED6, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0  - INT1                      (input floating).
+ * PE1  - INT2                      (input floating).
+ * PE2  - PIN2                      (input floating).
+ * PE3  - CS_SPI                    (output pushpull maximum).
+ * PE4  - PIN4                      (input floating).
+ * PE5  - PIN5                      (input floating).
+ * PE6  - PIN6                      (input floating).
+ * PE7  - PIN7                      (input floating).
+ * PE8  - PIN8                      (input floating).
+ * PE9  - PIN9                      (input floating).
+ * PE10 - PIN10                     (input floating).
+ * PE11 - PIN11                     (input floating).
+ * PE12 - PIN12                     (input floating).
+ * PE13 - PIN13                     (input floating).
+ * PE14 - PIN14                     (input floating).
+ * PE15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_INT1) |           \
+                                     PIN_MODE_INPUT(GPIOE_INT2) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_CS_SPI) |        \
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_INT1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_INT2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_100M(GPIOE_INT1) |          \
+                                     PIN_OSPEED_100M(GPIOE_INT2) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOE_CS_SPI) |        \
+                                     PIN_OSPEED_100M(GPIOE_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_FLOATING(GPIOE_INT1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_INT2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_CS_SPI) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_INT1) |             \
+                                     PIN_ODR_HIGH(GPIOE_INT2) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOE_CS_SPI) |           \
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_INT1, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_INT2, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_CS_SPI, 0) |         \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0  - PIN0                      (input floating).
+ * PF1  - PIN1                      (input floating).
+ * PF2  - PIN2                      (input floating).
+ * PF3  - PIN3                      (input floating).
+ * PF4  - PIN4                      (input floating).
+ * PF5  - PIN5                      (input floating).
+ * PF6  - PIN6                      (input floating).
+ * PF7  - PIN7                      (input floating).
+ * PF8  - PIN8                      (input floating).
+ * PF9  - PIN9                      (input floating).
+ * PF10 - PIN10                     (input floating).
+ * PF11 - PIN11                     (input floating).
+ * PF12 - PIN12                     (input floating).
+ * PF13 - PIN13                     (input floating).
+ * PF14 - PIN14                     (input floating).
+ * PF15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_100M(GPIOF_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0  - PIN0                      (input floating).
+ * PG1  - PIN1                      (input floating).
+ * PG2  - PIN2                      (input floating).
+ * PG3  - PIN3                      (input floating).
+ * PG4  - PIN4                      (input floating).
+ * PG5  - PIN5                      (input floating).
+ * PG6  - PIN6                      (input floating).
+ * PG7  - PIN7                      (input floating).
+ * PG8  - PIN8                      (input floating).
+ * PG9  - PIN9                      (input floating).
+ * PG10 - PIN10                     (input floating).
+ * PG11 - PIN11                     (input floating).
+ * PG12 - PIN12                     (input floating).
+ * PG13 - PIN13                     (input floating).
+ * PG14 - PIN14                     (input floating).
+ * PG15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOG_MODER             (PIN_MODE_INPUT(GPIOG_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_100M(GPIOG_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_FLOATING(GPIOG_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0  - OSC_IN                    (input floating).
+ * PH1  - OSC_OUT                   (input floating).
+ * PH2  - PIN2                      (input floating).
+ * PH3  - PIN3                      (input floating).
+ * PH4  - PIN4                      (input floating).
+ * PH5  - PIN5                      (input floating).
+ * PH6  - PIN6                      (input floating).
+ * PH7  - PIN7                      (input floating).
+ * PH8  - PIN8                      (input floating).
+ * PH9  - PIN9                      (input floating).
+ * PH10 - PIN10                     (input floating).
+ * PH11 - PIN11                     (input floating).
+ * PH12 - PIN12                     (input floating).
+ * PH13 - PIN13                     (input floating).
+ * PH14 - PIN14                     (input floating).
+ * PH15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_100M(GPIOH_OSC_IN) |        \
+                                     PIN_OSPEED_100M(GPIOH_OSC_OUT) |       \
+                                     PIN_OSPEED_100M(GPIOH_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOH_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0  - PIN0                      (input floating).
+ * PI1  - PIN1                      (input floating).
+ * PI2  - PIN2                      (input floating).
+ * PI3  - PIN3                      (input floating).
+ * PI4  - PIN4                      (input floating).
+ * PI5  - PIN5                      (input floating).
+ * PI6  - PIN6                      (input floating).
+ * PI7  - PIN7                      (input floating).
+ * PI8  - PIN8                      (input floating).
+ * PI9  - PIN9                      (input floating).
+ * PI10 - PIN10                     (input floating).
+ * PI11 - PIN11                     (input floating).
+ * PI12 - PIN12                     (input floating).
+ * PI13 - PIN13                     (input floating).
+ * PI14 - PIN14                     (input floating).
+ * PI15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOI_MODER             (PIN_MODE_INPUT(GPIOI_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR           (PIN_OSPEED_100M(GPIOI_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR             (PIN_PUPDR_FLOATING(GPIOI_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR               (PIN_ODR_HIGH(GPIOI_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL              (PIN_AFIO_AF(GPIOI_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH              (PIN_AFIO_AF(GPIOI_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
new file mode 100644
index 000000000..0c11b6fe3
--- /dev/null
+++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F4_DISCOVERY
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg
new file mode 100644
index 000000000..fd1a569c5
--- /dev/null
+++ b/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg
@@ -0,0 +1,1192 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F4xx board Template -->
+<board
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+  <configuration_settings>
+    <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+    <output_path>..</output_path>
+  </configuration_settings>
+  <board_name>STMicroelectronics STM32F4-Discovery</board_name>
+  <board_id>ST_STM32F4_DISCOVERY</board_id>
+  <board_functions></board_functions>
+  <subtype>STM32F40_41xxx</subtype>
+  <clocks
+    HSEFrequency="8000000"
+    HSEBypass="false"
+    LSEFrequency="0"
+    LSEBypass="false"
+    VDD="300" />
+  <ports>
+    <GPIOA>
+      <pin0
+        ID="BUTTON"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID="LRCK"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin5
+        ID="SPC"
+        Type="PushPull"
+        Level="High"
+        Speed="High"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin6
+        ID="SDO"
+        Type="PushPull"
+        Level="High"
+        Speed="High"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin7
+        ID="SDI"
+        Type="PushPull"
+        Level="High"
+        Speed="High"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" ></pin8>
+      <pin9
+        ID="VBUS_FS"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID="OTG_FS_ID"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="10" />
+      <pin11
+        ID="OTG_FS_DM"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="10" />
+      <pin12
+        ID="OTG_FS_DP"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="10" />
+      <pin13
+        ID="SWDIO"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin14
+        ID="SWCLK"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOA>
+    <GPIOB>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="SWO"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="0" ></pin3>
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID="SCL"
+        Type="OpenDrain"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID="SDA"
+        Type="OpenDrain"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="4" ></pin9>
+      <pin10
+        ID="CLK_IN"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOB>
+    <GPIOC>
+      <pin0
+        ID="OTG_FS_POWER_ON"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="PDM_OUT"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" ></pin3>
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID="MCLK"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID="SCLK"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID="SDIN"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOC>
+    <GPIOD>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID="RESET"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin5
+        ID="OVER_CURRENT"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" ></pin5>
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID="LED4"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin13
+        ID="LED3"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin14
+        ID="LED5"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" ></pin14>
+      <pin15
+        ID="LED6"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+    </GPIOD>
+    <GPIOE>
+      <pin0
+        ID="INT1"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="INT2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="CS_SPI"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOE>
+    <GPIOF>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOF>
+    <GPIOG>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOG>
+    <GPIOH>
+      <pin0
+        ID="OSC_IN"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="OSC_OUT"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" ></pin2>
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOH>
+    <GPIOI>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOI>
+  </ports>
+</board>
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/board.c b/os/hal/boards/ST_STM32L_DISCOVERY/board.c
new file mode 100644
index 000000000..684cacdf2
--- /dev/null
+++ b/os/hal/boards/ST_STM32L_DISCOVERY/board.c
@@ -0,0 +1,101 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH}
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/board.h b/os/hal/boards/ST_STM32L_DISCOVERY/board.h
new file mode 100644
index 000000000..efbd86dae
--- /dev/null
+++ b/os/hal/boards/ST_STM32L_DISCOVERY/board.h
@@ -0,0 +1,890 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for ST STM32L-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32L_DISCOVERY
+#define BOARD_NAME                  "ST STM32L-Discovery"
+
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: HSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                0
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header file stm32l1xx.h.
+ */
+#define STM32L1XX_MD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON                0
+#define GPIOA_PIN1                  1
+#define GPIOA_PIN2                  2
+#define GPIOA_PIN3                  3
+#define GPIOA_PIN4                  4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_PIN7                  7
+#define GPIOA_PIN8                  8
+#define GPIOA_PIN9                  9
+#define GPIOA_PIN10                 10
+#define GPIOA_PIN11                 11
+#define GPIOA_PIN12                 12
+#define GPIOA_JTAG_TMS              13
+#define GPIOA_JTAG_TCK              14
+#define GPIOA_JTAG_TDI              15
+
+#define GPIOB_PIN0                  0
+#define GPIOB_PIN1                  1
+#define GPIOB_BOOT1                 2
+#define GPIOB_JTAG_TDO              3
+#define GPIOB_JTAG_TRST             4
+#define GPIOB_PIN5                  5
+#define GPIOB_LED4                  6
+#define GPIOB_LED3                  7
+#define GPIOB_PIN8                  8
+#define GPIOB_PIN9                  9
+#define GPIOB_PIN10                 10
+#define GPIOB_PIN11                 11
+#define GPIOB_PIN12                 12
+#define GPIOB_PIN13                 13
+#define GPIOB_PIN14                 14
+#define GPIOB_PIN15                 15
+
+#define GPIOC_PIN0                  0
+#define GPIOC_PIN1                  1
+#define GPIOC_PIN2                  2
+#define GPIOC_PIN3                  3
+#define GPIOC_PIN4                  4
+#define GPIOC_PIN5                  5
+#define GPIOC_PIN6                  6
+#define GPIOC_PIN7                  7
+#define GPIOC_PIN8                  8
+#define GPIOC_PIN9                  9
+#define GPIOC_PIN10                 10
+#define GPIOC_PIN11                 11
+#define GPIOC_PIN12                 12
+#define GPIOC_PIN13                 13
+#define GPIOC_OSC32_IN              14
+#define GPIOC_OSC32_OUT             15
+
+#define GPIOD_PIN0                  0
+#define GPIOD_PIN1                  1
+#define GPIOD_PIN2                  2
+#define GPIOD_PIN3                  3
+#define GPIOD_PIN4                  4
+#define GPIOD_PIN5                  5
+#define GPIOD_PIN6                  6
+#define GPIOD_PIN7                  7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_PIN11                 11
+#define GPIOD_PIN12                 12
+#define GPIOD_PIN13                 13
+#define GPIOD_PIN14                 14
+#define GPIOD_PIN15                 15
+
+#define GPIOE_PIN0                  0
+#define GPIOE_PIN1                  1
+#define GPIOE_PIN2                  2
+#define GPIOE_PIN3                  3
+#define GPIOE_PIN4                  4
+#define GPIOE_PIN5                  5
+#define GPIOE_PIN6                  6
+#define GPIOE_PIN7                  7
+#define GPIOE_PIN8                  8
+#define GPIOE_PIN9                  9
+#define GPIOE_PIN10                 10
+#define GPIOE_PIN11                 11
+#define GPIOE_PIN12                 12
+#define GPIOE_PIN13                 13
+#define GPIOE_PIN14                 14
+#define GPIOE_PIN15                 15
+
+#define GPIOH_OSC_IN                0
+#define GPIOH_OSC_OUT               1
+#define GPIOH_PIN2                  2
+#define GPIOH_PIN3                  3
+#define GPIOH_PIN4                  4
+#define GPIOH_PIN5                  5
+#define GPIOH_PIN6                  6
+#define GPIOH_PIN7                  7
+#define GPIOH_PIN8                  8
+#define GPIOH_PIN9                  9
+#define GPIOH_PIN10                 10
+#define GPIOH_PIN11                 11
+#define GPIOH_PIN12                 12
+#define GPIOH_PIN13                 13
+#define GPIOH_PIN14                 14
+#define GPIOH_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_400K(n)          (0U << ((n) * 2))
+#define PIN_OSPEED_2M(n)            (1U << ((n) * 2))
+#define PIN_OSPEED_10M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_40M(n)           (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - BUTTON                    (input floating).
+ * PA1  - PIN1                      (input pullup).
+ * PA2  - PIN2                      (input pullup).
+ * PA3  - PIN3                      (input pullup).
+ * PA4  - PIN4                      (input pullup).
+ * PA5  - PIN5                      (input pullup).
+ * PA6  - PIN6                      (input pullup).
+ * PA7  - PIN7                      (input pullup).
+ * PA8  - PIN8                      (input pullup).
+ * PA9  - PIN9                      (input pullup).
+ * PA10 - PIN10                     (input pullup).
+ * PA11 - PIN11                     (input pullup).
+ * PA12 - PIN12                     (input pullup).
+ * PA13 - JTAG_TMS                  (alternate 0).
+ * PA14 - JTAG_TCK                  (alternate 0).
+ * PA15 - JTAG_TDI                  (alternate 0).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_BUTTON) |         \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOA_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOA_PIN12) |          \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) |   \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) |   \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_400K(GPIOA_BUTTON) |        \
+                                     PIN_OSPEED_400K(GPIOA_PIN1) |          \
+                                     PIN_OSPEED_400K(GPIOA_PIN2) |          \
+                                     PIN_OSPEED_400K(GPIOA_PIN3) |          \
+                                     PIN_OSPEED_400K(GPIOA_PIN4) |          \
+                                     PIN_OSPEED_400K(GPIOA_PIN5) |          \
+                                     PIN_OSPEED_400K(GPIOA_PIN6) |          \
+                                     PIN_OSPEED_400K(GPIOA_PIN7) |          \
+                                     PIN_OSPEED_400K(GPIOA_PIN8) |          \
+                                     PIN_OSPEED_400K(GPIOA_PIN9) |          \
+                                     PIN_OSPEED_400K(GPIOA_PIN10) |         \
+                                     PIN_OSPEED_400K(GPIOA_PIN11) |         \
+                                     PIN_OSPEED_400K(GPIOA_PIN12) |         \
+                                     PIN_OSPEED_40M(GPIOA_JTAG_TMS) |       \
+                                     PIN_OSPEED_40M(GPIOA_JTAG_TCK) |       \
+                                     PIN_OSPEED_40M(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_BUTTON) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_JTAG_TMS) |     \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) |   \
+                                     PIN_PUPDR_PULLUP(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_BUTTON) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOA_JTAG_TMS) |         \
+                                     PIN_ODR_HIGH(GPIOA_JTAG_TCK) |         \
+                                     PIN_ODR_HIGH(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_BUTTON, 0) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN7, 0))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) |       \
+                                     PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) |       \
+                                     PIN_AFIO_AF(GPIOA_JTAG_TDI, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - PIN0                      (input pullup).
+ * PB1  - PIN1                      (input pullup).
+ * PB2  - BOOT1                     (input floating).
+ * PB3  - JTAG_TDO                  (alternate 0).
+ * PB4  - JTAG_TRST                 (alternate 0).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - LED4                      (output pushpull maximum).
+ * PB7  - LED3                      (output pushpull maximum).
+ * PB8  - PIN8                      (input pullup).
+ * PB9  - PIN9                      (input pullup).
+ * PB10 - PIN10                     (input pullup).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - PIN13                     (input pullup).
+ * PB14 - PIN14                     (input pullup).
+ * PB15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_BOOT1) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) |  \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_OUTPUT(GPIOB_LED4) |          \
+                                     PIN_MODE_OUTPUT(GPIOB_LED3) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_LED4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_LED3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_400K(GPIOB_PIN0) |          \
+                                     PIN_OSPEED_400K(GPIOB_PIN1) |          \
+                                     PIN_OSPEED_40M(GPIOB_BOOT1) |          \
+                                     PIN_OSPEED_40M(GPIOB_JTAG_TDO) |       \
+                                     PIN_OSPEED_40M(GPIOB_JTAG_TRST) |      \
+                                     PIN_OSPEED_400K(GPIOB_PIN5) |          \
+                                     PIN_OSPEED_40M(GPIOB_LED4) |           \
+                                     PIN_OSPEED_40M(GPIOB_LED3) |           \
+                                     PIN_OSPEED_400K(GPIOB_PIN8) |          \
+                                     PIN_OSPEED_400K(GPIOB_PIN9) |          \
+                                     PIN_OSPEED_400K(GPIOB_PIN10) |         \
+                                     PIN_OSPEED_400K(GPIOB_PIN11) |         \
+                                     PIN_OSPEED_400K(GPIOB_PIN12) |         \
+                                     PIN_OSPEED_400K(GPIOB_PIN13) |         \
+                                     PIN_OSPEED_400K(GPIOB_PIN14) |         \
+                                     PIN_OSPEED_400K(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_BOOT1) |      \
+                                     PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) |   \
+                                     PIN_PUPDR_PULLUP(GPIOB_JTAG_TRST) |    \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_LED4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOB_LED3) |       \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOB_BOOT1) |            \
+                                     PIN_ODR_HIGH(GPIOB_JTAG_TDO) |         \
+                                     PIN_ODR_HIGH(GPIOB_JTAG_TRST) |        \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_LOW(GPIOB_LED4) |              \
+                                     PIN_ODR_LOW(GPIOB_LED3) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_BOOT1, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) |       \
+                                     PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) |      \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_LED4, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_LED3, 0))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - PIN0                      (input pullup).
+ * PC1  - PIN1                      (input pullup).
+ * PC2  - PIN2                      (input pullup).
+ * PC3  - PIN3                      (input pullup).
+ * PC4  - PIN4                      (input pullup).
+ * PC5  - PIN5                      (input pullup).
+ * PC6  - PIN6                      (input pullup).
+ * PC7  - PIN7                      (input pullup).
+ * PC8  - PIN8                      (input pullup).
+ * PC9  - PIN9                      (input pullup).
+ * PC10 - PIN10                     (input pullup).
+ * PC11 - PIN11                     (input pullup).
+ * PC12 - PIN12                     (input pullup).
+ * PC13 - PIN13                     (input pullup).
+ * PC14 - OSC32_IN                  (input floating).
+ * PC15 - OSC32_OUT                 (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_400K(GPIOC_PIN0) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN1) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN2) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN3) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN4) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN5) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN6) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN7) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN8) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN9) |          \
+                                     PIN_OSPEED_400K(GPIOC_PIN10) |         \
+                                     PIN_OSPEED_400K(GPIOC_PIN11) |         \
+                                     PIN_OSPEED_400K(GPIOC_PIN12) |         \
+                                     PIN_OSPEED_400K(GPIOC_PIN13) |         \
+                                     PIN_OSPEED_40M(GPIOC_OSC32_IN) |       \
+                                     PIN_OSPEED_40M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0) |       \
+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - PIN2                      (input pullup).
+ * PD3  - PIN3                      (input pullup).
+ * PD4  - PIN4                      (input pullup).
+ * PD5  - PIN5                      (input pullup).
+ * PD6  - PIN6                      (input pullup).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - PIN12                     (input pullup).
+ * PD13 - PIN13                     (input pullup).
+ * PD14 - PIN14                     (input pullup).
+ * PD15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_400K(GPIOD_PIN0) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN1) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN2) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN3) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN4) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN5) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN6) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN7) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN8) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN9) |          \
+                                     PIN_OSPEED_400K(GPIOD_PIN10) |         \
+                                     PIN_OSPEED_400K(GPIOD_PIN11) |         \
+                                     PIN_OSPEED_400K(GPIOD_PIN12) |         \
+                                     PIN_OSPEED_400K(GPIOD_PIN13) |         \
+                                     PIN_OSPEED_400K(GPIOD_PIN14) |         \
+                                     PIN_OSPEED_400K(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0  - PIN0                      (input pullup).
+ * PE1  - PIN1                      (input pullup).
+ * PE2  - PIN2                      (input pullup).
+ * PE3  - PIN3                      (input pullup).
+ * PE4  - PIN4                      (input pullup).
+ * PE5  - PIN5                      (input pullup).
+ * PE6  - PIN6                      (input pullup).
+ * PE7  - PIN7                      (input pullup).
+ * PE8  - PIN8                      (input pullup).
+ * PE9  - PIN9                      (input pullup).
+ * PE10 - PIN10                     (input pullup).
+ * PE11 - PIN11                     (input pullup).
+ * PE12 - PIN12                     (input pullup).
+ * PE13 - PIN13                     (input pullup).
+ * PE14 - PIN14                     (input pullup).
+ * PE15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_400K(GPIOE_PIN0) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN1) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN2) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN3) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN4) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN5) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN6) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN7) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN8) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN9) |          \
+                                     PIN_OSPEED_400K(GPIOE_PIN10) |         \
+                                     PIN_OSPEED_400K(GPIOE_PIN11) |         \
+                                     PIN_OSPEED_400K(GPIOE_PIN12) |         \
+                                     PIN_OSPEED_400K(GPIOE_PIN13) |         \
+                                     PIN_OSPEED_400K(GPIOE_PIN14) |         \
+                                     PIN_OSPEED_400K(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_PULLUP(GPIOE_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0  - OSC_IN                    (input floating).
+ * PH1  - OSC_OUT                   (input floating).
+ * PH2  - PIN2                      (input pullup).
+ * PH3  - PIN3                      (input pullup).
+ * PH4  - PIN4                      (input pullup).
+ * PH5  - PIN5                      (input pullup).
+ * PH6  - PIN6                      (input pullup).
+ * PH7  - PIN7                      (input pullup).
+ * PH8  - PIN8                      (input pullup).
+ * PH9  - PIN9                      (input pullup).
+ * PH10 - PIN10                     (input pullup).
+ * PH11 - PIN11                     (input pullup).
+ * PH12 - PIN12                     (input pullup).
+ * PH13 - PIN13                     (input pullup).
+ * PH14 - PIN14                     (input pullup).
+ * PH15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_40M(GPIOH_OSC_IN) |         \
+                                     PIN_OSPEED_40M(GPIOH_OSC_OUT) |        \
+                                     PIN_OSPEED_400K(GPIOH_PIN2) |          \
+                                     PIN_OSPEED_400K(GPIOH_PIN3) |          \
+                                     PIN_OSPEED_400K(GPIOH_PIN4) |          \
+                                     PIN_OSPEED_400K(GPIOH_PIN5) |          \
+                                     PIN_OSPEED_400K(GPIOH_PIN6) |          \
+                                     PIN_OSPEED_400K(GPIOH_PIN7) |          \
+                                     PIN_OSPEED_400K(GPIOH_PIN8) |          \
+                                     PIN_OSPEED_400K(GPIOH_PIN9) |          \
+                                     PIN_OSPEED_400K(GPIOH_PIN10) |         \
+                                     PIN_OSPEED_400K(GPIOH_PIN11) |         \
+                                     PIN_OSPEED_400K(GPIOH_PIN12) |         \
+                                     PIN_OSPEED_400K(GPIOH_PIN13) |         \
+                                     PIN_OSPEED_400K(GPIOH_PIN14) |         \
+                                     PIN_OSPEED_400K(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOH_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/board.mk b/os/hal/boards/ST_STM32L_DISCOVERY/board.mk
new file mode 100644
index 000000000..5726178cb
--- /dev/null
+++ b/os/hal/boards/ST_STM32L_DISCOVERY/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32L_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32L_DISCOVERY
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg
new file mode 100644
index 000000000..b0c6406f7
--- /dev/null
+++ b/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg
@@ -0,0 +1,801 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32L1xx board Template -->
+<board
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32l1xx_board.xsd">
+  <configuration_settings>
+    <templates_path>resources/gencfg/processors/boards/stm32l1xx/templates</templates_path>
+    <output_path>..</output_path>
+  </configuration_settings>
+  <board_name>ST STM32L-Discovery</board_name>
+  <board_id>ST_STM32L_DISCOVERY</board_id>
+  <board_functions></board_functions>
+  <clocks
+     HSEFrequency="0"
+     HSEBypass="true"
+     LSEFrequency="32768"
+     LSEBypass="false"
+  />
+  <ports>
+    <GPIOA>
+      <pin0
+        ID="BUTTON"
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin1>
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" ></pin4>
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID="JTAG_TMS"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin14
+        ID="JTAG_TCK"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin15
+        ID="JTAG_TDI"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+    </GPIOA>
+    <GPIOB>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID="BOOT1"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="JTAG_TDO"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin4
+        ID="JTAG_TRST"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID="LED4"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin7
+        ID="LED3"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="Low"
+        Mode="Output"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOB>
+    <GPIOC>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID="OSC32_IN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID="OSC32_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOC>
+    <GPIOD>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOD>
+    <GPIOE>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOE>
+    <GPIOH>
+      <pin0
+        ID="OSC_IN"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0"></pin0>
+      <pin1
+        ID="OSC_OUT"
+        Type="PushPull"
+        Speed="Maximum"
+        Resistor="Floating"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Speed="Minimum"
+        Resistor="PullUp"
+        Level="High"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOH>
+  </ports>
+</board>
diff --git a/os/hal/boards/ST_STM32VL_DISCOVERY/board.c b/os/hal/boards/ST_STM32VL_DISCOVERY/board.c
new file mode 100644
index 000000000..bd21d1738
--- /dev/null
+++ b/os/hal/boards/ST_STM32VL_DISCOVERY/board.c
@@ -0,0 +1,49 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32VL_DISCOVERY/board.h b/os/hal/boards/ST_STM32VL_DISCOVERY/board.h
new file mode 100644
index 000000000..36e157d48
--- /dev/null
+++ b/os/hal/boards/ST_STM32VL_DISCOVERY/board.h
@@ -0,0 +1,143 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32VL-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32VL_DISCOVERY
+#define BOARD_NAME              "ST STM32VL-Discovery"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD_VL
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON            0
+#define GPIOA_SPI1NSS           4
+
+#define GPIOB_SPI2NSS           12
+
+#define GPIOC_LED4              8
+#define GPIOC_LED3              9
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0  - Normal input      (BUTTON).
+ * PA2  - Alternate output  (USART2 TX).
+ * PA3  - Normal input      (USART2 RX).
+ * PA4  - Push pull output  (SPI1 NSS), initially high state.
+ * PA5  - Alternate output  (SPI1 SCK).
+ * PA6  - Normal input      (SPI1 MISO).
+ * PA7  - Alternate output  (SPI1 MOSI).
+ * PA9  - Alternate output  (USART1 TX).
+ * PA10 - Normal input      (USART1 RX).
+ */
+#define VAL_GPIOACRL            0xB4B34B84      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x888884B8      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB12 - Push pull output  (SPI2 NSS), initially high state.
+ * PB13 - Alternate output  (SPI2 SCK).
+ * PB14 - Normal input      (SPI2 MISO).
+ * PB15 - Alternate output  (SPI2 MOSI).
+ */
+#define VAL_GPIOBCRL            0x88888888      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0xB4B38888      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC8  - Push-pull output (LED4), initially low state.
+ * PC9  - Push-pull output (LED3), initially low state.
+ */
+#define VAL_GPIOCCRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x88888833      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFCFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0  - Normal input (XTAL).
+ * PD1  - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL            0x88888844      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x88888888      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x88888888      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32VL_DISCOVERY/board.mk b/os/hal/boards/ST_STM32VL_DISCOVERY/board.mk
new file mode 100644
index 000000000..e165b3523
--- /dev/null
+++ b/os/hal/boards/ST_STM32VL_DISCOVERY/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32VL_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32VL_DISCOVERY
diff --git a/os/hal/boards/ST_STM8L_DISCOVERY/board.c b/os/hal/boards/ST_STM8L_DISCOVERY/board.c
new file mode 100644
index 000000000..9331b6f37
--- /dev/null
+++ b/os/hal/boards/ST_STM8L_DISCOVERY/board.c
@@ -0,0 +1,61 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+ROMCONST PALConfig pal_default_config =
+{
+  {
+    {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2},
+    {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
+    {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
+    {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
+    {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
+    {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
+  }
+};
+#endif
+
+/*
+ * TIM 2 clock after the prescaler.
+ */
+#define TIM2_CLOCK  (SYSCLK / 16)
+#define TIM2_ARR    ((TIM2_CLOCK / CH_FREQUENCY) - 1)
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * TIM2 initialization as system tick.
+   */
+  CLK->PCKENR1 |= CLK_PCKENR1_TIM2;
+  TIM2->PSCR    = 4;            /* Prescaler divide by 2^4=16.*/
+  TIM2->ARRH    = (uint8_t)(TIM2_ARR >> 8);
+  TIM2->ARRL    = (uint8_t)(TIM2_ARR);
+  TIM2->CNTRH   = 0;
+  TIM2->CNTRL   = 0;
+  TIM2->SR1     = 0;
+  TIM2->IER     = TIM_IER_UIE;
+  TIM2->CR1     = TIM_CR1_CEN;
+}
diff --git a/os/hal/boards/ST_STM8L_DISCOVERY/board.h b/os/hal/boards/ST_STM8L_DISCOVERY/board.h
new file mode 100644
index 000000000..907279ee7
--- /dev/null
+++ b/os/hal/boards/ST_STM8L_DISCOVERY/board.h
@@ -0,0 +1,167 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM8L-Discovery board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_ST_STM8L_DISCOVERY
+#define BOARD_NAME          "ST STM8L-Discovery"
+
+/*
+ * Board frequencies and bypass modes.
+ *
+ * The bypass must be set to TRUE if the chip is driven by an external
+ * oscillator rather than a crystal. Frequency must be set to zero if
+ * the clock source is not used at all.
+ * The following constants are used by the HAL low level driver for
+ * correct clock initialization.
+ */
+#define HSECLK              0
+#define HSEBYPASS           FALSE
+#define LSECLK              32768
+#define LSEBYPASS           FALSE
+
+/*
+ * MCU model used on the board.
+ */
+#define STM8L152C6
+#define STM8L15X_MD
+
+/*
+ * Pin definitions.
+ */
+#define PA_OSC_IN           2
+#define PA_OSC_OUT          3
+#define PA_LCD_COM0         4
+#define PA_LCD_COM1         5
+#define PA_LCD_COM2         6
+#define PA_LCD_SEG0         7
+
+#define PB_LCD_SEG10        0
+#define PB_LCD_SEG11        1
+#define PB_LCD_SEG12        2
+#define PB_LCD_SEG13        3
+#define PB_LCD_SEG14        4
+#define PB_LCD_SEG15        5
+#define PB_LCD_SEG16        6
+#define PB_LCD_SEG17        7
+
+#define PC_UNUSED           0
+#define PC_BUTTON           1
+#define PC_LCD_SEG22        2
+#define PC_LCD_SEG23        3
+#define PC_IDD_CNT_EN       4
+#define PC_LED4             7
+
+#define PD_LCD_SEG7         0
+#define PD_LCD_COM3         1
+#define PD_LCD_SEG8         2
+#define PD_LCD_SEG9         3
+#define PD_LCD_SEG18        4
+#define PD_LCD_SEG19        5
+#define PD_LCD_SEG20        6
+#define PD_LCD_SEG21        7
+
+#define PE_LCD_SEG1         0
+#define PE_LCD_SEG2         1
+#define PE_LCD_SEG3         2
+#define PE_LCD_SEG4         3
+#define PE_LCD_SEG5         4
+#define PE_LCD_SEG6         5
+#define PE_IDD_WAKEUP       6
+#define PE_LED3             7
+
+#define PF0_IDD_MEASUREMENT 0
+
+/*
+ * Port A initial setup.
+ */
+#define VAL_GPIOAODR        0
+#define VAL_GPIOADDR        0               /* All inputs.                  */
+#define VAL_GPIOACR1        0xFF            /* All pull-up/push-pull.       */
+#define VAL_GPIOACR2        0
+
+/*
+ * Port B initial setup.
+ */
+#define VAL_GPIOBODR        0
+#define VAL_GPIOBDDR        0               /* All inputs.                  */
+#define VAL_GPIOBCR1        0xFF            /* All pull-up/push-pull.       */
+#define VAL_GPIOBCR2        0
+
+/*
+ * Port C initial setup.
+ */
+#define VAL_GPIOCODR        0
+#define VAL_GPIOCDDR        (1 << PC_LED4)
+#define VAL_GPIOCCR1        0xFF            /* All pull-up/push-pull.       */
+#define VAL_GPIOCCR2        0
+
+/*
+ * Port D initial setup.
+ */
+#define VAL_GPIODODR        0
+#define VAL_GPIODDDR        0               /* All inputs.                  */
+#define VAL_GPIODCR1        0xFF            /* All pull-up/push-pull.       */
+#define VAL_GPIODCR2        0
+
+/*
+ * Port E initial setup.
+ */
+#define VAL_GPIOEODR        0
+#define VAL_GPIOEDDR        (1 << PE_LED3)
+#define VAL_GPIOECR1        0xFF            /* All pull-up/push-pull.       */
+#define VAL_GPIOECR2        0
+
+/*
+ * Port F initial setup.
+ */
+#define VAL_GPIOFODR        0
+#define VAL_GPIOFDDR        0               /* All inputs.                  */
+#define VAL_GPIOFCR1        0xFF            /* All pull-up/push-pull.       */
+#define VAL_GPIOFCR2        0
+
+/*
+ * TIM2-update ISR segment code. This code is injected into the appropriate
+ * ISR by the HAL.
+ */
+#define _TIM2_UPDATE_ISR() {                                                \
+  if (TIM2->SR1 & TIM_SR1_UIF) {                                            \
+    chSysLockFromIsr();                                                     \
+    chSysTimerHandlerI();                                                   \
+    chSysUnlockFromIsr();                                                   \
+    TIM2->SR1 = 0;                                                          \
+  }                                                                         \
+}
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM8S_DISCOVERY/board.c b/os/hal/boards/ST_STM8S_DISCOVERY/board.c
new file mode 100644
index 000000000..ee9c9d32f
--- /dev/null
+++ b/os/hal/boards/ST_STM8S_DISCOVERY/board.c
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+ROMCONST PALConfig pal_default_config =
+{
+  {
+    {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2},
+    {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
+    {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
+    {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
+    {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
+    {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
+    {VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
+  }
+};
+#endif
+
+/*
+ * TIM 2 clock after the prescaler.
+ */
+#define TIM2_CLOCK  (SYSCLK / 16)
+#define TIM2_ARR    ((TIM2_CLOCK / CH_FREQUENCY) - 1)
+
+/*
+ * TIM2 interrupt handler.
+ */
+CH_IRQ_HANDLER(13) {
+
+  CH_IRQ_PROLOGUE();
+
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+
+  TIM2->SR1 = 0;
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+  /*
+   * TIM2 initialization as system tick.
+   */
+  CLK->PCKENR1 |= CLK_PCKENR1_TIM2;
+  TIM2->PSCR    = 4;            /* Prescaler divide by 2^4=16.*/
+  TIM2->ARRH    = (uint8_t)(TIM2_ARR >> 8);
+  TIM2->ARRL    = (uint8_t)(TIM2_ARR);
+  TIM2->CNTRH   = 0;
+  TIM2->CNTRL   = 0;
+  TIM2->SR1     = 0;
+  TIM2->IER     = TIM2_IER_UIE;
+  TIM2->CR1     = TIM2_CR1_CEN;
+}
diff --git a/os/hal/boards/ST_STM8S_DISCOVERY/board.h b/os/hal/boards/ST_STM8S_DISCOVERY/board.h
new file mode 100644
index 000000000..70e8682da
--- /dev/null
+++ b/os/hal/boards/ST_STM8S_DISCOVERY/board.h
@@ -0,0 +1,121 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM8S-Discovery board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_ST_STM8S_DISCOVERY
+#define BOARD_NAME      "ST STM8S-Discovery"
+
+/*
+ * Board frequencies.
+ */
+#define HSECLK          16000000
+
+/*
+ * MCU model used on the board.
+ */
+#define STM8S105
+
+/*
+ * Pin definitions.
+ */
+#define PA_OSCIN        1
+#define PA_OSCOUT       2
+
+#define PC_TS_KEY       1
+#define PC_TS_LOADREF   2
+#define PC_TS_SHIELD    3
+
+#define PD_LD10         0
+#define PD_SWIM         1
+#define PD_TX           5
+#define PD_RX           6
+
+/*
+ * Port A initial setup.
+ */
+#define VAL_GPIOAODR    0
+#define VAL_GPIOADDR    0               /* All inputs.                      */
+#define VAL_GPIOACR1    0xFF            /* All pull-up or push-pull.        */
+#define VAL_GPIOACR2    0
+
+/*
+ * Port B initial setup.
+ */
+#define VAL_GPIOBODR    0
+#define VAL_GPIOBDDR    0               /* All inputs.                      */
+#define VAL_GPIOBCR1    0xFF            /* All push-pull.                   */
+#define VAL_GPIOBCR2    0
+
+/*
+ * Port C initial setup.
+ */
+#define VAL_GPIOCODR    0
+#define VAL_GPIOCDDR    0               /* All inputs.                      */
+#define VAL_GPIOCCR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIOCCR2    0
+
+/*
+ * Port D initial setup.
+ */
+#define VAL_GPIODODR    (1 << PD_LD10) | (1 << PD_TX)
+#define VAL_GPIODDDR    (1 << PD_LD10) | (1 << PD_TX)
+#define VAL_GPIODCR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIODCR2    0
+
+/*
+ * Port E initial setup.
+ */
+#define VAL_GPIOEODR    0 
+#define VAL_GPIOEDDR    0               /* All inputs.                      */
+#define VAL_GPIOECR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIOECR2    0
+
+/*
+ * Port F initial setup.
+ */
+#define VAL_GPIOFODR    0
+#define VAL_GPIOFDDR    0               /* All inputs.                      */
+#define VAL_GPIOFCR1    0xFF            /* All pull-up.                     */
+#define VAL_GPIOFCR2    0
+
+/*
+ * Port G initial setup.
+ */
+#define VAL_GPIOGODR    0
+#define VAL_GPIOGDDR    0               /* All inputs.                      */
+#define VAL_GPIOGCR1    0xFF            /* All pull-up or push-pull.        */
+#define VAL_GPIOGCR2    0
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/readme.txt b/os/hal/boards/readme.txt
new file mode 100644
index 000000000..b08a21bfb
--- /dev/null
+++ b/os/hal/boards/readme.txt
@@ -0,0 +1,6 @@
+This directory contains the support files for various board models. If you
+want to support a new board:
+- Create a new directory under ./boards, give it the name of your board.
+- Copy inside the new directory the files from a similar board.
+- Customize board.c, board.h and board.mk in order to correctly initialize
+  your board.
diff --git a/os/hal/boards/simulator/board.c b/os/hal/boards/simulator/board.c
new file mode 100644
index 000000000..6bc4be78d
--- /dev/null
+++ b/os/hal/boards/simulator/board.c
@@ -0,0 +1,34 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {0, 0, 0},
+ {0, 0, 0}
+};
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/simulator/board.h b/os/hal/boards/simulator/board.h
new file mode 100644
index 000000000..ee9b14e73
--- /dev/null
+++ b/os/hal/boards/simulator/board.h
@@ -0,0 +1,30 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/simulator/board.mk b/os/hal/boards/simulator/board.mk
new file mode 100644
index 000000000..53df6209f
--- /dev/null
+++ b/os/hal/boards/simulator/board.mk
@@ -0,0 +1,5 @@
+# List of all the simulator board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/simulator/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/simulator
diff --git a/os/hal/dox/adc.dox b/os/hal/dox/adc.dox
deleted file mode 100644
index 8ac1cb556..000000000
--- a/os/hal/dox/adc.dox
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup ADC ADC Driver
- * @brief Generic ADC Driver.
- * @details This module implements a generic ADC (Analog to Digital Converter)
- *          driver supporting a variety of buffer and conversion modes.
- * @pre     In order to use the ADC driver the @p HAL_USE_ADC option
- *          must be enabled in @p halconf.h.
- *
- * @section adc_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
-  digraph example {
-    rankdir="LR";
-    size="5, 7";
-
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop  [label="ADC_STOP\nLow Power"];
-    uninit [label="ADC_UNINIT", style="bold"];
-    ready [label="ADC_READY\nClock Enabled"];
-    active [label="ADC_ACTIVE\nConverting"];
-    error [label="ADC_ERROR\nError"];
-    complete [label="ADC_COMPLETE\nComplete"];
-
-    uninit -> stop [label="\n adcInit()", constraint=false];
-    stop -> ready [label="\nadcStart()"];
-    ready -> ready [label="\nadcStart()\nadcStopConversion()"];
-    ready -> stop [label="\nadcStop()"];
-    stop -> stop [label="\nadcStop()"];
-    ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"];
-    active -> ready [label="\nadcStopConversion()\nsync return"];
-    active -> active [label="\nasync callback (half buffer, circular)\nasync callback (full buffer)\n>acg_endcb<"];
-    active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"];
-    active -> error [label="\n\nasync callback (error)\n>error_cb<"];
-    complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"];
-    complete -> ready [label="\ncallback return"];
-    error -> active [label="\nadcStartConversionI()\nthen\ncallback return"];
-    error -> ready [label="\ncallback return"];
-  }
- * @enddot
- * @else
- * @dot
-  digraph example {
-    rankdir="LR";
-
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop  [label="ADC_STOP\nLow Power"];
-    uninit [label="ADC_UNINIT", style="bold"];
-    ready [label="ADC_READY\nClock Enabled"];
-    active [label="ADC_ACTIVE\nConverting"];
-    error [label="ADC_ERROR\nError"];
-    complete [label="ADC_COMPLETE\nComplete"];
-
-    uninit -> stop [label="\n adcInit()", constraint=false];
-    stop -> ready [label="\nadcStart()"];
-    ready -> ready [label="\nadcStart()\nadcStopConversion()"];
-    ready -> stop [label="\nadcStop()"];
-    stop -> stop [label="\nadcStop()"];
-    ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"];
-    active -> ready [label="\nadcStopConversion()\nsync return"];
-    active -> active [label="\nasync callback (half buffer, circular)\nasync callback (full buffer)\n>acg_endcb<"];
-    active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"];
-    active -> error [label="\n\nasync callback (error)\n>error_cb<"];
-    complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"];
-    complete -> ready [label="\ncallback return"];
-    error -> active [label="\nadcStartConversionI()\nthen\ncallback return"];
-    error -> ready [label="\ncallback return"];
-  }
- * @enddot
- * @endif
- *
- * @section adc_2 ADC Operations
- * The ADC driver is quite complex, an explanation of the terminology and of
- * the operational details follows.
- *
- * @subsection adc_2_1 ADC Conversion Groups
- * The @p ADCConversionGroup is the objects that specifies a physical
- * conversion operation. This structure contains some standard fields and
- * several implementation-dependent fields.<br>
- * The standard fields define the CG mode, the number of channels belonging
- * to the CG and the optional callbacks.<br>
- * The implementation-dependent fields specify the physical ADC operation
- * mode, the analog channels belonging to the group and any other
- * implementation-specific setting. Usually the extra fields just mirror
- * the physical ADC registers, please refer to the vendor's MCU Reference
- * Manual for details about the available settings. Details are also available
- * into the documentation of the ADC low level drivers and in the various
- * sample applications.
- *
- * @subsection adc_2_2 ADC Conversion Modes
- * The driver supports several conversion modes:
- * - <b>One Shot</b>, the driver performs a single group conversion then stops.
- * - <b>Linear Buffer</b>, the driver performs a series of group conversions
- *   then stops. This mode is like a one shot conversion repeated N times,
- *   the buffer pointer increases after each conversion. The buffer is
- *   organized as an S(CG)*N samples matrix, when S(CG) is the conversion
- *   group size (number of channels) and N is the buffer depth (number of
- *   repeated conversions).
- * - <b>Circular Buffer</b>, much like the linear mode but the operation does
- *   not stop when the buffer is filled, it is automatically restarted
- *   with the buffer pointer wrapping back to the buffer base.
- * .
- * @subsection adc_2_3 ADC Callbacks
- * The driver is able to invoke callbacks during the conversion process. A
- * callback is invoked when the operation has been completed or, in circular
- * mode, when the buffer has been filled and the operation is restarted. In
- * circular mode a callback is also invoked when the buffer is half filled.<br>
- * The "half filled" and "filled" callbacks in circular mode allow to
- * implement "streaming processing" of the sampled data, while the driver is
- * busy filling one half of the buffer the application can process the
- * other half, this allows for continuous interleaved operations.
- *
- * The driver is not thread safe for performance reasons, if you need to access
- * the ADC bus from multiple threads then use the @p adcAcquireBus() and
- * @p adcReleaseBus() APIs in order to gain exclusive access.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/can.dox b/os/hal/dox/can.dox
deleted file mode 100644
index e4a0d47a3..000000000
--- a/os/hal/dox/can.dox
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup CAN CAN Driver
- * @brief Generic CAN Driver.
- * @details This module implements a generic CAN (Controller Area Network)
- *          driver allowing the exchange of information at frame level.
- * @pre     In order to use the CAN driver the @p HAL_USE_CAN option
- *          must be enabled in @p halconf.h.
- *
- * @section can_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
-  digraph example {
-    size="5, 7";
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop  [label="CAN_STOP\nLow Power"];
-    uninit [label="CAN_UNINIT", style="bold"];
-    starting [label="CAN_STARTING\nInitializing"];
-    ready [label="CAN_READY\nClock Enabled"];
-    sleep [label="CAN_SLEEP\nLow Power"];
-
-    uninit -> stop [label=" canInit()", constraint=false];
-    stop -> stop [label="\ncanStop()"];
-    stop -> ready [label="\ncanStart()\n(fast implementation)"];
-    stop -> starting [label="\ncanStart()\n(slow implementation)"];
-    starting -> starting [label="\ncanStart()\n(other thread)"];
-    starting -> ready [label="\ninitialization complete\n(all threads)"];
-    ready -> stop [label="\ncanStop()"];
-    ready -> ready [label="\ncanStart()\ncanReceive()\ncanTransmit()"];
-    ready -> sleep [label="\ncanSleep()"];
-    sleep -> sleep [label="\ncanSleep()"];
-    sleep -> ready [label="\ncanWakeup()"];
-    sleep -> ready [label="\nhardware\nwakeup event"];
-  }
- * @enddot
- * @else
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop  [label="CAN_STOP\nLow Power"];
-    uninit [label="CAN_UNINIT", style="bold"];
-    starting [label="CAN_STARTING\nInitializing"];
-    ready [label="CAN_READY\nClock Enabled"];
-    sleep [label="CAN_SLEEP\nLow Power"];
-
-    uninit -> stop [label=" canInit()", constraint=false];
-    stop -> stop [label="\ncanStop()"];
-    stop -> ready [label="\ncanStart()\n(fast implementation)"];
-    stop -> starting [label="\ncanStart()\n(slow implementation)"];
-    starting -> starting [label="\ncanStart()\n(other thread)"];
-    starting -> ready [label="\ninitialization complete\n(all threads)"];
-    ready -> stop [label="\ncanStop()"];
-    ready -> ready [label="\ncanStart()\ncanReceive()\ncanTransmit()"];
-    ready -> sleep [label="\ncanSleep()"];
-    sleep -> sleep [label="\ncanSleep()"];
-    sleep -> ready [label="\ncanWakeup()"];
-    sleep -> ready [label="\nhardware\nwakeup event"];
-  }
- * @enddot
- * @endif
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/ext.dox b/os/hal/dox/ext.dox
deleted file mode 100644
index 904c63f08..000000000
--- a/os/hal/dox/ext.dox
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup EXT EXT Driver
- * @brief   Generic EXT Driver.
- * @details This module implements a generic EXT (EXTernal) driver.
- * @pre     In order to use the EXT driver the @p HAL_USE_EXT option
- *          must be enabled in @p halconf.h.
- *
- * @section ext_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
-  digraph example {
-    size="5, 7";
-    rankdir="LR";
-
-    node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Sans, fontsize=8];
-
-    uninit [label="EXT_UNINIT", style="bold"];
-    stop  [label="EXT_STOP\nLow Power"];
-    active [label="EXT_ACTIVE"];
-
-    uninit -> stop [label="extInit()"];
-    stop -> stop [label="\nextStop()"];
-    stop -> active [label="\nextStart()"];
-    active -> stop [label="\nextStop()"];
-    active -> active [label="\nextStart()"];
-  }
- * @enddot
- * @else
- * @dot
-  digraph example {
-    rankdir="LR";
-
-    node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Sans, fontsize=8];
-
-    uninit [label="EXT_UNINIT", style="bold"];
-    stop  [label="EXT_STOP\nLow Power"];
-    active [label="EXT_ACTIVE"];
-
-    uninit -> stop [label="extInit()"];
-    stop -> stop [label="\nextStop()"];
-    stop -> active [label="\nextStart()"];
-    active -> stop [label="\nextStop()"];
-    active -> active [label="\nextStart()"];
-  }
- * @enddot
- * @endif
- *
- * @section ext_2 EXT Operations.
- * This driver abstracts generic external interrupt sources, a callback
- * is invoked when a programmable transition is detected on one of the
- * configured channels. Several channel modes are possible.
- * - <b>EXT_CH_MODE_DISABLED</b>, channel not used.
- * - <b>EXT_CH_MODE_RISING_EDGE</b>, callback on a rising edge.
- * - <b>EXT_CH_MODE_FALLING_EDGE</b>, callback on a falling edge.
- * - <b>EXT_CH_MODE_BOTH_EDGES</b>, callback on a both edges.
- * .
- * @ingroup IO
- */
diff --git a/os/hal/dox/gpt.dox b/os/hal/dox/gpt.dox
deleted file mode 100644
index 50a3ffd1e..000000000
--- a/os/hal/dox/gpt.dox
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup GPT GPT Driver
- * @brief   Generic GPT Driver.
- * @details This module implements a generic GPT (General Purpose Timer)
- *          driver. The timer can be programmed in order to trigger callbacks
- *          after a specified time period or continuously with a specified
- *          interval.
- * @pre     In order to use the GPT driver the @p HAL_USE_GPT option
- *          must be enabled in @p halconf.h.
- *
- * @section gpt_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop  [label="GPT_STOP\nLow Power"];
-    uninit [label="GPT_UNINIT", style="bold"];
-    ready [label="GPT_READY\nClock Enabled"];
-    continuous [label="GPT_CONT..S\nContinuous\nMode"];
-    oneshot [label="GPT_ONESHOT\nOne Shot\nMode"];
-
-    uninit -> stop [label=" gptInit()", constraint=false];
-    stop -> stop [label="\ngptStop()"];
-    stop -> ready [label="\ngptStart()"];
-    ready -> stop [label="\ngptStop()"];
-    ready -> ready [label="\ngptStart()"];
-    ready -> continuous [label="\ngptStartContinuous()"];
-    continuous -> ready [label="\ngptStopTimer()"];
-    continuous -> continuous [label=">callback<"];
-    ready -> oneshot [label="\ngptStartOneShot()\ngptPolledDelay()"];
-    oneshot -> ready [label="\n>callback<\nor\nDelay Over"];
-  }
- * @enddot
- *
- * @section gpt_2 GPT Operations.
- * This driver abstracts a generic timer composed of:
- * - A clock prescaler.
- * - A main up counter.
- * - A comparator register that resets the main counter to zero when the limit
- *   is reached. A callback is invoked when this happens.
- * .
- * The timer can operate in three different modes:
- * - <b>Continuous Mode</b>, a periodic callback is invoked until the driver
- *   is explicitly stopped.
- * - <b>One Shot Mode</b>, a callback is invoked after the programmed period
- *   and then the timer automatically stops.
- * - <b>Delay Mode</b>, the timer is used for inserting a brief delay into
- *   the execution flow, no callback is invoked in this mode.
- * .
- * @ingroup IO
- */
diff --git a/os/hal/dox/hal.dox b/os/hal/dox/hal.dox
deleted file mode 100644
index 1c449e7e3..000000000
--- a/os/hal/dox/hal.dox
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup HAL HAL Driver
- * @brief   Hardware Abstraction Layer.
- * @details The HAL (Hardware Abstraction Layer) driver performs the system
- *          initialization and includes the platform support code shared by
- *          the other drivers. This driver does contain any API function
- *          except for a general initialization function @p halInit() that
- *          must be invoked before any HAL service can be used, usually the
- *          HAL initialization should be performed immediately before the
- *          kernel initialization.<br>
- *          Some HAL driver implementations also offer a custom early clock
- *          setup function that can be invoked before the C runtime
- *          initialization in order to accelerate the startup time.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/i2c.dox b/os/hal/dox/i2c.dox
deleted file mode 100644
index 4b2342e5d..000000000
--- a/os/hal/dox/i2c.dox
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup I2C I2C Driver
- * @brief   Generic I2C Driver.
- * @details This module implements a generic I2C (Inter-Integrated Circuit)
- *          driver.
- * @pre     In order to use the I2C driver the @p HAL_USE_I2C option
- *          must be enabled in @p halconf.h.
- *
- * @section i2c_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
-  digraph example {
-    size="5, 7";
-    rankdir="LR";
-
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop [label="I2C_STOP\nLow Power"];
-    uninit [label="I2C_UNINIT", style="bold"];
-    ready [label="I2C_READY\nClock Enabled"];
-    active_tx [label="I2C_ACTIVE_TX\nBus TX Active"];
-    active_rx [label="I2C_ACTIVE_RX\nBus RX Active"];
-    locked [label="I2C_LOCKED\nBus Locked"];
-
-    uninit -> stop [label="i2cInit()", constraint=false];
-    stop -> stop [label="i2cStop()"];
-    stop -> ready [label="i2cStart()"];
-    ready -> ready [label="i2cStart()"];
-    ready -> stop [label="i2cStop()"];
-    ready -> active_tx [label="i2cMasterTransmit()"];
-    ready -> active_rx [label="i2cMasterReceive()"];
-    active_tx -> ready [label="completed"];
-    active_rx -> ready [label="completed"];
-    active_tx -> locked [label="RDY_TIMEOUT"];
-    active_rx -> locked [label="RDY_TIMEOUT"];
-    locked -> stop [label="i2cStop()"];
-    locked -> ready [label="i2cStart()"];
-  }
- * @else
- * @dot
-  digraph example {
-    rankdir="LR";
-
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop [label="I2C_STOP\nLow Power"];
-    uninit [label="I2C_UNINIT", style="bold"];
-    ready [label="I2C_READY\nClock Enabled"];
-    active_tx [label="I2C_ACTIVE_TX\nBus TX Active"];
-    active_rx [label="I2C_ACTIVE_RX\nBus RX Active"];
-    locked [label="I2C_LOCKED\nBus Locked"];
-
-    uninit -> stop [label="i2cInit()", constraint=false];
-    stop -> stop [label="i2cStop()"];
-    stop -> ready [label="i2cStart()"];
-    ready -> ready [label="i2cStart()"];
-    ready -> stop [label="i2cStop()"];
-    ready -> active_tx [label="i2cMasterTransmit()"];
-    ready -> active_rx [label="i2cMasterReceive()"];
-    active_tx -> ready [label="completed"];
-    active_rx -> ready [label="completed"];
-    active_tx -> locked [label="RDY_TIMEOUT"];
-    active_rx -> locked [label="RDY_TIMEOUT"];
-    locked -> stop [label="i2cStop()"];
-    locked -> ready [label="i2cStart()"];
-  }
- * @enddot
- * @endif
- * The driver is not thread safe for performance reasons, if you need to access
- * the I2C bus from multiple threads then use the @p i2cAcquireBus() and
- * @p i2cReleaseBus() APIs in order to gain exclusive access.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/i2s.dox b/os/hal/dox/i2s.dox
deleted file mode 100644
index 1dffb75d4..000000000
--- a/os/hal/dox/i2s.dox
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup I2S I2S Driver
- * @brief   Generic I2S Driver.
- * @details This module implements a generic I2S  driver.
- * @pre     In order to use the I2S driver the @p HAL_USE_I2S option
- *          must be enabled in @p halconf.h.
- *
- * @section i2s_1 Driver State Machine
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/icu.dox b/os/hal/dox/icu.dox
deleted file mode 100644
index 76506c10a..000000000
--- a/os/hal/dox/icu.dox
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup ICU ICU Driver
- * @brief   Generic ICU Driver.
- * @details This module implements a generic ICU (Input Capture Unit) driver.
- * @pre     In order to use the ICU driver the @p HAL_USE_ICU option
- *          must be enabled in @p halconf.h.
- *
- * @section icu_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
-  digraph example {
-    size="5, 7";
-    rankdir="LR";
-
-    node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Sans, fontsize=8];
-
-    stop  [label="ICU_STOP\nLow Power"];
-    uninit [label="ICU_UNINIT", style="bold"];
-    ready [label="ICU_READY\nClock Enabled"];
-    waiting [label="ICU_WAITING"];
-    active [label="ICU_ACTIVE"];
-    idle [label="ICU_IDLE"];
-
-    uninit -> stop [label=" icuInit()", constraint=false];
-    stop -> stop [label="\nicuStop()"];
-    stop -> ready [label="\nicuStart()"];
-    ready -> stop [label="\nicuStop()"];
-    ready -> ready [label="\nicuStart()\nicuDisable()"];
-    ready -> waiting [label="\nicuEnable()"];
-    waiting -> active [label="\nStart Front"];
-    waiting -> ready [label="\nicuDisable()"];
-    waiting -> waiting [label="\nStop Front"];
-    active -> idle [label="\nStop Front\n>width_cb<"];
-    active -> ready [label="\nicuDisable()\nicuDisableI()"];
-    idle -> active [label="\nStart Front\n>period_cb<"];
-    idle -> ready [label="\nicuDisable()\nicuDisableI()"];
-  }
- * @enddot
- * @else
- * @dot
-  digraph example {
-    rankdir="LR";
-
-    node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Sans, fontsize=8];
-
-    stop  [label="ICU_STOP\nLow Power"];
-    uninit [label="ICU_UNINIT", style="bold"];
-    ready [label="ICU_READY\nClock Enabled"];
-    waiting [label="ICU_WAITING"];
-    active [label="ICU_ACTIVE"];
-    idle [label="ICU_IDLE"];
-
-    uninit -> stop [label=" icuInit()", constraint=false];
-    stop -> stop [label="\nicuStop()"];
-    stop -> ready [label="\nicuStart()"];
-    ready -> stop [label="\nicuStop()"];
-    ready -> ready [label="\nicuStart()\nicuDisable()"];
-    ready -> waiting [label="\nicuEnable()"];
-    waiting -> active [label="\nStart Front"];
-    waiting -> ready [label="\nicuDisable()"];
-    waiting -> waiting [label="\nStop Front"];
-    active -> idle [label="\nStop Front\n>width_cb<"];
-    active -> ready [label="\nicuDisable()\nicuDisableI()"];
-    idle -> active [label="\nStart Front\n>period_cb<"];
-    idle -> ready [label="\nicuDisable()\nicuDisableI()"];
-  }
- * @enddot
- * @endif
- *
- * @section icu_2 ICU Operations.
- * This driver abstracts a generic Input Capture Unit composed of:
- * - A clock prescaler.
- * - A main up counter.
- * - Two capture registers triggered by the rising and falling edges on
- *   the sampled input.
- * .
- * The ICU unit can be programmed to synchronize on the rising or falling
- * edge of the sample input:
- * - <b>ICU_INPUT_ACTIVE_HIGH</b>, a rising edge is the start signal.
- * - <b>ICU_INPUT_ACTIVE_LOW</b>, a falling edge is the start signal.
- * .
- * After the activation the ICU unit can be in one of the following
- * states at any time:
- * - <b>ICU_WAITING</b>, waiting the first start signal.
- * - <b>ICU_ACTIVE</b>, after a start signal.
- * - <b>ICU_IDLE</b>, after a stop signal.
- * .
- * Callbacks are invoked when start or stop signals occur.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/io_block.dox b/os/hal/dox/io_block.dox
deleted file mode 100644
index bc709f11e..000000000
--- a/os/hal/dox/io_block.dox
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup IO_BLOCK Abstract I/O Block Device
- * @ingroup IO
- *
- * @section io_block_1 Driver State Machine
- * The drivers implementing this interface shall implement the following
- * state machine internally. Not all the driver functionalities can be used
- * in any moment, any transition not explicitly shown in the following
- * diagram has to be considered an error and shall be captured by an
- * assertion (if enabled).
- * @if LATEX_PDF
- * @dot
-  digraph example {
-    size="5, 7";
-    rankdir="LR";
-
-    node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Sans, fontsize=8];
-
-    stop  [label="BLK_STOP\nLow Power"];
-    uninit [label="BLK_UNINIT", style="bold"];
-    active [label="BLK_ACTIVE\nClock Enabled"];
-    connecting [label="BLK_CONN.ING\nConnecting"];
-    disconnecting [label="BLK_DISC.ING\nDisconnecting"];
-    ready [label="BLK_READY\nCard Ready"];
-    reading [label="BLK_READING\nReading"];
-    writing [label="BLK_WRITING\nWriting"];
-
-    uninit -> stop [label=" blkInit()", constraint=false];
-    stop -> stop [label="\nblkStop()"];
-    stop -> active [label="\nblkStart()"];
-    active -> stop [label="\nblkStop()"];
-    active -> active [label="\nblkStart()\nblkDisconnect()"];
-    active -> connecting [label="\nblkConnect()"];
-    connecting -> ready [label="\nconnection\nsuccessful"];
-    connecting -> ready [label="\nblkConnect()", dir="back"];
-    connecting -> active [label="\nconnection\nfailed"];
-    disconnecting -> ready [label="\nblkDisconnect()", dir="back"];
-    active -> disconnecting [label="\ndisconnection\nfinished", dir="back"];
-    ready -> reading [label="\nblkRead()"];
-    reading -> ready [label="\nread finished\nread error"];
-    ready -> writing [label="\nblkWrite()"];
-    writing -> ready [label="\nwrite finished\nwrite error"];
-  }
- * @enddot
- * @else
- * @dot
-  digraph example {
-    rankdir="LR";
-
-    node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Sans, fontsize=8];
-
-    stop  [label="BLK_STOP\nLow Power"];
-    uninit [label="BLK_UNINIT", style="bold"];
-    active [label="BLK_ACTIVE\nClock Enabled"];
-    connecting [label="BLK_CONN.ING\nConnecting"];
-    disconnecting [label="BLK_DISC.ING\nDisconnecting"];
-    ready [label="BLK_READY\nCard Ready"];
-    reading [label="BLK_READING\nReading"];
-    writing [label="BLK_WRITING\nWriting"];
-    syncing [label="BLK_SYNCING\nSynchronizing"];
-
-    uninit -> stop [label=" blkInit()", constraint=false];
-    stop -> stop [label="\nblkStop()"];
-    stop -> active [label="\nblkStart()"];
-    active -> stop [label="\nblkStop()"];
-    active -> active [label="\nblkStart()\nblkDisconnect()"];
-    active -> connecting [label="\nblkConnect()"];
-    connecting -> ready [label="\nconnection\nsuccessful"];
-    connecting -> ready [label="\nblkConnect()", dir="back"];
-    connecting -> active [label="\nconnection\nfailed"];
-    disconnecting -> ready [label="\nblkDisconnect()", dir="back"];
-    active -> disconnecting [label="\ndisconnection\nfinished", dir="back"];
-    ready -> reading [label="\nblkRead()"];
-    reading -> ready [label="\nread finished\nread error"];
-    ready -> writing [label="\nblkWrite()"];
-    writing -> ready [label="\nwrite finished\nwrite error"];
-    ready -> syncing [label="\nblkSync()"];
-    syncing -> ready [label="\nsynchronization finished"];
-  }
- * @enddot
- * @endif
- */
diff --git a/os/hal/dox/io_channel.dox b/os/hal/dox/io_channel.dox
deleted file mode 100644
index 66c6bae2c..000000000
--- a/os/hal/dox/io_channel.dox
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup IO_CHANNEL Abstract I/O Channel
- * @ingroup IO
- */
diff --git a/os/hal/dox/mac.dox b/os/hal/dox/mac.dox
deleted file mode 100644
index f73185268..000000000
--- a/os/hal/dox/mac.dox
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup MAC MAC Driver
- * @brief Generic MAC driver.
- * @details This module implements a generic MAC (Media Access Control)
- *          driver for Ethernet controllers.
- * @pre     In order to use the MAC driver the @p HAL_USE_MAC option
- *          must be enabled in @p halconf.h.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/mmc_spi.dox b/os/hal/dox/mmc_spi.dox
deleted file mode 100644
index 55dcaafd8..000000000
--- a/os/hal/dox/mmc_spi.dox
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup MMC_SPI MMC over SPI Driver
- * @brief Generic MMC driver.
- * @details This module implements a portable MMC/SD driver that uses a SPI
- *          driver as physical layer. Hot plugging and removal are supported
- *          through kernel events.
- * @pre     In order to use the MMC_SPI driver the @p HAL_USE_MMC_SPI and
- *          @p HAL_USE_SPI options must be enabled in @p halconf.h.
- *
- * @section mmc_spi_1 Driver State Machine
- * This driver implements a state machine internally, see the @ref IO_BLOCK
- * module documentation for details.
- *
- * @section mmc_spi_2 Driver Operations
- * This driver allows to read or write single or multiple 512 bytes blocks
- * on a SD Card.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/mmcsd.dox b/os/hal/dox/mmcsd.dox
deleted file mode 100644
index c7551b975..000000000
--- a/os/hal/dox/mmcsd.dox
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup MMCSD MMC/SD Block Device
- * @details This module implements a common ancestor for all device drivers
- *          accessing MMC or SD cards. This interface inherits the state
- *          machine and the interface from the @ref IO_BLOCK module.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/pal.dox b/os/hal/dox/pal.dox
deleted file mode 100644
index d917545a7..000000000
--- a/os/hal/dox/pal.dox
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup PAL PAL Driver
- * @brief   I/O Ports Abstraction Layer
- * @details This module defines an abstract interface for digital I/O ports.
- *          Note that most I/O ports functions are just macros. The macros
- *          have default software implementations that can be redefined in a
- *          PAL Low Level Driver if the target hardware supports special
- *          features like, for example, atomic bit set/reset/masking. Please
- *          refer to the ports specific documentation for details.<br>
- *          The @ref PAL has the advantage to make the access to the I/O
- *          ports platform independent and still be optimized for the specific
- *          architectures.<br>
- *          Note that the PAL Low Level Driver may also offer non standard
- *          macro and functions in order to support specific features but,
- *          of course, the use of such interfaces would not be portable.
- *          Such interfaces shall be marked with the architecture name inside
- *          the function names.
- * @pre     In order to use the PAL driver the @p HAL_USE_PAL option
- *          must be enabled in @p halconf.h.
- *
- * @section pal_1 Implementation Rules
- * In implementing a PAL Low Level Driver there are some rules/behaviors that
- * should be respected.
- *
- * @subsection pal_1_1 Writing on input pads
- * The behavior is not specified but there are implementations better than
- * others, this is the list of possible implementations, preferred options
- * are on top:
- * -# The written value is not actually output but latched, should the pads
- *    be reprogrammed as outputs the value would be in effect.
- * -# The write operation is ignored.
- * -# The write operation has side effects, as example disabling/enabling
- *    pull up/down resistors or changing the pad direction. This scenario is
- *    discouraged, please try to avoid this scenario.
- * .
- * @subsection pal_1_2 Reading from output pads
- * The behavior is not specified but there are implementations better than
- * others, this is the list of possible implementations, preferred options
- * are on top:
- * -# The actual pads states are read (not the output latch).
- * -# The output latch value is read (regardless of the actual pads states).
- * -# Unspecified, please try to avoid this scenario.
- * .
- * @subsection pal_1_3 Writing unused or unimplemented port bits
- * The behavior is not specified.
- *
- * @subsection pal_1_4 Reading from unused or unimplemented port bits
- * The behavior is not specified.
- *
- * @subsection pal_1_5 Reading or writing on pins associated to other functionalities
- * The behavior is not specified.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/pwm.dox b/os/hal/dox/pwm.dox
deleted file mode 100644
index f990502a4..000000000
--- a/os/hal/dox/pwm.dox
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup PWM PWM Driver
- * @brief   Generic PWM Driver.
- * @details This module implements a generic PWM (Pulse Width Modulation)
- *          driver.
- * @pre     In order to use the PWM driver the @p HAL_USE_PWM option
- *          must be enabled in @p halconf.h.
- *
- * @section pwm_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-    uninit [label="PWM_UNINIT", style="bold"];
-    stop  [label="PWM_STOP\nLow Power"];
-    ready [label="PWM_READY\nClock Enabled"];
-    uninit -> stop [label="pwmInit()"];
-    stop -> stop [label="pwmStop()"];
-    stop -> ready [label="pwmStart()"];
-    ready -> stop [label="pwmStop()"];
-    ready -> ready [label="pwmEnableChannel()\npwmDisableChannel()"];
-  }
- * @enddot
- *
- * @section pwm_2 PWM Operations.
- * This driver abstracts a generic PWM timer composed of:
- * - A clock prescaler.
- * - A main up counter.
- * - A comparator register that resets the main counter to zero when the limit
- *   is reached. An optional callback can be generated when this happens.
- * - An array of @p PWM_CHANNELS PWM channels, each channel has an output,
- *   a comparator and is able to invoke an optional callback when a comparator
- *   match with the main counter happens.
- * .
- * A PWM channel output can be in two different states:
- * - <b>IDLE</b>, when the channel is disabled or after a match occurred.
- * - <b>ACTIVE</b>, when the channel is enabled and a match didn't occur yet
- *   in the current PWM cycle.
- * .
- * Note that the two states can be associated to both logical zero or one in
- * the @p PWMChannelConfig structure.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/rtc.dox b/os/hal/dox/rtc.dox
deleted file mode 100644
index d80b6e837..000000000
--- a/os/hal/dox/rtc.dox
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup RTC RTC Driver
- * @brief   Real Time Clock Abstraction Layer
- * @details This module defines an abstract interface for a Real Time Clock
- *          Peripheral.
- * @pre     In order to use the RTC driver the @p HAL_USE_RTC option
- *          must be enabled in @p halconf.h. 
- *          
- * @ingroup IO
- */
diff --git a/os/hal/dox/sdc.dox b/os/hal/dox/sdc.dox
deleted file mode 100644
index 073629457..000000000
--- a/os/hal/dox/sdc.dox
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup SDC SDC Driver
- * @brief   Generic SD Card Driver.
- * @details This module implements a generic SDC (Secure Digital Card) driver.
- * @pre     In order to use the SDC driver the @p HAL_USE_SDC option
- *          must be enabled in @p halconf.h.
- *
- * @section sdc_1 Driver State Machine
- * This driver implements a state machine internally, see the @ref IO_BLOCK
- * module documentation for details.
- *
- * @section sdc_2 Driver Operations
- * This driver allows to read or write single or multiple 512 bytes blocks
- * on a SD Card.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/serial.dox b/os/hal/dox/serial.dox
deleted file mode 100644
index 304955216..000000000
--- a/os/hal/dox/serial.dox
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup SERIAL Serial Driver
- * @brief   Generic Serial Driver.
- * @details This module implements a generic full duplex serial driver. The
- *          driver implements a @p SerialDriver interface and uses I/O Queues
- *          for communication between the upper and the lower driver. Event
- *          flags are used to notify the application about incoming data,
- *          outgoing data and other I/O events.<br>
- *          The  module also contains functions that make the implementation
- *          of the interrupt service routines much easier.
- * @pre     In order to use the SERIAL driver the @p HAL_USE_SERIAL option
- *          must be enabled in @p halconf.h.
- *
- *
- * @section serial_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    uninit [label="SD_UNINIT", style="bold"];
-    stop [label="SD_STOP\nLow Power"];
-    ready [label="SD_READY\nClock Enabled"];
-
-    uninit -> stop [label=" sdInit()"];
-    stop -> stop [label="\nsdStop()"];
-    stop -> ready [label="\nsdStart()"];
-    ready -> stop [label="\nsdStop()"];
-    ready -> ready [label="\nsdStart()"];
-    ready -> ready [label="\nAny I/O operation"];
-  }
- * @enddot
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/serial_usb.dox b/os/hal/dox/serial_usb.dox
deleted file mode 100644
index 9377878ee..000000000
--- a/os/hal/dox/serial_usb.dox
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup SERIAL_USB Serial over USB Driver
- * @brief   Serial over USB Driver.
- * @details This module implements an USB Communication Device Class
- *          (CDC) as a normal serial communication port accessible from
- *          the device application.
- * @pre     In order to use the USB over Serial driver the
- *          @p HAL_USE_SERIAL_USB option must be enabled in @p halconf.h.
- *
- * @section usb_serial_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    uninit [label="SDU_UNINIT", style="bold"];
-    stop [label="SDU_STOP\nLow Power"];
-    ready [label="SDU_READY\nClock Enabled"];
-
-    uninit -> stop [label=" sduInit()"];
-    stop -> stop [label="\nsduStop()"];
-    stop -> ready [label="\nsduStart()"];
-    ready -> stop [label="\nsduStop()"];
-    ready -> ready [label="\nsduStart()"];
-    ready -> ready [label="\nAny I/O operation"];
-  }
- * @enddot
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/spi.dox b/os/hal/dox/spi.dox
deleted file mode 100644
index 2143f9590..000000000
--- a/os/hal/dox/spi.dox
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup SPI SPI Driver
- * @brief   Generic SPI Driver.
- * @details This module implements a generic SPI (Serial Peripheral Interface)
- *          driver allowing bidirectional and monodirectional transfers,
- *          complex atomic transactions are supported as well.
- * @pre     In order to use the SPI driver the @p HAL_USE_SPI option
- *          must be enabled in @p halconf.h.
- *
- * @section spi_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
-  digraph example {
-    size="5, 7";
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop  [label="SPI_STOP\nLow Power"];
-    uninit [label="SPI_UNINIT", style="bold"];
-    ready [label="SPI_READY\nClock Enabled"];
-    active [label="SPI_ACTIVE\nBus Active"];
-    complete [label="SPI_COMPLETE\nComplete"];
-
-    uninit -> stop [label="\n spiInit()", constraint=false];
-    stop -> ready [label="\nspiStart()"];
-    ready -> ready [label="\nspiSelect()\nspiUnselect()\nspiStart()"];
-    ready -> stop [label="\nspiStop()"];
-    stop -> stop [label="\nspiStop()"];
-    ready -> active [label="\nspiStartXXXI() (async)\nspiXXX() (sync)"];
-    active -> ready [label="\nsync return"];
-    active -> complete [label="\nasync callback\n>spc_endcb<"];
-    complete -> active [label="\nspiStartXXXI() (async)\nthen\ncallback return"];
-    complete -> ready [label="\ncallback return"];
-  }
- * @enddot
- * @else
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop  [label="SPI_STOP\nLow Power"];
-    uninit [label="SPI_UNINIT", style="bold"];
-    ready [label="SPI_READY\nClock Enabled"];
-    active [label="SPI_ACTIVE\nBus Active"];
-    complete [label="SPI_COMPLETE\nComplete"];
-
-    uninit -> stop [label="\n spiInit()", constraint=false];
-    stop -> ready [label="\nspiStart()"];
-    ready -> ready [label="\nspiSelect()\nspiUnselect()\nspiStart()"];
-    ready -> stop [label="\nspiStop()"];
-    stop -> stop [label="\nspiStop()"];
-    ready -> active [label="\nspiStartXXX() (async)\nspiXXX() (sync)"];
-    active -> ready [label="\nsync return"];
-    active -> complete [label="\nasync callback\n>spc_endcb<"];
-    complete -> active [label="\nspiStartXXXI() (async)\nthen\ncallback return"];
-    complete -> ready [label="\ncallback return"];
-  }
- * @enddot
- * @endif
- *
- * The driver is not thread safe for performance reasons, if you need to access
- * the SPI bus from multiple threads then use the @p spiAcquireBus() and
- * @p spiReleaseBus() APIs in order to gain exclusive access.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/tm.dox b/os/hal/dox/tm.dox
deleted file mode 100644
index 939066bda..000000000
--- a/os/hal/dox/tm.dox
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup TM Time Measurement Driver
- *
- * @brief   Time Measurement unit.
- * @details This module implements a time measurement mechanism able to
- *          monitor a portion of code and store the best/worst/last
- *          measurement. The measurement is performed using the realtime
- *          counter mechanism abstracted in the HAL driver.
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/uart.dox b/os/hal/dox/uart.dox
deleted file mode 100644
index 57ff5fbb6..000000000
--- a/os/hal/dox/uart.dox
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup UART UART Driver
- * @brief   Generic UART Driver.
- * @details This driver abstracts a generic UART (Universal Asynchronous
- *          Receiver Transmitter) peripheral, the API is designed to be:
- *          - Unbuffered and copy-less, transfers are always directly performed
- *            from/to the application-level buffers without extra copy
- *            operations.
- *          - Asynchronous, the API is always non blocking.
- *          - Callbacks capable, operations completion and other events are
- *            notified using callbacks.
- *          .
- *          Special hardware features like deep hardware buffers, DMA transfers
- *          are hidden to the user but fully supportable by the low level
- *          implementations.<br>
- *          This driver model is best used where communication events are
- *          meant to drive an higher level state machine, as example:
- *          - RS485 drivers.
- *          - Multipoint network drivers.
- *          - Serial protocol decoders.
- *          .
- *          If your application requires a synchronous buffered driver then
- *          the @ref SERIAL should be used instead.
- * @pre     In order to use the UART driver the @p HAL_USE_UART option
- *          must be enabled in @p halconf.h.
- *
- * @section uart_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    uninit [label="UART_UNINIT", style="bold"];
-    stop  [label="UART_STOP\nLow Power"];
-    ready [label="UART_READY\nClock Enabled"];
-
-    uninit -> stop [label="\nuartInit()"];
-    stop -> ready [label="\nuartStart()"];
-    ready -> ready [label="\nuartStart()"];
-    ready -> stop [label="\nuartStop()"];
-    stop -> stop [label="\nuartStop()"];
-  }
- * @enddot
- *
- * @subsection uart_1_1 Transmitter sub State Machine
- * The follow diagram describes the transmitter state machine, this diagram
- * is valid while the driver is in the @p UART_READY state. This state
- * machine is automatically reset to the @p TX_IDLE state each time the
- * driver enters the @p UART_READY state.
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    tx_idle [label="TX_IDLE", style="bold"];
-    tx_active [label="TX_ACTIVE"];
-    tx_complete [label="TX_COMPLETE"];
-    tx_fatal [label="Fatal Error", style="bold"];
-
-    tx_idle -> tx_active [label="\nuartStartSend()"];
-    tx_idle -> tx_idle [label="\nuartStopSend()\n>uc_txend2<"];
-    tx_active -> tx_complete [label="\nbuffer transmitted\n>uc_txend1<"];
-    tx_active -> tx_idle [label="\nuartStopSend()"];
-    tx_active -> tx_fatal [label="\nuartStartSend()"];
-    tx_complete -> tx_active [label="\nuartStartSendI()\nthen\ncallback return"];
-    tx_complete -> tx_idle [label="\ncallback return"];
-  }
- * @enddot
- *
- * @subsection uart_1_2 Receiver sub State Machine
- * The follow diagram describes the receiver state machine, this diagram
- * is valid while the driver is in the @p UART_READY state. This state
- * machine is automatically reset to the @p RX_IDLE state each time the
- * driver enters the @p UART_READY state.
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    rx_idle [label="RX_IDLE", style="bold"];
-    rx_active [label="RX_ACTIVE"];
-    rx_complete [label="RX_COMPLETE"];
-    rx_fatal [label="Fatal Error", style="bold"];
-
-    rx_idle -> rx_idle [label="\nuartStopReceive()\n>uc_rxchar<\n>uc_rxerr<"];
-    rx_idle -> rx_active [label="\nuartStartReceive()"];
-
-    rx_active -> rx_complete [label="\nbuffer filled\n>uc_rxend<"];
-    rx_active -> rx_idle [label="\nuartStopReceive()"];
-    rx_active -> rx_active [label="\nreceive error\n>uc_rxerr<"];
-    rx_active -> rx_fatal [label="\nuartStartReceive()"];
-    rx_complete -> rx_active [label="\nuartStartReceiveI()\nthen\ncallback return"];
-    rx_complete -> rx_idle [label="\ncallback return"];
-  }
- * @enddot
- *
- * @ingroup IO
- */
diff --git a/os/hal/dox/usb.dox b/os/hal/dox/usb.dox
deleted file mode 100644
index b71a75186..000000000
--- a/os/hal/dox/usb.dox
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup USB USB Driver
- * @brief   Generic USB Driver.
- * @details This module implements a generic USB (Universal Serial Bus) driver
- *          supporting device-mode operations.
- * @pre     In order to use the USB driver the @p HAL_USE_USB option
- *          must be enabled in @p halconf.h.
- *
- * @section usb_1 Driver State Machine
- * The driver implements a state machine internally, not all the driver
- * functionalities can be used in any moment, any transition not explicitly
- * shown in the following diagram has to be considered an error and shall
- * be captured by an assertion (if enabled).
- * @if LATEX_PDF
- * @dot
-  digraph example {
-    size="5, 7";
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop  [label="USB_STOP\nLow Power"];
-    uninit [label="USB_UNINIT", style="bold"];
-    ready [label="USB_READY\nClock Enabled"];
-    selected [label="\nUSB_SELECTED\naddress\nassigned"];
-    active [label="\nUSB_ACTIVE\nconfiguration\nselected"];
-
-    uninit -> stop [label=" usbInit()", constraint=false];
-    stop -> stop [label="\nusbStop()"];
-    stop -> ready [label="\nusbStart()"];
-    ready -> stop [label="\nusbStop()"];
-    ready -> ready [label="\n\nusbStart()"];
-    ready -> ready [label="\nSUSPEND/WAKEUP\n>event_cb<"];
-    ready -> selected [label="\nSET_ADDRESS\n>event_cb<"];
-    selected -> stop [label="\nusbStop()"];
-    selected -> ready [label="\nUSB RESET\n>event_cb<"];
-    selected -> selected [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<"];
-    selected -> active [label="\nSET_CONF(n)\n>event_cb<"];
-    active -> stop [label="\nusbStop()"];
-    active -> selected [label="\nSET_CONF(0)\n>event_cb<"];
-    active -> active [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<\n\nEndpoints Activity\n >in_cb< or >out_cb<"];
-    active -> ready [label="\nUSB RESET\n>event_cb<"];
-  }
- * @enddot
- * @else
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    stop  [label="USB_STOP\nLow Power"];
-    uninit [label="USB_UNINIT", style="bold"];
-    ready [label="USB_READY\nClock Enabled"];
-    selected [label="\nUSB_SELECTED\naddress\nassigned"];
-    active [label="\nUSB_ACTIVE\nconfiguration\nselected"];
-
-    uninit -> stop [label=" usbInit()", constraint=false];
-    stop -> stop [label="\nusbStop()"];
-    stop -> ready [label="\nusbStart()"];
-    ready -> stop [label="\nusbStop()"];
-    ready -> ready [label="\n\nusbStart()"];
-    ready -> ready [label="\nSUSPEND/WAKEUP\n>event_cb<"];
-    ready -> selected [label="\nSET_ADDRESS\n>event_cb<"];
-    selected -> stop [label="\nusbStop()"];
-    selected -> ready [label="\nUSB RESET\n>event_cb<"];
-    selected -> selected [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<"];
-    selected -> active [label="\nSET_CONF(n)\n>event_cb<"];
-    active -> stop [label="\nusbStop()"];
-    active -> selected [label="\nSET_CONF(0)\n>event_cb<"];
-    active -> active [label="\nSUSPEND/WAKEUP\n>event_cb<\n\nValid EP0 Message\n>requests_hook_cb<\n\nGET DESCRIPTOR\n>get_descriptor_cb<\n\nEndpoints Activity\n >in_cb< or >out_cb<"];
-    active -> ready [label="\nUSB RESET\n>event_cb<"];
-  }
- * @enddot
- * @endif
- *
- * @section usb_2 USB Operations
- * The USB driver is quite complex and USB is complex in itself, it is
- * recommended to study the USB specification before trying to use the
- * driver.
- *
- * @subsection usb_2_1 USB Implementation
- * The USB driver abstracts the inner details of the underlying USB hardware.
- * The driver works asynchronously and communicates with the application
- * using callbacks. The application is responsible of the descriptors and
- * strings required by the USB device class to be implemented and of the
- * handling of the specific messages sent over the endpoint zero. Standard
- * messages are handled internally to the driver. The application can use
- * hooks in order to handle custom messages or override the handling of the
- * default handling of standard messages.
- *
- * @subsection usb_2_2 USB Endpoints
- * USB endpoints are the objects that the application uses to exchange
- * data with the host. There are two kind of endpoints:
- * - <b>IN</b> endpoints are used by the application to transmit data to
- *   the host.<br>
- * - <b>OUT</b> endpoints are used by the application to receive data from
- *   the host.
- * .
- * The driver invokes a callback after finishing an IN or OUT transaction.
- * States diagram for OUT endpoints in transaction mode:
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    disabled [label="EP_DISABLED\nDisabled", style="bold"];
-    receiving [label="EP_BUSY\nReceiving"];
-    idle [label="EP_IDLE\nReady"];
-
-    disabled -> idle [label="\nusbInitEndpointI()"];
-    idle -> receiving [label="\nusbPrepareReceive()\nusbStartReceiveI()"];
-    receiving -> receiving [label="\nmore packets"];
-    receiving -> idle [label="\nreception end\n>out_cb<"];
-    receiving -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"];
-    idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"];
-  }
- * @enddot
- * <br><br>
- * States diagram for IN endpoints in transaction mode:
- * @dot
-  digraph example {
-    rankdir="LR";
-    node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true",
-          width="0.9", height="0.9"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    disabled [label="EP_DISABLED\nDisabled", style="bold"];
-    transmitting [label="EP_BUSY\nTransmitting"];
-    idle [label="EP_IDLE\nReady"];
-
-    disabled -> idle [label="\usbInitEndpointI()"];
-    idle -> transmitting [label="\nusbPrepareTransmit()\nusbStartTransmitI()"];
-    transmitting -> transmitting [label="\nmore packets"];
-    transmitting -> idle [label="\ntransmission end\n>in_cb<"];
-    transmitting -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"];
-    idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"];
-  }
- * @enddot
- * <br><br>
- *
- * @subsection usb_2_4 USB Callbacks
- * The USB driver uses callbacks in order to interact with the application.
- * There are several kinds of callbacks to be handled:
- * - Driver events callback. As example errors, suspend event, reset event
- *   etc.
- * - Messages Hook callback. This hook allows the application to implement
- *   handling of custom messages or to override the default handling of
- *   standard messages on endpoint zero.
- * - Descriptor Requested callback. When the driver endpoint zero handler
- *   receives a GET DESCRIPTOR message and needs to send a descriptor to
- *   the host it queries the application using this callback.
- * - Start of Frame callback. This callback is invoked each time a SOF
- *   packet is received.
- * - Endpoint callbacks. Each endpoint informs the application about I/O
- *   conditions using those callbacks.
- * .
- *
- * @ingroup IO
- */
diff --git a/os/hal/hal.dox b/os/hal/hal.dox
deleted file mode 100644
index 3e747a4ad..000000000
--- a/os/hal/hal.dox
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup IO HAL
- * @brief   Hardware Abstraction Layer.
- * @details Under ChibiOS/RT the set of the various device driver interfaces
- * is called the HAL subsystem: Hardware Abstraction Layer. The HAL is the
- * abstract interface between ChibiOS/RT application and hardware.
- *
- * @section hal_device_driver_arch HAL Device Drivers Architecture
- * A device driver is usually split in two layers:
- * - High Level Device Driver (<b>HLD</b>). This layer contains the definitions
- *   of the driver's APIs and the platform independent part of the driver.<br>
- *   An HLD is composed by two files:
- *   - @p @<driver@>.c, the HLD implementation file. This file must be
- *     included in the Makefile in order to use the driver.
- *   - @p @<driver@>.h, the HLD header file. This file is implicitly
- *     included by the HAL header file @p hal.h.
- *   .
- * - Low Level Device Driver (<b>LLD</b>). This layer contains the platform
- *   dependent part of the driver.<br>
- *   A LLD is composed by two files:
- *   - @p @<driver@>_lld.c, the LLD implementation file. This file must be
- *     included in the Makefile in order to use the driver.
- *   - @p @<driver@>_lld.h, the LLD header file. This file is implicitly
- *     included by the HLD header file.
- *   .
- *   The LLD may be not present in those drivers that do not access the
- *   hardware directly but through other device drivers, as example the
- *   MMC_SPI driver uses the SPI and PAL drivers in order to implement
- *   its functionalities.
- * .
- * @subsection hal_device_driver_diagram Diagram
- * @dot
-  digraph example {
-    graph [size="5, 7", pad="1.5, 0"];
-    node [shape=rectangle, fontname=Helvetica, fontsize=8,
-          fixedsize="true", width="2.0", height="0.4"];
-    edge [fontname=Helvetica, fontsize=8];
-
-    app [label="Application"];
-    hld [label="High Level Driver"];
-    lld [label="Low Level Driver"];
-    hw [label="Microcontroller Hardware"];
-    hal_lld [label="HAL shared low level code"];
-
-    app->hld;
-    hld->lld;
-    lld-> hw;
-    lld->hal_lld;
-    hal_lld->hw;
-  }
- * @enddot
- */
-
-/**
- * @defgroup HAL_CONF Configuration
- * @brief   HAL Configuration.
- * @details The file @p halconf.h contains the high level settings for all
- * the drivers supported by the HAL. The low level, platform dependent,
- * settings are contained in the @p mcuconf.h file instead and are describe
- * in the various platforms reference manuals.
- *
- * @ingroup IO
- */
diff --git a/os/hal/hal.mk b/os/hal/hal.mk
index 766d08b92..ab3a781aa 100644
--- a/os/hal/hal.mk
+++ b/os/hal/hal.mk
@@ -1,24 +1,24 @@
-# List of all the ChibiOS/RT HAL files, there is no need to remove the files
+# List of all the ChibiOS/HAL files, there is no need to remove the files
 # from this list, you can disable parts of the HAL by editing halconf.h.
 HALSRC = ${CHIBIOS}/os/hal/src/hal.c \
+         ${CHIBIOS}/os/hal/src/hal_queues.c \
+         ${CHIBIOS}/os/hal/src/hal_mmcsd.c \
          ${CHIBIOS}/os/hal/src/adc.c \
          ${CHIBIOS}/os/hal/src/can.c \
          ${CHIBIOS}/os/hal/src/dac.c \
          ${CHIBIOS}/os/hal/src/ext.c \
          ${CHIBIOS}/os/hal/src/gpt.c \
          ${CHIBIOS}/os/hal/src/i2c.c \
+         ${CHIBIOS}/os/hal/src/i2s.c \
          ${CHIBIOS}/os/hal/src/icu.c \
-         ${CHIBIOS}/os/hal/src/mac.c \
          ${CHIBIOS}/os/hal/src/mmc_spi.c \
-         ${CHIBIOS}/os/hal/src/mmcsd.c \
          ${CHIBIOS}/os/hal/src/pal.c \
          ${CHIBIOS}/os/hal/src/pwm.c \
-         ${CHIBIOS}/os/hal/src/rtc.c \
          ${CHIBIOS}/os/hal/src/sdc.c \
          ${CHIBIOS}/os/hal/src/serial.c \
          ${CHIBIOS}/os/hal/src/serial_usb.c \
          ${CHIBIOS}/os/hal/src/spi.c \
-         ${CHIBIOS}/os/hal/src/tm.c \
+         ${CHIBIOS}/os/hal/src/st.c \
          ${CHIBIOS}/os/hal/src/uart.c \
          ${CHIBIOS}/os/hal/src/usb.c
 
diff --git a/os/hal/include/adc.h b/os/hal/include/adc.h
index 32b4c65a2..626840c5e 100644
--- a/os/hal/include/adc.h
+++ b/os/hal/include/adc.h
@@ -64,10 +64,6 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if ADC_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
-#error "ADC_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
-#endif
-
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -102,14 +98,8 @@ typedef enum {
  *
  * @notapi
  */
-#define _adc_reset_i(adcp) {                                                \
-  if ((adcp)->thread != NULL) {                                             \
-    Thread *tp = (adcp)->thread;                                            \
-    (adcp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg  = RDY_RESET;                                            \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-}
+#define _adc_reset_i(adcp)                                                  \
+  osalThreadResumeI(&(adcp)->thread, MSG_RESET)
 
 /**
  * @brief   Resumes a thread waiting for a conversion completion.
@@ -118,13 +108,8 @@ typedef enum {
  *
  * @notapi
  */
-#define _adc_reset_s(adcp) {                                                \
-  if ((adcp)->thread != NULL) {                                             \
-    Thread *tp = (adcp)->thread;                                            \
-    (adcp)->thread = NULL;                                                  \
-    chSchWakeupS(tp, RDY_RESET);                                            \
-  }                                                                         \
-}
+#define _adc_reset_s(adcp)                                                  \
+  osalThreadResumeS(&(adcp)->thread, MSG_RESET)
 
 /**
  * @brief   Wakes up the waiting thread.
@@ -134,15 +119,9 @@ typedef enum {
  * @notapi
  */
 #define _adc_wakeup_isr(adcp) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((adcp)->thread != NULL) {                                             \
-    Thread *tp;                                                             \
-    tp = (adcp)->thread;                                                    \
-    (adcp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = RDY_OK;                                                \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
+  osalSysLockFromISR();                                                     \
+  osalThreadResumeI(&(adcp)->thread, MSG_OK);                               \
+  osalSysUnlockFromISR();                                                   \
 }
 
 /**
@@ -153,15 +132,9 @@ typedef enum {
  * @notapi
  */
 #define _adc_timeout_isr(adcp) {                                            \
-  chSysLockFromIsr();                                                       \
-  if ((adcp)->thread != NULL) {                                             \
-    Thread *tp;                                                             \
-    tp = (adcp)->thread;                                                    \
-    (adcp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = RDY_TIMEOUT;                                           \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
+  osalSysLockFromISR();                                                     \
+  osalThreadResumeI(&(adcp)->thread, MSG_TIMEOUT);                          \
+  osalSysUnlockFromISR();                                                   \
 }
 
 #else /* !ADC_USE_WAIT */
diff --git a/os/hal/include/can.h b/os/hal/include/can.h
index 4d502c0d2..534f6f622 100644
--- a/os/hal/include/can.h
+++ b/os/hal/include/can.h
@@ -89,10 +89,6 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS
-#error "CAN driver requires CH_USE_SEMAPHORES and CH_USE_EVENTS"
-#endif
-
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
diff --git a/os/hal/include/dac.h b/os/hal/include/dac.h
index fc0a09d4c..3d1157ae0 100644
--- a/os/hal/include/dac.h
+++ b/os/hal/include/dac.h
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
@@ -64,10 +64,6 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if DAC_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
-#error "DAC_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
-#endif
-
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -107,12 +103,8 @@ typedef enum {
  *
  * @notapi
  */
-#define _dac_wait_s(dacp) {                                                 \
-  chDbgAssert((dacp)->thread == NULL,                                       \
-              "_dac_wait_s(), #1", "already waiting");                      \
-  (dacp)->thread = chThdSelf();                                             \
-  chSchGoSleepS(THD_STATE_SUSPENDED);                                       \
-}
+#define _dac_wait_s(dacp) osalThreadSuspendS(&(dacp)->thread)
+
 /**
  * @brief   Resumes a thread waiting for a conversion completion.
  *
@@ -120,14 +112,7 @@ typedef enum {
  *
  * @notapi
  */
-#define _dac_reset_i(dacp) {                                                \
-  if ((dacp)->thread != NULL) {                                             \
-    Thread *tp = (dacp)->thread;                                            \
-    (dacp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg  = RDY_RESET;                                            \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-}
+#define _dac_reset_i(dacp) osalThreadResumeI(&(dacp)->thread, MSG_RESET)
 
 /**
  * @brief   Resumes a thread waiting for a conversion completion.
@@ -136,13 +121,7 @@ typedef enum {
  *
  * @notapi
  */
-#define _dac_reset_s(dacp) {                                                \
-  if ((dacp)->thread != NULL) {                                             \
-    Thread *tp = (dacp)->thread;                                            \
-    (dacp)->thread = NULL;                                                  \
-    chSchWakeupS(tp, RDY_RESET);                                            \
-  }                                                                         \
-}
+#define _dac_reset_s(dacp) osalThreadResumeS(&(dacp)->thread, MSG_RESET)
 
 /**
  * @brief   Wakes up the waiting thread.
@@ -152,15 +131,9 @@ typedef enum {
  * @notapi
  */
 #define _dac_wakeup_isr(dacp) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((dacp)->thread != NULL) {                                             \
-    Thread *tp;                                                             \
-    tp = (dacp)->thread;                                                    \
-    (dacp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = RDY_OK;                                                \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
+  osalSysLockFromISR();                                                     \
+  osalThreadResumeI(&(dacp)->thread, MSG_OK);                               \
+  osalSysUnlockFromISR();                                                   \
 }
 
 /**
@@ -171,15 +144,9 @@ typedef enum {
  * @notapi
  */
 #define _dac_timeout_isr(dacp) {                                            \
-  chSysLockFromIsr();                                                       \
-  if ((dacp)->thread != NULL) {                                             \
-    Thread *tp;                                                             \
-    tp = (dacp)->thread;                                                    \
-    (dacp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = RDY_TIMEOUT;                                           \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
+  osalSysLockFromISR();                                                     \
+  osalThreadResumeI(&(dacp)->thread, MSG_TIMEOUT);                          \
+  osalSysUnlockFromISR();                                                   \
 }
 
 #else /* !DAC_USE_WAIT */
diff --git a/os/hal/include/ext.h b/os/hal/include/ext.h
index 7f32c5f1f..89dc59df8 100644
--- a/os/hal/include/ext.h
+++ b/os/hal/include/ext.h
@@ -120,9 +120,9 @@ typedef struct EXTDriver EXTDriver;
  * @api
  */
 #define extSetChannelMode(extp, channel, extcp) {                           \
-  chSysLock();                                                              \
+  osalSysLock();                                                            \
   extSetChannelModeI(extp, channel, extcp);                                 \
-  chSysUnlock();                                                            \
+  osalSysUnlock();                                                          \
 }
 
 /** @} */
diff --git a/os/hal/include/gpt.h b/os/hal/include/gpt.h
index 3b474cb14..a900243ba 100644
--- a/os/hal/include/gpt.h
+++ b/os/hal/include/gpt.h
@@ -79,9 +79,7 @@ typedef void (*gptcallback_t)(GPTDriver *gptp);
 /**
  * @brief   Changes the interval of GPT peripheral.
  * @details This function changes the interval of a running GPT unit.
- * @pre     The GPT unit must have been activated using @p gptStart().
- * @pre     The GPT unit must have been running in continuous mode using
- *          @p gptStartContinuous().
+ * @pre     The GPT unit must be running in continuous mode.
  * @post    The GPT unit interval is changed to the new value.
  *
  * @param[in] gptp      pointer to a @p GPTDriver object
@@ -89,10 +87,34 @@ typedef void (*gptcallback_t)(GPTDriver *gptp);
  *
  * @iclass
  */
-#define gptChangeIntervalI(gptp, interval) {                                  \
-  gpt_lld_change_interval(gptp, interval);                                    \
+#define gptChangeIntervalI(gptp, interval) {                                \
+  gpt_lld_change_interval(gptp, interval);                                  \
 }
 
+/**
+ * @brief   Returns the interval of GPT peripheral.
+ * @pre     The GPT unit must be running in continuous mode.
+ *
+ * @param[in] gptp      pointer to a @p GPTDriver object
+ * @return              The current interval.
+ *
+ * @xclass
+ */
+#define gptGetIntervalX(gptp) gpt_lld_get_interval(gptp)
+
+/**
+ * @brief   Returns the counter value of GPT peripheral.
+ * @pre     The GPT unit must be running in continuous mode.
+ * @note    The nature of the counter is not defined, it may count upward
+ *          or downward, it could be continuously running or not.
+ *
+ * @param[in] gptp      pointer to a @p GPTDriver object
+ * @return              The current counter value.
+ *
+ * @xclass
+ */
+#define gptGetCounterX(gptp) gpt_lld_get_counter(gptp)
+
 /*===========================================================================*/
 /* External declarations.                                                    */
 /*===========================================================================*/
diff --git a/os/hal/include/hal.h b/os/hal/include/hal.h
index ceff2e0a9..bab2196d3 100644
--- a/os/hal/include/hal.h
+++ b/os/hal/include/hal.h
@@ -29,21 +29,22 @@
 #ifndef _HAL_H_
 #define _HAL_H_
 
-#include "ch.h"
+#include "osal.h"
 #include "board.h"
 #include "halconf.h"
 
 #include "hal_lld.h"
 
 /* Abstract interfaces.*/
-#include "io_channel.h"
-#include "io_block.h"
+#include "hal_streams.h"
+#include "hal_channels.h"
+#include "hal_ioblock.h"
+#include "hal_mmcsd.h"
 
 /* Shared headers.*/
-#include "mmcsd.h"
+#include "hal_queues.h"
 
-/* Layered drivers.*/
-#include "tm.h"
+/* Normal drivers.*/
 #include "pal.h"
 #include "adc.h"
 #include "can.h"
@@ -51,13 +52,15 @@
 #include "ext.h"
 #include "gpt.h"
 #include "i2c.h"
+#include "i2s.h"
 #include "icu.h"
-#include "mac.h"
+//#include "mac.h"
 #include "pwm.h"
-#include "rtc.h"
+//#include "rtc.h"
 #include "serial.h"
 #include "sdc.h"
 #include "spi.h"
+#include "st.h"
 #include "uart.h"
 #include "usb.h"
 
@@ -69,6 +72,14 @@
 /* Driver constants.                                                         */
 /*===========================================================================*/
 
+/**
+ * @name    Return codes
+ * @{
+ */
+#define HAL_SUCCESS                         false
+#define HAL_FAILED                          true
+/** @} */
+
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
@@ -85,113 +96,6 @@
 /* Driver macros.                                                            */
 /*===========================================================================*/
 
-#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__)
-/**
- * @name    Time conversion utilities for the realtime counter
- * @{
- */
-/**
- * @brief   Seconds to realtime ticks.
- * @details Converts from seconds to realtime ticks number.
- * @note    The result is rounded upward to the next tick boundary.
- *
- * @param[in] sec       number of seconds
- * @return              The number of ticks.
- *
- * @api
- */
-#define S2RTT(sec) (halGetCounterFrequency() * (sec))
-
-/**
- * @brief   Milliseconds to realtime ticks.
- * @details Converts from milliseconds to realtime ticks number.
- * @note    The result is rounded upward to the next tick boundary.
- *
- * @param[in] msec      number of milliseconds
- * @return              The number of ticks.
- *
- * @api
- */
-#define MS2RTT(msec) (((halGetCounterFrequency() + 999UL) / 1000UL) * (msec))
-
-/**
- * @brief   Microseconds to realtime ticks.
- * @details Converts from microseconds to realtime ticks number.
- * @note    The result is rounded upward to the next tick boundary.
- *
- * @param[in] usec      number of microseconds
- * @return              The number of ticks.
- *
- * @api
- */
-#define US2RTT(usec) (((halGetCounterFrequency() + 999999UL) / 1000000UL) * \
-                      (usec))
-
-/**
- * @brief   Realtime ticks to seconds to.
- * @details Converts from realtime ticks number to seconds.
- *
- * @param[in] ticks     number of ticks
- * @return              The number of seconds.
- *
- * @api
- */
-#define RTT2S(ticks) ((ticks) / halGetCounterFrequency())
-
-/**
- * @brief   Realtime ticks to milliseconds.
- * @details Converts from realtime ticks number to milliseconds.
- *
- * @param[in] ticks     number of ticks
- * @return              The number of milliseconds.
- *
- * @api
- */
-#define RTT2MS(ticks) ((ticks) / (halGetCounterFrequency() / 1000UL))
-
-/**
- * @brief   Realtime ticks to microseconds.
- * @details Converts from realtime ticks number to microseconds.
- *
- * @param[in] ticks     number of ticks
- * @return              The number of microseconds.
- *
- * @api
- */
-#define RTT2US(ticks) ((ticks) / (halGetCounterFrequency() / 1000000UL))
-/** @} */
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This is an optional service that could not be implemented in
- *          all HAL implementations.
- * @note    This function can be called from any context.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @special
- */
-#define halGetCounterValue() hal_lld_get_counter_value()
-
-/**
- * @brief   Realtime counter frequency.
- * @note    This is an optional service that could not be implemented in
- *          all HAL implementations.
- * @note    This function can be called from any context.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @special
- */
-#define halGetCounterFrequency() hal_lld_get_counter_frequency()
-/** @} */
-#endif /* HAL_IMPLEMENTS_COUNTERS */
-
 /*===========================================================================*/
 /* External declarations.                                                    */
 /*===========================================================================*/
@@ -200,10 +104,6 @@
 extern "C" {
 #endif
   void halInit(void);
-#if HAL_IMPLEMENTS_COUNTERS
-  bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end);
-  void halPolledDelay(halrtcnt_t ticks);
-#endif /* HAL_IMPLEMENTS_COUNTERS */
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/include/hal_channels.h b/os/hal/include/hal_channels.h
new file mode 100644
index 000000000..a5abe67b8
--- /dev/null
+++ b/os/hal/include/hal_channels.h
@@ -0,0 +1,291 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    hal_channels.h
+ * @brief   I/O channels access.
+ * @details This header defines an abstract interface useful to access generic
+ *          I/O serial devices in a standardized way.
+ *
+ * @addtogroup IO_CHANNEL
+ * @details This module defines an abstract interface for I/O channels by
+ *          extending the @p BaseSequentialStream interface.<br>
+ *          Note that no code is present, I/O channels are just abstract
+ *          interface like structures, you should look at the systems as
+ *          to a set of abstract C++ classes (even if written in C).
+ *          Specific device drivers can use/extend the interface and
+ *          implement them.<br>
+ *          This system has the advantage to make the access to channels
+ *          independent from the implementation logic.
+ * @{
+ */
+
+#ifndef _HAL_CHANNELS_H_
+#define _HAL_CHANNELS_H_
+
+/**
+ * @brief   @p BaseChannel specific methods.
+ */
+#define _base_channel_methods                                               \
+  _base_sequential_stream_methods                                           \
+  /* Channel put method with timeout specification.*/                       \
+  msg_t (*putt)(void *instance, uint8_t b, systime_t time);                 \
+  /* Channel get method with timeout specification.*/                       \
+  msg_t (*gett)(void *instance, systime_t time);                            \
+  /* Channel write method with timeout specification.*/                     \
+  size_t (*writet)(void *instance, const uint8_t *bp,                       \
+                   size_t n, systime_t time);                               \
+  /* Channel read method with timeout specification.*/                      \
+  size_t (*readt)(void *instance, uint8_t *bp, size_t n, systime_t time);
+
+/**
+ * @brief   @p BaseChannel specific data.
+ * @note    It is empty because @p BaseChannel is only an interface without
+ *          implementation.
+ */
+#define _base_channel_data                                                  \
+  _base_sequential_stream_data
+
+/**
+ * @extends BaseSequentialStreamVMT
+ *
+ * @brief   @p BaseChannel virtual methods table.
+ */
+struct BaseChannelVMT {
+  _base_channel_methods
+};
+
+/**
+ * @extends BaseSequentialStream
+ *
+ * @brief   Base channel class.
+ * @details This class represents a generic, byte-wide, I/O channel. This class
+ *          introduces generic I/O primitives with timeout specification.
+ */
+typedef struct {
+  /** @brief Virtual Methods Table.*/
+  const struct BaseChannelVMT *vmt;
+  _base_channel_data
+} BaseChannel;
+
+/**
+ * @name    Macro Functions (BaseChannel)
+ * @{
+ */
+/**
+ * @brief   Channel blocking byte write with timeout.
+ * @details This function writes a byte value to a channel. If the channel
+ *          is not ready to accept data then the calling thread is suspended.
+ *
+ * @param[in] ip        pointer to a @p BaseChannel or derived class
+ * @param[in] b         the byte value to be written to the channel
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval STM_OK       if the operation succeeded.
+ * @retval STM_TIMEOUT  if the specified time expired.
+ * @retval STM_RESET    if the channel associated queue (if any) was reset.
+ *
+ * @api
+ */
+#define chnPutTimeout(ip, b, time) ((ip)->vmt->putt(ip, b, time))
+
+/**
+ * @brief   Channel blocking byte read with timeout.
+ * @details This function reads a byte value from a channel. If the data
+ *          is not available then the calling thread is suspended.
+ *
+ * @param[in] ip        pointer to a @p BaseChannel or derived class
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              A byte value from the queue.
+ * @retval STM_TIMEOUT  if the specified time expired.
+ * @retval STM_RESET    if the channel associated queue (if any) has been
+ *                      reset.
+ *
+ * @api
+ */
+#define chnGetTimeout(ip, time) ((ip)->vmt->gett(ip, time))
+
+/**
+ * @brief   Channel blocking write.
+ * @details The function writes data from a buffer to a channel. If the channel
+ *          is not ready to accept data then the calling thread is suspended.
+ *
+ * @param[in] ip        pointer to a @p BaseChannel or derived class
+ * @param[out] bp       pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred
+ *
+ * @return              The number of bytes transferred.
+ *
+ * @api
+ */
+#define chnWrite(ip, bp, n) streamWrite(ip, bp, n)
+
+/**
+ * @brief   Channel blocking write with timeout.
+ * @details The function writes data from a buffer to a channel. If the channel
+ *          is not ready to accept data then the calling thread is suspended.
+ *
+ * @param[in] ip        pointer to a @p BaseChannel or derived class
+ * @param[out] bp       pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The number of bytes transferred.
+ *
+ * @api
+ */
+#define chnWriteTimeout(ip, bp, n, time) ((ip)->vmt->writet(ip, bp, n, time))
+
+/**
+ * @brief   Channel blocking read.
+ * @details The function reads data from a channel into a buffer. If the data
+ *          is not available then the calling thread is suspended.
+ *
+ * @param[in] ip        pointer to a @p BaseChannel or derived class
+ * @param[in] bp        pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred
+ *
+ * @return              The number of bytes transferred.
+ *
+ * @api
+ */
+#define chnRead(ip, bp, n) streamRead(ip, bp, n)
+
+/**
+ * @brief   Channel blocking read with timeout.
+ * @details The function reads data from a channel into a buffer. If the data
+ *          is not available then the calling thread is suspended.
+ *
+ * @param[in] ip        pointer to a @p BaseChannel or derived class
+ * @param[in] bp        pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The number of bytes transferred.
+ *
+ * @api
+ */
+#define chnReadTimeout(ip, bp, n, time) ((ip)->vmt->readt(ip, bp, n, time))
+/** @} */
+
+/**
+ * @name    I/O status flags added to the event listener
+ * @{
+ */
+/** @brief No pending conditions.*/
+#define CHN_NO_ERROR            0
+/** @brief Connection happened.*/
+#define CHN_CONNECTED           1
+/** @brief Disconnection happened.*/
+#define CHN_DISCONNECTED        2
+/** @brief Data available in the input queue.*/
+#define CHN_INPUT_AVAILABLE     4
+/** @brief Output queue empty.*/
+#define CHN_OUTPUT_EMPTY        8
+/** @brief Transmission end.*/
+#define CHN_TRANSMISSION_END    16
+/** @} */
+
+/**
+ * @brief   @p BaseAsynchronousChannel specific methods.
+ */
+#define _base_asynchronous_channel_methods                                  \
+  _base_channel_methods                                                     \
+
+/**
+ * @brief   @p BaseAsynchronousChannel specific data.
+ */
+#define _base_asynchronous_channel_data                                     \
+  _base_channel_data                                                        \
+  /* I/O condition event source.*/                                          \
+  event_source_t        event;
+
+/**
+ * @extends BaseChannelVMT
+ *
+ * @brief   @p BaseAsynchronousChannel virtual methods table.
+ */
+struct BaseAsynchronousChannelVMT {
+  _base_asynchronous_channel_methods
+};
+
+/**
+ * @extends BaseChannel
+ *
+ * @brief   Base asynchronous channel class.
+ * @details This class extends @p BaseChannel by adding event sources fields
+ *          for asynchronous I/O for use in an event-driven environment.
+ */
+typedef struct {
+  /** @brief Virtual Methods Table.*/
+  const struct BaseAsynchronousChannelVMT *vmt;
+  _base_asynchronous_channel_data
+} BaseAsynchronousChannel;
+
+/**
+ * @name    Macro Functions (BaseAsynchronousChannel)
+ * @{
+ */
+/**
+ * @brief   Returns the I/O condition event source.
+ * @details The event source is broadcasted when an I/O condition happens.
+ *
+ * @param[in] ip        pointer to a @p BaseAsynchronousChannel or derived
+ *                      class
+ * @return              A pointer to an @p EventSource object.
+ *
+ * @api
+ */
+#define chnGetEventSource(ip) (&((ip)->event))
+
+/**
+ * @brief   Adds status flags to the listeners's flags mask.
+ * @details This function is usually called from the I/O ISRs in order to
+ *          notify I/O conditions such as data events, errors, signal
+ *          changes etc.
+ *
+ * @param[in] ip        pointer to a @p BaseAsynchronousChannel or derived
+ *                      class
+ * @param[in] flags     condition flags to be added to the listener flags mask
+ *
+ * @iclass
+ */
+#define chnAddFlagsI(ip, flags) {                                           \
+  osalEventBroadcastFlagsI(&(ip)->event, flags);                            \
+}
+/** @} */
+
+#endif /* _HAL_CHANNELS_H_ */
+
+/** @} */
diff --git a/os/hal/include/hal_ioblock.h b/os/hal/include/hal_ioblock.h
new file mode 100644
index 000000000..f759a5dff
--- /dev/null
+++ b/os/hal/include/hal_ioblock.h
@@ -0,0 +1,269 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    hal_ioblock.h
+ * @brief   I/O block devices access.
+ * @details This header defines an abstract interface useful to access generic
+ *          I/O block devices in a standardized way.
+ *
+ * @addtogroup IO_BLOCK
+ * @details This module defines an abstract interface for accessing generic
+ *          block devices.<br>
+ *          Note that no code is present, just abstract interfaces-like
+ *          structures, you should look at the system as to a set of
+ *          abstract C++ classes (even if written in C). This system
+ *          has then advantage to make the access to block devices
+ *          independent from the implementation logic.
+ * @{
+ */
+
+#ifndef _HAL_IOBLOCK_H_
+#define _HAL_IOBLOCK_H_
+
+/**
+ * @brief   Driver state machine possible states.
+ */
+typedef enum {
+  BLK_UNINIT = 0,                   /**< Not initialized.                   */
+  BLK_STOP = 1,                     /**< Stopped.                           */
+  BLK_ACTIVE = 2,                   /**< Interface active.                  */
+  BLK_CONNECTING = 3,               /**< Connection in progress.            */
+  BLK_DISCONNECTING = 4,            /**< Disconnection in progress.         */
+  BLK_READY = 5,                    /**< Device ready.                      */
+  BLK_READING = 6,                  /**< Read operation in progress.        */
+  BLK_WRITING = 7,                  /**< Write operation in progress.       */
+  BLK_SYNCING = 8                   /**< Sync. operation in progress.       */
+} blkstate_t;
+
+/**
+ * @brief   Block device info.
+ */
+typedef struct {
+  uint32_t      blk_size;           /**< @brief Block size in bytes.        */
+  uint32_t      blk_num;            /**< @brief Total number of blocks.     */
+} BlockDeviceInfo;
+
+/**
+ * @brief   @p BaseBlockDevice specific methods.
+ */
+#define _base_block_device_methods                                          \
+  /* Removable media detection.*/                                           \
+  bool (*is_inserted)(void *instance);                                      \
+  /* Removable write protection detection.*/                                \
+  bool (*is_protected)(void *instance);                                     \
+  /* Connection to the block device.*/                                      \
+  bool (*connect)(void *instance);                                          \
+  /* Disconnection from the block device.*/                                 \
+  bool (*disconnect)(void *instance);                                       \
+  /* Reads one or more blocks.*/                                            \
+  bool (*read)(void *instance, uint32_t startblk,                           \
+                 uint8_t *buffer, uint32_t n);                              \
+  /* Writes one or more blocks.*/                                           \
+  bool (*write)(void *instance, uint32_t startblk,                          \
+                  const uint8_t *buffer, uint32_t n);                       \
+  /* Write operations synchronization.*/                                    \
+  bool (*sync)(void *instance);                                             \
+  /* Obtains info about the media.*/                                        \
+  bool (*get_info)(void *instance, BlockDeviceInfo *bdip);
+
+/**
+ * @brief   @p BaseBlockDevice specific data.
+ */
+#define _base_block_device_data                                             \
+  /* Driver state.*/                                                        \
+  blkstate_t            state;
+
+/**
+ * @brief   @p BaseBlockDevice virtual methods table.
+ */
+struct BaseBlockDeviceVMT {
+  _base_block_device_methods
+};
+
+/**
+ * @brief   Base block device class.
+ * @details This class represents a generic, block-accessible, device.
+ */
+typedef struct {
+  /** @brief Virtual Methods Table.*/
+  const struct BaseBlockDeviceVMT *vmt;
+  _base_block_device_data
+} BaseBlockDevice;
+
+/**
+ * @name    Macro Functions (BaseBlockDevice)
+ * @{
+ */
+/**
+ * @brief   Returns the driver state.
+ * @note    Can be called in ISR context.
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ *
+ * @return              The driver state.
+ *
+ * @special
+ */
+#define blkGetDriverState(ip) ((ip)->state)
+
+/**
+ * @brief   Determines if the device is transferring data.
+ * @note    Can be called in ISR context.
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ *
+ * @return              The driver state.
+ * @retval FALSE        the device is not transferring data.
+ * @retval TRUE         the device not transferring data.
+ *
+ * @special
+ */
+#define blkIsTransferring(ip) ((((ip)->state) == BLK_CONNECTING) ||         \
+                               (((ip)->state) == BLK_DISCONNECTING) ||      \
+                               (((ip)->state) == BLK_READING) ||            \
+                               (((ip)->state) == BLK_WRITING))
+
+/**
+ * @brief   Returns the media insertion status.
+ * @note    On some implementations this function can only be called if the
+ *          device is not transferring data.
+ *          The function @p blkIsTransferring() should be used before calling
+ *          this function.
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ *
+ * @return              The media state.
+ * @retval FALSE        media not inserted.
+ * @retval TRUE         media inserted.
+ *
+ * @api
+ */
+#define blkIsInserted(ip) ((ip)->vmt->is_inserted(ip))
+
+/**
+ * @brief   Returns the media write protection status.
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ *
+ * @return              The media state.
+ * @retval FALSE        writable media.
+ * @retval TRUE         non writable media.
+ *
+ * @api
+ */
+#define blkIsWriteProtected(ip) ((ip)->vmt->is_protected(ip))
+
+/**
+ * @brief   Performs the initialization procedure on the block device.
+ * @details This function should be performed before I/O operations can be
+ *          attempted on the block device and after insertion has been
+ *          confirmed using @p blkIsInserted().
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @api
+ */
+#define blkConnect(ip) ((ip)->vmt->connect(ip))
+
+/**
+ * @brief   Terminates operations on the block device.
+ * @details This operation safely terminates operations on the block device.
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @api
+ */
+#define blkDisconnect(ip) ((ip)->vmt->disconnect(ip))
+
+/**
+ * @brief   Reads one or more blocks.
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ * @param[in] startblk  first block to read
+ * @param[out] buf      pointer to the read buffer
+ * @param[in] n         number of blocks to read
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @api
+ */
+#define blkRead(ip, startblk, buf, n)                                       \
+  ((ip)->vmt->read(ip, startblk, buf, n))
+
+/**
+ * @brief   Writes one or more blocks.
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ * @param[in] startblk  first block to write
+ * @param[out] buf      pointer to the write buffer
+ * @param[in] n         number of blocks to write
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @api
+ */
+#define blkWrite(ip, startblk, buf, n)                                      \
+  ((ip)->vmt->write(ip, startblk, buf, n))
+
+/**
+ * @brief   Ensures write synchronization.
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @api
+ */
+#define blkSync(ip) ((ip)->vmt->sync(ip))
+
+/**
+ * @brief   Returns a media information structure.
+ *
+ * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
+ * @param[out] bdip     pointer to a @p BlockDeviceInfo structure
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @api
+ */
+#define blkGetInfo(ip, bdip) ((ip)->vmt->get_info(ip, bdip))
+
+/** @} */
+
+#endif /* _HAL_IOBLOCK_H_ */
+
+/** @} */
diff --git a/os/hal/include/hal_mmcsd.h b/os/hal/include/hal_mmcsd.h
new file mode 100644
index 000000000..09a789549
--- /dev/null
+++ b/os/hal/include/hal_mmcsd.h
@@ -0,0 +1,279 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    hal_mmcsd.h
+ * @brief   MMC/SD cards common header.
+ * @details This header defines an abstract interface useful to access MMC/SD
+ *          I/O block devices in a standardized way.
+ *
+ * @addtogroup MMCSD
+ * @{
+ */
+
+#ifndef _HAL_MMCSD_H_
+#define _HAL_MMCSD_H_
+
+#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Fixed block size for MMC/SD block devices.
+ */
+#define MMCSD_BLOCK_SIZE                512
+
+/**
+ * @brief   Mask of error bits in R1 responses.
+ */
+#define MMCSD_R1_ERROR_MASK             0xFDFFE008
+
+/**
+ * @brief   Fixed pattern for CMD8.
+ */
+#define MMCSD_CMD8_PATTERN              0x000001AA
+
+/**
+ * @name    SD/MMC status conditions
+ * @{
+ */
+#define MMCSD_STS_IDLE                  0
+#define MMCSD_STS_READY                 1
+#define MMCSD_STS_IDENT                 2
+#define MMCSD_STS_STBY                  3
+#define MMCSD_STS_TRAN                  4
+#define MMCSD_STS_DATA                  5
+#define MMCSD_STS_RCV                   6
+#define MMCSD_STS_PRG                   7
+#define MMCSD_STS_DIS                   8
+/** @} */
+
+/**
+ * @name    SD/MMC commands
+ * @{
+ */
+#define MMCSD_CMD_GO_IDLE_STATE         0
+#define MMCSD_CMD_INIT                  1
+#define MMCSD_CMD_ALL_SEND_CID          2
+#define MMCSD_CMD_SEND_RELATIVE_ADDR    3
+#define MMCSD_CMD_SET_BUS_WIDTH         6
+#define MMCSD_CMD_SEL_DESEL_CARD        7
+#define MMCSD_CMD_SEND_IF_COND          8
+#define MMCSD_CMD_SEND_CSD              9
+#define MMCSD_CMD_SEND_CID              10
+#define MMCSD_CMD_STOP_TRANSMISSION     12
+#define MMCSD_CMD_SEND_STATUS           13
+#define MMCSD_CMD_SET_BLOCKLEN          16
+#define MMCSD_CMD_READ_SINGLE_BLOCK     17
+#define MMCSD_CMD_READ_MULTIPLE_BLOCK   18
+#define MMCSD_CMD_SET_BLOCK_COUNT       23
+#define MMCSD_CMD_WRITE_BLOCK           24
+#define MMCSD_CMD_WRITE_MULTIPLE_BLOCK  25
+#define MMCSD_CMD_ERASE_RW_BLK_START    32
+#define MMCSD_CMD_ERASE_RW_BLK_END      33
+#define MMCSD_CMD_ERASE                 38
+#define MMCSD_CMD_APP_OP_COND           41
+#define MMCSD_CMD_LOCK_UNLOCK           42
+#define MMCSD_CMD_APP_CMD               55
+#define MMCSD_CMD_READ_OCR              58
+/** @} */
+
+/**
+ * @name   CSD record offsets
+ */
+/**
+ * @brief  Slice position of values in CSD register.
+ */
+/* CSD version 2.0 */
+#define MMCSD_CSD_20_CRC_SLICE                  7,1
+#define MMCSD_CSD_20_FILE_FORMAT_SLICE          11,10
+#define MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE    12,12
+#define MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE   13,13
+#define MMCSD_CSD_20_COPY_SLICE                 14,14
+#define MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE      15,15
+#define MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE     21,21
+#define MMCSD_CSD_20_WRITE_BL_LEN_SLICE         25,12
+#define MMCSD_CSD_20_R2W_FACTOR_SLICE           28,26
+#define MMCSD_CSD_20_WP_GRP_ENABLE_SLICE        31,31
+#define MMCSD_CSD_20_WP_GRP_SIZE_SLICE          38,32
+#define MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE    45,39
+#define MMCSD_CSD_20_ERASE_BLK_EN_SLICE         46,46
+#define MMCSD_CSD_20_C_SIZE_SLICE               69,48
+#define MMCSD_CSD_20_DSR_IMP_SLICE              76,76
+#define MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE    77,77
+#define MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE   78,78
+#define MMCSD_CSD_20_READ_BL_PARTIAL_SLICE      79,79
+#define MMCSD_CSD_20_READ_BL_LEN_SLICE          83,80
+#define MMCSD_CSD_20_CCC_SLICE                  95,84
+#define MMCSD_CSD_20_TRANS_SPEED_SLICE          103,96
+#define MMCSD_CSD_20_NSAC_SLICE                 111,104
+#define MMCSD_CSD_20_TAAC_SLICE                 119,112
+#define MMCSD_CSD_20_STRUCTURE_SLICE            127,126
+
+/* CSD version 1.0 */
+#define MMCSD_CSD_10_CRC_SLICE                  MMCSD_CSD_20_CRC_SLICE
+#define MMCSD_CSD_10_FILE_FORMAT_SLICE          MMCSD_CSD_20_FILE_FORMAT_SLICE
+#define MMCSD_CSD_10_TMP_WRITE_PROTECT_SLICE    MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE
+#define MMCSD_CSD_10_PERM_WRITE_PROTECT_SLICE   MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE
+#define MMCSD_CSD_10_COPY_SLICE                 MMCSD_CSD_20_COPY_SLICE
+#define MMCSD_CSD_10_FILE_FORMAT_GRP_SLICE      MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE
+#define MMCSD_CSD_10_WRITE_BL_PARTIAL_SLICE     MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE
+#define MMCSD_CSD_10_WRITE_BL_LEN_SLICE         MMCSD_CSD_20_WRITE_BL_LEN_SLICE
+#define MMCSD_CSD_10_R2W_FACTOR_SLICE           MMCSD_CSD_20_R2W_FACTOR_SLICE
+#define MMCSD_CSD_10_WP_GRP_ENABLE_SLICE        MMCSD_CSD_20_WP_GRP_ENABLE_SLICE
+#define MMCSD_CSD_10_WP_GRP_SIZE_SLICE          MMCSD_CSD_20_WP_GRP_SIZE_SLICE
+#define MMCSD_CSD_10_ERASE_SECTOR_SIZE_SLICE    MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE
+#define MMCSD_CSD_10_ERASE_BLK_EN_SLICE         MMCSD_CSD_20_ERASE_BLK_EN_SLICE
+#define MMCSD_CSD_10_C_SIZE_MULT_SLICE          49,47
+#define MMCSD_CSD_10_VDD_W_CURR_MAX_SLICE       52,50
+#define MMCSD_CSD_10_VDD_W_CURR_MIN_SLICE       55,53
+#define MMCSD_CSD_10_VDD_R_CURR_MAX_SLICE       58,56
+#define MMCSD_CSD_10_VDD_R_CURR_MIX_SLICE       61,59
+#define MMCSD_CSD_10_C_SIZE_SLICE               73,62
+#define MMCSD_CSD_10_DSR_IMP_SLICE              MMCSD_CSD_20_DSR_IMP_SLICE
+#define MMCSD_CSD_10_READ_BLK_MISALIGN_SLICE    MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE
+#define MMCSD_CSD_10_WRITE_BLK_MISALIGN_SLICE   MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE
+#define MMCSD_CSD_10_READ_BL_PARTIAL_SLICE      MMCSD_CSD_20_READ_BL_PARTIAL_SLICE
+#define MMCSD_CSD_10_READ_BL_LEN_SLICE          83, 80
+#define MMCSD_CSD_10_CCC_SLICE                  MMCSD_CSD_20_CCC_SLICE
+#define MMCSD_CSD_10_TRANS_SPEED_SLICE          MMCSD_CSD_20_TRANS_SPEED_SLICE
+#define MMCSD_CSD_10_NSAC_SLICE                 MMCSD_CSD_20_NSAC_SLICE
+#define MMCSD_CSD_10_TAAC_SLICE                 MMCSD_CSD_20_TAAC_SLICE
+#define MMCSD_CSD_10_STRUCTURE_SLICE            MMCSD_CSD_20_STRUCTURE_SLICE
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   @p MMCSDBlockDevice specific methods.
+ */
+#define _mmcsd_block_device_methods                                         \
+  _base_block_device_methods
+
+/**
+ * @brief   @p MMCSDBlockDevice specific data.
+ * @note    It is empty because @p MMCSDBlockDevice is only an interface
+ *          without implementation.
+ */
+#define _mmcsd_block_device_data                                            \
+  _base_block_device_data                                                   \
+  /* Card CID.*/                                                            \
+  uint32_t              cid[4];                                             \
+  /* Card CSD.*/                                                            \
+  uint32_t              csd[4];                                             \
+  /* Total number of blocks in card.*/                                      \
+  uint32_t              capacity;
+
+/**
+ * @extends BaseBlockDeviceVMT
+ *
+ * @brief   @p MMCSDBlockDevice virtual methods table.
+ */
+struct MMCSDBlockDeviceVMT {
+  _base_block_device_methods
+};
+
+/**
+ * @extends BaseBlockDevice
+ *
+ * @brief   MCC/SD block device class.
+ * @details This class represents a, block-accessible, MMC/SD device.
+ */
+typedef struct {
+  /** @brief Virtual Methods Table.*/
+  const struct MMCSDBlockDeviceVMT *vmt;
+  _mmcsd_block_device_data
+} MMCSDBlockDevice;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    R1 response utilities
+ * @{
+ */
+/**
+ * @brief   Evaluates to @p TRUE if the R1 response contains error flags.
+ *
+ * @param[in] r1        the r1 response
+ */
+#define MMCSD_R1_ERROR(r1)              (((r1) & MMCSD_R1_ERROR_MASK) != 0)
+
+/**
+ * @brief   Returns the status field of an R1 response.
+ *
+ * @param[in] r1        the r1 response
+ */
+#define MMCSD_R1_STS(r1)                (((r1) >> 9) & 15)
+
+/**
+ * @brief   Evaluates to @p TRUE if the R1 response indicates a locked card.
+ *
+ * @param[in] r1        the r1 response
+ */
+#define MMCSD_R1_IS_CARD_LOCKED(r1)     (((r1) >> 21) & 1)
+/** @} */
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Returns the card capacity in blocks.
+ *
+ * @param[in] ip        pointer to a @p MMCSDBlockDevice or derived class
+ *
+ * @return              The card capacity.
+ *
+ * @api
+ */
+#define mmcsdGetCardCapacity(ip)  ((ip)->capacity)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  uint32_t mmcsdGetCapacity(uint32_t csd[4]);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_MMC_SPI || HAL_USE_MMC_SDC*/
+
+#endif /* _HAL_MMCSD_H_ */
+
+/** @} */
diff --git a/os/hal/include/hal_queues.h b/os/hal/include/hal_queues.h
new file mode 100644
index 000000000..4eb21d076
--- /dev/null
+++ b/os/hal/include/hal_queues.h
@@ -0,0 +1,403 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    hal_queues.h
+ * @brief   I/O Queues macros and structures.
+ *
+ * @addtogroup io_queues
+ * @{
+ */
+
+#ifndef _HAL_QUEUES_H_
+#define _HAL_QUEUES_H_
+
+/* The ChibiOS/RT kernel provides the following definitions by itself, this
+   check is performed in order to avoid conflicts. */
+#if !defined(_CHIBIOS_RT_) || !CH_CFG_USE_QUEUES
+
+/**
+ * @name    Queue functions returned status value
+ * @{
+ */
+#define Q_OK            MSG_OK      /**< @brief Operation successful.       */
+#define Q_TIMEOUT       MSG_TIMEOUT /**< @brief Timeout condition.          */
+#define Q_RESET         MSG_RESET   /**< @brief Queue has been reset.       */
+#define Q_EMPTY         -3          /**< @brief Queue empty.                */
+#define Q_FULL          -4          /**< @brief Queue full,                 */
+/** @} */
+
+/**
+ * @brief   Type of a generic I/O queue structure.
+ */
+typedef struct io_queue_t io_queue_t;
+
+/** @brief Queue notification callback type.*/
+typedef void (*qnotify_t)(io_queue_t *qp);
+
+/**
+ * @brief   Generic I/O queue structure.
+ * @details This structure represents a generic Input or Output asymmetrical
+ *          queue. The queue is asymmetrical because one end is meant to be
+ *          accessed from a thread context, and thus can be blocking, the other
+ *          end is accessible from interrupt handlers or from within a kernel
+ *          lock zone (see <b>I-Locked</b> and <b>S-Locked</b> states in
+ *          @ref system_states) and is non-blocking.
+ */
+struct io_queue_t {
+  threads_queue_t       q_waiting;  /**< @brief Waiting thread.             */
+  size_t                q_counter;  /**< @brief Resources counter.          */
+  uint8_t               *q_buffer;  /**< @brief Pointer to the queue buffer.*/
+  uint8_t               *q_top;     /**< @brief Pointer to the first
+                                         location after the buffer.         */
+  uint8_t               *q_wrptr;   /**< @brief Write pointer.              */
+  uint8_t               *q_rdptr;   /**< @brief Read pointer.               */
+  qnotify_t             q_notify;   /**< @brief Data notification callback. */
+  void                  *q_link;    /**< @brief Application defined field.  */
+};
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Returns the queue's buffer size.
+ *
+ * @param[in] qp        pointer to a @p io_queue_t structure.
+ * @return              The buffer size.
+ *
+ * @iclass
+ */
+#define qSizeI(qp) ((size_t)((qp)->q_top - (qp)->q_buffer))
+
+/**
+ * @brief   Queue space.
+ * @details Returns the used space if used on an input queue or the empty
+ *          space if used on an output queue.
+ *
+ * @param[in] qp        pointer to a @p io_queue_t structure.
+ * @return              The buffer space.
+ *
+ * @iclass
+ */
+#define qSpaceI(qp) ((qp)->q_counter)
+
+/**
+ * @brief   Returns the queue application-defined link.
+ * @note    This function can be called in any context.
+ *
+ * @param[in] qp        pointer to a @p io_queue_t structure.
+ * @return              The application-defined link.
+ *
+ * @special
+ */
+#define qGetLink(qp) ((qp)->q_link)
+/** @} */
+
+/**
+ * @extends io_queue_t
+ *
+ * @brief   Type of an input queue structure.
+ * @details This structure represents a generic asymmetrical input queue.
+ *          Writing to the queue is non-blocking and can be performed from
+ *          interrupt handlers or from within a kernel lock zone (see
+ *          <b>I-Locked</b> and <b>S-Locked</b> states in @ref system_states).
+ *          Reading the queue can be a blocking operation and is supposed to
+ *          be performed by a system thread.
+ */
+typedef io_queue_t input_queue_t;
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Returns the filled space into an input queue.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @return              The number of full bytes in the queue.
+ * @retval 0            if the queue is empty.
+ *
+ * @iclass
+ */
+#define iqGetFullI(iqp) qSpaceI(iqp)
+
+/**
+ * @brief   Returns the empty space into an input queue.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @return              The number of empty bytes in the queue.
+ * @retval 0            if the queue is full.
+ *
+ * @iclass
+ */
+#define iqGetEmptyI(iqp) (qSizeI(iqp) - qSpaceI(iqp))
+
+/**
+ * @brief   Evaluates to @p TRUE if the specified input queue is empty.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure.
+ * @return              The queue status.
+ * @retval FALSE        if the queue is not empty.
+ * @retval TRUE         if the queue is empty.
+ *
+ * @iclass
+ */
+#define iqIsEmptyI(iqp) ((bool)(qSpaceI(iqp) <= 0))
+
+/**
+ * @brief   Evaluates to @p TRUE if the specified input queue is full.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure.
+ * @return              The queue status.
+ * @retval FALSE        if the queue is not full.
+ * @retval TRUE         if the queue is full.
+ *
+ * @iclass
+ */
+#define iqIsFullI(iqp) ((bool)(((iqp)->q_wrptr == (iqp)->q_rdptr) &&        \
+                               ((iqp)->q_counter != 0)))
+
+/**
+ * @brief   Input queue read.
+ * @details This function reads a byte value from an input queue. If the queue
+ *          is empty then the calling thread is suspended until a byte arrives
+ *          in the queue.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @return              A byte value from the queue.
+ * @retval Q_RESET      if the queue has been reset.
+ *
+ * @api
+ */
+#define iqGet(iqp) iqGetTimeout(iqp, TIME_INFINITE)
+/** @} */
+
+/**
+ * @brief   Data part of a static input queue initializer.
+ * @details This macro should be used when statically initializing an
+ *          input queue that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the input queue variable
+ * @param[in] buffer    pointer to the queue buffer area
+ * @param[in] size      size of the queue buffer area
+ * @param[in] inotify   input notification callback pointer
+ * @param[in] link      application defined pointer
+ */
+#define _INPUTQUEUE_DATA(name, buffer, size, inotify, link) {               \
+  NULL,                                                                     \
+  0,                                                                        \
+  (uint8_t *)(buffer),                                                      \
+  (uint8_t *)(buffer) + (size),                                             \
+  (uint8_t *)(buffer),                                                      \
+  (uint8_t *)(buffer),                                                      \
+  (inotify),                                                                \
+  (link)                                                                    \
+}
+
+/**
+ * @brief   Static input queue initializer.
+ * @details Statically initialized input queues require no explicit
+ *          initialization using @p iqInit().
+ *
+ * @param[in] name      the name of the input queue variable
+ * @param[in] buffer    pointer to the queue buffer area
+ * @param[in] size      size of the queue buffer area
+ * @param[in] inotify   input notification callback pointer
+ * @param[in] link      application defined pointer
+ */
+#define INPUTQUEUE_DECL(name, buffer, size, inotify, link)                  \
+  input_queue_t name = _INPUTQUEUE_DATA(name, buffer, size, inotify, link)
+
+/**
+ * @extends io_queue_t
+ *
+ * @brief   Type of an output queue structure.
+ * @details This structure represents a generic asymmetrical output queue.
+ *          Reading from the queue is non-blocking and can be performed from
+ *          interrupt handlers or from within a kernel lock zone (see
+ *          <b>I-Locked</b> and <b>S-Locked</b> states in @ref system_states).
+ *          Writing the queue can be a blocking operation and is supposed to
+ *          be performed by a system thread.
+ */
+typedef io_queue_t output_queue_t;
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Returns the filled space into an output queue.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @return              The number of full bytes in the queue.
+ * @retval 0            if the queue is empty.
+ *
+ * @iclass
+ */
+#define oqGetFullI(oqp) (qSizeI(oqp) - qSpaceI(oqp))
+
+/**
+ * @brief   Returns the empty space into an output queue.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @return              The number of empty bytes in the queue.
+ * @retval 0            if the queue is full.
+ *
+ * @iclass
+ */
+#define oqGetEmptyI(oqp) qSpaceI(oqp)
+
+/**
+ * @brief   Evaluates to @p TRUE if the specified output queue is empty.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure.
+ * @return              The queue status.
+ * @retval FALSE        if the queue is not empty.
+ * @retval TRUE         if the queue is empty.
+ *
+ * @iclass
+ */
+#define oqIsEmptyI(oqp) ((bool)(((oqp)->q_wrptr == (oqp)->q_rdptr) &&       \
+                                ((oqp)->q_counter != 0)))
+
+/**
+ * @brief   Evaluates to @p TRUE if the specified output queue is full.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure.
+ * @return              The queue status.
+ * @retval FALSE        if the queue is not full.
+ * @retval TRUE         if the queue is full.
+ *
+ * @iclass
+ */
+#define oqIsFullI(oqp) ((bool)(qSpaceI(oqp) <= 0))
+
+/**
+ * @brief   Output queue write.
+ * @details This function writes a byte value to an output queue. If the queue
+ *          is full then the calling thread is suspended until there is space
+ *          in the queue.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @param[in] b         the byte value to be written in the queue
+ * @return              The operation status.
+ * @retval Q_OK         if the operation succeeded.
+ * @retval Q_RESET      if the queue has been reset.
+ *
+ * @api
+ */
+#define oqPut(oqp, b) oqPutTimeout(oqp, b, TIME_INFINITE)
+ /** @} */
+
+/**
+ * @brief   Data part of a static output queue initializer.
+ * @details This macro should be used when statically initializing an
+ *          output queue that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the output queue variable
+ * @param[in] buffer    pointer to the queue buffer area
+ * @param[in] size      size of the queue buffer area
+ * @param[in] onotify   output notification callback pointer
+ * @param[in] link      application defined pointer
+ */
+#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) {              \
+  NULL,                                                                     \
+  (size),                                                                   \
+  (uint8_t *)(buffer),                                                      \
+  (uint8_t *)(buffer) + (size),                                             \
+  (uint8_t *)(buffer),                                                      \
+  (uint8_t *)(buffer),                                                      \
+  (onotify),                                                                \
+  (link)                                                                    \
+}
+
+/**
+ * @brief   Static output queue initializer.
+ * @details Statically initialized output queues require no explicit
+ *          initialization using @p oqInit().
+ *
+ * @param[in] name      the name of the output queue variable
+ * @param[in] buffer    pointer to the queue buffer area
+ * @param[in] size      size of the queue buffer area
+ * @param[in] onotify   output notification callback pointer
+ * @param[in] link      application defined pointer
+ */
+#define OUTPUTQUEUE_DECL(name, buffer, size, onotify, link)                 \
+  output_queue_t name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void iqObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size,
+                    qnotify_t infy, void *link);
+  void iqResetI(input_queue_t *iqp);
+  msg_t iqPutI(input_queue_t *iqp, uint8_t b);
+  msg_t iqGetTimeout(input_queue_t *iqp, systime_t time);
+  size_t iqReadTimeout(input_queue_t *iqp, uint8_t *bp,
+                       size_t n, systime_t time);
+
+  void oqObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size,
+                    qnotify_t onfy, void *link);
+  void oqResetI(output_queue_t *oqp);
+  msg_t oqPutTimeout(output_queue_t *oqp, uint8_t b, systime_t time);
+  msg_t oqGetI(output_queue_t *oqp);
+  size_t oqWriteTimeout(output_queue_t *oqp, const uint8_t *bp,
+                        size_t n, systime_t time);
+#ifdef __cplusplus
+}
+#endif
+
+
+#else /* defined(_CHIBIOS_RT_) && CH_USE_QUEUES */
+
+/* If ChibiOS is being used and its own queues subsystem is activated then
+   this module will use the ChibiOS queues code.*/
+#define qSizeI(qp)                          chQSizeI(qp)
+#define qSpaceI(qp)                         chQSpaceI(qp)
+#define qGetLink(qp)                        chQGetLinkX(qp)
+#define iqGetFullI(iqp)                     chIQGetFullI(iqp)
+#define iqGetEmptyI(iqp)                    chIQGetEmptyI(iqp)
+#define iqIsEmptyI(iqp)                     chIQIsEmptyI(iqp)
+#define iqIsFullI(iqp)                      chIQIsFullI(iqp)
+#define iqGet(iqp)                          chIQGet(iqp)
+#define oqGetFullI(oqp)                     chOQGetFullI(oqp)
+#define oqGetEmptyI(oqp)                    chOQGetEmptyI(oqp)
+#define oqIsEmptyI(oqp)                     chOQIsEmptyI(oqp)
+#define oqIsFullI(oqp)                      chOQIsFullI(oqp)
+#define oqPut(oqp, b)                       chOQPut(oqp, b)
+#define iqObjectInit(iqp, bp, size, infy, link)                             \
+  chIQObjectInit(iqp, bp, size, infy, link)
+#define iqResetI(iqp)                       chIQResetI(iqp)
+#define iqPutI(iqp, b)                      chIQPutI(iqp, b)
+#define iqGetTimeout(iqp, time)             chIQGetTimeout(iqp, time)
+#define iqReadTimeout(iqp, bp, n, time)     chIQReadTimeout(iqp, bp, n, time)
+#define oqObjectInit(oqp, bp, size, onfy, link)                             \
+  chOQObjectInit(oqp, bp, size, onfy, link)
+#define oqResetI(oqp)                       chOQResetI(oqp)
+#define oqPutTimeout(oqp, b, time)          chOQPutTimeout(oqp, b, time)
+#define oqGetI(oqp)                         chOQGetI(oqp)
+#define oqWriteTimeout(oqp, bp, n, time)    chOQWriteTimeout(oqp, bp, n, time)
+
+#endif /* defined(_CHIBIOS_RT_) && CH_USE_QUEUES */
+
+#endif /* _HAL_QUEUES_H_ */
+
+/** @} */
diff --git a/os/hal/include/hal_streams.h b/os/hal/include/hal_streams.h
new file mode 100644
index 000000000..e18a7e461
--- /dev/null
+++ b/os/hal/include/hal_streams.h
@@ -0,0 +1,162 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    hal_streams.h
+ * @brief   Data streams.
+ * @details This header defines abstract interfaces useful to access generic
+ *          data streams in a standardized way.
+ *
+ * @addtogroup data_streams
+ * @details This module define an abstract interface for generic data streams.
+ *          Note that no code is present, just abstract interfaces-like
+ *          structures, you should look at the system as to a set of
+ *          abstract C++ classes (even if written in C). This system
+ *          has then advantage to make the access to data streams
+ *          independent from the implementation logic.<br>
+ *          The stream interface can be used as base class for high level
+ *          object types such as files, sockets, serial ports, pipes etc.
+ * @{
+ */
+
+#ifndef _HAL_STREAMS_H_
+#define _HAL_STREAMS_H_
+
+/**
+ * @name    Streams return codes
+ * @{
+ */
+#define STM_OK               Q_OK
+#define STM_TIMEOUT          Q_TIMEOUT
+#define STM_RESET            Q_RESET
+/** @} */
+
+/* The ChibiOS/RT kernel provides the following definitions by itself, this
+   check is performed in order to avoid conflicts. */
+#if !defined(_CHIBIOS_RT_) || defined(__DOXYGEN__)
+
+/**
+ * @brief   BaseSequentialStream specific methods.
+ */
+#define _base_sequential_stream_methods                                     \
+  /* Stream write buffer method.*/                                          \
+  size_t (*write)(void *instance, const uint8_t *bp, size_t n);             \
+  /* Stream read buffer method.*/                                           \
+  size_t (*read)(void *instance, uint8_t *bp, size_t n);                    \
+  /* Channel put method, blocking.*/                                        \
+  msg_t (*put)(void *instance, uint8_t b);                                  \
+  /* Channel get method, blocking.*/                                        \
+  msg_t (*get)(void *instance);                                             \
+
+/**
+ * @brief   @p BaseSequentialStream specific data.
+ * @note    It is empty because @p BaseSequentialStream is only an interface
+ *          without implementation.
+ */
+#define _base_sequential_stream_data
+
+/**
+ * @brief   @p BaseSequentialStream virtual methods table.
+ */
+struct BaseSequentialStreamVMT {
+  _base_sequential_stream_methods
+};
+
+/**
+ * @brief   Base stream class.
+ * @details This class represents a generic blocking unbuffered sequential
+ *          data stream.
+ */
+typedef struct {
+  /** @brief Virtual Methods Table.*/
+  const struct BaseSequentialStreamVMT *vmt;
+  _base_sequential_stream_data
+} BaseSequentialStream;
+
+#endif /* !defined(_CHIBIOS_RT_)*/
+
+/**
+ * @name    Macro Functions (BaseSequentialStream)
+ * @{
+ */
+/**
+ * @brief   Sequential Stream write.
+ * @details The function writes data from a buffer to a stream.
+ *
+ * @param[in] ip        pointer to a @p BaseSequentialStream or derived class
+ * @param[in] bp        pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred
+ * @return              The number of bytes transferred. The return value can
+ *                      be less than the specified number of bytes if an
+ *                      end-of-file condition has been met.
+ *
+ * @api
+ */
+#define streamWrite(ip, bp, n) ((ip)->vmt->write(ip, bp, n))
+
+/**
+ * @brief   Sequential Stream read.
+ * @details The function reads data from a stream into a buffer.
+ *
+ * @param[in] ip        pointer to a @p BaseSequentialStream or derived class
+ * @param[out] bp       pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred
+ * @return              The number of bytes transferred. The return value can
+ *                      be less than the specified number of bytes if an
+ *                      end-of-file condition has been met.
+ *
+ * @api
+ */
+#define streamRead(ip, bp, n) ((ip)->vmt->read(ip, bp, n))
+
+/**
+ * @brief   Sequential Stream blocking byte write.
+ * @details This function writes a byte value to a channel. If the channel
+ *          is not ready to accept data then the calling thread is suspended.
+ *
+ * @param[in] ip        pointer to a @p BaseChannel or derived class
+ * @param[in] b         the byte value to be written to the channel
+ *
+ * @return              The operation status.
+ * @retval STM_OK       if the operation succeeded.
+ * @retval STM_RESET    if an end-of-file condition has been met.
+ *
+ * @api
+ */
+#define streamPut(ip, b) ((ip)->vmt->put(ip, b))
+
+/**
+ * @brief   Sequential Stream blocking byte read.
+ * @details This function reads a byte value from a channel. If the data
+ *          is not available then the calling thread is suspended.
+ *
+ * @param[in] ip        pointer to a @p BaseChannel or derived class
+ *
+ * @return              A byte value from the queue.
+ * @retval STM_RESET    if an end-of-file condition has been met.
+ *
+ * @api
+ */
+#define streamGet(ip) ((ip)->vmt->get(ip))
+/** @} */
+
+#endif /* _HAL_STREAMS_H_ */
+
+/** @} */
diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h
index 2e45450ee..dfae26e64 100644
--- a/os/hal/include/i2c.h
+++ b/os/hal/include/i2c.h
@@ -39,19 +39,20 @@
 /* Driver constants.                                                         */
 /*===========================================================================*/
 
+/* TODO: To be reviewed, too STM32-centric.*/
 /**
  * @name    I2C bus error conditions
  * @{
  */
-#define I2CD_NO_ERROR               0x00   /**< @brief No error.            */
-#define I2CD_BUS_ERROR              0x01   /**< @brief Bus Error.           */
-#define I2CD_ARBITRATION_LOST       0x02   /**< @brief Arbitration Lost.    */
-#define I2CD_ACK_FAILURE            0x04   /**< @brief Acknowledge Failure. */
-#define I2CD_OVERRUN                0x08   /**< @brief Overrun/Underrun.    */
-#define I2CD_PEC_ERROR              0x10   /**< @brief PEC Error in
+#define I2C_NO_ERROR               0x00    /**< @brief No error.            */
+#define I2C_BUS_ERROR              0x01    /**< @brief Bus Error.           */
+#define I2C_ARBITRATION_LOST       0x02    /**< @brief Arbitration Lost.    */
+#define I2C_ACK_FAILURE            0x04    /**< @brief Acknowledge Failure. */
+#define I2C_OVERRUN                0x08    /**< @brief Overrun/Underrun.    */
+#define I2C_PEC_ERROR              0x10    /**< @brief PEC Error in
                                                 reception.                  */
-#define I2CD_TIMEOUT                0x20   /**< @brief Hardware timeout.    */
-#define I2CD_SMB_ALERT              0x40   /**< @brief SMBus Alert.         */
+#define I2C_TIMEOUT                0x20    /**< @brief Hardware timeout.    */
+#define I2C_SMB_ALERT              0x40    /**< @brief SMBus Alert.         */
 /** @} */
 
 /*===========================================================================*/
@@ -69,10 +70,6 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if I2C_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
-#error "I2C_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
-#endif
-
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -96,6 +93,32 @@ typedef enum {
 /*===========================================================================*/
 
 /**
+ * @brief   Wakes up the waiting thread notifying no errors.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2c_wakeup_isr(i2cp) do {                                          \
+  osalSysLockFromISR();                                                     \
+  osalThreadResumeI(&(i2cp)->thread, MSG_OK);                               \
+  osalSysUnlockFromISR();                                                   \
+} while(0)
+
+/**
+ * @brief   Wakes up the waiting thread notifying errors.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2c_wakeup_error_isr(i2cp) do {                                    \
+  osalSysLockFromISR();                                                     \
+  osalThreadResumeI(&(i2cp)->thread, MSG_RESET);                            \
+  osalSysUnlockFromISR();                                                   \
+} while(0)
+
+/**
  * @brief   Wrap i2cMasterTransmitTimeout function with TIME_INFINITE timeout.
  * @api
  */
diff --git a/os/hal/include/i2s.h b/os/hal/include/i2s.h
index b2dacbb49..711ec3b5c 100644
--- a/os/hal/include/i2s.h
+++ b/os/hal/include/i2s.h
@@ -41,9 +41,6 @@
  */
 #define I2S_MODE_SLAVE          0
 #define I2S_MODE_MASTER         1
-#define I2S_MODE_TX             2
-#define I2S_MODE_RX             4
-#define I2S_MODE_TXRX           (I2S_MODE_TX | I2S_MODE_RX)
 /** @} */
 
 /*===========================================================================*/
@@ -69,11 +66,6 @@ typedef enum {
   I2S_COMPLETE = 4                  /**< Transmission complete.             */
 } i2sstate_t;
 
-/**
- * @brief   Type of a structure representing a I2S driver.
- */
-typedef struct I2SDriver I2SDriver;
-
 #include "i2s_lld.h"
 
 /*===========================================================================*/
@@ -88,6 +80,10 @@ typedef struct I2SDriver I2SDriver;
  * @brief   Starts a I2S data exchange.
  *
  * @param[in] i2sp      pointer to the @p I2SDriver object
+ * @param[in] n         size of the transmit buffer, must be even and greater
+ *                      than zero
+ * @param[out] txbuf    the pointer to the transmit buffer
+ * @param[out] rxbuf    the pointer to the receive buffer
  *
  * @iclass
  */
@@ -97,18 +93,6 @@ typedef struct I2SDriver I2SDriver;
 }
 
 /**
- * @brief   Starts a I2S data exchange in continuous mode.
- *
- * @param[in] i2sp      pointer to the @p I2SDriver object
- *
- * @iclass
- */
-#define i2sStartExchangeContinuousI(i2sp) {                                 \
-  i2s_lld_start_exchange_continuous(i2sp);                                  \
-  (i2sp)->state = I2S_ACTIVE;                                               \
-}
-
-/**
  * @brief   Stops the ongoing data exchange.
  * @details The ongoing data exchange, if any, is stopped, if the driver
  *          was not active the function does nothing.
@@ -122,6 +106,49 @@ typedef struct I2SDriver I2SDriver;
   (i2sp)->state = I2S_READY;                                                \
 }
 
+/**
+ * @brief   Common ISR code, half buffer event.
+ * @details This code handles the portable part of the ISR code:
+ *          - Callback invocation.
+ *          .
+ * @note    This macro is meant to be used in the low level drivers
+ *          implementation only.
+ *
+ * @param[in] i2sp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2s_isr_half_code(i2sp) {                                          \
+  if ((i2sp)->config->end_cb != NULL) {                                     \
+    (i2sp)->config->end_cb(i2sp, 0, (i2sp)->config->size / 2);              \
+  }                                                                         \
+}
+
+/**
+ * @brief   Common ISR code.
+ * @details This code handles the portable part of the ISR code:
+ *          - Callback invocation.
+ *          - Driver state transitions.
+ *          .
+ * @note    This macro is meant to be used in the low level drivers
+ *          implementation only.
+ *
+ * @param[in] i2sp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define _i2s_isr_full_code(i2sp) {                                               \
+  if ((i2sp)->config->end_cb) {                                             \
+    (i2sp)->state = I2S_COMPLETE;                                           \
+    (i2sp)->config->end_cb(i2sp,                                            \
+                           (i2sp)->config->size / 2,                        \
+                           (i2sp)->config->size / 2);                       \
+    if ((i2sp)->state == I2S_COMPLETE)                                      \
+      (i2sp)->state = I2S_READY;                                            \
+  }                                                                         \
+  else                                                                      \
+    (i2sp)->state = I2S_READY;                                              \
+}
 /** @} */
 
 /*===========================================================================*/
diff --git a/os/hal/include/io_block.h b/os/hal/include/io_block.h
deleted file mode 100644
index 7a2970f9f..000000000
--- a/os/hal/include/io_block.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    io_block.h
- * @brief   I/O block devices access.
- * @details This header defines an abstract interface useful to access generic
- *          I/O block devices in a standardized way.
- *
- * @addtogroup IO_BLOCK
- * @details This module defines an abstract interface for accessing generic
- *          block devices.<br>
- *          Note that no code is present, just abstract interfaces-like
- *          structures, you should look at the system as to a set of
- *          abstract C++ classes (even if written in C). This system
- *          has then advantage to make the access to block devices
- *          independent from the implementation logic.
- * @{
- */
-
-#ifndef _IO_BLOCK_H_
-#define _IO_BLOCK_H_
-
-/**
- * @brief   Driver state machine possible states.
- */
-typedef enum {
-  BLK_UNINIT = 0,                   /**< Not initialized.                   */
-  BLK_STOP = 1,                     /**< Stopped.                           */
-  BLK_ACTIVE = 2,                   /**< Interface active.                  */
-  BLK_CONNECTING = 3,               /**< Connection in progress.            */
-  BLK_DISCONNECTING = 4,            /**< Disconnection in progress.         */
-  BLK_READY = 5,                    /**< Device ready.                      */
-  BLK_READING = 6,                  /**< Read operation in progress.        */
-  BLK_WRITING = 7,                  /**< Write operation in progress.       */
-  BLK_SYNCING = 8                   /**< Sync. operation in progress.       */
-} blkstate_t;
-
-/**
- * @brief   Block device info.
- */
-typedef struct {
-  uint32_t      blk_size;           /**< @brief Block size in bytes.        */
-  uint32_t      blk_num;            /**< @brief Total number of blocks.     */
-} BlockDeviceInfo;
-
-/**
- * @brief   @p BaseBlockDevice specific methods.
- */
-#define _base_block_device_methods                                          \
-  /* Removable media detection.*/                                           \
-  bool_t (*is_inserted)(void *instance);                                    \
-  /* Removable write protection detection.*/                                \
-  bool_t (*is_protected)(void *instance);                                   \
-  /* Connection to the block device.*/                                      \
-  bool_t (*connect)(void *instance);                                        \
-  /* Disconnection from the block device.*/                                 \
-  bool_t (*disconnect)(void *instance);                                     \
-  /* Reads one or more blocks.*/                                            \
-  bool_t (*read)(void *instance, uint32_t startblk,                         \
-                 uint8_t *buffer, uint32_t n);                              \
-  /* Writes one or more blocks.*/                                           \
-  bool_t (*write)(void *instance, uint32_t startblk,                        \
-                  const uint8_t *buffer, uint32_t n);                       \
-  /* Write operations synchronization.*/                                    \
-  bool_t (*sync)(void *instance);                                           \
-  /* Obtains info about the media.*/                                        \
-  bool_t (*get_info)(void *instance, BlockDeviceInfo *bdip);
-
-/**
- * @brief   @p BaseBlockDevice specific data.
- */
-#define _base_block_device_data                                             \
-  /* Driver state.*/                                                        \
-  blkstate_t            state;
-
-/**
- * @brief   @p BaseBlockDevice virtual methods table.
- */
-struct BaseBlockDeviceVMT {
-  _base_block_device_methods
-};
-
-/**
- * @brief   Base block device class.
- * @details This class represents a generic, block-accessible, device.
- */
-typedef struct {
-  /** @brief Virtual Methods Table.*/
-  const struct BaseBlockDeviceVMT *vmt;
-  _base_block_device_data
-} BaseBlockDevice;
-
-/**
- * @name    Macro Functions (BaseBlockDevice)
- * @{
- */
-/**
- * @brief   Returns the driver state.
- * @note    Can be called in ISR context.
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- *
- * @return              The driver state.
- *
- * @special
- */
-#define blkGetDriverState(ip) ((ip)->state)
-
-/**
- * @brief   Determines if the device is transferring data.
- * @note    Can be called in ISR context.
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- *
- * @return              The driver state.
- * @retval FALSE        the device is not transferring data.
- * @retval TRUE         the device not transferring data.
- *
- * @special
- */
-#define blkIsTransferring(ip) ((((ip)->state) == BLK_CONNECTING) ||         \
-                               (((ip)->state) == BLK_DISCONNECTING) ||      \
-                               (((ip)->state) == BLK_READING) ||            \
-                               (((ip)->state) == BLK_WRITING))
-
-/**
- * @brief   Returns the media insertion status.
- * @note    On some implementations this function can only be called if the
- *          device is not transferring data.
- *          The function @p blkIsTransferring() should be used before calling
- *          this function.
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- *
- * @return              The media state.
- * @retval FALSE        media not inserted.
- * @retval TRUE         media inserted.
- *
- * @api
- */
-#define blkIsInserted(ip) ((ip)->vmt->is_inserted(ip))
-
-/**
- * @brief   Returns the media write protection status.
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- *
- * @return              The media state.
- * @retval FALSE        writable media.
- * @retval TRUE         non writable media.
- *
- * @api
- */
-#define blkIsWriteProtected(ip) ((ip)->vmt->is_protected(ip))
-
-/**
- * @brief   Performs the initialization procedure on the block device.
- * @details This function should be performed before I/O operations can be
- *          attempted on the block device and after insertion has been
- *          confirmed using @p blkIsInserted().
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @api
- */
-#define blkConnect(ip) ((ip)->vmt->connect(ip))
-
-/**
- * @brief   Terminates operations on the block device.
- * @details This operation safely terminates operations on the block device.
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @api
- */
-#define blkDisconnect(ip) ((ip)->vmt->disconnect(ip))
-
-/**
- * @brief   Reads one or more blocks.
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- * @param[in] startblk  first block to read
- * @param[out] buf      pointer to the read buffer
- * @param[in] n         number of blocks to read
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @api
- */
-#define blkRead(ip, startblk, buf, n)                                       \
-  ((ip)->vmt->read(ip, startblk, buf, n))
-
-/**
- * @brief   Writes one or more blocks.
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- * @param[in] startblk  first block to write
- * @param[out] buf      pointer to the write buffer
- * @param[in] n         number of blocks to write
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @api
- */
-#define blkWrite(ip, startblk, buf, n)                                      \
-  ((ip)->vmt->write(ip, startblk, buf, n))
-
-/**
- * @brief   Ensures write synchronization.
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @api
- */
-#define blkSync(ip) ((ip)->vmt->sync(ip))
-
-/**
- * @brief   Returns a media information structure.
- *
- * @param[in] ip        pointer to a @p BaseBlockDevice or derived class
- * @param[out] bdip     pointer to a @p BlockDeviceInfo structure
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @api
- */
-#define blkGetInfo(ip, bdip) ((ip)->vmt->get_info(ip, bdip))
-
-/** @} */
-
-#endif /* _IO_BLOCK_H_ */
-
-/** @} */
diff --git a/os/hal/include/io_channel.h b/os/hal/include/io_channel.h
deleted file mode 100644
index 66c81b683..000000000
--- a/os/hal/include/io_channel.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    io_channel.h
- * @brief   I/O channels access.
- * @details This header defines an abstract interface useful to access generic
- *          I/O serial devices in a standardized way.
- *
- * @addtogroup IO_CHANNEL
- * @details This module defines an abstract interface for I/O channels by
- *          extending the @p BaseSequentialStream interface.<br>
- *          Note that no code is present, I/O channels are just abstract
- *          interface like structures, you should look at the systems as
- *          to a set of abstract C++ classes (even if written in C).
- *          Specific device drivers can use/extend the interface and
- *          implement them.<br>
- *          This system has the advantage to make the access to channels
- *          independent from the implementation logic.
- * @{
- */
-
-#ifndef _IO_CHANNEL_H_
-#define _IO_CHANNEL_H_
-
-/**
- * @brief   @p BaseChannel specific methods.
- */
-#define _base_channel_methods                                               \
-  _base_sequential_stream_methods                                           \
-  /* Channel put method with timeout specification.*/                       \
-  msg_t (*putt)(void *instance, uint8_t b, systime_t time);                 \
-  /* Channel get method with timeout specification.*/                       \
-  msg_t (*gett)(void *instance, systime_t time);                            \
-  /* Channel write method with timeout specification.*/                     \
-  size_t (*writet)(void *instance, const uint8_t *bp,                       \
-                   size_t n, systime_t time);                               \
-  /* Channel read method with timeout specification.*/                      \
-  size_t (*readt)(void *instance, uint8_t *bp, size_t n, systime_t time);
-
-/**
- * @brief   @p BaseChannel specific data.
- * @note    It is empty because @p BaseChannel is only an interface without
- *          implementation.
- */
-#define _base_channel_data                                                  \
-  _base_sequential_stream_data
-
-/**
- * @extends BaseSequentialStreamVMT
- *
- * @brief   @p BaseChannel virtual methods table.
- */
-struct BaseChannelVMT {
-  _base_channel_methods
-};
-
-/**
- * @extends BaseSequentialStream
- *
- * @brief   Base channel class.
- * @details This class represents a generic, byte-wide, I/O channel. This class
- *          introduces generic I/O primitives with timeout specification.
- */
-typedef struct {
-  /** @brief Virtual Methods Table.*/
-  const struct BaseChannelVMT *vmt;
-  _base_channel_data
-} BaseChannel;
-
-/**
- * @name    Macro Functions (BaseChannel)
- * @{
- */
-/**
- * @brief   Channel blocking byte write with timeout.
- * @details This function writes a byte value to a channel. If the channel
- *          is not ready to accept data then the calling thread is suspended.
- *
- * @param[in] ip        pointer to a @p BaseChannel or derived class
- * @param[in] b         the byte value to be written to the channel
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval Q_OK         if the operation succeeded.
- * @retval Q_TIMEOUT    if the specified time expired.
- * @retval Q_RESET      if the channel associated queue (if any) was reset.
- *
- * @api
- */
-#define chnPutTimeout(ip, b, time) ((ip)->vmt->putt(ip, b, time))
-
-/**
- * @brief   Channel blocking byte read with timeout.
- * @details This function reads a byte value from a channel. If the data
- *          is not available then the calling thread is suspended.
- *
- * @param[in] ip        pointer to a @p BaseChannel or derived class
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              A byte value from the queue.
- * @retval Q_TIMEOUT    if the specified time expired.
- * @retval Q_RESET      if the channel associated queue (if any) has been
- *                      reset.
- *
- * @api
- */
-#define chnGetTimeout(ip, time) ((ip)->vmt->gett(ip, time))
-
-/**
- * @brief   Channel blocking write.
- * @details The function writes data from a buffer to a channel. If the channel
- *          is not ready to accept data then the calling thread is suspended.
- *
- * @param[in] ip        pointer to a @p BaseChannel or derived class
- * @param[out] bp       pointer to the data buffer
- * @param[in] n         the maximum amount of data to be transferred
- *
- * @return              The number of bytes transferred.
- *
- * @api
- */
-#define chnWrite(ip, bp, n) chSequentialStreamWrite(ip, bp, n)
-
-/**
- * @brief   Channel blocking write with timeout.
- * @details The function writes data from a buffer to a channel. If the channel
- *          is not ready to accept data then the calling thread is suspended.
- *
- * @param[in] ip        pointer to a @p BaseChannel or derived class
- * @param[out] bp       pointer to the data buffer
- * @param[in] n         the maximum amount of data to be transferred
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The number of bytes transferred.
- *
- * @api
- */
-#define chnWriteTimeout(ip, bp, n, time) ((ip)->vmt->writet(ip, bp, n, time))
-
-/**
- * @brief   Channel blocking read.
- * @details The function reads data from a channel into a buffer. If the data
- *          is not available then the calling thread is suspended.
- *
- * @param[in] ip        pointer to a @p BaseChannel or derived class
- * @param[in] bp        pointer to the data buffer
- * @param[in] n         the maximum amount of data to be transferred
- *
- * @return              The number of bytes transferred.
- *
- * @api
- */
-#define chnRead(ip, bp, n) chSequentialStreamRead(ip, bp, n)
-
-/**
- * @brief   Channel blocking read with timeout.
- * @details The function reads data from a channel into a buffer. If the data
- *          is not available then the calling thread is suspended.
- *
- * @param[in] ip        pointer to a @p BaseChannel or derived class
- * @param[in] bp        pointer to the data buffer
- * @param[in] n         the maximum amount of data to be transferred
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The number of bytes transferred.
- *
- * @api
- */
-#define chnReadTimeout(ip, bp, n, time) ((ip)->vmt->readt(ip, bp, n, time))
-/** @} */
-
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
-/**
- * @name    I/O status flags added to the event listener
- * @{
- */
-/** @brief No pending conditions.*/
-#define CHN_NO_ERROR            0
-/** @brief Connection happened.*/
-#define CHN_CONNECTED           1
-/** @brief Disconnection happened.*/
-#define CHN_DISCONNECTED        2
-/** @brief Data available in the input queue.*/
-#define CHN_INPUT_AVAILABLE     4
-/** @brief Output queue empty.*/
-#define CHN_OUTPUT_EMPTY        8
-/** @brief Transmission end.*/
-#define CHN_TRANSMISSION_END    16
-/** @} */
-
-/**
- * @brief   @p BaseAsynchronousChannel specific methods.
- */
-#define _base_asynchronous_channel_methods                                  \
-  _base_channel_methods                                                     \
-
-/**
- * @brief   @p BaseAsynchronousChannel specific data.
- */
-#define _base_asynchronous_channel_data                                     \
-  _base_channel_data                                                        \
-  /* I/O condition event source.*/                                          \
-  EventSource           event;
-
-/**
- * @extends BaseChannelVMT
- *
- * @brief   @p BaseAsynchronousChannel virtual methods table.
- */
-struct BaseAsynchronousChannelVMT {
-  _base_asynchronous_channel_methods
-};
-
-/**
- * @extends BaseChannel
- *
- * @brief   Base asynchronous channel class.
- * @details This class extends @p BaseChannel by adding event sources fields
- *          for asynchronous I/O for use in an event-driven environment.
- */
-typedef struct {
-  /** @brief Virtual Methods Table.*/
-  const struct BaseAsynchronousChannelVMT *vmt;
-  _base_asynchronous_channel_data
-} BaseAsynchronousChannel;
-
-/**
- * @name    Macro Functions (BaseAsynchronousChannel)
- * @{
- */
-/**
- * @brief   Returns the I/O condition event source.
- * @details The event source is broadcasted when an I/O condition happens.
- *
- * @param[in] ip        pointer to a @p BaseAsynchronousChannel or derived
- *                      class
- * @return              A pointer to an @p EventSource object.
- *
- * @api
- */
-#define chnGetEventSource(ip) (&((ip)->event))
-
-/**
- * @brief   Adds status flags to the listeners's flags mask.
- * @details This function is usually called from the I/O ISRs in order to
- *          notify I/O conditions such as data events, errors, signal
- *          changes etc.
- *
- * @param[in] ip        pointer to a @p BaseAsynchronousChannel or derived
- *                      class
- * @param[in] flags     condition flags to be added to the listener flags mask
- *
- * @iclass
- */
-#define chnAddFlagsI(ip, flags) {                                           \
-  chEvtBroadcastFlagsI(&(ip)->event, flags);                                \
-}
-/** @} */
-
-#endif /* CH_USE_EVENTS */
-
-#endif /* _IO_CHANNEL_H_ */
-
-/** @} */
diff --git a/os/hal/include/mac.h b/os/hal/include/mac.h
deleted file mode 100644
index 868460ad5..000000000
--- a/os/hal/include/mac.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    mac.h
- * @brief   MAC Driver macros and structures.
- * @addtogroup MAC
- * @{
- */
-
-#ifndef _MAC_H_
-#define _MAC_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    MAC configuration options
- * @{
- */
-/**
- * @brief   Enables an event sources for incoming packets.
- */
-#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
-#define MAC_USE_ZERO_COPY           FALSE
-#endif
-
-/**
- * @brief   Enables an event sources for incoming packets.
- */
-#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
-#define MAC_USE_EVENTS              TRUE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !CH_USE_SEMAPHORES || !CH_USE_EVENTS
-#error "the MAC driver requires CH_USE_SEMAPHORES"
-#endif
-
-#if MAC_USE_EVENTS && !CH_USE_EVENTS
-#error "the MAC driver requires CH_USE_EVENTS"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Driver state machine possible states.
- */
-typedef enum {
-  MAC_UNINIT = 0,                   /**< Not initialized.                   */
-  MAC_STOP = 1,                     /**< Stopped.                           */
-  MAC_ACTIVE = 2                    /**< Active.                            */
-} macstate_t;
-
-/**
- * @brief   Type of a structure representing a MAC driver.
- */
-typedef struct MACDriver MACDriver;
-
-#include "mac_lld.h"
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Returns the received frames event source.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @return              The pointer to the @p EventSource structure.
- *
- * @api
- */
-#if MAC_USE_EVENTS || defined(__DOXYGEN__)
-#define macGetReceiveEventSource(macp)  (&(macp)->rdevent)
-#endif
-
-/**
- * @brief   Writes to a transmit descriptor's stream.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf       pointer to the buffer containing the data to be written
- * @param[in] size      number of bytes to be written
- * @return              The number of bytes written into the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if the maximum frame
- *                      size is reached.
- *
- * @api
- */
-#define macWriteTransmitDescriptor(tdp, buf, size)                          \
-    mac_lld_write_transmit_descriptor(tdp, buf, size)
-
-/**
- * @brief   Reads from a receive descriptor's stream.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[in] buf       pointer to the buffer that will receive the read data
- * @param[in] size      number of bytes to be read
- * @return              The number of bytes read from the descriptor's stream,
- *                      this value can be less than the amount specified in the
- *                      parameter @p size if there are no more bytes to read.
- *
- * @api
- */
-#define macReadReceiveDescriptor(rdp, buf, size)                            \
-    mac_lld_read_receive_descriptor(rdp, buf, size)
-
-#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
-/**
- * @brief   Returns a pointer to the next transmit buffer in the descriptor
- *          chain.
- * @note    The API guarantees that enough buffers can be requested to fill
- *          a whole frame.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] size      size of the requested buffer. Specify the frame size
- *                      on the first call then scale the value down subtracting
- *                      the amount of data already copied into the previous
- *                      buffers.
- * @param[out] sizep    pointer to variable receiving the real buffer size.
- *                      The returned value can be less than the amount
- *                      requested, this means that more buffers must be
- *                      requested in order to fill the frame data entirely.
- * @return              Pointer to the returned buffer.
- *
- * @api
- */
-#define macGetNextTransmitBuffer(tdp, size, sizep)                          \
-  mac_lld_get_next_transmit_buffer(tdp, size, sizep)
-
-/**
- * @brief   Returns a pointer to the next receive buffer in the descriptor
- *          chain.
- * @note    The API guarantees that the descriptor chain contains a whole
- *          frame.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[out] sizep    pointer to variable receiving the buffer size, it is
- *                      zero when the last buffer has already been returned.
- * @return              Pointer to the returned buffer.
- * @retval NULL         if the buffer chain has been entirely scanned.
- *
- * @api
- */
-#define macGetNextReceiveBuffer(rdp, sizep)                                 \
-  mac_lld_get_next_receive_buffer(rdp, sizep)
-#endif /* MAC_USE_ZERO_COPY */
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void macInit(void);
-  void macObjectInit(MACDriver *macp);
-  void macStart(MACDriver *macp, const MACConfig *config);
-  void macStop(MACDriver *macp);
-  void macSetAddress(MACDriver *macp, const uint8_t *p);
-  msg_t macWaitTransmitDescriptor(MACDriver *macp,
-                                  MACTransmitDescriptor *tdp,
-                                  systime_t time);
-  void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp);
-  msg_t macWaitReceiveDescriptor(MACDriver *macp,
-                                 MACReceiveDescriptor *rdp,
-                                 systime_t time);
-  void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp);
-  bool_t macPollLinkStatus(MACDriver *macp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _MAC_H_ */
-
-/** @} */
diff --git a/os/hal/include/mii.h b/os/hal/include/mii.h
deleted file mode 100644
index d4b65da54..000000000
--- a/os/hal/include/mii.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/*-*
- * @file    mii.h
- * @brief   MII Driver macros and structures.
- *
- * @addtogroup MII
- * @{
- */
-
-#ifndef _MII_H_
-#define _MII_H_
-
-/*
- * Generic MII registers. Note, not all registers are present on all PHY
- * devices and some extra registers may be present.
- */
-#define MII_BMCR                0x00    /**< Basic mode control register.   */
-#define MII_BMSR                0x01    /**< Basic mode status register.    */
-#define MII_PHYSID1             0x02    /**< PHYS ID 1.                     */
-#define MII_PHYSID2             0x03    /**< PHYS ID 2.                     */
-#define MII_ADVERTISE           0x04    /**< Advertisement control reg.     */
-#define MII_LPA                 0x05    /**< Link partner ability reg.      */
-#define MII_EXPANSION           0x06    /**< Expansion register.            */
-#define MII_ANNPTR              0x07    /**< 1000BASE-T control.            */
-#define MII_CTRL1000            0x09    /**< 1000BASE-T control.            */
-#define MII_STAT1000            0x0a    /**< 1000BASE-T status.             */
-#define MII_ESTATUS             0x0f    /**< Extended Status.               */
-#define MII_PHYSTS              0x10    /**< PHY Status register.           */
-#define MII_MICR                0x11    /**< MII Interrupt ctrl register.   */
-#define MII_DCOUNTER            0x12    /**< Disconnect counter.            */
-#define MII_FCSCOUNTER          0x13    /**< False carrier counter.         */
-#define MII_NWAYTEST            0x14    /**< N-way auto-neg test reg.       */
-#define MII_RERRCOUNTER         0x15    /**< Receive error counter.         */
-#define MII_SREVISION           0x16    /**< Silicon revision.              */
-#define MII_RESV1               0x17    /**< Reserved.                      */
-#define MII_LBRERROR            0x18    /**< Lpback, rx, bypass error.      */
-#define MII_PHYADDR             0x19    /**< PHY address.                   */
-#define MII_RESV2               0x1a    /**< Reserved.                      */
-#define MII_TPISTATUS           0x1b    /**< TPI status for 10Mbps.         */
-#define MII_NCONFIG             0x1c    /**< Network interface config.      */
-
-/*
- * Basic mode control register.
- */
-#define BMCR_RESV               0x007f  /**< Unused.                        */
-#define BMCR_CTST               0x0080  /**< Collision test.                */
-#define BMCR_FULLDPLX           0x0100  /**< Full duplex.                   */
-#define BMCR_ANRESTART          0x0200  /**< Auto negotiation restart.      */
-#define BMCR_ISOLATE            0x0400  /**< Disconnect DP83840 from MII.   */
-#define BMCR_PDOWN              0x0800  /**< Powerdown.                     */
-#define BMCR_ANENABLE           0x1000  /**< Enable auto negotiation.       */
-#define BMCR_SPEED100           0x2000  /**< Select 100Mbps.                */
-#define BMCR_LOOPBACK           0x4000  /**< TXD loopback bit.              */
-#define BMCR_RESET              0x8000  /**< Reset.                         */
-
-/*
- * Basic mode status register.
- */
-#define BMSR_ERCAP              0x0001  /**< Ext-reg capability.            */
-#define BMSR_JCD                0x0002  /**< Jabber detected.               */
-#define BMSR_LSTATUS            0x0004  /**< Link status.                   */
-#define BMSR_ANEGCAPABLE        0x0008  /**< Able to do auto-negotiation.   */
-#define BMSR_RFAULT             0x0010  /**< Remote fault detected.         */
-#define BMSR_ANEGCOMPLETE       0x0020  /**< Auto-negotiation complete.     */
-#define BMSR_MFPRESUPPCAP       0x0040  /**< Able to suppress preamble.     */
-#define BMSR_RESV               0x0780  /**< Unused.                        */
-#define BMSR_10HALF             0x0800  /**< Can do 10mbps, half-duplex.    */
-#define BMSR_10FULL             0x1000  /**< Can do 10mbps, full-duplex.    */
-#define BMSR_100HALF            0x2000  /**< Can do 100mbps, half-duplex.   */
-#define BMSR_100FULL            0x4000  /**< Can do 100mbps, full-duplex.   */
-#define BMSR_100BASE4           0x8000  /**< Can do 100mbps, 4k packets.    */
-
-/*
- * Advertisement control register.
- */
-#define ADVERTISE_SLCT          0x001f  /**< Selector bits.                 */
-#define ADVERTISE_CSMA          0x0001  /**< Only selector supported.       */
-#define ADVERTISE_10HALF        0x0020  /**< Try for 10mbps half-duplex.    */
-#define ADVERTISE_10FULL        0x0040  /**< Try for 10mbps full-duplex.    */
-#define ADVERTISE_100HALF       0x0080  /**< Try for 100mbps half-duplex.   */
-#define ADVERTISE_100FULL       0x0100  /**< Try for 100mbps full-duplex.   */
-#define ADVERTISE_100BASE4      0x0200  /**< Try for 100mbps 4k packets.    */
-#define ADVERTISE_PAUSE_CAP     0x0400  /**< Try for pause.                 */
-#define ADVERTISE_PAUSE_ASYM    0x0800  /**< Try for asymetric pause.       */
-#define ADVERTISE_RESV          0x1000  /**< Unused.                        */
-#define ADVERTISE_RFAULT        0x2000  /**< Say we can detect faults.      */
-#define ADVERTISE_LPACK         0x4000  /**< Ack link partners response.    */
-#define ADVERTISE_NPAGE         0x8000  /**< Next page bit.                 */
-
-#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-                        ADVERTISE_CSMA)
-#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
-                       ADVERTISE_100HALF | ADVERTISE_100FULL)
-
-/*
- * Link partner ability register.
- */
-#define LPA_SLCT                0x001f  /**< Same as advertise selector.    */
-#define LPA_10HALF              0x0020  /**< Can do 10mbps half-duplex.     */
-#define LPA_10FULL              0x0040  /**< Can do 10mbps full-duplex.     */
-#define LPA_100HALF             0x0080  /**< Can do 100mbps half-duplex.    */
-#define LPA_100FULL             0x0100  /**< Can do 100mbps full-duplex.    */
-#define LPA_100BASE4            0x0200  /**< Can do 100mbps 4k packets.     */
-#define LPA_PAUSE_CAP           0x0400  /**< Can pause.                     */
-#define LPA_PAUSE_ASYM          0x0800  /**< Can pause asymetrically.       */
-#define LPA_RESV                0x1000  /**< Unused.                        */
-#define LPA_RFAULT              0x2000  /**< Link partner faulted.          */
-#define LPA_LPACK               0x4000  /**< Link partner acked us.         */
-#define LPA_NPAGE               0x8000  /**< Next page bit.                 */
-
-#define LPA_DUPLEX              (LPA_10FULL | LPA_100FULL)
-#define LPA_100                 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
-
-/*
- * Expansion register for auto-negotiation.
- */
-#define EXPANSION_NWAY          0x0001  /**< Can do N-way auto-nego.        */
-#define EXPANSION_LCWP          0x0002  /**< Got new RX page code word.     */
-#define EXPANSION_ENABLENPAGE   0x0004  /**< This enables npage words.      */
-#define EXPANSION_NPCAPABLE     0x0008  /**< Link partner supports npage.   */
-#define EXPANSION_MFAULTS       0x0010  /**< Multiple faults detected.      */
-#define EXPANSION_RESV          0xffe0  /**< Unused.                        */
-
-/*
- * N-way test register.
- */
-#define NWAYTEST_RESV1          0x00ff  /**< Unused.                        */
-#define NWAYTEST_LOOPBACK       0x0100  /**< Enable loopback for N-way.     */
-#define NWAYTEST_RESV2          0xfe00  /**< Unused.                        */
-
-/*
- * PHY identifiers.
- */
-#define MII_DM9161_ID     0x0181b8a0
-#define MII_AM79C875_ID   0x00225540
-#define MII_KS8721_ID     0x00221610
-#define MII_STE101P_ID    0x00061C50
-#define MII_DP83848I_ID   0x20005C90
-#define MII_LAN8710A_ID   0x0007C0F1
-
-#endif /* _MII_H_ */
-
-/** @} */
diff --git a/os/hal/include/mmc_spi.h b/os/hal/include/mmc_spi.h
index 2610d0024..9f51f7e2b 100644
--- a/os/hal/include/mmc_spi.h
+++ b/os/hal/include/mmc_spi.h
@@ -124,7 +124,7 @@ typedef struct {
   /***
    * @brief Addresses use blocks instead of bytes.
    */
-  bool_t                block_addresses;
+  bool                block_addresses;
 } MMCDriver;
 
 /*===========================================================================*/
@@ -175,19 +175,19 @@ extern "C" {
   void mmcObjectInit(MMCDriver *mmcp);
   void mmcStart(MMCDriver *mmcp, const MMCConfig *config);
   void mmcStop(MMCDriver *mmcp);
-  bool_t mmcConnect(MMCDriver *mmcp);
-  bool_t mmcDisconnect(MMCDriver *mmcp);
-  bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk);
-  bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer);
-  bool_t mmcStopSequentialRead(MMCDriver *mmcp);
-  bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk);
-  bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer);
-  bool_t mmcStopSequentialWrite(MMCDriver *mmcp);
-  bool_t mmcSync(MMCDriver *mmcp);
-  bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip);
-  bool_t mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk);
-  bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp);
-  bool_t mmc_lld_is_write_protected(MMCDriver *mmcp);
+  bool mmcConnect(MMCDriver *mmcp);
+  bool mmcDisconnect(MMCDriver *mmcp);
+  bool mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk);
+  bool mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer);
+  bool mmcStopSequentialRead(MMCDriver *mmcp);
+  bool mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk);
+  bool mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer);
+  bool mmcStopSequentialWrite(MMCDriver *mmcp);
+  bool mmcSync(MMCDriver *mmcp);
+  bool mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip);
+  bool mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk);
+  bool mmc_lld_is_card_inserted(MMCDriver *mmcp);
+  bool mmc_lld_is_write_protected(MMCDriver *mmcp);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/include/mmcsd.h b/os/hal/include/mmcsd.h
deleted file mode 100644
index 5ff3082c7..000000000
--- a/os/hal/include/mmcsd.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    mmcsd.h
- * @brief   MMC/SD cards common header.
- * @details This header defines an abstract interface useful to access MMC/SD
- *          I/O block devices in a standardized way.
- *
- * @addtogroup MMCSD
- * @{
- */
-
-#ifndef _MMCSD_H_
-#define _MMCSD_H_
-
-#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Fixed block size for MMC/SD block devices.
- */
-#define MMCSD_BLOCK_SIZE                512
-
-/**
- * @brief   Mask of error bits in R1 responses.
- */
-#define MMCSD_R1_ERROR_MASK             0xFDFFE008
-
-/**
- * @brief   Fixed pattern for CMD8.
- */
-#define MMCSD_CMD8_PATTERN              0x000001AA
-
-/**
- * @name    SD/MMC status conditions
- * @{
- */
-#define MMCSD_STS_IDLE                  0
-#define MMCSD_STS_READY                 1
-#define MMCSD_STS_IDENT                 2
-#define MMCSD_STS_STBY                  3
-#define MMCSD_STS_TRAN                  4
-#define MMCSD_STS_DATA                  5
-#define MMCSD_STS_RCV                   6
-#define MMCSD_STS_PRG                   7
-#define MMCSD_STS_DIS                   8
-/** @} */
-
-/**
- * @name    SD/MMC commands
- * @{
- */
-#define MMCSD_CMD_GO_IDLE_STATE         0
-#define MMCSD_CMD_INIT                  1
-#define MMCSD_CMD_ALL_SEND_CID          2
-#define MMCSD_CMD_SEND_RELATIVE_ADDR    3
-#define MMCSD_CMD_SET_BUS_WIDTH         6
-#define MMCSD_CMD_SEL_DESEL_CARD        7
-#define MMCSD_CMD_SEND_IF_COND          8
-#define MMCSD_CMD_SEND_CSD              9
-#define MMCSD_CMD_SEND_CID              10
-#define MMCSD_CMD_STOP_TRANSMISSION     12
-#define MMCSD_CMD_SEND_STATUS           13
-#define MMCSD_CMD_SET_BLOCKLEN          16
-#define MMCSD_CMD_READ_SINGLE_BLOCK     17
-#define MMCSD_CMD_READ_MULTIPLE_BLOCK   18
-#define MMCSD_CMD_SET_BLOCK_COUNT       23
-#define MMCSD_CMD_WRITE_BLOCK           24
-#define MMCSD_CMD_WRITE_MULTIPLE_BLOCK  25
-#define MMCSD_CMD_ERASE_RW_BLK_START    32
-#define MMCSD_CMD_ERASE_RW_BLK_END      33
-#define MMCSD_CMD_ERASE                 38
-#define MMCSD_CMD_APP_OP_COND           41
-#define MMCSD_CMD_LOCK_UNLOCK           42
-#define MMCSD_CMD_APP_CMD               55
-#define MMCSD_CMD_READ_OCR              58
-/** @} */
-
-/**
- * @name   CSD record offsets
- */
-/**
- * @brief  Slice position of values in CSD register.
- */
-/* CSD version 2.0 */
-#define MMCSD_CSD_20_CRC_SLICE                  7,1
-#define MMCSD_CSD_20_FILE_FORMAT_SLICE          11,10
-#define MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE    12,12
-#define MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE   13,13
-#define MMCSD_CSD_20_COPY_SLICE                 14,14
-#define MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE      15,15
-#define MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE     21,21
-#define MMCSD_CSD_20_WRITE_BL_LEN_SLICE         25,12
-#define MMCSD_CSD_20_R2W_FACTOR_SLICE           28,26
-#define MMCSD_CSD_20_WP_GRP_ENABLE_SLICE        31,31
-#define MMCSD_CSD_20_WP_GRP_SIZE_SLICE          38,32
-#define MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE    45,39
-#define MMCSD_CSD_20_ERASE_BLK_EN_SLICE         46,46
-#define MMCSD_CSD_20_C_SIZE_SLICE               69,48
-#define MMCSD_CSD_20_DSR_IMP_SLICE              76,76
-#define MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE    77,77
-#define MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE   78,78
-#define MMCSD_CSD_20_READ_BL_PARTIAL_SLICE      79,79
-#define MMCSD_CSD_20_READ_BL_LEN_SLICE          83,80
-#define MMCSD_CSD_20_CCC_SLICE                  95,84
-#define MMCSD_CSD_20_TRANS_SPEED_SLICE          103,96
-#define MMCSD_CSD_20_NSAC_SLICE                 111,104
-#define MMCSD_CSD_20_TAAC_SLICE                 119,112
-#define MMCSD_CSD_20_STRUCTURE_SLICE            127,126
-
-/* CSD version 1.0 */
-#define MMCSD_CSD_10_CRC_SLICE                  MMCSD_CSD_20_CRC_SLICE
-#define MMCSD_CSD_10_FILE_FORMAT_SLICE          MMCSD_CSD_20_FILE_FORMAT_SLICE
-#define MMCSD_CSD_10_TMP_WRITE_PROTECT_SLICE    MMCSD_CSD_20_TMP_WRITE_PROTECT_SLICE
-#define MMCSD_CSD_10_PERM_WRITE_PROTECT_SLICE   MMCSD_CSD_20_PERM_WRITE_PROTECT_SLICE
-#define MMCSD_CSD_10_COPY_SLICE                 MMCSD_CSD_20_COPY_SLICE
-#define MMCSD_CSD_10_FILE_FORMAT_GRP_SLICE      MMCSD_CSD_20_FILE_FORMAT_GRP_SLICE
-#define MMCSD_CSD_10_WRITE_BL_PARTIAL_SLICE     MMCSD_CSD_20_WRITE_BL_PARTIAL_SLICE
-#define MMCSD_CSD_10_WRITE_BL_LEN_SLICE         MMCSD_CSD_20_WRITE_BL_LEN_SLICE
-#define MMCSD_CSD_10_R2W_FACTOR_SLICE           MMCSD_CSD_20_R2W_FACTOR_SLICE
-#define MMCSD_CSD_10_WP_GRP_ENABLE_SLICE        MMCSD_CSD_20_WP_GRP_ENABLE_SLICE
-#define MMCSD_CSD_10_WP_GRP_SIZE_SLICE          MMCSD_CSD_20_WP_GRP_SIZE_SLICE
-#define MMCSD_CSD_10_ERASE_SECTOR_SIZE_SLICE    MMCSD_CSD_20_ERASE_SECTOR_SIZE_SLICE
-#define MMCSD_CSD_10_ERASE_BLK_EN_SLICE         MMCSD_CSD_20_ERASE_BLK_EN_SLICE
-#define MMCSD_CSD_10_C_SIZE_MULT_SLICE          49,47
-#define MMCSD_CSD_10_VDD_W_CURR_MAX_SLICE       52,50
-#define MMCSD_CSD_10_VDD_W_CURR_MIN_SLICE       55,53
-#define MMCSD_CSD_10_VDD_R_CURR_MAX_SLICE       58,56
-#define MMCSD_CSD_10_VDD_R_CURR_MIX_SLICE       61,59
-#define MMCSD_CSD_10_C_SIZE_SLICE               73,62
-#define MMCSD_CSD_10_DSR_IMP_SLICE              MMCSD_CSD_20_DSR_IMP_SLICE
-#define MMCSD_CSD_10_READ_BLK_MISALIGN_SLICE    MMCSD_CSD_20_READ_BLK_MISALIGN_SLICE
-#define MMCSD_CSD_10_WRITE_BLK_MISALIGN_SLICE   MMCSD_CSD_20_WRITE_BLK_MISALIGN_SLICE
-#define MMCSD_CSD_10_READ_BL_PARTIAL_SLICE      MMCSD_CSD_20_READ_BL_PARTIAL_SLICE
-#define MMCSD_CSD_10_READ_BL_LEN_SLICE          83, 80
-#define MMCSD_CSD_10_CCC_SLICE                  MMCSD_CSD_20_CCC_SLICE
-#define MMCSD_CSD_10_TRANS_SPEED_SLICE          MMCSD_CSD_20_TRANS_SPEED_SLICE
-#define MMCSD_CSD_10_NSAC_SLICE                 MMCSD_CSD_20_NSAC_SLICE
-#define MMCSD_CSD_10_TAAC_SLICE                 MMCSD_CSD_20_TAAC_SLICE
-#define MMCSD_CSD_10_STRUCTURE_SLICE            MMCSD_CSD_20_STRUCTURE_SLICE
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   @p MMCSDBlockDevice specific methods.
- */
-#define _mmcsd_block_device_methods                                         \
-  _base_block_device_methods
-
-/**
- * @brief   @p MMCSDBlockDevice specific data.
- * @note    It is empty because @p MMCSDBlockDevice is only an interface
- *          without implementation.
- */
-#define _mmcsd_block_device_data                                            \
-  _base_block_device_data                                                   \
-  /* Card CID.*/                                                            \
-  uint32_t              cid[4];                                             \
-  /* Card CSD.*/                                                            \
-  uint32_t              csd[4];                                             \
-  /* Total number of blocks in card.*/                                      \
-  uint32_t              capacity;
-
-/**
- * @extends BaseBlockDeviceVMT
- *
- * @brief   @p MMCSDBlockDevice virtual methods table.
- */
-struct MMCSDBlockDeviceVMT {
-  _base_block_device_methods
-};
-
-/**
- * @extends BaseBlockDevice
- *
- * @brief   MCC/SD block device class.
- * @details This class represents a, block-accessible, MMC/SD device.
- */
-typedef struct {
-  /** @brief Virtual Methods Table.*/
-  const struct MMCSDBlockDeviceVMT *vmt;
-  _mmcsd_block_device_data
-} MMCSDBlockDevice;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    R1 response utilities
- * @{
- */
-/**
- * @brief   Evaluates to @p TRUE if the R1 response contains error flags.
- *
- * @param[in] r1        the r1 response
- */
-#define MMCSD_R1_ERROR(r1)              (((r1) & MMCSD_R1_ERROR_MASK) != 0)
-
-/**
- * @brief   Returns the status field of an R1 response.
- *
- * @param[in] r1        the r1 response
- */
-#define MMCSD_R1_STS(r1)                (((r1) >> 9) & 15)
-
-/**
- * @brief   Evaluates to @p TRUE if the R1 response indicates a locked card.
- *
- * @param[in] r1        the r1 response
- */
-#define MMCSD_R1_IS_CARD_LOCKED(r1)     (((r1) >> 21) & 1)
-/** @} */
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Returns the card capacity in blocks.
- *
- * @param[in] ip        pointer to a @p MMCSDBlockDevice or derived class
- *
- * @return              The card capacity.
- *
- * @api
- */
-#define mmcsdGetCardCapacity(ip)  ((ip)->capacity)
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  uint32_t mmcsdGetCapacity(uint32_t csd[4]);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MMC_SPI || HAL_USE_MMC_SDC*/
-
-#endif /* _MMCSD_H_ */
-
-/** @} */
diff --git a/os/hal/include/pwm.h b/os/hal/include/pwm.h
index cdd1f43ca..4ece68d70 100644
--- a/os/hal/include/pwm.h
+++ b/os/hal/include/pwm.h
@@ -169,13 +169,13 @@ typedef void (*pwmcallback_t)(PWMDriver *pwmp);
  *          guaranteed.
  *
  * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] value     new cycle time in ticks
+ * @param[in] period    new cycle time in ticks
  *
  * @iclass
  */
-#define pwmChangePeriodI(pwmp, value) {                                     \
-  (pwmp)->period = (value);                                                 \
-  pwm_lld_change_period(pwmp, value);                                       \
+#define pwmChangePeriodI(pwmp, period) {                                    \
+  (pwmp)->period = (period);                                                \
+  pwm_lld_change_period(pwmp, period);                                      \
 }
 
 /**
diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h
deleted file mode 100644
index b510df907..000000000
--- a/os/hal/include/rtc.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    rtc.h
- * @brief   RTC Driver macros and structures.
- *
- * @addtogroup RTC
- * @{
- */
-
-#ifndef _RTC_H_
-#define _RTC_H_
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Date/Time bit masks
- * @{
- */
-#define RTC_TIME_SECONDS_MASK   0x0000001F  /* @brief Seconds mask.         */
-#define RTC_TIME_MINUTES_MASK   0x000007E0  /* @brief Minutes mask.         */
-#define RTC_TIME_HOURS_MASK     0x0000F800  /* @brief Hours mask.           */
-#define RTC_DATE_DAYS_MASK      0x001F0000  /* @brief Days mask.            */
-#define RTC_DATE_MONTHS_MASK    0x01E00000  /* @brief Months mask.          */
-#define RTC_DATE_YEARS_MASK     0xFE000000  /* @brief Years mask.           */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an RTC driver.
- */
-typedef struct RTCDriver RTCDriver;
-
-/**
- * @brief   Type of a structure representing an RTC time stamp.
- */
-typedef struct RTCTime RTCTime;
-
-#include "rtc_lld.h"
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Set current time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] timespec  pointer to a @p RTCTime structure
- *
- * @iclass
- */
-#define rtcSetTimeI(rtcp, timespec) rtc_lld_set_time(rtcp, timespec)
-
-/**
- * @brief   Get current time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @iclass
- */
-#define rtcGetTimeI(rtcp, timespec) rtc_lld_get_time(rtcp, timespec)
-
-#if (RTC_ALARMS > 0) || defined(__DOXYGEN__)
-/**
- * @brief   Set alarm time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] alarm     alarm identifier
- * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL
- *
- * @iclass
- */
-#define rtcSetAlarmI(rtcp, alarm, alarmspec)                                \
-  rtc_lld_set_alarm(rtcp, alarm, alarmspec)
-
-/**
- * @brief   Get current alarm.
- * @note    If an alarm has not been set then the returned alarm specification
- *          is not meaningful.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] alarm     alarm identifier
- * @param[out] alarmspec pointer to a @p RTCAlarm structure
- *
- * @iclass
- */
-#define rtcGetAlarmI(rtcp, alarm, alarmspec)                                \
-  rtc_lld_get_alarm(rtcp, alarm, alarmspec)
-#endif /* RTC_ALARMS > 0 */
-
-#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__)
-/**
- * @brief   Enables or disables RTC callbacks.
- * @details This function enables or disables the callback, use a @p NULL
- *          pointer in order to disable it.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] callback  callback function pointer or @p NULL
- *
- * @iclass
- */
-#define rtcSetCallbackI(rtcp, callback) rtc_lld_set_callback(rtcp, callback)
-#endif /* RTC_SUPPORTS_CALLBACKS */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void rtcInit(void);
-  void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec);
-  void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec);
-#if RTC_ALARMS > 0
-  void rtcSetAlarm(RTCDriver *rtcp,
-                   rtcalarm_t alarm,
-                   const RTCAlarm *alarmspec);
-  void rtcGetAlarm(RTCDriver *rtcp, rtcalarm_t alarm, RTCAlarm *alarmspec);
-#endif
-  uint32_t rtcGetTimeFat(RTCDriver *rtcp);
-#if RTC_SUPPORTS_CALLBACKS
-  void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_RTC */
-#endif /* _RTC_H_ */
-
-/** @} */
diff --git a/os/hal/include/sdc.h b/os/hal/include/sdc.h
index 0975ed167..3948a6189 100644
--- a/os/hal/include/sdc.h
+++ b/os/hal/include/sdc.h
@@ -36,30 +36,30 @@
 /*===========================================================================*/
 
 /**
- * @name    SD cart types
+ * @name    SD card types
  * @{
  */
-#define SDC_MODE_CARDTYPE_MASK          0xF     /**< @brief Card type mask. */
-#define SDC_MODE_CARDTYPE_SDV11         0       /**< @brief Card is SD V1.1.*/
-#define SDC_MODE_CARDTYPE_SDV20         1       /**< @brief Card is SD V2.0.*/
-#define SDC_MODE_CARDTYPE_MMC           2       /**< @brief Card is MMC.    */
-#define SDC_MODE_HIGH_CAPACITY          0x10    /**< @brief High cap.card.  */
+#define SDC_MODE_CARDTYPE_MASK              0xF /**< @brief Card type mask. */
+#define SDC_MODE_CARDTYPE_SDV11             0
+#define SDC_MODE_CARDTYPE_SDV20             1
+#define SDC_MODE_CARDTYPE_MMC               2
+#define SDC_MODE_HIGH_CAPACITY              0x10
 /** @} */
 
 /**
  * @name    SDC bus error conditions
  * @{
  */
-#define SDC_NO_ERROR          0           /**< @brief No error.             */
-#define SDC_CMD_CRC_ERROR     1           /**< @brief Command CRC error.    */
-#define SDC_DATA_CRC_ERROR    2           /**< @brief Data CRC error.       */
-#define SDC_DATA_TIMEOUT      4           /**< @brief HW write timeout.     */
-#define SDC_COMMAND_TIMEOUT   8           /**< @brief HW read timeout.      */
-#define SDC_TX_UNDERRUN       16          /**< @brief TX buffer underrun.   */
-#define SDC_RX_OVERRUN        32          /**< @brief RX buffer overrun.    */
-#define SDC_STARTBIT_ERROR    64          /**< @brief Start bit missing.    */
-#define SDC_OVERFLOW_ERROR    128         /**< @brief Card overflow error.  */
-#define SDC_UNHANDLED_ERROR   0xFFFFFFFF
+#define SDC_NO_ERROR                        0
+#define SDC_CMD_CRC_ERROR                   1
+#define SDC_DATA_CRC_ERROR                  2
+#define SDC_DATA_TIMEOUT                    4
+#define SDC_COMMAND_TIMEOUT                 8
+#define SDC_TX_UNDERRUN                     16
+#define SDC_RX_OVERRUN                      32
+#define SDC_STARTBIT_ERROR                  64
+#define SDC_OVERFLOW_ERROR                  128
+#define SDC_UNHANDLED_ERROR                 0xFFFFFFFF
 /** @} */
 
 /*===========================================================================*/
@@ -75,7 +75,7 @@
  * @note    Attempts are performed at 10mS intervals.
  */
 #if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
-#define SDC_INIT_RETRY                  100
+#define SDC_INIT_RETRY                      100
 #endif
 
 /**
@@ -84,7 +84,7 @@
  *          at @p FALSE.
  */
 #if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
-#define SDC_MMC_SUPPORT                 FALSE
+#define SDC_MMC_SUPPORT                     FALSE
 #endif
 
 /**
@@ -94,7 +94,7 @@
  *          lower priority, this may slow down the driver a bit however.
  */
 #if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
-#define SDC_NICE_WAITING                TRUE
+#define SDC_NICE_WAITING                    TRUE
 #endif
 /** @} */
 
@@ -160,17 +160,17 @@ extern "C" {
   void sdcObjectInit(SDCDriver *sdcp);
   void sdcStart(SDCDriver *sdcp, const SDCConfig *config);
   void sdcStop(SDCDriver *sdcp);
-  bool_t sdcConnect(SDCDriver *sdcp);
-  bool_t sdcDisconnect(SDCDriver *sdcp);
-  bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk,
-                 uint8_t *buffer, uint32_t n);
-  bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk,
-                  const uint8_t *buffer, uint32_t n);
+  bool sdcConnect(SDCDriver *sdcp);
+  bool sdcDisconnect(SDCDriver *sdcp);
+  bool sdcRead(SDCDriver *sdcp, uint32_t startblk,
+               uint8_t *buffer, uint32_t n);
+  bool sdcWrite(SDCDriver *sdcp, uint32_t startblk,
+                const uint8_t *buffer, uint32_t n);
   sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp);
-  bool_t sdcSync(SDCDriver *sdcp);
-  bool_t sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip);
-  bool_t sdcErase(SDCDriver *mmcp, uint32_t startblk, uint32_t endblk);
-  bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp);
+  bool sdcSync(SDCDriver *sdcp);
+  bool sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip);
+  bool sdcErase(SDCDriver *mmcp, uint32_t startblk, uint32_t endblk);
+  bool _sdc_wait_for_transfer_state(SDCDriver *sdcp);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/include/serial.h b/os/hal/include/serial.h
index 213a3c132..8ea2248bd 100644
--- a/os/hal/include/serial.h
+++ b/os/hal/include/serial.h
@@ -79,10 +79,6 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if !CH_USE_QUEUES && !CH_USE_EVENTS
-#error "Serial Driver requires CH_USE_QUEUES and CH_USE_EVENTS"
-#endif
-
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -149,7 +145,7 @@ struct SerialDriver {
  *
  * @api
  */
-#define sdPutWouldBlock(sdp) chOQIsFullI(&(sdp)->oqueue)
+#define sdPutWouldBlock(sdp) oqIsFullI(&(sdp)->oqueue)
 
 /**
  * @brief   Direct input check on a @p SerialDriver.
@@ -161,7 +157,7 @@ struct SerialDriver {
  *
  * @api
  */
-#define sdGetWouldBlock(sdp) chIQIsEmptyI(&(sdp)->iqueue)
+#define sdGetWouldBlock(sdp) iqIsEmptyI(&(sdp)->iqueue)
 
 /**
  * @brief   Direct write to a @p SerialDriver.
@@ -173,7 +169,7 @@ struct SerialDriver {
  *
  * @api
  */
-#define sdPut(sdp, b) chOQPut(&(sdp)->oqueue, b)
+#define sdPut(sdp, b) oqPut(&(sdp)->oqueue, b)
 
 /**
  * @brief   Direct write to a @p SerialDriver with timeout specification.
@@ -185,7 +181,7 @@ struct SerialDriver {
  *
  * @api
  */
-#define sdPutTimeout(sdp, b, t) chOQPutTimeout(&(sdp)->oqueue, b, t)
+#define sdPutTimeout(sdp, b, t) oqPutTimeout(&(sdp)->oqueue, b, t)
 
 /**
  * @brief   Direct read from a @p SerialDriver.
@@ -197,7 +193,7 @@ struct SerialDriver {
  *
  * @api
  */
-#define sdGet(sdp) chIQGet(&(sdp)->iqueue)
+#define sdGet(sdp) iqGet(&(sdp)->iqueue)
 
 /**
  * @brief   Direct read from a @p SerialDriver with timeout specification.
@@ -209,7 +205,7 @@ struct SerialDriver {
  *
  * @api
  */
-#define sdGetTimeout(sdp, t) chIQGetTimeout(&(sdp)->iqueue, t)
+#define sdGetTimeout(sdp, t) iqGetTimeout(&(sdp)->iqueue, t)
 
 /**
  * @brief   Direct blocking write to a @p SerialDriver.
@@ -222,7 +218,7 @@ struct SerialDriver {
  * @api
  */
 #define sdWrite(sdp, b, n)                                                  \
-  chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE)
+  oqWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE)
 
 /**
  * @brief   Direct blocking write to a @p SerialDriver with timeout
@@ -236,7 +232,7 @@ struct SerialDriver {
  * @api
  */
 #define sdWriteTimeout(sdp, b, n, t)                                        \
-  chOQWriteTimeout(&(sdp)->oqueue, b, n, t)
+  oqWriteTimeout(&(sdp)->oqueue, b, n, t)
 
 /**
  * @brief   Direct non-blocking write to a @p SerialDriver.
@@ -249,7 +245,7 @@ struct SerialDriver {
  * @api
  */
 #define sdAsynchronousWrite(sdp, b, n)                                      \
-  chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE)
+  oqWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE)
 
 /**
  * @brief   Direct blocking read from a @p SerialDriver.
@@ -262,7 +258,7 @@ struct SerialDriver {
  * @api
  */
 #define sdRead(sdp, b, n)                                                   \
-  chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE)
+  iqReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE)
 
 /**
  * @brief   Direct blocking read from a @p SerialDriver with timeout
@@ -276,7 +272,7 @@ struct SerialDriver {
  * @api
  */
 #define sdReadTimeout(sdp, b, n, t)                                         \
-  chIQReadTimeout(&(sdp)->iqueue, b, n, t)
+  iqReadTimeout(&(sdp)->iqueue, b, n, t)
 
 /**
  * @brief   Direct non-blocking read from a @p SerialDriver.
@@ -289,7 +285,7 @@ struct SerialDriver {
  * @api
  */
 #define sdAsynchronousRead(sdp, b, n)                                       \
-  chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE)
+  iqReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE)
 /** @} */
 
 /*===========================================================================*/
diff --git a/os/hal/include/serial_usb.h b/os/hal/include/serial_usb.h
index 28ab3a940..fb4ab25d5 100644
--- a/os/hal/include/serial_usb.h
+++ b/os/hal/include/serial_usb.h
@@ -99,9 +99,8 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if !HAL_USE_USB || !CH_USE_QUEUES || !CH_USE_EVENTS
-#error "Serial over USB Driver requires HAL_USE_USB, CH_USE_QUEUES, "
-       "CH_USE_EVENTS"
+#if !HAL_USE_USB
+#error "Serial over USB Driver requires HAL_USE_USB"
 #endif
 
 /*===========================================================================*/
@@ -164,9 +163,9 @@ typedef struct {
   /* Driver state.*/                                                        \
   sdustate_t                state;                                          \
   /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
+  input_queue_t             iqueue;                                         \
   /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
+  output_queue_t            oqueue;                                         \
   /* Input buffer.*/                                                        \
   uint8_t                   ib[SERIAL_USB_BUFFERS_SIZE];                    \
   /* Output buffer.*/                                                       \
@@ -219,7 +218,7 @@ extern "C" {
   void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config);
   void sduStop(SerialUSBDriver *sdup);
   void sduConfigureHookI(SerialUSBDriver *sdup);
-  bool_t sduRequestsHook(USBDriver *usbp);
+  bool sduRequestsHook(USBDriver *usbp);
   void sduDataTransmitted(USBDriver *usbp, usbep_t ep);
   void sduDataReceived(USBDriver *usbp, usbep_t ep);
   void sduInterruptTransmitted(USBDriver *usbp, usbep_t ep);
diff --git a/os/hal/include/spi.h b/os/hal/include/spi.h
index 5e0fa9e53..48182e65d 100644
--- a/os/hal/include/spi.h
+++ b/os/hal/include/spi.h
@@ -64,10 +64,6 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if SPI_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
-#error "SPI_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
-#endif
-
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -229,12 +225,7 @@ typedef enum {
  *
  * @notapi
  */
-#define _spi_wait_s(spip) {                                                 \
-  chDbgAssert((spip)->thread == NULL,                                       \
-              "_spi_wait(), #1", "already waiting");                        \
-  (spip)->thread = chThdSelf();                                             \
-  chSchGoSleepS(THD_STATE_SUSPENDED);                                       \
-}
+#define _spi_wait_s(spip) osalThreadSuspendS(&(spip)->thread)
 
 /**
  * @brief   Wakes up the waiting thread.
@@ -244,14 +235,9 @@ typedef enum {
  * @notapi
  */
 #define _spi_wakeup_isr(spip) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((spip)->thread != NULL) {                                             \
-    Thread *tp = (spip)->thread;                                            \
-    (spip)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = RDY_OK;                                                \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
+  osalSysLockFromISR();                                                     \
+  osalThreadResumeI(&(spip)->thread, MSG_OK);                               \
+  osalSysUnlockFromISR();                                                   \
 }
 #else /* !SPI_USE_WAIT */
 #define _spi_wait_s(spip)
diff --git a/os/hal/include/st.h b/os/hal/include/st.h
new file mode 100644
index 000000000..ebe906f1c
--- /dev/null
+++ b/os/hal/include/st.h
@@ -0,0 +1,101 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    st.h
+ * @brief   ST Driver macros and structures.
+ * @details This header is designed to be include-able without having to
+ *          include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef _ST_H_
+#define _ST_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+#include "st_lld.h"
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Returns the time counter value.
+ * @note    This functionality is only available in free running mode, the
+ *          behaviour in periodic mode is undefined.
+ *
+ * @return              The counter value.
+ *
+ * @api
+ */
+#define stGetCounter() st_lld_get_counter()
+
+/**
+ * @brief   Determines if the alarm is active.
+ *
+ * @return              The alarm status.
+ * @retval false        if the alarm is not active.
+ * @retval true         is the alarm is active
+ *
+ * @api
+ */
+#define stIsAlarmActive() st_lld_is_alarm_active()
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void stInit(void);
+  void stStartAlarm(systime_t time);
+  void stStopAlarm(void);
+  void stSetAlarm(systime_t time);
+  systime_t stGetAlarm(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ST_H_ */
+
+/** @} */
diff --git a/os/hal/include/tm.h b/os/hal/include/tm.h
deleted file mode 100644
index 14578a167..000000000
--- a/os/hal/include/tm.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    tm.h
- * @brief   Time Measurement driver header.
- *
- * @addtogroup TM
- * @{
- */
-
-#ifndef _TM_H_
-#define _TM_H_
-
-#if HAL_USE_TM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a Time Measurement object.
- * @note    Start/stop of measurements is performed through the function
- *          pointers in order to avoid inlining of those functions which
- *          could compromise measurement accuracy.
- * @note    The maximum measurable time period depends on the implementation
- *          of the realtime counter in the HAL driver.
- * @note    The measurement is not 100% cycle-accurate, it can be in excess
- *          of few cycles depending on the compiler and target architecture.
- * @note    Interrupts can affect measurement if the measurement is performed
- *          with interrupts enabled.
- */
-typedef struct TimeMeasurement TimeMeasurement;
-
-/**
- * @brief   Time Measurement structure.
- */
-struct TimeMeasurement {
-  void (*start)(TimeMeasurement *tmp);  /**< @brief Starts a measurement.   */
-  void (*stop)(TimeMeasurement *tmp);   /**< @brief Stops a measurement.    */
-  halrtcnt_t           last;            /**< @brief Last measurement.       */
-  halrtcnt_t           worst;           /**< @brief Worst measurement.      */
-  halrtcnt_t           best;            /**< @brief Best measurement.       */
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Starts a measurement.
- * @pre     The @p TimeMeasurement must be initialized.
- * @note    This function can be invoked in any context.
- *
- * @param[in,out] tmp   pointer to a @p TimeMeasurement structure
- *
- * @special
- */
-#define tmStartMeasurement(tmp) (tmp)->start(tmp)
-
-/**
- * @brief   Stops a measurement.
- * @pre     The @p TimeMeasurement must be initialized.
- * @note    This function can be invoked in any context.
- *
- * @param[in,out] tmp   pointer to a @p TimeMeasurement structure
- *
- * @special
- */
-#define tmStopMeasurement(tmp) (tmp)->stop(tmp)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void tmInit(void);
-  void tmObjectInit(TimeMeasurement *tmp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_TM */
-
-#endif /* _TM_H_ */
-
-/** @} */
diff --git a/os/hal/include/usb.h b/os/hal/include/usb.h
index 3d34708eb..790a08fab 100644
--- a/os/hal/include/usb.h
+++ b/os/hal/include/usb.h
@@ -325,7 +325,7 @@ typedef void (*usbeventcb_t)(USBDriver *usbp, usbevent_t event);
  * @retval FALSE        Request not recognized by the handler.
  * @retval TRUE         Request handled.
  */
-typedef bool_t (*usbreqhandler_t)(USBDriver *usbp);
+typedef bool (*usbreqhandler_t)(USBDriver *usbp);
 
 /**
  * @brief   Type of an USB descriptor-retrieving callback.
@@ -556,13 +556,13 @@ extern "C" {
   void usbPrepareTransmit(USBDriver *usbp, usbep_t ep,
                           const uint8_t *buf, size_t n);
   void usbPrepareQueuedReceive(USBDriver *usbp, usbep_t ep,
-                               InputQueue *iqp, size_t n);
+                               input_queue_t *iqp, size_t n);
   void usbPrepareQueuedTransmit(USBDriver *usbp, usbep_t ep,
-                                OutputQueue *oqp, size_t n);
-  bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep);
-  bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep);
-  bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep);
-  bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep);
+                                output_queue_t *oqp, size_t n);
+  bool usbStartReceiveI(USBDriver *usbp, usbep_t ep);
+  bool usbStartTransmitI(USBDriver *usbp, usbep_t ep);
+  bool usbStallReceiveI(USBDriver *usbp, usbep_t ep);
+  bool usbStallTransmitI(USBDriver *usbp, usbep_t ep);
   void _usb_reset(USBDriver *usbp);
   void _usb_ep0setup(USBDriver *usbp, usbep_t ep);
   void _usb_ep0in(USBDriver *usbp, usbep_t ep);
diff --git a/os/hal/osal/nil/osal.c b/os/hal/osal/nil/osal.c
new file mode 100644
index 000000000..d2927bc12
--- /dev/null
+++ b/os/hal/osal/nil/osal.c
@@ -0,0 +1,118 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    osal.c
+ * @brief   OSAL module code.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#include "osal.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Dequeues and wakes up one thread from the queue, if any.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+  semaphore_t *sp = &tqp->sem;
+
+  if (chSemGetCounterI(&tqp->sem) < 0) {
+    thread_reference_t tr = nil.threads;
+    while (true) {
+      /* Is this thread waiting on this semaphore?*/
+      if (tr->u1.semp == sp) {
+        sp->cnt++;
+
+        chDbgAssert(NIL_THD_IS_WTSEM(tr), "not waiting");
+
+        chSchReadyI(tr, msg);
+        return;
+      }
+      tr++;
+
+      chDbgAssert(tr < &nil.threads[NIL_CFG_NUM_THREADS],
+                  "pointer out of range");
+    }
+  }
+}
+
+/**
+ * @brief   Dequeues and wakes up all threads from the queue.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) {
+  semaphore_t *sp = &tqp->sem;
+  thread_reference_t tr;
+  cnt_t cnt;
+
+  cnt = sp->cnt;
+  sp->cnt = 0;
+  tr = nil.threads;
+  while (cnt < 0) {
+    /* Is this thread waiting on this semaphore?*/
+    if (tr->u1.semp == sp) {
+
+      chDbgAssert(NIL_THD_IS_WTSEM(tr), "not waiting");
+
+      cnt++;
+      chSchReadyI(tr, msg);
+    }
+    tr++;
+
+    chDbgAssert(tr < &nil.threads[NIL_CFG_NUM_THREADS],
+                "pointer out of range");
+  }
+}
+
+/** @} */
diff --git a/os/hal/osal/nil/osal.h b/os/hal/osal/nil/osal.h
new file mode 100644
index 000000000..d0811d444
--- /dev/null
+++ b/os/hal/osal/nil/osal.h
@@ -0,0 +1,820 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    osal.h
+ * @brief   OSAL module header.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#ifndef _OSAL_H_
+#define _OSAL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Common constants
+ * @{
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE                               0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                                (!FALSE)
+#endif
+
+#define OSAL_SUCCESS                        FALSE
+#define OSAL_FAILED                         TRUE
+/** @} */
+
+#if 0
+/**
+ * @name    Messages
+ * @{
+ */
+#define MSG_OK                              RDY_OK
+#define MSG_RESET                           RDY_RESET
+#define MSG_TIMEOUT                         RDY_TIMEOUT
+/** @} */
+#endif
+
+#if 0
+/**
+ * @name    Special time constants
+ * @{
+ */
+#define TIME_IMMEDIATE                      ((systime_t)0)
+#define TIME_INFINITE                       ((systime_t)-1)
+/** @} */
+#endif
+
+/**
+ * @name    Systick modes.
+ * @{
+ */
+#define OSAL_ST_MODE_NONE                   0
+#define OSAL_ST_MODE_PERIODIC               1
+#define OSAL_ST_MODE_FREERUNNING            2
+/** @} */
+
+/**
+ * @name    Systick parameters.
+ * @{
+ */
+/**
+ * @brief   Size in bits of the @p systick_t type.
+ */
+#define OSAL_ST_RESOLUTION                  NIL_CFG_ST_RESOLUTION
+
+/**
+ * @brief   Required systick frequency or resolution.
+ */
+#define OSAL_ST_FREQUENCY                   NIL_CFG_ST_FREQUENCY
+
+/**
+ * @brief   Systick mode required by the underlying OS.
+ */
+#if (NIL_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__)
+#define OSAL_ST_MODE                        OSAL_ST_MODE_PERIODIC
+#else
+#define OSAL_ST_MODE                        OSAL_ST_MODE_FREERUNNING
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !NIL_CFG_USE_EVENTS
+#error "OSAL requires NIL_CFG_USE_EVENTS=TRUE"
+#endif
+
+#if !(OSAL_ST_MODE == OSAL_ST_MODE_NONE) &&                                 \
+    !(OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) &&                             \
+    !(OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING)
+#error "invalid OSAL_ST_MODE setting in osal.h"
+#endif
+
+#if (OSAL_ST_RESOLUTION != 16) && (OSAL_ST_RESOLUTION != 32)
+#error "invalid OSAL_ST_RESOLUTION, must be 16 or 32"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+#if 0
+/**
+ * @brief   Type of a system status word.
+ */
+typedef uint32_t syssts_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of a message.
+ */
+typedef int32_t msg_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of system time counter.
+ */
+typedef uint32_t systime_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of realtime counter.
+ */
+typedef uint32_t rtcnt_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+#endif
+
+/**
+ * @brief   Type of an event flags object.
+ * @note    The content of this structure is not part of the API and should
+ *          not be relied upon. Implementers may define this structure in
+ *          an entirely different way.
+ * @note    Retrieval and clearing of the flags are not defined in this
+ *          API and are implementation-dependent.
+ */
+typedef struct event_source event_source_t;
+
+/**
+ * @brief   Type of an event source callback.
+ * @note    This type is not part of the OSAL API and is provided
+ *          exclusively as an example and for convenience.
+ */
+typedef void (*eventcallback_t)(event_source_t *);
+
+/**
+ * @brief   Type of an event flags mask.
+ */
+typedef uint32_t eventflags_t;
+
+/**
+ * @brief   Events source object.
+ * @note    The content of this structure is not part of the API and should
+ *          not be relied upon. Implementers may define this structure in
+ *          an entirely different way.
+ * @note    Retrieval and clearing of the flags are not defined in this
+ *          API and are implementation-dependent.
+ */
+struct event_source {
+  volatile eventflags_t flags;      /**< @brief Stored event flags.         */
+  eventcallback_t       cb;         /**< @brief Event source callback.      */
+  void                  *param;     /**< @brief User defined field.         */
+};
+
+/**
+ * @brief   Type of a mutex.
+ * @note    If the OS does not support mutexes or there is no OS then them
+ *          mechanism can be simulated.
+ */
+typedef semaphore_t mutex_t;
+
+/**
+ * @brief   Type of a thread queue.
+ * @details A thread queue is a queue of sleeping threads, queued threads
+ *          can be dequeued one at time or all together.
+ * @note    In this implementation it is implemented as a single reference
+ *          because there are no real threads.
+ */
+typedef struct {
+  semaphore_t   sem;
+} threads_queue_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Debug related macros
+ * @{
+ */
+/**
+ * @brief   Condition assertion.
+ * @details If the condition check fails then the OSAL panics with a
+ *          message and halts.
+ * @note    The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS
+ *          switch is enabled.
+ * @note    The convention for the message is the following:<br>
+ *          @<function_name@>(), #@<assert_number@>
+ * @note    The remark string is not currently used except for putting a
+ *          comment in the code about the assertion.
+ *
+ * @param[in] c         the condition to be verified to be true
+ * @param[in] remark    a remark string
+ *
+ * @api
+ */
+#define osalDbgAssert(c, remark) chDbgAssert(c, remark)
+
+/**
+ * @brief   Function parameters check.
+ * @details If the condition check fails then the OSAL panics and halts.
+ * @note    The condition is tested only if the @p OSAL_ENABLE_CHECKS switch
+ *          is enabled.
+ *
+ * @param[in] c         the condition to be verified to be true
+ *
+ * @api
+ */
+#define osalDbgCheck(c) chDbgAssert(c, "parameter check")
+
+/**
+ * @brief   I-Class state check.
+ * @note    Not implemented in this simplified OSAL.
+ */
+#define osalDbgCheckClassI() /*chDbgCheckClassI()*/
+/** @} */
+
+/**
+ * @brief   S-Class state check.
+ * @note    Not implemented in this simplified OSAL.
+ */
+#define osalDbgCheckClassS() /*chDbgCheckClassS()*/
+
+/**
+ * @name    IRQ service routines wrappers
+ * @{
+ */
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers.
+ */
+#define OSAL_IRQ_PROLOGUE() CH_IRQ_PROLOGUE()
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers.
+ */
+#define OSAL_IRQ_EPILOGUE() CH_IRQ_EPILOGUE()
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @details This macro hides the details of an ISR function declaration.
+ *
+ * @param[in] id        a vector name as defined in @p vectors.s
+ */
+#define OSAL_IRQ_HANDLER(id) CH_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name    Time conversion utilities
+ * @{
+ */
+/**
+ * @brief   Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec       number of seconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_S2ST(sec) S2ST(sec)
+
+/**
+ * @brief   Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec      number of milliseconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_MS2ST(msec) MS2ST(msec)
+/**
+ * @brief   Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec      number of microseconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_US2ST(usec) US2ST(usec)
+/** @} */
+
+/**
+ * @name    Sleep macros using absolute time
+ * @{
+ */
+/**
+ * @brief   Delays the invoking thread for the specified number of seconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system tick clock.
+ * @note    The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] sec       time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec))
+
+/**
+ * @brief   Delays the invoking thread for the specified number of
+ *          milliseconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system tick clock.
+ * @note    The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] msec      time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec))
+
+/**
+ * @brief   Delays the invoking thread for the specified number of
+ *          microseconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system tick clock.
+ * @note    The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] usec      time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+   void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg);
+   void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   OSAL module initialization.
+ *
+ * @api
+ */
+static inline void osalInit(void) {
+
+}
+
+/**
+ * @brief   System halt with error message.
+ *
+ * @param[in] reason    the halt message pointer
+ *
+ * @api
+ */
+static inline void osalSysHalt(const char *reason) {
+
+  chSysHalt(reason);
+}
+
+/**
+ * @brief   Enters a critical zone from thread context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLock(void) {
+
+  chSysLock();
+}
+
+/**
+ * @brief   Leaves a critical zone from thread context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlock(void) {
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Enters a critical zone from ISR context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLockFromISR(void) {
+
+  chSysLockFromISR();
+}
+
+/**
+ * @brief   Leaves a critical zone from ISR context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlockFromISR(void) {
+
+  chSysUnlockFromISR();
+}
+
+/**
+ * @brief   Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ *          from any context. Because its flexibility it is less efficient
+ *          than @p chSysLock() which is preferable when the calling context
+ *          is known.
+ * @post    The system is in a critical zone.
+ *
+ * @return              The previous system status, the encoding of this
+ *                      status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+static inline syssts_t osalSysGetStatusAndLockX(void)  {
+
+  return chSysGetStatusAndLockX();
+}
+
+/**
+ * @brief   Restores the specified execution status and leaves a critical zone.
+ * @note    A call to @p chSchRescheduleS() is automatically performed
+ *          if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts       the system status to be restored.
+ *
+ * @xclass
+ */
+static inline void osalSysRestoreStatusX(syssts_t sts) {
+
+  chSysRestoreStatusX(sts);
+}
+
+/**
+ * @brief   Polled delay.
+ * @note    The real delay is always few cycles in excess of the specified
+ *          value.
+ *
+ * @param[in] cycles    number of cycles
+ *
+ * @xclass
+ */
+#if PORT_SUPPORTS_RT || defined(__DOXYGEN__)
+static inline void osalSysPolledDelayX(rtcnt_t cycles) {
+
+  chSysPolledDelayX(cycles);
+}
+#endif
+
+/**
+ * @brief   Systick callback for the underlying OS.
+ * @note    This callback is only defined if the OSAL requires such a
+ *          service from the HAL.
+ */
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+static inline void osalOsTimerHandlerI(void) {
+
+  chSysTimerHandlerI();
+}
+#endif
+
+/**
+ * @brief   Checks if a reschedule is required and performs it.
+ * @note    I-Class functions invoked from thread context must not reschedule
+ *          by themselves, an explicit reschedule using this function is
+ *          required in this scenario.
+ * @note    Not implemented in this simplified OSAL.
+ *
+ * @sclass
+ */
+static inline void osalOsRescheduleS(void) {
+
+  chSchRescheduleS();
+}
+
+/**
+ * @brief   Current system time.
+ * @details Returns the number of system ticks since the @p chSysInit()
+ *          invocation.
+ * @note    The counter can reach its maximum and then restart from zero.
+ * @note    This function can be called from any context but its atomicity
+ *          is not guaranteed on architectures whose word size is less than
+ *          @systime_t size.
+ *
+ * @return              The system time in ticks.
+ *
+ * @xclass
+ */
+static inline systime_t osalOsGetSystemTimeX(void) {
+
+  return chVTGetSystemTimeX();
+}
+
+/**
+ * @brief   Checks if the specified time is within the specified time window.
+ * @note    When start==end then the function returns always true because the
+ *          whole time range is specified.
+ * @note    This function can be called from any context.
+ *
+ * @param[in] time      the time to be verified
+ * @param[in] start     the start of the time window (inclusive)
+ * @param[in] end       the end of the time window (non inclusive)
+ * @retval true         current time within the specified time window.
+ * @retval false        current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool osalOsIsTimeWithinX(systime_t time,
+                                       systime_t start,
+                                       systime_t end) {
+
+  return chVTIsTimeWithinX(time, start, end);
+}
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time      the delay in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE is allowed but interpreted as a
+ *                        normal time specification.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ *
+ * @sclass
+ */
+static inline void osalThreadSleepS(systime_t time) {
+
+  chThdSleepS(time);
+}
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time      the delay in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE is allowed but interpreted as a
+ *                        normal time specification.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ *
+ * @api
+ */
+static inline void osalThreadSleep(systime_t time) {
+
+  chThdSleep(time);
+}
+
+/**
+ * @brief   Sends the current thread sleeping and sets a reference variable.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @return              The wake up message.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadSuspendS(thread_reference_t *trp) {
+
+  return chThdSuspendTimeoutS(trp, TIME_INFINITE);
+}
+
+/**
+ * @brief   Sends the current thread sleeping and sets a reference variable.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] timeout   the timeout in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state.
+ *                      - @a TIME_IMMEDIATE the thread is not enqueued and
+ *                        the function returns @p MSG_TIMEOUT as if a timeout
+ *                        occurred.
+ *                      .
+ * @return              The wake up message.
+ * @retval MSG_TIMEOUT  if the operation timed out.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp,
+                                              systime_t timeout) {
+
+  return chThdSuspendTimeoutS(trp, timeout);
+}
+
+/**
+ * @brief   Wakes up a thread waiting on a thread reference object.
+ * @note    This function must not reschedule because it can be called from
+ *          ISR context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadResumeI(thread_reference_t *trp, msg_t msg) {
+
+  chThdResumeI(trp, msg);
+}
+
+/**
+ * @brief   Wakes up a thread waiting on a thread reference object.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadResumeS(thread_reference_t *trp, msg_t msg) {
+
+  chThdResumeI(trp, msg);
+  chSchRescheduleS();
+}
+
+/**
+ * @brief   Initializes a threads queue object.
+ *
+ * @param[out] tqp      pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) {
+
+  chSemObjectInit(&tqp->sem, 0);
+}
+
+/**
+ * @brief   Enqueues the caller thread.
+ * @details The caller thread is enqueued and put to sleep until it is
+ *          dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] time      the timeout in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state.
+ *                      - @a TIME_IMMEDIATE the thread is not enqueued and
+ *                        the function returns @p MSG_TIMEOUT as if a timeout
+ *                        occurred.
+ *                      .
+ * @return              The message from @p osalQueueWakeupOneI() or
+ *                      @p osalQueueWakeupAllI() functions.
+ * @retval RDY_TIMEOUT  if the thread has not been dequeued within the
+ *                      specified timeout or if the function has been
+ *                      invoked with @p TIME_IMMEDIATE as timeout
+ *                      specification.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp,
+                                              systime_t time) {
+
+  return chSemWaitTimeout(&tqp->sem, time);
+}
+
+/**
+ * @brief   Initializes an event flags object.
+ *
+ * @param[out] esp      pointer to the event flags object
+ *
+ * @init
+ */
+static inline void osalEventObjectInit(event_source_t *esp) {
+
+  esp->flags = 0;
+  esp->cb    = NULL;
+  esp->param = NULL;
+}
+
+/**
+ * @brief   Add flags to an event source object.
+ *
+ * @param[in] esp       pointer to the event flags object
+ * @param[in] flags     flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlagsI(event_source_t *esp,
+                                            eventflags_t flags) {
+
+  esp->flags |= flags;
+  if (esp->cb != NULL)
+    esp->cb(esp);
+}
+
+/**
+ * @brief   Add flags to an event source object.
+ *
+ * @param[in] esp       pointer to the event flags object
+ * @param[in] flags     flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlags(event_source_t *esp,
+                                           eventflags_t flags) {
+
+  chSysLock();
+  osalEventBroadcastFlagsI(esp, flags);
+  chSchRescheduleS();
+  chSysUnlock();
+}
+
+/**
+ * @brief   Initializes s @p mutex_t object.
+ *
+ * @param[out] mp       pointer to the @p mutex_t object
+ *
+ * @init
+ */
+static inline void osalMutexObjectInit(mutex_t *mp) {
+
+  chSemObjectInit((semaphore_t *)mp, 1);
+}
+
+/*
+ * @brief   Locks the specified mutex.
+ * @post    The mutex is locked and inserted in the per-thread stack of owned
+ *          mutexes.
+ *
+ * @param[in,out] mp    pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexLock(mutex_t *mp) {
+
+  chSemWait((semaphore_t *)mp);
+}
+
+/**
+ * @brief   Unlocks the specified mutex.
+ * @note    The HAL guarantees to release mutex in reverse lock order. The
+ *          mutex being unlocked is guaranteed to be the last locked mutex
+ *          by the invoking thread.
+ *          The implementation can rely on this behavior and eventually
+ *          ignore the @p mp parameter which is supplied in order to support
+ *          those OSes not supporting a stack of the owned mutexes.
+ *
+ * @param[in,out] mp    pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexUnlock(mutex_t *mp) {
+
+  chSemSignal((semaphore_t *)mp);
+}
+
+#endif /* _OSAL_H_ */
+
+/** @} */
diff --git a/os/hal/osal/nil/osal.mk b/os/hal/osal/nil/osal.mk
new file mode 100644
index 000000000..b4872a691
--- /dev/null
+++ b/os/hal/osal/nil/osal.mk
@@ -0,0 +1,5 @@
+# OSAL files.
+OSALSRC += ${CHIBIOS}/os/hal/osal/nil/osal.c
+
+# Required include directories
+OSALINC += ${CHIBIOS}/os/hal/osal/nil
diff --git a/os/hal/osal/rt/osal.c b/os/hal/osal/rt/osal.c
new file mode 100644
index 000000000..52fc27041
--- /dev/null
+++ b/os/hal/osal/rt/osal.c
@@ -0,0 +1,55 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    osal.c
+ * @brief   OSAL module code.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#include "osal.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/** @} */
diff --git a/os/hal/osal/rt/osal.h b/os/hal/osal/rt/osal.h
new file mode 100644
index 000000000..ab648d720
--- /dev/null
+++ b/os/hal/osal/rt/osal.h
@@ -0,0 +1,852 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    osal.h
+ * @brief   OSAL module header.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#ifndef _OSAL_H_
+#define _OSAL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Common constants
+ * @{
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE                               0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                                (!FALSE)
+#endif
+
+#define OSAL_SUCCESS                        FALSE
+#define OSAL_FAILED                         TRUE
+/** @} */
+
+#if 0
+/**
+ * @name    Messages
+ * @{
+ */
+#define MSG_OK                              RDY_OK
+#define MSG_RESET                           RDY_RESET
+#define MSG_TIMEOUT                         RDY_TIMEOUT
+/** @} */
+#endif
+
+#if 0
+/**
+ * @name    Special time constants
+ * @{
+ */
+#define TIME_IMMEDIATE                      ((systime_t)0)
+#define TIME_INFINITE                       ((systime_t)-1)
+/** @} */
+#endif
+
+/**
+ * @name    Systick modes.
+ * @{
+ */
+#define OSAL_ST_MODE_NONE                   0
+#define OSAL_ST_MODE_PERIODIC               1
+#define OSAL_ST_MODE_FREERUNNING            2
+/** @} */
+
+/**
+ * @name    Systick parameters.
+ * @{
+ */
+/**
+ * @brief   Size in bits of the @p systick_t type.
+ */
+#define OSAL_ST_RESOLUTION                  CH_CFG_ST_RESOLUTION
+
+/**
+ * @brief   Required systick frequency or resolution.
+ */
+#define OSAL_ST_FREQUENCY                   CH_CFG_ST_FREQUENCY
+
+/**
+ * @brief   Systick mode required by the underlying OS.
+ */
+#if (CH_CFG_ST_TIMEDELTA == 0) || defined(__DOXYGEN__)
+#define OSAL_ST_MODE                        OSAL_ST_MODE_PERIODIC
+#else
+#define OSAL_ST_MODE                        OSAL_ST_MODE_FREERUNNING
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !(OSAL_ST_MODE == OSAL_ST_MODE_NONE) &&                                 \
+    !(OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) &&                             \
+    !(OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING)
+#error "invalid OSAL_ST_MODE setting in osal.h"
+#endif
+
+#if (OSAL_ST_RESOLUTION != 16) && (OSAL_ST_RESOLUTION != 32)
+#error "invalid OSAL_ST_RESOLUTION, must be 16 or 32"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/* Temporary types provided for ChibiOS 2.x compatibility.*/
+typedef io_queue_t GenericQueue;
+typedef input_queue_t InputQueue;
+typedef output_queue_t OutputQueue;
+typedef bool bool_t;
+#define OSAL_FREQUENCY OSAL_ST_FREQUENCY
+
+#if 0
+/**
+ * @brief   Type of a system status word.
+ */
+typedef uint32_t syssts_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of a message.
+ */
+typedef int32_t msg_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of system time counter.
+ */
+typedef uint32_t systime_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of realtime counter.
+ */
+typedef uint32_t rtcnt_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of an event flags mask.
+ */
+typedef uint32_t eventflags_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of an event flags object.
+ * @note    The content of this structure is not part of the API and should
+ *          not be relied upon. Implementers may define this structure in
+ *          an entirely different way.
+ * @note    Retrieval and clearing of the flags are not defined in this
+ *          API and are implementation-dependent.
+ */
+typedef struct {
+  volatile eventflags_t flags;      /**< @brief Flags stored into the
+                                                object.                     */
+} event_source_t;
+#endif
+
+/**
+ * @brief   Type of a mutex.
+ * @note    If the OS does not support mutexes or there is no OS then them
+ *          mechanism can be simulated.
+ */
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+#elif CH_CFG_USE_SEMAPHORES
+typedef semaphore_t mutex_t;
+#else
+typedef uint32_t mutex_t;
+#endif
+
+#if 0
+/**
+ * @brief   Type of a thread queue.
+ * @details A thread queue is a queue of sleeping threads, queued threads
+ *          can be dequeued one at time or all together.
+ * @note    In this implementation it is implemented as a single reference
+ *          because there are no real threads.
+ */
+typedef struct {
+  thread_reference_t    tr;
+} threads_queue_t;
+#endif
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Debug related macros
+ * @{
+ */
+/**
+ * @brief   Condition assertion.
+ * @details If the condition check fails then the OSAL panics with a
+ *          message and halts.
+ * @note    The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS
+ *          switch is enabled.
+ * @note    The convention for the message is the following:<br>
+ *          @<function_name@>(), #@<assert_number@>
+ * @note    The remark string is not currently used except for putting a
+ *          comment in the code about the assertion.
+ *
+ * @param[in] c         the condition to be verified to be true
+ * @param[in] remark    a remark string
+ *
+ * @api
+ */
+#define osalDbgAssert(c, remark) chDbgAssert(c, remark)
+
+/**
+ * @brief   Function parameters check.
+ * @details If the condition check fails then the OSAL panics and halts.
+ * @note    The condition is tested only if the @p OSAL_ENABLE_CHECKS switch
+ *          is enabled.
+ *
+ * @param[in] c         the condition to be verified to be true
+ *
+ * @api
+ */
+#define osalDbgCheck(c) chDbgCheck(c)
+
+/**
+ * @brief   I-Class state check.
+ * @note    Not implemented in this simplified OSAL.
+ */
+#define osalDbgCheckClassI() chDbgCheckClassI()
+/** @} */
+
+/**
+ * @brief   S-Class state check.
+ * @note    Not implemented in this simplified OSAL.
+ */
+#define osalDbgCheckClassS() chDbgCheckClassS()
+
+/**
+ * @name    IRQ service routines wrappers
+ * @{
+ */
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers.
+ */
+#define OSAL_IRQ_PROLOGUE() CH_IRQ_PROLOGUE()
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers.
+ */
+#define OSAL_IRQ_EPILOGUE() CH_IRQ_EPILOGUE()
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @details This macro hides the details of an ISR function declaration.
+ *
+ * @param[in] id        a vector name as defined in @p vectors.s
+ */
+#define OSAL_IRQ_HANDLER(id) CH_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name    Time conversion utilities
+ * @{
+ */
+/**
+ * @brief   Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec       number of seconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_S2ST(sec) S2ST(sec)
+
+/**
+ * @brief   Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec      number of milliseconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_MS2ST(msec) MS2ST(msec)
+
+/**
+ * @brief   Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec      number of microseconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define OSAL_US2ST(usec) US2ST(usec)
+/** @} */
+
+/**
+ * @name    Sleep macros using absolute time
+ * @{
+ */
+/**
+ * @brief   Delays the invoking thread for the specified number of seconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system tick clock.
+ * @note    The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] sec       time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepSeconds(sec) osalThreadSleep(OSAL_S2ST(sec))
+
+/**
+ * @brief   Delays the invoking thread for the specified number of
+ *          milliseconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system tick clock.
+ * @note    The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] msec      time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMilliseconds(msec) osalThreadSleep(OSAL_MS2ST(msec))
+
+/**
+ * @brief   Delays the invoking thread for the specified number of
+ *          microseconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system tick clock.
+ * @note    The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] usec      time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define osalThreadSleepMicroseconds(usec) osalThreadSleep(OSAL_US2ST(usec))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   OSAL module initialization.
+ *
+ * @api
+ */
+static inline void osalInit(void) {
+
+}
+
+/**
+ * @brief   System halt with error message.
+ *
+ * @param[in] reason    the halt message pointer
+ *
+ * @api
+ */
+static inline void osalSysHalt(const char *reason) {
+
+  chSysHalt(reason);
+}
+
+/**
+ * @brief   Enters a critical zone from thread context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLock(void) {
+
+  chSysLock();
+}
+
+/**
+ * @brief   Leaves a critical zone from thread context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlock(void) {
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Enters a critical zone from ISR context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLockFromISR(void) {
+
+  chSysLockFromISR();
+}
+
+/**
+ * @brief   Leaves a critical zone from ISR context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlockFromISR(void) {
+
+  chSysUnlockFromISR();
+}
+
+/**
+ * @brief   Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ *          from any context. Because its flexibility it is less efficient
+ *          than @p chSysLock() which is preferable when the calling context
+ *          is known.
+ * @post    The system is in a critical zone.
+ *
+ * @return              The previous system status, the encoding of this
+ *                      status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+static inline syssts_t osalSysGetStatusAndLockX(void)  {
+
+  return chSysGetStatusAndLockX();
+}
+
+/**
+ * @brief   Restores the specified execution status and leaves a critical zone.
+ * @note    A call to @p chSchRescheduleS() is automatically performed
+ *          if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts       the system status to be restored.
+ *
+ * @xclass
+ */
+static inline void osalSysRestoreStatusX(syssts_t sts) {
+
+  chSysRestoreStatusX(sts);
+}
+
+/**
+ * @brief   Polled delay.
+ * @note    The real delay is always few cycles in excess of the specified
+ *          value.
+ *
+ * @param[in] cycles    number of cycles
+ *
+ * @xclass
+ */
+#if PORT_SUPPORTS_RT || defined(__DOXYGEN__)
+static inline void osalSysPolledDelayX(rtcnt_t cycles) {
+
+  chSysPolledDelayX(cycles);
+}
+#endif
+
+/**
+ * @brief   Systick callback for the underlying OS.
+ * @note    This callback is only defined if the OSAL requires such a
+ *          service from the HAL.
+ */
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+static inline void osalOsTimerHandlerI(void) {
+
+  chSysTimerHandlerI();
+}
+#endif
+
+/**
+ * @brief   Checks if a reschedule is required and performs it.
+ * @note    I-Class functions invoked from thread context must not reschedule
+ *          by themselves, an explicit reschedule using this function is
+ *          required in this scenario.
+ * @note    Not implemented in this simplified OSAL.
+ *
+ * @sclass
+ */
+static inline void osalOsRescheduleS(void) {
+
+  chSchRescheduleS();
+}
+
+/**
+ * @brief   Current system time.
+ * @details Returns the number of system ticks since the @p chSysInit()
+ *          invocation.
+ * @note    The counter can reach its maximum and then restart from zero.
+ * @note    This function can be called from any context but its atomicity
+ *          is not guaranteed on architectures whose word size is less than
+ *          @systime_t size.
+ *
+ * @return              The system time in ticks.
+ *
+ * @xclass
+ */
+static inline systime_t osalOsGetSystemTimeX(void) {
+
+  return chVTGetSystemTimeX();
+}
+
+/**
+ * @brief   Checks if the specified time is within the specified time window.
+ * @note    When start==end then the function returns always true because the
+ *          whole time range is specified.
+ * @note    This function can be called from any context.
+ *
+ * @param[in] time      the time to be verified
+ * @param[in] start     the start of the time window (inclusive)
+ * @param[in] end       the end of the time window (non inclusive)
+ * @retval true         current time within the specified time window.
+ * @retval false        current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool osalOsIsTimeWithinX(systime_t time,
+                                       systime_t start,
+                                       systime_t end) {
+
+  return chVTIsTimeWithinX(time, start, end);
+}
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time      the delay in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE is allowed but interpreted as a
+ *                        normal time specification.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ *
+ * @sclass
+ */
+static inline void osalThreadSleepS(systime_t time) {
+
+  chThdSleepS(time);
+}
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time      the delay in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE is allowed but interpreted as a
+ *                        normal time specification.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ *
+ * @api
+ */
+static inline void osalThreadSleep(systime_t time) {
+
+  chThdSleep(time);
+}
+
+/**
+ * @brief   Sends the current thread sleeping and sets a reference variable.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @return              The wake up message.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadSuspendS(thread_reference_t *trp) {
+
+  return chThdSuspendS(trp);
+}
+
+/**
+ * @brief   Sends the current thread sleeping and sets a reference variable.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] timeout   the timeout in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state.
+ *                      - @a TIME_IMMEDIATE the thread is not enqueued and
+ *                        the function returns @p MSG_TIMEOUT as if a timeout
+ *                        occurred.
+ *                      .
+ * @return              The wake up message.
+ * @retval MSG_TIMEOUT  if the operation timed out.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadSuspendTimeoutS(thread_reference_t *trp,
+                                              systime_t timeout) {
+
+  return chThdSuspendTimeoutS(trp, timeout);
+}
+
+/**
+ * @brief   Wakes up a thread waiting on a thread reference object.
+ * @note    This function must not reschedule because it can be called from
+ *          ISR context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadResumeI(thread_reference_t *trp, msg_t msg) {
+
+  chThdResumeI(trp, msg);
+}
+
+/**
+ * @brief   Wakes up a thread waiting on a thread reference object.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadResumeS(thread_reference_t *trp, msg_t msg) {
+
+  chThdResumeS(trp, msg);
+}
+
+/**
+ * @brief   Initializes a threads queue object.
+ *
+ * @param[out] tqp      pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void osalThreadQueueObjectInit(threads_queue_t *tqp) {
+
+  chThdQueueObjectInit(tqp);
+}
+
+/**
+ * @brief   Enqueues the caller thread.
+ * @details The caller thread is enqueued and put to sleep until it is
+ *          dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] time      the timeout in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state.
+ *                      - @a TIME_IMMEDIATE the thread is not enqueued and
+ *                        the function returns @p MSG_TIMEOUT as if a timeout
+ *                        occurred.
+ *                      .
+ * @return              The message from @p osalQueueWakeupOneI() or
+ *                      @p osalQueueWakeupAllI() functions.
+ * @retval RDY_TIMEOUT  if the thread has not been dequeued within the
+ *                      specified timeout or if the function has been
+ *                      invoked with @p TIME_IMMEDIATE as timeout
+ *                      specification.
+ *
+ * @sclass
+ */
+static inline msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp,
+                                              systime_t time) {
+
+  return chThdEnqueueTimeoutS(tqp, time);
+}
+
+/**
+ * @brief   Dequeues and wakes up one thread from the queue, if any.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+
+  chThdDequeueNextI(tqp, msg);
+}
+
+/**
+ * @brief   Dequeues and wakes up all threads from the queue.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+static inline void osalThreadDequeueAllI(threads_queue_t *tqp, msg_t msg) {
+
+  chThdDequeueAllI(tqp, msg);
+}
+
+/**
+ * @brief   Initializes an event flags object.
+ *
+ * @param[out] esp      pointer to the event flags object
+ *
+ * @init
+ */
+static inline void osalEventObjectInit(event_source_t *esp) {
+
+  chEvtObjectInit(esp);
+}
+
+/**
+ * @brief   Add flags to an event source object.
+ *
+ * @param[in] esp       pointer to the event flags object
+ * @param[in] flags     flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlagsI(event_source_t *esp,
+                                            eventflags_t flags) {
+
+  chEvtBroadcastFlagsI(esp, flags);
+}
+
+/**
+ * @brief   Add flags to an event source object.
+ *
+ * @param[in] esp       pointer to the event flags object
+ * @param[in] flags     flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlags(event_source_t *esp,
+                                           eventflags_t flags) {
+
+  chEvtBroadcastFlags(esp, flags);
+}
+
+/**
+ * @brief   Initializes s @p mutex_t object.
+ *
+ * @param[out] mp       pointer to the @p mutex_t object
+ *
+ * @init
+ */
+static inline void osalMutexObjectInit(mutex_t *mp) {
+
+#if CH_CFG_USE_MUTEXES
+  chMtxObjectInit(mp);
+#elif CH_CFG_USE_SEMAPHORES
+  chSemObjectInit((semaphore_t *)mp, 1);
+#else
+ *mp = 0;
+#endif
+}
+
+/*
+ * @brief   Locks the specified mutex.
+ * @post    The mutex is locked and inserted in the per-thread stack of owned
+ *          mutexes.
+ *
+ * @param[in,out] mp    pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexLock(mutex_t *mp) {
+
+#if CH_CFG_USE_MUTEXES
+  chMtxLock(mp);
+#elif CH_CFG_USE_SEMAPHORES
+  chSemWait((semaphore_t *)mp);
+#else
+  *mp = 1;
+#endif
+}
+
+/**
+ * @brief   Unlocks the specified mutex.
+ * @note    The HAL guarantees to release mutex in reverse lock order. The
+ *          mutex being unlocked is guaranteed to be the last locked mutex
+ *          by the invoking thread.
+ *          The implementation can rely on this behavior and eventually
+ *          ignore the @p mp parameter which is supplied in order to support
+ *          those OSes not supporting a stack of the owned mutexes.
+ *
+ * @param[in,out] mp    pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexUnlock(mutex_t *mp) {
+
+#if CH_CFG_USE_MUTEXES
+  chMtxUnlock(mp);
+#elif CH_CFG_USE_SEMAPHORES
+  chSemSignal((semaphore_t *)mp);
+#else
+  *mp = 0;
+#endif
+}
+
+#endif /* _OSAL_H_ */
+
+/** @} */
diff --git a/os/hal/osal/rt/osal.mk b/os/hal/osal/rt/osal.mk
new file mode 100644
index 000000000..3d123c986
--- /dev/null
+++ b/os/hal/osal/rt/osal.mk
@@ -0,0 +1,5 @@
+# OSAL files.
+OSALSRC += ${CHIBIOS}/os/hal/osal/rt/osal.c
+
+# Required include directories
+OSALINC += ${CHIBIOS}/os/hal/osal/rt
diff --git a/os/hal/platforms/AT91SAM7/adc_lld.c b/os/hal/platforms/AT91SAM7/adc_lld.c
deleted file mode 100644
index 25fb4b5fa..000000000
--- a/os/hal/platforms/AT91SAM7/adc_lld.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   This file has been contributed by:
-		Andrew Hannam aka inmarket.
-*/
-/**
- * @file    AT91SAM7/adc_lld.c
- * @brief   AT91SAM7 ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/**
- * @brief	ADC1 Prescaler
- * @detail	Prescale = RoundUp(MCK / 2 / ADCClock - 1)
- */
-#if ((((MCK/2)+(AT91_ADC1_CLOCK-1))/AT91_ADC1_CLOCK)-1) > 255
-	#define AT91_ADC1_PRESCALE	255
-#else
-	#define AT91_ADC1_PRESCALE	((((MCK/2)+(AT91_ADC1_CLOCK-1))/AT91_ADC1_CLOCK)-1)
-#endif
-
-/**
- * @brief	ADC1 Startup Time
- * @details	Startup = RoundUp(ADCClock / 400,000 - 1)
- * @note	Corresponds to a startup delay > 20uS (as required from the datasheet)
- */
-#if (((AT91_ADC1_CLOCK+399999)/400000)-1) > 127
-	#define AT91_ADC1_STARTUP	127
-#else
-	#define AT91_ADC1_STARTUP	(((AT91_ADC1_CLOCK+399999)/400000)-1)
-#endif
-
-#if AT91_ADC1_RESOLUTION == 8
-	#define AT91_ADC1_MAINMODE		(((AT91_ADC1_SHTM & 0x0F) << 24) | ((AT91_ADC1_STARTUP & 0x7F) << 16) | ((AT91_ADC1_PRESCALE & 0xFF) << 8) | AT91C_ADC_LOWRES_8_BIT)
-#else
-	#define AT91_ADC1_MAINMODE		(((AT91_ADC1_SHTM & 0x0F) << 24) | ((AT91_ADC1_STARTUP & 0x7F) << 16) | ((AT91_ADC1_PRESCALE & 0xFF) << 8) | AT91C_ADC_LOWRES_10_BIT)
-#endif
-
-#if AT91_ADC1_TIMER < 0 || AT91_ADC1_TIMER > 2
-	#error "Unknown Timer specified for ADC1"
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if !ADC_USE_ADC1
-	#error "You must specify ADC_USE_ADC1 if you have specified HAL_USE_ADC"
-#endif
-
-/** @brief ADC1 driver identifier.*/
-ADCDriver ADCD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-#define ADCReg1		((AT91S_ADC *)AT91C_ADC_CR)
-
-#if AT91_ADC1_MAINMODE == 2
-	#define ADCTimer1				((AT91S_TC *)AT91C_TC2_CCR)
-	#define AT91_ADC1_TIMERMODE		AT91C_ADC_TRGSEL_TIOA2
-	#define AT91_ADC1_TIMERID		AT91C_ID_TC2
-#elif AT91_ADC1_MAINMODE == 1
-	#define ADCTimer1				((AT91S_TC *)AT91C_TC1_CCR)
-	#define AT91_ADC1_TIMERMODE		AT91C_ADC_TRGSEL_TIOA1
-	#define AT91_ADC1_TIMERID		AT91C_ID_TC1
-#else
-	#define ADCTimer1				((AT91S_TC *)AT91C_TC0_CCR)
-	#define AT91_ADC1_TIMERMODE		AT91C_ADC_TRGSEL_TIOA0
-	#define AT91_ADC1_TIMERID		AT91C_ID_TC0
-#endif
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#define adc_sleep()				ADCReg1->ADC_MR = (AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_MODE | AT91C_ADC_TRGEN_DIS)
-#define adc_wake()				ADCReg1->ADC_MR = (AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_DIS)
-#define adc_disable()			{																\
-									ADCReg1->ADC_IDR = 0xFFFFFFFF;								\
-									ADCReg1->ADC_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;	\
-									adc_wake();													\
-									ADCReg1->ADC_CHDR = 0xFF;									\
-								}
-#define adc_clrint()			{																\
-									uint32_t	isr, dummy;										\
-																								\
-									isr = ADCReg1->ADC_SR;										\
-									if ((isr & AT91C_ADC_DRDY)) dummy = ADCReg1->ADC_LCDR;		\
-									if ((isr & AT91C_ADC_EOC0)) dummy = ADCReg1->ADC_CDR0;		\
-									if ((isr & AT91C_ADC_EOC1)) dummy = ADCReg1->ADC_CDR1;		\
-									if ((isr & AT91C_ADC_EOC2)) dummy = ADCReg1->ADC_CDR2;		\
-									if ((isr & AT91C_ADC_EOC3)) dummy = ADCReg1->ADC_CDR3;		\
-									if ((isr & AT91C_ADC_EOC4)) dummy = ADCReg1->ADC_CDR4;		\
-									if ((isr & AT91C_ADC_EOC5)) dummy = ADCReg1->ADC_CDR5;		\
-									if ((isr & AT91C_ADC_EOC6)) dummy = ADCReg1->ADC_CDR6;		\
-									if ((isr & AT91C_ADC_EOC7)) dummy = ADCReg1->ADC_CDR7;		\
-									(void) dummy;												\
-								}
-#define adc_stop()				{																\
-									adc_disable();												\
-									adc_clrint();												\
-								}
-
-/**
- * We must keep stack usage to a minimum - the default AT91SAM7 isr stack size is very small.
- * We sacrifice some speed and code size in order to achieve this by accessing the structure
- * and registers directly rather than through the passed in pointers. This works because the
- * AT91SAM7 supports only a single ADC device (although with 8 channels).
- */
-static void handleint(void) {
-	uint32_t	isr;
-
-	isr = ADCReg1->ADC_SR;
-
-	if (ADCD1.grpp) {
-
-		/* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/
-		if ((isr & AT91C_ADC_GOVRE)) {
-			_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
-
-		/* Transfer complete processing.*/
-		} else if ((isr & AT91C_ADC_RXBUFF)) {
-			if (ADCD1.grpp->circular) {
-				/* setup the DMA again */
-				ADCReg1->ADC_RPR = (uint32_t)ADCD1.samples;
-				if (ADCD1.depth <= 1) {
-					ADCReg1->ADC_RCR = ADCD1.grpp->num_channels;
-					ADCReg1->ADC_RNPR = 0;
-					ADCReg1->ADC_RNCR = 0;
-				} else {
-					ADCReg1->ADC_RCR = ADCD1.depth/2 * ADCD1.grpp->num_channels;
-					ADCReg1->ADC_RNPR = (uint32_t)(ADCD1.samples + (ADCD1.depth/2 * ADCD1.grpp->num_channels));
-					ADCReg1->ADC_RNCR = (ADCD1.depth - ADCD1.depth/2) * ADCD1.grpp->num_channels;
-				}
-				ADCReg1->ADC_PTCR = AT91C_PDC_RXTEN;			// DMA enabled
-			}
-			_adc_isr_full_code(&ADCD1);
-
-		/* Half transfer processing.*/
-		} else if ((isr & AT91C_ADC_ENDRX)) {
-			// Make sure we get a full complete next time.
-			ADCReg1->ADC_RNPR = 0;
-			ADCReg1->ADC_RNCR = 0;
-			_adc_isr_half_code(&ADCD1);
-		}
-
-	} else {
-		/* Spurious interrupt - Make sure it doesn't happen again */
-		adc_disable();
-	}
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ADC interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(ADC_IRQHandler) {
-	CH_IRQ_PROLOGUE();
-
-	handleint();
-
-	AT91C_BASE_AIC->AIC_EOICR = 0;
-	CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-	/* Turn on ADC in the power management controller */
-	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_ADC);
-
-	/* Driver object initialization.*/
-	adcObjectInit(&ADCD1);
-
-	ADCReg1->ADC_CR = 0;				// 0 or AT91C_ADC_SWRST if you want to do a ADC reset
-	adc_stop();
-	adc_sleep();
-
-	/* Setup interrupt handler */
-	AIC_ConfigureIT(AT91C_ID_ADC,
-		  AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91_ADC_IRQ_PRIORITY,
-		  ADC_IRQHandler);
-	AIC_EnableIT(AT91C_ID_ADC);
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-	/* If in stopped state then wake up the ADC */
-	if (adcp->state == ADC_STOP) {
-
-    	/* Take it out of sleep mode */
-    	/* We could stay in sleep mode provided total conversion rate < 44kHz but we can't guarantee that here */
-    	adc_wake();
-
-    	/* TODO: We really should perform a conversion here just to ensure that we are out of sleep mode */
-    }
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-	if (adcp->state != ADC_READY) {
-		adc_stop();
-    	adc_sleep();
-	}
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-	uint32_t			i;
-	(void)				adcp;
-
-	/* Make sure everything is stopped first */
-	adc_stop();
-
-	/* Safety check the trigger value */
-	switch(ADCD1.grpp->trigger & ~ADC_TRIGGER_SOFTWARE) {
-	case ADC_TRIGGER_TIMER:
-	case ADC_TRIGGER_EXTERNAL:
-		break;
-	default:
-		((ADCConversionGroup *)ADCD1.grpp)->trigger = ADC_TRIGGER_SOFTWARE;
-		ADCD1.depth = 1;
-		((ADCConversionGroup *)ADCD1.grpp)->circular = 0;
-		break;
-	}
-
-	/* Count the real number of activated channels in case the user got it wrong */
-	((ADCConversionGroup *)ADCD1.grpp)->num_channels = 0;
-	for(i=1; i < 0x100; i <<= 1) {
-		if ((ADCD1.grpp->channelselects & i))
-			((ADCConversionGroup *)ADCD1.grpp)->num_channels++;
-	}
-
-	/* Set the channels */
-	ADCReg1->ADC_CHER = ADCD1.grpp->channelselects;
-
-	/* Set up the DMA */
-	ADCReg1->ADC_RPR = (uint32_t)ADCD1.samples;
-	if (ADCD1.depth <= 1 || !ADCD1.grpp->circular) {
-		ADCReg1->ADC_RCR = ADCD1.depth * ADCD1.grpp->num_channels;
-		ADCReg1->ADC_RNPR = 0;
-		ADCReg1->ADC_RNCR = 0;
-	} else {
-		ADCReg1->ADC_RCR = ADCD1.depth/2 * ADCD1.grpp->num_channels;
-		ADCReg1->ADC_RNPR = (uint32_t)(ADCD1.samples + (ADCD1.depth/2 * ADCD1.grpp->num_channels));
-		ADCReg1->ADC_RNCR = (ADCD1.depth - ADCD1.depth/2) * ADCD1.grpp->num_channels;
-	}
-	ADCReg1->ADC_PTCR = AT91C_PDC_RXTEN;
-
-	/* Set up interrupts */
-	ADCReg1->ADC_IER = AT91C_ADC_GOVRE | AT91C_ADC_ENDRX | AT91C_ADC_RXBUFF;
-
-	/* Set the trigger */
-	switch(ADCD1.grpp->trigger & ~ADC_TRIGGER_SOFTWARE) {
-	case ADC_TRIGGER_TIMER:
-		// Set up the timer if ADCD1.grpp->frequency != 0
-		if (ADCD1.grpp->frequency) {
-			/* Turn on Timer in the power management controller */
-			AT91C_BASE_PMC->PMC_PCER = (1 << AT91_ADC1_TIMERID);
-
-		    /* Disable the clock and the interrupts */
-			ADCTimer1->TC_CCR = AT91C_TC_CLKDIS;
-			ADCTimer1->TC_IDR = 0xFFFFFFFF;
-
-		    /* Set the Mode of the Timer Counter and calculate the period */
-			i = (MCK/2)/ADCD1.grpp->frequency;
-			if (i < (0x10000<<0)) {
-				ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
-				                        AT91C_TC_WAVE  | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV1_CLOCK);
-			} else if (i < (0x10000<<2)) {
-				i >>= 2;
-				ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
-				                        AT91C_TC_WAVE  | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV2_CLOCK);
-			} else if (i < (0x10000<<4)) {
-				i >>= 4;
-				ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
-				                        AT91C_TC_WAVE  | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV3_CLOCK);
-			} else if (i < (0x10000<<6)) {
-				i >>= 6;
-				ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
-				                        AT91C_TC_WAVE  | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV4_CLOCK);
-			} else {
-				i >>= 9;
-				ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
-				                        AT91C_TC_WAVE  | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV5_CLOCK);
-			}
-
-		    /* RC is the period, RC-RA is the pulse width (in this case = 1) */
-			ADCTimer1->TC_RC = i;
-			ADCTimer1->TC_RA = i - 1;
-
-			/* Start the timer counter */
-			ADCTimer1->TC_CCR = (AT91C_TC_CLKEN |AT91C_TC_SWTRG);
-		}
-
-		ADCReg1->ADC_MR = AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_EN | AT91_ADC1_TIMERMODE;
-		break;
-
-	case ADC_TRIGGER_EXTERNAL:
-		/* Make sure the ADTRG pin is set as an input - assume pull-ups etc have already been set */
-		#if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) || (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512)
-			AT91C_BASE_PIOA->PIO_ODR	= AT91C_PA8_ADTRG;
-		#elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || (SAM7_PLATFORM == SAM7X512)
-			AT91C_BASE_PIOB->PIO_ODR	= AT91C_PB18_ADTRG;
-		#endif
-    	ADCReg1->ADC_MR = AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_EN | AT91C_ADC_TRGSEL_EXT;
-    	break;
-
-	default:
-    	ADCReg1->ADC_MR = AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_DIS;
-    	break;
-	}
-
-	/* Manually start a conversion if we need to */
-	if (ADCD1.grpp->trigger & ADC_TRIGGER_SOFTWARE)
-    	ADCReg1->ADC_CR = AT91C_ADC_START;
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-	(void) adcp;
-	adc_stop();
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/adc_lld.h b/os/hal/platforms/AT91SAM7/adc_lld.h
deleted file mode 100644
index e27931819..000000000
--- a/os/hal/platforms/AT91SAM7/adc_lld.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   This file has been contributed by:
-		Andrew Hannam aka inmarket.
-*/
-/**
- * @file    AT91SAM7/adc_lld.h
- * @brief   AT91SAM7 ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Trigger Sources
- * @{
- */
-#define ADC_TRIGGER_SOFTWARE	0x8000   				/**< @brief Software Triggering - Can be combined with another value */
-#define ADC_TRIGGER_TIMER		0x0001					/**< @brief TIO Timer Counter Channel  */
-#define ADC_TRIGGER_EXTERNAL	0x0002					/**< @brief External Trigger  */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define ADC_USE_ADC1                  TRUE
-#endif
-
-/**
- * @brief   ADC1 Timer to use when a periodic conversion is requested.
- * @details Should be set to 0..2
- * @note    The default is 0
- */
-#if !defined(AT91_ADC1_TIMER) || defined(__DOXYGEN__)
-#define AT91_ADC1_TIMER		0
-#endif
-
-/**
- * @brief   ADC1 Resolution.
- * @details Either 8 or 10 bits
- * @note    The default is 10 bits.
- */
-#if !defined(AT91_ADC1_RESOLUTION) || defined(__DOXYGEN__)
-#define AT91_ADC1_RESOLUTION	10
-#endif
-
-/**
- * @brief	ADC1 Clock
- * @details	Maximum is 5MHz for 10bit or 8MHz for 8bit
- * @note	The default is calculated from AT91_ADC1_RESOLUTION to give the fastest possible ADCClock
- */
-#if !defined(AT91_ADC1_CLOCK) || defined(__DOXYGEN__)
-	#if AT91_ADC1_RESOLUTION == 8
-		#define AT91_ADC1_CLOCK	8000000
-	#else
-		#define AT91_ADC1_CLOCK	5000000
-	#endif
-#endif
-
-/**
- * @brief	ADC1 Sample and Hold Time
- * @details	SHTM = RoundUp(ADCClock * SampleHoldTime). Range = RoundUp(ADCClock / 1,666,666) to 15
- * @note	Default corresponds to the minimum sample and hold time (600nS from the datasheet)
- * @note	Increasing the Sample Hold Time increases the ADC input impedance
- */
-#if !defined(AT91_ADC1_SHTM) || defined(__DOXYGEN__)
-	#define AT91_ADC1_SHTM	0
-#endif
-#if AT91_ADC1_SHTM < ((AT91_ADC1_CLOCK+1666665)/1666666)
-	#undef AT91_ADC1_SHTM
-	#define AT91_ADC1_SHTM	((AT91_ADC1_CLOCK+1666665)/1666666)
-#endif
-#if AT91_ADC1_SHTM > 15
-	#undef AT91_ADC1_SHTM
-	#define AT91_ADC1_SHTM	15
-#endif
-
-/**
- * @brief   ADC interrupt priority level setting.
- */
-#if !defined(AT91_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define AT91_ADC_IRQ_PRIORITY              (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !defined(AT91_DMA_REQUIRED)
-#define AT91_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-#if AT91_ADC1_RESOLUTION == AT91C_ADC_LOWRES_8_BIT
-	typedef uint8_t adcsample_t;
-#else
-	typedef uint16_t adcsample_t;
-#endif
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_OVERFLOW = 0,                     /**< ADC overflow condition. Something is not working fast enough. */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    The use of this configuration structure requires knowledge of
- *          STM32 ADC cell registers interface, please refer to the STM32
- *          reference manual for details.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Select the ADC Channels to read.
-   * @details The number of bits at logic level one in this register must
-   *          be equal to the number in the @p num_channels field.
-   */
-  uint16_t                  channelselects;
-  /**
-   * @brief   Select how to trigger the conversion.
-   */
-  uint16_t                  trigger;
-  /**
-   * @brief   When in ADC_TRIGGER_TIMER trigger mode - what frequency?
-   */
-  uint32_t                  frequency;
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7A3.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7A3.h
deleted file mode 100644
index 5d609f1cf..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7A3.h
+++ /dev/null
@@ -1,3352 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  Copyright (c) 2006, Atmel Corporation
-//
-//  All rights reserved.
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions are met:
-//
-//  - Redistributions of source code must retain the above copyright notice,
-//  this list of conditions and the disclaimer below.
-//
-//  Atmel's name may not be used to endorse or promote products derived from
-//  this software without specific prior written permission.
-//
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7A3.h
-// Object              : AT91SAM7A3 definitions
-// Generated           : AT91 SW Application Group  07/07/2008 (16:10:41)
-//
-// CVS Reference       : /AT91SAM7A3.pl/1.30/Wed Aug 30 14:08:29 2006//
-// CVS Reference       : /SYS_SAM7A3.pl/1.7/Thu Feb  3 17:24:14 2005//
-// CVS Reference       : /MC_SAM7A3.pl/1.3/Fri Sep 23 12:47:15 2005//
-// CVS Reference       : /PMC_SAM7A3.pl/1.2/Tue Feb  8 14:00:18 2005//
-// CVS Reference       : /RSTC_SAM7A3.pl/1.2/Wed Jul 13 15:25:16 2005//
-// CVS Reference       : /SHDWC_SAM7A3.pl/1.1/Thu Feb  3 17:23:24 2005//
-// CVS Reference       : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006//
-// CVS Reference       : /PWM_SAM7A3.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference       : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
-// CVS Reference       : /MCI_6101A.pl/1.1/Tue Jul 13 06:33:59 2004//
-// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// CVS Reference       : /AES_6149A.pl/1.12/Wed Nov  2 14:17:53 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 13:30:33 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7A3_H
-#define AT91SAM7A3_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	//
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	//
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	//
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	//
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	//
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	//
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	//
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	//
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	//
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	//
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	//
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	//
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	//
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	//
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	//
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	//
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	//
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	//
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[1]; 	//
-	AT91_REG	 SHDWC_SHCR; 	// Shut Down Control Register
-	AT91_REG	 SHDWC_SHMR; 	// Shut Down Mode Register
-	AT91_REG	 SHDWC_SHSR; 	// Shut Down Status Register
-	AT91_REG	 Reserved27[1]; 	//
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved28[1]; 	//
-	AT91_REG	 SYS_GPBR0; 	// General Purpose Register 0
-	AT91_REG	 SYS_GPBR1; 	// General Purpose Register 1
-	AT91_REG	 Reserved29[106]; 	//
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved30[1]; 	//
-	AT91_REG	 MC_PUIA[16]; 	// MC Protection Unit Area
-	AT91_REG	 MC_PUP; 	// MC Protection Unit Peripherals
-	AT91_REG	 MC_PUER; 	// MC Protection Unit Enable Register
-	AT91_REG	 Reserved31[2]; 	//
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-#define SYS_GPBR0       (AT91_CAST(AT91_REG *) 	0x00000D50) // (SYS_GPBR0) General Purpose Register 0
-#define SYS_GPBR1       (AT91_CAST(AT91_REG *) 	0x00000D54) // (SYS_GPBR1) General Purpose Register 1
-
-#endif
-// -------- GPBR : (SYS Offset: 0xd50) GPBR General Purpose Register --------
-// -------- GPBR : (SYS Offset: 0xd54) GPBR General Purpose Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	//
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	//
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	//
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
-#define CKGR_PLLR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	//
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_GENERAL              (0x0 <<  8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Length
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Shut Down Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SHDWC {
-	AT91_REG	 SHDWC_SHCR; 	// Shut Down Control Register
-	AT91_REG	 SHDWC_SHMR; 	// Shut Down Mode Register
-	AT91_REG	 SHDWC_SHSR; 	// Shut Down Status Register
-} AT91S_SHDWC, *AT91PS_SHDWC;
-#else
-#define SHDWC_SHCR      (AT91_CAST(AT91_REG *) 	0x00000000) // (SHDWC_SHCR) Shut Down Control Register
-#define SHDWC_SHMR      (AT91_CAST(AT91_REG *) 	0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
-#define SHDWC_SHSR      (AT91_CAST(AT91_REG *) 	0x00000008) // (SHDWC_SHSR) Shut Down Status Register
-
-#endif
-// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
-#define AT91C_SHDWC_SHDW      (0x1 <<  0) // (SHDWC) Processor Reset
-#define AT91C_SHDWC_KEY       (0xFF << 24) // (SHDWC) Shut down KEY Password
-// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
-#define AT91C_SHDWC_WKMODE0   (0x3 <<  0) // (SHDWC) Wake Up 0 Mode Selection
-#define 	AT91C_SHDWC_WKMODE0_NONE                 (0x0) // (SHDWC) None. No detection is performed on the wake up input.
-#define 	AT91C_SHDWC_WKMODE0_HIGH                 (0x1) // (SHDWC) High Level.
-#define 	AT91C_SHDWC_WKMODE0_LOW                  (0x2) // (SHDWC) Low Level.
-#define 	AT91C_SHDWC_WKMODE0_ANYLEVEL             (0x3) // (SHDWC) Any level change.
-#define AT91C_SHDWC_CPTWK0    (0xF <<  4) // (SHDWC) Counter On Wake Up 0
-#define AT91C_SHDWC_WKMODE1   (0x3 <<  8) // (SHDWC) Wake Up 1 Mode Selection
-#define 	AT91C_SHDWC_WKMODE1_NONE                 (0x0 <<  8) // (SHDWC) None. No detection is performed on the wake up input.
-#define 	AT91C_SHDWC_WKMODE1_HIGH                 (0x1 <<  8) // (SHDWC) High Level.
-#define 	AT91C_SHDWC_WKMODE1_LOW                  (0x2 <<  8) // (SHDWC) Low Level.
-#define 	AT91C_SHDWC_WKMODE1_ANYLEVEL             (0x3 <<  8) // (SHDWC) Any level change.
-#define AT91C_SHDWC_CPTWK1    (0xF << 12) // (SHDWC) Counter On Wake Up 1
-#define AT91C_SHDWC_RTTWKEN   (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
-// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
-#define AT91C_SHDWC_WAKEUP0   (0x1 <<  0) // (SHDWC) Wake Up 0 Status
-#define AT91C_SHDWC_WAKEUP1   (0x1 <<  1) // (SHDWC) Wake Up 1 Status
-#define AT91C_SHDWC_FWKUP     (0x1 <<  2) // (SHDWC) Force Wake Up Status
-#define AT91C_SHDWC_RTTWK     (0x1 << 16) // (SHDWC) Real Time Timer wake Up
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 MC_PUIA[16]; 	// MC Protection Unit Area
-	AT91_REG	 MC_PUP; 	// MC Protection Unit Peripherals
-	AT91_REG	 MC_PUER; 	// MC Protection Unit Enable Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR         (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_PUIA         (AT91_CAST(AT91_REG *) 	0x00000010) // (MC_PUIA) MC Protection Unit Area
-#define MC_PUP          (AT91_CAST(AT91_REG *) 	0x00000050) // (MC_PUP) MC Protection Unit Peripherals
-#define MC_PUER         (AT91_CAST(AT91_REG *) 	0x00000054) // (MC_PUER) MC Protection Unit Enable Register
-#define MC_FMR          (AT91_CAST(AT91_REG *) 	0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR          (AT91_CAST(AT91_REG *) 	0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR          (AT91_CAST(AT91_REG *) 	0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_MPU          (0x1 <<  2) // (MC) Memory protection Unit Abort Status
-#define AT91C_MC_ABTSZ        (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
-#define AT91C_MC_PROT         (0x3 <<  0) // (MC) Protection
-#define 	AT91C_MC_PROT_PNAUNA               (0x0) // (MC) Privilege: No Access, User: No Access
-#define 	AT91C_MC_PROT_PRWUNA               (0x1) // (MC) Privilege: Read/Write, User: No Access
-#define 	AT91C_MC_PROT_PRWURO               (0x2) // (MC) Privilege: Read/Write, User: Read Only
-#define 	AT91C_MC_PROT_PRWURW               (0x3) // (MC) Privilege: Read/Write, User: Read/Write
-#define AT91C_MC_SIZE         (0xF <<  4) // (MC) Internal Area Size
-#define 	AT91C_MC_SIZE_1KB                  (0x0 <<  4) // (MC) Area size 1KByte
-#define 	AT91C_MC_SIZE_2KB                  (0x1 <<  4) // (MC) Area size 2KByte
-#define 	AT91C_MC_SIZE_4KB                  (0x2 <<  4) // (MC) Area size 4KByte
-#define 	AT91C_MC_SIZE_8KB                  (0x3 <<  4) // (MC) Area size 8KByte
-#define 	AT91C_MC_SIZE_16KB                 (0x4 <<  4) // (MC) Area size 16KByte
-#define 	AT91C_MC_SIZE_32KB                 (0x5 <<  4) // (MC) Area size 32KByte
-#define 	AT91C_MC_SIZE_64KB                 (0x6 <<  4) // (MC) Area size 64KByte
-#define 	AT91C_MC_SIZE_128KB                (0x7 <<  4) // (MC) Area size 128KByte
-#define 	AT91C_MC_SIZE_256KB                (0x8 <<  4) // (MC) Area size 256KByte
-#define 	AT91C_MC_SIZE_512KB                (0x9 <<  4) // (MC) Area size 512KByte
-#define 	AT91C_MC_SIZE_1MB                  (0xA <<  4) // (MC) Area size 1MByte
-#define 	AT91C_MC_SIZE_2MB                  (0xB <<  4) // (MC) Area size 2MByte
-#define 	AT91C_MC_SIZE_4MB                  (0xC <<  4) // (MC) Area size 4MByte
-#define 	AT91C_MC_SIZE_8MB                  (0xD <<  4) // (MC) Area size 8MByte
-#define 	AT91C_MC_SIZE_16MB                 (0xE <<  4) // (MC) Area size 16MByte
-#define 	AT91C_MC_SIZE_64MB                 (0xF <<  4) // (MC) Area size 64MByte
-#define AT91C_MC_BA           (0x3FFFF << 10) // (MC) Internal Area Base Address
-// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
-// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
-#define AT91C_MC_PUEB         (0x1 <<  0) // (MC) Protection Unit enable Bit
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_EOP          (0x1 <<  0) // (MC) End Of Programming Flag
-#define AT91C_MC_EOL          (0x1 <<  1) // (MC) End Of Lock/Unlock Flag
-#define AT91C_MC_LOCKE        (0x1 <<  2) // (MC) Lock Error Flag
-#define AT91C_MC_PROGE        (0x1 <<  3) // (MC) Programming Error Flag
-#define AT91C_MC_NEBP         (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          (0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         (0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_PAGEN        (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Status Register --------
-#define AT91C_MC_LOCKS0       (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-#else
-#define CAN_MMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (CAN_MMR) MailBox Mode Register
-#define CAN_MAM         (AT91_CAST(AT91_REG *) 	0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
-#define CAN_MID         (AT91_CAST(AT91_REG *) 	0x00000008) // (CAN_MID) MailBox ID Register
-#define CAN_MFID        (AT91_CAST(AT91_REG *) 	0x0000000C) // (CAN_MFID) MailBox Family ID Register
-#define CAN_MSR         (AT91_CAST(AT91_REG *) 	0x00000010) // (CAN_MSR) MailBox Status Register
-#define CAN_MDL         (AT91_CAST(AT91_REG *) 	0x00000014) // (CAN_MDL) MailBox Data Low Register
-#define CAN_MDH         (AT91_CAST(AT91_REG *) 	0x00000018) // (CAN_MDH) MailBox Data High Register
-#define CAN_MCR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (CAN_MCR) MailBox Control Register
-
-#endif
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK   (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB       (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP  (0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR        (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	//
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-#else
-#define CAN_MR          (AT91_CAST(AT91_REG *) 	0x00000000) // (CAN_MR) Mode Register
-#define CAN_IER         (AT91_CAST(AT91_REG *) 	0x00000004) // (CAN_IER) Interrupt Enable Register
-#define CAN_IDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (CAN_IDR) Interrupt Disable Register
-#define CAN_IMR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (CAN_IMR) Interrupt Mask Register
-#define CAN_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (CAN_SR) Status Register
-#define CAN_BR          (AT91_CAST(AT91_REG *) 	0x00000014) // (CAN_BR) Baudrate Register
-#define CAN_TIM         (AT91_CAST(AT91_REG *) 	0x00000018) // (CAN_TIM) Timer Register
-#define CAN_TIMESTP     (AT91_CAST(AT91_REG *) 	0x0000001C) // (CAN_TIMESTP) Time Stamp Register
-#define CAN_ECR         (AT91_CAST(AT91_REG *) 	0x00000020) // (CAN_ECR) Error Counter Register
-#define CAN_TCR         (AT91_CAST(AT91_REG *) 	0x00000024) // (CAN_TCR) Transfer Command Register
-#define CAN_ACR         (AT91_CAST(AT91_REG *) 	0x00000028) // (CAN_ACR) Abort Command Register
-#define CAN_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (CAN_VR) Version Register
-
-#endif
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN       (0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      (0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        (0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0         (0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         (0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         (0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         (0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         (0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         (0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         (0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         (0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         (0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         (0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY        (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2      (0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      (0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      (0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER       (0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC         (0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST      (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
-#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
-#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
-#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
-#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
-#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	//
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	//
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	//
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MCI {
-	AT91_REG	 MCI_CR; 	// MCI Control Register
-	AT91_REG	 MCI_MR; 	// MCI Mode Register
-	AT91_REG	 MCI_DTOR; 	// MCI Data Timeout Register
-	AT91_REG	 MCI_SDCR; 	// MCI SD Card Register
-	AT91_REG	 MCI_ARGR; 	// MCI Argument Register
-	AT91_REG	 MCI_CMDR; 	// MCI Command Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 MCI_RSPR[4]; 	// MCI Response Register
-	AT91_REG	 MCI_RDR; 	// MCI Receive Data Register
-	AT91_REG	 MCI_TDR; 	// MCI Transmit Data Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 MCI_SR; 	// MCI Status Register
-	AT91_REG	 MCI_IER; 	// MCI Interrupt Enable Register
-	AT91_REG	 MCI_IDR; 	// MCI Interrupt Disable Register
-	AT91_REG	 MCI_IMR; 	// MCI Interrupt Mask Register
-	AT91_REG	 Reserved2[44]; 	//
-	AT91_REG	 MCI_RPR; 	// Receive Pointer Register
-	AT91_REG	 MCI_RCR; 	// Receive Counter Register
-	AT91_REG	 MCI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 MCI_TCR; 	// Transmit Counter Register
-	AT91_REG	 MCI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 MCI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 MCI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 MCI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 MCI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 MCI_PTSR; 	// PDC Transfer Status Register
-} AT91S_MCI, *AT91PS_MCI;
-#else
-#define MCI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MCI_CR) MCI Control Register
-#define MCI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MCI_MR) MCI Mode Register
-#define MCI_DTOR        (AT91_CAST(AT91_REG *) 	0x00000008) // (MCI_DTOR) MCI Data Timeout Register
-#define MCI_SDCR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (MCI_SDCR) MCI SD Card Register
-#define MCI_ARGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (MCI_ARGR) MCI Argument Register
-#define MCI_CMDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (MCI_CMDR) MCI Command Register
-#define MCI_RSPR        (AT91_CAST(AT91_REG *) 	0x00000020) // (MCI_RSPR) MCI Response Register
-#define MCI_RDR         (AT91_CAST(AT91_REG *) 	0x00000030) // (MCI_RDR) MCI Receive Data Register
-#define MCI_TDR         (AT91_CAST(AT91_REG *) 	0x00000034) // (MCI_TDR) MCI Transmit Data Register
-#define MCI_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (MCI_SR) MCI Status Register
-#define MCI_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (MCI_IER) MCI Interrupt Enable Register
-#define MCI_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
-#define MCI_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
-
-#endif
-// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
-#define AT91C_MCI_MCIEN       (0x1 <<  0) // (MCI) Multimedia Interface Enable
-#define AT91C_MCI_MCIDIS      (0x1 <<  1) // (MCI) Multimedia Interface Disable
-#define AT91C_MCI_PWSEN       (0x1 <<  2) // (MCI) Power Save Mode Enable
-#define AT91C_MCI_PWSDIS      (0x1 <<  3) // (MCI) Power Save Mode Disable
-#define AT91C_MCI_SWRST       (0x1 <<  7) // (MCI) MCI Software reset
-// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
-#define AT91C_MCI_CLKDIV      (0xFF <<  0) // (MCI) Clock Divider
-#define AT91C_MCI_PWSDIV      (0x7 <<  8) // (MCI) Power Saving Divider
-#define AT91C_MCI_PDCPADV     (0x1 << 14) // (MCI) PDC Padding Value
-#define AT91C_MCI_PDCMODE     (0x1 << 15) // (MCI) PDC Oriented Mode
-#define AT91C_MCI_BLKLEN      (0xFFF << 18) // (MCI) Data Block Length
-// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
-#define AT91C_MCI_DTOCYC      (0xF <<  0) // (MCI) Data Timeout Cycle Number
-#define AT91C_MCI_DTOMUL      (0x7 <<  4) // (MCI) Data Timeout Multiplier
-#define 	AT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1
-#define 	AT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16
-#define 	AT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128
-#define 	AT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256
-#define 	AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024
-#define 	AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096
-#define 	AT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536
-#define 	AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576
-// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
-#define AT91C_MCI_SCDSEL      (0xF <<  0) // (MCI) SD Card Selector
-#define AT91C_MCI_SCDBUS      (0x1 <<  7) // (MCI) SD Card Bus Width
-// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
-#define AT91C_MCI_CMDNB       (0x3F <<  0) // (MCI) Command Number
-#define AT91C_MCI_RSPTYP      (0x3 <<  6) // (MCI) Response Type
-#define 	AT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response
-#define 	AT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response
-#define 	AT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response
-#define AT91C_MCI_SPCMD       (0x7 <<  8) // (MCI) Special CMD
-#define 	AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD
-#define 	AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD
-#define 	AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD
-#define 	AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command
-#define 	AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response
-#define AT91C_MCI_OPDCMD      (0x1 << 11) // (MCI) Open Drain Command
-#define AT91C_MCI_MAXLAT      (0x1 << 12) // (MCI) Maximum Latency for Command to respond
-#define AT91C_MCI_TRCMD       (0x3 << 16) // (MCI) Transfer CMD
-#define 	AT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer
-#define 	AT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer
-#define 	AT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer
-#define AT91C_MCI_TRDIR       (0x1 << 18) // (MCI) Transfer Direction
-#define AT91C_MCI_TRTYP       (0x3 << 19) // (MCI) Transfer Type
-#define 	AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) Block Transfer type
-#define 	AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) Multiple Block transfer type
-#define 	AT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) Stream transfer type
-// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
-#define AT91C_MCI_CMDRDY      (0x1 <<  0) // (MCI) Command Ready flag
-#define AT91C_MCI_RXRDY       (0x1 <<  1) // (MCI) RX Ready flag
-#define AT91C_MCI_TXRDY       (0x1 <<  2) // (MCI) TX Ready flag
-#define AT91C_MCI_BLKE        (0x1 <<  3) // (MCI) Data Block Transfer Ended flag
-#define AT91C_MCI_DTIP        (0x1 <<  4) // (MCI) Data Transfer in Progress flag
-#define AT91C_MCI_NOTBUSY     (0x1 <<  5) // (MCI) Data Line Not Busy flag
-#define AT91C_MCI_ENDRX       (0x1 <<  6) // (MCI) End of RX Buffer flag
-#define AT91C_MCI_ENDTX       (0x1 <<  7) // (MCI) End of TX Buffer flag
-#define AT91C_MCI_RXBUFF      (0x1 << 14) // (MCI) RX Buffer Full flag
-#define AT91C_MCI_TXBUFE      (0x1 << 15) // (MCI) TX Buffer Empty flag
-#define AT91C_MCI_RINDE       (0x1 << 16) // (MCI) Response Index Error flag
-#define AT91C_MCI_RDIRE       (0x1 << 17) // (MCI) Response Direction Error flag
-#define AT91C_MCI_RCRCE       (0x1 << 18) // (MCI) Response CRC Error flag
-#define AT91C_MCI_RENDE       (0x1 << 19) // (MCI) Response End Bit Error flag
-#define AT91C_MCI_RTOE        (0x1 << 20) // (MCI) Response Time-out Error flag
-#define AT91C_MCI_DCRCE       (0x1 << 21) // (MCI) data CRC Error flag
-#define AT91C_MCI_DTOE        (0x1 << 22) // (MCI) Data timeout Error flag
-#define AT91C_MCI_OVRE        (0x1 << 30) // (MCI) Overrun flag
-#define AT91C_MCI_UNRE        (0x1 << 31) // (MCI) Underrun flag
-// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
-// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
-// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	//
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	//
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         (0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP)
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	//
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved2[50]; 	//
-	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
-	AT91_REG	 TWI_RCR; 	// Receive Counter Register
-	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
-	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
-#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	//
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	//
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
-#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
-#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
-#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR        (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR      (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR      (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR      (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved        (AT91_CAST(AT91_REG *) 	0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	//
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_PWMC_CH	 PWMC_CH[8]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA        (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS        (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR         (AT91_CAST(AT91_REG *) 	0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3
-#define AT91C_PWMC_CHID4      (0x1 <<  4) // (PWMC) Channel ID 4
-#define AT91C_PWMC_CHID5      (0x1 <<  5) // (PWMC) Channel ID 5
-#define AT91C_PWMC_CHID6      (0x1 <<  6) // (PWMC) Channel ID 6
-#define AT91C_PWMC_CHID7      (0x1 <<  7) // (PWMC) Channel ID 7
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	//
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	//
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
-#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	//
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	//
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	//
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
-#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
-#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7A3
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-#define AT91C_SYS_GPBR1 (AT91_CAST(AT91_REG *) 	0xFFFFFD54) // (SYS) General Purpose Register 1
-#define AT91C_SYS_GPBR0 (AT91_CAST(AT91_REG *) 	0xFFFFFD50) // (SYS) General Purpose Register 0
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for SHDWC peripheral ==========
-#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 	0xFFFFFD18) // (SHDWC) Shut Down Status Register
-#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 	0xFFFFFD14) // (SHDWC) Shut Down Mode Register
-#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 	0xFFFFFD10) // (SHDWC) Shut Down Control Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_PUIA   (AT91_CAST(AT91_REG *) 	0xFFFFFF10) // (MC) MC Protection Unit Area
-#define AT91C_MC_FMR    (AT91_CAST(AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-#define AT91C_MC_RCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_ASR    (AT91_CAST(AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_PUP    (AT91_CAST(AT91_REG *) 	0xFFFFFF50) // (MC) MC Protection Unit Peripherals
-#define AT91C_MC_AASR   (AT91_CAST(AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_FSR    (AT91_CAST(AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_PUER   (AT91_CAST(AT91_REG *) 	0xFFFFFF54) // (MC) MC Protection Unit Enable Register
-// ========== Register definition for CAN0_MB0 peripheral ==========
-#define AT91C_CAN0_MB0_MDH (AT91_CAST(AT91_REG *) 	0xFFF80218) // (CAN0_MB0) MailBox Data High Register
-#define AT91C_CAN0_MB0_MDL (AT91_CAST(AT91_REG *) 	0xFFF80214) // (CAN0_MB0) MailBox Data Low Register
-#define AT91C_CAN0_MB0_MAM (AT91_CAST(AT91_REG *) 	0xFFF80204) // (CAN0_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB0_MCR (AT91_CAST(AT91_REG *) 	0xFFF8021C) // (CAN0_MB0) MailBox Control Register
-#define AT91C_CAN0_MB0_MMR (AT91_CAST(AT91_REG *) 	0xFFF80200) // (CAN0_MB0) MailBox Mode Register
-#define AT91C_CAN0_MB0_MID (AT91_CAST(AT91_REG *) 	0xFFF80208) // (CAN0_MB0) MailBox ID Register
-#define AT91C_CAN0_MB0_MFID (AT91_CAST(AT91_REG *) 	0xFFF8020C) // (CAN0_MB0) MailBox Family ID Register
-#define AT91C_CAN0_MB0_MSR (AT91_CAST(AT91_REG *) 	0xFFF80210) // (CAN0_MB0) MailBox Status Register
-// ========== Register definition for CAN0_MB1 peripheral ==========
-#define AT91C_CAN0_MB1_MSR (AT91_CAST(AT91_REG *) 	0xFFF80230) // (CAN0_MB1) MailBox Status Register
-#define AT91C_CAN0_MB1_MDH (AT91_CAST(AT91_REG *) 	0xFFF80238) // (CAN0_MB1) MailBox Data High Register
-#define AT91C_CAN0_MB1_MFID (AT91_CAST(AT91_REG *) 	0xFFF8022C) // (CAN0_MB1) MailBox Family ID Register
-#define AT91C_CAN0_MB1_MAM (AT91_CAST(AT91_REG *) 	0xFFF80224) // (CAN0_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB1_MDL (AT91_CAST(AT91_REG *) 	0xFFF80234) // (CAN0_MB1) MailBox Data Low Register
-#define AT91C_CAN0_MB1_MMR (AT91_CAST(AT91_REG *) 	0xFFF80220) // (CAN0_MB1) MailBox Mode Register
-#define AT91C_CAN0_MB1_MID (AT91_CAST(AT91_REG *) 	0xFFF80228) // (CAN0_MB1) MailBox ID Register
-#define AT91C_CAN0_MB1_MCR (AT91_CAST(AT91_REG *) 	0xFFF8023C) // (CAN0_MB1) MailBox Control Register
-// ========== Register definition for CAN0_MB2 peripheral ==========
-#define AT91C_CAN0_MB2_MCR (AT91_CAST(AT91_REG *) 	0xFFF8025C) // (CAN0_MB2) MailBox Control Register
-#define AT91C_CAN0_MB2_MFID (AT91_CAST(AT91_REG *) 	0xFFF8024C) // (CAN0_MB2) MailBox Family ID Register
-#define AT91C_CAN0_MB2_MID (AT91_CAST(AT91_REG *) 	0xFFF80248) // (CAN0_MB2) MailBox ID Register
-#define AT91C_CAN0_MB2_MMR (AT91_CAST(AT91_REG *) 	0xFFF80240) // (CAN0_MB2) MailBox Mode Register
-#define AT91C_CAN0_MB2_MAM (AT91_CAST(AT91_REG *) 	0xFFF80244) // (CAN0_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB2_MDH (AT91_CAST(AT91_REG *) 	0xFFF80258) // (CAN0_MB2) MailBox Data High Register
-#define AT91C_CAN0_MB2_MSR (AT91_CAST(AT91_REG *) 	0xFFF80250) // (CAN0_MB2) MailBox Status Register
-#define AT91C_CAN0_MB2_MDL (AT91_CAST(AT91_REG *) 	0xFFF80254) // (CAN0_MB2) MailBox Data Low Register
-// ========== Register definition for CAN0_MB3 peripheral ==========
-#define AT91C_CAN0_MB3_MMR (AT91_CAST(AT91_REG *) 	0xFFF80260) // (CAN0_MB3) MailBox Mode Register
-#define AT91C_CAN0_MB3_MCR (AT91_CAST(AT91_REG *) 	0xFFF8027C) // (CAN0_MB3) MailBox Control Register
-#define AT91C_CAN0_MB3_MDH (AT91_CAST(AT91_REG *) 	0xFFF80278) // (CAN0_MB3) MailBox Data High Register
-#define AT91C_CAN0_MB3_MDL (AT91_CAST(AT91_REG *) 	0xFFF80274) // (CAN0_MB3) MailBox Data Low Register
-#define AT91C_CAN0_MB3_MAM (AT91_CAST(AT91_REG *) 	0xFFF80264) // (CAN0_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB3_MSR (AT91_CAST(AT91_REG *) 	0xFFF80270) // (CAN0_MB3) MailBox Status Register
-#define AT91C_CAN0_MB3_MFID (AT91_CAST(AT91_REG *) 	0xFFF8026C) // (CAN0_MB3) MailBox Family ID Register
-#define AT91C_CAN0_MB3_MID (AT91_CAST(AT91_REG *) 	0xFFF80268) // (CAN0_MB3) MailBox ID Register
-// ========== Register definition for CAN0_MB4 peripheral ==========
-#define AT91C_CAN0_MB4_MFID (AT91_CAST(AT91_REG *) 	0xFFF8028C) // (CAN0_MB4) MailBox Family ID Register
-#define AT91C_CAN0_MB4_MID (AT91_CAST(AT91_REG *) 	0xFFF80288) // (CAN0_MB4) MailBox ID Register
-#define AT91C_CAN0_MB4_MDH (AT91_CAST(AT91_REG *) 	0xFFF80298) // (CAN0_MB4) MailBox Data High Register
-#define AT91C_CAN0_MB4_MDL (AT91_CAST(AT91_REG *) 	0xFFF80294) // (CAN0_MB4) MailBox Data Low Register
-#define AT91C_CAN0_MB4_MAM (AT91_CAST(AT91_REG *) 	0xFFF80284) // (CAN0_MB4) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB4_MCR (AT91_CAST(AT91_REG *) 	0xFFF8029C) // (CAN0_MB4) MailBox Control Register
-#define AT91C_CAN0_MB4_MSR (AT91_CAST(AT91_REG *) 	0xFFF80290) // (CAN0_MB4) MailBox Status Register
-#define AT91C_CAN0_MB4_MMR (AT91_CAST(AT91_REG *) 	0xFFF80280) // (CAN0_MB4) MailBox Mode Register
-// ========== Register definition for CAN0_MB5 peripheral ==========
-#define AT91C_CAN0_MB5_MSR (AT91_CAST(AT91_REG *) 	0xFFF802B0) // (CAN0_MB5) MailBox Status Register
-#define AT91C_CAN0_MB5_MFID (AT91_CAST(AT91_REG *) 	0xFFF802AC) // (CAN0_MB5) MailBox Family ID Register
-#define AT91C_CAN0_MB5_MAM (AT91_CAST(AT91_REG *) 	0xFFF802A4) // (CAN0_MB5) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB5_MDL (AT91_CAST(AT91_REG *) 	0xFFF802B4) // (CAN0_MB5) MailBox Data Low Register
-#define AT91C_CAN0_MB5_MDH (AT91_CAST(AT91_REG *) 	0xFFF802B8) // (CAN0_MB5) MailBox Data High Register
-#define AT91C_CAN0_MB5_MID (AT91_CAST(AT91_REG *) 	0xFFF802A8) // (CAN0_MB5) MailBox ID Register
-#define AT91C_CAN0_MB5_MMR (AT91_CAST(AT91_REG *) 	0xFFF802A0) // (CAN0_MB5) MailBox Mode Register
-#define AT91C_CAN0_MB5_MCR (AT91_CAST(AT91_REG *) 	0xFFF802BC) // (CAN0_MB5) MailBox Control Register
-// ========== Register definition for CAN0_MB6 peripheral ==========
-#define AT91C_CAN0_MB6_MAM (AT91_CAST(AT91_REG *) 	0xFFF802C4) // (CAN0_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB6_MID (AT91_CAST(AT91_REG *) 	0xFFF802C8) // (CAN0_MB6) MailBox ID Register
-#define AT91C_CAN0_MB6_MDL (AT91_CAST(AT91_REG *) 	0xFFF802D4) // (CAN0_MB6) MailBox Data Low Register
-#define AT91C_CAN0_MB6_MDH (AT91_CAST(AT91_REG *) 	0xFFF802D8) // (CAN0_MB6) MailBox Data High Register
-#define AT91C_CAN0_MB6_MCR (AT91_CAST(AT91_REG *) 	0xFFF802DC) // (CAN0_MB6) MailBox Control Register
-#define AT91C_CAN0_MB6_MMR (AT91_CAST(AT91_REG *) 	0xFFF802C0) // (CAN0_MB6) MailBox Mode Register
-#define AT91C_CAN0_MB6_MFID (AT91_CAST(AT91_REG *) 	0xFFF802CC) // (CAN0_MB6) MailBox Family ID Register
-#define AT91C_CAN0_MB6_MSR (AT91_CAST(AT91_REG *) 	0xFFF802D0) // (CAN0_MB6) MailBox Status Register
-// ========== Register definition for CAN0_MB7 peripheral ==========
-#define AT91C_CAN0_MB7_MSR (AT91_CAST(AT91_REG *) 	0xFFF802F0) // (CAN0_MB7) MailBox Status Register
-#define AT91C_CAN0_MB7_MMR (AT91_CAST(AT91_REG *) 	0xFFF802E0) // (CAN0_MB7) MailBox Mode Register
-#define AT91C_CAN0_MB7_MCR (AT91_CAST(AT91_REG *) 	0xFFF802FC) // (CAN0_MB7) MailBox Control Register
-#define AT91C_CAN0_MB7_MDL (AT91_CAST(AT91_REG *) 	0xFFF802F4) // (CAN0_MB7) MailBox Data Low Register
-#define AT91C_CAN0_MB7_MID (AT91_CAST(AT91_REG *) 	0xFFF802E8) // (CAN0_MB7) MailBox ID Register
-#define AT91C_CAN0_MB7_MDH (AT91_CAST(AT91_REG *) 	0xFFF802F8) // (CAN0_MB7) MailBox Data High Register
-#define AT91C_CAN0_MB7_MFID (AT91_CAST(AT91_REG *) 	0xFFF802EC) // (CAN0_MB7) MailBox Family ID Register
-#define AT91C_CAN0_MB7_MAM (AT91_CAST(AT91_REG *) 	0xFFF802E4) // (CAN0_MB7) MailBox Acceptance Mask Register
-// ========== Register definition for CAN0_MB8 peripheral ==========
-#define AT91C_CAN0_MB8_MAM (AT91_CAST(AT91_REG *) 	0xFFF80304) // (CAN0_MB8) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB8_MCR (AT91_CAST(AT91_REG *) 	0xFFF8031C) // (CAN0_MB8) MailBox Control Register
-#define AT91C_CAN0_MB8_MSR (AT91_CAST(AT91_REG *) 	0xFFF80310) // (CAN0_MB8) MailBox Status Register
-#define AT91C_CAN0_MB8_MID (AT91_CAST(AT91_REG *) 	0xFFF80308) // (CAN0_MB8) MailBox ID Register
-#define AT91C_CAN0_MB8_MDH (AT91_CAST(AT91_REG *) 	0xFFF80318) // (CAN0_MB8) MailBox Data High Register
-#define AT91C_CAN0_MB8_MFID (AT91_CAST(AT91_REG *) 	0xFFF8030C) // (CAN0_MB8) MailBox Family ID Register
-#define AT91C_CAN0_MB8_MMR (AT91_CAST(AT91_REG *) 	0xFFF80300) // (CAN0_MB8) MailBox Mode Register
-#define AT91C_CAN0_MB8_MDL (AT91_CAST(AT91_REG *) 	0xFFF80314) // (CAN0_MB8) MailBox Data Low Register
-// ========== Register definition for CAN0_MB9 peripheral ==========
-#define AT91C_CAN0_MB9_MMR (AT91_CAST(AT91_REG *) 	0xFFF80320) // (CAN0_MB9) MailBox Mode Register
-#define AT91C_CAN0_MB9_MDH (AT91_CAST(AT91_REG *) 	0xFFF80338) // (CAN0_MB9) MailBox Data High Register
-#define AT91C_CAN0_MB9_MSR (AT91_CAST(AT91_REG *) 	0xFFF80330) // (CAN0_MB9) MailBox Status Register
-#define AT91C_CAN0_MB9_MDL (AT91_CAST(AT91_REG *) 	0xFFF80334) // (CAN0_MB9) MailBox Data Low Register
-#define AT91C_CAN0_MB9_MID (AT91_CAST(AT91_REG *) 	0xFFF80328) // (CAN0_MB9) MailBox ID Register
-#define AT91C_CAN0_MB9_MFID (AT91_CAST(AT91_REG *) 	0xFFF8032C) // (CAN0_MB9) MailBox Family ID Register
-#define AT91C_CAN0_MB9_MCR (AT91_CAST(AT91_REG *) 	0xFFF8033C) // (CAN0_MB9) MailBox Control Register
-#define AT91C_CAN0_MB9_MAM (AT91_CAST(AT91_REG *) 	0xFFF80324) // (CAN0_MB9) MailBox Acceptance Mask Register
-// ========== Register definition for CAN0_MB10 peripheral ==========
-#define AT91C_CAN0_MB10_MCR (AT91_CAST(AT91_REG *) 	0xFFF8035C) // (CAN0_MB10) MailBox Control Register
-#define AT91C_CAN0_MB10_MID (AT91_CAST(AT91_REG *) 	0xFFF80348) // (CAN0_MB10) MailBox ID Register
-#define AT91C_CAN0_MB10_MAM (AT91_CAST(AT91_REG *) 	0xFFF80344) // (CAN0_MB10) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB10_MFID (AT91_CAST(AT91_REG *) 	0xFFF8034C) // (CAN0_MB10) MailBox Family ID Register
-#define AT91C_CAN0_MB10_MDL (AT91_CAST(AT91_REG *) 	0xFFF80354) // (CAN0_MB10) MailBox Data Low Register
-#define AT91C_CAN0_MB10_MMR (AT91_CAST(AT91_REG *) 	0xFFF80340) // (CAN0_MB10) MailBox Mode Register
-#define AT91C_CAN0_MB10_MDH (AT91_CAST(AT91_REG *) 	0xFFF80358) // (CAN0_MB10) MailBox Data High Register
-#define AT91C_CAN0_MB10_MSR (AT91_CAST(AT91_REG *) 	0xFFF80350) // (CAN0_MB10) MailBox Status Register
-// ========== Register definition for CAN0_MB11 peripheral ==========
-#define AT91C_CAN0_MB11_MCR (AT91_CAST(AT91_REG *) 	0xFFF8037C) // (CAN0_MB11) MailBox Control Register
-#define AT91C_CAN0_MB11_MFID (AT91_CAST(AT91_REG *) 	0xFFF8036C) // (CAN0_MB11) MailBox Family ID Register
-#define AT91C_CAN0_MB11_MDH (AT91_CAST(AT91_REG *) 	0xFFF80378) // (CAN0_MB11) MailBox Data High Register
-#define AT91C_CAN0_MB11_MAM (AT91_CAST(AT91_REG *) 	0xFFF80364) // (CAN0_MB11) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB11_MID (AT91_CAST(AT91_REG *) 	0xFFF80368) // (CAN0_MB11) MailBox ID Register
-#define AT91C_CAN0_MB11_MMR (AT91_CAST(AT91_REG *) 	0xFFF80360) // (CAN0_MB11) MailBox Mode Register
-#define AT91C_CAN0_MB11_MSR (AT91_CAST(AT91_REG *) 	0xFFF80370) // (CAN0_MB11) MailBox Status Register
-#define AT91C_CAN0_MB11_MDL (AT91_CAST(AT91_REG *) 	0xFFF80374) // (CAN0_MB11) MailBox Data Low Register
-// ========== Register definition for CAN0_MB12 peripheral ==========
-#define AT91C_CAN0_MB12_MCR (AT91_CAST(AT91_REG *) 	0xFFF8039C) // (CAN0_MB12) MailBox Control Register
-#define AT91C_CAN0_MB12_MID (AT91_CAST(AT91_REG *) 	0xFFF80388) // (CAN0_MB12) MailBox ID Register
-#define AT91C_CAN0_MB12_MDH (AT91_CAST(AT91_REG *) 	0xFFF80398) // (CAN0_MB12) MailBox Data High Register
-#define AT91C_CAN0_MB12_MAM (AT91_CAST(AT91_REG *) 	0xFFF80384) // (CAN0_MB12) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB12_MFID (AT91_CAST(AT91_REG *) 	0xFFF8038C) // (CAN0_MB12) MailBox Family ID Register
-#define AT91C_CAN0_MB12_MDL (AT91_CAST(AT91_REG *) 	0xFFF80394) // (CAN0_MB12) MailBox Data Low Register
-#define AT91C_CAN0_MB12_MMR (AT91_CAST(AT91_REG *) 	0xFFF80380) // (CAN0_MB12) MailBox Mode Register
-#define AT91C_CAN0_MB12_MSR (AT91_CAST(AT91_REG *) 	0xFFF80390) // (CAN0_MB12) MailBox Status Register
-// ========== Register definition for CAN0_MB13 peripheral ==========
-#define AT91C_CAN0_MB13_MCR (AT91_CAST(AT91_REG *) 	0xFFF803BC) // (CAN0_MB13) MailBox Control Register
-#define AT91C_CAN0_MB13_MDL (AT91_CAST(AT91_REG *) 	0xFFF803B4) // (CAN0_MB13) MailBox Data Low Register
-#define AT91C_CAN0_MB13_MAM (AT91_CAST(AT91_REG *) 	0xFFF803A4) // (CAN0_MB13) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB13_MFID (AT91_CAST(AT91_REG *) 	0xFFF803AC) // (CAN0_MB13) MailBox Family ID Register
-#define AT91C_CAN0_MB13_MDH (AT91_CAST(AT91_REG *) 	0xFFF803B8) // (CAN0_MB13) MailBox Data High Register
-#define AT91C_CAN0_MB13_MID (AT91_CAST(AT91_REG *) 	0xFFF803A8) // (CAN0_MB13) MailBox ID Register
-#define AT91C_CAN0_MB13_MSR (AT91_CAST(AT91_REG *) 	0xFFF803B0) // (CAN0_MB13) MailBox Status Register
-#define AT91C_CAN0_MB13_MMR (AT91_CAST(AT91_REG *) 	0xFFF803A0) // (CAN0_MB13) MailBox Mode Register
-// ========== Register definition for CAN0_MB14 peripheral ==========
-#define AT91C_CAN0_MB14_MSR (AT91_CAST(AT91_REG *) 	0xFFF803D0) // (CAN0_MB14) MailBox Status Register
-#define AT91C_CAN0_MB14_MMR (AT91_CAST(AT91_REG *) 	0xFFF803C0) // (CAN0_MB14) MailBox Mode Register
-#define AT91C_CAN0_MB14_MDL (AT91_CAST(AT91_REG *) 	0xFFF803D4) // (CAN0_MB14) MailBox Data Low Register
-#define AT91C_CAN0_MB14_MDH (AT91_CAST(AT91_REG *) 	0xFFF803D8) // (CAN0_MB14) MailBox Data High Register
-#define AT91C_CAN0_MB14_MID (AT91_CAST(AT91_REG *) 	0xFFF803C8) // (CAN0_MB14) MailBox ID Register
-#define AT91C_CAN0_MB14_MCR (AT91_CAST(AT91_REG *) 	0xFFF803DC) // (CAN0_MB14) MailBox Control Register
-#define AT91C_CAN0_MB14_MFID (AT91_CAST(AT91_REG *) 	0xFFF803CC) // (CAN0_MB14) MailBox Family ID Register
-#define AT91C_CAN0_MB14_MAM (AT91_CAST(AT91_REG *) 	0xFFF803C4) // (CAN0_MB14) MailBox Acceptance Mask Register
-// ========== Register definition for CAN0_MB15 peripheral ==========
-#define AT91C_CAN0_MB15_MDH (AT91_CAST(AT91_REG *) 	0xFFF803F8) // (CAN0_MB15) MailBox Data High Register
-#define AT91C_CAN0_MB15_MMR (AT91_CAST(AT91_REG *) 	0xFFF803E0) // (CAN0_MB15) MailBox Mode Register
-#define AT91C_CAN0_MB15_MCR (AT91_CAST(AT91_REG *) 	0xFFF803FC) // (CAN0_MB15) MailBox Control Register
-#define AT91C_CAN0_MB15_MAM (AT91_CAST(AT91_REG *) 	0xFFF803E4) // (CAN0_MB15) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB15_MID (AT91_CAST(AT91_REG *) 	0xFFF803E8) // (CAN0_MB15) MailBox ID Register
-#define AT91C_CAN0_MB15_MFID (AT91_CAST(AT91_REG *) 	0xFFF803EC) // (CAN0_MB15) MailBox Family ID Register
-#define AT91C_CAN0_MB15_MSR (AT91_CAST(AT91_REG *) 	0xFFF803F0) // (CAN0_MB15) MailBox Status Register
-#define AT91C_CAN0_MB15_MDL (AT91_CAST(AT91_REG *) 	0xFFF803F4) // (CAN0_MB15) MailBox Data Low Register
-// ========== Register definition for CAN0 peripheral ==========
-#define AT91C_CAN0_BR   (AT91_CAST(AT91_REG *) 	0xFFF80014) // (CAN0) Baudrate Register
-#define AT91C_CAN0_TIMESTP (AT91_CAST(AT91_REG *) 	0xFFF8001C) // (CAN0) Time Stamp Register
-#define AT91C_CAN0_IER  (AT91_CAST(AT91_REG *) 	0xFFF80004) // (CAN0) Interrupt Enable Register
-#define AT91C_CAN0_MR   (AT91_CAST(AT91_REG *) 	0xFFF80000) // (CAN0) Mode Register
-#define AT91C_CAN0_TCR  (AT91_CAST(AT91_REG *) 	0xFFF80024) // (CAN0) Transfer Command Register
-#define AT91C_CAN0_ACR  (AT91_CAST(AT91_REG *) 	0xFFF80028) // (CAN0) Abort Command Register
-#define AT91C_CAN0_IDR  (AT91_CAST(AT91_REG *) 	0xFFF80008) // (CAN0) Interrupt Disable Register
-#define AT91C_CAN0_IMR  (AT91_CAST(AT91_REG *) 	0xFFF8000C) // (CAN0) Interrupt Mask Register
-#define AT91C_CAN0_TIM  (AT91_CAST(AT91_REG *) 	0xFFF80018) // (CAN0) Timer Register
-#define AT91C_CAN0_VR   (AT91_CAST(AT91_REG *) 	0xFFF800FC) // (CAN0) Version Register
-#define AT91C_CAN0_ECR  (AT91_CAST(AT91_REG *) 	0xFFF80020) // (CAN0) Error Counter Register
-#define AT91C_CAN0_SR   (AT91_CAST(AT91_REG *) 	0xFFF80010) // (CAN0) Status Register
-// ========== Register definition for CAN1_MB0 peripheral ==========
-#define AT91C_CAN1_MB0_MFID (AT91_CAST(AT91_REG *) 	0xFFF8420C) // (CAN1_MB0) MailBox Family ID Register
-#define AT91C_CAN1_MB0_MDL (AT91_CAST(AT91_REG *) 	0xFFF84214) // (CAN1_MB0) MailBox Data Low Register
-#define AT91C_CAN1_MB0_MID (AT91_CAST(AT91_REG *) 	0xFFF84208) // (CAN1_MB0) MailBox ID Register
-#define AT91C_CAN1_MB0_MMR (AT91_CAST(AT91_REG *) 	0xFFF84200) // (CAN1_MB0) MailBox Mode Register
-#define AT91C_CAN1_MB0_MAM (AT91_CAST(AT91_REG *) 	0xFFF84204) // (CAN1_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB0_MSR (AT91_CAST(AT91_REG *) 	0xFFF84210) // (CAN1_MB0) MailBox Status Register
-#define AT91C_CAN1_MB0_MDH (AT91_CAST(AT91_REG *) 	0xFFF84218) // (CAN1_MB0) MailBox Data High Register
-#define AT91C_CAN1_MB0_MCR (AT91_CAST(AT91_REG *) 	0xFFF8421C) // (CAN1_MB0) MailBox Control Register
-// ========== Register definition for CAN1_MB1 peripheral ==========
-#define AT91C_CAN1_MB1_MFID (AT91_CAST(AT91_REG *) 	0xFFF8422C) // (CAN1_MB1) MailBox Family ID Register
-#define AT91C_CAN1_MB1_MSR (AT91_CAST(AT91_REG *) 	0xFFF84230) // (CAN1_MB1) MailBox Status Register
-#define AT91C_CAN1_MB1_MMR (AT91_CAST(AT91_REG *) 	0xFFF84220) // (CAN1_MB1) MailBox Mode Register
-#define AT91C_CAN1_MB1_MDH (AT91_CAST(AT91_REG *) 	0xFFF84238) // (CAN1_MB1) MailBox Data High Register
-#define AT91C_CAN1_MB1_MID (AT91_CAST(AT91_REG *) 	0xFFF84228) // (CAN1_MB1) MailBox ID Register
-#define AT91C_CAN1_MB1_MDL (AT91_CAST(AT91_REG *) 	0xFFF84234) // (CAN1_MB1) MailBox Data Low Register
-#define AT91C_CAN1_MB1_MCR (AT91_CAST(AT91_REG *) 	0xFFF8423C) // (CAN1_MB1) MailBox Control Register
-#define AT91C_CAN1_MB1_MAM (AT91_CAST(AT91_REG *) 	0xFFF84224) // (CAN1_MB1) MailBox Acceptance Mask Register
-// ========== Register definition for CAN1_MB2 peripheral ==========
-#define AT91C_CAN1_MB2_MSR (AT91_CAST(AT91_REG *) 	0xFFF84250) // (CAN1_MB2) MailBox Status Register
-#define AT91C_CAN1_MB2_MMR (AT91_CAST(AT91_REG *) 	0xFFF84240) // (CAN1_MB2) MailBox Mode Register
-#define AT91C_CAN1_MB2_MAM (AT91_CAST(AT91_REG *) 	0xFFF84244) // (CAN1_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB2_MID (AT91_CAST(AT91_REG *) 	0xFFF84248) // (CAN1_MB2) MailBox ID Register
-#define AT91C_CAN1_MB2_MFID (AT91_CAST(AT91_REG *) 	0xFFF8424C) // (CAN1_MB2) MailBox Family ID Register
-#define AT91C_CAN1_MB2_MDL (AT91_CAST(AT91_REG *) 	0xFFF84254) // (CAN1_MB2) MailBox Data Low Register
-#define AT91C_CAN1_MB2_MDH (AT91_CAST(AT91_REG *) 	0xFFF84258) // (CAN1_MB2) MailBox Data High Register
-#define AT91C_CAN1_MB2_MCR (AT91_CAST(AT91_REG *) 	0xFFF8425C) // (CAN1_MB2) MailBox Control Register
-// ========== Register definition for CAN1_MB3 peripheral ==========
-#define AT91C_CAN1_MB3_MCR (AT91_CAST(AT91_REG *) 	0xFFF8427C) // (CAN1_MB3) MailBox Control Register
-#define AT91C_CAN1_MB3_MDH (AT91_CAST(AT91_REG *) 	0xFFF84278) // (CAN1_MB3) MailBox Data High Register
-#define AT91C_CAN1_MB3_MAM (AT91_CAST(AT91_REG *) 	0xFFF84264) // (CAN1_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB3_MDL (AT91_CAST(AT91_REG *) 	0xFFF84274) // (CAN1_MB3) MailBox Data Low Register
-#define AT91C_CAN1_MB3_MMR (AT91_CAST(AT91_REG *) 	0xFFF84260) // (CAN1_MB3) MailBox Mode Register
-#define AT91C_CAN1_MB3_MSR (AT91_CAST(AT91_REG *) 	0xFFF84270) // (CAN1_MB3) MailBox Status Register
-#define AT91C_CAN1_MB3_MFID (AT91_CAST(AT91_REG *) 	0xFFF8426C) // (CAN1_MB3) MailBox Family ID Register
-#define AT91C_CAN1_MB3_MID (AT91_CAST(AT91_REG *) 	0xFFF84268) // (CAN1_MB3) MailBox ID Register
-// ========== Register definition for CAN1_MB4 peripheral ==========
-#define AT91C_CAN1_MB4_MCR (AT91_CAST(AT91_REG *) 	0xFFF8429C) // (CAN1_MB4) MailBox Control Register
-#define AT91C_CAN1_MB4_MDH (AT91_CAST(AT91_REG *) 	0xFFF84298) // (CAN1_MB4) MailBox Data High Register
-#define AT91C_CAN1_MB4_MID (AT91_CAST(AT91_REG *) 	0xFFF84288) // (CAN1_MB4) MailBox ID Register
-#define AT91C_CAN1_MB4_MDL (AT91_CAST(AT91_REG *) 	0xFFF84294) // (CAN1_MB4) MailBox Data Low Register
-#define AT91C_CAN1_MB4_MFID (AT91_CAST(AT91_REG *) 	0xFFF8428C) // (CAN1_MB4) MailBox Family ID Register
-#define AT91C_CAN1_MB4_MAM (AT91_CAST(AT91_REG *) 	0xFFF84284) // (CAN1_MB4) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB4_MSR (AT91_CAST(AT91_REG *) 	0xFFF84290) // (CAN1_MB4) MailBox Status Register
-#define AT91C_CAN1_MB4_MMR (AT91_CAST(AT91_REG *) 	0xFFF84280) // (CAN1_MB4) MailBox Mode Register
-// ========== Register definition for CAN1_MB5 peripheral ==========
-#define AT91C_CAN1_MB5_MCR (AT91_CAST(AT91_REG *) 	0xFFF842BC) // (CAN1_MB5) MailBox Control Register
-#define AT91C_CAN1_MB5_MSR (AT91_CAST(AT91_REG *) 	0xFFF842B0) // (CAN1_MB5) MailBox Status Register
-#define AT91C_CAN1_MB5_MMR (AT91_CAST(AT91_REG *) 	0xFFF842A0) // (CAN1_MB5) MailBox Mode Register
-#define AT91C_CAN1_MB5_MDL (AT91_CAST(AT91_REG *) 	0xFFF842B4) // (CAN1_MB5) MailBox Data Low Register
-#define AT91C_CAN1_MB5_MAM (AT91_CAST(AT91_REG *) 	0xFFF842A4) // (CAN1_MB5) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB5_MID (AT91_CAST(AT91_REG *) 	0xFFF842A8) // (CAN1_MB5) MailBox ID Register
-#define AT91C_CAN1_MB5_MDH (AT91_CAST(AT91_REG *) 	0xFFF842B8) // (CAN1_MB5) MailBox Data High Register
-#define AT91C_CAN1_MB5_MFID (AT91_CAST(AT91_REG *) 	0xFFF842AC) // (CAN1_MB5) MailBox Family ID Register
-// ========== Register definition for CAN1_MB6 peripheral ==========
-#define AT91C_CAN1_MB6_MDH (AT91_CAST(AT91_REG *) 	0xFFF842D8) // (CAN1_MB6) MailBox Data High Register
-#define AT91C_CAN1_MB6_MDL (AT91_CAST(AT91_REG *) 	0xFFF842D4) // (CAN1_MB6) MailBox Data Low Register
-#define AT91C_CAN1_MB6_MAM (AT91_CAST(AT91_REG *) 	0xFFF842C4) // (CAN1_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB6_MCR (AT91_CAST(AT91_REG *) 	0xFFF842DC) // (CAN1_MB6) MailBox Control Register
-#define AT91C_CAN1_MB6_MMR (AT91_CAST(AT91_REG *) 	0xFFF842C0) // (CAN1_MB6) MailBox Mode Register
-#define AT91C_CAN1_MB6_MID (AT91_CAST(AT91_REG *) 	0xFFF842C8) // (CAN1_MB6) MailBox ID Register
-#define AT91C_CAN1_MB6_MSR (AT91_CAST(AT91_REG *) 	0xFFF842D0) // (CAN1_MB6) MailBox Status Register
-#define AT91C_CAN1_MB6_MFID (AT91_CAST(AT91_REG *) 	0xFFF842CC) // (CAN1_MB6) MailBox Family ID Register
-// ========== Register definition for CAN1_MB7 peripheral ==========
-#define AT91C_CAN1_MB7_MDH (AT91_CAST(AT91_REG *) 	0xFFF842F8) // (CAN1_MB7) MailBox Data High Register
-#define AT91C_CAN1_MB7_MDL (AT91_CAST(AT91_REG *) 	0xFFF842F4) // (CAN1_MB7) MailBox Data Low Register
-#define AT91C_CAN1_MB7_MID (AT91_CAST(AT91_REG *) 	0xFFF842E8) // (CAN1_MB7) MailBox ID Register
-#define AT91C_CAN1_MB7_MSR (AT91_CAST(AT91_REG *) 	0xFFF842F0) // (CAN1_MB7) MailBox Status Register
-#define AT91C_CAN1_MB7_MFID (AT91_CAST(AT91_REG *) 	0xFFF842EC) // (CAN1_MB7) MailBox Family ID Register
-#define AT91C_CAN1_MB7_MAM (AT91_CAST(AT91_REG *) 	0xFFF842E4) // (CAN1_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB7_MMR (AT91_CAST(AT91_REG *) 	0xFFF842E0) // (CAN1_MB7) MailBox Mode Register
-#define AT91C_CAN1_MB7_MCR (AT91_CAST(AT91_REG *) 	0xFFF842FC) // (CAN1_MB7) MailBox Control Register
-// ========== Register definition for CAN1_MB8 peripheral ==========
-#define AT91C_CAN1_MB8_MCR (AT91_CAST(AT91_REG *) 	0xFFF8431C) // (CAN1_MB8) MailBox Control Register
-#define AT91C_CAN1_MB8_MFID (AT91_CAST(AT91_REG *) 	0xFFF8430C) // (CAN1_MB8) MailBox Family ID Register
-#define AT91C_CAN1_MB8_MSR (AT91_CAST(AT91_REG *) 	0xFFF84310) // (CAN1_MB8) MailBox Status Register
-#define AT91C_CAN1_MB8_MAM (AT91_CAST(AT91_REG *) 	0xFFF84304) // (CAN1_MB8) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB8_MDL (AT91_CAST(AT91_REG *) 	0xFFF84314) // (CAN1_MB8) MailBox Data Low Register
-#define AT91C_CAN1_MB8_MID (AT91_CAST(AT91_REG *) 	0xFFF84308) // (CAN1_MB8) MailBox ID Register
-#define AT91C_CAN1_MB8_MDH (AT91_CAST(AT91_REG *) 	0xFFF84318) // (CAN1_MB8) MailBox Data High Register
-#define AT91C_CAN1_MB8_MMR (AT91_CAST(AT91_REG *) 	0xFFF84300) // (CAN1_MB8) MailBox Mode Register
-// ========== Register definition for CAN1_MB9 peripheral ==========
-#define AT91C_CAN1_MB9_MDH (AT91_CAST(AT91_REG *) 	0xFFF84338) // (CAN1_MB9) MailBox Data High Register
-#define AT91C_CAN1_MB9_MDL (AT91_CAST(AT91_REG *) 	0xFFF84334) // (CAN1_MB9) MailBox Data Low Register
-#define AT91C_CAN1_MB9_MFID (AT91_CAST(AT91_REG *) 	0xFFF8432C) // (CAN1_MB9) MailBox Family ID Register
-#define AT91C_CAN1_MB9_MMR (AT91_CAST(AT91_REG *) 	0xFFF84320) // (CAN1_MB9) MailBox Mode Register
-#define AT91C_CAN1_MB9_MAM (AT91_CAST(AT91_REG *) 	0xFFF84324) // (CAN1_MB9) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB9_MID (AT91_CAST(AT91_REG *) 	0xFFF84328) // (CAN1_MB9) MailBox ID Register
-#define AT91C_CAN1_MB9_MCR (AT91_CAST(AT91_REG *) 	0xFFF8433C) // (CAN1_MB9) MailBox Control Register
-#define AT91C_CAN1_MB9_MSR (AT91_CAST(AT91_REG *) 	0xFFF84330) // (CAN1_MB9) MailBox Status Register
-// ========== Register definition for CAN1_MB10 peripheral ==========
-#define AT91C_CAN1_MB10_MFID (AT91_CAST(AT91_REG *) 	0xFFF8434C) // (CAN1_MB10) MailBox Family ID Register
-#define AT91C_CAN1_MB10_MSR (AT91_CAST(AT91_REG *) 	0xFFF84350) // (CAN1_MB10) MailBox Status Register
-#define AT91C_CAN1_MB10_MDL (AT91_CAST(AT91_REG *) 	0xFFF84354) // (CAN1_MB10) MailBox Data Low Register
-#define AT91C_CAN1_MB10_MMR (AT91_CAST(AT91_REG *) 	0xFFF84340) // (CAN1_MB10) MailBox Mode Register
-#define AT91C_CAN1_MB10_MCR (AT91_CAST(AT91_REG *) 	0xFFF8435C) // (CAN1_MB10) MailBox Control Register
-#define AT91C_CAN1_MB10_MAM (AT91_CAST(AT91_REG *) 	0xFFF84344) // (CAN1_MB10) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB10_MID (AT91_CAST(AT91_REG *) 	0xFFF84348) // (CAN1_MB10) MailBox ID Register
-#define AT91C_CAN1_MB10_MDH (AT91_CAST(AT91_REG *) 	0xFFF84358) // (CAN1_MB10) MailBox Data High Register
-// ========== Register definition for CAN1_MB11 peripheral ==========
-#define AT91C_CAN1_MB11_MMR (AT91_CAST(AT91_REG *) 	0xFFF84360) // (CAN1_MB11) MailBox Mode Register
-#define AT91C_CAN1_MB11_MDL (AT91_CAST(AT91_REG *) 	0xFFF84374) // (CAN1_MB11) MailBox Data Low Register
-#define AT91C_CAN1_MB11_MAM (AT91_CAST(AT91_REG *) 	0xFFF84364) // (CAN1_MB11) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB11_MID (AT91_CAST(AT91_REG *) 	0xFFF84368) // (CAN1_MB11) MailBox ID Register
-#define AT91C_CAN1_MB11_MCR (AT91_CAST(AT91_REG *) 	0xFFF8437C) // (CAN1_MB11) MailBox Control Register
-#define AT91C_CAN1_MB11_MDH (AT91_CAST(AT91_REG *) 	0xFFF84378) // (CAN1_MB11) MailBox Data High Register
-#define AT91C_CAN1_MB11_MSR (AT91_CAST(AT91_REG *) 	0xFFF84370) // (CAN1_MB11) MailBox Status Register
-#define AT91C_CAN1_MB11_MFID (AT91_CAST(AT91_REG *) 	0xFFF8436C) // (CAN1_MB11) MailBox Family ID Register
-// ========== Register definition for CAN1_MB12 peripheral ==========
-#define AT91C_CAN1_MB12_MFID (AT91_CAST(AT91_REG *) 	0xFFF8438C) // (CAN1_MB12) MailBox Family ID Register
-#define AT91C_CAN1_MB12_MAM (AT91_CAST(AT91_REG *) 	0xFFF84384) // (CAN1_MB12) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB12_MDH (AT91_CAST(AT91_REG *) 	0xFFF84398) // (CAN1_MB12) MailBox Data High Register
-#define AT91C_CAN1_MB12_MMR (AT91_CAST(AT91_REG *) 	0xFFF84380) // (CAN1_MB12) MailBox Mode Register
-#define AT91C_CAN1_MB12_MID (AT91_CAST(AT91_REG *) 	0xFFF84388) // (CAN1_MB12) MailBox ID Register
-#define AT91C_CAN1_MB12_MCR (AT91_CAST(AT91_REG *) 	0xFFF8439C) // (CAN1_MB12) MailBox Control Register
-#define AT91C_CAN1_MB12_MDL (AT91_CAST(AT91_REG *) 	0xFFF84394) // (CAN1_MB12) MailBox Data Low Register
-#define AT91C_CAN1_MB12_MSR (AT91_CAST(AT91_REG *) 	0xFFF84390) // (CAN1_MB12) MailBox Status Register
-// ========== Register definition for CAN1_MB13 peripheral ==========
-#define AT91C_CAN1_MB13_MDL (AT91_CAST(AT91_REG *) 	0xFFF843B4) // (CAN1_MB13) MailBox Data Low Register
-#define AT91C_CAN1_MB13_MSR (AT91_CAST(AT91_REG *) 	0xFFF843B0) // (CAN1_MB13) MailBox Status Register
-#define AT91C_CAN1_MB13_MFID (AT91_CAST(AT91_REG *) 	0xFFF843AC) // (CAN1_MB13) MailBox Family ID Register
-#define AT91C_CAN1_MB13_MAM (AT91_CAST(AT91_REG *) 	0xFFF843A4) // (CAN1_MB13) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB13_MMR (AT91_CAST(AT91_REG *) 	0xFFF843A0) // (CAN1_MB13) MailBox Mode Register
-#define AT91C_CAN1_MB13_MCR (AT91_CAST(AT91_REG *) 	0xFFF843BC) // (CAN1_MB13) MailBox Control Register
-#define AT91C_CAN1_MB13_MDH (AT91_CAST(AT91_REG *) 	0xFFF843B8) // (CAN1_MB13) MailBox Data High Register
-#define AT91C_CAN1_MB13_MID (AT91_CAST(AT91_REG *) 	0xFFF843A8) // (CAN1_MB13) MailBox ID Register
-// ========== Register definition for CAN1_MB14 peripheral ==========
-#define AT91C_CAN1_MB14_MCR (AT91_CAST(AT91_REG *) 	0xFFF843DC) // (CAN1_MB14) MailBox Control Register
-#define AT91C_CAN1_MB14_MID (AT91_CAST(AT91_REG *) 	0xFFF843C8) // (CAN1_MB14) MailBox ID Register
-#define AT91C_CAN1_MB14_MMR (AT91_CAST(AT91_REG *) 	0xFFF843C0) // (CAN1_MB14) MailBox Mode Register
-#define AT91C_CAN1_MB14_MDH (AT91_CAST(AT91_REG *) 	0xFFF843D8) // (CAN1_MB14) MailBox Data High Register
-#define AT91C_CAN1_MB14_MSR (AT91_CAST(AT91_REG *) 	0xFFF843D0) // (CAN1_MB14) MailBox Status Register
-#define AT91C_CAN1_MB14_MFID (AT91_CAST(AT91_REG *) 	0xFFF843CC) // (CAN1_MB14) MailBox Family ID Register
-#define AT91C_CAN1_MB14_MDL (AT91_CAST(AT91_REG *) 	0xFFF843D4) // (CAN1_MB14) MailBox Data Low Register
-#define AT91C_CAN1_MB14_MAM (AT91_CAST(AT91_REG *) 	0xFFF843C4) // (CAN1_MB14) MailBox Acceptance Mask Register
-// ========== Register definition for CAN1_MB15 peripheral ==========
-#define AT91C_CAN1_MB15_MSR (AT91_CAST(AT91_REG *) 	0xFFF843F0) // (CAN1_MB15) MailBox Status Register
-#define AT91C_CAN1_MB15_MDL (AT91_CAST(AT91_REG *) 	0xFFF843F4) // (CAN1_MB15) MailBox Data Low Register
-#define AT91C_CAN1_MB15_MDH (AT91_CAST(AT91_REG *) 	0xFFF843F8) // (CAN1_MB15) MailBox Data High Register
-#define AT91C_CAN1_MB15_MMR (AT91_CAST(AT91_REG *) 	0xFFF843E0) // (CAN1_MB15) MailBox Mode Register
-#define AT91C_CAN1_MB15_MAM (AT91_CAST(AT91_REG *) 	0xFFF843E4) // (CAN1_MB15) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB15_MFID (AT91_CAST(AT91_REG *) 	0xFFF843EC) // (CAN1_MB15) MailBox Family ID Register
-#define AT91C_CAN1_MB15_MCR (AT91_CAST(AT91_REG *) 	0xFFF843FC) // (CAN1_MB15) MailBox Control Register
-#define AT91C_CAN1_MB15_MID (AT91_CAST(AT91_REG *) 	0xFFF843E8) // (CAN1_MB15) MailBox ID Register
-// ========== Register definition for CAN1 peripheral ==========
-#define AT91C_CAN1_ECR  (AT91_CAST(AT91_REG *) 	0xFFF84020) // (CAN1) Error Counter Register
-#define AT91C_CAN1_BR   (AT91_CAST(AT91_REG *) 	0xFFF84014) // (CAN1) Baudrate Register
-#define AT91C_CAN1_IDR  (AT91_CAST(AT91_REG *) 	0xFFF84008) // (CAN1) Interrupt Disable Register
-#define AT91C_CAN1_ACR  (AT91_CAST(AT91_REG *) 	0xFFF84028) // (CAN1) Abort Command Register
-#define AT91C_CAN1_IMR  (AT91_CAST(AT91_REG *) 	0xFFF8400C) // (CAN1) Interrupt Mask Register
-#define AT91C_CAN1_TCR  (AT91_CAST(AT91_REG *) 	0xFFF84024) // (CAN1) Transfer Command Register
-#define AT91C_CAN1_SR   (AT91_CAST(AT91_REG *) 	0xFFF84010) // (CAN1) Status Register
-#define AT91C_CAN1_TIM  (AT91_CAST(AT91_REG *) 	0xFFF84018) // (CAN1) Timer Register
-#define AT91C_CAN1_VR   (AT91_CAST(AT91_REG *) 	0xFFF840FC) // (CAN1) Version Register
-#define AT91C_CAN1_MR   (AT91_CAST(AT91_REG *) 	0xFFF84000) // (CAN1) Mode Register
-#define AT91C_CAN1_IER  (AT91_CAST(AT91_REG *) 	0xFFF84004) // (CAN1) Interrupt Enable Register
-#define AT91C_CAN1_TIMESTP (AT91_CAST(AT91_REG *) 	0xFFF8401C) // (CAN1) Time Stamp Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB0 peripheral ==========
-#define AT91C_TCB0_BMR  (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB0) TC Block Mode Register
-#define AT91C_TCB0_BCR  (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB0) TC Block Control Register
-// ========== Register definition for TC3 peripheral ==========
-#define AT91C_TC3_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA402C) // (TC3) Interrupt Mask Register
-#define AT91C_TC3_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA4004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC3_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA4028) // (TC3) Interrupt Disable Register
-#define AT91C_TC3_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA4000) // (TC3) Channel Control Register
-#define AT91C_TC3_RA    (AT91_CAST(AT91_REG *) 	0xFFFA4014) // (TC3) Register A
-#define AT91C_TC3_RB    (AT91_CAST(AT91_REG *) 	0xFFFA4018) // (TC3) Register B
-#define AT91C_TC3_CV    (AT91_CAST(AT91_REG *) 	0xFFFA4010) // (TC3) Counter Value
-#define AT91C_TC3_SR    (AT91_CAST(AT91_REG *) 	0xFFFA4020) // (TC3) Status Register
-#define AT91C_TC3_IER   (AT91_CAST(AT91_REG *) 	0xFFFA4024) // (TC3) Interrupt Enable Register
-#define AT91C_TC3_RC    (AT91_CAST(AT91_REG *) 	0xFFFA401C) // (TC3) Register C
-// ========== Register definition for TC4 peripheral ==========
-#define AT91C_TC4_SR    (AT91_CAST(AT91_REG *) 	0xFFFA4060) // (TC4) Status Register
-#define AT91C_TC4_RA    (AT91_CAST(AT91_REG *) 	0xFFFA4054) // (TC4) Register A
-#define AT91C_TC4_CV    (AT91_CAST(AT91_REG *) 	0xFFFA4050) // (TC4) Counter Value
-#define AT91C_TC4_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA4044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC4_RB    (AT91_CAST(AT91_REG *) 	0xFFFA4058) // (TC4) Register B
-#define AT91C_TC4_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA4040) // (TC4) Channel Control Register
-#define AT91C_TC4_IER   (AT91_CAST(AT91_REG *) 	0xFFFA4064) // (TC4) Interrupt Enable Register
-#define AT91C_TC4_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA406C) // (TC4) Interrupt Mask Register
-#define AT91C_TC4_RC    (AT91_CAST(AT91_REG *) 	0xFFFA405C) // (TC4) Register C
-#define AT91C_TC4_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA4068) // (TC4) Interrupt Disable Register
-// ========== Register definition for TC5 peripheral ==========
-#define AT91C_TC5_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA4084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC5_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA40A8) // (TC5) Interrupt Disable Register
-#define AT91C_TC5_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA4080) // (TC5) Channel Control Register
-#define AT91C_TC5_RB    (AT91_CAST(AT91_REG *) 	0xFFFA4098) // (TC5) Register B
-#define AT91C_TC5_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA40AC) // (TC5) Interrupt Mask Register
-#define AT91C_TC5_CV    (AT91_CAST(AT91_REG *) 	0xFFFA4090) // (TC5) Counter Value
-#define AT91C_TC5_RC    (AT91_CAST(AT91_REG *) 	0xFFFA409C) // (TC5) Register C
-#define AT91C_TC5_SR    (AT91_CAST(AT91_REG *) 	0xFFFA40A0) // (TC5) Status Register
-#define AT91C_TC5_IER   (AT91_CAST(AT91_REG *) 	0xFFFA40A4) // (TC5) Interrupt Enable Register
-#define AT91C_TC5_RA    (AT91_CAST(AT91_REG *) 	0xFFFA4094) // (TC5) Register A
-// ========== Register definition for TCB1 peripheral ==========
-#define AT91C_TCB1_BMR  (AT91_CAST(AT91_REG *) 	0xFFFA40C4) // (TCB1) TC Block Mode Register
-#define AT91C_TCB1_BCR  (AT91_CAST(AT91_REG *) 	0xFFFA40C0) // (TCB1) TC Block Control Register
-// ========== Register definition for TC6 peripheral ==========
-#define AT91C_TC6_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA8028) // (TC6) Interrupt Disable Register
-#define AT91C_TC6_RA    (AT91_CAST(AT91_REG *) 	0xFFFA8014) // (TC6) Register A
-#define AT91C_TC6_IER   (AT91_CAST(AT91_REG *) 	0xFFFA8024) // (TC6) Interrupt Enable Register
-#define AT91C_TC6_RB    (AT91_CAST(AT91_REG *) 	0xFFFA8018) // (TC6) Register B
-#define AT91C_TC6_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA8004) // (TC6) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC6_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA8000) // (TC6) Channel Control Register
-#define AT91C_TC6_CV    (AT91_CAST(AT91_REG *) 	0xFFFA8010) // (TC6) Counter Value
-#define AT91C_TC6_RC    (AT91_CAST(AT91_REG *) 	0xFFFA801C) // (TC6) Register C
-#define AT91C_TC6_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA802C) // (TC6) Interrupt Mask Register
-#define AT91C_TC6_SR    (AT91_CAST(AT91_REG *) 	0xFFFA8020) // (TC6) Status Register
-// ========== Register definition for TC7 peripheral ==========
-#define AT91C_TC7_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA806C) // (TC7) Interrupt Mask Register
-#define AT91C_TC7_SR    (AT91_CAST(AT91_REG *) 	0xFFFA8060) // (TC7) Status Register
-#define AT91C_TC7_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA8068) // (TC7) Interrupt Disable Register
-#define AT91C_TC7_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA8044) // (TC7) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC7_CV    (AT91_CAST(AT91_REG *) 	0xFFFA8050) // (TC7) Counter Value
-#define AT91C_TC7_RA    (AT91_CAST(AT91_REG *) 	0xFFFA8054) // (TC7) Register A
-#define AT91C_TC7_RB    (AT91_CAST(AT91_REG *) 	0xFFFA8058) // (TC7) Register B
-#define AT91C_TC7_RC    (AT91_CAST(AT91_REG *) 	0xFFFA805C) // (TC7) Register C
-#define AT91C_TC7_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA8040) // (TC7) Channel Control Register
-#define AT91C_TC7_IER   (AT91_CAST(AT91_REG *) 	0xFFFA8064) // (TC7) Interrupt Enable Register
-// ========== Register definition for TC8 peripheral ==========
-#define AT91C_TC8_RA    (AT91_CAST(AT91_REG *) 	0xFFFA8094) // (TC8) Register A
-#define AT91C_TC8_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA80A8) // (TC8) Interrupt Disable Register
-#define AT91C_TC8_RC    (AT91_CAST(AT91_REG *) 	0xFFFA809C) // (TC8) Register C
-#define AT91C_TC8_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA8080) // (TC8) Channel Control Register
-#define AT91C_TC8_SR    (AT91_CAST(AT91_REG *) 	0xFFFA80A0) // (TC8) Status Register
-#define AT91C_TC8_RB    (AT91_CAST(AT91_REG *) 	0xFFFA8098) // (TC8) Register B
-#define AT91C_TC8_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA80AC) // (TC8) Interrupt Mask Register
-#define AT91C_TC8_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA8084) // (TC8) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC8_IER   (AT91_CAST(AT91_REG *) 	0xFFFA80A4) // (TC8) Interrupt Enable Register
-#define AT91C_TC8_CV    (AT91_CAST(AT91_REG *) 	0xFFFA8090) // (TC8) Counter Value
-// ========== Register definition for TCB2 peripheral ==========
-#define AT91C_TCB2_BMR  (AT91_CAST(AT91_REG *) 	0xFFFA80C4) // (TCB2) TC Block Mode Register
-#define AT91C_TCB2_BCR  (AT91_CAST(AT91_REG *) 	0xFFFA80C0) // (TCB2) TC Block Control Register
-// ========== Register definition for PDC_MCI peripheral ==========
-#define AT91C_MCI_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFAC124) // (PDC_MCI) PDC Transfer Status Register
-#define AT91C_MCI_RPR   (AT91_CAST(AT91_REG *) 	0xFFFAC100) // (PDC_MCI) Receive Pointer Register
-#define AT91C_MCI_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFAC114) // (PDC_MCI) Receive Next Counter Register
-#define AT91C_MCI_RCR   (AT91_CAST(AT91_REG *) 	0xFFFAC104) // (PDC_MCI) Receive Counter Register
-#define AT91C_MCI_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFAC120) // (PDC_MCI) PDC Transfer Control Register
-#define AT91C_MCI_TPR   (AT91_CAST(AT91_REG *) 	0xFFFAC108) // (PDC_MCI) Transmit Pointer Register
-#define AT91C_MCI_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFAC110) // (PDC_MCI) Receive Next Pointer Register
-#define AT91C_MCI_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFAC118) // (PDC_MCI) Transmit Next Pointer Register
-#define AT91C_MCI_TCR   (AT91_CAST(AT91_REG *) 	0xFFFAC10C) // (PDC_MCI) Transmit Counter Register
-#define AT91C_MCI_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFAC11C) // (PDC_MCI) Transmit Next Counter Register
-// ========== Register definition for MCI peripheral ==========
-#define AT91C_MCI_TDR   (AT91_CAST(AT91_REG *) 	0xFFFAC034) // (MCI) MCI Transmit Data Register
-#define AT91C_MCI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFAC048) // (MCI) MCI Interrupt Disable Register
-#define AT91C_MCI_SR    (AT91_CAST(AT91_REG *) 	0xFFFAC040) // (MCI) MCI Status Register
-#define AT91C_MCI_CMDR  (AT91_CAST(AT91_REG *) 	0xFFFAC014) // (MCI) MCI Command Register
-#define AT91C_MCI_DTOR  (AT91_CAST(AT91_REG *) 	0xFFFAC008) // (MCI) MCI Data Timeout Register
-#define AT91C_MCI_IER   (AT91_CAST(AT91_REG *) 	0xFFFAC044) // (MCI) MCI Interrupt Enable Register
-#define AT91C_MCI_ARGR  (AT91_CAST(AT91_REG *) 	0xFFFAC010) // (MCI) MCI Argument Register
-#define AT91C_MCI_SDCR  (AT91_CAST(AT91_REG *) 	0xFFFAC00C) // (MCI) MCI SD Card Register
-#define AT91C_MCI_RDR   (AT91_CAST(AT91_REG *) 	0xFFFAC030) // (MCI) MCI Receive Data Register
-#define AT91C_MCI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFAC04C) // (MCI) MCI Interrupt Mask Register
-#define AT91C_MCI_MR    (AT91_CAST(AT91_REG *) 	0xFFFAC004) // (MCI) MCI Mode Register
-#define AT91C_MCI_RSPR  (AT91_CAST(AT91_REG *) 	0xFFFAC020) // (MCI) MCI Response Register
-#define AT91C_MCI_CR    (AT91_CAST(AT91_REG *) 	0xFFFAC000) // (MCI) MCI Control Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   (AT91_CAST(AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US2 peripheral ==========
-#define AT91C_US2_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC8120) // (PDC_US2) PDC Transfer Control Register
-#define AT91C_US2_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC810C) // (PDC_US2) Transmit Counter Register
-#define AT91C_US2_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC8100) // (PDC_US2) Receive Pointer Register
-#define AT91C_US2_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC8108) // (PDC_US2) Transmit Pointer Register
-#define AT91C_US2_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC8124) // (PDC_US2) PDC Transfer Status Register
-#define AT91C_US2_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC8114) // (PDC_US2) Receive Next Counter Register
-#define AT91C_US2_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register
-#define AT91C_US2_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC8104) // (PDC_US2) Receive Counter Register
-#define AT91C_US2_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC8110) // (PDC_US2) Receive Next Pointer Register
-#define AT91C_US2_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC811C) // (PDC_US2) Transmit Next Counter Register
-// ========== Register definition for US2 peripheral ==========
-#define AT91C_US2_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC8018) // (US2) Receiver Holding Register
-#define AT91C_US2_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC8020) // (US2) Baud Rate Generator Register
-#define AT91C_US2_IF    (AT91_CAST(AT91_REG *) 	0xFFFC804C) // (US2) IRDA_FILTER Register
-#define AT91C_US2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC800C) // (US2) Interrupt Disable Register
-#define AT91C_US2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC8010) // (US2) Interrupt Mask Register
-#define AT91C_US2_CR    (AT91_CAST(AT91_REG *) 	0xFFFC8000) // (US2) Control Register
-#define AT91C_US2_IER   (AT91_CAST(AT91_REG *) 	0xFFFC8008) // (US2) Interrupt Enable Register
-#define AT91C_US2_NER   (AT91_CAST(AT91_REG *) 	0xFFFC8044) // (US2) Nb Errors Register
-#define AT91C_US2_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC8024) // (US2) Receiver Time-out Register
-#define AT91C_US2_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC8028) // (US2) Transmitter Time-guard Register
-#define AT91C_US2_MR    (AT91_CAST(AT91_REG *) 	0xFFFC8004) // (US2) Mode Register
-#define AT91C_US2_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC8014) // (US2) Channel Status Register
-#define AT91C_US2_THR   (AT91_CAST(AT91_REG *) 	0xFFFC801C) // (US2) Transmitter Holding Register
-#define AT91C_US2_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC8040) // (US2) FI_DI_Ratio Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH4 peripheral ==========
-#define AT91C_PWMC_CH4_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC294) // (PWMC_CH4) Reserved
-#define AT91C_PWMC_CH4_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC284) // (PWMC_CH4) Channel Duty Cycle Register
-#define AT91C_PWMC_CH4_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC290) // (PWMC_CH4) Channel Update Register
-#define AT91C_PWMC_CH4_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC28C) // (PWMC_CH4) Channel Counter Register
-#define AT91C_PWMC_CH4_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC280) // (PWMC_CH4) Channel Mode Register
-#define AT91C_PWMC_CH4_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC288) // (PWMC_CH4) Channel Period Register
-// ========== Register definition for PWMC_CH5 peripheral ==========
-#define AT91C_PWMC_CH5_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC2B4) // (PWMC_CH5) Reserved
-#define AT91C_PWMC_CH5_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC2AC) // (PWMC_CH5) Channel Counter Register
-#define AT91C_PWMC_CH5_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC2A4) // (PWMC_CH5) Channel Duty Cycle Register
-#define AT91C_PWMC_CH5_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC2A8) // (PWMC_CH5) Channel Period Register
-#define AT91C_PWMC_CH5_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC2A0) // (PWMC_CH5) Channel Mode Register
-#define AT91C_PWMC_CH5_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC2B0) // (PWMC_CH5) Channel Update Register
-// ========== Register definition for PWMC_CH6 peripheral ==========
-#define AT91C_PWMC_CH6_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC2CC) // (PWMC_CH6) Channel Counter Register
-#define AT91C_PWMC_CH6_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC2C0) // (PWMC_CH6) Channel Mode Register
-#define AT91C_PWMC_CH6_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC2C4) // (PWMC_CH6) Channel Duty Cycle Register
-#define AT91C_PWMC_CH6_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC2D4) // (PWMC_CH6) Reserved
-#define AT91C_PWMC_CH6_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC2C8) // (PWMC_CH6) Channel Period Register
-#define AT91C_PWMC_CH6_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC2D0) // (PWMC_CH6) Channel Update Register
-// ========== Register definition for PWMC_CH7 peripheral ==========
-#define AT91C_PWMC_CH7_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC2EC) // (PWMC_CH7) Channel Counter Register
-#define AT91C_PWMC_CH7_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC2E4) // (PWMC_CH7) Channel Duty Cycle Register
-#define AT91C_PWMC_CH7_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC2E8) // (PWMC_CH7) Channel Period Register
-#define AT91C_PWMC_CH7_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC2F4) // (PWMC_CH7) Reserved
-#define AT91C_PWMC_CH7_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC2F0) // (PWMC_CH7) Channel Update Register
-#define AT91C_PWMC_CH7_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC2E0) // (PWMC_CH7) Channel Mode Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   (AT91_CAST(AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for PDC_SSC0 peripheral ==========
-#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register
-#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register
-#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register
-#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register
-#define AT91C_SSC0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFD010C) // (PDC_SSC0) Transmit Counter Register
-#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register
-#define AT91C_SSC0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFD0104) // (PDC_SSC0) Receive Counter Register
-#define AT91C_SSC0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register
-#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register
-#define AT91C_SSC0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFD0100) // (PDC_SSC0) Receive Pointer Register
-// ========== Register definition for SSC0 peripheral ==========
-#define AT91C_SSC0_IER  (AT91_CAST(AT91_REG *) 	0xFFFD0044) // (SSC0) Interrupt Enable Register
-#define AT91C_SSC0_THR  (AT91_CAST(AT91_REG *) 	0xFFFD0024) // (SSC0) Transmit Holding Register
-#define AT91C_SSC0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFD0048) // (SSC0) Interrupt Disable Register
-#define AT91C_SSC0_CMR  (AT91_CAST(AT91_REG *) 	0xFFFD0004) // (SSC0) Clock Mode Register
-#define AT91C_SSC0_SR   (AT91_CAST(AT91_REG *) 	0xFFFD0040) // (SSC0) Status Register
-#define AT91C_SSC0_RHR  (AT91_CAST(AT91_REG *) 	0xFFFD0020) // (SSC0) Receive Holding Register
-#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 	0xFFFD001C) // (SSC0) Transmit Frame Mode Register
-#define AT91C_SSC0_CR   (AT91_CAST(AT91_REG *) 	0xFFFD0000) // (SSC0) Control Register
-#define AT91C_SSC0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFD004C) // (SSC0) Interrupt Mask Register
-#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 	0xFFFD0018) // (SSC0) Transmit Clock Mode Register
-#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 	0xFFFD0010) // (SSC0) Receive Clock ModeRegister
-#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 	0xFFFD0030) // (SSC0) Receive Sync Holding Register
-#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 	0xFFFD0034) // (SSC0) Transmit Sync Holding Register
-#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 	0xFFFD0014) // (SSC0) Receive Frame Mode Register
-// ========== Register definition for PDC_SSC1 peripheral ==========
-#define AT91C_SSC1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register
-#define AT91C_SSC1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_SSC1) Receive Pointer Register
-#define AT91C_SSC1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register
-#define AT91C_SSC1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register
-#define AT91C_SSC1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register
-#define AT91C_SSC1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_SSC1) Transmit Counter Register
-#define AT91C_SSC1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_SSC1) Receive Counter Register
-#define AT91C_SSC1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register
-#define AT91C_SSC1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register
-#define AT91C_SSC1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register
-// ========== Register definition for SSC1 peripheral ==========
-#define AT91C_SSC1_RHR  (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (SSC1) Receive Holding Register
-#define AT91C_SSC1_RSHR (AT91_CAST(AT91_REG *) 	0xFFFD4030) // (SSC1) Receive Sync Holding Register
-#define AT91C_SSC1_TFMR (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (SSC1) Transmit Frame Mode Register
-#define AT91C_SSC1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFD4048) // (SSC1) Interrupt Disable Register
-#define AT91C_SSC1_THR  (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (SSC1) Transmit Holding Register
-#define AT91C_SSC1_RCMR (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (SSC1) Receive Clock ModeRegister
-#define AT91C_SSC1_IER  (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (SSC1) Interrupt Enable Register
-#define AT91C_SSC1_TSHR (AT91_CAST(AT91_REG *) 	0xFFFD4034) // (SSC1) Transmit Sync Holding Register
-#define AT91C_SSC1_SR   (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (SSC1) Status Register
-#define AT91C_SSC1_CMR  (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (SSC1) Clock Mode Register
-#define AT91C_SSC1_TCMR (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (SSC1) Transmit Clock Mode Register
-#define AT91C_SSC1_CR   (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (SSC1) Control Register
-#define AT91C_SSC1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (SSC1) Interrupt Mask Register
-#define AT91C_SSC1_RFMR (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (SSC1) Receive Frame Mode Register
-// ========== Register definition for PDC_ADC0 peripheral ==========
-#define AT91C_ADC0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_ADC0) PDC Transfer Status Register
-#define AT91C_ADC0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_ADC0) PDC Transfer Control Register
-#define AT91C_ADC0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_ADC0) Transmit Next Pointer Register
-#define AT91C_ADC0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_ADC0) Transmit Next Counter Register
-#define AT91C_ADC0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_ADC0) Receive Next Pointer Register
-#define AT91C_ADC0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_ADC0) Receive Next Counter Register
-#define AT91C_ADC0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_ADC0) Receive Pointer Register
-#define AT91C_ADC0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_ADC0) Transmit Counter Register
-#define AT91C_ADC0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_ADC0) Transmit Pointer Register
-#define AT91C_ADC0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_ADC0) Receive Counter Register
-// ========== Register definition for ADC0 peripheral ==========
-#define AT91C_ADC0_CDR2 (AT91_CAST(AT91_REG *) 	0xFFFD8038) // (ADC0) ADC Channel Data Register 2
-#define AT91C_ADC0_CDR3 (AT91_CAST(AT91_REG *) 	0xFFFD803C) // (ADC0) ADC Channel Data Register 3
-#define AT91C_ADC0_CDR0 (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (ADC0) ADC Channel Data Register 0
-#define AT91C_ADC0_CDR5 (AT91_CAST(AT91_REG *) 	0xFFFD8044) // (ADC0) ADC Channel Data Register 5
-#define AT91C_ADC0_CHDR (AT91_CAST(AT91_REG *) 	0xFFFD8014) // (ADC0) ADC Channel Disable Register
-#define AT91C_ADC0_SR   (AT91_CAST(AT91_REG *) 	0xFFFD801C) // (ADC0) ADC Status Register
-#define AT91C_ADC0_CDR4 (AT91_CAST(AT91_REG *) 	0xFFFD8040) // (ADC0) ADC Channel Data Register 4
-#define AT91C_ADC0_CDR1 (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (ADC0) ADC Channel Data Register 1
-#define AT91C_ADC0_LCDR (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (ADC0) ADC Last Converted Data Register
-#define AT91C_ADC0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (ADC0) ADC Interrupt Disable Register
-#define AT91C_ADC0_CR   (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (ADC0) ADC Control Register
-#define AT91C_ADC0_CDR7 (AT91_CAST(AT91_REG *) 	0xFFFD804C) // (ADC0) ADC Channel Data Register 7
-#define AT91C_ADC0_CDR6 (AT91_CAST(AT91_REG *) 	0xFFFD8048) // (ADC0) ADC Channel Data Register 6
-#define AT91C_ADC0_IER  (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (ADC0) ADC Interrupt Enable Register
-#define AT91C_ADC0_CHER (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (ADC0) ADC Channel Enable Register
-#define AT91C_ADC0_CHSR (AT91_CAST(AT91_REG *) 	0xFFFD8018) // (ADC0) ADC Channel Status Register
-#define AT91C_ADC0_MR   (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (ADC0) ADC Mode Register
-#define AT91C_ADC0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (ADC0) ADC Interrupt Mask Register
-// ========== Register definition for PDC_ADC1 peripheral ==========
-#define AT91C_ADC1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFDC104) // (PDC_ADC1) Receive Counter Register
-#define AT91C_ADC1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFDC108) // (PDC_ADC1) Transmit Pointer Register
-#define AT91C_ADC1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFDC118) // (PDC_ADC1) Transmit Next Pointer Register
-#define AT91C_ADC1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFDC114) // (PDC_ADC1) Receive Next Counter Register
-#define AT91C_ADC1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFDC124) // (PDC_ADC1) PDC Transfer Status Register
-#define AT91C_ADC1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFDC120) // (PDC_ADC1) PDC Transfer Control Register
-#define AT91C_ADC1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFDC110) // (PDC_ADC1) Receive Next Pointer Register
-#define AT91C_ADC1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFDC11C) // (PDC_ADC1) Transmit Next Counter Register
-#define AT91C_ADC1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFDC10C) // (PDC_ADC1) Transmit Counter Register
-#define AT91C_ADC1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFDC100) // (PDC_ADC1) Receive Pointer Register
-// ========== Register definition for ADC1 peripheral ==========
-#define AT91C_ADC1_IER  (AT91_CAST(AT91_REG *) 	0xFFFDC024) // (ADC1) ADC Interrupt Enable Register
-#define AT91C_ADC1_CHSR (AT91_CAST(AT91_REG *) 	0xFFFDC018) // (ADC1) ADC Channel Status Register
-#define AT91C_ADC1_MR   (AT91_CAST(AT91_REG *) 	0xFFFDC004) // (ADC1) ADC Mode Register
-#define AT91C_ADC1_CR   (AT91_CAST(AT91_REG *) 	0xFFFDC000) // (ADC1) ADC Control Register
-#define AT91C_ADC1_LCDR (AT91_CAST(AT91_REG *) 	0xFFFDC020) // (ADC1) ADC Last Converted Data Register
-#define AT91C_ADC1_CHER (AT91_CAST(AT91_REG *) 	0xFFFDC010) // (ADC1) ADC Channel Enable Register
-#define AT91C_ADC1_CHDR (AT91_CAST(AT91_REG *) 	0xFFFDC014) // (ADC1) ADC Channel Disable Register
-#define AT91C_ADC1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFDC02C) // (ADC1) ADC Interrupt Mask Register
-#define AT91C_ADC1_CDR1 (AT91_CAST(AT91_REG *) 	0xFFFDC034) // (ADC1) ADC Channel Data Register 1
-#define AT91C_ADC1_CDR4 (AT91_CAST(AT91_REG *) 	0xFFFDC040) // (ADC1) ADC Channel Data Register 4
-#define AT91C_ADC1_CDR0 (AT91_CAST(AT91_REG *) 	0xFFFDC030) // (ADC1) ADC Channel Data Register 0
-#define AT91C_ADC1_CDR5 (AT91_CAST(AT91_REG *) 	0xFFFDC044) // (ADC1) ADC Channel Data Register 5
-#define AT91C_ADC1_CDR3 (AT91_CAST(AT91_REG *) 	0xFFFDC03C) // (ADC1) ADC Channel Data Register 3
-#define AT91C_ADC1_CDR6 (AT91_CAST(AT91_REG *) 	0xFFFDC048) // (ADC1) ADC Channel Data Register 6
-#define AT91C_ADC1_SR   (AT91_CAST(AT91_REG *) 	0xFFFDC01C) // (ADC1) ADC Status Register
-#define AT91C_ADC1_CDR2 (AT91_CAST(AT91_REG *) 	0xFFFDC038) // (ADC1) ADC Channel Data Register 2
-#define AT91C_ADC1_CDR7 (AT91_CAST(AT91_REG *) 	0xFFFDC04C) // (ADC1) ADC Channel Data Register 7
-#define AT91C_ADC1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFDC028) // (ADC1) ADC Interrupt Disable Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   (AT91_CAST(AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  (AT91_CAST(AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  (AT91_CAST(AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  (AT91_CAST(AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7A3
-// *****************************************************************************
-#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_TWD      (AT91C_PIO_PA0) //  TWI Two-wire Serial Data
-#define AT91C_PA0_ADTRG0   (AT91C_PIO_PA0) //  ADC0 External Trigger
-#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TWCK     (AT91C_PIO_PA1) //  TWI Two-wire Serial Clock
-#define AT91C_PA1_ADTRG1   (AT91C_PIO_PA1) //  ADC1 External Trigger
-#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TXD2     (AT91C_PIO_PA10) //  USART 2 Transmit Data
-#define AT91C_PA10_SPI1_SPCK (AT91C_PIO_PA10) //  SPI1 Serial Clock
-#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_SPI0_NPCS0 (AT91C_PIO_PA11) //  SPI0 Peripheral Chip Select 0
-#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS1 (AT91C_PIO_PA12) //  SPI0 Peripheral Chip Select 1
-#define AT91C_PA12_MCDA1    (AT91C_PIO_PA12) //  Multimedia Card A Data 1
-#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS2 (AT91C_PIO_PA13) //  SPI0 Peripheral Chip Select 2
-#define AT91C_PA13_MCDA2    (AT91C_PIO_PA13) //  Multimedia Card A Data 2
-#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS3 (AT91C_PIO_PA14) //  SPI0 Peripheral Chip Select 3
-#define AT91C_PA14_MCDA3    (AT91C_PIO_PA14) //  Multimedia Card A Data 3
-#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_MISO (AT91C_PIO_PA15) //  SPI0 Master In Slave
-#define AT91C_PA15_MCDA0    (AT91C_PIO_PA15) //  Multimedia Card A Data 0
-#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MOSI (AT91C_PIO_PA16) //  SPI0 Master Out Slave
-#define AT91C_PA16_MCCDA    (AT91C_PIO_PA16) //  Multimedia Card A Command
-#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_SPCK (AT91C_PIO_PA17) //  SPI0 Serial Clock
-#define AT91C_PA17_MCCK     (AT91C_PIO_PA17) //  Multimedia Card Clock
-#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_PWM0     (AT91C_PIO_PA18) //  PWMC Channel 0
-#define AT91C_PA18_PCK0     (AT91C_PIO_PA18) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_PWM1     (AT91C_PIO_PA19) //  PWMC Channel 1
-#define AT91C_PA19_PCK1     (AT91C_PIO_PA19) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_RXD0     (AT91C_PIO_PA2) //  USART 0 Receive Data
-#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_PWM2     (AT91C_PIO_PA20) //  PWMC Channel 2
-#define AT91C_PA20_PCK2     (AT91C_PIO_PA20) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_PWM3     (AT91C_PIO_PA21) //  PWMC Channel 3
-#define AT91C_PA21_PCK3     (AT91C_PIO_PA21) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_PWM4     (AT91C_PIO_PA22) //  PWMC Channel 4
-#define AT91C_PA22_IRQ0     (AT91C_PIO_PA22) //  Interrupt input 0
-#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_PWM5     (AT91C_PIO_PA23) //  PWMC Channel 5
-#define AT91C_PA23_IRQ1     (AT91C_PIO_PA23) //  Interrupt input 1
-#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_PWM6     (AT91C_PIO_PA24) //  PWMC Channel 6
-#define AT91C_PA24_TCLK4    (AT91C_PIO_PA24) //  Timer Counter 4 external Clock Input
-#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_PWM7     (AT91C_PIO_PA25) //  PWMC Channel 7
-#define AT91C_PA25_TCLK5    (AT91C_PIO_PA25) //  Timer Counter 5 external Clock Input
-#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_CANRX0   (AT91C_PIO_PA26) //  CAN Receive 0
-#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_CANTX0   (AT91C_PIO_PA27) //  CAN Transmit 0
-#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_CANRX1   (AT91C_PIO_PA28) //  CAN Receive 1
-#define AT91C_PA28_TCLK3    (AT91C_PIO_PA28) //  Timer Counter 3 external Clock Input
-#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_CANTX1   (AT91C_PIO_PA29) //  CAN Transmit 1
-#define AT91C_PA29_TCLK6    (AT91C_PIO_PA29) //  Timer Counter 6 external clock input
-#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_TXD0     (AT91C_PIO_PA3) //  USART 0 Transmit Data
-#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_DRXD     (AT91C_PIO_PA30) //  DBGU Debug Receive Data
-#define AT91C_PA30_TCLK7    (AT91C_PIO_PA30) //  Timer Counter 7 external clock input
-#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_DTXD     (AT91C_PIO_PA31) //  DBGU Debug Transmit Data
-#define AT91C_PA31_TCLK8    (AT91C_PIO_PA31) //  Timer Counter 8 external clock input
-#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_SCK0     (AT91C_PIO_PA4) //  USART 0 Serial Clock
-#define AT91C_PA4_SPI1_NPCS0 (AT91C_PIO_PA4) //  SPI1 Peripheral Chip Select 0
-#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RTS0     (AT91C_PIO_PA5) //  USART 0 Ready To Send
-#define AT91C_PA5_SPI1_NPCS1 (AT91C_PIO_PA5) //  SPI1 Peripheral Chip Select 1
-#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_CTS0     (AT91C_PIO_PA6) //  USART 0 Clear To Send
-#define AT91C_PA6_SPI1_NPCS2 (AT91C_PIO_PA6) //  SPI1 Peripheral Chip Select 2
-#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_RXD1     (AT91C_PIO_PA7) //  USART 1 Receive Data
-#define AT91C_PA7_SPI1_NPCS3 (AT91C_PIO_PA7) //  SPI1 Peripheral Chip Select 3
-#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_TXD1     (AT91C_PIO_PA8) //  USART 1 Transmit Data
-#define AT91C_PA8_SPI1_MISO (AT91C_PIO_PA8) //  SPI1 Master In Slave
-#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_RXD2     (AT91C_PIO_PA9) //  USART 2 Receive Data
-#define AT91C_PA9_SPI1_MOSI (AT91C_PIO_PA9) //  SPI1 Master Out Slave
-#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_IRQ2     (AT91C_PIO_PB0) //  Interrupt input 2
-#define AT91C_PB0_PWM5     (AT91C_PIO_PB0) //  PWMC Channel 5
-#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_IRQ3     (AT91C_PIO_PB1) //  Interrupt input 3
-#define AT91C_PB1_PWM6     (AT91C_PIO_PB1) //  PWMC Channel 6
-#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_TCLK1    (AT91C_PIO_PB10) //  Timer Counter 1 external clock input
-#define AT91C_PB10_RK1      (AT91C_PIO_PB10) //  SSC Receive Clock 1
-#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_TCLK2    (AT91C_PIO_PB11) //  Timer Counter 2 external clock input
-#define AT91C_PB11_RF1      (AT91C_PIO_PB11) //  SSC Receive Frame Sync 1
-#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_TIOA0    (AT91C_PIO_PB12) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB12_TD1      (AT91C_PIO_PB12) //  SSC Transmit Data 1
-#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_TIOB0    (AT91C_PIO_PB13) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB13_RD1      (AT91C_PIO_PB13) //  SSC Receive Data 1
-#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_TIOA1    (AT91C_PIO_PB14) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB14_PWM0     (AT91C_PIO_PB14) //  PWMC Channel 0
-#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_TIOB1    (AT91C_PIO_PB15) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB15_PWM1     (AT91C_PIO_PB15) //  PWMC Channel 1
-#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_TIOA2    (AT91C_PIO_PB16) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB16_PWM2     (AT91C_PIO_PB16) //  PWMC Channel 2
-#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_TIOB2    (AT91C_PIO_PB17) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB17_PWM3     (AT91C_PIO_PB17) //  PWMC Channel 3
-#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_TIOA3    (AT91C_PIO_PB18) //  Timer Counter 3 Multipurpose Timer I/O Pin A
-#define AT91C_PB18_PWM4     (AT91C_PIO_PB18) //  PWMC Channel 4
-#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_TIOB3    (AT91C_PIO_PB19) //  Timer Counter 3 Multipurpose Timer I/O Pin B
-#define AT91C_PB19_SPI1_NPCS1 (AT91C_PIO_PB19) //  SPI1 Peripheral Chip Select 1
-#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_TF0      (AT91C_PIO_PB2) //  SSC Transmit Frame Sync 0
-#define AT91C_PB2_PWM7     (AT91C_PIO_PB2) //  PWMC Channel 7
-#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_TIOA4    (AT91C_PIO_PB20) //  Timer Counter 4 Multipurpose Timer I/O Pin A
-#define AT91C_PB20_SPI1_NPCS2 (AT91C_PIO_PB20) //  SPI1 Peripheral Chip Select 2
-#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_TIOB4    (AT91C_PIO_PB21) //  Timer Counter 4 Multipurpose Timer I/O Pin B
-#define AT91C_PB21_SPI1_NPCS3 (AT91C_PIO_PB21) //  SPI1 Peripheral Chip Select 3
-#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_TIOA5    (AT91C_PIO_PB22) //  Timer Counter 5 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOB5    (AT91C_PIO_PB23) //  Timer Counter 5 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOA6    (AT91C_PIO_PB24) //  Timer Counter 6 Multipurpose Timer I/O Pin A
-#define AT91C_PB24_RTS1     (AT91C_PIO_PB24) //  USART 1 Ready To Send
-#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOB6    (AT91C_PIO_PB25) //  Timer Counter 6 Multipurpose Timer I/O Pin B
-#define AT91C_PB25_CTS1     (AT91C_PIO_PB25) //  USART 1 Clear To Send
-#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOA7    (AT91C_PIO_PB26) //  Timer Counter 7 Multipurpose Timer I/O Pin A
-#define AT91C_PB26_SCK1     (AT91C_PIO_PB26) //  USART 1 Serial Clock
-#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOB7    (AT91C_PIO_PB27) //  Timer Counter 7 Multipurpose Timer I/O Pin B
-#define AT91C_PB27_RTS2     (AT91C_PIO_PB27) //  USART 2 Ready To Send
-#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOA8    (AT91C_PIO_PB28) //  Timer Counter 8 Multipurpose Timer I/O Pin A
-#define AT91C_PB28_CTS2     (AT91C_PIO_PB28) //  USART 2 Clear To Send
-#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_TIOB8    (AT91C_PIO_PB29) //  Timer Counter 8 Multipurpose Timer I/O Pin B
-#define AT91C_PB29_SCK2     (AT91C_PIO_PB29) //  USART 2 Serial Clock
-#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_TK0      (AT91C_PIO_PB3) //  SSC Transmit Clock 0
-#define AT91C_PB3_PCK0     (AT91C_PIO_PB3) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_TD0      (AT91C_PIO_PB4) //  SSC Transmit data
-#define AT91C_PB4_PCK1     (AT91C_PIO_PB4) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_RD0      (AT91C_PIO_PB5) //  SSC Receive Data
-#define AT91C_PB5_PCK2     (AT91C_PIO_PB5) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_RK0      (AT91C_PIO_PB6) //  SSC Receive Clock
-#define AT91C_PB6_PCK3     (AT91C_PIO_PB6) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_RF0      (AT91C_PIO_PB7) //  SSC Receive Frame Sync 0
-#define AT91C_PB7_CANTX1   (AT91C_PIO_PB7) //  CAN Transmit 1
-#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_FIQ      (AT91C_PIO_PB8) //  AIC Fast Interrupt Input
-#define AT91C_PB8_TF1      (AT91C_PIO_PB8) //  SSC Transmit Frame Sync 1
-#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_TCLK0    (AT91C_PIO_PB9) //  Timer Counter 0 external clock input
-#define AT91C_PB9_TK1      (AT91C_PIO_PB9) //  SSC Transmit Clock 1
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7A3
-// *****************************************************************************
-#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ( 1) // System Peripheral
-#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
-#define AT91C_ID_CAN0   ( 4) // Control Area Network Controller 0
-#define AT91C_ID_CAN1   ( 5) // Control Area Network Controller 1
-#define AT91C_ID_US0    ( 6) // USART 0
-#define AT91C_ID_US1    ( 7) // USART 1
-#define AT91C_ID_US2    ( 8) // USART 2
-#define AT91C_ID_MCI    ( 9) // Multimedia Card Interface
-#define AT91C_ID_TWI    (10) // Two-Wire Interface
-#define AT91C_ID_SPI0   (11) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   (12) // Serial Peripheral Interface 1
-#define AT91C_ID_SSC0   (13) // Serial Synchronous Controller 0
-#define AT91C_ID_SSC1   (14) // Serial Synchronous Controller 1
-#define AT91C_ID_TC0    (15) // Timer Counter 0
-#define AT91C_ID_TC1    (16) // Timer Counter 1
-#define AT91C_ID_TC2    (17) // Timer Counter 2
-#define AT91C_ID_TC3    (18) // Timer Counter 3
-#define AT91C_ID_TC4    (19) // Timer Counter 4
-#define AT91C_ID_TC5    (20) // Timer Counter 5
-#define AT91C_ID_TC6    (21) // Timer Counter 6
-#define AT91C_ID_TC7    (22) // Timer Counter 7
-#define AT91C_ID_TC8    (23) // Timer Counter 8
-#define AT91C_ID_ADC0   (24) // Analog To Digital Converter 0
-#define AT91C_ID_ADC1   (25) // Analog To Digital Converter 1
-#define AT91C_ID_PWMC   (26) // Pulse Width Modulation Controller
-#define AT91C_ID_UDP    (27) // USB Device Port
-#define AT91C_ID_IRQ0   (28) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   (29) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ID_IRQ2   (30) // Advanced Interrupt Controller (IRQ2)
-#define AT91C_ID_IRQ3   (31) // Advanced Interrupt Controller (IRQ3)
-#define AT91C_ALL_INT   (0xFFFFFFFF) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7A3
-// *****************************************************************************
-#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_SHDWC     (AT91_CAST(AT91PS_SHDWC) 	0xFFFFFD10) // (SHDWC) Base Address
-#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_MC        (AT91_CAST(AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_CAN0_MB0  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80200) // (CAN0_MB0) Base Address
-#define AT91C_BASE_CAN0_MB1  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80220) // (CAN0_MB1) Base Address
-#define AT91C_BASE_CAN0_MB2  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80240) // (CAN0_MB2) Base Address
-#define AT91C_BASE_CAN0_MB3  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80260) // (CAN0_MB3) Base Address
-#define AT91C_BASE_CAN0_MB4  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80280) // (CAN0_MB4) Base Address
-#define AT91C_BASE_CAN0_MB5  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF802A0) // (CAN0_MB5) Base Address
-#define AT91C_BASE_CAN0_MB6  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF802C0) // (CAN0_MB6) Base Address
-#define AT91C_BASE_CAN0_MB7  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF802E0) // (CAN0_MB7) Base Address
-#define AT91C_BASE_CAN0_MB8  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80300) // (CAN0_MB8) Base Address
-#define AT91C_BASE_CAN0_MB9  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80320) // (CAN0_MB9) Base Address
-#define AT91C_BASE_CAN0_MB10 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80340) // (CAN0_MB10) Base Address
-#define AT91C_BASE_CAN0_MB11 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80360) // (CAN0_MB11) Base Address
-#define AT91C_BASE_CAN0_MB12 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF80380) // (CAN0_MB12) Base Address
-#define AT91C_BASE_CAN0_MB13 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF803A0) // (CAN0_MB13) Base Address
-#define AT91C_BASE_CAN0_MB14 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF803C0) // (CAN0_MB14) Base Address
-#define AT91C_BASE_CAN0_MB15 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF803E0) // (CAN0_MB15) Base Address
-#define AT91C_BASE_CAN0      (AT91_CAST(AT91PS_CAN) 	0xFFF80000) // (CAN0) Base Address
-#define AT91C_BASE_CAN1_MB0  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84200) // (CAN1_MB0) Base Address
-#define AT91C_BASE_CAN1_MB1  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84220) // (CAN1_MB1) Base Address
-#define AT91C_BASE_CAN1_MB2  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84240) // (CAN1_MB2) Base Address
-#define AT91C_BASE_CAN1_MB3  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84260) // (CAN1_MB3) Base Address
-#define AT91C_BASE_CAN1_MB4  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84280) // (CAN1_MB4) Base Address
-#define AT91C_BASE_CAN1_MB5  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF842A0) // (CAN1_MB5) Base Address
-#define AT91C_BASE_CAN1_MB6  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF842C0) // (CAN1_MB6) Base Address
-#define AT91C_BASE_CAN1_MB7  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF842E0) // (CAN1_MB7) Base Address
-#define AT91C_BASE_CAN1_MB8  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84300) // (CAN1_MB8) Base Address
-#define AT91C_BASE_CAN1_MB9  (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84320) // (CAN1_MB9) Base Address
-#define AT91C_BASE_CAN1_MB10 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84340) // (CAN1_MB10) Base Address
-#define AT91C_BASE_CAN1_MB11 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84360) // (CAN1_MB11) Base Address
-#define AT91C_BASE_CAN1_MB12 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF84380) // (CAN1_MB12) Base Address
-#define AT91C_BASE_CAN1_MB13 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF843A0) // (CAN1_MB13) Base Address
-#define AT91C_BASE_CAN1_MB14 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF843C0) // (CAN1_MB14) Base Address
-#define AT91C_BASE_CAN1_MB15 (AT91_CAST(AT91PS_CAN_MB) 	0xFFF843E0) // (CAN1_MB15) Base Address
-#define AT91C_BASE_CAN1      (AT91_CAST(AT91PS_CAN) 	0xFFF84000) // (CAN1) Base Address
-#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB0      (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB0) Base Address
-#define AT91C_BASE_TC3       (AT91_CAST(AT91PS_TC) 	0xFFFA4000) // (TC3) Base Address
-#define AT91C_BASE_TC4       (AT91_CAST(AT91PS_TC) 	0xFFFA4040) // (TC4) Base Address
-#define AT91C_BASE_TC5       (AT91_CAST(AT91PS_TC) 	0xFFFA4080) // (TC5) Base Address
-#define AT91C_BASE_TCB1      (AT91_CAST(AT91PS_TCB) 	0xFFFA4000) // (TCB1) Base Address
-#define AT91C_BASE_TC6       (AT91_CAST(AT91PS_TC) 	0xFFFA8000) // (TC6) Base Address
-#define AT91C_BASE_TC7       (AT91_CAST(AT91PS_TC) 	0xFFFA8040) // (TC7) Base Address
-#define AT91C_BASE_TC8       (AT91_CAST(AT91PS_TC) 	0xFFFA8080) // (TC8) Base Address
-#define AT91C_BASE_TCB2      (AT91_CAST(AT91PS_TCB) 	0xFFFA8000) // (TCB2) Base Address
-#define AT91C_BASE_PDC_MCI   (AT91_CAST(AT91PS_PDC) 	0xFFFAC100) // (PDC_MCI) Base Address
-#define AT91C_BASE_MCI       (AT91_CAST(AT91PS_MCI) 	0xFFFAC000) // (MCI) Base Address
-#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TWI       (AT91_CAST(AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US2   (AT91_CAST(AT91PS_PDC) 	0xFFFC8100) // (PDC_US2) Base Address
-#define AT91C_BASE_US2       (AT91_CAST(AT91PS_USART) 	0xFFFC8000) // (US2) Base Address
-#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH4  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC280) // (PWMC_CH4) Base Address
-#define AT91C_BASE_PWMC_CH5  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC2A0) // (PWMC_CH5) Base Address
-#define AT91C_BASE_PWMC_CH6  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC2C0) // (PWMC_CH6) Base Address
-#define AT91C_BASE_PWMC_CH7  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC2E0) // (PWMC_CH7) Base Address
-#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_PDC_SSC0  (AT91_CAST(AT91PS_PDC) 	0xFFFD0100) // (PDC_SSC0) Base Address
-#define AT91C_BASE_SSC0      (AT91_CAST(AT91PS_SSC) 	0xFFFD0000) // (SSC0) Base Address
-#define AT91C_BASE_PDC_SSC1  (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC1) Base Address
-#define AT91C_BASE_SSC1      (AT91_CAST(AT91PS_SSC) 	0xFFFD4000) // (SSC1) Base Address
-#define AT91C_BASE_PDC_ADC0  (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC0) Base Address
-#define AT91C_BASE_ADC0      (AT91_CAST(AT91PS_ADC) 	0xFFFD8000) // (ADC0) Base Address
-#define AT91C_BASE_PDC_ADC1  (AT91_CAST(AT91PS_PDC) 	0xFFFDC100) // (PDC_ADC1) Base Address
-#define AT91C_BASE_ADC1      (AT91_CAST(AT91PS_ADC) 	0xFFFDC000) // (ADC1) Base Address
-#define AT91C_BASE_PDC_SPI0  (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_SPI1  (AT91_CAST(AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      (AT91_CAST(AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7A3
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM	 (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 (0x00008000) // Internal SRAM size in byte (32 Kbytes)
-// IFLASH
-#define AT91C_IFLASH	 (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE	 (0x00040000) // Internal FLASH size in byte (256 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE	 (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE	 (4096) // Internal FLASH Lock Region Size: 4 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES	 (1024) // Internal FLASH Number of Pages: 1024 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (16) // Internal FLASH Number of Lock Bits: 16 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h
deleted file mode 100644
index 8fc3a9883..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h
+++ /dev/null
@@ -1,2229 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  Copyright (c) 2006, Atmel Corporation
-//
-//  All rights reserved.
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions are met:
-//
-//  - Redistributions of source code must retain the above copyright notice,
-//  this list of conditions and the disclaimer below.
-//
-//  Atmel's name may not be used to endorse or promote products derived from
-//  this software without specific prior written permission.
-//
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7S128.h
-// Object              : AT91SAM7S128 definitions
-// Generated           : AT91 SW Application Group  07/07/2008 (16:12:49)
-//
-// CVS Reference       : /AT91SAM7S128.pl/1.12/Wed Aug 30 14:08:34 2006//
-// CVS Reference       : /SYS_SAM7S.pl/1.2/Thu Feb  3 10:47:39 2005//
-// CVS Reference       : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006//
-// CVS Reference       : /PMC_SAM7S_USB.pl/1.4/Tue Feb  8 14:00:19 2005//
-// CVS Reference       : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference       : /UDP_4ept.pl/1.1/Thu Aug  3 12:26:00 2006//
-// CVS Reference       : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:40:38 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
-// CVS Reference       : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7S128_H
-#define AT91SAM7S128_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	//
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	//
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	//
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	//
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	//
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	//
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	//
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	//
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[469]; 	//
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved13[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved14[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved15[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved16[3]; 	//
-	AT91_REG	 PMC_PCKR[3]; 	// Programmable Clock Register
-	AT91_REG	 Reserved17[5]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved18[36]; 	//
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved19[5]; 	//
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved20[5]; 	//
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	//
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	//
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	//
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
-#define CKGR_PLLR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	//
-	AT91_REG	 PMC_PCKR[3]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[5]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN     (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	//
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR         (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR          (AT91_CAST(AT91_REG *) 	0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR          (AT91_CAST(AT91_REG *) 	0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR          (AT91_CAST(AT91_REG *) 	0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          (0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         (0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	//
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	//
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
-#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
-#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	//
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	//
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	//
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
-#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	//
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	//
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
-#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
-#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
-#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	//
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved2[50]; 	//
-	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
-	AT91_REG	 TWI_RCR; 	// Receive Counter Register
-	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
-	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
-#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
-#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
-#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
-#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
-#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
-#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	//
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	//
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	//
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR        (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR      (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR      (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR      (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved        (AT91_CAST(AT91_REG *) 	0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	//
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA        (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS        (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR         (AT91_CAST(AT91_REG *) 	0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 UDP_CSR[4]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[4]; 	//
-	AT91_REG	 UDP_FDR[4]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[5]; 	//
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP)
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S128
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   (AT91_CAST(AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    (AT91_CAST(AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   (AT91_CAST(AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    (AT91_CAST(AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    (AT91_CAST(AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TPR   (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_TCR   (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR   (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_SPI) Receive Counter Register
-#define AT91C_SPI_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_RPR   (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_IER   (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_SR    (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_CR    (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_MR    (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (SPI) Mode Register
-#define AT91C_SPI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_TDR   (AT91_CAST(AT91_REG *) 	0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_RDR   (AT91_CAST(AT91_REG *) 	0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CSR   (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (SPI) Chip Select Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   (AT91_CAST(AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   (AT91_CAST(AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7S128
-// *****************************************************************************
-#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0     (AT91C_PIO_PA0) //  PWM Channel 0
-#define AT91C_PA0_TIOA0    (AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1     (AT91C_PIO_PA1) //  PWM Channel 1
-#define AT91C_PA1_TIOB0    (AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD     (AT91C_PIO_PA10) //  DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2    (AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0    (AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0     (AT91C_PIO_PA11) //  PWM Channel 0
-#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO     (AT91C_PIO_PA12) //  SPI Master In Slave
-#define AT91C_PA12_PWM1     (AT91C_PIO_PA12) //  PWM Channel 1
-#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI     (AT91C_PIO_PA13) //  SPI Master Out Slave
-#define AT91C_PA13_PWM2     (AT91C_PIO_PA13) //  PWM Channel 2
-#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK     (AT91C_PIO_PA14) //  SPI Serial Clock
-#define AT91C_PA14_PWM3     (AT91C_PIO_PA14) //  PWM Channel 3
-#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF       (AT91C_PIO_PA15) //  SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1    (AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK       (AT91C_PIO_PA16) //  SSC Transmit Clock
-#define AT91C_PA16_TIOB1    (AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD       (AT91C_PIO_PA17) //  SSC Transmit data
-#define AT91C_PA17_PCK1     (AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD       (AT91C_PIO_PA18) //  SSC Receive Data
-#define AT91C_PA18_PCK2     (AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK       (AT91C_PIO_PA19) //  SSC Receive Clock
-#define AT91C_PA19_FIQ      (AT91C_PIO_PA19) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2     (AT91C_PIO_PA2) //  PWM Channel 2
-#define AT91C_PA2_SCK0     (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF       (AT91C_PIO_PA20) //  SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0     (AT91C_PIO_PA20) //  External Interrupt 0
-#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1     (AT91C_PIO_PA21) //  USART 1 Receive Data
-#define AT91C_PA21_PCK1     (AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1     (AT91C_PIO_PA22) //  USART 1 Transmit Data
-#define AT91C_PA22_NPCS3    (AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1     (AT91C_PIO_PA23) //  USART 1 Serial Clock
-#define AT91C_PA23_PWM0     (AT91C_PIO_PA23) //  PWM Channel 0
-#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1     (AT91C_PIO_PA24) //  USART 1 Ready To Send
-#define AT91C_PA24_PWM1     (AT91C_PIO_PA24) //  PWM Channel 1
-#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1     (AT91C_PIO_PA25) //  USART 1 Clear To Send
-#define AT91C_PA25_PWM2     (AT91C_PIO_PA25) //  PWM Channel 2
-#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1     (AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2    (AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1     (AT91C_PIO_PA27) //  USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2    (AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1     (AT91C_PIO_PA28) //  USART 1 Data Set ready
-#define AT91C_PA28_TCLK1    (AT91C_PIO_PA28) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1      (AT91C_PIO_PA29) //  USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2    (AT91C_PIO_PA29) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD      (AT91C_PIO_PA3) //  TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3    (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1     (AT91C_PIO_PA30) //  External Interrupt 1
-#define AT91C_PA30_NPCS2    (AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1    (AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2     (AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK     (AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0    (AT91C_PIO_PA4) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0     (AT91C_PIO_PA5) //  USART 0 Receive Data
-#define AT91C_PA5_NPCS3    (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0     (AT91C_PIO_PA6) //  USART 0 Transmit Data
-#define AT91C_PA6_PCK0     (AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0     (AT91C_PIO_PA7) //  USART 0 Ready To Send
-#define AT91C_PA7_PWM3     (AT91C_PIO_PA7) //  PWM Channel 3
-#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0     (AT91C_PIO_PA8) //  USART 0 Clear To Send
-#define AT91C_PA8_ADTRG    (AT91C_PIO_PA8) //  ADC External Trigger
-#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD     (AT91C_PIO_PA9) //  DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1    (AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S128
-// *****************************************************************************
-#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ( 1) // System Peripheral
-#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ( 3) // Reserved
-#define AT91C_ID_ADC    ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI    ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0    ( 6) // USART 0
-#define AT91C_ID_US1    ( 7) // USART 1
-#define AT91C_ID_SSC    ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC   (10) // PWM Controller
-#define AT91C_ID_UDP    (11) // USB Device Port
-#define AT91C_ID_TC0    (12) // Timer Counter 0
-#define AT91C_ID_TC1    (13) // Timer Counter 1
-#define AT91C_ID_TC2    (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved (15) // Reserved
-#define AT91C_ID_16_Reserved (16) // Reserved
-#define AT91C_ID_17_Reserved (17) // Reserved
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0   (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT   (0xC0007FF7) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S128
-// *****************************************************************************
-#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      (AT91_CAST(AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        (AT91_CAST(AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI   (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI       (AT91_CAST(AT91PS_SPI) 	0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       (AT91_CAST(AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI       (AT91_CAST(AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S128
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM	 (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 (0x00008000) // Internal SRAM size in byte (32 Kbytes)
-// IFLASH
-#define AT91C_IFLASH	 (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE	 (0x00020000) // Internal FLASH size in byte (128 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE	 (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE	 (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES	 (512) // Internal FLASH Number of Pages: 512 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (8) // Internal FLASH Number of Lock Bits: 8 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h
deleted file mode 100644
index a4f1af138..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h
+++ /dev/null
@@ -1,2229 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  Copyright (c) 2006, Atmel Corporation
-//
-//  All rights reserved.
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions are met:
-//
-//  - Redistributions of source code must retain the above copyright notice,
-//  this list of conditions and the disclaimer below.
-//
-//  Atmel's name may not be used to endorse or promote products derived from
-//  this software without specific prior written permission.
-//
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7S256.h
-// Object              : AT91SAM7S256 definitions
-// Generated           : AT91 SW Application Group  07/07/2008 (16:12:57)
-//
-// CVS Reference       : /AT91SAM7S256.pl/1.12/Wed Aug 30 14:08:39 2006//
-// CVS Reference       : /SYS_SAM7S.pl/1.2/Thu Feb  3 10:47:39 2005//
-// CVS Reference       : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006//
-// CVS Reference       : /PMC_SAM7S_USB.pl/1.4/Tue Feb  8 14:00:19 2005//
-// CVS Reference       : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference       : /UDP_4ept.pl/1.1/Thu Aug  3 12:26:00 2006//
-// CVS Reference       : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:40:38 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
-// CVS Reference       : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7S256_H
-#define AT91SAM7S256_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	//
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	//
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	//
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	//
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	//
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	//
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	//
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	//
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[469]; 	//
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved13[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved14[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved15[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved16[3]; 	//
-	AT91_REG	 PMC_PCKR[3]; 	// Programmable Clock Register
-	AT91_REG	 Reserved17[5]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved18[36]; 	//
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved19[5]; 	//
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved20[5]; 	//
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	//
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	//
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	//
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
-#define CKGR_PLLR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	//
-	AT91_REG	 PMC_PCKR[3]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[5]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN     (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	//
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR         (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR          (AT91_CAST(AT91_REG *) 	0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR          (AT91_CAST(AT91_REG *) 	0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR          (AT91_CAST(AT91_REG *) 	0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          (0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         (0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	//
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	//
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
-#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
-#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	//
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	//
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	//
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
-#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	//
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	//
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
-#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
-#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
-#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	//
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved2[50]; 	//
-	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
-	AT91_REG	 TWI_RCR; 	// Receive Counter Register
-	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
-	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
-#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
-#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
-#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
-#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
-#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
-#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	//
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	//
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	//
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR        (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR      (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR      (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR      (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved        (AT91_CAST(AT91_REG *) 	0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	//
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA        (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS        (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR         (AT91_CAST(AT91_REG *) 	0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 UDP_CSR[4]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[4]; 	//
-	AT91_REG	 UDP_FDR[4]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[5]; 	//
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP)
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   (AT91_CAST(AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    (AT91_CAST(AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   (AT91_CAST(AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    (AT91_CAST(AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    (AT91_CAST(AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TPR   (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_TCR   (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR   (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_SPI) Receive Counter Register
-#define AT91C_SPI_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_RPR   (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_IER   (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_SR    (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_CR    (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_MR    (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (SPI) Mode Register
-#define AT91C_SPI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_TDR   (AT91_CAST(AT91_REG *) 	0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_RDR   (AT91_CAST(AT91_REG *) 	0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CSR   (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (SPI) Chip Select Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   (AT91_CAST(AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   (AT91_CAST(AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7S256
-// *****************************************************************************
-#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0     (AT91C_PIO_PA0) //  PWM Channel 0
-#define AT91C_PA0_TIOA0    (AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1     (AT91C_PIO_PA1) //  PWM Channel 1
-#define AT91C_PA1_TIOB0    (AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD     (AT91C_PIO_PA10) //  DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2    (AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0    (AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0     (AT91C_PIO_PA11) //  PWM Channel 0
-#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO     (AT91C_PIO_PA12) //  SPI Master In Slave
-#define AT91C_PA12_PWM1     (AT91C_PIO_PA12) //  PWM Channel 1
-#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI     (AT91C_PIO_PA13) //  SPI Master Out Slave
-#define AT91C_PA13_PWM2     (AT91C_PIO_PA13) //  PWM Channel 2
-#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK     (AT91C_PIO_PA14) //  SPI Serial Clock
-#define AT91C_PA14_PWM3     (AT91C_PIO_PA14) //  PWM Channel 3
-#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF       (AT91C_PIO_PA15) //  SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1    (AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK       (AT91C_PIO_PA16) //  SSC Transmit Clock
-#define AT91C_PA16_TIOB1    (AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD       (AT91C_PIO_PA17) //  SSC Transmit data
-#define AT91C_PA17_PCK1     (AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD       (AT91C_PIO_PA18) //  SSC Receive Data
-#define AT91C_PA18_PCK2     (AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK       (AT91C_PIO_PA19) //  SSC Receive Clock
-#define AT91C_PA19_FIQ      (AT91C_PIO_PA19) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2     (AT91C_PIO_PA2) //  PWM Channel 2
-#define AT91C_PA2_SCK0     (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF       (AT91C_PIO_PA20) //  SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0     (AT91C_PIO_PA20) //  External Interrupt 0
-#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1     (AT91C_PIO_PA21) //  USART 1 Receive Data
-#define AT91C_PA21_PCK1     (AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1     (AT91C_PIO_PA22) //  USART 1 Transmit Data
-#define AT91C_PA22_NPCS3    (AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1     (AT91C_PIO_PA23) //  USART 1 Serial Clock
-#define AT91C_PA23_PWM0     (AT91C_PIO_PA23) //  PWM Channel 0
-#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1     (AT91C_PIO_PA24) //  USART 1 Ready To Send
-#define AT91C_PA24_PWM1     (AT91C_PIO_PA24) //  PWM Channel 1
-#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1     (AT91C_PIO_PA25) //  USART 1 Clear To Send
-#define AT91C_PA25_PWM2     (AT91C_PIO_PA25) //  PWM Channel 2
-#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1     (AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2    (AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1     (AT91C_PIO_PA27) //  USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2    (AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1     (AT91C_PIO_PA28) //  USART 1 Data Set ready
-#define AT91C_PA28_TCLK1    (AT91C_PIO_PA28) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1      (AT91C_PIO_PA29) //  USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2    (AT91C_PIO_PA29) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD      (AT91C_PIO_PA3) //  TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3    (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1     (AT91C_PIO_PA30) //  External Interrupt 1
-#define AT91C_PA30_NPCS2    (AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1    (AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2     (AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK     (AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0    (AT91C_PIO_PA4) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0     (AT91C_PIO_PA5) //  USART 0 Receive Data
-#define AT91C_PA5_NPCS3    (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0     (AT91C_PIO_PA6) //  USART 0 Transmit Data
-#define AT91C_PA6_PCK0     (AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0     (AT91C_PIO_PA7) //  USART 0 Ready To Send
-#define AT91C_PA7_PWM3     (AT91C_PIO_PA7) //  PWM Channel 3
-#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0     (AT91C_PIO_PA8) //  USART 0 Clear To Send
-#define AT91C_PA8_ADTRG    (AT91C_PIO_PA8) //  ADC External Trigger
-#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD     (AT91C_PIO_PA9) //  DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1    (AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256
-// *****************************************************************************
-#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ( 1) // System Peripheral
-#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ( 3) // Reserved
-#define AT91C_ID_ADC    ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI    ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0    ( 6) // USART 0
-#define AT91C_ID_US1    ( 7) // USART 1
-#define AT91C_ID_SSC    ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC   (10) // PWM Controller
-#define AT91C_ID_UDP    (11) // USB Device Port
-#define AT91C_ID_TC0    (12) // Timer Counter 0
-#define AT91C_ID_TC1    (13) // Timer Counter 1
-#define AT91C_ID_TC2    (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved (15) // Reserved
-#define AT91C_ID_16_Reserved (16) // Reserved
-#define AT91C_ID_17_Reserved (17) // Reserved
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0   (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT   (0xC0007FF7) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S256
-// *****************************************************************************
-#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      (AT91_CAST(AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        (AT91_CAST(AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI   (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI       (AT91_CAST(AT91PS_SPI) 	0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       (AT91_CAST(AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI       (AT91_CAST(AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM	 (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 (0x00010000) // Internal SRAM size in byte (64 Kbytes)
-// IFLASH
-#define AT91C_IFLASH	 (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE	 (0x00040000) // Internal FLASH size in byte (256 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE	 (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE	 (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES	 (1024) // Internal FLASH Number of Pages: 1024 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (16) // Internal FLASH Number of Lock Bits: 16 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h
deleted file mode 100644
index aa45c3924..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h
+++ /dev/null
@@ -1,2303 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  Copyright (c) 2006, Atmel Corporation
-//
-//  All rights reserved.
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions are met:
-//
-//  - Redistributions of source code must retain the above copyright notice,
-//  this list of conditions and the disclaimer below.
-//
-//  Atmel's name may not be used to endorse or promote products derived from
-//  this software without specific prior written permission.
-//
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7S512.h
-// Object              : AT91SAM7S512 definitions
-// Generated           : AT91 SW Application Group  07/07/2008 (16:13:20)
-//
-// CVS Reference       : /AT91SAM7S512.pl/1.6/Wed Aug 30 14:08:44 2006//
-// CVS Reference       : /SYS_SAM7S.pl/1.2/Thu Feb  3 10:47:39 2005//
-// CVS Reference       : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006//
-// CVS Reference       : /PMC_SAM7S_USB.pl/1.4/Tue Feb  8 14:00:19 2005//
-// CVS Reference       : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference       : /UDP_4ept.pl/1.1/Thu Aug  3 12:26:00 2006//
-// CVS Reference       : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:40:38 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference       : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// CVS Reference       : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005//
-// CVS Reference       : /SMC_1783A.pl/1.4/Thu Feb  3 10:30:06 2005//
-// CVS Reference       : /SDRC_SAM7SE512.pl/1.7/Fri Jul  8 07:50:18 2005//
-// CVS Reference       : /HECC_SAM7SE512.pl/1.8/Tue Jul 12 06:31:42 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7S512_H
-#define AT91SAM7S512_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	//
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	//
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	//
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	//
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	//
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	//
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	//
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	//
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[469]; 	//
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved13[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved14[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved15[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved16[3]; 	//
-	AT91_REG	 PMC_PCKR[3]; 	// Programmable Clock Register
-	AT91_REG	 Reserved17[5]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved18[36]; 	//
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved19[5]; 	//
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved20[5]; 	//
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	//
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	//
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	//
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
-#define CKGR_PLLR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	//
-	AT91_REG	 PMC_PCKR[3]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[5]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN     (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Embedded Flash Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EFC {
-	AT91_REG	 EFC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 EFC_FCR; 	// MC Flash Command Register
-	AT91_REG	 EFC_FSR; 	// MC Flash Status Register
-	AT91_REG	 EFC_VR; 	// MC Flash Version Register
-} AT91S_EFC, *AT91PS_EFC;
-#else
-#define MC_FMR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_FCR) MC Flash Command Register
-#define MC_FSR          (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_FSR) MC Flash Status Register
-#define MC_VR           (AT91_CAST(AT91_REG *) 	0x0000000C) // (MC_VR) MC Flash Version Register
-
-#endif
-// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         (0x1 <<  0) // (EFC) Flash Ready
-#define AT91C_MC_LOCKE        (0x1 <<  2) // (EFC) Lock Error
-#define AT91C_MC_PROGE        (0x1 <<  3) // (EFC) Programming Error
-#define AT91C_MC_NEBP         (0x1 <<  7) // (EFC) No Erase Before Programming
-#define AT91C_MC_FWS          (0x3 <<  8) // (EFC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (EFC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (EFC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (EFC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (EFC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         (0xFF << 16) // (EFC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register --------
-#define AT91C_MC_FCMD         (0xF <<  0) // (EFC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (EFC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (EFC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (EFC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (EFC) Set Security Bit.
-#define AT91C_MC_PAGEN        (0x3FF <<  8) // (EFC) Page Number
-#define AT91C_MC_KEY          (0xFF << 24) // (EFC) Writing Protect Key
-// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     (0x1 <<  4) // (EFC) Security Bit Status
-#define AT91C_MC_GPNVM0       (0x1 <<  8) // (EFC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       (0x1 <<  9) // (EFC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       (0x1 << 10) // (EFC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       (0x1 << 11) // (EFC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       (0x1 << 12) // (EFC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       (0x1 << 13) // (EFC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       (0x1 << 14) // (EFC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       (0x1 << 15) // (EFC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       (0x1 << 16) // (EFC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       (0x1 << 17) // (EFC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       (0x1 << 18) // (EFC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       (0x1 << 19) // (EFC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       (0x1 << 20) // (EFC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       (0x1 << 21) // (EFC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       (0x1 << 22) // (EFC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       (0x1 << 23) // (EFC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       (0x1 << 24) // (EFC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       (0x1 << 25) // (EFC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      (0x1 << 26) // (EFC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      (0x1 << 27) // (EFC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      (0x1 << 28) // (EFC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      (0x1 << 29) // (EFC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      (0x1 << 30) // (EFC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      (0x1 << 31) // (EFC) Sector 15 Lock Status
-// -------- EFC_VR : (EFC Offset: 0xc) EFC version register --------
-#define AT91C_EFC_VERSION     (0xFFF <<  0) // (EFC) EFC version number
-#define AT91C_EFC_MFN         (0x7 << 16) // (EFC) EFC MFN
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 MC_PUIA[16]; 	// MC Protection Unit Area
-	AT91_REG	 MC_PUP; 	// MC Protection Unit Peripherals
-	AT91_REG	 MC_PUER; 	// MC Protection Unit Enable Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 MC0_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC0_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC0_FSR; 	// MC Flash Status Register
-	AT91_REG	 MC0_VR; 	// MC Flash Version Register
-	AT91_REG	 MC1_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC1_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC1_FSR; 	// MC Flash Status Register
-	AT91_REG	 MC1_VR; 	// MC Flash Version Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR         (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_PUIA         (AT91_CAST(AT91_REG *) 	0x00000010) // (MC_PUIA) MC Protection Unit Area
-#define MC_PUP          (AT91_CAST(AT91_REG *) 	0x00000050) // (MC_PUP) MC Protection Unit Peripherals
-#define MC_PUER         (AT91_CAST(AT91_REG *) 	0x00000054) // (MC_PUER) MC Protection Unit Enable Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_MPU          (0x1 <<  2) // (MC) Memory protection Unit Abort Status
-#define AT91C_MC_ABTSZ        (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
-#define AT91C_MC_PROT         (0x3 <<  0) // (MC) Protection
-#define 	AT91C_MC_PROT_PNAUNA               (0x0) // (MC) Privilege: No Access, User: No Access
-#define 	AT91C_MC_PROT_PRWUNA               (0x1) // (MC) Privilege: Read/Write, User: No Access
-#define 	AT91C_MC_PROT_PRWURO               (0x2) // (MC) Privilege: Read/Write, User: Read Only
-#define 	AT91C_MC_PROT_PRWURW               (0x3) // (MC) Privilege: Read/Write, User: Read/Write
-#define AT91C_MC_SIZE         (0xF <<  4) // (MC) Internal Area Size
-#define 	AT91C_MC_SIZE_1KB                  (0x0 <<  4) // (MC) Area size 1KByte
-#define 	AT91C_MC_SIZE_2KB                  (0x1 <<  4) // (MC) Area size 2KByte
-#define 	AT91C_MC_SIZE_4KB                  (0x2 <<  4) // (MC) Area size 4KByte
-#define 	AT91C_MC_SIZE_8KB                  (0x3 <<  4) // (MC) Area size 8KByte
-#define 	AT91C_MC_SIZE_16KB                 (0x4 <<  4) // (MC) Area size 16KByte
-#define 	AT91C_MC_SIZE_32KB                 (0x5 <<  4) // (MC) Area size 32KByte
-#define 	AT91C_MC_SIZE_64KB                 (0x6 <<  4) // (MC) Area size 64KByte
-#define 	AT91C_MC_SIZE_128KB                (0x7 <<  4) // (MC) Area size 128KByte
-#define 	AT91C_MC_SIZE_256KB                (0x8 <<  4) // (MC) Area size 256KByte
-#define 	AT91C_MC_SIZE_512KB                (0x9 <<  4) // (MC) Area size 512KByte
-#define 	AT91C_MC_SIZE_1MB                  (0xA <<  4) // (MC) Area size 1MByte
-#define 	AT91C_MC_SIZE_2MB                  (0xB <<  4) // (MC) Area size 2MByte
-#define 	AT91C_MC_SIZE_4MB                  (0xC <<  4) // (MC) Area size 4MByte
-#define 	AT91C_MC_SIZE_8MB                  (0xD <<  4) // (MC) Area size 8MByte
-#define 	AT91C_MC_SIZE_16MB                 (0xE <<  4) // (MC) Area size 16MByte
-#define 	AT91C_MC_SIZE_64MB                 (0xF <<  4) // (MC) Area size 64MByte
-#define AT91C_MC_BA           (0x3FFFF << 10) // (MC) Internal Area Base Address
-// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
-// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
-#define AT91C_MC_PUEB         (0x1 <<  0) // (MC) Protection Unit enable Bit
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	//
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	//
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
-#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
-#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	//
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	//
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	//
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
-#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	//
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	//
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
-#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
-#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
-#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	//
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved2[50]; 	//
-	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
-	AT91_REG	 TWI_RCR; 	// Receive Counter Register
-	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
-	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
-#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
-#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
-#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
-#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
-#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
-#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	//
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	//
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	//
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR        (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR      (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR      (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR      (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved        (AT91_CAST(AT91_REG *) 	0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	//
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA        (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS        (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR         (AT91_CAST(AT91_REG *) 	0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 UDP_CSR[4]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[4]; 	//
-	AT91_REG	 UDP_FDR[4]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[5]; 	//
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP)
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S512
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   (AT91_CAST(AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for EFC0 peripheral ==========
-#define AT91C_EFC0_FCR  (AT91_CAST(AT91_REG *) 	0xFFFFFF64) // (EFC0) MC Flash Command Register
-#define AT91C_EFC0_FSR  (AT91_CAST(AT91_REG *) 	0xFFFFFF68) // (EFC0) MC Flash Status Register
-#define AT91C_EFC0_VR   (AT91_CAST(AT91_REG *) 	0xFFFFFF6C) // (EFC0) MC Flash Version Register
-#define AT91C_EFC0_FMR  (AT91_CAST(AT91_REG *) 	0xFFFFFF60) // (EFC0) MC Flash Mode Register
-// ========== Register definition for EFC1 peripheral ==========
-#define AT91C_EFC1_VR   (AT91_CAST(AT91_REG *) 	0xFFFFFF7C) // (EFC1) MC Flash Version Register
-#define AT91C_EFC1_FCR  (AT91_CAST(AT91_REG *) 	0xFFFFFF74) // (EFC1) MC Flash Command Register
-#define AT91C_EFC1_FSR  (AT91_CAST(AT91_REG *) 	0xFFFFFF78) // (EFC1) MC Flash Status Register
-#define AT91C_EFC1_FMR  (AT91_CAST(AT91_REG *) 	0xFFFFFF70) // (EFC1) MC Flash Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    (AT91_CAST(AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_PUP    (AT91_CAST(AT91_REG *) 	0xFFFFFF50) // (MC) MC Protection Unit Peripherals
-#define AT91C_MC_PUIA   (AT91_CAST(AT91_REG *) 	0xFFFFFF10) // (MC) MC Protection Unit Area
-#define AT91C_MC_AASR   (AT91_CAST(AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_PUER   (AT91_CAST(AT91_REG *) 	0xFFFFFF54) // (MC) MC Protection Unit Enable Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TPR   (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_TCR   (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR   (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_SPI) Receive Counter Register
-#define AT91C_SPI_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_RPR   (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_IER   (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_SR    (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_CR    (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_MR    (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (SPI) Mode Register
-#define AT91C_SPI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_TDR   (AT91_CAST(AT91_REG *) 	0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_RDR   (AT91_CAST(AT91_REG *) 	0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CSR   (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (SPI) Chip Select Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   (AT91_CAST(AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   (AT91_CAST(AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7S512
-// *****************************************************************************
-#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0     (AT91C_PIO_PA0) //  PWM Channel 0
-#define AT91C_PA0_TIOA0    (AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1     (AT91C_PIO_PA1) //  PWM Channel 1
-#define AT91C_PA1_TIOB0    (AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD     (AT91C_PIO_PA10) //  DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2    (AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0    (AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0     (AT91C_PIO_PA11) //  PWM Channel 0
-#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO     (AT91C_PIO_PA12) //  SPI Master In Slave
-#define AT91C_PA12_PWM1     (AT91C_PIO_PA12) //  PWM Channel 1
-#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI     (AT91C_PIO_PA13) //  SPI Master Out Slave
-#define AT91C_PA13_PWM2     (AT91C_PIO_PA13) //  PWM Channel 2
-#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK     (AT91C_PIO_PA14) //  SPI Serial Clock
-#define AT91C_PA14_PWM3     (AT91C_PIO_PA14) //  PWM Channel 3
-#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF       (AT91C_PIO_PA15) //  SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1    (AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK       (AT91C_PIO_PA16) //  SSC Transmit Clock
-#define AT91C_PA16_TIOB1    (AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD       (AT91C_PIO_PA17) //  SSC Transmit data
-#define AT91C_PA17_PCK1     (AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD       (AT91C_PIO_PA18) //  SSC Receive Data
-#define AT91C_PA18_PCK2     (AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK       (AT91C_PIO_PA19) //  SSC Receive Clock
-#define AT91C_PA19_FIQ      (AT91C_PIO_PA19) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2     (AT91C_PIO_PA2) //  PWM Channel 2
-#define AT91C_PA2_SCK0     (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF       (AT91C_PIO_PA20) //  SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0     (AT91C_PIO_PA20) //  External Interrupt 0
-#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1     (AT91C_PIO_PA21) //  USART 1 Receive Data
-#define AT91C_PA21_PCK1     (AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1     (AT91C_PIO_PA22) //  USART 1 Transmit Data
-#define AT91C_PA22_NPCS3    (AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1     (AT91C_PIO_PA23) //  USART 1 Serial Clock
-#define AT91C_PA23_PWM0     (AT91C_PIO_PA23) //  PWM Channel 0
-#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1     (AT91C_PIO_PA24) //  USART 1 Ready To Send
-#define AT91C_PA24_PWM1     (AT91C_PIO_PA24) //  PWM Channel 1
-#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1     (AT91C_PIO_PA25) //  USART 1 Clear To Send
-#define AT91C_PA25_PWM2     (AT91C_PIO_PA25) //  PWM Channel 2
-#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1     (AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2    (AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1     (AT91C_PIO_PA27) //  USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2    (AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1     (AT91C_PIO_PA28) //  USART 1 Data Set ready
-#define AT91C_PA28_TCLK1    (AT91C_PIO_PA28) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1      (AT91C_PIO_PA29) //  USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2    (AT91C_PIO_PA29) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD      (AT91C_PIO_PA3) //  TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3    (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1     (AT91C_PIO_PA30) //  External Interrupt 1
-#define AT91C_PA30_NPCS2    (AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1    (AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2     (AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK     (AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0    (AT91C_PIO_PA4) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0     (AT91C_PIO_PA5) //  USART 0 Receive Data
-#define AT91C_PA5_NPCS3    (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0     (AT91C_PIO_PA6) //  USART 0 Transmit Data
-#define AT91C_PA6_PCK0     (AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0     (AT91C_PIO_PA7) //  USART 0 Ready To Send
-#define AT91C_PA7_PWM3     (AT91C_PIO_PA7) //  PWM Channel 3
-#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0     (AT91C_PIO_PA8) //  USART 0 Clear To Send
-#define AT91C_PA8_ADTRG    (AT91C_PIO_PA8) //  ADC External Trigger
-#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD     (AT91C_PIO_PA9) //  DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1    (AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S512
-// *****************************************************************************
-#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ( 1) // System Peripheral
-#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ( 3) // Reserved
-#define AT91C_ID_ADC    ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI    ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0    ( 6) // USART 0
-#define AT91C_ID_US1    ( 7) // USART 1
-#define AT91C_ID_SSC    ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC   (10) // PWM Controller
-#define AT91C_ID_UDP    (11) // USB Device Port
-#define AT91C_ID_TC0    (12) // Timer Counter 0
-#define AT91C_ID_TC1    (13) // Timer Counter 1
-#define AT91C_ID_TC2    (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved (15) // Reserved
-#define AT91C_ID_16_Reserved (16) // Reserved
-#define AT91C_ID_17_Reserved (17) // Reserved
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0   (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT   (0xC0007FF7) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S512
-// *****************************************************************************
-#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      (AT91_CAST(AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_EFC0      (AT91_CAST(AT91PS_EFC) 	0xFFFFFF60) // (EFC0) Base Address
-#define AT91C_BASE_EFC1      (AT91_CAST(AT91PS_EFC) 	0xFFFFFF70) // (EFC1) Base Address
-#define AT91C_BASE_MC        (AT91_CAST(AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI   (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI       (AT91_CAST(AT91PS_SPI) 	0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       (AT91_CAST(AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI       (AT91_CAST(AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S512
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM	 (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 (0x00010000) // Internal SRAM size in byte (64 Kbytes)
-// IFLASH
-#define AT91C_IFLASH	 (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE	 (0x00080000) // Internal FLASH size in byte (512 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE	 (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE	 (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES	 (2048) // Internal FLASH Number of Pages: 2048 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (32) // Internal FLASH Number of Lock Bits: 32 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h
deleted file mode 100644
index d124ce2a9..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h
+++ /dev/null
@@ -1,2229 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  Copyright (c) 2006, Atmel Corporation
-//
-//  All rights reserved.
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions are met:
-//
-//  - Redistributions of source code must retain the above copyright notice,
-//  this list of conditions and the disclaimer below.
-//
-//  Atmel's name may not be used to endorse or promote products derived from
-//  this software without specific prior written permission.
-//
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7S64.h
-// Object              : AT91SAM7S64 definitions
-// Generated           : AT91 SW Application Group  07/07/2008 (16:13:29)
-//
-// CVS Reference       : /AT91SAM7S64.pl/1.23/Wed Aug 30 14:08:51 2006//
-// CVS Reference       : /SYS_SAM7S.pl/1.2/Thu Feb  3 10:47:39 2005//
-// CVS Reference       : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006//
-// CVS Reference       : /PMC_SAM7S_USB.pl/1.4/Tue Feb  8 14:00:19 2005//
-// CVS Reference       : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference       : /UDP_4ept.pl/1.1/Thu Aug  3 12:26:00 2006//
-// CVS Reference       : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:40:38 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
-// CVS Reference       : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7S64_H
-#define AT91SAM7S64_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	//
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	//
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	//
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	//
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	//
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	//
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	//
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	//
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[469]; 	//
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved13[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved14[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved15[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved16[3]; 	//
-	AT91_REG	 PMC_PCKR[3]; 	// Programmable Clock Register
-	AT91_REG	 Reserved17[5]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved18[36]; 	//
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved19[5]; 	//
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved20[5]; 	//
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	//
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	//
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	//
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
-#define CKGR_PLLR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	//
-	AT91_REG	 PMC_PCKR[3]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[5]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN     (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	//
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR         (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR          (AT91_CAST(AT91_REG *) 	0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR          (AT91_CAST(AT91_REG *) 	0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR          (AT91_CAST(AT91_REG *) 	0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          (0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         (0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	//
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	//
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
-#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
-#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	//
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	//
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	//
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
-#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	//
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	//
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
-#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
-#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
-#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	//
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved2[50]; 	//
-	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
-	AT91_REG	 TWI_RCR; 	// Receive Counter Register
-	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
-	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
-#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
-#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
-#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
-#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
-#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
-#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	//
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	//
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	//
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR        (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR      (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR      (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR      (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved        (AT91_CAST(AT91_REG *) 	0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	//
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA        (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS        (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR         (AT91_CAST(AT91_REG *) 	0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 UDP_CSR[4]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[4]; 	//
-	AT91_REG	 UDP_FDR[4]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[5]; 	//
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP)
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   (AT91_CAST(AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    (AT91_CAST(AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   (AT91_CAST(AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    (AT91_CAST(AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    (AT91_CAST(AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TPR   (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_TCR   (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR   (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_SPI) Receive Counter Register
-#define AT91C_SPI_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_RPR   (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_IER   (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_SR    (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_CR    (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_MR    (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (SPI) Mode Register
-#define AT91C_SPI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_TDR   (AT91_CAST(AT91_REG *) 	0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_RDR   (AT91_CAST(AT91_REG *) 	0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CSR   (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (SPI) Chip Select Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   (AT91_CAST(AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   (AT91_CAST(AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0     (AT91C_PIO_PA0) //  PWM Channel 0
-#define AT91C_PA0_TIOA0    (AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1     (AT91C_PIO_PA1) //  PWM Channel 1
-#define AT91C_PA1_TIOB0    (AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD     (AT91C_PIO_PA10) //  DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2    (AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0    (AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0     (AT91C_PIO_PA11) //  PWM Channel 0
-#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO     (AT91C_PIO_PA12) //  SPI Master In Slave
-#define AT91C_PA12_PWM1     (AT91C_PIO_PA12) //  PWM Channel 1
-#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI     (AT91C_PIO_PA13) //  SPI Master Out Slave
-#define AT91C_PA13_PWM2     (AT91C_PIO_PA13) //  PWM Channel 2
-#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK     (AT91C_PIO_PA14) //  SPI Serial Clock
-#define AT91C_PA14_PWM3     (AT91C_PIO_PA14) //  PWM Channel 3
-#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF       (AT91C_PIO_PA15) //  SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1    (AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK       (AT91C_PIO_PA16) //  SSC Transmit Clock
-#define AT91C_PA16_TIOB1    (AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD       (AT91C_PIO_PA17) //  SSC Transmit data
-#define AT91C_PA17_PCK1     (AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD       (AT91C_PIO_PA18) //  SSC Receive Data
-#define AT91C_PA18_PCK2     (AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK       (AT91C_PIO_PA19) //  SSC Receive Clock
-#define AT91C_PA19_FIQ      (AT91C_PIO_PA19) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2     (AT91C_PIO_PA2) //  PWM Channel 2
-#define AT91C_PA2_SCK0     (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF       (AT91C_PIO_PA20) //  SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0     (AT91C_PIO_PA20) //  External Interrupt 0
-#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1     (AT91C_PIO_PA21) //  USART 1 Receive Data
-#define AT91C_PA21_PCK1     (AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1     (AT91C_PIO_PA22) //  USART 1 Transmit Data
-#define AT91C_PA22_NPCS3    (AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1     (AT91C_PIO_PA23) //  USART 1 Serial Clock
-#define AT91C_PA23_PWM0     (AT91C_PIO_PA23) //  PWM Channel 0
-#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1     (AT91C_PIO_PA24) //  USART 1 Ready To Send
-#define AT91C_PA24_PWM1     (AT91C_PIO_PA24) //  PWM Channel 1
-#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1     (AT91C_PIO_PA25) //  USART 1 Clear To Send
-#define AT91C_PA25_PWM2     (AT91C_PIO_PA25) //  PWM Channel 2
-#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1     (AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2    (AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1     (AT91C_PIO_PA27) //  USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2    (AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1     (AT91C_PIO_PA28) //  USART 1 Data Set ready
-#define AT91C_PA28_TCLK1    (AT91C_PIO_PA28) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1      (AT91C_PIO_PA29) //  USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2    (AT91C_PIO_PA29) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD      (AT91C_PIO_PA3) //  TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3    (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1     (AT91C_PIO_PA30) //  External Interrupt 1
-#define AT91C_PA30_NPCS2    (AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1    (AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2     (AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK     (AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0    (AT91C_PIO_PA4) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0     (AT91C_PIO_PA5) //  USART 0 Receive Data
-#define AT91C_PA5_NPCS3    (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0     (AT91C_PIO_PA6) //  USART 0 Transmit Data
-#define AT91C_PA6_PCK0     (AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0     (AT91C_PIO_PA7) //  USART 0 Ready To Send
-#define AT91C_PA7_PWM3     (AT91C_PIO_PA7) //  PWM Channel 3
-#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0     (AT91C_PIO_PA8) //  USART 0 Clear To Send
-#define AT91C_PA8_ADTRG    (AT91C_PIO_PA8) //  ADC External Trigger
-#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD     (AT91C_PIO_PA9) //  DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1    (AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ( 1) // System Peripheral
-#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ( 3) // Reserved
-#define AT91C_ID_ADC    ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI    ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0    ( 6) // USART 0
-#define AT91C_ID_US1    ( 7) // USART 1
-#define AT91C_ID_SSC    ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC   (10) // PWM Controller
-#define AT91C_ID_UDP    (11) // USB Device Port
-#define AT91C_ID_TC0    (12) // Timer Counter 0
-#define AT91C_ID_TC1    (13) // Timer Counter 1
-#define AT91C_ID_TC2    (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved (15) // Reserved
-#define AT91C_ID_16_Reserved (16) // Reserved
-#define AT91C_ID_17_Reserved (17) // Reserved
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0   (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT   (0xC0007FF7) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      (AT91_CAST(AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        (AT91_CAST(AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI   (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI       (AT91_CAST(AT91PS_SPI) 	0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       (AT91_CAST(AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI       (AT91_CAST(AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM	 (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 (0x00004000) // Internal SRAM size in byte (16 Kbytes)
-// IFLASH
-#define AT91C_IFLASH	 (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE	 (0x00010000) // Internal FLASH size in byte (64 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE	 (128) // Internal FLASH Page Size: 128 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE	 (4096) // Internal FLASH Lock Region Size: 4 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES	 (512) // Internal FLASH Number of Pages: 512 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (16) // Internal FLASH Number of Lock Bits: 16 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h
deleted file mode 100644
index 7fab07f8b..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h
+++ /dev/null
@@ -1,2914 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  Copyright (c) 2006, Atmel Corporation
-//
-//  All rights reserved.
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions are met:
-//
-//  - Redistributions of source code must retain the above copyright notice,
-//  this list of conditions and the disclaimer below.
-//
-//  Atmel's name may not be used to endorse or promote products derived from
-//  this software without specific prior written permission.
-//
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X128.h
-// Object              : AT91SAM7X128 definitions
-// Generated           : AT91 SW Application Group  07/07/2008 (16:15:23)
-//
-// CVS Reference       : /AT91SAM7X128.pl/1.19/Wed Aug 30 14:09:08 2006//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Wed Feb  2 15:48:15 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 14:00:19 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference       : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:40:38 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference       : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008//
-// CVS Reference       : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X128_H
-#define AT91SAM7X128_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	//
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	//
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	//
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	//
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	//
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	//
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	//
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	//
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	//
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	//
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	//
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	//
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	//
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	//
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	//
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	//
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	//
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	//
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[5]; 	//
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved27[5]; 	//
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	//
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	//
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	//
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
-#define CKGR_PLLR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	//
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN     (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	//
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR         (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR          (AT91_CAST(AT91_REG *) 	0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR          (AT91_CAST(AT91_REG *) 	0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR          (AT91_CAST(AT91_REG *) 	0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          (0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         (0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	//
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	//
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
-#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
-#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	//
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	//
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
-#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
-#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
-#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	//
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	//
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
-#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG         (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
-#define 	AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define 	AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define 	AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STOP        (0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0         (0x1 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_CP1         (0x1 <<  9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	//
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved2[50]; 	//
-	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
-	AT91_REG	 TWI_RCR; 	// Receive Counter Register
-	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
-	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
-#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR        (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR      (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR      (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR      (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved        (AT91_CAST(AT91_REG *) 	0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	//
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA        (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS        (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR         (AT91_CAST(AT91_REG *) 	0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	//
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	//
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         (0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP)
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
-#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
-#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
-#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
-#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
-#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	//
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	//
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	//
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-#else
-#define CAN_MMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (CAN_MMR) MailBox Mode Register
-#define CAN_MAM         (AT91_CAST(AT91_REG *) 	0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
-#define CAN_MID         (AT91_CAST(AT91_REG *) 	0x00000008) // (CAN_MID) MailBox ID Register
-#define CAN_MFID        (AT91_CAST(AT91_REG *) 	0x0000000C) // (CAN_MFID) MailBox Family ID Register
-#define CAN_MSR         (AT91_CAST(AT91_REG *) 	0x00000010) // (CAN_MSR) MailBox Status Register
-#define CAN_MDL         (AT91_CAST(AT91_REG *) 	0x00000014) // (CAN_MDL) MailBox Data Low Register
-#define CAN_MDH         (AT91_CAST(AT91_REG *) 	0x00000018) // (CAN_MDH) MailBox Data High Register
-#define CAN_MCR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (CAN_MCR) MailBox Control Register
-
-#endif
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK   (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB       (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP  (0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR        (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	//
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-#else
-#define CAN_MR          (AT91_CAST(AT91_REG *) 	0x00000000) // (CAN_MR) Mode Register
-#define CAN_IER         (AT91_CAST(AT91_REG *) 	0x00000004) // (CAN_IER) Interrupt Enable Register
-#define CAN_IDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (CAN_IDR) Interrupt Disable Register
-#define CAN_IMR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (CAN_IMR) Interrupt Mask Register
-#define CAN_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (CAN_SR) Status Register
-#define CAN_BR          (AT91_CAST(AT91_REG *) 	0x00000014) // (CAN_BR) Baudrate Register
-#define CAN_TIM         (AT91_CAST(AT91_REG *) 	0x00000018) // (CAN_TIM) Timer Register
-#define CAN_TIMESTP     (AT91_CAST(AT91_REG *) 	0x0000001C) // (CAN_TIMESTP) Time Stamp Register
-#define CAN_ECR         (AT91_CAST(AT91_REG *) 	0x00000020) // (CAN_ECR) Error Counter Register
-#define CAN_TCR         (AT91_CAST(AT91_REG *) 	0x00000024) // (CAN_TCR) Transfer Command Register
-#define CAN_ACR         (AT91_CAST(AT91_REG *) 	0x00000028) // (CAN_ACR) Abort Command Register
-#define CAN_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (CAN_VR) Version Register
-
-#endif
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN       (0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      (0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        (0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0         (0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         (0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         (0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         (0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         (0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         (0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         (0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         (0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         (0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         (0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY        (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2      (0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      (0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      (0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER       (0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC         (0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST      (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_NCR; 	// Network Control Register
-	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
-	AT91_REG	 EMAC_NSR; 	// Network Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 EMAC_PTR; 	// Pause Time Register
-	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
-	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
-	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
-	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
-	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
-	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
-	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
-	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
-	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
-	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
-	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
-	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
-	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
-	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
-	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
-	AT91_REG	 Reserved1[13]; 	//
-	AT91_REG	 EMAC_REV; 	// Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-#else
-#define EMAC_NCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (EMAC_NCR) Network Control Register
-#define EMAC_NCFGR      (AT91_CAST(AT91_REG *) 	0x00000004) // (EMAC_NCFGR) Network Configuration Register
-#define EMAC_NSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (EMAC_NSR) Network Status Register
-#define EMAC_TSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (EMAC_TSR) Transmit Status Register
-#define EMAC_RBQP       (AT91_CAST(AT91_REG *) 	0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
-#define EMAC_TBQP       (AT91_CAST(AT91_REG *) 	0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
-#define EMAC_RSR        (AT91_CAST(AT91_REG *) 	0x00000020) // (EMAC_RSR) Receive Status Register
-#define EMAC_ISR        (AT91_CAST(AT91_REG *) 	0x00000024) // (EMAC_ISR) Interrupt Status Register
-#define EMAC_IER        (AT91_CAST(AT91_REG *) 	0x00000028) // (EMAC_IER) Interrupt Enable Register
-#define EMAC_IDR        (AT91_CAST(AT91_REG *) 	0x0000002C) // (EMAC_IDR) Interrupt Disable Register
-#define EMAC_IMR        (AT91_CAST(AT91_REG *) 	0x00000030) // (EMAC_IMR) Interrupt Mask Register
-#define EMAC_MAN        (AT91_CAST(AT91_REG *) 	0x00000034) // (EMAC_MAN) PHY Maintenance Register
-#define EMAC_PTR        (AT91_CAST(AT91_REG *) 	0x00000038) // (EMAC_PTR) Pause Time Register
-#define EMAC_PFR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (EMAC_PFR) Pause Frames received Register
-#define EMAC_FTO        (AT91_CAST(AT91_REG *) 	0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
-#define EMAC_SCF        (AT91_CAST(AT91_REG *) 	0x00000044) // (EMAC_SCF) Single Collision Frame Register
-#define EMAC_MCF        (AT91_CAST(AT91_REG *) 	0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
-#define EMAC_FRO        (AT91_CAST(AT91_REG *) 	0x0000004C) // (EMAC_FRO) Frames Received OK Register
-#define EMAC_FCSE       (AT91_CAST(AT91_REG *) 	0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
-#define EMAC_ALE        (AT91_CAST(AT91_REG *) 	0x00000054) // (EMAC_ALE) Alignment Error Register
-#define EMAC_DTF        (AT91_CAST(AT91_REG *) 	0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
-#define EMAC_LCOL       (AT91_CAST(AT91_REG *) 	0x0000005C) // (EMAC_LCOL) Late Collision Register
-#define EMAC_ECOL       (AT91_CAST(AT91_REG *) 	0x00000060) // (EMAC_ECOL) Excessive Collision Register
-#define EMAC_TUND       (AT91_CAST(AT91_REG *) 	0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
-#define EMAC_CSE        (AT91_CAST(AT91_REG *) 	0x00000068) // (EMAC_CSE) Carrier Sense Error Register
-#define EMAC_RRE        (AT91_CAST(AT91_REG *) 	0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
-#define EMAC_ROV        (AT91_CAST(AT91_REG *) 	0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
-#define EMAC_RSE        (AT91_CAST(AT91_REG *) 	0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
-#define EMAC_ELE        (AT91_CAST(AT91_REG *) 	0x00000078) // (EMAC_ELE) Excessive Length Errors Register
-#define EMAC_RJA        (AT91_CAST(AT91_REG *) 	0x0000007C) // (EMAC_RJA) Receive Jabbers Register
-#define EMAC_USF        (AT91_CAST(AT91_REG *) 	0x00000080) // (EMAC_USF) Undersize Frames Register
-#define EMAC_STE        (AT91_CAST(AT91_REG *) 	0x00000084) // (EMAC_STE) SQE Test Error Register
-#define EMAC_RLE        (AT91_CAST(AT91_REG *) 	0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
-#define EMAC_TPF        (AT91_CAST(AT91_REG *) 	0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
-#define EMAC_HRB        (AT91_CAST(AT91_REG *) 	0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
-#define EMAC_HRT        (AT91_CAST(AT91_REG *) 	0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
-#define EMAC_SA1L       (AT91_CAST(AT91_REG *) 	0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H       (AT91_CAST(AT91_REG *) 	0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L       (AT91_CAST(AT91_REG *) 	0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H       (AT91_CAST(AT91_REG *) 	0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L       (AT91_CAST(AT91_REG *) 	0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H       (AT91_CAST(AT91_REG *) 	0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L       (AT91_CAST(AT91_REG *) 	0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H       (AT91_CAST(AT91_REG *) 	0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID        (AT91_CAST(AT91_REG *) 	0x000000B8) // (EMAC_TID) Type ID Checking Register
-#define EMAC_TPQ        (AT91_CAST(AT91_REG *) 	0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
-#define EMAC_USRIO      (AT91_CAST(AT91_REG *) 	0x000000C0) // (EMAC_USRIO) USER Input/Output Register
-#define EMAC_WOL        (AT91_CAST(AT91_REG *) 	0x000000C4) // (EMAC_WOL) Wake On LAN Register
-#define EMAC_REV        (AT91_CAST(AT91_REG *) 	0x000000FC) // (EMAC_REV) Revision Register
-
-#endif
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  --------
-#define AT91C_EMAC_LB         (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        (0x1 <<  1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE         (0x1 <<  2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE         (0x1 <<  3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE        (0x1 <<  4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT    (0x1 <<  5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT    (0x1 <<  6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT     (0x1 <<  7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP         (0x1 <<  8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART     (0x1 <<  9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT      (0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR       (0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ        (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD        (0x1 <<  0) // (EMAC) Speed.
-#define AT91C_EMAC_FD         (0x1 <<  1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME     (0x1 <<  3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF        (0x1 <<  4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC        (0x1 <<  5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI        (0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        (0x1 <<  7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG        (0x1 <<  8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE        (0x1 <<  9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK        (0x3 << 10) // (EMAC)
-#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE        (0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF       (0x3 << 14) // (EMAC)
-#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      (0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS     (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR      (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_MDIO       (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_IDLE       (0x1 <<  2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR        (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_COL        (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RLES       (0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TGO        (0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       (0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_UND        (0x1 <<  6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA        (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_REC        (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_OVR        (0x1 <<  2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD        (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_RCOMP      (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RXUBR      (0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TXUBR      (0x1 <<  3) // (EMAC)
-#define AT91C_EMAC_TUNDR      (0x1 <<  4) // (EMAC)
-#define AT91C_EMAC_RLEX       (0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_TXERR      (0x1 <<  6) // (EMAC)
-#define AT91C_EMAC_TCOMP      (0x1 <<  7) // (EMAC)
-#define AT91C_EMAC_LINK       (0x1 <<  9) // (EMAC)
-#define AT91C_EMAC_ROVR       (0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP      (0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE       (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ        (0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA       (0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_CODE       (0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA       (0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA       (0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW         (0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF        (0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII       (0x1 <<  0) // (EMAC) Reduce MII
-#define AT91C_EMAC_CLKEN      (0x1 <<  1) // (EMAC) Clock Enable
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP         (0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF     (0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_PARTREF    (0xFFFF << 16) // (EMAC)
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	//
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   (AT91_CAST(AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    (AT91_CAST(AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   (AT91_CAST(AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    (AT91_CAST(AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    (AT91_CAST(AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   (AT91_CAST(AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  (AT91_CAST(AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  (AT91_CAST(AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  (AT91_CAST(AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   (AT91_CAST(AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   (AT91_CAST(AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   (AT91_CAST(AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   (AT91_CAST(AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    (AT91_CAST(AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   (AT91_CAST(AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   (AT91_CAST(AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    (AT91_CAST(AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    (AT91_CAST(AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    (AT91_CAST(AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  (AT91_CAST(AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  (AT91_CAST(AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  (AT91_CAST(AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  (AT91_CAST(AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  (AT91_CAST(AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  (AT91_CAST(AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  (AT91_CAST(AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  (AT91_CAST(AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  (AT91_CAST(AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  (AT91_CAST(AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  (AT91_CAST(AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  (AT91_CAST(AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  (AT91_CAST(AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  (AT91_CAST(AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  (AT91_CAST(AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  (AT91_CAST(AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  (AT91_CAST(AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  (AT91_CAST(AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  (AT91_CAST(AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  (AT91_CAST(AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  (AT91_CAST(AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  (AT91_CAST(AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  (AT91_CAST(AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  (AT91_CAST(AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  (AT91_CAST(AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  (AT91_CAST(AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  (AT91_CAST(AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  (AT91_CAST(AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  (AT91_CAST(AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     (AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     (AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     (AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    (AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    (AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       (AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       (AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       (AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       (AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       (AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     (AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     (AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     (AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     (AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     (AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     (AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     (AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     (AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     (AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    (AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     (AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     (AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     (AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     (AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     (AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      (AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     (AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     (AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     (AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     (AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ( 1) // System Peripheral
-#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ( 6) // USART 0
-#define AT91C_ID_US1    ( 7) // USART 1
-#define AT91C_ID_SSC    ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC   (10) // PWM Controller
-#define AT91C_ID_UDP    (11) // USB Device Port
-#define AT91C_ID_TC0    (12) // Timer Counter 0
-#define AT91C_ID_TC1    (13) // Timer Counter 1
-#define AT91C_ID_TC2    (14) // Timer Counter 2
-#define AT91C_ID_CAN    (15) // Control Area Network Controller
-#define AT91C_ID_EMAC   (16) // Ethernet MAC
-#define AT91C_ID_ADC    (17) // Analog-to-Digital Converter
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0   (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT   (0xC003FFFF) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      (AT91_CAST(AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        (AT91_CAST(AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  (AT91_CAST(AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      (AT91_CAST(AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       (AT91_CAST(AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       (AT91_CAST(AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       (AT91_CAST(AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      (AT91_CAST(AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM	 (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 (0x00008000) // Internal SRAM size in byte (32 Kbytes)
-// IFLASH
-#define AT91C_IFLASH	 (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE	 (0x00020000) // Internal FLASH size in byte (128 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE	 (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE	 (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES	 (512) // Internal FLASH Number of Pages: 512 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (8) // Internal FLASH Number of Lock Bits: 8 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h
deleted file mode 100644
index 20b0e747d..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h
+++ /dev/null
@@ -1,2918 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  Copyright (c) 2006, Atmel Corporation
-// 
-//  All rights reserved.
-// 
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions are met:
-// 
-//  - Redistributions of source code must retain the above copyright notice,
-//  this list of conditions and the disclaimer below.
-// 
-//  - Redistributions in binary form must reproduce the above copyright notice,
-//  this list of conditions and the disclaimer below in the documentation and/or
-//  other materials provided with the distribution. 
-// 
-//  Atmel's name may not be used to endorse or promote products derived from
-//  this software without specific prior written permission. 
-//  
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X256.h
-// Object              : AT91SAM7X256 definitions
-// Generated           : AT91 SW Application Group  06/19/2007 (15:41:06)
-// 
-// CVS Reference       : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Wed Feb  2 15:48:15 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 14:00:19 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference       : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:40:38 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference       : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005//
-// CVS Reference       : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006//
-// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X256_H
-#define AT91SAM7X256_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	// 
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	// 
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	// 
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	// 
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	// 
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	// 
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	// 
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	// 
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	// 
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	// 
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	// 
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	// 
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	// 
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	// 
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	// 
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	// 
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	// 
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[5]; 	// 
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved27[5]; 	// 
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	// 
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	// 
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	// 
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
-#define CKGR_PLLR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN     (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-#define AT91C_VREG_PSTDBY     (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	// 
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR         (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR          (AT91_CAST(AT91_REG *) 	0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR          (AT91_CAST(AT91_REG *) 	0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR          (AT91_CAST(AT91_REG *) 	0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB          (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD       (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY         (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          (0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD         (0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY     (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	// 
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
-#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
-#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	// 
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
-#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
-#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
-#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	// 
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
-#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG         (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
-#define 	AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define 	AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define 	AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STOP        (0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0         (0x1 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_CP1         (0x1 <<  9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	// 
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved2[50]; 	// 
-	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
-	AT91_REG	 TWI_RCR; 	// Receive Counter Register
-	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
-	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
-#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP      (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI) 
-#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI) 
-#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI) 
-#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI) 
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR        (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR      (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR      (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR      (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved        (AT91_CAST(AT91_REG *) 	0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY       (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD       (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT       (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD       (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	// 
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA        (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS        (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR         (AT91_CAST(AT91_REG *) 	0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	// 
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         (0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
-#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
-#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
-#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
-#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
-#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         (0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	// 
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-#else
-#define CAN_MMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (CAN_MMR) MailBox Mode Register
-#define CAN_MAM         (AT91_CAST(AT91_REG *) 	0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
-#define CAN_MID         (AT91_CAST(AT91_REG *) 	0x00000008) // (CAN_MID) MailBox ID Register
-#define CAN_MFID        (AT91_CAST(AT91_REG *) 	0x0000000C) // (CAN_MFID) MailBox Family ID Register
-#define CAN_MSR         (AT91_CAST(AT91_REG *) 	0x00000010) // (CAN_MSR) MailBox Status Register
-#define CAN_MDL         (AT91_CAST(AT91_REG *) 	0x00000014) // (CAN_MDL) MailBox Data Low Register
-#define CAN_MDH         (AT91_CAST(AT91_REG *) 	0x00000018) // (CAN_MDH) MailBox Data High Register
-#define CAN_MCR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (CAN_MCR) MailBox Control Register
-
-#endif
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-#define AT91C_CAN_MTIMEMARK   (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB) 
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-#define AT91C_CAN_MIDvB       (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-#define AT91C_CAN_MTIMESTAMP  (0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-#define AT91C_CAN_MACR        (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	// 
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-#else
-#define CAN_MR          (AT91_CAST(AT91_REG *) 	0x00000000) // (CAN_MR) Mode Register
-#define CAN_IER         (AT91_CAST(AT91_REG *) 	0x00000004) // (CAN_IER) Interrupt Enable Register
-#define CAN_IDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (CAN_IDR) Interrupt Disable Register
-#define CAN_IMR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (CAN_IMR) Interrupt Mask Register
-#define CAN_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (CAN_SR) Status Register
-#define CAN_BR          (AT91_CAST(AT91_REG *) 	0x00000014) // (CAN_BR) Baudrate Register
-#define CAN_TIM         (AT91_CAST(AT91_REG *) 	0x00000018) // (CAN_TIM) Timer Register
-#define CAN_TIMESTP     (AT91_CAST(AT91_REG *) 	0x0000001C) // (CAN_TIMESTP) Time Stamp Register
-#define CAN_ECR         (AT91_CAST(AT91_REG *) 	0x00000020) // (CAN_ECR) Error Counter Register
-#define CAN_TCR         (AT91_CAST(AT91_REG *) 	0x00000024) // (CAN_TCR) Transfer Command Register
-#define CAN_ACR         (AT91_CAST(AT91_REG *) 	0x00000028) // (CAN_ACR) Abort Command Register
-#define CAN_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (CAN_VR) Version Register
-
-#endif
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-#define AT91C_CAN_CANEN       (0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      (0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        (0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-#define AT91C_CAN_MB0         (0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         (0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         (0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         (0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         (0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         (0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         (0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         (0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         (0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         (0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-#define AT91C_CAN_RBSY        (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-#define AT91C_CAN_PHASE2      (0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      (0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      (0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-#define AT91C_CAN_TIMER       (0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-#define AT91C_CAN_REC         (0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-#define AT91C_CAN_TIMRST      (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_NCR; 	// Network Control Register
-	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
-	AT91_REG	 EMAC_NSR; 	// Network Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 EMAC_PTR; 	// Pause Time Register
-	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
-	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
-	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
-	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
-	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
-	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
-	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
-	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
-	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
-	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
-	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
-	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
-	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
-	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
-	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
-	AT91_REG	 Reserved1[13]; 	// 
-	AT91_REG	 EMAC_REV; 	// Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-#else
-#define EMAC_NCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (EMAC_NCR) Network Control Register
-#define EMAC_NCFGR      (AT91_CAST(AT91_REG *) 	0x00000004) // (EMAC_NCFGR) Network Configuration Register
-#define EMAC_NSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (EMAC_NSR) Network Status Register
-#define EMAC_TSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (EMAC_TSR) Transmit Status Register
-#define EMAC_RBQP       (AT91_CAST(AT91_REG *) 	0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
-#define EMAC_TBQP       (AT91_CAST(AT91_REG *) 	0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
-#define EMAC_RSR        (AT91_CAST(AT91_REG *) 	0x00000020) // (EMAC_RSR) Receive Status Register
-#define EMAC_ISR        (AT91_CAST(AT91_REG *) 	0x00000024) // (EMAC_ISR) Interrupt Status Register
-#define EMAC_IER        (AT91_CAST(AT91_REG *) 	0x00000028) // (EMAC_IER) Interrupt Enable Register
-#define EMAC_IDR        (AT91_CAST(AT91_REG *) 	0x0000002C) // (EMAC_IDR) Interrupt Disable Register
-#define EMAC_IMR        (AT91_CAST(AT91_REG *) 	0x00000030) // (EMAC_IMR) Interrupt Mask Register
-#define EMAC_MAN        (AT91_CAST(AT91_REG *) 	0x00000034) // (EMAC_MAN) PHY Maintenance Register
-#define EMAC_PTR        (AT91_CAST(AT91_REG *) 	0x00000038) // (EMAC_PTR) Pause Time Register
-#define EMAC_PFR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (EMAC_PFR) Pause Frames received Register
-#define EMAC_FTO        (AT91_CAST(AT91_REG *) 	0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
-#define EMAC_SCF        (AT91_CAST(AT91_REG *) 	0x00000044) // (EMAC_SCF) Single Collision Frame Register
-#define EMAC_MCF        (AT91_CAST(AT91_REG *) 	0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
-#define EMAC_FRO        (AT91_CAST(AT91_REG *) 	0x0000004C) // (EMAC_FRO) Frames Received OK Register
-#define EMAC_FCSE       (AT91_CAST(AT91_REG *) 	0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
-#define EMAC_ALE        (AT91_CAST(AT91_REG *) 	0x00000054) // (EMAC_ALE) Alignment Error Register
-#define EMAC_DTF        (AT91_CAST(AT91_REG *) 	0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
-#define EMAC_LCOL       (AT91_CAST(AT91_REG *) 	0x0000005C) // (EMAC_LCOL) Late Collision Register
-#define EMAC_ECOL       (AT91_CAST(AT91_REG *) 	0x00000060) // (EMAC_ECOL) Excessive Collision Register
-#define EMAC_TUND       (AT91_CAST(AT91_REG *) 	0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
-#define EMAC_CSE        (AT91_CAST(AT91_REG *) 	0x00000068) // (EMAC_CSE) Carrier Sense Error Register
-#define EMAC_RRE        (AT91_CAST(AT91_REG *) 	0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
-#define EMAC_ROV        (AT91_CAST(AT91_REG *) 	0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
-#define EMAC_RSE        (AT91_CAST(AT91_REG *) 	0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
-#define EMAC_ELE        (AT91_CAST(AT91_REG *) 	0x00000078) // (EMAC_ELE) Excessive Length Errors Register
-#define EMAC_RJA        (AT91_CAST(AT91_REG *) 	0x0000007C) // (EMAC_RJA) Receive Jabbers Register
-#define EMAC_USF        (AT91_CAST(AT91_REG *) 	0x00000080) // (EMAC_USF) Undersize Frames Register
-#define EMAC_STE        (AT91_CAST(AT91_REG *) 	0x00000084) // (EMAC_STE) SQE Test Error Register
-#define EMAC_RLE        (AT91_CAST(AT91_REG *) 	0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
-#define EMAC_TPF        (AT91_CAST(AT91_REG *) 	0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
-#define EMAC_HRB        (AT91_CAST(AT91_REG *) 	0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
-#define EMAC_HRT        (AT91_CAST(AT91_REG *) 	0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
-#define EMAC_SA1L       (AT91_CAST(AT91_REG *) 	0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H       (AT91_CAST(AT91_REG *) 	0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L       (AT91_CAST(AT91_REG *) 	0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H       (AT91_CAST(AT91_REG *) 	0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L       (AT91_CAST(AT91_REG *) 	0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H       (AT91_CAST(AT91_REG *) 	0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L       (AT91_CAST(AT91_REG *) 	0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H       (AT91_CAST(AT91_REG *) 	0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID        (AT91_CAST(AT91_REG *) 	0x000000B8) // (EMAC_TID) Type ID Checking Register
-#define EMAC_TPQ        (AT91_CAST(AT91_REG *) 	0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
-#define EMAC_USRIO      (AT91_CAST(AT91_REG *) 	0x000000C0) // (EMAC_USRIO) USER Input/Output Register
-#define EMAC_WOL        (AT91_CAST(AT91_REG *) 	0x000000C4) // (EMAC_WOL) Wake On LAN Register
-#define EMAC_REV        (AT91_CAST(AT91_REG *) 	0x000000FC) // (EMAC_REV) Revision Register
-
-#endif
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB         (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        (0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE         (0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE         (0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE        (0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CLRSTAT    (0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_INCSTAT    (0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WESTAT     (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP         (0x1 <<  8) // (EMAC) Back pressure. 
-#define AT91C_EMAC_TSTART     (0x1 <<  9) // (EMAC) Start Transmission. 
-#define AT91C_EMAC_THALT      (0x1 << 10) // (EMAC) Transmission Halt. 
-#define AT91C_EMAC_TPFR       (0x1 << 11) // (EMAC) Transmit pause frame 
-#define AT91C_EMAC_TZQ        (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD        (0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD         (0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_JFRAME     (0x1 <<  3) // (EMAC) Jumbo Frames. 
-#define AT91C_EMAC_CAF        (0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC        (0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI        (0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        (0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG        (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE        (0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK        (0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        (0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PAE        (0x1 << 13) // (EMAC) 
-#define AT91C_EMAC_RBOF       (0x3 << 14) // (EMAC) 
-#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      (0x1 << 18) // (EMAC) 
-#define AT91C_EMAC_IRXFCS     (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_LINKR      (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_MDIO       (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE       (0x1 <<  2) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-#define AT91C_EMAC_UBR        (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL        (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLES       (0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TGO        (0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       (0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND        (0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA        (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC        (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_OVR        (0x1 <<  2) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_MFD        (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOMP      (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RXUBR      (0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXUBR      (0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUNDR      (0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RLEX       (0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TXERR      (0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOMP      (0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_LINK       (0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR       (0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP      (0x1 << 11) // (EMAC) 
-#define AT91C_EMAC_PFRE       (0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PTZ        (0x1 << 13) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA       (0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE       (0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA       (0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA       (0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW         (0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_SOF        (0x3 << 30) // (EMAC) 
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-#define AT91C_EMAC_RMII       (0x1 <<  0) // (EMAC) Reduce MII
-#define AT91C_EMAC_CLKEN      (0x1 <<  1) // (EMAC) Clock Enable
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-#define AT91C_EMAC_IP         (0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-#define AT91C_EMAC_REVREF     (0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_PARTREF    (0xFFFF << 16) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ========== 
-#define AT91C_VREG_MR   (AT91_CAST(AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_ASR    (AT91_CAST(AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   (AT91_CAST(AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    (AT91_CAST(AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    (AT91_CAST(AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ========== 
-#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ========== 
-#define AT91C_SPI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   (AT91_CAST(AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  (AT91_CAST(AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  (AT91_CAST(AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  (AT91_CAST(AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ========== 
-#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ========== 
-#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   (AT91_CAST(AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   (AT91_CAST(AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR   (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ========== 
-#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ========== 
-#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ========== 
-#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ========== 
-#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ========== 
-#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ========== 
-#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ========== 
-#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ========== 
-#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ========== 
-#define AT91C_CAN_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   (AT91_CAST(AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   (AT91_CAST(AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    (AT91_CAST(AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   (AT91_CAST(AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   (AT91_CAST(AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    (AT91_CAST(AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    (AT91_CAST(AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    (AT91_CAST(AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  (AT91_CAST(AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  (AT91_CAST(AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  (AT91_CAST(AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  (AT91_CAST(AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  (AT91_CAST(AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  (AT91_CAST(AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  (AT91_CAST(AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  (AT91_CAST(AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  (AT91_CAST(AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  (AT91_CAST(AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  (AT91_CAST(AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  (AT91_CAST(AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  (AT91_CAST(AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  (AT91_CAST(AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  (AT91_CAST(AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  (AT91_CAST(AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  (AT91_CAST(AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  (AT91_CAST(AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  (AT91_CAST(AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  (AT91_CAST(AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  (AT91_CAST(AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  (AT91_CAST(AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  (AT91_CAST(AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  (AT91_CAST(AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  (AT91_CAST(AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  (AT91_CAST(AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  (AT91_CAST(AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  (AT91_CAST(AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  (AT91_CAST(AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     (AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     (AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     (AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    (AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    (AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       (AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       (AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       (AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       (AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       (AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     (AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     (AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     (AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     (AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     (AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     (AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     (AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     (AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     (AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    (AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     (AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     (AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     (AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     (AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     (AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      (AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     (AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     (AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     (AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     (AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ( 1) // System Peripheral
-#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ( 6) // USART 0
-#define AT91C_ID_US1    ( 7) // USART 1
-#define AT91C_ID_SSC    ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC   (10) // PWM Controller
-#define AT91C_ID_UDP    (11) // USB Device Port
-#define AT91C_ID_TC0    (12) // Timer Counter 0
-#define AT91C_ID_TC1    (13) // Timer Counter 1
-#define AT91C_ID_TC2    (14) // Timer Counter 2
-#define AT91C_ID_CAN    (15) // Control Area Network Controller
-#define AT91C_ID_EMAC   (16) // Ethernet MAC
-#define AT91C_ID_ADC    (17) // Analog-to-Digital Converter
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0   (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT   (0xC003FFFF) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      (AT91_CAST(AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        (AT91_CAST(AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  (AT91_CAST(AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      (AT91_CAST(AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       (AT91_CAST(AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       (AT91_CAST(AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       (AT91_CAST(AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      (AT91_CAST(AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM	 (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 (0x00010000) // Internal SRAM size in byte (64 Kbytes)
-// IFLASH
-#define AT91C_IFLASH	 (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE	 (0x00040000) // Internal FLASH size in byte (256 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE	 (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE	 (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES	 (1024) // Internal FLASH Number of Pages: 1024 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (16) // Internal FLASH Number of Lock Bits: 16 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h
deleted file mode 100644
index 7c03a0db4..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h
+++ /dev/null
@@ -1,2984 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  Copyright (c) 2006, Atmel Corporation
-//
-//  All rights reserved.
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions are met:
-//
-//  - Redistributions of source code must retain the above copyright notice,
-//  this list of conditions and the disclaimer below.
-//
-//  Atmel's name may not be used to endorse or promote products derived from
-//  this software without specific prior written permission.
-//
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X512.h
-// Object              : AT91SAM7X512 definitions
-// Generated           : AT91 SW Application Group  07/07/2008 (16:15:41)
-//
-// CVS Reference       : /AT91SAM7X512.pl/1.7/Wed Aug 30 14:09:17 2006//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Wed Feb  2 15:48:15 2005//
-// CVS Reference       : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 14:00:19 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference       : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:40:38 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference       : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008//
-// CVS Reference       : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X512_H
-#define AT91SAM7X512_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	//
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	//
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	//
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	//
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	//
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	//
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	//
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	//
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	//
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	//
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	//
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	//
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	//
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	//
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	//
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	//
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	//
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	//
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[5]; 	//
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved27[5]; 	//
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	//
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	//
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	//
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	//
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	//
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
-#define CKGR_PLLR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	//
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	//
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN     (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Embedded Flash Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EFC {
-	AT91_REG	 EFC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 EFC_FCR; 	// MC Flash Command Register
-	AT91_REG	 EFC_FSR; 	// MC Flash Status Register
-	AT91_REG	 EFC_VR; 	// MC Flash Version Register
-} AT91S_EFC, *AT91PS_EFC;
-#else
-#define MC_FMR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_FCR) MC Flash Command Register
-#define MC_FSR          (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_FSR) MC Flash Status Register
-#define MC_VR           (AT91_CAST(AT91_REG *) 	0x0000000C) // (MC_VR) MC Flash Version Register
-
-#endif
-// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         (0x1 <<  0) // (EFC) Flash Ready
-#define AT91C_MC_LOCKE        (0x1 <<  2) // (EFC) Lock Error
-#define AT91C_MC_PROGE        (0x1 <<  3) // (EFC) Programming Error
-#define AT91C_MC_NEBP         (0x1 <<  7) // (EFC) No Erase Before Programming
-#define AT91C_MC_FWS          (0x3 <<  8) // (EFC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (EFC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (EFC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (EFC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (EFC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         (0xFF << 16) // (EFC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register --------
-#define AT91C_MC_FCMD         (0xF <<  0) // (EFC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (EFC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (EFC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (EFC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (EFC) Set Security Bit.
-#define AT91C_MC_PAGEN        (0x3FF <<  8) // (EFC) Page Number
-#define AT91C_MC_KEY          (0xFF << 24) // (EFC) Writing Protect Key
-// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     (0x1 <<  4) // (EFC) Security Bit Status
-#define AT91C_MC_GPNVM0       (0x1 <<  8) // (EFC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       (0x1 <<  9) // (EFC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       (0x1 << 10) // (EFC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       (0x1 << 11) // (EFC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       (0x1 << 12) // (EFC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       (0x1 << 13) // (EFC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       (0x1 << 14) // (EFC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       (0x1 << 15) // (EFC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       (0x1 << 16) // (EFC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       (0x1 << 17) // (EFC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       (0x1 << 18) // (EFC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       (0x1 << 19) // (EFC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       (0x1 << 20) // (EFC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       (0x1 << 21) // (EFC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       (0x1 << 22) // (EFC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       (0x1 << 23) // (EFC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       (0x1 << 24) // (EFC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       (0x1 << 25) // (EFC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      (0x1 << 26) // (EFC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      (0x1 << 27) // (EFC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      (0x1 << 28) // (EFC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      (0x1 << 29) // (EFC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      (0x1 << 30) // (EFC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      (0x1 << 31) // (EFC) Sector 15 Lock Status
-// -------- EFC_VR : (EFC Offset: 0xc) EFC version register --------
-#define AT91C_EFC_VERSION     (0xFFF <<  0) // (EFC) EFC version number
-#define AT91C_EFC_MFN         (0x7 << 16) // (EFC) EFC MFN
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 MC_PUIA[16]; 	// MC Protection Unit Area
-	AT91_REG	 MC_PUP; 	// MC Protection Unit Peripherals
-	AT91_REG	 MC_PUER; 	// MC Protection Unit Enable Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 MC0_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC0_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC0_FSR; 	// MC Flash Status Register
-	AT91_REG	 MC0_VR; 	// MC Flash Version Register
-	AT91_REG	 MC1_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC1_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC1_FSR; 	// MC Flash Status Register
-	AT91_REG	 MC1_VR; 	// MC Flash Version Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR         (AT91_CAST(AT91_REG *) 	0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_PUIA         (AT91_CAST(AT91_REG *) 	0x00000010) // (MC_PUIA) MC Protection Unit Area
-#define MC_PUP          (AT91_CAST(AT91_REG *) 	0x00000050) // (MC_PUP) MC Protection Unit Peripherals
-#define MC_PUER         (AT91_CAST(AT91_REG *) 	0x00000054) // (MC_PUER) MC Protection Unit Enable Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_MPU          (0x1 <<  2) // (MC) Memory protection Unit Abort Status
-#define AT91C_MC_ABTSZ        (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
-#define AT91C_MC_PROT         (0x3 <<  0) // (MC) Protection
-#define 	AT91C_MC_PROT_PNAUNA               (0x0) // (MC) Privilege: No Access, User: No Access
-#define 	AT91C_MC_PROT_PRWUNA               (0x1) // (MC) Privilege: Read/Write, User: No Access
-#define 	AT91C_MC_PROT_PRWURO               (0x2) // (MC) Privilege: Read/Write, User: Read Only
-#define 	AT91C_MC_PROT_PRWURW               (0x3) // (MC) Privilege: Read/Write, User: Read/Write
-#define AT91C_MC_SIZE         (0xF <<  4) // (MC) Internal Area Size
-#define 	AT91C_MC_SIZE_1KB                  (0x0 <<  4) // (MC) Area size 1KByte
-#define 	AT91C_MC_SIZE_2KB                  (0x1 <<  4) // (MC) Area size 2KByte
-#define 	AT91C_MC_SIZE_4KB                  (0x2 <<  4) // (MC) Area size 4KByte
-#define 	AT91C_MC_SIZE_8KB                  (0x3 <<  4) // (MC) Area size 8KByte
-#define 	AT91C_MC_SIZE_16KB                 (0x4 <<  4) // (MC) Area size 16KByte
-#define 	AT91C_MC_SIZE_32KB                 (0x5 <<  4) // (MC) Area size 32KByte
-#define 	AT91C_MC_SIZE_64KB                 (0x6 <<  4) // (MC) Area size 64KByte
-#define 	AT91C_MC_SIZE_128KB                (0x7 <<  4) // (MC) Area size 128KByte
-#define 	AT91C_MC_SIZE_256KB                (0x8 <<  4) // (MC) Area size 256KByte
-#define 	AT91C_MC_SIZE_512KB                (0x9 <<  4) // (MC) Area size 512KByte
-#define 	AT91C_MC_SIZE_1MB                  (0xA <<  4) // (MC) Area size 1MByte
-#define 	AT91C_MC_SIZE_2MB                  (0xB <<  4) // (MC) Area size 2MByte
-#define 	AT91C_MC_SIZE_4MB                  (0xC <<  4) // (MC) Area size 4MByte
-#define 	AT91C_MC_SIZE_8MB                  (0xD <<  4) // (MC) Area size 8MByte
-#define 	AT91C_MC_SIZE_16MB                 (0xE <<  4) // (MC) Area size 16MByte
-#define 	AT91C_MC_SIZE_64MB                 (0xF <<  4) // (MC) Area size 64MByte
-#define AT91C_MC_BA           (0x3FFFF << 10) // (MC) Internal Area Base Address
-// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
-// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
-#define AT91C_MC_PUEB         (0x1 <<  0) // (MC) Protection Unit enable Bit
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	//
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	//
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
-#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
-#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	//
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	//
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
-#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
-#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
-#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	//
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	//
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	//
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
-#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG         (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
-#define 	AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define 	AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define 	AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STOP        (0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0         (0x1 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_CP1         (0x1 <<  9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	//
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved2[50]; 	//
-	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
-	AT91_REG	 TWI_RCR; 	// Receive Counter Register
-	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
-	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
-#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR        (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR      (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR      (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR      (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved        (AT91_CAST(AT91_REG *) 	0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	//
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA        (AT91_CAST(AT91_REG *) 	0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS        (AT91_CAST(AT91_REG *) 	0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR         (AT91_CAST(AT91_REG *) 	0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	//
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	//
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	//
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	//
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	//
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         (0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP)
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
-#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
-#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
-#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
-#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
-#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	//
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	//
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	//
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-#else
-#define CAN_MMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (CAN_MMR) MailBox Mode Register
-#define CAN_MAM         (AT91_CAST(AT91_REG *) 	0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
-#define CAN_MID         (AT91_CAST(AT91_REG *) 	0x00000008) // (CAN_MID) MailBox ID Register
-#define CAN_MFID        (AT91_CAST(AT91_REG *) 	0x0000000C) // (CAN_MFID) MailBox Family ID Register
-#define CAN_MSR         (AT91_CAST(AT91_REG *) 	0x00000010) // (CAN_MSR) MailBox Status Register
-#define CAN_MDL         (AT91_CAST(AT91_REG *) 	0x00000014) // (CAN_MDL) MailBox Data Low Register
-#define CAN_MDH         (AT91_CAST(AT91_REG *) 	0x00000018) // (CAN_MDH) MailBox Data High Register
-#define CAN_MCR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (CAN_MCR) MailBox Control Register
-
-#endif
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK   (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB)
-#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB       (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP  (0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR        (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	//
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	//
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-#else
-#define CAN_MR          (AT91_CAST(AT91_REG *) 	0x00000000) // (CAN_MR) Mode Register
-#define CAN_IER         (AT91_CAST(AT91_REG *) 	0x00000004) // (CAN_IER) Interrupt Enable Register
-#define CAN_IDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (CAN_IDR) Interrupt Disable Register
-#define CAN_IMR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (CAN_IMR) Interrupt Mask Register
-#define CAN_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (CAN_SR) Status Register
-#define CAN_BR          (AT91_CAST(AT91_REG *) 	0x00000014) // (CAN_BR) Baudrate Register
-#define CAN_TIM         (AT91_CAST(AT91_REG *) 	0x00000018) // (CAN_TIM) Timer Register
-#define CAN_TIMESTP     (AT91_CAST(AT91_REG *) 	0x0000001C) // (CAN_TIMESTP) Time Stamp Register
-#define CAN_ECR         (AT91_CAST(AT91_REG *) 	0x00000020) // (CAN_ECR) Error Counter Register
-#define CAN_TCR         (AT91_CAST(AT91_REG *) 	0x00000024) // (CAN_TCR) Transfer Command Register
-#define CAN_ACR         (AT91_CAST(AT91_REG *) 	0x00000028) // (CAN_ACR) Abort Command Register
-#define CAN_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (CAN_VR) Version Register
-
-#endif
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN       (0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      (0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        (0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0         (0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         (0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         (0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         (0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         (0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         (0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         (0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         (0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         (0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         (0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY        (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2      (0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      (0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      (0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER       (0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC         (0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST      (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_NCR; 	// Network Control Register
-	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
-	AT91_REG	 EMAC_NSR; 	// Network Status Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 EMAC_PTR; 	// Pause Time Register
-	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
-	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
-	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
-	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
-	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
-	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
-	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
-	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
-	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
-	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
-	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
-	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
-	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
-	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
-	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
-	AT91_REG	 Reserved1[13]; 	//
-	AT91_REG	 EMAC_REV; 	// Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-#else
-#define EMAC_NCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (EMAC_NCR) Network Control Register
-#define EMAC_NCFGR      (AT91_CAST(AT91_REG *) 	0x00000004) // (EMAC_NCFGR) Network Configuration Register
-#define EMAC_NSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (EMAC_NSR) Network Status Register
-#define EMAC_TSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (EMAC_TSR) Transmit Status Register
-#define EMAC_RBQP       (AT91_CAST(AT91_REG *) 	0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
-#define EMAC_TBQP       (AT91_CAST(AT91_REG *) 	0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
-#define EMAC_RSR        (AT91_CAST(AT91_REG *) 	0x00000020) // (EMAC_RSR) Receive Status Register
-#define EMAC_ISR        (AT91_CAST(AT91_REG *) 	0x00000024) // (EMAC_ISR) Interrupt Status Register
-#define EMAC_IER        (AT91_CAST(AT91_REG *) 	0x00000028) // (EMAC_IER) Interrupt Enable Register
-#define EMAC_IDR        (AT91_CAST(AT91_REG *) 	0x0000002C) // (EMAC_IDR) Interrupt Disable Register
-#define EMAC_IMR        (AT91_CAST(AT91_REG *) 	0x00000030) // (EMAC_IMR) Interrupt Mask Register
-#define EMAC_MAN        (AT91_CAST(AT91_REG *) 	0x00000034) // (EMAC_MAN) PHY Maintenance Register
-#define EMAC_PTR        (AT91_CAST(AT91_REG *) 	0x00000038) // (EMAC_PTR) Pause Time Register
-#define EMAC_PFR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (EMAC_PFR) Pause Frames received Register
-#define EMAC_FTO        (AT91_CAST(AT91_REG *) 	0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
-#define EMAC_SCF        (AT91_CAST(AT91_REG *) 	0x00000044) // (EMAC_SCF) Single Collision Frame Register
-#define EMAC_MCF        (AT91_CAST(AT91_REG *) 	0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
-#define EMAC_FRO        (AT91_CAST(AT91_REG *) 	0x0000004C) // (EMAC_FRO) Frames Received OK Register
-#define EMAC_FCSE       (AT91_CAST(AT91_REG *) 	0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
-#define EMAC_ALE        (AT91_CAST(AT91_REG *) 	0x00000054) // (EMAC_ALE) Alignment Error Register
-#define EMAC_DTF        (AT91_CAST(AT91_REG *) 	0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
-#define EMAC_LCOL       (AT91_CAST(AT91_REG *) 	0x0000005C) // (EMAC_LCOL) Late Collision Register
-#define EMAC_ECOL       (AT91_CAST(AT91_REG *) 	0x00000060) // (EMAC_ECOL) Excessive Collision Register
-#define EMAC_TUND       (AT91_CAST(AT91_REG *) 	0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
-#define EMAC_CSE        (AT91_CAST(AT91_REG *) 	0x00000068) // (EMAC_CSE) Carrier Sense Error Register
-#define EMAC_RRE        (AT91_CAST(AT91_REG *) 	0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
-#define EMAC_ROV        (AT91_CAST(AT91_REG *) 	0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
-#define EMAC_RSE        (AT91_CAST(AT91_REG *) 	0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
-#define EMAC_ELE        (AT91_CAST(AT91_REG *) 	0x00000078) // (EMAC_ELE) Excessive Length Errors Register
-#define EMAC_RJA        (AT91_CAST(AT91_REG *) 	0x0000007C) // (EMAC_RJA) Receive Jabbers Register
-#define EMAC_USF        (AT91_CAST(AT91_REG *) 	0x00000080) // (EMAC_USF) Undersize Frames Register
-#define EMAC_STE        (AT91_CAST(AT91_REG *) 	0x00000084) // (EMAC_STE) SQE Test Error Register
-#define EMAC_RLE        (AT91_CAST(AT91_REG *) 	0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
-#define EMAC_TPF        (AT91_CAST(AT91_REG *) 	0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
-#define EMAC_HRB        (AT91_CAST(AT91_REG *) 	0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
-#define EMAC_HRT        (AT91_CAST(AT91_REG *) 	0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
-#define EMAC_SA1L       (AT91_CAST(AT91_REG *) 	0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H       (AT91_CAST(AT91_REG *) 	0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L       (AT91_CAST(AT91_REG *) 	0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H       (AT91_CAST(AT91_REG *) 	0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L       (AT91_CAST(AT91_REG *) 	0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H       (AT91_CAST(AT91_REG *) 	0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L       (AT91_CAST(AT91_REG *) 	0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H       (AT91_CAST(AT91_REG *) 	0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID        (AT91_CAST(AT91_REG *) 	0x000000B8) // (EMAC_TID) Type ID Checking Register
-#define EMAC_TPQ        (AT91_CAST(AT91_REG *) 	0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
-#define EMAC_USRIO      (AT91_CAST(AT91_REG *) 	0x000000C0) // (EMAC_USRIO) USER Input/Output Register
-#define EMAC_WOL        (AT91_CAST(AT91_REG *) 	0x000000C4) // (EMAC_WOL) Wake On LAN Register
-#define EMAC_REV        (AT91_CAST(AT91_REG *) 	0x000000FC) // (EMAC_REV) Revision Register
-
-#endif
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  --------
-#define AT91C_EMAC_LB         (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        (0x1 <<  1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE         (0x1 <<  2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE         (0x1 <<  3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE        (0x1 <<  4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT    (0x1 <<  5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT    (0x1 <<  6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT     (0x1 <<  7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP         (0x1 <<  8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART     (0x1 <<  9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT      (0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR       (0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ        (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD        (0x1 <<  0) // (EMAC) Speed.
-#define AT91C_EMAC_FD         (0x1 <<  1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME     (0x1 <<  3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF        (0x1 <<  4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC        (0x1 <<  5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI        (0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        (0x1 <<  7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG        (0x1 <<  8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE        (0x1 <<  9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK        (0x3 << 10) // (EMAC)
-#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE        (0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF       (0x3 << 14) // (EMAC)
-#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      (0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS     (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR      (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_MDIO       (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_IDLE       (0x1 <<  2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR        (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_COL        (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RLES       (0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TGO        (0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       (0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_UND        (0x1 <<  6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA        (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_REC        (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_OVR        (0x1 <<  2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD        (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_RCOMP      (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RXUBR      (0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TXUBR      (0x1 <<  3) // (EMAC)
-#define AT91C_EMAC_TUNDR      (0x1 <<  4) // (EMAC)
-#define AT91C_EMAC_RLEX       (0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_TXERR      (0x1 <<  6) // (EMAC)
-#define AT91C_EMAC_TCOMP      (0x1 <<  7) // (EMAC)
-#define AT91C_EMAC_LINK       (0x1 <<  9) // (EMAC)
-#define AT91C_EMAC_ROVR       (0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP      (0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE       (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ        (0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA       (0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_CODE       (0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA       (0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA       (0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW         (0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF        (0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII       (0x1 <<  0) // (EMAC) Reduce MII
-#define AT91C_EMAC_CLKEN      (0x1 <<  1) // (EMAC) Clock Enable
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP         (0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF     (0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_PARTREF    (0xFFFF << 16) // (EMAC)
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	//
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	//
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X512
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   (AT91_CAST(AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for EFC0 peripheral ==========
-#define AT91C_EFC0_FCR  (AT91_CAST(AT91_REG *) 	0xFFFFFF64) // (EFC0) MC Flash Command Register
-#define AT91C_EFC0_FSR  (AT91_CAST(AT91_REG *) 	0xFFFFFF68) // (EFC0) MC Flash Status Register
-#define AT91C_EFC0_VR   (AT91_CAST(AT91_REG *) 	0xFFFFFF6C) // (EFC0) MC Flash Version Register
-#define AT91C_EFC0_FMR  (AT91_CAST(AT91_REG *) 	0xFFFFFF60) // (EFC0) MC Flash Mode Register
-// ========== Register definition for EFC1 peripheral ==========
-#define AT91C_EFC1_VR   (AT91_CAST(AT91_REG *) 	0xFFFFFF7C) // (EFC1) MC Flash Version Register
-#define AT91C_EFC1_FCR  (AT91_CAST(AT91_REG *) 	0xFFFFFF74) // (EFC1) MC Flash Command Register
-#define AT91C_EFC1_FSR  (AT91_CAST(AT91_REG *) 	0xFFFFFF78) // (EFC1) MC Flash Status Register
-#define AT91C_EFC1_FMR  (AT91_CAST(AT91_REG *) 	0xFFFFFF70) // (EFC1) MC Flash Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    (AT91_CAST(AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    (AT91_CAST(AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_PUP    (AT91_CAST(AT91_REG *) 	0xFFFFFF50) // (MC) MC Protection Unit Peripherals
-#define AT91C_MC_PUIA   (AT91_CAST(AT91_REG *) 	0xFFFFFF10) // (MC) MC Protection Unit Area
-#define AT91C_MC_AASR   (AT91_CAST(AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_PUER   (AT91_CAST(AT91_REG *) 	0xFFFFFF54) // (MC) MC Protection Unit Enable Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   (AT91_CAST(AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  (AT91_CAST(AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  (AT91_CAST(AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  (AT91_CAST(AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  (AT91_CAST(AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   (AT91_CAST(AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   (AT91_CAST(AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   (AT91_CAST(AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   (AT91_CAST(AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    (AT91_CAST(AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   (AT91_CAST(AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   (AT91_CAST(AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    (AT91_CAST(AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    (AT91_CAST(AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    (AT91_CAST(AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  (AT91_CAST(AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  (AT91_CAST(AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  (AT91_CAST(AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  (AT91_CAST(AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  (AT91_CAST(AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  (AT91_CAST(AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  (AT91_CAST(AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  (AT91_CAST(AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  (AT91_CAST(AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  (AT91_CAST(AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  (AT91_CAST(AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  (AT91_CAST(AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  (AT91_CAST(AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  (AT91_CAST(AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  (AT91_CAST(AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  (AT91_CAST(AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  (AT91_CAST(AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  (AT91_CAST(AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  (AT91_CAST(AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  (AT91_CAST(AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  (AT91_CAST(AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  (AT91_CAST(AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  (AT91_CAST(AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  (AT91_CAST(AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  (AT91_CAST(AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  (AT91_CAST(AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  (AT91_CAST(AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  (AT91_CAST(AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  (AT91_CAST(AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X512
-// *****************************************************************************
-#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     (AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     (AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     (AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    (AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    (AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       (AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       (AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       (AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       (AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       (AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     (AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     (AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     (AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     (AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     (AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     (AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     (AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     (AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     (AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    (AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     (AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     (AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     (AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     (AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     (AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      (AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     (AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     (AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     (AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     (AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X512
-// *****************************************************************************
-#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ( 1) // System Peripheral
-#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ( 6) // USART 0
-#define AT91C_ID_US1    ( 7) // USART 1
-#define AT91C_ID_SSC    ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC   (10) // PWM Controller
-#define AT91C_ID_UDP    (11) // USB Device Port
-#define AT91C_ID_TC0    (12) // Timer Counter 0
-#define AT91C_ID_TC1    (13) // Timer Counter 1
-#define AT91C_ID_TC2    (14) // Timer Counter 2
-#define AT91C_ID_CAN    (15) // Control Area Network Controller
-#define AT91C_ID_EMAC   (16) // Ethernet MAC
-#define AT91C_ID_ADC    (17) // Analog-to-Digital Converter
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0   (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT   (0xC003FFFF) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X512
-// *****************************************************************************
-#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      (AT91_CAST(AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_EFC0      (AT91_CAST(AT91PS_EFC) 	0xFFFFFF60) // (EFC0) Base Address
-#define AT91C_BASE_EFC1      (AT91_CAST(AT91PS_EFC) 	0xFFFFFF70) // (EFC1) Base Address
-#define AT91C_BASE_MC        (AT91_CAST(AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  (AT91_CAST(AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      (AT91_CAST(AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       (AT91_CAST(AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       (AT91_CAST(AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   (AT91_CAST(AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       (AT91_CAST(AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      (AT91_CAST(AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X512
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM	 (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 (0x00020000) // Internal SRAM size in byte (128 Kbytes)
-// IFLASH
-#define AT91C_IFLASH	 (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE	 (0x00080000) // Internal FLASH size in byte (512 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE	 (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE	 (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES	 (2048) // Internal FLASH Number of Pages: 2048 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (32) // Internal FLASH Number of Lock Bits: 32 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/aic.c b/os/hal/platforms/AT91SAM7/at91lib/aic.c
deleted file mode 100644
index 66eebf94e..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/aic.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* ----------------------------------------------------------------------------
- *         ATMEL Microcontroller Software Support  -  ROUSSET  -
- * ----------------------------------------------------------------------------
- * Copyright (c) 2006, Atmel Corporation
-
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * 
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaiimer below.
- * 
- * - Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the disclaimer below in the documentation and/or
- * other materials provided with the distribution. 
- * 
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission. 
- * 
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-//         Headers
-//------------------------------------------------------------------------------
-
-#include "aic.h"
-#include <board.h>
-
-//------------------------------------------------------------------------------
-//         Exported functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Configures the interrupt associated with the given source, using the
-/// specified mode and interrupt handler.
-/// \param source  Interrupt source to configure.
-/// \param mode  Triggering mode of the interrupt.
-/// \param handler  Interrupt handler function.
-//------------------------------------------------------------------------------
-void AIC_ConfigureIT(unsigned int source,
-                            unsigned int mode,
-                            void (*handler)( void ))
-{
-    // Disable the interrupt first
-    AT91C_BASE_AIC->AIC_IDCR = 1 << source;
-
-    // Configure mode and handler
-    AT91C_BASE_AIC->AIC_SMR[source] = mode;
-    AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler;
-
-    // Clear interrupt
-    AT91C_BASE_AIC->AIC_ICCR = 1 << source;
-}
-
-//------------------------------------------------------------------------------
-/// Enables interrupts coming from the given (unique) source.
-/// \param source  Interrupt source to enable.
-//------------------------------------------------------------------------------
-void AIC_EnableIT(unsigned int source)
-{
-    AT91C_BASE_AIC->AIC_IECR = 1 << source;
-}
-
-//------------------------------------------------------------------------------
-/// Disables interrupts coming from the given (unique) source.
-/// \param source  Interrupt source to enable.
-//------------------------------------------------------------------------------
-void AIC_DisableIT(unsigned int source)
-{
-    AT91C_BASE_AIC->AIC_IDCR = 1 << source;
-}
-
diff --git a/os/hal/platforms/AT91SAM7/at91lib/aic.h b/os/hal/platforms/AT91SAM7/at91lib/aic.h
deleted file mode 100644
index e8e52c78a..000000000
--- a/os/hal/platforms/AT91SAM7/at91lib/aic.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* ----------------------------------------------------------------------------
- *         ATMEL Microcontroller Software Support  -  ROUSSET  -
- * ----------------------------------------------------------------------------
- * Copyright (c) 2006, Atmel Corporation
-
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * 
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaiimer below.
- * 
- * - Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the disclaimer below in the documentation and/or
- * other materials provided with the distribution. 
- * 
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission. 
- * 
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \dir
-/// !Purpose
-/// 
-/// Methods and definitions for configuring interrupts using the Advanced
-/// Interrupt Controller (AIC).
-/// 
-/// !Usage
-/// -# Configure an interrupt source using AIC_ConfigureIT
-/// -# Enable or disable interrupt generation of a particular source with
-///    AIC_EnableIT and AIC_DisableIT.
-//------------------------------------------------------------------------------
-
-#ifndef AIC_H
-#define AIC_H
-
-//------------------------------------------------------------------------------
-//         Headers
-//------------------------------------------------------------------------------
-
-#include <board.h>
-
-//------------------------------------------------------------------------------
-//         Definitions
-//------------------------------------------------------------------------------
-
-#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL
-    /// Redefinition of missing constant.
-    #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE
-#endif
-
-//------------------------------------------------------------------------------
-//         Global functions
-//------------------------------------------------------------------------------
-
-extern void AIC_ConfigureIT(unsigned int source,
-                                   unsigned int mode,
-                                   void (*handler)( void ));
-
-extern void AIC_EnableIT(unsigned int source);
-
-extern void AIC_DisableIT(unsigned int source);
-
-#endif //#ifndef AIC_H
-
diff --git a/os/hal/platforms/AT91SAM7/at91sam7.h b/os/hal/platforms/AT91SAM7/at91sam7.h
deleted file mode 100644
index 0d3ce288e..000000000
--- a/os/hal/platforms/AT91SAM7/at91sam7.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-#ifndef _AT91SAM7_H_
-#define _AT91SAM7_H_
-
-/*
- * Supported platforms.
- */
-#define SAM7S64         0
-#define SAM7S128        1
-#define SAM7S256        2
-#define SAM7S512        3
-#define SAM7X128        4
-#define SAM7X256        5
-#define SAM7X512        6
-#define SAM7A3          7
-
-#ifndef SAM7_PLATFORM
-#error "SAM7 platform not defined"
-#endif
-
-#if SAM7_PLATFORM == SAM7S64
-#include "at91lib/AT91SAM7S64.h"
-#elif SAM7_PLATFORM == SAM7S128
-#include "at91lib/AT91SAM7S128.h"
-#elif SAM7_PLATFORM == SAM7S256
-#include "at91lib/AT91SAM7S256.h"
-#elif SAM7_PLATFORM == SAM7S512
-#include "at91lib/AT91SAM7S512.h"
-#elif SAM7_PLATFORM == SAM7X128
-#include "at91lib/AT91SAM7X128.h"
-#elif SAM7_PLATFORM == SAM7X256
-#include "at91lib/AT91SAM7X256.h"
-#elif SAM7_PLATFORM == SAM7X512
-#include "at91lib/AT91SAM7X512.h"
-#elif SAM7_PLATFORM == SAM7A3
-#include "at91lib/AT91SAM7A3.h"
-#else
-#error "SAM7 platform not supported"
-#endif
-
-#endif /* _AT91SAM7_H_ */
diff --git a/os/hal/platforms/AT91SAM7/at91sam7_mii.c b/os/hal/platforms/AT91SAM7/at91sam7_mii.c
deleted file mode 100644
index b64a389a2..000000000
--- a/os/hal/platforms/AT91SAM7/at91sam7_mii.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/at91sam7_mii.c
- * @brief   AT91SAM7 low level MII driver code.
- *
- * @addtogroup AT91SAM7_MII
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-#include "at91sam7_mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level MII driver initialization.
- *
- * @notapi
- */
-void miiInit(void) {
-
-}
-
-/**
- * @brief   Resets a PHY device.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void miiReset(MACDriver *macp) {
-
-  (void)macp;
-
-  /*
-   * Disables the pullups on all the pins that are latched on reset by the PHY.
-   */
-  AT91C_BASE_PIOB->PIO_PPUDR = PHY_LATCHED_PINS;
-
-#ifdef PIOB_PHY_PD_MASK
-  /*
-   * PHY power control.
-   */
-  AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD_MASK;  /* Becomes an output.       */
-  AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD_MASK;/* Default pullup disabled. */
-#if (PHY_HARDWARE == PHY_DAVICOM_9161)
-  AT91C_BASE_PIOB->PIO_CODR = PIOB_PHY_PD_MASK; /* Output to low level.     */
-#else
-  AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD_MASK; /* Output to high level.    */
-#endif
-#endif
-
-  /*
-   * PHY reset by pulsing the NRST pin.
-   */
-  AT91C_BASE_RSTC->RSTC_RMR = 0xA5000100;
-  AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST;
-  while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL))
-    ;
-}
-
-/**
- * @brief   Reads a PHY register through the MII interface.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] addr      the register address
- * @return              The register value.
- *
- * @notapi
- */
-phyreg_t miiGet(MACDriver *macp, phyaddr_t addr) {
-
-  (void)macp;
-  AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) |            /* SOF */
-                              (0b10 << 28) |            /* RW */
-                              (PHY_ADDRESS << 23) |     /* PHYA */
-                              (addr << 18) |            /* REGA */
-                              (0b10 << 16);             /* CODE */
-  while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
-    ;
-  return (phyreg_t)(AT91C_BASE_EMAC->EMAC_MAN & 0xFFFF);
-}
-
-/**
- * @brief   Writes a PHY register through the MII interface.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] addr      the register address
- * @param[in] value     the new register value
- *
- * @notapi
- */
-void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value) {
-
-  (void)macp;
-  AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) |            /* SOF */
-                              (0b01 << 28) |            /* RW */
-                              (PHY_ADDRESS << 23) |     /* PHYA */
-                              (addr << 18) |            /* REGA */
-                              (0b10 << 16) |            /* CODE */
-                              value;
-  while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
-    ;
-}
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/at91sam7_mii.h b/os/hal/platforms/AT91SAM7/at91sam7_mii.h
deleted file mode 100644
index f55db7e78..000000000
--- a/os/hal/platforms/AT91SAM7/at91sam7_mii.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/at91sam7_mii.h
- * @brief   AT91SAM7 low level MII driver header.
- *
- * @addtogroup AT91SAM7_MII
- * @{
- */
-
-#ifndef _AT91SAM7_MII_H_
-#define _AT91SAM7_MII_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define PHY_MICREL_KS8721       0
-#define PHY_DAVICOM_9161        1
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   PHY manufacturer and model.
- */
-#if !defined(PHY_HARDWARE) || defined(__DOXYGEN__)
-#define PHY_HARDWARE            PHY_MICREL_KS8721
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Pins latched by the PHY at reset.
- */
-#if PHY_HARDWARE == PHY_MICREL_KS8721
-#define PHY_ADDRESS             1
-#define PHY_ID                  MII_KS8721_ID
-#define PHY_LATCHED_PINS        (AT91C_PB4_ECRS          | AT91C_PB5_ERX0  | \
-                                 AT91C_PB6_ERX1          | AT91C_PB7_ERXER | \
-                                 AT91C_PB13_ERX2         | AT91C_PB14_ERX3 | \
-                                 AT91C_PB15_ERXDV_ECRSDV | AT91C_PB16_ECOL | \
-                                 AT91C_PIO_PB26)
-
-#elif PHY_HARDWARE == PHY_DAVICOM_9161
-#define PHY_ADDRESS             0
-#define PHY_ID                  MII_DM9161_ID
-#define PHY_LATCHED_PINS        (AT91C_PB0_ETXCK_EREFCK  | AT91C_PB4_ECRS          | \
-                                 AT91C_PB5_ERX0          | AT91C_PB6_ERX1          | \
-                                 AT91C_PB7_ERXER         | AT91C_PB13_ERX2         | \
-                                 AT91C_PB14_ERX3         | AT91C_PB15_ERXDV_ECRSDV | \
-                                 AT91C_PB16_ECOL         | AT91C_PB17_ERXCK)
-#endif /* PHY_HARDWARE */
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a PHY register value.
- */
-typedef uint16_t phyreg_t;
-
-/**
- * @brief   Type of a PHY register address.
- */
-typedef uint8_t phyaddr_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void miiInit(void);
-  void miiReset(MACDriver *macp);
-  phyreg_t miiGet(MACDriver *macp, phyaddr_t addr);
-  void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _AT91SAM7_MII_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/can_lld.c b/os/hal/platforms/AT91SAM7/can_lld.c
deleted file mode 100644
index 38cc6c166..000000000
--- a/os/hal/platforms/AT91SAM7/can_lld.c
+++ /dev/null
@@ -1,640 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,2011 Giovanni Di Sirio.
- 2012,2013 Martin Schüßler and Florian Sehl, Embedded Software Laboratory,
- RWTH Aachen University
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
- */
-
-/**
- * @file    AT91SAM7/can_lld.c
- * @brief   AT91SAM7 CAN Driver subsystem low level driver source.
- *
- * @pre     - Make sure that the Mailbox you are receiving from is holding your
- * 			  data.
- * 			- If you have more than one use the rxfull_event provided by the
- * 			  Driver.
- * 			- In order to use the Events APIs the CH_USE_EVENTS option must
- * 			  be enabled in chconf.h.
- * 			- In order to use the CAN driver the HAL_USE_CAN option must be
- * 			  enabled in halconf.h.
- * 			- Mailbox0 is used as a Transmitmailbox.
- * 			- Mailboxes 1-7 are used as receive Mailboxes.
- *
- * @addtogroup CAN
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief CAN driver identifier.
- */
-#if AT91SAM7_CAN_USE_CAN || defined(__DOXYGEN__)
-CANDriver CAND;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   CAN[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(CANIrqHandler) {
-
-  CH_IRQ_PROLOGUE();
-  can_lld_serve_interrupt(&CAND);
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-  CH_IRQ_EPILOGUE();
-}
-
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-/**
- * @brief   Handles CAN interrupts.
- *
- * @param[in] pointer to the driver that received the interrupt
- */
-
-
-void can_lld_serve_interrupt(CANDriver *canp) {
-
-  canstatus_t status;
-  chSysLockFromIsr();
-
-  status = canp->base->CAN_SR & canp->base->CAN_IMR;
-
-  /* if AT91C_CAN_WAKEUP is set, the can test was successful
-   * such that the CAN is now able to Transmit and Receive Data.
-   */
-  if ((status & AT91C_CAN_WAKEUP) == AT91C_CAN_WAKEUP) {
-	  canp->base->CAN_IDR = AT91C_CAN_WAKEUP;
-      canp->testok = AT91C_TEST_OK;
-  }
-
-  else {
-	  /* check the mailboxes (MB0-MB7) and broadcast the corresponding event.*/
-
-	    /* configure send mailbox, mailbox 0 */
-	#if CAN_USE_MB0
-	if(status & AT91C_CAN_MB0 && canp->mb[CAN_TxMB0-1]->CAN_MB_MSR & AT91C_CAN_MRDY) {
-	 canp->base->CAN_IDR = AT91C_CAN_MB0;
-	 chSemSignalI(&(canp->txsem));
-
-	}
-	#else
-	#warning You need to acivate Mailbox0 to transmit.
-	#endif
-
-	#if CAN_USE_MB1
-    if (status & AT91C_CAN_MB1 &&
-    		canp->mb[CAN_RxMB1-1]->CAN_MB_MSR & AT91C_CAN_MRDY) {
-      chSemSignalI(&(canp->rxsem));
-      chEvtBroadcastFlagsI(&(canp->rxfull_event), EVENT_MASK (CAN_RxMB1-1));
-      canp->base->CAN_IDR = AT91C_CAN_MB1;
-    }
-	#endif
-
-	#if CAN_USE_MB2
-    if (status & AT91C_CAN_MB2 &&
-    		canp->mb[CAN_RxMB2-1]->CAN_MB_MSR & AT91C_CAN_MRDY) {
-      chSemSignalI(&(canp->rxsem));
-      chEvtBroadcastFlagsI(&(canp->rxfull_event), EVENT_MASK (CAN_RxMB2-1));
-      canp->base->CAN_IDR = AT91C_CAN_MB2;
-    }
-	#endif
-
-	#if CAN_USE_MB3
-    if (status & AT91C_CAN_MB3 &&
-    		canp->mb[CAN_RxMB3-1]->CAN_MB_MSR & AT91C_CAN_MRDY) {
-      chSemSignalI(&(canp->rxsem));
-      chEvtBroadcastFlagsI(&(canp->rxfull_event), EVENT_MASK (CAN_RxMB3-1));
-      canp->base->CAN_IDR = AT91C_CAN_MB3;
-    }
-	#endif
-
-    #if CAN_USE_MB4
-    if (status & AT91C_CAN_MB4 && c
-    		anp->mb[CAN_RxMB4-1]->CAN_MB_MSR & AT91C_CAN_MRDY) {
-      chSemSignalI(&(canp->rxsem));
-      chEvtBroadcastFlagsI(&(canp->rxfull_event), EVENT_MASK (CAN_RxMB4-1));
-      canp->base->CAN_IDR = AT91C_CAN_MB4;
-    }
-	#endif
-
-	#if CAN_USE_MB5
-    if (status & AT91C_CAN_MB5 &&
-    		canp->mb[CAN_RxMB5-1]->CAN_MB_MSR & AT91C_CAN_MRDY) {
-      chSemSignalI(&(canp->rxsem));
-      chEvtBroadcastFlagsI(&(canp->rxfull_event), EVENT_MASK (CAN_RxMB5-1));
-      canp->base->CAN_IDR = AT91C_CAN_MB5;
-    }
-	#endif
-
-	#if CAN_USE_MB6
-    if (status & AT91C_CAN_MB6 &&
-    		canp->mb[CAN_RxMB6-1]->CAN_MB_MSR & AT91C_CAN_MRDY) {
-      chSemSignalI(&(canp->rxsem));
-      chEvtBroadcastFlagsI(&(canp->rxfull_event, EVENT_MASK (CAN_RxMB6-1));
-      canp->base->CAN_IDR = AT91C_CAN_MB6;
-    }
-	#endif
-
-	#if CAN_USE_MB7
-    if (status & AT91C_CAN_MB7 &&
-    		canp->mb[CAN_RxMB7-1]->CAN_MB_MSR & AT91C_CAN_MRDY) {
-      chSemSignalI(&(canp->rxsem));
-      chEvtBroadcastFlagsI(&(canp->rxfull_event), EVENT_MASK (CAN_RxMB7-1));
-      canp->base->CAN_IDR = AT91C_CAN_MB7;
-    }
-	#endif
-  }
-
-  /*check if error event is detected*/
-  if ((status & 0xFFCF0000) != 0) {
-	  /*The content of the SR register is copied unchanged in the upper
-       half word of the listener flags mask*/
-	chEvtBroadcastFlagsI(&(canp->error_event), (eventmask_t)(status&0xFFFF0000));
-  }
-
-  chSysUnlockFromIsr();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level CAN driver initialization.
- *
- * @notapi
- */
-void can_lld_init(void) {
-	/* Driver initialization.*/
-	canObjectInit(&CAND);
-
-	/*
-	* mailbox vector initialization
-	*/
-#if CAN_USE_MB0
-	CAND.mb[CAN_TxMB0-1] = AT91C_BASE_CAN_MB0;
-#endif
-#if CAN_USE_MB1
-	CAND.mb[CAN_RxMB1-1] = AT91C_BASE_CAN_MB1;
-#endif
-#if CAN_USE_MB2
-	CAND.mb[CAN_RxMB2-1] = AT91C_BASE_CAN_MB2;
-#endif
-#if CAN_USE_MB3
-	CAND.mb[CAN_RxMB3-1] = AT91C_BASE_CAN_MB3;
-#endif
-#if CAN_USE_MB4
-	CAND.mb[CAN_RxMB4-1] = AT91C_BASE_CAN_MB4;
-#endif
-#if CAN_USE_MB5
-	CAND.mb[CAN_RxMB5-1] = AT91C_BASE_CAN_MB5;
-#endif
-#if CAN_USE_MB6
-	CAND.mb[CAN_RxMB6-1] = AT91C_BASE_CAN_MB6;
-#endif
-#if CAN_USE_MB7
-	CAND.mb[CAN_RxMB7-1] = AT91C_BASE_CAN_MB7;
-#endif
-
-	/*
-	* PIO
-	*/
-	/* Disable interrupts on the pin(s)*/
-	AT91C_BASE_PIOA->PIO_IDR = AT91C_PA19_CANRX;
-	AT91C_BASE_PIOA->PIO_IDR = AT91C_PA20_CANTX;
-	/* Select peripheral function A*/
-	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA19_CANRX;
-	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA20_CANTX;
-	/* Disables the PIO from controlling the corresponding pin
-	 * (enables peripheral control of the pin)
-	 */
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA19_CANRX;
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA20_CANTX;
-	/* Disable pull up */
-	AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PA19_CANRX | AT91C_PA20_CANTX;
-
-	/* Configure the AIC for CAN interrupts */
-	AIC_ConfigureIT(AT91C_ID_CAN, AT91C_AIC_PRIOR_HIGHEST, CANIrqHandler);
-	CAND.base = AT91C_BASE_CAN;
-}
-
-/**
- * @brief   configures and starts the CAN peripheral.
- */
-static void can_startsequence(CANDriver *canp) {
-	  canp->state = CAN_STARTING;
-	  canp->testok = AT91C_TEST_NOK;
-
-	  /* clock */
-	  /* Enable clock for PIOA */
-	  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA);
-	  /* Enable the CAN controller peripheral clock */
-	  AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN);
-
-	  /* interrupts */
-
-	  /* disable all interrupts */
-	  canp->base->CAN_IDR = 0x1FFFFFFF;
-	  /* Enable the interrupt on the interrupt controller*/
-	  AIC_EnableIT(AT91C_ID_CAN);
-
-	  canp->base->CAN_BR = canp->config->br;
-
-
-	  /* configure send mailbox, mailbox 0 */
-	#if CAN_USE_MB0
-		canp->mb[CAN_TxMB0-1]->CAN_MB_MCR = 0x0;
-		canp->mb[CAN_TxMB0-1]->CAN_MB_MMR = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;
-		canp->mb[CAN_TxMB0-1]->CAN_MB_MAM = 0x00000000;
-		canp->mb[CAN_TxMB0-1]->CAN_MB_MID = AT91C_CAN_MIDE;
-		canp->mb[CAN_TxMB0-1]->CAN_MB_MDL = 0x11223344;
-		canp->mb[CAN_TxMB0-1]->CAN_MB_MDH = 0x01234567;
-		canp->mb[CAN_TxMB0-1]->CAN_MB_MCR = (AT91C_CAN_MDLC & (0x8 << 16));
-		canp->mb[CAN_TxMB0-1]->CAN_MB_MMR = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;
-	#else
-	#warning You need to acivate Mailbox0 to transmit.
-	#endif
-
-	#if CAN_USE_MB1
-		canp->mb[CAN_RxMB1-1]->CAN_MB_MCR = 0x0;
-		canp->mb[CAN_RxMB1-1]->CAN_MB_MMR = AT91C_CAN_MOT_RX | AT91C_CAN_PRIOR;
-		canp->mb[CAN_RxMB1-1]->CAN_MB_MAM = AT91C_CAN_MIDE
-				|(AT91C_CAN_MIDvB & canp->config->mb1_acceptance_mask)
-				| (AT91C_CAN_MIDvA & canp->config->mb1_acceptance_mask);
-		canp->mb[CAN_RxMB1-1]->CAN_MB_MID = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb1_can_id)
-				| (AT91C_CAN_MIDvA & canp->config->mb1_can_id);
-		canp->mb[CAN_RxMB1-1]->CAN_MB_MDL = 0x00000000;
-		canp->mb[CAN_RxMB1-1]->CAN_MB_MDH = 0x00000000;
-
-	#endif
-	#if CAN_USE_MB2
-		canp->mb[CAN_RxMB2-1]->CAN_MB_MCR = 0x0;
-		canp->mb[CAN_RxMB2-1]->CAN_MB_MMR = AT91C_CAN_MOT_RX | AT91C_CAN_PRIOR;
-		canp->mb[CAN_RxMB2-1]->CAN_MB_MAM = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb2_acceptance_mask)
-				| (AT91C_CAN_MIDvA & canp->config->mb2_acceptance_mask);
-		canp->mb[CAN_RxMB2-1]->CAN_MB_MID = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb2_can_id)
-				| (AT91C_CAN_MIDvA & canp->config->mb2_can_id);
-			canp->mb[CAN_RxMB2-1]->CAN_MB_MDL = 0x00000000;
-			canp->mb[CAN_RxMB2-1]->CAN_MB_MDH = 0x00000000;
-
-	#endif
-	#if CAN_USE_MB3
-		canp->mb[CAN_RxMB3-1]->CAN_MB_MCR = 0x0;
-		canp->mb[CAN_RxMB3-1]->CAN_MB_MMR = AT91C_CAN_MOT_RX | AT91C_CAN_PRIOR;
-		canp->mb[CAN_RxMB3-1]->CAN_MB_MAM = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb3_acceptance_mask)
-				| (AT91C_CAN_MIDvA & canp->config->mb3_acceptance_mask);
-		canp->mb[CAN_RxMB3-1]->CAN_MB_MID = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb3_can_id)
-				| (AT91C_CAN_MIDvA & canp->config->mb3_can_id);
-		canp->mb[CAN_RxMB3-1]->CAN_MB_MDL = 0x00000000;
-		canp->mb[CAN_RxMB3-1]->CAN_MB_MDH = 0x00000000;
-
-	#endif
-	#if CAN_USE_MB4
-		canp->mb[CAN_RxMB4-1]->CAN_MB_MCR = 0x0;
-		canp->mb[CAN_RxMB4-1]->CAN_MB_MMR = AT91C_CAN_MOT_RX | AT91C_CAN_PRIOR;_MAM = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb4_acceptance_mask)
-				| (AT91C_CAN_MIDvA & canp->config->mb4_acceptance_mask);
-		canp->mb[CAN_RxMB4-1]->CAN_MB_MID = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb4_can_id)
-				| (AT91C_CAN_MIDvA & canp->config->mb4_can_id);
-		canp->mb[CAN_RxMB4-1]->CAN_MB_MDL = 0x00000000;
-		canp->mb[CAN_RxMB4-1]->CAN_MB_MDH = 0x00000000;
-
-	#endif
-	#if CAN_USE_MB5
-		canp->mb[CAN_RxMB5-1]->CAN_MB_MCR = 0x0;
-		canp->mb[CAN_RxMB4-1]->CAN_MB_MMR = AT91C_CAN_MOT_RX | AT91C_CAN_PRIOR;
-		canp->mb[CAN_RxMB5-1]->CAN_MB_MAM = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb5_acceptance_mask)
-				| (AT91C_CAN_MIDvA & canp->config->mb5_acceptance_mask);
-		canp->mb[CAN_RxMB5-1]->CAN_MB_MID = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb5_can_id)
-				| (AT91C_CAN_MIDvA & canp->config->mb5_can_id);
-		canp->mb[CAN_RxMB5-1]->CAN_MB_MDL = 0x00000000;
-		canp->mb[CAN_RxMB5-1]->CAN_MB_MDH = 0x00000000;
-	#endif
-	#if CAN_USE_MB6
-		canp->mb[CAN_RxMB6-1]->CAN_MB_MCR = 0x0;
-		canp->mb[CAN_RxMB6-1]->CAN_MB_MMR = AT91C_CAN_MOT_RX | AT91C_CAN_PRIOR;
-		canp->mb[CAN_RxMB6-1]->CAN_MB_MAM = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb6_acceptance_mask)
-				| (AT91C_CAN_MIDvA & canp->config->mb6_acceptance_mask);
-		canp->mb[CAN_RxMB6-1]->CAN_MB_MID = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb6_can_id)
-				| (AT91C_CAN_MIDvA & canp->config->mb6_can_id);
-		canp->mb[CAN_RxMB6-1]->CAN_MB_MDL = 0x00000000;
-		canp->mb[CAN_RxMB6-1]->CAN_MB_MDH = 0x00000000;
-	#endif
-	#if CAN_USE_MB7
-		canp->mb[CAN_RxMB7-1]->CAN_MB_MCR = 0x0;
-		canp->mb[CAN_RxMB7-1]->CAN_MB_MMR = AT91C_CAN_MOT_RX | AT91C_CAN_PRIOR;
-		canp->mb[CAN_RxMB7-1]->CAN_MB_MAM = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb7_acceptance_mask)
-				| (AT91C_CAN_MIDvA & canp->config->mb7_acceptance_mask);
-		canp->mb[CAN_RxMB7-1]->CAN_MB_MID = AT91C_CAN_MIDE
-				| (AT91C_CAN_MIDvB & canp->config->mb7_can_id)
-				| (AT91C_CAN_MIDvA & canp->config->mb7_can_id);
-		canp->mb[CAN_RxMB7-1]->CAN_MB_MDL = 0x00000000;
-		canp->mb[CAN_RxMB7-1]->CAN_MB_MDH = 0x00000000;
-	#endif
-	    /* Enable the interrupt with all error cases */
-		canp->base->CAN_IER = AT91C_CAN_CERR	/* (CAN) CRC Error				*/
-			| AT91C_CAN_SERR 					/* (CAN) Stuffing Error			*/
-			| AT91C_CAN_BERR 					/* (CAN) Bit Error				*/
-			| AT91C_CAN_FERR					/* (CAN) Form Error				*/
-			| AT91C_CAN_AERR;					/* (CAN) Acknowledgment Error	*/
-
-	  /* Enable CAN and */
-	  canp->base->CAN_IER = AT91C_CAN_WAKEUP;
-
-	  /* CAN Controller Enable */
-	  canp->base->CAN_MR = AT91C_CAN_CANEN;
-}
-
-/**
- * @brief   Configures and activates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-
-void can_lld_start(CANDriver *canp) {
-
-	/*start CAN*/
-	can_startsequence(canp);
-	/* wait until wakeup. If no wakeup after 1 sec restart. */
-	chThdSleepS(1);
-	while( (canp->testok) == AT91C_TEST_NOK) {
-	  /* stop CAN */
-	    /* Disable all interrupts */
-	    canp->base->CAN_IDR = 0x1FFFFFFF;
-	    /* Disable the interrupt on the interrupt controller */
-	    AIC_DisableIT(AT91C_ID_CAN);
-	    /* Disable the CAN controller peripheral clock */
-	    AT91C_BASE_PMC->PMC_PCER = (0 << AT91C_ID_CAN);
-	  /* restart CAN */
-	    can_startsequence(canp);
-
-	    chThdSleepS(1);
-	}
-
-  /*enable Mailboxes */
-#if CAN_USE_MB1
-	canp->base->CAN_IER = (0x1 << 1);
-#endif
-#if CAN_USE_MB2
-	canp->base->CAN_IER = (0x1 << 2);
-#endif
-#if CAN_USE_MB3
-    canp->base->CAN_IER = (0x1 << 3);
-#endif
-#if CAN_USE_MB4
-	canp->base->CAN_IER = (0x1 << 4);
-#endif
-#if CAN_USE_MB5
-	canp->base->CAN_IER = (0x1 << 5);
-#endif
-#if CAN_USE_MB6
-	canp->base->CAN_IER = (0x1 << 6);
-#endif
-#if CAN_USE_MB7
-	canp->base->CAN_IER = (0x1 << 7);
-#endif
-
-
-}
-
-/**
- * @brief   Deactivates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_stop(CANDriver *canp) {
-
-  /* If in ready state then disables the CAN peripheral.*/
-  if (canp->state == CAN_READY) {
-
-    /* Disable all interrupts */
-    canp->base->CAN_IDR = 0x1FFFFFFF;
-
-    /* Disable the interrupt on the interrupt controller */
-    AIC_DisableIT(AT91C_ID_CAN);
-
-    /* Disable the CAN controller peripheral clock */
-    AT91C_BASE_PMC->PMC_PCER = (0 << AT91C_ID_CAN);
-  }
-}
-
-/**
- * @brief   Determines whether a frame can be transmitted.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @return              The queue space availability.
- * @retval FALSE        no space in the transmit queue.
- * @retval TRUE         transmit slot available.
- *
- * @notapi
- */
-bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
-
-    return ((canp->mb[CAN_TxMB0-1]->CAN_MB_MSR & AT91C_CAN_MRDY) != 0);
-}
-
-/**
- * @brief  Send specified frame.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @param[in] ctfp      pointer to the CAN frame to be transmitted
- *
- * @notapi
- */
-void can_lld_transmit(CANDriver *canp, canmbx_t mailbox, const CANTxFrame *ctfp) {
-  while (!( canp->mb[CAN_TxMB0-1]->CAN_MB_MSR & AT91C_CAN_MRDY)){
-  }
-#if CAN_IDE_EXT
-   canp->mb[CAN_TxMB0-1]->CAN_MB_MID =
-		   AT91C_CAN_MIDE | (AT91C_CAN_MIDvB & ctfp->EID)
-      | (AT91C_CAN_MIDvA & (ctfp->EID)); //configure the id
-#else
-   canp->mb[CAN_TxMB0-1]->CAN_MB_MID = AT91C_CAN_MIDE |
-		   (AT91C_CAN_MIDvB & 0x0)
-      | (AT91C_CAN_MIDvA & ctfp->SID); //configure the id
-
-#endif
-
-   /* set length of data */
-   canp->mb[CAN_TxMB0-1]->CAN_MB_MCR = (AT91C_CAN_MDLC & (ctfp->DLC << 16));
-
-   /* fill low register if 0<Length<=8 */
-   if(ctfp->DLC>0)
-	   canp->mb[CAN_TxMB0-1]->CAN_MB_MDL = ctfp->data32[0];
-   /* fill high register 4<Length<=8 */
-   if(ctfp->DLC>4)
-	   canp->mb[CAN_TxMB0-1]->CAN_MB_MDH = ctfp->data32[1];
-   canp->base->CAN_IER = 1 << CAN_TxMB0-1;
-   canp->base->CAN_TCR = 1 << 0; //send msg
-}
-
-/**
- * @brief   check if some data is available mailbox.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox	mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @return              The queue space availability.
- * @retval FALSE		mailbox is empty
- * @retval TRUE			some data in the mailbox
- *
- * @notapi
- */
-bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
-
-  if(mailbox == CAN_ANY_MAILBOX){
-	/* get status of all receive mailboxes (Mailbox0 is transmit mailbox) */
-	  if((canp->base->CAN_SR & 0xFE) != 0){
-	  	  return TRUE;
-      }
-  } else{
-	/* get status of specified mailbox */
-	if((canp->base->CAN_SR & (1<<(mailbox-1))) != 0){
-		/* data available */
-		return TRUE;
-	} else{
-		/* no data */
-		return FALSE;
-	}
-  }
-}
-
-/**
- * @brief   Receives a frame from the specified mailbox.
- *
- * @pre     Make sure that the Mailbox you are receiving from is holding
- * 			your data. If you have more than one use the rxfull_event
- * 			provided by the Driver.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @param[out] crfp     pointer to the buffer where the CAN frame is copied
- *
- * @notapi
- */
-void can_lld_receive(CANDriver *canp, canmbx_t mailbox, CANRxFrame *crfp) {
-  if(mailbox != CAN_ANY_MAILBOX){
-	  /* get length of data */
-	  crfp->DLC = (canp->mb[mailbox-1]->CAN_MB_MSR &
-			  AT91C_CAN_MDLC) >> 16;
-	  /* store data */
-	  if(crfp->DLC>0){
-		  crfp->data32[0] = canp->mb[mailbox-1]->CAN_MB_MDL;
-	  }
-	  if(crfp->DLC>=4){
-		  crfp->data32[1] = canp->mb[mailbox-1]->CAN_MB_MDH;
-	  }
-  }
-  else{
-	  /* TODO implement can_lld_receive for CAN_ANY_MAILBOX */
-  }
-  /* clear register */
-  canp->base->CAN_TCR = (0x1 << (mailbox-1));
-  /* reenable interrupt */
-  canp->base->CAN_IER = (0x1 << (mailbox-1));
-}
-
-#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
-/**
- * @brief   Enters the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_sleep(CANDriver *canp) {
-	/* Wait till Tx Mailbox is ready */
-	while(!((canp->mb[CAN_TxMB0-1]->CAN_MB_MSR & AT91C_CAN_MRDY) == AT91C_CAN_MRDY)){
-	}
-	/* enable low power mode */
-	canp->base->CAN_MR |= AT91C_CAN_LPM;
-	/* wait till CAN is in low power mode */
-	while(!((canp->base->CAN_SR & AT91C_CAN_SLEEP) == AT91C_CAN_SLEEP)){
-	}
-	/* disable Clock */
-	AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_CAN);
-
-}
-
-/**
- * @brief   Enforces leaving the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_wakeup(CANDriver *canp) {
-	/* enable clock */
-	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN);
-	/* disable low power mode */
-	canp->base->CAN_MR &= ~(AT91C_CAN_SLEEP);
-	while(!((canp->base->CAN_SR & AT91C_CAN_WAKEUP)==AT91C_CAN_WAKEUP)){
-	}
-
-}
-#endif /* CAN_USE_SLEEP_MODE */
-
-#endif /* HAL_USE_CAN */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/can_lld.h b/os/hal/platforms/AT91SAM7/can_lld.h
deleted file mode 100644
index f9ea7f6c2..000000000
--- a/os/hal/platforms/AT91SAM7/can_lld.h
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,2011 Giovanni Di Sirio.
- 2012,2013 Martin Sch��ler and Florian Sehl, Embedded Software Laboratory,
- RWTH Aachen University
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
-
- ---
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes ChibiOS/RT, without being obliged to provide
- the source code for any proprietary components. See the file exception.txt
- for full details of how and when the exception can be applied.
- */
-
-/**
- * @file    AT91SAM7/can_lld.h
- * @brief   AT91SAM7 CAN Driver subsystem low level driver header.
- *
- * @pre     - Make sure that the Mailbox you are receiving from is holding your
- * 			  data.
- * 			- If you have more than one use the rxfull_event provided by the
- * 			  Driver.
- * 			- In order to use the Events APIs the CH_USE_EVENTS option must
- * 			  be enabled in chconf.h.
- * 			- In order to use the CAN driver the HAL_USE_CAN option must be
- * 			  enabled in halconf.h.
- * 			- Mailbox0 is used as a Transmitmailbox.
- * 			- Mailboxes 1-7 are used as receive Mailboxes.
- *
- * @addtogroup CAN
- * @{
- */
-
-#ifndef _CAN_LLD_H_
-#define _CAN_LLD_H_
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   This switch defines whether the driver implementation supports
- *          a low power switch mode with automatic an wakeup feature.
- */
-#define CAN_SUPPORTS_SLEEP  		TRUE
-
-/**
- * @brief   This implementation supports one transmit mailboxes.
- */
-#define CAN_TX_MAILBOXES            1
-
-/**
- * @brief   This implementation supports two receive mailboxes.
- */
-#define CAN_RX_MAILBOXES            7
-
-/**
- * @brief   CAN mailboxes (Mailbox0 should always enabled to transmit)
- */
-#ifndef CAN_USE_MB0
-#define CAN_USE_MB0 TRUE
-#endif
-#ifndef CAN_USE_MB1
-#define CAN_USE_MB1 TRUE
-#endif
-#ifndef CAN_USE_MB2
-#define CAN_USE_MB2 TRUE
-#endif
-#ifndef CAN_USE_MB3
-#define CAN_USE_MB3 TRUE
-#endif
-#ifndef CAN_USE_MB4
-#define CAN_USE_MB4 FALSE
-#endif
-#ifndef CAN_USE_MB5
-#define CAN_USE_MB5 FALSE
-#endif
-#ifndef CAN_USE_MB6
-#define CAN_USE_MB6 FALSE
-#endif
-#ifndef CAN_USE_MB7
-#define CAN_USE_MB7 FALSE
-#endif
-
-
-#define CAN_IDE_STD                 FALSE        /**< @brief Standard id.    */
-#define CAN_IDE_EXT                 TRUE         /**< @brief Extended id.    */
-
-#define CAN_RTR_DATA                FALSE        /**< @brief Data frame.     */
-#define CAN_RTR_REMOTE              TRUE         /**< @brief Remote frame.   */
-
-/**
- * @brief timeout until can_lld_start stops waiting
- * on CAN and ends up in error state
- */
-#define AT91C_CAN_TIMEOUT			100
-
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   CAN driver enable switch.
- * @details If set to @p TRUE the support for CAN0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(AT91SAM7_CAN_USE_CAN) || defined(__DOXYGEN__)
-#define AT91SAM7_CAN_USE_CAN                  TRUE
-#endif
-
-/**
- * @brief   CAN interrupt priority level setting.
- */
-#if !defined(AT91SAM7_CAN_CAN_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define AT91SAM7_CAN_CAN_IRQ_PRIORITY         11
-#endif
-
-/**
- * @brief   Sleep mode related APIs inclusion switch.
- * @note    This switch is enforced to @p FALSE if the driver implementation
- *          does not support the sleep mode.
- */
-#if CAN_SUPPORTS_SLEEP || defined(__DOXYGEN__)
-#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
-#define CAN_USE_SLEEP_MODE  TRUE
-#endif
-#else /* !CAN_SUPPORTS_SLEEP */
-#define CAN_USE_SLEEP_MODE  FALSE
-#endif /* !CAN_SUPPORTS_SLEEP */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
-#error "CAN sleep mode not supported in this architecture"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief Type of a transmission mailbox index
- */
-typedef uint32_t canmbx_t;
-
-/**
- *  wakeup status possible states
- */
-typedef enum {
-	AT91C_TEST_NOK = 0,                    /**< waiting for wakeup event  	*/
-	AT91C_TEST_OK = 1                     /**< wakeup event occured		*/
-} canteststate_t;
-
-/**
- * @brief possible receive mailboxes.
- * These Mailboxes get an offset to ensure that the Mailbox are not uninitialized.
- *
- */
-typedef enum {
-	CAN_TxMB0 = 1,		/**< Transmit Mailbox.          */
-	CAN_RxMB1 = 2,		/**< Receive Mailbox 1.         */
-	CAN_RxMB2 = 3,		/**< Receive Mailbox 2.         */
-	CAN_RxMB3 = 4,		/**< Receive Mailbox 3.         */
-	CAN_RxMB4 = 5,		/**< Receive Mailbox 4.         */
-	CAN_RxMB5 = 6,		/**< Receive Mailbox 5.         */
-	CAN_RxMB6 = 7,		/**< Receive Mailbox 6.         */
-	CAN_RxMB7 = 8		/**< Receive Mailbox 7.         */
-} canmailbox_t;
-
-/**
- * @brief   CAN status flags.
- */
-typedef uint32_t canstatus_t;
-
-/**
- * @brief   CAN transmission frame.
- * @note    Accessing the frame data as word16 or word32 is not portable
- *          because machine data endianness, it can be still useful for a
- *          quick filling.
- */
-typedef struct {
-  struct {
-    uint8_t DLC:4; /**< @brief Data length.        */
-    uint8_t RTR:1; /**< @brief Frame type.         */
-    uint8_t IDE:1; /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t SID:11; /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t EID:29; /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t data8[8]; /**< @brief Frame data.         */
-    uint16_t data16[4]; /**< @brief Frame data.         */
-    uint32_t data32[2]; /**< @brief Frame data.         */
-  };
-}CANTxFrame;
-
-/**
- * @brief   CAN received frame.
- * @note    Accessing the frame data as word16 or word32 is not portable
- *          because machine data endianness, it can be still useful for a
- *          quick filling.
- */
-typedef struct {
-  struct {
-    uint8_t DLC:4; /**< @brief Data length.        */
-    uint8_t RTR:1; /**< @brief Frame type.         */
-    uint8_t IDE:1; /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t SID:11; /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t EID:29; /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t data8[8]; /**< @brief Frame data.         */
-    uint16_t data16[4]; /**< @brief Frame data.         */
-    uint32_t data32[2]; /**< @brief Frame data.         */
-  };
-  canmailbox_t mbid; /**< @brief mailbox to read from  */
-}CANRxFrame;
-
-/**
- * @brief   CAN filter.
- * @note    NOT used on this platform
- */
-typedef struct {
-}CANFilter;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-
-#if CAN_USE_MB1
-	uint32_t mb1_can_id; /**< @brief mailbox 1 can id  */
-	uint32_t mb1_acceptance_mask; /**< @brief mailbox 1 acceptance mask  */
-#endif
-#if CAN_USE_MB2
-	uint32_t mb2_can_id; /**< @brief mailbox 2 can id  */
-	uint32_t mb2_acceptance_mask; /**< @brief mailbox 2 acceptance mask  */
-#endif
-#if CAN_USE_MB3
-	uint32_t mb3_can_id; /**< @brief mailbox 3 can id  */
-	uint32_t mb3_acceptance_mask; /**< @brief mailbox 3 acceptance mask  */
-#endif
-#if CAN_USE_MB4
-	uint32_t mb4_can_id; /**< @brief mailbox 4 can id  */
-	uint32_t mb4_acceptance_mask; /**< @brief mailbox 4 acceptance mask  */
-#endif
-#if CAN_USE_MB5
-	uint32_t mb5_can_id; /**< @brief mailbox 5 can id  */
-	uint32_t mb5_acceptance_mask; /**< @brief mailbox 5 acceptance mask  */
-#endif
-#if CAN_USE_MB6
-	uint32_t mb6_can_id; /**< @brief mailbox 6 can id  */
-	uint32_t mb6_acceptance_mask; /**< @brief mailbox 6 acceptance mask  */
-#endif
-#if CAN_USE_MB7
-	uint32_t mb7_can_id; /**< @brief mailbox 7 can id  */
-	uint32_t mb7_acceptance_mask; /**< @brief mailbox 7 acceptance mask  */
-#endif
-  /**
-   * @brief value of the BR register
-   * @note  use 0x00050301 for 1MBit/s!
-   *
-   */
-  uint32_t br;
-
-}CANConfig;
-
-
-/**
- * @brief   Structure representing an CAN driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief Driver state.
-   */
-  canstate_t state;
-  /**
-   * @brief Current configuration data.
-   */
-  const CANConfig *config;
-  /**
-   * @brief Transmission queue semaphore.
-   */
-  Semaphore txsem;
-  /**
-   * @brief Receive queue semaphore.
-   */
-  Semaphore rxsem;
-  /**
-   * @brief One frame for one specified mailbox become available.
-   * @note  The number of the mailbox will be broadcasted to all listening threads.
-   *        It is responsibility of the application(thread) to empty the specified mailbox
-   *        by invoking @p chReceive() when listening to this event.
-   */
-  EventSource rxfull_event;
-  /**
-   * @brief transmission slot become available.
-   */
-  EventSource txempty_event;
-  /**
-   * @brief A CAN bus error happened.
-   */
-  EventSource error_event;
-#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
-  /**
-   * @brief Entering sleep state event.
-   */
-  EventSource sleep_event;
-  /**
-   * @brief Exiting sleep state event.
-   */
-  EventSource wakeup_event;
-#endif /* CAN_USE_SLEEP_MODE */
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Driver test OK (wakeup event occurred).
-   */
-  volatile canteststate_t testok;
-  /**
-   * @brief Pointer to the Mailboxes registers block.
-   */
-  AT91PS_CAN_MB mb[8];
-  /**
-   * @brief Pointer to the CAN registers.
-   */
-  AT91PS_CAN base;
-}CANDriver;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-  /**
-   * @brief create event mask using enum of the corresponding mailbox.
-   */
-#define CAN_EVENT_MASK(mailbox) EVENT_MASK(mailbox-1)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if AT91SAM7_CAN_USE_CAN && !defined(__DOXYGEN__)
-extern CANDriver CAND;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void can_lld_init(void);
-  void can_lld_serve_interrupt(CANDriver *canp);
-  void can_lld_start(CANDriver *canp);
-  void can_lld_stop(CANDriver *canp);
-  bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox);
-  void can_lld_transmit(CANDriver *canp,
-  	  	  				canmbx_t mailbox,
-		  	  	  	  	const CANTxFrame *crfp);
-  bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox);
-  void can_lld_receive(CANDriver *canp,
-  	  	  			   canmbx_t mailbox,
-		  	  	  	   CANRxFrame *ctfp);
-#if CAN_USE_SLEEP_MODE
-  void can_lld_sleep(CANDriver *canp);
-  void can_lld_wakeup(CANDriver *canp);
-
-#endif /* CAN_USE_SLEEP_MODE */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_CAN */
-
-#endif /* _CAN_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/ext_lld.c b/os/hal/platforms/AT91SAM7/ext_lld.c
deleted file mode 100644
index 91d0b7a8d..000000000
--- a/os/hal/platforms/AT91SAM7/ext_lld.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/ext_lld.c
- * @brief   AT91SAM7 EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTDA driver identifier.
- */
-EXTDriver EXTDA;
-
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
-    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-/**
- * @brief   EXTDB driver identifier.
- */
-EXTDriver EXTDB;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Handles external interrupts.
- *
- * @param[in] extp      pointer to the driver that received the interrupt
- */
-static void ext_lld_serveInterrupt(EXTDriver *extp) {
-  uint32_t irqFlags;
-  uint32_t ch;
-
-  chSysLockFromIsr();
-
-  /* Read flags of pending PIO interrupts.*/
-  irqFlags = extp->pio->PIO_ISR;
-
-  /* Call callback function for any pending interrupt.*/
-  for(ch = 0; ch < EXT_MAX_CHANNELS; ch++) {
-
-    /* Check if the channel is activated and if its IRQ flag is set.*/
-    if((extp->config->channels[ch].mode &
-        EXT_CH_MODE_ENABLED & EXT_CH_MODE_EDGES_MASK)
-        && ((1 << ch) & irqFlags)) {
-      (extp->config->channels[ch].cb)(extp, ch);
-    }
-  }
-
-  chSysUnlockFromIsr();
-
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTI[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTIA_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  ext_lld_serveInterrupt(&EXTDA);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
-    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-/**
- * @brief   EXTI[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTIB_IRQHandler) {
-  CH_IRQ_PROLOGUE();
-
-  ext_lld_serveInterrupt(&EXTDB);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
-  /* Driver initialization.*/
-  extObjectInit(&EXTDA);
-
-  /* Set PIO base addresses.*/
-  EXTDA.pio = AT91C_BASE_PIOA;
-
-  /* Set peripheral IDs.*/
-  EXTDA.pid = AT91C_ID_PIOA;
-
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
-    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-  /* Same for PIOB.*/
-  extObjectInit(&EXTDB);
-  EXTDB.pio = AT91C_BASE_PIOB;
-  EXTDB.pid = AT91C_ID_PIOB;
-#endif
-}
-
-/**
- * @brief   Configures and activates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
-  uint16_t ch;
-  uint32_t ier = 0;
-  const EXTConfig *config = extp->config;
-
-  switch(extp->pid) {
-  case AT91C_ID_PIOA:
-    AIC_ConfigureIT(AT91C_ID_PIOA, SAM7_computeSMR(config->mode,
-                                                   config->priority),
-                                                   EXTIA_IRQHandler);
-    break;
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
-    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-  case AT91C_ID_PIOB:
-    AIC_ConfigureIT(AT91C_ID_PIOB, SAM7_computeSMR(config->mode,
-                                                   config->priority),
-                                                   EXTIB_IRQHandler);
-    break;
-#endif
-  }
-
-  /* Enable and Disable channels with respect to config.*/
-  for(ch = 0; ch < EXT_MAX_CHANNELS; ch++) {
-    ier |= (config->channels[ch].mode & EXT_CH_MODE_EDGES_MASK & EXT_CH_MODE_ENABLED ? 1 : 0) << ch;
-  }
-  extp->pio->PIO_IER = ier;
-  extp->pio->PIO_IDR = ~ier;
-
-  /* Enable interrupt on corresponding PIO port in AIC.*/
-  AIC_EnableIT(extp->pid);
-}
-
-/**
- * @brief   Deactivates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-
-  /* Disable interrupt on corresponding PIO port in AIC.*/
-  AIC_DisableIT(extp->pid);
-}
-
-/**
- * @brief   Enables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
-  chDbgCheck((extp->config->channels[channel].cb != NULL),
-      "Call back pointer can not be NULL");
-
-  extp->pio->PIO_IER = (1 << channel);
-}
-
-/**
- * @brief   Disables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-
-  extp->pio->PIO_IDR = (1 << channel);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/ext_lld.h b/os/hal/platforms/AT91SAM7/ext_lld.h
deleted file mode 100644
index 3bc0baa99..000000000
--- a/os/hal/platforms/AT91SAM7/ext_lld.h
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/ext_lld.h
- * @brief   AT91SAM7 EXT subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_H_
-#define _EXT_LLD_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief    Pointer to the SAM7 AIC register block.
- */
-#define SAM7_EXT_AIC                  ((AT91PS_AIC *)AT91C_BASE_AIC)
-
-/**
- * @brief    Number of channels within one ext driver.
- */
-#define EXT_MAX_CHANNELS              32
-
-/**
- * @brief    Mask of priority bits in interrupt mode register.
- */
-#define SAM7_EXT_PRIORITY_MASK        0x00000007
-
-/**
- * @brief    Shifter for priority bits in interrupt mode register.
- */
-#define SAM7_EXT_PRIORITY_SHIFTER     0
-
-/**
- * @brief    Shifter for mode bits in interrupt mode register.
- */
-#define SAM7_EXT_MODE_SHIFTER         5
-
-/*
- * On the SAM7 architecture, a single channel can only be enables or disabled
- * Hence, undefine the other channel mode constants
- */
-#ifdef EXT_CH_MODE_RISING_EDGE
-#undef EXT_CH_MODE_RISING_EDGE
-#endif
-
-#ifdef EXT_CH_MODE_FALLING_EDGE
-#undef EXT_CH_MODE_FALLING_EDGE
-#endif
-
-#ifdef EXT_CH_MODE_BOTH_EDGES
-#undef EXT_CH_MODE_BOTH_EDGES
-#endif
-
-/**
- * @name    EXT channels mode
- * @{
- */
-#define EXT_CH_MODE_ENABLED           1     /**< @brief Channel is enabled. */
-/** @} */
-
-/**
- * @name    EXT drivers mode
- * @{
- */
-/**
- * @brief   Mask for modes.
- */
-#define SAM7_EXT_MODE_MASK            AT91C_AIC_SRCTYPE
-/**
- * @brief   Falling edge callback.
- */
-#define SAM7_EXT_MODE_FALLING_EDGE    AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE
-/**
- * @brief   Rising edge callback.
- */
-#define SAM7_EXT_MODE_RISING_EDGE     AT91C_AIC_SRCTYPE_POSITIVE_EDGE
-/**
- * @brief   High-level callback.
- */
-#define SAM7_EXT_MODE_HIGH_LEVEL      AT91C_AIC_SRCTYPE_HIGH_LEVEL
-/**
- * @brief   Low-level callback.
- */
-#define SAM7_EXT_MODE_LOW_LEVEL       AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL
-/** @} */
-
-/**
- * @name    EXT drivers priorities
- * @{
- */
-#define SAM7_EXT_PRIOR_HIGHEST        AT91C_AIC_PRIOR_HIGHEST
-#define SAM7_EXT_PRIOR_LOWEST         AT91C_AIC_PRIOR_LOWEST
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief   Type of an EXT generic notification callback.
- *
- * @param[in] extp      pointer to the @p EXPDriver object triggering the
- *                      callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief   Channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel mode.
-   */
-  uint32_t              mode;
-  /**
-   * @brief Channel callback.
-   */
-  extcallback_t         cb;
-} EXTChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief Channel configurations.
-   */
-  EXTChannelConfig      channels[EXT_MAX_CHANNELS];
-  /* End of the mandatory fields.*/
-  /**
-   * @brief interrupt mode.
-   */
-  uint32_t              mode;
-  /**
-   * @brief interrupt priority.
-   */
-  uint32_t              priority;
-} EXTConfig;
-
-/**
- * @brief   Structure representing an EXT driver.
- */
-struct EXTDriver {
-  /**
-   * @brief Driver state.
-   */
-  extstate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const EXTConfig       *config;
-  /* End of the mandatory fields.*/
-
-  /**
-   * @brief Pointer to the corresponding PIO registers block.
-   */
-  AT91PS_PIO            pio;
-  /**
-   * @brief peripheral ID of the corresponding PIO block.
-   */
-  uint32_t              pid;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief    Computes the content for the interrupt source mode register.
- */
-#define SAM7_computeSMR(mode, prio) (                                       \
-    ((mode & SAM7_EXT_MODE_MASK) << SAM7_EXT_MODE_SHIFTER) |                \
-    ((prio & SAM7_EXT_PRIORITY_MASK) << SAM7_EXT_PRIORITY_SHIFTER)          \
-)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern EXTDriver EXTDA;
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) ||           \
-    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-extern EXTDriver EXTDB;
-#endif
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_init(void);
-  void ext_lld_start(EXTDriver *extp);
-  void ext_lld_stop(EXTDriver *extp);
-  void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
-  void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/gpt_lld.c b/os/hal/platforms/AT91SAM7/gpt_lld.c
deleted file mode 100644
index 8cd226e5d..000000000
--- a/os/hal/platforms/AT91SAM7/gpt_lld.c
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/gpt_lld.c
- * @brief   AT91SAM7 GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPTD1 driver identifier.
- * @note    The driver GPTD1 allocates the complex timer TC0 when enabled.
- */
-#if AT91_GPT_USE_TC0 || defined(__DOXYGEN__)
-	GPTDriver GPTD1;
-#endif
-
-/**
- * @brief   GPTD2 driver identifier.
- * @note    The driver GPTD2 allocates the timer TC1 when enabled.
- */
-#if AT91_GPT_USE_TC1 || defined(__DOXYGEN__)
-	GPTDriver GPTD2;
-#endif
-
-/**
- * @brief   GPTD3 driver identifier.
- * @note    The driver GPTD3 allocates the timer TC2 when enabled.
- */
-#if AT91_GPT_USE_TC2 || defined(__DOXYGEN__)
-	GPTDriver GPTD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-	// Read the status to clear the interrupts
-	{ uint32_t	isr = gptp->tc->TC_SR; (void) isr; }
-
-	// Do the callback
-	gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if AT91_GPT_USE_TC0
-	/**
-	 * @brief   TC1 interrupt handler.
-	 *
-	 * @isr
-	 */
-	CH_IRQ_HANDLER(TC0_IRQHandler) {
-		CH_IRQ_PROLOGUE();
-		gpt_lld_serve_interrupt(&GPTD1);
-		AT91C_BASE_AIC->AIC_EOICR = 0;
-		CH_IRQ_EPILOGUE();
-	}
-#endif /* AT91_GPT_USE_TC0 */
-
-#if AT91_GPT_USE_TC1
-	/**
-	 * @brief   TC1 interrupt handler.
-	 *
-	 * @isr
-	 */
-	CH_IRQ_HANDLER(TC1_IRQHandler) {
-		CH_IRQ_PROLOGUE();
-		gpt_lld_serve_interrupt(&GPTD2);
-		AT91C_BASE_AIC->AIC_EOICR = 0;
-		CH_IRQ_EPILOGUE();
-	}
-#endif /* AT91_GPT_USE_TC1 */
-
-#if AT91_GPT_USE_TC2
-	/**
-	 * @brief   TC1 interrupt handler.
-	 *
-	 * @isr
-	 */
-	CH_IRQ_HANDLER(TC2_IRQHandler) {
-		CH_IRQ_PROLOGUE();
-		gpt_lld_serve_interrupt(&GPTD2);
-		AT91C_BASE_AIC->AIC_EOICR = 0;
-		CH_IRQ_EPILOGUE();
-	}
-}
-#endif /* AT91_GPT_USE_TC2 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-	#if AT91_GPT_USE_TC0
-		AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);			// Turn on the power
-		GPTD1.tc = AT91C_BASE_TC0;
-		gptObjectInit(&GPTD1);
-		gpt_lld_stop(&GPTD1);									// Make sure it is disabled
-		AIC_ConfigureIT(AT91C_ID_TC0, AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91_GPT_TC0_IRQ_PRIORITY, TC0_IRQHandler);
-		AIC_EnableIT(AT91C_ID_TC0);
-	#endif
-
-	#if AT91_GPT_USE_TC1
-		AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);			// Turn on the power
-		GPTD2.tc = AT91C_BASE_TC1;
-		gptObjectInit(&GPTD2);
-		gpt_lld_stop(&GPTD2);									// Make sure it is disabled
-		AIC_ConfigureIT(AT91C_ID_TC1, AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91_GPT_TC1_IRQ_PRIORITY, TC1_IRQHandler);
-		AIC_EnableIT(AT91C_ID_TC1);
-	#endif
-
-	#if AT91_GPT_USE_TC2
-		AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);			// Turn on the power
-		GPTD3.tc = AT91C_BASE_TC2;
-		gptObjectInit(&GPTD3);
-		gpt_lld_stop(&GPTD3);									// Make sure it is disabled
-		AIC_ConfigureIT(AT91C_ID_TC2, AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91_GPT_TC2_IRQ_PRIORITY, TC2_IRQHandler);
-		AIC_EnableIT(AT91C_ID_TC2);
-	#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-	uint32_t	cmr, bmr;
-
-	bmr = *AT91C_TCB_BMR;
-	cmr = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET |
-            AT91C_TC_WAVE  | AT91C_TC_WAVESEL_UP_AUTO);
-
-	// Calculate clock
-	switch(gptp->config->clocksource) {
-	case GPT_CLOCK_MCLK:
-		switch(gptp->config->frequency) {
-		case MCK/2:		cmr |= AT91C_TC_CLKS_TIMER_DIV1_CLOCK;	break;
-		case MCK/8:		cmr |= AT91C_TC_CLKS_TIMER_DIV2_CLOCK;	break;
-		case MCK/32:	cmr |= AT91C_TC_CLKS_TIMER_DIV3_CLOCK;	break;
-		case MCK/128:	cmr |= AT91C_TC_CLKS_TIMER_DIV4_CLOCK;	break;
-		case MCK/1024:	cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;	break;
-		default:
-			chDbgAssert(TRUE, "gpt_lld_start(), #1", "invalid frequency");
-			cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
-			break;
-		}
-		break;
-	case GPT_CLOCK_FREQUENCY:
-	    /* The mode and period will be calculated when the timer is started */
-		cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
-		break;
-	case GPT_CLOCK_RE_TCLK0:
-	case GPT_CLOCK_FE_TCLK0:
-		if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
-		cmr |= AT91C_TC_CLKS_XC0;
-		#if AT91_GPT_USE_TC0
-			if (gptp == &GPTD1) bmr = (bmr & ~AT91C_TCB_TC0XC0S) | AT91C_TCB_TC0XC0S_TCLK0;
-		#endif
-		break;
-	case GPT_CLOCK_RE_TCLK1:
-	case GPT_CLOCK_FE_TCLK1:
-		if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
-		cmr |= AT91C_TC_CLKS_XC1;
-		#if AT91_GPT_USE_TC1
-			if (gptp == &GPTD2) bmr = (bmr & ~AT91C_TCB_TC1XC1S) | AT91C_TCB_TC1XC1S_TCLK1;
-		#endif
-		break;
-	case GPT_CLOCK_RE_TCLK2:
-	case GPT_CLOCK_FE_TCLK2:
-		if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
-		cmr |= AT91C_TC_CLKS_XC2;
-		#if AT91_GPT_USE_TC2
-			if (gptp == &GPTD3) bmr = (bmr & ~AT91C_TCB_TC2XC2S) | AT91C_TCB_TC2XC2S_TCLK2;
-		#endif
-		break;
-	case GPT_CLOCK_RE_TC0:
-	case GPT_CLOCK_FE_TC0:
-		if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
-		#if AT91_GPT_USE_TC0
-			if (gptp == &GPTD1) {
-				chDbgAssert(TRUE, "gpt_lld_start(), #2", "invalid clock");
-				cmr |= AT91C_TC_CLKS_XC0;
-				bmr = (bmr & ~AT91C_TCB_TC0XC0S) | AT91C_TCB_TC0XC0S_NONE;
-				break;
-			}
-		#endif
-		#if AT91_GPT_USE_TC1
-			if (gptp == &GPTD2) {
-				cmr |= AT91C_TC_CLKS_XC1;
-				bmr = (bmr & ~AT91C_TCB_TC1XC1S) | AT91C_TCB_TC1XC1S_TIOA0;
-				break;
-			}
-		#endif
-		#if AT91_GPT_USE_TC2
-			if (gptp == &GPTD3) {
-				cmr |= AT91C_TC_CLKS_XC2;
-				bmr = (bmr & ~AT91C_TCB_TC2XC2S) | AT91C_TCB_TC2XC2S_TIOA0;
-				break;
-			}
-		#endif
-		chDbgAssert(TRUE, "gpt_lld_start(), #3", "invalid GPT device");
-		cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
-		break;
-	case GPT_CLOCK_RE_TC1:
-	case GPT_CLOCK_FE_TC1:
-		if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
-		#if AT91_GPT_USE_TC0
-			if (gptp == &GPTD1) {
-				cmr |= AT91C_TC_CLKS_XC0;
-				bmr = (bmr & ~AT91C_TCB_TC0XC0S) | AT91C_TCB_TC0XC0S_TIOA1;
-				break;
-			}
-		#endif
-		#if AT91_GPT_USE_TC1
-			if (gptp == &GPTD2) {
-				chDbgAssert(TRUE, "gpt_lld_start(), #4", "invalid clock");
-				cmr |= AT91C_TC_CLKS_XC1;
-				bmr = (bmr & ~AT91C_TCB_TC1XC1S) | AT91C_TCB_TC1XC1S_NONE;
-				break;
-			}
-		#endif
-		#if AT91_GPT_USE_TC2
-			if (gptp == &GPTD3) {
-				cmr |= AT91C_TC_CLKS_XC2;
-				bmr = (bmr & ~AT91C_TCB_TC2XC2S) | AT91C_TCB_TC2XC2S_TIOA1;
-				break;
-			}
-		#endif
-		chDbgAssert(TRUE, "gpt_lld_start(), #5", "invalid GPT device");
-		cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
-		break;
-	case GPT_CLOCK_RE_TC2:
-	case GPT_CLOCK_FE_TC2:
-		if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
-		#if AT91_GPT_USE_TC0
-			if (gptp == &GPTD1) {
-				cmr |= AT91C_TC_CLKS_XC0;
-				bmr = (bmr & ~AT91C_TCB_TC0XC0S) | AT91C_TCB_TC0XC0S_TIOA2;
-				break;
-			}
-		#endif
-		#if AT91_GPT_USE_TC1
-			if (gptp == &GPTD2) {
-				cmr |= AT91C_TC_CLKS_XC1;
-				bmr = (bmr & ~AT91C_TCB_TC1XC1S) | AT91C_TCB_TC1XC1S_TIOA2;
-				break;
-			}
-		#endif
-		#if AT91_GPT_USE_TC2
-			if (gptp == &GPTD3) {
-				chDbgAssert(TRUE, "gpt_lld_start(), #6", "invalid clock");
-				cmr |= AT91C_TC_CLKS_XC2;
-				bmr = (bmr & ~AT91C_TCB_TC2XC2S) | AT91C_TCB_TC2XC2S_NONE;
-				break;
-			}
-		#endif
-		chDbgAssert(TRUE, "gpt_lld_start(), #7", "invalid GPT device");
-		cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
-		break;
-	default:
-		chDbgAssert(TRUE, "gpt_lld_start(), #8", "invalid clock");
-		cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
-		break;
-	}
-
-	// Calculate clock gating
-	chDbgAssert(gptp->config->clockgate == GPT_GATE_NONE || gptp->config->clockgate == GPT_GATE_TCLK0
-			|| gptp->config->clockgate == GPT_GATE_TCLK1 || gptp->config->clockgate == GPT_GATE_TCLK2
-			, "gpt_lld_start(), #9", "invalid clockgate");
-	cmr |= ((uint32_t)(gptp->config->clockgate & 0x03)) << 4;		// special magic numbers here
-
-	// Calculate triggers
-	chDbgAssert(gptp->config->trigger == GPT_TRIGGER_NONE
-			|| gptp->config->trigger == GPT_TRIGGER_RE_TIOB  || gptp->config->trigger == GPT_TRIGGER_FE_TIOB  || gptp->config->trigger == GPT_TRIGGER_BE_TIOB
-			|| gptp->config->trigger == GPT_TRIGGER_RE_TCLK0 || gptp->config->trigger == GPT_TRIGGER_FE_TCLK0 || gptp->config->trigger == GPT_TRIGGER_BE_TCLK0
-			|| gptp->config->trigger == GPT_TRIGGER_RE_TCLK1 || gptp->config->trigger == GPT_TRIGGER_FE_TCLK1 || gptp->config->trigger == GPT_TRIGGER_BE_TCLK1
-			|| gptp->config->trigger == GPT_TRIGGER_RE_TCLK2 || gptp->config->trigger == GPT_TRIGGER_FE_TCLK2 || gptp->config->trigger == GPT_TRIGGER_BE_TCLK2
-			, "gpt_lld_start(), #10", "invalid trigger");
-	cmr |= ((uint32_t)(gptp->config->trigger & 0x03)) << 10;			// special magic numbers here
-	cmr |= ((uint32_t)(gptp->config->trigger & 0x30)) << (8-4);		// special magic numbers here
-
-    /* Set everything up but disabled */
-	gptp->tc->TC_CCR = AT91C_TC_CLKDIS;
-	gptp->tc->TC_IDR = 0xFFFFFFFF;
-	gptp->tc->TC_CMR = cmr;
-	gptp->tc->TC_RC = 65535;
-	gptp->tc->TC_RA = 32768;
-	*AT91C_TCB_BMR = bmr;
-	cmr = gptp->tc->TC_SR;			// Clear any pending interrupts
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-	gptp->tc->TC_CCR = AT91C_TC_CLKDIS;
-	gptp->tc->TC_IDR = 0xFFFFFFFF;
-	{ uint32_t isr = gptp->tc->TC_SR; (void)isr; }
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-	gpt_lld_change_interval(gptp, interval);
-	if (gptp->state == GPT_ONESHOT)
-		gptp->tc->TC_CMR |= AT91C_TC_CPCDIS;
-	else
-		gptp->tc->TC_CMR &= ~AT91C_TC_CPCDIS;
-	gptp->tc->TC_CCR = AT91C_TC_CLKEN|AT91C_TC_SWTRG;
-	if (gptp->config->callback)
-		gptp->tc->TC_IER = AT91C_TC_CPCS|AT91C_TC_COVFS;
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-	gptp->tc->TC_CCR = AT91C_TC_CLKDIS;
-	gptp->tc->TC_IDR = 0xFFFFFFFF;
-	{ uint32_t isr = gptp->tc->TC_SR; (void)isr; }
-}
-
-/**
- * @brief   Changes the interval of GPT peripheral.
- * @details This function changes the interval of a running GPT unit.
- * @pre     The GPT unit must have been activated using @p gptStart().
- * @pre     The GPT unit must have been running in continuous mode using
- *          @p gptStartContinuous().
- * @post    The GPT unit interval is changed to the new value.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- * @param[in] interval  new cycle time in timer ticks
- * @notapi
- */
-void gpt_lld_change_interval(GPTDriver *gptp, gptcnt_t interval) {
-	if (gptp->config->clocksource == GPT_CLOCK_FREQUENCY) {
-		uint32_t	rc, cmr;
-
-		// Reset the timer to the (possibly) new frequency value
-		rc = (MCK/2)/gptp->config->frequency;
-		if (rc < (0x10000<<0)) {
-			cmr = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
-		} else if (rc < (0x10000<<2)) {
-			rc >>= 2;
-			cmr = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
-		} else if (rc < (0x10000<<4)) {
-			rc >>= 4;
-			cmr = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
-		} else if (rc < (0x10000<<6)) {
-			rc >>= 6;
-			cmr = AT91C_TC_CLKS_TIMER_DIV4_CLOCK;
-		} else {
-			rc >>= 9;
-			cmr = AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
-		}
-		gptp->tc->TC_CMR = (gptp->tc->TC_CMR & ~AT91C_TC_CLKS) | cmr;
-		gptp->tc->TC_RC = rc;
-		gptp->tc->TC_RA = rc/2;
-	} else {
-		gptp->tc->TC_RC = interval;
-		gptp->tc->TC_RA = interval/2;
-	}
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-	gpt_lld_change_interval(gptp, interval);
-	gptp->tc->TC_CMR |= AT91C_TC_CPCDIS;
-	gptp->tc->TC_CCR = AT91C_TC_CLKEN|AT91C_TC_SWTRG;
-	while (!(gptp->tc->TC_SR & (AT91C_TC_CPCS|AT91C_TC_COVFS)));
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/gpt_lld.h b/os/hal/platforms/AT91SAM7/gpt_lld.h
deleted file mode 100644
index dc6338210..000000000
--- a/os/hal/platforms/AT91SAM7/gpt_lld.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/gpt_lld.h
- * @brief   AT91SAM7 GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   GPTD1 driver enable switch.
- * @details If set to @p TRUE the support for GPTD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(AT91_GPT_USE_TC0) || defined(__DOXYGEN__)
-#define AT91_GPT_USE_TC0                  FALSE
-#endif
-
-/**
- * @brief   GPTD2 driver enable switch.
- * @details If set to @p TRUE the support for GPTD2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(AT91_GPT_USE_TC1) || defined(__DOXYGEN__)
-#define AT91_GPT_USE_TC1                  FALSE
-#endif
-
-/**
- * @brief   GPTD3 driver enable switch.
- * @details If set to @p TRUE the support for GPTD3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(AT91_GPT_USE_TC2) || defined(__DOXYGEN__)
-#define AT91_GPT_USE_TC3                  FALSE
-#endif
-
-/**
- * @brief   GPTD1 interrupt priority level setting.
- */
-#if !defined(AT91_GPT_TC0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define AT91_GPT_TC0_IRQ_PRIORITY         (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/**
- * @brief   GPTD2 interrupt priority level setting.
- */
-#if !defined(AT91_GPT_TC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define AT91_GPT_TC1_IRQ_PRIORITY         (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/**
- * @brief   GPTD3 interrupt priority level setting.
- */
-#if !defined(AT91_GPT_TC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define AT91_GPT_TC2_IRQ_PRIORITY         (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !AT91_GPT_USE_TC0 && !AT91_GPT_USE_TC1 && !AT91_GPT_USE_TC2
-#error "GPT driver activated but no TC peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint16_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Timer Clock Source.
-   */
-  uint8_t                  clocksource;
-	#define GPT_CLOCK_MCLK			0				// @< Internal clock. frequency must = MCLK/2, MCLK/8, MCLK/32, MCLK/128 or MCLK/1024
-	#define GPT_CLOCK_FREQUENCY		1				// @< Internal clock. interval is ignored. frequency determines rate
-	#define GPT_CLOCK_RE_TCLK0		2				// @< External TCLK0. Rising Edge
-	#define GPT_CLOCK_FE_TCLK0		3				// @< External TCLK0. Falling Edge
-	#define GPT_CLOCK_RE_TCLK1		4				// @< External TCLK1. Rising Edge
-	#define GPT_CLOCK_FE_TCLK1		5				// @< External TCLK1. Falling Edge
-	#define GPT_CLOCK_RE_TCLK2		6				// @< External TCLK2. Rising Edge
-	#define GPT_CLOCK_FE_TCLK2		7				// @< External TCLK2. Falling Edge
-	#define GPT_CLOCK_RE_TC0		8				// @< TC0 output. Rising Edge. Do not use on TC0
-	#define GPT_CLOCK_FE_TC0		9				// @< TC0 output. Falling Edge. Do not use on TC0
-	#define GPT_CLOCK_RE_TC1		10				// @< TC1 output. Rising Edge. Do not use on TC1
-	#define GPT_CLOCK_FE_TC1		11				// @< TC1 output. Falling Edge. Do not use on TC1
-	#define GPT_CLOCK_RE_TC2		12				// @< TC2 output. Rising Edge. Do not use on TC2
-	#define GPT_CLOCK_FE_TC2		13				// @< TC2 output. Falling Edge. Do not use on TC2
-  uint8_t					clockgate;
-	#define GPT_GATE_NONE			0				// @< Clock gating off
-	#define GPT_GATE_TCLK0			1				// @< Clock on TCLK0 active high signal. If using this on TC0 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_GATE_TCLK1			2				// @< Clock on TCLK1 active high signal. If using this on TC1 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_GATE_TCLK2			3				// @< Clock on TCLK2 active high signal. If using this on TC2 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-  uint8_t					trigger;
-	#define GPT_TRIGGER_NONE		0x00			// @< Start immediately
-	#define GPT_TRIGGER_RE_TIOB		0x10			// @< Start on TIOB  signal. Rising Edge.
-	#define GPT_TRIGGER_FE_TIOB		0x20			// @< Start on TIOB  signal. Falling Edge.
-	#define GPT_TRIGGER_BE_TIOB		0x30			// @< Start on TIOB  signal. Both Edges.
-	#define GPT_TRIGGER_RE_TCLK0	0x11			// @< Start on TCLK0 signal. Rising Edge.  If using this on TC0 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_TRIGGER_FE_TCLK0	0x21			// @< Start on TCLK0 signal. Falling Edge. If using this on TC0 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_TRIGGER_BE_TCLK0	0x31			// @< Start on TCLK0 signal. Both Edges.   If using this on TC0 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_TRIGGER_RE_TCLK1	0x12			// @< Start on TCLK1 signal. Rising Edge.  If using this on TC1 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_TRIGGER_FE_TCLK1	0x22			// @< Start on TCLK1 signal. Falling Edge. If using this on TC1 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_TRIGGER_BE_TCLK1	0x32			// @< Start on TCLK1 signal. Both Edges.   If using this on TC1 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_TRIGGER_RE_TCLK2	0x13			// @< Start on TCLK2 signal. Rising Edge.  If using this on TC2 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_TRIGGER_FE_TCLK2	0x23			// @< Start on TCLK2 signal. Falling Edge. If using this on TC2 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-	#define GPT_TRIGGER_BE_TCLK2	0x33			// @< Start on TCLK2 signal. Both Edges.   If using this on TC2 with GPT_CLOCK_xx_TIMx, the TIMx output will be used instead.
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-#if defined(GPT_DRIVER_EXT_FIELDS)
-  GPT_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the TCx registers block.
-   */
-  AT91S_TC               *tc;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if AT91_GPT_USE_TC0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if AT91_GPT_USE_TC1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if AT91_GPT_USE_TC2 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_change_interval(GPTDriver *gptp, gptcnt_t interval);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/hal_lld.c b/os/hal/platforms/AT91SAM7/hal_lld.c
deleted file mode 100644
index 43659ed9c..000000000
--- a/os/hal/platforms/AT91SAM7/hal_lld.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/hal_lld.c
- * @brief   AT91SAM7 HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-static CH_IRQ_HANDLER(spurious_handler) {
-
-  CH_IRQ_PROLOGUE();
-
-  AT91SAM7_SPURIOUS_HANDLER_HOOK();
-
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-  unsigned i;
-
-  /* FIQ Handler weak symbol defined in vectors.s.*/
-  void FiqHandler(void);
-
-  /* Default AIC setup, the device drivers will modify it as needed.*/
-  AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
-  AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
-  AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler;
-  for (i = 1; i < 31; i++) {
-    AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL;
-    AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i;
-  }
-  AT91C_BASE_AIC->AIC_SPU  = (AT91_REG)spurious_handler;
-
-}
-
-/**
- * @brief   AT91SAM7 clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void at91sam7_clock_init(void) {
-
-  /* wait for reset */
-  while((AT91C_BASE_RSTC->RSTC_RSR & (AT91C_RSTC_SRCMP | AT91C_RSTC_NRSTL)) != AT91C_RSTC_NRSTL)
-    ;
-  /* enable reset */
-  AT91C_BASE_RSTC->RSTC_RMR = ((0xA5 << 24) | AT91C_RSTC_URSTEN);
-
-  /* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/
-#if SAM7_PLATFORM == SAM7X512
-  AT91C_BASE_MC->MC0_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
-  AT91C_BASE_MC->MC1_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
-#else
-  AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
-#endif
-
-  /* Enables the main oscillator and waits 56 slow cycles as startup time.*/
-  AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN;
-  while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS))
-    ;
-
-  /* PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10
-     PLLfreq = 96109714 Hz (rounded).*/
-  AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) |
-                             (AT91C_CKGR_PLLCOUNT & (10 << 8)) |
-                             (AT91SAM7_USBDIV) |
-                             (AT91C_CKGR_MUL & (72 << 16));
-  while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK))
-    ;
-
-  /* Master clock = PLLfreq / 2 = 48054858 Hz (rounded).*/
-  AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
-  while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
-    ;
-
-  AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
-  while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
-    ;
-}
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/hal_lld.h b/os/hal/platforms/AT91SAM7/hal_lld.h
deleted file mode 100644
index 2a489be6f..000000000
--- a/os/hal/platforms/AT91SAM7/hal_lld.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/hal_lld.h
- * @brief   AT91SAM7 HAL subsystem low level driver header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "at91sam7.h"
-#include "at91lib/aic.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME   "AT91SAM7x"
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Default action for the spurious handler, nothing.
- */
-#if !defined(AT91SAM7_SPURIOUS_HANDLER_HOOK) || defined(__DOXYGEN__)
-#define AT91SAM7_SPURIOUS_HANDLER_HOOK()
-#endif
-
-/**
- * @brief   Default divider for the USB clock - half the PLL clock.
- */
-#if !defined(AT91SAM7_USBDIV) || defined(__DOXYGEN__)
-#define AT91SAM7_USBDIV AT91C_CKGR_USBDIV_1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void at91sam7_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/i2c_lld.c b/os/hal/platforms/AT91SAM7/i2c_lld.c
deleted file mode 100644
index 1e6e02829..000000000
--- a/os/hal/platforms/AT91SAM7/i2c_lld.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    AT91SAM7/i2c_lld.c
- * @brief   AT91SAM7 I2C subsystem low level driver source.
- * @note    I2C peripheral interrupts on AT91SAM7 platform must have highest
- *          priority in system.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief I2C1 driver identifier.*/
-#if SAM7_I2C_USE_I2C1 || defined(__DOXYGEN__)
-I2CDriver I2CD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Wakes up the waiting thread.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] msg       wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((i2cp)->thread != NULL) {                                             \
-    Thread *tp = (i2cp)->thread;                                            \
-    (i2cp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = (msg);                                                 \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
-}
-
-/**
- * @brief   Helper function.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void _i2c_lld_serve_rx_interrupt(I2CDriver *i2cp){
-  if (i2cp->rxbytes == 1)
-    AT91C_BASE_TWI->TWI_CR |= AT91C_TWI_STOP;
-
-  *(i2cp->rxbuf) = AT91C_BASE_TWI->TWI_RHR;
-  i2cp->rxbuf++;
-  i2cp->rxbytes--;
-  if (i2cp->rxbytes == 0){
-    AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_RXRDY;
-    AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXCOMP;
-  }
-}
-
-/**
- * @brief   Helper function.
- * @note    During write operation you do not need to set STOP manually.
- *          It sets automatically when THR and shift registers becomes empty.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void _i2c_lld_serve_tx_interrupt(I2CDriver *i2cp){
-
-  if (i2cp->txbytes == 0){
-    AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXRDY;
-    AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXCOMP;
-  }
-  else{
-    AT91C_BASE_TWI->TWI_THR = *(i2cp->txbuf);
-    i2cp->txbuf++;
-    i2cp->txbytes--;
-  }
-}
-
-/**
- * @brief   I2C shared ISR code.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_interrupt(I2CDriver *i2cp) {
-
-  uint32_t sr;
-  sr = AT91C_BASE_TWI->TWI_SR;
-  /* this masking doing in official Atmel driver. Is it needed ??? */
-  sr &= AT91C_BASE_TWI->TWI_IMR;
-
-  if (sr & AT91C_TWI_NACK){
-    i2cp->errors |= I2CD_ACK_FAILURE;
-    wakeup_isr(i2cp, RDY_RESET);
-    return;
-  }
-  if (sr & AT91C_TWI_RXRDY){
-    _i2c_lld_serve_rx_interrupt(i2cp);
-  }
-  else if (sr & AT91C_TWI_TXRDY){
-    _i2c_lld_serve_tx_interrupt(i2cp);
-  }
-  else if (sr & AT91C_TWI_TXCOMP){
-    AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXCOMP;
-    wakeup_isr(i2cp, RDY_OK);
-  }
-  else
-    chDbgPanic("Invalid value");
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SAM7_I2C_USE_I2C1 || defined(__DOXYGEN__)
-/**
- * @brief   I2C1 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(TWI_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-  i2c_lld_serve_interrupt(&I2CD1);
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_I2C_USE_I2C1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-#if SAM7_I2C_USE_I2C1
-  i2cObjectInit(&I2CD1);
-  I2CD1.thread  = NULL;
-  I2CD1.txbuf   = NULL;
-  I2CD1.rxbuf   = NULL;
-  I2CD1.txbytes = 0;
-  I2CD1.rxbytes = 0;
-
-  AT91C_BASE_PIOA->PIO_PDR   = AT91C_PA0_TWD | AT91C_PA1_TWCK;
-  AT91C_BASE_PIOA->PIO_ASR   = AT91C_PA0_TWD | AT91C_PA1_TWCK;
-  AT91C_BASE_PIOA->PIO_MDER  = AT91C_PA0_TWD | AT91C_PA1_TWCK;
-  AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PA0_TWD | AT91C_PA1_TWCK;
-
-  AIC_ConfigureIT(AT91C_ID_TWI,
-                  AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | SAM7_I2C_I2C1_IRQ_PRIORITY,
-                  TWI_IRQHandler);
-#endif /* STM32_I2C_USE_I2C1 */
-}
-
-/**
- * @brief   Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-
-  volatile uint32_t fake;
-
-  /* If in stopped state then enables the I2C clocks.*/
-  if (i2cp->state == I2C_STOP) {
-
-#if SAM7_I2C_USE_I2C1
-    if (&I2CD1 == i2cp) {
-      /* enable peripheral clock */
-      AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TWI);
-
-      /* Enables associated interrupt vector.*/
-      AIC_EnableIT(AT91C_ID_TWI);
-
-      /* Reset */
-      AT91C_BASE_TWI->TWI_CR = AT91C_TWI_SWRST;
-      fake = AT91C_BASE_TWI->TWI_RHR;
-
-      /* Set master mode */
-      AT91C_BASE_TWI->TWI_CR = AT91C_TWI_MSDIS;
-      AT91C_BASE_TWI->TWI_CR = AT91C_TWI_MSEN;
-
-      /* Setup I2C parameters. */
-      AT91C_BASE_TWI->TWI_CWGR = i2cp->config->cwgr;
-    }
-#endif /* STM32_I2C_USE_I2C1 */
-  }
-
-  (void)fake;
-}
-
-/**
- * @brief   Deactivates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
-  /* If not in stopped state then disables the I2C clock.*/
-  if (i2cp->state != I2C_STOP) {
-
-#if SAM7_I2C_USE_I2C1
-    if (&I2CD1 == i2cp) {
-      AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXCOMP | AT91C_TWI_RXRDY |
-                                 AT91C_TWI_TXRDY | AT91C_TWI_NACK;
-      AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_TWI);
-      AIC_DisableIT(AT91C_ID_TWI);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Receives data via the I2C bus as master.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   this value is ignored on SAM7 platform.
- *
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                     uint8_t *rxbuf, size_t rxbytes,
-                                     systime_t timeout) {
-  (void)timeout;
-
-  /* delete trash from RHR*/
-  volatile uint32_t fake;
-  fake = AT91C_BASE_TWI->TWI_RHR;
-  (void)fake;
-
-  /* Initializes driver fields.*/
-  i2cp->rxbuf   = rxbuf;
-  i2cp->rxbytes = rxbytes;
-
-  i2cp->txbuf   = NULL;
-  i2cp->txbytes = 0;
-
-  /* tune master mode register */
-  AT91C_BASE_TWI->TWI_MMR = 0;
-  AT91C_BASE_TWI->TWI_MMR |= (addr << 16) | AT91C_TWI_MREAD;
-
-  /* enable just needed interrupts */
-  AT91C_BASE_TWI->TWI_IER = AT91C_TWI_RXRDY | AT91C_TWI_NACK;
-
-  /* In single data byte master read or write, the START and STOP must both be set. */
-  if (rxbytes == 1)
-    AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP | AT91C_TWI_START;
-  else
-    AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START;
-
-  /* Waits for the operation completion.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief   Read data via the I2C bus as master using internal slave addressing.
- * @details Address bytes must be written in special purpose SAM7 registers.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[in] txbuf     pointer to the transmit buffer
- * @param[in] txbytes   number of bytes to be transmitted
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   this value is ignored on SAM7 platform.
- *
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- *
- * @notapi
- */
-msg_t i2c_lld_transceive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                 const uint8_t *txbuf, size_t txbytes,
-                                 uint8_t *rxbuf, size_t rxbytes,
-                                 systime_t timeout) {
-  (void)timeout;
-
-  /* delete trash from RHR*/
-  volatile uint32_t fake;
-  fake = AT91C_BASE_TWI->TWI_RHR;
-  (void)fake;
-
-  /* Initializes driver fields.*/
-  i2cp->rxbuf   = rxbuf;
-  i2cp->rxbytes = rxbytes;
-
-  /* tune master mode register */
-  AT91C_BASE_TWI->TWI_MMR = 0;
-  AT91C_BASE_TWI->TWI_MMR |= (addr << 16) | (txbytes << 8) | AT91C_TWI_MREAD;
-
-  /* store internal slave address in TWI_IADR registers */
-  AT91C_BASE_TWI->TWI_IADR = 0;
-  while (txbytes > 0){
-    AT91C_BASE_TWI->TWI_IADR = (AT91C_BASE_TWI->TWI_IADR << 8);
-    AT91C_BASE_TWI->TWI_IADR |= *(txbuf++);
-    txbytes--;
-  }
-
-  /* enable just needed interrupts */
-  AT91C_BASE_TWI->TWI_IER = AT91C_TWI_RXRDY | AT91C_TWI_NACK;
-
-  /* Internal address of I2C slave was set in special Atmel registers.
-   * Now we must call read function. The I2C cell automatically sends
-   * bytes from IADR register to bus and issues repeated start. */
-  if (rxbytes == 1)
-    AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP | AT91C_TWI_START;
-  else
-    AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START;
-
-  /* Waits for the operation completion.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief   Transmits data via the I2C bus as master.
- * @details When performing reading through write you can not write more than
- *          3 bytes of data to I2C slave. This is SAM7 platform limitation.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[in] txbuf     pointer to the transmit buffer
- * @param[in] txbytes   number of bytes to be transmitted
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   this value is ignored on SAM7 platform.
- *
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                      const uint8_t *txbuf, size_t txbytes,
-                                      uint8_t *rxbuf, size_t rxbytes,
-                                      systime_t timeout) {
-  (void)timeout;
-
-  /* SAM7 specific check */
-  chDbgCheck(((rxbytes == 0) ||
-             ((txbytes > 0) && (txbytes < 4) && (rxbuf != NULL))),
-               "i2c_lld_master_transmit_timeout");
-
-  /* prepare to read through write operation */
-  if (rxbytes > 0){
-    return i2c_lld_transceive_timeout(i2cp, addr, txbuf, txbytes, rxbuf,
-                                      rxbytes, timeout);
-  }
-  else{
-    if (txbytes == 1){
-      /* In single data byte master read or write, the START and STOP
-       * must both be set. */
-      AT91C_BASE_TWI->TWI_CR |= AT91C_TWI_STOP;
-    }
-    AT91C_BASE_TWI->TWI_MMR  = 0;
-    AT91C_BASE_TWI->TWI_MMR |= addr << 16;
-
-    /* enable just needed interrupts */
-    AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXRDY | AT91C_TWI_NACK;
-
-    /* correct size and pointer because first byte will be written
-     * for issue start condition */
-    i2cp->txbuf   = txbuf + 1;
-    i2cp->txbytes = txbytes - 1;
-
-    /* According to datasheet there is no need to set START manually
-     * we just need to write first byte in THR */
-    AT91C_BASE_TWI->TWI_THR = txbuf[0];
-
-    /* Waits for the operation completion.*/
-    i2cp->thread = chThdSelf();
-    chSchGoSleepS(THD_STATE_SUSPENDED);
-
-    return chThdSelf()->p_u.rdymsg;
-  }
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/i2c_lld.h b/os/hal/platforms/AT91SAM7/i2c_lld.h
deleted file mode 100644
index 8e22acaf6..000000000
--- a/os/hal/platforms/AT91SAM7/i2c_lld.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    AT91SAM7/i2c_lld.h
- * @brief   AT91SAM7 I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Peripheral clock frequency.
- */
-#define I2C_CLK_FREQ  ((STM32_PCLK1) / 1000000)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   I2C1 driver enable switch.
- * @details If set to @p TRUE the support for I2C1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SAM7_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define SAM7_I2C_USE_I2C1              FALSE
-#endif
-
-/**
- * @brief   I2C1 interrupt priority level setting.
- */
-#if !defined(SAM7_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_I2C_I2C1_IRQ_PRIORITY     (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/** @brief  error checks */
-#if !SAM7_I2C_USE_I2C1
-#error "I2C driver activated but no I2C peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing I2C address.
- */
-typedef uint16_t i2caddr_t;
-
-/**
- * @brief   I2C Driver condition flags type.
- */
-typedef uint32_t i2cflags_t;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   CWGR regitster content.
-   */
-  uint32_t                  cwgr;
-} I2CConfig;
-
-/**
- * @brief   Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver{
-  /**
-   * @brief   Driver state.
-   */
-  i2cstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const I2CConfig           *config;
-  /**
-   * @brief   Error flags.
-   */
-  i2cflags_t                errors;
-  /**
-   * @brief   Pointer to receive buffer.
-   */
-  uint8_t                   *rxbuf;
-  /**
-   * @brief   Pointer to transmit buffer.
-   */
-  const uint8_t             *txbuf;
-  /**
-   * @brief   Bytes count to be received.
-   */
-  size_t                    rxbytes;
-  /**
-   * @brief   Bytes count to be transmitted.
-   */
-  size_t                    txbytes;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
-  I2C_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Thread waiting for I/O completion.
-   */
-  Thread                    *thread;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Get errors from I2C driver.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-#if SAM7_I2C_USE_I2C1
-extern I2CDriver I2CD1;
-#endif
-
-#endif /* !defined(__DOXYGEN__) */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void i2c_lld_init(void);
-  void i2c_lld_start(I2CDriver *i2cp);
-  void i2c_lld_stop(I2CDriver *i2cp);
-  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                        const uint8_t *txbuf, size_t txbytes,
-                                        uint8_t *rxbuf, size_t rxbytes,
-                                        systime_t timeout);
-  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                       uint8_t *rxbuf, size_t rxbytes,
-                                       systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_I2C  */
-
-#endif /* _I2C_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/mac_lld.c b/os/hal/platforms/AT91SAM7/mac_lld.c
deleted file mode 100644
index df1e0b88b..000000000
--- a/os/hal/platforms/AT91SAM7/mac_lld.c
+++ /dev/null
@@ -1,551 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/mac_lld.c
- * @brief   AT91SAM7 low level MAC driver code.
- *
- * @addtogroup MAC
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-#include "mii.h"
-#include "at91sam7_mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-#define EMAC_PIN_MASK (AT91C_PB0_ETXCK_EREFCK  | AT91C_PB1_ETXEN         | \
-                       AT91C_PB2_ETX0          | AT91C_PB3_ETX1          | \
-                       AT91C_PB4_ECRS          | AT91C_PB5_ERX0          | \
-                       AT91C_PB6_ERX1          | AT91C_PB7_ERXER         | \
-                       AT91C_PB8_EMDC          | AT91C_PB9_EMDIO         | \
-                       AT91C_PB10_ETX2         | AT91C_PB11_ETX3         | \
-                       AT91C_PB12_ETXER        | AT91C_PB13_ERX2         | \
-                       AT91C_PB14_ERX3         | AT91C_PB15_ERXDV_ECRSDV | \
-                       AT91C_PB16_ECOL         | AT91C_PB17_ERXCK)
-
-#define RSR_BITS (AT91C_EMAC_BNA | AT91C_EMAC_REC | AT91C_EMAC_OVR)
-
-#define TSR_BITS (AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES | \
-                  AT91C_EMAC_BEX | AT91C_EMAC_COMP | AT91C_EMAC_UND)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Ethernet driver 1.
- */
-MACDriver ETHD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-#ifndef __DOXYGEN__
-
-static uint8_t default_mac[] = {0xAA, 0x55, 0x13, 0x37, 0x01, 0x10};
-
-static EMACDescriptor *rxptr;
-static EMACDescriptor *txptr;
-static EMACDescriptor rd[EMAC_RECEIVE_DESCRIPTORS]
-    __attribute__((aligned(8)));
-static EMACDescriptor td[EMAC_TRANSMIT_DESCRIPTORS]
-    __attribute__((aligned(8)));
-static uint8_t rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE]
-    __attribute__((aligned(8)));
-static uint8_t tb[EMAC_TRANSMIT_DESCRIPTORS * EMAC_TRANSMIT_BUFFERS_SIZE]
-    __attribute__((aligned(8)));
-#endif
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   IRQ handler.
- */
-/** @cond never*/
-__attribute__((noinline))
-/** @endcond*/
-static void serve_interrupt(void) {
-  uint32_t isr, rsr, tsr;
-
-  /* Fix for the EMAC errata */
-  isr = AT91C_BASE_EMAC->EMAC_ISR;
-  rsr = AT91C_BASE_EMAC->EMAC_RSR;
-  tsr = AT91C_BASE_EMAC->EMAC_TSR;
-
-  if ((isr & AT91C_EMAC_RCOMP) || (rsr & RSR_BITS)) {
-    if (rsr & AT91C_EMAC_REC) {
-      chSysLockFromIsr();
-      chSemResetI(&ETHD1.rdsem, 0);
-#if MAC_USE_EVENTS
-      chEvtBroadcastI(&ETHD1.rdevent);
-#endif
-      chSysUnlockFromIsr();
-    }
-    AT91C_BASE_EMAC->EMAC_RSR = RSR_BITS;
-  }
-
-  if ((isr & AT91C_EMAC_TCOMP) || (tsr & TSR_BITS)) {
-    if (tsr & AT91C_EMAC_COMP) {
-      chSysLockFromIsr();
-      chSemResetI(&ETHD1.tdsem, 0);
-      chSysUnlockFromIsr();
-    }
-    AT91C_BASE_EMAC->EMAC_TSR = TSR_BITS;
-  }
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-}
-
-/**
- * @brief   Cleans an incomplete frame.
- *
- * @param[in] from      the start position of the incomplete frame
- */
-static void cleanup(EMACDescriptor *from) {
-
-  while (from != rxptr) {
-    from->w1 &= ~W1_R_OWNERSHIP;
-    if (++from >= &rd[EMAC_RECEIVE_DESCRIPTORS])
-      from = rd;
-  }
-}
-
-/**
- * @brief   MAC address setup.
- *
- * @param[in] p         pointer to a six bytes buffer containing the MAC
- *                      address
- */
-static void set_address(const uint8_t *p) {
-
-  AT91C_BASE_EMAC->EMAC_SA1L = (AT91_REG)((p[3] << 24) | (p[2] << 16) |
-                                          (p[1] << 8) | p[0]);
-  AT91C_BASE_EMAC->EMAC_SA1H = (AT91_REG)((p[5] << 8) | p[4]);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EMAC IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(irq_handler) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt();
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level MAC initialization.
- *
- * @notapi
- */
-void mac_lld_init(void) {
-
-  miiInit();
-  macObjectInit(&ETHD1);
-
-  /*
-   * Associated PHY initialization.
-   */
-  miiReset(&ETHD1);
-
-  /*
-   * EMAC pins setup. Note, PB18 is not included because it is
-   * used as #PD control and not as EF100.
-   */
-  AT91C_BASE_PIOB->PIO_ASR = EMAC_PIN_MASK;
-  AT91C_BASE_PIOB->PIO_PDR = EMAC_PIN_MASK;
-  AT91C_BASE_PIOB->PIO_PPUDR = EMAC_PIN_MASK;
-}
-
-/**
- * @brief   Configures and activates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_start(MACDriver *macp) {
-  unsigned i;
-
-  /*
-   * Buffers initialization.
-   */
-  for (i = 0; i < EMAC_RECEIVE_DESCRIPTORS; i++) {
-    rd[i].w1 = (uint32_t)&rb[i * EMAC_RECEIVE_BUFFERS_SIZE];
-    rd[i].w2 = 0;
-  }
-  rd[EMAC_RECEIVE_DESCRIPTORS - 1].w1 |= W1_R_WRAP;
-  rxptr = rd;
-  for (i = 0; i < EMAC_TRANSMIT_DESCRIPTORS; i++) {
-    td[i].w1 = (uint32_t)&tb[i * EMAC_TRANSMIT_BUFFERS_SIZE];
-    td[i].w2 = EMAC_TRANSMIT_BUFFERS_SIZE | W2_T_LAST_BUFFER | W2_T_USED;
-  }
-  td[EMAC_TRANSMIT_DESCRIPTORS - 1].w2 |= W2_T_WRAP;
-  txptr = td;
-
-  /*
-   * EMAC clock enable.
-   */
-  AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
-
-  /*
-   * EMAC Initial setup.
-   */
-  AT91C_BASE_EMAC->EMAC_NCR = 0;                /* Stopped but MCE active.*/
-  AT91C_BASE_EMAC->EMAC_NCFGR = 2 << 10;        /* MDC-CLK = MCK / 32 */
-  AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;/* Enable EMAC in MII mode.*/
-  AT91C_BASE_EMAC->EMAC_RBQP = (AT91_REG)rd;    /* RX descriptors list.*/
-  AT91C_BASE_EMAC->EMAC_TBQP = (AT91_REG)td;    /* TX descriptors list.*/
-  AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR |
-                              AT91C_EMAC_REC |
-                              AT91C_EMAC_BNA;   /* Clears RSR.*/
-  AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_DRFCS;/* Initial NCFGR settings.*/
-  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE |
-                               AT91C_EMAC_RE |
-                               AT91C_EMAC_CLRSTAT;/* Initial NCR settings.*/
-  if (macp->config->mac_address == NULL)
-    set_address(default_mac);
-  else
-    set_address(macp->config->mac_address);
-
-  /*
-   * PHY device identification.
-   */
-  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
-  if ((miiGet(&ETHD1, MII_PHYSID1) != (PHY_ID >> 16)) ||
-      ((miiGet(&ETHD1, MII_PHYSID2) & 0xFFF0) != (PHY_ID & 0xFFF0)))
-    chSysHalt();
-  AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
-
-  /*
-   * Interrupt configuration.
-   */
-  AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
-  AIC_ConfigureIT(AT91C_ID_EMAC,
-                  AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | EMAC_INTERRUPT_PRIORITY,
-                  irq_handler);
-  AIC_EnableIT(AT91C_ID_EMAC);
-}
-
-/**
- * @brief   Deactivates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_stop(MACDriver *macp) {
-
-  (void)macp;
-}
-
-/**
- * @brief   Returns a transmission descriptor.
- * @details One of the available transmission descriptors is locked and
- *          returned.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] tdp      pointer to a @p MACTransmitDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                      MACTransmitDescriptor *tdp) {
-  EMACDescriptor *edp;
-
-  (void)macp;
-
-  if (!macp->link_up)
-    return RDY_TIMEOUT;
-
-  chSysLock();
-  edp = txptr;
-  if (!(edp->w2 & W2_T_USED) || (edp->w2 & W2_T_LOCKED)) {
-    chSysUnlock();
-    return RDY_TIMEOUT;
-  }
-  /*
-   * Set the buffer size and configuration, the buffer is also marked
-   * as locked.
-   */
-  if (++txptr >= &td[EMAC_TRANSMIT_DESCRIPTORS]) {
-    edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER | W2_T_WRAP;
-    txptr = td;
-  }
-  else
-    edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER;
-  chSysUnlock();
-  tdp->offset = 0;
-  tdp->size = EMAC_TRANSMIT_BUFFERS_SIZE;
-  tdp->physdesc = edp;
-  return RDY_OK;
-}
-
-/**
- * @brief   Writes to a transmit descriptor's stream.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf       pointer to the buffer containing the data to be
- *                      written
- * @param[in] size      number of bytes to be written
- * @return              The number of bytes written into the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if the maximum
- *                      frame size is reached.
- *
- * @notapi
- */
-size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                         uint8_t *buf,
-                                         size_t size) {
-
-  if (size > tdp->size - tdp->offset)
-    size = tdp->size - tdp->offset;
-  if (size > 0) {
-    memcpy((uint8_t *)(tdp->physdesc->w1 & W1_T_ADDRESS_MASK) +
-                      tdp->offset,
-           buf, size);
-    tdp->offset += size;
-  }
-  return size;
-}
-
-/**
- * @brief   Releases a transmit descriptor and starts the transmission of the
- *          enqueued data as a single frame.
- *
- * @param[in] tdp       the pointer to the @p MACTransmitDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
-
-  chSysLock();
-  tdp->physdesc->w2 = (tdp->physdesc->w2 &
-                          ~(W2_T_LOCKED | W2_T_USED | W2_T_LENGTH_MASK)) |
-                         tdp->offset;
-  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
-  chSysUnlock();
-}
-
-/**
- * @brief   Returns a receive descriptor.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] rdp      pointer to a @p MACReceiveDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                     MACReceiveDescriptor *rdp) {
-  unsigned n;
-  EMACDescriptor *edp;
-
-  (void)macp;
-  n = EMAC_RECEIVE_DESCRIPTORS;
-
-  /*
-   * Skips unused buffers, if any.
-   */
-skip:
-  while ((n > 0) && !(rxptr->w1 & W1_R_OWNERSHIP)) {
-    if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS])
-      rxptr = rd;
-    n--;
-  }
-
-  /*
-   * Skips fragments, if any, cleaning them up.
-   */
-  while ((n > 0) && (rxptr->w1 & W1_R_OWNERSHIP) &&
-                    !(rxptr->w2 & W2_R_FRAME_START)) {
-    rxptr->w1 &= ~W1_R_OWNERSHIP;
-    if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS])
-      rxptr = rd;
-    n--;
-  }
-
-  /*
-   * Now compute the total frame size skipping eventual incomplete frames
-   * or holes...
-   */
-restart:
-  edp = rxptr;
-  while (n > 0) {
-    if (!(rxptr->w1 & W1_R_OWNERSHIP)) {
-      /* Empty buffer for some reason... cleaning up the incomplete frame.*/
-      cleanup(edp);
-      goto skip;
-    }
-    /*
-     * End Of Frame found.
-     */
-    if (rxptr->w2 & W2_R_FRAME_END) {
-      rdp->offset = 0;
-      rdp->size = rxptr->w2 & W2_T_LENGTH_MASK;
-      rdp->physdesc = edp;
-      return RDY_OK;
-    }
-
-    if ((edp != rxptr) && (rxptr->w2 & W2_R_FRAME_START)) {
-      /* Found another start... cleaning up the incomplete frame.*/
-      cleanup(edp);
-      goto restart;     /* Another start buffer for some reason... */
-    }
-
-    if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS])
-      rxptr = rd;
-    n--;
-  }
-  return RDY_TIMEOUT;
-}
-
-/**
- * @brief   Reads from a receive descriptor's stream.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[in] buf       pointer to the buffer that will receive the read data
- * @param[in] size      number of bytes to be read
- * @return              The number of bytes read from the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if there are
- *                      no more bytes to read.
- *
- * @notapi
- */
-size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                         uint8_t *buf,
-                                         size_t size) {
-  if (size > rdp->size - rdp->offset)
-    size = rdp->size - rdp->offset;
-  if (size > 0) {
-    uint8_t *src = (uint8_t *)(rdp->physdesc->w1 & W1_R_ADDRESS_MASK) +
-                   rdp->offset;
-    uint8_t *limit = &rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE];
-    if (src >= limit)
-      src -= EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE;
-    if (src + size > limit ) {
-      memcpy(buf, src, (size_t)(limit - src));
-      memcpy(buf + (size_t)(limit - src), rb, size - (size_t)(limit - src));
-    }
-    else
-      memcpy(buf, src, size);
-    rdp->offset += size;
-  }
-  return size;
-}
-
-/**
- * @brief   Releases a receive descriptor.
- * @details The descriptor and its buffer are made available for more incoming
- *          frames.
- *
- * @param[in] rdp       the pointer to the @p MACReceiveDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
-  bool_t done;
-  EMACDescriptor *edp = rdp->physdesc;
-
-  unsigned n = EMAC_RECEIVE_DESCRIPTORS;
-  do {
-    done = ((edp->w2 & W2_R_FRAME_END) != 0);
-    chDbgAssert(edp->w1 & W1_R_OWNERSHIP,
-                "mac_lld_release_receive_descriptor(), #1",
-                "found not owned descriptor");
-    edp->w1 &= ~(W1_R_OWNERSHIP | W2_R_FRAME_START | W2_R_FRAME_END);
-    if (++edp >= &rd[EMAC_RECEIVE_DESCRIPTORS])
-      edp = rd;
-    n--;
-  }
-  while ((n > 0) && !done);
-  /*
-   * Make rxptr point to the descriptor where the next frame will most
-   * likely appear.
-   */
-  rxptr = edp;
-}
-
-/**
- * @brief   Updates and returns the link status.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @return              The link status.
- * @retval TRUE         if the link is active.
- * @retval FALSE        if the link is down.
- *
- * @notapi
- */
-bool_t mac_lld_poll_link_status(MACDriver *macp) {
-  uint32_t ncfgr, bmsr, bmcr, lpa;
-
-  AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
-  (void)miiGet(macp, MII_BMSR);
-  bmsr = miiGet(macp, MII_BMSR);
-  if (!(bmsr & BMSR_LSTATUS)) {
-    AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
-    return macp->link_up = FALSE;
-  }
-
-  ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-  bmcr = miiGet(macp, MII_BMCR);
-  if (bmcr & BMCR_ANENABLE) {
-    lpa = miiGet(macp, MII_LPA);
-    if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
-      ncfgr |= AT91C_EMAC_SPD;
-    if (lpa & (LPA_10FULL | LPA_100FULL))
-      ncfgr |= AT91C_EMAC_FD;
-  }
-  else {
-    if (bmcr & BMCR_SPEED100)
-      ncfgr |= AT91C_EMAC_SPD;
-    if (bmcr & BMCR_FULLDPLX)
-      ncfgr |= AT91C_EMAC_FD;
-  }
-  AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr;
-  AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
-  return macp->link_up = TRUE;
-}
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/mac_lld.h b/os/hal/platforms/AT91SAM7/mac_lld.h
deleted file mode 100644
index 8a56b6793..000000000
--- a/os/hal/platforms/AT91SAM7/mac_lld.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/mac_lld.h
- * @brief   AT91SAM7 low level MAC driver header.
- *
- * @addtogroup MAC
- * @{
- */
-
-#ifndef _MAC_LLD_H_
-#define _MAC_LLD_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   This implementation does not support the zero-copy mode API.
- */
-#define MAC_SUPPORTS_ZERO_COPY      FALSE
-
-#define EMAC_RECEIVE_BUFFERS_SIZE       128     /* Do not modify */
-#define EMAC_TRANSMIT_BUFFERS_SIZE      MAC_BUFFERS_SIZE
-#define EMAC_RECEIVE_DESCRIPTORS                                            \
-    (((((MAC_BUFFERS_SIZE - 1) | (EMAC_RECEIVE_BUFFERS_SIZE - 1)) + 1)      \
-      / EMAC_RECEIVE_BUFFERS_SIZE) * MAC_RECEIVE_BUFFERS)
-#define EMAC_TRANSMIT_DESCRIPTORS       MAC_TRANSMIT_BUFFERS
-
-#define W1_R_OWNERSHIP          0x00000001
-#define W1_R_WRAP               0x00000002
-#define W1_R_ADDRESS_MASK       0xFFFFFFFC
-
-#define W2_R_LENGTH_MASK        0x00000FFF
-#define W2_R_FRAME_START        0x00004000
-#define W2_R_FRAME_END          0x00008000
-#define W2_R_CFI                0x00010000
-#define W2_R_VLAN_PRIO_MASK     0x000E0000
-#define W2_R_PRIO_TAG_DETECTED  0x00100000
-#define W2_R_VLAN_TAG_DETECTED  0x00200000
-#define W2_R_TYPE_ID_MATCH      0x00400000
-#define W2_R_ADDR4_MATCH        0x00800000
-#define W2_R_ADDR3_MATCH        0x01000000
-#define W2_R_ADDR2_MATCH        0x02000000
-#define W2_R_ADDR1_MATCH        0x04000000
-#define W2_R_RFU1               0x08000000
-#define W2_R_ADDR_EXT_MATCH     0x10000000
-#define W2_R_UNICAST_MATCH      0x20000000
-#define W2_R_MULTICAST_MATCH    0x40000000
-#define W2_R_BROADCAST_DETECTED 0x80000000
-
-#define W1_T_ADDRESS_MASK       0xFFFFFFFF
-
-#define W2_T_LENGTH_MASK        0x000007FF
-#define W2_T_LOCKED             0x00000800 /* Not an EMAC flag.             */
-#define W2_T_RFU1               0x00003000
-#define W2_T_LAST_BUFFER        0x00008000
-#define W2_T_NO_CRC             0x00010000
-#define W2_T_RFU2               0x07FE0000
-#define W2_T_BUFFERS_EXHAUSTED  0x08000000
-#define W2_T_TRANSMIT_UNDERRUN  0x10000000
-#define W2_T_RETRY_LIMIT_EXC    0x20000000
-#define W2_T_WRAP               0x40000000
-#define W2_T_USED               0x80000000
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of available transmit buffers.
- */
-#if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
-#define MAC_TRANSMIT_BUFFERS        2
-#endif
-
-/**
- * @brief   Number of available receive buffers.
- */
-#if !defined(MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
-#define MAC_RECEIVE_BUFFERS         2
-#endif
-
-/**
- * @brief   Maximum supported frame size.
- */
-#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define MAC_BUFFERS_SIZE            1518
-#endif
-
-/**
- * @brief   Interrupt priority level for the EMAC device.
- */
-#if !defined(EMAC_INTERRUPT_PRIORITY) || defined(__DOXYGEN__)
-#define EMAC_INTERRUPT_PRIORITY     (AT91C_AIC_PRIOR_HIGHEST - 3)
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Structure representing a buffer physical descriptor.
- * @note    It represents both descriptor types.
- */
-typedef struct {
-  uint32_t              w1;
-  uint32_t              w2;
-} EMACDescriptor;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief MAC address.
-   */
-  const uint8_t         *mac_address;
-  /* End of the mandatory fields.*/
-} MACConfig;
-
-/**
- * @brief   Structure representing a MAC driver.
- */
-struct MACDriver {
-  /**
-   * @brief Driver state.
-   */
-  macstate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const MACConfig       *config;
-  /**
-   * @brief Transmit semaphore.
-   */
-  Semaphore             tdsem;
-  /**
-   * @brief Receive semaphore.
-   */
-  Semaphore             rdsem;
-#if MAC_USE_EVENTS || defined(__DOXYGEN__)
-  /**
-   * @brief Receive event.
-   */
-  EventSource           rdevent;
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Link status flag.
-   */
-  bool_t                link_up;
-};
-
-/**
- * @brief   Structure representing a transmit descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current write offset.
-   */
-  size_t                offset;
-  /**
-   * @brief Available space size.
-   */
-  size_t                size;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the physical descriptor.
-   */
-  EMACDescriptor        *physdesc;
-} MACTransmitDescriptor;
-
-/**
- * @brief   Structure representing a receive descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current read offset.
-   */
-  size_t                offset;
-  /**
-   * @brief Available data size.
-   */
-  size_t                size;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the first descriptor of the buffers chain.
-   */
-  EMACDescriptor        *physdesc;
-} MACReceiveDescriptor;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern MACDriver ETHD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void mac_lld_init(void);
-  void mac_lld_start(MACDriver *macp);
-  void mac_lld_stop(MACDriver *macp);
-  msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                        MACTransmitDescriptor *tdp);
-  size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                           uint8_t *buf,
-                                           size_t size);
-  void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
-  msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                       MACReceiveDescriptor *rdp);
-  size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                         uint8_t *buf,
-                                         size_t size);
-  void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
-  bool_t mac_lld_poll_link_status(MACDriver *macp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _MAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/pal_lld.c b/os/hal/platforms/AT91SAM7/pal_lld.c
deleted file mode 100644
index 506d42d22..000000000
--- a/os/hal/platforms/AT91SAM7/pal_lld.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/pal_lld.c
- * @brief   AT91SAM7 PIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   AT91SAM7 I/O ports configuration.
- * @details PIO registers initialization.
- *
- * @param[in] config    the AT91SAM7 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  uint32_t ports = (1 << AT91C_ID_PIOA);
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
-    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-  ports |= (1 << AT91C_ID_PIOB);
-#endif
-  AT91C_BASE_PMC->PMC_PCER = ports;
-
-  /*
-   * PIOA setup.
-   */
-  AT91C_BASE_PIOA->PIO_PPUER  = config->P0Data.pusr;    /* Pull-up as spec.*/
-  AT91C_BASE_PIOA->PIO_PPUDR  = ~config->P0Data.pusr;
-  AT91C_BASE_PIOA->PIO_PER  = 0xFFFFFFFF;               /* PIO enabled.*/
-  AT91C_BASE_PIOA->PIO_ODSR = config->P0Data.odsr;      /* Data as specified.*/
-  AT91C_BASE_PIOA->PIO_OER  = config->P0Data.osr;       /* Dir. as specified.*/
-  AT91C_BASE_PIOA->PIO_ODR  = ~config->P0Data.osr;
-  AT91C_BASE_PIOA->PIO_IFDR = 0xFFFFFFFF;               /* Filter disabled.*/
-  AT91C_BASE_PIOA->PIO_IDR  = 0xFFFFFFFF;               /* Int. disabled.*/
-  AT91C_BASE_PIOA->PIO_MDDR = 0xFFFFFFFF;               /* Push Pull drive.*/
-  AT91C_BASE_PIOA->PIO_ASR  = 0xFFFFFFFF;               /* Peripheral A.*/
-  AT91C_BASE_PIOA->PIO_OWER = 0xFFFFFFFF;               /* Write enabled.*/
-
-  /*
-   * PIOB setup.
-   */
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
-    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-  AT91C_BASE_PIOB->PIO_PPUER  = config->P1Data.pusr;    /* Pull-up as spec.*/
-  AT91C_BASE_PIOB->PIO_PPUDR  = ~config->P1Data.pusr;
-  AT91C_BASE_PIOB->PIO_PER  = 0xFFFFFFFF;               /* PIO enabled.*/
-  AT91C_BASE_PIOB->PIO_ODSR = config->P1Data.odsr;      /* Data as specified.*/
-  AT91C_BASE_PIOB->PIO_OER  = config->P1Data.osr;       /* Dir. as specified.*/
-  AT91C_BASE_PIOB->PIO_ODR  = ~config->P1Data.osr;
-  AT91C_BASE_PIOB->PIO_IFDR = 0xFFFFFFFF;               /* Filter disabled.*/
-  AT91C_BASE_PIOB->PIO_IDR  = 0xFFFFFFFF;               /* Int. disabled.*/
-  AT91C_BASE_PIOB->PIO_MDDR = 0xFFFFFFFF;               /* Push Pull drive.*/
-  AT91C_BASE_PIOB->PIO_ASR  = 0xFFFFFFFF;               /* Peripheral A.*/
-  AT91C_BASE_PIOB->PIO_OWER = 0xFFFFFFFF;               /* Write enabled.*/
-#endif
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    This function is not meant to be invoked directly from the
- *          application code.
- * @note    @p PAL_MODE_RESET is implemented as input with pull-up.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    @p PAL_MODE_OUTPUT_OPENDRAIN also enables the pull-up resistor.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT_PULLUP:
-    port->PIO_PPUER = mask;
-    port->PIO_ODR = mask;
-    break;
-  case PAL_MODE_INPUT:
-  case PAL_MODE_INPUT_ANALOG:
-    port->PIO_PPUDR = mask;
-    port->PIO_ODR = mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    port->PIO_SODR = mask;
-    /* Falls in */
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->PIO_PPUDR = mask;
-    port->PIO_OER = mask;
-    port->PIO_MDDR = mask;
-    break;
-  case PAL_MODE_OUTPUT_OPENDRAIN:
-    port->PIO_PPUER = mask;
-    port->PIO_OER = mask;
-    port->PIO_MDER = mask;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/pal_lld.h b/os/hal/platforms/AT91SAM7/pal_lld.h
deleted file mode 100644
index 761a7142a..000000000
--- a/os/hal/platforms/AT91SAM7/pal_lld.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/pal_lld.h
- * @brief   AT91SAM7 PIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLDOWN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   PIO port setup info.
- */
-typedef struct {
-  /** Initial value for ODSR register (data).*/
-  uint32_t      odsr;
-  /** Initial value for OSR register (direction).*/
-  uint32_t      osr;
-  /** Initial value for PUSR register (Pull-ups).*/
-  uint32_t      pusr;
-} at91sam7_pio_setup_t;
-
-/**
- * @brief   AT91SAM7 PIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialize the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-  /** @brief Port 0 setup data.*/
-  at91sam7_pio_setup_t P0Data;
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
-    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) || \
-    defined(__DOXYGEN__)
-  /** @brief Port 1 setup data.*/
-  at91sam7_pio_setup_t P1Data;
-#endif
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- *          any assumption about it, use the provided macros when populating
- *          variables of this type.
- */
-typedef AT91PS_PIO ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   PIO port A identifier.
- */
-#define IOPORT1         AT91C_BASE_PIOA
-
-/**
- * @brief   PIO port B identifier.
- */
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
-    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) || \
-    defined(__DOXYGEN__)
-#define IOPORT2         AT91C_BASE_PIOB
-#endif
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- * @details This function is implemented by reading the PIO_PDSR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->PIO_PDSR)
-
-/**
- * @brief   Reads the output latch.
- * @details This function is implemented by reading the PIO_ODSR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->PIO_ODSR)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- * @details This function is implemented by writing the PIO_ODSR register, the
- *          implementation has no side effects.
- *
- * @param[in] port the port identifier
- * @param[in] bits the bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->PIO_ODSR = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @details This function is implemented by writing the PIO_SODR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->PIO_SODR = (bits))
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @details This function is implemented by writing the PIO_CODR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) ((port)->PIO_CODR = (bits))
-
-/**
- * @brief   Writes a group of bits.
- * @details This function is implemented by writing the PIO_OWER, PIO_ODSR and
- *          PIO_OWDR registers, the implementation is not atomic because the
- *          multiple accesses.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    the group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group
- *                      width are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                    \
-  ((port)->PIO_OWER = (mask) << (offset),                               \
-   (port)->PIO_ODSR = (bits) << (offset),                               \
-   (port)->PIO_OWDR = (mask) << (offset))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/platform.dox b/os/hal/platforms/AT91SAM7/platform.dox
deleted file mode 100644
index ec810c211..000000000
--- a/os/hal/platforms/AT91SAM7/platform.dox
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup AT91SAM7 AT91SAM7 Drivers
- * @details This section describes all the supported drivers on the AT91SAM7
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup AT91SAM7_HAL AT91SAM7 Initialization Support
- * @details The AT91SAM7 HAL support is responsible for system initialization.
- *
- * @section at91sam7_hal_1 Supported HW resources
- * - MC.
- * - PMC.
- * .
- * @section at91sam7_hal_2 AT91SAM7 HAL driver implementation features
- * - PLLs startup and stabilization.
- * - Clock source selection.
- * - Flash wait states.
- * .
-* @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_MAC AT91SAM7 MAC Support
- * @details The AT91SAM7 MAC driver supports the EMAC peripheral.
- *
- * @section at91sam7_mac_1 Supported HW resources
- * - EMAC.
- * .
- * @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_MII AT91SAM7 MII Support
- * @details This driver supports the AT91SAM7 EMAC peripheral communicating
- *          with an external PHY transceiver. The driver currently supports
- *          the Micrel KS8721 PHY and the Davicom DV9161 modules. This driver
- *          is used internally by the MAC driver.
- *
- * @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_PAL AT91SAM7 PAL Support
- * @details The AT91SAM7 PAL driver supports the PIO peripherals.
- *
- * @section at91sam7_pal_1 Supported HW resources
- * - PIOA.
- * - PIOB.
- * .
- * @section at91sam7_pal_2 AT91SAM7 PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 32 bits wide ports.
- * - Atomic set/reset functions.
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section at91sam7_pal_3 Supported PAL setup modes
- * The AT91SAM7 PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_ANALOG (same as @p PAL_MODE_INPUT).
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section at91sam7_pal_4 Suboptimal behavior
- * The AT91SAM7 PIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * .
- * @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_SERIAL AT91SAM7 Serial Support
- * @details The AT91SAM7 Serial driver uses the USART/UART peripherals in a
- *          buffered, interrupt driven, implementation.
- *
- * @section at91sam7_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - DBGU.
- * .
- * @section at91sam7_serial_2 AT91SAM7 Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each USART can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable priority levels for each USART.
- * .
- * @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_SPI AT91SAM7 SPI Support
- * @details The SPI driver supports the AT91SAM7 SPI peripherals using DMA
- *          channels for maximum performance.
- *
- * @section at91sam7_spi_1 Supported HW resources
- * - SPI1.
- * - SPI2.
- * .
- * @section at91sam7_spi_2 AT91SAM7 SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SPI can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each SPI.
- * - DMA is used for receiving and transmitting.
- * .
- * @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_CAN AT91SAM7 CAN Support
- * @details The CAN driver supports the AT91SAM7 CAN peripherals.
- *
- * @section at91sam7_can_1 Supported HW resources
- * - CAN.
- * .
- * @section at91sam7_can_1 AT91SAM7 CAN driver implementation features
- * - one send mailbox and seven receive mailboxes.
- * - wakeup event on receive data.
- * - deactivate unused mailbox to decrease memory usage and CPU usage
- * .
- * @ingroup AT91SAM7
- */
diff --git a/os/hal/platforms/AT91SAM7/platform.mk b/os/hal/platforms/AT91SAM7/platform.mk
deleted file mode 100644
index 1f173f9d5..000000000
--- a/os/hal/platforms/AT91SAM7/platform.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# List of all the AT91SAM7 platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AT91SAM7/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/mac_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/can_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91sam7_mii.c \
-              ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91lib/aic.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/AT91SAM7
diff --git a/os/hal/platforms/AT91SAM7/pwm_lld.c b/os/hal/platforms/AT91SAM7/pwm_lld.c
deleted file mode 100644
index 7d4060427..000000000
--- a/os/hal/platforms/AT91SAM7/pwm_lld.c
+++ /dev/null
@@ -1,467 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   This file has been contributed by:
-		Andrew Hannam aka inmarket.
-*/
-
-/**
- * @file    AT91SAM7/pwm_lld.c
- * @brief   AT91SAM7 PWM Driver subsystem low level driver source.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#ifdef UNUSED 
-#elif defined(__GNUC__) 
-# define UNUSED(x) UNUSED_ ## x __attribute__((unused)) 
-#elif defined(__LCLINT__) 
-# define UNUSED(x) /*@unused@*/ x 
-#else 
-# define UNUSED(x) x 
-#endif 
-
-#define PWMC_M	((AT91S_PWMC *)AT91C_PWMC_MR)
-
-#define PWM_MCK_MASK					0x0F00
-#define PWM_MCK_SHIFT					8
-
-typedef struct pindef {
-	uint32_t	portpin;	/* Set to 0 if this pin combination is invalid */
-	AT91S_PIO	*pio;
-	AT91_REG	*perab;
-} pindef_t;
-
-typedef struct pwmpindefs {
-	pindef_t	pin[3];
-} pwmpindefs_t;
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-#if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) ||            \
-    (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512)
-
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP1 = {{
-		{ AT91C_PA0_PWM0 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_ASR },
-		{ AT91C_PA11_PWM0, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
-		{ AT91C_PA23_PWM0, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
-	}};
-#endif
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP2 = {{
-		{ AT91C_PA1_PWM1 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_ASR },
-		{ AT91C_PA12_PWM1, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
-		{ AT91C_PA24_PWM1, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
-	}};
-#endif
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP3 = {{
-		{ AT91C_PA2_PWM2 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_ASR },
-		{ AT91C_PA13_PWM2, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
-		{ AT91C_PA25_PWM2, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
-	}};
-#endif
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP4 = {{
-		{ AT91C_PA7_PWM3 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
-		{ AT91C_PA14_PWM3, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
-		{ 0, 0, 0 },
-	}};
-#endif
-
-#elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) ||         \
-      (SAM7_PLATFORM == SAM7X512)
-
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP1 = {{
-		{ AT91C_PB19_PWM0, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR },
-		{ AT91C_PB27_PWM0, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR },
-		{ 0, 0, 0 },
-	}};
-#endif
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP2 = {{
-		{ AT91C_PB20_PWM1, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR },
-		{ AT91C_PB28_PWM1, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR },
-		{ 0, 0, 0 },
-	}};
-#endif
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP3 = {{
-		{ AT91C_PB21_PWM2, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR },
-		{ AT91C_PB29_PWM2, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR },
-		{ 0, 0, 0 },
-	}};
-#endif
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP4 = {{
-		{ AT91C_PB22_PWM3, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR },
-		{ AT91C_PB30_PWM3, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR },
-		{ 0, 0, 0 },
-	}};
-#endif
-
-#else
-	#error "PWM pins not defined for this SAM7 version"
-#endif
-
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-/**
- * @brief   Common IRQ handler.
- */
-static void pwm_lld_serve_interrupt(void) {
-	uint32_t	isr;
-	
-	isr = PWMC_M->PWMC_ISR;
-#if PWM_USE_PWM1
-	if ((isr & 1) && PWMD1.config->channels[0].callback)
-		PWMD1.config->channels[0].callback(&PWMD1);
-#endif
-#if PWM_USE_PWM2
-	if ((isr & 2) && PWMD2.config->channels[0].callback)
-		PWMD2.config->channels[0].callback(&PWMD2);
-#endif
-#if PWM_USE_PWM3
-	if ((isr & 4) && PWMD3.config->channels[0].callback)
-		PWMD3.config->channels[0].callback(&PWMD3);
-#endif
-#if PWM_USE_PWM4
-	if ((isr & 8) && PWMD4.config->channels[0].callback)
-		PWMD4.config->channels[0].callback(&PWMD4);
-#endif
-}
-
-CH_IRQ_HANDLER(PWMIrqHandler) {
-  CH_IRQ_PROLOGUE();
-  pwm_lld_serve_interrupt();
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-	/* Driver initialization.*/
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
-	pwmObjectInit(&PWMD1);
-	PWMD1.chbit = 1;
-	PWMD1.reg = AT91C_BASE_PWMC_CH0;
-	PWMD1.pins = &PWMP1;
-#endif
-
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-	pwmObjectInit(&PWMD2);
-	PWMD2.chbit = 2;
-	PWMD2.reg = AT91C_BASE_PWMC_CH1;
-	PWMD2.pins = &PWMP2;
-#endif
-
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-	pwmObjectInit(&PWMD3);
-	PWMD3.chbit = 4;
-	PWMD3.reg = AT91C_BASE_PWMC_CH2;
-	PWMD3.pins = &PWMP3;
-#endif
-
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-	pwmObjectInit(&PWMD4);
-	PWMD4.chbit = 8;
-	PWMD4.reg = AT91C_BASE_PWMC_CH3;
-	PWMD4.pins = &PWMP4;
-#endif
-
-	/* Turn on PWM in the power management controller */
-	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PWMC);
-  
-	/* Setup interrupt handler */
-	PWMC_M->PWMC_IDR = 0xFFFFFFFF;
-	AIC_ConfigureIT(AT91C_ID_PWMC,
-		  AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_PWM_PRIORITY,
-		  PWMIrqHandler);
-    AIC_EnableIT(AT91C_ID_PWMC);
-}
-
-/**
- * @brief   Configures and activates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-	uint32_t	mode, mr, div, pre;
-
-	/* Steps:
-		1. Turn the IO pin to a PWM output
-		2. Configuration of Clock if DIVA or DIVB used
-		3. Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
-		4. Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)
-		5. Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register)
-		6. Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in
-			PWM_CPRDx Register is possible while the channel is disabled. After validation of the
-			channel, the user must use PWM_CUPDx Register to update PWM_CPRDx
-		7. Enable Interrupts (Writing CHIDx in the PWM_IER register)
-	*/
-
-	/* Make sure it is off first */
-	pwm_lld_disable_channel(pwmp, 0);
-
-	/* Configuration.*/
-	mode = pwmp->config->channels[0].mode;
-
-	/* Step 1 */
-	if (mode & PWM_OUTPUT_PIN1) {
-		pwmp->pins->pin[0].perab[0]		= pwmp->pins->pin[0].portpin;		/* Select A or B peripheral */
-		pwmp->pins->pin[0].pio->PIO_PDR	= pwmp->pins->pin[0].portpin;		/* Turn PIO into PWM output */
-		pwmp->pins->pin[0].pio->PIO_MDDR	= pwmp->pins->pin[0].portpin;		/* Turn off PIO multi-drive */
-		if (mode & PWM_DISABLEPULLUP_PIN1)
-			pwmp->pins->pin[0].pio->PIO_PPUDR	= pwmp->pins->pin[0].portpin;	/* Turn off PIO pullup */
-		else
-			pwmp->pins->pin[0].pio->PIO_PPUER	= pwmp->pins->pin[0].portpin;	/* Turn on PIO pullup */
-	}
-	if (mode & PWM_OUTPUT_PIN2) {
-		pwmp->pins->pin[1].perab[0]		= pwmp->pins->pin[1].portpin;
-		pwmp->pins->pin[1].pio->PIO_PDR	= pwmp->pins->pin[1].portpin;
-		pwmp->pins->pin[1].pio->PIO_MDDR	= pwmp->pins->pin[1].portpin;
-		if (mode & PWM_DISABLEPULLUP_PIN2)
-			pwmp->pins->pin[1].pio->PIO_PPUDR	= pwmp->pins->pin[1].portpin;
-		else
-			pwmp->pins->pin[1].pio->PIO_PPUER	= pwmp->pins->pin[1].portpin;
-	}
-	if ((mode & PWM_OUTPUT_PIN3) && pwmp->pins->pin[2].portpin) {
-		pwmp->pins->pin[2].perab[0]		= pwmp->pins->pin[2].portpin;
-		pwmp->pins->pin[2].pio->PIO_PDR	= pwmp->pins->pin[2].portpin;
-		pwmp->pins->pin[2].pio->PIO_MDDR	= pwmp->pins->pin[2].portpin;
-		if (mode & PWM_DISABLEPULLUP_PIN3)
-			pwmp->pins->pin[2].pio->PIO_PPUDR	= pwmp->pins->pin[2].portpin;
-		else
-			pwmp->pins->pin[2].pio->PIO_PPUER	= pwmp->pins->pin[2].portpin;
-	}
-
-	/* Step 2 */
-	if ((mode & PWM_MCK_MASK) == PWM_MCK_DIV_CLKA) {
-		if (!pwmp->config->frequency) {
-			/* As slow as we go */
-			PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0xFFFF0000) | (10 << 8) | (255 << 0);
-		} else if (pwmp->config->frequency > MCK) {
-			/* Just use MCLK */
-			mode &= ~PWM_MCK_MASK;
-		} else {
-			div = MCK / pwmp->config->frequency;
-			if (mode & PWM_OUTPUT_CENTER) div >>= 1;
-			for(pre = 0; div > 255 && pre < 10; pre++) div >>= 1;
-			if (div > 255) div = 255;
-			PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0xFFFF0000) | (pre << 8) | (div << 0);
-		}
-	} else if ((mode & PWM_MCK_MASK) == PWM_MCK_DIV_CLKB) {
-		if (!pwmp->config->frequency) {
-			/* As slow as we go */
-			PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0x0000FFFF) | (10 << 24) | (255 << 16);
-		} else if (pwmp->config->frequency > MCK) {
-			/* Just use MCLK */
-			mode &= ~PWM_MCK_MASK;
-		} else {
-			div = MCK / pwmp->config->frequency;
-			if (mode & PWM_OUTPUT_CENTER) div >>= 1;
-			for(pre = 0; div > 255 && pre < 10; pre++) div >>= 1;
-			if (div > 255) div = 255;
-			PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0x0000FFFF) | (pre << 24) | (div << 16);
-		}
-	}
-
-	/* Step 3 -> 5 */
-	mr = (mode & PWM_MCK_MASK) >> PWM_MCK_SHIFT;
-	if (mode & PWM_OUTPUT_CENTER) mr |= AT91C_PWMC_CALG;
-	if (mode & PWM_OUTPUT_ACTIVE_HIGH) mr |= AT91C_PWMC_CPOL;
-	pwmp->reg->PWMC_CMR = mr;
-
-	/* Step 6 */
-	pwmp->reg->PWMC_CPRDR = pwmp->period;
-	
-	/* Step 7 */
-	if (pwmp->config->channels[0].callback)
-		PWMC_M->PWMC_IER = pwmp->chbit;
-}
-
-/**
- * @brief   Deactivates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-	/* Make sure it is off */
-	pwm_lld_disable_channel(pwmp, 0);
-	
-	/* Turn the pin back to a PIO pin - we have forgotten pull-up and multi-drive state for the pin though */
-	if (pwmp->config->channels[0].mode & PWM_OUTPUT_PIN1)
-		pwmp->pins->pin[0].pio->PIO_PER	= pwmp->pins->pin[0].portpin;
-	if (pwmp->config->channels[0].mode & PWM_OUTPUT_PIN2)
-		pwmp->pins->pin[1].pio->PIO_PER	= pwmp->pins->pin[1].portpin;
-	if ((pwmp->config->channels[0].mode & PWM_OUTPUT_PIN3) && pwmp->pins->pin[2].portpin)
-		pwmp->pins->pin[2].pio->PIO_PER	= pwmp->pins->pin[2].portpin;
-}
-
-/**
- * @brief   Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- *          been activated using @p pwmStart().
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The PWM unit period is changed to the new value.
- * @note    The function has effect at the next cycle start.
- * @note    If a period is specified that is shorter than the pulse width
- *          programmed in one of the channels then the behavior is not
- *          guaranteed.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] period    new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
-	pwmp->period = period;
-	
-	if (PWMC_M->PWMC_SR & pwmp->chbit) {
-		pwmp->reg->PWMC_CMR |= AT91C_PWMC_CPD;
-		pwmp->reg->PWMC_CUPDR = period;
-	} else {
-		pwmp->reg->PWMC_CPRDR = period;
-	}
-}
-
-/**
- * @brief   Enables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is active using the specified configuration.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t UNUSED(channel),
-                            pwmcnt_t width) {
-	/*
-		6. Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register).
-			Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of
-			the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx.
-		7. Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
-	*/
-
-	/* Step 6 */
-	if (PWMC_M->PWMC_SR & pwmp->chbit) {
-		pwmp->reg->PWMC_CMR &= ~AT91C_PWMC_CPD;
-		pwmp->reg->PWMC_CUPDR = width;
-	} else {
-		pwmp->reg->PWMC_CDTYR = width;
-		PWMC_M->PWMC_ENA = pwmp->chbit;
-	}
-	
-	/* Step 7 */
-	PWMC_M->PWMC_ENA = pwmp->chbit;
-}
-
-/**
- * @brief   Disables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is disabled and its output line returned to the
- *          idle state.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t UNUSED(channel)) {
-	PWMC_M->PWMC_IDR = pwmp->chbit;
-	PWMC_M->PWMC_DIS = pwmp->chbit;
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/pwm_lld.h b/os/hal/platforms/AT91SAM7/pwm_lld.h
deleted file mode 100644
index cb1a830ff..000000000
--- a/os/hal/platforms/AT91SAM7/pwm_lld.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   This file has been contributed by:
-		Andrew Hannam aka inmarket.
-*/
-/**
- * @file    AT91SAM7/pwm_lld.h
- * @brief   AT91SAM7 PWM Driver subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS        1
-
-/**
- * @brief   PWM device interrupt priority level setting.
- */
-#if !defined(AT91SAM7_PWM_PRIORITY) || defined(__DOXYGEN__)
-#define AT91SAM7_PWM_PRIORITY          (AT91C_AIC_PRIOR_HIGHEST - 4)
-#endif
-
-/**
- * @brief   PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(PWM_USE_PWM1) || defined(__DOXYGEN__)
-#define PWM_USE_PWM1					TRUE
-#endif
-
-/**
- * @brief   PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(PWM_USE_PWM2) || defined(__DOXYGEN__)
-#define PWM_USE_PWM2					TRUE
-#endif
-
-/**
- * @brief   PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(PWM_USE_PWM3) || defined(__DOXYGEN__)
-#define PWM_USE_PWM3					TRUE
-#endif
-
-/**
- * @brief   PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(PWM_USE_PWM4) || defined(__DOXYGEN__)
-#define PWM_USE_PWM4					TRUE
-#endif
-
-/**
- * @brief   PWM left (count up) logic
- */
-#define PWM_OUTPUT_LEFT					0x00000000
-
-/**
- * @brief   PWM center (count up-down) logic. Gives symetric waveform
- */
-#define PWM_OUTPUT_CENTER				0x00000010
-
-/**
- * @brief   PWM Master Clock = MCK / 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, CLKA or CLKB. CLKA or CLKB uses the frequency field
- */
-#define PWM_MCK_DIV_1					0x00000000
-#define PWM_MCK_DIV_2					0x00000100
-#define PWM_MCK_DIV_4					0x00000200
-#define PWM_MCK_DIV_8					0x00000300
-#define PWM_MCK_DIV_16					0x00000400
-#define PWM_MCK_DIV_32					0x00000500
-#define PWM_MCK_DIV_64					0x00000600
-#define PWM_MCK_DIV_128					0x00000700
-#define PWM_MCK_DIV_256					0x00000800
-#define PWM_MCK_DIV_512					0x00000900
-#define PWM_MCK_DIV_1024				0x00000A00
-#define PWM_MCK_DIV_CLKA				0x00000B00
-#define PWM_MCK_DIV_CLKB				0x00000C00
-
-/**
- * @brief   Which PWM output pins to turn on. PIN1 is the lowest numbered pin, PIN2 next lowest, and then on some packages PIN3.
- */
-#define PWM_OUTPUT_PIN1					0x00001000
-#define PWM_OUTPUT_PIN2					0x00002000
-#define PWM_OUTPUT_PIN3					0x00004000
-
-/**
- * @brief   Which PWM output pins should have pullups disabled.
- */
-#define PWM_DISABLEPULLUP_PIN1			0x00010000
-#define PWM_DISABLEPULLUP_PIN2			0x00020000
-#define PWM_DISABLEPULLUP_PIN3			0x00040000
-
- /*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief   PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief   PWM counter type.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief   PWM driver channel configuration structure.
- * @note    Some architectures may not be able to support the channel mode
- *          or the callback, in this case the fields are ignored.
- */
-typedef struct {
-  /**
-   * @brief Channel active logic level.
-   */
-  pwmmode_t                 mode;
-  /**
-   * @brief Channel callback pointer.
-   * @note  This callback is invoked on the channel compare event. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  uint32_t                  frequency;
-  /**
-   * @brief   PWM period in ticks.
-   * @note    The low level can use assertions in order to catch invalid
-   *          period specifications.
-   */
-  pwmcnt_t                  period;
-  /**
-   * @brief Periodic callback pointer.
-   * @note  This callback is invoked on PWM counter reset. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /**
-   * @brief Channels configurations.
-   */
-  PWMChannelConfig          channels[PWM_CHANNELS];
-  /* End of the mandatory fields.*/
-} PWMConfig;
-
-/**
- * @brief   Structure representing an PWM driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct PWMDriver {
-  /**
-   * @brief Driver state.
-   */
-  pwmstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const PWMConfig           *config;
-  /**
-   * @brief   Current PWM period in ticks.
-   */
-  pwmcnt_t                  period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
-  PWM_DRIVER_EXT_FIELDS
-#endif
-
-  /* End of the mandatory fields.*/
-
-  /**
-   * @brief The PWM internal channel number as a bit mask (1, 2, 4 or 8).
-   */
-  uint32_t					chbit;
-  /**
-   * @brief Pointer to the PWMCx registers block.
-   */
-  AT91S_PWMC_CH             *reg;
-  /**
-   * @brief Pointer to the output pins descriptor.
-   */
-  const struct pwmpindefs	*pins;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void pwm_lld_init(void);
-  void pwm_lld_start(PWMDriver *pwmp);
-  void pwm_lld_stop(PWMDriver *pwmp);
-  void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
-  void pwm_lld_enable_channel(PWMDriver *pwmp,
-                              pwmchannel_t channel,
-                              pwmcnt_t width);
-  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/serial_lld.c b/os/hal/platforms/AT91SAM7/serial_lld.c
deleted file mode 100644
index e586a6342..000000000
--- a/os/hal/platforms/AT91SAM7/serial_lld.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/serial_lld.c
- * @brief   AT91SAM7 low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-#if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) ||            \
-    (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512)
-
-#define SAM7_USART0_RX    AT91C_PA5_RXD0
-#define SAM7_USART0_TX    AT91C_PA6_TXD0
-#define SAM7_USART1_RX    AT91C_PA21_RXD1
-#define SAM7_USART1_TX    AT91C_PA22_TXD1
-#define SAM7_DBGU_RX      AT91C_PA9_DRXD
-#define SAM7_DBGU_TX      AT91C_PA10_DTXD
-
-#elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) ||         \
-      (SAM7_PLATFORM == SAM7X512)
-
-#define SAM7_USART0_RX    AT91C_PA0_RXD0
-#define SAM7_USART0_TX    AT91C_PA1_TXD0
-#define SAM7_USART1_RX    AT91C_PA5_RXD1
-#define SAM7_USART1_TX    AT91C_PA6_TXD1
-#define SAM7_DBGU_RX      AT91C_PA27_DRXD
-#define SAM7_DBGU_TX      AT91C_PA28_DTXD
-
-#elif (SAM7_PLATFORM == SAM7A3)
-#define SAM7_USART0_RX    AT91C_PA2_RXD0
-#define SAM7_USART0_TX    AT91C_PA3_TXD0
-#define SAM7_USART1_RX    AT91C_PA7_RXD1
-#define SAM7_USART1_TX    AT91C_PA8_TXD1
-#define SAM7_USART2_RX    AT91C_PA9_RXD2
-#define SAM7_USART2_TX    AT91C_PA10_TXD2
-#define SAM7_DBGU_RX      AT91C_PA30_DRXD
-#define SAM7_DBGU_TX      AT91C_PA31_DTXD
-
-#else
-#error "serial lines not defined for this SAM7 version"
-#endif /* HAL_USE_SERIAL */
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if USE_SAM7_USART0 || defined(__DOXYGEN__)
-/** @brief USART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-#if USE_SAM7_USART1 || defined(__DOXYGEN__)
-/** @brief USART1 serial driver identifier.*/
-SerialDriver SD2;
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2 || defined(__DOXYGEN__)
-/** @brief USART2 serial driver identifier.*/
-SerialDriver SD3;
-#endif
-#endif
-
-#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__)
-/** @brief DBGU_UART serial driver identifier.*/
-SerialDriver SDDBG;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
-  AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   USART initialization.
- *
- * @param[in] sdp       communication channel associated to the USART
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
-  AT91PS_USART u = sdp->usart;
-
-  /* Disables IRQ sources and stop operations.*/
-  u->US_IDR = 0xFFFFFFFF;
-  u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA;
-
-  /* New parameters setup.*/
-  if (config->sc_mr & AT91C_US_OVER)
-    u->US_BRGR = MCK / (config->sc_speed * 8);
-  else
-    u->US_BRGR = MCK / (config->sc_speed * 16);
-  u->US_MR = config->sc_mr;
-  u->US_RTOR = 0;
-  u->US_TTGR = 0;
-
-  /* Enables operations and IRQ sources.*/
-  u->US_CR = AT91C_US_RXEN | AT91C_US_TXEN | AT91C_US_DTREN | AT91C_US_RTSEN;
-  u->US_IER = AT91C_US_RXRDY | AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE |
-              AT91C_US_RXBRK;
-}
-
-/**
- * @brief   USART de-initialization.
- *
- * @param[in] u         pointer to an USART I/O block
- */
-static void usart_deinit(AT91PS_USART u) {
-
-  /* Disables IRQ sources and stop operations.*/
-  u->US_IDR = 0xFFFFFFFF;
-  u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA;
-  u->US_MR = 0;
-  u->US_RTOR = 0;
-  u->US_TTGR = 0;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] err       USART CSR register value
- * @param[in] sdp       communication channel associated to the USART
- */
-static void set_error(SerialDriver *sdp, AT91_REG csr) {
-  flagsmask_t sts = 0;
-
-  if (csr & AT91C_US_OVRE)
-    sts |= SD_OVERRUN_ERROR;
-  if (csr & AT91C_US_PARE)
-    sts |= SD_PARITY_ERROR;
-  if (csr & AT91C_US_FRAME)
-    sts |= SD_FRAMING_ERROR;
-  if (csr & AT91C_US_RXBRK)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-#if !USE_SAM7_DBGU_UART
-static
-#endif
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] sdp       communication channel associated to the USART
- */
-void sd_lld_serve_interrupt(SerialDriver *sdp) {
-  uint32_t csr;
-  AT91PS_USART u = sdp->usart;
-
-  csr = u->US_CSR;
-  if (csr & AT91C_US_RXRDY) {
-    chSysLockFromIsr();
-    sdIncomingDataI(sdp, u->US_RHR);
-    chSysUnlockFromIsr();
-  }
-  if ((u->US_IMR & AT91C_US_TXRDY) && (csr & AT91C_US_TXRDY)) {
-    msg_t b;
-
-    chSysLockFromIsr();
-    b = chOQGetI(&sdp->oqueue);
-    if (b < Q_OK) {
-      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-      u->US_IDR = AT91C_US_TXRDY;
-    }
-    else
-      u->US_THR = b;
-    chSysUnlockFromIsr();
-  }
-  csr &= (AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE | AT91C_US_RXBRK);
-  if (csr != 0) {
-    set_error(sdp, csr);
-    u->US_CR = AT91C_US_RSTSTA;
-  }
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-}
-
-#if USE_SAM7_USART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  AT91C_BASE_US0->US_IER = AT91C_US_TXRDY;
-}
-#endif
-
-#if USE_SAM7_USART1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  AT91C_BASE_US1->US_IER = AT91C_US_TXRDY;
-}
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
-  (void)qp;
-  AT91C_BASE_US2->US_IER = AT91C_US_TXRDY;
-}
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__)
-static void notify_dbg(GenericQueue *qp) {
-
-  (void)qp;
-  AT91C_BASE_DBGU->DBGU_IER = AT91C_US_TXRDY;
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if USE_SAM7_USART0 || defined(__DOXYGEN__)
-/**
- * @brief   USART0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART0IrqHandler) {
-
-  CH_IRQ_PROLOGUE();
-  sd_lld_serve_interrupt(&SD1);
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if USE_SAM7_USART1 || defined(__DOXYGEN__)
-/**
- * @brief   USART1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART1IrqHandler) {
-
-  CH_IRQ_PROLOGUE();
-  sd_lld_serve_interrupt(&SD2);
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2 || defined(__DOXYGEN__)
-/**
- * @brief   USART2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART2IrqHandler) {
-
-  CH_IRQ_PROLOGUE();
-  sd_lld_serve_interrupt(&SD3);
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-/* note - DBGU_UART IRQ is the SysIrq in board.c
-   since it's not vectored separately by the AIC.*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if USE_SAM7_USART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.usart = AT91C_BASE_US0;
-  AT91C_BASE_PIOA->PIO_PDR   = SAM7_USART0_RX | SAM7_USART0_TX;
-  AT91C_BASE_PIOA->PIO_ASR   = SAM7_USART0_RX | SAM7_USART0_TX;
-  AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART0_RX | SAM7_USART0_TX;
-  AIC_ConfigureIT(AT91C_ID_US0,
-                  AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART0_PRIORITY,
-                  USART0IrqHandler);
-#endif
-
-#if USE_SAM7_USART1
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.usart = AT91C_BASE_US1;
-  AT91C_BASE_PIOA->PIO_PDR   = SAM7_USART1_RX | SAM7_USART1_TX;
-  AT91C_BASE_PIOA->PIO_ASR   = SAM7_USART1_RX | SAM7_USART1_TX;
-  AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART1_RX | SAM7_USART1_TX;
-  AIC_ConfigureIT(AT91C_ID_US1,
-                  AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART1_PRIORITY,
-                  USART1IrqHandler);
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2
-  sdObjectInit(&SD3, NULL, notify3);
-  SD3.usart = AT91C_BASE_US2;
-  AT91C_BASE_PIOA->PIO_PDR   = SAM7_USART2_RX | SAM7_USART2_TX;
-  AT91C_BASE_PIOA->PIO_ASR   = SAM7_USART2_RX | SAM7_USART2_TX;
-  AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART2_RX | SAM7_USART2_TX;
-  AIC_ConfigureIT(AT91C_ID_US2,
-                  AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART2_PRIORITY,
-                  USART2IrqHandler);
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-#if USE_SAM7_DBGU_UART
-  sdObjectInit(&SDDBG, NULL, notify_dbg);
-  /* this is a little cheap, but OK for now since there's enough overlap
-     between dbgu and usart register maps.  it means we can reuse all the
-     same usart interrupt handling and config that already exists.*/
-  SDDBG.usart = (AT91PS_USART)AT91C_BASE_DBGU;
-  AT91C_BASE_PIOA->PIO_PDR   = SAM7_DBGU_RX | SAM7_DBGU_TX;
-  AT91C_BASE_PIOA->PIO_ASR   = SAM7_DBGU_RX | SAM7_DBGU_TX;
-  AT91C_BASE_PIOA->PIO_PPUDR = SAM7_DBGU_RX | SAM7_DBGU_TX;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if USE_SAM7_USART0
-    if (&SD1 == sdp) {
-      /* Starts the clock and clears possible sources of immediate interrupts.*/
-      AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US0);
-      /* Enables associated interrupt vector.*/
-      AIC_EnableIT(AT91C_ID_US0);
-    }
-#endif
-#if USE_SAM7_USART1
-    if (&SD2 == sdp) {
-      /* Starts the clock and clears possible sources of immediate interrupts.*/
-      AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US1);
-      /* Enables associated interrupt vector.*/
-      AIC_EnableIT(AT91C_ID_US1);
-    }
-#endif
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2
-    if (&SD3 == sdp) {
-      /* Starts the clock and clears possible sources of immediate interrupts.*/
-      AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US2);
-      /* Enables associated interrupt vector.*/
-      AIC_EnableIT(AT91C_ID_US2);
-    }
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-  /* Note - no explicit start for SD3 (DBGU_UART) since it's not included
-     in the AIC or PMC.*/
-  }
-  usart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    usart_deinit(sdp->usart);
-#if USE_SAM7_USART0
-    if (&SD1 == sdp) {
-      AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US0);
-      AIC_DisableIT(AT91C_ID_US0);
-      return;
-    }
-#endif
-#if USE_SAM7_USART1
-    if (&SD2 == sdp) {
-      AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US1);
-      AIC_DisableIT(AT91C_ID_US1);
-      return;
-    }
-#endif
-#if USE_SAM7_DBGU_UART
-    if (&SDDBG == sdp) {
-      AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF;
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/serial_lld.h b/os/hal/platforms/AT91SAM7/serial_lld.h
deleted file mode 100644
index 9b25b2be3..000000000
--- a/os/hal/platforms/AT91SAM7/serial_lld.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/serial_lld.h
- * @brief   AT91SAM7 low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_SAM7_USART0) || defined(__DOXYGEN__)
-#define USE_SAM7_USART0             TRUE
-#endif
-
-/**
- * @brief   UART1 driver enable switch.
- * @details If set to @p TRUE the support for USART2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_SAM7_USART1) || defined(__DOXYGEN__)
-#define USE_SAM7_USART1             TRUE
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-/**
- * @brief   UART2 driver enable switch.
- * @details If set to @p TRUE the support for USART3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_SAM7_USART2) || defined(__DOXYGEN__)
-#define USE_SAM7_USART2             TRUE
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-/**
- * @brief   DBGU UART driver enable switch.
- * @details If set to @p TRUE the support for the DBGU UART is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_SAM7_DBGU_UART) || defined(__DOXYGEN__)
-#define USE_SAM7_DBGU_UART          TRUE
-#endif
-
-/**
- * @brief   UART1 interrupt priority level setting.
- */
-#if !defined(SAM7_USART0_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_USART0_PRIORITY        (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/**
- * @brief   UART2 interrupt priority level setting.
- */
-#if !defined(SAM7_USART1_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_USART1_PRIORITY        (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-/**
- * @brief   UART2 interrupt priority level setting.
- */
-#if !defined(SAM7_USART2_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_USART2_PRIORITY        (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-/**
- * @brief   DBGU_UART interrupt priority level setting.
- */
-#if !defined(SAM7_DBGU_UART_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_DBGU_UART_PRIORITY        (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   AT91SAM7 Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief   Bit rate.
-   * @details This is written to the US_BRGR register of the appropriate AT91S_USART
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief   Initialization value for the MR register.
-   * @details This is written to the US_MR register of the appropriate AT91S_USART
-   */
-  uint32_t                  sc_mr;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  AT91PS_USART              usart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if USE_SAM7_USART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if USE_SAM7_USART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-#endif
-#if USE_SAM7_DBGU_UART
-extern SerialDriver SDDBG;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#if USE_SAM7_DBGU_UART
-  void sd_lld_serve_interrupt(SerialDriver *sdp);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/spi_lld.c b/os/hal/platforms/AT91SAM7/spi_lld.c
deleted file mode 100644
index a2ffcfd2e..000000000
--- a/os/hal/platforms/AT91SAM7/spi_lld.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/spi_lld.c
- * @brief   AT91SAM7 low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if AT91SAM7_SPI_USE_SPI0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-#if AT91SAM7_SPI_USE_SPI1 || defined(__DOXYGEN__)
-/** @brief SPI2 driver identifier.*/
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Idle line value.
- * @details This thing's DMA apparently does not allow to *not* increment
- *          the memory pointer so a buffer filled with ones is required
- *          somewhere.
- * @note    This buffer size also limits the maximum transfer size, 512B,
- *          for @p spiReceive() and @p spiIgnore(). @p spiSend() and
- *          @p spiExchange are not affected.
- */
-static const uint16_t idle_buf[] = {
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
-  0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes a SPI device.
- */
-static void spi_init(AT91PS_SPI spi) {
-
-  /* Software reset must be written twice (errata for revision B parts).*/
-  spi->SPI_CR   = AT91C_SPI_SWRST;
-  spi->SPI_CR   = AT91C_SPI_SWRST;
-  spi->SPI_RCR  = 0;
-  spi->SPI_RNCR = 0;
-  spi->SPI_TCR  = 0;
-  spi->SPI_TNCR = 0;
-  spi->SPI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
-  spi->SPI_MR   = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS;
-}
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-/**
- * @brief   Shared interrupt handling code.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void spi_lld_serve_interrupt(SPIDriver *spip) {
-  uint32_t sr = spip->spi->SPI_SR;
-
-  if ((sr & AT91C_SPI_ENDRX) != 0) {
-    (void)spip->spi->SPI_RDR;                   /* Clears eventual overflow.*/
-    spip->spi->SPI_PTCR = AT91C_PDC_RXTDIS |
-                              AT91C_PDC_TXTDIS; /* PDC disabled.            */
-    spip->spi->SPI_IDR  = AT91C_SPI_ENDRX;      /* Interrupt disabled.      */
-    spip->spi->SPI_CR   = AT91C_SPI_SPIDIS;     /* SPI disabled.            */
-    /* Portable SPI ISR code defined in the high level driver, note, it is
-       a macro.*/
-    _spi_isr_code(spip);
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if AT91SAM7_SPI_USE_SPI0 || defined(__DOXYGEN__)
-/**
- * @brief   SPI0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPI0IrqHandler) {
-
-  CH_IRQ_PROLOGUE();
-  spi_lld_serve_interrupt(&SPID1);
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AT91SAM7_SPI_USE_SPI1 || defined(__DOXYGEN__)
-/**
- * @brief   SPI1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPI1IrqHandler) {
-
-  CH_IRQ_PROLOGUE();
-  spi_lld_serve_interrupt(&SPID2);
-  AT91C_BASE_AIC->AIC_EOICR = 0;
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if AT91SAM7_SPI_USE_SPI0
-  spiObjectInit(&SPID1);
-  SPID1.spi = AT91C_BASE_SPI0;
-  spi_init(AT91C_BASE_SPI0);
-  AT91C_BASE_PIOA->PIO_PDR   = SPI0_MISO | SPI0_MOSI | SPI0_SCK;
-  AT91C_BASE_PIOA->PIO_ASR   = SPI0_MISO | SPI0_MOSI | SPI0_SCK;
-  AT91C_BASE_PIOA->PIO_PPUDR = SPI0_MISO | SPI0_MOSI | SPI0_SCK;
-  AIC_ConfigureIT(AT91C_ID_SPI0,
-                  AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI0_PRIORITY,
-                  SPI0IrqHandler);
-#endif
-
-#if AT91SAM7_SPI_USE_SPI1
-  spiObjectInit(&SPID2);
-  SPID2.spi = AT91C_BASE_SPI1;
-  spi_init(AT91C_BASE_SPI1);
-  AT91C_BASE_PIOA->PIO_PDR   = SPI1_MISO | SPI1_MOSI | SPI1_SCK;
-  AT91C_BASE_PIOA->PIO_BSR   = SPI1_MISO | SPI1_MOSI | SPI1_SCK;
-  AT91C_BASE_PIOA->PIO_PPUDR = SPI1_MISO | SPI1_MOSI | SPI1_SCK;
-  AIC_ConfigureIT(AT91C_ID_SPI1,
-                  AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI1_PRIORITY,
-                  SPI1IrqHandler);
-#endif
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-#if AT91SAM7_SPI_USE_SPI0
-    if (&SPID1 == spip) {
-      /* Clock activation.*/
-      AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI0);
-      /* Enables associated interrupt vector.*/
-      AIC_EnableIT(AT91C_ID_SPI0);
-    }
-#endif
-#if AT91SAM7_SPI_USE_SPI1
-    if (&SPID2 == spip) {
-      /* Clock activation.*/
-      AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI1);
-      /* Enables associated interrupt vector.*/
-      AIC_EnableIT(AT91C_ID_SPI1);
-    }
-#endif
-  }
-  /* Configuration.*/
-  spip->spi->SPI_CSR[0] = spip->config->csr;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state != SPI_STOP) {
-#if AT91SAM7_SPI_USE_SPI0
-    if (&SPID1 == spip) {
-      AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_SPI0);
-      AIC_DisableIT(AT91C_ID_SPI0);
-    }
-#endif
-#if AT91SAM7_SPI_USE_SPI1
-    if (&SPID1 == spip) {
-      AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_SPI1);
-      AIC_DisableIT(AT91C_ID_SPI0);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->spi->SPI_TCR  = n;
-  spip->spi->SPI_RCR  = n;
-  spip->spi->SPI_TPR  = (AT91_REG)idle_buf;
-  spip->spi->SPI_RPR  = (AT91_REG)idle_buf;
-  spip->spi->SPI_IER  = AT91C_SPI_ENDRX;
-  spip->spi->SPI_CR   = AT91C_SPI_SPIEN;
-  spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This function performs a simultaneous transmit/receive operation.
- * @note    The buffers are organized as uint8_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->spi->SPI_TCR  = n;
-  spip->spi->SPI_RCR  = n;
-  spip->spi->SPI_TPR  = (AT91_REG)txbuf;
-  spip->spi->SPI_RPR  = (AT91_REG)rxbuf;
-  spip->spi->SPI_IER  = AT91C_SPI_ENDRX;
-  spip->spi->SPI_CR   = AT91C_SPI_SPIEN;
-  spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @note    The buffers are organized as uint8_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->spi->SPI_TCR  = n;
-  spip->spi->SPI_RCR  = n;
-  spip->spi->SPI_TPR  = (AT91_REG)txbuf;
-  spip->spi->SPI_RPR  = (AT91_REG)idle_buf;
-  spip->spi->SPI_IER  = AT91C_SPI_ENDRX;
-  spip->spi->SPI_CR   = AT91C_SPI_SPIEN;
-  spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @note    The buffers are organized as uint8_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->spi->SPI_TCR  = n;
-  spip->spi->SPI_RCR  = n;
-  spip->spi->SPI_TPR  = (AT91_REG)idle_buf;
-  spip->spi->SPI_RPR  = (AT91_REG)rxbuf;
-  spip->spi->SPI_IER  = AT91C_SPI_ENDRX;
-  spip->spi->SPI_CR   = AT91C_SPI_SPIEN;
-  spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->spi->SPI_CR   = AT91C_SPI_SPIEN;
-  spip->spi->SPI_TDR = frame;
-  while ((spip->spi->SPI_SR & AT91C_SPI_RDRF) == 0)
-    ;
-  return spip->spi->SPI_RDR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/spi_lld.h b/os/hal/platforms/AT91SAM7/spi_lld.h
deleted file mode 100644
index 18299391a..000000000
--- a/os/hal/platforms/AT91SAM7/spi_lld.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AT91SAM7/spi_lld.h
- * @brief   AT91SAM7 low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Device compatibility..                                                    */
-/*===========================================================================*/
-
-#if defined (AT91C_BASE_SPI)
-#define AT91C_BASE_SPI0                 AT91C_BASE_SPI
-#define AT91C_ID_SPI0                   AT91C_ID_SPI
-
-#define SPI0_MISO                       (1 << 12)
-#define SPI0_MOSI                       (1 << 13)
-#define SPI0_SCK                        (1 << 14)
-#else
-#define SPI0_MISO                       (1 << 16)
-#define SPI0_MOSI                       (1 << 17)
-#define SPI0_SCK                        (1 << 18)
-
-#define SPI1_MISO                       (1 << 24)
-#define SPI1_MOSI                       (1 << 23)
-#define SPI1_SCK                        (1 << 22)
-#endif
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPID1 enable switch (SPI0 device).
- * @details If set to @p TRUE the support for SPI0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(AT91SAM7_SPI_USE_SPI0) || defined(__DOXYGEN__)
-#define AT91SAM7_SPI_USE_SPI0           TRUE
-#endif
-
-/**
- * @brief   SPID2 enable switch (SPI1 device).
- * @details If set to @p TRUE the support for SPI1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(AT91SAM7_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define AT91SAM7_SPI_USE_SPI1           TRUE
-#endif
-
-/**
- * @brief   SPI0 device interrupt priority level setting.
- */
-#if !defined(AT91SAM7_SPI0_PRIORITY) || defined(__DOXYGEN__)
-#define AT91SAM7_SPI0_PRIORITY          (AT91C_AIC_PRIOR_HIGHEST - 1)
-#endif
-
-/**
- * @brief   SPI1 device interrupt priority level setting.
- */
-#if !defined(AT91SAM7_SPI1_PRIORITY) || defined(__DOXYGEN__)
-#define AT91SAM7_SPI1_PRIORITY          (AT91C_AIC_PRIOR_HIGHEST - 1)
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if defined (AT91C_BASE_SPI) && AT91SAM7_SPI_USE_SPI1
-#error "SPI1 not present"
-#endif
-
-#if !AT91SAM7_SPI_USE_SPI0 && !AT91SAM7_SPI_USE_SPI1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief SPI Chip Select Register initialization data.
-   */
-  uint32_t              csr;
-} SPIConfig;
-
-/**
- * @brief Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SPIx registers block.
-   */
-  AT91PS_SPI            spi;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if AT91SAM7_SPI_USE_SPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if AT91SAM7_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/adc_lld.c b/os/hal/platforms/AVR/adc_lld.c
deleted file mode 100644
index 13656cfdb..000000000
--- a/os/hal/platforms/AVR/adc_lld.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/adc_lld.c
- * @brief   ADC Driver subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-/** @brief ADC1 driver identifier.*/
-#if AVR_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static size_t getAdcChannelNumberFromMask(uint8_t mask, uint8_t currentChannel) {
-
-  for (uint8_t i = 0; mask > 0; i++) {
-    if (mask & 0x01) {
-      if (!currentChannel)
-        return i;
-      currentChannel--;
-    }
-    mask >>= 1;
-  }
-
-  /* error, should never reach this line */
-}
-
-static void setAdcChannel(uint8_t channelNum) {
-
-  ADMUX = (ADMUX & 0xf8) | (channelNum & 0x07);
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#include <util/delay.h>
-
-CH_IRQ_HANDLER(ADC_vect) {
-
-  CH_IRQ_PROLOGUE();
-  uint8_t low = ADCL;
-  uint8_t high = ADCH;
-  uint16_t result = (high << 8) | low;
-
-  ADCD1.samples[ADCD1.currentBufferPosition] = result;
-  ADCD1.currentBufferPosition++;
-
-  size_t bufferSize = ADCD1.depth * ADCD1.grpp->num_channels;
-  size_t currentChannel = ADCD1.currentBufferPosition % ADCD1.grpp->num_channels;
-  size_t currentIteration = ADCD1.currentBufferPosition / ADCD1.grpp->num_channels;
-  if (ADCD1.grpp->circular && currentChannel == 0 && currentIteration == ADCD1.depth/2) {
-    _adc_isr_half_code(&ADCD1);
-  }
-
-  if (ADCD1.currentBufferPosition == bufferSize) {
-    _adc_isr_full_code(&ADCD1);
-  } else {
-    setAdcChannel(getAdcChannelNumberFromMask(ADCD1.grpp->channelsMask,currentChannel));
-    ADCSRA |= 1 << ADSC;
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-  adcObjectInit(&ADCD1);
-
-  //prescaler 128, only value possible at 20Mhz, interrupt
-  ADCSRA = (1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0) | (1 << ADIE);
-
-  ADCSRB = 0; //single shot
-
-  //uso aref, only valid for arduino. arduino ha aref collegato
-  ADMUX = (0 << REFS1) | (0 << REFS0);
-
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  if (adcp->state == ADC_STOP) {
-    /* Clock activation.*/
-    ADCSRA |= (1 << ADEN);
-  }
-
-  if (adcp->config != NULL) {
-    ADMUX = (adcp->config->analog_reference << REFS0);
-  }
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  if (adcp->state == ADC_READY) {
-    /* Clock de-activation.*/
-    ADCSRA &= ~(1 << ADEN);
-  }
-
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-
-  adcp->currentBufferPosition=0;
-
-  setAdcChannel(getAdcChannelNumberFromMask(adcp->grpp->channelsMask,0));
-  ADCSRA |= 1 << ADSC;
-
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-    ADCSRA &= ~(1 << ADSC);
-
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/adc_lld.h b/os/hal/platforms/AVR/adc_lld.h
deleted file mode 100644
index 2ac8e871c..000000000
--- a/os/hal/platforms/AVR/adc_lld.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/adc_lld.h
- * @brief   ADC Driver subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define ANALOG_REFERENCE_AREF   0
-#define ANALOG_REFERENCE_AVCC   1
-#define ANALOG_REFERENCE_1V1    2
-#define ANALOG_REFERENCE_2V56   3
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !CH_USE_SEMAPHORES
-#error "the ADC driver requires CH_USE_SEMAPHORES"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /* End of the mandatory fields.*/
-
-  uint8_t                   channelsMask;
-
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-
-  uint8_t analog_reference;
-
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct ADCDriver {
-  /**
-   * @brief Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif /* ADC_USE_WAIT */
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Current position in the buffer.
-   */
-  size_t currentBufferPosition;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if AVR_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/avr_pins.h b/os/hal/platforms/AVR/avr_pins.h
deleted file mode 100644
index afc7b315c..000000000
--- a/os/hal/platforms/AVR/avr_pins.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-#ifndef _AVR_PINS_H_
-#define _AVR_PINS_H_
-
-#include <avr/io.h>
-
-#if AVR_SPI_USE_SPI1
-
-#if defined(__AVR_ATmega644__) || defined(__AVR_ATmega644P__)
-  #define PIN_SPI1            PINB
-  #define PORT_SPI1           PORTB
-  #define DDR_SPI1            DDRB
-  #define SPI1_SS             4
-  #define SPI1_SCK            7
-  #define SPI1_MOSI           5
-  #define SPI1_MISO           6
-#elif defined(__AVR_ATmega328P__)
-  #define PIN_SPI1            PINB
-  #define PORT_SPI1           PORTB
-  #define DDR_SPI1            DDRB
-  #define SPI1_SS             2
-  #define SPI1_SCK            5
-  #define SPI1_MOSI           3
-  #define SPI1_MISO           4
-#elif defined(__AVR_ATmega2560__) || \
-      defined(__AVR_ATmega1280__) || \
-      defined(__AVR_ATmega128__)
-  #define PIN_SPI1            PINB
-  #define PORT_SPI1           PORTB
-  #define DDR_SPI1            DDRB
-  #define SPI1_SS             0
-  #define SPI1_SCK            1
-  #define SPI1_MOSI           2
-  #define SPI1_MISO           3
-#elif defined(__AVR_AT90CAN128__) || \
-      defined(__AVR_AT90CAN64__)  || \
-      defined(__AVR_AT90CAN32__)
-  #define PIN_SPI1            PINB
-  #define PORT_SPI1           PORTB
-  #define DDR_SPI1            DDRB
-  #define SPI1_SS             0
-  #define SPI1_SCK            1
-  #define SPI1_MOSI           2
-  #define SPI1_MISO           3
-#else
-  #warning "Device not supported by SPI driver"
-#endif
-
-#endif /* AVR_SPI_USE_SPI1 */
-
-#if AVR_ADC_USE_ADC1
-
-#if defined(__AVR_ATmega644__) || defined(__AVR_ATmega644P__)
-  #define PINADC              PINA
-  #define PORTADC             PORTA
-  #define DDRADC              DDRA
-#elif defined(__AVR_ATmega328P__)
-  #define PINADC              PINC
-  #define PORTADC             PORTC
-  #define DDRADC              DDRC
-#elif defined(__AVR_ATmega2560__) || \
-      defined(__AVR_ATmega1280__) || \
-      defined(__AVR_ATmega128__)
-  #define PINADC              PINF
-  #define PORTADC             PORTF
-  #define DDRADC              DDRF
-#elif defined(__AVR_AT90CAN128__) || \
-      defined(__AVR_AT90CAN64__)  || \
-      defined(__AVR_AT90CAN32__)
-  #define PINADC              PINF
-  #define PORTADC             PORTF
-  #define DDRADC              DDRF
-#else
-  #warning "Device not supported by ADC driver"
-#endif
-
-#endif /* AVR_ADC_USE_ADC1 */
-
-#endif /* _AVR_PINS_H_ */
diff --git a/os/hal/platforms/AVR/avr_timers.h b/os/hal/platforms/AVR/avr_timers.h
deleted file mode 100644
index 28fd90b7e..000000000
--- a/os/hal/platforms/AVR/avr_timers.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-#ifndef _AVR_TIMERS_H_
-#define _AVR_TIMERS_H_
-
-#if ((AVR_GPT_USE_TIM1 && AVR_PWM_USE_TIM1) || \
-     (AVR_GPT_USE_TIM1 && AVR_ICU_USE_TIM1) || \
-     (AVR_PWM_USE_TIM1 && AVR_ICU_USE_TIM1))
-  #error "Timer 1 cannot simultaneously be used by multiple drivers."
-#endif
-
-#if ((AVR_GPT_USE_TIM2 && AVR_PWM_USE_TIM2))
-  #error "Timer 2 cannot simultaneously be used by multiple drivers."
-#endif
-
-#if ((AVR_GPT_USE_TIM3 && AVR_PWM_USE_TIM3) || \
-     (AVR_GPT_USE_TIM3 && AVR_ICU_USE_TIM3) || \
-     (AVR_PWM_USE_TIM3 && AVR_ICU_USE_TIM3))
-  #error "Timer 3 cannot simultaneously be used by multiple drivers."
-#endif
-
-#if ((AVR_GPT_USE_TIM4 && AVR_PWM_USE_TIM4) || \
-     (AVR_GPT_USE_TIM4 && AVR_ICU_USE_TIM4) || \
-     (AVR_PWM_USE_TIM4 && AVR_ICU_USE_TIM4))
-  #error "Timer 4 cannot simultaneously be used by multiple drivers."
-#endif
-
-#if ((AVR_GPT_USE_TIM5 && AVR_PWM_USE_TIM5) || \
-     (AVR_GPT_USE_TIM5 && AVR_ICU_USE_TIM5) || \
-     (AVR_PWM_USE_TIM5 && AVR_ICU_USE_TIM5))
-  #error "Timer 5 cannot simultaneously be used by multiple drivers."
-#endif
-
-#endif /* _AVR_TIMERS_H_ */
diff --git a/os/hal/platforms/AVR/gpt_lld.c b/os/hal/platforms/AVR/gpt_lld.c
deleted file mode 100644
index 4f3b535b6..000000000
--- a/os/hal/platforms/AVR/gpt_lld.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-   This driver is based on the work done by Matteo Serva available at
-   http://github.com/matteoserva/ChibiOS-AVR
-*/
-
-/**
- * @file    AVR/gpt_lld.c
- * @brief   AVR GPT driver subsystem low level driver.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define PRESCALER_SIZE_BASE       5
-#define PRESCALER_SIZE_EXTENDED   7
-
-// FIXME: could use better names here!
-typedef struct {
-  volatile uint8_t *tccra;
-  volatile uint8_t *tccrb;
-  volatile uint8_t *ocr1;
-  volatile uint8_t *ocr2;
-  volatile uint8_t *tcnt1;
-  volatile uint8_t *tcnt2;
-  volatile uint8_t *tifr;
-  volatile uint8_t *timsk;
-} timer_registers_t;
-
-const timer_registers_t regs_table[] = {
-#if AVR_GPT_USE_TIM1 || defined(__DOXYGEN__)
-  { &TCCR1A, &TCCR1B, &OCR1AH, &OCR1AL, &TCNT1H, &TCNT1L, &TIFR1, &TIMSK1 },
-#endif
-#if AVR_GPT_USE_TIM2 || defined(__DOXYGEN__)
-  { &TCCR2A, &TCCR2B, &OCR2A, &OCR2A, &TCNT2, &TCNT2, &TIFR2, &TIMSK2 },
-#endif
-#if AVR_GPT_USE_TIM3 || defined(__DOXYGEN__)
-  { &TCCR3A, &TCCR3B, &OCR3AH, &OCR3AL, &TCNT3H, &TCNT3L, &TIFR3, &TIMSK3 },
-#endif
-#if AVR_GPT_USE_TIM4 || defined(__DOXYGEN__)
-  { &TCCR4A, &TCCR4B, &OCR4AH, &OCR4AL, &TCNT4H, &TCNT4L, &TIFR4, &TIMSK4 },
-#endif
-#if AVR_GPT_USE_TIM5 || defined(__DOXYGEN__)
-  { &TCCR5A, &TCCR5B, &OCR5AH, &OCR5AL, &TCNT5H, &TCNT5L, &TIFR5, &TIMSK5 },
-#endif
-};
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if AVR_GPT_USE_TIM1 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-#if AVR_GPT_USE_TIM2 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-#if AVR_GPT_USE_TIM3 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-#if AVR_GPT_USE_TIM4 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-#if AVR_GPT_USE_TIM5 || defined(__DOXYGEN__)
-GPTDriver GPTD5;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-static uint16_t ratio_base[] = { 1024, 256, 64, 8, 1 };
-static uint8_t  clock_source_base[]= { 5, 4, 3, 2, 1 };
-static uint16_t ratio_extended[] = { 1024, 256, 128, 64, 32, 8, 1 };
-static uint8_t  clock_source_extended[] = { 7, 6, 5, 4, 3, 2, 1 };
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static uint8_t prescaler(uint16_t freq, uint16_t *ratio, uint8_t n)
-{
-  uint8_t i;
-  for (i = 0; i < n; ++i) {
-    uint32_t result = F_CPU / ratio[i] / freq;
-    if (result > 256UL)
-       return i - 1;
-    if ((result * ratio[i] * freq) == F_CPU)
-      return i;
-  }
-}
-
-static void gpt_lld_serve_interrupt(GPTDriver *gptp)
-{
-  gptp->counter++;
-  if (gptp->counter == gptp->period) {
-    gptp->counter = 0;
-    if (gptp->state == GPT_ONESHOT) {
-      gptp->state = GPT_READY;             /* Back in GPT_READY state.     */
-      gpt_lld_stop_timer(gptp);            /* Timer automatically stopped. */
-    }
-    gptp->callback(gptp);
-  }
-}
-
-static void gpt_lld_dummy_callback(GPTDriver *gptp)
-{
-}
-
-static uint8_t getTimerIndex(GPTDriver *gptp)
-{
-  uint8_t index = 0;
-#if AVR_GPT_USE_TIM1 || defined(__DOXYGEN__)
-  if (gptp == &GPTD1) return index;
-  else index++;
-#endif
-#if AVR_GPT_USE_TIM2 || defined(__DOXYGEN__)
-  if (gptp == &GPTD2) return index;
-  else index++;
-#endif
-#if AVR_GPT_USE_TIM3 || defined(__DOXYGEN__)
-  if (gptp == &GPTD3) return index;
-  else index++;
-#endif
-#if AVR_GPT_USE_TIM4 || defined(__DOXYGEN__)
-  if (gptp == &GPTD4) return index;
-  else index++;
-#endif
-#if AVR_GPT_USE_TIM5 || defined(__DOXYGEN__)
-  if (gptp == &GPTD5) return index;
-  else index++;
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if AVR_GPT_USE_TIM1 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER1_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  gpt_lld_serve_interrupt(&GPTD1);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_GPT_USE_TIM2 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER2_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  gpt_lld_serve_interrupt(&GPTD2);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_GPT_USE_TIM3 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER3_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  gpt_lld_serve_interrupt(&GPTD3);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_GPT_USE_TIM4 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER4_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  gpt_lld_serve_interrupt(&GPTD4);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_GPT_USE_TIM5 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER5_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  gpt_lld_serve_interrupt(&GPTD5);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void)
-{
-#if AVR_GPT_USE_TIM1 || defined(__DOXYGEN__)
-  gptObjectInit(&GPTD1);
-#endif
-#if AVR_GPT_USE_TIM2 || defined(__DOXYGEN__)
-  gptObjectInit(&GPTD2);
-#endif
-#if AVR_GPT_USE_TIM3 || defined(__DOXYGEN__)
-  gptObjectInit(&GPTD3);
-#endif
-#if AVR_GPT_USE_TIM4 || defined(__DOXYGEN__)
-  gptObjectInit(&GPTD4);
-#endif
-#if AVR_GPT_USE_TIM5 || defined(__DOXYGEN__)
-  gptObjectInit(&GPTD5);
-#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp)
-{
-  uint8_t psc;
-
-  if (gptp->state == GPT_STOP) {
-    /* Clock activation.*/
-  }
-
-  /* Configuration.*/
-
-#if AVR_GPT_USE_TIM2 || defined(__DOXYGEN__)
-  if (gptp == &GPTD2) {
-    psc = prescaler(gptp->config->frequency, ratio_extended, PRESCALER_SIZE_EXTENDED);
-    gptp->clock_source = clock_source_extended[psc] & 0x07;
-    TCCR2A  = (1 << WGM21) | (0 << WGM20);
-    TCCR2B  = (0 << WGM22);
-    OCR2A = F_CPU / ratio_extended[psc] /gptp->config->frequency - 1;
-    return;
-  }
-#endif
-
-  uint8_t i = getTimerIndex(gptp);
-  psc = prescaler(gptp->config->frequency, ratio_base, PRESCALER_SIZE_BASE);
-  gptp->clock_source = clock_source_base[psc] & 0x07;
-  *regs_table[i].tccra = (0 << WGM11)  |
-                         (0 << WGM10)  |
-                         (0 << COM1A1) |
-                         (0 << COM1A0) |
-                         (0 << COM1B1) |
-                         (0 << COM1B0);
-  *regs_table[i].tccrb = (1 << WGM12);
-  *regs_table[i].ocr1 = 0;
-  *regs_table[i].ocr2 = F_CPU / ratio_base[psc] / gptp->config->frequency - 1;
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp)
-{
-  /* nothing to be done */
-  if (gptp->state == GPT_READY) {
-    /* Clock de-activation.*/
-  }
-  gpt_lld_stop_timer(gptp);
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] period    period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period)
-{
-  gptp->callback = gptp->config->callback;
-  gptp->period = period;
-  gptp->counter = 0;
-
-  uint8_t i = getTimerIndex(gptp);
-  *regs_table[i].tcnt1 = 0;
-  *regs_table[i].tcnt2 = 0;
-  *regs_table[i].tifr  = (1 << OCF1A);
-  *regs_table[i].timsk = (1 << OCIE1A);
-  *regs_table[i].tccrb |= (gptp->clock_source << CS10);
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp)
-{
-  uint8_t i = getTimerIndex(gptp);
-  *regs_table[i].tccrb &= ~((7 << CS10) | (1 << OCIE1A));
-  *regs_table[i].tifr = (1 << OCF1A);
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval)
-{
-  gptp->callback = gpt_lld_dummy_callback;
-  gpt_lld_start_timer(gptp, interval);
-  //FIX
-  while (gptp->state != GPT_READY) {}
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/gpt_lld.h b/os/hal/platforms/AVR/gpt_lld.h
deleted file mode 100644
index 387a2d4bb..000000000
--- a/os/hal/platforms/AVR/gpt_lld.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-   This driver is based on the work done by Matteo Serva available at
-   http://github.com/matteoserva/ChibiOS-AVR
-*/
-
-/**
- * @file    AVR/gpt_lld.h
- * @brief   AVR GPT driver subsystem low level driver.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-#include "avr_timers.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver enable switch.
- * @details If set to @p TRUE the support for GPT1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(AVR_GPT_USE_TIM1)
-#define AVR_GPT_USE_TIM1              FALSE
-#endif
-
-/**
- * @brief   GPT2 driver enable switch.
- * @details If set to @p TRUE the support for GPT2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(AVR_GPT_USE_TIM2)
-#define AVR_GPT_USE_TIM2              FALSE
-#endif
-
-/**
- * @brief   GPT3 driver enable switch.
- * @details If set to @p TRUE the support for GPT3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(AVR_GPT_USE_TIM3)
-#define AVR_GPT_USE_TIM3              FALSE
-#endif
-
-/**
- * @brief   GPT4 driver enable switch.
- * @details If set to @p TRUE the support for GPT4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(AVR_GPT_USE_TIM4)
-#define AVR_GPT_USE_TIM4              FALSE
-#endif
-
-/**
- * @brief   GPT5 driver enable switch.
- * @details If set to @p TRUE the support for GPT5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(AVR_GPT_USE_TIM5)
-#define AVR_GPT_USE_TIM5              FALSE
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint16_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  volatile gptstate_t       state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-
-#if defined(GPT_DRIVER_EXT_FIELDS)
-  GPT_DRIVER_EXT_FIELDS
-#endif
-
-  /* End of the mandatory fields.*/
-  /**
-   * @brief input clock from prescaler
-   */
-  uint8_t                   clock_source;
-  /**
-   * @brief Lenght of the period in clock ticks
-   */
-  gptcnt_t                  period;
-  /**
-   * @brief Current clock tick.
-   */
-  gptcnt_t                  counter;
-  /**
-   * @brief Function called from the interrupt service routine
-   */
-  gptcallback_t             callback;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Changes the interval of GPT peripheral.
- * @details This function changes the interval of a running GPT unit.
- * @pre     The GPT unit must have been activated using @p gptStart().
- * @pre     The GPT unit must have been running in continuous mode using
- *          @p gptStartContinuous().
- * @post    The GPT unit interval is changed to the new value.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- * @param[in] interval  new cycle time in timer ticks
- * @notapi
- */
-
-// FIXME: placeholder to enable compile, should be implemented!
-#define gpt_lld_change_interval(gptp, interval)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if AVR_GPT_USE_TIM1 || defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-#if AVR_GPT_USE_TIM2 || defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-#if AVR_GPT_USE_TIM3 || defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-#if AVR_GPT_USE_TIM4 || defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-#if AVR_GPT_USE_TIM5 || defined(__DOXYGEN__)
-extern GPTDriver GPTD5;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/hal_lld.c b/os/hal/platforms/AVR/hal_lld.c
deleted file mode 100644
index b574a9dc8..000000000
--- a/os/hal/platforms/AVR/hal_lld.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/hal_lld.c
- * @brief   AVR HAL subsystem low level driver code.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Timer0 interrupt handler.
- */
-CH_IRQ_HANDLER(AVR_TIMER_VECT) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /*
-   * Timer 0 setup.
-   */
-#if defined(TCCR0B) /* Timer has multiple output comparators                       */
-  TCCR0A  = (1 << WGM01) | (0 << WGM00) |                /* CTC mode.        */
-            (0 << COM0A1) | (0 << COM0A0) |              /* OC0A disabled.   */
-            (0 << COM0B1) | (0 << COM0B0);               /* OC0B disabled.   */
-  TCCR0B  = (0 << WGM02) | AVR_TIMER_PRESCALER_BITS;     /* CTC mode.        */
-  OCR0A   = AVR_TIMER_COUNTER - 1;
-  TCNT0   = 0;                                           /* Reset counter.   */
-  TIFR0   = (1 << OCF0A);                                /* Reset pending.   */
-  TIMSK0  = (1 << OCIE0A);                               /* IRQ on compare.  */
-
-#elif defined(TCCR0A) /* AT90CAN doesn't have TCCR0B and slightly different TCCR0A */
-  TCCR0A  = (1 << WGM01) | (0 << WGM00) |                /* CTC mode.        */
-            (0 << COM0A1) | (0 << COM0A0);               /* OC0A disabled.   */
-  OCR0A   = AVR_TIMER_COUNTER - 1;
-  TCNT0   = 0;                                           /* Reset counter.   */
-  TIFR0   = (1 << OCF0A);                                /* Reset pending.   */
-  TIMSK0  = (1 << OCIE0A);                               /* IRQ on compare.  */
-
-#elif defined(TCCR0) /* Timer has single output comparator                   */
-  TCCR0   = (1 << WGM01) | (0 << WGM00) |                /* CTC mode.        */
-            (0 << COM01) | (0 << COM00) |                /* OC0A disabled.   */
-            AVR_TIMER_PRESCALER_BITS;
-  OCR0    = AVR_TIMER_COUNTER - 1;
-  TCNT0   = 0;                                           /* Reset counter.   */
-  TIFR    = (1 << OCF0);                                 /* Reset pending.   */
-  TIMSK   = (1 << OCIE0);                                /* IRQ on compare.  */
-#else
-  #error "Neither TCCR0A nor TCCR0 registers are defined"
-#endif
-}
-
-/** @} */
diff --git a/os/hal/platforms/AVR/hal_lld.h b/os/hal/platforms/AVR/hal_lld.h
deleted file mode 100644
index 1dfb5edc9..000000000
--- a/os/hal/platforms/AVR/hal_lld.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/hal_lld.h
- * @brief   AVR HAL subsystem low level driver header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME   "AVR"
-
-/**
- * @brief  Timer maximum value 
- */
-#define AVR_TIMER_COUNTER_MAX 255
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/* Work out what the timer interrupt is called on this MCU */
-#ifdef TIMER0_COMPA_vect
-  #define AVR_TIMER_VECT TIMER0_COMPA_vect
-#elif defined(TIMER_COMPA_vect)
-  #define AVR_TIMER_VECT TIMER_COMPA_vect
-#elif defined(TIMER0_COMP_vect)
-  #define AVR_TIMER_VECT TIMER0_COMP_vect
-#else
-  #error "Cannot find interrupt vector name for timer"
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/* Find the most suitable prescaler setting for the desired CH_FREQUENCY */
-#if ((F_CPU / CH_FREQUENCY) <= AVR_TIMER_COUNTER_MAX)
-  #define AVR_TIMER_PRESCALER 1
-  #define AVR_TIMER_PRESCALER_BITS (0 << CS02)  | (0 << CS01)  | (1 << CS00); /* CLK      */
-#elif ((F_CPU / CH_FREQUENCY / 8) <= AVR_TIMER_COUNTER_MAX)
-  #define AVR_TIMER_PRESCALER 8
-  #define AVR_TIMER_PRESCALER_BITS (0 << CS02)  | (1 << CS01)  | (0 << CS00); /* CLK/8    */
-#elif ((F_CPU / CH_FREQUENCY / 64) <= AVR_TIMER_COUNTER_MAX)
-  #define AVR_TIMER_PRESCALER 64
-  #define AVR_TIMER_PRESCALER_BITS (0 << CS02)  | (1 << CS01)  | (1 << CS00); /* CLK/64   */
-#elif ((F_CPU / CH_FREQUENCY / 256) <= AVR_TIMER_COUNTER_MAX)
-  #define AVR_TIMER_PRESCALER 256
-  #define AVR_TIMER_PRESCALER_BITS (1 << CS02)  | (0 << CS01)  | (0 << CS00); /* CLK/256  */
-#elif ((F_CPU / CH_FREQUENCY / 1024) <= AVR_TIMER_COUNTER_MAX)
-  #define AVR_TIMER_PRESCALER 1024
-  #define AVR_TIMER_PRESCALER_BITS (1 << CS02)  | (0 << CS01)  | (1 << CS00); /* CLK/1024 */
-#else
-  #error "Frequency too low for timer, please set CH_FREQUENCY to a higher value"
-#endif
-
-#define AVR_TIMER_COUNTER (F_CPU / CH_FREQUENCY / AVR_TIMER_PRESCALER)
-
-/* Test if CH_FREQUENCY can be matched exactly using this timer */
-#define F_CPU_ (AVR_TIMER_COUNTER * AVR_TIMER_PRESCALER * CH_FREQUENCY)
-#if (F_CPU_ != F_CPU)
-  #warning "CH_FREQUENCY cannot be generated exactly using timer"
-#endif
-#undef F_CPU_
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/i2c_lld.c b/os/hal/platforms/AVR/i2c_lld.c
deleted file mode 100644
index b22a6c8b0..000000000
--- a/os/hal/platforms/AVR/i2c_lld.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/i2c_lld.c
- * @brief   AVR I2C subsystem low level driver source.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief I2C driver identifier.*/
-#if AVR_I2C_USE_I2C1 || defined(__DOXYGEN__)
-I2CDriver I2CD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Wakes up the waiting thread.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] msg       wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((i2cp)->thread != NULL) {                                             \
-    Thread *tp = (i2cp)->thread;                                            \
-    (i2cp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = (msg);                                                 \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if AVR_I2C_USE_I2C1 || defined(__DOXYGEN__)
-/**
- * @brief   I2C event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(TWI_vect) {
-  CH_IRQ_PROLOGUE();
-
-  I2CDriver *i2cp = &I2CD1;
-
-  switch (TWSR & 0xF8) {
-  case TWI_START:
-  case TWI_REPEAT_START:
-    TWDR = (i2cp->addr << 1);
-    if ((i2cp->txbuf == NULL) || (i2cp->txbytes == 0) || (i2cp->txidx == i2cp->txbytes)) {
-      TWDR |= 0x01;
-    }
-    TWCR = ((1 << TWINT) | (1 << TWEN) | (1 << TWIE));
-    break;
-  case TWI_MASTER_TX_ADDR_ACK:
-  case TWI_MASTER_TX_DATA_ACK:
-    if (i2cp->txidx < i2cp->txbytes) {
-      TWDR = i2cp->txbuf[i2cp->txidx++];
-      TWCR = ((1 << TWINT) | (1 << TWEN) | (1 << TWIE));
-    } else {
-      if (i2cp->rxbuf && i2cp->rxbytes) {
-        TWCR = ((1 << TWSTA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE));
-      } else {
-        TWCR = ((1 << TWSTO) | (1 << TWINT) | (1 << TWEN));
-        wakeup_isr(i2cp, RDY_OK);
-      }
-    }
-    break;
-  case TWI_MASTER_RX_ADDR_ACK:
-    if (i2cp->rxidx == (i2cp->rxbytes - 1)) {
-      TWCR = ((1 << TWINT) | (1 << TWEN) | (1 << TWIE));
-    } else {
-      TWCR = ((1 << TWEA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE));
-    }
-    break;
-  case TWI_MASTER_RX_DATA_ACK:
-    i2cp->rxbuf[i2cp->rxidx++] = TWDR;
-    if (i2cp->rxidx == (i2cp->rxbytes - 1)) {
-      TWCR = ((1 << TWINT) | (1 << TWEN) | (1 << TWIE));
-    } else {
-      TWCR = ((1 << TWEA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE));
-    }
-    break;
-  case TWI_MASTER_RX_DATA_NACK:
-    i2cp->rxbuf[i2cp->rxidx] = TWDR;
-    TWCR = ((1 << TWSTO) | (1 << TWINT) | (1 << TWEN));
-    wakeup_isr(i2cp, RDY_OK);
-  case TWI_MASTER_TX_ADDR_NACK:
-  case TWI_MASTER_TX_DATA_NACK:
-  case TWI_MASTER_RX_ADDR_NACK:
-    i2cp->errors |= I2CD_ACK_FAILURE;
-    break;
-  case TWI_ARBITRATION_LOST:
-    i2cp->errors |= I2CD_ARBITRATION_LOST;
-    break;
-  case TWI_BUS_ERROR:
-    i2cp->errors |= I2CD_BUS_ERROR;
-    break;
-  default:
-    /* FIXME: only gets here if there are other MASTERs in the bus */
-    TWCR = ((1 << TWSTO) | (1 << TWINT) | (1 << TWEN));
-    wakeup_isr(i2cp, RDY_RESET);
-  }
-
-  if (i2cp->errors != I2CD_NO_ERROR) {
-    TWCR = ((1 << TWSTO) | (1 << TWINT) | (1 << TWEN));
-    wakeup_isr(i2cp, RDY_RESET);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* AVR_I2C_USE_I2C1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-  i2cObjectInit(&I2CD1);
-}
-
-/**
- * @brief   Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-
-  /* TODO: Test TWI without external pull-ups (use internal) */
-
-  /* Configure prescaler to 1 */
-  TWSR &= 0xF8;
-
-  /* Configure baudrate */
-  TWBR = ((F_CPU / i2cp->config->clock_speed) - 16) / 2;
-}
-
-/**
- * @brief   Deactivates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
-  if (i2cp->state != I2C_STOP) {
-    /* Disable TWI subsystem and stop all operations */
-    TWCR &= ~(1 << TWEN);
-  }
-}
-
-/**
- * @brief   Receives data via the I2C bus as master.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                     uint8_t *rxbuf, size_t rxbytes,
-                                     systime_t timeout) {
-  i2cp->addr = addr;
-  i2cp->txbuf = NULL;
-  i2cp->txbytes = 0;
-  i2cp->txidx = 0;
-  i2cp->rxbuf = rxbuf;
-  i2cp->rxbytes = rxbytes;
-  i2cp->rxidx = 0;
-
-  /* Send START */
-  TWCR = ((1 << TWSTA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE));
-
-  chSysLock();
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  chSysUnlock();
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief   Transmits data via the I2C bus as master.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[in] txbuf     pointer to the transmit buffer
- * @param[in] txbytes   number of bytes to be transmitted
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                      const uint8_t *txbuf, size_t txbytes,
-                                      uint8_t *rxbuf, size_t rxbytes,
-                                      systime_t timeout) {
-  i2cp->addr = addr;
-  i2cp->txbuf = txbuf;
-  i2cp->txbytes = txbytes;
-  i2cp->txidx = 0;
-  i2cp->rxbuf = rxbuf;
-  i2cp->rxbytes = rxbytes;
-  i2cp->rxidx = 0;
-
-  TWCR = ((1 << TWSTA) | (1 << TWINT) | (1 << TWEN) | (1 << TWIE));
-
-  chSysLock();
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  chSysUnlock();
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/i2c_lld.h b/os/hal/platforms/AVR/i2c_lld.h
deleted file mode 100644
index 3e125d9b8..000000000
--- a/os/hal/platforms/AVR/i2c_lld.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/i2c_lld.h
- * @brief   AVR I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/** @brief   START transmitted.*/
-#define TWI_START                  0x08
-/** @brief   Repeated START transmitted.*/
-#define TWI_REPEAT_START           0x10
-/** @brief   Arbitration Lost.*/
-#define TWI_ARBITRATION_LOST       0x38
-/** @brief   Bus errors.*/
-#define TWI_BUS_ERROR              0x00
-
-/** @brief   SLA+W transmitted with ACK response.*/
-#define TWI_MASTER_TX_ADDR_ACK     0x18
-/** @brief   SLA+W transmitted with NACK response.*/
-#define TWI_MASTER_TX_ADDR_NACK    0x20
-/** @brief   DATA transmitted with ACK response.*/
-#define TWI_MASTER_TX_DATA_ACK     0x28
-/** @brief   DATA transmitted with NACK response.*/
-#define TWI_MASTER_TX_DATA_NACK    0x30
-
-/** @brief   SLA+R transmitted with ACK response.*/
-#define TWI_MASTER_RX_ADDR_ACK     0x40
-/** @brief   SLA+R transmitted with NACK response.*/
-#define TWI_MASTER_RX_ADDR_NACK    0x48
-/** @brief   DATA received with ACK response.*/
-#define TWI_MASTER_RX_DATA_ACK     0x50
-/** @brief   DATA received with NACK response.*/
-#define TWI_MASTER_RX_DATA_NACK    0x58
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   I2C driver enable switch.
- * @details If set to @p TRUE the support for I2C is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(AVR_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define AVR_I2C_USE_I2C1           FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing I2C address.
- */
-typedef uint8_t i2caddr_t;
-
-/**
- * @brief   I2C Driver condition flags type.
- */
-typedef uint8_t i2cflags_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-
-  /**
-   * @brief Specifies the I2C clock frequency.
-   */
-  uint32_t        clock_speed;
-
-} I2CConfig;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver {
-  /**
-   * @brief   Driver state.
-   */
-  i2cstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const I2CConfig           *config;
-  /**
-   * @brief   Error flags.
-   */
-  i2cflags_t                errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
-  I2C_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Thread waiting for I/O completion.
-   */
-  Thread                    *thread;
-  /**
-   * @brief   Address of slave device.
-   */
-  i2caddr_t                 addr;
-  /**
-   * @brief   Pointer to the buffer with data to send.
-   */
-  const uint8_t             *txbuf;
-  /**
-   * @brief   Number of bytes of data to send.
-   */
-  size_t                    txbytes;
-  /**
-   * @brief   Current index in buffer when sending data.
-   */
-  size_t                    txidx;
-  /**
-   * @brief   Pointer to the buffer to put received data.
-   */
-  uint8_t                   *rxbuf;
-  /**
-   * @brief   Number of bytes of data to receive.
-   */
-  size_t                    rxbytes;
-  /**
-   * @brief   Current index in buffer when receiving data.
-   */
-  size_t                    rxidx;
-};
-
-/**
- * @brief   Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Get errors from I2C driver.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-#if AVR_I2C_USE_I2C1
-extern I2CDriver I2CD1;
-#endif
-#endif /* !defined(__DOXYGEN__) */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void i2c_lld_init(void);
-  void i2c_lld_start(I2CDriver *i2cp);
-  void i2c_lld_stop(I2CDriver *i2cp);
-  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                        const uint8_t *txbuf, size_t txbytes,
-                                        uint8_t *rxbuf, size_t rxbytes,
-                                        systime_t timeout);
-  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                       uint8_t *rxbuf, size_t rxbytes,
-                                       systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_I2C */
-
-#endif /* _I2C_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/icu_lld.c b/os/hal/platforms/AVR/icu_lld.c
deleted file mode 100644
index 5977f5551..000000000
--- a/os/hal/platforms/AVR/icu_lld.c
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/icu_lld.c
- * @brief   AVR ICU driver subsystem low level driver source.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-typedef struct {
-  volatile uint8_t  *tccra;
-  volatile uint8_t  *tccrb;
-  volatile uint16_t *tcnt;
-  volatile uint8_t  *timsk;
-} icu_registers_t;
-
-static icu_registers_t regs_table[]=
-{
-#if AVR_ICU_USE_TIM1 || defined(__DOXYGEN__)
-  {&TCCR1A, &TCCR1B, &TCNT1, &TIMSK1},
-#endif
-#if AVR_ICU_USE_TIM3 || defined(__DOXYGEN__)
-  {&TCCR3A, &TCCR3B, &TCNT3, &TIMSK3},
-#endif
-#if AVR_ICU_USE_TIM4 || defined(__DOXYGEN__)
-  {&TCCR4A, &TCCR4B, &TCNT4, &TIMSK4},
-#endif
-#if AVR_ICU_USE_TIM5 || defined(__DOXYGEN__)
-  {&TCCR5A, &TCCR5B, &TCNT5, &TIMSK5},
-#endif
-};
-
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ICU1 driver identifier.
- */
-#if AVR_ICU_USE_TIM1 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-/**
- * @brief   ICU3 driver identifier.
- */
-#if AVR_ICU_USE_TIM3 || defined(__DOXYGEN__)
-ICUDriver ICUD3;
-#endif
-/**
- * @brief   ICU4 driver identifier.
- */
-#if AVR_ICU_USE_TIM4 || defined(__DOXYGEN__)
-ICUDriver ICUD4;
-#endif
-/**
- * @brief   ICU5 driver identifier.
- */
-#if AVR_ICU_USE_TIM5 || defined(__DOXYGEN__)
-ICUDriver ICUD5;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static inline void handle_capture_isr(ICUDriver *icup,
-                                      volatile uint16_t *icr,
-                                      volatile uint8_t  *tccrb,
-                                      volatile uint16_t *tcnt)
-{
-  uint16_t value = *icr;
-  uint8_t rising = (*tccrb & (1 << ICES1)) ? 1 : 0;
-  *tccrb ^= (1 << ICES1);
-  if ((icup->config->mode == ICU_INPUT_ACTIVE_HIGH && rising) ||
-      (icup->config->mode == ICU_INPUT_ACTIVE_LOW  && !rising)) {
-   icup->width = value;
-   if (icup->config->width_cb != NULL)
-     icup->config->width_cb(icup);
-  } else {
-   icup->period = value;
-   if (icup->config->period_cb != NULL)
-     icup->config->period_cb(icup);
-   /* Reset counter at the end of every cycle */
-   *tcnt = 0;
-  }
-}
-
-static uint8_t index(ICUDriver *icup)
-{
-  uint8_t index = 0;
-#if AVR_ICU_USE_TIM1 || defined(__DOXYGEN__)
-  if (icup == &ICUD1) return index;
-  else index++;
-#endif
-#if AVR_ICU_USE_TIM3 || defined(__DOXYGEN__)
-  if (icup == &ICUD3) return index;
-  else index++;
-#endif
-#if AVR_ICU_USE_TIM4 || defined(__DOXYGEN__)
-  if (icup == &ICUD4) return index;
-  else index++;
-#endif
-#if AVR_ICU_USE_TIM5 || defined(__DOXYGEN__)
-  if (icup == &ICUD5) return index;
-  else index++;
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if AVR_ICU_USE_TIM1 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER1_CAPT_vect)
-{
-  CH_IRQ_PROLOGUE();
-  handle_capture_isr(&ICUD1, &ICR1, &TCCR1B, &TCNT1);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER1_OVF_vect)
-{
-  CH_IRQ_PROLOGUE();
-  ICUD1.config->overflow_cb(&ICUD1);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_ICU_USE_TIM3 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER3_CAPT_vect)
-{
-  CH_IRQ_PROLOGUE();
-  handle_capture_isr(&ICUD3, &ICR3, &TCCR3B, &TCNT3);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER3_OVF_vect)
-{
-  CH_IRQ_PROLOGUE();
-  ICUD3.config->overflow_cb(&ICUD3);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_ICU_USE_TIM4 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER4_CAPT_vect)
-{
-  CH_IRQ_PROLOGUE();
-  handle_capture_isr(&ICUD4, &ICR4, &TCCR4B, &TCNT4);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER4_OVF_vect)
-{
-  CH_IRQ_PROLOGUE();
-  ICUD4.config->overflow_cb(&ICUD4);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_ICU_USE_TIM5 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER5_CAPT_vect)
-{
-  CH_IRQ_PROLOGUE();
-  handle_capture_isr(&ICUD5, &ICR5, &TCCR5B, &TCNT5);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER5_OVF_vect)
-{
-  CH_IRQ_PROLOGUE();
-  ICUD5.config->overflow_cb(&ICUD5);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
-#if AVR_ICU_USE_TIM1
-  icuObjectInit(&ICUD1);
-#endif
-#if AVR_ICU_USE_TIM3
-  icuObjectInit(&ICUD3);
-#endif
-#if AVR_ICU_USE_TIM4
-  icuObjectInit(&ICUD4);
-#endif
-#if AVR_ICU_USE_TIM5
-  icuObjectInit(&ICUD5);
-#endif
-}
-
-/**
- * @brief   Configures and activates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-
-  if (icup->state == ICU_STOP) {
-    uint8_t i = index(icup);
-    /* Normal waveform generation (counts from 0 to 0xFFFF) */
-    *regs_table[i].tccra &= ~((1 << WGM11) | (1 << WGM10));
-    *regs_table[i].tccrb &= ~((1 << WGM13) | (1 << WGM12));
-    /* Enable noise canceler, set prescale to CLK/1024 */
-    *regs_table[i].tccrb |= (1 << ICNC1) | (1 << CS12) | (1 << CS10);
-    if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH)
-      *regs_table[i].tccrb |= (1 << ICES1);
-    else
-      *regs_table[i].tccrb &= ~(1 << ICES1);
-  }
-}
-
-/**
- * @brief   Deactivates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
-  if (icup->state == ICU_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if AVR_ICU_USE_TIM1
-    if (&ICUD1 == icup) {
-
-    }
-#endif /* AVR_ICU_USE_TIM1 */
-  }
-}
-
-/**
- * @brief   Enables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
-  uint8_t i = index(icup);
-  icup->width = icup->period = 0;
-  *regs_table[i].tcnt = 0;
-  *regs_table[i].timsk |= (1 << ICIE1);
-  if (icup->config->overflow_cb != NULL)
-    *regs_table[i].timsk |= (1 << TOIE1);
-}
-
-/**
- * @brief   Disables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
-  uint8_t i = index(icup);
-  *regs_table[i].timsk &= ~((1 << ICIE1) | (1 << TOIE1));
-}
-
-/**
- * @brief   Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- *          edge and the stop edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-icucnt_t icu_lld_get_width(ICUDriver *icup) {
-
-  return icup->width;
-}
-
-/**
- * @brief   Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- *          edge and the next start edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-icucnt_t icu_lld_get_period(ICUDriver *icup) {
-
-  return icup->period;
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/icu_lld.h b/os/hal/platforms/AVR/icu_lld.h
deleted file mode 100644
index 407ffba30..000000000
--- a/os/hal/platforms/AVR/icu_lld.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/icu_lld.h
- * @brief   AVR ICU driver subsystem low level driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-#include "avr_timers.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ICU driver enable switch.
- * @details If set to @p TRUE the support for ICU1 is included.
- */
-#if !defined(AVR_ICU_USE_TIM1) || defined(__DOXYGEN__)
-#define AVR_ICU_USE_TIM1               FALSE
-#endif
-/**
- * @brief   ICU driver enable switch.
- * @details If set to @p TRUE the support for ICU3 is included.
- */
-#if !defined(AVR_ICU_USE_TIM3) || defined(__DOXYGEN__)
-#define AVR_ICU_USE_TIM3               FALSE
-#endif
-/**
- * @brief   ICU driver enable switch.
- * @details If set to @p TRUE the support for ICU4 is included.
- */
-#if !defined(AVR_ICU_USE_TIM4) || defined(__DOXYGEN__)
-#define AVR_ICU_USE_TIM4               FALSE
-#endif
-/**
- * @brief   ICU driver enable switch.
- * @details If set to @p TRUE the support for ICU5 is included.
- */
-#if !defined(AVR_ICU_USE_TIM5) || defined(__DOXYGEN__)
-#define AVR_ICU_USE_TIM5               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief ICU driver mode.
- */
-typedef enum {
-  ICU_INPUT_ACTIVE_HIGH = 0,        /**< Trigger on rising edge.            */
-  ICU_INPUT_ACTIVE_LOW = 1,         /**< Trigger on falling edge.           */
-} icumode_t;
-
-/**
- * @brief   ICU frequency type.
- */
-typedef uint16_t icufreq_t;
-
-/**
- * @brief   ICU counter type.
- */
-typedef uint16_t icucnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Driver mode.
-   */
-  icumode_t                 mode;
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  icufreq_t                 frequency;
-  /**
-   * @brief   Callback for pulse width measurement.
-   */
-  icucallback_t             width_cb;
-  /**
-   * @brief   Callback for cycle period measurement.
-   */
-  icucallback_t             period_cb;
-  /**
-   * @brief   Callback for timer overflow.
-   */
-  icucallback_t             overflow_cb;
-  /* End of the mandatory fields.*/
-} ICUConfig;
-
-/**
- * @brief   Structure representing an ICU driver.
- */
-struct ICUDriver {
-  /**
-   * @brief Driver state.
-   */
-  icustate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ICUConfig           *config;
-#if defined(ICU_DRIVER_EXT_FIELDS)
-  ICU_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Width value read by ISR.
-   */
-  icucnt_t                  width;
-  /**
-   * @brief Period value read by ISR.
-   */
-  icucnt_t                  period;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if AVR_ICU_USE_TIM1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-#if AVR_ICU_USE_TIM3 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD3;
-#endif
-#if AVR_ICU_USE_TIM4 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD4;
-#endif
-#if AVR_ICU_USE_TIM5 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD5;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void icu_lld_init(void);
-  void icu_lld_start(ICUDriver *icup);
-  void icu_lld_stop(ICUDriver *icup);
-  void icu_lld_enable(ICUDriver *icup);
-  void icu_lld_disable(ICUDriver *icup);
-  icucnt_t icu_lld_get_width(ICUDriver *icup);
-  icucnt_t icu_lld_get_period(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/pal_lld.c b/os/hal/platforms/AVR/pal_lld.c
deleted file mode 100644
index def4bd430..000000000
--- a/os/hal/platforms/AVR/pal_lld.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/pal_lld.c
- * @brief   AVR GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   AVR GPIO ports configuration.
- * @details GPIO registers initialization.
- *
- * @param[in] config    the AVR ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-#if defined(PORTA) || defined(__DOXYGEN__)
-  PORTA = config->porta.out;
-  DDRA = config->porta.dir;
-#endif
-
-#if defined(PORTB) || defined(__DOXYGEN__)
-  PORTB = config->portb.out;
-  DDRB = config->portb.dir;
-#endif
-
-#if defined(PORTC) || defined(__DOXYGEN__)
-  PORTC = config->portc.out;
-  DDRC = config->portc.dir;
-#endif
-
-#if defined(PORTD) || defined(__DOXYGEN__)
-  PORTD = config->portd.out;
-  DDRD = config->portd.dir;
-#endif
-
-#if defined(PORTE) || defined(__DOXYGEN__)
-  PORTE = config->porte.out;
-  DDRE = config->porte.dir;
-#endif
-
-#if defined(PORTF) || defined(__DOXYGEN__)
-  PORTF = config->portf.out;
-  DDRF = config->portf.dir;
-#endif
-
-#if defined(PORTG) || defined(__DOXYGEN__)
-  PORTG = config->portg.out;
-  DDRG = config->portg.dir;
-#endif
-
-#if defined(PORTH) || defined(__DOXYGEN__)
-  PORTH = config->porth.out;
-  DDRH = config->porth.dir;
-#endif
-
-#if defined(PORTJ) || defined(__DOXYGEN__)
-  PORTJ = config->portj.out;
-  DDRJ = config->portj.dir;
-#endif
-
-#if defined(PORTK) || defined(__DOXYGEN__)
-  PORTK = config->portk.out;
-  DDRK = config->portk.dir;
-#endif
-
-#if defined(PORTL) || defined(__DOXYGEN__)
-  PORTL = config->portl.out;
-  DDRL = config->portl.dir;
-#endif
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @note This function is not meant to be invoked directly by the application
- *       code.
- * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by
- *       the AVR Family User's Guide. Unconnected pads are set to input
- *       with pull-up by default.
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-  case PAL_MODE_INPUT_ANALOG:
-    port->dir &= ~mask;
-    port->out &= ~mask;
-	break;
-  case PAL_MODE_UNCONNECTED:
-  case PAL_MODE_INPUT_PULLUP:
-    port->dir &= ~mask;
-    port->out |= mask;
-    break;
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->dir |= mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/pal_lld.h b/os/hal/platforms/AVR/pal_lld.h
deleted file mode 100644
index a158691c2..000000000
--- a/os/hal/platforms/AVR/pal_lld.h
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file	AVR/pal_lld.h
- * @brief	AVR GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#include "avr_pins.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 8
-
-/**
- * @brief   Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
-
-/**
- * @brief   AVR setup registers.
- */
-typedef struct  {
-  uint8_t  out;
-  uint8_t  dir;
-} avr_gpio_setup_t;
-
-/**
- * @brief   AVR registers block.
- * @note    On some devices registers do not follow this layout on some
- *          ports, the ports with abnormal layout cannot be used through
- *          PAL driver. Example: PORT F on Mega128.
- */
-typedef struct  {
-  volatile uint8_t  in;
-  volatile uint8_t  dir;
-  volatile uint8_t  out;
-} avr_gpio_registers_t;
-
-/**
- * @brief   Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-#if defined(PORTA) || defined(__DOXYGEN__)
-  avr_gpio_setup_t porta;
-#endif
-#if defined(PORTB) || defined(__DOXYGEN__)
-  avr_gpio_setup_t portb;
-#endif
-#if defined(PORTC) || defined(__DOXYGEN__)
-  avr_gpio_setup_t portc;
-#endif
-#if defined(PORTD) || defined(__DOXYGEN__)
-  avr_gpio_setup_t portd;
-#endif
-#if defined(PORTE) || defined(__DOXYGEN__)
-  avr_gpio_setup_t porte;
-#endif
-#if defined(PORTF) || defined(__DOXYGEN__)
-  avr_gpio_setup_t portf;
-#endif
-#if defined(PORTG) || defined(__DOXYGEN__)
-  avr_gpio_setup_t portg;
-#endif
-#if defined(PORTH) || defined(__DOXYGEN__)
-  avr_gpio_setup_t porth;
-#endif
-#if defined(PORTJ) || defined(__DOXYGEN__)
-  avr_gpio_setup_t portj;
-#endif
-#if defined(PORTK) || defined(__DOXYGEN__)
-  avr_gpio_setup_t portk;
-#endif
-#if defined(PORTL) || defined(__DOXYGEN__)
-  avr_gpio_setup_t portl;
-#endif
-} PALConfig;
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint8_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint8_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- *          any assumption about it, use the provided macros when populating
- *          variables of this type.
- */
-typedef avr_gpio_registers_t *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-#if defined(PORTA) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port A identifier.
- */
-#define IOPORT1			((volatile avr_gpio_registers_t *)&PINA)
-#endif
-
-#if defined(PORTB) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port B identifier.
- */
-#define IOPORT2			((volatile avr_gpio_registers_t *)&PINB)
-#endif
-
-#if defined(PORTC) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port C identifier.
- */
-#define IOPORT3			((volatile avr_gpio_registers_t *)&PINC)
-#endif
-
-#if defined(PORTD) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port D identifier.
- */
-#define IOPORT4			((volatile avr_gpio_registers_t *)&PIND)
-#endif
-
-#if defined(PORTE) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port E identifier.
- */
-#define IOPORT5			((volatile avr_gpio_registers_t *)&PINE)
-#endif
-
-#if defined(PORTF) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port F identifier.
- */
-#define IOPORT6			((volatile avr_gpio_registers_t *)&PINF)
-#endif
-
-#if defined(PORTG) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port G identifier.
- */
-#define IOPORT7			((volatile avr_gpio_registers_t *)&PING)
-#endif
-
-#if defined(PORTH) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port H identifier.
- */
-#define IOPORT8         ((volatile avr_gpio_registers_t *)&PINH)
-#endif
-
-#if defined(PORTJ) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port J identifier.
- */
-#define IOPORT9         ((volatile avr_gpio_registers_t *)&PINJ)
-#endif
-
-#if defined(PORTK) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port K identifier.
- */
-#define IOPORT10        ((volatile avr_gpio_registers_t *)&PINK)
-#endif
-
-#if defined(PORTL) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port L identifier.
- */
-#define IOPORT11        ((volatile avr_gpio_registers_t *)&PINL)
-#endif
-
-#if defined(PORTADC) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port ADC identifier.
- */
-#define IOPORTADC			((volatile avr_gpio_registers_t *)&PINADC)
-#endif
-
-#if defined(PORT_SPI1) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port SPI1 identifier.
- */
-#define IOPORTSPI1			((volatile avr_gpio_registers_t *)&PIN_SPI1)
-#endif
-
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config the architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->in)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->out)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->out = bits)
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-__asm__ __volatile__                                                        \
-(                                                                           \
-	"sbi %0,%1\n\t"                                                         \
-	:                                                                       \
-	: "I" (_SFR_IO_ADDR(port->out)),                                        \
-	  "I" (pad)                                                             \
-								                                            \
-)
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-__asm__ __volatile__                                                        \
-(                                                                           \
-	"cbi %0,%1\n\t"                                                         \
-	:                                                                       \
-	: "I" (_SFR_IO_ADDR(port->out)),                                        \
-	  "I" (pad)                                                             \
-								                                            \
-)
-
-extern ROMCONST PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/platform.dox b/os/hal/platforms/AVR/platform.dox
deleted file mode 100644
index c7d636fd8..000000000
--- a/os/hal/platforms/AVR/platform.dox
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup AVR_DRIVERS AVR Drivers
- * @details This section describes all the supported drivers on the AVR
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup AVR_HAL AVR Initialization Support
- * @details On the AVR platform the HAL driver is a stub and does not perform
- *          any platform-specific initialization, it still performs the
- *          initialization of the other drivers.
- *
- * @ingroup AVR_DRIVERS
- */
-
-/**
- * @defgroup AVR_PAL AVR PAL Support
- * @details The AVR PAL driver uses the PORT peripherals.
- *
- * @section avr_pal_1 Supported HW resources
- * - PORTA.
- * - PORTB.
- * - PORTC.
- * - PORTD.
- * - PORTE.
- * - PORTF.
- * - PORTG.
- * .
- * @section avr_pal_2 AVR PAL driver implementation features
- * The AVR PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 8 bits wide ports.
- * - Atomic set/reset functions.
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section avr_pal_3 Supported PAL setup modes
- * The AVR PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_INPUT_ANALOG.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section avr_pal_4 Suboptimal behavior
- * The AVR PORT is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * - Group set+reset function is not atomic.
- * - Writing on pads/groups/ports programmed as input with pull-up
- *   resistor changes the resistor setting because the output latch is
- *   used for resistor selection.
- * - The PORT registers layout on some devices is not regular (it does
- *   not have contiguous PIN, DDR, PORT registers in this order), such
- *   ports cannot be accessed using the PAL driver. For example, PORT F
- *   on ATmega128. Verify the user manual of your device.
- * .
- * @ingroup AVR_DRIVERS
- */
-
-/**
- * @defgroup AVR_SERIAL AVR Serial Support
- * @details The AVR Serial driver uses the USART peripherals in a
- *          buffered, interrupt driven, implementation.
- *
- * @section avr_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART0.
- * - USART1.
- * .
- * @section avr_serial_2 AVR Serial driver implementation features
- * - Each USART can be independently enabled and programmed.
- * - Fully interrupt driven.
- * .
- * @ingroup AVR_DRIVERS
- */
-
-/**
- * @defgroup AVR_ADC AVR ADC Support
- * @details The AVR ADC driver uses the ADC and ADCMUX peripherals
- * in an interrupt driven, one-shot or multiple shot implementation.
- *
- * @section avr_adc Supported HW resources
- * The i2c driver can support the following hardware resource:
- * - ADC.
- * .
- * @ingroup AVR_DRIVERS
- */
-
-/**
- * @defgroup AVR_I2C AVR I2C Support
- * @details The AVR I2C driver uses the TWI peripheral in an interrupt
- *          driven, implementation.
- *
- * @section avr_i2c Supported HW resources
- * The i2c driver can support the following hardware resource:
- * - I2C.
- * .
- * @ingroup AVR_DRIVERS
- */
-
-/**
- * @defgroup AVR_SPI AVR SPI Support
- * @details The AVR SPI driver uses the SPI peripheral (USART in SPI mode
- * is not supported). It works as an interrupt driven implementation but
- * a polled mode is available for 8 bit or 16 bit messages. Both master
- * and slave mode are supported.
- *
- * @section avr_spi Supported HW resources
- * The spi driver can support the following hardware resource:
- * - SPI.
- * .
- * @ingroup AVR_DRIVERS
- */
diff --git a/os/hal/platforms/AVR/platform.mk b/os/hal/platforms/AVR/platform.mk
deleted file mode 100644
index e2e8c1101..000000000
--- a/os/hal/platforms/AVR/platform.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of all the AVR platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AVR/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AVR/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AVR/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AVR/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AVR/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AVR/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AVR/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AVR/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/AVR/icu_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/AVR
diff --git a/os/hal/platforms/AVR/pwm_lld.c b/os/hal/platforms/AVR/pwm_lld.c
deleted file mode 100644
index 900a7d8d1..000000000
--- a/os/hal/platforms/AVR/pwm_lld.c
+++ /dev/null
@@ -1,492 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-   This driver is based on the work done by Matteo Serva available at
-   http://github.com/matteoserva/ChibiOS-AVR
-*/
-
-/**
- * @file    AVR/pwm_lld.c
- * @brief   AVR PWM driver subsystem low level driver.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-typedef struct {
-  volatile uint8_t *tccra;
-  volatile uint8_t *tccrb;
-  volatile uint8_t *ocrah;
-  volatile uint8_t *ocral;
-  volatile uint8_t *ocrbh;
-  volatile uint8_t *ocrbl;
-  volatile uint8_t *ocrch;
-  volatile uint8_t *ocrcl;
-  volatile uint8_t *tifr;
-  volatile uint8_t *timsk;
-} timer_registers_t;
-
-static timer_registers_t regs_table[]=
-{
-#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
-#if defined(OCR1C)
-  {&TCCR1A, &TCCR1B, &OCR1AH, &OCR1AL, &OCR1BH, &OCR1BL, &OCR1CH, &OCR1CL, &TIFR1, &TIMSK1},
-#else
-  {&TCCR1A, &TCCR1B, &OCR1AH, &OCR1AL, &OCR1BH, &OCR1BL, NULL, NULL, &TIFR1, &TIMSK1},
-#endif
-#endif
-#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
-  {&TCCR2A, &TCCR2B, &OCR2A, &OCR2A, &OCR2B, &OCR2B, NULL, NULL, &TIFR2, &TIMSK2},
-#endif
-#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
-  {&TCCR3A, &TCCR3B, &OCR3AH, &OCR3AL, &OCR3BH, &OCR3BL, &OCR3CH, &OCR3CL, &TIFR3, &TIMSK3},
-#endif
-#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
-  {&TCCR4A, &TCCR4B, &OCR4AH, &OCR4AL, &OCR4CH, &OCR4CL, &OCR4CH, &OCR4CL, &TIFR4, &TIMSK4},
-#endif
-#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
-  {&TCCR5A, &TCCR5B, &OCR5AH, &OCR5AL, &OCR5BH, &OCR5BL, &OCR5CH, &OCR5CL, &TIFR5, &TIMSK5},
-#endif
-};
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief PWM driver identifiers.*/
-#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
-PWMDriver PWMD5;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void config_channel(volatile uint8_t *tccra,
-                           uint8_t com1,
-                           uint8_t com0,
-                           pwmmode_t mode)
-{
-  *tccra &= ~((1 << com1) | (1 << com0));
-  if (mode == PWM_OUTPUT_ACTIVE_HIGH)
-    *tccra |= ((1 << com1) | (0 << com0)); /* non inverting mode */
-  else if (mode == PWM_OUTPUT_ACTIVE_LOW)
-    *tccra |= (1 << com1) | (1 << com0);   /* inverting mode */
-}
-
-static uint8_t timer_index(PWMDriver *pwmp)
-{
-  uint8_t index = 0;
-#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
-  if (pwmp == &PWMD1) return index;
-  else index++;
-#endif
-#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
-  if (pwmp == &PWMD2) return index;
-  else index++;
-#endif
-#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
-  if (pwmp == &PWMD3) return index;
-  else index++;
-#endif
-#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
-  if (pwmp == &PWMD4) return index;
-  else index++;
-#endif
-#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
-  if (pwmp == &PWMD5) return index;
-  else index++;
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*
- * interrupt for compare1&2 and clock overflow. pwmd1 & pwmd2
- */
-#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER1_OVF_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD1.config->callback(&PWMD1);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER1_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD1.config->channels[0].callback(&PWMD1);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER1_COMPB_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD1.config->channels[1].callback(&PWMD1);
-  CH_IRQ_EPILOGUE();
-}
-#if PWM_CHANNELS > 2
-CH_IRQ_HANDLER(TIMER1_COMPC_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD1.config->channels[2].callback(&PWMD1);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#endif
-
-#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER2_OVF_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD2.config->callback(&PWMD2);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER2_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD2.config->channels[0].callback(&PWMD2);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER2_COMPB_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD2.config->channels[1].callback(&PWMD2);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER3_OVF_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD3.config->callback(&PWMD3);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER3_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD3.config->channels[0].callback(&PWMD3);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER3_COMPB_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD3.config->channels[1].callback(&PWMD3);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER3_COMPC_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD3.config->channels[2].callback(&PWMD3);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER4_OVF_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD4.config->callback(&PWMD4);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER4_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD4.config->channels[0].callback(&PWMD4);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER4_COMPB_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD4.config->channels[1].callback(&PWMD4);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER4_COMPC_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD4.config->channels[2].callback(&PWMD4);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(TIMER5_OVF_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD5.config->callback(&PWMD5);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER5_COMPA_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD5.config->channels[0].callback(&PWMD5);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER5_COMPB_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD5.config->channels[1].callback(&PWMD5);
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(TIMER5_COMPC_vect)
-{
-  CH_IRQ_PROLOGUE();
-  PWMD5.config->channels[2].callback(&PWMD5);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void)
-{
-#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
-  pwmObjectInit(&PWMD1);
-  TCCR1A = (1 << WGM11) | (1 << WGM10);
-  TCCR1B = (0 << WGM13) | (1 << WGM12);
-#endif
-
-#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
-  pwmObjectInit(&PWMD2);
-  TCCR2A = (1 << WGM21) | (1 << WGM20);
-  TCCR2B = (0 << WGM22);
-#endif
-
-#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
-  pwmObjectInit(&PWMD3);
-  TCCR3A = (1 << WGM31) | (1 << WGM30);
-  TCCR3B = (0 << WGM33) | (1 << WGM32);
-#endif
-
-#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
-  pwmObjectInit(&PWMD4);
-  TCCR4A = (1 << WGM41) | (1 << WGM40);
-  TCCR4B = (0 << WGM43) | (1 << WGM42);
-#endif
-
-#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
-  pwmObjectInit(&PWMD5);
-  TCCR5A = (1 << WGM51) | (1 << WGM50);
-  TCCR5B = (0 << WGM53) | (1 << WGM52);
-#endif
-}
-
-/**
- * @brief   Configures and activates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp)
-{
-  if (pwmp->state == PWM_STOP) {
-
-#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
-    if (pwmp == &PWMD2) {
-      TCCR2B &= ~((1 << CS22) | (1 << CS21));
-      TCCR2B |= (1 << CS20);
-      if (pwmp->config->callback != NULL)
-        TIMSK2 |= (1 << TOIE2);
-      return;
-    }
-#endif
-
-    /* TODO: support other prescaler options */
-
-    uint8_t i = timer_index(pwmp);
-    *regs_table[i].tccrb &= ~(1 << CS11);
-    *regs_table[i].tccrb |= (1 << CS12) | (1 << CS10);
-    *regs_table[i].timsk = (1 << TOIE1);
-  }
-}
-
-/**
- * @brief   Deactivates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp)
-{
-  uint8_t i = timer_index(pwmp);
-  *regs_table[i].tccrb &= ~((1 << CS12) | (1 << CS11) | (1 << CS10));
-  *regs_table[i].timsk = 0;
-}
-
-/**
- * @brief   Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- *          been activated using @p pwmStart().
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The PWM unit period is changed to the new value.
- * @note    The function has effect at the next cycle start.
- * @note    If a period is specified that is shorter than the pulse width
- *          programmed in one of the channels then the behavior is not
- *          guaranteed.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] period    new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period)
-{
-}
-
-/**
- * @brief   Enables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is active using the specified configuration.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t channel,
-                            pwmcnt_t width)
-{
-  uint16_t val = width;
-  if (val > MAX_PWM_VALUE)
-    val = MAX_PWM_VALUE;
-
-#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
-  if (pwmp == &PWMD2) {
-    config_channel(&TCCR2A,
-                   7 - 2*channel,
-                   6 - 2*channel,
-                   pwmp->config->channels[channel].mode);
-    TIMSK2 |= (1 << (channel + 1));
-    /* Timer 2 is 8 bit */
-    if (val > 0xFF)
-      val = 0xFF;
-    if (pwmp->config->channels[channel].callback) {
-      switch (channel) {
-      case 0: OCR2A = val; break;
-      case 1: OCR2B = val; break;
-      }
-    }
-    return;
-  }
-#endif
-
-  uint8_t i = timer_index(pwmp);
-  config_channel(regs_table[i].tccra,
-                 7 - 2*channel,
-                 6 - 2*channel,
-                 pwmp->config->channels[channel].mode);
-  volatile uint8_t *ocrh, *ocrl;
-  switch (channel) {
-  case 1:
-    ocrh = regs_table[i].ocrbh;
-    ocrl = regs_table[i].ocrbl;
-    break;
-  case 2:
-    ocrh = regs_table[i].ocrch;
-    ocrl = regs_table[i].ocrcl;
-    break;
-  default:
-    ocrh = regs_table[i].ocrah;
-    ocrl = regs_table[i].ocral;
-  }
-  *ocrh = val >> 8;
-  *ocrl = val & 0xFF;
-  *regs_table[i].tifr |= (1 << (channel + 1));
-  if (pwmp->config->channels[channel].callback)
-    *regs_table[i].timsk |= (1 << (channel + 1));
-}
-
-/**
- * @brief   Disables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is disabled and its output line returned to the
- *          idle state.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel)
-{
-  uint8_t i = timer_index(pwmp);
-  config_channel(regs_table[i].tccra,
-                 7 - 2*channel,
-                 6 - 2*channel,
-                 PWM_OUTPUT_DISABLED);
-  *regs_table[i].timsk &= ~(1 << (channel + 1));
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/pwm_lld.h b/os/hal/platforms/AVR/pwm_lld.h
deleted file mode 100644
index 36ab5cb73..000000000
--- a/os/hal/platforms/AVR/pwm_lld.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-   This driver is based on the work done by Matteo Serva available at
-   http://github.com/matteoserva/ChibiOS-AVR
-*/
-
-/**
- * @file    AVR/pwm_lld.h
- * @brief   AVR PWM driver subsystem low level driver.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "avr_timers.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#if !defined(AVR_PWM_USE_TIM1)
-#define AVR_PWM_USE_TIM1 FALSE
-#endif
-#if !defined(AVR_PWM_USE_TIM2)
-#define AVR_PWM_USE_TIM2 FALSE
-#endif
-#if !defined(AVR_PWM_USE_TIM3)
-#define AVR_PWM_USE_TIM3 FALSE
-#endif
-#if !defined(AVR_PWM_USE_TIM4)
-#define AVR_PWM_USE_TIM4 FALSE
-#endif
-#if !defined(AVR_PWM_USE_TIM5)
-#define AVR_PWM_USE_TIM5 FALSE
-#endif
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of PWM channels per PWM driver.
- */
-#if !defined(PWM_CHANNELS) || defined(__DOXYGEN__)
-  #if defined(TIMER1_COMPC_vect)
-    #define PWM_CHANNELS        3
-  #else
-    #define PWM_CHANNELS        2
-  #endif
-#endif
-
-#define MAX_PWM_VALUE           0x3FF
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint8_t pwmmode_t;
-
-/**
- * @brief   PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief   PWM counter type.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief   PWM driver channel configuration structure.
- * @note    Some architectures may not be able to support the channel mode
- *          or the callback, in this case the fields are ignored.
- */
-typedef struct {
-  /**
-   * @brief Channel active logic level.
-   */
-  pwmmode_t                 mode;
-  /**
-   * @brief Channel callback pointer.
-   * @note  This callback is invoked on the channel compare event. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  uint16_t                  frequency;
-  /**
-   * @brief   PWM period in ticks.
-   * @note    The low level can use assertions in order to catch invalid
-   *          period specifications.
-   */
-  pwmcnt_t                  period;
-  /**
-   * @brief Periodic callback pointer.
-   * @note  This callback is invoked on PWM counter reset. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /**
-   * @brief Channels configurations.
-   */
-  PWMChannelConfig          channels[PWM_CHANNELS];
-  /* End of the mandatory fields.*/
-} PWMConfig;
-
-/**
- * @brief   Structure representing an PWM driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct PWMDriver {
-  /**
-   * @brief Driver state.
-   */
-  pwmstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const PWMConfig           *config;
-  /**
-   * @brief   Current PWM period in ticks.
-   */
-  pwmcnt_t                  period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
-  PWM_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
-extern PWMDriver PWMD5;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void pwm_lld_init(void);
-  void pwm_lld_start(PWMDriver *pwmp);
-  void pwm_lld_stop(PWMDriver *pwmp);
-  void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
-  void pwm_lld_enable_channel(PWMDriver *pwmp,
-                              pwmchannel_t channel,
-                              pwmcnt_t width);
-  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/serial_lld.c b/os/hal/platforms/AVR/serial_lld.c
deleted file mode 100644
index a60074252..000000000
--- a/os/hal/platforms/AVR/serial_lld.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/serial_lld.c
- * @brief   AVR low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   USART0 serial driver identifier.
- * @note    The name does not follow the convention used in the other ports
- *          (COMn) because a name conflict with the AVR headers.
- */
-#if AVR_SERIAL_USE_USART0 || defined(__DOXYGEN__)
-SerialDriver SD1;
-
-  /* USARTs are not consistently named across the AVR range */
-  #ifdef USART0_RX_vect
-    #define AVR_SD1_RX_VECT USART0_RX_vect
-    #define AVR_SD1_TX_VECT USART0_UDRE_vect
-  #elif defined(USART_RX_vect)
-    #define AVR_SD1_RX_VECT USART_RX_vect
-    #define AVR_SD1_TX_VECT USART_UDRE_vect
-  #else
-    #error "Cannot find USART to use for SD1"
-  #endif 
-#endif /* AVR_SERIAL_USE_USART0 */
-
-/**
- * @brief   USART1 serial driver identifier.
- * @note    The name does not follow the convention used in the other ports
- *          (COMn) because a name conflict with the AVR headers.
- */
-#if AVR_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-SerialDriver SD2;
-
-  /* Check if USART1 exists for this MCU */
-  #ifdef USART1_RX_vect
-    #define AVR_SD2_RX_VECT USART1_RX_vect
-    #define AVR_SD2_TX_VECT USART1_UDRE_vect
-  #else
-    #error "Cannot find USART to use for SD2"
-  #endif
-#endif /* AVR_SERIAL_USE_USART1 */
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Driver default configuration.
- */
-static const SerialConfig default_config = {
-  UBRR(SERIAL_DEFAULT_BITRATE),
-  USART_CHAR_SIZE_8
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void set_error(uint8_t sra, SerialDriver *sdp) {
-  flagsmask_t sts = 0;
-  uint8_t dor = 0;
-  uint8_t upe = 0;
-  uint8_t fe = 0;
-
-#if AVR_SERIAL_USE_USART0
-  if (&SD1 == sdp) {
-    dor = (1 << DOR0);
-    upe = (1 << UPE0);
-    fe = (1 << FE0);
-  }
-#endif
-
-#if AVR_SERIAL_USE_USART1
-  if (&SD2 == sdp) {
-    dor = (1 << DOR1);
-    upe = (1 << UPE1);
-    fe = (1 << FE1);
-  }
-#endif
-
-  if (sra & dor)
-    sts |= SD_OVERRUN_ERROR;
-  if (sra & upe)
-    sts |= SD_PARITY_ERROR;
-  if (sra & fe)
-    sts |= SD_FRAMING_ERROR;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-#if AVR_SERIAL_USE_USART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  UCSR0B |= (1 << UDRIE0);
-}
-
-/**
- * @brief   USART0 initialization.
- *
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void usart0_init(const SerialConfig *config) {
-
-  UBRR0L = config->sc_brr;
-  UBRR0H = config->sc_brr >> 8;
-  UCSR0A = 0;
-  UCSR0B = (1 << RXEN0) | (1 << TXEN0) | (1 << RXCIE0);
-  switch (config->sc_bits_per_char) {
-  case USART_CHAR_SIZE_5:
-    UCSR0C = 0;
-    break;
-  case USART_CHAR_SIZE_6:
-    UCSR0C = (1 << UCSZ00);
-    break;
-  case USART_CHAR_SIZE_7:
-    UCSR0C = (1 << UCSZ01);
-    break;
-  case USART_CHAR_SIZE_9:
-    UCSR0B |= (1 << UCSZ02);
-    UCSR0C = (1 << UCSZ00) | (1 << UCSZ01);
-    break;
-  case USART_CHAR_SIZE_8:
-  default:
-    UCSR0C = (1 << UCSZ00) | (1 << UCSZ01);
-  }
-}
-
-/**
- * @brief   USART0 de-initialization.
- */
-static void usart0_deinit(void) {
-
-  UCSR0A = 0;
-  UCSR0B = 0;
-  UCSR0C = 0;
-}
-#endif
-
-#if AVR_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  UCSR1B |= (1 << UDRIE1);
-}
-
-/**
- * @brief   USART1 initialization.
- *
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void usart1_init(const SerialConfig *config) {
-
-  UBRR1L = config->sc_brr;
-  UBRR1H = config->sc_brr >> 8;
-  UCSR1A = 0;
-  UCSR1B = (1 << RXEN1) | (1 << TXEN1) | (1 << RXCIE1);
-  switch (config->sc_bits_per_char) {
-  case USART_CHAR_SIZE_5:
-    UCSR1C = 0;
-    break;
-  case USART_CHAR_SIZE_6:
-    UCSR1C = (1 << UCSZ10);
-    break;
-  case USART_CHAR_SIZE_7:
-    UCSR1C = (1 << UCSZ11);
-    break;
-  case USART_CHAR_SIZE_9:
-    UCSR1B |= (1 << UCSZ12);
-    UCSR1C = (1 << UCSZ10) | (1 << UCSZ11);
-    break;
-  case USART_CHAR_SIZE_8:
-  default:
-    UCSR1C = (1 << UCSZ10) | (1 << UCSZ11);
-  }
-}
-
-/**
- * @brief   USART1 de-initialization.
- */
-static void usart1_deinit(void) {
-
-  UCSR1A = 0;
-  UCSR1B = 0;
-  UCSR1C = 0;
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if AVR_SERIAL_USE_USART0 || defined(__DOXYGEN__)
-/**
- * @brief   USART0 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(AVR_SD1_RX_VECT) {
-  uint8_t sra;
-
-  CH_IRQ_PROLOGUE();
-
-  sra = UCSR0A;
-  if (sra & ((1 << DOR0) | (1 << UPE0) | (1 << FE0)))
-    set_error(sra, &SD1);
-  chSysLockFromIsr();
-  sdIncomingDataI(&SD1, UDR0);
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   USART0 TX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(AVR_SD1_TX_VECT) {
-  msg_t b;
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  b = sdRequestDataI(&SD1);
-  chSysUnlockFromIsr();
-  if (b < Q_OK)
-    UCSR0B &= ~(1 << UDRIE0);
-  else
-    UDR0 = b;
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* AVR_SERIAL_USE_USART0 */
-
-#if AVR_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-/**
- * @brief   USART1 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(AVR_SD2_RX_VECT) {
-  uint8_t sra;
-
-  CH_IRQ_PROLOGUE();
-
-  sra = UCSR1A;
-  if (sra & ((1 << DOR1) | (1 << UPE1) | (1 << FE1)))
-    set_error(sra, &SD2);
-  chSysLockFromIsr();
-  sdIncomingDataI(&SD2, UDR1);
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   USART1 TX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(AVR_SD2_TX_VECT) {
-  msg_t b;
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  b = sdRequestDataI(&SD2);
-  chSysUnlockFromIsr();
-  if (b < Q_OK)
-    UCSR1B &= ~(1 << UDRIE1);
-  else
-    UDR1 = b;
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* AVR_SERIAL_USE_USART1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if AVR_SERIAL_USE_USART0
-  sdObjectInit(&SD1, NULL, notify1);
-#endif
-#if AVR_SERIAL_USE_USART1
-  sdObjectInit(&SD2, NULL, notify2);
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-#if AVR_SERIAL_USE_USART0
-  if (&SD1 == sdp) {
-    usart0_init(config);
-    return;
-  }
-#endif
-#if AVR_SERIAL_USE_USART1
-  if (&SD2 == sdp) {
-    usart1_init(config);
-    return;
-  }
-#endif
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-#if AVR_SERIAL_USE_USART0
-  if (&SD1 == sdp)
-    usart0_deinit();
-#endif
-#if AVR_SERIAL_USE_USART1
-  if (&SD2 == sdp)
-    usart1_deinit();
-#endif
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/serial_lld.h b/os/hal/platforms/AVR/serial_lld.h
deleted file mode 100644
index 18c6c1d56..000000000
--- a/os/hal/platforms/AVR/serial_lld.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/serial_lld.h
- * @brief   AVR low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   USART0 driver enable switch.
- * @details If set to @p TRUE the support for USART0 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(AVR_SERIAL_USE_USART0) || defined(__DOXYGEN__)
-  #define AVR_SERIAL_USE_USART0              TRUE
-#endif
-
-/**
- * @brief   USART1 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(AVR_SERIAL_USE_USART1) || defined(__DOXYGEN__)
-#define AVR_SERIAL_USE_USART1              TRUE
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   AVR Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Initialization value for the BRR register.
-   */
-  uint16_t                  sc_brr;
-  /**
-   * @brief Number of bits per character (USART_CHAR_SIZE_5 to USART_CHAR_SIZE_9).
-   */
-  uint8_t                   sc_bits_per_char;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Macro for baud rate computation.
- * @note    Make sure the final baud rate is within tolerance.
- */
-#define UBRR(b)     (((F_CPU / b) >> 4) - 1)
-
-/**
- * @brief   Macro for baud rate computation when U2Xn == 1.
- * @note    Make sure the final baud rate is within tolerance.
- */
-#define UBRR2x(b)    (((F_CPU / b) >> 3) - 1)
-
-/**
-* @brief   Macro for baud rate computation.
-* @note    Make sure the final baud rate is within tolerance.
-* @note    This version uses floating point math for greater accuracy.
-*/
-#define UBRR_F(b)   ((((double) F_CPU / (double) b) / 16.0) - 0.5)
-
-/**
-* @brief   Macro for baud rate computation when U2Xn == 1.
-* @note    Make sure the final baud rate is within tolerance.
-* @note    This version uses floating point math for greater accuracy.
-*/
-#define UBRR2x_F(b)  ((((double) F_CPU / (double) b) / 8.0) - 0.5)
-
-#define USART_CHAR_SIZE_5      0
-#define USART_CHAR_SIZE_6      1
-#define USART_CHAR_SIZE_7      2
-#define USART_CHAR_SIZE_8      3
-#define USART_CHAR_SIZE_9      4
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if AVR_SERIAL_USE_USART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if AVR_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/spi_lld.c b/os/hal/platforms/AVR/spi_lld.c
deleted file mode 100644
index 4651e7d74..000000000
--- a/os/hal/platforms/AVR/spi_lld.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/spi_lld.c
- * @brief   AVR SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver identifier.
- */
-#if AVR_SPI_USE_SPI1 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if AVR_SPI_USE_SPI1 || defined(__DOXYGEN__)
-/**
- * @brief   SPI event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(SPI_STC_vect) {
-  CH_IRQ_PROLOGUE();
-
-  SPIDriver *spip = &SPID1;
-
-  /* spi_lld_exchange or spi_lld_receive */
-  if (spip->rxbuf && spip->rxidx < spip->rxbytes) {
-    spip->rxbuf[spip->rxidx++] = SPDR;  // receive
-  }
-
-  /* spi_lld_exchange, spi_lld_send or spi_lld_ignore */
-  if (spip->txidx < spip->txbytes) {
-    if (spip->txbuf) { 
-      SPDR = spip->txbuf[spip->txidx++]; // send
-    } else {
-      SPDR = 0; spip->txidx++; // dummy send
-    }
-  }
-
-  /* spi_lld_send */
-  else if (spip->rxidx < spip->rxbytes) { /* rx not done */
-    SPDR = 0; // dummy send to keep the clock going
-  }
-
-  /* rx done and tx done */
-  if (spip->rxidx >= spip->rxbytes && spip->txidx >= spip->txbytes) { 
-    _spi_isr_code(spip);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* AVR_SPI_USE_SPI1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if AVR_SPI_USE_SPI1
-  /* Driver initialization.*/
-  spiObjectInit(&SPID1);
-#endif /* AVR_SPI_USE_SPI1 */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  uint8_t dummy;
-
-  /* Configures the peripheral.*/
-
-  if (spip->state == SPI_STOP) {
-    /* Enables the peripheral.*/
-#if AVR_SPI_USE_SPI1
-    if (&SPID1 == spip) {
-    /* Enable SPI clock using Power Reduction Register */
-#if defined(PRR0)
-      PRR0 &= ~(1 << PRSPI);
-#elif defined(PRR)
-      PRR &= ~(1 << PRSPI);
-#endif
-
-      /* SPI enable, SPI interrupt enable */
-      SPCR |= ((1 << SPE) | (1 << SPIE));
-
-      switch (spip->config->role) {
-      case SPI_ROLE_SLAVE:
-        SPCR &= ~(1 << MSTR);                                          /* master mode */
-        DDR_SPI1 |=  (1 << SPI1_MISO);                                 /*      output */
-        DDR_SPI1 &= ~((1 << SPI1_MOSI) | (1 << SPI1_SCK) | (1 << SPI1_SS)); /*  input */
-        break;
-      case SPI_ROLE_MASTER: /* fallthrough */
-      default:
-        SPCR |= (1 << MSTR);                                            /* slave mode */
-        DDR_SPI1 |=  ((1 << SPI1_MOSI) | (1 << SPI1_SCK));              /*     output */
-        DDR_SPI1 &= ~(1 << SPI1_MISO);                                  /*      input */
-        spip->config->ssport->dir |= (1 << spip->config->sspad);
-      }
-
-      switch (spip->config->bitorder) {
-      case SPI_LSB_FIRST:
-        SPCR |= (1 << DORD);
-        break;
-      case SPI_MSB_FIRST: /* fallthrough */
-      default:
-        SPCR &= ~(1 << DORD);
-        break;
-      }
-
-      SPCR &= ~((1 << CPOL) | (1 << CPHA));
-      switch (spip->config->mode) {
-      case SPI_MODE_1:
-        SPCR |= (1 << CPHA);
-        break;
-      case SPI_MODE_2:
-        SPCR |= (1 << CPOL);
-        break;
-      case SPI_MODE_3:
-        SPCR |= ((1 << CPOL) | (1 << CPHA));
-        break;
-      case SPI_MODE_0: /* fallthrough */
-      default: break;
-      }
-
-      SPCR &= ~((1 << SPR1) | (1 << SPR0));
-      SPSR &= ~(1 << SPI2X);
-      switch (spip->config->clockrate) {
-      case SPI_SCK_FOSC_2:
-        SPSR |= (1 << SPI2X);
-        break;
-      case SPI_SCK_FOSC_8:
-        SPSR |= (1 << SPI2X);
-        SPCR |= (1 << SPR0);
-        break;
-      case SPI_SCK_FOSC_16:
-        SPCR |= (1 << SPR0);
-        break;
-      case SPI_SCK_FOSC_32:
-        SPSR |= (1 << SPI2X);
-        SPCR |= (1 << SPR1);
-        break;
-      case SPI_SCK_FOSC_64:
-        SPCR |= (1 << SPR1);
-        break;
-      case SPI_SCK_FOSC_128:
-        SPCR |= ((1 << SPR1) | (1 << SPR0));
-        break;
-      case SPI_SCK_FOSC_4: /* fallthrough */
-      default: break;
-      }
-
-      /* dummy reads before enabling interrupt */
-      dummy = SPSR;
-      dummy = SPDR;
-      (void) dummy; /* suppress warning about unused variable */
-      SPCR |= (1 << SPIE);
-    }
-#endif /* AVR_SPI_USE_SPI1 */
-  }
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state == SPI_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if AVR_SPI_USE_SPI1
-    if (&SPID1 == spip) {
-      SPCR &= ((1 << SPIE) | (1 << SPE));
-      spip->config->ssport->dir &= ~(1 << spip->config->sspad);
-    }
-/* Disable SPI clock using Power Reduction Register */
-#if defined(PRR0)
-      PRR0 |= (1 << PRSPI);
-#elif defined(PRR)
-      PRR |= (1 << PRSPI);
-#endif
-#endif /* AVR_SPI_USE_SPI1 */
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-  
-  /**
-   * NOTE: This should only be called in master mode 
-   */ 
-  spip->config->ssport->out &= ~(1 << spip->config->sspad);
-
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  /**
-   * NOTE: This should only be called in master mode 
-   */ 
-  spip->config->ssport->out |= (1 << spip->config->sspad);
-
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- *          idle words on the SPI bus and ignores the received data.
- * @post    At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->rxbuf = spip->txbuf = NULL;
-  spip->txbytes = n;
-  spip->txidx = 0;
-
-  SPDR = 0;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxbuf = rxbuf;
-  spip->txbuf = txbuf;
-  spip->txbytes = spip->rxbytes = n;
-  spip->txidx = spip->rxidx = 0;
-
-  SPDR = spip->txbuf[spip->txidx++];
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->rxbuf = NULL;
-  spip->txbuf = txbuf;
-  spip->txbytes = n;
-  spip->txidx = 0;
-
-  SPDR = spip->txbuf[spip->txidx++];
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->txbuf = NULL;
-  spip->rxbuf = rxbuf;
-  spip->rxbytes = n;
-  spip->rxidx = 0;
-
-  /* Write dummy byte to start communication */
-  SPDR = 0;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-#if AVR_SPI_USE_16BIT_POLLED_EXCHANGE
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  uint16_t spdr = 0;
-  uint8_t dummy;
-
-  /* disable interrupt */
-  SPCR &= ~(1 << SPIE);
-
-  SPDR = frame >> 8;
-  while (!(SPSR & (1 << SPIF))) ;
-  spdr = SPDR << 8;
-
-  SPDR = frame & 0xFF;
-  while (!(SPSR & (1 << SPIF))) ;
-  spdr |= SPDR;
-
-  dummy = SPSR;
-  dummy = SPDR;
-  (void) dummy; /* suppress warning about unused variable */
-  SPCR |= (1 << SPIE);
-
-  return spdr;
-}
-#else /* AVR_SPI_USE_16BIT_POLLED_EXCHANGE */
-uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) {
-
-  uint8_t spdr = 0;
-  uint8_t dummy;
-
-  /* disable interrupt */
-  SPCR &= ~(1 << SPIE);
-
-  SPDR = frame;
-  while (!(SPSR & (1 << SPIF))) ;
-  spdr = SPDR;
-
-  dummy = SPSR;
-  dummy = SPDR;
-  (void) dummy; /* suppress warning about unused variable */
-  SPCR |= (1 << SPIE);
-
-  return spdr;
-}
-#endif /* AVR_SPI_USE_16BIT_POLLED_EXCHANGE */
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/AVR/spi_lld.h b/os/hal/platforms/AVR/spi_lld.h
deleted file mode 100644
index 7ed6d2dd3..000000000
--- a/os/hal/platforms/AVR/spi_lld.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    AVR/spi_lld.h
- * @brief   AVR SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/** @brief SPI Mode (Polarity/Phase) */
-#define SPI_ROLE_MASTER    0
-#define SPI_ROLE_SLAVE     1
-
-/** @brief SPI Mode (Polarity/Phase) */
-#define SPI_CPOL0_CPHA0    0
-#define SPI_CPOL0_CPHA1    1
-#define SPI_CPOL1_CPHA0    2
-#define SPI_CPOL1_CPHA1    3
-
-#define SPI_MODE_0         SPI_CPOL0_CPHA0
-#define SPI_MODE_1         SPI_CPOL0_CPHA1
-#define SPI_MODE_2         SPI_CPOL1_CPHA0
-#define SPI_MODE_3         SPI_CPOL1_CPHA1
-
-/** @brief Bit order */
-#define SPI_LSB_FIRST      0
-#define SPI_MSB_FIRST      1
-
-/** @brief SPI clock rate FOSC/x */
-#define SPI_SCK_FOSC_2     0
-#define SPI_SCK_FOSC_4     1
-#define SPI_SCK_FOSC_8     2
-#define SPI_SCK_FOSC_16    3
-#define SPI_SCK_FOSC_32    4
-#define SPI_SCK_FOSC_64    5
-#define SPI_SCK_FOSC_128   6
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   SPI driver enable switch.
- * @details If set to @p TRUE the support for SPI1 is included.
- */
-#if !defined(AVR_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define AVR_SPI_USE_SPI1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief Role: Master or Slave
-   */
-  uint8_t               role;
-  /**
-   * @brief Port used of Slave Select
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief Pad used of Slave Select
-   */
-  uint8_t               sspad;
-  /**
-   * @brief Polarity/Phase mode
-   */
-  uint8_t               mode;
-  /**
-   * @brief Use MSB/LSB first?
-   */
-  uint8_t               bitorder;
-  /**
-   * @brief Clock rate of the subsystem
-   */
-  uint8_t               clockrate;
-  /**
-   * @brief Operation complete callback.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-} SPIConfig;
-
-/**
- * @brief   Structure representing an SPI driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  SPIConfig             *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /**
-   * @brief   Pointer to the buffer with data to send.
-   */
-  uint8_t                   *txbuf;
-  /**
-   * @brief   Number of bytes of data to send.
-   */
-  size_t                    txbytes;
-  /**
-   * @brief   Current index in buffer when sending data.
-   */
-  size_t                    txidx;
-  /**
-   * @brief   Pointer to the buffer to put received data.
-   */
-  uint8_t                   *rxbuf;
-  /**
-   * @brief   Number of bytes of data to receive.
-   */
-  size_t                    rxbytes;
-  /**
-   * @brief   Current index in buffer when receiving data.
-   */
-  size_t                    rxidx;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if AVR_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-
-#if AVR_SPI_USE_16BIT_POLLED_EXCHANGE
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#else
-  uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame);
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/LPC11Uxx.h b/os/hal/platforms/LPC11Uxx/LPC11Uxx.h
deleted file mode 100644
index 81d37a704..000000000
--- a/os/hal/platforms/LPC11Uxx/LPC11Uxx.h
+++ /dev/null
@@ -1,668 +0,0 @@
-
-/****************************************************************************************************//**
- * @file     LPC11Uxx.h
- *
- *
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
- *           default LPC11Uxx Device Series
- *
- * @version  V0.1
- * @date     21. March 2011
- *
- * @note     Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
- *
- *           from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
- *           created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
- *
- *******************************************************************************************************/
-
-
-
-/** @addtogroup NXP
-  * @{
-  */
-
-/** @addtogroup LPC11Uxx
-  * @{
-  */
-
-#ifndef __LPC11UXX_H__
-#define __LPC11UXX_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-
-#if defined ( __CC_ARM   )
-  #pragma anon_unions
-#endif
-
- /* Interrupt Number Definition */
-
-typedef enum {
-// -------------------------  Cortex-M0 Processor Exceptions Numbers  -----------------------------
-  Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
-  NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
-  HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
-  SVCall_IRQn                       = -5,   /*!<  11  System Service Call via SVC instruction */
-  DebugMonitor_IRQn                 = -4,   /*!<  12  Debug Monitor                    */
-  PendSV_IRQn                       = -2,   /*!<  14  Pendable request for system service */
-  SysTick_IRQn                      = -1,   /*!<  15  System Tick Timer                */
-// ---------------------------  LPC11Uxx Specific Interrupt Numbers  ------------------------------
-FLEX_INT0_IRQn                = 0,        /*!< All I/O pins can be routed to below 8 interrupts. */
-  FLEX_INT1_IRQn                = 1,
-  FLEX_INT2_IRQn                = 2,
-  FLEX_INT3_IRQn                = 3,
-  FLEX_INT4_IRQn                = 4,   
-  FLEX_INT5_IRQn                = 5,        
-  FLEX_INT6_IRQn                = 6,        
-  FLEX_INT7_IRQn                = 7,        
-  GINT0_IRQn                    = 8,        /*!< Grouped Interrupt 0                              */
-  GINT1_IRQn                    = 9,        /*!< Grouped Interrupt 1                              */
-  Reserved0_IRQn                = 10,       /*!< Reserved Interrupt                               */
-  Reserved1_IRQn                = 11,       
-  Reserved2_IRQn                = 12,       
-  Reserved3_IRQn                = 13,       
-  SSP1_IRQn                     = 14,       /*!< SSP1 Interrupt                                   */
-  I2C_IRQn                      = 15,       /*!< I2C Interrupt                                    */
-  TIMER_16_0_IRQn               = 16,       /*!< 16-bit Timer0 Interrupt                          */
-  TIMER_16_1_IRQn               = 17,       /*!< 16-bit Timer1 Interrupt                          */
-  TIMER_32_0_IRQn               = 18,       /*!< 32-bit Timer0 Interrupt                          */
-  TIMER_32_1_IRQn               = 19,       /*!< 32-bit Timer1 Interrupt                          */
-  SSP0_IRQn                     = 20,       /*!< SSP0 Interrupt                                   */
-  UART_IRQn                     = 21,       /*!< UART Interrupt                                   */
-  USB_IRQn                      = 22,       /*!< USB IRQ Interrupt                                */
-  USB_FIQn                      = 23,       /*!< USB FIQ Interrupt                                */
-  ADC_IRQn                      = 24,       /*!< A/D Converter Interrupt                          */
-  WDT_IRQn                      = 25,       /*!< Watchdog timer Interrupt                         */  
-  BOD_IRQn                      = 26,       /*!< Brown Out Detect(BOD) Interrupt                  */
-  FMC_IRQn                      = 27,       /*!< Flash Memory Controller Interrupt                */
-  Reserved4_IRQn                = 28,       /*!< Reserved Interrupt                               */
-  Reserved5_IRQn                = 29,       /*!< Reserved Interrupt                               */
-  USBWakeup_IRQn                = 30,       /*!< USB wakeup Interrupt                             */
-  Reserved6_IRQn                = 31,       /*!< Reserved Interrupt                               */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
-  * @{
-  */
-
-/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
-
-#define __MPU_PRESENT             0         /*!< MPU present or not                    */
-#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include "core_cm0.h"                       /*!< Cortex-M0 processor and core peripherals */
-#include "system_LPC11Uxx.h"                /*!< LPC11Uxx System                       */
-
-/** @addtogroup Device_Peripheral_Registers
-  * @{
-  */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          I2C                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3  (I2C)
-  */
-
-typedef struct {                            /*!< (@ 0x40000000) I2C Structure          */
-  __IO uint32_t CONSET;                     /*!< (@ 0x40000000) I2C Control Set Register */
-  __I  uint32_t STAT;                       /*!< (@ 0x40000004) I2C Status Register */
-  __IO uint32_t DAT;                        /*!< (@ 0x40000008) I2C Data Register.  */
-  __IO uint32_t ADR0;                       /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
-  __IO uint32_t SCLH;                       /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
-  __IO uint32_t SCLL;                       /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
-  __IO uint32_t CONCLR;                     /*!< (@ 0x40000018) I2C Control Clear Register*/
-  __IO uint32_t MMCTRL;                     /*!< (@ 0x4000001C) Monitor mode control register*/
-  __IO uint32_t ADR1;                       /*!< (@ 0x40000020) I2C Slave Address Register 1*/
-  __IO uint32_t ADR2;                       /*!< (@ 0x40000024) I2C Slave Address Register 2*/
-  __IO uint32_t ADR3;                       /*!< (@ 0x40000028) I2C Slave Address Register 3*/
-  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x4000002C) Data buffer register */
-union{
-  __IO uint32_t MASK[4];                    /*!< (@ 0x40000030) I2C Slave address mask register */
-  struct{
-  __IO uint32_t MASK0;
-  __IO uint32_t MASK1;
-  __IO uint32_t MASK2;
-  __IO uint32_t MASK3;
-  };
-  };
-} LPC_I2C_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         WWDT                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3  (WWDT)
-  */
-
-typedef struct {                            /*!< (@ 0x40004000) WWDT Structure         */
-  __IO uint32_t MOD;                        /*!< (@ 0x40004000) Watchdog mode register*/
-  __IO uint32_t TC;                         /*!< (@ 0x40004004) Watchdog timer constant register */
-  __IO uint32_t FEED;                       /*!< (@ 0x40004008) Watchdog feed sequence register */
-  __I  uint32_t TV;                         /*!< (@ 0x4000400C) Watchdog timer value register */
-  __IO uint32_t CLKSEL;                     /*!< (@ 0x40004010) Watchdog clock select register. */
-  __IO uint32_t WARNINT;                    /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
-  __IO uint32_t WINDOW;                     /*!< (@ 0x40004018) Watchdog Window compare value. */
-} LPC_WWDT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         USART                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3  (USART)
-  */
-
-typedef struct {                            /*!< (@ 0x40008000) USART Structure        */
-  
-  union {
-    __IO uint32_t DLL;                      /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
-    __O  uint32_t THR;                      /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
-    __I  uint32_t RBR;                      /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
-  };
-  
-  union {
-    __IO uint32_t IER;                      /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
-    __IO uint32_t DLM;                      /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
-  };
-  
-  union {
-    __O  uint32_t FCR;                      /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
-    __I  uint32_t IIR;                      /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
-  };
-  __IO uint32_t LCR;                        /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
-  __IO uint32_t MCR;                        /*!< (@ 0x40008010) Modem Control Register. */
-  __I  uint32_t LSR;                        /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
-  __I  uint32_t MSR;                        /*!< (@ 0x40008018) Modem Status Register. */
-  __IO uint32_t SCR;                        /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
-  __IO uint32_t ACR;                        /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
-  __IO uint32_t ICR;                        /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
-  __IO uint32_t FDR;                        /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
-  __IO uint32_t OSR;                        /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
-  __IO uint32_t TER;                        /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
-  __I  uint32_t RESERVED0[3];
-  __IO uint32_t HDEN;                       /*!< (@ 0x40008040) Half duplex enable register. */
-  __I  uint32_t RESERVED1;
-  __IO uint32_t SCICTRL;                    /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
-  __IO uint32_t RS485CTRL;                  /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
-  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
-  __IO uint32_t RS485DLY;                   /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
-  __IO uint32_t SYNCCTRL; 
-} LPC_USART_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        Timer                                       -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3  
-  */
-
-typedef struct {                            /*!< (@ 0x40014000) CT32B0 Structure        */
-  __IO uint32_t IR;                         /*!< (@ 0x40014000) Interrupt Register      */
-  __IO uint32_t TCR;                        /*!< (@ 0x40014004) Timer Control Register  */
-  __IO uint32_t TC;                         /*!< (@ 0x40014008) Timer Counter 		*/
-  __IO uint32_t PR;                         /*!< (@ 0x4001400C) Prescale Register  	*/
-  __IO uint32_t PC;                         /*!< (@ 0x40014010) Prescale Counter	 */
-  __IO uint32_t MCR;                        /*!< (@ 0x40014014) Match Control Register */
-  union {
-  __IO uint32_t MR[4];                      /*!< (@ 0x40014018) Match Register */
-  struct{
-  __IO uint32_t MR0;                        /*!< (@ 0x40018018) Match Register. MR0 */
-  __IO uint32_t MR1;                        /*!< (@ 0x4001801C) Match Register. MR1 */
-  __IO uint32_t MR2;                        /*!< (@ 0x40018020) Match Register. MR2 */
-  __IO uint32_t MR3;                        /*!< (@ 0x40018024) Match Register. MR3 */
-  };
-  };
-  __IO uint32_t CCR;                        /*!< (@ 0x40014028) Capture Control Register */
-  union{
-  __I  uint32_t CR[4];                      /*!< (@ 0x4001402C) Capture Register  */
-    struct{
-  __I  uint32_t CR0;			    /*!< (@ 0x4001802C) Capture Register. CR 0 */
-  __I  uint32_t CR1;			    /*!< (@ 0x40018030) Capture Register. CR 1 */
-  __I  uint32_t CR2;			    /*!< (@ 0x40018034) Capture Register. CR 2 */
-  __I  uint32_t CR3;			    /*!< (@ 0x40018038) Capture Register. CR 3 */
-  };
-  };
-__IO uint32_t EMR;                        /*!< (@ 0x4001403C) External Match Register */
-  __I  uint32_t RESERVED0[12];
-  __IO uint32_t CTCR;                       /*!< (@ 0x40014070) Count Control Register */
-  __IO uint32_t PWMC;                       /*!< (@ 0x40014074) PWM Control Register */
-} LPC_CTxxBx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          ADC                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3  (ADC)
-  */
-
-typedef struct {                            /*!< (@ 0x4001C000) ADC Structure          */
-  __IO uint32_t CR;                         /*!< (@ 0x4001C000) A/D Control Register */
-  __IO uint32_t GDR;                        /*!< (@ 0x4001C004) A/D Global Data Register */
-  __I  uint32_t RESERVED0[1];
-  __IO uint32_t INTEN;                      /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
-  union{
-  __I  uint32_t DR[8];                      /*!< (@ 0x4001C010) A/D Channel Data Register*/
-    struct{
-  __IO uint32_t DR0;                      	/*!< (@ 0x40020010) A/D Channel Data Register 0*/
-  __IO uint32_t DR1;                      	/*!< (@ 0x40020014) A/D Channel Data Register 1*/
-  __IO uint32_t DR2;                      	/*!< (@ 0x40020018) A/D Channel Data Register 2*/
-  __IO uint32_t DR3;                      	/*!< (@ 0x4002001C) A/D Channel Data Register 3*/
-  __IO uint32_t DR4;                      	/*!< (@ 0x40020020) A/D Channel Data Register 4*/
-  __IO uint32_t DR5;                      	/*!< (@ 0x40020024) A/D Channel Data Register 5*/
-  __IO uint32_t DR6;                      	/*!< (@ 0x40020028) A/D Channel Data Register 6*/
-  __IO uint32_t DR7;                      	/*!< (@ 0x4002002C) A/D Channel Data Register 7*/
-  };
-  };
-  __I  uint32_t STAT;                       /*!< (@ 0x4001C030) A/D Status Register.  */
-} LPC_ADC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          PMU                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3  (PMU)
-  */
-
-typedef struct {                            /*!< (@ 0x40038000) PMU Structure          */
-  __IO uint32_t PCON;                       /*!< (@ 0x40038000) Power control register */
-  union{
-  __IO uint32_t GPREG[4];                   /*!< (@ 0x40038004) General purpose register 0 */
-  struct{
-  __IO uint32_t GPREG0;                   	/*!< (@ 0x40038004) General purpose register 0 */
-  __IO uint32_t GPREG1;                   	/*!< (@ 0x40038008) General purpose register 1 */
-  __IO uint32_t GPREG2;                   	/*!< (@ 0x4003800C) General purpose register 2 */
-  __IO uint32_t GPREG3;                   	/*!< (@ 0x40038010) General purpose register 3 */
-  };
-  };
-} LPC_PMU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       FLASHCTRL                                      -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3  (FLASHCTRL)
-  */
-
-typedef struct {                            /*!< (@ 0x4003C000) FLASHCTRL Structure    */
-  __I  uint32_t RESERVED0[4];
-  __IO uint32_t FLASHCFG;                   /*!< (@ 0x4003C010) Flash memory access time configuration register */
-  __I  uint32_t RESERVED1[3];
-  __IO uint32_t FMSSTART;                   /*!< (@ 0x4003C020) Signature start address register */
-  __IO uint32_t FMSSTOP;                    /*!< (@ 0x4003C024) Signature stop-address register */
-  __I  uint32_t RESERVED2[1];
-  __I  uint32_t FMSW0;                      /*!< (@ 0x4003C02C) Word 0 [31:0]          */
-  __I  uint32_t FMSW1;                      /*!< (@ 0x4003C030) Word 1 [63:32]         */
-  __I  uint32_t FMSW2;                      /*!< (@ 0x4003C034) Word 2 [95:64]         */
-  __I  uint32_t FMSW3;                      /*!< (@ 0x4003C038) Word 3 [127:96]        */
-  __I  uint32_t RESERVED3[1001];
-  __I  uint32_t FMSTAT;                     /*!< (@ 0x4003CFE0) Signature generation status register */
-  __I  uint32_t RESERVED4[1];
-  __IO uint32_t FMSTATCLR;                  /*!< (@ 0x4003CFE8) Signature generation status clear register */
-} LPC_FLASHCTRL_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         SSP0/1                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3  (SSP0)
-  */
-
-typedef struct {                            /*!< (@ 0x40040000) SSP0 Structure         */
-  __IO uint32_t CR0;                        /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
-  __IO uint32_t CR1;                        /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
-  __IO uint32_t DR;                         /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
-  __I  uint32_t SR;                         /*!< (@ 0x4004000C) Status Register        */
-  __IO uint32_t CPSR;                       /*!< (@ 0x40040010) Clock Prescale Register */
-  __IO uint32_t IMSC;                       /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
-  __I  uint32_t RIS;                        /*!< (@ 0x40040018) Raw Interrupt Status Register */
-  __I  uint32_t MIS;                        /*!< (@ 0x4004001C) Masked Interrupt Status Register */
-  __IO uint32_t ICR;                        /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
-} LPC_SSPx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       IOCONFIG                                       -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3  (IOCONFIG)
-  */
-
-typedef struct {                            /*!< (@ 0x40044000) IOCONFIG Structure     */
-  __IO uint32_t RESET_PIO0_0;               /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
-  __IO uint32_t PIO0_1;                     /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
-  __IO uint32_t PIO0_2;                     /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
-  __IO uint32_t PIO0_3;                     /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
-  __IO uint32_t PIO0_4;                     /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
-  __IO uint32_t PIO0_5;                     /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
-  __IO uint32_t PIO0_6;                     /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
-  __IO uint32_t PIO0_7;                     /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
-  __IO uint32_t PIO0_8;                     /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
-  __IO uint32_t PIO0_9;                     /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
-  __IO uint32_t SWCLK_PIO0_10;              /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
-  __IO uint32_t TDI_PIO0_11;                /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
-  __IO uint32_t TMS_PIO0_12;                /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
-  __IO uint32_t TDO_PIO0_13;                /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
-  __IO uint32_t TRST_PIO0_14;               /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
-  __IO uint32_t SWDIO_PIO0_15;              /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
-  __IO uint32_t PIO0_16;                    /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
-  __IO uint32_t PIO0_17;                    /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
-  __IO uint32_t PIO0_18;                    /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
-  __IO uint32_t PIO0_19;                    /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
-  __IO uint32_t PIO0_20;                    /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
-  __IO uint32_t PIO0_21;                    /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
-  __IO uint32_t PIO0_22;                    /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
-  __IO uint32_t PIO0_23;                    /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
-  __IO uint32_t PIO1_0;                 /*!< Offset: 0x060 */
-  __IO uint32_t PIO1_1;         
-  __IO uint32_t PIO1_2;       
-  __IO uint32_t PIO1_3;      
-  __IO uint32_t PIO1_4;                 /*!< Offset: 0x070 */
-  __IO uint32_t PIO1_5;                     /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
-  __IO uint32_t PIO1_6;     
-  __IO uint32_t PIO1_7;       
-  __IO uint32_t PIO1_8;                 /*!< Offset: 0x080 */
-  __IO uint32_t PIO1_9;        
-  __IO uint32_t PIO1_10;        
-  __IO uint32_t PIO1_11;       
-  __IO uint32_t PIO1_12;                /*!< Offset: 0x090 */
-  __IO uint32_t PIO1_13;                    /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
-  __IO uint32_t PIO1_14;                    /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
-  __IO uint32_t PIO1_15;                    /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
-  __IO uint32_t PIO1_16;                    /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
-  __IO uint32_t PIO1_17;
-  __IO uint32_t PIO1_18;
-  __IO uint32_t PIO1_19;                    /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
-  __IO uint32_t PIO1_20;                    /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
-  __IO uint32_t PIO1_21;                    /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
-  __IO uint32_t PIO1_22;                    /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
-  __IO uint32_t PIO1_23;                    /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
-  __IO uint32_t PIO1_24;                    /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
-  __IO uint32_t PIO1_25;                    /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
-  __IO uint32_t PIO1_26;                    /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
-  __IO uint32_t PIO1_27;                    /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
-  __IO uint32_t PIO1_28;                    /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
-  __IO uint32_t PIO1_29;                    /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
-  __IO uint32_t PIO1_30;
-  __IO uint32_t PIO1_31;                    /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
-} LPC_IOCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        SYSCON                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3  (SYSCON)
-  */
-
-typedef struct {                            /*!< (@ 0x40048000) SYSCON Structure       */
-  __IO uint32_t SYSMEMREMAP;                /*!< (@ 0x40048000) System memory remap    */
-  __IO uint32_t PRESETCTRL;                 /*!< (@ 0x40048004) Peripheral reset control */
-  __IO uint32_t SYSPLLCTRL;                 /*!< (@ 0x40048008) System PLL control     */
-  __I  uint32_t SYSPLLSTAT;                 /*!< (@ 0x4004800C) System PLL status      */
-  __IO uint32_t USBPLLCTRL;                 /*!< (@ 0x40048010) USB PLL control        */
-  __I  uint32_t USBPLLSTAT;                 /*!< (@ 0x40048014) USB PLL status         */
-  __I  uint32_t RESERVED0[2];
-  __IO uint32_t SYSOSCCTRL;                 /*!< (@ 0x40048020) System oscillator control */
-  __IO uint32_t WDTOSCCTRL;                 /*!< (@ 0x40048024) Watchdog oscillator control */
-  __I  uint32_t RESERVED1[2];
-  __IO uint32_t SYSRSTSTAT;                 /*!< (@ 0x40048030) System reset status register */
-  __I  uint32_t RESERVED2[3];
-  __IO uint32_t SYSPLLCLKSEL;               /*!< (@ 0x40048040) System PLL clock source select */
-  __IO uint32_t SYSPLLCLKUEN;               /*!< (@ 0x40048044) System PLL clock source update enable */
-  __IO uint32_t USBPLLCLKSEL;               /*!< (@ 0x40048048) USB PLL clock source select */
-  __IO uint32_t USBPLLCLKUEN;               /*!< (@ 0x4004804C) USB PLL clock source update enable */
-  __I  uint32_t RESERVED3[8];
-  __IO uint32_t MAINCLKSEL;                 /*!< (@ 0x40048070) Main clock source select */
-  __IO uint32_t MAINCLKUEN;                 /*!< (@ 0x40048074) Main clock source update enable */
-  __IO uint32_t SYSAHBCLKDIV;               /*!< (@ 0x40048078) System clock divider   */
-  __I  uint32_t RESERVED4[1];
-  __IO uint32_t SYSAHBCLKCTRL;              /*!< (@ 0x40048080) System clock control   */
-  __I  uint32_t RESERVED5[4];
-  __IO uint32_t SSP0CLKDIV;                 /*!< (@ 0x40048094) SSP0 clock divider     */
-  __IO uint32_t UARTCLKDIV;                 /*!< (@ 0x40048098) UART clock divider     */
-  __IO uint32_t SSP1CLKDIV;                 /*!< (@ 0x4004809C) SSP1 clock divider     */
-  __I  uint32_t RESERVED6[8];
-  __IO uint32_t USBCLKSEL;                  /*!< (@ 0x400480C0) USB clock source select */
-  __IO uint32_t USBCLKUEN;                  /*!< (@ 0x400480C4) USB clock source update enable */
-  __IO uint32_t USBCLKDIV;                  /*!< (@ 0x400480C8) USB clock source divider */
-  __I  uint32_t RESERVED7[5];
-  __IO uint32_t CLKOUTSEL;                  /*!< (@ 0x400480E0) CLKOUT clock source select */
-  __IO uint32_t CLKOUTUEN;                  /*!< (@ 0x400480E4) CLKOUT clock source update enable */
-  __IO uint32_t CLKOUTDIV;                  /*!< (@ 0x400480E8) CLKOUT clock divider   */
-  __I  uint32_t RESERVED8[5];
-  __I  uint32_t PIOPORCAP0;                 /*!< (@ 0x40048100) POR captured PIO status 0 */
-  __I  uint32_t PIOPORCAP1;                 /*!< (@ 0x40048104) POR captured PIO status 1 */
-  __I  uint32_t RESERVED9[18];
-  __IO uint32_t BODCTRL;                    /*!< (@ 0x40048150) Brown-Out Detect       */
-  __IO uint32_t SYSTCKCAL;                  /*!< (@ 0x40048154) System tick counter calibration */
-  __I  uint32_t RESERVED10[6];
-  __IO uint32_t IRQLATENCY;                 /*!< (@ 0x40048170) IQR delay */
-  __IO uint32_t NMISRC;                     /*!< (@ 0x40048174) NMI Source Control     */
-  __IO uint32_t PINTSEL[8];                 /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
-  __IO uint32_t USBCLKCTRL;                 /*!< (@ 0x40048198) USB clock control      */
-  __I  uint32_t USBCLKST;                   /*!< (@ 0x4004819C) USB clock status       */
-  __I  uint32_t RESERVED11[25];
-  __IO uint32_t STARTERP0;                  /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
-  __I  uint32_t RESERVED12[3];
-  __IO uint32_t STARTERP1;                  /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
-  __I  uint32_t RESERVED13[6];
-  __IO uint32_t PDSLEEPCFG;                 /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
-  __IO uint32_t PDAWAKECFG;                 /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
-  __IO uint32_t PDRUNCFG;                   /*!< (@ 0x40048238) Power configuration register */
-  __I  uint32_t RESERVED14[110];
-  __I  uint32_t DEVICE_ID;                  /*!< (@ 0x400483F4) Device ID              */
-} LPC_SYSCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                     GPIO_PIN_INT                                     -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_PIN_INT)
-  */
-
-typedef struct {                            /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
-  __IO uint32_t ISEL;                       /*!< (@ 0x4004C000) Pin Interrupt Mode register */
-  __IO uint32_t IENR;                       /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
-  __IO uint32_t SIENR;                      /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
-  __IO uint32_t CIENR;                      /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
-  __IO uint32_t IENF;                       /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
-  __IO uint32_t SIENF;                      /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
-  __IO uint32_t CIENF;                      /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
-  __IO uint32_t RISE;                       /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
-  __IO uint32_t FALL;                       /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
-  __IO uint32_t IST;                        /*!< (@ 0x4004C024) Pin Interrupt Status register */
-} LPC_GPIO_PIN_INT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                    GPIO_GROUP_INT0/1                                   -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_GROUP_INT0)
-  */
-
-typedef struct {                            /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
-  __IO uint32_t CTRL;                       /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
-  __I  uint32_t RESERVED0[7];
-  __IO uint32_t PORT_POL[2];                /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
-  __I  uint32_t RESERVED1[6];
-  __IO uint32_t PORT_ENA[2];                /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
-} LPC_GPIO_GROUP_INTx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          USB                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3  (USB)
-  */
-
-typedef struct {                            /*!< (@ 0x40080000) USB Structure          */
-  __IO uint32_t DEVCMDSTAT;                 /*!< (@ 0x40080000) USB Device Command/Status register */
-  __IO uint32_t INFO;                       /*!< (@ 0x40080004) USB Info register      */
-  __IO uint32_t EPLISTSTART;                /*!< (@ 0x40080008) USB EP Command/Status List start address */
-  __IO uint32_t DATABUFSTART;               /*!< (@ 0x4008000C) USB Data buffer start address */
-  __IO uint32_t LPM;                        /*!< (@ 0x40080010) Link Power Management register */
-  __IO uint32_t EPSKIP;                     /*!< (@ 0x40080014) USB Endpoint skip      */
-  __IO uint32_t EPINUSE;                    /*!< (@ 0x40080018) USB Endpoint Buffer in use */
-  __IO uint32_t EPBUFCFG;                   /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
-  __IO uint32_t INTSTAT;                    /*!< (@ 0x40080020) USB interrupt status register */
-  __IO uint32_t INTEN;                      /*!< (@ 0x40080024) USB interrupt enable register */
-  __IO uint32_t INTSETSTAT;                 /*!< (@ 0x40080028) USB set interrupt status register */
-  __IO uint32_t INTROUTING;                 /*!< (@ 0x4008002C) USB interrupt routing register */
-  __I  uint32_t RESERVED0[1];
-  __I  uint32_t EPTOGGLE;                   /*!< (@ 0x40080034) USB Endpoint toggle register */
-} LPC_USB_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       GPIO_PORT                                      -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_PORT)
-  */
-
-typedef struct {                            
-  union {
-    struct {
-      __IO uint8_t B0[32];                       /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
-      __IO uint8_t B1[32];                       /*!< (@ 0x50000020) Byte pin registers port 1 */
-    };
-    __IO uint8_t B[64];                       /*!< (@ 0x50000000) Byte pin registers port 0/1 */
-  };
-  __I  uint32_t RESERVED0[1008];
-  union {
-    struct {
-      __IO uint32_t W0[32];                      /*!< (@ 0x50001000) Word pin registers port 0 */
-      __IO uint32_t W1[32];                      /*!< (@ 0x50001080) Word pin registers port 1 */
-    };
-    __IO uint32_t W[64];                       /*!< (@ 0x50001000) Word pin registers port 0/1 */
-  };
-       uint32_t RESERVED1[960];
-  __IO uint32_t DIR[2];			/* 0x2000 */
-       uint32_t RESERVED2[30];
-  __IO uint32_t MASK[2];		/* 0x2080 */
-       uint32_t RESERVED3[30];
-  __IO uint32_t PIN[2];			/* 0x2100 */
-       uint32_t RESERVED4[30];
-  __IO uint32_t MPIN[2];		/* 0x2180 */
-       uint32_t RESERVED5[30];
-  __IO uint32_t SET[2];			/* 0x2200 */
-       uint32_t RESERVED6[30];
-  __O  uint32_t CLR[2];			/* 0x2280 */
-       uint32_t RESERVED7[30];
-  __O  uint32_t NOT[2];			/* 0x2300 */
-} LPC_GPIO_Type;
-
-
-#if defined ( __CC_ARM   )
-  #pragma no_anon_unions
-#endif
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 Peripheral memory map                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C_BASE              (0x40000000)
-#define LPC_WWDT_BASE             (0x40004000)
-#define LPC_USART_BASE            (0x40008000)
-#define LPC_CT16B0_BASE           (0x4000C000)
-#define LPC_CT16B1_BASE           (0x40010000)
-#define LPC_CT32B0_BASE           (0x40014000)
-#define LPC_CT32B1_BASE           (0x40018000)
-#define LPC_ADC_BASE              (0x4001C000)
-#define LPC_PMU_BASE              (0x40038000)
-#define LPC_FLASHCTRL_BASE        (0x4003C000)
-#define LPC_SSP0_BASE             (0x40040000)
-#define LPC_SSP1_BASE             (0x40058000)
-#define LPC_IOCON_BASE            (0x40044000)
-#define LPC_SYSCON_BASE           (0x40048000)
-#define LPC_GPIO_PIN_INT_BASE     (0x4004C000)
-#define LPC_GPIO_GROUP_INT0_BASE  (0x4005C000)
-#define LPC_GPIO_GROUP_INT1_BASE  (0x40060000)
-#define LPC_USB_BASE              (0x40080000)
-#define LPC_GPIO_BASE             (0x50000000)
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                Peripheral declaration                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C                   ((LPC_I2C_Type            *) LPC_I2C_BASE)
-#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
-#define LPC_USART                 ((LPC_USART_Type          *) LPC_USART_BASE)
-#define LPC_CT16B0                ((LPC_CTxxBx_Type         *) LPC_CT16B0_BASE)
-#define LPC_CT16B1                ((LPC_CTxxBx_Type         *) LPC_CT16B1_BASE)
-#define LPC_CT32B0                ((LPC_CTxxBx_Type         *) LPC_CT32B0_BASE)
-#define LPC_CT32B1                ((LPC_CTxxBx_Type         *) LPC_CT32B1_BASE)
-#define LPC_ADC                   ((LPC_ADC_Type            *) LPC_ADC_BASE)
-#define LPC_PMU                   ((LPC_PMU_Type            *) LPC_PMU_BASE)
-#define LPC_FLASHCTRL             ((LPC_FLASHCTRL_Type      *) LPC_FLASHCTRL_BASE)
-#define LPC_SSP0                  ((LPC_SSPx_Type           *) LPC_SSP0_BASE)
-#define LPC_SSP1                  ((LPC_SSPx_Type           *) LPC_SSP1_BASE)
-#define LPC_IOCON                 ((LPC_IOCON_Type          *) LPC_IOCON_BASE)
-#define LPC_SYSCON                ((LPC_SYSCON_Type         *) LPC_SYSCON_BASE)
-#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_USB                   ((LPC_USB_Type            *) LPC_USB_BASE)
-#define LPC_GPIO                  ((LPC_GPIO_Type           *) LPC_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group (null) */
-/** @} */ /* End of group LPC11Uxx */
-
-#ifdef __cplusplus
-}
-#endif 
-
-
-#endif  // __LPC11UXX_H__
diff --git a/os/hal/platforms/LPC11Uxx/ext_lld.c b/os/hal/platforms/LPC11Uxx/ext_lld.c
deleted file mode 100644
index 81cdaf4aa..000000000
--- a/os/hal/platforms/LPC11Uxx/ext_lld.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/ext_lld.c
- * @brief   LPC11Uxx EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTD1 driver identifier.
- */
-EXTDriver EXTD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
-  /* Driver initialization.*/
-  extObjectInit(&EXTD1);
-}
-
-/**
- * @brief   Configures and activates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
-  int i;
-
-  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<19);
-  /* Configuration of automatic channels.*/
-  for (i = 0; i < EXT_MAX_CHANNELS; i++)
-    if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
-      ext_lld_channel_enable(extp, i);
-    else
-      ext_lld_channel_disable(extp, i);
-}
-
-/**
- * @brief   Deactivates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-  int i;
-
-  if (extp->state == EXT_ACTIVE)
-    for (i = 0; i < EXT_MAX_CHANNELS; i++)
-      ext_lld_exti_irq_disable(i);
-
-  LPC_GPIO_PIN_INT->ISEL  = 0;
-  LPC_GPIO_PIN_INT->CIENR = EXT_CHANNELS_MASK;
-  LPC_GPIO_PIN_INT->RISE  = EXT_CHANNELS_MASK;
-  LPC_GPIO_PIN_INT->FALL  = EXT_CHANNELS_MASK;
-  LPC_GPIO_PIN_INT->IST   = EXT_CHANNELS_MASK;
-
-  LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<19);
-}
-
-/**
- * @brief   Enables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
-  /* program the IOpin for this channel */
-  LPC_SYSCON->PINTSEL[channel] = extp->config->channels[channel].iopin;
-  
-  /* Programming edge irq enables */
-  if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
-    LPC_GPIO_PIN_INT->SIENR =  (1 << channel);
-  else
-    LPC_GPIO_PIN_INT->CIENR =  (1 << channel);
-    
-  if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
-    LPC_GPIO_PIN_INT->SIENF =  (1 << channel);
-  else
-    LPC_GPIO_PIN_INT->CIENF =  (1 << channel);
-
-  LPC_GPIO_PIN_INT->RISE = (1<<channel);
-  LPC_GPIO_PIN_INT->FALL = (1<<channel);
-  LPC_GPIO_PIN_INT->IST  = (1<<channel);
-  
-  ext_lld_exti_irq_enable( channel );
-}
-
-/**
- * @brief   Disables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-  (void)extp;
-
-  ext_lld_exti_irq_disable(channel);
-
-  LPC_GPIO_PIN_INT->ISEL &= ~(1 << channel);
-  LPC_GPIO_PIN_INT->CIENR =  (1 << channel);
-  LPC_GPIO_PIN_INT->RISE  =  (1 << channel);
-  LPC_GPIO_PIN_INT->FALL  =  (1 << channel);
-  LPC_GPIO_PIN_INT->IST   =  (1 << channel);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/ext_lld.h b/os/hal/platforms/LPC11Uxx/ext_lld.h
deleted file mode 100644
index 9ec20f9f1..000000000
--- a/os/hal/platforms/LPC11Uxx/ext_lld.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/ext_lld.h
- * @brief   LPC11Uxx EXT subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_H_
-#define _EXT_LLD_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Available number of EXT channels.
- */
-#define EXT_MAX_CHANNELS    8
-
-/**
- * @brief   Mask of the available channels.
- */
-#define EXT_CHANNELS_MASK   ((1 << EXT_MAX_CHANNELS) - 1)
-
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
-
- * @brief   EXT channel callback reason.
- */
-typedef uint32_t expreason_t;
-
-/**
- * @brief   Type of an EXT generic notification callback.
- *
- * @param[in] extp      pointer to the @p EXPDriver object triggering the
- *                      callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp,
-                              expchannel_t channel,
-                              expreason_t reason);
-
-/**
- * @brief   Channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel mode.
-   */
-  uint8_t              mode;
-  /**
-   * @brief IO Pin.
-   */
-  uint8_t              iopin;
-  /**
-   * @brief Channel callback.
-   */
-  extcallback_t         cb;
-} EXTChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief Channel configurations.
-   */
-  EXTChannelConfig      channels[EXT_MAX_CHANNELS];
-  /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief   Structure representing an EXT driver.
- */
-struct EXTDriver {
-  /**
-   * @brief Driver state.
-   */
-  extstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const EXTConfig           *config;
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_init(void);
-  void ext_lld_start(EXTDriver *extp);
-  void ext_lld_stop(EXTDriver *extp);
-  void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
-  void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/ext_lld_isr.c b/os/hal/platforms/LPC11Uxx/ext_lld_isr.c
deleted file mode 100644
index 818d493e3..000000000
--- a/os/hal/platforms/LPC11Uxx/ext_lld_isr.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/ext_lld_isr.c
- * @brief   LPC11Uxx EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-static void ext_lld_interrupt( uint32_t n ) {
-  uint32_t reason;
-  
-  reason =  ((LPC_GPIO_PIN_INT->RISE)>> n   ) & 0x01;
-  reason |= ((LPC_GPIO_PIN_INT->FALL)>>(n-1)) & 0x02;
-  LPC_GPIO_PIN_INT->RISE = (1<<n);
-  LPC_GPIO_PIN_INT->FALL = (1<<n);
-  LPC_GPIO_PIN_INT->IST  = (1<<n);
-  EXTD1.config->channels[n].cb(&EXTD1, n, reason);
-}
-
-/**
- * @brief   EXT[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector40) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(0);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector44) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(1);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[2] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector48) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(2);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[3] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector4C) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(3);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[4] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector50) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(4);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[5] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector54) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(5);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[6] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector58) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(6);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[7] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector5C) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(7);
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-static const uint8_t LPC11_EXT_EXTIn_IRQ_PRIORITY[] =
-    { LPC11_EXT_EXTI0_IRQ_PRIORITY,
-      LPC11_EXT_EXTI1_IRQ_PRIORITY,
-      LPC11_EXT_EXTI2_IRQ_PRIORITY,
-      LPC11_EXT_EXTI3_IRQ_PRIORITY,
-      LPC11_EXT_EXTI4_IRQ_PRIORITY,
-      LPC11_EXT_EXTI5_IRQ_PRIORITY,
-      LPC11_EXT_EXTI6_IRQ_PRIORITY,
-      LPC11_EXT_EXTI7_IRQ_PRIORITY };
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable( uint32_t exti_n ) {
-
-  nvicEnableVector(FLEX_INT0_IRQn + exti_n,
-                   CORTEX_PRIORITY_MASK(LPC11_EXT_EXTIn_IRQ_PRIORITY[exti_n]));
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable( uint32_t exti_n ) {
-
-  nvicDisableVector(FLEX_INT0_IRQn + exti_n);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/ext_lld_isr.h b/os/hal/platforms/LPC11Uxx/ext_lld_isr.h
deleted file mode 100644
index 4fbbff862..000000000
--- a/os/hal/platforms/LPC11Uxx/ext_lld_isr.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/ext_lld_isr.h
- * @brief   LPC11Uxx EXT subsystem low level driver ISR header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_ISR_H_
-#define _EXT_LLD_ISR_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   EXTI0 interrupt priority level setting.
- */
-#if !defined(LPC11_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11_EXT_EXTI0_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI1 interrupt priority level setting.
- */
-#if !defined(LPC11_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11_EXT_EXTI1_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI2 interrupt priority level setting.
- */
-#if !defined(LPC11_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11_EXT_EXTI2_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI3 interrupt priority level setting.
- */
-#if !defined(LPC11_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11_EXT_EXTI3_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI4 interrupt priority level setting.
- */
-#if !defined(LPC11_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11_EXT_EXTI4_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI5 interrupt priority level setting.
- */
-#if !defined(LPC11_EXT_EXTI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11_EXT_EXTI5_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI6 interrupt priority level setting.
- */
-#if !defined(LPC11_EXT_EXTI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11_EXT_EXTI6_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI7 interrupt priority level setting.
- */
-#if !defined(LPC11_EXT_EXTI7_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11_EXT_EXTI7_IRQ_PRIORITY      3
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_exti_irq_enable( uint32_t exti_n );
-  void ext_lld_exti_irq_disable( uint32_t exti_n );
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_ISR_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.c b/os/hal/platforms/LPC11Uxx/gpt_lld.c
deleted file mode 100644
index 15a1c6068..000000000
--- a/os/hal/platforms/LPC11Uxx/gpt_lld.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/gpt_lld.c
- * @brief   LPC11Uxx GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver identifier.
- * @note    The driver GPT1 allocates the complex timer CT16B0 when enabled.
- */
-#if LPC_GPT_USE_CT16B0 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief   GPT2 driver identifier.
- * @note    The driver GPT2 allocates the timer CT16B1 when enabled.
- */
-#if LPC_GPT_USE_CT16B1 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief   GPT3 driver identifier.
- * @note    The driver GPT3 allocates the timer CT32B0 when enabled.
- */
-#if LPC_GPT_USE_CT32B0 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/**
- * @brief   GPT4 driver identifier.
- * @note    The driver GPT4 allocates the timer CT32B1 when enabled.
- */
-#if LPC_GPT_USE_CT32B1 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
-  gptp->tmr->IR = 1;                        /* Clear interrupt on match MR0.*/
-  if (gptp->state == GPT_ONESHOT) {
-    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
-    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
-  }
-  gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC_GPT_USE_CT16B0
-/**
- * @brief   CT16B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector80) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC_GPT_USE_CT16B0 */
-
-#if LPC_GPT_USE_CT16B1
-/**
- * @brief   CT16B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector84) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC_GPT_USE_CT16B0 */
-
-#if LPC_GPT_USE_CT32B0
-/**
- * @brief   CT32B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector88) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC_GPT_USE_CT32B0 */
-
-#if LPC_GPT_USE_CT32B1
-/**
- * @brief   CT32B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector8C) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC_GPT_USE_CT32B1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if LPC_GPT_USE_CT16B0
-  /* Driver initialization.*/
-  GPTD1.tmr = LPC_CT16B0;
-  gptObjectInit(&GPTD1);
-#endif
-
-#if LPC_GPT_USE_CT16B1
-  /* Driver initialization.*/
-  GPTD2.tmr = LPC_CT16B1;
-  gptObjectInit(&GPTD2);
-#endif
-
-#if LPC_GPT_USE_CT32B0
-  /* Driver initialization.*/
-  GPTD3.tmr = LPC_CT32B0;
-  gptObjectInit(&GPTD3);
-#endif
-
-#if LPC_GPT_USE_CT32B1
-  /* Driver initialization.*/
-  GPTD4.tmr = LPC_CT32B1;
-  gptObjectInit(&GPTD4);
-#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-  uint32_t pr;
-
-  if (gptp->state == GPT_STOP) {
-    /* Clock activation.*/
-#if LPC_GPT_USE_CT16B0
-    if (&GPTD1 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7);
-      nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC_GPT_USE_CT16B1
-    if (&GPTD2 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
-      nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3));
-    }
-#endif
-#if LPC_GPT_USE_CT32B0
-    if (&GPTD3 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9);
-      nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC_GPT_USE_CT32B1
-    if (&GPTD4 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
-      nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-  }
-
-  /* Prescaler value calculation.*/
-  pr = (uint16_t)((LPC_SYSCLK / gptp->config->frequency) - 1);
-  chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC_SYSCLK,
-              "gpt_lld_start(), #1", "invalid frequency");
-
-  /* Timer configuration.*/
-  gptp->tmr->PR  = pr;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
-  if (gptp->state == GPT_READY) {
-    gptp->tmr->MCR = 0;
-    gptp->tmr->TCR = 0;
-
-#if LPC_GPT_USE_CT16B0
-    if (&GPTD1 == gptp) {
-      nvicDisableVector(TIMER_16_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
-    }
-#endif
-#if LPC_GPT_USE_CT16B1
-    if (&GPTD2 == gptp) {
-      nvicDisableVector(TIMER_16_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
-    }
-#endif
-#if LPC_GPT_USE_CT32B0
-    if (&GPTD3 == gptp) {
-      nvicDisableVector(TIMER_32_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
-    }
-#endif
-#if LPC_GPT_USE_CT32B1
-    if (&GPTD4 == gptp) {
-      nvicDisableVector(TIMER_32_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 3;                       /* IRQ and clr TC on match MR0. */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 4;                       /* Stop TC on match MR0.        */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-  while (gptp->tmr->TCR & 1)
-    ;
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.h b/os/hal/platforms/LPC11Uxx/gpt_lld.h
deleted file mode 100644
index 674960c7b..000000000
--- a/os/hal/platforms/LPC11Uxx/gpt_lld.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/gpt_lld.h
- * @brief   LPC11Uxx GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver enable switch.
- * @details If set to @p TRUE the support for GPT1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_GPT_USE_CT16B0) || defined(__DOXYGEN__)
-#define LPC_GPT_USE_CT16B0                  TRUE
-#endif
-
-/**
- * @brief   GPT2 driver enable switch.
- * @details If set to @p TRUE the support for GPT2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_GPT_USE_CT16B1) || defined(__DOXYGEN__)
-#define LPC_GPT_USE_CT16B1                  TRUE
-#endif
-
-/**
- * @brief   GPT3 driver enable switch.
- * @details If set to @p TRUE the support for GPT3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_GPT_USE_CT32B0) || defined(__DOXYGEN__)
-#define LPC_GPT_USE_CT32B0                  TRUE
-#endif
-
-/**
- * @brief   GPT4 driver enable switch.
- * @details If set to @p TRUE the support for GPT4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_GPT_USE_CT32B1) || defined(__DOXYGEN__)
-#define LPC_GPT_USE_CT32B1                  TRUE
-#endif
-
-/**
- * @brief   GPT1 interrupt priority level setting.
- */
-#if !defined(LPC_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_GPT_CT16B0_IRQ_PRIORITY         2
-#endif
-
-/**
- * @brief   GPT2 interrupt priority level setting.
- */
-#if !defined(LPC_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_GPT_CT16B1_IRQ_PRIORITY         2
-#endif
-
-/**
- * @brief   GPT3 interrupt priority level setting.
- */
-#if !defined(LPC_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_GPT_CT32B0_IRQ_PRIORITY         2
-#endif
-
-/**
- * @brief   GPT4 interrupt priority level setting.
- */
-#if !defined(LPC_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_GPT_CT32B1_IRQ_PRIORITY         2
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !LPC_GPT_USE_CT16B0 && !LPC_GPT_USE_CT16B1 &&                           \
-    !LPC_GPT_USE_CT32B0 && !LPC_GPT_USE_CT32B1
-#error "GPT driver activated but no CT peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the CTxxBy registers block.
-   */
-  LPC_CTxxBx_Type           *tmr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC_GPT_USE_CT16B0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if LPC_GPT_USE_CT16B1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if LPC_GPT_USE_CT32B0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#if LPC_GPT_USE_CT32B1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.c b/os/hal/platforms/LPC11Uxx/hal_lld.c
deleted file mode 100644
index 0e795c1a0..000000000
--- a/os/hal/platforms/LPC11Uxx/hal_lld.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/hal_lld.c
- * @brief   LPC11Uxx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* SysTick initialization using the system clock.*/
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
-  SysTick->LOAD = LPC_SYSCLK / CH_FREQUENCY - 1;
-  SysTick->VAL  = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
- * @brief   LPC11Uxx clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void lpc_clock_init(void) {
-  unsigned i;
-
-  /* Flash wait states setting, the code takes care to not touch TBD bits.*/
-  LPC_FLASHCTRL->FLASHCFG = (LPC_FLASHCTRL->FLASHCFG & ~3) |
-                            LPC_FLASHCFG_FLASHTIM;
-
-  /* System oscillator initialization if required.*/
-#if LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-#if LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC
-  LPC_SYSCON->SYSOSCCTRL = LPC_SYSOSCCTRL;
-  LPC_SYSCON->PDRUNCFG &= ~(1 << 5);            /* System oscillator ON.    */
-  for (i = 0; i < 200; i++)
-    __NOP();                                    /* Stabilization delay.     */
-#endif /* LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */
-
-  /* PLL initialization if required.*/
-  LPC_SYSCON->SYSPLLCLKSEL = LPC_PLLCLK_SOURCE;
-  LPC_SYSCON->SYSPLLCLKUEN = 1;                 /* Really required?         */
-  LPC_SYSCON->SYSPLLCLKUEN = 0;
-  LPC_SYSCON->SYSPLLCLKUEN = 1;
-  LPC_SYSCON->SYSPLLCTRL = LPC_SYSPLLCTRL_MSEL | LPC_SYSPLLCTRL_PSEL;
-  LPC_SYSCON->PDRUNCFG &= ~(1 << 7);            /* System PLL ON.           */
-  while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0)     /* Wait PLL lock.           */
-    ;
-#endif /* LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */
-
-  /* Main clock source selection.*/
-  LPC_SYSCON->MAINCLKSEL = LPC_MAINCLK_SOURCE;
-  LPC_SYSCON->MAINCLKUEN = 1;                   /* Really required?         */
-  LPC_SYSCON->MAINCLKUEN = 0;
-  LPC_SYSCON->MAINCLKUEN = 1;
-  while ((LPC_SYSCON->MAINCLKUEN & 1) == 0)     /* Wait switch completion.  */
-    ;
-
-  /* ABH divider initialization, peripheral clocks are initially disabled,
-     the various device drivers will handle their own setup except GPIO and
-     IOCON that are left enabled.*/
-  LPC_SYSCON->SYSAHBCLKDIV = LPC_SYSABHCLK_DIV;
-  LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F;
-
-  /* Memory remapping, vectors always in ROM.*/
-  LPC_SYSCON->SYSMEMREMAP = 2;
-}
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.h b/os/hal/platforms/LPC11Uxx/hal_lld.h
deleted file mode 100644
index 057dd47e3..000000000
--- a/os/hal/platforms/LPC11Uxx/hal_lld.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/hal_lld.h
- * @brief   HAL subsystem low level driver header template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "LPC11Uxx.h"
-#include "nvic.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME           "LPC11Uxx"
-
-#define IRCOSCCLK               12000000    /**< High speed internal clock. */
-#define WDGOSCCLK               1600000     /**< Watchdog internal clock.   */
-
-#define SYSPLLCLKSEL_IRCOSC     0           /**< Internal RC oscillator
-                                                 clock source.              */
-#define SYSPLLCLKSEL_SYSOSC     1           /**< System oscillator clock
-                                                 source.                    */
-
-#define SYSMAINCLKSEL_IRCOSC    0           /**< Clock source is IRC.       */
-#define SYSMAINCLKSEL_PLLIN     1           /**< Clock source is PLLIN.     */
-#define SYSMAINCLKSEL_WDGOSC    2           /**< Clock source is WDGOSC.    */
-#define SYSMAINCLKSEL_PLLOUT    3           /**< Clock source is PLLOUT.    */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   System PLL clock source.
- */
-#if !defined(LPC_PLLCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC_PLLCLK_SOURCE                   SYSPLLCLKSEL_SYSOSC
-#endif
-
-/**
- * @brief   System PLL multiplier.
- * @note    The value must be in the 1..32 range and the final frequency
- *          must not exceed the CCO ratings.
- */
-#if !defined(LPC_SYSPLL_MUL) || defined(__DOXYGEN__)
-#define LPC_SYSPLL_MUL                      4
-#endif
-
-/**
- * @brief   System PLL divider.
- * @note    The value must be chosen between (2, 4, 8, 16).
- */
-#if !defined(LPC_SYSPLL_DIV) || defined(__DOXYGEN__)
-#define LPC_SYSPLL_DIV                      4
-#endif
-
-/**
- * @brief   System main clock source.
- */
-#if !defined(LPC_MAINCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC_MAINCLK_SOURCE                  SYSMAINCLKSEL_PLLOUT
-#endif
-
-/**
- * @brief   AHB clock divider.
- * @note    The value must be chosen between (1...255).
- */
-#if !defined(LPC_SYSCLK_DIV) || defined(__DOXYGEN__)
-#define LPC_SYSABHCLK_DIV                   1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Calculated SYSOSCCTRL setting.
- */
-#if (SYSOSCCLK < 20000000) || defined(__DOXYGEN__)
-#define LPC_SYSOSCCTRL              0
-#else
-#define LPC_SYSOSCCTRL              1
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
-#define LPC_SYSPLLCLKIN             SYSOSCCLK
-#elif LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC
-#define LPC_SYSPLLCLKIN             IRCOSCCLK
-#else
-#error "invalid LPC_PLLCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   MSEL mask in SYSPLLCTRL register.
- */
-#if (LPC_SYSPLL_MUL >= 1) && (LPC_SYSPLL_MUL <= 32) || defined(__DOXYGEN__)
-#define LPC_SYSPLLCTRL_MSEL         (LPC_SYSPLL_MUL - 1)
-#else
-#error "LPC_SYSPLL_MUL out of range (1...32)"
-#endif
-
-/**
- * @brief   PSEL mask in SYSPLLCTRL register.
- */
-#if (LPC_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
-#define LPC_SYSPLLCTRL_PSEL (0 << 5)
-#elif LPC_SYSPLL_DIV == 4
-#define LPC_SYSPLLCTRL_PSEL (1 << 5)
-#elif LPC_SYSPLL_DIV == 8
-#define LPC_SYSPLLCTRL_PSEL (2 << 5)
-#elif LPC_SYSPLL_DIV == 16
-#define LPC_SYSPLLCTRL_PSEL (3 << 5)
-#else
-#error "invalid LPC_SYSPLL_DIV value (2,4,8,16)"
-#endif
-
-/**
- * @brief   CCP frequency.
- */
-#define  LPC_SYSPLLCCO              (LPC_SYSPLLCLKIN * LPC_SYSPLL_MUL *     \
-                                     LPC_SYSPLL_DIV)
-
-#if (LPC_SYSPLLCCO < 156000000) || (LPC_SYSPLLCCO > 320000000)
-#error "CCO frequency out of the acceptable range (156...320)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define  LPC_SYSPLLCLKOUT           (LPC_SYSPLLCCO / LPC_SYSPLL_DIV)
-
-#if (LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__)
-#define LPC_MAINCLK                 IRCOSCCLK
-#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
-#define LPC_MAINCLK                 LPC_SYSPLLCLKIN
-#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
-#define LPC_MAINCLK                 WDGOSCCLK
-#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-#define LPC_MAINCLK                 LPC_SYSPLLCLKOUT
-#else
-#error "invalid LPC_MAINCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   AHB clock.
- */
-#define  LPC_SYSCLK     (LPC_MAINCLK / LPC_SYSABHCLK_DIV)
-#if LPC_SYSCLK > 50000000
-#error "AHB clock frequency out of the acceptable range (50MHz max)"
-#endif
-
-/**
- * @brief   Flash wait states.
- */
-#if (LPC_SYSCLK <= 20000000) || defined(__DOXYGEN__)
-#define LPC_FLASHCFG_FLASHTIM       0
-#elif LPC_SYSCLK <= 40000000
-#define LPC_FLASHCFG_FLASHTIM       1
-#else
-#define LPC_FLASHCFG_FLASHTIM       2
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void lpc_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/pal_lld.c b/os/hal/platforms/LPC11Uxx/pal_lld.c
deleted file mode 100644
index 0b9d21391..000000000
--- a/os/hal/platforms/LPC11Uxx/pal_lld.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/pal_lld.c
- * @brief   LPC11Uxx GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-/**
- * @brief   LPC11Uxx I/O ports configuration.
- * @details GPIO unit registers initialization.
- *
- * @param[in] config    the LPC11Uxx ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  LPC_GPIO->DIR[0] = config->P0.dir;
-  LPC_GPIO->DIR[1] = config->P1.dir;
-  LPC_GPIO->PIN[0] = config->P0.data;
-  LPC_GPIO->PIN[1] = config->P1.data;
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    This function does not alter the @p PINSELx registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    LPC_GPIO->DIR[port] &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    palSetPort(port, PAL_WHOLE_PORT);
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    LPC_GPIO->DIR[port] |=  mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/pal_lld.h b/os/hal/platforms/LPC11Uxx/pal_lld.h
deleted file mode 100644
index a5072e70b..000000000
--- a/os/hal/platforms/LPC11Uxx/pal_lld.h
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/pal_lld.h
- * @brief   LPC11Uxx GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port setup info.
- */
-typedef struct {
-  /** Initial value for FIO_PIN register.*/
-  uint32_t      data;
-  /** Initial value for FIO_DIR register.*/
-  uint32_t      dir;
-} gpio_setup_t;
-
-/**
- * @brief   GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    The @p IOCON block is not configured, initially all pins have
- *          enabled pullups and are programmed as GPIO. It is responsibility
- *          of the various drivers to reprogram the pins in the proper mode.
- *          Pins that are not handled by any driver may be programmed in
- *          @p board.c.
- */
-typedef struct {
-  /** @brief GPIO 0 setup data.*/
-  gpio_setup_t  P0;
-  /** @brief GPIO 1 setup data.*/
-  gpio_setup_t  P1;
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef uint32_t ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO0 port identifier.
- */
-#define IOPORT1         0
-#define GPIO0           0
-
-/**
- * @brief   GPIO1 port identifier.
- */
-#define IOPORT2         1
-#define GPIO1           1
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) (LPC_GPIO->PIN[(port)])
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) (LPC_GPIO->SET[(port)])
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) (LPC_GPIO->PIN[(port)] = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) (LPC_GPIO->SET[(port)] = (bits))
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) (LPC_GPIO->CLR[(port)] = (bits))
-
-/**
- * @brief   Toggles a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be XORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_toggleport(port, bits) (LPC_GPIO->NOT[(port)] = (bits))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Reads a logical state from an I/O pad.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @return              The logical state.
- * @retval PAL_LOW      low logical state.
- * @retval PAL_HIGH     high logical state.
- *
- * @notapi
- */
-#define pal_lld_readpad(port, pad)                                          \
-  (LPC_GPIO->B[((port) * 32) + (pad)])
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)                                    \
-  ((LPC_GPIO->B[((port) * 32) + (pad)]) = (bit))
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-  (LPC_GPIO->SET[(port)] = 1 << (pad))
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-    (LPC_GPIO->CLR[(port)] = 1 << (pad))
-
-/**
- * @brief   Toggles a pad logical state.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad)                                        \
-    (LPC_GPIO->NOT[(port)] = 1 << (pad))
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/platform.mk b/os/hal/platforms/LPC11Uxx/platform.mk
deleted file mode 100644
index 508238833..000000000
--- a/os/hal/platforms/LPC11Uxx/platform.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# List of all the LPC11Uxx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC11Uxx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11Uxx/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11Uxx/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11Uxx/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11Uxx/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11Uxx/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11Uxx/ext_lld_isr.c 
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC11Uxx
diff --git a/os/hal/platforms/LPC11Uxx/serial_lld.c b/os/hal/platforms/LPC11Uxx/serial_lld.c
deleted file mode 100644
index 17587cbb0..000000000
--- a/os/hal/platforms/LPC11Uxx/serial_lld.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/serial_lld.c
- * @brief   LPC11Uxx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  LCR_WL8 | LCR_STOP1 | LCR_NOPARITY,
-  FCR_TRIGGER0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   USART initialization.
- *
- * @param[in] sdp       communication channel associated to the USART
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
-  LPC_USART_Type *u = sdp->uart;
-
-  uint32_t div = LPC_SERIAL_UART0_PCLK / (config->sc_speed << 4);
-  u->LCR = config->sc_lcr | LCR_DLAB;
-  u->DLL = div;
-  u->DLM = div >> 8;
-  u->LCR = config->sc_lcr;
-  u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr;
-  u->ACR = 0;
-  u->FDR = 0x10;
-  u->TER = TER_ENABLE;
-  u->IER = IER_RBR | IER_STATUS;
-}
-
-/**
- * @brief   USART de-initialization.
- *
- * @param[in] u         pointer to an USART I/O block
- */
-static void uart_deinit(LPC_USART_Type *u) {
-
-  u->LCR = LCR_DLAB;
-  u->DLL = 1;
-  u->DLM = 0;
-  u->LCR = 0;
-  u->FDR = 0x10;
-  u->IER = 0;
-  u->FCR = FCR_RXRESET | FCR_TXRESET;
-  u->ACR = 0;
-  u->TER = TER_ENABLE;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] err       UART LSR register value
- */
-static void set_error(SerialDriver *sdp, IOREG32 err) {
-  flagsmask_t sts = 0;
-
-  if (err & LSR_OVERRUN)
-    sts |= SD_OVERRUN_ERROR;
-  if (err & LSR_PARITY)
-    sts |= SD_PARITY_ERROR;
-  if (err & LSR_FRAMING)
-    sts |= SD_FRAMING_ERROR;
-  if (err & LSR_BREAK)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- * @note    Tries hard to clear all the pending interrupt sources, we don't
- *          want to go through the whole ISR and have another interrupt soon
- *          after.
- *
- * @param[in] u         pointer to an UART I/O block
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  LPC_USART_Type *u = sdp->uart;
-
-  while (TRUE) {
-    switch (u->IIR & IIR_SRC_MASK) {
-    case IIR_SRC_NONE:
-      return;
-    case IIR_SRC_ERROR:
-      set_error(sdp, u->LSR);
-      break;
-    case IIR_SRC_TIMEOUT:
-    case IIR_SRC_RX:
-      chSysLockFromIsr();
-      if (chIQIsEmptyI(&sdp->iqueue))
-        chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
-      chSysUnlockFromIsr();
-      while (u->LSR & LSR_RBR_FULL) {
-        chSysLockFromIsr();
-        if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK)
-          chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
-        chSysUnlockFromIsr();
-      }
-      break;
-    case IIR_SRC_TX:
-      {
-        int i = LPC_SERIAL_FIFO_PRELOAD;
-        do {
-          msg_t b;
-
-          chSysLockFromIsr();
-          b = chOQGetI(&sdp->oqueue);
-          chSysUnlockFromIsr();
-          if (b < Q_OK) {
-            u->IER &= ~IER_THRE;
-            chSysLockFromIsr();
-            chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-            chSysUnlockFromIsr();
-            break;
-          }
-          u->THR = b;
-        } while (--i);
-      }
-      break;
-    default:
-      (void) u->THR;
-      (void) u->RBR;
-    }
-  }
-}
-
-/**
- * @brief   Attempts a TX FIFO preload.
- */
-static void preload(SerialDriver *sdp) {
-  LPC_USART_Type *u = sdp->uart;
-
-  if (u->LSR & LSR_THRE) {
-    int i = LPC_SERIAL_FIFO_PRELOAD;
-    do {
-      msg_t b = chOQGetI(&sdp->oqueue);
-      if (b < Q_OK) {
-        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-        return;
-      }
-      u->THR = b;
-    } while (--i);
-  }
-  u->IER |= IER_THRE;
-}
-
-/**
- * @brief   Driver SD1 output notification.
- */
-#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD1);
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 IRQ handler.
- *
- * @isr
- */
-#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector94) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if LPC_SERIAL_USE_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = LPC_USART;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if LPC_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
-      LPC_SYSCON->UARTCLKDIV = LPC_SERIAL_UART0CLKDIV;
-      nvicEnableVector(UART_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC_SERIAL_UART0_IRQ_PRIORITY));
-    }
-#endif
-  }
-  uart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the UART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    uart_deinit(sdp->uart);
-#if LPC_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->UARTCLKDIV = 0;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12);
-      nvicDisableVector(UART_IRQn);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/serial_lld.h b/os/hal/platforms/LPC11Uxx/serial_lld.h
deleted file mode 100644
index 162e9ae16..000000000
--- a/os/hal/platforms/LPC11Uxx/serial_lld.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/serial_lld.h
- * @brief   LPC11Uxx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define IIR_SRC_MASK    0x0F
-#define IIR_SRC_NONE    0x01
-#define IIR_SRC_MODEM   0x00
-#define IIR_SRC_TX      0x02
-#define IIR_SRC_RX      0x04
-#define IIR_SRC_ERROR   0x06
-#define IIR_SRC_TIMEOUT 0x0C
-
-#define IER_RBR         1
-#define IER_THRE        2
-#define IER_STATUS      4
-
-#define LCR_WL5         0
-#define LCR_WL6         1
-#define LCR_WL7         2
-#define LCR_WL8         3
-#define LCR_STOP1       0
-#define LCR_STOP2       4
-#define LCR_NOPARITY    0
-#define LCR_PARITYODD   0x08
-#define LCR_PARITYEVEN  0x18
-#define LCR_PARITYONE   0x28
-#define LCR_PARITYZERO  0x38
-#define LCR_BREAK_ON    0x40
-#define LCR_DLAB        0x80
-
-#define FCR_ENABLE      1
-#define FCR_RXRESET     2
-#define FCR_TXRESET     4
-#define FCR_TRIGGER0    0
-#define FCR_TRIGGER1    0x40
-#define FCR_TRIGGER2    0x80
-#define FCR_TRIGGER3    0xC0
-
-#define LSR_RBR_FULL    1
-#define LSR_OVERRUN     2
-#define LSR_PARITY      4
-#define LSR_FRAMING     8
-#define LSR_BREAK       0x10
-#define LSR_THRE        0x20
-#define LSR_TEMT        0x40
-#define LSR_RXFE        0x80
-
-#define TER_ENABLE      0x80
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define LPC_SERIAL_USE_UART0                TRUE
-#endif
-
-/**
- * @brief   FIFO preload parameter.
- * @details Configuration parameter, this values defines how many bytes are
- *          preloaded in the HW transmit FIFO for each interrupt, the maximum
- *          value is 16 the minimum is 1.
- * @note    An high value reduces the number of interrupts generated but can
- *          also increase the worst case interrupt response time because the
- *          preload loops.
- */
-#if !defined(LPC_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__)
-#define LPC_SERIAL_FIFO_PRELOAD             16
-#endif
-
-/**
- * @brief   UART0 PCLK divider.
- */
-#if !defined(LPC_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__)
-#define LPC_SERIAL_UART0CLKDIV              1
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(LPC_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_SERIAL_UART0_IRQ_PRIORITY       3
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC_SERIAL_UART0CLKDIV < 1) || (LPC_SERIAL_UART0CLKDIV > 255)
-#error "invalid LPC_SERIAL_UART0CLKDIV setting"
-#endif
-
-#if (LPC_SERIAL_FIFO_PRELOAD < 1) || (LPC_SERIAL_FIFO_PRELOAD > 16)
-#error "invalid LPC_SERIAL_FIFO_PRELOAD setting"
-#endif
-
-/**
- * @brief   UART0 clock.
- */
-#define  LPC_SERIAL_UART0_PCLK                                          \
-  (LPC_MAINCLK / LPC_SERIAL_UART0CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   LPC11xx Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the LCR register.
-   */
-  uint32_t                  sc_lcr;
-  /**
-   * @brief Initialization value for the FCR register.
-   */
-  uint32_t                  sc_fcr;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  LPC_USART_Type            *uart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.c b/os/hal/platforms/LPC11Uxx/spi_lld.c
deleted file mode 100644
index 67282e8a4..000000000
--- a/os/hal/platforms/LPC11Uxx/spi_lld.c
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/spi_lld.c
- * @brief   LPC11Uxx low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/** @brief SPI2 driver identifier.*/
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Preloads the transmit FIFO.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void ssp_fifo_preload(SPIDriver *spip) {
-  LPC_SSPx_Type *ssp = spip->ssp;
-  uint32_t n = spip->txcnt > LPC_SSP_FIFO_DEPTH ?
-               LPC_SSP_FIFO_DEPTH : spip->txcnt;
-
-  while(((ssp->SR & SR_TNF) != 0) && (n > 0)) {
-    if (spip->txptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        const uint16_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-      else {
-        const uint8_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-    }
-    else
-      ssp->DR = 0xFFFFFFFF;
-    n--;
-    spip->txcnt--;
-  }
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void spi_serve_interrupt(SPIDriver *spip) {
-  LPC_SSPx_Type *ssp = spip->ssp;
-
-  if ((ssp->MIS & MIS_ROR) != 0) {
-    /* The overflow condition should never happen because priority is given
-       to receive but a hook macro is provided anyway...*/
-    LPC_SPI_SSP_ERROR_HOOK(spip);
-  }
-  ssp->ICR = ICR_RT | ICR_ROR;
-  while ((ssp->SR & SR_RNE) != 0) {
-    if (spip->rxptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        uint16_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-      else {
-        uint8_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-    }
-    else
-      (void)ssp->DR;
-    if (--spip->rxcnt == 0) {
-      chDbgAssert(spip->txcnt == 0,
-                  "spi_serve_interrupt(), #1", "counter out of synch");
-      /* Stops the IRQ sources.*/
-      ssp->IMSC = 0;
-      /* Portable SPI ISR code defined in the high level driver, note, it is
-         a macro.*/
-      _spi_isr_code(spip);
-      return;
-    }
-  }
-  ssp_fifo_preload(spip);
-  if (spip->txcnt == 0)
-    ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/**
- * @brief   SSP0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector90) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/**
- * @brief   SSP1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector78) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if LPC_SPI_USE_SSP0
-  spiObjectInit(&SPID1);
-  SPID1.ssp = LPC_SSP0;
-#endif /* LPC_SPI_USE_SSP0 */
-
-#if LPC_SPI_USE_SSP1
-  spiObjectInit(&SPID2);
-  SPID2.ssp = LPC_SSP1;
-#endif /* LPC_SPI_USE_SSP0 */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-    /* Clock activation.*/
-#if LPC_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SYSCON->SSP0CLKDIV = LPC_SPI_SSP0CLKDIV;
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11);
-      LPC_SYSCON->PRESETCTRL |= 1;
-      nvicEnableVector(SSP0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC_SPI_SSP0_IRQ_PRIORITY));
-    }
-#endif
-#if LPC_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_SYSCON->SSP1CLKDIV = LPC_SPI_SSP1CLKDIV;
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18);
-      LPC_SYSCON->PRESETCTRL |= 4;
-      nvicEnableVector(SSP1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC_SPI_SSP1_IRQ_PRIORITY));
-    }
-#endif
-  }
-  /* Configuration.*/
-  spip->ssp->CR1  = 0;
-  spip->ssp->ICR  = ICR_RT | ICR_ROR;
-  spip->ssp->CR0  = spip->config->cr0;
-  spip->ssp->CPSR = spip->config->cpsr;
-  spip->ssp->CR1  = CR1_SSE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state != SPI_STOP) {
-    spip->ssp->CR1  = 0;
-    spip->ssp->CR0  = 0;
-    spip->ssp->CPSR = 0;
-#if LPC_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SYSCON->PRESETCTRL &= ~1;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11);
-      LPC_SYSCON->SSP0CLKDIV = 0;
-      nvicDisableVector(SSP0_IRQn);
-    }
-#endif
-#if LPC_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_SYSCON->PRESETCTRL &= ~4;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18);
-      LPC_SYSCON->SSP1CLKDIV = 0;
-      nvicDisableVector(SSP1_IRQn);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->rxptr = NULL;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->rxptr = NULL;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->ssp->DR = (uint32_t)frame;
-  while ((spip->ssp->SR & SR_RNE) == 0)
-    ;
-  return (uint16_t)spip->ssp->DR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.h b/os/hal/platforms/LPC11Uxx/spi_lld.h
deleted file mode 100644
index 9d15dcee2..000000000
--- a/os/hal/platforms/LPC11Uxx/spi_lld.h
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11Uxx/spi_lld.h
- * @brief   LPC11Uxx low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Hardware FIFO depth.
- */
-#define LPC_SSP_FIFO_DEPTH      8
-
-#define CR0_DSSMASK             0x0F
-#define CR0_DSS4BIT             3
-#define CR0_DSS5BIT             4
-#define CR0_DSS6BIT             5
-#define CR0_DSS7BIT             6
-#define CR0_DSS8BIT             7
-#define CR0_DSS9BIT             8
-#define CR0_DSS10BIT            9
-#define CR0_DSS11BIT            0xA
-#define CR0_DSS12BIT            0xB
-#define CR0_DSS13BIT            0xC
-#define CR0_DSS14BIT            0xD
-#define CR0_DSS15BIT            0xE
-#define CR0_DSS16BIT            0xF
-#define CR0_FRFSPI              0
-#define CR0_FRFSSI              0x10
-#define CR0_FRFMW               0x20
-#define CR0_CPOL                0x40
-#define CR0_CPHA                0x80
-#define CR0_CLOCKRATE(n)        ((n) << 8)
-
-#define CR1_LBM                 1
-#define CR1_SSE                 2
-#define CR1_MS                  4
-#define CR1_SOD                 8
-
-#define SR_TFE                  1
-#define SR_TNF                  2
-#define SR_RNE                  4
-#define SR_RFF                  8
-#define SR_BSY                  16
-
-#define IMSC_ROR                1
-#define IMSC_RT                 2
-#define IMSC_RX                 4
-#define IMSC_TX                 8
-
-#define RIS_ROR                 1
-#define RIS_RT                  2
-#define RIS_RX                  4
-#define RIS_TX                  8
-
-#define MIS_ROR                 1
-#define MIS_RT                  2
-#define MIS_RX                  4
-#define MIS_TX                  8
-
-#define ICR_ROR                 1
-#define ICR_RT                  2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for device SSP0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_SPI_USE_SSP0) || defined(__DOXYGEN__)
-#define LPC_SPI_USE_SSP0                    TRUE
-#endif
-
-/**
- * @brief   SPI2 driver enable switch.
- * @details If set to @p TRUE the support for device SSP1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_SPI_USE_SSP1) || defined(__DOXYGEN__)
-#define LPC_SPI_USE_SSP1                    TRUE
-#endif
-
-/**
- * @brief   SSP0 PCLK divider.
- */
-#if !defined(LPC_SPI_SSP0CLKDIV) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP0CLKDIV                  1
-#endif
-
-/**
- * @brief   SSP1 PCLK divider.
- */
-#if !defined(LPC_SPI_SSP1CLKDIV) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP1CLKDIV                  1
-#endif
-
-/**
- * @brief   SPI0 interrupt priority level setting.
- */
-#if !defined(LPC_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP0_IRQ_PRIORITY           1
-#endif
-
-/**
- * @brief   SPI1 interrupt priority level setting.
- */
-#if !defined(LPC_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP1_IRQ_PRIORITY           1
-#endif
-
-/**
- * @brief   Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(LPC_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP_ERROR_HOOK(spip)        chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC_SPI_SSP0CLKDIV < 1) || (LPC_SPI_SSP0CLKDIV > 255)
-#error "invalid LPC_SPI_SSP0CLKDIV setting"
-#endif
-
-#if (LPC_SPI_SSP1CLKDIV < 1) || (LPC_SPI_SSP1CLKDIV > 255)
-#error "invalid LPC_SPI_SSP1CLKDIV setting"
-#endif
-
-#if !LPC_SPI_USE_SSP0 && !LPC_SPI_USE_SSP1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-/**
- * @brief   SSP0 clock.
- */
-#define LPC_SPI_SSP0_PCLK                                                   \
-  (LPC_MAINCLK / LPC_SPI_SSP0CLKDIV)
-
-/**
- * @brief   SSP1 clock.
- */
-#define LPC_SPI_SSP1_PCLK                                                   \
-  (LPC_MAINCLK / LPC_SPI_SSP1CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief SSP CR0 initialization data.
-   */
-  uint16_t              cr0;
-  /**
-   * @brief SSP CPSR initialization data.
-   */
-  uint32_t              cpsr;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SSP registers block.
-   */
-  LPC_SSPx_Type         *ssp;
-  /**
-   * @brief Number of bytes yet to be received.
-   */
-  uint32_t              rxcnt;
-  /**
-   * @brief Receive pointer or @p NULL.
-   */
-  void                  *rxptr;
-  /**
-   * @brief Number of bytes yet to be transmitted.
-   */
-  uint32_t              txcnt;
-  /**
-   * @brief Transmit pointer or @p NULL.
-   */
-  const void            *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC_SPI_USE_SSP0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if LPC_SPI_USE_SSP1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h b/os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h
deleted file mode 100644
index e490d17dc..000000000
--- a/os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC11Uxx.h
- * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Header File
- *           for the NXP LPC11Uxx Device Series
- * @version  V1.10
- * @date     24. November 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC11Uxx_H
-#define __SYSTEM_LPC11Uxx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC11Uxx_H */
diff --git a/os/hal/platforms/LPC11xx/LPC11xx.h b/os/hal/platforms/LPC11xx/LPC11xx.h
deleted file mode 100644
index 3f96459c7..000000000
--- a/os/hal/platforms/LPC11xx/LPC11xx.h
+++ /dev/null
@@ -1,561 +0,0 @@
-/****************************************************************************
- *   $Id:: LPC11xx.h 4070 2010-07-30 03:16:37Z usb00423                     $
- *   Project: NXP LPC11xx software example  
- *
- *   Description:
- *     CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 
- *     NXP LPC11xx Device Series 
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __LPC11xx_H__
-#define __LPC11xx_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup LPC11xx_Definitions LPC11xx Definitions
-  This file defines all structures and symbols for LPC11xx:
-    - Registers and bitfields
-    - peripheral base address
-    - peripheral ID
-    - PIO definitions
-  @{
-*/
-
-
-/******************************************************************************/
-/*                Processor and Core Peripherals                              */
-/******************************************************************************/
-/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
-  Configuration of the Cortex-M0 Processor and Core Peripherals
-  @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-typedef enum IRQn
-{
-/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,    /*!< 2 Non Maskable Interrupt                           */
-  HardFault_IRQn                = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                   */
-  SVCall_IRQn                   = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                     */
-  PendSV_IRQn                   = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                     */
-  SysTick_IRQn                  = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                 */
-
-/******  LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/
-  WAKEUP0_IRQn                  = 0,        /*!< All I/O pins can be used as wakeup source.       */
-  WAKEUP1_IRQn                  = 1,        /*!< There are 13 pins in total for LPC11xx           */
-  WAKEUP2_IRQn                  = 2,
-  WAKEUP3_IRQn                  = 3,
-  WAKEUP4_IRQn                  = 4,   
-  WAKEUP5_IRQn                  = 5,        
-  WAKEUP6_IRQn                  = 6,        
-  WAKEUP7_IRQn                  = 7,        
-  WAKEUP8_IRQn                  = 8,        
-  WAKEUP9_IRQn                  = 9,        
-  WAKEUP10_IRQn                 = 10,       
-  WAKEUP11_IRQn                 = 11,       
-  WAKEUP12_IRQn                 = 12,       
-  CAN_IRQn                      = 13,       /*!< CAN Interrupt                                    */
-  SSP1_IRQn                     = 14,       /*!< SSP1 Interrupt                                   */
-  I2C_IRQn                      = 15,       /*!< I2C Interrupt                                    */
-  TIMER_16_0_IRQn               = 16,       /*!< 16-bit Timer0 Interrupt                          */
-  TIMER_16_1_IRQn               = 17,       /*!< 16-bit Timer1 Interrupt                          */
-  TIMER_32_0_IRQn               = 18,       /*!< 32-bit Timer0 Interrupt                          */
-  TIMER_32_1_IRQn               = 19,       /*!< 32-bit Timer1 Interrupt                          */
-  SSP0_IRQn                     = 20,       /*!< SSP0 Interrupt                                   */
-  UART_IRQn                     = 21,       /*!< UART Interrupt                                   */
-  Reserved0_IRQn                = 22,       /*!< Reserved Interrupt                               */
-  Reserved1_IRQn                = 23,       
-  ADC_IRQn                      = 24,       /*!< A/D Converter Interrupt                          */
-  WDT_IRQn                      = 25,       /*!< Watchdog timer Interrupt                         */  
-  BOD_IRQn                      = 26,       /*!< Brown Out Detect(BOD) Interrupt                  */
-  FMC_IRQn                      = 27,       /*!< Flash Memory Controller Interrupt                */
-  EINT3_IRQn                    = 28,       /*!< External Interrupt 3 Interrupt                   */
-  EINT2_IRQn                    = 29,       /*!< External Interrupt 2 Interrupt                   */
-  EINT1_IRQn                    = 30,       /*!< External Interrupt 1 Interrupt                   */
-  EINT0_IRQn                    = 31,       /*!< External Interrupt 0 Interrupt                   */
-} IRQn_Type;
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             0         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-/*@}*/ /* end of group LPC11xx_CMSIS */
-
-
-#include "core_cm0.h"                       /* Cortex-M0 processor and core peripherals           */
-#include "system_LPC11xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral Registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SYSCON) --------------------------------------*/
-/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 System memory remap (R/W) */
-  __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 Peripheral reset control (R/W) */
-  __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 System PLL control (R/W) */
-  __IO uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/W ) */
-       uint32_t RESERVED0[4];
-
-  __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 System oscillator control (R/W) */
-  __IO uint32_t WDTOSCCTRL;             /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
-  __IO uint32_t IRCCTRL;                /*!< Offset: 0x028 IRC control (R/W) */
-       uint32_t RESERVED1[1];
-  __IO uint32_t SYSRESSTAT;             /*!< Offset: 0x030 System reset status Register (R/ ) */
-       uint32_t RESERVED2[3];
-  __IO uint32_t SYSPLLCLKSEL;           /*!< Offset: 0x040 System PLL clock source select (R/W) */	
-  __IO uint32_t SYSPLLCLKUEN;           /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
-       uint32_t RESERVED3[10];
-
-  __IO uint32_t MAINCLKSEL;             /*!< Offset: 0x070 Main clock source select (R/W) */
-  __IO uint32_t MAINCLKUEN;             /*!< Offset: 0x074 Main clock source update enable (R/W) */
-  __IO uint32_t SYSAHBCLKDIV;           /*!< Offset: 0x078 System AHB clock divider (R/W) */
-       uint32_t RESERVED4[1];
-
-  __IO uint32_t SYSAHBCLKCTRL;          /*!< Offset: 0x080 System AHB clock control (R/W) */
-       uint32_t RESERVED5[4];
-  __IO uint32_t SSP0CLKDIV;             /*!< Offset: 0x094 SSP0 clock divider (R/W) */          
-  __IO uint32_t UARTCLKDIV;             /*!< Offset: 0x098 UART clock divider (R/W) */
-  __IO uint32_t SSP1CLKDIV;             /*!< Offset: 0x09C SSP1 clock divider (R/W) */          
-       uint32_t RESERVED6[4];
-
-  __IO uint32_t SYSTICKCLKDIV;          /*!< Offset: 0x0B0 SYSTICK clock divider (R/W) */          
-       uint32_t RESERVED7[7];
-
-  __IO uint32_t WDTCLKSEL;              /*!< Offset: 0x0D0 WDT clock source select (R/W) */
-  __IO uint32_t WDTCLKUEN;              /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
-  __IO uint32_t WDTCLKDIV;              /*!< Offset: 0x0D8 WDT clock divider (R/W) */
-       uint32_t RESERVED8[1];              
-  __IO uint32_t CLKOUTCLKSEL;           /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
-  __IO uint32_t CLKOUTUEN;              /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
-  __IO uint32_t CLKOUTDIV;              /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */       
-       uint32_t RESERVED9[5];
-  
-  __IO uint32_t PIOPORCAP0;             /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */           
-  __IO uint32_t PIOPORCAP1;             /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */   
-       uint32_t RESERVED10[18];
-  __IO uint32_t BODCTRL;                /*!< Offset: 0x150 BOD control (R/W) */
-       uint32_t RESERVED11[1];
-  __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x158 System tick counter calibration (R/W) */
-       uint32_t RESERVED12;
-  __IO uint32_t MAINREGVOUT0CFG;        /*!< Offset: 0x160 Main Regulator Voltage 0 Configuration */ 
-  __IO uint32_t MAINREGVOUT1CFG;        /*!< Offset: 0x164 Main Regulator Voltage 1 Configuration */
-       uint32_t RESERVED13[38];
-
-  __IO uint32_t STARTAPRP0;             /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */     
-  __IO uint32_t STARTERP0;              /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */      
-  __O  uint32_t STARTRSRP0CLR;          /*!< Offset: 0x208 Start logic reset Register 0  ( /W) */
-  __IO uint32_t STARTSRP0;              /*!< Offset: 0x20C Start logic status Register 0 (R/W) */
-  __IO uint32_t STARTAPRP1;             /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */     
-  __IO uint32_t STARTERP1;              /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */      
-  __O  uint32_t STARTRSRP1CLR;          /*!< Offset: 0x218 Start logic reset Register 0  ( /W). (LPC11UXX only) */
-  __IO uint32_t STARTSRP1;              /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */
-       uint32_t RESERVED17[4];
-
-  __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
-  __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 Power-down states after wake-up (R/W) */        
-  __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 Power-down configuration Register (R/W) */
-       uint32_t RESERVED15[101];
-  __O  uint32_t VOUTCFGPROT;            /*!< Offset: 0x3D0 Voltage Output Configuration Protection Register (W) */
-       uint32_t RESERVED16[8];
-  __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 Device ID (R/ ) */
-} LPC_SYSCON_TypeDef;
-/*@}*/ /* end of group LPC11xx_SYSCON */
-
-
-/*------------- Pin Connect Block (IOCON) --------------------------------*/
-/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t PIO2_6;                 /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
-       uint32_t RESERVED0[1];
-  __IO uint32_t PIO2_0;                 /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
-  __IO uint32_t RESET_PIO0_0;           /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0  (R/W) */
-  __IO uint32_t PIO0_1;                 /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
-  __IO uint32_t PIO1_8;                 /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
-       uint32_t RESERVED1[1];
-  __IO uint32_t PIO0_2;                 /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
-
-  __IO uint32_t PIO2_7;                 /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
-  __IO uint32_t PIO2_8;                 /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
-  __IO uint32_t PIO2_1;                 /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
-  __IO uint32_t PIO0_3;                 /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
-  __IO uint32_t PIO0_4;                 /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
-  __IO uint32_t PIO0_5;                 /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
-  __IO uint32_t PIO1_9;                 /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
-  __IO uint32_t PIO3_4;                 /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
-
-  __IO uint32_t PIO2_4;                 /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
-  __IO uint32_t PIO2_5;                 /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
-  __IO uint32_t PIO3_5;                 /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
-  __IO uint32_t PIO0_6;                 /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
-  __IO uint32_t PIO0_7;                 /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
-  __IO uint32_t PIO2_9;                 /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
-  __IO uint32_t PIO2_10;                /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
-  __IO uint32_t PIO2_2;                 /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
-
-  __IO uint32_t PIO0_8;                 /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
-  __IO uint32_t PIO0_9;                 /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
-  __IO uint32_t SWCLK_PIO0_10;          /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
-  __IO uint32_t PIO1_10;                /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
-  __IO uint32_t PIO2_11;                /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
-  __IO uint32_t R_PIO0_11;              /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
-  __IO uint32_t R_PIO1_0;               /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
-  __IO uint32_t R_PIO1_1;               /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
-
-  __IO uint32_t R_PIO1_2;               /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
-  __IO uint32_t PIO3_0;                 /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
-  __IO uint32_t PIO3_1;                 /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
-  __IO uint32_t PIO2_3;                 /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
-  __IO uint32_t SWDIO_PIO1_3;           /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
-  __IO uint32_t PIO1_4;                 /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
-  __IO uint32_t PIO1_11;                /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
-  __IO uint32_t PIO3_2;                 /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
-
-  __IO uint32_t PIO1_5;                 /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
-  __IO uint32_t PIO1_6;                 /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
-  __IO uint32_t PIO1_7;                 /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
-  __IO uint32_t PIO3_3;                 /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
-  __IO uint32_t SCK_LOC;                /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
-  __IO uint32_t DSR_LOC;                /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
-  __IO uint32_t DCD_LOC;                /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
-  __IO uint32_t RI_LOC;                 /*!< Offset: 0x0BC RI pin location Register (R/W) */
-} LPC_IOCON_TypeDef;
-/*@}*/ /* end of group LPC11xx_IOCON */
-
-
-/*------------- Power Management Unit (PMU) --------------------------*/
-/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t PCON;                   /*!< Offset: 0x000 Power control Register (R/W) */
-  __IO uint32_t GPREG0;                 /*!< Offset: 0x004 General purpose Register 0 (R/W) */
-  __IO uint32_t GPREG1;                 /*!< Offset: 0x008 General purpose Register 1 (R/W) */
-  __IO uint32_t GPREG2;                 /*!< Offset: 0x00C General purpose Register 2 (R/W) */
-  __IO uint32_t GPREG3;                 /*!< Offset: 0x010 General purpose Register 3 (R/W) */
-  __IO uint32_t GPREG4;                 /*!< Offset: 0x014 General purpose Register 4 (R/W) */
-} LPC_PMU_TypeDef;
-/*@}*/ /* end of group LPC11xx_PMU */
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output 
-  @{
-*/
-typedef struct
-{
-  union {
-    __IO uint32_t MASKED_ACCESS[4096];  /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
-    struct {
-         uint32_t RESERVED0[4095];
-    __IO uint32_t DATA;                 /*!< Offset: 0x3FFC Port data Register (R/W) */
-    };
-  };
-       uint32_t RESERVED1[4096];
-  __IO uint32_t DIR;                    /*!< Offset: 0x8000 Data direction Register (R/W) */
-  __IO uint32_t IS;                     /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
-  __IO uint32_t IBE;                    /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
-  __IO uint32_t IEV;                    /*!< Offset: 0x800C Interrupt event Register  (R/W) */
-  __IO uint32_t IE;                     /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
-  __IO uint32_t RIS;                    /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
-  __IO uint32_t MIS;                    /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
-  __IO uint32_t IC;                     /*!< Offset: 0x801C Interrupt clear Register (R/W) */
-} LPC_GPIO_TypeDef;
-/*@}*/ /* end of group LPC11xx_GPIO */
-
-/*------------- Timer (TMR) --------------------------------------------------*/
-/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-       uint32_t RESERVED1[3];
-  __IO uint32_t EMR;                    /*!< Offset: 0x03C External Match Register (R/W) */
-       uint32_t RESERVED2[12];
-  __IO uint32_t CTCR;                   /*!< Offset: 0x070 Count Control Register (R/W) */
-  __IO uint32_t PWMC;                   /*!< Offset: 0x074 PWM Control Register (R/W) */
-} LPC_TMR_TypeDef;
-/*@}*/ /* end of group LPC11xx_TMR */
-
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter 
-  @{
-*/
-typedef struct
-{
-  union {
-  __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
-  __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
-  __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
-  };
-  union {
-  __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
-  __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
-  };
-  union {
-  __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
-  __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
-  };
-  __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
-  __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */
-  __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
-  __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */
-  __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
-  __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
-       uint32_t  RESERVED0;
-  __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
-       uint32_t  RESERVED1;
-  __IO uint32_t  TER;                   /*!< Offset: 0x030 Transmit Enable Register (R/W) */
-       uint32_t  RESERVED2[6];
-  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
-  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
-  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
-  __I  uint32_t  FIFOLVL;               /*!< Offset: 0x058 FIFO Level Register (R) */
-} LPC_UART_TypeDef;
-/*@}*/ /* end of group LPC11xx_UART */
-
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CR0;                    /*!< Offset: 0x000 Control Register 0 (R/W) */
-  __IO uint32_t CR1;                    /*!< Offset: 0x004 Control Register 1 (R/W) */
-  __IO uint32_t DR;                     /*!< Offset: 0x008 Data Register (R/W) */
-  __I  uint32_t SR;                     /*!< Offset: 0x00C Status Registe (R/ ) */
-  __IO uint32_t CPSR;                   /*!< Offset: 0x010 Clock Prescale Register (R/W) */
-  __IO uint32_t IMSC;                   /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
-  __IO uint32_t RIS;                    /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
-  __IO uint32_t MIS;                    /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
-  __IO uint32_t ICR;                    /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
-} LPC_SSP_TypeDef;
-/*@}*/ /* end of group LPC11xx_SSP */
-
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ ) */
-  __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W) */
-  __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
-  __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
-  __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
-  __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
-  __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W) */
-  __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
-  __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
-  __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
-  __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W) */
-  __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
-  __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
-  __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
-  __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
-} LPC_I2C_TypeDef;
-/*@}*/ /* end of group LPC11xx_I2C */
-
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t MOD;                    /*!< Offset: 0x000 Watchdog mode register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
-  __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register (W) */
-  __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R) */
-       uint32_t RESERVED0;
-  __IO uint32_t WARNINT;				/*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
-  __IO uint32_t WINDOW;					/*!< Offset: 0x018 Watchdog timer window value register (R/W) */
-} LPC_WDT_TypeDef;
-/*@}*/ /* end of group LPC11xx_WDT */
-
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W) */
-  __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W) */
-       uint32_t RESERVED0;
-  __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W) */
-  __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ ) */
-} LPC_ADC_TypeDef;
-/*@}*/ /* end of group LPC11xx_ADC */
-
-
-/*------------- CAN Controller (CAN) ----------------------------*/
-/** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN) 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CNTL;				/* 0x000 */
-  __IO uint32_t STAT;
-  __IO uint32_t EC;
-  __IO uint32_t BT;
-  __IO uint32_t INT;
-  __IO uint32_t TEST;
-  __IO uint32_t BRPE;
-       uint32_t RESERVED0;
-  __IO uint32_t IF1_CMDREQ;			/* 0x020 */
-  __IO uint32_t IF1_CMDMSK;
-  __IO uint32_t IF1_MSK1;
-  __IO uint32_t IF1_MSK2;
-  __IO uint32_t IF1_ARB1;
-  __IO uint32_t IF1_ARB2;
-  __IO uint32_t IF1_MCTRL;
-  __IO uint32_t IF1_DA1;
-  __IO uint32_t IF1_DA2;
-  __IO uint32_t IF1_DB1;
-  __IO uint32_t IF1_DB2;
-       uint32_t RESERVED1[13];   
-  __IO uint32_t IF2_CMDREQ;			/* 0x080 */
-  __IO uint32_t IF2_CMDMSK;
-  __IO uint32_t IF2_MSK1;
-  __IO uint32_t IF2_MSK2;
-  __IO uint32_t IF2_ARB1;
-  __IO uint32_t IF2_ARB2;
-  __IO uint32_t IF2_MCTRL;
-  __IO uint32_t IF2_DA1;
-  __IO uint32_t IF2_DA2;
-  __IO uint32_t IF2_DB1;
-  __IO uint32_t IF2_DB2;
-       uint32_t RESERVED2[21];
-  __I  uint32_t TXREQ1;				/* 0x100 */
-  __I  uint32_t TXREQ2;
-       uint32_t RESERVED3[6];
-  __I  uint32_t ND1;				/* 0x120 */
-  __I  uint32_t ND2;
-       uint32_t RESERVED4[6];
-  __I  uint32_t IR1;				/* 0x140 */
-  __I  uint32_t IR2;
-       uint32_t RESERVED5[6];
-  __I  uint32_t MSGV1;				/* 0x160 */
-  __I  uint32_t MSGV2;
-       uint32_t RESERVED6[6];
-  __IO uint32_t CLKDIV;				/* 0x180 */
-} LPC_CAN_TypeDef;
-/*@}*/ /* end of group LPC11xx_CAN */
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_AHB_BASE          (0x50000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_I2C_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x04000)
-#define LPC_UART_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_CT16B0_BASE       (LPC_APB0_BASE + 0x0C000)
-#define LPC_CT16B1_BASE       (LPC_APB0_BASE + 0x10000)
-#define LPC_CT32B0_BASE       (LPC_APB0_BASE + 0x14000)
-#define LPC_CT32B1_BASE       (LPC_APB0_BASE + 0x18000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x1C000)
-#define LPC_PMU_BASE          (LPC_APB0_BASE + 0x38000)
-#define LPC_SSP0_BASE         (LPC_APB0_BASE + 0x40000)
-#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)
-#define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)
-#define LPC_CAN_BASE          (LPC_APB0_BASE + 0x50000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x58000)
-
-/* AHB peripherals                                                            */
-#define LPC_GPIO_BASE         (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x10000)
-#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x20000)
-#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x30000)
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )
-#define LPC_WDT               ((LPC_WDT_TypeDef    *) LPC_WDT_BASE   )
-#define LPC_UART              ((LPC_UART_TypeDef   *) LPC_UART_BASE  )
-#define LPC_TMR16B0           ((LPC_TMR_TypeDef    *) LPC_CT16B0_BASE)
-#define LPC_TMR16B1           ((LPC_TMR_TypeDef    *) LPC_CT16B1_BASE)
-#define LPC_TMR32B0           ((LPC_TMR_TypeDef    *) LPC_CT32B0_BASE)
-#define LPC_TMR32B1           ((LPC_TMR_TypeDef    *) LPC_CT32B1_BASE)
-#define LPC_ADC               ((LPC_ADC_TypeDef    *) LPC_ADC_BASE   )
-#define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )
-#define LPC_SSP0              ((LPC_SSP_TypeDef    *) LPC_SSP0_BASE  )
-#define LPC_SSP1              ((LPC_SSP_TypeDef    *) LPC_SSP1_BASE  )
-#define LPC_CAN               ((LPC_CAN_TypeDef    *) LPC_CAN_BASE   )
-#define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )
-#define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __LPC11xx_H__ */
diff --git a/os/hal/platforms/LPC11xx/ext_lld.c b/os/hal/platforms/LPC11xx/ext_lld.c
deleted file mode 100644
index c22cd83be..000000000
--- a/os/hal/platforms/LPC11xx/ext_lld.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/ext_lld.c
- * @brief   LPC11xx EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTD0 driver identifier.
- */
-#if LPC11xx_EXT_USE_EXT0 || defined(__DOXYGEN__)
-EXTDriver EXTD0;
-#endif
-
-/**
- * @brief   EXTD1 driver identifier.
- */
-#if LPC11xx_EXT_USE_EXT1 || defined(__DOXYGEN__)
-EXTDriver EXTD1;
-#endif
-
-/**
- * @brief   EXTD2 driver identifier.
- */
-#if LPC11xx_EXT_USE_EXT2 || defined(__DOXYGEN__)
-EXTDriver EXTD2;
-#endif
-
-/**
- * @brief   EXTD3 driver identifier.
- */
-#if LPC11xx_EXT_USE_EXT3 || defined(__DOXYGEN__)
-EXTDriver EXTD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
-  /* Driver initialization.*/
-#if LPC11xx_EXT_USE_EXT0
-  extObjectInit(&EXTD0);
-  EXTD0.gpio = LPC_GPIO0;
-#endif
-
-#if LPC11xx_EXT_USE_EXT1
-  extObjectInit(&EXTD1);
-  EXTD1.gpio = LPC_GPIO1;
-#endif
-
-#if LPC11xx_EXT_USE_EXT2
-  extObjectInit(&EXTD2);
-  EXTD2.gpio = LPC_GPIO2;
-#endif
-
-#if LPC11xx_EXT_USE_EXT3
-  extObjectInit(&EXTD3);
-  EXTD3.gpio = LPC_GPIO3;
-#endif
-}
-
-/**
- * @brief   Configures and activates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
-  int i;
-
-  /* Configure all pins as edge sensitive */
-#if LPC11xx_EXT_USE_EXT0
-  if (extp == &EXTD0) {
-    LPC_GPIO0->IS = 0;
-    ext_lld_exti_irq_enable(EXTI0_IRQ);
-  }
-#endif
-
-#if LPC11xx_EXT_USE_EXT1
-  if (extp == &EXTD1) {
-    LPC_GPIO1->IS = 0;
-    ext_lld_exti_irq_enable(EXTI1_IRQ);
-  }
-#endif
-
-#if LPC11xx_EXT_USE_EXT2
-  if (extp == &EXTD2) {
-    LPC_GPIO2->IS = 0;
-    ext_lld_exti_irq_enable(EXTI2_IRQ);
-  }
-#endif
-
-#if LPC11xx_EXT_USE_EXT3
-  if (extp == &EXTD3) {
-    LPC_GPIO3->IS = 0;
-    ext_lld_exti_irq_enable(EXTI3_IRQ);
-  }
-#endif
-
-  /* Configuration of autostart channels.*/
-  for (i = 0; i < EXT_MAX_CHANNELS; i++)
-    if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
-      ext_lld_channel_enable(extp, i);
-    else
-      ext_lld_channel_disable(extp, i);
-}
-
-/**
- * @brief   Deactivates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-
-  LPC_GPIO_TypeDef * gp = extp->gpio;
-
-  if (extp->state == EXT_ACTIVE) {
-#if LPC11xx_EXT_USE_EXT0
-    if (extp == &EXTD0) {
-      ext_lld_exti_irq_disable(EXTI0_IRQ);
-    }
-#endif
-
-#if LPC11xx_EXT_USE_EXT1
-    if (extp == &EXTD1) {
-      ext_lld_exti_irq_disable(EXTI1_IRQ);
-    }
-#endif
-
-#if LPC11xx_EXT_USE_EXT2
-    if (extp == &EXTD2) {
-      ext_lld_exti_irq_disable(EXTI2_IRQ);
-    }
-#endif
-
-#if LPC11xx_EXT_USE_EXT3
-    if (extp == &EXTD3) {
-      ext_lld_exti_irq_disable(EXTI3_IRQ);
-    }
-#endif
-  }
-
-  gp->IE = 0;
-  gp->IC = 0xFFFFFFFF;
-  __NOP();
-  __NOP();
-}
-
-/**
- * @brief   Enables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
-  LPC_GPIO_TypeDef * gp;
-
-  gp = extp->gpio;
-  
-  /* Programming edge irq enables */
-  if (extp->config->channels[channel].mode & EXT_CH_MODE_BOTH_EDGES)
-    gp->IBE |=  (1 << channel);
-  else {
-    gp->IBE &=  ~(1 << channel);
-    if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
-      gp->IEV |= (1 << channel);
-    else
-      gp->IEV &= (1 << channel);
-  }
-
-  gp->IC = (1 << channel);    /* Clear interrupt on selected channel */
-  __NOP();
-  __NOP();
-
-  gp->IE |= (1 << channel);  /* Interrupt on selected channel
-                                    is not masked */
-}
-
-/**
- * @brief   Disables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-
-  LPC_GPIO_TypeDef * gp;
-
-  gp = extp->gpio;
-
-  gp->IE &= ~(1 << channel);   /* Mask interrupt on selected channel */
-  gp->IC = (1 << channel);      /* Clear interrupt on selected channel */
-  __NOP();
-  __NOP();
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/ext_lld.h b/os/hal/platforms/LPC11xx/ext_lld.h
deleted file mode 100644
index 9a05f6d22..000000000
--- a/os/hal/platforms/LPC11xx/ext_lld.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel
-                       - Copyright (C) 2013 mike brown
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/ext_lld.h
- * @brief   LPC11xx EXT subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_H_
-#define _EXT_LLD_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Available number of EXT channels.
- */
-#define EXT_MAX_CHANNELS    12
-
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT0 driver enable switch.
- * @details If set to @p TRUE the support for EXT0 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_EXT_USE_EXT0) || defined(__DOXYGEN__)
-#define LPC11xx_EXT_USE_EXT0              FALSE
-#endif
-
-/**
- * @brief   EXT1 driver enable switch.
- * @details If set to @p TRUE the support for EXT1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_EXT_USE_EXT1) || defined(__DOXYGEN__)
-#define LPC11xx_EXT_USE_EXT1              FALSE
-#endif
-
-/**
- * @brief   EXT2 driver enable switch.
- * @details If set to @p TRUE the support for EXT2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_EXT_USE_EXT2) || defined(__DOXYGEN__)
-#define LPC11xx_EXT_USE_EXT2              FALSE
-#endif
-
-/**
- * @brief   EXT3 driver enable switch.
- * @details If set to @p TRUE the support for EXT3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_EXT_USE_EXT3) || defined(__DOXYGEN__)
-#define LPC11xx_EXT_USE_EXT3              FALSE
-#endif
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief   Type of an EXT generic notification callback.
- *
- * @param[in] extp      pointer to the @p EXPDriver object triggering the
- *                      callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief   Channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel mode.
-   */
-  uint8_t               mode;
-
-  /**
-   * @brief Channel callback.
-   */
-  extcallback_t         cb;
-} EXTChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief Channel configurations.
-   */
-  EXTChannelConfig      channels[EXT_MAX_CHANNELS];
-  /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief   Structure representing an EXT driver.
- */
-struct EXTDriver {
-  /**
-   * @brief Driver state.
-   */
-  extstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const EXTConfig           *config;
-  /* End of the mandatory fields.*/
-  LPC_GPIO_TypeDef          *gpio;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC11xx_EXT_USE_EXT0 || !defined(__DOXYGEN__)
-extern EXTDriver EXTD0;
-#endif
-
-#if LPC11xx_EXT_USE_EXT1 || !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#if LPC11xx_EXT_USE_EXT2 || !defined(__DOXYGEN__)
-extern EXTDriver EXTD2;
-#endif
-
-#if LPC11xx_EXT_USE_EXT3 || !defined(__DOXYGEN__)
-extern EXTDriver EXTD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_init(void);
-  void ext_lld_start(EXTDriver *extp);
-  void ext_lld_stop(EXTDriver *extp);
-  void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
-  void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/ext_lld_isr.c b/os/hal/platforms/LPC11xx/ext_lld_isr.c
deleted file mode 100644
index 9d3b92eeb..000000000
--- a/os/hal/platforms/LPC11xx/ext_lld_isr.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/ext_lld_isr.c
- * @brief   LPC11xx EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if LPC11xx_EXT_USE_EXT0 || LPC11xx_EXT_USE_EXT1 || LPC11xx_EXT_USE_EXT2 ||   \
-  LPC11xx_EXT_USE_EXT3 || defined(__DOXYGEN__)
-/**
- * @brief   I2C error handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void ext_lld_serve_interrupt(EXTDriver *extp) {
-  uint32_t port_stat;
-  uint8_t i;
-
-  port_stat = extp->gpio->MIS;   /* Read interrupt status */
-  extp->gpio->IC = port_stat;    /* Clear interrupt flags */
-
-  for (i = 0; i < EXT_MAX_CHANNELS; i++) {
-    if (port_stat & 0x01) {
-      extp->config->channels[i].cb(extp, i);
-    }
-    port_stat  = port_stat >> 1;
-  }
-}
-#endif
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PIO0 interrupt handler.
- *
- * @isr
- */
-#if LPC11xx_EXT_USE_EXT0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(VectorBC) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_serve_interrupt(&EXTD0);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC11xx_EXT_USE_EXT1 || defined(__DOXYGEN__)
-/**
- * @brief   PIO1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorB8) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_serve_interrupt(&EXTD1);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC11xx_EXT_USE_EXT2 || defined(__DOXYGEN__)
-/**
- * @brief   PIO2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorB4) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_serve_interrupt(&EXTD2);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC11xx_EXT_USE_EXT3 || defined(__DOXYGEN__)
-/**
- * @brief   PIO_3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorB0) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_serve_interrupt(&EXTD3);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(extirq_t irqn) {
-
-  uint32_t pmask;
-
-  switch (irqn) {
-  case EXTI0_IRQ:
-    pmask = LPC11xx_EXT_EXTI0_IRQ_PRIORITY;
-    break;
-  case EXTI1_IRQ:
-    pmask = LPC11xx_EXT_EXTI1_IRQ_PRIORITY;
-    break;
-  case EXTI2_IRQ:
-    pmask = LPC11xx_EXT_EXTI2_IRQ_PRIORITY;
-    break;
-  case EXTI3_IRQ:
-    pmask = LPC11xx_EXT_EXTI3_IRQ_PRIORITY;
-    break;
-  }
-  nvicEnableVector(EINT0_IRQn - irqn, CORTEX_PRIORITY_MASK(pmask));
-
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(extirq_t irqn) {
-
-  nvicDisableVector(EINT0_IRQn - irqn);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/ext_lld_isr.h b/os/hal/platforms/LPC11xx/ext_lld_isr.h
deleted file mode 100644
index 442d109da..000000000
--- a/os/hal/platforms/LPC11xx/ext_lld_isr.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC11xx EXT driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/ext_lld_isr.h
- * @brief   LPC11xx EXT subsystem low level driver ISR header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_ISR_H_
-#define _EXT_LLD_ISR_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define EXTI0_IRQ           0
-#define EXTI1_IRQ           1
-#define EXTI2_IRQ           2
-#define EXTI3_IRQ           3
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   EXTI0 interrupt priority level setting.
- */
-#if !defined(LPC11xx_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_EXT_EXTI0_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI1 interrupt priority level setting.
- */
-#if !defined(LPC11xx_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_EXT_EXTI1_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI2 interrupt priority level setting.
- */
-#if !defined(LPC11xx_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_EXT_EXTI2_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI3 interrupt priority level setting.
- */
-#if !defined(LPC11xx_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_EXT_EXTI3_IRQ_PRIORITY      3
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT irq port identifier.
- */
-typedef uint32_t extirq_t;
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_exti_irq_enable(extirq_t irqn);
-  void ext_lld_exti_irq_disable(extirq_t irqn);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_ISR_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/gpt_lld.c b/os/hal/platforms/LPC11xx/gpt_lld.c
deleted file mode 100644
index 82a51f50a..000000000
--- a/os/hal/platforms/LPC11xx/gpt_lld.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/gpt_lld.c
- * @brief   LPC11xx GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver identifier.
- * @note    The driver GPT1 allocates the complex timer CT16B0 when enabled.
- */
-#if LPC11xx_GPT_USE_CT16B0 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief   GPT2 driver identifier.
- * @note    The driver GPT2 allocates the timer CT16B1 when enabled.
- */
-#if LPC11xx_GPT_USE_CT16B1 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief   GPT3 driver identifier.
- * @note    The driver GPT3 allocates the timer CT32B0 when enabled.
- */
-#if LPC11xx_GPT_USE_CT32B0 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/**
- * @brief   GPT4 driver identifier.
- * @note    The driver GPT4 allocates the timer CT32B1 when enabled.
- */
-#if LPC11xx_GPT_USE_CT32B1 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
-  gptp->tmr->IR = 1;                        /* Clear interrupt on match MR0.*/
-  if (gptp->state == GPT_ONESHOT) {
-    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
-    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
-  }
-  gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC11xx_GPT_USE_CT16B0
-/**
- * @brief   CT16B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector80) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC11xx_GPT_USE_CT16B0 */
-
-#if LPC11xx_GPT_USE_CT16B1
-/**
- * @brief   CT16B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector84) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC11xx_GPT_USE_CT16B0 */
-
-#if LPC11xx_GPT_USE_CT32B0
-/**
- * @brief   CT32B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector88) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC11xx_GPT_USE_CT32B0 */
-
-#if LPC11xx_GPT_USE_CT32B1
-/**
- * @brief   CT32B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector8C) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC11xx_GPT_USE_CT32B1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if LPC11xx_GPT_USE_CT16B0
-  /* Driver initialization.*/
-  GPTD1.tmr = LPC_TMR16B0;
-  gptObjectInit(&GPTD1);
-#endif
-
-#if LPC11xx_GPT_USE_CT16B1
-  /* Driver initialization.*/
-  GPTD2.tmr = LPC_TMR16B1;
-  gptObjectInit(&GPTD2);
-#endif
-
-#if LPC11xx_GPT_USE_CT32B0
-  /* Driver initialization.*/
-  GPTD3.tmr = LPC_TMR32B0;
-  gptObjectInit(&GPTD3);
-#endif
-
-#if LPC11xx_GPT_USE_CT32B1
-  /* Driver initialization.*/
-  GPTD4.tmr = LPC_TMR32B1;
-  gptObjectInit(&GPTD4);
-#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-  uint32_t pr;
-
-  if (gptp->state == GPT_STOP) {
-    /* Clock activation.*/
-#if LPC11xx_GPT_USE_CT16B0
-    if (&GPTD1 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7);
-      nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC11xx_GPT_USE_CT16B1
-    if (&GPTD2 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
-      nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3));
-    }
-#endif
-#if LPC11xx_GPT_USE_CT32B0
-    if (&GPTD3 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9);
-      nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC11xx_GPT_USE_CT32B1
-    if (&GPTD4 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
-      nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-  }
-
-  /* Prescaler value calculation.*/
-  pr = (uint16_t)((LPC11xx_SYSCLK / gptp->config->frequency) - 1);
-  chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC11xx_SYSCLK,
-              "gpt_lld_start(), #1", "invalid frequency");
-
-  /* Timer configuration.*/
-  gptp->tmr->PR  = pr;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
-  if (gptp->state == GPT_READY) {
-    gptp->tmr->MCR = 0;
-    gptp->tmr->TCR = 0;
-
-#if LPC11xx_GPT_USE_CT16B0
-    if (&GPTD1 == gptp) {
-      nvicDisableVector(TIMER_16_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
-    }
-#endif
-#if LPC11xx_GPT_USE_CT16B1
-    if (&GPTD2 == gptp) {
-      nvicDisableVector(TIMER_16_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
-    }
-#endif
-#if LPC11xx_GPT_USE_CT32B0
-    if (&GPTD3 == gptp) {
-      nvicDisableVector(TIMER_32_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
-    }
-#endif
-#if LPC11xx_GPT_USE_CT32B1
-    if (&GPTD4 == gptp) {
-      nvicDisableVector(TIMER_32_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 3;                       /* IRQ and clr TC on match MR0. */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 4;                       /* Stop TC on match MR0.        */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-  while (gptp->tmr->TCR & 1)
-    ;
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/gpt_lld.h b/os/hal/platforms/LPC11xx/gpt_lld.h
deleted file mode 100644
index cdf7ddd0a..000000000
--- a/os/hal/platforms/LPC11xx/gpt_lld.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/gpt_lld.h
- * @brief   LPC11xx GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver enable switch.
- * @details If set to @p TRUE the support for GPT1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_GPT_USE_CT16B0) || defined(__DOXYGEN__)
-#define LPC11xx_GPT_USE_CT16B0              TRUE
-#endif
-
-/**
- * @brief   GPT2 driver enable switch.
- * @details If set to @p TRUE the support for GPT2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_GPT_USE_CT16B1) || defined(__DOXYGEN__)
-#define LPC11xx_GPT_USE_CT16B1              TRUE
-#endif
-
-/**
- * @brief   GPT3 driver enable switch.
- * @details If set to @p TRUE the support for GPT3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_GPT_USE_CT32B0) || defined(__DOXYGEN__)
-#define LPC11xx_GPT_USE_CT32B0              TRUE
-#endif
-
-/**
- * @brief   GPT4 driver enable switch.
- * @details If set to @p TRUE the support for GPT4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_GPT_USE_CT32B1) || defined(__DOXYGEN__)
-#define LPC11xx_GPT_USE_CT32B1              TRUE
-#endif
-
-/**
- * @brief   GPT1 interrupt priority level setting.
- */
-#if !defined(LPC11xx_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_GPT_CT16B0_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT2 interrupt priority level setting.
- */
-#if !defined(LPC11xx_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_GPT_CT16B1_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT3 interrupt priority level setting.
- */
-#if !defined(LPC11xx_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_GPT_CT32B0_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT4 interrupt priority level setting.
- */
-#if !defined(LPC11xx_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_GPT_CT32B1_IRQ_PRIORITY     2
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !LPC11xx_GPT_USE_CT16B0 && !LPC11xx_GPT_USE_CT16B1 &&                   \
-    !LPC11xx_GPT_USE_CT32B0 && !LPC11xx_GPT_USE_CT32B1
-#error "GPT driver activated but no CT peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the CTxxBy registers block.
-   */
-  LPC_TMR_TypeDef           *tmr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC11xx_GPT_USE_CT16B0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if LPC11xx_GPT_USE_CT16B1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if LPC11xx_GPT_USE_CT32B0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#if LPC11xx_GPT_USE_CT32B1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/hal_lld.c b/os/hal/platforms/LPC11xx/hal_lld.c
deleted file mode 100644
index af14d406a..000000000
--- a/os/hal/platforms/LPC11xx/hal_lld.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/hal_lld.c
- * @brief   LPC11xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/**
- * @brief   Register missing in NXP header file.
- */
-#define FLASHCFG (*((volatile uint32_t *)0x4003C010))
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* SysTick initialization using the system clock.*/
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
-  SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
- * @brief   LPC11xx clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void lpc111x_clock_init(void) {
-  unsigned i;
-
-  /* Flash wait states setting, the code takes care to not touch TBD bits.*/
-  FLASHCFG = (FLASHCFG & ~3) | LPC11xx_FLASHCFG_FLASHTIM;
-
-  /* System oscillator initialization if required.*/
-#if LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-#if LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC
-  LPC_SYSCON->SYSOSCCTRL = LPC11xx_SYSOSCCTRL;
-  LPC_SYSCON->PDRUNCFG &= ~(1 << 5);            /* System oscillator ON.    */
-  for (i = 0; i < 200; i++)
-    __NOP();                                    /* Stabilization delay.     */
-#endif /* LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */
-
-  /* PLL initialization if required.*/
-  LPC_SYSCON->SYSPLLCLKSEL = LPC11xx_PLLCLK_SOURCE;
-  LPC_SYSCON->SYSPLLCLKUEN = 1;                 /* Really required?         */
-  LPC_SYSCON->SYSPLLCLKUEN = 0;
-  LPC_SYSCON->SYSPLLCLKUEN = 1;
-  LPC_SYSCON->SYSPLLCTRL = LPC11xx_SYSPLLCTRL_MSEL | LPC11xx_SYSPLLCTRL_PSEL;
-  LPC_SYSCON->PDRUNCFG &= ~(1 << 7);            /* System PLL ON.           */
-  while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0)     /* Wait PLL lock.           */
-    ;
-#endif /* LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */
-
-  /* Main clock source selection.*/
-  LPC_SYSCON->MAINCLKSEL = LPC11xx_MAINCLK_SOURCE;
-  LPC_SYSCON->MAINCLKUEN = 1;                   /* Really required?         */
-  LPC_SYSCON->MAINCLKUEN = 0;
-  LPC_SYSCON->MAINCLKUEN = 1;
-  while ((LPC_SYSCON->MAINCLKUEN & 1) == 0)     /* Wait switch completion.  */
-    ;
-
-  /* ABH divider initialization, peripheral clocks are initially disabled,
-     the various device drivers will handle their own setup except GPIO and
-     IOCON that are left enabled.*/
-  LPC_SYSCON->SYSAHBCLKDIV = LPC11xx_SYSABHCLK_DIV;
-  LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F;
-
-  /* Memory remapping, vectors always in ROM.*/
-  LPC_SYSCON->SYSMEMREMAP = 2;
-}
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/hal_lld.h b/os/hal/platforms/LPC11xx/hal_lld.h
deleted file mode 100644
index ee778dd47..000000000
--- a/os/hal/platforms/LPC11xx/hal_lld.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/hal_lld.h
- * @brief   HAL subsystem low level driver header template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "LPC11xx.h"
-#include "nvic.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME           "LPC11xx"
-
-#define IRCOSCCLK               12000000    /**< High speed internal clock. */
-#define WDGOSCCLK               1600000     /**< Watchdog internal clock.   */
-
-#define SYSPLLCLKSEL_IRCOSC     0           /**< Internal RC oscillator
-                                                 clock source.              */
-#define SYSPLLCLKSEL_SYSOSC     1           /**< System oscillator clock
-                                                 source.                    */
-
-#define SYSMAINCLKSEL_IRCOSC    0           /**< Clock source is IRC.       */
-#define SYSMAINCLKSEL_PLLIN     1           /**< Clock source is PLLIN.     */
-#define SYSMAINCLKSEL_WDGOSC    2           /**< Clock source is WDGOSC.    */
-#define SYSMAINCLKSEL_PLLOUT    3           /**< Clock source is PLLOUT.    */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   System PLL clock source.
- */
-#if !defined(LPC11xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC11xx_PLLCLK_SOURCE               SYSPLLCLKSEL_SYSOSC
-#endif
-
-/**
- * @brief   System PLL multiplier.
- * @note    The value must be in the 1..32 range and the final frequency
- *          must not exceed the CCO ratings.
- */
-#if !defined(LPC11xx_SYSPLL_MUL) || defined(__DOXYGEN__)
-#define LPC11xx_SYSPLL_MUL                  4
-#endif
-
-/**
- * @brief   System PLL divider.
- * @note    The value must be chosen between (2, 4, 8, 16).
- */
-#if !defined(LPC11xx_SYSPLL_DIV) || defined(__DOXYGEN__)
-#define LPC11xx_SYSPLL_DIV                  4
-#endif
-
-/**
- * @brief   System main clock source.
- */
-#if !defined(LPC11xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC11xx_MAINCLK_SOURCE              SYSMAINCLKSEL_PLLOUT
-#endif
-
-/**
- * @brief   AHB clock divider.
- * @note    The value must be chosen between (1...255).
- */
-#if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__)
-#define LPC11xx_SYSABHCLK_DIV               1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Calculated SYSOSCCTRL setting.
- */
-#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__)
-#define LPC11xx_SYSOSCCTRL      0
-#else
-#define LPC11xx_SYSOSCCTRL      1
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
-#define LPC11xx_SYSPLLCLKIN     SYSOSCCLK
-#elif LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC
-#define LPC11xx_SYSPLLCLKIN     IRCOSCCLK
-#else
-#error "invalid LPC11xx_PLLCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   MSEL mask in SYSPLLCTRL register.
- */
-#if (LPC11xx_SYSPLL_MUL >= 1) && (LPC11xx_SYSPLL_MUL <= 32) ||              \
-    defined(__DOXYGEN__)
-#define LPC11xx_SYSPLLCTRL_MSEL (LPC11xx_SYSPLL_MUL - 1)
-#else
-#error "LPC11xx_SYSPLL_MUL out of range (1...32)"
-#endif
-
-/**
- * @brief   PSEL mask in SYSPLLCTRL register.
- */
-#if (LPC11xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
-#define LPC11xx_SYSPLLCTRL_PSEL (0 << 5)
-#elif LPC11xx_SYSPLL_DIV == 4
-#define LPC11xx_SYSPLLCTRL_PSEL (1 << 5)
-#elif LPC11xx_SYSPLL_DIV == 8
-#define LPC11xx_SYSPLLCTRL_PSEL (2 << 5)
-#elif LPC11xx_SYSPLL_DIV == 16
-#define LPC11xx_SYSPLLCTRL_PSEL (3 << 5)
-#else
-#error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)"
-#endif
-
-/**
- * @brief   CCP frequency.
- */
-#define  LPC11xx_SYSPLLCCO   (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL *    \
-                              LPC11xx_SYSPLL_DIV)
-
-#if (LPC11xx_SYSPLLCCO < 156000000) || (LPC11xx_SYSPLLCCO > 320000000)
-#error "CCO frequency out of the acceptable range (156...320)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define  LPC11xx_SYSPLLCLKOUT   (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV)
-
-#if (LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__)
-#define LPC11xx_MAINCLK     IRCOSCCLK
-#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
-#define LPC11xx_MAINCLK     LPC11xx_SYSPLLCLKIN
-#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
-#define LPC11xx_MAINCLK     WDGOSCCLK
-#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-#define LPC11xx_MAINCLK     LPC11xx_SYSPLLCLKOUT
-#else
-#error "invalid LPC11xx_MAINCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   AHB clock.
- */
-#define  LPC11xx_SYSCLK     (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV)
-#if LPC11xx_SYSCLK > 50000000
-#error "AHB clock frequency out of the acceptable range (50MHz max)"
-#endif
-
-/**
- * @brief   Flash wait states.
- */
-#if (LPC11xx_SYSCLK <= 20000000) || defined(__DOXYGEN__)
-#define LPC11xx_FLASHCFG_FLASHTIM   0
-#elif LPC11xx_SYSCLK <= 40000000
-#define LPC11xx_FLASHCFG_FLASHTIM   1
-#else
-#define LPC11xx_FLASHCFG_FLASHTIM   2
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void lpc111x_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/i2c_lld.c b/os/hal/platforms/LPC11xx/i2c_lld.c
deleted file mode 100644
index c68f11460..000000000
--- a/os/hal/platforms/LPC11xx/i2c_lld.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC11xx I2C driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-
-/**
- * @file    LPC11xx/i2c_lld.h
- * @brief   LPC11xx I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief I2C1 driver identifier.*/
-I2CDriver I2CD1;
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Wakes up the waiting thread.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] msg       wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((i2cp)->thread != NULL) {                                             \
-    Thread *tp = (i2cp)->thread;                                            \
-    (i2cp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = (msg);                                                 \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
-}
-
-/**
- * @brief   Handling of stalled I2C transactions.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_safety_timeout(void *p) {
-  I2CDriver *i2cp = (I2CDriver *)p;
-
-  chSysLockFromIsr();
-  if (i2cp->thread) {
-    Thread *tp = i2cp->thread;
-    i2cp->thread = NULL;
-    tp->p_u.rdymsg = RDY_TIMEOUT;
-    chSchReadyI(tp);
-  }
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   I2C error handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t status) {
-  i2cflags_t error = 0;
-
-  switch (status) {
-    case I2C_STATE_ARB_LOST:
-      error = I2CD_ARBITRATION_LOST;
-      break;
-    case I2C_STATE_BUS_ERROR:
-      error = I2CD_BUS_ERROR;
-      break;
-    case I2C_STATE_MS_SLAR_NACK:
-    case I2C_STATE_MS_TDAT_NACK:
-    case I2C_STATE_MS_SLAW_NACK:
-      error = I2CD_ACK_FAILURE ;
-      break;
-  }
-
-  /* If some error has been identified then sends wakes the waiting thread.*/
-  i2cp->errors = error;
-  wakeup_isr(i2cp, RDY_RESET);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-/**
- * @brief   I2C event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(Vector7C) {
-  uint32_t status;
-
-  CH_IRQ_PROLOGUE();
-  status = LPC_I2C->STAT;
-  switch(status) {
-    case I2C_STATE_MS_START:    /*  A START condition has been transmitted. */
-      if (I2CD1.txbytes > 0) {
-        LPC_I2C->DAT = I2CD1.addr;                  /* Write slave address with WR bit. */
-      }
-      else {
-        LPC_I2C->DAT = I2CD1.addr | I2C_RD_BIT;     /* Write slave address with RD bit. */
-      }
-
-      LPC_I2C->CONCLR = I2C_CONCLR_STAC | I2C_CONCLR_SIC;   /* Clear START and SI bit. */
-      break;
-
-    case I2C_STATE_MS_SLAR_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */
-    case I2C_STATE_MS_TDAT_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */
-    case I2C_STATE_MS_SLAW_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */
-      LPC_I2C->CONSET = I2C_CONSET_STO;             /* Set STOP bit. */
-      LPC_I2C->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      i2c_lld_serve_error_interrupt(&I2CD1, status);
-      break;
-
-    case I2C_STATE_MS_SLAW_ACK: /* SLA + W has been transmitted, ACK has been received. */
-    case I2C_STATE_MS_TDAT_ACK: /* Data byte has been transmitted, ACK has been received. */
-      if (I2CD1.txbytes > 0) {
-        LPC_I2C->DAT = *I2CD1.txbuf++;               /* Write data. */
-        I2CD1.txbytes--;
-      }
-      else {
-        if (I2CD1.rxbytes > 0) {
-          LPC_I2C->CONSET = I2C_CONSET_STO | I2C_CONSET_STA; /* Set START and STOP bit. */
-        }                                                    /* STOP bit will be transmit, then START bit. */
-        else {
-          LPC_I2C->CONSET = I2C_CONSET_STO;         /* Set STOP bit. */
-          wakeup_isr(&I2CD1, RDY_OK);
-        }
-      }
-      LPC_I2C->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      break;
-
-    case I2C_STATE_MS_SLAR_ACK: /* SLA + R has been transmitted, ACK has been received. */
-    case I2C_STATE_MS_RDAT_ACK: /* Data byte has been received, ACK has been returned. */
-      if (status == I2C_STATE_MS_RDAT_ACK) {
-        *I2CD1.rxbuf++ = LPC_I2C->DAT;                /* Read data */
-        I2CD1.rxbytes--;
-      }
-      if (I2CD1.rxbytes == 1) {
-        LPC_I2C->CONCLR = I2C_CONCLR_SIC | I2C_CONCLR_AAC; /* Clear SI and ACK bit. */
-      }
-      else {
-        LPC_I2C->CONSET = I2C_CONSET_AA;            /* Set ACK bit. */
-        LPC_I2C->CONCLR = I2C_CONCLR_SIC;           /* Clear SI bit. */
-      }
-      break;
-
-    case I2C_STATE_MS_RDAT_NACK: /* Data byte has been received, NOT ACK has been returned. */
-      *I2CD1.rxbuf++ = LPC_I2C->DAT;                /* Read data. */
-      I2CD1.rxbytes--;
-      LPC_I2C->CONSET = I2C_CONSET_STO;             /* Set STOP bit. */
-      LPC_I2C->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      wakeup_isr(&I2CD1, RDY_OK);
-      break;
-
-    case I2C_STATE_BUS_ERROR: /* Bus error. */
-    case I2C_STATE_ARB_LOST:  /* Arbitration lost. */
-      LPC_I2C->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      i2c_lld_serve_error_interrupt(&I2CD1, status);
-      break;
-
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-  i2cObjectInit(&I2CD1);
-  I2CD1.thread = NULL;
-  I2CD1.i2c    = LPC_I2C;
-
-  LPC_IOCON->PIO0_4 = 0x01;  /* Set I2C SCL pin function */
-  LPC_IOCON->PIO0_5 = 0x01;  /* Set I2C SDA pin function */
-}
-
-/**
- * @brief   Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-  uint32_t i2cscl;
-  uint32_t mulh, mull, div;
-  LPC_I2C_TypeDef *dp = i2cp->i2c;
-
-  /* Make sure I2C peripheral is disabled */
-  dp->CONCLR = I2C_CONCLR_ENC;
-
-  /* If in stopped state then enables the I2C clock. */
-  if (i2cp->state == I2C_STOP) {
-
-  if (&I2CD1 == i2cp) {
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5); /* Enable clock. */
-    LPC_SYSCON->PRESETCTRL &= ~(1 << 1);   /* Reset I2C peripheral.*/
-    __NOP();
-    LPC_SYSCON->PRESETCTRL |= (1 << 1);
-    nvicEnableVector(I2C_IRQn,
-          CORTEX_PRIORITY_MASK(LPC11xx_I2C_IRQ_PRIORITY));
-  }
-
-  }
-
-  /* Setup I2C clock parameters.*/
-  i2cscl = (LPC11xx_SYSCLK/(i2cp->config->clock_timing));
-  if (i2cp->config->mode == I2C_FAST_MODE) {
-    div = 19;
-    mull = 13;
-    mulh = 6;
-  } else if (i2cp->config->mode == I2C_FAST_MODE_PLUS) {
-    div = 3;
-    mull = 2;
-    mulh = 1;
-  } else { /* i2cp->config->mode == I2C_STANDARD_MODE */
-    div = 2;
-    mull = 1;
-    mulh = 1;
-  }
-
-  dp->SCLH = (mulh * i2cscl) / div;
-  dp->SCLL = (mull * i2cscl) / div;
-
-  /* Enable I2C.*/
-  dp->CONSET |= I2C_CONSET_EN;
-}
-
-/**
- * @brief   Deactivates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
-  /* If not in stopped state then disables the I2C clock.*/
-  if (i2cp->state != I2C_STOP) {
-
-    /* I2C disable.*/
-    i2cp->i2c->CONCLR = I2C_CONCLR_ENC;
-
-    if (&I2CD1 == i2cp) {
-      nvicDisableVector(I2C_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 5);
-    }
-  }
-}
-
-/**
- * @brief   Receives data via the I2C bus as master.
- * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
- *          hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                     uint8_t *rxbuf, size_t rxbytes,
-                                     systime_t timeout) {
-  LPC_I2C_TypeDef *dp = i2cp->i2c;
-  VirtualTimer vt;
-
-  i2cp->addr = addr << 1;
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Initializes driver fields */
-  i2cp->errors = 0;
-  i2cp->rxbuf = rxbuf;
-  i2cp->rxbytes = rxbytes;
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Starts the operation.*/
-  dp->CONSET = I2C_CONSET_STA;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief   Transmits data via the I2C bus as master.
- * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
- *          This is hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[in] txbuf     pointer to the transmit buffer
- * @param[in] txbytes   number of bytes to be transmitted
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                      const uint8_t *txbuf, size_t txbytes,
-                                      uint8_t *rxbuf, size_t rxbytes,
-                                      systime_t timeout) {
-  LPC_I2C_TypeDef *dp = i2cp->i2c;
-  VirtualTimer vt;
-
-  i2cp->addr = addr << 1;
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Initializes driver fields */
-  i2cp->errors = 0;
-  i2cp->txbuf = txbuf;
-  i2cp->txbytes = txbytes;
-  i2cp->rxbuf = rxbuf;
-  i2cp->rxbytes = rxbytes;
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Starts the operation.*/
-  dp->CONSET = I2C_CONSET_STA;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/i2c_lld.h b/os/hal/platforms/LPC11xx/i2c_lld.h
deleted file mode 100644
index b908ba6e4..000000000
--- a/os/hal/platforms/LPC11xx/i2c_lld.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC11xx I2C driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    LPC11xx/i2c_lld.h
- * @brief   LPC11xx I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define I2C_CONSET_AA               0x04  /* Assert acknowledge flag. */
-#define I2C_CONSET_SI               0x08  /* I2C interrupt flag. */
-#define I2C_CONSET_STO              0x10  /* STOP flag. */
-#define I2C_CONSET_STA              0x20  /* START flag. */
-#define I2C_CONSET_EN               0x40  /* I2C interface enable. */
-
-#define I2C_CONCLR_AAC              0x04  /* Assert acknowledge Clear bit. */
-#define I2C_CONCLR_SIC              0x08  /* I2C interrupt Clear bit. */
-#define I2C_CONCLR_STAC             0x20  /* START flag Clear bit. */
-#define I2C_CONCLR_ENC              0x40  /* I2C interface Disable bit. */
-
-#define I2C_WR_BIT                  0x00
-#define I2C_RD_BIT                  0x01
-
-#define I2C_STATE_MS_START          0x08
-#define I2C_STATE_MS_RSTART         0x10
-#define I2C_STATE_MS_SLAW_ACK       0x18
-#define I2C_STATE_MS_SLAW_NACK      0x20
-#define I2C_STATE_MS_TDAT_ACK       0x28
-#define I2C_STATE_MS_TDAT_NACK      0x30
-#define I2C_STATE_ARB_LOST          0x38
-
-#define I2C_STATE_MS_SLAR_ACK       0x40
-#define I2C_STATE_MS_SLAR_NACK      0x48
-#define I2C_STATE_MS_RDAT_ACK       0x50
-#define I2C_STATE_MS_RDAT_NACK      0x58
-
-#define I2C_STATE_BUS_ERROR         0x00
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-/**
- * @name    Configuration options
- * @{
- */
-
-/**
- * @brief   I2C1 interrupt priority level setting.
- */
-#if !defined(LPC11xx_I2C_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_I2C_IRQ_PRIORITY     3
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing I2C address.
- */
-typedef uint16_t i2caddr_t;
-
-/**
- * @brief   I2C Driver condition flags type.
- */
-typedef uint32_t i2cflags_t;
-/**
- * @brief   Supported modes for the I2C bus.
- */
-typedef enum {
-  I2C_STANDARD_MODE = 1,
-  I2C_FAST_MODE = 2,
-  I2C_FAST_MODE_PLUS = 3,
-} i2cmode_t;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
-  i2cmode_t       mode;             /**< @brief Specifies the I2C mode.        */
-  uint32_t        clock_timing;     /**< @brief Specifies the clock timing     */
-} I2CConfig;
-
-/**
- * @brief   Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver {
-  /**
-   * @brief   Driver state.
-   */
-  i2cstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const I2CConfig           *config;
-  /**
-   * @brief   Error flags.
-   */
-  i2cflags_t                errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
-  I2C_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Thread waiting for I/O completion.
-   */
-  Thread                    *thread;
-  /**
-   * @brief     Current slave address without R/W bit.
-   */
-  i2caddr_t                 addr;
-  /**
-   * @brief     Pointer to the transmit buffer.
-   */
-  const uint8_t             *txbuf;
-  /**
-    * @brief    Number of bytes to transmit.
-    */
-  size_t                    txbytes;
-  /**
-    * @brief     Pointer to the receive buffer.
-    */
-  uint8_t                   *rxbuf;
-  /**
-      * @brief    Number of bytes to receive.
-      */
-  size_t                    rxbytes;
-  /**
-   * @brief     Pointer to the I2C registers block.
-   */
-  LPC_I2C_TypeDef           *i2c;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Get errors from I2C driver.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern I2CDriver I2CD1;
-#endif
-
-#endif /* !defined(__DOXYGEN__) */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void i2c_lld_init(void);
-  void i2c_lld_start(I2CDriver *i2cp);
-  void i2c_lld_stop(I2CDriver *i2cp);
-  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                        const uint8_t *txbuf, size_t txbytes,
-                                        uint8_t *rxbuf, size_t rxbytes,
-                                        systime_t timeout);
-  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                       uint8_t *rxbuf, size_t rxbytes,
-                                       systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _I2C_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/pal_lld.c b/os/hal/platforms/LPC11xx/pal_lld.c
deleted file mode 100644
index 2fc1201f0..000000000
--- a/os/hal/platforms/LPC11xx/pal_lld.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/pal_lld.c
- * @brief   LPC11xx GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-/**
- * @brief   LPC11xx I/O ports configuration.
- * @details GPIO unit registers initialization.
- *
- * @param[in] config    the LPC11xx ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  LPC_GPIO0->DIR = config->P0.dir;
-  LPC_GPIO1->DIR = config->P1.dir;
-  LPC_GPIO2->DIR = config->P2.dir;
-  LPC_GPIO3->DIR = config->P3.dir;
-  LPC_GPIO0->DATA = config->P0.data;
-  LPC_GPIO1->DATA = config->P1.data;
-  LPC_GPIO2->DATA = config->P2.data;
-  LPC_GPIO3->DATA = config->P3.data;
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    This function does not alter the @p PINSELx registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    port->DIR &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    palSetPort(port, PAL_WHOLE_PORT);
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->DIR |=  mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/pal_lld.h b/os/hal/platforms/LPC11xx/pal_lld.h
deleted file mode 100644
index 82a1d53f9..000000000
--- a/os/hal/platforms/LPC11xx/pal_lld.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/pal_lld.h
- * @brief   LPC11xx GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port setup info.
- */
-typedef struct {
-  /** Initial value for FIO_PIN register.*/
-  uint32_t      data;
-  /** Initial value for FIO_DIR register.*/
-  uint32_t      dir;
-} lpc111x_gpio_setup_t;
-
-/**
- * @brief   GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    The @p IOCON block is not configured, initially all pins have
- *          enabled pullups and are programmed as GPIO. It is responsibility
- *          of the various drivers to reprogram the pins in the proper mode.
- *          Pins that are not handled by any driver may be programmed in
- *          @p board.c.
- */
-typedef struct {
-  /** @brief GPIO 0 setup data.*/
-  lpc111x_gpio_setup_t   P0;
-  /** @brief GPIO 1 setup data.*/
-  lpc111x_gpio_setup_t   P1;
-  /** @brief GPIO 2 setup data.*/
-  lpc111x_gpio_setup_t   P2;
-  /** @brief GPIO 3 setup data.*/
-  lpc111x_gpio_setup_t   P3;
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef LPC_GPIO_TypeDef *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO0 port identifier.
- */
-#define IOPORT1         LPC_GPIO0
-#define GPIO0           LPC_GPIO0
-
-/**
- * @brief   GPIO1 port identifier.
- */
-#define IOPORT2         LPC_GPIO1
-#define GPIO1           LPC_GPIO1
-
-/**
- * @brief   GPIO2 port identifier.
- */
-#define IOPORT3         LPC_GPIO2
-#define GPIO2           LPC_GPIO2
-
-/**
- * @brief   GPIO3 port identifier.
- */
-#define IOPORT4         LPC_GPIO3
-#define GPIO3           LPC_GPIO3
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->DATA)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->DATA)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->DATA = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF)
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0)
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset)                               \
-  ((port)->MASKED_ACCESS[(mask) << (offset)])
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                        \
-  ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)                                    \
-  ((port)->MASKED_ACCESS[1 << (pad)] = (bit) << (pad))
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-  ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-  ((port)->MASKED_ACCESS[1 << (pad)] = 0)
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/platform.dox b/os/hal/platforms/LPC11xx/platform.dox
deleted file mode 100644
index dab5d1e86..000000000
--- a/os/hal/platforms/LPC11xx/platform.dox
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup LPC11xx LPC11xx Drivers
- * @details This section describes all the supported drivers on the LPC11xx
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup LPC11xx_HAL LPC11xx Initialization Support
- * @details The LPC11xx HAL support is responsible for system initialization.
- *
- * @section lpc11xx_hal_1 Supported HW resources
- * - SYSCON.
- * - Flash.
- * .
- * @section lpc11xx_hal_2 LPC11xx HAL driver implementation features
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash controller initialization.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * .
- * @ingroup LPC11xx
- */
-
-/**
- * @defgroup LPC11xx_GPT LPC11xx GPT Support
- * @details The LPC11xx GPT driver uses the CTxxBy peripherals.
- *
- * @section lpc11xx_gpt_1 Supported HW resources
- * - CT16B0.
- * - CT16B1.
- * - CT32B0.
- * - CT32B1.
- * .
- * @section lpc11xx_gpt_2 LPC11xx GPT driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable CTxxBy interrupts priority level.
- * .
- * @ingroup LPC11xx
- */
-
-/**
- * @defgroup LPC11xx_PAL LPC11xx PAL Support
- * @details The LPC11xx PAL driver uses the GPIO peripherals.
- *
- * @section lpc11xx_pal_1 Supported HW resources
- * - GPIO0.
- * - GPIO1.
- * - GPIO2.
- * - GPIO3.
- * .
- * @section lpc11xx_pal_2 LPC11xx PAL driver implementation features
- * - 12 bits wide ports.
- * - Atomic set/reset functions.
- * - Atomic set+reset function (atomic bus operations).
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section lpc11xx_pal_3 Supported PAL setup modes
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section lpc11xx_pal_4 Suboptimal behavior
- * Some GPIO features are less than optimal:
- * - Pad/port toggling operations are not atomic.
- * - Pull-up and Pull-down resistors cannot be programmed through the PAL
- *   driver and must be programmed separately using the IOCON peripheral.
- * - Reading of the output latch for pads programmed as input is not possible,
- *   the input pin value is returned instead.
- * .
- * @ingroup LPC11xx
- */
-
-/**
- * @defgroup LPC11xx_SERIAL LPC11xx Serial Support
- * @details The LPC11xx Serial driver uses the UART peripheral in a
- *          buffered, interrupt driven, implementation. The serial driver
- *          also takes advantage of the LPC11xx UARTs deep hardware buffers.
- *
- * @section lpc11xx_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - UART.
- * .
- * @section lpc11xx_serial_2 LPC11xx Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Fully interrupt driven.
- * - Programmable priority level.
- * - Takes advantage of the input and output FIFOs.
- * .
- * @ingroup LPC11xx
- */
-
-/**
- * @defgroup LPC11xx_SPI LPC11xx SPI Support
- * @details The SPI driver supports the LPC11xx SSP peripherals in an interrupt
- *          driven implementation.
- * @note    Being the SPI a fast peripheral, much care must be taken to
- *          not saturate the CPU bandwidth with an excessive IRQ rate. The
- *          maximum transfer bit rate is likely limited by the IRQ
- *          handling.
- *
- * @section lpc11xx_spi_1 Supported HW resources
- * - SSP0.
- * - SSP1 (where present).
- * .
- * @section lpc11xx_spi_2 LPC11xx SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SSP can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable interrupt priority levels for each SSP.
- * .
- * @ingroup LPC11xx
- */
diff --git a/os/hal/platforms/LPC11xx/platform.mk b/os/hal/platforms/LPC11xx/platform.mk
deleted file mode 100644
index 61f2a49dd..000000000
--- a/os/hal/platforms/LPC11xx/platform.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of all the LPC11xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC11xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11xx/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11xx/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11xx/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11xx/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11xx/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11xx/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11xx/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC11xx/spi_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC11xx
diff --git a/os/hal/platforms/LPC11xx/pwm_lld.c b/os/hal/platforms/LPC11xx/pwm_lld.c
deleted file mode 100644
index 06de0bbc6..000000000
--- a/os/hal/platforms/LPC11xx/pwm_lld.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC11xx PWM driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/pwm_lld.c
- * @brief   LPC11xx PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PWMD1 driver identifier.
- * @note    The driver PWMD1 allocates the complex timer TIM1 when enabled.
- */
-#if LPC11xx_PWM_USE_CT16B0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief   PWMD2 driver identifier.
- * @note    The driver PWMD2 allocates the timer TIM2 when enabled.
- */
-#if LPC11xx_PWM_USE_CT16B1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief   PWMD3 driver identifier.
- * @note    The driver PWMD3 allocates the timer TIM3 when enabled.
- */
-#if LPC11xx_PWM_USE_CT32B0 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief   PWMD4 driver identifier.
- * @note    The driver PWMD4 allocates the timer TIM4 when enabled.
- */
-#if LPC11xx_PWM_USE_CT32B1 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if LPC11xx_PWM_USE_CT16B0 || LPC11xx_PWM_USE_CT16B1 || LPC11xx_PWM_USE_CT32B0 ||       \
-    LPC11xx_PWM_USE_CT32B1 || defined(__DOXYGEN__)
-/**
- * @brief   Common TIM2...TIM5 IRQ handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
-  uint16_t sr;
-
-  sr  = pwmp->tim->IR;
-  pwmp->tim->IR = sr;
-  if ((sr & IR_MR0INT) != 0)
-    pwmp->config->channels[0].callback(pwmp);
-  if ((sr & IR_MR1INT) != 0)
-    pwmp->config->channels[1].callback(pwmp);
-  if ((sr & IR_MR3INT) != 0)
-    pwmp->config->callback(pwmp);
-}
-#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC11xx_PWM_USE_CT16B0 || defined(__DOXYGEN__)
-/**
- * @brief   CT16B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector80) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#endif /* STM32_PWM_USE_TIM1 */
-
-#if LPC11xx_PWM_USE_CT16B1 || defined(__DOXYGEN__)
-/**
- * @brief   CT16B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector84) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC11xx_PWM_USE_CT16B1 */
-
-#if LPC11xx_PWM_USE_CT32B0 || defined(__DOXYGEN__)
-/**
- * @brief   CT32B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector88) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC11xx_PWM_USE_CT32B0 */
-
-#if LPC11xx_PWM_USE_CT32B1 || defined(__DOXYGEN__)
-/**
- * @brief   CT32B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector8C) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC11xx_PWM_USE_CT32B1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-#if LPC11xx_PWM_USE_CT16B0
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD1);
-  PWMD1.tim = LPC_TMR16B0;
-
-#if LPC11xx_PWM_USE_CT16B0_CH0
-  LPC_IOCON->PIO0_8 = 0xC2;
-#endif
-
-#if LPC11xx_PWM_USE_CT16B0_CH1
-  LPC_IOCON->PIO0_9 = 0xC2;
-#endif
-#endif
-
-#if LPC11xx_PWM_USE_CT16B1
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD2);
-  PWMD2.tim = LPC_TMR16B1;
-
-#if LPC11xx_PWM_USE_CT16B1_CH0
-  LPC_IOCON->PIO1_9 = 0xC1;
-#endif
-
-#if LPC11xx_PWM_USE_CT16B1_CH1
-  LPC_IOCON->PIO1_10 = 0xC2;
-#endif
-#endif
-
-#if LPC11xx_PWM_USE_CT32B0
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD3);
-  PWMD3.tim = LPC_TMR32B0;
-
-#if LPC11xx_PWM_USE_CT32B0_CH0
-  LPC_IOCON->PIO1_6 = 0xC2;
-#endif
-
-#if  LPC11xx_PWM_USE_CT32B0_CH1
-  LPC_IOCON->PIO1_7 = 0xC2;
-#endif
-#endif
-
-#if LPC11xx_PWM_USE_CT32B1
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD4);
-  PWMD4.tim = LPC_TMR32B1;
-
-#if LPC11xx_PWM_USE_CT32B1_CH0
-  LPC_IOCON->R_PIO1_1 = 0xC3;
-#endif
-
-#if LPC11xx_PWM_USE_CT32B1_CH1
-  LPC_IOCON->R_PIO1_2 = 0xC3;
-#endif
-#endif
-}
-
-/**
- * @brief   Configures and activates the PWM peripheral.
- * @note    Starting a driver that is already in the @p PWM_READY state
- *          disables all the active channels.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-  uint32_t pr;
-
-  if (pwmp->state == PWM_STOP) {
-    /* Clock activation and timer reset.*/
-#if LPC11xx_PWM_USE_CT16B0
-    if (&PWMD1 == pwmp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7);
-      nvicEnableVector(TIMER_16_0_IRQn, LPC11xx_PWM_CT16B0_IRQ_PRIORITY);
-    }
-#endif
-#if LPC11xx_PWM_USE_CT16B1
-    if (&PWMD2 == pwmp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
-      nvicEnableVector(TIMER_16_1_IRQn, LPC11xx_PWM_CT16B1_IRQ_PRIORITY);
-    }
-#endif
-#if LPC11xx_PWM_USE_CT32B0
-    if (&PWMD3 == pwmp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9);
-      nvicEnableVector(TIMER_32_0_IRQn, LPC11xx_PWM_CT32B0_IRQ_PRIORITY);
-    }
-#endif
-#if LPC11xx_PWM_USE_CT32B1
-     if (&PWMD4 == pwmp) {
-       LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
-       nvicEnableVector(TIMER_32_1_IRQn, LPC11xx_PWM_CT32B1_IRQ_PRIORITY);
-     }
-#endif
-  }
-  else {
-    /* Driver re-configuration scenario, it must be stopped first.*/
-    pwmp->tim->TCR = 0;
-  }
-
-  /* Output enables and polarities setup.*/
-    if(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW)
-        pwmp->tim->PWMC = (1 << 0);
-
-    if(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW)
-          pwmp->tim->PWMC |= (1 << 1);
-
-    /* Timer configured and started.*/
-    pr = (uint16_t)((LPC11xx_SYSCLK / pwmp->config->frequency) - 1);
-    chDbgAssert(((uint32_t)(pr + 1) * pwmp->config->frequency) == LPC11xx_SYSCLK,
-                    "pwm_lld_start(), #1", "invalid frequency");
-
-    pwmp->tim->TC = 0;
-    pwmp->tim->PR  = pr;
-    pwmp->tim->IR  = 0xFF;
-    pwmp->tim->MCR = MCR_MR3R;              /* Reset on Match3 */
-    pwmp->tim->MR3 = pwmp->config->period;
-
-    if (pwmp->config->callback != NULL)
-        pwmp->tim->MCR |= MCR_MR3I;
-
-    pwmp->tim->TCR = 1;                     /* Timer start */
-}
-
-/**
- * @brief   Deactivates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
-  /* If in ready state then disables the PWM clock.*/
-  if (pwmp->state == PWM_READY) {
-    pwmp->tim->TCR = 0;                     /* Timer disabled.              */
-    pwmp->tim->MCR = 0;                     /* All IRQs disabled.           */
-    pwmp->tim->IR  = 0xFF;                  /* Clear eventual pending IRQs. */
-    pwmp->tim->PWMC = 0;                    /* PWM outputs disable.         */
-
-#if LPC11xx_PWM_USE_CT16B0
-    if (&PWMD1 == pwmp) {
-      nvicDisableVector(TIMER_16_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
-    }
-#endif
-#if LPC11xx_PWM_USE_CT16B1
-    if (&PWMD2 == pwmp) {
-      nvicDisableVector(TIMER_16_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
-    }
-#endif
-#if LPC11xx_PWM_USE_CT32B0
-    if (&PWMD3 == pwmp) {
-      nvicDisableVector(TIMER_32_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
-    }
-#endif
-#if LPC11xx_PWM_USE_CT32B1
-    if (&PWMD4 == pwmp) {
-      nvicDisableVector(TIMER_32_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
-    }
-#endif
-
-  }
-}
-
-/**
- * @brief   Enables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is active using the specified configuration.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t channel,
-                            pwmcnt_t width) {
-
-  pwmp->tim->MCR &= ~(7 << (channel * 3));
-
-  if ( channel == 0)
-    pwmp->tim->MR0 = width;                  /* New duty cycle.      */
-  else
-    pwmp->tim->MR1 = width;                  /* New duty cycle.      */
-  /* If there is a callback defined for the channel then the associated
-     interrupt must be enabled.*/
-  if (pwmp->config->channels[channel].callback != NULL) {
-    pwmp->tim->IR = (1 << channel);         /* Clear interrupt flag*/
-    pwmp->tim->MCR |= (1 << (channel * 3)); /* Set interrupt on selected channel */
-  }
-
-}
-
-/**
- * @brief   Disables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is disabled and its output line returned to the
- *          idle state.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-  if ( channel == 0)
-    pwmp->tim->MR0 = 0;
-  else
-    pwmp->tim->MR1 = 0;
-  pwmp->tim->MCR &= ~(7 << (channel * 3));
-  pwmp->tim->IR = (1 << channel);
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/pwm_lld.h b/os/hal/platforms/LPC11xx/pwm_lld.h
deleted file mode 100644
index 2b3a37fd1..000000000
--- a/os/hal/platforms/LPC11xx/pwm_lld.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC11xx PWM driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/pwm_lld.h
- * @brief   LPC11xx PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-#undef PWM_OUTPUT_ACTIVE_HIGH
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define IR_MR0INT   (1 << 0)
-#define IR_MR1INT   (1 << 1)
-#define IR_MR2INT   (1 << 2)
-#define IR_MR3INT   (1 << 3)
-#define IR_CR0INT   (1 << 4)
-#define IR_CR1INT   (1 << 5)
-#define IR_CR2INT   (1 << 6)
-#define IR_CR3INT   (1 << 7)
-
-#define MCR_MR3I    (1 << 9)
-#define MCR_MR3R    (1 << 10)
-#define MCR_MR3S    (1 << 11)
-/**
- * @brief   Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS                            2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-
-/**
- * @brief   PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_PWM_USE_CT16B0) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT16B0                  FALSE
-#endif
-
-/**
- * @brief   PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_PWM_USE_CT16B1) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT16B1                  FALSE
-#endif
-
-/**
- * @brief   PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_PWM_USE_CT32B0) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT32B0                  FALSE
-#endif
-
-/**
- * @brief   PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_PWM_USE_CT32B1) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT32B1                  FALSE
-#endif
-
-/**
- * @brief   PWMD1 Channel 0 driver enable switch.
- * @details If set to @p TRUE PWMD1 Channel 0 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_PWM_USE_CT16B0_CH0) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT16B0_CH0             FALSE
-#endif
-
-/**
- * @brief   PWMD1 Channel 1 driver enable switch.
- * @details If set to @p TRUE PWMD1 Channel 1 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_PWM_USE_CT16B0_CH1) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT16B0_CH1             FALSE
-#endif
-
-/**
- * @brief   PWMD2 Channel 0 driver enable switch.
- * @details If set to @p TRUE PWMD2 Channel 0 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_PWM_USE_CT16B1_CH0) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT16B1_CH0             FALSE
-#endif
-
-/**
- * @brief   PWMD2 Channel 1 driver enable switch.
- * @details If set to @p TRUE PWMD2 Channel 1 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_PWM_USE_CT16B1_CH1) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT16B1_CH1             FALSE
-#endif
-
-/**
- * @brief   PWMD3 Channel 0 driver enable switch.
- * @details If set to @p TRUE PWMD3 Channel 0 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_PWM_USE_CT32B0_CH0) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT32B0_CH0             FALSE
-#endif
-
-/**
- * @brief   PWMD3 Channel 1 driver enable switch.
- * @details If set to @p TRUE PWMD3 Channel 1 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_PWM_USE_CT32B0_CH1) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT32B0_CH1             FALSE
-#endif
-
-/**
- * @brief   PWMD4 Channel 0 driver enable switch.
- * @details If set to @p TRUE PWMD4 Channel 0 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_PWM_USE_CT32B1_CH0) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT32B1_CH0             FALSE
-#endif
-
-/**
- * @brief   PWMD4 Channel 1 driver enable switch.
- * @details If set to @p TRUE PWMD4 Channel 1 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC11xx_PWM_USE_CT32B1_CH1) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_USE_CT32B1_CH1             FALSE
-#endif
-/**
- * @brief   PWMD1 interrupt priority level setting.
- */
-#if !defined(LPC11xx_PWM_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_CT16B0_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   PWMD2 interrupt priority level setting.
- */
-#if !defined(LPC11xx_PWM_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_CT16B1_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   PWMD3 interrupt priority level setting.
- */
-#if !defined(LPC11xx_PWM_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_CT32B0_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   PWMD4 interrupt priority level setting.
- */
-#if !defined(LPC11xx_PWM_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_PWM_CT32B1_IRQ_PRIORITY         3
-#endif
-
-/*===========================================================================*/
-/* Configuration checks.                                                     */
-/*===========================================================================*/
-
-
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief   PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief   PWM counter type.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief   PWM driver channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel active logic level.
-   */
-  pwmmode_t                 mode;
-  /**
-   * @brief Channel callback pointer.
-   * @note  This callback is invoked on the channel compare event. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief   PWM driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  uint32_t                  frequency;
-  /**
-   * @brief   PWM period in ticks.
-   * @note    The low level can use assertions in order to catch invalid
-   *          period specifications.
-   */
-  pwmcnt_t                  period;
-  /**
-   * @brief Periodic callback pointer.
-   * @note  This callback is invoked on PWM counter reset. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /**
-   * @brief Channels configurations.
-   */
-  PWMChannelConfig          channels[PWM_CHANNELS];
-  /* End of the mandatory fields.*/
-
-} PWMConfig;
-
-/**
- * @brief   Structure representing a PWM driver.
- */
-struct PWMDriver {
-  /**
-   * @brief Driver state.
-   */
-  pwmstate_t                state;
-  /**
-   * @brief Current driver configuration data.
-   */
-  const PWMConfig           *config;
-  /**
-   * @brief   Current PWM period in ticks.
-   */
-  pwmcnt_t                  period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
-  PWM_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Timer base clock.
-   */
-  uint32_t                  clock;
-  /**
-   * @brief Pointer to the TIMx registers block.
-   */
-  LPC_TMR_TypeDef           *tim;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- *          been activated using @p pwmStart().
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The PWM unit period is changed to the new value.
- * @note    The function has effect at the next cycle start.
- * @note    If a period is specified that is shorter than the pulse width
- *          programmed in one of the channels then the behavior is not
- *          guaranteed.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] period    new cycle time in ticks
- *
- * @notapi
- */
-#define pwm_lld_change_period(pwmp, period)                                 \
-  ((pwmp)->tim->MR3 = (period))
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC11xx_PWM_USE_CT16B0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if LPC11xx_PWM_USE_CT16B1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if LPC11xx_PWM_USE_CT32B0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if LPC11xx_PWM_USE_CT32B1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void pwm_lld_init(void);
-  void pwm_lld_start(PWMDriver *pwmp);
-  void pwm_lld_stop(PWMDriver *pwmp);
-  void pwm_lld_enable_channel(PWMDriver *pwmp,
-                              pwmchannel_t channel,
-                              pwmcnt_t width);
-  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/serial_lld.c b/os/hal/platforms/LPC11xx/serial_lld.c
deleted file mode 100644
index 2fdb14ed0..000000000
--- a/os/hal/platforms/LPC11xx/serial_lld.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/serial_lld.c
- * @brief   LPC11xx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC11xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  LCR_WL8 | LCR_STOP1 | LCR_NOPARITY,
-  FCR_TRIGGER0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   UART initialization.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
-  LPC_UART_TypeDef *u = sdp->uart;
-
-  uint32_t div = LPC11xx_SERIAL_UART0_PCLK / (config->sc_speed << 4);
-  u->LCR = config->sc_lcr | LCR_DLAB;
-  u->DLL = div;
-  u->DLM = div >> 8;
-  u->LCR = config->sc_lcr;
-  u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr;
-  u->ACR = 0;
-  u->FDR = 0x10;
-  u->TER = TER_ENABLE;
-  u->IER = IER_RBR | IER_STATUS;
-}
-
-/**
- * @brief   UART de-initialization.
- *
- * @param[in] u         pointer to an UART I/O block
- */
-static void uart_deinit(LPC_UART_TypeDef *u) {
-
-  u->LCR = LCR_DLAB;
-  u->DLL = 1;
-  u->DLM = 0;
-  u->LCR = 0;
-  u->FDR = 0x10;
-  u->IER = 0;
-  u->FCR = FCR_RXRESET | FCR_TXRESET;
-  u->ACR = 0;
-  u->TER = TER_ENABLE;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] err       UART LSR register value
- */
-static void set_error(SerialDriver *sdp, IOREG32 err) {
-  flagsmask_t sts = 0;
-
-  if (err & LSR_OVERRUN)
-    sts |= SD_OVERRUN_ERROR;
-  if (err & LSR_PARITY)
-    sts |= SD_PARITY_ERROR;
-  if (err & LSR_FRAMING)
-    sts |= SD_FRAMING_ERROR;
-  if (err & LSR_BREAK)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- * @note    Tries hard to clear all the pending interrupt sources, we don't
- *          want to go through the whole ISR and have another interrupt soon
- *          after.
- *
- * @param[in] u         pointer to an UART I/O block
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  LPC_UART_TypeDef *u = sdp->uart;
-
-  while (TRUE) {
-    switch (u->IIR & IIR_SRC_MASK) {
-    case IIR_SRC_NONE:
-      return;
-    case IIR_SRC_ERROR:
-      set_error(sdp, u->LSR);
-      break;
-    case IIR_SRC_TIMEOUT:
-    case IIR_SRC_RX:
-      chSysLockFromIsr();
-      if (chIQIsEmptyI(&sdp->iqueue))
-        chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
-      chSysUnlockFromIsr();
-      while (u->LSR & LSR_RBR_FULL) {
-        chSysLockFromIsr();
-        if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK)
-          chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
-        chSysUnlockFromIsr();
-      }
-      break;
-    case IIR_SRC_TX:
-      {
-        int i = LPC11xx_SERIAL_FIFO_PRELOAD;
-        do {
-          msg_t b;
-
-          chSysLockFromIsr();
-          b = chOQGetI(&sdp->oqueue);
-          chSysUnlockFromIsr();
-          if (b < Q_OK) {
-            u->IER &= ~IER_THRE;
-            chSysLockFromIsr();
-            chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-            chSysUnlockFromIsr();
-            break;
-          }
-          u->THR = b;
-        } while (--i);
-      }
-      break;
-    default:
-      (void) u->THR;
-      (void) u->RBR;
-    }
-  }
-}
-
-/**
- * @brief   Attempts a TX FIFO preload.
- */
-static void preload(SerialDriver *sdp) {
-  LPC_UART_TypeDef *u = sdp->uart;
-
-  if (u->LSR & LSR_THRE) {
-    int i = LPC11xx_SERIAL_FIFO_PRELOAD;
-    do {
-      msg_t b = chOQGetI(&sdp->oqueue);
-      if (b < Q_OK) {
-        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-        return;
-      }
-      u->THR = b;
-    } while (--i);
-  }
-  u->IER |= IER_THRE;
-}
-
-/**
- * @brief   Driver SD1 output notification.
- */
-#if LPC11xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD1);
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 IRQ handler.
- *
- * @isr
- */
-#if LPC11xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector94) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if LPC11xx_SERIAL_USE_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = LPC_UART;
-  LPC_IOCON->PIO1_6 = 0xC1;                 /* RDX without resistors.       */
-  LPC_IOCON->PIO1_7 = 0xC1;                 /* TDX without resistors.       */
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if LPC11xx_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
-      LPC_SYSCON->UARTCLKDIV = LPC11xx_SERIAL_UART0CLKDIV;
-      nvicEnableVector(UART_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC11xx_SERIAL_UART0_IRQ_PRIORITY));
-    }
-#endif
-  }
-  uart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the UART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    uart_deinit(sdp->uart);
-#if LPC11xx_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->UARTCLKDIV = 0;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12);
-      nvicDisableVector(UART_IRQn);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/serial_lld.h b/os/hal/platforms/LPC11xx/serial_lld.h
deleted file mode 100644
index c4178816e..000000000
--- a/os/hal/platforms/LPC11xx/serial_lld.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/serial_lld.h
- * @brief   LPC11xx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define IIR_SRC_MASK    0x0F
-#define IIR_SRC_NONE    0x01
-#define IIR_SRC_MODEM   0x00
-#define IIR_SRC_TX      0x02
-#define IIR_SRC_RX      0x04
-#define IIR_SRC_ERROR   0x06
-#define IIR_SRC_TIMEOUT 0x0C
-
-#define IER_RBR         1
-#define IER_THRE        2
-#define IER_STATUS      4
-
-#define LCR_WL5         0
-#define LCR_WL6         1
-#define LCR_WL7         2
-#define LCR_WL8         3
-#define LCR_STOP1       0
-#define LCR_STOP2       4
-#define LCR_NOPARITY    0
-#define LCR_PARITYODD   0x08
-#define LCR_PARITYEVEN  0x18
-#define LCR_PARITYONE   0x28
-#define LCR_PARITYZERO  0x38
-#define LCR_BREAK_ON    0x40
-#define LCR_DLAB        0x80
-
-#define FCR_ENABLE      1
-#define FCR_RXRESET     2
-#define FCR_TXRESET     4
-#define FCR_TRIGGER0    0
-#define FCR_TRIGGER1    0x40
-#define FCR_TRIGGER2    0x80
-#define FCR_TRIGGER3    0xC0
-
-#define LSR_RBR_FULL    1
-#define LSR_OVERRUN     2
-#define LSR_PARITY      4
-#define LSR_FRAMING     8
-#define LSR_BREAK       0x10
-#define LSR_THRE        0x20
-#define LSR_TEMT        0x40
-#define LSR_RXFE        0x80
-
-#define TER_ENABLE      0x80
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC11xx_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define LPC11xx_SERIAL_USE_UART0            TRUE
-#endif
-
-/**
- * @brief   FIFO preload parameter.
- * @details Configuration parameter, this values defines how many bytes are
- *          preloaded in the HW transmit FIFO for each interrupt, the maximum
- *          value is 16 the minimum is 1.
- * @note    An high value reduces the number of interrupts generated but can
- *          also increase the worst case interrupt response time because the
- *          preload loops.
- */
-#if !defined(LPC11xx_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__)
-#define LPC11xx_SERIAL_FIFO_PRELOAD         16
-#endif
-
-/**
- * @brief   UART0 PCLK divider.
- */
-#if !defined(LPC11xx_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__)
-#define LPC11xx_SERIAL_UART0CLKDIV          1
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(LPC11xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_SERIAL_UART0_IRQ_PRIORITY   3
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC11xx_SERIAL_UART0CLKDIV < 1) || (LPC11xx_SERIAL_UART0CLKDIV > 255)
-#error "invalid LPC11xx_SERIAL_UART0CLKDIV setting"
-#endif
-
-#if (LPC11xx_SERIAL_FIFO_PRELOAD < 1) || (LPC11xx_SERIAL_FIFO_PRELOAD > 16)
-#error "invalid LPC11xx_SERIAL_FIFO_PRELOAD setting"
-#endif
-
-/**
- * @brief   UART0 clock.
- */
-#define  LPC11xx_SERIAL_UART0_PCLK                                          \
-  (LPC11xx_MAINCLK / LPC11xx_SERIAL_UART0CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   LPC11xx Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the LCR register.
-   */
-  uint32_t                  sc_lcr;
-  /**
-   * @brief Initialization value for the FCR register.
-   */
-  uint32_t                  sc_fcr;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  LPC_UART_TypeDef        *uart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC11xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/spi_lld.c b/os/hal/platforms/LPC11xx/spi_lld.c
deleted file mode 100644
index ab09f540b..000000000
--- a/os/hal/platforms/LPC11xx/spi_lld.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/spi_lld.c
- * @brief   LPC11xx low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC11xx_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-#if LPC11xx_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/** @brief SPI2 driver identifier.*/
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Preloads the transmit FIFO.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void ssp_fifo_preload(SPIDriver *spip) {
-  LPC_SSP_TypeDef *ssp = spip->ssp;
-  uint32_t n = spip->txcnt > LPC11xx_SSP_FIFO_DEPTH ?
-               LPC11xx_SSP_FIFO_DEPTH : spip->txcnt;
-
-  while(((ssp->SR & SR_TNF) != 0) && (n > 0)) {
-    if (spip->txptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        const uint16_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-      else {
-        const uint8_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-    }
-    else
-      ssp->DR = 0xFFFFFFFF;
-    n--;
-    spip->txcnt--;
-  }
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void spi_serve_interrupt(SPIDriver *spip) {
-  LPC_SSP_TypeDef *ssp = spip->ssp;
-
-  if ((ssp->MIS & MIS_ROR) != 0) {
-    /* The overflow condition should never happen because priority is given
-       to receive but a hook macro is provided anyway...*/
-    LPC11xx_SPI_SSP_ERROR_HOOK(spip);
-  }
-  ssp->ICR = ICR_RT | ICR_ROR;
-  while ((ssp->SR & SR_RNE) != 0) {
-    if (spip->rxptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        uint16_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-      else {
-        uint8_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-    }
-    else
-      (void)ssp->DR;
-    if (--spip->rxcnt == 0) {
-      chDbgAssert(spip->txcnt == 0,
-                  "spi_serve_interrupt(), #1", "counter out of synch");
-      /* Stops the IRQ sources.*/
-      ssp->IMSC = 0;
-      /* Portable SPI ISR code defined in the high level driver, note, it is
-         a macro.*/
-      _spi_isr_code(spip);
-      return;
-    }
-  }
-  ssp_fifo_preload(spip);
-  if (spip->txcnt == 0)
-    ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC11xx_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/**
- * @brief   SSP0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector90) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC11xx_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/**
- * @brief   SSP1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector78) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if LPC11xx_SPI_USE_SSP0
-  spiObjectInit(&SPID1);
-  SPID1.ssp = LPC_SSP0;
-  LPC_IOCON->SCK_LOC = LPC11xx_SPI_SCK0_SELECTOR;
-#if LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_10
-  LPC_IOCON->SWCLK_PIO0_10 = 0xC2;          /* SCK0 without resistors.      */
-#elif LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO2_11
-  LPC_IOCON->PIO2_11 = 0xC1;                /* SCK0 without resistors.      */
-#else /* LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_6 */
-  LPC_IOCON->PIO0_6  = 0xC2;                /* SCK0 without resistors.      */
-#endif
-  LPC_IOCON->PIO0_8  = 0xC1;                /* MISO0 without resistors.     */
-  LPC_IOCON->PIO0_9  = 0xC1;                /* MOSI0 without resistors.     */
-#endif /* LPC11xx_SPI_USE_SSP0 */
-
-#if LPC11xx_SPI_USE_SSP1
-  spiObjectInit(&SPID2);
-  SPID2.ssp = LPC_SSP1;
-  LPC_IOCON->PIO2_1  = 0xC2;                /* SCK1 without resistors.      */
-  LPC_IOCON->PIO2_2  = 0xC2;                /* MISO1 without resistors.     */
-  LPC_IOCON->PIO2_3  = 0xC2;                /* MOSI1 without resistors.     */
-#endif /* LPC11xx_SPI_USE_SSP0 */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-    /* Clock activation.*/
-#if LPC11xx_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SYSCON->SSP0CLKDIV = LPC11xx_SPI_SSP0CLKDIV;
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11);
-      LPC_SYSCON->PRESETCTRL |= 1;
-      nvicEnableVector(SSP0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP0_IRQ_PRIORITY));
-    }
-#endif
-#if LPC11xx_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_SYSCON->SSP1CLKDIV = LPC11xx_SPI_SSP1CLKDIV;
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18);
-      LPC_SYSCON->PRESETCTRL |= 4;
-      nvicEnableVector(SSP1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC11xx_SPI_SSP1_IRQ_PRIORITY));
-    }
-#endif
-  }
-  /* Configuration.*/
-  spip->ssp->CR1  = 0;
-  spip->ssp->ICR  = ICR_RT | ICR_ROR;
-  spip->ssp->CR0  = spip->config->cr0;
-  spip->ssp->CPSR = spip->config->cpsr;
-  spip->ssp->CR1  = CR1_SSE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state != SPI_STOP) {
-    spip->ssp->CR1  = 0;
-    spip->ssp->CR0  = 0;
-    spip->ssp->CPSR = 0;
-#if LPC11xx_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SYSCON->PRESETCTRL &= ~1;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11);
-      LPC_SYSCON->SSP0CLKDIV = 0;
-      nvicDisableVector(SSP0_IRQn);
-    }
-#endif
-#if LPC11xx_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_SYSCON->PRESETCTRL &= ~4;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18);
-      LPC_SYSCON->SSP1CLKDIV = 0;
-      nvicDisableVector(SSP1_IRQn);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->rxptr = NULL;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->rxptr = NULL;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->ssp->DR = (uint32_t)frame;
-  while ((spip->ssp->SR & SR_RNE) == 0)
-    ;
-  return (uint16_t)spip->ssp->DR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/spi_lld.h b/os/hal/platforms/LPC11xx/spi_lld.h
deleted file mode 100644
index 4d6c56027..000000000
--- a/os/hal/platforms/LPC11xx/spi_lld.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC11xx/spi_lld.h
- * @brief   LPC11xx low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Hardware FIFO depth.
- */
-#define LPC11xx_SSP_FIFO_DEPTH  8
-
-#define CR0_DSSMASK             0x0F
-#define CR0_DSS4BIT             3
-#define CR0_DSS5BIT             4
-#define CR0_DSS6BIT             5
-#define CR0_DSS7BIT             6
-#define CR0_DSS8BIT             7
-#define CR0_DSS9BIT             8
-#define CR0_DSS10BIT            9
-#define CR0_DSS11BIT            0xA
-#define CR0_DSS12BIT            0xB
-#define CR0_DSS13BIT            0xC
-#define CR0_DSS14BIT            0xD
-#define CR0_DSS15BIT            0xE
-#define CR0_DSS16BIT            0xF
-#define CR0_FRFSPI              0
-#define CR0_FRFSSI              0x10
-#define CR0_FRFMW               0x20
-#define CR0_CPOL                0x40
-#define CR0_CPHA                0x80
-#define CR0_CLOCKRATE(n)        ((n) << 8)
-
-#define CR1_LBM                 1
-#define CR1_SSE                 2
-#define CR1_MS                  4
-#define CR1_SOD                 8
-
-#define SR_TFE                  1
-#define SR_TNF                  2
-#define SR_RNE                  4
-#define SR_RFF                  8
-#define SR_BSY                  16
-
-#define IMSC_ROR                1
-#define IMSC_RT                 2
-#define IMSC_RX                 4
-#define IMSC_TX                 8
-
-#define RIS_ROR                 1
-#define RIS_RT                  2
-#define RIS_RX                  4
-#define RIS_TX                  8
-
-#define MIS_ROR                 1
-#define MIS_RT                  2
-#define MIS_RX                  4
-#define MIS_TX                  8
-
-#define ICR_ROR                 1
-#define ICR_RT                  2
-
-/**
- * @brief   SCK0 signal assigned to pin PIO0_10.
- */
-#define SCK0_IS_PIO0_10         0
-
-/**
- * @brief   SCK0 signal assigned to pin PIO2_11.
- */
-#define SCK0_IS_PIO2_11         1
-
-/**
- * @brief   SCK0 signal assigned to pin PIO0_6.
- */
-#define SCK0_IS_PIO0_6          2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for device SSP0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_SPI_USE_SSP0) || defined(__DOXYGEN__)
-#define LPC11xx_SPI_USE_SSP0                TRUE
-#endif
-
-/**
- * @brief   SPI2 driver enable switch.
- * @details If set to @p TRUE the support for device SSP1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC11xx_SPI_USE_SSP1) || defined(__DOXYGEN__)
-#define LPC11xx_SPI_USE_SSP1                TRUE
-#endif
-
-/**
- * @brief   SSP0 PCLK divider.
- */
-#if !defined(LPC11xx_SPI_SSP0CLKDIV) || defined(__DOXYGEN__)
-#define LPC11xx_SPI_SSP0CLKDIV              1
-#endif
-
-/**
- * @brief   SSP1 PCLK divider.
- */
-#if !defined(LPC11xx_SPI_SSP1CLKDIV) || defined(__DOXYGEN__)
-#define LPC11xx_SPI_SSP1CLKDIV              1
-#endif
-
-/**
- * @brief   SPI0 interrupt priority level setting.
- */
-#if !defined(LPC11xx_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_SPI_SSP0_IRQ_PRIORITY       1
-#endif
-
-/**
- * @brief   SPI1 interrupt priority level setting.
- */
-#if !defined(LPC11xx_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC11xx_SPI_SSP1_IRQ_PRIORITY       1
-#endif
-
-/**
- * @brief   Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(LPC11xx_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__)
-#define LPC11xx_SPI_SSP_ERROR_HOOK(spip)    chSysHalt()
-#endif
-
-/**
- * @brief   SCK0 signal selector.
- */
-#if !defined(LPC11xx_SPI_SCK0_SELECTOR) || defined(__DOXYGEN__)
-#define LPC11xx_SPI_SCK0_SELECTOR           SCK0_IS_PIO2_11
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC11xx_SPI_SSP0CLKDIV < 1) || (LPC11xx_SPI_SSP0CLKDIV > 255)
-#error "invalid LPC11xx_SPI_SSP0CLKDIV setting"
-#endif
-
-#if (LPC11xx_SPI_SSP1CLKDIV < 1) || (LPC11xx_SPI_SSP1CLKDIV > 255)
-#error "invalid LPC11xx_SPI_SSP1CLKDIV setting"
-#endif
-
-#if !LPC11xx_SPI_USE_SSP0 && !LPC11xx_SPI_USE_SSP1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-#if (LPC11xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_10) &&                       \
-    (LPC11xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO2_11) &&                       \
-    (LPC11xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_6)
-#error "invalid pin assigned to SCK0 signal"
-#endif
-
-/**
- * @brief   SSP0 clock.
- */
-#define LPC11xx_SPI_SSP0_PCLK                                               \
-  (LPC11xx_MAINCLK / LPC11xx_SPI_SSP0CLKDIV)
-
-/**
- * @brief   SSP1 clock.
- */
-#define LPC11xx_SPI_SSP1_PCLK                                               \
-  (LPC11xx_MAINCLK / LPC11xx_SPI_SSP1CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief SSP CR0 initialization data.
-   */
-  uint16_t              cr0;
-  /**
-   * @brief SSP CPSR initialization data.
-   */
-  uint32_t              cpsr;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SSP registers block.
-   */
-  LPC_SSP_TypeDef       *ssp;
-  /**
-   * @brief Number of bytes yet to be received.
-   */
-  uint32_t              rxcnt;
-  /**
-   * @brief Receive pointer or @p NULL.
-   */
-  void                  *rxptr;
-  /**
-   * @brief Number of bytes yet to be transmitted.
-   */
-  uint32_t              txcnt;
-  /**
-   * @brief Transmit pointer or @p NULL.
-   */
-  const void            *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC11xx_SPI_USE_SSP0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if LPC11xx_SPI_USE_SSP1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC11xx/system_LPC11xx.h b/os/hal/platforms/LPC11xx/system_LPC11xx.h
deleted file mode 100644
index e4536b8a5..000000000
--- a/os/hal/platforms/LPC11xx/system_LPC11xx.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/******************************************************************************
- * @file:    system_LPC11xx.h
- * @purpose: CMSIS Cortex-M0 Device Peripheral Access Layer Header File
- *           for the NXP LPC11xx Device Series 
- * @version: V1.0
- * @date:    25. Nov. 2008
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2008 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC11xx_H
-#define __SYSTEM_LPC11xx_H
-
-/* Vector Table Base ---------------------------------------------------------*/
-#define NVIC_VectTab_RAM             (0x10000000)
-#define NVIC_VectTab_FLASH           (0x00000000)
-
-extern uint32_t ClockSource;
-extern uint32_t SystemFrequency;    /*!< System Clock Frequency (Core Clock)  */
-extern uint32_t SystemAHBFrequency;
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemFrequency variable.
- */
-extern void SystemInit (void);
-#endif
diff --git a/os/hal/platforms/LPC122x/LPC122x.h b/os/hal/platforms/LPC122x/LPC122x.h
deleted file mode 100644
index 8415b06fa..000000000
--- a/os/hal/platforms/LPC122x/LPC122x.h
+++ /dev/null
@@ -1,725 +0,0 @@
-/**************************************************************************//**
- * $Id: LPC122x.h 6933 2011-03-23 19:02:11Z nxp28548 $
- *
- * @file     LPC122x.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 
- *           NXP LPC122x Device Series
- * @version  1.1
- * @date     $Date:: 2011-03-23#$
- * @author   NXP MCU Team
- *
- * @note
- * Copyright (C) 2011 NXP Semiconductors(NXP). All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
- ******************************************************************************/
-
-
-
-/** @addtogroup (null)
-  * @{
-  */
-
-/** @addtogroup LPC122x
-  * @{
-  */
-
-#ifndef __LPC122X_H__
-#define __LPC122X_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-
-#if defined ( __CC_ARM   )
-  #pragma anon_unions
-#endif
-
- /* Interrupt Number Definition */
-
-typedef enum {
-	// -------------------------  Cortex-M0 Processor Exceptions Numbers  -----------------------------
-	Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
-	NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
-	HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
-	SVCall_IRQn                       = -5,   /*!<  11  System Service Call via SVC instruction */
-	DebugMonitor_IRQn                 = -4,   /*!<  12  Debug Monitor                    */
-	PendSV_IRQn                       = -2,   /*!<  14  Pendable request for system service */
-	SysTick_IRQn                      = -1,   /*!<  15  System Tick Timer                */
-	// ---------------------------  LPC122x Specific Interrupt Numbers  -------------------------------
-	WAKEUP0_IRQn			= 0,	/*!< PIO0_0 to PIO0_11	Wakeup */
-	WAKEUP1_IRQn			= 1,
-	WAKEUP2_IRQn			= 2,
-	WAKEUP3_IRQn			= 3,
-	WAKEUP4_IRQn			= 4,
-	WAKEUP5_IRQn			= 5,
-	WAKEUP6_IRQn			= 6,
-	WAKEUP7_IRQn			= 7,
-	WAKEUP8_IRQn			= 8,
-	WAKEUP9_IRQn			= 9,
-	WAKEUP10_IRQn			= 10,
-	WAKEUP11_IRQn			= 11,	/*!< PIO0_0 to PIO0_11	Wakeup */
-	I2C_IRQn				=12,	/*!< I2C Interrupt	*/
-	TIMER_16_0_IRQn			= 13,	/*!< 16-bit Timer0 Interrupt	*/
-	TIMER_16_1_IRQn			= 14,	/*!< 16-bit Timer1 Interrupt	*/
-	TIMER_32_0_IRQn			= 15,	/*!< 32-bit Timer0 Interrupt	*/
-	TIMER_32_1_IRQn			= 16,	/*!< 32-bit Timer1 Interrupt	*/
-	SSP_IRQn				= 17,	/*!< SSP Interrupt	*/
-	UART0_IRQn				= 18,	/*!< UART0 Interrupt	*/
-	UART1_IRQn				= 19,	/*!< UART1 Interrupt	*/
-	CMP_IRQn				= 20,	/*!< Comparator Interrupt	*/
-	ADC_IRQn				= 21,	/*!< A/D Converter Interrupt	*/
-	WDT_IRQn				= 22,	/*!< Watchdog timer Interrupt	*/
-	BOD_IRQn				= 23,	/*!< Brown Out Detect(BOD) Interrupt	*/
-	EINT0_IRQn				= 25,	/*!< External Interrupt 0 Interrupt	*/
-	EINT1_IRQn				= 26,	/*!< External Interrupt 1 Interrupt	*/
-	EINT2_IRQn				= 27,	/*!< External Interrupt 2 Interrupt	*/
-	DMA_IRQn				= 29,	/*!< DMA Interrupt	*/
-	RTC_IRQn				= 30,	/*!< RTC Interrupt	*/
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
-  * @{
-  */
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M0 Processor and Core Peripherals */
-#define __MPU_PRESENT             0         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-/*@}*/ /* end of group LPC12xx_CMSIS */
-
-
-#include "core_cm0.h"                       /* Cortex-M0 processor and core peripherals           */
-#include "system_LPC122x.h"                 /* System Header									  */
-
-/** @addtogroup Device_Peripheral_Registers
-  * @{
-  */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          I2C                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x I2C-bus controller Modification date=2/2/2011 Major revision=0 Minor revision=17  (I2C)
-  */
-
-typedef struct {                            /*!< (@ 0x40000000) I2C Structure          */
-  __IO uint32_t CONSET;                     /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
-  __I  uint32_t STAT;                       /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
-  __IO uint32_t DAT;                        /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
-  __IO uint32_t ADR0;                       /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  __IO uint32_t SCLH;                       /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
-  __IO uint32_t SCLL;                       /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
-  __IO uint32_t CONCLR;                     /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
-  __IO uint32_t MMCTRL;                     /*!< (@ 0x4000001C) Monitor mode control register. */
-  __IO uint32_t ADR1;                       /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  __IO uint32_t ADR2;                       /*!< (@ 0x40000024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  __IO uint32_t ADR3;                       /*!< (@ 0x40000028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
-  __IO uint32_t MASK[4];                    /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
-} LPC_I2C_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         WWDT                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x Windowed Watchdog Timer (WWDT) Modification date=2/2/2011 Major revision=0 Minor revision=17  (WWDT)
-  */
-
-typedef struct {                            /*!< (@ 0x40004000) WWDT Structure         */
-  __IO uint32_t MOD;                        /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
-  __IO uint32_t TC;                         /*!< (@ 0x40004004) Watchdog timer constant register. This register determines the time-out value. */
-  __IO uint32_t FEED;                       /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
-  __I  uint32_t TV;                         /*!< (@ 0x4000400C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
-  __IO uint32_t CLKSEL;                     /*!< (@ 0x40004010) Watchdog clock source selection register. */
-  __IO uint32_t WARNINT;                    /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
-  __IO uint32_t WINDOW;                     /*!< (@ 0x40004018) Watchdog Window compare value. */
-} LPC_WWDT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         UART0                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x UART0 with modem control Modification date=2/2/2011 Major revision=0 Minor revision=17  (UART0)
-  */
-
-typedef struct {                            /*!< (@ 0x40008000) UART0 Structure        */
-  
-  union {
-    __IO uint32_t DLL;                      /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB = 1) */
-    __IO uint32_t THR;                      /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
-    __I  uint32_t RBR;                      /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
-  };
-  
-  union {
-    __IO uint32_t IER;                      /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0) */
-    __IO uint32_t DLM;                      /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB = 1) */
-  };
-  
-  union {
-    __IO uint32_t FCR;                      /*!< (@ 0x40008008) FIFO Control Register. Controls UART FIFO usage and modes. */
-    __I  uint32_t IIR;                      /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
-  };
-  __IO uint32_t LCR;                        /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
-  __IO uint32_t MCR;                        /*!< (@ 0x40008010) Modem control register */
-  __I  uint32_t LSR;                        /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
-  __I  uint32_t MSR;                        /*!< (@ 0x40008018) Modem status register  */
-  __IO uint32_t SCR;                        /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
-  __IO uint32_t ACR;                        /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
-  __I  uint32_t RESERVED0[1];
-  __IO uint32_t FDR;                        /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
-  __I  uint32_t RESERVED1[1];
-  __IO uint32_t TER;                        /*!< (@ 0x40008030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
-  __I  uint32_t RESERVED2[6];
-  __IO uint32_t RS485CTRL;                  /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
-  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
-  __IO uint32_t RS485DLY;                   /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
-  __I  uint32_t FIFOLVL;                    /*!< (@ 0x40008058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
-} LPC_UART0_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         UART1                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x UART1 Modification date=2/3/2011 Major revision=0 Minor revision=17  (UART1)
-  */
-
-typedef struct {                            /*!< (@ 0x4000C000) UART1 Structure        */
-  
-  union {
-    __IO uint32_t DLL;                      /*!< (@ 0x4000C000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. */
-    __IO uint32_t THR;                      /*!< (@ 0x4000C000) Transmit Holding Register. The next character to be transmitted is written here. */
-    __I  uint32_t RBR;                      /*!< (@ 0x4000C000) Receiver Buffer Register. Contains the next received character to be read. */
-  };
-  
-  union {
-    __IO uint32_t IER;                      /*!< (@ 0x4000C004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. */
-    __IO uint32_t DLM;                      /*!< (@ 0x4000C004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. */
-  };
-  
-  union {
-    __IO uint32_t FCR;                      /*!< (@ 0x4000C008) FIFO Control Register. Controls UART FIFO usage and modes. */
-    __I  uint32_t IIR;                      /*!< (@ 0x4000C008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
-  };
-  __IO uint32_t LCR;                        /*!< (@ 0x4000C00C) Line Control Register. Contains controls for frame formatting and break generation. */
-  __I  uint32_t RESERVED0[1];
-  __I  uint32_t LSR;                        /*!< (@ 0x4000C014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
-  __I  uint32_t RESERVED1[1];
-  __IO uint32_t SCR;                        /*!< (@ 0x4000C01C) Scratch Pad Register. Eight-bit temporary storage for software. */
-  __IO uint32_t ACR;                        /*!< (@ 0x4000C020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
-  __IO uint32_t ICR;                        /*!< (@ 0x4000C024) IrDA Control Register. Enables and configures the IrDA mode. */
-  __IO uint32_t FDR;                        /*!< (@ 0x4000C028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
-  __I  uint32_t RESERVED2[1];
-  __IO uint32_t TER;                        /*!< (@ 0x4000C030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
-  __I  uint32_t RESERVED3[9];
-  __I  uint32_t FIFOLVL;                    /*!< (@ 0x4000C058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
-} LPC_UART1_Type;
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        CT32B0                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x 32-bit Counter/timer 0/1 (CT32B0/1) Modification date=2/3/2011 Major revision=0 Minor revision=17  (CT32B0)
-  */
-
-typedef struct {                            /*!< (@ 0x40018000) CT32B0 Structure       */
-  __IO uint32_t IR;                         /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
-  __IO uint32_t TCR;                        /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
-  __IO uint32_t TC;                         /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
-  __IO uint32_t PR;                         /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
-  __IO uint32_t PC;                         /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
-  __IO uint32_t MCR;                        /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
-  union {
-  __IO uint32_t MR[4];                      /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
-  struct{
-  __IO uint32_t MR0;                        /*!< (@ 0x40018018) Match Register. MR0 */
-  __IO uint32_t MR1;                        /*!< (@ 0x40018018) Match Register. MR1 */
-  __IO uint32_t MR2;                        /*!< (@ 0x40018018) Match Register. MR2 */
-  __IO uint32_t MR3;                        /*!< (@ 0x40018018) Match Register. MR3 */
-  };
-  };
-  __IO uint32_t CCR;                        /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
-  union{
-  __I  uint32_t CR[4];                      /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP input. */
-  struct{
-  __I  uint32_t CR0;						/*!< (@ 0x4001802C) Capture Register. CR 0 */
-  __I  uint32_t CR1;						/*!< (@ 0x4001802C) Capture Register. CR 1 */
-  __I  uint32_t CR2;						/*!< (@ 0x4001802C) Capture Register. CR 2 */
-  __I  uint32_t CR3;						/*!< (@ 0x4001802C) Capture Register. CR 3 */
-  };
-  };
-  __IO uint32_t EMR;                        /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
-  __I  uint32_t RESERVED0[12];
-  __IO uint32_t CTCR;                       /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-  __IO uint32_t PWMC;                       /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
-} LPC_CTxxBx_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          ADC                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x ADC Modification date=2/9/2011 Major revision=0 Minor revision=17  (ADC)
-  */
-
-typedef struct {                            /*!< (@ 0x40020000) ADC Structure          */
-  __IO uint32_t CR;                         /*!< (@ 0x40020000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
-  __IO uint32_t GDR;                        /*!< (@ 0x40020004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
-  __I  uint32_t RESERVED0[1];
-  __IO uint32_t INTEN;                      /*!< (@ 0x4002000C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
-  union{
-  __IO uint32_t DR[8];                  	/*!< (@ 0x40020010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel. */
-  struct{
-  __IO uint32_t DR0;                      	/*!< (@ 0x40020010) A/D Channel Data Register 0*/
-  __IO uint32_t DR1;                      	/*!< (@ 0x40020010) A/D Channel Data Register 1*/
-  __IO uint32_t DR2;                      	/*!< (@ 0x40020010) A/D Channel Data Register 2*/
-  __IO uint32_t DR3;                      	/*!< (@ 0x40020010) A/D Channel Data Register 3*/
-  __IO uint32_t DR4;                      	/*!< (@ 0x40020010) A/D Channel Data Register 4*/
-  __IO uint32_t DR5;                      	/*!< (@ 0x40020010) A/D Channel Data Register 5*/
-  __IO uint32_t DR6;                      	/*!< (@ 0x40020010) A/D Channel Data Register 6*/
-  __IO uint32_t DR7;                      	/*!< (@ 0x40020010) A/D Channel Data Register 7*/
-  };
-  };
-  __I  uint32_t STAT;                       /*!< (@ 0x40020030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
-  __IO uint32_t TRM;                        /*!< (@ 0x40020034) A/D trim register      */
-} LPC_ADC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          PMU                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x Power Monitor Unit (PMU) Modification date=2/10/2011 Major revision=0 Minor revision=17  (PMU)
-  */
-
-typedef struct {                            /*!< (@ 0x40038000) PMU Structure          */
-  __IO uint32_t PCON;                       /*!< (@ 0x40038000) Power control register */
-  union{
-  __IO uint32_t GPREG[4];                   /*!< (@ 0x40038004) General purpose register  */
-  struct{
-  __IO uint32_t GPREG0;                   	/*!< (@ 0x40038004) General purpose register 0 */
-  __IO uint32_t GPREG1;                   	/*!< (@ 0x40038004) General purpose register 1 */
-  __IO uint32_t GPREG2;                   	/*!< (@ 0x40038004) General purpose register 2 */
-  __IO uint32_t GPREG3;                   	/*!< (@ 0x40038004) General purpose register 3 */
-  };
-  };
-  __IO uint32_t SYSCFG;                     /*!< (@ 0x40038014) System configuration register (RTC clock control and hysteresis of the WAKEUP pin). */
-} LPC_PMU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          SSP                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x SSP controller Modification date=2/10/2011 Major revision=0 Minor revision=17  (SSP)
-  */
-
-typedef struct {                            /*!< (@ 0x40040000) SSP Structure          */
-	union{
-  __IO uint32_t CR[2];						/*!< (@ 0x40040000) Control Registers. */
-  struct{
-  __IO uint32_t CR0;                        /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
-  __IO uint32_t CR1;                        /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
-  };
-  };
-  __IO uint32_t DR;                         /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
-  __I  uint32_t SR;                         /*!< (@ 0x4004000C) Status Register        */
-  __IO uint32_t CPSR;                       /*!< (@ 0x40040010) Clock Prescale Register */
-  __IO uint32_t IMSC;                       /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
-  __I  uint32_t RIS;                        /*!< (@ 0x40040018) Raw Interrupt Status Register */
-  __I  uint32_t MIS;                        /*!< (@ 0x4004001C) Masked Interrupt Status Register */
-  __IO uint32_t ICR;                        /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
-  __IO uint32_t DMACR;                      /*!< (@ 0x40040024) DMA Control Register   */
-} LPC_SSP_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         IOCON                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x /O configuration (IOCONFIG) Modification date=2/11/2011 Major revision=1 Minor revision=0  (IOCON)
-  */
-
-typedef struct {                            /*!< (@ 0x40044000) IOCON Structure        */
-  __I  uint32_t RESERVED0[2];
-  __IO uint32_t PIO0_19;                    /*!< (@ 0x40044008) Configures pin PIO0_19/ACMP0_I0/CT32B0_1. */
-  __IO uint32_t PIO0_20;                    /*!< (@ 0x4004400C) Configures pin PIO0_20/ACMP0_I1/CT32B0_2. */
-  __IO uint32_t PIO0_21;                    /*!< (@ 0x40044010) Configures pin PIO0_21/ACMP0_I2/CT32B0_3. */
-  __IO uint32_t PIO0_22;                    /*!< (@ 0x40044014) Configures pin PIO0_22/ACMP0_I3. */
-  __IO uint32_t PIO0_23;                    /*!< (@ 0x40044018) Configures pin PIO0_23/ACMP1_I0/CT32B1_0. */
-  __IO uint32_t PIO0_24;                    /*!< (@ 0x4004401C) Configures pin PIO0_24/ACMP1_I1/CT32B1_1. */
-  __IO uint32_t SWDIO_PIO0_25;              /*!< (@ 0x40044020) Configures pin SWDIO/ACMP1_I2/ CT32B1_2/PIO0_25. */
-  __IO uint32_t SWCLK_PIO0_26;              /*!< (@ 0x40044024) Configures pin SWCLK/PIO0_26/ACMP1_I3/ CT32B1_3/PIO0_26 */
-  __IO uint32_t PIO0_27;                    /*!< (@ 0x40044028) Configures pin PIO0_27/ACMP0_O. */
-  __IO uint32_t PIO2_12;                    /*!< (@ 0x4004402C) Configures pin PIO2_12/RXD1. */
-  __IO uint32_t PIO2_13;                    /*!< (@ 0x40044030) Configures pin PIO2_13/TXD1. */
-  __IO uint32_t PIO2_14;                    /*!< (@ 0x40044034) Configures pin PIO2_14. */
-  __IO uint32_t PIO2_15;                    /*!< (@ 0x40044038) Configures pin PIO2_15. */
-  __IO uint32_t PIO0_28;                    /*!< (@ 0x4004403C) Configures pin PIO0_28/ACMP1_O/CT16B0_0. */
-  __IO uint32_t PIO0_29;                    /*!< (@ 0x40044040) Configures pin PIO0_29/ROSC/CT16B0_1. */
-  __IO uint32_t PIO0_0;                     /*!< (@ 0x40044044) Configures pin PIO0_0/ RTS0. */
-  __IO uint32_t PIO0_1;                     /*!< (@ 0x40044048) Configures pin PIO0_1CT32B0_0/RXD0. */
-  __IO uint32_t PIO0_2;                     /*!< (@ 0x4004404C) Configures pin PIO0_2/TXD0/CT32B0_1. */
-  __I  uint32_t RESERVED1[1];
-  __IO uint32_t PIO0_3;                     /*!< (@ 0x40044054) Configures pin PIO0_3/DTR0/CT32B0_2. */
-  __IO uint32_t PIO0_4;                     /*!< (@ 0x40044058) Configures pin PIO0_4/ DSR0/CT32B0_3. */
-  __IO uint32_t PIO0_5;                     /*!< (@ 0x4004405C) Configures pin PIO0_5. */
-  __IO uint32_t PIO0_6;                     /*!< (@ 0x40044060) Configures pin PIO0_6/RI0/CT32B1_0. */
-  __IO uint32_t PIO0_7;                     /*!< (@ 0x40044064) Configures pin PIO0_7CTS0/CT32B1_1. */
-  __IO uint32_t PIO0_8;                     /*!< (@ 0x40044068) Configures pin PIO0_8/RXD1/CT32B1_2. */
-  __IO uint32_t PIO0_9;                     /*!< (@ 0x4004406C) Configures pin PIO0_9/TXD1/CT32B1_3. */
-  __IO uint32_t PIO2_0;                     /*!< (@ 0x40044070) Configures pin PIO2_0/CT16B0_0/ RTS0. */
-  __IO uint32_t PIO2_1;                     /*!< (@ 0x40044074) Configures pin PIO2_1/CT16B0_1/RXD0. */
-  __IO uint32_t PIO2_2;                     /*!< (@ 0x40044078) Configures pin PIO2_2/CT16B1_0/TXD0. */
-  __IO uint32_t PIO2_3;                     /*!< (@ 0x4004407C) Configures pin PIO2_3/CT16B1_1/DTR0. */
-  __IO uint32_t PIO2_4;                     /*!< (@ 0x40044080) Configures pin PIO2_4/CT32B0_0/CTS0. */
-  __IO uint32_t PIO2_5;                     /*!< (@ 0x40044084) Configures pin PIO2_5/CT32B0_1/ DCD0. */
-  __IO uint32_t PIO2_6;                     /*!< (@ 0x40044088) Configures pin PIO2_6/CT32B0_2/RI0. */
-  __IO uint32_t PIO2_7;                     /*!< (@ 0x4004408C) Configures pin PIO2_7/CT32B0_3/DSR0. */
-  __IO uint32_t PIO0_10;                    /*!< (@ 0x40044090) Configures pin PIO0_10/SCL. */
-  __IO uint32_t PIO0_11;                    /*!< (@ 0x40044094) Configures pin PIO0_11/SDA/CT16B0_0. */
-  __IO uint32_t PIO0_12;                    /*!< (@ 0x40044098) Configures pin PIO0_12/CLKOUT/CT16B0_1. */
-  __IO uint32_t RESET_PIO0_13;              /*!< (@ 0x4004409C) Configures pin RESET/PIO0_13. */
-  __IO uint32_t PIO0_14;                    /*!< (@ 0x400440A0) Configures pin PIO0_14/SSP_CLK. */
-  __IO uint32_t PIO0_15;                    /*!< (@ 0x400440A4) Configures pin PIO0_15/SSP_SSEL/CT16B1_0. */
-  __IO uint32_t PIO0_16;                    /*!< (@ 0x400440A8) Configures pin PIO0_16/SSP_MISO/CT16B1_1. */
-  __IO uint32_t PIO0_17;                    /*!< (@ 0x400440AC) Configures pin PIO0_17/SSP_MOSI. */
-  __IO uint32_t PIO0_18;                    /*!< (@ 0x400440B0) Configures pin PIO0_18/SWCLK/CT32B0_0. */
-  __IO uint32_t R_PIO0_30;                  /*!< (@ 0x400440B4) Configures pin R/PIO0_30/AD0. */
-  __IO uint32_t R_PIO0_31;                  /*!< (@ 0x400440B8) Configures pin R/PIO0_31/AD1. */
-  __IO uint32_t R_PIO1_0;                   /*!< (@ 0x400440BC) Configures pin R/PIO1_0/AD2. */
-  __IO uint32_t R_PIO1_1;                   /*!< (@ 0x400440C0) Configures pin R/PIO1_1/AD3. */
-  __IO uint32_t PIO1_2;                     /*!< (@ 0x400440C4) Configures pin PIO1_2/SWDIO/AD4. */
-  __IO uint32_t PIO1_3;                     /*!< (@ 0x400440C8) Configures pin PIO1_3/AD5/WAKEUP. */
-  __IO uint32_t PIO1_4;                     /*!< (@ 0x400440CC) Configures pin PIO1_4/AD6 */
-  __IO uint32_t PIO1_5;                     /*!< (@ 0x400440D0) Configures pin PIO1_5/AD7/CT16B1_0. */
-  __IO uint32_t PIO1_6;                     /*!< (@ 0x400440D4) Configures pin PIO1_6/CT16B1_1. */
-  __I  uint32_t RESERVED2[2];
-  __IO uint32_t PIO2_8;                     /*!< (@ 0x400440E0) Configures pin PIO2_8/CT32B1_0. */
-  __IO uint32_t PIO2_9;                     /*!< (@ 0x400440E4) Configures pin PIO2_9/CT32B1_1. */
-  __IO uint32_t PIO2_10;                    /*!< (@ 0x400440E8) Configures pin PIO2_10/CT32B1_2/TXD1. */
-  __IO uint32_t PIO2_11;                    /*!< (@ 0x400440EC) Configures pin PIO2_11/CT32B1_3/RXD1. */
-} LPC_IOCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        SYSCON                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x System control (SYSCON) Modification date=2/10/2011 Major revision=1 Minor revision=0  (SYSCON)
-  */
-
-typedef struct {                            /*!< (@ 0x40048000) SYSCON Structure       */
-  __IO uint32_t SYSMEMREMAP;                /*!< (@ 0x40048000) System memory remap    */
-  __IO uint32_t PRESETCTRL;                 /*!< (@ 0x40048004) Peripheral reset control and flash timing overwrite */
-  __IO uint32_t SYSPLLCTRL;                 /*!< (@ 0x40048008) System PLL control     */
-  __I  uint32_t SYSPLLSTAT;                 /*!< (@ 0x4004800C) System PLL status      */
-  __I  uint32_t RESERVED0[4];
-  __IO uint32_t SYSOSCCTRL;                 /*!< (@ 0x40048020) System oscillator control */
-  __IO uint32_t WDTOSCCTRL;                 /*!< (@ 0x40048024) Watchdog oscillator control */
-  __IO uint32_t IRCCTRL;                    /*!< (@ 0x40048028) IRC control            */
-  __I  uint32_t RESERVED1[1];
-  __IO uint32_t SYSRESSTAT;                 /*!< (@ 0x40048030) System reset status register */
-  __I  uint32_t RESERVED2[3];
-  __IO uint32_t SYSPLLCLKSEL;               /*!< (@ 0x40048040) System PLL clock source select */
-  __IO uint32_t SYSPLLCLKUEN;               /*!< (@ 0x40048044) System PLL clock source update enable */
-  __I  uint32_t RESERVED3[10];
-  __IO uint32_t MAINCLKSEL;                 /*!< (@ 0x40048070) Main clock source select */
-  __IO uint32_t MAINCLKUEN;                 /*!< (@ 0x40048074) Main clock source update enable */
-  __IO uint32_t SYSAHBCLKDIV;               /*!< (@ 0x40048078) System AHB clock divider */
-  __I  uint32_t RESERVED4[1];
-  __IO uint32_t SYSAHBCLKCTRL;              /*!< (@ 0x40048080) System AHB clock control */
-  __I  uint32_t RESERVED5[4];
-  __IO uint32_t SSPCLKDIV;                  /*!< (@ 0x40048094) SSP clock divder       */
-  __IO uint32_t UART0CLKDIV;                /*!< (@ 0x40048098) UART0 clock divider    */
-  __IO uint32_t UART1CLKDIV;                /*!< (@ 0x4004809C) UART1 clock divider    */
-  __IO uint32_t RTCCLKDIV;                  /*!< (@ 0x400480A0) RTC clock divider      */
-  __I  uint32_t RESERVED6[15];
-  __IO uint32_t CLKOUTCLKSEL;               /*!< (@ 0x400480E0) CLKOUT clock source select */
-  __IO uint32_t CLKOUTUEN;                  /*!< (@ 0x400480E4) CLKOUT clock source update enable */
-  __IO uint32_t CLKOUTDIV;                  /*!< (@ 0x400480E8) CLKOUT clock divider   */
-  __I  uint32_t RESERVED7[5];
-  __I  uint32_t PIOPORCAP0;                 /*!< (@ 0x40048100) POR captured PIO status 0 */
-  __I  uint32_t PIOPORCAP1;                 /*!< (@ 0x40048104) POR captured PIO status 1 */
-  __I  uint32_t RESERVED8[11];
-  __IO uint32_t IOCONFIGCLKDIV6;            /*!< (@ 0x40048134) Peripheral clock 6 to the IOCONFIG block for programmable glitch filter */
-  __IO uint32_t IOCONFIGCLKDIV5;            /*!< (@ 0x40048138) Peripheral clock 5 to the IOCONFIG block for programmable glitch filter */
-  __IO uint32_t IOCONFIGCLKDIV4;            /*!< (@ 0x4004813C) Peripheral clock 4 to the IOCONFIG block for programmable glitch filter */
-  __IO uint32_t IOCONFIGCLKDIV3;            /*!< (@ 0x40048140) Peripheral clock 3to the IOCONFIG block for programmable glitch filter */
-  __IO uint32_t IOCONFIGCLKDIV2;            /*!< (@ 0x40048144) Peripheral clock 2 to the IOCONFIG block for programmable glitch filter */
-  __IO uint32_t IOCONFIGCLKDIV1;            /*!< (@ 0x40048148) Peripheral clock 1 to the IOCONFIG block for programmable glitch filter */
-  __IO uint32_t IOCONFIGCLKDIV0;            /*!< (@ 0x4004814C) Peripheral clock 0 to the IOCONFIG block for programmable glitch filter */
-  __IO uint32_t BODCTRL;                    /*!< (@ 0x40048150) BOD control            */
-  __IO uint32_t SYSTCKCAL;                  /*!< (@ 0x40048154) System tick counter calibration */
-  __IO uint32_t AHBPRIO;                    /*!< (@ 0x40048158) AHB priority setting   */
-  __I  uint32_t RESERVED9[5];
-  __IO uint32_t IRQLATENCY;                 /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
-  __IO uint32_t INTNMI;                     /*!< (@ 0x40048174) NMI interrupt source configuration control */
-  __I  uint32_t RESERVED10[34];
-  __IO uint32_t STARTAPRP0;                 /*!< (@ 0x40048200) Start logic edge control register 0 */
-  __IO uint32_t STARTERP0;                  /*!< (@ 0x40048204) Start logic signal enable register 0 */
-  __IO uint32_t STARTRSRP0CLR;              /*!< (@ 0x40048208) Start logic reset register 0 */
-  __I  uint32_t STARTSRP0;                  /*!< (@ 0x4004820C) Start logic status register 0 */
-  __IO uint32_t STARTAPRP1;                 /*!< (@ 0x40048210) Start logic edge control register 1; peripheral interrupts */
-  __IO uint32_t STARTERP1;                  /*!< (@ 0x40048214) Start logic signal enable register 1; peripheral interrupts */
-  __IO uint32_t STARTRSRP1CLR;              /*!< (@ 0x40048218) Start logic reset register 1; peripheral interrupts */
-  __I  uint32_t STARTSRP1;                  /*!< (@ 0x4004821C) Start logic status register 1; peripheral interrupts */
-  __I  uint32_t RESERVED11[4];
-  __IO uint32_t PDSLEEPCFG;                 /*!< (@ 0x40048230) Power-down states in Deep-sleep mode */
-  __IO uint32_t PDAWAKECFG;                 /*!< (@ 0x40048234) Power-down states after wake-up from Deep-sleep mode */
-  __IO uint32_t PDRUNCFG;                   /*!< (@ 0x40048238) Power-down configuration register */
-  __I  uint32_t RESERVED12[110];
-  __I  uint32_t DEVICE_ID;                  /*!< (@ 0x400483F4) Device ID              */
-} LPC_SYSCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       MICRO_DMA                                      -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x General purpose micro DMA controller Modification date=2/10/2011 Major revision=0 Minor revision=17  (MICRO_DMA)
-  */
-
-typedef struct {                            /*!< (@ 0x4004C000) MICRO_DMA Structure    */
-  __I  uint32_t DMA_STATUS;                 /*!< (@ 0x4004C000) DMA status register    */
-  __IO uint32_t DMA_CFG;                    /*!< (@ 0x4004C004) DMA configuration register */
-  __IO uint32_t CTRL_BASE_PTR;              /*!< (@ 0x4004C008) Channel control base pointer register */
-  __I  uint32_t ATL_CTRL_BASE_PTR;          /*!< (@ 0x4004C00C) Channel alternate control base pointer register */
-  __I  uint32_t DMA_WAITONREQ_STATUS;       /*!< (@ 0x4004C010) Channel wait on request status register */
-  __IO uint32_t CHNL_SW_REQUEST;            /*!< (@ 0x4004C014) Channel software request register */
-  __IO uint32_t CHNL_USEBURST_SET;          /*!< (@ 0x4004C018) Channel useburst set register */
-  __IO uint32_t CHNL_USEBURST_CLR;          /*!< (@ 0x4004C01C) Channel useburst clear register */
-  __IO uint32_t CHNL_REQ_MASK_SET;          /*!< (@ 0x4004C020) Channel request mask set register */
-  __IO uint32_t CHNL_REQ_MASK_CLR;          /*!< (@ 0x4004C024) Channel request mask clear register */
-  __IO uint32_t CHNL_ENABLE_SET;            /*!< (@ 0x4004C028) Channel enable set register */
-  __IO uint32_t CHNL_ENABLE_CLR;            /*!< (@ 0x4004C02C) Channel enable clear register */
-  __IO uint32_t CHNL_PRI_ALT_SET;           /*!< (@ 0x4004C030) Channel primary-alternate set register */
-  __IO uint32_t CHNL_PRI_ALT_CLR;           /*!< (@ 0x4004C034) Channel primary-alternate clear register */
-  __IO uint32_t CHNL_PRIORITY_SET;          /*!< (@ 0x4004C038) Channel priority set register */
-  __IO uint32_t CHNL_PRIORITY_CLR;          /*!< (@ 0x4004C03C) Channel priority clear register */
-  __I  uint32_t RESERVED0[3];
-  __IO uint32_t ERR_CLR;                    /*!< (@ 0x4004C04C) Bus error clear register */
-  __I  uint32_t RESERVED1[12];
-  __IO uint32_t CHNL_IRQ_STATUS;            /*!< (@ 0x4004C080) Channel DMA interrupt status register */
-  __IO uint32_t IRQ_ERR_ENABLE;             /*!< (@ 0x4004C084) DMA error interrupt enable register */
-  __IO uint32_t CHNL_IRQ_ENABLE;            /*!< (@ 0x4004C088) Channel DMA interrupt enable register */
-} LPC_MICRO_DMA_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          RTC                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x Real-Time Clock (RTC) Modification date=2/11/2011 Major revision=1 Minor revision=0  (RTC)
-  */
-
-typedef struct {                            /*!< (@ 0x40050000) RTC Structure          */
-  __I  uint32_t DR;                         /*!< (@ 0x40050000) Data register          */
-  __IO uint32_t MR;                         /*!< (@ 0x40050004) Match register         */
-  __IO uint32_t LR;                         /*!< (@ 0x40050008) Load register          */
-  __IO uint32_t CR;                         /*!< (@ 0x4005000C) Control register       */
-  __IO uint32_t ICSC;                       /*!< (@ 0x40050010) Interrupt control set/clear register */
-  __I  uint32_t RIS;                        /*!< (@ 0x40050014) Raw interrupt status register */
-  __I  uint32_t MIS;                        /*!< (@ 0x40050018) Masked interrupt status register */
-  __IO uint32_t ICR;                        /*!< (@ 0x4005001C) Interrupt clear register */
-} LPC_RTC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         ACOMP                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x Comparator Modification date=2/11/2011 Major revision=0 Minor revision=17  (ACOMP)
-  */
-
-typedef struct {                            /*!< (@ 0x40054000) ACOMP Structure        */
-  __IO uint32_t CMP;                        /*!< (@ 0x40054000) Comparator control register */
-  __IO uint32_t VLAD;                       /*!< (@ 0x40054004) Voltage ladder register */
-} LPC_ACOMP_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         GPIO0/1/2                                    -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x General Purpose I/O (GPIO) Modification date=2/11/2011 Major revision=0 Minor revision=17  (GPIO0)
-  */
-
-typedef struct {                            /*!< (@ 0x500X0000) GPIO0 Structure        */
-  __IO uint32_t MASK;                       /*!< (@ 0x500X0000) Pin value mask register. Affects operations on PIN, OUT, SET, CLR, and NOT registers. */
-  __I  uint32_t PIN;                        /*!< (@ 0x500X0004) Pin value register.    */
-  __IO uint32_t OUT;                        /*!< (@ 0x500X0008) Pin output value register. */
-  __IO uint32_t SET;                        /*!< (@ 0x500X000C) Pin output value set register. */
-  __IO uint32_t CLR;                        /*!< (@ 0x500X0010) Pin output value clear register. */
-  __IO uint32_t NOT;                        /*!< (@ 0x500X0014) Pin output value invert register. */
-  __I  uint32_t RESERVED0[2];
-  __IO uint32_t DIR;                        /*!< (@ 0x500X0020) Data direction register. */
-  __IO uint32_t IS;                         /*!< (@ 0x500X0024) Interrupt sense register. */
-  __IO uint32_t IBE;                        /*!< (@ 0x500X0028) Interrupt both edges register. */
-  __IO uint32_t IEV;                        /*!< (@ 0x500X002C) Interrupt event register. */
-  __IO uint32_t IE;                         /*!< (@ 0x500X0030) Interrupt mask register. */
-  __I  uint32_t RIS;                        /*!< (@ 0x500X0034) Raw interrupt status register. */
-  __I  uint32_t MIS;                        /*!< (@ 0x500X0038) Masked interrupt status register. */
-  __IO uint32_t IC;                         /*!< (@ 0x5000003C) Interrupt clear register. */
-} LPC_GPIO_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       FLASHCTRL                                      -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x System control (SYSCON) Modification date=2/16/2011 Major revision=1 Minor revision=0  (FLASHCTRL)
-  */
-
-typedef struct {                            /*!< (@ 0x50060000) FLASHCTRL Structure    */
-  __I  uint32_t RESERVED0[10];
-  __IO uint32_t FLASHCFG;                   /*!< (@ 0x50060028) Flash read cycle configuration */
-} LPC_FLASHCTRL_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          CRC                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10441 Chapter title=LPC122x CRC engine Modification date=2/11/2011 Major revision=0 Minor revision=17  (CRC)
-  */
-
-typedef struct {                            /*!< (@ 0x50070000) CRC Structure          */
-  __IO uint32_t MODE;                       /*!< (@ 0x50070000) CRC mode register      */
-  __IO uint32_t SEED;                       /*!< (@ 0x50070004) CRC seed register      */
-  
-  union {
-    union{
-    	__O uint8_t WR_DATA_8;                  /*!< (@ 0x50070008) CRC 8-bit data register      */
-    	__O uint16_t WR_DATA_16;                /*!< (@ 0x50070008) CRC 16-bit data register      */
-    	__O uint32_t WR_DATA_32;                /*!< (@ 0x50070008) CRC 32-bit data register      */
-    };
-    __I  uint32_t SUM;                      /*!< (@ 0x50070008) CRC checksum register  */
-  };
-} LPC_CRC_Type;
-
-
-#if defined ( __CC_ARM   )
-  #pragma no_anon_unions
-#endif
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 Peripheral memory map                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C_BASE              (0x40000000)
-#define LPC_WWDT_BASE             (0x40004000)
-#define LPC_UART0_BASE            (0x40008000)
-#define LPC_UART1_BASE            (0x4000C000)
-#define LPC_CT16B0_BASE           (0x40010000)
-#define LPC_CT16B1_BASE           (0x40014000)
-#define LPC_CT32B0_BASE           (0x40018000)
-#define LPC_CT32B1_BASE           (0x4001C000)
-#define LPC_ADC_BASE              (0x40020000)
-#define LPC_PMU_BASE              (0x40038000)
-#define LPC_SSP_BASE              (0x40040000)
-#define LPC_IOCON_BASE            (0x40044000)
-#define LPC_SYSCON_BASE           (0x40048000)
-#define LPC_MICRO_DMA_BASE        (0x4004C000)
-#define LPC_RTC_BASE              (0x40050000)
-#define LPC_ACOMP_BASE            (0x40054000)
-#define LPC_GPIO0_BASE            (0x50000000)
-#define LPC_GPIO1_BASE            (0x50010000)
-#define LPC_GPIO2_BASE            (0x50020000)
-#define LPC_FLASHCTRL_BASE        (0x50060000)
-#define LPC_CRC_BASE              (0x50070000)
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                Peripheral declaration                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C                   ((LPC_I2C_Type            *) LPC_I2C_BASE)
-#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
-#define LPC_UART0                 ((LPC_UART0_Type          *) LPC_UART0_BASE)
-#define LPC_UART1                 ((LPC_UART1_Type          *) LPC_UART1_BASE)
-#define LPC_CT16B0                ((LPC_CTxxBx_Type         *) LPC_CT16B0_BASE)
-#define LPC_CT16B1                ((LPC_CTxxBx_Type         *) LPC_CT16B1_BASE)
-#define LPC_CT32B0                ((LPC_CTxxBx_Type         *) LPC_CT32B0_BASE)
-#define LPC_CT32B1                ((LPC_CTxxBx_Type         *) LPC_CT32B1_BASE)
-#define LPC_ADC                   ((LPC_ADC_Type            *) LPC_ADC_BASE)
-#define LPC_PMU                   ((LPC_PMU_Type            *) LPC_PMU_BASE)
-#define LPC_SSP                   ((LPC_SSP_Type            *) LPC_SSP_BASE)
-#define LPC_IOCON                 ((LPC_IOCON_Type          *) LPC_IOCON_BASE)
-#define LPC_SYSCON                ((LPC_SYSCON_Type         *) LPC_SYSCON_BASE)
-#define LPC_MICRO_DMA             ((LPC_MICRO_DMA_Type      *) LPC_MICRO_DMA_BASE)
-#define LPC_RTC                   ((LPC_RTC_Type            *) LPC_RTC_BASE)
-#define LPC_ACOMP                 ((LPC_ACOMP_Type          *) LPC_ACOMP_BASE)
-#define LPC_GPIO0                 ((LPC_GPIO_Type          	*) LPC_GPIO0_BASE)
-#define LPC_GPIO1                 ((LPC_GPIO_Type          	*) LPC_GPIO1_BASE)
-#define LPC_GPIO2                 ((LPC_GPIO_Type          	*) LPC_GPIO2_BASE)
-#define LPC_FLASHCTRL             ((LPC_FLASHCTRL_Type      *) LPC_FLASHCTRL_BASE)
-#define LPC_CRC                   ((LPC_CRC_Type            *) LPC_CRC_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group (null) */
-/** @} */ /* End of group LPC122x */
-
-#ifdef __cplusplus
-}
-#endif 
-
-
-#endif  // __LPC122X_H__
diff --git a/os/hal/platforms/LPC122x/ext_lld.c b/os/hal/platforms/LPC122x/ext_lld.c
deleted file mode 100644
index 553ae9b5c..000000000
--- a/os/hal/platforms/LPC122x/ext_lld.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/ext_lld.c
- * @brief   LPC122x EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTD0 driver identifier.
- */
-#if LPC122x_EXT_USE_EXT0 || defined(__DOXYGEN__)
-EXTDriver EXTD0;
-#endif
-
-/**
- * @brief   EXTD1 driver identifier.
- */
-#if LPC122x_EXT_USE_EXT1 || defined(__DOXYGEN__)
-EXTDriver EXTD1;
-#endif
-
-/**
- * @brief   EXTD2 driver identifier.
- */
-#if LPC122x_EXT_USE_EXT2 || defined(__DOXYGEN__)
-EXTDriver EXTD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
-  /* Driver initialization.*/
-#if LPC122x_EXT_USE_EXT0
-  extObjectInit(&EXTD0);
-  EXTD0.gpio = LPC_GPIO0;
-#endif
-
-#if LPC122x_EXT_USE_EXT1
-  extObjectInit(&EXTD1);
-  EXTD1.gpio = LPC_GPIO1;
-#endif
-
-#if LPC122x_EXT_USE_EXT2
-  extObjectInit(&EXTD2);
-  EXTD2.gpio = LPC_GPIO2;
-#endif
-}
-
-/**
- * @brief   Configures and activates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
-  int i;
-
-  /* Configure all pins as edge sensitive */
-#if LPC122x_EXT_USE_EXT0
-  if (extp == &EXTD0) {
-    LPC_GPIO0->IS = 0;
-    ext_lld_exti_irq_enable(EXTI0_IRQ);
-  }
-#endif
-
-#if LPC122x_EXT_USE_EXT1
-  if (extp == &EXTD1) {
-    LPC_GPIO1->IS = 0;
-    ext_lld_exti_irq_enable(EXTI1_IRQ);
-  }
-#endif
-
-#if LPC122x_EXT_USE_EXT2
-  if (extp == &EXTD2) {
-    LPC_GPIO2->IS = 0;
-    ext_lld_exti_irq_enable(EXTI2_IRQ);
-  }
-#endif
-
-  /* Configuration of autostart channels.*/
-  for (i = 0; i < EXT_MAX_CHANNELS; i++)
-    if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
-      ext_lld_channel_enable(extp, i);
-    else
-      ext_lld_channel_disable(extp, i);
-}
-
-/**
- * @brief   Deactivates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-
-  LPC_GPIO_Type * gp = extp->gpio;
-
-  if (extp->state == EXT_ACTIVE) {
-#if LPC122x_EXT_USE_EXT0
-    if (extp == &EXTD0) {
-      ext_lld_exti_irq_disable(EXTI0_IRQ);
-    }
-#endif
-
-#if LPC122x_EXT_USE_EXT1
-    if (extp == &EXTD1) {
-      ext_lld_exti_irq_disable(EXTI1_IRQ);
-    }
-#endif
-
-#if LPC122x_EXT_USE_EXT2
-    if (extp == &EXTD2) {
-      ext_lld_exti_irq_disable(EXTI2_IRQ);
-    }
-#endif
-  }
-
-  gp->IE = 0;
-  gp->IC = 0xFFFFFFFF;
-  __NOP();
-  __NOP();
-}
-
-/**
- * @brief   Enables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
-  LPC_GPIO_Type * gp;
-
-  gp = extp->gpio;
-  
-  /* Programming edge irq enables */
-  if (extp->config->channels[channel].mode & EXT_CH_MODE_BOTH_EDGES)
-    gp->IBE |=  (1 << channel);
-  else {
-    gp->IBE &=  ~(1 << channel);
-    if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
-      gp->IEV |= (1 << channel);
-    else
-      gp->IEV &= (1 << channel);
-  }
-
-  gp->IC = (1 << channel);    /* Clear interrupt on selected channel */
-  __NOP();
-  __NOP();
-
-  gp->IE |= (1 << channel);  /* Interrupt on selected channel
-                                    is not masked */
-}
-
-/**
- * @brief   Disables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-
-  LPC_GPIO_Type * gp;
-
-  gp = extp->gpio;
-
-  gp->IE &= ~(1 << channel);   /* Mask interrupt on selected channel */
-  gp->IC = (1 << channel);     /* Clear interrupt on selected channel */
-  __NOP();
-  __NOP();
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/ext_lld.h b/os/hal/platforms/LPC122x/ext_lld.h
deleted file mode 100644
index 89e720494..000000000
--- a/os/hal/platforms/LPC122x/ext_lld.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/ext_lld.h
- * @brief   LPC122x EXT subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_H_
-#define _EXT_LLD_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Available number of EXT channels.
- */
-#define EXT_MAX_CHANNELS    32
-
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT0 driver enable switch.
- * @details If set to @p TRUE the support for EXT1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_EXT_USE_EXT0) || defined(__DOXYGEN__)
-#define LPC122x_EXT_USE_EXT0              FALSE
-#endif
-
-/**
- * @brief   EXT1 driver enable switch.
- * @details If set to @p TRUE the support for EXT1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_EXT_USE_EXT1) || defined(__DOXYGEN__)
-#define LPC122x_EXT_USE_EXT1              FALSE
-#endif
-
-/**
- * @brief   EXT2 driver enable switch.
- * @details If set to @p TRUE the support for EXT1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_EXT_USE_EXT2) || defined(__DOXYGEN__)
-#define LPC122x_EXT_USE_EXT2              FALSE
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief   Type of an EXT generic notification callback.
- *
- * @param[in] extp      pointer to the @p EXPDriver object triggering the
- *                      callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief   Channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel mode.
-   */
-  uint8_t               mode;
-
-  /**
-   * @brief Channel callback.
-   */
-  extcallback_t         cb;
-} EXTChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief Channel configurations.
-   */
-  EXTChannelConfig      channels[EXT_MAX_CHANNELS];
-  /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief   Structure representing an EXT driver.
- */
-struct EXTDriver {
-  /**
-   * @brief Driver state.
-   */
-  extstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const EXTConfig           *config;
-  /* End of the mandatory fields.*/
-  LPC_GPIO_Type             *gpio;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC122x_EXT_USE_EXT0 || !defined(__DOXYGEN__)
-extern EXTDriver EXTD0;
-#endif
-
-#if LPC122x_EXT_USE_EXT1 || !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#if LPC122x_EXT_USE_EXT2 || !defined(__DOXYGEN__)
-extern EXTDriver EXTD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_init(void);
-  void ext_lld_start(EXTDriver *extp);
-  void ext_lld_stop(EXTDriver *extp);
-  void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
-  void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/ext_lld_isr.c b/os/hal/platforms/LPC122x/ext_lld_isr.c
deleted file mode 100644
index e8ad6f841..000000000
--- a/os/hal/platforms/LPC122x/ext_lld_isr.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/ext_lld_isr.c
- * @brief   LPC122x EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if LPC122x_EXT_USE_EXT0 || LPC122x_EXT_USE_EXT1 || LPC122x_EXT_USE_EXT2 ||   \
-  defined(__DOXYGEN__)
-/**
- * @brief   I2C error handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void ext_lld_serve_interrupt(EXTDriver *extp) {
-  uint32_t port_stat;
-  uint8_t i;
-
-  port_stat = extp->gpio->MIS;   /* Read interrupt status */
-  extp->gpio->IC = port_stat;    /* Clear interrupt flags */
-
-  for (i = 0; i < EXT_MAX_CHANNELS; i++) {
-    if (port_stat & 0x01) {
-      extp->config->channels[i].cb(extp, i);
-    }
-    port_stat  = port_stat >> 1;
-  }
-}
-#endif
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC122x_EXT_USE_EXT0 || defined(__DOXYGEN__)
-/**
- * @brief   PIO0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorA4) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_serve_interrupt(&EXTD0);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC122x_EXT_USE_EXT1 || defined(__DOXYGEN__)
-/**
- * @brief   PIO1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorA8) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_serve_interrupt(&EXTD1);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC122x_EXT_USE_EXT2 || defined(__DOXYGEN__)
-/**
- * @brief   PIO2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorAC) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_serve_interrupt(&EXTD2);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(extirq_t irqn) {
-
-  uint32_t pmask;
-
-  switch (irqn) {
-  case EXTI0_IRQ:
-    pmask = LPC122x_EXT_EXTI0_IRQ_PRIORITY;
-    break;
-  case EXTI1_IRQ:
-    pmask = LPC122x_EXT_EXTI1_IRQ_PRIORITY;
-    break;
-  case EXTI2_IRQ:
-    pmask = LPC122x_EXT_EXTI2_IRQ_PRIORITY;
-    break;
-  }
-  nvicEnableVector(EINT0_IRQn + irqn, CORTEX_PRIORITY_MASK(pmask));
-
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(extirq_t irqn) {
-
-  nvicDisableVector(EINT0_IRQn + irqn);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/ext_lld_isr.h b/os/hal/platforms/LPC122x/ext_lld_isr.h
deleted file mode 100644
index a201cce9b..000000000
--- a/os/hal/platforms/LPC122x/ext_lld_isr.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x EXT driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/ext_lld_isr.h
- * @brief   LPC122x EXT subsystem low level driver ISR header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_ISR_H_
-#define _EXT_LLD_ISR_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define EXTI0_IRQ           0
-#define EXTI1_IRQ           1
-#define EXTI2_IRQ           2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   EXTI0 interrupt priority level setting.
- */
-#if !defined(LPC122x_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_EXT_EXTI0_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI1 interrupt priority level setting.
- */
-#if !defined(LPC122x_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_EXT_EXTI1_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI2 interrupt priority level setting.
- */
-#if !defined(LPC122x_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_EXT_EXTI2_IRQ_PRIORITY      3
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT irq port identifier.
- */
-typedef uint32_t extirq_t;
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_exti_irq_enable(extirq_t irqn);
-  void ext_lld_exti_irq_disable(extirq_t irqn);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_ISR_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/gpt_lld.c b/os/hal/platforms/LPC122x/gpt_lld.c
deleted file mode 100644
index 86ea73759..000000000
--- a/os/hal/platforms/LPC122x/gpt_lld.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/gpt_lld.c
- * @brief   LPC122x GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver identifier.
- * @note    The driver GPT1 allocates the complex timer CT16B0 when enabled.
- */
-#if LPC122x_GPT_USE_CT16B0 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief   GPT2 driver identifier.
- * @note    The driver GPT2 allocates the timer CT16B1 when enabled.
- */
-#if LPC122x_GPT_USE_CT16B1 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief   GPT3 driver identifier.
- * @note    The driver GPT3 allocates the timer CT32B0 when enabled.
- */
-#if LPC122x_GPT_USE_CT32B0 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/**
- * @brief   GPT4 driver identifier.
- * @note    The driver GPT4 allocates the timer CT32B1 when enabled.
- */
-#if LPC122x_GPT_USE_CT32B1 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
-  gptp->tmr->IR = 1;                        /* Clear interrupt on match MR0.*/
-  if (gptp->state == GPT_ONESHOT) {
-    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
-    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
-  }
-  gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC122x_GPT_USE_CT16B0
-/**
- * @brief   CT16B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector74) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC122x_GPT_USE_CT16B0 */
-
-#if LPC122x_GPT_USE_CT16B1
-/**
- * @brief   CT16B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector78) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC122x_GPT_USE_CT16B0 */
-
-#if LPC122x_GPT_USE_CT32B0
-/**
- * @brief   CT32B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector7C) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC122x_GPT_USE_CT32B0 */
-
-#if LPC122x_GPT_USE_CT32B1
-/**
- * @brief   CT32B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector80) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC122x_GPT_USE_CT32B1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if LPC122x_GPT_USE_CT16B0
-  /* Driver initialization.*/
-  GPTD1.tmr = LPC_CT16B0;
-  gptObjectInit(&GPTD1);
-#endif
-
-#if LPC122x_GPT_USE_CT16B1
-  /* Driver initialization.*/
-  GPTD2.tmr = LPC_CT16B1;
-  gptObjectInit(&GPTD2);
-#endif
-
-#if LPC122x_GPT_USE_CT32B0
-  /* Driver initialization.*/
-  GPTD3.tmr = LPC_CT32B0;
-  gptObjectInit(&GPTD3);
-#endif
-
-#if LPC122x_GPT_USE_CT32B1
-  /* Driver initialization.*/
-  GPTD4.tmr = LPC_CT32B1;
-  gptObjectInit(&GPTD4);
-#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-  uint32_t pr;
-
-  if (gptp->state == GPT_STOP) {
-    /* Clock activation.*/
-#if LPC122x_GPT_USE_CT16B0
-    if (&GPTD1 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7);
-      nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC122x_GPT_USE_CT16B1
-    if (&GPTD2 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
-      nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3));
-    }
-#endif
-#if LPC122x_GPT_USE_CT32B0
-    if (&GPTD3 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9);
-      nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC122x_GPT_USE_CT32B1
-    if (&GPTD4 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
-      nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-  }
-
-  /* Prescaler value calculation.*/
-  pr = (uint16_t)((LPC122x_SYSCLK / gptp->config->frequency) - 1);
-  chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC122x_SYSCLK,
-              "gpt_lld_start(), #1", "invalid frequency");
-
-  /* Timer configuration.*/
-  gptp->tmr->PR  = pr;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
-  if (gptp->state == GPT_READY) {
-    gptp->tmr->MCR = 0;
-    gptp->tmr->TCR = 0;
-
-#if LPC122x_GPT_USE_CT16B0
-    if (&GPTD1 == gptp) {
-      nvicDisableVector(TIMER_16_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
-    }
-#endif
-#if LPC122x_GPT_USE_CT16B1
-    if (&GPTD2 == gptp) {
-      nvicDisableVector(TIMER_16_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
-    }
-#endif
-#if LPC122x_GPT_USE_CT32B0
-    if (&GPTD3 == gptp) {
-      nvicDisableVector(TIMER_32_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
-    }
-#endif
-#if LPC122x_GPT_USE_CT32B1
-    if (&GPTD4 == gptp) {
-      nvicDisableVector(TIMER_32_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 3;                       /* IRQ and clr TC on match MR0. */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 4;                       /* Stop TC on match MR0.        */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-  while (gptp->tmr->TCR & 1)
-    ;
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/gpt_lld.h b/os/hal/platforms/LPC122x/gpt_lld.h
deleted file mode 100644
index e38fe17c1..000000000
--- a/os/hal/platforms/LPC122x/gpt_lld.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/gpt_lld.h
- * @brief   LPC122x GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver enable switch.
- * @details If set to @p TRUE the support for GPT1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC122x_GPT_USE_CT16B0) || defined(__DOXYGEN__)
-#define LPC122x_GPT_USE_CT16B0              TRUE
-#endif
-
-/**
- * @brief   GPT2 driver enable switch.
- * @details If set to @p TRUE the support for GPT2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC122x_GPT_USE_CT16B1) || defined(__DOXYGEN__)
-#define LPC122x_GPT_USE_CT16B1              TRUE
-#endif
-
-/**
- * @brief   GPT3 driver enable switch.
- * @details If set to @p TRUE the support for GPT3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC122x_GPT_USE_CT32B0) || defined(__DOXYGEN__)
-#define LPC122x_GPT_USE_CT32B0              TRUE
-#endif
-
-/**
- * @brief   GPT4 driver enable switch.
- * @details If set to @p TRUE the support for GPT4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC122x_GPT_USE_CT32B1) || defined(__DOXYGEN__)
-#define LPC122x_GPT_USE_CT32B1              TRUE
-#endif
-
-/**
- * @brief   GPT1 interrupt priority level setting.
- */
-#if !defined(LPC122x_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_GPT_CT16B0_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT2 interrupt priority level setting.
- */
-#if !defined(LPC122x_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_GPT_CT16B1_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT3 interrupt priority level setting.
- */
-#if !defined(LPC122x_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_GPT_CT32B0_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT4 interrupt priority level setting.
- */
-#if !defined(LPC122x_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_GPT_CT32B1_IRQ_PRIORITY     2
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !LPC122x_GPT_USE_CT16B0 && !LPC122x_GPT_USE_CT16B1 &&                   \
-    !LPC122x_GPT_USE_CT32B0 && !LPC122x_GPT_USE_CT32B1
-#error "GPT driver activated but no CT peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the CTxxBy registers block.
-   */
-  LPC_CTxxBx_Type           *tmr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC122x_GPT_USE_CT16B0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if LPC122x_GPT_USE_CT16B1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if LPC122x_GPT_USE_CT32B0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#if LPC122x_GPT_USE_CT32B1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/hal_lld.c b/os/hal/platforms/LPC122x/hal_lld.c
deleted file mode 100644
index 9069434ba..000000000
--- a/os/hal/platforms/LPC122x/hal_lld.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/hal_lld.c
- * @brief   LPC122x HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* SysTick initialization using the system clock.*/
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
-  SysTick->LOAD = LPC122x_SYSCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
- * @brief   LPC122x clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void lpc122x_clock_init(void) {
-  unsigned i;
-
-  LPC_WWDT->MOD = 0;                          /* Disable Watchdog */
-  LPC_WWDT->FEED = 0xAA;
-  LPC_WWDT->FEED = 0x55;
-
-#if LPC122x_FLASHCFG_FLASHTIM == 0
-  LPC_SYSCON->PRESETCTRL |= (1 << 15);         /* Flash 1-cycle read mode */
-#else
-  LPC_FLASHCTRL->FLASHCFG = 0;                 /* 2 system clock cycles flash access time */
-  LPC_SYSCON->PRESETCTRL &= ~(1 << 15);        /* Flash multi-cycle read mode */
-#endif
-
-  /* System oscillator initialization if required.*/
-#if LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-#if LPC122x_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC
-  LPC_SYSCON->SYSOSCCTRL = LPC122x_SYSOSCCTRL;
-  LPC_SYSCON->PDRUNCFG &= ~(1 << 5);            /* System oscillator ON.    */
-  for (i = 0; i < 200; i++)
-    __NOP();                                    /* Stabilization delay.     */
-#endif /* LPC122x_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */
-
-  /* PLL initialization if required.*/
-  LPC_SYSCON->SYSPLLCLKSEL = LPC122x_PLLCLK_SOURCE;
-  LPC_SYSCON->SYSPLLCLKUEN = 1;                 /* Really required?         */
-  LPC_SYSCON->SYSPLLCLKUEN = 0;
-  LPC_SYSCON->SYSPLLCLKUEN = 1;
-  LPC_SYSCON->SYSPLLCTRL = LPC122x_SYSPLLCTRL_MSEL | LPC122x_SYSPLLCTRL_PSEL;
-  LPC_SYSCON->PDRUNCFG &= ~(1 << 7);            /* System PLL ON.           */
-  while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0)     /* Wait PLL lock.           */
-    ;
-#endif /* LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */
-
-  /* Main clock source selection.*/
-  LPC_SYSCON->MAINCLKSEL = LPC122x_MAINCLK_SOURCE;
-  LPC_SYSCON->MAINCLKUEN = 1;                   /* Really required?         */
-  LPC_SYSCON->MAINCLKUEN = 0;
-  LPC_SYSCON->MAINCLKUEN = 1;
-  while ((LPC_SYSCON->MAINCLKUEN & 1) == 0)     /* Wait switch completion.  */
-    ;
-
-  /* ABH divider initialization, peripheral clocks are initially disabled,
-     the various device drivers will handle their own setup except GPIO and
-     IOCON that are left enabled.*/
-  LPC_SYSCON->SYSAHBCLKDIV = LPC122x_SYSABHCLK_DIV;
-  LPC_SYSCON->SYSAHBCLKCTRL = 0xE009001F;
-
-  /* Memory remapping, vectors always in ROM.*/
-  LPC_SYSCON->SYSMEMREMAP = 2;
-}
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/hal_lld.h b/os/hal/platforms/LPC122x/hal_lld.h
deleted file mode 100644
index 35624962a..000000000
--- a/os/hal/platforms/LPC122x/hal_lld.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/hal_lld.h
- * @brief   HAL subsystem low level driver header template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "LPC122x.h"
-#include "nvic.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME           "LPC122x"
-
-#define IRCOSCCLK               12000000    /**< High speed internal clock. */
-#define WDGOSCCLK               1600000     /**< Watchdog internal clock.   */
-
-#define SYSPLLCLKSEL_IRCOSC     0           /**< Internal RC oscillator
-                                                 clock source.              */
-#define SYSPLLCLKSEL_SYSOSC     1           /**< System oscillator clock
-                                                 source.                    */
-
-#define SYSMAINCLKSEL_IRCOSC    0           /**< Clock source is IRC.       */
-#define SYSMAINCLKSEL_PLLIN     1           /**< Clock source is PLLIN.     */
-#define SYSMAINCLKSEL_WDGOSC    2           /**< Clock source is WDGOSC.    */
-#define SYSMAINCLKSEL_PLLOUT    3           /**< Clock source is PLLOUT.    */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   System PLL clock source.
- */
-#if !defined(LPC122x_PLLCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC122x_PLLCLK_SOURCE               SYSPLLCLKSEL_SYSOSC
-#endif
-
-/**
- * @brief   System PLL multiplier.
- * @note    The value must be in the 1..32 range and the final frequency
- *          must not exceed the CCO ratings.
- */
-#if !defined(LPC122x_SYSPLL_MUL) || defined(__DOXYGEN__)
-#define LPC122x_SYSPLL_MUL                  2
-#endif
-
-/**
- * @brief   System PLL divider.
- * @note    The value must be chosen between (2, 4, 8, 16).
- */
-#if !defined(LPC122x_SYSPLL_DIV) || defined(__DOXYGEN__)
-#define LPC122x_SYSPLL_DIV                  8
-#endif
-
-/**
- * @brief   System main clock source.
- */
-#if !defined(LPC122x_MAINCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC122x_MAINCLK_SOURCE              SYSMAINCLKSEL_PLLOUT
-#endif
-
-/**
- * @brief   AHB clock divider.
- * @note    The value must be chosen between (1...255).
- */
-#if !defined(LPC122x_SYSCLK_DIV) || defined(__DOXYGEN__)
-#define LPC122x_SYSABHCLK_DIV               1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Calculated SYSOSCCTRL setting.
- */
-#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__)
-#define LPC122x_SYSOSCCTRL      0
-#else
-#define LPC122x_SYSOSCCTRL      1
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (LPC122x_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
-#define LPC122x_SYSPLLCLKIN     SYSOSCCLK
-#elif LPC122x_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC
-#define LPC122x_SYSPLLCLKIN     IRCOSCCLK
-#else
-#error "invalid LPC122x_PLLCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   MSEL mask in SYSPLLCTRL register.
- */
-#if (LPC122x_SYSPLL_MUL >= 1) && (LPC122x_SYSPLL_MUL <= 32) ||              \
-    defined(__DOXYGEN__)
-#define LPC122x_SYSPLLCTRL_MSEL (LPC122x_SYSPLL_MUL - 1)
-#else
-#error "LPC122x_SYSPLL_MUL out of range (1...32)"
-#endif
-
-/**
- * @brief   PSEL mask in SYSPLLCTRL register.
- */
-#if (LPC122x_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
-#define LPC122x_SYSPLLCTRL_PSEL (0 << 5)
-#elif LPC122x_SYSPLL_DIV == 4
-#define LPC122x_SYSPLLCTRL_PSEL (1 << 5)
-#elif LPC122x_SYSPLL_DIV == 8
-#define LPC122x_SYSPLLCTRL_PSEL (2 << 5)
-#elif LPC122x_SYSPLL_DIV == 16
-#define LPC122x_SYSPLLCTRL_PSEL (3 << 5)
-#else
-#error "invalid LPC122x_SYSPLL_DIV value (2,4,8,16)"
-#endif
-
-/**
- * @brief   CCP frequency.
- */
-#define  LPC122x_SYSPLLCCO   (LPC122x_SYSPLLCLKIN * LPC122x_SYSPLL_MUL *    \
-                              LPC122x_SYSPLL_DIV)
-
-#if (LPC122x_SYSPLLCCO < 156000000) || (LPC122x_SYSPLLCCO > 320000000)
-#error "CCO frequency out of the acceptable range (156...320)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define  LPC122x_SYSPLLCLKOUT   (LPC122x_SYSPLLCCO / LPC122x_SYSPLL_DIV)
-
-#if (LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__)
-#define LPC122x_MAINCLK     IRCOSCCLK
-#elif LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
-#define LPC122x_MAINCLK     LPC122x_SYSPLLCLKIN
-#elif LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
-#define LPC122x_MAINCLK     WDGOSCCLK
-#elif LPC122x_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-#define LPC122x_MAINCLK     LPC122x_SYSPLLCLKOUT
-#else
-#error "invalid LPC122x_MAINCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   AHB clock.
- */
-#define  LPC122x_SYSCLK     (LPC122x_MAINCLK / LPC122x_SYSABHCLK_DIV)
-#if LPC122x_SYSCLK > 45000000
-#error "AHB clock frequency out of the acceptable range (45MHz max)"
-#endif
-
-/**
- * @brief   Flash wait states.
- */
-#if (LPC122x_SYSCLK <= 30000000) || defined(__DOXYGEN__)
-#define LPC122x_FLASHCFG_FLASHTIM   0
-#else
-#define LPC122x_FLASHCFG_FLASHTIM   1
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void lpc122x_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/i2c_lld.c b/os/hal/platforms/LPC122x/i2c_lld.c
deleted file mode 100644
index 32055d4c2..000000000
--- a/os/hal/platforms/LPC122x/i2c_lld.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x I2C driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-
-/**
- * @file    LPC122x/i2c_lld.h
- * @brief   LPC122x I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief I2C1 driver identifier.*/
-I2CDriver I2CD1;
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Wakes up the waiting thread.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] msg       wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((i2cp)->thread != NULL) {                                             \
-    Thread *tp = (i2cp)->thread;                                            \
-    (i2cp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = (msg);                                                 \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
-}
-
-/**
- * @brief   Handling of stalled I2C transactions.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_safety_timeout(void *p) {
-  I2CDriver *i2cp = (I2CDriver *)p;
-
-  chSysLockFromIsr();
-  if (i2cp->thread) {
-    Thread *tp = i2cp->thread;
-    i2cp->thread = NULL;
-    tp->p_u.rdymsg = RDY_TIMEOUT;
-    chSchReadyI(tp);
-  }
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   I2C error handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t status) {
-  i2cflags_t error = 0;
-
-  switch (status) {
-    case I2C_STATE_ARB_LOST:
-      error = I2CD_ARBITRATION_LOST;
-      break;
-    case I2C_STATE_BUS_ERROR:
-      error = I2CD_BUS_ERROR;
-      break;
-    case I2C_STATE_MS_SLAR_NACK:
-    case I2C_STATE_MS_TDAT_NACK:
-    case I2C_STATE_MS_SLAW_NACK:
-      error = I2CD_ACK_FAILURE ;
-      break;
-  }
-
-  /* If some error has been identified then sends wakes the waiting thread.*/
-  i2cp->errors = error;
-  wakeup_isr(i2cp, RDY_RESET);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-/**
- * @brief   I2C1 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(Vector70) {
-  uint32_t status;
-
-  CH_IRQ_PROLOGUE();
-  status = LPC_I2C->STAT;
-  switch(status) {
-    case I2C_STATE_MS_START:    /*  A START condition has been transmitted. */
-      if (I2CD1.txbytes > 0) {
-        LPC_I2C->DAT = I2CD1.addr;                  /* Write slave address with WR bit. */
-      }
-      else {
-        LPC_I2C->DAT = I2CD1.addr | I2C_RD_BIT;     /* Write slave address with RD bit. */
-      }
-
-      LPC_I2C->CONCLR = I2C_CONCLR_STAC | I2C_CONCLR_SIC;   /* Clear START and SI bit. */
-      break;
-
-    case I2C_STATE_MS_SLAR_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */
-    case I2C_STATE_MS_TDAT_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */
-    case I2C_STATE_MS_SLAW_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */
-      LPC_I2C->CONSET = I2C_CONSET_STO;             /* Set STOP bit. */
-      LPC_I2C->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      i2c_lld_serve_error_interrupt(&I2CD1, status);
-      break;
-
-    case I2C_STATE_MS_SLAW_ACK: /* SLA + W has been transmitted, ACK has been received. */
-    case I2C_STATE_MS_TDAT_ACK: /* Data byte has been transmitted, ACK has been received. */
-      if (I2CD1.txbytes > 0) {
-        LPC_I2C->DAT = *I2CD1.txbuf++;               /* Write data. */
-        I2CD1.txbytes--;
-      }
-      else {
-        if (I2CD1.rxbytes > 0) {
-          LPC_I2C->CONSET = I2C_CONSET_STO | I2C_CONSET_STA; /* Set START and STOP bit. */
-        }                                                    /* STOP bit will be transmit, then START bit. */
-        else {
-          LPC_I2C->CONSET = I2C_CONSET_STO;         /* Set STOP bit. */
-          wakeup_isr(&I2CD1, RDY_OK);
-        }
-      }
-      LPC_I2C->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      break;
-
-    case I2C_STATE_MS_SLAR_ACK: /* SLA + R has been transmitted, ACK has been received. */
-    case I2C_STATE_MS_RDAT_ACK: /* Data byte has been received, ACK has been returned. */
-      if (status == I2C_STATE_MS_RDAT_ACK) {
-        *I2CD1.rxbuf++ = LPC_I2C->DAT;                /* Read data */
-        I2CD1.rxbytes--;
-      }
-      if (I2CD1.rxbytes == 1) {
-        LPC_I2C->CONCLR = I2C_CONCLR_SIC | I2C_CONCLR_AAC; /* Clear SI and ACK bit. */
-      }
-      else {
-        LPC_I2C->CONSET = I2C_CONSET_AA;            /* Set ACK bit. */
-        LPC_I2C->CONCLR = I2C_CONCLR_SIC;           /* Clear SI bit. */
-      }
-      break;
-
-    case I2C_STATE_MS_RDAT_NACK: /* Data byte has been received, NOT ACK has been returned. */
-      *I2CD1.rxbuf++ = LPC_I2C->DAT;                /* Read data. */
-      I2CD1.rxbytes--;
-      LPC_I2C->CONSET = I2C_CONSET_STO;             /* Set STOP bit. */
-      LPC_I2C->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      wakeup_isr(&I2CD1, RDY_OK);
-      break;
-
-    case I2C_STATE_BUS_ERROR: /* Bus error. */
-    case I2C_STATE_ARB_LOST:  /* Arbitration lost. */
-      LPC_I2C->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      i2c_lld_serve_error_interrupt(&I2CD1, status);
-      break;
-
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-  i2cObjectInit(&I2CD1);
-  I2CD1.thread = NULL;
-  I2CD1.i2c    = LPC_I2C;
-
-  LPC_IOCON->PIO0_10 = 0x0482;  /* Set I2C SCL pin function */
-  LPC_IOCON->PIO0_11 = 0x0482;  /* Set I2C SDA pin function */
-}
-
-/**
- * @brief   Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-  uint32_t i2cscl;
-  uint32_t mulh, mull, div;
-  LPC_I2C_Type *dp = i2cp->i2c;
-
-  /* Make sure I2C peripheral is disabled */
-  dp->CONCLR = I2C_CONCLR_ENC;
-
-  /* If in stopped state then enables the I2C clock. */
-  if (i2cp->state == I2C_STOP) {
-
-  if (&I2CD1 == i2cp) {
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5); /* Enable clock. */
-    LPC_SYSCON->PRESETCTRL &= ~(1 << 1);   /* Reset I2C peripheral.*/
-    __NOP();
-    LPC_SYSCON->PRESETCTRL |= (1 << 1);
-    nvicEnableVector(I2C_IRQn,
-          CORTEX_PRIORITY_MASK(LPC122x_I2C_IRQ_PRIORITY));
-  }
-
-  }
-
-  /* Setup I2C clock parameters.*/
-  i2cscl = (LPC122x_SYSCLK/(i2cp->config->clock_timing));
-  if (i2cp->config->mode == I2C_FAST_MODE) {
-    div = 19;
-    mull = 13;
-    mulh = 6;
-  } else if (i2cp->config->mode == I2C_FAST_MODE_PLUS) {
-    div = 3;
-    mull = 2;
-    mulh = 1;
-  } else { /* i2cp->config->mode == I2C_STANDARD_MODE */
-    div = 2;
-    mull = 1;
-    mulh = 1;
-  }
-
-  dp->SCLH = (mulh * i2cscl) / div;
-  dp->SCLL = (mull *i2cscl) / div;
-
-  /* Enable I2C.*/
-  dp->CONSET |= I2C_CONSET_EN;
-}
-
-/**
- * @brief   Deactivates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
-  /* If not in stopped state then disables the I2C clock.*/
-  if (i2cp->state != I2C_STOP) {
-
-    /* I2C disable.*/
-    i2cp->i2c->CONCLR = I2C_CONCLR_ENC;
-
-    if (&I2CD1 == i2cp) {
-      nvicDisableVector(I2C_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 5);
-    }
-  }
-}
-
-/**
- * @brief   Receives data via the I2C bus as master.
- * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
- *          hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                     uint8_t *rxbuf, size_t rxbytes,
-                                     systime_t timeout) {
-  LPC_I2C_Type *dp = i2cp->i2c;
-  VirtualTimer vt;
-
-  i2cp->addr = addr << 1;
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Initializes driver fields */
-  i2cp->errors = 0;
-  i2cp->rxbuf = rxbuf;
-  i2cp->rxbytes = rxbytes;
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Starts the operation.*/
-  dp->CONSET = I2C_CONSET_STA;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief   Transmits data via the I2C bus as master.
- * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
- *          This is hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[in] txbuf     pointer to the transmit buffer
- * @param[in] txbytes   number of bytes to be transmitted
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                      const uint8_t *txbuf, size_t txbytes,
-                                      uint8_t *rxbuf, size_t rxbytes,
-                                      systime_t timeout) {
-  LPC_I2C_Type *dp = i2cp->i2c;
-  VirtualTimer vt;
-
-  i2cp->addr = addr << 1;
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Initializes driver fields */
-  i2cp->errors = 0;
-  i2cp->txbuf = txbuf;
-  i2cp->txbytes = txbytes;
-  i2cp->rxbuf = rxbuf;
-  i2cp->rxbytes = rxbytes;
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Starts the operation.*/
-  dp->CONSET = I2C_CONSET_STA;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/i2c_lld.h b/os/hal/platforms/LPC122x/i2c_lld.h
deleted file mode 100644
index edff13a95..000000000
--- a/os/hal/platforms/LPC122x/i2c_lld.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x I2C driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    LPC122x/i2c_lld.h
- * @brief   LPC122x I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define I2C_CONSET_AA               0x04  /* Assert acknowledge flag. */
-#define I2C_CONSET_SI               0x08  /* I2C interrupt flag. */
-#define I2C_CONSET_STO              0x10  /* STOP flag. */
-#define I2C_CONSET_STA              0x20  /* START flag. */
-#define I2C_CONSET_EN               0x40  /* I2C interface enable. */
-
-#define I2C_CONCLR_AAC              0x04  /* Assert acknowledge Clear bit. */
-#define I2C_CONCLR_SIC              0x08  /* I2C interrupt Clear bit. */
-#define I2C_CONCLR_STAC             0x20  /* START flag Clear bit. */
-#define I2C_CONCLR_ENC              0x40  /* I2C interface Disable bit. */
-
-#define I2C_WR_BIT                  0x00
-#define I2C_RD_BIT                  0x01
-
-#define I2C_STATE_MS_START          0x08
-#define I2C_STATE_MS_RSTART         0x10
-#define I2C_STATE_MS_SLAW_ACK       0x18
-#define I2C_STATE_MS_SLAW_NACK      0x20
-#define I2C_STATE_MS_TDAT_ACK       0x28
-#define I2C_STATE_MS_TDAT_NACK      0x30
-#define I2C_STATE_ARB_LOST          0x38
-
-#define I2C_STATE_MS_SLAR_ACK       0x40
-#define I2C_STATE_MS_SLAR_NACK      0x48
-#define I2C_STATE_MS_RDAT_ACK       0x50
-#define I2C_STATE_MS_RDAT_NACK      0x58
-
-#define I2C_STATE_BUS_ERROR         0x00
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-/**
- * @name    Configuration options
- * @{
- */
-
-/**
- * @brief   I2C interrupt priority level setting.
- */
-#if !defined(LPC122x_I2C_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_I2C_IRQ_PRIORITY     3
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing I2C address.
- */
-typedef uint16_t i2caddr_t;
-
-/**
- * @brief   I2C Driver condition flags type.
- */
-typedef uint32_t i2cflags_t;
-/**
- * @brief   Supported modes for the I2C bus.
- */
-typedef enum {
-  I2C_STANDARD_MODE = 1,
-  I2C_FAST_MODE = 2,
-  I2C_FAST_MODE_PLUS = 3
-} i2cmode_t;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
-  i2cmode_t       mode;          /**< @brief Specifies the I2C mode.        */
-  uint32_t        clock_timing;  /**< @brief Specifies the clock timing     */
-} I2CConfig;
-
-/**
- * @brief   Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver {
-  /**
-   * @brief   Driver state.
-   */
-  i2cstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const I2CConfig           *config;
-  /**
-   * @brief   Error flags.
-   */
-  i2cflags_t                errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
-  I2C_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Thread waiting for I/O completion.
-   */
-  Thread                    *thread;
-  /**
-   * @brief     Current slave address without R/W bit.
-   */
-  i2caddr_t                 addr;
-  /**
-   * @brief     Pointer to the transmit buffer.
-   */
-  const uint8_t             *txbuf;
-  /**
-    * @brief    Number of bytes to transmit.
-    */
-  size_t                    txbytes;
-  /**
-    * @brief     Pointer to the receive buffer.
-    */
-  uint8_t                   *rxbuf;
-  /**
-      * @brief    Number of bytes to receive.
-      */
-  size_t                    rxbytes;
-  /**
-   * @brief     Pointer to the I2C registers block.
-   */
-  LPC_I2C_Type              *i2c;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Get errors from I2C driver.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern I2CDriver I2CD1;
-#endif
-
-#endif /* !defined(__DOXYGEN__) */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void i2c_lld_init(void);
-  void i2c_lld_start(I2CDriver *i2cp);
-  void i2c_lld_stop(I2CDriver *i2cp);
-  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                        const uint8_t *txbuf, size_t txbytes,
-                                        uint8_t *rxbuf, size_t rxbytes,
-                                        systime_t timeout);
-  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                       uint8_t *rxbuf, size_t rxbytes,
-                                       systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /* _I2C_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/pal_lld.c b/os/hal/platforms/LPC122x/pal_lld.c
deleted file mode 100644
index c23608a75..000000000
--- a/os/hal/platforms/LPC122x/pal_lld.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-
-/**
- * @file    LPC122x/pal_lld.c
- * @brief   LPC122x GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-/**
- * @brief   LPC122x I/O ports configuration.
- * @details GPIO unit registers initialization.
- *
- * @param[in] config    the LPC122x ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  LPC_GPIO0->DIR = config->P0.dir;
-  LPC_GPIO1->DIR = config->P1.dir;
-  LPC_GPIO2->DIR = config->P2.dir;
-  LPC_GPIO0->MASK = 0;
-  LPC_GPIO1->MASK = 0;
-  LPC_GPIO2->MASK = 0;
-  LPC_GPIO0->OUT = config->P0.data;
-  LPC_GPIO1->OUT = config->P1.data;
-  LPC_GPIO2->OUT = config->P2.data;
-}
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-uint32_t _pal_lld_readgroup(ioportid_t port,
-                            ioportmask_t mask,
-                            uint32_t offset) {
-
-  uint32_t p;
-
-  port->MASK = ~((mask) << offset);
-  p = port->PIN;
-  port->MASK = 0;
-  return p;
-}
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-void _pal_lld_writegroup(ioportid_t port,
-                         ioportmask_t mask,
-                         uint32_t offset,
-                         uint32_t bits) {
-
-  port->MASK = ~((mask) << offset);
-  port->OUT = bits;
-  port->MASK = 0;
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    This function does not alter the @p PINSELx registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    port->DIR &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    palSetPort(port, PAL_WHOLE_PORT);
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->DIR |=  mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/pal_lld.h b/os/hal/platforms/LPC122x/pal_lld.h
deleted file mode 100644
index 4cf870410..000000000
--- a/os/hal/platforms/LPC122x/pal_lld.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-
-/**
- * @file    LPC122x/pal_lld.h
- * @brief   LPC122x GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port setup info.
- */
-typedef struct {
-  /** Initial value for FIO_PIN register.*/
-  uint32_t      data;
-  /** Initial value for FIO_DIR register.*/
-  uint32_t      dir;
-} lpc122x_gpio_setup_t;
-
-/**
- * @brief   GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    The @p IOCON block is not configured, initially all pins have
- *          enabled pullups and are programmed as GPIO. It is responsibility
- *          of the various drivers to reprogram the pins in the proper mode.
- *          Pins that are not handled by any driver may be programmed in
- *          @p board.c.
- */
-typedef struct {
-  /** @brief GPIO 0 setup data.*/
-  lpc122x_gpio_setup_t   P0;
-  /** @brief GPIO 1 setup data.*/
-  lpc122x_gpio_setup_t   P1;
-  /** @brief GPIO 2 setup data.*/
-  lpc122x_gpio_setup_t   P2;
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef LPC_GPIO_Type *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO0 port identifier.
- */
-#define IOPORT1         LPC_GPIO0
-#define GPIO0           LPC_GPIO0
-
-/**
- * @brief   GPIO1 port identifier.
- */
-#define IOPORT2         LPC_GPIO1
-#define GPIO1           LPC_GPIO1
-
-/**
- * @brief   GPIO2 port identifier.
- */
-#define IOPORT3         LPC_GPIO2
-#define GPIO2           LPC_GPIO2
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config)                                                \
-  _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port)                                               \
-  ((port)->PIN)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port)                                              \
-  ((port)->PIN)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits)                                       \
-	((port)->OUT = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits)                                       \
-  ((port)->SET = (bits))
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits)                                       \
-  ((port)->CLR = (bits))
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset)                               \
-  _pal_lld_readgroup(port, mask, offset)
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                        \
-  _pal_lld_writegroup(port, mask, offset, bits)
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)                                    \
-  ((bit) == PAL_LOW) ? pal_lld_clearpad(port, pad) :                        \
-	pal_lld_setpad(port, pad)
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-  ((port)->SET = 1 << (pad))
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-	((port)->CLR = 1 << (pad))
-
-/**
- * @brief   Toggles a pad logical state.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad)                                      \
-  ((port)->NOT = 1 << (pad))
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-  uint32_t _pal_lld_readgroup(ioportid_t port,
-                              ioportmask_t mask,
-                              uint32_t offset);
-  void _pal_lld_writegroup(ioportid_t port,
-                           ioportmask_t mask,
-                           uint32_t offset,
-                           uint32_t bits);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/platform.mk b/os/hal/platforms/LPC122x/platform.mk
deleted file mode 100644
index 9a9853fbd..000000000
--- a/os/hal/platforms/LPC122x/platform.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# List of all the LPC122x platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC122x/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC122x/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC122x/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC122x/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC122x/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/platforms/LPC122x/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC122x/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC122x/rtc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC122x/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC122x/spi_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC122x
diff --git a/os/hal/platforms/LPC122x/pwm_lld.c b/os/hal/platforms/LPC122x/pwm_lld.c
deleted file mode 100644
index 24e5b2639..000000000
--- a/os/hal/platforms/LPC122x/pwm_lld.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x PWM driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/pwm_lld.c
- * @brief   LPC122x PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PWMD1 driver identifier.
- * @note    The driver PWMD1 allocates the complex timer TIM1 when enabled.
- */
-#if LPC122x_PWM_USE_CT16B0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief   PWMD2 driver identifier.
- * @note    The driver PWMD2 allocates the timer TIM2 when enabled.
- */
-#if LPC122x_PWM_USE_CT16B1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief   PWMD3 driver identifier.
- * @note    The driver PWMD3 allocates the timer TIM3 when enabled.
- */
-#if LPC122x_PWM_USE_CT32B0 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief   PWMD4 driver identifier.
- * @note    The driver PWMD4 allocates the timer TIM4 when enabled.
- */
-#if LPC122x_PWM_USE_CT32B1 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if LPC122x_PWM_USE_CT16B0 || LPC122x_PWM_USE_CT16B1 ||                       \
-  LPC122x_PWM_USE_CT32B0 || LPC122x_PWM_USE_CT32B1 || defined(__DOXYGEN__)
-/**
- * @brief   Common TIM2...TIM5 IRQ handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
-  uint16_t sr;
-
-  sr  = pwmp->tim->IR;
-  pwmp->tim->IR = sr;
-  if ((sr & IR_MR0INT) != 0)
-    pwmp->config->channels[0].callback(pwmp);
-  if ((sr & IR_MR1INT) != 0)
-    pwmp->config->channels[1].callback(pwmp);
-  if ((sr & IR_MR3INT) != 0)
-    pwmp->config->callback(pwmp);
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC122x_PWM_USE_CT16B0 || defined(__DOXYGEN__)
-/**
- * @brief   CT16B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector74) {
-
-  CH_IRQ_PROLOGUE();
-  pwm_lld_serve_interrupt(&PWMD1);
-  CH_IRQ_EPILOGUE();
-}
-
-#endif /* STM32_PWM_USE_TIM1 */
-
-#if LPC122x_PWM_USE_CT16B1 || defined(__DOXYGEN__)
-/**
- * @brief   CT16B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector78) {
-
-  CH_IRQ_PROLOGUE();
-  pwm_lld_serve_interrupt(&PWMD2);
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC122x_PWM_USE_CT16B1 */
-
-#if LPC122x_PWM_USE_CT32B0 || defined(__DOXYGEN__)
-/**
- * @brief   CT32B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector7C) {
-
-  CH_IRQ_PROLOGUE();
-  pwm_lld_serve_interrupt(&PWMD3);
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC122x_PWM_USE_CT32B0 */
-
-#if LPC122x_PWM_USE_CT32B1 || defined(__DOXYGEN__)
-/**
- * @brief   CT32B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector80) {
-
-  CH_IRQ_PROLOGUE();
-  pwm_lld_serve_interrupt(&PWMD4);
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC122x_PWM_USE_CT32B1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-#if LPC122x_PWM_USE_CT16B0
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD1);
-  PWMD1.tim = LPC_CT16B0;
-
-#if LPC122x_PWM_USE_CT16B0_CH0
-#if LPC122x_PWM_CT16B0_CH0_SELECTOR == PWM_CT16B0_CH0_IS_PIO0_11
-  LPC_IOCON->PIO0_11 = 0x84;
-#elif LPC122x_PWM_CT16B0_CH0_SELECTOR == PWM_CT16B0_CH0_IS_PIO0_28
-  LPC_IOCON->PIO0_28 = 0x84;
-#else /* LPC122x_PWM_CT16B0_CH0_SELECTOR == PWM_CT16B0_CH0_IS_PIO2_0  */
-  LPC_IOCON->PIO2_0 = 0x84;
-#endif
-#endif
-
-#if LPC122x_PWM_USE_CT16B0_CH1
-#if LPC122x_PWM_CT16B0_CH1_SELECTOR == PWM_CT16B0_CH1_IS_PIO0_12
-  LPC_IOCON->PIO0_12 = 0x84;
-#elif LPC122x_PWM_CT16B0_CH1_SELECTOR == PWM_CT16B0_CH1_IS_PIO0_29
-  LPC_IOCON->PIO0_29 = 0x84;
-#else /* LPC122x_PWM_CT16B0_CH1_SELECTOR == PWM_CT16B0_CH1_IS_PIO2_1  */
-  LPC_IOCON->PIO2_1 = 0x83;
-#endif
-#endif
-#endif
-
-#if LPC122x_PWM_USE_CT16B1
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD2);
-  PWMD2.tim = LPC_CT16B1;
-
-#if LPC122x_PWM_USE_CT16B1_CH0
-#if LPC122x_PWM_CT16B1_CH0_SELECTOR == PWM_CT16B1_CH0_IS_PIO0_15
-  LPC_IOCON->PIO0_15 = 0x84;
-#elif LPC122x_PWM_CT16B1_CH0_SELECTOR == PWM_CT16B1_CH0_IS_PIO1_5
-  LPC_IOCON->PIO1_5 = 0x83;
-#else /* LPC122x_PWM_CT16B1_CH0_SELECTOR == PWM_CT16B1_CH0_IS_PIO2_2 */
-  LPC_IOCON->PIO2_2 = 0x83;
-#endif
-#endif
-
-#if LPC122x_PWM_USE_CT16B1_CH1
-#if LPC122x_PWM_CT16B1_CH1_SELECTOR == PWM_CT16B1_CH1_IS_PIO0_16
-  LPC_IOCON->PIO0_16 = 0x84;
-#elif LPC122x_PWM_CT16B1_CH1_SELECTOR == PWM_CT16B1_CH1_IS_PIO1_6
-  LPC_IOCON->PIO1_6 = 0x82;
-#else /* LPC122x_PWM_CT16B1_CH1_SELECTOR == PWM_CT16B1_CH1_IS_PIO2_3 */
-  LPC_IOCON->PIO2_3 = 0x83;
-#endif
-#endif
-#endif
-
-#if LPC122x_PWM_USE_CT32B0
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD3);
-  PWMD3.tim = LPC_CT32B0;
-
-#if LPC122x_PWM_USE_CT32B0_CH0
-#if LPC122x_PWM_CT32B0_CH0_SELECTOR == PWM_CT32B0_CH0_IS_PIO0_1
-  LPC_IOCON->PIO0_1 = 0x84;
-#elif LPC122x_PWM_CT32B0_CH0_SELECTOR == PWM_CT32B0_CH0_IS_PIO0_18
-  LPC_IOCON->PIO0_18 = 0x84;
-#else /* LPC122x_PWM_CT32B0_CH0_SELECTOR == PWM_CT32B0_CH0_IS_PIO2_4 */
-  LPC_IOCON->PIO2_4 = 0x83;
-#endif
-#endif
-
-#if  LPC122x_PWM_USE_CT32B0_CH1
-#if LPC122x_PWM_CT32B0_CH1_SELECTOR == PWM_CT32B0_CH1_IS_PIO0_2
-  LPC_IOCON->PIO0_2 = 0x84;
-#elif LPC122x_PWM_CT32B0_CH1_SELECTOR == PWM_CT32B0_CH1_IS_PIO0_19
-  LPC_IOCON->PIO0_19 = 0x84;
-#else /* LPC122x_PWM_CT32B0_CH1_SELECTOR == PWM_CT32B0_CH1_IS_PIO2_5  */
-  LPC_IOCON->PIO2_5 = 0x83;
-#endif
-#endif
-#endif
-
-#if LPC122x_PWM_USE_CT32B1
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD4);
-  PWMD4.tim = LPC_CT32B1;
-
-#if LPC122x_PWM_USE_CT32B1_CH0
-#if LPC122x_PWM_CT32B1_CH0_SELECTOR == PWM_CT32B1_CH0_IS_PIO0_6
-  LPC_IOCON->PIO0_6 = 0x84;
-#elif LPC122x_PWM_CT32B1_CH0_SELECTOR == PWM_CT32B1_CH0_IS_PIO0_23
-  LPC_IOCON->PIO0_23 = 0x84;
-#else /* LPC122x_PWM_CT32B1_CH0_SELECTOR == PWM_CT32B1_CH0_IS_PIO2_8 */
-  LPC_IOCON->PIO2_8 = 0x83;
-#endif
-#endif
-
-#if LPC122x_PWM_USE_CT32B1_CH1
-#if LPC122x_PWM_CT32B1_CH1_SELECTOR == PWM_CT32B1_CH1_IS_PIO0_7
-  LPC_IOCON->PIO0_7 = 0x84;
-#elif LPC122x_PWM_CT32B1_CH1_SELECTOR == PWM_CT32B1_CH1_IS_PIO0_24
-  LPC_IOCON->PIO0_24 = 0x84;
-#else /* LPC122x_PWM_CT32B1_CH1_SELECTOR == PWM_CT32B1_CH1_IS_PIO2_9  */
-  LPC_IOCON->PIO2_9 = 0x83;
-#endif
-#endif
-#endif
-}
-
-/**
- * @brief   Configures and activates the PWM peripheral.
- * @note    Starting a driver that is already in the @p PWM_READY state
- *          disables all the active channels.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-  uint32_t pr;
-
-  if (pwmp->state == PWM_STOP) {
-    /* Clock activation and timer reset.*/
-#if LPC122x_PWM_USE_CT16B0
-    if (&PWMD1 == pwmp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7);
-      nvicEnableVector(TIMER_16_0_IRQn, LPC122x_PWM_CT16B0_IRQ_PRIORITY);
-    }
-#endif
-#if LPC122x_PWM_USE_CT16B1
-    if (&PWMD2 == pwmp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
-      nvicEnableVector(TIMER_16_1_IRQn, LPC122x_PWM_CT16B1_IRQ_PRIORITY);
-    }
-#endif
-#if LPC122x_PWM_USE_CT32B0
-    if (&PWMD3 == pwmp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9);
-      nvicEnableVector(TIMER_32_0_IRQn, LPC122x_PWM_CT32B0_IRQ_PRIORITY);
-    }
-#endif
-#if LPC122x_PWM_USE_CT32B1
-     if (&PWMD4 == pwmp) {
-       LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
-       nvicEnableVector(TIMER_32_1_IRQn, LPC122x_PWM_CT32B1_IRQ_PRIORITY);
-     }
-#endif
-  }
-  else {
-    /* Driver re-configuration scenario, it must be stopped first.*/
-    pwmp->tim->TCR = 0;
-  }
-
-  /* Output enables and polarities setup.*/
-  if(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW)
-    pwmp->tim->PWMC = (1 << 0);
-
-  if(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW)
-    pwmp->tim->PWMC |= (1 << 1);
-
-  /* Timer configured and started.*/
-  pr = (uint16_t)((LPC122x_SYSCLK / pwmp->config->frequency) - 1);
-  chDbgAssert(((uint32_t)(pr + 1) * pwmp->config->frequency) == LPC122x_SYSCLK,
-      "pwm_lld_start(), #1", "invalid frequency");
-
-  pwmp->tim->TC = 0;
-  pwmp->tim->PR  = pr;
-  pwmp->tim->IR  = 0xFF;
-  pwmp->tim->MCR = MCR_MR3R;              /* Reset on Match3 */
-  pwmp->tim->MR3 = pwmp->config->period;
-
-  if (pwmp->config->callback != NULL)
-    pwmp->tim->MCR |= MCR_MR3I;
-
-  pwmp->tim->TCR = 1;                     /* Timer start */
-}
-
-/**
- * @brief   Deactivates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
-  /* If in ready state then disables the PWM clock.*/
-  if (pwmp->state == PWM_READY) {
-    pwmp->tim->TCR = 0;                    /* Timer disabled.              */
-    pwmp->tim->MCR = 0;                    /* All IRQs disabled.           */
-    pwmp->tim->IR  = 0xFF;                 /* Clear eventual pending IRQs. */
-    pwmp->tim->PWMC = 0;                   /* PWM outputs disable          */
-
-#if LPC122x_PWM_USE_CT16B0
-    if (&PWMD1 == pwmp) {
-      nvicDisableVector(TIMER_16_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
-    }
-#endif
-#if LPC122x_PWM_USE_CT16B1
-    if (&PWMD2 == pwmp) {
-      nvicDisableVector(TIMER_16_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
-    }
-#endif
-#if LPC122x_PWM_USE_CT32B0
-    if (&PWMD3 == pwmp) {
-      nvicDisableVector(TIMER_32_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
-    }
-#endif
-#if LPC122x_PWM_USE_CT32B1
-    if (&PWMD4 == pwmp) {
-      nvicDisableVector(TIMER_32_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Enables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is active using the specified configuration.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t channel,
-                            pwmcnt_t width) {
-
-  pwmp->tim->MCR &= ~(7 << (channel * 3));
-
-  if ( channel == 0)
-    pwmp->tim->MR0 = width;                  /* New duty cycle. */
-  else
-    pwmp->tim->MR1 = width;                  /* New duty cycle. */
-  /* If there is a callback defined for the channel then the associated
-     interrupt must be enabled.*/
-  if (pwmp->config->channels[channel].callback != NULL) {
-    pwmp->tim->IR = (1 << channel);         /* Clear interrupt flag*/
-    pwmp->tim->MCR |= (1 << (channel * 3)); /* Set interrupt on selected channel */
-  }
-
-}
-
-/**
- * @brief   Disables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is disabled and its output line returned to the
- *          idle state.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-  if ( channel == 0)
-    pwmp->tim->MR0 = 0;
-  else
-    pwmp->tim->MR1 = 0;
-  pwmp->tim->MCR &= ~(7 << (channel * 3));
-  pwmp->tim->IR = (1 << channel);
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/pwm_lld.h b/os/hal/platforms/LPC122x/pwm_lld.h
deleted file mode 100644
index d0d54d234..000000000
--- a/os/hal/platforms/LPC122x/pwm_lld.h
+++ /dev/null
@@ -1,455 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x PWM driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/pwm_lld.h
- * @brief   LPC122x PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-#undef PWM_OUTPUT_ACTIVE_HIGH
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define IR_MR0INT   (1 << 0)
-#define IR_MR1INT   (1 << 1)
-#define IR_MR2INT   (1 << 2)
-#define IR_MR3INT   (1 << 3)
-#define IR_CR0INT   (1 << 4)
-#define IR_CR1INT   (1 << 5)
-#define IR_CR2INT   (1 << 6)
-#define IR_CR3INT   (1 << 7)
-
-#define MCR_MR3I    (1 << 9)
-#define MCR_MR3R    (1 << 10)
-#define MCR_MR3S    (1 << 11)
-
-/**
- * @brief   Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS                      2
-
-#define PWM_CT16B0_CH0_IS_PIO0_11         0
-#define PWM_CT16B0_CH0_IS_PIO0_28         1
-#define PWM_CT16B0_CH0_IS_PIO2_0          2
-
-#define PWM_CT16B0_CH1_IS_PIO0_12         0
-#define PWM_CT16B0_CH1_IS_PIO0_29         1
-#define PWM_CT16B0_CH1_IS_PIO2_1          2
-
-#define PWM_CT16B1_CH0_IS_PIO0_15         0
-#define PWM_CT16B1_CH0_IS_PIO1_5          1
-#define PWM_CT16B1_CH0_IS_PIO2_2          2
-
-#define PWM_CT16B1_CH1_IS_PIO0_16         0
-#define PWM_CT16B1_CH1_IS_PIO1_6          1
-#define PWM_CT16B1_CH1_IS_PIO2_3          2
-
-
-#define PWM_CT32B0_CH0_IS_PIO0_1          0
-#define PWM_CT32B0_CH0_IS_PIO0_18         1
-#define PWM_CT32B0_CH0_IS_PIO2_4          2
-
-#define PWM_CT32B0_CH1_IS_PIO0_2          0
-#define PWM_CT32B0_CH1_IS_PIO0_19         1
-#define PWM_CT32B0_CH1_IS_PIO2_5          2
-
-
-#define PWM_CT32B1_CH0_IS_PIO0_6          0
-#define PWM_CT32B1_CH0_IS_PIO0_23         1
-#define PWM_CT32B1_CH0_IS_PIO2_8          2
-
-#define PWM_CT32B1_CH1_IS_PIO0_7          0
-#define PWM_CT32B1_CH1_IS_PIO0_24         1
-#define PWM_CT32B1_CH1_IS_PIO2_9          2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-
-/**
- * @brief   PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC122x_PWM_USE_CT16B0) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT16B0                  FALSE
-#endif
-
-/**
- * @brief   PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC122x_PWM_USE_CT16B1) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT16B1                  FALSE
-#endif
-
-/**
- * @brief   PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC122x_PWM_USE_CT32B0) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT32B0                  FALSE
-#endif
-
-/**
- * @brief   PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC122x_PWM_USE_CT32B1) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT32B1                  FALSE
-#endif
-
-/**
- * @brief   PWMD1 Channel 0 driver enable switch.
- * @details If set to @p TRUE PWMD1 Channel 0 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_PWM_USE_CT16B0_CH0) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT16B0_CH0                   FALSE
-#endif
-
-/**
- * @brief   PWMD1 Channel 1 driver enable switch.
- * @details If set to @p TRUE PWMD1 Channel 1 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_PWM_USE_CT16B0_CH1) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT16B0_CH1                  FALSE
-#endif
-
-/**
- * @brief   PWMD2 Channel 0 driver enable switch.
- * @details If set to @p TRUE PWMD2 Channel 0 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_PWM_USE_CT16B1_CH0) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT16B1_CH0                   FALSE
-#endif
-
-/**
- * @brief   PWMD2 Channel 1 driver enable switch.
- * @details If set to @p TRUE PWMD2 Channel 1 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_PWM_USE_CT16B1_CH1) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT16B1_CH1                  FALSE
-#endif
-
-/**
- * @brief   PWMD3 Channel 0 driver enable switch.
- * @details If set to @p TRUE PWMD3 Channel 0 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_PWM_USE_CT32B0_CH0) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT32B0_CH0                   FALSE
-#endif
-
-/**
- * @brief   PWMD3 Channel 1 driver enable switch.
- * @details If set to @p TRUE PWMD3 Channel 1 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_PWM_USE_CT32B0_CH1) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT32B0_CH1                  FALSE
-#endif
-
-/**
- * @brief   PWMD4 Channel 0 driver enable switch.
- * @details If set to @p TRUE PWMD4 Channel 0 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_PWM_USE_CT32B1_CH0) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT32B1_CH0                   FALSE
-#endif
-
-/**
- * @brief   PWMD4 Channel 1 driver enable switch.
- * @details If set to @p TRUE PWMD4 Channel 1 is enabled.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC122x_PWM_USE_CT32B1_CH1) || defined(__DOXYGEN__)
-#define LPC122x_PWM_USE_CT32B1_CH1                  FALSE
-#endif
-/**
- * @brief   PWMD1 interrupt priority level setting.
- */
-#if !defined(LPC122x_PWM_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT16B0_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   PWMD2 interrupt priority level setting.
- */
-#if !defined(LPC122x_PWM_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT16B1_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   PWMD3 interrupt priority level setting.
- */
-#if !defined(LPC122x_PWM_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT32B0_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   PWMD4 interrupt priority level setting.
- */
-#if !defined(LPC122x_PWM_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT32B1_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   PWM_CT16B0_CH0 signal selector.
- */
-#if !defined(LPC122x_PWM_CT16B0_CH0_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT16B0_CH0_SELECTOR           PWM_CT16B0_CH0_IS_PIO0_11
-#endif
-
-/**
- * @brief   PWM_CT16B0_CH1 signal selector.
- */
-#if !defined(LPC122x_PWM_CT16B0_CH1_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT16B0_CH1_SELECTOR           PWM_CT16B0_CH1_IS_PIO0_12
-#endif
-
-/**
- * @brief   PWM_CT16B1_CH0 signal selector.
- */
-#if !defined(LPC122x_PWM_CT16B1_CH0_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT16B1_CH0_SELECTOR           PWM_CT16B1_CH0_IS_PIO0_15
-#endif
-
-/**
- * @brief   PWM_CT16B1_CH1 signal selector.
- */
-#if !defined(LPC122x_PWM_CT16B1_CH1_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT16B1_CH1_SELECTOR           PWM_CT16B1_CH1_IS_PIO0_16
-#endif
-
-/**
- * @brief   PWM_CT32B0_CH0 signal selector.
- */
-#if !defined(LPC122x_PWM_CT32B0_CH0_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT32B0_CH0_SELECTOR           PWM_CT32B0_CH0_IS_PIO0_1
-#endif
-
-/**
- * @brief   PWM_CT32B0_CH1 signal selector.
- */
-#if !defined(LPC122x_PWM_CT32B0_CH1_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT32B0_CH1_SELECTOR           PWM_CT32B0_CH1_IS_PIO0_2
-#endif
-
-/**
- * @brief   PWM_CT32B1_CH0 signal selector.
- */
-#if !defined(LPC122x_PWM_CT32B1_CH0_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT32B1_CH0_SELECTOR           PWM_CT32B1_CH0_IS_PIO0_6
-#endif
-
-/**
- * @brief   PWM_CT32B1_CH1 signal selector.
- */
-#if !defined(LPC122x_PWM_CT32B1_CH1_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_PWM_CT32B1_CH1_SELECTOR           PWM_CT32B1_CH1_IS_PIO0_7
-#endif
-
-/*===========================================================================*/
-/* Configuration checks.                                                     */
-/*===========================================================================*/
-
-
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief   PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief   PWM counter type.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief   PWM driver channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel active logic level.
-   */
-  pwmmode_t                 mode;
-  /**
-   * @brief Channel callback pointer.
-   * @note  This callback is invoked on the channel compare event. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief   PWM driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  uint32_t                  frequency;
-  /**
-   * @brief   PWM period in ticks.
-   * @note    The low level can use assertions in order to catch invalid
-   *          period specifications.
-   */
-  pwmcnt_t                  period;
-  /**
-   * @brief Periodic callback pointer.
-   * @note  This callback is invoked on PWM counter reset. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /**
-   * @brief Channels configurations.
-   */
-  PWMChannelConfig          channels[PWM_CHANNELS];
-  /* End of the mandatory fields.*/
-
-} PWMConfig;
-
-/**
- * @brief   Structure representing a PWM driver.
- */
-struct PWMDriver {
-  /**
-   * @brief Driver state.
-   */
-  pwmstate_t                state;
-  /**
-   * @brief Current driver configuration data.
-   */
-  const PWMConfig           *config;
-  /**
-   * @brief   Current PWM period in ticks.
-   */
-  pwmcnt_t                  period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
-  PWM_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Timer base clock.
-   */
-  uint32_t                  clock;
-  /**
-   * @brief Pointer to the TIMx registers block.
-   */
-  LPC_CTxxBx_Type           *tim;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- *          been activated using @p pwmStart().
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The PWM unit period is changed to the new value.
- * @note    The function has effect at the next cycle start.
- * @note    If a period is specified that is shorter than the pulse width
- *          programmed in one of the channels then the behavior is not
- *          guaranteed.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] period    new cycle time in ticks
- *
- * @notapi
- */
-#define pwm_lld_change_period(pwmp, period)                                 \
-  ((pwmp)->tim->MR3 = (period))
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC122x_PWM_USE_CT16B0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if LPC122x_PWM_USE_CT16B1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if LPC122x_PWM_USE_CT32B0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if LPC122x_PWM_USE_CT32B1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void pwm_lld_init(void);
-  void pwm_lld_start(PWMDriver *pwmp);
-  void pwm_lld_stop(PWMDriver *pwmp);
-  void pwm_lld_enable_channel(PWMDriver *pwmp,
-                              pwmchannel_t channel,
-                              pwmcnt_t width);
-  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/rtc_lld.c b/os/hal/platforms/LPC122x/rtc_lld.c
deleted file mode 100644
index ad1a15f80..000000000
--- a/os/hal/platforms/LPC122x/rtc_lld.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x RTC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    LPC122x/rtc_lld.c
- * @brief   LPC122x RTC low level driver.
- *
- * @addtogroup RTC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief RTC driver identifier.
- */
-RTCDriver RTCD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   RTC interrupt handler.
- *
- * @isr
- */
-
-#if LPC122x_RTC_USE_ALARM || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(VectorB8) {
-  uint32_t flag;
-
-  CH_IRQ_PROLOGUE();
-
-  flag = LPC_RTC->RIS;
-  LPC_RTC->ICR = flag;    /* Clear interrupt flag */
-
-  if ((flag & RIS_RTCRIS) && (RTCD1.callback != NULL))
-    RTCD1.callback(&RTCD1, RTC_EVENT_ALARM);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enable access to registers.
- *
- * @api
- */
-void rtc_lld_init(void) {
-  uint32_t temp[2];
-
-  if(LPC_SYSCON->SYSRESSTAT & 0x1) {            /* POR detected */
-
-    LPC_SYSCON->SYSAHBCLKCTRL &= ~(1UL << 19);  /* Disable clock for RTC */
-    LPC_PMU->SYSCFG &= ~(0x0FUL << 11);         /* Clear RTC clock source */
-    LPC_SYSCON->RTCCLKDIV = LPC122x_RTC_CLKDIV;
-    LPC_PMU->SYSCFG |= (LPC122x_RTCCLK << 11);  /* Set RTC clock source */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 19);   /* Enable clock for RTC registers*/
-    LPC_RTC->ICR = 0x01;                        /* Clear interrupt flag */
-    LPC_RTC->CR= 1;                             /* Enable RTC start */
-    LPC_SYSCON->SYSRESSTAT = 0x1;               /* Clear POR flag */
-
-    while(LPC_RTC->DR <3 ) {  /* Wait, data read not valid */
-          __NOP();
-    }
-  }
-  else {
-
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 19);   /* Enable clock for RTC registers*/
-
-    do {
-      temp[0] = LPC_RTC->DR;
-      temp[1] = LPC_RTC->DR;
-    } while(temp[0] == temp[1]);
-
-#if LPC122x_RTC_USE_ALARM
-   if (temp[1] >= LPC_RTC->MR) {  /* Check for match event in software, handle if found */
-     CH_IRQ_HANDLER(VectorB8); /* Manually invoke ISR */
-   }
-#endif
-
-  }
-
-#if LPC122x_RTC_USE_ALARM
-  nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(LPC122x_RTC_IRQ_PRIORITY));
-#endif
-  return;
-}
-
-/**
- * @brief   Set current time.
- * @note    Fractional part will be silently ignored. There is no possibility
- *          to set it on STM32 platform.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] timespec  pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
-  (void)rtcp;
-
-  LPC_RTC->LR = timespec->tv_sec;
-}
-
-/**
- * @brief   Get current time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
-  (void)rtcp;
-
-  timespec->tv_sec = LPC_RTC->DR;
-}
-
-/**
- * @brief     Set alarm time.
- *
- * @note      Default value after BKP domain reset for both comparators is 0.
- * @note      Function does not performs any checks of alarm time validity.
- *
- * @param[in] rtcp      Pointer to RTC driver structure.
- * @param[in] alarm     Alarm identifier. Can be 1 or 2.
- * @param[in] alarmspec Pointer to a @p RTCAlarm structure.
- *
- * @api
- */
-void rtc_lld_set_alarm(RTCDriver *rtcp,
-                       rtcalarm_t alarm,
-                       const RTCAlarm *alarmspec) {
-  (void)rtcp;
-  (void)alarm;
-  LPC_RTC->MR = alarmspec->tv_sec;
-
-}
-
-/**
- * @brief   Get alarm time.
- *
- * @param[in] rtcp       pointer to RTC driver structure
- * @param[in] alarm      alarm identifier
- * @param[out] alarmspec pointer to a @p RTCAlarm structure
- *
- * @api
- */
-void rtc_lld_get_alarm(RTCDriver *rtcp,
-                       rtcalarm_t alarm,
-                       RTCAlarm *alarmspec) {
-  (void)rtcp;
-  (void)alarm;
-  alarmspec->tv_sec = LPC_RTC->MR;
-
-}
-
-/**
- * @brief   Enables or disables RTC callbacks.
- * @details This function enables or disables callbacks, use a @p NULL pointer
- *          in order to disable a callback.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] callback  callback function pointer or @p NULL
- *
- * @notapi
- */
-void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
-
-  LPC_RTC->ICR = 0x01;         /* Clear interrupt flag */
-
-  if (callback != NULL) {
-
-    /* IRQ sources enabled only after setting up the callback.*/
-    rtcp->callback = callback;
-    LPC_RTC->ICSC = ICSC_RTCCIC; /* Enable RTC interrupt */
-  }
-  else {
-
-    LPC_RTC->ICSC = 0;           /* Disable RTC interrupt */
-
-    /* Callback set to NULL only after disabling the IRQ sources.*/
-    rtcp->callback = NULL;
-  }
-}
-
-#include "chrtclib.h"
-
-/**
- * @brief   Get current time in format suitable for usage in FatFS.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @return              FAT time value.
- *
- * @api
- */
-uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) {
-  uint32_t fattime;
-  struct tm timp;
-
-  rtcGetTimeTm(rtcp, &timp);
-
-  fattime  = (timp.tm_sec)       >> 1;
-  fattime |= (timp.tm_min)       << 5;
-  fattime |= (timp.tm_hour)      << 11;
-  fattime |= (timp.tm_mday)      << 16;
-  fattime |= (timp.tm_mon + 1)   << 21;
-  fattime |= (timp.tm_year - 80) << 25;
-
-  return fattime;
-}
-
-#endif /* HAL_USE_RTC */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/rtc_lld.h b/os/hal/platforms/LPC122x/rtc_lld.h
deleted file mode 100644
index b3d3b48ff..000000000
--- a/os/hal/platforms/LPC122x/rtc_lld.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC122x RTC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    LPC122x/rtc_lld.h
- * @brief   LPC122x RTC low level driver header.
- *
- * @addtogroup RTC
- * @{
- */
-
-#ifndef _RTC_LLD_H_
-#define _RTC_LLD_H_
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define CR_RTCSTART         1
-#define ICSC_RTCCIC         1
-#define RIS_RTCRIS          1
-#define MIS_RTCMIS          1
-#define ICR_RTCICR          1
-
-/**
- * @brief   This RTC implementation supports callbacks.
- */
-#define RTC_SUPPORTS_CALLBACKS      TRUE
-
-/**
- * @brief   One alarm comparator available.
- */
-#define RTC_ALARMS              1
-
-/**
- * @brief   RTC Clock source type
- */
-#define SYSCFG_RTCCLK_1Hz		    0		  /* 1 Hz clock */
-#define SYSCFG_RTCCLK_DEL_1Hz	  1		  /* delayed 1 Hz clock */
-#define SYSCFG_RTCCLK_1kHz		  10		/* 1 kHz clock */
-#define SYSCFG_RTCCLK_PCLK		  4		  /* Main clock source divided by RTC */
-										                  /* clock divider */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/*
- * RTC driver system settings.
- */
-
-/**
- * @brief   RTC PCLK divider.
- */
-#if !defined(LPC122x_RTC_CLKDIV) || defined(__DOXYGEN__)
-#define LPC122x_RTC_CLKDIV          0
-#endif
-
-/**
- * @brief   RTC CLK Source
- */
-#if !defined(LPC122x_RTCCLK) || defined(__DOXYGEN__)
-#define LPC122x_RTCCLK   SYSCFG_RTCCLK_1Hz
-#endif
-
-/**
- * @brief   RTC Alarm enable.
- */
-#if !defined(LPC122x_RTC_USE_ALARM) || defined(__DOXYGEN__)
-#define LPC122x_RTC_USE_ALARM         FALSE
-#endif
-
-/**
- * @brief   RTC IRQ Priority.
- */
-#if !defined(LPC122x_RTC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_RTC_IRQ_PRIORITY      3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !(LPC122x_RTCCLK == SYSCFG_RTCCLK_1Hz) &&                                 \
-    !(LPC122x_RTCCLK == SYSCFG_RTCCLK_DEL_1Hz) &&                             \
-    !(LPC122x_RTCCLK == SYSCFG_RTCCLK_1kHz) &&                                \
-    !(LPC122x_RTCCLK == SYSCFG_RTCCLK_PCLK)
-#error "Invalid source selected for RTC clock"
-#endif
-
-#if LPC122x_RTCCLK == SYSCFG_RTCCLK_1kHz
-#error "1 kHz RTC clock not supported"
-#endif
-
-#if LPC122x_RTCCLK == SYSCFG_RTCCLK_PCLK
-#if (LPC122x_MAINCLK/LPC122x_RTC_CLKDIV) != 1
-#error "RTC clock is not 1 Hz"
-#endif
-#endif
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an RTC alarm time stamp.
- */
-typedef struct RTCAlarm RTCAlarm;
-
-/**
- * @brief   Type of a structure representing an RTC wakeup period.
- */
-typedef struct RTCWakeup RTCWakeup;
-
-/**
- * @brief   Type of a structure representing an RTC callbacks config.
- */
-typedef struct RTCCallbackConfig RTCCallbackConfig;
-
-/**
- * @brief   Type of an RTC alarm.
- * @details Meaningful on platforms with more than 1 alarm comparator.
- */
-typedef uint32_t rtcalarm_t;
-
-/**
- * @brief   Type of an RTC event.
- */
-typedef enum {
-  RTC_EVENT_ALARM = 0                  /** Triggered on alarm. */
-} rtcevent_t;
-
-/**
- * @brief   Type of a generic RTC callback.
- */
-typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event);
-
-/**
- * @brief   Structure representing an RTC callbacks config.
- */
-struct RTCCallbackConfig{
-  /**
-   * @brief Generic RTC callback pointer.
-   */
-  rtccb_t           callback;
-};
-
-/**
- * @brief   Structure representing an RTC time stamp.
- */
-struct RTCTime {
-  /**
-   * @brief Seconds since UNIX epoch.
-   */
-  uint32_t tv_sec;
-};
-
-/**
- * @brief   Structure representing an RTC alarm time stamp.
- */
-struct RTCAlarm {
-  /**
-   * @brief Seconds since UNIX epoch.
-   */
-  uint32_t          tv_sec;
-};
-
-/**
- * @brief   Structure representing an RTC driver.
- */
-struct RTCDriver{
-  /**
-   * @brief Callback pointer.
-   */
-  rtccb_t           callback;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern RTCDriver RTCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void rtc_lld_init(void);
-  void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec);
-  void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec);
-  void rtc_lld_set_alarm(RTCDriver *rtcp,
-                         rtcalarm_t alarm,
-                         const RTCAlarm *alarmspec);
-  void rtc_lld_get_alarm(RTCDriver *rtcp,
-                         rtcalarm_t alarm,
-                         RTCAlarm *alarmspec);
-  void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback);
-  uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_RTC */
-
-#endif /* _RTC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/serial_lld.c b/os/hal/platforms/LPC122x/serial_lld.c
deleted file mode 100644
index 88ba5661f..000000000
--- a/os/hal/platforms/LPC122x/serial_lld.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/serial_lld.c
- * @brief   LPC122x low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC122x_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-#if LPC122x_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  LCR_WL8 | LCR_STOP1 | LCR_NOPARITY,
-  FCR_TRIGGER0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   UART initialization.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
-  LPC_UART0_Type *u = sdp->uart;
-  uint32_t upclk;
-#if LPC122x_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      upclk = LPC122x_SERIAL_UART0_PCLK;
-    }
-#endif
-#if LPC122x_SERIAL_USE_UART1
-    if (&SD2 == sdp) {
-      upclk = LPC122x_SERIAL_UART1_PCLK;
-    }
-#endif
-  uint32_t div = upclk / (config->sc_speed << 4);
-  u->LCR = config->sc_lcr | LCR_DLAB;
-  u->DLL = div;
-  u->DLM = div >> 8;
-  u->LCR = config->sc_lcr;
-  u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr;
-  u->ACR = 0;
-  u->FDR = 0x10;
-  u->TER = TER_ENABLE;
-  u->IER = IER_RBR | IER_STATUS;
-}
-
-/**
- * @brief   UART de-initialization.
- *
- * @param[in] u         pointer to an UART I/O block
- */
-static void uart_deinit(LPC_UART0_Type *u) {
-
-  u->LCR = LCR_DLAB;
-  u->DLL = 1;
-  u->DLM = 0;
-  u->LCR = 0;
-  u->FDR = 0x10;
-  u->IER = 0;
-  u->FCR = FCR_RXRESET | FCR_TXRESET;
-  u->ACR = 0;
-  u->TER = TER_ENABLE;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] err       UART LSR register value
- */
-static void set_error(SerialDriver *sdp, IOREG32 err) {
-  flagsmask_t sts = 0;
-
-  if (err & LSR_OVERRUN)
-    sts |= SD_OVERRUN_ERROR;
-  if (err & LSR_PARITY)
-    sts |= SD_PARITY_ERROR;
-  if (err & LSR_FRAMING)
-    sts |= SD_FRAMING_ERROR;
-  if (err & LSR_BREAK)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- * @note    Tries hard to clear all the pending interrupt sources, we don't
- *          want to go through the whole ISR and have another interrupt soon
- *          after.
- *
- * @param[in] u         pointer to an UART I/O block
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  LPC_UART0_Type *u = sdp->uart;
-
-  while (TRUE) {
-    switch (u->IIR & IIR_SRC_MASK) {
-    case IIR_SRC_NONE:
-      return;
-    case IIR_SRC_ERROR:
-      set_error(sdp, u->LSR);
-      break;
-    case IIR_SRC_TIMEOUT:
-    case IIR_SRC_RX:
-      chSysLockFromIsr();
-      if (chIQIsEmptyI(&sdp->iqueue))
-        chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
-      chSysUnlockFromIsr();
-      while (u->LSR & LSR_RBR_FULL) {
-        chSysLockFromIsr();
-        if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK)
-          chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
-        chSysUnlockFromIsr();
-      }
-      break;
-    case IIR_SRC_TX:
-      {
-        int i = LPC122x_SERIAL_FIFO_PRELOAD;
-        do {
-          msg_t b;
-
-          chSysLockFromIsr();
-          b = chOQGetI(&sdp->oqueue);
-          chSysUnlockFromIsr();
-          if (b < Q_OK) {
-            u->IER &= ~IER_THRE;
-            chSysLockFromIsr();
-            chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-            chSysUnlockFromIsr();
-            break;
-          }
-          u->THR = b;
-        } while (--i);
-      }
-      break;
-    default:
-      (void) u->THR;
-      (void) u->RBR;
-    }
-  }
-}
-
-/**
- * @brief   Attempts a TX FIFO preload.
- */
-static void preload(SerialDriver *sdp) {
-  LPC_UART0_Type *u = sdp->uart;
-
-  if (u->LSR & LSR_THRE) {
-    int i = LPC122x_SERIAL_FIFO_PRELOAD;
-    do {
-      msg_t b = chOQGetI(&sdp->oqueue);
-      if (b < Q_OK) {
-        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-        return;
-      }
-      u->THR = b;
-    } while (--i);
-  }
-  u->IER |= IER_THRE;
-}
-
-/**
- * @brief   Driver SD1 output notification.
- */
-#if LPC122x_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD1);
-}
-#endif
-
-/**
- * @brief   Driver SD2 output notification.
- */
-#if LPC122x_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD2);
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 IRQ handler.
- *
- * @isr
- */
-#if LPC122x_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector88) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   UART0 IRQ handler.
- *
- * @isr
- */
-#if LPC122x_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector8C) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if LPC122x_SERIAL_USE_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = LPC_UART0;
-#if LLPC122x_SERIAL_RXD0_SELECTOR == RXD0_IS_PIO0_1
-  LPC_IOCON->PIO0_1 = 0x82;                 /* RDX0 without resistors.       */
-#else /* LPC122x_SERIAL_RXD0_SELECTOR == RXD1_IS_PIO2_1 */
-  LPC_IOCON->PIO2_1  = 0x84;                /* RXD0 without resistors.      */
-#endif
-#if LLPC122x_SERIAL_TXD0_SELECTOR == TXD0_IS_PIO0_8
-  LPC_IOCON->PIO0_2 = 0x82;                 /* TDX0 without resistors.       */
-#else /* LPC122x_SERIAL_TXD0_SELECTOR == TXD0_IS_PIO2_2 */
-  LPC_IOCON->PIO2_2  = 0x84;                /* TXD0 without resistors.      */
-#endif
-#endif
-
-#if LPC122x_SERIAL_USE_UART1
-  sdObjectInit(&SD2, NULL, notify1);
-  SD2.uart = (LPC_UART0_Type *) LPC_UART1;
-#if LLPC122x_SERIAL_RXD1_SELECTOR == RXD1_IS_PIO0_8
-  LPC_IOCON->PIO0_8 = 0x82;          /* RXD1 without resistors.      */
-#elif LPC122x_SERIAL_RXD1_SELECTOR == RXD1_IS_PIO2_11
-  LPC_IOCON->PIO2_11 = 0x85;                /* RXD1 without resistors.      */
-#else /* LPC122x_SERIAL_RXD1_SELECTOR == RXD1_IS_PIO2_12 */
-  LPC_IOCON->PIO2_12  = 0x83;                /* RXD1 without resistors.      */
-#endif
-#if LLPC122x_SERIAL_TXD1_SELECTOR == TXD1_IS_PIO0_8
-  LPC_IOCON->PIO0_9 = 0x82;          /* TXD1 without resistors.      */
-#elif LPC122x_SERIAL_TXD1_SELECTOR == TXD1_IS_PIO2_11
-  LPC_IOCON->PIO2_10 = 0x85;                /* TXD1 without resistors.      */
-#else /* LPC122x_SERIAL_TXD1_SELECTOR == TXD1_IS_PIO2_12 */
-  LPC_IOCON->PIO2_13  = 0x83;                /* TXD1 without resistors.      */
-#endif
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if LPC122x_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
-      LPC_SYSCON->UART0CLKDIV = LPC122x_SERIAL_UART0CLKDIV;
-      nvicEnableVector(UART0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC122x_SERIAL_UART0_IRQ_PRIORITY));
-    }
-#endif
-#if LPC122x_SERIAL_USE_UART1
-    if (&SD2 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 13);
-      LPC_SYSCON->UART1CLKDIV = LPC122x_SERIAL_UART1CLKDIV;
-      nvicEnableVector(UART1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC122x_SERIAL_UART1_IRQ_PRIORITY));
-    }
-#endif
-  }
-  uart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the UART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    uart_deinit(sdp->uart);
-#if LPC122x_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->UART0CLKDIV = 0;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12);
-      nvicDisableVector(UART0_IRQn);
-      return;
-    }
-#endif
-#if LPC122x_SERIAL_USE_UART1
-    if (&SD2 == sdp) {
-      LPC_SYSCON->UART1CLKDIV = 0;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 13);
-      nvicDisableVector(UART1_IRQn);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/serial_lld.h b/os/hal/platforms/LPC122x/serial_lld.h
deleted file mode 100644
index c7ed627d0..000000000
--- a/os/hal/platforms/LPC122x/serial_lld.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/serial_lld.h
- * @brief   LPC122x low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define IIR_SRC_MASK    0x0F
-#define IIR_SRC_NONE    0x01
-#define IIR_SRC_MODEM   0x00
-#define IIR_SRC_TX      0x02
-#define IIR_SRC_RX      0x04
-#define IIR_SRC_ERROR   0x06
-#define IIR_SRC_TIMEOUT 0x0C
-
-#define IER_RBR         1
-#define IER_THRE        2
-#define IER_STATUS      4
-
-#define LCR_WL5         0
-#define LCR_WL6         1
-#define LCR_WL7         2
-#define LCR_WL8         3
-#define LCR_STOP1       0
-#define LCR_STOP2       4
-#define LCR_NOPARITY    0
-#define LCR_PARITYODD   0x08
-#define LCR_PARITYEVEN  0x18
-#define LCR_PARITYONE   0x28
-#define LCR_PARITYZERO  0x38
-#define LCR_BREAK_ON    0x40
-#define LCR_DLAB        0x80
-
-#define FCR_ENABLE      1
-#define FCR_RXRESET     2
-#define FCR_TXRESET     4
-#define FCR_TRIGGER0    0
-#define FCR_TRIGGER1    0x40
-#define FCR_TRIGGER2    0x80
-#define FCR_TRIGGER3    0xC0
-
-#define LSR_RBR_FULL    1
-#define LSR_OVERRUN     2
-#define LSR_PARITY      4
-#define LSR_FRAMING     8
-#define LSR_BREAK       0x10
-#define LSR_THRE        0x20
-#define LSR_TEMT        0x40
-#define LSR_RXFE        0x80
-
-#define TER_ENABLE      0x80
-
-/**
- * @brief   RXD0 signal assigned to pin PIO0_1.
- */
-#define RXD0_IS_PIO0_1         0
-
-/**
- * @brief   RXD0 signal assigned to pin PIO2_1.
- */
-#define RXD0_IS_PIO2_1         1
-
-/**
- * @brief   TXD0 signal assigned to pin PIO0_2.
- */
-#define TXD0_IS_PIO0_2         0
-
-/**
- * @brief   TXD0 signal assigned to pin PIO2_2.
- */
-#define TXD0_IS_PIO2_2         1
-
-/**
- * @brief   RXD1 signal assigned to pin PIO0_8.
- */
-#define RXD1_IS_PIO0_8         0
-
-/**
- * @brief   RXD1 signal assigned to pin PIO2_11.
- */
-#define RXD1_IS_PIO2_11        1
-
-/**
- * @brief   RXD1 signal assigned to pin PIO2_12.
- */
-#define RXD1_IS_PIO2_12        2
-
-/**
- * @brief   TXD1 signal assigned to pin PIO0_9.
- */
-#define TXD1_IS_PIO0_9         0
-
-/**
- * @brief   TXD1 signal assigned to pin PIO2_10.
- */
-#define TXD1_IS_PIO2_10        1
-
-/**
- * @brief   TXD1 signal assigned to pin PIO2_13.
- */
-#define TXD1_IS_PIO2_13       2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC122x_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_USE_UART0            TRUE
-#endif
-
-/**
- * @brief   UART1 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC122x_SERIAL_USE_UART1) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_USE_UART1            TRUE
-#endif
-
-/**
- * @brief   FIFO preload parameter.
- * @details Configuration parameter, this values defines how many bytes are
- *          preloaded in the HW transmit FIFO for each interrupt, the maximum
- *          value is 16 the minimum is 1.
- * @note    An high value reduces the number of interrupts generated but can
- *          also increase the worst case interrupt response time because the
- *          preload loops.
- */
-#if !defined(LPC122x_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_FIFO_PRELOAD         16
-#endif
-
-/**
- * @brief   UART0 PCLK divider.
- */
-#if !defined(LPC122x_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_UART0CLKDIV          1
-#endif
-
-/**
- * @brief   UART1 PCLK divider.
- */
-#if !defined(LPC122x_SERIAL_UART1CLKDIV) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_UART1CLKDIV          1
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(LPC122x_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_UART0_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(LPC122x_SERIAL_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_UART1_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   RXD0 signal selector.
- */
-#if !defined(LPC122x_SERIAL_RXD0_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_RXD0_SELECTOR           RXD0_IS_PIO0_1
-#endif
-
-/**
- * @brief   TXD0 signal selector.
- */
-#if !defined(LPC122x_SERIAL_TXD0_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_TXD0_SELECTOR           TXD0_IS_PIO0_2
-#endif
-
-/**
- * @brief   RXD1 signal selector.
- */
-#if !defined(LPC122x_SERIAL_RXD1_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_RXD1_SELECTOR           RXD1_IS_PIO0_8
-#endif
-
-/**
- * @brief   TXD1 signal selector.
- */
-#if !defined(LPC122x_SERIAL_TXD1_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_SERIAL_TXD1_SELECTOR           TXD1_IS_PIO0_9
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC122x_SERIAL_UART0CLKDIV < 1) || (LPC122x_SERIAL_UART0CLKDIV > 255)
-#error "invalid LPC122x_SERIAL_UART0CLKDIV setting"
-#endif
-
-#if (LPC122x_SERIAL_UART1CLKDIV < 1) || (LPC122x_SERIAL_UART10CLKDIV > 255)
-#error "invalid LPC122x_SERIAL_UART1CLKDIV setting"
-#endif
-
-#if (LPC122x_SERIAL_FIFO_PRELOAD < 1) || (LPC122x_SERIAL_FIFO_PRELOAD > 16)
-#error "invalid LPC122x_SERIAL_FIFO_PRELOAD setting"
-#endif
-
-/**
- * @brief   UART0 clock.
- */
-#define  LPC122x_SERIAL_UART0_PCLK                                          \
-  (LPC122x_MAINCLK / LPC122x_SERIAL_UART0CLKDIV)
-
-/**
- * @brief   UART0 clock.
- */
-#define  LPC122x_SERIAL_UART1_PCLK                                          \
-  (LPC122x_MAINCLK / LPC122x_SERIAL_UART1CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   LPC122x Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the LCR register.
-   */
-  uint32_t                  sc_lcr;
-  /**
-   * @brief Initialization value for the FCR register.
-   */
-  uint32_t                  sc_fcr;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  LPC_UART0_Type       *uart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC122x_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/spi_lld.c b/os/hal/platforms/LPC122x/spi_lld.c
deleted file mode 100644
index 4f8799a54..000000000
--- a/os/hal/platforms/LPC122x/spi_lld.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/spi_lld.c
- * @brief   LPC122x low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC122x_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Preloads the transmit FIFO.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void ssp_fifo_preload(SPIDriver *spip) {
-  LPC_SSP_Type *ssp = spip->ssp;
-  uint32_t n = spip->txcnt > LPC122x_SSP_FIFO_DEPTH ?
-               LPC122x_SSP_FIFO_DEPTH : spip->txcnt;
-
-  while(((ssp->SR & SR_TNF) != 0) && (n > 0)) {
-    if (spip->txptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        const uint16_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-      else {
-        const uint8_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-    }
-    else
-      ssp->DR = 0xFFFFFFFF;
-    n--;
-    spip->txcnt--;
-  }
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void spi_serve_interrupt(SPIDriver *spip) {
-  LPC_SSP_Type *ssp = spip->ssp;
-
-  if ((ssp->MIS & MIS_ROR) != 0) {
-    /* The overflow condition should never happen because priority is given
-       to receive but a hook macro is provided anyway...*/
-    LPC122x_SPI_SSP_ERROR_HOOK(spip);
-  }
-  ssp->ICR = ICR_RT | ICR_ROR;
-  while ((ssp->SR & SR_RNE) != 0) {
-    if (spip->rxptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        uint16_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-      else {
-        uint8_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-    }
-    else
-      (void)ssp->DR;
-    if (--spip->rxcnt == 0) {
-      chDbgAssert(spip->txcnt == 0,
-                  "spi_serve_interrupt(), #1", "counter out of synch");
-      /* Stops the IRQ sources.*/
-      ssp->IMSC = 0;
-      /* Portable SPI ISR code defined in the high level driver, note, it is
-         a macro.*/
-      _spi_isr_code(spip);
-      return;
-    }
-  }
-  ssp_fifo_preload(spip);
-  if (spip->txcnt == 0)
-    ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC122x_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/**
- * @brief   SSP0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector84) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if LPC122x_SPI_USE_SSP0
-  spiObjectInit(&SPID1);
-  SPID1.ssp = LPC_SSP;
-
-  LPC_IOCON->PIO0_14  = 0x82;                /* SCK0 without resistors.      */
-  LPC_IOCON->PIO0_16  = 0x82;                /* MISO0 without resistors.     */
-  LPC_IOCON->PIO0_17  = 0x82;                /* MOSI0 without resistors.     */
-#endif /* LPC122x_SPI_USE_SSP0 */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-    /* Clock activation.*/
-#if LPC122x_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SYSCON->SSPCLKDIV = LPC122x_SPI_SSP0CLKDIV;
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11);
-      LPC_SYSCON->PRESETCTRL |= 1;
-      nvicEnableVector(SSP_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC122x_SPI_SSP0_IRQ_PRIORITY));
-    }
-#endif
-  }
-  /* Configuration.*/
-  spip->ssp->CR1  = 0;
-  spip->ssp->ICR  = ICR_RT | ICR_ROR;
-  spip->ssp->CR0  = spip->config->cr0;
-  spip->ssp->CPSR = spip->config->cpsr;
-  spip->ssp->CR1  = CR1_SSE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state != SPI_STOP) {
-    spip->ssp->CR1  = 0;
-    spip->ssp->CR0  = 0;
-    spip->ssp->CPSR = 0;
-#if LPC122x_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SYSCON->PRESETCTRL &= ~1;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11);
-      LPC_SYSCON->SSPCLKDIV = 0;
-      nvicDisableVector(SSP_IRQn);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->rxptr = NULL;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->rxptr = NULL;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->ssp->DR = (uint32_t)frame;
-  while ((spip->ssp->SR & SR_RNE) == 0)
-    ;
-  return (uint16_t)spip->ssp->DR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/spi_lld.h b/os/hal/platforms/LPC122x/spi_lld.h
deleted file mode 100644
index 0cb48f89f..000000000
--- a/os/hal/platforms/LPC122x/spi_lld.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC122x/spi_lld.h
- * @brief   LPC122x low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Hardware FIFO depth.
- */
-#define LPC122x_SSP_FIFO_DEPTH  8
-
-#define CR0_DSSMASK             0x0F
-#define CR0_DSS4BIT             3
-#define CR0_DSS5BIT             4
-#define CR0_DSS6BIT             5
-#define CR0_DSS7BIT             6
-#define CR0_DSS8BIT             7
-#define CR0_DSS9BIT             8
-#define CR0_DSS10BIT            9
-#define CR0_DSS11BIT            0xA
-#define CR0_DSS12BIT            0xB
-#define CR0_DSS13BIT            0xC
-#define CR0_DSS14BIT            0xD
-#define CR0_DSS15BIT            0xE
-#define CR0_DSS16BIT            0xF
-#define CR0_FRFSPI              0
-#define CR0_FRFSSI              0x10
-#define CR0_FRFMW               0x20
-#define CR0_CPOL                0x40
-#define CR0_CPHA                0x80
-#define CR0_CLOCKRATE(n)        ((n) << 8)
-
-#define CR1_LBM                 1
-#define CR1_SSE                 2
-#define CR1_MS                  4
-#define CR1_SOD                 8
-
-#define SR_TFE                  1
-#define SR_TNF                  2
-#define SR_RNE                  4
-#define SR_RFF                  8
-#define SR_BSY                  16
-
-#define IMSC_ROR                1
-#define IMSC_RT                 2
-#define IMSC_RX                 4
-#define IMSC_TX                 8
-
-#define RIS_ROR                 1
-#define RIS_RT                  2
-#define RIS_RX                  4
-#define RIS_TX                  8
-
-#define MIS_ROR                 1
-#define MIS_RT                  2
-#define MIS_RX                  4
-#define MIS_TX                  8
-
-#define ICR_ROR                 1
-#define ICR_RT                  2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for device SSP0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC122x_SPI_USE_SSP0) || defined(__DOXYGEN__)
-#define LPC122x_SPI_USE_SSP0                TRUE
-#endif
-
-/**
- * @brief   SSP0 PCLK divider.
- */
-#if !defined(LPC122x_SPI_SSP0CLKDIV) || defined(__DOXYGEN__)
-#define LPC122x_SPI_SSP0CLKDIV              1
-#endif
-
-/**
- * @brief   SPI0 interrupt priority level setting.
- */
-#if !defined(LPC122x_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC122x_SPI_SSP0_IRQ_PRIORITY       1
-#endif
-
-/**
- * @brief   Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(LPC122x_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__)
-#define LPC122x_SPI_SSP_ERROR_HOOK(spip)    chSysHalt()
-#endif
-
-/**
- * @brief   SCK0 signal selector.
- */
-#if !defined(LPC122x_SPI_SCK0_SELECTOR) || defined(__DOXYGEN__)
-#define LPC122x_SPI_SCK0_SELECTOR           SCK0_IS_PIO2_11
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC122x_SPI_SSP0CLKDIV < 1) || (LPC122x_SPI_SSP0CLKDIV > 255)
-#error "invalid LPC122x_SPI_SSP0CLKDIV setting"
-#endif
-
-#if !LPC122x_SPI_USE_SSP0 && !LPC122x_SPI_USE_SSP1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-/**
- * @brief   SSP0 clock.
- */
-#define LPC122x_SPI_SSP0_PCLK                                               \
-  (LPC122x_MAINCLK / LPC122x_SPI_SSP0CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief SSP CR0 initialization data.
-   */
-  uint16_t              cr0;
-  /**
-   * @brief SSP CPSR initialization data.
-   */
-  uint32_t              cpsr;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SSP registers block.
-   */
-  LPC_SSP_Type       *ssp;
-  /**
-   * @brief Number of bytes yet to be received.
-   */
-  uint32_t              rxcnt;
-  /**
-   * @brief Receive pointer or @p NULL.
-   */
-  void                  *rxptr;
-  /**
-   * @brief Number of bytes yet to be transmitted.
-   */
-  uint32_t              txcnt;
-  /**
-   * @brief Transmit pointer or @p NULL.
-   */
-  const void            *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC122x_SPI_USE_SSP0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC122x/system_LPC122x.h b/os/hal/platforms/LPC122x/system_LPC122x.h
deleted file mode 100644
index 0a8ecda0f..000000000
--- a/os/hal/platforms/LPC122x/system_LPC122x.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**************************************************************************//**
- * $Id: system_LPC122x.h 6933 2011-03-23 19:02:11Z nxp28548 $
- *
- * @file     system_LPC12xx.h
- * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Header File
- *           for the NXP LPC12xx Device Series
- * @version  1.1
- * @date     $Date:: 2011-03-23#$
- * @author   NXP MCU Team
- *
- * @note
- * Copyright (C) 2010 NXP Semiconductors(NXP). All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
- ******************************************************************************/
-
-#ifndef __SYSTEM_LPC12xx_H
-#define __SYSTEM_LPC12xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-extern uint32_t MainClock;          /*!< Main Clock Frequency (Main Clock) */
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC12xx_H */
diff --git a/os/hal/platforms/LPC13xx/LPC13xx.h b/os/hal/platforms/LPC13xx/LPC13xx.h
deleted file mode 100644
index 89f937e22..000000000
--- a/os/hal/platforms/LPC13xx/LPC13xx.h
+++ /dev/null
@@ -1,570 +0,0 @@
-/****************************************************************************
-*   $Id:: LPC13xx.h 7402 2011-05-25 18:48:12Z usb00175                     $
-*   Project: NXP LPC13xx software example  
- *
-*   Description:
-*     CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 
- *     NXP LPC13xx Device Series 
- *
-****************************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-****************************************************************************/
-
-
-
-#ifndef __LPC13xx_H__
-#define __LPC13xx_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup LPC13xx_Definitions LPC13xx Definitions
-  This file defines all structures and symbols for LPC13xx:
-    - Registers and bitfields
-    - peripheral base address
-    - peripheral ID
-    - PIO definitions
-  @{
-*/
-
-
-/******************************************************************************/
-/*                Processor and Core Peripherals                              */
-/******************************************************************************/
-/** @addtogroup LPC13xx_CMSIS LPC13xx CMSIS Definitions
-  Configuration of the Cortex-M3 Processor and Core Peripherals
-  @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
-  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
-  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
-  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
-
-/******  LPC13xx Specific Interrupt Numbers *******************************************************/
-  WAKEUP0_IRQn                  = 0,        /*!< All I/O pins can be used as wakeup source.       */
-  WAKEUP1_IRQn                  = 1,        /*!< There are 40 pins in total for LPC17xx           */
-  WAKEUP2_IRQn                  = 2,
-  WAKEUP3_IRQn                  = 3,
-  WAKEUP4_IRQn                  = 4,   
-  WAKEUP5_IRQn                  = 5,        
-  WAKEUP6_IRQn                  = 6,        
-  WAKEUP7_IRQn                  = 7,        
-  WAKEUP8_IRQn                  = 8,        
-  WAKEUP9_IRQn                  = 9,        
-  WAKEUP10_IRQn                 = 10,       
-  WAKEUP11_IRQn                 = 11,       
-  WAKEUP12_IRQn                 = 12,       
-  WAKEUP13_IRQn                 = 13,       
-  WAKEUP14_IRQn                 = 14,       
-  WAKEUP15_IRQn                 = 15,       
-  WAKEUP16_IRQn                 = 16,       
-  WAKEUP17_IRQn                 = 17,       
-  WAKEUP18_IRQn                 = 18,       
-  WAKEUP19_IRQn                 = 19,       
-  WAKEUP20_IRQn                 = 20,       
-  WAKEUP21_IRQn                 = 21,       
-  WAKEUP22_IRQn                 = 22,       
-  WAKEUP23_IRQn                 = 23,       
-  WAKEUP24_IRQn                 = 24,       
-  WAKEUP25_IRQn                 = 25,       
-  WAKEUP26_IRQn                 = 26,       
-  WAKEUP27_IRQn                 = 27,       
-  WAKEUP28_IRQn                 = 28,       
-  WAKEUP29_IRQn                 = 29,       
-  WAKEUP30_IRQn                 = 30,       
-  WAKEUP31_IRQn                 = 31,       
-  WAKEUP32_IRQn                 = 32,       
-  WAKEUP33_IRQn                 = 33,       
-  WAKEUP34_IRQn                 = 34,       
-  WAKEUP35_IRQn                 = 35,       
-  WAKEUP36_IRQn                 = 36,       
-  WAKEUP37_IRQn                 = 37,       
-  WAKEUP38_IRQn                 = 38,       
-  WAKEUP39_IRQn                 = 39,       
-  I2C_IRQn                      = 40,       /*!< I2C Interrupt                                    */
-  TIMER_16_0_IRQn               = 41,       /*!< 16-bit Timer0 Interrupt                          */
-  TIMER_16_1_IRQn               = 42,       /*!< 16-bit Timer1 Interrupt                          */
-  TIMER_32_0_IRQn               = 43,       /*!< 32-bit Timer0 Interrupt                          */
-  TIMER_32_1_IRQn               = 44,       /*!< 32-bit Timer1 Interrupt                          */
-  SSP0_IRQn                     = 45,       /*!< SSP Interrupt                                    */
-  UART_IRQn                     = 46,       /*!< UART Interrupt                                   */
-  USB_IRQn                      = 47,       /*!< USB Regular Interrupt                            */
-  USB_FIQn                      = 48,       /*!< USB Fast Interrupt                               */
-  ADC_IRQn                      = 49,       /*!< A/D Converter Interrupt                          */
-  WDT_IRQn                      = 50,       /*!< Watchdog timer Interrupt                         */  
-  BOD_IRQn                      = 51,       /*!< Brown Out Detect(BOD) Interrupt                  */
-  EINT3_IRQn                    = 53,       /*!< External Interrupt 3 Interrupt                   */
-  EINT2_IRQn                    = 54,       /*!< External Interrupt 2 Interrupt                   */
-  EINT1_IRQn                    = 55,       /*!< External Interrupt 1 Interrupt                   */
-  EINT0_IRQn                    = 56,       /*!< External Interrupt 0 Interrupt                   */
-  SSP1_IRQn                     = 57,       /*!< SSP1 Interrupt                                   */
-} IRQn_Type;
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-/*@}*/ /* end of group LPC13xx_CMSIS */
-
-
-#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
-#include "system_LPC13xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral Registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SYSCON) --------------------------------------*/
-/** @addtogroup LPC13xx_SYSCON LPC13xx System Control Block 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 (R/W)  System memory remap Register */
-  __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 (R/W)  Peripheral reset control Register */
-  __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 (R/W)  System PLL control Register */
-  __I  uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C (R/ )  System PLL status Register */
-  __IO uint32_t USBPLLCTRL;      /* USB PLL control, offset 0x10 */
-  __IO uint32_t USBPLLSTAT;
-       uint32_t RESERVED0[2];
-
-  __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 (R/W)  System oscillator control Register */
-  __IO uint32_t WDTOSCCTRL;             /*!< Offset: 0x024 (R/W)  Watchdog oscillator control Register */
-  __IO uint32_t IRCCTRL;                /*!< Offset: 0x028 (R/W)  IRC control Register */
-       uint32_t RESERVED1[1];
-  __IO uint32_t SYSRSTSTAT;             /*!< Offset: 0x030 (R/W)  System reset status Register */
-       uint32_t RESERVED2[3];
-  __IO uint32_t SYSPLLCLKSEL;           /*!< Offset: 0x040 (R/W)  System PLL clock source select Register */	
-  __IO uint32_t SYSPLLCLKUEN;           /*!< Offset: 0x044 (R/W)  System PLL clock source update enable Register */
-  __IO uint32_t USBPLLCLKSEL;
-  __IO uint32_t USBPLLCLKUEN;
-       uint32_t RESERVED3[8];
-
-  __IO uint32_t MAINCLKSEL;             /*!< Offset: 0x070 (R/W)  Main clock source select Register */
-  __IO uint32_t MAINCLKUEN;             /*!< Offset: 0x074 (R/W)  Main clock source update enable Register */
-  __IO uint32_t SYSAHBCLKDIV;           /*!< Offset: 0x078 (R/W)  System AHB clock divider Register */
-       uint32_t RESERVED4[1];
-
-  __IO uint32_t SYSAHBCLKCTRL;          /*!< Offset: 0x080 (R/W)  System AHB clock control Register */
-       uint32_t RESERVED5[4];
-  __IO uint32_t SSP0CLKDIV;                 
-  __IO uint32_t UARTCLKDIV;
-  __IO uint32_t SSP1CLKDIV;             /*!< Offset: 0x09C SSP1 clock divider (R/W) */
-       uint32_t RESERVED6[3];
-
-  __IO uint32_t TRACECLKDIV;
-
-  __IO uint32_t SYSTICKCLKDIV;   /* Offset 0xB0 */           
-       uint32_t RESERVED7[3];
-
-  __IO uint32_t USBCLKSEL;       /* Offset 0xC0 */ 
-  __IO uint32_t USBCLKUEN;
-  __IO uint32_t USBCLKDIV;
-       uint32_t RESERVED8[1];
-  __IO uint32_t WDTCLKSEL;              /*!< Offset: 0x0D0 (R/W)  WDT clock source select Register */
-  __IO uint32_t WDTCLKUEN;              /*!< Offset: 0x0D4 (R/W)  WDT clock source update enable Register */
-  __IO uint32_t WDTCLKDIV;              /*!< Offset: 0x0D8 (R/W)  WDT clock divider Register */
-       uint32_t RESERVED9[1];
-
-  __IO uint32_t CLKOUTCLKSEL;           /*!< Offset: 0x0E0 (R/W)  CLKOUT clock source select Register */
-  __IO uint32_t CLKOUTUEN;              /*!< Offset: 0x0E4 (R/W)  CLKOUT clock source update enable Register */
-  __IO uint32_t CLKOUTDIV;              /*!< Offset: 0x0E8 (R/W)  CLKOUT clock divider Register */
-       uint32_t RESERVED10[5];
-
-  __I  uint32_t PIOPORCAP0;             /*!< Offset: 0x100 (R/ )  POR captured PIO status 0 Register */
-  __I  uint32_t PIOPORCAP1;             /*!< Offset: 0x104 (R/ )  POR captured PIO status 1 Register */
-       uint32_t RESERVED11[11];
-       uint32_t RESERVED12[7];
-  __IO uint32_t BODCTRL;                /*!< Offset: 0x150 (R/W)  BOD control Register */
-       uint32_t RESERVED13[1];
-  __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x158 (R/W)  System tick counter calibration Register */
-       uint32_t RESERVED14[41];          
-
-  __IO uint32_t STARTAPRP0;             /*!< Offset: 0x200 (R/W)  Start logic edge control Register 0 */     
-  __IO uint32_t STARTERP0;              /*!< Offset: 0x204 (R/W)  Start logic signal enable Register 0 */
-  __O  uint32_t STARTRSRP0CLR;          /*!< Offset: 0x208 ( /W)  Start logic reset Register 0 */
-  __I  uint32_t STARTSRP0;              /*!< Offset: 0x20C (R/ )  Start logic status Register 0 */
-  __IO uint32_t STARTAPRP1;             /*!< Offset: 0x210 (R/W)  Start logic edge control Register 1   (LPC11UXX only) */     
-  __IO uint32_t STARTERP1;              /*!< Offset: 0x214 (R/W)  Start logic signal enable Register 1  (LPC11UXX only) */      
-  __O  uint32_t STARTRSRP1CLR;          /*!< Offset: 0x218 ( /W)  Start logic reset Register 1          (LPC11UXX only) */
-  __I  uint32_t STARTSRP1;              /*!< Offset: 0x21C (R/ )  Start logic status Register 1         (LPC11UXX only) */
-       uint32_t RESERVED17[4];
-
-  __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 (R/W)  Power-down states in Deep-sleep mode Register  */
-  __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 (R/W)  Power-down states after wake-up from Deep-sleep mode Register*/       
-  __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 (R/W)  Power-down configuration Register*/
-       uint32_t RESERVED18[110];
-  __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 (R/ )  Device ID Register */
-} LPC_SYSCON_TypeDef;
-/*@}*/ /* end of group LPC13xx_SYSCON */
-
-
-/*------------- Pin Connect Block (IOCON) --------------------------------*/
-/** @addtogroup LPC13xx_IOCON LPC13xx I/O Configuration Block 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t PIO2_6;                 /*!< Offset: 0x000 (R/W) I/O configuration for pin PIO2_6 */
-       uint32_t RESERVED0[1];
-  __IO uint32_t PIO2_0;                 /*!< Offset: 0x008 (R/W)  I/O configuration for pin PIO2_0/DTR/SSEL1 */
-  __IO uint32_t RESET_PIO0_0;           /*!< Offset: 0x00C (R/W)  I/O configuration for pin RESET/PIO0_0  */
-  __IO uint32_t PIO0_1;                 /*!< Offset: 0x010 (R/W)  I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 */
-  __IO uint32_t PIO1_8;                 /*!< Offset: 0x014 (R/W)  I/O configuration for pin PIO1_8/CT16B1_CAP0 */
-       uint32_t RESERVED1[1];
-  __IO uint32_t PIO0_2;                 /*!< Offset: 0x01C (R/W)  I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
-
-  __IO uint32_t PIO2_7;                 /*!< Offset: 0x020 (R/W)  I/O configuration for pin PIO2_7 */
-  __IO uint32_t PIO2_8;                 /*!< Offset: 0x024 (R/W)  I/O configuration for pin PIO2_8 */
-  __IO uint32_t PIO2_1;                 /*!< Offset: 0x028 (R/W)  I/O configuration for pin PIO2_1/nDSR/SCK1 */
-  __IO uint32_t PIO0_3;                 /*!< Offset: 0x02C (R/W)  I/O configuration for pin PIO0_3 */
-  __IO uint32_t PIO0_4;                 /*!< Offset: 0x030 (R/W)  I/O configuration for pin PIO0_4/SCL */
-  __IO uint32_t PIO0_5;                 /*!< Offset: 0x034 (R/W)  I/O configuration for pin PIO0_5/SDA */
-  __IO uint32_t PIO1_9;                 /*!< Offset: 0x038 (R/W)  I/O configuration for pin PIO1_9/CT16B1_MAT0 */
-  __IO uint32_t PIO3_4;                 /*!< Offset: 0x03C (R/W)  I/O configuration for pin PIO3_4 */
-
-  __IO uint32_t PIO2_4;                 /*!< Offset: 0x040 (R/W)  I/O configuration for pin PIO2_4 */
-  __IO uint32_t PIO2_5;                 /*!< Offset: 0x044 (R/W)  I/O configuration for pin PIO2_5 */
-  __IO uint32_t PIO3_5;                 /*!< Offset: 0x048 (R/W)  I/O configuration for pin PIO3_5 */
-  __IO uint32_t PIO0_6;                 /*!< Offset: 0x04C (R/W)  I/O configuration for pin PIO0_6/SCK0 */
-  __IO uint32_t PIO0_7;                 /*!< Offset: 0x050 (R/W)  I/O configuration for pin PIO0_7/nCTS */
-  __IO uint32_t PIO2_9;                 /*!< Offset: 0x054 (R/W)  I/O configuration for pin PIO2_9 */
-  __IO uint32_t PIO2_10;                /*!< Offset: 0x058 (R/W)  I/O configuration for pin PIO2_10 */
-  __IO uint32_t PIO2_2;                 /*!< Offset: 0x05C (R/W)  I/O configuration for pin PIO2_2/DCD/MISO1 */
-
-  __IO uint32_t PIO0_8;                 /*!< Offset: 0x060 (R/W)  I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
-  __IO uint32_t PIO0_9;                 /*!< Offset: 0x064 (R/W)  I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
-  __IO uint32_t SWCLK_PIO0_10;          /*!< Offset: 0x068 (R/W)  I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 */
-  __IO uint32_t PIO1_10;                /*!< Offset: 0x06C (R/W)  I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 */
-  __IO uint32_t PIO2_11;                /*!< Offset: 0x070 (R/W)  I/O configuration for pin PIO2_11/SCK0 */
-  __IO uint32_t R_PIO0_11;              /*!< Offset: 0x074 (R/W)  I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
-  __IO uint32_t R_PIO1_0;               /*!< Offset: 0x078 (R/W)  I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 */
-  __IO uint32_t R_PIO1_1;               /*!< Offset: 0x07C (R/W)  I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 */
-
-  __IO uint32_t R_PIO1_2;               /*!< Offset: 0x080 (R/W)  I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 */
-  __IO uint32_t PIO3_0;                 /*!< Offset: 0x084 (R/W)  I/O configuration for pin PIO3_0/nDTR */
-  __IO uint32_t PIO3_1;                 /*!< Offset: 0x088 (R/W)  I/O configuration for pin PIO3_1/nDSR */
-  __IO uint32_t PIO2_3;                 /*!< Offset: 0x08C (R/W)  I/O configuration for pin PIO2_3/RI/MOSI1 */
-  __IO uint32_t SWDIO_PIO1_3;           /*!< Offset: 0x090 (R/W)  I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 */
-  __IO uint32_t PIO1_4;                 /*!< Offset: 0x094 (R/W)  I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 */
-  __IO uint32_t PIO1_11;                /*!< Offset: 0x098 (R/W)  I/O configuration for pin PIO1_11/AD7 */
-  __IO uint32_t PIO3_2;                 /*!< Offset: 0x09C (R/W)  I/O configuration for pin PIO3_2/nDCD */
-
-  __IO uint32_t PIO1_5;
-  __IO uint32_t PIO1_6;
-  __IO uint32_t PIO1_7;
-  __IO uint32_t PIO3_3;
-  __IO uint32_t SCK_LOC;                /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
-  __IO uint32_t DSR_LOC;                /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
-  __IO uint32_t DCD_LOC;                /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
-  __IO uint32_t RI_LOC;                 /*!< Offset: 0x0BC RI pin location Register (R/W) */
-} LPC_IOCON_TypeDef;
-/*@}*/ /* end of group LPC13xx_IOCON */
-
-
-/*------------- Power Management Unit (PMU) --------------------------*/
-/** @addtogroup LPC13xx_PMU LPC13xx Power Management Unit
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t PCON;                   /*!< Offset: 0x000 (R/W)  Power control Register */
-  __IO uint32_t GPREG0;                 /*!< Offset: 0x004 (R/W)  General purpose Register 0 */
-  __IO uint32_t GPREG1;                 /*!< Offset: 0x008 (R/W)  General purpose Register 1 */
-  __IO uint32_t GPREG2;                 /*!< Offset: 0x00C (R/W)  General purpose Register 2 */
-  __IO uint32_t GPREG3;                 /*!< Offset: 0x010 (R/W)  General purpose Register 3 */
-  __IO uint32_t GPREG4;                 /*!< Offset: 0x014 (R/W)  General purpose Register 4 */
-} LPC_PMU_TypeDef;
-/*@}*/ /* end of group LPC13xx_PMU */
-
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-/** @addtogroup LPC13xx_GPIO LPC13xx General Purpose Input/Output 
-  @{
-*/
-typedef struct
-{
-  union {
-    __IO uint32_t MASKED_ACCESS[4096];  /*!< Offset: 0x0000 (R/W) Port data Register for pins PIOn_0 to PIOn_11 */
-    struct {
-         uint32_t RESERVED0[4095];
-    __IO uint32_t DATA;                 /*!< Offset: 0x3FFC (R/W) Port data Register */
-    };
-  };
-       uint32_t RESERVED1[4096];
-  __IO uint32_t DIR;                    /*!< Offset: 0x8000 (R/W)  Data direction Register */
-  __IO uint32_t IS;                     /*!< Offset: 0x8004 (R/W)  Interrupt sense Register */
-  __IO uint32_t IBE;                    /*!< Offset: 0x8008 (R/W)  Interrupt both edges Register */
-  __IO uint32_t IEV;                    /*!< Offset: 0x800C (R/W)  Interrupt event Register */
-  __IO uint32_t IE;                     /*!< Offset: 0x8010 (R/W)  Interrupt mask Register */
-  __I  uint32_t RIS;                    /*!< Offset: 0x8014 (R/ )  Raw interrupt status Register */
-  __I  uint32_t MIS;                    /*!< Offset: 0x8018 (R/ )  Masked interrupt status Register */
-  __O  uint32_t IC;                     /*!< Offset: 0x801C ( /W)  Interrupt clear Register */
-} LPC_GPIO_TypeDef;
-/*@}*/ /* end of group LPC13xx_GPIO */
-
-
-/*------------- Timer (TMR) --------------------------------------------------*/
-/** @addtogroup LPC13xx_TMR LPC13xx 16/32-bit Counter/Timer 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 (R/W)  Interrupt Register */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 (R/W)  Timer Control Register */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 (R/W)  Timer Counter Register */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C (R/W)  Prescale Register */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 (R/W)  Prescale Counter Register */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 (R/W)  Match Control Register */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 (R/W)  Match Register 0 */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C (R/W)  Match Register 1 */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 (R/W)  Match Register 2 */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 (R/W)  Match Register 3 */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 (R/W)  Capture Control Register */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C (R/ )  Capture Register 0 */
-       uint32_t RESERVED1[3];
-  __IO uint32_t EMR;                    /*!< Offset: 0x03C (R/W)  External Match Register */
-       uint32_t RESERVED2[12];
-  __IO uint32_t CTCR;                   /*!< Offset: 0x070 (R/W)  Count Control Register */
-  __IO uint32_t PWMC;                   /*!< Offset: 0x074 (R/W)  PWM Control Register */
-} LPC_TMR_TypeDef;
-/*@}*/ /* end of group LPC13xx_TMR */
-
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-/** @addtogroup LPC13xx_UART LPC13xx Universal Asynchronous Receiver/Transmitter 
-  @{
-*/
-typedef struct
-{
-  union {
-  __I  uint32_t  RBR;                   /*!< Offset: 0x000 (R/ )  Receiver Buffer  Register */
-  __O  uint32_t  THR;                   /*!< Offset: 0x000 ( /W)  Transmit Holding Register */
-  __IO uint32_t  DLL;                   /*!< Offset: 0x000 (R/W)  Divisor Latch LSB */
-  };
-  union {
-  __IO uint32_t  DLM;                   /*!< Offset: 0x004 (R/W)  Divisor Latch MSB */
-  __IO uint32_t  IER;                   /*!< Offset: 0x000 (R/W)  Interrupt Enable Register */
-  };
-  union {
-  __I  uint32_t  IIR;                   /*!< Offset: 0x008 (R/ )  Interrupt ID Register */
-  __O  uint32_t  FCR;                   /*!< Offset: 0x008 ( /W)  FIFO Control Register */
-  };
-  __IO uint32_t  LCR;                   /*!< Offset: 0x00C (R/W)  Line Control Register */
-  __IO uint32_t  MCR;                   /*!< Offset: 0x010 (R/W)  Modem control Register */
-  __I  uint32_t  LSR;                   /*!< Offset: 0x014 (R/ )  Line Status Register */
-  __I  uint32_t  MSR;                   /*!< Offset: 0x018 (R/ )  Modem status Register */
-  __IO uint32_t  SCR;                   /*!< Offset: 0x01C (R/W)  Scratch Pad Register */
-  __IO uint32_t  ACR;                   /*!< Offset: 0x020 (R/W)  Auto-baud Control Register */
-       uint32_t  RESERVED0[1];
-  __IO uint32_t  FDR;                   /*!< Offset: 0x028 (R/W)  Fractional Divider Register */
-       uint32_t  RESERVED1[1];
-  __IO uint32_t  TER;                   /*!< Offset: 0x030 (R/W)  Transmit Enable Register */
-       uint32_t  RESERVED2[6];
-  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C (R/W)  RS-485/EIA-485 Control Register */
-  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 (R/W)  RS-485/EIA-485 address match Register */
-  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 (R/W)  RS-485/EIA-485 direction control delay Register */
-
-} LPC_UART_TypeDef;
-/*@}*/ /* end of group LPC13xx_UART */
-
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-/** @addtogroup LPC13xx_SSP LPC13xx Synchronous Serial Port 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CR0;                    /*!< Offset: 0x000 (R/W)  Control Register 0 */
-  __IO uint32_t CR1;                    /*!< Offset: 0x004 (R/W)  Control Register 1 */
-  __IO uint32_t DR;                     /*!< Offset: 0x008 (R/W)  Data Register */
-  __I  uint32_t SR;                     /*!< Offset: 0x00C (R/ )  Status Register */
-  __IO uint32_t CPSR;                   /*!< Offset: 0x010 (R/W)  Clock Prescale Register */
-  __IO uint32_t IMSC;                   /*!< Offset: 0x014 (R/W)  Interrupt Mask Set and Clear Register */
-  __I  uint32_t RIS;                    /*!< Offset: 0x018 (R/ )  Raw Interrupt Status Register */
-  __I  uint32_t MIS;                    /*!< Offset: 0x01C (R/ )  Masked Interrupt Status Register */
-  __O  uint32_t ICR;                    /*!< Offset: 0x020 ( /W)  SSPICR Interrupt Clear Register */
-} LPC_SSP_TypeDef;
-/*@}*/ /* end of group LPC13xx_SSP */
-
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-/** @addtogroup LPC13xx_I2C LPC13xx I2C-Bus Interface 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CONSET;                 /*!< Offset: 0x000 (R/W)  I2C Control Set Register */
-  __I  uint32_t STAT;                   /*!< Offset: 0x004 (R/ )  I2C Status Register */
-  __IO uint32_t DAT;                    /*!< Offset: 0x008 (R/W)  I2C Data Register */
-  __IO uint32_t ADR0;                   /*!< Offset: 0x00C (R/W)  I2C Slave Address Register 0 */
-  __IO uint32_t SCLH;                   /*!< Offset: 0x010 (R/W)  SCH Duty Cycle Register High Half Word */
-  __IO uint32_t SCLL;                   /*!< Offset: 0x014 (R/W)  SCL Duty Cycle Register Low Half Word */
-  __O  uint32_t CONCLR;                 /*!< Offset: 0x018 ( /W)  I2C Control Clear Register */
-  __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C (R/W)  Monitor mode control register */
-  __IO uint32_t ADR1;                   /*!< Offset: 0x020 (R/W)  I2C Slave Address Register 1 */
-  __IO uint32_t ADR2;                   /*!< Offset: 0x024 (R/W)  I2C Slave Address Register 2 */
-  __IO uint32_t ADR3;                   /*!< Offset: 0x028 (R/W)  I2C Slave Address Register 3 */
-  __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C (R/ )  Data buffer Register */
-  __IO uint32_t MASK0;                  /*!< Offset: 0x030 (R/W)  I2C Slave address mask register 0 */
-  __IO uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  I2C Slave address mask register 1 */
-  __IO uint32_t MASK2;                  /*!< Offset: 0x038 (R/W)  I2C Slave address mask register 2 */
-  __IO uint32_t MASK3;                  /*!< Offset: 0x03C (R/W)  I2C Slave address mask register 3 */
-} LPC_I2C_TypeDef;
-/*@}*/ /* end of group LPC13xx_I2C */
-
-
-/*------------- Windowed Watchdog Timer (WWDT) -----------------------------------------*/
-/** @addtogroup LPC13xx_WWDT LPC13xx Windowed WatchDog Timer 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t MOD;
-  __IO uint32_t TC;
-  __O  uint32_t FEED;
-  __I  uint32_t TV;
-       uint32_t RESERVED0;
-  __IO uint32_t WARNINT;				/*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
-  __IO uint32_t WINDOW;					/*!< Offset: 0x018 Watchdog timer window value register (R/W) */
-} LPC_WWDT_TypeDef;
-/*@}*/ /* end of group LPC13xx_WWDT */
-
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-/** @addtogroup LPC13xx_ADC LPC13xx Analog-to-Digital Converter 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CR;                     /*!< Offset: 0x000 (R/W)  A/D Control Register */
-  __IO uint32_t GDR;                    /*!< Offset: 0x004 (R/W)  A/D Global Data Register */
-       uint32_t RESERVED0[1];
-  __IO uint32_t INTEN;                  /*!< Offset: 0x00C (R/W)  A/D Interrupt Enable Register */
-  __IO uint32_t DR[8];                  /*!< Offset: 0x010 (R/W)  A/D Channel 0..7 Data Register */
-  __I  uint32_t STAT;                   /*!< Offset: 0x030 (R/ )  A/D Status Register */
-} LPC_ADC_TypeDef;
-/*@}*/ /* end of group LPC13xx_ADC */
-
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-/** @addtogroup LPC13xx_USB LPC13xx Universal Serial Bus 
-  @{
-*/
-typedef struct
-{
-  __I  uint32_t DevIntSt;               /*!< Offset: 0x000 (R/ )  USB Device Interrupt Status Register */
-  __IO uint32_t DevIntEn;               /*!< Offset: 0x004 (R/W)  USB Device Interrupt Enable Register */
-  __O  uint32_t DevIntClr;              /*!< Offset: 0x008 ( /W)  USB Device Interrupt Clear Register */
-  __O  uint32_t DevIntSet;              /*!< Offset: 0x00C ( /W)  USB Device Interrupt Set Register */
-
-  __O  uint32_t CmdCode;                /*!< Offset: 0x010 ( /W)  USB Command Code Register */
-  __I  uint32_t CmdData;                /*!< Offset: 0x014 (R/ )  USB Command Data Register */
-
-  __I  uint32_t RxData;                 /*!< Offset: 0x018 (R/ )  USB Receive Data Register */
-  __O  uint32_t TxData;                 /*!< Offset: 0x01C ( /W)  USB Transmit Data Register */
-  __I  uint32_t RxPLen;                 /*!< Offset: 0x020 (R/ )  USB Receive Packet Length Register */
-  __O  uint32_t TxPLen;                 /*!< Offset: 0x024 ( /W)  USB Transmit Packet Length Register */
-  __IO uint32_t Ctrl;                   /*!< Offset: 0x028 (R/ )  USB Control Register */
-  __O  uint32_t DevFIQSel;              /*!< Offset: 0x02C ( /W)  USB Device FIQ select Register */
-} LPC_USB_TypeDef;
-/*@}*/ /* end of group LPC13xx_USB */
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_AHB_BASE          (0x50000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_I2C_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_WWDT_BASE         (LPC_APB0_BASE + 0x04000)
-#define LPC_UART_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_CT16B0_BASE       (LPC_APB0_BASE + 0x0C000)
-#define LPC_CT16B1_BASE       (LPC_APB0_BASE + 0x10000)
-#define LPC_CT32B0_BASE       (LPC_APB0_BASE + 0x14000)
-#define LPC_CT32B1_BASE       (LPC_APB0_BASE + 0x18000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x1C000)
-#define LPC_USB_BASE          (LPC_APB0_BASE + 0x20000)
-#define LPC_PMU_BASE          (LPC_APB0_BASE + 0x38000)
-#define LPC_SSP0_BASE         (LPC_APB0_BASE + 0x40000)
-#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)
-#define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x58000)
-
-/* AHB peripherals                                                            */	
-#define LPC_GPIO_BASE         (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x10000)
-#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x20000)
-#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x30000)
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )
-#define LPC_WWDT              ((LPC_WWDT_TypeDef   *) LPC_WWDT_BASE  )
-#define LPC_UART              ((LPC_UART_TypeDef   *) LPC_UART_BASE  )
-#define LPC_TMR16B0           ((LPC_TMR_TypeDef    *) LPC_CT16B0_BASE)
-#define LPC_TMR16B1           ((LPC_TMR_TypeDef    *) LPC_CT16B1_BASE)
-#define LPC_TMR32B0           ((LPC_TMR_TypeDef    *) LPC_CT32B0_BASE)
-#define LPC_TMR32B1           ((LPC_TMR_TypeDef    *) LPC_CT32B1_BASE)
-#define LPC_ADC               ((LPC_ADC_TypeDef    *) LPC_ADC_BASE   )
-#define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )
-#define LPC_SSP0              ((LPC_SSP_TypeDef    *) LPC_SSP0_BASE  )
-#define LPC_SSP1              ((LPC_SSP_TypeDef    *) LPC_SSP1_BASE  )
-#define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )
-#define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
-#define LPC_USB               ((LPC_USB_TypeDef    *) LPC_USB_BASE   )
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __LPC13xx_H__ */
diff --git a/os/hal/platforms/LPC13xx/gpt_lld.c b/os/hal/platforms/LPC13xx/gpt_lld.c
deleted file mode 100644
index 66581dfc9..000000000
--- a/os/hal/platforms/LPC13xx/gpt_lld.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/gpt_lld.c
- * @brief   LPC13xx GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver identifier.
- * @note    The driver GPT1 allocates the complex timer CT16B0 when enabled.
- */
-#if LPC13xx_GPT_USE_CT16B0 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief   GPT2 driver identifier.
- * @note    The driver GPT2 allocates the timer CT16B1 when enabled.
- */
-#if LPC13xx_GPT_USE_CT16B1 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief   GPT3 driver identifier.
- * @note    The driver GPT3 allocates the timer CT32B0 when enabled.
- */
-#if LPC13xx_GPT_USE_CT32B0 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/**
- * @brief   GPT4 driver identifier.
- * @note    The driver GPT4 allocates the timer CT32B1 when enabled.
- */
-#if LPC13xx_GPT_USE_CT32B1 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
-  gptp->tmr->IR = 1;                        /* Clear interrupt on match MR0.*/
-  if (gptp->state == GPT_ONESHOT) {
-    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
-    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
-  }
-  gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC13xx_GPT_USE_CT16B0
-/**
- * @brief   CT16B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorE4) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC13xx_GPT_USE_CT16B0 */
-
-#if LPC13xx_GPT_USE_CT16B1
-/**
- * @brief   CT16B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorE8) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC13xx_GPT_USE_CT16B0 */
-
-#if LPC13xx_GPT_USE_CT32B0
-/**
- * @brief   CT32B0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorEC) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC13xx_GPT_USE_CT32B0 */
-
-#if LPC13xx_GPT_USE_CT32B1
-/**
- * @brief   CT32B1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorF0) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC13xx_GPT_USE_CT32B1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if LPC13xx_GPT_USE_CT16B0
-  /* Driver initialization.*/
-  GPTD1.tmr = LPC_TMR16B0;
-  gptObjectInit(&GPTD1);
-#endif
-
-#if LPC13xx_GPT_USE_CT16B1
-  /* Driver initialization.*/
-  GPTD2.tmr = LPC_TMR16B1;
-  gptObjectInit(&GPTD2);
-#endif
-
-#if LPC13xx_GPT_USE_CT32B0
-  /* Driver initialization.*/
-  GPTD3.tmr = LPC_TMR32B0;
-  gptObjectInit(&GPTD3);
-#endif
-
-#if LPC13xx_GPT_USE_CT32B1
-  /* Driver initialization.*/
-  GPTD4.tmr = LPC_TMR32B1;
-  gptObjectInit(&GPTD4);
-#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-  uint32_t pr;
-
-  if (gptp->state == GPT_STOP) {
-    /* Clock activation.*/
-#if LPC13xx_GPT_USE_CT16B0
-    if (&GPTD1 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7);
-      nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC13xx_GPT_USE_CT16B1
-    if (&GPTD2 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
-      nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3));
-    }
-#endif
-#if LPC13xx_GPT_USE_CT32B0
-    if (&GPTD3 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9);
-      nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC13xx_GPT_USE_CT32B1
-    if (&GPTD4 == gptp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
-      nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-  }
-
-  /* Prescaler value calculation.*/
-  pr = (uint16_t)((LPC13xx_SYSCLK / gptp->config->frequency) - 1);
-  chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC13xx_SYSCLK,
-              "gpt_lld_start(), #1", "invalid frequency");
-
-  /* Timer configuration.*/
-  gptp->tmr->PR  = pr;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
-  if (gptp->state == GPT_READY) {
-    gptp->tmr->MCR = 0;
-    gptp->tmr->TCR = 0;
-
-#if LPC13xx_GPT_USE_CT16B0
-    if (&GPTD1 == gptp) {
-      nvicDisableVector(TIMER_16_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7);
-    }
-#endif
-#if LPC13xx_GPT_USE_CT16B1
-    if (&GPTD2 == gptp) {
-      nvicDisableVector(TIMER_16_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
-    }
-#endif
-#if LPC13xx_GPT_USE_CT32B0
-    if (&GPTD3 == gptp) {
-      nvicDisableVector(TIMER_32_0_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9);
-    }
-#endif
-#if LPC13xx_GPT_USE_CT32B1
-    if (&GPTD4 == gptp) {
-      nvicDisableVector(TIMER_32_1_IRQn);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 3;                       /* IRQ and clr TC on match MR0. */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 4;                       /* Stop TC on match MR0.        */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-  while (gptp->tmr->TCR & 1)
-    ;
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/gpt_lld.h b/os/hal/platforms/LPC13xx/gpt_lld.h
deleted file mode 100644
index 87c8475e9..000000000
--- a/os/hal/platforms/LPC13xx/gpt_lld.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/gpt_lld.h
- * @brief   LPC13xx GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver enable switch.
- * @details If set to @p TRUE the support for GPT1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC13xx_GPT_USE_CT16B0) || defined(__DOXYGEN__)
-#define LPC13xx_GPT_USE_CT16B0              TRUE
-#endif
-
-/**
- * @brief   GPT2 driver enable switch.
- * @details If set to @p TRUE the support for GPT2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC13xx_GPT_USE_CT16B1) || defined(__DOXYGEN__)
-#define LPC13xx_GPT_USE_CT16B1              TRUE
-#endif
-
-/**
- * @brief   GPT3 driver enable switch.
- * @details If set to @p TRUE the support for GPT3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC13xx_GPT_USE_CT32B0) || defined(__DOXYGEN__)
-#define LPC13xx_GPT_USE_CT32B0              TRUE
-#endif
-
-/**
- * @brief   GPT4 driver enable switch.
- * @details If set to @p TRUE the support for GPT4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC13xx_GPT_USE_CT32B1) || defined(__DOXYGEN__)
-#define LPC13xx_GPT_USE_CT32B1              TRUE
-#endif
-
-/**
- * @brief   GPT1 interrupt priority level setting.
- */
-#if !defined(LPC13xx_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC13xx_GPT_CT16B0_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT2 interrupt priority level setting.
- */
-#if !defined(LPC13xx_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC13xx_GPT_CT16B1_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT3 interrupt priority level setting.
- */
-#if !defined(LPC13xx_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC13xx_GPT_CT32B0_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT4 interrupt priority level setting.
- */
-#if !defined(LPC13xx_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC13xx_GPT_CT32B1_IRQ_PRIORITY     2
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !LPC13xx_GPT_USE_CT16B0 && !LPC13xx_GPT_USE_CT16B1 &&                   \
-    !LPC13xx_GPT_USE_CT32B0 && !LPC13xx_GPT_USE_CT32B1
-#error "GPT driver activated but no CT peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Timer base clock.
-   */
-  uint32_t                  clock;
-  /**
-   * @brief Pointer to the CTxxBy registers block.
-   */
-  LPC_TMR_TypeDef           *tmr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC13xx_GPT_USE_CT16B0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if LPC13xx_GPT_USE_CT16B1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if LPC13xx_GPT_USE_CT32B0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#if LPC13xx_GPT_USE_CT32B1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/hal_lld.c b/os/hal/platforms/LPC13xx/hal_lld.c
deleted file mode 100644
index 561537537..000000000
--- a/os/hal/platforms/LPC13xx/hal_lld.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/hal_lld.c
- * @brief   LPC13xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/**
- * @brief   Register missing in NXP header file.
- */
-#define FLASHCFG (*((volatile uint32_t *)0x4003C010))
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* SysTick initialization using the system clock.*/
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
-  SysTick->LOAD = LPC13xx_SYSCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
- * @brief   LPC13xx clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void LPC13xx_clock_init(void) {
-  unsigned i;
-
-  /* Flash wait states setting, the code takes care to not touch TBD bits.*/
-  FLASHCFG = (FLASHCFG & ~3) | LPC13xx_FLASHCFG_FLASHTIM;
-
-  /* System oscillator initialization if required.*/
-#if LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-#if LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC
-  LPC_SYSCON->SYSOSCCTRL = LPC13xx_SYSOSCCTRL;
-  LPC_SYSCON->PDRUNCFG &= ~(1 << 5);            /* System oscillator ON.    */
-  for (i = 0; i < 200; i++)
-    __NOP();                                    /* Stabilization delay.     */
-#endif /* LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */
-
-  /* PLL initialization if required.*/
-  LPC_SYSCON->SYSPLLCLKSEL = LPC13xx_PLLCLK_SOURCE;
-  LPC_SYSCON->SYSPLLCLKUEN = 1;                 /* Really required?         */
-  LPC_SYSCON->SYSPLLCLKUEN = 0;
-  LPC_SYSCON->SYSPLLCLKUEN = 1;
-  LPC_SYSCON->SYSPLLCTRL = LPC13xx_SYSPLLCTRL_MSEL | LPC13xx_SYSPLLCTRL_PSEL;
-  LPC_SYSCON->PDRUNCFG &= ~(1 << 7);            /* System PLL ON.           */
-  while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0)     /* Wait PLL lock.           */
-    ;
-#endif /* LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */
-
-  /* Main clock source selection.*/
-  LPC_SYSCON->MAINCLKSEL = LPC13xx_MAINCLK_SOURCE;
-  LPC_SYSCON->MAINCLKUEN = 1;                   /* Really required?         */
-  LPC_SYSCON->MAINCLKUEN = 0;
-  LPC_SYSCON->MAINCLKUEN = 1;
-  while ((LPC_SYSCON->MAINCLKUEN & 1) == 0)     /* Wait switch completion.  */
-    ;
-
-  /* ABH divider initialization, peripheral clocks are initially disabled,
-     the various device drivers will handle their own setup except GPIO and
-     IOCON that are left enabled.*/
-  LPC_SYSCON->SYSAHBCLKDIV = LPC13xx_SYSABHCLK_DIV;
-  LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F;
-
-  /* Memory remapping, vectors always in ROM.*/
-  LPC_SYSCON->SYSMEMREMAP = 2;
-}
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/hal_lld.h b/os/hal/platforms/LPC13xx/hal_lld.h
deleted file mode 100644
index 0fd17871c..000000000
--- a/os/hal/platforms/LPC13xx/hal_lld.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/hal_lld.h
- * @brief   HAL subsystem low level driver header template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "LPC13xx.h"
-#include "nvic.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME           "LPC13xx"
-
-#define IRCOSCCLK               12000000    /**< High speed internal clock. */
-#define WDGOSCCLK               1600000     /**< Watchdog internal clock.   */
-
-#define SYSPLLCLKSEL_IRCOSC     0           /**< Internal RC oscillator
-                                                 clock source.              */
-#define SYSPLLCLKSEL_SYSOSC     1           /**< System oscillator clock
-                                                 source.                    */
-
-#define SYSMAINCLKSEL_IRCOSC    0           /**< Clock source is IRC.       */
-#define SYSMAINCLKSEL_PLLIN     1           /**< Clock source is PLLIN.     */
-#define SYSMAINCLKSEL_WDGOSC    2           /**< Clock source is WDGOSC.    */
-#define SYSMAINCLKSEL_PLLOUT    3           /**< Clock source is PLLOUT.    */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   System PLL clock source.
- */
-#if !defined(LPC13xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC13xx_PLLCLK_SOURCE               SYSPLLCLKSEL_SYSOSC
-#endif
-
-/**
- * @brief   System PLL multiplier.
- * @note    The value must be in the 1..32 range and the final frequency
- *          must not exceed the CCO ratings.
- */
-#if !defined(LPC13xx_SYSPLL_MUL) || defined(__DOXYGEN__)
-#define LPC13xx_SYSPLL_MUL                  6
-#endif
-
-/**
- * @brief   System PLL divider.
- * @note    The value must be chosen between (2, 4, 8, 16).
- */
-#if !defined(LPC13xx_SYSPLL_DIV) || defined(__DOXYGEN__)
-#define LPC13xx_SYSPLL_DIV                  4
-#endif
-
-/**
- * @brief   System main clock source.
- */
-#if !defined(LPC13xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC13xx_MAINCLK_SOURCE              SYSMAINCLKSEL_PLLOUT
-#endif
-
-/**
- * @brief   AHB clock divider.
- * @note    The value must be chosen between (1...255).
- */
-#if !defined(LPC13xx_SYSCLK_DIV) || defined(__DOXYGEN__)
-#define LPC13xx_SYSABHCLK_DIV               1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Calculated SYSOSCCTRL setting.
- */
-#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__)
-#define LPC13xx_SYSOSCCTRL      0
-#else
-#define LPC13xx_SYSOSCCTRL      1
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
-#define LPC13xx_SYSPLLCLKIN     SYSOSCCLK
-#elif LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC
-#define LPC13xx_SYSPLLCLKIN     IRCOSCCLK
-#else
-#error "invalid LPC13xx_PLLCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   MSEL mask in SYSPLLCTRL register.
- */
-#if (LPC13xx_SYSPLL_MUL >= 1) && (LPC13xx_SYSPLL_MUL <= 32) ||              \
-    defined(__DOXYGEN__)
-#define LPC13xx_SYSPLLCTRL_MSEL (LPC13xx_SYSPLL_MUL - 1)
-#else
-#error "LPC13xx_SYSPLL_MUL out of range (1...32)"
-#endif
-
-/**
- * @brief   PSEL mask in SYSPLLCTRL register.
- */
-#if (LPC13xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
-#define LPC13xx_SYSPLLCTRL_PSEL (0 << 5)
-#elif LPC13xx_SYSPLL_DIV == 4
-#define LPC13xx_SYSPLLCTRL_PSEL (1 << 5)
-#elif LPC13xx_SYSPLL_DIV == 8
-#define LPC13xx_SYSPLLCTRL_PSEL (2 << 5)
-#elif LPC13xx_SYSPLL_DIV == 16
-#define LPC13xx_SYSPLLCTRL_PSEL (3 << 5)
-#else
-#error "invalid LPC13xx_SYSPLL_DIV value (2,4,8,16)"
-#endif
-
-/**
- * @brief   CCP frequency.
- */
-#define  LPC13xx_SYSPLLCCO   (LPC13xx_SYSPLLCLKIN * LPC13xx_SYSPLL_MUL *    \
-                              LPC13xx_SYSPLL_DIV)
-
-#if (LPC13xx_SYSPLLCCO < 156000000) || (LPC13xx_SYSPLLCCO > 320000000)
-#error "CCO frequency out of the acceptable range (156...320)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define  LPC13xx_SYSPLLCLKOUT   (LPC13xx_SYSPLLCCO / LPC13xx_SYSPLL_DIV)
-
-#if (LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__)
-#define LPC13xx_MAINCLK     IRCOSCCLK
-#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
-#define LPC13xx_MAINCLK     LPC13xx_SYSPLLCLKIN
-#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
-#define LPC13xx_MAINCLK     WDGOSCCLK
-#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-#define LPC13xx_MAINCLK     LPC13xx_SYSPLLCLKOUT
-#else
-#error "invalid LPC13xx_MAINCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   AHB clock.
- */
-#define  LPC13xx_SYSCLK     (LPC13xx_MAINCLK / LPC13xx_SYSABHCLK_DIV)
-#if LPC13xx_SYSCLK > 72000000
-#error "AHB clock frequency out of the acceptable range (72MHz max)"
-#endif
-
-/**
- * @brief   Flash wait states.
- */
-#if (LPC13xx_SYSCLK <= 20000000) || defined(__DOXYGEN__)
-#define LPC13xx_FLASHCFG_FLASHTIM   0
-#elif LPC13xx_SYSCLK <= 40000000
-#define LPC13xx_FLASHCFG_FLASHTIM   1
-#else
-#define LPC13xx_FLASHCFG_FLASHTIM   2
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void LPC13xx_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/pal_lld.c b/os/hal/platforms/LPC13xx/pal_lld.c
deleted file mode 100644
index 42a446b44..000000000
--- a/os/hal/platforms/LPC13xx/pal_lld.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/pal_lld.c
- * @brief   LPC13xx GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-/**
- * @brief   LPC13xx I/O ports configuration.
- * @details GPIO unit registers initialization.
- *
- * @param[in] config    the LPC13xx ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  LPC_GPIO0->DIR = config->P0.dir;
-  LPC_GPIO1->DIR = config->P1.dir;
-  LPC_GPIO2->DIR = config->P2.dir;
-  LPC_GPIO3->DIR = config->P3.dir;
-  LPC_GPIO0->DATA = config->P0.data;
-  LPC_GPIO1->DATA = config->P1.data;
-  LPC_GPIO2->DATA = config->P2.data;
-  LPC_GPIO3->DATA = config->P3.data;
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    This function does not alter the @p PINSELx registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    port->DIR &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    palSetPort(port, PAL_WHOLE_PORT);
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->DIR |=  mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/pal_lld.h b/os/hal/platforms/LPC13xx/pal_lld.h
deleted file mode 100644
index a8df95e12..000000000
--- a/os/hal/platforms/LPC13xx/pal_lld.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/pal_lld.h
- * @brief   LPC13xx GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port setup info.
- */
-typedef struct {
-  /** Initial value for FIO_PIN register.*/
-  uint32_t      data;
-  /** Initial value for FIO_DIR register.*/
-  uint32_t      dir;
-} lpc13xx_gpio_setup_t;
-
-/**
- * @brief   GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    The @p IOCON block is not configured, initially all pins have
- *          enabled pullups and are programmed as GPIO. It is responsibility
- *          of the various drivers to reprogram the pins in the proper mode.
- *          Pins that are not handled by any driver may be programmed in
- *          @p board.c.
- */
-typedef struct {
-  /** @brief GPIO 0 setup data.*/
-  lpc13xx_gpio_setup_t   P0;
-  /** @brief GPIO 1 setup data.*/
-  lpc13xx_gpio_setup_t   P1;
-  /** @brief GPIO 2 setup data.*/
-  lpc13xx_gpio_setup_t   P2;
-  /** @brief GPIO 3 setup data.*/
-  lpc13xx_gpio_setup_t   P3;
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef LPC_GPIO_TypeDef *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO0 port identifier.
- */
-#define IOPORT1         LPC_GPIO0
-#define GPIO0           LPC_GPIO0
-
-/**
- * @brief   GPIO1 port identifier.
- */
-#define IOPORT2         LPC_GPIO1
-#define GPIO1           LPC_GPIO1
-
-/**
- * @brief   GPIO2 port identifier.
- */
-#define IOPORT3         LPC_GPIO2
-#define GPIO2           LPC_GPIO2
-
-/**
- * @brief   GPIO3 port identifier.
- */
-#define IOPORT4         LPC_GPIO3
-#define GPIO3           LPC_GPIO3
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->DATA)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->DATA)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->DATA = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF)
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0)
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset)                               \
-  ((port)->MASKED_ACCESS[(mask) << (offset)])
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                        \
-  ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)                                    \
-  ((port)->MASKED_ACCESS[1 << (pad)] = (bit) << (pad))
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-  ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-  ((port)->MASKED_ACCESS[1 << (pad)] = 0)
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/platform.dox b/os/hal/platforms/LPC13xx/platform.dox
deleted file mode 100644
index bda4ceb5c..000000000
--- a/os/hal/platforms/LPC13xx/platform.dox
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup LPC13xx LPC13xx Drivers
- * @details This section describes all the supported drivers on the LPC13xx
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup LPC13xx_HAL LPC13xx Initialization Support
- * @details The LPC13xx HAL support is responsible for system initialization.
- *
- * @section lpc13xx_hal_1 Supported HW resources
- * - SYSCON.
- * - Flash.
- * .
- * @section lpc13xx_hal_2 LPC13xx HAL driver implementation features
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash controller initialization.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * .
- * @ingroup LPC13xx
- */
-
-/**
- * @defgroup LPC13xx_GPT LPC13xx GPT Support
- * @details The LPC13xx GPT driver uses the CTxxBy peripherals.
- *
- * @section lpc13xx_gpt_1 Supported HW resources
- * - CT16B0.
- * - CT16B1.
- * - CT32B0.
- * - CT32B1.
- * .
- * @section lpc13xx_gpt_2 LPC13xx GPT driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable CTxxBy interrupts priority level.
- * .
- * @ingroup LPC13xx
- */
-
-/**
- * @defgroup LPC13xx_PAL LPC13xx PAL Support
- * @details The LPC13xx PAL driver uses the GPIO peripherals.
- *
- * @section lpc13xx_pal_1 Supported HW resources
- * - GPIO0.
- * - GPIO1.
- * - GPIO2.
- * - GPIO3.
- * .
- * @section lpc13xx_pal_2 LPC13xx PAL driver implementation features
- * - 12 bits wide ports.
- * - Atomic set/reset functions.
- * - Atomic set+reset function (atomic bus operations).
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section lpc13xx_pal_3 Supported PAL setup modes
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section lpc13xx_pal_4 Suboptimal behavior
- * Some GPIO features are less than optimal:
- * - Pad/port toggling operations are not atomic.
- * - Pull-up and Pull-down resistors cannot be programmed through the PAL
- *   driver and must be programmed separately using the IOCON peripheral.
- * - Reading of the output latch for pads programmed as input is not possible,
- *   the input pin value is returned instead.
- * .
- * @ingroup LPC13xx
- */
-
-/**
- * @defgroup LPC13xx_SERIAL LPC13xx Serial Support
- * @details The LPC13xx Serial driver uses the UART peripheral in a
- *          buffered, interrupt driven, implementation. The serial driver
- *          also takes advantage of the LPC13xx UARTs deep hardware buffers.
- *
- * @section lpc13xx_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - UART.
- * .
- * @section lpc13xx_serial_2 LPC13xx Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Fully interrupt driven.
- * - Programmable priority level.
- * - Takes advantage of the input and output FIFOs.
- * .
- * @ingroup LPC13xx
- */
-
-/**
- * @defgroup LPC13xx_SPI LPC13xx SPI Support
- * @details The SPI driver supports the LPC13xx SSP peripherals in an interrupt
- *          driven implementation.
- * @note    Being the SPI a fast peripheral, much care must be taken to
- *          not saturate the CPU bandwidth with an excessive IRQ rate. The
- *          maximum transfer bit rate is likely limited by the IRQ
- *          handling.
- *
- * @section lpc13xx_spi_1 Supported HW resources
- * - SSP0.
- * - SSP1 (where present).
- * .
- * @section lpc13xx_spi_2 LPC13xx SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SSP can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable interrupt priority levels for each SSP.
- * .
- * @ingroup LPC13xx
- */
diff --git a/os/hal/platforms/LPC13xx/platform.mk b/os/hal/platforms/LPC13xx/platform.mk
deleted file mode 100644
index 1171af7d7..000000000
--- a/os/hal/platforms/LPC13xx/platform.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-# List of all the LPC13xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC13xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC13xx/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC13xx/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC13xx/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC13xx/spi_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC13xx
diff --git a/os/hal/platforms/LPC13xx/serial_lld.c b/os/hal/platforms/LPC13xx/serial_lld.c
deleted file mode 100644
index 3b59238d5..000000000
--- a/os/hal/platforms/LPC13xx/serial_lld.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/serial_lld.c
- * @brief   LPC13xx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC13xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  LCR_WL8 | LCR_STOP1 | LCR_NOPARITY,
-  FCR_TRIGGER0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   UART initialization.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
-  LPC_UART_TypeDef *u = sdp->uart;
-
-  uint32_t div = LPC13xx_SERIAL_UART0_PCLK / (config->sc_speed << 4);
-  u->LCR = config->sc_lcr | LCR_DLAB;
-  u->DLL = div;
-  u->DLM = div >> 8;
-  u->LCR = config->sc_lcr;
-  u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr;
-  u->ACR = 0;
-  u->FDR = 0x10;
-  u->TER = TER_ENABLE;
-  u->IER = IER_RBR | IER_STATUS;
-}
-
-/**
- * @brief   UART de-initialization.
- *
- * @param[in] u         pointer to an UART I/O block
- */
-static void uart_deinit(LPC_UART_TypeDef *u) {
-
-  u->LCR = LCR_DLAB;
-  u->DLL = 1;
-  u->DLM = 0;
-  u->LCR = 0;
-  u->FDR = 0x10;
-  u->IER = 0;
-  u->FCR = FCR_RXRESET | FCR_TXRESET;
-  u->ACR = 0;
-  u->TER = TER_ENABLE;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] err       UART LSR register value
- */
-static void set_error(SerialDriver *sdp, IOREG32 err) {
-  flagsmask_t sts = 0;
-
-  if (err & LSR_OVERRUN)
-    sts |= SD_OVERRUN_ERROR;
-  if (err & LSR_PARITY)
-    sts |= SD_PARITY_ERROR;
-  if (err & LSR_FRAMING)
-    sts |= SD_FRAMING_ERROR;
-  if (err & LSR_BREAK)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- * @note    Tries hard to clear all the pending interrupt sources, we don't
- *          want to go through the whole ISR and have another interrupt soon
- *          after.
- *
- * @param[in] u         pointer to an UART I/O block
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  LPC_UART_TypeDef *u = sdp->uart;
-
-  while (TRUE) {
-    switch (u->IIR & IIR_SRC_MASK) {
-    case IIR_SRC_NONE:
-      return;
-    case IIR_SRC_ERROR:
-      set_error(sdp, u->LSR);
-      break;
-    case IIR_SRC_TIMEOUT:
-    case IIR_SRC_RX:
-      chSysLockFromIsr();
-      if (chIQIsEmptyI(&sdp->iqueue))
-        chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
-      chSysUnlockFromIsr();
-      while (u->LSR & LSR_RBR_FULL) {
-        chSysLockFromIsr();
-        if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK)
-          chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
-        chSysUnlockFromIsr();
-      }
-      break;
-    case IIR_SRC_TX:
-      {
-        int i = LPC13xx_SERIAL_FIFO_PRELOAD;
-        do {
-          msg_t b;
-
-          chSysLockFromIsr();
-          b = chOQGetI(&sdp->oqueue);
-          chSysUnlockFromIsr();
-          if (b < Q_OK) {
-            u->IER &= ~IER_THRE;
-            chSysLockFromIsr();
-            chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-            chSysUnlockFromIsr();
-            break;
-          }
-          u->THR = b;
-        } while (--i);
-      }
-      break;
-    default:
-      (void) u->THR;
-      (void) u->RBR;
-    }
-  }
-}
-
-/**
- * @brief   Attempts a TX FIFO preload.
- */
-static void preload(SerialDriver *sdp) {
-  LPC_UART_TypeDef *u = sdp->uart;
-
-  if (u->LSR & LSR_THRE) {
-    int i = LPC13xx_SERIAL_FIFO_PRELOAD;
-    do {
-      msg_t b = chOQGetI(&sdp->oqueue);
-      if (b < Q_OK) {
-        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-        return;
-      }
-      u->THR = b;
-    } while (--i);
-  }
-  u->IER |= IER_THRE;
-}
-
-/**
- * @brief   Driver SD1 output notification.
- */
-#if LPC13xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD1);
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 IRQ handler.
- *
- * @isr
- */
-#if LPC13xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(VectorF8) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if LPC13xx_SERIAL_USE_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = LPC_UART;
-  LPC_IOCON->PIO1_6 = 0xC1;                 /* RDX without resistors.       */
-  LPC_IOCON->PIO1_7 = 0xC1;                 /* TDX without resistors.       */
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if LPC13xx_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
-      LPC_SYSCON->UARTCLKDIV = LPC13xx_SERIAL_UART0CLKDIV;
-      nvicEnableVector(UART_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC13xx_SERIAL_UART0_IRQ_PRIORITY));
-    }
-#endif
-  }
-  uart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the UART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    uart_deinit(sdp->uart);
-#if LPC13xx_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->UARTCLKDIV = 0;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12);
-      nvicDisableVector(UART_IRQn);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/serial_lld.h b/os/hal/platforms/LPC13xx/serial_lld.h
deleted file mode 100644
index cbc00d3f8..000000000
--- a/os/hal/platforms/LPC13xx/serial_lld.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/serial_lld.h
- * @brief   LPC13xx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define IIR_SRC_MASK    0x0F
-#define IIR_SRC_NONE    0x01
-#define IIR_SRC_MODEM   0x00
-#define IIR_SRC_TX      0x02
-#define IIR_SRC_RX      0x04
-#define IIR_SRC_ERROR   0x06
-#define IIR_SRC_TIMEOUT 0x0C
-
-#define IER_RBR         1
-#define IER_THRE        2
-#define IER_STATUS      4
-
-#define LCR_WL5         0
-#define LCR_WL6         1
-#define LCR_WL7         2
-#define LCR_WL8         3
-#define LCR_STOP1       0
-#define LCR_STOP2       4
-#define LCR_NOPARITY    0
-#define LCR_PARITYODD   0x08
-#define LCR_PARITYEVEN  0x18
-#define LCR_PARITYONE   0x28
-#define LCR_PARITYZERO  0x38
-#define LCR_BREAK_ON    0x40
-#define LCR_DLAB        0x80
-
-#define FCR_ENABLE      1
-#define FCR_RXRESET     2
-#define FCR_TXRESET     4
-#define FCR_TRIGGER0    0
-#define FCR_TRIGGER1    0x40
-#define FCR_TRIGGER2    0x80
-#define FCR_TRIGGER3    0xC0
-
-#define LSR_RBR_FULL    1
-#define LSR_OVERRUN     2
-#define LSR_PARITY      4
-#define LSR_FRAMING     8
-#define LSR_BREAK       0x10
-#define LSR_THRE        0x20
-#define LSR_TEMT        0x40
-#define LSR_RXFE        0x80
-
-#define TER_ENABLE      0x80
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC13xx_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define LPC13xx_SERIAL_USE_UART0            TRUE
-#endif
-
-/**
- * @brief   FIFO preload parameter.
- * @details Configuration parameter, this values defines how many bytes are
- *          preloaded in the HW transmit FIFO for each interrupt, the maximum
- *          value is 16 the minimum is 1.
- * @note    An high value reduces the number of interrupts generated but can
- *          also increase the worst case interrupt response time because the
- *          preload loops.
- */
-#if !defined(LPC13xx_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__)
-#define LPC13xx_SERIAL_FIFO_PRELOAD         16
-#endif
-
-/**
- * @brief   UART0 PCLK divider.
- */
-#if !defined(LPC13xx_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__)
-#define LPC13xx_SERIAL_UART0CLKDIV          1
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(LPC13xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC13xx_SERIAL_UART0_IRQ_PRIORITY   3
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC13xx_SERIAL_UART0CLKDIV < 1) || (LPC11xx_SERIAL_UART0CLKDIV > 255)
-#error "invalid LPC13xx_SERIAL_UART0CLKDIV setting"
-#endif
-
-#if (LPC13xx_SERIAL_FIFO_PRELOAD < 1) || (LPC13xx_SERIAL_FIFO_PRELOAD > 16)
-#error "invalid LPC13xx_SERIAL_FIFO_PRELOAD setting"
-#endif
-
-/**
- * @brief   UART0 clock.
- */
-#define  LPC13xx_SERIAL_UART0_PCLK                                          \
-  (LPC13xx_MAINCLK / LPC13xx_SERIAL_UART0CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   LPC13xx Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the LCR register.
-   */
-  uint32_t                  sc_lcr;
-  /**
-   * @brief Initialization value for the FCR register.
-   */
-  uint32_t                  sc_fcr;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  LPC_UART_TypeDef        *uart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC13xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/spi_lld.c b/os/hal/platforms/LPC13xx/spi_lld.c
deleted file mode 100644
index 3b8ad65b6..000000000
--- a/os/hal/platforms/LPC13xx/spi_lld.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/spi_lld.c
- * @brief   LPC13xx low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC13xx_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-#if LPC13xx_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/** @brief SPI2 driver identifier.*/
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Preloads the transmit FIFO.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void ssp_fifo_preload(SPIDriver *spip) {
-  LPC_SSP_TypeDef *ssp = spip->ssp;
-  uint32_t n = spip->txcnt > LPC13xx_SSP_FIFO_DEPTH ?
-               LPC13xx_SSP_FIFO_DEPTH : spip->txcnt;
-
-  while(((ssp->SR & SR_TNF) != 0) && (n > 0)) {
-    if (spip->txptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        const uint16_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-      else {
-        const uint8_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-    }
-    else
-      ssp->DR = 0xFFFFFFFF;
-    n--;
-    spip->txcnt--;
-  }
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void spi_serve_interrupt(SPIDriver *spip) {
-  LPC_SSP_TypeDef *ssp = spip->ssp;
-
-  if ((ssp->MIS & MIS_ROR) != 0) {
-    /* The overflow condition should never happen because priority is given
-       to receive but a hook macro is provided anyway...*/
-    LPC13xx_SPI_SSP_ERROR_HOOK(spip);
-  }
-  ssp->ICR = ICR_RT | ICR_ROR;
-  while ((ssp->SR & SR_RNE) != 0) {
-    if (spip->rxptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        uint16_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-      else {
-        uint8_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-    }
-    else
-      (void)ssp->DR;
-    if (--spip->rxcnt == 0) {
-      chDbgAssert(spip->txcnt == 0,
-                  "spi_serve_interrupt(), #1", "counter out of synch");
-      /* Stops the IRQ sources.*/
-      ssp->IMSC = 0;
-      /* Portable SPI ISR code defined in the high level driver, note, it is
-         a macro.*/
-      _spi_isr_code(spip);
-      return;
-    }
-  }
-  ssp_fifo_preload(spip);
-  if (spip->txcnt == 0)
-    ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC13xx_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/**
- * @brief   SSP0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorF4) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC13xx_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/**
- * @brief   SSP1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector124) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if LPC13xx_SPI_USE_SSP0
-  spiObjectInit(&SPID1);
-  SPID1.ssp = LPC_SSP0;
-  LPC_IOCON->SCK_LOC = LPC13xx_SPI_SCK0_SELECTOR;
-#if LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_10
-  LPC_IOCON->SWCLK_PIO0_10 = 0xC2;          /* SCK0 without resistors.      */
-#elif LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO2_11
-  LPC_IOCON->PIO2_11 = 0xC1;                /* SCK0 without resistors.      */
-#else /* LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_6 */
-  LPC_IOCON->PIO0_6  = 0xC2;                /* SCK0 without resistors.      */
-#endif
-  LPC_IOCON->PIO0_8  = 0xC1;                /* MISO0 without resistors.     */
-  LPC_IOCON->PIO0_9  = 0xC1;                /* MOSI0 without resistors.     */
-#endif /* LPC13xx_SPI_USE_SSP0 */
-
-#if LPC13xx_SPI_USE_SSP1
-  spiObjectInit(&SPID2);
-  SPID2.ssp = LPC_SSP1;
-  LPC_IOCON->PIO2_1  = 0xC2;                /* SCK1 without resistors.      */
-  LPC_IOCON->PIO2_2  = 0xC2;                /* MISO1 without resistors.     */
-  LPC_IOCON->PIO2_3  = 0xC2;                /* MOSI1 without resistors.     */
-#endif /* LPC13xx_SPI_USE_SSP0 */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-    /* Clock activation.*/
-#if LPC13xx_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SYSCON->SSP0CLKDIV = LPC13xx_SPI_SSP0CLKDIV;
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11);
-      LPC_SYSCON->PRESETCTRL |= 1;
-      nvicEnableVector(SSP0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC13xx_SPI_SSP0_IRQ_PRIORITY));
-    }
-#endif
-#if LPC13xx_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_SYSCON->SSP1CLKDIV = LPC13xx_SPI_SSP1CLKDIV;
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18);
-      LPC_SYSCON->PRESETCTRL |= 4;
-      nvicEnableVector(SSP1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC13xx_SPI_SSP1_IRQ_PRIORITY));
-    }
-#endif
-  }
-  /* Configuration.*/
-  spip->ssp->CR1  = 0;
-  spip->ssp->ICR  = ICR_RT | ICR_ROR;
-  spip->ssp->CR0  = spip->config->cr0;
-  spip->ssp->CPSR = spip->config->cpsr;
-  spip->ssp->CR1  = CR1_SSE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state != SPI_STOP) {
-    spip->ssp->CR1  = 0;
-    spip->ssp->CR0  = 0;
-    spip->ssp->CPSR = 0;
-#if LPC13xx_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SYSCON->PRESETCTRL &= ~1;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11);
-      LPC_SYSCON->SSP0CLKDIV = 0;
-      nvicDisableVector(SSP0_IRQn);
-    }
-#endif
-#if LPC13xx_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_SYSCON->PRESETCTRL &= ~4;
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18);
-      LPC_SYSCON->SSP1CLKDIV = 0;
-      nvicDisableVector(SSP1_IRQn);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->rxptr = NULL;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->rxptr = NULL;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->ssp->DR = (uint32_t)frame;
-  while ((spip->ssp->SR & SR_RNE) == 0)
-    ;
-  return (uint16_t)spip->ssp->DR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/spi_lld.h b/os/hal/platforms/LPC13xx/spi_lld.h
deleted file mode 100644
index 9328cd69d..000000000
--- a/os/hal/platforms/LPC13xx/spi_lld.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC13xx/spi_lld.h
- * @brief   LPC13xx low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Hardware FIFO depth.
- */
-#define LPC13xx_SSP_FIFO_DEPTH  8
-
-#define CR0_DSSMASK             0x0F
-#define CR0_DSS4BIT             3
-#define CR0_DSS5BIT             4
-#define CR0_DSS6BIT             5
-#define CR0_DSS7BIT             6
-#define CR0_DSS8BIT             7
-#define CR0_DSS9BIT             8
-#define CR0_DSS10BIT            9
-#define CR0_DSS11BIT            0xA
-#define CR0_DSS12BIT            0xB
-#define CR0_DSS13BIT            0xC
-#define CR0_DSS14BIT            0xD
-#define CR0_DSS15BIT            0xE
-#define CR0_DSS16BIT            0xF
-#define CR0_FRFSPI              0
-#define CR0_FRFSSI              0x10
-#define CR0_FRFMW               0x20
-#define CR0_CPOL                0x40
-#define CR0_CPHA                0x80
-#define CR0_CLOCKRATE(n)        ((n) << 8)
-
-#define CR1_LBM                 1
-#define CR1_SSE                 2
-#define CR1_MS                  4
-#define CR1_SOD                 8
-
-#define SR_TFE                  1
-#define SR_TNF                  2
-#define SR_RNE                  4
-#define SR_RFF                  8
-#define SR_BSY                  16
-
-#define IMSC_ROR                1
-#define IMSC_RT                 2
-#define IMSC_RX                 4
-#define IMSC_TX                 8
-
-#define RIS_ROR                 1
-#define RIS_RT                  2
-#define RIS_RX                  4
-#define RIS_TX                  8
-
-#define MIS_ROR                 1
-#define MIS_RT                  2
-#define MIS_RX                  4
-#define MIS_TX                  8
-
-#define ICR_ROR                 1
-#define ICR_RT                  2
-
-/**
- * @brief   SCK0 signal assigned to pin PIO0_10.
- */
-#define SCK0_IS_PIO0_10         0
-
-/**
- * @brief   SCK0 signal assigned to pin PIO2_11.
- */
-#define SCK0_IS_PIO2_11         1
-
-/**
- * @brief   SCK0 signal assigned to pin PIO0_6.
- */
-#define SCK0_IS_PIO0_6          2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for device SSP0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC13xx_SPI_USE_SSP0) || defined(__DOXYGEN__)
-#define LPC13xx_SPI_USE_SSP0                TRUE
-#endif
-
-/**
- * @brief   SPI2 driver enable switch.
- * @details If set to @p TRUE the support for device SSP1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC13xx_SPI_USE_SSP1) || defined(__DOXYGEN__)
-#define LPC13xx_SPI_USE_SSP1                FALSE
-#endif
-
-/**
- * @brief   SSP0 PCLK divider.
- */
-#if !defined(LPC13xx_SPI_SSP0CLKDIV) || defined(__DOXYGEN__)
-#define LPC13xx_SPI_SSP0CLKDIV              1
-#endif
-
-/**
- * @brief   SSP1 PCLK divider.
- */
-#if !defined(LPC13xx_SPI_SSP1CLKDIV) || defined(__DOXYGEN__)
-#define LPC13xx_SPI_SSP1CLKDIV              1
-#endif
-
-/**
- * @brief   SPI0 interrupt priority level setting.
- */
-#if !defined(LPC13xx_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC13xx_SPI_SSP0_IRQ_PRIORITY       5
-#endif
-
-/**
- * @brief   SPI1 interrupt priority level setting.
- */
-#if !defined(LPC13xx_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC13xx_SPI_SSP1_IRQ_PRIORITY       5
-#endif
-
-/**
- * @brief   Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(LPC13xx_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__)
-#define LPC13xx_SPI_SSP_ERROR_HOOK(spip)    chSysHalt()
-#endif
-
-/**
- * @brief   SCK0 signal selector.
- */
-#if !defined(LPC13xx_SPI_SCK0_SELECTOR) || defined(__DOXYGEN__)
-#define LPC13xx_SPI_SCK0_SELECTOR           SCK0_IS_PIO2_11
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC13xx_SPI_SSP0CLKDIV < 1) || (LPC13xx_SPI_SSP0CLKDIV > 255)
-#error "invalid LPC13xx_SPI_SSP0CLKDIV setting"
-#endif
-
-#if (LPC13xx_SPI_SSP1CLKDIV < 1) || (LPC13xx_SPI_SSP1CLKDIV > 255)
-#error "invalid LPC13xx_SPI_SSP1CLKDIV setting"
-#endif
-
-#if !LPC13xx_SPI_USE_SSP0 && !LPC13xx_SPI_USE_SSP1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-#if (LPC13xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_10) &&                       \
-    (LPC13xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO2_11) &&                       \
-    (LPC13xx_SPI_SCK0_SELECTOR != SCK0_IS_PIO0_6)
-#error "invalid pin assigned to SCK0 signal"
-#endif
-
-/**
- * @brief   SSP0 clock.
- */
-#define LPC13xx_SPI_SSP0_PCLK                                               \
-  (LPC13xx_MAINCLK / LPC13xx_SPI_SSP0CLKDIV)
-
-/**
- * @brief   SSP1 clock.
- */
-#define LPC13xx_SPI_SSP1_PCLK                                               \
-  (LPC13xx_MAINCLK / LPC13xx_SPI_SSP1CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief SSP CR0 initialization data.
-   */
-  uint16_t              cr0;
-  /**
-   * @brief SSP CPSR initialization data.
-   */
-  uint32_t              cpsr;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SSP registers block.
-   */
-  LPC_SSP_TypeDef       *ssp;
-  /**
-   * @brief Number of bytes yet to be received.
-   */
-  uint32_t              rxcnt;
-  /**
-   * @brief Receive pointer or @p NULL.
-   */
-  void                  *rxptr;
-  /**
-   * @brief Number of bytes yet to be transmitted.
-   */
-  uint32_t              txcnt;
-  /**
-   * @brief Transmit pointer or @p NULL.
-   */
-  const void            *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC13xx_SPI_USE_SSP0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if LPC13xx_SPI_USE_SSP1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC13xx/system_LPC13xx.h b/os/hal/platforms/LPC13xx/system_LPC13xx.h
deleted file mode 100644
index 812f12365..000000000
--- a/os/hal/platforms/LPC13xx/system_LPC13xx.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC13xx.h
- * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Header File
- *           for the NXP LPC13xx Device Series
- * @version  V1.10
- * @date     24. November 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC13xx_H
-#define __SYSTEM_LPC13xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC13xx_H */
diff --git a/os/hal/platforms/LPC17xx/LPC17xx.h b/os/hal/platforms/LPC17xx/LPC17xx.h
deleted file mode 100644
index cdf5d3b7e..000000000
--- a/os/hal/platforms/LPC17xx/LPC17xx.h
+++ /dev/null
@@ -1,999 +0,0 @@
-/******************************************************************************
- * @file:    LPC17xx.h
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 
- *           NXP LPC17xx Device Series 
- * @version: V1.10
- * @date:    24. September 2010
- *----------------------------------------------------------------------------
- *
- * @note
- * Copyright (C) 2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __LPC17xx_H__
-#define __LPC17xx_H__
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-/** @addtogroup LPC17xx_System
- * @{
- */
-
-/** @brief IRQ interrupt source definition */
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
-  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
-  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
-  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
-
-/******  LPC17xx Specific Interrupt Numbers *******************************************************/
-  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
-  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
-  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
-  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
-  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
-  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
-  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
-  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
-  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
-  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
-  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
-  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
-  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
-  SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */
-  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
-  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
-  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
-  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
-  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
-  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
-  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
-  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
-  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
-  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
-  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
-  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
-  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
-  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
-  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
-  RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */
-  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
-  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
-  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
-  USBActivity_IRQn              = 33,       /*!< USB Activity Interrupt(For wakeup only)          */
-  CANActivity_IRQn              = 34        /*!< CAN Activity Interrupt(For wakeup only)          */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-
-#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
-#include "system_LPC17xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SC) ------------------------------------------*/
-/** @brief System Control (SC) register structure definition */
-typedef struct
-{
-  __IO uint32_t FLASHCFG;                   /*!< Offset: 0x000 (R/W)  Flash Accelerator Configuration Register */
-       uint32_t RESERVED0[31];
-  __IO uint32_t PLL0CON;                    /*!< Offset: 0x080 (R/W)  PLL0 Control Register */
-  __IO uint32_t PLL0CFG;                    /*!< Offset: 0x084 (R/W)  PLL0 Configuration Register */
-  __I  uint32_t PLL0STAT;                   /*!< Offset: 0x088 (R/ )  PLL0 Status Register */
-  __O  uint32_t PLL0FEED;                   /*!< Offset: 0x08C ( /W)  PLL0 Feed Register */
-       uint32_t RESERVED1[4];
-  __IO uint32_t PLL1CON;                    /*!< Offset: 0x0A0 (R/W)  PLL1 Control Register */
-  __IO uint32_t PLL1CFG;                    /*!< Offset: 0x0A4 (R/W)  PLL1 Configuration Register */
-  __I  uint32_t PLL1STAT;                   /*!< Offset: 0x0A8 (R/ )  PLL1 Status Register */
-  __O  uint32_t PLL1FEED;                   /*!< Offset: 0x0AC ( /W)  PLL1 Feed Register */
-       uint32_t RESERVED2[4];
-  __IO uint32_t PCON;                       /*!< Offset: 0x0C0 (R/W)  Power Control Register */
-  __IO uint32_t PCONP;                      /*!< Offset: 0x0C4 (R/W)  Power Control for Peripherals Register */
-       uint32_t RESERVED3[15];
-  __IO uint32_t CCLKCFG;                    /*!< Offset: 0x104 (R/W)  CPU Clock Configure Register  */
-  __IO uint32_t USBCLKCFG;                  /*!< Offset: 0x108 (R/W)  USB Clock Configure Register */
-  __IO uint32_t CLKSRCSEL;                  /*!< Offset: 0x10C (R/W)  Clock Source Select Register */
-  __IO uint32_t CANSLEEPCLR;                /*!< Offset: 0x110 (R/W)  CAN Sleep Clear Register */
-  __IO uint32_t CANWAKEFLAGS;               /*!< Offset: 0x114 (R/W)  CAN Wake-up Flags Register */
-       uint32_t RESERVED4[10];
-  __IO uint32_t EXTINT;                     /*!< Offset: 0x140 (R/W)  External Interrupt Flag Register */
-       uint32_t RESERVED5[1];
-  __IO uint32_t EXTMODE;                    /*!< Offset: 0x148 (R/W)  External Interrupt Mode Register */
-  __IO uint32_t EXTPOLAR;                   /*!< Offset: 0x14C (R/W)  External Interrupt Polarity Register */
-       uint32_t RESERVED6[12];
-  __IO uint32_t RSID;                       /*!< Offset: 0x180 (R/W)  Reset Source Identification Register */
-       uint32_t RESERVED7[7];
-  __IO uint32_t SCS;                        /*!< Offset: 0x1A0 (R/W)  System Controls and Status Register */
-  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
-  __IO uint32_t PCLKSEL0;                   /*!< Offset: 0x1A8 (R/W)  Peripheral Clock Select 0 Register */
-  __IO uint32_t PCLKSEL1;                   /*!< Offset: 0x1AC (R/W)  Peripheral Clock Select 1 Register */
-       uint32_t RESERVED8[4];
-  __IO uint32_t USBIntSt;                   /*!< Offset: 0x1C0 (R/W)  USB Interrupt Status Register */
-  __IO uint32_t DMAREQSEL;                  /*!< Offset: 0x1C4 (R/W)  DMA Request Select Register */
-  __IO uint32_t CLKOUTCFG;                  /*!< Offset: 0x1C8 (R/W)  Clock Output Configuration Register */
-
- } LPC_SC_TypeDef;
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-/** @brief Pin Connect Block (PINCON) register structure definition */
-typedef struct
-{
-  __IO uint32_t PINSEL0;				 /* !< Offset: 0x000 PIN Select0 (R/W) */
-  __IO uint32_t PINSEL1;				 /* !< Offset: 0x004 PIN Select1 (R/W) */
-  __IO uint32_t PINSEL2;				 /* !< Offset: 0x008 PIN Select2 (R/W) */
-  __IO uint32_t PINSEL3;				 /* !< Offset: 0x00C PIN Select3 (R/W) */
-  __IO uint32_t PINSEL4;				 /* !< Offset: 0x010 PIN Select4 (R/W) */
-  __IO uint32_t PINSEL5;				 /* !< Offset: 0x014 PIN Select5 (R/W) */
-  __IO uint32_t PINSEL6;				 /* !< Offset: 0x018 PIN Select6 (R/W) */
-  __IO uint32_t PINSEL7;				 /* !< Offset: 0x01C PIN Select7 (R/W) */
-  __IO uint32_t PINSEL8;				 /* !< Offset: 0x020 PIN Select8 (R/W) */
-  __IO uint32_t PINSEL9;				 /* !< Offset: 0x024 PIN Select9 (R/W) */
-  __IO uint32_t PINSEL10;				 /* !< Offset: 0x028 PIN Select20 (R/W) */
-       uint32_t RESERVED0[5];
-  __IO uint32_t PINMODE0;				 /* !< Offset: 0x040 PIN Mode0 (R/W) */
-  __IO uint32_t PINMODE1;				 /* !< Offset: 0x044 PIN Mode1 (R/W) */
-  __IO uint32_t PINMODE2;				 /* !< Offset: 0x048 PIN Mode2 (R/W) */
-  __IO uint32_t PINMODE3;				 /* !< Offset: 0x04C PIN Mode3 (R/W) */
-  __IO uint32_t PINMODE4;				 /* !< Offset: 0x050 PIN Mode4 (R/W) */
-  __IO uint32_t PINMODE5;				 /* !< Offset: 0x054 PIN Mode5 (R/W) */
-  __IO uint32_t PINMODE6;				 /* !< Offset: 0x058 PIN Mode6 (R/W) */
-  __IO uint32_t PINMODE7;				 /* !< Offset: 0x05C PIN Mode7 (R/W) */
-  __IO uint32_t PINMODE8;				 /* !< Offset: 0x060 PIN Mode8 (R/W) */
-  __IO uint32_t PINMODE9;				 /* !< Offset: 0x064 PIN Mode9 (R/W) */
-  __IO uint32_t PINMODE_OD0;			 /* !< Offset: 0x068 Open Drain PIN Mode0 (R/W) */
-  __IO uint32_t PINMODE_OD1;			 /* !< Offset: 0x06C Open Drain PIN Mode1 (R/W) */
-  __IO uint32_t PINMODE_OD2;			 /* !< Offset: 0x070 Open Drain PIN Mode2 (R/W) */
-  __IO uint32_t PINMODE_OD3;			 /* !< Offset: 0x074 Open Drain PIN Mode3 (R/W) */
-  __IO uint32_t PINMODE_OD4;			 /* !< Offset: 0x078 Open Drain PIN Mode4 (R/W) */
-  __IO uint32_t I2CPADCFG;				 /* !< Offset: 0x07C I2C Pad Configure (R/W) */
-} LPC_PINCON_TypeDef;
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-/** @brief General Purpose Input/Output (GPIO) register structure definition */
-typedef struct
-{
-  union {
-    __IO uint32_t FIODIR;				 /* !< Offset: 0x00 Port direction (R/W) */
-    struct {
-      __IO uint16_t FIODIRL;
-      __IO uint16_t FIODIRH;
-    };
-    struct {
-      __IO uint8_t  FIODIR0;
-      __IO uint8_t  FIODIR1;
-      __IO uint8_t  FIODIR2;
-      __IO uint8_t  FIODIR3;
-    };
-  };
-  uint32_t RESERVED0[3];
-  union {
-    __IO uint32_t FIOMASK;				 /* !< Offset: 0x10 Port mask (R/W) */
-    struct {
-      __IO uint16_t FIOMASKL;
-      __IO uint16_t FIOMASKH;
-    };
-    struct {
-      __IO uint8_t  FIOMASK0;
-      __IO uint8_t  FIOMASK1;
-      __IO uint8_t  FIOMASK2;
-      __IO uint8_t  FIOMASK3;
-    };
-  };
-  union {
-    __IO uint32_t FIOPIN;				 /* !< Offset: 0x14 Port value (R/W) */
-    struct {
-      __IO uint16_t FIOPINL;
-      __IO uint16_t FIOPINH;
-    };
-    struct {
-      __IO uint8_t  FIOPIN0;
-      __IO uint8_t  FIOPIN1;
-      __IO uint8_t  FIOPIN2;
-      __IO uint8_t  FIOPIN3;
-    };
-  };
-  union {
-    __IO uint32_t FIOSET;				 /* !< Offset: 0x18 Port output set (R/W) */
-    struct {
-      __IO uint16_t FIOSETL;
-      __IO uint16_t FIOSETH;
-    };
-    struct {
-      __IO uint8_t  FIOSET0;
-      __IO uint8_t  FIOSET1;
-      __IO uint8_t  FIOSET2;
-      __IO uint8_t  FIOSET3;
-    };
-  };
-  union {
-    __O  uint32_t FIOCLR;				 /* !< Offset: 0x1C Port output clear (R/W) */
-    struct {
-      __O  uint16_t FIOCLRL;
-      __O  uint16_t FIOCLRH;
-    };
-    struct {
-      __O  uint8_t  FIOCLR0;
-      __O  uint8_t  FIOCLR1;
-      __O  uint8_t  FIOCLR2;
-      __O  uint8_t  FIOCLR3;
-    };
-  };
-} LPC_GPIO_TypeDef;
-
-/** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
-typedef struct
-{
-  __I  uint32_t IntStatus;                  /*!< Offset: 0x000 (R/ )  GPIO overall Interrupt Status Register */
-  __I  uint32_t IO0IntStatR;                /*!< Offset: 0x004 (R/ )  GPIO Interrupt Status Register 0 for Rising edge */
-  __I  uint32_t IO0IntStatF;                /*!< Offset: 0x008 (R/ )  GPIO Interrupt Status Register 0 for Falling edge */
-  __O  uint32_t IO0IntClr;                  /*!< Offset: 0x00C (R/W)  GPIO Interrupt Clear  Register 0 */
-  __IO uint32_t IO0IntEnR;                  /*!< Offset: 0x010 ( /W)  GPIO Interrupt Enable Register 0 for Rising edge */
-  __IO uint32_t IO0IntEnF;                  /*!< Offset: 0x014 (R/W)  GPIO Interrupt Enable Register 0 for Falling edge */
-       uint32_t RESERVED0[3];
-  __I  uint32_t IO2IntStatR;                /*!< Offset: 0x000 (R/ )  GPIO Interrupt Status Register 2 for Rising edge */
-  __I  uint32_t IO2IntStatF;                /*!< Offset: 0x000 (R/ )  GPIO Interrupt Status Register 2 for Falling edge */
-  __O  uint32_t IO2IntClr;                  /*!< Offset: 0x000 ( /W)  GPIO Interrupt Clear  Register 2 */
-  __IO uint32_t IO2IntEnR;                  /*!< Offset: 0x000 (R/W)  GPIO Interrupt Enable Register 2 for Rising edge */
-  __IO uint32_t IO2IntEnF;                  /*!< Offset: 0x000 (R/W)  GPIO Interrupt Enable Register 2 for Falling edge */
-} LPC_GPIOINT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-/** @brief Timer (TIM) register structure definition */
-typedef struct
-{
-  __IO uint32_t IR;                         /*!< Offset: 0x000 (R/W)  Interrupt Register */
-  __IO uint32_t TCR;                        /*!< Offset: 0x004 (R/W)  Timer Control Register */
-  __IO uint32_t TC;                         /*!< Offset: 0x008 (R/W)  Timer Counter Register */
-  __IO uint32_t PR;                         /*!< Offset: 0x00C (R/W)  Prescale Register */
-  __IO uint32_t PC;                         /*!< Offset: 0x010 (R/W)  Prescale Counter Register */
-  __IO uint32_t MCR;                        /*!< Offset: 0x014 (R/W)  Match Control Register */
-  __IO uint32_t MR0;                        /*!< Offset: 0x018 (R/W)  Match Register 0 */
-  __IO uint32_t MR1;                        /*!< Offset: 0x01C (R/W)  Match Register 1 */
-  __IO uint32_t MR2;                        /*!< Offset: 0x020 (R/W)  Match Register 2 */
-  __IO uint32_t MR3;                        /*!< Offset: 0x024 (R/W)  Match Register 3 */
-  __IO uint32_t CCR;                        /*!< Offset: 0x028 (R/W)  Capture Control Register */
-  __I  uint32_t CR0;                        /*!< Offset: 0x02C (R/ )  Capture Register 0 */
-  __I  uint32_t CR1;                        /*!< Offset: 0x030 (R/ )  Capture Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t EMR;                        /*!< Offset: 0x03C (R/W)  External Match Register */
-       uint32_t RESERVED1[12];
-  __IO uint32_t CTCR;                       /*!< Offset: 0x070 (R/W)  Count Control Register */
-} LPC_TIM_TypeDef;
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-/** @brief Pulse-Width Modulation (PWM) register structure definition */
-typedef struct
-{
-  __IO uint32_t IR;                         /*!< Offset: 0x000 (R/W)  Interrupt Register */
-  __IO uint32_t TCR;                        /*!< Offset: 0x004 (R/W)  Timer Control Register. Register */
-  __IO uint32_t TC;                         /*!< Offset: 0x008 (R/W)  Timer Counter Register */
-  __IO uint32_t PR;                         /*!< Offset: 0x00C (R/W)  Prescale Register */
-  __IO uint32_t PC;                         /*!< Offset: 0x010 (R/W)  Prescale Counter Register */
-  __IO uint32_t MCR;                        /*!< Offset: 0x014 (R/W)  Match Control Register */
-  __IO uint32_t MR0;                        /*!< Offset: 0x018 (R/W)  Match Register 0 */
-  __IO uint32_t MR1;                        /*!< Offset: 0x01C (R/W)  Match Register 1 */
-  __IO uint32_t MR2;                        /*!< Offset: 0x020 (R/W)  Match Register 2 */
-  __IO uint32_t MR3;                        /*!< Offset: 0x024 (R/W)  Match Register 3 */
-  __IO uint32_t CCR;                        /*!< Offset: 0x028 (R/W)  Capture Control Register */
-  __I  uint32_t CR0;                        /*!< Offset: 0x02C (R/ )  Capture Register 0 */
-  __I  uint32_t CR1;                        /*!< Offset: 0x030 (R/ )  Capture Register 1 */
-  __I  uint32_t CR2;                        /*!< Offset: 0x034 (R/ )  Capture Register 2 */
-  __I  uint32_t CR3;                        /*!< Offset: 0x038 (R/ )  Capture Register 3 */
-       uint32_t RESERVED0;
-  __IO uint32_t MR4;                        /*!< Offset: 0x040 (R/W)  Match Register 4 */
-  __IO uint32_t MR5;                        /*!< Offset: 0x044 (R/W)  Match Register 5 */
-  __IO uint32_t MR6;                        /*!< Offset: 0x048 (R/W)  Match Register 6 */
-  __IO uint32_t PCR;                        /*!< Offset: 0x04C (R/W)  PWM Control Register */
-  __IO uint32_t LER;                        /*!< Offset: 0x050 (R/W)  Load Enable Register */
-       uint32_t RESERVED1[7];
-  __IO uint32_t CTCR;                       /*!< Offset: 0x070 (R/W)  Count Control Register */
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-/** @brief  Universal Asynchronous Receiver Transmitter (UART) register structure definition */
-typedef struct
-{
-  union {
-  __I  uint32_t RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
-  __O  uint32_t THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
-  __IO uint32_t DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
-  };
-  union {
-  __IO uint32_t DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
-  __IO uint32_t IER;                   /*!< Offset: 0x004 Interrupt Enable Register (R/W) */
-  };
-  union {
-  __I  uint32_t IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
-  __O  uint32_t FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
-  };
-  __IO uint32_t LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
-       uint32_t RESERVED0;
-  __I  uint32_t LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
-       uint32_t RESERVED1;
-  __IO uint32_t SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
-  __IO uint32_t ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
-  __IO uint32_t ICR;                   /*!< Offset: 0x024 IrDA Control Register (R/W) */
-  __IO uint32_t FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
-       uint32_t RESERVED2;
-  __IO uint32_t TER;                   /*!< Offset: 0x030 Transmit Enable Register (R/W) */
-} LPC_UART_TypeDef;
-
-/** @brief  Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
-typedef struct
-{
-  union {
-  __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
-  __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
-  __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
-  };
-  union {
-  __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
-  __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
-  };
-  union {
-  __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
-  __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
-  };
-  __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
-  __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */
-  __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
-  __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */
-  __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
-  __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
-       uint32_t  RESERVED0;
-  __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
-       uint32_t  RESERVED1;
-  __IO uint32_t  TER;                   /*!< Offset: 0x030 Transmit Enable Register (R/W) */
-       uint32_t  RESERVED2[6];
-  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
-  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
-  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
-} LPC_UART1_TypeDef;
-
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
-/** @brief  Serial Peripheral Interface (SPI) register structure definition */
-typedef struct
-{
-  __IO uint32_t SPCR;                       /*!< Offset: 0x000 SPI Control Register (R/W) */
-  __I  uint32_t SPSR;                       /*!< Offset: 0x004 SPI Status Register (R/) */
-  __IO uint32_t SPDR;                       /*!< Offset: 0x008 SPI Data Register (R/W) */
-  __IO uint32_t SPCCR;                      /*!< Offset: 0x00C SPI Clock Counter Register (R/W) */
-       uint32_t RESERVED0[3];
-  __IO uint32_t SPINT;                      /*!< Offset: 0x01C SPI Interrupt Flag Register (R/W) */
-} LPC_SPI_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-/** @brief  Synchronous Serial Communication (SSP) register structure definition */
-typedef struct
-{
-  __IO uint32_t CR0;                        /*!< Offset: 0x000 (R/W)  Control Register 0 */
-  __IO uint32_t CR1;                        /*!< Offset: 0x004 (R/W)  Control Register 1 */
-  __IO uint32_t DR;                         /*!< Offset: 0x008 (R/W)  Data Register */
-  __I  uint32_t SR;                         /*!< Offset: 0x00C (R/ )  Status Register */
-  __IO uint32_t CPSR;                       /*!< Offset: 0x010 (R/W)  Clock Prescale Register */
-  __IO uint32_t IMSC;                       /*!< Offset: 0x014 (R/W)  Interrupt Mask Set and Clear Register */
-  __IO uint32_t RIS;                        /*!< Offset: 0x018 (R/W)  Raw Interrupt Status Register */
-  __IO uint32_t MIS;                        /*!< Offset: 0x01C (R/W)  Masked Interrupt Status Register */
-  __IO uint32_t ICR;                        /*!< Offset: 0x020 (R/W)  SSPICR Interrupt Clear Register */
-  __IO uint32_t DMACR;                      /*!< Offset: 0x024 (R/W)  DMA Control Register */
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-/** @brief  Inter-Integrated Circuit (I2C) register structure definition */
-typedef struct
-{
-  __IO uint32_t CONSET;                     /*!< Offset: 0x000 (R/W)  I2C Control Set Register */
-  __I  uint32_t STAT;                       /*!< Offset: 0x004 (R/ )  I2C Status Register */
-  __IO uint32_t DAT;                        /*!< Offset: 0x008 (R/W)  I2C Data Register */
-  __IO uint32_t ADR0;                       /*!< Offset: 0x00C (R/W)  I2C Slave Address Register 0 */
-  __IO uint32_t SCLH;                       /*!< Offset: 0x010 (R/W)  SCH Duty Cycle Register High Half Word */
-  __IO uint32_t SCLL;                       /*!< Offset: 0x014 (R/W)  SCL Duty Cycle Register Low Half Word */
-  __O  uint32_t CONCLR;                     /*!< Offset: 0x018 (R/W)  I2C Control Clear Register */
-  __IO uint32_t MMCTRL;                     /*!< Offset: 0x01C (R/W)  Monitor mode control register */
-  __IO uint32_t ADR1;                       /*!< Offset: 0x020 (R/W)  I2C Slave Address Register 1 */
-  __IO uint32_t ADR2;                       /*!< Offset: 0x024 (R/W)  I2C Slave Address Register 2 */
-  __IO uint32_t ADR3;                       /*!< Offset: 0x028 (R/W)  I2C Slave Address Register 3 */
-  __I  uint32_t DATA_BUFFER;                /*!< Offset: 0x02C (R/ )  Data buffer Register */
-  __IO uint32_t MASK0;                      /*!< Offset: 0x030 (R/W)  I2C Slave address mask register 0 */
-  __IO uint32_t MASK1;                      /*!< Offset: 0x034 (R/W)  I2C Slave address mask register 1 */
-  __IO uint32_t MASK2;                      /*!< Offset: 0x038 (R/W)  I2C Slave address mask register 2 */
-  __IO uint32_t MASK3;                      /*!< Offset: 0x03C (R/W)  I2C Slave address mask register 3 */
-} LPC_I2C_TypeDef;
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-/** @brief  Inter IC Sound (I2S) register structure definition */
-typedef struct
-{
-  __IO uint32_t DAO;                        /*!< Offset: 0x000 (R/W)  Digital Audio Output Register */
-  __IO uint32_t DAI;                        /*!< Offset: 0x004 (R/W)  Digital Audio Input Register */
-  __O  uint32_t TXFIFO;                     /*!< Offset: 0x008 ( /W)  Transmit FIFO */
-  __I  uint32_t RXFIFO;                     /*!< Offset: 0x00C (R/ )  Receive FIFO */
-  __I  uint32_t STATE;                      /*!< Offset: 0x010 (R/W)  Status Feedback Register */
-  __IO uint32_t DMA1;                       /*!< Offset: 0x014 (R/W)  DMA Configuration Register 1 */
-  __IO uint32_t DMA2;                       /*!< Offset: 0x018 (R/W)  DMA Configuration Register 2 */
-  __IO uint32_t IRQ;                        /*!< Offset: 0x01C (R/W)  Interrupt Request Control Register */
-  __IO uint32_t TXRATE;                     /*!< Offset: 0x020 (R/W)  Transmit reference clock divider Register */
-  __IO uint32_t RXRATE;                     /*!< Offset: 0x024 (R/W)  Receive reference clock divider Register */
-  __IO uint32_t TXBITRATE;                  /*!< Offset: 0x028 (R/W)  Transmit bit rate divider Register */
-  __IO uint32_t RXBITRATE;                  /*!< Offset: 0x02C (R/W)  Receive bit rate divider Register */
-  __IO uint32_t TXMODE;                     /*!< Offset: 0x030 (R/W)  Transmit mode control Register */
-  __IO uint32_t RXMODE;                     /*!< Offset: 0x034 (R/W)  Receive mode control Register */
-} LPC_I2S_TypeDef;
-
-/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
-/** @brief  Repetitive Interrupt Timer (RIT) register structure definition */
-typedef struct
-{
-  __IO uint32_t RICOMPVAL;
-  __IO uint32_t RIMASK;
-  __IO uint32_t RICTRL;
-  __IO uint32_t RICOUNTER;
-} LPC_RIT_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-/** @brief  Real-Time Clock (RTC) register structure definition */
-typedef struct
-{
-  __IO uint32_t ILR;                        /*!< Offset: 0x000 (R/W)  Interrupt Location Register */
-       uint32_t RESERVED0;				    
-  __IO uint32_t CCR;                        /*!< Offset: 0x008 (R/W)  Clock Control Register */
-  __IO uint32_t CIIR;                       /*!< Offset: 0x00C (R/W)  Counter Increment Interrupt Register */
-  __IO uint32_t AMR;                        /*!< Offset: 0x010 (R/W)  Alarm Mask Register */
-  __I  uint32_t CTIME0;                     /*!< Offset: 0x014 (R/ )  Consolidated Time Register 0 */
-  __I  uint32_t CTIME1;                     /*!< Offset: 0x018 (R/ )  Consolidated Time Register 1 */
-  __I  uint32_t CTIME2;                     /*!< Offset: 0x01C (R/ )  Consolidated Time Register 2 */
-  __IO uint32_t SEC;                        /*!< Offset: 0x020 (R/W)  Seconds Counter Register */
-  __IO uint32_t MIN;                        /*!< Offset: 0x024 (R/W)  Minutes Register */
-  __IO uint32_t HOUR;                       /*!< Offset: 0x028 (R/W)  Hours Register */
-  __IO uint32_t DOM;                        /*!< Offset: 0x02C (R/W)  Day of Month Register */
-  __IO uint32_t DOW;                        /*!< Offset: 0x030 (R/W)  Day of Week Register */
-  __IO uint32_t DOY;                        /*!< Offset: 0x034 (R/W)  Day of Year Register */
-  __IO uint32_t MONTH;                      /*!< Offset: 0x038 (R/W)  Months Register */
-  __IO uint32_t YEAR;                       /*!< Offset: 0x03C (R/W)  Years Register */
-  __IO uint32_t CALIBRATION;                /*!< Offset: 0x040 (R/W)  Calibration Value Register */
-  __IO uint32_t GPREG0;                     /*!< Offset: 0x044 (R/W)  General Purpose Register 0 */
-  __IO uint32_t GPREG1;                     /*!< Offset: 0x048 (R/W)  General Purpose Register 1 */
-  __IO uint32_t GPREG2;                     /*!< Offset: 0x04C (R/W)  General Purpose Register 2 */
-  __IO uint32_t GPREG3;                     /*!< Offset: 0x050 (R/W)  General Purpose Register 3 */
-  __IO uint32_t GPREG4;                     /*!< Offset: 0x054 (R/W)  General Purpose Register 4 */
-  __IO uint32_t RTC_AUXEN;                  /*!< Offset: 0x058 (R/W)  RTC Auxiliary Enable Register */
-  __IO uint32_t RTC_AUX;                    /*!< Offset: 0x05C (R/W)  RTC Auxiliary Control Register */
-  __IO uint32_t ALSEC;                      /*!< Offset: 0x060 (R/W)  Alarm value for Seconds */
-  __IO uint32_t ALMIN;                      /*!< Offset: 0x064 (R/W)  Alarm value for Minutes */
-  __IO uint32_t ALHOUR;                     /*!< Offset: 0x068 (R/W)  Alarm value for Hours */
-  __IO uint32_t ALDOM;                      /*!< Offset: 0x06C (R/W)  Alarm value for Day of Month */
-  __IO uint32_t ALDOW;                      /*!< Offset: 0x070 (R/W)  Alarm value for Day of Week */
-  __IO uint32_t ALDOY;                      /*!< Offset: 0x074 (R/W)  Alarm value for Day of Year */
-  __IO uint32_t ALMON;                      /*!< Offset: 0x078 (R/W)  Alarm value for Months */
-  __IO uint32_t ALYEAR;                     /*!< Offset: 0x07C (R/W)  Alarm value for Year */
-} LPC_RTC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-/** @brief  Watchdog Timer (WDT) register structure definition */
-typedef struct
-{
-  __IO uint32_t MOD;                        /*!< Offset: 0x000 (R/W)  Watchdog mode Register */
-  __IO uint32_t TC;                         /*!< Offset: 0x004 (R/W)  Watchdog timer constant Register */
-  __O  uint32_t FEED;                       /*!< Offset: 0x008 ( /W)  Watchdog feed sequence Register */
-  __I  uint32_t TV;                         /*!< Offset: 0x00C (R/ )  Watchdog timer value Register */
-  __IO uint32_t WDCLKSEL;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-/** @brief  Analog-to-Digital Converter (ADC) register structure definition */
-typedef struct
-{
-  __IO uint32_t CR;                         /*!< Offset: 0x000 (R/W)  A/D Control Register */
-  __IO uint32_t GDR;                        /*!< Offset: 0x004 (R/W)  A/D Global Data Register */
-       uint32_t RESERVED0;
-  __IO uint32_t INTEN;                      /*!< Offset: 0x00C (R/W)  A/D Interrupt Enable Register */
-  __I  uint32_t DR[8];                      /*!< Offset: 0x010 (R/ )  A/D Channel # Data Register */
-  __I  uint32_t STAT;                       /*!< Offset: 0x030 (R/ )  A/D Status Register */
-  __IO uint32_t ADTRM;                      /*!< Offset: 0x034 (R/W)  ADC trim Register */
-} LPC_ADC_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-/** @brief  Digital-to-Analog Converter (DAC) register structure definition */
-typedef struct
-{
-  __IO uint32_t CR;                         /*!< Offset: 0x000 (R/W)  D/A Converter Register */
-  __IO uint32_t CTRL;                       /*!< Offset: 0x004 (R/W)  DAC Control register */
-  __IO uint32_t CNTVAL;                     /*!< Offset: 0x008 (R/W)  DAC Counter Value Register */
-} LPC_DAC_TypeDef;
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-/** @brief  Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
-typedef struct
-{
-  __I  uint32_t CON;                        /*!< Offset: 0x000 (R/ )  PWM Control read address Register */
-  __O  uint32_t CON_SET;                    /*!< Offset: 0x004 ( /W)  PWM Control set address Register */
-  __O  uint32_t CON_CLR;                    /*!< Offset: 0x008 ( /W)  PWM Control clear address Register */
-  __I  uint32_t CAPCON;                     /*!< Offset: 0x00C (R/ )  Capture Control read address Register */
-  __O  uint32_t CAPCON_SET;                 /*!< Offset: 0x010 ( /W)  Capture Control set address Register */
-  __O  uint32_t CAPCON_CLR;                 /*!< Offset: 0x014 ( /W)  Event Control clear address Register */
-  __IO uint32_t TC0;                        /*!< Offset: 0x018 (R/W)  Timer Counter Register, channel 0 */
-  __IO uint32_t TC1;                        /*!< Offset: 0x01C (R/W)  Timer Counter Register, channel 1 */
-  __IO uint32_t TC2;                        /*!< Offset: 0x020 (R/W)  Timer Counter Register, channel 2 */
-  __IO uint32_t LIM0;                       /*!< Offset: 0x024 (R/W)  Limit Register, channel 0 */
-  __IO uint32_t LIM1;                       /*!< Offset: 0x028 (R/W)  Limit Register, channel 1 */
-  __IO uint32_t LIM2;                       /*!< Offset: 0x02C (R/W)  Limit Register, channel 2 */
-  __IO uint32_t MAT0;                       /*!< Offset: 0x030 (R/W)  Match Register, channel 0 */
-  __IO uint32_t MAT1;                       /*!< Offset: 0x034 (R/W)  Match Register, channel 1 */
-  __IO uint32_t MAT2;                       /*!< Offset: 0x038 (R/W)  Match Register, channel 2 */
-  __IO uint32_t DT;                         /*!< Offset: 0x03C (R/W)  Dead time Register */
-  __IO uint32_t CP;                         /*!< Offset: 0x040 (R/W)  Commutation Pattern Register */
-  __IO uint32_t CAP0;                       /*!< Offset: 0x044 (R/W)  Capture Register, channel 0 */
-  __IO uint32_t CAP1;                       /*!< Offset: 0x048 (R/W)  Capture Register, channel 1 */
-  __IO uint32_t CAP2;                       /*!< Offset: 0x04C (R/W)  Capture Register, channel 2 */
-  __I  uint32_t INTEN;                      /*!< Offset: 0x050 (R/ )  Interrupt Enable read Register */
-  __O  uint32_t INTEN_SET;                  /*!< Offset: 0x054 ( /W)  Interrupt Enable set address Register */
-  __O  uint32_t INTEN_CLR;                  /*!< Offset: 0x058 ( /W)  Interrupt Enable clear address Register */
-  __I  uint32_t CNTCON;                     /*!< Offset: 0x05C (R/ )  Count Control read address Register */
-  __O  uint32_t CNTCON_SET;                 /*!< Offset: 0x060 ( /W)  Count Control set address Register */
-  __O  uint32_t CNTCON_CLR;                 /*!< Offset: 0x064 ( /W)  Count Control clear address Register */
-  __I  uint32_t INTF;                       /*!< Offset: 0x068 (R/ )  Interrupt flags read address Register */
-  __O  uint32_t INTF_SET;                   /*!< Offset: 0x06C ( /W)  Interrupt flags set address Register */
-  __O  uint32_t INTF_CLR;                   /*!< Offset: 0x070 ( /W)  Interrupt flags clear address Register */
-  __O  uint32_t CAP_CLR;                    /*!< Offset: 0x074 ( /W)  Capture clear address Register */
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-/** @brief  Quadrature Encoder Interface (QEI) register structure definition */
-typedef struct
-{
-  __O  uint32_t CON;                        /*!< Offset: 0x000 ( /W)  Control Register */
-  __I  uint32_t STAT;                       /*!< Offset: 0x004 (R/ )  Encoder Status Register */
-  __IO uint32_t CONF;                       /*!< Offset: 0x008 (R/W)  Configuration Register */
-  __I  uint32_t POS;                        /*!< Offset: 0x00C (R/ )  Position Register */
-  __IO uint32_t MAXPOS;                     /*!< Offset: 0x010 (R/W)  Maximum position Register */
-  __IO uint32_t CMPOS0;                     /*!< Offset: 0x014 (R/W)  Position compare Register 0 */
-  __IO uint32_t CMPOS1;                     /*!< Offset: 0x018 (R/W)  Position compare Register 1 */
-  __IO uint32_t CMPOS2;                     /*!< Offset: 0x01C (R/W)  Position compare Register 2 */
-  __I  uint32_t INXCNT;                     /*!< Offset: 0x020 (R/ )  Index count Register */
-  __IO uint32_t INXCMP0;                    /*!< Offset: 0x024 (R/W)  Index compare Register 0 */
-  __IO uint32_t LOAD;                       /*!< Offset: 0x028 (R/W)  Velocity timer reload Register */
-  __I  uint32_t TIME;                       /*!< Offset: 0x02C (R/ )  Velocity timer Register */
-  __I  uint32_t VEL;                        /*!< Offset: 0x030 (R/ )  Velocity counter Register */
-  __I  uint32_t CAP;                        /*!< Offset: 0x034 (R/ )  Velocity capture Register */
-  __IO uint32_t VELCOMP;                    /*!< Offset: 0x038 (R/W)  Velocity compare Register */
-  __IO uint32_t FILTER;
-       uint32_t RESERVED0[998];
-  __O  uint32_t IEC;                        /*!< Offset: 0xFD8 ( /W)  Interrupt enable clear Register */
-  __O  uint32_t IES;                        /*!< Offset: 0xFDC ( /W)  Interrupt enable set Register */
-  __I  uint32_t INTSTAT;                    /*!< Offset: 0xFE0 (R/ )  Interrupt status Register */
-  __I  uint32_t IE;                         /*!< Offset: 0xFE4 (R/ )  Interrupt enable Register */
-  __O  uint32_t CLR;                        /*!< Offset: 0xFE8 ( /W)  Interrupt status clear Register */
-  __O  uint32_t SET;                        /*!< Offset: 0xFEC ( /W)  Interrupt status set Register */
-} LPC_QEI_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-/** @brief  Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
-typedef struct
-{
-  __IO uint32_t mask[512];                  /*!< Offset: 0x000 (R/W)  Acceptance Filter RAM */
-} LPC_CANAF_RAM_TypeDef;
-
-/** @brief  Controller Area Network Acceptance Filter(CANAF) register structure definition */
-typedef struct                          /* Acceptance Filter Registers        */
-{
-  __IO uint32_t AFMR;                       /*!< Offset: 0x000 (R/W)  Acceptance Filter Register */
-  __IO uint32_t SFF_sa;                     /*!< Offset: 0x004 (R/W)  Standard Frame Individual Start Address Register */
-  __IO uint32_t SFF_GRP_sa;                 /*!< Offset: 0x008 (R/W)  Standard Frame Group Start Address Register */
-  __IO uint32_t EFF_sa;                     /*!< Offset: 0x00C (R/W)  Extended Frame Start Address Register */
-  __IO uint32_t EFF_GRP_sa;                 /*!< Offset: 0x010 (R/W)  Extended Frame Group Start Address Register */
-  __IO uint32_t ENDofTable;                 /*!< Offset: 0x014 (R/W)  End of AF Tables Register */
-  __I  uint32_t LUTerrAd;                   /*!< Offset: 0x018 (R/ )  LUT Error Address Register */
-  __I  uint32_t LUTerr;                     /*!< Offset: 0x01C (R/ )  LUT Error Register */
-  __IO uint32_t FCANIE;                     /*!< Offset: 0x020 (R/W)  Global FullCANInterrupt Enable Register */
-  __IO uint32_t FCANIC0;                    /*!< Offset: 0x024 (R/W)  FullCAN Interrupt and Capture Register 0 */
-  __IO uint32_t FCANIC1;                    /*!< Offset: 0x028 (R/W)  FullCAN Interrupt and Capture Register 1 */
-} LPC_CANAF_TypeDef;
-
-/** @brief  Controller Area Network Central (CANCR) register structure definition */
-typedef struct                          /* Central Registers                  */
-{
-  __I  uint32_t TxSR;                       /*!< Offset: 0x000 (R/ )  CAN Central Transmit Status Register */
-  __I  uint32_t RxSR;                       /*!< Offset: 0x004 (R/ )  CAN Central Receive Status Register */
-  __I  uint32_t MSR;                        /*!< Offset: 0x008 (R/ )  CAN Central Miscellaneous Register */
-} LPC_CANCR_TypeDef;
-
-/** @brief  Controller Area Network Controller (CAN) register structure definition */
-typedef struct                              /* Controller Registers               */
-{
-  __IO uint32_t MOD;                        /*!< Offset: 0x000 (R/W)  CAN Mode Register */
-  __O  uint32_t CMR;                        /*!< Offset: 0x004 ( /W)  CAN Command Register */
-  __IO uint32_t GSR;                        /*!< Offset: 0x008 (R/W)  CAN Global Status Register */
-  __I  uint32_t ICR;                        /*!< Offset: 0x00C (R/ )  CAN Interrupt and Capture Register */
-  __IO uint32_t IER;                        /*!< Offset: 0x010 (R/W)  CAN Interrupt Enable Register */
-  __IO uint32_t BTR;                        /*!< Offset: 0x014 (R/W)  CAN Bus Timing Register */
-  __IO uint32_t EWL;                        /*!< Offset: 0x018 (R/W)  CAN Error Warning Limit Register */
-  __I  uint32_t SR;                         /*!< Offset: 0x01C (R/ )  CAN Status Register */
-  __IO uint32_t RFS;                        /*!< Offset: 0x020 (R/W)  CAN Receive Frame Status Register */
-  __IO uint32_t RID;                        /*!< Offset: 0x024 (R/W)  CAN Receive Identifier Register */
-  __IO uint32_t RDA;                        /*!< Offset: 0x028 (R/W)  CAN Receive Data Register A */
-  __IO uint32_t RDB;                        /*!< Offset: 0x02C (R/W)  CAN Receive Data Register B */
-  __IO uint32_t TFI1;                       /*!< Offset: 0x030 (R/W)  CAN Transmit Frame Information Register 1 */
-  __IO uint32_t TID1;                       /*!< Offset: 0x034 (R/W)  CAN Transmit Identifier Register 1 */
-  __IO uint32_t TDA1;                       /*!< Offset: 0x038 (R/W)  CAN Transmit Data Register A 1 */
-  __IO uint32_t TDB1;                       /*!< Offset: 0x03C (R/W)  CAN Transmit Data Register B 1 */
-  __IO uint32_t TFI2;                       /*!< Offset: 0x040 (R/W)  CAN Transmit Frame Information Register 2 */
-  __IO uint32_t TID2;                       /*!< Offset: 0x044 (R/W)  CAN Transmit Identifier Register 2 */
-  __IO uint32_t TDA2;                       /*!< Offset: 0x048 (R/W)  CAN Transmit Data Register A 2 */
-  __IO uint32_t TDB2;                       /*!< Offset: 0x04C (R/W)  CAN Transmit Data Register B 2 */
-  __IO uint32_t TFI3;                       /*!< Offset: 0x050 (R/W)  CAN Transmit Frame Information Register 3 */
-  __IO uint32_t TID3;                       /*!< Offset: 0x054 (R/W)  CAN Transmit Identifier Register 3 */
-  __IO uint32_t TDA3;                       /*!< Offset: 0x058 (R/W)  CAN Transmit Data Register A 3 */
-  __IO uint32_t TDB3;                       /*!< Offset: 0x05C (R/W)  CAN Transmit Data Register B 3 */
-} LPC_CAN_TypeDef;
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-/** @brief  General Purpose Direct Memory Access (GPDMA) register structure definition */
-typedef struct                              /* Common Registers                   */
-{
-  __I  uint32_t IntStat;                    /*!< Offset: 0x000 (R/ )  DMA Interrupt Status Register */
-  __I  uint32_t IntTCStat;                  /*!< Offset: 0x004 (R/ )  DMA Interrupt Terminal Count Request Status Register */
-  __O  uint32_t IntTCClear;                 /*!< Offset: 0x008 ( /W)  DMA Interrupt Terminal Count Request Clear Register */
-  __I  uint32_t IntErrStat;                 /*!< Offset: 0x00C (R/ )  DMA Interrupt Error Status Register */
-  __O  uint32_t IntErrClr;                  /*!< Offset: 0x010 ( /W)  DMA Interrupt Error Clear Register */
-  __I  uint32_t RawIntTCStat;               /*!< Offset: 0x014 (R/ )  DMA Raw Interrupt Terminal Count Status Register */
-  __I  uint32_t RawIntErrStat;              /*!< Offset: 0x018 (R/ )  DMA Raw Error Interrupt Status Register */
-  __I  uint32_t EnbldChns;                  /*!< Offset: 0x01C (R/ )  DMA Enabled Channel Register */
-  __IO uint32_t SoftBReq;                   /*!< Offset: 0x020 (R/W)  DMA Software Burst Request Register */
-  __IO uint32_t SoftSReq;                   /*!< Offset: 0x024 (R/W)  DMA Software Single Request Register */
-  __IO uint32_t SoftLBReq;                  /*!< Offset: 0x028 (R/W)  DMA Software Last Burst Request Register */
-  __IO uint32_t SoftLSReq;                  /*!< Offset: 0x02C (R/W)  DMA Software Last Single Request Register */
-  __IO uint32_t Config;                     /*!< Offset: 0x030 (R/W)  DMA Configuration Register */
-  __IO uint32_t Sync;                       /*!< Offset: 0x034 (R/W)  DMA Synchronization Register */
-} LPC_GPDMA_TypeDef;
-
-/** @brief  General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
-typedef struct                              /* Channel Registers                  */
-{
-  __IO uint32_t CSrcAddr;                   /*!< Offset: 0x000 (R/W)  DMA Channel # Source Address Register */
-  __IO uint32_t CDestAddr;                  /*!< Offset: 0x004 (R/W)  DMA Channel # Destination Address Register */
-  __IO uint32_t CLLI;                       /*!< Offset: 0x008 (R/W)  DMA Channel # Linked List Item Register */
-  __IO uint32_t CControl;                   /*!< Offset: 0x00C (R/W)  DMA Channel # Control Register */
-  __IO uint32_t CConfig;                    /*!< Offset: 0x010 (R/W)  DMA Channel # Configuration Register */
-} LPC_GPDMACH_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-/** @brief  Universal Serial Bus (USB) register structure definition */
-typedef struct
-{
-  __I  uint32_t Revision;                 /*!< Offset: 0x000 (R/ )  Revision Register */
-  __IO uint32_t Control;                  /*!< Offset: 0x004 (R/W)  Control Register */
-  __IO uint32_t CommandStatus;            /*!< Offset: 0x008 (R/W)  Command / Status Register */
-  __IO uint32_t InterruptStatus;          /*!< Offset: 0x00C (R/W)  Interrupt Status Register */
-  __IO uint32_t InterruptEnable;          /*!< Offset: 0x010 (R/W)  Interrupt Enable Register */
-  __IO uint32_t InterruptDisable;         /*!< Offset: 0x014 (R/W)  Interrupt Disable Register */
-  __IO uint32_t HCCA;                     /*!< Offset: 0x018 (R/W)  Host Controller communication Area Register */
-  __I  uint32_t PeriodCurrentED;          /*!< Offset: 0x01C (R/ )   Register */
-  __IO uint32_t ControlHeadED;            /*!< Offset: 0x020 (R/W)   Register */
-  __IO uint32_t ControlCurrentED;         /*!< Offset: 0x024 (R/W)   Register */
-  __IO uint32_t BulkHeadED;               /*!< Offset: 0x028 (R/W)   Register */
-  __IO uint32_t BulkCurrentED;            /*!< Offset: 0x02C (R/W)   Register */
-  __I  uint32_t DoneHead;                 /*!< Offset: 0x030 (R/ )   Register */
-  __IO uint32_t FmInterval;               /*!< Offset: 0x034 (R/W)   Register */
-  __I  uint32_t FmRemaining;              /*!< Offset: 0x038 (R/ )   Register */
-  __I  uint32_t FmNumber;                 /*!< Offset: 0x03C (R/ )   Register */
-  __IO uint32_t PeriodicStart;            /*!< Offset: 0x040 (R/W)   Register */
-  __IO uint32_t LSTreshold;               /*!< Offset: 0x044 (R/W)   Register */
-  __IO uint32_t RhDescriptorA;            /*!< Offset: 0x048 (R/W)   Register */
-  __IO uint32_t RhDescriptorB;            /*!< Offset: 0x04C (R/W)   Register */
-  __IO uint32_t RhStatus;                 /*!< Offset: 0x050 (R/W)   Register */
-  __IO uint32_t RhPortStatus1;            /*!< Offset: 0x054 (R/W)   Register */
-  __IO uint32_t RhPortStatus2;            /*!< Offset: 0x05C (R/W)   Register */
-       uint32_t RESERVED0[40];
-  __I  uint32_t Module_ID;                /*!< Offset: 0x0FC (R/ )  Module ID / Version Reverence ID Register */
-                                          /* USB On-The-Go Registers            */
-  __I  uint32_t IntSt;                    /*!< Offset: 0x100 (R/ )  OTG Interrupt Status Register */
-  __IO uint32_t IntEn;                    /*!< Offset: 0x104 (R/W)  OTG Interrupt Enable Register */
-  __O  uint32_t IntSet;                   /*!< Offset: 0x108 ( /W)  OTG Interrupt Set Register */
-  __O  uint32_t IntClr;                   /*!< Offset: 0x10C ( /W)  OTG Interrupt Clear Register */
-  __IO uint32_t StCtrl;                   /*!< Offset: 0x110 (R/W)  OTG Status and Control Register */
-  __IO uint32_t Tmr;                      /*!< Offset: 0x114 (R/W)  OTG Timer Register */
-       uint32_t RESERVED1[58];
-                                          /* USB Device Interrupt Registers     */
-  __I  uint32_t DevIntSt;                 /*!< Offset: 0x200 (R/ )  USB Device Interrupt Status Register */
-  __IO uint32_t DevIntEn;                 /*!< Offset: 0x204 (R/W)  USB Device Interrupt Enable Register */
-  __O  uint32_t DevIntClr;                /*!< Offset: 0x208 ( /W)  USB Device Interrupt Clear Register */
-  __O  uint32_t DevIntSet;                /*!< Offset: 0x20C ( /W)  USB Device Interrupt Set Register */
-                                          /* USB Device SIE Command Registers   */
-  __O  uint32_t CmdCode;                  /*!< Offset: 0x210 (R/W)  USB Command Code Register */
-  __I  uint32_t CmdData;                  /*!< Offset: 0x214 (R/W)  USB Command Data Register */
-                                          /* USB Device Transfer Registers      */
-  __I  uint32_t RxData;                   /*!< Offset: 0x218 (R/ )  USB Receive Data Register */
-  __O  uint32_t TxData;                   /*!< Offset: 0x21C ( /W)  USB Transmit Data Register */
-  __I  uint32_t RxPLen;                   /*!< Offset: 0x220 (R/ )  USB Receive Packet Length Register */
-  __O  uint32_t TxPLen;                   /*!< Offset: 0x224 ( /W)  USB Transmit Packet Length Register */
-  __IO uint32_t Ctrl;                     /*!< Offset: 0x228 (R/W)  USB Control Register */
-  __O  uint32_t DevIntPri;                /*!< Offset: 0x22C (R/W)  USB Device Interrupt Priority Register */
-                                          /* USB Device Endpoint Interrupt Regs */
-  __I  uint32_t EpIntSt;                  /*!< Offset: 0x230 (R/ )  USB Endpoint Interrupt Status Register */
-  __IO uint32_t EpIntEn;                  /*!< Offset: 0x234 (R/W)  USB Endpoint Interrupt Enable Register */
-  __O  uint32_t EpIntClr;                 /*!< Offset: 0x238 ( /W)  USB Endpoint Interrupt Clear Register */
-  __O  uint32_t EpIntSet;                 /*!< Offset: 0x23C ( /W)  USB Endpoint Interrupt Set Register */
-  __O  uint32_t EpIntPri;                 /*!< Offset: 0x240 ( /W)  USB Endpoint Interrupt Priority Register */
-                                          /* USB Device Endpoint Realization Reg*/
-  __IO uint32_t ReEp;                     /*!< Offset: 0x244 (R/W)  USB Realize Endpoint Register */
-  __O  uint32_t EpInd;                    /*!< Offset: 0x248 ( /W)  USB Endpoint Index Register */
-  __IO uint32_t MaxPSize;                 /*!< Offset: 0x24C (R/W)  USB MaxPacketSize Register */
-                                          /* USB Device DMA Registers           */
-  __I  uint32_t DMARSt;                   /*!< Offset: 0x250 (R/ )  USB DMA Request Status Register */
-  __O  uint32_t DMARClr;                  /*!< Offset: 0x254 ( /W)  USB DMA Request Clear Register */
-  __O  uint32_t DMARSet;                  /*!< Offset: 0x258 ( /W)  USB DMA Request Set Register */
-       uint32_t RESERVED2[9];
-  __IO uint32_t UDCAH;                    /*!< Offset: 0x280 (R/W)  USB UDCA Head Register */
-  __I  uint32_t EpDMASt;                  /*!< Offset: 0x284 (R/ )  USB EP DMA Status Register */
-  __O  uint32_t EpDMAEn;                  /*!< Offset: 0x288 ( /W)  USB EP DMA Enable Register */
-  __O  uint32_t EpDMADis;                 /*!< Offset: 0x28C ( /W)  USB EP DMA Disable Register */
-  __I  uint32_t DMAIntSt;                 /*!< Offset: 0x290 (R/ )  USB DMA Interrupt Status Register */
-  __IO uint32_t DMAIntEn;                 /*!< Offset: 0x294 (R/W)  USB DMA Interrupt Enable Register */
-       uint32_t RESERVED3[2];
-  __I  uint32_t EoTIntSt;                 /*!< Offset: 0x2A0 (R/ )  USB End of Transfer Interrupt Status Register */
-  __O  uint32_t EoTIntClr;                /*!< Offset: 0x2A4 ( /W)  USB End of Transfer Interrupt Clear Register */
-  __O  uint32_t EoTIntSet;                /*!< Offset: 0x2A8 ( /W)  USB End of Transfer Interrupt Set Register */
-  __I  uint32_t NDDRIntSt;                /*!< Offset: 0x2AC (R/ )  USB New DD Request Interrupt Status Register */
-  __O  uint32_t NDDRIntClr;               /*!< Offset: 0x2B0 ( /W)  USB New DD Request Interrupt Clear Register */
-  __O  uint32_t NDDRIntSet;               /*!< Offset: 0x2B4 ( /W)  USB New DD Request Interrupt Set Register */
-  __I  uint32_t SysErrIntSt;              /*!< Offset: 0x2B8 (R/ )  USB System Error Interrupt Status Register */
-  __O  uint32_t SysErrIntClr;             /*!< Offset: 0x2BC ( /W)  USB System Error Interrupt Clear Register */
-  __O  uint32_t SysErrIntSet;             /*!< Offset: 0x2C0 ( /W)  USB System Error Interrupt Set Register */
-       uint32_t RESERVED4[15];
-                                          /* USB OTG I2C Registers              */
-  union {
-  __I  uint32_t I2C_RX;                   /*!< Offset: 0x300 (R/ )  OTG I2C Receive Register */
-  __O  uint32_t I2C_TX;                   /*!< Offset: 0x300 ( /W)  OTG I2C Transmit Register */
-  };
-  __I  uint32_t I2C_STS;                  /*!< Offset: 0x304 (R/ )  OTG I2C Status Register */
-  __IO uint32_t I2C_CTL;                  /*!< Offset: 0x308 (R/W)  OTG I2C Control Register */
-  __IO uint32_t I2C_CLKHI;                /*!< Offset: 0x30C (R/W)  OTG I2C Clock High Register */
-  __O  uint32_t I2C_CLKLO;                /*!< Offset: 0x310 ( /W)  OTG I2C Clock Low Register */
-       uint32_t RESERVED5[824];
-                                          /* USB Clock Control Registers        */
-  union {
-  __IO uint32_t USBClkCtrl;               /*!< Offset: 0xFF4 (R/W)  OTG clock controller Register */
-  __IO uint32_t OTGClkCtrl;               /*!< Offset: 0xFF4 (R/W)  USB clock controller Register */
-  };
-  union {
-  __I  uint32_t USBClkSt;                 /*!< Offset: 0xFF8 (R/ )  OTG clock status Register */
-  __I  uint32_t OTGClkSt;                 /*!< Offset: 0xFF8 (R/ )  USB clock status Register */
-  };
-} LPC_USB_TypeDef;
-
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-/** @brief  Ethernet Media Access Controller (EMAC) register structure definition */
-typedef struct
-{
-  __IO uint32_t MAC1;                       /*!< Offset: 0x000 (R/W)  MAC Configuration Register 1 */
-  __IO uint32_t MAC2;                       /*!< Offset: 0x004 (R/W)  MAC Configuration Register 2 */
-  __IO uint32_t IPGT;                       /*!< Offset: 0x008 (R/W)  Back-to-Back Inter-Packet-Gap Register */
-  __IO uint32_t IPGR;                       /*!< Offset: 0x00C (R/W)  Non Back-to-Back Inter-Packet-Gap Register */
-  __IO uint32_t CLRT;                       /*!< Offset: 0x010 (R/W)  Collision Window / Retry Register */
-  __IO uint32_t MAXF;                       /*!< Offset: 0x014 (R/W)  Maximum Frame Register */
-  __IO uint32_t SUPP;                       /*!< Offset: 0x018 (R/W)  PHY Support Register */
-  __IO uint32_t TEST;                       /*!< Offset: 0x01C (R/W)  Test Register */
-  __IO uint32_t MCFG;                       /*!< Offset: 0x020 (R/W)  MII Mgmt Configuration Register */
-  __IO uint32_t MCMD;                       /*!< Offset: 0x024 (R/W)  MII Mgmt Command Register */
-  __IO uint32_t MADR;                       /*!< Offset: 0x028 (R/W)  MII Mgmt Address Register */
-  __O  uint32_t MWTD;                       /*!< Offset: 0x02C ( /W)  MII Mgmt Write Data Register */
-  __I  uint32_t MRDD;                       /*!< Offset: 0x030 (R/ )  MII Mgmt Read Data Register */
-  __I  uint32_t MIND;                       /*!< Offset: 0x034 (R/ )  MII Mgmt Indicators Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t SA0;                        /*!< Offset: 0x040 (R/W)  Station Address 0 Register */
-  __IO uint32_t SA1;                        /*!< Offset: 0x044 (R/W)  Station Address 1 Register */
-  __IO uint32_t SA2;                        /*!< Offset: 0x048 (R/W)  Station Address 2 Register */
-       uint32_t RESERVED1[45];
-  __IO uint32_t Command;                    /*!< Offset: 0x100 (R/W)  Command Register */
-  __I  uint32_t Status;                     /*!< Offset: 0x104 (R/ )  Status Register */
-  __IO uint32_t RxDescriptor;               /*!< Offset: 0x108 (R/W)  Receive Descriptor Base Address Register */
-  __IO uint32_t RxStatus;                   /*!< Offset: 0x10C (R/W)  Receive Status Base Address Register */
-  __IO uint32_t RxDescriptorNumber;         /*!< Offset: 0x110 (R/W)  Receive Number of Descriptors Register */
-  __I  uint32_t RxProduceIndex;             /*!< Offset: 0x114 (R/ )  Receive Produce Index Register */
-  __IO uint32_t RxConsumeIndex;             /*!< Offset: 0x118 (R/W)  Receive Consume Index Register */
-  __IO uint32_t TxDescriptor;               /*!< Offset: 0x11C (R/W)  Transmit Descriptor Base Address Register */
-  __IO uint32_t TxStatus;                   /*!< Offset: 0x120 (R/W)  Transmit Status Base Address Register */
-  __IO uint32_t TxDescriptorNumber;         /*!< Offset: 0x124 (R/W)  Transmit Number of Descriptors Register */
-  __IO uint32_t TxProduceIndex;             /*!< Offset: 0x128 (R/W)  Transmit Produce Index Register */
-  __I  uint32_t TxConsumeIndex;             /*!< Offset: 0x12C (R/ )  Transmit Consume Index Register */
-       uint32_t RESERVED2[10];
-  __I  uint32_t TSV0;                       /*!< Offset: 0x158 (R/ )  Transmit Status Vector 0 Register */
-  __I  uint32_t TSV1;                       /*!< Offset: 0x15C (R/ )  Transmit Status Vector 1 Register */
-  __I  uint32_t RSV;                        /*!< Offset: 0x160 (R/ )  Receive Status Vector Register */
-       uint32_t RESERVED3[3];
-  __IO uint32_t FlowControlCounter;         /*!< Offset: 0x170 (R/W)  Flow Control Counter Register */
-  __I  uint32_t FlowControlStatus;          /*!< Offset: 0x174 (R/ )  Flow Control Status egister */
-       uint32_t RESERVED4[34];
-  __IO uint32_t RxFilterCtrl;               /*!< Offset: 0x200 (R/W)  Receive Filter Control Register */
-  __I  uint32_t RxFilterWoLStatus;          /*!< Offset: 0x204 (R/ )  Receive Filter WoL Status Register */
-  __O  uint32_t RxFilterWoLClear;           /*!< Offset: 0x208 ( /W)  Receive Filter WoL Clear Register */
-       uint32_t RESERVED5;
-  __IO uint32_t HashFilterL;                /*!< Offset: 0x210 (R/W)  Hash Filter Table LSBs Register */
-  __IO uint32_t HashFilterH;                /*!< Offset: 0x214 (R/W)  Hash Filter Table MSBs Register */
-       uint32_t RESERVED6[882];
-  __I  uint32_t IntStatus;                  /*!< Offset: 0xFE0 (R/ )  Interrupt Status Register */
-  __IO uint32_t IntEnable;                  /*!< Offset: 0xFE4 (R/W)  Interrupt Enable Register */
-  __O  uint32_t IntClear;                   /*!< Offset: 0xFE8 ( /W)  Interrupt Clear Register */
-  __O  uint32_t IntSet;                     /*!< Offset: 0xFEC ( /W)  Interrupt Set Register */
-       uint32_t RESERVED7;
-  __IO uint32_t PowerDown;                  /*!< Offset: 0xFF4 (R/W)  Power-Down Register */
-} LPC_EMAC_TypeDef;
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#ifdef __LPC17XX_REV00
-#define LPC_AHBRAM0_BASE      (0x20000000UL)
-#define LPC_AHBRAM1_BASE      (0x20004000UL)
-#else
-#define LPC_AHBRAM0_BASE      (0x2007C000UL)
-#define LPC_AHBRAM1_BASE      (0x20080000UL)
-#endif
-#define LPC_GPIO_BASE         (0x2009C000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_APB1_BASE         (0x40080000UL)
-#define LPC_AHB_BASE          (0x50000000UL)
-#define LPC_CM3_BASE          (0xE0000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
-#define LPC_SPI_BASE          (LPC_APB0_BASE + 0x20000)
-#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
-#define LPC_PINCON_BASE       (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals                                                           */
-#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
-#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
-#define LPC_RIT_BASE          (LPC_APB1_BASE + 0x30000)
-#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
-#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals                                                            */
-#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x04000)
-#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x04100)
-#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x04120)
-#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x04140)
-#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x04160)
-#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x04180)
-#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x041A0)
-#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x041C0)
-#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x041E0)
-#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
-
-/* GPIOs                                                                      */
-#define LPC_GPIO0_BASE        (LPC_GPIO_BASE + 0x00000)
-#define LPC_GPIO1_BASE        (LPC_GPIO_BASE + 0x00020)
-#define LPC_GPIO2_BASE        (LPC_GPIO_BASE + 0x00040)
-#define LPC_GPIO3_BASE        (LPC_GPIO_BASE + 0x00060)
-#define LPC_GPIO4_BASE        (LPC_GPIO_BASE + 0x00080)
-
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
-#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
-#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
-#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
-#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
-#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
-#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
-#define LPC_RIT               ((LPC_RIT_TypeDef       *) LPC_RIT_BASE      )
-#define LPC_UART0             ((LPC_UART_TypeDef      *) LPC_UART0_BASE    )
-#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
-#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
-#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
-#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
-#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
-#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
-#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
-#define LPC_SPI               ((LPC_SPI_TypeDef       *) LPC_SPI_BASE      )
-#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
-#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
-#define LPC_PINCON            ((LPC_PINCON_TypeDef    *) LPC_PINCON_BASE   )
-#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
-#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
-#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
-#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
-#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
-#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
-#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
-#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
-#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
-#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
-#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
-#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
-#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
-#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
-
-/**
- * @}
- */
-
-#endif  // __LPC17xx_H__
diff --git a/os/hal/platforms/LPC17xx/adc_lld.c b/os/hal/platforms/LPC17xx/adc_lld.c
deleted file mode 100644
index aebd04b38..000000000
--- a/os/hal/platforms/LPC17xx/adc_lld.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx ADC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/adc_lld.c
- * @brief   LPC17xx ADC subsystem low level driver source.
- * @note    Values in samples buffer are from DR register.
- *          To get ADC values make conversion (DR >> 6) & 0x03FF.
- *          DMA only support one ADC channel.
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-ADCDriver ADCD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static lpc17xx_dma_lli_config_t lpc_adc_lli[2] __attribute__((aligned(0x10)));
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if LPC17xx_ADC_USE_DMA
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
-  (void) flags;
-
-  if ((flags & (1 << LPC17xx_ADC_DMA_CHANNEL)) != 0) {
-     _adc_isr_error_code(adcp, flags);              /* DMA errors handling.*/
-   }
-  else if (adcp->half_buffer == false) {
-    _adc_isr_half_code(adcp);
-    adcp->half_buffer = true;
-  }
-  else {
-    _adc_isr_full_code(adcp);
-    adcp->half_buffer = false;
-  }
-}
-#endif
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ADC interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector98) {
-  uint32_t status;
-  uint32_t n;
-  uint8_t i;
-
-  CH_IRQ_PROLOGUE();
-  status = LPC_ADC->STAT;
-
-  n = ADCD1.num;
-
-  /* Note, an overrun may occur only in burst mode, if one or more
-     conversions was (were) lost. */
-  if ((status & ADC0STAT_OVERRUN_MASK)) {
-    if (ADCD1.grpp != NULL)
-      _adc_isr_error_code(&ADCD1, ADC_ERR_OVERRUN);
-  }
-  else {
-
-    status = status & ADC0STAT_DONE_MASK;
-    for (i = 0; i < ADC_MAX_CHANNELS; i++) {
-      if (status & (0x01 << i)) {
-        ADCD1.samples[n] = LPC_ADC->DR[i];
-        n++;
-      }
-    }
-
-    if (n == (ADCD1.nsamples / 2)) {
-      _adc_isr_half_code(&ADCD1);
-    }
-
-    if (n == ADCD1.nsamples) {
-      n = 0;
-      _adc_isr_full_code(&ADCD1);
-    }
-  }
-  ADCD1.num = n;
-  CH_IRQ_EPILOGUE();
-}
-
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-  ADCD1.adc = LPC_ADC;
-
-#if LPC17xx_ADC_USE_DMA
-  nvicDisableVector(ADC_IRQn);
-#else
-  nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(LPC17xx_ADC_IRQ_PRIORITY));
-#endif
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  /* If in stopped state then enables the ADC. */
-  if (adcp->state == ADC_STOP) {
-    LPC_SC->PCONP |= (1UL << 12);            /* Enable ADC power */
-
-#if LPC17xx_ADC_USE_DMA
-  dmaChannelAllocate(LPC17xx_ADC_DMA_CHANNEL, \
-                     (lpc17xx_dmaisr_t)adc_serve_dma_interrupt, \
-                     (void *)adcp);
-#endif
-  }
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  /* If in ready state then disables the ADC clock.*/
-  if (adcp->state == ADC_READY) {
-    adcp->adc->CR = 0;                              /* Clear PDN bit */
-    LPC_SC->PCONP &= ~(1UL << 12);                  /* Disable ADC power */
-
-#if LPC17xx_ADC_USE_DMA
-    dmaChannelRelease(LPC17xx_ADC_DMA_CHANNEL);
-#endif
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-
-  uint32_t dummy;
-  uint32_t cr;
-  uint8_t i;
-
-#if LPC17xx_ADC_USE_DMA
-  uint32_t dma_ch_config;
-  uint8_t ch;
-#endif
-
-  cr = adcp->grpp->cr0;
-  adcp->num = 0;
-  adcp->nsamples = adcp->depth * adcp->grpp->num_channels;
-
-  for (i = 0; i < ADC_MAX_CHANNELS; i++) {
-    dummy = adcp->adc->DR[i];  /* Clear all DONE and OVERRUN flags. */
-  }
-
-#if LPC17xx_ADC_USE_DMA
-  adcp->half_buffer = false;
-
-  ch = 0;
-  for (i = 0; i < 8; i++) {
-    if (cr & (1UL << i)) {
-      ch = i;                  /* Get number of first enabled channel. */
-      break;
-    }
-  }
-
-  /* DMA configuration */
-  lpc_adc_lli[0].srcaddr = (uint32_t)&adcp->adc->DR[ch];
-  lpc_adc_lli[0].dstaddr = (uint32_t)&adcp->samples[0];
-  lpc_adc_lli[0].lli = (uint32_t) &lpc_adc_lli[1];
-  lpc_adc_lli[0].control =
-    DMA_CTRL_TRANSFER_SIZE(adcp->nsamples/2)    |
-    DMA_CTRL_SRC_BSIZE_1                        |
-    DMA_CTRL_DST_BSIZE_1                        |
-    DMA_CTRL_SRC_WIDTH_WORD                     |
-    DMA_CTRL_DST_WIDTH_WORD                     |
-    DMA_CTRL_SRC_NOINC                          |
-    DMA_CTRL_DST_INC                            |
-    DMA_CTRL_PROT1_USER                         |
-    DMA_CTRL_PROT2_NONBUFF                      |
-    DMA_CTRL_PROT3_NONCACHE                     |
-    DMA_CTRL_INT;
-
-  lpc_adc_lli[1].srcaddr = lpc_adc_lli[0].srcaddr;
-  lpc_adc_lli[1].dstaddr = (uint32_t)&adcp->samples[adcp->nsamples/2];
-  lpc_adc_lli[1].control = lpc_adc_lli[0].control;
-
-  if (adcp->grpp->circular == true) {
-    lpc_adc_lli[1].lli = (uint32_t) &lpc_adc_lli[0];
-  }
-  else {
-    lpc_adc_lli[1].lli = 0;
-  }
-
-  dma_ch_config =
-    DMA_CFG_CH_ENABLE           |
-    DMA_CFG_SRC_PERIPH(DMA_ADC) |
-    DMA_CFG_TTYPE_P2M           |
-    DMA_CFG_IE                  |
-    DMA_CFG_ITC;
-
-  dmaChannelSrcAddr(LPC17xx_ADC_DMA_CHANNEL, lpc_adc_lli[0].srcaddr);
-  dmaChannelDstAddr(LPC17xx_ADC_DMA_CHANNEL, lpc_adc_lli[0].dstaddr);
-  dmaChannelLinkedList(LPC17xx_ADC_DMA_CHANNEL, lpc_adc_lli[0].lli);
-  dmaChannelControl(LPC17xx_ADC_DMA_CHANNEL, lpc_adc_lli[0].control);
-  dmaChannelConfig(LPC17xx_ADC_DMA_CHANNEL, dma_ch_config);
-#endif
-
-  /* ADC configuration and conversion start. */
-  adcp->adc->INTEN = adcp->grpp->inten;  /* Set ADC interrupt on selected channels */
-  adcp->adc->CR = (cr & 0x0000FFFF) | ((LPC17xx_ADC_CLKDIV - 1) << 8) | AD0CR_PDN;
-  adcp->adc->CR |= cr & 0xFFFF0000;
-
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-#if LPC17xx_ADC_USE_DMA
-  dmaChannelDisable(LPC17xx_ADC_DMA_CHANNEL);
-#endif
-  adcp->adc->CR &= ~(AD0CR_MODE_BURST | AD0CR_START_MASK);  /* Disable ADC conversion. */
-  adcp->adc->INTEN = 0;                                     /* Mask ADC interrupts. */
-}
-
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/adc_lld.h b/os/hal/platforms/LPC17xx/adc_lld.h
deleted file mode 100644
index 570ef606b..000000000
--- a/os/hal/platforms/LPC17xx/adc_lld.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx ADC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/adc_lld.h
- * @brief   LPC17xx ADC subsystem low level driver header.
- * @note    Values in samples buffer are from DR register.
- *          To get ADC values make conversion (DR >> 6) & 0x03FF.
- *          DMA only support one ADC channel.
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define ADC0STAT_DONE_MASK         0x000000FF
-#define ADC0STAT_OVERRUN_MASK      0x0000FF00
-
-#define AD0CR_PDN                  (1UL << 21)
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-
-/**
- * @brief   Maximum ADC clock frequency.
- */
-#define LPC17xx_ADCCLK_MAX          13000000
-
-/**
- * @brief   Available number of ADC channels.
- */
-#define ADC_MAX_CHANNELS            8
-/** @} */
-
-/**
- * @name    ADC  settings
- * @{
- */
-
-/**
- * @name    Available analog channels
- * @note    In software-controlled mode only
- *          one channel can be selected.
- * @{
- */
-#define AD0CR_CHANNEL0              (1UL << 0)
-#define AD0CR_CHANNEL1              (1UL << 1)
-#define AD0CR_CHANNEL2              (1UL << 2)
-#define AD0CR_CHANNEL3              (1UL << 3)
-#define AD0CR_CHANNEL4              (1UL << 4)
-#define AD0CR_CHANNEL5              (1UL << 5)
-#define AD0CR_CHANNEL6              (1UL << 6)
-#define AD0CR_CHANNEL7              (1UL << 7)
-/** @} */
-
-/**
- * @name    ADC mode types
- * @note    In software-controlled mode only one conversion
- *          is make
- * @{
- */
-#define AD0CR_MODE_SOFT             (0UL  << 16)
-#define AD0CR_MODE_BURST            (1UL  << 16)
-/** @} */
-
-/**
- * @name    Triggers selection
- * @note    Only use in software-controlled mode
- * @{
- */
-#define AD0CR_START_NO              (0UL << 24)
-#define AD0CR_START_NOW             (1UL << 24)
-#define AD0CR_START_CT16B0_CAP0     (2UL << 24)
-#define AD0CR_START_CT32B0_CAP0     (3UL << 24)
-#define AD0CR_START_CT32B0_MAT0     (4UL << 24)
-#define AD0CR_START_CT32B0_MAT1     (5UL << 24)
-#define AD0CR_START_CT16B0_MAT0     (6UL << 24)
-#define AD0CR_START_CT16B0_MAT1     (7UL << 24)
-#define AD0CR_START_MASK            (7UL << 24)
-/** @} */
-
-/**
- * @name    Trigger edge type selection
- * @note    Only use in software-controlled mode.
- * @{
- */
-#define AD0CR_EDGE_RISSING           (0UL << 27)
-#define AD0CR_EDGE_FALLING           (1UL << 27)
-/** @} */
-/** @} */
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC common clock divider.
- */
-#if !defined(LPC17xx_ADC_CLKDIV) || defined(__DOXYGEN__)
-#define LPC17xx_ADC_CLKDIV                  12
-#endif
-
-#if LPC17xx_PCLK/LPC17xx_ADC_CLKDIV > LPC17xx_ADCCLK_MAX
-#error "ADC clock frequency out of the acceptable range (13MHz max)"
-#endif
-
-/**
- * @brief   ADC interrupt priority level setting.
- */
-#if !defined(LPC17xx_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_ADC_IRQ_PRIORITY            3
-#endif
-
-/**
- * @brief   ADC DMA enable switch.
- * @details If set to @p TRUE the support for ADC DMA is included.
- * @note    ADC DMA only support one selected channel. The default is @p FALSE.
- */
-#if !defined(LPC17xx_ADC_USE_DMA) || defined(__DOXYGEN__)
-#define LPC17xx_ADC_USE_DMA                  FALSE
-#endif
-
-#if LPC17xx_ADC_USE_DMA || defined(__DOXYGEN__)
-#if !defined(LPC17xx_DMA_REQUIRED)
-#define LPC17xx_DMA_REQUIRED
-#endif
-#endif
-
-/**
- * @brief   ADC DMA channel.
- */
-#if !defined(LPC17xx_ADC_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define LPC17xx_ADC_DMA_CHANNEL                 DMA_CHANNEL6
-#endif
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-typedef uint32_t adcsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_OVERRUN = 1                      /**< ADC overrun condition.    */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    The use of this configuration structure requires knowledge of
- *          LPC17xx ADC cell registers interface, please refer to the LPC17xx
- *          reference manual for details.
- */
-typedef struct {
-  /**
-  * @brief   Enables the circular buffer mode for the group.
-  */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   ADC CR0 register initialization data.
-   * @note    All the required bits must be defined into this field.
-   */
-  uint32_t                  cr0;
-  /**
-   * @brief   ADC INTENT register initialization data.
-   * @note    In interrupt burst mode only define interrupt for
-   *          last enabled channel.
-   */
-  uint32_t                  inten;
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the ADCx registers block.
-   */
-  LPC_ADC_TypeDef           *adc;
-  /**
-   * @brief Number of all samples in buffer.
-   */
-  uint32_t                  nsamples;
-  /**
-   * @brief Samples buffer counter.
-   */
-  uint32_t                  num;
-#if LPC17xx_ADC_USE_DMA
-  /**
-   * @brief Half buffer indicator.
-   */
-  bool_t                    half_buffer;
-#endif
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/can_lld.c b/os/hal/platforms/LPC17xx/can_lld.c
deleted file mode 100644
index 39309973b..000000000
--- a/os/hal/platforms/LPC17xx/can_lld.c
+++ /dev/null
@@ -1,657 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/can_lld.c
- * @brief   LPC17xx CAN subsystem low level driver source.
- *
- * @addtogroup CAN
- * @{
- */
-
-/*
-  This file has been contributed by:
-                Marcin Jokel.
-*/
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-/* TODO: FullCAN mode. */
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief CAN1 driver identifier.*/
-#if LPC17xx_CAN_USE_CAN1 || defined(__DOXYGEN__)
-CANDriver CAND1;
-#endif
-
-/** @brief CAN2 driver identifier.*/
-#if LPC17xx_CAN_USE_CAN2 || defined(__DOXYGEN__)
-CANDriver CAND2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if LPC17xx_CAN_USE_FILTER
-/**
- * @brief   Copy table to filter ram.
- *
- * @param[in] reg
- * @param[in] ptable
- * @param[in] addr_start
- * @param[in] addr_end
- *
- * @notapi
- */
-
-static void can_lld_copy_table_to_ram(volatile uint32_t * reg,
-                                  const uint32_t * ptable,
-                                  uint32_t addr_start,
-                                  uint32_t addr_end) {
-
-  uint32_t i;
-
-  if (reg != NULL) {
-  *reg = ((addr_start * 4) << 2);
-  }
-   for (i = addr_start; i < addr_end; i++) {
-     LPC_CANAF_RAM->mask[i] = ptable[i];
-   }
-}
-
-/**
- * @brief   Programs the filters.
- *
- * @param[in] cfc       pointer to the can filter configuration structure
- *
- * @notapi
- */
-static void can_lld_set_filter( const CANFilterConfig *cfc) {
-
-  uint32_t addr_start;
-  uint32_t addr_end;
-
-  LPC_CANAF->AFMR = AFMR_ACC_OFF;           /* Acceptance filter off mode. */
-
-  addr_start = cfc->fc_id_table_n;
-
-  if (addr_start > 0) {
-    can_lld_copy_table_to_ram(NULL, cfc->fc_id_table, 0, addr_start);
-  }
-
-  addr_start = cfc->fc_id_table_n;
-  addr_end = cfc->std_id_table_n;
-
-  can_lld_copy_table_to_ram(&LPC_CANAF->SFF_sa, cfc->std_id_table, addr_start, addr_end);
-
-  addr_start = addr_end;
-  addr_end += cfc->std_range_id_table_n;
-
-  can_lld_copy_table_to_ram(&LPC_CANAF->SFF_GRP_sa, cfc->std_range_id_table, addr_start, addr_end);
-
-  addr_start = addr_end;
-  addr_end += cfc->ext_id_table_n;
-
-  can_lld_copy_table_to_ram(&LPC_CANAF->EFF_sa, cfc->ext_id_table, addr_start, addr_end);
-
-  addr_start = addr_end;
-  addr_end += cfc->ext_range_id_table_n;
-
-  can_lld_copy_table_to_ram(&LPC_CANAF->EFF_GRP_sa, cfc->ext_range_id_table, addr_start, addr_end);
-
-  LPC_CANAF->ENDofTable = (addr_end * 4) << 2;
-
-  LPC_CANAF->AFMR = cfc->afmr;
-}
-#endif
-
-/**
- * @brief   Common TX ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_tx_handler(CANDriver *canp) {
-
-  /* All transmit buffers are available.*/
-  if (canp->can->GSR & CANGSR_TBS) {
-    chSysLockFromIsr();
-    while (chSemGetCounterI(&canp->txsem) < 0)
-      chSemSignalI(&canp->txsem);
-    chEvtBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1));
-    chSysUnlockFromIsr();
-  }
-}
-
-/**
- * @brief   Common RX ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] status
- * @notapi
- */
-static void can_lld_rx_handler(CANDriver *canp, uint32_t status) {
-
-  /* No more receive events until the queue 0 has been emptied.*/
-  canp->can->IER &= ~CANIER_RIE;
-  chSysLockFromIsr();
-  while (chSemGetCounterI(&canp->rxsem) < 0)
-    chSemSignalI(&canp->rxsem);
-  chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1));
-  chSysUnlockFromIsr();
-
-  if (( status & CANICR_DOI) > 0) {
-    /* Overflow events handling.*/
-    canp->can->CMR = CANCMR_CDO;
-    chSysLockFromIsr();
-    chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
-    chSysUnlockFromIsr();
-  }
-}
-
-/**
- * @brief   Error ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] flags
- *
- * @notapi
- */
-static void can_lld_error_handler(CANDriver *canp, uint32_t status) {
-
-  uint32_t flags;
-
-  /* Error event.*/
-  /* The high 16-bits of the ICR register (error codes for bus error)
-     is copied unchanged in the upper half word of the listener flags mask.*/
-  flags = status & 0xFFFF0000;
-  if (status & CANICR_EI)
-    flags |= CAN_WARNING_ERROR;
-  if (status & CANICR_EPI)
-    flags |= CAN_PASSIVE_ERROR;
-  if (status & CANICR_BEI)
-      flags |= CAN_BUS_ERROR;
-
-  chSysLockFromIsr();
-  chEvtBroadcastFlagsI(&canp->error_event, flags);
-  chSysUnlockFromIsr();
-}
-
-
-#if CAN_USE_SLEEP_MODE
-/**
- * @brief   Wake up ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_wakeup_handler(CANDriver *canp) {
-
-  /* Wakeup event.*/
-  canp->state = CAN_READY;
-  can_lld_wakeup(canp);
-  chSysLockFromIsr();
-  chEvtBroadcastI(&canp->wakeup_event);
-  chSysUnlockFromIsr();
-
-}
-#endif /* CAN_USE_SLEEP_MODE */
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC17xx_CAN_USE_CAN1 || LPC17xx_CAN_USE_CAN2 ||defined(__DOXYGEN__)
-/**
- * @brief   CAN Common, CAN 1 Tx, CAN 1 Rx, CAN 2 Tx, CAN 2 Rx.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorA4) {
-
-#if LPC17xx_CAN_USE_CAN1
-  volatile uint32_t can1_status;
-#endif
-#if LPC17xx_CAN_USE_CAN2
-  volatile uint32_t can2_status;
-#endif
-
-  CH_IRQ_PROLOGUE();
-
-#if LPC17xx_CAN_USE_CAN1
-  can1_status = LPC_CAN1->ICR;
-#endif
-#if LPC17xx_CAN_USE_CAN2
-  can2_status = LPC_CAN2->ICR;
-#endif
-
-#if LPC17xx_CAN_USE_CAN1
-  if (can1_status & 0x000007FF) {
-
-    if (can1_status & (CANICR_EI | CANICR_EPI | CANICR_BEI)) {
-      can_lld_error_handler(&CAND1, can1_status);
-    }
-
-    if (can1_status & (CANICR_RI | CANICR_DOI)) {
-      can_lld_rx_handler(&CAND1, can1_status);
-    }
-
-    if (can1_status & (CANICR_TI1 | CANICR_TI2 | CANICR_TI3)){
-      can_lld_tx_handler(&CAND1);
-    }
-  }
-#endif
-
-#if LPC17xx_CAN_USE_CAN2
-  if (can2_status & 0x000007FF) {
-
-    if (can2_status & CANICR_EI) {
-      can_lld_error_handler(&CAND2, can2_status);
-    }
-
-    if (can2_status & (CANICR_RI | CANICR_DOI)) {
-      can_lld_rx_handler(&CAND2, can2_status);
-    }
-
-    if (can2_status & (CANICR_TI1 | CANICR_TI2 | CANICR_TI3)){
-      can_lld_tx_handler(&CAND2);
-    }
-  }
-#endif
-  CH_IRQ_EPILOGUE();
-}
-
-#if CAN_USE_SLEEP_MODE
-/**
- * @brief   CAN Common, CAN 1 Tx, CAN 1 Rx, CAN 2 Tx, CAN 2 Rx.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorC8) {
-
-#if LPC17xx_CAN_USE_CAN1
- uint32_t can1_status;
-#endif
-#if LPC17xx_CAN_USE_CAN2
- uint32_t can2_status;
-#endif
-
- CH_IRQ_PROLOGUE();
-
-#if LPC17xx_CAN_USE_CAN1
- can1_status = LPC_CAN1->ICR;
-#endif
-#if LPC17xx_CAN_USE_CAN2
- can2_status = LPC_CAN2->ICR;
-#endif
-
-#if LPC17xx_CAN_USE_CAN1
- if (can1_status & CANICR_WUI) {
-   can_lld_wakeup_handler(&CAND1);
- }
-#endif
-
-#if LPC17xx_CAN_USE_CAN2
- if (can2_status & CANICR_WUI) {
-   can_lld_wakeup_handler(&CAND2);
- }
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* CAN_USE_SLEEP_MODE */
-
-#endif /* LPC17xx_CAN_USE_CAN1 || LPC17xx_CAN_USE_CAN2 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level CAN driver initialization.
- *
- * @notapi
- */
-void can_lld_init(void) {
-
-#if LPC17xx_CAN_USE_CAN1
-  /* Driver initialization.*/
-  canObjectInit(&CAND1);
-  CAND1.can = LPC_CAN1;
-#endif
-#if LPC17xx_CAN_USE_CAN2
-  /* Driver initialization.*/
-  canObjectInit(&CAND2);
-  CAND2.can = LPC_CAN2;
-#endif
-
-}
-
-/**
- * @brief   Configures and activates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_start(CANDriver *canp) {
-
-#if LPC17xx_CAN_USE_CAN1
-  if (&CAND1 == canp) {
-    LPC_SC->PCONP |= (1UL << 13);
-  }
-#endif
-#if LPC17xx_CAN_USE_CAN2
-  if (&CAND2 == canp) {
-    LPC_SC->PCONP |= (1UL << 14);
-  }
-#endif
-
-  canp->can->MOD = CANMOD_RM;           /* Reset mode. */
-
-#if !LPC17xx_CAN_USE_FILTER
-  LPC_CANAF->AFMR = AFMR_ACC_BP;        /* Bypass can filter. */
-#endif
-
-  /* Entering initialization mode. */
-  canp->state = CAN_STARTING;
-
-  canp->can->BTR = canp->config->btr;   /* BTR initialization.*/
-  canp->can->CMR = CANCMR_RRB;
-
-  /* Interrupt sources initialization.*/
-  canp->can->IER = CANIER_TIE3 | CANIER_TIE2 | CANIER_BEIE |
-                   CANIER_EPIE | CANIER_DOIE | CANIER_EIE  |
-                   CANIER_TIE1 | CANIER_RIE;
-
-#if CAN_USE_SLEEP_MODE
-  canp->can->IER |= CANIER_WUIE;
-  nvicEnableVector(CANActivity_IRQn,
-                           CORTEX_PRIORITY_MASK(LPC17xx_CAN_IRQ_PRIORITY));
-#endif /* CAN_USE_SLEEP_MODE */
-
-  canp->can->MOD = canp->config->mod;       /* Operating mode. */
-
-  nvicEnableVector(CAN_IRQn,
-                         CORTEX_PRIORITY_MASK(LPC17xx_CAN_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Deactivates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_stop(CANDriver *canp) {
-
-  /* If in ready state then disables the CAN peripheral.*/
-  if (canp->state == CAN_READY) {
-
-    canp->can->MOD = CANMOD_RM;                 /* Reset mode. */
-    canp->can->IER = 0;
-#if (LPC17xx_CAN_USE_CAN1 && LPC17xx_CAN_USE_CAN2) == 0
-    nvicDisableVector(CAN_IRQn);                /* Interrupt disabled only if one CAN is in use. */
-#endif
-
-#if LPC17xx_CAN_USE_CAN1
-    if (&CAND1 == canp) {
-      LPC_SC->PCONP &= ~(1UL << 13);
-    }
-#endif
-#if LPC17xx_CAN_USE_CAN2
-    if (&CAND2 == canp) {
-      LPC_SC->PCONP &= ~(1UL << 14);
-    }
-#endif
-
-#if CAN_USE_SLEEP_MODE
-    nvicDisableVector(CANActivity_IRQn);
-#endif /* CAN_USE_SLEEP_MODE */
-  }
-}
-
-/**
- * @brief   Determines whether a frame can be transmitted.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return              The queue space availability.
- * @retval FALSE        no space in the transmit queue.
- * @retval TRUE         transmit slot available.
- *
- * @notapi
- */
-bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
-
-  switch (mailbox) {
-  case CAN_ANY_MAILBOX:
-    return ((canp->can->SR & (CANSR_TBS1 | CANSR_TBS2 | CANSR_TBS3)) != 0);
-  case 1:
-    return (canp->can->SR & CANSR_TBS1) != 0;
-  case 2:
-    return (canp->can->SR & CANSR_TBS2) != 0;
-  case 3:
-    return (canp->can->SR & CANSR_TBS3) != 0;
-  default:
-    return FALSE;
-  }
-}
-
-/**
- * @brief   Inserts a frame into the transmit queue.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] ctfp      pointer to the CAN frame to be transmitted
- * @param[in] mailbox   mailbox number,  @p CAN_ANY_MAILBOX for any mailbox
- *
- * @notapi
- */
-void can_lld_transmit(CANDriver *canp,
-                      canmbx_t mailbox,
-                      const CANTxFrame *ctfp) {
-  volatile uint32_t * tfi;
-  uint32_t tbs_n;
-  uint32_t sr;
-
-  tbs_n = mailbox;
-
-  if (mailbox == CAN_ANY_MAILBOX) {
-    sr = canp->can->SR;
-    if (sr & CANSR_TBS1) {
-      tbs_n = 1;
-    }
-    else if (sr & CANSR_TBS2) {
-      tbs_n = 2;
-    }
-    else if (sr & CANSR_TBS3) {
-      tbs_n = 3;
-    }
-    else {
-      return;
-    }
-  }
-
-  /* Pointer to a free transmission mailbox.*/
-  switch (tbs_n) {
-  case 1:
-    tfi = &canp->can->TFI1;
-    break;
-  case 2:
-    tfi = &canp->can->TFI2;
-    break;
-  case 3:
-    tfi = &canp->can->TFI3;
-    break;
-  default:
-    return;
-  }
-
-  /* Preparing the message.*/
-  * tfi = ((uint32_t)ctfp->IDE << 31) | ((uint32_t)ctfp->RTR << 30) |
-      (((uint32_t)ctfp->DLC) << 16);    /* CAN Transmit Frame Information Register. */
-  if (ctfp->IDE)
-    *(tfi + 1) = ctfp->EID;             /* CAN Transmit Identifier register 29-bit. */
-  else
-    *(tfi + 1) = ctfp->SID;             /* CAN Transmit Identifier register 11-bit. */
-
-  *(tfi + 2) = ctfp->data32[0];         /* CAN Transmit Data Register A. */
-  *(tfi + 3) = ctfp->data32[1];         /* CAN Transmit Data Register B. */
-
-#if LPC17xx_CAN_USE_LOCAL_SELF_TEST
-  canp->can->CMR = (1UL << (4 + tbs_n)) | CANCMR_SRR;
-#else
-  canp->can->CMR = (1UL << (4 + tbs_n)) | CANCMR_TR;
-#endif
-}
-
-/**
- * @brief   Determines whether a frame has been received.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return              The queue space availability.
- * @retval FALSE        no space in the transmit queue.
- * @retval TRUE         transmit slot available.
- *
- * @notapi
- */
-bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
-
-  switch (mailbox) {
-  case CAN_ANY_MAILBOX:
-  case 1:
-    return ((canp->can->GSR & CANGSR_RBS) != 0);
-  default:
-    return FALSE;
-  }
-}
-
-/**
- * @brief   Receives a frame from the input queue.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @param[out] crfp     pointer to the buffer where the CAN frame is copied
- *
- * @notapi
- */
-void can_lld_receive(CANDriver *canp,
-                     canmbx_t mailbox,
-                     CANRxFrame *crfp) {
-  uint32_t rfs, rid;
-
-  switch (mailbox) {
-  case CAN_ANY_MAILBOX:
-  case 1:
-    /* Fetches the message.*/
-    rfs = canp->can->RFS;
-    rid = canp->can->RID;
-    crfp->data32[0] = canp->can->RDA;
-    crfp->data32[1] = canp->can->RDB;
-
-    /* Releases the mailbox.*/
-    canp->can->CMR = CANCMR_RRB;
-
-    /* Re-enables the interrupt in order to generate
-       events again. */
-    canp->can->IER |= CANIER_RIE;
-    break;
-  default:
-    /* Should not happen, do nothing.*/
-    return;
-  }
-
-  /* Decodes the various fields in the RX frame.*/
-  crfp->RTR = (rfs & CANRFS_RTR) >> 30;
-  crfp->IDE = (rfs & CANRFS_FF) >> 31;
-  if (crfp->IDE) {
-    crfp->EID = rid;
-  }
-  else {
-    crfp->SID = rid;
-  }
-  crfp->DLC = (rfs & CANRFS_DLC) >> 16;
-  crfp->IDF = (uint16_t)(rfs & CANRFS_ID);
-}
-
-#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
-/**
- * @brief   Enters the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_sleep(CANDriver *canp) {
-
-  canp->can->MOD |= CANMOD_SM;
-}
-
-/**
- * @brief   Enforces leaving the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_wakeup(CANDriver *canp) {
-
-  uint32_t reg_val;
-
-#if LPC17xx_CAN_USE_CAN1
-  if (&CAND1 == canp) {
-    reg_val = (1UL << 1);
-  }
-#endif
-#if LPC17xx_CAN_USE_CAN2
-  if (&CAND2 == canp) {
-    reg_val = (1UL << 2);
-  }
-#endif
-
-  LPC_SC->CANSLEEPCLR = reg_val;
-  canp->can->MOD &= ~CANMOD_SM;
-  LPC_SC->CANWAKEFLAGS = reg_val;
-}
-#endif /* CAN_USE_SLEEP_MODE */
-
-#if LPC17xx_CAN_USE_FILTER
-void canSetFilter(const CANFilterConfig *cfc) {
-  can_lld_set_filter(cfc);
-}
-#endif
-
-#endif /* HAL_USE_CAN */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/can_lld.h b/os/hal/platforms/LPC17xx/can_lld.h
deleted file mode 100644
index b265c9412..000000000
--- a/os/hal/platforms/LPC17xx/can_lld.h
+++ /dev/null
@@ -1,645 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/can_lld.h
- * @brief   LPC17xx CAN subsystem low level driver header.
- *
- * @addtogroup CAN
- * @{
- */
-
-/*
-  This file has been contributed by:
-                Marcin Jokel.
-*/
-
-#ifndef _CAN_LLD_H_
-#define _CAN_LLD_H_
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-/* TODO: FullCAN mode. */
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*
- *  CAN Mode register bits.
- */
-#define CANMOD_RM                   (1UL << 0)
-#define CANMOD_LOM                  (1UL << 1)
-#define CANMOD_STM                  (1UL << 2)
-#define CANMOD_TPM                  (1UL << 3)
-#define CANMOD_SM                   (1UL << 4)
-#define CANMOD_RPM                  (1UL << 5)
-#define CANMOD_TM                   (1UL << 7)
-
-/*
- *  CAN Command register bits.
- */
-#define CANCMR_TR                   (1UL << 0)
-#define CANCMR_AT                   (1UL << 1)
-#define CANCMR_RRB                  (1UL << 2)
-#define CANCMR_CDO                  (1UL << 3)
-#define CANCMR_SRR                  (1UL << 4)
-#define CANCMR_STB1                 (1UL << 5)
-#define CANCMR_STB2                 (1UL << 6)
-#define CANCMR_STB3                 (1UL << 7)
-
-/*
- *  CAN Global Status register bits.
- */
-#define CANGSR_RBS                  (1UL << 0)
-#define CANGSR_DOS                  (1UL << 1)
-#define CANGSR_TBS                  (1UL << 2)
-#define CANGSR_TCS                  (1UL << 3)
-#define CANGSR_RS                   (1UL << 4)
-#define CANGSR_TS                   (1UL << 5)
-#define CANGSR_ES                   (1UL << 6)
-#define CANGSR_BS                   (1UL << 7)
-#define CANGSR_RXERR                0x00FF0000
-#define CANGSR_TXERR                0xFF000000
-
-/*
- *  CAN Interrupt and Capture register bits.
- */
-#define CANICR_RI                   (1UL << 0)
-#define CANICR_TI1                  (1UL << 1)
-#define CANICR_EI                   (1UL << 2)
-#define CANICR_DOI                  (1UL << 3)
-#define CANICR_WUI                  (1UL << 4)
-#define CANICR_EPI                  (1UL << 5)
-#define CANICR_ALI                  (1UL << 6)
-#define CANICR_BEI                  (1UL << 7)
-#define CANICR_IDI                  (1UL << 8)
-#define CANICR_TI2                  (1UL << 9)
-#define CANICR_TI3                  (1UL << 10)
-#define CANICR_ERRBIT               0x001F0000
-#define CANICR_ERRBIT_SOF           0x00030000
-#define CANICR_ERRBIT_ID28_ID21     0x00020000
-#define CANICR_ERRBIT_ID20_ID18     0x00060000
-#define CANICR_ERRBIT_SRTR          0x00040000
-#define CANICR_ERRBIT_IDE           0x00050000
-#define CANICR_ERRBIT_ID17_ID13     0x00070000
-#define CANICR_ERRBIT_ID12_ID5      0x000F0000
-#define CANICR_ERRBIT_ID4_ID0       0x000E0000
-#define CANICR_ERRBIT_RTR           0x000C0000
-#define CANICR_ERRBIT_RES_BIT1      0x000D0000
-#define CANICR_ERRBIT_RES_BIT0      0x00090000
-#define CANICR_ERRBIT_DATA_LEN_CODE 0x000B0000
-#define CANICR_ERRBIT_DATA_FIELD    0x000A0000
-#define CANICR_ERRBIT_CRC_SEQ       0x00080000
-#define CANICR_ERRBIT_CRC_DEL       0x00180000
-#define CANICR_ERRBIT_ACK_SLOT      0x00190000
-#define CANICR_ERRBIT_ACK_DEL       0x001B0000
-#define CANICR_ERRBIT_EOF           0x001A0000
-#define CANICR_ERRBIT_INTERMISSION  0x00120000
-#define CANICR_ERRBIT_ACTIVE_ERROR  0x00110000
-#define CANICR_ERRBIT_PASSIVE_ERROR 0x00160000
-#define CANICR_ERRBIT_TOL_DOM_BITS  0x00130000
-#define CANICR_ERRBIT_ERROR_DEL     0x00170000
-#define CANICR_ERRBIT_OVERLOAD      0x001C0000
-#define CANICR_ERRDIR               (1UL << 21)
-#define CANICR_ERRC                 (3UL << 22)
-#define CANICR_ERRC_BIT_ERR         (0UL << 22)
-#define CANICR_ERRC_FORM_ERR        (1UL << 22)
-#define CANICR_ERRC_STUFF_ERR       (2UL << 22)
-#define CANICR_ERRC_OTHER_ERR       (3UL << 22)
-#define CANICR_ALCBIT               0xFF000000
-
-/*
- *  CAN Interrupt Enable register bits.
- */
-#define CANIER_RIE                  (1UL << 0)
-#define CANIER_TIE1                 (1UL << 1)
-#define CANIER_EIE                  (1UL << 2)
-#define CANIER_DOIE                 (1UL << 3)
-#define CANIER_WUIE                 (1UL << 4)
-#define CANIER_EPIE                 (1UL << 5)
-#define CANIER_ALIE                 (1UL << 6)
-#define CANIER_BEIE                 (1UL << 7)
-#define CANIER_IDIE                 (1UL << 8)
-#define CANIER_TIE2                 (1UL << 9)
-#define CANIER_TIE3                 (1UL << 10)
-
-/*
- *   CAN Bus Timing register bits.
- */
-#define CANBTR_BRP(t)               ((t) << 0)
-#define CANBTR_SJW(t)               ((t) << 14)
-#define CANBTR_TESG1(t)             ((t) << 16)
-#define CANBTR_TESG2(t)             ((t) << 20)
-#define CANBTR_SAM                  (1UL << 23)
-
-/*
- *    CAN Status register bits.
- */
-#define CANSR_RBS                   (1UL << 0)
-#define CANSR_DOS                   (1UL << 1)
-#define CANSR_TBS1                  (1UL << 2)
-#define CANSR_TCS1                  (1UL << 3)
-#define CANSR_RS                    (1UL << 4)
-#define CANSR_TS1                   (1UL << 5)
-#define CANSR_ES                    (1UL << 6)
-#define CANSR_BS                    (1UL << 7)
-#define CANSR_TBS2                  (1UL << 10)
-#define CANSR_TCS2                  (1UL << 11)
-#define CANSR_TS2                   (1UL << 13)
-#define CANSR_TBS3                  (1UL << 18)
-#define CANSR_TCS3                  (1UL << 19)
-#define CANSR_TS3                   (1UL << 21)
-
-/*
- *    CAN Receive Frame Status register bits.
- */
-#define CANRFS_ID                   0x000001FF
-#define CANRFS_BP                   (1UL << 10)
-#define CANRFS_DLC                  0x000F0000
-#define CANRFS_RTR                  (1UL << 30)
-#define CANRFS_FF                   (1UL << 31)
-
-/*
- *    CAN Transmit Frame Information register bits.
- */
-#define CANTFI_PRIO(p)              ((p) << 0)
-#define CANTFI_DLC(l)               ((l) << 16)
-#define CANTFI_RTR                  (1UL << 30)
-#define CANTFI_FF                   (1UL << 31)
-
-/*
- *    CAN Sleep Clear register bits.
- */
-#define CANSLEEPCLR_CAN1SLEEP       (1UL << 1)
-#define CANSLEEPCLR_CAN2SLEEP       (1UL << 2)
-
-/*
- *    CAN Wake-up Flags register bits.
- */
-#define CANWAKEFLAGS_CAN1WAKE       (1UL << 1)
-#define CANWAKEFLAGS_CAN2WAKE       (1UL << 2)
-
-/*
- *    Central Transmit Status register bits.
- */
-#define CANTSR_TS1                  (1UL << 0)
-#define CANTSR_TS2                  (1UL << 1)
-#define CANTSR_TBS1                 (1UL << 8)
-#define CANTSR_TBS2                 (1UL << 9)
-#define CANTSR_TCS1                 (1UL << 16)
-#define CANTSR_TCS2                 (1UL << 17)
-
-/*
- *     Central Receive Status register bits.
- */
-#define CANRSR_RS1                  (1UL << 0)
-#define CANRSR_RS2                  (1UL << 1)
-#define CANRSR_RB1                  (1UL << 8)
-#define CANRSR_RB2                  (1UL << 9)
-#define CANRSR_DOS1                 (1UL << 16)
-#define CANRSR_DOS2                 (1UL << 17)
-
-/*
- *     Central Miscellaneous Status register bits.
- */
-#define CANMSR_E1                   (1UL << 0)
-#define CANMSR_E2                   (1UL << 1)
-#define CANMSR_BS1                  (1UL << 8)
-#define CANMSR_BS2                  (1UL << 9)
-
-/*
- *     Acceptance Filter Mode register bits.
- */
-#define AFMR_ACC_OFF                (1UL << 0)
-#define AFMR_ACC_BP                 (1UL << 1)
-#define AFMR_E_FCAN                 (1UL << 2)
-
-/**
- * @brief   This switch defines whether the driver implementation supports
- *          a low power switch mode with automatic an wakeup feature.
- */
-#define CAN_SUPPORTS_SLEEP          TRUE
-
-/**
- * @brief   This implementation supports three transmit mailboxes.
- */
-#define CAN_TX_MAILBOXES            3
-
-/**
- * @brief   This implementation supports two receive mailboxes.
- */
-#define CAN_RX_MAILBOXES            1
-
-/** @} */
-
-/**
- * @name    CAN registers helper macros
- * @{
- */
-#define CAN_IDE_STD                 0           /**< @brief Standard id.    */
-#define CAN_IDE_EXT                 1           /**< @brief Extended id.    */
-
-#define CAN_RTR_DATA                0           /**< @brief Data frame.     */
-#define CAN_RTR_REMOTE              1           /**< @brief Remote frame.   */
-
-#undef CAN_LIMIT_WARNING
-#undef CAN_LIMIT_ERROR
-#undef CAN_BUS_OFF_ERROR
-#undef CAN_FRAMING_ERROR
-
-#define CAN_WARNING_ERROR           1
-#define CAN_PASSIVE_ERROR           2
-#define CAN_BUS_ERROR               4
-
-/**
- * @brief   CAN filter fullCAN (standard identifier) type entry.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-#define CANFilterFCEntry(ctrl_i1, dis_i1, id_i1, ctrl_i2, dis_i2, id_i2)                       \
-  ((((uint32_t)ctrl_i1) << 29) | (((uint32_t)dis_i1) << 28) | (((uint32_t)id_i1) << 16)   |     \
-   (((uint32_t)ctrl_i2) << 13)  | (((uint32_t)dis_i2) << 12)  | ((uint32_t)(id_i2)))
-
-/**
- * @brief   CAN filter standard identifier type entry.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-#define CANFilterStdEntry(ctrl_i1, dis_i1, id_i1, ctrl_i2, dis_i2, id_i2)                       \
-  ((((uint32_t)ctrl_i1) << 29) | (((uint32_t)dis_i1) << 28) | (((uint32_t)id_i1) << 16)   |     \
-   (((uint32_t)ctrl_i2) << 13)  | (((uint32_t)dis_i2) << 12)  | ((uint32_t)(id_i2)))
-/**
- * @brief   CAN filter extended identifier range type entry.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-#define CANFilterStdRangeEntry(ctrl_low, dis_low, id_low, ctrl_high, dis_high, id_high)         \
-  ((((uint32_t)ctrl_low) << 29) | (((uint32_t)dis_low) << 28) | (((uint32_t)id_low) << 16)   |  \
-   (((uint32_t)ctrl_up) << 13)  | (((uint32_t)dis_up) << 12)  | ((uint32_t)(id_up)))
-
-/**
- * @brief   CAN filter extended identifier type entry.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-#define CANFilterExtEntry(ctrl, id) \
-  ((((uint32_t)ctrl) << 29) | ((uint32_t)(id)))
-
-/**
- * @brief   CAN filter extended range identifier type entry.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-#define CANFilterExtRangeEntry(ctrl, id) \
-  ((((uint32_t)ctrl) << 29) | ((uint32_t)(id)))
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   CAN1 driver enable switch.
- * @details If set to @p TRUE the support for CAN1 is included.
- */
-#if !defined(LPC17xx_CAN_USE_CAN1) || defined(__DOXYGEN__)
-#define LPC17xx_CAN_USE_CAN1                  FALSE
-#endif
-
-/**
- * @brief   CAN2 driver enable switch.
- * @details If set to @p TRUE the support for CAN2 is included.
- */
-#if !defined(LPC17xx_CAN_USE_CAN2) || defined(__DOXYGEN__)
-#define LPC17xx_CAN_USE_CAN2                  FALSE
-#endif
-
-/**
- * @brief   CAN1 and CAN2 interrupt priority level setting.
- */
-#if !defined(LPC17xx_CAN_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_CAN_IRQ_PRIORITY              11
-#endif
-/** @} */
-
-/**
- * @brief   CAN1 and CAN2 local self test enable.
- */
-#if !defined(LPC17xx_CAN_USE_LOCAL_SELF_TEST) || defined(__DOXYGEN__)
-#define LPC17xx_CAN_USE_LOCAL_SELF_TEST       FALSE
-#endif
-/** @} */
-
-/**
- * @brief   CAN1 and CAN2 acceptance filter enable.
- */
-#if !defined(LPC17xx_CAN_USE_FILTER) || defined(__DOXYGEN__)
-#define LPC17xx_CAN_USE_FILTER              FALSE
-#endif
-/** @} */
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if LPC17xx_CAN_USE_CAN1 && !LPC17xx_HAS_CAN1
-#error "CAN1 not present in the selected device"
-#endif
-
-#if LPC17xx_CAN_USE_CAN2 && !LPC17xx_HAS_CAN2
-#error "CAN2 not present in the selected device"
-#endif
-
-#if !LPC17xx_CAN_USE_CAN1 && !LPC17xx_CAN_USE_CAN2
-#error "CAN driver activated but no CAN peripheral assigned"
-#endif
-
-#if !LPC17xx_CAN_USE_CAN1 && LPC17xx_CAN_USE_CAN2
-#error "CAN2 requires CAN1, it cannot operate independently"
-#endif
-
-#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
-#error "CAN sleep mode not supported in this architecture"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a transmission mailbox index.
- */
-typedef uint32_t canmbx_t;
-
-/**
- * @brief   CAN transmission frame.
- * @note    Accessing the frame data as word16 or word32 is not portable because
- *          machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
-  struct {
-    uint8_t                 DLC:4;          /**< @brief Data length.        */
-    uint8_t                 RTR:1;          /**< @brief Frame type.         */
-    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t              SID:11;         /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t              EID:29;         /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t                 data8[8];       /**< @brief Frame data.         */
-    uint16_t                data16[4];      /**< @brief Frame data.         */
-    uint32_t                data32[2];      /**< @brief Frame data.         */
-  };
-} CANTxFrame;
-
-/**
- * @brief   CAN received frame.
- * @note    Accessing the frame data as word16 or word32 is not portable because
- *          machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
-  struct {
-    uint16_t                IDF:10;          /**< @brief Filter id.          */
-  };
-  struct {
-    uint8_t                 DLC:4;          /**< @brief Data length.        */
-    uint8_t                 RTR:1;          /**< @brief Frame type.         */
-    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t              SID:11;         /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t              EID:29;         /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t                 data8[8];       /**< @brief Frame data.         */
-    uint16_t                data16[4];      /**< @brief Frame data.         */
-    uint32_t                data32[2];      /**< @brief Frame data.         */
-  };
-} CANRxFrame;
-
-/**
- * @brief   CAN filter standard identifier type.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-typedef const uint32_t CANFilterStd;
-
-/**
- * @brief   CAN filter standard identifier range type.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-typedef const uint32_t CANFilterStdRange;
-
-/**
- * @brief   CAN filter extended identifier range type.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-typedef  const uint32_t CANFilterExt;
-
-/**
- * @brief   CAN filter extended range identifier type.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-typedef  const uint32_t CANFilterExtRange;
-
-/**
- * @brief   CAN filter configuration structure.
- * @note    Refer to the LPC17xx reference manual for info about filters.
- */
-typedef struct {
-  /**
-   * @brief   Acceptance filter mode register.
-   */
-  uint32_t                  afmr;
-  /**
-   * @brief   FullCAN (standard identifier) table.
-   */
-  CANFilterStd              *fc_id_table;
-  /**
-     * @brief  Number of positions in fullCAN (standard identifier) table.
-     */
-  uint32_t                  fc_id_table_n;
-  /**
-   * @brief   Standard identifier table.
-   */
-  CANFilterStd              *std_id_table;
-  /**
-     * @brief  Number of positions in standard identifier table.
-     */
-  uint32_t                  std_id_table_n;
-  /**
-   * @brief   Standard range identifier table.
-   */
-  CANFilterStdRange         *std_range_id_table;
-  /**
-   * @brief   Number of positions in standard range identifier table.
-   */
-  uint32_t                  std_range_id_table_n;
-  /**
-   * @brief   Extended identifier table.
-   */
-  CANFilterExt              *ext_id_table;
-  /**
-   * @brief   Number of positions in extended identifier table.
-   */
-  uint32_t                  ext_id_table_n;
-  /**
-   * @brief   Extended range identifier table.
-   */
-  CANFilterExtRange         *ext_range_id_table;
-  /**
-   * @brief   Number of positions in extended range identifier table.
-   */
-  uint32_t                  ext_range_id_table_n;
-} CANFilterConfig;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   CAN MOD register initialization data.
-   * @note    Some bits in this register are enforced by the driver regardless
-   *          their status in this field.
-   */
-  uint32_t                  mod;
-  /**
-   * @brief   CAN BTR register initialization data.
-   * @note    Some bits in this register are enforced by the driver regardless
-   *          their status in this field.
-   */
-  uint32_t                  btr;
-} CANConfig;
-
-/**
- * @brief   Structure representing an CAN driver.
- */
-typedef struct {
-  /**
-   * @brief   Driver state.
-   */
-  canstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const CANConfig           *config;
-  /**
-   * @brief   Transmission queue semaphore.
-   */
-  Semaphore                 txsem;
-  /**
-   * @brief   Receive queue semaphore.
-   */
-  Semaphore                 rxsem;
-  /**
-   * @brief   One or more frames become available.
-   * @note    After broadcasting this event it will not be broadcasted again
-   *          until the received frames queue has been completely emptied. It
-   *          is <b>not</b> broadcasted for each received frame. It is
-   *          responsibility of the application to empty the queue by
-   *          repeatedly invoking @p chReceive() when listening to this event.
-   *          This behavior minimizes the interrupt served by the system
-   *          because CAN traffic.
-   * @note    The flags associated to the listeners will indicate which
-   *          receive mailboxes become non-empty.
-   */
-  EventSource               rxfull_event;
-  /**
-   * @brief   One or more transmission mailbox become available.
-   * @note    The flags associated to the listeners will indicate which
-   *          transmit mailboxes become empty.
-   *
-   */
-  EventSource               txempty_event;
-  /**
-   * @brief   A CAN bus error happened.
-   * @note    The flags associated to the listeners will indicate the
-   *          error(s) that have occurred.
-   */
-  EventSource               error_event;
-#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
-  /**
-   * @brief   Entering sleep state event.
-   */
-  EventSource               sleep_event;
-  /**
-   * @brief   Exiting sleep state event.
-   */
-  EventSource               wakeup_event;
-#endif /* CAN_USE_SLEEP_MODE */
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Pointer to the CAN registers.
-   */
-  LPC_CAN_TypeDef               *can;
-} CANDriver;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC17xx_CAN_USE_CAN1 && !defined(__DOXYGEN__)
-extern CANDriver CAND1;
-#endif
-
-#if LPC17xx_CAN_USE_CAN2 && !defined(__DOXYGEN__)
-extern CANDriver CAND2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void can_lld_init(void);
-  void can_lld_start(CANDriver *canp);
-  void can_lld_stop(CANDriver *canp);
-  bool_t can_lld_is_tx_empty(CANDriver *canp,
-                             canmbx_t mailbox);
-  void can_lld_transmit(CANDriver *canp,
-                        canmbx_t mailbox,
-                        const CANTxFrame *crfp);
-  bool_t can_lld_is_rx_nonempty(CANDriver *canp,
-                                canmbx_t mailbox);
-  void can_lld_receive(CANDriver *canp,
-                       canmbx_t mailbox,
-                       CANRxFrame *ctfp);
-#if CAN_USE_SLEEP_MODE
-  void can_lld_sleep(CANDriver *canp);
-  void can_lld_wakeup(CANDriver *canp);
-#endif /* CAN_USE_SLEEP_MODE */
-#if LPC17xx_CAN_USE_FILTER
-  void canSetFilter(const CANFilterConfig *cfc);
-#endif  /* LPC17xx_CAN_USE_FILTER */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_CAN */
-
-#endif /* _CAN_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/dac_lld.c b/os/hal/platforms/LPC17xx/dac_lld.c
deleted file mode 100644
index 461ce4970..000000000
--- a/os/hal/platforms/LPC17xx/dac_lld.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx DAC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/dac_lld.c
- * @brief   LPC17xx DAC subsystem low level driver source.
- *
- * @addtogroup DAC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief CHN1 driver identifier.*/
-DACDriver DACD1;
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-static lpc17xx_dma_lli_config_t lpc_dac_lli[2] __attribute__((aligned(0x10)));
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-
-/**
- * @brief   DAC DMA interrupt function.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- * @param[in] flags     dma error flags
- */
-static void dac_serve_dma_interrupt(DACDriver *dacp, uint32_t flags) {
-
-  if ((flags & (1 << LPC17xx_DAC_DMA_CHANNEL)) != 0) {
-    _dac_isr_error_code(dacp, flags);  /* DMA errors handling.*/
-  }
-  else {
-    if (dacp->half_buffer == false) {
-      _dac_isr_half_code(dacp);
-      dacp->half_buffer = true;
-    }
-    else {
-      _dac_isr_full_code(dacp);
-      dacp->half_buffer = false;
-    }
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level DAC driver initialization.
- *
- * @notapi
- */
-void dac_lld_init(void) {
-  dacObjectInit(&DACD1);
-}
-
-/**
- * @brief   Configures and activates the DAC peripheral.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_start(DACDriver *dacp) {
-
-  if (dacp->state == DAC_STOP) {
-
-    /* Enable DAC */
-    LPC_PINCON->PINSEL1 |= (2UL << 20);   /* Set AOUT P0.26 pin.*/
-
-    LPC_DAC->CR = 0;
-    LPC_DAC->CTRL = 0;
-    LPC_DAC->CNTVAL = LPC17xx_PCLK/dacp->config->frequency;
-
-    dmaChannelAllocate(LPC17xx_DAC_DMA_CHANNEL, \
-                     (lpc17xx_dmaisr_t)dac_serve_dma_interrupt, \
-                     (void *)dacp);
-  }
-}
-
-/**
- * @brief   Deactivates the DAC peripheral.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_stop(DACDriver *dacp) {
-
-  /* If in ready state then disables the DAC clock.*/
-  if (dacp->state == DAC_READY) {
-
-    /* DMA disable.*/
-    dmaChannelDisable(LPC17xx_DAC_DMA_CHANNEL);
-    dmaChannelRelease(LPC17xx_DAC_DMA_CHANNEL);
-
-    /* Disable DAC */
-    LPC_PINCON->PINSEL1 &= ~(2UL << 20);   /* Disable AOUT P0.26 pin.*/
-  }
-}
-
-/**
- * @brief   Sends data over the DAC bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void dac_lld_start_conversion(DACDriver *dacp) {
-
-  dacp->half_buffer  = false;
-  uint32_t dma_ch_config;
-
-  /* DMA configuration */
-  lpc_dac_lli[0].srcaddr = (uint32_t) &dacp->samples[0];
-  lpc_dac_lli[0].dstaddr = (uint32_t)&LPC_DAC->CR;
-  lpc_dac_lli[0].lli = (uint32_t) &lpc_dac_lli[1];
-  lpc_dac_lli[0].control =
-    DMA_CTRL_TRANSFER_SIZE(dacp->depth/2)                   |
-    DMA_CTRL_SRC_BSIZE_1                                    |
-    DMA_CTRL_DST_BSIZE_1                                    |
-    DMA_CTRL_SRC_WIDTH_WORD                                 |
-    DMA_CTRL_DST_WIDTH_WORD                                 |
-    DMA_CTRL_SRC_INC                                        |
-    DMA_CTRL_DST_NOINC                                      |
-    DMA_CTRL_PROT1_USER                                     |
-    DMA_CTRL_PROT2_NONBUFF                                  |
-    DMA_CTRL_PROT3_NONCACHE                                 |
-    DMA_CTRL_INT;
-
-  lpc_dac_lli[1].srcaddr = (uint32_t) &dacp->samples[dacp->depth/2];
-  lpc_dac_lli[1].dstaddr = lpc_dac_lli[0].dstaddr;
-  lpc_dac_lli[1].control = lpc_dac_lli[0].control;
-
-  if (dacp->grpp->circular == true) {
-    lpc_dac_lli[1].lli = (uint32_t) &lpc_dac_lli[0];
-  }
-  else {
-    lpc_dac_lli[1].lli = 0;
-  }
-
-  dma_ch_config =
-    DMA_CFG_CH_ENABLE                |
-    DMA_CFG_DST_PERIPH(DMA_DAC)      |
-    DMA_CFG_TTYPE_M2P                |
-    DMA_CFG_IE                       |
-    DMA_CFG_ITC;
-
-  dmaChannelSrcAddr(LPC17xx_DAC_DMA_CHANNEL, lpc_dac_lli[0].srcaddr);
-  dmaChannelDstAddr(LPC17xx_DAC_DMA_CHANNEL, lpc_dac_lli[0].dstaddr);
-  dmaChannelLinkedList(LPC17xx_DAC_DMA_CHANNEL, lpc_dac_lli[0].lli);
-  dmaChannelControl(LPC17xx_DAC_DMA_CHANNEL, lpc_dac_lli[0].control);
-  dmaChannelConfig(LPC17xx_DAC_DMA_CHANNEL, dma_ch_config);
-
-  LPC_DAC->CTRL = DACCTRL_DMA_ENA | DACCTRL_CNT_ENA | DACCTRL_DBLBUF_ENA;
-}
-
-void dac_lld_stop_conversion(DACDriver *dacp) {
-
-  /* If in active state then disables the DAC.*/
-  if (dacp->state == DAC_ACTIVE) {
-
-    /* DMA disable.*/
-    dmaChannelDisable(LPC17xx_DAC_DMA_CHANNEL);
-  }
-};
-
-#endif /* HAL_USE_DAC */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/dac_lld.h b/os/hal/platforms/LPC17xx/dac_lld.h
deleted file mode 100644
index 0932d7a86..000000000
--- a/os/hal/platforms/LPC17xx/dac_lld.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx DAC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/dac_lld.h
- * @brief   LPC17xx DAC subsystem low level driver header.
- *
- * @addtogroup DAC
- * @{
- */
-
-#ifndef _DAC_LLD_H_
-#define _DAC_LLD_H_
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define DACR_BIAS                   (1UL << 16)
-
-#define DACCTRL_INT_DMA_REQ         (1UL << 0)
-#define DACCTRL_DBLBUF_ENA          (1UL << 1)
-#define DACCTRL_CNT_ENA             (1UL << 2)
-#define DACCTRL_DMA_ENA             (1UL << 3)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-
-/**
- * @brief   DMA stream used for DAC CHN1 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(LPC17xx_DAC_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define LPC17xx_DAC_DMA_CHANNEL             DMA_CHANNEL5
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !defined(LPC17xx_DMA_REQUIRED)
-#define LPC17xx_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an DAC driver.
- */
-typedef struct DACDriver DACDriver;
-
-/**
- * @brief   Type representing a DAC sample.
- */
-typedef uint32_t dacsample_t;
-
-/**
- * @brief   DAC notification callback type.
- *
- * @param[in] dacp      pointer to the @p DACDriver object triggering the
- *                      callback
- */
-typedef void (*dacendcallback_t)(DACDriver *dacp, const dacsample_t * samples, size_t pos);
-
-/**
- * @brief   DAC notification callback type.
- *
- * @param[in] dacp      pointer to the @p DACDriver object triggering the
- *                      callback
- */
-typedef void (*dacerrcallback_t)(DACDriver *dacp, uint32_t flags);
-
-/**
- * @brief   DAC Conversion group structure.
- */
-typedef struct {
-  /**
-   * @brief Number of DAC channels.
-   */
-  uint16_t              num_channels;
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  dacendcallback_t     end_cb;
-  /**
-   * @brief Error handling callback or @p NULL.
-   */
-  dacerrcallback_t      error_cb;
-  /**
-   * @brief Error handling callback or @p NULL.
-   */
-  bool      circular;
-
-} DACConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   Timer frequency in Hz.
-   */
-  uint32_t                  frequency;
-  /* End of the mandatory fields.*/
-} DACConfig;
-
-/**
- * @brief   Structure representing a DAC driver.
- */
-struct DACDriver {
-  /**
-   * @brief Driver state.
-   */
-  dacstate_t                state;
-  /**
-   * @brief Conversion group.
-   */
-  const DACConversionGroup *grpp;
-  /**
-   * @brief Samples buffer pointer.
-   */
-  const dacsample_t *samples;
-  /**
-   * @brief Samples buffer size.
-   */
-  uint16_t depth;
-  /**
-   * @brief Current configuration data.
-   */
-  const DACConfig           *config;
-#if DAC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif /* DAC_USE_WAIT */
-#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* DAC_USE_MUTUAL_EXCLUSION */
-#if defined(DAC_DRIVER_EXT_FIELDS)
-  DAC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Half buffer indicator.
-   */
-  bool_t                    half_buffer;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-extern DACDriver DACD1;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dac_lld_init(void);
-  void dac_lld_start(DACDriver *dacp);
-  void dac_lld_stop(DACDriver *dacp);
-  void dac_lld_start_conversion(DACDriver *dacp);
-  void dac_lld_stop_conversion(DACDriver *dacp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_DAC */
-
-#endif /* _DAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/gpt_lld.c b/os/hal/platforms/LPC17xx/gpt_lld.c
deleted file mode 100644
index 5402154b7..000000000
--- a/os/hal/platforms/LPC17xx/gpt_lld.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/gpt_lld.c
- * @brief   LPC17xx GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver identifier.
- * @note    The driver GPT1 allocates the complex timer TIM0 when enabled.
- */
-#if LPC17xx_GPT_USE_TIM0 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief   GPT2 driver identifier.
- * @note    The driver GPT2 allocates the timer TIM1 when enabled.
- */
-#if LPC17xx_GPT_USE_TIM1 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief   GPT3 driver identifier.
- * @note    The driver GPT3 allocates the timer TIM2 when enabled.
- */
-#if LPC17xx_GPT_USE_TIM2 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/**
- * @brief   GPT4 driver identifier.
- * @note    The driver GPT4 allocates the timer TIM3 when enabled.
- */
-#if LPC17xx_GPT_USE_TIM3 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
-  gptp->tmr->IR = 1;                        /* Clear interrupt on match MR0.*/
-  if (gptp->state == GPT_ONESHOT) {
-    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
-    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
-  }
-  gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC17xx_GPT_USE_TIM0
-/**
- * @brief   TIM0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector44) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC17xx_GPT_USE_TIM0 */
-
-#if LPC17xx_GPT_USE_TIM1
-/**
- * @brief   TIM1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector48) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC17xx_GPT_USE_TIM0 */
-
-#if LPC17xx_GPT_USE_TIM2
-/**
- * @brief   TIM2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector4C) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC17xx_GPT_USE_TIM2 */
-
-#if LPC17xx_GPT_USE_TIM3
-/**
- * @brief   TIM3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector50) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC17xx_GPT_USE_TIM3 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if LPC17xx_GPT_USE_TIM0
-  /* Driver initialization.*/
-  GPTD1.tmr = LPC_TIM0;
-  gptObjectInit(&GPTD1);
-#endif
-
-#if LPC17xx_GPT_USE_TIM1
-  /* Driver initialization.*/
-  GPTD2.tmr = LPC_TIM1;
-  gptObjectInit(&GPTD2);
-#endif
-
-#if LPC17xx_GPT_USE_TIM2
-  /* Driver initialization.*/
-  GPTD3.tmr = LPC_TIM2;
-  gptObjectInit(&GPTD3);
-#endif
-
-#if LPC17xx_GPT_USE_TIM3
-  /* Driver initialization.*/
-  GPTD4.tmr = LPC_TIM3;
-  gptObjectInit(&GPTD4);
-#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-  uint32_t pr;
-
-  if (gptp->state == GPT_STOP) {
-    /* Clock activation.*/
-#if LPC17xx_GPT_USE_TIM0
-    if (&GPTD1 == gptp) {
-      LPC_SC->PCONP |= (1UL << 1);
-      nvicEnableVector(TIMER0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC17xx_GPT_USE_TIM1
-    if (&GPTD2 == gptp) {
-      LPC_SC->PCONP |= (1UL << 2);
-      nvicEnableVector(TIMER1_IRQn, CORTEX_PRIORITY_MASK(3));
-    }
-#endif
-#if LPC17xx_GPT_USE_TIM2
-    if (&GPTD3 == gptp) {
-      LPC_SC->PCONP |= (1UL << 22);
-      nvicEnableVector(TIMER2_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC17xx_GPT_USE_TIM3
-    if (&GPTD4 == gptp) {
-      LPC_SC->PCONP |= (1UL << 23);
-      nvicEnableVector(TIMER3_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-  }
-
-  /* Prescaler value calculation.*/
-  pr = (uint16_t)((LPC17xx_PCLK/ gptp->config->frequency) - 1);
-  chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC17xx_PCLK,
-              "gpt_lld_start(), #1", "invalid frequency");
-
-  /* Timer configuration.*/
-  gptp->tmr->PR  = pr;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
-  if (gptp->state == GPT_READY) {
-    gptp->tmr->MCR = 0;
-    gptp->tmr->TCR = 0;
-
-#if LPC17xx_GPT_USE_TIM0
-    if (&GPTD1 == gptp) {
-      nvicDisableVector(TIMER0_IRQn);
-      LPC_SC->PCONP &= ~(1UL << 1);
-    }
-#endif
-#if LPC17xx_GPT_USE_TIM1
-    if (&GPTD2 == gptp) {
-      nvicDisableVector(TIMER1_IRQn);
-      LPC_SC->PCONP &= ~(1UL << 2);
-    }
-#endif
-#if LPC17xx_GPT_USE_TIM2
-    if (&GPTD3 == gptp) {
-      nvicDisableVector(TIMER2_IRQn);
-      LPC_SC->PCONP &= ~(1UL << 22);
-    }
-#endif
-#if LPC17xx_GPT_USE_TIM3
-    if (&GPTD4 == gptp) {
-      nvicDisableVector(TIMER3_IRQn);
-      LPC_SC->PCONP &= ~(1UL << 23);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 3;                       /* IRQ and clr TC on match MR0. */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR0 = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 4;                       /* Stop TC on match MR0.        */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-  while (gptp->tmr->TCR & 1)
-    ;
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/gpt_lld.h b/os/hal/platforms/LPC17xx/gpt_lld.h
deleted file mode 100644
index b4e379f80..000000000
--- a/os/hal/platforms/LPC17xx/gpt_lld.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/gpt_lld.h
- * @brief   LPC17xx GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver enable switch.
- * @details If set to @p TRUE the support for GPT1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC17xx_GPT_USE_TIM0) || defined(__DOXYGEN__)
-#define LPC17xx_GPT_USE_TIM0              TRUE
-#endif
-
-/**
- * @brief   GPT2 driver enable switch.
- * @details If set to @p TRUE the support for GPT2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC17xx_GPT_USE_TIM1) || defined(__DOXYGEN__)
-#define LPC17xx_GPT_USE_TIM1              TRUE
-#endif
-
-/**
- * @brief   GPT3 driver enable switch.
- * @details If set to @p TRUE the support for GPT3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC17xx_GPT_USE_TIM2) || defined(__DOXYGEN__)
-#define LPC17xx_GPT_USE_TIM2              TRUE
-#endif
-
-/**
- * @brief   GPT4 driver enable switch.
- * @details If set to @p TRUE the support for GPT4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC17xx_GPT_USE_TIM3) || defined(__DOXYGEN__)
-#define LPC17xx_GPT_USE_TIM3              TRUE
-#endif
-
-/**
- * @brief   GPT1 interrupt priority level setting.
- */
-#if !defined(LPC17xx_GPT_TIM0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_GPT_TIM0_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT2 interrupt priority level setting.
- */
-#if !defined(LPC17xx_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_GPT_TIM1_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT3 interrupt priority level setting.
- */
-#if !defined(LPC17xx_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_GPT_TIM2_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT4 interrupt priority level setting.
- */
-#if !defined(LPC17xx_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_GPT_TIM3_IRQ_PRIORITY     2
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !LPC17xx_GPT_USE_TIM0 && !LPC17xx_GPT_USE_TIM1 &&                   \
-    !LPC17xx_GPT_USE_TIM2 && !LPC17xx_GPT_USE_TIM3
-#error "GPT driver activated but no CT peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Timer base clock.
-   */
-  uint32_t                  clock;
-  /**
-   * @brief Pointer to the CTxxBy registers block.
-   */
-  LPC_TIM_TypeDef           *tmr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC17xx_GPT_USE_TIM0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if LPC17xx_GPT_USE_TIM1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if LPC17xx_GPT_USE_TIM2 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#if LPC17xx_GPT_USE_TIM3 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/hal_lld.c b/os/hal/platforms/LPC17xx/hal_lld.c
deleted file mode 100644
index b207a5375..000000000
--- a/os/hal/platforms/LPC17xx/hal_lld.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx HAL driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/hal_lld.c
- * @brief   LPC17xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/**
- * @brief   Register missing in NXP header file.
- */
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* SysTick initialization using the system clock.*/
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
-  SysTick->LOAD = LPC17xx_CCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-
-  /* DWT cycle counter enable.*/
-  SCS_DEMCR |= SCS_DEMCR_TRCENA;
-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
-
-#if defined(LPC17xx_DMA_REQUIRED)
-  dmaInit();
-#endif
-}
-
-/**
- * @brief   LPC17xx clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void LPC17xx_clock_init(void) {
-
-  /* Flash wait states setting, the code takes care to not touch TBD bits.*/
-  LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~(0x0000000F << 12)) | (LPC17xx_FLASHCFG_FLASHTIM << 12);
-
-  /* System oscillator initialization if required.*/
-
-#if LPC17xx_MAINOSC_ENABLE
-  LPC_SC->SCS = (1 << 5) | (LPC17xx_OSCRANGE << 4);     /* Enable Main oscillator */
-  while (!(LPC_SC->SCS & (1 << 6)))
-    ;                                                   /* Wait for main oscillator to be ready */
-#endif
-
-  /* Peripheral clock divider initialization, must be set before enabling Main PLL (PLL0).
-     Read errata sheet ES_LPC176x. */
-  LPC_SC->PCLKSEL0 = LPC17xx_PCLKSEL0;
-  LPC_SC->PCLKSEL1 = LPC17xx_PCLKSEL1;
-
-  LPC_SC->CCLKCFG = LPC17xx_CCLK_DIV - 1;               /* Set CPU clock divider */
-
-  LPC_SC->CLKSRCSEL = LPC17xx_SYSCLK_SELECT;            /* Select clock source for PLL0 if enabled or CPU */
-
-#if LPC17xx_MAINPLL_ENABLE
-
-  /* PLL0 configuration and start */
-  LPC_SC->PLL0CFG = (LPC17xx_PLL0CFG_NSEL0 << 16) | LPC17xx_PLL0CFG_MSEL0;
-  LPC_SC->PLL0FEED = 0xAA;
-  LPC_SC->PLL0FEED = 0x55;
-
-  LPC_SC->PLL0CON = 0x01;      	/* Enable PLL0. */
-  LPC_SC->PLL0FEED = 0xAA;
-  LPC_SC->PLL0FEED = 0x55;
-  while (!(LPC_SC->PLL0STAT & (1UL << 26)))
-      ;                         /* Wait for PLL0 locked */
-
-  LPC_SC->PLL0CON = 0x03;      	/* Enable and Connect PLL0. */
-  LPC_SC->PLL0FEED = 0xAA;
-  LPC_SC->PLL0FEED = 0x55;
-  while (!(LPC_SC->PLL0STAT & ((1UL << 25) | (1UL << 24))))
-        ;                       /* Wait for PLL0 connected */
-
-#endif /* LPC17xx_MAINPLL_ENABLE == TRUE */
-
-#if LPC17xx_USBPLL_ENABLE
-  /* PLL1 configuration and start */
-  LPC_SC->PLL1CFG = (LPC17xx_PLL1CFG_PSEL1 << 5) | LPC17xx_PLL1CFG_MSEL1;
-  LPC_SC->PLL1FEED = 0xAA;
-  LPC_SC->PLL1FEED = 0x55;
-
-  LPC_SC->PLL1CON = 0x01;      	/* Enable PLL1. */
-  LPC_SC->PLL1FEED = 0xAA;
-  LPC_SC->PLL1FEED = 0x55;
-  while (!(LPC_SC->PLL1STAT & (1UL << 10)))
-    ;                           /* Wait for PLL1 locked */
-
-   LPC_SC->PLL1CON = 0x03;      /* Enable and Connect PLL1. */
-   LPC_SC->PLL1FEED = 0xAA;
-   LPC_SC->PLL1FEED = 0x55;
-   while (!(LPC_SC->PLL1STAT & ((1UL << 9) | (1UL << 8))))
-     ;                          /* Wait for PLL1 connected */
-#endif /* LPC17xx_USBPLL_ENABLE == TRUE */
-
-#if !LPC17xx_USBPLL_ENABLE && HAL_USE_USB
-   LPC_SC->USBCLKCFG = LPC17xx_USBCLKPLL0_SELECT;
-#endif
-
-  /* Power control configuration */
-  LPC_SC->PCONP = (1 << 15) | (1 << 9); /* Enable power for GPIO and RTC */
-
-#if LPC17xx_CLKOUT_ENABLE
-  LPC_SC->CLKOUTCFG = (1UL << 8) | ((LPC17xx_CLKOUT_DIV - 1) << 4) | LPC17xx_CLKOUT_SELECT;
-#endif
-}
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/hal_lld.h b/os/hal/platforms/LPC17xx/hal_lld.h
deleted file mode 100644
index bfe66de91..000000000
--- a/os/hal/platforms/LPC17xx/hal_lld.h
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx HAL driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/hal_lld.h
- * @brief   HAL subsystem low level driver header template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "LPC17xx.h"
-#include "nvic.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME           "LPC17xx"
-
-#define IRCOSCCLK               4000000UL	/**< High speed internal clock. */
-
-#define CLKSRCSEL_IRCOSC        0UL      	/**< Clock source is IRC.       */
-#define CLKSRCSEL_MAINOSC       1UL         /**< Clock source is Main oscillator.   */
-#define CLKSRCSEL_RTCOSC        2UL         /**< Clock source is RTC oscillator.    */
-
-#define PCLKSEL_CCLK_DIV_4      0UL         /**< Peripheral clock source is CCLK/4  */
-#define PCLKSEL_CCLK            1UL         /**< Peripheral clock source is CCLK    */
-#define PCLKSEL_CCLK_DIV_2      2UL         /**< Peripheral clock source is CCLK/2  */
-#define PCLKSEL_CCLK_DIV_8      3UL         /**< Peripheral clock source is CCLK/8  */
-#define PCLKSEL_MASK            3UL
-
-#define CLKOUTSEL_CCLK          0UL         /**< Clock output is CPU clock.         */
-#define CLKOUTSEL_MAINOSC       1UL         /**< Clock output is Main oscillator.   */
-#define CLKOUTSEL_IRCOSC        2UL         /**< Clock output is IRC oscillator.    */
-#define CLKOUTSEL_USBCLK        3UL         /**< Clock output is USB clock.         */
-#define CLKOUTSEL_RTCOSC        4UL         /**< Clock output is RTC oscillator.    */
-
-#define PCLKSEL_CCLK_DIV_4      0UL         /**< Peripheral clock output is CCLK/4  */
-#define PCLKSEL_CCLK            1UL         /**< Peripheral clock output is CCLK    */
-#define PCLKSEL_CCLK_DIV_2      2UL         /**< Peripheral clock output is CCLK/2  */
-#define PCLKSEL_CCLK_DIV_8      3UL         /**< Peripheral clock output is CCLK/8  */
-
-#define USBSEL_PLL0_DIV_6       5UL         /**< USB clock source is PLL0/6.        */
-#define USBSEL_PLL0_DIV_7       7UL         /**< USB clock source is PLL0/7.        */
-#define USBSEL_PLL0_DIV_9       9UL         /**< USB clock source is PLL0/9.        */
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Main oscillator enable.
- */
-#if !defined(LPC17xx_MAINOSC_ENABLE) || defined(__DOXYGEN__)
-#define LPC17xx_MAINOSC_ENABLE              TRUE
-#endif
-
-/**
- * @brief   System PLL clock source select.
- */
-#if !defined(LPC17xx_SYSCLK_SELECT) || defined(__DOXYGEN__)
-#define LPC17xx_SYSCLK_SELECT               CLKSRCSEL_MAINOSC
-#endif
-
-/**
- * @brief   Main PLL enable.
- */
-#if !defined(LPC17xx_MAINPLL_ENABLE) || defined(__DOXYGEN__)
-#define LPC17xx_MAINPLL_ENABLE              TRUE
-#endif
-
-/**
- * @brief   Main PLL multiplier.
- * @note    Final frequency must not exceed the CCO ratings.
- */
-#if !defined(LPC17xx_MAINPLL_MUL) || defined(__DOXYGEN__)
-#define LPC17xx_MAINPLL_MUL                 200
-#endif
-
-/**
- * @brief   Main PLL pre-divider.
- * @note    The value must be in the 1..32 range and the final frequency
- *          must not exceed the CCO ratings.
- */
-#if !defined(LPC17xx_MAINPLL_PREDIV) || defined(__DOXYGEN__)
-#define LPC17xx_MAINPLL_PREDIV              6
-#endif
-
-/**
- * @brief   USB PLL enable.
- */
-#if !defined(LPC17xx_USBPLL_ENABLE) || defined(__DOXYGEN__)
-#define LPC17xx_USBPLL_ENABLE               FALSE
-#endif
-
-/**
- * @brief   USB PLL multiplier.
- * @note    The value must be in the 1..32 range and the final frequency
- *          must not exceed the CCO ratings and USB clock must be equal 48MHz.
- */
-#if !defined(LPC17xx_USBPLL_MUL) || defined(__DOXYGEN__)
-#define LPC17xx_USBPLL_MUL                  4
-#endif
-
-/**
- * @brief   USB PLL divider.
- * @note    The value must be 2, 4, 8 or 16 and the final frequency
- *          must not exceed the CCO ratings and USB clock must be equal 48MHz.
- */
-#if !defined(LPC17xx_USBPLL_DIV) || defined(__DOXYGEN__)
-#define LPC17xx_USBPLL_DIV                  4
-#endif
-
-/**
- * @brief   CPU clock divider.
- * @note    The value must be chosen between (1...255).
- */
-#if !defined(LPC17xx_CCLK_DIV) || defined(__DOXYGEN__)
-#define LPC17xx_CCLK_DIV                    4
-#endif
-
-/**
- * @brief   PCLK clock select.
- */
-#if !defined(LPC17xx_PCLK_SELECT) || defined(__DOXYGEN__)
-#define LPC17xx_PCLK_SELECT                 PCLKSEL_CCLK
-#endif
-
-/**
- * @brief   Clock output enable.
- * @note
- */
-#if !defined(LPC17xx_CLKOUT_ENABLE) || defined(__DOXYGEN__)
-#define LPC17xx_CLKOUT_ENABLE               FALSE
-#endif
-
-/**
- * @brief   Clock output divider.
- * @note    The value must be chosen between (1...16).
- */
-#if !defined(LPC17xx_CLKOUT_DIV) || defined(__DOXYGEN__)
-#define LPC17xx_CLKOUT_DIV                  4
-#endif
-
-/**
- * @brief   Clock output clock source select.
- */
-#if !defined(LPC17xx_CLKOUT_SELECT) || defined(__DOXYGEN__)
-#define LPC17xx_CLKOUT_SELECT               CLKOUTSEL_MAINOSC
-#endif
-
-/**
- * @brief   USB clock PPL0 clock source select.
- * @note    PLL0 output must be 288MHz (USBSEL_PLL0_DIV_6), 384MHz (USBSEL_PLL0_DIV_8) or
- * 			480MHz(USBSEL_PLL0_DIV_10). Only is used when USB PLL (PLL1) disable.
- */
-#if !defined(LPC17xx_USBCLKPLL0_SELECT) || defined(__DOXYGEN__)
-#define LPC17xx_USBCLKPLL0_SELECT           USBSEL_PLL0_DIV_6
-#endif
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Calculated OSCRANGE setting.
- */
-#if (MAINOSCCLK < 18000000) || defined(__DOXYGEN__)
-#define LPC17xx_OSCRANGE        0
-#else
-#define LPC17xx_OSCRANGE        1
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (LPC17xx_SYSCLK_SELECT == CLKSRCSEL_IRCOSC) || defined(__DOXYGEN__)
-#define LPC17xx_SYSCLK          IRCOSCCLK
-#elif LPC17xx_SYSCLK_SELECT == CLKSRCSEL_MAINOSC
-#define LPC17xx_SYSCLK          MAINOSCCLK
-#elif LPC17xx_SYSCLK_SELECT == CLKSRCSEL_RTCOSC
-#define LPC17xx_SYSCLK          RTCOSCCLK
-#else
-#error "Invalid LPC17xx_SYSCLK_SELECT clock source specified."
-#endif
-
-/**
- * @brief   MSEL mask in SYSPLLCTRL register.
- */
-#if ((LPC17xx_MAINPLL_MUL % 2) == 0) || defined(__DOXYGEN__)
-#define LPC17xx_PLL0CFG_MSEL0 ((LPC17xx_MAINPLL_MUL/2) - 1)
-#else
-#error "Invalid LPC17xx_PLL0CFG_MUL value."
-#endif
-
-/**
- * @brief   PSEL mask in SYSPLLCTRL register.
- */
-#if ((LPC17xx_MAINPLL_PREDIV >= 1) && (LPC17xx_MAINPLL_PREDIV <= 32)) || defined(__DOXYGEN__)
-#define LPC17xx_PLL0CFG_NSEL0 (LPC17xx_MAINPLL_PREDIV - 1)
-#else
-#error "Invalid LPC17xx_MAINPLL_PREDIV value (1 to 32 accepted)."
-#endif
-
-/**
- * @brief   CCO frequency.
- */
-#define  LPC17xx_MAINPLLCCO   ((LPC17xx_MAINPLL_MUL *    \
-                              LPC17xx_SYSCLK)/LPC17xx_MAINPLL_PREDIV)
-
-#if (LPC17xx_MAINPLLCCO < 275000000) || (LPC17xx_SYSPLLCCO > 550000000)
-#error "CCO frequency out of the acceptable range (275...550)."
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#if LPC17xx_MAINPLL_ENABLE
-#define  LPC17xx_MAINPLLCLK   LPC17xx_MAINPLLCCO
-#else
-#define  LPC17xx_MAINPLLCLK   LPC17xx_SYSCLK
-#endif
-
-/**
- * @brief   CPU clock frequency.
- * @note 	Most of LPC17xx have max 120 MHz clock.
- */
-#define LPC17xx_CCLK     (LPC17xx_MAINPLLCLK/LPC17xx_CCLK_DIV)
-#if (LPC17xx_CCLK > 120000000) || defined(__DOXYGEN__)
-#error "CPU Clock out of range."
-#endif
-
-#if LPC17xx_USBPLL_ENABLE
-/**
- * @brief   Main oscillator out of range.
- */
-#if ((MAINOSCCLK < 10000000) && (MAINOSCCLK > 25000000)) || defined(__DOXYGEN__)
-#error "Main oscillator clock out of range."
-#endif
-
-/**
- * @brief   MSEL1 mask in PLL1CFG register.
- */
-#if (LPC17xx_USBPLL_MUL >= 1) && (LPC17xx_USBPLL_MUL <= 32) || defined(__DOXYGEN__)
-#define LPC17xx_PLL1CFG_MSEL1 (LPC17xx_USBPLL_MUL - 1)
-#else
-#error "Invalid LPC17xx_USBPLL_MUL value (1 to 32 accepted)."
-#endif
-
-/**
- * @brief   PSEL1 mask in PLL1CFG register.
- */
-#if (LPC17xx_USBPLL_DIV == 2) || defined(__DOXYGEN__)
-#define LPC17xx_PLL1CFG_PSEL1 		0UL
-#elif (LPC17xx_USBPLL_DIV == 4)
-#define LPC17xx_PLL1CFG_PSEL1 		1UL
-#elif (LPC17xx_USBPLL_DIV == 8)
-#define LPC17xx_PLL1CFG_PSEL1 		2UL
-#elif (LPC17xx_USBPLL_DIV == 16)
-#define LPC17xx_PLL1CFG_PSEL1 		3UL
-#else
-#error "Invalid LPC17xx_USBPLL_DIV value (2, 4, 8, 16 accepted)."
-#endif
-
-/**
- * @brief   USB PLL CCO frequency.
- */
-#define  LPC17xx_USBPLLCCO   (MAINOSCCLK * LPC17xx_USBPLL_MUL * \
-								LPC17xx_USBPLL_DIV)
-
-#if (LPC17xx_USBPLLCCO < 156000000) || (LPC17xx_SYSPLLCCO > 320000000)
-#error "CCO frequency out of the acceptable range (156...320)"
-#endif
-
-/**
- * @brief   USB clock frequency.
- * @note 	Must be 48 MHz.
- */
-#define LPC17xx_USBCLK     (LPC17xx_USBPLLCCO/LPC17xx_USBPLL_DIV)
-#if (LPC17xx_USBCLK != 48000000) || defined(__DOXYGEN__)
-#error "USB clock out of range."
-#endif
-#endif
-
-/**
- * @brief   Peripheral clock frequency.
- */
-#if (LPC17xx_PCLK_SELECT == PCLKSEL_CCLK_DIV_4) || defined(__DOXYGEN__)
-#define LPC17xx_PCLK            (LPC17xx_CCLK/4)
-#define LPC17xx_PCLKSEL0        0x00
-#define LPC17xx_PCLKSEL1        0x00
-#elif (LPC17xx_PCLK_SELECT == PCLKSEL_CCLK)
-#define LPC17xx_PCLK            (LPC17xx_CCLK)
-#define LPC17xx_PCLKSEL0        0x55515155
-#define LPC17xx_PCLKSEL1        0x54555455
-#elif (LPC17xx_PCLK_SELECT == PCLKSEL_CCLK_DIV_2)
-#define LPC17xx_PCLK            (LPC17xx_CCLK/2)
-#define LPC17xx_PCLKSEL0        0xAAA2A2AA
-#define LPC17xx_PCLKSEL1        0xA8AAA8AA
-#elif (LPC17xx_PCLK_SELECT == PCLKSEL_CCLK_DIV_8)
-#define LPC17xx_PCLK            (LPC17xx_CCLK/8)
-#define LPC17xx_PCLKSEL0        0xFFF3F3FF
-#define LPC17xx_PCLKSEL1        0xFCFFFCFF
-#else
-#error "Invalid LPC17xx_PCLK_SELECT value"
-#endif
-
-/**
- * @brief   LPC17xx_CLKOUT_DIV out of range.
- */
-#if ((LPC17xx_CLKOUT_DIV < 1) && (LPC17xx_CLKOUT_DIV > 16)) || defined(__DOXYGEN__)
-#error "Invalid LPC17xx_CLKOUT_DIV value (1 to 16 accepted)."
-#endif
-
-/**
- * @brief   CLKOUT frequency.
- */
-#if (LPC17xx_CLKOUT_SELECT == CLKOUTSEL_CCLK) || defined(__DOXYGEN__)
-#define LPC17xx_CLKOUTCLK (LPC17xx_CCLK/LPC17xx_CLKOUT_DIV)
-#elif (LPC17xx_CLKOUT_SELECT == CLKOUTSEL_MAINOSC)
-#define LPC17xx_CLKOUTCLK (MAINOSCCLK/LPC17xx_CLKOUT_DIV)
-#elif (LPC17xx_CLKOUT_SELECT == CLKOUTSEL_IRCOSC)
-#define LPC17xx_CLKOUTCLK (IRCOSCCLK/LPC17xx_CLKOUT_DIV)
-#elif (LPC17xx_CLKOUT_SELECT == CLKOUTSEL_USBCLK)
-#define LPC17xx_CLKOUTCLK (LPC17xx_USBCLK/LPC17xx_CLKOUT_DIV)
-#elif (LPC17xx_CLKOUT_SELECT == CLKOUTSEL_RTCOSC)
-#define LPC17xx_CLKOUTCLK (RTCOSCCLK/LPC17xx_CLKOUT_DIV)
-#else
-#error "Invalid LPC17xx_CLKOUT_SELECT value."
-#endif
-
-/**
- * @brief   CLKOUT frequency out of range.
- */
-#if (LPC17xx_CLKOUTCLK > 50000000) || defined(__DOXYGEN__)
-#error "CLKOUT frequency out of the acceptable range (less than 50 MHz)"
-#endif
-
-/**
- * @brief   Flash wait states.
- */
-#if (LPC17xx_CCLK <= 20000000) || defined(__DOXYGEN__)
-#define LPC17xx_FLASHCFG_FLASHTIM   0UL
-#elif LPC17xx_CCLK <= 40000000
-#define LPC17xx_FLASHCFG_FLASHTIM   1UL
-#elif LPC17xx_CCLK <= 60000000
-#define LPC17xx_FLASHCFG_FLASHTIM   2UL
-#elif LPC17xx_CCLK <= 80000000
-#define LPC17xx_FLASHCFG_FLASHTIM   3UL
-#elif LPC17xx_CCLK <= 120000000
-#define LPC17xx_FLASHCFG_FLASHTIM   4UL
-#else
-#define LPC17xx_FLASHCFG_FLASHTIM   5UL
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This service is implemented by returning the content of the
- *          DWT_CYCCNT register.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value()         DWT_CYCCNT
-
-/**
- * @brief   Realtime counter frequency.
- * @note    The DWT_CYCCNT register is incremented directly by the cpu
- *          clock so this function returns LPC17xx_CCLK.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency()     LPC17xx_CCLK
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#include "lpc17xx_dma.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void LPC17xx_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/i2c_lld.c b/os/hal/platforms/LPC17xx/i2c_lld.c
deleted file mode 100644
index 74987956d..000000000
--- a/os/hal/platforms/LPC17xx/i2c_lld.c
+++ /dev/null
@@ -1,533 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx I2C driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-
-/**
- * @file    LPC17xx/i2c_lld.h
- * @brief   LPC17xx I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC17xx_I2C_USE_I2C0 || defined(__DOXYGEN__)
-/** @brief I2C1 driver identifier.*/
-I2CDriver I2CD1;
-#endif
-
-#if LPC17xx_I2C_USE_I2C1 || defined(__DOXYGEN__)
-/** @brief I2C2 driver identifier.*/
-I2CDriver I2CD2;
-#endif
-
-#if LPC17xx_I2C_USE_I2C2 || defined(__DOXYGEN__)
-/** @brief I2C3 driver identifier.*/
-I2CDriver I2CD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Wakes up the waiting thread.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] msg       wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((i2cp)->thread != NULL) {                                             \
-    Thread *tp = (i2cp)->thread;                                            \
-    (i2cp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = (msg);                                                 \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
-}
-
-/**
- * @brief   Handling of stalled I2C transactions.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_safety_timeout(void *p) {
-  I2CDriver *i2cp = (I2CDriver *)p;
-
-  chSysLockFromIsr();
-  if (i2cp->thread) {
-    Thread *tp = i2cp->thread;
-    i2cp->thread = NULL;
-    tp->p_u.rdymsg = RDY_TIMEOUT;
-    chSchReadyI(tp);
-  }
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   I2C error handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t status) {
-  i2cflags_t error = 0;
-
-  switch (status) {
-    case I2C_STATE_ARB_LOST:
-      error = I2CD_ARBITRATION_LOST;
-      break;
-    case I2C_STATE_BUS_ERROR:
-      error = I2CD_BUS_ERROR;
-      break;
-    case I2C_STATE_MS_SLAR_NACK:
-    case I2C_STATE_MS_TDAT_NACK:
-    case I2C_STATE_MS_SLAW_NACK:
-      error = I2CD_ACK_FAILURE ;
-      break;
-  }
-
-  /* If some error has been identified then sends wakes the waiting thread.*/
-  i2cp->errors = error;
-  wakeup_isr(i2cp, RDY_RESET);
-}
-
-/**
- * @brief   I2C serve interrupt handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_interrupt(I2CDriver *i2cp) {
-  uint32_t status;
-  LPC_I2C_TypeDef *dp = i2cp->i2c;
-
-  status = dp->STAT;
-  switch(status) {
-    case I2C_STATE_MS_START:    /*  A START condition has been transmitted. */
-      if (i2cp->txbytes > 0) {
-        dp->DAT = i2cp->addr;                  /* Write slave address with WR bit. */
-      }
-      else {
-        dp->DAT = i2cp->addr | I2C_RD_BIT;     /* Write slave address with RD bit. */
-      }
-
-      dp->CONCLR = I2C_CONCLR_STAC | I2C_CONCLR_SIC;   /* Clear START and SI bit. */
-      break;
-
-    case I2C_STATE_MS_SLAR_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */
-    case I2C_STATE_MS_TDAT_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */
-    case I2C_STATE_MS_SLAW_NACK: /* NOT ACK has been received, Master will be transmitted STOP. */
-      dp->CONSET = I2C_CONSET_STO;             /* Set STOP bit. */
-      dp->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      i2c_lld_serve_error_interrupt(i2cp, status);
-      break;
-
-    case I2C_STATE_MS_SLAW_ACK: /* SLA + W has been transmitted, ACK has been received. */
-    case I2C_STATE_MS_TDAT_ACK: /* Data byte has been transmitted, ACK has been received. */
-      if (i2cp->txbytes > 0) {
-        dp->DAT = *i2cp->txbuf++;               /* Write data. */
-        i2cp->txbytes--;
-      }
-      else {
-        if (i2cp->rxbytes > 0) {
-          dp->CONSET = I2C_CONSET_STO | I2C_CONSET_STA; /* Set START and STOP bit. */
-        }                                                    /* STOP bit will be transmit, then START bit. */
-        else {
-          dp->CONSET = I2C_CONSET_STO;         /* Set STOP bit. */
-          wakeup_isr(i2cp, RDY_OK);
-        }
-      }
-      dp->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      break;
-
-    case I2C_STATE_MS_SLAR_ACK: /* SLA + R has been transmitted, ACK has been received. */
-    case I2C_STATE_MS_RDAT_ACK: /* Data byte has been received, ACK has been returned. */
-      if (status == I2C_STATE_MS_RDAT_ACK) {
-        *i2cp->rxbuf++ = dp->DAT;                /* Read data */
-        i2cp->rxbytes--;
-      }
-      if (i2cp->rxbytes == 1) {
-        dp->CONCLR = I2C_CONCLR_SIC | I2C_CONCLR_AAC; /* Clear SI and ACK bit. */
-      }
-      else {
-        dp->CONSET = I2C_CONSET_AA;            /* Set ACK bit. */
-        dp->CONCLR = I2C_CONCLR_SIC;           /* Clear SI bit. */
-      }
-      break;
-
-    case I2C_STATE_MS_RDAT_NACK: /* Data byte has been received, NOT ACK has been returned. */
-      *i2cp->rxbuf++ = dp->DAT;                /* Read data. */
-      i2cp->rxbytes--;
-      dp->CONSET = I2C_CONSET_STO;             /* Set STOP bit. */
-      dp->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      wakeup_isr(i2cp, RDY_OK);
-      break;
-
-    case I2C_STATE_BUS_ERROR: /* Bus error. */
-    case I2C_STATE_ARB_LOST:  /* Arbitration lost. */
-      dp->CONCLR = I2C_CONCLR_SIC;             /* Clear SI bit. */
-      i2c_lld_serve_error_interrupt(i2cp, status);
-      break;
-  }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-#if LPC17xx_I2C_USE_I2C0 || defined(__DOXYGEN__)
-/**
- * @brief   I2C0 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(Vector68) {
-
-  CH_IRQ_PROLOGUE();
-  i2c_lld_serve_interrupt(&I2CD1);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC17xx_I2C_USE_I2C1 || defined(__DOXYGEN__)
-/**
- * @brief   I2C1 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(Vector6C) {
-
-  CH_IRQ_PROLOGUE();
-  i2c_lld_serve_interrupt(&I2CD2);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC17xx_I2C_USE_I2C2 || defined(__DOXYGEN__)
-/**
- * @brief   I2C2 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(Vector70) {
-
-  CH_IRQ_PROLOGUE();
-  i2c_lld_serve_interrupt(&I2CD3);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-#if LPC17xx_I2C_USE_I2C0
-  i2cObjectInit(&I2CD1);
-  I2CD1.thread = NULL;
-  I2CD1.i2c    = LPC_I2C0;
-#endif
-
-#if LPC17xx_I2C_USE_I2C1
-  i2cObjectInit(&I2CD2);
-  I2CD2.thread = NULL;
-  I2CD2.i2c    = LPC_I2C1;
-#endif
-
-#if LPC17xx_I2C_USE_I2C2
-  i2cObjectInit(&I2CD3);
-  I2CD3.thread = NULL;
-  I2CD3.i2c    = LPC_I2C2;
-#endif
-}
-
-/**
- * @brief   Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-
-  uint32_t i2cscl;
-  uint32_t mulh, mull, div;
-  LPC_I2C_TypeDef *dp = i2cp->i2c;
-
-  /* If in stopped state then enables the I2C clock. */
-  if (i2cp->state == I2C_STOP) {
-#if LPC17xx_I2C_USE_I2C0
-    if (&I2CD1 == i2cp) {
-      LPC_SC->PCONP |= (1UL << 7);
-      nvicEnableVector(I2C0_IRQn,
-            CORTEX_PRIORITY_MASK(LPC17xx_I2C_I2C0_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC17xx_I2C_USE_I2C1
-    if (&I2CD2 == i2cp) {
-      LPC_SC->PCONP |= (1UL << 19);
-      nvicEnableVector(I2C1_IRQn,
-            CORTEX_PRIORITY_MASK(LPC17xx_I2C_I2C1_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC17xx_I2C_USE_I2C2
-    if (&I2CD3 == i2cp) {
-      LPC_SC->PCONP |= (1UL << 26);
-      nvicEnableVector(I2C2_IRQn,
-            CORTEX_PRIORITY_MASK(LPC17xx_I2C_I2C2_IRQ_PRIORITY));
-    }
-#endif
-  }
-
-  /* Make sure I2C peripheral is disabled */
-  dp->CONCLR = I2C_CONCLR_ENC;
-
-  /* Setup I2C clock parameters.*/
-  i2cscl = (LPC17xx_PCLK/(i2cp->config->clock_timing));
-  if (i2cp->config->mode == I2C_FAST_MODE) {
-    div = 19;
-    mull = 13;
-    mulh = 6;
-  } else if (i2cp->config->mode == I2C_FAST_MODE_PLUS) {
-    div = 3;
-    mull = 2;
-    mulh = 1;
-  } else { /* i2cp->config->mode == I2C_STANDARD_MODE */
-    div = 2;
-    mull = 1;
-    mulh = 1;
-  }
-
-  dp->SCLH = (mulh * i2cscl) / div;
-  dp->SCLL = (mull * i2cscl) / div;
-
-  /* Enable I2C.*/
-  dp->CONSET |= I2C_CONSET_EN;
-
-}
-
-/**
- * @brief   Deactivates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
-  /* If not in stopped state then disables the I2C clock.*/
-  if (i2cp->state != I2C_STOP) {
-
-    /* I2C disable.*/
-    i2cp->i2c->CONCLR = I2C_CONCLR_ENC;
-#if LPC17xx_I2C_USE_I2C0
- if (&I2CD1 == i2cp) {
-   nvicDisableVector(I2C0_IRQn);
-   LPC_SC->PCONP &= ~(1UL << 7);
- }
-#endif
-
-#if LPC17xx_I2C_USE_I2C1
- if (&I2CD2 == i2cp) {
-   nvicDisableVector(I2C1_IRQn);
-   LPC_SC->PCONP &= ~(1UL << 19);
- }
-#endif
-
-#if LPC17xx_I2C_USE_I2C2
- if (&I2CD3 == i2cp) {
-   nvicDisableVector(I2C2_IRQn);
-   LPC_SC->PCONP &= ~(1UL << 26);
- }
-#endif
-  }
-}
-
-/**
- * @brief   Receives data via the I2C bus as master.
- * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
- *          hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                     uint8_t *rxbuf, size_t rxbytes,
-                                     systime_t timeout) {
-  LPC_I2C_TypeDef *dp = i2cp->i2c;
-  VirtualTimer vt;
-
-  i2cp->addr = addr << 1;
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Initializes driver fields */
-  i2cp->errors = 0;
-  i2cp->rxbuf = rxbuf;
-  i2cp->rxbytes = rxbytes;
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Starts the operation.*/
-  dp->CONSET = I2C_CONSET_STA;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief   Transmits data via the I2C bus as master.
- * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
- *          This is hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[in] txbuf     pointer to the transmit buffer
- * @param[in] txbytes   number of bytes to be transmitted
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                      const uint8_t *txbuf, size_t txbytes,
-                                      uint8_t *rxbuf, size_t rxbytes,
-                                      systime_t timeout) {
-  LPC_I2C_TypeDef *dp = i2cp->i2c;
-  VirtualTimer vt;
-
-  i2cp->addr = addr << 1;
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Initializes driver fields */
-  i2cp->errors = 0;
-  i2cp->txbuf = txbuf;
-  i2cp->txbytes = txbytes;
-  i2cp->rxbuf = rxbuf;
-  i2cp->rxbytes = rxbytes;
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Starts the operation.*/
-  dp->CONSET = I2C_CONSET_STA;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/i2c_lld.h b/os/hal/platforms/LPC17xx/i2c_lld.h
deleted file mode 100644
index b02501971..000000000
--- a/os/hal/platforms/LPC17xx/i2c_lld.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx I2C driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    LPC17xx/i2c_lld.h
- * @brief   LPC17xx I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define I2C_CONSET_AA               0x04  /* Assert acknowledge flag. */
-#define I2C_CONSET_SI               0x08  /* I2C interrupt flag. */
-#define I2C_CONSET_STO              0x10  /* STOP flag. */
-#define I2C_CONSET_STA              0x20  /* START flag. */
-#define I2C_CONSET_EN               0x40  /* I2C interface enable. */
-
-#define I2C_CONCLR_AAC              0x04  /* Assert acknowledge Clear bit. */
-#define I2C_CONCLR_SIC              0x08  /* I2C interrupt Clear bit. */
-#define I2C_CONCLR_STAC             0x20  /* START flag Clear bit. */
-#define I2C_CONCLR_ENC              0x40  /* I2C interface Disable bit. */
-
-#define I2C_WR_BIT                  0x00
-#define I2C_RD_BIT                  0x01
-
-#define I2C_STATE_MS_START          0x08
-#define I2C_STATE_MS_RSTART         0x10
-#define I2C_STATE_MS_SLAW_ACK       0x18
-#define I2C_STATE_MS_SLAW_NACK      0x20
-#define I2C_STATE_MS_TDAT_ACK       0x28
-#define I2C_STATE_MS_TDAT_NACK      0x30
-#define I2C_STATE_ARB_LOST          0x38
-
-#define I2C_STATE_MS_SLAR_ACK       0x40
-#define I2C_STATE_MS_SLAR_NACK      0x48
-#define I2C_STATE_MS_RDAT_ACK       0x50
-#define I2C_STATE_MS_RDAT_NACK      0x58
-
-#define I2C_STATE_BUS_ERROR         0x00
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   I2C0 driver enable switch.
- * @details If set to @p TRUE the support for device I2C0 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC17xx_I2C_USE_I2C0) || defined(__DOXYGEN__)
-#define LPC17xx_I2C_USE_I2C0                FALSE
-#endif
-
-/**
- * @brief   I2C0 interrupt priority level setting.
- */
-#if !defined(LPC17xx_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_I2C_I2C0_IRQ_PRIORITY       3
-#endif
-
-/**
- * @brief   I2C1 driver enable switch.
- * @details If set to @p TRUE the support for device I2C0 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC17xx_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define LPC17xx_I2C_USE_I2C1                FALSE
-#endif
-
-/**
- * @brief   I2C1 interrupt priority level setting.
- */
-#if !defined(LPC17xx_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_I2C_I2C1_IRQ_PRIORITY       3
-#endif
-
-/**
- * @brief   I2C2 driver enable switch.
- * @details If set to @p TRUE the support for device I2C0 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC17xx_I2C_USE_I2C2) || defined(__DOXYGEN__)
-#define LPC17xx_I2C_USE_I2C2                FALSE
-#endif
-
-/**
- * @brief   I2C0 interrupt priority level setting.
- */
-#if !defined(LPC17xx_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_I2C_I2C2_IRQ_PRIORITY       3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing I2C address.
- */
-typedef uint16_t i2caddr_t;
-
-/**
- * @brief   I2C Driver condition flags type.
- */
-typedef uint32_t i2cflags_t;
-/**
- * @brief   Supported modes for the I2C bus.
- */
-typedef enum {
-  I2C_STANDARD_MODE = 1,
-  I2C_FAST_MODE = 2,
-  I2C_FAST_MODE_PLUS = 3,
-} i2cmode_t;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
-  i2cmode_t       mode;             /**< @brief Specifies the I2C mode.        */
-  uint32_t        clock_timing;     /**< @brief Specifies the clock timing     */
-} I2CConfig;
-
-/**
- * @brief   Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver {
-  /**
-   * @brief   Driver state.
-   */
-  i2cstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const I2CConfig           *config;
-  /**
-   * @brief   Error flags.
-   */
-  i2cflags_t                errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
-  I2C_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Thread waiting for I/O completion.
-   */
-  Thread                    *thread;
-  /**
-   * @brief     Current slave address without R/W bit.
-   */
-  i2caddr_t                 addr;
-  /**
-   * @brief     Pointer to the transmit buffer.
-   */
-  const uint8_t             *txbuf;
-  /**
-    * @brief    Number of bytes to transmit.
-    */
-  size_t                    txbytes;
-  /**
-    * @brief     Pointer to the receive buffer.
-    */
-  uint8_t                   *rxbuf;
-  /**
-      * @brief    Number of bytes to receive.
-      */
-  size_t                    rxbytes;
-  /**
-   * @brief     Pointer to the I2C registers block.
-   */
-  LPC_I2C_TypeDef           *i2c;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Get errors from I2C driver.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC17xx_I2C_USE_I2C0 && !defined(__DOXYGEN__)
-extern I2CDriver I2CD1;
-#endif
-
-#if LPC17xx_I2C_USE_I2C1 && !defined(__DOXYGEN__)
-extern I2CDriver I2CD2;
-#endif
-
-#if LPC17xx_I2C_USE_I2C2 && !defined(__DOXYGEN__)
-extern I2CDriver I2CD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void i2c_lld_init(void);
-  void i2c_lld_start(I2CDriver *i2cp);
-  void i2c_lld_stop(I2CDriver *i2cp);
-  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                        const uint8_t *txbuf, size_t txbytes,
-                                        uint8_t *rxbuf, size_t rxbytes,
-                                        systime_t timeout);
-  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                       uint8_t *rxbuf, size_t rxbytes,
-                                       systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-#endif
-#endif /* _I2C_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/lpc17xx_dma.c b/os/hal/platforms/LPC17xx/lpc17xx_dma.c
deleted file mode 100644
index 8a607ddc0..000000000
--- a/os/hal/platforms/LPC17xx/lpc17xx_dma.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx DMA driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/LPC17xx_dma.c
- * @brief   DMA driver code.
- *
- * @addtogroup LPC17xx_DMA
- * @details DMA sharing helper driver. In the LPC17xx the DMA streams are a
- *          shared resource, this driver allows to allocate and free DMA
- *          streams at runtime in order to allow all the other device
- *          drivers to coordinate the access to the resource.
- * @note    The DMA ISR handlers are all declared into this module because
- *          sharing, the various device drivers can associate a callback to
- *          ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
-   has been enabled.*/
-#if defined(LPC17xx_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-  LPC_GPDMACH_TypeDef * \
-  _lpc17xx_dma_channel_config_t[LPC17xx_DMA_CHANNELS] = {
-  LPC_GPDMACH0, LPC_GPDMACH1, LPC_GPDMACH2, LPC_GPDMACH3, LPC_GPDMACH4,
-  LPC_GPDMACH5, LPC_GPDMACH6, LPC_GPDMACH7 };
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   DMA ISR redirector type.
- */
-typedef struct {
-  lpc17xx_dmaisr_t  dma_func;       /**< @brief DMA callback function.  */
-  void              *dma_param;     /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief   Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief   DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[LPC17xx_DMA_CHANNELS];
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorA8) {
-  uint32_t irq_status;
-  uint32_t err_status;
-  uint8_t i;
-
-  CH_IRQ_PROLOGUE();
-
-  irq_status = LPC_GPDMA->IntTCStat;
-  LPC_GPDMA->IntTCClear = irq_status;  /* Clear DMA interrupt flag */
-  err_status = LPC_GPDMA->IntErrStat;
-  LPC_GPDMA->IntErrClr = err_status;   /* Clear DMA error flag if any*/
-
-  for (i = 0; i < LPC17xx_DMA_CHANNELS; i++) {
-    if (irq_status & (1UL << i)) {
-      if (dma_isr_redir[i].dma_func)
-        dma_isr_redir[i].dma_func(dma_isr_redir[i].dma_param, err_status);
-    }
-  }
-
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   LPC17xx DMA initialization.
- *
- * @init
- */
-void dmaInit(void) {
-  uint8_t i;
-
-  LPC_SC->PCONP |= (1UL << 29);                   /* Enable DMA power */
-
-                                                  /* Disable all channels */
-  for (i = 0; i < LPC17xx_DMA_CHANNELS; i++)
-    _lpc17xx_dma_channel_config_t[i]->CConfig = 0;
-
-  LPC_GPDMA->IntTCClear = 0xFF;
-  LPC_GPDMA->IntErrClr = 0xFF;
-
-  LPC_GPDMA->Config = DMACCONFIG_E;               /* Enable DMA Controller */
-  while((LPC_GPDMA->Config & DMACCONFIG_E) != 0x01)
-    ;
-
-  nvicEnableVector(DMA_IRQn, CORTEX_PRIORITY_MASK(LPC17xx_DMA_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Allocates a DMA channel.
- * @details The channel is allocated.
- * @pre     The channel must not be already in use or an error is returned.
- * @post    The channel is allocated and the default ISR handler redirected
- *          to the specified function.
- * @post    The channel must be freed using @p dmaChannelRelease() before it can
- *          be reused with another peripheral.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmach     DMA channel number
- * @param[in] func      handling function pointer, can be @p NULL
- * @param[in] param     a parameter to be passed to the handling function
- * @return              The operation status.
- * @retval FALSE        no error, stream taken.
- * @retval TRUE         error, stream already taken.
- *
- * @special
- */
-bool_t dmaChannelAllocate(lpc17xx_dma_channel_t dmach,
-                         lpc17xx_dmaisr_t func,
-                         void *param) {
-  uint32_t channel;
-  channel = (1UL << dmach);
-
-  /* Checks if the channel is already taken.*/
-  if ((dma_streams_mask & channel) != 0)
-    return TRUE;
-
-  /* Marks the stream as allocated.*/
-  dma_isr_redir[dmach].dma_func  = func;
-  dma_isr_redir[dmach].dma_param = param;
-  dma_streams_mask |= channel;
-
-  return FALSE;
-}
-
-/**
- * @brief   Releases a DMA channel.
- * @details The channel is freed.
- *          Trying to release a unallocated channel is an illegal operation
- *          and is trapped if assertions are enabled.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    The channel is again available.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmach     DMA channel number
- *
- * @special
- */
-void dmaChannelRelease(lpc17xx_dma_channel_t dmach) {
-
-  uint32_t channel;
-  channel = (1UL << dmach);
-
-  /* Check if the streams is not taken.*/
-  chDbgAssert((dma_streams_mask & channel) != 0,
-                "dmaStreamRelease(), #1", "not allocated");
-
-  dma_streams_mask &= ~channel; /* Marks the stream as not allocated.*/
-}
-
-#endif /* LPC17xx_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/lpc17xx_dma.h b/os/hal/platforms/LPC17xx/lpc17xx_dma.h
deleted file mode 100644
index 259f90d7a..000000000
--- a/os/hal/platforms/LPC17xx/lpc17xx_dma.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx DMA driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/LPC17xx_dma.h
- * @brief   DMA driver header.
- *
- * @addtogroup LPC17xx_DMA
- * @{
- */
-
-#ifndef _LPC17xx_DMA_H_
-#define _LPC17xx_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define DMACCONFIG_E                        (1UL << 0)
-#define DMACCONFIG_M                        (1UL << 1)
-
-/**
- * @brief   Total number of DMA streams.
- * @note    This is the total number of streams among all the DMA units.
- */
-#define LPC17xx_DMA_CHANNELS                8
-
-/**
- * @name    DMA control data configuration
- * @{
- */
-
-/**
- * @brief   DMA transfer size.
- *
- * @param[in] n    DMA transfer size
- */
-#define DMA_CTRL_TRANSFER_SIZE(n)           (n)
-
-/**
- * @brief   DMA source burst size.
- */
-#define DMA_CTRL_SRC_BSIZE_1                (0 << 12)
-#define DMA_CTRL_SRC_BSIZE_4                (1UL << 12)
-#define DMA_CTRL_SRC_BSIZE_8                (2UL << 12)
-#define DMA_CTRL_SRC_BSIZE_16               (3UL << 12)
-#define DMA_CTRL_SRC_BSIZE_32               (4UL << 12)
-#define DMA_CTRL_SRC_BSIZE_64               (5UL << 12)
-#define DMA_CTRL_SRC_BSIZE_128              (6UL << 12)
-#define DMA_CTRL_SRC_BSIZE_256              (7UL << 12)
-
-/**
- * @brief   DMA destination burst size.
- * @{
- */
-#define DMA_CTRL_DST_BSIZE_1                (0 << 15)
-#define DMA_CTRL_DST_BSIZE_4                (1UL << 15)
-#define DMA_CTRL_DST_BSIZE_8                (2UL << 15)
-#define DMA_CTRL_DST_BSIZE_16               (3UL << 15)
-#define DMA_CTRL_DST_BSIZE_32               (4UL << 15)
-#define DMA_CTRL_DST_BSIZE_64               (5UL << 15)
-#define DMA_CTRL_DST_BSIZE_128              (6UL << 15)
-#define DMA_CTRL_DST_BSIZE_256              (7UL << 15)
-/** @} */
-
-/**
- * @name    DMA source transfer width.
- * @{
- */
-#define DMA_CTRL_SRC_WIDTH_BYTE             (0 << 18)
-#define DMA_CTRL_SRC_WIDTH_HWORD            (1UL << 18)
-#define DMA_CTRL_SRC_WIDTH_WORD             (2UL << 18)
-/** @} */
-
-/**
- * @name    DMA destination transfer width.
- * @{
- */
-#define DMA_CTRL_DST_WIDTH_BYTE             (0 << 21)
-#define DMA_CTRL_DST_WIDTH_HWORD            (1UL << 21)
-#define DMA_CTRL_DST_WIDTH_WORD             (2UL << 21)
-
-/**
- * @name    DMA source increment after each transfer.
- * @{
- */
-#define DMA_CTRL_SRC_NOINC                  (0UL << 26)
-#define DMA_CTRL_SRC_INC                    (1UL << 26)
-
-/**
- * @name    DMA destination increment after each transfer.
- * @{
- */
-#define DMA_CTRL_DST_NOINC                  (0UL << 27)
-#define DMA_CTRL_DST_INC                    (1UL << 27)
-
-/**
- * @name    DMA bus access bits.
- * @{
- */
-#define DMA_CTRL_PROT1_USER                 (0 << 28)
-#define DMA_CTRL_PROT1_PRIV                 (1UL << 28)
-
-#define DMA_CTRL_PROT2_NONBUFF              (0 << 29)
-#define DMA_CTRL_PROT2_BUFF                 (1UL << 29)
-
-#define DMA_CTRL_PROT3_NONCACHE             (0 << 30)
-#define DMA_CTRL_PROT3_CACHE                (1UL << 30)
-/** @} */
-
-/**
- * @name    DMA terminal count interrupt enable.
- * @{
- */
-#define DMA_CTRL_INT                        (1UL << 31)
-/** @} */
-
-/**
- * @name    DMA channel enable.
- * @{
- */
-#define DMA_CFG_CH_ENABLE                   (1UL << 0)
-
-/**
- * @brief   Source peripheral.
- *
- * @param[in] source        source peripheral
- */
-#define DMA_CFG_SRC_PERIPH(src)             ((src) << 1)
-
-/**
- * @brief   Destination peripheral.
- *
- * @param[in] destination   destination peripheral
- */
-#define DMA_CFG_DST_PERIPH(dst)             ((dst) << 6)
-
-/**
- * @name    Transfer type.
- * @{
- */
-#define DMA_CFG_TTYPE_M2M                   (0 << 11)
-#define DMA_CFG_TTYPE_M2P                   (1UL << 11)
-#define DMA_CFG_TTYPE_P2M                   (2UL << 11)
-#define DMA_CFG_TTYPE_P2P                   (3UL << 11)
-/** @} */
-
-/**
- * @name    Interrupt error mask.
- * @{
- */
-#define DMA_CFG_IE                          (1UL << 14)
-/** @} */
-
-/**
- * @name    Terminal count interrupt mask.
- * @{
- */
-#define DMA_CFG_ITC                         (1UL << 15)
-/** @} */
-
-/**
- * @name    Active.
- * @note    Read only
- * @{
- */
-#define DMA_CFG_ACTIVE                      (1UL << 17)
-/** @} */
-
-/**
- * @name    Halt.
- * @{
- */
-#define DMA_CFG_HALT                        (1UL << 18)
-/** @} */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DMA interrupt priority level setting.
- */
-#if !defined(LPC17xx_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_DMA_IRQ_PRIORITY            3
-#endif
-
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-typedef struct {
-  volatile uint32_t srcaddr;        /**< @brief Source address.         */
-  volatile uint32_t dstaddr;        /**< @brief Destination address.    */
-  volatile uint32_t lli;            /**< @brief Linked List Item.       */
-  volatile uint32_t control;        /**< @brief Control.                */
-  volatile uint32_t config;         /**< @brief Configuration.          */
-} lpc17xx_dma_channel_config_t;
-
-typedef struct {
-  volatile uint32_t srcaddr;        /**< @brief Source address.         */
-  volatile uint32_t dstaddr;        /**< @brief Destination address.    */
-  volatile uint32_t lli;            /**< @brief Linked List Item.       */
-  volatile uint32_t control;        /**< @brief Control.                */
-} lpc17xx_dma_lli_config_t;
-
-/**
- * @brief   DMA channel number.
- */
-typedef enum {
-  DMA_CHANNEL0               = 0,
-  DMA_CHANNEL1               = 1,
-  DMA_CHANNEL2               = 2,
-  DMA_CHANNEL3               = 3,
-  DMA_CHANNEL4               = 4,
-  DMA_CHANNEL5               = 5,
-  DMA_CHANNEL6               = 6,
-  DMA_CHANNEL7               = 7
-
-} lpc17xx_dma_channel_t;
-
- /**
-  * @brief   DMA source or destination type.
-  */
- typedef enum {
-   DMA_SSP0_TX          = 0,
-   DMA_SSP0_RX          = 1,
-   DMA_SSP1_TX          = 2,
-   DMA_SSP1_RX          = 3,
-   DMA_ADC              = 4,
-   DMA_I2S_CH0          = 5,
-   DMA_I2S_CH1          = 6,
-   DMA_DAC              = 7,
-   DMA_UART0_TX_MAT0_0  = 8,
-   DMA_UART0_RX_MAT0_1  = 9,
-   DMA_UART1_TX_MAT1_0  = 10,
-   DMA_UART1_RX_MAT1_1  = 11,
-   DMA_UART2_TX_MAT2_0  = 12,
-   DMA_UART2_RX_MAT2_1  = 13,
-   DMA_UART3_TX_MAT3_0  = 14,
-   DMA_UART3_RX_MAT3_1  = 15
- } lpc17xx_dma_src_dst_t;
-
-/**
- * @brief   LPC17xx DMA ISR function type.
- *
- * @param[in] p         parameter for the registered function
- * @param[in] flags     pre-shifted content of the xISR register, the bits
- *                      are aligned to bit zero
- */
-typedef void (*lpc17xx_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-
-/**
- * @brief   Associates a memory source to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] addr      pointer to a source address
- *
- * @special
- */
-#define dmaChannelSrcAddr(dmach, addr)                                     \
-  _lpc17xx_dma_channel_config_t[dmach]->CSrcAddr = (uint32_t)(addr)
-
-/**
- * @brief   Associates a memory destination to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] addr      pointer to a destination address
- *
- * @special
- */
-#define dmaChannelDstAddr(dmach, addr)                                    \
-  _lpc17xx_dma_channel_config_t[dmach]->CDestAddr = (uint32_t)(addr)
-
-/**
- * @brief   Associates a linked list item address to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] addr      pointer to a linked list item
- *
- * @special
- */
-#define dmaChannelLinkedList(dmach, addr)                                 \
-  _lpc17xx_dma_channel_config_t[dmach]->CLLI = ((uint32_t)(addr))
-
-/**
- * @brief   Set control configuration to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] ctrl      control configuration value
- *
- * @special
- */
-#define dmaChannelControl(dmach, ctrl)                                     \
-  _lpc17xx_dma_channel_config_t[dmach]->CControl = (ctrl)
-
-/**
- * @brief   Set configuration to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaStreamAllocate().
- * @post    After use the channel can be released using @p dmaStreamRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] config    dma channel configuration value
- *
- * @special
- */
-#define dmaChannelConfig(dmach, config)                                    \
-  _lpc17xx_dma_channel_config_t[dmach]->CConfig = (config)
-
-/**
- * @brief   Trigger DMA software burst transfer request.
- *
- * @param[in] src   peripheral source request
- *
- * @special
- */
-#define dmaSoftBurstRequest(src)                                            \
-  LPC_GPDMA->SoftBReq = (src)
-
-/**
- * @brief   Trigger DMA software single transfer request.
- *
- * @param[in] src   peripheral source request
- *
- * @special
- */
-#define dmaSoftSingleRequest(src)                                           \
-  LPC_GPDMA->SoftSReq = (src)
-
-/**
- * @brief   DMA channel enable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- *
- * @special
- */
-#define dmaChannelEnable(dmach)                                            \
-  _lpc17xx_dma_channel_config_t[dmach]->CConfig |= (DMA_CFG_CH_ENABLE)
-
-/**
- * @brief   DMA channel disable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- *
- * @special
- */
-#define dmaChannelDisable(dmach)                                           \
-  _lpc17xx_dma_channel_config_t[dmach]->CConfig &= ~(DMA_CFG_CH_ENABLE)
-
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern LPC_GPDMACH_TypeDef * _lpc17xx_dma_channel_config_t[];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dmaInit(void);
-  bool_t dmaChannelAllocate(lpc17xx_dma_channel_t dmach,
-                           lpc17xx_dmaisr_t func,
-                           void *param);
-  void dmaChannelRelease(lpc17xx_dma_channel_t dmach);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _LPC17xx_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/mac_lld.c b/os/hal/platforms/LPC17xx/mac_lld.c
deleted file mode 100644
index 81b76a36f..000000000
--- a/os/hal/platforms/LPC17xx/mac_lld.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-  This file has been contributed by:
-                Marcin Jokel.
-*/
-
-/**
- * @file    LPC17xx/mac_lld.c
- * @brief   LPC17xx low level MAC driver code.
- *
- * @addtogroup MAC
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-#include "mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define BUFFER_SIZE ((((LPC17xx_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
-
-/* MII divider optimal value.*/
-#if (LPC17xx_CCLK <= 50000000)
-#define MAC_MII_MCFG_CLK_SEL      EMAC_MCFG_CLK_DIV_20
-#elif (LPC17xx_CCLK <= 70000000)
-#define MAC_MII_MCFG_CLK_SEL      EMAC_MCFG_CLK_DIV_28
-#elif (LPC17xx_CCLK <= 80000000)
-#define MAC_MII_MCFG_CLK_SEL      EMAC_MCFG_CLK_DIV_36
-#elif (LPC17xx_CCLK <= 90000000)
-#define MAC_MII_MCFG_CLK_SEL      EMAC_MCFG_CLK_DIV_40
-#elif (LPC17xx_CCLK <= 100000000)
-#define MAC_MII_MCFG_CLK_SEL      EMAC_MCFG_CLK_DIV_44
-#elif (LPC17xx_CCLK <= 120000000)
-#define MAC_MII_MCFG_CLK_SEL      EMAC_MCFG_CLK_DIV_48
-#else
-#error "LPC17xx_CCLK over maximum frequency for ETH operations (120MHz)"
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Ethernet driver 1.
- */
-MACDriver ETHD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
-                                              0x37, 0x01, 0x10};
-
-static lpc17xx_eth_rx_descriptor_t rd[LPC17xx_MAC_RECEIVE_BUFFERS]
-  __attribute__((aligned(4))) __attribute__((section(".eth_ram")));
-static lpc17xx_eth_tx_descriptor_t td[LPC17xx_MAC_TRANSMIT_BUFFERS]
-  __attribute__((aligned(4))) __attribute__((section(".eth_ram")));
-
-static lpc17xx_eth_tx_descriptor_t td_tmp[LPC17xx_MAC_TRANSMIT_BUFFERS]
-  __attribute__((aligned(4))) __attribute__((section(".eth_ram")));
-
-static lpc17xx_eth_rx_status_t rd_stat[LPC17xx_MAC_RECEIVE_BUFFERS]
-  __attribute__((aligned(8))) __attribute__((section(".eth_ram")));
-static lpc17xx_eth_tx_status_t td_stat[LPC17xx_MAC_TRANSMIT_BUFFERS]
-  __attribute__((aligned(4))) __attribute__((section(".eth_ram")));
-
-static uint32_t rb[LPC17xx_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]
-  __attribute__((aligned(4))) __attribute__((section(".eth_ram")));
-static uint32_t tb[LPC17xx_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]
-  __attribute__((aligned(4))) __attribute__((section(".eth_ram")));
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Writes a PHY register.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] reg       register number
- * @param[in] value     new register value
- */
-void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) {
-
-  LPC_EMAC->MCMD = 0;
-  LPC_EMAC->MADR = macp->phyaddr | reg; /* Write PHY address and register address */
-  LPC_EMAC->MWTD = value;               /* Write data */
-  while((LPC_EMAC->MIND & EMAC_MIND_BUSY) != 0)
-    ;                                   /* Wait for busy bit to be cleared in MIND */
-
-}
-
-/**
- * @brief   Reads a PHY register.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] reg       register number
- *
- * @return              The PHY register content.
- */
-uint32_t mii_read(MACDriver *macp, uint32_t reg) {
-
-  LPC_EMAC->MCMD = 1;
-  LPC_EMAC->MADR = macp->phyaddr | reg; /* Write PHY address and register address */
-  while((LPC_EMAC->MIND & EMAC_MIND_BUSY) != 0)
-    ;                                   /* Wait for busy bit to be cleared in MIND */
-  LPC_EMAC->MCMD = 0;
-  return LPC_EMAC->MRDD;
-}
-
-#if !defined(BOARD_PHY_ADDRESS)
-/**
- * @brief   PHY address detection.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- */
-void mii_find_phy(MACDriver *macp) {
-  uint32_t i;
-
-#if LPC17xx_MAC_PHY_TIMEOUT > 0
-  halrtcnt_t start = halGetCounterValue();
-  halrtcnt_t timeout  = start + MS2RTT(LPC17xx_MAC_PHY_TIMEOUT);
-  while (halIsCounterWithin(start, timeout)) {
-#endif
-    for (i = 0; i < 31; i++) {
-      macp->phyaddr = i << 8;
-      if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
-          ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
-        return;
-      }
-    }
-#if LPC17xx_MAC_PHY_TIMEOUT > 0
-  }
-#endif
-  /* Wrong or defective board.*/
-  chSysHalt();
-}
-#endif
-
-/**
- * @brief   MAC address setup.
- *
- * @param[in] p         pointer to a six bytes buffer containing the MAC
- *                      address
- */
-static void mac_lld_set_address(const uint8_t *p) {
-
-  /* MAC address configuration, only a single address comparator is used,
-     hash table not used.*/
-
-  LPC_EMAC->SA0 = ((uint32_t)p[5] << 8) |
-                  ((uint32_t)p[4] << 0);
-  LPC_EMAC->SA1 = ((uint32_t)p[3] << 8) |
-                  ((uint32_t)p[2] << 0);
-  LPC_EMAC->SA2 = ((uint32_t)p[1] << 8) |
-                  ((uint32_t)p[0] << 0);
-
-  LPC_EMAC->HashFilterL = 0;
-  LPC_EMAC->HashFilterH = 0;
-
-  LPC_EMAC->RxFilterCtrl = EMAC_RXFILCTRL_PERFECT_EN | EMAC_RXFILCTRL_BROADCAST_EN;
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-CH_IRQ_HANDLER(VectorB0) {
-
-  uint32_t intstatus;
-  uint32_t consume_index;
-  uint32_t txdescn;
-
-  CH_IRQ_PROLOGUE();
-
-  intstatus = LPC_EMAC->IntStatus;
-  LPC_EMAC->IntClear = intstatus;
-
-  if (intstatus & EMAC_INTSTAT_RX_OVERRUN) {
-    /* Reset receive logic. */
-    LPC_EMAC->MAC1 |= EMAC_MAC1_RESET_RX | EMAC_MAC1_RESET_MCS_RX;
-    __NOP();
-    LPC_EMAC->MAC1 &= ~(EMAC_MAC1_RESET_RX | EMAC_MAC1_RESET_MCS_RX);
-  }
-
-  if (intstatus & EMAC_INTSTAT_TX_UNDERRUN) {
-    /* Reset transmit logic. */
-    LPC_EMAC->MAC1 |= EMAC_MAC1_RESET_TX | EMAC_MAC1_RESET_MCS_TX;
-    __NOP();
-    LPC_EMAC->MAC1 &= ~(EMAC_MAC1_RESET_TX | EMAC_MAC1_RESET_MCS_TX);
-  }
-
-  if (intstatus & EMAC_INTSTAT_RX_DONE) {
-    /* Data Received.*/
-    chSysLockFromIsr();
-    chSemResetI(&ETHD1.rdsem, 0);
-#if MAC_USE_EVENTS
-    chEvtBroadcastI(&ETHD1.rdevent);
-#endif
-    chSysUnlockFromIsr();
-  }
-
-  if (intstatus & EMAC_INTSTAT_TX_DONE) {
-    /* Data Transmitted.*/
-    consume_index = LPC_EMAC->TxConsumeIndex;
-    if (consume_index == 0)
-      consume_index = LPC17xx_MAC_TRANSMIT_BUFFERS - 1;
-    else
-      consume_index--;
-    txdescn = (td[consume_index].control >> 12) & 0x000000FF;
-    td_tmp[txdescn].control = 0;    /* Unlock temporary descriptor. */
-    chSysLockFromIsr();
-    chSemResetI(&ETHD1.tdsem, 0);
-    chSysUnlockFromIsr();
-  }
-
-  CH_IRQ_EPILOGUE();
-
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level MAC initialization.
- *
- * @notapi
- */
-void mac_lld_init(void) {
-  unsigned i;
-
-  macObjectInit(&ETHD1);
-  ETHD1.link_up = FALSE;
-
-  LPC_SC->PCONP |= (1 << 30);  /* Power up MAC */
-
-  /* Rx desciptor and Rx status tables are initialized. */
-  for (i = 0; i < LPC17xx_MAC_RECEIVE_BUFFERS; i++) {
-    rd[i].packet = (uint32_t) &rb[i];
-    rd[i].control = EMAC_RXSTATUS_CTRL_INT | (LPC17xx_MAC_BUFFERS_SIZE - 1);
-
-    rd_stat[i].info = 0;
-    rd_stat[i].hashcrc = 0;
-  }
-
-  /* Tx desciptor and Tx status tables are cleared. They are set up every time
-  when transmission starts. */
-  for (i = 0; i < LPC17xx_MAC_TRANSMIT_BUFFERS; i++) {
-    td[i].packet = 0;
-    td[i].control = 0;
-    td_stat[i] = 0;
-
-    td_tmp[i].packet = (uint32_t) &tb[i];
-    td_tmp[i].control = 0;
-  }
-
-  /* Reset all EMAC internal modules. */
-  LPC_EMAC->MAC1 = EMAC_MAC1_RESET_TX | EMAC_MAC1_RESET_MCS_TX | EMAC_MAC1_RESET_RX |
-      EMAC_MAC1_RESET_MCS_RX  | EMAC_MAC1_SIM_RESET | EMAC_MAC1_SOFT_RESET;
-  LPC_EMAC->Command = EMAC_COMMAND_REG_RESET | EMAC_COMMAND_TX_RESET | EMAC_COMMAND_RX_RESET;
-  LPC_EMAC->MCFG = EMAC_MCFG_RESET_MII_MGMT;        /* Reset MII Managment hardware. */
-
-  halPolledDelay(LPC17XX_MAC_RESET_DELAY);
-
-  LPC_EMAC->MAC1 = 0;                           /* MAC reset de-asserted. */
-
-  /* Selection of the RMII or MII mode based on info exported by board.h.*/
-#if defined(BOARD_PHY_RMII)
-  LPC_EMAC->Command = EMAC_COMMAND_RMII | EMAC_COMMAND_PASS_RUN_FRAME;
-#else
-  LPC_EMAC->Command = EMAC_COMMAND_PASS_RUN_FRAME;
-#endif
-
-  LPC_EMAC->MCFG = MAC_MII_MCFG_CLK_SEL;        /* Set MII clock divider. */
-
-  /* PHY address setup.*/
-#if defined(BOARD_PHY_ADDRESS)
-  ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
-#else
-  mii_find_phy(&ETHD1);
-#endif
-
-#if defined(BOARD_PHY_RESET)
-  /* PHY board-specific reset procedure.*/
-  BOARD_PHY_RESET();
-#else
-  /* PHY soft reset procedure.*/
-  mii_write(&ETHD1, MII_BMCR, BMCR_RESET);
-#if defined(BOARD_PHY_RESET_DELAY)
-  halPolledDelay(BOARD_PHY_RESET_DELAY);
-#endif
-  while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)
-    ;
-#endif
-
-}
-
-/**
- * @brief   Configures and activates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_start(MACDriver *macp) {
-
-  /* PHY in power up mode.*/
-  mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
-
-  /* MAC registers configuration.*/
-  LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL_REC;
-  LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_CRC_EN;
-  LPC_EMAC->MAXF = LPC17XX_MAC_MAX_FLEN;
-  LPC_EMAC->CLRT = LPC17XX_MAC_CLRT_DEF;
-  LPC_EMAC->IPGR = LPC17XX_MAC_IPGR_DEF;
-
-  /* MAC descriptor registers configuration. */
-  macp->rxsoftindex = 0;
-  LPC_EMAC->RxDescriptor = (uint32_t) &rd[0];
-  LPC_EMAC->RxDescriptorNumber = LPC17xx_MAC_RECEIVE_BUFFERS - 1;
-  LPC_EMAC->RxConsumeIndex = 0;
-  LPC_EMAC->RxStatus = (uint32_t) &rd_stat[0];
-
-  macp->txsoftindex = 0;
-  LPC_EMAC->TxDescriptor = (uint32_t) &td[0];
-  LPC_EMAC->TxDescriptorNumber = LPC17xx_MAC_TRANSMIT_BUFFERS - 1;
-  LPC_EMAC->TxProduceIndex = 0;
-  LPC_EMAC->TxStatus = (uint32_t) &td_stat[0];
-
-  /* MAC address setup.*/
-  if (macp->config->mac_address == NULL)
-    mac_lld_set_address(default_mac_address);
-  else
-    mac_lld_set_address(macp->config->mac_address);
-
-  /* Enable EMAC interrupts. */
-  LPC_EMAC->IntEnable = EMAC_INTEN_TX_DONE | EMAC_INTEN_RX_DONE |
-      EMAC_INTEN_RX_OVERRUN | EMAC_INTEN_TX_UNDERRUN;
-
-  /* Reset all interrupts. */
-  LPC_EMAC->IntClear  = 0xFFFF;
-
-  /* ISR vector enabled.*/
-  nvicEnableVector(ENET_IRQn, CORTEX_PRIORITY_MASK(LPC17xx_MAC_ETH_IRQ_PRIORITY));
-
-  /* Enable receive and transmit mode. */
-  LPC_EMAC->Command  |= EMAC_COMMAND_TX_ENABLE | EMAC_COMMAND_RX_ENABLE;
-  LPC_EMAC->MAC1     |= EMAC_MAC1_RECEIVE_EN;
-
-}
-
-/**
- * @brief   Deactivates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_stop(MACDriver *macp) {
-
-  if (macp->state != MAC_STOP) {
-
-    /* MAC and DMA stopped.*/
-    LPC_EMAC->MAC1 = 0;
-    LPC_EMAC->Command = 0;
-    LPC_EMAC->IntEnable = 0;
-
-    /* PHY in power down mode until the driver will be restarted.*/
-    mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
-
-    /* ISR vector disabled.*/
-    nvicDisableVector(ENET_IRQn);
-  }
-
-}
-
-/**
- * @brief   Returns a transmission descriptor.
- * @details One of the available transmission descriptors is locked and
- *          returned.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] tdp      pointer to a @p MACTransmitDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                      MACTransmitDescriptor *tdp) {
-  uint32_t produce_index;
-  uint32_t produce_index_next;
-
-  if (!macp->link_up)
-    return RDY_TIMEOUT;
-
-  chSysLock();
-
-  /* Get Current TX descriptor.*/
-  produce_index = macp->txsoftindex;
-
-  produce_index_next = (produce_index + 1) % LPC17xx_MAC_TRANSMIT_BUFFERS;
-  if (produce_index_next == LPC_EMAC->TxConsumeIndex) {
-    /* Full */
-    chSysUnlock();
-    return RDY_TIMEOUT;
-  }
-
-  /* Ensure that descriptor isn't locked by the Ethernet DMA or
-     another thread.*/
-  if (td_tmp[produce_index].control == EMAC_TXSTATUS_CTRL_LOCK) {
-    chSysUnlock();
-    return RDY_TIMEOUT;
-  }
-
-  /* Marks the current descriptor as locked using a reserved bit.*/
-  td_tmp[produce_index].control = EMAC_TXSTATUS_CTRL_LOCK;
-
-  /* Next TX descriptor to use.*/
-  macp->txsoftindex = produce_index_next;
-
-  chSysUnlock();
-
-  /* Set the buffer size and configuration.*/
-  tdp->offset = 0;
-  tdp->size = LPC17xx_MAC_BUFFERS_SIZE;
-  tdp->txdescn = produce_index;
-
-  return RDY_OK;
-}
-
-/**
- * @brief   Releases a transmit descriptor and starts the transmission of the
- *          enqueued data as a single frame.
- *
- * @param[in] tdp       the pointer to the @p MACTransmitDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
-
-  uint32_t produce_index;
-  uint32_t descn;
-
-  chSysLock();
-
-  produce_index = LPC_EMAC->TxProduceIndex;
-  descn = tdp->txdescn;
-
-  /* Set control bits and save temporary descriptor number. */
-  td[produce_index].control = EMAC_TXSTATUS_CTRL_INT | EMAC_TXSTATUS_CTRL_LAST | (descn << 12) |
-     (tdp->offset - 1);
-
-  td[produce_index].packet = td_tmp[descn].packet;
-  LPC_EMAC->TxProduceIndex = (LPC_EMAC->TxProduceIndex + 1) % LPC17xx_MAC_TRANSMIT_BUFFERS;
-  chSysUnlock();
-}
-
-/**
- * @brief   Returns a receive descriptor.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] rdp      pointer to a @p MACReceiveDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                     MACReceiveDescriptor *rdp) {
-  uint32_t consume_index;
-  uint32_t status;
-
-  chSysLock();
-
-  /* Get current rx descriptor number.*/
-  consume_index = macp->rxsoftindex;
-
-  if (LPC_EMAC->RxProduceIndex != consume_index) {
-    status = rd_stat[consume_index].info;
-    if (status != EMAC_RXSTATUS_INFO_ERROR) {
-      /* Found a valid one.*/
-      rdp->offset   = 0;
-      rdp->size     = (status & EMAC_RXSTATUS_INFO_SIZE_MASK) + 1;
-      rdp->rxdescn = consume_index;
-
-      macp->rxsoftindex = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
-
-      chSysUnlock();
-      return RDY_OK;
-    }
-    else {
-      /* Invalid frame found. */
-      if (LPC_EMAC->RxConsumeIndex == consume_index) {
-        consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
-        LPC_EMAC->RxConsumeIndex = consume_index;
-      }
-      else {
-        rd[consume_index].control |= EMAC_RXSTATUS_CTRL_READY;
-        consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
-      }
-      macp->rxsoftindex = consume_index;
-    }
-  }
-
-  chSysUnlock();
-
-  return RDY_TIMEOUT;
-}
-
-/**
- * @brief   Releases a receive descriptor.
- * @details The descriptor and its buffer are made available for more incoming
- *          frames.
- *
- * @param[in] rdp       the pointer to the @p MACReceiveDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
-
-  uint32_t consume_index;
-
-  chSysLock();
-
-  /* Only descriptor with number match RxConsumeIndex can release receive descriptors. */
-  consume_index = LPC_EMAC->RxConsumeIndex;
-
-  if (rdp->rxdescn == consume_index) {
-    consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
-
-    while (LPC_EMAC->RxProduceIndex != consume_index) {
-      if (rd[consume_index].control & EMAC_RXSTATUS_CTRL_READY) {
-        rd[consume_index].control &= ~EMAC_RXSTATUS_CTRL_READY;
-        consume_index = (consume_index + 1) % LPC17xx_MAC_RECEIVE_BUFFERS;
-      }
-      else {
-        break;
-      }
-    }
-
-  LPC_EMAC->RxConsumeIndex = consume_index;
-  }
-  else {
-    rd[rdp->rxdescn].control |= EMAC_RXSTATUS_CTRL_READY;
-  }
-
-  chSysUnlock();
-}
-
-/**
- * @brief   Updates and returns the link status.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @return              The link status.
- * @retval TRUE         if the link is active.
- * @retval FALSE        if the link is down.
- *
- * @notapi
- */
-bool_t mac_lld_poll_link_status(MACDriver *macp) {
-  uint32_t mac2, cmd, ipgt, supp, bmsr, bmcr;
-
-  mac2 = LPC_EMAC->MAC2;
-  cmd = LPC_EMAC->Command;
-
-  /* PHY CR and SR registers read.*/
-  (void)mii_read(macp, MII_BMSR);
-  bmsr = mii_read(macp, MII_BMSR);
-  bmcr = mii_read(macp, MII_BMCR);
-
-  /* Check on auto-negotiation mode.*/
-  if (bmcr & BMCR_ANENABLE) {
-    uint32_t lpa;
-
-    /* Auto-negotiation must be finished without faults and link established.*/
-    if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
-        (BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
-      return macp->link_up = FALSE;
-
-    /* Auto-negotiation enabled, checks the LPA register.*/
-    lpa = mii_read(macp, MII_LPA);
-
-    /* Check on link speed.*/
-    if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
-      supp = EMAC_SUPP_SPEED;
-    else
-      supp = 0;
-
-    /* Check on link mode.*/
-    if (lpa & (LPA_10FULL | LPA_100FULL)) {
-      mac2 |= EMAC_MAC2_FULL_DUPLEX;
-      cmd  |= EMAC_COMMAND_FULL_DUPLEX;
-      ipgt = LPC17XX_MAC_IPGT_FULL_DUPLEX_DEF;
-    }
-    else {
-      mac2 &= ~EMAC_MAC2_FULL_DUPLEX;
-      cmd  &= ~EMAC_COMMAND_FULL_DUPLEX;
-      ipgt = LPC17XX_MAC_IPGT_HALF_DUPLEX_DEF;
-    }
-  }
-  else {
-    /* Link must be established.*/
-    if (!(bmsr & BMSR_LSTATUS))
-      return macp->link_up = FALSE;
-
-    /* Check on link speed.*/
-    if (bmcr & BMCR_SPEED100)
-      supp = EMAC_SUPP_SPEED;
-    else
-      supp = 0;
-
-    /* Check on link mode.*/
-    if (bmcr & BMCR_FULLDPLX) {
-      mac2 |= EMAC_MAC2_FULL_DUPLEX;
-      cmd  |= EMAC_COMMAND_FULL_DUPLEX;
-      ipgt = LPC17XX_MAC_IPGT_FULL_DUPLEX_DEF;
-    }
-    else {
-      mac2 &= ~EMAC_MAC2_FULL_DUPLEX;
-      cmd  &= ~EMAC_COMMAND_FULL_DUPLEX;
-      ipgt = LPC17XX_MAC_IPGT_HALF_DUPLEX_DEF;
-    }
-  }
-
-  LPC_EMAC->MAC2 = mac2;
-  LPC_EMAC->SUPP = supp;
-  LPC_EMAC->Command = cmd;
-  LPC_EMAC->IPGT = ipgt;
-
-  /* Returns the link status.*/
-  return macp->link_up = TRUE;
-}
-
-/**
- * @brief   Writes to a transmit descriptor's stream.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf       pointer to the buffer containing the data to be
- *                      written
- * @param[in] size      number of bytes to be written
- * @return              The number of bytes written into the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if the maximum
- *                      frame size is reached.
- *
- * @notapi
- */
-size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                         uint8_t *buf,
-                                         size_t size) {
-
-  if (size > tdp->size - tdp->offset)
-    size = tdp->size - tdp->offset;
-
-  if (size > 0) {
-    memcpy((uint8_t *)td_tmp[tdp->txdescn].packet + tdp->offset, buf, size);
-    tdp->offset += size;
-  }
-  return size;
-
-}
-
-/**
- * @brief   Reads from a receive descriptor's stream.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[in] buf       pointer to the buffer that will receive the read data
- * @param[in] size      number of bytes to be read
- * @return              The number of bytes read from the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if there are
- *                      no more bytes to read.
- *
- * @notapi
- */
-size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                       uint8_t *buf,
-                                       size_t size) {
-
-  if (size > rdp->size - rdp->offset)
-    size = rdp->size - rdp->offset;
-
-  if (size > 0) {
-    memcpy(buf, (uint8_t *)rd[rdp->rxdescn].packet + rdp->offset, size);
-    rdp->offset += size;
-  }
-
-  return size;
-}
-
-#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
-/**
- * @brief   Returns a pointer to the next transmit buffer in the descriptor
- *          chain.
- * @note    The API guarantees that enough buffers can be requested to fill
- *          a whole frame.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] size      size of the requested buffer. Specify the frame size
- *                      on the first call then scale the value down subtracting
- *                      the amount of data already copied into the previous
- *                      buffers.
- * @param[out] sizep    pointer to variable receiving the buffer size, it is
- *                      zero when the last buffer has already been returned.
- *                      Note that a returned size lower than the amount
- *                      requested means that more buffers must be requested
- *                      in order to fill the frame data entirely.
- * @return              Pointer to the returned buffer.
- * @retval NULL         if the buffer chain has been entirely scanned.
- *
- * @notapi
- */
-uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
-                                          size_t size,
-                                          size_t *sizep) {
-
-  if (tdp->offset == 0) {
-    *sizep      = tdp->size;
-    tdp->offset = size;
-    return (uint8_t *)td_tmp[tdp->txdescn].packet;
-  }
-  *sizep = 0;
-  return NULL;
-}
-
-/**
- * @brief   Returns a pointer to the next receive buffer in the descriptor
- *          chain.
- * @note    The API guarantees that the descriptor chain contains a whole
- *          frame.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[out] sizep    pointer to variable receiving the buffer size, it is
- *                      zero when the last buffer has already been returned.
- * @return              Pointer to the returned buffer.
- * @retval NULL         if the buffer chain has been entirely scanned.
- *
- * @notapi
- */
-const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
-                                               size_t *sizep) {
-
-  if (rdp->size > 0) {
-    *sizep      = rdp->size;
-    rdp->offset = rdp->size;
-    rdp->size   = 0;
-    return (uint8_t *)rd[rdp->rxdescn].packet;
-  }
-  *sizep = 0;
-  return NULL;
-}
-#endif /* MAC_USE_ZERO_COPY */
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/mac_lld.h b/os/hal/platforms/LPC17xx/mac_lld.h
deleted file mode 100644
index 20d998c15..000000000
--- a/os/hal/platforms/LPC17xx/mac_lld.h
+++ /dev/null
@@ -1,661 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-  This file has been contributed by:
-                Marcin Jokel.
-*/
-
-/**
- * @file    LPC17xx/mac_lld.h
- * @brief   LPC17xx low level MAC driver header.
- *
- * @addtogroup MAC
- * @{
- */
-
-#ifndef _MAC_LLD_H_
-#define _MAC_LLD_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   This implementation supports the zero-copy mode API.
- */
-#define MAC_SUPPORTS_ZERO_COPY              TRUE
-
-/**
- * @name     MAC Configuration Register 1 bits
- * @{
- */
-#define EMAC_MAC1_RECEIVE_EN                (1UL << 0)
-#define EMAC_MAC1_PASS_ALL_REC              (1UL << 1)
-#define EMAC_MAC1_RX_FLOW_CTRL              (1UL << 2)
-#define EMAC_MAC1_TX_FLOW_CTRL              (1UL << 3)
-#define EMAC_MAC1_LOOPBACK                  (1UL << 4)
-#define EMAC_MAC1_RESET_TX                  (1UL << 8)
-#define EMAC_MAC1_RESET_MCS_TX              (1UL << 9)
-#define EMAC_MAC1_RESET_RX                  (1UL << 10)
-#define EMAC_MAC1_RESET_MCS_RX              (1UL << 11)
-#define EMAC_MAC1_SIM_RESET                 (1UL << 14)
-#define EMAC_MAC1_SOFT_RESET                (1UL << 15)
-
-/**
- * @name     MAC Configuration Register 2 bits
- * @{
- */
-#define EMAC_MAC2_FULL_DUPLEX               (1UL << 0)
-#define EMAC_MAC2_FRAME_LEN_CHECK           (1UL << 1)
-#define EMAC_MAC2_HUGE_FRAME_EN             (1UL << 2)
-#define EMAC_MAC2_DELAYED_CRC               (1UL << 3)
-#define EMAC_MAC2_CRC_EN                    (1UL << 4)
-#define EMAC_MAC2_PAD_CRC_EN                (1UL << 5)
-#define EMAC_MAC2_VLAN_PAN_EN               (1UL << 6)
-#define EMAC_MAC2_AUTO_DET_PAD_EN           (1UL << 7)
-#define EMAC_MAC2_PURE_PREA_ENF             (1UL << 8)
-#define EMAC_MAC2_LONG_PRE_ENF              (1UL << 9)
-#define EMAC_MAC2_NO_BACKOFF                (1UL << 12)
-#define EMAC_MAC2_BACK_PRESSURE             (1UL << 13)
-#define EMAC_MAC2_EXCESS_DEFFER             (1UL << 14)
-/** @} */
-
-/**
- * @name     PHY Support Register bits
- * @{
- */
-#define EMAC_SUPP_SPEED                     (1UL << 8)
-/** @} */
-
-/**
- * @name     Test Register bits
- * @{
- */
-#define EMAC_TEST_SHORTCUT_PAUSE_QUANTA     (1UL << 0)
-#define EMAC_TEST_PAUSE                     (1UL << 1)
-#define EMAC_TEST_BACKPRESSURE              (1UL << 2)
-/** @} */
-
-/**
- * @name     Test Register bits
- * @{
- */
-#define EMAC_TEST_SHORTCUT_PAUSE_QUANTA     (1UL << 0)
-#define EMAC_TEST_PAUSE                     (1UL << 1)
-#define EMAC_TEST_BACKPRESSURE              (1UL << 2)
-/** @} */
-
-/**
- * @name     MII Mgmt Configuration Register bits
- * @{
- */
-#define EMAC_MCFG_SCAN_INCR                 (1UL << 0)
-#define EMAC_MCFG_SUPPRESS_PREAMBLE         (1UL << 1)
-#define EMAC_MCFG_CLK_DIV_4                 (1UL << 2)
-#define EMAC_MCFG_CLK_DIV_6                 (2UL << 2)
-#define EMAC_MCFG_CLK_DIV_8                 (3UL << 2)
-#define EMAC_MCFG_CLK_DIV_10                (4UL << 2)
-#define EMAC_MCFG_CLK_DIV_14                (5UL << 2)
-#define EMAC_MCFG_CLK_DIV_20                (6UL << 2)
-#define EMAC_MCFG_CLK_DIV_28                (7UL << 2)
-#define EMAC_MCFG_CLK_DIV_36                (8UL << 2)
-#define EMAC_MCFG_CLK_DIV_40                (9UL << 2)
-#define EMAC_MCFG_CLK_DIV_44                (10UL << 2)
-#define EMAC_MCFG_CLK_DIV_48                (11UL << 2)
-#define EMAC_MCFG_CLK_DIV_52                (12UL << 2)
-#define EMAC_MCFG_CLK_DIV_56                (13UL << 2)
-#define EMAC_MCFG_CLK_DIV_60                (14UL << 2)
-#define EMAC_MCFG_CLK_DIV_64                (15UL << 2)
-#define EMAC_MCFG_RESET_MII_MGMT            (1UL << 15)
-/** @} */
-
-
-/**
- * @name     MII Mgmt Command Register bits
- * @{
- */
-#define EMAC_MCMD_READ                      (1UL << 0)
-#define EMAC_MCMD_SCAN                      (1UL << 1)
-/** @} */
-
-/**
- * @name    MIND MII Mgmt Indicators Register bits
- * @{
- */
-#define EMAC_MIND_BUSY                      (1UL << 0)
-#define EMAC_MIND_SCANNING                  (1UL << 1)
-#define EMAC_MIND_NOT_VALID                 (1UL << 2)
-#define EMAC_MIND_LINK_FAIL                 (1UL << 3)
-/** @} */
-
-/**
- * @name    Command Register bits
- * @{
- */
-#define EMAC_COMMAND_RX_ENABLE              (1UL << 0)
-#define EMAC_COMMAND_TX_ENABLE              (1UL << 1)
-#define EMAC_COMMAND_REG_RESET              (1UL << 3)
-#define EMAC_COMMAND_TX_RESET               (1UL << 4)
-#define EMAC_COMMAND_RX_RESET               (1UL << 5)
-#define EMAC_COMMAND_PASS_RUN_FRAME         (1UL << 6)
-#define EMAC_COMMAND_PASS_RX_FILTER         (1UL << 7)
-#define EMAC_COMMAND_PASS_TX_FLOW_CTRL      (1UL << 8)
-#define EMAC_COMMAND_RMII                   (1UL << 9)
-#define EMAC_COMMAND_FULL_DUPLEX            (1UL << 10)
-/** @} */
-
-/**
- * @name    Status Register bits
- * @{
- */
-#define EMAC_STATUS_RX                      (1UL << 0)
-#define EMAC_STATUS_TX                      (1UL << 1)
-/** @} */
-
-/**
- * @name    Transmit Status Vector 0 Register bits
- * @{
- */
-#define EMAC_TSV0_CRC_ERROR                 (1UL << 0)
-#define EMAC_TSV0_LEN_CHECK_ERROR           (1UL << 1)
-#define EMAC_TSV0_LEN_OUT_OF_RANGE          (1UL << 2)
-#define EMAC_TSV0_DONE                      (1UL << 3)
-#define EMAC_TSV0_MULTICAST                 (1UL << 4)
-#define EMAC_TSV0_BROADCAST                 (1UL << 5)
-#define EMAC_TSV0_PACKET_DEFER              (1UL << 6)
-#define EMAC_TSV0_EXCESSIVE_DEFER           (1UL << 7)
-#define EMAC_TSV0_EXCESSIVE_COLLISION       (1UL << 8)
-#define EMAC_TSV0_LATE_COLLISION            (1UL << 9)
-#define EMAC_TSV0_GIANT                     (1UL << 10)
-#define EMAC_TSV0_UNDERRUN                  (1UL << 11)
-#define EMAC_TSV0_CONTROL_FRAME             (1UL << 28)
-#define EMAC_TSV0_PAUSE                     (1UL << 29)
-#define EMAC_TSV0_BACKPRESSURE              (1UL << 30)
-#define EMAC_TSV0_VLAN                      (1UL << 31)
-/** @} */
-
-/**
- * @name    Receive Status Vector Register bits
- * @{
- */
-#define EMAC_RSV_PACKET_PREV_IGN            (1UL << 16)
-#define EMAC_RSV_RXDV_EVENT                 (1UL << 17)
-#define EMAC_RSV_CARRIER_EVENT              (1UL << 18)
-#define EMAC_RSV_RECEIVE_CODE               (1UL << 19)
-#define EMAC_RSV_CRC_ERROR                  (1UL << 20)
-#define EMAC_RSV_LEN_CHECK_ERROR            (1UL << 21)
-#define EMAC_RSV_LEN_OUT_OF_RANGE           (1UL << 22)
-#define EMAC_RSV_RECEIVE_OK                 (1UL << 23)
-#define EMAC_RSV_MULTICAST                  (1UL << 24)
-#define EMAC_RSV_BROADCAST                  (1UL << 25)
-#define EMAC_RSV_DRIBBLE_NIBBLE             (1UL << 26)
-#define EMAC_RSV_CTRL_FRAME                 (1UL << 27)
-#define EMAC_RSV_PAUSE                      (1UL << 28)
-#define EMAC_RSV_UNSUPPORTED_OPCODE         (1UL << 29)
-#define EMAC_RSV_VLAN                       (1UL << 30)
-/** @} */
-
-/**
- * @name    Receive Filter Control Register bits
- * @{
- */
-#define EMAC_RXFILCTRL_UNICAST_EN           (1UL << 0)
-#define EMAC_RXFILCTRL_BROADCAST_EN         (1UL << 1)
-#define EMAC_RXFILCTRL_MULTICAST_EN         (1UL << 2)
-#define EMAC_RXFILCTRL_UNICAST_HASH_EN      (1UL << 3)
-#define EMAC_RXFILCTRL_MULTICAST_HASH_EN    (1UL << 4)
-#define EMAC_RXFILCTRL_PERFECT_EN           (1UL << 5)
-#define EMAC_RXFILCTRL_MAGIC_PACKET_EN      (1UL << 12)
-#define EMAC_RXFILCTRL_RX_FILTER_EN         (1UL << 13)
-/** @} */
-
-/**
- * @name    Receive Filter WoL Status bits
- * @{
- */
-#define EMAC_RXFILWOLSTAT_UNICAST           (1UL << 0)
-#define EMAC_RXFILWOLSTAT_BROADCAST         (1UL << 1)
-#define EMAC_RXFILWOLSTAT_MULTICAST         (1UL << 2)
-#define EMAC_RXFILWOLSTAT_UNICAST_HASH      (1UL << 3)
-#define EMAC_RXFILWOLSTAT_MULTICAST_HASH    (1UL << 4)
-#define EMAC_RXFILWOLSTAT_PERFECT           (1UL << 5)
-#define EMAC_RXFILWOLSTAT_RX_FILTER         (1UL << 7)
-#define EMAC_RXFILWOLSTAT_MAGIC_PACKET      (1UL << 8)
-/** @} */
-
-/**
- * @name    Receive Filter WoL Clear bits
- * @{
- */
-#define EMAC_RXFILWOLCLR_UNICAST            (1UL << 0)
-#define EMAC_RXFILWOLCLR_BROADCAST          (1UL << 1)
-#define EMAC_RXFILWOLCLR_MULTICAST          (1UL << 2)
-#define EMAC_RXFILWOLCLR_UNICAST_HASH       (1UL << 3)
-#define EMAC_RXFILWOLCLR_MULTICAST_HASH     (1UL << 4)
-#define EMAC_RXFILWOLCLR_PERFECT            (1UL << 5)
-#define EMAC_RXFILWOLCLR_RX_FILTER          (1UL << 7)
-#define EMAC_RXFILWOLCLR_MAGIC_PACKET       (1UL << 8)
-/** @} */
-
-/**
- * @name    Interrupt Status Register bits
- * @{
- */
-#define EMAC_INTSTAT_RX_OVERRUN             (1UL << 0)
-#define EMAC_INTSTAT_RX_ERROR               (1UL << 1)
-#define EMAC_INTSTAT_RX_FINISHED            (1UL << 2)
-#define EMAC_INTSTAT_RX_DONE                (1UL << 3)
-#define EMAC_INTSTAT_TX_UNDERRUN            (1UL << 4)
-#define EMAC_INTSTAT_TX_ERROR               (1UL << 5)
-#define EMAC_INTSTAT_TX_FINISHED            (1UL << 6)
-#define EMAC_INTSTAT_TX_DONE                (1UL << 7)
-#define EMAC_INTSTAT_SOFT                   (1UL << 12)
-#define EMAC_INTSTAT_WAKEUP                 (1UL << 13)
-/** @} */
-
-/**
- * @name    Interrupt Enable Register bits
- * @{
- */
-#define EMAC_INTEN_RX_OVERRUN               (1UL << 0)
-#define EMAC_INTEN_RX_ERROR                 (1UL << 1)
-#define EMAC_INTEN_RX_FINISHED              (1UL << 2)
-#define EMAC_INTEN_RX_DONE                  (1UL << 3)
-#define EMAC_INTEN_TX_UNDERRUN              (1UL << 4)
-#define EMAC_INTEN_TX_ERROR                 (1UL << 5)
-#define EMAC_INTEN_TX_FINISHED              (1UL << 6)
-#define EMAC_INTEN_TX_DONE                  (1UL << 7)
-#define EMAC_INTEN_SOFT                     (1UL << 12)
-#define EMAC_INTEN_WAKEUP                   (1UL << 13)
-/** @} */
-
-/**
- * @name    Interrupt Clear Register bits
- * @{
- */
-#define EMAC_INTCLR_RX_OVERRUN              (1UL << 0)
-#define EMAC_INTCLR_RX_ERROR                (1UL << 1)
-#define EMAC_INTCLR_RX_FINISHED             (1UL << 2)
-#define EMAC_INTCLR_RX_DONE                 (1UL << 3)
-#define EMAC_INTCLR_TX_UNDERRUN             (1UL << 4)
-#define EMAC_INTCLR_TX_ERROR                 (1UL << 5)
-#define EMAC_INTCLR_TX_FINISHED             (1UL << 6)
-#define EMAC_INTCLR_TX_DONE                 (1UL << 7)
-#define EMAC_INTCLR_SOFT                    (1UL << 12)
-#define EMAC_INTCLR_WAKEUP                  (1UL << 13)
-/** @} */
-
-/**
- * @name    Interrupt Set Register bits
- * @{
- */
-#define EMAC_INTSET_RX_OVERRUN              (1UL << 0)
-#define EMAC_INTSET_RX_ERROR                (1UL << 1)
-#define EMAC_INTSET_RX_FINISHED             (1UL << 2)
-#define EMAC_INTSET_RX_DONE                 (1UL << 3)
-#define EMAC_INTSET_TX_UNDERRUN             (1UL << 4)
-#define EMAC_INTSET_TX_ERROR                (1UL << 5)
-#define EMAC_INTSET_TX_FINISHED             (1UL << 6)
-#define EMAC_INTSET_TX_DONE                 (1UL << 7)
-#define EMAC_INTSET_SOFT                    (1UL << 12)
-#define EMAC_INTSET_WAKEUP                  (1UL << 13)
-/** @} */
-
-/**
- * @name     Power-Down Register bits
- * @{
- */
-#define EMAC_PWRDOWN_MAC_AHB                (1UL << 31)
-/** @} */
-
-/**
- * @name     Receive Descriptor Control bits
- * @{
- */
-#define EMAC_RXSTATUS_CTRL_SIZE_MASK        0x000007FF
-#define EMAC_RXSTATUS_CTRL_LOCK             (1UL << 11)
-#define EMAC_RXSTATUS_CTRL_READY            (1UL << 12)
-#define EMAC_RXSTATUS_RELEASE               (1UL << 12)
-#define EMAC_RXSTATUS_CTRL_INT              (1UL << 31)
-/** @} */
-
-/**
- * @name     Receive Descriptor Status bits
- * @{
- */
-#define EMAC_RXSTATUS_INFO_SIZE_MASK        0x000007FF
-#define EMAC_RXSTATUS_INFO_CTRL_FRAME       (1UL << 18)
-#define EMAC_RXSTATUS_INFO_VLAN             (1UL << 19)
-#define EMAC_RXSTATUS_INFO_FAIL_FILTER      (1UL << 20)
-#define EMAC_RXSTATUS_INFO_MULTICAST        (1UL << 21)
-#define EMAC_RXSTATUS_INFO_BROADCAST        (1UL << 22)
-#define EMAC_RXSTATUS_INFO_CRC_ERROR        (1UL << 23)
-#define EMAC_RXSTATUS_INFO_SYMBOL_ERROR     (1UL << 24)
-#define EMAC_RXSTATUS_INFO_LENGTH_ERROR     (1UL << 25)
-#define EMAC_RXSTATUS_INFO_RANGE_ERROR      (1UL << 26)
-#define EMAC_RXSTATUS_INFO_ALLIG_ERROR      (1UL << 27)
-#define EMAC_RXSTATUS_INFO_OVERRUN          (1UL << 28)
-#define EMAC_RXSTATUS_INFO_NO_DESCRIPTOR    (1UL << 29)
-#define EMAC_RXSTATUS_INFO_LAST_FLAG        (1UL << 30)
-#define EMAC_RXSTATUS_INFO_ERROR            (1UL << 31)
-/** @} */
-
-/**
- * @name     Transmit Descriptor Control bits
- * @{
- */
-#define EMAC_TXSTATUS_CTRL_SIZE_MASK        0x000007FF
-#define EMAC_TXSTATUS_CTRL_LOCK             (1UL << 11)
-#define EMAC_TXSTATUS_CTRL_OVERRIDE         (1UL << 26)
-#define EMAC_TXSTATUS_CTRL_HUGE             (1UL << 27)
-#define EMAC_TXSTATUS_CTRL_PAD              (1UL << 28)
-#define EMAC_TXSTATUS_CTRL_CRC              (1UL << 29)
-#define EMAC_TXSTATUS_CTRL_LAST             (1UL << 30)
-#define EMAC_TXSTATUS_CTRL_INT              (1UL << 31)
-/** @} */
-
-/**
- * @name     Transmit Descriptor Status bits
- * @{
- */
-#define EMAC_RXSTATUS_INFO_COL_COUNT_MASK   (0x0FUL << 21)
-#define EMAC_RXSTATUS_INFO_DEFER            (1UL << 25)
-#define EMAC_RXSTATUS_INFO_EXC_DEFER        (1UL << 26)
-#define EMAC_RXSTATUS_INFO_EXC_COL          (1UL << 27)
-#define EMAC_RXSTATUS_INFO_LATE_COL         (1UL << 28)
-#define EMAC_RXSTATUS_INFO_UNDERRUN         (1UL << 29)
-#define EMAC_RXSTATUS_INFO_NO_DESC          (1UL << 30)
-#define EMAC_RXSTATUS_INFO_ERROR            (1UL << 31)
-/** @} */
-
-/**
- * @brief Collision Window / Retry register default value
- */
-#define LPC17XX_MAC_CLRT_DEF                0x0000370F
-
-/**
- * @brief Non Back-to-Back Inter-Packet-Gap register default value
- */
-#define LPC17XX_MAC_IPGR_DEF                0x00000015
-
-/**
- * @brief Back-to-Back Inter-Packet-Gap register default value
- */
-#define LPC17XX_MAC_IPGT_FULL_DUPLEX_DEF    0x00000015
-#define LPC17XX_MAC_IPGT_HALF_DUPLEX_DEF    0x00000012
-
-/** @} */
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Number of available transmit buffers.
- */
-#if !defined(LPC17xx_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
-#define LPC17xx_MAC_TRANSMIT_BUFFERS          2
-#endif
-
-/**
- * @brief   Number of available receive buffers.
- */
-#if !defined(LPC17xx_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
-#define LPC17xx_MAC_RECEIVE_BUFFERS           4
-#endif
-
-/**
- * @brief   Maximum supported frame size.
- */
-#if !defined(LPC17xx_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define LPC17xx_MAC_BUFFERS_SIZE              1522
-#endif
-
-/**
- * @brief   PHY detection timeout.
- * @details Timeout, in milliseconds, for PHY address detection, if a PHY
- *          is not detected within the timeout then the driver halts during
- *          initialization. This setting applies only if the PHY address is
- *          not explicitly set in the board header file using
- *          @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
- *          single search path is performed.
- */
-#if !defined(LPC17xx_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
-#define LPC17xx_MAC_PHY_TIMEOUT               100
-#endif
-
-/**
- * @brief   Change the PHY power state inside the driver.
- */
-#if !defined(LPC17xx_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
-#define LPC17xx_MAC_ETH1_CHANGE_PHY_STATE     TRUE
-#endif
-
-/**
- * @brief   ETHD1 interrupt priority level setting.
- */
-#if !defined(LPC17xx_MAC_ETH_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_MAC_ETH_IRQ_PRIORITY         13
-#endif
-
-/**
- * @brief   MAC number of ticks of delay after reset.
- */
-#if !defined(LPC17XX_MAC_RESET_DELAY) || defined(__DOXYGEN__)
-#define LPC17XX_MAC_RESET_DELAY               100
-#endif
-
-/**
- * @brief   MAC maximum frame length.
- */
-#if !defined(LPC17XX_MAC_MAX_FLEN) || defined(__DOXYGEN__)
-#define LPC17XX_MAC_MAX_FLEN                  1536
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC17xx_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
-#error "LPC17xx_MAC_PHY_TIMEOUT requires the realtime counter service"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of an LPC17xx Ethernet receive descriptor.
- */
-typedef struct {
-  volatile uint32_t     packet;
-  volatile uint32_t     control;
-} lpc17xx_eth_rx_descriptor_t;
-
-/**
- * @brief   Type of an LPC17xx Ethernet transmit descriptor.
- */
-typedef struct {
-  volatile uint32_t     packet;
-  volatile uint32_t     control;
-} lpc17xx_eth_tx_descriptor_t;
-
-/**
- * @brief   Type of an LPC17xx Ethernet receive status.
- */
-typedef struct {
-  volatile uint32_t     info;
-  volatile uint32_t     hashcrc;
-} lpc17xx_eth_rx_status_t;
-
-/**
- * @brief   Type of an LPC17xx Ethernet transmit status.
- */
-typedef volatile uint32_t lpc17xx_eth_tx_status_t;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief MAC address.
-   */
-  uint8_t               *mac_address;
-  /* End of the mandatory fields.*/
-} MACConfig;
-
-/**
- * @brief   Structure representing a MAC driver.
- */
-struct MACDriver {
-  /**
-   * @brief Driver state.
-   */
-  macstate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const MACConfig       *config;
-  /**
-   * @brief Transmit semaphore.
-   */
-  Semaphore             tdsem;
-  /**
-   * @brief Receive semaphore.
-   */
-  Semaphore             rdsem;
-#if MAC_USE_EVENTS || defined(__DOXYGEN__)
-  /**
-   * @brief Receive event.
-   */
-  EventSource           rdevent;
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Link status flag.
-   */
-  bool_t                link_up;
-  /**
-   * @brief PHY address (pre shifted).
-   */
-  uint32_t phyaddr;
-  /**
-   * @brief Software receive descriptor number.
-   */
-  uint32_t rxsoftindex;
-  /**
-   * @brief Software transmit descriptor number.
-   */
-  uint32_t txsoftindex;
-
-};
-
-/**
- * @brief   Structure representing a transmit descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current write offset.
-   */
-  size_t                    offset;
-  /**
-   * @brief Available space size.
-   */
-  size_t                    size;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Physical descriptor number.
-   */
-  uint32_t                  txdescn;
-} MACTransmitDescriptor;
-
-/**
- * @brief   Structure representing a receive descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current read offset.
-   */
-  size_t                offset;
-  /**
-   * @brief Available data size.
-   */
-  size_t                size;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Physical descriptor number.
-   */
-  uint32_t              rxdescn;
-} MACReceiveDescriptor;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern MACDriver ETHD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void mac_lld_init(void);
-  void mac_lld_start(MACDriver *macp);
-  void mac_lld_stop(MACDriver *macp);
-  msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                        MACTransmitDescriptor *tdp);
-  void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
-  msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                       MACReceiveDescriptor *rdp);
-  void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
-  bool_t mac_lld_poll_link_status(MACDriver *macp);
-  size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                           uint8_t *buf,
-                                           size_t size);
-  size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                         uint8_t *buf,
-                                         size_t size);
-
-  uint32_t mii_read(MACDriver *macp, uint32_t reg);
-  void mii_write(MACDriver *macp, uint32_t reg, uint32_t value);
-  void mii_find_phy(MACDriver *macp);
-#if MAC_USE_ZERO_COPY
-  uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
-                                            size_t size,
-                                            size_t *sizep);
-  const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
-                                                 size_t *sizep);
-#endif /* MAC_USE_ZERO_COPY */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _MAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/pal_lld.c b/os/hal/platforms/LPC17xx/pal_lld.c
deleted file mode 100644
index ce37a12f3..000000000
--- a/os/hal/platforms/LPC17xx/pal_lld.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/pal_lld.c
- * @brief   LPC17xx GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-/**
- * @brief   LPC17xx I/O ports configuration.
- * @details GPIO unit registers initialization.
- *
- * @param[in] config    the LPC17xx ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  LPC_GPIO0->FIODIR = config->P0.dir;
-  LPC_GPIO1->FIODIR = config->P1.dir;
-  LPC_GPIO2->FIODIR = config->P2.dir;
-  LPC_GPIO3->FIODIR = config->P3.dir;
-  LPC_GPIO4->FIODIR = config->P4.dir;
-  LPC_GPIO0->FIOMASK = 0;
-  LPC_GPIO1->FIOMASK = 0;
-  LPC_GPIO2->FIOMASK = 0;
-  LPC_GPIO3->FIOMASK = 0;
-  LPC_GPIO4->FIOMASK = 0;
-  LPC_GPIO0->FIOPIN = config->P0.data;
-  LPC_GPIO1->FIOPIN = config->P1.data;
-  LPC_GPIO2->FIOPIN = config->P2.data;
-  LPC_GPIO3->FIOPIN = config->P3.data;
-  LPC_GPIO4->FIOPIN = config->P4.data;
-}
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-uint32_t _pal_lld_readgroup(ioportid_t port,
-                            ioportmask_t mask,
-                            uint32_t offset) {
-
-  uint32_t p;
-
-  port->FIOMASK = ~((mask) << offset);
-  p = port->FIOPIN;
-  port->FIOMASK = 0;
-  return p;
-}
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-void _pal_lld_writegroup(ioportid_t port,
-                         ioportmask_t mask,
-                         uint32_t offset,
-                         uint32_t bits) {
-
-  port->FIOMASK = ~((mask) << offset);
-  port->FIOPIN = bits;
-  port->FIOMASK = 0;
-}
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    This function does not alter the @p PINSELx registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    port->FIODIR &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    palSetPort(port, PAL_WHOLE_PORT);
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->FIODIR |=  mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/pal_lld.h b/os/hal/platforms/LPC17xx/pal_lld.h
deleted file mode 100644
index 358956895..000000000
--- a/os/hal/platforms/LPC17xx/pal_lld.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/pal_lld.h
- * @brief   LPC17xx GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port setup info.
- */
-typedef struct {
-  /** Initial value for FIO_PIN register.*/
-  uint32_t      data;
-  /** Initial value for FIO_DIR register.*/
-  uint32_t      dir;
-} lpc17xx_gpio_setup_t;
-
-/**
- * @brief   GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    The @p IOCON block is not configured, initially all pins have
- *          enabled pullups and are programmed as GPIO. It is responsibility
- *          of the various drivers to reprogram the pins in the proper mode.
- *          Pins that are not handled by any driver may be programmed in
- *          @p board.c.
- */
-typedef struct {
-  /** @brief GPIO 0 setup data.*/
-  lpc17xx_gpio_setup_t   P0;
-  /** @brief GPIO 1 setup data.*/
-  lpc17xx_gpio_setup_t   P1;
-  /** @brief GPIO 2 setup data.*/
-  lpc17xx_gpio_setup_t   P2;
-  /** @brief GPIO 3 setup data.*/
-  lpc17xx_gpio_setup_t   P3;
-  /** @brief GPIO 4 setup data.*/
-  lpc17xx_gpio_setup_t   P4;
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef LPC_GPIO_TypeDef *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO0 port identifier.
- */
-#define IOPORT1         LPC_GPIO0
-#define GPIO0           LPC_GPIO0
-
-/**
- * @brief   GPIO1 port identifier.
- */
-#define IOPORT2         LPC_GPIO1
-#define GPIO1           LPC_GPIO1
-
-/**
- * @brief   GPIO2 port identifier.
- */
-#define IOPORT3         LPC_GPIO2
-#define GPIO2           LPC_GPIO2
-
-/**
- * @brief   GPIO3 port identifier.
- */
-#define IOPORT4         LPC_GPIO3
-#define GPIO3           LPC_GPIO3
-
-/**
- * @brief   GPIO3 port identifier.
- */
-#define IOPORT5         LPC_GPIO4
-#define GPIO4           LPC_GPIO4
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->FIOPIN)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->FIOPIN)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->FIOPIN = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->FIOSET = bits)
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) ((port)->FIOCLR = bits)
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset)                               \
-  _pal_lld_readgroup(port, mask, offset)
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                        \
-  _pal_lld_writegroup(port, mask, offset, bits)
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)                                    \
-  ((bit) == PAL_LOW) ? pal_lld_clearpad(port, pad) :                        \
-  pal_lld_setpad(port, pad)
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-  ((port)->FIOSET = 1UL << (pad))
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-  ((port)->FIOCLR = 1UL << (pad))
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  uint32_t _pal_lld_readgroup(ioportid_t port,
-                              ioportmask_t mask,
-                              uint32_t offset);
-  void _pal_lld_writegroup(ioportid_t port,
-                           ioportmask_t mask,
-                           uint32_t offset,
-                           uint32_t bits);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/platform.mk b/os/hal/platforms/LPC17xx/platform.mk
deleted file mode 100644
index 538532411..000000000
--- a/os/hal/platforms/LPC17xx/platform.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# List of all the LPC17xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC17xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/lpc17xx_dma.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/rtc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/dac_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/mac_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC17xx/can_lld.c
-             
-         
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC17xx
diff --git a/os/hal/platforms/LPC17xx/rtc_lld.c b/os/hal/platforms/LPC17xx/rtc_lld.c
deleted file mode 100644
index 7fffe4e36..000000000
--- a/os/hal/platforms/LPC17xx/rtc_lld.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx RTC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    LPC17xx/rtc_lld.c
- * @brief   LPC17xx RTC low level driver.
- *
- * @addtogroup RTC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief RTC driver identifier.
- */
-RTCDriver RTCD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Enable RTC clock.
- */
-#define _rtc_clk_enable()                                                     \
-  LPC_RTC->CCR |= CCR_CLKEN
-
-/**
- * @brief   Disable RTC clock.
- */
-#define _rtc_clk_disable()                                                    \
-    LPC_RTC->CCR &= ~CCR_CLKEN
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   RTC interrupt handler.
- *
- * @isr
- */
-
-#if LPC17xx_RTC_USE_ALARM || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector84) {
-  uint32_t status;
-
-  CH_IRQ_PROLOGUE();
-
-  status = LPC_RTC->ILR;
-  LPC_RTC->ILR = status;    /* Clear interrupt flag */
-
-  if ((status & ILR_RTCALF) && (RTCD1.callback != NULL))
-    RTCD1.callback(&RTCD1, RTC_EVENT_ALARM);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enable access to registers.
- *
- * @api
- */
-void rtc_lld_init(void) {
-
-  if(LPC_RTC->RTC_AUX & RTC_AUX_RTC_OSCF) {     /* Set after RTC power was first turn. */
-
-    LPC_RTC->CCR = CCR_CCALEN;                  /* Disable calibration and RTC clock. */
-    LPC_RTC->CALIBRATION = 0;
-    LPC_RTC->RTC_AUX = RTC_AUX_RTC_OSCF;        /* Clear RTC Oscillator Fail detect flag. */
-
-    LPC_RTC->CIIR = 0;                          /* Disable Counter Increment Interrupt. */
-    LPC_RTC->AMR = AMR_MASK_ALL;                /* Mask alarm interrupt. */
-    LPC_RTC->ILR = ILR_RTCALF | ILR_RTCCIF;     /* Clear interrupt flags. */
-
-    /* Set date to Saturday 01.01.2000 00:00:00 */
-    LPC_RTC->SEC  = 0;
-    LPC_RTC->MIN  = 0;
-    LPC_RTC->HOUR = 0;
-    LPC_RTC->DOM  = 1;
-    LPC_RTC->MONTH = 1;
-    LPC_RTC->YEAR = 2000;
-    LPC_RTC->DOW = 6;
-    LPC_RTC->DOY = 1;
-
-    _rtc_clk_enable();                          /* Enable RTC clock. */
-  }
-
-#if LPC17xx_RTC_USE_ALARM
-  nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(LPC17xx_RTC_IRQ_PRIORITY));
-#endif
-  return;
-}
-
-/**
- * @brief   Set current time.
- * @note    Fractional part will be silently ignored. There is no possibility
- *          to set it on STM32 platform.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] timespec  pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
-  (void)rtcp;
-
-  _rtc_clk_disable();                  /* Disable RTC clock. */
-  LPC_RTC->SEC  = timespec->sec;
-  LPC_RTC->MIN  = timespec->min;
-  LPC_RTC->HOUR = timespec->hour;
-  LPC_RTC->DOM  = timespec->dom;
-  LPC_RTC->MONTH = timespec->month;
-  LPC_RTC->YEAR = timespec->year;
-  LPC_RTC->DOW = timespec->dow;
-  LPC_RTC->DOY = timespec->doy;
-  _rtc_clk_enable();                  /* Enable RTC clock. */
-
-}
-
-/**
- * @brief   Get current time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
-  (void)rtcp;
-
-  timespec->sec = LPC_RTC->SEC;
-  timespec->min = LPC_RTC->MIN;
-  timespec->hour = LPC_RTC->HOUR;
-  timespec->dom = LPC_RTC->DOM;
-  timespec->month = LPC_RTC->MONTH;
-  timespec->year = LPC_RTC->YEAR;
-  timespec->dow = LPC_RTC->DOW;
-  timespec->doy = LPC_RTC->DOY;
-}
-
-/**
- * @brief     Set alarm time.
- *
- * @note      Default value after BKP domain reset for both comparators is 0.
- * @note      Function does not performs any checks of alarm time validity.
- *
- * @param[in] rtcp      Pointer to RTC driver structure.
- * @param[in] alarm     Alarm identifier. Can be 1 or 2.
- * @param[in] alarmspec Pointer to a @p RTCAlarm structure.
- *
- * @api
- */
-void rtc_lld_set_alarm(RTCDriver *rtcp,
-                       rtcalarm_t alarm,
-                       const RTCAlarm *alarmspec) {
-  (void)rtcp;
-  (void)alarm;
-  LPC_RTC->ALSEC = alarmspec->alsec;
-  LPC_RTC->ALMIN = alarmspec->almin;
-  LPC_RTC->ALHOUR = alarmspec->alhour;
-  LPC_RTC->ALDOM = alarmspec->aldom;
-  LPC_RTC->ALMON = alarmspec->almonth;
-  LPC_RTC->ALYEAR = alarmspec->alyear;
-  LPC_RTC->ALDOW = alarmspec->aldow;
-  LPC_RTC->ALDOY = alarmspec->aldoy;
-
-}
-
-/**
- * @brief   Get alarm time.
- *
- * @param[in] rtcp       pointer to RTC driver structure
- * @param[in] alarm      alarm identifier
- * @param[out] alarmspec pointer to a @p RTCAlarm structure
- *
- * @api
- */
-void rtc_lld_get_alarm(RTCDriver *rtcp,
-                       rtcalarm_t alarm,
-                       RTCAlarm *alarmspec) {
-  (void)rtcp;
-  (void)alarm;
-  alarmspec->alsec = LPC_RTC->ALSEC;
-  alarmspec->almin = LPC_RTC->ALMIN;
-  alarmspec->alhour = LPC_RTC->ALHOUR;
-  alarmspec->aldom = LPC_RTC->ALDOM;
-  alarmspec->almonth = LPC_RTC->ALMON;
-  alarmspec->alyear = LPC_RTC->ALYEAR;
-  alarmspec->aldow = LPC_RTC->ALDOW;
-  alarmspec->aldoy = LPC_RTC->ALDOY;
-
-}
-
-/**
- * @brief   Enables or disables RTC callbacks.
- * @details This function enables or disables callbacks, use a @p NULL pointer
- *          in order to disable a callback.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] callback  callback function pointer or @p NULL
- *
- * @notapi
- */
-void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
-
-  LPC_RTC->AMR = AMR_MASK_ALL;                /* Mask alarm interrupt. */
-  LPC_RTC->ILR = ILR_RTCALF;                  /* Clear interrupt flag. */
-
-  if (callback != NULL) {
-
-    /* IRQ sources enabled only after setting up the callback.*/
-    rtcp->callback = callback;
-    LPC_RTC->AMR = 0;           /* Enable alarm interrupt. */
-  }
-  else {
-
-    /* Callback set to NULL only after disabling the IRQ sources.*/
-    rtcp->callback = NULL;
-  }
-}
-
-#include "chrtclib.h"
-
-/**
- * @brief   Get current time in format suitable for usage in FatFS.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @return              FAT time value.
- *
- * @api
- */
-uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) {
-  uint32_t fattime;
-  struct tm timp;
-
-  rtcGetTimeTm(rtcp, &timp);
-
-  fattime  = (timp.tm_sec)       >> 1;
-  fattime |= (timp.tm_min)       << 5;
-  fattime |= (timp.tm_hour)      << 11;
-  fattime |= (timp.tm_mday)      << 16;
-  fattime |= (timp.tm_mon + 1)   << 21;
-  fattime |= (timp.tm_year - 80) << 25;
-
-  return fattime;
-}
-
-#endif /* HAL_USE_RTC */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/rtc_lld.h b/os/hal/platforms/LPC17xx/rtc_lld.h
deleted file mode 100644
index 5f65c0988..000000000
--- a/os/hal/platforms/LPC17xx/rtc_lld.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC17xx RTC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    LPC17xx/rtc_lld.h
- * @brief   LPC17xx RTC low level driver header.
- *
- * @addtogroup RTC
- * @{
- */
-
-#ifndef _RTC_LLD_H_
-#define _RTC_LLD_H_
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define ILR_RTCCIF         0x01
-#define ILR_RTCALF         0x02
-
-#define CCR_CLKEN          0x01
-#define CCR_CTCRST         0x02
-#define CCR_CCALEN         0x10
-
-#define CIIR_IMSEC         0x01
-#define CIIR_IMMIN         0x02
-#define CIIR_IMHOUR        0x04
-#define CIIR_IMDOM         0x08
-#define CIIR_IMDOW         0x10
-#define CIIR_IMDOY         0x20
-#define CIIR_IMMON         0x40
-#define CIIR_IMYEAR        0x80
-
-#define AMR_AMRSEC         0x01
-#define AMR_AMRMIN         0x02
-#define AMR_AMRHOUR        0x04
-#define AMR_AMRDOM         0x08
-#define AMR_AMRDOW         0x10
-#define AMR_AMRDOY         0x20
-#define AMR_AMRMON         0x40
-#define AMR_AMRYEAR        0x80
-#define AMR_MASK_ALL       0xFF
-
-#define RTC_AUX_RTC_OSCF        0x10
-
-#define RTC_AUXEN_RTC_OSCFEN    0x10
-
-/**
- * @brief   This RTC implementation supports callbacks.
- */
-#define RTC_SUPPORTS_CALLBACKS      TRUE
-
-/**
- * @brief   One alarm comparator available.
- */
-#define RTC_ALARMS          		1
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/*
- * RTC driver system settings.
- */
-
-/**
- * @brief   RTC Alarm enable.
- */
-#if !defined(LPC17xx_RTC_USE_ALARM) || defined(__DOXYGEN__)
-#define LPC17xx_RTC_USE_ALARM         FALSE
-#endif
-
-/**
- * @brief   RTC IRQ Priority.
- */
-#if !defined(LPC17xx_RTC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_RTC_IRQ_PRIORITY      3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an RTC alarm time stamp.
- */
-typedef struct RTCAlarm RTCAlarm;
-
-/**
- * @brief   Type of a structure representing an RTC wakeup period.
- */
-typedef struct RTCWakeup RTCWakeup;
-
-/**
- * @brief   Type of a structure representing an RTC callbacks config.
- */
-typedef struct RTCCallbackConfig RTCCallbackConfig;
-
-/**
- * @brief   Type of an RTC alarm.
- * @details Meaningful on platforms with more than 1 alarm comparator.
- */
-typedef uint32_t rtcalarm_t;
-
-/**
- * @brief   Type of an RTC event.
- */
-typedef enum {
-  RTC_EVENT_ALARM = 0                  /** Triggered on alarm. */
-} rtcevent_t;
-
-/**
- * @brief   Type of a generic RTC callback.
- */
-typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event);
-
-/**
- * @brief   Structure representing an RTC callbacks config.
- */
-struct RTCCallbackConfig{
-  /**
-   * @brief Generic RTC callback pointer.
-   */
-  rtccb_t           callback;
-};
-
-/**
- * @brief   Structure representing an RTC time stamp.
- */
-struct RTCTime {
-  /**
-   * @brief RTC seconds register.
-   */
-  uint8_t sec;
-  /**
-   * @brief RTC minutes register.
-   */
-  uint8_t min;
-  /**
-   * @brief RTC hours register.
-   */
-  uint8_t hour;
-  /**
-   * @brief RTC day of month register.
-   */
-  uint8_t dom;
-  /**
-   * @brief RTC month register.
-   */
-  uint8_t month;
-  /**
-   * @brief RTC day of week register.
-   */
-  uint8_t dow;
-  /**
-   * @brief RTC year register.
-   */
-  uint16_t year;
-  /**
-   * @brief RTC day of year register.
-   */
-  uint16_t doy;
-
-};
-
-/**
- * @brief   Structure representing an RTC alarm time stamp.
- */
-struct RTCAlarm {
-  /**
-   * @brief RTC alarm seconds register.
-   */
-  uint8_t alsec;
-  /**
-   * @brief RTC alarm minutes register.
-   */
-  uint8_t almin;
-  /**
-   * @brief RTC alarm hours register.
-   */
-  uint8_t alhour;
-  /**
-   * @brief RTC alarm day of month register.
-   */
-  uint8_t aldom;
-  /**
-   * @brief RTC alarm month register.
-   */
-  uint8_t almonth;
-  /**
-   * @brief RTC alarm day of week register.
-   */
-  uint8_t aldow;
-  /**
-   * @brief RTC alarm year register.
-   */
-  uint16_t alyear;
-  /**
-   * @brief RTC alarm day of year register.
-   */
-  uint16_t aldoy;
-
-};
-
-/**
- * @brief   Structure representing an RTC driver.
- */
-struct RTCDriver{
-  /**
-   * @brief Callback pointer.
-   */
-  rtccb_t           callback;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern RTCDriver RTCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void rtc_lld_init(void);
-  void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec);
-  void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec);
-  void rtc_lld_set_alarm(RTCDriver *rtcp,
-                         rtcalarm_t alarm,
-                         const RTCAlarm *alarmspec);
-  void rtc_lld_get_alarm(RTCDriver *rtcp,
-                         rtcalarm_t alarm,
-                         RTCAlarm *alarmspec);
-  void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback);
-  uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_RTC */
-
-#endif /* _RTC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/serial_lld.c b/os/hal/platforms/LPC17xx/serial_lld.c
deleted file mode 100644
index 0a73b0e03..000000000
--- a/os/hal/platforms/LPC17xx/serial_lld.c
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/serial_lld.c
- * @brief   LPC17xx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC17xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-#if LPC17xx_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-/** @brief UART1 serial driver identifier.*/
-SerialDriver SD2;
-#endif
-
-#if LPC17xx_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-/** @brief UART2 serial driver identifier.*/
-SerialDriver SD3;
-#endif
-
-#if LPC17xx_SERIAL_USE_UART3 || defined(__DOXYGEN__)
-/** @brief UART3 serial driver identifier.*/
-SerialDriver SD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  LCR_WL8 | LCR_STOP1 | LCR_NOPARITY,
-  FCR_TRIGGER0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   UART initialization.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
-  LPC_UART_TypeDef *u = sdp->uart;
-  uint32_t div = 0;
-
-#if LPC17xx_SERIAL_USE_UART0
-  if (&SD1 == sdp) {
-    div = LPC17xx_SERIAL_UART0_PCLK / (config->sc_speed << 4);
-  }
-#endif
-
-#if LPC17xx_SERIAL_USE_UART1
-  if (&SD2 == sdp) {
-    div = LPC17xx_SERIAL_UART1_PCLK / (config->sc_speed << 4);
-  }
-#endif
-
-#if LPC17xx_SERIAL_USE_UART2
-  if (&SD3 == sdp) {
-    div = LPC17xx_SERIAL_UART2_PCLK / (config->sc_speed << 4);
-  }
-#endif
-
-#if LPC17xx_SERIAL_USE_UART3
-  if (&SD4 == sdp) {
-    div = LPC17xx_SERIAL_UART3_PCLK / (config->sc_speed << 4);
-  }
-#endif
-
-  u->LCR = config->sc_lcr | LCR_DLAB;
-  u->DLL = div;
-  u->DLM = div >> 8;
-  u->LCR = config->sc_lcr;
-  u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr;
-  u->ACR = 0;
-  u->FDR = 0x10;
-  u->TER = TER_ENABLE;
-  u->IER = IER_RBR | IER_STATUS;
-}
-
-/**
- * @brief   UART de-initialization.
- *
- * @param[in] u         pointer to an UART I/O block
- */
-static void uart_deinit(LPC_UART_TypeDef *u) {
-
-  u->LCR = LCR_DLAB;
-  u->DLL = 1;
-  u->DLM = 0;
-  u->LCR = 0;
-  u->FDR = 0x10;
-  u->IER = 0;
-  u->FCR = FCR_RXRESET | FCR_TXRESET;
-  u->ACR = 0;
-  u->TER = TER_ENABLE;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] err       UART LSR register value
- */
-static void set_error(SerialDriver *sdp, IOREG32 err) {
-  flagsmask_t sts = 0;
-
-  if (err & LSR_OVERRUN)
-    sts |= SD_OVERRUN_ERROR;
-  if (err & LSR_PARITY)
-    sts |= SD_PARITY_ERROR;
-  if (err & LSR_FRAMING)
-    sts |= SD_FRAMING_ERROR;
-  if (err & LSR_BREAK)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- * @note    Tries hard to clear all the pending interrupt sources, we don't
- *          want to go through the whole ISR and have another interrupt soon
- *          after.
- *
- * @param[in] u         pointer to an UART I/O block
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  LPC_UART_TypeDef *u = sdp->uart;
-
-  while (TRUE) {
-    switch (u->IIR & IIR_SRC_MASK) {
-    case IIR_SRC_NONE:
-      return;
-    case IIR_SRC_ERROR:
-      set_error(sdp, u->LSR);
-      break;
-    case IIR_SRC_TIMEOUT:
-    case IIR_SRC_RX:
-      chSysLockFromIsr();
-      if (chIQIsEmptyI(&sdp->iqueue))
-        chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
-      chSysUnlockFromIsr();
-      while (u->LSR & LSR_RBR_FULL) {
-        chSysLockFromIsr();
-        if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK)
-          chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
-        chSysUnlockFromIsr();
-      }
-      break;
-    case IIR_SRC_TX:
-      {
-        int i = LPC17xx_SERIAL_FIFO_PRELOAD;
-        do {
-          msg_t b;
-
-          chSysLockFromIsr();
-          b = chOQGetI(&sdp->oqueue);
-          chSysUnlockFromIsr();
-          if (b < Q_OK) {
-            u->IER &= ~IER_THRE;
-            chSysLockFromIsr();
-            chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-            chSysUnlockFromIsr();
-            break;
-          }
-          u->THR = b;
-        } while (--i);
-      }
-      break;
-    default:
-      (void) u->THR;
-      (void) u->RBR;
-    }
-  }
-}
-
-/**
- * @brief   Attempts a TX FIFO preload.
- */
-static void preload(SerialDriver *sdp) {
-  LPC_UART_TypeDef *u = sdp->uart;
-
-  if (u->LSR & LSR_THRE) {
-    int i = LPC17xx_SERIAL_FIFO_PRELOAD;
-    do {
-      msg_t b = chOQGetI(&sdp->oqueue);
-      if (b < Q_OK) {
-        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-        return;
-      }
-      u->THR = b;
-    } while (--i);
-  }
-  u->IER |= IER_THRE;
-}
-
-/**
- * @brief   Driver SD1 output notification.
- */
-#if LPC17xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD1);
-}
-#endif
-
-/**
- * @brief   Driver SD2 output notification.
- */
-#if LPC17xx_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD2);
-}
-#endif
-
-/**
- * @brief   Driver SD3 output notification.
- */
-#if LPC17xx_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD3);
-}
-#endif
-
-/**
- * @brief   Driver SD4 output notification.
- */
-#if LPC17xx_SERIAL_USE_UART3 || defined(__DOXYGEN__)
-static void notify4(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD4);
-}
-#endif
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 IRQ handler.
- *
- * @isr
- */
-#if LPC17xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector54) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   UART1 IRQ handler.
- *
- * @isr
- */
-#if LPC17xx_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector58) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   UART2 IRQ handler.
- *
- * @isr
- */
-#if LPC17xx_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector5C) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   UART3 IRQ handler.
- *
- * @isr
- */
-#if LPC17xx_SERIAL_USE_UART3 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector60) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if LPC17xx_SERIAL_USE_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = (LPC_UART_TypeDef*) LPC_UART0;
-#endif
-
-#if LPC17xx_SERIAL_USE_UART1
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.uart = (LPC_UART_TypeDef*) LPC_UART1;
-#endif
-
-#if LPC17xx_SERIAL_USE_UART2
-  sdObjectInit(&SD3, NULL, notify3);
-  SD3.uart = (LPC_UART_TypeDef*) LPC_UART2;
-#endif
-
-#if LPC17xx_SERIAL_USE_UART3
-  sdObjectInit(&SD4, NULL, notify4);
-  SD4.uart = (LPC_UART_TypeDef*) LPC_UART3;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if LPC17xx_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SC->PCONP |= (1 << 3);
-      nvicEnableVector(UART0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC17xx_SERIAL_UART0_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC17xx_SERIAL_USE_UART1
-    if (&SD2 == sdp) {
-      LPC_SC->PCONP |= (1 << 4);
-      nvicEnableVector(UART1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC17xx_SERIAL_UART1_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC17xx_SERIAL_USE_UART2
-    if (&SD3 == sdp) {
-      LPC_SC->PCONP |= (1 << 24);
-      nvicEnableVector(UART2_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC17xx_SERIAL_UART2_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC17xx_SERIAL_USE_UART3
-    if (&SD4 == sdp) {
-      LPC_SC->PCONP |= (1 << 25);
-      nvicEnableVector(UART3_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC17xx_SERIAL_UART3_IRQ_PRIORITY));
-    }
-#endif
-  }
-  uart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the UART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    uart_deinit(sdp->uart);
-#if LPC17xx_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SC->PCONP &= ~(1 << 3);
-      nvicDisableVector(UART0_IRQn);
-      return;
-    }
-#endif
-
-#if LPC17xx_SERIAL_USE_UART1
-    if (&SD2 == sdp) {
-      LPC_SC->PCONP &= ~(1 << 4);
-      nvicDisableVector(UART1_IRQn);
-      return;
-    }
-#endif
-
-#if LPC17xx_SERIAL_USE_UART2
-    if (&SD3 == sdp) {
-      LPC_SC->PCONP &= ~(1 << 24);
-      nvicDisableVector(UART2_IRQn);
-      return;
-    }
-#endif
-
-#if LPC17xx_SERIAL_USE_UART3
-    if (&SD4 == sdp) {
-      LPC_SC->PCONP &= ~(1 << 25);
-      nvicDisableVector(UART3_IRQn);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/serial_lld.h b/os/hal/platforms/LPC17xx/serial_lld.h
deleted file mode 100644
index b4ff8cbbd..000000000
--- a/os/hal/platforms/LPC17xx/serial_lld.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/serial_lld.h
- * @brief   LPC17xx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define IIR_SRC_MASK    0x0F
-#define IIR_SRC_NONE    0x01
-#define IIR_SRC_MODEM   0x00
-#define IIR_SRC_TX      0x02
-#define IIR_SRC_RX      0x04
-#define IIR_SRC_ERROR   0x06
-#define IIR_SRC_TIMEOUT 0x0C
-
-#define IER_RBR         1
-#define IER_THRE        2
-#define IER_STATUS      4
-
-#define LCR_WL5         0
-#define LCR_WL6         1
-#define LCR_WL7         2
-#define LCR_WL8         3
-#define LCR_STOP1       0
-#define LCR_STOP2       4
-#define LCR_NOPARITY    0
-#define LCR_PARITYODD   0x08
-#define LCR_PARITYEVEN  0x18
-#define LCR_PARITYONE   0x28
-#define LCR_PARITYZERO  0x38
-#define LCR_BREAK_ON    0x40
-#define LCR_DLAB        0x80
-
-#define FCR_ENABLE      1
-#define FCR_RXRESET     2
-#define FCR_TXRESET     4
-#define FCR_TRIGGER0    0
-#define FCR_TRIGGER1    0x40
-#define FCR_TRIGGER2    0x80
-#define FCR_TRIGGER3    0xC0
-
-#define LSR_RBR_FULL    1
-#define LSR_OVERRUN     2
-#define LSR_PARITY      4
-#define LSR_FRAMING     8
-#define LSR_BREAK       0x10
-#define LSR_THRE        0x20
-#define LSR_TEMT        0x40
-#define LSR_RXFE        0x80
-
-#define TER_ENABLE      0x80
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC17xx_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define LPC17xx_SERIAL_USE_UART0            TRUE
-#endif
-
-/**
- * @brief   UART1 driver enable switch.
- * @details If set to @p TRUE the support for UART1 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC17xx_SERIAL_USE_UART1) || defined(__DOXYGEN__)
-#define LPC17xx_SERIAL_USE_UART1            TRUE
-#endif
-
-/**
- * @brief   UART2 driver enable switch.
- * @details If set to @p TRUE the support for UART2 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC17xx_SERIAL_USE_UART2) || defined(__DOXYGEN__)
-#define LPC17xx_SERIAL_USE_UART2            TRUE
-#endif
-
-/**
- * @brief   UART3 driver enable switch.
- * @details If set to @p TRUE the support for UART3 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC17xx_SERIAL_USE_UART3) || defined(__DOXYGEN__)
-#define LPC17xx_SERIAL_USE_UART3            TRUE
-#endif
-
-/**
- * @brief   FIFO preload parameter.
- * @details Configuration parameter, this values defines how many bytes are
- *          preloaded in the HW transmit FIFO for each interrupt, the maximum
- *          value is 16 the minimum is 1.
- * @note    An high value reduces the number of interrupts generated but can
- *          also increase the worst case interrupt response time because the
- *          preload loops.
- */
-#if !defined(LPC17xx_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__)
-#define LPC17xx_SERIAL_FIFO_PRELOAD         16
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(LPC17xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_SERIAL_UART0_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   UART1 interrupt priority level setting.
- */
-#if !defined(LPC17xx_SERIAL_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_SERIAL_UART1_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   UART2 interrupt priority level setting.
- */
-#if !defined(LPC17xx_SERIAL_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_SERIAL_UART2_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   UART3 interrupt priority level setting.
- */
-#if !defined(LPC17xx_SERIAL_UART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_SERIAL_UART0_IRQ_PRIORITY   3
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-#if (LPC17xx_SERIAL_FIFO_PRELOAD < 1) || (LPC17xx_SERIAL_FIFO_PRELOAD > 16)
-#error "invalid LPC17xx_SERIAL_FIFO_PRELOAD setting"
-#endif
-
-/**
- * @brief   UART0 clock.
- */
-#define  LPC17xx_SERIAL_UART0_PCLK LPC17xx_PCLK
-
-/**
- * @brief   UART1 clock.
- */
-#define  LPC17xx_SERIAL_UART1_PCLK LPC17xx_PCLK
-
-/**
- * @brief   UART2 clock.
- */
-#define  LPC17xx_SERIAL_UART2_PCLK LPC17xx_PCLK
-
-/**
- * @brief   UART3 clock.
- */
-#define  LPC17xx_SERIAL_UART3_PCLK LPC17xx_PCLK
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   LPC17xx Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the LCR register.
-   */
-  uint32_t                  sc_lcr;
-  /**
-   * @brief Initialization value for the FCR register.
-   */
-  uint32_t                  sc_fcr;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  LPC_UART_TypeDef        *uart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC17xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#if LPC17xx_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#if LPC17xx_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-
-#if LPC17xx_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
-extern SerialDriver SD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/spi_lld.c b/os/hal/platforms/LPC17xx/spi_lld.c
deleted file mode 100644
index a388361f1..000000000
--- a/os/hal/platforms/LPC17xx/spi_lld.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/spi_lld.c
- * @brief   LPC17xx low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC17xx_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-#if LPC17xx_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/** @brief SPI2 driver identifier.*/
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Preloads the transmit FIFO.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void ssp_fifo_preload(SPIDriver *spip) {
-  LPC_SSP_TypeDef *ssp = spip->ssp;
-  uint32_t n = spip->txcnt > LPC17xx_SSP_FIFO_DEPTH ?
-               LPC17xx_SSP_FIFO_DEPTH : spip->txcnt;
-
-  while(((ssp->SR & SR_TNF) != 0) && (n > 0)) {
-    if (spip->txptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        const uint16_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-      else {
-        const uint8_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-    }
-    else
-      ssp->DR = 0xFFFFFFFF;
-    n--;
-    spip->txcnt--;
-  }
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void spi_serve_interrupt(SPIDriver *spip) {
-  LPC_SSP_TypeDef *ssp = spip->ssp;
-
-  if ((ssp->MIS & MIS_ROR) != 0) {
-    /* The overflow condition should never happen because priority is given
-       to receive but a hook macro is provided anyway...*/
-    LPC17xx_SPI_SSP_ERROR_HOOK(spip);
-  }
-  ssp->ICR = ICR_RT | ICR_ROR;
-  while ((ssp->SR & SR_RNE) != 0) {
-    if (spip->rxptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        uint16_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-      else {
-        uint8_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-    }
-    else
-      (void)ssp->DR;
-    if (--spip->rxcnt == 0) {
-      chDbgAssert(spip->txcnt == 0,
-                  "spi_serve_interrupt(), #1", "counter out of synch");
-      /* Stops the IRQ sources.*/
-      ssp->IMSC = 0;
-      /* Portable SPI ISR code defined in the high level driver, note, it is
-         a macro.*/
-      _spi_isr_code(spip);
-      return;
-    }
-  }
-  ssp_fifo_preload(spip);
-  if (spip->txcnt == 0)
-    ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC17xx_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/**
- * @brief   SSP0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector78) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC17xx_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/**
- * @brief   SSP1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector7C) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if LPC17xx_SPI_USE_SSP0
-  spiObjectInit(&SPID1);
-  SPID1.ssp = LPC_SSP0;
-#endif /* LPC17xx_SPI_USE_SSP0 */
-
-#if LPC17xx_SPI_USE_SSP1
-  spiObjectInit(&SPID2);
-  SPID2.ssp = LPC_SSP1;
-#endif /* LPC17xx_SPI_USE_SSP0 */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-    /* Clock activation.*/
-#if LPC17xx_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SC->PCONP |= (1UL << 21);
-      LPC_SC->PCLKSEL0 &= (PCLKSEL_MASK << 20);
-      LPC_SC->PCLKSEL0 |= (LPC17xx_SPI_SSP0_PCLKSEL << 20);
-      nvicEnableVector(SSP0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC17xx_SPI_SSP0_IRQ_PRIORITY));
-    }
-#endif
-#if LPC17xx_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_SC->PCONP |= (1UL << 10);
-      LPC_SC->PCLKSEL1 &= (PCLKSEL_MASK << 10);
-      LPC_SC->PCLKSEL1 |= (LPC17xx_SPI_SSP0_PCLKSEL << 10);
-      nvicEnableVector(SSP1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC17xx_SPI_SSP1_IRQ_PRIORITY));
-    }
-#endif
-  }
-  /* Configuration.*/
-  spip->ssp->CR1  = 0;
-  spip->ssp->ICR  = ICR_RT | ICR_ROR;
-  spip->ssp->CR0  = spip->config->cr0;
-  spip->ssp->CPSR = spip->config->cpsr;
-  spip->ssp->CR1  = CR1_SSE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state != SPI_STOP) {
-    spip->ssp->CR1  = 0;
-    spip->ssp->CR0  = 0;
-    spip->ssp->CPSR = 0;
-#if LPC17xx_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_SC->PCONP &= ~(1UL << 21);
-      nvicDisableVector(SSP0_IRQn);
-    }
-#endif
-#if LPC17xx_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_SC->PCONP &= ~(1UL << 10);
-      nvicDisableVector(SSP1_IRQn);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->rxptr = NULL;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->rxptr = NULL;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->ssp->DR = (uint32_t)frame;
-  while ((spip->ssp->SR & SR_RNE) == 0)
-    ;
-  return (uint16_t)spip->ssp->DR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/spi_lld.h b/os/hal/platforms/LPC17xx/spi_lld.h
deleted file mode 100644
index c6d8d161f..000000000
--- a/os/hal/platforms/LPC17xx/spi_lld.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC17xx/spi_lld.h
- * @brief   LPC17xx low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Hardware FIFO depth.
- */
-#define LPC17xx_SSP_FIFO_DEPTH  8
-
-#define CR0_DSSMASK             0x0F
-#define CR0_DSS4BIT             3
-#define CR0_DSS5BIT             4
-#define CR0_DSS6BIT             5
-#define CR0_DSS7BIT             6
-#define CR0_DSS8BIT             7
-#define CR0_DSS9BIT             8
-#define CR0_DSS10BIT            9
-#define CR0_DSS11BIT            0xA
-#define CR0_DSS12BIT            0xB
-#define CR0_DSS13BIT            0xC
-#define CR0_DSS14BIT            0xD
-#define CR0_DSS15BIT            0xE
-#define CR0_DSS16BIT            0xF
-#define CR0_FRFSPI              0
-#define CR0_FRFSSI              0x10
-#define CR0_FRFMW               0x20
-#define CR0_CPOL                0x40
-#define CR0_CPHA                0x80
-#define CR0_CLOCKRATE(n)        ((n) << 8)
-
-#define CR1_LBM                 1
-#define CR1_SSE                 2
-#define CR1_MS                  4
-#define CR1_SOD                 8
-
-#define SR_TFE                  1
-#define SR_TNF                  2
-#define SR_RNE                  4
-#define SR_RFF                  8
-#define SR_BSY                  16
-
-#define IMSC_ROR                1
-#define IMSC_RT                 2
-#define IMSC_RX                 4
-#define IMSC_TX                 8
-
-#define RIS_ROR                 1
-#define RIS_RT                  2
-#define RIS_RX                  4
-#define RIS_TX                  8
-
-#define MIS_ROR                 1
-#define MIS_RT                  2
-#define MIS_RX                  4
-#define MIS_TX                  8
-
-#define ICR_ROR                 1
-#define ICR_RT                  2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for device SSP0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC17xx_SPI_USE_SSP0) || defined(__DOXYGEN__)
-#define LPC17xx_SPI_USE_SSP0                TRUE
-#endif
-
-/**
- * @brief   SPI2 driver enable switch.
- * @details If set to @p TRUE the support for device SSP1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC17xx_SPI_USE_SSP1) || defined(__DOXYGEN__)
-#define LPC17xx_SPI_USE_SSP1                FALSE
-#endif
-
-/**
- * @brief   SSP0 PCLK divider.
- */
-#if !defined(LPC17xx_SPI_SSP0CLKDIV) || defined(__DOXYGEN__)
-#define LPC17xx_SPI_SSP0CLKDIV              1
-#endif
-
-/**
- * @brief   SSP1 PCLK divider.
- */
-#if !defined(LPC17xx_SPI_SSP1CLKDIV) || defined(__DOXYGEN__)
-#define LPC17xx_SPI_SSP1CLKDIV              1
-#endif
-
-/**
- * @brief   SPI0 interrupt priority level setting.
- */
-#if !defined(LPC17xx_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_SPI_SSP0_IRQ_PRIORITY       5
-#endif
-
-/**
- * @brief   SPI1 interrupt priority level setting.
- */
-#if !defined(LPC17xx_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC17xx_SPI_SSP1_IRQ_PRIORITY       5
-#endif
-
-/**
- * @brief   Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(LPC17xx_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__)
-#define LPC17xx_SPI_SSP_ERROR_HOOK(spip)    chSysHalt()
-#endif
-
-#if LPC17xx_SPI_SSP0CLKDIV == 1
-#define LPC17xx_SPI_SSP0_PCLKSEL	PCLKSEL_CCLK
-#elif LPC17xx_SPI_SSP0CLKDIV == 2
-#define LPC17xx_SPI_SSP0_PCLKSEL	PCLKSEL_CCLK_DIV_2
-#elif LPC17xx_SPI_SSP0CLKDIV == 4
-#define LPC17xx_SPI_SSP0_PCLKSEL	PCLKSEL_CCLK_DIV_4
-#elif LPC17xx_SPI_SSP0CLKDIV == 8
-#define LPC17xx_SPI_SSP0_PCLKSEL	PCLKSEL_CCLK_DIV_8
-#else
-#error "Invalid LPC17xx_SPI_SSP0CLKDIV setting (1, 2, 4 or 8 accepted)"
-#endif
-
-#if LPC17xx_SPI_SSP1CLKDIV == 1
-#define LPC17xx_SPI_SSP1_PCLKSEL	PCLKSEL_CCLK
-#elif LPC17xx_SPI_SSP1CLKDIV == 2
-#define LPC17xx_SPI_SSP1_PCLKSEL	PCLKSEL_CCLK_DIV_2
-#elif LPC17xx_SPI_SSP1CLKDIV == 4
-#define LPC17xx_SPI_SSP1_PCLKSEL	PCLKSEL_CCLK_DIV_4
-#elif LPC17xx_SPI_SSP1CLKDIV == 8
-#define LPC17xx_SPI_SSP1_PCLKSEL	PCLKSEL_CCLK_DIV_8
-#else
-#error "Invalid LPC17xx_SPI_SSP1CLKDIV setting (1, 2, 4 or 8 accepted)"
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC17xx_SPI_SSP0CLKDIV != 1) && (LPC17xx_SPI_SSP0CLKDIV != 2) && 	\
-	(LPC17xx_SPI_SSP0CLKDIV != 4) && (LPC17xx_SPI_SSP0CLKDIV != 8)
-#error "Invalid LPC17xx_SPI_SSP0CLKDIV setting (1, 2, 4 or 8 accepted)"
-#endif
-
-#if (LPC17xx_SPI_SSP1CLKDIV != 1) && (LPC17xx_SPI_SSP1CLKDIV != 2) && 	\
-	(LPC17xx_SPI_SSP1CLKDIV != 4) && (LPC17xx_SPI_SSP1CLKDIV != 8)
-#error "invalid LPC17xx_SPI_SSP1CLKDIV setting (1, 2, 4 or 8 accepted)"
-#endif
-
-#if !LPC17xx_SPI_USE_SSP0 && !LPC17xx_SPI_USE_SSP1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-/**
- * @brief   SSP0 clock.
- */
-#define LPC17xx_SPI_SSP0_PCLK                                               \
-  (LPC17xx_CCLK / LPC17xx_SPI_SSP0CLKDIV)
-
-/**
- * @brief   SSP1 clock.
- */
-#define LPC17xx_SPI_SSP1_PCLK                                               \
-  (LPC17xx_CCLK / LPC17xx_SPI_SSP1CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief SSP CR0 initialization data.
-   */
-  uint16_t              cr0;
-  /**
-   * @brief SSP CPSR initialization data.
-   */
-  uint32_t              cpsr;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SSP registers block.
-   */
-  LPC_SSP_TypeDef       *ssp;
-  /**
-   * @brief Number of bytes yet to be received.
-   */
-  uint32_t              rxcnt;
-  /**
-   * @brief Receive pointer or @p NULL.
-   */
-  void                  *rxptr;
-  /**
-   * @brief Number of bytes yet to be transmitted.
-   */
-  uint32_t              txcnt;
-  /**
-   * @brief Transmit pointer or @p NULL.
-   */
-  const void            *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC17xx_SPI_USE_SSP0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if LPC17xx_SPI_USE_SSP1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC17xx/system_LPC17xx.h b/os/hal/platforms/LPC17xx/system_LPC17xx.h
deleted file mode 100644
index e58767e9c..000000000
--- a/os/hal/platforms/LPC17xx/system_LPC17xx.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC17xx.h
- * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Header File
- *           for the NXP LPC17xx Device Series
- * @version  V1.02
- * @date     08. September 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC17xx_H
-#define __SYSTEM_LPC17xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC17xx_H */
diff --git a/os/hal/platforms/LPC214x/hal_lld.c b/os/hal/platforms/LPC214x/hal_lld.c
deleted file mode 100644
index 4f6784e29..000000000
--- a/os/hal/platforms/LPC214x/hal_lld.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/hal_lld.c
- * @brief   LPC214x HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*
- * Non-vectored IRQs handler, the default action can be overridden by
- * redefining the @p LPC214x_NON_VECTORED_IRQ_HOOK() hook macro.
- */
-static CH_IRQ_HANDLER(irq_handler) {
-
-  CH_IRQ_PROLOGUE();
-
-  LPC214x_NON_VECTORED_IRQ_HOOK();
-
-  VICVectAddr = 0;
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  vic_init();
-  VICDefVectAddr = (IOREG32)irq_handler;
-
-}
-
-/**
- * @brief   LPC214x clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void lpc214x_clock_init(void) {
-
-  /*
-   * All peripherals clock disabled by default in order to save power.
-   */
-  PCONP = PCRTC | PCTIM0;
-
-  /*
-   * MAM setup.
-   */
-  MAMTIM = 0x3;                 /* 3 cycles for flash accesses. */
-  MAMCR  = 0x2;                 /* MAM fully enabled. */
-
-  /*
-   * PLL setup for Fosc=12MHz and CCLK=48MHz.
-   * P=2 M=3.
-   */
-  PLL *pll = PLL0Base;
-  pll->PLL_CFG  = 0x23;         /* P and M values. */
-  pll->PLL_CON  = 0x1;          /* Enables the PLL 0. */
-  pll->PLL_FEED = 0xAA;
-  pll->PLL_FEED = 0x55;
-  while (!(pll->PLL_STAT & 0x400))
-    ;                           /* Wait for PLL lock. */
-
-  pll->PLL_CON  = 0x3;          /* Connects the PLL. */
-  pll->PLL_FEED = 0xAA;
-  pll->PLL_FEED = 0x55;
-
-  /*
-   * VPB setup.
-   * PCLK = CCLK / 4.
-   */
-  VPBDIV = VPD_D4;
-}
-
-/** @} */
diff --git a/os/hal/platforms/LPC214x/hal_lld.h b/os/hal/platforms/LPC214x/hal_lld.h
deleted file mode 100644
index d58977e33..000000000
--- a/os/hal/platforms/LPC214x/hal_lld.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/hal_lld.h
- * @brief   LPC214x HAL subsystem low level driver header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "lpc214x.h"
-#include "vic.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME   "LPC214x"
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Default action for the non vectored IRQ handler, nothing.
- */
-#if !defined(LPC214x_NON_VECTORED_IRQ_HOOK) || defined(__DOXYGEN__)
-#define LPC214x_NON_VECTORED_IRQ_HOOK()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void lpc214x_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC214x/lpc214x.h b/os/hal/platforms/LPC214x/lpc214x.h
deleted file mode 100644
index 4aa4dd96b..000000000
--- a/os/hal/platforms/LPC214x/lpc214x.h
+++ /dev/null
@@ -1,523 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file lpc214x.h
- * @brief LPC214x register definitions.
- */
-
-#ifndef _LPC214X_H_
-#define _LPC214X_H_
-
-typedef volatile uint8_t IOREG8;
-typedef volatile uint16_t IOREG16;
-typedef volatile uint32_t IOREG32;
-
-/*
- * System.
- */
-#define MEMMAP                  (*((IOREG32 *)0xE01FC040))
-#define PCON                    (*((IOREG32 *)0xE01FC0C0))
-#define PCONP                   (*((IOREG32 *)0xE01FC0C4))
-#define VPBDIV                  (*((IOREG32 *)0xE01FC100))
-#define EXTINT                  (*((IOREG32 *)0xE01FC140))
-#define INTWAKE                 (*((IOREG32 *)0xE01FC144))
-#define EXTMODE                 (*((IOREG32 *)0xE01FC148))
-#define EXTPOLAR                (*((IOREG32 *)0xE01FC14C))
-#define RSID                    (*((IOREG32 *)0xE01FC180))
-#define CSPR                    (*((IOREG32 *)0xE01FC184))
-#define SCS                     (*((IOREG32 *)0xE01FC1A0))
-
-#define VPD_D4                  0
-#define VPD_D1                  1
-#define VPD_D2                  2
-#define VPD_RESERVED            3
-
-#define PCTIM0                  (1 << 1)
-#define PCTIM1                  (1 << 2)
-#define PCUART0                 (1 << 3)
-#define PCUART1                 (1 << 4)
-#define PCPWM0                  (1 << 5)
-#define PCI2C0                  (1 << 7)
-#define PCSPI0                  (1 << 8)
-#define PCRTC                   (1 << 9)
-#define PCSPI1                  (1 << 10)
-#define PCAD0                   (1 << 12)
-#define PCI2C1                  (1 << 19)
-#define PCAD1                   (1 << 20)
-#define PCUSB                   (1 << 31)
-#define PCALL                   (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \
-                                 PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \
-                                 PCAD0 | PCI2C1 | PCAD1 | PCUSB)
-
-#define EINT0                   1
-#define EINT1                   2
-#define EINT2                   4
-#define EINT3                   8
-
-#define EXTWAKE0                1
-#define EXTWAKE1                2
-#define EXTWAKE2                4
-#define EXTWAKE3                8
-#define USBWAKE                 0x20
-#define BODWAKE                 0x4000
-#define RTCWAKE                 0x8000
-
-#define EXTMODE0                1
-#define EXTMODE1                2
-#define EXTMODE2                4
-#define EXTMODE3                8
-
-#define EXTPOLAR0               1
-#define EXTPOLAR1               2
-#define EXTPOLAR2               4
-#define EXTPOLAR3               8
-
-typedef struct {
-  IOREG32       PLL_CON;
-  IOREG32       PLL_CFG;
-  IOREG32       PLL_STAT;
-  IOREG32       PLL_FEED;
-} PLL;
-
-#define PLL0Base                ((PLL *)0xE01FC080)
-#define PLL1Base                ((PLL *)0xE01FC0A0)
-#define PLL0CON                 (PLL0Base->PLL_CON)
-#define PLL0CFG                 (PLL0Base->PLL_CFG)
-#define PLL0STAT                (PLL0Base->PLL_STAT)
-#define PLL0FEED                (PLL0Base->PLL_FEED)
-#define PLL1CON                 (PLL1Base->PLL_CON)
-#define PLL1CFG                 (PLL1Base->PLL_CFG)
-#define PLL1STAT                (PLL1Base->PLL_STAT)
-#define PLL1FEED                (PLL1Base->PLL_FEED)
-
-/*
- * Pins.
- */
-typedef struct {
-  IOREG32       PS_SEL0;
-  IOREG32       PS_SEL1;
-  IOREG32       _dummy[3];
-  IOREG32       PS_SEL2;
-} PS;
-
-#define PSBase                  ((PS *)0xE002C000)
-#define PINSEL0                 (PSBase->PS_SEL0)
-#define PINSEL1                 (PSBase->PS_SEL1)
-#define PINSEL2                 (PSBase->PS_SEL2)
-
-/*
- * VIC
- */
-#define SOURCE_WDT              0
-#define SOURCE_ARMCore0         2
-#define SOURCE_ARMCore1         3
-#define SOURCE_Timer0           4
-#define SOURCE_Timer1           5
-#define SOURCE_UART0            6
-#define SOURCE_UART1            7
-#define SOURCE_PWM0             8
-#define SOURCE_I2C0             9
-#define SOURCE_SPI0             10
-#define SOURCE_SPI1             11
-#define SOURCE_PLL              12
-#define SOURCE_RTC              13
-#define SOURCE_EINT0            14
-#define SOURCE_EINT1            15
-#define SOURCE_EINT2            16
-#define SOURCE_EINT3            17
-#define SOURCE_ADC0             18
-#define SOURCE_I2C1             19
-#define SOURCE_BOD              20
-#define SOURCE_ADC1             21
-#define SOURCE_USB              22
-
-#define INTMASK(n)              (1 << (n))
-#define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \
-                    INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \
-                    INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \
-                    INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \
-                    INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \
-                    INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \
-                    INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \
-                    INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \
-                    INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \
-                    INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \
-                    INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB))
-
-typedef struct {
-  IOREG32       VIC_IRQStatus;
-  IOREG32       VIC_FIQStatus;
-  IOREG32       VIC_RawIntr;
-  IOREG32       VIC_IntSelect;
-  IOREG32       VIC_IntEnable;
-  IOREG32       VIC_IntEnClear;
-  IOREG32       VIC_SoftInt;
-  IOREG32       VIC_SoftIntClear;
-  IOREG32       VIC_Protection;
-  IOREG32       unused1[3];
-  IOREG32       VIC_VectAddr;
-  IOREG32       VIC_DefVectAddr;
-  IOREG32       unused2[50];
-  IOREG32       VIC_VectAddrs[16];
-  IOREG32       unused3[48];
-  IOREG32       VIC_VectCntls[16];
-} VIC;
-
-#define VICBase                 ((VIC *)0xFFFFF000)
-#define VICVectorsBase          ((IOREG32 *)0xFFFFF100)
-#define VICControlsBase         ((IOREG32 *)0xFFFFF200)
-
-#define VICIRQStatus            (VICBase->VIC_IRQStatus)
-#define VICFIQStatus            (VICBase->VIC_FIQStatus)
-#define VICRawIntr              (VICBase->VIC_RawIntr)
-#define VICIntSelect            (VICBase->VIC_IntSelect)
-#define VICIntEnable            (VICBase->VIC_IntEnable)
-#define VICIntEnClear           (VICBase->VIC_IntEnClear)
-#define VICSoftInt              (VICBase->VIC_SoftInt)
-#define VICSoftIntClear         (VICBase->VIC_SoftIntClear)
-#define VICProtection           (VICBase->VIC_Protection)
-#define VICVectAddr             (VICBase->VIC_VectAddr)
-#define VICDefVectAddr          (VICBase->VIC_DefVectAddr)
-
-#define VICVectAddrs(n)         (VICBase->VIC_VectAddrs[n])
-#define VICVectCntls(n)         (VICBase->VIC_VectCntls[n])
-
-/*
- * MAM.
- */
-typedef struct {
-  IOREG32       MAM_Control;
-  IOREG32       MAM_Timing;
-} MAM;
-
-#define MAMBase                 ((MAM *)0xE01FC000)
-#define MAMCR                   (MAMBase->MAM_Control)
-#define MAMTIM                  (MAMBase->MAM_Timing)
-
-/*
- * GPIO - FIO.
- */
-typedef struct {
-  IOREG32       IO_PIN;
-  IOREG32       IO_SET;
-  IOREG32       IO_DIR;
-  IOREG32       IO_CLR;
-} GPIO;
-
-#define GPIO0Base                ((GPIO *)0xE0028000)
-#define IO0PIN                   (GPIO0Base->IO_PIN)
-#define IO0SET                   (GPIO0Base->IO_SET)
-#define IO0DIR                   (GPIO0Base->IO_DIR)
-#define IO0CLR                   (GPIO0Base->IO_CLR)
-
-#define GPIO1Base                ((GPIO *)0xE0028010)
-#define IO1PIN                   (GPIO1Base->IO_PIN)
-#define IO1SET                   (GPIO1Base->IO_SET)
-#define IO1DIR                   (GPIO1Base->IO_DIR)
-#define IO1CLR                   (GPIO1Base->IO_CLR)
-
-typedef struct {
-  IOREG32       FIO_DIR;
-  IOREG32       unused1;
-  IOREG32       unused2;
-  IOREG32       unused3;
-  IOREG32       FIO_MASK;
-  IOREG32       FIO_PIN;
-  IOREG32       FIO_SET;
-  IOREG32       FIO_CLR;
-} FIO;
-
-#define FIO0Base                ((FIO *)0x3FFFC000)
-#define FIO0DIR                 (FIO0Base->FIO_DIR)
-#define FIO0MASK                (FIO0Base->FIO_MASK)
-#define FIO0PIN                 (FIO0Base->FIO_PIN)
-#define FIO0SET                 (FIO0Base->FIO_SET)
-#define FIO0CLR                 (FIO0Base->FIO_CLR)
-
-#define FIO1Base                ((FIO *)0x3FFFC020)
-#define FIO1DIR                 (FIO1Base->FIO_DIR)
-#define FIO1MASK                (FIO1Base->FIO_MASK)
-#define FIO1PIN                 (FIO1Base->FIO_PIN)
-#define FIO1SET                 (FIO1Base->FIO_SET)
-#define FIO1CLR                 (FIO1Base->FIO_CLR)
-
-/*
- * UART.
- */
-typedef struct {
-  union {
-    IOREG32     UART_RBR;
-    IOREG32     UART_THR;
-    IOREG32     UART_DLL;
-  };
-  union {
-    IOREG32     UART_IER;
-    IOREG32     UART_DLM;
-  };
-  union {
-    IOREG32     UART_IIR;
-    IOREG32     UART_FCR;
-  };
-  IOREG32       UART_LCR;
-  IOREG32       UART_MCR;
-  IOREG32       UART_LSR;
-  IOREG32       unused18;
-  IOREG32       UART_SCR;
-  IOREG32       UART_ACR;
-  IOREG32       unused24;
-  IOREG32       UART_FDR;
-  IOREG32       unused2C;
-  IOREG32       UART_TER;
-} UART;
-
-#define U0Base                  ((UART *)0xE000C000)
-#define U0RBR                   (U0Base->UART_RBR)
-#define U0THR                   (U0Base->UART_THR)
-#define U0DLL                   (U0Base->UART_DLL)
-#define U0IER                   (U0Base->UART_IER)
-#define U0DLM                   (U0Base->UART_DLM)
-#define U0IIR                   (U0Base->UART_IIR)
-#define U0FCR                   (U0Base->UART_FCR)
-#define U0LCR                   (U0Base->UART_LCR)
-#define U0LSR                   (U0Base->UART_LSR)
-#define U0SCR                   (U0Base->UART_SCR)
-#define U0ACR                   (U0Base->UART_ACR)
-#define U0FDR                   (U0Base->UART_FDR)
-#define U0TER                   (U0Base->UART_TER)
-
-#define U1Base                  ((UART *)0xE0010000)
-#define U1RBR                   (U1Base->UART_RBR)
-#define U1THR                   (U1Base->UART_THR)
-#define U1DLL                   (U1Base->UART_DLL)
-#define U1IER                   (U1Base->UART_IER)
-#define U1DLM                   (U1Base->UART_DLM)
-#define U1IIR                   (U1Base->UART_IIR)
-#define U1FCR                   (U1Base->UART_FCR)
-#define U1MCR                   (U1Base->UART_MCR)
-#define U1LCR                   (U1Base->UART_LCR)
-#define U1LSR                   (U1Base->UART_LSR)
-#define U1SCR                   (U1Base->UART_SCR)
-#define U1ACR                   (U1Base->UART_ACR)
-#define U1FDR                   (U1Base->UART_FDR)
-#define U1TER                   (U1Base->UART_TER)
-
-#define IIR_SRC_MASK    0x0F
-#define IIR_SRC_NONE    0x01
-#define IIR_SRC_TX      0x02
-#define IIR_SRC_RX      0x04
-#define IIR_SRC_ERROR   0x06
-#define IIR_SRC_TIMEOUT 0x0C
-
-#define IER_RBR         1
-#define IER_THRE        2
-#define IER_STATUS      4
-
-#define IIR_INT_PENDING 1
-
-#define LCR_WL5         0
-#define LCR_WL6         1
-#define LCR_WL7         2
-#define LCR_WL8         3
-#define LCR_STOP1       0
-#define LCR_STOP2       4
-#define LCR_NOPARITY    0
-#define LCR_PARITYODD   0x08
-#define LCR_PARITYEVEN  0x18
-#define LCR_PARITYONE   0x28
-#define LCR_PARITYZERO  0x38
-#define LCR_BREAK_ON    0x40
-#define LCR_DLAB        0x80
-
-#define FCR_ENABLE      1
-#define FCR_RXRESET     2
-#define FCR_TXRESET     4
-#define FCR_TRIGGER0    0
-#define FCR_TRIGGER1    0x40
-#define FCR_TRIGGER2    0x80
-#define FCR_TRIGGER3    0xC0
-
-#define LSR_RBR_FULL    1
-#define LSR_OVERRUN     2
-#define LSR_PARITY      4
-#define LSR_FRAMING     8
-#define LSR_BREAK       0x10
-#define LSR_THRE        0x20
-#define LSR_TEMT        0x40
-#define LSR_RXFE        0x80
-
-#define TER_ENABLE      0x80
-
-/*
- * SSP.
- */
-typedef struct {
-  IOREG32       SSP_CR0;
-  IOREG32       SSP_CR1;
-  IOREG32       SSP_DR;
-  IOREG32       SSP_SR;
-  IOREG32       SSP_CPSR;
-  IOREG32       SSP_IMSC;
-  IOREG32       SSP_RIS;
-  IOREG32       SSP_MIS;
-  IOREG32       SSP_ICR;
-} SSP;
-
-#define SSPBase                 ((SSP *)0xE0068000)
-#define SSPCR0                  (SSPBase->SSP_CR0)
-#define SSPCR1                  (SSPBase->SSP_CR1)
-#define SSPDR                   (SSPBase->SSP_DR)
-#define SSPSR                   (SSPBase->SSP_SR)
-#define SSPCPSR                 (SSPBase->SSP_CPSR)
-#define SSPIMSC                 (SSPBase->SSP_IMSC)
-#define SSPRIS                  (SSPBase->SSP_RIS)
-#define SSPMIS                  (SSPBase->SSP_MIS)
-#define SSPICR                  (SSPBase->SSP_ICR)
-
-#define CR0_DSSMASK             0x0F
-#define CR0_DSS4BIT             3
-#define CR0_DSS5BIT             4
-#define CR0_DSS6BIT             5
-#define CR0_DSS7BIT             6
-#define CR0_DSS8BIT             7
-#define CR0_DSS9BIT             8
-#define CR0_DSS10BIT            9
-#define CR0_DSS11BIT            0xA
-#define CR0_DSS12BIT            0xB
-#define CR0_DSS13BIT            0xC
-#define CR0_DSS14BIT            0xD
-#define CR0_DSS15BIT            0xE
-#define CR0_DSS16BIT            0xF
-#define CR0_FRFSPI              0
-#define CR0_FRFSSI              0x10
-#define CR0_FRFMW               0x20
-#define CR0_CPOL                0x40
-#define CR0_CPHA                0x80
-#define CR0_CLOCKRATE(n)        ((n) << 8)
-
-#define CR1_LBM                 1
-#define CR1_SSE                 2
-#define CR1_MS                  4
-#define CR1_SOD                 8
-
-#define SR_TFE                  1
-#define SR_TNF                  2
-#define SR_RNE                  4
-#define SR_RFF                  8
-#define SR_BSY                  0x10
-
-#define IMSC_ROR                1
-#define IMSC_RT                 2
-#define IMSC_RX                 4
-#define IMSC_TX                 8
-
-#define RIS_ROR                 1
-#define RIS_RT                  2
-#define RIS_RX                  4
-#define RIS_TX                  8
-
-#define MIS_ROR                 1
-#define MIS_RT                  2
-#define MIS_RX                  4
-#define MIS_TX                  8
-
-#define ICR_ROR                 1
-#define ICR_RT                  2
-
-/*
- * Timers/Counters.
- */
-typedef struct {
-  IOREG32       TC_IR;
-  IOREG32       TC_TCR;
-  IOREG32       TC_TC;
-  IOREG32       TC_PR;
-  IOREG32       TC_PC;
-  IOREG32       TC_MCR;
-  IOREG32       TC_MR0;
-  IOREG32       TC_MR1;
-  IOREG32       TC_MR2;
-  IOREG32       TC_MR3;
-  IOREG32       TC_CCR;
-  IOREG32       TC_CR0;
-  IOREG32       TC_CR1;
-  IOREG32       TC_CR2;
-  IOREG32       TC_CR3;
-  IOREG32       TC_EMR;
-  IOREG32       TC_CTCR;
-} TC;
-
-#define T0Base                  ((TC *)0xE0004000)
-#define T0IR                    (T0Base->TC_IR)
-#define T0TCR                   (T0Base->TC_TCR)
-#define T0TC                    (T0Base->TC_TC)
-#define T0PR                    (T0Base->TC_PR)
-#define T0PC                    (T0Base->TC_PC)
-#define T0MCR                   (T0Base->TC_MCR)
-#define T0MR0                   (T0Base->TC_MR0)
-#define T0MR1                   (T0Base->TC_MR1)
-#define T0MR2                   (T0Base->TC_MR2)
-#define T0MR3                   (T0Base->TC_MR3)
-#define T0CCR                   (T0Base->TC_CCR)
-#define T0CR0                   (T0Base->TC_CR0)
-#define T0CR1                   (T0Base->TC_CR1)
-#define T0CR2                   (T0Base->TC_CR2)
-#define T0CR3                   (T0Base->TC_CR3)
-#define T0EMR                   (T0Base->TC_EMR)
-#define T0CTCR                  (T0Base->TC_CTCR)
-
-#define T1Base                  ((TC *)0xE0008000)
-#define T1IR                    (T1Base->TC_IR)
-#define T1TCR                   (T1Base->TC_TCR)
-#define T1TC                    (T1Base->TC_TC)
-#define T1PR                    (T1Base->TC_PR)
-#define T1PC                    (T1Base->TC_PC)
-#define T1MCR                   (T1Base->TC_MCR)
-#define T1MR0                   (T1Base->TC_MR0)
-#define T1MR1                   (T1Base->TC_MR1)
-#define T1MR2                   (T1Base->TC_MR2)
-#define T1MR3                   (T1Base->TC_MR3)
-#define T1CCR                   (T1Base->TC_CCR)
-#define T1CR0                   (T1Base->TC_CR0)
-#define T1CR1                   (T1Base->TC_CR1)
-#define T1CR2                   (T1Base->TC_CR2)
-#define T1CR3                   (T1Base->TC_CR3)
-#define T1EMR                   (T1Base->TC_EMR)
-#define T1CTCR                  (T1Base->TC_CTCR)
-
-/*
- * Watchdog.
- */
-typedef struct {
-  IOREG32       WD_MOD;
-  IOREG32       WD_TC;
-  IOREG32       WD_FEED;
-  IOREG32       WD_TV;
-} WD;
-
-#define WDBase                  ((WD *)0xE0000000)
-#define WDMOD                   (WDBase->WD_MOD)
-#define WDTC                    (WDBase->WD_TC)
-#define WDFEED                  (WDBase->WD_FEED)
-#define WDTV                    (WDBase->WD_TV)
-
-/*
- * DAC.
- */
-#define DACR                    (*((IOREG32 *)0xE006C000))
-
-#endif /* _LPC214X_H_ */
-
diff --git a/os/hal/platforms/LPC214x/pal_lld.c b/os/hal/platforms/LPC214x/pal_lld.c
deleted file mode 100644
index 1d0b45ad4..000000000
--- a/os/hal/platforms/LPC214x/pal_lld.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/pal_lld.c
- * @brief   LPC214x FIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   LPC214x I/O ports configuration.
- * @details FIO units and PINSEL registers initialization.
- *
- * @param[in] config    the LPC214x ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  /* Enables the access through the fast registers.*/
-  SCS = 3;
-
-  /* I/O pads initial assignment, device drivers may change this setup at a
-   * later time.*/
-  PINSEL0 = config->pinsel0;
-  PINSEL1 = config->pinsel1;
-  PINSEL2 = config->pinsel2;
-
-  /* I/O pads direction initial setting.*/
-  FIO0Base->FIO_MASK = 0;
-  FIO0Base->FIO_PIN = config->P0Data.pin;
-  FIO0Base->FIO_DIR = config->P0Data.dir;
-  FIO1Base->FIO_MASK = 0;
-  FIO1Base->FIO_PIN = config->P1Data.pin;
-  FIO1Base->FIO_DIR = config->P1Data.dir;
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    This function does not alter the @p PINSELx registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    port->FIO_DIR &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    port->FIO_PIN |= mask;
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->FIO_DIR |= mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC214x/pal_lld.h b/os/hal/platforms/LPC214x/pal_lld.h
deleted file mode 100644
index 6ffcabdf5..000000000
--- a/os/hal/platforms/LPC214x/pal_lld.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/pal_lld.h
- * @brief   LPC214x FIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   FIO port setup info.
- */
-typedef struct {
-  /** Initial value for FIO_PIN register.*/
-  uint32_t      pin;
-  /** Initial value for FIO_DIR register.*/
-  uint32_t      dir;
-} lpc214x_fio_setup_t;
-
-/**
- * @brief   LPC214x FIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialize the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-  /** @brief PINSEL0 initial value.*/
-  uint32_t              pinsel0;
-  /** @brief PINSEL1 initial value.*/
-  uint32_t              pinsel1;
-  /** @brief PINSEL2 initial value.*/
-  uint32_t              pinsel2;
-  /** @brief Port 0 setup data.*/
-  lpc214x_fio_setup_t   P0Data;
-  /** @brief Port 1 setup data.*/
-  lpc214x_fio_setup_t   P1Data;
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef FIO * ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   FIO port 0 identifier.
- */
-#define IOPORT1        FIO0Base
-
-/**
- * @brief   FIO port 1 identifier.
- */
-#define IOPORT2        FIO1Base
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   FIO subsystem initialization.
- * @details Enables the access through the fast registers.
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads an I/O port.
- * @details This function is implemented by reading the FIO PIN register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->FIO_PIN)
-
-/**
- * @brief   Reads the output latch.
- * @details This function is implemented by reading the FIO SET register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->FIO_SET)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- * @details This function is implemented by writing the FIO PIN register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->FIO_PIN = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @details This function is implemented by writing the FIO SET register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->FIO_SET = (bits))
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @details This function is implemented by writing the FIO CLR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) ((port)->FIO_CLR = (bits))
-
-/**
- * @brief   Writes a value on an I/O bus.
- * @details This function is implemented by writing the FIO PIN and MASK
- *          registers, the implementation is not atomic because the multiple
- *          accesses.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask, a logical AND is performed on the
- *                      output data
- * @param[in] offset    the group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group
- *                      width are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                    \
-  ((port)->FIO_MASK = ~((mask) << (offset)),                            \
-   (port)->FIO_PIN = (bits) << (offset),                                \
-   (port)->FIO_MASK = 0)
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    This function does not alter the @p PINSELx registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
-
-/**
- * @brief   FIO port setup.
- * @details This function programs the pins direction within a port.
- *
- * @notapi
- */
-#define pal_lld_lpc214x_set_direction(port, dir) ((port)->FIO_DIR = (dir))
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC214x/platform.dox b/os/hal/platforms/LPC214x/platform.dox
deleted file mode 100644
index e5189558a..000000000
--- a/os/hal/platforms/LPC214x/platform.dox
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup LPC214x LPC214x Drivers
- * @details This section describes all the supported drivers on the LPC214x
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup LPC214x_HAL LPC214x Initialization Support
- * @details The LPC214x HAL support is responsible for system initialization.
- *
- * @section lpc214x_hal_1 Supported HW resources
- * - PLL0.
- * - MAM.
- * - VPBDIV.
- * .
- * @section lpc214x_hal_2 LPC214x HAL driver implementation features
- * - Clock tree initialization.
- * - Clock source selection.
- * - MAM initialization.
- * .
- * @ingroup LPC214x
- */
-
-/**
- * @defgroup LPC214x_PAL LPC214x PAL Support
- * @details The LPC214x PAL driver uses the FIO peripherals.
- *
- * @section lpc214x_pal_1 Supported HW resources
- * - FIO0.
- * - FIO1.
- * .
- * @section lpc214x_pal_2 LPC214x PAL driver implementation features
- * - 32 bits wide ports.
- * - Atomic set/reset functions.
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section lpc214x_pal_3 Supported PAL setup modes
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_ANALOG (same as @p PAL_MODE_INPUT).
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section lpc214x_pal_4 Suboptimal behavior
- * Some FIO features are less than optimal:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * .
- * @ingroup LPC214x
- */
-
-/**
- * @defgroup LPC214x_SERIAL LPC214x Serial Support
- * @details The LPC214x Serial driver uses the UART peripherals in a
- *          buffered, interrupt driven, implementation. The serial driver
- *          also takes advantage of the LPC214x UARTs deep hardware buffers.
- *
- * @section lpc214x_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - UART0.
- * - UART1.
- * .
- * @section lpc214x_serial_2 LPC214x Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Fully interrupt driven.
- * - Programmable interrupt priority levels for each UART.
- * - Takes advantage of the input and output FIFOs.
- * .
- * @ingroup LPC214x
- */
-
-/**
- * @defgroup LPC214x_SPI LPC214x SPI Support
- * @details The SPI driver supports the LPC214x SSP peripheral in an interrupt
- *          driven implementation.
- * @note    Being the SPI a fast peripheral, much care must be taken to
- *          not saturate the CPU bandwidth with an excessive IRQ rate. The
- *          maximum transfer bit rate is likely limited by the IRQ
- *          handling.
- *
- * @section lpc214x_spi_1 Supported HW resources
- * - SSP (SPI0).
- * .
- * @section lpc214x_spi_2 LPC214x SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority level.
- * .
- * @ingroup LPC214x
- */
-
-/**
- * @defgroup LPC214x_VIC LPC214x VIC Support
- * @details This VIC helper driver is used by the other drivers in order to
- *          access the shared VIC resources in a consistent way.
- *
- * @ingroup LPC214x
- */
diff --git a/os/hal/platforms/LPC214x/platform.mk b/os/hal/platforms/LPC214x/platform.mk
deleted file mode 100644
index 0253e47f7..000000000
--- a/os/hal/platforms/LPC214x/platform.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-# List of all the LPC214x platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC214x/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC214x/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC214x/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC214x/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC214x/vic.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC214x
diff --git a/os/hal/platforms/LPC214x/serial_lld.c b/os/hal/platforms/LPC214x/serial_lld.c
deleted file mode 100644
index f552b094d..000000000
--- a/os/hal/platforms/LPC214x/serial_lld.c
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/serial_lld.c
- * @brief   LPC214x low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if USE_LPC214x_UART0 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-#if USE_LPC214x_UART1 || defined(__DOXYGEN__)
-/** @brief UART1 serial driver identifier.*/
-SerialDriver SD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief  Driver default configuration.*/
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  LCR_WL8 | LCR_STOP1 | LCR_NOPARITY,
-  FCR_TRIGGER0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   UART initialization.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
-  UART *u = sdp->uart;
-
-  uint32_t div = PCLK / (config->sc_speed << 4);
-  u->UART_LCR = config->sc_lcr | LCR_DLAB;
-  u->UART_DLL = div;
-  u->UART_DLM = div >> 8;
-  u->UART_LCR = config->sc_lcr;
-  u->UART_FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr;
-  u->UART_ACR = 0;
-  u->UART_FDR = 0x10;
-  u->UART_TER = TER_ENABLE;
-  u->UART_IER = IER_RBR | IER_STATUS;
-}
-
-/**
- * @brief   UART de-initialization.
- *
- * @param[in] u         pointer to an UART I/O block
- */
-static void uart_deinit(UART *u) {
-
-  u->UART_LCR = LCR_DLAB;
-  u->UART_DLL = 1;
-  u->UART_DLM = 0;
-  u->UART_LCR = 0;
-  u->UART_FDR = 0x10;
-  u->UART_IER = 0;
-  u->UART_FCR = FCR_RXRESET | FCR_TXRESET;
-  u->UART_ACR = 0;
-  u->UART_TER = TER_ENABLE;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] err       UART LSR register value
- */
-static void set_error(SerialDriver *sdp, IOREG32 err) {
-  flagsmask_t sts = 0;
-
-  if (err & LSR_OVERRUN)
-    sts |= SD_OVERRUN_ERROR;
-  if (err & LSR_PARITY)
-    sts |= SD_PARITY_ERROR;
-  if (err & LSR_FRAMING)
-    sts |= SD_FRAMING_ERROR;
-  if (err & LSR_BREAK)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-/**
- * @brief   Common IRQ handler.
- * @note    Tries hard to clear all the pending interrupt sources, we dont want
- *          to go through the whole ISR and have another interrupt soon after.
- *
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  UART *u = sdp->uart;
-
-  while (TRUE) {
-    switch (u->UART_IIR & IIR_SRC_MASK) {
-    case IIR_SRC_NONE:
-      return;
-    case IIR_SRC_ERROR:
-      set_error(sdp, u->UART_LSR);
-      break;
-    case IIR_SRC_TIMEOUT:
-    case IIR_SRC_RX:
-      chSysLockFromIsr();
-      if (chIQIsEmptyI(&sdp->iqueue))
-        chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
-      chSysUnlockFromIsr();
-      while (u->UART_LSR & LSR_RBR_FULL) {
-        chSysLockFromIsr();
-        if (chIQPutI(&sdp->iqueue, u->UART_RBR) < Q_OK)
-          chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
-        chSysUnlockFromIsr();
-      }
-      break;
-    case IIR_SRC_TX:
-      {
-        int i = LPC214x_UART_FIFO_PRELOAD;
-        do {
-          msg_t b;
-
-          chSysLockFromIsr();
-          b = chOQGetI(&sdp->oqueue);
-          chSysUnlockFromIsr();
-          if (b < Q_OK) {
-            u->UART_IER &= ~IER_THRE;
-            chSysLockFromIsr();
-            chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-            chSysUnlockFromIsr();
-            break;
-          }
-          u->UART_THR = b;
-        } while (--i);
-      }
-      break;
-    default:
-      (void) u->UART_THR;
-      (void) u->UART_RBR;
-    }
-  }
-}
-
-/**
- * @brief   Attempts a TX FIFO preload.
- */
-static void preload(SerialDriver *sdp) {
-  UART *u = sdp->uart;
-
-  if (u->UART_LSR & LSR_THRE) {
-    int i = LPC214x_UART_FIFO_PRELOAD;
-    do {
-      msg_t b = chOQGetI(&sdp->oqueue);
-      if (b < Q_OK) {
-        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-        return;
-      }
-      u->UART_THR = b;
-    } while (--i);
-  }
-  u->UART_IER |= IER_THRE;
-}
-
-/**
- * @brief   Driver SD1 output notification.
- */
-#if USE_LPC214x_UART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD1);
-}
-#endif
-
-/**
- * @brief   Driver SD2 output notification.
- */
-#if USE_LPC214x_UART1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD2);
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 IRQ handler.
- *
- * @isr
- */
-#if USE_LPC214x_UART0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(UART0IrqHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-  VICVectAddr = 0;
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   UART1 IRQ handler.
- *
- * @isr
- */
-#if USE_LPC214x_UART1 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(UART1IrqHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD2);
-  VICVectAddr = 0;
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if USE_LPC214x_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = U0Base;
-  SetVICVector(UART0IrqHandler, LPC214x_UART0_PRIORITY, SOURCE_UART0);
-#endif
-#if USE_LPC214x_UART1
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.uart = U1Base;
-  SetVICVector(UART1IrqHandler, LPC214x_UART1_PRIORITY, SOURCE_UART1);
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if USE_LPC214x_UART0
-    if (&SD1 == sdp) {
-      PCONP = (PCONP & PCALL) | PCUART0;
-      VICIntEnable = INTMASK(SOURCE_UART0);
-    }
-#endif
-#if USE_LPC214x_UART1
-    if (&SD2 == sdp) {
-      PCONP = (PCONP & PCALL) | PCUART1;
-      VICIntEnable = INTMASK(SOURCE_UART1);
-    }
-#endif
-  }
-  uart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the UART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    uart_deinit(sdp->uart);
-#if USE_LPC214x_UART0
-    if (&SD1 == sdp) {
-      PCONP = (PCONP & PCALL) & ~PCUART0;
-      VICIntEnClear = INTMASK(SOURCE_UART0);
-      return;
-    }
-#endif
-#if USE_LPC214x_UART1
-    if (&SD2 == sdp) {
-      PCONP = (PCONP & PCALL) & ~PCUART1;
-      VICIntEnClear = INTMASK(SOURCE_UART1);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC214x/serial_lld.h b/os/hal/platforms/LPC214x/serial_lld.h
deleted file mode 100644
index b57957580..000000000
--- a/os/hal/platforms/LPC214x/serial_lld.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/serial_lld.h
- * @brief   LPC214x low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(USE_LPC214x_UART0) || defined(__DOXYGEN__)
-#define USE_LPC214x_UART0           TRUE
-#endif
-
-/**
- * @brief   UART1 driver enable switch.
- * @details If set to @p TRUE the support for UART1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_LPC214x_UART1) || defined(__DOXYGEN__)
-#define USE_LPC214x_UART1           TRUE
-#endif
-
-/**
- * @brief   FIFO preload parameter.
- * @details Configuration parameter, this values defines how many bytes are
- *          preloaded in the HW transmit FIFO for each interrupt, the maximum
- *          value is 16 the minimum is 1.
- * @note    An high value reduces the number of interrupts generated but can
- *          also increase the worst case interrupt response time because the
- *          preload loops.
- */
-#if !defined(LPC214x_UART_FIFO_PRELOAD) || defined(__DOXYGEN__)
-#define LPC214x_UART_FIFO_PRELOAD   16
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(LPC214x_UART0_PRIORITY) || defined(__DOXYGEN__)
-#define LPC214x_UART0_PRIORITY      1
-#endif
-
-/**
- * @brief   UART1 interrupt priority level setting.
- */
-#if !defined(LPC214x_UART1_PRIORITY) || defined(__DOXYGEN__)
-#define LPC214x_UART1_PRIORITY      2
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC214x_UART_FIFO_PRELOAD < 1) || (LPC214x_UART_FIFO_PRELOAD > 16)
-#error "invalid LPC214x_UART_FIFO_PRELOAD setting"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   LPC214x Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the LCR register.
-   */
-  uint32_t                  sc_lcr;
-  /**
-   * @brief Initialization value for the FCR register.
-   */
-  uint32_t                  sc_fcr;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  UART                      *uart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if USE_LPC214x_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if USE_LPC214x_UART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC214x/spi_lld.c b/os/hal/platforms/LPC214x/spi_lld.c
deleted file mode 100644
index b5e7f864f..000000000
--- a/os/hal/platforms/LPC214x/spi_lld.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/spi_lld.c
- * @brief   LPC214x low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC214x_SPI_USE_SSP || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Preloads the transmit FIFO.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void ssp_fifo_preload(SPIDriver *spip) {
-  SSP *ssp = spip->ssp;
-  uint32_t n = spip->txcnt > LPC214x_SSP_FIFO_DEPTH ?
-               LPC214x_SSP_FIFO_DEPTH : spip->txcnt;
-
-  while(((ssp->SSP_SR & SR_TNF) != 0) && (n > 0)) {
-    if (spip->txptr != NULL) {
-      if ((ssp->SSP_CR0 & CR0_DSSMASK) > CR0_DSS8BIT)
-        ssp->SSP_DR = *(uint16_t *)spip->txptr++;
-      else
-        ssp->SSP_DR = *(uint8_t *)spip->txptr++;
-    }
-    else
-      ssp->SSP_DR = 0xFFFFFFFF;
-    n--;
-    spip->txcnt--;
-  }
-}
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void serve_interrupt(SPIDriver *spip) {
-  SSP *ssp = spip->ssp;
-
-  if ((ssp->SSP_MIS & MIS_ROR) != 0) {
-    /* The overflow condition should never happen because priority is given
-       to receive but a hook macro is provided anyway...*/
-    LPC214x_SPI_SSP_ERROR_HOOK();
-  }
-  ssp->SSP_ICR = ICR_RT | ICR_ROR;
-  while ((ssp->SSP_SR & SR_RNE) != 0) {
-    if (spip->rxptr != NULL) {
-      if ((ssp->SSP_CR0 & CR0_DSSMASK) > CR0_DSS8BIT)
-        *(uint16_t *)spip->rxptr++ = ssp->SSP_DR;
-      else
-        *(uint8_t *)spip->rxptr++ = ssp->SSP_DR;
-    }
-    else
-      (void)ssp->SSP_DR;
-    if (--spip->rxcnt == 0) {
-      chDbgAssert(spip->txcnt == 0,
-                  "spi_serve_interrupt(), #1", "counter out of synch");
-      /* Stops the IRQ sources.*/
-      ssp->SSP_IMSC = 0;
-      /* Portable SPI ISR code defined in the high level driver, note, it is
-         a macro.*/
-      _spi_isr_code(spip);
-      return;
-    }
-  }
-  ssp_fifo_preload(spip);
-  if (spip->txcnt == 0)
-    ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_RX;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC214x_SPI_USE_SSP || defined(__DOXYGEN__)
-/**
- * @brief   SPI1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPI1IrqHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SPID1);
-  VICVectAddr = 0;
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if LPC214x_SPI_USE_SSP
-  spiObjectInit(&SPID1);
-  SPID1.ssp = SSPBase;
-  SetVICVector(SPI1IrqHandler, LPC214x_SPI_SSP_IRQ_PRIORITY, SOURCE_SPI1);
-#endif
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-    /* Clock activation.*/
-#if LPC214x_SPI_USE_SSP
-    if (&SPID1 == spip) {
-      PCONP = (PCONP & PCALL) | PCSPI1;
-      VICIntEnable = INTMASK(SOURCE_SPI1);
-    }
-#endif
-  }
-  /* Configuration.*/
-  spip->ssp->SSP_CR1  = 0;
-  /* Emptying the receive FIFO, it happens to not be empty while debugging.*/
-  while (spip->ssp->SSP_SR & SR_RNE)
-    (void) spip->ssp->SSP_DR;
-  spip->ssp->SSP_ICR  = ICR_RT | ICR_ROR;
-  spip->ssp->SSP_CR0  = spip->config->cr0;
-  spip->ssp->SSP_CPSR = spip->config->cpsr;
-  spip->ssp->SSP_CR1  = CR1_SSE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state != SPI_STOP) {
-    spip->ssp->SSP_CR1  = 0;
-    spip->ssp->SSP_CR0  = 0;
-    spip->ssp->SSP_CPSR = 0;
-#if LPC214x_SPI_USE_SSP
-    if (&SPID1 == spip) {
-      PCONP = (PCONP & PCALL) & ~PCSPI1;
-      VICIntEnClear = INTMASK(SOURCE_SPI1);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->rxptr = NULL;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->rxptr = NULL;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->SSP_IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->ssp->SSP_DR = (uint32_t)frame;
-  while ((spip->ssp->SSP_SR & SR_RNE) == 0)
-    ;
-  return (uint16_t)spip->ssp->SSP_DR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/LPC214x/spi_lld.h b/os/hal/platforms/LPC214x/spi_lld.h
deleted file mode 100644
index 9def6f16a..000000000
--- a/os/hal/platforms/LPC214x/spi_lld.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/spi_lld.h
- * @brief   LPC214x low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Hardware FIFO depth.
- */
-#define LPC214x_SSP_FIFO_DEPTH          8
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for SSP is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC214x_SPI_USE_SSP) || defined(__DOXYGEN__)
-#define LPC214x_SPI_USE_SSP             TRUE
-#endif
-
-/**
- * @brief   SSP interrupt priority level setting.
- */
-#if !defined(LPC214x_SPI_SSP_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC214x_SPI_SSP_IRQ_PRIORITY    4
-#endif
-
-/**
- * @brief   Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(LPC214x_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__)
-#define LPC214x_SPI_SSP_ERROR_HOOK()    chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !LPC214x_SPI_USE_SSP
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief SSP CR0 initialization data.
-   */
-  uint16_t              cr0;
-  /**
-   * @brief SSP CPSR initialization data.
-   */
-  uint32_t              cpsr;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SSP registers block.
-   */
-  SSP                   *ssp;
-  /**
-   * @brief Number of bytes yet to be received.
-   */
-  uint32_t              rxcnt;
-  /**
-   * @brief Receive pointer or @p NULL.
-   */
-  void                  *rxptr;
-  /**
-   * @brief Number of bytes yet to be transmitted.
-   */
-  uint32_t              txcnt;
-  /**
-   * @brief Transmit pointer or @p NULL.
-   */
-  const void            *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC214x_SPI_USE_SSP && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC214x/vic.c b/os/hal/platforms/LPC214x/vic.c
deleted file mode 100644
index 8c64f44ce..000000000
--- a/os/hal/platforms/LPC214x/vic.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/vic.c
- * @brief   LPC214x VIC peripheral support code.
- *
- * @addtogroup LPC214x_VIC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/**
- * @brief   VIC Initialization.
- * @note    Better reset everything in the VIC, it is a HUGE source of trouble.
- *
- * @notapi
- */
-void vic_init(void) {
-  int i;
-
-  VIC *vic = VICBase;
-  vic->VIC_IntSelect = 0;               /* All sources assigned to IRQ. */
-  vic->VIC_SoftIntClear = ALLINTMASK;   /* No interrupts enforced */
-  vic->VIC_IntEnClear = ALLINTMASK;     /* All sources disabled. */
-  for (i = 0; i < 16; i++) {
-    vic->VIC_VectCntls[i] = 0;
-    vic->VIC_VectAddrs[i] = 0;
-    vic->VIC_VectAddr = 0;
-  }
-}
-
-/**
- * @brief   Initializes a VIC vector.
- * @details Set a vector for an interrupt source and enables it.
- *
- * @param[in] handler   the pointer to the IRQ service routine
- * @param[in] vector    the vector number
- * @param[in] source    the IRQ source to be associated to the vector
- *
- * @api
- */
-void SetVICVector(void *handler, int vector, int source) {
-
-  VIC *vicp = VICBase;
-  vicp->VIC_VectAddrs[vector] = (IOREG32)handler;
-  vicp->VIC_VectCntls[vector] = (IOREG32)(source | 0x20);
-}
-
-/** @} */
diff --git a/os/hal/platforms/LPC214x/vic.h b/os/hal/platforms/LPC214x/vic.h
deleted file mode 100644
index 99c97b936..000000000
--- a/os/hal/platforms/LPC214x/vic.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC214x/vic.h
- * @brief   LPC214x VIC peripheral support header.
- *
- * @addtogroup LPC214x_VIC
- * @{
- */
-
-#ifndef _VIC_H_
-#define _VIC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void vic_init(void);
-  void SetVICVector(void *handler, int vector, int source);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _VIC_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/LPC43xx.h b/os/hal/platforms/LPC43xx/LPC43xx.h
deleted file mode 100644
index 99a9e8e8d..000000000
--- a/os/hal/platforms/LPC43xx/LPC43xx.h
+++ /dev/null
@@ -1,34895 +0,0 @@
-
-/****************************************************************************************************//**
- * @file     LPC43xx.h
- *
- * @status   RELEASE
- *
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
- *           default LPC43xx Device Series
- *
- * @version  V5
- * @date     9. December 2011
- *
- * @note     Generated with SVDConv V2.6 Build 6c  on Friday, 09.12.2011 13:56:08
- *
- *           from CMSIS SVD File 'LPC43xxv5.xml' Version 5,
- *           created on Friday, 09.12.2011 21:56:03, last modified on Friday, 09.12.2011 21:56:04
- *
- *******************************************************************************************************/
-
-
-
-/** @addtogroup (null)
-  * @{
-  */
-
-/** @addtogroup LPC43xx
-  * @{
-  */
-
-#ifndef __LPC43XX_H__
-#define __LPC43XX_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-
-
-/********************************************
-** Start of section using anonymous unions **
-*********************************************/
-
-#if defined(__ARMCC_VERSION)
-  #pragma push
-  #pragma anon_unions
-#elif defined(__CWCC__)
-  #pragma push
-  #pragma cpp_extensions on
-#elif defined(__GNUC__)
-  /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
-  #pragma push
-  #pragma language=extended
-#else
-  #error Not supported compiler type
-#endif
-
-
- /* Interrupt Number Definition */
-
-typedef enum {
-// -------------------------  Cortex-M4 Processor Exceptions Numbers  -----------------------------
-  Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
-  NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
-  HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
-  MemoryManagement_IRQn             = -12,  /*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
-  BusFault_IRQn                     = -11,  /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
-  UsageFault_IRQn                   = -10,  /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
-  SVCall_IRQn                       =  -5,  /*!<  11  System Service Call via SVC instruction */
-  DebugMonitor_IRQn                 =  -4,  /*!<  12  Debug Monitor                    */
-  PendSV_IRQn                       =  -2,  /*!<  14  Pendable request for system service */
-  SysTick_IRQn                      =  -1,  /*!<  15  System Tick Timer                */
-// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
-  DAC_IRQn                          =   0,  /*!<   0  DAC                              */
-  M0CORE_IRQn                  		=   1,  /*!<   1  M0a                              */
-  DMA_IRQn                          =   2,  /*!<   2  DMA                              */
-  RESERVED1_IRQn                    =   3,  /*!<   3  EZH/EDM                          */
-  RESERVED2_IRQn                    =   4,
-  ETHERNET_IRQn                     =   5,  /*!<   5  ETHERNET                         */
-  SDIO_IRQn                         =   6,  /*!<   6  SDIO                             */
-  LCD_IRQn                          =   7,  /*!<   7  LCD                              */
-  USB0_IRQn                         =   8,  /*!<   8  USB0                             */
-  USB1_IRQn                         =   9,  /*!<   9  USB1                             */
-  SCT_IRQn                          =  10,  /*!<  10  SCT                              */
-  RITIMER_IRQn                      =  11,  /*!<  11  RITIMER                          */
-  TIMER0_IRQn                       =  12,  /*!<  12  TIMER0                           */
-  TIMER1_IRQn                       =  13,  /*!<  13  TIMER1                           */
-  TIMER2_IRQn                       =  14,  /*!<  14  TIMER2                           */
-  TIMER3_IRQn                       =  15,  /*!<  15  TIMER3                           */
-  MCPWM_IRQn                        =  16,  /*!<  16  MCPWM                            */
-  ADC0_IRQn                         =  17,  /*!<  17  ADC0                             */
-  I2C0_IRQn                         =  18,  /*!<  18  I2C0                             */
-  I2C1_IRQn                         =  19,  /*!<  19  I2C1                             */
-  SPI_INT_IRQn                      =  20,  /*!<  20  SPI_INT                          */
-  ADC1_IRQn                         =  21,  /*!<  21  ADC1                             */
-  SSP0_IRQn                         =  22,  /*!<  22  SSP0                             */
-  SSP1_IRQn                         =  23,  /*!<  23  SSP1                             */
-  USART0_IRQn                       =  24,  /*!<  24  USART0                           */
-  UART1_IRQn                        =  25,  /*!<  25  UART1                            */
-  USART2_IRQn                       =  26,  /*!<  26  USART2                           */
-  USART3_IRQn                       =  27,  /*!<  27  USART3                           */
-  I2S0_IRQn                         =  28,  /*!<  28  I2S0                             */
-  I2S1_IRQn                         =  29,  /*!<  29  I2S1                             */
-  RESERVED4_IRQn                    =  30,
-  SGPIO_IINT_IRQn                   =  31,  /*!<  31  SGPIO_IINT                       */
-  PIN_INT0_IRQn                     =  32,  /*!<  32  PIN_INT0                         */
-  PIN_INT1_IRQn                     =  33,  /*!<  33  PIN_INT1                         */
-  PIN_INT2_IRQn                     =  34,  /*!<  34  PIN_INT2                         */
-  PIN_INT3_IRQn                     =  35,  /*!<  35  PIN_INT3                         */
-  PIN_INT4_IRQn                     =  36,  /*!<  36  PIN_INT4                         */
-  PIN_INT5_IRQn                     =  37,  /*!<  37  PIN_INT5                         */
-  PIN_INT6_IRQn                     =  38,  /*!<  38  PIN_INT6                         */
-  PIN_INT7_IRQn                     =  39,  /*!<  39  PIN_INT7                         */
-  GINT0_IRQn                        =  40,  /*!<  40  GINT0                            */
-  GINT1_IRQn                        =  41,  /*!<  41  GINT1                            */
-  EVENTROUTER_IRQn                  =  42,  /*!<  42  EVENTROUTER                      */
-  C_CAN1_IRQn                       =  43,  /*!<  43  C_CAN1                           */
-  RESERVED6_IRQn                    =  44,
-  RESERVED7_IRQn                    =  45,  /*!<  45  VADC                             */
-  ATIMER_IRQn                       =  46,  /*!<  46  ATIMER                           */
-  RTC_IRQn                          =  47,  /*!<  47  RTC                              */
-  RESERVED8_IRQn                    =  48,
-  WWDT_IRQn                         =  49,  /*!<  49  WWDT                             */
-  RESERVED9_IRQn                    =  50,
-  C_CAN0_IRQn                       =  51,  /*!<  51  C_CAN0                           */
-  QEI_IRQn                          =  52,  /*!<  52  QEI                              */
-
-// -------------------------  Cortex-M0 Processor Exceptions Numbers  -----------------------------
-  M0_Reset_IRQn                     = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
-  M0_NonMaskableInt_IRQn            = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
-  M0_HardFault_IRQn                 = -13,  /*!<   3  Hard Fault, all classes of Fault */
-  M0_SVCall_IRQn                    =  -5,  /*!<  11  System Service Call via SVC instruction */
-  M0_DebugMonitor_IRQn              =  -4,  /*!<  12  Debug Monitor                    */
-  M0_PendSV_IRQn                    =  -2,  /*!<  14  Pendable request for system service */
-  M0_SysTick_IRQn                   =  -1,  /*!<  15  System Tick Timer                */
-// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
-  M0_RTC_IRQn                       =   0,  /*!<   0  RTC                              */
-  M0_M4CORE_IRQn					=   1,  /*!<   1  M4                               */
-  M0_DMA_IRQn                       =   2,  /*!<   2  DMA                              */
-  M0_RESERVED0_IRQn					=   3,
-  M0_RESERVED1_IRQn					=   4,
-  M0_ETHERNET_IRQn                  =   5,  /*!<   5  ETHERNET                         */
-  M0_SDIO_IRQn                      =   6,  /*!<   6  SDIO                             */
-  M0_LCD_IRQn                       =   7,  /*!<   7  LCD                              */
-  M0_USB0_IRQn                      =   8,  /*!<   8  USB0                             */
-  M0_USB1_IRQn                      =   9,  /*!<   9  USB1                             */
-  M0_SCT_IRQn                       =  10,  /*!<  10  SCT                              */
-  M0_RITIMER_OR_WWDT_IRQn           =  11,  /*!<  11  RITIMER_OR_WWDT                  */
-  M0_TIMER0_IRQn                    =  12,  /*!<  12  TIMER0                           */
-  M0_GINT1_IRQn                     =  13,  /*!<  13  GINT1                            */
-  M0_TIMER3_IRQn                    =  15,  /*!<  15  TIMER3                           */
-  M0_RESERVED2_IRQn					=  14,
-  M0_RESERVED3_IRQn					=  15,
-  M0_MCPWM_IRQn                     =  16,  /*!<  16  MCPWM                            */
-  M0_ADC0_IRQn                      =  17,  /*!<  17  ADC0                             */
-  M0_I2C0_OR_I2C1_IRQn              =  18,  /*!<  18  I2C0_OR_I2C1                     */
-  M0_SGPIO_IRQn                     =  19,  /*!<  19  SGPIO                            */
-  M0_SPI_OR_DAC_IRQn                =  20,  /*!<  20  SPI_OR_DAC                       */
-  M0_ADC1_IRQn                      =  21,  /*!<  21  ADC1                             */
-  M0_SSP0_OR_SSP1_IRQn              =  22,  /*!<  22  SSP0_OR_SSP1                     */
-  M0_EVENTROUTER_IRQn               =  23,  /*!<  23  EVENTROUTER                      */
-  M0_USART0_IRQn                    =  24,  /*!<  24  USART0                           */
-  M0_UART1_IRQn                     =  25,  /*!<  25  UART1                            */
-  M0_USART2_OR_C_CAN1_IRQn          =  26,  /*!<  26  USART2_OR_C_CAN1                 */
-  M0_USART3_IRQn                    =  27,  /*!<  27  USART3                           */
-  M0_I2S0_OR_I2S1_OR_QEI_IRQn       =  28,  /*!<  28  I2S0_OR_I2S1_OR_QEI              */
-  M0_C_CAN0_IRQn                    =  29   /*!<  29  C_CAN0                           */
-} IRQn_Type;
-
- /* Event Router Input (ERI) Number Definitions */
-typedef enum {
-  WAKEUP0_ERIn                      = 0,
-  WAKEUP1_ERIn                      = 1,
-  WAKEUP2_ERIn                      = 2,
-  WAKEUP3_ERIn                      = 3,
-  ATIMER_ERIn                       = 4,
-  RTC_ERIn                          = 5,
-  BOD1_ERIn                         = 6,  /* Bod trip 1 */
-  WWDT_ERIn                         = 7,
-  ETH_ERIn                          = 8,
-  USB0_ERIn                         = 9,
-  USB1_ERIn                         = 10,
-  SDIO_ERIn                         = 11,
-  CAN_ERIn                          = 12, /* CAN0/1 or'ed */
-  TIM2_ERIn                         = 13,
-  TIM6_ERIn                         = 14,
-  QEI_ERIn                          = 15,
-  TIM14_ERIn                        = 16,
-  RESERVED0_ERIn                    = 17, /* M0s */
-  RESERVED1_ERIn                    = 18, /* M3/M4 */
-  RESET_ERIn                        = 19
-}ERIn_Type;
-
-/** @addtogroup Configuration_of_CMSIS
-  * @{
-  */
-
-/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M4 Processor and Core Peripherals */
-
-#ifdef CORE_M4
-#define __CM4_REV              0x0000       /*!< Cortex-M4 Core Revision               */
-#define __MPU_PRESENT             1         /*!< MPU present or not                    */
-#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig    	0         	/*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT             1         /*!< FPU present or not                    */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include <core_cm4.h>                       /*!< Cortex-M4 processor and core peripherals */
-#else
-#ifdef CORE_M0
-#define __MPU_PRESENT             0         /*!< MPU present or not                    */
-#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig    	0         	/*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT             0         /*!< FPU present or not                    */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include <core_cm0.h>                       /*!< Cortex-M4 processor and core peripherals */
-#else
-#error Please #define CORE_M0 or CORE_M4
-#endif
-#endif
-
-/** @} */ /* End of group Configuration_of_CMSIS */
-#include "system_LPC43xx.h"                 /*!< LPC43xx System                        */
-
-/** @addtogroup Device_Peripheral_Registers
-  * @{
-  */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          SCT                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7  (SCT)
-  */
-
-#define CONFIG_SCT_nEV   (16)            /* Number of events */
-#define CONFIG_SCT_nRG   (16)            /* Number of match/compare registers */
-#define CONFIG_SCT_nOU   (16)            /* Number of outputs */
-
-typedef struct
-{
-    __IO  uint32_t CONFIG;              /* 0x000 Configuration Register */
-    union {
-        __IO uint32_t CTRL_U;           /* 0x004 Control Register */
-        struct {
-            __IO uint16_t CTRL_L;       /* 0x004 low control register */
-            __IO uint16_t CTRL_H;       /* 0x006 high control register */
-        };
-    };
-    __IO uint16_t LIMIT_L;              /* 0x008 limit register for counter L */
-    __IO uint16_t LIMIT_H;              /* 0x00A limit register for counter H */
-    __IO uint16_t HALT_L;               /* 0x00C halt register for counter L */
-    __IO uint16_t HALT_H;               /* 0x00E halt register for counter H */
-    __IO uint16_t STOP_L;               /* 0x010 stop register for counter L */
-    __IO uint16_t STOP_H;               /* 0x012 stop register for counter H */
-    __IO uint16_t START_L;              /* 0x014 start register for counter L */
-    __IO uint16_t START_H;              /* 0x016 start register for counter H */
-         uint32_t RESERVED1[10];        /* 0x018-0x03C reserved */
-    union {
-        __IO uint32_t COUNT_U;          /* 0x040 counter register */
-        struct {
-            __IO uint16_t COUNT_L;      /* 0x040 counter register for counter L */
-            __IO uint16_t COUNT_H;      /* 0x042 counter register for counter H */
-        };
-    };
-    __IO uint16_t STATE_L;              /* 0x044 state register for counter L */
-    __IO uint16_t STATE_H;              /* 0x046 state register for counter H */
-    __I  uint32_t INPUT;                /* 0x048 input register */
-    __IO uint16_t REGMODE_L;            /* 0x04C match - capture registers mode register L */
-    __IO uint16_t REGMODE_H;            /* 0x04E match - capture registers mode register H */
-    __IO uint32_t OUTPUT;               /* 0x050 output register */
-    __IO uint32_t OUTPUTDIRCTRL;        /* 0x054 Output counter direction Control Register */
-    __IO uint32_t RES;                  /* 0x058 conflict resolution register */
-    __IO uint32_t DMA0REQUEST;          /* 0x05C DMA0 Request Register */
-    __IO uint32_t DMA1REQUEST;          /* 0x060 DMA1 Request Register */
-         uint32_t RESERVED2[35];        /* 0x064-0x0EC reserved */
-    __IO uint32_t EVEN;                 /* 0x0F0 event enable register */
-    __IO uint32_t EVFLAG;               /* 0x0F4 event flag register */
-    __IO uint32_t CONEN;                /* 0x0F8 conflict enable register */
-    __IO uint32_t CONFLAG;              /* 0x0FC conflict flag register */
-
-    union {
-        __IO union {                    /* 0x100-... Match / Capture value */
-            uint32_t U;                 /*       SCTMATCH[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTMATCH[i].L  Access to L value */
-                uint16_t H;             /*       SCTMATCH[i].H  Access to H value */
-            };
-        } MATCH[CONFIG_SCT_nRG];
-        __I union {
-            uint32_t U;                 /*       SCTCAP[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTCAP[i].L  Access to H value */
-                uint16_t H;             /*       SCTCAP[i].H  Access to H value */
-            };
-        } CAP[CONFIG_SCT_nRG];
-    };
-
-         uint32_t RESERVED3[32-CONFIG_SCT_nRG];      /* ...-0x17C reserved */
-
-    union {
-        __IO uint16_t MATCH_L[CONFIG_SCT_nRG];       /* 0x180-... Match Value L counter */
-        __I  uint16_t CAP_L[CONFIG_SCT_nRG];         /* 0x180-... Capture Value L counter */
-    };
-         uint16_t RESERVED4[32-CONFIG_SCT_nRG];      /* ...-0x1BE reserved */
-    union {
-        __IO uint16_t MATCH_H[CONFIG_SCT_nRG];       /* 0x1C0-... Match Value H counter */
-        __I  uint16_t CAP_H[CONFIG_SCT_nRG];         /* 0x1C0-... Capture Value H counter */
-    };
-         uint16_t RESERVED5[32-CONFIG_SCT_nRG];      /* ...-0x1FE reserved */
-
-    union {
-        __IO union {                    /* 0x200-... Match Reload / Capture Control value */
-            uint32_t U;                 /*       SCTMATCHREL[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTMATCHREL[i].L  Access to L value */
-                uint16_t H;             /*       SCTMATCHREL[i].H  Access to H value */
-            };
-        } MATCHREL[CONFIG_SCT_nRG];
-        __IO union {
-            uint32_t U;                 /*       SCTCAPCTRL[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTCAPCTRL[i].L  Access to H value */
-                uint16_t H;             /*       SCTCAPCTRL[i].H  Access to H value */
-            };
-        } CAPCTRL[CONFIG_SCT_nRG];
-    };
-
-         uint32_t RESERVED6[32-CONFIG_SCT_nRG];      /* ...-0x27C reserved */
-
-    union {
-        __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];    /* 0x280-... Match Reload value L counter */
-        __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];     /* 0x280-... Capture Control value L counter */
-    };
-         uint16_t RESERVED7[32-CONFIG_SCT_nRG];      /* ...-0x2BE reserved */
-    union {
-        __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];    /* 0x2C0-... Match Reload value H counter */
-        __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];     /* 0x2C0-... Capture Control value H counter */
-    };
-         uint16_t RESERVED8[32-CONFIG_SCT_nRG];      /* ...-0x2FE reserved */
-
-    __IO struct {                       /* 0x300-0x3FC  SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
-        uint32_t STATE;                 /* Event State Register */
-        uint32_t CTRL;                  /* Event Control Register */
-    } EVENT[CONFIG_SCT_nEV];
-
-         uint32_t RESERVED9[128-2*CONFIG_SCT_nEV];   /* ...-0x4FC reserved */
-
-    __IO struct {                       /* 0x500-0x57C  SCTOUT[i].SET / SCTOUT[i].CLR */
-        uint32_t SET;                   /* Output n Set Register */
-        uint32_t CLR;                   /* Output n Clear Register */
-    } OUT[CONFIG_SCT_nOU];
-
-         uint32_t RESERVED10[191-2*CONFIG_SCT_nOU];  /* ...-0x7F8 reserved */
-
-    __I  uint32_t MODULECONTENT;        /* 0x7FC Module Content */
-
-} LPC_SCT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         GPDMA                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (GPDMA)
-  */
-
-typedef struct {                            /*!< (@ 0x40002000) GPDMA Structure        */
-  __I  uint32_t  INTSTAT;                   /*!< (@ 0x40002000) DMA Interrupt Status Register */
-  __I  uint32_t  INTTCSTAT;                 /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */
-  __O  uint32_t  INTTCCLEAR;                /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */
-  __I  uint32_t  INTERRSTAT;                /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */
-  __O  uint32_t  INTERRCLR;                 /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */
-  __I  uint32_t  RAWINTTCSTAT;              /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */
-  __I  uint32_t  RAWINTERRSTAT;             /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */
-  __I  uint32_t  ENBLDCHNS;                 /*!< (@ 0x4000201C) DMA Enabled Channel Register */
-  __IO uint32_t  SOFTBREQ;                  /*!< (@ 0x40002020) DMA Software Burst Request Register */
-  __IO uint32_t  SOFTSREQ;                  /*!< (@ 0x40002024) DMA Software Single Request Register */
-  __IO uint32_t  SOFTLBREQ;                 /*!< (@ 0x40002028) DMA Software Last Burst Request Register */
-  __IO uint32_t  SOFTLSREQ;                 /*!< (@ 0x4000202C) DMA Software Last Single Request Register */
-  __IO uint32_t  CONFIG;                    /*!< (@ 0x40002030) DMA Configuration Register */
-  __IO uint32_t  SYNC;                      /*!< (@ 0x40002034) DMA Synchronization Register */
-  __I  uint32_t  RESERVED0[50];
-  __IO uint32_t  C0SRCADDR;                 /*!< (@ 0x40002100) DMA Channel Source Address Register */
-  __IO uint32_t  C0DESTADDR;                /*!< (@ 0x40002104) DMA Channel Destination Address Register */
-  __IO uint32_t  C0LLI;                     /*!< (@ 0x40002108) DMA Channel Linked List Item Register */
-  __IO uint32_t  C0CONTROL;                 /*!< (@ 0x4000210C) DMA Channel Control Register */
-  __IO uint32_t  C0CONFIG;                  /*!< (@ 0x40002110) DMA Channel Configuration Register */
-  __I  uint32_t  RESERVED1[3];
-  __IO uint32_t  C1SRCADDR;                 /*!< (@ 0x40002120) DMA Channel Source Address Register */
-  __IO uint32_t  C1DESTADDR;                /*!< (@ 0x40002124) DMA Channel Destination Address Register */
-  __IO uint32_t  C1LLI;                     /*!< (@ 0x40002128) DMA Channel Linked List Item Register */
-  __IO uint32_t  C1CONTROL;                 /*!< (@ 0x4000212C) DMA Channel Control Register */
-  __IO uint32_t  C1CONFIG;                  /*!< (@ 0x40002130) DMA Channel Configuration Register */
-  __I  uint32_t  RESERVED2[3];
-  __IO uint32_t  C2SRCADDR;                 /*!< (@ 0x40002140) DMA Channel Source Address Register */
-  __IO uint32_t  C2DESTADDR;                /*!< (@ 0x40002144) DMA Channel Destination Address Register */
-  __IO uint32_t  C2LLI;                     /*!< (@ 0x40002148) DMA Channel Linked List Item Register */
-  __IO uint32_t  C2CONTROL;                 /*!< (@ 0x4000214C) DMA Channel Control Register */
-  __IO uint32_t  C2CONFIG;                  /*!< (@ 0x40002150) DMA Channel Configuration Register */
-  __I  uint32_t  RESERVED3[3];
-  __IO uint32_t  C3SRCADDR;                 /*!< (@ 0x40002160) DMA Channel Source Address Register */
-  __IO uint32_t  C3DESTADDR;                /*!< (@ 0x40002164) DMA Channel Destination Address Register */
-  __IO uint32_t  C3LLI;                     /*!< (@ 0x40002168) DMA Channel Linked List Item Register */
-  __IO uint32_t  C3CONTROL;                 /*!< (@ 0x4000216C) DMA Channel Control Register */
-  __IO uint32_t  C3CONFIG;                  /*!< (@ 0x40002170) DMA Channel Configuration Register */
-  __I  uint32_t  RESERVED4[3];
-  __IO uint32_t  C4SRCADDR;                 /*!< (@ 0x40002180) DMA Channel Source Address Register */
-  __IO uint32_t  C4DESTADDR;                /*!< (@ 0x40002184) DMA Channel Destination Address Register */
-  __IO uint32_t  C4LLI;                     /*!< (@ 0x40002188) DMA Channel Linked List Item Register */
-  __IO uint32_t  C4CONTROL;                 /*!< (@ 0x4000218C) DMA Channel Control Register */
-  __IO uint32_t  C4CONFIG;                  /*!< (@ 0x40002190) DMA Channel Configuration Register */
-  __I  uint32_t  RESERVED5[3];
-  __IO uint32_t  C5SRCADDR;                 /*!< (@ 0x400021A0) DMA Channel Source Address Register */
-  __IO uint32_t  C5DESTADDR;                /*!< (@ 0x400021A4) DMA Channel Destination Address Register */
-  __IO uint32_t  C5LLI;                     /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */
-  __IO uint32_t  C5CONTROL;                 /*!< (@ 0x400021AC) DMA Channel Control Register */
-  __IO uint32_t  C5CONFIG;                  /*!< (@ 0x400021B0) DMA Channel Configuration Register */
-  __I  uint32_t  RESERVED6[3];
-  __IO uint32_t  C6SRCADDR;                 /*!< (@ 0x400021C0) DMA Channel Source Address Register */
-  __IO uint32_t  C6DESTADDR;                /*!< (@ 0x400021C4) DMA Channel Destination Address Register */
-  __IO uint32_t  C6LLI;                     /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */
-  __IO uint32_t  C6CONTROL;                 /*!< (@ 0x400021CC) DMA Channel Control Register */
-  __IO uint32_t  C6CONFIG;                  /*!< (@ 0x400021D0) DMA Channel Configuration Register */
-  __I  uint32_t  RESERVED7[3];
-  __IO uint32_t  C7SRCADDR;                 /*!< (@ 0x400021E0) DMA Channel Source Address Register */
-  __IO uint32_t  C7DESTADDR;                /*!< (@ 0x400021E4) DMA Channel Destination Address Register */
-  __IO uint32_t  C7LLI;                     /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */
-  __IO uint32_t  C7CONTROL;                 /*!< (@ 0x400021EC) DMA Channel Control Register */
-  __IO uint32_t  C7CONFIG;                  /*!< (@ 0x400021F0) DMA Channel Configuration Register */
-} LPC_GPDMA_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         SDMMC                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a  (SDMMC)
-  */
-
-typedef struct {                            /*!< (@ 0x40004000) SDMMC Structure        */
-  __IO uint32_t  CTRL;                      /*!< (@ 0x40004000) Control Register       */
-  __IO uint32_t  PWREN;                     /*!< (@ 0x40004004) Power Enable Register  */
-  __IO uint32_t  CLKDIV;                    /*!< (@ 0x40004008) Clock Divider Register */
-  __IO uint32_t  CLKSRC;                    /*!< (@ 0x4000400C) SD Clock Source Register */
-  __IO uint32_t  CLKENA;                    /*!< (@ 0x40004010) Clock Enable Register  */
-  __IO uint32_t  TMOUT;                     /*!< (@ 0x40004014) Timeout Register       */
-  __IO uint32_t  CTYPE;                     /*!< (@ 0x40004018) Card Type Register     */
-  __IO uint32_t  BLKSIZ;                    /*!< (@ 0x4000401C) Block Size Register    */
-  __IO uint32_t  BYTCNT;                    /*!< (@ 0x40004020) Byte Count Register    */
-  __IO uint32_t  INTMASK;                   /*!< (@ 0x40004024) Interrupt Mask Register */
-  __IO uint32_t  CMDARG;                    /*!< (@ 0x40004028) Command Argument Register */
-  __IO uint32_t  CMD;                       /*!< (@ 0x4000402C) Command Register       */
-  __I  uint32_t  RESP0;                     /*!< (@ 0x40004030) Response Register 0    */
-  __I  uint32_t  RESP1;                     /*!< (@ 0x40004034) Response Register 1    */
-  __I  uint32_t  RESP2;                     /*!< (@ 0x40004038) Response Register 2    */
-  __I  uint32_t  RESP3;                     /*!< (@ 0x4000403C) Response Register 3    */
-  __I  uint32_t  MINTSTS;                   /*!< (@ 0x40004040) Masked Interrupt Status Register */
-  __IO uint32_t  RINTSTS;                   /*!< (@ 0x40004044) Raw Interrupt Status Register */
-  __I  uint32_t  STATUS;                    /*!< (@ 0x40004048) Status Register        */
-  __IO uint32_t  FIFOTH;                    /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */
-  __I  uint32_t  CDETECT;                   /*!< (@ 0x40004050) Card Detect Register   */
-  __I  uint32_t  WRTPRT;                    /*!< (@ 0x40004054) Write Protect Register */
-  __IO uint32_t  GPIO;                      /*!< (@ 0x40004058) General Purpose Input/Output Register */
-  __I  uint32_t  TCBCNT;                    /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */
-  __I  uint32_t  TBBCNT;                    /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */
-  __IO uint32_t  DEBNCE;                    /*!< (@ 0x40004064) Debounce Count Register */
-  __IO uint32_t  USRID;                     /*!< (@ 0x40004068) User ID Register       */
-  __I  uint32_t  VERID;                     /*!< (@ 0x4000406C) Version ID Register    */
-  __I  uint32_t  RESERVED0;
-  __IO uint32_t  UHS_REG;                   /*!< (@ 0x40004074) UHS-1 Register         */
-  __IO uint32_t  RST_N;                     /*!< (@ 0x40004078) Hardware Reset         */
-  __I  uint32_t  RESERVED1;
-  __IO uint32_t  BMOD;                      /*!< (@ 0x40004080) Bus Mode Register      */
-  __O  uint32_t  PLDMND;                    /*!< (@ 0x40004084) Poll Demand Register   */
-  __IO uint32_t  DBADDR;                    /*!< (@ 0x40004088) Descriptor List Base Address Register */
-  __IO uint32_t  IDSTS;                     /*!< (@ 0x4000408C) Internal DMAC Status Register */
-  __IO uint32_t  IDINTEN;                   /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */
-  __I  uint32_t  DSCADDR;                   /*!< (@ 0x40004094) Current Host Descriptor Address Register */
-  __I  uint32_t  BUFADDR;                   /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */
-} LPC_SDMMC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          EMC                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7  (EMC)
-  */
-
-typedef struct {                            /*!< (@ 0x40005000) EMC Structure          */
-  __IO uint32_t  CONTROL;                   /*!< (@ 0x40005000) Controls operation of the memory controller. */
-  __I  uint32_t  STATUS;                    /*!< (@ 0x40005004) Provides EMC status information. */
-  __IO uint32_t  CONFIG;                    /*!< (@ 0x40005008) Configures operation of the memory controller. */
-  __I  uint32_t  RESERVED0[5];
-  __IO uint32_t  DYNAMICCONTROL;            /*!< (@ 0x40005020) Controls dynamic memory operation. */
-  __IO uint32_t  DYNAMICREFRESH;            /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */
-  __IO uint32_t  DYNAMICREADCONFIG;         /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */
-  __I  uint32_t  RESERVED1;
-  __IO uint32_t  DYNAMICRP;                 /*!< (@ 0x40005030) Selects the precharge command period. */
-  __IO uint32_t  DYNAMICRAS;                /*!< (@ 0x40005034) Selects the active to precharge command period. */
-  __IO uint32_t  DYNAMICSREX;               /*!< (@ 0x40005038) Selects the self-refresh exit time. */
-  __IO uint32_t  DYNAMICAPR;                /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */
-  __IO uint32_t  DYNAMICDAL;                /*!< (@ 0x40005040) Selects the data-in to active command time. */
-  __IO uint32_t  DYNAMICWR;                 /*!< (@ 0x40005044) Selects the write recovery time. */
-  __IO uint32_t  DYNAMICRC;                 /*!< (@ 0x40005048) Selects the active to active command period. */
-  __IO uint32_t  DYNAMICRFC;                /*!< (@ 0x4000504C) Selects the auto-refresh period. */
-  __IO uint32_t  DYNAMICXSR;                /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */
-  __IO uint32_t  DYNAMICRRD;                /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */
-  __IO uint32_t  DYNAMICMRD;                /*!< (@ 0x40005058) Selects the load mode register to active command time. */
-  __I  uint32_t  RESERVED2[9];
-  __IO uint32_t  STATICEXTENDEDWAIT;        /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */
-  __I  uint32_t  RESERVED3[31];
-  __IO uint32_t  DYNAMICCONFIG0;            /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */
-  __IO uint32_t  DYNAMICRASCAS0;            /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */
-  __I  uint32_t  RESERVED4[6];
-  __IO uint32_t  DYNAMICCONFIG1;            /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */
-  __IO uint32_t  DYNAMICRASCAS1;            /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */
-  __I  uint32_t  RESERVED5[6];
-  __IO uint32_t  DYNAMICCONFIG2;            /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */
-  __IO uint32_t  DYNAMICRASCAS2;            /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */
-  __I  uint32_t  RESERVED6[6];
-  __IO uint32_t  DYNAMICCONFIG3;            /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */
-  __IO uint32_t  DYNAMICRASCAS3;            /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */
-  __I  uint32_t  RESERVED7[38];
-  __IO uint32_t  STATICCONFIG0;             /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */
-  __IO uint32_t  STATICWAITWEN0;            /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */
-  __IO uint32_t  STATICWAITOEN0;            /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */
-  __IO uint32_t  STATICWAITRD0;             /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */
-  __IO uint32_t  STATICWAITPAG0;            /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
-  __IO uint32_t  STATICWAITWR0;             /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */
-  __IO uint32_t  STATICWAITTURN0;           /*!< (@ 0x40005218) Selects bus turnaround cycles */
-  __I  uint32_t  RESERVED8;
-  __IO uint32_t  STATICCONFIG1;             /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */
-  __IO uint32_t  STATICWAITWEN1;            /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */
-  __IO uint32_t  STATICWAITOEN1;            /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */
-  __IO uint32_t  STATICWAITRD1;             /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */
-  __IO uint32_t  STATICWAITPAG1;            /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
-  __IO uint32_t  STATICWAITWR1;             /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */
-  __IO uint32_t  STATICWAITTURN1;           /*!< (@ 0x40005238) Selects bus turnaround cycles */
-  __I  uint32_t  RESERVED9;
-  __IO uint32_t  STATICCONFIG2;             /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */
-  __IO uint32_t  STATICWAITWEN2;            /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */
-  __IO uint32_t  STATICWAITOEN2;            /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */
-  __IO uint32_t  STATICWAITRD2;             /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */
-  __IO uint32_t  STATICWAITPAG2;            /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
-  __IO uint32_t  STATICWAITWR2;             /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */
-  __IO uint32_t  STATICWAITTURN2;           /*!< (@ 0x40005258) Selects bus turnaround cycles */
-  __I  uint32_t  RESERVED10;
-  __IO uint32_t  STATICCONFIG3;             /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */
-  __IO uint32_t  STATICWAITWEN3;            /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */
-  __IO uint32_t  STATICWAITOEN3;            /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */
-  __IO uint32_t  STATICWAITRD3;             /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */
-  __IO uint32_t  STATICWAITPAG3;            /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
-  __IO uint32_t  STATICWAITWR3;             /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */
-  __IO uint32_t  STATICWAITTURN3;           /*!< (@ 0x40005278) Selects bus turnaround cycles */
-} LPC_EMC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         USB0                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB0)
-  */
-
-typedef struct {                            /*!< (@ 0x40006000) USB0 Structure         */
-  __I  uint32_t  RESERVED0[64];
-  __I  uint32_t  CAPLENGTH;                 /*!< (@ 0x40006100) Capability register length */
-  __I  uint32_t  HCSPARAMS;                 /*!< (@ 0x40006104) Host controller structural parameters */
-  __I  uint32_t  HCCPARAMS;                 /*!< (@ 0x40006108) Host controller capability parameters */
-  __I  uint32_t  RESERVED1[5];
-  __I  uint32_t  DCIVERSION;                /*!< (@ 0x40006120) Device interface version number */
-  __I  uint32_t  RESERVED2[7];
-  
-  union {
-    __IO uint32_t  USBCMD_H;                /*!< (@ 0x40006140) USB command (host mode) */
-    __IO uint32_t  USBCMD_D;                /*!< (@ 0x40006140) USB command (device mode) */
-  } ;
-  
-  union {
-    __IO uint32_t  USBSTS_H;                /*!< (@ 0x40006144) USB status (host mode) */
-    __IO uint32_t  USBSTS_D;                /*!< (@ 0x40006144) USB status (device mode) */
-  } ;
-  
-  union {
-    __IO uint32_t  USBINTR_H;               /*!< (@ 0x40006148) USB interrupt enable (host mode) */
-    __IO uint32_t  USBINTR_D;               /*!< (@ 0x40006148) USB interrupt enable (device mode) */
-  } ;
-  
-  union {
-    __IO uint32_t  FRINDEX_H;               /*!< (@ 0x4000614C) USB frame index (host mode) */
-    __IO uint32_t  FRINDEX_D;               /*!< (@ 0x4000614C) USB frame index (device mode) */
-  } ;
-  __I  uint32_t  RESERVED3;
-  
-  union {
-    __IO uint32_t  PERIODICLISTBASE;        /*!< (@ 0x40006154) Frame list base address (host mode) */
-    __IO uint32_t  DEVICEADDR;              /*!< (@ 0x40006154) USB device address (device mode) */
-  } ;
-  
-  union {
-    __IO uint32_t  ASYNCLISTADDR;           /*!< (@ 0x40006158) Address of endpoint list in memory */
-    __IO uint32_t  ENDPOINTLISTADDR;        /*!< (@ 0x40006158) Address of endpoint list in memory */
-  } ;
-  __IO uint32_t  TTCTRL;                    /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */
-  __IO uint32_t  BURSTSIZE;                 /*!< (@ 0x40006160) Programmable burst size */
-  __IO uint32_t  TXFILLTUNING;              /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */
-  __I  uint32_t  RESERVED4[3];
-  __IO uint32_t  BINTERVAL;                 /*!< (@ 0x40006174) Length of virtual frame */
-  __IO uint32_t  ENDPTNAK;                  /*!< (@ 0x40006178) Endpoint NAK (device mode) */
-  __IO uint32_t  ENDPTNAKEN;                /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */
-  __I  uint32_t  RESERVED5;
-  
-  union {
-    __IO uint32_t  PORTSC1_H;               /*!< (@ 0x40006184) Port 1 status/control (host mode) */
-    __IO uint32_t  PORTSC1_D;               /*!< (@ 0x40006184) Port 1 status/control (device mode) */
-  } ;
-  __I  uint32_t  RESERVED6[7];
-  __IO uint32_t  OTGSC;                     /*!< (@ 0x400061A4) OTG status and control */
-  
-  union {
-    __IO uint32_t  USBMODE_H;               /*!< (@ 0x400061A8) USB mode (host mode)   */
-    __IO uint32_t  USBMODE_D;               /*!< (@ 0x400061A8) USB device mode (device mode) */
-  } ;
-  __IO uint32_t  ENDPTSETUPSTAT;            /*!< (@ 0x400061AC) Endpoint setup status  */
-  __IO uint32_t  ENDPTPRIME;                /*!< (@ 0x400061B0) Endpoint initialization */
-  __IO uint32_t  ENDPTFLUSH;                /*!< (@ 0x400061B4) Endpoint de-initialization */
-  __I  uint32_t  ENDPTSTAT;                 /*!< (@ 0x400061B8) Endpoint status        */
-  __IO uint32_t  ENDPTCOMPLETE;             /*!< (@ 0x400061BC) Endpoint complete      */
-  __IO uint32_t  ENDPTCTRL0;                /*!< (@ 0x400061C0) Endpoint control 0     */
-  __IO uint32_t  ENDPTCTRL1;                /*!< (@ 0x400061C4) Endpoint control       */
-  __IO uint32_t  ENDPTCTRL2;                /*!< (@ 0x400061C8) Endpoint control       */
-  __IO uint32_t  ENDPTCTRL3;                /*!< (@ 0x400061CC) Endpoint control       */
-  __IO uint32_t  ENDPTCTRL4;                /*!< (@ 0x400061D0) Endpoint control       */
-  __IO uint32_t  ENDPTCTRL5;                /*!< (@ 0x400061D4) Endpoint control       */
-} LPC_USB0_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         USB1                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB1)
-  */
-
-typedef struct {                            /*!< (@ 0x40007000) USB1 Structure         */
-  __I  uint32_t  RESERVED0[64];
-  __I  uint32_t  CAPLENGTH;                 /*!< (@ 0x40007100) Capability register length */
-  __I  uint32_t  HCSPARAMS;                 /*!< (@ 0x40007104) Host controller structural parameters */
-  __I  uint32_t  HCCPARAMS;                 /*!< (@ 0x40007108) Host controller capability parameters */
-  __I  uint32_t  RESERVED1[5];
-  __I  uint32_t  DCIVERSION;                /*!< (@ 0x40007120) Device interface version number */
-  __I  uint32_t  RESERVED2[7];
-  
-  union {
-    __IO uint32_t  USBCMD_H;                /*!< (@ 0x40007140) USB command (host mode) */
-    __IO uint32_t  USBCMD_D;                /*!< (@ 0x40007140) USB command (device mode) */
-  } ;
-  
-  union {
-    __IO uint32_t  USBSTS_H;                /*!< (@ 0x40007144) USB status (host mode) */
-    __IO uint32_t  USBSTS_D;                /*!< (@ 0x40007144) USB status (device mode) */
-  } ;
-  
-  union {
-    __IO uint32_t  USBINTR_H;               /*!< (@ 0x40007148) USB interrupt enable (host mode) */
-    __IO uint32_t  USBINTR_D;               /*!< (@ 0x40007148) USB interrupt enable (device mode) */
-  } ;
-  
-  union {
-    __IO uint32_t  FRINDEX_H;               /*!< (@ 0x4000714C) USB frame index (host mode) */
-    __I  uint32_t  FRINDEX_D;               /*!< (@ 0x4000714C) USB frame index (device mode) */
-  } ;
-  __I  uint32_t  RESERVED3;
-  
-  union {
-    __IO uint32_t  PERIODICLISTBASE;        /*!< (@ 0x40007154) Frame list base address */
-    __IO uint32_t  DEVICEADDR;              /*!< (@ 0x40007154) USB device address     */
-  } ;
-  
-  union {
-    __IO uint32_t  ASYNCLISTADDR;           /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */
-    __IO uint32_t  ENDPOINTLISTADDR;        /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */
-  } ;
-  __IO uint32_t  TTCTRL;                    /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */
-  __IO uint32_t  BURSTSIZE;                 /*!< (@ 0x40007160) Programmable burst size */
-  __IO uint32_t  TXFILLTUNING;              /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */
-  __I  uint32_t  RESERVED4[2];
-  __IO uint32_t  ULPIVIEWPORT;              /*!< (@ 0x40007170) ULPI viewport          */
-  __IO uint32_t  BINTERVAL;                 /*!< (@ 0x40007174) Length of virtual frame */
-  __IO uint32_t  ENDPTNAK;                  /*!< (@ 0x40007178) Endpoint NAK (device mode) */
-  __IO uint32_t  ENDPTNAKEN;                /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */
-  __I  uint32_t  RESERVED5;
-  
-  union {
-    __IO uint32_t  PORTSC1_H;               /*!< (@ 0x40007184) Port 1 status/control (host mode) */
-    __IO uint32_t  PORTSC1_D;               /*!< (@ 0x40007184) Port 1 status/control (device mode) */
-  } ;
-  __I  uint32_t  RESERVED6[8];
-  
-  union {
-    __IO uint32_t  USBMODE_H;               /*!< (@ 0x400071A8) USB mode (host mode)   */
-    __IO uint32_t  USBMODE_D;               /*!< (@ 0x400071A8) USB mode (device mode) */
-  } ;
-  __IO uint32_t  ENDPTSETUPSTAT;            /*!< (@ 0x400071AC) Endpoint setup status  */
-  __IO uint32_t  ENDPTPRIME;                /*!< (@ 0x400071B0) Endpoint initialization */
-  __IO uint32_t  ENDPTFLUSH;                /*!< (@ 0x400071B4) Endpoint de-initialization */
-  __I  uint32_t  ENDPTSTAT;                 /*!< (@ 0x400071B8) Endpoint status        */
-  __IO uint32_t  ENDPTCOMPLETE;             /*!< (@ 0x400071BC) Endpoint complete      */
-  __IO uint32_t  ENDPTCTRL0;                /*!< (@ 0x400071C0) Endpoint control 0     */
-  __IO uint32_t  ENDPTCTRL1;                /*!< (@ 0x400071C4) Endpoint control       */
-  __IO uint32_t  ENDPTCTRL2;                /*!< (@ 0x400071C8) Endpoint control       */
-  __IO uint32_t  ENDPTCTRL3;                /*!< (@ 0x400071CC) Endpoint control       */
-} LPC_USB1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          LCD                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7  (LCD)
-  */
-
-typedef struct {                            /*!< (@ 0x40008000) LCD Structure          */
-  __IO uint32_t  TIMH;                      /*!< (@ 0x40008000) Horizontal Timing Control register */
-  __IO uint32_t  TIMV;                      /*!< (@ 0x40008004) Vertical Timing Control register */
-  __IO uint32_t  POL;                       /*!< (@ 0x40008008) Clock and Signal Polarity Control register */
-  __IO uint32_t  LE;                        /*!< (@ 0x4000800C) Line End Control register */
-  __IO uint32_t  UPBASE;                    /*!< (@ 0x40008010) Upper Panel Frame Base Address register */
-  __IO uint32_t  LPBASE;                    /*!< (@ 0x40008014) Lower Panel Frame Base Address register */
-  __IO uint32_t  CTRL;                      /*!< (@ 0x40008018) LCD Control register   */
-  __IO uint32_t  INTMSK;                    /*!< (@ 0x4000801C) Interrupt Mask register */
-  __I  uint32_t  INTRAW;                    /*!< (@ 0x40008020) Raw Interrupt Status register */
-  __I  uint32_t  INTSTAT;                   /*!< (@ 0x40008024) Masked Interrupt Status register */
-  __O  uint32_t  INTCLR;                    /*!< (@ 0x40008028) Interrupt Clear register */
-  __I  uint32_t  UPCURR;                    /*!< (@ 0x4000802C) Upper Panel Current Address Value register */
-  __I  uint32_t  LPCURR;                    /*!< (@ 0x40008030) Lower Panel Current Address Value register */
-  __I  uint32_t  RESERVED0[115];
-  __IO uint32_t PAL[256];					/*!< (@ 0x40008200) 256x16-bit Color Palette registers */
-  __I  uint32_t  RESERVED1[128];
-  __IO uint32_t CRSR_IMG[256];              /*!< (@ 0x40008800) Cursor Image registers */
-  __IO uint32_t  CRSR_CTRL;                 /*!< (@ 0x40008C00) Cursor Control register */
-  __IO uint32_t  CRSR_CFG;                  /*!< (@ 0x40008C04) Cursor Configuration register */
-  __IO uint32_t  CRSR_PAL0;                 /*!< (@ 0x40008C08) Cursor Palette register 0 */
-  __IO uint32_t  CRSR_PAL1;                 /*!< (@ 0x40008C0C) Cursor Palette register 1 */
-  __IO uint32_t  CRSR_XY;                   /*!< (@ 0x40008C10) Cursor XY Position register */
-  __IO uint32_t  CRSR_CLIP;                 /*!< (@ 0x40008C14) Cursor Clip Position register */
-  __I  uint32_t  RESERVED2[2];
-  __IO uint32_t  CRSR_INTMSK;               /*!< (@ 0x40008C20) Cursor Interrupt Mask register */
-  __O  uint32_t  CRSR_INTCLR;               /*!< (@ 0x40008C24) Cursor Interrupt Clear register */
-  __I  uint32_t  CRSR_INTRAW;               /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */
-  __I  uint32_t  CRSR_INTSTAT;              /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */
-} LPC_LCD_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       ETHERNET                                       -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=12/9/2011 Major revision=1.1 Minor revision=not available  (ETHERNET)
-  */
-
-typedef struct {                            /*!< (@ 0x40010000) ETHERNET Structure     */
-  __IO uint32_t  MAC_CONFIG;                /*!< (@ 0x40010000) MAC configuration register */
-  __IO uint32_t  MAC_FRAME_FILTER;          /*!< (@ 0x40010004) MAC frame filter       */
-  __IO uint32_t  MAC_HASHTABLE_HIGH;        /*!< (@ 0x40010008) Hash table high register */
-  __IO uint32_t  MAC_HASHTABLE_LOW;         /*!< (@ 0x4001000C) Hash table low register */
-  __IO uint32_t  MAC_MII_ADDR;              /*!< (@ 0x40010010) MII address register   */
-  __IO uint32_t  MAC_MII_DATA;              /*!< (@ 0x40010014) MII data register      */
-  __IO uint32_t  MAC_FLOW_CTRL;             /*!< (@ 0x40010018) Flow control register  */
-  __IO uint32_t  MAC_VLAN_TAG;              /*!< (@ 0x4001001C) VLAN tag register      */
-  __I  uint32_t  RESERVED0;
-  __I  uint32_t  MAC_DEBUG;                 /*!< (@ 0x40010024) Debug register         */
-  __IO uint32_t  MAC_RWAKE_FRFLT;           /*!< (@ 0x40010028) Remote wake-up frame filter */
-  __IO uint32_t  MAC_PMT_CTRL_STAT;         /*!< (@ 0x4001002C) PMT control and status */
-  __I  uint32_t  RESERVED1[2];
-  __I  uint32_t  MAC_INTR;                  /*!< (@ 0x40010038) Interrupt status register */
-  __IO uint32_t  MAC_INTR_MASK;             /*!< (@ 0x4001003C) Interrupt mask register */
-  __IO uint32_t  MAC_ADDR0_HIGH;            /*!< (@ 0x40010040) MAC address 0 high register */
-  __IO uint32_t  MAC_ADDR0_LOW;             /*!< (@ 0x40010044) MAC address 0 low register */
-  __I  uint32_t  RESERVED2[430];
-  __IO uint32_t  MAC_TIMESTP_CTRL;          /*!< (@ 0x40010700) Time stamp control register */
-  __IO uint32_t  SUBSECOND_INCR;            /*!< (@ 0x40010704) Sub-second increment register */
-  __I  uint32_t  SECONDS;                   /*!< (@ 0x40010708) System time seconds register */
-  __I  uint32_t  NANOSECONDS;               /*!< (@ 0x4001070C) System time nanoseconds register */
-  __IO uint32_t  SECONDSUPDATE;             /*!< (@ 0x40010710) System time seconds update register */
-  __IO uint32_t  NANOSECONDSUPDATE;         /*!< (@ 0x40010714) System time nanoseconds update register */
-  __IO uint32_t  ADDEND;                    /*!< (@ 0x40010718) Time stamp addend register */
-  __IO uint32_t  TARGETSECONDS;             /*!< (@ 0x4001071C) Target time seconds register */
-  __IO uint32_t  TARGETNANOSECONDS;         /*!< (@ 0x40010720) Target time nanoseconds register */
-  __IO uint32_t  HIGHWORD;                  /*!< (@ 0x40010724) System time higher word seconds register */
-  __I  uint32_t  TIMESTAMPSTAT;             /*!< (@ 0x40010728) Time stamp status register */
-  __IO uint32_t  PPSCTRL;                   /*!< (@ 0x4001072C) PPS control register   */
-  __I  uint32_t  AUXNANOSECONDS;            /*!< (@ 0x40010730) Auxiliary time stamp nanoseconds register */
-  __I  uint32_t  AUXSECONDS;                /*!< (@ 0x40010734) Auxiliary time stamp seconds register */
-  __I  uint32_t  RESERVED3[562];
-  __IO uint32_t  DMA_BUS_MODE;              /*!< (@ 0x40011000) Bus Mode Register      */
-  __IO uint32_t  DMA_TRANS_POLL_DEMAND;     /*!< (@ 0x40011004) Transmit poll demand register */
-  __IO uint32_t  DMA_REC_POLL_DEMAND;       /*!< (@ 0x40011008) Receive poll demand register */
-  __IO uint32_t  DMA_REC_DES_ADDR;          /*!< (@ 0x4001100C) Receive descriptor list address register */
-  __IO uint32_t  DMA_TRANS_DES_ADDR;        /*!< (@ 0x40011010) Transmit descriptor list address register */
-  __IO uint32_t  DMA_STAT;                  /*!< (@ 0x40011014) Status register        */
-  __IO uint32_t  DMA_OP_MODE;               /*!< (@ 0x40011018) Operation mode register */
-  __IO uint32_t  DMA_INT_EN;                /*!< (@ 0x4001101C) Interrupt enable register */
-  __I  uint32_t  DMA_MFRM_BUFOF;            /*!< (@ 0x40011020) Missed frame and buffer overflow register */
-  __IO uint32_t  DMA_REC_INT_WDT;           /*!< (@ 0x40011024) Receive interrupt watchdog timer register */
-  __I  uint32_t  RESERVED4[8];
-  __I  uint32_t  DMA_CURHOST_TRANS_DES;     /*!< (@ 0x40011048) Current host transmit descriptor register */
-  __I  uint32_t  DMA_CURHOST_REC_DES;       /*!< (@ 0x4001104C) Current host receive descriptor register */
-  __I  uint32_t  DMA_CURHOST_TRANS_BUF;     /*!< (@ 0x40011050) Current host transmit buffer address register */
-  __I  uint32_t  DMA_CURHOST_REC_BUF;       /*!< (@ 0x40011054) Current host receive buffer address register */
-} LPC_ETHERNET_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        ATIMER                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6  (ATIMER)
-  */
-
-typedef struct {                            /*!< (@ 0x40040000) ATIMER Structure       */
-  __IO uint32_t  DOWNCOUNTER;               /*!< (@ 0x40040000) Downcounter register   */
-  __IO uint32_t  PRESET;                    /*!< (@ 0x40040004) Preset value register  */
-  __I  uint32_t  RESERVED0[1012];
-  __O  uint32_t  CLR_EN;                    /*!< (@ 0x40040FD8) Interrupt clear enable register */
-  __O  uint32_t  SET_EN;                    /*!< (@ 0x40040FDC) Interrupt set enable register */
-  __I  uint32_t  STATUS;                    /*!< (@ 0x40040FE0) Status register        */
-  __I  uint32_t  ENABLE;                    /*!< (@ 0x40040FE4) Enable register        */
-  __O  uint32_t  CLR_STAT;                  /*!< (@ 0x40040FE8) Clear register         */
-  __O  uint32_t  SET_STAT;                  /*!< (@ 0x40040FEC) Set register           */
-} LPC_ATIMER_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        REGFILE                                       -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7  (REGFILE)
-  */
-
-typedef struct {                            /*!< (@ 0x40041000) REGFILE Structure      */
-  __IO uint32_t REGFILE[64];                /*!< (@ 0x40041000) General purpose storage register */
-} LPC_REGFILE_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          PMC                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (PMC)
-  */
-
-typedef struct {                            /*!< (@ 0x40042000) PMC Structure          */
-  __IO uint32_t  PD0_SLEEP0_HW_ENA;         /*!< (@ 0x40042000) Hardware sleep event enable register */
-  __I  uint32_t  RESERVED0[6];
-  __IO uint32_t  PD0_SLEEP0_MODE;           /*!< (@ 0x4004201C) Sleep power mode register */
-} LPC_PMC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         CREG                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10503 Chapter title=LPC43xx Configuration Registers (CREG) Modification date=10/7/2011 Major revision=0 Minor revision=3  (CREG)
-  */
-
-typedef struct {                            /*!< (@ 0x40043000) CREG Structure         */
-  __I  uint32_t  IRCTRM;                    /*!< (@ 0x40043000) IRC trim register      */
-  __IO uint32_t  CREG0;                     /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */
-  __I  uint32_t  RESERVED1[62];
-  __IO uint32_t  M4MEMMAP;                  /*!< (@ 0x40043100) ARM Cortex-M4 memory mapping */
-  __I  uint32_t  RESERVED2[5];
-  __IO uint32_t  CREG5;                     /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */
-  __IO uint32_t  DMAMUX;                    /*!< (@ 0x4004311C) DMA muxing control     */
-  __I  uint32_t  RESERVED3[2];
-  __IO uint32_t  ETBCFG;                    /*!< (@ 0x40043128) ETB RAM configuration  */
-  __IO uint32_t  CREG6;                     /*!< (@ 0x4004312C) Chip configuration register 6. */
-  __IO uint32_t  M4TXEVENT;                 /*!< (@ 0x40043130) Cortex-M4 TXEV event clear */
-  __I  uint32_t  RESERVED4[51];
-  __I  uint32_t  CHIPID;                    /*!< (@ 0x40043200) Part ID                */
-  __I  uint32_t  RESERVED5[127];
-  __IO uint32_t  M0TXEVENT;                 /*!< (@ 0x40043400) Cortex-M0 TXEV event clear */
-  __IO uint32_t  M0APPMEMMAP;               /*!< (@ 0x40043404) ARM Cortex-M0 memory mapping */
-} LPC_CREG_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                      EVENTROUTER                                     -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10503 Chapter title=LPC43xx Event router Modification date=10/7/2011 Major revision=0 Minor revision=3  (EVENTROUTER)
-  */
-
-typedef struct {                            /*!< (@ 0x40044000) EVENTROUTER Structure  */
-  __IO uint32_t  HILO;                      /*!< (@ 0x40044000) Level configuration register */
-  __IO uint32_t  EDGE;                      /*!< (@ 0x40044004) Edge configuration     */
-  __I  uint32_t  RESERVED0[1012];
-  __O  uint32_t  CLR_EN;                    /*!< (@ 0x40044FD8) Clear event enable register */
-  __O  uint32_t  SET_EN;                    /*!< (@ 0x40044FDC) Set event enable register */
-  __I  uint32_t  STATUS;                    /*!< (@ 0x40044FE0) Event Status register  */
-  __I  uint32_t  ENABLE;                    /*!< (@ 0x40044FE4) Event Enable register  */
-  __O  uint32_t  CLR_STAT;                  /*!< (@ 0x40044FE8) Clear event status register */
-  __O  uint32_t  SET_STAT;                  /*!< (@ 0x40044FEC) Set event status register */
-} LPC_EVENTROUTER_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          RTC                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (RTC)
-  */
-
-typedef struct {                            /*!< (@ 0x40046000) RTC Structure          */
-  __O  uint32_t  ILR;                       /*!< (@ 0x40046000) Interrupt Location Register */
-  __I  uint32_t  RESERVED0;
-  __IO uint32_t  CCR;                       /*!< (@ 0x40046008) Clock Control Register */
-  __IO uint32_t  CIIR;                      /*!< (@ 0x4004600C) Counter Increment Interrupt Register */
-  __IO uint32_t  AMR;                       /*!< (@ 0x40046010) Alarm Mask Register    */
-  __I  uint32_t  CTIME0;                    /*!< (@ 0x40046014) Consolidated Time Register 0 */
-  __I  uint32_t  CTIME1;                    /*!< (@ 0x40046018) Consolidated Time Register 1 */
-  __I  uint32_t  CTIME2;                    /*!< (@ 0x4004601C) Consolidated Time Register 2 */
-  __IO uint32_t  SEC;                       /*!< (@ 0x40046020) Seconds Register       */
-  __IO uint32_t  MIN;                       /*!< (@ 0x40046024) Minutes Register       */
-  __IO uint32_t  HRS;                       /*!< (@ 0x40046028) Hours Register         */
-  __IO uint32_t  DOM;                       /*!< (@ 0x4004602C) Day of Month Register  */
-  __IO uint32_t  DOW;                       /*!< (@ 0x40046030) Day of Week Register   */
-  __IO uint32_t  DOY;                       /*!< (@ 0x40046034) Day of Year Register   */
-  __IO uint32_t  MONTH;                     /*!< (@ 0x40046038) Months Register        */
-  __IO uint32_t  YEAR;                      /*!< (@ 0x4004603C) Years Register         */
-  __IO uint32_t  CALIBRATION;               /*!< (@ 0x40046040) Calibration Value Register */
-  __I  uint32_t  RESERVED1[7];
-  __IO uint32_t  ASEC;                      /*!< (@ 0x40046060) Alarm value for Seconds */
-  __IO uint32_t  AMIN;                      /*!< (@ 0x40046064) Alarm value for Minutes */
-  __IO uint32_t  AHRS;                      /*!< (@ 0x40046068) Alarm value for Hours  */
-  __IO uint32_t  ADOM;                      /*!< (@ 0x4004606C) Alarm value for Day of Month */
-  __IO uint32_t  ADOW;                      /*!< (@ 0x40046070) Alarm value for Day of Week */
-  __IO uint32_t  ADOY;                      /*!< (@ 0x40046074) Alarm value for Day of Year */
-  __IO uint32_t  AMON;                      /*!< (@ 0x40046078) Alarm value for Months */
-  __IO uint32_t  AYRS;                      /*!< (@ 0x4004607C) Alarm value for Year   */
-} LPC_RTC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          CGU                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1  (CGU)
-  */
-
-typedef struct {                            /*!< (@ 0x40050000) CGU Structure          */
-  __I  uint32_t  RESERVED0[5];
-  __IO uint32_t  FREQ_MON;                  /*!< (@ 0x40050014) Frequency monitor register */
-  __IO uint32_t  XTAL_OSC_CTRL;             /*!< (@ 0x40050018) Crystal oscillator control register */
-  __I  uint32_t  PLL0USB_STAT;              /*!< (@ 0x4005001C) PLL0 (USB) status register */
-  __IO uint32_t  PLL0USB_CTRL;              /*!< (@ 0x40050020) PLL0 (USB) control register */
-  __IO uint32_t  PLL0USB_MDIV;              /*!< (@ 0x40050024) PLL0 (USB) M-divider register */
-  __IO uint32_t  PLL0USB_NP_DIV;            /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
-  __I  uint32_t  PLL0AUDIO_STAT;            /*!< (@ 0x4005002C) PLL0 (audio) status register */
-  __IO uint32_t  PLL0AUDIO_CTRL;            /*!< (@ 0x40050030) PLL0 (audio) control register */
-  __IO uint32_t  PLL0AUDIO_MDIV;            /*!< (@ 0x40050034) PLL0 (audio) M-divider register */
-  __IO uint32_t  PLL0AUDIO_NP_DIV;          /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
-  __IO uint32_t  PLL0AUDIO_FRAC;            /*!< (@ 0x4005003C) PLL0 (audio)           */
-  __I  uint32_t  PLL1_STAT;                 /*!< (@ 0x40050040) PLL1 status register   */
-  __IO uint32_t  PLL1_CTRL;                 /*!< (@ 0x40050044) PLL1 control register  */
-  __IO uint32_t  IDIVA_CTRL;                /*!< (@ 0x40050048) Integer divider A control register */
-  __IO uint32_t  IDIVB_CTRL;                /*!< (@ 0x4005004C) Integer divider B control register */
-  __IO uint32_t  IDIVC_CTRL;                /*!< (@ 0x40050050) Integer divider C control register */
-  __IO uint32_t  IDIVD_CTRL;                /*!< (@ 0x40050054) Integer divider D control register */
-  __IO uint32_t  IDIVE_CTRL;                /*!< (@ 0x40050058) Integer divider E control register */
-  __IO uint32_t  BASE_SAFE_CLK;             /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */
-  __IO uint32_t  BASE_USB0_CLK;             /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */
-  __IO uint32_t  BASE_PERIPH_CLK;           /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */
-  __IO uint32_t  BASE_USB1_CLK;             /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */
-  __IO uint32_t  BASE_M4_CLK;               /*!< (@ 0x4005006C) Output stage BASE_M4_CLK control register */
-  __IO uint32_t  BASE_SPIFI_CLK;            /*!< (@ 0x40050070) Output stage BASE_SPIFI_CLK control register */
-  __IO uint32_t  BASE_SPI_CLK;              /*!< (@ 0x40050074) Output stage BASE_SPI_CLK control register */
-  __IO uint32_t  BASE_PHY_RX_CLK;           /*!< (@ 0x40050078) Output stage BASE_PHY_RX_CLK control register */
-  __IO uint32_t  BASE_PHY_TX_CLK;           /*!< (@ 0x4005007C) Output stage BASE_PHY_TX_CLK control register */
-  __IO uint32_t  BASE_APB1_CLK;             /*!< (@ 0x40050080) Output stage BASE_APB1_CLK control register */
-  __IO uint32_t  BASE_APB3_CLK;             /*!< (@ 0x40050084) Output stage BASE_APB3_CLK control register */
-  __IO uint32_t  BASE_LCD_CLK;              /*!< (@ 0x40050088) Output stage BASE_LCD_CLK control register */
-  __I  uint32_t  RESERVED2;
-  __IO uint32_t  BASE_SDIO_CLK;             /*!< (@ 0x40050090) Output stage BASE_SDIO_CLK control register */
-  __IO uint32_t  BASE_SSP0_CLK;             /*!< (@ 0x40050094) Output stage BASE_SSP0_CLK control register */
-  __IO uint32_t  BASE_SSP1_CLK;             /*!< (@ 0x40050098) Output stage BASE_SSP1_CLK control register */
-  __IO uint32_t  BASE_UART0_CLK;            /*!< (@ 0x4005009C) Output stage BASE_UART0_CLK control register */
-  __IO uint32_t  BASE_UART1_CLK;            /*!< (@ 0x400500A0) Output stage BASE_UART1_CLK control register */
-  __IO uint32_t  BASE_UART2_CLK;            /*!< (@ 0x400500A4) Output stage BASE_UART2_CLK control register */
-  __IO uint32_t  BASE_UART3_CLK;            /*!< (@ 0x400500A8) Output stage BASE_UART3_CLK control register */
-  __IO uint32_t  BASE_OUT_CLK;              /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */
-  __I  uint32_t  RESERVED3[4];
-  __IO uint32_t  BASE_APLL_CLK;             /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */
-  __IO uint32_t  BASE_CGU_OUT0_CLK;         /*!< (@ 0x400500C4) Output stage 25 control register for base clock BASE_CGU_OUT0_CLK */
-  __IO uint32_t  BASE_CGU_OUT1_CLK;         /*!< (@ 0x400500C8) Output stage 25 control register for base clock BASE_CGU_OUT1_CLK */
-} LPC_CGU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         CCU1                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC43xx Clock Control Unit (CCU) (CCU1)
-  */
-
-typedef struct {                            /*!< (@ 0x40051000) CCU1 Structure         */
-  __IO uint32_t  PM;                        /*!< (@ 0x40051000) CCU1 power mode register */
-  __I  uint32_t  BASE_STAT;                 /*!< (@ 0x40051004) CCU1 base clocks status register */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  CLK_APB3_BUS_CFG;          /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */
-  __I  uint32_t  CLK_APB3_BUS_STAT;         /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */
-  __IO uint32_t  CLK_APB3_I2C1_CFG;         /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */
-  __I  uint32_t  CLK_APB3_I2C1_STAT;        /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */
-  __IO uint32_t  CLK_APB3_DAC_CFG;          /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */
-  __I  uint32_t  CLK_APB3_DAC_STAT;         /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */
-  __IO uint32_t  CLK_APB3_ADC0_CFG;         /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */
-  __I  uint32_t  CLK_APB3_ADC0_STAT;        /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */
-  __IO uint32_t  CLK_APB3_ADC1_CFG;         /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */
-  __I  uint32_t  CLK_APB3_ADC1_STAT;        /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */
-  __IO uint32_t  CLK_APB3_CAN0_CFG;         /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */
-  __I  uint32_t  CLK_APB3_CAN0_STAT;        /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */
-  __I  uint32_t  RESERVED1[52];
-  __IO uint32_t  CLK_APB1_BUS_CFG;          /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */
-  __I  uint32_t  CLK_APB1_BUS_STAT;         /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */
-  __IO uint32_t  CLK_APB1_MOTOCONPWM_CFG;   /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */
-  __I  uint32_t  CLK_APB1_MOTOCONPWM_STAT;  /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */
-  __IO uint32_t  CLK_ABP1_I2C0_CFG;         /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */
-  __I  uint32_t  CLK_APB1_I2C0_STAT;        /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */
-  __IO uint32_t  CLK_APB1_I2S_CFG;          /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */
-  __I  uint32_t  CLK_APB1_I2S_STAT;         /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */
-  __IO uint32_t  CLK_APB1_CAN1_CFG;         /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */
-  __I  uint32_t  CLK_APB1_CAN1_STAT;        /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */
-  __I  uint32_t  RESERVED2[54];
-  __IO uint32_t  CLK_SPIFI_CFG;             /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */
-  __I  uint32_t  CLK_SPIFI_STAT;            /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */
-  __I  uint32_t  RESERVED3[62];
-  __IO uint32_t  CLK_M4_BUS_CFG;            /*!< (@ 0x40051400) CLK_M4_BUS clock configuration register */
-  __I  uint32_t  CLK_M4_BUS_STAT;           /*!< (@ 0x40051404) CLK_M4_BUSclock status register */
-  __IO uint32_t  CLK_M4_SPIFI_CFG;          /*!< (@ 0x40051408) CLK_M4_SPIFI clock configuration register */
-  __I  uint32_t  CLK_M4_SPIFI_STAT;         /*!< (@ 0x4005140C) CLK_M4_SPIFI clock status register */
-  __IO uint32_t  CLK_M4_GPIO_CFG;           /*!< (@ 0x40051410) CLK_M4_GPIO clock configuration register */
-  __I  uint32_t  CLK_M4_GPIO_STAT;          /*!< (@ 0x40051414) CLK_M4_GPIO clock status register */
-  __IO uint32_t  CLK_M4_LCD_CFG;            /*!< (@ 0x40051418) CLK_M4_LCD clock configuration register */
-  __I  uint32_t  CLK_M4_LCD_STAT;           /*!< (@ 0x4005141C) CLK_M4_LCD clock status register */
-  __IO uint32_t  CLK_M4_ETHERNET_CFG;       /*!< (@ 0x40051420) CLK_M4_ETHERNET clock configuration register */
-  __I  uint32_t  CLK_M4_ETHERNET_STAT;      /*!< (@ 0x40051424) CLK_M4_ETHERNET clock status register */
-  __IO uint32_t  CLK_M4_USB0_CFG;           /*!< (@ 0x40051428) CLK_M4_USB0 clock configuration register */
-  __I  uint32_t  CLK_M4_USB0_STAT;          /*!< (@ 0x4005142C) CLK_M4_USB0 clock status register */
-  __IO uint32_t  CLK_M4_EMC_CFG;            /*!< (@ 0x40051430) CLK_M4_EMC clock configuration register */
-  __I  uint32_t  CLK_M4_EMC_STAT;           /*!< (@ 0x40051434) CLK_M4_EMC clock status register */
-  __IO uint32_t  CLK_M4_SDIO_CFG;           /*!< (@ 0x40051438) CLK_M4_SDIO clock configuration register */
-  __I  uint32_t  CLK_M4_SDIO_STAT;          /*!< (@ 0x4005143C) CLK_M4_SDIO clock status register */
-  __IO uint32_t  CLK_M4_DMA_CFG;            /*!< (@ 0x40051440) CLK_M4_DMA clock configuration register */
-  __I  uint32_t  CLK_M4_DMA_STAT;           /*!< (@ 0x40051444) CLK_M4_DMA clock status register */
-  __IO uint32_t  CLK_M4_M4CORE_CFG;         /*!< (@ 0x40051448) CLK_M4_M4CORE clock configuration register */
-  __I  uint32_t  CLK_M4_M3CORE_STAT;        /*!< (@ 0x4005144C) CLK_M4_M3CORE clock status register */
-  __I  uint32_t  RESERVED4[6];
-  __IO uint32_t  CLK_M4_SCT_CFG;            /*!< (@ 0x40051468) CLK_M4_SCT clock configuration register */
-  __I  uint32_t  CLK_M4_SCT_STAT;           /*!< (@ 0x4005146C) CLK_M4_SCT clock status register */
-  __IO uint32_t  CLK_M4_USB1_CFG;           /*!< (@ 0x40051470) CLK_M4_USB1 clock configuration register */
-  __I  uint32_t  CLK_M4_USB1_STAT;          /*!< (@ 0x40051474) CLK_M4_USB1 clock status register */
-  __IO uint32_t  CLK_M4_EMCDIV_CFG;         /*!< (@ 0x40051478) CLK_M4_EMCDIV clock configuration register */
-  __I  uint32_t  CLK_M4_EMCDIV_STAT;        /*!< (@ 0x4005147C) CLK_M4_EMCDIV clock status register */
-  __I  uint32_t  RESERVED5[4];
-  __IO uint32_t  CLK_M4_M0APP_CFG;          /*!< (@ 0x40051490) CLK_M0APP_CFG clock configuration register */
-  __I  uint32_t  CLK_M4_M0APP_STAT;         /*!< (@ 0x40051494) CLK_M4_MOAPP clock status register */
-  __I  uint32_t  RESERVED6[26];
-  __IO uint32_t  CLK_M4_WWDT_CFG;           /*!< (@ 0x40051500) CLK_M4_WWDT clock configuration register */
-  __I  uint32_t  CLK_M4_WWDT_STAT;          /*!< (@ 0x40051504) CLK_M4_WWDT clock status register */
-  __IO uint32_t  CLK_M4_USART0_CFG;         /*!< (@ 0x40051508) CLK_M4_USART0 clock configuration register */
-  __I  uint32_t  CLK_M4_USART0_STAT;        /*!< (@ 0x4005150C) CLK_M4_USART0 clock status register */
-  __IO uint32_t  CLK_M4_UART1_CFG;          /*!< (@ 0x40051510) CLK_M4_UART1 clock configuration register */
-  __I  uint32_t  CLK_M4_UART1_STAT;         /*!< (@ 0x40051514) CLK_M4_UART1 clock status register */
-  __IO uint32_t  CLK_M4_SSP0_CFG;           /*!< (@ 0x40051518) CLK_M4_SSP0 clock configuration register */
-  __I  uint32_t  CLK_M4_SSP0_STAT;          /*!< (@ 0x4005151C) CLK_M4_SSP0 clock status register */
-  __IO uint32_t  CLK_M4_TIMER0_CFG;         /*!< (@ 0x40051520) CLK_M4_TIMER0 clock configuration register */
-  __I  uint32_t  CLK_M4_TIMER0_STAT;        /*!< (@ 0x40051524) CLK_M4_TIMER0 clock status register */
-  __IO uint32_t  CLK_M4_TIMER1_CFG;         /*!< (@ 0x40051528) CLK_M4_TIMER1clock configuration register */
-  __I  uint32_t  CLK_M4_TIMER1_STAT;        /*!< (@ 0x4005152C) CLK_M4_TIMER1 clock status register */
-  __IO uint32_t  CLK_M4_SCU_CFG;            /*!< (@ 0x40051530) CLK_M4_SCU clock configuration register */
-  __I  uint32_t  CLK_M4_SCU_STAT;           /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */
-  __IO uint32_t  CLK_M4_CREG_CFG;           /*!< (@ 0x40051538) CLK_M4_CREGclock configuration register */
-  __I  uint32_t  CLK_M4_CREG_STAT;          /*!< (@ 0x4005153C) CLK_M4_CREG clock status register */
-  __I  uint32_t  RESERVED7[48];
-  __IO uint32_t  CLK_M4_RITIMER_CFG;        /*!< (@ 0x40051600) CLK_M4_RITIMER clock configuration register */
-  __I  uint32_t  CLK_M4_RITIMER_STAT;       /*!< (@ 0x40051604) CLK_M4_RITIMER clock status register */
-  __IO uint32_t  CLK_M4_USART2_CFG;         /*!< (@ 0x40051608) CLK_M4_USART2 clock configuration register */
-  __I  uint32_t  CLK_M4_USART2_STAT;        /*!< (@ 0x4005160C) CLK_M4_USART2 clock status register */
-  __IO uint32_t  CLK_M4_USART3_CFG;         /*!< (@ 0x40051610) CLK_M4_USART3 clock configuration register */
-  __I  uint32_t  CLK_M4_USART3_STAT;        /*!< (@ 0x40051614) CLK_M4_USART3 clock status register */
-  __IO uint32_t  CLK_M4_TIMER2_CFG;         /*!< (@ 0x40051618) CLK_M4_TIMER2 clock configuration register */
-  __I  uint32_t  CLK_M4_TIMER2_STAT;        /*!< (@ 0x4005161C) CLK_M4_TIMER2 clock status register */
-  __IO uint32_t  CLK_M4_TIMER3_CFG;         /*!< (@ 0x40051620) CLK_M4_TIMER3 clock configuration register */
-  __I  uint32_t  CLK_M4_TIMER3_STAT;        /*!< (@ 0x40051624) CLK_M4_TIMER3 clock status register */
-  __IO uint32_t  CLK_M4_SSP1_CFG;           /*!< (@ 0x40051628) CLK_M4_SSP1 clock configuration register */
-  __I  uint32_t  CLK_M4_SSP1_STAT;          /*!< (@ 0x4005162C) CLK_M4_SSP1 clock status register */
-  __IO uint32_t  CLK_M4_QEI_CFG;            /*!< (@ 0x40051630) CLK_M4_QEIclock configuration register */
-  __I  uint32_t  CLK_M4_QEI_STAT;           /*!< (@ 0x40051634) CLK_M4_QEI clock status register */
-  __I  uint32_t  RESERVED8[50];
-  __IO uint32_t  CLK_PERIPH_BUS_CFG;        /*!< (@ 0x40051700) CLK_PERIPH_BUS_CFG clock configuration register */
-  __I  uint32_t  CLK_PERIPH_BUS_STAT;       /*!< (@ 0x40051704) CLK_PERIPH_BUS_STAT clock status register */
-  __I  uint32_t  RESERVED9[2];
-  __IO uint32_t  CLK_PERIPH_CORE_CFG;       /*!< (@ 0x40051710) CLK_PERIPH_CORE_CFG clock configuration register */
-  __I  uint32_t  CLK_PERIPH_CORE_STAT;      /*!< (@ 0x40051714) CLK_CORE_BUS_STAT clock status register */
-  __IO uint32_t  CLK_PERIPH_SGPIO_CFG;      /*!< (@ 0x40051718) CLK_PERIPH_SGPIO_CFG clock configuration register */
-  __I  uint32_t  CLK_PERIPH_SGPIO_STAT;     /*!< (@ 0x4005171C) CLK_CORE_SGPIO_STAT clock status register */
-  __I  uint32_t  RESERVED10[56];
-  __IO uint32_t  CLK_USB0_CFG;              /*!< (@ 0x40051800) CLK_M4_USB0 clock configuration register */
-  __I  uint32_t  CLK_USB0_STAT;             /*!< (@ 0x40051804) CLK_USB0 clock status register */
-  __I  uint32_t  RESERVED11[62];
-  __IO uint32_t  CLK_USB1_CFG;              /*!< (@ 0x40051900) CLK_USB1 clock configuration register */
-  __I  uint32_t  CLK_USB1_STAT;             /*!< (@ 0x40051904) CLK_USB1 clock status register */
-  __I  uint32_t  RESERVED12[62];
-  __IO uint32_t  CLK_SPI_CFG;               /*!< (@ 0x40051A00) CLK_SPI clock configuration register */
-  __I  uint32_t  CLK_SPI_STAT;              /*!< (@ 0x40051A04) CLK_SPI clock status register */
-  __I  uint32_t  RESERVED13[62];
-  __IO uint32_t  CLK_VADC_CFG;              /*!< (@ 0x40051B00) CLK_VADC clock configuration register */
-  __I  uint32_t  CLK_VADC_STAT;             /*!< (@ 0x40051B04) CLK_VADC clock status register */
-} LPC_CCU1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         CCU2                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7  (CCU2)
-  */
-
-typedef struct {                            /*!< (@ 0x40052000) CCU2 Structure         */
-  __IO uint32_t  PM;                        /*!< (@ 0x40052000) Power mode register    */
-  __I  uint32_t  BASE_STAT;                 /*!< (@ 0x40052004) CCU base clocks status register */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  CLK_APLL_CFG;              /*!< (@ 0x40052100) CLK_APLL clock configuration register */
-  __I  uint32_t  CLK_APLL_STAT;             /*!< (@ 0x40052104) CLK_APLL clock status register */
-  __I  uint32_t  RESERVED1[62];
-  __IO uint32_t  CLK_APB2_USART3_CFG;       /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */
-  __I  uint32_t  CLK_APB2_USART3_STAT;      /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */
-  __I  uint32_t  RESERVED2[62];
-  __IO uint32_t  CLK_APB2_USART2_CFG;       /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */
-  __I  uint32_t  CLK_APB2_USART2_STAT;      /*!< (@ 0x40052304) CLK_APB2_USART clock status register */
-  __I  uint32_t  RESERVED3[62];
-  __IO uint32_t  CLK_APB0_UART1_CFG;        /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */
-  __I  uint32_t  CLK_APB0_UART1_STAT;       /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */
-  __I  uint32_t  RESERVED4[62];
-  __IO uint32_t  CLK_APB0_USART0_CFG;       /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */
-  __I  uint32_t  CLK_APB0_USART0_STAT;      /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */
-  __I  uint32_t  RESERVED5[62];
-  __IO uint32_t  CLK_APB2_SSP1_CFG;         /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */
-  __I  uint32_t  CLK_APB2_SSP1_STAT;        /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */
-  __I  uint32_t  RESERVED6[62];
-  __IO uint32_t  CLK_APB0_SSP0_CFG;         /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */
-  __I  uint32_t  CLK_APB0_SSP0_STAT;        /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */
-  __I  uint32_t  RESERVED7[62];
-  __IO uint32_t  CLK_SDIO_CFG;              /*!< (@ 0x40052800) CLK_SDIO clock configuration register */
-  __I  uint32_t  CLK_SDIO_STAT;             /*!< (@ 0x40052804) CLK_SDIO clock status register */
-} LPC_CCU2_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          RGU                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10503 Chapter title=LPC43xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13  (RGU)
-  */
-
-typedef struct {                            /*!< (@ 0x40053000) RGU Structure          */
-  __I  uint32_t  RESERVED0[64];
-  __O  uint32_t  RESET_CTRL0;               /*!< (@ 0x40053100) Reset control register 0 */
-  __O  uint32_t  RESET_CTRL1;               /*!< (@ 0x40053104) Reset control register 1 */
-  __I  uint32_t  RESERVED1[2];
-  __IO uint32_t  RESET_STATUS0;             /*!< (@ 0x40053110) Reset status register 0 */
-  __IO uint32_t  RESET_STATUS1;             /*!< (@ 0x40053114) Reset status register 1 */
-  __IO uint32_t  RESET_STATUS2;             /*!< (@ 0x40053118) Reset status register 2 */
-  __IO uint32_t  RESET_STATUS3;             /*!< (@ 0x4005311C) Reset status register 3 */
-  __I  uint32_t  RESERVED2[12];
-  __I  uint32_t  RESET_ACTIVE_STATUS0;      /*!< (@ 0x40053150) Reset active status register 0 */
-  __I  uint32_t  RESET_ACTIVE_STATUS1;      /*!< (@ 0x40053154) Reset active status register 1 */
-  __I  uint32_t  RESERVED3[170];
-  __IO uint32_t  RESET_EXT_STAT0;           /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */
-  __IO uint32_t  RESET_EXT_STAT1;           /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */
-  __IO uint32_t  RESET_EXT_STAT2;           /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */
-  __I  uint32_t  RESERVED4;
-  __IO uint32_t  RESET_EXT_STAT4;           /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */
-  __IO uint32_t  RESET_EXT_STAT5;           /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */
-  __I  uint32_t  RESERVED5[2];
-  __IO uint32_t  RESET_EXT_STAT8;           /*!< (@ 0x40053420) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT9;           /*!< (@ 0x40053424) Reset external status register */
-  __I  uint32_t  RESERVED6[3];
-  __IO uint32_t  RESET_EXT_STAT13;          /*!< (@ 0x40053434) Reset external status register */
-  __I  uint32_t  RESERVED7[2];
-  __IO uint32_t  RESET_EXT_STAT16;          /*!< (@ 0x40053440) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT17;          /*!< (@ 0x40053444) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT18;          /*!< (@ 0x40053448) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT19;          /*!< (@ 0x4005344C) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT20;          /*!< (@ 0x40053450) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT21;          /*!< (@ 0x40053454) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT22;          /*!< (@ 0x40053458) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT23;          /*!< (@ 0x4005345C) Reset external status register */
-  __I  uint32_t  RESERVED8[4];
-  __IO uint32_t  RESET_EXT_STAT28;          /*!< (@ 0x40053470) Reset external status register */
-  __I  uint32_t  RESERVED9[3];
-  __IO uint32_t  RESET_EXT_STAT32;          /*!< (@ 0x40053480) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT33;          /*!< (@ 0x40053484) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT34;          /*!< (@ 0x40053488) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT35;          /*!< (@ 0x4005348C) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT36;          /*!< (@ 0x40053490) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT37;          /*!< (@ 0x40053494) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT38;          /*!< (@ 0x40053498) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT39;          /*!< (@ 0x4005349C) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT40;          /*!< (@ 0x400534A0) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT41;          /*!< (@ 0x400534A4) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT42;          /*!< (@ 0x400534A8) Reset external status register */
-  __I  uint32_t  RESERVED10;
-  __IO uint32_t  RESET_EXT_STAT44;          /*!< (@ 0x400534B0) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT45;          /*!< (@ 0x400534B4) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT46;          /*!< (@ 0x400534B8) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT47;          /*!< (@ 0x400534BC) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT48;          /*!< (@ 0x400534C0) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT49;          /*!< (@ 0x400534C4) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT50;          /*!< (@ 0x400534C8) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT51;          /*!< (@ 0x400534CC) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT52;          /*!< (@ 0x400534D0) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT53;          /*!< (@ 0x400534D4) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT54;          /*!< (@ 0x400534D8) Reset external status register */
-  __IO uint32_t  RESET_EXT_STAT55;          /*!< (@ 0x400534DC) Reset external status register */
-} LPC_RGU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         WWDT                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (WWDT)
-  */
-
-typedef struct {                            /*!< (@ 0x40080000) WWDT Structure         */
-  __IO uint32_t  MOD;                       /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
-  __IO uint32_t  TC;                        /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */
-  __O  uint32_t  FEED;                      /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
-  __I  uint32_t  TV;                        /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
-  __I  uint32_t  RESERVED0;
-  __IO uint32_t  WARNINT;                   /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
-  __IO uint32_t  WINDOW;                    /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */
-} LPC_WWDT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        USARTn                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (USARTn)
-  */
-
-typedef struct {                            /*!< (@ 0x400xx000) USARTn Structure       */
-  
-  union {
-    __IO uint32_t  DLL;                     /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
-    __O  uint32_t  THR;                     /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
-    __I  uint32_t  RBR;                     /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
-  } ;
-  
-  union {
-    __IO uint32_t IER;                      /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
-    __IO uint32_t DLM;                      /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
-  } ;
-  
-  union {
-    __O  uint32_t FCR;                      /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */
-    __I  uint32_t IIR;                      /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
-  } ;
-  __IO uint32_t LCR;                        /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */
-  __I  uint32_t RESERVED0[1];
-  __I  uint32_t LSR;                        /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
-  __I  uint32_t RESERVED1[1];
-  __IO uint32_t SCR;                        /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */
-  __IO uint32_t ACR;                        /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
-  __IO uint32_t ICR;                        /*!< (@ 0x400xx024) IrDA control register (UART3 only) */
-  __IO uint32_t FDR;                        /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
-  __IO uint32_t OSR;                        /*!< (@ 0x400xx02C) Oversampling Register. Controls the degree of oversampling during each bit time. */
-  __I  uint32_t  RESERVED2[4];
-  __IO uint32_t HDEN;                       /*!< (@ 0x400xx03C) Half-duplex enable Register */
-  __I  uint32_t RESERVED3[1];
-  __IO uint32_t SCICTRL;                    /*!< (@ 0x400xx048) Smart card interface control register */
-  __IO uint32_t RS485CTRL;                  /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
-  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
-  __IO uint32_t RS485DLY;                   /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */
-  __IO uint32_t SYNCCTRL;                   /*!< (@ 0x400xx058) Synchronous mode control register. */
-  __IO uint32_t TER;                        /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
-} LPC_USARTn_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         UART1                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (UART1)
-  */
-
-typedef struct {                            /*!< (@ 0x40082000) UART1 Structure        */
-  
-  union {
-    __IO uint32_t  DLL;                     /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
-    __O  uint32_t  THR;                     /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
-    __I  uint32_t  RBR;                     /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
-  } ;
-  
-  union {
-    __IO uint32_t  IER;                     /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */
-    __IO uint32_t  DLM;                     /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */
-  } ;
-  
-  union {
-    __O  uint32_t  FCR;                     /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */
-    __I  uint32_t  IIR;                     /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
-  } ;
-  __IO uint32_t  LCR;                       /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */
-  __IO uint32_t  MCR;                       /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */
-  __I  uint32_t  LSR;                       /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
-  __I  uint32_t  MSR;                       /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */
-  __IO uint32_t  SCR;                       /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */
-  __IO uint32_t  ACR;                       /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
-  __I  uint32_t  RESERVED0;
-  __IO uint32_t  FDR;                       /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
-  __I  uint32_t  RESERVED1;
-  __IO uint32_t  TER;                       /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
-  __I  uint32_t  RESERVED2[6];
-  __IO uint32_t  RS485CTRL;                 /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
-  __IO uint32_t  RS485ADRMATCH;             /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
-  __IO uint32_t  RS485DLY;                  /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */
-  __I  uint32_t  FIFOLVL;                   /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs.  */
-} LPC_UART1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         SSPn                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (SSP0)
-  */
-
-typedef struct {                            /*!< (@ 0x400xx000) SSPn Structure         */
-  __IO uint32_t CR0;                        /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
-  __IO uint32_t CR1;                        /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */
-  __IO uint32_t DR;                         /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
-  __I  uint32_t SR;                         /*!< (@ 0x400xx00C) Status Register        */
-  __IO uint32_t CPSR;                       /*!< (@ 0x400xx010) Clock Prescale Register */
-  __IO uint32_t IMSC;                       /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */
-  __I  uint32_t RIS;                        /*!< (@ 0x400xx018) Raw Interrupt Status Register */
-  __I  uint32_t MIS;                        /*!< (@ 0x400xx01C) Masked Interrupt Status Register */
-  __O  uint32_t ICR;                        /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */
-  __IO uint32_t DMACR;                      /*!< (@ 0x400xx024) SSPn DMA control register */
-} LPC_SSPn_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        TIMERn                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (TIMERn)
-  */
-
-typedef struct {                            /*!< (@ 0x400xx000) TIMERn Structure       */
-  __IO uint32_t IR;                         /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
-  __IO uint32_t TCR;                        /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
-  __IO uint32_t TC;                         /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
-  __IO uint32_t PR;                         /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
-  __IO uint32_t PC;                         /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
-  __IO uint32_t MCR;                        /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
-  __IO uint32_t MR[4];                      /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
-  __IO uint32_t CCR;                        /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
-  __IO uint32_t CR[4];                      /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
-  __IO uint32_t EMR;                        /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
-  __I  uint32_t  RESERVED0[12];
-  __IO uint32_t CTCR;                       /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-} LPC_TIMERn_Type;
-
-
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          SCU                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10  (SCU)
-  */
-
-typedef struct {                            /*!< (@ 0x40086000) SCU Structure          */
-  __IO uint32_t  SFSP0_0;                   /*!< (@ 0x40086000) Pin configuration register for pins P0 */
-  __IO uint32_t  SFSP0_1;                   /*!< (@ 0x40086004) Pin configuration register for pins P0 */
-  __I  uint32_t  RESERVED0[30];
-  __IO uint32_t  SFSP1_0;                   /*!< (@ 0x40086080) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_1;                   /*!< (@ 0x40086084) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_2;                   /*!< (@ 0x40086088) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_3;                   /*!< (@ 0x4008608C) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_4;                   /*!< (@ 0x40086090) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_5;                   /*!< (@ 0x40086094) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_6;                   /*!< (@ 0x40086098) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_7;                   /*!< (@ 0x4008609C) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_8;                   /*!< (@ 0x400860A0) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_9;                   /*!< (@ 0x400860A4) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_10;                  /*!< (@ 0x400860A8) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_11;                  /*!< (@ 0x400860AC) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_12;                  /*!< (@ 0x400860B0) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_13;                  /*!< (@ 0x400860B4) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_14;                  /*!< (@ 0x400860B8) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_15;                  /*!< (@ 0x400860BC) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_16;                  /*!< (@ 0x400860C0) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_17;                  /*!< (@ 0x400860C4) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_18;                  /*!< (@ 0x400860C8) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_19;                  /*!< (@ 0x400860CC) Pin configuration register for pins P1 */
-  __IO uint32_t  SFSP1_20;                  /*!< (@ 0x400860D0) Pin configuration register for pins P1 */
-  __I  uint32_t  RESERVED1[11];
-  __IO uint32_t  SFSP2_0;                   /*!< (@ 0x40086100) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_1;                   /*!< (@ 0x40086104) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_2;                   /*!< (@ 0x40086108) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_3;                   /*!< (@ 0x4008610C) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_4;                   /*!< (@ 0x40086110) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_5;                   /*!< (@ 0x40086114) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_6;                   /*!< (@ 0x40086118) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_7;                   /*!< (@ 0x4008611C) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_8;                   /*!< (@ 0x40086120) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_9;                   /*!< (@ 0x40086124) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_10;                  /*!< (@ 0x40086128) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_11;                  /*!< (@ 0x4008612C) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_12;                  /*!< (@ 0x40086130) Pin configuration register for pins P2 */
-  __IO uint32_t  SFSP2_13;                  /*!< (@ 0x40086134) Pin configuration register for pins P2 */
-  __I  uint32_t  RESERVED2[18];
-  __IO uint32_t  SFSP3_0;                   /*!< (@ 0x40086180) Pin configuration register for pins P3 */
-  __IO uint32_t  SFSP3_1;                   /*!< (@ 0x40086184) Pin configuration register for pins P3 */
-  __IO uint32_t  SFSP3_2;                   /*!< (@ 0x40086188) Pin configuration register for pins P3 */
-  __IO uint32_t  SFSP3_3;                   /*!< (@ 0x4008618C) Pin configuration register for pins P3 */
-  __IO uint32_t  SFSP3_4;                   /*!< (@ 0x40086190) Pin configuration register for pins P3 */
-  __IO uint32_t  SFSP3_5;                   /*!< (@ 0x40086194) Pin configuration register for pins P3 */
-  __IO uint32_t  SFSP3_6;                   /*!< (@ 0x40086198) Pin configuration register for pins P3 */
-  __IO uint32_t  SFSP3_7;                   /*!< (@ 0x4008619C) Pin configuration register for pins P3 */
-  __IO uint32_t  SFSP3_8;                   /*!< (@ 0x400861A0) Pin configuration register for pins P3 */
-  __I  uint32_t  RESERVED3[23];
-  __IO uint32_t  SFSP4_0;                   /*!< (@ 0x40086200) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_1;                   /*!< (@ 0x40086204) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_2;                   /*!< (@ 0x40086208) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_3;                   /*!< (@ 0x4008620C) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_4;                   /*!< (@ 0x40086210) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_5;                   /*!< (@ 0x40086214) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_6;                   /*!< (@ 0x40086218) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_7;                   /*!< (@ 0x4008621C) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_8;                   /*!< (@ 0x40086220) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_9;                   /*!< (@ 0x40086224) Pin configuration register for pins P4 */
-  __IO uint32_t  SFSP4_10;                  /*!< (@ 0x40086228) Pin configuration register for pins P4 */
-  __I  uint32_t  RESERVED4[21];
-  __IO uint32_t  SFSP5_0;                   /*!< (@ 0x40086280) Pin configuration register for pins P5 */
-  __IO uint32_t  SFSP5_1;                   /*!< (@ 0x40086284) Pin configuration register for pins P5 */
-  __IO uint32_t  SFSP5_2;                   /*!< (@ 0x40086288) Pin configuration register for pins P5 */
-  __IO uint32_t  SFSP5_3;                   /*!< (@ 0x4008628C) Pin configuration register for pins P5 */
-  __IO uint32_t  SFSP5_4;                   /*!< (@ 0x40086290) Pin configuration register for pins P5 */
-  __IO uint32_t  SFSP5_5;                   /*!< (@ 0x40086294) Pin configuration register for pins P5 */
-  __IO uint32_t  SFSP5_6;                   /*!< (@ 0x40086298) Pin configuration register for pins P5 */
-  __IO uint32_t  SFSP5_7;                   /*!< (@ 0x4008629C) Pin configuration register for pins P5 */
-  __I  uint32_t  RESERVED5[24];
-  __IO uint32_t  SFSP6_0;                   /*!< (@ 0x40086300) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_1;                   /*!< (@ 0x40086304) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_2;                   /*!< (@ 0x40086308) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_3;                   /*!< (@ 0x4008630C) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_4;                   /*!< (@ 0x40086310) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_5;                   /*!< (@ 0x40086314) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_6;                   /*!< (@ 0x40086318) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_7;                   /*!< (@ 0x4008631C) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_8;                   /*!< (@ 0x40086320) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_9;                   /*!< (@ 0x40086324) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_10;                  /*!< (@ 0x40086328) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_11;                  /*!< (@ 0x4008632C) Pin configuration register for pins P6 */
-  __IO uint32_t  SFSP6_12;                  /*!< (@ 0x40086330) Pin configuration register for pins P6 */
-  __I  uint32_t  RESERVED6[19];
-  __IO uint32_t  SFSP7_0;                   /*!< (@ 0x40086380) Pin configuration register for pins P7 */
-  __IO uint32_t  SFSP7_1;                   /*!< (@ 0x40086384) Pin configuration register for pins P7 */
-  __IO uint32_t  SFSP7_2;                   /*!< (@ 0x40086388) Pin configuration register for pins P7 */
-  __IO uint32_t  SFSP7_3;                   /*!< (@ 0x4008638C) Pin configuration register for pins P7 */
-  __IO uint32_t  SFSP7_4;                   /*!< (@ 0x40086390) Pin configuration register for pins P7 */
-  __IO uint32_t  SFSP7_5;                   /*!< (@ 0x40086394) Pin configuration register for pins P7 */
-  __IO uint32_t  SFSP7_6;                   /*!< (@ 0x40086398) Pin configuration register for pins P7 */
-  __IO uint32_t  SFSP7_7;                   /*!< (@ 0x4008639C) Pin configuration register for pins P7 */
-  __I  uint32_t  RESERVED7[24];
-  __IO uint32_t  SFSP8_0;                   /*!< (@ 0x40086400) Pin configuration register for pins P8 */
-  __IO uint32_t  SFSP8_1;                   /*!< (@ 0x40086404) Pin configuration register for pins P8 */
-  __IO uint32_t  SFSP8_2;                   /*!< (@ 0x40086408) Pin configuration register for pins P8 */
-  __IO uint32_t  SFSP8_3;                   /*!< (@ 0x4008640C) Pin configuration register for pins P8 */
-  __IO uint32_t  SFSP8_4;                   /*!< (@ 0x40086410) Pin configuration register for pins P8 */
-  __IO uint32_t  SFSP8_5;                   /*!< (@ 0x40086414) Pin configuration register for pins P8 */
-  __IO uint32_t  SFSP8_6;                   /*!< (@ 0x40086418) Pin configuration register for pins P8 */
-  __IO uint32_t  SFSP8_7;                   /*!< (@ 0x4008641C) Pin configuration register for pins P8 */
-  __IO uint32_t  SFSP8_8;                   /*!< (@ 0x40086420) Pin configuration register for pins P8 */
-  __I  uint32_t  RESERVED8[23];
-  __IO uint32_t  SFSP9_0;                   /*!< (@ 0x40086480) Pin configuration register for pins P9 */
-  __IO uint32_t  SFSP9_1;                   /*!< (@ 0x40086484) Pin configuration register for pins P9 */
-  __IO uint32_t  SFSP9_2;                   /*!< (@ 0x40086488) Pin configuration register for pins P9 */
-  __IO uint32_t  SFSP9_3;                   /*!< (@ 0x4008648C) Pin configuration register for pins P9 */
-  __IO uint32_t  SFSP9_4;                   /*!< (@ 0x40086490) Pin configuration register for pins P9 */
-  __IO uint32_t  SFSP9_5;                   /*!< (@ 0x40086494) Pin configuration register for pins P9 */
-  __IO uint32_t  SFSP9_6;                   /*!< (@ 0x40086498) Pin configuration register for pins P9 */
-  __I  uint32_t  RESERVED9[25];
-  __IO uint32_t  SFSPA_0;                   /*!< (@ 0x40086500) Pin configuration register for pins PA */
-  __IO uint32_t  SFSPA_1;                   /*!< (@ 0x40086504) Pin configuration register for pins PA */
-  __IO uint32_t  SFSPA_2;                   /*!< (@ 0x40086508) Pin configuration register for pins PA */
-  __IO uint32_t  SFSPA_3;                   /*!< (@ 0x4008650C) Pin configuration register for pins PA */
-  __IO uint32_t  SFSPA_4;                   /*!< (@ 0x40086510) Pin configuration register for pins PA */
-  __I  uint32_t  RESERVED10[27];
-  __IO uint32_t  SFSPB_0;                   /*!< (@ 0x40086580) Pin configuration register for pins PB */
-  __IO uint32_t  SFSPB_1;                   /*!< (@ 0x40086584) Pin configuration register for pins PB */
-  __IO uint32_t  SFSPB_2;                   /*!< (@ 0x40086588) Pin configuration register for pins PB */
-  __IO uint32_t  SFSPB_3;                   /*!< (@ 0x4008658C) Pin configuration register for pins PB */
-  __IO uint32_t  SFSPB_4;                   /*!< (@ 0x40086590) Pin configuration register for pins PB */
-  __IO uint32_t  SFSPB_5;                   /*!< (@ 0x40086594) Pin configuration register for pins PB */
-  __IO uint32_t  SFSPB_6;                   /*!< (@ 0x40086598) Pin configuration register for pins PB */
-  __I  uint32_t  RESERVED11[25];
-  __IO uint32_t  SFSPC_0;                   /*!< (@ 0x40086600) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_1;                   /*!< (@ 0x40086604) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_2;                   /*!< (@ 0x40086608) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_3;                   /*!< (@ 0x4008660C) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_4;                   /*!< (@ 0x40086610) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_5;                   /*!< (@ 0x40086614) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_6;                   /*!< (@ 0x40086618) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_7;                   /*!< (@ 0x4008661C) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_8;                   /*!< (@ 0x40086620) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_9;                   /*!< (@ 0x40086624) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_10;                  /*!< (@ 0x40086628) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_11;                  /*!< (@ 0x4008662C) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_12;                  /*!< (@ 0x40086630) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_13;                  /*!< (@ 0x40086634) Pin configuration register for pins PC */
-  __IO uint32_t  SFSPC_14;                  /*!< (@ 0x40086638) Pin configuration register for pins PC */
-  __I  uint32_t  RESERVED12[17];
-  __IO uint32_t  SFSPD_0;                   /*!< (@ 0x40086680) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_1;                   /*!< (@ 0x40086684) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_2;                   /*!< (@ 0x40086688) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_3;                   /*!< (@ 0x4008668C) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_4;                   /*!< (@ 0x40086690) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_5;                   /*!< (@ 0x40086694) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_6;                   /*!< (@ 0x40086698) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_7;                   /*!< (@ 0x4008669C) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_8;                   /*!< (@ 0x400866A0) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_9;                   /*!< (@ 0x400866A4) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_10;                  /*!< (@ 0x400866A8) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_11;                  /*!< (@ 0x400866AC) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_12;                  /*!< (@ 0x400866B0) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_13;                  /*!< (@ 0x400866B4) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_14;                  /*!< (@ 0x400866B8) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_15;                  /*!< (@ 0x400866BC) Pin configuration register for pins PD */
-  __IO uint32_t  SFSPD_16;                  /*!< (@ 0x400866C0) Pin configuration register for pins PD */
-  __I  uint32_t  RESERVED13[15];
-  __IO uint32_t  SFSPE_0;                   /*!< (@ 0x40086700) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_1;                   /*!< (@ 0x40086704) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_2;                   /*!< (@ 0x40086708) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_3;                   /*!< (@ 0x4008670C) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_4;                   /*!< (@ 0x40086710) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_5;                   /*!< (@ 0x40086714) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_6;                   /*!< (@ 0x40086718) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_7;                   /*!< (@ 0x4008671C) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_8;                   /*!< (@ 0x40086720) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_9;                   /*!< (@ 0x40086724) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_10;                  /*!< (@ 0x40086728) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_11;                  /*!< (@ 0x4008672C) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_12;                  /*!< (@ 0x40086730) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_13;                  /*!< (@ 0x40086734) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_14;                  /*!< (@ 0x40086738) Pin configuration register for pins PE */
-  __IO uint32_t  SFSPE_15;                  /*!< (@ 0x4008673C) Pin configuration register for pins PE */
-  __I  uint32_t  RESERVED14[16];
-  __IO uint32_t  SFSPF_0;                   /*!< (@ 0x40086780) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_1;                   /*!< (@ 0x40086784) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_2;                   /*!< (@ 0x40086788) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_3;                   /*!< (@ 0x4008678C) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_4;                   /*!< (@ 0x40086790) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_5;                   /*!< (@ 0x40086794) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_6;                   /*!< (@ 0x40086798) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_7;                   /*!< (@ 0x4008679C) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_8;                   /*!< (@ 0x400867A0) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_9;                   /*!< (@ 0x400867A4) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_10;                  /*!< (@ 0x400867A8) Pin configuration register for pins PF */
-  __IO uint32_t  SFSPF_11;                  /*!< (@ 0x400867AC) Pin configuration register for pins PF */
-  __I  uint32_t  RESERVED15[276];
-  __IO uint32_t  SFSCLK_0;                  /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */
-  __IO uint32_t  SFSCLK_1;                  /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */
-  __IO uint32_t  SFSCLK_2;                  /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */
-  __IO uint32_t  SFSCLK_3;                  /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */
-  __I  uint32_t  RESERVED16[28];
-  __IO uint32_t  SFSUSB;                    /*!< (@ 0x40086C80) Pin configuration register for */
-  __IO uint32_t  SFSI2C0;                   /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */
-  __IO uint32_t  ENAIO0;                    /*!< (@ 0x40086C88) ADC0 function select register */
-  __IO uint32_t  ENAIO1;                    /*!< (@ 0x40086C8C) ADC1 function select register */
-  __IO uint32_t  ENAIO2;                    /*!< (@ 0x40086C90) Analog function select register */
-  __I  uint32_t  RESERVED17[27];
-  __IO uint32_t  EMCDELAYCLK;               /*!< (@ 0x40086D00) EMC clock delay register */
-  __I  uint32_t  RESERVED18[63];
-  __IO uint32_t  PINTSEL0;                  /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */
-  __IO uint32_t  PINTSEL1;                  /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */
-} LPC_SCU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                     GPIO_PIN_INT                                     -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief GPIO pin interrupt (GPIO_PIN_INT)
-  */
-
-typedef struct {                            /*!< (@ 0x40087000) GPIO_PIN_INT Structure */
-  __IO uint32_t  ISEL;                      /*!< (@ 0x40087000) Pin Interrupt Mode register */
-  __IO uint32_t  IENR;                      /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */
-  __O  uint32_t  SIENR;                     /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */
-  __O  uint32_t  CIENR;                     /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */
-  __IO uint32_t  IENF;                      /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */
-  __O  uint32_t  SIENF;                     /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */
-  __O  uint32_t  CIENF;                     /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
-  __IO uint32_t  RISE;                      /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */
-  __IO uint32_t  FALL;                      /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */
-  __IO uint32_t  IST;                       /*!< (@ 0x40087024) Pin Interrupt Status register */
-} LPC_GPIO_PIN_INT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                    GPIO_GROUP_INTn                                   -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn)
-  */
-
-typedef struct {                            /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */
-  __IO uint32_t  CTRL;                      /*!< (@ 0x40088000) GPIO grouped interrupt control register */
-  __I  uint32_t  RESERVED0[7];
-  __IO uint32_t  PORT_POL0;                 /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */
-  __IO uint32_t  PORT_POL1;                 /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */
-  __IO uint32_t  PORT_POL2;                 /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */
-  __IO uint32_t  PORT_POL3;                 /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */
-  __IO uint32_t  PORT_POL4;                 /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */
-  __IO uint32_t  PORT_POL5;                 /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */
-  __IO uint32_t  PORT_POL6;                 /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */
-  __IO uint32_t  PORT_POL7;                 /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */
-  __IO uint32_t  PORT_ENA0;                 /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */
-  __IO uint32_t  PORT_ENA1;                 /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */
-  __IO uint32_t  PORT_ENA2;                 /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */
-  __IO uint32_t  PORT_ENA3;                 /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */
-  __IO uint32_t  PORT_ENA4;                 /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */
-  __IO uint32_t  PORT_ENA5;                 /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */
-  __IO uint32_t  PORT_ENA6;                 /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */
-  __IO uint32_t  PORT_ENA7;                 /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */
-} LPC_GPIO_GROUP_INTn_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         MCPWM                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7  (MCPWM)
-  */
-
-typedef struct {                            /*!< (@ 0x400A0000) MCPWM Structure        */
-  __I  uint32_t  CON;                       /*!< (@ 0x400A0000) PWM Control read address */
-  __O  uint32_t  CON_SET;                   /*!< (@ 0x400A0004) PWM Control set address */
-  __O  uint32_t  CON_CLR;                   /*!< (@ 0x400A0008) PWM Control clear address */
-  __I  uint32_t  CAPCON;                    /*!< (@ 0x400A000C) Capture Control read address */
-  __O  uint32_t  CAPCON_SET;                /*!< (@ 0x400A0010) Capture Control set address */
-  __O  uint32_t  CAPCON_CLR;                /*!< (@ 0x400A0014) Event Control clear address */
-  __IO uint32_t TC[3];                      /*!< (@ 0x400A0018) Timer Counter register */
-  __IO uint32_t LIM[3];                     /*!< (@ 0x400A0024) Limit register         */
-  __IO uint32_t MAT[3];                     /*!< (@ 0x400A0030) Match register         */
-  __IO uint32_t  DT;                        /*!< (@ 0x400A003C) Dead time register     */
-  __IO uint32_t  CCP;                       /*!< (@ 0x400A0040) Communication Pattern register */
-  __I  uint32_t CAP[3];                     /*!< (@ 0x400A0044) Capture register       */
-  __I  uint32_t  INTEN;                     /*!< (@ 0x400A0050) Interrupt Enable read address */
-  __O  uint32_t  INTEN_SET;                 /*!< (@ 0x400A0054) Interrupt Enable set address */
-  __O  uint32_t  INTEN_CLR;                 /*!< (@ 0x400A0058) Interrupt Enable clear address */
-  __I  uint32_t  CNTCON;                    /*!< (@ 0x400A005C) Count Control read address */
-  __O  uint32_t  CNTCON_SET;                /*!< (@ 0x400A0060) Count Control set address */
-  __O  uint32_t  CNTCON_CLR;                /*!< (@ 0x400A0064) Count Control clear address */
-  __I  uint32_t  INTF;                      /*!< (@ 0x400A0068) Interrupt flags read address */
-  __O  uint32_t  INTF_SET;                  /*!< (@ 0x400A006C) Interrupt flags set address */
-  __O  uint32_t  INTF_CLR;                  /*!< (@ 0x400A0070) Interrupt flags clear address */
-  __O  uint32_t  CAP_CLR;                   /*!< (@ 0x400A0074) Capture clear address  */
-} LPC_MCPWM_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         I2C0                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx I2C-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Cn)
-  */
-
-typedef struct {                            /*!< (@ 0x400xx000) I2C0 Structure         */
-  __IO uint32_t CONSET;                     /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
-  __I  uint32_t STAT;                       /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
-  __IO uint32_t DAT;                        /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
-  __IO uint32_t ADR0;                       /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  __IO uint32_t SCLH;                       /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
-  __IO uint32_t SCLL;                       /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
-  __O  uint32_t CONCLR;                     /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
-  __IO uint32_t MMCTRL;                     /*!< (@ 0x400xx01C) Monitor mode control register. */
-  __IO uint32_t ADR1;                       /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  __IO uint32_t ADR2;                       /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  __IO uint32_t ADR3;                       /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
-  __IO uint32_t MASK[4];                    /*!< (@ 0x400xx030) I2C Slave address mask register */
-} LPC_I2Cn_Type;
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         I2Sn                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Sn)
-    0x400A2000 / 0x400A3000
-  */
-
-typedef struct {                            /*!< (@ 0x400Ax000) I2S Structure         */
-  __IO uint32_t DAO;                        /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */
-  __IO uint32_t DAI;                        /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */
-  __O  uint32_t TXFIFO;                     /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */
-  __I  uint32_t RXFIFO;                     /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */
-  __I  uint32_t STATE;                      /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */
-  __IO uint32_t DMA1;                       /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */
-  __IO uint32_t DMA2;                       /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */
-  __IO uint32_t IRQ;                        /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */
-  __IO uint32_t TXRATE;                     /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
-  __IO uint32_t RXRATE;                     /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
-  __IO uint32_t TXBITRATE;                  /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */
-  __IO uint32_t RXBITRATE;                  /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */
-  __IO uint32_t TXMODE;                     /*!< (@ 0x400Ax030) I2S Transmit mode control. */
-  __IO uint32_t RXMODE;                     /*!< (@ 0x400Ax034) I2S Receive mode control. */
-} LPC_I2Sn_Type;
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        C_CANn                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7  (C_CANn)
-    0x400A4000 / 0x400E2000
-  */
-
-typedef struct {                            /*!< (@ 0x400E2000) C_CAN Structure       */
-  __IO uint32_t CNTL;                       /*!< (@ 0x400E2000) CAN control            */
-  __IO uint32_t STAT;                       /*!< (@ 0x400E2004) Status register        */
-  __I  uint32_t EC;                         /*!< (@ 0x400E2008) Error counter          */
-  __IO uint32_t BT;                         /*!< (@ 0x400E200C) Bit timing register    */
-  __I  uint32_t INT;                        /*!< (@ 0x400E2010) Interrupt register     */
-  __IO uint32_t TEST;                       /*!< (@ 0x400E2014) Test register          */
-  __IO uint32_t BRPE;                       /*!< (@ 0x400E2018) Baud rate prescaler extension register */
-  __I  uint32_t  RESERVED0;
-  __IO uint32_t IF1_CMDREQ;                 /*!< (@ 0x400E2020) Message interface command request  */
-  
-  union {
-    __IO uint32_t IF1_CMDMSK_R;             /*!< (@ 0x400E2024) Message interface command mask (read direction) */
-    __IO uint32_t IF1_CMDMSK_W;             /*!< (@ 0x400E2024) Message interface command mask (write direction) */
-  } ;
-  __IO uint32_t IF1_MSK1;                   /*!< (@ 0x400E2028) Message interface mask 1 */
-  __IO uint32_t IF1_MSK2;                   /*!< (@ 0x400E202C) Message interface 1 mask 2 */
-  __IO uint32_t IF1_ARB1;                   /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */
-  __IO uint32_t IF1_ARB2;                   /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */
-  __IO uint32_t IF1_MCTRL;                  /*!< (@ 0x400E2038) Message interface 1 message control */
-  __IO uint32_t IF1_DA1;                    /*!< (@ 0x400E203C) Message interface data A1 */
-  __IO uint32_t IF1_DA2;                    /*!< (@ 0x400E2040) Message interface 1 data A2 */
-  __IO uint32_t IF1_DB1;                    /*!< (@ 0x400E2044) Message interface 1 data B1 */
-  __IO uint32_t IF1_DB2;                    /*!< (@ 0x400E2048) Message interface 1 data B2 */
-  __I  uint32_t  RESERVED1[13];
-  __IO uint32_t IF2_CMDREQ;                 /*!< (@ 0x400E2080) Message interface command request  */
-  
-  union {
-    __IO uint32_t IF2_CMDMSK_R;             /*!< (@ 0x400E2084) Message interface command mask (read direction) */
-    __IO uint32_t IF2_CMDMSK_W;             /*!< (@ 0x400E2084) Message interface command mask (write direction) */
-  } ;
-  __IO uint32_t IF2_MSK1;                   /*!< (@ 0x400E2088) Message interface mask 1 */
-  __IO uint32_t IF2_MSK2;                   /*!< (@ 0x400E208C) Message interface 1 mask 2 */
-  __IO uint32_t IF2_ARB1;                   /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */
-  __IO uint32_t IF2_ARB2;                   /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */
-  __IO uint32_t IF2_MCTRL;                  /*!< (@ 0x400E2098) Message interface 1 message control */
-  __IO uint32_t IF2_DA1;                    /*!< (@ 0x400E209C) Message interface data A1 */
-  __IO uint32_t IF2_DA2;                    /*!< (@ 0x400E20A0) Message interface 1 data A2 */
-  __IO uint32_t IF2_DB1;                    /*!< (@ 0x400E20A4) Message interface 1 data B1 */
-  __IO uint32_t IF2_DB2;                    /*!< (@ 0x400E20A8) Message interface 1 data B2 */
-  __I  uint32_t  RESERVED2[21];
-  __I  uint32_t TXREQ1;                     /*!< (@ 0x400E2100) Transmission request 1 */
-  __I  uint32_t TXREQ2;                     /*!< (@ 0x400E2104) Transmission request 2 */
-  __I  uint32_t  RESERVED3[6];
-  __I  uint32_t ND1;                        /*!< (@ 0x400E2120) New data 1             */
-  __I  uint32_t ND2;                        /*!< (@ 0x400E2124) New data 2             */
-  __I  uint32_t  RESERVED4[6];
-  __I  uint32_t IR1;                        /*!< (@ 0x400E2140) Interrupt pending 1    */
-  __I  uint32_t IR2;                        /*!< (@ 0x400E2144) Interrupt pending 2    */
-  __I  uint32_t  RESERVED5[6];
-  __I  uint32_t MSGV1;                      /*!< (@ 0x400E2160) Message valid 1        */
-  __I  uint32_t MSGV2;                      /*!< (@ 0x400E2164) Message valid 2        */
-  __I  uint32_t  RESERVED6[6];
-  __IO uint32_t CLKDIV;                     /*!< (@ 0x400E2180) CAN clock divider register */
-} LPC_C_CANn_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        RITIMER                                       -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (RITIMER)
-  */
-
-typedef struct {                            /*!< (@ 0x400C0000) RITIMER Structure      */
-  __IO uint32_t  COMPVAL;                   /*!< (@ 0x400C0000) Compare register       */
-  __IO uint32_t  MASK;                      /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
-  __IO uint32_t  CTRL;                      /*!< (@ 0x400C0008) Control register.      */
-  __IO uint32_t  COUNTER;                   /*!< (@ 0x400C000C) 32-bit counter         */
-} LPC_RITIMER_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          QEI                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7  (QEI)
-  */
-
-typedef struct {                            /*!< (@ 0x400C6000) QEI Structure          */
-  __O  uint32_t  CON;                       /*!< (@ 0x400C6000) Control register       */
-  __I  uint32_t  STAT;                      /*!< (@ 0x400C6004) Encoder status register */
-  __IO uint32_t  CONF;                      /*!< (@ 0x400C6008) Configuration register */
-  __I  uint32_t  POS;                       /*!< (@ 0x400C600C) Position register      */
-  __IO uint32_t  MAXPOS;                    /*!< (@ 0x400C6010) Maximum position register */
-  __IO uint32_t  CMPOS0;                    /*!< (@ 0x400C6014) position compare register 0 */
-  __IO uint32_t  CMPOS1;                    /*!< (@ 0x400C6018) position compare register 1 */
-  __IO uint32_t  CMPOS2;                    /*!< (@ 0x400C601C) position compare register 2 */
-  __I  uint32_t  INXCNT;                    /*!< (@ 0x400C6020) Index count register   */
-  __IO uint32_t  INXCMP0;                   /*!< (@ 0x400C6024) Index compare register 0 */
-  __IO uint32_t  LOAD;                      /*!< (@ 0x400C6028) Velocity timer reload register */
-  __I  uint32_t  TIME;                      /*!< (@ 0x400C602C) Velocity timer register */
-  __I  uint32_t  VEL;                       /*!< (@ 0x400C6030) Velocity counter register */
-  __I  uint32_t  CAP;                       /*!< (@ 0x400C6034) Velocity capture register */
-  __IO uint32_t  VELCOMP;                   /*!< (@ 0x400C6038) Velocity compare register */
-  __IO uint32_t  FILTERPHA;                 /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */
-  __IO uint32_t  FILTERPHB;                 /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */
-  __IO uint32_t  FILTERINX;                 /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */
-  __IO uint32_t  WINDOW;                    /*!< (@ 0x400C6048) Index acceptance window register */
-  __IO uint32_t  INXCMP1;                   /*!< (@ 0x400C604C) Index compare register 1 */
-  __IO uint32_t  INXCMP2;                   /*!< (@ 0x400C6050) Index compare register 2 */
-  __I  uint32_t  RESERVED0[993];
-  __O  uint32_t  IEC;                       /*!< (@ 0x400C6FD8) Interrupt enable clear register */
-  __O  uint32_t  IES;                       /*!< (@ 0x400C6FDC) Interrupt enable set register */
-  __I  uint32_t  INTSTAT;                   /*!< (@ 0x400C6FE0) Interrupt status register */
-  __I  uint32_t  IE;                        /*!< (@ 0x400C6FE4) Interrupt enable register */
-  __O  uint32_t  CLR;                       /*!< (@ 0x400C6FE8) Interrupt status clear register */
-  __O  uint32_t  SET;                       /*!< (@ 0x400C6FEC) Interrupt status set register */
-} LPC_QEI_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         GIMA                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10503 Chapter title=LPC43xx Global Input Multiplexer Array (GIMA) Modification date=10/7/2011 Major revision=0 Minor revision=3  (GIMA)
-  */
-
-typedef struct {                            /*!< (@ 0x400C7000) GIMA Structure         */
-  __IO uint32_t  CAP0_0_IN;                 /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
-  __IO uint32_t  CAP0_1_IN;                 /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
-  __IO uint32_t  CAP0_2_IN;                 /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
-  __IO uint32_t  CAP0_3_IN;                 /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
-  __IO uint32_t  CAP1_0_IN;                 /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
-  __IO uint32_t  CAP1_1_IN;                 /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
-  __IO uint32_t  CAP1_2_IN;                 /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
-  __IO uint32_t  CAP1_3_IN;                 /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
-  __IO uint32_t  CAP2_0_IN;                 /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
-  __IO uint32_t  CAP2_1_IN;                 /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
-  __IO uint32_t  CAP2_2_IN;                 /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
-  __IO uint32_t  CAP2_3_IN;                 /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
-  __IO uint32_t  CAP3_0_IN;                 /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
-  __IO uint32_t  CAP3_1_IN;                 /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
-  __IO uint32_t  CAP3_2_IN;                 /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
-  __IO uint32_t  CAP3_3_IN;                 /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
-  __IO uint32_t  CTIN_0_IN;                 /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */
-  __IO uint32_t  CTIN_1_IN;                 /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */
-  __IO uint32_t  CTIN_2_IN;                 /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */
-  __IO uint32_t  CTIN_3_IN;                 /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */
-  __IO uint32_t  CTIN_4_IN;                 /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */
-  __IO uint32_t  CTIN_5_IN;                 /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */
-  __IO uint32_t  CTIN_6_IN;                 /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */
-  __IO uint32_t  CTIN_7_IN;                 /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */
-  __IO uint32_t  VADC_TRIGGER_IN;           /*!< (@ 0x400C7060) VADC trigger input multiplexer (GIMA output 24) */
-  __IO uint32_t  EVENTROUTER_13_IN;         /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */
-  __IO uint32_t  EVENTROUTER_14_IN;         /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */
-  __IO uint32_t  EVENTROUTER_16_IN;         /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */
-  __IO uint32_t  ADCSTART0_IN;              /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */
-  __IO uint32_t  ADCSTART1_IN;              /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */
-} LPC_GIMA_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          DAC                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7  (DAC)
-  */
-
-typedef struct {                            /*!< (@ 0x400E1000) DAC Structure          */
-  __IO uint32_t  CR;                        /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */
-  __IO uint32_t  CTRL;                      /*!< (@ 0x400E1004) DAC control register.  */
-  __IO uint32_t  CNTVAL;                    /*!< (@ 0x400E1008) DAC counter value register. */
-} LPC_DAC_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         ADCn                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7  (ADCn)
-    0x400E3000 / 0x400E4000
-  */
-
-typedef struct {                            /*!< (@ 0x400Ex000) ADCn Structure         */
-  __IO uint32_t CR;                         /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
-  __I  uint32_t GDR;                        /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
-  __I  uint32_t  RESERVED0;
-  __IO uint32_t INTEN;                      /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
-  __I  uint32_t DR[8];                      /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
-  __I  uint32_t STAT;                       /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
-} LPC_ADCn_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       GPIO_PORT                                      -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief GPIO port  (GPIO_PORT)
-  */
-
-typedef struct {                            /*!< (@ 0x400F4000) GPIO_PORT Structure    */
-  __IO uint8_t B[256];                      /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */
-  __I  uint32_t  RESERVED0[960];
-  __IO uint32_t W[256];                     /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */
-  __I  uint32_t  RESERVED1[768];
-  __IO uint32_t DIR[8];                     /*!< (@ 0x400F6000) Direction registers port n */
-  __I  uint32_t  RESERVED2[24];
-  __IO uint32_t MASK[8];                    /*!< (@ 0x400F6080) Mask register port n   */
-  __I  uint32_t  RESERVED3[24];
-  __IO uint32_t PIN[8];                     /*!< (@ 0x400F6100) Portpin register port n */
-  __I  uint32_t  RESERVED4[24];
-  __IO uint32_t MPIN[8];                    /*!< (@ 0x400F6180) Masked port register port n */
-  __I  uint32_t  RESERVED5[24];
-  __IO uint32_t SET[8];                     /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */
-  __I  uint32_t  RESERVED6[24];
-  __O  uint32_t CLR[8];                     /*!< (@ 0x400F6280) Clear port n           */
-  __I  uint32_t  RESERVED7[24];
-  __O  uint32_t NOT[8];                     /*!< (@ 0x400F6300) Toggle port n          */
-} LPC_GPIO_PORT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          SPI                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10503 Chapter title=LPC43xxSPI Modification date=10/7/2011 Major revision=0 Minor revision=3  (SPI)
-  */
-
-typedef struct {                            /*!< (@ 0x40100000) SPI Structure          */
-  __IO uint32_t  CR;                        /*!< (@ 0x40100000) SPI Control Register. This register controls the operation of the SPI. */
-  __I  uint32_t  SR;                        /*!< (@ 0x40100004) SPI Status Register. This register shows the status of the SPI. */
-  __IO uint32_t  DR;                        /*!< (@ 0x40100008) SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
-  __IO uint32_t  CCR;                       /*!< (@ 0x4010000C) SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
-  __IO uint32_t  TCR;                       /*!< (@ 0x40100010) SPI Test Control register. For functional testing only. */
-  __IO uint32_t  TSR;                       /*!< (@ 0x40100014) SPI Test Status register. For functional testing only. */
-  __I  uint32_t  RESERVED0;
-  __IO uint32_t  INT;                       /*!< (@ 0x4010001C) SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
-} LPC_SPI_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         SGPIO                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10503 Chapter title=LPC43xx SerialGPIO (SGPIO) Modification date=10/7/2011 Major revision=0 Minor revision=3  (SGPIO)
-  */
-
-typedef struct {                            /*!< (@ 0x40101000) SGPIO Structure        */
-  __IO uint32_t  OUT_MUX_CFG[16];              /*!< (@ 0x40101000) Pin multiplexer configurationregisters. */
-  __IO uint32_t  SGPIO_MUX_CFG[16];            /*!< (@ 0x40101040) SGPIO multiplexer configuration registers. */
-  __IO uint32_t  SLICE_MUX_CFG[16];            /*!< (@ 0x40101080) Slice multiplexer configuration registers. */
-  __IO uint32_t  REG[16];                      /*!< (@ 0x401010C0) Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
-  __IO uint32_t  REG_SS[16];                   /*!< (@ 0x40101100) Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
-  __IO uint32_t  PRESET[16];                   /*!< (@ 0x40101140) Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
-  __IO uint32_t  COUNT[16];                    /*!< (@ 0x40101180) Down counter, counts down each clock cycle. */
-  __IO uint32_t  POS[16];                      /*!< (@ 0x401011C0) Each time COUNT0 reaches 0x0 */
-  __IO uint32_t  MASK_A;                    /*!< (@ 0x40101200) Mask for pattern match function of slice A */
-  __IO uint32_t  MASK_H;                    /*!< (@ 0x40101204) Mask for pattern match function of slice H */
-  __IO uint32_t  MASK_I;                    /*!< (@ 0x40101208) Mask for pattern match function of slice I */
-  __IO uint32_t  MASK_P;                    /*!< (@ 0x4010120C) Mask for pattern match function of slice P */
-  __I  uint32_t  GPIO_INREG;                /*!< (@ 0x40101210) GPIO input status register */
-  __IO uint32_t  GPIO_OUTREG;               /*!< (@ 0x40101214) GPIO output control register */
-  __IO uint32_t  GPIO_OENREG;               /*!< (@ 0x40101218) GPIO OE control register */
-  __IO uint32_t  CTRL_ENABLED;              /*!< (@ 0x4010121C) Enables the slice COUNT counter */
-  __IO uint32_t  CTRL_DISABLED;             /*!< (@ 0x40101220) Disables the slice COUNT counter */
-  __I  uint32_t  RESERVED0[823];
-  __O  uint32_t  CLR_EN_0;                  /*!< (@ 0x40101F00) Shift clock interrupt clear mask */
-  __O  uint32_t  SET_EN_0;                  /*!< (@ 0x40101F04) Shift clock interrupt set mask */
-  __I  uint32_t  ENABLE_0;                  /*!< (@ 0x40101F08) Shift clock interrupt enable */
-  __I  uint32_t  STATUS_0;                  /*!< (@ 0x40101F0C) Shift clock interrupt status */
-  __O  uint32_t  CTR_STATUS_0;              /*!< (@ 0x40101F10) Shift clock interrupt clear status */
-  __O  uint32_t  SET_STATUS_0;              /*!< (@ 0x40101F14) Shift clock interrupt set status */
-  __I  uint32_t  RESERVED1[2];
-  __O  uint32_t  CLR_EN_1;                  /*!< (@ 0x40101F20) Capture clock interrupt clear mask */
-  __O  uint32_t  SET_EN_1;                  /*!< (@ 0x40101F24) Capture clock interrupt set mask */
-  __I  uint32_t  ENABLE_1;                  /*!< (@ 0x40101F28) Capture clock interrupt enable */
-  __I  uint32_t  STATUS_1;                  /*!< (@ 0x40101F2C) Capture clock interrupt status */
-  __O  uint32_t  CTR_STATUS_1;              /*!< (@ 0x40101F30) Capture clock interrupt clear status */
-  __O  uint32_t  SET_STATUS_1;              /*!< (@ 0x40101F34) Capture clock interrupt set status */
-  __I  uint32_t  RESERVED2[2];
-  __O  uint32_t  CLR_EN_2;                  /*!< (@ 0x40101F40) Pattern match interrupt clear mask */
-  __O  uint32_t  SET_EN_2;                  /*!< (@ 0x40101F44) Pattern match interrupt set mask */
-  __I  uint32_t  ENABLE_2;                  /*!< (@ 0x40101F48) Pattern match interrupt enable */
-  __I  uint32_t  STATUS_2;                  /*!< (@ 0x40101F4C) Pattern match interrupt status */
-  __O  uint32_t  CTR_STATUS_2;              /*!< (@ 0x40101F50) Pattern match interrupt clear status */
-  __O  uint32_t  SET_STATUS_2;              /*!< (@ 0x40101F54) Pattern match interrupt set status */
-  __I  uint32_t  RESERVED3[2];
-  __O  uint32_t  CLR_EN_3;                  /*!< (@ 0x40101F60) Input interrupt clear mask */
-  __O  uint32_t  SET_EN_3;                  /*!< (@ 0x40101F64) Input bit match interrupt set mask */
-  __I  uint32_t  ENABLE_3;                  /*!< (@ 0x40101F68) Input bit match interrupt enable */
-  __I  uint32_t  STATUS_3;                  /*!< (@ 0x40101F6C) Input bit match interrupt status */
-  __O  uint32_t  CTR_STATUS_3;              /*!< (@ 0x40101F70) Input bit match interrupt clear status */
-  __O  uint32_t  SET_STATUS_3;              /*!< (@ 0x40101F74) Shift clock interrupt set status */
-} LPC_SGPIO_Type;
-
-
-
-/********************************************
-** End of section using anonymous unions   **
-*********************************************/
-
-#if defined(__ARMCC_VERSION)
-  #pragma pop
-#elif defined(__CWCC__)
-  #pragma pop
-#elif defined(__GNUC__)
-  /* leave anonymous unions enabled */
-#elif defined(__IAR_SYSTEMS_ICC__)
-  #pragma pop
-#else
-  #error Not supported compiler type
-#endif
-
-
-#ifdef CMSIS_BITPOSITIONS
-// ------------------------------------------------------------------------------------------------
-// -----                                  SCT Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  SCT_CONFIG  -------------------------------------------
-#define SCT_CONFIG_UNIFY_Pos                                  0                                                         /*!< SCT CONFIG: UNIFY Position          */
-#define SCT_CONFIG_UNIFY_Msk                                  (0x01UL << SCT_CONFIG_UNIFY_Pos)                          /*!< SCT CONFIG: UNIFY Mask              */
-#define SCT_CONFIG_CLKMODE_Pos                                1                                                         /*!< SCT CONFIG: CLKMODE Position        */
-#define SCT_CONFIG_CLKMODE_Msk                                (0x03UL << SCT_CONFIG_CLKMODE_Pos)                        /*!< SCT CONFIG: CLKMODE Mask            */
-#define SCT_CONFIG_CLKSEL_Pos                                 3                                                         /*!< SCT CONFIG: CLKSEL Position         */
-#define SCT_CONFIG_CLKSEL_Msk                                 (0x0fUL << SCT_CONFIG_CLKSEL_Pos)                         /*!< SCT CONFIG: CLKSEL Mask             */
-#define SCT_CONFIG_NORELAODL_NORELOADU_Pos                    7                                                         /*!< SCT CONFIG: NORELAODL_NORELOADU Position */
-#define SCT_CONFIG_NORELAODL_NORELOADU_Msk                    (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos)            /*!< SCT CONFIG: NORELAODL_NORELOADU Mask */
-#define SCT_CONFIG_NORELOADH_Pos                              8                                                         /*!< SCT CONFIG: NORELOADH Position      */
-#define SCT_CONFIG_NORELOADH_Msk                              (0x01UL << SCT_CONFIG_NORELOADH_Pos)                      /*!< SCT CONFIG: NORELOADH Mask          */
-#define SCT_CONFIG_INSYNCn_Pos                                9                                                         /*!< SCT CONFIG: INSYNCn Position        */
-#define SCT_CONFIG_INSYNCn_Msk                                (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos)                  /*!< SCT CONFIG: INSYNCn Mask            */
-
-// ----------------------------------------  SCT_CTRL  --------------------------------------------
-#define SCT_CTRL_DOWN_L_Pos                                   0                                                         /*!< SCT CTRL: DOWN_L Position           */
-#define SCT_CTRL_DOWN_L_Msk                                   (0x01UL << SCT_CTRL_DOWN_L_Pos)                           /*!< SCT CTRL: DOWN_L Mask               */
-#define SCT_CTRL_STOP_L_Pos                                   1                                                         /*!< SCT CTRL: STOP_L Position           */
-#define SCT_CTRL_STOP_L_Msk                                   (0x01UL << SCT_CTRL_STOP_L_Pos)                           /*!< SCT CTRL: STOP_L Mask               */
-#define SCT_CTRL_HALT_L_Pos                                   2                                                         /*!< SCT CTRL: HALT_L Position           */
-#define SCT_CTRL_HALT_L_Msk                                   (0x01UL << SCT_CTRL_HALT_L_Pos)                           /*!< SCT CTRL: HALT_L Mask               */
-#define SCT_CTRL_CLRCTR_L_Pos                                 3                                                         /*!< SCT CTRL: CLRCTR_L Position         */
-#define SCT_CTRL_CLRCTR_L_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_L_Pos)                         /*!< SCT CTRL: CLRCTR_L Mask             */
-#define SCT_CTRL_BIDIR_L_Pos                                  4                                                         /*!< SCT CTRL: BIDIR_L Position          */
-#define SCT_CTRL_BIDIR_L_Msk                                  (0x01UL << SCT_CTRL_BIDIR_L_Pos)                          /*!< SCT CTRL: BIDIR_L Mask              */
-#define SCT_CTRL_PRE_L_Pos                                    5                                                         /*!< SCT CTRL: PRE_L Position            */
-#define SCT_CTRL_PRE_L_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_L_Pos)                      /*!< SCT CTRL: PRE_L Mask                */
-#define SCT_CTRL_DOWN_H_Pos                                   16                                                        /*!< SCT CTRL: DOWN_H Position           */
-#define SCT_CTRL_DOWN_H_Msk                                   (0x01UL << SCT_CTRL_DOWN_H_Pos)                           /*!< SCT CTRL: DOWN_H Mask               */
-#define SCT_CTRL_STOP_H_Pos                                   17                                                        /*!< SCT CTRL: STOP_H Position           */
-#define SCT_CTRL_STOP_H_Msk                                   (0x01UL << SCT_CTRL_STOP_H_Pos)                           /*!< SCT CTRL: STOP_H Mask               */
-#define SCT_CTRL_HALT_H_Pos                                   18                                                        /*!< SCT CTRL: HALT_H Position           */
-#define SCT_CTRL_HALT_H_Msk                                   (0x01UL << SCT_CTRL_HALT_H_Pos)                           /*!< SCT CTRL: HALT_H Mask               */
-#define SCT_CTRL_CLRCTR_H_Pos                                 19                                                        /*!< SCT CTRL: CLRCTR_H Position         */
-#define SCT_CTRL_CLRCTR_H_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_H_Pos)                         /*!< SCT CTRL: CLRCTR_H Mask             */
-#define SCT_CTRL_BIDIR_H_Pos                                  20                                                        /*!< SCT CTRL: BIDIR_H Position          */
-#define SCT_CTRL_BIDIR_H_Msk                                  (0x01UL << SCT_CTRL_BIDIR_H_Pos)                          /*!< SCT CTRL: BIDIR_H Mask              */
-#define SCT_CTRL_PRE_H_Pos                                    21                                                        /*!< SCT CTRL: PRE_H Position            */
-#define SCT_CTRL_PRE_H_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_H_Pos)                      /*!< SCT CTRL: PRE_H Mask                */
-
-// ----------------------------------------  SCT_LIMIT  -------------------------------------------
-#define SCT_LIMIT_LIMMSK_L_Pos                                0                                                         /*!< SCT LIMIT: LIMMSK_L Position        */
-#define SCT_LIMIT_LIMMSK_L_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos)                  /*!< SCT LIMIT: LIMMSK_L Mask            */
-#define SCT_LIMIT_LIMMSK_H_Pos                                16                                                        /*!< SCT LIMIT: LIMMSK_H Position        */
-#define SCT_LIMIT_LIMMSK_H_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos)                  /*!< SCT LIMIT: LIMMSK_H Mask            */
-
-// ----------------------------------------  SCT_HALT  --------------------------------------------
-#define SCT_HALT_HALTMSK_L_Pos                                0                                                         /*!< SCT HALT: HALTMSK_L Position        */
-#define SCT_HALT_HALTMSK_L_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos)                  /*!< SCT HALT: HALTMSK_L Mask            */
-#define SCT_HALT_HALTMSK_H_Pos                                16                                                        /*!< SCT HALT: HALTMSK_H Position        */
-#define SCT_HALT_HALTMSK_H_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos)                  /*!< SCT HALT: HALTMSK_H Mask            */
-
-// ----------------------------------------  SCT_STOP  --------------------------------------------
-#define SCT_STOP_STOPMSK_L_Pos                                0                                                         /*!< SCT STOP: STOPMSK_L Position        */
-#define SCT_STOP_STOPMSK_L_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos)                  /*!< SCT STOP: STOPMSK_L Mask            */
-#define SCT_STOP_STOPMSK_H_Pos                                16                                                        /*!< SCT STOP: STOPMSK_H Position        */
-#define SCT_STOP_STOPMSK_H_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos)                  /*!< SCT STOP: STOPMSK_H Mask            */
-
-// ----------------------------------------  SCT_START  -------------------------------------------
-#define SCT_START_STARTMSK_L_Pos                              0                                                         /*!< SCT START: STARTMSK_L Position      */
-#define SCT_START_STARTMSK_L_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_L_Pos)                /*!< SCT START: STARTMSK_L Mask          */
-#define SCT_START_STARTMSK_H_Pos                              16                                                        /*!< SCT START: STARTMSK_H Position      */
-#define SCT_START_STARTMSK_H_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_H_Pos)                /*!< SCT START: STARTMSK_H Mask          */
-
-// ----------------------------------------  SCT_COUNT  -------------------------------------------
-#define SCT_COUNT_CTR_L_Pos                                   0                                                         /*!< SCT COUNT: CTR_L Position           */
-#define SCT_COUNT_CTR_L_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_L_Pos)                     /*!< SCT COUNT: CTR_L Mask               */
-#define SCT_COUNT_CTR_H_Pos                                   16                                                        /*!< SCT COUNT: CTR_H Position           */
-#define SCT_COUNT_CTR_H_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_H_Pos)                     /*!< SCT COUNT: CTR_H Mask               */
-
-// ----------------------------------------  SCT_STATE  -------------------------------------------
-#define SCT_STATE_STATE_L_Pos                                 0                                                         /*!< SCT STATE: STATE_L Position         */
-#define SCT_STATE_STATE_L_Msk                                 (0x1fUL << SCT_STATE_STATE_L_Pos)                         /*!< SCT STATE: STATE_L Mask             */
-#define SCT_STATE_STATE_H_Pos                                 16                                                        /*!< SCT STATE: STATE_H Position         */
-#define SCT_STATE_STATE_H_Msk                                 (0x1fUL << SCT_STATE_STATE_H_Pos)                         /*!< SCT STATE: STATE_H Mask             */
-
-// ----------------------------------------  SCT_INPUT  -------------------------------------------
-#define SCT_INPUT_AIN0_Pos                                    0                                                         /*!< SCT INPUT: AIN0 Position            */
-#define SCT_INPUT_AIN0_Msk                                    (0x01UL << SCT_INPUT_AIN0_Pos)                            /*!< SCT INPUT: AIN0 Mask                */
-#define SCT_INPUT_AIN1_Pos                                    1                                                         /*!< SCT INPUT: AIN1 Position            */
-#define SCT_INPUT_AIN1_Msk                                    (0x01UL << SCT_INPUT_AIN1_Pos)                            /*!< SCT INPUT: AIN1 Mask                */
-#define SCT_INPUT_AIN2_Pos                                    2                                                         /*!< SCT INPUT: AIN2 Position            */
-#define SCT_INPUT_AIN2_Msk                                    (0x01UL << SCT_INPUT_AIN2_Pos)                            /*!< SCT INPUT: AIN2 Mask                */
-#define SCT_INPUT_AIN3_Pos                                    3                                                         /*!< SCT INPUT: AIN3 Position            */
-#define SCT_INPUT_AIN3_Msk                                    (0x01UL << SCT_INPUT_AIN3_Pos)                            /*!< SCT INPUT: AIN3 Mask                */
-#define SCT_INPUT_AIN4_Pos                                    4                                                         /*!< SCT INPUT: AIN4 Position            */
-#define SCT_INPUT_AIN4_Msk                                    (0x01UL << SCT_INPUT_AIN4_Pos)                            /*!< SCT INPUT: AIN4 Mask                */
-#define SCT_INPUT_AIN5_Pos                                    5                                                         /*!< SCT INPUT: AIN5 Position            */
-#define SCT_INPUT_AIN5_Msk                                    (0x01UL << SCT_INPUT_AIN5_Pos)                            /*!< SCT INPUT: AIN5 Mask                */
-#define SCT_INPUT_AIN6_Pos                                    6                                                         /*!< SCT INPUT: AIN6 Position            */
-#define SCT_INPUT_AIN6_Msk                                    (0x01UL << SCT_INPUT_AIN6_Pos)                            /*!< SCT INPUT: AIN6 Mask                */
-#define SCT_INPUT_AIN7_Pos                                    7                                                         /*!< SCT INPUT: AIN7 Position            */
-#define SCT_INPUT_AIN7_Msk                                    (0x01UL << SCT_INPUT_AIN7_Pos)                            /*!< SCT INPUT: AIN7 Mask                */
-#define SCT_INPUT_SIN0_Pos                                    16                                                        /*!< SCT INPUT: SIN0 Position            */
-#define SCT_INPUT_SIN0_Msk                                    (0x01UL << SCT_INPUT_SIN0_Pos)                            /*!< SCT INPUT: SIN0 Mask                */
-#define SCT_INPUT_SIN1_Pos                                    17                                                        /*!< SCT INPUT: SIN1 Position            */
-#define SCT_INPUT_SIN1_Msk                                    (0x01UL << SCT_INPUT_SIN1_Pos)                            /*!< SCT INPUT: SIN1 Mask                */
-#define SCT_INPUT_SIN2_Pos                                    18                                                        /*!< SCT INPUT: SIN2 Position            */
-#define SCT_INPUT_SIN2_Msk                                    (0x01UL << SCT_INPUT_SIN2_Pos)                            /*!< SCT INPUT: SIN2 Mask                */
-#define SCT_INPUT_SIN3_Pos                                    19                                                        /*!< SCT INPUT: SIN3 Position            */
-#define SCT_INPUT_SIN3_Msk                                    (0x01UL << SCT_INPUT_SIN3_Pos)                            /*!< SCT INPUT: SIN3 Mask                */
-#define SCT_INPUT_SIN4_Pos                                    20                                                        /*!< SCT INPUT: SIN4 Position            */
-#define SCT_INPUT_SIN4_Msk                                    (0x01UL << SCT_INPUT_SIN4_Pos)                            /*!< SCT INPUT: SIN4 Mask                */
-#define SCT_INPUT_SIN5_Pos                                    21                                                        /*!< SCT INPUT: SIN5 Position            */
-#define SCT_INPUT_SIN5_Msk                                    (0x01UL << SCT_INPUT_SIN5_Pos)                            /*!< SCT INPUT: SIN5 Mask                */
-#define SCT_INPUT_SIN6_Pos                                    22                                                        /*!< SCT INPUT: SIN6 Position            */
-#define SCT_INPUT_SIN6_Msk                                    (0x01UL << SCT_INPUT_SIN6_Pos)                            /*!< SCT INPUT: SIN6 Mask                */
-#define SCT_INPUT_SIN7_Pos                                    23                                                        /*!< SCT INPUT: SIN7 Position            */
-#define SCT_INPUT_SIN7_Msk                                    (0x01UL << SCT_INPUT_SIN7_Pos)                            /*!< SCT INPUT: SIN7 Mask                */
-
-// ---------------------------------------  SCT_REGMODE  ------------------------------------------
-#define SCT_REGMODE_REGMOD_L0_Pos                             0                                                         /*!< SCT REGMODE: REGMOD_L0 Position     */
-#define SCT_REGMODE_REGMOD_L0_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L0_Pos)                     /*!< SCT REGMODE: REGMOD_L0 Mask         */
-#define SCT_REGMODE_REGMOD_L1_Pos                             1                                                         /*!< SCT REGMODE: REGMOD_L1 Position     */
-#define SCT_REGMODE_REGMOD_L1_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L1_Pos)                     /*!< SCT REGMODE: REGMOD_L1 Mask         */
-#define SCT_REGMODE_REGMOD_L2_Pos                             2                                                         /*!< SCT REGMODE: REGMOD_L2 Position     */
-#define SCT_REGMODE_REGMOD_L2_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L2_Pos)                     /*!< SCT REGMODE: REGMOD_L2 Mask         */
-#define SCT_REGMODE_REGMOD_L3_Pos                             3                                                         /*!< SCT REGMODE: REGMOD_L3 Position     */
-#define SCT_REGMODE_REGMOD_L3_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L3_Pos)                     /*!< SCT REGMODE: REGMOD_L3 Mask         */
-#define SCT_REGMODE_REGMOD_L4_Pos                             4                                                         /*!< SCT REGMODE: REGMOD_L4 Position     */
-#define SCT_REGMODE_REGMOD_L4_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L4_Pos)                     /*!< SCT REGMODE: REGMOD_L4 Mask         */
-#define SCT_REGMODE_REGMOD_L5_Pos                             5                                                         /*!< SCT REGMODE: REGMOD_L5 Position     */
-#define SCT_REGMODE_REGMOD_L5_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L5_Pos)                     /*!< SCT REGMODE: REGMOD_L5 Mask         */
-#define SCT_REGMODE_REGMOD_L6_Pos                             6                                                         /*!< SCT REGMODE: REGMOD_L6 Position     */
-#define SCT_REGMODE_REGMOD_L6_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L6_Pos)                     /*!< SCT REGMODE: REGMOD_L6 Mask         */
-#define SCT_REGMODE_REGMOD_L7_Pos                             7                                                         /*!< SCT REGMODE: REGMOD_L7 Position     */
-#define SCT_REGMODE_REGMOD_L7_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L7_Pos)                     /*!< SCT REGMODE: REGMOD_L7 Mask         */
-#define SCT_REGMODE_REGMOD_L8_Pos                             8                                                         /*!< SCT REGMODE: REGMOD_L8 Position     */
-#define SCT_REGMODE_REGMOD_L8_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L8_Pos)                     /*!< SCT REGMODE: REGMOD_L8 Mask         */
-#define SCT_REGMODE_REGMOD_L9_Pos                             9                                                         /*!< SCT REGMODE: REGMOD_L9 Position     */
-#define SCT_REGMODE_REGMOD_L9_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L9_Pos)                     /*!< SCT REGMODE: REGMOD_L9 Mask         */
-#define SCT_REGMODE_REGMOD_L10_Pos                            10                                                        /*!< SCT REGMODE: REGMOD_L10 Position    */
-#define SCT_REGMODE_REGMOD_L10_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L10_Pos)                    /*!< SCT REGMODE: REGMOD_L10 Mask        */
-#define SCT_REGMODE_REGMOD_L11_Pos                            11                                                        /*!< SCT REGMODE: REGMOD_L11 Position    */
-#define SCT_REGMODE_REGMOD_L11_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L11_Pos)                    /*!< SCT REGMODE: REGMOD_L11 Mask        */
-#define SCT_REGMODE_REGMOD_L12_Pos                            12                                                        /*!< SCT REGMODE: REGMOD_L12 Position    */
-#define SCT_REGMODE_REGMOD_L12_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L12_Pos)                    /*!< SCT REGMODE: REGMOD_L12 Mask        */
-#define SCT_REGMODE_REGMOD_L13_Pos                            13                                                        /*!< SCT REGMODE: REGMOD_L13 Position    */
-#define SCT_REGMODE_REGMOD_L13_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L13_Pos)                    /*!< SCT REGMODE: REGMOD_L13 Mask        */
-#define SCT_REGMODE_REGMOD_L14_Pos                            14                                                        /*!< SCT REGMODE: REGMOD_L14 Position    */
-#define SCT_REGMODE_REGMOD_L14_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L14_Pos)                    /*!< SCT REGMODE: REGMOD_L14 Mask        */
-#define SCT_REGMODE_REGMOD_L15_Pos                            15                                                        /*!< SCT REGMODE: REGMOD_L15 Position    */
-#define SCT_REGMODE_REGMOD_L15_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L15_Pos)                    /*!< SCT REGMODE: REGMOD_L15 Mask        */
-#define SCT_REGMODE_REGMOD_H16_Pos                            16                                                        /*!< SCT REGMODE: REGMOD_H16 Position    */
-#define SCT_REGMODE_REGMOD_H16_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H16_Pos)                    /*!< SCT REGMODE: REGMOD_H16 Mask        */
-#define SCT_REGMODE_REGMOD_H17_Pos                            17                                                        /*!< SCT REGMODE: REGMOD_H17 Position    */
-#define SCT_REGMODE_REGMOD_H17_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H17_Pos)                    /*!< SCT REGMODE: REGMOD_H17 Mask        */
-#define SCT_REGMODE_REGMOD_H18_Pos                            18                                                        /*!< SCT REGMODE: REGMOD_H18 Position    */
-#define SCT_REGMODE_REGMOD_H18_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H18_Pos)                    /*!< SCT REGMODE: REGMOD_H18 Mask        */
-#define SCT_REGMODE_REGMOD_H19_Pos                            19                                                        /*!< SCT REGMODE: REGMOD_H19 Position    */
-#define SCT_REGMODE_REGMOD_H19_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H19_Pos)                    /*!< SCT REGMODE: REGMOD_H19 Mask        */
-#define SCT_REGMODE_REGMOD_H20_Pos                            20                                                        /*!< SCT REGMODE: REGMOD_H20 Position    */
-#define SCT_REGMODE_REGMOD_H20_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H20_Pos)                    /*!< SCT REGMODE: REGMOD_H20 Mask        */
-#define SCT_REGMODE_REGMOD_H21_Pos                            21                                                        /*!< SCT REGMODE: REGMOD_H21 Position    */
-#define SCT_REGMODE_REGMOD_H21_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H21_Pos)                    /*!< SCT REGMODE: REGMOD_H21 Mask        */
-#define SCT_REGMODE_REGMOD_H22_Pos                            22                                                        /*!< SCT REGMODE: REGMOD_H22 Position    */
-#define SCT_REGMODE_REGMOD_H22_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H22_Pos)                    /*!< SCT REGMODE: REGMOD_H22 Mask        */
-#define SCT_REGMODE_REGMOD_H23_Pos                            23                                                        /*!< SCT REGMODE: REGMOD_H23 Position    */
-#define SCT_REGMODE_REGMOD_H23_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H23_Pos)                    /*!< SCT REGMODE: REGMOD_H23 Mask        */
-#define SCT_REGMODE_REGMOD_H24_Pos                            24                                                        /*!< SCT REGMODE: REGMOD_H24 Position    */
-#define SCT_REGMODE_REGMOD_H24_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H24_Pos)                    /*!< SCT REGMODE: REGMOD_H24 Mask        */
-#define SCT_REGMODE_REGMOD_H25_Pos                            25                                                        /*!< SCT REGMODE: REGMOD_H25 Position    */
-#define SCT_REGMODE_REGMOD_H25_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H25_Pos)                    /*!< SCT REGMODE: REGMOD_H25 Mask        */
-#define SCT_REGMODE_REGMOD_H26_Pos                            26                                                        /*!< SCT REGMODE: REGMOD_H26 Position    */
-#define SCT_REGMODE_REGMOD_H26_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H26_Pos)                    /*!< SCT REGMODE: REGMOD_H26 Mask        */
-#define SCT_REGMODE_REGMOD_H27_Pos                            27                                                        /*!< SCT REGMODE: REGMOD_H27 Position    */
-#define SCT_REGMODE_REGMOD_H27_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H27_Pos)                    /*!< SCT REGMODE: REGMOD_H27 Mask        */
-#define SCT_REGMODE_REGMOD_H28_Pos                            28                                                        /*!< SCT REGMODE: REGMOD_H28 Position    */
-#define SCT_REGMODE_REGMOD_H28_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H28_Pos)                    /*!< SCT REGMODE: REGMOD_H28 Mask        */
-#define SCT_REGMODE_REGMOD_H29_Pos                            29                                                        /*!< SCT REGMODE: REGMOD_H29 Position    */
-#define SCT_REGMODE_REGMOD_H29_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H29_Pos)                    /*!< SCT REGMODE: REGMOD_H29 Mask        */
-#define SCT_REGMODE_REGMOD_H30_Pos                            30                                                        /*!< SCT REGMODE: REGMOD_H30 Position    */
-#define SCT_REGMODE_REGMOD_H30_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H30_Pos)                    /*!< SCT REGMODE: REGMOD_H30 Mask        */
-#define SCT_REGMODE_REGMOD_H31_Pos                            31                                                        /*!< SCT REGMODE: REGMOD_H31 Position    */
-#define SCT_REGMODE_REGMOD_H31_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H31_Pos)                    /*!< SCT REGMODE: REGMOD_H31 Mask        */
-
-// ---------------------------------------  SCT_OUTPUT  -------------------------------------------
-#define SCT_OUTPUT_OUT0_Pos                                   0                                                         /*!< SCT OUTPUT: OUT0 Position           */
-#define SCT_OUTPUT_OUT0_Msk                                   (0x01UL << SCT_OUTPUT_OUT0_Pos)                           /*!< SCT OUTPUT: OUT0 Mask               */
-#define SCT_OUTPUT_OUT1_Pos                                   1                                                         /*!< SCT OUTPUT: OUT1 Position           */
-#define SCT_OUTPUT_OUT1_Msk                                   (0x01UL << SCT_OUTPUT_OUT1_Pos)                           /*!< SCT OUTPUT: OUT1 Mask               */
-#define SCT_OUTPUT_OUT2_Pos                                   2                                                         /*!< SCT OUTPUT: OUT2 Position           */
-#define SCT_OUTPUT_OUT2_Msk                                   (0x01UL << SCT_OUTPUT_OUT2_Pos)                           /*!< SCT OUTPUT: OUT2 Mask               */
-#define SCT_OUTPUT_OUT3_Pos                                   3                                                         /*!< SCT OUTPUT: OUT3 Position           */
-#define SCT_OUTPUT_OUT3_Msk                                   (0x01UL << SCT_OUTPUT_OUT3_Pos)                           /*!< SCT OUTPUT: OUT3 Mask               */
-#define SCT_OUTPUT_OUT4_Pos                                   4                                                         /*!< SCT OUTPUT: OUT4 Position           */
-#define SCT_OUTPUT_OUT4_Msk                                   (0x01UL << SCT_OUTPUT_OUT4_Pos)                           /*!< SCT OUTPUT: OUT4 Mask               */
-#define SCT_OUTPUT_OUT5_Pos                                   5                                                         /*!< SCT OUTPUT: OUT5 Position           */
-#define SCT_OUTPUT_OUT5_Msk                                   (0x01UL << SCT_OUTPUT_OUT5_Pos)                           /*!< SCT OUTPUT: OUT5 Mask               */
-#define SCT_OUTPUT_OUT6_Pos                                   6                                                         /*!< SCT OUTPUT: OUT6 Position           */
-#define SCT_OUTPUT_OUT6_Msk                                   (0x01UL << SCT_OUTPUT_OUT6_Pos)                           /*!< SCT OUTPUT: OUT6 Mask               */
-#define SCT_OUTPUT_OUT7_Pos                                   7                                                         /*!< SCT OUTPUT: OUT7 Position           */
-#define SCT_OUTPUT_OUT7_Msk                                   (0x01UL << SCT_OUTPUT_OUT7_Pos)                           /*!< SCT OUTPUT: OUT7 Mask               */
-#define SCT_OUTPUT_OUT8_Pos                                   8                                                         /*!< SCT OUTPUT: OUT8 Position           */
-#define SCT_OUTPUT_OUT8_Msk                                   (0x01UL << SCT_OUTPUT_OUT8_Pos)                           /*!< SCT OUTPUT: OUT8 Mask               */
-#define SCT_OUTPUT_OUT9_Pos                                   9                                                         /*!< SCT OUTPUT: OUT9 Position           */
-#define SCT_OUTPUT_OUT9_Msk                                   (0x01UL << SCT_OUTPUT_OUT9_Pos)                           /*!< SCT OUTPUT: OUT9 Mask               */
-#define SCT_OUTPUT_OUT10_Pos                                  10                                                        /*!< SCT OUTPUT: OUT10 Position          */
-#define SCT_OUTPUT_OUT10_Msk                                  (0x01UL << SCT_OUTPUT_OUT10_Pos)                          /*!< SCT OUTPUT: OUT10 Mask              */
-#define SCT_OUTPUT_OUT11_Pos                                  11                                                        /*!< SCT OUTPUT: OUT11 Position          */
-#define SCT_OUTPUT_OUT11_Msk                                  (0x01UL << SCT_OUTPUT_OUT11_Pos)                          /*!< SCT OUTPUT: OUT11 Mask              */
-#define SCT_OUTPUT_OUT12_Pos                                  12                                                        /*!< SCT OUTPUT: OUT12 Position          */
-#define SCT_OUTPUT_OUT12_Msk                                  (0x01UL << SCT_OUTPUT_OUT12_Pos)                          /*!< SCT OUTPUT: OUT12 Mask              */
-#define SCT_OUTPUT_OUT13_Pos                                  13                                                        /*!< SCT OUTPUT: OUT13 Position          */
-#define SCT_OUTPUT_OUT13_Msk                                  (0x01UL << SCT_OUTPUT_OUT13_Pos)                          /*!< SCT OUTPUT: OUT13 Mask              */
-#define SCT_OUTPUT_OUT14_Pos                                  14                                                        /*!< SCT OUTPUT: OUT14 Position          */
-#define SCT_OUTPUT_OUT14_Msk                                  (0x01UL << SCT_OUTPUT_OUT14_Pos)                          /*!< SCT OUTPUT: OUT14 Mask              */
-#define SCT_OUTPUT_OUT15_Pos                                  15                                                        /*!< SCT OUTPUT: OUT15 Position          */
-#define SCT_OUTPUT_OUT15_Msk                                  (0x01UL << SCT_OUTPUT_OUT15_Pos)                          /*!< SCT OUTPUT: OUT15 Mask              */
-
-// ------------------------------------  SCT_OUTPUTDIRCTRL  ---------------------------------------
-#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos                         0                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos                         2                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos                         4                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos                         6                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos                         8                                                         /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos                         10                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos                         12                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos                         14                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos                         16                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos                         18                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos)                 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask     */
-#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos                        20                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask    */
-#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos                        22                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask    */
-#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos                        24                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask    */
-#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos                        26                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask    */
-#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos                        28                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask    */
-#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos                        30                                                        /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */
-#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos)                /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask    */
-
-// -----------------------------------------  SCT_RES  --------------------------------------------
-#define SCT_RES_O0RES_Pos                                     0                                                         /*!< SCT RES: O0RES Position             */
-#define SCT_RES_O0RES_Msk                                     (0x03UL << SCT_RES_O0RES_Pos)                             /*!< SCT RES: O0RES Mask                 */
-#define SCT_RES_O1RES_Pos                                     2                                                         /*!< SCT RES: O1RES Position             */
-#define SCT_RES_O1RES_Msk                                     (0x03UL << SCT_RES_O1RES_Pos)                             /*!< SCT RES: O1RES Mask                 */
-#define SCT_RES_O2RES_Pos                                     4                                                         /*!< SCT RES: O2RES Position             */
-#define SCT_RES_O2RES_Msk                                     (0x03UL << SCT_RES_O2RES_Pos)                             /*!< SCT RES: O2RES Mask                 */
-#define SCT_RES_O3RES_Pos                                     6                                                         /*!< SCT RES: O3RES Position             */
-#define SCT_RES_O3RES_Msk                                     (0x03UL << SCT_RES_O3RES_Pos)                             /*!< SCT RES: O3RES Mask                 */
-#define SCT_RES_O4RES_Pos                                     8                                                         /*!< SCT RES: O4RES Position             */
-#define SCT_RES_O4RES_Msk                                     (0x03UL << SCT_RES_O4RES_Pos)                             /*!< SCT RES: O4RES Mask                 */
-#define SCT_RES_O5RES_Pos                                     10                                                        /*!< SCT RES: O5RES Position             */
-#define SCT_RES_O5RES_Msk                                     (0x03UL << SCT_RES_O5RES_Pos)                             /*!< SCT RES: O5RES Mask                 */
-#define SCT_RES_O6RES_Pos                                     12                                                        /*!< SCT RES: O6RES Position             */
-#define SCT_RES_O6RES_Msk                                     (0x03UL << SCT_RES_O6RES_Pos)                             /*!< SCT RES: O6RES Mask                 */
-#define SCT_RES_O7RES_Pos                                     14                                                        /*!< SCT RES: O7RES Position             */
-#define SCT_RES_O7RES_Msk                                     (0x03UL << SCT_RES_O7RES_Pos)                             /*!< SCT RES: O7RES Mask                 */
-#define SCT_RES_O8RES_Pos                                     16                                                        /*!< SCT RES: O8RES Position             */
-#define SCT_RES_O8RES_Msk                                     (0x03UL << SCT_RES_O8RES_Pos)                             /*!< SCT RES: O8RES Mask                 */
-#define SCT_RES_O9RES_Pos                                     18                                                        /*!< SCT RES: O9RES Position             */
-#define SCT_RES_O9RES_Msk                                     (0x03UL << SCT_RES_O9RES_Pos)                             /*!< SCT RES: O9RES Mask                 */
-#define SCT_RES_O10RES_Pos                                    20                                                        /*!< SCT RES: O10RES Position            */
-#define SCT_RES_O10RES_Msk                                    (0x03UL << SCT_RES_O10RES_Pos)                            /*!< SCT RES: O10RES Mask                */
-#define SCT_RES_O11RES_Pos                                    22                                                        /*!< SCT RES: O11RES Position            */
-#define SCT_RES_O11RES_Msk                                    (0x03UL << SCT_RES_O11RES_Pos)                            /*!< SCT RES: O11RES Mask                */
-#define SCT_RES_O12RES_Pos                                    24                                                        /*!< SCT RES: O12RES Position            */
-#define SCT_RES_O12RES_Msk                                    (0x03UL << SCT_RES_O12RES_Pos)                            /*!< SCT RES: O12RES Mask                */
-#define SCT_RES_O13RES_Pos                                    26                                                        /*!< SCT RES: O13RES Position            */
-#define SCT_RES_O13RES_Msk                                    (0x03UL << SCT_RES_O13RES_Pos)                            /*!< SCT RES: O13RES Mask                */
-#define SCT_RES_O14RES_Pos                                    28                                                        /*!< SCT RES: O14RES Position            */
-#define SCT_RES_O14RES_Msk                                    (0x03UL << SCT_RES_O14RES_Pos)                            /*!< SCT RES: O14RES Mask                */
-#define SCT_RES_O15RES_Pos                                    30                                                        /*!< SCT RES: O15RES Position            */
-#define SCT_RES_O15RES_Msk                                    (0x03UL << SCT_RES_O15RES_Pos)                            /*!< SCT RES: O15RES Mask                */
-
-// ---------------------------------------  SCT_DMAREQ0  ------------------------------------------
-#define SCT_DMAREQ0_DEV_0_0_Pos                               0                                                         /*!< SCT DMAREQ0: DEV_0_0 Position       */
-#define SCT_DMAREQ0_DEV_0_0_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos)                       /*!< SCT DMAREQ0: DEV_0_0 Mask           */
-#define SCT_DMAREQ0_DEV_0_1_Pos                               1                                                         /*!< SCT DMAREQ0: DEV_0_1 Position       */
-#define SCT_DMAREQ0_DEV_0_1_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos)                       /*!< SCT DMAREQ0: DEV_0_1 Mask           */
-#define SCT_DMAREQ0_DEV_0_2_Pos                               2                                                         /*!< SCT DMAREQ0: DEV_0_2 Position       */
-#define SCT_DMAREQ0_DEV_0_2_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos)                       /*!< SCT DMAREQ0: DEV_0_2 Mask           */
-#define SCT_DMAREQ0_DEV_0_3_Pos                               3                                                         /*!< SCT DMAREQ0: DEV_0_3 Position       */
-#define SCT_DMAREQ0_DEV_0_3_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos)                       /*!< SCT DMAREQ0: DEV_0_3 Mask           */
-#define SCT_DMAREQ0_DEV_0_4_Pos                               4                                                         /*!< SCT DMAREQ0: DEV_0_4 Position       */
-#define SCT_DMAREQ0_DEV_0_4_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos)                       /*!< SCT DMAREQ0: DEV_0_4 Mask           */
-#define SCT_DMAREQ0_DEV_0_5_Pos                               5                                                         /*!< SCT DMAREQ0: DEV_0_5 Position       */
-#define SCT_DMAREQ0_DEV_0_5_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos)                       /*!< SCT DMAREQ0: DEV_0_5 Mask           */
-#define SCT_DMAREQ0_DEV_0_6_Pos                               6                                                         /*!< SCT DMAREQ0: DEV_0_6 Position       */
-#define SCT_DMAREQ0_DEV_0_6_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos)                       /*!< SCT DMAREQ0: DEV_0_6 Mask           */
-#define SCT_DMAREQ0_DEV_0_7_Pos                               7                                                         /*!< SCT DMAREQ0: DEV_0_7 Position       */
-#define SCT_DMAREQ0_DEV_0_7_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos)                       /*!< SCT DMAREQ0: DEV_0_7 Mask           */
-#define SCT_DMAREQ0_DEV_0_8_Pos                               8                                                         /*!< SCT DMAREQ0: DEV_0_8 Position       */
-#define SCT_DMAREQ0_DEV_0_8_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos)                       /*!< SCT DMAREQ0: DEV_0_8 Mask           */
-#define SCT_DMAREQ0_DEV_0_9_Pos                               9                                                         /*!< SCT DMAREQ0: DEV_0_9 Position       */
-#define SCT_DMAREQ0_DEV_0_9_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos)                       /*!< SCT DMAREQ0: DEV_0_9 Mask           */
-#define SCT_DMAREQ0_DEV_0_10_Pos                              10                                                        /*!< SCT DMAREQ0: DEV_0_10 Position      */
-#define SCT_DMAREQ0_DEV_0_10_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos)                      /*!< SCT DMAREQ0: DEV_0_10 Mask          */
-#define SCT_DMAREQ0_DEV_0_11_Pos                              11                                                        /*!< SCT DMAREQ0: DEV_0_11 Position      */
-#define SCT_DMAREQ0_DEV_0_11_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos)                      /*!< SCT DMAREQ0: DEV_0_11 Mask          */
-#define SCT_DMAREQ0_DEV_0_12_Pos                              12                                                        /*!< SCT DMAREQ0: DEV_0_12 Position      */
-#define SCT_DMAREQ0_DEV_0_12_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos)                      /*!< SCT DMAREQ0: DEV_0_12 Mask          */
-#define SCT_DMAREQ0_DEV_0_13_Pos                              13                                                        /*!< SCT DMAREQ0: DEV_0_13 Position      */
-#define SCT_DMAREQ0_DEV_0_13_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos)                      /*!< SCT DMAREQ0: DEV_0_13 Mask          */
-#define SCT_DMAREQ0_DEV_0_14_Pos                              14                                                        /*!< SCT DMAREQ0: DEV_0_14 Position      */
-#define SCT_DMAREQ0_DEV_0_14_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos)                      /*!< SCT DMAREQ0: DEV_0_14 Mask          */
-#define SCT_DMAREQ0_DEV_0_15_Pos                              15                                                        /*!< SCT DMAREQ0: DEV_0_15 Position      */
-#define SCT_DMAREQ0_DEV_0_15_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos)                      /*!< SCT DMAREQ0: DEV_0_15 Mask          */
-#define SCT_DMAREQ0_DRL0_Pos                                  30                                                        /*!< SCT DMAREQ0: DRL0 Position          */
-#define SCT_DMAREQ0_DRL0_Msk                                  (0x01UL << SCT_DMAREQ0_DRL0_Pos)                          /*!< SCT DMAREQ0: DRL0 Mask              */
-#define SCT_DMAREQ0_DRQ0_Pos                                  31                                                        /*!< SCT DMAREQ0: DRQ0 Position          */
-#define SCT_DMAREQ0_DRQ0_Msk                                  (0x01UL << SCT_DMAREQ0_DRQ0_Pos)                          /*!< SCT DMAREQ0: DRQ0 Mask              */
-
-// ---------------------------------------  SCT_DMAREQ1  ------------------------------------------
-#define SCT_DMAREQ1_DEV_1_0_Pos                               0                                                         /*!< SCT DMAREQ1: DEV_1_0 Position       */
-#define SCT_DMAREQ1_DEV_1_0_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos)                       /*!< SCT DMAREQ1: DEV_1_0 Mask           */
-#define SCT_DMAREQ1_DEV_1_1_Pos                               1                                                         /*!< SCT DMAREQ1: DEV_1_1 Position       */
-#define SCT_DMAREQ1_DEV_1_1_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos)                       /*!< SCT DMAREQ1: DEV_1_1 Mask           */
-#define SCT_DMAREQ1_DEV_1_2_Pos                               2                                                         /*!< SCT DMAREQ1: DEV_1_2 Position       */
-#define SCT_DMAREQ1_DEV_1_2_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos)                       /*!< SCT DMAREQ1: DEV_1_2 Mask           */
-#define SCT_DMAREQ1_DEV_1_3_Pos                               3                                                         /*!< SCT DMAREQ1: DEV_1_3 Position       */
-#define SCT_DMAREQ1_DEV_1_3_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos)                       /*!< SCT DMAREQ1: DEV_1_3 Mask           */
-#define SCT_DMAREQ1_DEV_1_4_Pos                               4                                                         /*!< SCT DMAREQ1: DEV_1_4 Position       */
-#define SCT_DMAREQ1_DEV_1_4_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos)                       /*!< SCT DMAREQ1: DEV_1_4 Mask           */
-#define SCT_DMAREQ1_DEV_1_5_Pos                               5                                                         /*!< SCT DMAREQ1: DEV_1_5 Position       */
-#define SCT_DMAREQ1_DEV_1_5_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos)                       /*!< SCT DMAREQ1: DEV_1_5 Mask           */
-#define SCT_DMAREQ1_DEV_1_6_Pos                               6                                                         /*!< SCT DMAREQ1: DEV_1_6 Position       */
-#define SCT_DMAREQ1_DEV_1_6_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos)                       /*!< SCT DMAREQ1: DEV_1_6 Mask           */
-#define SCT_DMAREQ1_DEV_1_7_Pos                               7                                                         /*!< SCT DMAREQ1: DEV_1_7 Position       */
-#define SCT_DMAREQ1_DEV_1_7_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos)                       /*!< SCT DMAREQ1: DEV_1_7 Mask           */
-#define SCT_DMAREQ1_DEV_1_8_Pos                               8                                                         /*!< SCT DMAREQ1: DEV_1_8 Position       */
-#define SCT_DMAREQ1_DEV_1_8_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos)                       /*!< SCT DMAREQ1: DEV_1_8 Mask           */
-#define SCT_DMAREQ1_DEV_1_9_Pos                               9                                                         /*!< SCT DMAREQ1: DEV_1_9 Position       */
-#define SCT_DMAREQ1_DEV_1_9_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos)                       /*!< SCT DMAREQ1: DEV_1_9 Mask           */
-#define SCT_DMAREQ1_DEV_1_10_Pos                              10                                                        /*!< SCT DMAREQ1: DEV_1_10 Position      */
-#define SCT_DMAREQ1_DEV_1_10_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos)                      /*!< SCT DMAREQ1: DEV_1_10 Mask          */
-#define SCT_DMAREQ1_DEV_1_11_Pos                              11                                                        /*!< SCT DMAREQ1: DEV_1_11 Position      */
-#define SCT_DMAREQ1_DEV_1_11_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos)                      /*!< SCT DMAREQ1: DEV_1_11 Mask          */
-#define SCT_DMAREQ1_DEV_1_12_Pos                              12                                                        /*!< SCT DMAREQ1: DEV_1_12 Position      */
-#define SCT_DMAREQ1_DEV_1_12_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos)                      /*!< SCT DMAREQ1: DEV_1_12 Mask          */
-#define SCT_DMAREQ1_DEV_1_13_Pos                              13                                                        /*!< SCT DMAREQ1: DEV_1_13 Position      */
-#define SCT_DMAREQ1_DEV_1_13_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos)                      /*!< SCT DMAREQ1: DEV_1_13 Mask          */
-#define SCT_DMAREQ1_DEV_1_14_Pos                              14                                                        /*!< SCT DMAREQ1: DEV_1_14 Position      */
-#define SCT_DMAREQ1_DEV_1_14_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos)                      /*!< SCT DMAREQ1: DEV_1_14 Mask          */
-#define SCT_DMAREQ1_DEV_1_15_Pos                              15                                                        /*!< SCT DMAREQ1: DEV_1_15 Position      */
-#define SCT_DMAREQ1_DEV_1_15_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos)                      /*!< SCT DMAREQ1: DEV_1_15 Mask          */
-#define SCT_DMAREQ1_DRL1_Pos                                  30                                                        /*!< SCT DMAREQ1: DRL1 Position          */
-#define SCT_DMAREQ1_DRL1_Msk                                  (0x01UL << SCT_DMAREQ1_DRL1_Pos)                          /*!< SCT DMAREQ1: DRL1 Mask              */
-#define SCT_DMAREQ1_DRQ1_Pos                                  31                                                        /*!< SCT DMAREQ1: DRQ1 Position          */
-#define SCT_DMAREQ1_DRQ1_Msk                                  (0x01UL << SCT_DMAREQ1_DRQ1_Pos)                          /*!< SCT DMAREQ1: DRQ1 Mask              */
-
-// ----------------------------------------  SCT_EVEN  --------------------------------------------
-#define SCT_EVEN_IEN0_Pos                                     0                                                         /*!< SCT EVEN: IEN0 Position             */
-#define SCT_EVEN_IEN0_Msk                                     (0x01UL << SCT_EVEN_IEN0_Pos)                             /*!< SCT EVEN: IEN0 Mask                 */
-#define SCT_EVEN_IEN1_Pos                                     1                                                         /*!< SCT EVEN: IEN1 Position             */
-#define SCT_EVEN_IEN1_Msk                                     (0x01UL << SCT_EVEN_IEN1_Pos)                             /*!< SCT EVEN: IEN1 Mask                 */
-#define SCT_EVEN_IEN2_Pos                                     2                                                         /*!< SCT EVEN: IEN2 Position             */
-#define SCT_EVEN_IEN2_Msk                                     (0x01UL << SCT_EVEN_IEN2_Pos)                             /*!< SCT EVEN: IEN2 Mask                 */
-#define SCT_EVEN_IEN3_Pos                                     3                                                         /*!< SCT EVEN: IEN3 Position             */
-#define SCT_EVEN_IEN3_Msk                                     (0x01UL << SCT_EVEN_IEN3_Pos)                             /*!< SCT EVEN: IEN3 Mask                 */
-#define SCT_EVEN_IEN4_Pos                                     4                                                         /*!< SCT EVEN: IEN4 Position             */
-#define SCT_EVEN_IEN4_Msk                                     (0x01UL << SCT_EVEN_IEN4_Pos)                             /*!< SCT EVEN: IEN4 Mask                 */
-#define SCT_EVEN_IEN5_Pos                                     5                                                         /*!< SCT EVEN: IEN5 Position             */
-#define SCT_EVEN_IEN5_Msk                                     (0x01UL << SCT_EVEN_IEN5_Pos)                             /*!< SCT EVEN: IEN5 Mask                 */
-#define SCT_EVEN_IEN6_Pos                                     6                                                         /*!< SCT EVEN: IEN6 Position             */
-#define SCT_EVEN_IEN6_Msk                                     (0x01UL << SCT_EVEN_IEN6_Pos)                             /*!< SCT EVEN: IEN6 Mask                 */
-#define SCT_EVEN_IEN7_Pos                                     7                                                         /*!< SCT EVEN: IEN7 Position             */
-#define SCT_EVEN_IEN7_Msk                                     (0x01UL << SCT_EVEN_IEN7_Pos)                             /*!< SCT EVEN: IEN7 Mask                 */
-#define SCT_EVEN_IEN8_Pos                                     8                                                         /*!< SCT EVEN: IEN8 Position             */
-#define SCT_EVEN_IEN8_Msk                                     (0x01UL << SCT_EVEN_IEN8_Pos)                             /*!< SCT EVEN: IEN8 Mask                 */
-#define SCT_EVEN_IEN9_Pos                                     9                                                         /*!< SCT EVEN: IEN9 Position             */
-#define SCT_EVEN_IEN9_Msk                                     (0x01UL << SCT_EVEN_IEN9_Pos)                             /*!< SCT EVEN: IEN9 Mask                 */
-#define SCT_EVEN_IEN10_Pos                                    10                                                        /*!< SCT EVEN: IEN10 Position            */
-#define SCT_EVEN_IEN10_Msk                                    (0x01UL << SCT_EVEN_IEN10_Pos)                            /*!< SCT EVEN: IEN10 Mask                */
-#define SCT_EVEN_IEN11_Pos                                    11                                                        /*!< SCT EVEN: IEN11 Position            */
-#define SCT_EVEN_IEN11_Msk                                    (0x01UL << SCT_EVEN_IEN11_Pos)                            /*!< SCT EVEN: IEN11 Mask                */
-#define SCT_EVEN_IEN12_Pos                                    12                                                        /*!< SCT EVEN: IEN12 Position            */
-#define SCT_EVEN_IEN12_Msk                                    (0x01UL << SCT_EVEN_IEN12_Pos)                            /*!< SCT EVEN: IEN12 Mask                */
-#define SCT_EVEN_IEN13_Pos                                    13                                                        /*!< SCT EVEN: IEN13 Position            */
-#define SCT_EVEN_IEN13_Msk                                    (0x01UL << SCT_EVEN_IEN13_Pos)                            /*!< SCT EVEN: IEN13 Mask                */
-#define SCT_EVEN_IEN14_Pos                                    14                                                        /*!< SCT EVEN: IEN14 Position            */
-#define SCT_EVEN_IEN14_Msk                                    (0x01UL << SCT_EVEN_IEN14_Pos)                            /*!< SCT EVEN: IEN14 Mask                */
-#define SCT_EVEN_IEN15_Pos                                    15                                                        /*!< SCT EVEN: IEN15 Position            */
-#define SCT_EVEN_IEN15_Msk                                    (0x01UL << SCT_EVEN_IEN15_Pos)                            /*!< SCT EVEN: IEN15 Mask                */
-
-// ---------------------------------------  SCT_EVFLAG  -------------------------------------------
-#define SCT_EVFLAG_FLAG0_Pos                                  0                                                         /*!< SCT EVFLAG: FLAG0 Position          */
-#define SCT_EVFLAG_FLAG0_Msk                                  (0x01UL << SCT_EVFLAG_FLAG0_Pos)                          /*!< SCT EVFLAG: FLAG0 Mask              */
-#define SCT_EVFLAG_FLAG1_Pos                                  1                                                         /*!< SCT EVFLAG: FLAG1 Position          */
-#define SCT_EVFLAG_FLAG1_Msk                                  (0x01UL << SCT_EVFLAG_FLAG1_Pos)                          /*!< SCT EVFLAG: FLAG1 Mask              */
-#define SCT_EVFLAG_FLAG2_Pos                                  2                                                         /*!< SCT EVFLAG: FLAG2 Position          */
-#define SCT_EVFLAG_FLAG2_Msk                                  (0x01UL << SCT_EVFLAG_FLAG2_Pos)                          /*!< SCT EVFLAG: FLAG2 Mask              */
-#define SCT_EVFLAG_FLAG3_Pos                                  3                                                         /*!< SCT EVFLAG: FLAG3 Position          */
-#define SCT_EVFLAG_FLAG3_Msk                                  (0x01UL << SCT_EVFLAG_FLAG3_Pos)                          /*!< SCT EVFLAG: FLAG3 Mask              */
-#define SCT_EVFLAG_FLAG4_Pos                                  4                                                         /*!< SCT EVFLAG: FLAG4 Position          */
-#define SCT_EVFLAG_FLAG4_Msk                                  (0x01UL << SCT_EVFLAG_FLAG4_Pos)                          /*!< SCT EVFLAG: FLAG4 Mask              */
-#define SCT_EVFLAG_FLAG5_Pos                                  5                                                         /*!< SCT EVFLAG: FLAG5 Position          */
-#define SCT_EVFLAG_FLAG5_Msk                                  (0x01UL << SCT_EVFLAG_FLAG5_Pos)                          /*!< SCT EVFLAG: FLAG5 Mask              */
-#define SCT_EVFLAG_FLAG6_Pos                                  6                                                         /*!< SCT EVFLAG: FLAG6 Position          */
-#define SCT_EVFLAG_FLAG6_Msk                                  (0x01UL << SCT_EVFLAG_FLAG6_Pos)                          /*!< SCT EVFLAG: FLAG6 Mask              */
-#define SCT_EVFLAG_FLAG7_Pos                                  7                                                         /*!< SCT EVFLAG: FLAG7 Position          */
-#define SCT_EVFLAG_FLAG7_Msk                                  (0x01UL << SCT_EVFLAG_FLAG7_Pos)                          /*!< SCT EVFLAG: FLAG7 Mask              */
-#define SCT_EVFLAG_FLAG8_Pos                                  8                                                         /*!< SCT EVFLAG: FLAG8 Position          */
-#define SCT_EVFLAG_FLAG8_Msk                                  (0x01UL << SCT_EVFLAG_FLAG8_Pos)                          /*!< SCT EVFLAG: FLAG8 Mask              */
-#define SCT_EVFLAG_FLAG9_Pos                                  9                                                         /*!< SCT EVFLAG: FLAG9 Position          */
-#define SCT_EVFLAG_FLAG9_Msk                                  (0x01UL << SCT_EVFLAG_FLAG9_Pos)                          /*!< SCT EVFLAG: FLAG9 Mask              */
-#define SCT_EVFLAG_FLAG10_Pos                                 10                                                        /*!< SCT EVFLAG: FLAG10 Position         */
-#define SCT_EVFLAG_FLAG10_Msk                                 (0x01UL << SCT_EVFLAG_FLAG10_Pos)                         /*!< SCT EVFLAG: FLAG10 Mask             */
-#define SCT_EVFLAG_FLAG11_Pos                                 11                                                        /*!< SCT EVFLAG: FLAG11 Position         */
-#define SCT_EVFLAG_FLAG11_Msk                                 (0x01UL << SCT_EVFLAG_FLAG11_Pos)                         /*!< SCT EVFLAG: FLAG11 Mask             */
-#define SCT_EVFLAG_FLAG12_Pos                                 12                                                        /*!< SCT EVFLAG: FLAG12 Position         */
-#define SCT_EVFLAG_FLAG12_Msk                                 (0x01UL << SCT_EVFLAG_FLAG12_Pos)                         /*!< SCT EVFLAG: FLAG12 Mask             */
-#define SCT_EVFLAG_FLAG13_Pos                                 13                                                        /*!< SCT EVFLAG: FLAG13 Position         */
-#define SCT_EVFLAG_FLAG13_Msk                                 (0x01UL << SCT_EVFLAG_FLAG13_Pos)                         /*!< SCT EVFLAG: FLAG13 Mask             */
-#define SCT_EVFLAG_FLAG14_Pos                                 14                                                        /*!< SCT EVFLAG: FLAG14 Position         */
-#define SCT_EVFLAG_FLAG14_Msk                                 (0x01UL << SCT_EVFLAG_FLAG14_Pos)                         /*!< SCT EVFLAG: FLAG14 Mask             */
-#define SCT_EVFLAG_FLAG15_Pos                                 15                                                        /*!< SCT EVFLAG: FLAG15 Position         */
-#define SCT_EVFLAG_FLAG15_Msk                                 (0x01UL << SCT_EVFLAG_FLAG15_Pos)                         /*!< SCT EVFLAG: FLAG15 Mask             */
-
-// ----------------------------------------  SCT_CONEN  -------------------------------------------
-#define SCT_CONEN_NCEN0_Pos                                   0                                                         /*!< SCT CONEN: NCEN0 Position           */
-#define SCT_CONEN_NCEN0_Msk                                   (0x01UL << SCT_CONEN_NCEN0_Pos)                           /*!< SCT CONEN: NCEN0 Mask               */
-#define SCT_CONEN_NCEN1_Pos                                   1                                                         /*!< SCT CONEN: NCEN1 Position           */
-#define SCT_CONEN_NCEN1_Msk                                   (0x01UL << SCT_CONEN_NCEN1_Pos)                           /*!< SCT CONEN: NCEN1 Mask               */
-#define SCT_CONEN_NCEN2_Pos                                   2                                                         /*!< SCT CONEN: NCEN2 Position           */
-#define SCT_CONEN_NCEN2_Msk                                   (0x01UL << SCT_CONEN_NCEN2_Pos)                           /*!< SCT CONEN: NCEN2 Mask               */
-#define SCT_CONEN_NCEN3_Pos                                   3                                                         /*!< SCT CONEN: NCEN3 Position           */
-#define SCT_CONEN_NCEN3_Msk                                   (0x01UL << SCT_CONEN_NCEN3_Pos)                           /*!< SCT CONEN: NCEN3 Mask               */
-#define SCT_CONEN_NCEN4_Pos                                   4                                                         /*!< SCT CONEN: NCEN4 Position           */
-#define SCT_CONEN_NCEN4_Msk                                   (0x01UL << SCT_CONEN_NCEN4_Pos)                           /*!< SCT CONEN: NCEN4 Mask               */
-#define SCT_CONEN_NCEN5_Pos                                   5                                                         /*!< SCT CONEN: NCEN5 Position           */
-#define SCT_CONEN_NCEN5_Msk                                   (0x01UL << SCT_CONEN_NCEN5_Pos)                           /*!< SCT CONEN: NCEN5 Mask               */
-#define SCT_CONEN_NCEN6_Pos                                   6                                                         /*!< SCT CONEN: NCEN6 Position           */
-#define SCT_CONEN_NCEN6_Msk                                   (0x01UL << SCT_CONEN_NCEN6_Pos)                           /*!< SCT CONEN: NCEN6 Mask               */
-#define SCT_CONEN_NCEN7_Pos                                   7                                                         /*!< SCT CONEN: NCEN7 Position           */
-#define SCT_CONEN_NCEN7_Msk                                   (0x01UL << SCT_CONEN_NCEN7_Pos)                           /*!< SCT CONEN: NCEN7 Mask               */
-#define SCT_CONEN_NCEN8_Pos                                   8                                                         /*!< SCT CONEN: NCEN8 Position           */
-#define SCT_CONEN_NCEN8_Msk                                   (0x01UL << SCT_CONEN_NCEN8_Pos)                           /*!< SCT CONEN: NCEN8 Mask               */
-#define SCT_CONEN_NCEN9_Pos                                   9                                                         /*!< SCT CONEN: NCEN9 Position           */
-#define SCT_CONEN_NCEN9_Msk                                   (0x01UL << SCT_CONEN_NCEN9_Pos)                           /*!< SCT CONEN: NCEN9 Mask               */
-#define SCT_CONEN_NCEN10_Pos                                  10                                                        /*!< SCT CONEN: NCEN10 Position          */
-#define SCT_CONEN_NCEN10_Msk                                  (0x01UL << SCT_CONEN_NCEN10_Pos)                          /*!< SCT CONEN: NCEN10 Mask              */
-#define SCT_CONEN_NCEN11_Pos                                  11                                                        /*!< SCT CONEN: NCEN11 Position          */
-#define SCT_CONEN_NCEN11_Msk                                  (0x01UL << SCT_CONEN_NCEN11_Pos)                          /*!< SCT CONEN: NCEN11 Mask              */
-#define SCT_CONEN_NCEN12_Pos                                  12                                                        /*!< SCT CONEN: NCEN12 Position          */
-#define SCT_CONEN_NCEN12_Msk                                  (0x01UL << SCT_CONEN_NCEN12_Pos)                          /*!< SCT CONEN: NCEN12 Mask              */
-#define SCT_CONEN_NCEN13_Pos                                  13                                                        /*!< SCT CONEN: NCEN13 Position          */
-#define SCT_CONEN_NCEN13_Msk                                  (0x01UL << SCT_CONEN_NCEN13_Pos)                          /*!< SCT CONEN: NCEN13 Mask              */
-#define SCT_CONEN_NCEN14_Pos                                  14                                                        /*!< SCT CONEN: NCEN14 Position          */
-#define SCT_CONEN_NCEN14_Msk                                  (0x01UL << SCT_CONEN_NCEN14_Pos)                          /*!< SCT CONEN: NCEN14 Mask              */
-#define SCT_CONEN_NCEN15_Pos                                  15                                                        /*!< SCT CONEN: NCEN15 Position          */
-#define SCT_CONEN_NCEN15_Msk                                  (0x01UL << SCT_CONEN_NCEN15_Pos)                          /*!< SCT CONEN: NCEN15 Mask              */
-
-// ---------------------------------------  SCT_CONFLAG  ------------------------------------------
-#define SCT_CONFLAG_NCFLAG0_Pos                               0                                                         /*!< SCT CONFLAG: NCFLAG0 Position       */
-#define SCT_CONFLAG_NCFLAG0_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG0_Pos)                       /*!< SCT CONFLAG: NCFLAG0 Mask           */
-#define SCT_CONFLAG_NCFLAG1_Pos                               1                                                         /*!< SCT CONFLAG: NCFLAG1 Position       */
-#define SCT_CONFLAG_NCFLAG1_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG1_Pos)                       /*!< SCT CONFLAG: NCFLAG1 Mask           */
-#define SCT_CONFLAG_NCFLAG2_Pos                               2                                                         /*!< SCT CONFLAG: NCFLAG2 Position       */
-#define SCT_CONFLAG_NCFLAG2_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG2_Pos)                       /*!< SCT CONFLAG: NCFLAG2 Mask           */
-#define SCT_CONFLAG_NCFLAG3_Pos                               3                                                         /*!< SCT CONFLAG: NCFLAG3 Position       */
-#define SCT_CONFLAG_NCFLAG3_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG3_Pos)                       /*!< SCT CONFLAG: NCFLAG3 Mask           */
-#define SCT_CONFLAG_NCFLAG4_Pos                               4                                                         /*!< SCT CONFLAG: NCFLAG4 Position       */
-#define SCT_CONFLAG_NCFLAG4_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG4_Pos)                       /*!< SCT CONFLAG: NCFLAG4 Mask           */
-#define SCT_CONFLAG_NCFLAG5_Pos                               5                                                         /*!< SCT CONFLAG: NCFLAG5 Position       */
-#define SCT_CONFLAG_NCFLAG5_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG5_Pos)                       /*!< SCT CONFLAG: NCFLAG5 Mask           */
-#define SCT_CONFLAG_NCFLAG6_Pos                               6                                                         /*!< SCT CONFLAG: NCFLAG6 Position       */
-#define SCT_CONFLAG_NCFLAG6_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG6_Pos)                       /*!< SCT CONFLAG: NCFLAG6 Mask           */
-#define SCT_CONFLAG_NCFLAG7_Pos                               7                                                         /*!< SCT CONFLAG: NCFLAG7 Position       */
-#define SCT_CONFLAG_NCFLAG7_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG7_Pos)                       /*!< SCT CONFLAG: NCFLAG7 Mask           */
-#define SCT_CONFLAG_NCFLAG8_Pos                               8                                                         /*!< SCT CONFLAG: NCFLAG8 Position       */
-#define SCT_CONFLAG_NCFLAG8_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG8_Pos)                       /*!< SCT CONFLAG: NCFLAG8 Mask           */
-#define SCT_CONFLAG_NCFLAG9_Pos                               9                                                         /*!< SCT CONFLAG: NCFLAG9 Position       */
-#define SCT_CONFLAG_NCFLAG9_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG9_Pos)                       /*!< SCT CONFLAG: NCFLAG9 Mask           */
-#define SCT_CONFLAG_NCFLAG10_Pos                              10                                                        /*!< SCT CONFLAG: NCFLAG10 Position      */
-#define SCT_CONFLAG_NCFLAG10_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG10_Pos)                      /*!< SCT CONFLAG: NCFLAG10 Mask          */
-#define SCT_CONFLAG_NCFLAG11_Pos                              11                                                        /*!< SCT CONFLAG: NCFLAG11 Position      */
-#define SCT_CONFLAG_NCFLAG11_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG11_Pos)                      /*!< SCT CONFLAG: NCFLAG11 Mask          */
-#define SCT_CONFLAG_NCFLAG12_Pos                              12                                                        /*!< SCT CONFLAG: NCFLAG12 Position      */
-#define SCT_CONFLAG_NCFLAG12_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG12_Pos)                      /*!< SCT CONFLAG: NCFLAG12 Mask          */
-#define SCT_CONFLAG_NCFLAG13_Pos                              13                                                        /*!< SCT CONFLAG: NCFLAG13 Position      */
-#define SCT_CONFLAG_NCFLAG13_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG13_Pos)                      /*!< SCT CONFLAG: NCFLAG13 Mask          */
-#define SCT_CONFLAG_NCFLAG14_Pos                              14                                                        /*!< SCT CONFLAG: NCFLAG14 Position      */
-#define SCT_CONFLAG_NCFLAG14_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG14_Pos)                      /*!< SCT CONFLAG: NCFLAG14 Mask          */
-#define SCT_CONFLAG_NCFLAG15_Pos                              15                                                        /*!< SCT CONFLAG: NCFLAG15 Position      */
-#define SCT_CONFLAG_NCFLAG15_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG15_Pos)                      /*!< SCT CONFLAG: NCFLAG15 Mask          */
-#define SCT_CONFLAG_BUSERRL_Pos                               30                                                        /*!< SCT CONFLAG: BUSERRL Position       */
-#define SCT_CONFLAG_BUSERRL_Msk                               (0x01UL << SCT_CONFLAG_BUSERRL_Pos)                       /*!< SCT CONFLAG: BUSERRL Mask           */
-#define SCT_CONFLAG_BUSERRH_Pos                               31                                                        /*!< SCT CONFLAG: BUSERRH Position       */
-#define SCT_CONFLAG_BUSERRH_Msk                               (0x01UL << SCT_CONFLAG_BUSERRH_Pos)                       /*!< SCT CONFLAG: BUSERRH Mask           */
-
-// ---------------------------------------  SCT_MATCH0  -------------------------------------------
-#define SCT_MATCH0_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH0: MATCHn_L Position       */
-#define SCT_MATCH0_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos)                 /*!< SCT MATCH0: MATCHn_L Mask           */
-#define SCT_MATCH0_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH0: MATCHn_H Position       */
-#define SCT_MATCH0_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos)                 /*!< SCT MATCH0: MATCHn_H Mask           */
-
-// ----------------------------------------  SCT_CAP0  --------------------------------------------
-#define SCT_CAP0_CAPn_L_Pos                                   0                                                         /*!< SCT CAP0: CAPn_L Position           */
-#define SCT_CAP0_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos)                     /*!< SCT CAP0: CAPn_L Mask               */
-#define SCT_CAP0_CAPn_H_Pos                                   16                                                        /*!< SCT CAP0: CAPn_H Position           */
-#define SCT_CAP0_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos)                     /*!< SCT CAP0: CAPn_H Mask               */
-
-// ---------------------------------------  SCT_MATCH1  -------------------------------------------
-#define SCT_MATCH1_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH1: MATCHn_L Position       */
-#define SCT_MATCH1_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos)                 /*!< SCT MATCH1: MATCHn_L Mask           */
-#define SCT_MATCH1_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH1: MATCHn_H Position       */
-#define SCT_MATCH1_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos)                 /*!< SCT MATCH1: MATCHn_H Mask           */
-
-// ----------------------------------------  SCT_CAP1  --------------------------------------------
-#define SCT_CAP1_CAPn_L_Pos                                   0                                                         /*!< SCT CAP1: CAPn_L Position           */
-#define SCT_CAP1_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos)                     /*!< SCT CAP1: CAPn_L Mask               */
-#define SCT_CAP1_CAPn_H_Pos                                   16                                                        /*!< SCT CAP1: CAPn_H Position           */
-#define SCT_CAP1_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos)                     /*!< SCT CAP1: CAPn_H Mask               */
-
-// ---------------------------------------  SCT_MATCH2  -------------------------------------------
-#define SCT_MATCH2_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH2: MATCHn_L Position       */
-#define SCT_MATCH2_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos)                 /*!< SCT MATCH2: MATCHn_L Mask           */
-#define SCT_MATCH2_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH2: MATCHn_H Position       */
-#define SCT_MATCH2_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos)                 /*!< SCT MATCH2: MATCHn_H Mask           */
-
-// ----------------------------------------  SCT_CAP2  --------------------------------------------
-#define SCT_CAP2_CAPn_L_Pos                                   0                                                         /*!< SCT CAP2: CAPn_L Position           */
-#define SCT_CAP2_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos)                     /*!< SCT CAP2: CAPn_L Mask               */
-#define SCT_CAP2_CAPn_H_Pos                                   16                                                        /*!< SCT CAP2: CAPn_H Position           */
-#define SCT_CAP2_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos)                     /*!< SCT CAP2: CAPn_H Mask               */
-
-// ----------------------------------------  SCT_CAP3  --------------------------------------------
-#define SCT_CAP3_CAPn_L_Pos                                   0                                                         /*!< SCT CAP3: CAPn_L Position           */
-#define SCT_CAP3_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos)                     /*!< SCT CAP3: CAPn_L Mask               */
-#define SCT_CAP3_CAPn_H_Pos                                   16                                                        /*!< SCT CAP3: CAPn_H Position           */
-#define SCT_CAP3_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos)                     /*!< SCT CAP3: CAPn_H Mask               */
-
-// ---------------------------------------  SCT_MATCH3  -------------------------------------------
-#define SCT_MATCH3_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH3: MATCHn_L Position       */
-#define SCT_MATCH3_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos)                 /*!< SCT MATCH3: MATCHn_L Mask           */
-#define SCT_MATCH3_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH3: MATCHn_H Position       */
-#define SCT_MATCH3_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos)                 /*!< SCT MATCH3: MATCHn_H Mask           */
-
-// ---------------------------------------  SCT_MATCH4  -------------------------------------------
-#define SCT_MATCH4_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH4: MATCHn_L Position       */
-#define SCT_MATCH4_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos)                 /*!< SCT MATCH4: MATCHn_L Mask           */
-#define SCT_MATCH4_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH4: MATCHn_H Position       */
-#define SCT_MATCH4_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos)                 /*!< SCT MATCH4: MATCHn_H Mask           */
-
-// ----------------------------------------  SCT_CAP4  --------------------------------------------
-#define SCT_CAP4_CAPn_L_Pos                                   0                                                         /*!< SCT CAP4: CAPn_L Position           */
-#define SCT_CAP4_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos)                     /*!< SCT CAP4: CAPn_L Mask               */
-#define SCT_CAP4_CAPn_H_Pos                                   16                                                        /*!< SCT CAP4: CAPn_H Position           */
-#define SCT_CAP4_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos)                     /*!< SCT CAP4: CAPn_H Mask               */
-
-// ---------------------------------------  SCT_MATCH5  -------------------------------------------
-#define SCT_MATCH5_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH5: MATCHn_L Position       */
-#define SCT_MATCH5_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos)                 /*!< SCT MATCH5: MATCHn_L Mask           */
-#define SCT_MATCH5_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH5: MATCHn_H Position       */
-#define SCT_MATCH5_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos)                 /*!< SCT MATCH5: MATCHn_H Mask           */
-
-// ----------------------------------------  SCT_CAP5  --------------------------------------------
-#define SCT_CAP5_CAPn_L_Pos                                   0                                                         /*!< SCT CAP5: CAPn_L Position           */
-#define SCT_CAP5_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos)                     /*!< SCT CAP5: CAPn_L Mask               */
-#define SCT_CAP5_CAPn_H_Pos                                   16                                                        /*!< SCT CAP5: CAPn_H Position           */
-#define SCT_CAP5_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos)                     /*!< SCT CAP5: CAPn_H Mask               */
-
-// ---------------------------------------  SCT_MATCH6  -------------------------------------------
-#define SCT_MATCH6_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH6: MATCHn_L Position       */
-#define SCT_MATCH6_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos)                 /*!< SCT MATCH6: MATCHn_L Mask           */
-#define SCT_MATCH6_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH6: MATCHn_H Position       */
-#define SCT_MATCH6_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos)                 /*!< SCT MATCH6: MATCHn_H Mask           */
-
-// ----------------------------------------  SCT_CAP6  --------------------------------------------
-#define SCT_CAP6_CAPn_L_Pos                                   0                                                         /*!< SCT CAP6: CAPn_L Position           */
-#define SCT_CAP6_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos)                     /*!< SCT CAP6: CAPn_L Mask               */
-#define SCT_CAP6_CAPn_H_Pos                                   16                                                        /*!< SCT CAP6: CAPn_H Position           */
-#define SCT_CAP6_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos)                     /*!< SCT CAP6: CAPn_H Mask               */
-
-// ----------------------------------------  SCT_CAP7  --------------------------------------------
-#define SCT_CAP7_CAPn_L_Pos                                   0                                                         /*!< SCT CAP7: CAPn_L Position           */
-#define SCT_CAP7_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos)                     /*!< SCT CAP7: CAPn_L Mask               */
-#define SCT_CAP7_CAPn_H_Pos                                   16                                                        /*!< SCT CAP7: CAPn_H Position           */
-#define SCT_CAP7_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos)                     /*!< SCT CAP7: CAPn_H Mask               */
-
-// ---------------------------------------  SCT_MATCH7  -------------------------------------------
-#define SCT_MATCH7_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH7: MATCHn_L Position       */
-#define SCT_MATCH7_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos)                 /*!< SCT MATCH7: MATCHn_L Mask           */
-#define SCT_MATCH7_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH7: MATCHn_H Position       */
-#define SCT_MATCH7_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos)                 /*!< SCT MATCH7: MATCHn_H Mask           */
-
-// ----------------------------------------  SCT_CAP8  --------------------------------------------
-#define SCT_CAP8_CAPn_L_Pos                                   0                                                         /*!< SCT CAP8: CAPn_L Position           */
-#define SCT_CAP8_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos)                     /*!< SCT CAP8: CAPn_L Mask               */
-#define SCT_CAP8_CAPn_H_Pos                                   16                                                        /*!< SCT CAP8: CAPn_H Position           */
-#define SCT_CAP8_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos)                     /*!< SCT CAP8: CAPn_H Mask               */
-
-// ---------------------------------------  SCT_MATCH8  -------------------------------------------
-#define SCT_MATCH8_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH8: MATCHn_L Position       */
-#define SCT_MATCH8_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos)                 /*!< SCT MATCH8: MATCHn_L Mask           */
-#define SCT_MATCH8_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH8: MATCHn_H Position       */
-#define SCT_MATCH8_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos)                 /*!< SCT MATCH8: MATCHn_H Mask           */
-
-// ---------------------------------------  SCT_MATCH9  -------------------------------------------
-#define SCT_MATCH9_MATCHn_L_Pos                               0                                                         /*!< SCT MATCH9: MATCHn_L Position       */
-#define SCT_MATCH9_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos)                 /*!< SCT MATCH9: MATCHn_L Mask           */
-#define SCT_MATCH9_MATCHn_H_Pos                               16                                                        /*!< SCT MATCH9: MATCHn_H Position       */
-#define SCT_MATCH9_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos)                 /*!< SCT MATCH9: MATCHn_H Mask           */
-
-// ----------------------------------------  SCT_CAP9  --------------------------------------------
-#define SCT_CAP9_CAPn_L_Pos                                   0                                                         /*!< SCT CAP9: CAPn_L Position           */
-#define SCT_CAP9_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos)                     /*!< SCT CAP9: CAPn_L Mask               */
-#define SCT_CAP9_CAPn_H_Pos                                   16                                                        /*!< SCT CAP9: CAPn_H Position           */
-#define SCT_CAP9_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos)                     /*!< SCT CAP9: CAPn_H Mask               */
-
-// ----------------------------------------  SCT_CAP10  -------------------------------------------
-#define SCT_CAP10_CAPn_L_Pos                                  0                                                         /*!< SCT CAP10: CAPn_L Position          */
-#define SCT_CAP10_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos)                    /*!< SCT CAP10: CAPn_L Mask              */
-#define SCT_CAP10_CAPn_H_Pos                                  16                                                        /*!< SCT CAP10: CAPn_H Position          */
-#define SCT_CAP10_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos)                    /*!< SCT CAP10: CAPn_H Mask              */
-
-// ---------------------------------------  SCT_MATCH10  ------------------------------------------
-#define SCT_MATCH10_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH10: MATCHn_L Position      */
-#define SCT_MATCH10_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos)                /*!< SCT MATCH10: MATCHn_L Mask          */
-#define SCT_MATCH10_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH10: MATCHn_H Position      */
-#define SCT_MATCH10_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos)                /*!< SCT MATCH10: MATCHn_H Mask          */
-
-// ----------------------------------------  SCT_CAP11  -------------------------------------------
-#define SCT_CAP11_CAPn_L_Pos                                  0                                                         /*!< SCT CAP11: CAPn_L Position          */
-#define SCT_CAP11_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos)                    /*!< SCT CAP11: CAPn_L Mask              */
-#define SCT_CAP11_CAPn_H_Pos                                  16                                                        /*!< SCT CAP11: CAPn_H Position          */
-#define SCT_CAP11_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos)                    /*!< SCT CAP11: CAPn_H Mask              */
-
-// ---------------------------------------  SCT_MATCH11  ------------------------------------------
-#define SCT_MATCH11_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH11: MATCHn_L Position      */
-#define SCT_MATCH11_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos)                /*!< SCT MATCH11: MATCHn_L Mask          */
-#define SCT_MATCH11_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH11: MATCHn_H Position      */
-#define SCT_MATCH11_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos)                /*!< SCT MATCH11: MATCHn_H Mask          */
-
-// ---------------------------------------  SCT_MATCH12  ------------------------------------------
-#define SCT_MATCH12_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH12: MATCHn_L Position      */
-#define SCT_MATCH12_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos)                /*!< SCT MATCH12: MATCHn_L Mask          */
-#define SCT_MATCH12_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH12: MATCHn_H Position      */
-#define SCT_MATCH12_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos)                /*!< SCT MATCH12: MATCHn_H Mask          */
-
-// ----------------------------------------  SCT_CAP12  -------------------------------------------
-#define SCT_CAP12_CAPn_L_Pos                                  0                                                         /*!< SCT CAP12: CAPn_L Position          */
-#define SCT_CAP12_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos)                    /*!< SCT CAP12: CAPn_L Mask              */
-#define SCT_CAP12_CAPn_H_Pos                                  16                                                        /*!< SCT CAP12: CAPn_H Position          */
-#define SCT_CAP12_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos)                    /*!< SCT CAP12: CAPn_H Mask              */
-
-// ----------------------------------------  SCT_CAP13  -------------------------------------------
-#define SCT_CAP13_CAPn_L_Pos                                  0                                                         /*!< SCT CAP13: CAPn_L Position          */
-#define SCT_CAP13_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos)                    /*!< SCT CAP13: CAPn_L Mask              */
-#define SCT_CAP13_CAPn_H_Pos                                  16                                                        /*!< SCT CAP13: CAPn_H Position          */
-#define SCT_CAP13_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos)                    /*!< SCT CAP13: CAPn_H Mask              */
-
-// ---------------------------------------  SCT_MATCH13  ------------------------------------------
-#define SCT_MATCH13_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH13: MATCHn_L Position      */
-#define SCT_MATCH13_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos)                /*!< SCT MATCH13: MATCHn_L Mask          */
-#define SCT_MATCH13_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH13: MATCHn_H Position      */
-#define SCT_MATCH13_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos)                /*!< SCT MATCH13: MATCHn_H Mask          */
-
-// ---------------------------------------  SCT_MATCH14  ------------------------------------------
-#define SCT_MATCH14_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH14: MATCHn_L Position      */
-#define SCT_MATCH14_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos)                /*!< SCT MATCH14: MATCHn_L Mask          */
-#define SCT_MATCH14_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH14: MATCHn_H Position      */
-#define SCT_MATCH14_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos)                /*!< SCT MATCH14: MATCHn_H Mask          */
-
-// ----------------------------------------  SCT_CAP14  -------------------------------------------
-#define SCT_CAP14_CAPn_L_Pos                                  0                                                         /*!< SCT CAP14: CAPn_L Position          */
-#define SCT_CAP14_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos)                    /*!< SCT CAP14: CAPn_L Mask              */
-#define SCT_CAP14_CAPn_H_Pos                                  16                                                        /*!< SCT CAP14: CAPn_H Position          */
-#define SCT_CAP14_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos)                    /*!< SCT CAP14: CAPn_H Mask              */
-
-// ---------------------------------------  SCT_MATCH15  ------------------------------------------
-#define SCT_MATCH15_MATCHn_L_Pos                              0                                                         /*!< SCT MATCH15: MATCHn_L Position      */
-#define SCT_MATCH15_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos)                /*!< SCT MATCH15: MATCHn_L Mask          */
-#define SCT_MATCH15_MATCHn_H_Pos                              16                                                        /*!< SCT MATCH15: MATCHn_H Position      */
-#define SCT_MATCH15_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos)                /*!< SCT MATCH15: MATCHn_H Mask          */
-
-// ----------------------------------------  SCT_CAP15  -------------------------------------------
-#define SCT_CAP15_CAPn_L_Pos                                  0                                                         /*!< SCT CAP15: CAPn_L Position          */
-#define SCT_CAP15_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos)                    /*!< SCT CAP15: CAPn_L Mask              */
-#define SCT_CAP15_CAPn_H_Pos                                  16                                                        /*!< SCT CAP15: CAPn_H Position          */
-#define SCT_CAP15_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos)                    /*!< SCT CAP15: CAPn_H Mask              */
-
-// --------------------------------------  SCT_MATCHREL0  -----------------------------------------
-#define SCT_MATCHREL0_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL0: RELOADn_L Position   */
-#define SCT_MATCHREL0_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos)             /*!< SCT MATCHREL0: RELOADn_L Mask       */
-#define SCT_MATCHREL0_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL0: RELOADn_H Position   */
-#define SCT_MATCHREL0_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos)             /*!< SCT MATCHREL0: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_CAPCTRL0  ------------------------------------------
-#define SCT_CAPCTRL0_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL0: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL0: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL0: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL0: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL0: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL0: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL0: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL0: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL0: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL0: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL0_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL0: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL0_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL0: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL0_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL0_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL0: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL0_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL0_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL0: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL0_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL0_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL0: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL0_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL0_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL0: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL0_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL0_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL0: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL0_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL0: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL0_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL0: CAPCONn_H Position    */
-#define SCT_CAPCTRL0_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos)              /*!< SCT CAPCTRL0: CAPCONn_H Mask        */
-
-// --------------------------------------  SCT_MATCHREL1  -----------------------------------------
-#define SCT_MATCHREL1_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL1: RELOADn_L Position   */
-#define SCT_MATCHREL1_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos)             /*!< SCT MATCHREL1: RELOADn_L Mask       */
-#define SCT_MATCHREL1_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL1: RELOADn_H Position   */
-#define SCT_MATCHREL1_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos)             /*!< SCT MATCHREL1: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_CAPCTRL1  ------------------------------------------
-#define SCT_CAPCTRL1_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL1: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL1: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL1: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL1: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL1: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL1: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL1: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL1: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL1: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL1: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL1_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL1: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL1_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL1: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL1_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL1_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL1: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL1_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL1_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL1: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL1_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL1_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL1: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL1_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL1_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL1: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL1_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL1_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL1: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL1_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL1: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL1_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL1: CAPCONn_H Position    */
-#define SCT_CAPCTRL1_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos)              /*!< SCT CAPCTRL1: CAPCONn_H Mask        */
-
-// --------------------------------------  SCT_MATCHREL2  -----------------------------------------
-#define SCT_MATCHREL2_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL2: RELOADn_L Position   */
-#define SCT_MATCHREL2_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos)             /*!< SCT MATCHREL2: RELOADn_L Mask       */
-#define SCT_MATCHREL2_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL2: RELOADn_H Position   */
-#define SCT_MATCHREL2_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos)             /*!< SCT MATCHREL2: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_CAPCTRL2  ------------------------------------------
-#define SCT_CAPCTRL2_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL2: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL2: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL2: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL2: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL2: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL2: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL2: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL2: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL2: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL2: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL2_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL2: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL2_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL2: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL2_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL2_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL2: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL2_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL2_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL2: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL2_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL2_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL2: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL2_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL2_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL2: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL2_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL2_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL2: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL2_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL2: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL2_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL2: CAPCONn_H Position    */
-#define SCT_CAPCTRL2_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos)              /*!< SCT CAPCTRL2: CAPCONn_H Mask        */
-
-// --------------------------------------  SCT_MATCHREL3  -----------------------------------------
-#define SCT_MATCHREL3_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL3: RELOADn_L Position   */
-#define SCT_MATCHREL3_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos)             /*!< SCT MATCHREL3: RELOADn_L Mask       */
-#define SCT_MATCHREL3_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL3: RELOADn_H Position   */
-#define SCT_MATCHREL3_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos)             /*!< SCT MATCHREL3: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_CAPCTRL3  ------------------------------------------
-#define SCT_CAPCTRL3_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL3: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL3: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL3: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL3: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL3: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL3: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL3: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL3: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL3: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL3: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL3_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL3: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL3_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL3: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL3_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL3_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL3: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL3_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL3_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL3: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL3_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL3_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL3: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL3_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL3_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL3: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL3_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL3_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL3: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL3_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL3: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL3_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL3: CAPCONn_H Position    */
-#define SCT_CAPCTRL3_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos)              /*!< SCT CAPCTRL3: CAPCONn_H Mask        */
-
-// --------------------------------------  SCT_CAPCTRL4  ------------------------------------------
-#define SCT_CAPCTRL4_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL4: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL4: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL4: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL4: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL4: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL4: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL4: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL4: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL4: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL4: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL4_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL4: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL4_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL4: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL4_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL4_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL4: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL4_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL4_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL4: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL4_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL4_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL4: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL4_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL4_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL4: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL4_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL4_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL4: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL4_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL4: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL4_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL4: CAPCONn_H Position    */
-#define SCT_CAPCTRL4_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos)              /*!< SCT CAPCTRL4: CAPCONn_H Mask        */
-
-// --------------------------------------  SCT_MATCHREL4  -----------------------------------------
-#define SCT_MATCHREL4_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL4: RELOADn_L Position   */
-#define SCT_MATCHREL4_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos)             /*!< SCT MATCHREL4: RELOADn_L Mask       */
-#define SCT_MATCHREL4_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL4: RELOADn_H Position   */
-#define SCT_MATCHREL4_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos)             /*!< SCT MATCHREL4: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_CAPCTRL5  ------------------------------------------
-#define SCT_CAPCTRL5_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL5: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL5: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL5: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL5: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL5: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL5: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL5: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL5: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL5: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL5: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL5_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL5: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL5_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL5: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL5_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL5_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL5: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL5_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL5_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL5: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL5_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL5_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL5: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL5_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL5_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL5: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL5_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL5_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL5: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL5_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL5: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL5_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL5: CAPCONn_H Position    */
-#define SCT_CAPCTRL5_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos)              /*!< SCT CAPCTRL5: CAPCONn_H Mask        */
-
-// --------------------------------------  SCT_MATCHREL5  -----------------------------------------
-#define SCT_MATCHREL5_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL5: RELOADn_L Position   */
-#define SCT_MATCHREL5_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos)             /*!< SCT MATCHREL5: RELOADn_L Mask       */
-#define SCT_MATCHREL5_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL5: RELOADn_H Position   */
-#define SCT_MATCHREL5_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos)             /*!< SCT MATCHREL5: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_MATCHREL6  -----------------------------------------
-#define SCT_MATCHREL6_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL6: RELOADn_L Position   */
-#define SCT_MATCHREL6_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos)             /*!< SCT MATCHREL6: RELOADn_L Mask       */
-#define SCT_MATCHREL6_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL6: RELOADn_H Position   */
-#define SCT_MATCHREL6_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos)             /*!< SCT MATCHREL6: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_CAPCTRL6  ------------------------------------------
-#define SCT_CAPCTRL6_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL6: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL6: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL6: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL6: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL6: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL6: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL6: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL6: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL6: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL6: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL6_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL6: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL6_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL6: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL6_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL6_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL6: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL6_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL6_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL6: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL6_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL6_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL6: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL6_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL6_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL6: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL6_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL6_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL6: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL6_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL6: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL6_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL6: CAPCONn_H Position    */
-#define SCT_CAPCTRL6_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos)              /*!< SCT CAPCTRL6: CAPCONn_H Mask        */
-
-// --------------------------------------  SCT_CAPCTRL7  ------------------------------------------
-#define SCT_CAPCTRL7_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL7: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL7: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL7: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL7: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL7: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL7: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL7: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL7: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL7: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL7: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL7_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL7: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL7_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL7: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL7_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL7_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL7: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL7_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL7_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL7: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL7_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL7_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL7: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL7_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL7_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL7: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL7_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL7_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL7: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL7_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL7: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL7_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL7: CAPCONn_H Position    */
-#define SCT_CAPCTRL7_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos)              /*!< SCT CAPCTRL7: CAPCONn_H Mask        */
-
-// --------------------------------------  SCT_MATCHREL7  -----------------------------------------
-#define SCT_MATCHREL7_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL7: RELOADn_L Position   */
-#define SCT_MATCHREL7_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos)             /*!< SCT MATCHREL7: RELOADn_L Mask       */
-#define SCT_MATCHREL7_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL7: RELOADn_H Position   */
-#define SCT_MATCHREL7_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos)             /*!< SCT MATCHREL7: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_CAPCTRL8  ------------------------------------------
-#define SCT_CAPCTRL8_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL8: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL8: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL8: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL8: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL8: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL8: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL8: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL8: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL8: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL8: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL8_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL8: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL8_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL8: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL8_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL8_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL8: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL8_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL8_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL8: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL8_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL8_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL8: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL8_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL8_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL8: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL8_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL8_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL8: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL8_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL8: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL8_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL8: CAPCONn_H Position    */
-#define SCT_CAPCTRL8_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos)              /*!< SCT CAPCTRL8: CAPCONn_H Mask        */
-
-// --------------------------------------  SCT_MATCHREL8  -----------------------------------------
-#define SCT_MATCHREL8_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL8: RELOADn_L Position   */
-#define SCT_MATCHREL8_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos)             /*!< SCT MATCHREL8: RELOADn_L Mask       */
-#define SCT_MATCHREL8_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL8: RELOADn_H Position   */
-#define SCT_MATCHREL8_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos)             /*!< SCT MATCHREL8: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_MATCHREL9  -----------------------------------------
-#define SCT_MATCHREL9_RELOADn_L_Pos                           0                                                         /*!< SCT MATCHREL9: RELOADn_L Position   */
-#define SCT_MATCHREL9_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos)             /*!< SCT MATCHREL9: RELOADn_L Mask       */
-#define SCT_MATCHREL9_RELOADn_H_Pos                           16                                                        /*!< SCT MATCHREL9: RELOADn_H Position   */
-#define SCT_MATCHREL9_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos)             /*!< SCT MATCHREL9: RELOADn_H Mask       */
-
-// --------------------------------------  SCT_CAPCTRL9  ------------------------------------------
-#define SCT_CAPCTRL9_CAPCONn_L0_Pos                           0                                                         /*!< SCT CAPCTRL9: CAPCONn_L0 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L0 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L1_Pos                           1                                                         /*!< SCT CAPCTRL9: CAPCONn_L1 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L1 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L2_Pos                           2                                                         /*!< SCT CAPCTRL9: CAPCONn_L2 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L2 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L3_Pos                           3                                                         /*!< SCT CAPCTRL9: CAPCONn_L3 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L3 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L4_Pos                           4                                                         /*!< SCT CAPCTRL9: CAPCONn_L4 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L4 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L5_Pos                           5                                                         /*!< SCT CAPCTRL9: CAPCONn_L5 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L5 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L6_Pos                           6                                                         /*!< SCT CAPCTRL9: CAPCONn_L6 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L6 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L7_Pos                           7                                                         /*!< SCT CAPCTRL9: CAPCONn_L7 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L7 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L8_Pos                           8                                                         /*!< SCT CAPCTRL9: CAPCONn_L8 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L8 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L9_Pos                           9                                                         /*!< SCT CAPCTRL9: CAPCONn_L9 Position   */
-#define SCT_CAPCTRL9_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos)                   /*!< SCT CAPCTRL9: CAPCONn_L9 Mask       */
-#define SCT_CAPCTRL9_CAPCONn_L10_Pos                          10                                                        /*!< SCT CAPCTRL9: CAPCONn_L10 Position  */
-#define SCT_CAPCTRL9_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L10 Mask      */
-#define SCT_CAPCTRL9_CAPCONn_L11_Pos                          11                                                        /*!< SCT CAPCTRL9: CAPCONn_L11 Position  */
-#define SCT_CAPCTRL9_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L11 Mask      */
-#define SCT_CAPCTRL9_CAPCONn_L12_Pos                          12                                                        /*!< SCT CAPCTRL9: CAPCONn_L12 Position  */
-#define SCT_CAPCTRL9_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L12 Mask      */
-#define SCT_CAPCTRL9_CAPCONn_L13_Pos                          13                                                        /*!< SCT CAPCTRL9: CAPCONn_L13 Position  */
-#define SCT_CAPCTRL9_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L13 Mask      */
-#define SCT_CAPCTRL9_CAPCONn_L14_Pos                          14                                                        /*!< SCT CAPCTRL9: CAPCONn_L14 Position  */
-#define SCT_CAPCTRL9_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L14 Mask      */
-#define SCT_CAPCTRL9_CAPCONn_L15_Pos                          15                                                        /*!< SCT CAPCTRL9: CAPCONn_L15 Position  */
-#define SCT_CAPCTRL9_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos)                  /*!< SCT CAPCTRL9: CAPCONn_L15 Mask      */
-#define SCT_CAPCTRL9_CAPCONn_H_Pos                            16                                                        /*!< SCT CAPCTRL9: CAPCONn_H Position    */
-#define SCT_CAPCTRL9_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos)              /*!< SCT CAPCTRL9: CAPCONn_H Mask        */
-
-// -------------------------------------  SCT_MATCHREL10  -----------------------------------------
-#define SCT_MATCHREL10_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL10: RELOADn_L Position  */
-#define SCT_MATCHREL10_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos)            /*!< SCT MATCHREL10: RELOADn_L Mask      */
-#define SCT_MATCHREL10_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL10: RELOADn_H Position  */
-#define SCT_MATCHREL10_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos)            /*!< SCT MATCHREL10: RELOADn_H Mask      */
-
-// --------------------------------------  SCT_CAPCTRL10  -----------------------------------------
-#define SCT_CAPCTRL10_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL10: CAPCONn_L0 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L0 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL10: CAPCONn_L1 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L1 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL10: CAPCONn_L2 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L2 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL10: CAPCONn_L3 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L3 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL10: CAPCONn_L4 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L4 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL10: CAPCONn_L5 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L5 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL10: CAPCONn_L6 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L6 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL10: CAPCONn_L7 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L7 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL10: CAPCONn_L8 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L8 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL10: CAPCONn_L9 Position  */
-#define SCT_CAPCTRL10_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL10: CAPCONn_L9 Mask      */
-#define SCT_CAPCTRL10_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL10: CAPCONn_L10 Position */
-#define SCT_CAPCTRL10_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L10 Mask     */
-#define SCT_CAPCTRL10_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL10: CAPCONn_L11 Position */
-#define SCT_CAPCTRL10_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L11 Mask     */
-#define SCT_CAPCTRL10_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL10: CAPCONn_L12 Position */
-#define SCT_CAPCTRL10_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L12 Mask     */
-#define SCT_CAPCTRL10_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL10: CAPCONn_L13 Position */
-#define SCT_CAPCTRL10_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L13 Mask     */
-#define SCT_CAPCTRL10_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL10: CAPCONn_L14 Position */
-#define SCT_CAPCTRL10_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L14 Mask     */
-#define SCT_CAPCTRL10_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL10: CAPCONn_L15 Position */
-#define SCT_CAPCTRL10_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL10: CAPCONn_L15 Mask     */
-#define SCT_CAPCTRL10_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL10: CAPCONn_H Position   */
-#define SCT_CAPCTRL10_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos)             /*!< SCT CAPCTRL10: CAPCONn_H Mask       */
-
-// -------------------------------------  SCT_MATCHREL11  -----------------------------------------
-#define SCT_MATCHREL11_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL11: RELOADn_L Position  */
-#define SCT_MATCHREL11_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos)            /*!< SCT MATCHREL11: RELOADn_L Mask      */
-#define SCT_MATCHREL11_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL11: RELOADn_H Position  */
-#define SCT_MATCHREL11_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos)            /*!< SCT MATCHREL11: RELOADn_H Mask      */
-
-// --------------------------------------  SCT_CAPCTRL11  -----------------------------------------
-#define SCT_CAPCTRL11_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL11: CAPCONn_L0 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L0 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL11: CAPCONn_L1 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L1 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL11: CAPCONn_L2 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L2 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL11: CAPCONn_L3 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L3 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL11: CAPCONn_L4 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L4 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL11: CAPCONn_L5 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L5 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL11: CAPCONn_L6 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L6 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL11: CAPCONn_L7 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L7 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL11: CAPCONn_L8 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L8 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL11: CAPCONn_L9 Position  */
-#define SCT_CAPCTRL11_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL11: CAPCONn_L9 Mask      */
-#define SCT_CAPCTRL11_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL11: CAPCONn_L10 Position */
-#define SCT_CAPCTRL11_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L10 Mask     */
-#define SCT_CAPCTRL11_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL11: CAPCONn_L11 Position */
-#define SCT_CAPCTRL11_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L11 Mask     */
-#define SCT_CAPCTRL11_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL11: CAPCONn_L12 Position */
-#define SCT_CAPCTRL11_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L12 Mask     */
-#define SCT_CAPCTRL11_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL11: CAPCONn_L13 Position */
-#define SCT_CAPCTRL11_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L13 Mask     */
-#define SCT_CAPCTRL11_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL11: CAPCONn_L14 Position */
-#define SCT_CAPCTRL11_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L14 Mask     */
-#define SCT_CAPCTRL11_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL11: CAPCONn_L15 Position */
-#define SCT_CAPCTRL11_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL11: CAPCONn_L15 Mask     */
-#define SCT_CAPCTRL11_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL11: CAPCONn_H Position   */
-#define SCT_CAPCTRL11_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos)             /*!< SCT CAPCTRL11: CAPCONn_H Mask       */
-
-// -------------------------------------  SCT_MATCHREL12  -----------------------------------------
-#define SCT_MATCHREL12_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL12: RELOADn_L Position  */
-#define SCT_MATCHREL12_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos)            /*!< SCT MATCHREL12: RELOADn_L Mask      */
-#define SCT_MATCHREL12_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL12: RELOADn_H Position  */
-#define SCT_MATCHREL12_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos)            /*!< SCT MATCHREL12: RELOADn_H Mask      */
-
-// --------------------------------------  SCT_CAPCTRL12  -----------------------------------------
-#define SCT_CAPCTRL12_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL12: CAPCONn_L0 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L0 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL12: CAPCONn_L1 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L1 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL12: CAPCONn_L2 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L2 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL12: CAPCONn_L3 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L3 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL12: CAPCONn_L4 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L4 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL12: CAPCONn_L5 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L5 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL12: CAPCONn_L6 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L6 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL12: CAPCONn_L7 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L7 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL12: CAPCONn_L8 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L8 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL12: CAPCONn_L9 Position  */
-#define SCT_CAPCTRL12_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL12: CAPCONn_L9 Mask      */
-#define SCT_CAPCTRL12_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL12: CAPCONn_L10 Position */
-#define SCT_CAPCTRL12_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L10 Mask     */
-#define SCT_CAPCTRL12_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL12: CAPCONn_L11 Position */
-#define SCT_CAPCTRL12_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L11 Mask     */
-#define SCT_CAPCTRL12_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL12: CAPCONn_L12 Position */
-#define SCT_CAPCTRL12_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L12 Mask     */
-#define SCT_CAPCTRL12_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL12: CAPCONn_L13 Position */
-#define SCT_CAPCTRL12_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L13 Mask     */
-#define SCT_CAPCTRL12_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL12: CAPCONn_L14 Position */
-#define SCT_CAPCTRL12_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L14 Mask     */
-#define SCT_CAPCTRL12_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL12: CAPCONn_L15 Position */
-#define SCT_CAPCTRL12_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL12: CAPCONn_L15 Mask     */
-#define SCT_CAPCTRL12_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL12: CAPCONn_H Position   */
-#define SCT_CAPCTRL12_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos)             /*!< SCT CAPCTRL12: CAPCONn_H Mask       */
-
-// -------------------------------------  SCT_MATCHREL13  -----------------------------------------
-#define SCT_MATCHREL13_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL13: RELOADn_L Position  */
-#define SCT_MATCHREL13_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos)            /*!< SCT MATCHREL13: RELOADn_L Mask      */
-#define SCT_MATCHREL13_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL13: RELOADn_H Position  */
-#define SCT_MATCHREL13_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos)            /*!< SCT MATCHREL13: RELOADn_H Mask      */
-
-// --------------------------------------  SCT_CAPCTRL13  -----------------------------------------
-#define SCT_CAPCTRL13_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL13: CAPCONn_L0 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L0 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL13: CAPCONn_L1 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L1 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL13: CAPCONn_L2 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L2 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL13: CAPCONn_L3 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L3 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL13: CAPCONn_L4 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L4 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL13: CAPCONn_L5 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L5 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL13: CAPCONn_L6 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L6 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL13: CAPCONn_L7 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L7 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL13: CAPCONn_L8 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L8 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL13: CAPCONn_L9 Position  */
-#define SCT_CAPCTRL13_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL13: CAPCONn_L9 Mask      */
-#define SCT_CAPCTRL13_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL13: CAPCONn_L10 Position */
-#define SCT_CAPCTRL13_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L10 Mask     */
-#define SCT_CAPCTRL13_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL13: CAPCONn_L11 Position */
-#define SCT_CAPCTRL13_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L11 Mask     */
-#define SCT_CAPCTRL13_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL13: CAPCONn_L12 Position */
-#define SCT_CAPCTRL13_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L12 Mask     */
-#define SCT_CAPCTRL13_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL13: CAPCONn_L13 Position */
-#define SCT_CAPCTRL13_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L13 Mask     */
-#define SCT_CAPCTRL13_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL13: CAPCONn_L14 Position */
-#define SCT_CAPCTRL13_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L14 Mask     */
-#define SCT_CAPCTRL13_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL13: CAPCONn_L15 Position */
-#define SCT_CAPCTRL13_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL13: CAPCONn_L15 Mask     */
-#define SCT_CAPCTRL13_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL13: CAPCONn_H Position   */
-#define SCT_CAPCTRL13_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos)             /*!< SCT CAPCTRL13: CAPCONn_H Mask       */
-
-// -------------------------------------  SCT_MATCHREL14  -----------------------------------------
-#define SCT_MATCHREL14_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL14: RELOADn_L Position  */
-#define SCT_MATCHREL14_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos)            /*!< SCT MATCHREL14: RELOADn_L Mask      */
-#define SCT_MATCHREL14_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL14: RELOADn_H Position  */
-#define SCT_MATCHREL14_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos)            /*!< SCT MATCHREL14: RELOADn_H Mask      */
-
-// --------------------------------------  SCT_CAPCTRL14  -----------------------------------------
-#define SCT_CAPCTRL14_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL14: CAPCONn_L0 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L0 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL14: CAPCONn_L1 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L1 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL14: CAPCONn_L2 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L2 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL14: CAPCONn_L3 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L3 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL14: CAPCONn_L4 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L4 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL14: CAPCONn_L5 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L5 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL14: CAPCONn_L6 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L6 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL14: CAPCONn_L7 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L7 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL14: CAPCONn_L8 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L8 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL14: CAPCONn_L9 Position  */
-#define SCT_CAPCTRL14_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL14: CAPCONn_L9 Mask      */
-#define SCT_CAPCTRL14_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL14: CAPCONn_L10 Position */
-#define SCT_CAPCTRL14_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L10 Mask     */
-#define SCT_CAPCTRL14_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL14: CAPCONn_L11 Position */
-#define SCT_CAPCTRL14_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L11 Mask     */
-#define SCT_CAPCTRL14_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL14: CAPCONn_L12 Position */
-#define SCT_CAPCTRL14_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L12 Mask     */
-#define SCT_CAPCTRL14_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL14: CAPCONn_L13 Position */
-#define SCT_CAPCTRL14_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L13 Mask     */
-#define SCT_CAPCTRL14_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL14: CAPCONn_L14 Position */
-#define SCT_CAPCTRL14_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L14 Mask     */
-#define SCT_CAPCTRL14_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL14: CAPCONn_L15 Position */
-#define SCT_CAPCTRL14_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL14: CAPCONn_L15 Mask     */
-#define SCT_CAPCTRL14_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL14: CAPCONn_H Position   */
-#define SCT_CAPCTRL14_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos)             /*!< SCT CAPCTRL14: CAPCONn_H Mask       */
-
-// -------------------------------------  SCT_MATCHREL15  -----------------------------------------
-#define SCT_MATCHREL15_RELOADn_L_Pos                          0                                                         /*!< SCT MATCHREL15: RELOADn_L Position  */
-#define SCT_MATCHREL15_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos)            /*!< SCT MATCHREL15: RELOADn_L Mask      */
-#define SCT_MATCHREL15_RELOADn_H_Pos                          16                                                        /*!< SCT MATCHREL15: RELOADn_H Position  */
-#define SCT_MATCHREL15_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos)            /*!< SCT MATCHREL15: RELOADn_H Mask      */
-
-// --------------------------------------  SCT_CAPCTRL15  -----------------------------------------
-#define SCT_CAPCTRL15_CAPCONn_L0_Pos                          0                                                         /*!< SCT CAPCTRL15: CAPCONn_L0 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L0 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L1_Pos                          1                                                         /*!< SCT CAPCTRL15: CAPCONn_L1 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L1 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L2_Pos                          2                                                         /*!< SCT CAPCTRL15: CAPCONn_L2 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L2 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L3_Pos                          3                                                         /*!< SCT CAPCTRL15: CAPCONn_L3 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L3 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L4_Pos                          4                                                         /*!< SCT CAPCTRL15: CAPCONn_L4 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L4 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L5_Pos                          5                                                         /*!< SCT CAPCTRL15: CAPCONn_L5 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L5 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L6_Pos                          6                                                         /*!< SCT CAPCTRL15: CAPCONn_L6 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L6 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L7_Pos                          7                                                         /*!< SCT CAPCTRL15: CAPCONn_L7 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L7 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L8_Pos                          8                                                         /*!< SCT CAPCTRL15: CAPCONn_L8 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L8 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L9_Pos                          9                                                         /*!< SCT CAPCTRL15: CAPCONn_L9 Position  */
-#define SCT_CAPCTRL15_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos)                  /*!< SCT CAPCTRL15: CAPCONn_L9 Mask      */
-#define SCT_CAPCTRL15_CAPCONn_L10_Pos                         10                                                        /*!< SCT CAPCTRL15: CAPCONn_L10 Position */
-#define SCT_CAPCTRL15_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L10 Mask     */
-#define SCT_CAPCTRL15_CAPCONn_L11_Pos                         11                                                        /*!< SCT CAPCTRL15: CAPCONn_L11 Position */
-#define SCT_CAPCTRL15_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L11 Mask     */
-#define SCT_CAPCTRL15_CAPCONn_L12_Pos                         12                                                        /*!< SCT CAPCTRL15: CAPCONn_L12 Position */
-#define SCT_CAPCTRL15_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L12 Mask     */
-#define SCT_CAPCTRL15_CAPCONn_L13_Pos                         13                                                        /*!< SCT CAPCTRL15: CAPCONn_L13 Position */
-#define SCT_CAPCTRL15_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L13 Mask     */
-#define SCT_CAPCTRL15_CAPCONn_L14_Pos                         14                                                        /*!< SCT CAPCTRL15: CAPCONn_L14 Position */
-#define SCT_CAPCTRL15_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L14 Mask     */
-#define SCT_CAPCTRL15_CAPCONn_L15_Pos                         15                                                        /*!< SCT CAPCTRL15: CAPCONn_L15 Position */
-#define SCT_CAPCTRL15_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos)                 /*!< SCT CAPCTRL15: CAPCONn_L15 Mask     */
-#define SCT_CAPCTRL15_CAPCONn_H_Pos                           16                                                        /*!< SCT CAPCTRL15: CAPCONn_H Position   */
-#define SCT_CAPCTRL15_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos)             /*!< SCT CAPCTRL15: CAPCONn_H Mask       */
-
-// -------------------------------------  SCT_EVSTATEMSK0  ----------------------------------------
-#define SCT_EVSTATEMSK0_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK0: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK0: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK0: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK0: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK0: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK0: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK0: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK0: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK0: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK0: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK0: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK0_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK0: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK0: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK0: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK0: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK0: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK0: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK0: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK0: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK0: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK0: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK0: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK0: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK0: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK0: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK0: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK0: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK0: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK0: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK0: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK0: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK0: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK0_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK0: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK0_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK0: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL0  ------------------------------------------
-#define SCT_EVCTRL0_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL0: MATCHSEL Position      */
-#define SCT_EVCTRL0_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos)                      /*!< SCT EVCTRL0: MATCHSEL Mask          */
-#define SCT_EVCTRL0_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL0: HEVENT Position        */
-#define SCT_EVCTRL0_HEVENT_Msk                                (0x01UL << SCT_EVCTRL0_HEVENT_Pos)                        /*!< SCT EVCTRL0: HEVENT Mask            */
-#define SCT_EVCTRL0_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL0: OUTSEL Position        */
-#define SCT_EVCTRL0_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL0_OUTSEL_Pos)                        /*!< SCT EVCTRL0: OUTSEL Mask            */
-#define SCT_EVCTRL0_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL0: IOSEL Position         */
-#define SCT_EVCTRL0_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL0_IOSEL_Pos)                         /*!< SCT EVCTRL0: IOSEL Mask             */
-#define SCT_EVCTRL0_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL0: IOCOND Position        */
-#define SCT_EVCTRL0_IOCOND_Msk                                (0x03UL << SCT_EVCTRL0_IOCOND_Pos)                        /*!< SCT EVCTRL0: IOCOND Mask            */
-#define SCT_EVCTRL0_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL0: COMBMODE Position      */
-#define SCT_EVCTRL0_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL0_COMBMODE_Pos)                      /*!< SCT EVCTRL0: COMBMODE Mask          */
-#define SCT_EVCTRL0_STATELD_Pos                               14                                                        /*!< SCT EVCTRL0: STATELD Position       */
-#define SCT_EVCTRL0_STATELD_Msk                               (0x01UL << SCT_EVCTRL0_STATELD_Pos)                       /*!< SCT EVCTRL0: STATELD Mask           */
-#define SCT_EVCTRL0_STATEV_Pos                                15                                                        /*!< SCT EVCTRL0: STATEV Position        */
-#define SCT_EVCTRL0_STATEV_Msk                                (0x1fUL << SCT_EVCTRL0_STATEV_Pos)                        /*!< SCT EVCTRL0: STATEV Mask            */
-
-// -------------------------------------  SCT_EVSTATEMSK1  ----------------------------------------
-#define SCT_EVSTATEMSK1_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK1: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK1: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK1: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK1: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK1: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK1: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK1: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK1: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK1: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK1: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK1: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK1_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK1: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK1: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK1: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK1: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK1: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK1: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK1: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK1: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK1: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK1: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK1: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK1: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK1: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK1: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK1: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK1: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK1: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK1: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK1: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK1: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK1: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK1_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK1: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK1_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK1: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL1  ------------------------------------------
-#define SCT_EVCTRL1_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL1: MATCHSEL Position      */
-#define SCT_EVCTRL1_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos)                      /*!< SCT EVCTRL1: MATCHSEL Mask          */
-#define SCT_EVCTRL1_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL1: HEVENT Position        */
-#define SCT_EVCTRL1_HEVENT_Msk                                (0x01UL << SCT_EVCTRL1_HEVENT_Pos)                        /*!< SCT EVCTRL1: HEVENT Mask            */
-#define SCT_EVCTRL1_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL1: OUTSEL Position        */
-#define SCT_EVCTRL1_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL1_OUTSEL_Pos)                        /*!< SCT EVCTRL1: OUTSEL Mask            */
-#define SCT_EVCTRL1_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL1: IOSEL Position         */
-#define SCT_EVCTRL1_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL1_IOSEL_Pos)                         /*!< SCT EVCTRL1: IOSEL Mask             */
-#define SCT_EVCTRL1_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL1: IOCOND Position        */
-#define SCT_EVCTRL1_IOCOND_Msk                                (0x03UL << SCT_EVCTRL1_IOCOND_Pos)                        /*!< SCT EVCTRL1: IOCOND Mask            */
-#define SCT_EVCTRL1_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL1: COMBMODE Position      */
-#define SCT_EVCTRL1_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL1_COMBMODE_Pos)                      /*!< SCT EVCTRL1: COMBMODE Mask          */
-#define SCT_EVCTRL1_STATELD_Pos                               14                                                        /*!< SCT EVCTRL1: STATELD Position       */
-#define SCT_EVCTRL1_STATELD_Msk                               (0x01UL << SCT_EVCTRL1_STATELD_Pos)                       /*!< SCT EVCTRL1: STATELD Mask           */
-#define SCT_EVCTRL1_STATEV_Pos                                15                                                        /*!< SCT EVCTRL1: STATEV Position        */
-#define SCT_EVCTRL1_STATEV_Msk                                (0x1fUL << SCT_EVCTRL1_STATEV_Pos)                        /*!< SCT EVCTRL1: STATEV Mask            */
-
-// -------------------------------------  SCT_EVSTATEMSK2  ----------------------------------------
-#define SCT_EVSTATEMSK2_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK2: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK2: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK2: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK2: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK2: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK2: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK2: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK2: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK2: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK2: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK2: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK2_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK2: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK2: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK2: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK2: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK2: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK2: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK2: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK2: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK2: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK2: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK2: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK2: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK2: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK2: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK2: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK2: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK2: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK2: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK2: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK2: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK2: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK2_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK2: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK2_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK2: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL2  ------------------------------------------
-#define SCT_EVCTRL2_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL2: MATCHSEL Position      */
-#define SCT_EVCTRL2_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos)                      /*!< SCT EVCTRL2: MATCHSEL Mask          */
-#define SCT_EVCTRL2_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL2: HEVENT Position        */
-#define SCT_EVCTRL2_HEVENT_Msk                                (0x01UL << SCT_EVCTRL2_HEVENT_Pos)                        /*!< SCT EVCTRL2: HEVENT Mask            */
-#define SCT_EVCTRL2_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL2: OUTSEL Position        */
-#define SCT_EVCTRL2_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL2_OUTSEL_Pos)                        /*!< SCT EVCTRL2: OUTSEL Mask            */
-#define SCT_EVCTRL2_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL2: IOSEL Position         */
-#define SCT_EVCTRL2_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL2_IOSEL_Pos)                         /*!< SCT EVCTRL2: IOSEL Mask             */
-#define SCT_EVCTRL2_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL2: IOCOND Position        */
-#define SCT_EVCTRL2_IOCOND_Msk                                (0x03UL << SCT_EVCTRL2_IOCOND_Pos)                        /*!< SCT EVCTRL2: IOCOND Mask            */
-#define SCT_EVCTRL2_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL2: COMBMODE Position      */
-#define SCT_EVCTRL2_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL2_COMBMODE_Pos)                      /*!< SCT EVCTRL2: COMBMODE Mask          */
-#define SCT_EVCTRL2_STATELD_Pos                               14                                                        /*!< SCT EVCTRL2: STATELD Position       */
-#define SCT_EVCTRL2_STATELD_Msk                               (0x01UL << SCT_EVCTRL2_STATELD_Pos)                       /*!< SCT EVCTRL2: STATELD Mask           */
-#define SCT_EVCTRL2_STATEV_Pos                                15                                                        /*!< SCT EVCTRL2: STATEV Position        */
-#define SCT_EVCTRL2_STATEV_Msk                                (0x1fUL << SCT_EVCTRL2_STATEV_Pos)                        /*!< SCT EVCTRL2: STATEV Mask            */
-
-// -------------------------------------  SCT_EVSTATEMSK3  ----------------------------------------
-#define SCT_EVSTATEMSK3_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK3: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK3: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK3: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK3: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK3: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK3: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK3: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK3: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK3: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK3: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK3: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK3_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK3: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK3: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK3: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK3: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK3: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK3: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK3: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK3: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK3: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK3: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK3: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK3: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK3: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK3: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK3: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK3: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK3: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK3: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK3: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK3: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK3: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK3_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK3: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK3_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK3: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL3  ------------------------------------------
-#define SCT_EVCTRL3_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL3: MATCHSEL Position      */
-#define SCT_EVCTRL3_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos)                      /*!< SCT EVCTRL3: MATCHSEL Mask          */
-#define SCT_EVCTRL3_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL3: HEVENT Position        */
-#define SCT_EVCTRL3_HEVENT_Msk                                (0x01UL << SCT_EVCTRL3_HEVENT_Pos)                        /*!< SCT EVCTRL3: HEVENT Mask            */
-#define SCT_EVCTRL3_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL3: OUTSEL Position        */
-#define SCT_EVCTRL3_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL3_OUTSEL_Pos)                        /*!< SCT EVCTRL3: OUTSEL Mask            */
-#define SCT_EVCTRL3_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL3: IOSEL Position         */
-#define SCT_EVCTRL3_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL3_IOSEL_Pos)                         /*!< SCT EVCTRL3: IOSEL Mask             */
-#define SCT_EVCTRL3_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL3: IOCOND Position        */
-#define SCT_EVCTRL3_IOCOND_Msk                                (0x03UL << SCT_EVCTRL3_IOCOND_Pos)                        /*!< SCT EVCTRL3: IOCOND Mask            */
-#define SCT_EVCTRL3_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL3: COMBMODE Position      */
-#define SCT_EVCTRL3_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL3_COMBMODE_Pos)                      /*!< SCT EVCTRL3: COMBMODE Mask          */
-#define SCT_EVCTRL3_STATELD_Pos                               14                                                        /*!< SCT EVCTRL3: STATELD Position       */
-#define SCT_EVCTRL3_STATELD_Msk                               (0x01UL << SCT_EVCTRL3_STATELD_Pos)                       /*!< SCT EVCTRL3: STATELD Mask           */
-#define SCT_EVCTRL3_STATEV_Pos                                15                                                        /*!< SCT EVCTRL3: STATEV Position        */
-#define SCT_EVCTRL3_STATEV_Msk                                (0x1fUL << SCT_EVCTRL3_STATEV_Pos)                        /*!< SCT EVCTRL3: STATEV Mask            */
-
-// -------------------------------------  SCT_EVSTATEMSK4  ----------------------------------------
-#define SCT_EVSTATEMSK4_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK4: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK4: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK4: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK4: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK4: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK4: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK4: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK4: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK4: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK4: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK4: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK4_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK4: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK4: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK4: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK4: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK4: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK4: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK4: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK4: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK4: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK4: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK4: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK4: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK4: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK4: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK4: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK4: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK4: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK4: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK4: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK4: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK4: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK4_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK4: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK4_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK4: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL4  ------------------------------------------
-#define SCT_EVCTRL4_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL4: MATCHSEL Position      */
-#define SCT_EVCTRL4_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos)                      /*!< SCT EVCTRL4: MATCHSEL Mask          */
-#define SCT_EVCTRL4_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL4: HEVENT Position        */
-#define SCT_EVCTRL4_HEVENT_Msk                                (0x01UL << SCT_EVCTRL4_HEVENT_Pos)                        /*!< SCT EVCTRL4: HEVENT Mask            */
-#define SCT_EVCTRL4_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL4: OUTSEL Position        */
-#define SCT_EVCTRL4_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL4_OUTSEL_Pos)                        /*!< SCT EVCTRL4: OUTSEL Mask            */
-#define SCT_EVCTRL4_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL4: IOSEL Position         */
-#define SCT_EVCTRL4_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL4_IOSEL_Pos)                         /*!< SCT EVCTRL4: IOSEL Mask             */
-#define SCT_EVCTRL4_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL4: IOCOND Position        */
-#define SCT_EVCTRL4_IOCOND_Msk                                (0x03UL << SCT_EVCTRL4_IOCOND_Pos)                        /*!< SCT EVCTRL4: IOCOND Mask            */
-#define SCT_EVCTRL4_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL4: COMBMODE Position      */
-#define SCT_EVCTRL4_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL4_COMBMODE_Pos)                      /*!< SCT EVCTRL4: COMBMODE Mask          */
-#define SCT_EVCTRL4_STATELD_Pos                               14                                                        /*!< SCT EVCTRL4: STATELD Position       */
-#define SCT_EVCTRL4_STATELD_Msk                               (0x01UL << SCT_EVCTRL4_STATELD_Pos)                       /*!< SCT EVCTRL4: STATELD Mask           */
-#define SCT_EVCTRL4_STATEV_Pos                                15                                                        /*!< SCT EVCTRL4: STATEV Position        */
-#define SCT_EVCTRL4_STATEV_Msk                                (0x1fUL << SCT_EVCTRL4_STATEV_Pos)                        /*!< SCT EVCTRL4: STATEV Mask            */
-
-// -------------------------------------  SCT_EVSTATEMSK5  ----------------------------------------
-#define SCT_EVSTATEMSK5_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK5: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK5: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK5: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK5: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK5: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK5: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK5: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK5: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK5: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK5: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK5: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK5_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK5: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK5: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK5: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK5: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK5: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK5: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK5: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK5: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK5: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK5: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK5: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK5: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK5: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK5: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK5: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK5: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK5: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK5: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK5: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK5: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK5: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK5_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK5: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK5_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK5: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL5  ------------------------------------------
-#define SCT_EVCTRL5_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL5: MATCHSEL Position      */
-#define SCT_EVCTRL5_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos)                      /*!< SCT EVCTRL5: MATCHSEL Mask          */
-#define SCT_EVCTRL5_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL5: HEVENT Position        */
-#define SCT_EVCTRL5_HEVENT_Msk                                (0x01UL << SCT_EVCTRL5_HEVENT_Pos)                        /*!< SCT EVCTRL5: HEVENT Mask            */
-#define SCT_EVCTRL5_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL5: OUTSEL Position        */
-#define SCT_EVCTRL5_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL5_OUTSEL_Pos)                        /*!< SCT EVCTRL5: OUTSEL Mask            */
-#define SCT_EVCTRL5_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL5: IOSEL Position         */
-#define SCT_EVCTRL5_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL5_IOSEL_Pos)                         /*!< SCT EVCTRL5: IOSEL Mask             */
-#define SCT_EVCTRL5_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL5: IOCOND Position        */
-#define SCT_EVCTRL5_IOCOND_Msk                                (0x03UL << SCT_EVCTRL5_IOCOND_Pos)                        /*!< SCT EVCTRL5: IOCOND Mask            */
-#define SCT_EVCTRL5_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL5: COMBMODE Position      */
-#define SCT_EVCTRL5_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL5_COMBMODE_Pos)                      /*!< SCT EVCTRL5: COMBMODE Mask          */
-#define SCT_EVCTRL5_STATELD_Pos                               14                                                        /*!< SCT EVCTRL5: STATELD Position       */
-#define SCT_EVCTRL5_STATELD_Msk                               (0x01UL << SCT_EVCTRL5_STATELD_Pos)                       /*!< SCT EVCTRL5: STATELD Mask           */
-#define SCT_EVCTRL5_STATEV_Pos                                15                                                        /*!< SCT EVCTRL5: STATEV Position        */
-#define SCT_EVCTRL5_STATEV_Msk                                (0x1fUL << SCT_EVCTRL5_STATEV_Pos)                        /*!< SCT EVCTRL5: STATEV Mask            */
-
-// -------------------------------------  SCT_EVSTATEMSK6  ----------------------------------------
-#define SCT_EVSTATEMSK6_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK6: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK6: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK6: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK6: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK6: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK6: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK6: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK6: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK6: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK6: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK6: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK6_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK6: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK6: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK6: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK6: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK6: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK6: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK6: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK6: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK6: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK6: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK6: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK6: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK6: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK6: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK6: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK6: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK6: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK6: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK6: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK6: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK6: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK6_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK6: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK6_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK6: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL6  ------------------------------------------
-#define SCT_EVCTRL6_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL6: MATCHSEL Position      */
-#define SCT_EVCTRL6_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos)                      /*!< SCT EVCTRL6: MATCHSEL Mask          */
-#define SCT_EVCTRL6_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL6: HEVENT Position        */
-#define SCT_EVCTRL6_HEVENT_Msk                                (0x01UL << SCT_EVCTRL6_HEVENT_Pos)                        /*!< SCT EVCTRL6: HEVENT Mask            */
-#define SCT_EVCTRL6_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL6: OUTSEL Position        */
-#define SCT_EVCTRL6_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL6_OUTSEL_Pos)                        /*!< SCT EVCTRL6: OUTSEL Mask            */
-#define SCT_EVCTRL6_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL6: IOSEL Position         */
-#define SCT_EVCTRL6_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL6_IOSEL_Pos)                         /*!< SCT EVCTRL6: IOSEL Mask             */
-#define SCT_EVCTRL6_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL6: IOCOND Position        */
-#define SCT_EVCTRL6_IOCOND_Msk                                (0x03UL << SCT_EVCTRL6_IOCOND_Pos)                        /*!< SCT EVCTRL6: IOCOND Mask            */
-#define SCT_EVCTRL6_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL6: COMBMODE Position      */
-#define SCT_EVCTRL6_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL6_COMBMODE_Pos)                      /*!< SCT EVCTRL6: COMBMODE Mask          */
-#define SCT_EVCTRL6_STATELD_Pos                               14                                                        /*!< SCT EVCTRL6: STATELD Position       */
-#define SCT_EVCTRL6_STATELD_Msk                               (0x01UL << SCT_EVCTRL6_STATELD_Pos)                       /*!< SCT EVCTRL6: STATELD Mask           */
-#define SCT_EVCTRL6_STATEV_Pos                                15                                                        /*!< SCT EVCTRL6: STATEV Position        */
-#define SCT_EVCTRL6_STATEV_Msk                                (0x1fUL << SCT_EVCTRL6_STATEV_Pos)                        /*!< SCT EVCTRL6: STATEV Mask            */
-
-// -------------------------------------  SCT_EVSTATEMSK7  ----------------------------------------
-#define SCT_EVSTATEMSK7_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK7: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK7: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK7: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK7: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK7: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK7: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK7: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK7: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK7: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK7: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK7: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK7_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK7: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK7: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK7: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK7: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK7: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK7: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK7: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK7: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK7: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK7: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK7: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK7: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK7: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK7: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK7: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK7: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK7: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK7: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK7: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK7: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK7: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK7_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK7: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK7_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK7: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL7  ------------------------------------------
-#define SCT_EVCTRL7_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL7: MATCHSEL Position      */
-#define SCT_EVCTRL7_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos)                      /*!< SCT EVCTRL7: MATCHSEL Mask          */
-#define SCT_EVCTRL7_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL7: HEVENT Position        */
-#define SCT_EVCTRL7_HEVENT_Msk                                (0x01UL << SCT_EVCTRL7_HEVENT_Pos)                        /*!< SCT EVCTRL7: HEVENT Mask            */
-#define SCT_EVCTRL7_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL7: OUTSEL Position        */
-#define SCT_EVCTRL7_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL7_OUTSEL_Pos)                        /*!< SCT EVCTRL7: OUTSEL Mask            */
-#define SCT_EVCTRL7_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL7: IOSEL Position         */
-#define SCT_EVCTRL7_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL7_IOSEL_Pos)                         /*!< SCT EVCTRL7: IOSEL Mask             */
-#define SCT_EVCTRL7_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL7: IOCOND Position        */
-#define SCT_EVCTRL7_IOCOND_Msk                                (0x03UL << SCT_EVCTRL7_IOCOND_Pos)                        /*!< SCT EVCTRL7: IOCOND Mask            */
-#define SCT_EVCTRL7_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL7: COMBMODE Position      */
-#define SCT_EVCTRL7_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL7_COMBMODE_Pos)                      /*!< SCT EVCTRL7: COMBMODE Mask          */
-#define SCT_EVCTRL7_STATELD_Pos                               14                                                        /*!< SCT EVCTRL7: STATELD Position       */
-#define SCT_EVCTRL7_STATELD_Msk                               (0x01UL << SCT_EVCTRL7_STATELD_Pos)                       /*!< SCT EVCTRL7: STATELD Mask           */
-#define SCT_EVCTRL7_STATEV_Pos                                15                                                        /*!< SCT EVCTRL7: STATEV Position        */
-#define SCT_EVCTRL7_STATEV_Msk                                (0x1fUL << SCT_EVCTRL7_STATEV_Pos)                        /*!< SCT EVCTRL7: STATEV Mask            */
-
-// -------------------------------------  SCT_EVSTATEMSK8  ----------------------------------------
-#define SCT_EVSTATEMSK8_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK8: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK8: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK8: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK8: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK8: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK8: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK8: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK8: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK8: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK8: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK8: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK8_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK8: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK8: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK8: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK8: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK8: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK8: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK8: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK8: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK8: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK8: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK8: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK8: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK8: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK8: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK8: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK8: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK8: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK8: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK8: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK8: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK8: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK8_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK8: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK8_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK8: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL8  ------------------------------------------
-#define SCT_EVCTRL8_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL8: MATCHSEL Position      */
-#define SCT_EVCTRL8_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos)                      /*!< SCT EVCTRL8: MATCHSEL Mask          */
-#define SCT_EVCTRL8_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL8: HEVENT Position        */
-#define SCT_EVCTRL8_HEVENT_Msk                                (0x01UL << SCT_EVCTRL8_HEVENT_Pos)                        /*!< SCT EVCTRL8: HEVENT Mask            */
-#define SCT_EVCTRL8_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL8: OUTSEL Position        */
-#define SCT_EVCTRL8_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL8_OUTSEL_Pos)                        /*!< SCT EVCTRL8: OUTSEL Mask            */
-#define SCT_EVCTRL8_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL8: IOSEL Position         */
-#define SCT_EVCTRL8_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL8_IOSEL_Pos)                         /*!< SCT EVCTRL8: IOSEL Mask             */
-#define SCT_EVCTRL8_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL8: IOCOND Position        */
-#define SCT_EVCTRL8_IOCOND_Msk                                (0x03UL << SCT_EVCTRL8_IOCOND_Pos)                        /*!< SCT EVCTRL8: IOCOND Mask            */
-#define SCT_EVCTRL8_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL8: COMBMODE Position      */
-#define SCT_EVCTRL8_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL8_COMBMODE_Pos)                      /*!< SCT EVCTRL8: COMBMODE Mask          */
-#define SCT_EVCTRL8_STATELD_Pos                               14                                                        /*!< SCT EVCTRL8: STATELD Position       */
-#define SCT_EVCTRL8_STATELD_Msk                               (0x01UL << SCT_EVCTRL8_STATELD_Pos)                       /*!< SCT EVCTRL8: STATELD Mask           */
-#define SCT_EVCTRL8_STATEV_Pos                                15                                                        /*!< SCT EVCTRL8: STATEV Position        */
-#define SCT_EVCTRL8_STATEV_Msk                                (0x1fUL << SCT_EVCTRL8_STATEV_Pos)                        /*!< SCT EVCTRL8: STATEV Mask            */
-
-// -------------------------------------  SCT_EVSTATEMSK9  ----------------------------------------
-#define SCT_EVSTATEMSK9_STATEMSKn0_Pos                        0                                                         /*!< SCT EVSTATEMSK9: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn0 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn1_Pos                        1                                                         /*!< SCT EVSTATEMSK9: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn1 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn2_Pos                        2                                                         /*!< SCT EVSTATEMSK9: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn2 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn3_Pos                        3                                                         /*!< SCT EVSTATEMSK9: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn3 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn4_Pos                        4                                                         /*!< SCT EVSTATEMSK9: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn4 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn5_Pos                        5                                                         /*!< SCT EVSTATEMSK9: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn5 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn6_Pos                        6                                                         /*!< SCT EVSTATEMSK9: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn6 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn7_Pos                        7                                                         /*!< SCT EVSTATEMSK9: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn7 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn8_Pos                        8                                                         /*!< SCT EVSTATEMSK9: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn8 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn9_Pos                        9                                                         /*!< SCT EVSTATEMSK9: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos)                /*!< SCT EVSTATEMSK9: STATEMSKn9 Mask    */
-#define SCT_EVSTATEMSK9_STATEMSKn10_Pos                       10                                                        /*!< SCT EVSTATEMSK9: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn10 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn11_Pos                       11                                                        /*!< SCT EVSTATEMSK9: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn11 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn12_Pos                       12                                                        /*!< SCT EVSTATEMSK9: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn12 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn13_Pos                       13                                                        /*!< SCT EVSTATEMSK9: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn13 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn14_Pos                       14                                                        /*!< SCT EVSTATEMSK9: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn14 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn15_Pos                       15                                                        /*!< SCT EVSTATEMSK9: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn15 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn16_Pos                       16                                                        /*!< SCT EVSTATEMSK9: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn16 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn17_Pos                       17                                                        /*!< SCT EVSTATEMSK9: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn17 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn18_Pos                       18                                                        /*!< SCT EVSTATEMSK9: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn18 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn19_Pos                       19                                                        /*!< SCT EVSTATEMSK9: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn19 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn20_Pos                       20                                                        /*!< SCT EVSTATEMSK9: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn20 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn21_Pos                       21                                                        /*!< SCT EVSTATEMSK9: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn21 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn22_Pos                       22                                                        /*!< SCT EVSTATEMSK9: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn22 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn23_Pos                       23                                                        /*!< SCT EVSTATEMSK9: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn23 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn24_Pos                       24                                                        /*!< SCT EVSTATEMSK9: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn24 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn25_Pos                       25                                                        /*!< SCT EVSTATEMSK9: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn25 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn26_Pos                       26                                                        /*!< SCT EVSTATEMSK9: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn26 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn27_Pos                       27                                                        /*!< SCT EVSTATEMSK9: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn27 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn28_Pos                       28                                                        /*!< SCT EVSTATEMSK9: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn28 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn29_Pos                       29                                                        /*!< SCT EVSTATEMSK9: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn29 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn30_Pos                       30                                                        /*!< SCT EVSTATEMSK9: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn30 Mask   */
-#define SCT_EVSTATEMSK9_STATEMSKn31_Pos                       31                                                        /*!< SCT EVSTATEMSK9: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK9_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos)               /*!< SCT EVSTATEMSK9: STATEMSKn31 Mask   */
-
-// ---------------------------------------  SCT_EVCTRL9  ------------------------------------------
-#define SCT_EVCTRL9_MATCHSEL_Pos                              0                                                         /*!< SCT EVCTRL9: MATCHSEL Position      */
-#define SCT_EVCTRL9_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos)                      /*!< SCT EVCTRL9: MATCHSEL Mask          */
-#define SCT_EVCTRL9_HEVENT_Pos                                4                                                         /*!< SCT EVCTRL9: HEVENT Position        */
-#define SCT_EVCTRL9_HEVENT_Msk                                (0x01UL << SCT_EVCTRL9_HEVENT_Pos)                        /*!< SCT EVCTRL9: HEVENT Mask            */
-#define SCT_EVCTRL9_OUTSEL_Pos                                5                                                         /*!< SCT EVCTRL9: OUTSEL Position        */
-#define SCT_EVCTRL9_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL9_OUTSEL_Pos)                        /*!< SCT EVCTRL9: OUTSEL Mask            */
-#define SCT_EVCTRL9_IOSEL_Pos                                 6                                                         /*!< SCT EVCTRL9: IOSEL Position         */
-#define SCT_EVCTRL9_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL9_IOSEL_Pos)                         /*!< SCT EVCTRL9: IOSEL Mask             */
-#define SCT_EVCTRL9_IOCOND_Pos                                10                                                        /*!< SCT EVCTRL9: IOCOND Position        */
-#define SCT_EVCTRL9_IOCOND_Msk                                (0x03UL << SCT_EVCTRL9_IOCOND_Pos)                        /*!< SCT EVCTRL9: IOCOND Mask            */
-#define SCT_EVCTRL9_COMBMODE_Pos                              12                                                        /*!< SCT EVCTRL9: COMBMODE Position      */
-#define SCT_EVCTRL9_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL9_COMBMODE_Pos)                      /*!< SCT EVCTRL9: COMBMODE Mask          */
-#define SCT_EVCTRL9_STATELD_Pos                               14                                                        /*!< SCT EVCTRL9: STATELD Position       */
-#define SCT_EVCTRL9_STATELD_Msk                               (0x01UL << SCT_EVCTRL9_STATELD_Pos)                       /*!< SCT EVCTRL9: STATELD Mask           */
-#define SCT_EVCTRL9_STATEV_Pos                                15                                                        /*!< SCT EVCTRL9: STATEV Position        */
-#define SCT_EVCTRL9_STATEV_Msk                                (0x1fUL << SCT_EVCTRL9_STATEV_Pos)                        /*!< SCT EVCTRL9: STATEV Mask            */
-
-// ------------------------------------  SCT_EVSTATEMSK10  ----------------------------------------
-#define SCT_EVSTATEMSK10_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK10: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn0 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK10: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn1 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK10: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn2 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK10: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn3 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK10: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn4 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK10: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn5 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK10: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn6 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK10: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn7 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK10: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn8 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK10: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK10: STATEMSKn9 Mask   */
-#define SCT_EVSTATEMSK10_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK10: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn10 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK10: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn11 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK10: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn12 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK10: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn13 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK10: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn14 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK10: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn15 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK10: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn16 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK10: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn17 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK10: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn18 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK10: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn19 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK10: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn20 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK10: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn21 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK10: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn22 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK10: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn23 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK10: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn24 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK10: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn25 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK10: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn26 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK10: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn27 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK10: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn28 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK10: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn29 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK10: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn30 Mask  */
-#define SCT_EVSTATEMSK10_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK10: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK10_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK10: STATEMSKn31 Mask  */
-
-// --------------------------------------  SCT_EVCTRL10  ------------------------------------------
-#define SCT_EVCTRL10_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL10: MATCHSEL Position     */
-#define SCT_EVCTRL10_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos)                     /*!< SCT EVCTRL10: MATCHSEL Mask         */
-#define SCT_EVCTRL10_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL10: HEVENT Position       */
-#define SCT_EVCTRL10_HEVENT_Msk                               (0x01UL << SCT_EVCTRL10_HEVENT_Pos)                       /*!< SCT EVCTRL10: HEVENT Mask           */
-#define SCT_EVCTRL10_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL10: OUTSEL Position       */
-#define SCT_EVCTRL10_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL10_OUTSEL_Pos)                       /*!< SCT EVCTRL10: OUTSEL Mask           */
-#define SCT_EVCTRL10_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL10: IOSEL Position        */
-#define SCT_EVCTRL10_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL10_IOSEL_Pos)                        /*!< SCT EVCTRL10: IOSEL Mask            */
-#define SCT_EVCTRL10_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL10: IOCOND Position       */
-#define SCT_EVCTRL10_IOCOND_Msk                               (0x03UL << SCT_EVCTRL10_IOCOND_Pos)                       /*!< SCT EVCTRL10: IOCOND Mask           */
-#define SCT_EVCTRL10_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL10: COMBMODE Position     */
-#define SCT_EVCTRL10_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL10_COMBMODE_Pos)                     /*!< SCT EVCTRL10: COMBMODE Mask         */
-#define SCT_EVCTRL10_STATELD_Pos                              14                                                        /*!< SCT EVCTRL10: STATELD Position      */
-#define SCT_EVCTRL10_STATELD_Msk                              (0x01UL << SCT_EVCTRL10_STATELD_Pos)                      /*!< SCT EVCTRL10: STATELD Mask          */
-#define SCT_EVCTRL10_STATEV_Pos                               15                                                        /*!< SCT EVCTRL10: STATEV Position       */
-#define SCT_EVCTRL10_STATEV_Msk                               (0x1fUL << SCT_EVCTRL10_STATEV_Pos)                       /*!< SCT EVCTRL10: STATEV Mask           */
-
-// ------------------------------------  SCT_EVSTATEMSK11  ----------------------------------------
-#define SCT_EVSTATEMSK11_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK11: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn0 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK11: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn1 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK11: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn2 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK11: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn3 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK11: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn4 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK11: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn5 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK11: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn6 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK11: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn7 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK11: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn8 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK11: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK11: STATEMSKn9 Mask   */
-#define SCT_EVSTATEMSK11_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK11: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn10 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK11: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn11 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK11: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn12 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK11: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn13 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK11: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn14 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK11: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn15 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK11: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn16 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK11: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn17 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK11: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn18 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK11: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn19 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK11: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn20 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK11: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn21 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK11: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn22 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK11: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn23 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK11: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn24 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK11: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn25 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK11: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn26 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK11: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn27 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK11: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn28 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK11: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn29 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK11: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn30 Mask  */
-#define SCT_EVSTATEMSK11_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK11: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK11_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK11: STATEMSKn31 Mask  */
-
-// --------------------------------------  SCT_EVCTRL11  ------------------------------------------
-#define SCT_EVCTRL11_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL11: MATCHSEL Position     */
-#define SCT_EVCTRL11_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos)                     /*!< SCT EVCTRL11: MATCHSEL Mask         */
-#define SCT_EVCTRL11_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL11: HEVENT Position       */
-#define SCT_EVCTRL11_HEVENT_Msk                               (0x01UL << SCT_EVCTRL11_HEVENT_Pos)                       /*!< SCT EVCTRL11: HEVENT Mask           */
-#define SCT_EVCTRL11_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL11: OUTSEL Position       */
-#define SCT_EVCTRL11_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL11_OUTSEL_Pos)                       /*!< SCT EVCTRL11: OUTSEL Mask           */
-#define SCT_EVCTRL11_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL11: IOSEL Position        */
-#define SCT_EVCTRL11_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL11_IOSEL_Pos)                        /*!< SCT EVCTRL11: IOSEL Mask            */
-#define SCT_EVCTRL11_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL11: IOCOND Position       */
-#define SCT_EVCTRL11_IOCOND_Msk                               (0x03UL << SCT_EVCTRL11_IOCOND_Pos)                       /*!< SCT EVCTRL11: IOCOND Mask           */
-#define SCT_EVCTRL11_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL11: COMBMODE Position     */
-#define SCT_EVCTRL11_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL11_COMBMODE_Pos)                     /*!< SCT EVCTRL11: COMBMODE Mask         */
-#define SCT_EVCTRL11_STATELD_Pos                              14                                                        /*!< SCT EVCTRL11: STATELD Position      */
-#define SCT_EVCTRL11_STATELD_Msk                              (0x01UL << SCT_EVCTRL11_STATELD_Pos)                      /*!< SCT EVCTRL11: STATELD Mask          */
-#define SCT_EVCTRL11_STATEV_Pos                               15                                                        /*!< SCT EVCTRL11: STATEV Position       */
-#define SCT_EVCTRL11_STATEV_Msk                               (0x1fUL << SCT_EVCTRL11_STATEV_Pos)                       /*!< SCT EVCTRL11: STATEV Mask           */
-
-// ------------------------------------  SCT_EVSTATEMSK12  ----------------------------------------
-#define SCT_EVSTATEMSK12_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK12: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn0 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK12: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn1 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK12: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn2 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK12: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn3 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK12: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn4 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK12: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn5 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK12: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn6 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK12: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn7 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK12: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn8 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK12: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK12: STATEMSKn9 Mask   */
-#define SCT_EVSTATEMSK12_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK12: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn10 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK12: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn11 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK12: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn12 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK12: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn13 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK12: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn14 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK12: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn15 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK12: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn16 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK12: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn17 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK12: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn18 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK12: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn19 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK12: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn20 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK12: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn21 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK12: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn22 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK12: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn23 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK12: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn24 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK12: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn25 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK12: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn26 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK12: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn27 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK12: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn28 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK12: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn29 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK12: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn30 Mask  */
-#define SCT_EVSTATEMSK12_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK12: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK12_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK12: STATEMSKn31 Mask  */
-
-// --------------------------------------  SCT_EVCTRL12  ------------------------------------------
-#define SCT_EVCTRL12_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL12: MATCHSEL Position     */
-#define SCT_EVCTRL12_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos)                     /*!< SCT EVCTRL12: MATCHSEL Mask         */
-#define SCT_EVCTRL12_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL12: HEVENT Position       */
-#define SCT_EVCTRL12_HEVENT_Msk                               (0x01UL << SCT_EVCTRL12_HEVENT_Pos)                       /*!< SCT EVCTRL12: HEVENT Mask           */
-#define SCT_EVCTRL12_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL12: OUTSEL Position       */
-#define SCT_EVCTRL12_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL12_OUTSEL_Pos)                       /*!< SCT EVCTRL12: OUTSEL Mask           */
-#define SCT_EVCTRL12_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL12: IOSEL Position        */
-#define SCT_EVCTRL12_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL12_IOSEL_Pos)                        /*!< SCT EVCTRL12: IOSEL Mask            */
-#define SCT_EVCTRL12_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL12: IOCOND Position       */
-#define SCT_EVCTRL12_IOCOND_Msk                               (0x03UL << SCT_EVCTRL12_IOCOND_Pos)                       /*!< SCT EVCTRL12: IOCOND Mask           */
-#define SCT_EVCTRL12_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL12: COMBMODE Position     */
-#define SCT_EVCTRL12_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL12_COMBMODE_Pos)                     /*!< SCT EVCTRL12: COMBMODE Mask         */
-#define SCT_EVCTRL12_STATELD_Pos                              14                                                        /*!< SCT EVCTRL12: STATELD Position      */
-#define SCT_EVCTRL12_STATELD_Msk                              (0x01UL << SCT_EVCTRL12_STATELD_Pos)                      /*!< SCT EVCTRL12: STATELD Mask          */
-#define SCT_EVCTRL12_STATEV_Pos                               15                                                        /*!< SCT EVCTRL12: STATEV Position       */
-#define SCT_EVCTRL12_STATEV_Msk                               (0x1fUL << SCT_EVCTRL12_STATEV_Pos)                       /*!< SCT EVCTRL12: STATEV Mask           */
-
-// ------------------------------------  SCT_EVSTATEMSK13  ----------------------------------------
-#define SCT_EVSTATEMSK13_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK13: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn0 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK13: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn1 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK13: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn2 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK13: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn3 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK13: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn4 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK13: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn5 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK13: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn6 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK13: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn7 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK13: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn8 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK13: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK13: STATEMSKn9 Mask   */
-#define SCT_EVSTATEMSK13_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK13: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn10 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK13: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn11 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK13: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn12 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK13: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn13 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK13: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn14 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK13: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn15 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK13: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn16 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK13: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn17 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK13: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn18 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK13: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn19 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK13: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn20 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK13: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn21 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK13: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn22 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK13: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn23 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK13: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn24 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK13: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn25 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK13: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn26 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK13: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn27 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK13: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn28 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK13: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn29 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK13: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn30 Mask  */
-#define SCT_EVSTATEMSK13_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK13: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK13_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK13: STATEMSKn31 Mask  */
-
-// --------------------------------------  SCT_EVCTRL13  ------------------------------------------
-#define SCT_EVCTRL13_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL13: MATCHSEL Position     */
-#define SCT_EVCTRL13_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos)                     /*!< SCT EVCTRL13: MATCHSEL Mask         */
-#define SCT_EVCTRL13_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL13: HEVENT Position       */
-#define SCT_EVCTRL13_HEVENT_Msk                               (0x01UL << SCT_EVCTRL13_HEVENT_Pos)                       /*!< SCT EVCTRL13: HEVENT Mask           */
-#define SCT_EVCTRL13_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL13: OUTSEL Position       */
-#define SCT_EVCTRL13_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL13_OUTSEL_Pos)                       /*!< SCT EVCTRL13: OUTSEL Mask           */
-#define SCT_EVCTRL13_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL13: IOSEL Position        */
-#define SCT_EVCTRL13_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL13_IOSEL_Pos)                        /*!< SCT EVCTRL13: IOSEL Mask            */
-#define SCT_EVCTRL13_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL13: IOCOND Position       */
-#define SCT_EVCTRL13_IOCOND_Msk                               (0x03UL << SCT_EVCTRL13_IOCOND_Pos)                       /*!< SCT EVCTRL13: IOCOND Mask           */
-#define SCT_EVCTRL13_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL13: COMBMODE Position     */
-#define SCT_EVCTRL13_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL13_COMBMODE_Pos)                     /*!< SCT EVCTRL13: COMBMODE Mask         */
-#define SCT_EVCTRL13_STATELD_Pos                              14                                                        /*!< SCT EVCTRL13: STATELD Position      */
-#define SCT_EVCTRL13_STATELD_Msk                              (0x01UL << SCT_EVCTRL13_STATELD_Pos)                      /*!< SCT EVCTRL13: STATELD Mask          */
-#define SCT_EVCTRL13_STATEV_Pos                               15                                                        /*!< SCT EVCTRL13: STATEV Position       */
-#define SCT_EVCTRL13_STATEV_Msk                               (0x1fUL << SCT_EVCTRL13_STATEV_Pos)                       /*!< SCT EVCTRL13: STATEV Mask           */
-
-// ------------------------------------  SCT_EVSTATEMSK14  ----------------------------------------
-#define SCT_EVSTATEMSK14_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK14: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn0 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK14: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn1 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK14: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn2 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK14: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn3 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK14: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn4 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK14: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn5 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK14: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn6 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK14: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn7 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK14: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn8 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK14: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK14: STATEMSKn9 Mask   */
-#define SCT_EVSTATEMSK14_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK14: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn10 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK14: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn11 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK14: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn12 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK14: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn13 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK14: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn14 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK14: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn15 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK14: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn16 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK14: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn17 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK14: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn18 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK14: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn19 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK14: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn20 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK14: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn21 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK14: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn22 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK14: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn23 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK14: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn24 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK14: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn25 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK14: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn26 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK14: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn27 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK14: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn28 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK14: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn29 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK14: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn30 Mask  */
-#define SCT_EVSTATEMSK14_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK14: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK14_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK14: STATEMSKn31 Mask  */
-
-// --------------------------------------  SCT_EVCTRL14  ------------------------------------------
-#define SCT_EVCTRL14_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL14: MATCHSEL Position     */
-#define SCT_EVCTRL14_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos)                     /*!< SCT EVCTRL14: MATCHSEL Mask         */
-#define SCT_EVCTRL14_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL14: HEVENT Position       */
-#define SCT_EVCTRL14_HEVENT_Msk                               (0x01UL << SCT_EVCTRL14_HEVENT_Pos)                       /*!< SCT EVCTRL14: HEVENT Mask           */
-#define SCT_EVCTRL14_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL14: OUTSEL Position       */
-#define SCT_EVCTRL14_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL14_OUTSEL_Pos)                       /*!< SCT EVCTRL14: OUTSEL Mask           */
-#define SCT_EVCTRL14_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL14: IOSEL Position        */
-#define SCT_EVCTRL14_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL14_IOSEL_Pos)                        /*!< SCT EVCTRL14: IOSEL Mask            */
-#define SCT_EVCTRL14_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL14: IOCOND Position       */
-#define SCT_EVCTRL14_IOCOND_Msk                               (0x03UL << SCT_EVCTRL14_IOCOND_Pos)                       /*!< SCT EVCTRL14: IOCOND Mask           */
-#define SCT_EVCTRL14_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL14: COMBMODE Position     */
-#define SCT_EVCTRL14_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL14_COMBMODE_Pos)                     /*!< SCT EVCTRL14: COMBMODE Mask         */
-#define SCT_EVCTRL14_STATELD_Pos                              14                                                        /*!< SCT EVCTRL14: STATELD Position      */
-#define SCT_EVCTRL14_STATELD_Msk                              (0x01UL << SCT_EVCTRL14_STATELD_Pos)                      /*!< SCT EVCTRL14: STATELD Mask          */
-#define SCT_EVCTRL14_STATEV_Pos                               15                                                        /*!< SCT EVCTRL14: STATEV Position       */
-#define SCT_EVCTRL14_STATEV_Msk                               (0x1fUL << SCT_EVCTRL14_STATEV_Pos)                       /*!< SCT EVCTRL14: STATEV Mask           */
-
-// ------------------------------------  SCT_EVSTATEMSK15  ----------------------------------------
-#define SCT_EVSTATEMSK15_STATEMSKn0_Pos                       0                                                         /*!< SCT EVSTATEMSK15: STATEMSKn0 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn0 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn1_Pos                       1                                                         /*!< SCT EVSTATEMSK15: STATEMSKn1 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn1 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn2_Pos                       2                                                         /*!< SCT EVSTATEMSK15: STATEMSKn2 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn2 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn3_Pos                       3                                                         /*!< SCT EVSTATEMSK15: STATEMSKn3 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn3 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn4_Pos                       4                                                         /*!< SCT EVSTATEMSK15: STATEMSKn4 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn4 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn5_Pos                       5                                                         /*!< SCT EVSTATEMSK15: STATEMSKn5 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn5 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn6_Pos                       6                                                         /*!< SCT EVSTATEMSK15: STATEMSKn6 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn6 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn7_Pos                       7                                                         /*!< SCT EVSTATEMSK15: STATEMSKn7 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn7 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn8_Pos                       8                                                         /*!< SCT EVSTATEMSK15: STATEMSKn8 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn8 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn9_Pos                       9                                                         /*!< SCT EVSTATEMSK15: STATEMSKn9 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos)               /*!< SCT EVSTATEMSK15: STATEMSKn9 Mask   */
-#define SCT_EVSTATEMSK15_STATEMSKn10_Pos                      10                                                        /*!< SCT EVSTATEMSK15: STATEMSKn10 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn10 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn11_Pos                      11                                                        /*!< SCT EVSTATEMSK15: STATEMSKn11 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn11 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn12_Pos                      12                                                        /*!< SCT EVSTATEMSK15: STATEMSKn12 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn12 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn13_Pos                      13                                                        /*!< SCT EVSTATEMSK15: STATEMSKn13 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn13 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn14_Pos                      14                                                        /*!< SCT EVSTATEMSK15: STATEMSKn14 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn14 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn15_Pos                      15                                                        /*!< SCT EVSTATEMSK15: STATEMSKn15 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn15 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn16_Pos                      16                                                        /*!< SCT EVSTATEMSK15: STATEMSKn16 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn16 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn17_Pos                      17                                                        /*!< SCT EVSTATEMSK15: STATEMSKn17 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn17 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn18_Pos                      18                                                        /*!< SCT EVSTATEMSK15: STATEMSKn18 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn18 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn19_Pos                      19                                                        /*!< SCT EVSTATEMSK15: STATEMSKn19 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn19 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn20_Pos                      20                                                        /*!< SCT EVSTATEMSK15: STATEMSKn20 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn20 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn21_Pos                      21                                                        /*!< SCT EVSTATEMSK15: STATEMSKn21 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn21 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn22_Pos                      22                                                        /*!< SCT EVSTATEMSK15: STATEMSKn22 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn22 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn23_Pos                      23                                                        /*!< SCT EVSTATEMSK15: STATEMSKn23 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn23 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn24_Pos                      24                                                        /*!< SCT EVSTATEMSK15: STATEMSKn24 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn24 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn25_Pos                      25                                                        /*!< SCT EVSTATEMSK15: STATEMSKn25 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn25 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn26_Pos                      26                                                        /*!< SCT EVSTATEMSK15: STATEMSKn26 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn26 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn27_Pos                      27                                                        /*!< SCT EVSTATEMSK15: STATEMSKn27 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn27 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn28_Pos                      28                                                        /*!< SCT EVSTATEMSK15: STATEMSKn28 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn28 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn29_Pos                      29                                                        /*!< SCT EVSTATEMSK15: STATEMSKn29 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn29 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn30_Pos                      30                                                        /*!< SCT EVSTATEMSK15: STATEMSKn30 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn30 Mask  */
-#define SCT_EVSTATEMSK15_STATEMSKn31_Pos                      31                                                        /*!< SCT EVSTATEMSK15: STATEMSKn31 Position */
-#define SCT_EVSTATEMSK15_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos)              /*!< SCT EVSTATEMSK15: STATEMSKn31 Mask  */
-
-// --------------------------------------  SCT_EVCTRL15  ------------------------------------------
-#define SCT_EVCTRL15_MATCHSEL_Pos                             0                                                         /*!< SCT EVCTRL15: MATCHSEL Position     */
-#define SCT_EVCTRL15_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos)                     /*!< SCT EVCTRL15: MATCHSEL Mask         */
-#define SCT_EVCTRL15_HEVENT_Pos                               4                                                         /*!< SCT EVCTRL15: HEVENT Position       */
-#define SCT_EVCTRL15_HEVENT_Msk                               (0x01UL << SCT_EVCTRL15_HEVENT_Pos)                       /*!< SCT EVCTRL15: HEVENT Mask           */
-#define SCT_EVCTRL15_OUTSEL_Pos                               5                                                         /*!< SCT EVCTRL15: OUTSEL Position       */
-#define SCT_EVCTRL15_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL15_OUTSEL_Pos)                       /*!< SCT EVCTRL15: OUTSEL Mask           */
-#define SCT_EVCTRL15_IOSEL_Pos                                6                                                         /*!< SCT EVCTRL15: IOSEL Position        */
-#define SCT_EVCTRL15_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL15_IOSEL_Pos)                        /*!< SCT EVCTRL15: IOSEL Mask            */
-#define SCT_EVCTRL15_IOCOND_Pos                               10                                                        /*!< SCT EVCTRL15: IOCOND Position       */
-#define SCT_EVCTRL15_IOCOND_Msk                               (0x03UL << SCT_EVCTRL15_IOCOND_Pos)                       /*!< SCT EVCTRL15: IOCOND Mask           */
-#define SCT_EVCTRL15_COMBMODE_Pos                             12                                                        /*!< SCT EVCTRL15: COMBMODE Position     */
-#define SCT_EVCTRL15_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL15_COMBMODE_Pos)                     /*!< SCT EVCTRL15: COMBMODE Mask         */
-#define SCT_EVCTRL15_STATELD_Pos                              14                                                        /*!< SCT EVCTRL15: STATELD Position      */
-#define SCT_EVCTRL15_STATELD_Msk                              (0x01UL << SCT_EVCTRL15_STATELD_Pos)                      /*!< SCT EVCTRL15: STATELD Mask          */
-#define SCT_EVCTRL15_STATEV_Pos                               15                                                        /*!< SCT EVCTRL15: STATEV Position       */
-#define SCT_EVCTRL15_STATEV_Msk                               (0x1fUL << SCT_EVCTRL15_STATEV_Pos)                       /*!< SCT EVCTRL15: STATEV Mask           */
-
-// -------------------------------------  SCT_OUTPUTSET0  -----------------------------------------
-#define SCT_OUTPUTSET0_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET0: SETn0 Position      */
-#define SCT_OUTPUTSET0_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn0_Pos)                      /*!< SCT OUTPUTSET0: SETn0 Mask          */
-#define SCT_OUTPUTSET0_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET0: SETn1 Position      */
-#define SCT_OUTPUTSET0_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn1_Pos)                      /*!< SCT OUTPUTSET0: SETn1 Mask          */
-#define SCT_OUTPUTSET0_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET0: SETn2 Position      */
-#define SCT_OUTPUTSET0_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn2_Pos)                      /*!< SCT OUTPUTSET0: SETn2 Mask          */
-#define SCT_OUTPUTSET0_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET0: SETn3 Position      */
-#define SCT_OUTPUTSET0_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn3_Pos)                      /*!< SCT OUTPUTSET0: SETn3 Mask          */
-#define SCT_OUTPUTSET0_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET0: SETn4 Position      */
-#define SCT_OUTPUTSET0_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn4_Pos)                      /*!< SCT OUTPUTSET0: SETn4 Mask          */
-#define SCT_OUTPUTSET0_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET0: SETn5 Position      */
-#define SCT_OUTPUTSET0_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn5_Pos)                      /*!< SCT OUTPUTSET0: SETn5 Mask          */
-#define SCT_OUTPUTSET0_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET0: SETn6 Position      */
-#define SCT_OUTPUTSET0_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn6_Pos)                      /*!< SCT OUTPUTSET0: SETn6 Mask          */
-#define SCT_OUTPUTSET0_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET0: SETn7 Position      */
-#define SCT_OUTPUTSET0_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn7_Pos)                      /*!< SCT OUTPUTSET0: SETn7 Mask          */
-#define SCT_OUTPUTSET0_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET0: SETn8 Position      */
-#define SCT_OUTPUTSET0_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn8_Pos)                      /*!< SCT OUTPUTSET0: SETn8 Mask          */
-#define SCT_OUTPUTSET0_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET0: SETn9 Position      */
-#define SCT_OUTPUTSET0_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn9_Pos)                      /*!< SCT OUTPUTSET0: SETn9 Mask          */
-#define SCT_OUTPUTSET0_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET0: SETn10 Position     */
-#define SCT_OUTPUTSET0_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn10_Pos)                     /*!< SCT OUTPUTSET0: SETn10 Mask         */
-#define SCT_OUTPUTSET0_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET0: SETn11 Position     */
-#define SCT_OUTPUTSET0_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn11_Pos)                     /*!< SCT OUTPUTSET0: SETn11 Mask         */
-#define SCT_OUTPUTSET0_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET0: SETn12 Position     */
-#define SCT_OUTPUTSET0_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn12_Pos)                     /*!< SCT OUTPUTSET0: SETn12 Mask         */
-#define SCT_OUTPUTSET0_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET0: SETn13 Position     */
-#define SCT_OUTPUTSET0_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn13_Pos)                     /*!< SCT OUTPUTSET0: SETn13 Mask         */
-#define SCT_OUTPUTSET0_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET0: SETn14 Position     */
-#define SCT_OUTPUTSET0_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn14_Pos)                     /*!< SCT OUTPUTSET0: SETn14 Mask         */
-#define SCT_OUTPUTSET0_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET0: SETn15 Position     */
-#define SCT_OUTPUTSET0_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn15_Pos)                     /*!< SCT OUTPUTSET0: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR0  -----------------------------------------
-#define SCT_OUTPUTCLR0_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR0: CLRn0 Position      */
-#define SCT_OUTPUTCLR0_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos)                      /*!< SCT OUTPUTCLR0: CLRn0 Mask          */
-#define SCT_OUTPUTCLR0_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR0: CLRn1 Position      */
-#define SCT_OUTPUTCLR0_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos)                      /*!< SCT OUTPUTCLR0: CLRn1 Mask          */
-#define SCT_OUTPUTCLR0_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR0: CLRn2 Position      */
-#define SCT_OUTPUTCLR0_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos)                      /*!< SCT OUTPUTCLR0: CLRn2 Mask          */
-#define SCT_OUTPUTCLR0_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR0: CLRn3 Position      */
-#define SCT_OUTPUTCLR0_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos)                      /*!< SCT OUTPUTCLR0: CLRn3 Mask          */
-#define SCT_OUTPUTCLR0_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR0: CLRn4 Position      */
-#define SCT_OUTPUTCLR0_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos)                      /*!< SCT OUTPUTCLR0: CLRn4 Mask          */
-#define SCT_OUTPUTCLR0_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR0: CLRn5 Position      */
-#define SCT_OUTPUTCLR0_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos)                      /*!< SCT OUTPUTCLR0: CLRn5 Mask          */
-#define SCT_OUTPUTCLR0_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR0: CLRn6 Position      */
-#define SCT_OUTPUTCLR0_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos)                      /*!< SCT OUTPUTCLR0: CLRn6 Mask          */
-#define SCT_OUTPUTCLR0_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR0: CLRn7 Position      */
-#define SCT_OUTPUTCLR0_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos)                      /*!< SCT OUTPUTCLR0: CLRn7 Mask          */
-#define SCT_OUTPUTCLR0_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR0: CLRn8 Position      */
-#define SCT_OUTPUTCLR0_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos)                      /*!< SCT OUTPUTCLR0: CLRn8 Mask          */
-#define SCT_OUTPUTCLR0_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR0: CLRn9 Position      */
-#define SCT_OUTPUTCLR0_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos)                      /*!< SCT OUTPUTCLR0: CLRn9 Mask          */
-#define SCT_OUTPUTCLR0_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR0: CLRn10 Position     */
-#define SCT_OUTPUTCLR0_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos)                     /*!< SCT OUTPUTCLR0: CLRn10 Mask         */
-#define SCT_OUTPUTCLR0_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR0: CLRn11 Position     */
-#define SCT_OUTPUTCLR0_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos)                     /*!< SCT OUTPUTCLR0: CLRn11 Mask         */
-#define SCT_OUTPUTCLR0_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR0: CLRn12 Position     */
-#define SCT_OUTPUTCLR0_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos)                     /*!< SCT OUTPUTCLR0: CLRn12 Mask         */
-#define SCT_OUTPUTCLR0_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR0: CLRn13 Position     */
-#define SCT_OUTPUTCLR0_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos)                     /*!< SCT OUTPUTCLR0: CLRn13 Mask         */
-#define SCT_OUTPUTCLR0_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR0: CLRn14 Position     */
-#define SCT_OUTPUTCLR0_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos)                     /*!< SCT OUTPUTCLR0: CLRn14 Mask         */
-#define SCT_OUTPUTCLR0_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR0: CLRn15 Position     */
-#define SCT_OUTPUTCLR0_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos)                     /*!< SCT OUTPUTCLR0: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET1  -----------------------------------------
-#define SCT_OUTPUTSET1_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET1: SETn0 Position      */
-#define SCT_OUTPUTSET1_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn0_Pos)                      /*!< SCT OUTPUTSET1: SETn0 Mask          */
-#define SCT_OUTPUTSET1_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET1: SETn1 Position      */
-#define SCT_OUTPUTSET1_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn1_Pos)                      /*!< SCT OUTPUTSET1: SETn1 Mask          */
-#define SCT_OUTPUTSET1_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET1: SETn2 Position      */
-#define SCT_OUTPUTSET1_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn2_Pos)                      /*!< SCT OUTPUTSET1: SETn2 Mask          */
-#define SCT_OUTPUTSET1_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET1: SETn3 Position      */
-#define SCT_OUTPUTSET1_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn3_Pos)                      /*!< SCT OUTPUTSET1: SETn3 Mask          */
-#define SCT_OUTPUTSET1_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET1: SETn4 Position      */
-#define SCT_OUTPUTSET1_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn4_Pos)                      /*!< SCT OUTPUTSET1: SETn4 Mask          */
-#define SCT_OUTPUTSET1_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET1: SETn5 Position      */
-#define SCT_OUTPUTSET1_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn5_Pos)                      /*!< SCT OUTPUTSET1: SETn5 Mask          */
-#define SCT_OUTPUTSET1_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET1: SETn6 Position      */
-#define SCT_OUTPUTSET1_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn6_Pos)                      /*!< SCT OUTPUTSET1: SETn6 Mask          */
-#define SCT_OUTPUTSET1_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET1: SETn7 Position      */
-#define SCT_OUTPUTSET1_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn7_Pos)                      /*!< SCT OUTPUTSET1: SETn7 Mask          */
-#define SCT_OUTPUTSET1_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET1: SETn8 Position      */
-#define SCT_OUTPUTSET1_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn8_Pos)                      /*!< SCT OUTPUTSET1: SETn8 Mask          */
-#define SCT_OUTPUTSET1_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET1: SETn9 Position      */
-#define SCT_OUTPUTSET1_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn9_Pos)                      /*!< SCT OUTPUTSET1: SETn9 Mask          */
-#define SCT_OUTPUTSET1_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET1: SETn10 Position     */
-#define SCT_OUTPUTSET1_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn10_Pos)                     /*!< SCT OUTPUTSET1: SETn10 Mask         */
-#define SCT_OUTPUTSET1_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET1: SETn11 Position     */
-#define SCT_OUTPUTSET1_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn11_Pos)                     /*!< SCT OUTPUTSET1: SETn11 Mask         */
-#define SCT_OUTPUTSET1_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET1: SETn12 Position     */
-#define SCT_OUTPUTSET1_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn12_Pos)                     /*!< SCT OUTPUTSET1: SETn12 Mask         */
-#define SCT_OUTPUTSET1_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET1: SETn13 Position     */
-#define SCT_OUTPUTSET1_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn13_Pos)                     /*!< SCT OUTPUTSET1: SETn13 Mask         */
-#define SCT_OUTPUTSET1_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET1: SETn14 Position     */
-#define SCT_OUTPUTSET1_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn14_Pos)                     /*!< SCT OUTPUTSET1: SETn14 Mask         */
-#define SCT_OUTPUTSET1_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET1: SETn15 Position     */
-#define SCT_OUTPUTSET1_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn15_Pos)                     /*!< SCT OUTPUTSET1: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR1  -----------------------------------------
-#define SCT_OUTPUTCLR1_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR1: CLRn0 Position      */
-#define SCT_OUTPUTCLR1_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos)                      /*!< SCT OUTPUTCLR1: CLRn0 Mask          */
-#define SCT_OUTPUTCLR1_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR1: CLRn1 Position      */
-#define SCT_OUTPUTCLR1_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos)                      /*!< SCT OUTPUTCLR1: CLRn1 Mask          */
-#define SCT_OUTPUTCLR1_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR1: CLRn2 Position      */
-#define SCT_OUTPUTCLR1_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos)                      /*!< SCT OUTPUTCLR1: CLRn2 Mask          */
-#define SCT_OUTPUTCLR1_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR1: CLRn3 Position      */
-#define SCT_OUTPUTCLR1_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos)                      /*!< SCT OUTPUTCLR1: CLRn3 Mask          */
-#define SCT_OUTPUTCLR1_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR1: CLRn4 Position      */
-#define SCT_OUTPUTCLR1_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos)                      /*!< SCT OUTPUTCLR1: CLRn4 Mask          */
-#define SCT_OUTPUTCLR1_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR1: CLRn5 Position      */
-#define SCT_OUTPUTCLR1_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos)                      /*!< SCT OUTPUTCLR1: CLRn5 Mask          */
-#define SCT_OUTPUTCLR1_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR1: CLRn6 Position      */
-#define SCT_OUTPUTCLR1_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos)                      /*!< SCT OUTPUTCLR1: CLRn6 Mask          */
-#define SCT_OUTPUTCLR1_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR1: CLRn7 Position      */
-#define SCT_OUTPUTCLR1_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos)                      /*!< SCT OUTPUTCLR1: CLRn7 Mask          */
-#define SCT_OUTPUTCLR1_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR1: CLRn8 Position      */
-#define SCT_OUTPUTCLR1_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos)                      /*!< SCT OUTPUTCLR1: CLRn8 Mask          */
-#define SCT_OUTPUTCLR1_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR1: CLRn9 Position      */
-#define SCT_OUTPUTCLR1_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos)                      /*!< SCT OUTPUTCLR1: CLRn9 Mask          */
-#define SCT_OUTPUTCLR1_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR1: CLRn10 Position     */
-#define SCT_OUTPUTCLR1_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos)                     /*!< SCT OUTPUTCLR1: CLRn10 Mask         */
-#define SCT_OUTPUTCLR1_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR1: CLRn11 Position     */
-#define SCT_OUTPUTCLR1_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos)                     /*!< SCT OUTPUTCLR1: CLRn11 Mask         */
-#define SCT_OUTPUTCLR1_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR1: CLRn12 Position     */
-#define SCT_OUTPUTCLR1_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos)                     /*!< SCT OUTPUTCLR1: CLRn12 Mask         */
-#define SCT_OUTPUTCLR1_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR1: CLRn13 Position     */
-#define SCT_OUTPUTCLR1_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos)                     /*!< SCT OUTPUTCLR1: CLRn13 Mask         */
-#define SCT_OUTPUTCLR1_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR1: CLRn14 Position     */
-#define SCT_OUTPUTCLR1_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos)                     /*!< SCT OUTPUTCLR1: CLRn14 Mask         */
-#define SCT_OUTPUTCLR1_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR1: CLRn15 Position     */
-#define SCT_OUTPUTCLR1_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos)                     /*!< SCT OUTPUTCLR1: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET2  -----------------------------------------
-#define SCT_OUTPUTSET2_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET2: SETn0 Position      */
-#define SCT_OUTPUTSET2_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn0_Pos)                      /*!< SCT OUTPUTSET2: SETn0 Mask          */
-#define SCT_OUTPUTSET2_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET2: SETn1 Position      */
-#define SCT_OUTPUTSET2_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn1_Pos)                      /*!< SCT OUTPUTSET2: SETn1 Mask          */
-#define SCT_OUTPUTSET2_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET2: SETn2 Position      */
-#define SCT_OUTPUTSET2_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn2_Pos)                      /*!< SCT OUTPUTSET2: SETn2 Mask          */
-#define SCT_OUTPUTSET2_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET2: SETn3 Position      */
-#define SCT_OUTPUTSET2_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn3_Pos)                      /*!< SCT OUTPUTSET2: SETn3 Mask          */
-#define SCT_OUTPUTSET2_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET2: SETn4 Position      */
-#define SCT_OUTPUTSET2_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn4_Pos)                      /*!< SCT OUTPUTSET2: SETn4 Mask          */
-#define SCT_OUTPUTSET2_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET2: SETn5 Position      */
-#define SCT_OUTPUTSET2_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn5_Pos)                      /*!< SCT OUTPUTSET2: SETn5 Mask          */
-#define SCT_OUTPUTSET2_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET2: SETn6 Position      */
-#define SCT_OUTPUTSET2_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn6_Pos)                      /*!< SCT OUTPUTSET2: SETn6 Mask          */
-#define SCT_OUTPUTSET2_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET2: SETn7 Position      */
-#define SCT_OUTPUTSET2_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn7_Pos)                      /*!< SCT OUTPUTSET2: SETn7 Mask          */
-#define SCT_OUTPUTSET2_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET2: SETn8 Position      */
-#define SCT_OUTPUTSET2_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn8_Pos)                      /*!< SCT OUTPUTSET2: SETn8 Mask          */
-#define SCT_OUTPUTSET2_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET2: SETn9 Position      */
-#define SCT_OUTPUTSET2_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn9_Pos)                      /*!< SCT OUTPUTSET2: SETn9 Mask          */
-#define SCT_OUTPUTSET2_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET2: SETn10 Position     */
-#define SCT_OUTPUTSET2_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn10_Pos)                     /*!< SCT OUTPUTSET2: SETn10 Mask         */
-#define SCT_OUTPUTSET2_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET2: SETn11 Position     */
-#define SCT_OUTPUTSET2_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn11_Pos)                     /*!< SCT OUTPUTSET2: SETn11 Mask         */
-#define SCT_OUTPUTSET2_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET2: SETn12 Position     */
-#define SCT_OUTPUTSET2_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn12_Pos)                     /*!< SCT OUTPUTSET2: SETn12 Mask         */
-#define SCT_OUTPUTSET2_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET2: SETn13 Position     */
-#define SCT_OUTPUTSET2_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn13_Pos)                     /*!< SCT OUTPUTSET2: SETn13 Mask         */
-#define SCT_OUTPUTSET2_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET2: SETn14 Position     */
-#define SCT_OUTPUTSET2_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn14_Pos)                     /*!< SCT OUTPUTSET2: SETn14 Mask         */
-#define SCT_OUTPUTSET2_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET2: SETn15 Position     */
-#define SCT_OUTPUTSET2_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn15_Pos)                     /*!< SCT OUTPUTSET2: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR2  -----------------------------------------
-#define SCT_OUTPUTCLR2_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR2: CLRn0 Position      */
-#define SCT_OUTPUTCLR2_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos)                      /*!< SCT OUTPUTCLR2: CLRn0 Mask          */
-#define SCT_OUTPUTCLR2_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR2: CLRn1 Position      */
-#define SCT_OUTPUTCLR2_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos)                      /*!< SCT OUTPUTCLR2: CLRn1 Mask          */
-#define SCT_OUTPUTCLR2_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR2: CLRn2 Position      */
-#define SCT_OUTPUTCLR2_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos)                      /*!< SCT OUTPUTCLR2: CLRn2 Mask          */
-#define SCT_OUTPUTCLR2_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR2: CLRn3 Position      */
-#define SCT_OUTPUTCLR2_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos)                      /*!< SCT OUTPUTCLR2: CLRn3 Mask          */
-#define SCT_OUTPUTCLR2_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR2: CLRn4 Position      */
-#define SCT_OUTPUTCLR2_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos)                      /*!< SCT OUTPUTCLR2: CLRn4 Mask          */
-#define SCT_OUTPUTCLR2_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR2: CLRn5 Position      */
-#define SCT_OUTPUTCLR2_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos)                      /*!< SCT OUTPUTCLR2: CLRn5 Mask          */
-#define SCT_OUTPUTCLR2_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR2: CLRn6 Position      */
-#define SCT_OUTPUTCLR2_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos)                      /*!< SCT OUTPUTCLR2: CLRn6 Mask          */
-#define SCT_OUTPUTCLR2_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR2: CLRn7 Position      */
-#define SCT_OUTPUTCLR2_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos)                      /*!< SCT OUTPUTCLR2: CLRn7 Mask          */
-#define SCT_OUTPUTCLR2_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR2: CLRn8 Position      */
-#define SCT_OUTPUTCLR2_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos)                      /*!< SCT OUTPUTCLR2: CLRn8 Mask          */
-#define SCT_OUTPUTCLR2_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR2: CLRn9 Position      */
-#define SCT_OUTPUTCLR2_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos)                      /*!< SCT OUTPUTCLR2: CLRn9 Mask          */
-#define SCT_OUTPUTCLR2_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR2: CLRn10 Position     */
-#define SCT_OUTPUTCLR2_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos)                     /*!< SCT OUTPUTCLR2: CLRn10 Mask         */
-#define SCT_OUTPUTCLR2_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR2: CLRn11 Position     */
-#define SCT_OUTPUTCLR2_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos)                     /*!< SCT OUTPUTCLR2: CLRn11 Mask         */
-#define SCT_OUTPUTCLR2_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR2: CLRn12 Position     */
-#define SCT_OUTPUTCLR2_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos)                     /*!< SCT OUTPUTCLR2: CLRn12 Mask         */
-#define SCT_OUTPUTCLR2_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR2: CLRn13 Position     */
-#define SCT_OUTPUTCLR2_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos)                     /*!< SCT OUTPUTCLR2: CLRn13 Mask         */
-#define SCT_OUTPUTCLR2_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR2: CLRn14 Position     */
-#define SCT_OUTPUTCLR2_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos)                     /*!< SCT OUTPUTCLR2: CLRn14 Mask         */
-#define SCT_OUTPUTCLR2_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR2: CLRn15 Position     */
-#define SCT_OUTPUTCLR2_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos)                     /*!< SCT OUTPUTCLR2: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET3  -----------------------------------------
-#define SCT_OUTPUTSET3_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET3: SETn0 Position      */
-#define SCT_OUTPUTSET3_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn0_Pos)                      /*!< SCT OUTPUTSET3: SETn0 Mask          */
-#define SCT_OUTPUTSET3_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET3: SETn1 Position      */
-#define SCT_OUTPUTSET3_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn1_Pos)                      /*!< SCT OUTPUTSET3: SETn1 Mask          */
-#define SCT_OUTPUTSET3_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET3: SETn2 Position      */
-#define SCT_OUTPUTSET3_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn2_Pos)                      /*!< SCT OUTPUTSET3: SETn2 Mask          */
-#define SCT_OUTPUTSET3_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET3: SETn3 Position      */
-#define SCT_OUTPUTSET3_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn3_Pos)                      /*!< SCT OUTPUTSET3: SETn3 Mask          */
-#define SCT_OUTPUTSET3_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET3: SETn4 Position      */
-#define SCT_OUTPUTSET3_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn4_Pos)                      /*!< SCT OUTPUTSET3: SETn4 Mask          */
-#define SCT_OUTPUTSET3_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET3: SETn5 Position      */
-#define SCT_OUTPUTSET3_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn5_Pos)                      /*!< SCT OUTPUTSET3: SETn5 Mask          */
-#define SCT_OUTPUTSET3_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET3: SETn6 Position      */
-#define SCT_OUTPUTSET3_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn6_Pos)                      /*!< SCT OUTPUTSET3: SETn6 Mask          */
-#define SCT_OUTPUTSET3_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET3: SETn7 Position      */
-#define SCT_OUTPUTSET3_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn7_Pos)                      /*!< SCT OUTPUTSET3: SETn7 Mask          */
-#define SCT_OUTPUTSET3_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET3: SETn8 Position      */
-#define SCT_OUTPUTSET3_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn8_Pos)                      /*!< SCT OUTPUTSET3: SETn8 Mask          */
-#define SCT_OUTPUTSET3_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET3: SETn9 Position      */
-#define SCT_OUTPUTSET3_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn9_Pos)                      /*!< SCT OUTPUTSET3: SETn9 Mask          */
-#define SCT_OUTPUTSET3_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET3: SETn10 Position     */
-#define SCT_OUTPUTSET3_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn10_Pos)                     /*!< SCT OUTPUTSET3: SETn10 Mask         */
-#define SCT_OUTPUTSET3_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET3: SETn11 Position     */
-#define SCT_OUTPUTSET3_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn11_Pos)                     /*!< SCT OUTPUTSET3: SETn11 Mask         */
-#define SCT_OUTPUTSET3_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET3: SETn12 Position     */
-#define SCT_OUTPUTSET3_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn12_Pos)                     /*!< SCT OUTPUTSET3: SETn12 Mask         */
-#define SCT_OUTPUTSET3_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET3: SETn13 Position     */
-#define SCT_OUTPUTSET3_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn13_Pos)                     /*!< SCT OUTPUTSET3: SETn13 Mask         */
-#define SCT_OUTPUTSET3_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET3: SETn14 Position     */
-#define SCT_OUTPUTSET3_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn14_Pos)                     /*!< SCT OUTPUTSET3: SETn14 Mask         */
-#define SCT_OUTPUTSET3_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET3: SETn15 Position     */
-#define SCT_OUTPUTSET3_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn15_Pos)                     /*!< SCT OUTPUTSET3: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR3  -----------------------------------------
-#define SCT_OUTPUTCLR3_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR3: CLRn0 Position      */
-#define SCT_OUTPUTCLR3_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos)                      /*!< SCT OUTPUTCLR3: CLRn0 Mask          */
-#define SCT_OUTPUTCLR3_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR3: CLRn1 Position      */
-#define SCT_OUTPUTCLR3_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos)                      /*!< SCT OUTPUTCLR3: CLRn1 Mask          */
-#define SCT_OUTPUTCLR3_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR3: CLRn2 Position      */
-#define SCT_OUTPUTCLR3_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos)                      /*!< SCT OUTPUTCLR3: CLRn2 Mask          */
-#define SCT_OUTPUTCLR3_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR3: CLRn3 Position      */
-#define SCT_OUTPUTCLR3_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos)                      /*!< SCT OUTPUTCLR3: CLRn3 Mask          */
-#define SCT_OUTPUTCLR3_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR3: CLRn4 Position      */
-#define SCT_OUTPUTCLR3_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos)                      /*!< SCT OUTPUTCLR3: CLRn4 Mask          */
-#define SCT_OUTPUTCLR3_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR3: CLRn5 Position      */
-#define SCT_OUTPUTCLR3_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos)                      /*!< SCT OUTPUTCLR3: CLRn5 Mask          */
-#define SCT_OUTPUTCLR3_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR3: CLRn6 Position      */
-#define SCT_OUTPUTCLR3_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos)                      /*!< SCT OUTPUTCLR3: CLRn6 Mask          */
-#define SCT_OUTPUTCLR3_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR3: CLRn7 Position      */
-#define SCT_OUTPUTCLR3_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos)                      /*!< SCT OUTPUTCLR3: CLRn7 Mask          */
-#define SCT_OUTPUTCLR3_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR3: CLRn8 Position      */
-#define SCT_OUTPUTCLR3_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos)                      /*!< SCT OUTPUTCLR3: CLRn8 Mask          */
-#define SCT_OUTPUTCLR3_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR3: CLRn9 Position      */
-#define SCT_OUTPUTCLR3_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos)                      /*!< SCT OUTPUTCLR3: CLRn9 Mask          */
-#define SCT_OUTPUTCLR3_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR3: CLRn10 Position     */
-#define SCT_OUTPUTCLR3_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos)                     /*!< SCT OUTPUTCLR3: CLRn10 Mask         */
-#define SCT_OUTPUTCLR3_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR3: CLRn11 Position     */
-#define SCT_OUTPUTCLR3_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos)                     /*!< SCT OUTPUTCLR3: CLRn11 Mask         */
-#define SCT_OUTPUTCLR3_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR3: CLRn12 Position     */
-#define SCT_OUTPUTCLR3_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos)                     /*!< SCT OUTPUTCLR3: CLRn12 Mask         */
-#define SCT_OUTPUTCLR3_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR3: CLRn13 Position     */
-#define SCT_OUTPUTCLR3_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos)                     /*!< SCT OUTPUTCLR3: CLRn13 Mask         */
-#define SCT_OUTPUTCLR3_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR3: CLRn14 Position     */
-#define SCT_OUTPUTCLR3_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos)                     /*!< SCT OUTPUTCLR3: CLRn14 Mask         */
-#define SCT_OUTPUTCLR3_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR3: CLRn15 Position     */
-#define SCT_OUTPUTCLR3_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos)                     /*!< SCT OUTPUTCLR3: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET4  -----------------------------------------
-#define SCT_OUTPUTSET4_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET4: SETn0 Position      */
-#define SCT_OUTPUTSET4_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn0_Pos)                      /*!< SCT OUTPUTSET4: SETn0 Mask          */
-#define SCT_OUTPUTSET4_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET4: SETn1 Position      */
-#define SCT_OUTPUTSET4_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn1_Pos)                      /*!< SCT OUTPUTSET4: SETn1 Mask          */
-#define SCT_OUTPUTSET4_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET4: SETn2 Position      */
-#define SCT_OUTPUTSET4_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn2_Pos)                      /*!< SCT OUTPUTSET4: SETn2 Mask          */
-#define SCT_OUTPUTSET4_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET4: SETn3 Position      */
-#define SCT_OUTPUTSET4_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn3_Pos)                      /*!< SCT OUTPUTSET4: SETn3 Mask          */
-#define SCT_OUTPUTSET4_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET4: SETn4 Position      */
-#define SCT_OUTPUTSET4_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn4_Pos)                      /*!< SCT OUTPUTSET4: SETn4 Mask          */
-#define SCT_OUTPUTSET4_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET4: SETn5 Position      */
-#define SCT_OUTPUTSET4_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn5_Pos)                      /*!< SCT OUTPUTSET4: SETn5 Mask          */
-#define SCT_OUTPUTSET4_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET4: SETn6 Position      */
-#define SCT_OUTPUTSET4_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn6_Pos)                      /*!< SCT OUTPUTSET4: SETn6 Mask          */
-#define SCT_OUTPUTSET4_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET4: SETn7 Position      */
-#define SCT_OUTPUTSET4_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn7_Pos)                      /*!< SCT OUTPUTSET4: SETn7 Mask          */
-#define SCT_OUTPUTSET4_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET4: SETn8 Position      */
-#define SCT_OUTPUTSET4_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn8_Pos)                      /*!< SCT OUTPUTSET4: SETn8 Mask          */
-#define SCT_OUTPUTSET4_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET4: SETn9 Position      */
-#define SCT_OUTPUTSET4_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn9_Pos)                      /*!< SCT OUTPUTSET4: SETn9 Mask          */
-#define SCT_OUTPUTSET4_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET4: SETn10 Position     */
-#define SCT_OUTPUTSET4_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn10_Pos)                     /*!< SCT OUTPUTSET4: SETn10 Mask         */
-#define SCT_OUTPUTSET4_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET4: SETn11 Position     */
-#define SCT_OUTPUTSET4_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn11_Pos)                     /*!< SCT OUTPUTSET4: SETn11 Mask         */
-#define SCT_OUTPUTSET4_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET4: SETn12 Position     */
-#define SCT_OUTPUTSET4_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn12_Pos)                     /*!< SCT OUTPUTSET4: SETn12 Mask         */
-#define SCT_OUTPUTSET4_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET4: SETn13 Position     */
-#define SCT_OUTPUTSET4_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn13_Pos)                     /*!< SCT OUTPUTSET4: SETn13 Mask         */
-#define SCT_OUTPUTSET4_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET4: SETn14 Position     */
-#define SCT_OUTPUTSET4_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn14_Pos)                     /*!< SCT OUTPUTSET4: SETn14 Mask         */
-#define SCT_OUTPUTSET4_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET4: SETn15 Position     */
-#define SCT_OUTPUTSET4_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn15_Pos)                     /*!< SCT OUTPUTSET4: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR4  -----------------------------------------
-#define SCT_OUTPUTCLR4_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR4: CLRn0 Position      */
-#define SCT_OUTPUTCLR4_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos)                      /*!< SCT OUTPUTCLR4: CLRn0 Mask          */
-#define SCT_OUTPUTCLR4_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR4: CLRn1 Position      */
-#define SCT_OUTPUTCLR4_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos)                      /*!< SCT OUTPUTCLR4: CLRn1 Mask          */
-#define SCT_OUTPUTCLR4_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR4: CLRn2 Position      */
-#define SCT_OUTPUTCLR4_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos)                      /*!< SCT OUTPUTCLR4: CLRn2 Mask          */
-#define SCT_OUTPUTCLR4_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR4: CLRn3 Position      */
-#define SCT_OUTPUTCLR4_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos)                      /*!< SCT OUTPUTCLR4: CLRn3 Mask          */
-#define SCT_OUTPUTCLR4_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR4: CLRn4 Position      */
-#define SCT_OUTPUTCLR4_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos)                      /*!< SCT OUTPUTCLR4: CLRn4 Mask          */
-#define SCT_OUTPUTCLR4_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR4: CLRn5 Position      */
-#define SCT_OUTPUTCLR4_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos)                      /*!< SCT OUTPUTCLR4: CLRn5 Mask          */
-#define SCT_OUTPUTCLR4_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR4: CLRn6 Position      */
-#define SCT_OUTPUTCLR4_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos)                      /*!< SCT OUTPUTCLR4: CLRn6 Mask          */
-#define SCT_OUTPUTCLR4_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR4: CLRn7 Position      */
-#define SCT_OUTPUTCLR4_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos)                      /*!< SCT OUTPUTCLR4: CLRn7 Mask          */
-#define SCT_OUTPUTCLR4_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR4: CLRn8 Position      */
-#define SCT_OUTPUTCLR4_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos)                      /*!< SCT OUTPUTCLR4: CLRn8 Mask          */
-#define SCT_OUTPUTCLR4_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR4: CLRn9 Position      */
-#define SCT_OUTPUTCLR4_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos)                      /*!< SCT OUTPUTCLR4: CLRn9 Mask          */
-#define SCT_OUTPUTCLR4_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR4: CLRn10 Position     */
-#define SCT_OUTPUTCLR4_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos)                     /*!< SCT OUTPUTCLR4: CLRn10 Mask         */
-#define SCT_OUTPUTCLR4_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR4: CLRn11 Position     */
-#define SCT_OUTPUTCLR4_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos)                     /*!< SCT OUTPUTCLR4: CLRn11 Mask         */
-#define SCT_OUTPUTCLR4_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR4: CLRn12 Position     */
-#define SCT_OUTPUTCLR4_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos)                     /*!< SCT OUTPUTCLR4: CLRn12 Mask         */
-#define SCT_OUTPUTCLR4_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR4: CLRn13 Position     */
-#define SCT_OUTPUTCLR4_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos)                     /*!< SCT OUTPUTCLR4: CLRn13 Mask         */
-#define SCT_OUTPUTCLR4_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR4: CLRn14 Position     */
-#define SCT_OUTPUTCLR4_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos)                     /*!< SCT OUTPUTCLR4: CLRn14 Mask         */
-#define SCT_OUTPUTCLR4_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR4: CLRn15 Position     */
-#define SCT_OUTPUTCLR4_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos)                     /*!< SCT OUTPUTCLR4: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET5  -----------------------------------------
-#define SCT_OUTPUTSET5_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET5: SETn0 Position      */
-#define SCT_OUTPUTSET5_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn0_Pos)                      /*!< SCT OUTPUTSET5: SETn0 Mask          */
-#define SCT_OUTPUTSET5_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET5: SETn1 Position      */
-#define SCT_OUTPUTSET5_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn1_Pos)                      /*!< SCT OUTPUTSET5: SETn1 Mask          */
-#define SCT_OUTPUTSET5_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET5: SETn2 Position      */
-#define SCT_OUTPUTSET5_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn2_Pos)                      /*!< SCT OUTPUTSET5: SETn2 Mask          */
-#define SCT_OUTPUTSET5_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET5: SETn3 Position      */
-#define SCT_OUTPUTSET5_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn3_Pos)                      /*!< SCT OUTPUTSET5: SETn3 Mask          */
-#define SCT_OUTPUTSET5_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET5: SETn4 Position      */
-#define SCT_OUTPUTSET5_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn4_Pos)                      /*!< SCT OUTPUTSET5: SETn4 Mask          */
-#define SCT_OUTPUTSET5_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET5: SETn5 Position      */
-#define SCT_OUTPUTSET5_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn5_Pos)                      /*!< SCT OUTPUTSET5: SETn5 Mask          */
-#define SCT_OUTPUTSET5_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET5: SETn6 Position      */
-#define SCT_OUTPUTSET5_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn6_Pos)                      /*!< SCT OUTPUTSET5: SETn6 Mask          */
-#define SCT_OUTPUTSET5_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET5: SETn7 Position      */
-#define SCT_OUTPUTSET5_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn7_Pos)                      /*!< SCT OUTPUTSET5: SETn7 Mask          */
-#define SCT_OUTPUTSET5_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET5: SETn8 Position      */
-#define SCT_OUTPUTSET5_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn8_Pos)                      /*!< SCT OUTPUTSET5: SETn8 Mask          */
-#define SCT_OUTPUTSET5_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET5: SETn9 Position      */
-#define SCT_OUTPUTSET5_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn9_Pos)                      /*!< SCT OUTPUTSET5: SETn9 Mask          */
-#define SCT_OUTPUTSET5_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET5: SETn10 Position     */
-#define SCT_OUTPUTSET5_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn10_Pos)                     /*!< SCT OUTPUTSET5: SETn10 Mask         */
-#define SCT_OUTPUTSET5_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET5: SETn11 Position     */
-#define SCT_OUTPUTSET5_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn11_Pos)                     /*!< SCT OUTPUTSET5: SETn11 Mask         */
-#define SCT_OUTPUTSET5_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET5: SETn12 Position     */
-#define SCT_OUTPUTSET5_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn12_Pos)                     /*!< SCT OUTPUTSET5: SETn12 Mask         */
-#define SCT_OUTPUTSET5_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET5: SETn13 Position     */
-#define SCT_OUTPUTSET5_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn13_Pos)                     /*!< SCT OUTPUTSET5: SETn13 Mask         */
-#define SCT_OUTPUTSET5_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET5: SETn14 Position     */
-#define SCT_OUTPUTSET5_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn14_Pos)                     /*!< SCT OUTPUTSET5: SETn14 Mask         */
-#define SCT_OUTPUTSET5_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET5: SETn15 Position     */
-#define SCT_OUTPUTSET5_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn15_Pos)                     /*!< SCT OUTPUTSET5: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR5  -----------------------------------------
-#define SCT_OUTPUTCLR5_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR5: CLRn0 Position      */
-#define SCT_OUTPUTCLR5_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos)                      /*!< SCT OUTPUTCLR5: CLRn0 Mask          */
-#define SCT_OUTPUTCLR5_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR5: CLRn1 Position      */
-#define SCT_OUTPUTCLR5_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos)                      /*!< SCT OUTPUTCLR5: CLRn1 Mask          */
-#define SCT_OUTPUTCLR5_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR5: CLRn2 Position      */
-#define SCT_OUTPUTCLR5_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos)                      /*!< SCT OUTPUTCLR5: CLRn2 Mask          */
-#define SCT_OUTPUTCLR5_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR5: CLRn3 Position      */
-#define SCT_OUTPUTCLR5_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos)                      /*!< SCT OUTPUTCLR5: CLRn3 Mask          */
-#define SCT_OUTPUTCLR5_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR5: CLRn4 Position      */
-#define SCT_OUTPUTCLR5_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos)                      /*!< SCT OUTPUTCLR5: CLRn4 Mask          */
-#define SCT_OUTPUTCLR5_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR5: CLRn5 Position      */
-#define SCT_OUTPUTCLR5_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos)                      /*!< SCT OUTPUTCLR5: CLRn5 Mask          */
-#define SCT_OUTPUTCLR5_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR5: CLRn6 Position      */
-#define SCT_OUTPUTCLR5_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos)                      /*!< SCT OUTPUTCLR5: CLRn6 Mask          */
-#define SCT_OUTPUTCLR5_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR5: CLRn7 Position      */
-#define SCT_OUTPUTCLR5_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos)                      /*!< SCT OUTPUTCLR5: CLRn7 Mask          */
-#define SCT_OUTPUTCLR5_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR5: CLRn8 Position      */
-#define SCT_OUTPUTCLR5_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos)                      /*!< SCT OUTPUTCLR5: CLRn8 Mask          */
-#define SCT_OUTPUTCLR5_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR5: CLRn9 Position      */
-#define SCT_OUTPUTCLR5_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos)                      /*!< SCT OUTPUTCLR5: CLRn9 Mask          */
-#define SCT_OUTPUTCLR5_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR5: CLRn10 Position     */
-#define SCT_OUTPUTCLR5_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos)                     /*!< SCT OUTPUTCLR5: CLRn10 Mask         */
-#define SCT_OUTPUTCLR5_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR5: CLRn11 Position     */
-#define SCT_OUTPUTCLR5_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos)                     /*!< SCT OUTPUTCLR5: CLRn11 Mask         */
-#define SCT_OUTPUTCLR5_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR5: CLRn12 Position     */
-#define SCT_OUTPUTCLR5_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos)                     /*!< SCT OUTPUTCLR5: CLRn12 Mask         */
-#define SCT_OUTPUTCLR5_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR5: CLRn13 Position     */
-#define SCT_OUTPUTCLR5_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos)                     /*!< SCT OUTPUTCLR5: CLRn13 Mask         */
-#define SCT_OUTPUTCLR5_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR5: CLRn14 Position     */
-#define SCT_OUTPUTCLR5_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos)                     /*!< SCT OUTPUTCLR5: CLRn14 Mask         */
-#define SCT_OUTPUTCLR5_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR5: CLRn15 Position     */
-#define SCT_OUTPUTCLR5_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos)                     /*!< SCT OUTPUTCLR5: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET6  -----------------------------------------
-#define SCT_OUTPUTSET6_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET6: SETn0 Position      */
-#define SCT_OUTPUTSET6_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn0_Pos)                      /*!< SCT OUTPUTSET6: SETn0 Mask          */
-#define SCT_OUTPUTSET6_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET6: SETn1 Position      */
-#define SCT_OUTPUTSET6_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn1_Pos)                      /*!< SCT OUTPUTSET6: SETn1 Mask          */
-#define SCT_OUTPUTSET6_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET6: SETn2 Position      */
-#define SCT_OUTPUTSET6_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn2_Pos)                      /*!< SCT OUTPUTSET6: SETn2 Mask          */
-#define SCT_OUTPUTSET6_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET6: SETn3 Position      */
-#define SCT_OUTPUTSET6_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn3_Pos)                      /*!< SCT OUTPUTSET6: SETn3 Mask          */
-#define SCT_OUTPUTSET6_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET6: SETn4 Position      */
-#define SCT_OUTPUTSET6_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn4_Pos)                      /*!< SCT OUTPUTSET6: SETn4 Mask          */
-#define SCT_OUTPUTSET6_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET6: SETn5 Position      */
-#define SCT_OUTPUTSET6_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn5_Pos)                      /*!< SCT OUTPUTSET6: SETn5 Mask          */
-#define SCT_OUTPUTSET6_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET6: SETn6 Position      */
-#define SCT_OUTPUTSET6_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn6_Pos)                      /*!< SCT OUTPUTSET6: SETn6 Mask          */
-#define SCT_OUTPUTSET6_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET6: SETn7 Position      */
-#define SCT_OUTPUTSET6_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn7_Pos)                      /*!< SCT OUTPUTSET6: SETn7 Mask          */
-#define SCT_OUTPUTSET6_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET6: SETn8 Position      */
-#define SCT_OUTPUTSET6_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn8_Pos)                      /*!< SCT OUTPUTSET6: SETn8 Mask          */
-#define SCT_OUTPUTSET6_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET6: SETn9 Position      */
-#define SCT_OUTPUTSET6_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn9_Pos)                      /*!< SCT OUTPUTSET6: SETn9 Mask          */
-#define SCT_OUTPUTSET6_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET6: SETn10 Position     */
-#define SCT_OUTPUTSET6_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn10_Pos)                     /*!< SCT OUTPUTSET6: SETn10 Mask         */
-#define SCT_OUTPUTSET6_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET6: SETn11 Position     */
-#define SCT_OUTPUTSET6_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn11_Pos)                     /*!< SCT OUTPUTSET6: SETn11 Mask         */
-#define SCT_OUTPUTSET6_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET6: SETn12 Position     */
-#define SCT_OUTPUTSET6_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn12_Pos)                     /*!< SCT OUTPUTSET6: SETn12 Mask         */
-#define SCT_OUTPUTSET6_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET6: SETn13 Position     */
-#define SCT_OUTPUTSET6_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn13_Pos)                     /*!< SCT OUTPUTSET6: SETn13 Mask         */
-#define SCT_OUTPUTSET6_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET6: SETn14 Position     */
-#define SCT_OUTPUTSET6_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn14_Pos)                     /*!< SCT OUTPUTSET6: SETn14 Mask         */
-#define SCT_OUTPUTSET6_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET6: SETn15 Position     */
-#define SCT_OUTPUTSET6_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn15_Pos)                     /*!< SCT OUTPUTSET6: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR6  -----------------------------------------
-#define SCT_OUTPUTCLR6_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR6: CLRn0 Position      */
-#define SCT_OUTPUTCLR6_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos)                      /*!< SCT OUTPUTCLR6: CLRn0 Mask          */
-#define SCT_OUTPUTCLR6_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR6: CLRn1 Position      */
-#define SCT_OUTPUTCLR6_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos)                      /*!< SCT OUTPUTCLR6: CLRn1 Mask          */
-#define SCT_OUTPUTCLR6_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR6: CLRn2 Position      */
-#define SCT_OUTPUTCLR6_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos)                      /*!< SCT OUTPUTCLR6: CLRn2 Mask          */
-#define SCT_OUTPUTCLR6_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR6: CLRn3 Position      */
-#define SCT_OUTPUTCLR6_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos)                      /*!< SCT OUTPUTCLR6: CLRn3 Mask          */
-#define SCT_OUTPUTCLR6_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR6: CLRn4 Position      */
-#define SCT_OUTPUTCLR6_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos)                      /*!< SCT OUTPUTCLR6: CLRn4 Mask          */
-#define SCT_OUTPUTCLR6_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR6: CLRn5 Position      */
-#define SCT_OUTPUTCLR6_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos)                      /*!< SCT OUTPUTCLR6: CLRn5 Mask          */
-#define SCT_OUTPUTCLR6_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR6: CLRn6 Position      */
-#define SCT_OUTPUTCLR6_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos)                      /*!< SCT OUTPUTCLR6: CLRn6 Mask          */
-#define SCT_OUTPUTCLR6_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR6: CLRn7 Position      */
-#define SCT_OUTPUTCLR6_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos)                      /*!< SCT OUTPUTCLR6: CLRn7 Mask          */
-#define SCT_OUTPUTCLR6_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR6: CLRn8 Position      */
-#define SCT_OUTPUTCLR6_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos)                      /*!< SCT OUTPUTCLR6: CLRn8 Mask          */
-#define SCT_OUTPUTCLR6_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR6: CLRn9 Position      */
-#define SCT_OUTPUTCLR6_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos)                      /*!< SCT OUTPUTCLR6: CLRn9 Mask          */
-#define SCT_OUTPUTCLR6_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR6: CLRn10 Position     */
-#define SCT_OUTPUTCLR6_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos)                     /*!< SCT OUTPUTCLR6: CLRn10 Mask         */
-#define SCT_OUTPUTCLR6_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR6: CLRn11 Position     */
-#define SCT_OUTPUTCLR6_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos)                     /*!< SCT OUTPUTCLR6: CLRn11 Mask         */
-#define SCT_OUTPUTCLR6_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR6: CLRn12 Position     */
-#define SCT_OUTPUTCLR6_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos)                     /*!< SCT OUTPUTCLR6: CLRn12 Mask         */
-#define SCT_OUTPUTCLR6_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR6: CLRn13 Position     */
-#define SCT_OUTPUTCLR6_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos)                     /*!< SCT OUTPUTCLR6: CLRn13 Mask         */
-#define SCT_OUTPUTCLR6_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR6: CLRn14 Position     */
-#define SCT_OUTPUTCLR6_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos)                     /*!< SCT OUTPUTCLR6: CLRn14 Mask         */
-#define SCT_OUTPUTCLR6_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR6: CLRn15 Position     */
-#define SCT_OUTPUTCLR6_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos)                     /*!< SCT OUTPUTCLR6: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET7  -----------------------------------------
-#define SCT_OUTPUTSET7_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET7: SETn0 Position      */
-#define SCT_OUTPUTSET7_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn0_Pos)                      /*!< SCT OUTPUTSET7: SETn0 Mask          */
-#define SCT_OUTPUTSET7_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET7: SETn1 Position      */
-#define SCT_OUTPUTSET7_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn1_Pos)                      /*!< SCT OUTPUTSET7: SETn1 Mask          */
-#define SCT_OUTPUTSET7_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET7: SETn2 Position      */
-#define SCT_OUTPUTSET7_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn2_Pos)                      /*!< SCT OUTPUTSET7: SETn2 Mask          */
-#define SCT_OUTPUTSET7_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET7: SETn3 Position      */
-#define SCT_OUTPUTSET7_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn3_Pos)                      /*!< SCT OUTPUTSET7: SETn3 Mask          */
-#define SCT_OUTPUTSET7_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET7: SETn4 Position      */
-#define SCT_OUTPUTSET7_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn4_Pos)                      /*!< SCT OUTPUTSET7: SETn4 Mask          */
-#define SCT_OUTPUTSET7_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET7: SETn5 Position      */
-#define SCT_OUTPUTSET7_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn5_Pos)                      /*!< SCT OUTPUTSET7: SETn5 Mask          */
-#define SCT_OUTPUTSET7_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET7: SETn6 Position      */
-#define SCT_OUTPUTSET7_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn6_Pos)                      /*!< SCT OUTPUTSET7: SETn6 Mask          */
-#define SCT_OUTPUTSET7_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET7: SETn7 Position      */
-#define SCT_OUTPUTSET7_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn7_Pos)                      /*!< SCT OUTPUTSET7: SETn7 Mask          */
-#define SCT_OUTPUTSET7_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET7: SETn8 Position      */
-#define SCT_OUTPUTSET7_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn8_Pos)                      /*!< SCT OUTPUTSET7: SETn8 Mask          */
-#define SCT_OUTPUTSET7_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET7: SETn9 Position      */
-#define SCT_OUTPUTSET7_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn9_Pos)                      /*!< SCT OUTPUTSET7: SETn9 Mask          */
-#define SCT_OUTPUTSET7_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET7: SETn10 Position     */
-#define SCT_OUTPUTSET7_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn10_Pos)                     /*!< SCT OUTPUTSET7: SETn10 Mask         */
-#define SCT_OUTPUTSET7_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET7: SETn11 Position     */
-#define SCT_OUTPUTSET7_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn11_Pos)                     /*!< SCT OUTPUTSET7: SETn11 Mask         */
-#define SCT_OUTPUTSET7_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET7: SETn12 Position     */
-#define SCT_OUTPUTSET7_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn12_Pos)                     /*!< SCT OUTPUTSET7: SETn12 Mask         */
-#define SCT_OUTPUTSET7_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET7: SETn13 Position     */
-#define SCT_OUTPUTSET7_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn13_Pos)                     /*!< SCT OUTPUTSET7: SETn13 Mask         */
-#define SCT_OUTPUTSET7_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET7: SETn14 Position     */
-#define SCT_OUTPUTSET7_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn14_Pos)                     /*!< SCT OUTPUTSET7: SETn14 Mask         */
-#define SCT_OUTPUTSET7_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET7: SETn15 Position     */
-#define SCT_OUTPUTSET7_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn15_Pos)                     /*!< SCT OUTPUTSET7: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR7  -----------------------------------------
-#define SCT_OUTPUTCLR7_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR7: CLRn0 Position      */
-#define SCT_OUTPUTCLR7_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos)                      /*!< SCT OUTPUTCLR7: CLRn0 Mask          */
-#define SCT_OUTPUTCLR7_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR7: CLRn1 Position      */
-#define SCT_OUTPUTCLR7_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos)                      /*!< SCT OUTPUTCLR7: CLRn1 Mask          */
-#define SCT_OUTPUTCLR7_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR7: CLRn2 Position      */
-#define SCT_OUTPUTCLR7_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos)                      /*!< SCT OUTPUTCLR7: CLRn2 Mask          */
-#define SCT_OUTPUTCLR7_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR7: CLRn3 Position      */
-#define SCT_OUTPUTCLR7_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos)                      /*!< SCT OUTPUTCLR7: CLRn3 Mask          */
-#define SCT_OUTPUTCLR7_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR7: CLRn4 Position      */
-#define SCT_OUTPUTCLR7_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos)                      /*!< SCT OUTPUTCLR7: CLRn4 Mask          */
-#define SCT_OUTPUTCLR7_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR7: CLRn5 Position      */
-#define SCT_OUTPUTCLR7_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos)                      /*!< SCT OUTPUTCLR7: CLRn5 Mask          */
-#define SCT_OUTPUTCLR7_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR7: CLRn6 Position      */
-#define SCT_OUTPUTCLR7_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos)                      /*!< SCT OUTPUTCLR7: CLRn6 Mask          */
-#define SCT_OUTPUTCLR7_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR7: CLRn7 Position      */
-#define SCT_OUTPUTCLR7_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos)                      /*!< SCT OUTPUTCLR7: CLRn7 Mask          */
-#define SCT_OUTPUTCLR7_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR7: CLRn8 Position      */
-#define SCT_OUTPUTCLR7_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos)                      /*!< SCT OUTPUTCLR7: CLRn8 Mask          */
-#define SCT_OUTPUTCLR7_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR7: CLRn9 Position      */
-#define SCT_OUTPUTCLR7_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos)                      /*!< SCT OUTPUTCLR7: CLRn9 Mask          */
-#define SCT_OUTPUTCLR7_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR7: CLRn10 Position     */
-#define SCT_OUTPUTCLR7_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos)                     /*!< SCT OUTPUTCLR7: CLRn10 Mask         */
-#define SCT_OUTPUTCLR7_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR7: CLRn11 Position     */
-#define SCT_OUTPUTCLR7_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos)                     /*!< SCT OUTPUTCLR7: CLRn11 Mask         */
-#define SCT_OUTPUTCLR7_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR7: CLRn12 Position     */
-#define SCT_OUTPUTCLR7_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos)                     /*!< SCT OUTPUTCLR7: CLRn12 Mask         */
-#define SCT_OUTPUTCLR7_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR7: CLRn13 Position     */
-#define SCT_OUTPUTCLR7_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos)                     /*!< SCT OUTPUTCLR7: CLRn13 Mask         */
-#define SCT_OUTPUTCLR7_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR7: CLRn14 Position     */
-#define SCT_OUTPUTCLR7_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos)                     /*!< SCT OUTPUTCLR7: CLRn14 Mask         */
-#define SCT_OUTPUTCLR7_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR7: CLRn15 Position     */
-#define SCT_OUTPUTCLR7_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos)                     /*!< SCT OUTPUTCLR7: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET8  -----------------------------------------
-#define SCT_OUTPUTSET8_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET8: SETn0 Position      */
-#define SCT_OUTPUTSET8_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn0_Pos)                      /*!< SCT OUTPUTSET8: SETn0 Mask          */
-#define SCT_OUTPUTSET8_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET8: SETn1 Position      */
-#define SCT_OUTPUTSET8_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn1_Pos)                      /*!< SCT OUTPUTSET8: SETn1 Mask          */
-#define SCT_OUTPUTSET8_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET8: SETn2 Position      */
-#define SCT_OUTPUTSET8_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn2_Pos)                      /*!< SCT OUTPUTSET8: SETn2 Mask          */
-#define SCT_OUTPUTSET8_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET8: SETn3 Position      */
-#define SCT_OUTPUTSET8_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn3_Pos)                      /*!< SCT OUTPUTSET8: SETn3 Mask          */
-#define SCT_OUTPUTSET8_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET8: SETn4 Position      */
-#define SCT_OUTPUTSET8_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn4_Pos)                      /*!< SCT OUTPUTSET8: SETn4 Mask          */
-#define SCT_OUTPUTSET8_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET8: SETn5 Position      */
-#define SCT_OUTPUTSET8_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn5_Pos)                      /*!< SCT OUTPUTSET8: SETn5 Mask          */
-#define SCT_OUTPUTSET8_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET8: SETn6 Position      */
-#define SCT_OUTPUTSET8_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn6_Pos)                      /*!< SCT OUTPUTSET8: SETn6 Mask          */
-#define SCT_OUTPUTSET8_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET8: SETn7 Position      */
-#define SCT_OUTPUTSET8_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn7_Pos)                      /*!< SCT OUTPUTSET8: SETn7 Mask          */
-#define SCT_OUTPUTSET8_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET8: SETn8 Position      */
-#define SCT_OUTPUTSET8_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn8_Pos)                      /*!< SCT OUTPUTSET8: SETn8 Mask          */
-#define SCT_OUTPUTSET8_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET8: SETn9 Position      */
-#define SCT_OUTPUTSET8_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn9_Pos)                      /*!< SCT OUTPUTSET8: SETn9 Mask          */
-#define SCT_OUTPUTSET8_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET8: SETn10 Position     */
-#define SCT_OUTPUTSET8_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn10_Pos)                     /*!< SCT OUTPUTSET8: SETn10 Mask         */
-#define SCT_OUTPUTSET8_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET8: SETn11 Position     */
-#define SCT_OUTPUTSET8_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn11_Pos)                     /*!< SCT OUTPUTSET8: SETn11 Mask         */
-#define SCT_OUTPUTSET8_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET8: SETn12 Position     */
-#define SCT_OUTPUTSET8_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn12_Pos)                     /*!< SCT OUTPUTSET8: SETn12 Mask         */
-#define SCT_OUTPUTSET8_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET8: SETn13 Position     */
-#define SCT_OUTPUTSET8_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn13_Pos)                     /*!< SCT OUTPUTSET8: SETn13 Mask         */
-#define SCT_OUTPUTSET8_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET8: SETn14 Position     */
-#define SCT_OUTPUTSET8_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn14_Pos)                     /*!< SCT OUTPUTSET8: SETn14 Mask         */
-#define SCT_OUTPUTSET8_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET8: SETn15 Position     */
-#define SCT_OUTPUTSET8_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn15_Pos)                     /*!< SCT OUTPUTSET8: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR8  -----------------------------------------
-#define SCT_OUTPUTCLR8_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR8: CLRn0 Position      */
-#define SCT_OUTPUTCLR8_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos)                      /*!< SCT OUTPUTCLR8: CLRn0 Mask          */
-#define SCT_OUTPUTCLR8_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR8: CLRn1 Position      */
-#define SCT_OUTPUTCLR8_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos)                      /*!< SCT OUTPUTCLR8: CLRn1 Mask          */
-#define SCT_OUTPUTCLR8_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR8: CLRn2 Position      */
-#define SCT_OUTPUTCLR8_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos)                      /*!< SCT OUTPUTCLR8: CLRn2 Mask          */
-#define SCT_OUTPUTCLR8_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR8: CLRn3 Position      */
-#define SCT_OUTPUTCLR8_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos)                      /*!< SCT OUTPUTCLR8: CLRn3 Mask          */
-#define SCT_OUTPUTCLR8_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR8: CLRn4 Position      */
-#define SCT_OUTPUTCLR8_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos)                      /*!< SCT OUTPUTCLR8: CLRn4 Mask          */
-#define SCT_OUTPUTCLR8_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR8: CLRn5 Position      */
-#define SCT_OUTPUTCLR8_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos)                      /*!< SCT OUTPUTCLR8: CLRn5 Mask          */
-#define SCT_OUTPUTCLR8_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR8: CLRn6 Position      */
-#define SCT_OUTPUTCLR8_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos)                      /*!< SCT OUTPUTCLR8: CLRn6 Mask          */
-#define SCT_OUTPUTCLR8_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR8: CLRn7 Position      */
-#define SCT_OUTPUTCLR8_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos)                      /*!< SCT OUTPUTCLR8: CLRn7 Mask          */
-#define SCT_OUTPUTCLR8_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR8: CLRn8 Position      */
-#define SCT_OUTPUTCLR8_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos)                      /*!< SCT OUTPUTCLR8: CLRn8 Mask          */
-#define SCT_OUTPUTCLR8_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR8: CLRn9 Position      */
-#define SCT_OUTPUTCLR8_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos)                      /*!< SCT OUTPUTCLR8: CLRn9 Mask          */
-#define SCT_OUTPUTCLR8_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR8: CLRn10 Position     */
-#define SCT_OUTPUTCLR8_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos)                     /*!< SCT OUTPUTCLR8: CLRn10 Mask         */
-#define SCT_OUTPUTCLR8_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR8: CLRn11 Position     */
-#define SCT_OUTPUTCLR8_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos)                     /*!< SCT OUTPUTCLR8: CLRn11 Mask         */
-#define SCT_OUTPUTCLR8_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR8: CLRn12 Position     */
-#define SCT_OUTPUTCLR8_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos)                     /*!< SCT OUTPUTCLR8: CLRn12 Mask         */
-#define SCT_OUTPUTCLR8_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR8: CLRn13 Position     */
-#define SCT_OUTPUTCLR8_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos)                     /*!< SCT OUTPUTCLR8: CLRn13 Mask         */
-#define SCT_OUTPUTCLR8_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR8: CLRn14 Position     */
-#define SCT_OUTPUTCLR8_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos)                     /*!< SCT OUTPUTCLR8: CLRn14 Mask         */
-#define SCT_OUTPUTCLR8_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR8: CLRn15 Position     */
-#define SCT_OUTPUTCLR8_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos)                     /*!< SCT OUTPUTCLR8: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET9  -----------------------------------------
-#define SCT_OUTPUTSET9_SETn0_Pos                              0                                                         /*!< SCT OUTPUTSET9: SETn0 Position      */
-#define SCT_OUTPUTSET9_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn0_Pos)                      /*!< SCT OUTPUTSET9: SETn0 Mask          */
-#define SCT_OUTPUTSET9_SETn1_Pos                              1                                                         /*!< SCT OUTPUTSET9: SETn1 Position      */
-#define SCT_OUTPUTSET9_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn1_Pos)                      /*!< SCT OUTPUTSET9: SETn1 Mask          */
-#define SCT_OUTPUTSET9_SETn2_Pos                              2                                                         /*!< SCT OUTPUTSET9: SETn2 Position      */
-#define SCT_OUTPUTSET9_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn2_Pos)                      /*!< SCT OUTPUTSET9: SETn2 Mask          */
-#define SCT_OUTPUTSET9_SETn3_Pos                              3                                                         /*!< SCT OUTPUTSET9: SETn3 Position      */
-#define SCT_OUTPUTSET9_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn3_Pos)                      /*!< SCT OUTPUTSET9: SETn3 Mask          */
-#define SCT_OUTPUTSET9_SETn4_Pos                              4                                                         /*!< SCT OUTPUTSET9: SETn4 Position      */
-#define SCT_OUTPUTSET9_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn4_Pos)                      /*!< SCT OUTPUTSET9: SETn4 Mask          */
-#define SCT_OUTPUTSET9_SETn5_Pos                              5                                                         /*!< SCT OUTPUTSET9: SETn5 Position      */
-#define SCT_OUTPUTSET9_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn5_Pos)                      /*!< SCT OUTPUTSET9: SETn5 Mask          */
-#define SCT_OUTPUTSET9_SETn6_Pos                              6                                                         /*!< SCT OUTPUTSET9: SETn6 Position      */
-#define SCT_OUTPUTSET9_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn6_Pos)                      /*!< SCT OUTPUTSET9: SETn6 Mask          */
-#define SCT_OUTPUTSET9_SETn7_Pos                              7                                                         /*!< SCT OUTPUTSET9: SETn7 Position      */
-#define SCT_OUTPUTSET9_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn7_Pos)                      /*!< SCT OUTPUTSET9: SETn7 Mask          */
-#define SCT_OUTPUTSET9_SETn8_Pos                              8                                                         /*!< SCT OUTPUTSET9: SETn8 Position      */
-#define SCT_OUTPUTSET9_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn8_Pos)                      /*!< SCT OUTPUTSET9: SETn8 Mask          */
-#define SCT_OUTPUTSET9_SETn9_Pos                              9                                                         /*!< SCT OUTPUTSET9: SETn9 Position      */
-#define SCT_OUTPUTSET9_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn9_Pos)                      /*!< SCT OUTPUTSET9: SETn9 Mask          */
-#define SCT_OUTPUTSET9_SETn10_Pos                             10                                                        /*!< SCT OUTPUTSET9: SETn10 Position     */
-#define SCT_OUTPUTSET9_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn10_Pos)                     /*!< SCT OUTPUTSET9: SETn10 Mask         */
-#define SCT_OUTPUTSET9_SETn11_Pos                             11                                                        /*!< SCT OUTPUTSET9: SETn11 Position     */
-#define SCT_OUTPUTSET9_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn11_Pos)                     /*!< SCT OUTPUTSET9: SETn11 Mask         */
-#define SCT_OUTPUTSET9_SETn12_Pos                             12                                                        /*!< SCT OUTPUTSET9: SETn12 Position     */
-#define SCT_OUTPUTSET9_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn12_Pos)                     /*!< SCT OUTPUTSET9: SETn12 Mask         */
-#define SCT_OUTPUTSET9_SETn13_Pos                             13                                                        /*!< SCT OUTPUTSET9: SETn13 Position     */
-#define SCT_OUTPUTSET9_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn13_Pos)                     /*!< SCT OUTPUTSET9: SETn13 Mask         */
-#define SCT_OUTPUTSET9_SETn14_Pos                             14                                                        /*!< SCT OUTPUTSET9: SETn14 Position     */
-#define SCT_OUTPUTSET9_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn14_Pos)                     /*!< SCT OUTPUTSET9: SETn14 Mask         */
-#define SCT_OUTPUTSET9_SETn15_Pos                             15                                                        /*!< SCT OUTPUTSET9: SETn15 Position     */
-#define SCT_OUTPUTSET9_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn15_Pos)                     /*!< SCT OUTPUTSET9: SETn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTCLR9  -----------------------------------------
-#define SCT_OUTPUTCLR9_CLRn0_Pos                              0                                                         /*!< SCT OUTPUTCLR9: CLRn0 Position      */
-#define SCT_OUTPUTCLR9_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos)                      /*!< SCT OUTPUTCLR9: CLRn0 Mask          */
-#define SCT_OUTPUTCLR9_CLRn1_Pos                              1                                                         /*!< SCT OUTPUTCLR9: CLRn1 Position      */
-#define SCT_OUTPUTCLR9_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos)                      /*!< SCT OUTPUTCLR9: CLRn1 Mask          */
-#define SCT_OUTPUTCLR9_CLRn2_Pos                              2                                                         /*!< SCT OUTPUTCLR9: CLRn2 Position      */
-#define SCT_OUTPUTCLR9_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos)                      /*!< SCT OUTPUTCLR9: CLRn2 Mask          */
-#define SCT_OUTPUTCLR9_CLRn3_Pos                              3                                                         /*!< SCT OUTPUTCLR9: CLRn3 Position      */
-#define SCT_OUTPUTCLR9_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos)                      /*!< SCT OUTPUTCLR9: CLRn3 Mask          */
-#define SCT_OUTPUTCLR9_CLRn4_Pos                              4                                                         /*!< SCT OUTPUTCLR9: CLRn4 Position      */
-#define SCT_OUTPUTCLR9_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos)                      /*!< SCT OUTPUTCLR9: CLRn4 Mask          */
-#define SCT_OUTPUTCLR9_CLRn5_Pos                              5                                                         /*!< SCT OUTPUTCLR9: CLRn5 Position      */
-#define SCT_OUTPUTCLR9_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos)                      /*!< SCT OUTPUTCLR9: CLRn5 Mask          */
-#define SCT_OUTPUTCLR9_CLRn6_Pos                              6                                                         /*!< SCT OUTPUTCLR9: CLRn6 Position      */
-#define SCT_OUTPUTCLR9_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos)                      /*!< SCT OUTPUTCLR9: CLRn6 Mask          */
-#define SCT_OUTPUTCLR9_CLRn7_Pos                              7                                                         /*!< SCT OUTPUTCLR9: CLRn7 Position      */
-#define SCT_OUTPUTCLR9_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos)                      /*!< SCT OUTPUTCLR9: CLRn7 Mask          */
-#define SCT_OUTPUTCLR9_CLRn8_Pos                              8                                                         /*!< SCT OUTPUTCLR9: CLRn8 Position      */
-#define SCT_OUTPUTCLR9_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos)                      /*!< SCT OUTPUTCLR9: CLRn8 Mask          */
-#define SCT_OUTPUTCLR9_CLRn9_Pos                              9                                                         /*!< SCT OUTPUTCLR9: CLRn9 Position      */
-#define SCT_OUTPUTCLR9_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos)                      /*!< SCT OUTPUTCLR9: CLRn9 Mask          */
-#define SCT_OUTPUTCLR9_CLRn10_Pos                             10                                                        /*!< SCT OUTPUTCLR9: CLRn10 Position     */
-#define SCT_OUTPUTCLR9_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos)                     /*!< SCT OUTPUTCLR9: CLRn10 Mask         */
-#define SCT_OUTPUTCLR9_CLRn11_Pos                             11                                                        /*!< SCT OUTPUTCLR9: CLRn11 Position     */
-#define SCT_OUTPUTCLR9_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos)                     /*!< SCT OUTPUTCLR9: CLRn11 Mask         */
-#define SCT_OUTPUTCLR9_CLRn12_Pos                             12                                                        /*!< SCT OUTPUTCLR9: CLRn12 Position     */
-#define SCT_OUTPUTCLR9_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos)                     /*!< SCT OUTPUTCLR9: CLRn12 Mask         */
-#define SCT_OUTPUTCLR9_CLRn13_Pos                             13                                                        /*!< SCT OUTPUTCLR9: CLRn13 Position     */
-#define SCT_OUTPUTCLR9_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos)                     /*!< SCT OUTPUTCLR9: CLRn13 Mask         */
-#define SCT_OUTPUTCLR9_CLRn14_Pos                             14                                                        /*!< SCT OUTPUTCLR9: CLRn14 Position     */
-#define SCT_OUTPUTCLR9_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos)                     /*!< SCT OUTPUTCLR9: CLRn14 Mask         */
-#define SCT_OUTPUTCLR9_CLRn15_Pos                             15                                                        /*!< SCT OUTPUTCLR9: CLRn15 Position     */
-#define SCT_OUTPUTCLR9_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos)                     /*!< SCT OUTPUTCLR9: CLRn15 Mask         */
-
-// -------------------------------------  SCT_OUTPUTSET10  ----------------------------------------
-#define SCT_OUTPUTSET10_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET10: SETn0 Position     */
-#define SCT_OUTPUTSET10_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn0_Pos)                     /*!< SCT OUTPUTSET10: SETn0 Mask         */
-#define SCT_OUTPUTSET10_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET10: SETn1 Position     */
-#define SCT_OUTPUTSET10_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn1_Pos)                     /*!< SCT OUTPUTSET10: SETn1 Mask         */
-#define SCT_OUTPUTSET10_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET10: SETn2 Position     */
-#define SCT_OUTPUTSET10_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn2_Pos)                     /*!< SCT OUTPUTSET10: SETn2 Mask         */
-#define SCT_OUTPUTSET10_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET10: SETn3 Position     */
-#define SCT_OUTPUTSET10_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn3_Pos)                     /*!< SCT OUTPUTSET10: SETn3 Mask         */
-#define SCT_OUTPUTSET10_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET10: SETn4 Position     */
-#define SCT_OUTPUTSET10_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn4_Pos)                     /*!< SCT OUTPUTSET10: SETn4 Mask         */
-#define SCT_OUTPUTSET10_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET10: SETn5 Position     */
-#define SCT_OUTPUTSET10_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn5_Pos)                     /*!< SCT OUTPUTSET10: SETn5 Mask         */
-#define SCT_OUTPUTSET10_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET10: SETn6 Position     */
-#define SCT_OUTPUTSET10_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn6_Pos)                     /*!< SCT OUTPUTSET10: SETn6 Mask         */
-#define SCT_OUTPUTSET10_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET10: SETn7 Position     */
-#define SCT_OUTPUTSET10_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn7_Pos)                     /*!< SCT OUTPUTSET10: SETn7 Mask         */
-#define SCT_OUTPUTSET10_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET10: SETn8 Position     */
-#define SCT_OUTPUTSET10_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn8_Pos)                     /*!< SCT OUTPUTSET10: SETn8 Mask         */
-#define SCT_OUTPUTSET10_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET10: SETn9 Position     */
-#define SCT_OUTPUTSET10_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn9_Pos)                     /*!< SCT OUTPUTSET10: SETn9 Mask         */
-#define SCT_OUTPUTSET10_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET10: SETn10 Position    */
-#define SCT_OUTPUTSET10_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn10_Pos)                    /*!< SCT OUTPUTSET10: SETn10 Mask        */
-#define SCT_OUTPUTSET10_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET10: SETn11 Position    */
-#define SCT_OUTPUTSET10_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn11_Pos)                    /*!< SCT OUTPUTSET10: SETn11 Mask        */
-#define SCT_OUTPUTSET10_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET10: SETn12 Position    */
-#define SCT_OUTPUTSET10_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn12_Pos)                    /*!< SCT OUTPUTSET10: SETn12 Mask        */
-#define SCT_OUTPUTSET10_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET10: SETn13 Position    */
-#define SCT_OUTPUTSET10_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn13_Pos)                    /*!< SCT OUTPUTSET10: SETn13 Mask        */
-#define SCT_OUTPUTSET10_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET10: SETn14 Position    */
-#define SCT_OUTPUTSET10_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn14_Pos)                    /*!< SCT OUTPUTSET10: SETn14 Mask        */
-#define SCT_OUTPUTSET10_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET10: SETn15 Position    */
-#define SCT_OUTPUTSET10_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn15_Pos)                    /*!< SCT OUTPUTSET10: SETn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTCLR10  ----------------------------------------
-#define SCT_OUTPUTCLR10_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR10: CLRn0 Position     */
-#define SCT_OUTPUTCLR10_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos)                     /*!< SCT OUTPUTCLR10: CLRn0 Mask         */
-#define SCT_OUTPUTCLR10_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR10: CLRn1 Position     */
-#define SCT_OUTPUTCLR10_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos)                     /*!< SCT OUTPUTCLR10: CLRn1 Mask         */
-#define SCT_OUTPUTCLR10_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR10: CLRn2 Position     */
-#define SCT_OUTPUTCLR10_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos)                     /*!< SCT OUTPUTCLR10: CLRn2 Mask         */
-#define SCT_OUTPUTCLR10_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR10: CLRn3 Position     */
-#define SCT_OUTPUTCLR10_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos)                     /*!< SCT OUTPUTCLR10: CLRn3 Mask         */
-#define SCT_OUTPUTCLR10_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR10: CLRn4 Position     */
-#define SCT_OUTPUTCLR10_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos)                     /*!< SCT OUTPUTCLR10: CLRn4 Mask         */
-#define SCT_OUTPUTCLR10_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR10: CLRn5 Position     */
-#define SCT_OUTPUTCLR10_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos)                     /*!< SCT OUTPUTCLR10: CLRn5 Mask         */
-#define SCT_OUTPUTCLR10_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR10: CLRn6 Position     */
-#define SCT_OUTPUTCLR10_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos)                     /*!< SCT OUTPUTCLR10: CLRn6 Mask         */
-#define SCT_OUTPUTCLR10_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR10: CLRn7 Position     */
-#define SCT_OUTPUTCLR10_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos)                     /*!< SCT OUTPUTCLR10: CLRn7 Mask         */
-#define SCT_OUTPUTCLR10_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR10: CLRn8 Position     */
-#define SCT_OUTPUTCLR10_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos)                     /*!< SCT OUTPUTCLR10: CLRn8 Mask         */
-#define SCT_OUTPUTCLR10_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR10: CLRn9 Position     */
-#define SCT_OUTPUTCLR10_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos)                     /*!< SCT OUTPUTCLR10: CLRn9 Mask         */
-#define SCT_OUTPUTCLR10_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR10: CLRn10 Position    */
-#define SCT_OUTPUTCLR10_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos)                    /*!< SCT OUTPUTCLR10: CLRn10 Mask        */
-#define SCT_OUTPUTCLR10_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR10: CLRn11 Position    */
-#define SCT_OUTPUTCLR10_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos)                    /*!< SCT OUTPUTCLR10: CLRn11 Mask        */
-#define SCT_OUTPUTCLR10_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR10: CLRn12 Position    */
-#define SCT_OUTPUTCLR10_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos)                    /*!< SCT OUTPUTCLR10: CLRn12 Mask        */
-#define SCT_OUTPUTCLR10_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR10: CLRn13 Position    */
-#define SCT_OUTPUTCLR10_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos)                    /*!< SCT OUTPUTCLR10: CLRn13 Mask        */
-#define SCT_OUTPUTCLR10_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR10: CLRn14 Position    */
-#define SCT_OUTPUTCLR10_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos)                    /*!< SCT OUTPUTCLR10: CLRn14 Mask        */
-#define SCT_OUTPUTCLR10_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR10: CLRn15 Position    */
-#define SCT_OUTPUTCLR10_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos)                    /*!< SCT OUTPUTCLR10: CLRn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTSET11  ----------------------------------------
-#define SCT_OUTPUTSET11_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET11: SETn0 Position     */
-#define SCT_OUTPUTSET11_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn0_Pos)                     /*!< SCT OUTPUTSET11: SETn0 Mask         */
-#define SCT_OUTPUTSET11_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET11: SETn1 Position     */
-#define SCT_OUTPUTSET11_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn1_Pos)                     /*!< SCT OUTPUTSET11: SETn1 Mask         */
-#define SCT_OUTPUTSET11_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET11: SETn2 Position     */
-#define SCT_OUTPUTSET11_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn2_Pos)                     /*!< SCT OUTPUTSET11: SETn2 Mask         */
-#define SCT_OUTPUTSET11_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET11: SETn3 Position     */
-#define SCT_OUTPUTSET11_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn3_Pos)                     /*!< SCT OUTPUTSET11: SETn3 Mask         */
-#define SCT_OUTPUTSET11_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET11: SETn4 Position     */
-#define SCT_OUTPUTSET11_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn4_Pos)                     /*!< SCT OUTPUTSET11: SETn4 Mask         */
-#define SCT_OUTPUTSET11_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET11: SETn5 Position     */
-#define SCT_OUTPUTSET11_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn5_Pos)                     /*!< SCT OUTPUTSET11: SETn5 Mask         */
-#define SCT_OUTPUTSET11_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET11: SETn6 Position     */
-#define SCT_OUTPUTSET11_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn6_Pos)                     /*!< SCT OUTPUTSET11: SETn6 Mask         */
-#define SCT_OUTPUTSET11_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET11: SETn7 Position     */
-#define SCT_OUTPUTSET11_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn7_Pos)                     /*!< SCT OUTPUTSET11: SETn7 Mask         */
-#define SCT_OUTPUTSET11_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET11: SETn8 Position     */
-#define SCT_OUTPUTSET11_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn8_Pos)                     /*!< SCT OUTPUTSET11: SETn8 Mask         */
-#define SCT_OUTPUTSET11_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET11: SETn9 Position     */
-#define SCT_OUTPUTSET11_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn9_Pos)                     /*!< SCT OUTPUTSET11: SETn9 Mask         */
-#define SCT_OUTPUTSET11_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET11: SETn10 Position    */
-#define SCT_OUTPUTSET11_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn10_Pos)                    /*!< SCT OUTPUTSET11: SETn10 Mask        */
-#define SCT_OUTPUTSET11_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET11: SETn11 Position    */
-#define SCT_OUTPUTSET11_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn11_Pos)                    /*!< SCT OUTPUTSET11: SETn11 Mask        */
-#define SCT_OUTPUTSET11_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET11: SETn12 Position    */
-#define SCT_OUTPUTSET11_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn12_Pos)                    /*!< SCT OUTPUTSET11: SETn12 Mask        */
-#define SCT_OUTPUTSET11_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET11: SETn13 Position    */
-#define SCT_OUTPUTSET11_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn13_Pos)                    /*!< SCT OUTPUTSET11: SETn13 Mask        */
-#define SCT_OUTPUTSET11_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET11: SETn14 Position    */
-#define SCT_OUTPUTSET11_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn14_Pos)                    /*!< SCT OUTPUTSET11: SETn14 Mask        */
-#define SCT_OUTPUTSET11_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET11: SETn15 Position    */
-#define SCT_OUTPUTSET11_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn15_Pos)                    /*!< SCT OUTPUTSET11: SETn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTCLR11  ----------------------------------------
-#define SCT_OUTPUTCLR11_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR11: CLRn0 Position     */
-#define SCT_OUTPUTCLR11_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos)                     /*!< SCT OUTPUTCLR11: CLRn0 Mask         */
-#define SCT_OUTPUTCLR11_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR11: CLRn1 Position     */
-#define SCT_OUTPUTCLR11_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos)                     /*!< SCT OUTPUTCLR11: CLRn1 Mask         */
-#define SCT_OUTPUTCLR11_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR11: CLRn2 Position     */
-#define SCT_OUTPUTCLR11_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos)                     /*!< SCT OUTPUTCLR11: CLRn2 Mask         */
-#define SCT_OUTPUTCLR11_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR11: CLRn3 Position     */
-#define SCT_OUTPUTCLR11_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos)                     /*!< SCT OUTPUTCLR11: CLRn3 Mask         */
-#define SCT_OUTPUTCLR11_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR11: CLRn4 Position     */
-#define SCT_OUTPUTCLR11_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos)                     /*!< SCT OUTPUTCLR11: CLRn4 Mask         */
-#define SCT_OUTPUTCLR11_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR11: CLRn5 Position     */
-#define SCT_OUTPUTCLR11_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos)                     /*!< SCT OUTPUTCLR11: CLRn5 Mask         */
-#define SCT_OUTPUTCLR11_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR11: CLRn6 Position     */
-#define SCT_OUTPUTCLR11_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos)                     /*!< SCT OUTPUTCLR11: CLRn6 Mask         */
-#define SCT_OUTPUTCLR11_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR11: CLRn7 Position     */
-#define SCT_OUTPUTCLR11_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos)                     /*!< SCT OUTPUTCLR11: CLRn7 Mask         */
-#define SCT_OUTPUTCLR11_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR11: CLRn8 Position     */
-#define SCT_OUTPUTCLR11_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos)                     /*!< SCT OUTPUTCLR11: CLRn8 Mask         */
-#define SCT_OUTPUTCLR11_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR11: CLRn9 Position     */
-#define SCT_OUTPUTCLR11_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos)                     /*!< SCT OUTPUTCLR11: CLRn9 Mask         */
-#define SCT_OUTPUTCLR11_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR11: CLRn10 Position    */
-#define SCT_OUTPUTCLR11_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos)                    /*!< SCT OUTPUTCLR11: CLRn10 Mask        */
-#define SCT_OUTPUTCLR11_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR11: CLRn11 Position    */
-#define SCT_OUTPUTCLR11_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos)                    /*!< SCT OUTPUTCLR11: CLRn11 Mask        */
-#define SCT_OUTPUTCLR11_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR11: CLRn12 Position    */
-#define SCT_OUTPUTCLR11_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos)                    /*!< SCT OUTPUTCLR11: CLRn12 Mask        */
-#define SCT_OUTPUTCLR11_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR11: CLRn13 Position    */
-#define SCT_OUTPUTCLR11_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos)                    /*!< SCT OUTPUTCLR11: CLRn13 Mask        */
-#define SCT_OUTPUTCLR11_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR11: CLRn14 Position    */
-#define SCT_OUTPUTCLR11_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos)                    /*!< SCT OUTPUTCLR11: CLRn14 Mask        */
-#define SCT_OUTPUTCLR11_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR11: CLRn15 Position    */
-#define SCT_OUTPUTCLR11_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos)                    /*!< SCT OUTPUTCLR11: CLRn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTSET12  ----------------------------------------
-#define SCT_OUTPUTSET12_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET12: SETn0 Position     */
-#define SCT_OUTPUTSET12_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn0_Pos)                     /*!< SCT OUTPUTSET12: SETn0 Mask         */
-#define SCT_OUTPUTSET12_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET12: SETn1 Position     */
-#define SCT_OUTPUTSET12_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn1_Pos)                     /*!< SCT OUTPUTSET12: SETn1 Mask         */
-#define SCT_OUTPUTSET12_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET12: SETn2 Position     */
-#define SCT_OUTPUTSET12_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn2_Pos)                     /*!< SCT OUTPUTSET12: SETn2 Mask         */
-#define SCT_OUTPUTSET12_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET12: SETn3 Position     */
-#define SCT_OUTPUTSET12_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn3_Pos)                     /*!< SCT OUTPUTSET12: SETn3 Mask         */
-#define SCT_OUTPUTSET12_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET12: SETn4 Position     */
-#define SCT_OUTPUTSET12_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn4_Pos)                     /*!< SCT OUTPUTSET12: SETn4 Mask         */
-#define SCT_OUTPUTSET12_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET12: SETn5 Position     */
-#define SCT_OUTPUTSET12_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn5_Pos)                     /*!< SCT OUTPUTSET12: SETn5 Mask         */
-#define SCT_OUTPUTSET12_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET12: SETn6 Position     */
-#define SCT_OUTPUTSET12_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn6_Pos)                     /*!< SCT OUTPUTSET12: SETn6 Mask         */
-#define SCT_OUTPUTSET12_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET12: SETn7 Position     */
-#define SCT_OUTPUTSET12_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn7_Pos)                     /*!< SCT OUTPUTSET12: SETn7 Mask         */
-#define SCT_OUTPUTSET12_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET12: SETn8 Position     */
-#define SCT_OUTPUTSET12_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn8_Pos)                     /*!< SCT OUTPUTSET12: SETn8 Mask         */
-#define SCT_OUTPUTSET12_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET12: SETn9 Position     */
-#define SCT_OUTPUTSET12_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn9_Pos)                     /*!< SCT OUTPUTSET12: SETn9 Mask         */
-#define SCT_OUTPUTSET12_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET12: SETn10 Position    */
-#define SCT_OUTPUTSET12_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn10_Pos)                    /*!< SCT OUTPUTSET12: SETn10 Mask        */
-#define SCT_OUTPUTSET12_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET12: SETn11 Position    */
-#define SCT_OUTPUTSET12_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn11_Pos)                    /*!< SCT OUTPUTSET12: SETn11 Mask        */
-#define SCT_OUTPUTSET12_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET12: SETn12 Position    */
-#define SCT_OUTPUTSET12_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn12_Pos)                    /*!< SCT OUTPUTSET12: SETn12 Mask        */
-#define SCT_OUTPUTSET12_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET12: SETn13 Position    */
-#define SCT_OUTPUTSET12_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn13_Pos)                    /*!< SCT OUTPUTSET12: SETn13 Mask        */
-#define SCT_OUTPUTSET12_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET12: SETn14 Position    */
-#define SCT_OUTPUTSET12_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn14_Pos)                    /*!< SCT OUTPUTSET12: SETn14 Mask        */
-#define SCT_OUTPUTSET12_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET12: SETn15 Position    */
-#define SCT_OUTPUTSET12_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn15_Pos)                    /*!< SCT OUTPUTSET12: SETn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTCLR12  ----------------------------------------
-#define SCT_OUTPUTCLR12_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR12: CLRn0 Position     */
-#define SCT_OUTPUTCLR12_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos)                     /*!< SCT OUTPUTCLR12: CLRn0 Mask         */
-#define SCT_OUTPUTCLR12_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR12: CLRn1 Position     */
-#define SCT_OUTPUTCLR12_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos)                     /*!< SCT OUTPUTCLR12: CLRn1 Mask         */
-#define SCT_OUTPUTCLR12_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR12: CLRn2 Position     */
-#define SCT_OUTPUTCLR12_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos)                     /*!< SCT OUTPUTCLR12: CLRn2 Mask         */
-#define SCT_OUTPUTCLR12_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR12: CLRn3 Position     */
-#define SCT_OUTPUTCLR12_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos)                     /*!< SCT OUTPUTCLR12: CLRn3 Mask         */
-#define SCT_OUTPUTCLR12_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR12: CLRn4 Position     */
-#define SCT_OUTPUTCLR12_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos)                     /*!< SCT OUTPUTCLR12: CLRn4 Mask         */
-#define SCT_OUTPUTCLR12_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR12: CLRn5 Position     */
-#define SCT_OUTPUTCLR12_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos)                     /*!< SCT OUTPUTCLR12: CLRn5 Mask         */
-#define SCT_OUTPUTCLR12_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR12: CLRn6 Position     */
-#define SCT_OUTPUTCLR12_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos)                     /*!< SCT OUTPUTCLR12: CLRn6 Mask         */
-#define SCT_OUTPUTCLR12_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR12: CLRn7 Position     */
-#define SCT_OUTPUTCLR12_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos)                     /*!< SCT OUTPUTCLR12: CLRn7 Mask         */
-#define SCT_OUTPUTCLR12_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR12: CLRn8 Position     */
-#define SCT_OUTPUTCLR12_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos)                     /*!< SCT OUTPUTCLR12: CLRn8 Mask         */
-#define SCT_OUTPUTCLR12_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR12: CLRn9 Position     */
-#define SCT_OUTPUTCLR12_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos)                     /*!< SCT OUTPUTCLR12: CLRn9 Mask         */
-#define SCT_OUTPUTCLR12_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR12: CLRn10 Position    */
-#define SCT_OUTPUTCLR12_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos)                    /*!< SCT OUTPUTCLR12: CLRn10 Mask        */
-#define SCT_OUTPUTCLR12_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR12: CLRn11 Position    */
-#define SCT_OUTPUTCLR12_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos)                    /*!< SCT OUTPUTCLR12: CLRn11 Mask        */
-#define SCT_OUTPUTCLR12_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR12: CLRn12 Position    */
-#define SCT_OUTPUTCLR12_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos)                    /*!< SCT OUTPUTCLR12: CLRn12 Mask        */
-#define SCT_OUTPUTCLR12_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR12: CLRn13 Position    */
-#define SCT_OUTPUTCLR12_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos)                    /*!< SCT OUTPUTCLR12: CLRn13 Mask        */
-#define SCT_OUTPUTCLR12_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR12: CLRn14 Position    */
-#define SCT_OUTPUTCLR12_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos)                    /*!< SCT OUTPUTCLR12: CLRn14 Mask        */
-#define SCT_OUTPUTCLR12_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR12: CLRn15 Position    */
-#define SCT_OUTPUTCLR12_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos)                    /*!< SCT OUTPUTCLR12: CLRn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTSET13  ----------------------------------------
-#define SCT_OUTPUTSET13_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET13: SETn0 Position     */
-#define SCT_OUTPUTSET13_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn0_Pos)                     /*!< SCT OUTPUTSET13: SETn0 Mask         */
-#define SCT_OUTPUTSET13_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET13: SETn1 Position     */
-#define SCT_OUTPUTSET13_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn1_Pos)                     /*!< SCT OUTPUTSET13: SETn1 Mask         */
-#define SCT_OUTPUTSET13_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET13: SETn2 Position     */
-#define SCT_OUTPUTSET13_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn2_Pos)                     /*!< SCT OUTPUTSET13: SETn2 Mask         */
-#define SCT_OUTPUTSET13_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET13: SETn3 Position     */
-#define SCT_OUTPUTSET13_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn3_Pos)                     /*!< SCT OUTPUTSET13: SETn3 Mask         */
-#define SCT_OUTPUTSET13_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET13: SETn4 Position     */
-#define SCT_OUTPUTSET13_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn4_Pos)                     /*!< SCT OUTPUTSET13: SETn4 Mask         */
-#define SCT_OUTPUTSET13_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET13: SETn5 Position     */
-#define SCT_OUTPUTSET13_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn5_Pos)                     /*!< SCT OUTPUTSET13: SETn5 Mask         */
-#define SCT_OUTPUTSET13_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET13: SETn6 Position     */
-#define SCT_OUTPUTSET13_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn6_Pos)                     /*!< SCT OUTPUTSET13: SETn6 Mask         */
-#define SCT_OUTPUTSET13_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET13: SETn7 Position     */
-#define SCT_OUTPUTSET13_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn7_Pos)                     /*!< SCT OUTPUTSET13: SETn7 Mask         */
-#define SCT_OUTPUTSET13_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET13: SETn8 Position     */
-#define SCT_OUTPUTSET13_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn8_Pos)                     /*!< SCT OUTPUTSET13: SETn8 Mask         */
-#define SCT_OUTPUTSET13_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET13: SETn9 Position     */
-#define SCT_OUTPUTSET13_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn9_Pos)                     /*!< SCT OUTPUTSET13: SETn9 Mask         */
-#define SCT_OUTPUTSET13_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET13: SETn10 Position    */
-#define SCT_OUTPUTSET13_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn10_Pos)                    /*!< SCT OUTPUTSET13: SETn10 Mask        */
-#define SCT_OUTPUTSET13_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET13: SETn11 Position    */
-#define SCT_OUTPUTSET13_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn11_Pos)                    /*!< SCT OUTPUTSET13: SETn11 Mask        */
-#define SCT_OUTPUTSET13_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET13: SETn12 Position    */
-#define SCT_OUTPUTSET13_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn12_Pos)                    /*!< SCT OUTPUTSET13: SETn12 Mask        */
-#define SCT_OUTPUTSET13_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET13: SETn13 Position    */
-#define SCT_OUTPUTSET13_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn13_Pos)                    /*!< SCT OUTPUTSET13: SETn13 Mask        */
-#define SCT_OUTPUTSET13_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET13: SETn14 Position    */
-#define SCT_OUTPUTSET13_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn14_Pos)                    /*!< SCT OUTPUTSET13: SETn14 Mask        */
-#define SCT_OUTPUTSET13_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET13: SETn15 Position    */
-#define SCT_OUTPUTSET13_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn15_Pos)                    /*!< SCT OUTPUTSET13: SETn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTCLR13  ----------------------------------------
-#define SCT_OUTPUTCLR13_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR13: CLRn0 Position     */
-#define SCT_OUTPUTCLR13_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos)                     /*!< SCT OUTPUTCLR13: CLRn0 Mask         */
-#define SCT_OUTPUTCLR13_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR13: CLRn1 Position     */
-#define SCT_OUTPUTCLR13_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos)                     /*!< SCT OUTPUTCLR13: CLRn1 Mask         */
-#define SCT_OUTPUTCLR13_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR13: CLRn2 Position     */
-#define SCT_OUTPUTCLR13_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos)                     /*!< SCT OUTPUTCLR13: CLRn2 Mask         */
-#define SCT_OUTPUTCLR13_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR13: CLRn3 Position     */
-#define SCT_OUTPUTCLR13_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos)                     /*!< SCT OUTPUTCLR13: CLRn3 Mask         */
-#define SCT_OUTPUTCLR13_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR13: CLRn4 Position     */
-#define SCT_OUTPUTCLR13_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos)                     /*!< SCT OUTPUTCLR13: CLRn4 Mask         */
-#define SCT_OUTPUTCLR13_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR13: CLRn5 Position     */
-#define SCT_OUTPUTCLR13_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos)                     /*!< SCT OUTPUTCLR13: CLRn5 Mask         */
-#define SCT_OUTPUTCLR13_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR13: CLRn6 Position     */
-#define SCT_OUTPUTCLR13_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos)                     /*!< SCT OUTPUTCLR13: CLRn6 Mask         */
-#define SCT_OUTPUTCLR13_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR13: CLRn7 Position     */
-#define SCT_OUTPUTCLR13_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos)                     /*!< SCT OUTPUTCLR13: CLRn7 Mask         */
-#define SCT_OUTPUTCLR13_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR13: CLRn8 Position     */
-#define SCT_OUTPUTCLR13_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos)                     /*!< SCT OUTPUTCLR13: CLRn8 Mask         */
-#define SCT_OUTPUTCLR13_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR13: CLRn9 Position     */
-#define SCT_OUTPUTCLR13_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos)                     /*!< SCT OUTPUTCLR13: CLRn9 Mask         */
-#define SCT_OUTPUTCLR13_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR13: CLRn10 Position    */
-#define SCT_OUTPUTCLR13_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos)                    /*!< SCT OUTPUTCLR13: CLRn10 Mask        */
-#define SCT_OUTPUTCLR13_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR13: CLRn11 Position    */
-#define SCT_OUTPUTCLR13_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos)                    /*!< SCT OUTPUTCLR13: CLRn11 Mask        */
-#define SCT_OUTPUTCLR13_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR13: CLRn12 Position    */
-#define SCT_OUTPUTCLR13_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos)                    /*!< SCT OUTPUTCLR13: CLRn12 Mask        */
-#define SCT_OUTPUTCLR13_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR13: CLRn13 Position    */
-#define SCT_OUTPUTCLR13_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos)                    /*!< SCT OUTPUTCLR13: CLRn13 Mask        */
-#define SCT_OUTPUTCLR13_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR13: CLRn14 Position    */
-#define SCT_OUTPUTCLR13_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos)                    /*!< SCT OUTPUTCLR13: CLRn14 Mask        */
-#define SCT_OUTPUTCLR13_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR13: CLRn15 Position    */
-#define SCT_OUTPUTCLR13_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos)                    /*!< SCT OUTPUTCLR13: CLRn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTSET14  ----------------------------------------
-#define SCT_OUTPUTSET14_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET14: SETn0 Position     */
-#define SCT_OUTPUTSET14_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn0_Pos)                     /*!< SCT OUTPUTSET14: SETn0 Mask         */
-#define SCT_OUTPUTSET14_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET14: SETn1 Position     */
-#define SCT_OUTPUTSET14_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn1_Pos)                     /*!< SCT OUTPUTSET14: SETn1 Mask         */
-#define SCT_OUTPUTSET14_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET14: SETn2 Position     */
-#define SCT_OUTPUTSET14_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn2_Pos)                     /*!< SCT OUTPUTSET14: SETn2 Mask         */
-#define SCT_OUTPUTSET14_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET14: SETn3 Position     */
-#define SCT_OUTPUTSET14_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn3_Pos)                     /*!< SCT OUTPUTSET14: SETn3 Mask         */
-#define SCT_OUTPUTSET14_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET14: SETn4 Position     */
-#define SCT_OUTPUTSET14_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn4_Pos)                     /*!< SCT OUTPUTSET14: SETn4 Mask         */
-#define SCT_OUTPUTSET14_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET14: SETn5 Position     */
-#define SCT_OUTPUTSET14_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn5_Pos)                     /*!< SCT OUTPUTSET14: SETn5 Mask         */
-#define SCT_OUTPUTSET14_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET14: SETn6 Position     */
-#define SCT_OUTPUTSET14_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn6_Pos)                     /*!< SCT OUTPUTSET14: SETn6 Mask         */
-#define SCT_OUTPUTSET14_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET14: SETn7 Position     */
-#define SCT_OUTPUTSET14_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn7_Pos)                     /*!< SCT OUTPUTSET14: SETn7 Mask         */
-#define SCT_OUTPUTSET14_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET14: SETn8 Position     */
-#define SCT_OUTPUTSET14_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn8_Pos)                     /*!< SCT OUTPUTSET14: SETn8 Mask         */
-#define SCT_OUTPUTSET14_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET14: SETn9 Position     */
-#define SCT_OUTPUTSET14_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn9_Pos)                     /*!< SCT OUTPUTSET14: SETn9 Mask         */
-#define SCT_OUTPUTSET14_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET14: SETn10 Position    */
-#define SCT_OUTPUTSET14_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn10_Pos)                    /*!< SCT OUTPUTSET14: SETn10 Mask        */
-#define SCT_OUTPUTSET14_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET14: SETn11 Position    */
-#define SCT_OUTPUTSET14_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn11_Pos)                    /*!< SCT OUTPUTSET14: SETn11 Mask        */
-#define SCT_OUTPUTSET14_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET14: SETn12 Position    */
-#define SCT_OUTPUTSET14_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn12_Pos)                    /*!< SCT OUTPUTSET14: SETn12 Mask        */
-#define SCT_OUTPUTSET14_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET14: SETn13 Position    */
-#define SCT_OUTPUTSET14_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn13_Pos)                    /*!< SCT OUTPUTSET14: SETn13 Mask        */
-#define SCT_OUTPUTSET14_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET14: SETn14 Position    */
-#define SCT_OUTPUTSET14_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn14_Pos)                    /*!< SCT OUTPUTSET14: SETn14 Mask        */
-#define SCT_OUTPUTSET14_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET14: SETn15 Position    */
-#define SCT_OUTPUTSET14_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn15_Pos)                    /*!< SCT OUTPUTSET14: SETn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTCLR14  ----------------------------------------
-#define SCT_OUTPUTCLR14_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR14: CLRn0 Position     */
-#define SCT_OUTPUTCLR14_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos)                     /*!< SCT OUTPUTCLR14: CLRn0 Mask         */
-#define SCT_OUTPUTCLR14_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR14: CLRn1 Position     */
-#define SCT_OUTPUTCLR14_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos)                     /*!< SCT OUTPUTCLR14: CLRn1 Mask         */
-#define SCT_OUTPUTCLR14_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR14: CLRn2 Position     */
-#define SCT_OUTPUTCLR14_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos)                     /*!< SCT OUTPUTCLR14: CLRn2 Mask         */
-#define SCT_OUTPUTCLR14_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR14: CLRn3 Position     */
-#define SCT_OUTPUTCLR14_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos)                     /*!< SCT OUTPUTCLR14: CLRn3 Mask         */
-#define SCT_OUTPUTCLR14_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR14: CLRn4 Position     */
-#define SCT_OUTPUTCLR14_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos)                     /*!< SCT OUTPUTCLR14: CLRn4 Mask         */
-#define SCT_OUTPUTCLR14_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR14: CLRn5 Position     */
-#define SCT_OUTPUTCLR14_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos)                     /*!< SCT OUTPUTCLR14: CLRn5 Mask         */
-#define SCT_OUTPUTCLR14_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR14: CLRn6 Position     */
-#define SCT_OUTPUTCLR14_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos)                     /*!< SCT OUTPUTCLR14: CLRn6 Mask         */
-#define SCT_OUTPUTCLR14_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR14: CLRn7 Position     */
-#define SCT_OUTPUTCLR14_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos)                     /*!< SCT OUTPUTCLR14: CLRn7 Mask         */
-#define SCT_OUTPUTCLR14_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR14: CLRn8 Position     */
-#define SCT_OUTPUTCLR14_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos)                     /*!< SCT OUTPUTCLR14: CLRn8 Mask         */
-#define SCT_OUTPUTCLR14_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR14: CLRn9 Position     */
-#define SCT_OUTPUTCLR14_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos)                     /*!< SCT OUTPUTCLR14: CLRn9 Mask         */
-#define SCT_OUTPUTCLR14_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR14: CLRn10 Position    */
-#define SCT_OUTPUTCLR14_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos)                    /*!< SCT OUTPUTCLR14: CLRn10 Mask        */
-#define SCT_OUTPUTCLR14_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR14: CLRn11 Position    */
-#define SCT_OUTPUTCLR14_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos)                    /*!< SCT OUTPUTCLR14: CLRn11 Mask        */
-#define SCT_OUTPUTCLR14_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR14: CLRn12 Position    */
-#define SCT_OUTPUTCLR14_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos)                    /*!< SCT OUTPUTCLR14: CLRn12 Mask        */
-#define SCT_OUTPUTCLR14_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR14: CLRn13 Position    */
-#define SCT_OUTPUTCLR14_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos)                    /*!< SCT OUTPUTCLR14: CLRn13 Mask        */
-#define SCT_OUTPUTCLR14_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR14: CLRn14 Position    */
-#define SCT_OUTPUTCLR14_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos)                    /*!< SCT OUTPUTCLR14: CLRn14 Mask        */
-#define SCT_OUTPUTCLR14_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR14: CLRn15 Position    */
-#define SCT_OUTPUTCLR14_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos)                    /*!< SCT OUTPUTCLR14: CLRn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTSET15  ----------------------------------------
-#define SCT_OUTPUTSET15_SETn0_Pos                             0                                                         /*!< SCT OUTPUTSET15: SETn0 Position     */
-#define SCT_OUTPUTSET15_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn0_Pos)                     /*!< SCT OUTPUTSET15: SETn0 Mask         */
-#define SCT_OUTPUTSET15_SETn1_Pos                             1                                                         /*!< SCT OUTPUTSET15: SETn1 Position     */
-#define SCT_OUTPUTSET15_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn1_Pos)                     /*!< SCT OUTPUTSET15: SETn1 Mask         */
-#define SCT_OUTPUTSET15_SETn2_Pos                             2                                                         /*!< SCT OUTPUTSET15: SETn2 Position     */
-#define SCT_OUTPUTSET15_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn2_Pos)                     /*!< SCT OUTPUTSET15: SETn2 Mask         */
-#define SCT_OUTPUTSET15_SETn3_Pos                             3                                                         /*!< SCT OUTPUTSET15: SETn3 Position     */
-#define SCT_OUTPUTSET15_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn3_Pos)                     /*!< SCT OUTPUTSET15: SETn3 Mask         */
-#define SCT_OUTPUTSET15_SETn4_Pos                             4                                                         /*!< SCT OUTPUTSET15: SETn4 Position     */
-#define SCT_OUTPUTSET15_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn4_Pos)                     /*!< SCT OUTPUTSET15: SETn4 Mask         */
-#define SCT_OUTPUTSET15_SETn5_Pos                             5                                                         /*!< SCT OUTPUTSET15: SETn5 Position     */
-#define SCT_OUTPUTSET15_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn5_Pos)                     /*!< SCT OUTPUTSET15: SETn5 Mask         */
-#define SCT_OUTPUTSET15_SETn6_Pos                             6                                                         /*!< SCT OUTPUTSET15: SETn6 Position     */
-#define SCT_OUTPUTSET15_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn6_Pos)                     /*!< SCT OUTPUTSET15: SETn6 Mask         */
-#define SCT_OUTPUTSET15_SETn7_Pos                             7                                                         /*!< SCT OUTPUTSET15: SETn7 Position     */
-#define SCT_OUTPUTSET15_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn7_Pos)                     /*!< SCT OUTPUTSET15: SETn7 Mask         */
-#define SCT_OUTPUTSET15_SETn8_Pos                             8                                                         /*!< SCT OUTPUTSET15: SETn8 Position     */
-#define SCT_OUTPUTSET15_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn8_Pos)                     /*!< SCT OUTPUTSET15: SETn8 Mask         */
-#define SCT_OUTPUTSET15_SETn9_Pos                             9                                                         /*!< SCT OUTPUTSET15: SETn9 Position     */
-#define SCT_OUTPUTSET15_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn9_Pos)                     /*!< SCT OUTPUTSET15: SETn9 Mask         */
-#define SCT_OUTPUTSET15_SETn10_Pos                            10                                                        /*!< SCT OUTPUTSET15: SETn10 Position    */
-#define SCT_OUTPUTSET15_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn10_Pos)                    /*!< SCT OUTPUTSET15: SETn10 Mask        */
-#define SCT_OUTPUTSET15_SETn11_Pos                            11                                                        /*!< SCT OUTPUTSET15: SETn11 Position    */
-#define SCT_OUTPUTSET15_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn11_Pos)                    /*!< SCT OUTPUTSET15: SETn11 Mask        */
-#define SCT_OUTPUTSET15_SETn12_Pos                            12                                                        /*!< SCT OUTPUTSET15: SETn12 Position    */
-#define SCT_OUTPUTSET15_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn12_Pos)                    /*!< SCT OUTPUTSET15: SETn12 Mask        */
-#define SCT_OUTPUTSET15_SETn13_Pos                            13                                                        /*!< SCT OUTPUTSET15: SETn13 Position    */
-#define SCT_OUTPUTSET15_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn13_Pos)                    /*!< SCT OUTPUTSET15: SETn13 Mask        */
-#define SCT_OUTPUTSET15_SETn14_Pos                            14                                                        /*!< SCT OUTPUTSET15: SETn14 Position    */
-#define SCT_OUTPUTSET15_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn14_Pos)                    /*!< SCT OUTPUTSET15: SETn14 Mask        */
-#define SCT_OUTPUTSET15_SETn15_Pos                            15                                                        /*!< SCT OUTPUTSET15: SETn15 Position    */
-#define SCT_OUTPUTSET15_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn15_Pos)                    /*!< SCT OUTPUTSET15: SETn15 Mask        */
-
-// -------------------------------------  SCT_OUTPUTCLR15  ----------------------------------------
-#define SCT_OUTPUTCLR15_CLRn0_Pos                             0                                                         /*!< SCT OUTPUTCLR15: CLRn0 Position     */
-#define SCT_OUTPUTCLR15_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos)                     /*!< SCT OUTPUTCLR15: CLRn0 Mask         */
-#define SCT_OUTPUTCLR15_CLRn1_Pos                             1                                                         /*!< SCT OUTPUTCLR15: CLRn1 Position     */
-#define SCT_OUTPUTCLR15_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos)                     /*!< SCT OUTPUTCLR15: CLRn1 Mask         */
-#define SCT_OUTPUTCLR15_CLRn2_Pos                             2                                                         /*!< SCT OUTPUTCLR15: CLRn2 Position     */
-#define SCT_OUTPUTCLR15_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos)                     /*!< SCT OUTPUTCLR15: CLRn2 Mask         */
-#define SCT_OUTPUTCLR15_CLRn3_Pos                             3                                                         /*!< SCT OUTPUTCLR15: CLRn3 Position     */
-#define SCT_OUTPUTCLR15_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos)                     /*!< SCT OUTPUTCLR15: CLRn3 Mask         */
-#define SCT_OUTPUTCLR15_CLRn4_Pos                             4                                                         /*!< SCT OUTPUTCLR15: CLRn4 Position     */
-#define SCT_OUTPUTCLR15_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos)                     /*!< SCT OUTPUTCLR15: CLRn4 Mask         */
-#define SCT_OUTPUTCLR15_CLRn5_Pos                             5                                                         /*!< SCT OUTPUTCLR15: CLRn5 Position     */
-#define SCT_OUTPUTCLR15_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos)                     /*!< SCT OUTPUTCLR15: CLRn5 Mask         */
-#define SCT_OUTPUTCLR15_CLRn6_Pos                             6                                                         /*!< SCT OUTPUTCLR15: CLRn6 Position     */
-#define SCT_OUTPUTCLR15_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos)                     /*!< SCT OUTPUTCLR15: CLRn6 Mask         */
-#define SCT_OUTPUTCLR15_CLRn7_Pos                             7                                                         /*!< SCT OUTPUTCLR15: CLRn7 Position     */
-#define SCT_OUTPUTCLR15_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos)                     /*!< SCT OUTPUTCLR15: CLRn7 Mask         */
-#define SCT_OUTPUTCLR15_CLRn8_Pos                             8                                                         /*!< SCT OUTPUTCLR15: CLRn8 Position     */
-#define SCT_OUTPUTCLR15_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos)                     /*!< SCT OUTPUTCLR15: CLRn8 Mask         */
-#define SCT_OUTPUTCLR15_CLRn9_Pos                             9                                                         /*!< SCT OUTPUTCLR15: CLRn9 Position     */
-#define SCT_OUTPUTCLR15_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos)                     /*!< SCT OUTPUTCLR15: CLRn9 Mask         */
-#define SCT_OUTPUTCLR15_CLRn10_Pos                            10                                                        /*!< SCT OUTPUTCLR15: CLRn10 Position    */
-#define SCT_OUTPUTCLR15_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos)                    /*!< SCT OUTPUTCLR15: CLRn10 Mask        */
-#define SCT_OUTPUTCLR15_CLRn11_Pos                            11                                                        /*!< SCT OUTPUTCLR15: CLRn11 Position    */
-#define SCT_OUTPUTCLR15_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos)                    /*!< SCT OUTPUTCLR15: CLRn11 Mask        */
-#define SCT_OUTPUTCLR15_CLRn12_Pos                            12                                                        /*!< SCT OUTPUTCLR15: CLRn12 Position    */
-#define SCT_OUTPUTCLR15_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos)                    /*!< SCT OUTPUTCLR15: CLRn12 Mask        */
-#define SCT_OUTPUTCLR15_CLRn13_Pos                            13                                                        /*!< SCT OUTPUTCLR15: CLRn13 Position    */
-#define SCT_OUTPUTCLR15_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos)                    /*!< SCT OUTPUTCLR15: CLRn13 Mask        */
-#define SCT_OUTPUTCLR15_CLRn14_Pos                            14                                                        /*!< SCT OUTPUTCLR15: CLRn14 Position    */
-#define SCT_OUTPUTCLR15_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos)                    /*!< SCT OUTPUTCLR15: CLRn14 Mask        */
-#define SCT_OUTPUTCLR15_CLRn15_Pos                            15                                                        /*!< SCT OUTPUTCLR15: CLRn15 Position    */
-#define SCT_OUTPUTCLR15_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos)                    /*!< SCT OUTPUTCLR15: CLRn15 Mask        */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 GPDMA Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// --------------------------------------  GPDMA_INTSTAT  -----------------------------------------
-#define GPDMA_INTSTAT_INTSTAT0_Pos                            0                                                         /*!< GPDMA INTSTAT: INTSTAT0 Position    */
-#define GPDMA_INTSTAT_INTSTAT0_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos)                    /*!< GPDMA INTSTAT: INTSTAT0 Mask        */
-#define GPDMA_INTSTAT_INTSTAT1_Pos                            1                                                         /*!< GPDMA INTSTAT: INTSTAT1 Position    */
-#define GPDMA_INTSTAT_INTSTAT1_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos)                    /*!< GPDMA INTSTAT: INTSTAT1 Mask        */
-#define GPDMA_INTSTAT_INTSTAT2_Pos                            2                                                         /*!< GPDMA INTSTAT: INTSTAT2 Position    */
-#define GPDMA_INTSTAT_INTSTAT2_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos)                    /*!< GPDMA INTSTAT: INTSTAT2 Mask        */
-#define GPDMA_INTSTAT_INTSTAT3_Pos                            3                                                         /*!< GPDMA INTSTAT: INTSTAT3 Position    */
-#define GPDMA_INTSTAT_INTSTAT3_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos)                    /*!< GPDMA INTSTAT: INTSTAT3 Mask        */
-#define GPDMA_INTSTAT_INTSTAT4_Pos                            4                                                         /*!< GPDMA INTSTAT: INTSTAT4 Position    */
-#define GPDMA_INTSTAT_INTSTAT4_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos)                    /*!< GPDMA INTSTAT: INTSTAT4 Mask        */
-#define GPDMA_INTSTAT_INTSTAT5_Pos                            5                                                         /*!< GPDMA INTSTAT: INTSTAT5 Position    */
-#define GPDMA_INTSTAT_INTSTAT5_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos)                    /*!< GPDMA INTSTAT: INTSTAT5 Mask        */
-#define GPDMA_INTSTAT_INTSTAT6_Pos                            6                                                         /*!< GPDMA INTSTAT: INTSTAT6 Position    */
-#define GPDMA_INTSTAT_INTSTAT6_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos)                    /*!< GPDMA INTSTAT: INTSTAT6 Mask        */
-#define GPDMA_INTSTAT_INTSTAT7_Pos                            7                                                         /*!< GPDMA INTSTAT: INTSTAT7 Position    */
-#define GPDMA_INTSTAT_INTSTAT7_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos)                    /*!< GPDMA INTSTAT: INTSTAT7 Mask        */
-
-// -------------------------------------  GPDMA_INTTCSTAT  ----------------------------------------
-#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos                        0                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */
-#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask    */
-#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos                        1                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */
-#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask    */
-#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos                        2                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */
-#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask    */
-#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos                        3                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */
-#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask    */
-#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos                        4                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */
-#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask    */
-#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos                        5                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */
-#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask    */
-#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos                        6                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */
-#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask    */
-#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos                        7                                                         /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */
-#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos)                /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask    */
-
-// ------------------------------------  GPDMA_INTTCCLEAR  ----------------------------------------
-#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos                      0                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask  */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos                      1                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask  */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos                      2                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask  */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos                      3                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask  */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos                      4                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask  */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos                      5                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask  */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos                      6                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask  */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos                      7                                                         /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */
-#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos)              /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask  */
-
-// ------------------------------------  GPDMA_INTERRSTAT  ----------------------------------------
-#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos                      0                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */
-#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask  */
-#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos                      1                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */
-#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask  */
-#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos                      2                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */
-#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask  */
-#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos                      3                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */
-#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask  */
-#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos                      4                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */
-#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask  */
-#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos                      5                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */
-#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask  */
-#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos                      6                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */
-#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask  */
-#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos                      7                                                         /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */
-#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos)              /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask  */
-
-// -------------------------------------  GPDMA_INTERRCLR  ----------------------------------------
-#define GPDMA_INTERRCLR_INTERRCLR0_Pos                        0                                                         /*!< GPDMA INTERRCLR: INTERRCLR0 Position */
-#define GPDMA_INTERRCLR_INTERRCLR0_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR0 Mask    */
-#define GPDMA_INTERRCLR_INTERRCLR1_Pos                        1                                                         /*!< GPDMA INTERRCLR: INTERRCLR1 Position */
-#define GPDMA_INTERRCLR_INTERRCLR1_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR1 Mask    */
-#define GPDMA_INTERRCLR_INTERRCLR2_Pos                        2                                                         /*!< GPDMA INTERRCLR: INTERRCLR2 Position */
-#define GPDMA_INTERRCLR_INTERRCLR2_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR2 Mask    */
-#define GPDMA_INTERRCLR_INTERRCLR3_Pos                        3                                                         /*!< GPDMA INTERRCLR: INTERRCLR3 Position */
-#define GPDMA_INTERRCLR_INTERRCLR3_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR3 Mask    */
-#define GPDMA_INTERRCLR_INTERRCLR4_Pos                        4                                                         /*!< GPDMA INTERRCLR: INTERRCLR4 Position */
-#define GPDMA_INTERRCLR_INTERRCLR4_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR4 Mask    */
-#define GPDMA_INTERRCLR_INTERRCLR5_Pos                        5                                                         /*!< GPDMA INTERRCLR: INTERRCLR5 Position */
-#define GPDMA_INTERRCLR_INTERRCLR5_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR5 Mask    */
-#define GPDMA_INTERRCLR_INTERRCLR6_Pos                        6                                                         /*!< GPDMA INTERRCLR: INTERRCLR6 Position */
-#define GPDMA_INTERRCLR_INTERRCLR6_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR6 Mask    */
-#define GPDMA_INTERRCLR_INTERRCLR7_Pos                        7                                                         /*!< GPDMA INTERRCLR: INTERRCLR7 Position */
-#define GPDMA_INTERRCLR_INTERRCLR7_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos)                /*!< GPDMA INTERRCLR: INTERRCLR7 Mask    */
-
-// -----------------------------------  GPDMA_RAWINTTCSTAT  ---------------------------------------
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos                  0                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos                  1                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos                  2                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos                  3                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos                  4                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos                  5                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos                  6                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos                  7                                                         /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos)          /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */
-
-// -----------------------------------  GPDMA_RAWINTERRSTAT  --------------------------------------
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos                0                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos                1                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos                2                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos                3                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos                4                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos                5                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos                6                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos                7                                                         /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos)        /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */
-
-// -------------------------------------  GPDMA_ENBLDCHNS  ----------------------------------------
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos                  0                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos                  1                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos                  2                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos                  3                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos                  4                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos                  5                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos                  6                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos                  7                                                         /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos)          /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */
-
-// -------------------------------------  GPDMA_SOFTBREQ  -----------------------------------------
-#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos                          0                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos                          1                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos                          2                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos                          3                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos                          4                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos                          5                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos                          6                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos                          7                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos                          8                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos                          9                                                         /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position  */
-#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos)                  /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask      */
-#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos                         10                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */
-#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask     */
-#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos                         11                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */
-#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask     */
-#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos                         12                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */
-#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask     */
-#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos                         13                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */
-#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask     */
-#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos                         14                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */
-#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask     */
-#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos                         15                                                        /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */
-#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos)                 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask     */
-
-// -------------------------------------  GPDMA_SOFTSREQ  -----------------------------------------
-#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos                          0                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos                          1                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos                          2                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos                          3                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos                          4                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos                          5                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos                          6                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos                          7                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos                          8                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos                          9                                                         /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position  */
-#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos)                  /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask      */
-#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos                         10                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */
-#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask     */
-#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos                         11                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */
-#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask     */
-#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos                         12                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */
-#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask     */
-#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos                         13                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */
-#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask     */
-#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos                         14                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */
-#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask     */
-#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos                         15                                                        /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */
-#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos)                 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask     */
-
-// -------------------------------------  GPDMA_SOFTLBREQ  ----------------------------------------
-#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos                        0                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos                        1                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos                        2                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos                        3                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos                        4                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos                        5                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos                        6                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos                        7                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos                        8                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos                        9                                                         /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos)                /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask    */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos                       10                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask   */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos                       11                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask   */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos                       12                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask   */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos                       13                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask   */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos                       14                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask   */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos                       15                                                        /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */
-#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos)               /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask   */
-
-// -------------------------------------  GPDMA_SOFTLSREQ  ----------------------------------------
-#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos                        0                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos                        1                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos                        2                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos                        3                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos                        4                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos                        5                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos                        6                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos                        7                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos                        8                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos                        9                                                         /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos)                /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask    */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos                       10                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask   */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos                       11                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask   */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos                       12                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask   */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos                       13                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask   */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos                       14                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask   */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos                       15                                                        /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */
-#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos)               /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask   */
-
-// --------------------------------------  GPDMA_CONFIG  ------------------------------------------
-#define GPDMA_CONFIG_E_Pos                                    0                                                         /*!< GPDMA CONFIG: E Position            */
-#define GPDMA_CONFIG_E_Msk                                    (0x01UL << GPDMA_CONFIG_E_Pos)                            /*!< GPDMA CONFIG: E Mask                */
-#define GPDMA_CONFIG_M0_Pos                                   1                                                         /*!< GPDMA CONFIG: M0 Position           */
-#define GPDMA_CONFIG_M0_Msk                                   (0x01UL << GPDMA_CONFIG_M0_Pos)                           /*!< GPDMA CONFIG: M0 Mask               */
-#define GPDMA_CONFIG_M1_Pos                                   2                                                         /*!< GPDMA CONFIG: M1 Position           */
-#define GPDMA_CONFIG_M1_Msk                                   (0x01UL << GPDMA_CONFIG_M1_Pos)                           /*!< GPDMA CONFIG: M1 Mask               */
-
-// ---------------------------------------  GPDMA_SYNC  -------------------------------------------
-#define GPDMA_SYNC_DMACSYNC0_Pos                              0                                                         /*!< GPDMA SYNC: DMACSYNC0 Position      */
-#define GPDMA_SYNC_DMACSYNC0_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos)                      /*!< GPDMA SYNC: DMACSYNC0 Mask          */
-#define GPDMA_SYNC_DMACSYNC1_Pos                              1                                                         /*!< GPDMA SYNC: DMACSYNC1 Position      */
-#define GPDMA_SYNC_DMACSYNC1_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos)                      /*!< GPDMA SYNC: DMACSYNC1 Mask          */
-#define GPDMA_SYNC_DMACSYNC2_Pos                              2                                                         /*!< GPDMA SYNC: DMACSYNC2 Position      */
-#define GPDMA_SYNC_DMACSYNC2_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos)                      /*!< GPDMA SYNC: DMACSYNC2 Mask          */
-#define GPDMA_SYNC_DMACSYNC3_Pos                              3                                                         /*!< GPDMA SYNC: DMACSYNC3 Position      */
-#define GPDMA_SYNC_DMACSYNC3_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos)                      /*!< GPDMA SYNC: DMACSYNC3 Mask          */
-#define GPDMA_SYNC_DMACSYNC4_Pos                              4                                                         /*!< GPDMA SYNC: DMACSYNC4 Position      */
-#define GPDMA_SYNC_DMACSYNC4_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos)                      /*!< GPDMA SYNC: DMACSYNC4 Mask          */
-#define GPDMA_SYNC_DMACSYNC5_Pos                              5                                                         /*!< GPDMA SYNC: DMACSYNC5 Position      */
-#define GPDMA_SYNC_DMACSYNC5_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos)                      /*!< GPDMA SYNC: DMACSYNC5 Mask          */
-#define GPDMA_SYNC_DMACSYNC6_Pos                              6                                                         /*!< GPDMA SYNC: DMACSYNC6 Position      */
-#define GPDMA_SYNC_DMACSYNC6_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos)                      /*!< GPDMA SYNC: DMACSYNC6 Mask          */
-#define GPDMA_SYNC_DMACSYNC7_Pos                              7                                                         /*!< GPDMA SYNC: DMACSYNC7 Position      */
-#define GPDMA_SYNC_DMACSYNC7_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos)                      /*!< GPDMA SYNC: DMACSYNC7 Mask          */
-#define GPDMA_SYNC_DMACSYNC8_Pos                              8                                                         /*!< GPDMA SYNC: DMACSYNC8 Position      */
-#define GPDMA_SYNC_DMACSYNC8_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos)                      /*!< GPDMA SYNC: DMACSYNC8 Mask          */
-#define GPDMA_SYNC_DMACSYNC9_Pos                              9                                                         /*!< GPDMA SYNC: DMACSYNC9 Position      */
-#define GPDMA_SYNC_DMACSYNC9_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos)                      /*!< GPDMA SYNC: DMACSYNC9 Mask          */
-#define GPDMA_SYNC_DMACSYNC10_Pos                             10                                                        /*!< GPDMA SYNC: DMACSYNC10 Position     */
-#define GPDMA_SYNC_DMACSYNC10_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos)                     /*!< GPDMA SYNC: DMACSYNC10 Mask         */
-#define GPDMA_SYNC_DMACSYNC11_Pos                             11                                                        /*!< GPDMA SYNC: DMACSYNC11 Position     */
-#define GPDMA_SYNC_DMACSYNC11_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos)                     /*!< GPDMA SYNC: DMACSYNC11 Mask         */
-#define GPDMA_SYNC_DMACSYNC12_Pos                             12                                                        /*!< GPDMA SYNC: DMACSYNC12 Position     */
-#define GPDMA_SYNC_DMACSYNC12_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos)                     /*!< GPDMA SYNC: DMACSYNC12 Mask         */
-#define GPDMA_SYNC_DMACSYNC13_Pos                             13                                                        /*!< GPDMA SYNC: DMACSYNC13 Position     */
-#define GPDMA_SYNC_DMACSYNC13_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos)                     /*!< GPDMA SYNC: DMACSYNC13 Mask         */
-#define GPDMA_SYNC_DMACSYNC14_Pos                             14                                                        /*!< GPDMA SYNC: DMACSYNC14 Position     */
-#define GPDMA_SYNC_DMACSYNC14_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos)                     /*!< GPDMA SYNC: DMACSYNC14 Mask         */
-#define GPDMA_SYNC_DMACSYNC15_Pos                             15                                                        /*!< GPDMA SYNC: DMACSYNC15 Position     */
-#define GPDMA_SYNC_DMACSYNC15_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos)                     /*!< GPDMA SYNC: DMACSYNC15 Mask         */
-
-// -------------------------------------  GPDMA_C0SRCADDR  ----------------------------------------
-#define GPDMA_C0SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C0SRCADDR: SRCADDR Position   */
-#define GPDMA_C0SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos)             /*!< GPDMA C0SRCADDR: SRCADDR Mask       */
-
-// ------------------------------------  GPDMA_C0DESTADDR  ----------------------------------------
-#define GPDMA_C0DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C0DESTADDR: DESTADDR Position */
-#define GPDMA_C0DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos)           /*!< GPDMA C0DESTADDR: DESTADDR Mask     */
-
-// ---------------------------------------  GPDMA_C0LLI  ------------------------------------------
-#define GPDMA_C0LLI_LM_Pos                                    0                                                         /*!< GPDMA C0LLI: LM Position            */
-#define GPDMA_C0LLI_LM_Msk                                    (0x01UL << GPDMA_C0LLI_LM_Pos)                            /*!< GPDMA C0LLI: LM Mask                */
-#define GPDMA_C0LLI_R_Pos                                     1                                                         /*!< GPDMA C0LLI: R Position             */
-#define GPDMA_C0LLI_R_Msk                                     (0x01UL << GPDMA_C0LLI_R_Pos)                             /*!< GPDMA C0LLI: R Mask                 */
-#define GPDMA_C0LLI_LLI_Pos                                   2                                                         /*!< GPDMA C0LLI: LLI Position           */
-#define GPDMA_C0LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos)                     /*!< GPDMA C0LLI: LLI Mask               */
-
-// -------------------------------------  GPDMA_C0CONTROL  ----------------------------------------
-#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */
-#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask  */
-#define GPDMA_C0CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C0CONTROL: SBSIZE Position    */
-#define GPDMA_C0CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos)                    /*!< GPDMA C0CONTROL: SBSIZE Mask        */
-#define GPDMA_C0CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C0CONTROL: DBSIZE Position    */
-#define GPDMA_C0CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos)                    /*!< GPDMA C0CONTROL: DBSIZE Mask        */
-#define GPDMA_C0CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C0CONTROL: SWIDTH Position    */
-#define GPDMA_C0CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos)                    /*!< GPDMA C0CONTROL: SWIDTH Mask        */
-#define GPDMA_C0CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C0CONTROL: DWIDTH Position    */
-#define GPDMA_C0CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos)                    /*!< GPDMA C0CONTROL: DWIDTH Mask        */
-#define GPDMA_C0CONTROL_S_Pos                                 24                                                        /*!< GPDMA C0CONTROL: S Position         */
-#define GPDMA_C0CONTROL_S_Msk                                 (0x01UL << GPDMA_C0CONTROL_S_Pos)                         /*!< GPDMA C0CONTROL: S Mask             */
-#define GPDMA_C0CONTROL_D_Pos                                 25                                                        /*!< GPDMA C0CONTROL: D Position         */
-#define GPDMA_C0CONTROL_D_Msk                                 (0x01UL << GPDMA_C0CONTROL_D_Pos)                         /*!< GPDMA C0CONTROL: D Mask             */
-#define GPDMA_C0CONTROL_SI_Pos                                26                                                        /*!< GPDMA C0CONTROL: SI Position        */
-#define GPDMA_C0CONTROL_SI_Msk                                (0x01UL << GPDMA_C0CONTROL_SI_Pos)                        /*!< GPDMA C0CONTROL: SI Mask            */
-#define GPDMA_C0CONTROL_DI_Pos                                27                                                        /*!< GPDMA C0CONTROL: DI Position        */
-#define GPDMA_C0CONTROL_DI_Msk                                (0x01UL << GPDMA_C0CONTROL_DI_Pos)                        /*!< GPDMA C0CONTROL: DI Mask            */
-#define GPDMA_C0CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C0CONTROL: PROT1 Position     */
-#define GPDMA_C0CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT1_Pos)                     /*!< GPDMA C0CONTROL: PROT1 Mask         */
-#define GPDMA_C0CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C0CONTROL: PROT2 Position     */
-#define GPDMA_C0CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT2_Pos)                     /*!< GPDMA C0CONTROL: PROT2 Mask         */
-#define GPDMA_C0CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C0CONTROL: PROT3 Position     */
-#define GPDMA_C0CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT3_Pos)                     /*!< GPDMA C0CONTROL: PROT3 Mask         */
-#define GPDMA_C0CONTROL_I_Pos                                 31                                                        /*!< GPDMA C0CONTROL: I Position         */
-#define GPDMA_C0CONTROL_I_Msk                                 (0x01UL << GPDMA_C0CONTROL_I_Pos)                         /*!< GPDMA C0CONTROL: I Mask             */
-
-// -------------------------------------  GPDMA_C0CONFIG  -----------------------------------------
-#define GPDMA_C0CONFIG_E_Pos                                  0                                                         /*!< GPDMA C0CONFIG: E Position          */
-#define GPDMA_C0CONFIG_E_Msk                                  (0x01UL << GPDMA_C0CONFIG_E_Pos)                          /*!< GPDMA C0CONFIG: E Mask              */
-#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */
-#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask  */
-#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */
-#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */
-#define GPDMA_C0CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C0CONFIG: FLOWCNTRL Position  */
-#define GPDMA_C0CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C0CONFIG: FLOWCNTRL Mask      */
-#define GPDMA_C0CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C0CONFIG: IE Position         */
-#define GPDMA_C0CONFIG_IE_Msk                                 (0x01UL << GPDMA_C0CONFIG_IE_Pos)                         /*!< GPDMA C0CONFIG: IE Mask             */
-#define GPDMA_C0CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C0CONFIG: ITC Position        */
-#define GPDMA_C0CONFIG_ITC_Msk                                (0x01UL << GPDMA_C0CONFIG_ITC_Pos)                        /*!< GPDMA C0CONFIG: ITC Mask            */
-#define GPDMA_C0CONFIG_L_Pos                                  16                                                        /*!< GPDMA C0CONFIG: L Position          */
-#define GPDMA_C0CONFIG_L_Msk                                  (0x01UL << GPDMA_C0CONFIG_L_Pos)                          /*!< GPDMA C0CONFIG: L Mask              */
-#define GPDMA_C0CONFIG_A_Pos                                  17                                                        /*!< GPDMA C0CONFIG: A Position          */
-#define GPDMA_C0CONFIG_A_Msk                                  (0x01UL << GPDMA_C0CONFIG_A_Pos)                          /*!< GPDMA C0CONFIG: A Mask              */
-#define GPDMA_C0CONFIG_H_Pos                                  18                                                        /*!< GPDMA C0CONFIG: H Position          */
-#define GPDMA_C0CONFIG_H_Msk                                  (0x01UL << GPDMA_C0CONFIG_H_Pos)                          /*!< GPDMA C0CONFIG: H Mask              */
-
-// -------------------------------------  GPDMA_C1SRCADDR  ----------------------------------------
-#define GPDMA_C1SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C1SRCADDR: SRCADDR Position   */
-#define GPDMA_C1SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos)             /*!< GPDMA C1SRCADDR: SRCADDR Mask       */
-
-// ------------------------------------  GPDMA_C1DESTADDR  ----------------------------------------
-#define GPDMA_C1DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C1DESTADDR: DESTADDR Position */
-#define GPDMA_C1DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos)           /*!< GPDMA C1DESTADDR: DESTADDR Mask     */
-
-// ---------------------------------------  GPDMA_C1LLI  ------------------------------------------
-#define GPDMA_C1LLI_LM_Pos                                    0                                                         /*!< GPDMA C1LLI: LM Position            */
-#define GPDMA_C1LLI_LM_Msk                                    (0x01UL << GPDMA_C1LLI_LM_Pos)                            /*!< GPDMA C1LLI: LM Mask                */
-#define GPDMA_C1LLI_R_Pos                                     1                                                         /*!< GPDMA C1LLI: R Position             */
-#define GPDMA_C1LLI_R_Msk                                     (0x01UL << GPDMA_C1LLI_R_Pos)                             /*!< GPDMA C1LLI: R Mask                 */
-#define GPDMA_C1LLI_LLI_Pos                                   2                                                         /*!< GPDMA C1LLI: LLI Position           */
-#define GPDMA_C1LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos)                     /*!< GPDMA C1LLI: LLI Mask               */
-
-// -------------------------------------  GPDMA_C1CONTROL  ----------------------------------------
-#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */
-#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask  */
-#define GPDMA_C1CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C1CONTROL: SBSIZE Position    */
-#define GPDMA_C1CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos)                    /*!< GPDMA C1CONTROL: SBSIZE Mask        */
-#define GPDMA_C1CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C1CONTROL: DBSIZE Position    */
-#define GPDMA_C1CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos)                    /*!< GPDMA C1CONTROL: DBSIZE Mask        */
-#define GPDMA_C1CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C1CONTROL: SWIDTH Position    */
-#define GPDMA_C1CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos)                    /*!< GPDMA C1CONTROL: SWIDTH Mask        */
-#define GPDMA_C1CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C1CONTROL: DWIDTH Position    */
-#define GPDMA_C1CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos)                    /*!< GPDMA C1CONTROL: DWIDTH Mask        */
-#define GPDMA_C1CONTROL_S_Pos                                 24                                                        /*!< GPDMA C1CONTROL: S Position         */
-#define GPDMA_C1CONTROL_S_Msk                                 (0x01UL << GPDMA_C1CONTROL_S_Pos)                         /*!< GPDMA C1CONTROL: S Mask             */
-#define GPDMA_C1CONTROL_D_Pos                                 25                                                        /*!< GPDMA C1CONTROL: D Position         */
-#define GPDMA_C1CONTROL_D_Msk                                 (0x01UL << GPDMA_C1CONTROL_D_Pos)                         /*!< GPDMA C1CONTROL: D Mask             */
-#define GPDMA_C1CONTROL_SI_Pos                                26                                                        /*!< GPDMA C1CONTROL: SI Position        */
-#define GPDMA_C1CONTROL_SI_Msk                                (0x01UL << GPDMA_C1CONTROL_SI_Pos)                        /*!< GPDMA C1CONTROL: SI Mask            */
-#define GPDMA_C1CONTROL_DI_Pos                                27                                                        /*!< GPDMA C1CONTROL: DI Position        */
-#define GPDMA_C1CONTROL_DI_Msk                                (0x01UL << GPDMA_C1CONTROL_DI_Pos)                        /*!< GPDMA C1CONTROL: DI Mask            */
-#define GPDMA_C1CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C1CONTROL: PROT1 Position     */
-#define GPDMA_C1CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT1_Pos)                     /*!< GPDMA C1CONTROL: PROT1 Mask         */
-#define GPDMA_C1CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C1CONTROL: PROT2 Position     */
-#define GPDMA_C1CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT2_Pos)                     /*!< GPDMA C1CONTROL: PROT2 Mask         */
-#define GPDMA_C1CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C1CONTROL: PROT3 Position     */
-#define GPDMA_C1CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT3_Pos)                     /*!< GPDMA C1CONTROL: PROT3 Mask         */
-#define GPDMA_C1CONTROL_I_Pos                                 31                                                        /*!< GPDMA C1CONTROL: I Position         */
-#define GPDMA_C1CONTROL_I_Msk                                 (0x01UL << GPDMA_C1CONTROL_I_Pos)                         /*!< GPDMA C1CONTROL: I Mask             */
-
-// -------------------------------------  GPDMA_C1CONFIG  -----------------------------------------
-#define GPDMA_C1CONFIG_E_Pos                                  0                                                         /*!< GPDMA C1CONFIG: E Position          */
-#define GPDMA_C1CONFIG_E_Msk                                  (0x01UL << GPDMA_C1CONFIG_E_Pos)                          /*!< GPDMA C1CONFIG: E Mask              */
-#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */
-#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask  */
-#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */
-#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */
-#define GPDMA_C1CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C1CONFIG: FLOWCNTRL Position  */
-#define GPDMA_C1CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C1CONFIG: FLOWCNTRL Mask      */
-#define GPDMA_C1CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C1CONFIG: IE Position         */
-#define GPDMA_C1CONFIG_IE_Msk                                 (0x01UL << GPDMA_C1CONFIG_IE_Pos)                         /*!< GPDMA C1CONFIG: IE Mask             */
-#define GPDMA_C1CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C1CONFIG: ITC Position        */
-#define GPDMA_C1CONFIG_ITC_Msk                                (0x01UL << GPDMA_C1CONFIG_ITC_Pos)                        /*!< GPDMA C1CONFIG: ITC Mask            */
-#define GPDMA_C1CONFIG_L_Pos                                  16                                                        /*!< GPDMA C1CONFIG: L Position          */
-#define GPDMA_C1CONFIG_L_Msk                                  (0x01UL << GPDMA_C1CONFIG_L_Pos)                          /*!< GPDMA C1CONFIG: L Mask              */
-#define GPDMA_C1CONFIG_A_Pos                                  17                                                        /*!< GPDMA C1CONFIG: A Position          */
-#define GPDMA_C1CONFIG_A_Msk                                  (0x01UL << GPDMA_C1CONFIG_A_Pos)                          /*!< GPDMA C1CONFIG: A Mask              */
-#define GPDMA_C1CONFIG_H_Pos                                  18                                                        /*!< GPDMA C1CONFIG: H Position          */
-#define GPDMA_C1CONFIG_H_Msk                                  (0x01UL << GPDMA_C1CONFIG_H_Pos)                          /*!< GPDMA C1CONFIG: H Mask              */
-
-// -------------------------------------  GPDMA_C2SRCADDR  ----------------------------------------
-#define GPDMA_C2SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C2SRCADDR: SRCADDR Position   */
-#define GPDMA_C2SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos)             /*!< GPDMA C2SRCADDR: SRCADDR Mask       */
-
-// ------------------------------------  GPDMA_C2DESTADDR  ----------------------------------------
-#define GPDMA_C2DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C2DESTADDR: DESTADDR Position */
-#define GPDMA_C2DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos)           /*!< GPDMA C2DESTADDR: DESTADDR Mask     */
-
-// ---------------------------------------  GPDMA_C2LLI  ------------------------------------------
-#define GPDMA_C2LLI_LM_Pos                                    0                                                         /*!< GPDMA C2LLI: LM Position            */
-#define GPDMA_C2LLI_LM_Msk                                    (0x01UL << GPDMA_C2LLI_LM_Pos)                            /*!< GPDMA C2LLI: LM Mask                */
-#define GPDMA_C2LLI_R_Pos                                     1                                                         /*!< GPDMA C2LLI: R Position             */
-#define GPDMA_C2LLI_R_Msk                                     (0x01UL << GPDMA_C2LLI_R_Pos)                             /*!< GPDMA C2LLI: R Mask                 */
-#define GPDMA_C2LLI_LLI_Pos                                   2                                                         /*!< GPDMA C2LLI: LLI Position           */
-#define GPDMA_C2LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos)                     /*!< GPDMA C2LLI: LLI Mask               */
-
-// -------------------------------------  GPDMA_C2CONTROL  ----------------------------------------
-#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */
-#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask  */
-#define GPDMA_C2CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C2CONTROL: SBSIZE Position    */
-#define GPDMA_C2CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos)                    /*!< GPDMA C2CONTROL: SBSIZE Mask        */
-#define GPDMA_C2CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C2CONTROL: DBSIZE Position    */
-#define GPDMA_C2CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos)                    /*!< GPDMA C2CONTROL: DBSIZE Mask        */
-#define GPDMA_C2CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C2CONTROL: SWIDTH Position    */
-#define GPDMA_C2CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos)                    /*!< GPDMA C2CONTROL: SWIDTH Mask        */
-#define GPDMA_C2CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C2CONTROL: DWIDTH Position    */
-#define GPDMA_C2CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos)                    /*!< GPDMA C2CONTROL: DWIDTH Mask        */
-#define GPDMA_C2CONTROL_S_Pos                                 24                                                        /*!< GPDMA C2CONTROL: S Position         */
-#define GPDMA_C2CONTROL_S_Msk                                 (0x01UL << GPDMA_C2CONTROL_S_Pos)                         /*!< GPDMA C2CONTROL: S Mask             */
-#define GPDMA_C2CONTROL_D_Pos                                 25                                                        /*!< GPDMA C2CONTROL: D Position         */
-#define GPDMA_C2CONTROL_D_Msk                                 (0x01UL << GPDMA_C2CONTROL_D_Pos)                         /*!< GPDMA C2CONTROL: D Mask             */
-#define GPDMA_C2CONTROL_SI_Pos                                26                                                        /*!< GPDMA C2CONTROL: SI Position        */
-#define GPDMA_C2CONTROL_SI_Msk                                (0x01UL << GPDMA_C2CONTROL_SI_Pos)                        /*!< GPDMA C2CONTROL: SI Mask            */
-#define GPDMA_C2CONTROL_DI_Pos                                27                                                        /*!< GPDMA C2CONTROL: DI Position        */
-#define GPDMA_C2CONTROL_DI_Msk                                (0x01UL << GPDMA_C2CONTROL_DI_Pos)                        /*!< GPDMA C2CONTROL: DI Mask            */
-#define GPDMA_C2CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C2CONTROL: PROT1 Position     */
-#define GPDMA_C2CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT1_Pos)                     /*!< GPDMA C2CONTROL: PROT1 Mask         */
-#define GPDMA_C2CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C2CONTROL: PROT2 Position     */
-#define GPDMA_C2CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT2_Pos)                     /*!< GPDMA C2CONTROL: PROT2 Mask         */
-#define GPDMA_C2CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C2CONTROL: PROT3 Position     */
-#define GPDMA_C2CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT3_Pos)                     /*!< GPDMA C2CONTROL: PROT3 Mask         */
-#define GPDMA_C2CONTROL_I_Pos                                 31                                                        /*!< GPDMA C2CONTROL: I Position         */
-#define GPDMA_C2CONTROL_I_Msk                                 (0x01UL << GPDMA_C2CONTROL_I_Pos)                         /*!< GPDMA C2CONTROL: I Mask             */
-
-// -------------------------------------  GPDMA_C2CONFIG  -----------------------------------------
-#define GPDMA_C2CONFIG_E_Pos                                  0                                                         /*!< GPDMA C2CONFIG: E Position          */
-#define GPDMA_C2CONFIG_E_Msk                                  (0x01UL << GPDMA_C2CONFIG_E_Pos)                          /*!< GPDMA C2CONFIG: E Mask              */
-#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */
-#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask  */
-#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */
-#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */
-#define GPDMA_C2CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C2CONFIG: FLOWCNTRL Position  */
-#define GPDMA_C2CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C2CONFIG: FLOWCNTRL Mask      */
-#define GPDMA_C2CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C2CONFIG: IE Position         */
-#define GPDMA_C2CONFIG_IE_Msk                                 (0x01UL << GPDMA_C2CONFIG_IE_Pos)                         /*!< GPDMA C2CONFIG: IE Mask             */
-#define GPDMA_C2CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C2CONFIG: ITC Position        */
-#define GPDMA_C2CONFIG_ITC_Msk                                (0x01UL << GPDMA_C2CONFIG_ITC_Pos)                        /*!< GPDMA C2CONFIG: ITC Mask            */
-#define GPDMA_C2CONFIG_L_Pos                                  16                                                        /*!< GPDMA C2CONFIG: L Position          */
-#define GPDMA_C2CONFIG_L_Msk                                  (0x01UL << GPDMA_C2CONFIG_L_Pos)                          /*!< GPDMA C2CONFIG: L Mask              */
-#define GPDMA_C2CONFIG_A_Pos                                  17                                                        /*!< GPDMA C2CONFIG: A Position          */
-#define GPDMA_C2CONFIG_A_Msk                                  (0x01UL << GPDMA_C2CONFIG_A_Pos)                          /*!< GPDMA C2CONFIG: A Mask              */
-#define GPDMA_C2CONFIG_H_Pos                                  18                                                        /*!< GPDMA C2CONFIG: H Position          */
-#define GPDMA_C2CONFIG_H_Msk                                  (0x01UL << GPDMA_C2CONFIG_H_Pos)                          /*!< GPDMA C2CONFIG: H Mask              */
-
-// -------------------------------------  GPDMA_C3SRCADDR  ----------------------------------------
-#define GPDMA_C3SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C3SRCADDR: SRCADDR Position   */
-#define GPDMA_C3SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos)             /*!< GPDMA C3SRCADDR: SRCADDR Mask       */
-
-// ------------------------------------  GPDMA_C3DESTADDR  ----------------------------------------
-#define GPDMA_C3DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C3DESTADDR: DESTADDR Position */
-#define GPDMA_C3DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos)           /*!< GPDMA C3DESTADDR: DESTADDR Mask     */
-
-// ---------------------------------------  GPDMA_C3LLI  ------------------------------------------
-#define GPDMA_C3LLI_LM_Pos                                    0                                                         /*!< GPDMA C3LLI: LM Position            */
-#define GPDMA_C3LLI_LM_Msk                                    (0x01UL << GPDMA_C3LLI_LM_Pos)                            /*!< GPDMA C3LLI: LM Mask                */
-#define GPDMA_C3LLI_R_Pos                                     1                                                         /*!< GPDMA C3LLI: R Position             */
-#define GPDMA_C3LLI_R_Msk                                     (0x01UL << GPDMA_C3LLI_R_Pos)                             /*!< GPDMA C3LLI: R Mask                 */
-#define GPDMA_C3LLI_LLI_Pos                                   2                                                         /*!< GPDMA C3LLI: LLI Position           */
-#define GPDMA_C3LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos)                     /*!< GPDMA C3LLI: LLI Mask               */
-
-// -------------------------------------  GPDMA_C3CONTROL  ----------------------------------------
-#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */
-#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask  */
-#define GPDMA_C3CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C3CONTROL: SBSIZE Position    */
-#define GPDMA_C3CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos)                    /*!< GPDMA C3CONTROL: SBSIZE Mask        */
-#define GPDMA_C3CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C3CONTROL: DBSIZE Position    */
-#define GPDMA_C3CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos)                    /*!< GPDMA C3CONTROL: DBSIZE Mask        */
-#define GPDMA_C3CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C3CONTROL: SWIDTH Position    */
-#define GPDMA_C3CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos)                    /*!< GPDMA C3CONTROL: SWIDTH Mask        */
-#define GPDMA_C3CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C3CONTROL: DWIDTH Position    */
-#define GPDMA_C3CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos)                    /*!< GPDMA C3CONTROL: DWIDTH Mask        */
-#define GPDMA_C3CONTROL_S_Pos                                 24                                                        /*!< GPDMA C3CONTROL: S Position         */
-#define GPDMA_C3CONTROL_S_Msk                                 (0x01UL << GPDMA_C3CONTROL_S_Pos)                         /*!< GPDMA C3CONTROL: S Mask             */
-#define GPDMA_C3CONTROL_D_Pos                                 25                                                        /*!< GPDMA C3CONTROL: D Position         */
-#define GPDMA_C3CONTROL_D_Msk                                 (0x01UL << GPDMA_C3CONTROL_D_Pos)                         /*!< GPDMA C3CONTROL: D Mask             */
-#define GPDMA_C3CONTROL_SI_Pos                                26                                                        /*!< GPDMA C3CONTROL: SI Position        */
-#define GPDMA_C3CONTROL_SI_Msk                                (0x01UL << GPDMA_C3CONTROL_SI_Pos)                        /*!< GPDMA C3CONTROL: SI Mask            */
-#define GPDMA_C3CONTROL_DI_Pos                                27                                                        /*!< GPDMA C3CONTROL: DI Position        */
-#define GPDMA_C3CONTROL_DI_Msk                                (0x01UL << GPDMA_C3CONTROL_DI_Pos)                        /*!< GPDMA C3CONTROL: DI Mask            */
-#define GPDMA_C3CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C3CONTROL: PROT1 Position     */
-#define GPDMA_C3CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT1_Pos)                     /*!< GPDMA C3CONTROL: PROT1 Mask         */
-#define GPDMA_C3CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C3CONTROL: PROT2 Position     */
-#define GPDMA_C3CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT2_Pos)                     /*!< GPDMA C3CONTROL: PROT2 Mask         */
-#define GPDMA_C3CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C3CONTROL: PROT3 Position     */
-#define GPDMA_C3CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT3_Pos)                     /*!< GPDMA C3CONTROL: PROT3 Mask         */
-#define GPDMA_C3CONTROL_I_Pos                                 31                                                        /*!< GPDMA C3CONTROL: I Position         */
-#define GPDMA_C3CONTROL_I_Msk                                 (0x01UL << GPDMA_C3CONTROL_I_Pos)                         /*!< GPDMA C3CONTROL: I Mask             */
-
-// -------------------------------------  GPDMA_C3CONFIG  -----------------------------------------
-#define GPDMA_C3CONFIG_E_Pos                                  0                                                         /*!< GPDMA C3CONFIG: E Position          */
-#define GPDMA_C3CONFIG_E_Msk                                  (0x01UL << GPDMA_C3CONFIG_E_Pos)                          /*!< GPDMA C3CONFIG: E Mask              */
-#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */
-#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask  */
-#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */
-#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */
-#define GPDMA_C3CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C3CONFIG: FLOWCNTRL Position  */
-#define GPDMA_C3CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C3CONFIG: FLOWCNTRL Mask      */
-#define GPDMA_C3CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C3CONFIG: IE Position         */
-#define GPDMA_C3CONFIG_IE_Msk                                 (0x01UL << GPDMA_C3CONFIG_IE_Pos)                         /*!< GPDMA C3CONFIG: IE Mask             */
-#define GPDMA_C3CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C3CONFIG: ITC Position        */
-#define GPDMA_C3CONFIG_ITC_Msk                                (0x01UL << GPDMA_C3CONFIG_ITC_Pos)                        /*!< GPDMA C3CONFIG: ITC Mask            */
-#define GPDMA_C3CONFIG_L_Pos                                  16                                                        /*!< GPDMA C3CONFIG: L Position          */
-#define GPDMA_C3CONFIG_L_Msk                                  (0x01UL << GPDMA_C3CONFIG_L_Pos)                          /*!< GPDMA C3CONFIG: L Mask              */
-#define GPDMA_C3CONFIG_A_Pos                                  17                                                        /*!< GPDMA C3CONFIG: A Position          */
-#define GPDMA_C3CONFIG_A_Msk                                  (0x01UL << GPDMA_C3CONFIG_A_Pos)                          /*!< GPDMA C3CONFIG: A Mask              */
-#define GPDMA_C3CONFIG_H_Pos                                  18                                                        /*!< GPDMA C3CONFIG: H Position          */
-#define GPDMA_C3CONFIG_H_Msk                                  (0x01UL << GPDMA_C3CONFIG_H_Pos)                          /*!< GPDMA C3CONFIG: H Mask              */
-
-// -------------------------------------  GPDMA_C4SRCADDR  ----------------------------------------
-#define GPDMA_C4SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C4SRCADDR: SRCADDR Position   */
-#define GPDMA_C4SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos)             /*!< GPDMA C4SRCADDR: SRCADDR Mask       */
-
-// ------------------------------------  GPDMA_C4DESTADDR  ----------------------------------------
-#define GPDMA_C4DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C4DESTADDR: DESTADDR Position */
-#define GPDMA_C4DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos)           /*!< GPDMA C4DESTADDR: DESTADDR Mask     */
-
-// ---------------------------------------  GPDMA_C4LLI  ------------------------------------------
-#define GPDMA_C4LLI_LM_Pos                                    0                                                         /*!< GPDMA C4LLI: LM Position            */
-#define GPDMA_C4LLI_LM_Msk                                    (0x01UL << GPDMA_C4LLI_LM_Pos)                            /*!< GPDMA C4LLI: LM Mask                */
-#define GPDMA_C4LLI_R_Pos                                     1                                                         /*!< GPDMA C4LLI: R Position             */
-#define GPDMA_C4LLI_R_Msk                                     (0x01UL << GPDMA_C4LLI_R_Pos)                             /*!< GPDMA C4LLI: R Mask                 */
-#define GPDMA_C4LLI_LLI_Pos                                   2                                                         /*!< GPDMA C4LLI: LLI Position           */
-#define GPDMA_C4LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos)                     /*!< GPDMA C4LLI: LLI Mask               */
-
-// -------------------------------------  GPDMA_C4CONTROL  ----------------------------------------
-#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */
-#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask  */
-#define GPDMA_C4CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C4CONTROL: SBSIZE Position    */
-#define GPDMA_C4CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos)                    /*!< GPDMA C4CONTROL: SBSIZE Mask        */
-#define GPDMA_C4CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C4CONTROL: DBSIZE Position    */
-#define GPDMA_C4CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos)                    /*!< GPDMA C4CONTROL: DBSIZE Mask        */
-#define GPDMA_C4CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C4CONTROL: SWIDTH Position    */
-#define GPDMA_C4CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos)                    /*!< GPDMA C4CONTROL: SWIDTH Mask        */
-#define GPDMA_C4CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C4CONTROL: DWIDTH Position    */
-#define GPDMA_C4CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos)                    /*!< GPDMA C4CONTROL: DWIDTH Mask        */
-#define GPDMA_C4CONTROL_S_Pos                                 24                                                        /*!< GPDMA C4CONTROL: S Position         */
-#define GPDMA_C4CONTROL_S_Msk                                 (0x01UL << GPDMA_C4CONTROL_S_Pos)                         /*!< GPDMA C4CONTROL: S Mask             */
-#define GPDMA_C4CONTROL_D_Pos                                 25                                                        /*!< GPDMA C4CONTROL: D Position         */
-#define GPDMA_C4CONTROL_D_Msk                                 (0x01UL << GPDMA_C4CONTROL_D_Pos)                         /*!< GPDMA C4CONTROL: D Mask             */
-#define GPDMA_C4CONTROL_SI_Pos                                26                                                        /*!< GPDMA C4CONTROL: SI Position        */
-#define GPDMA_C4CONTROL_SI_Msk                                (0x01UL << GPDMA_C4CONTROL_SI_Pos)                        /*!< GPDMA C4CONTROL: SI Mask            */
-#define GPDMA_C4CONTROL_DI_Pos                                27                                                        /*!< GPDMA C4CONTROL: DI Position        */
-#define GPDMA_C4CONTROL_DI_Msk                                (0x01UL << GPDMA_C4CONTROL_DI_Pos)                        /*!< GPDMA C4CONTROL: DI Mask            */
-#define GPDMA_C4CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C4CONTROL: PROT1 Position     */
-#define GPDMA_C4CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT1_Pos)                     /*!< GPDMA C4CONTROL: PROT1 Mask         */
-#define GPDMA_C4CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C4CONTROL: PROT2 Position     */
-#define GPDMA_C4CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT2_Pos)                     /*!< GPDMA C4CONTROL: PROT2 Mask         */
-#define GPDMA_C4CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C4CONTROL: PROT3 Position     */
-#define GPDMA_C4CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT3_Pos)                     /*!< GPDMA C4CONTROL: PROT3 Mask         */
-#define GPDMA_C4CONTROL_I_Pos                                 31                                                        /*!< GPDMA C4CONTROL: I Position         */
-#define GPDMA_C4CONTROL_I_Msk                                 (0x01UL << GPDMA_C4CONTROL_I_Pos)                         /*!< GPDMA C4CONTROL: I Mask             */
-
-// -------------------------------------  GPDMA_C4CONFIG  -----------------------------------------
-#define GPDMA_C4CONFIG_E_Pos                                  0                                                         /*!< GPDMA C4CONFIG: E Position          */
-#define GPDMA_C4CONFIG_E_Msk                                  (0x01UL << GPDMA_C4CONFIG_E_Pos)                          /*!< GPDMA C4CONFIG: E Mask              */
-#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */
-#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask  */
-#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */
-#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */
-#define GPDMA_C4CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C4CONFIG: FLOWCNTRL Position  */
-#define GPDMA_C4CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C4CONFIG: FLOWCNTRL Mask      */
-#define GPDMA_C4CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C4CONFIG: IE Position         */
-#define GPDMA_C4CONFIG_IE_Msk                                 (0x01UL << GPDMA_C4CONFIG_IE_Pos)                         /*!< GPDMA C4CONFIG: IE Mask             */
-#define GPDMA_C4CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C4CONFIG: ITC Position        */
-#define GPDMA_C4CONFIG_ITC_Msk                                (0x01UL << GPDMA_C4CONFIG_ITC_Pos)                        /*!< GPDMA C4CONFIG: ITC Mask            */
-#define GPDMA_C4CONFIG_L_Pos                                  16                                                        /*!< GPDMA C4CONFIG: L Position          */
-#define GPDMA_C4CONFIG_L_Msk                                  (0x01UL << GPDMA_C4CONFIG_L_Pos)                          /*!< GPDMA C4CONFIG: L Mask              */
-#define GPDMA_C4CONFIG_A_Pos                                  17                                                        /*!< GPDMA C4CONFIG: A Position          */
-#define GPDMA_C4CONFIG_A_Msk                                  (0x01UL << GPDMA_C4CONFIG_A_Pos)                          /*!< GPDMA C4CONFIG: A Mask              */
-#define GPDMA_C4CONFIG_H_Pos                                  18                                                        /*!< GPDMA C4CONFIG: H Position          */
-#define GPDMA_C4CONFIG_H_Msk                                  (0x01UL << GPDMA_C4CONFIG_H_Pos)                          /*!< GPDMA C4CONFIG: H Mask              */
-
-// -------------------------------------  GPDMA_C5SRCADDR  ----------------------------------------
-#define GPDMA_C5SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C5SRCADDR: SRCADDR Position   */
-#define GPDMA_C5SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos)             /*!< GPDMA C5SRCADDR: SRCADDR Mask       */
-
-// ------------------------------------  GPDMA_C5DESTADDR  ----------------------------------------
-#define GPDMA_C5DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C5DESTADDR: DESTADDR Position */
-#define GPDMA_C5DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos)           /*!< GPDMA C5DESTADDR: DESTADDR Mask     */
-
-// ---------------------------------------  GPDMA_C5LLI  ------------------------------------------
-#define GPDMA_C5LLI_LM_Pos                                    0                                                         /*!< GPDMA C5LLI: LM Position            */
-#define GPDMA_C5LLI_LM_Msk                                    (0x01UL << GPDMA_C5LLI_LM_Pos)                            /*!< GPDMA C5LLI: LM Mask                */
-#define GPDMA_C5LLI_R_Pos                                     1                                                         /*!< GPDMA C5LLI: R Position             */
-#define GPDMA_C5LLI_R_Msk                                     (0x01UL << GPDMA_C5LLI_R_Pos)                             /*!< GPDMA C5LLI: R Mask                 */
-#define GPDMA_C5LLI_LLI_Pos                                   2                                                         /*!< GPDMA C5LLI: LLI Position           */
-#define GPDMA_C5LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos)                     /*!< GPDMA C5LLI: LLI Mask               */
-
-// -------------------------------------  GPDMA_C5CONTROL  ----------------------------------------
-#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */
-#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask  */
-#define GPDMA_C5CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C5CONTROL: SBSIZE Position    */
-#define GPDMA_C5CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos)                    /*!< GPDMA C5CONTROL: SBSIZE Mask        */
-#define GPDMA_C5CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C5CONTROL: DBSIZE Position    */
-#define GPDMA_C5CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos)                    /*!< GPDMA C5CONTROL: DBSIZE Mask        */
-#define GPDMA_C5CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C5CONTROL: SWIDTH Position    */
-#define GPDMA_C5CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos)                    /*!< GPDMA C5CONTROL: SWIDTH Mask        */
-#define GPDMA_C5CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C5CONTROL: DWIDTH Position    */
-#define GPDMA_C5CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos)                    /*!< GPDMA C5CONTROL: DWIDTH Mask        */
-#define GPDMA_C5CONTROL_S_Pos                                 24                                                        /*!< GPDMA C5CONTROL: S Position         */
-#define GPDMA_C5CONTROL_S_Msk                                 (0x01UL << GPDMA_C5CONTROL_S_Pos)                         /*!< GPDMA C5CONTROL: S Mask             */
-#define GPDMA_C5CONTROL_D_Pos                                 25                                                        /*!< GPDMA C5CONTROL: D Position         */
-#define GPDMA_C5CONTROL_D_Msk                                 (0x01UL << GPDMA_C5CONTROL_D_Pos)                         /*!< GPDMA C5CONTROL: D Mask             */
-#define GPDMA_C5CONTROL_SI_Pos                                26                                                        /*!< GPDMA C5CONTROL: SI Position        */
-#define GPDMA_C5CONTROL_SI_Msk                                (0x01UL << GPDMA_C5CONTROL_SI_Pos)                        /*!< GPDMA C5CONTROL: SI Mask            */
-#define GPDMA_C5CONTROL_DI_Pos                                27                                                        /*!< GPDMA C5CONTROL: DI Position        */
-#define GPDMA_C5CONTROL_DI_Msk                                (0x01UL << GPDMA_C5CONTROL_DI_Pos)                        /*!< GPDMA C5CONTROL: DI Mask            */
-#define GPDMA_C5CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C5CONTROL: PROT1 Position     */
-#define GPDMA_C5CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT1_Pos)                     /*!< GPDMA C5CONTROL: PROT1 Mask         */
-#define GPDMA_C5CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C5CONTROL: PROT2 Position     */
-#define GPDMA_C5CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT2_Pos)                     /*!< GPDMA C5CONTROL: PROT2 Mask         */
-#define GPDMA_C5CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C5CONTROL: PROT3 Position     */
-#define GPDMA_C5CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT3_Pos)                     /*!< GPDMA C5CONTROL: PROT3 Mask         */
-#define GPDMA_C5CONTROL_I_Pos                                 31                                                        /*!< GPDMA C5CONTROL: I Position         */
-#define GPDMA_C5CONTROL_I_Msk                                 (0x01UL << GPDMA_C5CONTROL_I_Pos)                         /*!< GPDMA C5CONTROL: I Mask             */
-
-// -------------------------------------  GPDMA_C5CONFIG  -----------------------------------------
-#define GPDMA_C5CONFIG_E_Pos                                  0                                                         /*!< GPDMA C5CONFIG: E Position          */
-#define GPDMA_C5CONFIG_E_Msk                                  (0x01UL << GPDMA_C5CONFIG_E_Pos)                          /*!< GPDMA C5CONFIG: E Mask              */
-#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */
-#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask  */
-#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */
-#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */
-#define GPDMA_C5CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C5CONFIG: FLOWCNTRL Position  */
-#define GPDMA_C5CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C5CONFIG: FLOWCNTRL Mask      */
-#define GPDMA_C5CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C5CONFIG: IE Position         */
-#define GPDMA_C5CONFIG_IE_Msk                                 (0x01UL << GPDMA_C5CONFIG_IE_Pos)                         /*!< GPDMA C5CONFIG: IE Mask             */
-#define GPDMA_C5CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C5CONFIG: ITC Position        */
-#define GPDMA_C5CONFIG_ITC_Msk                                (0x01UL << GPDMA_C5CONFIG_ITC_Pos)                        /*!< GPDMA C5CONFIG: ITC Mask            */
-#define GPDMA_C5CONFIG_L_Pos                                  16                                                        /*!< GPDMA C5CONFIG: L Position          */
-#define GPDMA_C5CONFIG_L_Msk                                  (0x01UL << GPDMA_C5CONFIG_L_Pos)                          /*!< GPDMA C5CONFIG: L Mask              */
-#define GPDMA_C5CONFIG_A_Pos                                  17                                                        /*!< GPDMA C5CONFIG: A Position          */
-#define GPDMA_C5CONFIG_A_Msk                                  (0x01UL << GPDMA_C5CONFIG_A_Pos)                          /*!< GPDMA C5CONFIG: A Mask              */
-#define GPDMA_C5CONFIG_H_Pos                                  18                                                        /*!< GPDMA C5CONFIG: H Position          */
-#define GPDMA_C5CONFIG_H_Msk                                  (0x01UL << GPDMA_C5CONFIG_H_Pos)                          /*!< GPDMA C5CONFIG: H Mask              */
-
-// -------------------------------------  GPDMA_C6SRCADDR  ----------------------------------------
-#define GPDMA_C6SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C6SRCADDR: SRCADDR Position   */
-#define GPDMA_C6SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos)             /*!< GPDMA C6SRCADDR: SRCADDR Mask       */
-
-// ------------------------------------  GPDMA_C6DESTADDR  ----------------------------------------
-#define GPDMA_C6DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C6DESTADDR: DESTADDR Position */
-#define GPDMA_C6DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos)           /*!< GPDMA C6DESTADDR: DESTADDR Mask     */
-
-// ---------------------------------------  GPDMA_C6LLI  ------------------------------------------
-#define GPDMA_C6LLI_LM_Pos                                    0                                                         /*!< GPDMA C6LLI: LM Position            */
-#define GPDMA_C6LLI_LM_Msk                                    (0x01UL << GPDMA_C6LLI_LM_Pos)                            /*!< GPDMA C6LLI: LM Mask                */
-#define GPDMA_C6LLI_R_Pos                                     1                                                         /*!< GPDMA C6LLI: R Position             */
-#define GPDMA_C6LLI_R_Msk                                     (0x01UL << GPDMA_C6LLI_R_Pos)                             /*!< GPDMA C6LLI: R Mask                 */
-#define GPDMA_C6LLI_LLI_Pos                                   2                                                         /*!< GPDMA C6LLI: LLI Position           */
-#define GPDMA_C6LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos)                     /*!< GPDMA C6LLI: LLI Mask               */
-
-// -------------------------------------  GPDMA_C6CONTROL  ----------------------------------------
-#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */
-#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask  */
-#define GPDMA_C6CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C6CONTROL: SBSIZE Position    */
-#define GPDMA_C6CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos)                    /*!< GPDMA C6CONTROL: SBSIZE Mask        */
-#define GPDMA_C6CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C6CONTROL: DBSIZE Position    */
-#define GPDMA_C6CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos)                    /*!< GPDMA C6CONTROL: DBSIZE Mask        */
-#define GPDMA_C6CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C6CONTROL: SWIDTH Position    */
-#define GPDMA_C6CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos)                    /*!< GPDMA C6CONTROL: SWIDTH Mask        */
-#define GPDMA_C6CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C6CONTROL: DWIDTH Position    */
-#define GPDMA_C6CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos)                    /*!< GPDMA C6CONTROL: DWIDTH Mask        */
-#define GPDMA_C6CONTROL_S_Pos                                 24                                                        /*!< GPDMA C6CONTROL: S Position         */
-#define GPDMA_C6CONTROL_S_Msk                                 (0x01UL << GPDMA_C6CONTROL_S_Pos)                         /*!< GPDMA C6CONTROL: S Mask             */
-#define GPDMA_C6CONTROL_D_Pos                                 25                                                        /*!< GPDMA C6CONTROL: D Position         */
-#define GPDMA_C6CONTROL_D_Msk                                 (0x01UL << GPDMA_C6CONTROL_D_Pos)                         /*!< GPDMA C6CONTROL: D Mask             */
-#define GPDMA_C6CONTROL_SI_Pos                                26                                                        /*!< GPDMA C6CONTROL: SI Position        */
-#define GPDMA_C6CONTROL_SI_Msk                                (0x01UL << GPDMA_C6CONTROL_SI_Pos)                        /*!< GPDMA C6CONTROL: SI Mask            */
-#define GPDMA_C6CONTROL_DI_Pos                                27                                                        /*!< GPDMA C6CONTROL: DI Position        */
-#define GPDMA_C6CONTROL_DI_Msk                                (0x01UL << GPDMA_C6CONTROL_DI_Pos)                        /*!< GPDMA C6CONTROL: DI Mask            */
-#define GPDMA_C6CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C6CONTROL: PROT1 Position     */
-#define GPDMA_C6CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT1_Pos)                     /*!< GPDMA C6CONTROL: PROT1 Mask         */
-#define GPDMA_C6CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C6CONTROL: PROT2 Position     */
-#define GPDMA_C6CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT2_Pos)                     /*!< GPDMA C6CONTROL: PROT2 Mask         */
-#define GPDMA_C6CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C6CONTROL: PROT3 Position     */
-#define GPDMA_C6CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT3_Pos)                     /*!< GPDMA C6CONTROL: PROT3 Mask         */
-#define GPDMA_C6CONTROL_I_Pos                                 31                                                        /*!< GPDMA C6CONTROL: I Position         */
-#define GPDMA_C6CONTROL_I_Msk                                 (0x01UL << GPDMA_C6CONTROL_I_Pos)                         /*!< GPDMA C6CONTROL: I Mask             */
-
-// -------------------------------------  GPDMA_C6CONFIG  -----------------------------------------
-#define GPDMA_C6CONFIG_E_Pos                                  0                                                         /*!< GPDMA C6CONFIG: E Position          */
-#define GPDMA_C6CONFIG_E_Msk                                  (0x01UL << GPDMA_C6CONFIG_E_Pos)                          /*!< GPDMA C6CONFIG: E Mask              */
-#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */
-#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask  */
-#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */
-#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */
-#define GPDMA_C6CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C6CONFIG: FLOWCNTRL Position  */
-#define GPDMA_C6CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C6CONFIG: FLOWCNTRL Mask      */
-#define GPDMA_C6CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C6CONFIG: IE Position         */
-#define GPDMA_C6CONFIG_IE_Msk                                 (0x01UL << GPDMA_C6CONFIG_IE_Pos)                         /*!< GPDMA C6CONFIG: IE Mask             */
-#define GPDMA_C6CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C6CONFIG: ITC Position        */
-#define GPDMA_C6CONFIG_ITC_Msk                                (0x01UL << GPDMA_C6CONFIG_ITC_Pos)                        /*!< GPDMA C6CONFIG: ITC Mask            */
-#define GPDMA_C6CONFIG_L_Pos                                  16                                                        /*!< GPDMA C6CONFIG: L Position          */
-#define GPDMA_C6CONFIG_L_Msk                                  (0x01UL << GPDMA_C6CONFIG_L_Pos)                          /*!< GPDMA C6CONFIG: L Mask              */
-#define GPDMA_C6CONFIG_A_Pos                                  17                                                        /*!< GPDMA C6CONFIG: A Position          */
-#define GPDMA_C6CONFIG_A_Msk                                  (0x01UL << GPDMA_C6CONFIG_A_Pos)                          /*!< GPDMA C6CONFIG: A Mask              */
-#define GPDMA_C6CONFIG_H_Pos                                  18                                                        /*!< GPDMA C6CONFIG: H Position          */
-#define GPDMA_C6CONFIG_H_Msk                                  (0x01UL << GPDMA_C6CONFIG_H_Pos)                          /*!< GPDMA C6CONFIG: H Mask              */
-
-// -------------------------------------  GPDMA_C7SRCADDR  ----------------------------------------
-#define GPDMA_C7SRCADDR_SRCADDR_Pos                           0                                                         /*!< GPDMA C7SRCADDR: SRCADDR Position   */
-#define GPDMA_C7SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos)             /*!< GPDMA C7SRCADDR: SRCADDR Mask       */
-
-// ------------------------------------  GPDMA_C7DESTADDR  ----------------------------------------
-#define GPDMA_C7DESTADDR_DESTADDR_Pos                         0                                                         /*!< GPDMA C7DESTADDR: DESTADDR Position */
-#define GPDMA_C7DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos)           /*!< GPDMA C7DESTADDR: DESTADDR Mask     */
-
-// ---------------------------------------  GPDMA_C7LLI  ------------------------------------------
-#define GPDMA_C7LLI_LM_Pos                                    0                                                         /*!< GPDMA C7LLI: LM Position            */
-#define GPDMA_C7LLI_LM_Msk                                    (0x01UL << GPDMA_C7LLI_LM_Pos)                            /*!< GPDMA C7LLI: LM Mask                */
-#define GPDMA_C7LLI_R_Pos                                     1                                                         /*!< GPDMA C7LLI: R Position             */
-#define GPDMA_C7LLI_R_Msk                                     (0x01UL << GPDMA_C7LLI_R_Pos)                             /*!< GPDMA C7LLI: R Mask                 */
-#define GPDMA_C7LLI_LLI_Pos                                   2                                                         /*!< GPDMA C7LLI: LLI Position           */
-#define GPDMA_C7LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos)                     /*!< GPDMA C7LLI: LLI Mask               */
-
-// -------------------------------------  GPDMA_C7CONTROL  ----------------------------------------
-#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos                      0                                                         /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */
-#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos)        /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask  */
-#define GPDMA_C7CONTROL_SBSIZE_Pos                            12                                                        /*!< GPDMA C7CONTROL: SBSIZE Position    */
-#define GPDMA_C7CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos)                    /*!< GPDMA C7CONTROL: SBSIZE Mask        */
-#define GPDMA_C7CONTROL_DBSIZE_Pos                            15                                                        /*!< GPDMA C7CONTROL: DBSIZE Position    */
-#define GPDMA_C7CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos)                    /*!< GPDMA C7CONTROL: DBSIZE Mask        */
-#define GPDMA_C7CONTROL_SWIDTH_Pos                            18                                                        /*!< GPDMA C7CONTROL: SWIDTH Position    */
-#define GPDMA_C7CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos)                    /*!< GPDMA C7CONTROL: SWIDTH Mask        */
-#define GPDMA_C7CONTROL_DWIDTH_Pos                            21                                                        /*!< GPDMA C7CONTROL: DWIDTH Position    */
-#define GPDMA_C7CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos)                    /*!< GPDMA C7CONTROL: DWIDTH Mask        */
-#define GPDMA_C7CONTROL_S_Pos                                 24                                                        /*!< GPDMA C7CONTROL: S Position         */
-#define GPDMA_C7CONTROL_S_Msk                                 (0x01UL << GPDMA_C7CONTROL_S_Pos)                         /*!< GPDMA C7CONTROL: S Mask             */
-#define GPDMA_C7CONTROL_D_Pos                                 25                                                        /*!< GPDMA C7CONTROL: D Position         */
-#define GPDMA_C7CONTROL_D_Msk                                 (0x01UL << GPDMA_C7CONTROL_D_Pos)                         /*!< GPDMA C7CONTROL: D Mask             */
-#define GPDMA_C7CONTROL_SI_Pos                                26                                                        /*!< GPDMA C7CONTROL: SI Position        */
-#define GPDMA_C7CONTROL_SI_Msk                                (0x01UL << GPDMA_C7CONTROL_SI_Pos)                        /*!< GPDMA C7CONTROL: SI Mask            */
-#define GPDMA_C7CONTROL_DI_Pos                                27                                                        /*!< GPDMA C7CONTROL: DI Position        */
-#define GPDMA_C7CONTROL_DI_Msk                                (0x01UL << GPDMA_C7CONTROL_DI_Pos)                        /*!< GPDMA C7CONTROL: DI Mask            */
-#define GPDMA_C7CONTROL_PROT1_Pos                             28                                                        /*!< GPDMA C7CONTROL: PROT1 Position     */
-#define GPDMA_C7CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT1_Pos)                     /*!< GPDMA C7CONTROL: PROT1 Mask         */
-#define GPDMA_C7CONTROL_PROT2_Pos                             29                                                        /*!< GPDMA C7CONTROL: PROT2 Position     */
-#define GPDMA_C7CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT2_Pos)                     /*!< GPDMA C7CONTROL: PROT2 Mask         */
-#define GPDMA_C7CONTROL_PROT3_Pos                             30                                                        /*!< GPDMA C7CONTROL: PROT3 Position     */
-#define GPDMA_C7CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT3_Pos)                     /*!< GPDMA C7CONTROL: PROT3 Mask         */
-#define GPDMA_C7CONTROL_I_Pos                                 31                                                        /*!< GPDMA C7CONTROL: I Position         */
-#define GPDMA_C7CONTROL_I_Msk                                 (0x01UL << GPDMA_C7CONTROL_I_Pos)                         /*!< GPDMA C7CONTROL: I Mask             */
-
-// -------------------------------------  GPDMA_C7CONFIG  -----------------------------------------
-#define GPDMA_C7CONFIG_E_Pos                                  0                                                         /*!< GPDMA C7CONFIG: E Position          */
-#define GPDMA_C7CONFIG_E_Msk                                  (0x01UL << GPDMA_C7CONFIG_E_Pos)                          /*!< GPDMA C7CONFIG: E Mask              */
-#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos                      1                                                         /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */
-#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos)              /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask  */
-#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos                     6                                                         /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */
-#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos)             /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */
-#define GPDMA_C7CONFIG_FLOWCNTRL_Pos                          11                                                        /*!< GPDMA C7CONFIG: FLOWCNTRL Position  */
-#define GPDMA_C7CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos)                  /*!< GPDMA C7CONFIG: FLOWCNTRL Mask      */
-#define GPDMA_C7CONFIG_IE_Pos                                 14                                                        /*!< GPDMA C7CONFIG: IE Position         */
-#define GPDMA_C7CONFIG_IE_Msk                                 (0x01UL << GPDMA_C7CONFIG_IE_Pos)                         /*!< GPDMA C7CONFIG: IE Mask             */
-#define GPDMA_C7CONFIG_ITC_Pos                                15                                                        /*!< GPDMA C7CONFIG: ITC Position        */
-#define GPDMA_C7CONFIG_ITC_Msk                                (0x01UL << GPDMA_C7CONFIG_ITC_Pos)                        /*!< GPDMA C7CONFIG: ITC Mask            */
-#define GPDMA_C7CONFIG_L_Pos                                  16                                                        /*!< GPDMA C7CONFIG: L Position          */
-#define GPDMA_C7CONFIG_L_Msk                                  (0x01UL << GPDMA_C7CONFIG_L_Pos)                          /*!< GPDMA C7CONFIG: L Mask              */
-#define GPDMA_C7CONFIG_A_Pos                                  17                                                        /*!< GPDMA C7CONFIG: A Position          */
-#define GPDMA_C7CONFIG_A_Msk                                  (0x01UL << GPDMA_C7CONFIG_A_Pos)                          /*!< GPDMA C7CONFIG: A Mask              */
-#define GPDMA_C7CONFIG_H_Pos                                  18                                                        /*!< GPDMA C7CONFIG: H Position          */
-#define GPDMA_C7CONFIG_H_Msk                                  (0x01UL << GPDMA_C7CONFIG_H_Pos)                          /*!< GPDMA C7CONFIG: H Mask              */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 SDMMC Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  SDMMC_CTRL  -------------------------------------------
-#define SDMMC_CTRL_CONTROLLER_RESET_Pos                       0                                                         /*!< SDMMC CTRL: CONTROLLER_RESET Position */
-#define SDMMC_CTRL_CONTROLLER_RESET_Msk                       (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos)               /*!< SDMMC CTRL: CONTROLLER_RESET Mask   */
-#define SDMMC_CTRL_FIFO_RESET_Pos                             1                                                         /*!< SDMMC CTRL: FIFO_RESET Position     */
-#define SDMMC_CTRL_FIFO_RESET_Msk                             (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos)                     /*!< SDMMC CTRL: FIFO_RESET Mask         */
-#define SDMMC_CTRL_DMA_RESET_Pos                              2                                                         /*!< SDMMC CTRL: DMA_RESET Position      */
-#define SDMMC_CTRL_DMA_RESET_Msk                              (0x01UL << SDMMC_CTRL_DMA_RESET_Pos)                      /*!< SDMMC CTRL: DMA_RESET Mask          */
-#define SDMMC_CTRL_INT_ENABLE_Pos                             4                                                         /*!< SDMMC CTRL: INT_ENABLE Position     */
-#define SDMMC_CTRL_INT_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos)                     /*!< SDMMC CTRL: INT_ENABLE Mask         */
-#define SDMMC_CTRL_DMA_ENABLE_Pos                             5                                                         /*!< SDMMC CTRL: DMA_ENABLE Position     */
-#define SDMMC_CTRL_DMA_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos)                     /*!< SDMMC CTRL: DMA_ENABLE Mask         */
-#define SDMMC_CTRL_READ_WAIT_Pos                              6                                                         /*!< SDMMC CTRL: READ_WAIT Position      */
-#define SDMMC_CTRL_READ_WAIT_Msk                              (0x01UL << SDMMC_CTRL_READ_WAIT_Pos)                      /*!< SDMMC CTRL: READ_WAIT Mask          */
-#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos                      7                                                         /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */
-#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk                      (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos)              /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask  */
-#define SDMMC_CTRL_ABORT_READ_DATA_Pos                        8                                                         /*!< SDMMC CTRL: ABORT_READ_DATA Position */
-#define SDMMC_CTRL_ABORT_READ_DATA_Msk                        (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos)                /*!< SDMMC CTRL: ABORT_READ_DATA Mask    */
-#define SDMMC_CTRL_SEND_CCSD_Pos                              9                                                         /*!< SDMMC CTRL: SEND_CCSD Position      */
-#define SDMMC_CTRL_SEND_CCSD_Msk                              (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos)                      /*!< SDMMC CTRL: SEND_CCSD Mask          */
-#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos                    10                                                        /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Position */
-#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk                    (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos)            /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Mask */
-#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos          11                                                        /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */
-#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk          (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos)  /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */
-#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos                         16                                                        /*!< SDMMC CTRL: CARD_VOLTAGE_A Position */
-#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos)                 /*!< SDMMC CTRL: CARD_VOLTAGE_A Mask     */
-#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos                         20                                                        /*!< SDMMC CTRL: CARD_VOLTAGE_B Position */
-#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos)                 /*!< SDMMC CTRL: CARD_VOLTAGE_B Mask     */
-#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos                       24                                                        /*!< SDMMC CTRL: ENABLE_OD_PULLUP Position */
-#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk                       (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos)               /*!< SDMMC CTRL: ENABLE_OD_PULLUP Mask   */
-#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos                      25                                                        /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */
-#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk                      (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos)              /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask  */
-
-// ---------------------------------------  SDMMC_PWREN  ------------------------------------------
-#define SDMMC_PWREN_POWER_ENABLE_Pos                          0                                                         /*!< SDMMC PWREN: POWER_ENABLE Position  */
-#define SDMMC_PWREN_POWER_ENABLE_Msk                          (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos)            /*!< SDMMC PWREN: POWER_ENABLE Mask      */
-
-// --------------------------------------  SDMMC_CLKDIV  ------------------------------------------
-#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos                         0                                                         /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */
-#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask     */
-#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos                         8                                                         /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */
-#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask     */
-#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos                         16                                                        /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */
-#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask     */
-#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos                         24                                                        /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */
-#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos)           /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask     */
-
-// --------------------------------------  SDMMC_CLKSRC  ------------------------------------------
-#define SDMMC_CLKSRC_CLK_SOURCE_Pos                           0                                                         /*!< SDMMC CLKSRC: CLK_SOURCE Position   */
-#define SDMMC_CLKSRC_CLK_SOURCE_Msk                           (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos)             /*!< SDMMC CLKSRC: CLK_SOURCE Mask       */
-
-// --------------------------------------  SDMMC_CLKENA  ------------------------------------------
-#define SDMMC_CLKENA_CCLK_ENABLE_Pos                          0                                                         /*!< SDMMC CLKENA: CCLK_ENABLE Position  */
-#define SDMMC_CLKENA_CCLK_ENABLE_Msk                          (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos)            /*!< SDMMC CLKENA: CCLK_ENABLE Mask      */
-#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos                       16                                                        /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */
-#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk                       (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos)         /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask   */
-
-// ---------------------------------------  SDMMC_TMOUT  ------------------------------------------
-#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos                      0                                                         /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */
-#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk                      (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos)        /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask  */
-#define SDMMC_TMOUT_DATA_TIMEOUT_Pos                          8                                                         /*!< SDMMC TMOUT: DATA_TIMEOUT Position  */
-#define SDMMC_TMOUT_DATA_TIMEOUT_Msk                          (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos)            /*!< SDMMC TMOUT: DATA_TIMEOUT Mask      */
-
-// ---------------------------------------  SDMMC_CTYPE  ------------------------------------------
-#define SDMMC_CTYPE_CARD_WIDTH0_Pos                           0                                                         /*!< SDMMC CTYPE: CARD_WIDTH0 Position   */
-#define SDMMC_CTYPE_CARD_WIDTH0_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos)             /*!< SDMMC CTYPE: CARD_WIDTH0 Mask       */
-#define SDMMC_CTYPE_CARD_WIDTH1_Pos                           16                                                        /*!< SDMMC CTYPE: CARD_WIDTH1 Position   */
-#define SDMMC_CTYPE_CARD_WIDTH1_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos)             /*!< SDMMC CTYPE: CARD_WIDTH1 Mask       */
-
-// --------------------------------------  SDMMC_BLKSIZ  ------------------------------------------
-#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos                           0                                                         /*!< SDMMC BLKSIZ: BLOCK_SIZE Position   */
-#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk                           (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos)             /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask       */
-
-// --------------------------------------  SDMMC_BYTCNT  ------------------------------------------
-#define SDMMC_BYTCNT_BYTE_COUNT_Pos                           0                                                         /*!< SDMMC BYTCNT: BYTE_COUNT Position   */
-#define SDMMC_BYTCNT_BYTE_COUNT_Msk                           (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos)             /*!< SDMMC BYTCNT: BYTE_COUNT Mask       */
-
-// --------------------------------------  SDMMC_INTMASK  -----------------------------------------
-#define SDMMC_INTMASK_CDET_Pos                                0                                                         /*!< SDMMC INTMASK: CDET Position        */
-#define SDMMC_INTMASK_CDET_Msk                                (0x01UL << SDMMC_INTMASK_CDET_Pos)                        /*!< SDMMC INTMASK: CDET Mask            */
-#define SDMMC_INTMASK_RE_Pos                                  1                                                         /*!< SDMMC INTMASK: RE Position          */
-#define SDMMC_INTMASK_RE_Msk                                  (0x01UL << SDMMC_INTMASK_RE_Pos)                          /*!< SDMMC INTMASK: RE Mask              */
-#define SDMMC_INTMASK_CDONE_Pos                               2                                                         /*!< SDMMC INTMASK: CDONE Position       */
-#define SDMMC_INTMASK_CDONE_Msk                               (0x01UL << SDMMC_INTMASK_CDONE_Pos)                       /*!< SDMMC INTMASK: CDONE Mask           */
-#define SDMMC_INTMASK_DTO_Pos                                 3                                                         /*!< SDMMC INTMASK: DTO Position         */
-#define SDMMC_INTMASK_DTO_Msk                                 (0x01UL << SDMMC_INTMASK_DTO_Pos)                         /*!< SDMMC INTMASK: DTO Mask             */
-#define SDMMC_INTMASK_TXDR_Pos                                4                                                         /*!< SDMMC INTMASK: TXDR Position        */
-#define SDMMC_INTMASK_TXDR_Msk                                (0x01UL << SDMMC_INTMASK_TXDR_Pos)                        /*!< SDMMC INTMASK: TXDR Mask            */
-#define SDMMC_INTMASK_RXDR_Pos                                5                                                         /*!< SDMMC INTMASK: RXDR Position        */
-#define SDMMC_INTMASK_RXDR_Msk                                (0x01UL << SDMMC_INTMASK_RXDR_Pos)                        /*!< SDMMC INTMASK: RXDR Mask            */
-#define SDMMC_INTMASK_RCRC_Pos                                6                                                         /*!< SDMMC INTMASK: RCRC Position        */
-#define SDMMC_INTMASK_RCRC_Msk                                (0x01UL << SDMMC_INTMASK_RCRC_Pos)                        /*!< SDMMC INTMASK: RCRC Mask            */
-#define SDMMC_INTMASK_DCRC_Pos                                7                                                         /*!< SDMMC INTMASK: DCRC Position        */
-#define SDMMC_INTMASK_DCRC_Msk                                (0x01UL << SDMMC_INTMASK_DCRC_Pos)                        /*!< SDMMC INTMASK: DCRC Mask            */
-#define SDMMC_INTMASK_RTO_Pos                                 8                                                         /*!< SDMMC INTMASK: RTO Position         */
-#define SDMMC_INTMASK_RTO_Msk                                 (0x01UL << SDMMC_INTMASK_RTO_Pos)                         /*!< SDMMC INTMASK: RTO Mask             */
-#define SDMMC_INTMASK_DRTO_Pos                                9                                                         /*!< SDMMC INTMASK: DRTO Position        */
-#define SDMMC_INTMASK_DRTO_Msk                                (0x01UL << SDMMC_INTMASK_DRTO_Pos)                        /*!< SDMMC INTMASK: DRTO Mask            */
-#define SDMMC_INTMASK_HTO_Pos                                 10                                                        /*!< SDMMC INTMASK: HTO Position         */
-#define SDMMC_INTMASK_HTO_Msk                                 (0x01UL << SDMMC_INTMASK_HTO_Pos)                         /*!< SDMMC INTMASK: HTO Mask             */
-#define SDMMC_INTMASK_FRUN_Pos                                11                                                        /*!< SDMMC INTMASK: FRUN Position        */
-#define SDMMC_INTMASK_FRUN_Msk                                (0x01UL << SDMMC_INTMASK_FRUN_Pos)                        /*!< SDMMC INTMASK: FRUN Mask            */
-#define SDMMC_INTMASK_HLE_Pos                                 12                                                        /*!< SDMMC INTMASK: HLE Position         */
-#define SDMMC_INTMASK_HLE_Msk                                 (0x01UL << SDMMC_INTMASK_HLE_Pos)                         /*!< SDMMC INTMASK: HLE Mask             */
-#define SDMMC_INTMASK_SBE_Pos                                 13                                                        /*!< SDMMC INTMASK: SBE Position         */
-#define SDMMC_INTMASK_SBE_Msk                                 (0x01UL << SDMMC_INTMASK_SBE_Pos)                         /*!< SDMMC INTMASK: SBE Mask             */
-#define SDMMC_INTMASK_ACD_Pos                                 14                                                        /*!< SDMMC INTMASK: ACD Position         */
-#define SDMMC_INTMASK_ACD_Msk                                 (0x01UL << SDMMC_INTMASK_ACD_Pos)                         /*!< SDMMC INTMASK: ACD Mask             */
-#define SDMMC_INTMASK_EBE_Pos                                 15                                                        /*!< SDMMC INTMASK: EBE Position         */
-#define SDMMC_INTMASK_EBE_Msk                                 (0x01UL << SDMMC_INTMASK_EBE_Pos)                         /*!< SDMMC INTMASK: EBE Mask             */
-#define SDMMC_INTMASK_SDIO_INT_MASK_Pos                       16                                                        /*!< SDMMC INTMASK: SDIO_INT_MASK Position */
-#define SDMMC_INTMASK_SDIO_INT_MASK_Msk                       (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos)         /*!< SDMMC INTMASK: SDIO_INT_MASK Mask   */
-
-// --------------------------------------  SDMMC_CMDARG  ------------------------------------------
-#define SDMMC_CMDARG_CMD_ARG_Pos                              0                                                         /*!< SDMMC CMDARG: CMD_ARG Position      */
-#define SDMMC_CMDARG_CMD_ARG_Msk                              (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos)                /*!< SDMMC CMDARG: CMD_ARG Mask          */
-
-// ----------------------------------------  SDMMC_CMD  -------------------------------------------
-#define SDMMC_CMD_CMD_INDEX_Pos                               0                                                         /*!< SDMMC CMD: CMD_INDEX Position       */
-#define SDMMC_CMD_CMD_INDEX_Msk                               (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos)                       /*!< SDMMC CMD: CMD_INDEX Mask           */
-#define SDMMC_CMD_RESPONSE_EXPECT_Pos                         6                                                         /*!< SDMMC CMD: RESPONSE_EXPECT Position */
-#define SDMMC_CMD_RESPONSE_EXPECT_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos)                 /*!< SDMMC CMD: RESPONSE_EXPECT Mask     */
-#define SDMMC_CMD_RESPONSE_LENGTH_Pos                         7                                                         /*!< SDMMC CMD: RESPONSE_LENGTH Position */
-#define SDMMC_CMD_RESPONSE_LENGTH_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos)                 /*!< SDMMC CMD: RESPONSE_LENGTH Mask     */
-#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos                      8                                                         /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */
-#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk                      (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos)              /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask  */
-#define SDMMC_CMD_DATA_EXPECTED_Pos                           9                                                         /*!< SDMMC CMD: DATA_EXPECTED Position   */
-#define SDMMC_CMD_DATA_EXPECTED_Msk                           (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos)                   /*!< SDMMC CMD: DATA_EXPECTED Mask       */
-#define SDMMC_CMD_READ_WRITE_Pos                              10                                                        /*!< SDMMC CMD: READ_WRITE Position      */
-#define SDMMC_CMD_READ_WRITE_Msk                              (0x01UL << SDMMC_CMD_READ_WRITE_Pos)                      /*!< SDMMC CMD: READ_WRITE Mask          */
-#define SDMMC_CMD_TRANSFER_MODE_Pos                           11                                                        /*!< SDMMC CMD: TRANSFER_MODE Position   */
-#define SDMMC_CMD_TRANSFER_MODE_Msk                           (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos)                   /*!< SDMMC CMD: TRANSFER_MODE Mask       */
-#define SDMMC_CMD_SEND_AUTO_STOP_Pos                          12                                                        /*!< SDMMC CMD: SEND_AUTO_STOP Position  */
-#define SDMMC_CMD_SEND_AUTO_STOP_Msk                          (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos)                  /*!< SDMMC CMD: SEND_AUTO_STOP Mask      */
-#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos                   13                                                        /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */
-#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk                   (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos)           /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */
-#define SDMMC_CMD_STOP_ABORT_CMd_Pos                          14                                                        /*!< SDMMC CMD: STOP_ABORT_CMd Position  */
-#define SDMMC_CMD_STOP_ABORT_CMd_Msk                          (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos)                  /*!< SDMMC CMD: STOP_ABORT_CMd Mask      */
-#define SDMMC_CMD_SEND_INITIALIZATION_Pos                     15                                                        /*!< SDMMC CMD: SEND_INITIALIZATION Position */
-#define SDMMC_CMD_SEND_INITIALIZATION_Msk                     (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos)             /*!< SDMMC CMD: SEND_INITIALIZATION Mask */
-#define SDMMC_CMD_CARD_NUMBER_Pos                             16                                                        /*!< SDMMC CMD: CARD_NUMBER Position     */
-#define SDMMC_CMD_CARD_NUMBER_Msk                             (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos)                     /*!< SDMMC CMD: CARD_NUMBER Mask         */
-#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos             21                                                        /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */
-#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk             (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos)     /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */
-#define SDMMC_CMD_READ_CEATA_DEVICE_Pos                       22                                                        /*!< SDMMC CMD: READ_CEATA_DEVICE Position */
-#define SDMMC_CMD_READ_CEATA_DEVICE_Msk                       (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos)               /*!< SDMMC CMD: READ_CEATA_DEVICE Mask   */
-#define SDMMC_CMD_CCS_EXPECTED_Pos                            23                                                        /*!< SDMMC CMD: CCS_EXPECTED Position    */
-#define SDMMC_CMD_CCS_EXPECTED_Msk                            (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos)                    /*!< SDMMC CMD: CCS_EXPECTED Mask        */
-#define SDMMC_CMD_ENABLE_BOOT_Pos                             24                                                        /*!< SDMMC CMD: ENABLE_BOOT Position     */
-#define SDMMC_CMD_ENABLE_BOOT_Msk                             (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos)                     /*!< SDMMC CMD: ENABLE_BOOT Mask         */
-#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos                         25                                                        /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */
-#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk                         (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos)                 /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask     */
-#define SDMMC_CMD_DISABLE_BOOT_Pos                            26                                                        /*!< SDMMC CMD: DISABLE_BOOT Position    */
-#define SDMMC_CMD_DISABLE_BOOT_Msk                            (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos)                    /*!< SDMMC CMD: DISABLE_BOOT Mask        */
-#define SDMMC_CMD_BOOT_MODE_Pos                               27                                                        /*!< SDMMC CMD: BOOT_MODE Position       */
-#define SDMMC_CMD_BOOT_MODE_Msk                               (0x01UL << SDMMC_CMD_BOOT_MODE_Pos)                       /*!< SDMMC CMD: BOOT_MODE Mask           */
-#define SDMMC_CMD_VOLT_SWITCH_Pos                             28                                                        /*!< SDMMC CMD: VOLT_SWITCH Position     */
-#define SDMMC_CMD_VOLT_SWITCH_Msk                             (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos)                     /*!< SDMMC CMD: VOLT_SWITCH Mask         */
-#define SDMMC_CMD_START_CMD_Pos                               31                                                        /*!< SDMMC CMD: START_CMD Position       */
-#define SDMMC_CMD_START_CMD_Msk                               (0x01UL << SDMMC_CMD_START_CMD_Pos)                       /*!< SDMMC CMD: START_CMD Mask           */
-
-// ---------------------------------------  SDMMC_RESP0  ------------------------------------------
-#define SDMMC_RESP0_RESPONSE0_Pos                             0                                                         /*!< SDMMC RESP0: RESPONSE0 Position     */
-#define SDMMC_RESP0_RESPONSE0_Msk                             (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos)               /*!< SDMMC RESP0: RESPONSE0 Mask         */
-
-// ---------------------------------------  SDMMC_RESP1  ------------------------------------------
-#define SDMMC_RESP1_RESPONSE1_Pos                             0                                                         /*!< SDMMC RESP1: RESPONSE1 Position     */
-#define SDMMC_RESP1_RESPONSE1_Msk                             (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos)               /*!< SDMMC RESP1: RESPONSE1 Mask         */
-
-// ---------------------------------------  SDMMC_RESP2  ------------------------------------------
-#define SDMMC_RESP2_RESPONSE2_Pos                             0                                                         /*!< SDMMC RESP2: RESPONSE2 Position     */
-#define SDMMC_RESP2_RESPONSE2_Msk                             (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos)               /*!< SDMMC RESP2: RESPONSE2 Mask         */
-
-// ---------------------------------------  SDMMC_RESP3  ------------------------------------------
-#define SDMMC_RESP3_RESPONSE3_Pos                             0                                                         /*!< SDMMC RESP3: RESPONSE3 Position     */
-#define SDMMC_RESP3_RESPONSE3_Msk                             (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos)               /*!< SDMMC RESP3: RESPONSE3 Mask         */
-
-// --------------------------------------  SDMMC_MINTSTS  -----------------------------------------
-#define SDMMC_MINTSTS_CDET_Pos                                0                                                         /*!< SDMMC MINTSTS: CDET Position        */
-#define SDMMC_MINTSTS_CDET_Msk                                (0x01UL << SDMMC_MINTSTS_CDET_Pos)                        /*!< SDMMC MINTSTS: CDET Mask            */
-#define SDMMC_MINTSTS_RE_Pos                                  1                                                         /*!< SDMMC MINTSTS: RE Position          */
-#define SDMMC_MINTSTS_RE_Msk                                  (0x01UL << SDMMC_MINTSTS_RE_Pos)                          /*!< SDMMC MINTSTS: RE Mask              */
-#define SDMMC_MINTSTS_CDONE_Pos                               2                                                         /*!< SDMMC MINTSTS: CDONE Position       */
-#define SDMMC_MINTSTS_CDONE_Msk                               (0x01UL << SDMMC_MINTSTS_CDONE_Pos)                       /*!< SDMMC MINTSTS: CDONE Mask           */
-#define SDMMC_MINTSTS_DTO_Pos                                 3                                                         /*!< SDMMC MINTSTS: DTO Position         */
-#define SDMMC_MINTSTS_DTO_Msk                                 (0x01UL << SDMMC_MINTSTS_DTO_Pos)                         /*!< SDMMC MINTSTS: DTO Mask             */
-#define SDMMC_MINTSTS_TXDR_Pos                                4                                                         /*!< SDMMC MINTSTS: TXDR Position        */
-#define SDMMC_MINTSTS_TXDR_Msk                                (0x01UL << SDMMC_MINTSTS_TXDR_Pos)                        /*!< SDMMC MINTSTS: TXDR Mask            */
-#define SDMMC_MINTSTS_RXDR_Pos                                5                                                         /*!< SDMMC MINTSTS: RXDR Position        */
-#define SDMMC_MINTSTS_RXDR_Msk                                (0x01UL << SDMMC_MINTSTS_RXDR_Pos)                        /*!< SDMMC MINTSTS: RXDR Mask            */
-#define SDMMC_MINTSTS_RCRC_Pos                                6                                                         /*!< SDMMC MINTSTS: RCRC Position        */
-#define SDMMC_MINTSTS_RCRC_Msk                                (0x01UL << SDMMC_MINTSTS_RCRC_Pos)                        /*!< SDMMC MINTSTS: RCRC Mask            */
-#define SDMMC_MINTSTS_DCRC_Pos                                7                                                         /*!< SDMMC MINTSTS: DCRC Position        */
-#define SDMMC_MINTSTS_DCRC_Msk                                (0x01UL << SDMMC_MINTSTS_DCRC_Pos)                        /*!< SDMMC MINTSTS: DCRC Mask            */
-#define SDMMC_MINTSTS_RTO_Pos                                 8                                                         /*!< SDMMC MINTSTS: RTO Position         */
-#define SDMMC_MINTSTS_RTO_Msk                                 (0x01UL << SDMMC_MINTSTS_RTO_Pos)                         /*!< SDMMC MINTSTS: RTO Mask             */
-#define SDMMC_MINTSTS_DRTO_Pos                                9                                                         /*!< SDMMC MINTSTS: DRTO Position        */
-#define SDMMC_MINTSTS_DRTO_Msk                                (0x01UL << SDMMC_MINTSTS_DRTO_Pos)                        /*!< SDMMC MINTSTS: DRTO Mask            */
-#define SDMMC_MINTSTS_HTO_Pos                                 10                                                        /*!< SDMMC MINTSTS: HTO Position         */
-#define SDMMC_MINTSTS_HTO_Msk                                 (0x01UL << SDMMC_MINTSTS_HTO_Pos)                         /*!< SDMMC MINTSTS: HTO Mask             */
-#define SDMMC_MINTSTS_FRUN_Pos                                11                                                        /*!< SDMMC MINTSTS: FRUN Position        */
-#define SDMMC_MINTSTS_FRUN_Msk                                (0x01UL << SDMMC_MINTSTS_FRUN_Pos)                        /*!< SDMMC MINTSTS: FRUN Mask            */
-#define SDMMC_MINTSTS_HLE_Pos                                 12                                                        /*!< SDMMC MINTSTS: HLE Position         */
-#define SDMMC_MINTSTS_HLE_Msk                                 (0x01UL << SDMMC_MINTSTS_HLE_Pos)                         /*!< SDMMC MINTSTS: HLE Mask             */
-#define SDMMC_MINTSTS_SBE_Pos                                 13                                                        /*!< SDMMC MINTSTS: SBE Position         */
-#define SDMMC_MINTSTS_SBE_Msk                                 (0x01UL << SDMMC_MINTSTS_SBE_Pos)                         /*!< SDMMC MINTSTS: SBE Mask             */
-#define SDMMC_MINTSTS_ACD_Pos                                 14                                                        /*!< SDMMC MINTSTS: ACD Position         */
-#define SDMMC_MINTSTS_ACD_Msk                                 (0x01UL << SDMMC_MINTSTS_ACD_Pos)                         /*!< SDMMC MINTSTS: ACD Mask             */
-#define SDMMC_MINTSTS_EBE_Pos                                 15                                                        /*!< SDMMC MINTSTS: EBE Position         */
-#define SDMMC_MINTSTS_EBE_Msk                                 (0x01UL << SDMMC_MINTSTS_EBE_Pos)                         /*!< SDMMC MINTSTS: EBE Mask             */
-#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos                      16                                                        /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */
-#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos)        /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask  */
-
-// --------------------------------------  SDMMC_RINTSTS  -----------------------------------------
-#define SDMMC_RINTSTS_CDET_Pos                                0                                                         /*!< SDMMC RINTSTS: CDET Position        */
-#define SDMMC_RINTSTS_CDET_Msk                                (0x01UL << SDMMC_RINTSTS_CDET_Pos)                        /*!< SDMMC RINTSTS: CDET Mask            */
-#define SDMMC_RINTSTS_RE_Pos                                  1                                                         /*!< SDMMC RINTSTS: RE Position          */
-#define SDMMC_RINTSTS_RE_Msk                                  (0x01UL << SDMMC_RINTSTS_RE_Pos)                          /*!< SDMMC RINTSTS: RE Mask              */
-#define SDMMC_RINTSTS_CDONE_Pos                               2                                                         /*!< SDMMC RINTSTS: CDONE Position       */
-#define SDMMC_RINTSTS_CDONE_Msk                               (0x01UL << SDMMC_RINTSTS_CDONE_Pos)                       /*!< SDMMC RINTSTS: CDONE Mask           */
-#define SDMMC_RINTSTS_DTO_Pos                                 3                                                         /*!< SDMMC RINTSTS: DTO Position         */
-#define SDMMC_RINTSTS_DTO_Msk                                 (0x01UL << SDMMC_RINTSTS_DTO_Pos)                         /*!< SDMMC RINTSTS: DTO Mask             */
-#define SDMMC_RINTSTS_TXDR_Pos                                4                                                         /*!< SDMMC RINTSTS: TXDR Position        */
-#define SDMMC_RINTSTS_TXDR_Msk                                (0x01UL << SDMMC_RINTSTS_TXDR_Pos)                        /*!< SDMMC RINTSTS: TXDR Mask            */
-#define SDMMC_RINTSTS_RXDR_Pos                                5                                                         /*!< SDMMC RINTSTS: RXDR Position        */
-#define SDMMC_RINTSTS_RXDR_Msk                                (0x01UL << SDMMC_RINTSTS_RXDR_Pos)                        /*!< SDMMC RINTSTS: RXDR Mask            */
-#define SDMMC_RINTSTS_RCRC_Pos                                6                                                         /*!< SDMMC RINTSTS: RCRC Position        */
-#define SDMMC_RINTSTS_RCRC_Msk                                (0x01UL << SDMMC_RINTSTS_RCRC_Pos)                        /*!< SDMMC RINTSTS: RCRC Mask            */
-#define SDMMC_RINTSTS_DCRC_Pos                                7                                                         /*!< SDMMC RINTSTS: DCRC Position        */
-#define SDMMC_RINTSTS_DCRC_Msk                                (0x01UL << SDMMC_RINTSTS_DCRC_Pos)                        /*!< SDMMC RINTSTS: DCRC Mask            */
-#define SDMMC_RINTSTS_RTO_BAR_Pos                             8                                                         /*!< SDMMC RINTSTS: RTO_BAR Position     */
-#define SDMMC_RINTSTS_RTO_BAR_Msk                             (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos)                     /*!< SDMMC RINTSTS: RTO_BAR Mask         */
-#define SDMMC_RINTSTS_DRTO_BDS_Pos                            9                                                         /*!< SDMMC RINTSTS: DRTO_BDS Position    */
-#define SDMMC_RINTSTS_DRTO_BDS_Msk                            (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos)                    /*!< SDMMC RINTSTS: DRTO_BDS Mask        */
-#define SDMMC_RINTSTS_HTO_Pos                                 10                                                        /*!< SDMMC RINTSTS: HTO Position         */
-#define SDMMC_RINTSTS_HTO_Msk                                 (0x01UL << SDMMC_RINTSTS_HTO_Pos)                         /*!< SDMMC RINTSTS: HTO Mask             */
-#define SDMMC_RINTSTS_FRUN_Pos                                11                                                        /*!< SDMMC RINTSTS: FRUN Position        */
-#define SDMMC_RINTSTS_FRUN_Msk                                (0x01UL << SDMMC_RINTSTS_FRUN_Pos)                        /*!< SDMMC RINTSTS: FRUN Mask            */
-#define SDMMC_RINTSTS_HLE_Pos                                 12                                                        /*!< SDMMC RINTSTS: HLE Position         */
-#define SDMMC_RINTSTS_HLE_Msk                                 (0x01UL << SDMMC_RINTSTS_HLE_Pos)                         /*!< SDMMC RINTSTS: HLE Mask             */
-#define SDMMC_RINTSTS_SBE_Pos                                 13                                                        /*!< SDMMC RINTSTS: SBE Position         */
-#define SDMMC_RINTSTS_SBE_Msk                                 (0x01UL << SDMMC_RINTSTS_SBE_Pos)                         /*!< SDMMC RINTSTS: SBE Mask             */
-#define SDMMC_RINTSTS_ACD_Pos                                 14                                                        /*!< SDMMC RINTSTS: ACD Position         */
-#define SDMMC_RINTSTS_ACD_Msk                                 (0x01UL << SDMMC_RINTSTS_ACD_Pos)                         /*!< SDMMC RINTSTS: ACD Mask             */
-#define SDMMC_RINTSTS_EBE_Pos                                 15                                                        /*!< SDMMC RINTSTS: EBE Position         */
-#define SDMMC_RINTSTS_EBE_Msk                                 (0x01UL << SDMMC_RINTSTS_EBE_Pos)                         /*!< SDMMC RINTSTS: EBE Mask             */
-#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos                      16                                                        /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */
-#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos)        /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask  */
-
-// --------------------------------------  SDMMC_STATUS  ------------------------------------------
-#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos                    0                                                         /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */
-#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos)            /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */
-#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos                    1                                                         /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */
-#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos)            /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */
-#define SDMMC_STATUS_FIFO_EMPTY_Pos                           2                                                         /*!< SDMMC STATUS: FIFO_EMPTY Position   */
-#define SDMMC_STATUS_FIFO_EMPTY_Msk                           (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos)                   /*!< SDMMC STATUS: FIFO_EMPTY Mask       */
-#define SDMMC_STATUS_FIFO_FULL_Pos                            3                                                         /*!< SDMMC STATUS: FIFO_FULL Position    */
-#define SDMMC_STATUS_FIFO_FULL_Msk                            (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos)                    /*!< SDMMC STATUS: FIFO_FULL Mask        */
-#define SDMMC_STATUS_CMDFSMSTATES_Pos                         4                                                         /*!< SDMMC STATUS: CMDFSMSTATES Position */
-#define SDMMC_STATUS_CMDFSMSTATES_Msk                         (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos)                 /*!< SDMMC STATUS: CMDFSMSTATES Mask     */
-#define SDMMC_STATUS_DATA_3_STATUS_Pos                        8                                                         /*!< SDMMC STATUS: DATA_3_STATUS Position */
-#define SDMMC_STATUS_DATA_3_STATUS_Msk                        (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos)                /*!< SDMMC STATUS: DATA_3_STATUS Mask    */
-#define SDMMC_STATUS_DATA_BUSY_Pos                            9                                                         /*!< SDMMC STATUS: DATA_BUSY Position    */
-#define SDMMC_STATUS_DATA_BUSY_Msk                            (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos)                    /*!< SDMMC STATUS: DATA_BUSY Mask        */
-#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos                   10                                                        /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */
-#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk                   (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos)           /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */
-#define SDMMC_STATUS_RESPONSE_INDEX_Pos                       11                                                        /*!< SDMMC STATUS: RESPONSE_INDEX Position */
-#define SDMMC_STATUS_RESPONSE_INDEX_Msk                       (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos)               /*!< SDMMC STATUS: RESPONSE_INDEX Mask   */
-#define SDMMC_STATUS_FIFO_COUNT_Pos                           17                                                        /*!< SDMMC STATUS: FIFO_COUNT Position   */
-#define SDMMC_STATUS_FIFO_COUNT_Msk                           (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos)             /*!< SDMMC STATUS: FIFO_COUNT Mask       */
-#define SDMMC_STATUS_DMA_ACK_Pos                              30                                                        /*!< SDMMC STATUS: DMA_ACK Position      */
-#define SDMMC_STATUS_DMA_ACK_Msk                              (0x01UL << SDMMC_STATUS_DMA_ACK_Pos)                      /*!< SDMMC STATUS: DMA_ACK Mask          */
-#define SDMMC_STATUS_DMA_REQ_Pos                              31                                                        /*!< SDMMC STATUS: DMA_REQ Position      */
-#define SDMMC_STATUS_DMA_REQ_Msk                              (0x01UL << SDMMC_STATUS_DMA_REQ_Pos)                      /*!< SDMMC STATUS: DMA_REQ Mask          */
-
-// --------------------------------------  SDMMC_FIFOTH  ------------------------------------------
-#define SDMMC_FIFOTH_TX_WMARK_Pos                             0                                                         /*!< SDMMC FIFOTH: TX_WMARK Position     */
-#define SDMMC_FIFOTH_TX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos)               /*!< SDMMC FIFOTH: TX_WMARK Mask         */
-#define SDMMC_FIFOTH_RX_WMARK_Pos                             16                                                        /*!< SDMMC FIFOTH: RX_WMARK Position     */
-#define SDMMC_FIFOTH_RX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos)               /*!< SDMMC FIFOTH: RX_WMARK Mask         */
-#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos      28                                                        /*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Position */
-#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk      (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */
-
-// --------------------------------------  SDMMC_CDETECT  -----------------------------------------
-#define SDMMC_CDETECT_CARD_DETECT_N_Pos                       0                                                         /*!< SDMMC CDETECT: CARD_DETECT_N Position */
-#define SDMMC_CDETECT_CARD_DETECT_N_Msk                       (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos)         /*!< SDMMC CDETECT: CARD_DETECT_N Mask   */
-
-// --------------------------------------  SDMMC_WRTPRT  ------------------------------------------
-#define SDMMC_WRTPRT_WRITE_PROTECT_Pos                        0                                                         /*!< SDMMC WRTPRT: WRITE_PROTECT Position */
-#define SDMMC_WRTPRT_WRITE_PROTECT_Msk                        (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos)          /*!< SDMMC WRTPRT: WRITE_PROTECT Mask    */
-
-// ---------------------------------------  SDMMC_GPIO  -------------------------------------------
-#define SDMMC_GPIO_GPI_Pos                                    0                                                         /*!< SDMMC GPIO: GPI Position            */
-#define SDMMC_GPIO_GPI_Msk                                    (0x000000ffUL << SDMMC_GPIO_GPI_Pos)                      /*!< SDMMC GPIO: GPI Mask                */
-#define SDMMC_GPIO_GPO_Pos                                    8                                                         /*!< SDMMC GPIO: GPO Position            */
-#define SDMMC_GPIO_GPO_Msk                                    (0x0000ffffUL << SDMMC_GPIO_GPO_Pos)                      /*!< SDMMC GPIO: GPO Mask                */
-
-// --------------------------------------  SDMMC_TCBCNT  ------------------------------------------
-#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos                0                                                         /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */
-#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos)  /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */
-
-// --------------------------------------  SDMMC_TBBCNT  ------------------------------------------
-#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos                0                                                         /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */
-#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos)  /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */
-
-// --------------------------------------  SDMMC_DEBNCE  ------------------------------------------
-#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos                       0                                                         /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */
-#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk                       (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos)         /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask   */
-
-// ---------------------------------------  SDMMC_USRID  ------------------------------------------
-#define SDMMC_USRID_USRID_Pos                                 0                                                         /*!< SDMMC USRID: USRID Position         */
-#define SDMMC_USRID_USRID_Msk                                 (0xffffffffUL << SDMMC_USRID_USRID_Pos)                   /*!< SDMMC USRID: USRID Mask             */
-
-// ---------------------------------------  SDMMC_VERID  ------------------------------------------
-#define SDMMC_VERID_VERID_Pos                                 0                                                         /*!< SDMMC VERID: VERID Position         */
-#define SDMMC_VERID_VERID_Msk                                 (0xffffffffUL << SDMMC_VERID_VERID_Pos)                   /*!< SDMMC VERID: VERID Mask             */
-
-// --------------------------------------  SDMMC_UHS_REG  -----------------------------------------
-#define SDMMC_UHS_REG_VOLT_REG_Pos                            0                                                         /*!< SDMMC UHS_REG: VOLT_REG Position    */
-#define SDMMC_UHS_REG_VOLT_REG_Msk                            (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos)              /*!< SDMMC UHS_REG: VOLT_REG Mask        */
-#define SDMMC_UHS_REG_DDR_REG_Pos                             16                                                        /*!< SDMMC UHS_REG: DDR_REG Position     */
-#define SDMMC_UHS_REG_DDR_REG_Msk                             (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos)               /*!< SDMMC UHS_REG: DDR_REG Mask         */
-
-// ---------------------------------------  SDMMC_RST_N  ------------------------------------------
-#define SDMMC_RST_N_CARD_RESET_Pos                            0                                                         /*!< SDMMC RST_N: CARD_RESET Position    */
-#define SDMMC_RST_N_CARD_RESET_Msk                            (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos)              /*!< SDMMC RST_N: CARD_RESET Mask        */
-
-// ---------------------------------------  SDMMC_BMOD  -------------------------------------------
-#define SDMMC_BMOD_SWR_Pos                                    0                                                         /*!< SDMMC BMOD: SWR Position            */
-#define SDMMC_BMOD_SWR_Msk                                    (0x01UL << SDMMC_BMOD_SWR_Pos)                            /*!< SDMMC BMOD: SWR Mask                */
-#define SDMMC_BMOD_FB_Pos                                     1                                                         /*!< SDMMC BMOD: FB Position             */
-#define SDMMC_BMOD_FB_Msk                                     (0x01UL << SDMMC_BMOD_FB_Pos)                             /*!< SDMMC BMOD: FB Mask                 */
-#define SDMMC_BMOD_DSL_Pos                                    2                                                         /*!< SDMMC BMOD: DSL Position            */
-#define SDMMC_BMOD_DSL_Msk                                    (0x1fUL << SDMMC_BMOD_DSL_Pos)                            /*!< SDMMC BMOD: DSL Mask                */
-#define SDMMC_BMOD_DE_Pos                                     7                                                         /*!< SDMMC BMOD: DE Position             */
-#define SDMMC_BMOD_DE_Msk                                     (0x01UL << SDMMC_BMOD_DE_Pos)                             /*!< SDMMC BMOD: DE Mask                 */
-#define SDMMC_BMOD_PBL_Pos                                    8                                                         /*!< SDMMC BMOD: PBL Position            */
-#define SDMMC_BMOD_PBL_Msk                                    (0x07UL << SDMMC_BMOD_PBL_Pos)                            /*!< SDMMC BMOD: PBL Mask                */
-
-// --------------------------------------  SDMMC_PLDMND  ------------------------------------------
-#define SDMMC_PLDMND_PD_Pos                                   0                                                         /*!< SDMMC PLDMND: PD Position           */
-#define SDMMC_PLDMND_PD_Msk                                   (0xffffffffUL << SDMMC_PLDMND_PD_Pos)                     /*!< SDMMC PLDMND: PD Mask               */
-
-// --------------------------------------  SDMMC_DBADDR  ------------------------------------------
-#define SDMMC_DBADDR_SDL_Pos                                  0                                                         /*!< SDMMC DBADDR: SDL Position          */
-#define SDMMC_DBADDR_SDL_Msk                                  (0xffffffffUL << SDMMC_DBADDR_SDL_Pos)                    /*!< SDMMC DBADDR: SDL Mask              */
-
-// ---------------------------------------  SDMMC_IDSTS  ------------------------------------------
-#define SDMMC_IDSTS_TI_Pos                                    0                                                         /*!< SDMMC IDSTS: TI Position            */
-#define SDMMC_IDSTS_TI_Msk                                    (0x01UL << SDMMC_IDSTS_TI_Pos)                            /*!< SDMMC IDSTS: TI Mask                */
-#define SDMMC_IDSTS_RI_Pos                                    1                                                         /*!< SDMMC IDSTS: RI Position            */
-#define SDMMC_IDSTS_RI_Msk                                    (0x01UL << SDMMC_IDSTS_RI_Pos)                            /*!< SDMMC IDSTS: RI Mask                */
-#define SDMMC_IDSTS_FBE_Pos                                   2                                                         /*!< SDMMC IDSTS: FBE Position           */
-#define SDMMC_IDSTS_FBE_Msk                                   (0x01UL << SDMMC_IDSTS_FBE_Pos)                           /*!< SDMMC IDSTS: FBE Mask               */
-#define SDMMC_IDSTS_DU_Pos                                    4                                                         /*!< SDMMC IDSTS: DU Position            */
-#define SDMMC_IDSTS_DU_Msk                                    (0x01UL << SDMMC_IDSTS_DU_Pos)                            /*!< SDMMC IDSTS: DU Mask                */
-#define SDMMC_IDSTS_CES_Pos                                   5                                                         /*!< SDMMC IDSTS: CES Position           */
-#define SDMMC_IDSTS_CES_Msk                                   (0x01UL << SDMMC_IDSTS_CES_Pos)                           /*!< SDMMC IDSTS: CES Mask               */
-#define SDMMC_IDSTS_NIS_Pos                                   8                                                         /*!< SDMMC IDSTS: NIS Position           */
-#define SDMMC_IDSTS_NIS_Msk                                   (0x01UL << SDMMC_IDSTS_NIS_Pos)                           /*!< SDMMC IDSTS: NIS Mask               */
-#define SDMMC_IDSTS_AIS_Pos                                   9                                                         /*!< SDMMC IDSTS: AIS Position           */
-#define SDMMC_IDSTS_AIS_Msk                                   (0x01UL << SDMMC_IDSTS_AIS_Pos)                           /*!< SDMMC IDSTS: AIS Mask               */
-#define SDMMC_IDSTS_EB_Pos                                    10                                                        /*!< SDMMC IDSTS: EB Position            */
-#define SDMMC_IDSTS_EB_Msk                                    (0x07UL << SDMMC_IDSTS_EB_Pos)                            /*!< SDMMC IDSTS: EB Mask                */
-#define SDMMC_IDSTS_FSM_Pos                                   13                                                        /*!< SDMMC IDSTS: FSM Position           */
-#define SDMMC_IDSTS_FSM_Msk                                   (0x0fUL << SDMMC_IDSTS_FSM_Pos)                           /*!< SDMMC IDSTS: FSM Mask               */
-
-// --------------------------------------  SDMMC_IDINTEN  -----------------------------------------
-#define SDMMC_IDINTEN_TI_Pos                                  0                                                         /*!< SDMMC IDINTEN: TI Position          */
-#define SDMMC_IDINTEN_TI_Msk                                  (0x01UL << SDMMC_IDINTEN_TI_Pos)                          /*!< SDMMC IDINTEN: TI Mask              */
-#define SDMMC_IDINTEN_RI_Pos                                  1                                                         /*!< SDMMC IDINTEN: RI Position          */
-#define SDMMC_IDINTEN_RI_Msk                                  (0x01UL << SDMMC_IDINTEN_RI_Pos)                          /*!< SDMMC IDINTEN: RI Mask              */
-#define SDMMC_IDINTEN_FBE_Pos                                 2                                                         /*!< SDMMC IDINTEN: FBE Position         */
-#define SDMMC_IDINTEN_FBE_Msk                                 (0x01UL << SDMMC_IDINTEN_FBE_Pos)                         /*!< SDMMC IDINTEN: FBE Mask             */
-#define SDMMC_IDINTEN_DU_Pos                                  4                                                         /*!< SDMMC IDINTEN: DU Position          */
-#define SDMMC_IDINTEN_DU_Msk                                  (0x01UL << SDMMC_IDINTEN_DU_Pos)                          /*!< SDMMC IDINTEN: DU Mask              */
-#define SDMMC_IDINTEN_CES_Pos                                 5                                                         /*!< SDMMC IDINTEN: CES Position         */
-#define SDMMC_IDINTEN_CES_Msk                                 (0x01UL << SDMMC_IDINTEN_CES_Pos)                         /*!< SDMMC IDINTEN: CES Mask             */
-#define SDMMC_IDINTEN_NIS_Pos                                 8                                                         /*!< SDMMC IDINTEN: NIS Position         */
-#define SDMMC_IDINTEN_NIS_Msk                                 (0x01UL << SDMMC_IDINTEN_NIS_Pos)                         /*!< SDMMC IDINTEN: NIS Mask             */
-#define SDMMC_IDINTEN_AIS_Pos                                 9                                                         /*!< SDMMC IDINTEN: AIS Position         */
-#define SDMMC_IDINTEN_AIS_Msk                                 (0x01UL << SDMMC_IDINTEN_AIS_Pos)                         /*!< SDMMC IDINTEN: AIS Mask             */
-
-// --------------------------------------  SDMMC_DSCADDR  -----------------------------------------
-#define SDMMC_DSCADDR_HDA_Pos                                 0                                                         /*!< SDMMC DSCADDR: HDA Position         */
-#define SDMMC_DSCADDR_HDA_Msk                                 (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos)                   /*!< SDMMC DSCADDR: HDA Mask             */
-
-// --------------------------------------  SDMMC_BUFADDR  -----------------------------------------
-#define SDMMC_BUFADDR_HBA_Pos                                 0                                                         /*!< SDMMC BUFADDR: HBA Position         */
-#define SDMMC_BUFADDR_HBA_Msk                                 (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos)                   /*!< SDMMC BUFADDR: HBA Mask             */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  EMC Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  EMC_CONTROL  ------------------------------------------
-#define EMC_CONTROL_E_Pos                                     0                                                         /*!< EMC CONTROL: E Position             */
-#define EMC_CONTROL_E_Msk                                     (0x01UL << EMC_CONTROL_E_Pos)                             /*!< EMC CONTROL: E Mask                 */
-#define EMC_CONTROL_M_Pos                                     1                                                         /*!< EMC CONTROL: M Position             */
-#define EMC_CONTROL_M_Msk                                     (0x01UL << EMC_CONTROL_M_Pos)                             /*!< EMC CONTROL: M Mask                 */
-#define EMC_CONTROL_L_Pos                                     2                                                         /*!< EMC CONTROL: L Position             */
-#define EMC_CONTROL_L_Msk                                     (0x01UL << EMC_CONTROL_L_Pos)                             /*!< EMC CONTROL: L Mask                 */
-
-// ---------------------------------------  EMC_STATUS  -------------------------------------------
-#define EMC_STATUS_B_Pos                                      0                                                         /*!< EMC STATUS: B Position              */
-#define EMC_STATUS_B_Msk                                      (0x01UL << EMC_STATUS_B_Pos)                              /*!< EMC STATUS: B Mask                  */
-#define EMC_STATUS_S_Pos                                      1                                                         /*!< EMC STATUS: S Position              */
-#define EMC_STATUS_S_Msk                                      (0x01UL << EMC_STATUS_S_Pos)                              /*!< EMC STATUS: S Mask                  */
-#define EMC_STATUS_SA_Pos                                     2                                                         /*!< EMC STATUS: SA Position             */
-#define EMC_STATUS_SA_Msk                                     (0x01UL << EMC_STATUS_SA_Pos)                             /*!< EMC STATUS: SA Mask                 */
-
-// ---------------------------------------  EMC_CONFIG  -------------------------------------------
-#define EMC_CONFIG_EM_Pos                                     0                                                         /*!< EMC CONFIG: EM Position             */
-#define EMC_CONFIG_EM_Msk                                     (0x01UL << EMC_CONFIG_EM_Pos)                             /*!< EMC CONFIG: EM Mask                 */
-#define EMC_CONFIG_CR_Pos                                     8                                                         /*!< EMC CONFIG: CR Position             */
-#define EMC_CONFIG_CR_Msk                                     (0x01UL << EMC_CONFIG_CR_Pos)                             /*!< EMC CONFIG: CR Mask                 */
-
-// -----------------------------------  EMC_DYNAMICCONTROL  ---------------------------------------
-#define EMC_DYNAMICCONTROL_CE_Pos                             0                                                         /*!< EMC DYNAMICCONTROL: CE Position     */
-#define EMC_DYNAMICCONTROL_CE_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CE_Pos)                     /*!< EMC DYNAMICCONTROL: CE Mask         */
-#define EMC_DYNAMICCONTROL_CS_Pos                             1                                                         /*!< EMC DYNAMICCONTROL: CS Position     */
-#define EMC_DYNAMICCONTROL_CS_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CS_Pos)                     /*!< EMC DYNAMICCONTROL: CS Mask         */
-#define EMC_DYNAMICCONTROL_SR_Pos                             2                                                         /*!< EMC DYNAMICCONTROL: SR Position     */
-#define EMC_DYNAMICCONTROL_SR_Msk                             (0x01UL << EMC_DYNAMICCONTROL_SR_Pos)                     /*!< EMC DYNAMICCONTROL: SR Mask         */
-#define EMC_DYNAMICCONTROL_MMC_Pos                            5                                                         /*!< EMC DYNAMICCONTROL: MMC Position    */
-#define EMC_DYNAMICCONTROL_MMC_Msk                            (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos)                    /*!< EMC DYNAMICCONTROL: MMC Mask        */
-#define EMC_DYNAMICCONTROL_I_Pos                              7                                                         /*!< EMC DYNAMICCONTROL: I Position      */
-#define EMC_DYNAMICCONTROL_I_Msk                              (0x03UL << EMC_DYNAMICCONTROL_I_Pos)                      /*!< EMC DYNAMICCONTROL: I Mask          */
-#define EMC_DYNAMICCONTROL_DP_Pos                             13                                                        /*!< EMC DYNAMICCONTROL: DP Position     */
-#define EMC_DYNAMICCONTROL_DP_Msk                             (0x01UL << EMC_DYNAMICCONTROL_DP_Pos)                     /*!< EMC DYNAMICCONTROL: DP Mask         */
-
-// -----------------------------------  EMC_DYNAMICREFRESH  ---------------------------------------
-#define EMC_DYNAMICREFRESH_REFRESH_Pos                        0                                                         /*!< EMC DYNAMICREFRESH: REFRESH Position */
-#define EMC_DYNAMICREFRESH_REFRESH_Msk                        (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos)          /*!< EMC DYNAMICREFRESH: REFRESH Mask    */
-
-// ----------------------------------  EMC_DYNAMICREADCONFIG  -------------------------------------
-#define EMC_DYNAMICREADCONFIG_RD_Pos                          0                                                         /*!< EMC DYNAMICREADCONFIG: RD Position  */
-#define EMC_DYNAMICREADCONFIG_RD_Msk                          (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos)                  /*!< EMC DYNAMICREADCONFIG: RD Mask      */
-
-// --------------------------------------  EMC_DYNAMICRP  -----------------------------------------
-#define EMC_DYNAMICRP_tRP_Pos                                 0                                                         /*!< EMC DYNAMICRP: tRP Position         */
-#define EMC_DYNAMICRP_tRP_Msk                                 (0x0fUL << EMC_DYNAMICRP_tRP_Pos)                         /*!< EMC DYNAMICRP: tRP Mask             */
-
-// -------------------------------------  EMC_DYNAMICRAS  -----------------------------------------
-#define EMC_DYNAMICRAS_tRAS_Pos                               0                                                         /*!< EMC DYNAMICRAS: tRAS Position       */
-#define EMC_DYNAMICRAS_tRAS_Msk                               (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos)                       /*!< EMC DYNAMICRAS: tRAS Mask           */
-
-// -------------------------------------  EMC_DYNAMICSREX  ----------------------------------------
-#define EMC_DYNAMICSREX_tSREX_Pos                             0                                                         /*!< EMC DYNAMICSREX: tSREX Position     */
-#define EMC_DYNAMICSREX_tSREX_Msk                             (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos)                     /*!< EMC DYNAMICSREX: tSREX Mask         */
-
-// -------------------------------------  EMC_DYNAMICAPR  -----------------------------------------
-#define EMC_DYNAMICAPR_tAPR_Pos                               0                                                         /*!< EMC DYNAMICAPR: tAPR Position       */
-#define EMC_DYNAMICAPR_tAPR_Msk                               (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos)                       /*!< EMC DYNAMICAPR: tAPR Mask           */
-
-// -------------------------------------  EMC_DYNAMICDAL  -----------------------------------------
-#define EMC_DYNAMICDAL_tDAL_Pos                               0                                                         /*!< EMC DYNAMICDAL: tDAL Position       */
-#define EMC_DYNAMICDAL_tDAL_Msk                               (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos)                       /*!< EMC DYNAMICDAL: tDAL Mask           */
-
-// --------------------------------------  EMC_DYNAMICWR  -----------------------------------------
-#define EMC_DYNAMICWR_tWR_Pos                                 0                                                         /*!< EMC DYNAMICWR: tWR Position         */
-#define EMC_DYNAMICWR_tWR_Msk                                 (0x0fUL << EMC_DYNAMICWR_tWR_Pos)                         /*!< EMC DYNAMICWR: tWR Mask             */
-
-// --------------------------------------  EMC_DYNAMICRC  -----------------------------------------
-#define EMC_DYNAMICRC_tRC_Pos                                 0                                                         /*!< EMC DYNAMICRC: tRC Position         */
-#define EMC_DYNAMICRC_tRC_Msk                                 (0x1fUL << EMC_DYNAMICRC_tRC_Pos)                         /*!< EMC DYNAMICRC: tRC Mask             */
-
-// -------------------------------------  EMC_DYNAMICRFC  -----------------------------------------
-#define EMC_DYNAMICRFC_tRFC_Pos                               0                                                         /*!< EMC DYNAMICRFC: tRFC Position       */
-#define EMC_DYNAMICRFC_tRFC_Msk                               (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos)                       /*!< EMC DYNAMICRFC: tRFC Mask           */
-
-// -------------------------------------  EMC_DYNAMICXSR  -----------------------------------------
-#define EMC_DYNAMICXSR_tXSR_Pos                               0                                                         /*!< EMC DYNAMICXSR: tXSR Position       */
-#define EMC_DYNAMICXSR_tXSR_Msk                               (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos)                       /*!< EMC DYNAMICXSR: tXSR Mask           */
-
-// -------------------------------------  EMC_DYNAMICRRD  -----------------------------------------
-#define EMC_DYNAMICRRD_tRRD_Pos                               0                                                         /*!< EMC DYNAMICRRD: tRRD Position       */
-#define EMC_DYNAMICRRD_tRRD_Msk                               (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos)                       /*!< EMC DYNAMICRRD: tRRD Mask           */
-
-// -------------------------------------  EMC_DYNAMICMRD  -----------------------------------------
-#define EMC_DYNAMICMRD_tMRD_Pos                               0                                                         /*!< EMC DYNAMICMRD: tMRD Position       */
-#define EMC_DYNAMICMRD_tMRD_Msk                               (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos)                       /*!< EMC DYNAMICMRD: tMRD Mask           */
-
-// ---------------------------------  EMC_STATICEXTENDEDWAIT  -------------------------------------
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos               0                                                         /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk               (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos) /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */
-
-// -----------------------------------  EMC_DYNAMICCONFIG0  ---------------------------------------
-#define EMC_DYNAMICCONFIG0_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG0: MD Position     */
-#define EMC_DYNAMICCONFIG0_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos)                     /*!< EMC DYNAMICCONFIG0: MD Mask         */
-#define EMC_DYNAMICCONFIG0_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG0: AM0 Position    */
-#define EMC_DYNAMICCONFIG0_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos)                    /*!< EMC DYNAMICCONFIG0: AM0 Mask        */
-#define EMC_DYNAMICCONFIG0_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG0: AM1 Position    */
-#define EMC_DYNAMICCONFIG0_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos)                    /*!< EMC DYNAMICCONFIG0: AM1 Mask        */
-#define EMC_DYNAMICCONFIG0_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG0: B Position      */
-#define EMC_DYNAMICCONFIG0_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_B_Pos)                      /*!< EMC DYNAMICCONFIG0: B Mask          */
-#define EMC_DYNAMICCONFIG0_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG0: P Position      */
-#define EMC_DYNAMICCONFIG0_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_P_Pos)                      /*!< EMC DYNAMICCONFIG0: P Mask          */
-
-// -----------------------------------  EMC_DYNAMICRASCAS0  ---------------------------------------
-#define EMC_DYNAMICRASCAS0_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS0: RAS Position    */
-#define EMC_DYNAMICRASCAS0_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos)                    /*!< EMC DYNAMICRASCAS0: RAS Mask        */
-#define EMC_DYNAMICRASCAS0_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS0: CAS Position    */
-#define EMC_DYNAMICRASCAS0_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos)                    /*!< EMC DYNAMICRASCAS0: CAS Mask        */
-
-// -----------------------------------  EMC_DYNAMICCONFIG1  ---------------------------------------
-#define EMC_DYNAMICCONFIG1_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG1: MD Position     */
-#define EMC_DYNAMICCONFIG1_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos)                     /*!< EMC DYNAMICCONFIG1: MD Mask         */
-#define EMC_DYNAMICCONFIG1_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG1: AM0 Position    */
-#define EMC_DYNAMICCONFIG1_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos)                    /*!< EMC DYNAMICCONFIG1: AM0 Mask        */
-#define EMC_DYNAMICCONFIG1_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG1: AM1 Position    */
-#define EMC_DYNAMICCONFIG1_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos)                    /*!< EMC DYNAMICCONFIG1: AM1 Mask        */
-#define EMC_DYNAMICCONFIG1_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG1: B Position      */
-#define EMC_DYNAMICCONFIG1_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_B_Pos)                      /*!< EMC DYNAMICCONFIG1: B Mask          */
-#define EMC_DYNAMICCONFIG1_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG1: P Position      */
-#define EMC_DYNAMICCONFIG1_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_P_Pos)                      /*!< EMC DYNAMICCONFIG1: P Mask          */
-
-// -----------------------------------  EMC_DYNAMICRASCAS1  ---------------------------------------
-#define EMC_DYNAMICRASCAS1_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS1: RAS Position    */
-#define EMC_DYNAMICRASCAS1_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos)                    /*!< EMC DYNAMICRASCAS1: RAS Mask        */
-#define EMC_DYNAMICRASCAS1_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS1: CAS Position    */
-#define EMC_DYNAMICRASCAS1_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos)                    /*!< EMC DYNAMICRASCAS1: CAS Mask        */
-
-// -----------------------------------  EMC_DYNAMICCONFIG2  ---------------------------------------
-#define EMC_DYNAMICCONFIG2_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG2: MD Position     */
-#define EMC_DYNAMICCONFIG2_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos)                     /*!< EMC DYNAMICCONFIG2: MD Mask         */
-#define EMC_DYNAMICCONFIG2_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG2: AM0 Position    */
-#define EMC_DYNAMICCONFIG2_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos)                    /*!< EMC DYNAMICCONFIG2: AM0 Mask        */
-#define EMC_DYNAMICCONFIG2_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG2: AM1 Position    */
-#define EMC_DYNAMICCONFIG2_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos)                    /*!< EMC DYNAMICCONFIG2: AM1 Mask        */
-#define EMC_DYNAMICCONFIG2_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG2: B Position      */
-#define EMC_DYNAMICCONFIG2_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_B_Pos)                      /*!< EMC DYNAMICCONFIG2: B Mask          */
-#define EMC_DYNAMICCONFIG2_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG2: P Position      */
-#define EMC_DYNAMICCONFIG2_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_P_Pos)                      /*!< EMC DYNAMICCONFIG2: P Mask          */
-
-// -----------------------------------  EMC_DYNAMICRASCAS2  ---------------------------------------
-#define EMC_DYNAMICRASCAS2_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS2: RAS Position    */
-#define EMC_DYNAMICRASCAS2_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos)                    /*!< EMC DYNAMICRASCAS2: RAS Mask        */
-#define EMC_DYNAMICRASCAS2_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS2: CAS Position    */
-#define EMC_DYNAMICRASCAS2_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos)                    /*!< EMC DYNAMICRASCAS2: CAS Mask        */
-
-// -----------------------------------  EMC_DYNAMICCONFIG3  ---------------------------------------
-#define EMC_DYNAMICCONFIG3_MD_Pos                             3                                                         /*!< EMC DYNAMICCONFIG3: MD Position     */
-#define EMC_DYNAMICCONFIG3_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos)                     /*!< EMC DYNAMICCONFIG3: MD Mask         */
-#define EMC_DYNAMICCONFIG3_AM0_Pos                            7                                                         /*!< EMC DYNAMICCONFIG3: AM0 Position    */
-#define EMC_DYNAMICCONFIG3_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos)                    /*!< EMC DYNAMICCONFIG3: AM0 Mask        */
-#define EMC_DYNAMICCONFIG3_AM1_Pos                            14                                                        /*!< EMC DYNAMICCONFIG3: AM1 Position    */
-#define EMC_DYNAMICCONFIG3_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos)                    /*!< EMC DYNAMICCONFIG3: AM1 Mask        */
-#define EMC_DYNAMICCONFIG3_B_Pos                              19                                                        /*!< EMC DYNAMICCONFIG3: B Position      */
-#define EMC_DYNAMICCONFIG3_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_B_Pos)                      /*!< EMC DYNAMICCONFIG3: B Mask          */
-#define EMC_DYNAMICCONFIG3_P_Pos                              20                                                        /*!< EMC DYNAMICCONFIG3: P Position      */
-#define EMC_DYNAMICCONFIG3_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_P_Pos)                      /*!< EMC DYNAMICCONFIG3: P Mask          */
-
-// -----------------------------------  EMC_DYNAMICRASCAS3  ---------------------------------------
-#define EMC_DYNAMICRASCAS3_RAS_Pos                            0                                                         /*!< EMC DYNAMICRASCAS3: RAS Position    */
-#define EMC_DYNAMICRASCAS3_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos)                    /*!< EMC DYNAMICRASCAS3: RAS Mask        */
-#define EMC_DYNAMICRASCAS3_CAS_Pos                            8                                                         /*!< EMC DYNAMICRASCAS3: CAS Position    */
-#define EMC_DYNAMICRASCAS3_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos)                    /*!< EMC DYNAMICRASCAS3: CAS Mask        */
-
-// ------------------------------------  EMC_STATICCONFIG0  ---------------------------------------
-#define EMC_STATICCONFIG0_MW_Pos                              0                                                         /*!< EMC STATICCONFIG0: MW Position      */
-#define EMC_STATICCONFIG0_MW_Msk                              (0x03UL << EMC_STATICCONFIG0_MW_Pos)                      /*!< EMC STATICCONFIG0: MW Mask          */
-#define EMC_STATICCONFIG0_PM_Pos                              3                                                         /*!< EMC STATICCONFIG0: PM Position      */
-#define EMC_STATICCONFIG0_PM_Msk                              (0x01UL << EMC_STATICCONFIG0_PM_Pos)                      /*!< EMC STATICCONFIG0: PM Mask          */
-#define EMC_STATICCONFIG0_PC_Pos                              6                                                         /*!< EMC STATICCONFIG0: PC Position      */
-#define EMC_STATICCONFIG0_PC_Msk                              (0x01UL << EMC_STATICCONFIG0_PC_Pos)                      /*!< EMC STATICCONFIG0: PC Mask          */
-#define EMC_STATICCONFIG0_PB_Pos                              7                                                         /*!< EMC STATICCONFIG0: PB Position      */
-#define EMC_STATICCONFIG0_PB_Msk                              (0x01UL << EMC_STATICCONFIG0_PB_Pos)                      /*!< EMC STATICCONFIG0: PB Mask          */
-#define EMC_STATICCONFIG0_EW_Pos                              8                                                         /*!< EMC STATICCONFIG0: EW Position      */
-#define EMC_STATICCONFIG0_EW_Msk                              (0x01UL << EMC_STATICCONFIG0_EW_Pos)                      /*!< EMC STATICCONFIG0: EW Mask          */
-#define EMC_STATICCONFIG0_B_Pos                               19                                                        /*!< EMC STATICCONFIG0: B Position       */
-#define EMC_STATICCONFIG0_B_Msk                               (0x01UL << EMC_STATICCONFIG0_B_Pos)                       /*!< EMC STATICCONFIG0: B Mask           */
-#define EMC_STATICCONFIG0_P_Pos                               20                                                        /*!< EMC STATICCONFIG0: P Position       */
-#define EMC_STATICCONFIG0_P_Msk                               (0x01UL << EMC_STATICCONFIG0_P_Pos)                       /*!< EMC STATICCONFIG0: P Mask           */
-
-// -----------------------------------  EMC_STATICWAITWEN0  ---------------------------------------
-#define EMC_STATICWAITWEN0_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN0: WAITWEN Position */
-#define EMC_STATICWAITWEN0_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos)                /*!< EMC STATICWAITWEN0: WAITWEN Mask    */
-
-// -----------------------------------  EMC_STATICWAITOEN0  ---------------------------------------
-#define EMC_STATICWAITOEN0_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN0: WAITOEN Position */
-#define EMC_STATICWAITOEN0_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos)                /*!< EMC STATICWAITOEN0: WAITOEN Mask    */
-
-// ------------------------------------  EMC_STATICWAITRD0  ---------------------------------------
-#define EMC_STATICWAITRD0_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD0: WAITRD Position  */
-#define EMC_STATICWAITRD0_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos)                  /*!< EMC STATICWAITRD0: WAITRD Mask      */
-
-// -----------------------------------  EMC_STATICWAITPAG0  ---------------------------------------
-#define EMC_STATICWAITPAG0_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG0: WAITPAGE Position */
-#define EMC_STATICWAITPAG0_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG0: WAITPAGE Mask   */
-
-// ------------------------------------  EMC_STATICWAITWR0  ---------------------------------------
-#define EMC_STATICWAITWR0_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR0: WAITWR Position  */
-#define EMC_STATICWAITWR0_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos)                  /*!< EMC STATICWAITWR0: WAITWR Mask      */
-
-// -----------------------------------  EMC_STATICWAITTURN0  --------------------------------------
-#define EMC_STATICWAITTURN0_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN0: WAITTURN Position */
-#define EMC_STATICWAITTURN0_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos)              /*!< EMC STATICWAITTURN0: WAITTURN Mask  */
-
-// ------------------------------------  EMC_STATICCONFIG1  ---------------------------------------
-#define EMC_STATICCONFIG1_MW_Pos                              0                                                         /*!< EMC STATICCONFIG1: MW Position      */
-#define EMC_STATICCONFIG1_MW_Msk                              (0x03UL << EMC_STATICCONFIG1_MW_Pos)                      /*!< EMC STATICCONFIG1: MW Mask          */
-#define EMC_STATICCONFIG1_PM_Pos                              3                                                         /*!< EMC STATICCONFIG1: PM Position      */
-#define EMC_STATICCONFIG1_PM_Msk                              (0x01UL << EMC_STATICCONFIG1_PM_Pos)                      /*!< EMC STATICCONFIG1: PM Mask          */
-#define EMC_STATICCONFIG1_PC_Pos                              6                                                         /*!< EMC STATICCONFIG1: PC Position      */
-#define EMC_STATICCONFIG1_PC_Msk                              (0x01UL << EMC_STATICCONFIG1_PC_Pos)                      /*!< EMC STATICCONFIG1: PC Mask          */
-#define EMC_STATICCONFIG1_PB_Pos                              7                                                         /*!< EMC STATICCONFIG1: PB Position      */
-#define EMC_STATICCONFIG1_PB_Msk                              (0x01UL << EMC_STATICCONFIG1_PB_Pos)                      /*!< EMC STATICCONFIG1: PB Mask          */
-#define EMC_STATICCONFIG1_EW_Pos                              8                                                         /*!< EMC STATICCONFIG1: EW Position      */
-#define EMC_STATICCONFIG1_EW_Msk                              (0x01UL << EMC_STATICCONFIG1_EW_Pos)                      /*!< EMC STATICCONFIG1: EW Mask          */
-#define EMC_STATICCONFIG1_B_Pos                               19                                                        /*!< EMC STATICCONFIG1: B Position       */
-#define EMC_STATICCONFIG1_B_Msk                               (0x01UL << EMC_STATICCONFIG1_B_Pos)                       /*!< EMC STATICCONFIG1: B Mask           */
-#define EMC_STATICCONFIG1_P_Pos                               20                                                        /*!< EMC STATICCONFIG1: P Position       */
-#define EMC_STATICCONFIG1_P_Msk                               (0x01UL << EMC_STATICCONFIG1_P_Pos)                       /*!< EMC STATICCONFIG1: P Mask           */
-
-// -----------------------------------  EMC_STATICWAITWEN1  ---------------------------------------
-#define EMC_STATICWAITWEN1_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN1: WAITWEN Position */
-#define EMC_STATICWAITWEN1_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos)                /*!< EMC STATICWAITWEN1: WAITWEN Mask    */
-
-// -----------------------------------  EMC_STATICWAITOEN1  ---------------------------------------
-#define EMC_STATICWAITOEN1_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN1: WAITOEN Position */
-#define EMC_STATICWAITOEN1_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos)                /*!< EMC STATICWAITOEN1: WAITOEN Mask    */
-
-// ------------------------------------  EMC_STATICWAITRD1  ---------------------------------------
-#define EMC_STATICWAITRD1_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD1: WAITRD Position  */
-#define EMC_STATICWAITRD1_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos)                  /*!< EMC STATICWAITRD1: WAITRD Mask      */
-
-// -----------------------------------  EMC_STATICWAITPAG1  ---------------------------------------
-#define EMC_STATICWAITPAG1_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG1: WAITPAGE Position */
-#define EMC_STATICWAITPAG1_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG1: WAITPAGE Mask   */
-
-// ------------------------------------  EMC_STATICWAITWR1  ---------------------------------------
-#define EMC_STATICWAITWR1_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR1: WAITWR Position  */
-#define EMC_STATICWAITWR1_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos)                  /*!< EMC STATICWAITWR1: WAITWR Mask      */
-
-// -----------------------------------  EMC_STATICWAITTURN1  --------------------------------------
-#define EMC_STATICWAITTURN1_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN1: WAITTURN Position */
-#define EMC_STATICWAITTURN1_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos)              /*!< EMC STATICWAITTURN1: WAITTURN Mask  */
-
-// ------------------------------------  EMC_STATICCONFIG2  ---------------------------------------
-#define EMC_STATICCONFIG2_MW_Pos                              0                                                         /*!< EMC STATICCONFIG2: MW Position      */
-#define EMC_STATICCONFIG2_MW_Msk                              (0x03UL << EMC_STATICCONFIG2_MW_Pos)                      /*!< EMC STATICCONFIG2: MW Mask          */
-#define EMC_STATICCONFIG2_PM_Pos                              3                                                         /*!< EMC STATICCONFIG2: PM Position      */
-#define EMC_STATICCONFIG2_PM_Msk                              (0x01UL << EMC_STATICCONFIG2_PM_Pos)                      /*!< EMC STATICCONFIG2: PM Mask          */
-#define EMC_STATICCONFIG2_PC_Pos                              6                                                         /*!< EMC STATICCONFIG2: PC Position      */
-#define EMC_STATICCONFIG2_PC_Msk                              (0x01UL << EMC_STATICCONFIG2_PC_Pos)                      /*!< EMC STATICCONFIG2: PC Mask          */
-#define EMC_STATICCONFIG2_PB_Pos                              7                                                         /*!< EMC STATICCONFIG2: PB Position      */
-#define EMC_STATICCONFIG2_PB_Msk                              (0x01UL << EMC_STATICCONFIG2_PB_Pos)                      /*!< EMC STATICCONFIG2: PB Mask          */
-#define EMC_STATICCONFIG2_EW_Pos                              8                                                         /*!< EMC STATICCONFIG2: EW Position      */
-#define EMC_STATICCONFIG2_EW_Msk                              (0x01UL << EMC_STATICCONFIG2_EW_Pos)                      /*!< EMC STATICCONFIG2: EW Mask          */
-#define EMC_STATICCONFIG2_B_Pos                               19                                                        /*!< EMC STATICCONFIG2: B Position       */
-#define EMC_STATICCONFIG2_B_Msk                               (0x01UL << EMC_STATICCONFIG2_B_Pos)                       /*!< EMC STATICCONFIG2: B Mask           */
-#define EMC_STATICCONFIG2_P_Pos                               20                                                        /*!< EMC STATICCONFIG2: P Position       */
-#define EMC_STATICCONFIG2_P_Msk                               (0x01UL << EMC_STATICCONFIG2_P_Pos)                       /*!< EMC STATICCONFIG2: P Mask           */
-
-// -----------------------------------  EMC_STATICWAITWEN2  ---------------------------------------
-#define EMC_STATICWAITWEN2_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN2: WAITWEN Position */
-#define EMC_STATICWAITWEN2_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos)                /*!< EMC STATICWAITWEN2: WAITWEN Mask    */
-
-// -----------------------------------  EMC_STATICWAITOEN2  ---------------------------------------
-#define EMC_STATICWAITOEN2_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN2: WAITOEN Position */
-#define EMC_STATICWAITOEN2_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos)                /*!< EMC STATICWAITOEN2: WAITOEN Mask    */
-
-// ------------------------------------  EMC_STATICWAITRD2  ---------------------------------------
-#define EMC_STATICWAITRD2_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD2: WAITRD Position  */
-#define EMC_STATICWAITRD2_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos)                  /*!< EMC STATICWAITRD2: WAITRD Mask      */
-
-// -----------------------------------  EMC_STATICWAITPAG2  ---------------------------------------
-#define EMC_STATICWAITPAG2_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG2: WAITPAGE Position */
-#define EMC_STATICWAITPAG2_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG2: WAITPAGE Mask   */
-
-// ------------------------------------  EMC_STATICWAITWR2  ---------------------------------------
-#define EMC_STATICWAITWR2_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR2: WAITWR Position  */
-#define EMC_STATICWAITWR2_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos)                  /*!< EMC STATICWAITWR2: WAITWR Mask      */
-
-// -----------------------------------  EMC_STATICWAITTURN2  --------------------------------------
-#define EMC_STATICWAITTURN2_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN2: WAITTURN Position */
-#define EMC_STATICWAITTURN2_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos)              /*!< EMC STATICWAITTURN2: WAITTURN Mask  */
-
-// ------------------------------------  EMC_STATICCONFIG3  ---------------------------------------
-#define EMC_STATICCONFIG3_MW_Pos                              0                                                         /*!< EMC STATICCONFIG3: MW Position      */
-#define EMC_STATICCONFIG3_MW_Msk                              (0x03UL << EMC_STATICCONFIG3_MW_Pos)                      /*!< EMC STATICCONFIG3: MW Mask          */
-#define EMC_STATICCONFIG3_PM_Pos                              3                                                         /*!< EMC STATICCONFIG3: PM Position      */
-#define EMC_STATICCONFIG3_PM_Msk                              (0x01UL << EMC_STATICCONFIG3_PM_Pos)                      /*!< EMC STATICCONFIG3: PM Mask          */
-#define EMC_STATICCONFIG3_PC_Pos                              6                                                         /*!< EMC STATICCONFIG3: PC Position      */
-#define EMC_STATICCONFIG3_PC_Msk                              (0x01UL << EMC_STATICCONFIG3_PC_Pos)                      /*!< EMC STATICCONFIG3: PC Mask          */
-#define EMC_STATICCONFIG3_PB_Pos                              7                                                         /*!< EMC STATICCONFIG3: PB Position      */
-#define EMC_STATICCONFIG3_PB_Msk                              (0x01UL << EMC_STATICCONFIG3_PB_Pos)                      /*!< EMC STATICCONFIG3: PB Mask          */
-#define EMC_STATICCONFIG3_EW_Pos                              8                                                         /*!< EMC STATICCONFIG3: EW Position      */
-#define EMC_STATICCONFIG3_EW_Msk                              (0x01UL << EMC_STATICCONFIG3_EW_Pos)                      /*!< EMC STATICCONFIG3: EW Mask          */
-#define EMC_STATICCONFIG3_B_Pos                               19                                                        /*!< EMC STATICCONFIG3: B Position       */
-#define EMC_STATICCONFIG3_B_Msk                               (0x01UL << EMC_STATICCONFIG3_B_Pos)                       /*!< EMC STATICCONFIG3: B Mask           */
-#define EMC_STATICCONFIG3_P_Pos                               20                                                        /*!< EMC STATICCONFIG3: P Position       */
-#define EMC_STATICCONFIG3_P_Msk                               (0x01UL << EMC_STATICCONFIG3_P_Pos)                       /*!< EMC STATICCONFIG3: P Mask           */
-
-// -----------------------------------  EMC_STATICWAITWEN3  ---------------------------------------
-#define EMC_STATICWAITWEN3_WAITWEN_Pos                        0                                                         /*!< EMC STATICWAITWEN3: WAITWEN Position */
-#define EMC_STATICWAITWEN3_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos)                /*!< EMC STATICWAITWEN3: WAITWEN Mask    */
-
-// -----------------------------------  EMC_STATICWAITOEN3  ---------------------------------------
-#define EMC_STATICWAITOEN3_WAITOEN_Pos                        0                                                         /*!< EMC STATICWAITOEN3: WAITOEN Position */
-#define EMC_STATICWAITOEN3_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos)                /*!< EMC STATICWAITOEN3: WAITOEN Mask    */
-
-// ------------------------------------  EMC_STATICWAITRD3  ---------------------------------------
-#define EMC_STATICWAITRD3_WAITRD_Pos                          0                                                         /*!< EMC STATICWAITRD3: WAITRD Position  */
-#define EMC_STATICWAITRD3_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos)                  /*!< EMC STATICWAITRD3: WAITRD Mask      */
-
-// -----------------------------------  EMC_STATICWAITPAG3  ---------------------------------------
-#define EMC_STATICWAITPAG3_WAITPAGE_Pos                       0                                                         /*!< EMC STATICWAITPAG3: WAITPAGE Position */
-#define EMC_STATICWAITPAG3_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos)               /*!< EMC STATICWAITPAG3: WAITPAGE Mask   */
-
-// ------------------------------------  EMC_STATICWAITWR3  ---------------------------------------
-#define EMC_STATICWAITWR3_WAITWR_Pos                          0                                                         /*!< EMC STATICWAITWR3: WAITWR Position  */
-#define EMC_STATICWAITWR3_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos)                  /*!< EMC STATICWAITWR3: WAITWR Mask      */
-
-// -----------------------------------  EMC_STATICWAITTURN3  --------------------------------------
-#define EMC_STATICWAITTURN3_WAITTURN_Pos                      0                                                         /*!< EMC STATICWAITTURN3: WAITTURN Position */
-#define EMC_STATICWAITTURN3_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos)              /*!< EMC STATICWAITTURN3: WAITTURN Mask  */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 USB0 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -------------------------------------  USB0_CAPLENGTH  -----------------------------------------
-#define USB0_CAPLENGTH_CAPLENGTH_Pos                          0                                                         /*!< USB0 CAPLENGTH: CAPLENGTH Position  */
-#define USB0_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos)            /*!< USB0 CAPLENGTH: CAPLENGTH Mask      */
-#define USB0_CAPLENGTH_HCIVERSION_Pos                         8                                                         /*!< USB0 CAPLENGTH: HCIVERSION Position */
-#define USB0_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos)           /*!< USB0 CAPLENGTH: HCIVERSION Mask     */
-
-// -------------------------------------  USB0_HCSPARAMS  -----------------------------------------
-#define USB0_HCSPARAMS_N_PORTS_Pos                            0                                                         /*!< USB0 HCSPARAMS: N_PORTS Position    */
-#define USB0_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos)                    /*!< USB0 HCSPARAMS: N_PORTS Mask        */
-#define USB0_HCSPARAMS_PPC_Pos                                4                                                         /*!< USB0 HCSPARAMS: PPC Position        */
-#define USB0_HCSPARAMS_PPC_Msk                                (0x01UL << USB0_HCSPARAMS_PPC_Pos)                        /*!< USB0 HCSPARAMS: PPC Mask            */
-#define USB0_HCSPARAMS_N_PCC_Pos                              8                                                         /*!< USB0 HCSPARAMS: N_PCC Position      */
-#define USB0_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos)                      /*!< USB0 HCSPARAMS: N_PCC Mask          */
-#define USB0_HCSPARAMS_N_CC_Pos                               12                                                        /*!< USB0 HCSPARAMS: N_CC Position       */
-#define USB0_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB0_HCSPARAMS_N_CC_Pos)                       /*!< USB0 HCSPARAMS: N_CC Mask           */
-#define USB0_HCSPARAMS_PI_Pos                                 16                                                        /*!< USB0 HCSPARAMS: PI Position         */
-#define USB0_HCSPARAMS_PI_Msk                                 (0x01UL << USB0_HCSPARAMS_PI_Pos)                         /*!< USB0 HCSPARAMS: PI Mask             */
-#define USB0_HCSPARAMS_N_PTT_Pos                              20                                                        /*!< USB0 HCSPARAMS: N_PTT Position      */
-#define USB0_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos)                      /*!< USB0 HCSPARAMS: N_PTT Mask          */
-#define USB0_HCSPARAMS_N_TT_Pos                               24                                                        /*!< USB0 HCSPARAMS: N_TT Position       */
-#define USB0_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB0_HCSPARAMS_N_TT_Pos)                       /*!< USB0 HCSPARAMS: N_TT Mask           */
-
-// -------------------------------------  USB0_HCCPARAMS  -----------------------------------------
-#define USB0_HCCPARAMS_ADC_Pos                                0                                                         /*!< USB0 HCCPARAMS: ADC Position        */
-#define USB0_HCCPARAMS_ADC_Msk                                (0x01UL << USB0_HCCPARAMS_ADC_Pos)                        /*!< USB0 HCCPARAMS: ADC Mask            */
-#define USB0_HCCPARAMS_PFL_Pos                                1                                                         /*!< USB0 HCCPARAMS: PFL Position        */
-#define USB0_HCCPARAMS_PFL_Msk                                (0x01UL << USB0_HCCPARAMS_PFL_Pos)                        /*!< USB0 HCCPARAMS: PFL Mask            */
-#define USB0_HCCPARAMS_ASP_Pos                                2                                                         /*!< USB0 HCCPARAMS: ASP Position        */
-#define USB0_HCCPARAMS_ASP_Msk                                (0x01UL << USB0_HCCPARAMS_ASP_Pos)                        /*!< USB0 HCCPARAMS: ASP Mask            */
-#define USB0_HCCPARAMS_IST_Pos                                4                                                         /*!< USB0 HCCPARAMS: IST Position        */
-#define USB0_HCCPARAMS_IST_Msk                                (0x0fUL << USB0_HCCPARAMS_IST_Pos)                        /*!< USB0 HCCPARAMS: IST Mask            */
-#define USB0_HCCPARAMS_EECP_Pos                               8                                                         /*!< USB0 HCCPARAMS: EECP Position       */
-#define USB0_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos)                 /*!< USB0 HCCPARAMS: EECP Mask           */
-
-// -------------------------------------  USB0_DCIVERSION  ----------------------------------------
-#define USB0_DCIVERSION_DCIVERSION_Pos                        0                                                         /*!< USB0 DCIVERSION: DCIVERSION Position */
-#define USB0_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos)          /*!< USB0 DCIVERSION: DCIVERSION Mask    */
-
-// --------------------------------------  USB0_USBCMD_D  -----------------------------------------
-#define USB0_USBCMD_D_RS_Pos                                  0                                                         /*!< USB0 USBCMD_D: RS Position          */
-#define USB0_USBCMD_D_RS_Msk                                  (0x01UL << USB0_USBCMD_D_RS_Pos)                          /*!< USB0 USBCMD_D: RS Mask              */
-#define USB0_USBCMD_D_RST_Pos                                 1                                                         /*!< USB0 USBCMD_D: RST Position         */
-#define USB0_USBCMD_D_RST_Msk                                 (0x01UL << USB0_USBCMD_D_RST_Pos)                         /*!< USB0 USBCMD_D: RST Mask             */
-#define USB0_USBCMD_D_SUTW_Pos                                13                                                        /*!< USB0 USBCMD_D: SUTW Position        */
-#define USB0_USBCMD_D_SUTW_Msk                                (0x01UL << USB0_USBCMD_D_SUTW_Pos)                        /*!< USB0 USBCMD_D: SUTW Mask            */
-#define USB0_USBCMD_D_ATDTW_Pos                               14                                                        /*!< USB0 USBCMD_D: ATDTW Position       */
-#define USB0_USBCMD_D_ATDTW_Msk                               (0x01UL << USB0_USBCMD_D_ATDTW_Pos)                       /*!< USB0 USBCMD_D: ATDTW Mask           */
-#define USB0_USBCMD_D_ITC_Pos                                 16                                                        /*!< USB0 USBCMD_D: ITC Position         */
-#define USB0_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_D_ITC_Pos)                   /*!< USB0 USBCMD_D: ITC Mask             */
-
-// --------------------------------------  USB0_USBCMD_H  -----------------------------------------
-#define USB0_USBCMD_H_RS_Pos                                  0                                                         /*!< USB0 USBCMD_H: RS Position          */
-#define USB0_USBCMD_H_RS_Msk                                  (0x01UL << USB0_USBCMD_H_RS_Pos)                          /*!< USB0 USBCMD_H: RS Mask              */
-#define USB0_USBCMD_H_RST_Pos                                 1                                                         /*!< USB0 USBCMD_H: RST Position         */
-#define USB0_USBCMD_H_RST_Msk                                 (0x01UL << USB0_USBCMD_H_RST_Pos)                         /*!< USB0 USBCMD_H: RST Mask             */
-#define USB0_USBCMD_H_FS0_Pos                                 2                                                         /*!< USB0 USBCMD_H: FS0 Position         */
-#define USB0_USBCMD_H_FS0_Msk                                 (0x01UL << USB0_USBCMD_H_FS0_Pos)                         /*!< USB0 USBCMD_H: FS0 Mask             */
-#define USB0_USBCMD_H_FS1_Pos                                 3                                                         /*!< USB0 USBCMD_H: FS1 Position         */
-#define USB0_USBCMD_H_FS1_Msk                                 (0x01UL << USB0_USBCMD_H_FS1_Pos)                         /*!< USB0 USBCMD_H: FS1 Mask             */
-#define USB0_USBCMD_H_PSE_Pos                                 4                                                         /*!< USB0 USBCMD_H: PSE Position         */
-#define USB0_USBCMD_H_PSE_Msk                                 (0x01UL << USB0_USBCMD_H_PSE_Pos)                         /*!< USB0 USBCMD_H: PSE Mask             */
-#define USB0_USBCMD_H_ASE_Pos                                 5                                                         /*!< USB0 USBCMD_H: ASE Position         */
-#define USB0_USBCMD_H_ASE_Msk                                 (0x01UL << USB0_USBCMD_H_ASE_Pos)                         /*!< USB0 USBCMD_H: ASE Mask             */
-#define USB0_USBCMD_H_IAA_Pos                                 6                                                         /*!< USB0 USBCMD_H: IAA Position         */
-#define USB0_USBCMD_H_IAA_Msk                                 (0x01UL << USB0_USBCMD_H_IAA_Pos)                         /*!< USB0 USBCMD_H: IAA Mask             */
-#define USB0_USBCMD_H_ASP1_0_Pos                              8                                                         /*!< USB0 USBCMD_H: ASP1_0 Position      */
-#define USB0_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB0_USBCMD_H_ASP1_0_Pos)                      /*!< USB0 USBCMD_H: ASP1_0 Mask          */
-#define USB0_USBCMD_H_ASPE_Pos                                11                                                        /*!< USB0 USBCMD_H: ASPE Position        */
-#define USB0_USBCMD_H_ASPE_Msk                                (0x01UL << USB0_USBCMD_H_ASPE_Pos)                        /*!< USB0 USBCMD_H: ASPE Mask            */
-#define USB0_USBCMD_H_FS2_Pos                                 15                                                        /*!< USB0 USBCMD_H: FS2 Position         */
-#define USB0_USBCMD_H_FS2_Msk                                 (0x01UL << USB0_USBCMD_H_FS2_Pos)                         /*!< USB0 USBCMD_H: FS2 Mask             */
-#define USB0_USBCMD_H_ITC_Pos                                 16                                                        /*!< USB0 USBCMD_H: ITC Position         */
-#define USB0_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_H_ITC_Pos)                   /*!< USB0 USBCMD_H: ITC Mask             */
-
-// --------------------------------------  USB0_USBSTS_D  -----------------------------------------
-#define USB0_USBSTS_D_UI_Pos                                  0                                                         /*!< USB0 USBSTS_D: UI Position          */
-#define USB0_USBSTS_D_UI_Msk                                  (0x01UL << USB0_USBSTS_D_UI_Pos)                          /*!< USB0 USBSTS_D: UI Mask              */
-#define USB0_USBSTS_D_UEI_Pos                                 1                                                         /*!< USB0 USBSTS_D: UEI Position         */
-#define USB0_USBSTS_D_UEI_Msk                                 (0x01UL << USB0_USBSTS_D_UEI_Pos)                         /*!< USB0 USBSTS_D: UEI Mask             */
-#define USB0_USBSTS_D_PCI_Pos                                 2                                                         /*!< USB0 USBSTS_D: PCI Position         */
-#define USB0_USBSTS_D_PCI_Msk                                 (0x01UL << USB0_USBSTS_D_PCI_Pos)                         /*!< USB0 USBSTS_D: PCI Mask             */
-#define USB0_USBSTS_D_AAI_Pos                                 5                                                         /*!< USB0 USBSTS_D: AAI Position         */
-#define USB0_USBSTS_D_AAI_Msk                                 (0x01UL << USB0_USBSTS_D_AAI_Pos)                         /*!< USB0 USBSTS_D: AAI Mask             */
-#define USB0_USBSTS_D_URI_Pos                                 6                                                         /*!< USB0 USBSTS_D: URI Position         */
-#define USB0_USBSTS_D_URI_Msk                                 (0x01UL << USB0_USBSTS_D_URI_Pos)                         /*!< USB0 USBSTS_D: URI Mask             */
-#define USB0_USBSTS_D_SRI_Pos                                 7                                                         /*!< USB0 USBSTS_D: SRI Position         */
-#define USB0_USBSTS_D_SRI_Msk                                 (0x01UL << USB0_USBSTS_D_SRI_Pos)                         /*!< USB0 USBSTS_D: SRI Mask             */
-#define USB0_USBSTS_D_SLI_Pos                                 8                                                         /*!< USB0 USBSTS_D: SLI Position         */
-#define USB0_USBSTS_D_SLI_Msk                                 (0x01UL << USB0_USBSTS_D_SLI_Pos)                         /*!< USB0 USBSTS_D: SLI Mask             */
-#define USB0_USBSTS_D_NAKI_Pos                                16                                                        /*!< USB0 USBSTS_D: NAKI Position        */
-#define USB0_USBSTS_D_NAKI_Msk                                (0x01UL << USB0_USBSTS_D_NAKI_Pos)                        /*!< USB0 USBSTS_D: NAKI Mask            */
-
-// --------------------------------------  USB0_USBSTS_H  -----------------------------------------
-#define USB0_USBSTS_H_UI_Pos                                  0                                                         /*!< USB0 USBSTS_H: UI Position          */
-#define USB0_USBSTS_H_UI_Msk                                  (0x01UL << USB0_USBSTS_H_UI_Pos)                          /*!< USB0 USBSTS_H: UI Mask              */
-#define USB0_USBSTS_H_UEI_Pos                                 1                                                         /*!< USB0 USBSTS_H: UEI Position         */
-#define USB0_USBSTS_H_UEI_Msk                                 (0x01UL << USB0_USBSTS_H_UEI_Pos)                         /*!< USB0 USBSTS_H: UEI Mask             */
-#define USB0_USBSTS_H_PCI_Pos                                 2                                                         /*!< USB0 USBSTS_H: PCI Position         */
-#define USB0_USBSTS_H_PCI_Msk                                 (0x01UL << USB0_USBSTS_H_PCI_Pos)                         /*!< USB0 USBSTS_H: PCI Mask             */
-#define USB0_USBSTS_H_FRI_Pos                                 3                                                         /*!< USB0 USBSTS_H: FRI Position         */
-#define USB0_USBSTS_H_FRI_Msk                                 (0x01UL << USB0_USBSTS_H_FRI_Pos)                         /*!< USB0 USBSTS_H: FRI Mask             */
-#define USB0_USBSTS_H_AAI_Pos                                 5                                                         /*!< USB0 USBSTS_H: AAI Position         */
-#define USB0_USBSTS_H_AAI_Msk                                 (0x01UL << USB0_USBSTS_H_AAI_Pos)                         /*!< USB0 USBSTS_H: AAI Mask             */
-#define USB0_USBSTS_H_SRI_Pos                                 7                                                         /*!< USB0 USBSTS_H: SRI Position         */
-#define USB0_USBSTS_H_SRI_Msk                                 (0x01UL << USB0_USBSTS_H_SRI_Pos)                         /*!< USB0 USBSTS_H: SRI Mask             */
-#define USB0_USBSTS_H_HCH_Pos                                 12                                                        /*!< USB0 USBSTS_H: HCH Position         */
-#define USB0_USBSTS_H_HCH_Msk                                 (0x01UL << USB0_USBSTS_H_HCH_Pos)                         /*!< USB0 USBSTS_H: HCH Mask             */
-#define USB0_USBSTS_H_RCL_Pos                                 13                                                        /*!< USB0 USBSTS_H: RCL Position         */
-#define USB0_USBSTS_H_RCL_Msk                                 (0x01UL << USB0_USBSTS_H_RCL_Pos)                         /*!< USB0 USBSTS_H: RCL Mask             */
-#define USB0_USBSTS_H_PS_Pos                                  14                                                        /*!< USB0 USBSTS_H: PS Position          */
-#define USB0_USBSTS_H_PS_Msk                                  (0x01UL << USB0_USBSTS_H_PS_Pos)                          /*!< USB0 USBSTS_H: PS Mask              */
-#define USB0_USBSTS_H_AS_Pos                                  15                                                        /*!< USB0 USBSTS_H: AS Position          */
-#define USB0_USBSTS_H_AS_Msk                                  (0x01UL << USB0_USBSTS_H_AS_Pos)                          /*!< USB0 USBSTS_H: AS Mask              */
-#define USB0_USBSTS_H_UAI_Pos                                 18                                                        /*!< USB0 USBSTS_H: UAI Position         */
-#define USB0_USBSTS_H_UAI_Msk                                 (0x01UL << USB0_USBSTS_H_UAI_Pos)                         /*!< USB0 USBSTS_H: UAI Mask             */
-#define USB0_USBSTS_H_UPI_Pos                                 19                                                        /*!< USB0 USBSTS_H: UPI Position         */
-#define USB0_USBSTS_H_UPI_Msk                                 (0x01UL << USB0_USBSTS_H_UPI_Pos)                         /*!< USB0 USBSTS_H: UPI Mask             */
-
-// -------------------------------------  USB0_USBINTR_D  -----------------------------------------
-#define USB0_USBINTR_D_UE_Pos                                 0                                                         /*!< USB0 USBINTR_D: UE Position         */
-#define USB0_USBINTR_D_UE_Msk                                 (0x01UL << USB0_USBINTR_D_UE_Pos)                         /*!< USB0 USBINTR_D: UE Mask             */
-#define USB0_USBINTR_D_UEE_Pos                                1                                                         /*!< USB0 USBINTR_D: UEE Position        */
-#define USB0_USBINTR_D_UEE_Msk                                (0x01UL << USB0_USBINTR_D_UEE_Pos)                        /*!< USB0 USBINTR_D: UEE Mask            */
-#define USB0_USBINTR_D_PCE_Pos                                2                                                         /*!< USB0 USBINTR_D: PCE Position        */
-#define USB0_USBINTR_D_PCE_Msk                                (0x01UL << USB0_USBINTR_D_PCE_Pos)                        /*!< USB0 USBINTR_D: PCE Mask            */
-#define USB0_USBINTR_D_URE_Pos                                6                                                         /*!< USB0 USBINTR_D: URE Position        */
-#define USB0_USBINTR_D_URE_Msk                                (0x01UL << USB0_USBINTR_D_URE_Pos)                        /*!< USB0 USBINTR_D: URE Mask            */
-#define USB0_USBINTR_D_SRE_Pos                                7                                                         /*!< USB0 USBINTR_D: SRE Position        */
-#define USB0_USBINTR_D_SRE_Msk                                (0x01UL << USB0_USBINTR_D_SRE_Pos)                        /*!< USB0 USBINTR_D: SRE Mask            */
-#define USB0_USBINTR_D_SLE_Pos                                8                                                         /*!< USB0 USBINTR_D: SLE Position        */
-#define USB0_USBINTR_D_SLE_Msk                                (0x01UL << USB0_USBINTR_D_SLE_Pos)                        /*!< USB0 USBINTR_D: SLE Mask            */
-#define USB0_USBINTR_D_NAKE_Pos                               16                                                        /*!< USB0 USBINTR_D: NAKE Position       */
-#define USB0_USBINTR_D_NAKE_Msk                               (0x01UL << USB0_USBINTR_D_NAKE_Pos)                       /*!< USB0 USBINTR_D: NAKE Mask           */
-
-// -------------------------------------  USB0_USBINTR_H  -----------------------------------------
-#define USB0_USBINTR_H_UE_Pos                                 0                                                         /*!< USB0 USBINTR_H: UE Position         */
-#define USB0_USBINTR_H_UE_Msk                                 (0x01UL << USB0_USBINTR_H_UE_Pos)                         /*!< USB0 USBINTR_H: UE Mask             */
-#define USB0_USBINTR_H_UEE_Pos                                1                                                         /*!< USB0 USBINTR_H: UEE Position        */
-#define USB0_USBINTR_H_UEE_Msk                                (0x01UL << USB0_USBINTR_H_UEE_Pos)                        /*!< USB0 USBINTR_H: UEE Mask            */
-#define USB0_USBINTR_H_PCE_Pos                                2                                                         /*!< USB0 USBINTR_H: PCE Position        */
-#define USB0_USBINTR_H_PCE_Msk                                (0x01UL << USB0_USBINTR_H_PCE_Pos)                        /*!< USB0 USBINTR_H: PCE Mask            */
-#define USB0_USBINTR_H_FRE_Pos                                3                                                         /*!< USB0 USBINTR_H: FRE Position        */
-#define USB0_USBINTR_H_FRE_Msk                                (0x01UL << USB0_USBINTR_H_FRE_Pos)                        /*!< USB0 USBINTR_H: FRE Mask            */
-#define USB0_USBINTR_H_AAE_Pos                                5                                                         /*!< USB0 USBINTR_H: AAE Position        */
-#define USB0_USBINTR_H_AAE_Msk                                (0x01UL << USB0_USBINTR_H_AAE_Pos)                        /*!< USB0 USBINTR_H: AAE Mask            */
-#define USB0_USBINTR_H_SRE_Pos                                7                                                         /*!< USB0 USBINTR_H: SRE Position        */
-#define USB0_USBINTR_H_SRE_Msk                                (0x01UL << USB0_USBINTR_H_SRE_Pos)                        /*!< USB0 USBINTR_H: SRE Mask            */
-#define USB0_USBINTR_H_UAIE_Pos                               18                                                        /*!< USB0 USBINTR_H: UAIE Position       */
-#define USB0_USBINTR_H_UAIE_Msk                               (0x01UL << USB0_USBINTR_H_UAIE_Pos)                       /*!< USB0 USBINTR_H: UAIE Mask           */
-#define USB0_USBINTR_H_UPIA_Pos                               19                                                        /*!< USB0 USBINTR_H: UPIA Position       */
-#define USB0_USBINTR_H_UPIA_Msk                               (0x01UL << USB0_USBINTR_H_UPIA_Pos)                       /*!< USB0 USBINTR_H: UPIA Mask           */
-
-// -------------------------------------  USB0_FRINDEX_D  -----------------------------------------
-#define USB0_FRINDEX_D_FRINDEX2_0_Pos                         0                                                         /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */
-#define USB0_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos)                 /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask     */
-#define USB0_FRINDEX_D_FRINDEX13_3_Pos                        3                                                         /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */
-#define USB0_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos)          /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask    */
-
-// -------------------------------------  USB0_FRINDEX_H  -----------------------------------------
-#define USB0_FRINDEX_H_FRINDEX2_0_Pos                         0                                                         /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */
-#define USB0_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos)                 /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask     */
-#define USB0_FRINDEX_H_FRINDEX12_3_Pos                        3                                                         /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */
-#define USB0_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos)          /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask    */
-
-// -------------------------------------  USB0_DEVICEADDR  ----------------------------------------
-#define USB0_DEVICEADDR_USBADRA_Pos                           24                                                        /*!< USB0 DEVICEADDR: USBADRA Position   */
-#define USB0_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB0_DEVICEADDR_USBADRA_Pos)                   /*!< USB0 DEVICEADDR: USBADRA Mask       */
-#define USB0_DEVICEADDR_USBADR_Pos                            25                                                        /*!< USB0 DEVICEADDR: USBADR Position    */
-#define USB0_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB0_DEVICEADDR_USBADR_Pos)                    /*!< USB0 DEVICEADDR: USBADR Mask        */
-
-// ----------------------------------  USB0_PERIODICLISTBASE  -------------------------------------
-#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos                12                                                        /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */
-#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos)  /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */
-
-// ----------------------------------  USB0_ENDPOINTLISTADDR  -------------------------------------
-#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11                                                        /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */
-#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos)   /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */
-
-// -----------------------------------  USB0_ASYNCLISTADDR  ---------------------------------------
-#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos                    5                                                         /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */
-#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos)      /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */
-
-// ---------------------------------------  USB0_TTCTRL  ------------------------------------------
-#define USB0_TTCTRL_TTHA_Pos                                  24                                                        /*!< USB0 TTCTRL: TTHA Position          */
-#define USB0_TTCTRL_TTHA_Msk                                  (0x7fUL << USB0_TTCTRL_TTHA_Pos)                          /*!< USB0 TTCTRL: TTHA Mask              */
-
-// -------------------------------------  USB0_BURSTSIZE  -----------------------------------------
-#define USB0_BURSTSIZE_RXPBURST_Pos                           0                                                         /*!< USB0 BURSTSIZE: RXPBURST Position   */
-#define USB0_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos)             /*!< USB0 BURSTSIZE: RXPBURST Mask       */
-#define USB0_BURSTSIZE_TXPBURST_Pos                           8                                                         /*!< USB0 BURSTSIZE: TXPBURST Position   */
-#define USB0_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos)             /*!< USB0 BURSTSIZE: TXPBURST Mask       */
-
-// ------------------------------------  USB0_TXFILLTUNING  ---------------------------------------
-#define USB0_TXFILLTUNING_TXSCHOH_Pos                         0                                                         /*!< USB0 TXFILLTUNING: TXSCHOH Position */
-#define USB0_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos)           /*!< USB0 TXFILLTUNING: TXSCHOH Mask     */
-#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos                     8                                                         /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */
-#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos)             /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */
-#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos                     16                                                        /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */
-#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos)             /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */
-
-// -------------------------------------  USB0_BINTERVAL  -----------------------------------------
-#define USB0_BINTERVAL_BINT_Pos                               0                                                         /*!< USB0 BINTERVAL: BINT Position       */
-#define USB0_BINTERVAL_BINT_Msk                               (0x0fUL << USB0_BINTERVAL_BINT_Pos)                       /*!< USB0 BINTERVAL: BINT Mask           */
-
-// --------------------------------------  USB0_ENDPTNAK  -----------------------------------------
-#define USB0_ENDPTNAK_EPRN0_Pos                               0                                                         /*!< USB0 ENDPTNAK: EPRN0 Position       */
-#define USB0_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN0_Pos)                       /*!< USB0 ENDPTNAK: EPRN0 Mask           */
-#define USB0_ENDPTNAK_EPRN1_Pos                               1                                                         /*!< USB0 ENDPTNAK: EPRN1 Position       */
-#define USB0_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN1_Pos)                       /*!< USB0 ENDPTNAK: EPRN1 Mask           */
-#define USB0_ENDPTNAK_EPRN2_Pos                               2                                                         /*!< USB0 ENDPTNAK: EPRN2 Position       */
-#define USB0_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN2_Pos)                       /*!< USB0 ENDPTNAK: EPRN2 Mask           */
-#define USB0_ENDPTNAK_EPRN3_Pos                               3                                                         /*!< USB0 ENDPTNAK: EPRN3 Position       */
-#define USB0_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN3_Pos)                       /*!< USB0 ENDPTNAK: EPRN3 Mask           */
-#define USB0_ENDPTNAK_EPRN4_Pos                               4                                                         /*!< USB0 ENDPTNAK: EPRN4 Position       */
-#define USB0_ENDPTNAK_EPRN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN4_Pos)                       /*!< USB0 ENDPTNAK: EPRN4 Mask           */
-#define USB0_ENDPTNAK_EPRN5_Pos                               5                                                         /*!< USB0 ENDPTNAK: EPRN5 Position       */
-#define USB0_ENDPTNAK_EPRN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN5_Pos)                       /*!< USB0 ENDPTNAK: EPRN5 Mask           */
-#define USB0_ENDPTNAK_EPTN0_Pos                               16                                                        /*!< USB0 ENDPTNAK: EPTN0 Position       */
-#define USB0_ENDPTNAK_EPTN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN0_Pos)                       /*!< USB0 ENDPTNAK: EPTN0 Mask           */
-#define USB0_ENDPTNAK_EPTN1_Pos                               17                                                        /*!< USB0 ENDPTNAK: EPTN1 Position       */
-#define USB0_ENDPTNAK_EPTN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN1_Pos)                       /*!< USB0 ENDPTNAK: EPTN1 Mask           */
-#define USB0_ENDPTNAK_EPTN2_Pos                               18                                                        /*!< USB0 ENDPTNAK: EPTN2 Position       */
-#define USB0_ENDPTNAK_EPTN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN2_Pos)                       /*!< USB0 ENDPTNAK: EPTN2 Mask           */
-#define USB0_ENDPTNAK_EPTN3_Pos                               19                                                        /*!< USB0 ENDPTNAK: EPTN3 Position       */
-#define USB0_ENDPTNAK_EPTN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN3_Pos)                       /*!< USB0 ENDPTNAK: EPTN3 Mask           */
-#define USB0_ENDPTNAK_EPTN4_Pos                               20                                                        /*!< USB0 ENDPTNAK: EPTN4 Position       */
-#define USB0_ENDPTNAK_EPTN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN4_Pos)                       /*!< USB0 ENDPTNAK: EPTN4 Mask           */
-#define USB0_ENDPTNAK_EPTN5_Pos                               21                                                        /*!< USB0 ENDPTNAK: EPTN5 Position       */
-#define USB0_ENDPTNAK_EPTN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN5_Pos)                       /*!< USB0 ENDPTNAK: EPTN5 Mask           */
-
-// -------------------------------------  USB0_ENDPTNAKEN  ----------------------------------------
-#define USB0_ENDPTNAKEN_EPRNE0_Pos                            0                                                         /*!< USB0 ENDPTNAKEN: EPRNE0 Position    */
-#define USB0_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE0 Mask        */
-#define USB0_ENDPTNAKEN_EPRNE1_Pos                            1                                                         /*!< USB0 ENDPTNAKEN: EPRNE1 Position    */
-#define USB0_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE1 Mask        */
-#define USB0_ENDPTNAKEN_EPRNE2_Pos                            2                                                         /*!< USB0 ENDPTNAKEN: EPRNE2 Position    */
-#define USB0_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE2 Mask        */
-#define USB0_ENDPTNAKEN_EPRNE3_Pos                            3                                                         /*!< USB0 ENDPTNAKEN: EPRNE3 Position    */
-#define USB0_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE3 Mask        */
-#define USB0_ENDPTNAKEN_EPRNE4_Pos                            4                                                         /*!< USB0 ENDPTNAKEN: EPRNE4 Position    */
-#define USB0_ENDPTNAKEN_EPRNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE4 Mask        */
-#define USB0_ENDPTNAKEN_EPRNE5_Pos                            5                                                         /*!< USB0 ENDPTNAKEN: EPRNE5 Position    */
-#define USB0_ENDPTNAKEN_EPRNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos)                    /*!< USB0 ENDPTNAKEN: EPRNE5 Mask        */
-#define USB0_ENDPTNAKEN_EPTNE0_Pos                            16                                                        /*!< USB0 ENDPTNAKEN: EPTNE0 Position    */
-#define USB0_ENDPTNAKEN_EPTNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE0 Mask        */
-#define USB0_ENDPTNAKEN_EPTNE1_Pos                            17                                                        /*!< USB0 ENDPTNAKEN: EPTNE1 Position    */
-#define USB0_ENDPTNAKEN_EPTNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE1 Mask        */
-#define USB0_ENDPTNAKEN_EPTNE2_Pos                            18                                                        /*!< USB0 ENDPTNAKEN: EPTNE2 Position    */
-#define USB0_ENDPTNAKEN_EPTNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE2 Mask        */
-#define USB0_ENDPTNAKEN_EPTNE3_Pos                            19                                                        /*!< USB0 ENDPTNAKEN: EPTNE3 Position    */
-#define USB0_ENDPTNAKEN_EPTNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE3 Mask        */
-#define USB0_ENDPTNAKEN_EPTNE4_Pos                            20                                                        /*!< USB0 ENDPTNAKEN: EPTNE4 Position    */
-#define USB0_ENDPTNAKEN_EPTNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE4 Mask        */
-#define USB0_ENDPTNAKEN_EPTNE5_Pos                            21                                                        /*!< USB0 ENDPTNAKEN: EPTNE5 Position    */
-#define USB0_ENDPTNAKEN_EPTNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos)                    /*!< USB0 ENDPTNAKEN: EPTNE5 Mask        */
-
-// -------------------------------------  USB0_PORTSC1_D  -----------------------------------------
-#define USB0_PORTSC1_D_CCS_Pos                                0                                                         /*!< USB0 PORTSC1_D: CCS Position        */
-#define USB0_PORTSC1_D_CCS_Msk                                (0x01UL << USB0_PORTSC1_D_CCS_Pos)                        /*!< USB0 PORTSC1_D: CCS Mask            */
-#define USB0_PORTSC1_D_PE_Pos                                 2                                                         /*!< USB0 PORTSC1_D: PE Position         */
-#define USB0_PORTSC1_D_PE_Msk                                 (0x01UL << USB0_PORTSC1_D_PE_Pos)                         /*!< USB0 PORTSC1_D: PE Mask             */
-#define USB0_PORTSC1_D_PEC_Pos                                3                                                         /*!< USB0 PORTSC1_D: PEC Position        */
-#define USB0_PORTSC1_D_PEC_Msk                                (0x01UL << USB0_PORTSC1_D_PEC_Pos)                        /*!< USB0 PORTSC1_D: PEC Mask            */
-#define USB0_PORTSC1_D_FPR_Pos                                6                                                         /*!< USB0 PORTSC1_D: FPR Position        */
-#define USB0_PORTSC1_D_FPR_Msk                                (0x01UL << USB0_PORTSC1_D_FPR_Pos)                        /*!< USB0 PORTSC1_D: FPR Mask            */
-#define USB0_PORTSC1_D_SUSP_Pos                               7                                                         /*!< USB0 PORTSC1_D: SUSP Position       */
-#define USB0_PORTSC1_D_SUSP_Msk                               (0x01UL << USB0_PORTSC1_D_SUSP_Pos)                       /*!< USB0 PORTSC1_D: SUSP Mask           */
-#define USB0_PORTSC1_D_PR_Pos                                 8                                                         /*!< USB0 PORTSC1_D: PR Position         */
-#define USB0_PORTSC1_D_PR_Msk                                 (0x01UL << USB0_PORTSC1_D_PR_Pos)                         /*!< USB0 PORTSC1_D: PR Mask             */
-#define USB0_PORTSC1_D_HSP_Pos                                9                                                         /*!< USB0 PORTSC1_D: HSP Position        */
-#define USB0_PORTSC1_D_HSP_Msk                                (0x01UL << USB0_PORTSC1_D_HSP_Pos)                        /*!< USB0 PORTSC1_D: HSP Mask            */
-#define USB0_PORTSC1_D_PIC1_0_Pos                             14                                                        /*!< USB0 PORTSC1_D: PIC1_0 Position     */
-#define USB0_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos)                     /*!< USB0 PORTSC1_D: PIC1_0 Mask         */
-#define USB0_PORTSC1_D_PTC3_0_Pos                             16                                                        /*!< USB0 PORTSC1_D: PTC3_0 Position     */
-#define USB0_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos)                     /*!< USB0 PORTSC1_D: PTC3_0 Mask         */
-#define USB0_PORTSC1_D_PHCD_Pos                               23                                                        /*!< USB0 PORTSC1_D: PHCD Position       */
-#define USB0_PORTSC1_D_PHCD_Msk                               (0x01UL << USB0_PORTSC1_D_PHCD_Pos)                       /*!< USB0 PORTSC1_D: PHCD Mask           */
-#define USB0_PORTSC1_D_PFSC_Pos                               24                                                        /*!< USB0 PORTSC1_D: PFSC Position       */
-#define USB0_PORTSC1_D_PFSC_Msk                               (0x01UL << USB0_PORTSC1_D_PFSC_Pos)                       /*!< USB0 PORTSC1_D: PFSC Mask           */
-#define USB0_PORTSC1_D_PSPD_Pos                               26                                                        /*!< USB0 PORTSC1_D: PSPD Position       */
-#define USB0_PORTSC1_D_PSPD_Msk                               (0x03UL << USB0_PORTSC1_D_PSPD_Pos)                       /*!< USB0 PORTSC1_D: PSPD Mask           */
-
-// -------------------------------------  USB0_PORTSC1_H  -----------------------------------------
-#define USB0_PORTSC1_H_CCS_Pos                                0                                                         /*!< USB0 PORTSC1_H: CCS Position        */
-#define USB0_PORTSC1_H_CCS_Msk                                (0x01UL << USB0_PORTSC1_H_CCS_Pos)                        /*!< USB0 PORTSC1_H: CCS Mask            */
-#define USB0_PORTSC1_H_CSC_Pos                                1                                                         /*!< USB0 PORTSC1_H: CSC Position        */
-#define USB0_PORTSC1_H_CSC_Msk                                (0x01UL << USB0_PORTSC1_H_CSC_Pos)                        /*!< USB0 PORTSC1_H: CSC Mask            */
-#define USB0_PORTSC1_H_PE_Pos                                 2                                                         /*!< USB0 PORTSC1_H: PE Position         */
-#define USB0_PORTSC1_H_PE_Msk                                 (0x01UL << USB0_PORTSC1_H_PE_Pos)                         /*!< USB0 PORTSC1_H: PE Mask             */
-#define USB0_PORTSC1_H_PEC_Pos                                3                                                         /*!< USB0 PORTSC1_H: PEC Position        */
-#define USB0_PORTSC1_H_PEC_Msk                                (0x01UL << USB0_PORTSC1_H_PEC_Pos)                        /*!< USB0 PORTSC1_H: PEC Mask            */
-#define USB0_PORTSC1_H_OCA_Pos                                4                                                         /*!< USB0 PORTSC1_H: OCA Position        */
-#define USB0_PORTSC1_H_OCA_Msk                                (0x01UL << USB0_PORTSC1_H_OCA_Pos)                        /*!< USB0 PORTSC1_H: OCA Mask            */
-#define USB0_PORTSC1_H_OCC_Pos                                5                                                         /*!< USB0 PORTSC1_H: OCC Position        */
-#define USB0_PORTSC1_H_OCC_Msk                                (0x01UL << USB0_PORTSC1_H_OCC_Pos)                        /*!< USB0 PORTSC1_H: OCC Mask            */
-#define USB0_PORTSC1_H_FPR_Pos                                6                                                         /*!< USB0 PORTSC1_H: FPR Position        */
-#define USB0_PORTSC1_H_FPR_Msk                                (0x01UL << USB0_PORTSC1_H_FPR_Pos)                        /*!< USB0 PORTSC1_H: FPR Mask            */
-#define USB0_PORTSC1_H_SUSP_Pos                               7                                                         /*!< USB0 PORTSC1_H: SUSP Position       */
-#define USB0_PORTSC1_H_SUSP_Msk                               (0x01UL << USB0_PORTSC1_H_SUSP_Pos)                       /*!< USB0 PORTSC1_H: SUSP Mask           */
-#define USB0_PORTSC1_H_PR_Pos                                 8                                                         /*!< USB0 PORTSC1_H: PR Position         */
-#define USB0_PORTSC1_H_PR_Msk                                 (0x01UL << USB0_PORTSC1_H_PR_Pos)                         /*!< USB0 PORTSC1_H: PR Mask             */
-#define USB0_PORTSC1_H_HSP_Pos                                9                                                         /*!< USB0 PORTSC1_H: HSP Position        */
-#define USB0_PORTSC1_H_HSP_Msk                                (0x01UL << USB0_PORTSC1_H_HSP_Pos)                        /*!< USB0 PORTSC1_H: HSP Mask            */
-#define USB0_PORTSC1_H_LS_Pos                                 10                                                        /*!< USB0 PORTSC1_H: LS Position         */
-#define USB0_PORTSC1_H_LS_Msk                                 (0x03UL << USB0_PORTSC1_H_LS_Pos)                         /*!< USB0 PORTSC1_H: LS Mask             */
-#define USB0_PORTSC1_H_PP_Pos                                 12                                                        /*!< USB0 PORTSC1_H: PP Position         */
-#define USB0_PORTSC1_H_PP_Msk                                 (0x01UL << USB0_PORTSC1_H_PP_Pos)                         /*!< USB0 PORTSC1_H: PP Mask             */
-#define USB0_PORTSC1_H_PIC1_0_Pos                             14                                                        /*!< USB0 PORTSC1_H: PIC1_0 Position     */
-#define USB0_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos)                     /*!< USB0 PORTSC1_H: PIC1_0 Mask         */
-#define USB0_PORTSC1_H_PTC3_0_Pos                             16                                                        /*!< USB0 PORTSC1_H: PTC3_0 Position     */
-#define USB0_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos)                     /*!< USB0 PORTSC1_H: PTC3_0 Mask         */
-#define USB0_PORTSC1_H_WKCN_Pos                               20                                                        /*!< USB0 PORTSC1_H: WKCN Position       */
-#define USB0_PORTSC1_H_WKCN_Msk                               (0x01UL << USB0_PORTSC1_H_WKCN_Pos)                       /*!< USB0 PORTSC1_H: WKCN Mask           */
-#define USB0_PORTSC1_H_WKDC_Pos                               21                                                        /*!< USB0 PORTSC1_H: WKDC Position       */
-#define USB0_PORTSC1_H_WKDC_Msk                               (0x01UL << USB0_PORTSC1_H_WKDC_Pos)                       /*!< USB0 PORTSC1_H: WKDC Mask           */
-#define USB0_PORTSC1_H_WKOC_Pos                               22                                                        /*!< USB0 PORTSC1_H: WKOC Position       */
-#define USB0_PORTSC1_H_WKOC_Msk                               (0x01UL << USB0_PORTSC1_H_WKOC_Pos)                       /*!< USB0 PORTSC1_H: WKOC Mask           */
-#define USB0_PORTSC1_H_PHCD_Pos                               23                                                        /*!< USB0 PORTSC1_H: PHCD Position       */
-#define USB0_PORTSC1_H_PHCD_Msk                               (0x01UL << USB0_PORTSC1_H_PHCD_Pos)                       /*!< USB0 PORTSC1_H: PHCD Mask           */
-#define USB0_PORTSC1_H_PFSC_Pos                               24                                                        /*!< USB0 PORTSC1_H: PFSC Position       */
-#define USB0_PORTSC1_H_PFSC_Msk                               (0x01UL << USB0_PORTSC1_H_PFSC_Pos)                       /*!< USB0 PORTSC1_H: PFSC Mask           */
-#define USB0_PORTSC1_H_PSPD_Pos                               26                                                        /*!< USB0 PORTSC1_H: PSPD Position       */
-#define USB0_PORTSC1_H_PSPD_Msk                               (0x03UL << USB0_PORTSC1_H_PSPD_Pos)                       /*!< USB0 PORTSC1_H: PSPD Mask           */
-
-// ---------------------------------------  USB0_OTGSC  -------------------------------------------
-#define USB0_OTGSC_VD_Pos                                     0                                                         /*!< USB0 OTGSC: VD Position             */
-#define USB0_OTGSC_VD_Msk                                     (0x01UL << USB0_OTGSC_VD_Pos)                             /*!< USB0 OTGSC: VD Mask                 */
-#define USB0_OTGSC_VC_Pos                                     1                                                         /*!< USB0 OTGSC: VC Position             */
-#define USB0_OTGSC_VC_Msk                                     (0x01UL << USB0_OTGSC_VC_Pos)                             /*!< USB0 OTGSC: VC Mask                 */
-#define USB0_OTGSC_HAAR_Pos                                   2                                                         /*!< USB0 OTGSC: HAAR Position           */
-#define USB0_OTGSC_HAAR_Msk                                   (0x01UL << USB0_OTGSC_HAAR_Pos)                           /*!< USB0 OTGSC: HAAR Mask               */
-#define USB0_OTGSC_OT_Pos                                     3                                                         /*!< USB0 OTGSC: OT Position             */
-#define USB0_OTGSC_OT_Msk                                     (0x01UL << USB0_OTGSC_OT_Pos)                             /*!< USB0 OTGSC: OT Mask                 */
-#define USB0_OTGSC_DP_Pos                                     4                                                         /*!< USB0 OTGSC: DP Position             */
-#define USB0_OTGSC_DP_Msk                                     (0x01UL << USB0_OTGSC_DP_Pos)                             /*!< USB0 OTGSC: DP Mask                 */
-#define USB0_OTGSC_IDPU_Pos                                   5                                                         /*!< USB0 OTGSC: IDPU Position           */
-#define USB0_OTGSC_IDPU_Msk                                   (0x01UL << USB0_OTGSC_IDPU_Pos)                           /*!< USB0 OTGSC: IDPU Mask               */
-#define USB0_OTGSC_HADP_Pos                                   6                                                         /*!< USB0 OTGSC: HADP Position           */
-#define USB0_OTGSC_HADP_Msk                                   (0x01UL << USB0_OTGSC_HADP_Pos)                           /*!< USB0 OTGSC: HADP Mask               */
-#define USB0_OTGSC_HABA_Pos                                   7                                                         /*!< USB0 OTGSC: HABA Position           */
-#define USB0_OTGSC_HABA_Msk                                   (0x01UL << USB0_OTGSC_HABA_Pos)                           /*!< USB0 OTGSC: HABA Mask               */
-#define USB0_OTGSC_ID_Pos                                     8                                                         /*!< USB0 OTGSC: ID Position             */
-#define USB0_OTGSC_ID_Msk                                     (0x01UL << USB0_OTGSC_ID_Pos)                             /*!< USB0 OTGSC: ID Mask                 */
-#define USB0_OTGSC_AVV_Pos                                    9                                                         /*!< USB0 OTGSC: AVV Position            */
-#define USB0_OTGSC_AVV_Msk                                    (0x01UL << USB0_OTGSC_AVV_Pos)                            /*!< USB0 OTGSC: AVV Mask                */
-#define USB0_OTGSC_ASV_Pos                                    10                                                        /*!< USB0 OTGSC: ASV Position            */
-#define USB0_OTGSC_ASV_Msk                                    (0x01UL << USB0_OTGSC_ASV_Pos)                            /*!< USB0 OTGSC: ASV Mask                */
-#define USB0_OTGSC_BSV_Pos                                    11                                                        /*!< USB0 OTGSC: BSV Position            */
-#define USB0_OTGSC_BSV_Msk                                    (0x01UL << USB0_OTGSC_BSV_Pos)                            /*!< USB0 OTGSC: BSV Mask                */
-#define USB0_OTGSC_BSE_Pos                                    12                                                        /*!< USB0 OTGSC: BSE Position            */
-#define USB0_OTGSC_BSE_Msk                                    (0x01UL << USB0_OTGSC_BSE_Pos)                            /*!< USB0 OTGSC: BSE Mask                */
-#define USB0_OTGSC_MS1T_Pos                                   13                                                        /*!< USB0 OTGSC: MS1T Position           */
-#define USB0_OTGSC_MS1T_Msk                                   (0x01UL << USB0_OTGSC_MS1T_Pos)                           /*!< USB0 OTGSC: MS1T Mask               */
-#define USB0_OTGSC_DPS_Pos                                    14                                                        /*!< USB0 OTGSC: DPS Position            */
-#define USB0_OTGSC_DPS_Msk                                    (0x01UL << USB0_OTGSC_DPS_Pos)                            /*!< USB0 OTGSC: DPS Mask                */
-#define USB0_OTGSC_IDIS_Pos                                   16                                                        /*!< USB0 OTGSC: IDIS Position           */
-#define USB0_OTGSC_IDIS_Msk                                   (0x01UL << USB0_OTGSC_IDIS_Pos)                           /*!< USB0 OTGSC: IDIS Mask               */
-#define USB0_OTGSC_AVVIS_Pos                                  17                                                        /*!< USB0 OTGSC: AVVIS Position          */
-#define USB0_OTGSC_AVVIS_Msk                                  (0x01UL << USB0_OTGSC_AVVIS_Pos)                          /*!< USB0 OTGSC: AVVIS Mask              */
-#define USB0_OTGSC_ASVIS_Pos                                  18                                                        /*!< USB0 OTGSC: ASVIS Position          */
-#define USB0_OTGSC_ASVIS_Msk                                  (0x01UL << USB0_OTGSC_ASVIS_Pos)                          /*!< USB0 OTGSC: ASVIS Mask              */
-#define USB0_OTGSC_BSVIS_Pos                                  19                                                        /*!< USB0 OTGSC: BSVIS Position          */
-#define USB0_OTGSC_BSVIS_Msk                                  (0x01UL << USB0_OTGSC_BSVIS_Pos)                          /*!< USB0 OTGSC: BSVIS Mask              */
-#define USB0_OTGSC_BSEIS_Pos                                  20                                                        /*!< USB0 OTGSC: BSEIS Position          */
-#define USB0_OTGSC_BSEIS_Msk                                  (0x01UL << USB0_OTGSC_BSEIS_Pos)                          /*!< USB0 OTGSC: BSEIS Mask              */
-#define USB0_OTGSC_ms1S_Pos                                   21                                                        /*!< USB0 OTGSC: ms1S Position           */
-#define USB0_OTGSC_ms1S_Msk                                   (0x01UL << USB0_OTGSC_ms1S_Pos)                           /*!< USB0 OTGSC: ms1S Mask               */
-#define USB0_OTGSC_DPIS_Pos                                   22                                                        /*!< USB0 OTGSC: DPIS Position           */
-#define USB0_OTGSC_DPIS_Msk                                   (0x01UL << USB0_OTGSC_DPIS_Pos)                           /*!< USB0 OTGSC: DPIS Mask               */
-#define USB0_OTGSC_IDIE_Pos                                   24                                                        /*!< USB0 OTGSC: IDIE Position           */
-#define USB0_OTGSC_IDIE_Msk                                   (0x01UL << USB0_OTGSC_IDIE_Pos)                           /*!< USB0 OTGSC: IDIE Mask               */
-#define USB0_OTGSC_AVVIE_Pos                                  25                                                        /*!< USB0 OTGSC: AVVIE Position          */
-#define USB0_OTGSC_AVVIE_Msk                                  (0x01UL << USB0_OTGSC_AVVIE_Pos)                          /*!< USB0 OTGSC: AVVIE Mask              */
-#define USB0_OTGSC_ASVIE_Pos                                  26                                                        /*!< USB0 OTGSC: ASVIE Position          */
-#define USB0_OTGSC_ASVIE_Msk                                  (0x01UL << USB0_OTGSC_ASVIE_Pos)                          /*!< USB0 OTGSC: ASVIE Mask              */
-#define USB0_OTGSC_BSVIE_Pos                                  27                                                        /*!< USB0 OTGSC: BSVIE Position          */
-#define USB0_OTGSC_BSVIE_Msk                                  (0x01UL << USB0_OTGSC_BSVIE_Pos)                          /*!< USB0 OTGSC: BSVIE Mask              */
-#define USB0_OTGSC_BSEIE_Pos                                  28                                                        /*!< USB0 OTGSC: BSEIE Position          */
-#define USB0_OTGSC_BSEIE_Msk                                  (0x01UL << USB0_OTGSC_BSEIE_Pos)                          /*!< USB0 OTGSC: BSEIE Mask              */
-#define USB0_OTGSC_MS1E_Pos                                   29                                                        /*!< USB0 OTGSC: MS1E Position           */
-#define USB0_OTGSC_MS1E_Msk                                   (0x01UL << USB0_OTGSC_MS1E_Pos)                           /*!< USB0 OTGSC: MS1E Mask               */
-#define USB0_OTGSC_DPIE_Pos                                   30                                                        /*!< USB0 OTGSC: DPIE Position           */
-#define USB0_OTGSC_DPIE_Msk                                   (0x01UL << USB0_OTGSC_DPIE_Pos)                           /*!< USB0 OTGSC: DPIE Mask               */
-
-// -------------------------------------  USB0_USBMODE_D  -----------------------------------------
-#define USB0_USBMODE_D_CM1_0_Pos                              0                                                         /*!< USB0 USBMODE_D: CM1_0 Position      */
-#define USB0_USBMODE_D_CM1_0_Msk                              (0x03UL << USB0_USBMODE_D_CM1_0_Pos)                      /*!< USB0 USBMODE_D: CM1_0 Mask          */
-#define USB0_USBMODE_D_ES_Pos                                 2                                                         /*!< USB0 USBMODE_D: ES Position         */
-#define USB0_USBMODE_D_ES_Msk                                 (0x01UL << USB0_USBMODE_D_ES_Pos)                         /*!< USB0 USBMODE_D: ES Mask             */
-#define USB0_USBMODE_D_SLOM_Pos                               3                                                         /*!< USB0 USBMODE_D: SLOM Position       */
-#define USB0_USBMODE_D_SLOM_Msk                               (0x01UL << USB0_USBMODE_D_SLOM_Pos)                       /*!< USB0 USBMODE_D: SLOM Mask           */
-#define USB0_USBMODE_D_SDIS_Pos                               4                                                         /*!< USB0 USBMODE_D: SDIS Position       */
-#define USB0_USBMODE_D_SDIS_Msk                               (0x01UL << USB0_USBMODE_D_SDIS_Pos)                       /*!< USB0 USBMODE_D: SDIS Mask           */
-
-// -------------------------------------  USB0_USBMODE_H  -----------------------------------------
-#define USB0_USBMODE_H_CM_Pos                                 0                                                         /*!< USB0 USBMODE_H: CM Position         */
-#define USB0_USBMODE_H_CM_Msk                                 (0x03UL << USB0_USBMODE_H_CM_Pos)                         /*!< USB0 USBMODE_H: CM Mask             */
-#define USB0_USBMODE_H_ES_Pos                                 2                                                         /*!< USB0 USBMODE_H: ES Position         */
-#define USB0_USBMODE_H_ES_Msk                                 (0x01UL << USB0_USBMODE_H_ES_Pos)                         /*!< USB0 USBMODE_H: ES Mask             */
-#define USB0_USBMODE_H_SDIS_Pos                               4                                                         /*!< USB0 USBMODE_H: SDIS Position       */
-#define USB0_USBMODE_H_SDIS_Msk                               (0x01UL << USB0_USBMODE_H_SDIS_Pos)                       /*!< USB0 USBMODE_H: SDIS Mask           */
-#define USB0_USBMODE_H_VBPS_Pos                               5                                                         /*!< USB0 USBMODE_H: VBPS Position       */
-#define USB0_USBMODE_H_VBPS_Msk                               (0x01UL << USB0_USBMODE_H_VBPS_Pos)                       /*!< USB0 USBMODE_H: VBPS Mask           */
-
-// -----------------------------------  USB0_ENDPTSETUPSTAT  --------------------------------------
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos               4                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos               5                                                         /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos)       /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */
-
-// -------------------------------------  USB0_ENDPTPRIME  ----------------------------------------
-#define USB0_ENDPTPRIME_PERB0_Pos                             0                                                         /*!< USB0 ENDPTPRIME: PERB0 Position     */
-#define USB0_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB0_Pos)                     /*!< USB0 ENDPTPRIME: PERB0 Mask         */
-#define USB0_ENDPTPRIME_PERB1_Pos                             1                                                         /*!< USB0 ENDPTPRIME: PERB1 Position     */
-#define USB0_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB1_Pos)                     /*!< USB0 ENDPTPRIME: PERB1 Mask         */
-#define USB0_ENDPTPRIME_PERB2_Pos                             2                                                         /*!< USB0 ENDPTPRIME: PERB2 Position     */
-#define USB0_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB2_Pos)                     /*!< USB0 ENDPTPRIME: PERB2 Mask         */
-#define USB0_ENDPTPRIME_PERB3_Pos                             3                                                         /*!< USB0 ENDPTPRIME: PERB3 Position     */
-#define USB0_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB3_Pos)                     /*!< USB0 ENDPTPRIME: PERB3 Mask         */
-#define USB0_ENDPTPRIME_PERB4_Pos                             4                                                         /*!< USB0 ENDPTPRIME: PERB4 Position     */
-#define USB0_ENDPTPRIME_PERB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB4_Pos)                     /*!< USB0 ENDPTPRIME: PERB4 Mask         */
-#define USB0_ENDPTPRIME_PERB5_Pos                             5                                                         /*!< USB0 ENDPTPRIME: PERB5 Position     */
-#define USB0_ENDPTPRIME_PERB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB5_Pos)                     /*!< USB0 ENDPTPRIME: PERB5 Mask         */
-#define USB0_ENDPTPRIME_PETB0_Pos                             16                                                        /*!< USB0 ENDPTPRIME: PETB0 Position     */
-#define USB0_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB0_Pos)                     /*!< USB0 ENDPTPRIME: PETB0 Mask         */
-#define USB0_ENDPTPRIME_PETB1_Pos                             17                                                        /*!< USB0 ENDPTPRIME: PETB1 Position     */
-#define USB0_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB1_Pos)                     /*!< USB0 ENDPTPRIME: PETB1 Mask         */
-#define USB0_ENDPTPRIME_PETB2_Pos                             18                                                        /*!< USB0 ENDPTPRIME: PETB2 Position     */
-#define USB0_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB2_Pos)                     /*!< USB0 ENDPTPRIME: PETB2 Mask         */
-#define USB0_ENDPTPRIME_PETB3_Pos                             19                                                        /*!< USB0 ENDPTPRIME: PETB3 Position     */
-#define USB0_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB3_Pos)                     /*!< USB0 ENDPTPRIME: PETB3 Mask         */
-#define USB0_ENDPTPRIME_PETB4_Pos                             20                                                        /*!< USB0 ENDPTPRIME: PETB4 Position     */
-#define USB0_ENDPTPRIME_PETB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB4_Pos)                     /*!< USB0 ENDPTPRIME: PETB4 Mask         */
-#define USB0_ENDPTPRIME_PETB5_Pos                             21                                                        /*!< USB0 ENDPTPRIME: PETB5 Position     */
-#define USB0_ENDPTPRIME_PETB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB5_Pos)                     /*!< USB0 ENDPTPRIME: PETB5 Mask         */
-
-// -------------------------------------  USB0_ENDPTFLUSH  ----------------------------------------
-#define USB0_ENDPTFLUSH_FERB0_Pos                             0                                                         /*!< USB0 ENDPTFLUSH: FERB0 Position     */
-#define USB0_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos)                     /*!< USB0 ENDPTFLUSH: FERB0 Mask         */
-#define USB0_ENDPTFLUSH_FERB1_Pos                             1                                                         /*!< USB0 ENDPTFLUSH: FERB1 Position     */
-#define USB0_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos)                     /*!< USB0 ENDPTFLUSH: FERB1 Mask         */
-#define USB0_ENDPTFLUSH_FERB2_Pos                             2                                                         /*!< USB0 ENDPTFLUSH: FERB2 Position     */
-#define USB0_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos)                     /*!< USB0 ENDPTFLUSH: FERB2 Mask         */
-#define USB0_ENDPTFLUSH_FERB3_Pos                             3                                                         /*!< USB0 ENDPTFLUSH: FERB3 Position     */
-#define USB0_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos)                     /*!< USB0 ENDPTFLUSH: FERB3 Mask         */
-#define USB0_ENDPTFLUSH_FERB4_Pos                             4                                                         /*!< USB0 ENDPTFLUSH: FERB4 Position     */
-#define USB0_ENDPTFLUSH_FERB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos)                     /*!< USB0 ENDPTFLUSH: FERB4 Mask         */
-#define USB0_ENDPTFLUSH_FERB5_Pos                             5                                                         /*!< USB0 ENDPTFLUSH: FERB5 Position     */
-#define USB0_ENDPTFLUSH_FERB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos)                     /*!< USB0 ENDPTFLUSH: FERB5 Mask         */
-#define USB0_ENDPTFLUSH_FETB0_Pos                             16                                                        /*!< USB0 ENDPTFLUSH: FETB0 Position     */
-#define USB0_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos)                     /*!< USB0 ENDPTFLUSH: FETB0 Mask         */
-#define USB0_ENDPTFLUSH_FETB1_Pos                             17                                                        /*!< USB0 ENDPTFLUSH: FETB1 Position     */
-#define USB0_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos)                     /*!< USB0 ENDPTFLUSH: FETB1 Mask         */
-#define USB0_ENDPTFLUSH_FETB2_Pos                             18                                                        /*!< USB0 ENDPTFLUSH: FETB2 Position     */
-#define USB0_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos)                     /*!< USB0 ENDPTFLUSH: FETB2 Mask         */
-#define USB0_ENDPTFLUSH_FETB3_Pos                             19                                                        /*!< USB0 ENDPTFLUSH: FETB3 Position     */
-#define USB0_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos)                     /*!< USB0 ENDPTFLUSH: FETB3 Mask         */
-#define USB0_ENDPTFLUSH_FETB4_Pos                             20                                                        /*!< USB0 ENDPTFLUSH: FETB4 Position     */
-#define USB0_ENDPTFLUSH_FETB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos)                     /*!< USB0 ENDPTFLUSH: FETB4 Mask         */
-#define USB0_ENDPTFLUSH_FETB5_Pos                             21                                                        /*!< USB0 ENDPTFLUSH: FETB5 Position     */
-#define USB0_ENDPTFLUSH_FETB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos)                     /*!< USB0 ENDPTFLUSH: FETB5 Mask         */
-
-// -------------------------------------  USB0_ENDPTSTAT  -----------------------------------------
-#define USB0_ENDPTSTAT_ERBR0_Pos                              0                                                         /*!< USB0 ENDPTSTAT: ERBR0 Position      */
-#define USB0_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos)                      /*!< USB0 ENDPTSTAT: ERBR0 Mask          */
-#define USB0_ENDPTSTAT_ERBR1_Pos                              1                                                         /*!< USB0 ENDPTSTAT: ERBR1 Position      */
-#define USB0_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos)                      /*!< USB0 ENDPTSTAT: ERBR1 Mask          */
-#define USB0_ENDPTSTAT_ERBR2_Pos                              2                                                         /*!< USB0 ENDPTSTAT: ERBR2 Position      */
-#define USB0_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos)                      /*!< USB0 ENDPTSTAT: ERBR2 Mask          */
-#define USB0_ENDPTSTAT_ERBR3_Pos                              3                                                         /*!< USB0 ENDPTSTAT: ERBR3 Position      */
-#define USB0_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos)                      /*!< USB0 ENDPTSTAT: ERBR3 Mask          */
-#define USB0_ENDPTSTAT_ERBR4_Pos                              4                                                         /*!< USB0 ENDPTSTAT: ERBR4 Position      */
-#define USB0_ENDPTSTAT_ERBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos)                      /*!< USB0 ENDPTSTAT: ERBR4 Mask          */
-#define USB0_ENDPTSTAT_ERBR5_Pos                              5                                                         /*!< USB0 ENDPTSTAT: ERBR5 Position      */
-#define USB0_ENDPTSTAT_ERBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos)                      /*!< USB0 ENDPTSTAT: ERBR5 Mask          */
-#define USB0_ENDPTSTAT_ETBR0_Pos                              16                                                        /*!< USB0 ENDPTSTAT: ETBR0 Position      */
-#define USB0_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos)                      /*!< USB0 ENDPTSTAT: ETBR0 Mask          */
-#define USB0_ENDPTSTAT_ETBR1_Pos                              17                                                        /*!< USB0 ENDPTSTAT: ETBR1 Position      */
-#define USB0_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos)                      /*!< USB0 ENDPTSTAT: ETBR1 Mask          */
-#define USB0_ENDPTSTAT_ETBR2_Pos                              18                                                        /*!< USB0 ENDPTSTAT: ETBR2 Position      */
-#define USB0_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos)                      /*!< USB0 ENDPTSTAT: ETBR2 Mask          */
-#define USB0_ENDPTSTAT_ETBR3_Pos                              19                                                        /*!< USB0 ENDPTSTAT: ETBR3 Position      */
-#define USB0_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos)                      /*!< USB0 ENDPTSTAT: ETBR3 Mask          */
-#define USB0_ENDPTSTAT_ETBR4_Pos                              20                                                        /*!< USB0 ENDPTSTAT: ETBR4 Position      */
-#define USB0_ENDPTSTAT_ETBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos)                      /*!< USB0 ENDPTSTAT: ETBR4 Mask          */
-#define USB0_ENDPTSTAT_ETBR5_Pos                              21                                                        /*!< USB0 ENDPTSTAT: ETBR5 Position      */
-#define USB0_ENDPTSTAT_ETBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos)                      /*!< USB0 ENDPTSTAT: ETBR5 Mask          */
-
-// -----------------------------------  USB0_ENDPTCOMPLETE  ---------------------------------------
-#define USB0_ENDPTCOMPLETE_ERCE0_Pos                          0                                                         /*!< USB0 ENDPTCOMPLETE: ERCE0 Position  */
-#define USB0_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask      */
-#define USB0_ENDPTCOMPLETE_ERCE1_Pos                          1                                                         /*!< USB0 ENDPTCOMPLETE: ERCE1 Position  */
-#define USB0_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask      */
-#define USB0_ENDPTCOMPLETE_ERCE2_Pos                          2                                                         /*!< USB0 ENDPTCOMPLETE: ERCE2 Position  */
-#define USB0_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask      */
-#define USB0_ENDPTCOMPLETE_ERCE3_Pos                          3                                                         /*!< USB0 ENDPTCOMPLETE: ERCE3 Position  */
-#define USB0_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask      */
-#define USB0_ENDPTCOMPLETE_ERCE4_Pos                          4                                                         /*!< USB0 ENDPTCOMPLETE: ERCE4 Position  */
-#define USB0_ENDPTCOMPLETE_ERCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask      */
-#define USB0_ENDPTCOMPLETE_ERCE5_Pos                          5                                                         /*!< USB0 ENDPTCOMPLETE: ERCE5 Position  */
-#define USB0_ENDPTCOMPLETE_ERCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos)                  /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask      */
-#define USB0_ENDPTCOMPLETE_ETCE0_Pos                          16                                                        /*!< USB0 ENDPTCOMPLETE: ETCE0 Position  */
-#define USB0_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask      */
-#define USB0_ENDPTCOMPLETE_ETCE1_Pos                          17                                                        /*!< USB0 ENDPTCOMPLETE: ETCE1 Position  */
-#define USB0_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask      */
-#define USB0_ENDPTCOMPLETE_ETCE2_Pos                          18                                                        /*!< USB0 ENDPTCOMPLETE: ETCE2 Position  */
-#define USB0_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask      */
-#define USB0_ENDPTCOMPLETE_ETCE3_Pos                          19                                                        /*!< USB0 ENDPTCOMPLETE: ETCE3 Position  */
-#define USB0_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask      */
-#define USB0_ENDPTCOMPLETE_ETCE4_Pos                          20                                                        /*!< USB0 ENDPTCOMPLETE: ETCE4 Position  */
-#define USB0_ENDPTCOMPLETE_ETCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask      */
-#define USB0_ENDPTCOMPLETE_ETCE5_Pos                          21                                                        /*!< USB0 ENDPTCOMPLETE: ETCE5 Position  */
-#define USB0_ENDPTCOMPLETE_ETCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos)                  /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask      */
-
-// -------------------------------------  USB0_ENDPTCTRL0  ----------------------------------------
-#define USB0_ENDPTCTRL0_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL0: RXS Position       */
-#define USB0_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXS_Pos)                       /*!< USB0 ENDPTCTRL0: RXS Mask           */
-#define USB0_ENDPTCTRL0_RXT1_0_Pos                            2                                                         /*!< USB0 ENDPTCTRL0: RXT1_0 Position    */
-#define USB0_ENDPTCTRL0_RXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos)                    /*!< USB0 ENDPTCTRL0: RXT1_0 Mask        */
-#define USB0_ENDPTCTRL0_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL0: RXE Position       */
-#define USB0_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXE_Pos)                       /*!< USB0 ENDPTCTRL0: RXE Mask           */
-#define USB0_ENDPTCTRL0_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL0: TXS Position       */
-#define USB0_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXS_Pos)                       /*!< USB0 ENDPTCTRL0: TXS Mask           */
-#define USB0_ENDPTCTRL0_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL0: TXT1_0 Position    */
-#define USB0_ENDPTCTRL0_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL0: TXT1_0 Mask        */
-#define USB0_ENDPTCTRL0_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL0: TXE Position       */
-#define USB0_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXE_Pos)                       /*!< USB0 ENDPTCTRL0: TXE Mask           */
-
-// -------------------------------------  USB0_ENDPTCTRL1  ----------------------------------------
-#define USB0_ENDPTCTRL1_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL1: RXS Position       */
-#define USB0_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXS_Pos)                       /*!< USB0 ENDPTCTRL1: RXS Mask           */
-#define USB0_ENDPTCTRL1_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL1: RXT Position       */
-#define USB0_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL1_RXT_Pos)                       /*!< USB0 ENDPTCTRL1: RXT Mask           */
-#define USB0_ENDPTCTRL1_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL1: RXI Position       */
-#define USB0_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXI_Pos)                       /*!< USB0 ENDPTCTRL1: RXI Mask           */
-#define USB0_ENDPTCTRL1_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL1: RXR Position       */
-#define USB0_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXR_Pos)                       /*!< USB0 ENDPTCTRL1: RXR Mask           */
-#define USB0_ENDPTCTRL1_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL1: RXE Position       */
-#define USB0_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXE_Pos)                       /*!< USB0 ENDPTCTRL1: RXE Mask           */
-#define USB0_ENDPTCTRL1_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL1: TXS Position       */
-#define USB0_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXS_Pos)                       /*!< USB0 ENDPTCTRL1: TXS Mask           */
-#define USB0_ENDPTCTRL1_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL1: TXT1_0 Position    */
-#define USB0_ENDPTCTRL1_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL1: TXT1_0 Mask        */
-#define USB0_ENDPTCTRL1_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL1: TXI Position       */
-#define USB0_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXI_Pos)                       /*!< USB0 ENDPTCTRL1: TXI Mask           */
-#define USB0_ENDPTCTRL1_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL1: TXR Position       */
-#define USB0_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXR_Pos)                       /*!< USB0 ENDPTCTRL1: TXR Mask           */
-#define USB0_ENDPTCTRL1_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL1: TXE Position       */
-#define USB0_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXE_Pos)                       /*!< USB0 ENDPTCTRL1: TXE Mask           */
-
-// -------------------------------------  USB0_ENDPTCTRL2  ----------------------------------------
-#define USB0_ENDPTCTRL2_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL2: RXS Position       */
-#define USB0_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXS_Pos)                       /*!< USB0 ENDPTCTRL2: RXS Mask           */
-#define USB0_ENDPTCTRL2_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL2: RXT Position       */
-#define USB0_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL2_RXT_Pos)                       /*!< USB0 ENDPTCTRL2: RXT Mask           */
-#define USB0_ENDPTCTRL2_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL2: RXI Position       */
-#define USB0_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXI_Pos)                       /*!< USB0 ENDPTCTRL2: RXI Mask           */
-#define USB0_ENDPTCTRL2_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL2: RXR Position       */
-#define USB0_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXR_Pos)                       /*!< USB0 ENDPTCTRL2: RXR Mask           */
-#define USB0_ENDPTCTRL2_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL2: RXE Position       */
-#define USB0_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXE_Pos)                       /*!< USB0 ENDPTCTRL2: RXE Mask           */
-#define USB0_ENDPTCTRL2_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL2: TXS Position       */
-#define USB0_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXS_Pos)                       /*!< USB0 ENDPTCTRL2: TXS Mask           */
-#define USB0_ENDPTCTRL2_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL2: TXT1_0 Position    */
-#define USB0_ENDPTCTRL2_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL2: TXT1_0 Mask        */
-#define USB0_ENDPTCTRL2_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL2: TXI Position       */
-#define USB0_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXI_Pos)                       /*!< USB0 ENDPTCTRL2: TXI Mask           */
-#define USB0_ENDPTCTRL2_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL2: TXR Position       */
-#define USB0_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXR_Pos)                       /*!< USB0 ENDPTCTRL2: TXR Mask           */
-#define USB0_ENDPTCTRL2_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL2: TXE Position       */
-#define USB0_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXE_Pos)                       /*!< USB0 ENDPTCTRL2: TXE Mask           */
-
-// -------------------------------------  USB0_ENDPTCTRL3  ----------------------------------------
-#define USB0_ENDPTCTRL3_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL3: RXS Position       */
-#define USB0_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXS_Pos)                       /*!< USB0 ENDPTCTRL3: RXS Mask           */
-#define USB0_ENDPTCTRL3_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL3: RXT Position       */
-#define USB0_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL3_RXT_Pos)                       /*!< USB0 ENDPTCTRL3: RXT Mask           */
-#define USB0_ENDPTCTRL3_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL3: RXI Position       */
-#define USB0_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXI_Pos)                       /*!< USB0 ENDPTCTRL3: RXI Mask           */
-#define USB0_ENDPTCTRL3_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL3: RXR Position       */
-#define USB0_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXR_Pos)                       /*!< USB0 ENDPTCTRL3: RXR Mask           */
-#define USB0_ENDPTCTRL3_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL3: RXE Position       */
-#define USB0_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXE_Pos)                       /*!< USB0 ENDPTCTRL3: RXE Mask           */
-#define USB0_ENDPTCTRL3_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL3: TXS Position       */
-#define USB0_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXS_Pos)                       /*!< USB0 ENDPTCTRL3: TXS Mask           */
-#define USB0_ENDPTCTRL3_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL3: TXT1_0 Position    */
-#define USB0_ENDPTCTRL3_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL3: TXT1_0 Mask        */
-#define USB0_ENDPTCTRL3_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL3: TXI Position       */
-#define USB0_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXI_Pos)                       /*!< USB0 ENDPTCTRL3: TXI Mask           */
-#define USB0_ENDPTCTRL3_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL3: TXR Position       */
-#define USB0_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXR_Pos)                       /*!< USB0 ENDPTCTRL3: TXR Mask           */
-#define USB0_ENDPTCTRL3_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL3: TXE Position       */
-#define USB0_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXE_Pos)                       /*!< USB0 ENDPTCTRL3: TXE Mask           */
-
-// -------------------------------------  USB0_ENDPTCTRL4  ----------------------------------------
-#define USB0_ENDPTCTRL4_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL4: RXS Position       */
-#define USB0_ENDPTCTRL4_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXS_Pos)                       /*!< USB0 ENDPTCTRL4: RXS Mask           */
-#define USB0_ENDPTCTRL4_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL4: RXT Position       */
-#define USB0_ENDPTCTRL4_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL4_RXT_Pos)                       /*!< USB0 ENDPTCTRL4: RXT Mask           */
-#define USB0_ENDPTCTRL4_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL4: RXI Position       */
-#define USB0_ENDPTCTRL4_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXI_Pos)                       /*!< USB0 ENDPTCTRL4: RXI Mask           */
-#define USB0_ENDPTCTRL4_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL4: RXR Position       */
-#define USB0_ENDPTCTRL4_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXR_Pos)                       /*!< USB0 ENDPTCTRL4: RXR Mask           */
-#define USB0_ENDPTCTRL4_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL4: RXE Position       */
-#define USB0_ENDPTCTRL4_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXE_Pos)                       /*!< USB0 ENDPTCTRL4: RXE Mask           */
-#define USB0_ENDPTCTRL4_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL4: TXS Position       */
-#define USB0_ENDPTCTRL4_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXS_Pos)                       /*!< USB0 ENDPTCTRL4: TXS Mask           */
-#define USB0_ENDPTCTRL4_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL4: TXT1_0 Position    */
-#define USB0_ENDPTCTRL4_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL4: TXT1_0 Mask        */
-#define USB0_ENDPTCTRL4_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL4: TXI Position       */
-#define USB0_ENDPTCTRL4_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXI_Pos)                       /*!< USB0 ENDPTCTRL4: TXI Mask           */
-#define USB0_ENDPTCTRL4_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL4: TXR Position       */
-#define USB0_ENDPTCTRL4_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXR_Pos)                       /*!< USB0 ENDPTCTRL4: TXR Mask           */
-#define USB0_ENDPTCTRL4_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL4: TXE Position       */
-#define USB0_ENDPTCTRL4_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXE_Pos)                       /*!< USB0 ENDPTCTRL4: TXE Mask           */
-
-// -------------------------------------  USB0_ENDPTCTRL5  ----------------------------------------
-#define USB0_ENDPTCTRL5_RXS_Pos                               0                                                         /*!< USB0 ENDPTCTRL5: RXS Position       */
-#define USB0_ENDPTCTRL5_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXS_Pos)                       /*!< USB0 ENDPTCTRL5: RXS Mask           */
-#define USB0_ENDPTCTRL5_RXT_Pos                               2                                                         /*!< USB0 ENDPTCTRL5: RXT Position       */
-#define USB0_ENDPTCTRL5_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL5_RXT_Pos)                       /*!< USB0 ENDPTCTRL5: RXT Mask           */
-#define USB0_ENDPTCTRL5_RXI_Pos                               5                                                         /*!< USB0 ENDPTCTRL5: RXI Position       */
-#define USB0_ENDPTCTRL5_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXI_Pos)                       /*!< USB0 ENDPTCTRL5: RXI Mask           */
-#define USB0_ENDPTCTRL5_RXR_Pos                               6                                                         /*!< USB0 ENDPTCTRL5: RXR Position       */
-#define USB0_ENDPTCTRL5_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXR_Pos)                       /*!< USB0 ENDPTCTRL5: RXR Mask           */
-#define USB0_ENDPTCTRL5_RXE_Pos                               7                                                         /*!< USB0 ENDPTCTRL5: RXE Position       */
-#define USB0_ENDPTCTRL5_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXE_Pos)                       /*!< USB0 ENDPTCTRL5: RXE Mask           */
-#define USB0_ENDPTCTRL5_TXS_Pos                               16                                                        /*!< USB0 ENDPTCTRL5: TXS Position       */
-#define USB0_ENDPTCTRL5_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXS_Pos)                       /*!< USB0 ENDPTCTRL5: TXS Mask           */
-#define USB0_ENDPTCTRL5_TXT1_0_Pos                            18                                                        /*!< USB0 ENDPTCTRL5: TXT1_0 Position    */
-#define USB0_ENDPTCTRL5_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos)                    /*!< USB0 ENDPTCTRL5: TXT1_0 Mask        */
-#define USB0_ENDPTCTRL5_TXI_Pos                               21                                                        /*!< USB0 ENDPTCTRL5: TXI Position       */
-#define USB0_ENDPTCTRL5_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXI_Pos)                       /*!< USB0 ENDPTCTRL5: TXI Mask           */
-#define USB0_ENDPTCTRL5_TXR_Pos                               22                                                        /*!< USB0 ENDPTCTRL5: TXR Position       */
-#define USB0_ENDPTCTRL5_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXR_Pos)                       /*!< USB0 ENDPTCTRL5: TXR Mask           */
-#define USB0_ENDPTCTRL5_TXE_Pos                               23                                                        /*!< USB0 ENDPTCTRL5: TXE Position       */
-#define USB0_ENDPTCTRL5_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXE_Pos)                       /*!< USB0 ENDPTCTRL5: TXE Mask           */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 USB1 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -------------------------------------  USB1_CAPLENGTH  -----------------------------------------
-#define USB1_CAPLENGTH_CAPLENGTH_Pos                          0                                                         /*!< USB1 CAPLENGTH: CAPLENGTH Position  */
-#define USB1_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos)            /*!< USB1 CAPLENGTH: CAPLENGTH Mask      */
-#define USB1_CAPLENGTH_HCIVERSION_Pos                         8                                                         /*!< USB1 CAPLENGTH: HCIVERSION Position */
-#define USB1_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos)           /*!< USB1 CAPLENGTH: HCIVERSION Mask     */
-
-// -------------------------------------  USB1_HCSPARAMS  -----------------------------------------
-#define USB1_HCSPARAMS_N_PORTS_Pos                            0                                                         /*!< USB1 HCSPARAMS: N_PORTS Position    */
-#define USB1_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos)                    /*!< USB1 HCSPARAMS: N_PORTS Mask        */
-#define USB1_HCSPARAMS_PPC_Pos                                4                                                         /*!< USB1 HCSPARAMS: PPC Position        */
-#define USB1_HCSPARAMS_PPC_Msk                                (0x01UL << USB1_HCSPARAMS_PPC_Pos)                        /*!< USB1 HCSPARAMS: PPC Mask            */
-#define USB1_HCSPARAMS_N_PCC_Pos                              8                                                         /*!< USB1 HCSPARAMS: N_PCC Position      */
-#define USB1_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos)                      /*!< USB1 HCSPARAMS: N_PCC Mask          */
-#define USB1_HCSPARAMS_N_CC_Pos                               12                                                        /*!< USB1 HCSPARAMS: N_CC Position       */
-#define USB1_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB1_HCSPARAMS_N_CC_Pos)                       /*!< USB1 HCSPARAMS: N_CC Mask           */
-#define USB1_HCSPARAMS_PI_Pos                                 16                                                        /*!< USB1 HCSPARAMS: PI Position         */
-#define USB1_HCSPARAMS_PI_Msk                                 (0x01UL << USB1_HCSPARAMS_PI_Pos)                         /*!< USB1 HCSPARAMS: PI Mask             */
-#define USB1_HCSPARAMS_N_PTT_Pos                              20                                                        /*!< USB1 HCSPARAMS: N_PTT Position      */
-#define USB1_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos)                      /*!< USB1 HCSPARAMS: N_PTT Mask          */
-#define USB1_HCSPARAMS_N_TT_Pos                               24                                                        /*!< USB1 HCSPARAMS: N_TT Position       */
-#define USB1_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB1_HCSPARAMS_N_TT_Pos)                       /*!< USB1 HCSPARAMS: N_TT Mask           */
-
-// -------------------------------------  USB1_HCCPARAMS  -----------------------------------------
-#define USB1_HCCPARAMS_ADC_Pos                                0                                                         /*!< USB1 HCCPARAMS: ADC Position        */
-#define USB1_HCCPARAMS_ADC_Msk                                (0x01UL << USB1_HCCPARAMS_ADC_Pos)                        /*!< USB1 HCCPARAMS: ADC Mask            */
-#define USB1_HCCPARAMS_PFL_Pos                                1                                                         /*!< USB1 HCCPARAMS: PFL Position        */
-#define USB1_HCCPARAMS_PFL_Msk                                (0x01UL << USB1_HCCPARAMS_PFL_Pos)                        /*!< USB1 HCCPARAMS: PFL Mask            */
-#define USB1_HCCPARAMS_ASP_Pos                                2                                                         /*!< USB1 HCCPARAMS: ASP Position        */
-#define USB1_HCCPARAMS_ASP_Msk                                (0x01UL << USB1_HCCPARAMS_ASP_Pos)                        /*!< USB1 HCCPARAMS: ASP Mask            */
-#define USB1_HCCPARAMS_IST_Pos                                4                                                         /*!< USB1 HCCPARAMS: IST Position        */
-#define USB1_HCCPARAMS_IST_Msk                                (0x0fUL << USB1_HCCPARAMS_IST_Pos)                        /*!< USB1 HCCPARAMS: IST Mask            */
-#define USB1_HCCPARAMS_EECP_Pos                               8                                                         /*!< USB1 HCCPARAMS: EECP Position       */
-#define USB1_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos)                 /*!< USB1 HCCPARAMS: EECP Mask           */
-
-// -------------------------------------  USB1_DCIVERSION  ----------------------------------------
-#define USB1_DCIVERSION_DCIVERSION_Pos                        0                                                         /*!< USB1 DCIVERSION: DCIVERSION Position */
-#define USB1_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos)          /*!< USB1 DCIVERSION: DCIVERSION Mask    */
-
-// --------------------------------------  USB1_USBCMD_D  -----------------------------------------
-#define USB1_USBCMD_D_RS_Pos                                  0                                                         /*!< USB1 USBCMD_D: RS Position          */
-#define USB1_USBCMD_D_RS_Msk                                  (0x01UL << USB1_USBCMD_D_RS_Pos)                          /*!< USB1 USBCMD_D: RS Mask              */
-#define USB1_USBCMD_D_RST_Pos                                 1                                                         /*!< USB1 USBCMD_D: RST Position         */
-#define USB1_USBCMD_D_RST_Msk                                 (0x01UL << USB1_USBCMD_D_RST_Pos)                         /*!< USB1 USBCMD_D: RST Mask             */
-#define USB1_USBCMD_D_SUTW_Pos                                13                                                        /*!< USB1 USBCMD_D: SUTW Position        */
-#define USB1_USBCMD_D_SUTW_Msk                                (0x01UL << USB1_USBCMD_D_SUTW_Pos)                        /*!< USB1 USBCMD_D: SUTW Mask            */
-#define USB1_USBCMD_D_ATDTW_Pos                               14                                                        /*!< USB1 USBCMD_D: ATDTW Position       */
-#define USB1_USBCMD_D_ATDTW_Msk                               (0x01UL << USB1_USBCMD_D_ATDTW_Pos)                       /*!< USB1 USBCMD_D: ATDTW Mask           */
-#define USB1_USBCMD_D_FS2_Pos                                 15                                                        /*!< USB1 USBCMD_D: FS2 Position         */
-#define USB1_USBCMD_D_FS2_Msk                                 (0x01UL << USB1_USBCMD_D_FS2_Pos)                         /*!< USB1 USBCMD_D: FS2 Mask             */
-#define USB1_USBCMD_D_ITC_Pos                                 16                                                        /*!< USB1 USBCMD_D: ITC Position         */
-#define USB1_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_D_ITC_Pos)                   /*!< USB1 USBCMD_D: ITC Mask             */
-
-// --------------------------------------  USB1_USBCMD_H  -----------------------------------------
-#define USB1_USBCMD_H_RS_Pos                                  0                                                         /*!< USB1 USBCMD_H: RS Position          */
-#define USB1_USBCMD_H_RS_Msk                                  (0x01UL << USB1_USBCMD_H_RS_Pos)                          /*!< USB1 USBCMD_H: RS Mask              */
-#define USB1_USBCMD_H_RST_Pos                                 1                                                         /*!< USB1 USBCMD_H: RST Position         */
-#define USB1_USBCMD_H_RST_Msk                                 (0x01UL << USB1_USBCMD_H_RST_Pos)                         /*!< USB1 USBCMD_H: RST Mask             */
-#define USB1_USBCMD_H_FS0_Pos                                 2                                                         /*!< USB1 USBCMD_H: FS0 Position         */
-#define USB1_USBCMD_H_FS0_Msk                                 (0x01UL << USB1_USBCMD_H_FS0_Pos)                         /*!< USB1 USBCMD_H: FS0 Mask             */
-#define USB1_USBCMD_H_FS1_Pos                                 3                                                         /*!< USB1 USBCMD_H: FS1 Position         */
-#define USB1_USBCMD_H_FS1_Msk                                 (0x01UL << USB1_USBCMD_H_FS1_Pos)                         /*!< USB1 USBCMD_H: FS1 Mask             */
-#define USB1_USBCMD_H_PSE_Pos                                 4                                                         /*!< USB1 USBCMD_H: PSE Position         */
-#define USB1_USBCMD_H_PSE_Msk                                 (0x01UL << USB1_USBCMD_H_PSE_Pos)                         /*!< USB1 USBCMD_H: PSE Mask             */
-#define USB1_USBCMD_H_ASE_Pos                                 5                                                         /*!< USB1 USBCMD_H: ASE Position         */
-#define USB1_USBCMD_H_ASE_Msk                                 (0x01UL << USB1_USBCMD_H_ASE_Pos)                         /*!< USB1 USBCMD_H: ASE Mask             */
-#define USB1_USBCMD_H_IAA_Pos                                 6                                                         /*!< USB1 USBCMD_H: IAA Position         */
-#define USB1_USBCMD_H_IAA_Msk                                 (0x01UL << USB1_USBCMD_H_IAA_Pos)                         /*!< USB1 USBCMD_H: IAA Mask             */
-#define USB1_USBCMD_H_ASP1_0_Pos                              8                                                         /*!< USB1 USBCMD_H: ASP1_0 Position      */
-#define USB1_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB1_USBCMD_H_ASP1_0_Pos)                      /*!< USB1 USBCMD_H: ASP1_0 Mask          */
-#define USB1_USBCMD_H_ASPE_Pos                                11                                                        /*!< USB1 USBCMD_H: ASPE Position        */
-#define USB1_USBCMD_H_ASPE_Msk                                (0x01UL << USB1_USBCMD_H_ASPE_Pos)                        /*!< USB1 USBCMD_H: ASPE Mask            */
-#define USB1_USBCMD_H_FS2_Pos                                 15                                                        /*!< USB1 USBCMD_H: FS2 Position         */
-#define USB1_USBCMD_H_FS2_Msk                                 (0x01UL << USB1_USBCMD_H_FS2_Pos)                         /*!< USB1 USBCMD_H: FS2 Mask             */
-#define USB1_USBCMD_H_ITC_Pos                                 16                                                        /*!< USB1 USBCMD_H: ITC Position         */
-#define USB1_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_H_ITC_Pos)                   /*!< USB1 USBCMD_H: ITC Mask             */
-
-// --------------------------------------  USB1_USBSTS_D  -----------------------------------------
-#define USB1_USBSTS_D_UI_Pos                                  0                                                         /*!< USB1 USBSTS_D: UI Position          */
-#define USB1_USBSTS_D_UI_Msk                                  (0x01UL << USB1_USBSTS_D_UI_Pos)                          /*!< USB1 USBSTS_D: UI Mask              */
-#define USB1_USBSTS_D_UEI_Pos                                 1                                                         /*!< USB1 USBSTS_D: UEI Position         */
-#define USB1_USBSTS_D_UEI_Msk                                 (0x01UL << USB1_USBSTS_D_UEI_Pos)                         /*!< USB1 USBSTS_D: UEI Mask             */
-#define USB1_USBSTS_D_PCI_Pos                                 2                                                         /*!< USB1 USBSTS_D: PCI Position         */
-#define USB1_USBSTS_D_PCI_Msk                                 (0x01UL << USB1_USBSTS_D_PCI_Pos)                         /*!< USB1 USBSTS_D: PCI Mask             */
-#define USB1_USBSTS_D_URI_Pos                                 6                                                         /*!< USB1 USBSTS_D: URI Position         */
-#define USB1_USBSTS_D_URI_Msk                                 (0x01UL << USB1_USBSTS_D_URI_Pos)                         /*!< USB1 USBSTS_D: URI Mask             */
-#define USB1_USBSTS_D_SRI_Pos                                 7                                                         /*!< USB1 USBSTS_D: SRI Position         */
-#define USB1_USBSTS_D_SRI_Msk                                 (0x01UL << USB1_USBSTS_D_SRI_Pos)                         /*!< USB1 USBSTS_D: SRI Mask             */
-#define USB1_USBSTS_D_SLI_Pos                                 8                                                         /*!< USB1 USBSTS_D: SLI Position         */
-#define USB1_USBSTS_D_SLI_Msk                                 (0x01UL << USB1_USBSTS_D_SLI_Pos)                         /*!< USB1 USBSTS_D: SLI Mask             */
-#define USB1_USBSTS_D_NAKI_Pos                                16                                                        /*!< USB1 USBSTS_D: NAKI Position        */
-#define USB1_USBSTS_D_NAKI_Msk                                (0x01UL << USB1_USBSTS_D_NAKI_Pos)                        /*!< USB1 USBSTS_D: NAKI Mask            */
-
-// --------------------------------------  USB1_USBSTS_H  -----------------------------------------
-#define USB1_USBSTS_H_UI_Pos                                  0                                                         /*!< USB1 USBSTS_H: UI Position          */
-#define USB1_USBSTS_H_UI_Msk                                  (0x01UL << USB1_USBSTS_H_UI_Pos)                          /*!< USB1 USBSTS_H: UI Mask              */
-#define USB1_USBSTS_H_UEI_Pos                                 1                                                         /*!< USB1 USBSTS_H: UEI Position         */
-#define USB1_USBSTS_H_UEI_Msk                                 (0x01UL << USB1_USBSTS_H_UEI_Pos)                         /*!< USB1 USBSTS_H: UEI Mask             */
-#define USB1_USBSTS_H_PCI_Pos                                 2                                                         /*!< USB1 USBSTS_H: PCI Position         */
-#define USB1_USBSTS_H_PCI_Msk                                 (0x01UL << USB1_USBSTS_H_PCI_Pos)                         /*!< USB1 USBSTS_H: PCI Mask             */
-#define USB1_USBSTS_H_FRI_Pos                                 3                                                         /*!< USB1 USBSTS_H: FRI Position         */
-#define USB1_USBSTS_H_FRI_Msk                                 (0x01UL << USB1_USBSTS_H_FRI_Pos)                         /*!< USB1 USBSTS_H: FRI Mask             */
-#define USB1_USBSTS_H_AAI_Pos                                 5                                                         /*!< USB1 USBSTS_H: AAI Position         */
-#define USB1_USBSTS_H_AAI_Msk                                 (0x01UL << USB1_USBSTS_H_AAI_Pos)                         /*!< USB1 USBSTS_H: AAI Mask             */
-#define USB1_USBSTS_H_SRI_Pos                                 7                                                         /*!< USB1 USBSTS_H: SRI Position         */
-#define USB1_USBSTS_H_SRI_Msk                                 (0x01UL << USB1_USBSTS_H_SRI_Pos)                         /*!< USB1 USBSTS_H: SRI Mask             */
-#define USB1_USBSTS_H_SLI_Pos                                 8                                                         /*!< USB1 USBSTS_H: SLI Position         */
-#define USB1_USBSTS_H_SLI_Msk                                 (0x01UL << USB1_USBSTS_H_SLI_Pos)                         /*!< USB1 USBSTS_H: SLI Mask             */
-#define USB1_USBSTS_H_HCH_Pos                                 12                                                        /*!< USB1 USBSTS_H: HCH Position         */
-#define USB1_USBSTS_H_HCH_Msk                                 (0x01UL << USB1_USBSTS_H_HCH_Pos)                         /*!< USB1 USBSTS_H: HCH Mask             */
-#define USB1_USBSTS_H_RCL_Pos                                 13                                                        /*!< USB1 USBSTS_H: RCL Position         */
-#define USB1_USBSTS_H_RCL_Msk                                 (0x01UL << USB1_USBSTS_H_RCL_Pos)                         /*!< USB1 USBSTS_H: RCL Mask             */
-#define USB1_USBSTS_H_PS_Pos                                  14                                                        /*!< USB1 USBSTS_H: PS Position          */
-#define USB1_USBSTS_H_PS_Msk                                  (0x01UL << USB1_USBSTS_H_PS_Pos)                          /*!< USB1 USBSTS_H: PS Mask              */
-#define USB1_USBSTS_H_AS_Pos                                  15                                                        /*!< USB1 USBSTS_H: AS Position          */
-#define USB1_USBSTS_H_AS_Msk                                  (0x01UL << USB1_USBSTS_H_AS_Pos)                          /*!< USB1 USBSTS_H: AS Mask              */
-#define USB1_USBSTS_H_UAI_Pos                                 18                                                        /*!< USB1 USBSTS_H: UAI Position         */
-#define USB1_USBSTS_H_UAI_Msk                                 (0x01UL << USB1_USBSTS_H_UAI_Pos)                         /*!< USB1 USBSTS_H: UAI Mask             */
-#define USB1_USBSTS_H_UPI_Pos                                 19                                                        /*!< USB1 USBSTS_H: UPI Position         */
-#define USB1_USBSTS_H_UPI_Msk                                 (0x01UL << USB1_USBSTS_H_UPI_Pos)                         /*!< USB1 USBSTS_H: UPI Mask             */
-
-// -------------------------------------  USB1_USBINTR_D  -----------------------------------------
-#define USB1_USBINTR_D_UE_Pos                                 0                                                         /*!< USB1 USBINTR_D: UE Position         */
-#define USB1_USBINTR_D_UE_Msk                                 (0x01UL << USB1_USBINTR_D_UE_Pos)                         /*!< USB1 USBINTR_D: UE Mask             */
-#define USB1_USBINTR_D_UEE_Pos                                1                                                         /*!< USB1 USBINTR_D: UEE Position        */
-#define USB1_USBINTR_D_UEE_Msk                                (0x01UL << USB1_USBINTR_D_UEE_Pos)                        /*!< USB1 USBINTR_D: UEE Mask            */
-#define USB1_USBINTR_D_PCE_Pos                                2                                                         /*!< USB1 USBINTR_D: PCE Position        */
-#define USB1_USBINTR_D_PCE_Msk                                (0x01UL << USB1_USBINTR_D_PCE_Pos)                        /*!< USB1 USBINTR_D: PCE Mask            */
-#define USB1_USBINTR_D_URE_Pos                                6                                                         /*!< USB1 USBINTR_D: URE Position        */
-#define USB1_USBINTR_D_URE_Msk                                (0x01UL << USB1_USBINTR_D_URE_Pos)                        /*!< USB1 USBINTR_D: URE Mask            */
-#define USB1_USBINTR_D_SRE_Pos                                7                                                         /*!< USB1 USBINTR_D: SRE Position        */
-#define USB1_USBINTR_D_SRE_Msk                                (0x01UL << USB1_USBINTR_D_SRE_Pos)                        /*!< USB1 USBINTR_D: SRE Mask            */
-#define USB1_USBINTR_D_SLE_Pos                                8                                                         /*!< USB1 USBINTR_D: SLE Position        */
-#define USB1_USBINTR_D_SLE_Msk                                (0x01UL << USB1_USBINTR_D_SLE_Pos)                        /*!< USB1 USBINTR_D: SLE Mask            */
-#define USB1_USBINTR_D_NAKE_Pos                               16                                                        /*!< USB1 USBINTR_D: NAKE Position       */
-#define USB1_USBINTR_D_NAKE_Msk                               (0x01UL << USB1_USBINTR_D_NAKE_Pos)                       /*!< USB1 USBINTR_D: NAKE Mask           */
-#define USB1_USBINTR_D_UAIE_Pos                               18                                                        /*!< USB1 USBINTR_D: UAIE Position       */
-#define USB1_USBINTR_D_UAIE_Msk                               (0x01UL << USB1_USBINTR_D_UAIE_Pos)                       /*!< USB1 USBINTR_D: UAIE Mask           */
-#define USB1_USBINTR_D_UPIA_Pos                               19                                                        /*!< USB1 USBINTR_D: UPIA Position       */
-#define USB1_USBINTR_D_UPIA_Msk                               (0x01UL << USB1_USBINTR_D_UPIA_Pos)                       /*!< USB1 USBINTR_D: UPIA Mask           */
-
-// -------------------------------------  USB1_USBINTR_H  -----------------------------------------
-#define USB1_USBINTR_H_UE_Pos                                 0                                                         /*!< USB1 USBINTR_H: UE Position         */
-#define USB1_USBINTR_H_UE_Msk                                 (0x01UL << USB1_USBINTR_H_UE_Pos)                         /*!< USB1 USBINTR_H: UE Mask             */
-#define USB1_USBINTR_H_UEE_Pos                                1                                                         /*!< USB1 USBINTR_H: UEE Position        */
-#define USB1_USBINTR_H_UEE_Msk                                (0x01UL << USB1_USBINTR_H_UEE_Pos)                        /*!< USB1 USBINTR_H: UEE Mask            */
-#define USB1_USBINTR_H_PCE_Pos                                2                                                         /*!< USB1 USBINTR_H: PCE Position        */
-#define USB1_USBINTR_H_PCE_Msk                                (0x01UL << USB1_USBINTR_H_PCE_Pos)                        /*!< USB1 USBINTR_H: PCE Mask            */
-#define USB1_USBINTR_H_FRE_Pos                                3                                                         /*!< USB1 USBINTR_H: FRE Position        */
-#define USB1_USBINTR_H_FRE_Msk                                (0x01UL << USB1_USBINTR_H_FRE_Pos)                        /*!< USB1 USBINTR_H: FRE Mask            */
-#define USB1_USBINTR_H_AAE_Pos                                5                                                         /*!< USB1 USBINTR_H: AAE Position        */
-#define USB1_USBINTR_H_AAE_Msk                                (0x01UL << USB1_USBINTR_H_AAE_Pos)                        /*!< USB1 USBINTR_H: AAE Mask            */
-#define USB1_USBINTR_H_SRE_Pos                                7                                                         /*!< USB1 USBINTR_H: SRE Position        */
-#define USB1_USBINTR_H_SRE_Msk                                (0x01UL << USB1_USBINTR_H_SRE_Pos)                        /*!< USB1 USBINTR_H: SRE Mask            */
-#define USB1_USBINTR_H_UAIE_Pos                               18                                                        /*!< USB1 USBINTR_H: UAIE Position       */
-#define USB1_USBINTR_H_UAIE_Msk                               (0x01UL << USB1_USBINTR_H_UAIE_Pos)                       /*!< USB1 USBINTR_H: UAIE Mask           */
-#define USB1_USBINTR_H_UPIA_Pos                               19                                                        /*!< USB1 USBINTR_H: UPIA Position       */
-#define USB1_USBINTR_H_UPIA_Msk                               (0x01UL << USB1_USBINTR_H_UPIA_Pos)                       /*!< USB1 USBINTR_H: UPIA Mask           */
-
-// -------------------------------------  USB1_FRINDEX_D  -----------------------------------------
-#define USB1_FRINDEX_D_FRINDEX2_0_Pos                         0                                                         /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */
-#define USB1_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos)                 /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask     */
-#define USB1_FRINDEX_D_FRINDEX13_3_Pos                        3                                                         /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */
-#define USB1_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos)          /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask    */
-
-// -------------------------------------  USB1_FRINDEX_H  -----------------------------------------
-#define USB1_FRINDEX_H_FRINDEX2_0_Pos                         0                                                         /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */
-#define USB1_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos)                 /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask     */
-#define USB1_FRINDEX_H_FRINDEX12_3_Pos                        3                                                         /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */
-#define USB1_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos)          /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask    */
-
-// -------------------------------------  USB1_DEVICEADDR  ----------------------------------------
-#define USB1_DEVICEADDR_USBADRA_Pos                           24                                                        /*!< USB1 DEVICEADDR: USBADRA Position   */
-#define USB1_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB1_DEVICEADDR_USBADRA_Pos)                   /*!< USB1 DEVICEADDR: USBADRA Mask       */
-#define USB1_DEVICEADDR_USBADR_Pos                            25                                                        /*!< USB1 DEVICEADDR: USBADR Position    */
-#define USB1_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB1_DEVICEADDR_USBADR_Pos)                    /*!< USB1 DEVICEADDR: USBADR Mask        */
-
-// ----------------------------------  USB1_PERIODICLISTBASE  -------------------------------------
-#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos                12                                                        /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */
-#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos)  /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */
-
-// ----------------------------------  USB1_ENDPOINTLISTADDR  -------------------------------------
-#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11                                                        /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */
-#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos)   /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */
-
-// -----------------------------------  USB1_ASYNCLISTADDR  ---------------------------------------
-#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos                    5                                                         /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */
-#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos)      /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */
-
-// ---------------------------------------  USB1_TTCTRL  ------------------------------------------
-#define USB1_TTCTRL_TTHA_Pos                                  24                                                        /*!< USB1 TTCTRL: TTHA Position          */
-#define USB1_TTCTRL_TTHA_Msk                                  (0x7fUL << USB1_TTCTRL_TTHA_Pos)                          /*!< USB1 TTCTRL: TTHA Mask              */
-
-// -------------------------------------  USB1_BURSTSIZE  -----------------------------------------
-#define USB1_BURSTSIZE_RXPBURST_Pos                           0                                                         /*!< USB1 BURSTSIZE: RXPBURST Position   */
-#define USB1_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos)             /*!< USB1 BURSTSIZE: RXPBURST Mask       */
-#define USB1_BURSTSIZE_TXPBURST_Pos                           8                                                         /*!< USB1 BURSTSIZE: TXPBURST Position   */
-#define USB1_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos)             /*!< USB1 BURSTSIZE: TXPBURST Mask       */
-
-// ------------------------------------  USB1_TXFILLTUNING  ---------------------------------------
-#define USB1_TXFILLTUNING_TXSCHOH_Pos                         0                                                         /*!< USB1 TXFILLTUNING: TXSCHOH Position */
-#define USB1_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos)           /*!< USB1 TXFILLTUNING: TXSCHOH Mask     */
-#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos                     8                                                         /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */
-#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos)             /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */
-#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos                     16                                                        /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */
-#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos)             /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */
-
-// ------------------------------------  USB1_ULPIVIEWPORT  ---------------------------------------
-#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos                       0                                                         /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */
-#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos)         /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask   */
-#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos                       8                                                         /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */
-#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos)         /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask   */
-#define USB1_ULPIVIEWPORT_ULPIADDR_Pos                        16                                                        /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */
-#define USB1_ULPIVIEWPORT_ULPIADDR_Msk                        (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos)          /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask    */
-#define USB1_ULPIVIEWPORT_ULPIPORT_Pos                        24                                                        /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */
-#define USB1_ULPIVIEWPORT_ULPIPORT_Msk                        (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos)                /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask    */
-#define USB1_ULPIVIEWPORT_ULPISS_Pos                          27                                                        /*!< USB1 ULPIVIEWPORT: ULPISS Position  */
-#define USB1_ULPIVIEWPORT_ULPISS_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPISS Mask      */
-#define USB1_ULPIVIEWPORT_ULPIRW_Pos                          29                                                        /*!< USB1 ULPIVIEWPORT: ULPIRW Position  */
-#define USB1_ULPIVIEWPORT_ULPIRW_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPIRW Mask      */
-#define USB1_ULPIVIEWPORT_ULPIRUN_Pos                         30                                                        /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */
-#define USB1_ULPIVIEWPORT_ULPIRUN_Msk                         (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos)                 /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask     */
-#define USB1_ULPIVIEWPORT_ULPIWU_Pos                          31                                                        /*!< USB1 ULPIVIEWPORT: ULPIWU Position  */
-#define USB1_ULPIVIEWPORT_ULPIWU_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos)                  /*!< USB1 ULPIVIEWPORT: ULPIWU Mask      */
-
-// -------------------------------------  USB1_BINTERVAL  -----------------------------------------
-#define USB1_BINTERVAL_BINT_Pos                               0                                                         /*!< USB1 BINTERVAL: BINT Position       */
-#define USB1_BINTERVAL_BINT_Msk                               (0x0fUL << USB1_BINTERVAL_BINT_Pos)                       /*!< USB1 BINTERVAL: BINT Mask           */
-
-// --------------------------------------  USB1_ENDPTNAK  -----------------------------------------
-#define USB1_ENDPTNAK_EPRN0_Pos                               0                                                         /*!< USB1 ENDPTNAK: EPRN0 Position       */
-#define USB1_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN0_Pos)                       /*!< USB1 ENDPTNAK: EPRN0 Mask           */
-#define USB1_ENDPTNAK_EPRN1_Pos                               1                                                         /*!< USB1 ENDPTNAK: EPRN1 Position       */
-#define USB1_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN1_Pos)                       /*!< USB1 ENDPTNAK: EPRN1 Mask           */
-#define USB1_ENDPTNAK_EPRN2_Pos                               2                                                         /*!< USB1 ENDPTNAK: EPRN2 Position       */
-#define USB1_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN2_Pos)                       /*!< USB1 ENDPTNAK: EPRN2 Mask           */
-#define USB1_ENDPTNAK_EPRN3_Pos                               3                                                         /*!< USB1 ENDPTNAK: EPRN3 Position       */
-#define USB1_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN3_Pos)                       /*!< USB1 ENDPTNAK: EPRN3 Mask           */
-#define USB1_ENDPTNAK_EPTN16_Pos                              16                                                        /*!< USB1 ENDPTNAK: EPTN16 Position      */
-#define USB1_ENDPTNAK_EPTN16_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN16_Pos)                      /*!< USB1 ENDPTNAK: EPTN16 Mask          */
-#define USB1_ENDPTNAK_EPTN17_Pos                              17                                                        /*!< USB1 ENDPTNAK: EPTN17 Position      */
-#define USB1_ENDPTNAK_EPTN17_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN17_Pos)                      /*!< USB1 ENDPTNAK: EPTN17 Mask          */
-#define USB1_ENDPTNAK_EPTN18_Pos                              18                                                        /*!< USB1 ENDPTNAK: EPTN18 Position      */
-#define USB1_ENDPTNAK_EPTN18_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN18_Pos)                      /*!< USB1 ENDPTNAK: EPTN18 Mask          */
-#define USB1_ENDPTNAK_EPTN19_Pos                              19                                                        /*!< USB1 ENDPTNAK: EPTN19 Position      */
-#define USB1_ENDPTNAK_EPTN19_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN19_Pos)                      /*!< USB1 ENDPTNAK: EPTN19 Mask          */
-
-// -------------------------------------  USB1_ENDPTNAKEN  ----------------------------------------
-#define USB1_ENDPTNAKEN_EPRNE0_Pos                            0                                                         /*!< USB1 ENDPTNAKEN: EPRNE0 Position    */
-#define USB1_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE0 Mask        */
-#define USB1_ENDPTNAKEN_EPRNE1_Pos                            1                                                         /*!< USB1 ENDPTNAKEN: EPRNE1 Position    */
-#define USB1_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE1 Mask        */
-#define USB1_ENDPTNAKEN_EPRNE2_Pos                            2                                                         /*!< USB1 ENDPTNAKEN: EPRNE2 Position    */
-#define USB1_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE2 Mask        */
-#define USB1_ENDPTNAKEN_EPRNE3_Pos                            3                                                         /*!< USB1 ENDPTNAKEN: EPRNE3 Position    */
-#define USB1_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos)                    /*!< USB1 ENDPTNAKEN: EPRNE3 Mask        */
-#define USB1_ENDPTNAKEN_EPTNE16_Pos                           16                                                        /*!< USB1 ENDPTNAKEN: EPTNE16 Position   */
-#define USB1_ENDPTNAKEN_EPTNE16_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE16 Mask       */
-#define USB1_ENDPTNAKEN_EPTNE17_Pos                           17                                                        /*!< USB1 ENDPTNAKEN: EPTNE17 Position   */
-#define USB1_ENDPTNAKEN_EPTNE17_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE17 Mask       */
-#define USB1_ENDPTNAKEN_EPTNE18_Pos                           18                                                        /*!< USB1 ENDPTNAKEN: EPTNE18 Position   */
-#define USB1_ENDPTNAKEN_EPTNE18_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE18 Mask       */
-#define USB1_ENDPTNAKEN_EPTNE19_Pos                           19                                                        /*!< USB1 ENDPTNAKEN: EPTNE19 Position   */
-#define USB1_ENDPTNAKEN_EPTNE19_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos)                   /*!< USB1 ENDPTNAKEN: EPTNE19 Mask       */
-
-// -------------------------------------  USB1_PORTSC1_D  -----------------------------------------
-#define USB1_PORTSC1_D_CCS_Pos                                0                                                         /*!< USB1 PORTSC1_D: CCS Position        */
-#define USB1_PORTSC1_D_CCS_Msk                                (0x01UL << USB1_PORTSC1_D_CCS_Pos)                        /*!< USB1 PORTSC1_D: CCS Mask            */
-#define USB1_PORTSC1_D_CSC_Pos                                1                                                         /*!< USB1 PORTSC1_D: CSC Position        */
-#define USB1_PORTSC1_D_CSC_Msk                                (0x01UL << USB1_PORTSC1_D_CSC_Pos)                        /*!< USB1 PORTSC1_D: CSC Mask            */
-#define USB1_PORTSC1_D_PE_Pos                                 2                                                         /*!< USB1 PORTSC1_D: PE Position         */
-#define USB1_PORTSC1_D_PE_Msk                                 (0x01UL << USB1_PORTSC1_D_PE_Pos)                         /*!< USB1 PORTSC1_D: PE Mask             */
-#define USB1_PORTSC1_D_PEC_Pos                                3                                                         /*!< USB1 PORTSC1_D: PEC Position        */
-#define USB1_PORTSC1_D_PEC_Msk                                (0x01UL << USB1_PORTSC1_D_PEC_Pos)                        /*!< USB1 PORTSC1_D: PEC Mask            */
-#define USB1_PORTSC1_D_FPR_Pos                                6                                                         /*!< USB1 PORTSC1_D: FPR Position        */
-#define USB1_PORTSC1_D_FPR_Msk                                (0x01UL << USB1_PORTSC1_D_FPR_Pos)                        /*!< USB1 PORTSC1_D: FPR Mask            */
-#define USB1_PORTSC1_D_SUSP_Pos                               7                                                         /*!< USB1 PORTSC1_D: SUSP Position       */
-#define USB1_PORTSC1_D_SUSP_Msk                               (0x01UL << USB1_PORTSC1_D_SUSP_Pos)                       /*!< USB1 PORTSC1_D: SUSP Mask           */
-#define USB1_PORTSC1_D_PR_Pos                                 8                                                         /*!< USB1 PORTSC1_D: PR Position         */
-#define USB1_PORTSC1_D_PR_Msk                                 (0x01UL << USB1_PORTSC1_D_PR_Pos)                         /*!< USB1 PORTSC1_D: PR Mask             */
-#define USB1_PORTSC1_D_HSP_Pos                                9                                                         /*!< USB1 PORTSC1_D: HSP Position        */
-#define USB1_PORTSC1_D_HSP_Msk                                (0x01UL << USB1_PORTSC1_D_HSP_Pos)                        /*!< USB1 PORTSC1_D: HSP Mask            */
-#define USB1_PORTSC1_D_LS_Pos                                 10                                                        /*!< USB1 PORTSC1_D: LS Position         */
-#define USB1_PORTSC1_D_LS_Msk                                 (0x03UL << USB1_PORTSC1_D_LS_Pos)                         /*!< USB1 PORTSC1_D: LS Mask             */
-#define USB1_PORTSC1_D_PP_Pos                                 12                                                        /*!< USB1 PORTSC1_D: PP Position         */
-#define USB1_PORTSC1_D_PP_Msk                                 (0x01UL << USB1_PORTSC1_D_PP_Pos)                         /*!< USB1 PORTSC1_D: PP Mask             */
-#define USB1_PORTSC1_D_PIC1_0_Pos                             14                                                        /*!< USB1 PORTSC1_D: PIC1_0 Position     */
-#define USB1_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos)                     /*!< USB1 PORTSC1_D: PIC1_0 Mask         */
-#define USB1_PORTSC1_D_PTC3_0_Pos                             16                                                        /*!< USB1 PORTSC1_D: PTC3_0 Position     */
-#define USB1_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos)                     /*!< USB1 PORTSC1_D: PTC3_0 Mask         */
-#define USB1_PORTSC1_D_PHCD_Pos                               23                                                        /*!< USB1 PORTSC1_D: PHCD Position       */
-#define USB1_PORTSC1_D_PHCD_Msk                               (0x01UL << USB1_PORTSC1_D_PHCD_Pos)                       /*!< USB1 PORTSC1_D: PHCD Mask           */
-#define USB1_PORTSC1_D_PFSC_Pos                               24                                                        /*!< USB1 PORTSC1_D: PFSC Position       */
-#define USB1_PORTSC1_D_PFSC_Msk                               (0x01UL << USB1_PORTSC1_D_PFSC_Pos)                       /*!< USB1 PORTSC1_D: PFSC Mask           */
-#define USB1_PORTSC1_D_PSPD_Pos                               26                                                        /*!< USB1 PORTSC1_D: PSPD Position       */
-#define USB1_PORTSC1_D_PSPD_Msk                               (0x03UL << USB1_PORTSC1_D_PSPD_Pos)                       /*!< USB1 PORTSC1_D: PSPD Mask           */
-#define USB1_PORTSC1_D_PTS_Pos                                30                                                        /*!< USB1 PORTSC1_D: PTS Position        */
-#define USB1_PORTSC1_D_PTS_Msk                                (0x03UL << USB1_PORTSC1_D_PTS_Pos)                        /*!< USB1 PORTSC1_D: PTS Mask            */
-
-// -------------------------------------  USB1_PORTSC1_H  -----------------------------------------
-#define USB1_PORTSC1_H_CCS_Pos                                0                                                         /*!< USB1 PORTSC1_H: CCS Position        */
-#define USB1_PORTSC1_H_CCS_Msk                                (0x01UL << USB1_PORTSC1_H_CCS_Pos)                        /*!< USB1 PORTSC1_H: CCS Mask            */
-#define USB1_PORTSC1_H_CSC_Pos                                1                                                         /*!< USB1 PORTSC1_H: CSC Position        */
-#define USB1_PORTSC1_H_CSC_Msk                                (0x01UL << USB1_PORTSC1_H_CSC_Pos)                        /*!< USB1 PORTSC1_H: CSC Mask            */
-#define USB1_PORTSC1_H_PE_Pos                                 2                                                         /*!< USB1 PORTSC1_H: PE Position         */
-#define USB1_PORTSC1_H_PE_Msk                                 (0x01UL << USB1_PORTSC1_H_PE_Pos)                         /*!< USB1 PORTSC1_H: PE Mask             */
-#define USB1_PORTSC1_H_PEC_Pos                                3                                                         /*!< USB1 PORTSC1_H: PEC Position        */
-#define USB1_PORTSC1_H_PEC_Msk                                (0x01UL << USB1_PORTSC1_H_PEC_Pos)                        /*!< USB1 PORTSC1_H: PEC Mask            */
-#define USB1_PORTSC1_H_OCA_Pos                                4                                                         /*!< USB1 PORTSC1_H: OCA Position        */
-#define USB1_PORTSC1_H_OCA_Msk                                (0x01UL << USB1_PORTSC1_H_OCA_Pos)                        /*!< USB1 PORTSC1_H: OCA Mask            */
-#define USB1_PORTSC1_H_OCC_Pos                                5                                                         /*!< USB1 PORTSC1_H: OCC Position        */
-#define USB1_PORTSC1_H_OCC_Msk                                (0x01UL << USB1_PORTSC1_H_OCC_Pos)                        /*!< USB1 PORTSC1_H: OCC Mask            */
-#define USB1_PORTSC1_H_FPR_Pos                                6                                                         /*!< USB1 PORTSC1_H: FPR Position        */
-#define USB1_PORTSC1_H_FPR_Msk                                (0x01UL << USB1_PORTSC1_H_FPR_Pos)                        /*!< USB1 PORTSC1_H: FPR Mask            */
-#define USB1_PORTSC1_H_SUSP_Pos                               7                                                         /*!< USB1 PORTSC1_H: SUSP Position       */
-#define USB1_PORTSC1_H_SUSP_Msk                               (0x01UL << USB1_PORTSC1_H_SUSP_Pos)                       /*!< USB1 PORTSC1_H: SUSP Mask           */
-#define USB1_PORTSC1_H_PR_Pos                                 8                                                         /*!< USB1 PORTSC1_H: PR Position         */
-#define USB1_PORTSC1_H_PR_Msk                                 (0x01UL << USB1_PORTSC1_H_PR_Pos)                         /*!< USB1 PORTSC1_H: PR Mask             */
-#define USB1_PORTSC1_H_HSP_Pos                                9                                                         /*!< USB1 PORTSC1_H: HSP Position        */
-#define USB1_PORTSC1_H_HSP_Msk                                (0x01UL << USB1_PORTSC1_H_HSP_Pos)                        /*!< USB1 PORTSC1_H: HSP Mask            */
-#define USB1_PORTSC1_H_LS_Pos                                 10                                                        /*!< USB1 PORTSC1_H: LS Position         */
-#define USB1_PORTSC1_H_LS_Msk                                 (0x03UL << USB1_PORTSC1_H_LS_Pos)                         /*!< USB1 PORTSC1_H: LS Mask             */
-#define USB1_PORTSC1_H_PP_Pos                                 12                                                        /*!< USB1 PORTSC1_H: PP Position         */
-#define USB1_PORTSC1_H_PP_Msk                                 (0x01UL << USB1_PORTSC1_H_PP_Pos)                         /*!< USB1 PORTSC1_H: PP Mask             */
-#define USB1_PORTSC1_H_PIC1_0_Pos                             14                                                        /*!< USB1 PORTSC1_H: PIC1_0 Position     */
-#define USB1_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos)                     /*!< USB1 PORTSC1_H: PIC1_0 Mask         */
-#define USB1_PORTSC1_H_PTC3_0_Pos                             16                                                        /*!< USB1 PORTSC1_H: PTC3_0 Position     */
-#define USB1_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos)                     /*!< USB1 PORTSC1_H: PTC3_0 Mask         */
-#define USB1_PORTSC1_H_WKCN_Pos                               20                                                        /*!< USB1 PORTSC1_H: WKCN Position       */
-#define USB1_PORTSC1_H_WKCN_Msk                               (0x01UL << USB1_PORTSC1_H_WKCN_Pos)                       /*!< USB1 PORTSC1_H: WKCN Mask           */
-#define USB1_PORTSC1_H_WKDC_Pos                               21                                                        /*!< USB1 PORTSC1_H: WKDC Position       */
-#define USB1_PORTSC1_H_WKDC_Msk                               (0x01UL << USB1_PORTSC1_H_WKDC_Pos)                       /*!< USB1 PORTSC1_H: WKDC Mask           */
-#define USB1_PORTSC1_H_WKOC_Pos                               22                                                        /*!< USB1 PORTSC1_H: WKOC Position       */
-#define USB1_PORTSC1_H_WKOC_Msk                               (0x01UL << USB1_PORTSC1_H_WKOC_Pos)                       /*!< USB1 PORTSC1_H: WKOC Mask           */
-#define USB1_PORTSC1_H_PHCD_Pos                               23                                                        /*!< USB1 PORTSC1_H: PHCD Position       */
-#define USB1_PORTSC1_H_PHCD_Msk                               (0x01UL << USB1_PORTSC1_H_PHCD_Pos)                       /*!< USB1 PORTSC1_H: PHCD Mask           */
-#define USB1_PORTSC1_H_PFSC_Pos                               24                                                        /*!< USB1 PORTSC1_H: PFSC Position       */
-#define USB1_PORTSC1_H_PFSC_Msk                               (0x01UL << USB1_PORTSC1_H_PFSC_Pos)                       /*!< USB1 PORTSC1_H: PFSC Mask           */
-#define USB1_PORTSC1_H_PSPD_Pos                               26                                                        /*!< USB1 PORTSC1_H: PSPD Position       */
-#define USB1_PORTSC1_H_PSPD_Msk                               (0x03UL << USB1_PORTSC1_H_PSPD_Pos)                       /*!< USB1 PORTSC1_H: PSPD Mask           */
-#define USB1_PORTSC1_H_PTS_Pos                                30                                                        /*!< USB1 PORTSC1_H: PTS Position        */
-#define USB1_PORTSC1_H_PTS_Msk                                (0x03UL << USB1_PORTSC1_H_PTS_Pos)                        /*!< USB1 PORTSC1_H: PTS Mask            */
-
-// -------------------------------------  USB1_USBMODE_D  -----------------------------------------
-#define USB1_USBMODE_D_CM1_0_Pos                              0                                                         /*!< USB1 USBMODE_D: CM1_0 Position      */
-#define USB1_USBMODE_D_CM1_0_Msk                              (0x03UL << USB1_USBMODE_D_CM1_0_Pos)                      /*!< USB1 USBMODE_D: CM1_0 Mask          */
-#define USB1_USBMODE_D_ES_Pos                                 2                                                         /*!< USB1 USBMODE_D: ES Position         */
-#define USB1_USBMODE_D_ES_Msk                                 (0x01UL << USB1_USBMODE_D_ES_Pos)                         /*!< USB1 USBMODE_D: ES Mask             */
-#define USB1_USBMODE_D_SLOM_Pos                               3                                                         /*!< USB1 USBMODE_D: SLOM Position       */
-#define USB1_USBMODE_D_SLOM_Msk                               (0x01UL << USB1_USBMODE_D_SLOM_Pos)                       /*!< USB1 USBMODE_D: SLOM Mask           */
-#define USB1_USBMODE_D_SDIS_Pos                               4                                                         /*!< USB1 USBMODE_D: SDIS Position       */
-#define USB1_USBMODE_D_SDIS_Msk                               (0x01UL << USB1_USBMODE_D_SDIS_Pos)                       /*!< USB1 USBMODE_D: SDIS Mask           */
-
-// -------------------------------------  USB1_USBMODE_H  -----------------------------------------
-#define USB1_USBMODE_H_CM1_0_Pos                              0                                                         /*!< USB1 USBMODE_H: CM1_0 Position      */
-#define USB1_USBMODE_H_CM1_0_Msk                              (0x03UL << USB1_USBMODE_H_CM1_0_Pos)                      /*!< USB1 USBMODE_H: CM1_0 Mask          */
-#define USB1_USBMODE_H_ES_Pos                                 2                                                         /*!< USB1 USBMODE_H: ES Position         */
-#define USB1_USBMODE_H_ES_Msk                                 (0x01UL << USB1_USBMODE_H_ES_Pos)                         /*!< USB1 USBMODE_H: ES Mask             */
-#define USB1_USBMODE_H_SDIS_Pos                               4                                                         /*!< USB1 USBMODE_H: SDIS Position       */
-#define USB1_USBMODE_H_SDIS_Msk                               (0x01UL << USB1_USBMODE_H_SDIS_Pos)                       /*!< USB1 USBMODE_H: SDIS Mask           */
-#define USB1_USBMODE_H_VBPS_Pos                               5                                                         /*!< USB1 USBMODE_H: VBPS Position       */
-#define USB1_USBMODE_H_VBPS_Msk                               (0x01UL << USB1_USBMODE_H_VBPS_Pos)                       /*!< USB1 USBMODE_H: VBPS Mask           */
-
-// -----------------------------------  USB1_ENDPTSETUPSTAT  --------------------------------------
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3                                                         /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)       /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
-
-// -------------------------------------  USB1_ENDPTPRIME  ----------------------------------------
-#define USB1_ENDPTPRIME_PERB0_Pos                             0                                                         /*!< USB1 ENDPTPRIME: PERB0 Position     */
-#define USB1_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB0_Pos)                     /*!< USB1 ENDPTPRIME: PERB0 Mask         */
-#define USB1_ENDPTPRIME_PERB1_Pos                             1                                                         /*!< USB1 ENDPTPRIME: PERB1 Position     */
-#define USB1_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB1_Pos)                     /*!< USB1 ENDPTPRIME: PERB1 Mask         */
-#define USB1_ENDPTPRIME_PERB2_Pos                             2                                                         /*!< USB1 ENDPTPRIME: PERB2 Position     */
-#define USB1_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB2_Pos)                     /*!< USB1 ENDPTPRIME: PERB2 Mask         */
-#define USB1_ENDPTPRIME_PERB3_Pos                             3                                                         /*!< USB1 ENDPTPRIME: PERB3 Position     */
-#define USB1_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB3_Pos)                     /*!< USB1 ENDPTPRIME: PERB3 Mask         */
-#define USB1_ENDPTPRIME_PETB0_Pos                             16                                                        /*!< USB1 ENDPTPRIME: PETB0 Position     */
-#define USB1_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB0_Pos)                     /*!< USB1 ENDPTPRIME: PETB0 Mask         */
-#define USB1_ENDPTPRIME_PETB1_Pos                             17                                                        /*!< USB1 ENDPTPRIME: PETB1 Position     */
-#define USB1_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB1_Pos)                     /*!< USB1 ENDPTPRIME: PETB1 Mask         */
-#define USB1_ENDPTPRIME_PETB2_Pos                             18                                                        /*!< USB1 ENDPTPRIME: PETB2 Position     */
-#define USB1_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB2_Pos)                     /*!< USB1 ENDPTPRIME: PETB2 Mask         */
-#define USB1_ENDPTPRIME_PETB3_Pos                             19                                                        /*!< USB1 ENDPTPRIME: PETB3 Position     */
-#define USB1_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB3_Pos)                     /*!< USB1 ENDPTPRIME: PETB3 Mask         */
-
-// -------------------------------------  USB1_ENDPTFLUSH  ----------------------------------------
-#define USB1_ENDPTFLUSH_FERB0_Pos                             0                                                         /*!< USB1 ENDPTFLUSH: FERB0 Position     */
-#define USB1_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos)                     /*!< USB1 ENDPTFLUSH: FERB0 Mask         */
-#define USB1_ENDPTFLUSH_FERB1_Pos                             1                                                         /*!< USB1 ENDPTFLUSH: FERB1 Position     */
-#define USB1_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos)                     /*!< USB1 ENDPTFLUSH: FERB1 Mask         */
-#define USB1_ENDPTFLUSH_FERB2_Pos                             2                                                         /*!< USB1 ENDPTFLUSH: FERB2 Position     */
-#define USB1_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos)                     /*!< USB1 ENDPTFLUSH: FERB2 Mask         */
-#define USB1_ENDPTFLUSH_FERB3_Pos                             3                                                         /*!< USB1 ENDPTFLUSH: FERB3 Position     */
-#define USB1_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos)                     /*!< USB1 ENDPTFLUSH: FERB3 Mask         */
-#define USB1_ENDPTFLUSH_FETB0_Pos                             16                                                        /*!< USB1 ENDPTFLUSH: FETB0 Position     */
-#define USB1_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos)                     /*!< USB1 ENDPTFLUSH: FETB0 Mask         */
-#define USB1_ENDPTFLUSH_FETB1_Pos                             17                                                        /*!< USB1 ENDPTFLUSH: FETB1 Position     */
-#define USB1_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos)                     /*!< USB1 ENDPTFLUSH: FETB1 Mask         */
-#define USB1_ENDPTFLUSH_FETB2_Pos                             18                                                        /*!< USB1 ENDPTFLUSH: FETB2 Position     */
-#define USB1_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos)                     /*!< USB1 ENDPTFLUSH: FETB2 Mask         */
-#define USB1_ENDPTFLUSH_FETB3_Pos                             19                                                        /*!< USB1 ENDPTFLUSH: FETB3 Position     */
-#define USB1_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos)                     /*!< USB1 ENDPTFLUSH: FETB3 Mask         */
-
-// -------------------------------------  USB1_ENDPTSTAT  -----------------------------------------
-#define USB1_ENDPTSTAT_ERBR0_Pos                              0                                                         /*!< USB1 ENDPTSTAT: ERBR0 Position      */
-#define USB1_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos)                      /*!< USB1 ENDPTSTAT: ERBR0 Mask          */
-#define USB1_ENDPTSTAT_ERBR1_Pos                              1                                                         /*!< USB1 ENDPTSTAT: ERBR1 Position      */
-#define USB1_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos)                      /*!< USB1 ENDPTSTAT: ERBR1 Mask          */
-#define USB1_ENDPTSTAT_ERBR2_Pos                              2                                                         /*!< USB1 ENDPTSTAT: ERBR2 Position      */
-#define USB1_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos)                      /*!< USB1 ENDPTSTAT: ERBR2 Mask          */
-#define USB1_ENDPTSTAT_ERBR3_Pos                              3                                                         /*!< USB1 ENDPTSTAT: ERBR3 Position      */
-#define USB1_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos)                      /*!< USB1 ENDPTSTAT: ERBR3 Mask          */
-#define USB1_ENDPTSTAT_ETBR0_Pos                              16                                                        /*!< USB1 ENDPTSTAT: ETBR0 Position      */
-#define USB1_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos)                      /*!< USB1 ENDPTSTAT: ETBR0 Mask          */
-#define USB1_ENDPTSTAT_ETBR1_Pos                              17                                                        /*!< USB1 ENDPTSTAT: ETBR1 Position      */
-#define USB1_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos)                      /*!< USB1 ENDPTSTAT: ETBR1 Mask          */
-#define USB1_ENDPTSTAT_ETBR2_Pos                              18                                                        /*!< USB1 ENDPTSTAT: ETBR2 Position      */
-#define USB1_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos)                      /*!< USB1 ENDPTSTAT: ETBR2 Mask          */
-#define USB1_ENDPTSTAT_ETBR3_Pos                              19                                                        /*!< USB1 ENDPTSTAT: ETBR3 Position      */
-#define USB1_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos)                      /*!< USB1 ENDPTSTAT: ETBR3 Mask          */
-
-// -----------------------------------  USB1_ENDPTCOMPLETE  ---------------------------------------
-#define USB1_ENDPTCOMPLETE_ERCE0_Pos                          0                                                         /*!< USB1 ENDPTCOMPLETE: ERCE0 Position  */
-#define USB1_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask      */
-#define USB1_ENDPTCOMPLETE_ERCE1_Pos                          1                                                         /*!< USB1 ENDPTCOMPLETE: ERCE1 Position  */
-#define USB1_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask      */
-#define USB1_ENDPTCOMPLETE_ERCE2_Pos                          2                                                         /*!< USB1 ENDPTCOMPLETE: ERCE2 Position  */
-#define USB1_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask      */
-#define USB1_ENDPTCOMPLETE_ERCE3_Pos                          3                                                         /*!< USB1 ENDPTCOMPLETE: ERCE3 Position  */
-#define USB1_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos)                  /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask      */
-#define USB1_ENDPTCOMPLETE_ETCE0_Pos                          16                                                        /*!< USB1 ENDPTCOMPLETE: ETCE0 Position  */
-#define USB1_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask      */
-#define USB1_ENDPTCOMPLETE_ETCE1_Pos                          17                                                        /*!< USB1 ENDPTCOMPLETE: ETCE1 Position  */
-#define USB1_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask      */
-#define USB1_ENDPTCOMPLETE_ETCE2_Pos                          18                                                        /*!< USB1 ENDPTCOMPLETE: ETCE2 Position  */
-#define USB1_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask      */
-#define USB1_ENDPTCOMPLETE_ETCE3_Pos                          19                                                        /*!< USB1 ENDPTCOMPLETE: ETCE3 Position  */
-#define USB1_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos)                  /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask      */
-
-// -------------------------------------  USB1_ENDPTCTRL0  ----------------------------------------
-#define USB1_ENDPTCTRL0_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL0: RXS Position       */
-#define USB1_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXS_Pos)                       /*!< USB1 ENDPTCTRL0: RXS Mask           */
-#define USB1_ENDPTCTRL0_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL0: RXT Position       */
-#define USB1_ENDPTCTRL0_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_RXT_Pos)                       /*!< USB1 ENDPTCTRL0: RXT Mask           */
-#define USB1_ENDPTCTRL0_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL0: RXE Position       */
-#define USB1_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXE_Pos)                       /*!< USB1 ENDPTCTRL0: RXE Mask           */
-#define USB1_ENDPTCTRL0_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL0: TXS Position       */
-#define USB1_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXS_Pos)                       /*!< USB1 ENDPTCTRL0: TXS Mask           */
-#define USB1_ENDPTCTRL0_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL0: TXT Position       */
-#define USB1_ENDPTCTRL0_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_TXT_Pos)                       /*!< USB1 ENDPTCTRL0: TXT Mask           */
-#define USB1_ENDPTCTRL0_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL0: TXE Position       */
-#define USB1_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXE_Pos)                       /*!< USB1 ENDPTCTRL0: TXE Mask           */
-
-// -------------------------------------  USB1_ENDPTCTRL1  ----------------------------------------
-#define USB1_ENDPTCTRL1_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL1: RXS Position       */
-#define USB1_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXS_Pos)                       /*!< USB1 ENDPTCTRL1: RXS Mask           */
-#define USB1_ENDPTCTRL1_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL1: RXT Position       */
-#define USB1_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_RXT_Pos)                       /*!< USB1 ENDPTCTRL1: RXT Mask           */
-#define USB1_ENDPTCTRL1_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL1: RXI Position       */
-#define USB1_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXI_Pos)                       /*!< USB1 ENDPTCTRL1: RXI Mask           */
-#define USB1_ENDPTCTRL1_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL1: RXR Position       */
-#define USB1_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXR_Pos)                       /*!< USB1 ENDPTCTRL1: RXR Mask           */
-#define USB1_ENDPTCTRL1_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL1: RXE Position       */
-#define USB1_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXE_Pos)                       /*!< USB1 ENDPTCTRL1: RXE Mask           */
-#define USB1_ENDPTCTRL1_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL1: TXS Position       */
-#define USB1_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXS_Pos)                       /*!< USB1 ENDPTCTRL1: TXS Mask           */
-#define USB1_ENDPTCTRL1_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL1: TXT Position       */
-#define USB1_ENDPTCTRL1_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_TXT_Pos)                       /*!< USB1 ENDPTCTRL1: TXT Mask           */
-#define USB1_ENDPTCTRL1_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL1: TXI Position       */
-#define USB1_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXI_Pos)                       /*!< USB1 ENDPTCTRL1: TXI Mask           */
-#define USB1_ENDPTCTRL1_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL1: TXR Position       */
-#define USB1_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXR_Pos)                       /*!< USB1 ENDPTCTRL1: TXR Mask           */
-#define USB1_ENDPTCTRL1_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL1: TXE Position       */
-#define USB1_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXE_Pos)                       /*!< USB1 ENDPTCTRL1: TXE Mask           */
-
-// -------------------------------------  USB1_ENDPTCTRL2  ----------------------------------------
-#define USB1_ENDPTCTRL2_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL2: RXS Position       */
-#define USB1_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXS_Pos)                       /*!< USB1 ENDPTCTRL2: RXS Mask           */
-#define USB1_ENDPTCTRL2_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL2: RXT Position       */
-#define USB1_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_RXT_Pos)                       /*!< USB1 ENDPTCTRL2: RXT Mask           */
-#define USB1_ENDPTCTRL2_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL2: RXI Position       */
-#define USB1_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXI_Pos)                       /*!< USB1 ENDPTCTRL2: RXI Mask           */
-#define USB1_ENDPTCTRL2_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL2: RXR Position       */
-#define USB1_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXR_Pos)                       /*!< USB1 ENDPTCTRL2: RXR Mask           */
-#define USB1_ENDPTCTRL2_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL2: RXE Position       */
-#define USB1_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXE_Pos)                       /*!< USB1 ENDPTCTRL2: RXE Mask           */
-#define USB1_ENDPTCTRL2_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL2: TXS Position       */
-#define USB1_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXS_Pos)                       /*!< USB1 ENDPTCTRL2: TXS Mask           */
-#define USB1_ENDPTCTRL2_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL2: TXT Position       */
-#define USB1_ENDPTCTRL2_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_TXT_Pos)                       /*!< USB1 ENDPTCTRL2: TXT Mask           */
-#define USB1_ENDPTCTRL2_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL2: TXI Position       */
-#define USB1_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXI_Pos)                       /*!< USB1 ENDPTCTRL2: TXI Mask           */
-#define USB1_ENDPTCTRL2_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL2: TXR Position       */
-#define USB1_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXR_Pos)                       /*!< USB1 ENDPTCTRL2: TXR Mask           */
-#define USB1_ENDPTCTRL2_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL2: TXE Position       */
-#define USB1_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXE_Pos)                       /*!< USB1 ENDPTCTRL2: TXE Mask           */
-
-// -------------------------------------  USB1_ENDPTCTRL3  ----------------------------------------
-#define USB1_ENDPTCTRL3_RXS_Pos                               0                                                         /*!< USB1 ENDPTCTRL3: RXS Position       */
-#define USB1_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXS_Pos)                       /*!< USB1 ENDPTCTRL3: RXS Mask           */
-#define USB1_ENDPTCTRL3_RXT_Pos                               2                                                         /*!< USB1 ENDPTCTRL3: RXT Position       */
-#define USB1_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_RXT_Pos)                       /*!< USB1 ENDPTCTRL3: RXT Mask           */
-#define USB1_ENDPTCTRL3_RXI_Pos                               5                                                         /*!< USB1 ENDPTCTRL3: RXI Position       */
-#define USB1_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXI_Pos)                       /*!< USB1 ENDPTCTRL3: RXI Mask           */
-#define USB1_ENDPTCTRL3_RXR_Pos                               6                                                         /*!< USB1 ENDPTCTRL3: RXR Position       */
-#define USB1_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXR_Pos)                       /*!< USB1 ENDPTCTRL3: RXR Mask           */
-#define USB1_ENDPTCTRL3_RXE_Pos                               7                                                         /*!< USB1 ENDPTCTRL3: RXE Position       */
-#define USB1_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXE_Pos)                       /*!< USB1 ENDPTCTRL3: RXE Mask           */
-#define USB1_ENDPTCTRL3_TXS_Pos                               16                                                        /*!< USB1 ENDPTCTRL3: TXS Position       */
-#define USB1_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXS_Pos)                       /*!< USB1 ENDPTCTRL3: TXS Mask           */
-#define USB1_ENDPTCTRL3_TXT_Pos                               18                                                        /*!< USB1 ENDPTCTRL3: TXT Position       */
-#define USB1_ENDPTCTRL3_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_TXT_Pos)                       /*!< USB1 ENDPTCTRL3: TXT Mask           */
-#define USB1_ENDPTCTRL3_TXI_Pos                               21                                                        /*!< USB1 ENDPTCTRL3: TXI Position       */
-#define USB1_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXI_Pos)                       /*!< USB1 ENDPTCTRL3: TXI Mask           */
-#define USB1_ENDPTCTRL3_TXR_Pos                               22                                                        /*!< USB1 ENDPTCTRL3: TXR Position       */
-#define USB1_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXR_Pos)                       /*!< USB1 ENDPTCTRL3: TXR Mask           */
-#define USB1_ENDPTCTRL3_TXE_Pos                               23                                                        /*!< USB1 ENDPTCTRL3: TXE Position       */
-#define USB1_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXE_Pos)                       /*!< USB1 ENDPTCTRL3: TXE Mask           */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  LCD Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  LCD_TIMH  --------------------------------------------
-#define LCD_TIMH_PPL_Pos                                      2                                                         /*!< LCD TIMH: PPL Position              */
-#define LCD_TIMH_PPL_Msk                                      (0x3fUL << LCD_TIMH_PPL_Pos)                              /*!< LCD TIMH: PPL Mask                  */
-#define LCD_TIMH_HSW_Pos                                      8                                                         /*!< LCD TIMH: HSW Position              */
-#define LCD_TIMH_HSW_Msk                                      (0x000000ffUL << LCD_TIMH_HSW_Pos)                        /*!< LCD TIMH: HSW Mask                  */
-#define LCD_TIMH_HFP_Pos                                      16                                                        /*!< LCD TIMH: HFP Position              */
-#define LCD_TIMH_HFP_Msk                                      (0x000000ffUL << LCD_TIMH_HFP_Pos)                        /*!< LCD TIMH: HFP Mask                  */
-#define LCD_TIMH_HBP_Pos                                      24                                                        /*!< LCD TIMH: HBP Position              */
-#define LCD_TIMH_HBP_Msk                                      (0x000000ffUL << LCD_TIMH_HBP_Pos)                        /*!< LCD TIMH: HBP Mask                  */
-
-// ----------------------------------------  LCD_TIMV  --------------------------------------------
-#define LCD_TIMV_LPP_Pos                                      0                                                         /*!< LCD TIMV: LPP Position              */
-#define LCD_TIMV_LPP_Msk                                      (0x000003ffUL << LCD_TIMV_LPP_Pos)                        /*!< LCD TIMV: LPP Mask                  */
-#define LCD_TIMV_VSW_Pos                                      10                                                        /*!< LCD TIMV: VSW Position              */
-#define LCD_TIMV_VSW_Msk                                      (0x3fUL << LCD_TIMV_VSW_Pos)                              /*!< LCD TIMV: VSW Mask                  */
-#define LCD_TIMV_VFP_Pos                                      16                                                        /*!< LCD TIMV: VFP Position              */
-#define LCD_TIMV_VFP_Msk                                      (0x000000ffUL << LCD_TIMV_VFP_Pos)                        /*!< LCD TIMV: VFP Mask                  */
-#define LCD_TIMV_VBP_Pos                                      24                                                        /*!< LCD TIMV: VBP Position              */
-#define LCD_TIMV_VBP_Msk                                      (0x000000ffUL << LCD_TIMV_VBP_Pos)                        /*!< LCD TIMV: VBP Mask                  */
-
-// -----------------------------------------  LCD_POL  --------------------------------------------
-#define LCD_POL_PCD_LO_Pos                                    0                                                         /*!< LCD POL: PCD_LO Position            */
-#define LCD_POL_PCD_LO_Msk                                    (0x1fUL << LCD_POL_PCD_LO_Pos)                            /*!< LCD POL: PCD_LO Mask                */
-#define LCD_POL_CLKSEL_Pos                                    5                                                         /*!< LCD POL: CLKSEL Position            */
-#define LCD_POL_CLKSEL_Msk                                    (0x01UL << LCD_POL_CLKSEL_Pos)                            /*!< LCD POL: CLKSEL Mask                */
-#define LCD_POL_ACB_Pos                                       6                                                         /*!< LCD POL: ACB Position               */
-#define LCD_POL_ACB_Msk                                       (0x1fUL << LCD_POL_ACB_Pos)                               /*!< LCD POL: ACB Mask                   */
-#define LCD_POL_IVS_Pos                                       11                                                        /*!< LCD POL: IVS Position               */
-#define LCD_POL_IVS_Msk                                       (0x01UL << LCD_POL_IVS_Pos)                               /*!< LCD POL: IVS Mask                   */
-#define LCD_POL_IHS_Pos                                       12                                                        /*!< LCD POL: IHS Position               */
-#define LCD_POL_IHS_Msk                                       (0x01UL << LCD_POL_IHS_Pos)                               /*!< LCD POL: IHS Mask                   */
-#define LCD_POL_IPC_Pos                                       13                                                        /*!< LCD POL: IPC Position               */
-#define LCD_POL_IPC_Msk                                       (0x01UL << LCD_POL_IPC_Pos)                               /*!< LCD POL: IPC Mask                   */
-#define LCD_POL_IOE_Pos                                       14                                                        /*!< LCD POL: IOE Position               */
-#define LCD_POL_IOE_Msk                                       (0x01UL << LCD_POL_IOE_Pos)                               /*!< LCD POL: IOE Mask                   */
-#define LCD_POL_CPL_Pos                                       16                                                        /*!< LCD POL: CPL Position               */
-#define LCD_POL_CPL_Msk                                       (0x000003ffUL << LCD_POL_CPL_Pos)                         /*!< LCD POL: CPL Mask                   */
-#define LCD_POL_BCD_Pos                                       26                                                        /*!< LCD POL: BCD Position               */
-#define LCD_POL_BCD_Msk                                       (0x01UL << LCD_POL_BCD_Pos)                               /*!< LCD POL: BCD Mask                   */
-#define LCD_POL_PCD_HI_Pos                                    27                                                        /*!< LCD POL: PCD_HI Position            */
-#define LCD_POL_PCD_HI_Msk                                    (0x1fUL << LCD_POL_PCD_HI_Pos)                            /*!< LCD POL: PCD_HI Mask                */
-
-// -----------------------------------------  LCD_LE  ---------------------------------------------
-#define LCD_LE_LED_Pos                                        0                                                         /*!< LCD LE: LED Position                */
-#define LCD_LE_LED_Msk                                        (0x7fUL << LCD_LE_LED_Pos)                                /*!< LCD LE: LED Mask                    */
-#define LCD_LE_LEE_Pos                                        16                                                        /*!< LCD LE: LEE Position                */
-#define LCD_LE_LEE_Msk                                        (0x01UL << LCD_LE_LEE_Pos)                                /*!< LCD LE: LEE Mask                    */
-
-// ---------------------------------------  LCD_UPBASE  -------------------------------------------
-#define LCD_UPBASE_LCDUPBASE_Pos                              3                                                         /*!< LCD UPBASE: LCDUPBASE Position      */
-#define LCD_UPBASE_LCDUPBASE_Msk                              (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos)                /*!< LCD UPBASE: LCDUPBASE Mask          */
-
-// ---------------------------------------  LCD_LPBASE  -------------------------------------------
-#define LCD_LPBASE_LCDLPBASE_Pos                              3                                                         /*!< LCD LPBASE: LCDLPBASE Position      */
-#define LCD_LPBASE_LCDLPBASE_Msk                              (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos)                /*!< LCD LPBASE: LCDLPBASE Mask          */
-
-// ----------------------------------------  LCD_CTRL  --------------------------------------------
-#define LCD_CTRL_LCDEN_Pos                                    0                                                         /*!< LCD CTRL: LCDEN Position            */
-#define LCD_CTRL_LCDEN_Msk                                    (0x01UL << LCD_CTRL_LCDEN_Pos)                            /*!< LCD CTRL: LCDEN Mask                */
-#define LCD_CTRL_LCDBPP_Pos                                   1                                                         /*!< LCD CTRL: LCDBPP Position           */
-#define LCD_CTRL_LCDBPP_Msk                                   (0x07UL << LCD_CTRL_LCDBPP_Pos)                           /*!< LCD CTRL: LCDBPP Mask               */
-#define LCD_CTRL_LCDBW_Pos                                    4                                                         /*!< LCD CTRL: LCDBW Position            */
-#define LCD_CTRL_LCDBW_Msk                                    (0x01UL << LCD_CTRL_LCDBW_Pos)                            /*!< LCD CTRL: LCDBW Mask                */
-#define LCD_CTRL_LCDTFT_Pos                                   5                                                         /*!< LCD CTRL: LCDTFT Position           */
-#define LCD_CTRL_LCDTFT_Msk                                   (0x01UL << LCD_CTRL_LCDTFT_Pos)                           /*!< LCD CTRL: LCDTFT Mask               */
-#define LCD_CTRL_LCDMONO8_Pos                                 6                                                         /*!< LCD CTRL: LCDMONO8 Position         */
-#define LCD_CTRL_LCDMONO8_Msk                                 (0x01UL << LCD_CTRL_LCDMONO8_Pos)                         /*!< LCD CTRL: LCDMONO8 Mask             */
-#define LCD_CTRL_LCDDUAL_Pos                                  7                                                         /*!< LCD CTRL: LCDDUAL Position          */
-#define LCD_CTRL_LCDDUAL_Msk                                  (0x01UL << LCD_CTRL_LCDDUAL_Pos)                          /*!< LCD CTRL: LCDDUAL Mask              */
-#define LCD_CTRL_BGR_Pos                                      8                                                         /*!< LCD CTRL: BGR Position              */
-#define LCD_CTRL_BGR_Msk                                      (0x01UL << LCD_CTRL_BGR_Pos)                              /*!< LCD CTRL: BGR Mask                  */
-#define LCD_CTRL_BEBO_Pos                                     9                                                         /*!< LCD CTRL: BEBO Position             */
-#define LCD_CTRL_BEBO_Msk                                     (0x01UL << LCD_CTRL_BEBO_Pos)                             /*!< LCD CTRL: BEBO Mask                 */
-#define LCD_CTRL_BEPO_Pos                                     10                                                        /*!< LCD CTRL: BEPO Position             */
-#define LCD_CTRL_BEPO_Msk                                     (0x01UL << LCD_CTRL_BEPO_Pos)                             /*!< LCD CTRL: BEPO Mask                 */
-#define LCD_CTRL_LCDPWR_Pos                                   11                                                        /*!< LCD CTRL: LCDPWR Position           */
-#define LCD_CTRL_LCDPWR_Msk                                   (0x01UL << LCD_CTRL_LCDPWR_Pos)                           /*!< LCD CTRL: LCDPWR Mask               */
-#define LCD_CTRL_LCDVCOMP_Pos                                 12                                                        /*!< LCD CTRL: LCDVCOMP Position         */
-#define LCD_CTRL_LCDVCOMP_Msk                                 (0x03UL << LCD_CTRL_LCDVCOMP_Pos)                         /*!< LCD CTRL: LCDVCOMP Mask             */
-#define LCD_CTRL_WATERMARK_Pos                                16                                                        /*!< LCD CTRL: WATERMARK Position        */
-#define LCD_CTRL_WATERMARK_Msk                                (0x01UL << LCD_CTRL_WATERMARK_Pos)                        /*!< LCD CTRL: WATERMARK Mask            */
-
-// ---------------------------------------  LCD_INTMSK  -------------------------------------------
-#define LCD_INTMSK_FUFIM_Pos                                  1                                                         /*!< LCD INTMSK: FUFIM Position          */
-#define LCD_INTMSK_FUFIM_Msk                                  (0x01UL << LCD_INTMSK_FUFIM_Pos)                          /*!< LCD INTMSK: FUFIM Mask              */
-#define LCD_INTMSK_LNBUIM_Pos                                 2                                                         /*!< LCD INTMSK: LNBUIM Position         */
-#define LCD_INTMSK_LNBUIM_Msk                                 (0x01UL << LCD_INTMSK_LNBUIM_Pos)                         /*!< LCD INTMSK: LNBUIM Mask             */
-#define LCD_INTMSK_VCOMPIM_Pos                                3                                                         /*!< LCD INTMSK: VCOMPIM Position        */
-#define LCD_INTMSK_VCOMPIM_Msk                                (0x01UL << LCD_INTMSK_VCOMPIM_Pos)                        /*!< LCD INTMSK: VCOMPIM Mask            */
-#define LCD_INTMSK_BERIM_Pos                                  4                                                         /*!< LCD INTMSK: BERIM Position          */
-#define LCD_INTMSK_BERIM_Msk                                  (0x01UL << LCD_INTMSK_BERIM_Pos)                          /*!< LCD INTMSK: BERIM Mask              */
-
-// ---------------------------------------  LCD_INTRAW  -------------------------------------------
-#define LCD_INTRAW_FUFRIS_Pos                                 1                                                         /*!< LCD INTRAW: FUFRIS Position         */
-#define LCD_INTRAW_FUFRIS_Msk                                 (0x01UL << LCD_INTRAW_FUFRIS_Pos)                         /*!< LCD INTRAW: FUFRIS Mask             */
-#define LCD_INTRAW_LNBURIS_Pos                                2                                                         /*!< LCD INTRAW: LNBURIS Position        */
-#define LCD_INTRAW_LNBURIS_Msk                                (0x01UL << LCD_INTRAW_LNBURIS_Pos)                        /*!< LCD INTRAW: LNBURIS Mask            */
-#define LCD_INTRAW_VCOMPRIS_Pos                               3                                                         /*!< LCD INTRAW: VCOMPRIS Position       */
-#define LCD_INTRAW_VCOMPRIS_Msk                               (0x01UL << LCD_INTRAW_VCOMPRIS_Pos)                       /*!< LCD INTRAW: VCOMPRIS Mask           */
-#define LCD_INTRAW_BERRAW_Pos                                 4                                                         /*!< LCD INTRAW: BERRAW Position         */
-#define LCD_INTRAW_BERRAW_Msk                                 (0x01UL << LCD_INTRAW_BERRAW_Pos)                         /*!< LCD INTRAW: BERRAW Mask             */
-
-// ---------------------------------------  LCD_INTSTAT  ------------------------------------------
-#define LCD_INTSTAT_FUFMIS_Pos                                1                                                         /*!< LCD INTSTAT: FUFMIS Position        */
-#define LCD_INTSTAT_FUFMIS_Msk                                (0x01UL << LCD_INTSTAT_FUFMIS_Pos)                        /*!< LCD INTSTAT: FUFMIS Mask            */
-#define LCD_INTSTAT_LNBUMIS_Pos                               2                                                         /*!< LCD INTSTAT: LNBUMIS Position       */
-#define LCD_INTSTAT_LNBUMIS_Msk                               (0x01UL << LCD_INTSTAT_LNBUMIS_Pos)                       /*!< LCD INTSTAT: LNBUMIS Mask           */
-#define LCD_INTSTAT_VCOMPMIS_Pos                              3                                                         /*!< LCD INTSTAT: VCOMPMIS Position      */
-#define LCD_INTSTAT_VCOMPMIS_Msk                              (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos)                      /*!< LCD INTSTAT: VCOMPMIS Mask          */
-#define LCD_INTSTAT_BERMIS_Pos                                4                                                         /*!< LCD INTSTAT: BERMIS Position        */
-#define LCD_INTSTAT_BERMIS_Msk                                (0x01UL << LCD_INTSTAT_BERMIS_Pos)                        /*!< LCD INTSTAT: BERMIS Mask            */
-
-// ---------------------------------------  LCD_INTCLR  -------------------------------------------
-#define LCD_INTCLR_FUFIC_Pos                                  1                                                         /*!< LCD INTCLR: FUFIC Position          */
-#define LCD_INTCLR_FUFIC_Msk                                  (0x01UL << LCD_INTCLR_FUFIC_Pos)                          /*!< LCD INTCLR: FUFIC Mask              */
-#define LCD_INTCLR_LNBUIC_Pos                                 2                                                         /*!< LCD INTCLR: LNBUIC Position         */
-#define LCD_INTCLR_LNBUIC_Msk                                 (0x01UL << LCD_INTCLR_LNBUIC_Pos)                         /*!< LCD INTCLR: LNBUIC Mask             */
-#define LCD_INTCLR_VCOMPIC_Pos                                3                                                         /*!< LCD INTCLR: VCOMPIC Position        */
-#define LCD_INTCLR_VCOMPIC_Msk                                (0x01UL << LCD_INTCLR_VCOMPIC_Pos)                        /*!< LCD INTCLR: VCOMPIC Mask            */
-#define LCD_INTCLR_BERIC_Pos                                  4                                                         /*!< LCD INTCLR: BERIC Position          */
-#define LCD_INTCLR_BERIC_Msk                                  (0x01UL << LCD_INTCLR_BERIC_Pos)                          /*!< LCD INTCLR: BERIC Mask              */
-
-// ---------------------------------------  LCD_UPCURR  -------------------------------------------
-#define LCD_UPCURR_LCDUPCURR_Pos                              0                                                         /*!< LCD UPCURR: LCDUPCURR Position      */
-#define LCD_UPCURR_LCDUPCURR_Msk                              (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos)                /*!< LCD UPCURR: LCDUPCURR Mask          */
-
-// ---------------------------------------  LCD_LPCURR  -------------------------------------------
-#define LCD_LPCURR_LCDLPCURR_Pos                              0                                                         /*!< LCD LPCURR: LCDLPCURR Position      */
-#define LCD_LPCURR_LCDLPCURR_Msk                              (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos)                /*!< LCD LPCURR: LCDLPCURR Mask          */
-
-// ----------------------------------------  LCD_PAL0  --------------------------------------------
-#define LCD_PAL0_R04_0_Pos                                    0                                                         /*!< LCD PAL0: R04_0 Position            */
-#define LCD_PAL0_R04_0_Msk                                    (0x1fUL << LCD_PAL0_R04_0_Pos)                            /*!< LCD PAL0: R04_0 Mask                */
-#define LCD_PAL0_G04_0_Pos                                    5                                                         /*!< LCD PAL0: G04_0 Position            */
-#define LCD_PAL0_G04_0_Msk                                    (0x1fUL << LCD_PAL0_G04_0_Pos)                            /*!< LCD PAL0: G04_0 Mask                */
-#define LCD_PAL0_B04_0_Pos                                    10                                                        /*!< LCD PAL0: B04_0 Position            */
-#define LCD_PAL0_B04_0_Msk                                    (0x1fUL << LCD_PAL0_B04_0_Pos)                            /*!< LCD PAL0: B04_0 Mask                */
-#define LCD_PAL0_I0_Pos                                       15                                                        /*!< LCD PAL0: I0 Position               */
-#define LCD_PAL0_I0_Msk                                       (0x01UL << LCD_PAL0_I0_Pos)                               /*!< LCD PAL0: I0 Mask                   */
-#define LCD_PAL0_R14_0_Pos                                    16                                                        /*!< LCD PAL0: R14_0 Position            */
-#define LCD_PAL0_R14_0_Msk                                    (0x1fUL << LCD_PAL0_R14_0_Pos)                            /*!< LCD PAL0: R14_0 Mask                */
-#define LCD_PAL0_G14_0_Pos                                    21                                                        /*!< LCD PAL0: G14_0 Position            */
-#define LCD_PAL0_G14_0_Msk                                    (0x1fUL << LCD_PAL0_G14_0_Pos)                            /*!< LCD PAL0: G14_0 Mask                */
-#define LCD_PAL0_B14_0_Pos                                    26                                                        /*!< LCD PAL0: B14_0 Position            */
-#define LCD_PAL0_B14_0_Msk                                    (0x1fUL << LCD_PAL0_B14_0_Pos)                            /*!< LCD PAL0: B14_0 Mask                */
-#define LCD_PAL0_I1_Pos                                       31                                                        /*!< LCD PAL0: I1 Position               */
-#define LCD_PAL0_I1_Msk                                       (0x01UL << LCD_PAL0_I1_Pos)                               /*!< LCD PAL0: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL1  --------------------------------------------
-#define LCD_PAL1_R04_0_Pos                                    0                                                         /*!< LCD PAL1: R04_0 Position            */
-#define LCD_PAL1_R04_0_Msk                                    (0x1fUL << LCD_PAL1_R04_0_Pos)                            /*!< LCD PAL1: R04_0 Mask                */
-#define LCD_PAL1_G04_0_Pos                                    5                                                         /*!< LCD PAL1: G04_0 Position            */
-#define LCD_PAL1_G04_0_Msk                                    (0x1fUL << LCD_PAL1_G04_0_Pos)                            /*!< LCD PAL1: G04_0 Mask                */
-#define LCD_PAL1_B04_0_Pos                                    10                                                        /*!< LCD PAL1: B04_0 Position            */
-#define LCD_PAL1_B04_0_Msk                                    (0x1fUL << LCD_PAL1_B04_0_Pos)                            /*!< LCD PAL1: B04_0 Mask                */
-#define LCD_PAL1_I0_Pos                                       15                                                        /*!< LCD PAL1: I0 Position               */
-#define LCD_PAL1_I0_Msk                                       (0x01UL << LCD_PAL1_I0_Pos)                               /*!< LCD PAL1: I0 Mask                   */
-#define LCD_PAL1_R14_0_Pos                                    16                                                        /*!< LCD PAL1: R14_0 Position            */
-#define LCD_PAL1_R14_0_Msk                                    (0x1fUL << LCD_PAL1_R14_0_Pos)                            /*!< LCD PAL1: R14_0 Mask                */
-#define LCD_PAL1_G14_0_Pos                                    21                                                        /*!< LCD PAL1: G14_0 Position            */
-#define LCD_PAL1_G14_0_Msk                                    (0x1fUL << LCD_PAL1_G14_0_Pos)                            /*!< LCD PAL1: G14_0 Mask                */
-#define LCD_PAL1_B14_0_Pos                                    26                                                        /*!< LCD PAL1: B14_0 Position            */
-#define LCD_PAL1_B14_0_Msk                                    (0x1fUL << LCD_PAL1_B14_0_Pos)                            /*!< LCD PAL1: B14_0 Mask                */
-#define LCD_PAL1_I1_Pos                                       31                                                        /*!< LCD PAL1: I1 Position               */
-#define LCD_PAL1_I1_Msk                                       (0x01UL << LCD_PAL1_I1_Pos)                               /*!< LCD PAL1: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL2  --------------------------------------------
-#define LCD_PAL2_R04_0_Pos                                    0                                                         /*!< LCD PAL2: R04_0 Position            */
-#define LCD_PAL2_R04_0_Msk                                    (0x1fUL << LCD_PAL2_R04_0_Pos)                            /*!< LCD PAL2: R04_0 Mask                */
-#define LCD_PAL2_G04_0_Pos                                    5                                                         /*!< LCD PAL2: G04_0 Position            */
-#define LCD_PAL2_G04_0_Msk                                    (0x1fUL << LCD_PAL2_G04_0_Pos)                            /*!< LCD PAL2: G04_0 Mask                */
-#define LCD_PAL2_B04_0_Pos                                    10                                                        /*!< LCD PAL2: B04_0 Position            */
-#define LCD_PAL2_B04_0_Msk                                    (0x1fUL << LCD_PAL2_B04_0_Pos)                            /*!< LCD PAL2: B04_0 Mask                */
-#define LCD_PAL2_I0_Pos                                       15                                                        /*!< LCD PAL2: I0 Position               */
-#define LCD_PAL2_I0_Msk                                       (0x01UL << LCD_PAL2_I0_Pos)                               /*!< LCD PAL2: I0 Mask                   */
-#define LCD_PAL2_R14_0_Pos                                    16                                                        /*!< LCD PAL2: R14_0 Position            */
-#define LCD_PAL2_R14_0_Msk                                    (0x1fUL << LCD_PAL2_R14_0_Pos)                            /*!< LCD PAL2: R14_0 Mask                */
-#define LCD_PAL2_G14_0_Pos                                    21                                                        /*!< LCD PAL2: G14_0 Position            */
-#define LCD_PAL2_G14_0_Msk                                    (0x1fUL << LCD_PAL2_G14_0_Pos)                            /*!< LCD PAL2: G14_0 Mask                */
-#define LCD_PAL2_B14_0_Pos                                    26                                                        /*!< LCD PAL2: B14_0 Position            */
-#define LCD_PAL2_B14_0_Msk                                    (0x1fUL << LCD_PAL2_B14_0_Pos)                            /*!< LCD PAL2: B14_0 Mask                */
-#define LCD_PAL2_I1_Pos                                       31                                                        /*!< LCD PAL2: I1 Position               */
-#define LCD_PAL2_I1_Msk                                       (0x01UL << LCD_PAL2_I1_Pos)                               /*!< LCD PAL2: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL3  --------------------------------------------
-#define LCD_PAL3_R04_0_Pos                                    0                                                         /*!< LCD PAL3: R04_0 Position            */
-#define LCD_PAL3_R04_0_Msk                                    (0x1fUL << LCD_PAL3_R04_0_Pos)                            /*!< LCD PAL3: R04_0 Mask                */
-#define LCD_PAL3_G04_0_Pos                                    5                                                         /*!< LCD PAL3: G04_0 Position            */
-#define LCD_PAL3_G04_0_Msk                                    (0x1fUL << LCD_PAL3_G04_0_Pos)                            /*!< LCD PAL3: G04_0 Mask                */
-#define LCD_PAL3_B04_0_Pos                                    10                                                        /*!< LCD PAL3: B04_0 Position            */
-#define LCD_PAL3_B04_0_Msk                                    (0x1fUL << LCD_PAL3_B04_0_Pos)                            /*!< LCD PAL3: B04_0 Mask                */
-#define LCD_PAL3_I0_Pos                                       15                                                        /*!< LCD PAL3: I0 Position               */
-#define LCD_PAL3_I0_Msk                                       (0x01UL << LCD_PAL3_I0_Pos)                               /*!< LCD PAL3: I0 Mask                   */
-#define LCD_PAL3_R14_0_Pos                                    16                                                        /*!< LCD PAL3: R14_0 Position            */
-#define LCD_PAL3_R14_0_Msk                                    (0x1fUL << LCD_PAL3_R14_0_Pos)                            /*!< LCD PAL3: R14_0 Mask                */
-#define LCD_PAL3_G14_0_Pos                                    21                                                        /*!< LCD PAL3: G14_0 Position            */
-#define LCD_PAL3_G14_0_Msk                                    (0x1fUL << LCD_PAL3_G14_0_Pos)                            /*!< LCD PAL3: G14_0 Mask                */
-#define LCD_PAL3_B14_0_Pos                                    26                                                        /*!< LCD PAL3: B14_0 Position            */
-#define LCD_PAL3_B14_0_Msk                                    (0x1fUL << LCD_PAL3_B14_0_Pos)                            /*!< LCD PAL3: B14_0 Mask                */
-#define LCD_PAL3_I1_Pos                                       31                                                        /*!< LCD PAL3: I1 Position               */
-#define LCD_PAL3_I1_Msk                                       (0x01UL << LCD_PAL3_I1_Pos)                               /*!< LCD PAL3: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL4  --------------------------------------------
-#define LCD_PAL4_R04_0_Pos                                    0                                                         /*!< LCD PAL4: R04_0 Position            */
-#define LCD_PAL4_R04_0_Msk                                    (0x1fUL << LCD_PAL4_R04_0_Pos)                            /*!< LCD PAL4: R04_0 Mask                */
-#define LCD_PAL4_G04_0_Pos                                    5                                                         /*!< LCD PAL4: G04_0 Position            */
-#define LCD_PAL4_G04_0_Msk                                    (0x1fUL << LCD_PAL4_G04_0_Pos)                            /*!< LCD PAL4: G04_0 Mask                */
-#define LCD_PAL4_B04_0_Pos                                    10                                                        /*!< LCD PAL4: B04_0 Position            */
-#define LCD_PAL4_B04_0_Msk                                    (0x1fUL << LCD_PAL4_B04_0_Pos)                            /*!< LCD PAL4: B04_0 Mask                */
-#define LCD_PAL4_I0_Pos                                       15                                                        /*!< LCD PAL4: I0 Position               */
-#define LCD_PAL4_I0_Msk                                       (0x01UL << LCD_PAL4_I0_Pos)                               /*!< LCD PAL4: I0 Mask                   */
-#define LCD_PAL4_R14_0_Pos                                    16                                                        /*!< LCD PAL4: R14_0 Position            */
-#define LCD_PAL4_R14_0_Msk                                    (0x1fUL << LCD_PAL4_R14_0_Pos)                            /*!< LCD PAL4: R14_0 Mask                */
-#define LCD_PAL4_G14_0_Pos                                    21                                                        /*!< LCD PAL4: G14_0 Position            */
-#define LCD_PAL4_G14_0_Msk                                    (0x1fUL << LCD_PAL4_G14_0_Pos)                            /*!< LCD PAL4: G14_0 Mask                */
-#define LCD_PAL4_B14_0_Pos                                    26                                                        /*!< LCD PAL4: B14_0 Position            */
-#define LCD_PAL4_B14_0_Msk                                    (0x1fUL << LCD_PAL4_B14_0_Pos)                            /*!< LCD PAL4: B14_0 Mask                */
-#define LCD_PAL4_I1_Pos                                       31                                                        /*!< LCD PAL4: I1 Position               */
-#define LCD_PAL4_I1_Msk                                       (0x01UL << LCD_PAL4_I1_Pos)                               /*!< LCD PAL4: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL5  --------------------------------------------
-#define LCD_PAL5_R04_0_Pos                                    0                                                         /*!< LCD PAL5: R04_0 Position            */
-#define LCD_PAL5_R04_0_Msk                                    (0x1fUL << LCD_PAL5_R04_0_Pos)                            /*!< LCD PAL5: R04_0 Mask                */
-#define LCD_PAL5_G04_0_Pos                                    5                                                         /*!< LCD PAL5: G04_0 Position            */
-#define LCD_PAL5_G04_0_Msk                                    (0x1fUL << LCD_PAL5_G04_0_Pos)                            /*!< LCD PAL5: G04_0 Mask                */
-#define LCD_PAL5_B04_0_Pos                                    10                                                        /*!< LCD PAL5: B04_0 Position            */
-#define LCD_PAL5_B04_0_Msk                                    (0x1fUL << LCD_PAL5_B04_0_Pos)                            /*!< LCD PAL5: B04_0 Mask                */
-#define LCD_PAL5_I0_Pos                                       15                                                        /*!< LCD PAL5: I0 Position               */
-#define LCD_PAL5_I0_Msk                                       (0x01UL << LCD_PAL5_I0_Pos)                               /*!< LCD PAL5: I0 Mask                   */
-#define LCD_PAL5_R14_0_Pos                                    16                                                        /*!< LCD PAL5: R14_0 Position            */
-#define LCD_PAL5_R14_0_Msk                                    (0x1fUL << LCD_PAL5_R14_0_Pos)                            /*!< LCD PAL5: R14_0 Mask                */
-#define LCD_PAL5_G14_0_Pos                                    21                                                        /*!< LCD PAL5: G14_0 Position            */
-#define LCD_PAL5_G14_0_Msk                                    (0x1fUL << LCD_PAL5_G14_0_Pos)                            /*!< LCD PAL5: G14_0 Mask                */
-#define LCD_PAL5_B14_0_Pos                                    26                                                        /*!< LCD PAL5: B14_0 Position            */
-#define LCD_PAL5_B14_0_Msk                                    (0x1fUL << LCD_PAL5_B14_0_Pos)                            /*!< LCD PAL5: B14_0 Mask                */
-#define LCD_PAL5_I1_Pos                                       31                                                        /*!< LCD PAL5: I1 Position               */
-#define LCD_PAL5_I1_Msk                                       (0x01UL << LCD_PAL5_I1_Pos)                               /*!< LCD PAL5: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL6  --------------------------------------------
-#define LCD_PAL6_R04_0_Pos                                    0                                                         /*!< LCD PAL6: R04_0 Position            */
-#define LCD_PAL6_R04_0_Msk                                    (0x1fUL << LCD_PAL6_R04_0_Pos)                            /*!< LCD PAL6: R04_0 Mask                */
-#define LCD_PAL6_G04_0_Pos                                    5                                                         /*!< LCD PAL6: G04_0 Position            */
-#define LCD_PAL6_G04_0_Msk                                    (0x1fUL << LCD_PAL6_G04_0_Pos)                            /*!< LCD PAL6: G04_0 Mask                */
-#define LCD_PAL6_B04_0_Pos                                    10                                                        /*!< LCD PAL6: B04_0 Position            */
-#define LCD_PAL6_B04_0_Msk                                    (0x1fUL << LCD_PAL6_B04_0_Pos)                            /*!< LCD PAL6: B04_0 Mask                */
-#define LCD_PAL6_I0_Pos                                       15                                                        /*!< LCD PAL6: I0 Position               */
-#define LCD_PAL6_I0_Msk                                       (0x01UL << LCD_PAL6_I0_Pos)                               /*!< LCD PAL6: I0 Mask                   */
-#define LCD_PAL6_R14_0_Pos                                    16                                                        /*!< LCD PAL6: R14_0 Position            */
-#define LCD_PAL6_R14_0_Msk                                    (0x1fUL << LCD_PAL6_R14_0_Pos)                            /*!< LCD PAL6: R14_0 Mask                */
-#define LCD_PAL6_G14_0_Pos                                    21                                                        /*!< LCD PAL6: G14_0 Position            */
-#define LCD_PAL6_G14_0_Msk                                    (0x1fUL << LCD_PAL6_G14_0_Pos)                            /*!< LCD PAL6: G14_0 Mask                */
-#define LCD_PAL6_B14_0_Pos                                    26                                                        /*!< LCD PAL6: B14_0 Position            */
-#define LCD_PAL6_B14_0_Msk                                    (0x1fUL << LCD_PAL6_B14_0_Pos)                            /*!< LCD PAL6: B14_0 Mask                */
-#define LCD_PAL6_I1_Pos                                       31                                                        /*!< LCD PAL6: I1 Position               */
-#define LCD_PAL6_I1_Msk                                       (0x01UL << LCD_PAL6_I1_Pos)                               /*!< LCD PAL6: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL7  --------------------------------------------
-#define LCD_PAL7_R04_0_Pos                                    0                                                         /*!< LCD PAL7: R04_0 Position            */
-#define LCD_PAL7_R04_0_Msk                                    (0x1fUL << LCD_PAL7_R04_0_Pos)                            /*!< LCD PAL7: R04_0 Mask                */
-#define LCD_PAL7_G04_0_Pos                                    5                                                         /*!< LCD PAL7: G04_0 Position            */
-#define LCD_PAL7_G04_0_Msk                                    (0x1fUL << LCD_PAL7_G04_0_Pos)                            /*!< LCD PAL7: G04_0 Mask                */
-#define LCD_PAL7_B04_0_Pos                                    10                                                        /*!< LCD PAL7: B04_0 Position            */
-#define LCD_PAL7_B04_0_Msk                                    (0x1fUL << LCD_PAL7_B04_0_Pos)                            /*!< LCD PAL7: B04_0 Mask                */
-#define LCD_PAL7_I0_Pos                                       15                                                        /*!< LCD PAL7: I0 Position               */
-#define LCD_PAL7_I0_Msk                                       (0x01UL << LCD_PAL7_I0_Pos)                               /*!< LCD PAL7: I0 Mask                   */
-#define LCD_PAL7_R14_0_Pos                                    16                                                        /*!< LCD PAL7: R14_0 Position            */
-#define LCD_PAL7_R14_0_Msk                                    (0x1fUL << LCD_PAL7_R14_0_Pos)                            /*!< LCD PAL7: R14_0 Mask                */
-#define LCD_PAL7_G14_0_Pos                                    21                                                        /*!< LCD PAL7: G14_0 Position            */
-#define LCD_PAL7_G14_0_Msk                                    (0x1fUL << LCD_PAL7_G14_0_Pos)                            /*!< LCD PAL7: G14_0 Mask                */
-#define LCD_PAL7_B14_0_Pos                                    26                                                        /*!< LCD PAL7: B14_0 Position            */
-#define LCD_PAL7_B14_0_Msk                                    (0x1fUL << LCD_PAL7_B14_0_Pos)                            /*!< LCD PAL7: B14_0 Mask                */
-#define LCD_PAL7_I1_Pos                                       31                                                        /*!< LCD PAL7: I1 Position               */
-#define LCD_PAL7_I1_Msk                                       (0x01UL << LCD_PAL7_I1_Pos)                               /*!< LCD PAL7: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL8  --------------------------------------------
-#define LCD_PAL8_R04_0_Pos                                    0                                                         /*!< LCD PAL8: R04_0 Position            */
-#define LCD_PAL8_R04_0_Msk                                    (0x1fUL << LCD_PAL8_R04_0_Pos)                            /*!< LCD PAL8: R04_0 Mask                */
-#define LCD_PAL8_G04_0_Pos                                    5                                                         /*!< LCD PAL8: G04_0 Position            */
-#define LCD_PAL8_G04_0_Msk                                    (0x1fUL << LCD_PAL8_G04_0_Pos)                            /*!< LCD PAL8: G04_0 Mask                */
-#define LCD_PAL8_B04_0_Pos                                    10                                                        /*!< LCD PAL8: B04_0 Position            */
-#define LCD_PAL8_B04_0_Msk                                    (0x1fUL << LCD_PAL8_B04_0_Pos)                            /*!< LCD PAL8: B04_0 Mask                */
-#define LCD_PAL8_I0_Pos                                       15                                                        /*!< LCD PAL8: I0 Position               */
-#define LCD_PAL8_I0_Msk                                       (0x01UL << LCD_PAL8_I0_Pos)                               /*!< LCD PAL8: I0 Mask                   */
-#define LCD_PAL8_R14_0_Pos                                    16                                                        /*!< LCD PAL8: R14_0 Position            */
-#define LCD_PAL8_R14_0_Msk                                    (0x1fUL << LCD_PAL8_R14_0_Pos)                            /*!< LCD PAL8: R14_0 Mask                */
-#define LCD_PAL8_G14_0_Pos                                    21                                                        /*!< LCD PAL8: G14_0 Position            */
-#define LCD_PAL8_G14_0_Msk                                    (0x1fUL << LCD_PAL8_G14_0_Pos)                            /*!< LCD PAL8: G14_0 Mask                */
-#define LCD_PAL8_B14_0_Pos                                    26                                                        /*!< LCD PAL8: B14_0 Position            */
-#define LCD_PAL8_B14_0_Msk                                    (0x1fUL << LCD_PAL8_B14_0_Pos)                            /*!< LCD PAL8: B14_0 Mask                */
-#define LCD_PAL8_I1_Pos                                       31                                                        /*!< LCD PAL8: I1 Position               */
-#define LCD_PAL8_I1_Msk                                       (0x01UL << LCD_PAL8_I1_Pos)                               /*!< LCD PAL8: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL9  --------------------------------------------
-#define LCD_PAL9_R04_0_Pos                                    0                                                         /*!< LCD PAL9: R04_0 Position            */
-#define LCD_PAL9_R04_0_Msk                                    (0x1fUL << LCD_PAL9_R04_0_Pos)                            /*!< LCD PAL9: R04_0 Mask                */
-#define LCD_PAL9_G04_0_Pos                                    5                                                         /*!< LCD PAL9: G04_0 Position            */
-#define LCD_PAL9_G04_0_Msk                                    (0x1fUL << LCD_PAL9_G04_0_Pos)                            /*!< LCD PAL9: G04_0 Mask                */
-#define LCD_PAL9_B04_0_Pos                                    10                                                        /*!< LCD PAL9: B04_0 Position            */
-#define LCD_PAL9_B04_0_Msk                                    (0x1fUL << LCD_PAL9_B04_0_Pos)                            /*!< LCD PAL9: B04_0 Mask                */
-#define LCD_PAL9_I0_Pos                                       15                                                        /*!< LCD PAL9: I0 Position               */
-#define LCD_PAL9_I0_Msk                                       (0x01UL << LCD_PAL9_I0_Pos)                               /*!< LCD PAL9: I0 Mask                   */
-#define LCD_PAL9_R14_0_Pos                                    16                                                        /*!< LCD PAL9: R14_0 Position            */
-#define LCD_PAL9_R14_0_Msk                                    (0x1fUL << LCD_PAL9_R14_0_Pos)                            /*!< LCD PAL9: R14_0 Mask                */
-#define LCD_PAL9_G14_0_Pos                                    21                                                        /*!< LCD PAL9: G14_0 Position            */
-#define LCD_PAL9_G14_0_Msk                                    (0x1fUL << LCD_PAL9_G14_0_Pos)                            /*!< LCD PAL9: G14_0 Mask                */
-#define LCD_PAL9_B14_0_Pos                                    26                                                        /*!< LCD PAL9: B14_0 Position            */
-#define LCD_PAL9_B14_0_Msk                                    (0x1fUL << LCD_PAL9_B14_0_Pos)                            /*!< LCD PAL9: B14_0 Mask                */
-#define LCD_PAL9_I1_Pos                                       31                                                        /*!< LCD PAL9: I1 Position               */
-#define LCD_PAL9_I1_Msk                                       (0x01UL << LCD_PAL9_I1_Pos)                               /*!< LCD PAL9: I1 Mask                   */
-
-// ----------------------------------------  LCD_PAL10  -------------------------------------------
-#define LCD_PAL10_R04_0_Pos                                   0                                                         /*!< LCD PAL10: R04_0 Position           */
-#define LCD_PAL10_R04_0_Msk                                   (0x1fUL << LCD_PAL10_R04_0_Pos)                           /*!< LCD PAL10: R04_0 Mask               */
-#define LCD_PAL10_G04_0_Pos                                   5                                                         /*!< LCD PAL10: G04_0 Position           */
-#define LCD_PAL10_G04_0_Msk                                   (0x1fUL << LCD_PAL10_G04_0_Pos)                           /*!< LCD PAL10: G04_0 Mask               */
-#define LCD_PAL10_B04_0_Pos                                   10                                                        /*!< LCD PAL10: B04_0 Position           */
-#define LCD_PAL10_B04_0_Msk                                   (0x1fUL << LCD_PAL10_B04_0_Pos)                           /*!< LCD PAL10: B04_0 Mask               */
-#define LCD_PAL10_I0_Pos                                      15                                                        /*!< LCD PAL10: I0 Position              */
-#define LCD_PAL10_I0_Msk                                      (0x01UL << LCD_PAL10_I0_Pos)                              /*!< LCD PAL10: I0 Mask                  */
-#define LCD_PAL10_R14_0_Pos                                   16                                                        /*!< LCD PAL10: R14_0 Position           */
-#define LCD_PAL10_R14_0_Msk                                   (0x1fUL << LCD_PAL10_R14_0_Pos)                           /*!< LCD PAL10: R14_0 Mask               */
-#define LCD_PAL10_G14_0_Pos                                   21                                                        /*!< LCD PAL10: G14_0 Position           */
-#define LCD_PAL10_G14_0_Msk                                   (0x1fUL << LCD_PAL10_G14_0_Pos)                           /*!< LCD PAL10: G14_0 Mask               */
-#define LCD_PAL10_B14_0_Pos                                   26                                                        /*!< LCD PAL10: B14_0 Position           */
-#define LCD_PAL10_B14_0_Msk                                   (0x1fUL << LCD_PAL10_B14_0_Pos)                           /*!< LCD PAL10: B14_0 Mask               */
-#define LCD_PAL10_I1_Pos                                      31                                                        /*!< LCD PAL10: I1 Position              */
-#define LCD_PAL10_I1_Msk                                      (0x01UL << LCD_PAL10_I1_Pos)                              /*!< LCD PAL10: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL11  -------------------------------------------
-#define LCD_PAL11_R04_0_Pos                                   0                                                         /*!< LCD PAL11: R04_0 Position           */
-#define LCD_PAL11_R04_0_Msk                                   (0x1fUL << LCD_PAL11_R04_0_Pos)                           /*!< LCD PAL11: R04_0 Mask               */
-#define LCD_PAL11_G04_0_Pos                                   5                                                         /*!< LCD PAL11: G04_0 Position           */
-#define LCD_PAL11_G04_0_Msk                                   (0x1fUL << LCD_PAL11_G04_0_Pos)                           /*!< LCD PAL11: G04_0 Mask               */
-#define LCD_PAL11_B04_0_Pos                                   10                                                        /*!< LCD PAL11: B04_0 Position           */
-#define LCD_PAL11_B04_0_Msk                                   (0x1fUL << LCD_PAL11_B04_0_Pos)                           /*!< LCD PAL11: B04_0 Mask               */
-#define LCD_PAL11_I0_Pos                                      15                                                        /*!< LCD PAL11: I0 Position              */
-#define LCD_PAL11_I0_Msk                                      (0x01UL << LCD_PAL11_I0_Pos)                              /*!< LCD PAL11: I0 Mask                  */
-#define LCD_PAL11_R14_0_Pos                                   16                                                        /*!< LCD PAL11: R14_0 Position           */
-#define LCD_PAL11_R14_0_Msk                                   (0x1fUL << LCD_PAL11_R14_0_Pos)                           /*!< LCD PAL11: R14_0 Mask               */
-#define LCD_PAL11_G14_0_Pos                                   21                                                        /*!< LCD PAL11: G14_0 Position           */
-#define LCD_PAL11_G14_0_Msk                                   (0x1fUL << LCD_PAL11_G14_0_Pos)                           /*!< LCD PAL11: G14_0 Mask               */
-#define LCD_PAL11_B14_0_Pos                                   26                                                        /*!< LCD PAL11: B14_0 Position           */
-#define LCD_PAL11_B14_0_Msk                                   (0x1fUL << LCD_PAL11_B14_0_Pos)                           /*!< LCD PAL11: B14_0 Mask               */
-#define LCD_PAL11_I1_Pos                                      31                                                        /*!< LCD PAL11: I1 Position              */
-#define LCD_PAL11_I1_Msk                                      (0x01UL << LCD_PAL11_I1_Pos)                              /*!< LCD PAL11: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL12  -------------------------------------------
-#define LCD_PAL12_R04_0_Pos                                   0                                                         /*!< LCD PAL12: R04_0 Position           */
-#define LCD_PAL12_R04_0_Msk                                   (0x1fUL << LCD_PAL12_R04_0_Pos)                           /*!< LCD PAL12: R04_0 Mask               */
-#define LCD_PAL12_G04_0_Pos                                   5                                                         /*!< LCD PAL12: G04_0 Position           */
-#define LCD_PAL12_G04_0_Msk                                   (0x1fUL << LCD_PAL12_G04_0_Pos)                           /*!< LCD PAL12: G04_0 Mask               */
-#define LCD_PAL12_B04_0_Pos                                   10                                                        /*!< LCD PAL12: B04_0 Position           */
-#define LCD_PAL12_B04_0_Msk                                   (0x1fUL << LCD_PAL12_B04_0_Pos)                           /*!< LCD PAL12: B04_0 Mask               */
-#define LCD_PAL12_I0_Pos                                      15                                                        /*!< LCD PAL12: I0 Position              */
-#define LCD_PAL12_I0_Msk                                      (0x01UL << LCD_PAL12_I0_Pos)                              /*!< LCD PAL12: I0 Mask                  */
-#define LCD_PAL12_R14_0_Pos                                   16                                                        /*!< LCD PAL12: R14_0 Position           */
-#define LCD_PAL12_R14_0_Msk                                   (0x1fUL << LCD_PAL12_R14_0_Pos)                           /*!< LCD PAL12: R14_0 Mask               */
-#define LCD_PAL12_G14_0_Pos                                   21                                                        /*!< LCD PAL12: G14_0 Position           */
-#define LCD_PAL12_G14_0_Msk                                   (0x1fUL << LCD_PAL12_G14_0_Pos)                           /*!< LCD PAL12: G14_0 Mask               */
-#define LCD_PAL12_B14_0_Pos                                   26                                                        /*!< LCD PAL12: B14_0 Position           */
-#define LCD_PAL12_B14_0_Msk                                   (0x1fUL << LCD_PAL12_B14_0_Pos)                           /*!< LCD PAL12: B14_0 Mask               */
-#define LCD_PAL12_I1_Pos                                      31                                                        /*!< LCD PAL12: I1 Position              */
-#define LCD_PAL12_I1_Msk                                      (0x01UL << LCD_PAL12_I1_Pos)                              /*!< LCD PAL12: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL13  -------------------------------------------
-#define LCD_PAL13_R04_0_Pos                                   0                                                         /*!< LCD PAL13: R04_0 Position           */
-#define LCD_PAL13_R04_0_Msk                                   (0x1fUL << LCD_PAL13_R04_0_Pos)                           /*!< LCD PAL13: R04_0 Mask               */
-#define LCD_PAL13_G04_0_Pos                                   5                                                         /*!< LCD PAL13: G04_0 Position           */
-#define LCD_PAL13_G04_0_Msk                                   (0x1fUL << LCD_PAL13_G04_0_Pos)                           /*!< LCD PAL13: G04_0 Mask               */
-#define LCD_PAL13_B04_0_Pos                                   10                                                        /*!< LCD PAL13: B04_0 Position           */
-#define LCD_PAL13_B04_0_Msk                                   (0x1fUL << LCD_PAL13_B04_0_Pos)                           /*!< LCD PAL13: B04_0 Mask               */
-#define LCD_PAL13_I0_Pos                                      15                                                        /*!< LCD PAL13: I0 Position              */
-#define LCD_PAL13_I0_Msk                                      (0x01UL << LCD_PAL13_I0_Pos)                              /*!< LCD PAL13: I0 Mask                  */
-#define LCD_PAL13_R14_0_Pos                                   16                                                        /*!< LCD PAL13: R14_0 Position           */
-#define LCD_PAL13_R14_0_Msk                                   (0x1fUL << LCD_PAL13_R14_0_Pos)                           /*!< LCD PAL13: R14_0 Mask               */
-#define LCD_PAL13_G14_0_Pos                                   21                                                        /*!< LCD PAL13: G14_0 Position           */
-#define LCD_PAL13_G14_0_Msk                                   (0x1fUL << LCD_PAL13_G14_0_Pos)                           /*!< LCD PAL13: G14_0 Mask               */
-#define LCD_PAL13_B14_0_Pos                                   26                                                        /*!< LCD PAL13: B14_0 Position           */
-#define LCD_PAL13_B14_0_Msk                                   (0x1fUL << LCD_PAL13_B14_0_Pos)                           /*!< LCD PAL13: B14_0 Mask               */
-#define LCD_PAL13_I1_Pos                                      31                                                        /*!< LCD PAL13: I1 Position              */
-#define LCD_PAL13_I1_Msk                                      (0x01UL << LCD_PAL13_I1_Pos)                              /*!< LCD PAL13: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL14  -------------------------------------------
-#define LCD_PAL14_R04_0_Pos                                   0                                                         /*!< LCD PAL14: R04_0 Position           */
-#define LCD_PAL14_R04_0_Msk                                   (0x1fUL << LCD_PAL14_R04_0_Pos)                           /*!< LCD PAL14: R04_0 Mask               */
-#define LCD_PAL14_G04_0_Pos                                   5                                                         /*!< LCD PAL14: G04_0 Position           */
-#define LCD_PAL14_G04_0_Msk                                   (0x1fUL << LCD_PAL14_G04_0_Pos)                           /*!< LCD PAL14: G04_0 Mask               */
-#define LCD_PAL14_B04_0_Pos                                   10                                                        /*!< LCD PAL14: B04_0 Position           */
-#define LCD_PAL14_B04_0_Msk                                   (0x1fUL << LCD_PAL14_B04_0_Pos)                           /*!< LCD PAL14: B04_0 Mask               */
-#define LCD_PAL14_I0_Pos                                      15                                                        /*!< LCD PAL14: I0 Position              */
-#define LCD_PAL14_I0_Msk                                      (0x01UL << LCD_PAL14_I0_Pos)                              /*!< LCD PAL14: I0 Mask                  */
-#define LCD_PAL14_R14_0_Pos                                   16                                                        /*!< LCD PAL14: R14_0 Position           */
-#define LCD_PAL14_R14_0_Msk                                   (0x1fUL << LCD_PAL14_R14_0_Pos)                           /*!< LCD PAL14: R14_0 Mask               */
-#define LCD_PAL14_G14_0_Pos                                   21                                                        /*!< LCD PAL14: G14_0 Position           */
-#define LCD_PAL14_G14_0_Msk                                   (0x1fUL << LCD_PAL14_G14_0_Pos)                           /*!< LCD PAL14: G14_0 Mask               */
-#define LCD_PAL14_B14_0_Pos                                   26                                                        /*!< LCD PAL14: B14_0 Position           */
-#define LCD_PAL14_B14_0_Msk                                   (0x1fUL << LCD_PAL14_B14_0_Pos)                           /*!< LCD PAL14: B14_0 Mask               */
-#define LCD_PAL14_I1_Pos                                      31                                                        /*!< LCD PAL14: I1 Position              */
-#define LCD_PAL14_I1_Msk                                      (0x01UL << LCD_PAL14_I1_Pos)                              /*!< LCD PAL14: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL15  -------------------------------------------
-#define LCD_PAL15_R04_0_Pos                                   0                                                         /*!< LCD PAL15: R04_0 Position           */
-#define LCD_PAL15_R04_0_Msk                                   (0x1fUL << LCD_PAL15_R04_0_Pos)                           /*!< LCD PAL15: R04_0 Mask               */
-#define LCD_PAL15_G04_0_Pos                                   5                                                         /*!< LCD PAL15: G04_0 Position           */
-#define LCD_PAL15_G04_0_Msk                                   (0x1fUL << LCD_PAL15_G04_0_Pos)                           /*!< LCD PAL15: G04_0 Mask               */
-#define LCD_PAL15_B04_0_Pos                                   10                                                        /*!< LCD PAL15: B04_0 Position           */
-#define LCD_PAL15_B04_0_Msk                                   (0x1fUL << LCD_PAL15_B04_0_Pos)                           /*!< LCD PAL15: B04_0 Mask               */
-#define LCD_PAL15_I0_Pos                                      15                                                        /*!< LCD PAL15: I0 Position              */
-#define LCD_PAL15_I0_Msk                                      (0x01UL << LCD_PAL15_I0_Pos)                              /*!< LCD PAL15: I0 Mask                  */
-#define LCD_PAL15_R14_0_Pos                                   16                                                        /*!< LCD PAL15: R14_0 Position           */
-#define LCD_PAL15_R14_0_Msk                                   (0x1fUL << LCD_PAL15_R14_0_Pos)                           /*!< LCD PAL15: R14_0 Mask               */
-#define LCD_PAL15_G14_0_Pos                                   21                                                        /*!< LCD PAL15: G14_0 Position           */
-#define LCD_PAL15_G14_0_Msk                                   (0x1fUL << LCD_PAL15_G14_0_Pos)                           /*!< LCD PAL15: G14_0 Mask               */
-#define LCD_PAL15_B14_0_Pos                                   26                                                        /*!< LCD PAL15: B14_0 Position           */
-#define LCD_PAL15_B14_0_Msk                                   (0x1fUL << LCD_PAL15_B14_0_Pos)                           /*!< LCD PAL15: B14_0 Mask               */
-#define LCD_PAL15_I1_Pos                                      31                                                        /*!< LCD PAL15: I1 Position              */
-#define LCD_PAL15_I1_Msk                                      (0x01UL << LCD_PAL15_I1_Pos)                              /*!< LCD PAL15: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL16  -------------------------------------------
-#define LCD_PAL16_R04_0_Pos                                   0                                                         /*!< LCD PAL16: R04_0 Position           */
-#define LCD_PAL16_R04_0_Msk                                   (0x1fUL << LCD_PAL16_R04_0_Pos)                           /*!< LCD PAL16: R04_0 Mask               */
-#define LCD_PAL16_G04_0_Pos                                   5                                                         /*!< LCD PAL16: G04_0 Position           */
-#define LCD_PAL16_G04_0_Msk                                   (0x1fUL << LCD_PAL16_G04_0_Pos)                           /*!< LCD PAL16: G04_0 Mask               */
-#define LCD_PAL16_B04_0_Pos                                   10                                                        /*!< LCD PAL16: B04_0 Position           */
-#define LCD_PAL16_B04_0_Msk                                   (0x1fUL << LCD_PAL16_B04_0_Pos)                           /*!< LCD PAL16: B04_0 Mask               */
-#define LCD_PAL16_I0_Pos                                      15                                                        /*!< LCD PAL16: I0 Position              */
-#define LCD_PAL16_I0_Msk                                      (0x01UL << LCD_PAL16_I0_Pos)                              /*!< LCD PAL16: I0 Mask                  */
-#define LCD_PAL16_R14_0_Pos                                   16                                                        /*!< LCD PAL16: R14_0 Position           */
-#define LCD_PAL16_R14_0_Msk                                   (0x1fUL << LCD_PAL16_R14_0_Pos)                           /*!< LCD PAL16: R14_0 Mask               */
-#define LCD_PAL16_G14_0_Pos                                   21                                                        /*!< LCD PAL16: G14_0 Position           */
-#define LCD_PAL16_G14_0_Msk                                   (0x1fUL << LCD_PAL16_G14_0_Pos)                           /*!< LCD PAL16: G14_0 Mask               */
-#define LCD_PAL16_B14_0_Pos                                   26                                                        /*!< LCD PAL16: B14_0 Position           */
-#define LCD_PAL16_B14_0_Msk                                   (0x1fUL << LCD_PAL16_B14_0_Pos)                           /*!< LCD PAL16: B14_0 Mask               */
-#define LCD_PAL16_I1_Pos                                      31                                                        /*!< LCD PAL16: I1 Position              */
-#define LCD_PAL16_I1_Msk                                      (0x01UL << LCD_PAL16_I1_Pos)                              /*!< LCD PAL16: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL17  -------------------------------------------
-#define LCD_PAL17_R04_0_Pos                                   0                                                         /*!< LCD PAL17: R04_0 Position           */
-#define LCD_PAL17_R04_0_Msk                                   (0x1fUL << LCD_PAL17_R04_0_Pos)                           /*!< LCD PAL17: R04_0 Mask               */
-#define LCD_PAL17_G04_0_Pos                                   5                                                         /*!< LCD PAL17: G04_0 Position           */
-#define LCD_PAL17_G04_0_Msk                                   (0x1fUL << LCD_PAL17_G04_0_Pos)                           /*!< LCD PAL17: G04_0 Mask               */
-#define LCD_PAL17_B04_0_Pos                                   10                                                        /*!< LCD PAL17: B04_0 Position           */
-#define LCD_PAL17_B04_0_Msk                                   (0x1fUL << LCD_PAL17_B04_0_Pos)                           /*!< LCD PAL17: B04_0 Mask               */
-#define LCD_PAL17_I0_Pos                                      15                                                        /*!< LCD PAL17: I0 Position              */
-#define LCD_PAL17_I0_Msk                                      (0x01UL << LCD_PAL17_I0_Pos)                              /*!< LCD PAL17: I0 Mask                  */
-#define LCD_PAL17_R14_0_Pos                                   16                                                        /*!< LCD PAL17: R14_0 Position           */
-#define LCD_PAL17_R14_0_Msk                                   (0x1fUL << LCD_PAL17_R14_0_Pos)                           /*!< LCD PAL17: R14_0 Mask               */
-#define LCD_PAL17_G14_0_Pos                                   21                                                        /*!< LCD PAL17: G14_0 Position           */
-#define LCD_PAL17_G14_0_Msk                                   (0x1fUL << LCD_PAL17_G14_0_Pos)                           /*!< LCD PAL17: G14_0 Mask               */
-#define LCD_PAL17_B14_0_Pos                                   26                                                        /*!< LCD PAL17: B14_0 Position           */
-#define LCD_PAL17_B14_0_Msk                                   (0x1fUL << LCD_PAL17_B14_0_Pos)                           /*!< LCD PAL17: B14_0 Mask               */
-#define LCD_PAL17_I1_Pos                                      31                                                        /*!< LCD PAL17: I1 Position              */
-#define LCD_PAL17_I1_Msk                                      (0x01UL << LCD_PAL17_I1_Pos)                              /*!< LCD PAL17: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL18  -------------------------------------------
-#define LCD_PAL18_R04_0_Pos                                   0                                                         /*!< LCD PAL18: R04_0 Position           */
-#define LCD_PAL18_R04_0_Msk                                   (0x1fUL << LCD_PAL18_R04_0_Pos)                           /*!< LCD PAL18: R04_0 Mask               */
-#define LCD_PAL18_G04_0_Pos                                   5                                                         /*!< LCD PAL18: G04_0 Position           */
-#define LCD_PAL18_G04_0_Msk                                   (0x1fUL << LCD_PAL18_G04_0_Pos)                           /*!< LCD PAL18: G04_0 Mask               */
-#define LCD_PAL18_B04_0_Pos                                   10                                                        /*!< LCD PAL18: B04_0 Position           */
-#define LCD_PAL18_B04_0_Msk                                   (0x1fUL << LCD_PAL18_B04_0_Pos)                           /*!< LCD PAL18: B04_0 Mask               */
-#define LCD_PAL18_I0_Pos                                      15                                                        /*!< LCD PAL18: I0 Position              */
-#define LCD_PAL18_I0_Msk                                      (0x01UL << LCD_PAL18_I0_Pos)                              /*!< LCD PAL18: I0 Mask                  */
-#define LCD_PAL18_R14_0_Pos                                   16                                                        /*!< LCD PAL18: R14_0 Position           */
-#define LCD_PAL18_R14_0_Msk                                   (0x1fUL << LCD_PAL18_R14_0_Pos)                           /*!< LCD PAL18: R14_0 Mask               */
-#define LCD_PAL18_G14_0_Pos                                   21                                                        /*!< LCD PAL18: G14_0 Position           */
-#define LCD_PAL18_G14_0_Msk                                   (0x1fUL << LCD_PAL18_G14_0_Pos)                           /*!< LCD PAL18: G14_0 Mask               */
-#define LCD_PAL18_B14_0_Pos                                   26                                                        /*!< LCD PAL18: B14_0 Position           */
-#define LCD_PAL18_B14_0_Msk                                   (0x1fUL << LCD_PAL18_B14_0_Pos)                           /*!< LCD PAL18: B14_0 Mask               */
-#define LCD_PAL18_I1_Pos                                      31                                                        /*!< LCD PAL18: I1 Position              */
-#define LCD_PAL18_I1_Msk                                      (0x01UL << LCD_PAL18_I1_Pos)                              /*!< LCD PAL18: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL19  -------------------------------------------
-#define LCD_PAL19_R04_0_Pos                                   0                                                         /*!< LCD PAL19: R04_0 Position           */
-#define LCD_PAL19_R04_0_Msk                                   (0x1fUL << LCD_PAL19_R04_0_Pos)                           /*!< LCD PAL19: R04_0 Mask               */
-#define LCD_PAL19_G04_0_Pos                                   5                                                         /*!< LCD PAL19: G04_0 Position           */
-#define LCD_PAL19_G04_0_Msk                                   (0x1fUL << LCD_PAL19_G04_0_Pos)                           /*!< LCD PAL19: G04_0 Mask               */
-#define LCD_PAL19_B04_0_Pos                                   10                                                        /*!< LCD PAL19: B04_0 Position           */
-#define LCD_PAL19_B04_0_Msk                                   (0x1fUL << LCD_PAL19_B04_0_Pos)                           /*!< LCD PAL19: B04_0 Mask               */
-#define LCD_PAL19_I0_Pos                                      15                                                        /*!< LCD PAL19: I0 Position              */
-#define LCD_PAL19_I0_Msk                                      (0x01UL << LCD_PAL19_I0_Pos)                              /*!< LCD PAL19: I0 Mask                  */
-#define LCD_PAL19_R14_0_Pos                                   16                                                        /*!< LCD PAL19: R14_0 Position           */
-#define LCD_PAL19_R14_0_Msk                                   (0x1fUL << LCD_PAL19_R14_0_Pos)                           /*!< LCD PAL19: R14_0 Mask               */
-#define LCD_PAL19_G14_0_Pos                                   21                                                        /*!< LCD PAL19: G14_0 Position           */
-#define LCD_PAL19_G14_0_Msk                                   (0x1fUL << LCD_PAL19_G14_0_Pos)                           /*!< LCD PAL19: G14_0 Mask               */
-#define LCD_PAL19_B14_0_Pos                                   26                                                        /*!< LCD PAL19: B14_0 Position           */
-#define LCD_PAL19_B14_0_Msk                                   (0x1fUL << LCD_PAL19_B14_0_Pos)                           /*!< LCD PAL19: B14_0 Mask               */
-#define LCD_PAL19_I1_Pos                                      31                                                        /*!< LCD PAL19: I1 Position              */
-#define LCD_PAL19_I1_Msk                                      (0x01UL << LCD_PAL19_I1_Pos)                              /*!< LCD PAL19: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL20  -------------------------------------------
-#define LCD_PAL20_R04_0_Pos                                   0                                                         /*!< LCD PAL20: R04_0 Position           */
-#define LCD_PAL20_R04_0_Msk                                   (0x1fUL << LCD_PAL20_R04_0_Pos)                           /*!< LCD PAL20: R04_0 Mask               */
-#define LCD_PAL20_G04_0_Pos                                   5                                                         /*!< LCD PAL20: G04_0 Position           */
-#define LCD_PAL20_G04_0_Msk                                   (0x1fUL << LCD_PAL20_G04_0_Pos)                           /*!< LCD PAL20: G04_0 Mask               */
-#define LCD_PAL20_B04_0_Pos                                   10                                                        /*!< LCD PAL20: B04_0 Position           */
-#define LCD_PAL20_B04_0_Msk                                   (0x1fUL << LCD_PAL20_B04_0_Pos)                           /*!< LCD PAL20: B04_0 Mask               */
-#define LCD_PAL20_I0_Pos                                      15                                                        /*!< LCD PAL20: I0 Position              */
-#define LCD_PAL20_I0_Msk                                      (0x01UL << LCD_PAL20_I0_Pos)                              /*!< LCD PAL20: I0 Mask                  */
-#define LCD_PAL20_R14_0_Pos                                   16                                                        /*!< LCD PAL20: R14_0 Position           */
-#define LCD_PAL20_R14_0_Msk                                   (0x1fUL << LCD_PAL20_R14_0_Pos)                           /*!< LCD PAL20: R14_0 Mask               */
-#define LCD_PAL20_G14_0_Pos                                   21                                                        /*!< LCD PAL20: G14_0 Position           */
-#define LCD_PAL20_G14_0_Msk                                   (0x1fUL << LCD_PAL20_G14_0_Pos)                           /*!< LCD PAL20: G14_0 Mask               */
-#define LCD_PAL20_B14_0_Pos                                   26                                                        /*!< LCD PAL20: B14_0 Position           */
-#define LCD_PAL20_B14_0_Msk                                   (0x1fUL << LCD_PAL20_B14_0_Pos)                           /*!< LCD PAL20: B14_0 Mask               */
-#define LCD_PAL20_I1_Pos                                      31                                                        /*!< LCD PAL20: I1 Position              */
-#define LCD_PAL20_I1_Msk                                      (0x01UL << LCD_PAL20_I1_Pos)                              /*!< LCD PAL20: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL21  -------------------------------------------
-#define LCD_PAL21_R04_0_Pos                                   0                                                         /*!< LCD PAL21: R04_0 Position           */
-#define LCD_PAL21_R04_0_Msk                                   (0x1fUL << LCD_PAL21_R04_0_Pos)                           /*!< LCD PAL21: R04_0 Mask               */
-#define LCD_PAL21_G04_0_Pos                                   5                                                         /*!< LCD PAL21: G04_0 Position           */
-#define LCD_PAL21_G04_0_Msk                                   (0x1fUL << LCD_PAL21_G04_0_Pos)                           /*!< LCD PAL21: G04_0 Mask               */
-#define LCD_PAL21_B04_0_Pos                                   10                                                        /*!< LCD PAL21: B04_0 Position           */
-#define LCD_PAL21_B04_0_Msk                                   (0x1fUL << LCD_PAL21_B04_0_Pos)                           /*!< LCD PAL21: B04_0 Mask               */
-#define LCD_PAL21_I0_Pos                                      15                                                        /*!< LCD PAL21: I0 Position              */
-#define LCD_PAL21_I0_Msk                                      (0x01UL << LCD_PAL21_I0_Pos)                              /*!< LCD PAL21: I0 Mask                  */
-#define LCD_PAL21_R14_0_Pos                                   16                                                        /*!< LCD PAL21: R14_0 Position           */
-#define LCD_PAL21_R14_0_Msk                                   (0x1fUL << LCD_PAL21_R14_0_Pos)                           /*!< LCD PAL21: R14_0 Mask               */
-#define LCD_PAL21_G14_0_Pos                                   21                                                        /*!< LCD PAL21: G14_0 Position           */
-#define LCD_PAL21_G14_0_Msk                                   (0x1fUL << LCD_PAL21_G14_0_Pos)                           /*!< LCD PAL21: G14_0 Mask               */
-#define LCD_PAL21_B14_0_Pos                                   26                                                        /*!< LCD PAL21: B14_0 Position           */
-#define LCD_PAL21_B14_0_Msk                                   (0x1fUL << LCD_PAL21_B14_0_Pos)                           /*!< LCD PAL21: B14_0 Mask               */
-#define LCD_PAL21_I1_Pos                                      31                                                        /*!< LCD PAL21: I1 Position              */
-#define LCD_PAL21_I1_Msk                                      (0x01UL << LCD_PAL21_I1_Pos)                              /*!< LCD PAL21: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL22  -------------------------------------------
-#define LCD_PAL22_R04_0_Pos                                   0                                                         /*!< LCD PAL22: R04_0 Position           */
-#define LCD_PAL22_R04_0_Msk                                   (0x1fUL << LCD_PAL22_R04_0_Pos)                           /*!< LCD PAL22: R04_0 Mask               */
-#define LCD_PAL22_G04_0_Pos                                   5                                                         /*!< LCD PAL22: G04_0 Position           */
-#define LCD_PAL22_G04_0_Msk                                   (0x1fUL << LCD_PAL22_G04_0_Pos)                           /*!< LCD PAL22: G04_0 Mask               */
-#define LCD_PAL22_B04_0_Pos                                   10                                                        /*!< LCD PAL22: B04_0 Position           */
-#define LCD_PAL22_B04_0_Msk                                   (0x1fUL << LCD_PAL22_B04_0_Pos)                           /*!< LCD PAL22: B04_0 Mask               */
-#define LCD_PAL22_I0_Pos                                      15                                                        /*!< LCD PAL22: I0 Position              */
-#define LCD_PAL22_I0_Msk                                      (0x01UL << LCD_PAL22_I0_Pos)                              /*!< LCD PAL22: I0 Mask                  */
-#define LCD_PAL22_R14_0_Pos                                   16                                                        /*!< LCD PAL22: R14_0 Position           */
-#define LCD_PAL22_R14_0_Msk                                   (0x1fUL << LCD_PAL22_R14_0_Pos)                           /*!< LCD PAL22: R14_0 Mask               */
-#define LCD_PAL22_G14_0_Pos                                   21                                                        /*!< LCD PAL22: G14_0 Position           */
-#define LCD_PAL22_G14_0_Msk                                   (0x1fUL << LCD_PAL22_G14_0_Pos)                           /*!< LCD PAL22: G14_0 Mask               */
-#define LCD_PAL22_B14_0_Pos                                   26                                                        /*!< LCD PAL22: B14_0 Position           */
-#define LCD_PAL22_B14_0_Msk                                   (0x1fUL << LCD_PAL22_B14_0_Pos)                           /*!< LCD PAL22: B14_0 Mask               */
-#define LCD_PAL22_I1_Pos                                      31                                                        /*!< LCD PAL22: I1 Position              */
-#define LCD_PAL22_I1_Msk                                      (0x01UL << LCD_PAL22_I1_Pos)                              /*!< LCD PAL22: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL23  -------------------------------------------
-#define LCD_PAL23_R04_0_Pos                                   0                                                         /*!< LCD PAL23: R04_0 Position           */
-#define LCD_PAL23_R04_0_Msk                                   (0x1fUL << LCD_PAL23_R04_0_Pos)                           /*!< LCD PAL23: R04_0 Mask               */
-#define LCD_PAL23_G04_0_Pos                                   5                                                         /*!< LCD PAL23: G04_0 Position           */
-#define LCD_PAL23_G04_0_Msk                                   (0x1fUL << LCD_PAL23_G04_0_Pos)                           /*!< LCD PAL23: G04_0 Mask               */
-#define LCD_PAL23_B04_0_Pos                                   10                                                        /*!< LCD PAL23: B04_0 Position           */
-#define LCD_PAL23_B04_0_Msk                                   (0x1fUL << LCD_PAL23_B04_0_Pos)                           /*!< LCD PAL23: B04_0 Mask               */
-#define LCD_PAL23_I0_Pos                                      15                                                        /*!< LCD PAL23: I0 Position              */
-#define LCD_PAL23_I0_Msk                                      (0x01UL << LCD_PAL23_I0_Pos)                              /*!< LCD PAL23: I0 Mask                  */
-#define LCD_PAL23_R14_0_Pos                                   16                                                        /*!< LCD PAL23: R14_0 Position           */
-#define LCD_PAL23_R14_0_Msk                                   (0x1fUL << LCD_PAL23_R14_0_Pos)                           /*!< LCD PAL23: R14_0 Mask               */
-#define LCD_PAL23_G14_0_Pos                                   21                                                        /*!< LCD PAL23: G14_0 Position           */
-#define LCD_PAL23_G14_0_Msk                                   (0x1fUL << LCD_PAL23_G14_0_Pos)                           /*!< LCD PAL23: G14_0 Mask               */
-#define LCD_PAL23_B14_0_Pos                                   26                                                        /*!< LCD PAL23: B14_0 Position           */
-#define LCD_PAL23_B14_0_Msk                                   (0x1fUL << LCD_PAL23_B14_0_Pos)                           /*!< LCD PAL23: B14_0 Mask               */
-#define LCD_PAL23_I1_Pos                                      31                                                        /*!< LCD PAL23: I1 Position              */
-#define LCD_PAL23_I1_Msk                                      (0x01UL << LCD_PAL23_I1_Pos)                              /*!< LCD PAL23: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL24  -------------------------------------------
-#define LCD_PAL24_R04_0_Pos                                   0                                                         /*!< LCD PAL24: R04_0 Position           */
-#define LCD_PAL24_R04_0_Msk                                   (0x1fUL << LCD_PAL24_R04_0_Pos)                           /*!< LCD PAL24: R04_0 Mask               */
-#define LCD_PAL24_G04_0_Pos                                   5                                                         /*!< LCD PAL24: G04_0 Position           */
-#define LCD_PAL24_G04_0_Msk                                   (0x1fUL << LCD_PAL24_G04_0_Pos)                           /*!< LCD PAL24: G04_0 Mask               */
-#define LCD_PAL24_B04_0_Pos                                   10                                                        /*!< LCD PAL24: B04_0 Position           */
-#define LCD_PAL24_B04_0_Msk                                   (0x1fUL << LCD_PAL24_B04_0_Pos)                           /*!< LCD PAL24: B04_0 Mask               */
-#define LCD_PAL24_I0_Pos                                      15                                                        /*!< LCD PAL24: I0 Position              */
-#define LCD_PAL24_I0_Msk                                      (0x01UL << LCD_PAL24_I0_Pos)                              /*!< LCD PAL24: I0 Mask                  */
-#define LCD_PAL24_R14_0_Pos                                   16                                                        /*!< LCD PAL24: R14_0 Position           */
-#define LCD_PAL24_R14_0_Msk                                   (0x1fUL << LCD_PAL24_R14_0_Pos)                           /*!< LCD PAL24: R14_0 Mask               */
-#define LCD_PAL24_G14_0_Pos                                   21                                                        /*!< LCD PAL24: G14_0 Position           */
-#define LCD_PAL24_G14_0_Msk                                   (0x1fUL << LCD_PAL24_G14_0_Pos)                           /*!< LCD PAL24: G14_0 Mask               */
-#define LCD_PAL24_B14_0_Pos                                   26                                                        /*!< LCD PAL24: B14_0 Position           */
-#define LCD_PAL24_B14_0_Msk                                   (0x1fUL << LCD_PAL24_B14_0_Pos)                           /*!< LCD PAL24: B14_0 Mask               */
-#define LCD_PAL24_I1_Pos                                      31                                                        /*!< LCD PAL24: I1 Position              */
-#define LCD_PAL24_I1_Msk                                      (0x01UL << LCD_PAL24_I1_Pos)                              /*!< LCD PAL24: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL25  -------------------------------------------
-#define LCD_PAL25_R04_0_Pos                                   0                                                         /*!< LCD PAL25: R04_0 Position           */
-#define LCD_PAL25_R04_0_Msk                                   (0x1fUL << LCD_PAL25_R04_0_Pos)                           /*!< LCD PAL25: R04_0 Mask               */
-#define LCD_PAL25_G04_0_Pos                                   5                                                         /*!< LCD PAL25: G04_0 Position           */
-#define LCD_PAL25_G04_0_Msk                                   (0x1fUL << LCD_PAL25_G04_0_Pos)                           /*!< LCD PAL25: G04_0 Mask               */
-#define LCD_PAL25_B04_0_Pos                                   10                                                        /*!< LCD PAL25: B04_0 Position           */
-#define LCD_PAL25_B04_0_Msk                                   (0x1fUL << LCD_PAL25_B04_0_Pos)                           /*!< LCD PAL25: B04_0 Mask               */
-#define LCD_PAL25_I0_Pos                                      15                                                        /*!< LCD PAL25: I0 Position              */
-#define LCD_PAL25_I0_Msk                                      (0x01UL << LCD_PAL25_I0_Pos)                              /*!< LCD PAL25: I0 Mask                  */
-#define LCD_PAL25_R14_0_Pos                                   16                                                        /*!< LCD PAL25: R14_0 Position           */
-#define LCD_PAL25_R14_0_Msk                                   (0x1fUL << LCD_PAL25_R14_0_Pos)                           /*!< LCD PAL25: R14_0 Mask               */
-#define LCD_PAL25_G14_0_Pos                                   21                                                        /*!< LCD PAL25: G14_0 Position           */
-#define LCD_PAL25_G14_0_Msk                                   (0x1fUL << LCD_PAL25_G14_0_Pos)                           /*!< LCD PAL25: G14_0 Mask               */
-#define LCD_PAL25_B14_0_Pos                                   26                                                        /*!< LCD PAL25: B14_0 Position           */
-#define LCD_PAL25_B14_0_Msk                                   (0x1fUL << LCD_PAL25_B14_0_Pos)                           /*!< LCD PAL25: B14_0 Mask               */
-#define LCD_PAL25_I1_Pos                                      31                                                        /*!< LCD PAL25: I1 Position              */
-#define LCD_PAL25_I1_Msk                                      (0x01UL << LCD_PAL25_I1_Pos)                              /*!< LCD PAL25: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL26  -------------------------------------------
-#define LCD_PAL26_R04_0_Pos                                   0                                                         /*!< LCD PAL26: R04_0 Position           */
-#define LCD_PAL26_R04_0_Msk                                   (0x1fUL << LCD_PAL26_R04_0_Pos)                           /*!< LCD PAL26: R04_0 Mask               */
-#define LCD_PAL26_G04_0_Pos                                   5                                                         /*!< LCD PAL26: G04_0 Position           */
-#define LCD_PAL26_G04_0_Msk                                   (0x1fUL << LCD_PAL26_G04_0_Pos)                           /*!< LCD PAL26: G04_0 Mask               */
-#define LCD_PAL26_B04_0_Pos                                   10                                                        /*!< LCD PAL26: B04_0 Position           */
-#define LCD_PAL26_B04_0_Msk                                   (0x1fUL << LCD_PAL26_B04_0_Pos)                           /*!< LCD PAL26: B04_0 Mask               */
-#define LCD_PAL26_I0_Pos                                      15                                                        /*!< LCD PAL26: I0 Position              */
-#define LCD_PAL26_I0_Msk                                      (0x01UL << LCD_PAL26_I0_Pos)                              /*!< LCD PAL26: I0 Mask                  */
-#define LCD_PAL26_R14_0_Pos                                   16                                                        /*!< LCD PAL26: R14_0 Position           */
-#define LCD_PAL26_R14_0_Msk                                   (0x1fUL << LCD_PAL26_R14_0_Pos)                           /*!< LCD PAL26: R14_0 Mask               */
-#define LCD_PAL26_G14_0_Pos                                   21                                                        /*!< LCD PAL26: G14_0 Position           */
-#define LCD_PAL26_G14_0_Msk                                   (0x1fUL << LCD_PAL26_G14_0_Pos)                           /*!< LCD PAL26: G14_0 Mask               */
-#define LCD_PAL26_B14_0_Pos                                   26                                                        /*!< LCD PAL26: B14_0 Position           */
-#define LCD_PAL26_B14_0_Msk                                   (0x1fUL << LCD_PAL26_B14_0_Pos)                           /*!< LCD PAL26: B14_0 Mask               */
-#define LCD_PAL26_I1_Pos                                      31                                                        /*!< LCD PAL26: I1 Position              */
-#define LCD_PAL26_I1_Msk                                      (0x01UL << LCD_PAL26_I1_Pos)                              /*!< LCD PAL26: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL27  -------------------------------------------
-#define LCD_PAL27_R04_0_Pos                                   0                                                         /*!< LCD PAL27: R04_0 Position           */
-#define LCD_PAL27_R04_0_Msk                                   (0x1fUL << LCD_PAL27_R04_0_Pos)                           /*!< LCD PAL27: R04_0 Mask               */
-#define LCD_PAL27_G04_0_Pos                                   5                                                         /*!< LCD PAL27: G04_0 Position           */
-#define LCD_PAL27_G04_0_Msk                                   (0x1fUL << LCD_PAL27_G04_0_Pos)                           /*!< LCD PAL27: G04_0 Mask               */
-#define LCD_PAL27_B04_0_Pos                                   10                                                        /*!< LCD PAL27: B04_0 Position           */
-#define LCD_PAL27_B04_0_Msk                                   (0x1fUL << LCD_PAL27_B04_0_Pos)                           /*!< LCD PAL27: B04_0 Mask               */
-#define LCD_PAL27_I0_Pos                                      15                                                        /*!< LCD PAL27: I0 Position              */
-#define LCD_PAL27_I0_Msk                                      (0x01UL << LCD_PAL27_I0_Pos)                              /*!< LCD PAL27: I0 Mask                  */
-#define LCD_PAL27_R14_0_Pos                                   16                                                        /*!< LCD PAL27: R14_0 Position           */
-#define LCD_PAL27_R14_0_Msk                                   (0x1fUL << LCD_PAL27_R14_0_Pos)                           /*!< LCD PAL27: R14_0 Mask               */
-#define LCD_PAL27_G14_0_Pos                                   21                                                        /*!< LCD PAL27: G14_0 Position           */
-#define LCD_PAL27_G14_0_Msk                                   (0x1fUL << LCD_PAL27_G14_0_Pos)                           /*!< LCD PAL27: G14_0 Mask               */
-#define LCD_PAL27_B14_0_Pos                                   26                                                        /*!< LCD PAL27: B14_0 Position           */
-#define LCD_PAL27_B14_0_Msk                                   (0x1fUL << LCD_PAL27_B14_0_Pos)                           /*!< LCD PAL27: B14_0 Mask               */
-#define LCD_PAL27_I1_Pos                                      31                                                        /*!< LCD PAL27: I1 Position              */
-#define LCD_PAL27_I1_Msk                                      (0x01UL << LCD_PAL27_I1_Pos)                              /*!< LCD PAL27: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL28  -------------------------------------------
-#define LCD_PAL28_R04_0_Pos                                   0                                                         /*!< LCD PAL28: R04_0 Position           */
-#define LCD_PAL28_R04_0_Msk                                   (0x1fUL << LCD_PAL28_R04_0_Pos)                           /*!< LCD PAL28: R04_0 Mask               */
-#define LCD_PAL28_G04_0_Pos                                   5                                                         /*!< LCD PAL28: G04_0 Position           */
-#define LCD_PAL28_G04_0_Msk                                   (0x1fUL << LCD_PAL28_G04_0_Pos)                           /*!< LCD PAL28: G04_0 Mask               */
-#define LCD_PAL28_B04_0_Pos                                   10                                                        /*!< LCD PAL28: B04_0 Position           */
-#define LCD_PAL28_B04_0_Msk                                   (0x1fUL << LCD_PAL28_B04_0_Pos)                           /*!< LCD PAL28: B04_0 Mask               */
-#define LCD_PAL28_I0_Pos                                      15                                                        /*!< LCD PAL28: I0 Position              */
-#define LCD_PAL28_I0_Msk                                      (0x01UL << LCD_PAL28_I0_Pos)                              /*!< LCD PAL28: I0 Mask                  */
-#define LCD_PAL28_R14_0_Pos                                   16                                                        /*!< LCD PAL28: R14_0 Position           */
-#define LCD_PAL28_R14_0_Msk                                   (0x1fUL << LCD_PAL28_R14_0_Pos)                           /*!< LCD PAL28: R14_0 Mask               */
-#define LCD_PAL28_G14_0_Pos                                   21                                                        /*!< LCD PAL28: G14_0 Position           */
-#define LCD_PAL28_G14_0_Msk                                   (0x1fUL << LCD_PAL28_G14_0_Pos)                           /*!< LCD PAL28: G14_0 Mask               */
-#define LCD_PAL28_B14_0_Pos                                   26                                                        /*!< LCD PAL28: B14_0 Position           */
-#define LCD_PAL28_B14_0_Msk                                   (0x1fUL << LCD_PAL28_B14_0_Pos)                           /*!< LCD PAL28: B14_0 Mask               */
-#define LCD_PAL28_I1_Pos                                      31                                                        /*!< LCD PAL28: I1 Position              */
-#define LCD_PAL28_I1_Msk                                      (0x01UL << LCD_PAL28_I1_Pos)                              /*!< LCD PAL28: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL29  -------------------------------------------
-#define LCD_PAL29_R04_0_Pos                                   0                                                         /*!< LCD PAL29: R04_0 Position           */
-#define LCD_PAL29_R04_0_Msk                                   (0x1fUL << LCD_PAL29_R04_0_Pos)                           /*!< LCD PAL29: R04_0 Mask               */
-#define LCD_PAL29_G04_0_Pos                                   5                                                         /*!< LCD PAL29: G04_0 Position           */
-#define LCD_PAL29_G04_0_Msk                                   (0x1fUL << LCD_PAL29_G04_0_Pos)                           /*!< LCD PAL29: G04_0 Mask               */
-#define LCD_PAL29_B04_0_Pos                                   10                                                        /*!< LCD PAL29: B04_0 Position           */
-#define LCD_PAL29_B04_0_Msk                                   (0x1fUL << LCD_PAL29_B04_0_Pos)                           /*!< LCD PAL29: B04_0 Mask               */
-#define LCD_PAL29_I0_Pos                                      15                                                        /*!< LCD PAL29: I0 Position              */
-#define LCD_PAL29_I0_Msk                                      (0x01UL << LCD_PAL29_I0_Pos)                              /*!< LCD PAL29: I0 Mask                  */
-#define LCD_PAL29_R14_0_Pos                                   16                                                        /*!< LCD PAL29: R14_0 Position           */
-#define LCD_PAL29_R14_0_Msk                                   (0x1fUL << LCD_PAL29_R14_0_Pos)                           /*!< LCD PAL29: R14_0 Mask               */
-#define LCD_PAL29_G14_0_Pos                                   21                                                        /*!< LCD PAL29: G14_0 Position           */
-#define LCD_PAL29_G14_0_Msk                                   (0x1fUL << LCD_PAL29_G14_0_Pos)                           /*!< LCD PAL29: G14_0 Mask               */
-#define LCD_PAL29_B14_0_Pos                                   26                                                        /*!< LCD PAL29: B14_0 Position           */
-#define LCD_PAL29_B14_0_Msk                                   (0x1fUL << LCD_PAL29_B14_0_Pos)                           /*!< LCD PAL29: B14_0 Mask               */
-#define LCD_PAL29_I1_Pos                                      31                                                        /*!< LCD PAL29: I1 Position              */
-#define LCD_PAL29_I1_Msk                                      (0x01UL << LCD_PAL29_I1_Pos)                              /*!< LCD PAL29: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL30  -------------------------------------------
-#define LCD_PAL30_R04_0_Pos                                   0                                                         /*!< LCD PAL30: R04_0 Position           */
-#define LCD_PAL30_R04_0_Msk                                   (0x1fUL << LCD_PAL30_R04_0_Pos)                           /*!< LCD PAL30: R04_0 Mask               */
-#define LCD_PAL30_G04_0_Pos                                   5                                                         /*!< LCD PAL30: G04_0 Position           */
-#define LCD_PAL30_G04_0_Msk                                   (0x1fUL << LCD_PAL30_G04_0_Pos)                           /*!< LCD PAL30: G04_0 Mask               */
-#define LCD_PAL30_B04_0_Pos                                   10                                                        /*!< LCD PAL30: B04_0 Position           */
-#define LCD_PAL30_B04_0_Msk                                   (0x1fUL << LCD_PAL30_B04_0_Pos)                           /*!< LCD PAL30: B04_0 Mask               */
-#define LCD_PAL30_I0_Pos                                      15                                                        /*!< LCD PAL30: I0 Position              */
-#define LCD_PAL30_I0_Msk                                      (0x01UL << LCD_PAL30_I0_Pos)                              /*!< LCD PAL30: I0 Mask                  */
-#define LCD_PAL30_R14_0_Pos                                   16                                                        /*!< LCD PAL30: R14_0 Position           */
-#define LCD_PAL30_R14_0_Msk                                   (0x1fUL << LCD_PAL30_R14_0_Pos)                           /*!< LCD PAL30: R14_0 Mask               */
-#define LCD_PAL30_G14_0_Pos                                   21                                                        /*!< LCD PAL30: G14_0 Position           */
-#define LCD_PAL30_G14_0_Msk                                   (0x1fUL << LCD_PAL30_G14_0_Pos)                           /*!< LCD PAL30: G14_0 Mask               */
-#define LCD_PAL30_B14_0_Pos                                   26                                                        /*!< LCD PAL30: B14_0 Position           */
-#define LCD_PAL30_B14_0_Msk                                   (0x1fUL << LCD_PAL30_B14_0_Pos)                           /*!< LCD PAL30: B14_0 Mask               */
-#define LCD_PAL30_I1_Pos                                      31                                                        /*!< LCD PAL30: I1 Position              */
-#define LCD_PAL30_I1_Msk                                      (0x01UL << LCD_PAL30_I1_Pos)                              /*!< LCD PAL30: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL31  -------------------------------------------
-#define LCD_PAL31_R04_0_Pos                                   0                                                         /*!< LCD PAL31: R04_0 Position           */
-#define LCD_PAL31_R04_0_Msk                                   (0x1fUL << LCD_PAL31_R04_0_Pos)                           /*!< LCD PAL31: R04_0 Mask               */
-#define LCD_PAL31_G04_0_Pos                                   5                                                         /*!< LCD PAL31: G04_0 Position           */
-#define LCD_PAL31_G04_0_Msk                                   (0x1fUL << LCD_PAL31_G04_0_Pos)                           /*!< LCD PAL31: G04_0 Mask               */
-#define LCD_PAL31_B04_0_Pos                                   10                                                        /*!< LCD PAL31: B04_0 Position           */
-#define LCD_PAL31_B04_0_Msk                                   (0x1fUL << LCD_PAL31_B04_0_Pos)                           /*!< LCD PAL31: B04_0 Mask               */
-#define LCD_PAL31_I0_Pos                                      15                                                        /*!< LCD PAL31: I0 Position              */
-#define LCD_PAL31_I0_Msk                                      (0x01UL << LCD_PAL31_I0_Pos)                              /*!< LCD PAL31: I0 Mask                  */
-#define LCD_PAL31_R14_0_Pos                                   16                                                        /*!< LCD PAL31: R14_0 Position           */
-#define LCD_PAL31_R14_0_Msk                                   (0x1fUL << LCD_PAL31_R14_0_Pos)                           /*!< LCD PAL31: R14_0 Mask               */
-#define LCD_PAL31_G14_0_Pos                                   21                                                        /*!< LCD PAL31: G14_0 Position           */
-#define LCD_PAL31_G14_0_Msk                                   (0x1fUL << LCD_PAL31_G14_0_Pos)                           /*!< LCD PAL31: G14_0 Mask               */
-#define LCD_PAL31_B14_0_Pos                                   26                                                        /*!< LCD PAL31: B14_0 Position           */
-#define LCD_PAL31_B14_0_Msk                                   (0x1fUL << LCD_PAL31_B14_0_Pos)                           /*!< LCD PAL31: B14_0 Mask               */
-#define LCD_PAL31_I1_Pos                                      31                                                        /*!< LCD PAL31: I1 Position              */
-#define LCD_PAL31_I1_Msk                                      (0x01UL << LCD_PAL31_I1_Pos)                              /*!< LCD PAL31: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL32  -------------------------------------------
-#define LCD_PAL32_R04_0_Pos                                   0                                                         /*!< LCD PAL32: R04_0 Position           */
-#define LCD_PAL32_R04_0_Msk                                   (0x1fUL << LCD_PAL32_R04_0_Pos)                           /*!< LCD PAL32: R04_0 Mask               */
-#define LCD_PAL32_G04_0_Pos                                   5                                                         /*!< LCD PAL32: G04_0 Position           */
-#define LCD_PAL32_G04_0_Msk                                   (0x1fUL << LCD_PAL32_G04_0_Pos)                           /*!< LCD PAL32: G04_0 Mask               */
-#define LCD_PAL32_B04_0_Pos                                   10                                                        /*!< LCD PAL32: B04_0 Position           */
-#define LCD_PAL32_B04_0_Msk                                   (0x1fUL << LCD_PAL32_B04_0_Pos)                           /*!< LCD PAL32: B04_0 Mask               */
-#define LCD_PAL32_I0_Pos                                      15                                                        /*!< LCD PAL32: I0 Position              */
-#define LCD_PAL32_I0_Msk                                      (0x01UL << LCD_PAL32_I0_Pos)                              /*!< LCD PAL32: I0 Mask                  */
-#define LCD_PAL32_R14_0_Pos                                   16                                                        /*!< LCD PAL32: R14_0 Position           */
-#define LCD_PAL32_R14_0_Msk                                   (0x1fUL << LCD_PAL32_R14_0_Pos)                           /*!< LCD PAL32: R14_0 Mask               */
-#define LCD_PAL32_G14_0_Pos                                   21                                                        /*!< LCD PAL32: G14_0 Position           */
-#define LCD_PAL32_G14_0_Msk                                   (0x1fUL << LCD_PAL32_G14_0_Pos)                           /*!< LCD PAL32: G14_0 Mask               */
-#define LCD_PAL32_B14_0_Pos                                   26                                                        /*!< LCD PAL32: B14_0 Position           */
-#define LCD_PAL32_B14_0_Msk                                   (0x1fUL << LCD_PAL32_B14_0_Pos)                           /*!< LCD PAL32: B14_0 Mask               */
-#define LCD_PAL32_I1_Pos                                      31                                                        /*!< LCD PAL32: I1 Position              */
-#define LCD_PAL32_I1_Msk                                      (0x01UL << LCD_PAL32_I1_Pos)                              /*!< LCD PAL32: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL33  -------------------------------------------
-#define LCD_PAL33_R04_0_Pos                                   0                                                         /*!< LCD PAL33: R04_0 Position           */
-#define LCD_PAL33_R04_0_Msk                                   (0x1fUL << LCD_PAL33_R04_0_Pos)                           /*!< LCD PAL33: R04_0 Mask               */
-#define LCD_PAL33_G04_0_Pos                                   5                                                         /*!< LCD PAL33: G04_0 Position           */
-#define LCD_PAL33_G04_0_Msk                                   (0x1fUL << LCD_PAL33_G04_0_Pos)                           /*!< LCD PAL33: G04_0 Mask               */
-#define LCD_PAL33_B04_0_Pos                                   10                                                        /*!< LCD PAL33: B04_0 Position           */
-#define LCD_PAL33_B04_0_Msk                                   (0x1fUL << LCD_PAL33_B04_0_Pos)                           /*!< LCD PAL33: B04_0 Mask               */
-#define LCD_PAL33_I0_Pos                                      15                                                        /*!< LCD PAL33: I0 Position              */
-#define LCD_PAL33_I0_Msk                                      (0x01UL << LCD_PAL33_I0_Pos)                              /*!< LCD PAL33: I0 Mask                  */
-#define LCD_PAL33_R14_0_Pos                                   16                                                        /*!< LCD PAL33: R14_0 Position           */
-#define LCD_PAL33_R14_0_Msk                                   (0x1fUL << LCD_PAL33_R14_0_Pos)                           /*!< LCD PAL33: R14_0 Mask               */
-#define LCD_PAL33_G14_0_Pos                                   21                                                        /*!< LCD PAL33: G14_0 Position           */
-#define LCD_PAL33_G14_0_Msk                                   (0x1fUL << LCD_PAL33_G14_0_Pos)                           /*!< LCD PAL33: G14_0 Mask               */
-#define LCD_PAL33_B14_0_Pos                                   26                                                        /*!< LCD PAL33: B14_0 Position           */
-#define LCD_PAL33_B14_0_Msk                                   (0x1fUL << LCD_PAL33_B14_0_Pos)                           /*!< LCD PAL33: B14_0 Mask               */
-#define LCD_PAL33_I1_Pos                                      31                                                        /*!< LCD PAL33: I1 Position              */
-#define LCD_PAL33_I1_Msk                                      (0x01UL << LCD_PAL33_I1_Pos)                              /*!< LCD PAL33: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL34  -------------------------------------------
-#define LCD_PAL34_R04_0_Pos                                   0                                                         /*!< LCD PAL34: R04_0 Position           */
-#define LCD_PAL34_R04_0_Msk                                   (0x1fUL << LCD_PAL34_R04_0_Pos)                           /*!< LCD PAL34: R04_0 Mask               */
-#define LCD_PAL34_G04_0_Pos                                   5                                                         /*!< LCD PAL34: G04_0 Position           */
-#define LCD_PAL34_G04_0_Msk                                   (0x1fUL << LCD_PAL34_G04_0_Pos)                           /*!< LCD PAL34: G04_0 Mask               */
-#define LCD_PAL34_B04_0_Pos                                   10                                                        /*!< LCD PAL34: B04_0 Position           */
-#define LCD_PAL34_B04_0_Msk                                   (0x1fUL << LCD_PAL34_B04_0_Pos)                           /*!< LCD PAL34: B04_0 Mask               */
-#define LCD_PAL34_I0_Pos                                      15                                                        /*!< LCD PAL34: I0 Position              */
-#define LCD_PAL34_I0_Msk                                      (0x01UL << LCD_PAL34_I0_Pos)                              /*!< LCD PAL34: I0 Mask                  */
-#define LCD_PAL34_R14_0_Pos                                   16                                                        /*!< LCD PAL34: R14_0 Position           */
-#define LCD_PAL34_R14_0_Msk                                   (0x1fUL << LCD_PAL34_R14_0_Pos)                           /*!< LCD PAL34: R14_0 Mask               */
-#define LCD_PAL34_G14_0_Pos                                   21                                                        /*!< LCD PAL34: G14_0 Position           */
-#define LCD_PAL34_G14_0_Msk                                   (0x1fUL << LCD_PAL34_G14_0_Pos)                           /*!< LCD PAL34: G14_0 Mask               */
-#define LCD_PAL34_B14_0_Pos                                   26                                                        /*!< LCD PAL34: B14_0 Position           */
-#define LCD_PAL34_B14_0_Msk                                   (0x1fUL << LCD_PAL34_B14_0_Pos)                           /*!< LCD PAL34: B14_0 Mask               */
-#define LCD_PAL34_I1_Pos                                      31                                                        /*!< LCD PAL34: I1 Position              */
-#define LCD_PAL34_I1_Msk                                      (0x01UL << LCD_PAL34_I1_Pos)                              /*!< LCD PAL34: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL35  -------------------------------------------
-#define LCD_PAL35_R04_0_Pos                                   0                                                         /*!< LCD PAL35: R04_0 Position           */
-#define LCD_PAL35_R04_0_Msk                                   (0x1fUL << LCD_PAL35_R04_0_Pos)                           /*!< LCD PAL35: R04_0 Mask               */
-#define LCD_PAL35_G04_0_Pos                                   5                                                         /*!< LCD PAL35: G04_0 Position           */
-#define LCD_PAL35_G04_0_Msk                                   (0x1fUL << LCD_PAL35_G04_0_Pos)                           /*!< LCD PAL35: G04_0 Mask               */
-#define LCD_PAL35_B04_0_Pos                                   10                                                        /*!< LCD PAL35: B04_0 Position           */
-#define LCD_PAL35_B04_0_Msk                                   (0x1fUL << LCD_PAL35_B04_0_Pos)                           /*!< LCD PAL35: B04_0 Mask               */
-#define LCD_PAL35_I0_Pos                                      15                                                        /*!< LCD PAL35: I0 Position              */
-#define LCD_PAL35_I0_Msk                                      (0x01UL << LCD_PAL35_I0_Pos)                              /*!< LCD PAL35: I0 Mask                  */
-#define LCD_PAL35_R14_0_Pos                                   16                                                        /*!< LCD PAL35: R14_0 Position           */
-#define LCD_PAL35_R14_0_Msk                                   (0x1fUL << LCD_PAL35_R14_0_Pos)                           /*!< LCD PAL35: R14_0 Mask               */
-#define LCD_PAL35_G14_0_Pos                                   21                                                        /*!< LCD PAL35: G14_0 Position           */
-#define LCD_PAL35_G14_0_Msk                                   (0x1fUL << LCD_PAL35_G14_0_Pos)                           /*!< LCD PAL35: G14_0 Mask               */
-#define LCD_PAL35_B14_0_Pos                                   26                                                        /*!< LCD PAL35: B14_0 Position           */
-#define LCD_PAL35_B14_0_Msk                                   (0x1fUL << LCD_PAL35_B14_0_Pos)                           /*!< LCD PAL35: B14_0 Mask               */
-#define LCD_PAL35_I1_Pos                                      31                                                        /*!< LCD PAL35: I1 Position              */
-#define LCD_PAL35_I1_Msk                                      (0x01UL << LCD_PAL35_I1_Pos)                              /*!< LCD PAL35: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL36  -------------------------------------------
-#define LCD_PAL36_R04_0_Pos                                   0                                                         /*!< LCD PAL36: R04_0 Position           */
-#define LCD_PAL36_R04_0_Msk                                   (0x1fUL << LCD_PAL36_R04_0_Pos)                           /*!< LCD PAL36: R04_0 Mask               */
-#define LCD_PAL36_G04_0_Pos                                   5                                                         /*!< LCD PAL36: G04_0 Position           */
-#define LCD_PAL36_G04_0_Msk                                   (0x1fUL << LCD_PAL36_G04_0_Pos)                           /*!< LCD PAL36: G04_0 Mask               */
-#define LCD_PAL36_B04_0_Pos                                   10                                                        /*!< LCD PAL36: B04_0 Position           */
-#define LCD_PAL36_B04_0_Msk                                   (0x1fUL << LCD_PAL36_B04_0_Pos)                           /*!< LCD PAL36: B04_0 Mask               */
-#define LCD_PAL36_I0_Pos                                      15                                                        /*!< LCD PAL36: I0 Position              */
-#define LCD_PAL36_I0_Msk                                      (0x01UL << LCD_PAL36_I0_Pos)                              /*!< LCD PAL36: I0 Mask                  */
-#define LCD_PAL36_R14_0_Pos                                   16                                                        /*!< LCD PAL36: R14_0 Position           */
-#define LCD_PAL36_R14_0_Msk                                   (0x1fUL << LCD_PAL36_R14_0_Pos)                           /*!< LCD PAL36: R14_0 Mask               */
-#define LCD_PAL36_G14_0_Pos                                   21                                                        /*!< LCD PAL36: G14_0 Position           */
-#define LCD_PAL36_G14_0_Msk                                   (0x1fUL << LCD_PAL36_G14_0_Pos)                           /*!< LCD PAL36: G14_0 Mask               */
-#define LCD_PAL36_B14_0_Pos                                   26                                                        /*!< LCD PAL36: B14_0 Position           */
-#define LCD_PAL36_B14_0_Msk                                   (0x1fUL << LCD_PAL36_B14_0_Pos)                           /*!< LCD PAL36: B14_0 Mask               */
-#define LCD_PAL36_I1_Pos                                      31                                                        /*!< LCD PAL36: I1 Position              */
-#define LCD_PAL36_I1_Msk                                      (0x01UL << LCD_PAL36_I1_Pos)                              /*!< LCD PAL36: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL37  -------------------------------------------
-#define LCD_PAL37_R04_0_Pos                                   0                                                         /*!< LCD PAL37: R04_0 Position           */
-#define LCD_PAL37_R04_0_Msk                                   (0x1fUL << LCD_PAL37_R04_0_Pos)                           /*!< LCD PAL37: R04_0 Mask               */
-#define LCD_PAL37_G04_0_Pos                                   5                                                         /*!< LCD PAL37: G04_0 Position           */
-#define LCD_PAL37_G04_0_Msk                                   (0x1fUL << LCD_PAL37_G04_0_Pos)                           /*!< LCD PAL37: G04_0 Mask               */
-#define LCD_PAL37_B04_0_Pos                                   10                                                        /*!< LCD PAL37: B04_0 Position           */
-#define LCD_PAL37_B04_0_Msk                                   (0x1fUL << LCD_PAL37_B04_0_Pos)                           /*!< LCD PAL37: B04_0 Mask               */
-#define LCD_PAL37_I0_Pos                                      15                                                        /*!< LCD PAL37: I0 Position              */
-#define LCD_PAL37_I0_Msk                                      (0x01UL << LCD_PAL37_I0_Pos)                              /*!< LCD PAL37: I0 Mask                  */
-#define LCD_PAL37_R14_0_Pos                                   16                                                        /*!< LCD PAL37: R14_0 Position           */
-#define LCD_PAL37_R14_0_Msk                                   (0x1fUL << LCD_PAL37_R14_0_Pos)                           /*!< LCD PAL37: R14_0 Mask               */
-#define LCD_PAL37_G14_0_Pos                                   21                                                        /*!< LCD PAL37: G14_0 Position           */
-#define LCD_PAL37_G14_0_Msk                                   (0x1fUL << LCD_PAL37_G14_0_Pos)                           /*!< LCD PAL37: G14_0 Mask               */
-#define LCD_PAL37_B14_0_Pos                                   26                                                        /*!< LCD PAL37: B14_0 Position           */
-#define LCD_PAL37_B14_0_Msk                                   (0x1fUL << LCD_PAL37_B14_0_Pos)                           /*!< LCD PAL37: B14_0 Mask               */
-#define LCD_PAL37_I1_Pos                                      31                                                        /*!< LCD PAL37: I1 Position              */
-#define LCD_PAL37_I1_Msk                                      (0x01UL << LCD_PAL37_I1_Pos)                              /*!< LCD PAL37: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL38  -------------------------------------------
-#define LCD_PAL38_R04_0_Pos                                   0                                                         /*!< LCD PAL38: R04_0 Position           */
-#define LCD_PAL38_R04_0_Msk                                   (0x1fUL << LCD_PAL38_R04_0_Pos)                           /*!< LCD PAL38: R04_0 Mask               */
-#define LCD_PAL38_G04_0_Pos                                   5                                                         /*!< LCD PAL38: G04_0 Position           */
-#define LCD_PAL38_G04_0_Msk                                   (0x1fUL << LCD_PAL38_G04_0_Pos)                           /*!< LCD PAL38: G04_0 Mask               */
-#define LCD_PAL38_B04_0_Pos                                   10                                                        /*!< LCD PAL38: B04_0 Position           */
-#define LCD_PAL38_B04_0_Msk                                   (0x1fUL << LCD_PAL38_B04_0_Pos)                           /*!< LCD PAL38: B04_0 Mask               */
-#define LCD_PAL38_I0_Pos                                      15                                                        /*!< LCD PAL38: I0 Position              */
-#define LCD_PAL38_I0_Msk                                      (0x01UL << LCD_PAL38_I0_Pos)                              /*!< LCD PAL38: I0 Mask                  */
-#define LCD_PAL38_R14_0_Pos                                   16                                                        /*!< LCD PAL38: R14_0 Position           */
-#define LCD_PAL38_R14_0_Msk                                   (0x1fUL << LCD_PAL38_R14_0_Pos)                           /*!< LCD PAL38: R14_0 Mask               */
-#define LCD_PAL38_G14_0_Pos                                   21                                                        /*!< LCD PAL38: G14_0 Position           */
-#define LCD_PAL38_G14_0_Msk                                   (0x1fUL << LCD_PAL38_G14_0_Pos)                           /*!< LCD PAL38: G14_0 Mask               */
-#define LCD_PAL38_B14_0_Pos                                   26                                                        /*!< LCD PAL38: B14_0 Position           */
-#define LCD_PAL38_B14_0_Msk                                   (0x1fUL << LCD_PAL38_B14_0_Pos)                           /*!< LCD PAL38: B14_0 Mask               */
-#define LCD_PAL38_I1_Pos                                      31                                                        /*!< LCD PAL38: I1 Position              */
-#define LCD_PAL38_I1_Msk                                      (0x01UL << LCD_PAL38_I1_Pos)                              /*!< LCD PAL38: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL39  -------------------------------------------
-#define LCD_PAL39_R04_0_Pos                                   0                                                         /*!< LCD PAL39: R04_0 Position           */
-#define LCD_PAL39_R04_0_Msk                                   (0x1fUL << LCD_PAL39_R04_0_Pos)                           /*!< LCD PAL39: R04_0 Mask               */
-#define LCD_PAL39_G04_0_Pos                                   5                                                         /*!< LCD PAL39: G04_0 Position           */
-#define LCD_PAL39_G04_0_Msk                                   (0x1fUL << LCD_PAL39_G04_0_Pos)                           /*!< LCD PAL39: G04_0 Mask               */
-#define LCD_PAL39_B04_0_Pos                                   10                                                        /*!< LCD PAL39: B04_0 Position           */
-#define LCD_PAL39_B04_0_Msk                                   (0x1fUL << LCD_PAL39_B04_0_Pos)                           /*!< LCD PAL39: B04_0 Mask               */
-#define LCD_PAL39_I0_Pos                                      15                                                        /*!< LCD PAL39: I0 Position              */
-#define LCD_PAL39_I0_Msk                                      (0x01UL << LCD_PAL39_I0_Pos)                              /*!< LCD PAL39: I0 Mask                  */
-#define LCD_PAL39_R14_0_Pos                                   16                                                        /*!< LCD PAL39: R14_0 Position           */
-#define LCD_PAL39_R14_0_Msk                                   (0x1fUL << LCD_PAL39_R14_0_Pos)                           /*!< LCD PAL39: R14_0 Mask               */
-#define LCD_PAL39_G14_0_Pos                                   21                                                        /*!< LCD PAL39: G14_0 Position           */
-#define LCD_PAL39_G14_0_Msk                                   (0x1fUL << LCD_PAL39_G14_0_Pos)                           /*!< LCD PAL39: G14_0 Mask               */
-#define LCD_PAL39_B14_0_Pos                                   26                                                        /*!< LCD PAL39: B14_0 Position           */
-#define LCD_PAL39_B14_0_Msk                                   (0x1fUL << LCD_PAL39_B14_0_Pos)                           /*!< LCD PAL39: B14_0 Mask               */
-#define LCD_PAL39_I1_Pos                                      31                                                        /*!< LCD PAL39: I1 Position              */
-#define LCD_PAL39_I1_Msk                                      (0x01UL << LCD_PAL39_I1_Pos)                              /*!< LCD PAL39: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL40  -------------------------------------------
-#define LCD_PAL40_R04_0_Pos                                   0                                                         /*!< LCD PAL40: R04_0 Position           */
-#define LCD_PAL40_R04_0_Msk                                   (0x1fUL << LCD_PAL40_R04_0_Pos)                           /*!< LCD PAL40: R04_0 Mask               */
-#define LCD_PAL40_G04_0_Pos                                   5                                                         /*!< LCD PAL40: G04_0 Position           */
-#define LCD_PAL40_G04_0_Msk                                   (0x1fUL << LCD_PAL40_G04_0_Pos)                           /*!< LCD PAL40: G04_0 Mask               */
-#define LCD_PAL40_B04_0_Pos                                   10                                                        /*!< LCD PAL40: B04_0 Position           */
-#define LCD_PAL40_B04_0_Msk                                   (0x1fUL << LCD_PAL40_B04_0_Pos)                           /*!< LCD PAL40: B04_0 Mask               */
-#define LCD_PAL40_I0_Pos                                      15                                                        /*!< LCD PAL40: I0 Position              */
-#define LCD_PAL40_I0_Msk                                      (0x01UL << LCD_PAL40_I0_Pos)                              /*!< LCD PAL40: I0 Mask                  */
-#define LCD_PAL40_R14_0_Pos                                   16                                                        /*!< LCD PAL40: R14_0 Position           */
-#define LCD_PAL40_R14_0_Msk                                   (0x1fUL << LCD_PAL40_R14_0_Pos)                           /*!< LCD PAL40: R14_0 Mask               */
-#define LCD_PAL40_G14_0_Pos                                   21                                                        /*!< LCD PAL40: G14_0 Position           */
-#define LCD_PAL40_G14_0_Msk                                   (0x1fUL << LCD_PAL40_G14_0_Pos)                           /*!< LCD PAL40: G14_0 Mask               */
-#define LCD_PAL40_B14_0_Pos                                   26                                                        /*!< LCD PAL40: B14_0 Position           */
-#define LCD_PAL40_B14_0_Msk                                   (0x1fUL << LCD_PAL40_B14_0_Pos)                           /*!< LCD PAL40: B14_0 Mask               */
-#define LCD_PAL40_I1_Pos                                      31                                                        /*!< LCD PAL40: I1 Position              */
-#define LCD_PAL40_I1_Msk                                      (0x01UL << LCD_PAL40_I1_Pos)                              /*!< LCD PAL40: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL41  -------------------------------------------
-#define LCD_PAL41_R04_0_Pos                                   0                                                         /*!< LCD PAL41: R04_0 Position           */
-#define LCD_PAL41_R04_0_Msk                                   (0x1fUL << LCD_PAL41_R04_0_Pos)                           /*!< LCD PAL41: R04_0 Mask               */
-#define LCD_PAL41_G04_0_Pos                                   5                                                         /*!< LCD PAL41: G04_0 Position           */
-#define LCD_PAL41_G04_0_Msk                                   (0x1fUL << LCD_PAL41_G04_0_Pos)                           /*!< LCD PAL41: G04_0 Mask               */
-#define LCD_PAL41_B04_0_Pos                                   10                                                        /*!< LCD PAL41: B04_0 Position           */
-#define LCD_PAL41_B04_0_Msk                                   (0x1fUL << LCD_PAL41_B04_0_Pos)                           /*!< LCD PAL41: B04_0 Mask               */
-#define LCD_PAL41_I0_Pos                                      15                                                        /*!< LCD PAL41: I0 Position              */
-#define LCD_PAL41_I0_Msk                                      (0x01UL << LCD_PAL41_I0_Pos)                              /*!< LCD PAL41: I0 Mask                  */
-#define LCD_PAL41_R14_0_Pos                                   16                                                        /*!< LCD PAL41: R14_0 Position           */
-#define LCD_PAL41_R14_0_Msk                                   (0x1fUL << LCD_PAL41_R14_0_Pos)                           /*!< LCD PAL41: R14_0 Mask               */
-#define LCD_PAL41_G14_0_Pos                                   21                                                        /*!< LCD PAL41: G14_0 Position           */
-#define LCD_PAL41_G14_0_Msk                                   (0x1fUL << LCD_PAL41_G14_0_Pos)                           /*!< LCD PAL41: G14_0 Mask               */
-#define LCD_PAL41_B14_0_Pos                                   26                                                        /*!< LCD PAL41: B14_0 Position           */
-#define LCD_PAL41_B14_0_Msk                                   (0x1fUL << LCD_PAL41_B14_0_Pos)                           /*!< LCD PAL41: B14_0 Mask               */
-#define LCD_PAL41_I1_Pos                                      31                                                        /*!< LCD PAL41: I1 Position              */
-#define LCD_PAL41_I1_Msk                                      (0x01UL << LCD_PAL41_I1_Pos)                              /*!< LCD PAL41: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL42  -------------------------------------------
-#define LCD_PAL42_R04_0_Pos                                   0                                                         /*!< LCD PAL42: R04_0 Position           */
-#define LCD_PAL42_R04_0_Msk                                   (0x1fUL << LCD_PAL42_R04_0_Pos)                           /*!< LCD PAL42: R04_0 Mask               */
-#define LCD_PAL42_G04_0_Pos                                   5                                                         /*!< LCD PAL42: G04_0 Position           */
-#define LCD_PAL42_G04_0_Msk                                   (0x1fUL << LCD_PAL42_G04_0_Pos)                           /*!< LCD PAL42: G04_0 Mask               */
-#define LCD_PAL42_B04_0_Pos                                   10                                                        /*!< LCD PAL42: B04_0 Position           */
-#define LCD_PAL42_B04_0_Msk                                   (0x1fUL << LCD_PAL42_B04_0_Pos)                           /*!< LCD PAL42: B04_0 Mask               */
-#define LCD_PAL42_I0_Pos                                      15                                                        /*!< LCD PAL42: I0 Position              */
-#define LCD_PAL42_I0_Msk                                      (0x01UL << LCD_PAL42_I0_Pos)                              /*!< LCD PAL42: I0 Mask                  */
-#define LCD_PAL42_R14_0_Pos                                   16                                                        /*!< LCD PAL42: R14_0 Position           */
-#define LCD_PAL42_R14_0_Msk                                   (0x1fUL << LCD_PAL42_R14_0_Pos)                           /*!< LCD PAL42: R14_0 Mask               */
-#define LCD_PAL42_G14_0_Pos                                   21                                                        /*!< LCD PAL42: G14_0 Position           */
-#define LCD_PAL42_G14_0_Msk                                   (0x1fUL << LCD_PAL42_G14_0_Pos)                           /*!< LCD PAL42: G14_0 Mask               */
-#define LCD_PAL42_B14_0_Pos                                   26                                                        /*!< LCD PAL42: B14_0 Position           */
-#define LCD_PAL42_B14_0_Msk                                   (0x1fUL << LCD_PAL42_B14_0_Pos)                           /*!< LCD PAL42: B14_0 Mask               */
-#define LCD_PAL42_I1_Pos                                      31                                                        /*!< LCD PAL42: I1 Position              */
-#define LCD_PAL42_I1_Msk                                      (0x01UL << LCD_PAL42_I1_Pos)                              /*!< LCD PAL42: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL43  -------------------------------------------
-#define LCD_PAL43_R04_0_Pos                                   0                                                         /*!< LCD PAL43: R04_0 Position           */
-#define LCD_PAL43_R04_0_Msk                                   (0x1fUL << LCD_PAL43_R04_0_Pos)                           /*!< LCD PAL43: R04_0 Mask               */
-#define LCD_PAL43_G04_0_Pos                                   5                                                         /*!< LCD PAL43: G04_0 Position           */
-#define LCD_PAL43_G04_0_Msk                                   (0x1fUL << LCD_PAL43_G04_0_Pos)                           /*!< LCD PAL43: G04_0 Mask               */
-#define LCD_PAL43_B04_0_Pos                                   10                                                        /*!< LCD PAL43: B04_0 Position           */
-#define LCD_PAL43_B04_0_Msk                                   (0x1fUL << LCD_PAL43_B04_0_Pos)                           /*!< LCD PAL43: B04_0 Mask               */
-#define LCD_PAL43_I0_Pos                                      15                                                        /*!< LCD PAL43: I0 Position              */
-#define LCD_PAL43_I0_Msk                                      (0x01UL << LCD_PAL43_I0_Pos)                              /*!< LCD PAL43: I0 Mask                  */
-#define LCD_PAL43_R14_0_Pos                                   16                                                        /*!< LCD PAL43: R14_0 Position           */
-#define LCD_PAL43_R14_0_Msk                                   (0x1fUL << LCD_PAL43_R14_0_Pos)                           /*!< LCD PAL43: R14_0 Mask               */
-#define LCD_PAL43_G14_0_Pos                                   21                                                        /*!< LCD PAL43: G14_0 Position           */
-#define LCD_PAL43_G14_0_Msk                                   (0x1fUL << LCD_PAL43_G14_0_Pos)                           /*!< LCD PAL43: G14_0 Mask               */
-#define LCD_PAL43_B14_0_Pos                                   26                                                        /*!< LCD PAL43: B14_0 Position           */
-#define LCD_PAL43_B14_0_Msk                                   (0x1fUL << LCD_PAL43_B14_0_Pos)                           /*!< LCD PAL43: B14_0 Mask               */
-#define LCD_PAL43_I1_Pos                                      31                                                        /*!< LCD PAL43: I1 Position              */
-#define LCD_PAL43_I1_Msk                                      (0x01UL << LCD_PAL43_I1_Pos)                              /*!< LCD PAL43: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL44  -------------------------------------------
-#define LCD_PAL44_R04_0_Pos                                   0                                                         /*!< LCD PAL44: R04_0 Position           */
-#define LCD_PAL44_R04_0_Msk                                   (0x1fUL << LCD_PAL44_R04_0_Pos)                           /*!< LCD PAL44: R04_0 Mask               */
-#define LCD_PAL44_G04_0_Pos                                   5                                                         /*!< LCD PAL44: G04_0 Position           */
-#define LCD_PAL44_G04_0_Msk                                   (0x1fUL << LCD_PAL44_G04_0_Pos)                           /*!< LCD PAL44: G04_0 Mask               */
-#define LCD_PAL44_B04_0_Pos                                   10                                                        /*!< LCD PAL44: B04_0 Position           */
-#define LCD_PAL44_B04_0_Msk                                   (0x1fUL << LCD_PAL44_B04_0_Pos)                           /*!< LCD PAL44: B04_0 Mask               */
-#define LCD_PAL44_I0_Pos                                      15                                                        /*!< LCD PAL44: I0 Position              */
-#define LCD_PAL44_I0_Msk                                      (0x01UL << LCD_PAL44_I0_Pos)                              /*!< LCD PAL44: I0 Mask                  */
-#define LCD_PAL44_R14_0_Pos                                   16                                                        /*!< LCD PAL44: R14_0 Position           */
-#define LCD_PAL44_R14_0_Msk                                   (0x1fUL << LCD_PAL44_R14_0_Pos)                           /*!< LCD PAL44: R14_0 Mask               */
-#define LCD_PAL44_G14_0_Pos                                   21                                                        /*!< LCD PAL44: G14_0 Position           */
-#define LCD_PAL44_G14_0_Msk                                   (0x1fUL << LCD_PAL44_G14_0_Pos)                           /*!< LCD PAL44: G14_0 Mask               */
-#define LCD_PAL44_B14_0_Pos                                   26                                                        /*!< LCD PAL44: B14_0 Position           */
-#define LCD_PAL44_B14_0_Msk                                   (0x1fUL << LCD_PAL44_B14_0_Pos)                           /*!< LCD PAL44: B14_0 Mask               */
-#define LCD_PAL44_I1_Pos                                      31                                                        /*!< LCD PAL44: I1 Position              */
-#define LCD_PAL44_I1_Msk                                      (0x01UL << LCD_PAL44_I1_Pos)                              /*!< LCD PAL44: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL45  -------------------------------------------
-#define LCD_PAL45_R04_0_Pos                                   0                                                         /*!< LCD PAL45: R04_0 Position           */
-#define LCD_PAL45_R04_0_Msk                                   (0x1fUL << LCD_PAL45_R04_0_Pos)                           /*!< LCD PAL45: R04_0 Mask               */
-#define LCD_PAL45_G04_0_Pos                                   5                                                         /*!< LCD PAL45: G04_0 Position           */
-#define LCD_PAL45_G04_0_Msk                                   (0x1fUL << LCD_PAL45_G04_0_Pos)                           /*!< LCD PAL45: G04_0 Mask               */
-#define LCD_PAL45_B04_0_Pos                                   10                                                        /*!< LCD PAL45: B04_0 Position           */
-#define LCD_PAL45_B04_0_Msk                                   (0x1fUL << LCD_PAL45_B04_0_Pos)                           /*!< LCD PAL45: B04_0 Mask               */
-#define LCD_PAL45_I0_Pos                                      15                                                        /*!< LCD PAL45: I0 Position              */
-#define LCD_PAL45_I0_Msk                                      (0x01UL << LCD_PAL45_I0_Pos)                              /*!< LCD PAL45: I0 Mask                  */
-#define LCD_PAL45_R14_0_Pos                                   16                                                        /*!< LCD PAL45: R14_0 Position           */
-#define LCD_PAL45_R14_0_Msk                                   (0x1fUL << LCD_PAL45_R14_0_Pos)                           /*!< LCD PAL45: R14_0 Mask               */
-#define LCD_PAL45_G14_0_Pos                                   21                                                        /*!< LCD PAL45: G14_0 Position           */
-#define LCD_PAL45_G14_0_Msk                                   (0x1fUL << LCD_PAL45_G14_0_Pos)                           /*!< LCD PAL45: G14_0 Mask               */
-#define LCD_PAL45_B14_0_Pos                                   26                                                        /*!< LCD PAL45: B14_0 Position           */
-#define LCD_PAL45_B14_0_Msk                                   (0x1fUL << LCD_PAL45_B14_0_Pos)                           /*!< LCD PAL45: B14_0 Mask               */
-#define LCD_PAL45_I1_Pos                                      31                                                        /*!< LCD PAL45: I1 Position              */
-#define LCD_PAL45_I1_Msk                                      (0x01UL << LCD_PAL45_I1_Pos)                              /*!< LCD PAL45: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL46  -------------------------------------------
-#define LCD_PAL46_R04_0_Pos                                   0                                                         /*!< LCD PAL46: R04_0 Position           */
-#define LCD_PAL46_R04_0_Msk                                   (0x1fUL << LCD_PAL46_R04_0_Pos)                           /*!< LCD PAL46: R04_0 Mask               */
-#define LCD_PAL46_G04_0_Pos                                   5                                                         /*!< LCD PAL46: G04_0 Position           */
-#define LCD_PAL46_G04_0_Msk                                   (0x1fUL << LCD_PAL46_G04_0_Pos)                           /*!< LCD PAL46: G04_0 Mask               */
-#define LCD_PAL46_B04_0_Pos                                   10                                                        /*!< LCD PAL46: B04_0 Position           */
-#define LCD_PAL46_B04_0_Msk                                   (0x1fUL << LCD_PAL46_B04_0_Pos)                           /*!< LCD PAL46: B04_0 Mask               */
-#define LCD_PAL46_I0_Pos                                      15                                                        /*!< LCD PAL46: I0 Position              */
-#define LCD_PAL46_I0_Msk                                      (0x01UL << LCD_PAL46_I0_Pos)                              /*!< LCD PAL46: I0 Mask                  */
-#define LCD_PAL46_R14_0_Pos                                   16                                                        /*!< LCD PAL46: R14_0 Position           */
-#define LCD_PAL46_R14_0_Msk                                   (0x1fUL << LCD_PAL46_R14_0_Pos)                           /*!< LCD PAL46: R14_0 Mask               */
-#define LCD_PAL46_G14_0_Pos                                   21                                                        /*!< LCD PAL46: G14_0 Position           */
-#define LCD_PAL46_G14_0_Msk                                   (0x1fUL << LCD_PAL46_G14_0_Pos)                           /*!< LCD PAL46: G14_0 Mask               */
-#define LCD_PAL46_B14_0_Pos                                   26                                                        /*!< LCD PAL46: B14_0 Position           */
-#define LCD_PAL46_B14_0_Msk                                   (0x1fUL << LCD_PAL46_B14_0_Pos)                           /*!< LCD PAL46: B14_0 Mask               */
-#define LCD_PAL46_I1_Pos                                      31                                                        /*!< LCD PAL46: I1 Position              */
-#define LCD_PAL46_I1_Msk                                      (0x01UL << LCD_PAL46_I1_Pos)                              /*!< LCD PAL46: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL47  -------------------------------------------
-#define LCD_PAL47_R04_0_Pos                                   0                                                         /*!< LCD PAL47: R04_0 Position           */
-#define LCD_PAL47_R04_0_Msk                                   (0x1fUL << LCD_PAL47_R04_0_Pos)                           /*!< LCD PAL47: R04_0 Mask               */
-#define LCD_PAL47_G04_0_Pos                                   5                                                         /*!< LCD PAL47: G04_0 Position           */
-#define LCD_PAL47_G04_0_Msk                                   (0x1fUL << LCD_PAL47_G04_0_Pos)                           /*!< LCD PAL47: G04_0 Mask               */
-#define LCD_PAL47_B04_0_Pos                                   10                                                        /*!< LCD PAL47: B04_0 Position           */
-#define LCD_PAL47_B04_0_Msk                                   (0x1fUL << LCD_PAL47_B04_0_Pos)                           /*!< LCD PAL47: B04_0 Mask               */
-#define LCD_PAL47_I0_Pos                                      15                                                        /*!< LCD PAL47: I0 Position              */
-#define LCD_PAL47_I0_Msk                                      (0x01UL << LCD_PAL47_I0_Pos)                              /*!< LCD PAL47: I0 Mask                  */
-#define LCD_PAL47_R14_0_Pos                                   16                                                        /*!< LCD PAL47: R14_0 Position           */
-#define LCD_PAL47_R14_0_Msk                                   (0x1fUL << LCD_PAL47_R14_0_Pos)                           /*!< LCD PAL47: R14_0 Mask               */
-#define LCD_PAL47_G14_0_Pos                                   21                                                        /*!< LCD PAL47: G14_0 Position           */
-#define LCD_PAL47_G14_0_Msk                                   (0x1fUL << LCD_PAL47_G14_0_Pos)                           /*!< LCD PAL47: G14_0 Mask               */
-#define LCD_PAL47_B14_0_Pos                                   26                                                        /*!< LCD PAL47: B14_0 Position           */
-#define LCD_PAL47_B14_0_Msk                                   (0x1fUL << LCD_PAL47_B14_0_Pos)                           /*!< LCD PAL47: B14_0 Mask               */
-#define LCD_PAL47_I1_Pos                                      31                                                        /*!< LCD PAL47: I1 Position              */
-#define LCD_PAL47_I1_Msk                                      (0x01UL << LCD_PAL47_I1_Pos)                              /*!< LCD PAL47: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL48  -------------------------------------------
-#define LCD_PAL48_R04_0_Pos                                   0                                                         /*!< LCD PAL48: R04_0 Position           */
-#define LCD_PAL48_R04_0_Msk                                   (0x1fUL << LCD_PAL48_R04_0_Pos)                           /*!< LCD PAL48: R04_0 Mask               */
-#define LCD_PAL48_G04_0_Pos                                   5                                                         /*!< LCD PAL48: G04_0 Position           */
-#define LCD_PAL48_G04_0_Msk                                   (0x1fUL << LCD_PAL48_G04_0_Pos)                           /*!< LCD PAL48: G04_0 Mask               */
-#define LCD_PAL48_B04_0_Pos                                   10                                                        /*!< LCD PAL48: B04_0 Position           */
-#define LCD_PAL48_B04_0_Msk                                   (0x1fUL << LCD_PAL48_B04_0_Pos)                           /*!< LCD PAL48: B04_0 Mask               */
-#define LCD_PAL48_I0_Pos                                      15                                                        /*!< LCD PAL48: I0 Position              */
-#define LCD_PAL48_I0_Msk                                      (0x01UL << LCD_PAL48_I0_Pos)                              /*!< LCD PAL48: I0 Mask                  */
-#define LCD_PAL48_R14_0_Pos                                   16                                                        /*!< LCD PAL48: R14_0 Position           */
-#define LCD_PAL48_R14_0_Msk                                   (0x1fUL << LCD_PAL48_R14_0_Pos)                           /*!< LCD PAL48: R14_0 Mask               */
-#define LCD_PAL48_G14_0_Pos                                   21                                                        /*!< LCD PAL48: G14_0 Position           */
-#define LCD_PAL48_G14_0_Msk                                   (0x1fUL << LCD_PAL48_G14_0_Pos)                           /*!< LCD PAL48: G14_0 Mask               */
-#define LCD_PAL48_B14_0_Pos                                   26                                                        /*!< LCD PAL48: B14_0 Position           */
-#define LCD_PAL48_B14_0_Msk                                   (0x1fUL << LCD_PAL48_B14_0_Pos)                           /*!< LCD PAL48: B14_0 Mask               */
-#define LCD_PAL48_I1_Pos                                      31                                                        /*!< LCD PAL48: I1 Position              */
-#define LCD_PAL48_I1_Msk                                      (0x01UL << LCD_PAL48_I1_Pos)                              /*!< LCD PAL48: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL49  -------------------------------------------
-#define LCD_PAL49_R04_0_Pos                                   0                                                         /*!< LCD PAL49: R04_0 Position           */
-#define LCD_PAL49_R04_0_Msk                                   (0x1fUL << LCD_PAL49_R04_0_Pos)                           /*!< LCD PAL49: R04_0 Mask               */
-#define LCD_PAL49_G04_0_Pos                                   5                                                         /*!< LCD PAL49: G04_0 Position           */
-#define LCD_PAL49_G04_0_Msk                                   (0x1fUL << LCD_PAL49_G04_0_Pos)                           /*!< LCD PAL49: G04_0 Mask               */
-#define LCD_PAL49_B04_0_Pos                                   10                                                        /*!< LCD PAL49: B04_0 Position           */
-#define LCD_PAL49_B04_0_Msk                                   (0x1fUL << LCD_PAL49_B04_0_Pos)                           /*!< LCD PAL49: B04_0 Mask               */
-#define LCD_PAL49_I0_Pos                                      15                                                        /*!< LCD PAL49: I0 Position              */
-#define LCD_PAL49_I0_Msk                                      (0x01UL << LCD_PAL49_I0_Pos)                              /*!< LCD PAL49: I0 Mask                  */
-#define LCD_PAL49_R14_0_Pos                                   16                                                        /*!< LCD PAL49: R14_0 Position           */
-#define LCD_PAL49_R14_0_Msk                                   (0x1fUL << LCD_PAL49_R14_0_Pos)                           /*!< LCD PAL49: R14_0 Mask               */
-#define LCD_PAL49_G14_0_Pos                                   21                                                        /*!< LCD PAL49: G14_0 Position           */
-#define LCD_PAL49_G14_0_Msk                                   (0x1fUL << LCD_PAL49_G14_0_Pos)                           /*!< LCD PAL49: G14_0 Mask               */
-#define LCD_PAL49_B14_0_Pos                                   26                                                        /*!< LCD PAL49: B14_0 Position           */
-#define LCD_PAL49_B14_0_Msk                                   (0x1fUL << LCD_PAL49_B14_0_Pos)                           /*!< LCD PAL49: B14_0 Mask               */
-#define LCD_PAL49_I1_Pos                                      31                                                        /*!< LCD PAL49: I1 Position              */
-#define LCD_PAL49_I1_Msk                                      (0x01UL << LCD_PAL49_I1_Pos)                              /*!< LCD PAL49: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL50  -------------------------------------------
-#define LCD_PAL50_R04_0_Pos                                   0                                                         /*!< LCD PAL50: R04_0 Position           */
-#define LCD_PAL50_R04_0_Msk                                   (0x1fUL << LCD_PAL50_R04_0_Pos)                           /*!< LCD PAL50: R04_0 Mask               */
-#define LCD_PAL50_G04_0_Pos                                   5                                                         /*!< LCD PAL50: G04_0 Position           */
-#define LCD_PAL50_G04_0_Msk                                   (0x1fUL << LCD_PAL50_G04_0_Pos)                           /*!< LCD PAL50: G04_0 Mask               */
-#define LCD_PAL50_B04_0_Pos                                   10                                                        /*!< LCD PAL50: B04_0 Position           */
-#define LCD_PAL50_B04_0_Msk                                   (0x1fUL << LCD_PAL50_B04_0_Pos)                           /*!< LCD PAL50: B04_0 Mask               */
-#define LCD_PAL50_I0_Pos                                      15                                                        /*!< LCD PAL50: I0 Position              */
-#define LCD_PAL50_I0_Msk                                      (0x01UL << LCD_PAL50_I0_Pos)                              /*!< LCD PAL50: I0 Mask                  */
-#define LCD_PAL50_R14_0_Pos                                   16                                                        /*!< LCD PAL50: R14_0 Position           */
-#define LCD_PAL50_R14_0_Msk                                   (0x1fUL << LCD_PAL50_R14_0_Pos)                           /*!< LCD PAL50: R14_0 Mask               */
-#define LCD_PAL50_G14_0_Pos                                   21                                                        /*!< LCD PAL50: G14_0 Position           */
-#define LCD_PAL50_G14_0_Msk                                   (0x1fUL << LCD_PAL50_G14_0_Pos)                           /*!< LCD PAL50: G14_0 Mask               */
-#define LCD_PAL50_B14_0_Pos                                   26                                                        /*!< LCD PAL50: B14_0 Position           */
-#define LCD_PAL50_B14_0_Msk                                   (0x1fUL << LCD_PAL50_B14_0_Pos)                           /*!< LCD PAL50: B14_0 Mask               */
-#define LCD_PAL50_I1_Pos                                      31                                                        /*!< LCD PAL50: I1 Position              */
-#define LCD_PAL50_I1_Msk                                      (0x01UL << LCD_PAL50_I1_Pos)                              /*!< LCD PAL50: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL51  -------------------------------------------
-#define LCD_PAL51_R04_0_Pos                                   0                                                         /*!< LCD PAL51: R04_0 Position           */
-#define LCD_PAL51_R04_0_Msk                                   (0x1fUL << LCD_PAL51_R04_0_Pos)                           /*!< LCD PAL51: R04_0 Mask               */
-#define LCD_PAL51_G04_0_Pos                                   5                                                         /*!< LCD PAL51: G04_0 Position           */
-#define LCD_PAL51_G04_0_Msk                                   (0x1fUL << LCD_PAL51_G04_0_Pos)                           /*!< LCD PAL51: G04_0 Mask               */
-#define LCD_PAL51_B04_0_Pos                                   10                                                        /*!< LCD PAL51: B04_0 Position           */
-#define LCD_PAL51_B04_0_Msk                                   (0x1fUL << LCD_PAL51_B04_0_Pos)                           /*!< LCD PAL51: B04_0 Mask               */
-#define LCD_PAL51_I0_Pos                                      15                                                        /*!< LCD PAL51: I0 Position              */
-#define LCD_PAL51_I0_Msk                                      (0x01UL << LCD_PAL51_I0_Pos)                              /*!< LCD PAL51: I0 Mask                  */
-#define LCD_PAL51_R14_0_Pos                                   16                                                        /*!< LCD PAL51: R14_0 Position           */
-#define LCD_PAL51_R14_0_Msk                                   (0x1fUL << LCD_PAL51_R14_0_Pos)                           /*!< LCD PAL51: R14_0 Mask               */
-#define LCD_PAL51_G14_0_Pos                                   21                                                        /*!< LCD PAL51: G14_0 Position           */
-#define LCD_PAL51_G14_0_Msk                                   (0x1fUL << LCD_PAL51_G14_0_Pos)                           /*!< LCD PAL51: G14_0 Mask               */
-#define LCD_PAL51_B14_0_Pos                                   26                                                        /*!< LCD PAL51: B14_0 Position           */
-#define LCD_PAL51_B14_0_Msk                                   (0x1fUL << LCD_PAL51_B14_0_Pos)                           /*!< LCD PAL51: B14_0 Mask               */
-#define LCD_PAL51_I1_Pos                                      31                                                        /*!< LCD PAL51: I1 Position              */
-#define LCD_PAL51_I1_Msk                                      (0x01UL << LCD_PAL51_I1_Pos)                              /*!< LCD PAL51: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL52  -------------------------------------------
-#define LCD_PAL52_R04_0_Pos                                   0                                                         /*!< LCD PAL52: R04_0 Position           */
-#define LCD_PAL52_R04_0_Msk                                   (0x1fUL << LCD_PAL52_R04_0_Pos)                           /*!< LCD PAL52: R04_0 Mask               */
-#define LCD_PAL52_G04_0_Pos                                   5                                                         /*!< LCD PAL52: G04_0 Position           */
-#define LCD_PAL52_G04_0_Msk                                   (0x1fUL << LCD_PAL52_G04_0_Pos)                           /*!< LCD PAL52: G04_0 Mask               */
-#define LCD_PAL52_B04_0_Pos                                   10                                                        /*!< LCD PAL52: B04_0 Position           */
-#define LCD_PAL52_B04_0_Msk                                   (0x1fUL << LCD_PAL52_B04_0_Pos)                           /*!< LCD PAL52: B04_0 Mask               */
-#define LCD_PAL52_I0_Pos                                      15                                                        /*!< LCD PAL52: I0 Position              */
-#define LCD_PAL52_I0_Msk                                      (0x01UL << LCD_PAL52_I0_Pos)                              /*!< LCD PAL52: I0 Mask                  */
-#define LCD_PAL52_R14_0_Pos                                   16                                                        /*!< LCD PAL52: R14_0 Position           */
-#define LCD_PAL52_R14_0_Msk                                   (0x1fUL << LCD_PAL52_R14_0_Pos)                           /*!< LCD PAL52: R14_0 Mask               */
-#define LCD_PAL52_G14_0_Pos                                   21                                                        /*!< LCD PAL52: G14_0 Position           */
-#define LCD_PAL52_G14_0_Msk                                   (0x1fUL << LCD_PAL52_G14_0_Pos)                           /*!< LCD PAL52: G14_0 Mask               */
-#define LCD_PAL52_B14_0_Pos                                   26                                                        /*!< LCD PAL52: B14_0 Position           */
-#define LCD_PAL52_B14_0_Msk                                   (0x1fUL << LCD_PAL52_B14_0_Pos)                           /*!< LCD PAL52: B14_0 Mask               */
-#define LCD_PAL52_I1_Pos                                      31                                                        /*!< LCD PAL52: I1 Position              */
-#define LCD_PAL52_I1_Msk                                      (0x01UL << LCD_PAL52_I1_Pos)                              /*!< LCD PAL52: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL53  -------------------------------------------
-#define LCD_PAL53_R04_0_Pos                                   0                                                         /*!< LCD PAL53: R04_0 Position           */
-#define LCD_PAL53_R04_0_Msk                                   (0x1fUL << LCD_PAL53_R04_0_Pos)                           /*!< LCD PAL53: R04_0 Mask               */
-#define LCD_PAL53_G04_0_Pos                                   5                                                         /*!< LCD PAL53: G04_0 Position           */
-#define LCD_PAL53_G04_0_Msk                                   (0x1fUL << LCD_PAL53_G04_0_Pos)                           /*!< LCD PAL53: G04_0 Mask               */
-#define LCD_PAL53_B04_0_Pos                                   10                                                        /*!< LCD PAL53: B04_0 Position           */
-#define LCD_PAL53_B04_0_Msk                                   (0x1fUL << LCD_PAL53_B04_0_Pos)                           /*!< LCD PAL53: B04_0 Mask               */
-#define LCD_PAL53_I0_Pos                                      15                                                        /*!< LCD PAL53: I0 Position              */
-#define LCD_PAL53_I0_Msk                                      (0x01UL << LCD_PAL53_I0_Pos)                              /*!< LCD PAL53: I0 Mask                  */
-#define LCD_PAL53_R14_0_Pos                                   16                                                        /*!< LCD PAL53: R14_0 Position           */
-#define LCD_PAL53_R14_0_Msk                                   (0x1fUL << LCD_PAL53_R14_0_Pos)                           /*!< LCD PAL53: R14_0 Mask               */
-#define LCD_PAL53_G14_0_Pos                                   21                                                        /*!< LCD PAL53: G14_0 Position           */
-#define LCD_PAL53_G14_0_Msk                                   (0x1fUL << LCD_PAL53_G14_0_Pos)                           /*!< LCD PAL53: G14_0 Mask               */
-#define LCD_PAL53_B14_0_Pos                                   26                                                        /*!< LCD PAL53: B14_0 Position           */
-#define LCD_PAL53_B14_0_Msk                                   (0x1fUL << LCD_PAL53_B14_0_Pos)                           /*!< LCD PAL53: B14_0 Mask               */
-#define LCD_PAL53_I1_Pos                                      31                                                        /*!< LCD PAL53: I1 Position              */
-#define LCD_PAL53_I1_Msk                                      (0x01UL << LCD_PAL53_I1_Pos)                              /*!< LCD PAL53: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL54  -------------------------------------------
-#define LCD_PAL54_R04_0_Pos                                   0                                                         /*!< LCD PAL54: R04_0 Position           */
-#define LCD_PAL54_R04_0_Msk                                   (0x1fUL << LCD_PAL54_R04_0_Pos)                           /*!< LCD PAL54: R04_0 Mask               */
-#define LCD_PAL54_G04_0_Pos                                   5                                                         /*!< LCD PAL54: G04_0 Position           */
-#define LCD_PAL54_G04_0_Msk                                   (0x1fUL << LCD_PAL54_G04_0_Pos)                           /*!< LCD PAL54: G04_0 Mask               */
-#define LCD_PAL54_B04_0_Pos                                   10                                                        /*!< LCD PAL54: B04_0 Position           */
-#define LCD_PAL54_B04_0_Msk                                   (0x1fUL << LCD_PAL54_B04_0_Pos)                           /*!< LCD PAL54: B04_0 Mask               */
-#define LCD_PAL54_I0_Pos                                      15                                                        /*!< LCD PAL54: I0 Position              */
-#define LCD_PAL54_I0_Msk                                      (0x01UL << LCD_PAL54_I0_Pos)                              /*!< LCD PAL54: I0 Mask                  */
-#define LCD_PAL54_R14_0_Pos                                   16                                                        /*!< LCD PAL54: R14_0 Position           */
-#define LCD_PAL54_R14_0_Msk                                   (0x1fUL << LCD_PAL54_R14_0_Pos)                           /*!< LCD PAL54: R14_0 Mask               */
-#define LCD_PAL54_G14_0_Pos                                   21                                                        /*!< LCD PAL54: G14_0 Position           */
-#define LCD_PAL54_G14_0_Msk                                   (0x1fUL << LCD_PAL54_G14_0_Pos)                           /*!< LCD PAL54: G14_0 Mask               */
-#define LCD_PAL54_B14_0_Pos                                   26                                                        /*!< LCD PAL54: B14_0 Position           */
-#define LCD_PAL54_B14_0_Msk                                   (0x1fUL << LCD_PAL54_B14_0_Pos)                           /*!< LCD PAL54: B14_0 Mask               */
-#define LCD_PAL54_I1_Pos                                      31                                                        /*!< LCD PAL54: I1 Position              */
-#define LCD_PAL54_I1_Msk                                      (0x01UL << LCD_PAL54_I1_Pos)                              /*!< LCD PAL54: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL55  -------------------------------------------
-#define LCD_PAL55_R04_0_Pos                                   0                                                         /*!< LCD PAL55: R04_0 Position           */
-#define LCD_PAL55_R04_0_Msk                                   (0x1fUL << LCD_PAL55_R04_0_Pos)                           /*!< LCD PAL55: R04_0 Mask               */
-#define LCD_PAL55_G04_0_Pos                                   5                                                         /*!< LCD PAL55: G04_0 Position           */
-#define LCD_PAL55_G04_0_Msk                                   (0x1fUL << LCD_PAL55_G04_0_Pos)                           /*!< LCD PAL55: G04_0 Mask               */
-#define LCD_PAL55_B04_0_Pos                                   10                                                        /*!< LCD PAL55: B04_0 Position           */
-#define LCD_PAL55_B04_0_Msk                                   (0x1fUL << LCD_PAL55_B04_0_Pos)                           /*!< LCD PAL55: B04_0 Mask               */
-#define LCD_PAL55_I0_Pos                                      15                                                        /*!< LCD PAL55: I0 Position              */
-#define LCD_PAL55_I0_Msk                                      (0x01UL << LCD_PAL55_I0_Pos)                              /*!< LCD PAL55: I0 Mask                  */
-#define LCD_PAL55_R14_0_Pos                                   16                                                        /*!< LCD PAL55: R14_0 Position           */
-#define LCD_PAL55_R14_0_Msk                                   (0x1fUL << LCD_PAL55_R14_0_Pos)                           /*!< LCD PAL55: R14_0 Mask               */
-#define LCD_PAL55_G14_0_Pos                                   21                                                        /*!< LCD PAL55: G14_0 Position           */
-#define LCD_PAL55_G14_0_Msk                                   (0x1fUL << LCD_PAL55_G14_0_Pos)                           /*!< LCD PAL55: G14_0 Mask               */
-#define LCD_PAL55_B14_0_Pos                                   26                                                        /*!< LCD PAL55: B14_0 Position           */
-#define LCD_PAL55_B14_0_Msk                                   (0x1fUL << LCD_PAL55_B14_0_Pos)                           /*!< LCD PAL55: B14_0 Mask               */
-#define LCD_PAL55_I1_Pos                                      31                                                        /*!< LCD PAL55: I1 Position              */
-#define LCD_PAL55_I1_Msk                                      (0x01UL << LCD_PAL55_I1_Pos)                              /*!< LCD PAL55: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL56  -------------------------------------------
-#define LCD_PAL56_R04_0_Pos                                   0                                                         /*!< LCD PAL56: R04_0 Position           */
-#define LCD_PAL56_R04_0_Msk                                   (0x1fUL << LCD_PAL56_R04_0_Pos)                           /*!< LCD PAL56: R04_0 Mask               */
-#define LCD_PAL56_G04_0_Pos                                   5                                                         /*!< LCD PAL56: G04_0 Position           */
-#define LCD_PAL56_G04_0_Msk                                   (0x1fUL << LCD_PAL56_G04_0_Pos)                           /*!< LCD PAL56: G04_0 Mask               */
-#define LCD_PAL56_B04_0_Pos                                   10                                                        /*!< LCD PAL56: B04_0 Position           */
-#define LCD_PAL56_B04_0_Msk                                   (0x1fUL << LCD_PAL56_B04_0_Pos)                           /*!< LCD PAL56: B04_0 Mask               */
-#define LCD_PAL56_I0_Pos                                      15                                                        /*!< LCD PAL56: I0 Position              */
-#define LCD_PAL56_I0_Msk                                      (0x01UL << LCD_PAL56_I0_Pos)                              /*!< LCD PAL56: I0 Mask                  */
-#define LCD_PAL56_R14_0_Pos                                   16                                                        /*!< LCD PAL56: R14_0 Position           */
-#define LCD_PAL56_R14_0_Msk                                   (0x1fUL << LCD_PAL56_R14_0_Pos)                           /*!< LCD PAL56: R14_0 Mask               */
-#define LCD_PAL56_G14_0_Pos                                   21                                                        /*!< LCD PAL56: G14_0 Position           */
-#define LCD_PAL56_G14_0_Msk                                   (0x1fUL << LCD_PAL56_G14_0_Pos)                           /*!< LCD PAL56: G14_0 Mask               */
-#define LCD_PAL56_B14_0_Pos                                   26                                                        /*!< LCD PAL56: B14_0 Position           */
-#define LCD_PAL56_B14_0_Msk                                   (0x1fUL << LCD_PAL56_B14_0_Pos)                           /*!< LCD PAL56: B14_0 Mask               */
-#define LCD_PAL56_I1_Pos                                      31                                                        /*!< LCD PAL56: I1 Position              */
-#define LCD_PAL56_I1_Msk                                      (0x01UL << LCD_PAL56_I1_Pos)                              /*!< LCD PAL56: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL57  -------------------------------------------
-#define LCD_PAL57_R04_0_Pos                                   0                                                         /*!< LCD PAL57: R04_0 Position           */
-#define LCD_PAL57_R04_0_Msk                                   (0x1fUL << LCD_PAL57_R04_0_Pos)                           /*!< LCD PAL57: R04_0 Mask               */
-#define LCD_PAL57_G04_0_Pos                                   5                                                         /*!< LCD PAL57: G04_0 Position           */
-#define LCD_PAL57_G04_0_Msk                                   (0x1fUL << LCD_PAL57_G04_0_Pos)                           /*!< LCD PAL57: G04_0 Mask               */
-#define LCD_PAL57_B04_0_Pos                                   10                                                        /*!< LCD PAL57: B04_0 Position           */
-#define LCD_PAL57_B04_0_Msk                                   (0x1fUL << LCD_PAL57_B04_0_Pos)                           /*!< LCD PAL57: B04_0 Mask               */
-#define LCD_PAL57_I0_Pos                                      15                                                        /*!< LCD PAL57: I0 Position              */
-#define LCD_PAL57_I0_Msk                                      (0x01UL << LCD_PAL57_I0_Pos)                              /*!< LCD PAL57: I0 Mask                  */
-#define LCD_PAL57_R14_0_Pos                                   16                                                        /*!< LCD PAL57: R14_0 Position           */
-#define LCD_PAL57_R14_0_Msk                                   (0x1fUL << LCD_PAL57_R14_0_Pos)                           /*!< LCD PAL57: R14_0 Mask               */
-#define LCD_PAL57_G14_0_Pos                                   21                                                        /*!< LCD PAL57: G14_0 Position           */
-#define LCD_PAL57_G14_0_Msk                                   (0x1fUL << LCD_PAL57_G14_0_Pos)                           /*!< LCD PAL57: G14_0 Mask               */
-#define LCD_PAL57_B14_0_Pos                                   26                                                        /*!< LCD PAL57: B14_0 Position           */
-#define LCD_PAL57_B14_0_Msk                                   (0x1fUL << LCD_PAL57_B14_0_Pos)                           /*!< LCD PAL57: B14_0 Mask               */
-#define LCD_PAL57_I1_Pos                                      31                                                        /*!< LCD PAL57: I1 Position              */
-#define LCD_PAL57_I1_Msk                                      (0x01UL << LCD_PAL57_I1_Pos)                              /*!< LCD PAL57: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL58  -------------------------------------------
-#define LCD_PAL58_R04_0_Pos                                   0                                                         /*!< LCD PAL58: R04_0 Position           */
-#define LCD_PAL58_R04_0_Msk                                   (0x1fUL << LCD_PAL58_R04_0_Pos)                           /*!< LCD PAL58: R04_0 Mask               */
-#define LCD_PAL58_G04_0_Pos                                   5                                                         /*!< LCD PAL58: G04_0 Position           */
-#define LCD_PAL58_G04_0_Msk                                   (0x1fUL << LCD_PAL58_G04_0_Pos)                           /*!< LCD PAL58: G04_0 Mask               */
-#define LCD_PAL58_B04_0_Pos                                   10                                                        /*!< LCD PAL58: B04_0 Position           */
-#define LCD_PAL58_B04_0_Msk                                   (0x1fUL << LCD_PAL58_B04_0_Pos)                           /*!< LCD PAL58: B04_0 Mask               */
-#define LCD_PAL58_I0_Pos                                      15                                                        /*!< LCD PAL58: I0 Position              */
-#define LCD_PAL58_I0_Msk                                      (0x01UL << LCD_PAL58_I0_Pos)                              /*!< LCD PAL58: I0 Mask                  */
-#define LCD_PAL58_R14_0_Pos                                   16                                                        /*!< LCD PAL58: R14_0 Position           */
-#define LCD_PAL58_R14_0_Msk                                   (0x1fUL << LCD_PAL58_R14_0_Pos)                           /*!< LCD PAL58: R14_0 Mask               */
-#define LCD_PAL58_G14_0_Pos                                   21                                                        /*!< LCD PAL58: G14_0 Position           */
-#define LCD_PAL58_G14_0_Msk                                   (0x1fUL << LCD_PAL58_G14_0_Pos)                           /*!< LCD PAL58: G14_0 Mask               */
-#define LCD_PAL58_B14_0_Pos                                   26                                                        /*!< LCD PAL58: B14_0 Position           */
-#define LCD_PAL58_B14_0_Msk                                   (0x1fUL << LCD_PAL58_B14_0_Pos)                           /*!< LCD PAL58: B14_0 Mask               */
-#define LCD_PAL58_I1_Pos                                      31                                                        /*!< LCD PAL58: I1 Position              */
-#define LCD_PAL58_I1_Msk                                      (0x01UL << LCD_PAL58_I1_Pos)                              /*!< LCD PAL58: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL59  -------------------------------------------
-#define LCD_PAL59_R04_0_Pos                                   0                                                         /*!< LCD PAL59: R04_0 Position           */
-#define LCD_PAL59_R04_0_Msk                                   (0x1fUL << LCD_PAL59_R04_0_Pos)                           /*!< LCD PAL59: R04_0 Mask               */
-#define LCD_PAL59_G04_0_Pos                                   5                                                         /*!< LCD PAL59: G04_0 Position           */
-#define LCD_PAL59_G04_0_Msk                                   (0x1fUL << LCD_PAL59_G04_0_Pos)                           /*!< LCD PAL59: G04_0 Mask               */
-#define LCD_PAL59_B04_0_Pos                                   10                                                        /*!< LCD PAL59: B04_0 Position           */
-#define LCD_PAL59_B04_0_Msk                                   (0x1fUL << LCD_PAL59_B04_0_Pos)                           /*!< LCD PAL59: B04_0 Mask               */
-#define LCD_PAL59_I0_Pos                                      15                                                        /*!< LCD PAL59: I0 Position              */
-#define LCD_PAL59_I0_Msk                                      (0x01UL << LCD_PAL59_I0_Pos)                              /*!< LCD PAL59: I0 Mask                  */
-#define LCD_PAL59_R14_0_Pos                                   16                                                        /*!< LCD PAL59: R14_0 Position           */
-#define LCD_PAL59_R14_0_Msk                                   (0x1fUL << LCD_PAL59_R14_0_Pos)                           /*!< LCD PAL59: R14_0 Mask               */
-#define LCD_PAL59_G14_0_Pos                                   21                                                        /*!< LCD PAL59: G14_0 Position           */
-#define LCD_PAL59_G14_0_Msk                                   (0x1fUL << LCD_PAL59_G14_0_Pos)                           /*!< LCD PAL59: G14_0 Mask               */
-#define LCD_PAL59_B14_0_Pos                                   26                                                        /*!< LCD PAL59: B14_0 Position           */
-#define LCD_PAL59_B14_0_Msk                                   (0x1fUL << LCD_PAL59_B14_0_Pos)                           /*!< LCD PAL59: B14_0 Mask               */
-#define LCD_PAL59_I1_Pos                                      31                                                        /*!< LCD PAL59: I1 Position              */
-#define LCD_PAL59_I1_Msk                                      (0x01UL << LCD_PAL59_I1_Pos)                              /*!< LCD PAL59: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL60  -------------------------------------------
-#define LCD_PAL60_R04_0_Pos                                   0                                                         /*!< LCD PAL60: R04_0 Position           */
-#define LCD_PAL60_R04_0_Msk                                   (0x1fUL << LCD_PAL60_R04_0_Pos)                           /*!< LCD PAL60: R04_0 Mask               */
-#define LCD_PAL60_G04_0_Pos                                   5                                                         /*!< LCD PAL60: G04_0 Position           */
-#define LCD_PAL60_G04_0_Msk                                   (0x1fUL << LCD_PAL60_G04_0_Pos)                           /*!< LCD PAL60: G04_0 Mask               */
-#define LCD_PAL60_B04_0_Pos                                   10                                                        /*!< LCD PAL60: B04_0 Position           */
-#define LCD_PAL60_B04_0_Msk                                   (0x1fUL << LCD_PAL60_B04_0_Pos)                           /*!< LCD PAL60: B04_0 Mask               */
-#define LCD_PAL60_I0_Pos                                      15                                                        /*!< LCD PAL60: I0 Position              */
-#define LCD_PAL60_I0_Msk                                      (0x01UL << LCD_PAL60_I0_Pos)                              /*!< LCD PAL60: I0 Mask                  */
-#define LCD_PAL60_R14_0_Pos                                   16                                                        /*!< LCD PAL60: R14_0 Position           */
-#define LCD_PAL60_R14_0_Msk                                   (0x1fUL << LCD_PAL60_R14_0_Pos)                           /*!< LCD PAL60: R14_0 Mask               */
-#define LCD_PAL60_G14_0_Pos                                   21                                                        /*!< LCD PAL60: G14_0 Position           */
-#define LCD_PAL60_G14_0_Msk                                   (0x1fUL << LCD_PAL60_G14_0_Pos)                           /*!< LCD PAL60: G14_0 Mask               */
-#define LCD_PAL60_B14_0_Pos                                   26                                                        /*!< LCD PAL60: B14_0 Position           */
-#define LCD_PAL60_B14_0_Msk                                   (0x1fUL << LCD_PAL60_B14_0_Pos)                           /*!< LCD PAL60: B14_0 Mask               */
-#define LCD_PAL60_I1_Pos                                      31                                                        /*!< LCD PAL60: I1 Position              */
-#define LCD_PAL60_I1_Msk                                      (0x01UL << LCD_PAL60_I1_Pos)                              /*!< LCD PAL60: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL61  -------------------------------------------
-#define LCD_PAL61_R04_0_Pos                                   0                                                         /*!< LCD PAL61: R04_0 Position           */
-#define LCD_PAL61_R04_0_Msk                                   (0x1fUL << LCD_PAL61_R04_0_Pos)                           /*!< LCD PAL61: R04_0 Mask               */
-#define LCD_PAL61_G04_0_Pos                                   5                                                         /*!< LCD PAL61: G04_0 Position           */
-#define LCD_PAL61_G04_0_Msk                                   (0x1fUL << LCD_PAL61_G04_0_Pos)                           /*!< LCD PAL61: G04_0 Mask               */
-#define LCD_PAL61_B04_0_Pos                                   10                                                        /*!< LCD PAL61: B04_0 Position           */
-#define LCD_PAL61_B04_0_Msk                                   (0x1fUL << LCD_PAL61_B04_0_Pos)                           /*!< LCD PAL61: B04_0 Mask               */
-#define LCD_PAL61_I0_Pos                                      15                                                        /*!< LCD PAL61: I0 Position              */
-#define LCD_PAL61_I0_Msk                                      (0x01UL << LCD_PAL61_I0_Pos)                              /*!< LCD PAL61: I0 Mask                  */
-#define LCD_PAL61_R14_0_Pos                                   16                                                        /*!< LCD PAL61: R14_0 Position           */
-#define LCD_PAL61_R14_0_Msk                                   (0x1fUL << LCD_PAL61_R14_0_Pos)                           /*!< LCD PAL61: R14_0 Mask               */
-#define LCD_PAL61_G14_0_Pos                                   21                                                        /*!< LCD PAL61: G14_0 Position           */
-#define LCD_PAL61_G14_0_Msk                                   (0x1fUL << LCD_PAL61_G14_0_Pos)                           /*!< LCD PAL61: G14_0 Mask               */
-#define LCD_PAL61_B14_0_Pos                                   26                                                        /*!< LCD PAL61: B14_0 Position           */
-#define LCD_PAL61_B14_0_Msk                                   (0x1fUL << LCD_PAL61_B14_0_Pos)                           /*!< LCD PAL61: B14_0 Mask               */
-#define LCD_PAL61_I1_Pos                                      31                                                        /*!< LCD PAL61: I1 Position              */
-#define LCD_PAL61_I1_Msk                                      (0x01UL << LCD_PAL61_I1_Pos)                              /*!< LCD PAL61: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL62  -------------------------------------------
-#define LCD_PAL62_R04_0_Pos                                   0                                                         /*!< LCD PAL62: R04_0 Position           */
-#define LCD_PAL62_R04_0_Msk                                   (0x1fUL << LCD_PAL62_R04_0_Pos)                           /*!< LCD PAL62: R04_0 Mask               */
-#define LCD_PAL62_G04_0_Pos                                   5                                                         /*!< LCD PAL62: G04_0 Position           */
-#define LCD_PAL62_G04_0_Msk                                   (0x1fUL << LCD_PAL62_G04_0_Pos)                           /*!< LCD PAL62: G04_0 Mask               */
-#define LCD_PAL62_B04_0_Pos                                   10                                                        /*!< LCD PAL62: B04_0 Position           */
-#define LCD_PAL62_B04_0_Msk                                   (0x1fUL << LCD_PAL62_B04_0_Pos)                           /*!< LCD PAL62: B04_0 Mask               */
-#define LCD_PAL62_I0_Pos                                      15                                                        /*!< LCD PAL62: I0 Position              */
-#define LCD_PAL62_I0_Msk                                      (0x01UL << LCD_PAL62_I0_Pos)                              /*!< LCD PAL62: I0 Mask                  */
-#define LCD_PAL62_R14_0_Pos                                   16                                                        /*!< LCD PAL62: R14_0 Position           */
-#define LCD_PAL62_R14_0_Msk                                   (0x1fUL << LCD_PAL62_R14_0_Pos)                           /*!< LCD PAL62: R14_0 Mask               */
-#define LCD_PAL62_G14_0_Pos                                   21                                                        /*!< LCD PAL62: G14_0 Position           */
-#define LCD_PAL62_G14_0_Msk                                   (0x1fUL << LCD_PAL62_G14_0_Pos)                           /*!< LCD PAL62: G14_0 Mask               */
-#define LCD_PAL62_B14_0_Pos                                   26                                                        /*!< LCD PAL62: B14_0 Position           */
-#define LCD_PAL62_B14_0_Msk                                   (0x1fUL << LCD_PAL62_B14_0_Pos)                           /*!< LCD PAL62: B14_0 Mask               */
-#define LCD_PAL62_I1_Pos                                      31                                                        /*!< LCD PAL62: I1 Position              */
-#define LCD_PAL62_I1_Msk                                      (0x01UL << LCD_PAL62_I1_Pos)                              /*!< LCD PAL62: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL63  -------------------------------------------
-#define LCD_PAL63_R04_0_Pos                                   0                                                         /*!< LCD PAL63: R04_0 Position           */
-#define LCD_PAL63_R04_0_Msk                                   (0x1fUL << LCD_PAL63_R04_0_Pos)                           /*!< LCD PAL63: R04_0 Mask               */
-#define LCD_PAL63_G04_0_Pos                                   5                                                         /*!< LCD PAL63: G04_0 Position           */
-#define LCD_PAL63_G04_0_Msk                                   (0x1fUL << LCD_PAL63_G04_0_Pos)                           /*!< LCD PAL63: G04_0 Mask               */
-#define LCD_PAL63_B04_0_Pos                                   10                                                        /*!< LCD PAL63: B04_0 Position           */
-#define LCD_PAL63_B04_0_Msk                                   (0x1fUL << LCD_PAL63_B04_0_Pos)                           /*!< LCD PAL63: B04_0 Mask               */
-#define LCD_PAL63_I0_Pos                                      15                                                        /*!< LCD PAL63: I0 Position              */
-#define LCD_PAL63_I0_Msk                                      (0x01UL << LCD_PAL63_I0_Pos)                              /*!< LCD PAL63: I0 Mask                  */
-#define LCD_PAL63_R14_0_Pos                                   16                                                        /*!< LCD PAL63: R14_0 Position           */
-#define LCD_PAL63_R14_0_Msk                                   (0x1fUL << LCD_PAL63_R14_0_Pos)                           /*!< LCD PAL63: R14_0 Mask               */
-#define LCD_PAL63_G14_0_Pos                                   21                                                        /*!< LCD PAL63: G14_0 Position           */
-#define LCD_PAL63_G14_0_Msk                                   (0x1fUL << LCD_PAL63_G14_0_Pos)                           /*!< LCD PAL63: G14_0 Mask               */
-#define LCD_PAL63_B14_0_Pos                                   26                                                        /*!< LCD PAL63: B14_0 Position           */
-#define LCD_PAL63_B14_0_Msk                                   (0x1fUL << LCD_PAL63_B14_0_Pos)                           /*!< LCD PAL63: B14_0 Mask               */
-#define LCD_PAL63_I1_Pos                                      31                                                        /*!< LCD PAL63: I1 Position              */
-#define LCD_PAL63_I1_Msk                                      (0x01UL << LCD_PAL63_I1_Pos)                              /*!< LCD PAL63: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL64  -------------------------------------------
-#define LCD_PAL64_R04_0_Pos                                   0                                                         /*!< LCD PAL64: R04_0 Position           */
-#define LCD_PAL64_R04_0_Msk                                   (0x1fUL << LCD_PAL64_R04_0_Pos)                           /*!< LCD PAL64: R04_0 Mask               */
-#define LCD_PAL64_G04_0_Pos                                   5                                                         /*!< LCD PAL64: G04_0 Position           */
-#define LCD_PAL64_G04_0_Msk                                   (0x1fUL << LCD_PAL64_G04_0_Pos)                           /*!< LCD PAL64: G04_0 Mask               */
-#define LCD_PAL64_B04_0_Pos                                   10                                                        /*!< LCD PAL64: B04_0 Position           */
-#define LCD_PAL64_B04_0_Msk                                   (0x1fUL << LCD_PAL64_B04_0_Pos)                           /*!< LCD PAL64: B04_0 Mask               */
-#define LCD_PAL64_I0_Pos                                      15                                                        /*!< LCD PAL64: I0 Position              */
-#define LCD_PAL64_I0_Msk                                      (0x01UL << LCD_PAL64_I0_Pos)                              /*!< LCD PAL64: I0 Mask                  */
-#define LCD_PAL64_R14_0_Pos                                   16                                                        /*!< LCD PAL64: R14_0 Position           */
-#define LCD_PAL64_R14_0_Msk                                   (0x1fUL << LCD_PAL64_R14_0_Pos)                           /*!< LCD PAL64: R14_0 Mask               */
-#define LCD_PAL64_G14_0_Pos                                   21                                                        /*!< LCD PAL64: G14_0 Position           */
-#define LCD_PAL64_G14_0_Msk                                   (0x1fUL << LCD_PAL64_G14_0_Pos)                           /*!< LCD PAL64: G14_0 Mask               */
-#define LCD_PAL64_B14_0_Pos                                   26                                                        /*!< LCD PAL64: B14_0 Position           */
-#define LCD_PAL64_B14_0_Msk                                   (0x1fUL << LCD_PAL64_B14_0_Pos)                           /*!< LCD PAL64: B14_0 Mask               */
-#define LCD_PAL64_I1_Pos                                      31                                                        /*!< LCD PAL64: I1 Position              */
-#define LCD_PAL64_I1_Msk                                      (0x01UL << LCD_PAL64_I1_Pos)                              /*!< LCD PAL64: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL65  -------------------------------------------
-#define LCD_PAL65_R04_0_Pos                                   0                                                         /*!< LCD PAL65: R04_0 Position           */
-#define LCD_PAL65_R04_0_Msk                                   (0x1fUL << LCD_PAL65_R04_0_Pos)                           /*!< LCD PAL65: R04_0 Mask               */
-#define LCD_PAL65_G04_0_Pos                                   5                                                         /*!< LCD PAL65: G04_0 Position           */
-#define LCD_PAL65_G04_0_Msk                                   (0x1fUL << LCD_PAL65_G04_0_Pos)                           /*!< LCD PAL65: G04_0 Mask               */
-#define LCD_PAL65_B04_0_Pos                                   10                                                        /*!< LCD PAL65: B04_0 Position           */
-#define LCD_PAL65_B04_0_Msk                                   (0x1fUL << LCD_PAL65_B04_0_Pos)                           /*!< LCD PAL65: B04_0 Mask               */
-#define LCD_PAL65_I0_Pos                                      15                                                        /*!< LCD PAL65: I0 Position              */
-#define LCD_PAL65_I0_Msk                                      (0x01UL << LCD_PAL65_I0_Pos)                              /*!< LCD PAL65: I0 Mask                  */
-#define LCD_PAL65_R14_0_Pos                                   16                                                        /*!< LCD PAL65: R14_0 Position           */
-#define LCD_PAL65_R14_0_Msk                                   (0x1fUL << LCD_PAL65_R14_0_Pos)                           /*!< LCD PAL65: R14_0 Mask               */
-#define LCD_PAL65_G14_0_Pos                                   21                                                        /*!< LCD PAL65: G14_0 Position           */
-#define LCD_PAL65_G14_0_Msk                                   (0x1fUL << LCD_PAL65_G14_0_Pos)                           /*!< LCD PAL65: G14_0 Mask               */
-#define LCD_PAL65_B14_0_Pos                                   26                                                        /*!< LCD PAL65: B14_0 Position           */
-#define LCD_PAL65_B14_0_Msk                                   (0x1fUL << LCD_PAL65_B14_0_Pos)                           /*!< LCD PAL65: B14_0 Mask               */
-#define LCD_PAL65_I1_Pos                                      31                                                        /*!< LCD PAL65: I1 Position              */
-#define LCD_PAL65_I1_Msk                                      (0x01UL << LCD_PAL65_I1_Pos)                              /*!< LCD PAL65: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL66  -------------------------------------------
-#define LCD_PAL66_R04_0_Pos                                   0                                                         /*!< LCD PAL66: R04_0 Position           */
-#define LCD_PAL66_R04_0_Msk                                   (0x1fUL << LCD_PAL66_R04_0_Pos)                           /*!< LCD PAL66: R04_0 Mask               */
-#define LCD_PAL66_G04_0_Pos                                   5                                                         /*!< LCD PAL66: G04_0 Position           */
-#define LCD_PAL66_G04_0_Msk                                   (0x1fUL << LCD_PAL66_G04_0_Pos)                           /*!< LCD PAL66: G04_0 Mask               */
-#define LCD_PAL66_B04_0_Pos                                   10                                                        /*!< LCD PAL66: B04_0 Position           */
-#define LCD_PAL66_B04_0_Msk                                   (0x1fUL << LCD_PAL66_B04_0_Pos)                           /*!< LCD PAL66: B04_0 Mask               */
-#define LCD_PAL66_I0_Pos                                      15                                                        /*!< LCD PAL66: I0 Position              */
-#define LCD_PAL66_I0_Msk                                      (0x01UL << LCD_PAL66_I0_Pos)                              /*!< LCD PAL66: I0 Mask                  */
-#define LCD_PAL66_R14_0_Pos                                   16                                                        /*!< LCD PAL66: R14_0 Position           */
-#define LCD_PAL66_R14_0_Msk                                   (0x1fUL << LCD_PAL66_R14_0_Pos)                           /*!< LCD PAL66: R14_0 Mask               */
-#define LCD_PAL66_G14_0_Pos                                   21                                                        /*!< LCD PAL66: G14_0 Position           */
-#define LCD_PAL66_G14_0_Msk                                   (0x1fUL << LCD_PAL66_G14_0_Pos)                           /*!< LCD PAL66: G14_0 Mask               */
-#define LCD_PAL66_B14_0_Pos                                   26                                                        /*!< LCD PAL66: B14_0 Position           */
-#define LCD_PAL66_B14_0_Msk                                   (0x1fUL << LCD_PAL66_B14_0_Pos)                           /*!< LCD PAL66: B14_0 Mask               */
-#define LCD_PAL66_I1_Pos                                      31                                                        /*!< LCD PAL66: I1 Position              */
-#define LCD_PAL66_I1_Msk                                      (0x01UL << LCD_PAL66_I1_Pos)                              /*!< LCD PAL66: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL67  -------------------------------------------
-#define LCD_PAL67_R04_0_Pos                                   0                                                         /*!< LCD PAL67: R04_0 Position           */
-#define LCD_PAL67_R04_0_Msk                                   (0x1fUL << LCD_PAL67_R04_0_Pos)                           /*!< LCD PAL67: R04_0 Mask               */
-#define LCD_PAL67_G04_0_Pos                                   5                                                         /*!< LCD PAL67: G04_0 Position           */
-#define LCD_PAL67_G04_0_Msk                                   (0x1fUL << LCD_PAL67_G04_0_Pos)                           /*!< LCD PAL67: G04_0 Mask               */
-#define LCD_PAL67_B04_0_Pos                                   10                                                        /*!< LCD PAL67: B04_0 Position           */
-#define LCD_PAL67_B04_0_Msk                                   (0x1fUL << LCD_PAL67_B04_0_Pos)                           /*!< LCD PAL67: B04_0 Mask               */
-#define LCD_PAL67_I0_Pos                                      15                                                        /*!< LCD PAL67: I0 Position              */
-#define LCD_PAL67_I0_Msk                                      (0x01UL << LCD_PAL67_I0_Pos)                              /*!< LCD PAL67: I0 Mask                  */
-#define LCD_PAL67_R14_0_Pos                                   16                                                        /*!< LCD PAL67: R14_0 Position           */
-#define LCD_PAL67_R14_0_Msk                                   (0x1fUL << LCD_PAL67_R14_0_Pos)                           /*!< LCD PAL67: R14_0 Mask               */
-#define LCD_PAL67_G14_0_Pos                                   21                                                        /*!< LCD PAL67: G14_0 Position           */
-#define LCD_PAL67_G14_0_Msk                                   (0x1fUL << LCD_PAL67_G14_0_Pos)                           /*!< LCD PAL67: G14_0 Mask               */
-#define LCD_PAL67_B14_0_Pos                                   26                                                        /*!< LCD PAL67: B14_0 Position           */
-#define LCD_PAL67_B14_0_Msk                                   (0x1fUL << LCD_PAL67_B14_0_Pos)                           /*!< LCD PAL67: B14_0 Mask               */
-#define LCD_PAL67_I1_Pos                                      31                                                        /*!< LCD PAL67: I1 Position              */
-#define LCD_PAL67_I1_Msk                                      (0x01UL << LCD_PAL67_I1_Pos)                              /*!< LCD PAL67: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL68  -------------------------------------------
-#define LCD_PAL68_R04_0_Pos                                   0                                                         /*!< LCD PAL68: R04_0 Position           */
-#define LCD_PAL68_R04_0_Msk                                   (0x1fUL << LCD_PAL68_R04_0_Pos)                           /*!< LCD PAL68: R04_0 Mask               */
-#define LCD_PAL68_G04_0_Pos                                   5                                                         /*!< LCD PAL68: G04_0 Position           */
-#define LCD_PAL68_G04_0_Msk                                   (0x1fUL << LCD_PAL68_G04_0_Pos)                           /*!< LCD PAL68: G04_0 Mask               */
-#define LCD_PAL68_B04_0_Pos                                   10                                                        /*!< LCD PAL68: B04_0 Position           */
-#define LCD_PAL68_B04_0_Msk                                   (0x1fUL << LCD_PAL68_B04_0_Pos)                           /*!< LCD PAL68: B04_0 Mask               */
-#define LCD_PAL68_I0_Pos                                      15                                                        /*!< LCD PAL68: I0 Position              */
-#define LCD_PAL68_I0_Msk                                      (0x01UL << LCD_PAL68_I0_Pos)                              /*!< LCD PAL68: I0 Mask                  */
-#define LCD_PAL68_R14_0_Pos                                   16                                                        /*!< LCD PAL68: R14_0 Position           */
-#define LCD_PAL68_R14_0_Msk                                   (0x1fUL << LCD_PAL68_R14_0_Pos)                           /*!< LCD PAL68: R14_0 Mask               */
-#define LCD_PAL68_G14_0_Pos                                   21                                                        /*!< LCD PAL68: G14_0 Position           */
-#define LCD_PAL68_G14_0_Msk                                   (0x1fUL << LCD_PAL68_G14_0_Pos)                           /*!< LCD PAL68: G14_0 Mask               */
-#define LCD_PAL68_B14_0_Pos                                   26                                                        /*!< LCD PAL68: B14_0 Position           */
-#define LCD_PAL68_B14_0_Msk                                   (0x1fUL << LCD_PAL68_B14_0_Pos)                           /*!< LCD PAL68: B14_0 Mask               */
-#define LCD_PAL68_I1_Pos                                      31                                                        /*!< LCD PAL68: I1 Position              */
-#define LCD_PAL68_I1_Msk                                      (0x01UL << LCD_PAL68_I1_Pos)                              /*!< LCD PAL68: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL69  -------------------------------------------
-#define LCD_PAL69_R04_0_Pos                                   0                                                         /*!< LCD PAL69: R04_0 Position           */
-#define LCD_PAL69_R04_0_Msk                                   (0x1fUL << LCD_PAL69_R04_0_Pos)                           /*!< LCD PAL69: R04_0 Mask               */
-#define LCD_PAL69_G04_0_Pos                                   5                                                         /*!< LCD PAL69: G04_0 Position           */
-#define LCD_PAL69_G04_0_Msk                                   (0x1fUL << LCD_PAL69_G04_0_Pos)                           /*!< LCD PAL69: G04_0 Mask               */
-#define LCD_PAL69_B04_0_Pos                                   10                                                        /*!< LCD PAL69: B04_0 Position           */
-#define LCD_PAL69_B04_0_Msk                                   (0x1fUL << LCD_PAL69_B04_0_Pos)                           /*!< LCD PAL69: B04_0 Mask               */
-#define LCD_PAL69_I0_Pos                                      15                                                        /*!< LCD PAL69: I0 Position              */
-#define LCD_PAL69_I0_Msk                                      (0x01UL << LCD_PAL69_I0_Pos)                              /*!< LCD PAL69: I0 Mask                  */
-#define LCD_PAL69_R14_0_Pos                                   16                                                        /*!< LCD PAL69: R14_0 Position           */
-#define LCD_PAL69_R14_0_Msk                                   (0x1fUL << LCD_PAL69_R14_0_Pos)                           /*!< LCD PAL69: R14_0 Mask               */
-#define LCD_PAL69_G14_0_Pos                                   21                                                        /*!< LCD PAL69: G14_0 Position           */
-#define LCD_PAL69_G14_0_Msk                                   (0x1fUL << LCD_PAL69_G14_0_Pos)                           /*!< LCD PAL69: G14_0 Mask               */
-#define LCD_PAL69_B14_0_Pos                                   26                                                        /*!< LCD PAL69: B14_0 Position           */
-#define LCD_PAL69_B14_0_Msk                                   (0x1fUL << LCD_PAL69_B14_0_Pos)                           /*!< LCD PAL69: B14_0 Mask               */
-#define LCD_PAL69_I1_Pos                                      31                                                        /*!< LCD PAL69: I1 Position              */
-#define LCD_PAL69_I1_Msk                                      (0x01UL << LCD_PAL69_I1_Pos)                              /*!< LCD PAL69: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL70  -------------------------------------------
-#define LCD_PAL70_R04_0_Pos                                   0                                                         /*!< LCD PAL70: R04_0 Position           */
-#define LCD_PAL70_R04_0_Msk                                   (0x1fUL << LCD_PAL70_R04_0_Pos)                           /*!< LCD PAL70: R04_0 Mask               */
-#define LCD_PAL70_G04_0_Pos                                   5                                                         /*!< LCD PAL70: G04_0 Position           */
-#define LCD_PAL70_G04_0_Msk                                   (0x1fUL << LCD_PAL70_G04_0_Pos)                           /*!< LCD PAL70: G04_0 Mask               */
-#define LCD_PAL70_B04_0_Pos                                   10                                                        /*!< LCD PAL70: B04_0 Position           */
-#define LCD_PAL70_B04_0_Msk                                   (0x1fUL << LCD_PAL70_B04_0_Pos)                           /*!< LCD PAL70: B04_0 Mask               */
-#define LCD_PAL70_I0_Pos                                      15                                                        /*!< LCD PAL70: I0 Position              */
-#define LCD_PAL70_I0_Msk                                      (0x01UL << LCD_PAL70_I0_Pos)                              /*!< LCD PAL70: I0 Mask                  */
-#define LCD_PAL70_R14_0_Pos                                   16                                                        /*!< LCD PAL70: R14_0 Position           */
-#define LCD_PAL70_R14_0_Msk                                   (0x1fUL << LCD_PAL70_R14_0_Pos)                           /*!< LCD PAL70: R14_0 Mask               */
-#define LCD_PAL70_G14_0_Pos                                   21                                                        /*!< LCD PAL70: G14_0 Position           */
-#define LCD_PAL70_G14_0_Msk                                   (0x1fUL << LCD_PAL70_G14_0_Pos)                           /*!< LCD PAL70: G14_0 Mask               */
-#define LCD_PAL70_B14_0_Pos                                   26                                                        /*!< LCD PAL70: B14_0 Position           */
-#define LCD_PAL70_B14_0_Msk                                   (0x1fUL << LCD_PAL70_B14_0_Pos)                           /*!< LCD PAL70: B14_0 Mask               */
-#define LCD_PAL70_I1_Pos                                      31                                                        /*!< LCD PAL70: I1 Position              */
-#define LCD_PAL70_I1_Msk                                      (0x01UL << LCD_PAL70_I1_Pos)                              /*!< LCD PAL70: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL71  -------------------------------------------
-#define LCD_PAL71_R04_0_Pos                                   0                                                         /*!< LCD PAL71: R04_0 Position           */
-#define LCD_PAL71_R04_0_Msk                                   (0x1fUL << LCD_PAL71_R04_0_Pos)                           /*!< LCD PAL71: R04_0 Mask               */
-#define LCD_PAL71_G04_0_Pos                                   5                                                         /*!< LCD PAL71: G04_0 Position           */
-#define LCD_PAL71_G04_0_Msk                                   (0x1fUL << LCD_PAL71_G04_0_Pos)                           /*!< LCD PAL71: G04_0 Mask               */
-#define LCD_PAL71_B04_0_Pos                                   10                                                        /*!< LCD PAL71: B04_0 Position           */
-#define LCD_PAL71_B04_0_Msk                                   (0x1fUL << LCD_PAL71_B04_0_Pos)                           /*!< LCD PAL71: B04_0 Mask               */
-#define LCD_PAL71_I0_Pos                                      15                                                        /*!< LCD PAL71: I0 Position              */
-#define LCD_PAL71_I0_Msk                                      (0x01UL << LCD_PAL71_I0_Pos)                              /*!< LCD PAL71: I0 Mask                  */
-#define LCD_PAL71_R14_0_Pos                                   16                                                        /*!< LCD PAL71: R14_0 Position           */
-#define LCD_PAL71_R14_0_Msk                                   (0x1fUL << LCD_PAL71_R14_0_Pos)                           /*!< LCD PAL71: R14_0 Mask               */
-#define LCD_PAL71_G14_0_Pos                                   21                                                        /*!< LCD PAL71: G14_0 Position           */
-#define LCD_PAL71_G14_0_Msk                                   (0x1fUL << LCD_PAL71_G14_0_Pos)                           /*!< LCD PAL71: G14_0 Mask               */
-#define LCD_PAL71_B14_0_Pos                                   26                                                        /*!< LCD PAL71: B14_0 Position           */
-#define LCD_PAL71_B14_0_Msk                                   (0x1fUL << LCD_PAL71_B14_0_Pos)                           /*!< LCD PAL71: B14_0 Mask               */
-#define LCD_PAL71_I1_Pos                                      31                                                        /*!< LCD PAL71: I1 Position              */
-#define LCD_PAL71_I1_Msk                                      (0x01UL << LCD_PAL71_I1_Pos)                              /*!< LCD PAL71: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL72  -------------------------------------------
-#define LCD_PAL72_R04_0_Pos                                   0                                                         /*!< LCD PAL72: R04_0 Position           */
-#define LCD_PAL72_R04_0_Msk                                   (0x1fUL << LCD_PAL72_R04_0_Pos)                           /*!< LCD PAL72: R04_0 Mask               */
-#define LCD_PAL72_G04_0_Pos                                   5                                                         /*!< LCD PAL72: G04_0 Position           */
-#define LCD_PAL72_G04_0_Msk                                   (0x1fUL << LCD_PAL72_G04_0_Pos)                           /*!< LCD PAL72: G04_0 Mask               */
-#define LCD_PAL72_B04_0_Pos                                   10                                                        /*!< LCD PAL72: B04_0 Position           */
-#define LCD_PAL72_B04_0_Msk                                   (0x1fUL << LCD_PAL72_B04_0_Pos)                           /*!< LCD PAL72: B04_0 Mask               */
-#define LCD_PAL72_I0_Pos                                      15                                                        /*!< LCD PAL72: I0 Position              */
-#define LCD_PAL72_I0_Msk                                      (0x01UL << LCD_PAL72_I0_Pos)                              /*!< LCD PAL72: I0 Mask                  */
-#define LCD_PAL72_R14_0_Pos                                   16                                                        /*!< LCD PAL72: R14_0 Position           */
-#define LCD_PAL72_R14_0_Msk                                   (0x1fUL << LCD_PAL72_R14_0_Pos)                           /*!< LCD PAL72: R14_0 Mask               */
-#define LCD_PAL72_G14_0_Pos                                   21                                                        /*!< LCD PAL72: G14_0 Position           */
-#define LCD_PAL72_G14_0_Msk                                   (0x1fUL << LCD_PAL72_G14_0_Pos)                           /*!< LCD PAL72: G14_0 Mask               */
-#define LCD_PAL72_B14_0_Pos                                   26                                                        /*!< LCD PAL72: B14_0 Position           */
-#define LCD_PAL72_B14_0_Msk                                   (0x1fUL << LCD_PAL72_B14_0_Pos)                           /*!< LCD PAL72: B14_0 Mask               */
-#define LCD_PAL72_I1_Pos                                      31                                                        /*!< LCD PAL72: I1 Position              */
-#define LCD_PAL72_I1_Msk                                      (0x01UL << LCD_PAL72_I1_Pos)                              /*!< LCD PAL72: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL73  -------------------------------------------
-#define LCD_PAL73_R04_0_Pos                                   0                                                         /*!< LCD PAL73: R04_0 Position           */
-#define LCD_PAL73_R04_0_Msk                                   (0x1fUL << LCD_PAL73_R04_0_Pos)                           /*!< LCD PAL73: R04_0 Mask               */
-#define LCD_PAL73_G04_0_Pos                                   5                                                         /*!< LCD PAL73: G04_0 Position           */
-#define LCD_PAL73_G04_0_Msk                                   (0x1fUL << LCD_PAL73_G04_0_Pos)                           /*!< LCD PAL73: G04_0 Mask               */
-#define LCD_PAL73_B04_0_Pos                                   10                                                        /*!< LCD PAL73: B04_0 Position           */
-#define LCD_PAL73_B04_0_Msk                                   (0x1fUL << LCD_PAL73_B04_0_Pos)                           /*!< LCD PAL73: B04_0 Mask               */
-#define LCD_PAL73_I0_Pos                                      15                                                        /*!< LCD PAL73: I0 Position              */
-#define LCD_PAL73_I0_Msk                                      (0x01UL << LCD_PAL73_I0_Pos)                              /*!< LCD PAL73: I0 Mask                  */
-#define LCD_PAL73_R14_0_Pos                                   16                                                        /*!< LCD PAL73: R14_0 Position           */
-#define LCD_PAL73_R14_0_Msk                                   (0x1fUL << LCD_PAL73_R14_0_Pos)                           /*!< LCD PAL73: R14_0 Mask               */
-#define LCD_PAL73_G14_0_Pos                                   21                                                        /*!< LCD PAL73: G14_0 Position           */
-#define LCD_PAL73_G14_0_Msk                                   (0x1fUL << LCD_PAL73_G14_0_Pos)                           /*!< LCD PAL73: G14_0 Mask               */
-#define LCD_PAL73_B14_0_Pos                                   26                                                        /*!< LCD PAL73: B14_0 Position           */
-#define LCD_PAL73_B14_0_Msk                                   (0x1fUL << LCD_PAL73_B14_0_Pos)                           /*!< LCD PAL73: B14_0 Mask               */
-#define LCD_PAL73_I1_Pos                                      31                                                        /*!< LCD PAL73: I1 Position              */
-#define LCD_PAL73_I1_Msk                                      (0x01UL << LCD_PAL73_I1_Pos)                              /*!< LCD PAL73: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL74  -------------------------------------------
-#define LCD_PAL74_R04_0_Pos                                   0                                                         /*!< LCD PAL74: R04_0 Position           */
-#define LCD_PAL74_R04_0_Msk                                   (0x1fUL << LCD_PAL74_R04_0_Pos)                           /*!< LCD PAL74: R04_0 Mask               */
-#define LCD_PAL74_G04_0_Pos                                   5                                                         /*!< LCD PAL74: G04_0 Position           */
-#define LCD_PAL74_G04_0_Msk                                   (0x1fUL << LCD_PAL74_G04_0_Pos)                           /*!< LCD PAL74: G04_0 Mask               */
-#define LCD_PAL74_B04_0_Pos                                   10                                                        /*!< LCD PAL74: B04_0 Position           */
-#define LCD_PAL74_B04_0_Msk                                   (0x1fUL << LCD_PAL74_B04_0_Pos)                           /*!< LCD PAL74: B04_0 Mask               */
-#define LCD_PAL74_I0_Pos                                      15                                                        /*!< LCD PAL74: I0 Position              */
-#define LCD_PAL74_I0_Msk                                      (0x01UL << LCD_PAL74_I0_Pos)                              /*!< LCD PAL74: I0 Mask                  */
-#define LCD_PAL74_R14_0_Pos                                   16                                                        /*!< LCD PAL74: R14_0 Position           */
-#define LCD_PAL74_R14_0_Msk                                   (0x1fUL << LCD_PAL74_R14_0_Pos)                           /*!< LCD PAL74: R14_0 Mask               */
-#define LCD_PAL74_G14_0_Pos                                   21                                                        /*!< LCD PAL74: G14_0 Position           */
-#define LCD_PAL74_G14_0_Msk                                   (0x1fUL << LCD_PAL74_G14_0_Pos)                           /*!< LCD PAL74: G14_0 Mask               */
-#define LCD_PAL74_B14_0_Pos                                   26                                                        /*!< LCD PAL74: B14_0 Position           */
-#define LCD_PAL74_B14_0_Msk                                   (0x1fUL << LCD_PAL74_B14_0_Pos)                           /*!< LCD PAL74: B14_0 Mask               */
-#define LCD_PAL74_I1_Pos                                      31                                                        /*!< LCD PAL74: I1 Position              */
-#define LCD_PAL74_I1_Msk                                      (0x01UL << LCD_PAL74_I1_Pos)                              /*!< LCD PAL74: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL75  -------------------------------------------
-#define LCD_PAL75_R04_0_Pos                                   0                                                         /*!< LCD PAL75: R04_0 Position           */
-#define LCD_PAL75_R04_0_Msk                                   (0x1fUL << LCD_PAL75_R04_0_Pos)                           /*!< LCD PAL75: R04_0 Mask               */
-#define LCD_PAL75_G04_0_Pos                                   5                                                         /*!< LCD PAL75: G04_0 Position           */
-#define LCD_PAL75_G04_0_Msk                                   (0x1fUL << LCD_PAL75_G04_0_Pos)                           /*!< LCD PAL75: G04_0 Mask               */
-#define LCD_PAL75_B04_0_Pos                                   10                                                        /*!< LCD PAL75: B04_0 Position           */
-#define LCD_PAL75_B04_0_Msk                                   (0x1fUL << LCD_PAL75_B04_0_Pos)                           /*!< LCD PAL75: B04_0 Mask               */
-#define LCD_PAL75_I0_Pos                                      15                                                        /*!< LCD PAL75: I0 Position              */
-#define LCD_PAL75_I0_Msk                                      (0x01UL << LCD_PAL75_I0_Pos)                              /*!< LCD PAL75: I0 Mask                  */
-#define LCD_PAL75_R14_0_Pos                                   16                                                        /*!< LCD PAL75: R14_0 Position           */
-#define LCD_PAL75_R14_0_Msk                                   (0x1fUL << LCD_PAL75_R14_0_Pos)                           /*!< LCD PAL75: R14_0 Mask               */
-#define LCD_PAL75_G14_0_Pos                                   21                                                        /*!< LCD PAL75: G14_0 Position           */
-#define LCD_PAL75_G14_0_Msk                                   (0x1fUL << LCD_PAL75_G14_0_Pos)                           /*!< LCD PAL75: G14_0 Mask               */
-#define LCD_PAL75_B14_0_Pos                                   26                                                        /*!< LCD PAL75: B14_0 Position           */
-#define LCD_PAL75_B14_0_Msk                                   (0x1fUL << LCD_PAL75_B14_0_Pos)                           /*!< LCD PAL75: B14_0 Mask               */
-#define LCD_PAL75_I1_Pos                                      31                                                        /*!< LCD PAL75: I1 Position              */
-#define LCD_PAL75_I1_Msk                                      (0x01UL << LCD_PAL75_I1_Pos)                              /*!< LCD PAL75: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL76  -------------------------------------------
-#define LCD_PAL76_R04_0_Pos                                   0                                                         /*!< LCD PAL76: R04_0 Position           */
-#define LCD_PAL76_R04_0_Msk                                   (0x1fUL << LCD_PAL76_R04_0_Pos)                           /*!< LCD PAL76: R04_0 Mask               */
-#define LCD_PAL76_G04_0_Pos                                   5                                                         /*!< LCD PAL76: G04_0 Position           */
-#define LCD_PAL76_G04_0_Msk                                   (0x1fUL << LCD_PAL76_G04_0_Pos)                           /*!< LCD PAL76: G04_0 Mask               */
-#define LCD_PAL76_B04_0_Pos                                   10                                                        /*!< LCD PAL76: B04_0 Position           */
-#define LCD_PAL76_B04_0_Msk                                   (0x1fUL << LCD_PAL76_B04_0_Pos)                           /*!< LCD PAL76: B04_0 Mask               */
-#define LCD_PAL76_I0_Pos                                      15                                                        /*!< LCD PAL76: I0 Position              */
-#define LCD_PAL76_I0_Msk                                      (0x01UL << LCD_PAL76_I0_Pos)                              /*!< LCD PAL76: I0 Mask                  */
-#define LCD_PAL76_R14_0_Pos                                   16                                                        /*!< LCD PAL76: R14_0 Position           */
-#define LCD_PAL76_R14_0_Msk                                   (0x1fUL << LCD_PAL76_R14_0_Pos)                           /*!< LCD PAL76: R14_0 Mask               */
-#define LCD_PAL76_G14_0_Pos                                   21                                                        /*!< LCD PAL76: G14_0 Position           */
-#define LCD_PAL76_G14_0_Msk                                   (0x1fUL << LCD_PAL76_G14_0_Pos)                           /*!< LCD PAL76: G14_0 Mask               */
-#define LCD_PAL76_B14_0_Pos                                   26                                                        /*!< LCD PAL76: B14_0 Position           */
-#define LCD_PAL76_B14_0_Msk                                   (0x1fUL << LCD_PAL76_B14_0_Pos)                           /*!< LCD PAL76: B14_0 Mask               */
-#define LCD_PAL76_I1_Pos                                      31                                                        /*!< LCD PAL76: I1 Position              */
-#define LCD_PAL76_I1_Msk                                      (0x01UL << LCD_PAL76_I1_Pos)                              /*!< LCD PAL76: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL77  -------------------------------------------
-#define LCD_PAL77_R04_0_Pos                                   0                                                         /*!< LCD PAL77: R04_0 Position           */
-#define LCD_PAL77_R04_0_Msk                                   (0x1fUL << LCD_PAL77_R04_0_Pos)                           /*!< LCD PAL77: R04_0 Mask               */
-#define LCD_PAL77_G04_0_Pos                                   5                                                         /*!< LCD PAL77: G04_0 Position           */
-#define LCD_PAL77_G04_0_Msk                                   (0x1fUL << LCD_PAL77_G04_0_Pos)                           /*!< LCD PAL77: G04_0 Mask               */
-#define LCD_PAL77_B04_0_Pos                                   10                                                        /*!< LCD PAL77: B04_0 Position           */
-#define LCD_PAL77_B04_0_Msk                                   (0x1fUL << LCD_PAL77_B04_0_Pos)                           /*!< LCD PAL77: B04_0 Mask               */
-#define LCD_PAL77_I0_Pos                                      15                                                        /*!< LCD PAL77: I0 Position              */
-#define LCD_PAL77_I0_Msk                                      (0x01UL << LCD_PAL77_I0_Pos)                              /*!< LCD PAL77: I0 Mask                  */
-#define LCD_PAL77_R14_0_Pos                                   16                                                        /*!< LCD PAL77: R14_0 Position           */
-#define LCD_PAL77_R14_0_Msk                                   (0x1fUL << LCD_PAL77_R14_0_Pos)                           /*!< LCD PAL77: R14_0 Mask               */
-#define LCD_PAL77_G14_0_Pos                                   21                                                        /*!< LCD PAL77: G14_0 Position           */
-#define LCD_PAL77_G14_0_Msk                                   (0x1fUL << LCD_PAL77_G14_0_Pos)                           /*!< LCD PAL77: G14_0 Mask               */
-#define LCD_PAL77_B14_0_Pos                                   26                                                        /*!< LCD PAL77: B14_0 Position           */
-#define LCD_PAL77_B14_0_Msk                                   (0x1fUL << LCD_PAL77_B14_0_Pos)                           /*!< LCD PAL77: B14_0 Mask               */
-#define LCD_PAL77_I1_Pos                                      31                                                        /*!< LCD PAL77: I1 Position              */
-#define LCD_PAL77_I1_Msk                                      (0x01UL << LCD_PAL77_I1_Pos)                              /*!< LCD PAL77: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL78  -------------------------------------------
-#define LCD_PAL78_R04_0_Pos                                   0                                                         /*!< LCD PAL78: R04_0 Position           */
-#define LCD_PAL78_R04_0_Msk                                   (0x1fUL << LCD_PAL78_R04_0_Pos)                           /*!< LCD PAL78: R04_0 Mask               */
-#define LCD_PAL78_G04_0_Pos                                   5                                                         /*!< LCD PAL78: G04_0 Position           */
-#define LCD_PAL78_G04_0_Msk                                   (0x1fUL << LCD_PAL78_G04_0_Pos)                           /*!< LCD PAL78: G04_0 Mask               */
-#define LCD_PAL78_B04_0_Pos                                   10                                                        /*!< LCD PAL78: B04_0 Position           */
-#define LCD_PAL78_B04_0_Msk                                   (0x1fUL << LCD_PAL78_B04_0_Pos)                           /*!< LCD PAL78: B04_0 Mask               */
-#define LCD_PAL78_I0_Pos                                      15                                                        /*!< LCD PAL78: I0 Position              */
-#define LCD_PAL78_I0_Msk                                      (0x01UL << LCD_PAL78_I0_Pos)                              /*!< LCD PAL78: I0 Mask                  */
-#define LCD_PAL78_R14_0_Pos                                   16                                                        /*!< LCD PAL78: R14_0 Position           */
-#define LCD_PAL78_R14_0_Msk                                   (0x1fUL << LCD_PAL78_R14_0_Pos)                           /*!< LCD PAL78: R14_0 Mask               */
-#define LCD_PAL78_G14_0_Pos                                   21                                                        /*!< LCD PAL78: G14_0 Position           */
-#define LCD_PAL78_G14_0_Msk                                   (0x1fUL << LCD_PAL78_G14_0_Pos)                           /*!< LCD PAL78: G14_0 Mask               */
-#define LCD_PAL78_B14_0_Pos                                   26                                                        /*!< LCD PAL78: B14_0 Position           */
-#define LCD_PAL78_B14_0_Msk                                   (0x1fUL << LCD_PAL78_B14_0_Pos)                           /*!< LCD PAL78: B14_0 Mask               */
-#define LCD_PAL78_I1_Pos                                      31                                                        /*!< LCD PAL78: I1 Position              */
-#define LCD_PAL78_I1_Msk                                      (0x01UL << LCD_PAL78_I1_Pos)                              /*!< LCD PAL78: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL79  -------------------------------------------
-#define LCD_PAL79_R04_0_Pos                                   0                                                         /*!< LCD PAL79: R04_0 Position           */
-#define LCD_PAL79_R04_0_Msk                                   (0x1fUL << LCD_PAL79_R04_0_Pos)                           /*!< LCD PAL79: R04_0 Mask               */
-#define LCD_PAL79_G04_0_Pos                                   5                                                         /*!< LCD PAL79: G04_0 Position           */
-#define LCD_PAL79_G04_0_Msk                                   (0x1fUL << LCD_PAL79_G04_0_Pos)                           /*!< LCD PAL79: G04_0 Mask               */
-#define LCD_PAL79_B04_0_Pos                                   10                                                        /*!< LCD PAL79: B04_0 Position           */
-#define LCD_PAL79_B04_0_Msk                                   (0x1fUL << LCD_PAL79_B04_0_Pos)                           /*!< LCD PAL79: B04_0 Mask               */
-#define LCD_PAL79_I0_Pos                                      15                                                        /*!< LCD PAL79: I0 Position              */
-#define LCD_PAL79_I0_Msk                                      (0x01UL << LCD_PAL79_I0_Pos)                              /*!< LCD PAL79: I0 Mask                  */
-#define LCD_PAL79_R14_0_Pos                                   16                                                        /*!< LCD PAL79: R14_0 Position           */
-#define LCD_PAL79_R14_0_Msk                                   (0x1fUL << LCD_PAL79_R14_0_Pos)                           /*!< LCD PAL79: R14_0 Mask               */
-#define LCD_PAL79_G14_0_Pos                                   21                                                        /*!< LCD PAL79: G14_0 Position           */
-#define LCD_PAL79_G14_0_Msk                                   (0x1fUL << LCD_PAL79_G14_0_Pos)                           /*!< LCD PAL79: G14_0 Mask               */
-#define LCD_PAL79_B14_0_Pos                                   26                                                        /*!< LCD PAL79: B14_0 Position           */
-#define LCD_PAL79_B14_0_Msk                                   (0x1fUL << LCD_PAL79_B14_0_Pos)                           /*!< LCD PAL79: B14_0 Mask               */
-#define LCD_PAL79_I1_Pos                                      31                                                        /*!< LCD PAL79: I1 Position              */
-#define LCD_PAL79_I1_Msk                                      (0x01UL << LCD_PAL79_I1_Pos)                              /*!< LCD PAL79: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL80  -------------------------------------------
-#define LCD_PAL80_R04_0_Pos                                   0                                                         /*!< LCD PAL80: R04_0 Position           */
-#define LCD_PAL80_R04_0_Msk                                   (0x1fUL << LCD_PAL80_R04_0_Pos)                           /*!< LCD PAL80: R04_0 Mask               */
-#define LCD_PAL80_G04_0_Pos                                   5                                                         /*!< LCD PAL80: G04_0 Position           */
-#define LCD_PAL80_G04_0_Msk                                   (0x1fUL << LCD_PAL80_G04_0_Pos)                           /*!< LCD PAL80: G04_0 Mask               */
-#define LCD_PAL80_B04_0_Pos                                   10                                                        /*!< LCD PAL80: B04_0 Position           */
-#define LCD_PAL80_B04_0_Msk                                   (0x1fUL << LCD_PAL80_B04_0_Pos)                           /*!< LCD PAL80: B04_0 Mask               */
-#define LCD_PAL80_I0_Pos                                      15                                                        /*!< LCD PAL80: I0 Position              */
-#define LCD_PAL80_I0_Msk                                      (0x01UL << LCD_PAL80_I0_Pos)                              /*!< LCD PAL80: I0 Mask                  */
-#define LCD_PAL80_R14_0_Pos                                   16                                                        /*!< LCD PAL80: R14_0 Position           */
-#define LCD_PAL80_R14_0_Msk                                   (0x1fUL << LCD_PAL80_R14_0_Pos)                           /*!< LCD PAL80: R14_0 Mask               */
-#define LCD_PAL80_G14_0_Pos                                   21                                                        /*!< LCD PAL80: G14_0 Position           */
-#define LCD_PAL80_G14_0_Msk                                   (0x1fUL << LCD_PAL80_G14_0_Pos)                           /*!< LCD PAL80: G14_0 Mask               */
-#define LCD_PAL80_B14_0_Pos                                   26                                                        /*!< LCD PAL80: B14_0 Position           */
-#define LCD_PAL80_B14_0_Msk                                   (0x1fUL << LCD_PAL80_B14_0_Pos)                           /*!< LCD PAL80: B14_0 Mask               */
-#define LCD_PAL80_I1_Pos                                      31                                                        /*!< LCD PAL80: I1 Position              */
-#define LCD_PAL80_I1_Msk                                      (0x01UL << LCD_PAL80_I1_Pos)                              /*!< LCD PAL80: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL81  -------------------------------------------
-#define LCD_PAL81_R04_0_Pos                                   0                                                         /*!< LCD PAL81: R04_0 Position           */
-#define LCD_PAL81_R04_0_Msk                                   (0x1fUL << LCD_PAL81_R04_0_Pos)                           /*!< LCD PAL81: R04_0 Mask               */
-#define LCD_PAL81_G04_0_Pos                                   5                                                         /*!< LCD PAL81: G04_0 Position           */
-#define LCD_PAL81_G04_0_Msk                                   (0x1fUL << LCD_PAL81_G04_0_Pos)                           /*!< LCD PAL81: G04_0 Mask               */
-#define LCD_PAL81_B04_0_Pos                                   10                                                        /*!< LCD PAL81: B04_0 Position           */
-#define LCD_PAL81_B04_0_Msk                                   (0x1fUL << LCD_PAL81_B04_0_Pos)                           /*!< LCD PAL81: B04_0 Mask               */
-#define LCD_PAL81_I0_Pos                                      15                                                        /*!< LCD PAL81: I0 Position              */
-#define LCD_PAL81_I0_Msk                                      (0x01UL << LCD_PAL81_I0_Pos)                              /*!< LCD PAL81: I0 Mask                  */
-#define LCD_PAL81_R14_0_Pos                                   16                                                        /*!< LCD PAL81: R14_0 Position           */
-#define LCD_PAL81_R14_0_Msk                                   (0x1fUL << LCD_PAL81_R14_0_Pos)                           /*!< LCD PAL81: R14_0 Mask               */
-#define LCD_PAL81_G14_0_Pos                                   21                                                        /*!< LCD PAL81: G14_0 Position           */
-#define LCD_PAL81_G14_0_Msk                                   (0x1fUL << LCD_PAL81_G14_0_Pos)                           /*!< LCD PAL81: G14_0 Mask               */
-#define LCD_PAL81_B14_0_Pos                                   26                                                        /*!< LCD PAL81: B14_0 Position           */
-#define LCD_PAL81_B14_0_Msk                                   (0x1fUL << LCD_PAL81_B14_0_Pos)                           /*!< LCD PAL81: B14_0 Mask               */
-#define LCD_PAL81_I1_Pos                                      31                                                        /*!< LCD PAL81: I1 Position              */
-#define LCD_PAL81_I1_Msk                                      (0x01UL << LCD_PAL81_I1_Pos)                              /*!< LCD PAL81: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL82  -------------------------------------------
-#define LCD_PAL82_R04_0_Pos                                   0                                                         /*!< LCD PAL82: R04_0 Position           */
-#define LCD_PAL82_R04_0_Msk                                   (0x1fUL << LCD_PAL82_R04_0_Pos)                           /*!< LCD PAL82: R04_0 Mask               */
-#define LCD_PAL82_G04_0_Pos                                   5                                                         /*!< LCD PAL82: G04_0 Position           */
-#define LCD_PAL82_G04_0_Msk                                   (0x1fUL << LCD_PAL82_G04_0_Pos)                           /*!< LCD PAL82: G04_0 Mask               */
-#define LCD_PAL82_B04_0_Pos                                   10                                                        /*!< LCD PAL82: B04_0 Position           */
-#define LCD_PAL82_B04_0_Msk                                   (0x1fUL << LCD_PAL82_B04_0_Pos)                           /*!< LCD PAL82: B04_0 Mask               */
-#define LCD_PAL82_I0_Pos                                      15                                                        /*!< LCD PAL82: I0 Position              */
-#define LCD_PAL82_I0_Msk                                      (0x01UL << LCD_PAL82_I0_Pos)                              /*!< LCD PAL82: I0 Mask                  */
-#define LCD_PAL82_R14_0_Pos                                   16                                                        /*!< LCD PAL82: R14_0 Position           */
-#define LCD_PAL82_R14_0_Msk                                   (0x1fUL << LCD_PAL82_R14_0_Pos)                           /*!< LCD PAL82: R14_0 Mask               */
-#define LCD_PAL82_G14_0_Pos                                   21                                                        /*!< LCD PAL82: G14_0 Position           */
-#define LCD_PAL82_G14_0_Msk                                   (0x1fUL << LCD_PAL82_G14_0_Pos)                           /*!< LCD PAL82: G14_0 Mask               */
-#define LCD_PAL82_B14_0_Pos                                   26                                                        /*!< LCD PAL82: B14_0 Position           */
-#define LCD_PAL82_B14_0_Msk                                   (0x1fUL << LCD_PAL82_B14_0_Pos)                           /*!< LCD PAL82: B14_0 Mask               */
-#define LCD_PAL82_I1_Pos                                      31                                                        /*!< LCD PAL82: I1 Position              */
-#define LCD_PAL82_I1_Msk                                      (0x01UL << LCD_PAL82_I1_Pos)                              /*!< LCD PAL82: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL83  -------------------------------------------
-#define LCD_PAL83_R04_0_Pos                                   0                                                         /*!< LCD PAL83: R04_0 Position           */
-#define LCD_PAL83_R04_0_Msk                                   (0x1fUL << LCD_PAL83_R04_0_Pos)                           /*!< LCD PAL83: R04_0 Mask               */
-#define LCD_PAL83_G04_0_Pos                                   5                                                         /*!< LCD PAL83: G04_0 Position           */
-#define LCD_PAL83_G04_0_Msk                                   (0x1fUL << LCD_PAL83_G04_0_Pos)                           /*!< LCD PAL83: G04_0 Mask               */
-#define LCD_PAL83_B04_0_Pos                                   10                                                        /*!< LCD PAL83: B04_0 Position           */
-#define LCD_PAL83_B04_0_Msk                                   (0x1fUL << LCD_PAL83_B04_0_Pos)                           /*!< LCD PAL83: B04_0 Mask               */
-#define LCD_PAL83_I0_Pos                                      15                                                        /*!< LCD PAL83: I0 Position              */
-#define LCD_PAL83_I0_Msk                                      (0x01UL << LCD_PAL83_I0_Pos)                              /*!< LCD PAL83: I0 Mask                  */
-#define LCD_PAL83_R14_0_Pos                                   16                                                        /*!< LCD PAL83: R14_0 Position           */
-#define LCD_PAL83_R14_0_Msk                                   (0x1fUL << LCD_PAL83_R14_0_Pos)                           /*!< LCD PAL83: R14_0 Mask               */
-#define LCD_PAL83_G14_0_Pos                                   21                                                        /*!< LCD PAL83: G14_0 Position           */
-#define LCD_PAL83_G14_0_Msk                                   (0x1fUL << LCD_PAL83_G14_0_Pos)                           /*!< LCD PAL83: G14_0 Mask               */
-#define LCD_PAL83_B14_0_Pos                                   26                                                        /*!< LCD PAL83: B14_0 Position           */
-#define LCD_PAL83_B14_0_Msk                                   (0x1fUL << LCD_PAL83_B14_0_Pos)                           /*!< LCD PAL83: B14_0 Mask               */
-#define LCD_PAL83_I1_Pos                                      31                                                        /*!< LCD PAL83: I1 Position              */
-#define LCD_PAL83_I1_Msk                                      (0x01UL << LCD_PAL83_I1_Pos)                              /*!< LCD PAL83: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL84  -------------------------------------------
-#define LCD_PAL84_R04_0_Pos                                   0                                                         /*!< LCD PAL84: R04_0 Position           */
-#define LCD_PAL84_R04_0_Msk                                   (0x1fUL << LCD_PAL84_R04_0_Pos)                           /*!< LCD PAL84: R04_0 Mask               */
-#define LCD_PAL84_G04_0_Pos                                   5                                                         /*!< LCD PAL84: G04_0 Position           */
-#define LCD_PAL84_G04_0_Msk                                   (0x1fUL << LCD_PAL84_G04_0_Pos)                           /*!< LCD PAL84: G04_0 Mask               */
-#define LCD_PAL84_B04_0_Pos                                   10                                                        /*!< LCD PAL84: B04_0 Position           */
-#define LCD_PAL84_B04_0_Msk                                   (0x1fUL << LCD_PAL84_B04_0_Pos)                           /*!< LCD PAL84: B04_0 Mask               */
-#define LCD_PAL84_I0_Pos                                      15                                                        /*!< LCD PAL84: I0 Position              */
-#define LCD_PAL84_I0_Msk                                      (0x01UL << LCD_PAL84_I0_Pos)                              /*!< LCD PAL84: I0 Mask                  */
-#define LCD_PAL84_R14_0_Pos                                   16                                                        /*!< LCD PAL84: R14_0 Position           */
-#define LCD_PAL84_R14_0_Msk                                   (0x1fUL << LCD_PAL84_R14_0_Pos)                           /*!< LCD PAL84: R14_0 Mask               */
-#define LCD_PAL84_G14_0_Pos                                   21                                                        /*!< LCD PAL84: G14_0 Position           */
-#define LCD_PAL84_G14_0_Msk                                   (0x1fUL << LCD_PAL84_G14_0_Pos)                           /*!< LCD PAL84: G14_0 Mask               */
-#define LCD_PAL84_B14_0_Pos                                   26                                                        /*!< LCD PAL84: B14_0 Position           */
-#define LCD_PAL84_B14_0_Msk                                   (0x1fUL << LCD_PAL84_B14_0_Pos)                           /*!< LCD PAL84: B14_0 Mask               */
-#define LCD_PAL84_I1_Pos                                      31                                                        /*!< LCD PAL84: I1 Position              */
-#define LCD_PAL84_I1_Msk                                      (0x01UL << LCD_PAL84_I1_Pos)                              /*!< LCD PAL84: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL85  -------------------------------------------
-#define LCD_PAL85_R04_0_Pos                                   0                                                         /*!< LCD PAL85: R04_0 Position           */
-#define LCD_PAL85_R04_0_Msk                                   (0x1fUL << LCD_PAL85_R04_0_Pos)                           /*!< LCD PAL85: R04_0 Mask               */
-#define LCD_PAL85_G04_0_Pos                                   5                                                         /*!< LCD PAL85: G04_0 Position           */
-#define LCD_PAL85_G04_0_Msk                                   (0x1fUL << LCD_PAL85_G04_0_Pos)                           /*!< LCD PAL85: G04_0 Mask               */
-#define LCD_PAL85_B04_0_Pos                                   10                                                        /*!< LCD PAL85: B04_0 Position           */
-#define LCD_PAL85_B04_0_Msk                                   (0x1fUL << LCD_PAL85_B04_0_Pos)                           /*!< LCD PAL85: B04_0 Mask               */
-#define LCD_PAL85_I0_Pos                                      15                                                        /*!< LCD PAL85: I0 Position              */
-#define LCD_PAL85_I0_Msk                                      (0x01UL << LCD_PAL85_I0_Pos)                              /*!< LCD PAL85: I0 Mask                  */
-#define LCD_PAL85_R14_0_Pos                                   16                                                        /*!< LCD PAL85: R14_0 Position           */
-#define LCD_PAL85_R14_0_Msk                                   (0x1fUL << LCD_PAL85_R14_0_Pos)                           /*!< LCD PAL85: R14_0 Mask               */
-#define LCD_PAL85_G14_0_Pos                                   21                                                        /*!< LCD PAL85: G14_0 Position           */
-#define LCD_PAL85_G14_0_Msk                                   (0x1fUL << LCD_PAL85_G14_0_Pos)                           /*!< LCD PAL85: G14_0 Mask               */
-#define LCD_PAL85_B14_0_Pos                                   26                                                        /*!< LCD PAL85: B14_0 Position           */
-#define LCD_PAL85_B14_0_Msk                                   (0x1fUL << LCD_PAL85_B14_0_Pos)                           /*!< LCD PAL85: B14_0 Mask               */
-#define LCD_PAL85_I1_Pos                                      31                                                        /*!< LCD PAL85: I1 Position              */
-#define LCD_PAL85_I1_Msk                                      (0x01UL << LCD_PAL85_I1_Pos)                              /*!< LCD PAL85: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL86  -------------------------------------------
-#define LCD_PAL86_R04_0_Pos                                   0                                                         /*!< LCD PAL86: R04_0 Position           */
-#define LCD_PAL86_R04_0_Msk                                   (0x1fUL << LCD_PAL86_R04_0_Pos)                           /*!< LCD PAL86: R04_0 Mask               */
-#define LCD_PAL86_G04_0_Pos                                   5                                                         /*!< LCD PAL86: G04_0 Position           */
-#define LCD_PAL86_G04_0_Msk                                   (0x1fUL << LCD_PAL86_G04_0_Pos)                           /*!< LCD PAL86: G04_0 Mask               */
-#define LCD_PAL86_B04_0_Pos                                   10                                                        /*!< LCD PAL86: B04_0 Position           */
-#define LCD_PAL86_B04_0_Msk                                   (0x1fUL << LCD_PAL86_B04_0_Pos)                           /*!< LCD PAL86: B04_0 Mask               */
-#define LCD_PAL86_I0_Pos                                      15                                                        /*!< LCD PAL86: I0 Position              */
-#define LCD_PAL86_I0_Msk                                      (0x01UL << LCD_PAL86_I0_Pos)                              /*!< LCD PAL86: I0 Mask                  */
-#define LCD_PAL86_R14_0_Pos                                   16                                                        /*!< LCD PAL86: R14_0 Position           */
-#define LCD_PAL86_R14_0_Msk                                   (0x1fUL << LCD_PAL86_R14_0_Pos)                           /*!< LCD PAL86: R14_0 Mask               */
-#define LCD_PAL86_G14_0_Pos                                   21                                                        /*!< LCD PAL86: G14_0 Position           */
-#define LCD_PAL86_G14_0_Msk                                   (0x1fUL << LCD_PAL86_G14_0_Pos)                           /*!< LCD PAL86: G14_0 Mask               */
-#define LCD_PAL86_B14_0_Pos                                   26                                                        /*!< LCD PAL86: B14_0 Position           */
-#define LCD_PAL86_B14_0_Msk                                   (0x1fUL << LCD_PAL86_B14_0_Pos)                           /*!< LCD PAL86: B14_0 Mask               */
-#define LCD_PAL86_I1_Pos                                      31                                                        /*!< LCD PAL86: I1 Position              */
-#define LCD_PAL86_I1_Msk                                      (0x01UL << LCD_PAL86_I1_Pos)                              /*!< LCD PAL86: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL87  -------------------------------------------
-#define LCD_PAL87_R04_0_Pos                                   0                                                         /*!< LCD PAL87: R04_0 Position           */
-#define LCD_PAL87_R04_0_Msk                                   (0x1fUL << LCD_PAL87_R04_0_Pos)                           /*!< LCD PAL87: R04_0 Mask               */
-#define LCD_PAL87_G04_0_Pos                                   5                                                         /*!< LCD PAL87: G04_0 Position           */
-#define LCD_PAL87_G04_0_Msk                                   (0x1fUL << LCD_PAL87_G04_0_Pos)                           /*!< LCD PAL87: G04_0 Mask               */
-#define LCD_PAL87_B04_0_Pos                                   10                                                        /*!< LCD PAL87: B04_0 Position           */
-#define LCD_PAL87_B04_0_Msk                                   (0x1fUL << LCD_PAL87_B04_0_Pos)                           /*!< LCD PAL87: B04_0 Mask               */
-#define LCD_PAL87_I0_Pos                                      15                                                        /*!< LCD PAL87: I0 Position              */
-#define LCD_PAL87_I0_Msk                                      (0x01UL << LCD_PAL87_I0_Pos)                              /*!< LCD PAL87: I0 Mask                  */
-#define LCD_PAL87_R14_0_Pos                                   16                                                        /*!< LCD PAL87: R14_0 Position           */
-#define LCD_PAL87_R14_0_Msk                                   (0x1fUL << LCD_PAL87_R14_0_Pos)                           /*!< LCD PAL87: R14_0 Mask               */
-#define LCD_PAL87_G14_0_Pos                                   21                                                        /*!< LCD PAL87: G14_0 Position           */
-#define LCD_PAL87_G14_0_Msk                                   (0x1fUL << LCD_PAL87_G14_0_Pos)                           /*!< LCD PAL87: G14_0 Mask               */
-#define LCD_PAL87_B14_0_Pos                                   26                                                        /*!< LCD PAL87: B14_0 Position           */
-#define LCD_PAL87_B14_0_Msk                                   (0x1fUL << LCD_PAL87_B14_0_Pos)                           /*!< LCD PAL87: B14_0 Mask               */
-#define LCD_PAL87_I1_Pos                                      31                                                        /*!< LCD PAL87: I1 Position              */
-#define LCD_PAL87_I1_Msk                                      (0x01UL << LCD_PAL87_I1_Pos)                              /*!< LCD PAL87: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL88  -------------------------------------------
-#define LCD_PAL88_R04_0_Pos                                   0                                                         /*!< LCD PAL88: R04_0 Position           */
-#define LCD_PAL88_R04_0_Msk                                   (0x1fUL << LCD_PAL88_R04_0_Pos)                           /*!< LCD PAL88: R04_0 Mask               */
-#define LCD_PAL88_G04_0_Pos                                   5                                                         /*!< LCD PAL88: G04_0 Position           */
-#define LCD_PAL88_G04_0_Msk                                   (0x1fUL << LCD_PAL88_G04_0_Pos)                           /*!< LCD PAL88: G04_0 Mask               */
-#define LCD_PAL88_B04_0_Pos                                   10                                                        /*!< LCD PAL88: B04_0 Position           */
-#define LCD_PAL88_B04_0_Msk                                   (0x1fUL << LCD_PAL88_B04_0_Pos)                           /*!< LCD PAL88: B04_0 Mask               */
-#define LCD_PAL88_I0_Pos                                      15                                                        /*!< LCD PAL88: I0 Position              */
-#define LCD_PAL88_I0_Msk                                      (0x01UL << LCD_PAL88_I0_Pos)                              /*!< LCD PAL88: I0 Mask                  */
-#define LCD_PAL88_R14_0_Pos                                   16                                                        /*!< LCD PAL88: R14_0 Position           */
-#define LCD_PAL88_R14_0_Msk                                   (0x1fUL << LCD_PAL88_R14_0_Pos)                           /*!< LCD PAL88: R14_0 Mask               */
-#define LCD_PAL88_G14_0_Pos                                   21                                                        /*!< LCD PAL88: G14_0 Position           */
-#define LCD_PAL88_G14_0_Msk                                   (0x1fUL << LCD_PAL88_G14_0_Pos)                           /*!< LCD PAL88: G14_0 Mask               */
-#define LCD_PAL88_B14_0_Pos                                   26                                                        /*!< LCD PAL88: B14_0 Position           */
-#define LCD_PAL88_B14_0_Msk                                   (0x1fUL << LCD_PAL88_B14_0_Pos)                           /*!< LCD PAL88: B14_0 Mask               */
-#define LCD_PAL88_I1_Pos                                      31                                                        /*!< LCD PAL88: I1 Position              */
-#define LCD_PAL88_I1_Msk                                      (0x01UL << LCD_PAL88_I1_Pos)                              /*!< LCD PAL88: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL89  -------------------------------------------
-#define LCD_PAL89_R04_0_Pos                                   0                                                         /*!< LCD PAL89: R04_0 Position           */
-#define LCD_PAL89_R04_0_Msk                                   (0x1fUL << LCD_PAL89_R04_0_Pos)                           /*!< LCD PAL89: R04_0 Mask               */
-#define LCD_PAL89_G04_0_Pos                                   5                                                         /*!< LCD PAL89: G04_0 Position           */
-#define LCD_PAL89_G04_0_Msk                                   (0x1fUL << LCD_PAL89_G04_0_Pos)                           /*!< LCD PAL89: G04_0 Mask               */
-#define LCD_PAL89_B04_0_Pos                                   10                                                        /*!< LCD PAL89: B04_0 Position           */
-#define LCD_PAL89_B04_0_Msk                                   (0x1fUL << LCD_PAL89_B04_0_Pos)                           /*!< LCD PAL89: B04_0 Mask               */
-#define LCD_PAL89_I0_Pos                                      15                                                        /*!< LCD PAL89: I0 Position              */
-#define LCD_PAL89_I0_Msk                                      (0x01UL << LCD_PAL89_I0_Pos)                              /*!< LCD PAL89: I0 Mask                  */
-#define LCD_PAL89_R14_0_Pos                                   16                                                        /*!< LCD PAL89: R14_0 Position           */
-#define LCD_PAL89_R14_0_Msk                                   (0x1fUL << LCD_PAL89_R14_0_Pos)                           /*!< LCD PAL89: R14_0 Mask               */
-#define LCD_PAL89_G14_0_Pos                                   21                                                        /*!< LCD PAL89: G14_0 Position           */
-#define LCD_PAL89_G14_0_Msk                                   (0x1fUL << LCD_PAL89_G14_0_Pos)                           /*!< LCD PAL89: G14_0 Mask               */
-#define LCD_PAL89_B14_0_Pos                                   26                                                        /*!< LCD PAL89: B14_0 Position           */
-#define LCD_PAL89_B14_0_Msk                                   (0x1fUL << LCD_PAL89_B14_0_Pos)                           /*!< LCD PAL89: B14_0 Mask               */
-#define LCD_PAL89_I1_Pos                                      31                                                        /*!< LCD PAL89: I1 Position              */
-#define LCD_PAL89_I1_Msk                                      (0x01UL << LCD_PAL89_I1_Pos)                              /*!< LCD PAL89: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL90  -------------------------------------------
-#define LCD_PAL90_R04_0_Pos                                   0                                                         /*!< LCD PAL90: R04_0 Position           */
-#define LCD_PAL90_R04_0_Msk                                   (0x1fUL << LCD_PAL90_R04_0_Pos)                           /*!< LCD PAL90: R04_0 Mask               */
-#define LCD_PAL90_G04_0_Pos                                   5                                                         /*!< LCD PAL90: G04_0 Position           */
-#define LCD_PAL90_G04_0_Msk                                   (0x1fUL << LCD_PAL90_G04_0_Pos)                           /*!< LCD PAL90: G04_0 Mask               */
-#define LCD_PAL90_B04_0_Pos                                   10                                                        /*!< LCD PAL90: B04_0 Position           */
-#define LCD_PAL90_B04_0_Msk                                   (0x1fUL << LCD_PAL90_B04_0_Pos)                           /*!< LCD PAL90: B04_0 Mask               */
-#define LCD_PAL90_I0_Pos                                      15                                                        /*!< LCD PAL90: I0 Position              */
-#define LCD_PAL90_I0_Msk                                      (0x01UL << LCD_PAL90_I0_Pos)                              /*!< LCD PAL90: I0 Mask                  */
-#define LCD_PAL90_R14_0_Pos                                   16                                                        /*!< LCD PAL90: R14_0 Position           */
-#define LCD_PAL90_R14_0_Msk                                   (0x1fUL << LCD_PAL90_R14_0_Pos)                           /*!< LCD PAL90: R14_0 Mask               */
-#define LCD_PAL90_G14_0_Pos                                   21                                                        /*!< LCD PAL90: G14_0 Position           */
-#define LCD_PAL90_G14_0_Msk                                   (0x1fUL << LCD_PAL90_G14_0_Pos)                           /*!< LCD PAL90: G14_0 Mask               */
-#define LCD_PAL90_B14_0_Pos                                   26                                                        /*!< LCD PAL90: B14_0 Position           */
-#define LCD_PAL90_B14_0_Msk                                   (0x1fUL << LCD_PAL90_B14_0_Pos)                           /*!< LCD PAL90: B14_0 Mask               */
-#define LCD_PAL90_I1_Pos                                      31                                                        /*!< LCD PAL90: I1 Position              */
-#define LCD_PAL90_I1_Msk                                      (0x01UL << LCD_PAL90_I1_Pos)                              /*!< LCD PAL90: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL91  -------------------------------------------
-#define LCD_PAL91_R04_0_Pos                                   0                                                         /*!< LCD PAL91: R04_0 Position           */
-#define LCD_PAL91_R04_0_Msk                                   (0x1fUL << LCD_PAL91_R04_0_Pos)                           /*!< LCD PAL91: R04_0 Mask               */
-#define LCD_PAL91_G04_0_Pos                                   5                                                         /*!< LCD PAL91: G04_0 Position           */
-#define LCD_PAL91_G04_0_Msk                                   (0x1fUL << LCD_PAL91_G04_0_Pos)                           /*!< LCD PAL91: G04_0 Mask               */
-#define LCD_PAL91_B04_0_Pos                                   10                                                        /*!< LCD PAL91: B04_0 Position           */
-#define LCD_PAL91_B04_0_Msk                                   (0x1fUL << LCD_PAL91_B04_0_Pos)                           /*!< LCD PAL91: B04_0 Mask               */
-#define LCD_PAL91_I0_Pos                                      15                                                        /*!< LCD PAL91: I0 Position              */
-#define LCD_PAL91_I0_Msk                                      (0x01UL << LCD_PAL91_I0_Pos)                              /*!< LCD PAL91: I0 Mask                  */
-#define LCD_PAL91_R14_0_Pos                                   16                                                        /*!< LCD PAL91: R14_0 Position           */
-#define LCD_PAL91_R14_0_Msk                                   (0x1fUL << LCD_PAL91_R14_0_Pos)                           /*!< LCD PAL91: R14_0 Mask               */
-#define LCD_PAL91_G14_0_Pos                                   21                                                        /*!< LCD PAL91: G14_0 Position           */
-#define LCD_PAL91_G14_0_Msk                                   (0x1fUL << LCD_PAL91_G14_0_Pos)                           /*!< LCD PAL91: G14_0 Mask               */
-#define LCD_PAL91_B14_0_Pos                                   26                                                        /*!< LCD PAL91: B14_0 Position           */
-#define LCD_PAL91_B14_0_Msk                                   (0x1fUL << LCD_PAL91_B14_0_Pos)                           /*!< LCD PAL91: B14_0 Mask               */
-#define LCD_PAL91_I1_Pos                                      31                                                        /*!< LCD PAL91: I1 Position              */
-#define LCD_PAL91_I1_Msk                                      (0x01UL << LCD_PAL91_I1_Pos)                              /*!< LCD PAL91: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL92  -------------------------------------------
-#define LCD_PAL92_R04_0_Pos                                   0                                                         /*!< LCD PAL92: R04_0 Position           */
-#define LCD_PAL92_R04_0_Msk                                   (0x1fUL << LCD_PAL92_R04_0_Pos)                           /*!< LCD PAL92: R04_0 Mask               */
-#define LCD_PAL92_G04_0_Pos                                   5                                                         /*!< LCD PAL92: G04_0 Position           */
-#define LCD_PAL92_G04_0_Msk                                   (0x1fUL << LCD_PAL92_G04_0_Pos)                           /*!< LCD PAL92: G04_0 Mask               */
-#define LCD_PAL92_B04_0_Pos                                   10                                                        /*!< LCD PAL92: B04_0 Position           */
-#define LCD_PAL92_B04_0_Msk                                   (0x1fUL << LCD_PAL92_B04_0_Pos)                           /*!< LCD PAL92: B04_0 Mask               */
-#define LCD_PAL92_I0_Pos                                      15                                                        /*!< LCD PAL92: I0 Position              */
-#define LCD_PAL92_I0_Msk                                      (0x01UL << LCD_PAL92_I0_Pos)                              /*!< LCD PAL92: I0 Mask                  */
-#define LCD_PAL92_R14_0_Pos                                   16                                                        /*!< LCD PAL92: R14_0 Position           */
-#define LCD_PAL92_R14_0_Msk                                   (0x1fUL << LCD_PAL92_R14_0_Pos)                           /*!< LCD PAL92: R14_0 Mask               */
-#define LCD_PAL92_G14_0_Pos                                   21                                                        /*!< LCD PAL92: G14_0 Position           */
-#define LCD_PAL92_G14_0_Msk                                   (0x1fUL << LCD_PAL92_G14_0_Pos)                           /*!< LCD PAL92: G14_0 Mask               */
-#define LCD_PAL92_B14_0_Pos                                   26                                                        /*!< LCD PAL92: B14_0 Position           */
-#define LCD_PAL92_B14_0_Msk                                   (0x1fUL << LCD_PAL92_B14_0_Pos)                           /*!< LCD PAL92: B14_0 Mask               */
-#define LCD_PAL92_I1_Pos                                      31                                                        /*!< LCD PAL92: I1 Position              */
-#define LCD_PAL92_I1_Msk                                      (0x01UL << LCD_PAL92_I1_Pos)                              /*!< LCD PAL92: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL93  -------------------------------------------
-#define LCD_PAL93_R04_0_Pos                                   0                                                         /*!< LCD PAL93: R04_0 Position           */
-#define LCD_PAL93_R04_0_Msk                                   (0x1fUL << LCD_PAL93_R04_0_Pos)                           /*!< LCD PAL93: R04_0 Mask               */
-#define LCD_PAL93_G04_0_Pos                                   5                                                         /*!< LCD PAL93: G04_0 Position           */
-#define LCD_PAL93_G04_0_Msk                                   (0x1fUL << LCD_PAL93_G04_0_Pos)                           /*!< LCD PAL93: G04_0 Mask               */
-#define LCD_PAL93_B04_0_Pos                                   10                                                        /*!< LCD PAL93: B04_0 Position           */
-#define LCD_PAL93_B04_0_Msk                                   (0x1fUL << LCD_PAL93_B04_0_Pos)                           /*!< LCD PAL93: B04_0 Mask               */
-#define LCD_PAL93_I0_Pos                                      15                                                        /*!< LCD PAL93: I0 Position              */
-#define LCD_PAL93_I0_Msk                                      (0x01UL << LCD_PAL93_I0_Pos)                              /*!< LCD PAL93: I0 Mask                  */
-#define LCD_PAL93_R14_0_Pos                                   16                                                        /*!< LCD PAL93: R14_0 Position           */
-#define LCD_PAL93_R14_0_Msk                                   (0x1fUL << LCD_PAL93_R14_0_Pos)                           /*!< LCD PAL93: R14_0 Mask               */
-#define LCD_PAL93_G14_0_Pos                                   21                                                        /*!< LCD PAL93: G14_0 Position           */
-#define LCD_PAL93_G14_0_Msk                                   (0x1fUL << LCD_PAL93_G14_0_Pos)                           /*!< LCD PAL93: G14_0 Mask               */
-#define LCD_PAL93_B14_0_Pos                                   26                                                        /*!< LCD PAL93: B14_0 Position           */
-#define LCD_PAL93_B14_0_Msk                                   (0x1fUL << LCD_PAL93_B14_0_Pos)                           /*!< LCD PAL93: B14_0 Mask               */
-#define LCD_PAL93_I1_Pos                                      31                                                        /*!< LCD PAL93: I1 Position              */
-#define LCD_PAL93_I1_Msk                                      (0x01UL << LCD_PAL93_I1_Pos)                              /*!< LCD PAL93: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL94  -------------------------------------------
-#define LCD_PAL94_R04_0_Pos                                   0                                                         /*!< LCD PAL94: R04_0 Position           */
-#define LCD_PAL94_R04_0_Msk                                   (0x1fUL << LCD_PAL94_R04_0_Pos)                           /*!< LCD PAL94: R04_0 Mask               */
-#define LCD_PAL94_G04_0_Pos                                   5                                                         /*!< LCD PAL94: G04_0 Position           */
-#define LCD_PAL94_G04_0_Msk                                   (0x1fUL << LCD_PAL94_G04_0_Pos)                           /*!< LCD PAL94: G04_0 Mask               */
-#define LCD_PAL94_B04_0_Pos                                   10                                                        /*!< LCD PAL94: B04_0 Position           */
-#define LCD_PAL94_B04_0_Msk                                   (0x1fUL << LCD_PAL94_B04_0_Pos)                           /*!< LCD PAL94: B04_0 Mask               */
-#define LCD_PAL94_I0_Pos                                      15                                                        /*!< LCD PAL94: I0 Position              */
-#define LCD_PAL94_I0_Msk                                      (0x01UL << LCD_PAL94_I0_Pos)                              /*!< LCD PAL94: I0 Mask                  */
-#define LCD_PAL94_R14_0_Pos                                   16                                                        /*!< LCD PAL94: R14_0 Position           */
-#define LCD_PAL94_R14_0_Msk                                   (0x1fUL << LCD_PAL94_R14_0_Pos)                           /*!< LCD PAL94: R14_0 Mask               */
-#define LCD_PAL94_G14_0_Pos                                   21                                                        /*!< LCD PAL94: G14_0 Position           */
-#define LCD_PAL94_G14_0_Msk                                   (0x1fUL << LCD_PAL94_G14_0_Pos)                           /*!< LCD PAL94: G14_0 Mask               */
-#define LCD_PAL94_B14_0_Pos                                   26                                                        /*!< LCD PAL94: B14_0 Position           */
-#define LCD_PAL94_B14_0_Msk                                   (0x1fUL << LCD_PAL94_B14_0_Pos)                           /*!< LCD PAL94: B14_0 Mask               */
-#define LCD_PAL94_I1_Pos                                      31                                                        /*!< LCD PAL94: I1 Position              */
-#define LCD_PAL94_I1_Msk                                      (0x01UL << LCD_PAL94_I1_Pos)                              /*!< LCD PAL94: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL95  -------------------------------------------
-#define LCD_PAL95_R04_0_Pos                                   0                                                         /*!< LCD PAL95: R04_0 Position           */
-#define LCD_PAL95_R04_0_Msk                                   (0x1fUL << LCD_PAL95_R04_0_Pos)                           /*!< LCD PAL95: R04_0 Mask               */
-#define LCD_PAL95_G04_0_Pos                                   5                                                         /*!< LCD PAL95: G04_0 Position           */
-#define LCD_PAL95_G04_0_Msk                                   (0x1fUL << LCD_PAL95_G04_0_Pos)                           /*!< LCD PAL95: G04_0 Mask               */
-#define LCD_PAL95_B04_0_Pos                                   10                                                        /*!< LCD PAL95: B04_0 Position           */
-#define LCD_PAL95_B04_0_Msk                                   (0x1fUL << LCD_PAL95_B04_0_Pos)                           /*!< LCD PAL95: B04_0 Mask               */
-#define LCD_PAL95_I0_Pos                                      15                                                        /*!< LCD PAL95: I0 Position              */
-#define LCD_PAL95_I0_Msk                                      (0x01UL << LCD_PAL95_I0_Pos)                              /*!< LCD PAL95: I0 Mask                  */
-#define LCD_PAL95_R14_0_Pos                                   16                                                        /*!< LCD PAL95: R14_0 Position           */
-#define LCD_PAL95_R14_0_Msk                                   (0x1fUL << LCD_PAL95_R14_0_Pos)                           /*!< LCD PAL95: R14_0 Mask               */
-#define LCD_PAL95_G14_0_Pos                                   21                                                        /*!< LCD PAL95: G14_0 Position           */
-#define LCD_PAL95_G14_0_Msk                                   (0x1fUL << LCD_PAL95_G14_0_Pos)                           /*!< LCD PAL95: G14_0 Mask               */
-#define LCD_PAL95_B14_0_Pos                                   26                                                        /*!< LCD PAL95: B14_0 Position           */
-#define LCD_PAL95_B14_0_Msk                                   (0x1fUL << LCD_PAL95_B14_0_Pos)                           /*!< LCD PAL95: B14_0 Mask               */
-#define LCD_PAL95_I1_Pos                                      31                                                        /*!< LCD PAL95: I1 Position              */
-#define LCD_PAL95_I1_Msk                                      (0x01UL << LCD_PAL95_I1_Pos)                              /*!< LCD PAL95: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL96  -------------------------------------------
-#define LCD_PAL96_R04_0_Pos                                   0                                                         /*!< LCD PAL96: R04_0 Position           */
-#define LCD_PAL96_R04_0_Msk                                   (0x1fUL << LCD_PAL96_R04_0_Pos)                           /*!< LCD PAL96: R04_0 Mask               */
-#define LCD_PAL96_G04_0_Pos                                   5                                                         /*!< LCD PAL96: G04_0 Position           */
-#define LCD_PAL96_G04_0_Msk                                   (0x1fUL << LCD_PAL96_G04_0_Pos)                           /*!< LCD PAL96: G04_0 Mask               */
-#define LCD_PAL96_B04_0_Pos                                   10                                                        /*!< LCD PAL96: B04_0 Position           */
-#define LCD_PAL96_B04_0_Msk                                   (0x1fUL << LCD_PAL96_B04_0_Pos)                           /*!< LCD PAL96: B04_0 Mask               */
-#define LCD_PAL96_I0_Pos                                      15                                                        /*!< LCD PAL96: I0 Position              */
-#define LCD_PAL96_I0_Msk                                      (0x01UL << LCD_PAL96_I0_Pos)                              /*!< LCD PAL96: I0 Mask                  */
-#define LCD_PAL96_R14_0_Pos                                   16                                                        /*!< LCD PAL96: R14_0 Position           */
-#define LCD_PAL96_R14_0_Msk                                   (0x1fUL << LCD_PAL96_R14_0_Pos)                           /*!< LCD PAL96: R14_0 Mask               */
-#define LCD_PAL96_G14_0_Pos                                   21                                                        /*!< LCD PAL96: G14_0 Position           */
-#define LCD_PAL96_G14_0_Msk                                   (0x1fUL << LCD_PAL96_G14_0_Pos)                           /*!< LCD PAL96: G14_0 Mask               */
-#define LCD_PAL96_B14_0_Pos                                   26                                                        /*!< LCD PAL96: B14_0 Position           */
-#define LCD_PAL96_B14_0_Msk                                   (0x1fUL << LCD_PAL96_B14_0_Pos)                           /*!< LCD PAL96: B14_0 Mask               */
-#define LCD_PAL96_I1_Pos                                      31                                                        /*!< LCD PAL96: I1 Position              */
-#define LCD_PAL96_I1_Msk                                      (0x01UL << LCD_PAL96_I1_Pos)                              /*!< LCD PAL96: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL97  -------------------------------------------
-#define LCD_PAL97_R04_0_Pos                                   0                                                         /*!< LCD PAL97: R04_0 Position           */
-#define LCD_PAL97_R04_0_Msk                                   (0x1fUL << LCD_PAL97_R04_0_Pos)                           /*!< LCD PAL97: R04_0 Mask               */
-#define LCD_PAL97_G04_0_Pos                                   5                                                         /*!< LCD PAL97: G04_0 Position           */
-#define LCD_PAL97_G04_0_Msk                                   (0x1fUL << LCD_PAL97_G04_0_Pos)                           /*!< LCD PAL97: G04_0 Mask               */
-#define LCD_PAL97_B04_0_Pos                                   10                                                        /*!< LCD PAL97: B04_0 Position           */
-#define LCD_PAL97_B04_0_Msk                                   (0x1fUL << LCD_PAL97_B04_0_Pos)                           /*!< LCD PAL97: B04_0 Mask               */
-#define LCD_PAL97_I0_Pos                                      15                                                        /*!< LCD PAL97: I0 Position              */
-#define LCD_PAL97_I0_Msk                                      (0x01UL << LCD_PAL97_I0_Pos)                              /*!< LCD PAL97: I0 Mask                  */
-#define LCD_PAL97_R14_0_Pos                                   16                                                        /*!< LCD PAL97: R14_0 Position           */
-#define LCD_PAL97_R14_0_Msk                                   (0x1fUL << LCD_PAL97_R14_0_Pos)                           /*!< LCD PAL97: R14_0 Mask               */
-#define LCD_PAL97_G14_0_Pos                                   21                                                        /*!< LCD PAL97: G14_0 Position           */
-#define LCD_PAL97_G14_0_Msk                                   (0x1fUL << LCD_PAL97_G14_0_Pos)                           /*!< LCD PAL97: G14_0 Mask               */
-#define LCD_PAL97_B14_0_Pos                                   26                                                        /*!< LCD PAL97: B14_0 Position           */
-#define LCD_PAL97_B14_0_Msk                                   (0x1fUL << LCD_PAL97_B14_0_Pos)                           /*!< LCD PAL97: B14_0 Mask               */
-#define LCD_PAL97_I1_Pos                                      31                                                        /*!< LCD PAL97: I1 Position              */
-#define LCD_PAL97_I1_Msk                                      (0x01UL << LCD_PAL97_I1_Pos)                              /*!< LCD PAL97: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL98  -------------------------------------------
-#define LCD_PAL98_R04_0_Pos                                   0                                                         /*!< LCD PAL98: R04_0 Position           */
-#define LCD_PAL98_R04_0_Msk                                   (0x1fUL << LCD_PAL98_R04_0_Pos)                           /*!< LCD PAL98: R04_0 Mask               */
-#define LCD_PAL98_G04_0_Pos                                   5                                                         /*!< LCD PAL98: G04_0 Position           */
-#define LCD_PAL98_G04_0_Msk                                   (0x1fUL << LCD_PAL98_G04_0_Pos)                           /*!< LCD PAL98: G04_0 Mask               */
-#define LCD_PAL98_B04_0_Pos                                   10                                                        /*!< LCD PAL98: B04_0 Position           */
-#define LCD_PAL98_B04_0_Msk                                   (0x1fUL << LCD_PAL98_B04_0_Pos)                           /*!< LCD PAL98: B04_0 Mask               */
-#define LCD_PAL98_I0_Pos                                      15                                                        /*!< LCD PAL98: I0 Position              */
-#define LCD_PAL98_I0_Msk                                      (0x01UL << LCD_PAL98_I0_Pos)                              /*!< LCD PAL98: I0 Mask                  */
-#define LCD_PAL98_R14_0_Pos                                   16                                                        /*!< LCD PAL98: R14_0 Position           */
-#define LCD_PAL98_R14_0_Msk                                   (0x1fUL << LCD_PAL98_R14_0_Pos)                           /*!< LCD PAL98: R14_0 Mask               */
-#define LCD_PAL98_G14_0_Pos                                   21                                                        /*!< LCD PAL98: G14_0 Position           */
-#define LCD_PAL98_G14_0_Msk                                   (0x1fUL << LCD_PAL98_G14_0_Pos)                           /*!< LCD PAL98: G14_0 Mask               */
-#define LCD_PAL98_B14_0_Pos                                   26                                                        /*!< LCD PAL98: B14_0 Position           */
-#define LCD_PAL98_B14_0_Msk                                   (0x1fUL << LCD_PAL98_B14_0_Pos)                           /*!< LCD PAL98: B14_0 Mask               */
-#define LCD_PAL98_I1_Pos                                      31                                                        /*!< LCD PAL98: I1 Position              */
-#define LCD_PAL98_I1_Msk                                      (0x01UL << LCD_PAL98_I1_Pos)                              /*!< LCD PAL98: I1 Mask                  */
-
-// ----------------------------------------  LCD_PAL99  -------------------------------------------
-#define LCD_PAL99_R04_0_Pos                                   0                                                         /*!< LCD PAL99: R04_0 Position           */
-#define LCD_PAL99_R04_0_Msk                                   (0x1fUL << LCD_PAL99_R04_0_Pos)                           /*!< LCD PAL99: R04_0 Mask               */
-#define LCD_PAL99_G04_0_Pos                                   5                                                         /*!< LCD PAL99: G04_0 Position           */
-#define LCD_PAL99_G04_0_Msk                                   (0x1fUL << LCD_PAL99_G04_0_Pos)                           /*!< LCD PAL99: G04_0 Mask               */
-#define LCD_PAL99_B04_0_Pos                                   10                                                        /*!< LCD PAL99: B04_0 Position           */
-#define LCD_PAL99_B04_0_Msk                                   (0x1fUL << LCD_PAL99_B04_0_Pos)                           /*!< LCD PAL99: B04_0 Mask               */
-#define LCD_PAL99_I0_Pos                                      15                                                        /*!< LCD PAL99: I0 Position              */
-#define LCD_PAL99_I0_Msk                                      (0x01UL << LCD_PAL99_I0_Pos)                              /*!< LCD PAL99: I0 Mask                  */
-#define LCD_PAL99_R14_0_Pos                                   16                                                        /*!< LCD PAL99: R14_0 Position           */
-#define LCD_PAL99_R14_0_Msk                                   (0x1fUL << LCD_PAL99_R14_0_Pos)                           /*!< LCD PAL99: R14_0 Mask               */
-#define LCD_PAL99_G14_0_Pos                                   21                                                        /*!< LCD PAL99: G14_0 Position           */
-#define LCD_PAL99_G14_0_Msk                                   (0x1fUL << LCD_PAL99_G14_0_Pos)                           /*!< LCD PAL99: G14_0 Mask               */
-#define LCD_PAL99_B14_0_Pos                                   26                                                        /*!< LCD PAL99: B14_0 Position           */
-#define LCD_PAL99_B14_0_Msk                                   (0x1fUL << LCD_PAL99_B14_0_Pos)                           /*!< LCD PAL99: B14_0 Mask               */
-#define LCD_PAL99_I1_Pos                                      31                                                        /*!< LCD PAL99: I1 Position              */
-#define LCD_PAL99_I1_Msk                                      (0x01UL << LCD_PAL99_I1_Pos)                              /*!< LCD PAL99: I1 Mask                  */
-
-// ---------------------------------------  LCD_PAL100  -------------------------------------------
-#define LCD_PAL100_R04_0_Pos                                  0                                                         /*!< LCD PAL100: R04_0 Position          */
-#define LCD_PAL100_R04_0_Msk                                  (0x1fUL << LCD_PAL100_R04_0_Pos)                          /*!< LCD PAL100: R04_0 Mask              */
-#define LCD_PAL100_G04_0_Pos                                  5                                                         /*!< LCD PAL100: G04_0 Position          */
-#define LCD_PAL100_G04_0_Msk                                  (0x1fUL << LCD_PAL100_G04_0_Pos)                          /*!< LCD PAL100: G04_0 Mask              */
-#define LCD_PAL100_B04_0_Pos                                  10                                                        /*!< LCD PAL100: B04_0 Position          */
-#define LCD_PAL100_B04_0_Msk                                  (0x1fUL << LCD_PAL100_B04_0_Pos)                          /*!< LCD PAL100: B04_0 Mask              */
-#define LCD_PAL100_I0_Pos                                     15                                                        /*!< LCD PAL100: I0 Position             */
-#define LCD_PAL100_I0_Msk                                     (0x01UL << LCD_PAL100_I0_Pos)                             /*!< LCD PAL100: I0 Mask                 */
-#define LCD_PAL100_R14_0_Pos                                  16                                                        /*!< LCD PAL100: R14_0 Position          */
-#define LCD_PAL100_R14_0_Msk                                  (0x1fUL << LCD_PAL100_R14_0_Pos)                          /*!< LCD PAL100: R14_0 Mask              */
-#define LCD_PAL100_G14_0_Pos                                  21                                                        /*!< LCD PAL100: G14_0 Position          */
-#define LCD_PAL100_G14_0_Msk                                  (0x1fUL << LCD_PAL100_G14_0_Pos)                          /*!< LCD PAL100: G14_0 Mask              */
-#define LCD_PAL100_B14_0_Pos                                  26                                                        /*!< LCD PAL100: B14_0 Position          */
-#define LCD_PAL100_B14_0_Msk                                  (0x1fUL << LCD_PAL100_B14_0_Pos)                          /*!< LCD PAL100: B14_0 Mask              */
-#define LCD_PAL100_I1_Pos                                     31                                                        /*!< LCD PAL100: I1 Position             */
-#define LCD_PAL100_I1_Msk                                     (0x01UL << LCD_PAL100_I1_Pos)                             /*!< LCD PAL100: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL101  -------------------------------------------
-#define LCD_PAL101_R04_0_Pos                                  0                                                         /*!< LCD PAL101: R04_0 Position          */
-#define LCD_PAL101_R04_0_Msk                                  (0x1fUL << LCD_PAL101_R04_0_Pos)                          /*!< LCD PAL101: R04_0 Mask              */
-#define LCD_PAL101_G04_0_Pos                                  5                                                         /*!< LCD PAL101: G04_0 Position          */
-#define LCD_PAL101_G04_0_Msk                                  (0x1fUL << LCD_PAL101_G04_0_Pos)                          /*!< LCD PAL101: G04_0 Mask              */
-#define LCD_PAL101_B04_0_Pos                                  10                                                        /*!< LCD PAL101: B04_0 Position          */
-#define LCD_PAL101_B04_0_Msk                                  (0x1fUL << LCD_PAL101_B04_0_Pos)                          /*!< LCD PAL101: B04_0 Mask              */
-#define LCD_PAL101_I0_Pos                                     15                                                        /*!< LCD PAL101: I0 Position             */
-#define LCD_PAL101_I0_Msk                                     (0x01UL << LCD_PAL101_I0_Pos)                             /*!< LCD PAL101: I0 Mask                 */
-#define LCD_PAL101_R14_0_Pos                                  16                                                        /*!< LCD PAL101: R14_0 Position          */
-#define LCD_PAL101_R14_0_Msk                                  (0x1fUL << LCD_PAL101_R14_0_Pos)                          /*!< LCD PAL101: R14_0 Mask              */
-#define LCD_PAL101_G14_0_Pos                                  21                                                        /*!< LCD PAL101: G14_0 Position          */
-#define LCD_PAL101_G14_0_Msk                                  (0x1fUL << LCD_PAL101_G14_0_Pos)                          /*!< LCD PAL101: G14_0 Mask              */
-#define LCD_PAL101_B14_0_Pos                                  26                                                        /*!< LCD PAL101: B14_0 Position          */
-#define LCD_PAL101_B14_0_Msk                                  (0x1fUL << LCD_PAL101_B14_0_Pos)                          /*!< LCD PAL101: B14_0 Mask              */
-#define LCD_PAL101_I1_Pos                                     31                                                        /*!< LCD PAL101: I1 Position             */
-#define LCD_PAL101_I1_Msk                                     (0x01UL << LCD_PAL101_I1_Pos)                             /*!< LCD PAL101: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL102  -------------------------------------------
-#define LCD_PAL102_R04_0_Pos                                  0                                                         /*!< LCD PAL102: R04_0 Position          */
-#define LCD_PAL102_R04_0_Msk                                  (0x1fUL << LCD_PAL102_R04_0_Pos)                          /*!< LCD PAL102: R04_0 Mask              */
-#define LCD_PAL102_G04_0_Pos                                  5                                                         /*!< LCD PAL102: G04_0 Position          */
-#define LCD_PAL102_G04_0_Msk                                  (0x1fUL << LCD_PAL102_G04_0_Pos)                          /*!< LCD PAL102: G04_0 Mask              */
-#define LCD_PAL102_B04_0_Pos                                  10                                                        /*!< LCD PAL102: B04_0 Position          */
-#define LCD_PAL102_B04_0_Msk                                  (0x1fUL << LCD_PAL102_B04_0_Pos)                          /*!< LCD PAL102: B04_0 Mask              */
-#define LCD_PAL102_I0_Pos                                     15                                                        /*!< LCD PAL102: I0 Position             */
-#define LCD_PAL102_I0_Msk                                     (0x01UL << LCD_PAL102_I0_Pos)                             /*!< LCD PAL102: I0 Mask                 */
-#define LCD_PAL102_R14_0_Pos                                  16                                                        /*!< LCD PAL102: R14_0 Position          */
-#define LCD_PAL102_R14_0_Msk                                  (0x1fUL << LCD_PAL102_R14_0_Pos)                          /*!< LCD PAL102: R14_0 Mask              */
-#define LCD_PAL102_G14_0_Pos                                  21                                                        /*!< LCD PAL102: G14_0 Position          */
-#define LCD_PAL102_G14_0_Msk                                  (0x1fUL << LCD_PAL102_G14_0_Pos)                          /*!< LCD PAL102: G14_0 Mask              */
-#define LCD_PAL102_B14_0_Pos                                  26                                                        /*!< LCD PAL102: B14_0 Position          */
-#define LCD_PAL102_B14_0_Msk                                  (0x1fUL << LCD_PAL102_B14_0_Pos)                          /*!< LCD PAL102: B14_0 Mask              */
-#define LCD_PAL102_I1_Pos                                     31                                                        /*!< LCD PAL102: I1 Position             */
-#define LCD_PAL102_I1_Msk                                     (0x01UL << LCD_PAL102_I1_Pos)                             /*!< LCD PAL102: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL103  -------------------------------------------
-#define LCD_PAL103_R04_0_Pos                                  0                                                         /*!< LCD PAL103: R04_0 Position          */
-#define LCD_PAL103_R04_0_Msk                                  (0x1fUL << LCD_PAL103_R04_0_Pos)                          /*!< LCD PAL103: R04_0 Mask              */
-#define LCD_PAL103_G04_0_Pos                                  5                                                         /*!< LCD PAL103: G04_0 Position          */
-#define LCD_PAL103_G04_0_Msk                                  (0x1fUL << LCD_PAL103_G04_0_Pos)                          /*!< LCD PAL103: G04_0 Mask              */
-#define LCD_PAL103_B04_0_Pos                                  10                                                        /*!< LCD PAL103: B04_0 Position          */
-#define LCD_PAL103_B04_0_Msk                                  (0x1fUL << LCD_PAL103_B04_0_Pos)                          /*!< LCD PAL103: B04_0 Mask              */
-#define LCD_PAL103_I0_Pos                                     15                                                        /*!< LCD PAL103: I0 Position             */
-#define LCD_PAL103_I0_Msk                                     (0x01UL << LCD_PAL103_I0_Pos)                             /*!< LCD PAL103: I0 Mask                 */
-#define LCD_PAL103_R14_0_Pos                                  16                                                        /*!< LCD PAL103: R14_0 Position          */
-#define LCD_PAL103_R14_0_Msk                                  (0x1fUL << LCD_PAL103_R14_0_Pos)                          /*!< LCD PAL103: R14_0 Mask              */
-#define LCD_PAL103_G14_0_Pos                                  21                                                        /*!< LCD PAL103: G14_0 Position          */
-#define LCD_PAL103_G14_0_Msk                                  (0x1fUL << LCD_PAL103_G14_0_Pos)                          /*!< LCD PAL103: G14_0 Mask              */
-#define LCD_PAL103_B14_0_Pos                                  26                                                        /*!< LCD PAL103: B14_0 Position          */
-#define LCD_PAL103_B14_0_Msk                                  (0x1fUL << LCD_PAL103_B14_0_Pos)                          /*!< LCD PAL103: B14_0 Mask              */
-#define LCD_PAL103_I1_Pos                                     31                                                        /*!< LCD PAL103: I1 Position             */
-#define LCD_PAL103_I1_Msk                                     (0x01UL << LCD_PAL103_I1_Pos)                             /*!< LCD PAL103: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL104  -------------------------------------------
-#define LCD_PAL104_R04_0_Pos                                  0                                                         /*!< LCD PAL104: R04_0 Position          */
-#define LCD_PAL104_R04_0_Msk                                  (0x1fUL << LCD_PAL104_R04_0_Pos)                          /*!< LCD PAL104: R04_0 Mask              */
-#define LCD_PAL104_G04_0_Pos                                  5                                                         /*!< LCD PAL104: G04_0 Position          */
-#define LCD_PAL104_G04_0_Msk                                  (0x1fUL << LCD_PAL104_G04_0_Pos)                          /*!< LCD PAL104: G04_0 Mask              */
-#define LCD_PAL104_B04_0_Pos                                  10                                                        /*!< LCD PAL104: B04_0 Position          */
-#define LCD_PAL104_B04_0_Msk                                  (0x1fUL << LCD_PAL104_B04_0_Pos)                          /*!< LCD PAL104: B04_0 Mask              */
-#define LCD_PAL104_I0_Pos                                     15                                                        /*!< LCD PAL104: I0 Position             */
-#define LCD_PAL104_I0_Msk                                     (0x01UL << LCD_PAL104_I0_Pos)                             /*!< LCD PAL104: I0 Mask                 */
-#define LCD_PAL104_R14_0_Pos                                  16                                                        /*!< LCD PAL104: R14_0 Position          */
-#define LCD_PAL104_R14_0_Msk                                  (0x1fUL << LCD_PAL104_R14_0_Pos)                          /*!< LCD PAL104: R14_0 Mask              */
-#define LCD_PAL104_G14_0_Pos                                  21                                                        /*!< LCD PAL104: G14_0 Position          */
-#define LCD_PAL104_G14_0_Msk                                  (0x1fUL << LCD_PAL104_G14_0_Pos)                          /*!< LCD PAL104: G14_0 Mask              */
-#define LCD_PAL104_B14_0_Pos                                  26                                                        /*!< LCD PAL104: B14_0 Position          */
-#define LCD_PAL104_B14_0_Msk                                  (0x1fUL << LCD_PAL104_B14_0_Pos)                          /*!< LCD PAL104: B14_0 Mask              */
-#define LCD_PAL104_I1_Pos                                     31                                                        /*!< LCD PAL104: I1 Position             */
-#define LCD_PAL104_I1_Msk                                     (0x01UL << LCD_PAL104_I1_Pos)                             /*!< LCD PAL104: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL105  -------------------------------------------
-#define LCD_PAL105_R04_0_Pos                                  0                                                         /*!< LCD PAL105: R04_0 Position          */
-#define LCD_PAL105_R04_0_Msk                                  (0x1fUL << LCD_PAL105_R04_0_Pos)                          /*!< LCD PAL105: R04_0 Mask              */
-#define LCD_PAL105_G04_0_Pos                                  5                                                         /*!< LCD PAL105: G04_0 Position          */
-#define LCD_PAL105_G04_0_Msk                                  (0x1fUL << LCD_PAL105_G04_0_Pos)                          /*!< LCD PAL105: G04_0 Mask              */
-#define LCD_PAL105_B04_0_Pos                                  10                                                        /*!< LCD PAL105: B04_0 Position          */
-#define LCD_PAL105_B04_0_Msk                                  (0x1fUL << LCD_PAL105_B04_0_Pos)                          /*!< LCD PAL105: B04_0 Mask              */
-#define LCD_PAL105_I0_Pos                                     15                                                        /*!< LCD PAL105: I0 Position             */
-#define LCD_PAL105_I0_Msk                                     (0x01UL << LCD_PAL105_I0_Pos)                             /*!< LCD PAL105: I0 Mask                 */
-#define LCD_PAL105_R14_0_Pos                                  16                                                        /*!< LCD PAL105: R14_0 Position          */
-#define LCD_PAL105_R14_0_Msk                                  (0x1fUL << LCD_PAL105_R14_0_Pos)                          /*!< LCD PAL105: R14_0 Mask              */
-#define LCD_PAL105_G14_0_Pos                                  21                                                        /*!< LCD PAL105: G14_0 Position          */
-#define LCD_PAL105_G14_0_Msk                                  (0x1fUL << LCD_PAL105_G14_0_Pos)                          /*!< LCD PAL105: G14_0 Mask              */
-#define LCD_PAL105_B14_0_Pos                                  26                                                        /*!< LCD PAL105: B14_0 Position          */
-#define LCD_PAL105_B14_0_Msk                                  (0x1fUL << LCD_PAL105_B14_0_Pos)                          /*!< LCD PAL105: B14_0 Mask              */
-#define LCD_PAL105_I1_Pos                                     31                                                        /*!< LCD PAL105: I1 Position             */
-#define LCD_PAL105_I1_Msk                                     (0x01UL << LCD_PAL105_I1_Pos)                             /*!< LCD PAL105: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL106  -------------------------------------------
-#define LCD_PAL106_R04_0_Pos                                  0                                                         /*!< LCD PAL106: R04_0 Position          */
-#define LCD_PAL106_R04_0_Msk                                  (0x1fUL << LCD_PAL106_R04_0_Pos)                          /*!< LCD PAL106: R04_0 Mask              */
-#define LCD_PAL106_G04_0_Pos                                  5                                                         /*!< LCD PAL106: G04_0 Position          */
-#define LCD_PAL106_G04_0_Msk                                  (0x1fUL << LCD_PAL106_G04_0_Pos)                          /*!< LCD PAL106: G04_0 Mask              */
-#define LCD_PAL106_B04_0_Pos                                  10                                                        /*!< LCD PAL106: B04_0 Position          */
-#define LCD_PAL106_B04_0_Msk                                  (0x1fUL << LCD_PAL106_B04_0_Pos)                          /*!< LCD PAL106: B04_0 Mask              */
-#define LCD_PAL106_I0_Pos                                     15                                                        /*!< LCD PAL106: I0 Position             */
-#define LCD_PAL106_I0_Msk                                     (0x01UL << LCD_PAL106_I0_Pos)                             /*!< LCD PAL106: I0 Mask                 */
-#define LCD_PAL106_R14_0_Pos                                  16                                                        /*!< LCD PAL106: R14_0 Position          */
-#define LCD_PAL106_R14_0_Msk                                  (0x1fUL << LCD_PAL106_R14_0_Pos)                          /*!< LCD PAL106: R14_0 Mask              */
-#define LCD_PAL106_G14_0_Pos                                  21                                                        /*!< LCD PAL106: G14_0 Position          */
-#define LCD_PAL106_G14_0_Msk                                  (0x1fUL << LCD_PAL106_G14_0_Pos)                          /*!< LCD PAL106: G14_0 Mask              */
-#define LCD_PAL106_B14_0_Pos                                  26                                                        /*!< LCD PAL106: B14_0 Position          */
-#define LCD_PAL106_B14_0_Msk                                  (0x1fUL << LCD_PAL106_B14_0_Pos)                          /*!< LCD PAL106: B14_0 Mask              */
-#define LCD_PAL106_I1_Pos                                     31                                                        /*!< LCD PAL106: I1 Position             */
-#define LCD_PAL106_I1_Msk                                     (0x01UL << LCD_PAL106_I1_Pos)                             /*!< LCD PAL106: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL107  -------------------------------------------
-#define LCD_PAL107_R04_0_Pos                                  0                                                         /*!< LCD PAL107: R04_0 Position          */
-#define LCD_PAL107_R04_0_Msk                                  (0x1fUL << LCD_PAL107_R04_0_Pos)                          /*!< LCD PAL107: R04_0 Mask              */
-#define LCD_PAL107_G04_0_Pos                                  5                                                         /*!< LCD PAL107: G04_0 Position          */
-#define LCD_PAL107_G04_0_Msk                                  (0x1fUL << LCD_PAL107_G04_0_Pos)                          /*!< LCD PAL107: G04_0 Mask              */
-#define LCD_PAL107_B04_0_Pos                                  10                                                        /*!< LCD PAL107: B04_0 Position          */
-#define LCD_PAL107_B04_0_Msk                                  (0x1fUL << LCD_PAL107_B04_0_Pos)                          /*!< LCD PAL107: B04_0 Mask              */
-#define LCD_PAL107_I0_Pos                                     15                                                        /*!< LCD PAL107: I0 Position             */
-#define LCD_PAL107_I0_Msk                                     (0x01UL << LCD_PAL107_I0_Pos)                             /*!< LCD PAL107: I0 Mask                 */
-#define LCD_PAL107_R14_0_Pos                                  16                                                        /*!< LCD PAL107: R14_0 Position          */
-#define LCD_PAL107_R14_0_Msk                                  (0x1fUL << LCD_PAL107_R14_0_Pos)                          /*!< LCD PAL107: R14_0 Mask              */
-#define LCD_PAL107_G14_0_Pos                                  21                                                        /*!< LCD PAL107: G14_0 Position          */
-#define LCD_PAL107_G14_0_Msk                                  (0x1fUL << LCD_PAL107_G14_0_Pos)                          /*!< LCD PAL107: G14_0 Mask              */
-#define LCD_PAL107_B14_0_Pos                                  26                                                        /*!< LCD PAL107: B14_0 Position          */
-#define LCD_PAL107_B14_0_Msk                                  (0x1fUL << LCD_PAL107_B14_0_Pos)                          /*!< LCD PAL107: B14_0 Mask              */
-#define LCD_PAL107_I1_Pos                                     31                                                        /*!< LCD PAL107: I1 Position             */
-#define LCD_PAL107_I1_Msk                                     (0x01UL << LCD_PAL107_I1_Pos)                             /*!< LCD PAL107: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL108  -------------------------------------------
-#define LCD_PAL108_R04_0_Pos                                  0                                                         /*!< LCD PAL108: R04_0 Position          */
-#define LCD_PAL108_R04_0_Msk                                  (0x1fUL << LCD_PAL108_R04_0_Pos)                          /*!< LCD PAL108: R04_0 Mask              */
-#define LCD_PAL108_G04_0_Pos                                  5                                                         /*!< LCD PAL108: G04_0 Position          */
-#define LCD_PAL108_G04_0_Msk                                  (0x1fUL << LCD_PAL108_G04_0_Pos)                          /*!< LCD PAL108: G04_0 Mask              */
-#define LCD_PAL108_B04_0_Pos                                  10                                                        /*!< LCD PAL108: B04_0 Position          */
-#define LCD_PAL108_B04_0_Msk                                  (0x1fUL << LCD_PAL108_B04_0_Pos)                          /*!< LCD PAL108: B04_0 Mask              */
-#define LCD_PAL108_I0_Pos                                     15                                                        /*!< LCD PAL108: I0 Position             */
-#define LCD_PAL108_I0_Msk                                     (0x01UL << LCD_PAL108_I0_Pos)                             /*!< LCD PAL108: I0 Mask                 */
-#define LCD_PAL108_R14_0_Pos                                  16                                                        /*!< LCD PAL108: R14_0 Position          */
-#define LCD_PAL108_R14_0_Msk                                  (0x1fUL << LCD_PAL108_R14_0_Pos)                          /*!< LCD PAL108: R14_0 Mask              */
-#define LCD_PAL108_G14_0_Pos                                  21                                                        /*!< LCD PAL108: G14_0 Position          */
-#define LCD_PAL108_G14_0_Msk                                  (0x1fUL << LCD_PAL108_G14_0_Pos)                          /*!< LCD PAL108: G14_0 Mask              */
-#define LCD_PAL108_B14_0_Pos                                  26                                                        /*!< LCD PAL108: B14_0 Position          */
-#define LCD_PAL108_B14_0_Msk                                  (0x1fUL << LCD_PAL108_B14_0_Pos)                          /*!< LCD PAL108: B14_0 Mask              */
-#define LCD_PAL108_I1_Pos                                     31                                                        /*!< LCD PAL108: I1 Position             */
-#define LCD_PAL108_I1_Msk                                     (0x01UL << LCD_PAL108_I1_Pos)                             /*!< LCD PAL108: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL109  -------------------------------------------
-#define LCD_PAL109_R04_0_Pos                                  0                                                         /*!< LCD PAL109: R04_0 Position          */
-#define LCD_PAL109_R04_0_Msk                                  (0x1fUL << LCD_PAL109_R04_0_Pos)                          /*!< LCD PAL109: R04_0 Mask              */
-#define LCD_PAL109_G04_0_Pos                                  5                                                         /*!< LCD PAL109: G04_0 Position          */
-#define LCD_PAL109_G04_0_Msk                                  (0x1fUL << LCD_PAL109_G04_0_Pos)                          /*!< LCD PAL109: G04_0 Mask              */
-#define LCD_PAL109_B04_0_Pos                                  10                                                        /*!< LCD PAL109: B04_0 Position          */
-#define LCD_PAL109_B04_0_Msk                                  (0x1fUL << LCD_PAL109_B04_0_Pos)                          /*!< LCD PAL109: B04_0 Mask              */
-#define LCD_PAL109_I0_Pos                                     15                                                        /*!< LCD PAL109: I0 Position             */
-#define LCD_PAL109_I0_Msk                                     (0x01UL << LCD_PAL109_I0_Pos)                             /*!< LCD PAL109: I0 Mask                 */
-#define LCD_PAL109_R14_0_Pos                                  16                                                        /*!< LCD PAL109: R14_0 Position          */
-#define LCD_PAL109_R14_0_Msk                                  (0x1fUL << LCD_PAL109_R14_0_Pos)                          /*!< LCD PAL109: R14_0 Mask              */
-#define LCD_PAL109_G14_0_Pos                                  21                                                        /*!< LCD PAL109: G14_0 Position          */
-#define LCD_PAL109_G14_0_Msk                                  (0x1fUL << LCD_PAL109_G14_0_Pos)                          /*!< LCD PAL109: G14_0 Mask              */
-#define LCD_PAL109_B14_0_Pos                                  26                                                        /*!< LCD PAL109: B14_0 Position          */
-#define LCD_PAL109_B14_0_Msk                                  (0x1fUL << LCD_PAL109_B14_0_Pos)                          /*!< LCD PAL109: B14_0 Mask              */
-#define LCD_PAL109_I1_Pos                                     31                                                        /*!< LCD PAL109: I1 Position             */
-#define LCD_PAL109_I1_Msk                                     (0x01UL << LCD_PAL109_I1_Pos)                             /*!< LCD PAL109: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL110  -------------------------------------------
-#define LCD_PAL110_R04_0_Pos                                  0                                                         /*!< LCD PAL110: R04_0 Position          */
-#define LCD_PAL110_R04_0_Msk                                  (0x1fUL << LCD_PAL110_R04_0_Pos)                          /*!< LCD PAL110: R04_0 Mask              */
-#define LCD_PAL110_G04_0_Pos                                  5                                                         /*!< LCD PAL110: G04_0 Position          */
-#define LCD_PAL110_G04_0_Msk                                  (0x1fUL << LCD_PAL110_G04_0_Pos)                          /*!< LCD PAL110: G04_0 Mask              */
-#define LCD_PAL110_B04_0_Pos                                  10                                                        /*!< LCD PAL110: B04_0 Position          */
-#define LCD_PAL110_B04_0_Msk                                  (0x1fUL << LCD_PAL110_B04_0_Pos)                          /*!< LCD PAL110: B04_0 Mask              */
-#define LCD_PAL110_I0_Pos                                     15                                                        /*!< LCD PAL110: I0 Position             */
-#define LCD_PAL110_I0_Msk                                     (0x01UL << LCD_PAL110_I0_Pos)                             /*!< LCD PAL110: I0 Mask                 */
-#define LCD_PAL110_R14_0_Pos                                  16                                                        /*!< LCD PAL110: R14_0 Position          */
-#define LCD_PAL110_R14_0_Msk                                  (0x1fUL << LCD_PAL110_R14_0_Pos)                          /*!< LCD PAL110: R14_0 Mask              */
-#define LCD_PAL110_G14_0_Pos                                  21                                                        /*!< LCD PAL110: G14_0 Position          */
-#define LCD_PAL110_G14_0_Msk                                  (0x1fUL << LCD_PAL110_G14_0_Pos)                          /*!< LCD PAL110: G14_0 Mask              */
-#define LCD_PAL110_B14_0_Pos                                  26                                                        /*!< LCD PAL110: B14_0 Position          */
-#define LCD_PAL110_B14_0_Msk                                  (0x1fUL << LCD_PAL110_B14_0_Pos)                          /*!< LCD PAL110: B14_0 Mask              */
-#define LCD_PAL110_I1_Pos                                     31                                                        /*!< LCD PAL110: I1 Position             */
-#define LCD_PAL110_I1_Msk                                     (0x01UL << LCD_PAL110_I1_Pos)                             /*!< LCD PAL110: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL111  -------------------------------------------
-#define LCD_PAL111_R04_0_Pos                                  0                                                         /*!< LCD PAL111: R04_0 Position          */
-#define LCD_PAL111_R04_0_Msk                                  (0x1fUL << LCD_PAL111_R04_0_Pos)                          /*!< LCD PAL111: R04_0 Mask              */
-#define LCD_PAL111_G04_0_Pos                                  5                                                         /*!< LCD PAL111: G04_0 Position          */
-#define LCD_PAL111_G04_0_Msk                                  (0x1fUL << LCD_PAL111_G04_0_Pos)                          /*!< LCD PAL111: G04_0 Mask              */
-#define LCD_PAL111_B04_0_Pos                                  10                                                        /*!< LCD PAL111: B04_0 Position          */
-#define LCD_PAL111_B04_0_Msk                                  (0x1fUL << LCD_PAL111_B04_0_Pos)                          /*!< LCD PAL111: B04_0 Mask              */
-#define LCD_PAL111_I0_Pos                                     15                                                        /*!< LCD PAL111: I0 Position             */
-#define LCD_PAL111_I0_Msk                                     (0x01UL << LCD_PAL111_I0_Pos)                             /*!< LCD PAL111: I0 Mask                 */
-#define LCD_PAL111_R14_0_Pos                                  16                                                        /*!< LCD PAL111: R14_0 Position          */
-#define LCD_PAL111_R14_0_Msk                                  (0x1fUL << LCD_PAL111_R14_0_Pos)                          /*!< LCD PAL111: R14_0 Mask              */
-#define LCD_PAL111_G14_0_Pos                                  21                                                        /*!< LCD PAL111: G14_0 Position          */
-#define LCD_PAL111_G14_0_Msk                                  (0x1fUL << LCD_PAL111_G14_0_Pos)                          /*!< LCD PAL111: G14_0 Mask              */
-#define LCD_PAL111_B14_0_Pos                                  26                                                        /*!< LCD PAL111: B14_0 Position          */
-#define LCD_PAL111_B14_0_Msk                                  (0x1fUL << LCD_PAL111_B14_0_Pos)                          /*!< LCD PAL111: B14_0 Mask              */
-#define LCD_PAL111_I1_Pos                                     31                                                        /*!< LCD PAL111: I1 Position             */
-#define LCD_PAL111_I1_Msk                                     (0x01UL << LCD_PAL111_I1_Pos)                             /*!< LCD PAL111: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL112  -------------------------------------------
-#define LCD_PAL112_R04_0_Pos                                  0                                                         /*!< LCD PAL112: R04_0 Position          */
-#define LCD_PAL112_R04_0_Msk                                  (0x1fUL << LCD_PAL112_R04_0_Pos)                          /*!< LCD PAL112: R04_0 Mask              */
-#define LCD_PAL112_G04_0_Pos                                  5                                                         /*!< LCD PAL112: G04_0 Position          */
-#define LCD_PAL112_G04_0_Msk                                  (0x1fUL << LCD_PAL112_G04_0_Pos)                          /*!< LCD PAL112: G04_0 Mask              */
-#define LCD_PAL112_B04_0_Pos                                  10                                                        /*!< LCD PAL112: B04_0 Position          */
-#define LCD_PAL112_B04_0_Msk                                  (0x1fUL << LCD_PAL112_B04_0_Pos)                          /*!< LCD PAL112: B04_0 Mask              */
-#define LCD_PAL112_I0_Pos                                     15                                                        /*!< LCD PAL112: I0 Position             */
-#define LCD_PAL112_I0_Msk                                     (0x01UL << LCD_PAL112_I0_Pos)                             /*!< LCD PAL112: I0 Mask                 */
-#define LCD_PAL112_R14_0_Pos                                  16                                                        /*!< LCD PAL112: R14_0 Position          */
-#define LCD_PAL112_R14_0_Msk                                  (0x1fUL << LCD_PAL112_R14_0_Pos)                          /*!< LCD PAL112: R14_0 Mask              */
-#define LCD_PAL112_G14_0_Pos                                  21                                                        /*!< LCD PAL112: G14_0 Position          */
-#define LCD_PAL112_G14_0_Msk                                  (0x1fUL << LCD_PAL112_G14_0_Pos)                          /*!< LCD PAL112: G14_0 Mask              */
-#define LCD_PAL112_B14_0_Pos                                  26                                                        /*!< LCD PAL112: B14_0 Position          */
-#define LCD_PAL112_B14_0_Msk                                  (0x1fUL << LCD_PAL112_B14_0_Pos)                          /*!< LCD PAL112: B14_0 Mask              */
-#define LCD_PAL112_I1_Pos                                     31                                                        /*!< LCD PAL112: I1 Position             */
-#define LCD_PAL112_I1_Msk                                     (0x01UL << LCD_PAL112_I1_Pos)                             /*!< LCD PAL112: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL113  -------------------------------------------
-#define LCD_PAL113_R04_0_Pos                                  0                                                         /*!< LCD PAL113: R04_0 Position          */
-#define LCD_PAL113_R04_0_Msk                                  (0x1fUL << LCD_PAL113_R04_0_Pos)                          /*!< LCD PAL113: R04_0 Mask              */
-#define LCD_PAL113_G04_0_Pos                                  5                                                         /*!< LCD PAL113: G04_0 Position          */
-#define LCD_PAL113_G04_0_Msk                                  (0x1fUL << LCD_PAL113_G04_0_Pos)                          /*!< LCD PAL113: G04_0 Mask              */
-#define LCD_PAL113_B04_0_Pos                                  10                                                        /*!< LCD PAL113: B04_0 Position          */
-#define LCD_PAL113_B04_0_Msk                                  (0x1fUL << LCD_PAL113_B04_0_Pos)                          /*!< LCD PAL113: B04_0 Mask              */
-#define LCD_PAL113_I0_Pos                                     15                                                        /*!< LCD PAL113: I0 Position             */
-#define LCD_PAL113_I0_Msk                                     (0x01UL << LCD_PAL113_I0_Pos)                             /*!< LCD PAL113: I0 Mask                 */
-#define LCD_PAL113_R14_0_Pos                                  16                                                        /*!< LCD PAL113: R14_0 Position          */
-#define LCD_PAL113_R14_0_Msk                                  (0x1fUL << LCD_PAL113_R14_0_Pos)                          /*!< LCD PAL113: R14_0 Mask              */
-#define LCD_PAL113_G14_0_Pos                                  21                                                        /*!< LCD PAL113: G14_0 Position          */
-#define LCD_PAL113_G14_0_Msk                                  (0x1fUL << LCD_PAL113_G14_0_Pos)                          /*!< LCD PAL113: G14_0 Mask              */
-#define LCD_PAL113_B14_0_Pos                                  26                                                        /*!< LCD PAL113: B14_0 Position          */
-#define LCD_PAL113_B14_0_Msk                                  (0x1fUL << LCD_PAL113_B14_0_Pos)                          /*!< LCD PAL113: B14_0 Mask              */
-#define LCD_PAL113_I1_Pos                                     31                                                        /*!< LCD PAL113: I1 Position             */
-#define LCD_PAL113_I1_Msk                                     (0x01UL << LCD_PAL113_I1_Pos)                             /*!< LCD PAL113: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL114  -------------------------------------------
-#define LCD_PAL114_R04_0_Pos                                  0                                                         /*!< LCD PAL114: R04_0 Position          */
-#define LCD_PAL114_R04_0_Msk                                  (0x1fUL << LCD_PAL114_R04_0_Pos)                          /*!< LCD PAL114: R04_0 Mask              */
-#define LCD_PAL114_G04_0_Pos                                  5                                                         /*!< LCD PAL114: G04_0 Position          */
-#define LCD_PAL114_G04_0_Msk                                  (0x1fUL << LCD_PAL114_G04_0_Pos)                          /*!< LCD PAL114: G04_0 Mask              */
-#define LCD_PAL114_B04_0_Pos                                  10                                                        /*!< LCD PAL114: B04_0 Position          */
-#define LCD_PAL114_B04_0_Msk                                  (0x1fUL << LCD_PAL114_B04_0_Pos)                          /*!< LCD PAL114: B04_0 Mask              */
-#define LCD_PAL114_I0_Pos                                     15                                                        /*!< LCD PAL114: I0 Position             */
-#define LCD_PAL114_I0_Msk                                     (0x01UL << LCD_PAL114_I0_Pos)                             /*!< LCD PAL114: I0 Mask                 */
-#define LCD_PAL114_R14_0_Pos                                  16                                                        /*!< LCD PAL114: R14_0 Position          */
-#define LCD_PAL114_R14_0_Msk                                  (0x1fUL << LCD_PAL114_R14_0_Pos)                          /*!< LCD PAL114: R14_0 Mask              */
-#define LCD_PAL114_G14_0_Pos                                  21                                                        /*!< LCD PAL114: G14_0 Position          */
-#define LCD_PAL114_G14_0_Msk                                  (0x1fUL << LCD_PAL114_G14_0_Pos)                          /*!< LCD PAL114: G14_0 Mask              */
-#define LCD_PAL114_B14_0_Pos                                  26                                                        /*!< LCD PAL114: B14_0 Position          */
-#define LCD_PAL114_B14_0_Msk                                  (0x1fUL << LCD_PAL114_B14_0_Pos)                          /*!< LCD PAL114: B14_0 Mask              */
-#define LCD_PAL114_I1_Pos                                     31                                                        /*!< LCD PAL114: I1 Position             */
-#define LCD_PAL114_I1_Msk                                     (0x01UL << LCD_PAL114_I1_Pos)                             /*!< LCD PAL114: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL115  -------------------------------------------
-#define LCD_PAL115_R04_0_Pos                                  0                                                         /*!< LCD PAL115: R04_0 Position          */
-#define LCD_PAL115_R04_0_Msk                                  (0x1fUL << LCD_PAL115_R04_0_Pos)                          /*!< LCD PAL115: R04_0 Mask              */
-#define LCD_PAL115_G04_0_Pos                                  5                                                         /*!< LCD PAL115: G04_0 Position          */
-#define LCD_PAL115_G04_0_Msk                                  (0x1fUL << LCD_PAL115_G04_0_Pos)                          /*!< LCD PAL115: G04_0 Mask              */
-#define LCD_PAL115_B04_0_Pos                                  10                                                        /*!< LCD PAL115: B04_0 Position          */
-#define LCD_PAL115_B04_0_Msk                                  (0x1fUL << LCD_PAL115_B04_0_Pos)                          /*!< LCD PAL115: B04_0 Mask              */
-#define LCD_PAL115_I0_Pos                                     15                                                        /*!< LCD PAL115: I0 Position             */
-#define LCD_PAL115_I0_Msk                                     (0x01UL << LCD_PAL115_I0_Pos)                             /*!< LCD PAL115: I0 Mask                 */
-#define LCD_PAL115_R14_0_Pos                                  16                                                        /*!< LCD PAL115: R14_0 Position          */
-#define LCD_PAL115_R14_0_Msk                                  (0x1fUL << LCD_PAL115_R14_0_Pos)                          /*!< LCD PAL115: R14_0 Mask              */
-#define LCD_PAL115_G14_0_Pos                                  21                                                        /*!< LCD PAL115: G14_0 Position          */
-#define LCD_PAL115_G14_0_Msk                                  (0x1fUL << LCD_PAL115_G14_0_Pos)                          /*!< LCD PAL115: G14_0 Mask              */
-#define LCD_PAL115_B14_0_Pos                                  26                                                        /*!< LCD PAL115: B14_0 Position          */
-#define LCD_PAL115_B14_0_Msk                                  (0x1fUL << LCD_PAL115_B14_0_Pos)                          /*!< LCD PAL115: B14_0 Mask              */
-#define LCD_PAL115_I1_Pos                                     31                                                        /*!< LCD PAL115: I1 Position             */
-#define LCD_PAL115_I1_Msk                                     (0x01UL << LCD_PAL115_I1_Pos)                             /*!< LCD PAL115: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL116  -------------------------------------------
-#define LCD_PAL116_R04_0_Pos                                  0                                                         /*!< LCD PAL116: R04_0 Position          */
-#define LCD_PAL116_R04_0_Msk                                  (0x1fUL << LCD_PAL116_R04_0_Pos)                          /*!< LCD PAL116: R04_0 Mask              */
-#define LCD_PAL116_G04_0_Pos                                  5                                                         /*!< LCD PAL116: G04_0 Position          */
-#define LCD_PAL116_G04_0_Msk                                  (0x1fUL << LCD_PAL116_G04_0_Pos)                          /*!< LCD PAL116: G04_0 Mask              */
-#define LCD_PAL116_B04_0_Pos                                  10                                                        /*!< LCD PAL116: B04_0 Position          */
-#define LCD_PAL116_B04_0_Msk                                  (0x1fUL << LCD_PAL116_B04_0_Pos)                          /*!< LCD PAL116: B04_0 Mask              */
-#define LCD_PAL116_I0_Pos                                     15                                                        /*!< LCD PAL116: I0 Position             */
-#define LCD_PAL116_I0_Msk                                     (0x01UL << LCD_PAL116_I0_Pos)                             /*!< LCD PAL116: I0 Mask                 */
-#define LCD_PAL116_R14_0_Pos                                  16                                                        /*!< LCD PAL116: R14_0 Position          */
-#define LCD_PAL116_R14_0_Msk                                  (0x1fUL << LCD_PAL116_R14_0_Pos)                          /*!< LCD PAL116: R14_0 Mask              */
-#define LCD_PAL116_G14_0_Pos                                  21                                                        /*!< LCD PAL116: G14_0 Position          */
-#define LCD_PAL116_G14_0_Msk                                  (0x1fUL << LCD_PAL116_G14_0_Pos)                          /*!< LCD PAL116: G14_0 Mask              */
-#define LCD_PAL116_B14_0_Pos                                  26                                                        /*!< LCD PAL116: B14_0 Position          */
-#define LCD_PAL116_B14_0_Msk                                  (0x1fUL << LCD_PAL116_B14_0_Pos)                          /*!< LCD PAL116: B14_0 Mask              */
-#define LCD_PAL116_I1_Pos                                     31                                                        /*!< LCD PAL116: I1 Position             */
-#define LCD_PAL116_I1_Msk                                     (0x01UL << LCD_PAL116_I1_Pos)                             /*!< LCD PAL116: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL117  -------------------------------------------
-#define LCD_PAL117_R04_0_Pos                                  0                                                         /*!< LCD PAL117: R04_0 Position          */
-#define LCD_PAL117_R04_0_Msk                                  (0x1fUL << LCD_PAL117_R04_0_Pos)                          /*!< LCD PAL117: R04_0 Mask              */
-#define LCD_PAL117_G04_0_Pos                                  5                                                         /*!< LCD PAL117: G04_0 Position          */
-#define LCD_PAL117_G04_0_Msk                                  (0x1fUL << LCD_PAL117_G04_0_Pos)                          /*!< LCD PAL117: G04_0 Mask              */
-#define LCD_PAL117_B04_0_Pos                                  10                                                        /*!< LCD PAL117: B04_0 Position          */
-#define LCD_PAL117_B04_0_Msk                                  (0x1fUL << LCD_PAL117_B04_0_Pos)                          /*!< LCD PAL117: B04_0 Mask              */
-#define LCD_PAL117_I0_Pos                                     15                                                        /*!< LCD PAL117: I0 Position             */
-#define LCD_PAL117_I0_Msk                                     (0x01UL << LCD_PAL117_I0_Pos)                             /*!< LCD PAL117: I0 Mask                 */
-#define LCD_PAL117_R14_0_Pos                                  16                                                        /*!< LCD PAL117: R14_0 Position          */
-#define LCD_PAL117_R14_0_Msk                                  (0x1fUL << LCD_PAL117_R14_0_Pos)                          /*!< LCD PAL117: R14_0 Mask              */
-#define LCD_PAL117_G14_0_Pos                                  21                                                        /*!< LCD PAL117: G14_0 Position          */
-#define LCD_PAL117_G14_0_Msk                                  (0x1fUL << LCD_PAL117_G14_0_Pos)                          /*!< LCD PAL117: G14_0 Mask              */
-#define LCD_PAL117_B14_0_Pos                                  26                                                        /*!< LCD PAL117: B14_0 Position          */
-#define LCD_PAL117_B14_0_Msk                                  (0x1fUL << LCD_PAL117_B14_0_Pos)                          /*!< LCD PAL117: B14_0 Mask              */
-#define LCD_PAL117_I1_Pos                                     31                                                        /*!< LCD PAL117: I1 Position             */
-#define LCD_PAL117_I1_Msk                                     (0x01UL << LCD_PAL117_I1_Pos)                             /*!< LCD PAL117: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL118  -------------------------------------------
-#define LCD_PAL118_R04_0_Pos                                  0                                                         /*!< LCD PAL118: R04_0 Position          */
-#define LCD_PAL118_R04_0_Msk                                  (0x1fUL << LCD_PAL118_R04_0_Pos)                          /*!< LCD PAL118: R04_0 Mask              */
-#define LCD_PAL118_G04_0_Pos                                  5                                                         /*!< LCD PAL118: G04_0 Position          */
-#define LCD_PAL118_G04_0_Msk                                  (0x1fUL << LCD_PAL118_G04_0_Pos)                          /*!< LCD PAL118: G04_0 Mask              */
-#define LCD_PAL118_B04_0_Pos                                  10                                                        /*!< LCD PAL118: B04_0 Position          */
-#define LCD_PAL118_B04_0_Msk                                  (0x1fUL << LCD_PAL118_B04_0_Pos)                          /*!< LCD PAL118: B04_0 Mask              */
-#define LCD_PAL118_I0_Pos                                     15                                                        /*!< LCD PAL118: I0 Position             */
-#define LCD_PAL118_I0_Msk                                     (0x01UL << LCD_PAL118_I0_Pos)                             /*!< LCD PAL118: I0 Mask                 */
-#define LCD_PAL118_R14_0_Pos                                  16                                                        /*!< LCD PAL118: R14_0 Position          */
-#define LCD_PAL118_R14_0_Msk                                  (0x1fUL << LCD_PAL118_R14_0_Pos)                          /*!< LCD PAL118: R14_0 Mask              */
-#define LCD_PAL118_G14_0_Pos                                  21                                                        /*!< LCD PAL118: G14_0 Position          */
-#define LCD_PAL118_G14_0_Msk                                  (0x1fUL << LCD_PAL118_G14_0_Pos)                          /*!< LCD PAL118: G14_0 Mask              */
-#define LCD_PAL118_B14_0_Pos                                  26                                                        /*!< LCD PAL118: B14_0 Position          */
-#define LCD_PAL118_B14_0_Msk                                  (0x1fUL << LCD_PAL118_B14_0_Pos)                          /*!< LCD PAL118: B14_0 Mask              */
-#define LCD_PAL118_I1_Pos                                     31                                                        /*!< LCD PAL118: I1 Position             */
-#define LCD_PAL118_I1_Msk                                     (0x01UL << LCD_PAL118_I1_Pos)                             /*!< LCD PAL118: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL119  -------------------------------------------
-#define LCD_PAL119_R04_0_Pos                                  0                                                         /*!< LCD PAL119: R04_0 Position          */
-#define LCD_PAL119_R04_0_Msk                                  (0x1fUL << LCD_PAL119_R04_0_Pos)                          /*!< LCD PAL119: R04_0 Mask              */
-#define LCD_PAL119_G04_0_Pos                                  5                                                         /*!< LCD PAL119: G04_0 Position          */
-#define LCD_PAL119_G04_0_Msk                                  (0x1fUL << LCD_PAL119_G04_0_Pos)                          /*!< LCD PAL119: G04_0 Mask              */
-#define LCD_PAL119_B04_0_Pos                                  10                                                        /*!< LCD PAL119: B04_0 Position          */
-#define LCD_PAL119_B04_0_Msk                                  (0x1fUL << LCD_PAL119_B04_0_Pos)                          /*!< LCD PAL119: B04_0 Mask              */
-#define LCD_PAL119_I0_Pos                                     15                                                        /*!< LCD PAL119: I0 Position             */
-#define LCD_PAL119_I0_Msk                                     (0x01UL << LCD_PAL119_I0_Pos)                             /*!< LCD PAL119: I0 Mask                 */
-#define LCD_PAL119_R14_0_Pos                                  16                                                        /*!< LCD PAL119: R14_0 Position          */
-#define LCD_PAL119_R14_0_Msk                                  (0x1fUL << LCD_PAL119_R14_0_Pos)                          /*!< LCD PAL119: R14_0 Mask              */
-#define LCD_PAL119_G14_0_Pos                                  21                                                        /*!< LCD PAL119: G14_0 Position          */
-#define LCD_PAL119_G14_0_Msk                                  (0x1fUL << LCD_PAL119_G14_0_Pos)                          /*!< LCD PAL119: G14_0 Mask              */
-#define LCD_PAL119_B14_0_Pos                                  26                                                        /*!< LCD PAL119: B14_0 Position          */
-#define LCD_PAL119_B14_0_Msk                                  (0x1fUL << LCD_PAL119_B14_0_Pos)                          /*!< LCD PAL119: B14_0 Mask              */
-#define LCD_PAL119_I1_Pos                                     31                                                        /*!< LCD PAL119: I1 Position             */
-#define LCD_PAL119_I1_Msk                                     (0x01UL << LCD_PAL119_I1_Pos)                             /*!< LCD PAL119: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL120  -------------------------------------------
-#define LCD_PAL120_R04_0_Pos                                  0                                                         /*!< LCD PAL120: R04_0 Position          */
-#define LCD_PAL120_R04_0_Msk                                  (0x1fUL << LCD_PAL120_R04_0_Pos)                          /*!< LCD PAL120: R04_0 Mask              */
-#define LCD_PAL120_G04_0_Pos                                  5                                                         /*!< LCD PAL120: G04_0 Position          */
-#define LCD_PAL120_G04_0_Msk                                  (0x1fUL << LCD_PAL120_G04_0_Pos)                          /*!< LCD PAL120: G04_0 Mask              */
-#define LCD_PAL120_B04_0_Pos                                  10                                                        /*!< LCD PAL120: B04_0 Position          */
-#define LCD_PAL120_B04_0_Msk                                  (0x1fUL << LCD_PAL120_B04_0_Pos)                          /*!< LCD PAL120: B04_0 Mask              */
-#define LCD_PAL120_I0_Pos                                     15                                                        /*!< LCD PAL120: I0 Position             */
-#define LCD_PAL120_I0_Msk                                     (0x01UL << LCD_PAL120_I0_Pos)                             /*!< LCD PAL120: I0 Mask                 */
-#define LCD_PAL120_R14_0_Pos                                  16                                                        /*!< LCD PAL120: R14_0 Position          */
-#define LCD_PAL120_R14_0_Msk                                  (0x1fUL << LCD_PAL120_R14_0_Pos)                          /*!< LCD PAL120: R14_0 Mask              */
-#define LCD_PAL120_G14_0_Pos                                  21                                                        /*!< LCD PAL120: G14_0 Position          */
-#define LCD_PAL120_G14_0_Msk                                  (0x1fUL << LCD_PAL120_G14_0_Pos)                          /*!< LCD PAL120: G14_0 Mask              */
-#define LCD_PAL120_B14_0_Pos                                  26                                                        /*!< LCD PAL120: B14_0 Position          */
-#define LCD_PAL120_B14_0_Msk                                  (0x1fUL << LCD_PAL120_B14_0_Pos)                          /*!< LCD PAL120: B14_0 Mask              */
-#define LCD_PAL120_I1_Pos                                     31                                                        /*!< LCD PAL120: I1 Position             */
-#define LCD_PAL120_I1_Msk                                     (0x01UL << LCD_PAL120_I1_Pos)                             /*!< LCD PAL120: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL121  -------------------------------------------
-#define LCD_PAL121_R04_0_Pos                                  0                                                         /*!< LCD PAL121: R04_0 Position          */
-#define LCD_PAL121_R04_0_Msk                                  (0x1fUL << LCD_PAL121_R04_0_Pos)                          /*!< LCD PAL121: R04_0 Mask              */
-#define LCD_PAL121_G04_0_Pos                                  5                                                         /*!< LCD PAL121: G04_0 Position          */
-#define LCD_PAL121_G04_0_Msk                                  (0x1fUL << LCD_PAL121_G04_0_Pos)                          /*!< LCD PAL121: G04_0 Mask              */
-#define LCD_PAL121_B04_0_Pos                                  10                                                        /*!< LCD PAL121: B04_0 Position          */
-#define LCD_PAL121_B04_0_Msk                                  (0x1fUL << LCD_PAL121_B04_0_Pos)                          /*!< LCD PAL121: B04_0 Mask              */
-#define LCD_PAL121_I0_Pos                                     15                                                        /*!< LCD PAL121: I0 Position             */
-#define LCD_PAL121_I0_Msk                                     (0x01UL << LCD_PAL121_I0_Pos)                             /*!< LCD PAL121: I0 Mask                 */
-#define LCD_PAL121_R14_0_Pos                                  16                                                        /*!< LCD PAL121: R14_0 Position          */
-#define LCD_PAL121_R14_0_Msk                                  (0x1fUL << LCD_PAL121_R14_0_Pos)                          /*!< LCD PAL121: R14_0 Mask              */
-#define LCD_PAL121_G14_0_Pos                                  21                                                        /*!< LCD PAL121: G14_0 Position          */
-#define LCD_PAL121_G14_0_Msk                                  (0x1fUL << LCD_PAL121_G14_0_Pos)                          /*!< LCD PAL121: G14_0 Mask              */
-#define LCD_PAL121_B14_0_Pos                                  26                                                        /*!< LCD PAL121: B14_0 Position          */
-#define LCD_PAL121_B14_0_Msk                                  (0x1fUL << LCD_PAL121_B14_0_Pos)                          /*!< LCD PAL121: B14_0 Mask              */
-#define LCD_PAL121_I1_Pos                                     31                                                        /*!< LCD PAL121: I1 Position             */
-#define LCD_PAL121_I1_Msk                                     (0x01UL << LCD_PAL121_I1_Pos)                             /*!< LCD PAL121: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL122  -------------------------------------------
-#define LCD_PAL122_R04_0_Pos                                  0                                                         /*!< LCD PAL122: R04_0 Position          */
-#define LCD_PAL122_R04_0_Msk                                  (0x1fUL << LCD_PAL122_R04_0_Pos)                          /*!< LCD PAL122: R04_0 Mask              */
-#define LCD_PAL122_G04_0_Pos                                  5                                                         /*!< LCD PAL122: G04_0 Position          */
-#define LCD_PAL122_G04_0_Msk                                  (0x1fUL << LCD_PAL122_G04_0_Pos)                          /*!< LCD PAL122: G04_0 Mask              */
-#define LCD_PAL122_B04_0_Pos                                  10                                                        /*!< LCD PAL122: B04_0 Position          */
-#define LCD_PAL122_B04_0_Msk                                  (0x1fUL << LCD_PAL122_B04_0_Pos)                          /*!< LCD PAL122: B04_0 Mask              */
-#define LCD_PAL122_I0_Pos                                     15                                                        /*!< LCD PAL122: I0 Position             */
-#define LCD_PAL122_I0_Msk                                     (0x01UL << LCD_PAL122_I0_Pos)                             /*!< LCD PAL122: I0 Mask                 */
-#define LCD_PAL122_R14_0_Pos                                  16                                                        /*!< LCD PAL122: R14_0 Position          */
-#define LCD_PAL122_R14_0_Msk                                  (0x1fUL << LCD_PAL122_R14_0_Pos)                          /*!< LCD PAL122: R14_0 Mask              */
-#define LCD_PAL122_G14_0_Pos                                  21                                                        /*!< LCD PAL122: G14_0 Position          */
-#define LCD_PAL122_G14_0_Msk                                  (0x1fUL << LCD_PAL122_G14_0_Pos)                          /*!< LCD PAL122: G14_0 Mask              */
-#define LCD_PAL122_B14_0_Pos                                  26                                                        /*!< LCD PAL122: B14_0 Position          */
-#define LCD_PAL122_B14_0_Msk                                  (0x1fUL << LCD_PAL122_B14_0_Pos)                          /*!< LCD PAL122: B14_0 Mask              */
-#define LCD_PAL122_I1_Pos                                     31                                                        /*!< LCD PAL122: I1 Position             */
-#define LCD_PAL122_I1_Msk                                     (0x01UL << LCD_PAL122_I1_Pos)                             /*!< LCD PAL122: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL123  -------------------------------------------
-#define LCD_PAL123_R04_0_Pos                                  0                                                         /*!< LCD PAL123: R04_0 Position          */
-#define LCD_PAL123_R04_0_Msk                                  (0x1fUL << LCD_PAL123_R04_0_Pos)                          /*!< LCD PAL123: R04_0 Mask              */
-#define LCD_PAL123_G04_0_Pos                                  5                                                         /*!< LCD PAL123: G04_0 Position          */
-#define LCD_PAL123_G04_0_Msk                                  (0x1fUL << LCD_PAL123_G04_0_Pos)                          /*!< LCD PAL123: G04_0 Mask              */
-#define LCD_PAL123_B04_0_Pos                                  10                                                        /*!< LCD PAL123: B04_0 Position          */
-#define LCD_PAL123_B04_0_Msk                                  (0x1fUL << LCD_PAL123_B04_0_Pos)                          /*!< LCD PAL123: B04_0 Mask              */
-#define LCD_PAL123_I0_Pos                                     15                                                        /*!< LCD PAL123: I0 Position             */
-#define LCD_PAL123_I0_Msk                                     (0x01UL << LCD_PAL123_I0_Pos)                             /*!< LCD PAL123: I0 Mask                 */
-#define LCD_PAL123_R14_0_Pos                                  16                                                        /*!< LCD PAL123: R14_0 Position          */
-#define LCD_PAL123_R14_0_Msk                                  (0x1fUL << LCD_PAL123_R14_0_Pos)                          /*!< LCD PAL123: R14_0 Mask              */
-#define LCD_PAL123_G14_0_Pos                                  21                                                        /*!< LCD PAL123: G14_0 Position          */
-#define LCD_PAL123_G14_0_Msk                                  (0x1fUL << LCD_PAL123_G14_0_Pos)                          /*!< LCD PAL123: G14_0 Mask              */
-#define LCD_PAL123_B14_0_Pos                                  26                                                        /*!< LCD PAL123: B14_0 Position          */
-#define LCD_PAL123_B14_0_Msk                                  (0x1fUL << LCD_PAL123_B14_0_Pos)                          /*!< LCD PAL123: B14_0 Mask              */
-#define LCD_PAL123_I1_Pos                                     31                                                        /*!< LCD PAL123: I1 Position             */
-#define LCD_PAL123_I1_Msk                                     (0x01UL << LCD_PAL123_I1_Pos)                             /*!< LCD PAL123: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL124  -------------------------------------------
-#define LCD_PAL124_R04_0_Pos                                  0                                                         /*!< LCD PAL124: R04_0 Position          */
-#define LCD_PAL124_R04_0_Msk                                  (0x1fUL << LCD_PAL124_R04_0_Pos)                          /*!< LCD PAL124: R04_0 Mask              */
-#define LCD_PAL124_G04_0_Pos                                  5                                                         /*!< LCD PAL124: G04_0 Position          */
-#define LCD_PAL124_G04_0_Msk                                  (0x1fUL << LCD_PAL124_G04_0_Pos)                          /*!< LCD PAL124: G04_0 Mask              */
-#define LCD_PAL124_B04_0_Pos                                  10                                                        /*!< LCD PAL124: B04_0 Position          */
-#define LCD_PAL124_B04_0_Msk                                  (0x1fUL << LCD_PAL124_B04_0_Pos)                          /*!< LCD PAL124: B04_0 Mask              */
-#define LCD_PAL124_I0_Pos                                     15                                                        /*!< LCD PAL124: I0 Position             */
-#define LCD_PAL124_I0_Msk                                     (0x01UL << LCD_PAL124_I0_Pos)                             /*!< LCD PAL124: I0 Mask                 */
-#define LCD_PAL124_R14_0_Pos                                  16                                                        /*!< LCD PAL124: R14_0 Position          */
-#define LCD_PAL124_R14_0_Msk                                  (0x1fUL << LCD_PAL124_R14_0_Pos)                          /*!< LCD PAL124: R14_0 Mask              */
-#define LCD_PAL124_G14_0_Pos                                  21                                                        /*!< LCD PAL124: G14_0 Position          */
-#define LCD_PAL124_G14_0_Msk                                  (0x1fUL << LCD_PAL124_G14_0_Pos)                          /*!< LCD PAL124: G14_0 Mask              */
-#define LCD_PAL124_B14_0_Pos                                  26                                                        /*!< LCD PAL124: B14_0 Position          */
-#define LCD_PAL124_B14_0_Msk                                  (0x1fUL << LCD_PAL124_B14_0_Pos)                          /*!< LCD PAL124: B14_0 Mask              */
-#define LCD_PAL124_I1_Pos                                     31                                                        /*!< LCD PAL124: I1 Position             */
-#define LCD_PAL124_I1_Msk                                     (0x01UL << LCD_PAL124_I1_Pos)                             /*!< LCD PAL124: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL125  -------------------------------------------
-#define LCD_PAL125_R04_0_Pos                                  0                                                         /*!< LCD PAL125: R04_0 Position          */
-#define LCD_PAL125_R04_0_Msk                                  (0x1fUL << LCD_PAL125_R04_0_Pos)                          /*!< LCD PAL125: R04_0 Mask              */
-#define LCD_PAL125_G04_0_Pos                                  5                                                         /*!< LCD PAL125: G04_0 Position          */
-#define LCD_PAL125_G04_0_Msk                                  (0x1fUL << LCD_PAL125_G04_0_Pos)                          /*!< LCD PAL125: G04_0 Mask              */
-#define LCD_PAL125_B04_0_Pos                                  10                                                        /*!< LCD PAL125: B04_0 Position          */
-#define LCD_PAL125_B04_0_Msk                                  (0x1fUL << LCD_PAL125_B04_0_Pos)                          /*!< LCD PAL125: B04_0 Mask              */
-#define LCD_PAL125_I0_Pos                                     15                                                        /*!< LCD PAL125: I0 Position             */
-#define LCD_PAL125_I0_Msk                                     (0x01UL << LCD_PAL125_I0_Pos)                             /*!< LCD PAL125: I0 Mask                 */
-#define LCD_PAL125_R14_0_Pos                                  16                                                        /*!< LCD PAL125: R14_0 Position          */
-#define LCD_PAL125_R14_0_Msk                                  (0x1fUL << LCD_PAL125_R14_0_Pos)                          /*!< LCD PAL125: R14_0 Mask              */
-#define LCD_PAL125_G14_0_Pos                                  21                                                        /*!< LCD PAL125: G14_0 Position          */
-#define LCD_PAL125_G14_0_Msk                                  (0x1fUL << LCD_PAL125_G14_0_Pos)                          /*!< LCD PAL125: G14_0 Mask              */
-#define LCD_PAL125_B14_0_Pos                                  26                                                        /*!< LCD PAL125: B14_0 Position          */
-#define LCD_PAL125_B14_0_Msk                                  (0x1fUL << LCD_PAL125_B14_0_Pos)                          /*!< LCD PAL125: B14_0 Mask              */
-#define LCD_PAL125_I1_Pos                                     31                                                        /*!< LCD PAL125: I1 Position             */
-#define LCD_PAL125_I1_Msk                                     (0x01UL << LCD_PAL125_I1_Pos)                             /*!< LCD PAL125: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL126  -------------------------------------------
-#define LCD_PAL126_R04_0_Pos                                  0                                                         /*!< LCD PAL126: R04_0 Position          */
-#define LCD_PAL126_R04_0_Msk                                  (0x1fUL << LCD_PAL126_R04_0_Pos)                          /*!< LCD PAL126: R04_0 Mask              */
-#define LCD_PAL126_G04_0_Pos                                  5                                                         /*!< LCD PAL126: G04_0 Position          */
-#define LCD_PAL126_G04_0_Msk                                  (0x1fUL << LCD_PAL126_G04_0_Pos)                          /*!< LCD PAL126: G04_0 Mask              */
-#define LCD_PAL126_B04_0_Pos                                  10                                                        /*!< LCD PAL126: B04_0 Position          */
-#define LCD_PAL126_B04_0_Msk                                  (0x1fUL << LCD_PAL126_B04_0_Pos)                          /*!< LCD PAL126: B04_0 Mask              */
-#define LCD_PAL126_I0_Pos                                     15                                                        /*!< LCD PAL126: I0 Position             */
-#define LCD_PAL126_I0_Msk                                     (0x01UL << LCD_PAL126_I0_Pos)                             /*!< LCD PAL126: I0 Mask                 */
-#define LCD_PAL126_R14_0_Pos                                  16                                                        /*!< LCD PAL126: R14_0 Position          */
-#define LCD_PAL126_R14_0_Msk                                  (0x1fUL << LCD_PAL126_R14_0_Pos)                          /*!< LCD PAL126: R14_0 Mask              */
-#define LCD_PAL126_G14_0_Pos                                  21                                                        /*!< LCD PAL126: G14_0 Position          */
-#define LCD_PAL126_G14_0_Msk                                  (0x1fUL << LCD_PAL126_G14_0_Pos)                          /*!< LCD PAL126: G14_0 Mask              */
-#define LCD_PAL126_B14_0_Pos                                  26                                                        /*!< LCD PAL126: B14_0 Position          */
-#define LCD_PAL126_B14_0_Msk                                  (0x1fUL << LCD_PAL126_B14_0_Pos)                          /*!< LCD PAL126: B14_0 Mask              */
-#define LCD_PAL126_I1_Pos                                     31                                                        /*!< LCD PAL126: I1 Position             */
-#define LCD_PAL126_I1_Msk                                     (0x01UL << LCD_PAL126_I1_Pos)                             /*!< LCD PAL126: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL127  -------------------------------------------
-#define LCD_PAL127_R04_0_Pos                                  0                                                         /*!< LCD PAL127: R04_0 Position          */
-#define LCD_PAL127_R04_0_Msk                                  (0x1fUL << LCD_PAL127_R04_0_Pos)                          /*!< LCD PAL127: R04_0 Mask              */
-#define LCD_PAL127_G04_0_Pos                                  5                                                         /*!< LCD PAL127: G04_0 Position          */
-#define LCD_PAL127_G04_0_Msk                                  (0x1fUL << LCD_PAL127_G04_0_Pos)                          /*!< LCD PAL127: G04_0 Mask              */
-#define LCD_PAL127_B04_0_Pos                                  10                                                        /*!< LCD PAL127: B04_0 Position          */
-#define LCD_PAL127_B04_0_Msk                                  (0x1fUL << LCD_PAL127_B04_0_Pos)                          /*!< LCD PAL127: B04_0 Mask              */
-#define LCD_PAL127_I0_Pos                                     15                                                        /*!< LCD PAL127: I0 Position             */
-#define LCD_PAL127_I0_Msk                                     (0x01UL << LCD_PAL127_I0_Pos)                             /*!< LCD PAL127: I0 Mask                 */
-#define LCD_PAL127_R14_0_Pos                                  16                                                        /*!< LCD PAL127: R14_0 Position          */
-#define LCD_PAL127_R14_0_Msk                                  (0x1fUL << LCD_PAL127_R14_0_Pos)                          /*!< LCD PAL127: R14_0 Mask              */
-#define LCD_PAL127_G14_0_Pos                                  21                                                        /*!< LCD PAL127: G14_0 Position          */
-#define LCD_PAL127_G14_0_Msk                                  (0x1fUL << LCD_PAL127_G14_0_Pos)                          /*!< LCD PAL127: G14_0 Mask              */
-#define LCD_PAL127_B14_0_Pos                                  26                                                        /*!< LCD PAL127: B14_0 Position          */
-#define LCD_PAL127_B14_0_Msk                                  (0x1fUL << LCD_PAL127_B14_0_Pos)                          /*!< LCD PAL127: B14_0 Mask              */
-#define LCD_PAL127_I1_Pos                                     31                                                        /*!< LCD PAL127: I1 Position             */
-#define LCD_PAL127_I1_Msk                                     (0x01UL << LCD_PAL127_I1_Pos)                             /*!< LCD PAL127: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL128  -------------------------------------------
-#define LCD_PAL128_R04_0_Pos                                  0                                                         /*!< LCD PAL128: R04_0 Position          */
-#define LCD_PAL128_R04_0_Msk                                  (0x1fUL << LCD_PAL128_R04_0_Pos)                          /*!< LCD PAL128: R04_0 Mask              */
-#define LCD_PAL128_G04_0_Pos                                  5                                                         /*!< LCD PAL128: G04_0 Position          */
-#define LCD_PAL128_G04_0_Msk                                  (0x1fUL << LCD_PAL128_G04_0_Pos)                          /*!< LCD PAL128: G04_0 Mask              */
-#define LCD_PAL128_B04_0_Pos                                  10                                                        /*!< LCD PAL128: B04_0 Position          */
-#define LCD_PAL128_B04_0_Msk                                  (0x1fUL << LCD_PAL128_B04_0_Pos)                          /*!< LCD PAL128: B04_0 Mask              */
-#define LCD_PAL128_I0_Pos                                     15                                                        /*!< LCD PAL128: I0 Position             */
-#define LCD_PAL128_I0_Msk                                     (0x01UL << LCD_PAL128_I0_Pos)                             /*!< LCD PAL128: I0 Mask                 */
-#define LCD_PAL128_R14_0_Pos                                  16                                                        /*!< LCD PAL128: R14_0 Position          */
-#define LCD_PAL128_R14_0_Msk                                  (0x1fUL << LCD_PAL128_R14_0_Pos)                          /*!< LCD PAL128: R14_0 Mask              */
-#define LCD_PAL128_G14_0_Pos                                  21                                                        /*!< LCD PAL128: G14_0 Position          */
-#define LCD_PAL128_G14_0_Msk                                  (0x1fUL << LCD_PAL128_G14_0_Pos)                          /*!< LCD PAL128: G14_0 Mask              */
-#define LCD_PAL128_B14_0_Pos                                  26                                                        /*!< LCD PAL128: B14_0 Position          */
-#define LCD_PAL128_B14_0_Msk                                  (0x1fUL << LCD_PAL128_B14_0_Pos)                          /*!< LCD PAL128: B14_0 Mask              */
-#define LCD_PAL128_I1_Pos                                     31                                                        /*!< LCD PAL128: I1 Position             */
-#define LCD_PAL128_I1_Msk                                     (0x01UL << LCD_PAL128_I1_Pos)                             /*!< LCD PAL128: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL129  -------------------------------------------
-#define LCD_PAL129_R04_0_Pos                                  0                                                         /*!< LCD PAL129: R04_0 Position          */
-#define LCD_PAL129_R04_0_Msk                                  (0x1fUL << LCD_PAL129_R04_0_Pos)                          /*!< LCD PAL129: R04_0 Mask              */
-#define LCD_PAL129_G04_0_Pos                                  5                                                         /*!< LCD PAL129: G04_0 Position          */
-#define LCD_PAL129_G04_0_Msk                                  (0x1fUL << LCD_PAL129_G04_0_Pos)                          /*!< LCD PAL129: G04_0 Mask              */
-#define LCD_PAL129_B04_0_Pos                                  10                                                        /*!< LCD PAL129: B04_0 Position          */
-#define LCD_PAL129_B04_0_Msk                                  (0x1fUL << LCD_PAL129_B04_0_Pos)                          /*!< LCD PAL129: B04_0 Mask              */
-#define LCD_PAL129_I0_Pos                                     15                                                        /*!< LCD PAL129: I0 Position             */
-#define LCD_PAL129_I0_Msk                                     (0x01UL << LCD_PAL129_I0_Pos)                             /*!< LCD PAL129: I0 Mask                 */
-#define LCD_PAL129_R14_0_Pos                                  16                                                        /*!< LCD PAL129: R14_0 Position          */
-#define LCD_PAL129_R14_0_Msk                                  (0x1fUL << LCD_PAL129_R14_0_Pos)                          /*!< LCD PAL129: R14_0 Mask              */
-#define LCD_PAL129_G14_0_Pos                                  21                                                        /*!< LCD PAL129: G14_0 Position          */
-#define LCD_PAL129_G14_0_Msk                                  (0x1fUL << LCD_PAL129_G14_0_Pos)                          /*!< LCD PAL129: G14_0 Mask              */
-#define LCD_PAL129_B14_0_Pos                                  26                                                        /*!< LCD PAL129: B14_0 Position          */
-#define LCD_PAL129_B14_0_Msk                                  (0x1fUL << LCD_PAL129_B14_0_Pos)                          /*!< LCD PAL129: B14_0 Mask              */
-#define LCD_PAL129_I1_Pos                                     31                                                        /*!< LCD PAL129: I1 Position             */
-#define LCD_PAL129_I1_Msk                                     (0x01UL << LCD_PAL129_I1_Pos)                             /*!< LCD PAL129: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL130  -------------------------------------------
-#define LCD_PAL130_R04_0_Pos                                  0                                                         /*!< LCD PAL130: R04_0 Position          */
-#define LCD_PAL130_R04_0_Msk                                  (0x1fUL << LCD_PAL130_R04_0_Pos)                          /*!< LCD PAL130: R04_0 Mask              */
-#define LCD_PAL130_G04_0_Pos                                  5                                                         /*!< LCD PAL130: G04_0 Position          */
-#define LCD_PAL130_G04_0_Msk                                  (0x1fUL << LCD_PAL130_G04_0_Pos)                          /*!< LCD PAL130: G04_0 Mask              */
-#define LCD_PAL130_B04_0_Pos                                  10                                                        /*!< LCD PAL130: B04_0 Position          */
-#define LCD_PAL130_B04_0_Msk                                  (0x1fUL << LCD_PAL130_B04_0_Pos)                          /*!< LCD PAL130: B04_0 Mask              */
-#define LCD_PAL130_I0_Pos                                     15                                                        /*!< LCD PAL130: I0 Position             */
-#define LCD_PAL130_I0_Msk                                     (0x01UL << LCD_PAL130_I0_Pos)                             /*!< LCD PAL130: I0 Mask                 */
-#define LCD_PAL130_R14_0_Pos                                  16                                                        /*!< LCD PAL130: R14_0 Position          */
-#define LCD_PAL130_R14_0_Msk                                  (0x1fUL << LCD_PAL130_R14_0_Pos)                          /*!< LCD PAL130: R14_0 Mask              */
-#define LCD_PAL130_G14_0_Pos                                  21                                                        /*!< LCD PAL130: G14_0 Position          */
-#define LCD_PAL130_G14_0_Msk                                  (0x1fUL << LCD_PAL130_G14_0_Pos)                          /*!< LCD PAL130: G14_0 Mask              */
-#define LCD_PAL130_B14_0_Pos                                  26                                                        /*!< LCD PAL130: B14_0 Position          */
-#define LCD_PAL130_B14_0_Msk                                  (0x1fUL << LCD_PAL130_B14_0_Pos)                          /*!< LCD PAL130: B14_0 Mask              */
-#define LCD_PAL130_I1_Pos                                     31                                                        /*!< LCD PAL130: I1 Position             */
-#define LCD_PAL130_I1_Msk                                     (0x01UL << LCD_PAL130_I1_Pos)                             /*!< LCD PAL130: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL131  -------------------------------------------
-#define LCD_PAL131_R04_0_Pos                                  0                                                         /*!< LCD PAL131: R04_0 Position          */
-#define LCD_PAL131_R04_0_Msk                                  (0x1fUL << LCD_PAL131_R04_0_Pos)                          /*!< LCD PAL131: R04_0 Mask              */
-#define LCD_PAL131_G04_0_Pos                                  5                                                         /*!< LCD PAL131: G04_0 Position          */
-#define LCD_PAL131_G04_0_Msk                                  (0x1fUL << LCD_PAL131_G04_0_Pos)                          /*!< LCD PAL131: G04_0 Mask              */
-#define LCD_PAL131_B04_0_Pos                                  10                                                        /*!< LCD PAL131: B04_0 Position          */
-#define LCD_PAL131_B04_0_Msk                                  (0x1fUL << LCD_PAL131_B04_0_Pos)                          /*!< LCD PAL131: B04_0 Mask              */
-#define LCD_PAL131_I0_Pos                                     15                                                        /*!< LCD PAL131: I0 Position             */
-#define LCD_PAL131_I0_Msk                                     (0x01UL << LCD_PAL131_I0_Pos)                             /*!< LCD PAL131: I0 Mask                 */
-#define LCD_PAL131_R14_0_Pos                                  16                                                        /*!< LCD PAL131: R14_0 Position          */
-#define LCD_PAL131_R14_0_Msk                                  (0x1fUL << LCD_PAL131_R14_0_Pos)                          /*!< LCD PAL131: R14_0 Mask              */
-#define LCD_PAL131_G14_0_Pos                                  21                                                        /*!< LCD PAL131: G14_0 Position          */
-#define LCD_PAL131_G14_0_Msk                                  (0x1fUL << LCD_PAL131_G14_0_Pos)                          /*!< LCD PAL131: G14_0 Mask              */
-#define LCD_PAL131_B14_0_Pos                                  26                                                        /*!< LCD PAL131: B14_0 Position          */
-#define LCD_PAL131_B14_0_Msk                                  (0x1fUL << LCD_PAL131_B14_0_Pos)                          /*!< LCD PAL131: B14_0 Mask              */
-#define LCD_PAL131_I1_Pos                                     31                                                        /*!< LCD PAL131: I1 Position             */
-#define LCD_PAL131_I1_Msk                                     (0x01UL << LCD_PAL131_I1_Pos)                             /*!< LCD PAL131: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL132  -------------------------------------------
-#define LCD_PAL132_R04_0_Pos                                  0                                                         /*!< LCD PAL132: R04_0 Position          */
-#define LCD_PAL132_R04_0_Msk                                  (0x1fUL << LCD_PAL132_R04_0_Pos)                          /*!< LCD PAL132: R04_0 Mask              */
-#define LCD_PAL132_G04_0_Pos                                  5                                                         /*!< LCD PAL132: G04_0 Position          */
-#define LCD_PAL132_G04_0_Msk                                  (0x1fUL << LCD_PAL132_G04_0_Pos)                          /*!< LCD PAL132: G04_0 Mask              */
-#define LCD_PAL132_B04_0_Pos                                  10                                                        /*!< LCD PAL132: B04_0 Position          */
-#define LCD_PAL132_B04_0_Msk                                  (0x1fUL << LCD_PAL132_B04_0_Pos)                          /*!< LCD PAL132: B04_0 Mask              */
-#define LCD_PAL132_I0_Pos                                     15                                                        /*!< LCD PAL132: I0 Position             */
-#define LCD_PAL132_I0_Msk                                     (0x01UL << LCD_PAL132_I0_Pos)                             /*!< LCD PAL132: I0 Mask                 */
-#define LCD_PAL132_R14_0_Pos                                  16                                                        /*!< LCD PAL132: R14_0 Position          */
-#define LCD_PAL132_R14_0_Msk                                  (0x1fUL << LCD_PAL132_R14_0_Pos)                          /*!< LCD PAL132: R14_0 Mask              */
-#define LCD_PAL132_G14_0_Pos                                  21                                                        /*!< LCD PAL132: G14_0 Position          */
-#define LCD_PAL132_G14_0_Msk                                  (0x1fUL << LCD_PAL132_G14_0_Pos)                          /*!< LCD PAL132: G14_0 Mask              */
-#define LCD_PAL132_B14_0_Pos                                  26                                                        /*!< LCD PAL132: B14_0 Position          */
-#define LCD_PAL132_B14_0_Msk                                  (0x1fUL << LCD_PAL132_B14_0_Pos)                          /*!< LCD PAL132: B14_0 Mask              */
-#define LCD_PAL132_I1_Pos                                     31                                                        /*!< LCD PAL132: I1 Position             */
-#define LCD_PAL132_I1_Msk                                     (0x01UL << LCD_PAL132_I1_Pos)                             /*!< LCD PAL132: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL133  -------------------------------------------
-#define LCD_PAL133_R04_0_Pos                                  0                                                         /*!< LCD PAL133: R04_0 Position          */
-#define LCD_PAL133_R04_0_Msk                                  (0x1fUL << LCD_PAL133_R04_0_Pos)                          /*!< LCD PAL133: R04_0 Mask              */
-#define LCD_PAL133_G04_0_Pos                                  5                                                         /*!< LCD PAL133: G04_0 Position          */
-#define LCD_PAL133_G04_0_Msk                                  (0x1fUL << LCD_PAL133_G04_0_Pos)                          /*!< LCD PAL133: G04_0 Mask              */
-#define LCD_PAL133_B04_0_Pos                                  10                                                        /*!< LCD PAL133: B04_0 Position          */
-#define LCD_PAL133_B04_0_Msk                                  (0x1fUL << LCD_PAL133_B04_0_Pos)                          /*!< LCD PAL133: B04_0 Mask              */
-#define LCD_PAL133_I0_Pos                                     15                                                        /*!< LCD PAL133: I0 Position             */
-#define LCD_PAL133_I0_Msk                                     (0x01UL << LCD_PAL133_I0_Pos)                             /*!< LCD PAL133: I0 Mask                 */
-#define LCD_PAL133_R14_0_Pos                                  16                                                        /*!< LCD PAL133: R14_0 Position          */
-#define LCD_PAL133_R14_0_Msk                                  (0x1fUL << LCD_PAL133_R14_0_Pos)                          /*!< LCD PAL133: R14_0 Mask              */
-#define LCD_PAL133_G14_0_Pos                                  21                                                        /*!< LCD PAL133: G14_0 Position          */
-#define LCD_PAL133_G14_0_Msk                                  (0x1fUL << LCD_PAL133_G14_0_Pos)                          /*!< LCD PAL133: G14_0 Mask              */
-#define LCD_PAL133_B14_0_Pos                                  26                                                        /*!< LCD PAL133: B14_0 Position          */
-#define LCD_PAL133_B14_0_Msk                                  (0x1fUL << LCD_PAL133_B14_0_Pos)                          /*!< LCD PAL133: B14_0 Mask              */
-#define LCD_PAL133_I1_Pos                                     31                                                        /*!< LCD PAL133: I1 Position             */
-#define LCD_PAL133_I1_Msk                                     (0x01UL << LCD_PAL133_I1_Pos)                             /*!< LCD PAL133: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL134  -------------------------------------------
-#define LCD_PAL134_R04_0_Pos                                  0                                                         /*!< LCD PAL134: R04_0 Position          */
-#define LCD_PAL134_R04_0_Msk                                  (0x1fUL << LCD_PAL134_R04_0_Pos)                          /*!< LCD PAL134: R04_0 Mask              */
-#define LCD_PAL134_G04_0_Pos                                  5                                                         /*!< LCD PAL134: G04_0 Position          */
-#define LCD_PAL134_G04_0_Msk                                  (0x1fUL << LCD_PAL134_G04_0_Pos)                          /*!< LCD PAL134: G04_0 Mask              */
-#define LCD_PAL134_B04_0_Pos                                  10                                                        /*!< LCD PAL134: B04_0 Position          */
-#define LCD_PAL134_B04_0_Msk                                  (0x1fUL << LCD_PAL134_B04_0_Pos)                          /*!< LCD PAL134: B04_0 Mask              */
-#define LCD_PAL134_I0_Pos                                     15                                                        /*!< LCD PAL134: I0 Position             */
-#define LCD_PAL134_I0_Msk                                     (0x01UL << LCD_PAL134_I0_Pos)                             /*!< LCD PAL134: I0 Mask                 */
-#define LCD_PAL134_R14_0_Pos                                  16                                                        /*!< LCD PAL134: R14_0 Position          */
-#define LCD_PAL134_R14_0_Msk                                  (0x1fUL << LCD_PAL134_R14_0_Pos)                          /*!< LCD PAL134: R14_0 Mask              */
-#define LCD_PAL134_G14_0_Pos                                  21                                                        /*!< LCD PAL134: G14_0 Position          */
-#define LCD_PAL134_G14_0_Msk                                  (0x1fUL << LCD_PAL134_G14_0_Pos)                          /*!< LCD PAL134: G14_0 Mask              */
-#define LCD_PAL134_B14_0_Pos                                  26                                                        /*!< LCD PAL134: B14_0 Position          */
-#define LCD_PAL134_B14_0_Msk                                  (0x1fUL << LCD_PAL134_B14_0_Pos)                          /*!< LCD PAL134: B14_0 Mask              */
-#define LCD_PAL134_I1_Pos                                     31                                                        /*!< LCD PAL134: I1 Position             */
-#define LCD_PAL134_I1_Msk                                     (0x01UL << LCD_PAL134_I1_Pos)                             /*!< LCD PAL134: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL135  -------------------------------------------
-#define LCD_PAL135_R04_0_Pos                                  0                                                         /*!< LCD PAL135: R04_0 Position          */
-#define LCD_PAL135_R04_0_Msk                                  (0x1fUL << LCD_PAL135_R04_0_Pos)                          /*!< LCD PAL135: R04_0 Mask              */
-#define LCD_PAL135_G04_0_Pos                                  5                                                         /*!< LCD PAL135: G04_0 Position          */
-#define LCD_PAL135_G04_0_Msk                                  (0x1fUL << LCD_PAL135_G04_0_Pos)                          /*!< LCD PAL135: G04_0 Mask              */
-#define LCD_PAL135_B04_0_Pos                                  10                                                        /*!< LCD PAL135: B04_0 Position          */
-#define LCD_PAL135_B04_0_Msk                                  (0x1fUL << LCD_PAL135_B04_0_Pos)                          /*!< LCD PAL135: B04_0 Mask              */
-#define LCD_PAL135_I0_Pos                                     15                                                        /*!< LCD PAL135: I0 Position             */
-#define LCD_PAL135_I0_Msk                                     (0x01UL << LCD_PAL135_I0_Pos)                             /*!< LCD PAL135: I0 Mask                 */
-#define LCD_PAL135_R14_0_Pos                                  16                                                        /*!< LCD PAL135: R14_0 Position          */
-#define LCD_PAL135_R14_0_Msk                                  (0x1fUL << LCD_PAL135_R14_0_Pos)                          /*!< LCD PAL135: R14_0 Mask              */
-#define LCD_PAL135_G14_0_Pos                                  21                                                        /*!< LCD PAL135: G14_0 Position          */
-#define LCD_PAL135_G14_0_Msk                                  (0x1fUL << LCD_PAL135_G14_0_Pos)                          /*!< LCD PAL135: G14_0 Mask              */
-#define LCD_PAL135_B14_0_Pos                                  26                                                        /*!< LCD PAL135: B14_0 Position          */
-#define LCD_PAL135_B14_0_Msk                                  (0x1fUL << LCD_PAL135_B14_0_Pos)                          /*!< LCD PAL135: B14_0 Mask              */
-#define LCD_PAL135_I1_Pos                                     31                                                        /*!< LCD PAL135: I1 Position             */
-#define LCD_PAL135_I1_Msk                                     (0x01UL << LCD_PAL135_I1_Pos)                             /*!< LCD PAL135: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL136  -------------------------------------------
-#define LCD_PAL136_R04_0_Pos                                  0                                                         /*!< LCD PAL136: R04_0 Position          */
-#define LCD_PAL136_R04_0_Msk                                  (0x1fUL << LCD_PAL136_R04_0_Pos)                          /*!< LCD PAL136: R04_0 Mask              */
-#define LCD_PAL136_G04_0_Pos                                  5                                                         /*!< LCD PAL136: G04_0 Position          */
-#define LCD_PAL136_G04_0_Msk                                  (0x1fUL << LCD_PAL136_G04_0_Pos)                          /*!< LCD PAL136: G04_0 Mask              */
-#define LCD_PAL136_B04_0_Pos                                  10                                                        /*!< LCD PAL136: B04_0 Position          */
-#define LCD_PAL136_B04_0_Msk                                  (0x1fUL << LCD_PAL136_B04_0_Pos)                          /*!< LCD PAL136: B04_0 Mask              */
-#define LCD_PAL136_I0_Pos                                     15                                                        /*!< LCD PAL136: I0 Position             */
-#define LCD_PAL136_I0_Msk                                     (0x01UL << LCD_PAL136_I0_Pos)                             /*!< LCD PAL136: I0 Mask                 */
-#define LCD_PAL136_R14_0_Pos                                  16                                                        /*!< LCD PAL136: R14_0 Position          */
-#define LCD_PAL136_R14_0_Msk                                  (0x1fUL << LCD_PAL136_R14_0_Pos)                          /*!< LCD PAL136: R14_0 Mask              */
-#define LCD_PAL136_G14_0_Pos                                  21                                                        /*!< LCD PAL136: G14_0 Position          */
-#define LCD_PAL136_G14_0_Msk                                  (0x1fUL << LCD_PAL136_G14_0_Pos)                          /*!< LCD PAL136: G14_0 Mask              */
-#define LCD_PAL136_B14_0_Pos                                  26                                                        /*!< LCD PAL136: B14_0 Position          */
-#define LCD_PAL136_B14_0_Msk                                  (0x1fUL << LCD_PAL136_B14_0_Pos)                          /*!< LCD PAL136: B14_0 Mask              */
-#define LCD_PAL136_I1_Pos                                     31                                                        /*!< LCD PAL136: I1 Position             */
-#define LCD_PAL136_I1_Msk                                     (0x01UL << LCD_PAL136_I1_Pos)                             /*!< LCD PAL136: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL137  -------------------------------------------
-#define LCD_PAL137_R04_0_Pos                                  0                                                         /*!< LCD PAL137: R04_0 Position          */
-#define LCD_PAL137_R04_0_Msk                                  (0x1fUL << LCD_PAL137_R04_0_Pos)                          /*!< LCD PAL137: R04_0 Mask              */
-#define LCD_PAL137_G04_0_Pos                                  5                                                         /*!< LCD PAL137: G04_0 Position          */
-#define LCD_PAL137_G04_0_Msk                                  (0x1fUL << LCD_PAL137_G04_0_Pos)                          /*!< LCD PAL137: G04_0 Mask              */
-#define LCD_PAL137_B04_0_Pos                                  10                                                        /*!< LCD PAL137: B04_0 Position          */
-#define LCD_PAL137_B04_0_Msk                                  (0x1fUL << LCD_PAL137_B04_0_Pos)                          /*!< LCD PAL137: B04_0 Mask              */
-#define LCD_PAL137_I0_Pos                                     15                                                        /*!< LCD PAL137: I0 Position             */
-#define LCD_PAL137_I0_Msk                                     (0x01UL << LCD_PAL137_I0_Pos)                             /*!< LCD PAL137: I0 Mask                 */
-#define LCD_PAL137_R14_0_Pos                                  16                                                        /*!< LCD PAL137: R14_0 Position          */
-#define LCD_PAL137_R14_0_Msk                                  (0x1fUL << LCD_PAL137_R14_0_Pos)                          /*!< LCD PAL137: R14_0 Mask              */
-#define LCD_PAL137_G14_0_Pos                                  21                                                        /*!< LCD PAL137: G14_0 Position          */
-#define LCD_PAL137_G14_0_Msk                                  (0x1fUL << LCD_PAL137_G14_0_Pos)                          /*!< LCD PAL137: G14_0 Mask              */
-#define LCD_PAL137_B14_0_Pos                                  26                                                        /*!< LCD PAL137: B14_0 Position          */
-#define LCD_PAL137_B14_0_Msk                                  (0x1fUL << LCD_PAL137_B14_0_Pos)                          /*!< LCD PAL137: B14_0 Mask              */
-#define LCD_PAL137_I1_Pos                                     31                                                        /*!< LCD PAL137: I1 Position             */
-#define LCD_PAL137_I1_Msk                                     (0x01UL << LCD_PAL137_I1_Pos)                             /*!< LCD PAL137: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL138  -------------------------------------------
-#define LCD_PAL138_R04_0_Pos                                  0                                                         /*!< LCD PAL138: R04_0 Position          */
-#define LCD_PAL138_R04_0_Msk                                  (0x1fUL << LCD_PAL138_R04_0_Pos)                          /*!< LCD PAL138: R04_0 Mask              */
-#define LCD_PAL138_G04_0_Pos                                  5                                                         /*!< LCD PAL138: G04_0 Position          */
-#define LCD_PAL138_G04_0_Msk                                  (0x1fUL << LCD_PAL138_G04_0_Pos)                          /*!< LCD PAL138: G04_0 Mask              */
-#define LCD_PAL138_B04_0_Pos                                  10                                                        /*!< LCD PAL138: B04_0 Position          */
-#define LCD_PAL138_B04_0_Msk                                  (0x1fUL << LCD_PAL138_B04_0_Pos)                          /*!< LCD PAL138: B04_0 Mask              */
-#define LCD_PAL138_I0_Pos                                     15                                                        /*!< LCD PAL138: I0 Position             */
-#define LCD_PAL138_I0_Msk                                     (0x01UL << LCD_PAL138_I0_Pos)                             /*!< LCD PAL138: I0 Mask                 */
-#define LCD_PAL138_R14_0_Pos                                  16                                                        /*!< LCD PAL138: R14_0 Position          */
-#define LCD_PAL138_R14_0_Msk                                  (0x1fUL << LCD_PAL138_R14_0_Pos)                          /*!< LCD PAL138: R14_0 Mask              */
-#define LCD_PAL138_G14_0_Pos                                  21                                                        /*!< LCD PAL138: G14_0 Position          */
-#define LCD_PAL138_G14_0_Msk                                  (0x1fUL << LCD_PAL138_G14_0_Pos)                          /*!< LCD PAL138: G14_0 Mask              */
-#define LCD_PAL138_B14_0_Pos                                  26                                                        /*!< LCD PAL138: B14_0 Position          */
-#define LCD_PAL138_B14_0_Msk                                  (0x1fUL << LCD_PAL138_B14_0_Pos)                          /*!< LCD PAL138: B14_0 Mask              */
-#define LCD_PAL138_I1_Pos                                     31                                                        /*!< LCD PAL138: I1 Position             */
-#define LCD_PAL138_I1_Msk                                     (0x01UL << LCD_PAL138_I1_Pos)                             /*!< LCD PAL138: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL139  -------------------------------------------
-#define LCD_PAL139_R04_0_Pos                                  0                                                         /*!< LCD PAL139: R04_0 Position          */
-#define LCD_PAL139_R04_0_Msk                                  (0x1fUL << LCD_PAL139_R04_0_Pos)                          /*!< LCD PAL139: R04_0 Mask              */
-#define LCD_PAL139_G04_0_Pos                                  5                                                         /*!< LCD PAL139: G04_0 Position          */
-#define LCD_PAL139_G04_0_Msk                                  (0x1fUL << LCD_PAL139_G04_0_Pos)                          /*!< LCD PAL139: G04_0 Mask              */
-#define LCD_PAL139_B04_0_Pos                                  10                                                        /*!< LCD PAL139: B04_0 Position          */
-#define LCD_PAL139_B04_0_Msk                                  (0x1fUL << LCD_PAL139_B04_0_Pos)                          /*!< LCD PAL139: B04_0 Mask              */
-#define LCD_PAL139_I0_Pos                                     15                                                        /*!< LCD PAL139: I0 Position             */
-#define LCD_PAL139_I0_Msk                                     (0x01UL << LCD_PAL139_I0_Pos)                             /*!< LCD PAL139: I0 Mask                 */
-#define LCD_PAL139_R14_0_Pos                                  16                                                        /*!< LCD PAL139: R14_0 Position          */
-#define LCD_PAL139_R14_0_Msk                                  (0x1fUL << LCD_PAL139_R14_0_Pos)                          /*!< LCD PAL139: R14_0 Mask              */
-#define LCD_PAL139_G14_0_Pos                                  21                                                        /*!< LCD PAL139: G14_0 Position          */
-#define LCD_PAL139_G14_0_Msk                                  (0x1fUL << LCD_PAL139_G14_0_Pos)                          /*!< LCD PAL139: G14_0 Mask              */
-#define LCD_PAL139_B14_0_Pos                                  26                                                        /*!< LCD PAL139: B14_0 Position          */
-#define LCD_PAL139_B14_0_Msk                                  (0x1fUL << LCD_PAL139_B14_0_Pos)                          /*!< LCD PAL139: B14_0 Mask              */
-#define LCD_PAL139_I1_Pos                                     31                                                        /*!< LCD PAL139: I1 Position             */
-#define LCD_PAL139_I1_Msk                                     (0x01UL << LCD_PAL139_I1_Pos)                             /*!< LCD PAL139: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL140  -------------------------------------------
-#define LCD_PAL140_R04_0_Pos                                  0                                                         /*!< LCD PAL140: R04_0 Position          */
-#define LCD_PAL140_R04_0_Msk                                  (0x1fUL << LCD_PAL140_R04_0_Pos)                          /*!< LCD PAL140: R04_0 Mask              */
-#define LCD_PAL140_G04_0_Pos                                  5                                                         /*!< LCD PAL140: G04_0 Position          */
-#define LCD_PAL140_G04_0_Msk                                  (0x1fUL << LCD_PAL140_G04_0_Pos)                          /*!< LCD PAL140: G04_0 Mask              */
-#define LCD_PAL140_B04_0_Pos                                  10                                                        /*!< LCD PAL140: B04_0 Position          */
-#define LCD_PAL140_B04_0_Msk                                  (0x1fUL << LCD_PAL140_B04_0_Pos)                          /*!< LCD PAL140: B04_0 Mask              */
-#define LCD_PAL140_I0_Pos                                     15                                                        /*!< LCD PAL140: I0 Position             */
-#define LCD_PAL140_I0_Msk                                     (0x01UL << LCD_PAL140_I0_Pos)                             /*!< LCD PAL140: I0 Mask                 */
-#define LCD_PAL140_R14_0_Pos                                  16                                                        /*!< LCD PAL140: R14_0 Position          */
-#define LCD_PAL140_R14_0_Msk                                  (0x1fUL << LCD_PAL140_R14_0_Pos)                          /*!< LCD PAL140: R14_0 Mask              */
-#define LCD_PAL140_G14_0_Pos                                  21                                                        /*!< LCD PAL140: G14_0 Position          */
-#define LCD_PAL140_G14_0_Msk                                  (0x1fUL << LCD_PAL140_G14_0_Pos)                          /*!< LCD PAL140: G14_0 Mask              */
-#define LCD_PAL140_B14_0_Pos                                  26                                                        /*!< LCD PAL140: B14_0 Position          */
-#define LCD_PAL140_B14_0_Msk                                  (0x1fUL << LCD_PAL140_B14_0_Pos)                          /*!< LCD PAL140: B14_0 Mask              */
-#define LCD_PAL140_I1_Pos                                     31                                                        /*!< LCD PAL140: I1 Position             */
-#define LCD_PAL140_I1_Msk                                     (0x01UL << LCD_PAL140_I1_Pos)                             /*!< LCD PAL140: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL141  -------------------------------------------
-#define LCD_PAL141_R04_0_Pos                                  0                                                         /*!< LCD PAL141: R04_0 Position          */
-#define LCD_PAL141_R04_0_Msk                                  (0x1fUL << LCD_PAL141_R04_0_Pos)                          /*!< LCD PAL141: R04_0 Mask              */
-#define LCD_PAL141_G04_0_Pos                                  5                                                         /*!< LCD PAL141: G04_0 Position          */
-#define LCD_PAL141_G04_0_Msk                                  (0x1fUL << LCD_PAL141_G04_0_Pos)                          /*!< LCD PAL141: G04_0 Mask              */
-#define LCD_PAL141_B04_0_Pos                                  10                                                        /*!< LCD PAL141: B04_0 Position          */
-#define LCD_PAL141_B04_0_Msk                                  (0x1fUL << LCD_PAL141_B04_0_Pos)                          /*!< LCD PAL141: B04_0 Mask              */
-#define LCD_PAL141_I0_Pos                                     15                                                        /*!< LCD PAL141: I0 Position             */
-#define LCD_PAL141_I0_Msk                                     (0x01UL << LCD_PAL141_I0_Pos)                             /*!< LCD PAL141: I0 Mask                 */
-#define LCD_PAL141_R14_0_Pos                                  16                                                        /*!< LCD PAL141: R14_0 Position          */
-#define LCD_PAL141_R14_0_Msk                                  (0x1fUL << LCD_PAL141_R14_0_Pos)                          /*!< LCD PAL141: R14_0 Mask              */
-#define LCD_PAL141_G14_0_Pos                                  21                                                        /*!< LCD PAL141: G14_0 Position          */
-#define LCD_PAL141_G14_0_Msk                                  (0x1fUL << LCD_PAL141_G14_0_Pos)                          /*!< LCD PAL141: G14_0 Mask              */
-#define LCD_PAL141_B14_0_Pos                                  26                                                        /*!< LCD PAL141: B14_0 Position          */
-#define LCD_PAL141_B14_0_Msk                                  (0x1fUL << LCD_PAL141_B14_0_Pos)                          /*!< LCD PAL141: B14_0 Mask              */
-#define LCD_PAL141_I1_Pos                                     31                                                        /*!< LCD PAL141: I1 Position             */
-#define LCD_PAL141_I1_Msk                                     (0x01UL << LCD_PAL141_I1_Pos)                             /*!< LCD PAL141: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL142  -------------------------------------------
-#define LCD_PAL142_R04_0_Pos                                  0                                                         /*!< LCD PAL142: R04_0 Position          */
-#define LCD_PAL142_R04_0_Msk                                  (0x1fUL << LCD_PAL142_R04_0_Pos)                          /*!< LCD PAL142: R04_0 Mask              */
-#define LCD_PAL142_G04_0_Pos                                  5                                                         /*!< LCD PAL142: G04_0 Position          */
-#define LCD_PAL142_G04_0_Msk                                  (0x1fUL << LCD_PAL142_G04_0_Pos)                          /*!< LCD PAL142: G04_0 Mask              */
-#define LCD_PAL142_B04_0_Pos                                  10                                                        /*!< LCD PAL142: B04_0 Position          */
-#define LCD_PAL142_B04_0_Msk                                  (0x1fUL << LCD_PAL142_B04_0_Pos)                          /*!< LCD PAL142: B04_0 Mask              */
-#define LCD_PAL142_I0_Pos                                     15                                                        /*!< LCD PAL142: I0 Position             */
-#define LCD_PAL142_I0_Msk                                     (0x01UL << LCD_PAL142_I0_Pos)                             /*!< LCD PAL142: I0 Mask                 */
-#define LCD_PAL142_R14_0_Pos                                  16                                                        /*!< LCD PAL142: R14_0 Position          */
-#define LCD_PAL142_R14_0_Msk                                  (0x1fUL << LCD_PAL142_R14_0_Pos)                          /*!< LCD PAL142: R14_0 Mask              */
-#define LCD_PAL142_G14_0_Pos                                  21                                                        /*!< LCD PAL142: G14_0 Position          */
-#define LCD_PAL142_G14_0_Msk                                  (0x1fUL << LCD_PAL142_G14_0_Pos)                          /*!< LCD PAL142: G14_0 Mask              */
-#define LCD_PAL142_B14_0_Pos                                  26                                                        /*!< LCD PAL142: B14_0 Position          */
-#define LCD_PAL142_B14_0_Msk                                  (0x1fUL << LCD_PAL142_B14_0_Pos)                          /*!< LCD PAL142: B14_0 Mask              */
-#define LCD_PAL142_I1_Pos                                     31                                                        /*!< LCD PAL142: I1 Position             */
-#define LCD_PAL142_I1_Msk                                     (0x01UL << LCD_PAL142_I1_Pos)                             /*!< LCD PAL142: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL143  -------------------------------------------
-#define LCD_PAL143_R04_0_Pos                                  0                                                         /*!< LCD PAL143: R04_0 Position          */
-#define LCD_PAL143_R04_0_Msk                                  (0x1fUL << LCD_PAL143_R04_0_Pos)                          /*!< LCD PAL143: R04_0 Mask              */
-#define LCD_PAL143_G04_0_Pos                                  5                                                         /*!< LCD PAL143: G04_0 Position          */
-#define LCD_PAL143_G04_0_Msk                                  (0x1fUL << LCD_PAL143_G04_0_Pos)                          /*!< LCD PAL143: G04_0 Mask              */
-#define LCD_PAL143_B04_0_Pos                                  10                                                        /*!< LCD PAL143: B04_0 Position          */
-#define LCD_PAL143_B04_0_Msk                                  (0x1fUL << LCD_PAL143_B04_0_Pos)                          /*!< LCD PAL143: B04_0 Mask              */
-#define LCD_PAL143_I0_Pos                                     15                                                        /*!< LCD PAL143: I0 Position             */
-#define LCD_PAL143_I0_Msk                                     (0x01UL << LCD_PAL143_I0_Pos)                             /*!< LCD PAL143: I0 Mask                 */
-#define LCD_PAL143_R14_0_Pos                                  16                                                        /*!< LCD PAL143: R14_0 Position          */
-#define LCD_PAL143_R14_0_Msk                                  (0x1fUL << LCD_PAL143_R14_0_Pos)                          /*!< LCD PAL143: R14_0 Mask              */
-#define LCD_PAL143_G14_0_Pos                                  21                                                        /*!< LCD PAL143: G14_0 Position          */
-#define LCD_PAL143_G14_0_Msk                                  (0x1fUL << LCD_PAL143_G14_0_Pos)                          /*!< LCD PAL143: G14_0 Mask              */
-#define LCD_PAL143_B14_0_Pos                                  26                                                        /*!< LCD PAL143: B14_0 Position          */
-#define LCD_PAL143_B14_0_Msk                                  (0x1fUL << LCD_PAL143_B14_0_Pos)                          /*!< LCD PAL143: B14_0 Mask              */
-#define LCD_PAL143_I1_Pos                                     31                                                        /*!< LCD PAL143: I1 Position             */
-#define LCD_PAL143_I1_Msk                                     (0x01UL << LCD_PAL143_I1_Pos)                             /*!< LCD PAL143: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL144  -------------------------------------------
-#define LCD_PAL144_R04_0_Pos                                  0                                                         /*!< LCD PAL144: R04_0 Position          */
-#define LCD_PAL144_R04_0_Msk                                  (0x1fUL << LCD_PAL144_R04_0_Pos)                          /*!< LCD PAL144: R04_0 Mask              */
-#define LCD_PAL144_G04_0_Pos                                  5                                                         /*!< LCD PAL144: G04_0 Position          */
-#define LCD_PAL144_G04_0_Msk                                  (0x1fUL << LCD_PAL144_G04_0_Pos)                          /*!< LCD PAL144: G04_0 Mask              */
-#define LCD_PAL144_B04_0_Pos                                  10                                                        /*!< LCD PAL144: B04_0 Position          */
-#define LCD_PAL144_B04_0_Msk                                  (0x1fUL << LCD_PAL144_B04_0_Pos)                          /*!< LCD PAL144: B04_0 Mask              */
-#define LCD_PAL144_I0_Pos                                     15                                                        /*!< LCD PAL144: I0 Position             */
-#define LCD_PAL144_I0_Msk                                     (0x01UL << LCD_PAL144_I0_Pos)                             /*!< LCD PAL144: I0 Mask                 */
-#define LCD_PAL144_R14_0_Pos                                  16                                                        /*!< LCD PAL144: R14_0 Position          */
-#define LCD_PAL144_R14_0_Msk                                  (0x1fUL << LCD_PAL144_R14_0_Pos)                          /*!< LCD PAL144: R14_0 Mask              */
-#define LCD_PAL144_G14_0_Pos                                  21                                                        /*!< LCD PAL144: G14_0 Position          */
-#define LCD_PAL144_G14_0_Msk                                  (0x1fUL << LCD_PAL144_G14_0_Pos)                          /*!< LCD PAL144: G14_0 Mask              */
-#define LCD_PAL144_B14_0_Pos                                  26                                                        /*!< LCD PAL144: B14_0 Position          */
-#define LCD_PAL144_B14_0_Msk                                  (0x1fUL << LCD_PAL144_B14_0_Pos)                          /*!< LCD PAL144: B14_0 Mask              */
-#define LCD_PAL144_I1_Pos                                     31                                                        /*!< LCD PAL144: I1 Position             */
-#define LCD_PAL144_I1_Msk                                     (0x01UL << LCD_PAL144_I1_Pos)                             /*!< LCD PAL144: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL145  -------------------------------------------
-#define LCD_PAL145_R04_0_Pos                                  0                                                         /*!< LCD PAL145: R04_0 Position          */
-#define LCD_PAL145_R04_0_Msk                                  (0x1fUL << LCD_PAL145_R04_0_Pos)                          /*!< LCD PAL145: R04_0 Mask              */
-#define LCD_PAL145_G04_0_Pos                                  5                                                         /*!< LCD PAL145: G04_0 Position          */
-#define LCD_PAL145_G04_0_Msk                                  (0x1fUL << LCD_PAL145_G04_0_Pos)                          /*!< LCD PAL145: G04_0 Mask              */
-#define LCD_PAL145_B04_0_Pos                                  10                                                        /*!< LCD PAL145: B04_0 Position          */
-#define LCD_PAL145_B04_0_Msk                                  (0x1fUL << LCD_PAL145_B04_0_Pos)                          /*!< LCD PAL145: B04_0 Mask              */
-#define LCD_PAL145_I0_Pos                                     15                                                        /*!< LCD PAL145: I0 Position             */
-#define LCD_PAL145_I0_Msk                                     (0x01UL << LCD_PAL145_I0_Pos)                             /*!< LCD PAL145: I0 Mask                 */
-#define LCD_PAL145_R14_0_Pos                                  16                                                        /*!< LCD PAL145: R14_0 Position          */
-#define LCD_PAL145_R14_0_Msk                                  (0x1fUL << LCD_PAL145_R14_0_Pos)                          /*!< LCD PAL145: R14_0 Mask              */
-#define LCD_PAL145_G14_0_Pos                                  21                                                        /*!< LCD PAL145: G14_0 Position          */
-#define LCD_PAL145_G14_0_Msk                                  (0x1fUL << LCD_PAL145_G14_0_Pos)                          /*!< LCD PAL145: G14_0 Mask              */
-#define LCD_PAL145_B14_0_Pos                                  26                                                        /*!< LCD PAL145: B14_0 Position          */
-#define LCD_PAL145_B14_0_Msk                                  (0x1fUL << LCD_PAL145_B14_0_Pos)                          /*!< LCD PAL145: B14_0 Mask              */
-#define LCD_PAL145_I1_Pos                                     31                                                        /*!< LCD PAL145: I1 Position             */
-#define LCD_PAL145_I1_Msk                                     (0x01UL << LCD_PAL145_I1_Pos)                             /*!< LCD PAL145: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL146  -------------------------------------------
-#define LCD_PAL146_R04_0_Pos                                  0                                                         /*!< LCD PAL146: R04_0 Position          */
-#define LCD_PAL146_R04_0_Msk                                  (0x1fUL << LCD_PAL146_R04_0_Pos)                          /*!< LCD PAL146: R04_0 Mask              */
-#define LCD_PAL146_G04_0_Pos                                  5                                                         /*!< LCD PAL146: G04_0 Position          */
-#define LCD_PAL146_G04_0_Msk                                  (0x1fUL << LCD_PAL146_G04_0_Pos)                          /*!< LCD PAL146: G04_0 Mask              */
-#define LCD_PAL146_B04_0_Pos                                  10                                                        /*!< LCD PAL146: B04_0 Position          */
-#define LCD_PAL146_B04_0_Msk                                  (0x1fUL << LCD_PAL146_B04_0_Pos)                          /*!< LCD PAL146: B04_0 Mask              */
-#define LCD_PAL146_I0_Pos                                     15                                                        /*!< LCD PAL146: I0 Position             */
-#define LCD_PAL146_I0_Msk                                     (0x01UL << LCD_PAL146_I0_Pos)                             /*!< LCD PAL146: I0 Mask                 */
-#define LCD_PAL146_R14_0_Pos                                  16                                                        /*!< LCD PAL146: R14_0 Position          */
-#define LCD_PAL146_R14_0_Msk                                  (0x1fUL << LCD_PAL146_R14_0_Pos)                          /*!< LCD PAL146: R14_0 Mask              */
-#define LCD_PAL146_G14_0_Pos                                  21                                                        /*!< LCD PAL146: G14_0 Position          */
-#define LCD_PAL146_G14_0_Msk                                  (0x1fUL << LCD_PAL146_G14_0_Pos)                          /*!< LCD PAL146: G14_0 Mask              */
-#define LCD_PAL146_B14_0_Pos                                  26                                                        /*!< LCD PAL146: B14_0 Position          */
-#define LCD_PAL146_B14_0_Msk                                  (0x1fUL << LCD_PAL146_B14_0_Pos)                          /*!< LCD PAL146: B14_0 Mask              */
-#define LCD_PAL146_I1_Pos                                     31                                                        /*!< LCD PAL146: I1 Position             */
-#define LCD_PAL146_I1_Msk                                     (0x01UL << LCD_PAL146_I1_Pos)                             /*!< LCD PAL146: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL147  -------------------------------------------
-#define LCD_PAL147_R04_0_Pos                                  0                                                         /*!< LCD PAL147: R04_0 Position          */
-#define LCD_PAL147_R04_0_Msk                                  (0x1fUL << LCD_PAL147_R04_0_Pos)                          /*!< LCD PAL147: R04_0 Mask              */
-#define LCD_PAL147_G04_0_Pos                                  5                                                         /*!< LCD PAL147: G04_0 Position          */
-#define LCD_PAL147_G04_0_Msk                                  (0x1fUL << LCD_PAL147_G04_0_Pos)                          /*!< LCD PAL147: G04_0 Mask              */
-#define LCD_PAL147_B04_0_Pos                                  10                                                        /*!< LCD PAL147: B04_0 Position          */
-#define LCD_PAL147_B04_0_Msk                                  (0x1fUL << LCD_PAL147_B04_0_Pos)                          /*!< LCD PAL147: B04_0 Mask              */
-#define LCD_PAL147_I0_Pos                                     15                                                        /*!< LCD PAL147: I0 Position             */
-#define LCD_PAL147_I0_Msk                                     (0x01UL << LCD_PAL147_I0_Pos)                             /*!< LCD PAL147: I0 Mask                 */
-#define LCD_PAL147_R14_0_Pos                                  16                                                        /*!< LCD PAL147: R14_0 Position          */
-#define LCD_PAL147_R14_0_Msk                                  (0x1fUL << LCD_PAL147_R14_0_Pos)                          /*!< LCD PAL147: R14_0 Mask              */
-#define LCD_PAL147_G14_0_Pos                                  21                                                        /*!< LCD PAL147: G14_0 Position          */
-#define LCD_PAL147_G14_0_Msk                                  (0x1fUL << LCD_PAL147_G14_0_Pos)                          /*!< LCD PAL147: G14_0 Mask              */
-#define LCD_PAL147_B14_0_Pos                                  26                                                        /*!< LCD PAL147: B14_0 Position          */
-#define LCD_PAL147_B14_0_Msk                                  (0x1fUL << LCD_PAL147_B14_0_Pos)                          /*!< LCD PAL147: B14_0 Mask              */
-#define LCD_PAL147_I1_Pos                                     31                                                        /*!< LCD PAL147: I1 Position             */
-#define LCD_PAL147_I1_Msk                                     (0x01UL << LCD_PAL147_I1_Pos)                             /*!< LCD PAL147: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL148  -------------------------------------------
-#define LCD_PAL148_R04_0_Pos                                  0                                                         /*!< LCD PAL148: R04_0 Position          */
-#define LCD_PAL148_R04_0_Msk                                  (0x1fUL << LCD_PAL148_R04_0_Pos)                          /*!< LCD PAL148: R04_0 Mask              */
-#define LCD_PAL148_G04_0_Pos                                  5                                                         /*!< LCD PAL148: G04_0 Position          */
-#define LCD_PAL148_G04_0_Msk                                  (0x1fUL << LCD_PAL148_G04_0_Pos)                          /*!< LCD PAL148: G04_0 Mask              */
-#define LCD_PAL148_B04_0_Pos                                  10                                                        /*!< LCD PAL148: B04_0 Position          */
-#define LCD_PAL148_B04_0_Msk                                  (0x1fUL << LCD_PAL148_B04_0_Pos)                          /*!< LCD PAL148: B04_0 Mask              */
-#define LCD_PAL148_I0_Pos                                     15                                                        /*!< LCD PAL148: I0 Position             */
-#define LCD_PAL148_I0_Msk                                     (0x01UL << LCD_PAL148_I0_Pos)                             /*!< LCD PAL148: I0 Mask                 */
-#define LCD_PAL148_R14_0_Pos                                  16                                                        /*!< LCD PAL148: R14_0 Position          */
-#define LCD_PAL148_R14_0_Msk                                  (0x1fUL << LCD_PAL148_R14_0_Pos)                          /*!< LCD PAL148: R14_0 Mask              */
-#define LCD_PAL148_G14_0_Pos                                  21                                                        /*!< LCD PAL148: G14_0 Position          */
-#define LCD_PAL148_G14_0_Msk                                  (0x1fUL << LCD_PAL148_G14_0_Pos)                          /*!< LCD PAL148: G14_0 Mask              */
-#define LCD_PAL148_B14_0_Pos                                  26                                                        /*!< LCD PAL148: B14_0 Position          */
-#define LCD_PAL148_B14_0_Msk                                  (0x1fUL << LCD_PAL148_B14_0_Pos)                          /*!< LCD PAL148: B14_0 Mask              */
-#define LCD_PAL148_I1_Pos                                     31                                                        /*!< LCD PAL148: I1 Position             */
-#define LCD_PAL148_I1_Msk                                     (0x01UL << LCD_PAL148_I1_Pos)                             /*!< LCD PAL148: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL149  -------------------------------------------
-#define LCD_PAL149_R04_0_Pos                                  0                                                         /*!< LCD PAL149: R04_0 Position          */
-#define LCD_PAL149_R04_0_Msk                                  (0x1fUL << LCD_PAL149_R04_0_Pos)                          /*!< LCD PAL149: R04_0 Mask              */
-#define LCD_PAL149_G04_0_Pos                                  5                                                         /*!< LCD PAL149: G04_0 Position          */
-#define LCD_PAL149_G04_0_Msk                                  (0x1fUL << LCD_PAL149_G04_0_Pos)                          /*!< LCD PAL149: G04_0 Mask              */
-#define LCD_PAL149_B04_0_Pos                                  10                                                        /*!< LCD PAL149: B04_0 Position          */
-#define LCD_PAL149_B04_0_Msk                                  (0x1fUL << LCD_PAL149_B04_0_Pos)                          /*!< LCD PAL149: B04_0 Mask              */
-#define LCD_PAL149_I0_Pos                                     15                                                        /*!< LCD PAL149: I0 Position             */
-#define LCD_PAL149_I0_Msk                                     (0x01UL << LCD_PAL149_I0_Pos)                             /*!< LCD PAL149: I0 Mask                 */
-#define LCD_PAL149_R14_0_Pos                                  16                                                        /*!< LCD PAL149: R14_0 Position          */
-#define LCD_PAL149_R14_0_Msk                                  (0x1fUL << LCD_PAL149_R14_0_Pos)                          /*!< LCD PAL149: R14_0 Mask              */
-#define LCD_PAL149_G14_0_Pos                                  21                                                        /*!< LCD PAL149: G14_0 Position          */
-#define LCD_PAL149_G14_0_Msk                                  (0x1fUL << LCD_PAL149_G14_0_Pos)                          /*!< LCD PAL149: G14_0 Mask              */
-#define LCD_PAL149_B14_0_Pos                                  26                                                        /*!< LCD PAL149: B14_0 Position          */
-#define LCD_PAL149_B14_0_Msk                                  (0x1fUL << LCD_PAL149_B14_0_Pos)                          /*!< LCD PAL149: B14_0 Mask              */
-#define LCD_PAL149_I1_Pos                                     31                                                        /*!< LCD PAL149: I1 Position             */
-#define LCD_PAL149_I1_Msk                                     (0x01UL << LCD_PAL149_I1_Pos)                             /*!< LCD PAL149: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL150  -------------------------------------------
-#define LCD_PAL150_R04_0_Pos                                  0                                                         /*!< LCD PAL150: R04_0 Position          */
-#define LCD_PAL150_R04_0_Msk                                  (0x1fUL << LCD_PAL150_R04_0_Pos)                          /*!< LCD PAL150: R04_0 Mask              */
-#define LCD_PAL150_G04_0_Pos                                  5                                                         /*!< LCD PAL150: G04_0 Position          */
-#define LCD_PAL150_G04_0_Msk                                  (0x1fUL << LCD_PAL150_G04_0_Pos)                          /*!< LCD PAL150: G04_0 Mask              */
-#define LCD_PAL150_B04_0_Pos                                  10                                                        /*!< LCD PAL150: B04_0 Position          */
-#define LCD_PAL150_B04_0_Msk                                  (0x1fUL << LCD_PAL150_B04_0_Pos)                          /*!< LCD PAL150: B04_0 Mask              */
-#define LCD_PAL150_I0_Pos                                     15                                                        /*!< LCD PAL150: I0 Position             */
-#define LCD_PAL150_I0_Msk                                     (0x01UL << LCD_PAL150_I0_Pos)                             /*!< LCD PAL150: I0 Mask                 */
-#define LCD_PAL150_R14_0_Pos                                  16                                                        /*!< LCD PAL150: R14_0 Position          */
-#define LCD_PAL150_R14_0_Msk                                  (0x1fUL << LCD_PAL150_R14_0_Pos)                          /*!< LCD PAL150: R14_0 Mask              */
-#define LCD_PAL150_G14_0_Pos                                  21                                                        /*!< LCD PAL150: G14_0 Position          */
-#define LCD_PAL150_G14_0_Msk                                  (0x1fUL << LCD_PAL150_G14_0_Pos)                          /*!< LCD PAL150: G14_0 Mask              */
-#define LCD_PAL150_B14_0_Pos                                  26                                                        /*!< LCD PAL150: B14_0 Position          */
-#define LCD_PAL150_B14_0_Msk                                  (0x1fUL << LCD_PAL150_B14_0_Pos)                          /*!< LCD PAL150: B14_0 Mask              */
-#define LCD_PAL150_I1_Pos                                     31                                                        /*!< LCD PAL150: I1 Position             */
-#define LCD_PAL150_I1_Msk                                     (0x01UL << LCD_PAL150_I1_Pos)                             /*!< LCD PAL150: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL151  -------------------------------------------
-#define LCD_PAL151_R04_0_Pos                                  0                                                         /*!< LCD PAL151: R04_0 Position          */
-#define LCD_PAL151_R04_0_Msk                                  (0x1fUL << LCD_PAL151_R04_0_Pos)                          /*!< LCD PAL151: R04_0 Mask              */
-#define LCD_PAL151_G04_0_Pos                                  5                                                         /*!< LCD PAL151: G04_0 Position          */
-#define LCD_PAL151_G04_0_Msk                                  (0x1fUL << LCD_PAL151_G04_0_Pos)                          /*!< LCD PAL151: G04_0 Mask              */
-#define LCD_PAL151_B04_0_Pos                                  10                                                        /*!< LCD PAL151: B04_0 Position          */
-#define LCD_PAL151_B04_0_Msk                                  (0x1fUL << LCD_PAL151_B04_0_Pos)                          /*!< LCD PAL151: B04_0 Mask              */
-#define LCD_PAL151_I0_Pos                                     15                                                        /*!< LCD PAL151: I0 Position             */
-#define LCD_PAL151_I0_Msk                                     (0x01UL << LCD_PAL151_I0_Pos)                             /*!< LCD PAL151: I0 Mask                 */
-#define LCD_PAL151_R14_0_Pos                                  16                                                        /*!< LCD PAL151: R14_0 Position          */
-#define LCD_PAL151_R14_0_Msk                                  (0x1fUL << LCD_PAL151_R14_0_Pos)                          /*!< LCD PAL151: R14_0 Mask              */
-#define LCD_PAL151_G14_0_Pos                                  21                                                        /*!< LCD PAL151: G14_0 Position          */
-#define LCD_PAL151_G14_0_Msk                                  (0x1fUL << LCD_PAL151_G14_0_Pos)                          /*!< LCD PAL151: G14_0 Mask              */
-#define LCD_PAL151_B14_0_Pos                                  26                                                        /*!< LCD PAL151: B14_0 Position          */
-#define LCD_PAL151_B14_0_Msk                                  (0x1fUL << LCD_PAL151_B14_0_Pos)                          /*!< LCD PAL151: B14_0 Mask              */
-#define LCD_PAL151_I1_Pos                                     31                                                        /*!< LCD PAL151: I1 Position             */
-#define LCD_PAL151_I1_Msk                                     (0x01UL << LCD_PAL151_I1_Pos)                             /*!< LCD PAL151: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL152  -------------------------------------------
-#define LCD_PAL152_R04_0_Pos                                  0                                                         /*!< LCD PAL152: R04_0 Position          */
-#define LCD_PAL152_R04_0_Msk                                  (0x1fUL << LCD_PAL152_R04_0_Pos)                          /*!< LCD PAL152: R04_0 Mask              */
-#define LCD_PAL152_G04_0_Pos                                  5                                                         /*!< LCD PAL152: G04_0 Position          */
-#define LCD_PAL152_G04_0_Msk                                  (0x1fUL << LCD_PAL152_G04_0_Pos)                          /*!< LCD PAL152: G04_0 Mask              */
-#define LCD_PAL152_B04_0_Pos                                  10                                                        /*!< LCD PAL152: B04_0 Position          */
-#define LCD_PAL152_B04_0_Msk                                  (0x1fUL << LCD_PAL152_B04_0_Pos)                          /*!< LCD PAL152: B04_0 Mask              */
-#define LCD_PAL152_I0_Pos                                     15                                                        /*!< LCD PAL152: I0 Position             */
-#define LCD_PAL152_I0_Msk                                     (0x01UL << LCD_PAL152_I0_Pos)                             /*!< LCD PAL152: I0 Mask                 */
-#define LCD_PAL152_R14_0_Pos                                  16                                                        /*!< LCD PAL152: R14_0 Position          */
-#define LCD_PAL152_R14_0_Msk                                  (0x1fUL << LCD_PAL152_R14_0_Pos)                          /*!< LCD PAL152: R14_0 Mask              */
-#define LCD_PAL152_G14_0_Pos                                  21                                                        /*!< LCD PAL152: G14_0 Position          */
-#define LCD_PAL152_G14_0_Msk                                  (0x1fUL << LCD_PAL152_G14_0_Pos)                          /*!< LCD PAL152: G14_0 Mask              */
-#define LCD_PAL152_B14_0_Pos                                  26                                                        /*!< LCD PAL152: B14_0 Position          */
-#define LCD_PAL152_B14_0_Msk                                  (0x1fUL << LCD_PAL152_B14_0_Pos)                          /*!< LCD PAL152: B14_0 Mask              */
-#define LCD_PAL152_I1_Pos                                     31                                                        /*!< LCD PAL152: I1 Position             */
-#define LCD_PAL152_I1_Msk                                     (0x01UL << LCD_PAL152_I1_Pos)                             /*!< LCD PAL152: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL153  -------------------------------------------
-#define LCD_PAL153_R04_0_Pos                                  0                                                         /*!< LCD PAL153: R04_0 Position          */
-#define LCD_PAL153_R04_0_Msk                                  (0x1fUL << LCD_PAL153_R04_0_Pos)                          /*!< LCD PAL153: R04_0 Mask              */
-#define LCD_PAL153_G04_0_Pos                                  5                                                         /*!< LCD PAL153: G04_0 Position          */
-#define LCD_PAL153_G04_0_Msk                                  (0x1fUL << LCD_PAL153_G04_0_Pos)                          /*!< LCD PAL153: G04_0 Mask              */
-#define LCD_PAL153_B04_0_Pos                                  10                                                        /*!< LCD PAL153: B04_0 Position          */
-#define LCD_PAL153_B04_0_Msk                                  (0x1fUL << LCD_PAL153_B04_0_Pos)                          /*!< LCD PAL153: B04_0 Mask              */
-#define LCD_PAL153_I0_Pos                                     15                                                        /*!< LCD PAL153: I0 Position             */
-#define LCD_PAL153_I0_Msk                                     (0x01UL << LCD_PAL153_I0_Pos)                             /*!< LCD PAL153: I0 Mask                 */
-#define LCD_PAL153_R14_0_Pos                                  16                                                        /*!< LCD PAL153: R14_0 Position          */
-#define LCD_PAL153_R14_0_Msk                                  (0x1fUL << LCD_PAL153_R14_0_Pos)                          /*!< LCD PAL153: R14_0 Mask              */
-#define LCD_PAL153_G14_0_Pos                                  21                                                        /*!< LCD PAL153: G14_0 Position          */
-#define LCD_PAL153_G14_0_Msk                                  (0x1fUL << LCD_PAL153_G14_0_Pos)                          /*!< LCD PAL153: G14_0 Mask              */
-#define LCD_PAL153_B14_0_Pos                                  26                                                        /*!< LCD PAL153: B14_0 Position          */
-#define LCD_PAL153_B14_0_Msk                                  (0x1fUL << LCD_PAL153_B14_0_Pos)                          /*!< LCD PAL153: B14_0 Mask              */
-#define LCD_PAL153_I1_Pos                                     31                                                        /*!< LCD PAL153: I1 Position             */
-#define LCD_PAL153_I1_Msk                                     (0x01UL << LCD_PAL153_I1_Pos)                             /*!< LCD PAL153: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL154  -------------------------------------------
-#define LCD_PAL154_R04_0_Pos                                  0                                                         /*!< LCD PAL154: R04_0 Position          */
-#define LCD_PAL154_R04_0_Msk                                  (0x1fUL << LCD_PAL154_R04_0_Pos)                          /*!< LCD PAL154: R04_0 Mask              */
-#define LCD_PAL154_G04_0_Pos                                  5                                                         /*!< LCD PAL154: G04_0 Position          */
-#define LCD_PAL154_G04_0_Msk                                  (0x1fUL << LCD_PAL154_G04_0_Pos)                          /*!< LCD PAL154: G04_0 Mask              */
-#define LCD_PAL154_B04_0_Pos                                  10                                                        /*!< LCD PAL154: B04_0 Position          */
-#define LCD_PAL154_B04_0_Msk                                  (0x1fUL << LCD_PAL154_B04_0_Pos)                          /*!< LCD PAL154: B04_0 Mask              */
-#define LCD_PAL154_I0_Pos                                     15                                                        /*!< LCD PAL154: I0 Position             */
-#define LCD_PAL154_I0_Msk                                     (0x01UL << LCD_PAL154_I0_Pos)                             /*!< LCD PAL154: I0 Mask                 */
-#define LCD_PAL154_R14_0_Pos                                  16                                                        /*!< LCD PAL154: R14_0 Position          */
-#define LCD_PAL154_R14_0_Msk                                  (0x1fUL << LCD_PAL154_R14_0_Pos)                          /*!< LCD PAL154: R14_0 Mask              */
-#define LCD_PAL154_G14_0_Pos                                  21                                                        /*!< LCD PAL154: G14_0 Position          */
-#define LCD_PAL154_G14_0_Msk                                  (0x1fUL << LCD_PAL154_G14_0_Pos)                          /*!< LCD PAL154: G14_0 Mask              */
-#define LCD_PAL154_B14_0_Pos                                  26                                                        /*!< LCD PAL154: B14_0 Position          */
-#define LCD_PAL154_B14_0_Msk                                  (0x1fUL << LCD_PAL154_B14_0_Pos)                          /*!< LCD PAL154: B14_0 Mask              */
-#define LCD_PAL154_I1_Pos                                     31                                                        /*!< LCD PAL154: I1 Position             */
-#define LCD_PAL154_I1_Msk                                     (0x01UL << LCD_PAL154_I1_Pos)                             /*!< LCD PAL154: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL155  -------------------------------------------
-#define LCD_PAL155_R04_0_Pos                                  0                                                         /*!< LCD PAL155: R04_0 Position          */
-#define LCD_PAL155_R04_0_Msk                                  (0x1fUL << LCD_PAL155_R04_0_Pos)                          /*!< LCD PAL155: R04_0 Mask              */
-#define LCD_PAL155_G04_0_Pos                                  5                                                         /*!< LCD PAL155: G04_0 Position          */
-#define LCD_PAL155_G04_0_Msk                                  (0x1fUL << LCD_PAL155_G04_0_Pos)                          /*!< LCD PAL155: G04_0 Mask              */
-#define LCD_PAL155_B04_0_Pos                                  10                                                        /*!< LCD PAL155: B04_0 Position          */
-#define LCD_PAL155_B04_0_Msk                                  (0x1fUL << LCD_PAL155_B04_0_Pos)                          /*!< LCD PAL155: B04_0 Mask              */
-#define LCD_PAL155_I0_Pos                                     15                                                        /*!< LCD PAL155: I0 Position             */
-#define LCD_PAL155_I0_Msk                                     (0x01UL << LCD_PAL155_I0_Pos)                             /*!< LCD PAL155: I0 Mask                 */
-#define LCD_PAL155_R14_0_Pos                                  16                                                        /*!< LCD PAL155: R14_0 Position          */
-#define LCD_PAL155_R14_0_Msk                                  (0x1fUL << LCD_PAL155_R14_0_Pos)                          /*!< LCD PAL155: R14_0 Mask              */
-#define LCD_PAL155_G14_0_Pos                                  21                                                        /*!< LCD PAL155: G14_0 Position          */
-#define LCD_PAL155_G14_0_Msk                                  (0x1fUL << LCD_PAL155_G14_0_Pos)                          /*!< LCD PAL155: G14_0 Mask              */
-#define LCD_PAL155_B14_0_Pos                                  26                                                        /*!< LCD PAL155: B14_0 Position          */
-#define LCD_PAL155_B14_0_Msk                                  (0x1fUL << LCD_PAL155_B14_0_Pos)                          /*!< LCD PAL155: B14_0 Mask              */
-#define LCD_PAL155_I1_Pos                                     31                                                        /*!< LCD PAL155: I1 Position             */
-#define LCD_PAL155_I1_Msk                                     (0x01UL << LCD_PAL155_I1_Pos)                             /*!< LCD PAL155: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL156  -------------------------------------------
-#define LCD_PAL156_R04_0_Pos                                  0                                                         /*!< LCD PAL156: R04_0 Position          */
-#define LCD_PAL156_R04_0_Msk                                  (0x1fUL << LCD_PAL156_R04_0_Pos)                          /*!< LCD PAL156: R04_0 Mask              */
-#define LCD_PAL156_G04_0_Pos                                  5                                                         /*!< LCD PAL156: G04_0 Position          */
-#define LCD_PAL156_G04_0_Msk                                  (0x1fUL << LCD_PAL156_G04_0_Pos)                          /*!< LCD PAL156: G04_0 Mask              */
-#define LCD_PAL156_B04_0_Pos                                  10                                                        /*!< LCD PAL156: B04_0 Position          */
-#define LCD_PAL156_B04_0_Msk                                  (0x1fUL << LCD_PAL156_B04_0_Pos)                          /*!< LCD PAL156: B04_0 Mask              */
-#define LCD_PAL156_I0_Pos                                     15                                                        /*!< LCD PAL156: I0 Position             */
-#define LCD_PAL156_I0_Msk                                     (0x01UL << LCD_PAL156_I0_Pos)                             /*!< LCD PAL156: I0 Mask                 */
-#define LCD_PAL156_R14_0_Pos                                  16                                                        /*!< LCD PAL156: R14_0 Position          */
-#define LCD_PAL156_R14_0_Msk                                  (0x1fUL << LCD_PAL156_R14_0_Pos)                          /*!< LCD PAL156: R14_0 Mask              */
-#define LCD_PAL156_G14_0_Pos                                  21                                                        /*!< LCD PAL156: G14_0 Position          */
-#define LCD_PAL156_G14_0_Msk                                  (0x1fUL << LCD_PAL156_G14_0_Pos)                          /*!< LCD PAL156: G14_0 Mask              */
-#define LCD_PAL156_B14_0_Pos                                  26                                                        /*!< LCD PAL156: B14_0 Position          */
-#define LCD_PAL156_B14_0_Msk                                  (0x1fUL << LCD_PAL156_B14_0_Pos)                          /*!< LCD PAL156: B14_0 Mask              */
-#define LCD_PAL156_I1_Pos                                     31                                                        /*!< LCD PAL156: I1 Position             */
-#define LCD_PAL156_I1_Msk                                     (0x01UL << LCD_PAL156_I1_Pos)                             /*!< LCD PAL156: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL157  -------------------------------------------
-#define LCD_PAL157_R04_0_Pos                                  0                                                         /*!< LCD PAL157: R04_0 Position          */
-#define LCD_PAL157_R04_0_Msk                                  (0x1fUL << LCD_PAL157_R04_0_Pos)                          /*!< LCD PAL157: R04_0 Mask              */
-#define LCD_PAL157_G04_0_Pos                                  5                                                         /*!< LCD PAL157: G04_0 Position          */
-#define LCD_PAL157_G04_0_Msk                                  (0x1fUL << LCD_PAL157_G04_0_Pos)                          /*!< LCD PAL157: G04_0 Mask              */
-#define LCD_PAL157_B04_0_Pos                                  10                                                        /*!< LCD PAL157: B04_0 Position          */
-#define LCD_PAL157_B04_0_Msk                                  (0x1fUL << LCD_PAL157_B04_0_Pos)                          /*!< LCD PAL157: B04_0 Mask              */
-#define LCD_PAL157_I0_Pos                                     15                                                        /*!< LCD PAL157: I0 Position             */
-#define LCD_PAL157_I0_Msk                                     (0x01UL << LCD_PAL157_I0_Pos)                             /*!< LCD PAL157: I0 Mask                 */
-#define LCD_PAL157_R14_0_Pos                                  16                                                        /*!< LCD PAL157: R14_0 Position          */
-#define LCD_PAL157_R14_0_Msk                                  (0x1fUL << LCD_PAL157_R14_0_Pos)                          /*!< LCD PAL157: R14_0 Mask              */
-#define LCD_PAL157_G14_0_Pos                                  21                                                        /*!< LCD PAL157: G14_0 Position          */
-#define LCD_PAL157_G14_0_Msk                                  (0x1fUL << LCD_PAL157_G14_0_Pos)                          /*!< LCD PAL157: G14_0 Mask              */
-#define LCD_PAL157_B14_0_Pos                                  26                                                        /*!< LCD PAL157: B14_0 Position          */
-#define LCD_PAL157_B14_0_Msk                                  (0x1fUL << LCD_PAL157_B14_0_Pos)                          /*!< LCD PAL157: B14_0 Mask              */
-#define LCD_PAL157_I1_Pos                                     31                                                        /*!< LCD PAL157: I1 Position             */
-#define LCD_PAL157_I1_Msk                                     (0x01UL << LCD_PAL157_I1_Pos)                             /*!< LCD PAL157: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL158  -------------------------------------------
-#define LCD_PAL158_R04_0_Pos                                  0                                                         /*!< LCD PAL158: R04_0 Position          */
-#define LCD_PAL158_R04_0_Msk                                  (0x1fUL << LCD_PAL158_R04_0_Pos)                          /*!< LCD PAL158: R04_0 Mask              */
-#define LCD_PAL158_G04_0_Pos                                  5                                                         /*!< LCD PAL158: G04_0 Position          */
-#define LCD_PAL158_G04_0_Msk                                  (0x1fUL << LCD_PAL158_G04_0_Pos)                          /*!< LCD PAL158: G04_0 Mask              */
-#define LCD_PAL158_B04_0_Pos                                  10                                                        /*!< LCD PAL158: B04_0 Position          */
-#define LCD_PAL158_B04_0_Msk                                  (0x1fUL << LCD_PAL158_B04_0_Pos)                          /*!< LCD PAL158: B04_0 Mask              */
-#define LCD_PAL158_I0_Pos                                     15                                                        /*!< LCD PAL158: I0 Position             */
-#define LCD_PAL158_I0_Msk                                     (0x01UL << LCD_PAL158_I0_Pos)                             /*!< LCD PAL158: I0 Mask                 */
-#define LCD_PAL158_R14_0_Pos                                  16                                                        /*!< LCD PAL158: R14_0 Position          */
-#define LCD_PAL158_R14_0_Msk                                  (0x1fUL << LCD_PAL158_R14_0_Pos)                          /*!< LCD PAL158: R14_0 Mask              */
-#define LCD_PAL158_G14_0_Pos                                  21                                                        /*!< LCD PAL158: G14_0 Position          */
-#define LCD_PAL158_G14_0_Msk                                  (0x1fUL << LCD_PAL158_G14_0_Pos)                          /*!< LCD PAL158: G14_0 Mask              */
-#define LCD_PAL158_B14_0_Pos                                  26                                                        /*!< LCD PAL158: B14_0 Position          */
-#define LCD_PAL158_B14_0_Msk                                  (0x1fUL << LCD_PAL158_B14_0_Pos)                          /*!< LCD PAL158: B14_0 Mask              */
-#define LCD_PAL158_I1_Pos                                     31                                                        /*!< LCD PAL158: I1 Position             */
-#define LCD_PAL158_I1_Msk                                     (0x01UL << LCD_PAL158_I1_Pos)                             /*!< LCD PAL158: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL159  -------------------------------------------
-#define LCD_PAL159_R04_0_Pos                                  0                                                         /*!< LCD PAL159: R04_0 Position          */
-#define LCD_PAL159_R04_0_Msk                                  (0x1fUL << LCD_PAL159_R04_0_Pos)                          /*!< LCD PAL159: R04_0 Mask              */
-#define LCD_PAL159_G04_0_Pos                                  5                                                         /*!< LCD PAL159: G04_0 Position          */
-#define LCD_PAL159_G04_0_Msk                                  (0x1fUL << LCD_PAL159_G04_0_Pos)                          /*!< LCD PAL159: G04_0 Mask              */
-#define LCD_PAL159_B04_0_Pos                                  10                                                        /*!< LCD PAL159: B04_0 Position          */
-#define LCD_PAL159_B04_0_Msk                                  (0x1fUL << LCD_PAL159_B04_0_Pos)                          /*!< LCD PAL159: B04_0 Mask              */
-#define LCD_PAL159_I0_Pos                                     15                                                        /*!< LCD PAL159: I0 Position             */
-#define LCD_PAL159_I0_Msk                                     (0x01UL << LCD_PAL159_I0_Pos)                             /*!< LCD PAL159: I0 Mask                 */
-#define LCD_PAL159_R14_0_Pos                                  16                                                        /*!< LCD PAL159: R14_0 Position          */
-#define LCD_PAL159_R14_0_Msk                                  (0x1fUL << LCD_PAL159_R14_0_Pos)                          /*!< LCD PAL159: R14_0 Mask              */
-#define LCD_PAL159_G14_0_Pos                                  21                                                        /*!< LCD PAL159: G14_0 Position          */
-#define LCD_PAL159_G14_0_Msk                                  (0x1fUL << LCD_PAL159_G14_0_Pos)                          /*!< LCD PAL159: G14_0 Mask              */
-#define LCD_PAL159_B14_0_Pos                                  26                                                        /*!< LCD PAL159: B14_0 Position          */
-#define LCD_PAL159_B14_0_Msk                                  (0x1fUL << LCD_PAL159_B14_0_Pos)                          /*!< LCD PAL159: B14_0 Mask              */
-#define LCD_PAL159_I1_Pos                                     31                                                        /*!< LCD PAL159: I1 Position             */
-#define LCD_PAL159_I1_Msk                                     (0x01UL << LCD_PAL159_I1_Pos)                             /*!< LCD PAL159: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL160  -------------------------------------------
-#define LCD_PAL160_R04_0_Pos                                  0                                                         /*!< LCD PAL160: R04_0 Position          */
-#define LCD_PAL160_R04_0_Msk                                  (0x1fUL << LCD_PAL160_R04_0_Pos)                          /*!< LCD PAL160: R04_0 Mask              */
-#define LCD_PAL160_G04_0_Pos                                  5                                                         /*!< LCD PAL160: G04_0 Position          */
-#define LCD_PAL160_G04_0_Msk                                  (0x1fUL << LCD_PAL160_G04_0_Pos)                          /*!< LCD PAL160: G04_0 Mask              */
-#define LCD_PAL160_B04_0_Pos                                  10                                                        /*!< LCD PAL160: B04_0 Position          */
-#define LCD_PAL160_B04_0_Msk                                  (0x1fUL << LCD_PAL160_B04_0_Pos)                          /*!< LCD PAL160: B04_0 Mask              */
-#define LCD_PAL160_I0_Pos                                     15                                                        /*!< LCD PAL160: I0 Position             */
-#define LCD_PAL160_I0_Msk                                     (0x01UL << LCD_PAL160_I0_Pos)                             /*!< LCD PAL160: I0 Mask                 */
-#define LCD_PAL160_R14_0_Pos                                  16                                                        /*!< LCD PAL160: R14_0 Position          */
-#define LCD_PAL160_R14_0_Msk                                  (0x1fUL << LCD_PAL160_R14_0_Pos)                          /*!< LCD PAL160: R14_0 Mask              */
-#define LCD_PAL160_G14_0_Pos                                  21                                                        /*!< LCD PAL160: G14_0 Position          */
-#define LCD_PAL160_G14_0_Msk                                  (0x1fUL << LCD_PAL160_G14_0_Pos)                          /*!< LCD PAL160: G14_0 Mask              */
-#define LCD_PAL160_B14_0_Pos                                  26                                                        /*!< LCD PAL160: B14_0 Position          */
-#define LCD_PAL160_B14_0_Msk                                  (0x1fUL << LCD_PAL160_B14_0_Pos)                          /*!< LCD PAL160: B14_0 Mask              */
-#define LCD_PAL160_I1_Pos                                     31                                                        /*!< LCD PAL160: I1 Position             */
-#define LCD_PAL160_I1_Msk                                     (0x01UL << LCD_PAL160_I1_Pos)                             /*!< LCD PAL160: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL161  -------------------------------------------
-#define LCD_PAL161_R04_0_Pos                                  0                                                         /*!< LCD PAL161: R04_0 Position          */
-#define LCD_PAL161_R04_0_Msk                                  (0x1fUL << LCD_PAL161_R04_0_Pos)                          /*!< LCD PAL161: R04_0 Mask              */
-#define LCD_PAL161_G04_0_Pos                                  5                                                         /*!< LCD PAL161: G04_0 Position          */
-#define LCD_PAL161_G04_0_Msk                                  (0x1fUL << LCD_PAL161_G04_0_Pos)                          /*!< LCD PAL161: G04_0 Mask              */
-#define LCD_PAL161_B04_0_Pos                                  10                                                        /*!< LCD PAL161: B04_0 Position          */
-#define LCD_PAL161_B04_0_Msk                                  (0x1fUL << LCD_PAL161_B04_0_Pos)                          /*!< LCD PAL161: B04_0 Mask              */
-#define LCD_PAL161_I0_Pos                                     15                                                        /*!< LCD PAL161: I0 Position             */
-#define LCD_PAL161_I0_Msk                                     (0x01UL << LCD_PAL161_I0_Pos)                             /*!< LCD PAL161: I0 Mask                 */
-#define LCD_PAL161_R14_0_Pos                                  16                                                        /*!< LCD PAL161: R14_0 Position          */
-#define LCD_PAL161_R14_0_Msk                                  (0x1fUL << LCD_PAL161_R14_0_Pos)                          /*!< LCD PAL161: R14_0 Mask              */
-#define LCD_PAL161_G14_0_Pos                                  21                                                        /*!< LCD PAL161: G14_0 Position          */
-#define LCD_PAL161_G14_0_Msk                                  (0x1fUL << LCD_PAL161_G14_0_Pos)                          /*!< LCD PAL161: G14_0 Mask              */
-#define LCD_PAL161_B14_0_Pos                                  26                                                        /*!< LCD PAL161: B14_0 Position          */
-#define LCD_PAL161_B14_0_Msk                                  (0x1fUL << LCD_PAL161_B14_0_Pos)                          /*!< LCD PAL161: B14_0 Mask              */
-#define LCD_PAL161_I1_Pos                                     31                                                        /*!< LCD PAL161: I1 Position             */
-#define LCD_PAL161_I1_Msk                                     (0x01UL << LCD_PAL161_I1_Pos)                             /*!< LCD PAL161: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL162  -------------------------------------------
-#define LCD_PAL162_R04_0_Pos                                  0                                                         /*!< LCD PAL162: R04_0 Position          */
-#define LCD_PAL162_R04_0_Msk                                  (0x1fUL << LCD_PAL162_R04_0_Pos)                          /*!< LCD PAL162: R04_0 Mask              */
-#define LCD_PAL162_G04_0_Pos                                  5                                                         /*!< LCD PAL162: G04_0 Position          */
-#define LCD_PAL162_G04_0_Msk                                  (0x1fUL << LCD_PAL162_G04_0_Pos)                          /*!< LCD PAL162: G04_0 Mask              */
-#define LCD_PAL162_B04_0_Pos                                  10                                                        /*!< LCD PAL162: B04_0 Position          */
-#define LCD_PAL162_B04_0_Msk                                  (0x1fUL << LCD_PAL162_B04_0_Pos)                          /*!< LCD PAL162: B04_0 Mask              */
-#define LCD_PAL162_I0_Pos                                     15                                                        /*!< LCD PAL162: I0 Position             */
-#define LCD_PAL162_I0_Msk                                     (0x01UL << LCD_PAL162_I0_Pos)                             /*!< LCD PAL162: I0 Mask                 */
-#define LCD_PAL162_R14_0_Pos                                  16                                                        /*!< LCD PAL162: R14_0 Position          */
-#define LCD_PAL162_R14_0_Msk                                  (0x1fUL << LCD_PAL162_R14_0_Pos)                          /*!< LCD PAL162: R14_0 Mask              */
-#define LCD_PAL162_G14_0_Pos                                  21                                                        /*!< LCD PAL162: G14_0 Position          */
-#define LCD_PAL162_G14_0_Msk                                  (0x1fUL << LCD_PAL162_G14_0_Pos)                          /*!< LCD PAL162: G14_0 Mask              */
-#define LCD_PAL162_B14_0_Pos                                  26                                                        /*!< LCD PAL162: B14_0 Position          */
-#define LCD_PAL162_B14_0_Msk                                  (0x1fUL << LCD_PAL162_B14_0_Pos)                          /*!< LCD PAL162: B14_0 Mask              */
-#define LCD_PAL162_I1_Pos                                     31                                                        /*!< LCD PAL162: I1 Position             */
-#define LCD_PAL162_I1_Msk                                     (0x01UL << LCD_PAL162_I1_Pos)                             /*!< LCD PAL162: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL163  -------------------------------------------
-#define LCD_PAL163_R04_0_Pos                                  0                                                         /*!< LCD PAL163: R04_0 Position          */
-#define LCD_PAL163_R04_0_Msk                                  (0x1fUL << LCD_PAL163_R04_0_Pos)                          /*!< LCD PAL163: R04_0 Mask              */
-#define LCD_PAL163_G04_0_Pos                                  5                                                         /*!< LCD PAL163: G04_0 Position          */
-#define LCD_PAL163_G04_0_Msk                                  (0x1fUL << LCD_PAL163_G04_0_Pos)                          /*!< LCD PAL163: G04_0 Mask              */
-#define LCD_PAL163_B04_0_Pos                                  10                                                        /*!< LCD PAL163: B04_0 Position          */
-#define LCD_PAL163_B04_0_Msk                                  (0x1fUL << LCD_PAL163_B04_0_Pos)                          /*!< LCD PAL163: B04_0 Mask              */
-#define LCD_PAL163_I0_Pos                                     15                                                        /*!< LCD PAL163: I0 Position             */
-#define LCD_PAL163_I0_Msk                                     (0x01UL << LCD_PAL163_I0_Pos)                             /*!< LCD PAL163: I0 Mask                 */
-#define LCD_PAL163_R14_0_Pos                                  16                                                        /*!< LCD PAL163: R14_0 Position          */
-#define LCD_PAL163_R14_0_Msk                                  (0x1fUL << LCD_PAL163_R14_0_Pos)                          /*!< LCD PAL163: R14_0 Mask              */
-#define LCD_PAL163_G14_0_Pos                                  21                                                        /*!< LCD PAL163: G14_0 Position          */
-#define LCD_PAL163_G14_0_Msk                                  (0x1fUL << LCD_PAL163_G14_0_Pos)                          /*!< LCD PAL163: G14_0 Mask              */
-#define LCD_PAL163_B14_0_Pos                                  26                                                        /*!< LCD PAL163: B14_0 Position          */
-#define LCD_PAL163_B14_0_Msk                                  (0x1fUL << LCD_PAL163_B14_0_Pos)                          /*!< LCD PAL163: B14_0 Mask              */
-#define LCD_PAL163_I1_Pos                                     31                                                        /*!< LCD PAL163: I1 Position             */
-#define LCD_PAL163_I1_Msk                                     (0x01UL << LCD_PAL163_I1_Pos)                             /*!< LCD PAL163: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL164  -------------------------------------------
-#define LCD_PAL164_R04_0_Pos                                  0                                                         /*!< LCD PAL164: R04_0 Position          */
-#define LCD_PAL164_R04_0_Msk                                  (0x1fUL << LCD_PAL164_R04_0_Pos)                          /*!< LCD PAL164: R04_0 Mask              */
-#define LCD_PAL164_G04_0_Pos                                  5                                                         /*!< LCD PAL164: G04_0 Position          */
-#define LCD_PAL164_G04_0_Msk                                  (0x1fUL << LCD_PAL164_G04_0_Pos)                          /*!< LCD PAL164: G04_0 Mask              */
-#define LCD_PAL164_B04_0_Pos                                  10                                                        /*!< LCD PAL164: B04_0 Position          */
-#define LCD_PAL164_B04_0_Msk                                  (0x1fUL << LCD_PAL164_B04_0_Pos)                          /*!< LCD PAL164: B04_0 Mask              */
-#define LCD_PAL164_I0_Pos                                     15                                                        /*!< LCD PAL164: I0 Position             */
-#define LCD_PAL164_I0_Msk                                     (0x01UL << LCD_PAL164_I0_Pos)                             /*!< LCD PAL164: I0 Mask                 */
-#define LCD_PAL164_R14_0_Pos                                  16                                                        /*!< LCD PAL164: R14_0 Position          */
-#define LCD_PAL164_R14_0_Msk                                  (0x1fUL << LCD_PAL164_R14_0_Pos)                          /*!< LCD PAL164: R14_0 Mask              */
-#define LCD_PAL164_G14_0_Pos                                  21                                                        /*!< LCD PAL164: G14_0 Position          */
-#define LCD_PAL164_G14_0_Msk                                  (0x1fUL << LCD_PAL164_G14_0_Pos)                          /*!< LCD PAL164: G14_0 Mask              */
-#define LCD_PAL164_B14_0_Pos                                  26                                                        /*!< LCD PAL164: B14_0 Position          */
-#define LCD_PAL164_B14_0_Msk                                  (0x1fUL << LCD_PAL164_B14_0_Pos)                          /*!< LCD PAL164: B14_0 Mask              */
-#define LCD_PAL164_I1_Pos                                     31                                                        /*!< LCD PAL164: I1 Position             */
-#define LCD_PAL164_I1_Msk                                     (0x01UL << LCD_PAL164_I1_Pos)                             /*!< LCD PAL164: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL165  -------------------------------------------
-#define LCD_PAL165_R04_0_Pos                                  0                                                         /*!< LCD PAL165: R04_0 Position          */
-#define LCD_PAL165_R04_0_Msk                                  (0x1fUL << LCD_PAL165_R04_0_Pos)                          /*!< LCD PAL165: R04_0 Mask              */
-#define LCD_PAL165_G04_0_Pos                                  5                                                         /*!< LCD PAL165: G04_0 Position          */
-#define LCD_PAL165_G04_0_Msk                                  (0x1fUL << LCD_PAL165_G04_0_Pos)                          /*!< LCD PAL165: G04_0 Mask              */
-#define LCD_PAL165_B04_0_Pos                                  10                                                        /*!< LCD PAL165: B04_0 Position          */
-#define LCD_PAL165_B04_0_Msk                                  (0x1fUL << LCD_PAL165_B04_0_Pos)                          /*!< LCD PAL165: B04_0 Mask              */
-#define LCD_PAL165_I0_Pos                                     15                                                        /*!< LCD PAL165: I0 Position             */
-#define LCD_PAL165_I0_Msk                                     (0x01UL << LCD_PAL165_I0_Pos)                             /*!< LCD PAL165: I0 Mask                 */
-#define LCD_PAL165_R14_0_Pos                                  16                                                        /*!< LCD PAL165: R14_0 Position          */
-#define LCD_PAL165_R14_0_Msk                                  (0x1fUL << LCD_PAL165_R14_0_Pos)                          /*!< LCD PAL165: R14_0 Mask              */
-#define LCD_PAL165_G14_0_Pos                                  21                                                        /*!< LCD PAL165: G14_0 Position          */
-#define LCD_PAL165_G14_0_Msk                                  (0x1fUL << LCD_PAL165_G14_0_Pos)                          /*!< LCD PAL165: G14_0 Mask              */
-#define LCD_PAL165_B14_0_Pos                                  26                                                        /*!< LCD PAL165: B14_0 Position          */
-#define LCD_PAL165_B14_0_Msk                                  (0x1fUL << LCD_PAL165_B14_0_Pos)                          /*!< LCD PAL165: B14_0 Mask              */
-#define LCD_PAL165_I1_Pos                                     31                                                        /*!< LCD PAL165: I1 Position             */
-#define LCD_PAL165_I1_Msk                                     (0x01UL << LCD_PAL165_I1_Pos)                             /*!< LCD PAL165: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL166  -------------------------------------------
-#define LCD_PAL166_R04_0_Pos                                  0                                                         /*!< LCD PAL166: R04_0 Position          */
-#define LCD_PAL166_R04_0_Msk                                  (0x1fUL << LCD_PAL166_R04_0_Pos)                          /*!< LCD PAL166: R04_0 Mask              */
-#define LCD_PAL166_G04_0_Pos                                  5                                                         /*!< LCD PAL166: G04_0 Position          */
-#define LCD_PAL166_G04_0_Msk                                  (0x1fUL << LCD_PAL166_G04_0_Pos)                          /*!< LCD PAL166: G04_0 Mask              */
-#define LCD_PAL166_B04_0_Pos                                  10                                                        /*!< LCD PAL166: B04_0 Position          */
-#define LCD_PAL166_B04_0_Msk                                  (0x1fUL << LCD_PAL166_B04_0_Pos)                          /*!< LCD PAL166: B04_0 Mask              */
-#define LCD_PAL166_I0_Pos                                     15                                                        /*!< LCD PAL166: I0 Position             */
-#define LCD_PAL166_I0_Msk                                     (0x01UL << LCD_PAL166_I0_Pos)                             /*!< LCD PAL166: I0 Mask                 */
-#define LCD_PAL166_R14_0_Pos                                  16                                                        /*!< LCD PAL166: R14_0 Position          */
-#define LCD_PAL166_R14_0_Msk                                  (0x1fUL << LCD_PAL166_R14_0_Pos)                          /*!< LCD PAL166: R14_0 Mask              */
-#define LCD_PAL166_G14_0_Pos                                  21                                                        /*!< LCD PAL166: G14_0 Position          */
-#define LCD_PAL166_G14_0_Msk                                  (0x1fUL << LCD_PAL166_G14_0_Pos)                          /*!< LCD PAL166: G14_0 Mask              */
-#define LCD_PAL166_B14_0_Pos                                  26                                                        /*!< LCD PAL166: B14_0 Position          */
-#define LCD_PAL166_B14_0_Msk                                  (0x1fUL << LCD_PAL166_B14_0_Pos)                          /*!< LCD PAL166: B14_0 Mask              */
-#define LCD_PAL166_I1_Pos                                     31                                                        /*!< LCD PAL166: I1 Position             */
-#define LCD_PAL166_I1_Msk                                     (0x01UL << LCD_PAL166_I1_Pos)                             /*!< LCD PAL166: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL167  -------------------------------------------
-#define LCD_PAL167_R04_0_Pos                                  0                                                         /*!< LCD PAL167: R04_0 Position          */
-#define LCD_PAL167_R04_0_Msk                                  (0x1fUL << LCD_PAL167_R04_0_Pos)                          /*!< LCD PAL167: R04_0 Mask              */
-#define LCD_PAL167_G04_0_Pos                                  5                                                         /*!< LCD PAL167: G04_0 Position          */
-#define LCD_PAL167_G04_0_Msk                                  (0x1fUL << LCD_PAL167_G04_0_Pos)                          /*!< LCD PAL167: G04_0 Mask              */
-#define LCD_PAL167_B04_0_Pos                                  10                                                        /*!< LCD PAL167: B04_0 Position          */
-#define LCD_PAL167_B04_0_Msk                                  (0x1fUL << LCD_PAL167_B04_0_Pos)                          /*!< LCD PAL167: B04_0 Mask              */
-#define LCD_PAL167_I0_Pos                                     15                                                        /*!< LCD PAL167: I0 Position             */
-#define LCD_PAL167_I0_Msk                                     (0x01UL << LCD_PAL167_I0_Pos)                             /*!< LCD PAL167: I0 Mask                 */
-#define LCD_PAL167_R14_0_Pos                                  16                                                        /*!< LCD PAL167: R14_0 Position          */
-#define LCD_PAL167_R14_0_Msk                                  (0x1fUL << LCD_PAL167_R14_0_Pos)                          /*!< LCD PAL167: R14_0 Mask              */
-#define LCD_PAL167_G14_0_Pos                                  21                                                        /*!< LCD PAL167: G14_0 Position          */
-#define LCD_PAL167_G14_0_Msk                                  (0x1fUL << LCD_PAL167_G14_0_Pos)                          /*!< LCD PAL167: G14_0 Mask              */
-#define LCD_PAL167_B14_0_Pos                                  26                                                        /*!< LCD PAL167: B14_0 Position          */
-#define LCD_PAL167_B14_0_Msk                                  (0x1fUL << LCD_PAL167_B14_0_Pos)                          /*!< LCD PAL167: B14_0 Mask              */
-#define LCD_PAL167_I1_Pos                                     31                                                        /*!< LCD PAL167: I1 Position             */
-#define LCD_PAL167_I1_Msk                                     (0x01UL << LCD_PAL167_I1_Pos)                             /*!< LCD PAL167: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL168  -------------------------------------------
-#define LCD_PAL168_R04_0_Pos                                  0                                                         /*!< LCD PAL168: R04_0 Position          */
-#define LCD_PAL168_R04_0_Msk                                  (0x1fUL << LCD_PAL168_R04_0_Pos)                          /*!< LCD PAL168: R04_0 Mask              */
-#define LCD_PAL168_G04_0_Pos                                  5                                                         /*!< LCD PAL168: G04_0 Position          */
-#define LCD_PAL168_G04_0_Msk                                  (0x1fUL << LCD_PAL168_G04_0_Pos)                          /*!< LCD PAL168: G04_0 Mask              */
-#define LCD_PAL168_B04_0_Pos                                  10                                                        /*!< LCD PAL168: B04_0 Position          */
-#define LCD_PAL168_B04_0_Msk                                  (0x1fUL << LCD_PAL168_B04_0_Pos)                          /*!< LCD PAL168: B04_0 Mask              */
-#define LCD_PAL168_I0_Pos                                     15                                                        /*!< LCD PAL168: I0 Position             */
-#define LCD_PAL168_I0_Msk                                     (0x01UL << LCD_PAL168_I0_Pos)                             /*!< LCD PAL168: I0 Mask                 */
-#define LCD_PAL168_R14_0_Pos                                  16                                                        /*!< LCD PAL168: R14_0 Position          */
-#define LCD_PAL168_R14_0_Msk                                  (0x1fUL << LCD_PAL168_R14_0_Pos)                          /*!< LCD PAL168: R14_0 Mask              */
-#define LCD_PAL168_G14_0_Pos                                  21                                                        /*!< LCD PAL168: G14_0 Position          */
-#define LCD_PAL168_G14_0_Msk                                  (0x1fUL << LCD_PAL168_G14_0_Pos)                          /*!< LCD PAL168: G14_0 Mask              */
-#define LCD_PAL168_B14_0_Pos                                  26                                                        /*!< LCD PAL168: B14_0 Position          */
-#define LCD_PAL168_B14_0_Msk                                  (0x1fUL << LCD_PAL168_B14_0_Pos)                          /*!< LCD PAL168: B14_0 Mask              */
-#define LCD_PAL168_I1_Pos                                     31                                                        /*!< LCD PAL168: I1 Position             */
-#define LCD_PAL168_I1_Msk                                     (0x01UL << LCD_PAL168_I1_Pos)                             /*!< LCD PAL168: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL169  -------------------------------------------
-#define LCD_PAL169_R04_0_Pos                                  0                                                         /*!< LCD PAL169: R04_0 Position          */
-#define LCD_PAL169_R04_0_Msk                                  (0x1fUL << LCD_PAL169_R04_0_Pos)                          /*!< LCD PAL169: R04_0 Mask              */
-#define LCD_PAL169_G04_0_Pos                                  5                                                         /*!< LCD PAL169: G04_0 Position          */
-#define LCD_PAL169_G04_0_Msk                                  (0x1fUL << LCD_PAL169_G04_0_Pos)                          /*!< LCD PAL169: G04_0 Mask              */
-#define LCD_PAL169_B04_0_Pos                                  10                                                        /*!< LCD PAL169: B04_0 Position          */
-#define LCD_PAL169_B04_0_Msk                                  (0x1fUL << LCD_PAL169_B04_0_Pos)                          /*!< LCD PAL169: B04_0 Mask              */
-#define LCD_PAL169_I0_Pos                                     15                                                        /*!< LCD PAL169: I0 Position             */
-#define LCD_PAL169_I0_Msk                                     (0x01UL << LCD_PAL169_I0_Pos)                             /*!< LCD PAL169: I0 Mask                 */
-#define LCD_PAL169_R14_0_Pos                                  16                                                        /*!< LCD PAL169: R14_0 Position          */
-#define LCD_PAL169_R14_0_Msk                                  (0x1fUL << LCD_PAL169_R14_0_Pos)                          /*!< LCD PAL169: R14_0 Mask              */
-#define LCD_PAL169_G14_0_Pos                                  21                                                        /*!< LCD PAL169: G14_0 Position          */
-#define LCD_PAL169_G14_0_Msk                                  (0x1fUL << LCD_PAL169_G14_0_Pos)                          /*!< LCD PAL169: G14_0 Mask              */
-#define LCD_PAL169_B14_0_Pos                                  26                                                        /*!< LCD PAL169: B14_0 Position          */
-#define LCD_PAL169_B14_0_Msk                                  (0x1fUL << LCD_PAL169_B14_0_Pos)                          /*!< LCD PAL169: B14_0 Mask              */
-#define LCD_PAL169_I1_Pos                                     31                                                        /*!< LCD PAL169: I1 Position             */
-#define LCD_PAL169_I1_Msk                                     (0x01UL << LCD_PAL169_I1_Pos)                             /*!< LCD PAL169: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL170  -------------------------------------------
-#define LCD_PAL170_R04_0_Pos                                  0                                                         /*!< LCD PAL170: R04_0 Position          */
-#define LCD_PAL170_R04_0_Msk                                  (0x1fUL << LCD_PAL170_R04_0_Pos)                          /*!< LCD PAL170: R04_0 Mask              */
-#define LCD_PAL170_G04_0_Pos                                  5                                                         /*!< LCD PAL170: G04_0 Position          */
-#define LCD_PAL170_G04_0_Msk                                  (0x1fUL << LCD_PAL170_G04_0_Pos)                          /*!< LCD PAL170: G04_0 Mask              */
-#define LCD_PAL170_B04_0_Pos                                  10                                                        /*!< LCD PAL170: B04_0 Position          */
-#define LCD_PAL170_B04_0_Msk                                  (0x1fUL << LCD_PAL170_B04_0_Pos)                          /*!< LCD PAL170: B04_0 Mask              */
-#define LCD_PAL170_I0_Pos                                     15                                                        /*!< LCD PAL170: I0 Position             */
-#define LCD_PAL170_I0_Msk                                     (0x01UL << LCD_PAL170_I0_Pos)                             /*!< LCD PAL170: I0 Mask                 */
-#define LCD_PAL170_R14_0_Pos                                  16                                                        /*!< LCD PAL170: R14_0 Position          */
-#define LCD_PAL170_R14_0_Msk                                  (0x1fUL << LCD_PAL170_R14_0_Pos)                          /*!< LCD PAL170: R14_0 Mask              */
-#define LCD_PAL170_G14_0_Pos                                  21                                                        /*!< LCD PAL170: G14_0 Position          */
-#define LCD_PAL170_G14_0_Msk                                  (0x1fUL << LCD_PAL170_G14_0_Pos)                          /*!< LCD PAL170: G14_0 Mask              */
-#define LCD_PAL170_B14_0_Pos                                  26                                                        /*!< LCD PAL170: B14_0 Position          */
-#define LCD_PAL170_B14_0_Msk                                  (0x1fUL << LCD_PAL170_B14_0_Pos)                          /*!< LCD PAL170: B14_0 Mask              */
-#define LCD_PAL170_I1_Pos                                     31                                                        /*!< LCD PAL170: I1 Position             */
-#define LCD_PAL170_I1_Msk                                     (0x01UL << LCD_PAL170_I1_Pos)                             /*!< LCD PAL170: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL171  -------------------------------------------
-#define LCD_PAL171_R04_0_Pos                                  0                                                         /*!< LCD PAL171: R04_0 Position          */
-#define LCD_PAL171_R04_0_Msk                                  (0x1fUL << LCD_PAL171_R04_0_Pos)                          /*!< LCD PAL171: R04_0 Mask              */
-#define LCD_PAL171_G04_0_Pos                                  5                                                         /*!< LCD PAL171: G04_0 Position          */
-#define LCD_PAL171_G04_0_Msk                                  (0x1fUL << LCD_PAL171_G04_0_Pos)                          /*!< LCD PAL171: G04_0 Mask              */
-#define LCD_PAL171_B04_0_Pos                                  10                                                        /*!< LCD PAL171: B04_0 Position          */
-#define LCD_PAL171_B04_0_Msk                                  (0x1fUL << LCD_PAL171_B04_0_Pos)                          /*!< LCD PAL171: B04_0 Mask              */
-#define LCD_PAL171_I0_Pos                                     15                                                        /*!< LCD PAL171: I0 Position             */
-#define LCD_PAL171_I0_Msk                                     (0x01UL << LCD_PAL171_I0_Pos)                             /*!< LCD PAL171: I0 Mask                 */
-#define LCD_PAL171_R14_0_Pos                                  16                                                        /*!< LCD PAL171: R14_0 Position          */
-#define LCD_PAL171_R14_0_Msk                                  (0x1fUL << LCD_PAL171_R14_0_Pos)                          /*!< LCD PAL171: R14_0 Mask              */
-#define LCD_PAL171_G14_0_Pos                                  21                                                        /*!< LCD PAL171: G14_0 Position          */
-#define LCD_PAL171_G14_0_Msk                                  (0x1fUL << LCD_PAL171_G14_0_Pos)                          /*!< LCD PAL171: G14_0 Mask              */
-#define LCD_PAL171_B14_0_Pos                                  26                                                        /*!< LCD PAL171: B14_0 Position          */
-#define LCD_PAL171_B14_0_Msk                                  (0x1fUL << LCD_PAL171_B14_0_Pos)                          /*!< LCD PAL171: B14_0 Mask              */
-#define LCD_PAL171_I1_Pos                                     31                                                        /*!< LCD PAL171: I1 Position             */
-#define LCD_PAL171_I1_Msk                                     (0x01UL << LCD_PAL171_I1_Pos)                             /*!< LCD PAL171: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL172  -------------------------------------------
-#define LCD_PAL172_R04_0_Pos                                  0                                                         /*!< LCD PAL172: R04_0 Position          */
-#define LCD_PAL172_R04_0_Msk                                  (0x1fUL << LCD_PAL172_R04_0_Pos)                          /*!< LCD PAL172: R04_0 Mask              */
-#define LCD_PAL172_G04_0_Pos                                  5                                                         /*!< LCD PAL172: G04_0 Position          */
-#define LCD_PAL172_G04_0_Msk                                  (0x1fUL << LCD_PAL172_G04_0_Pos)                          /*!< LCD PAL172: G04_0 Mask              */
-#define LCD_PAL172_B04_0_Pos                                  10                                                        /*!< LCD PAL172: B04_0 Position          */
-#define LCD_PAL172_B04_0_Msk                                  (0x1fUL << LCD_PAL172_B04_0_Pos)                          /*!< LCD PAL172: B04_0 Mask              */
-#define LCD_PAL172_I0_Pos                                     15                                                        /*!< LCD PAL172: I0 Position             */
-#define LCD_PAL172_I0_Msk                                     (0x01UL << LCD_PAL172_I0_Pos)                             /*!< LCD PAL172: I0 Mask                 */
-#define LCD_PAL172_R14_0_Pos                                  16                                                        /*!< LCD PAL172: R14_0 Position          */
-#define LCD_PAL172_R14_0_Msk                                  (0x1fUL << LCD_PAL172_R14_0_Pos)                          /*!< LCD PAL172: R14_0 Mask              */
-#define LCD_PAL172_G14_0_Pos                                  21                                                        /*!< LCD PAL172: G14_0 Position          */
-#define LCD_PAL172_G14_0_Msk                                  (0x1fUL << LCD_PAL172_G14_0_Pos)                          /*!< LCD PAL172: G14_0 Mask              */
-#define LCD_PAL172_B14_0_Pos                                  26                                                        /*!< LCD PAL172: B14_0 Position          */
-#define LCD_PAL172_B14_0_Msk                                  (0x1fUL << LCD_PAL172_B14_0_Pos)                          /*!< LCD PAL172: B14_0 Mask              */
-#define LCD_PAL172_I1_Pos                                     31                                                        /*!< LCD PAL172: I1 Position             */
-#define LCD_PAL172_I1_Msk                                     (0x01UL << LCD_PAL172_I1_Pos)                             /*!< LCD PAL172: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL173  -------------------------------------------
-#define LCD_PAL173_R04_0_Pos                                  0                                                         /*!< LCD PAL173: R04_0 Position          */
-#define LCD_PAL173_R04_0_Msk                                  (0x1fUL << LCD_PAL173_R04_0_Pos)                          /*!< LCD PAL173: R04_0 Mask              */
-#define LCD_PAL173_G04_0_Pos                                  5                                                         /*!< LCD PAL173: G04_0 Position          */
-#define LCD_PAL173_G04_0_Msk                                  (0x1fUL << LCD_PAL173_G04_0_Pos)                          /*!< LCD PAL173: G04_0 Mask              */
-#define LCD_PAL173_B04_0_Pos                                  10                                                        /*!< LCD PAL173: B04_0 Position          */
-#define LCD_PAL173_B04_0_Msk                                  (0x1fUL << LCD_PAL173_B04_0_Pos)                          /*!< LCD PAL173: B04_0 Mask              */
-#define LCD_PAL173_I0_Pos                                     15                                                        /*!< LCD PAL173: I0 Position             */
-#define LCD_PAL173_I0_Msk                                     (0x01UL << LCD_PAL173_I0_Pos)                             /*!< LCD PAL173: I0 Mask                 */
-#define LCD_PAL173_R14_0_Pos                                  16                                                        /*!< LCD PAL173: R14_0 Position          */
-#define LCD_PAL173_R14_0_Msk                                  (0x1fUL << LCD_PAL173_R14_0_Pos)                          /*!< LCD PAL173: R14_0 Mask              */
-#define LCD_PAL173_G14_0_Pos                                  21                                                        /*!< LCD PAL173: G14_0 Position          */
-#define LCD_PAL173_G14_0_Msk                                  (0x1fUL << LCD_PAL173_G14_0_Pos)                          /*!< LCD PAL173: G14_0 Mask              */
-#define LCD_PAL173_B14_0_Pos                                  26                                                        /*!< LCD PAL173: B14_0 Position          */
-#define LCD_PAL173_B14_0_Msk                                  (0x1fUL << LCD_PAL173_B14_0_Pos)                          /*!< LCD PAL173: B14_0 Mask              */
-#define LCD_PAL173_I1_Pos                                     31                                                        /*!< LCD PAL173: I1 Position             */
-#define LCD_PAL173_I1_Msk                                     (0x01UL << LCD_PAL173_I1_Pos)                             /*!< LCD PAL173: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL174  -------------------------------------------
-#define LCD_PAL174_R04_0_Pos                                  0                                                         /*!< LCD PAL174: R04_0 Position          */
-#define LCD_PAL174_R04_0_Msk                                  (0x1fUL << LCD_PAL174_R04_0_Pos)                          /*!< LCD PAL174: R04_0 Mask              */
-#define LCD_PAL174_G04_0_Pos                                  5                                                         /*!< LCD PAL174: G04_0 Position          */
-#define LCD_PAL174_G04_0_Msk                                  (0x1fUL << LCD_PAL174_G04_0_Pos)                          /*!< LCD PAL174: G04_0 Mask              */
-#define LCD_PAL174_B04_0_Pos                                  10                                                        /*!< LCD PAL174: B04_0 Position          */
-#define LCD_PAL174_B04_0_Msk                                  (0x1fUL << LCD_PAL174_B04_0_Pos)                          /*!< LCD PAL174: B04_0 Mask              */
-#define LCD_PAL174_I0_Pos                                     15                                                        /*!< LCD PAL174: I0 Position             */
-#define LCD_PAL174_I0_Msk                                     (0x01UL << LCD_PAL174_I0_Pos)                             /*!< LCD PAL174: I0 Mask                 */
-#define LCD_PAL174_R14_0_Pos                                  16                                                        /*!< LCD PAL174: R14_0 Position          */
-#define LCD_PAL174_R14_0_Msk                                  (0x1fUL << LCD_PAL174_R14_0_Pos)                          /*!< LCD PAL174: R14_0 Mask              */
-#define LCD_PAL174_G14_0_Pos                                  21                                                        /*!< LCD PAL174: G14_0 Position          */
-#define LCD_PAL174_G14_0_Msk                                  (0x1fUL << LCD_PAL174_G14_0_Pos)                          /*!< LCD PAL174: G14_0 Mask              */
-#define LCD_PAL174_B14_0_Pos                                  26                                                        /*!< LCD PAL174: B14_0 Position          */
-#define LCD_PAL174_B14_0_Msk                                  (0x1fUL << LCD_PAL174_B14_0_Pos)                          /*!< LCD PAL174: B14_0 Mask              */
-#define LCD_PAL174_I1_Pos                                     31                                                        /*!< LCD PAL174: I1 Position             */
-#define LCD_PAL174_I1_Msk                                     (0x01UL << LCD_PAL174_I1_Pos)                             /*!< LCD PAL174: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL175  -------------------------------------------
-#define LCD_PAL175_R04_0_Pos                                  0                                                         /*!< LCD PAL175: R04_0 Position          */
-#define LCD_PAL175_R04_0_Msk                                  (0x1fUL << LCD_PAL175_R04_0_Pos)                          /*!< LCD PAL175: R04_0 Mask              */
-#define LCD_PAL175_G04_0_Pos                                  5                                                         /*!< LCD PAL175: G04_0 Position          */
-#define LCD_PAL175_G04_0_Msk                                  (0x1fUL << LCD_PAL175_G04_0_Pos)                          /*!< LCD PAL175: G04_0 Mask              */
-#define LCD_PAL175_B04_0_Pos                                  10                                                        /*!< LCD PAL175: B04_0 Position          */
-#define LCD_PAL175_B04_0_Msk                                  (0x1fUL << LCD_PAL175_B04_0_Pos)                          /*!< LCD PAL175: B04_0 Mask              */
-#define LCD_PAL175_I0_Pos                                     15                                                        /*!< LCD PAL175: I0 Position             */
-#define LCD_PAL175_I0_Msk                                     (0x01UL << LCD_PAL175_I0_Pos)                             /*!< LCD PAL175: I0 Mask                 */
-#define LCD_PAL175_R14_0_Pos                                  16                                                        /*!< LCD PAL175: R14_0 Position          */
-#define LCD_PAL175_R14_0_Msk                                  (0x1fUL << LCD_PAL175_R14_0_Pos)                          /*!< LCD PAL175: R14_0 Mask              */
-#define LCD_PAL175_G14_0_Pos                                  21                                                        /*!< LCD PAL175: G14_0 Position          */
-#define LCD_PAL175_G14_0_Msk                                  (0x1fUL << LCD_PAL175_G14_0_Pos)                          /*!< LCD PAL175: G14_0 Mask              */
-#define LCD_PAL175_B14_0_Pos                                  26                                                        /*!< LCD PAL175: B14_0 Position          */
-#define LCD_PAL175_B14_0_Msk                                  (0x1fUL << LCD_PAL175_B14_0_Pos)                          /*!< LCD PAL175: B14_0 Mask              */
-#define LCD_PAL175_I1_Pos                                     31                                                        /*!< LCD PAL175: I1 Position             */
-#define LCD_PAL175_I1_Msk                                     (0x01UL << LCD_PAL175_I1_Pos)                             /*!< LCD PAL175: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL176  -------------------------------------------
-#define LCD_PAL176_R04_0_Pos                                  0                                                         /*!< LCD PAL176: R04_0 Position          */
-#define LCD_PAL176_R04_0_Msk                                  (0x1fUL << LCD_PAL176_R04_0_Pos)                          /*!< LCD PAL176: R04_0 Mask              */
-#define LCD_PAL176_G04_0_Pos                                  5                                                         /*!< LCD PAL176: G04_0 Position          */
-#define LCD_PAL176_G04_0_Msk                                  (0x1fUL << LCD_PAL176_G04_0_Pos)                          /*!< LCD PAL176: G04_0 Mask              */
-#define LCD_PAL176_B04_0_Pos                                  10                                                        /*!< LCD PAL176: B04_0 Position          */
-#define LCD_PAL176_B04_0_Msk                                  (0x1fUL << LCD_PAL176_B04_0_Pos)                          /*!< LCD PAL176: B04_0 Mask              */
-#define LCD_PAL176_I0_Pos                                     15                                                        /*!< LCD PAL176: I0 Position             */
-#define LCD_PAL176_I0_Msk                                     (0x01UL << LCD_PAL176_I0_Pos)                             /*!< LCD PAL176: I0 Mask                 */
-#define LCD_PAL176_R14_0_Pos                                  16                                                        /*!< LCD PAL176: R14_0 Position          */
-#define LCD_PAL176_R14_0_Msk                                  (0x1fUL << LCD_PAL176_R14_0_Pos)                          /*!< LCD PAL176: R14_0 Mask              */
-#define LCD_PAL176_G14_0_Pos                                  21                                                        /*!< LCD PAL176: G14_0 Position          */
-#define LCD_PAL176_G14_0_Msk                                  (0x1fUL << LCD_PAL176_G14_0_Pos)                          /*!< LCD PAL176: G14_0 Mask              */
-#define LCD_PAL176_B14_0_Pos                                  26                                                        /*!< LCD PAL176: B14_0 Position          */
-#define LCD_PAL176_B14_0_Msk                                  (0x1fUL << LCD_PAL176_B14_0_Pos)                          /*!< LCD PAL176: B14_0 Mask              */
-#define LCD_PAL176_I1_Pos                                     31                                                        /*!< LCD PAL176: I1 Position             */
-#define LCD_PAL176_I1_Msk                                     (0x01UL << LCD_PAL176_I1_Pos)                             /*!< LCD PAL176: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL177  -------------------------------------------
-#define LCD_PAL177_R04_0_Pos                                  0                                                         /*!< LCD PAL177: R04_0 Position          */
-#define LCD_PAL177_R04_0_Msk                                  (0x1fUL << LCD_PAL177_R04_0_Pos)                          /*!< LCD PAL177: R04_0 Mask              */
-#define LCD_PAL177_G04_0_Pos                                  5                                                         /*!< LCD PAL177: G04_0 Position          */
-#define LCD_PAL177_G04_0_Msk                                  (0x1fUL << LCD_PAL177_G04_0_Pos)                          /*!< LCD PAL177: G04_0 Mask              */
-#define LCD_PAL177_B04_0_Pos                                  10                                                        /*!< LCD PAL177: B04_0 Position          */
-#define LCD_PAL177_B04_0_Msk                                  (0x1fUL << LCD_PAL177_B04_0_Pos)                          /*!< LCD PAL177: B04_0 Mask              */
-#define LCD_PAL177_I0_Pos                                     15                                                        /*!< LCD PAL177: I0 Position             */
-#define LCD_PAL177_I0_Msk                                     (0x01UL << LCD_PAL177_I0_Pos)                             /*!< LCD PAL177: I0 Mask                 */
-#define LCD_PAL177_R14_0_Pos                                  16                                                        /*!< LCD PAL177: R14_0 Position          */
-#define LCD_PAL177_R14_0_Msk                                  (0x1fUL << LCD_PAL177_R14_0_Pos)                          /*!< LCD PAL177: R14_0 Mask              */
-#define LCD_PAL177_G14_0_Pos                                  21                                                        /*!< LCD PAL177: G14_0 Position          */
-#define LCD_PAL177_G14_0_Msk                                  (0x1fUL << LCD_PAL177_G14_0_Pos)                          /*!< LCD PAL177: G14_0 Mask              */
-#define LCD_PAL177_B14_0_Pos                                  26                                                        /*!< LCD PAL177: B14_0 Position          */
-#define LCD_PAL177_B14_0_Msk                                  (0x1fUL << LCD_PAL177_B14_0_Pos)                          /*!< LCD PAL177: B14_0 Mask              */
-#define LCD_PAL177_I1_Pos                                     31                                                        /*!< LCD PAL177: I1 Position             */
-#define LCD_PAL177_I1_Msk                                     (0x01UL << LCD_PAL177_I1_Pos)                             /*!< LCD PAL177: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL178  -------------------------------------------
-#define LCD_PAL178_R04_0_Pos                                  0                                                         /*!< LCD PAL178: R04_0 Position          */
-#define LCD_PAL178_R04_0_Msk                                  (0x1fUL << LCD_PAL178_R04_0_Pos)                          /*!< LCD PAL178: R04_0 Mask              */
-#define LCD_PAL178_G04_0_Pos                                  5                                                         /*!< LCD PAL178: G04_0 Position          */
-#define LCD_PAL178_G04_0_Msk                                  (0x1fUL << LCD_PAL178_G04_0_Pos)                          /*!< LCD PAL178: G04_0 Mask              */
-#define LCD_PAL178_B04_0_Pos                                  10                                                        /*!< LCD PAL178: B04_0 Position          */
-#define LCD_PAL178_B04_0_Msk                                  (0x1fUL << LCD_PAL178_B04_0_Pos)                          /*!< LCD PAL178: B04_0 Mask              */
-#define LCD_PAL178_I0_Pos                                     15                                                        /*!< LCD PAL178: I0 Position             */
-#define LCD_PAL178_I0_Msk                                     (0x01UL << LCD_PAL178_I0_Pos)                             /*!< LCD PAL178: I0 Mask                 */
-#define LCD_PAL178_R14_0_Pos                                  16                                                        /*!< LCD PAL178: R14_0 Position          */
-#define LCD_PAL178_R14_0_Msk                                  (0x1fUL << LCD_PAL178_R14_0_Pos)                          /*!< LCD PAL178: R14_0 Mask              */
-#define LCD_PAL178_G14_0_Pos                                  21                                                        /*!< LCD PAL178: G14_0 Position          */
-#define LCD_PAL178_G14_0_Msk                                  (0x1fUL << LCD_PAL178_G14_0_Pos)                          /*!< LCD PAL178: G14_0 Mask              */
-#define LCD_PAL178_B14_0_Pos                                  26                                                        /*!< LCD PAL178: B14_0 Position          */
-#define LCD_PAL178_B14_0_Msk                                  (0x1fUL << LCD_PAL178_B14_0_Pos)                          /*!< LCD PAL178: B14_0 Mask              */
-#define LCD_PAL178_I1_Pos                                     31                                                        /*!< LCD PAL178: I1 Position             */
-#define LCD_PAL178_I1_Msk                                     (0x01UL << LCD_PAL178_I1_Pos)                             /*!< LCD PAL178: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL179  -------------------------------------------
-#define LCD_PAL179_R04_0_Pos                                  0                                                         /*!< LCD PAL179: R04_0 Position          */
-#define LCD_PAL179_R04_0_Msk                                  (0x1fUL << LCD_PAL179_R04_0_Pos)                          /*!< LCD PAL179: R04_0 Mask              */
-#define LCD_PAL179_G04_0_Pos                                  5                                                         /*!< LCD PAL179: G04_0 Position          */
-#define LCD_PAL179_G04_0_Msk                                  (0x1fUL << LCD_PAL179_G04_0_Pos)                          /*!< LCD PAL179: G04_0 Mask              */
-#define LCD_PAL179_B04_0_Pos                                  10                                                        /*!< LCD PAL179: B04_0 Position          */
-#define LCD_PAL179_B04_0_Msk                                  (0x1fUL << LCD_PAL179_B04_0_Pos)                          /*!< LCD PAL179: B04_0 Mask              */
-#define LCD_PAL179_I0_Pos                                     15                                                        /*!< LCD PAL179: I0 Position             */
-#define LCD_PAL179_I0_Msk                                     (0x01UL << LCD_PAL179_I0_Pos)                             /*!< LCD PAL179: I0 Mask                 */
-#define LCD_PAL179_R14_0_Pos                                  16                                                        /*!< LCD PAL179: R14_0 Position          */
-#define LCD_PAL179_R14_0_Msk                                  (0x1fUL << LCD_PAL179_R14_0_Pos)                          /*!< LCD PAL179: R14_0 Mask              */
-#define LCD_PAL179_G14_0_Pos                                  21                                                        /*!< LCD PAL179: G14_0 Position          */
-#define LCD_PAL179_G14_0_Msk                                  (0x1fUL << LCD_PAL179_G14_0_Pos)                          /*!< LCD PAL179: G14_0 Mask              */
-#define LCD_PAL179_B14_0_Pos                                  26                                                        /*!< LCD PAL179: B14_0 Position          */
-#define LCD_PAL179_B14_0_Msk                                  (0x1fUL << LCD_PAL179_B14_0_Pos)                          /*!< LCD PAL179: B14_0 Mask              */
-#define LCD_PAL179_I1_Pos                                     31                                                        /*!< LCD PAL179: I1 Position             */
-#define LCD_PAL179_I1_Msk                                     (0x01UL << LCD_PAL179_I1_Pos)                             /*!< LCD PAL179: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL180  -------------------------------------------
-#define LCD_PAL180_R04_0_Pos                                  0                                                         /*!< LCD PAL180: R04_0 Position          */
-#define LCD_PAL180_R04_0_Msk                                  (0x1fUL << LCD_PAL180_R04_0_Pos)                          /*!< LCD PAL180: R04_0 Mask              */
-#define LCD_PAL180_G04_0_Pos                                  5                                                         /*!< LCD PAL180: G04_0 Position          */
-#define LCD_PAL180_G04_0_Msk                                  (0x1fUL << LCD_PAL180_G04_0_Pos)                          /*!< LCD PAL180: G04_0 Mask              */
-#define LCD_PAL180_B04_0_Pos                                  10                                                        /*!< LCD PAL180: B04_0 Position          */
-#define LCD_PAL180_B04_0_Msk                                  (0x1fUL << LCD_PAL180_B04_0_Pos)                          /*!< LCD PAL180: B04_0 Mask              */
-#define LCD_PAL180_I0_Pos                                     15                                                        /*!< LCD PAL180: I0 Position             */
-#define LCD_PAL180_I0_Msk                                     (0x01UL << LCD_PAL180_I0_Pos)                             /*!< LCD PAL180: I0 Mask                 */
-#define LCD_PAL180_R14_0_Pos                                  16                                                        /*!< LCD PAL180: R14_0 Position          */
-#define LCD_PAL180_R14_0_Msk                                  (0x1fUL << LCD_PAL180_R14_0_Pos)                          /*!< LCD PAL180: R14_0 Mask              */
-#define LCD_PAL180_G14_0_Pos                                  21                                                        /*!< LCD PAL180: G14_0 Position          */
-#define LCD_PAL180_G14_0_Msk                                  (0x1fUL << LCD_PAL180_G14_0_Pos)                          /*!< LCD PAL180: G14_0 Mask              */
-#define LCD_PAL180_B14_0_Pos                                  26                                                        /*!< LCD PAL180: B14_0 Position          */
-#define LCD_PAL180_B14_0_Msk                                  (0x1fUL << LCD_PAL180_B14_0_Pos)                          /*!< LCD PAL180: B14_0 Mask              */
-#define LCD_PAL180_I1_Pos                                     31                                                        /*!< LCD PAL180: I1 Position             */
-#define LCD_PAL180_I1_Msk                                     (0x01UL << LCD_PAL180_I1_Pos)                             /*!< LCD PAL180: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL181  -------------------------------------------
-#define LCD_PAL181_R04_0_Pos                                  0                                                         /*!< LCD PAL181: R04_0 Position          */
-#define LCD_PAL181_R04_0_Msk                                  (0x1fUL << LCD_PAL181_R04_0_Pos)                          /*!< LCD PAL181: R04_0 Mask              */
-#define LCD_PAL181_G04_0_Pos                                  5                                                         /*!< LCD PAL181: G04_0 Position          */
-#define LCD_PAL181_G04_0_Msk                                  (0x1fUL << LCD_PAL181_G04_0_Pos)                          /*!< LCD PAL181: G04_0 Mask              */
-#define LCD_PAL181_B04_0_Pos                                  10                                                        /*!< LCD PAL181: B04_0 Position          */
-#define LCD_PAL181_B04_0_Msk                                  (0x1fUL << LCD_PAL181_B04_0_Pos)                          /*!< LCD PAL181: B04_0 Mask              */
-#define LCD_PAL181_I0_Pos                                     15                                                        /*!< LCD PAL181: I0 Position             */
-#define LCD_PAL181_I0_Msk                                     (0x01UL << LCD_PAL181_I0_Pos)                             /*!< LCD PAL181: I0 Mask                 */
-#define LCD_PAL181_R14_0_Pos                                  16                                                        /*!< LCD PAL181: R14_0 Position          */
-#define LCD_PAL181_R14_0_Msk                                  (0x1fUL << LCD_PAL181_R14_0_Pos)                          /*!< LCD PAL181: R14_0 Mask              */
-#define LCD_PAL181_G14_0_Pos                                  21                                                        /*!< LCD PAL181: G14_0 Position          */
-#define LCD_PAL181_G14_0_Msk                                  (0x1fUL << LCD_PAL181_G14_0_Pos)                          /*!< LCD PAL181: G14_0 Mask              */
-#define LCD_PAL181_B14_0_Pos                                  26                                                        /*!< LCD PAL181: B14_0 Position          */
-#define LCD_PAL181_B14_0_Msk                                  (0x1fUL << LCD_PAL181_B14_0_Pos)                          /*!< LCD PAL181: B14_0 Mask              */
-#define LCD_PAL181_I1_Pos                                     31                                                        /*!< LCD PAL181: I1 Position             */
-#define LCD_PAL181_I1_Msk                                     (0x01UL << LCD_PAL181_I1_Pos)                             /*!< LCD PAL181: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL182  -------------------------------------------
-#define LCD_PAL182_R04_0_Pos                                  0                                                         /*!< LCD PAL182: R04_0 Position          */
-#define LCD_PAL182_R04_0_Msk                                  (0x1fUL << LCD_PAL182_R04_0_Pos)                          /*!< LCD PAL182: R04_0 Mask              */
-#define LCD_PAL182_G04_0_Pos                                  5                                                         /*!< LCD PAL182: G04_0 Position          */
-#define LCD_PAL182_G04_0_Msk                                  (0x1fUL << LCD_PAL182_G04_0_Pos)                          /*!< LCD PAL182: G04_0 Mask              */
-#define LCD_PAL182_B04_0_Pos                                  10                                                        /*!< LCD PAL182: B04_0 Position          */
-#define LCD_PAL182_B04_0_Msk                                  (0x1fUL << LCD_PAL182_B04_0_Pos)                          /*!< LCD PAL182: B04_0 Mask              */
-#define LCD_PAL182_I0_Pos                                     15                                                        /*!< LCD PAL182: I0 Position             */
-#define LCD_PAL182_I0_Msk                                     (0x01UL << LCD_PAL182_I0_Pos)                             /*!< LCD PAL182: I0 Mask                 */
-#define LCD_PAL182_R14_0_Pos                                  16                                                        /*!< LCD PAL182: R14_0 Position          */
-#define LCD_PAL182_R14_0_Msk                                  (0x1fUL << LCD_PAL182_R14_0_Pos)                          /*!< LCD PAL182: R14_0 Mask              */
-#define LCD_PAL182_G14_0_Pos                                  21                                                        /*!< LCD PAL182: G14_0 Position          */
-#define LCD_PAL182_G14_0_Msk                                  (0x1fUL << LCD_PAL182_G14_0_Pos)                          /*!< LCD PAL182: G14_0 Mask              */
-#define LCD_PAL182_B14_0_Pos                                  26                                                        /*!< LCD PAL182: B14_0 Position          */
-#define LCD_PAL182_B14_0_Msk                                  (0x1fUL << LCD_PAL182_B14_0_Pos)                          /*!< LCD PAL182: B14_0 Mask              */
-#define LCD_PAL182_I1_Pos                                     31                                                        /*!< LCD PAL182: I1 Position             */
-#define LCD_PAL182_I1_Msk                                     (0x01UL << LCD_PAL182_I1_Pos)                             /*!< LCD PAL182: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL183  -------------------------------------------
-#define LCD_PAL183_R04_0_Pos                                  0                                                         /*!< LCD PAL183: R04_0 Position          */
-#define LCD_PAL183_R04_0_Msk                                  (0x1fUL << LCD_PAL183_R04_0_Pos)                          /*!< LCD PAL183: R04_0 Mask              */
-#define LCD_PAL183_G04_0_Pos                                  5                                                         /*!< LCD PAL183: G04_0 Position          */
-#define LCD_PAL183_G04_0_Msk                                  (0x1fUL << LCD_PAL183_G04_0_Pos)                          /*!< LCD PAL183: G04_0 Mask              */
-#define LCD_PAL183_B04_0_Pos                                  10                                                        /*!< LCD PAL183: B04_0 Position          */
-#define LCD_PAL183_B04_0_Msk                                  (0x1fUL << LCD_PAL183_B04_0_Pos)                          /*!< LCD PAL183: B04_0 Mask              */
-#define LCD_PAL183_I0_Pos                                     15                                                        /*!< LCD PAL183: I0 Position             */
-#define LCD_PAL183_I0_Msk                                     (0x01UL << LCD_PAL183_I0_Pos)                             /*!< LCD PAL183: I0 Mask                 */
-#define LCD_PAL183_R14_0_Pos                                  16                                                        /*!< LCD PAL183: R14_0 Position          */
-#define LCD_PAL183_R14_0_Msk                                  (0x1fUL << LCD_PAL183_R14_0_Pos)                          /*!< LCD PAL183: R14_0 Mask              */
-#define LCD_PAL183_G14_0_Pos                                  21                                                        /*!< LCD PAL183: G14_0 Position          */
-#define LCD_PAL183_G14_0_Msk                                  (0x1fUL << LCD_PAL183_G14_0_Pos)                          /*!< LCD PAL183: G14_0 Mask              */
-#define LCD_PAL183_B14_0_Pos                                  26                                                        /*!< LCD PAL183: B14_0 Position          */
-#define LCD_PAL183_B14_0_Msk                                  (0x1fUL << LCD_PAL183_B14_0_Pos)                          /*!< LCD PAL183: B14_0 Mask              */
-#define LCD_PAL183_I1_Pos                                     31                                                        /*!< LCD PAL183: I1 Position             */
-#define LCD_PAL183_I1_Msk                                     (0x01UL << LCD_PAL183_I1_Pos)                             /*!< LCD PAL183: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL184  -------------------------------------------
-#define LCD_PAL184_R04_0_Pos                                  0                                                         /*!< LCD PAL184: R04_0 Position          */
-#define LCD_PAL184_R04_0_Msk                                  (0x1fUL << LCD_PAL184_R04_0_Pos)                          /*!< LCD PAL184: R04_0 Mask              */
-#define LCD_PAL184_G04_0_Pos                                  5                                                         /*!< LCD PAL184: G04_0 Position          */
-#define LCD_PAL184_G04_0_Msk                                  (0x1fUL << LCD_PAL184_G04_0_Pos)                          /*!< LCD PAL184: G04_0 Mask              */
-#define LCD_PAL184_B04_0_Pos                                  10                                                        /*!< LCD PAL184: B04_0 Position          */
-#define LCD_PAL184_B04_0_Msk                                  (0x1fUL << LCD_PAL184_B04_0_Pos)                          /*!< LCD PAL184: B04_0 Mask              */
-#define LCD_PAL184_I0_Pos                                     15                                                        /*!< LCD PAL184: I0 Position             */
-#define LCD_PAL184_I0_Msk                                     (0x01UL << LCD_PAL184_I0_Pos)                             /*!< LCD PAL184: I0 Mask                 */
-#define LCD_PAL184_R14_0_Pos                                  16                                                        /*!< LCD PAL184: R14_0 Position          */
-#define LCD_PAL184_R14_0_Msk                                  (0x1fUL << LCD_PAL184_R14_0_Pos)                          /*!< LCD PAL184: R14_0 Mask              */
-#define LCD_PAL184_G14_0_Pos                                  21                                                        /*!< LCD PAL184: G14_0 Position          */
-#define LCD_PAL184_G14_0_Msk                                  (0x1fUL << LCD_PAL184_G14_0_Pos)                          /*!< LCD PAL184: G14_0 Mask              */
-#define LCD_PAL184_B14_0_Pos                                  26                                                        /*!< LCD PAL184: B14_0 Position          */
-#define LCD_PAL184_B14_0_Msk                                  (0x1fUL << LCD_PAL184_B14_0_Pos)                          /*!< LCD PAL184: B14_0 Mask              */
-#define LCD_PAL184_I1_Pos                                     31                                                        /*!< LCD PAL184: I1 Position             */
-#define LCD_PAL184_I1_Msk                                     (0x01UL << LCD_PAL184_I1_Pos)                             /*!< LCD PAL184: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL185  -------------------------------------------
-#define LCD_PAL185_R04_0_Pos                                  0                                                         /*!< LCD PAL185: R04_0 Position          */
-#define LCD_PAL185_R04_0_Msk                                  (0x1fUL << LCD_PAL185_R04_0_Pos)                          /*!< LCD PAL185: R04_0 Mask              */
-#define LCD_PAL185_G04_0_Pos                                  5                                                         /*!< LCD PAL185: G04_0 Position          */
-#define LCD_PAL185_G04_0_Msk                                  (0x1fUL << LCD_PAL185_G04_0_Pos)                          /*!< LCD PAL185: G04_0 Mask              */
-#define LCD_PAL185_B04_0_Pos                                  10                                                        /*!< LCD PAL185: B04_0 Position          */
-#define LCD_PAL185_B04_0_Msk                                  (0x1fUL << LCD_PAL185_B04_0_Pos)                          /*!< LCD PAL185: B04_0 Mask              */
-#define LCD_PAL185_I0_Pos                                     15                                                        /*!< LCD PAL185: I0 Position             */
-#define LCD_PAL185_I0_Msk                                     (0x01UL << LCD_PAL185_I0_Pos)                             /*!< LCD PAL185: I0 Mask                 */
-#define LCD_PAL185_R14_0_Pos                                  16                                                        /*!< LCD PAL185: R14_0 Position          */
-#define LCD_PAL185_R14_0_Msk                                  (0x1fUL << LCD_PAL185_R14_0_Pos)                          /*!< LCD PAL185: R14_0 Mask              */
-#define LCD_PAL185_G14_0_Pos                                  21                                                        /*!< LCD PAL185: G14_0 Position          */
-#define LCD_PAL185_G14_0_Msk                                  (0x1fUL << LCD_PAL185_G14_0_Pos)                          /*!< LCD PAL185: G14_0 Mask              */
-#define LCD_PAL185_B14_0_Pos                                  26                                                        /*!< LCD PAL185: B14_0 Position          */
-#define LCD_PAL185_B14_0_Msk                                  (0x1fUL << LCD_PAL185_B14_0_Pos)                          /*!< LCD PAL185: B14_0 Mask              */
-#define LCD_PAL185_I1_Pos                                     31                                                        /*!< LCD PAL185: I1 Position             */
-#define LCD_PAL185_I1_Msk                                     (0x01UL << LCD_PAL185_I1_Pos)                             /*!< LCD PAL185: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL186  -------------------------------------------
-#define LCD_PAL186_R04_0_Pos                                  0                                                         /*!< LCD PAL186: R04_0 Position          */
-#define LCD_PAL186_R04_0_Msk                                  (0x1fUL << LCD_PAL186_R04_0_Pos)                          /*!< LCD PAL186: R04_0 Mask              */
-#define LCD_PAL186_G04_0_Pos                                  5                                                         /*!< LCD PAL186: G04_0 Position          */
-#define LCD_PAL186_G04_0_Msk                                  (0x1fUL << LCD_PAL186_G04_0_Pos)                          /*!< LCD PAL186: G04_0 Mask              */
-#define LCD_PAL186_B04_0_Pos                                  10                                                        /*!< LCD PAL186: B04_0 Position          */
-#define LCD_PAL186_B04_0_Msk                                  (0x1fUL << LCD_PAL186_B04_0_Pos)                          /*!< LCD PAL186: B04_0 Mask              */
-#define LCD_PAL186_I0_Pos                                     15                                                        /*!< LCD PAL186: I0 Position             */
-#define LCD_PAL186_I0_Msk                                     (0x01UL << LCD_PAL186_I0_Pos)                             /*!< LCD PAL186: I0 Mask                 */
-#define LCD_PAL186_R14_0_Pos                                  16                                                        /*!< LCD PAL186: R14_0 Position          */
-#define LCD_PAL186_R14_0_Msk                                  (0x1fUL << LCD_PAL186_R14_0_Pos)                          /*!< LCD PAL186: R14_0 Mask              */
-#define LCD_PAL186_G14_0_Pos                                  21                                                        /*!< LCD PAL186: G14_0 Position          */
-#define LCD_PAL186_G14_0_Msk                                  (0x1fUL << LCD_PAL186_G14_0_Pos)                          /*!< LCD PAL186: G14_0 Mask              */
-#define LCD_PAL186_B14_0_Pos                                  26                                                        /*!< LCD PAL186: B14_0 Position          */
-#define LCD_PAL186_B14_0_Msk                                  (0x1fUL << LCD_PAL186_B14_0_Pos)                          /*!< LCD PAL186: B14_0 Mask              */
-#define LCD_PAL186_I1_Pos                                     31                                                        /*!< LCD PAL186: I1 Position             */
-#define LCD_PAL186_I1_Msk                                     (0x01UL << LCD_PAL186_I1_Pos)                             /*!< LCD PAL186: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL187  -------------------------------------------
-#define LCD_PAL187_R04_0_Pos                                  0                                                         /*!< LCD PAL187: R04_0 Position          */
-#define LCD_PAL187_R04_0_Msk                                  (0x1fUL << LCD_PAL187_R04_0_Pos)                          /*!< LCD PAL187: R04_0 Mask              */
-#define LCD_PAL187_G04_0_Pos                                  5                                                         /*!< LCD PAL187: G04_0 Position          */
-#define LCD_PAL187_G04_0_Msk                                  (0x1fUL << LCD_PAL187_G04_0_Pos)                          /*!< LCD PAL187: G04_0 Mask              */
-#define LCD_PAL187_B04_0_Pos                                  10                                                        /*!< LCD PAL187: B04_0 Position          */
-#define LCD_PAL187_B04_0_Msk                                  (0x1fUL << LCD_PAL187_B04_0_Pos)                          /*!< LCD PAL187: B04_0 Mask              */
-#define LCD_PAL187_I0_Pos                                     15                                                        /*!< LCD PAL187: I0 Position             */
-#define LCD_PAL187_I0_Msk                                     (0x01UL << LCD_PAL187_I0_Pos)                             /*!< LCD PAL187: I0 Mask                 */
-#define LCD_PAL187_R14_0_Pos                                  16                                                        /*!< LCD PAL187: R14_0 Position          */
-#define LCD_PAL187_R14_0_Msk                                  (0x1fUL << LCD_PAL187_R14_0_Pos)                          /*!< LCD PAL187: R14_0 Mask              */
-#define LCD_PAL187_G14_0_Pos                                  21                                                        /*!< LCD PAL187: G14_0 Position          */
-#define LCD_PAL187_G14_0_Msk                                  (0x1fUL << LCD_PAL187_G14_0_Pos)                          /*!< LCD PAL187: G14_0 Mask              */
-#define LCD_PAL187_B14_0_Pos                                  26                                                        /*!< LCD PAL187: B14_0 Position          */
-#define LCD_PAL187_B14_0_Msk                                  (0x1fUL << LCD_PAL187_B14_0_Pos)                          /*!< LCD PAL187: B14_0 Mask              */
-#define LCD_PAL187_I1_Pos                                     31                                                        /*!< LCD PAL187: I1 Position             */
-#define LCD_PAL187_I1_Msk                                     (0x01UL << LCD_PAL187_I1_Pos)                             /*!< LCD PAL187: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL188  -------------------------------------------
-#define LCD_PAL188_R04_0_Pos                                  0                                                         /*!< LCD PAL188: R04_0 Position          */
-#define LCD_PAL188_R04_0_Msk                                  (0x1fUL << LCD_PAL188_R04_0_Pos)                          /*!< LCD PAL188: R04_0 Mask              */
-#define LCD_PAL188_G04_0_Pos                                  5                                                         /*!< LCD PAL188: G04_0 Position          */
-#define LCD_PAL188_G04_0_Msk                                  (0x1fUL << LCD_PAL188_G04_0_Pos)                          /*!< LCD PAL188: G04_0 Mask              */
-#define LCD_PAL188_B04_0_Pos                                  10                                                        /*!< LCD PAL188: B04_0 Position          */
-#define LCD_PAL188_B04_0_Msk                                  (0x1fUL << LCD_PAL188_B04_0_Pos)                          /*!< LCD PAL188: B04_0 Mask              */
-#define LCD_PAL188_I0_Pos                                     15                                                        /*!< LCD PAL188: I0 Position             */
-#define LCD_PAL188_I0_Msk                                     (0x01UL << LCD_PAL188_I0_Pos)                             /*!< LCD PAL188: I0 Mask                 */
-#define LCD_PAL188_R14_0_Pos                                  16                                                        /*!< LCD PAL188: R14_0 Position          */
-#define LCD_PAL188_R14_0_Msk                                  (0x1fUL << LCD_PAL188_R14_0_Pos)                          /*!< LCD PAL188: R14_0 Mask              */
-#define LCD_PAL188_G14_0_Pos                                  21                                                        /*!< LCD PAL188: G14_0 Position          */
-#define LCD_PAL188_G14_0_Msk                                  (0x1fUL << LCD_PAL188_G14_0_Pos)                          /*!< LCD PAL188: G14_0 Mask              */
-#define LCD_PAL188_B14_0_Pos                                  26                                                        /*!< LCD PAL188: B14_0 Position          */
-#define LCD_PAL188_B14_0_Msk                                  (0x1fUL << LCD_PAL188_B14_0_Pos)                          /*!< LCD PAL188: B14_0 Mask              */
-#define LCD_PAL188_I1_Pos                                     31                                                        /*!< LCD PAL188: I1 Position             */
-#define LCD_PAL188_I1_Msk                                     (0x01UL << LCD_PAL188_I1_Pos)                             /*!< LCD PAL188: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL189  -------------------------------------------
-#define LCD_PAL189_R04_0_Pos                                  0                                                         /*!< LCD PAL189: R04_0 Position          */
-#define LCD_PAL189_R04_0_Msk                                  (0x1fUL << LCD_PAL189_R04_0_Pos)                          /*!< LCD PAL189: R04_0 Mask              */
-#define LCD_PAL189_G04_0_Pos                                  5                                                         /*!< LCD PAL189: G04_0 Position          */
-#define LCD_PAL189_G04_0_Msk                                  (0x1fUL << LCD_PAL189_G04_0_Pos)                          /*!< LCD PAL189: G04_0 Mask              */
-#define LCD_PAL189_B04_0_Pos                                  10                                                        /*!< LCD PAL189: B04_0 Position          */
-#define LCD_PAL189_B04_0_Msk                                  (0x1fUL << LCD_PAL189_B04_0_Pos)                          /*!< LCD PAL189: B04_0 Mask              */
-#define LCD_PAL189_I0_Pos                                     15                                                        /*!< LCD PAL189: I0 Position             */
-#define LCD_PAL189_I0_Msk                                     (0x01UL << LCD_PAL189_I0_Pos)                             /*!< LCD PAL189: I0 Mask                 */
-#define LCD_PAL189_R14_0_Pos                                  16                                                        /*!< LCD PAL189: R14_0 Position          */
-#define LCD_PAL189_R14_0_Msk                                  (0x1fUL << LCD_PAL189_R14_0_Pos)                          /*!< LCD PAL189: R14_0 Mask              */
-#define LCD_PAL189_G14_0_Pos                                  21                                                        /*!< LCD PAL189: G14_0 Position          */
-#define LCD_PAL189_G14_0_Msk                                  (0x1fUL << LCD_PAL189_G14_0_Pos)                          /*!< LCD PAL189: G14_0 Mask              */
-#define LCD_PAL189_B14_0_Pos                                  26                                                        /*!< LCD PAL189: B14_0 Position          */
-#define LCD_PAL189_B14_0_Msk                                  (0x1fUL << LCD_PAL189_B14_0_Pos)                          /*!< LCD PAL189: B14_0 Mask              */
-#define LCD_PAL189_I1_Pos                                     31                                                        /*!< LCD PAL189: I1 Position             */
-#define LCD_PAL189_I1_Msk                                     (0x01UL << LCD_PAL189_I1_Pos)                             /*!< LCD PAL189: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL190  -------------------------------------------
-#define LCD_PAL190_R04_0_Pos                                  0                                                         /*!< LCD PAL190: R04_0 Position          */
-#define LCD_PAL190_R04_0_Msk                                  (0x1fUL << LCD_PAL190_R04_0_Pos)                          /*!< LCD PAL190: R04_0 Mask              */
-#define LCD_PAL190_G04_0_Pos                                  5                                                         /*!< LCD PAL190: G04_0 Position          */
-#define LCD_PAL190_G04_0_Msk                                  (0x1fUL << LCD_PAL190_G04_0_Pos)                          /*!< LCD PAL190: G04_0 Mask              */
-#define LCD_PAL190_B04_0_Pos                                  10                                                        /*!< LCD PAL190: B04_0 Position          */
-#define LCD_PAL190_B04_0_Msk                                  (0x1fUL << LCD_PAL190_B04_0_Pos)                          /*!< LCD PAL190: B04_0 Mask              */
-#define LCD_PAL190_I0_Pos                                     15                                                        /*!< LCD PAL190: I0 Position             */
-#define LCD_PAL190_I0_Msk                                     (0x01UL << LCD_PAL190_I0_Pos)                             /*!< LCD PAL190: I0 Mask                 */
-#define LCD_PAL190_R14_0_Pos                                  16                                                        /*!< LCD PAL190: R14_0 Position          */
-#define LCD_PAL190_R14_0_Msk                                  (0x1fUL << LCD_PAL190_R14_0_Pos)                          /*!< LCD PAL190: R14_0 Mask              */
-#define LCD_PAL190_G14_0_Pos                                  21                                                        /*!< LCD PAL190: G14_0 Position          */
-#define LCD_PAL190_G14_0_Msk                                  (0x1fUL << LCD_PAL190_G14_0_Pos)                          /*!< LCD PAL190: G14_0 Mask              */
-#define LCD_PAL190_B14_0_Pos                                  26                                                        /*!< LCD PAL190: B14_0 Position          */
-#define LCD_PAL190_B14_0_Msk                                  (0x1fUL << LCD_PAL190_B14_0_Pos)                          /*!< LCD PAL190: B14_0 Mask              */
-#define LCD_PAL190_I1_Pos                                     31                                                        /*!< LCD PAL190: I1 Position             */
-#define LCD_PAL190_I1_Msk                                     (0x01UL << LCD_PAL190_I1_Pos)                             /*!< LCD PAL190: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL191  -------------------------------------------
-#define LCD_PAL191_R04_0_Pos                                  0                                                         /*!< LCD PAL191: R04_0 Position          */
-#define LCD_PAL191_R04_0_Msk                                  (0x1fUL << LCD_PAL191_R04_0_Pos)                          /*!< LCD PAL191: R04_0 Mask              */
-#define LCD_PAL191_G04_0_Pos                                  5                                                         /*!< LCD PAL191: G04_0 Position          */
-#define LCD_PAL191_G04_0_Msk                                  (0x1fUL << LCD_PAL191_G04_0_Pos)                          /*!< LCD PAL191: G04_0 Mask              */
-#define LCD_PAL191_B04_0_Pos                                  10                                                        /*!< LCD PAL191: B04_0 Position          */
-#define LCD_PAL191_B04_0_Msk                                  (0x1fUL << LCD_PAL191_B04_0_Pos)                          /*!< LCD PAL191: B04_0 Mask              */
-#define LCD_PAL191_I0_Pos                                     15                                                        /*!< LCD PAL191: I0 Position             */
-#define LCD_PAL191_I0_Msk                                     (0x01UL << LCD_PAL191_I0_Pos)                             /*!< LCD PAL191: I0 Mask                 */
-#define LCD_PAL191_R14_0_Pos                                  16                                                        /*!< LCD PAL191: R14_0 Position          */
-#define LCD_PAL191_R14_0_Msk                                  (0x1fUL << LCD_PAL191_R14_0_Pos)                          /*!< LCD PAL191: R14_0 Mask              */
-#define LCD_PAL191_G14_0_Pos                                  21                                                        /*!< LCD PAL191: G14_0 Position          */
-#define LCD_PAL191_G14_0_Msk                                  (0x1fUL << LCD_PAL191_G14_0_Pos)                          /*!< LCD PAL191: G14_0 Mask              */
-#define LCD_PAL191_B14_0_Pos                                  26                                                        /*!< LCD PAL191: B14_0 Position          */
-#define LCD_PAL191_B14_0_Msk                                  (0x1fUL << LCD_PAL191_B14_0_Pos)                          /*!< LCD PAL191: B14_0 Mask              */
-#define LCD_PAL191_I1_Pos                                     31                                                        /*!< LCD PAL191: I1 Position             */
-#define LCD_PAL191_I1_Msk                                     (0x01UL << LCD_PAL191_I1_Pos)                             /*!< LCD PAL191: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL192  -------------------------------------------
-#define LCD_PAL192_R04_0_Pos                                  0                                                         /*!< LCD PAL192: R04_0 Position          */
-#define LCD_PAL192_R04_0_Msk                                  (0x1fUL << LCD_PAL192_R04_0_Pos)                          /*!< LCD PAL192: R04_0 Mask              */
-#define LCD_PAL192_G04_0_Pos                                  5                                                         /*!< LCD PAL192: G04_0 Position          */
-#define LCD_PAL192_G04_0_Msk                                  (0x1fUL << LCD_PAL192_G04_0_Pos)                          /*!< LCD PAL192: G04_0 Mask              */
-#define LCD_PAL192_B04_0_Pos                                  10                                                        /*!< LCD PAL192: B04_0 Position          */
-#define LCD_PAL192_B04_0_Msk                                  (0x1fUL << LCD_PAL192_B04_0_Pos)                          /*!< LCD PAL192: B04_0 Mask              */
-#define LCD_PAL192_I0_Pos                                     15                                                        /*!< LCD PAL192: I0 Position             */
-#define LCD_PAL192_I0_Msk                                     (0x01UL << LCD_PAL192_I0_Pos)                             /*!< LCD PAL192: I0 Mask                 */
-#define LCD_PAL192_R14_0_Pos                                  16                                                        /*!< LCD PAL192: R14_0 Position          */
-#define LCD_PAL192_R14_0_Msk                                  (0x1fUL << LCD_PAL192_R14_0_Pos)                          /*!< LCD PAL192: R14_0 Mask              */
-#define LCD_PAL192_G14_0_Pos                                  21                                                        /*!< LCD PAL192: G14_0 Position          */
-#define LCD_PAL192_G14_0_Msk                                  (0x1fUL << LCD_PAL192_G14_0_Pos)                          /*!< LCD PAL192: G14_0 Mask              */
-#define LCD_PAL192_B14_0_Pos                                  26                                                        /*!< LCD PAL192: B14_0 Position          */
-#define LCD_PAL192_B14_0_Msk                                  (0x1fUL << LCD_PAL192_B14_0_Pos)                          /*!< LCD PAL192: B14_0 Mask              */
-#define LCD_PAL192_I1_Pos                                     31                                                        /*!< LCD PAL192: I1 Position             */
-#define LCD_PAL192_I1_Msk                                     (0x01UL << LCD_PAL192_I1_Pos)                             /*!< LCD PAL192: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL193  -------------------------------------------
-#define LCD_PAL193_R04_0_Pos                                  0                                                         /*!< LCD PAL193: R04_0 Position          */
-#define LCD_PAL193_R04_0_Msk                                  (0x1fUL << LCD_PAL193_R04_0_Pos)                          /*!< LCD PAL193: R04_0 Mask              */
-#define LCD_PAL193_G04_0_Pos                                  5                                                         /*!< LCD PAL193: G04_0 Position          */
-#define LCD_PAL193_G04_0_Msk                                  (0x1fUL << LCD_PAL193_G04_0_Pos)                          /*!< LCD PAL193: G04_0 Mask              */
-#define LCD_PAL193_B04_0_Pos                                  10                                                        /*!< LCD PAL193: B04_0 Position          */
-#define LCD_PAL193_B04_0_Msk                                  (0x1fUL << LCD_PAL193_B04_0_Pos)                          /*!< LCD PAL193: B04_0 Mask              */
-#define LCD_PAL193_I0_Pos                                     15                                                        /*!< LCD PAL193: I0 Position             */
-#define LCD_PAL193_I0_Msk                                     (0x01UL << LCD_PAL193_I0_Pos)                             /*!< LCD PAL193: I0 Mask                 */
-#define LCD_PAL193_R14_0_Pos                                  16                                                        /*!< LCD PAL193: R14_0 Position          */
-#define LCD_PAL193_R14_0_Msk                                  (0x1fUL << LCD_PAL193_R14_0_Pos)                          /*!< LCD PAL193: R14_0 Mask              */
-#define LCD_PAL193_G14_0_Pos                                  21                                                        /*!< LCD PAL193: G14_0 Position          */
-#define LCD_PAL193_G14_0_Msk                                  (0x1fUL << LCD_PAL193_G14_0_Pos)                          /*!< LCD PAL193: G14_0 Mask              */
-#define LCD_PAL193_B14_0_Pos                                  26                                                        /*!< LCD PAL193: B14_0 Position          */
-#define LCD_PAL193_B14_0_Msk                                  (0x1fUL << LCD_PAL193_B14_0_Pos)                          /*!< LCD PAL193: B14_0 Mask              */
-#define LCD_PAL193_I1_Pos                                     31                                                        /*!< LCD PAL193: I1 Position             */
-#define LCD_PAL193_I1_Msk                                     (0x01UL << LCD_PAL193_I1_Pos)                             /*!< LCD PAL193: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL194  -------------------------------------------
-#define LCD_PAL194_R04_0_Pos                                  0                                                         /*!< LCD PAL194: R04_0 Position          */
-#define LCD_PAL194_R04_0_Msk                                  (0x1fUL << LCD_PAL194_R04_0_Pos)                          /*!< LCD PAL194: R04_0 Mask              */
-#define LCD_PAL194_G04_0_Pos                                  5                                                         /*!< LCD PAL194: G04_0 Position          */
-#define LCD_PAL194_G04_0_Msk                                  (0x1fUL << LCD_PAL194_G04_0_Pos)                          /*!< LCD PAL194: G04_0 Mask              */
-#define LCD_PAL194_B04_0_Pos                                  10                                                        /*!< LCD PAL194: B04_0 Position          */
-#define LCD_PAL194_B04_0_Msk                                  (0x1fUL << LCD_PAL194_B04_0_Pos)                          /*!< LCD PAL194: B04_0 Mask              */
-#define LCD_PAL194_I0_Pos                                     15                                                        /*!< LCD PAL194: I0 Position             */
-#define LCD_PAL194_I0_Msk                                     (0x01UL << LCD_PAL194_I0_Pos)                             /*!< LCD PAL194: I0 Mask                 */
-#define LCD_PAL194_R14_0_Pos                                  16                                                        /*!< LCD PAL194: R14_0 Position          */
-#define LCD_PAL194_R14_0_Msk                                  (0x1fUL << LCD_PAL194_R14_0_Pos)                          /*!< LCD PAL194: R14_0 Mask              */
-#define LCD_PAL194_G14_0_Pos                                  21                                                        /*!< LCD PAL194: G14_0 Position          */
-#define LCD_PAL194_G14_0_Msk                                  (0x1fUL << LCD_PAL194_G14_0_Pos)                          /*!< LCD PAL194: G14_0 Mask              */
-#define LCD_PAL194_B14_0_Pos                                  26                                                        /*!< LCD PAL194: B14_0 Position          */
-#define LCD_PAL194_B14_0_Msk                                  (0x1fUL << LCD_PAL194_B14_0_Pos)                          /*!< LCD PAL194: B14_0 Mask              */
-#define LCD_PAL194_I1_Pos                                     31                                                        /*!< LCD PAL194: I1 Position             */
-#define LCD_PAL194_I1_Msk                                     (0x01UL << LCD_PAL194_I1_Pos)                             /*!< LCD PAL194: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL195  -------------------------------------------
-#define LCD_PAL195_R04_0_Pos                                  0                                                         /*!< LCD PAL195: R04_0 Position          */
-#define LCD_PAL195_R04_0_Msk                                  (0x1fUL << LCD_PAL195_R04_0_Pos)                          /*!< LCD PAL195: R04_0 Mask              */
-#define LCD_PAL195_G04_0_Pos                                  5                                                         /*!< LCD PAL195: G04_0 Position          */
-#define LCD_PAL195_G04_0_Msk                                  (0x1fUL << LCD_PAL195_G04_0_Pos)                          /*!< LCD PAL195: G04_0 Mask              */
-#define LCD_PAL195_B04_0_Pos                                  10                                                        /*!< LCD PAL195: B04_0 Position          */
-#define LCD_PAL195_B04_0_Msk                                  (0x1fUL << LCD_PAL195_B04_0_Pos)                          /*!< LCD PAL195: B04_0 Mask              */
-#define LCD_PAL195_I0_Pos                                     15                                                        /*!< LCD PAL195: I0 Position             */
-#define LCD_PAL195_I0_Msk                                     (0x01UL << LCD_PAL195_I0_Pos)                             /*!< LCD PAL195: I0 Mask                 */
-#define LCD_PAL195_R14_0_Pos                                  16                                                        /*!< LCD PAL195: R14_0 Position          */
-#define LCD_PAL195_R14_0_Msk                                  (0x1fUL << LCD_PAL195_R14_0_Pos)                          /*!< LCD PAL195: R14_0 Mask              */
-#define LCD_PAL195_G14_0_Pos                                  21                                                        /*!< LCD PAL195: G14_0 Position          */
-#define LCD_PAL195_G14_0_Msk                                  (0x1fUL << LCD_PAL195_G14_0_Pos)                          /*!< LCD PAL195: G14_0 Mask              */
-#define LCD_PAL195_B14_0_Pos                                  26                                                        /*!< LCD PAL195: B14_0 Position          */
-#define LCD_PAL195_B14_0_Msk                                  (0x1fUL << LCD_PAL195_B14_0_Pos)                          /*!< LCD PAL195: B14_0 Mask              */
-#define LCD_PAL195_I1_Pos                                     31                                                        /*!< LCD PAL195: I1 Position             */
-#define LCD_PAL195_I1_Msk                                     (0x01UL << LCD_PAL195_I1_Pos)                             /*!< LCD PAL195: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL196  -------------------------------------------
-#define LCD_PAL196_R04_0_Pos                                  0                                                         /*!< LCD PAL196: R04_0 Position          */
-#define LCD_PAL196_R04_0_Msk                                  (0x1fUL << LCD_PAL196_R04_0_Pos)                          /*!< LCD PAL196: R04_0 Mask              */
-#define LCD_PAL196_G04_0_Pos                                  5                                                         /*!< LCD PAL196: G04_0 Position          */
-#define LCD_PAL196_G04_0_Msk                                  (0x1fUL << LCD_PAL196_G04_0_Pos)                          /*!< LCD PAL196: G04_0 Mask              */
-#define LCD_PAL196_B04_0_Pos                                  10                                                        /*!< LCD PAL196: B04_0 Position          */
-#define LCD_PAL196_B04_0_Msk                                  (0x1fUL << LCD_PAL196_B04_0_Pos)                          /*!< LCD PAL196: B04_0 Mask              */
-#define LCD_PAL196_I0_Pos                                     15                                                        /*!< LCD PAL196: I0 Position             */
-#define LCD_PAL196_I0_Msk                                     (0x01UL << LCD_PAL196_I0_Pos)                             /*!< LCD PAL196: I0 Mask                 */
-#define LCD_PAL196_R14_0_Pos                                  16                                                        /*!< LCD PAL196: R14_0 Position          */
-#define LCD_PAL196_R14_0_Msk                                  (0x1fUL << LCD_PAL196_R14_0_Pos)                          /*!< LCD PAL196: R14_0 Mask              */
-#define LCD_PAL196_G14_0_Pos                                  21                                                        /*!< LCD PAL196: G14_0 Position          */
-#define LCD_PAL196_G14_0_Msk                                  (0x1fUL << LCD_PAL196_G14_0_Pos)                          /*!< LCD PAL196: G14_0 Mask              */
-#define LCD_PAL196_B14_0_Pos                                  26                                                        /*!< LCD PAL196: B14_0 Position          */
-#define LCD_PAL196_B14_0_Msk                                  (0x1fUL << LCD_PAL196_B14_0_Pos)                          /*!< LCD PAL196: B14_0 Mask              */
-#define LCD_PAL196_I1_Pos                                     31                                                        /*!< LCD PAL196: I1 Position             */
-#define LCD_PAL196_I1_Msk                                     (0x01UL << LCD_PAL196_I1_Pos)                             /*!< LCD PAL196: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL197  -------------------------------------------
-#define LCD_PAL197_R04_0_Pos                                  0                                                         /*!< LCD PAL197: R04_0 Position          */
-#define LCD_PAL197_R04_0_Msk                                  (0x1fUL << LCD_PAL197_R04_0_Pos)                          /*!< LCD PAL197: R04_0 Mask              */
-#define LCD_PAL197_G04_0_Pos                                  5                                                         /*!< LCD PAL197: G04_0 Position          */
-#define LCD_PAL197_G04_0_Msk                                  (0x1fUL << LCD_PAL197_G04_0_Pos)                          /*!< LCD PAL197: G04_0 Mask              */
-#define LCD_PAL197_B04_0_Pos                                  10                                                        /*!< LCD PAL197: B04_0 Position          */
-#define LCD_PAL197_B04_0_Msk                                  (0x1fUL << LCD_PAL197_B04_0_Pos)                          /*!< LCD PAL197: B04_0 Mask              */
-#define LCD_PAL197_I0_Pos                                     15                                                        /*!< LCD PAL197: I0 Position             */
-#define LCD_PAL197_I0_Msk                                     (0x01UL << LCD_PAL197_I0_Pos)                             /*!< LCD PAL197: I0 Mask                 */
-#define LCD_PAL197_R14_0_Pos                                  16                                                        /*!< LCD PAL197: R14_0 Position          */
-#define LCD_PAL197_R14_0_Msk                                  (0x1fUL << LCD_PAL197_R14_0_Pos)                          /*!< LCD PAL197: R14_0 Mask              */
-#define LCD_PAL197_G14_0_Pos                                  21                                                        /*!< LCD PAL197: G14_0 Position          */
-#define LCD_PAL197_G14_0_Msk                                  (0x1fUL << LCD_PAL197_G14_0_Pos)                          /*!< LCD PAL197: G14_0 Mask              */
-#define LCD_PAL197_B14_0_Pos                                  26                                                        /*!< LCD PAL197: B14_0 Position          */
-#define LCD_PAL197_B14_0_Msk                                  (0x1fUL << LCD_PAL197_B14_0_Pos)                          /*!< LCD PAL197: B14_0 Mask              */
-#define LCD_PAL197_I1_Pos                                     31                                                        /*!< LCD PAL197: I1 Position             */
-#define LCD_PAL197_I1_Msk                                     (0x01UL << LCD_PAL197_I1_Pos)                             /*!< LCD PAL197: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL198  -------------------------------------------
-#define LCD_PAL198_R04_0_Pos                                  0                                                         /*!< LCD PAL198: R04_0 Position          */
-#define LCD_PAL198_R04_0_Msk                                  (0x1fUL << LCD_PAL198_R04_0_Pos)                          /*!< LCD PAL198: R04_0 Mask              */
-#define LCD_PAL198_G04_0_Pos                                  5                                                         /*!< LCD PAL198: G04_0 Position          */
-#define LCD_PAL198_G04_0_Msk                                  (0x1fUL << LCD_PAL198_G04_0_Pos)                          /*!< LCD PAL198: G04_0 Mask              */
-#define LCD_PAL198_B04_0_Pos                                  10                                                        /*!< LCD PAL198: B04_0 Position          */
-#define LCD_PAL198_B04_0_Msk                                  (0x1fUL << LCD_PAL198_B04_0_Pos)                          /*!< LCD PAL198: B04_0 Mask              */
-#define LCD_PAL198_I0_Pos                                     15                                                        /*!< LCD PAL198: I0 Position             */
-#define LCD_PAL198_I0_Msk                                     (0x01UL << LCD_PAL198_I0_Pos)                             /*!< LCD PAL198: I0 Mask                 */
-#define LCD_PAL198_R14_0_Pos                                  16                                                        /*!< LCD PAL198: R14_0 Position          */
-#define LCD_PAL198_R14_0_Msk                                  (0x1fUL << LCD_PAL198_R14_0_Pos)                          /*!< LCD PAL198: R14_0 Mask              */
-#define LCD_PAL198_G14_0_Pos                                  21                                                        /*!< LCD PAL198: G14_0 Position          */
-#define LCD_PAL198_G14_0_Msk                                  (0x1fUL << LCD_PAL198_G14_0_Pos)                          /*!< LCD PAL198: G14_0 Mask              */
-#define LCD_PAL198_B14_0_Pos                                  26                                                        /*!< LCD PAL198: B14_0 Position          */
-#define LCD_PAL198_B14_0_Msk                                  (0x1fUL << LCD_PAL198_B14_0_Pos)                          /*!< LCD PAL198: B14_0 Mask              */
-#define LCD_PAL198_I1_Pos                                     31                                                        /*!< LCD PAL198: I1 Position             */
-#define LCD_PAL198_I1_Msk                                     (0x01UL << LCD_PAL198_I1_Pos)                             /*!< LCD PAL198: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL199  -------------------------------------------
-#define LCD_PAL199_R04_0_Pos                                  0                                                         /*!< LCD PAL199: R04_0 Position          */
-#define LCD_PAL199_R04_0_Msk                                  (0x1fUL << LCD_PAL199_R04_0_Pos)                          /*!< LCD PAL199: R04_0 Mask              */
-#define LCD_PAL199_G04_0_Pos                                  5                                                         /*!< LCD PAL199: G04_0 Position          */
-#define LCD_PAL199_G04_0_Msk                                  (0x1fUL << LCD_PAL199_G04_0_Pos)                          /*!< LCD PAL199: G04_0 Mask              */
-#define LCD_PAL199_B04_0_Pos                                  10                                                        /*!< LCD PAL199: B04_0 Position          */
-#define LCD_PAL199_B04_0_Msk                                  (0x1fUL << LCD_PAL199_B04_0_Pos)                          /*!< LCD PAL199: B04_0 Mask              */
-#define LCD_PAL199_I0_Pos                                     15                                                        /*!< LCD PAL199: I0 Position             */
-#define LCD_PAL199_I0_Msk                                     (0x01UL << LCD_PAL199_I0_Pos)                             /*!< LCD PAL199: I0 Mask                 */
-#define LCD_PAL199_R14_0_Pos                                  16                                                        /*!< LCD PAL199: R14_0 Position          */
-#define LCD_PAL199_R14_0_Msk                                  (0x1fUL << LCD_PAL199_R14_0_Pos)                          /*!< LCD PAL199: R14_0 Mask              */
-#define LCD_PAL199_G14_0_Pos                                  21                                                        /*!< LCD PAL199: G14_0 Position          */
-#define LCD_PAL199_G14_0_Msk                                  (0x1fUL << LCD_PAL199_G14_0_Pos)                          /*!< LCD PAL199: G14_0 Mask              */
-#define LCD_PAL199_B14_0_Pos                                  26                                                        /*!< LCD PAL199: B14_0 Position          */
-#define LCD_PAL199_B14_0_Msk                                  (0x1fUL << LCD_PAL199_B14_0_Pos)                          /*!< LCD PAL199: B14_0 Mask              */
-#define LCD_PAL199_I1_Pos                                     31                                                        /*!< LCD PAL199: I1 Position             */
-#define LCD_PAL199_I1_Msk                                     (0x01UL << LCD_PAL199_I1_Pos)                             /*!< LCD PAL199: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL200  -------------------------------------------
-#define LCD_PAL200_R04_0_Pos                                  0                                                         /*!< LCD PAL200: R04_0 Position          */
-#define LCD_PAL200_R04_0_Msk                                  (0x1fUL << LCD_PAL200_R04_0_Pos)                          /*!< LCD PAL200: R04_0 Mask              */
-#define LCD_PAL200_G04_0_Pos                                  5                                                         /*!< LCD PAL200: G04_0 Position          */
-#define LCD_PAL200_G04_0_Msk                                  (0x1fUL << LCD_PAL200_G04_0_Pos)                          /*!< LCD PAL200: G04_0 Mask              */
-#define LCD_PAL200_B04_0_Pos                                  10                                                        /*!< LCD PAL200: B04_0 Position          */
-#define LCD_PAL200_B04_0_Msk                                  (0x1fUL << LCD_PAL200_B04_0_Pos)                          /*!< LCD PAL200: B04_0 Mask              */
-#define LCD_PAL200_I0_Pos                                     15                                                        /*!< LCD PAL200: I0 Position             */
-#define LCD_PAL200_I0_Msk                                     (0x01UL << LCD_PAL200_I0_Pos)                             /*!< LCD PAL200: I0 Mask                 */
-#define LCD_PAL200_R14_0_Pos                                  16                                                        /*!< LCD PAL200: R14_0 Position          */
-#define LCD_PAL200_R14_0_Msk                                  (0x1fUL << LCD_PAL200_R14_0_Pos)                          /*!< LCD PAL200: R14_0 Mask              */
-#define LCD_PAL200_G14_0_Pos                                  21                                                        /*!< LCD PAL200: G14_0 Position          */
-#define LCD_PAL200_G14_0_Msk                                  (0x1fUL << LCD_PAL200_G14_0_Pos)                          /*!< LCD PAL200: G14_0 Mask              */
-#define LCD_PAL200_B14_0_Pos                                  26                                                        /*!< LCD PAL200: B14_0 Position          */
-#define LCD_PAL200_B14_0_Msk                                  (0x1fUL << LCD_PAL200_B14_0_Pos)                          /*!< LCD PAL200: B14_0 Mask              */
-#define LCD_PAL200_I1_Pos                                     31                                                        /*!< LCD PAL200: I1 Position             */
-#define LCD_PAL200_I1_Msk                                     (0x01UL << LCD_PAL200_I1_Pos)                             /*!< LCD PAL200: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL201  -------------------------------------------
-#define LCD_PAL201_R04_0_Pos                                  0                                                         /*!< LCD PAL201: R04_0 Position          */
-#define LCD_PAL201_R04_0_Msk                                  (0x1fUL << LCD_PAL201_R04_0_Pos)                          /*!< LCD PAL201: R04_0 Mask              */
-#define LCD_PAL201_G04_0_Pos                                  5                                                         /*!< LCD PAL201: G04_0 Position          */
-#define LCD_PAL201_G04_0_Msk                                  (0x1fUL << LCD_PAL201_G04_0_Pos)                          /*!< LCD PAL201: G04_0 Mask              */
-#define LCD_PAL201_B04_0_Pos                                  10                                                        /*!< LCD PAL201: B04_0 Position          */
-#define LCD_PAL201_B04_0_Msk                                  (0x1fUL << LCD_PAL201_B04_0_Pos)                          /*!< LCD PAL201: B04_0 Mask              */
-#define LCD_PAL201_I0_Pos                                     15                                                        /*!< LCD PAL201: I0 Position             */
-#define LCD_PAL201_I0_Msk                                     (0x01UL << LCD_PAL201_I0_Pos)                             /*!< LCD PAL201: I0 Mask                 */
-#define LCD_PAL201_R14_0_Pos                                  16                                                        /*!< LCD PAL201: R14_0 Position          */
-#define LCD_PAL201_R14_0_Msk                                  (0x1fUL << LCD_PAL201_R14_0_Pos)                          /*!< LCD PAL201: R14_0 Mask              */
-#define LCD_PAL201_G14_0_Pos                                  21                                                        /*!< LCD PAL201: G14_0 Position          */
-#define LCD_PAL201_G14_0_Msk                                  (0x1fUL << LCD_PAL201_G14_0_Pos)                          /*!< LCD PAL201: G14_0 Mask              */
-#define LCD_PAL201_B14_0_Pos                                  26                                                        /*!< LCD PAL201: B14_0 Position          */
-#define LCD_PAL201_B14_0_Msk                                  (0x1fUL << LCD_PAL201_B14_0_Pos)                          /*!< LCD PAL201: B14_0 Mask              */
-#define LCD_PAL201_I1_Pos                                     31                                                        /*!< LCD PAL201: I1 Position             */
-#define LCD_PAL201_I1_Msk                                     (0x01UL << LCD_PAL201_I1_Pos)                             /*!< LCD PAL201: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL202  -------------------------------------------
-#define LCD_PAL202_R04_0_Pos                                  0                                                         /*!< LCD PAL202: R04_0 Position          */
-#define LCD_PAL202_R04_0_Msk                                  (0x1fUL << LCD_PAL202_R04_0_Pos)                          /*!< LCD PAL202: R04_0 Mask              */
-#define LCD_PAL202_G04_0_Pos                                  5                                                         /*!< LCD PAL202: G04_0 Position          */
-#define LCD_PAL202_G04_0_Msk                                  (0x1fUL << LCD_PAL202_G04_0_Pos)                          /*!< LCD PAL202: G04_0 Mask              */
-#define LCD_PAL202_B04_0_Pos                                  10                                                        /*!< LCD PAL202: B04_0 Position          */
-#define LCD_PAL202_B04_0_Msk                                  (0x1fUL << LCD_PAL202_B04_0_Pos)                          /*!< LCD PAL202: B04_0 Mask              */
-#define LCD_PAL202_I0_Pos                                     15                                                        /*!< LCD PAL202: I0 Position             */
-#define LCD_PAL202_I0_Msk                                     (0x01UL << LCD_PAL202_I0_Pos)                             /*!< LCD PAL202: I0 Mask                 */
-#define LCD_PAL202_R14_0_Pos                                  16                                                        /*!< LCD PAL202: R14_0 Position          */
-#define LCD_PAL202_R14_0_Msk                                  (0x1fUL << LCD_PAL202_R14_0_Pos)                          /*!< LCD PAL202: R14_0 Mask              */
-#define LCD_PAL202_G14_0_Pos                                  21                                                        /*!< LCD PAL202: G14_0 Position          */
-#define LCD_PAL202_G14_0_Msk                                  (0x1fUL << LCD_PAL202_G14_0_Pos)                          /*!< LCD PAL202: G14_0 Mask              */
-#define LCD_PAL202_B14_0_Pos                                  26                                                        /*!< LCD PAL202: B14_0 Position          */
-#define LCD_PAL202_B14_0_Msk                                  (0x1fUL << LCD_PAL202_B14_0_Pos)                          /*!< LCD PAL202: B14_0 Mask              */
-#define LCD_PAL202_I1_Pos                                     31                                                        /*!< LCD PAL202: I1 Position             */
-#define LCD_PAL202_I1_Msk                                     (0x01UL << LCD_PAL202_I1_Pos)                             /*!< LCD PAL202: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL203  -------------------------------------------
-#define LCD_PAL203_R04_0_Pos                                  0                                                         /*!< LCD PAL203: R04_0 Position          */
-#define LCD_PAL203_R04_0_Msk                                  (0x1fUL << LCD_PAL203_R04_0_Pos)                          /*!< LCD PAL203: R04_0 Mask              */
-#define LCD_PAL203_G04_0_Pos                                  5                                                         /*!< LCD PAL203: G04_0 Position          */
-#define LCD_PAL203_G04_0_Msk                                  (0x1fUL << LCD_PAL203_G04_0_Pos)                          /*!< LCD PAL203: G04_0 Mask              */
-#define LCD_PAL203_B04_0_Pos                                  10                                                        /*!< LCD PAL203: B04_0 Position          */
-#define LCD_PAL203_B04_0_Msk                                  (0x1fUL << LCD_PAL203_B04_0_Pos)                          /*!< LCD PAL203: B04_0 Mask              */
-#define LCD_PAL203_I0_Pos                                     15                                                        /*!< LCD PAL203: I0 Position             */
-#define LCD_PAL203_I0_Msk                                     (0x01UL << LCD_PAL203_I0_Pos)                             /*!< LCD PAL203: I0 Mask                 */
-#define LCD_PAL203_R14_0_Pos                                  16                                                        /*!< LCD PAL203: R14_0 Position          */
-#define LCD_PAL203_R14_0_Msk                                  (0x1fUL << LCD_PAL203_R14_0_Pos)                          /*!< LCD PAL203: R14_0 Mask              */
-#define LCD_PAL203_G14_0_Pos                                  21                                                        /*!< LCD PAL203: G14_0 Position          */
-#define LCD_PAL203_G14_0_Msk                                  (0x1fUL << LCD_PAL203_G14_0_Pos)                          /*!< LCD PAL203: G14_0 Mask              */
-#define LCD_PAL203_B14_0_Pos                                  26                                                        /*!< LCD PAL203: B14_0 Position          */
-#define LCD_PAL203_B14_0_Msk                                  (0x1fUL << LCD_PAL203_B14_0_Pos)                          /*!< LCD PAL203: B14_0 Mask              */
-#define LCD_PAL203_I1_Pos                                     31                                                        /*!< LCD PAL203: I1 Position             */
-#define LCD_PAL203_I1_Msk                                     (0x01UL << LCD_PAL203_I1_Pos)                             /*!< LCD PAL203: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL204  -------------------------------------------
-#define LCD_PAL204_R04_0_Pos                                  0                                                         /*!< LCD PAL204: R04_0 Position          */
-#define LCD_PAL204_R04_0_Msk                                  (0x1fUL << LCD_PAL204_R04_0_Pos)                          /*!< LCD PAL204: R04_0 Mask              */
-#define LCD_PAL204_G04_0_Pos                                  5                                                         /*!< LCD PAL204: G04_0 Position          */
-#define LCD_PAL204_G04_0_Msk                                  (0x1fUL << LCD_PAL204_G04_0_Pos)                          /*!< LCD PAL204: G04_0 Mask              */
-#define LCD_PAL204_B04_0_Pos                                  10                                                        /*!< LCD PAL204: B04_0 Position          */
-#define LCD_PAL204_B04_0_Msk                                  (0x1fUL << LCD_PAL204_B04_0_Pos)                          /*!< LCD PAL204: B04_0 Mask              */
-#define LCD_PAL204_I0_Pos                                     15                                                        /*!< LCD PAL204: I0 Position             */
-#define LCD_PAL204_I0_Msk                                     (0x01UL << LCD_PAL204_I0_Pos)                             /*!< LCD PAL204: I0 Mask                 */
-#define LCD_PAL204_R14_0_Pos                                  16                                                        /*!< LCD PAL204: R14_0 Position          */
-#define LCD_PAL204_R14_0_Msk                                  (0x1fUL << LCD_PAL204_R14_0_Pos)                          /*!< LCD PAL204: R14_0 Mask              */
-#define LCD_PAL204_G14_0_Pos                                  21                                                        /*!< LCD PAL204: G14_0 Position          */
-#define LCD_PAL204_G14_0_Msk                                  (0x1fUL << LCD_PAL204_G14_0_Pos)                          /*!< LCD PAL204: G14_0 Mask              */
-#define LCD_PAL204_B14_0_Pos                                  26                                                        /*!< LCD PAL204: B14_0 Position          */
-#define LCD_PAL204_B14_0_Msk                                  (0x1fUL << LCD_PAL204_B14_0_Pos)                          /*!< LCD PAL204: B14_0 Mask              */
-#define LCD_PAL204_I1_Pos                                     31                                                        /*!< LCD PAL204: I1 Position             */
-#define LCD_PAL204_I1_Msk                                     (0x01UL << LCD_PAL204_I1_Pos)                             /*!< LCD PAL204: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL205  -------------------------------------------
-#define LCD_PAL205_R04_0_Pos                                  0                                                         /*!< LCD PAL205: R04_0 Position          */
-#define LCD_PAL205_R04_0_Msk                                  (0x1fUL << LCD_PAL205_R04_0_Pos)                          /*!< LCD PAL205: R04_0 Mask              */
-#define LCD_PAL205_G04_0_Pos                                  5                                                         /*!< LCD PAL205: G04_0 Position          */
-#define LCD_PAL205_G04_0_Msk                                  (0x1fUL << LCD_PAL205_G04_0_Pos)                          /*!< LCD PAL205: G04_0 Mask              */
-#define LCD_PAL205_B04_0_Pos                                  10                                                        /*!< LCD PAL205: B04_0 Position          */
-#define LCD_PAL205_B04_0_Msk                                  (0x1fUL << LCD_PAL205_B04_0_Pos)                          /*!< LCD PAL205: B04_0 Mask              */
-#define LCD_PAL205_I0_Pos                                     15                                                        /*!< LCD PAL205: I0 Position             */
-#define LCD_PAL205_I0_Msk                                     (0x01UL << LCD_PAL205_I0_Pos)                             /*!< LCD PAL205: I0 Mask                 */
-#define LCD_PAL205_R14_0_Pos                                  16                                                        /*!< LCD PAL205: R14_0 Position          */
-#define LCD_PAL205_R14_0_Msk                                  (0x1fUL << LCD_PAL205_R14_0_Pos)                          /*!< LCD PAL205: R14_0 Mask              */
-#define LCD_PAL205_G14_0_Pos                                  21                                                        /*!< LCD PAL205: G14_0 Position          */
-#define LCD_PAL205_G14_0_Msk                                  (0x1fUL << LCD_PAL205_G14_0_Pos)                          /*!< LCD PAL205: G14_0 Mask              */
-#define LCD_PAL205_B14_0_Pos                                  26                                                        /*!< LCD PAL205: B14_0 Position          */
-#define LCD_PAL205_B14_0_Msk                                  (0x1fUL << LCD_PAL205_B14_0_Pos)                          /*!< LCD PAL205: B14_0 Mask              */
-#define LCD_PAL205_I1_Pos                                     31                                                        /*!< LCD PAL205: I1 Position             */
-#define LCD_PAL205_I1_Msk                                     (0x01UL << LCD_PAL205_I1_Pos)                             /*!< LCD PAL205: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL206  -------------------------------------------
-#define LCD_PAL206_R04_0_Pos                                  0                                                         /*!< LCD PAL206: R04_0 Position          */
-#define LCD_PAL206_R04_0_Msk                                  (0x1fUL << LCD_PAL206_R04_0_Pos)                          /*!< LCD PAL206: R04_0 Mask              */
-#define LCD_PAL206_G04_0_Pos                                  5                                                         /*!< LCD PAL206: G04_0 Position          */
-#define LCD_PAL206_G04_0_Msk                                  (0x1fUL << LCD_PAL206_G04_0_Pos)                          /*!< LCD PAL206: G04_0 Mask              */
-#define LCD_PAL206_B04_0_Pos                                  10                                                        /*!< LCD PAL206: B04_0 Position          */
-#define LCD_PAL206_B04_0_Msk                                  (0x1fUL << LCD_PAL206_B04_0_Pos)                          /*!< LCD PAL206: B04_0 Mask              */
-#define LCD_PAL206_I0_Pos                                     15                                                        /*!< LCD PAL206: I0 Position             */
-#define LCD_PAL206_I0_Msk                                     (0x01UL << LCD_PAL206_I0_Pos)                             /*!< LCD PAL206: I0 Mask                 */
-#define LCD_PAL206_R14_0_Pos                                  16                                                        /*!< LCD PAL206: R14_0 Position          */
-#define LCD_PAL206_R14_0_Msk                                  (0x1fUL << LCD_PAL206_R14_0_Pos)                          /*!< LCD PAL206: R14_0 Mask              */
-#define LCD_PAL206_G14_0_Pos                                  21                                                        /*!< LCD PAL206: G14_0 Position          */
-#define LCD_PAL206_G14_0_Msk                                  (0x1fUL << LCD_PAL206_G14_0_Pos)                          /*!< LCD PAL206: G14_0 Mask              */
-#define LCD_PAL206_B14_0_Pos                                  26                                                        /*!< LCD PAL206: B14_0 Position          */
-#define LCD_PAL206_B14_0_Msk                                  (0x1fUL << LCD_PAL206_B14_0_Pos)                          /*!< LCD PAL206: B14_0 Mask              */
-#define LCD_PAL206_I1_Pos                                     31                                                        /*!< LCD PAL206: I1 Position             */
-#define LCD_PAL206_I1_Msk                                     (0x01UL << LCD_PAL206_I1_Pos)                             /*!< LCD PAL206: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL207  -------------------------------------------
-#define LCD_PAL207_R04_0_Pos                                  0                                                         /*!< LCD PAL207: R04_0 Position          */
-#define LCD_PAL207_R04_0_Msk                                  (0x1fUL << LCD_PAL207_R04_0_Pos)                          /*!< LCD PAL207: R04_0 Mask              */
-#define LCD_PAL207_G04_0_Pos                                  5                                                         /*!< LCD PAL207: G04_0 Position          */
-#define LCD_PAL207_G04_0_Msk                                  (0x1fUL << LCD_PAL207_G04_0_Pos)                          /*!< LCD PAL207: G04_0 Mask              */
-#define LCD_PAL207_B04_0_Pos                                  10                                                        /*!< LCD PAL207: B04_0 Position          */
-#define LCD_PAL207_B04_0_Msk                                  (0x1fUL << LCD_PAL207_B04_0_Pos)                          /*!< LCD PAL207: B04_0 Mask              */
-#define LCD_PAL207_I0_Pos                                     15                                                        /*!< LCD PAL207: I0 Position             */
-#define LCD_PAL207_I0_Msk                                     (0x01UL << LCD_PAL207_I0_Pos)                             /*!< LCD PAL207: I0 Mask                 */
-#define LCD_PAL207_R14_0_Pos                                  16                                                        /*!< LCD PAL207: R14_0 Position          */
-#define LCD_PAL207_R14_0_Msk                                  (0x1fUL << LCD_PAL207_R14_0_Pos)                          /*!< LCD PAL207: R14_0 Mask              */
-#define LCD_PAL207_G14_0_Pos                                  21                                                        /*!< LCD PAL207: G14_0 Position          */
-#define LCD_PAL207_G14_0_Msk                                  (0x1fUL << LCD_PAL207_G14_0_Pos)                          /*!< LCD PAL207: G14_0 Mask              */
-#define LCD_PAL207_B14_0_Pos                                  26                                                        /*!< LCD PAL207: B14_0 Position          */
-#define LCD_PAL207_B14_0_Msk                                  (0x1fUL << LCD_PAL207_B14_0_Pos)                          /*!< LCD PAL207: B14_0 Mask              */
-#define LCD_PAL207_I1_Pos                                     31                                                        /*!< LCD PAL207: I1 Position             */
-#define LCD_PAL207_I1_Msk                                     (0x01UL << LCD_PAL207_I1_Pos)                             /*!< LCD PAL207: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL208  -------------------------------------------
-#define LCD_PAL208_R04_0_Pos                                  0                                                         /*!< LCD PAL208: R04_0 Position          */
-#define LCD_PAL208_R04_0_Msk                                  (0x1fUL << LCD_PAL208_R04_0_Pos)                          /*!< LCD PAL208: R04_0 Mask              */
-#define LCD_PAL208_G04_0_Pos                                  5                                                         /*!< LCD PAL208: G04_0 Position          */
-#define LCD_PAL208_G04_0_Msk                                  (0x1fUL << LCD_PAL208_G04_0_Pos)                          /*!< LCD PAL208: G04_0 Mask              */
-#define LCD_PAL208_B04_0_Pos                                  10                                                        /*!< LCD PAL208: B04_0 Position          */
-#define LCD_PAL208_B04_0_Msk                                  (0x1fUL << LCD_PAL208_B04_0_Pos)                          /*!< LCD PAL208: B04_0 Mask              */
-#define LCD_PAL208_I0_Pos                                     15                                                        /*!< LCD PAL208: I0 Position             */
-#define LCD_PAL208_I0_Msk                                     (0x01UL << LCD_PAL208_I0_Pos)                             /*!< LCD PAL208: I0 Mask                 */
-#define LCD_PAL208_R14_0_Pos                                  16                                                        /*!< LCD PAL208: R14_0 Position          */
-#define LCD_PAL208_R14_0_Msk                                  (0x1fUL << LCD_PAL208_R14_0_Pos)                          /*!< LCD PAL208: R14_0 Mask              */
-#define LCD_PAL208_G14_0_Pos                                  21                                                        /*!< LCD PAL208: G14_0 Position          */
-#define LCD_PAL208_G14_0_Msk                                  (0x1fUL << LCD_PAL208_G14_0_Pos)                          /*!< LCD PAL208: G14_0 Mask              */
-#define LCD_PAL208_B14_0_Pos                                  26                                                        /*!< LCD PAL208: B14_0 Position          */
-#define LCD_PAL208_B14_0_Msk                                  (0x1fUL << LCD_PAL208_B14_0_Pos)                          /*!< LCD PAL208: B14_0 Mask              */
-#define LCD_PAL208_I1_Pos                                     31                                                        /*!< LCD PAL208: I1 Position             */
-#define LCD_PAL208_I1_Msk                                     (0x01UL << LCD_PAL208_I1_Pos)                             /*!< LCD PAL208: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL209  -------------------------------------------
-#define LCD_PAL209_R04_0_Pos                                  0                                                         /*!< LCD PAL209: R04_0 Position          */
-#define LCD_PAL209_R04_0_Msk                                  (0x1fUL << LCD_PAL209_R04_0_Pos)                          /*!< LCD PAL209: R04_0 Mask              */
-#define LCD_PAL209_G04_0_Pos                                  5                                                         /*!< LCD PAL209: G04_0 Position          */
-#define LCD_PAL209_G04_0_Msk                                  (0x1fUL << LCD_PAL209_G04_0_Pos)                          /*!< LCD PAL209: G04_0 Mask              */
-#define LCD_PAL209_B04_0_Pos                                  10                                                        /*!< LCD PAL209: B04_0 Position          */
-#define LCD_PAL209_B04_0_Msk                                  (0x1fUL << LCD_PAL209_B04_0_Pos)                          /*!< LCD PAL209: B04_0 Mask              */
-#define LCD_PAL209_I0_Pos                                     15                                                        /*!< LCD PAL209: I0 Position             */
-#define LCD_PAL209_I0_Msk                                     (0x01UL << LCD_PAL209_I0_Pos)                             /*!< LCD PAL209: I0 Mask                 */
-#define LCD_PAL209_R14_0_Pos                                  16                                                        /*!< LCD PAL209: R14_0 Position          */
-#define LCD_PAL209_R14_0_Msk                                  (0x1fUL << LCD_PAL209_R14_0_Pos)                          /*!< LCD PAL209: R14_0 Mask              */
-#define LCD_PAL209_G14_0_Pos                                  21                                                        /*!< LCD PAL209: G14_0 Position          */
-#define LCD_PAL209_G14_0_Msk                                  (0x1fUL << LCD_PAL209_G14_0_Pos)                          /*!< LCD PAL209: G14_0 Mask              */
-#define LCD_PAL209_B14_0_Pos                                  26                                                        /*!< LCD PAL209: B14_0 Position          */
-#define LCD_PAL209_B14_0_Msk                                  (0x1fUL << LCD_PAL209_B14_0_Pos)                          /*!< LCD PAL209: B14_0 Mask              */
-#define LCD_PAL209_I1_Pos                                     31                                                        /*!< LCD PAL209: I1 Position             */
-#define LCD_PAL209_I1_Msk                                     (0x01UL << LCD_PAL209_I1_Pos)                             /*!< LCD PAL209: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL210  -------------------------------------------
-#define LCD_PAL210_R04_0_Pos                                  0                                                         /*!< LCD PAL210: R04_0 Position          */
-#define LCD_PAL210_R04_0_Msk                                  (0x1fUL << LCD_PAL210_R04_0_Pos)                          /*!< LCD PAL210: R04_0 Mask              */
-#define LCD_PAL210_G04_0_Pos                                  5                                                         /*!< LCD PAL210: G04_0 Position          */
-#define LCD_PAL210_G04_0_Msk                                  (0x1fUL << LCD_PAL210_G04_0_Pos)                          /*!< LCD PAL210: G04_0 Mask              */
-#define LCD_PAL210_B04_0_Pos                                  10                                                        /*!< LCD PAL210: B04_0 Position          */
-#define LCD_PAL210_B04_0_Msk                                  (0x1fUL << LCD_PAL210_B04_0_Pos)                          /*!< LCD PAL210: B04_0 Mask              */
-#define LCD_PAL210_I0_Pos                                     15                                                        /*!< LCD PAL210: I0 Position             */
-#define LCD_PAL210_I0_Msk                                     (0x01UL << LCD_PAL210_I0_Pos)                             /*!< LCD PAL210: I0 Mask                 */
-#define LCD_PAL210_R14_0_Pos                                  16                                                        /*!< LCD PAL210: R14_0 Position          */
-#define LCD_PAL210_R14_0_Msk                                  (0x1fUL << LCD_PAL210_R14_0_Pos)                          /*!< LCD PAL210: R14_0 Mask              */
-#define LCD_PAL210_G14_0_Pos                                  21                                                        /*!< LCD PAL210: G14_0 Position          */
-#define LCD_PAL210_G14_0_Msk                                  (0x1fUL << LCD_PAL210_G14_0_Pos)                          /*!< LCD PAL210: G14_0 Mask              */
-#define LCD_PAL210_B14_0_Pos                                  26                                                        /*!< LCD PAL210: B14_0 Position          */
-#define LCD_PAL210_B14_0_Msk                                  (0x1fUL << LCD_PAL210_B14_0_Pos)                          /*!< LCD PAL210: B14_0 Mask              */
-#define LCD_PAL210_I1_Pos                                     31                                                        /*!< LCD PAL210: I1 Position             */
-#define LCD_PAL210_I1_Msk                                     (0x01UL << LCD_PAL210_I1_Pos)                             /*!< LCD PAL210: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL211  -------------------------------------------
-#define LCD_PAL211_R04_0_Pos                                  0                                                         /*!< LCD PAL211: R04_0 Position          */
-#define LCD_PAL211_R04_0_Msk                                  (0x1fUL << LCD_PAL211_R04_0_Pos)                          /*!< LCD PAL211: R04_0 Mask              */
-#define LCD_PAL211_G04_0_Pos                                  5                                                         /*!< LCD PAL211: G04_0 Position          */
-#define LCD_PAL211_G04_0_Msk                                  (0x1fUL << LCD_PAL211_G04_0_Pos)                          /*!< LCD PAL211: G04_0 Mask              */
-#define LCD_PAL211_B04_0_Pos                                  10                                                        /*!< LCD PAL211: B04_0 Position          */
-#define LCD_PAL211_B04_0_Msk                                  (0x1fUL << LCD_PAL211_B04_0_Pos)                          /*!< LCD PAL211: B04_0 Mask              */
-#define LCD_PAL211_I0_Pos                                     15                                                        /*!< LCD PAL211: I0 Position             */
-#define LCD_PAL211_I0_Msk                                     (0x01UL << LCD_PAL211_I0_Pos)                             /*!< LCD PAL211: I0 Mask                 */
-#define LCD_PAL211_R14_0_Pos                                  16                                                        /*!< LCD PAL211: R14_0 Position          */
-#define LCD_PAL211_R14_0_Msk                                  (0x1fUL << LCD_PAL211_R14_0_Pos)                          /*!< LCD PAL211: R14_0 Mask              */
-#define LCD_PAL211_G14_0_Pos                                  21                                                        /*!< LCD PAL211: G14_0 Position          */
-#define LCD_PAL211_G14_0_Msk                                  (0x1fUL << LCD_PAL211_G14_0_Pos)                          /*!< LCD PAL211: G14_0 Mask              */
-#define LCD_PAL211_B14_0_Pos                                  26                                                        /*!< LCD PAL211: B14_0 Position          */
-#define LCD_PAL211_B14_0_Msk                                  (0x1fUL << LCD_PAL211_B14_0_Pos)                          /*!< LCD PAL211: B14_0 Mask              */
-#define LCD_PAL211_I1_Pos                                     31                                                        /*!< LCD PAL211: I1 Position             */
-#define LCD_PAL211_I1_Msk                                     (0x01UL << LCD_PAL211_I1_Pos)                             /*!< LCD PAL211: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL212  -------------------------------------------
-#define LCD_PAL212_R04_0_Pos                                  0                                                         /*!< LCD PAL212: R04_0 Position          */
-#define LCD_PAL212_R04_0_Msk                                  (0x1fUL << LCD_PAL212_R04_0_Pos)                          /*!< LCD PAL212: R04_0 Mask              */
-#define LCD_PAL212_G04_0_Pos                                  5                                                         /*!< LCD PAL212: G04_0 Position          */
-#define LCD_PAL212_G04_0_Msk                                  (0x1fUL << LCD_PAL212_G04_0_Pos)                          /*!< LCD PAL212: G04_0 Mask              */
-#define LCD_PAL212_B04_0_Pos                                  10                                                        /*!< LCD PAL212: B04_0 Position          */
-#define LCD_PAL212_B04_0_Msk                                  (0x1fUL << LCD_PAL212_B04_0_Pos)                          /*!< LCD PAL212: B04_0 Mask              */
-#define LCD_PAL212_I0_Pos                                     15                                                        /*!< LCD PAL212: I0 Position             */
-#define LCD_PAL212_I0_Msk                                     (0x01UL << LCD_PAL212_I0_Pos)                             /*!< LCD PAL212: I0 Mask                 */
-#define LCD_PAL212_R14_0_Pos                                  16                                                        /*!< LCD PAL212: R14_0 Position          */
-#define LCD_PAL212_R14_0_Msk                                  (0x1fUL << LCD_PAL212_R14_0_Pos)                          /*!< LCD PAL212: R14_0 Mask              */
-#define LCD_PAL212_G14_0_Pos                                  21                                                        /*!< LCD PAL212: G14_0 Position          */
-#define LCD_PAL212_G14_0_Msk                                  (0x1fUL << LCD_PAL212_G14_0_Pos)                          /*!< LCD PAL212: G14_0 Mask              */
-#define LCD_PAL212_B14_0_Pos                                  26                                                        /*!< LCD PAL212: B14_0 Position          */
-#define LCD_PAL212_B14_0_Msk                                  (0x1fUL << LCD_PAL212_B14_0_Pos)                          /*!< LCD PAL212: B14_0 Mask              */
-#define LCD_PAL212_I1_Pos                                     31                                                        /*!< LCD PAL212: I1 Position             */
-#define LCD_PAL212_I1_Msk                                     (0x01UL << LCD_PAL212_I1_Pos)                             /*!< LCD PAL212: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL213  -------------------------------------------
-#define LCD_PAL213_R04_0_Pos                                  0                                                         /*!< LCD PAL213: R04_0 Position          */
-#define LCD_PAL213_R04_0_Msk                                  (0x1fUL << LCD_PAL213_R04_0_Pos)                          /*!< LCD PAL213: R04_0 Mask              */
-#define LCD_PAL213_G04_0_Pos                                  5                                                         /*!< LCD PAL213: G04_0 Position          */
-#define LCD_PAL213_G04_0_Msk                                  (0x1fUL << LCD_PAL213_G04_0_Pos)                          /*!< LCD PAL213: G04_0 Mask              */
-#define LCD_PAL213_B04_0_Pos                                  10                                                        /*!< LCD PAL213: B04_0 Position          */
-#define LCD_PAL213_B04_0_Msk                                  (0x1fUL << LCD_PAL213_B04_0_Pos)                          /*!< LCD PAL213: B04_0 Mask              */
-#define LCD_PAL213_I0_Pos                                     15                                                        /*!< LCD PAL213: I0 Position             */
-#define LCD_PAL213_I0_Msk                                     (0x01UL << LCD_PAL213_I0_Pos)                             /*!< LCD PAL213: I0 Mask                 */
-#define LCD_PAL213_R14_0_Pos                                  16                                                        /*!< LCD PAL213: R14_0 Position          */
-#define LCD_PAL213_R14_0_Msk                                  (0x1fUL << LCD_PAL213_R14_0_Pos)                          /*!< LCD PAL213: R14_0 Mask              */
-#define LCD_PAL213_G14_0_Pos                                  21                                                        /*!< LCD PAL213: G14_0 Position          */
-#define LCD_PAL213_G14_0_Msk                                  (0x1fUL << LCD_PAL213_G14_0_Pos)                          /*!< LCD PAL213: G14_0 Mask              */
-#define LCD_PAL213_B14_0_Pos                                  26                                                        /*!< LCD PAL213: B14_0 Position          */
-#define LCD_PAL213_B14_0_Msk                                  (0x1fUL << LCD_PAL213_B14_0_Pos)                          /*!< LCD PAL213: B14_0 Mask              */
-#define LCD_PAL213_I1_Pos                                     31                                                        /*!< LCD PAL213: I1 Position             */
-#define LCD_PAL213_I1_Msk                                     (0x01UL << LCD_PAL213_I1_Pos)                             /*!< LCD PAL213: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL214  -------------------------------------------
-#define LCD_PAL214_R04_0_Pos                                  0                                                         /*!< LCD PAL214: R04_0 Position          */
-#define LCD_PAL214_R04_0_Msk                                  (0x1fUL << LCD_PAL214_R04_0_Pos)                          /*!< LCD PAL214: R04_0 Mask              */
-#define LCD_PAL214_G04_0_Pos                                  5                                                         /*!< LCD PAL214: G04_0 Position          */
-#define LCD_PAL214_G04_0_Msk                                  (0x1fUL << LCD_PAL214_G04_0_Pos)                          /*!< LCD PAL214: G04_0 Mask              */
-#define LCD_PAL214_B04_0_Pos                                  10                                                        /*!< LCD PAL214: B04_0 Position          */
-#define LCD_PAL214_B04_0_Msk                                  (0x1fUL << LCD_PAL214_B04_0_Pos)                          /*!< LCD PAL214: B04_0 Mask              */
-#define LCD_PAL214_I0_Pos                                     15                                                        /*!< LCD PAL214: I0 Position             */
-#define LCD_PAL214_I0_Msk                                     (0x01UL << LCD_PAL214_I0_Pos)                             /*!< LCD PAL214: I0 Mask                 */
-#define LCD_PAL214_R14_0_Pos                                  16                                                        /*!< LCD PAL214: R14_0 Position          */
-#define LCD_PAL214_R14_0_Msk                                  (0x1fUL << LCD_PAL214_R14_0_Pos)                          /*!< LCD PAL214: R14_0 Mask              */
-#define LCD_PAL214_G14_0_Pos                                  21                                                        /*!< LCD PAL214: G14_0 Position          */
-#define LCD_PAL214_G14_0_Msk                                  (0x1fUL << LCD_PAL214_G14_0_Pos)                          /*!< LCD PAL214: G14_0 Mask              */
-#define LCD_PAL214_B14_0_Pos                                  26                                                        /*!< LCD PAL214: B14_0 Position          */
-#define LCD_PAL214_B14_0_Msk                                  (0x1fUL << LCD_PAL214_B14_0_Pos)                          /*!< LCD PAL214: B14_0 Mask              */
-#define LCD_PAL214_I1_Pos                                     31                                                        /*!< LCD PAL214: I1 Position             */
-#define LCD_PAL214_I1_Msk                                     (0x01UL << LCD_PAL214_I1_Pos)                             /*!< LCD PAL214: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL215  -------------------------------------------
-#define LCD_PAL215_R04_0_Pos                                  0                                                         /*!< LCD PAL215: R04_0 Position          */
-#define LCD_PAL215_R04_0_Msk                                  (0x1fUL << LCD_PAL215_R04_0_Pos)                          /*!< LCD PAL215: R04_0 Mask              */
-#define LCD_PAL215_G04_0_Pos                                  5                                                         /*!< LCD PAL215: G04_0 Position          */
-#define LCD_PAL215_G04_0_Msk                                  (0x1fUL << LCD_PAL215_G04_0_Pos)                          /*!< LCD PAL215: G04_0 Mask              */
-#define LCD_PAL215_B04_0_Pos                                  10                                                        /*!< LCD PAL215: B04_0 Position          */
-#define LCD_PAL215_B04_0_Msk                                  (0x1fUL << LCD_PAL215_B04_0_Pos)                          /*!< LCD PAL215: B04_0 Mask              */
-#define LCD_PAL215_I0_Pos                                     15                                                        /*!< LCD PAL215: I0 Position             */
-#define LCD_PAL215_I0_Msk                                     (0x01UL << LCD_PAL215_I0_Pos)                             /*!< LCD PAL215: I0 Mask                 */
-#define LCD_PAL215_R14_0_Pos                                  16                                                        /*!< LCD PAL215: R14_0 Position          */
-#define LCD_PAL215_R14_0_Msk                                  (0x1fUL << LCD_PAL215_R14_0_Pos)                          /*!< LCD PAL215: R14_0 Mask              */
-#define LCD_PAL215_G14_0_Pos                                  21                                                        /*!< LCD PAL215: G14_0 Position          */
-#define LCD_PAL215_G14_0_Msk                                  (0x1fUL << LCD_PAL215_G14_0_Pos)                          /*!< LCD PAL215: G14_0 Mask              */
-#define LCD_PAL215_B14_0_Pos                                  26                                                        /*!< LCD PAL215: B14_0 Position          */
-#define LCD_PAL215_B14_0_Msk                                  (0x1fUL << LCD_PAL215_B14_0_Pos)                          /*!< LCD PAL215: B14_0 Mask              */
-#define LCD_PAL215_I1_Pos                                     31                                                        /*!< LCD PAL215: I1 Position             */
-#define LCD_PAL215_I1_Msk                                     (0x01UL << LCD_PAL215_I1_Pos)                             /*!< LCD PAL215: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL216  -------------------------------------------
-#define LCD_PAL216_R04_0_Pos                                  0                                                         /*!< LCD PAL216: R04_0 Position          */
-#define LCD_PAL216_R04_0_Msk                                  (0x1fUL << LCD_PAL216_R04_0_Pos)                          /*!< LCD PAL216: R04_0 Mask              */
-#define LCD_PAL216_G04_0_Pos                                  5                                                         /*!< LCD PAL216: G04_0 Position          */
-#define LCD_PAL216_G04_0_Msk                                  (0x1fUL << LCD_PAL216_G04_0_Pos)                          /*!< LCD PAL216: G04_0 Mask              */
-#define LCD_PAL216_B04_0_Pos                                  10                                                        /*!< LCD PAL216: B04_0 Position          */
-#define LCD_PAL216_B04_0_Msk                                  (0x1fUL << LCD_PAL216_B04_0_Pos)                          /*!< LCD PAL216: B04_0 Mask              */
-#define LCD_PAL216_I0_Pos                                     15                                                        /*!< LCD PAL216: I0 Position             */
-#define LCD_PAL216_I0_Msk                                     (0x01UL << LCD_PAL216_I0_Pos)                             /*!< LCD PAL216: I0 Mask                 */
-#define LCD_PAL216_R14_0_Pos                                  16                                                        /*!< LCD PAL216: R14_0 Position          */
-#define LCD_PAL216_R14_0_Msk                                  (0x1fUL << LCD_PAL216_R14_0_Pos)                          /*!< LCD PAL216: R14_0 Mask              */
-#define LCD_PAL216_G14_0_Pos                                  21                                                        /*!< LCD PAL216: G14_0 Position          */
-#define LCD_PAL216_G14_0_Msk                                  (0x1fUL << LCD_PAL216_G14_0_Pos)                          /*!< LCD PAL216: G14_0 Mask              */
-#define LCD_PAL216_B14_0_Pos                                  26                                                        /*!< LCD PAL216: B14_0 Position          */
-#define LCD_PAL216_B14_0_Msk                                  (0x1fUL << LCD_PAL216_B14_0_Pos)                          /*!< LCD PAL216: B14_0 Mask              */
-#define LCD_PAL216_I1_Pos                                     31                                                        /*!< LCD PAL216: I1 Position             */
-#define LCD_PAL216_I1_Msk                                     (0x01UL << LCD_PAL216_I1_Pos)                             /*!< LCD PAL216: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL217  -------------------------------------------
-#define LCD_PAL217_R04_0_Pos                                  0                                                         /*!< LCD PAL217: R04_0 Position          */
-#define LCD_PAL217_R04_0_Msk                                  (0x1fUL << LCD_PAL217_R04_0_Pos)                          /*!< LCD PAL217: R04_0 Mask              */
-#define LCD_PAL217_G04_0_Pos                                  5                                                         /*!< LCD PAL217: G04_0 Position          */
-#define LCD_PAL217_G04_0_Msk                                  (0x1fUL << LCD_PAL217_G04_0_Pos)                          /*!< LCD PAL217: G04_0 Mask              */
-#define LCD_PAL217_B04_0_Pos                                  10                                                        /*!< LCD PAL217: B04_0 Position          */
-#define LCD_PAL217_B04_0_Msk                                  (0x1fUL << LCD_PAL217_B04_0_Pos)                          /*!< LCD PAL217: B04_0 Mask              */
-#define LCD_PAL217_I0_Pos                                     15                                                        /*!< LCD PAL217: I0 Position             */
-#define LCD_PAL217_I0_Msk                                     (0x01UL << LCD_PAL217_I0_Pos)                             /*!< LCD PAL217: I0 Mask                 */
-#define LCD_PAL217_R14_0_Pos                                  16                                                        /*!< LCD PAL217: R14_0 Position          */
-#define LCD_PAL217_R14_0_Msk                                  (0x1fUL << LCD_PAL217_R14_0_Pos)                          /*!< LCD PAL217: R14_0 Mask              */
-#define LCD_PAL217_G14_0_Pos                                  21                                                        /*!< LCD PAL217: G14_0 Position          */
-#define LCD_PAL217_G14_0_Msk                                  (0x1fUL << LCD_PAL217_G14_0_Pos)                          /*!< LCD PAL217: G14_0 Mask              */
-#define LCD_PAL217_B14_0_Pos                                  26                                                        /*!< LCD PAL217: B14_0 Position          */
-#define LCD_PAL217_B14_0_Msk                                  (0x1fUL << LCD_PAL217_B14_0_Pos)                          /*!< LCD PAL217: B14_0 Mask              */
-#define LCD_PAL217_I1_Pos                                     31                                                        /*!< LCD PAL217: I1 Position             */
-#define LCD_PAL217_I1_Msk                                     (0x01UL << LCD_PAL217_I1_Pos)                             /*!< LCD PAL217: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL218  -------------------------------------------
-#define LCD_PAL218_R04_0_Pos                                  0                                                         /*!< LCD PAL218: R04_0 Position          */
-#define LCD_PAL218_R04_0_Msk                                  (0x1fUL << LCD_PAL218_R04_0_Pos)                          /*!< LCD PAL218: R04_0 Mask              */
-#define LCD_PAL218_G04_0_Pos                                  5                                                         /*!< LCD PAL218: G04_0 Position          */
-#define LCD_PAL218_G04_0_Msk                                  (0x1fUL << LCD_PAL218_G04_0_Pos)                          /*!< LCD PAL218: G04_0 Mask              */
-#define LCD_PAL218_B04_0_Pos                                  10                                                        /*!< LCD PAL218: B04_0 Position          */
-#define LCD_PAL218_B04_0_Msk                                  (0x1fUL << LCD_PAL218_B04_0_Pos)                          /*!< LCD PAL218: B04_0 Mask              */
-#define LCD_PAL218_I0_Pos                                     15                                                        /*!< LCD PAL218: I0 Position             */
-#define LCD_PAL218_I0_Msk                                     (0x01UL << LCD_PAL218_I0_Pos)                             /*!< LCD PAL218: I0 Mask                 */
-#define LCD_PAL218_R14_0_Pos                                  16                                                        /*!< LCD PAL218: R14_0 Position          */
-#define LCD_PAL218_R14_0_Msk                                  (0x1fUL << LCD_PAL218_R14_0_Pos)                          /*!< LCD PAL218: R14_0 Mask              */
-#define LCD_PAL218_G14_0_Pos                                  21                                                        /*!< LCD PAL218: G14_0 Position          */
-#define LCD_PAL218_G14_0_Msk                                  (0x1fUL << LCD_PAL218_G14_0_Pos)                          /*!< LCD PAL218: G14_0 Mask              */
-#define LCD_PAL218_B14_0_Pos                                  26                                                        /*!< LCD PAL218: B14_0 Position          */
-#define LCD_PAL218_B14_0_Msk                                  (0x1fUL << LCD_PAL218_B14_0_Pos)                          /*!< LCD PAL218: B14_0 Mask              */
-#define LCD_PAL218_I1_Pos                                     31                                                        /*!< LCD PAL218: I1 Position             */
-#define LCD_PAL218_I1_Msk                                     (0x01UL << LCD_PAL218_I1_Pos)                             /*!< LCD PAL218: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL219  -------------------------------------------
-#define LCD_PAL219_R04_0_Pos                                  0                                                         /*!< LCD PAL219: R04_0 Position          */
-#define LCD_PAL219_R04_0_Msk                                  (0x1fUL << LCD_PAL219_R04_0_Pos)                          /*!< LCD PAL219: R04_0 Mask              */
-#define LCD_PAL219_G04_0_Pos                                  5                                                         /*!< LCD PAL219: G04_0 Position          */
-#define LCD_PAL219_G04_0_Msk                                  (0x1fUL << LCD_PAL219_G04_0_Pos)                          /*!< LCD PAL219: G04_0 Mask              */
-#define LCD_PAL219_B04_0_Pos                                  10                                                        /*!< LCD PAL219: B04_0 Position          */
-#define LCD_PAL219_B04_0_Msk                                  (0x1fUL << LCD_PAL219_B04_0_Pos)                          /*!< LCD PAL219: B04_0 Mask              */
-#define LCD_PAL219_I0_Pos                                     15                                                        /*!< LCD PAL219: I0 Position             */
-#define LCD_PAL219_I0_Msk                                     (0x01UL << LCD_PAL219_I0_Pos)                             /*!< LCD PAL219: I0 Mask                 */
-#define LCD_PAL219_R14_0_Pos                                  16                                                        /*!< LCD PAL219: R14_0 Position          */
-#define LCD_PAL219_R14_0_Msk                                  (0x1fUL << LCD_PAL219_R14_0_Pos)                          /*!< LCD PAL219: R14_0 Mask              */
-#define LCD_PAL219_G14_0_Pos                                  21                                                        /*!< LCD PAL219: G14_0 Position          */
-#define LCD_PAL219_G14_0_Msk                                  (0x1fUL << LCD_PAL219_G14_0_Pos)                          /*!< LCD PAL219: G14_0 Mask              */
-#define LCD_PAL219_B14_0_Pos                                  26                                                        /*!< LCD PAL219: B14_0 Position          */
-#define LCD_PAL219_B14_0_Msk                                  (0x1fUL << LCD_PAL219_B14_0_Pos)                          /*!< LCD PAL219: B14_0 Mask              */
-#define LCD_PAL219_I1_Pos                                     31                                                        /*!< LCD PAL219: I1 Position             */
-#define LCD_PAL219_I1_Msk                                     (0x01UL << LCD_PAL219_I1_Pos)                             /*!< LCD PAL219: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL220  -------------------------------------------
-#define LCD_PAL220_R04_0_Pos                                  0                                                         /*!< LCD PAL220: R04_0 Position          */
-#define LCD_PAL220_R04_0_Msk                                  (0x1fUL << LCD_PAL220_R04_0_Pos)                          /*!< LCD PAL220: R04_0 Mask              */
-#define LCD_PAL220_G04_0_Pos                                  5                                                         /*!< LCD PAL220: G04_0 Position          */
-#define LCD_PAL220_G04_0_Msk                                  (0x1fUL << LCD_PAL220_G04_0_Pos)                          /*!< LCD PAL220: G04_0 Mask              */
-#define LCD_PAL220_B04_0_Pos                                  10                                                        /*!< LCD PAL220: B04_0 Position          */
-#define LCD_PAL220_B04_0_Msk                                  (0x1fUL << LCD_PAL220_B04_0_Pos)                          /*!< LCD PAL220: B04_0 Mask              */
-#define LCD_PAL220_I0_Pos                                     15                                                        /*!< LCD PAL220: I0 Position             */
-#define LCD_PAL220_I0_Msk                                     (0x01UL << LCD_PAL220_I0_Pos)                             /*!< LCD PAL220: I0 Mask                 */
-#define LCD_PAL220_R14_0_Pos                                  16                                                        /*!< LCD PAL220: R14_0 Position          */
-#define LCD_PAL220_R14_0_Msk                                  (0x1fUL << LCD_PAL220_R14_0_Pos)                          /*!< LCD PAL220: R14_0 Mask              */
-#define LCD_PAL220_G14_0_Pos                                  21                                                        /*!< LCD PAL220: G14_0 Position          */
-#define LCD_PAL220_G14_0_Msk                                  (0x1fUL << LCD_PAL220_G14_0_Pos)                          /*!< LCD PAL220: G14_0 Mask              */
-#define LCD_PAL220_B14_0_Pos                                  26                                                        /*!< LCD PAL220: B14_0 Position          */
-#define LCD_PAL220_B14_0_Msk                                  (0x1fUL << LCD_PAL220_B14_0_Pos)                          /*!< LCD PAL220: B14_0 Mask              */
-#define LCD_PAL220_I1_Pos                                     31                                                        /*!< LCD PAL220: I1 Position             */
-#define LCD_PAL220_I1_Msk                                     (0x01UL << LCD_PAL220_I1_Pos)                             /*!< LCD PAL220: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL221  -------------------------------------------
-#define LCD_PAL221_R04_0_Pos                                  0                                                         /*!< LCD PAL221: R04_0 Position          */
-#define LCD_PAL221_R04_0_Msk                                  (0x1fUL << LCD_PAL221_R04_0_Pos)                          /*!< LCD PAL221: R04_0 Mask              */
-#define LCD_PAL221_G04_0_Pos                                  5                                                         /*!< LCD PAL221: G04_0 Position          */
-#define LCD_PAL221_G04_0_Msk                                  (0x1fUL << LCD_PAL221_G04_0_Pos)                          /*!< LCD PAL221: G04_0 Mask              */
-#define LCD_PAL221_B04_0_Pos                                  10                                                        /*!< LCD PAL221: B04_0 Position          */
-#define LCD_PAL221_B04_0_Msk                                  (0x1fUL << LCD_PAL221_B04_0_Pos)                          /*!< LCD PAL221: B04_0 Mask              */
-#define LCD_PAL221_I0_Pos                                     15                                                        /*!< LCD PAL221: I0 Position             */
-#define LCD_PAL221_I0_Msk                                     (0x01UL << LCD_PAL221_I0_Pos)                             /*!< LCD PAL221: I0 Mask                 */
-#define LCD_PAL221_R14_0_Pos                                  16                                                        /*!< LCD PAL221: R14_0 Position          */
-#define LCD_PAL221_R14_0_Msk                                  (0x1fUL << LCD_PAL221_R14_0_Pos)                          /*!< LCD PAL221: R14_0 Mask              */
-#define LCD_PAL221_G14_0_Pos                                  21                                                        /*!< LCD PAL221: G14_0 Position          */
-#define LCD_PAL221_G14_0_Msk                                  (0x1fUL << LCD_PAL221_G14_0_Pos)                          /*!< LCD PAL221: G14_0 Mask              */
-#define LCD_PAL221_B14_0_Pos                                  26                                                        /*!< LCD PAL221: B14_0 Position          */
-#define LCD_PAL221_B14_0_Msk                                  (0x1fUL << LCD_PAL221_B14_0_Pos)                          /*!< LCD PAL221: B14_0 Mask              */
-#define LCD_PAL221_I1_Pos                                     31                                                        /*!< LCD PAL221: I1 Position             */
-#define LCD_PAL221_I1_Msk                                     (0x01UL << LCD_PAL221_I1_Pos)                             /*!< LCD PAL221: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL222  -------------------------------------------
-#define LCD_PAL222_R04_0_Pos                                  0                                                         /*!< LCD PAL222: R04_0 Position          */
-#define LCD_PAL222_R04_0_Msk                                  (0x1fUL << LCD_PAL222_R04_0_Pos)                          /*!< LCD PAL222: R04_0 Mask              */
-#define LCD_PAL222_G04_0_Pos                                  5                                                         /*!< LCD PAL222: G04_0 Position          */
-#define LCD_PAL222_G04_0_Msk                                  (0x1fUL << LCD_PAL222_G04_0_Pos)                          /*!< LCD PAL222: G04_0 Mask              */
-#define LCD_PAL222_B04_0_Pos                                  10                                                        /*!< LCD PAL222: B04_0 Position          */
-#define LCD_PAL222_B04_0_Msk                                  (0x1fUL << LCD_PAL222_B04_0_Pos)                          /*!< LCD PAL222: B04_0 Mask              */
-#define LCD_PAL222_I0_Pos                                     15                                                        /*!< LCD PAL222: I0 Position             */
-#define LCD_PAL222_I0_Msk                                     (0x01UL << LCD_PAL222_I0_Pos)                             /*!< LCD PAL222: I0 Mask                 */
-#define LCD_PAL222_R14_0_Pos                                  16                                                        /*!< LCD PAL222: R14_0 Position          */
-#define LCD_PAL222_R14_0_Msk                                  (0x1fUL << LCD_PAL222_R14_0_Pos)                          /*!< LCD PAL222: R14_0 Mask              */
-#define LCD_PAL222_G14_0_Pos                                  21                                                        /*!< LCD PAL222: G14_0 Position          */
-#define LCD_PAL222_G14_0_Msk                                  (0x1fUL << LCD_PAL222_G14_0_Pos)                          /*!< LCD PAL222: G14_0 Mask              */
-#define LCD_PAL222_B14_0_Pos                                  26                                                        /*!< LCD PAL222: B14_0 Position          */
-#define LCD_PAL222_B14_0_Msk                                  (0x1fUL << LCD_PAL222_B14_0_Pos)                          /*!< LCD PAL222: B14_0 Mask              */
-#define LCD_PAL222_I1_Pos                                     31                                                        /*!< LCD PAL222: I1 Position             */
-#define LCD_PAL222_I1_Msk                                     (0x01UL << LCD_PAL222_I1_Pos)                             /*!< LCD PAL222: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL223  -------------------------------------------
-#define LCD_PAL223_R04_0_Pos                                  0                                                         /*!< LCD PAL223: R04_0 Position          */
-#define LCD_PAL223_R04_0_Msk                                  (0x1fUL << LCD_PAL223_R04_0_Pos)                          /*!< LCD PAL223: R04_0 Mask              */
-#define LCD_PAL223_G04_0_Pos                                  5                                                         /*!< LCD PAL223: G04_0 Position          */
-#define LCD_PAL223_G04_0_Msk                                  (0x1fUL << LCD_PAL223_G04_0_Pos)                          /*!< LCD PAL223: G04_0 Mask              */
-#define LCD_PAL223_B04_0_Pos                                  10                                                        /*!< LCD PAL223: B04_0 Position          */
-#define LCD_PAL223_B04_0_Msk                                  (0x1fUL << LCD_PAL223_B04_0_Pos)                          /*!< LCD PAL223: B04_0 Mask              */
-#define LCD_PAL223_I0_Pos                                     15                                                        /*!< LCD PAL223: I0 Position             */
-#define LCD_PAL223_I0_Msk                                     (0x01UL << LCD_PAL223_I0_Pos)                             /*!< LCD PAL223: I0 Mask                 */
-#define LCD_PAL223_R14_0_Pos                                  16                                                        /*!< LCD PAL223: R14_0 Position          */
-#define LCD_PAL223_R14_0_Msk                                  (0x1fUL << LCD_PAL223_R14_0_Pos)                          /*!< LCD PAL223: R14_0 Mask              */
-#define LCD_PAL223_G14_0_Pos                                  21                                                        /*!< LCD PAL223: G14_0 Position          */
-#define LCD_PAL223_G14_0_Msk                                  (0x1fUL << LCD_PAL223_G14_0_Pos)                          /*!< LCD PAL223: G14_0 Mask              */
-#define LCD_PAL223_B14_0_Pos                                  26                                                        /*!< LCD PAL223: B14_0 Position          */
-#define LCD_PAL223_B14_0_Msk                                  (0x1fUL << LCD_PAL223_B14_0_Pos)                          /*!< LCD PAL223: B14_0 Mask              */
-#define LCD_PAL223_I1_Pos                                     31                                                        /*!< LCD PAL223: I1 Position             */
-#define LCD_PAL223_I1_Msk                                     (0x01UL << LCD_PAL223_I1_Pos)                             /*!< LCD PAL223: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL224  -------------------------------------------
-#define LCD_PAL224_R04_0_Pos                                  0                                                         /*!< LCD PAL224: R04_0 Position          */
-#define LCD_PAL224_R04_0_Msk                                  (0x1fUL << LCD_PAL224_R04_0_Pos)                          /*!< LCD PAL224: R04_0 Mask              */
-#define LCD_PAL224_G04_0_Pos                                  5                                                         /*!< LCD PAL224: G04_0 Position          */
-#define LCD_PAL224_G04_0_Msk                                  (0x1fUL << LCD_PAL224_G04_0_Pos)                          /*!< LCD PAL224: G04_0 Mask              */
-#define LCD_PAL224_B04_0_Pos                                  10                                                        /*!< LCD PAL224: B04_0 Position          */
-#define LCD_PAL224_B04_0_Msk                                  (0x1fUL << LCD_PAL224_B04_0_Pos)                          /*!< LCD PAL224: B04_0 Mask              */
-#define LCD_PAL224_I0_Pos                                     15                                                        /*!< LCD PAL224: I0 Position             */
-#define LCD_PAL224_I0_Msk                                     (0x01UL << LCD_PAL224_I0_Pos)                             /*!< LCD PAL224: I0 Mask                 */
-#define LCD_PAL224_R14_0_Pos                                  16                                                        /*!< LCD PAL224: R14_0 Position          */
-#define LCD_PAL224_R14_0_Msk                                  (0x1fUL << LCD_PAL224_R14_0_Pos)                          /*!< LCD PAL224: R14_0 Mask              */
-#define LCD_PAL224_G14_0_Pos                                  21                                                        /*!< LCD PAL224: G14_0 Position          */
-#define LCD_PAL224_G14_0_Msk                                  (0x1fUL << LCD_PAL224_G14_0_Pos)                          /*!< LCD PAL224: G14_0 Mask              */
-#define LCD_PAL224_B14_0_Pos                                  26                                                        /*!< LCD PAL224: B14_0 Position          */
-#define LCD_PAL224_B14_0_Msk                                  (0x1fUL << LCD_PAL224_B14_0_Pos)                          /*!< LCD PAL224: B14_0 Mask              */
-#define LCD_PAL224_I1_Pos                                     31                                                        /*!< LCD PAL224: I1 Position             */
-#define LCD_PAL224_I1_Msk                                     (0x01UL << LCD_PAL224_I1_Pos)                             /*!< LCD PAL224: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL225  -------------------------------------------
-#define LCD_PAL225_R04_0_Pos                                  0                                                         /*!< LCD PAL225: R04_0 Position          */
-#define LCD_PAL225_R04_0_Msk                                  (0x1fUL << LCD_PAL225_R04_0_Pos)                          /*!< LCD PAL225: R04_0 Mask              */
-#define LCD_PAL225_G04_0_Pos                                  5                                                         /*!< LCD PAL225: G04_0 Position          */
-#define LCD_PAL225_G04_0_Msk                                  (0x1fUL << LCD_PAL225_G04_0_Pos)                          /*!< LCD PAL225: G04_0 Mask              */
-#define LCD_PAL225_B04_0_Pos                                  10                                                        /*!< LCD PAL225: B04_0 Position          */
-#define LCD_PAL225_B04_0_Msk                                  (0x1fUL << LCD_PAL225_B04_0_Pos)                          /*!< LCD PAL225: B04_0 Mask              */
-#define LCD_PAL225_I0_Pos                                     15                                                        /*!< LCD PAL225: I0 Position             */
-#define LCD_PAL225_I0_Msk                                     (0x01UL << LCD_PAL225_I0_Pos)                             /*!< LCD PAL225: I0 Mask                 */
-#define LCD_PAL225_R14_0_Pos                                  16                                                        /*!< LCD PAL225: R14_0 Position          */
-#define LCD_PAL225_R14_0_Msk                                  (0x1fUL << LCD_PAL225_R14_0_Pos)                          /*!< LCD PAL225: R14_0 Mask              */
-#define LCD_PAL225_G14_0_Pos                                  21                                                        /*!< LCD PAL225: G14_0 Position          */
-#define LCD_PAL225_G14_0_Msk                                  (0x1fUL << LCD_PAL225_G14_0_Pos)                          /*!< LCD PAL225: G14_0 Mask              */
-#define LCD_PAL225_B14_0_Pos                                  26                                                        /*!< LCD PAL225: B14_0 Position          */
-#define LCD_PAL225_B14_0_Msk                                  (0x1fUL << LCD_PAL225_B14_0_Pos)                          /*!< LCD PAL225: B14_0 Mask              */
-#define LCD_PAL225_I1_Pos                                     31                                                        /*!< LCD PAL225: I1 Position             */
-#define LCD_PAL225_I1_Msk                                     (0x01UL << LCD_PAL225_I1_Pos)                             /*!< LCD PAL225: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL226  -------------------------------------------
-#define LCD_PAL226_R04_0_Pos                                  0                                                         /*!< LCD PAL226: R04_0 Position          */
-#define LCD_PAL226_R04_0_Msk                                  (0x1fUL << LCD_PAL226_R04_0_Pos)                          /*!< LCD PAL226: R04_0 Mask              */
-#define LCD_PAL226_G04_0_Pos                                  5                                                         /*!< LCD PAL226: G04_0 Position          */
-#define LCD_PAL226_G04_0_Msk                                  (0x1fUL << LCD_PAL226_G04_0_Pos)                          /*!< LCD PAL226: G04_0 Mask              */
-#define LCD_PAL226_B04_0_Pos                                  10                                                        /*!< LCD PAL226: B04_0 Position          */
-#define LCD_PAL226_B04_0_Msk                                  (0x1fUL << LCD_PAL226_B04_0_Pos)                          /*!< LCD PAL226: B04_0 Mask              */
-#define LCD_PAL226_I0_Pos                                     15                                                        /*!< LCD PAL226: I0 Position             */
-#define LCD_PAL226_I0_Msk                                     (0x01UL << LCD_PAL226_I0_Pos)                             /*!< LCD PAL226: I0 Mask                 */
-#define LCD_PAL226_R14_0_Pos                                  16                                                        /*!< LCD PAL226: R14_0 Position          */
-#define LCD_PAL226_R14_0_Msk                                  (0x1fUL << LCD_PAL226_R14_0_Pos)                          /*!< LCD PAL226: R14_0 Mask              */
-#define LCD_PAL226_G14_0_Pos                                  21                                                        /*!< LCD PAL226: G14_0 Position          */
-#define LCD_PAL226_G14_0_Msk                                  (0x1fUL << LCD_PAL226_G14_0_Pos)                          /*!< LCD PAL226: G14_0 Mask              */
-#define LCD_PAL226_B14_0_Pos                                  26                                                        /*!< LCD PAL226: B14_0 Position          */
-#define LCD_PAL226_B14_0_Msk                                  (0x1fUL << LCD_PAL226_B14_0_Pos)                          /*!< LCD PAL226: B14_0 Mask              */
-#define LCD_PAL226_I1_Pos                                     31                                                        /*!< LCD PAL226: I1 Position             */
-#define LCD_PAL226_I1_Msk                                     (0x01UL << LCD_PAL226_I1_Pos)                             /*!< LCD PAL226: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL227  -------------------------------------------
-#define LCD_PAL227_R04_0_Pos                                  0                                                         /*!< LCD PAL227: R04_0 Position          */
-#define LCD_PAL227_R04_0_Msk                                  (0x1fUL << LCD_PAL227_R04_0_Pos)                          /*!< LCD PAL227: R04_0 Mask              */
-#define LCD_PAL227_G04_0_Pos                                  5                                                         /*!< LCD PAL227: G04_0 Position          */
-#define LCD_PAL227_G04_0_Msk                                  (0x1fUL << LCD_PAL227_G04_0_Pos)                          /*!< LCD PAL227: G04_0 Mask              */
-#define LCD_PAL227_B04_0_Pos                                  10                                                        /*!< LCD PAL227: B04_0 Position          */
-#define LCD_PAL227_B04_0_Msk                                  (0x1fUL << LCD_PAL227_B04_0_Pos)                          /*!< LCD PAL227: B04_0 Mask              */
-#define LCD_PAL227_I0_Pos                                     15                                                        /*!< LCD PAL227: I0 Position             */
-#define LCD_PAL227_I0_Msk                                     (0x01UL << LCD_PAL227_I0_Pos)                             /*!< LCD PAL227: I0 Mask                 */
-#define LCD_PAL227_R14_0_Pos                                  16                                                        /*!< LCD PAL227: R14_0 Position          */
-#define LCD_PAL227_R14_0_Msk                                  (0x1fUL << LCD_PAL227_R14_0_Pos)                          /*!< LCD PAL227: R14_0 Mask              */
-#define LCD_PAL227_G14_0_Pos                                  21                                                        /*!< LCD PAL227: G14_0 Position          */
-#define LCD_PAL227_G14_0_Msk                                  (0x1fUL << LCD_PAL227_G14_0_Pos)                          /*!< LCD PAL227: G14_0 Mask              */
-#define LCD_PAL227_B14_0_Pos                                  26                                                        /*!< LCD PAL227: B14_0 Position          */
-#define LCD_PAL227_B14_0_Msk                                  (0x1fUL << LCD_PAL227_B14_0_Pos)                          /*!< LCD PAL227: B14_0 Mask              */
-#define LCD_PAL227_I1_Pos                                     31                                                        /*!< LCD PAL227: I1 Position             */
-#define LCD_PAL227_I1_Msk                                     (0x01UL << LCD_PAL227_I1_Pos)                             /*!< LCD PAL227: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL228  -------------------------------------------
-#define LCD_PAL228_R04_0_Pos                                  0                                                         /*!< LCD PAL228: R04_0 Position          */
-#define LCD_PAL228_R04_0_Msk                                  (0x1fUL << LCD_PAL228_R04_0_Pos)                          /*!< LCD PAL228: R04_0 Mask              */
-#define LCD_PAL228_G04_0_Pos                                  5                                                         /*!< LCD PAL228: G04_0 Position          */
-#define LCD_PAL228_G04_0_Msk                                  (0x1fUL << LCD_PAL228_G04_0_Pos)                          /*!< LCD PAL228: G04_0 Mask              */
-#define LCD_PAL228_B04_0_Pos                                  10                                                        /*!< LCD PAL228: B04_0 Position          */
-#define LCD_PAL228_B04_0_Msk                                  (0x1fUL << LCD_PAL228_B04_0_Pos)                          /*!< LCD PAL228: B04_0 Mask              */
-#define LCD_PAL228_I0_Pos                                     15                                                        /*!< LCD PAL228: I0 Position             */
-#define LCD_PAL228_I0_Msk                                     (0x01UL << LCD_PAL228_I0_Pos)                             /*!< LCD PAL228: I0 Mask                 */
-#define LCD_PAL228_R14_0_Pos                                  16                                                        /*!< LCD PAL228: R14_0 Position          */
-#define LCD_PAL228_R14_0_Msk                                  (0x1fUL << LCD_PAL228_R14_0_Pos)                          /*!< LCD PAL228: R14_0 Mask              */
-#define LCD_PAL228_G14_0_Pos                                  21                                                        /*!< LCD PAL228: G14_0 Position          */
-#define LCD_PAL228_G14_0_Msk                                  (0x1fUL << LCD_PAL228_G14_0_Pos)                          /*!< LCD PAL228: G14_0 Mask              */
-#define LCD_PAL228_B14_0_Pos                                  26                                                        /*!< LCD PAL228: B14_0 Position          */
-#define LCD_PAL228_B14_0_Msk                                  (0x1fUL << LCD_PAL228_B14_0_Pos)                          /*!< LCD PAL228: B14_0 Mask              */
-#define LCD_PAL228_I1_Pos                                     31                                                        /*!< LCD PAL228: I1 Position             */
-#define LCD_PAL228_I1_Msk                                     (0x01UL << LCD_PAL228_I1_Pos)                             /*!< LCD PAL228: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL229  -------------------------------------------
-#define LCD_PAL229_R04_0_Pos                                  0                                                         /*!< LCD PAL229: R04_0 Position          */
-#define LCD_PAL229_R04_0_Msk                                  (0x1fUL << LCD_PAL229_R04_0_Pos)                          /*!< LCD PAL229: R04_0 Mask              */
-#define LCD_PAL229_G04_0_Pos                                  5                                                         /*!< LCD PAL229: G04_0 Position          */
-#define LCD_PAL229_G04_0_Msk                                  (0x1fUL << LCD_PAL229_G04_0_Pos)                          /*!< LCD PAL229: G04_0 Mask              */
-#define LCD_PAL229_B04_0_Pos                                  10                                                        /*!< LCD PAL229: B04_0 Position          */
-#define LCD_PAL229_B04_0_Msk                                  (0x1fUL << LCD_PAL229_B04_0_Pos)                          /*!< LCD PAL229: B04_0 Mask              */
-#define LCD_PAL229_I0_Pos                                     15                                                        /*!< LCD PAL229: I0 Position             */
-#define LCD_PAL229_I0_Msk                                     (0x01UL << LCD_PAL229_I0_Pos)                             /*!< LCD PAL229: I0 Mask                 */
-#define LCD_PAL229_R14_0_Pos                                  16                                                        /*!< LCD PAL229: R14_0 Position          */
-#define LCD_PAL229_R14_0_Msk                                  (0x1fUL << LCD_PAL229_R14_0_Pos)                          /*!< LCD PAL229: R14_0 Mask              */
-#define LCD_PAL229_G14_0_Pos                                  21                                                        /*!< LCD PAL229: G14_0 Position          */
-#define LCD_PAL229_G14_0_Msk                                  (0x1fUL << LCD_PAL229_G14_0_Pos)                          /*!< LCD PAL229: G14_0 Mask              */
-#define LCD_PAL229_B14_0_Pos                                  26                                                        /*!< LCD PAL229: B14_0 Position          */
-#define LCD_PAL229_B14_0_Msk                                  (0x1fUL << LCD_PAL229_B14_0_Pos)                          /*!< LCD PAL229: B14_0 Mask              */
-#define LCD_PAL229_I1_Pos                                     31                                                        /*!< LCD PAL229: I1 Position             */
-#define LCD_PAL229_I1_Msk                                     (0x01UL << LCD_PAL229_I1_Pos)                             /*!< LCD PAL229: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL230  -------------------------------------------
-#define LCD_PAL230_R04_0_Pos                                  0                                                         /*!< LCD PAL230: R04_0 Position          */
-#define LCD_PAL230_R04_0_Msk                                  (0x1fUL << LCD_PAL230_R04_0_Pos)                          /*!< LCD PAL230: R04_0 Mask              */
-#define LCD_PAL230_G04_0_Pos                                  5                                                         /*!< LCD PAL230: G04_0 Position          */
-#define LCD_PAL230_G04_0_Msk                                  (0x1fUL << LCD_PAL230_G04_0_Pos)                          /*!< LCD PAL230: G04_0 Mask              */
-#define LCD_PAL230_B04_0_Pos                                  10                                                        /*!< LCD PAL230: B04_0 Position          */
-#define LCD_PAL230_B04_0_Msk                                  (0x1fUL << LCD_PAL230_B04_0_Pos)                          /*!< LCD PAL230: B04_0 Mask              */
-#define LCD_PAL230_I0_Pos                                     15                                                        /*!< LCD PAL230: I0 Position             */
-#define LCD_PAL230_I0_Msk                                     (0x01UL << LCD_PAL230_I0_Pos)                             /*!< LCD PAL230: I0 Mask                 */
-#define LCD_PAL230_R14_0_Pos                                  16                                                        /*!< LCD PAL230: R14_0 Position          */
-#define LCD_PAL230_R14_0_Msk                                  (0x1fUL << LCD_PAL230_R14_0_Pos)                          /*!< LCD PAL230: R14_0 Mask              */
-#define LCD_PAL230_G14_0_Pos                                  21                                                        /*!< LCD PAL230: G14_0 Position          */
-#define LCD_PAL230_G14_0_Msk                                  (0x1fUL << LCD_PAL230_G14_0_Pos)                          /*!< LCD PAL230: G14_0 Mask              */
-#define LCD_PAL230_B14_0_Pos                                  26                                                        /*!< LCD PAL230: B14_0 Position          */
-#define LCD_PAL230_B14_0_Msk                                  (0x1fUL << LCD_PAL230_B14_0_Pos)                          /*!< LCD PAL230: B14_0 Mask              */
-#define LCD_PAL230_I1_Pos                                     31                                                        /*!< LCD PAL230: I1 Position             */
-#define LCD_PAL230_I1_Msk                                     (0x01UL << LCD_PAL230_I1_Pos)                             /*!< LCD PAL230: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL231  -------------------------------------------
-#define LCD_PAL231_R04_0_Pos                                  0                                                         /*!< LCD PAL231: R04_0 Position          */
-#define LCD_PAL231_R04_0_Msk                                  (0x1fUL << LCD_PAL231_R04_0_Pos)                          /*!< LCD PAL231: R04_0 Mask              */
-#define LCD_PAL231_G04_0_Pos                                  5                                                         /*!< LCD PAL231: G04_0 Position          */
-#define LCD_PAL231_G04_0_Msk                                  (0x1fUL << LCD_PAL231_G04_0_Pos)                          /*!< LCD PAL231: G04_0 Mask              */
-#define LCD_PAL231_B04_0_Pos                                  10                                                        /*!< LCD PAL231: B04_0 Position          */
-#define LCD_PAL231_B04_0_Msk                                  (0x1fUL << LCD_PAL231_B04_0_Pos)                          /*!< LCD PAL231: B04_0 Mask              */
-#define LCD_PAL231_I0_Pos                                     15                                                        /*!< LCD PAL231: I0 Position             */
-#define LCD_PAL231_I0_Msk                                     (0x01UL << LCD_PAL231_I0_Pos)                             /*!< LCD PAL231: I0 Mask                 */
-#define LCD_PAL231_R14_0_Pos                                  16                                                        /*!< LCD PAL231: R14_0 Position          */
-#define LCD_PAL231_R14_0_Msk                                  (0x1fUL << LCD_PAL231_R14_0_Pos)                          /*!< LCD PAL231: R14_0 Mask              */
-#define LCD_PAL231_G14_0_Pos                                  21                                                        /*!< LCD PAL231: G14_0 Position          */
-#define LCD_PAL231_G14_0_Msk                                  (0x1fUL << LCD_PAL231_G14_0_Pos)                          /*!< LCD PAL231: G14_0 Mask              */
-#define LCD_PAL231_B14_0_Pos                                  26                                                        /*!< LCD PAL231: B14_0 Position          */
-#define LCD_PAL231_B14_0_Msk                                  (0x1fUL << LCD_PAL231_B14_0_Pos)                          /*!< LCD PAL231: B14_0 Mask              */
-#define LCD_PAL231_I1_Pos                                     31                                                        /*!< LCD PAL231: I1 Position             */
-#define LCD_PAL231_I1_Msk                                     (0x01UL << LCD_PAL231_I1_Pos)                             /*!< LCD PAL231: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL232  -------------------------------------------
-#define LCD_PAL232_R04_0_Pos                                  0                                                         /*!< LCD PAL232: R04_0 Position          */
-#define LCD_PAL232_R04_0_Msk                                  (0x1fUL << LCD_PAL232_R04_0_Pos)                          /*!< LCD PAL232: R04_0 Mask              */
-#define LCD_PAL232_G04_0_Pos                                  5                                                         /*!< LCD PAL232: G04_0 Position          */
-#define LCD_PAL232_G04_0_Msk                                  (0x1fUL << LCD_PAL232_G04_0_Pos)                          /*!< LCD PAL232: G04_0 Mask              */
-#define LCD_PAL232_B04_0_Pos                                  10                                                        /*!< LCD PAL232: B04_0 Position          */
-#define LCD_PAL232_B04_0_Msk                                  (0x1fUL << LCD_PAL232_B04_0_Pos)                          /*!< LCD PAL232: B04_0 Mask              */
-#define LCD_PAL232_I0_Pos                                     15                                                        /*!< LCD PAL232: I0 Position             */
-#define LCD_PAL232_I0_Msk                                     (0x01UL << LCD_PAL232_I0_Pos)                             /*!< LCD PAL232: I0 Mask                 */
-#define LCD_PAL232_R14_0_Pos                                  16                                                        /*!< LCD PAL232: R14_0 Position          */
-#define LCD_PAL232_R14_0_Msk                                  (0x1fUL << LCD_PAL232_R14_0_Pos)                          /*!< LCD PAL232: R14_0 Mask              */
-#define LCD_PAL232_G14_0_Pos                                  21                                                        /*!< LCD PAL232: G14_0 Position          */
-#define LCD_PAL232_G14_0_Msk                                  (0x1fUL << LCD_PAL232_G14_0_Pos)                          /*!< LCD PAL232: G14_0 Mask              */
-#define LCD_PAL232_B14_0_Pos                                  26                                                        /*!< LCD PAL232: B14_0 Position          */
-#define LCD_PAL232_B14_0_Msk                                  (0x1fUL << LCD_PAL232_B14_0_Pos)                          /*!< LCD PAL232: B14_0 Mask              */
-#define LCD_PAL232_I1_Pos                                     31                                                        /*!< LCD PAL232: I1 Position             */
-#define LCD_PAL232_I1_Msk                                     (0x01UL << LCD_PAL232_I1_Pos)                             /*!< LCD PAL232: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL233  -------------------------------------------
-#define LCD_PAL233_R04_0_Pos                                  0                                                         /*!< LCD PAL233: R04_0 Position          */
-#define LCD_PAL233_R04_0_Msk                                  (0x1fUL << LCD_PAL233_R04_0_Pos)                          /*!< LCD PAL233: R04_0 Mask              */
-#define LCD_PAL233_G04_0_Pos                                  5                                                         /*!< LCD PAL233: G04_0 Position          */
-#define LCD_PAL233_G04_0_Msk                                  (0x1fUL << LCD_PAL233_G04_0_Pos)                          /*!< LCD PAL233: G04_0 Mask              */
-#define LCD_PAL233_B04_0_Pos                                  10                                                        /*!< LCD PAL233: B04_0 Position          */
-#define LCD_PAL233_B04_0_Msk                                  (0x1fUL << LCD_PAL233_B04_0_Pos)                          /*!< LCD PAL233: B04_0 Mask              */
-#define LCD_PAL233_I0_Pos                                     15                                                        /*!< LCD PAL233: I0 Position             */
-#define LCD_PAL233_I0_Msk                                     (0x01UL << LCD_PAL233_I0_Pos)                             /*!< LCD PAL233: I0 Mask                 */
-#define LCD_PAL233_R14_0_Pos                                  16                                                        /*!< LCD PAL233: R14_0 Position          */
-#define LCD_PAL233_R14_0_Msk                                  (0x1fUL << LCD_PAL233_R14_0_Pos)                          /*!< LCD PAL233: R14_0 Mask              */
-#define LCD_PAL233_G14_0_Pos                                  21                                                        /*!< LCD PAL233: G14_0 Position          */
-#define LCD_PAL233_G14_0_Msk                                  (0x1fUL << LCD_PAL233_G14_0_Pos)                          /*!< LCD PAL233: G14_0 Mask              */
-#define LCD_PAL233_B14_0_Pos                                  26                                                        /*!< LCD PAL233: B14_0 Position          */
-#define LCD_PAL233_B14_0_Msk                                  (0x1fUL << LCD_PAL233_B14_0_Pos)                          /*!< LCD PAL233: B14_0 Mask              */
-#define LCD_PAL233_I1_Pos                                     31                                                        /*!< LCD PAL233: I1 Position             */
-#define LCD_PAL233_I1_Msk                                     (0x01UL << LCD_PAL233_I1_Pos)                             /*!< LCD PAL233: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL234  -------------------------------------------
-#define LCD_PAL234_R04_0_Pos                                  0                                                         /*!< LCD PAL234: R04_0 Position          */
-#define LCD_PAL234_R04_0_Msk                                  (0x1fUL << LCD_PAL234_R04_0_Pos)                          /*!< LCD PAL234: R04_0 Mask              */
-#define LCD_PAL234_G04_0_Pos                                  5                                                         /*!< LCD PAL234: G04_0 Position          */
-#define LCD_PAL234_G04_0_Msk                                  (0x1fUL << LCD_PAL234_G04_0_Pos)                          /*!< LCD PAL234: G04_0 Mask              */
-#define LCD_PAL234_B04_0_Pos                                  10                                                        /*!< LCD PAL234: B04_0 Position          */
-#define LCD_PAL234_B04_0_Msk                                  (0x1fUL << LCD_PAL234_B04_0_Pos)                          /*!< LCD PAL234: B04_0 Mask              */
-#define LCD_PAL234_I0_Pos                                     15                                                        /*!< LCD PAL234: I0 Position             */
-#define LCD_PAL234_I0_Msk                                     (0x01UL << LCD_PAL234_I0_Pos)                             /*!< LCD PAL234: I0 Mask                 */
-#define LCD_PAL234_R14_0_Pos                                  16                                                        /*!< LCD PAL234: R14_0 Position          */
-#define LCD_PAL234_R14_0_Msk                                  (0x1fUL << LCD_PAL234_R14_0_Pos)                          /*!< LCD PAL234: R14_0 Mask              */
-#define LCD_PAL234_G14_0_Pos                                  21                                                        /*!< LCD PAL234: G14_0 Position          */
-#define LCD_PAL234_G14_0_Msk                                  (0x1fUL << LCD_PAL234_G14_0_Pos)                          /*!< LCD PAL234: G14_0 Mask              */
-#define LCD_PAL234_B14_0_Pos                                  26                                                        /*!< LCD PAL234: B14_0 Position          */
-#define LCD_PAL234_B14_0_Msk                                  (0x1fUL << LCD_PAL234_B14_0_Pos)                          /*!< LCD PAL234: B14_0 Mask              */
-#define LCD_PAL234_I1_Pos                                     31                                                        /*!< LCD PAL234: I1 Position             */
-#define LCD_PAL234_I1_Msk                                     (0x01UL << LCD_PAL234_I1_Pos)                             /*!< LCD PAL234: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL235  -------------------------------------------
-#define LCD_PAL235_R04_0_Pos                                  0                                                         /*!< LCD PAL235: R04_0 Position          */
-#define LCD_PAL235_R04_0_Msk                                  (0x1fUL << LCD_PAL235_R04_0_Pos)                          /*!< LCD PAL235: R04_0 Mask              */
-#define LCD_PAL235_G04_0_Pos                                  5                                                         /*!< LCD PAL235: G04_0 Position          */
-#define LCD_PAL235_G04_0_Msk                                  (0x1fUL << LCD_PAL235_G04_0_Pos)                          /*!< LCD PAL235: G04_0 Mask              */
-#define LCD_PAL235_B04_0_Pos                                  10                                                        /*!< LCD PAL235: B04_0 Position          */
-#define LCD_PAL235_B04_0_Msk                                  (0x1fUL << LCD_PAL235_B04_0_Pos)                          /*!< LCD PAL235: B04_0 Mask              */
-#define LCD_PAL235_I0_Pos                                     15                                                        /*!< LCD PAL235: I0 Position             */
-#define LCD_PAL235_I0_Msk                                     (0x01UL << LCD_PAL235_I0_Pos)                             /*!< LCD PAL235: I0 Mask                 */
-#define LCD_PAL235_R14_0_Pos                                  16                                                        /*!< LCD PAL235: R14_0 Position          */
-#define LCD_PAL235_R14_0_Msk                                  (0x1fUL << LCD_PAL235_R14_0_Pos)                          /*!< LCD PAL235: R14_0 Mask              */
-#define LCD_PAL235_G14_0_Pos                                  21                                                        /*!< LCD PAL235: G14_0 Position          */
-#define LCD_PAL235_G14_0_Msk                                  (0x1fUL << LCD_PAL235_G14_0_Pos)                          /*!< LCD PAL235: G14_0 Mask              */
-#define LCD_PAL235_B14_0_Pos                                  26                                                        /*!< LCD PAL235: B14_0 Position          */
-#define LCD_PAL235_B14_0_Msk                                  (0x1fUL << LCD_PAL235_B14_0_Pos)                          /*!< LCD PAL235: B14_0 Mask              */
-#define LCD_PAL235_I1_Pos                                     31                                                        /*!< LCD PAL235: I1 Position             */
-#define LCD_PAL235_I1_Msk                                     (0x01UL << LCD_PAL235_I1_Pos)                             /*!< LCD PAL235: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL236  -------------------------------------------
-#define LCD_PAL236_R04_0_Pos                                  0                                                         /*!< LCD PAL236: R04_0 Position          */
-#define LCD_PAL236_R04_0_Msk                                  (0x1fUL << LCD_PAL236_R04_0_Pos)                          /*!< LCD PAL236: R04_0 Mask              */
-#define LCD_PAL236_G04_0_Pos                                  5                                                         /*!< LCD PAL236: G04_0 Position          */
-#define LCD_PAL236_G04_0_Msk                                  (0x1fUL << LCD_PAL236_G04_0_Pos)                          /*!< LCD PAL236: G04_0 Mask              */
-#define LCD_PAL236_B04_0_Pos                                  10                                                        /*!< LCD PAL236: B04_0 Position          */
-#define LCD_PAL236_B04_0_Msk                                  (0x1fUL << LCD_PAL236_B04_0_Pos)                          /*!< LCD PAL236: B04_0 Mask              */
-#define LCD_PAL236_I0_Pos                                     15                                                        /*!< LCD PAL236: I0 Position             */
-#define LCD_PAL236_I0_Msk                                     (0x01UL << LCD_PAL236_I0_Pos)                             /*!< LCD PAL236: I0 Mask                 */
-#define LCD_PAL236_R14_0_Pos                                  16                                                        /*!< LCD PAL236: R14_0 Position          */
-#define LCD_PAL236_R14_0_Msk                                  (0x1fUL << LCD_PAL236_R14_0_Pos)                          /*!< LCD PAL236: R14_0 Mask              */
-#define LCD_PAL236_G14_0_Pos                                  21                                                        /*!< LCD PAL236: G14_0 Position          */
-#define LCD_PAL236_G14_0_Msk                                  (0x1fUL << LCD_PAL236_G14_0_Pos)                          /*!< LCD PAL236: G14_0 Mask              */
-#define LCD_PAL236_B14_0_Pos                                  26                                                        /*!< LCD PAL236: B14_0 Position          */
-#define LCD_PAL236_B14_0_Msk                                  (0x1fUL << LCD_PAL236_B14_0_Pos)                          /*!< LCD PAL236: B14_0 Mask              */
-#define LCD_PAL236_I1_Pos                                     31                                                        /*!< LCD PAL236: I1 Position             */
-#define LCD_PAL236_I1_Msk                                     (0x01UL << LCD_PAL236_I1_Pos)                             /*!< LCD PAL236: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL237  -------------------------------------------
-#define LCD_PAL237_R04_0_Pos                                  0                                                         /*!< LCD PAL237: R04_0 Position          */
-#define LCD_PAL237_R04_0_Msk                                  (0x1fUL << LCD_PAL237_R04_0_Pos)                          /*!< LCD PAL237: R04_0 Mask              */
-#define LCD_PAL237_G04_0_Pos                                  5                                                         /*!< LCD PAL237: G04_0 Position          */
-#define LCD_PAL237_G04_0_Msk                                  (0x1fUL << LCD_PAL237_G04_0_Pos)                          /*!< LCD PAL237: G04_0 Mask              */
-#define LCD_PAL237_B04_0_Pos                                  10                                                        /*!< LCD PAL237: B04_0 Position          */
-#define LCD_PAL237_B04_0_Msk                                  (0x1fUL << LCD_PAL237_B04_0_Pos)                          /*!< LCD PAL237: B04_0 Mask              */
-#define LCD_PAL237_I0_Pos                                     15                                                        /*!< LCD PAL237: I0 Position             */
-#define LCD_PAL237_I0_Msk                                     (0x01UL << LCD_PAL237_I0_Pos)                             /*!< LCD PAL237: I0 Mask                 */
-#define LCD_PAL237_R14_0_Pos                                  16                                                        /*!< LCD PAL237: R14_0 Position          */
-#define LCD_PAL237_R14_0_Msk                                  (0x1fUL << LCD_PAL237_R14_0_Pos)                          /*!< LCD PAL237: R14_0 Mask              */
-#define LCD_PAL237_G14_0_Pos                                  21                                                        /*!< LCD PAL237: G14_0 Position          */
-#define LCD_PAL237_G14_0_Msk                                  (0x1fUL << LCD_PAL237_G14_0_Pos)                          /*!< LCD PAL237: G14_0 Mask              */
-#define LCD_PAL237_B14_0_Pos                                  26                                                        /*!< LCD PAL237: B14_0 Position          */
-#define LCD_PAL237_B14_0_Msk                                  (0x1fUL << LCD_PAL237_B14_0_Pos)                          /*!< LCD PAL237: B14_0 Mask              */
-#define LCD_PAL237_I1_Pos                                     31                                                        /*!< LCD PAL237: I1 Position             */
-#define LCD_PAL237_I1_Msk                                     (0x01UL << LCD_PAL237_I1_Pos)                             /*!< LCD PAL237: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL238  -------------------------------------------
-#define LCD_PAL238_R04_0_Pos                                  0                                                         /*!< LCD PAL238: R04_0 Position          */
-#define LCD_PAL238_R04_0_Msk                                  (0x1fUL << LCD_PAL238_R04_0_Pos)                          /*!< LCD PAL238: R04_0 Mask              */
-#define LCD_PAL238_G04_0_Pos                                  5                                                         /*!< LCD PAL238: G04_0 Position          */
-#define LCD_PAL238_G04_0_Msk                                  (0x1fUL << LCD_PAL238_G04_0_Pos)                          /*!< LCD PAL238: G04_0 Mask              */
-#define LCD_PAL238_B04_0_Pos                                  10                                                        /*!< LCD PAL238: B04_0 Position          */
-#define LCD_PAL238_B04_0_Msk                                  (0x1fUL << LCD_PAL238_B04_0_Pos)                          /*!< LCD PAL238: B04_0 Mask              */
-#define LCD_PAL238_I0_Pos                                     15                                                        /*!< LCD PAL238: I0 Position             */
-#define LCD_PAL238_I0_Msk                                     (0x01UL << LCD_PAL238_I0_Pos)                             /*!< LCD PAL238: I0 Mask                 */
-#define LCD_PAL238_R14_0_Pos                                  16                                                        /*!< LCD PAL238: R14_0 Position          */
-#define LCD_PAL238_R14_0_Msk                                  (0x1fUL << LCD_PAL238_R14_0_Pos)                          /*!< LCD PAL238: R14_0 Mask              */
-#define LCD_PAL238_G14_0_Pos                                  21                                                        /*!< LCD PAL238: G14_0 Position          */
-#define LCD_PAL238_G14_0_Msk                                  (0x1fUL << LCD_PAL238_G14_0_Pos)                          /*!< LCD PAL238: G14_0 Mask              */
-#define LCD_PAL238_B14_0_Pos                                  26                                                        /*!< LCD PAL238: B14_0 Position          */
-#define LCD_PAL238_B14_0_Msk                                  (0x1fUL << LCD_PAL238_B14_0_Pos)                          /*!< LCD PAL238: B14_0 Mask              */
-#define LCD_PAL238_I1_Pos                                     31                                                        /*!< LCD PAL238: I1 Position             */
-#define LCD_PAL238_I1_Msk                                     (0x01UL << LCD_PAL238_I1_Pos)                             /*!< LCD PAL238: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL239  -------------------------------------------
-#define LCD_PAL239_R04_0_Pos                                  0                                                         /*!< LCD PAL239: R04_0 Position          */
-#define LCD_PAL239_R04_0_Msk                                  (0x1fUL << LCD_PAL239_R04_0_Pos)                          /*!< LCD PAL239: R04_0 Mask              */
-#define LCD_PAL239_G04_0_Pos                                  5                                                         /*!< LCD PAL239: G04_0 Position          */
-#define LCD_PAL239_G04_0_Msk                                  (0x1fUL << LCD_PAL239_G04_0_Pos)                          /*!< LCD PAL239: G04_0 Mask              */
-#define LCD_PAL239_B04_0_Pos                                  10                                                        /*!< LCD PAL239: B04_0 Position          */
-#define LCD_PAL239_B04_0_Msk                                  (0x1fUL << LCD_PAL239_B04_0_Pos)                          /*!< LCD PAL239: B04_0 Mask              */
-#define LCD_PAL239_I0_Pos                                     15                                                        /*!< LCD PAL239: I0 Position             */
-#define LCD_PAL239_I0_Msk                                     (0x01UL << LCD_PAL239_I0_Pos)                             /*!< LCD PAL239: I0 Mask                 */
-#define LCD_PAL239_R14_0_Pos                                  16                                                        /*!< LCD PAL239: R14_0 Position          */
-#define LCD_PAL239_R14_0_Msk                                  (0x1fUL << LCD_PAL239_R14_0_Pos)                          /*!< LCD PAL239: R14_0 Mask              */
-#define LCD_PAL239_G14_0_Pos                                  21                                                        /*!< LCD PAL239: G14_0 Position          */
-#define LCD_PAL239_G14_0_Msk                                  (0x1fUL << LCD_PAL239_G14_0_Pos)                          /*!< LCD PAL239: G14_0 Mask              */
-#define LCD_PAL239_B14_0_Pos                                  26                                                        /*!< LCD PAL239: B14_0 Position          */
-#define LCD_PAL239_B14_0_Msk                                  (0x1fUL << LCD_PAL239_B14_0_Pos)                          /*!< LCD PAL239: B14_0 Mask              */
-#define LCD_PAL239_I1_Pos                                     31                                                        /*!< LCD PAL239: I1 Position             */
-#define LCD_PAL239_I1_Msk                                     (0x01UL << LCD_PAL239_I1_Pos)                             /*!< LCD PAL239: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL240  -------------------------------------------
-#define LCD_PAL240_R04_0_Pos                                  0                                                         /*!< LCD PAL240: R04_0 Position          */
-#define LCD_PAL240_R04_0_Msk                                  (0x1fUL << LCD_PAL240_R04_0_Pos)                          /*!< LCD PAL240: R04_0 Mask              */
-#define LCD_PAL240_G04_0_Pos                                  5                                                         /*!< LCD PAL240: G04_0 Position          */
-#define LCD_PAL240_G04_0_Msk                                  (0x1fUL << LCD_PAL240_G04_0_Pos)                          /*!< LCD PAL240: G04_0 Mask              */
-#define LCD_PAL240_B04_0_Pos                                  10                                                        /*!< LCD PAL240: B04_0 Position          */
-#define LCD_PAL240_B04_0_Msk                                  (0x1fUL << LCD_PAL240_B04_0_Pos)                          /*!< LCD PAL240: B04_0 Mask              */
-#define LCD_PAL240_I0_Pos                                     15                                                        /*!< LCD PAL240: I0 Position             */
-#define LCD_PAL240_I0_Msk                                     (0x01UL << LCD_PAL240_I0_Pos)                             /*!< LCD PAL240: I0 Mask                 */
-#define LCD_PAL240_R14_0_Pos                                  16                                                        /*!< LCD PAL240: R14_0 Position          */
-#define LCD_PAL240_R14_0_Msk                                  (0x1fUL << LCD_PAL240_R14_0_Pos)                          /*!< LCD PAL240: R14_0 Mask              */
-#define LCD_PAL240_G14_0_Pos                                  21                                                        /*!< LCD PAL240: G14_0 Position          */
-#define LCD_PAL240_G14_0_Msk                                  (0x1fUL << LCD_PAL240_G14_0_Pos)                          /*!< LCD PAL240: G14_0 Mask              */
-#define LCD_PAL240_B14_0_Pos                                  26                                                        /*!< LCD PAL240: B14_0 Position          */
-#define LCD_PAL240_B14_0_Msk                                  (0x1fUL << LCD_PAL240_B14_0_Pos)                          /*!< LCD PAL240: B14_0 Mask              */
-#define LCD_PAL240_I1_Pos                                     31                                                        /*!< LCD PAL240: I1 Position             */
-#define LCD_PAL240_I1_Msk                                     (0x01UL << LCD_PAL240_I1_Pos)                             /*!< LCD PAL240: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL241  -------------------------------------------
-#define LCD_PAL241_R04_0_Pos                                  0                                                         /*!< LCD PAL241: R04_0 Position          */
-#define LCD_PAL241_R04_0_Msk                                  (0x1fUL << LCD_PAL241_R04_0_Pos)                          /*!< LCD PAL241: R04_0 Mask              */
-#define LCD_PAL241_G04_0_Pos                                  5                                                         /*!< LCD PAL241: G04_0 Position          */
-#define LCD_PAL241_G04_0_Msk                                  (0x1fUL << LCD_PAL241_G04_0_Pos)                          /*!< LCD PAL241: G04_0 Mask              */
-#define LCD_PAL241_B04_0_Pos                                  10                                                        /*!< LCD PAL241: B04_0 Position          */
-#define LCD_PAL241_B04_0_Msk                                  (0x1fUL << LCD_PAL241_B04_0_Pos)                          /*!< LCD PAL241: B04_0 Mask              */
-#define LCD_PAL241_I0_Pos                                     15                                                        /*!< LCD PAL241: I0 Position             */
-#define LCD_PAL241_I0_Msk                                     (0x01UL << LCD_PAL241_I0_Pos)                             /*!< LCD PAL241: I0 Mask                 */
-#define LCD_PAL241_R14_0_Pos                                  16                                                        /*!< LCD PAL241: R14_0 Position          */
-#define LCD_PAL241_R14_0_Msk                                  (0x1fUL << LCD_PAL241_R14_0_Pos)                          /*!< LCD PAL241: R14_0 Mask              */
-#define LCD_PAL241_G14_0_Pos                                  21                                                        /*!< LCD PAL241: G14_0 Position          */
-#define LCD_PAL241_G14_0_Msk                                  (0x1fUL << LCD_PAL241_G14_0_Pos)                          /*!< LCD PAL241: G14_0 Mask              */
-#define LCD_PAL241_B14_0_Pos                                  26                                                        /*!< LCD PAL241: B14_0 Position          */
-#define LCD_PAL241_B14_0_Msk                                  (0x1fUL << LCD_PAL241_B14_0_Pos)                          /*!< LCD PAL241: B14_0 Mask              */
-#define LCD_PAL241_I1_Pos                                     31                                                        /*!< LCD PAL241: I1 Position             */
-#define LCD_PAL241_I1_Msk                                     (0x01UL << LCD_PAL241_I1_Pos)                             /*!< LCD PAL241: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL242  -------------------------------------------
-#define LCD_PAL242_R04_0_Pos                                  0                                                         /*!< LCD PAL242: R04_0 Position          */
-#define LCD_PAL242_R04_0_Msk                                  (0x1fUL << LCD_PAL242_R04_0_Pos)                          /*!< LCD PAL242: R04_0 Mask              */
-#define LCD_PAL242_G04_0_Pos                                  5                                                         /*!< LCD PAL242: G04_0 Position          */
-#define LCD_PAL242_G04_0_Msk                                  (0x1fUL << LCD_PAL242_G04_0_Pos)                          /*!< LCD PAL242: G04_0 Mask              */
-#define LCD_PAL242_B04_0_Pos                                  10                                                        /*!< LCD PAL242: B04_0 Position          */
-#define LCD_PAL242_B04_0_Msk                                  (0x1fUL << LCD_PAL242_B04_0_Pos)                          /*!< LCD PAL242: B04_0 Mask              */
-#define LCD_PAL242_I0_Pos                                     15                                                        /*!< LCD PAL242: I0 Position             */
-#define LCD_PAL242_I0_Msk                                     (0x01UL << LCD_PAL242_I0_Pos)                             /*!< LCD PAL242: I0 Mask                 */
-#define LCD_PAL242_R14_0_Pos                                  16                                                        /*!< LCD PAL242: R14_0 Position          */
-#define LCD_PAL242_R14_0_Msk                                  (0x1fUL << LCD_PAL242_R14_0_Pos)                          /*!< LCD PAL242: R14_0 Mask              */
-#define LCD_PAL242_G14_0_Pos                                  21                                                        /*!< LCD PAL242: G14_0 Position          */
-#define LCD_PAL242_G14_0_Msk                                  (0x1fUL << LCD_PAL242_G14_0_Pos)                          /*!< LCD PAL242: G14_0 Mask              */
-#define LCD_PAL242_B14_0_Pos                                  26                                                        /*!< LCD PAL242: B14_0 Position          */
-#define LCD_PAL242_B14_0_Msk                                  (0x1fUL << LCD_PAL242_B14_0_Pos)                          /*!< LCD PAL242: B14_0 Mask              */
-#define LCD_PAL242_I1_Pos                                     31                                                        /*!< LCD PAL242: I1 Position             */
-#define LCD_PAL242_I1_Msk                                     (0x01UL << LCD_PAL242_I1_Pos)                             /*!< LCD PAL242: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL243  -------------------------------------------
-#define LCD_PAL243_R04_0_Pos                                  0                                                         /*!< LCD PAL243: R04_0 Position          */
-#define LCD_PAL243_R04_0_Msk                                  (0x1fUL << LCD_PAL243_R04_0_Pos)                          /*!< LCD PAL243: R04_0 Mask              */
-#define LCD_PAL243_G04_0_Pos                                  5                                                         /*!< LCD PAL243: G04_0 Position          */
-#define LCD_PAL243_G04_0_Msk                                  (0x1fUL << LCD_PAL243_G04_0_Pos)                          /*!< LCD PAL243: G04_0 Mask              */
-#define LCD_PAL243_B04_0_Pos                                  10                                                        /*!< LCD PAL243: B04_0 Position          */
-#define LCD_PAL243_B04_0_Msk                                  (0x1fUL << LCD_PAL243_B04_0_Pos)                          /*!< LCD PAL243: B04_0 Mask              */
-#define LCD_PAL243_I0_Pos                                     15                                                        /*!< LCD PAL243: I0 Position             */
-#define LCD_PAL243_I0_Msk                                     (0x01UL << LCD_PAL243_I0_Pos)                             /*!< LCD PAL243: I0 Mask                 */
-#define LCD_PAL243_R14_0_Pos                                  16                                                        /*!< LCD PAL243: R14_0 Position          */
-#define LCD_PAL243_R14_0_Msk                                  (0x1fUL << LCD_PAL243_R14_0_Pos)                          /*!< LCD PAL243: R14_0 Mask              */
-#define LCD_PAL243_G14_0_Pos                                  21                                                        /*!< LCD PAL243: G14_0 Position          */
-#define LCD_PAL243_G14_0_Msk                                  (0x1fUL << LCD_PAL243_G14_0_Pos)                          /*!< LCD PAL243: G14_0 Mask              */
-#define LCD_PAL243_B14_0_Pos                                  26                                                        /*!< LCD PAL243: B14_0 Position          */
-#define LCD_PAL243_B14_0_Msk                                  (0x1fUL << LCD_PAL243_B14_0_Pos)                          /*!< LCD PAL243: B14_0 Mask              */
-#define LCD_PAL243_I1_Pos                                     31                                                        /*!< LCD PAL243: I1 Position             */
-#define LCD_PAL243_I1_Msk                                     (0x01UL << LCD_PAL243_I1_Pos)                             /*!< LCD PAL243: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL244  -------------------------------------------
-#define LCD_PAL244_R04_0_Pos                                  0                                                         /*!< LCD PAL244: R04_0 Position          */
-#define LCD_PAL244_R04_0_Msk                                  (0x1fUL << LCD_PAL244_R04_0_Pos)                          /*!< LCD PAL244: R04_0 Mask              */
-#define LCD_PAL244_G04_0_Pos                                  5                                                         /*!< LCD PAL244: G04_0 Position          */
-#define LCD_PAL244_G04_0_Msk                                  (0x1fUL << LCD_PAL244_G04_0_Pos)                          /*!< LCD PAL244: G04_0 Mask              */
-#define LCD_PAL244_B04_0_Pos                                  10                                                        /*!< LCD PAL244: B04_0 Position          */
-#define LCD_PAL244_B04_0_Msk                                  (0x1fUL << LCD_PAL244_B04_0_Pos)                          /*!< LCD PAL244: B04_0 Mask              */
-#define LCD_PAL244_I0_Pos                                     15                                                        /*!< LCD PAL244: I0 Position             */
-#define LCD_PAL244_I0_Msk                                     (0x01UL << LCD_PAL244_I0_Pos)                             /*!< LCD PAL244: I0 Mask                 */
-#define LCD_PAL244_R14_0_Pos                                  16                                                        /*!< LCD PAL244: R14_0 Position          */
-#define LCD_PAL244_R14_0_Msk                                  (0x1fUL << LCD_PAL244_R14_0_Pos)                          /*!< LCD PAL244: R14_0 Mask              */
-#define LCD_PAL244_G14_0_Pos                                  21                                                        /*!< LCD PAL244: G14_0 Position          */
-#define LCD_PAL244_G14_0_Msk                                  (0x1fUL << LCD_PAL244_G14_0_Pos)                          /*!< LCD PAL244: G14_0 Mask              */
-#define LCD_PAL244_B14_0_Pos                                  26                                                        /*!< LCD PAL244: B14_0 Position          */
-#define LCD_PAL244_B14_0_Msk                                  (0x1fUL << LCD_PAL244_B14_0_Pos)                          /*!< LCD PAL244: B14_0 Mask              */
-#define LCD_PAL244_I1_Pos                                     31                                                        /*!< LCD PAL244: I1 Position             */
-#define LCD_PAL244_I1_Msk                                     (0x01UL << LCD_PAL244_I1_Pos)                             /*!< LCD PAL244: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL245  -------------------------------------------
-#define LCD_PAL245_R04_0_Pos                                  0                                                         /*!< LCD PAL245: R04_0 Position          */
-#define LCD_PAL245_R04_0_Msk                                  (0x1fUL << LCD_PAL245_R04_0_Pos)                          /*!< LCD PAL245: R04_0 Mask              */
-#define LCD_PAL245_G04_0_Pos                                  5                                                         /*!< LCD PAL245: G04_0 Position          */
-#define LCD_PAL245_G04_0_Msk                                  (0x1fUL << LCD_PAL245_G04_0_Pos)                          /*!< LCD PAL245: G04_0 Mask              */
-#define LCD_PAL245_B04_0_Pos                                  10                                                        /*!< LCD PAL245: B04_0 Position          */
-#define LCD_PAL245_B04_0_Msk                                  (0x1fUL << LCD_PAL245_B04_0_Pos)                          /*!< LCD PAL245: B04_0 Mask              */
-#define LCD_PAL245_I0_Pos                                     15                                                        /*!< LCD PAL245: I0 Position             */
-#define LCD_PAL245_I0_Msk                                     (0x01UL << LCD_PAL245_I0_Pos)                             /*!< LCD PAL245: I0 Mask                 */
-#define LCD_PAL245_R14_0_Pos                                  16                                                        /*!< LCD PAL245: R14_0 Position          */
-#define LCD_PAL245_R14_0_Msk                                  (0x1fUL << LCD_PAL245_R14_0_Pos)                          /*!< LCD PAL245: R14_0 Mask              */
-#define LCD_PAL245_G14_0_Pos                                  21                                                        /*!< LCD PAL245: G14_0 Position          */
-#define LCD_PAL245_G14_0_Msk                                  (0x1fUL << LCD_PAL245_G14_0_Pos)                          /*!< LCD PAL245: G14_0 Mask              */
-#define LCD_PAL245_B14_0_Pos                                  26                                                        /*!< LCD PAL245: B14_0 Position          */
-#define LCD_PAL245_B14_0_Msk                                  (0x1fUL << LCD_PAL245_B14_0_Pos)                          /*!< LCD PAL245: B14_0 Mask              */
-#define LCD_PAL245_I1_Pos                                     31                                                        /*!< LCD PAL245: I1 Position             */
-#define LCD_PAL245_I1_Msk                                     (0x01UL << LCD_PAL245_I1_Pos)                             /*!< LCD PAL245: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL246  -------------------------------------------
-#define LCD_PAL246_R04_0_Pos                                  0                                                         /*!< LCD PAL246: R04_0 Position          */
-#define LCD_PAL246_R04_0_Msk                                  (0x1fUL << LCD_PAL246_R04_0_Pos)                          /*!< LCD PAL246: R04_0 Mask              */
-#define LCD_PAL246_G04_0_Pos                                  5                                                         /*!< LCD PAL246: G04_0 Position          */
-#define LCD_PAL246_G04_0_Msk                                  (0x1fUL << LCD_PAL246_G04_0_Pos)                          /*!< LCD PAL246: G04_0 Mask              */
-#define LCD_PAL246_B04_0_Pos                                  10                                                        /*!< LCD PAL246: B04_0 Position          */
-#define LCD_PAL246_B04_0_Msk                                  (0x1fUL << LCD_PAL246_B04_0_Pos)                          /*!< LCD PAL246: B04_0 Mask              */
-#define LCD_PAL246_I0_Pos                                     15                                                        /*!< LCD PAL246: I0 Position             */
-#define LCD_PAL246_I0_Msk                                     (0x01UL << LCD_PAL246_I0_Pos)                             /*!< LCD PAL246: I0 Mask                 */
-#define LCD_PAL246_R14_0_Pos                                  16                                                        /*!< LCD PAL246: R14_0 Position          */
-#define LCD_PAL246_R14_0_Msk                                  (0x1fUL << LCD_PAL246_R14_0_Pos)                          /*!< LCD PAL246: R14_0 Mask              */
-#define LCD_PAL246_G14_0_Pos                                  21                                                        /*!< LCD PAL246: G14_0 Position          */
-#define LCD_PAL246_G14_0_Msk                                  (0x1fUL << LCD_PAL246_G14_0_Pos)                          /*!< LCD PAL246: G14_0 Mask              */
-#define LCD_PAL246_B14_0_Pos                                  26                                                        /*!< LCD PAL246: B14_0 Position          */
-#define LCD_PAL246_B14_0_Msk                                  (0x1fUL << LCD_PAL246_B14_0_Pos)                          /*!< LCD PAL246: B14_0 Mask              */
-#define LCD_PAL246_I1_Pos                                     31                                                        /*!< LCD PAL246: I1 Position             */
-#define LCD_PAL246_I1_Msk                                     (0x01UL << LCD_PAL246_I1_Pos)                             /*!< LCD PAL246: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL247  -------------------------------------------
-#define LCD_PAL247_R04_0_Pos                                  0                                                         /*!< LCD PAL247: R04_0 Position          */
-#define LCD_PAL247_R04_0_Msk                                  (0x1fUL << LCD_PAL247_R04_0_Pos)                          /*!< LCD PAL247: R04_0 Mask              */
-#define LCD_PAL247_G04_0_Pos                                  5                                                         /*!< LCD PAL247: G04_0 Position          */
-#define LCD_PAL247_G04_0_Msk                                  (0x1fUL << LCD_PAL247_G04_0_Pos)                          /*!< LCD PAL247: G04_0 Mask              */
-#define LCD_PAL247_B04_0_Pos                                  10                                                        /*!< LCD PAL247: B04_0 Position          */
-#define LCD_PAL247_B04_0_Msk                                  (0x1fUL << LCD_PAL247_B04_0_Pos)                          /*!< LCD PAL247: B04_0 Mask              */
-#define LCD_PAL247_I0_Pos                                     15                                                        /*!< LCD PAL247: I0 Position             */
-#define LCD_PAL247_I0_Msk                                     (0x01UL << LCD_PAL247_I0_Pos)                             /*!< LCD PAL247: I0 Mask                 */
-#define LCD_PAL247_R14_0_Pos                                  16                                                        /*!< LCD PAL247: R14_0 Position          */
-#define LCD_PAL247_R14_0_Msk                                  (0x1fUL << LCD_PAL247_R14_0_Pos)                          /*!< LCD PAL247: R14_0 Mask              */
-#define LCD_PAL247_G14_0_Pos                                  21                                                        /*!< LCD PAL247: G14_0 Position          */
-#define LCD_PAL247_G14_0_Msk                                  (0x1fUL << LCD_PAL247_G14_0_Pos)                          /*!< LCD PAL247: G14_0 Mask              */
-#define LCD_PAL247_B14_0_Pos                                  26                                                        /*!< LCD PAL247: B14_0 Position          */
-#define LCD_PAL247_B14_0_Msk                                  (0x1fUL << LCD_PAL247_B14_0_Pos)                          /*!< LCD PAL247: B14_0 Mask              */
-#define LCD_PAL247_I1_Pos                                     31                                                        /*!< LCD PAL247: I1 Position             */
-#define LCD_PAL247_I1_Msk                                     (0x01UL << LCD_PAL247_I1_Pos)                             /*!< LCD PAL247: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL248  -------------------------------------------
-#define LCD_PAL248_R04_0_Pos                                  0                                                         /*!< LCD PAL248: R04_0 Position          */
-#define LCD_PAL248_R04_0_Msk                                  (0x1fUL << LCD_PAL248_R04_0_Pos)                          /*!< LCD PAL248: R04_0 Mask              */
-#define LCD_PAL248_G04_0_Pos                                  5                                                         /*!< LCD PAL248: G04_0 Position          */
-#define LCD_PAL248_G04_0_Msk                                  (0x1fUL << LCD_PAL248_G04_0_Pos)                          /*!< LCD PAL248: G04_0 Mask              */
-#define LCD_PAL248_B04_0_Pos                                  10                                                        /*!< LCD PAL248: B04_0 Position          */
-#define LCD_PAL248_B04_0_Msk                                  (0x1fUL << LCD_PAL248_B04_0_Pos)                          /*!< LCD PAL248: B04_0 Mask              */
-#define LCD_PAL248_I0_Pos                                     15                                                        /*!< LCD PAL248: I0 Position             */
-#define LCD_PAL248_I0_Msk                                     (0x01UL << LCD_PAL248_I0_Pos)                             /*!< LCD PAL248: I0 Mask                 */
-#define LCD_PAL248_R14_0_Pos                                  16                                                        /*!< LCD PAL248: R14_0 Position          */
-#define LCD_PAL248_R14_0_Msk                                  (0x1fUL << LCD_PAL248_R14_0_Pos)                          /*!< LCD PAL248: R14_0 Mask              */
-#define LCD_PAL248_G14_0_Pos                                  21                                                        /*!< LCD PAL248: G14_0 Position          */
-#define LCD_PAL248_G14_0_Msk                                  (0x1fUL << LCD_PAL248_G14_0_Pos)                          /*!< LCD PAL248: G14_0 Mask              */
-#define LCD_PAL248_B14_0_Pos                                  26                                                        /*!< LCD PAL248: B14_0 Position          */
-#define LCD_PAL248_B14_0_Msk                                  (0x1fUL << LCD_PAL248_B14_0_Pos)                          /*!< LCD PAL248: B14_0 Mask              */
-#define LCD_PAL248_I1_Pos                                     31                                                        /*!< LCD PAL248: I1 Position             */
-#define LCD_PAL248_I1_Msk                                     (0x01UL << LCD_PAL248_I1_Pos)                             /*!< LCD PAL248: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL249  -------------------------------------------
-#define LCD_PAL249_R04_0_Pos                                  0                                                         /*!< LCD PAL249: R04_0 Position          */
-#define LCD_PAL249_R04_0_Msk                                  (0x1fUL << LCD_PAL249_R04_0_Pos)                          /*!< LCD PAL249: R04_0 Mask              */
-#define LCD_PAL249_G04_0_Pos                                  5                                                         /*!< LCD PAL249: G04_0 Position          */
-#define LCD_PAL249_G04_0_Msk                                  (0x1fUL << LCD_PAL249_G04_0_Pos)                          /*!< LCD PAL249: G04_0 Mask              */
-#define LCD_PAL249_B04_0_Pos                                  10                                                        /*!< LCD PAL249: B04_0 Position          */
-#define LCD_PAL249_B04_0_Msk                                  (0x1fUL << LCD_PAL249_B04_0_Pos)                          /*!< LCD PAL249: B04_0 Mask              */
-#define LCD_PAL249_I0_Pos                                     15                                                        /*!< LCD PAL249: I0 Position             */
-#define LCD_PAL249_I0_Msk                                     (0x01UL << LCD_PAL249_I0_Pos)                             /*!< LCD PAL249: I0 Mask                 */
-#define LCD_PAL249_R14_0_Pos                                  16                                                        /*!< LCD PAL249: R14_0 Position          */
-#define LCD_PAL249_R14_0_Msk                                  (0x1fUL << LCD_PAL249_R14_0_Pos)                          /*!< LCD PAL249: R14_0 Mask              */
-#define LCD_PAL249_G14_0_Pos                                  21                                                        /*!< LCD PAL249: G14_0 Position          */
-#define LCD_PAL249_G14_0_Msk                                  (0x1fUL << LCD_PAL249_G14_0_Pos)                          /*!< LCD PAL249: G14_0 Mask              */
-#define LCD_PAL249_B14_0_Pos                                  26                                                        /*!< LCD PAL249: B14_0 Position          */
-#define LCD_PAL249_B14_0_Msk                                  (0x1fUL << LCD_PAL249_B14_0_Pos)                          /*!< LCD PAL249: B14_0 Mask              */
-#define LCD_PAL249_I1_Pos                                     31                                                        /*!< LCD PAL249: I1 Position             */
-#define LCD_PAL249_I1_Msk                                     (0x01UL << LCD_PAL249_I1_Pos)                             /*!< LCD PAL249: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL250  -------------------------------------------
-#define LCD_PAL250_R04_0_Pos                                  0                                                         /*!< LCD PAL250: R04_0 Position          */
-#define LCD_PAL250_R04_0_Msk                                  (0x1fUL << LCD_PAL250_R04_0_Pos)                          /*!< LCD PAL250: R04_0 Mask              */
-#define LCD_PAL250_G04_0_Pos                                  5                                                         /*!< LCD PAL250: G04_0 Position          */
-#define LCD_PAL250_G04_0_Msk                                  (0x1fUL << LCD_PAL250_G04_0_Pos)                          /*!< LCD PAL250: G04_0 Mask              */
-#define LCD_PAL250_B04_0_Pos                                  10                                                        /*!< LCD PAL250: B04_0 Position          */
-#define LCD_PAL250_B04_0_Msk                                  (0x1fUL << LCD_PAL250_B04_0_Pos)                          /*!< LCD PAL250: B04_0 Mask              */
-#define LCD_PAL250_I0_Pos                                     15                                                        /*!< LCD PAL250: I0 Position             */
-#define LCD_PAL250_I0_Msk                                     (0x01UL << LCD_PAL250_I0_Pos)                             /*!< LCD PAL250: I0 Mask                 */
-#define LCD_PAL250_R14_0_Pos                                  16                                                        /*!< LCD PAL250: R14_0 Position          */
-#define LCD_PAL250_R14_0_Msk                                  (0x1fUL << LCD_PAL250_R14_0_Pos)                          /*!< LCD PAL250: R14_0 Mask              */
-#define LCD_PAL250_G14_0_Pos                                  21                                                        /*!< LCD PAL250: G14_0 Position          */
-#define LCD_PAL250_G14_0_Msk                                  (0x1fUL << LCD_PAL250_G14_0_Pos)                          /*!< LCD PAL250: G14_0 Mask              */
-#define LCD_PAL250_B14_0_Pos                                  26                                                        /*!< LCD PAL250: B14_0 Position          */
-#define LCD_PAL250_B14_0_Msk                                  (0x1fUL << LCD_PAL250_B14_0_Pos)                          /*!< LCD PAL250: B14_0 Mask              */
-#define LCD_PAL250_I1_Pos                                     31                                                        /*!< LCD PAL250: I1 Position             */
-#define LCD_PAL250_I1_Msk                                     (0x01UL << LCD_PAL250_I1_Pos)                             /*!< LCD PAL250: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL251  -------------------------------------------
-#define LCD_PAL251_R04_0_Pos                                  0                                                         /*!< LCD PAL251: R04_0 Position          */
-#define LCD_PAL251_R04_0_Msk                                  (0x1fUL << LCD_PAL251_R04_0_Pos)                          /*!< LCD PAL251: R04_0 Mask              */
-#define LCD_PAL251_G04_0_Pos                                  5                                                         /*!< LCD PAL251: G04_0 Position          */
-#define LCD_PAL251_G04_0_Msk                                  (0x1fUL << LCD_PAL251_G04_0_Pos)                          /*!< LCD PAL251: G04_0 Mask              */
-#define LCD_PAL251_B04_0_Pos                                  10                                                        /*!< LCD PAL251: B04_0 Position          */
-#define LCD_PAL251_B04_0_Msk                                  (0x1fUL << LCD_PAL251_B04_0_Pos)                          /*!< LCD PAL251: B04_0 Mask              */
-#define LCD_PAL251_I0_Pos                                     15                                                        /*!< LCD PAL251: I0 Position             */
-#define LCD_PAL251_I0_Msk                                     (0x01UL << LCD_PAL251_I0_Pos)                             /*!< LCD PAL251: I0 Mask                 */
-#define LCD_PAL251_R14_0_Pos                                  16                                                        /*!< LCD PAL251: R14_0 Position          */
-#define LCD_PAL251_R14_0_Msk                                  (0x1fUL << LCD_PAL251_R14_0_Pos)                          /*!< LCD PAL251: R14_0 Mask              */
-#define LCD_PAL251_G14_0_Pos                                  21                                                        /*!< LCD PAL251: G14_0 Position          */
-#define LCD_PAL251_G14_0_Msk                                  (0x1fUL << LCD_PAL251_G14_0_Pos)                          /*!< LCD PAL251: G14_0 Mask              */
-#define LCD_PAL251_B14_0_Pos                                  26                                                        /*!< LCD PAL251: B14_0 Position          */
-#define LCD_PAL251_B14_0_Msk                                  (0x1fUL << LCD_PAL251_B14_0_Pos)                          /*!< LCD PAL251: B14_0 Mask              */
-#define LCD_PAL251_I1_Pos                                     31                                                        /*!< LCD PAL251: I1 Position             */
-#define LCD_PAL251_I1_Msk                                     (0x01UL << LCD_PAL251_I1_Pos)                             /*!< LCD PAL251: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL252  -------------------------------------------
-#define LCD_PAL252_R04_0_Pos                                  0                                                         /*!< LCD PAL252: R04_0 Position          */
-#define LCD_PAL252_R04_0_Msk                                  (0x1fUL << LCD_PAL252_R04_0_Pos)                          /*!< LCD PAL252: R04_0 Mask              */
-#define LCD_PAL252_G04_0_Pos                                  5                                                         /*!< LCD PAL252: G04_0 Position          */
-#define LCD_PAL252_G04_0_Msk                                  (0x1fUL << LCD_PAL252_G04_0_Pos)                          /*!< LCD PAL252: G04_0 Mask              */
-#define LCD_PAL252_B04_0_Pos                                  10                                                        /*!< LCD PAL252: B04_0 Position          */
-#define LCD_PAL252_B04_0_Msk                                  (0x1fUL << LCD_PAL252_B04_0_Pos)                          /*!< LCD PAL252: B04_0 Mask              */
-#define LCD_PAL252_I0_Pos                                     15                                                        /*!< LCD PAL252: I0 Position             */
-#define LCD_PAL252_I0_Msk                                     (0x01UL << LCD_PAL252_I0_Pos)                             /*!< LCD PAL252: I0 Mask                 */
-#define LCD_PAL252_R14_0_Pos                                  16                                                        /*!< LCD PAL252: R14_0 Position          */
-#define LCD_PAL252_R14_0_Msk                                  (0x1fUL << LCD_PAL252_R14_0_Pos)                          /*!< LCD PAL252: R14_0 Mask              */
-#define LCD_PAL252_G14_0_Pos                                  21                                                        /*!< LCD PAL252: G14_0 Position          */
-#define LCD_PAL252_G14_0_Msk                                  (0x1fUL << LCD_PAL252_G14_0_Pos)                          /*!< LCD PAL252: G14_0 Mask              */
-#define LCD_PAL252_B14_0_Pos                                  26                                                        /*!< LCD PAL252: B14_0 Position          */
-#define LCD_PAL252_B14_0_Msk                                  (0x1fUL << LCD_PAL252_B14_0_Pos)                          /*!< LCD PAL252: B14_0 Mask              */
-#define LCD_PAL252_I1_Pos                                     31                                                        /*!< LCD PAL252: I1 Position             */
-#define LCD_PAL252_I1_Msk                                     (0x01UL << LCD_PAL252_I1_Pos)                             /*!< LCD PAL252: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL253  -------------------------------------------
-#define LCD_PAL253_R04_0_Pos                                  0                                                         /*!< LCD PAL253: R04_0 Position          */
-#define LCD_PAL253_R04_0_Msk                                  (0x1fUL << LCD_PAL253_R04_0_Pos)                          /*!< LCD PAL253: R04_0 Mask              */
-#define LCD_PAL253_G04_0_Pos                                  5                                                         /*!< LCD PAL253: G04_0 Position          */
-#define LCD_PAL253_G04_0_Msk                                  (0x1fUL << LCD_PAL253_G04_0_Pos)                          /*!< LCD PAL253: G04_0 Mask              */
-#define LCD_PAL253_B04_0_Pos                                  10                                                        /*!< LCD PAL253: B04_0 Position          */
-#define LCD_PAL253_B04_0_Msk                                  (0x1fUL << LCD_PAL253_B04_0_Pos)                          /*!< LCD PAL253: B04_0 Mask              */
-#define LCD_PAL253_I0_Pos                                     15                                                        /*!< LCD PAL253: I0 Position             */
-#define LCD_PAL253_I0_Msk                                     (0x01UL << LCD_PAL253_I0_Pos)                             /*!< LCD PAL253: I0 Mask                 */
-#define LCD_PAL253_R14_0_Pos                                  16                                                        /*!< LCD PAL253: R14_0 Position          */
-#define LCD_PAL253_R14_0_Msk                                  (0x1fUL << LCD_PAL253_R14_0_Pos)                          /*!< LCD PAL253: R14_0 Mask              */
-#define LCD_PAL253_G14_0_Pos                                  21                                                        /*!< LCD PAL253: G14_0 Position          */
-#define LCD_PAL253_G14_0_Msk                                  (0x1fUL << LCD_PAL253_G14_0_Pos)                          /*!< LCD PAL253: G14_0 Mask              */
-#define LCD_PAL253_B14_0_Pos                                  26                                                        /*!< LCD PAL253: B14_0 Position          */
-#define LCD_PAL253_B14_0_Msk                                  (0x1fUL << LCD_PAL253_B14_0_Pos)                          /*!< LCD PAL253: B14_0 Mask              */
-#define LCD_PAL253_I1_Pos                                     31                                                        /*!< LCD PAL253: I1 Position             */
-#define LCD_PAL253_I1_Msk                                     (0x01UL << LCD_PAL253_I1_Pos)                             /*!< LCD PAL253: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL254  -------------------------------------------
-#define LCD_PAL254_R04_0_Pos                                  0                                                         /*!< LCD PAL254: R04_0 Position          */
-#define LCD_PAL254_R04_0_Msk                                  (0x1fUL << LCD_PAL254_R04_0_Pos)                          /*!< LCD PAL254: R04_0 Mask              */
-#define LCD_PAL254_G04_0_Pos                                  5                                                         /*!< LCD PAL254: G04_0 Position          */
-#define LCD_PAL254_G04_0_Msk                                  (0x1fUL << LCD_PAL254_G04_0_Pos)                          /*!< LCD PAL254: G04_0 Mask              */
-#define LCD_PAL254_B04_0_Pos                                  10                                                        /*!< LCD PAL254: B04_0 Position          */
-#define LCD_PAL254_B04_0_Msk                                  (0x1fUL << LCD_PAL254_B04_0_Pos)                          /*!< LCD PAL254: B04_0 Mask              */
-#define LCD_PAL254_I0_Pos                                     15                                                        /*!< LCD PAL254: I0 Position             */
-#define LCD_PAL254_I0_Msk                                     (0x01UL << LCD_PAL254_I0_Pos)                             /*!< LCD PAL254: I0 Mask                 */
-#define LCD_PAL254_R14_0_Pos                                  16                                                        /*!< LCD PAL254: R14_0 Position          */
-#define LCD_PAL254_R14_0_Msk                                  (0x1fUL << LCD_PAL254_R14_0_Pos)                          /*!< LCD PAL254: R14_0 Mask              */
-#define LCD_PAL254_G14_0_Pos                                  21                                                        /*!< LCD PAL254: G14_0 Position          */
-#define LCD_PAL254_G14_0_Msk                                  (0x1fUL << LCD_PAL254_G14_0_Pos)                          /*!< LCD PAL254: G14_0 Mask              */
-#define LCD_PAL254_B14_0_Pos                                  26                                                        /*!< LCD PAL254: B14_0 Position          */
-#define LCD_PAL254_B14_0_Msk                                  (0x1fUL << LCD_PAL254_B14_0_Pos)                          /*!< LCD PAL254: B14_0 Mask              */
-#define LCD_PAL254_I1_Pos                                     31                                                        /*!< LCD PAL254: I1 Position             */
-#define LCD_PAL254_I1_Msk                                     (0x01UL << LCD_PAL254_I1_Pos)                             /*!< LCD PAL254: I1 Mask                 */
-
-// ---------------------------------------  LCD_PAL255  -------------------------------------------
-#define LCD_PAL255_R04_0_Pos                                  0                                                         /*!< LCD PAL255: R04_0 Position          */
-#define LCD_PAL255_R04_0_Msk                                  (0x1fUL << LCD_PAL255_R04_0_Pos)                          /*!< LCD PAL255: R04_0 Mask              */
-#define LCD_PAL255_G04_0_Pos                                  5                                                         /*!< LCD PAL255: G04_0 Position          */
-#define LCD_PAL255_G04_0_Msk                                  (0x1fUL << LCD_PAL255_G04_0_Pos)                          /*!< LCD PAL255: G04_0 Mask              */
-#define LCD_PAL255_B04_0_Pos                                  10                                                        /*!< LCD PAL255: B04_0 Position          */
-#define LCD_PAL255_B04_0_Msk                                  (0x1fUL << LCD_PAL255_B04_0_Pos)                          /*!< LCD PAL255: B04_0 Mask              */
-#define LCD_PAL255_I0_Pos                                     15                                                        /*!< LCD PAL255: I0 Position             */
-#define LCD_PAL255_I0_Msk                                     (0x01UL << LCD_PAL255_I0_Pos)                             /*!< LCD PAL255: I0 Mask                 */
-#define LCD_PAL255_R14_0_Pos                                  16                                                        /*!< LCD PAL255: R14_0 Position          */
-#define LCD_PAL255_R14_0_Msk                                  (0x1fUL << LCD_PAL255_R14_0_Pos)                          /*!< LCD PAL255: R14_0 Mask              */
-#define LCD_PAL255_G14_0_Pos                                  21                                                        /*!< LCD PAL255: G14_0 Position          */
-#define LCD_PAL255_G14_0_Msk                                  (0x1fUL << LCD_PAL255_G14_0_Pos)                          /*!< LCD PAL255: G14_0 Mask              */
-#define LCD_PAL255_B14_0_Pos                                  26                                                        /*!< LCD PAL255: B14_0 Position          */
-#define LCD_PAL255_B14_0_Msk                                  (0x1fUL << LCD_PAL255_B14_0_Pos)                          /*!< LCD PAL255: B14_0 Mask              */
-#define LCD_PAL255_I1_Pos                                     31                                                        /*!< LCD PAL255: I1 Position             */
-#define LCD_PAL255_I1_Msk                                     (0x01UL << LCD_PAL255_I1_Pos)                             /*!< LCD PAL255: I1 Mask                 */
-
-// --------------------------------------  LCD_CRSR_IMG0  -----------------------------------------
-#define LCD_CRSR_IMG0_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG0: CRSR_IMG Position    */
-#define LCD_CRSR_IMG0_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG0: CRSR_IMG Mask        */
-
-// --------------------------------------  LCD_CRSR_IMG1  -----------------------------------------
-#define LCD_CRSR_IMG1_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG1: CRSR_IMG Position    */
-#define LCD_CRSR_IMG1_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG1: CRSR_IMG Mask        */
-
-// --------------------------------------  LCD_CRSR_IMG2  -----------------------------------------
-#define LCD_CRSR_IMG2_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG2: CRSR_IMG Position    */
-#define LCD_CRSR_IMG2_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG2: CRSR_IMG Mask        */
-
-// --------------------------------------  LCD_CRSR_IMG3  -----------------------------------------
-#define LCD_CRSR_IMG3_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG3: CRSR_IMG Position    */
-#define LCD_CRSR_IMG3_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG3: CRSR_IMG Mask        */
-
-// --------------------------------------  LCD_CRSR_IMG4  -----------------------------------------
-#define LCD_CRSR_IMG4_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG4: CRSR_IMG Position    */
-#define LCD_CRSR_IMG4_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG4: CRSR_IMG Mask        */
-
-// --------------------------------------  LCD_CRSR_IMG5  -----------------------------------------
-#define LCD_CRSR_IMG5_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG5: CRSR_IMG Position    */
-#define LCD_CRSR_IMG5_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG5: CRSR_IMG Mask        */
-
-// --------------------------------------  LCD_CRSR_IMG6  -----------------------------------------
-#define LCD_CRSR_IMG6_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG6: CRSR_IMG Position    */
-#define LCD_CRSR_IMG6_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG6: CRSR_IMG Mask        */
-
-// --------------------------------------  LCD_CRSR_IMG7  -----------------------------------------
-#define LCD_CRSR_IMG7_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG7: CRSR_IMG Position    */
-#define LCD_CRSR_IMG7_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG7: CRSR_IMG Mask        */
-
-// --------------------------------------  LCD_CRSR_IMG8  -----------------------------------------
-#define LCD_CRSR_IMG8_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG8: CRSR_IMG Position    */
-#define LCD_CRSR_IMG8_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG8: CRSR_IMG Mask        */
-
-// --------------------------------------  LCD_CRSR_IMG9  -----------------------------------------
-#define LCD_CRSR_IMG9_CRSR_IMG_Pos                            0                                                         /*!< LCD CRSR_IMG9: CRSR_IMG Position    */
-#define LCD_CRSR_IMG9_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos)              /*!< LCD CRSR_IMG9: CRSR_IMG Mask        */
-
-// -------------------------------------  LCD_CRSR_IMG10  -----------------------------------------
-#define LCD_CRSR_IMG10_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG10: CRSR_IMG Position   */
-#define LCD_CRSR_IMG10_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG10: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG11  -----------------------------------------
-#define LCD_CRSR_IMG11_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG11: CRSR_IMG Position   */
-#define LCD_CRSR_IMG11_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG11: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG12  -----------------------------------------
-#define LCD_CRSR_IMG12_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG12: CRSR_IMG Position   */
-#define LCD_CRSR_IMG12_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG12: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG13  -----------------------------------------
-#define LCD_CRSR_IMG13_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG13: CRSR_IMG Position   */
-#define LCD_CRSR_IMG13_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG13: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG14  -----------------------------------------
-#define LCD_CRSR_IMG14_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG14: CRSR_IMG Position   */
-#define LCD_CRSR_IMG14_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG14: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG15  -----------------------------------------
-#define LCD_CRSR_IMG15_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG15: CRSR_IMG Position   */
-#define LCD_CRSR_IMG15_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG15: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG16  -----------------------------------------
-#define LCD_CRSR_IMG16_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG16: CRSR_IMG Position   */
-#define LCD_CRSR_IMG16_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG16: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG17  -----------------------------------------
-#define LCD_CRSR_IMG17_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG17: CRSR_IMG Position   */
-#define LCD_CRSR_IMG17_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG17: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG18  -----------------------------------------
-#define LCD_CRSR_IMG18_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG18: CRSR_IMG Position   */
-#define LCD_CRSR_IMG18_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG18: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG19  -----------------------------------------
-#define LCD_CRSR_IMG19_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG19: CRSR_IMG Position   */
-#define LCD_CRSR_IMG19_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG19: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG20  -----------------------------------------
-#define LCD_CRSR_IMG20_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG20: CRSR_IMG Position   */
-#define LCD_CRSR_IMG20_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG20: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG21  -----------------------------------------
-#define LCD_CRSR_IMG21_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG21: CRSR_IMG Position   */
-#define LCD_CRSR_IMG21_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG21: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG22  -----------------------------------------
-#define LCD_CRSR_IMG22_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG22: CRSR_IMG Position   */
-#define LCD_CRSR_IMG22_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG22: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG23  -----------------------------------------
-#define LCD_CRSR_IMG23_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG23: CRSR_IMG Position   */
-#define LCD_CRSR_IMG23_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG23: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG24  -----------------------------------------
-#define LCD_CRSR_IMG24_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG24: CRSR_IMG Position   */
-#define LCD_CRSR_IMG24_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG24: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG25  -----------------------------------------
-#define LCD_CRSR_IMG25_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG25: CRSR_IMG Position   */
-#define LCD_CRSR_IMG25_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG25: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG26  -----------------------------------------
-#define LCD_CRSR_IMG26_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG26: CRSR_IMG Position   */
-#define LCD_CRSR_IMG26_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG26: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG27  -----------------------------------------
-#define LCD_CRSR_IMG27_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG27: CRSR_IMG Position   */
-#define LCD_CRSR_IMG27_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG27: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG28  -----------------------------------------
-#define LCD_CRSR_IMG28_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG28: CRSR_IMG Position   */
-#define LCD_CRSR_IMG28_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG28: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG29  -----------------------------------------
-#define LCD_CRSR_IMG29_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG29: CRSR_IMG Position   */
-#define LCD_CRSR_IMG29_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG29: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG30  -----------------------------------------
-#define LCD_CRSR_IMG30_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG30: CRSR_IMG Position   */
-#define LCD_CRSR_IMG30_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG30: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG31  -----------------------------------------
-#define LCD_CRSR_IMG31_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG31: CRSR_IMG Position   */
-#define LCD_CRSR_IMG31_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG31: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG32  -----------------------------------------
-#define LCD_CRSR_IMG32_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG32: CRSR_IMG Position   */
-#define LCD_CRSR_IMG32_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG32: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG33  -----------------------------------------
-#define LCD_CRSR_IMG33_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG33: CRSR_IMG Position   */
-#define LCD_CRSR_IMG33_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG33: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG34  -----------------------------------------
-#define LCD_CRSR_IMG34_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG34: CRSR_IMG Position   */
-#define LCD_CRSR_IMG34_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG34: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG35  -----------------------------------------
-#define LCD_CRSR_IMG35_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG35: CRSR_IMG Position   */
-#define LCD_CRSR_IMG35_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG35: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG36  -----------------------------------------
-#define LCD_CRSR_IMG36_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG36: CRSR_IMG Position   */
-#define LCD_CRSR_IMG36_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG36: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG37  -----------------------------------------
-#define LCD_CRSR_IMG37_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG37: CRSR_IMG Position   */
-#define LCD_CRSR_IMG37_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG37: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG38  -----------------------------------------
-#define LCD_CRSR_IMG38_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG38: CRSR_IMG Position   */
-#define LCD_CRSR_IMG38_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG38: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG39  -----------------------------------------
-#define LCD_CRSR_IMG39_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG39: CRSR_IMG Position   */
-#define LCD_CRSR_IMG39_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG39: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG40  -----------------------------------------
-#define LCD_CRSR_IMG40_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG40: CRSR_IMG Position   */
-#define LCD_CRSR_IMG40_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG40: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG41  -----------------------------------------
-#define LCD_CRSR_IMG41_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG41: CRSR_IMG Position   */
-#define LCD_CRSR_IMG41_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG41: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG42  -----------------------------------------
-#define LCD_CRSR_IMG42_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG42: CRSR_IMG Position   */
-#define LCD_CRSR_IMG42_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG42: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG43  -----------------------------------------
-#define LCD_CRSR_IMG43_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG43: CRSR_IMG Position   */
-#define LCD_CRSR_IMG43_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG43: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG44  -----------------------------------------
-#define LCD_CRSR_IMG44_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG44: CRSR_IMG Position   */
-#define LCD_CRSR_IMG44_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG44: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG45  -----------------------------------------
-#define LCD_CRSR_IMG45_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG45: CRSR_IMG Position   */
-#define LCD_CRSR_IMG45_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG45: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG46  -----------------------------------------
-#define LCD_CRSR_IMG46_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG46: CRSR_IMG Position   */
-#define LCD_CRSR_IMG46_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG46: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG47  -----------------------------------------
-#define LCD_CRSR_IMG47_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG47: CRSR_IMG Position   */
-#define LCD_CRSR_IMG47_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG47: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG48  -----------------------------------------
-#define LCD_CRSR_IMG48_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG48: CRSR_IMG Position   */
-#define LCD_CRSR_IMG48_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG48: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG49  -----------------------------------------
-#define LCD_CRSR_IMG49_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG49: CRSR_IMG Position   */
-#define LCD_CRSR_IMG49_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG49: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG50  -----------------------------------------
-#define LCD_CRSR_IMG50_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG50: CRSR_IMG Position   */
-#define LCD_CRSR_IMG50_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG50: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG51  -----------------------------------------
-#define LCD_CRSR_IMG51_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG51: CRSR_IMG Position   */
-#define LCD_CRSR_IMG51_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG51: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG52  -----------------------------------------
-#define LCD_CRSR_IMG52_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG52: CRSR_IMG Position   */
-#define LCD_CRSR_IMG52_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG52: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG53  -----------------------------------------
-#define LCD_CRSR_IMG53_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG53: CRSR_IMG Position   */
-#define LCD_CRSR_IMG53_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG53: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG54  -----------------------------------------
-#define LCD_CRSR_IMG54_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG54: CRSR_IMG Position   */
-#define LCD_CRSR_IMG54_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG54: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG55  -----------------------------------------
-#define LCD_CRSR_IMG55_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG55: CRSR_IMG Position   */
-#define LCD_CRSR_IMG55_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG55: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG56  -----------------------------------------
-#define LCD_CRSR_IMG56_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG56: CRSR_IMG Position   */
-#define LCD_CRSR_IMG56_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG56: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG57  -----------------------------------------
-#define LCD_CRSR_IMG57_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG57: CRSR_IMG Position   */
-#define LCD_CRSR_IMG57_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG57: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG58  -----------------------------------------
-#define LCD_CRSR_IMG58_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG58: CRSR_IMG Position   */
-#define LCD_CRSR_IMG58_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG58: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG59  -----------------------------------------
-#define LCD_CRSR_IMG59_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG59: CRSR_IMG Position   */
-#define LCD_CRSR_IMG59_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG59: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG60  -----------------------------------------
-#define LCD_CRSR_IMG60_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG60: CRSR_IMG Position   */
-#define LCD_CRSR_IMG60_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG60: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG61  -----------------------------------------
-#define LCD_CRSR_IMG61_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG61: CRSR_IMG Position   */
-#define LCD_CRSR_IMG61_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG61: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG62  -----------------------------------------
-#define LCD_CRSR_IMG62_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG62: CRSR_IMG Position   */
-#define LCD_CRSR_IMG62_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG62: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG63  -----------------------------------------
-#define LCD_CRSR_IMG63_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG63: CRSR_IMG Position   */
-#define LCD_CRSR_IMG63_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG63: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG64  -----------------------------------------
-#define LCD_CRSR_IMG64_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG64: CRSR_IMG Position   */
-#define LCD_CRSR_IMG64_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG64: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG65  -----------------------------------------
-#define LCD_CRSR_IMG65_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG65: CRSR_IMG Position   */
-#define LCD_CRSR_IMG65_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG65: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG66  -----------------------------------------
-#define LCD_CRSR_IMG66_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG66: CRSR_IMG Position   */
-#define LCD_CRSR_IMG66_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG66: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG67  -----------------------------------------
-#define LCD_CRSR_IMG67_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG67: CRSR_IMG Position   */
-#define LCD_CRSR_IMG67_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG67: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG68  -----------------------------------------
-#define LCD_CRSR_IMG68_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG68: CRSR_IMG Position   */
-#define LCD_CRSR_IMG68_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG68: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG69  -----------------------------------------
-#define LCD_CRSR_IMG69_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG69: CRSR_IMG Position   */
-#define LCD_CRSR_IMG69_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG69: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG70  -----------------------------------------
-#define LCD_CRSR_IMG70_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG70: CRSR_IMG Position   */
-#define LCD_CRSR_IMG70_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG70: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG71  -----------------------------------------
-#define LCD_CRSR_IMG71_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG71: CRSR_IMG Position   */
-#define LCD_CRSR_IMG71_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG71: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG72  -----------------------------------------
-#define LCD_CRSR_IMG72_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG72: CRSR_IMG Position   */
-#define LCD_CRSR_IMG72_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG72: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG73  -----------------------------------------
-#define LCD_CRSR_IMG73_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG73: CRSR_IMG Position   */
-#define LCD_CRSR_IMG73_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG73: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG74  -----------------------------------------
-#define LCD_CRSR_IMG74_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG74: CRSR_IMG Position   */
-#define LCD_CRSR_IMG74_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG74: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG75  -----------------------------------------
-#define LCD_CRSR_IMG75_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG75: CRSR_IMG Position   */
-#define LCD_CRSR_IMG75_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG75: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG76  -----------------------------------------
-#define LCD_CRSR_IMG76_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG76: CRSR_IMG Position   */
-#define LCD_CRSR_IMG76_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG76: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG77  -----------------------------------------
-#define LCD_CRSR_IMG77_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG77: CRSR_IMG Position   */
-#define LCD_CRSR_IMG77_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG77: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG78  -----------------------------------------
-#define LCD_CRSR_IMG78_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG78: CRSR_IMG Position   */
-#define LCD_CRSR_IMG78_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG78: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG79  -----------------------------------------
-#define LCD_CRSR_IMG79_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG79: CRSR_IMG Position   */
-#define LCD_CRSR_IMG79_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG79: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG80  -----------------------------------------
-#define LCD_CRSR_IMG80_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG80: CRSR_IMG Position   */
-#define LCD_CRSR_IMG80_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG80: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG81  -----------------------------------------
-#define LCD_CRSR_IMG81_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG81: CRSR_IMG Position   */
-#define LCD_CRSR_IMG81_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG81: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG82  -----------------------------------------
-#define LCD_CRSR_IMG82_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG82: CRSR_IMG Position   */
-#define LCD_CRSR_IMG82_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG82: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG83  -----------------------------------------
-#define LCD_CRSR_IMG83_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG83: CRSR_IMG Position   */
-#define LCD_CRSR_IMG83_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG83: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG84  -----------------------------------------
-#define LCD_CRSR_IMG84_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG84: CRSR_IMG Position   */
-#define LCD_CRSR_IMG84_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG84: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG85  -----------------------------------------
-#define LCD_CRSR_IMG85_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG85: CRSR_IMG Position   */
-#define LCD_CRSR_IMG85_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG85: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG86  -----------------------------------------
-#define LCD_CRSR_IMG86_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG86: CRSR_IMG Position   */
-#define LCD_CRSR_IMG86_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG86: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG87  -----------------------------------------
-#define LCD_CRSR_IMG87_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG87: CRSR_IMG Position   */
-#define LCD_CRSR_IMG87_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG87: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG88  -----------------------------------------
-#define LCD_CRSR_IMG88_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG88: CRSR_IMG Position   */
-#define LCD_CRSR_IMG88_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG88: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG89  -----------------------------------------
-#define LCD_CRSR_IMG89_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG89: CRSR_IMG Position   */
-#define LCD_CRSR_IMG89_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG89: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG90  -----------------------------------------
-#define LCD_CRSR_IMG90_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG90: CRSR_IMG Position   */
-#define LCD_CRSR_IMG90_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG90: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG91  -----------------------------------------
-#define LCD_CRSR_IMG91_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG91: CRSR_IMG Position   */
-#define LCD_CRSR_IMG91_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG91: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG92  -----------------------------------------
-#define LCD_CRSR_IMG92_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG92: CRSR_IMG Position   */
-#define LCD_CRSR_IMG92_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG92: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG93  -----------------------------------------
-#define LCD_CRSR_IMG93_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG93: CRSR_IMG Position   */
-#define LCD_CRSR_IMG93_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG93: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG94  -----------------------------------------
-#define LCD_CRSR_IMG94_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG94: CRSR_IMG Position   */
-#define LCD_CRSR_IMG94_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG94: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG95  -----------------------------------------
-#define LCD_CRSR_IMG95_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG95: CRSR_IMG Position   */
-#define LCD_CRSR_IMG95_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG95: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG96  -----------------------------------------
-#define LCD_CRSR_IMG96_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG96: CRSR_IMG Position   */
-#define LCD_CRSR_IMG96_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG96: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG97  -----------------------------------------
-#define LCD_CRSR_IMG97_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG97: CRSR_IMG Position   */
-#define LCD_CRSR_IMG97_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG97: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG98  -----------------------------------------
-#define LCD_CRSR_IMG98_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG98: CRSR_IMG Position   */
-#define LCD_CRSR_IMG98_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG98: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG99  -----------------------------------------
-#define LCD_CRSR_IMG99_CRSR_IMG_Pos                           0                                                         /*!< LCD CRSR_IMG99: CRSR_IMG Position   */
-#define LCD_CRSR_IMG99_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos)             /*!< LCD CRSR_IMG99: CRSR_IMG Mask       */
-
-// -------------------------------------  LCD_CRSR_IMG100  ----------------------------------------
-#define LCD_CRSR_IMG100_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG100: CRSR_IMG Position  */
-#define LCD_CRSR_IMG100_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG100: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG101  ----------------------------------------
-#define LCD_CRSR_IMG101_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG101: CRSR_IMG Position  */
-#define LCD_CRSR_IMG101_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG101: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG102  ----------------------------------------
-#define LCD_CRSR_IMG102_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG102: CRSR_IMG Position  */
-#define LCD_CRSR_IMG102_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG102: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG103  ----------------------------------------
-#define LCD_CRSR_IMG103_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG103: CRSR_IMG Position  */
-#define LCD_CRSR_IMG103_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG103: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG104  ----------------------------------------
-#define LCD_CRSR_IMG104_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG104: CRSR_IMG Position  */
-#define LCD_CRSR_IMG104_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG104: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG105  ----------------------------------------
-#define LCD_CRSR_IMG105_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG105: CRSR_IMG Position  */
-#define LCD_CRSR_IMG105_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG105: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG106  ----------------------------------------
-#define LCD_CRSR_IMG106_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG106: CRSR_IMG Position  */
-#define LCD_CRSR_IMG106_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG106: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG107  ----------------------------------------
-#define LCD_CRSR_IMG107_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG107: CRSR_IMG Position  */
-#define LCD_CRSR_IMG107_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG107: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG108  ----------------------------------------
-#define LCD_CRSR_IMG108_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG108: CRSR_IMG Position  */
-#define LCD_CRSR_IMG108_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG108: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG109  ----------------------------------------
-#define LCD_CRSR_IMG109_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG109: CRSR_IMG Position  */
-#define LCD_CRSR_IMG109_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG109: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG110  ----------------------------------------
-#define LCD_CRSR_IMG110_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG110: CRSR_IMG Position  */
-#define LCD_CRSR_IMG110_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG110: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG111  ----------------------------------------
-#define LCD_CRSR_IMG111_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG111: CRSR_IMG Position  */
-#define LCD_CRSR_IMG111_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG111: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG112  ----------------------------------------
-#define LCD_CRSR_IMG112_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG112: CRSR_IMG Position  */
-#define LCD_CRSR_IMG112_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG112: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG113  ----------------------------------------
-#define LCD_CRSR_IMG113_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG113: CRSR_IMG Position  */
-#define LCD_CRSR_IMG113_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG113: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG114  ----------------------------------------
-#define LCD_CRSR_IMG114_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG114: CRSR_IMG Position  */
-#define LCD_CRSR_IMG114_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG114: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG115  ----------------------------------------
-#define LCD_CRSR_IMG115_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG115: CRSR_IMG Position  */
-#define LCD_CRSR_IMG115_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG115: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG116  ----------------------------------------
-#define LCD_CRSR_IMG116_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG116: CRSR_IMG Position  */
-#define LCD_CRSR_IMG116_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG116: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG117  ----------------------------------------
-#define LCD_CRSR_IMG117_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG117: CRSR_IMG Position  */
-#define LCD_CRSR_IMG117_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG117: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG118  ----------------------------------------
-#define LCD_CRSR_IMG118_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG118: CRSR_IMG Position  */
-#define LCD_CRSR_IMG118_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG118: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG119  ----------------------------------------
-#define LCD_CRSR_IMG119_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG119: CRSR_IMG Position  */
-#define LCD_CRSR_IMG119_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG119: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG120  ----------------------------------------
-#define LCD_CRSR_IMG120_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG120: CRSR_IMG Position  */
-#define LCD_CRSR_IMG120_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG120: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG121  ----------------------------------------
-#define LCD_CRSR_IMG121_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG121: CRSR_IMG Position  */
-#define LCD_CRSR_IMG121_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG121: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG122  ----------------------------------------
-#define LCD_CRSR_IMG122_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG122: CRSR_IMG Position  */
-#define LCD_CRSR_IMG122_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG122: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG123  ----------------------------------------
-#define LCD_CRSR_IMG123_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG123: CRSR_IMG Position  */
-#define LCD_CRSR_IMG123_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG123: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG124  ----------------------------------------
-#define LCD_CRSR_IMG124_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG124: CRSR_IMG Position  */
-#define LCD_CRSR_IMG124_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG124: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG125  ----------------------------------------
-#define LCD_CRSR_IMG125_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG125: CRSR_IMG Position  */
-#define LCD_CRSR_IMG125_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG125: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG126  ----------------------------------------
-#define LCD_CRSR_IMG126_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG126: CRSR_IMG Position  */
-#define LCD_CRSR_IMG126_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG126: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG127  ----------------------------------------
-#define LCD_CRSR_IMG127_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG127: CRSR_IMG Position  */
-#define LCD_CRSR_IMG127_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG127: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG128  ----------------------------------------
-#define LCD_CRSR_IMG128_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG128: CRSR_IMG Position  */
-#define LCD_CRSR_IMG128_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG128: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG129  ----------------------------------------
-#define LCD_CRSR_IMG129_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG129: CRSR_IMG Position  */
-#define LCD_CRSR_IMG129_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG129: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG130  ----------------------------------------
-#define LCD_CRSR_IMG130_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG130: CRSR_IMG Position  */
-#define LCD_CRSR_IMG130_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG130: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG131  ----------------------------------------
-#define LCD_CRSR_IMG131_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG131: CRSR_IMG Position  */
-#define LCD_CRSR_IMG131_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG131: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG132  ----------------------------------------
-#define LCD_CRSR_IMG132_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG132: CRSR_IMG Position  */
-#define LCD_CRSR_IMG132_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG132: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG133  ----------------------------------------
-#define LCD_CRSR_IMG133_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG133: CRSR_IMG Position  */
-#define LCD_CRSR_IMG133_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG133: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG134  ----------------------------------------
-#define LCD_CRSR_IMG134_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG134: CRSR_IMG Position  */
-#define LCD_CRSR_IMG134_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG134: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG135  ----------------------------------------
-#define LCD_CRSR_IMG135_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG135: CRSR_IMG Position  */
-#define LCD_CRSR_IMG135_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG135: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG136  ----------------------------------------
-#define LCD_CRSR_IMG136_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG136: CRSR_IMG Position  */
-#define LCD_CRSR_IMG136_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG136: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG137  ----------------------------------------
-#define LCD_CRSR_IMG137_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG137: CRSR_IMG Position  */
-#define LCD_CRSR_IMG137_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG137: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG138  ----------------------------------------
-#define LCD_CRSR_IMG138_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG138: CRSR_IMG Position  */
-#define LCD_CRSR_IMG138_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG138: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG139  ----------------------------------------
-#define LCD_CRSR_IMG139_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG139: CRSR_IMG Position  */
-#define LCD_CRSR_IMG139_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG139: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG140  ----------------------------------------
-#define LCD_CRSR_IMG140_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG140: CRSR_IMG Position  */
-#define LCD_CRSR_IMG140_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG140: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG141  ----------------------------------------
-#define LCD_CRSR_IMG141_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG141: CRSR_IMG Position  */
-#define LCD_CRSR_IMG141_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG141: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG142  ----------------------------------------
-#define LCD_CRSR_IMG142_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG142: CRSR_IMG Position  */
-#define LCD_CRSR_IMG142_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG142: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG143  ----------------------------------------
-#define LCD_CRSR_IMG143_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG143: CRSR_IMG Position  */
-#define LCD_CRSR_IMG143_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG143: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG144  ----------------------------------------
-#define LCD_CRSR_IMG144_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG144: CRSR_IMG Position  */
-#define LCD_CRSR_IMG144_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG144: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG145  ----------------------------------------
-#define LCD_CRSR_IMG145_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG145: CRSR_IMG Position  */
-#define LCD_CRSR_IMG145_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG145: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG146  ----------------------------------------
-#define LCD_CRSR_IMG146_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG146: CRSR_IMG Position  */
-#define LCD_CRSR_IMG146_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG146: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG147  ----------------------------------------
-#define LCD_CRSR_IMG147_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG147: CRSR_IMG Position  */
-#define LCD_CRSR_IMG147_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG147: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG148  ----------------------------------------
-#define LCD_CRSR_IMG148_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG148: CRSR_IMG Position  */
-#define LCD_CRSR_IMG148_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG148: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG149  ----------------------------------------
-#define LCD_CRSR_IMG149_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG149: CRSR_IMG Position  */
-#define LCD_CRSR_IMG149_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG149: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG150  ----------------------------------------
-#define LCD_CRSR_IMG150_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG150: CRSR_IMG Position  */
-#define LCD_CRSR_IMG150_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG150: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG151  ----------------------------------------
-#define LCD_CRSR_IMG151_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG151: CRSR_IMG Position  */
-#define LCD_CRSR_IMG151_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG151: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG152  ----------------------------------------
-#define LCD_CRSR_IMG152_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG152: CRSR_IMG Position  */
-#define LCD_CRSR_IMG152_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG152: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG153  ----------------------------------------
-#define LCD_CRSR_IMG153_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG153: CRSR_IMG Position  */
-#define LCD_CRSR_IMG153_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG153: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG154  ----------------------------------------
-#define LCD_CRSR_IMG154_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG154: CRSR_IMG Position  */
-#define LCD_CRSR_IMG154_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG154: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG155  ----------------------------------------
-#define LCD_CRSR_IMG155_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG155: CRSR_IMG Position  */
-#define LCD_CRSR_IMG155_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG155: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG156  ----------------------------------------
-#define LCD_CRSR_IMG156_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG156: CRSR_IMG Position  */
-#define LCD_CRSR_IMG156_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG156: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG157  ----------------------------------------
-#define LCD_CRSR_IMG157_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG157: CRSR_IMG Position  */
-#define LCD_CRSR_IMG157_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG157: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG158  ----------------------------------------
-#define LCD_CRSR_IMG158_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG158: CRSR_IMG Position  */
-#define LCD_CRSR_IMG158_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG158: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG159  ----------------------------------------
-#define LCD_CRSR_IMG159_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG159: CRSR_IMG Position  */
-#define LCD_CRSR_IMG159_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG159: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG160  ----------------------------------------
-#define LCD_CRSR_IMG160_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG160: CRSR_IMG Position  */
-#define LCD_CRSR_IMG160_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG160: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG161  ----------------------------------------
-#define LCD_CRSR_IMG161_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG161: CRSR_IMG Position  */
-#define LCD_CRSR_IMG161_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG161: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG162  ----------------------------------------
-#define LCD_CRSR_IMG162_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG162: CRSR_IMG Position  */
-#define LCD_CRSR_IMG162_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG162: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG163  ----------------------------------------
-#define LCD_CRSR_IMG163_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG163: CRSR_IMG Position  */
-#define LCD_CRSR_IMG163_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG163: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG164  ----------------------------------------
-#define LCD_CRSR_IMG164_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG164: CRSR_IMG Position  */
-#define LCD_CRSR_IMG164_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG164: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG165  ----------------------------------------
-#define LCD_CRSR_IMG165_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG165: CRSR_IMG Position  */
-#define LCD_CRSR_IMG165_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG165: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG166  ----------------------------------------
-#define LCD_CRSR_IMG166_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG166: CRSR_IMG Position  */
-#define LCD_CRSR_IMG166_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG166: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG167  ----------------------------------------
-#define LCD_CRSR_IMG167_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG167: CRSR_IMG Position  */
-#define LCD_CRSR_IMG167_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG167: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG168  ----------------------------------------
-#define LCD_CRSR_IMG168_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG168: CRSR_IMG Position  */
-#define LCD_CRSR_IMG168_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG168: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG169  ----------------------------------------
-#define LCD_CRSR_IMG169_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG169: CRSR_IMG Position  */
-#define LCD_CRSR_IMG169_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG169: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG170  ----------------------------------------
-#define LCD_CRSR_IMG170_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG170: CRSR_IMG Position  */
-#define LCD_CRSR_IMG170_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG170: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG171  ----------------------------------------
-#define LCD_CRSR_IMG171_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG171: CRSR_IMG Position  */
-#define LCD_CRSR_IMG171_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG171: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG172  ----------------------------------------
-#define LCD_CRSR_IMG172_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG172: CRSR_IMG Position  */
-#define LCD_CRSR_IMG172_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG172: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG173  ----------------------------------------
-#define LCD_CRSR_IMG173_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG173: CRSR_IMG Position  */
-#define LCD_CRSR_IMG173_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG173: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG174  ----------------------------------------
-#define LCD_CRSR_IMG174_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG174: CRSR_IMG Position  */
-#define LCD_CRSR_IMG174_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG174: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG175  ----------------------------------------
-#define LCD_CRSR_IMG175_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG175: CRSR_IMG Position  */
-#define LCD_CRSR_IMG175_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG175: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG176  ----------------------------------------
-#define LCD_CRSR_IMG176_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG176: CRSR_IMG Position  */
-#define LCD_CRSR_IMG176_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG176: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG177  ----------------------------------------
-#define LCD_CRSR_IMG177_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG177: CRSR_IMG Position  */
-#define LCD_CRSR_IMG177_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG177: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG178  ----------------------------------------
-#define LCD_CRSR_IMG178_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG178: CRSR_IMG Position  */
-#define LCD_CRSR_IMG178_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG178: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG179  ----------------------------------------
-#define LCD_CRSR_IMG179_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG179: CRSR_IMG Position  */
-#define LCD_CRSR_IMG179_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG179: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG180  ----------------------------------------
-#define LCD_CRSR_IMG180_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG180: CRSR_IMG Position  */
-#define LCD_CRSR_IMG180_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG180: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG181  ----------------------------------------
-#define LCD_CRSR_IMG181_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG181: CRSR_IMG Position  */
-#define LCD_CRSR_IMG181_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG181: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG182  ----------------------------------------
-#define LCD_CRSR_IMG182_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG182: CRSR_IMG Position  */
-#define LCD_CRSR_IMG182_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG182: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG183  ----------------------------------------
-#define LCD_CRSR_IMG183_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG183: CRSR_IMG Position  */
-#define LCD_CRSR_IMG183_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG183: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG184  ----------------------------------------
-#define LCD_CRSR_IMG184_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG184: CRSR_IMG Position  */
-#define LCD_CRSR_IMG184_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG184: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG185  ----------------------------------------
-#define LCD_CRSR_IMG185_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG185: CRSR_IMG Position  */
-#define LCD_CRSR_IMG185_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG185: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG186  ----------------------------------------
-#define LCD_CRSR_IMG186_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG186: CRSR_IMG Position  */
-#define LCD_CRSR_IMG186_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG186: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG187  ----------------------------------------
-#define LCD_CRSR_IMG187_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG187: CRSR_IMG Position  */
-#define LCD_CRSR_IMG187_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG187: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG188  ----------------------------------------
-#define LCD_CRSR_IMG188_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG188: CRSR_IMG Position  */
-#define LCD_CRSR_IMG188_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG188: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG189  ----------------------------------------
-#define LCD_CRSR_IMG189_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG189: CRSR_IMG Position  */
-#define LCD_CRSR_IMG189_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG189: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG190  ----------------------------------------
-#define LCD_CRSR_IMG190_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG190: CRSR_IMG Position  */
-#define LCD_CRSR_IMG190_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG190: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG191  ----------------------------------------
-#define LCD_CRSR_IMG191_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG191: CRSR_IMG Position  */
-#define LCD_CRSR_IMG191_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG191: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG192  ----------------------------------------
-#define LCD_CRSR_IMG192_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG192: CRSR_IMG Position  */
-#define LCD_CRSR_IMG192_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG192: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG193  ----------------------------------------
-#define LCD_CRSR_IMG193_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG193: CRSR_IMG Position  */
-#define LCD_CRSR_IMG193_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG193: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG194  ----------------------------------------
-#define LCD_CRSR_IMG194_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG194: CRSR_IMG Position  */
-#define LCD_CRSR_IMG194_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG194: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG195  ----------------------------------------
-#define LCD_CRSR_IMG195_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG195: CRSR_IMG Position  */
-#define LCD_CRSR_IMG195_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG195: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG196  ----------------------------------------
-#define LCD_CRSR_IMG196_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG196: CRSR_IMG Position  */
-#define LCD_CRSR_IMG196_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG196: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG197  ----------------------------------------
-#define LCD_CRSR_IMG197_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG197: CRSR_IMG Position  */
-#define LCD_CRSR_IMG197_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG197: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG198  ----------------------------------------
-#define LCD_CRSR_IMG198_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG198: CRSR_IMG Position  */
-#define LCD_CRSR_IMG198_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG198: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG199  ----------------------------------------
-#define LCD_CRSR_IMG199_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG199: CRSR_IMG Position  */
-#define LCD_CRSR_IMG199_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG199: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG200  ----------------------------------------
-#define LCD_CRSR_IMG200_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG200: CRSR_IMG Position  */
-#define LCD_CRSR_IMG200_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG200: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG201  ----------------------------------------
-#define LCD_CRSR_IMG201_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG201: CRSR_IMG Position  */
-#define LCD_CRSR_IMG201_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG201: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG202  ----------------------------------------
-#define LCD_CRSR_IMG202_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG202: CRSR_IMG Position  */
-#define LCD_CRSR_IMG202_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG202: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG203  ----------------------------------------
-#define LCD_CRSR_IMG203_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG203: CRSR_IMG Position  */
-#define LCD_CRSR_IMG203_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG203: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG204  ----------------------------------------
-#define LCD_CRSR_IMG204_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG204: CRSR_IMG Position  */
-#define LCD_CRSR_IMG204_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG204: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG205  ----------------------------------------
-#define LCD_CRSR_IMG205_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG205: CRSR_IMG Position  */
-#define LCD_CRSR_IMG205_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG205: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG206  ----------------------------------------
-#define LCD_CRSR_IMG206_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG206: CRSR_IMG Position  */
-#define LCD_CRSR_IMG206_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG206: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG207  ----------------------------------------
-#define LCD_CRSR_IMG207_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG207: CRSR_IMG Position  */
-#define LCD_CRSR_IMG207_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG207: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG208  ----------------------------------------
-#define LCD_CRSR_IMG208_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG208: CRSR_IMG Position  */
-#define LCD_CRSR_IMG208_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG208: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG209  ----------------------------------------
-#define LCD_CRSR_IMG209_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG209: CRSR_IMG Position  */
-#define LCD_CRSR_IMG209_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG209: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG210  ----------------------------------------
-#define LCD_CRSR_IMG210_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG210: CRSR_IMG Position  */
-#define LCD_CRSR_IMG210_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG210: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG211  ----------------------------------------
-#define LCD_CRSR_IMG211_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG211: CRSR_IMG Position  */
-#define LCD_CRSR_IMG211_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG211: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG212  ----------------------------------------
-#define LCD_CRSR_IMG212_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG212: CRSR_IMG Position  */
-#define LCD_CRSR_IMG212_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG212: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG213  ----------------------------------------
-#define LCD_CRSR_IMG213_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG213: CRSR_IMG Position  */
-#define LCD_CRSR_IMG213_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG213: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG214  ----------------------------------------
-#define LCD_CRSR_IMG214_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG214: CRSR_IMG Position  */
-#define LCD_CRSR_IMG214_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG214: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG215  ----------------------------------------
-#define LCD_CRSR_IMG215_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG215: CRSR_IMG Position  */
-#define LCD_CRSR_IMG215_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG215: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG216  ----------------------------------------
-#define LCD_CRSR_IMG216_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG216: CRSR_IMG Position  */
-#define LCD_CRSR_IMG216_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG216: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG217  ----------------------------------------
-#define LCD_CRSR_IMG217_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG217: CRSR_IMG Position  */
-#define LCD_CRSR_IMG217_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG217: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG218  ----------------------------------------
-#define LCD_CRSR_IMG218_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG218: CRSR_IMG Position  */
-#define LCD_CRSR_IMG218_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG218: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG219  ----------------------------------------
-#define LCD_CRSR_IMG219_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG219: CRSR_IMG Position  */
-#define LCD_CRSR_IMG219_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG219: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG220  ----------------------------------------
-#define LCD_CRSR_IMG220_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG220: CRSR_IMG Position  */
-#define LCD_CRSR_IMG220_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG220: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG221  ----------------------------------------
-#define LCD_CRSR_IMG221_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG221: CRSR_IMG Position  */
-#define LCD_CRSR_IMG221_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG221: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG222  ----------------------------------------
-#define LCD_CRSR_IMG222_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG222: CRSR_IMG Position  */
-#define LCD_CRSR_IMG222_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG222: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG223  ----------------------------------------
-#define LCD_CRSR_IMG223_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG223: CRSR_IMG Position  */
-#define LCD_CRSR_IMG223_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG223: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG224  ----------------------------------------
-#define LCD_CRSR_IMG224_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG224: CRSR_IMG Position  */
-#define LCD_CRSR_IMG224_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG224: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG225  ----------------------------------------
-#define LCD_CRSR_IMG225_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG225: CRSR_IMG Position  */
-#define LCD_CRSR_IMG225_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG225: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG226  ----------------------------------------
-#define LCD_CRSR_IMG226_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG226: CRSR_IMG Position  */
-#define LCD_CRSR_IMG226_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG226: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG227  ----------------------------------------
-#define LCD_CRSR_IMG227_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG227: CRSR_IMG Position  */
-#define LCD_CRSR_IMG227_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG227: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG228  ----------------------------------------
-#define LCD_CRSR_IMG228_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG228: CRSR_IMG Position  */
-#define LCD_CRSR_IMG228_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG228: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG229  ----------------------------------------
-#define LCD_CRSR_IMG229_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG229: CRSR_IMG Position  */
-#define LCD_CRSR_IMG229_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG229: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG230  ----------------------------------------
-#define LCD_CRSR_IMG230_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG230: CRSR_IMG Position  */
-#define LCD_CRSR_IMG230_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG230: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG231  ----------------------------------------
-#define LCD_CRSR_IMG231_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG231: CRSR_IMG Position  */
-#define LCD_CRSR_IMG231_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG231: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG232  ----------------------------------------
-#define LCD_CRSR_IMG232_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG232: CRSR_IMG Position  */
-#define LCD_CRSR_IMG232_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG232: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG233  ----------------------------------------
-#define LCD_CRSR_IMG233_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG233: CRSR_IMG Position  */
-#define LCD_CRSR_IMG233_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG233: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG234  ----------------------------------------
-#define LCD_CRSR_IMG234_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG234: CRSR_IMG Position  */
-#define LCD_CRSR_IMG234_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG234: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG235  ----------------------------------------
-#define LCD_CRSR_IMG235_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG235: CRSR_IMG Position  */
-#define LCD_CRSR_IMG235_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG235: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG236  ----------------------------------------
-#define LCD_CRSR_IMG236_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG236: CRSR_IMG Position  */
-#define LCD_CRSR_IMG236_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG236: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG237  ----------------------------------------
-#define LCD_CRSR_IMG237_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG237: CRSR_IMG Position  */
-#define LCD_CRSR_IMG237_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG237: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG238  ----------------------------------------
-#define LCD_CRSR_IMG238_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG238: CRSR_IMG Position  */
-#define LCD_CRSR_IMG238_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG238: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG239  ----------------------------------------
-#define LCD_CRSR_IMG239_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG239: CRSR_IMG Position  */
-#define LCD_CRSR_IMG239_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG239: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG240  ----------------------------------------
-#define LCD_CRSR_IMG240_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG240: CRSR_IMG Position  */
-#define LCD_CRSR_IMG240_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG240: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG241  ----------------------------------------
-#define LCD_CRSR_IMG241_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG241: CRSR_IMG Position  */
-#define LCD_CRSR_IMG241_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG241: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG242  ----------------------------------------
-#define LCD_CRSR_IMG242_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG242: CRSR_IMG Position  */
-#define LCD_CRSR_IMG242_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG242: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG243  ----------------------------------------
-#define LCD_CRSR_IMG243_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG243: CRSR_IMG Position  */
-#define LCD_CRSR_IMG243_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG243: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG244  ----------------------------------------
-#define LCD_CRSR_IMG244_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG244: CRSR_IMG Position  */
-#define LCD_CRSR_IMG244_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG244: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG245  ----------------------------------------
-#define LCD_CRSR_IMG245_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG245: CRSR_IMG Position  */
-#define LCD_CRSR_IMG245_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG245: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG246  ----------------------------------------
-#define LCD_CRSR_IMG246_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG246: CRSR_IMG Position  */
-#define LCD_CRSR_IMG246_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG246: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG247  ----------------------------------------
-#define LCD_CRSR_IMG247_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG247: CRSR_IMG Position  */
-#define LCD_CRSR_IMG247_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG247: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG248  ----------------------------------------
-#define LCD_CRSR_IMG248_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG248: CRSR_IMG Position  */
-#define LCD_CRSR_IMG248_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG248: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG249  ----------------------------------------
-#define LCD_CRSR_IMG249_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG249: CRSR_IMG Position  */
-#define LCD_CRSR_IMG249_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG249: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG250  ----------------------------------------
-#define LCD_CRSR_IMG250_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG250: CRSR_IMG Position  */
-#define LCD_CRSR_IMG250_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG250: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG251  ----------------------------------------
-#define LCD_CRSR_IMG251_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG251: CRSR_IMG Position  */
-#define LCD_CRSR_IMG251_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG251: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG252  ----------------------------------------
-#define LCD_CRSR_IMG252_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG252: CRSR_IMG Position  */
-#define LCD_CRSR_IMG252_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG252: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG253  ----------------------------------------
-#define LCD_CRSR_IMG253_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG253: CRSR_IMG Position  */
-#define LCD_CRSR_IMG253_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG253: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG254  ----------------------------------------
-#define LCD_CRSR_IMG254_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG254: CRSR_IMG Position  */
-#define LCD_CRSR_IMG254_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG254: CRSR_IMG Mask      */
-
-// -------------------------------------  LCD_CRSR_IMG255  ----------------------------------------
-#define LCD_CRSR_IMG255_CRSR_IMG_Pos                          0                                                         /*!< LCD CRSR_IMG255: CRSR_IMG Position  */
-#define LCD_CRSR_IMG255_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos)            /*!< LCD CRSR_IMG255: CRSR_IMG Mask      */
-
-// --------------------------------------  LCD_CRSR_CTRL  -----------------------------------------
-#define LCD_CRSR_CTRL_CrsrOn_Pos                              0                                                         /*!< LCD CRSR_CTRL: CrsrOn Position      */
-#define LCD_CRSR_CTRL_CrsrOn_Msk                              (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos)                      /*!< LCD CRSR_CTRL: CrsrOn Mask          */
-#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos                          4                                                         /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position  */
-#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk                          (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos)                  /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask      */
-
-// --------------------------------------  LCD_CRSR_CFG  ------------------------------------------
-#define LCD_CRSR_CFG_CrsrSize_Pos                             0                                                         /*!< LCD CRSR_CFG: CrsrSize Position     */
-#define LCD_CRSR_CFG_CrsrSize_Msk                             (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos)                     /*!< LCD CRSR_CFG: CrsrSize Mask         */
-#define LCD_CRSR_CFG_FRAMESYNC_Pos                            1                                                         /*!< LCD CRSR_CFG: FRAMESYNC Position    */
-#define LCD_CRSR_CFG_FRAMESYNC_Msk                            (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos)                    /*!< LCD CRSR_CFG: FRAMESYNC Mask        */
-
-// --------------------------------------  LCD_CRSR_PAL0  -----------------------------------------
-#define LCD_CRSR_PAL0_RED_Pos                                 0                                                         /*!< LCD CRSR_PAL0: RED Position         */
-#define LCD_CRSR_PAL0_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos)                   /*!< LCD CRSR_PAL0: RED Mask             */
-#define LCD_CRSR_PAL0_GREEN_Pos                               8                                                         /*!< LCD CRSR_PAL0: GREEN Position       */
-#define LCD_CRSR_PAL0_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos)                 /*!< LCD CRSR_PAL0: GREEN Mask           */
-#define LCD_CRSR_PAL0_BLUE_Pos                                16                                                        /*!< LCD CRSR_PAL0: BLUE Position        */
-#define LCD_CRSR_PAL0_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos)                  /*!< LCD CRSR_PAL0: BLUE Mask            */
-
-// --------------------------------------  LCD_CRSR_PAL1  -----------------------------------------
-#define LCD_CRSR_PAL1_RED_Pos                                 0                                                         /*!< LCD CRSR_PAL1: RED Position         */
-#define LCD_CRSR_PAL1_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos)                   /*!< LCD CRSR_PAL1: RED Mask             */
-#define LCD_CRSR_PAL1_GREEN_Pos                               8                                                         /*!< LCD CRSR_PAL1: GREEN Position       */
-#define LCD_CRSR_PAL1_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos)                 /*!< LCD CRSR_PAL1: GREEN Mask           */
-#define LCD_CRSR_PAL1_BLUE_Pos                                16                                                        /*!< LCD CRSR_PAL1: BLUE Position        */
-#define LCD_CRSR_PAL1_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos)                  /*!< LCD CRSR_PAL1: BLUE Mask            */
-
-// ---------------------------------------  LCD_CRSR_XY  ------------------------------------------
-#define LCD_CRSR_XY_CRSRX_Pos                                 0                                                         /*!< LCD CRSR_XY: CRSRX Position         */
-#define LCD_CRSR_XY_CRSRX_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos)                   /*!< LCD CRSR_XY: CRSRX Mask             */
-#define LCD_CRSR_XY_CRSRY_Pos                                 16                                                        /*!< LCD CRSR_XY: CRSRY Position         */
-#define LCD_CRSR_XY_CRSRY_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos)                   /*!< LCD CRSR_XY: CRSRY Mask             */
-
-// --------------------------------------  LCD_CRSR_CLIP  -----------------------------------------
-#define LCD_CRSR_CLIP_CRSRCLIPX_Pos                           0                                                         /*!< LCD CRSR_CLIP: CRSRCLIPX Position   */
-#define LCD_CRSR_CLIP_CRSRCLIPX_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos)                   /*!< LCD CRSR_CLIP: CRSRCLIPX Mask       */
-#define LCD_CRSR_CLIP_CRSRCLIPY_Pos                           8                                                         /*!< LCD CRSR_CLIP: CRSRCLIPY Position   */
-#define LCD_CRSR_CLIP_CRSRCLIPY_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos)                   /*!< LCD CRSR_CLIP: CRSRCLIPY Mask       */
-
-// -------------------------------------  LCD_CRSR_INTMSK  ----------------------------------------
-#define LCD_CRSR_INTMSK_CRSRIM_Pos                            0                                                         /*!< LCD CRSR_INTMSK: CRSRIM Position    */
-#define LCD_CRSR_INTMSK_CRSRIM_Msk                            (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos)                    /*!< LCD CRSR_INTMSK: CRSRIM Mask        */
-
-// -------------------------------------  LCD_CRSR_INTCLR  ----------------------------------------
-#define LCD_CRSR_INTCLR_CRSRIC_Pos                            0                                                         /*!< LCD CRSR_INTCLR: CRSRIC Position    */
-#define LCD_CRSR_INTCLR_CRSRIC_Msk                            (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos)                    /*!< LCD CRSR_INTCLR: CRSRIC Mask        */
-
-// -------------------------------------  LCD_CRSR_INTRAW  ----------------------------------------
-#define LCD_CRSR_INTRAW_CRSRRIS_Pos                           0                                                         /*!< LCD CRSR_INTRAW: CRSRRIS Position   */
-#define LCD_CRSR_INTRAW_CRSRRIS_Msk                           (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos)                   /*!< LCD CRSR_INTRAW: CRSRRIS Mask       */
-
-// ------------------------------------  LCD_CRSR_INTSTAT  ----------------------------------------
-#define LCD_CRSR_INTSTAT_CRSRMIS_Pos                          0                                                         /*!< LCD CRSR_INTSTAT: CRSRMIS Position  */
-#define LCD_CRSR_INTSTAT_CRSRMIS_Msk                          (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos)                  /*!< LCD CRSR_INTSTAT: CRSRMIS Mask      */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                               ETHERNET Position & Mask                               -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------  ETHERNET_MAC_CONFIG  --------------------------------------
-#define ETHERNET_MAC_CONFIG_RE_Pos                            2                                                         /*!< ETHERNET MAC_CONFIG: RE Position    */
-#define ETHERNET_MAC_CONFIG_RE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos)                    /*!< ETHERNET MAC_CONFIG: RE Mask        */
-#define ETHERNET_MAC_CONFIG_TE_Pos                            3                                                         /*!< ETHERNET MAC_CONFIG: TE Position    */
-#define ETHERNET_MAC_CONFIG_TE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos)                    /*!< ETHERNET MAC_CONFIG: TE Mask        */
-#define ETHERNET_MAC_CONFIG_DF_Pos                            4                                                         /*!< ETHERNET MAC_CONFIG: DF Position    */
-#define ETHERNET_MAC_CONFIG_DF_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos)                    /*!< ETHERNET MAC_CONFIG: DF Mask        */
-#define ETHERNET_MAC_CONFIG_BL_Pos                            5                                                         /*!< ETHERNET MAC_CONFIG: BL Position    */
-#define ETHERNET_MAC_CONFIG_BL_Msk                            (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos)                    /*!< ETHERNET MAC_CONFIG: BL Mask        */
-#define ETHERNET_MAC_CONFIG_ACS_Pos                           7                                                         /*!< ETHERNET MAC_CONFIG: ACS Position   */
-#define ETHERNET_MAC_CONFIG_ACS_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos)                   /*!< ETHERNET MAC_CONFIG: ACS Mask       */
-#define ETHERNET_MAC_CONFIG_DR_Pos                            9                                                         /*!< ETHERNET MAC_CONFIG: DR Position    */
-#define ETHERNET_MAC_CONFIG_DR_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos)                    /*!< ETHERNET MAC_CONFIG: DR Mask        */
-#define ETHERNET_MAC_CONFIG_IPC_Pos                           10                                                        /*!< ETHERNET MAC_CONFIG: IPC Position   */
-#define ETHERNET_MAC_CONFIG_IPC_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos)                   /*!< ETHERNET MAC_CONFIG: IPC Mask       */
-#define ETHERNET_MAC_CONFIG_DM_Pos                            11                                                        /*!< ETHERNET MAC_CONFIG: DM Position    */
-#define ETHERNET_MAC_CONFIG_DM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos)                    /*!< ETHERNET MAC_CONFIG: DM Mask        */
-#define ETHERNET_MAC_CONFIG_LM_Pos                            12                                                        /*!< ETHERNET MAC_CONFIG: LM Position    */
-#define ETHERNET_MAC_CONFIG_LM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos)                    /*!< ETHERNET MAC_CONFIG: LM Mask        */
-#define ETHERNET_MAC_CONFIG_DO_Pos                            13                                                        /*!< ETHERNET MAC_CONFIG: DO Position    */
-#define ETHERNET_MAC_CONFIG_DO_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos)                    /*!< ETHERNET MAC_CONFIG: DO Mask        */
-#define ETHERNET_MAC_CONFIG_FES_Pos                           14                                                        /*!< ETHERNET MAC_CONFIG: FES Position   */
-#define ETHERNET_MAC_CONFIG_FES_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos)                   /*!< ETHERNET MAC_CONFIG: FES Mask       */
-#define ETHERNET_MAC_CONFIG_PS_Pos                            15                                                        /*!< ETHERNET MAC_CONFIG: PS Position    */
-#define ETHERNET_MAC_CONFIG_PS_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos)                    /*!< ETHERNET MAC_CONFIG: PS Mask        */
-#define ETHERNET_MAC_CONFIG_DCRS_Pos                          16                                                        /*!< ETHERNET MAC_CONFIG: DCRS Position  */
-#define ETHERNET_MAC_CONFIG_DCRS_Msk                          (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos)                  /*!< ETHERNET MAC_CONFIG: DCRS Mask      */
-#define ETHERNET_MAC_CONFIG_IFG_Pos                           17                                                        /*!< ETHERNET MAC_CONFIG: IFG Position   */
-#define ETHERNET_MAC_CONFIG_IFG_Msk                           (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos)                   /*!< ETHERNET MAC_CONFIG: IFG Mask       */
-#define ETHERNET_MAC_CONFIG_JE_Pos                            20                                                        /*!< ETHERNET MAC_CONFIG: JE Position    */
-#define ETHERNET_MAC_CONFIG_JE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos)                    /*!< ETHERNET MAC_CONFIG: JE Mask        */
-#define ETHERNET_MAC_CONFIG_JD_Pos                            22                                                        /*!< ETHERNET MAC_CONFIG: JD Position    */
-#define ETHERNET_MAC_CONFIG_JD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos)                    /*!< ETHERNET MAC_CONFIG: JD Mask        */
-#define ETHERNET_MAC_CONFIG_WD_Pos                            23                                                        /*!< ETHERNET MAC_CONFIG: WD Position    */
-#define ETHERNET_MAC_CONFIG_WD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos)                    /*!< ETHERNET MAC_CONFIG: WD Mask        */
-
-// --------------------------------  ETHERNET_MAC_FRAME_FILTER  -----------------------------------
-#define ETHERNET_MAC_FRAME_FILTER_PR_Pos                      0                                                         /*!< ETHERNET MAC_FRAME_FILTER: PR Position */
-#define ETHERNET_MAC_FRAME_FILTER_PR_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: PR Mask  */
-#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos                    3                                                         /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */
-#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos)            /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */
-#define ETHERNET_MAC_FRAME_FILTER_PM_Pos                      4                                                         /*!< ETHERNET MAC_FRAME_FILTER: PM Position */
-#define ETHERNET_MAC_FRAME_FILTER_PM_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: PM Mask  */
-#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos                     5                                                         /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */
-#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */
-#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos                     6                                                         /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */
-#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk                     (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */
-#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos                    8                                                         /*!< ETHERNET MAC_FRAME_FILTER: SAIF Position */
-#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos)            /*!< ETHERNET MAC_FRAME_FILTER: SAIF Mask */
-#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos                     9                                                         /*!< ETHERNET MAC_FRAME_FILTER: SAF Position */
-#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos)             /*!< ETHERNET MAC_FRAME_FILTER: SAF Mask */
-#define ETHERNET_MAC_FRAME_FILTER_RA_Pos                      31                                                        /*!< ETHERNET MAC_FRAME_FILTER: RA Position */
-#define ETHERNET_MAC_FRAME_FILTER_RA_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos)              /*!< ETHERNET MAC_FRAME_FILTER: RA Mask  */
-
-// -------------------------------  ETHERNET_MAC_HASHTABLE_HIGH  ----------------------------------
-#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos                   0                                                         /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */
-#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk                   (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos)     /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */
-
-// -------------------------------  ETHERNET_MAC_HASHTABLE_LOW  -----------------------------------
-#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos                    0                                                         /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */
-#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk                    (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos)      /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */
-
-// ----------------------------------  ETHERNET_MAC_MII_ADDR  -------------------------------------
-#define ETHERNET_MAC_MII_ADDR_GB_Pos                          0                                                         /*!< ETHERNET MAC_MII_ADDR: GB Position  */
-#define ETHERNET_MAC_MII_ADDR_GB_Msk                          (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos)                  /*!< ETHERNET MAC_MII_ADDR: GB Mask      */
-#define ETHERNET_MAC_MII_ADDR_W_Pos                           1                                                         /*!< ETHERNET MAC_MII_ADDR: W Position   */
-#define ETHERNET_MAC_MII_ADDR_W_Msk                           (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos)                   /*!< ETHERNET MAC_MII_ADDR: W Mask       */
-#define ETHERNET_MAC_MII_ADDR_CR_Pos                          2                                                         /*!< ETHERNET MAC_MII_ADDR: CR Position  */
-#define ETHERNET_MAC_MII_ADDR_CR_Msk                          (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos)                  /*!< ETHERNET MAC_MII_ADDR: CR Mask      */
-#define ETHERNET_MAC_MII_ADDR_GR_Pos                          6                                                         /*!< ETHERNET MAC_MII_ADDR: GR Position  */
-#define ETHERNET_MAC_MII_ADDR_GR_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos)                  /*!< ETHERNET MAC_MII_ADDR: GR Mask      */
-#define ETHERNET_MAC_MII_ADDR_PA_Pos                          11                                                        /*!< ETHERNET MAC_MII_ADDR: PA Position  */
-#define ETHERNET_MAC_MII_ADDR_PA_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos)                  /*!< ETHERNET MAC_MII_ADDR: PA Mask      */
-
-// ----------------------------------  ETHERNET_MAC_MII_DATA  -------------------------------------
-#define ETHERNET_MAC_MII_DATA_GD_Pos                          0                                                         /*!< ETHERNET MAC_MII_DATA: GD Position  */
-#define ETHERNET_MAC_MII_DATA_GD_Msk                          (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos)            /*!< ETHERNET MAC_MII_DATA: GD Mask      */
-
-// ---------------------------------  ETHERNET_MAC_FLOW_CTRL  -------------------------------------
-#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos                        0                                                         /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */
-#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask    */
-#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos                        1                                                         /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */
-#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask    */
-#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos                        2                                                         /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */
-#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask    */
-#define ETHERNET_MAC_FLOW_CTRL_UP_Pos                         3                                                         /*!< ETHERNET MAC_FLOW_CTRL: UP Position */
-#define ETHERNET_MAC_FLOW_CTRL_UP_Msk                         (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos)                 /*!< ETHERNET MAC_FLOW_CTRL: UP Mask     */
-#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos                        4                                                         /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */
-#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk                        (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos)                /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask    */
-#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos                       7                                                         /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */
-#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk                       (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos)               /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask   */
-#define ETHERNET_MAC_FLOW_CTRL_PT_Pos                         16                                                        /*!< ETHERNET MAC_FLOW_CTRL: PT Position */
-#define ETHERNET_MAC_FLOW_CTRL_PT_Msk                         (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos)           /*!< ETHERNET MAC_FLOW_CTRL: PT Mask     */
-
-// ----------------------------------  ETHERNET_MAC_VLAN_TAG  -------------------------------------
-#define ETHERNET_MAC_VLAN_TAG_VL_Pos                          0                                                         /*!< ETHERNET MAC_VLAN_TAG: VL Position  */
-#define ETHERNET_MAC_VLAN_TAG_VL_Msk                          (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos)            /*!< ETHERNET MAC_VLAN_TAG: VL Mask      */
-#define ETHERNET_MAC_VLAN_TAG_ETV_Pos                         16                                                        /*!< ETHERNET MAC_VLAN_TAG: ETV Position */
-#define ETHERNET_MAC_VLAN_TAG_ETV_Msk                         (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos)                 /*!< ETHERNET MAC_VLAN_TAG: ETV Mask     */
-
-// -----------------------------------  ETHERNET_MAC_DEBUG  ---------------------------------------
-#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos                     0                                                         /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */
-#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos)             /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */
-#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos                      1                                                         /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */
-#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos)              /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask  */
-#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos                    4                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */
-#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos)            /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */
-#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos                     5                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */
-#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos)             /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */
-#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos                      8                                                         /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */
-#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos)              /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask  */
-#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos                     16                                                        /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */
-#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos)             /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */
-#define ETHERNET_MAC_DEBUG_TXSTAT_Pos                         17                                                        /*!< ETHERNET MAC_DEBUG: TXSTAT Position */
-#define ETHERNET_MAC_DEBUG_TXSTAT_Msk                         (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos)                 /*!< ETHERNET MAC_DEBUG: TXSTAT Mask     */
-#define ETHERNET_MAC_DEBUG_PAUSE_Pos                          19                                                        /*!< ETHERNET MAC_DEBUG: PAUSE Position  */
-#define ETHERNET_MAC_DEBUG_PAUSE_Msk                          (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos)                  /*!< ETHERNET MAC_DEBUG: PAUSE Mask      */
-#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos                     20                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */
-#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos)             /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */
-#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos                    22                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */
-#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos)            /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */
-#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos                      24                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */
-#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk                      (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos)              /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask  */
-#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos                     25                                                        /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */
-#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos)             /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */
-
-// --------------------------------  ETHERNET_MAC_RWAKE_FRFLT  ------------------------------------
-#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos                     0                                                         /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */
-#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk                     (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos)       /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */
-
-// -------------------------------  ETHERNET_MAC_PMT_CTRL_STAT  -----------------------------------
-#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos                     0                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */
-#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos)             /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */
-#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos                    1                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */
-#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos                    2                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */
-#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos                    5                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */
-#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos                    6                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos)            /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */
-#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos                     9                                                         /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */
-#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos)             /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos                 31                                                        /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk                 (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos)         /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */
-
-// ---------------------------------  ETHERNET_MAC_INTR_MASK  -------------------------------------
-#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos                     3                                                         /*!< ETHERNET MAC_INTR_MASK: PMTMSK Position */
-#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk                     (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos)             /*!< ETHERNET MAC_INTR_MASK: PMTMSK Mask */
-
-// ---------------------------------  ETHERNET_MAC_ADDR0_HIGH  ------------------------------------
-#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos                    0                                                         /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */
-#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk                    (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos)      /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */
-#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos                        31                                                        /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */
-#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk                        (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos)                /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask    */
-
-// ---------------------------------  ETHERNET_MAC_ADDR0_LOW  -------------------------------------
-#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos                      0                                                         /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */
-#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk                      (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos)        /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask  */
-
-// --------------------------------  ETHERNET_MAC_TIMESTP_CTRL  -----------------------------------
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos                   0                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk                   (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos)           /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos                1                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos)        /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos                  2                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos                  3                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos                  4                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos)          /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos                5                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos)        /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos                 8                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos)         /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos               9                                                         /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos               10                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos                 11                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos)         /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos               12                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos               13                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos               14                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos               15                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos               16                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk               (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos)       /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos             18                                                        /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk             (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos)     /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */
-
-// ---------------------------------  ETHERNET_SUBSECOND_INCR  ------------------------------------
-#define ETHERNET_SUBSECOND_INCR_SSINC_Pos                     0                                                         /*!< ETHERNET SUBSECOND_INCR: SSINC Position */
-#define ETHERNET_SUBSECOND_INCR_SSINC_Msk                     (0x000000ffUL << ETHERNET_SUBSECOND_INCR_SSINC_Pos)       /*!< ETHERNET SUBSECOND_INCR: SSINC Mask */
-
-// ------------------------------------  ETHERNET_SECONDS  ----------------------------------------
-#define ETHERNET_SECONDS_TSS_Pos                              0                                                         /*!< ETHERNET SECONDS: TSS Position      */
-#define ETHERNET_SECONDS_TSS_Msk                              (0xffffffffUL << ETHERNET_SECONDS_TSS_Pos)                /*!< ETHERNET SECONDS: TSS Mask          */
-
-// ----------------------------------  ETHERNET_NANOSECONDS  --------------------------------------
-#define ETHERNET_NANOSECONDS_TSSS_Pos                         0                                                         /*!< ETHERNET NANOSECONDS: TSSS Position */
-#define ETHERNET_NANOSECONDS_TSSS_Msk                         (0x7fffffffUL << ETHERNET_NANOSECONDS_TSSS_Pos)           /*!< ETHERNET NANOSECONDS: TSSS Mask     */
-#define ETHERNET_NANOSECONDS_PSNT_Pos                         31                                                        /*!< ETHERNET NANOSECONDS: PSNT Position */
-#define ETHERNET_NANOSECONDS_PSNT_Msk                         (0x01UL << ETHERNET_NANOSECONDS_PSNT_Pos)                 /*!< ETHERNET NANOSECONDS: PSNT Mask     */
-
-// ---------------------------------  ETHERNET_SECONDSUPDATE  -------------------------------------
-#define ETHERNET_SECONDSUPDATE_TSS_Pos                        0                                                         /*!< ETHERNET SECONDSUPDATE: TSS Position */
-#define ETHERNET_SECONDSUPDATE_TSS_Msk                        (0xffffffffUL << ETHERNET_SECONDSUPDATE_TSS_Pos)          /*!< ETHERNET SECONDSUPDATE: TSS Mask    */
-
-// -------------------------------  ETHERNET_NANOSECONDSUPDATE  -----------------------------------
-#define ETHERNET_NANOSECONDSUPDATE_TSSS_Pos                   0                                                         /*!< ETHERNET NANOSECONDSUPDATE: TSSS Position */
-#define ETHERNET_NANOSECONDSUPDATE_TSSS_Msk                   (0x7fffffffUL << ETHERNET_NANOSECONDSUPDATE_TSSS_Pos)     /*!< ETHERNET NANOSECONDSUPDATE: TSSS Mask */
-#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos                 31                                                        /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Position */
-#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Msk                 (0x01UL << ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos)         /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Mask */
-
-// -------------------------------------  ETHERNET_ADDEND  ----------------------------------------
-#define ETHERNET_ADDEND_TSAR_Pos                              0                                                         /*!< ETHERNET ADDEND: TSAR Position      */
-#define ETHERNET_ADDEND_TSAR_Msk                              (0xffffffffUL << ETHERNET_ADDEND_TSAR_Pos)                /*!< ETHERNET ADDEND: TSAR Mask          */
-
-// ---------------------------------  ETHERNET_TARGETSECONDS  -------------------------------------
-#define ETHERNET_TARGETSECONDS_TSTR_Pos                       0                                                         /*!< ETHERNET TARGETSECONDS: TSTR Position */
-#define ETHERNET_TARGETSECONDS_TSTR_Msk                       (0xffffffffUL << ETHERNET_TARGETSECONDS_TSTR_Pos)         /*!< ETHERNET TARGETSECONDS: TSTR Mask   */
-
-// -------------------------------  ETHERNET_TARGETNANOSECONDS  -----------------------------------
-#define ETHERNET_TARGETNANOSECONDS_TSTR_Pos                   0                                                         /*!< ETHERNET TARGETNANOSECONDS: TSTR Position */
-#define ETHERNET_TARGETNANOSECONDS_TSTR_Msk                   (0x7fffffffUL << ETHERNET_TARGETNANOSECONDS_TSTR_Pos)     /*!< ETHERNET TARGETNANOSECONDS: TSTR Mask */
-
-// ------------------------------------  ETHERNET_HIGHWORD  ---------------------------------------
-#define ETHERNET_HIGHWORD_TSHWR_Pos                           0                                                         /*!< ETHERNET HIGHWORD: TSHWR Position   */
-#define ETHERNET_HIGHWORD_TSHWR_Msk                           (0x0000ffffUL << ETHERNET_HIGHWORD_TSHWR_Pos)             /*!< ETHERNET HIGHWORD: TSHWR Mask       */
-
-// ---------------------------------  ETHERNET_TIMESTAMPSTAT  -------------------------------------
-#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos                     0                                                         /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Position */
-#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos)             /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Mask */
-#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos                    1                                                         /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Position */
-#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Msk                    (0x01UL << ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos)            /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Mask */
-#define ETHERNET_TIMESTAMPSTAT_AUXSS_Pos                      2                                                         /*!< ETHERNET TIMESTAMPSTAT: AUXSS Position */
-#define ETHERNET_TIMESTAMPSTAT_AUXSS_Msk                      (0x01UL << ETHERNET_TIMESTAMPSTAT_AUXSS_Pos)              /*!< ETHERNET TIMESTAMPSTAT: AUXSS Mask  */
-#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos                     24                                                        /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Position */
-#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos)             /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Mask */
-#define ETHERNET_TIMESTAMPSTAT_ATSNS_Pos                      25                                                        /*!< ETHERNET TIMESTAMPSTAT: ATSNS Position */
-#define ETHERNET_TIMESTAMPSTAT_ATSNS_Msk                      (0x07UL << ETHERNET_TIMESTAMPSTAT_ATSNS_Pos)              /*!< ETHERNET TIMESTAMPSTAT: ATSNS Mask  */
-
-// ------------------------------------  ETHERNET_PPSCTRL  ----------------------------------------
-#define ETHERNET_PPSCTRL_PPSCTRL_Pos                          0                                                         /*!< ETHERNET PPSCTRL: PPSCTRL Position  */
-#define ETHERNET_PPSCTRL_PPSCTRL_Msk                          (0x0fUL << ETHERNET_PPSCTRL_PPSCTRL_Pos)                  /*!< ETHERNET PPSCTRL: PPSCTRL Mask      */
-
-// ---------------------------------  ETHERNET_AUXNANOSECONDS  ------------------------------------
-#define ETHERNET_AUXNANOSECONDS_AUXNS_Pos                     0                                                         /*!< ETHERNET AUXNANOSECONDS: AUXNS Position */
-#define ETHERNET_AUXNANOSECONDS_AUXNS_Msk                     (0xffffffffUL << ETHERNET_AUXNANOSECONDS_AUXNS_Pos)       /*!< ETHERNET AUXNANOSECONDS: AUXNS Mask */
-
-// -----------------------------------  ETHERNET_AUXSECONDS  --------------------------------------
-#define ETHERNET_AUXSECONDS_AUXS_Pos                          0                                                         /*!< ETHERNET AUXSECONDS: AUXS Position  */
-#define ETHERNET_AUXSECONDS_AUXS_Msk                          (0xffffffffUL << ETHERNET_AUXSECONDS_AUXS_Pos)            /*!< ETHERNET AUXSECONDS: AUXS Mask      */
-
-// ----------------------------------  ETHERNET_DMA_BUS_MODE  -------------------------------------
-#define ETHERNET_DMA_BUS_MODE_SWR_Pos                         0                                                         /*!< ETHERNET DMA_BUS_MODE: SWR Position */
-#define ETHERNET_DMA_BUS_MODE_SWR_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos)                 /*!< ETHERNET DMA_BUS_MODE: SWR Mask     */
-#define ETHERNET_DMA_BUS_MODE_DA_Pos                          1                                                         /*!< ETHERNET DMA_BUS_MODE: DA Position  */
-#define ETHERNET_DMA_BUS_MODE_DA_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos)                  /*!< ETHERNET DMA_BUS_MODE: DA Mask      */
-#define ETHERNET_DMA_BUS_MODE_DSL_Pos                         2                                                         /*!< ETHERNET DMA_BUS_MODE: DSL Position */
-#define ETHERNET_DMA_BUS_MODE_DSL_Msk                         (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: DSL Mask     */
-#define ETHERNET_DMA_BUS_MODE_ATDS_Pos                        7                                                         /*!< ETHERNET DMA_BUS_MODE: ATDS Position */
-#define ETHERNET_DMA_BUS_MODE_ATDS_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos)                /*!< ETHERNET DMA_BUS_MODE: ATDS Mask    */
-#define ETHERNET_DMA_BUS_MODE_PBL_Pos                         8                                                         /*!< ETHERNET DMA_BUS_MODE: PBL Position */
-#define ETHERNET_DMA_BUS_MODE_PBL_Msk                         (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: PBL Mask     */
-#define ETHERNET_DMA_BUS_MODE_PR_Pos                          14                                                        /*!< ETHERNET DMA_BUS_MODE: PR Position  */
-#define ETHERNET_DMA_BUS_MODE_PR_Msk                          (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos)                  /*!< ETHERNET DMA_BUS_MODE: PR Mask      */
-#define ETHERNET_DMA_BUS_MODE_FB_Pos                          16                                                        /*!< ETHERNET DMA_BUS_MODE: FB Position  */
-#define ETHERNET_DMA_BUS_MODE_FB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos)                  /*!< ETHERNET DMA_BUS_MODE: FB Mask      */
-#define ETHERNET_DMA_BUS_MODE_RPBL_Pos                        17                                                        /*!< ETHERNET DMA_BUS_MODE: RPBL Position */
-#define ETHERNET_DMA_BUS_MODE_RPBL_Msk                        (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos)                /*!< ETHERNET DMA_BUS_MODE: RPBL Mask    */
-#define ETHERNET_DMA_BUS_MODE_USP_Pos                         23                                                        /*!< ETHERNET DMA_BUS_MODE: USP Position */
-#define ETHERNET_DMA_BUS_MODE_USP_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos)                 /*!< ETHERNET DMA_BUS_MODE: USP Mask     */
-#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos                       24                                                        /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */
-#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk                       (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos)               /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask   */
-#define ETHERNET_DMA_BUS_MODE_AAL_Pos                         25                                                        /*!< ETHERNET DMA_BUS_MODE: AAL Position */
-#define ETHERNET_DMA_BUS_MODE_AAL_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos)                 /*!< ETHERNET DMA_BUS_MODE: AAL Mask     */
-#define ETHERNET_DMA_BUS_MODE_MB_Pos                          26                                                        /*!< ETHERNET DMA_BUS_MODE: MB Position  */
-#define ETHERNET_DMA_BUS_MODE_MB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos)                  /*!< ETHERNET DMA_BUS_MODE: MB Mask      */
-#define ETHERNET_DMA_BUS_MODE_TXPR_Pos                        27                                                        /*!< ETHERNET DMA_BUS_MODE: TXPR Position */
-#define ETHERNET_DMA_BUS_MODE_TXPR_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos)                /*!< ETHERNET DMA_BUS_MODE: TXPR Mask    */
-
-// -----------------------------  ETHERNET_DMA_TRANS_POLL_DEMAND  ---------------------------------
-#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos                0                                                         /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */
-#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk                (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos)  /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */
-
-// ------------------------------  ETHERNET_DMA_REC_POLL_DEMAND  ----------------------------------
-#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos                  0                                                         /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */
-#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk                  (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos)    /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */
-
-// --------------------------------  ETHERNET_DMA_REC_DES_ADDR  -----------------------------------
-#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos                     0                                                         /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */
-#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk                     (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos)       /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */
-
-// -------------------------------  ETHERNET_DMA_TRANS_DES_ADDR  ----------------------------------
-#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos                   0                                                         /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */
-#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk                   (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos)     /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */
-
-// ------------------------------------  ETHERNET_DMA_STAT  ---------------------------------------
-#define ETHERNET_DMA_STAT_TI_Pos                              0                                                         /*!< ETHERNET DMA_STAT: TI Position      */
-#define ETHERNET_DMA_STAT_TI_Msk                              (0x01UL << ETHERNET_DMA_STAT_TI_Pos)                      /*!< ETHERNET DMA_STAT: TI Mask          */
-#define ETHERNET_DMA_STAT_TPS_Pos                             1                                                         /*!< ETHERNET DMA_STAT: TPS Position     */
-#define ETHERNET_DMA_STAT_TPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_TPS_Pos)                     /*!< ETHERNET DMA_STAT: TPS Mask         */
-#define ETHERNET_DMA_STAT_TU_Pos                              2                                                         /*!< ETHERNET DMA_STAT: TU Position      */
-#define ETHERNET_DMA_STAT_TU_Msk                              (0x01UL << ETHERNET_DMA_STAT_TU_Pos)                      /*!< ETHERNET DMA_STAT: TU Mask          */
-#define ETHERNET_DMA_STAT_TJT_Pos                             3                                                         /*!< ETHERNET DMA_STAT: TJT Position     */
-#define ETHERNET_DMA_STAT_TJT_Msk                             (0x01UL << ETHERNET_DMA_STAT_TJT_Pos)                     /*!< ETHERNET DMA_STAT: TJT Mask         */
-#define ETHERNET_DMA_STAT_OVF_Pos                             4                                                         /*!< ETHERNET DMA_STAT: OVF Position     */
-#define ETHERNET_DMA_STAT_OVF_Msk                             (0x01UL << ETHERNET_DMA_STAT_OVF_Pos)                     /*!< ETHERNET DMA_STAT: OVF Mask         */
-#define ETHERNET_DMA_STAT_UNF_Pos                             5                                                         /*!< ETHERNET DMA_STAT: UNF Position     */
-#define ETHERNET_DMA_STAT_UNF_Msk                             (0x01UL << ETHERNET_DMA_STAT_UNF_Pos)                     /*!< ETHERNET DMA_STAT: UNF Mask         */
-#define ETHERNET_DMA_STAT_RI_Pos                              6                                                         /*!< ETHERNET DMA_STAT: RI Position      */
-#define ETHERNET_DMA_STAT_RI_Msk                              (0x01UL << ETHERNET_DMA_STAT_RI_Pos)                      /*!< ETHERNET DMA_STAT: RI Mask          */
-#define ETHERNET_DMA_STAT_RU_Pos                              7                                                         /*!< ETHERNET DMA_STAT: RU Position      */
-#define ETHERNET_DMA_STAT_RU_Msk                              (0x01UL << ETHERNET_DMA_STAT_RU_Pos)                      /*!< ETHERNET DMA_STAT: RU Mask          */
-#define ETHERNET_DMA_STAT_RPS_Pos                             8                                                         /*!< ETHERNET DMA_STAT: RPS Position     */
-#define ETHERNET_DMA_STAT_RPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_RPS_Pos)                     /*!< ETHERNET DMA_STAT: RPS Mask         */
-#define ETHERNET_DMA_STAT_RWT_Pos                             9                                                         /*!< ETHERNET DMA_STAT: RWT Position     */
-#define ETHERNET_DMA_STAT_RWT_Msk                             (0x01UL << ETHERNET_DMA_STAT_RWT_Pos)                     /*!< ETHERNET DMA_STAT: RWT Mask         */
-#define ETHERNET_DMA_STAT_ETI_Pos                             10                                                        /*!< ETHERNET DMA_STAT: ETI Position     */
-#define ETHERNET_DMA_STAT_ETI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ETI_Pos)                     /*!< ETHERNET DMA_STAT: ETI Mask         */
-#define ETHERNET_DMA_STAT_FBI_Pos                             13                                                        /*!< ETHERNET DMA_STAT: FBI Position     */
-#define ETHERNET_DMA_STAT_FBI_Msk                             (0x01UL << ETHERNET_DMA_STAT_FBI_Pos)                     /*!< ETHERNET DMA_STAT: FBI Mask         */
-#define ETHERNET_DMA_STAT_ERI_Pos                             14                                                        /*!< ETHERNET DMA_STAT: ERI Position     */
-#define ETHERNET_DMA_STAT_ERI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ERI_Pos)                     /*!< ETHERNET DMA_STAT: ERI Mask         */
-#define ETHERNET_DMA_STAT_AIE_Pos                             15                                                        /*!< ETHERNET DMA_STAT: AIE Position     */
-#define ETHERNET_DMA_STAT_AIE_Msk                             (0x01UL << ETHERNET_DMA_STAT_AIE_Pos)                     /*!< ETHERNET DMA_STAT: AIE Mask         */
-#define ETHERNET_DMA_STAT_NIS_Pos                             16                                                        /*!< ETHERNET DMA_STAT: NIS Position     */
-#define ETHERNET_DMA_STAT_NIS_Msk                             (0x01UL << ETHERNET_DMA_STAT_NIS_Pos)                     /*!< ETHERNET DMA_STAT: NIS Mask         */
-
-// ----------------------------------  ETHERNET_DMA_OP_MODE  --------------------------------------
-#define ETHERNET_DMA_OP_MODE_SR_Pos                           1                                                         /*!< ETHERNET DMA_OP_MODE: SR Position   */
-#define ETHERNET_DMA_OP_MODE_SR_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos)                   /*!< ETHERNET DMA_OP_MODE: SR Mask       */
-#define ETHERNET_DMA_OP_MODE_OSF_Pos                          2                                                         /*!< ETHERNET DMA_OP_MODE: OSF Position  */
-#define ETHERNET_DMA_OP_MODE_OSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: OSF Mask      */
-#define ETHERNET_DMA_OP_MODE_RTC_Pos                          3                                                         /*!< ETHERNET DMA_OP_MODE: RTC Position  */
-#define ETHERNET_DMA_OP_MODE_RTC_Msk                          (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos)                  /*!< ETHERNET DMA_OP_MODE: RTC Mask      */
-#define ETHERNET_DMA_OP_MODE_FUF_Pos                          6                                                         /*!< ETHERNET DMA_OP_MODE: FUF Position  */
-#define ETHERNET_DMA_OP_MODE_FUF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FUF Mask      */
-#define ETHERNET_DMA_OP_MODE_FEF_Pos                          7                                                         /*!< ETHERNET DMA_OP_MODE: FEF Position  */
-#define ETHERNET_DMA_OP_MODE_FEF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FEF Mask      */
-#define ETHERNET_DMA_OP_MODE_ST_Pos                           13                                                        /*!< ETHERNET DMA_OP_MODE: ST Position   */
-#define ETHERNET_DMA_OP_MODE_ST_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos)                   /*!< ETHERNET DMA_OP_MODE: ST Mask       */
-#define ETHERNET_DMA_OP_MODE_TTC_Pos                          14                                                        /*!< ETHERNET DMA_OP_MODE: TTC Position  */
-#define ETHERNET_DMA_OP_MODE_TTC_Msk                          (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos)                  /*!< ETHERNET DMA_OP_MODE: TTC Mask      */
-#define ETHERNET_DMA_OP_MODE_FTF_Pos                          20                                                        /*!< ETHERNET DMA_OP_MODE: FTF Position  */
-#define ETHERNET_DMA_OP_MODE_FTF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos)                  /*!< ETHERNET DMA_OP_MODE: FTF Mask      */
-#define ETHERNET_DMA_OP_MODE_TSF_Pos                          21                                                        /*!< ETHERNET DMA_OP_MODE: TSF Position  */
-#define ETHERNET_DMA_OP_MODE_TSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: TSF Mask      */
-#define ETHERNET_DMA_OP_MODE_DFF_Pos                          24                                                        /*!< ETHERNET DMA_OP_MODE: DFF Position  */
-#define ETHERNET_DMA_OP_MODE_DFF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos)                  /*!< ETHERNET DMA_OP_MODE: DFF Mask      */
-#define ETHERNET_DMA_OP_MODE_RSF_Pos                          25                                                        /*!< ETHERNET DMA_OP_MODE: RSF Position  */
-#define ETHERNET_DMA_OP_MODE_RSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos)                  /*!< ETHERNET DMA_OP_MODE: RSF Mask      */
-#define ETHERNET_DMA_OP_MODE_DT_Pos                           26                                                        /*!< ETHERNET DMA_OP_MODE: DT Position   */
-#define ETHERNET_DMA_OP_MODE_DT_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos)                   /*!< ETHERNET DMA_OP_MODE: DT Mask       */
-
-// -----------------------------------  ETHERNET_DMA_INT_EN  --------------------------------------
-#define ETHERNET_DMA_INT_EN_TIE_Pos                           0                                                         /*!< ETHERNET DMA_INT_EN: TIE Position   */
-#define ETHERNET_DMA_INT_EN_TIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos)                   /*!< ETHERNET DMA_INT_EN: TIE Mask       */
-#define ETHERNET_DMA_INT_EN_TSE_Pos                           1                                                         /*!< ETHERNET DMA_INT_EN: TSE Position   */
-#define ETHERNET_DMA_INT_EN_TSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos)                   /*!< ETHERNET DMA_INT_EN: TSE Mask       */
-#define ETHERNET_DMA_INT_EN_TUE_Pos                           2                                                         /*!< ETHERNET DMA_INT_EN: TUE Position   */
-#define ETHERNET_DMA_INT_EN_TUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos)                   /*!< ETHERNET DMA_INT_EN: TUE Mask       */
-#define ETHERNET_DMA_INT_EN_TJE_Pos                           3                                                         /*!< ETHERNET DMA_INT_EN: TJE Position   */
-#define ETHERNET_DMA_INT_EN_TJE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos)                   /*!< ETHERNET DMA_INT_EN: TJE Mask       */
-#define ETHERNET_DMA_INT_EN_OVE_Pos                           4                                                         /*!< ETHERNET DMA_INT_EN: OVE Position   */
-#define ETHERNET_DMA_INT_EN_OVE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos)                   /*!< ETHERNET DMA_INT_EN: OVE Mask       */
-#define ETHERNET_DMA_INT_EN_UNE_Pos                           5                                                         /*!< ETHERNET DMA_INT_EN: UNE Position   */
-#define ETHERNET_DMA_INT_EN_UNE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos)                   /*!< ETHERNET DMA_INT_EN: UNE Mask       */
-#define ETHERNET_DMA_INT_EN_RIE_Pos                           6                                                         /*!< ETHERNET DMA_INT_EN: RIE Position   */
-#define ETHERNET_DMA_INT_EN_RIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos)                   /*!< ETHERNET DMA_INT_EN: RIE Mask       */
-#define ETHERNET_DMA_INT_EN_RUE_Pos                           7                                                         /*!< ETHERNET DMA_INT_EN: RUE Position   */
-#define ETHERNET_DMA_INT_EN_RUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos)                   /*!< ETHERNET DMA_INT_EN: RUE Mask       */
-#define ETHERNET_DMA_INT_EN_RSE_Pos                           8                                                         /*!< ETHERNET DMA_INT_EN: RSE Position   */
-#define ETHERNET_DMA_INT_EN_RSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos)                   /*!< ETHERNET DMA_INT_EN: RSE Mask       */
-#define ETHERNET_DMA_INT_EN_RWE_Pos                           9                                                         /*!< ETHERNET DMA_INT_EN: RWE Position   */
-#define ETHERNET_DMA_INT_EN_RWE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos)                   /*!< ETHERNET DMA_INT_EN: RWE Mask       */
-#define ETHERNET_DMA_INT_EN_ETE_Pos                           10                                                        /*!< ETHERNET DMA_INT_EN: ETE Position   */
-#define ETHERNET_DMA_INT_EN_ETE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos)                   /*!< ETHERNET DMA_INT_EN: ETE Mask       */
-#define ETHERNET_DMA_INT_EN_FBE_Pos                           13                                                        /*!< ETHERNET DMA_INT_EN: FBE Position   */
-#define ETHERNET_DMA_INT_EN_FBE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos)                   /*!< ETHERNET DMA_INT_EN: FBE Mask       */
-#define ETHERNET_DMA_INT_EN_ERE_Pos                           14                                                        /*!< ETHERNET DMA_INT_EN: ERE Position   */
-#define ETHERNET_DMA_INT_EN_ERE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos)                   /*!< ETHERNET DMA_INT_EN: ERE Mask       */
-#define ETHERNET_DMA_INT_EN_AIE_Pos                           15                                                        /*!< ETHERNET DMA_INT_EN: AIE Position   */
-#define ETHERNET_DMA_INT_EN_AIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos)                   /*!< ETHERNET DMA_INT_EN: AIE Mask       */
-#define ETHERNET_DMA_INT_EN_NIE_Pos                           16                                                        /*!< ETHERNET DMA_INT_EN: NIE Position   */
-#define ETHERNET_DMA_INT_EN_NIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos)                   /*!< ETHERNET DMA_INT_EN: NIE Mask       */
-
-// ---------------------------------  ETHERNET_DMA_MFRM_BUFOF  ------------------------------------
-#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos                       0                                                         /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */
-#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk                       (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos)         /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask   */
-#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos                        16                                                        /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */
-#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos)                /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask    */
-#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos                       17                                                        /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */
-#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk                       (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos)         /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask   */
-#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos                        28                                                        /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */
-#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos)                /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask    */
-
-// --------------------------------  ETHERNET_DMA_REC_INT_WDT  ------------------------------------
-#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos                     0                                                         /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */
-#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk                     (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos)       /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */
-
-// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_DES  ---------------------------------
-#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos                0                                                         /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */
-#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos)  /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */
-
-// ------------------------------  ETHERNET_DMA_CURHOST_REC_DES  ----------------------------------
-#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos                  0                                                         /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */
-#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos)    /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */
-
-// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_BUF  ---------------------------------
-#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos                0                                                         /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */
-#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos)  /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */
-
-// ------------------------------  ETHERNET_DMA_CURHOST_REC_BUF  ----------------------------------
-#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos                  0                                                         /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */
-#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos)    /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                ATIMER Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------  ATIMER_DOWNCOUNTER  ---------------------------------------
-#define ATIMER_DOWNCOUNTER_CVAL_Pos                           0                                                         /*!< ATIMER DOWNCOUNTER: CVAL Position   */
-#define ATIMER_DOWNCOUNTER_CVAL_Msk                           (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos)             /*!< ATIMER DOWNCOUNTER: CVAL Mask       */
-
-// --------------------------------------  ATIMER_PRESET  -----------------------------------------
-#define ATIMER_PRESET_PRESETVAL_Pos                           0                                                         /*!< ATIMER PRESET: PRESETVAL Position   */
-#define ATIMER_PRESET_PRESETVAL_Msk                           (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos)             /*!< ATIMER PRESET: PRESETVAL Mask       */
-
-// --------------------------------------  ATIMER_CLR_EN  -----------------------------------------
-#define ATIMER_CLR_EN_CLR_EN_Pos                              0                                                         /*!< ATIMER CLR_EN: CLR_EN Position      */
-#define ATIMER_CLR_EN_CLR_EN_Msk                              (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos)                      /*!< ATIMER CLR_EN: CLR_EN Mask          */
-
-// --------------------------------------  ATIMER_SET_EN  -----------------------------------------
-#define ATIMER_SET_EN_SET_EN_Pos                              0                                                         /*!< ATIMER SET_EN: SET_EN Position      */
-#define ATIMER_SET_EN_SET_EN_Msk                              (0x01UL << ATIMER_SET_EN_SET_EN_Pos)                      /*!< ATIMER SET_EN: SET_EN Mask          */
-
-// --------------------------------------  ATIMER_STATUS  -----------------------------------------
-#define ATIMER_STATUS_STAT_Pos                                0                                                         /*!< ATIMER STATUS: STAT Position        */
-#define ATIMER_STATUS_STAT_Msk                                (0x01UL << ATIMER_STATUS_STAT_Pos)                        /*!< ATIMER STATUS: STAT Mask            */
-
-// --------------------------------------  ATIMER_ENABLE  -----------------------------------------
-#define ATIMER_ENABLE_EN_Pos                                  0                                                         /*!< ATIMER ENABLE: EN Position          */
-#define ATIMER_ENABLE_EN_Msk                                  (0x01UL << ATIMER_ENABLE_EN_Pos)                          /*!< ATIMER ENABLE: EN Mask              */
-
-// -------------------------------------  ATIMER_CLR_STAT  ----------------------------------------
-#define ATIMER_CLR_STAT_CSTAT_Pos                             0                                                         /*!< ATIMER CLR_STAT: CSTAT Position     */
-#define ATIMER_CLR_STAT_CSTAT_Msk                             (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos)                     /*!< ATIMER CLR_STAT: CSTAT Mask         */
-
-// -------------------------------------  ATIMER_SET_STAT  ----------------------------------------
-#define ATIMER_SET_STAT_SSTAT_Pos                             0                                                         /*!< ATIMER SET_STAT: SSTAT Position     */
-#define ATIMER_SET_STAT_SSTAT_Msk                             (0x01UL << ATIMER_SET_STAT_SSTAT_Pos)                     /*!< ATIMER SET_STAT: SSTAT Mask         */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                REGFILE Position & Mask                               -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ------------------------------------  REGFILE_REGFILE0  ----------------------------------------
-#define REGFILE_REGFILE0_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE0: REGVAL Position   */
-#define REGFILE_REGFILE0_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos)             /*!< REGFILE REGFILE0: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE1  ----------------------------------------
-#define REGFILE_REGFILE1_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE1: REGVAL Position   */
-#define REGFILE_REGFILE1_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos)             /*!< REGFILE REGFILE1: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE2  ----------------------------------------
-#define REGFILE_REGFILE2_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE2: REGVAL Position   */
-#define REGFILE_REGFILE2_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos)             /*!< REGFILE REGFILE2: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE3  ----------------------------------------
-#define REGFILE_REGFILE3_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE3: REGVAL Position   */
-#define REGFILE_REGFILE3_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos)             /*!< REGFILE REGFILE3: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE4  ----------------------------------------
-#define REGFILE_REGFILE4_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE4: REGVAL Position   */
-#define REGFILE_REGFILE4_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos)             /*!< REGFILE REGFILE4: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE5  ----------------------------------------
-#define REGFILE_REGFILE5_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE5: REGVAL Position   */
-#define REGFILE_REGFILE5_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos)             /*!< REGFILE REGFILE5: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE6  ----------------------------------------
-#define REGFILE_REGFILE6_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE6: REGVAL Position   */
-#define REGFILE_REGFILE6_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos)             /*!< REGFILE REGFILE6: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE7  ----------------------------------------
-#define REGFILE_REGFILE7_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE7: REGVAL Position   */
-#define REGFILE_REGFILE7_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos)             /*!< REGFILE REGFILE7: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE8  ----------------------------------------
-#define REGFILE_REGFILE8_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE8: REGVAL Position   */
-#define REGFILE_REGFILE8_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos)             /*!< REGFILE REGFILE8: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE9  ----------------------------------------
-#define REGFILE_REGFILE9_REGVAL_Pos                           0                                                         /*!< REGFILE REGFILE9: REGVAL Position   */
-#define REGFILE_REGFILE9_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos)             /*!< REGFILE REGFILE9: REGVAL Mask       */
-
-// ------------------------------------  REGFILE_REGFILE10  ---------------------------------------
-#define REGFILE_REGFILE10_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE10: REGVAL Position  */
-#define REGFILE_REGFILE10_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos)            /*!< REGFILE REGFILE10: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE11  ---------------------------------------
-#define REGFILE_REGFILE11_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE11: REGVAL Position  */
-#define REGFILE_REGFILE11_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos)            /*!< REGFILE REGFILE11: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE12  ---------------------------------------
-#define REGFILE_REGFILE12_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE12: REGVAL Position  */
-#define REGFILE_REGFILE12_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos)            /*!< REGFILE REGFILE12: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE13  ---------------------------------------
-#define REGFILE_REGFILE13_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE13: REGVAL Position  */
-#define REGFILE_REGFILE13_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos)            /*!< REGFILE REGFILE13: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE14  ---------------------------------------
-#define REGFILE_REGFILE14_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE14: REGVAL Position  */
-#define REGFILE_REGFILE14_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos)            /*!< REGFILE REGFILE14: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE15  ---------------------------------------
-#define REGFILE_REGFILE15_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE15: REGVAL Position  */
-#define REGFILE_REGFILE15_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos)            /*!< REGFILE REGFILE15: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE16  ---------------------------------------
-#define REGFILE_REGFILE16_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE16: REGVAL Position  */
-#define REGFILE_REGFILE16_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos)            /*!< REGFILE REGFILE16: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE17  ---------------------------------------
-#define REGFILE_REGFILE17_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE17: REGVAL Position  */
-#define REGFILE_REGFILE17_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos)            /*!< REGFILE REGFILE17: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE18  ---------------------------------------
-#define REGFILE_REGFILE18_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE18: REGVAL Position  */
-#define REGFILE_REGFILE18_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos)            /*!< REGFILE REGFILE18: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE19  ---------------------------------------
-#define REGFILE_REGFILE19_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE19: REGVAL Position  */
-#define REGFILE_REGFILE19_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos)            /*!< REGFILE REGFILE19: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE20  ---------------------------------------
-#define REGFILE_REGFILE20_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE20: REGVAL Position  */
-#define REGFILE_REGFILE20_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos)            /*!< REGFILE REGFILE20: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE21  ---------------------------------------
-#define REGFILE_REGFILE21_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE21: REGVAL Position  */
-#define REGFILE_REGFILE21_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos)            /*!< REGFILE REGFILE21: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE22  ---------------------------------------
-#define REGFILE_REGFILE22_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE22: REGVAL Position  */
-#define REGFILE_REGFILE22_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos)            /*!< REGFILE REGFILE22: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE23  ---------------------------------------
-#define REGFILE_REGFILE23_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE23: REGVAL Position  */
-#define REGFILE_REGFILE23_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos)            /*!< REGFILE REGFILE23: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE24  ---------------------------------------
-#define REGFILE_REGFILE24_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE24: REGVAL Position  */
-#define REGFILE_REGFILE24_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos)            /*!< REGFILE REGFILE24: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE25  ---------------------------------------
-#define REGFILE_REGFILE25_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE25: REGVAL Position  */
-#define REGFILE_REGFILE25_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos)            /*!< REGFILE REGFILE25: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE26  ---------------------------------------
-#define REGFILE_REGFILE26_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE26: REGVAL Position  */
-#define REGFILE_REGFILE26_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos)            /*!< REGFILE REGFILE26: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE27  ---------------------------------------
-#define REGFILE_REGFILE27_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE27: REGVAL Position  */
-#define REGFILE_REGFILE27_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos)            /*!< REGFILE REGFILE27: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE28  ---------------------------------------
-#define REGFILE_REGFILE28_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE28: REGVAL Position  */
-#define REGFILE_REGFILE28_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos)            /*!< REGFILE REGFILE28: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE29  ---------------------------------------
-#define REGFILE_REGFILE29_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE29: REGVAL Position  */
-#define REGFILE_REGFILE29_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos)            /*!< REGFILE REGFILE29: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE30  ---------------------------------------
-#define REGFILE_REGFILE30_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE30: REGVAL Position  */
-#define REGFILE_REGFILE30_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos)            /*!< REGFILE REGFILE30: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE31  ---------------------------------------
-#define REGFILE_REGFILE31_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE31: REGVAL Position  */
-#define REGFILE_REGFILE31_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos)            /*!< REGFILE REGFILE31: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE32  ---------------------------------------
-#define REGFILE_REGFILE32_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE32: REGVAL Position  */
-#define REGFILE_REGFILE32_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos)            /*!< REGFILE REGFILE32: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE33  ---------------------------------------
-#define REGFILE_REGFILE33_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE33: REGVAL Position  */
-#define REGFILE_REGFILE33_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos)            /*!< REGFILE REGFILE33: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE34  ---------------------------------------
-#define REGFILE_REGFILE34_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE34: REGVAL Position  */
-#define REGFILE_REGFILE34_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos)            /*!< REGFILE REGFILE34: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE35  ---------------------------------------
-#define REGFILE_REGFILE35_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE35: REGVAL Position  */
-#define REGFILE_REGFILE35_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos)            /*!< REGFILE REGFILE35: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE36  ---------------------------------------
-#define REGFILE_REGFILE36_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE36: REGVAL Position  */
-#define REGFILE_REGFILE36_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos)            /*!< REGFILE REGFILE36: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE37  ---------------------------------------
-#define REGFILE_REGFILE37_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE37: REGVAL Position  */
-#define REGFILE_REGFILE37_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos)            /*!< REGFILE REGFILE37: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE38  ---------------------------------------
-#define REGFILE_REGFILE38_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE38: REGVAL Position  */
-#define REGFILE_REGFILE38_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos)            /*!< REGFILE REGFILE38: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE39  ---------------------------------------
-#define REGFILE_REGFILE39_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE39: REGVAL Position  */
-#define REGFILE_REGFILE39_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos)            /*!< REGFILE REGFILE39: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE40  ---------------------------------------
-#define REGFILE_REGFILE40_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE40: REGVAL Position  */
-#define REGFILE_REGFILE40_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos)            /*!< REGFILE REGFILE40: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE41  ---------------------------------------
-#define REGFILE_REGFILE41_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE41: REGVAL Position  */
-#define REGFILE_REGFILE41_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos)            /*!< REGFILE REGFILE41: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE42  ---------------------------------------
-#define REGFILE_REGFILE42_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE42: REGVAL Position  */
-#define REGFILE_REGFILE42_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos)            /*!< REGFILE REGFILE42: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE43  ---------------------------------------
-#define REGFILE_REGFILE43_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE43: REGVAL Position  */
-#define REGFILE_REGFILE43_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos)            /*!< REGFILE REGFILE43: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE44  ---------------------------------------
-#define REGFILE_REGFILE44_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE44: REGVAL Position  */
-#define REGFILE_REGFILE44_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos)            /*!< REGFILE REGFILE44: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE45  ---------------------------------------
-#define REGFILE_REGFILE45_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE45: REGVAL Position  */
-#define REGFILE_REGFILE45_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos)            /*!< REGFILE REGFILE45: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE46  ---------------------------------------
-#define REGFILE_REGFILE46_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE46: REGVAL Position  */
-#define REGFILE_REGFILE46_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos)            /*!< REGFILE REGFILE46: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE47  ---------------------------------------
-#define REGFILE_REGFILE47_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE47: REGVAL Position  */
-#define REGFILE_REGFILE47_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos)            /*!< REGFILE REGFILE47: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE48  ---------------------------------------
-#define REGFILE_REGFILE48_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE48: REGVAL Position  */
-#define REGFILE_REGFILE48_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos)            /*!< REGFILE REGFILE48: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE49  ---------------------------------------
-#define REGFILE_REGFILE49_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE49: REGVAL Position  */
-#define REGFILE_REGFILE49_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos)            /*!< REGFILE REGFILE49: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE50  ---------------------------------------
-#define REGFILE_REGFILE50_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE50: REGVAL Position  */
-#define REGFILE_REGFILE50_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos)            /*!< REGFILE REGFILE50: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE51  ---------------------------------------
-#define REGFILE_REGFILE51_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE51: REGVAL Position  */
-#define REGFILE_REGFILE51_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos)            /*!< REGFILE REGFILE51: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE52  ---------------------------------------
-#define REGFILE_REGFILE52_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE52: REGVAL Position  */
-#define REGFILE_REGFILE52_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos)            /*!< REGFILE REGFILE52: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE53  ---------------------------------------
-#define REGFILE_REGFILE53_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE53: REGVAL Position  */
-#define REGFILE_REGFILE53_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos)            /*!< REGFILE REGFILE53: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE54  ---------------------------------------
-#define REGFILE_REGFILE54_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE54: REGVAL Position  */
-#define REGFILE_REGFILE54_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos)            /*!< REGFILE REGFILE54: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE55  ---------------------------------------
-#define REGFILE_REGFILE55_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE55: REGVAL Position  */
-#define REGFILE_REGFILE55_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos)            /*!< REGFILE REGFILE55: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE56  ---------------------------------------
-#define REGFILE_REGFILE56_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE56: REGVAL Position  */
-#define REGFILE_REGFILE56_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos)            /*!< REGFILE REGFILE56: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE57  ---------------------------------------
-#define REGFILE_REGFILE57_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE57: REGVAL Position  */
-#define REGFILE_REGFILE57_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos)            /*!< REGFILE REGFILE57: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE58  ---------------------------------------
-#define REGFILE_REGFILE58_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE58: REGVAL Position  */
-#define REGFILE_REGFILE58_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos)            /*!< REGFILE REGFILE58: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE59  ---------------------------------------
-#define REGFILE_REGFILE59_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE59: REGVAL Position  */
-#define REGFILE_REGFILE59_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos)            /*!< REGFILE REGFILE59: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE60  ---------------------------------------
-#define REGFILE_REGFILE60_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE60: REGVAL Position  */
-#define REGFILE_REGFILE60_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos)            /*!< REGFILE REGFILE60: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE61  ---------------------------------------
-#define REGFILE_REGFILE61_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE61: REGVAL Position  */
-#define REGFILE_REGFILE61_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos)            /*!< REGFILE REGFILE61: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE62  ---------------------------------------
-#define REGFILE_REGFILE62_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE62: REGVAL Position  */
-#define REGFILE_REGFILE62_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos)            /*!< REGFILE REGFILE62: REGVAL Mask      */
-
-// ------------------------------------  REGFILE_REGFILE63  ---------------------------------------
-#define REGFILE_REGFILE63_REGVAL_Pos                          0                                                         /*!< REGFILE REGFILE63: REGVAL Position  */
-#define REGFILE_REGFILE63_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos)            /*!< REGFILE REGFILE63: REGVAL Mask      */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  PMC Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------  PMC_PD0_SLEEP0_HW_ENA  -------------------------------------
-#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos                  0                                                         /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */
-#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk                  (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos)          /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */
-
-// -----------------------------------  PMC_PD0_SLEEP0_MODE  --------------------------------------
-#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos                     0                                                         /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */
-#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk                     (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos)       /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 CREG Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  CREG_IRCTRM  ------------------------------------------
-#define CREG_IRCTRM_TRM_Pos                                   0                                                         /*!< CREG IRCTRM: TRM Position           */
-#define CREG_IRCTRM_TRM_Msk                                   (0x00000fffUL << CREG_IRCTRM_TRM_Pos)                     /*!< CREG IRCTRM: TRM Mask               */
-
-// ---------------------------------------  CREG_CREG0  -------------------------------------------
-#define CREG_CREG0_EN1KHZ_Pos                                 0                                                         /*!< CREG CREG0: EN1KHZ Position         */
-#define CREG_CREG0_EN1KHZ_Msk                                 (0x01UL << CREG_CREG0_EN1KHZ_Pos)                         /*!< CREG CREG0: EN1KHZ Mask             */
-#define CREG_CREG0_EN32KHZ_Pos                                1                                                         /*!< CREG CREG0: EN32KHZ Position        */
-#define CREG_CREG0_EN32KHZ_Msk                                (0x01UL << CREG_CREG0_EN32KHZ_Pos)                        /*!< CREG CREG0: EN32KHZ Mask            */
-#define CREG_CREG0_RESET32KHZ_Pos                             2                                                         /*!< CREG CREG0: RESET32KHZ Position     */
-#define CREG_CREG0_RESET32KHZ_Msk                             (0x01UL << CREG_CREG0_RESET32KHZ_Pos)                     /*!< CREG CREG0: RESET32KHZ Mask         */
-#define CREG_CREG0_32KHZPD_Pos                                3                                                         /*!< CREG CREG0: 32KHZPD Position        */
-#define CREG_CREG0_32KHZPD_Msk                                (0x01UL << CREG_CREG0_32KHZPD_Pos)                        /*!< CREG CREG0: 32KHZPD Mask            */
-#define CREG_CREG0_USB0PHY_Pos                                5                                                         /*!< CREG CREG0: USB0PHY Position        */
-#define CREG_CREG0_USB0PHY_Msk                                (0x01UL << CREG_CREG0_USB0PHY_Pos)                        /*!< CREG CREG0: USB0PHY Mask            */
-#define CREG_CREG0_ALARMCTRL_Pos                              6                                                         /*!< CREG CREG0: ALARMCTRL Position      */
-#define CREG_CREG0_ALARMCTRL_Msk                              (0x03UL << CREG_CREG0_ALARMCTRL_Pos)                      /*!< CREG CREG0: ALARMCTRL Mask          */
-#define CREG_CREG0_BODLVL1_Pos                                8                                                         /*!< CREG CREG0: BODLVL1 Position        */
-#define CREG_CREG0_BODLVL1_Msk                                (0x03UL << CREG_CREG0_BODLVL1_Pos)                        /*!< CREG CREG0: BODLVL1 Mask            */
-#define CREG_CREG0_BODLVL2_Pos                                10                                                        /*!< CREG CREG0: BODLVL2 Position        */
-#define CREG_CREG0_BODLVL2_Msk                                (0x03UL << CREG_CREG0_BODLVL2_Pos)                        /*!< CREG CREG0: BODLVL2 Mask            */
-#define CREG_CREG0_WAKEUP0CTRL_Pos                            14                                                        /*!< CREG CREG0: WAKEUP0CTRL Position    */
-#define CREG_CREG0_WAKEUP0CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos)                    /*!< CREG CREG0: WAKEUP0CTRL Mask        */
-#define CREG_CREG0_WAKEUP1CTRL_Pos                            16                                                        /*!< CREG CREG0: WAKEUP1CTRL Position    */
-#define CREG_CREG0_WAKEUP1CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos)                    /*!< CREG CREG0: WAKEUP1CTRL Mask        */
-
-// --------------------------------------  CREG_M4MEMMAP  -----------------------------------------
-#define CREG_M4MEMMAP_M4MAP_Pos                               12                                                        /*!< CREG M4MEMMAP: M4MAP Position       */
-#define CREG_M4MEMMAP_M4MAP_Msk                               (0x000fffffUL << CREG_M4MEMMAP_M4MAP_Pos)                 /*!< CREG M4MEMMAP: M4MAP Mask           */
-
-// ---------------------------------------  CREG_CREG5  -------------------------------------------
-#define CREG_CREG5_M4TAPSEL_Pos                               6                                                         /*!< CREG CREG5: M4TAPSEL Position       */
-#define CREG_CREG5_M4TAPSEL_Msk                               (0x01UL << CREG_CREG5_M4TAPSEL_Pos)                       /*!< CREG CREG5: M4TAPSEL Mask           */
-
-// ---------------------------------------  CREG_DMAMUX  ------------------------------------------
-#define CREG_DMAMUX_DMAMUXCH0_Pos                             0                                                         /*!< CREG DMAMUX: DMAMUXCH0 Position     */
-#define CREG_DMAMUX_DMAMUXCH0_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos)                     /*!< CREG DMAMUX: DMAMUXCH0 Mask         */
-#define CREG_DMAMUX_DMAMUXCH1_Pos                             2                                                         /*!< CREG DMAMUX: DMAMUXCH1 Position     */
-#define CREG_DMAMUX_DMAMUXCH1_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos)                     /*!< CREG DMAMUX: DMAMUXCH1 Mask         */
-#define CREG_DMAMUX_DMAMUXCH2_Pos                             4                                                         /*!< CREG DMAMUX: DMAMUXCH2 Position     */
-#define CREG_DMAMUX_DMAMUXCH2_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos)                     /*!< CREG DMAMUX: DMAMUXCH2 Mask         */
-#define CREG_DMAMUX_DMAMUXCH3_Pos                             6                                                         /*!< CREG DMAMUX: DMAMUXCH3 Position     */
-#define CREG_DMAMUX_DMAMUXCH3_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos)                     /*!< CREG DMAMUX: DMAMUXCH3 Mask         */
-#define CREG_DMAMUX_DMAMUXCH4_Pos                             8                                                         /*!< CREG DMAMUX: DMAMUXCH4 Position     */
-#define CREG_DMAMUX_DMAMUXCH4_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos)                     /*!< CREG DMAMUX: DMAMUXCH4 Mask         */
-#define CREG_DMAMUX_DMAMUXCH5_Pos                             10                                                        /*!< CREG DMAMUX: DMAMUXCH5 Position     */
-#define CREG_DMAMUX_DMAMUXCH5_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos)                     /*!< CREG DMAMUX: DMAMUXCH5 Mask         */
-#define CREG_DMAMUX_DMAMUXCH6_Pos                             12                                                        /*!< CREG DMAMUX: DMAMUXCH6 Position     */
-#define CREG_DMAMUX_DMAMUXCH6_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos)                     /*!< CREG DMAMUX: DMAMUXCH6 Mask         */
-#define CREG_DMAMUX_DMAMUXCH7_Pos                             14                                                        /*!< CREG DMAMUX: DMAMUXCH7 Position     */
-#define CREG_DMAMUX_DMAMUXCH7_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos)                     /*!< CREG DMAMUX: DMAMUXCH7 Mask         */
-#define CREG_DMAMUX_DMAMUXCH8_Pos                             16                                                        /*!< CREG DMAMUX: DMAMUXCH8 Position     */
-#define CREG_DMAMUX_DMAMUXCH8_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos)                     /*!< CREG DMAMUX: DMAMUXCH8 Mask         */
-#define CREG_DMAMUX_DMAMUXCH9_Pos                             18                                                        /*!< CREG DMAMUX: DMAMUXCH9 Position     */
-#define CREG_DMAMUX_DMAMUXCH9_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos)                     /*!< CREG DMAMUX: DMAMUXCH9 Mask         */
-#define CREG_DMAMUX_DMAMUXCH10_Pos                            20                                                        /*!< CREG DMAMUX: DMAMUXCH10 Position    */
-#define CREG_DMAMUX_DMAMUXCH10_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos)                    /*!< CREG DMAMUX: DMAMUXCH10 Mask        */
-#define CREG_DMAMUX_DMAMUXCH11_Pos                            22                                                        /*!< CREG DMAMUX: DMAMUXCH11 Position    */
-#define CREG_DMAMUX_DMAMUXCH11_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos)                    /*!< CREG DMAMUX: DMAMUXCH11 Mask        */
-#define CREG_DMAMUX_DMAMUXCH12_Pos                            24                                                        /*!< CREG DMAMUX: DMAMUXCH12 Position    */
-#define CREG_DMAMUX_DMAMUXCH12_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos)                    /*!< CREG DMAMUX: DMAMUXCH12 Mask        */
-#define CREG_DMAMUX_DMAMUXCH13_Pos                            26                                                        /*!< CREG DMAMUX: DMAMUXCH13 Position    */
-#define CREG_DMAMUX_DMAMUXCH13_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos)                    /*!< CREG DMAMUX: DMAMUXCH13 Mask        */
-#define CREG_DMAMUX_DMAMUXCH14_Pos                            28                                                        /*!< CREG DMAMUX: DMAMUXCH14 Position    */
-#define CREG_DMAMUX_DMAMUXCH14_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos)                    /*!< CREG DMAMUX: DMAMUXCH14 Mask        */
-#define CREG_DMAMUX_DMAMUXCH15_Pos                            30                                                        /*!< CREG DMAMUX: DMAMUXCH15 Position    */
-#define CREG_DMAMUX_DMAMUXCH15_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos)                    /*!< CREG DMAMUX: DMAMUXCH15 Mask        */
-
-// ---------------------------------------  CREG_ETBCFG  ------------------------------------------
-#define CREG_ETBCFG_ETB_Pos                                   0                                                         /*!< CREG ETBCFG: ETB Position           */
-#define CREG_ETBCFG_ETB_Msk                                   (0x01UL << CREG_ETBCFG_ETB_Pos)                           /*!< CREG ETBCFG: ETB Mask               */
-
-// ---------------------------------------  CREG_CREG6  -------------------------------------------
-#define CREG_CREG6_ETHMODE_Pos                                0                                                         /*!< CREG CREG6: ETHMODE Position        */
-#define CREG_CREG6_ETHMODE_Msk                                (0x07UL << CREG_CREG6_ETHMODE_Pos)                        /*!< CREG CREG6: ETHMODE Mask            */
-#define CREG_CREG6_TIMCTRL_Pos                                4                                                         /*!< CREG CREG6: TIMCTRL Position        */
-#define CREG_CREG6_TIMCTRL_Msk                                (0x01UL << CREG_CREG6_TIMCTRL_Pos)                        /*!< CREG CREG6: TIMCTRL Mask            */
-#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos                     12                                                        /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */
-#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */
-#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos                     13                                                        /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */
-#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */
-#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos                     14                                                        /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */
-#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */
-#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos                     15                                                        /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */
-#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos)             /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */
-#define CREG_CREG6_EMC_CLK_SEL_Pos                            16                                                        /*!< CREG CREG6: EMC_CLK_SEL Position    */
-#define CREG_CREG6_EMC_CLK_SEL_Msk                            (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos)                    /*!< CREG CREG6: EMC_CLK_SEL Mask        */
-
-// -------------------------------------  CREG_M4TXEVENT  -----------------------------------------
-#define CREG_M4TXEVENT_TXEVCLR_Pos                            0                                                         /*!< CREG M4TXEVENT: TXEVCLR Position    */
-#define CREG_M4TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M4TXEVENT_TXEVCLR_Pos)                    /*!< CREG M4TXEVENT: TXEVCLR Mask        */
-
-// ---------------------------------------  CREG_CHIPID  ------------------------------------------
-#define CREG_CHIPID_ID_Pos                                    0                                                         /*!< CREG CHIPID: ID Position            */
-#define CREG_CHIPID_ID_Msk                                    (0xffffffffUL << CREG_CHIPID_ID_Pos)                      /*!< CREG CHIPID: ID Mask                */
-
-// -------------------------------------  CREG_M0TXEVENT  -----------------------------------------
-#define CREG_M0TXEVENT_TXEVCLR_Pos                            0                                                         /*!< CREG M0TXEVENT: TXEVCLR Position    */
-#define CREG_M0TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M0TXEVENT_TXEVCLR_Pos)                    /*!< CREG M0TXEVENT: TXEVCLR Mask        */
-
-// ------------------------------------  CREG_M0APPMEMMAP  ----------------------------------------
-#define CREG_M0APPMEMMAP_M0APPMAP_Pos                         12                                                        /*!< CREG M0APPMEMMAP: M0APPMAP Position */
-#define CREG_M0APPMEMMAP_M0APPMAP_Msk                         (0x000fffffUL << CREG_M0APPMEMMAP_M0APPMAP_Pos)           /*!< CREG M0APPMEMMAP: M0APPMAP Mask     */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                              EVENTROUTER Position & Mask                             -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ------------------------------------  EVENTROUTER_HILO  ----------------------------------------
-#define EVENTROUTER_HILO_WAKEUP0_L_Pos                        0                                                         /*!< EVENTROUTER HILO: WAKEUP0_L Position */
-#define EVENTROUTER_HILO_WAKEUP0_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP0_L Mask    */
-#define EVENTROUTER_HILO_WAKEUP1_L_Pos                        1                                                         /*!< EVENTROUTER HILO: WAKEUP1_L Position */
-#define EVENTROUTER_HILO_WAKEUP1_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP1_L Mask    */
-#define EVENTROUTER_HILO_WAKEUP2_L_Pos                        2                                                         /*!< EVENTROUTER HILO: WAKEUP2_L Position */
-#define EVENTROUTER_HILO_WAKEUP2_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP2_L Mask    */
-#define EVENTROUTER_HILO_WAKEUP3_L_Pos                        3                                                         /*!< EVENTROUTER HILO: WAKEUP3_L Position */
-#define EVENTROUTER_HILO_WAKEUP3_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos)                /*!< EVENTROUTER HILO: WAKEUP3_L Mask    */
-#define EVENTROUTER_HILO_ATIMER_L_Pos                         4                                                         /*!< EVENTROUTER HILO: ATIMER_L Position */
-#define EVENTROUTER_HILO_ATIMER_L_Msk                         (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos)                 /*!< EVENTROUTER HILO: ATIMER_L Mask     */
-#define EVENTROUTER_HILO_RTC_L_Pos                            5                                                         /*!< EVENTROUTER HILO: RTC_L Position    */
-#define EVENTROUTER_HILO_RTC_L_Msk                            (0x01UL << EVENTROUTER_HILO_RTC_L_Pos)                    /*!< EVENTROUTER HILO: RTC_L Mask        */
-#define EVENTROUTER_HILO_BOD_L_Pos                            6                                                         /*!< EVENTROUTER HILO: BOD_L Position    */
-#define EVENTROUTER_HILO_BOD_L_Msk                            (0x01UL << EVENTROUTER_HILO_BOD_L_Pos)                    /*!< EVENTROUTER HILO: BOD_L Mask        */
-#define EVENTROUTER_HILO_WWDT_L_Pos                           7                                                         /*!< EVENTROUTER HILO: WWDT_L Position   */
-#define EVENTROUTER_HILO_WWDT_L_Msk                           (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos)                   /*!< EVENTROUTER HILO: WWDT_L Mask       */
-#define EVENTROUTER_HILO_ETH_L_Pos                            8                                                         /*!< EVENTROUTER HILO: ETH_L Position    */
-#define EVENTROUTER_HILO_ETH_L_Msk                            (0x01UL << EVENTROUTER_HILO_ETH_L_Pos)                    /*!< EVENTROUTER HILO: ETH_L Mask        */
-#define EVENTROUTER_HILO_USB0_L_Pos                           9                                                         /*!< EVENTROUTER HILO: USB0_L Position   */
-#define EVENTROUTER_HILO_USB0_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB0_L_Pos)                   /*!< EVENTROUTER HILO: USB0_L Mask       */
-#define EVENTROUTER_HILO_USB1_L_Pos                           10                                                        /*!< EVENTROUTER HILO: USB1_L Position   */
-#define EVENTROUTER_HILO_USB1_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB1_L_Pos)                   /*!< EVENTROUTER HILO: USB1_L Mask       */
-#define EVENTROUTER_HILO_SDMMC_L_Pos                          11                                                        /*!< EVENTROUTER HILO: SDMMC_L Position  */
-#define EVENTROUTER_HILO_SDMMC_L_Msk                          (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos)                  /*!< EVENTROUTER HILO: SDMMC_L Mask      */
-#define EVENTROUTER_HILO_CAN_L_Pos                            12                                                        /*!< EVENTROUTER HILO: CAN_L Position    */
-#define EVENTROUTER_HILO_CAN_L_Msk                            (0x01UL << EVENTROUTER_HILO_CAN_L_Pos)                    /*!< EVENTROUTER HILO: CAN_L Mask        */
-#define EVENTROUTER_HILO_TIM2_L_Pos                           13                                                        /*!< EVENTROUTER HILO: TIM2_L Position   */
-#define EVENTROUTER_HILO_TIM2_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos)                   /*!< EVENTROUTER HILO: TIM2_L Mask       */
-#define EVENTROUTER_HILO_TIM6_L_Pos                           14                                                        /*!< EVENTROUTER HILO: TIM6_L Position   */
-#define EVENTROUTER_HILO_TIM6_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos)                   /*!< EVENTROUTER HILO: TIM6_L Mask       */
-#define EVENTROUTER_HILO_QEI_L_Pos                            15                                                        /*!< EVENTROUTER HILO: QEI_L Position    */
-#define EVENTROUTER_HILO_QEI_L_Msk                            (0x01UL << EVENTROUTER_HILO_QEI_L_Pos)                    /*!< EVENTROUTER HILO: QEI_L Mask        */
-#define EVENTROUTER_HILO_TIM14_L_Pos                          16                                                        /*!< EVENTROUTER HILO: TIM14_L Position  */
-#define EVENTROUTER_HILO_TIM14_L_Msk                          (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos)                  /*!< EVENTROUTER HILO: TIM14_L Mask      */
-#define EVENTROUTER_HILO_RESET_L_Pos                          19                                                        /*!< EVENTROUTER HILO: RESET_L Position  */
-#define EVENTROUTER_HILO_RESET_L_Msk                          (0x01UL << EVENTROUTER_HILO_RESET_L_Pos)                  /*!< EVENTROUTER HILO: RESET_L Mask      */
-
-// ------------------------------------  EVENTROUTER_EDGE  ----------------------------------------
-#define EVENTROUTER_EDGE_WAKEUP0_E_Pos                        0                                                         /*!< EVENTROUTER EDGE: WAKEUP0_E Position */
-#define EVENTROUTER_EDGE_WAKEUP0_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP0_E Mask    */
-#define EVENTROUTER_EDGE_WAKEUP1_E_Pos                        1                                                         /*!< EVENTROUTER EDGE: WAKEUP1_E Position */
-#define EVENTROUTER_EDGE_WAKEUP1_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP1_E Mask    */
-#define EVENTROUTER_EDGE_WAKEUP2_E_Pos                        2                                                         /*!< EVENTROUTER EDGE: WAKEUP2_E Position */
-#define EVENTROUTER_EDGE_WAKEUP2_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP2_E Mask    */
-#define EVENTROUTER_EDGE_WAKEUP3_E_Pos                        3                                                         /*!< EVENTROUTER EDGE: WAKEUP3_E Position */
-#define EVENTROUTER_EDGE_WAKEUP3_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos)                /*!< EVENTROUTER EDGE: WAKEUP3_E Mask    */
-#define EVENTROUTER_EDGE_ATIMER_E_Pos                         4                                                         /*!< EVENTROUTER EDGE: ATIMER_E Position */
-#define EVENTROUTER_EDGE_ATIMER_E_Msk                         (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos)                 /*!< EVENTROUTER EDGE: ATIMER_E Mask     */
-#define EVENTROUTER_EDGE_RTC_E_Pos                            5                                                         /*!< EVENTROUTER EDGE: RTC_E Position    */
-#define EVENTROUTER_EDGE_RTC_E_Msk                            (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos)                    /*!< EVENTROUTER EDGE: RTC_E Mask        */
-#define EVENTROUTER_EDGE_BOD_E_Pos                            6                                                         /*!< EVENTROUTER EDGE: BOD_E Position    */
-#define EVENTROUTER_EDGE_BOD_E_Msk                            (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos)                    /*!< EVENTROUTER EDGE: BOD_E Mask        */
-#define EVENTROUTER_EDGE_WWDT_E_Pos                           7                                                         /*!< EVENTROUTER EDGE: WWDT_E Position   */
-#define EVENTROUTER_EDGE_WWDT_E_Msk                           (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos)                   /*!< EVENTROUTER EDGE: WWDT_E Mask       */
-#define EVENTROUTER_EDGE_ETH_E_Pos                            8                                                         /*!< EVENTROUTER EDGE: ETH_E Position    */
-#define EVENTROUTER_EDGE_ETH_E_Msk                            (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos)                    /*!< EVENTROUTER EDGE: ETH_E Mask        */
-#define EVENTROUTER_EDGE_USB0_E_Pos                           9                                                         /*!< EVENTROUTER EDGE: USB0_E Position   */
-#define EVENTROUTER_EDGE_USB0_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos)                   /*!< EVENTROUTER EDGE: USB0_E Mask       */
-#define EVENTROUTER_EDGE_USB1_E_Pos                           10                                                        /*!< EVENTROUTER EDGE: USB1_E Position   */
-#define EVENTROUTER_EDGE_USB1_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos)                   /*!< EVENTROUTER EDGE: USB1_E Mask       */
-#define EVENTROUTER_EDGE_SDMMC_E_Pos                          11                                                        /*!< EVENTROUTER EDGE: SDMMC_E Position  */
-#define EVENTROUTER_EDGE_SDMMC_E_Msk                          (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos)                  /*!< EVENTROUTER EDGE: SDMMC_E Mask      */
-#define EVENTROUTER_EDGE_CAN_E_Pos                            12                                                        /*!< EVENTROUTER EDGE: CAN_E Position    */
-#define EVENTROUTER_EDGE_CAN_E_Msk                            (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos)                    /*!< EVENTROUTER EDGE: CAN_E Mask        */
-#define EVENTROUTER_EDGE_TIM2_E_Pos                           13                                                        /*!< EVENTROUTER EDGE: TIM2_E Position   */
-#define EVENTROUTER_EDGE_TIM2_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos)                   /*!< EVENTROUTER EDGE: TIM2_E Mask       */
-#define EVENTROUTER_EDGE_TIM6_E_Pos                           14                                                        /*!< EVENTROUTER EDGE: TIM6_E Position   */
-#define EVENTROUTER_EDGE_TIM6_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos)                   /*!< EVENTROUTER EDGE: TIM6_E Mask       */
-#define EVENTROUTER_EDGE_QEI_E_Pos                            15                                                        /*!< EVENTROUTER EDGE: QEI_E Position    */
-#define EVENTROUTER_EDGE_QEI_E_Msk                            (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos)                    /*!< EVENTROUTER EDGE: QEI_E Mask        */
-#define EVENTROUTER_EDGE_TIM14_E_Pos                          16                                                        /*!< EVENTROUTER EDGE: TIM14_E Position  */
-#define EVENTROUTER_EDGE_TIM14_E_Msk                          (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos)                  /*!< EVENTROUTER EDGE: TIM14_E Mask      */
-#define EVENTROUTER_EDGE_RESET_E_Pos                          19                                                        /*!< EVENTROUTER EDGE: RESET_E Position  */
-#define EVENTROUTER_EDGE_RESET_E_Msk                          (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos)                  /*!< EVENTROUTER EDGE: RESET_E Mask      */
-
-// -----------------------------------  EVENTROUTER_CLR_EN  ---------------------------------------
-#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos                  0                                                         /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */
-#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */
-#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos                  1                                                         /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */
-#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */
-#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos                  2                                                         /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */
-#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */
-#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos                  3                                                         /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */
-#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos)          /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */
-#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos                   4                                                         /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */
-#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk                   (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos)           /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */
-#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos                      5                                                         /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */
-#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask  */
-#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos                      6                                                         /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */
-#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask  */
-#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos                     7                                                         /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */
-#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */
-#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos                      8                                                         /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */
-#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask  */
-#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos                     9                                                         /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */
-#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */
-#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos                     10                                                        /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */
-#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */
-#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos                    11                                                        /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */
-#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */
-#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos                      12                                                        /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */
-#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask  */
-#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos                     13                                                        /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */
-#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */
-#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos                     14                                                        /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */
-#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos)             /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */
-#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos                      15                                                        /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */
-#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos)              /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask  */
-#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos                    16                                                        /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */
-#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */
-#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos                    19                                                        /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */
-#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos)            /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */
-
-// -----------------------------------  EVENTROUTER_SET_EN  ---------------------------------------
-#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos                  0                                                         /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */
-#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */
-#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos                  1                                                         /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */
-#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */
-#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos                  2                                                         /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */
-#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */
-#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos                  3                                                         /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */
-#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos)          /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */
-#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos                   4                                                         /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */
-#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk                   (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos)           /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */
-#define EVENTROUTER_SET_EN_RTC_SETEN_Pos                      5                                                         /*!< EVENTROUTER SET_EN: RTC_SETEN Position */
-#define EVENTROUTER_SET_EN_RTC_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos)              /*!< EVENTROUTER SET_EN: RTC_SETEN Mask  */
-#define EVENTROUTER_SET_EN_BOD_SETEN_Pos                      6                                                         /*!< EVENTROUTER SET_EN: BOD_SETEN Position */
-#define EVENTROUTER_SET_EN_BOD_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos)              /*!< EVENTROUTER SET_EN: BOD_SETEN Mask  */
-#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos                     7                                                         /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */
-#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos)             /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */
-#define EVENTROUTER_SET_EN_ETH_SETEN_Pos                      8                                                         /*!< EVENTROUTER SET_EN: ETH_SETEN Position */
-#define EVENTROUTER_SET_EN_ETH_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos)              /*!< EVENTROUTER SET_EN: ETH_SETEN Mask  */
-#define EVENTROUTER_SET_EN_USB0_SETEN_Pos                     9                                                         /*!< EVENTROUTER SET_EN: USB0_SETEN Position */
-#define EVENTROUTER_SET_EN_USB0_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos)             /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */
-#define EVENTROUTER_SET_EN_USB1_SETEN_Pos                     10                                                        /*!< EVENTROUTER SET_EN: USB1_SETEN Position */
-#define EVENTROUTER_SET_EN_USB1_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos)             /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */
-#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos                    11                                                        /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */
-#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos)            /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */
-#define EVENTROUTER_SET_EN_CAN_SETEN_Pos                      12                                                        /*!< EVENTROUTER SET_EN: CAN_SETEN Position */
-#define EVENTROUTER_SET_EN_CAN_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos)              /*!< EVENTROUTER SET_EN: CAN_SETEN Mask  */
-#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos                     13                                                        /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */
-#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos)             /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */
-#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos                     14                                                        /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */
-#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos)             /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */
-#define EVENTROUTER_SET_EN_QEI_SETEN_Pos                      15                                                        /*!< EVENTROUTER SET_EN: QEI_SETEN Position */
-#define EVENTROUTER_SET_EN_QEI_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos)              /*!< EVENTROUTER SET_EN: QEI_SETEN Mask  */
-#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos                    16                                                        /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */
-#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos)            /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */
-#define EVENTROUTER_SET_EN_RESET_SETEN_Pos                    19                                                        /*!< EVENTROUTER SET_EN: RESET_SETEN Position */
-#define EVENTROUTER_SET_EN_RESET_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos)            /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */
-
-// -----------------------------------  EVENTROUTER_STATUS  ---------------------------------------
-#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos                     0                                                         /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */
-#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */
-#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos                     1                                                         /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */
-#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */
-#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos                     2                                                         /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */
-#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */
-#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos                     3                                                         /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */
-#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos)             /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */
-#define EVENTROUTER_STATUS_ATIMER_ST_Pos                      4                                                         /*!< EVENTROUTER STATUS: ATIMER_ST Position */
-#define EVENTROUTER_STATUS_ATIMER_ST_Msk                      (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos)              /*!< EVENTROUTER STATUS: ATIMER_ST Mask  */
-#define EVENTROUTER_STATUS_RTC_ST_Pos                         5                                                         /*!< EVENTROUTER STATUS: RTC_ST Position */
-#define EVENTROUTER_STATUS_RTC_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos)                 /*!< EVENTROUTER STATUS: RTC_ST Mask     */
-#define EVENTROUTER_STATUS_BOD_ST_Pos                         6                                                         /*!< EVENTROUTER STATUS: BOD_ST Position */
-#define EVENTROUTER_STATUS_BOD_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos)                 /*!< EVENTROUTER STATUS: BOD_ST Mask     */
-#define EVENTROUTER_STATUS_WWDT_ST_Pos                        7                                                         /*!< EVENTROUTER STATUS: WWDT_ST Position */
-#define EVENTROUTER_STATUS_WWDT_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos)                /*!< EVENTROUTER STATUS: WWDT_ST Mask    */
-#define EVENTROUTER_STATUS_ETH_ST_Pos                         8                                                         /*!< EVENTROUTER STATUS: ETH_ST Position */
-#define EVENTROUTER_STATUS_ETH_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos)                 /*!< EVENTROUTER STATUS: ETH_ST Mask     */
-#define EVENTROUTER_STATUS_USB0_ST_Pos                        9                                                         /*!< EVENTROUTER STATUS: USB0_ST Position */
-#define EVENTROUTER_STATUS_USB0_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos)                /*!< EVENTROUTER STATUS: USB0_ST Mask    */
-#define EVENTROUTER_STATUS_USB1_ST_Pos                        10                                                        /*!< EVENTROUTER STATUS: USB1_ST Position */
-#define EVENTROUTER_STATUS_USB1_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos)                /*!< EVENTROUTER STATUS: USB1_ST Mask    */
-#define EVENTROUTER_STATUS_SDMMC_ST_Pos                       11                                                        /*!< EVENTROUTER STATUS: SDMMC_ST Position */
-#define EVENTROUTER_STATUS_SDMMC_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos)               /*!< EVENTROUTER STATUS: SDMMC_ST Mask   */
-#define EVENTROUTER_STATUS_CAN_ST_Pos                         12                                                        /*!< EVENTROUTER STATUS: CAN_ST Position */
-#define EVENTROUTER_STATUS_CAN_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos)                 /*!< EVENTROUTER STATUS: CAN_ST Mask     */
-#define EVENTROUTER_STATUS_TIM2_ST_Pos                        13                                                        /*!< EVENTROUTER STATUS: TIM2_ST Position */
-#define EVENTROUTER_STATUS_TIM2_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos)                /*!< EVENTROUTER STATUS: TIM2_ST Mask    */
-#define EVENTROUTER_STATUS_TIM6_ST_Pos                        14                                                        /*!< EVENTROUTER STATUS: TIM6_ST Position */
-#define EVENTROUTER_STATUS_TIM6_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos)                /*!< EVENTROUTER STATUS: TIM6_ST Mask    */
-#define EVENTROUTER_STATUS_QEI_ST_Pos                         15                                                        /*!< EVENTROUTER STATUS: QEI_ST Position */
-#define EVENTROUTER_STATUS_QEI_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos)                 /*!< EVENTROUTER STATUS: QEI_ST Mask     */
-#define EVENTROUTER_STATUS_TIM14_ST_Pos                       16                                                        /*!< EVENTROUTER STATUS: TIM14_ST Position */
-#define EVENTROUTER_STATUS_TIM14_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos)               /*!< EVENTROUTER STATUS: TIM14_ST Mask   */
-#define EVENTROUTER_STATUS_RESET_ST_Pos                       19                                                        /*!< EVENTROUTER STATUS: RESET_ST Position */
-#define EVENTROUTER_STATUS_RESET_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos)               /*!< EVENTROUTER STATUS: RESET_ST Mask   */
-
-// -----------------------------------  EVENTROUTER_ENABLE  ---------------------------------------
-#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos                     0                                                         /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */
-#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */
-#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos                     1                                                         /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */
-#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */
-#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos                     2                                                         /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */
-#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */
-#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos                     3                                                         /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */
-#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos)             /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */
-#define EVENTROUTER_ENABLE_ATIMER_EN_Pos                      4                                                         /*!< EVENTROUTER ENABLE: ATIMER_EN Position */
-#define EVENTROUTER_ENABLE_ATIMER_EN_Msk                      (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos)              /*!< EVENTROUTER ENABLE: ATIMER_EN Mask  */
-#define EVENTROUTER_ENABLE_RTC_EN_Pos                         5                                                         /*!< EVENTROUTER ENABLE: RTC_EN Position */
-#define EVENTROUTER_ENABLE_RTC_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos)                 /*!< EVENTROUTER ENABLE: RTC_EN Mask     */
-#define EVENTROUTER_ENABLE_BOD_EN_Pos                         6                                                         /*!< EVENTROUTER ENABLE: BOD_EN Position */
-#define EVENTROUTER_ENABLE_BOD_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos)                 /*!< EVENTROUTER ENABLE: BOD_EN Mask     */
-#define EVENTROUTER_ENABLE_WWDT_EN_Pos                        7                                                         /*!< EVENTROUTER ENABLE: WWDT_EN Position */
-#define EVENTROUTER_ENABLE_WWDT_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos)                /*!< EVENTROUTER ENABLE: WWDT_EN Mask    */
-#define EVENTROUTER_ENABLE_ETH_EN_Pos                         8                                                         /*!< EVENTROUTER ENABLE: ETH_EN Position */
-#define EVENTROUTER_ENABLE_ETH_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos)                 /*!< EVENTROUTER ENABLE: ETH_EN Mask     */
-#define EVENTROUTER_ENABLE_USB0_EN_Pos                        9                                                         /*!< EVENTROUTER ENABLE: USB0_EN Position */
-#define EVENTROUTER_ENABLE_USB0_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos)                /*!< EVENTROUTER ENABLE: USB0_EN Mask    */
-#define EVENTROUTER_ENABLE_USB1_EN_Pos                        10                                                        /*!< EVENTROUTER ENABLE: USB1_EN Position */
-#define EVENTROUTER_ENABLE_USB1_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos)                /*!< EVENTROUTER ENABLE: USB1_EN Mask    */
-#define EVENTROUTER_ENABLE_SDMMC_EN_Pos                       11                                                        /*!< EVENTROUTER ENABLE: SDMMC_EN Position */
-#define EVENTROUTER_ENABLE_SDMMC_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos)               /*!< EVENTROUTER ENABLE: SDMMC_EN Mask   */
-#define EVENTROUTER_ENABLE_CAN_EN_Pos                         12                                                        /*!< EVENTROUTER ENABLE: CAN_EN Position */
-#define EVENTROUTER_ENABLE_CAN_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos)                 /*!< EVENTROUTER ENABLE: CAN_EN Mask     */
-#define EVENTROUTER_ENABLE_TIM2_EN_Pos                        13                                                        /*!< EVENTROUTER ENABLE: TIM2_EN Position */
-#define EVENTROUTER_ENABLE_TIM2_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos)                /*!< EVENTROUTER ENABLE: TIM2_EN Mask    */
-#define EVENTROUTER_ENABLE_TIM6_EN_Pos                        14                                                        /*!< EVENTROUTER ENABLE: TIM6_EN Position */
-#define EVENTROUTER_ENABLE_TIM6_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos)                /*!< EVENTROUTER ENABLE: TIM6_EN Mask    */
-#define EVENTROUTER_ENABLE_QEI_EN_Pos                         15                                                        /*!< EVENTROUTER ENABLE: QEI_EN Position */
-#define EVENTROUTER_ENABLE_QEI_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos)                 /*!< EVENTROUTER ENABLE: QEI_EN Mask     */
-#define EVENTROUTER_ENABLE_TIM14_EN_Pos                       16                                                        /*!< EVENTROUTER ENABLE: TIM14_EN Position */
-#define EVENTROUTER_ENABLE_TIM14_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos)               /*!< EVENTROUTER ENABLE: TIM14_EN Mask   */
-#define EVENTROUTER_ENABLE_RESET_EN_Pos                       19                                                        /*!< EVENTROUTER ENABLE: RESET_EN Position */
-#define EVENTROUTER_ENABLE_RESET_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos)               /*!< EVENTROUTER ENABLE: RESET_EN Mask   */
-
-// ----------------------------------  EVENTROUTER_CLR_STAT  --------------------------------------
-#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos                0                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */
-#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos                1                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */
-#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos                2                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */
-#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos                3                                                         /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */
-#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos)        /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos                 4                                                         /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */
-#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk                 (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos)         /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos                    5                                                         /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */
-#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos                    6                                                         /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */
-#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos                   7                                                         /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */
-#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos                    8                                                         /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */
-#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos                   9                                                         /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */
-#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos                   10                                                        /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */
-#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos                  11                                                        /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */
-#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos                    12                                                        /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */
-#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos                   13                                                        /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */
-#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos                   14                                                        /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */
-#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos)           /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos                    15                                                        /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */
-#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos)            /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos                  16                                                        /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */
-#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */
-#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos                  19                                                        /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */
-#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos)          /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */
-
-// ----------------------------------  EVENTROUTER_SET_STAT  --------------------------------------
-#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos                0                                                         /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */
-#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */
-#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos                1                                                         /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */
-#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */
-#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos                2                                                         /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */
-#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */
-#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos                3                                                         /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */
-#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos)        /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */
-#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos                 4                                                         /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */
-#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk                 (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos)         /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */
-#define EVENTROUTER_SET_STAT_RTC_SETST_Pos                    5                                                         /*!< EVENTROUTER SET_STAT: RTC_SETST Position */
-#define EVENTROUTER_SET_STAT_RTC_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos)            /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */
-#define EVENTROUTER_SET_STAT_BOD_SETST_Pos                    6                                                         /*!< EVENTROUTER SET_STAT: BOD_SETST Position */
-#define EVENTROUTER_SET_STAT_BOD_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos)            /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */
-#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos                   7                                                         /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */
-#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos)           /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */
-#define EVENTROUTER_SET_STAT_ETH_SETST_Pos                    8                                                         /*!< EVENTROUTER SET_STAT: ETH_SETST Position */
-#define EVENTROUTER_SET_STAT_ETH_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos)            /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */
-#define EVENTROUTER_SET_STAT_USB0_SETST_Pos                   9                                                         /*!< EVENTROUTER SET_STAT: USB0_SETST Position */
-#define EVENTROUTER_SET_STAT_USB0_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos)           /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */
-#define EVENTROUTER_SET_STAT_USB1_SETST_Pos                   10                                                        /*!< EVENTROUTER SET_STAT: USB1_SETST Position */
-#define EVENTROUTER_SET_STAT_USB1_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos)           /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */
-#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos                  11                                                        /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */
-#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos)          /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */
-#define EVENTROUTER_SET_STAT_CAN_SETST_Pos                    12                                                        /*!< EVENTROUTER SET_STAT: CAN_SETST Position */
-#define EVENTROUTER_SET_STAT_CAN_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos)            /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */
-#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos                   13                                                        /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */
-#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos)           /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */
-#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos                   14                                                        /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */
-#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos)           /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */
-#define EVENTROUTER_SET_STAT_QEI_SETST_Pos                    15                                                        /*!< EVENTROUTER SET_STAT: QEI_SETST Position */
-#define EVENTROUTER_SET_STAT_QEI_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos)            /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */
-#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos                  16                                                        /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */
-#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos)          /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */
-#define EVENTROUTER_SET_STAT_RESET_SETST_Pos                  19                                                        /*!< EVENTROUTER SET_STAT: RESET_SETST Position */
-#define EVENTROUTER_SET_STAT_RESET_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos)          /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  RTC Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------------  RTC_ILR  --------------------------------------------
-#define RTC_ILR_RTCCIF_Pos                                    0                                                         /*!< RTC ILR: RTCCIF Position            */
-#define RTC_ILR_RTCCIF_Msk                                    (0x01UL << RTC_ILR_RTCCIF_Pos)                            /*!< RTC ILR: RTCCIF Mask                */
-#define RTC_ILR_RTCALF_Pos                                    1                                                         /*!< RTC ILR: RTCALF Position            */
-#define RTC_ILR_RTCALF_Msk                                    (0x01UL << RTC_ILR_RTCALF_Pos)                            /*!< RTC ILR: RTCALF Mask                */
-
-// -----------------------------------------  RTC_CCR  --------------------------------------------
-#define RTC_CCR_CLKEN_Pos                                     0                                                         /*!< RTC CCR: CLKEN Position             */
-#define RTC_CCR_CLKEN_Msk                                     (0x01UL << RTC_CCR_CLKEN_Pos)                             /*!< RTC CCR: CLKEN Mask                 */
-#define RTC_CCR_CTCRST_Pos                                    1                                                         /*!< RTC CCR: CTCRST Position            */
-#define RTC_CCR_CTCRST_Msk                                    (0x01UL << RTC_CCR_CTCRST_Pos)                            /*!< RTC CCR: CTCRST Mask                */
-#define RTC_CCR_CCALEN_Pos                                    4                                                         /*!< RTC CCR: CCALEN Position            */
-#define RTC_CCR_CCALEN_Msk                                    (0x01UL << RTC_CCR_CCALEN_Pos)                            /*!< RTC CCR: CCALEN Mask                */
-
-// ----------------------------------------  RTC_CIIR  --------------------------------------------
-#define RTC_CIIR_IMSEC_Pos                                    0                                                         /*!< RTC CIIR: IMSEC Position            */
-#define RTC_CIIR_IMSEC_Msk                                    (0x01UL << RTC_CIIR_IMSEC_Pos)                            /*!< RTC CIIR: IMSEC Mask                */
-#define RTC_CIIR_IMMIN_Pos                                    1                                                         /*!< RTC CIIR: IMMIN Position            */
-#define RTC_CIIR_IMMIN_Msk                                    (0x01UL << RTC_CIIR_IMMIN_Pos)                            /*!< RTC CIIR: IMMIN Mask                */
-#define RTC_CIIR_IMHOUR_Pos                                   2                                                         /*!< RTC CIIR: IMHOUR Position           */
-#define RTC_CIIR_IMHOUR_Msk                                   (0x01UL << RTC_CIIR_IMHOUR_Pos)                           /*!< RTC CIIR: IMHOUR Mask               */
-#define RTC_CIIR_IMDOM_Pos                                    3                                                         /*!< RTC CIIR: IMDOM Position            */
-#define RTC_CIIR_IMDOM_Msk                                    (0x01UL << RTC_CIIR_IMDOM_Pos)                            /*!< RTC CIIR: IMDOM Mask                */
-#define RTC_CIIR_IMDOW_Pos                                    4                                                         /*!< RTC CIIR: IMDOW Position            */
-#define RTC_CIIR_IMDOW_Msk                                    (0x01UL << RTC_CIIR_IMDOW_Pos)                            /*!< RTC CIIR: IMDOW Mask                */
-#define RTC_CIIR_IMDOY_Pos                                    5                                                         /*!< RTC CIIR: IMDOY Position            */
-#define RTC_CIIR_IMDOY_Msk                                    (0x01UL << RTC_CIIR_IMDOY_Pos)                            /*!< RTC CIIR: IMDOY Mask                */
-#define RTC_CIIR_IMMON_Pos                                    6                                                         /*!< RTC CIIR: IMMON Position            */
-#define RTC_CIIR_IMMON_Msk                                    (0x01UL << RTC_CIIR_IMMON_Pos)                            /*!< RTC CIIR: IMMON Mask                */
-#define RTC_CIIR_IMYEAR_Pos                                   7                                                         /*!< RTC CIIR: IMYEAR Position           */
-#define RTC_CIIR_IMYEAR_Msk                                   (0x01UL << RTC_CIIR_IMYEAR_Pos)                           /*!< RTC CIIR: IMYEAR Mask               */
-
-// -----------------------------------------  RTC_AMR  --------------------------------------------
-#define RTC_AMR_AMRSEC_Pos                                    0                                                         /*!< RTC AMR: AMRSEC Position            */
-#define RTC_AMR_AMRSEC_Msk                                    (0x01UL << RTC_AMR_AMRSEC_Pos)                            /*!< RTC AMR: AMRSEC Mask                */
-#define RTC_AMR_AMRMIN_Pos                                    1                                                         /*!< RTC AMR: AMRMIN Position            */
-#define RTC_AMR_AMRMIN_Msk                                    (0x01UL << RTC_AMR_AMRMIN_Pos)                            /*!< RTC AMR: AMRMIN Mask                */
-#define RTC_AMR_AMRHOUR_Pos                                   2                                                         /*!< RTC AMR: AMRHOUR Position           */
-#define RTC_AMR_AMRHOUR_Msk                                   (0x01UL << RTC_AMR_AMRHOUR_Pos)                           /*!< RTC AMR: AMRHOUR Mask               */
-#define RTC_AMR_AMRDOM_Pos                                    3                                                         /*!< RTC AMR: AMRDOM Position            */
-#define RTC_AMR_AMRDOM_Msk                                    (0x01UL << RTC_AMR_AMRDOM_Pos)                            /*!< RTC AMR: AMRDOM Mask                */
-#define RTC_AMR_AMRDOW_Pos                                    4                                                         /*!< RTC AMR: AMRDOW Position            */
-#define RTC_AMR_AMRDOW_Msk                                    (0x01UL << RTC_AMR_AMRDOW_Pos)                            /*!< RTC AMR: AMRDOW Mask                */
-#define RTC_AMR_AMRDOY_Pos                                    5                                                         /*!< RTC AMR: AMRDOY Position            */
-#define RTC_AMR_AMRDOY_Msk                                    (0x01UL << RTC_AMR_AMRDOY_Pos)                            /*!< RTC AMR: AMRDOY Mask                */
-#define RTC_AMR_AMRMON_Pos                                    6                                                         /*!< RTC AMR: AMRMON Position            */
-#define RTC_AMR_AMRMON_Msk                                    (0x01UL << RTC_AMR_AMRMON_Pos)                            /*!< RTC AMR: AMRMON Mask                */
-#define RTC_AMR_AMRYEAR_Pos                                   7                                                         /*!< RTC AMR: AMRYEAR Position           */
-#define RTC_AMR_AMRYEAR_Msk                                   (0x01UL << RTC_AMR_AMRYEAR_Pos)                           /*!< RTC AMR: AMRYEAR Mask               */
-
-// ---------------------------------------  RTC_CTIME0  -------------------------------------------
-#define RTC_CTIME0_SECONDS_Pos                                0                                                         /*!< RTC CTIME0: SECONDS Position        */
-#define RTC_CTIME0_SECONDS_Msk                                (0x3fUL << RTC_CTIME0_SECONDS_Pos)                        /*!< RTC CTIME0: SECONDS Mask            */
-#define RTC_CTIME0_MINUTES_Pos                                8                                                         /*!< RTC CTIME0: MINUTES Position        */
-#define RTC_CTIME0_MINUTES_Msk                                (0x3fUL << RTC_CTIME0_MINUTES_Pos)                        /*!< RTC CTIME0: MINUTES Mask            */
-#define RTC_CTIME0_HOURS_Pos                                  16                                                        /*!< RTC CTIME0: HOURS Position          */
-#define RTC_CTIME0_HOURS_Msk                                  (0x1fUL << RTC_CTIME0_HOURS_Pos)                          /*!< RTC CTIME0: HOURS Mask              */
-#define RTC_CTIME0_DOW_Pos                                    24                                                        /*!< RTC CTIME0: DOW Position            */
-#define RTC_CTIME0_DOW_Msk                                    (0x07UL << RTC_CTIME0_DOW_Pos)                            /*!< RTC CTIME0: DOW Mask                */
-
-// ---------------------------------------  RTC_CTIME1  -------------------------------------------
-#define RTC_CTIME1_DOM_Pos                                    0                                                         /*!< RTC CTIME1: DOM Position            */
-#define RTC_CTIME1_DOM_Msk                                    (0x1fUL << RTC_CTIME1_DOM_Pos)                            /*!< RTC CTIME1: DOM Mask                */
-#define RTC_CTIME1_MONTH_Pos                                  8                                                         /*!< RTC CTIME1: MONTH Position          */
-#define RTC_CTIME1_MONTH_Msk                                  (0x0fUL << RTC_CTIME1_MONTH_Pos)                          /*!< RTC CTIME1: MONTH Mask              */
-#define RTC_CTIME1_YEAR_Pos                                   16                                                        /*!< RTC CTIME1: YEAR Position           */
-#define RTC_CTIME1_YEAR_Msk                                   (0x00000fffUL << RTC_CTIME1_YEAR_Pos)                     /*!< RTC CTIME1: YEAR Mask               */
-
-// ---------------------------------------  RTC_CTIME2  -------------------------------------------
-#define RTC_CTIME2_DOY_Pos                                    0                                                         /*!< RTC CTIME2: DOY Position            */
-#define RTC_CTIME2_DOY_Msk                                    (0x00000fffUL << RTC_CTIME2_DOY_Pos)                      /*!< RTC CTIME2: DOY Mask                */
-
-// -----------------------------------------  RTC_SEC  --------------------------------------------
-#define RTC_SEC_SECONDS_Pos                                   0                                                         /*!< RTC SEC: SECONDS Position           */
-#define RTC_SEC_SECONDS_Msk                                   (0x3fUL << RTC_SEC_SECONDS_Pos)                           /*!< RTC SEC: SECONDS Mask               */
-
-// -----------------------------------------  RTC_MIN  --------------------------------------------
-#define RTC_MIN_MINUTES_Pos                                   0                                                         /*!< RTC MIN: MINUTES Position           */
-#define RTC_MIN_MINUTES_Msk                                   (0x3fUL << RTC_MIN_MINUTES_Pos)                           /*!< RTC MIN: MINUTES Mask               */
-
-// -----------------------------------------  RTC_HRS  --------------------------------------------
-#define RTC_HRS_HOURS_Pos                                     0                                                         /*!< RTC HRS: HOURS Position             */
-#define RTC_HRS_HOURS_Msk                                     (0x1fUL << RTC_HRS_HOURS_Pos)                             /*!< RTC HRS: HOURS Mask                 */
-
-// -----------------------------------------  RTC_DOM  --------------------------------------------
-#define RTC_DOM_DOM_Pos                                       0                                                         /*!< RTC DOM: DOM Position               */
-#define RTC_DOM_DOM_Msk                                       (0x1fUL << RTC_DOM_DOM_Pos)                               /*!< RTC DOM: DOM Mask                   */
-
-// -----------------------------------------  RTC_DOW  --------------------------------------------
-#define RTC_DOW_DOW_Pos                                       0                                                         /*!< RTC DOW: DOW Position               */
-#define RTC_DOW_DOW_Msk                                       (0x07UL << RTC_DOW_DOW_Pos)                               /*!< RTC DOW: DOW Mask                   */
-
-// -----------------------------------------  RTC_DOY  --------------------------------------------
-#define RTC_DOY_DOY_Pos                                       0                                                         /*!< RTC DOY: DOY Position               */
-#define RTC_DOY_DOY_Msk                                       (0x000001ffUL << RTC_DOY_DOY_Pos)                         /*!< RTC DOY: DOY Mask                   */
-
-// ----------------------------------------  RTC_MONTH  -------------------------------------------
-#define RTC_MONTH_MONTH_Pos                                   0                                                         /*!< RTC MONTH: MONTH Position           */
-#define RTC_MONTH_MONTH_Msk                                   (0x0fUL << RTC_MONTH_MONTH_Pos)                           /*!< RTC MONTH: MONTH Mask               */
-
-// ----------------------------------------  RTC_YEAR  --------------------------------------------
-#define RTC_YEAR_YEAR_Pos                                     0                                                         /*!< RTC YEAR: YEAR Position             */
-#define RTC_YEAR_YEAR_Msk                                     (0x00000fffUL << RTC_YEAR_YEAR_Pos)                       /*!< RTC YEAR: YEAR Mask                 */
-
-// -------------------------------------  RTC_CALIBRATION  ----------------------------------------
-#define RTC_CALIBRATION_CALVAL_Pos                            0                                                         /*!< RTC CALIBRATION: CALVAL Position    */
-#define RTC_CALIBRATION_CALVAL_Msk                            (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos)              /*!< RTC CALIBRATION: CALVAL Mask        */
-#define RTC_CALIBRATION_CALDIR_Pos                            17                                                        /*!< RTC CALIBRATION: CALDIR Position    */
-#define RTC_CALIBRATION_CALDIR_Msk                            (0x01UL << RTC_CALIBRATION_CALDIR_Pos)                    /*!< RTC CALIBRATION: CALDIR Mask        */
-
-// ----------------------------------------  RTC_ASEC  --------------------------------------------
-#define RTC_ASEC_SECONDS_Pos                                  0                                                         /*!< RTC ASEC: SECONDS Position          */
-#define RTC_ASEC_SECONDS_Msk                                  (0x3fUL << RTC_ASEC_SECONDS_Pos)                          /*!< RTC ASEC: SECONDS Mask              */
-
-// ----------------------------------------  RTC_AMIN  --------------------------------------------
-#define RTC_AMIN_MINUTES_Pos                                  0                                                         /*!< RTC AMIN: MINUTES Position          */
-#define RTC_AMIN_MINUTES_Msk                                  (0x3fUL << RTC_AMIN_MINUTES_Pos)                          /*!< RTC AMIN: MINUTES Mask              */
-
-// ----------------------------------------  RTC_AHRS  --------------------------------------------
-#define RTC_AHRS_HOURS_Pos                                    0                                                         /*!< RTC AHRS: HOURS Position            */
-#define RTC_AHRS_HOURS_Msk                                    (0x1fUL << RTC_AHRS_HOURS_Pos)                            /*!< RTC AHRS: HOURS Mask                */
-
-// ----------------------------------------  RTC_ADOM  --------------------------------------------
-#define RTC_ADOM_DOM_Pos                                      0                                                         /*!< RTC ADOM: DOM Position              */
-#define RTC_ADOM_DOM_Msk                                      (0x1fUL << RTC_ADOM_DOM_Pos)                              /*!< RTC ADOM: DOM Mask                  */
-
-// ----------------------------------------  RTC_ADOW  --------------------------------------------
-#define RTC_ADOW_DOW_Pos                                      0                                                         /*!< RTC ADOW: DOW Position              */
-#define RTC_ADOW_DOW_Msk                                      (0x07UL << RTC_ADOW_DOW_Pos)                              /*!< RTC ADOW: DOW Mask                  */
-
-// ----------------------------------------  RTC_ADOY  --------------------------------------------
-#define RTC_ADOY_DOY_Pos                                      0                                                         /*!< RTC ADOY: DOY Position              */
-#define RTC_ADOY_DOY_Msk                                      (0x000001ffUL << RTC_ADOY_DOY_Pos)                        /*!< RTC ADOY: DOY Mask                  */
-
-// ----------------------------------------  RTC_AMON  --------------------------------------------
-#define RTC_AMON_MONTH_Pos                                    0                                                         /*!< RTC AMON: MONTH Position            */
-#define RTC_AMON_MONTH_Msk                                    (0x0fUL << RTC_AMON_MONTH_Pos)                            /*!< RTC AMON: MONTH Mask                */
-
-// ----------------------------------------  RTC_AYRS  --------------------------------------------
-#define RTC_AYRS_YEAR_Pos                                     0                                                         /*!< RTC AYRS: YEAR Position             */
-#define RTC_AYRS_YEAR_Msk                                     (0x00000fffUL << RTC_AYRS_YEAR_Pos)                       /*!< RTC AYRS: YEAR Mask                 */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  CGU Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// --------------------------------------  CGU_FREQ_MON  ------------------------------------------
-#define CGU_FREQ_MON_RCNT_Pos                                 0                                                         /*!< CGU FREQ_MON: RCNT Position         */
-#define CGU_FREQ_MON_RCNT_Msk                                 (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos)                   /*!< CGU FREQ_MON: RCNT Mask             */
-#define CGU_FREQ_MON_FCNT_Pos                                 9                                                         /*!< CGU FREQ_MON: FCNT Position         */
-#define CGU_FREQ_MON_FCNT_Msk                                 (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos)                   /*!< CGU FREQ_MON: FCNT Mask             */
-#define CGU_FREQ_MON_MEAS_Pos                                 23                                                        /*!< CGU FREQ_MON: MEAS Position         */
-#define CGU_FREQ_MON_MEAS_Msk                                 (0x01UL << CGU_FREQ_MON_MEAS_Pos)                         /*!< CGU FREQ_MON: MEAS Mask             */
-#define CGU_FREQ_MON_CLK_SEL_Pos                              24                                                        /*!< CGU FREQ_MON: CLK_SEL Position      */
-#define CGU_FREQ_MON_CLK_SEL_Msk                              (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos)                      /*!< CGU FREQ_MON: CLK_SEL Mask          */
-
-// ------------------------------------  CGU_XTAL_OSC_CTRL  ---------------------------------------
-#define CGU_XTAL_OSC_CTRL_ENABLE_Pos                          0                                                         /*!< CGU XTAL_OSC_CTRL: ENABLE Position  */
-#define CGU_XTAL_OSC_CTRL_ENABLE_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos)                  /*!< CGU XTAL_OSC_CTRL: ENABLE Mask      */
-#define CGU_XTAL_OSC_CTRL_BYPASS_Pos                          1                                                         /*!< CGU XTAL_OSC_CTRL: BYPASS Position  */
-#define CGU_XTAL_OSC_CTRL_BYPASS_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos)                  /*!< CGU XTAL_OSC_CTRL: BYPASS Mask      */
-#define CGU_XTAL_OSC_CTRL_HF_Pos                              2                                                         /*!< CGU XTAL_OSC_CTRL: HF Position      */
-#define CGU_XTAL_OSC_CTRL_HF_Msk                              (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos)                      /*!< CGU XTAL_OSC_CTRL: HF Mask          */
-
-// ------------------------------------  CGU_PLL0USB_STAT  ----------------------------------------
-#define CGU_PLL0USB_STAT_LOCK_Pos                             0                                                         /*!< CGU PLL0USB_STAT: LOCK Position     */
-#define CGU_PLL0USB_STAT_LOCK_Msk                             (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos)                     /*!< CGU PLL0USB_STAT: LOCK Mask         */
-#define CGU_PLL0USB_STAT_FR_Pos                               1                                                         /*!< CGU PLL0USB_STAT: FR Position       */
-#define CGU_PLL0USB_STAT_FR_Msk                               (0x01UL << CGU_PLL0USB_STAT_FR_Pos)                       /*!< CGU PLL0USB_STAT: FR Mask           */
-
-// ------------------------------------  CGU_PLL0USB_CTRL  ----------------------------------------
-#define CGU_PLL0USB_CTRL_PD_Pos                               0                                                         /*!< CGU PLL0USB_CTRL: PD Position       */
-#define CGU_PLL0USB_CTRL_PD_Msk                               (0x01UL << CGU_PLL0USB_CTRL_PD_Pos)                       /*!< CGU PLL0USB_CTRL: PD Mask           */
-#define CGU_PLL0USB_CTRL_BYPASS_Pos                           1                                                         /*!< CGU PLL0USB_CTRL: BYPASS Position   */
-#define CGU_PLL0USB_CTRL_BYPASS_Msk                           (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos)                   /*!< CGU PLL0USB_CTRL: BYPASS Mask       */
-#define CGU_PLL0USB_CTRL_DIRECTI_Pos                          2                                                         /*!< CGU PLL0USB_CTRL: DIRECTI Position  */
-#define CGU_PLL0USB_CTRL_DIRECTI_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos)                  /*!< CGU PLL0USB_CTRL: DIRECTI Mask      */
-#define CGU_PLL0USB_CTRL_DIRECTO_Pos                          3                                                         /*!< CGU PLL0USB_CTRL: DIRECTO Position  */
-#define CGU_PLL0USB_CTRL_DIRECTO_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos)                  /*!< CGU PLL0USB_CTRL: DIRECTO Mask      */
-#define CGU_PLL0USB_CTRL_CLKEN_Pos                            4                                                         /*!< CGU PLL0USB_CTRL: CLKEN Position    */
-#define CGU_PLL0USB_CTRL_CLKEN_Msk                            (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos)                    /*!< CGU PLL0USB_CTRL: CLKEN Mask        */
-#define CGU_PLL0USB_CTRL_FRM_Pos                              6                                                         /*!< CGU PLL0USB_CTRL: FRM Position      */
-#define CGU_PLL0USB_CTRL_FRM_Msk                              (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos)                      /*!< CGU PLL0USB_CTRL: FRM Mask          */
-#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos                        11                                                        /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */
-#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk                        (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos)                /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask    */
-#define CGU_PLL0USB_CTRL_CLK_SEL_Pos                          24                                                        /*!< CGU PLL0USB_CTRL: CLK_SEL Position  */
-#define CGU_PLL0USB_CTRL_CLK_SEL_Msk                          (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos)                  /*!< CGU PLL0USB_CTRL: CLK_SEL Mask      */
-
-// ------------------------------------  CGU_PLL0USB_MDIV  ----------------------------------------
-#define CGU_PLL0USB_MDIV_MDEC_Pos                             0                                                         /*!< CGU PLL0USB_MDIV: MDEC Position     */
-#define CGU_PLL0USB_MDIV_MDEC_Msk                             (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos)               /*!< CGU PLL0USB_MDIV: MDEC Mask         */
-#define CGU_PLL0USB_MDIV_SELP_Pos                             17                                                        /*!< CGU PLL0USB_MDIV: SELP Position     */
-#define CGU_PLL0USB_MDIV_SELP_Msk                             (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos)                     /*!< CGU PLL0USB_MDIV: SELP Mask         */
-#define CGU_PLL0USB_MDIV_SELI_Pos                             22                                                        /*!< CGU PLL0USB_MDIV: SELI Position     */
-#define CGU_PLL0USB_MDIV_SELI_Msk                             (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos)                     /*!< CGU PLL0USB_MDIV: SELI Mask         */
-#define CGU_PLL0USB_MDIV_SELR_Pos                             28                                                        /*!< CGU PLL0USB_MDIV: SELR Position     */
-#define CGU_PLL0USB_MDIV_SELR_Msk                             (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos)                     /*!< CGU PLL0USB_MDIV: SELR Mask         */
-
-// -----------------------------------  CGU_PLL0USB_NP_DIV  ---------------------------------------
-#define CGU_PLL0USB_NP_DIV_PDEC_Pos                           0                                                         /*!< CGU PLL0USB_NP_DIV: PDEC Position   */
-#define CGU_PLL0USB_NP_DIV_PDEC_Msk                           (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos)                   /*!< CGU PLL0USB_NP_DIV: PDEC Mask       */
-#define CGU_PLL0USB_NP_DIV_NDEC_Pos                           12                                                        /*!< CGU PLL0USB_NP_DIV: NDEC Position   */
-#define CGU_PLL0USB_NP_DIV_NDEC_Msk                           (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos)             /*!< CGU PLL0USB_NP_DIV: NDEC Mask       */
-
-// -----------------------------------  CGU_PLL0AUDIO_STAT  ---------------------------------------
-#define CGU_PLL0AUDIO_STAT_LOCK_Pos                           0                                                         /*!< CGU PLL0AUDIO_STAT: LOCK Position   */
-#define CGU_PLL0AUDIO_STAT_LOCK_Msk                           (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos)                   /*!< CGU PLL0AUDIO_STAT: LOCK Mask       */
-#define CGU_PLL0AUDIO_STAT_FR_Pos                             1                                                         /*!< CGU PLL0AUDIO_STAT: FR Position     */
-#define CGU_PLL0AUDIO_STAT_FR_Msk                             (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos)                     /*!< CGU PLL0AUDIO_STAT: FR Mask         */
-
-// -----------------------------------  CGU_PLL0AUDIO_CTRL  ---------------------------------------
-#define CGU_PLL0AUDIO_CTRL_PD_Pos                             0                                                         /*!< CGU PLL0AUDIO_CTRL: PD Position     */
-#define CGU_PLL0AUDIO_CTRL_PD_Msk                             (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos)                     /*!< CGU PLL0AUDIO_CTRL: PD Mask         */
-#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos                         1                                                         /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */
-#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos)                 /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask     */
-#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos                        2                                                         /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */
-#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos)                /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask    */
-#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos                        3                                                         /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */
-#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos)                /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask    */
-#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos                          4                                                         /*!< CGU PLL0AUDIO_CTRL: CLKEN Position  */
-#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk                          (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos)                  /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask      */
-#define CGU_PLL0AUDIO_CTRL_FRM_Pos                            6                                                         /*!< CGU PLL0AUDIO_CTRL: FRM Position    */
-#define CGU_PLL0AUDIO_CTRL_FRM_Msk                            (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos)                    /*!< CGU PLL0AUDIO_CTRL: FRM Mask        */
-#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos                      11                                                        /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */
-#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk                      (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos)              /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask  */
-#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos                    12                                                        /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Position */
-#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk                    (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos)            /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Mask */
-#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos                        13                                                        /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */
-#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos)                /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask    */
-#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos                         14                                                        /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */
-#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos)                 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask     */
-#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos                        24                                                        /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */
-#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk                        (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos)                /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask    */
-
-// -----------------------------------  CGU_PLL0AUDIO_MDIV  ---------------------------------------
-#define CGU_PLL0AUDIO_MDIV_MDEC_Pos                           0                                                         /*!< CGU PLL0AUDIO_MDIV: MDEC Position   */
-#define CGU_PLL0AUDIO_MDIV_MDEC_Msk                           (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos)             /*!< CGU PLL0AUDIO_MDIV: MDEC Mask       */
-
-// ----------------------------------  CGU_PLL0AUDIO_NP_DIV  --------------------------------------
-#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos                         0                                                         /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */
-#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk                         (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos)                 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask     */
-#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos                         12                                                        /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */
-#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk                         (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos)           /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask     */
-
-// -----------------------------------  CGU_PLL0AUDIO_FRAC  ---------------------------------------
-#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos                  0                                                         /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */
-#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk                  (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos)    /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */
-
-// --------------------------------------  CGU_PLL1_STAT  -----------------------------------------
-#define CGU_PLL1_STAT_LOCK_Pos                                0                                                         /*!< CGU PLL1_STAT: LOCK Position        */
-#define CGU_PLL1_STAT_LOCK_Msk                                (0x01UL << CGU_PLL1_STAT_LOCK_Pos)                        /*!< CGU PLL1_STAT: LOCK Mask            */
-
-// --------------------------------------  CGU_PLL1_CTRL  -----------------------------------------
-#define CGU_PLL1_CTRL_PD_Pos                                  0                                                         /*!< CGU PLL1_CTRL: PD Position          */
-#define CGU_PLL1_CTRL_PD_Msk                                  (0x01UL << CGU_PLL1_CTRL_PD_Pos)                          /*!< CGU PLL1_CTRL: PD Mask              */
-#define CGU_PLL1_CTRL_BYPASS_Pos                              1                                                         /*!< CGU PLL1_CTRL: BYPASS Position      */
-#define CGU_PLL1_CTRL_BYPASS_Msk                              (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos)                      /*!< CGU PLL1_CTRL: BYPASS Mask          */
-#define CGU_PLL1_CTRL_FBSEL_Pos                               6                                                         /*!< CGU PLL1_CTRL: FBSEL Position       */
-#define CGU_PLL1_CTRL_FBSEL_Msk                               (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos)                       /*!< CGU PLL1_CTRL: FBSEL Mask           */
-#define CGU_PLL1_CTRL_DIRECT_Pos                              7                                                         /*!< CGU PLL1_CTRL: DIRECT Position      */
-#define CGU_PLL1_CTRL_DIRECT_Msk                              (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos)                      /*!< CGU PLL1_CTRL: DIRECT Mask          */
-#define CGU_PLL1_CTRL_PSEL_Pos                                8                                                         /*!< CGU PLL1_CTRL: PSEL Position        */
-#define CGU_PLL1_CTRL_PSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_PSEL_Pos)                        /*!< CGU PLL1_CTRL: PSEL Mask            */
-#define CGU_PLL1_CTRL_AUTOBLOCK_Pos                           11                                                        /*!< CGU PLL1_CTRL: AUTOBLOCK Position   */
-#define CGU_PLL1_CTRL_AUTOBLOCK_Msk                           (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos)                   /*!< CGU PLL1_CTRL: AUTOBLOCK Mask       */
-#define CGU_PLL1_CTRL_NSEL_Pos                                12                                                        /*!< CGU PLL1_CTRL: NSEL Position        */
-#define CGU_PLL1_CTRL_NSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_NSEL_Pos)                        /*!< CGU PLL1_CTRL: NSEL Mask            */
-#define CGU_PLL1_CTRL_MSEL_Pos                                16                                                        /*!< CGU PLL1_CTRL: MSEL Position        */
-#define CGU_PLL1_CTRL_MSEL_Msk                                (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos)                  /*!< CGU PLL1_CTRL: MSEL Mask            */
-#define CGU_PLL1_CTRL_CLK_SEL_Pos                             24                                                        /*!< CGU PLL1_CTRL: CLK_SEL Position     */
-#define CGU_PLL1_CTRL_CLK_SEL_Msk                             (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos)                     /*!< CGU PLL1_CTRL: CLK_SEL Mask         */
-
-// -------------------------------------  CGU_IDIVA_CTRL  -----------------------------------------
-#define CGU_IDIVA_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVA_CTRL: PD Position         */
-#define CGU_IDIVA_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVA_CTRL_PD_Pos)                         /*!< CGU IDIVA_CTRL: PD Mask             */
-#define CGU_IDIVA_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVA_CTRL: IDIV Position       */
-#define CGU_IDIVA_CTRL_IDIV_Msk                               (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos)                       /*!< CGU IDIVA_CTRL: IDIV Mask           */
-#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVA_CTRL: AUTOBLOCK Position  */
-#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask      */
-#define CGU_IDIVA_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVA_CTRL: CLK_SEL Position    */
-#define CGU_IDIVA_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVA_CTRL: CLK_SEL Mask        */
-
-// -------------------------------------  CGU_IDIVB_CTRL  -----------------------------------------
-#define CGU_IDIVB_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVB_CTRL: PD Position         */
-#define CGU_IDIVB_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVB_CTRL_PD_Pos)                         /*!< CGU IDIVB_CTRL: PD Mask             */
-#define CGU_IDIVB_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVB_CTRL: IDIV Position       */
-#define CGU_IDIVB_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos)                       /*!< CGU IDIVB_CTRL: IDIV Mask           */
-#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVB_CTRL: AUTOBLOCK Position  */
-#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask      */
-#define CGU_IDIVB_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVB_CTRL: CLK_SEL Position    */
-#define CGU_IDIVB_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVB_CTRL: CLK_SEL Mask        */
-
-// -------------------------------------  CGU_IDIVE_CTRL  -----------------------------------------
-#define CGU_IDIVE_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVE_CTRL: PD Position         */
-#define CGU_IDIVE_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVE_CTRL_PD_Pos)                         /*!< CGU IDIVE_CTRL: PD Mask             */
-#define CGU_IDIVE_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVE_CTRL: IDIV Position       */
-#define CGU_IDIVE_CTRL_IDIV_Msk                               (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos)                 /*!< CGU IDIVE_CTRL: IDIV Mask           */
-#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVE_CTRL: AUTOBLOCK Position  */
-#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask      */
-#define CGU_IDIVE_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVE_CTRL: CLK_SEL Position    */
-#define CGU_IDIVE_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVE_CTRL: CLK_SEL Mask        */
-
-// ------------------------------------  CGU_BASE_SAFE_CLK  ---------------------------------------
-#define CGU_BASE_SAFE_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SAFE_CLK: PD Position      */
-#define CGU_BASE_SAFE_CLK_PD_Msk                              (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos)                      /*!< CGU BASE_SAFE_CLK: PD Mask          */
-#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */
-#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask   */
-#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */
-#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask     */
-
-// ------------------------------------  CGU_BASE_USB0_CLK  ---------------------------------------
-#define CGU_BASE_USB0_CLK_PD_Pos                              0                                                         /*!< CGU BASE_USB0_CLK: PD Position      */
-#define CGU_BASE_USB0_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB0_CLK_PD_Pos)                      /*!< CGU BASE_USB0_CLK: PD Mask          */
-#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */
-#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask   */
-#define CGU_BASE_USB0_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_USB0_CLK: CLK_SEL Position */
-#define CGU_BASE_USB0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_USB0_CLK: CLK_SEL Mask     */
-
-// -----------------------------------  CGU_BASE_PERIPH_CLK  --------------------------------------
-#define CGU_BASE_PERIPH_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PERIPH_CLK: PD Position    */
-#define CGU_BASE_PERIPH_CLK_PD_Msk                            (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos)                    /*!< CGU BASE_PERIPH_CLK: PD Mask        */
-#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */
-#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */
-#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */
-#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask   */
-
-// ------------------------------------  CGU_BASE_USB1_CLK  ---------------------------------------
-#define CGU_BASE_USB1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_USB1_CLK: PD Position      */
-#define CGU_BASE_USB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB1_CLK_PD_Pos)                      /*!< CGU BASE_USB1_CLK: PD Mask          */
-#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */
-#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask   */
-#define CGU_BASE_USB1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_USB1_CLK: CLK_SEL Position */
-#define CGU_BASE_USB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_USB1_CLK: CLK_SEL Mask     */
-
-// -------------------------------------  CGU_BASE_M4_CLK  ----------------------------------------
-#define CGU_BASE_M4_CLK_PD_Pos                                0                                                         /*!< CGU BASE_M4_CLK: PD Position        */
-#define CGU_BASE_M4_CLK_PD_Msk                                (0x01UL << CGU_BASE_M4_CLK_PD_Pos)                        /*!< CGU BASE_M4_CLK: PD Mask            */
-#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos                         11                                                        /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */
-#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk                         (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos)                 /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask     */
-#define CGU_BASE_M4_CLK_CLK_SEL_Pos                           24                                                        /*!< CGU BASE_M4_CLK: CLK_SEL Position   */
-#define CGU_BASE_M4_CLK_CLK_SEL_Msk                           (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos)                   /*!< CGU BASE_M4_CLK: CLK_SEL Mask       */
-
-// -----------------------------------  CGU_BASE_SPIFI_CLK  ---------------------------------------
-#define CGU_BASE_SPIFI_CLK_PD_Pos                             0                                                         /*!< CGU BASE_SPIFI_CLK: PD Position     */
-#define CGU_BASE_SPIFI_CLK_PD_Msk                             (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos)                     /*!< CGU BASE_SPIFI_CLK: PD Mask         */
-#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */
-#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask  */
-#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */
-#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos)                /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask    */
-
-// ------------------------------------  CGU_BASE_SPI_CLK  ----------------------------------------
-#define CGU_BASE_SPI_CLK_PD_Pos                               0                                                         /*!< CGU BASE_SPI_CLK: PD Position       */
-#define CGU_BASE_SPI_CLK_PD_Msk                               (0x01UL << CGU_BASE_SPI_CLK_PD_Pos)                       /*!< CGU BASE_SPI_CLK: PD Mask           */
-#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */
-#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask    */
-#define CGU_BASE_SPI_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_SPI_CLK: CLK_SEL Position  */
-#define CGU_BASE_SPI_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_SPI_CLK: CLK_SEL Mask      */
-
-// -----------------------------------  CGU_BASE_PHY_RX_CLK  --------------------------------------
-#define CGU_BASE_PHY_RX_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PHY_RX_CLK: PD Position    */
-#define CGU_BASE_PHY_RX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos)                    /*!< CGU BASE_PHY_RX_CLK: PD Mask        */
-#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */
-#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */
-#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */
-#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask   */
-
-// -----------------------------------  CGU_BASE_PHY_TX_CLK  --------------------------------------
-#define CGU_BASE_PHY_TX_CLK_PD_Pos                            0                                                         /*!< CGU BASE_PHY_TX_CLK: PD Position    */
-#define CGU_BASE_PHY_TX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos)                    /*!< CGU BASE_PHY_TX_CLK: PD Mask        */
-#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos                     11                                                        /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */
-#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos)             /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */
-#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos                       24                                                        /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */
-#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos)               /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask   */
-
-// ------------------------------------  CGU_BASE_APB1_CLK  ---------------------------------------
-#define CGU_BASE_APB1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APB1_CLK: PD Position      */
-#define CGU_BASE_APB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB1_CLK_PD_Pos)                      /*!< CGU BASE_APB1_CLK: PD Mask          */
-#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */
-#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask   */
-#define CGU_BASE_APB1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APB1_CLK: CLK_SEL Position */
-#define CGU_BASE_APB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APB1_CLK: CLK_SEL Mask     */
-
-// ------------------------------------  CGU_BASE_APB3_CLK  ---------------------------------------
-#define CGU_BASE_APB3_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APB3_CLK: PD Position      */
-#define CGU_BASE_APB3_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB3_CLK_PD_Pos)                      /*!< CGU BASE_APB3_CLK: PD Mask          */
-#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */
-#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask   */
-#define CGU_BASE_APB3_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APB3_CLK: CLK_SEL Position */
-#define CGU_BASE_APB3_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APB3_CLK: CLK_SEL Mask     */
-
-// ------------------------------------  CGU_BASE_LCD_CLK  ----------------------------------------
-#define CGU_BASE_LCD_CLK_PD_Pos                               0                                                         /*!< CGU BASE_LCD_CLK: PD Position       */
-#define CGU_BASE_LCD_CLK_PD_Msk                               (0x01UL << CGU_BASE_LCD_CLK_PD_Pos)                       /*!< CGU BASE_LCD_CLK: PD Mask           */
-#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */
-#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask    */
-#define CGU_BASE_LCD_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_LCD_CLK: CLK_SEL Position  */
-#define CGU_BASE_LCD_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_LCD_CLK: CLK_SEL Mask      */
-
-// ------------------------------------  CGU_BASE_SDIO_CLK  ---------------------------------------
-#define CGU_BASE_SDIO_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SDIO_CLK: PD Position      */
-#define CGU_BASE_SDIO_CLK_PD_Msk                              (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos)                      /*!< CGU BASE_SDIO_CLK: PD Mask          */
-#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */
-#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask   */
-#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */
-#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask     */
-
-// ------------------------------------  CGU_BASE_SSP0_CLK  ---------------------------------------
-#define CGU_BASE_SSP0_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SSP0_CLK: PD Position      */
-#define CGU_BASE_SSP0_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos)                      /*!< CGU BASE_SSP0_CLK: PD Mask          */
-#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */
-#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask   */
-#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */
-#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask     */
-
-// ------------------------------------  CGU_BASE_SSP1_CLK  ---------------------------------------
-#define CGU_BASE_SSP1_CLK_PD_Pos                              0                                                         /*!< CGU BASE_SSP1_CLK: PD Position      */
-#define CGU_BASE_SSP1_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos)                      /*!< CGU BASE_SSP1_CLK: PD Mask          */
-#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */
-#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask   */
-#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */
-#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask     */
-
-// -----------------------------------  CGU_BASE_UART0_CLK  ---------------------------------------
-#define CGU_BASE_UART0_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART0_CLK: PD Position     */
-#define CGU_BASE_UART0_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART0_CLK_PD_Pos)                     /*!< CGU BASE_UART0_CLK: PD Mask         */
-#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */
-#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask  */
-#define CGU_BASE_UART0_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART0_CLK: CLK_SEL Position */
-#define CGU_BASE_UART0_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART0_CLK: CLK_SEL Mask    */
-
-// -----------------------------------  CGU_BASE_UART1_CLK  ---------------------------------------
-#define CGU_BASE_UART1_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART1_CLK: PD Position     */
-#define CGU_BASE_UART1_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART1_CLK_PD_Pos)                     /*!< CGU BASE_UART1_CLK: PD Mask         */
-#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */
-#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask  */
-#define CGU_BASE_UART1_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART1_CLK: CLK_SEL Position */
-#define CGU_BASE_UART1_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART1_CLK: CLK_SEL Mask    */
-
-// -----------------------------------  CGU_BASE_UART2_CLK  ---------------------------------------
-#define CGU_BASE_UART2_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART2_CLK: PD Position     */
-#define CGU_BASE_UART2_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART2_CLK_PD_Pos)                     /*!< CGU BASE_UART2_CLK: PD Mask         */
-#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */
-#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask  */
-#define CGU_BASE_UART2_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART2_CLK: CLK_SEL Position */
-#define CGU_BASE_UART2_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART2_CLK: CLK_SEL Mask    */
-
-// -----------------------------------  CGU_BASE_UART3_CLK  ---------------------------------------
-#define CGU_BASE_UART3_CLK_PD_Pos                             0                                                         /*!< CGU BASE_UART3_CLK: PD Position     */
-#define CGU_BASE_UART3_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART3_CLK_PD_Pos)                     /*!< CGU BASE_UART3_CLK: PD Mask         */
-#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos                      11                                                        /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */
-#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos)              /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask  */
-#define CGU_BASE_UART3_CLK_CLK_SEL_Pos                        24                                                        /*!< CGU BASE_UART3_CLK: CLK_SEL Position */
-#define CGU_BASE_UART3_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos)                /*!< CGU BASE_UART3_CLK: CLK_SEL Mask    */
-
-// ------------------------------------  CGU_BASE_OUT_CLK  ----------------------------------------
-#define CGU_BASE_OUT_CLK_PD_Pos                               0                                                         /*!< CGU BASE_OUT_CLK: PD Position       */
-#define CGU_BASE_OUT_CLK_PD_Msk                               (0x01UL << CGU_BASE_OUT_CLK_PD_Pos)                       /*!< CGU BASE_OUT_CLK: PD Mask           */
-#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos                        11                                                        /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */
-#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos)                /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask    */
-#define CGU_BASE_OUT_CLK_CLK_SEL_Pos                          24                                                        /*!< CGU BASE_OUT_CLK: CLK_SEL Position  */
-#define CGU_BASE_OUT_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos)                  /*!< CGU BASE_OUT_CLK: CLK_SEL Mask      */
-
-// ------------------------------------  CGU_BASE_APLL_CLK  ---------------------------------------
-#define CGU_BASE_APLL_CLK_PD_Pos                              0                                                         /*!< CGU BASE_APLL_CLK: PD Position      */
-#define CGU_BASE_APLL_CLK_PD_Msk                              (0x01UL << CGU_BASE_APLL_CLK_PD_Pos)                      /*!< CGU BASE_APLL_CLK: PD Mask          */
-#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos                       11                                                        /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */
-#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos)               /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask   */
-#define CGU_BASE_APLL_CLK_CLK_SEL_Pos                         24                                                        /*!< CGU BASE_APLL_CLK: CLK_SEL Position */
-#define CGU_BASE_APLL_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos)                 /*!< CGU BASE_APLL_CLK: CLK_SEL Mask     */
-
-// ----------------------------------  CGU_BASE_CGU_OUT0_CLK  -------------------------------------
-#define CGU_BASE_CGU_OUT0_CLK_PD_Pos                          0                                                         /*!< CGU BASE_CGU_OUT0_CLK: PD Position  */
-#define CGU_BASE_CGU_OUT0_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos)                  /*!< CGU BASE_CGU_OUT0_CLK: PD Mask      */
-#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos                   11                                                        /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */
-#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos)           /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */
-#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos                     24                                                        /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */
-#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos)             /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */
-
-// ----------------------------------  CGU_BASE_CGU_OUT1_CLK  -------------------------------------
-#define CGU_BASE_CGU_OUT1_CLK_PD_Pos                          0                                                         /*!< CGU BASE_CGU_OUT1_CLK: PD Position  */
-#define CGU_BASE_CGU_OUT1_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos)                  /*!< CGU BASE_CGU_OUT1_CLK: PD Mask      */
-#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos                   11                                                        /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */
-#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos)           /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */
-#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos                     24                                                        /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */
-#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos)             /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */
-
-// -------------------------------------  CGU_IDIVC_CTRL  -----------------------------------------
-#define CGU_IDIVC_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVC_CTRL: PD Position         */
-#define CGU_IDIVC_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVC_CTRL_PD_Pos)                         /*!< CGU IDIVC_CTRL: PD Mask             */
-#define CGU_IDIVC_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVC_CTRL: IDIV Position       */
-#define CGU_IDIVC_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos)                       /*!< CGU IDIVC_CTRL: IDIV Mask           */
-#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVC_CTRL: AUTOBLOCK Position  */
-#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask      */
-#define CGU_IDIVC_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVC_CTRL: CLK_SEL Position    */
-#define CGU_IDIVC_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVC_CTRL: CLK_SEL Mask        */
-
-// -------------------------------------  CGU_IDIVD_CTRL  -----------------------------------------
-#define CGU_IDIVD_CTRL_PD_Pos                                 0                                                         /*!< CGU IDIVD_CTRL: PD Position         */
-#define CGU_IDIVD_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVD_CTRL_PD_Pos)                         /*!< CGU IDIVD_CTRL: PD Mask             */
-#define CGU_IDIVD_CTRL_IDIV_Pos                               2                                                         /*!< CGU IDIVD_CTRL: IDIV Position       */
-#define CGU_IDIVD_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos)                       /*!< CGU IDIVD_CTRL: IDIV Mask           */
-#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos                          11                                                        /*!< CGU IDIVD_CTRL: AUTOBLOCK Position  */
-#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos)                  /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask      */
-#define CGU_IDIVD_CTRL_CLK_SEL_Pos                            24                                                        /*!< CGU IDIVD_CTRL: CLK_SEL Position    */
-#define CGU_IDIVD_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos)                    /*!< CGU IDIVD_CTRL: CLK_SEL Mask        */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 CCU1 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------------  CCU1_PM  --------------------------------------------
-#define CCU1_PM_PD_Pos                                        0                                                         /*!< CCU1 PM: PD Position                */
-#define CCU1_PM_PD_Msk                                        (0x01UL << CCU1_PM_PD_Pos)                                /*!< CCU1 PM: PD Mask                    */
-
-// -------------------------------------  CCU1_BASE_STAT  -----------------------------------------
-#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos                  0                                                         /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */
-#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */
-#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos                  1                                                         /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */
-#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */
-#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos                 2                                                         /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */
-#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk                 (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos)         /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */
-#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos                    3                                                         /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */
-#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk                    (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos)            /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */
-#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos                  7                                                         /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */
-#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */
-#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos                  8                                                         /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */
-#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos)          /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */
-
-// ----------------------------------  CCU1_CLK_APB3_BUS_CFG  -------------------------------------
-#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */
-#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask     */
-#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */
-#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask    */
-#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */
-#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_APB3_BUS_STAT  -------------------------------------
-#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */
-#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos)                /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask    */
-#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */
-#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask   */
-#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */
-#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB3_I2C1_CFG  -------------------------------------
-#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */
-#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask    */
-#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */
-#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask   */
-#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */
-#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB3_I2C1_STAT  ------------------------------------
-#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */
-#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask   */
-#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */
-#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask  */
-#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */
-#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_APB3_DAC_CFG  -------------------------------------
-#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */
-#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask     */
-#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */
-#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask    */
-#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */
-#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_APB3_DAC_STAT  -------------------------------------
-#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */
-#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos)                /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask    */
-#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */
-#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask   */
-#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */
-#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB3_ADC0_CFG  -------------------------------------
-#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */
-#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask    */
-#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */
-#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask   */
-#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */
-#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB3_ADC0_STAT  ------------------------------------
-#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */
-#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask   */
-#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */
-#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask  */
-#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */
-#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB3_ADC1_CFG  -------------------------------------
-#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */
-#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask    */
-#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */
-#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask   */
-#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */
-#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB3_ADC1_STAT  ------------------------------------
-#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */
-#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask   */
-#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */
-#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask  */
-#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */
-#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB3_CAN0_CFG  -------------------------------------
-#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */
-#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos)                /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask    */
-#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */
-#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask   */
-#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */
-#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB3_CAN0_STAT  ------------------------------------
-#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */
-#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask   */
-#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */
-#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask  */
-#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */
-#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_APB1_BUS_CFG  -------------------------------------
-#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */
-#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask     */
-#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */
-#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask    */
-#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */
-#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_APB1_BUS_STAT  -------------------------------------
-#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */
-#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos)                /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask    */
-#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */
-#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask   */
-#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */
-#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */
-
-// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_CFG  ----------------------------------
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos                  0                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk                  (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos)          /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos                 1                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos)         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos               2                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk               (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos)       /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */
-
-// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_STAT  ---------------------------------
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos                 0                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos)         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos                1                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk                (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos)        /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos              2                                                         /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk              (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos)      /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_ABP1_I2C0_CFG  -------------------------------------
-#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Position */
-#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos)                /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Mask    */
-#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Position */
-#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos)               /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Mask   */
-#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Position */
-#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB1_I2C0_STAT  ------------------------------------
-#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */
-#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos)               /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask   */
-#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */
-#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask  */
-#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */
-#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_APB1_I2S_CFG  -------------------------------------
-#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */
-#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos)                 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask     */
-#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */
-#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos)                /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask    */
-#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */
-#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_APB1_I2S_STAT  -------------------------------------
-#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */
-#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos)                /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask    */
-#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */
-#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos)               /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask   */
-#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */
-#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB1_CAN1_CFG  -------------------------------------
-#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */
-#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos)                /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask    */
-#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */
-#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos)               /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask   */
-#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */
-#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_APB1_CAN1_STAT  ------------------------------------
-#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */
-#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos)               /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask   */
-#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */
-#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos)              /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask  */
-#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */
-#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */
-
-// -----------------------------------  CCU1_CLK_SPIFI_CFG  ---------------------------------------
-#define CCU1_CLK_SPIFI_CFG_RUN_Pos                            0                                                         /*!< CCU1 CLK_SPIFI_CFG: RUN Position    */
-#define CCU1_CLK_SPIFI_CFG_RUN_Msk                            (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos)                    /*!< CCU1 CLK_SPIFI_CFG: RUN Mask        */
-#define CCU1_CLK_SPIFI_CFG_AUTO_Pos                           1                                                         /*!< CCU1 CLK_SPIFI_CFG: AUTO Position   */
-#define CCU1_CLK_SPIFI_CFG_AUTO_Msk                           (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos)                   /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask       */
-#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */
-#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk                         (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos)                 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask     */
-
-// -----------------------------------  CCU1_CLK_SPIFI_STAT  --------------------------------------
-#define CCU1_CLK_SPIFI_STAT_RUN_Pos                           0                                                         /*!< CCU1 CLK_SPIFI_STAT: RUN Position   */
-#define CCU1_CLK_SPIFI_STAT_RUN_Msk                           (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos)                   /*!< CCU1 CLK_SPIFI_STAT: RUN Mask       */
-#define CCU1_CLK_SPIFI_STAT_AUTO_Pos                          1                                                         /*!< CCU1 CLK_SPIFI_STAT: AUTO Position  */
-#define CCU1_CLK_SPIFI_STAT_AUTO_Msk                          (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos)                  /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask      */
-#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */
-#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk                        (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos)                /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask    */
-
-// -----------------------------------  CCU1_CLK_M4_BUS_CFG  --------------------------------------
-#define CCU1_CLK_M4_BUS_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_BUS_CFG: RUN Position   */
-#define CCU1_CLK_M4_BUS_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_BUS_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_BUS_CFG: RUN Mask       */
-#define CCU1_CLK_M4_BUS_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_BUS_CFG: AUTO Position  */
-#define CCU1_CLK_M4_BUS_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_BUS_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_BUS_CFG: AUTO Mask      */
-#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Mask    */
-
-// ----------------------------------  CCU1_CLK_M4_BUS_STAT  --------------------------------------
-#define CCU1_CLK_M4_BUS_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_BUS_STAT: RUN Position  */
-#define CCU1_CLK_M4_BUS_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_BUS_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_BUS_STAT: RUN Mask      */
-#define CCU1_CLK_M4_BUS_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_BUS_STAT: AUTO Position */
-#define CCU1_CLK_M4_BUS_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_BUS_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_BUS_STAT: AUTO Mask     */
-#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_SPIFI_CFG  -------------------------------------
-#define CCU1_CLK_M4_SPIFI_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Position */
-#define CCU1_CLK_M4_SPIFI_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SPIFI_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Mask     */
-#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Position */
-#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Mask    */
-#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_M4_SPIFI_STAT  -------------------------------------
-#define CCU1_CLK_M4_SPIFI_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Position */
-#define CCU1_CLK_M4_SPIFI_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Mask    */
-#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Position */
-#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Mask   */
-#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_M4_GPIO_CFG  --------------------------------------
-#define CCU1_CLK_M4_GPIO_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_GPIO_CFG: RUN Position  */
-#define CCU1_CLK_M4_GPIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_GPIO_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_GPIO_CFG: RUN Mask      */
-#define CCU1_CLK_M4_GPIO_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Position */
-#define CCU1_CLK_M4_GPIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Mask     */
-#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_GPIO_STAT  -------------------------------------
-#define CCU1_CLK_M4_GPIO_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_GPIO_STAT: RUN Position */
-#define CCU1_CLK_M4_GPIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_GPIO_STAT: RUN Mask     */
-#define CCU1_CLK_M4_GPIO_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Position */
-#define CCU1_CLK_M4_GPIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_GPIO_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Mask    */
-#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Mask  */
-
-// -----------------------------------  CCU1_CLK_M4_LCD_CFG  --------------------------------------
-#define CCU1_CLK_M4_LCD_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_LCD_CFG: RUN Position   */
-#define CCU1_CLK_M4_LCD_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_LCD_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_LCD_CFG: RUN Mask       */
-#define CCU1_CLK_M4_LCD_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_LCD_CFG: AUTO Position  */
-#define CCU1_CLK_M4_LCD_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_LCD_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_LCD_CFG: AUTO Mask      */
-#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Mask    */
-
-// ----------------------------------  CCU1_CLK_M4_LCD_STAT  --------------------------------------
-#define CCU1_CLK_M4_LCD_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_LCD_STAT: RUN Position  */
-#define CCU1_CLK_M4_LCD_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_LCD_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_LCD_STAT: RUN Mask      */
-#define CCU1_CLK_M4_LCD_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_LCD_STAT: AUTO Position */
-#define CCU1_CLK_M4_LCD_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_LCD_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_LCD_STAT: AUTO Mask     */
-#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Mask   */
-
-// --------------------------------  CCU1_CLK_M4_ETHERNET_CFG  ------------------------------------
-#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos                      0                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Position */
-#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos)              /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Mask  */
-#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos                     1                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Position */
-#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos)             /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Mask */
-#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos)           /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Mask */
-
-// --------------------------------  CCU1_CLK_M4_ETHERNET_STAT  -----------------------------------
-#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos                     0                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Position */
-#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos)             /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Mask */
-#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos                    1                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Position */
-#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos)            /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Mask */
-#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos)          /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_M4_USB0_CFG  --------------------------------------
-#define CCU1_CLK_M4_USB0_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_USB0_CFG: RUN Position  */
-#define CCU1_CLK_M4_USB0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB0_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_USB0_CFG: RUN Mask      */
-#define CCU1_CLK_M4_USB0_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_USB0_CFG: AUTO Position */
-#define CCU1_CLK_M4_USB0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB0_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_USB0_CFG: AUTO Mask     */
-#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_USB0_STAT  -------------------------------------
-#define CCU1_CLK_M4_USB0_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_USB0_STAT: RUN Position */
-#define CCU1_CLK_M4_USB0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB0_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_USB0_STAT: RUN Mask     */
-#define CCU1_CLK_M4_USB0_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_USB0_STAT: AUTO Position */
-#define CCU1_CLK_M4_USB0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB0_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_USB0_STAT: AUTO Mask    */
-#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Mask  */
-
-// -----------------------------------  CCU1_CLK_M4_EMC_CFG  --------------------------------------
-#define CCU1_CLK_M4_EMC_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_EMC_CFG: RUN Position   */
-#define CCU1_CLK_M4_EMC_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_EMC_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_EMC_CFG: RUN Mask       */
-#define CCU1_CLK_M4_EMC_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_EMC_CFG: AUTO Position  */
-#define CCU1_CLK_M4_EMC_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_EMC_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_EMC_CFG: AUTO Mask      */
-#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Mask    */
-
-// ----------------------------------  CCU1_CLK_M4_EMC_STAT  --------------------------------------
-#define CCU1_CLK_M4_EMC_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_EMC_STAT: RUN Position  */
-#define CCU1_CLK_M4_EMC_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_EMC_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_EMC_STAT: RUN Mask      */
-#define CCU1_CLK_M4_EMC_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_EMC_STAT: AUTO Position */
-#define CCU1_CLK_M4_EMC_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_EMC_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_EMC_STAT: AUTO Mask     */
-#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_SDIO_CFG  --------------------------------------
-#define CCU1_CLK_M4_SDIO_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SDIO_CFG: RUN Position  */
-#define CCU1_CLK_M4_SDIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SDIO_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SDIO_CFG: RUN Mask      */
-#define CCU1_CLK_M4_SDIO_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Position */
-#define CCU1_CLK_M4_SDIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Mask     */
-#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_SDIO_STAT  -------------------------------------
-#define CCU1_CLK_M4_SDIO_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SDIO_STAT: RUN Position */
-#define CCU1_CLK_M4_SDIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SDIO_STAT: RUN Mask     */
-#define CCU1_CLK_M4_SDIO_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Position */
-#define CCU1_CLK_M4_SDIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SDIO_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Mask    */
-#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Mask  */
-
-// -----------------------------------  CCU1_CLK_M4_DMA_CFG  --------------------------------------
-#define CCU1_CLK_M4_DMA_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_DMA_CFG: RUN Position   */
-#define CCU1_CLK_M4_DMA_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_DMA_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_DMA_CFG: RUN Mask       */
-#define CCU1_CLK_M4_DMA_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_DMA_CFG: AUTO Position  */
-#define CCU1_CLK_M4_DMA_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_DMA_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_DMA_CFG: AUTO Mask      */
-#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Mask    */
-
-// ----------------------------------  CCU1_CLK_M4_DMA_STAT  --------------------------------------
-#define CCU1_CLK_M4_DMA_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_DMA_STAT: RUN Position  */
-#define CCU1_CLK_M4_DMA_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_DMA_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_DMA_STAT: RUN Mask      */
-#define CCU1_CLK_M4_DMA_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_DMA_STAT: AUTO Position */
-#define CCU1_CLK_M4_DMA_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_DMA_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_DMA_STAT: AUTO Mask     */
-#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Mask   */
-
-// ---------------------------------  CCU1_CLK_M4_M4CORE_CFG  -------------------------------------
-#define CCU1_CLK_M4_M4CORE_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Position */
-#define CCU1_CLK_M4_M4CORE_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M4CORE_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Mask    */
-#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Position */
-#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Mask   */
-#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_M3CORE_STAT  ------------------------------------
-#define CCU1_CLK_M4_M3CORE_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Position */
-#define CCU1_CLK_M4_M3CORE_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_M3CORE_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Mask   */
-#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Position */
-#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Mask  */
-#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Mask */
-
-// -----------------------------------  CCU1_CLK_M4_SCT_CFG  --------------------------------------
-#define CCU1_CLK_M4_SCT_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_SCT_CFG: RUN Position   */
-#define CCU1_CLK_M4_SCT_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCT_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_SCT_CFG: RUN Mask       */
-#define CCU1_CLK_M4_SCT_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_SCT_CFG: AUTO Position  */
-#define CCU1_CLK_M4_SCT_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCT_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_SCT_CFG: AUTO Mask      */
-#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Mask    */
-
-// ----------------------------------  CCU1_CLK_M4_SCT_STAT  --------------------------------------
-#define CCU1_CLK_M4_SCT_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SCT_STAT: RUN Position  */
-#define CCU1_CLK_M4_SCT_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCT_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_SCT_STAT: RUN Mask      */
-#define CCU1_CLK_M4_SCT_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SCT_STAT: AUTO Position */
-#define CCU1_CLK_M4_SCT_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCT_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_SCT_STAT: AUTO Mask     */
-#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_USB1_CFG  --------------------------------------
-#define CCU1_CLK_M4_USB1_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_USB1_CFG: RUN Position  */
-#define CCU1_CLK_M4_USB1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB1_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_USB1_CFG: RUN Mask      */
-#define CCU1_CLK_M4_USB1_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_USB1_CFG: AUTO Position */
-#define CCU1_CLK_M4_USB1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB1_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_USB1_CFG: AUTO Mask     */
-#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_USB1_STAT  -------------------------------------
-#define CCU1_CLK_M4_USB1_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_USB1_STAT: RUN Position */
-#define CCU1_CLK_M4_USB1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB1_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_USB1_STAT: RUN Mask     */
-#define CCU1_CLK_M4_USB1_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_USB1_STAT: AUTO Position */
-#define CCU1_CLK_M4_USB1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB1_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_USB1_STAT: AUTO Mask    */
-#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_M4_EMCDIV_CFG  -------------------------------------
-#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Position */
-#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Mask    */
-#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Position */
-#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Mask   */
-#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_EMCDIV_STAT  ------------------------------------
-#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Position */
-#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Mask   */
-#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Position */
-#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Mask  */
-#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_M4_M0APP_CFG  -------------------------------------
-#define CCU1_CLK_M4_M0APP_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_M0APP_CFG: RUN Position */
-#define CCU1_CLK_M4_M0APP_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_M0APP_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_M0APP_CFG: RUN Mask     */
-#define CCU1_CLK_M4_M0APP_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Position */
-#define CCU1_CLK_M4_M0APP_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Mask    */
-#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_M4_M0APP_STAT  -------------------------------------
-#define CCU1_CLK_M4_M0APP_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_M0APP_STAT: RUN Position */
-#define CCU1_CLK_M4_M0APP_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_M0APP_STAT: RUN Mask    */
-#define CCU1_CLK_M4_M0APP_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Position */
-#define CCU1_CLK_M4_M0APP_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M0APP_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Mask   */
-#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_M4_WWDT_CFG  --------------------------------------
-#define CCU1_CLK_M4_WWDT_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_WWDT_CFG: RUN Position  */
-#define CCU1_CLK_M4_WWDT_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_WWDT_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_WWDT_CFG: RUN Mask      */
-#define CCU1_CLK_M4_WWDT_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Position */
-#define CCU1_CLK_M4_WWDT_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Mask     */
-#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_WWDT_STAT  -------------------------------------
-#define CCU1_CLK_M4_WWDT_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_WWDT_STAT: RUN Position */
-#define CCU1_CLK_M4_WWDT_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_WWDT_STAT: RUN Mask     */
-#define CCU1_CLK_M4_WWDT_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Position */
-#define CCU1_CLK_M4_WWDT_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_WWDT_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Mask    */
-#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_M4_USART0_CFG  -------------------------------------
-#define CCU1_CLK_M4_USART0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART0_CFG: RUN Position */
-#define CCU1_CLK_M4_USART0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART0_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART0_CFG: RUN Mask    */
-#define CCU1_CLK_M4_USART0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART0_CFG: AUTO Position */
-#define CCU1_CLK_M4_USART0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART0_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART0_CFG: AUTO Mask   */
-#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_USART0_STAT  ------------------------------------
-#define CCU1_CLK_M4_USART0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART0_STAT: RUN Position */
-#define CCU1_CLK_M4_USART0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART0_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART0_STAT: RUN Mask   */
-#define CCU1_CLK_M4_USART0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART0_STAT: AUTO Position */
-#define CCU1_CLK_M4_USART0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART0_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART0_STAT: AUTO Mask  */
-#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_M4_UART1_CFG  -------------------------------------
-#define CCU1_CLK_M4_UART1_CFG_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_UART1_CFG: RUN Position */
-#define CCU1_CLK_M4_UART1_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_UART1_CFG_RUN_Pos)                 /*!< CCU1 CLK_M4_UART1_CFG: RUN Mask     */
-#define CCU1_CLK_M4_UART1_CFG_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_UART1_CFG: AUTO Position */
-#define CCU1_CLK_M4_UART1_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_UART1_CFG_AUTO_Pos)                /*!< CCU1 CLK_M4_UART1_CFG: AUTO Mask    */
-#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos)              /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_M4_UART1_STAT  -------------------------------------
-#define CCU1_CLK_M4_UART1_STAT_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_UART1_STAT: RUN Position */
-#define CCU1_CLK_M4_UART1_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_UART1_STAT_RUN_Pos)                /*!< CCU1 CLK_M4_UART1_STAT: RUN Mask    */
-#define CCU1_CLK_M4_UART1_STAT_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_UART1_STAT: AUTO Position */
-#define CCU1_CLK_M4_UART1_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_UART1_STAT_AUTO_Pos)               /*!< CCU1 CLK_M4_UART1_STAT: AUTO Mask   */
-#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos)             /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_M4_SSP0_CFG  --------------------------------------
-#define CCU1_CLK_M4_SSP0_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SSP0_CFG: RUN Position  */
-#define CCU1_CLK_M4_SSP0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP0_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SSP0_CFG: RUN Mask      */
-#define CCU1_CLK_M4_SSP0_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Position */
-#define CCU1_CLK_M4_SSP0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Mask     */
-#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_SSP0_STAT  -------------------------------------
-#define CCU1_CLK_M4_SSP0_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SSP0_STAT: RUN Position */
-#define CCU1_CLK_M4_SSP0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SSP0_STAT: RUN Mask     */
-#define CCU1_CLK_M4_SSP0_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Position */
-#define CCU1_CLK_M4_SSP0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP0_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Mask    */
-#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_M4_TIMER0_CFG  -------------------------------------
-#define CCU1_CLK_M4_TIMER0_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Position */
-#define CCU1_CLK_M4_TIMER0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER0_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Mask    */
-#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Position */
-#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Mask   */
-#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_TIMER0_STAT  ------------------------------------
-#define CCU1_CLK_M4_TIMER0_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Position */
-#define CCU1_CLK_M4_TIMER0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Mask   */
-#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Position */
-#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Mask  */
-#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_TIMER1_CFG  -------------------------------------
-#define CCU1_CLK_M4_TIMER1_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Position */
-#define CCU1_CLK_M4_TIMER1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER1_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Mask    */
-#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Position */
-#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Mask   */
-#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_TIMER1_STAT  ------------------------------------
-#define CCU1_CLK_M4_TIMER1_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Position */
-#define CCU1_CLK_M4_TIMER1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Mask   */
-#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Position */
-#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Mask  */
-#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Mask */
-
-// -----------------------------------  CCU1_CLK_M4_SCU_CFG  --------------------------------------
-#define CCU1_CLK_M4_SCU_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_SCU_CFG: RUN Position   */
-#define CCU1_CLK_M4_SCU_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCU_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_SCU_CFG: RUN Mask       */
-#define CCU1_CLK_M4_SCU_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_SCU_CFG: AUTO Position  */
-#define CCU1_CLK_M4_SCU_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCU_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_SCU_CFG: AUTO Mask      */
-#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Mask    */
-
-// ----------------------------------  CCU1_CLK_M4_SCU_STAT  --------------------------------------
-#define CCU1_CLK_M4_SCU_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SCU_STAT: RUN Position  */
-#define CCU1_CLK_M4_SCU_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCU_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_SCU_STAT: RUN Mask      */
-#define CCU1_CLK_M4_SCU_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SCU_STAT: AUTO Position */
-#define CCU1_CLK_M4_SCU_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCU_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_SCU_STAT: AUTO Mask     */
-#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_CREG_CFG  --------------------------------------
-#define CCU1_CLK_M4_CREG_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_CREG_CFG: RUN Position  */
-#define CCU1_CLK_M4_CREG_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_CREG_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_CREG_CFG: RUN Mask      */
-#define CCU1_CLK_M4_CREG_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_CREG_CFG: AUTO Position */
-#define CCU1_CLK_M4_CREG_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_CREG_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_CREG_CFG: AUTO Mask     */
-#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_CREG_STAT  -------------------------------------
-#define CCU1_CLK_M4_CREG_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_CREG_STAT: RUN Position */
-#define CCU1_CLK_M4_CREG_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_CREG_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_CREG_STAT: RUN Mask     */
-#define CCU1_CLK_M4_CREG_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_CREG_STAT: AUTO Position */
-#define CCU1_CLK_M4_CREG_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_CREG_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_CREG_STAT: AUTO Mask    */
-#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Mask  */
-
-// ---------------------------------  CCU1_CLK_M4_RITIMER_CFG  ------------------------------------
-#define CCU1_CLK_M4_RITIMER_CFG_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Position */
-#define CCU1_CLK_M4_RITIMER_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_M4_RITIMER_CFG_RUN_Pos)               /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Mask   */
-#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Position */
-#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos)              /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Mask  */
-#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos)            /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Mask */
-
-// --------------------------------  CCU1_CLK_M4_RITIMER_STAT  ------------------------------------
-#define CCU1_CLK_M4_RITIMER_STAT_RUN_Pos                      0                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Position */
-#define CCU1_CLK_M4_RITIMER_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_STAT_RUN_Pos)              /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Mask  */
-#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos                     1                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Position */
-#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos)             /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Mask */
-#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos)           /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_USART2_CFG  -------------------------------------
-#define CCU1_CLK_M4_USART2_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART2_CFG: RUN Position */
-#define CCU1_CLK_M4_USART2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART2_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART2_CFG: RUN Mask    */
-#define CCU1_CLK_M4_USART2_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART2_CFG: AUTO Position */
-#define CCU1_CLK_M4_USART2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART2_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART2_CFG: AUTO Mask   */
-#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_USART2_STAT  ------------------------------------
-#define CCU1_CLK_M4_USART2_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART2_STAT: RUN Position */
-#define CCU1_CLK_M4_USART2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART2_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART2_STAT: RUN Mask   */
-#define CCU1_CLK_M4_USART2_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART2_STAT: AUTO Position */
-#define CCU1_CLK_M4_USART2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART2_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART2_STAT: AUTO Mask  */
-#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_USART3_CFG  -------------------------------------
-#define CCU1_CLK_M4_USART3_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_USART3_CFG: RUN Position */
-#define CCU1_CLK_M4_USART3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART3_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_USART3_CFG: RUN Mask    */
-#define CCU1_CLK_M4_USART3_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_USART3_CFG: AUTO Position */
-#define CCU1_CLK_M4_USART3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART3_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_USART3_CFG: AUTO Mask   */
-#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_USART3_STAT  ------------------------------------
-#define CCU1_CLK_M4_USART3_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_USART3_STAT: RUN Position */
-#define CCU1_CLK_M4_USART3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART3_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_USART3_STAT: RUN Mask   */
-#define CCU1_CLK_M4_USART3_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_USART3_STAT: AUTO Position */
-#define CCU1_CLK_M4_USART3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART3_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_USART3_STAT: AUTO Mask  */
-#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_TIMER2_CFG  -------------------------------------
-#define CCU1_CLK_M4_TIMER2_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Position */
-#define CCU1_CLK_M4_TIMER2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER2_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Mask    */
-#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Position */
-#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Mask   */
-#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_TIMER2_STAT  ------------------------------------
-#define CCU1_CLK_M4_TIMER2_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Position */
-#define CCU1_CLK_M4_TIMER2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Mask   */
-#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Position */
-#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Mask  */
-#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_TIMER3_CFG  -------------------------------------
-#define CCU1_CLK_M4_TIMER3_CFG_RUN_Pos                        0                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Position */
-#define CCU1_CLK_M4_TIMER3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER3_CFG_RUN_Pos)                /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Mask    */
-#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos                       1                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Position */
-#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos)               /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Mask   */
-#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos                     2                                                         /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos)             /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU1_CLK_M4_TIMER3_STAT  ------------------------------------
-#define CCU1_CLK_M4_TIMER3_STAT_RUN_Pos                       0                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Position */
-#define CCU1_CLK_M4_TIMER3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_STAT_RUN_Pos)               /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Mask   */
-#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos                      1                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Position */
-#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos)              /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Mask  */
-#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos)            /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Mask */
-
-// ----------------------------------  CCU1_CLK_M4_SSP1_CFG  --------------------------------------
-#define CCU1_CLK_M4_SSP1_CFG_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_SSP1_CFG: RUN Position  */
-#define CCU1_CLK_M4_SSP1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP1_CFG_RUN_Pos)                  /*!< CCU1 CLK_M4_SSP1_CFG: RUN Mask      */
-#define CCU1_CLK_M4_SSP1_CFG_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Position */
-#define CCU1_CLK_M4_SSP1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_CFG_AUTO_Pos)                 /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Mask     */
-#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos)               /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Mask   */
-
-// ----------------------------------  CCU1_CLK_M4_SSP1_STAT  -------------------------------------
-#define CCU1_CLK_M4_SSP1_STAT_RUN_Pos                         0                                                         /*!< CCU1 CLK_M4_SSP1_STAT: RUN Position */
-#define CCU1_CLK_M4_SSP1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_STAT_RUN_Pos)                 /*!< CCU1 CLK_M4_SSP1_STAT: RUN Mask     */
-#define CCU1_CLK_M4_SSP1_STAT_AUTO_Pos                        1                                                         /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Position */
-#define CCU1_CLK_M4_SSP1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP1_STAT_AUTO_Pos)                /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Mask    */
-#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos                      2                                                         /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos)              /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Mask  */
-
-// -----------------------------------  CCU1_CLK_M4_QEI_CFG  --------------------------------------
-#define CCU1_CLK_M4_QEI_CFG_RUN_Pos                           0                                                         /*!< CCU1 CLK_M4_QEI_CFG: RUN Position   */
-#define CCU1_CLK_M4_QEI_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_QEI_CFG_RUN_Pos)                   /*!< CCU1 CLK_M4_QEI_CFG: RUN Mask       */
-#define CCU1_CLK_M4_QEI_CFG_AUTO_Pos                          1                                                         /*!< CCU1 CLK_M4_QEI_CFG: AUTO Position  */
-#define CCU1_CLK_M4_QEI_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_QEI_CFG_AUTO_Pos)                  /*!< CCU1 CLK_M4_QEI_CFG: AUTO Mask      */
-#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos                        2                                                         /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Position */
-#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos)                /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Mask    */
-
-// ----------------------------------  CCU1_CLK_M4_QEI_STAT  --------------------------------------
-#define CCU1_CLK_M4_QEI_STAT_RUN_Pos                          0                                                         /*!< CCU1 CLK_M4_QEI_STAT: RUN Position  */
-#define CCU1_CLK_M4_QEI_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_QEI_STAT_RUN_Pos)                  /*!< CCU1 CLK_M4_QEI_STAT: RUN Mask      */
-#define CCU1_CLK_M4_QEI_STAT_AUTO_Pos                         1                                                         /*!< CCU1 CLK_M4_QEI_STAT: AUTO Position */
-#define CCU1_CLK_M4_QEI_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_QEI_STAT_AUTO_Pos)                 /*!< CCU1 CLK_M4_QEI_STAT: AUTO Mask     */
-#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos                       2                                                         /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Position */
-#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos)               /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Mask   */
-
-// ---------------------------------  CCU1_CLK_PERIPH_BUS_CFG  ------------------------------------
-#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos                       0                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */
-#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos)               /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask   */
-#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos                      1                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */
-#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos)              /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask  */
-#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos                    2                                                         /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */
-#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos)            /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */
-
-// --------------------------------  CCU1_CLK_PERIPH_BUS_STAT  ------------------------------------
-#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos                      0                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */
-#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos)              /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask  */
-#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos                     1                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */
-#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos)             /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */
-#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */
-#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos)           /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */
-
-// --------------------------------  CCU1_CLK_PERIPH_CORE_CFG  ------------------------------------
-#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos                      0                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */
-#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos)              /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask  */
-#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos                     1                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */
-#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos)             /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */
-#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos                   2                                                         /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */
-#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos)           /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */
-
-// --------------------------------  CCU1_CLK_PERIPH_CORE_STAT  -----------------------------------
-#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos                     0                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */
-#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos)             /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */
-#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos                    1                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */
-#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos)            /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */
-#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */
-#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos)          /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */
-
-// --------------------------------  CCU1_CLK_PERIPH_SGPIO_CFG  -----------------------------------
-#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos                     0                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Position */
-#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos)             /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Mask */
-#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos                    1                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Position */
-#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos)            /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Mask */
-#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos                  2                                                         /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Position */
-#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos)          /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Mask */
-
-// -------------------------------  CCU1_CLK_PERIPH_SGPIO_STAT  -----------------------------------
-#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos                    0                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Position */
-#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos)            /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Mask */
-#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos                   1                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Position */
-#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Msk                   (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos)           /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Mask */
-#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos                 2                                                         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Position */
-#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Msk                 (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos)         /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Mask */
-
-// ------------------------------------  CCU1_CLK_USB0_CFG  ---------------------------------------
-#define CCU1_CLK_USB0_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_USB0_CFG: RUN Position     */
-#define CCU1_CLK_USB0_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos)                     /*!< CCU1 CLK_USB0_CFG: RUN Mask         */
-#define CCU1_CLK_USB0_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_USB0_CFG: AUTO Position    */
-#define CCU1_CLK_USB0_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos)                    /*!< CCU1 CLK_USB0_CFG: AUTO Mask        */
-#define CCU1_CLK_USB0_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_USB0_CFG: WAKEUP Position  */
-#define CCU1_CLK_USB0_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask      */
-
-// -----------------------------------  CCU1_CLK_USB0_STAT  ---------------------------------------
-#define CCU1_CLK_USB0_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_USB0_STAT: RUN Position    */
-#define CCU1_CLK_USB0_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos)                    /*!< CCU1 CLK_USB0_STAT: RUN Mask        */
-#define CCU1_CLK_USB0_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_USB0_STAT: AUTO Position   */
-#define CCU1_CLK_USB0_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos)                   /*!< CCU1 CLK_USB0_STAT: AUTO Mask       */
-#define CCU1_CLK_USB0_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */
-#define CCU1_CLK_USB0_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask     */
-
-// ------------------------------------  CCU1_CLK_USB1_CFG  ---------------------------------------
-#define CCU1_CLK_USB1_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_USB1_CFG: RUN Position     */
-#define CCU1_CLK_USB1_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos)                     /*!< CCU1 CLK_USB1_CFG: RUN Mask         */
-#define CCU1_CLK_USB1_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_USB1_CFG: AUTO Position    */
-#define CCU1_CLK_USB1_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos)                    /*!< CCU1 CLK_USB1_CFG: AUTO Mask        */
-#define CCU1_CLK_USB1_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_USB1_CFG: WAKEUP Position  */
-#define CCU1_CLK_USB1_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask      */
-
-// -----------------------------------  CCU1_CLK_USB1_STAT  ---------------------------------------
-#define CCU1_CLK_USB1_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_USB1_STAT: RUN Position    */
-#define CCU1_CLK_USB1_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos)                    /*!< CCU1 CLK_USB1_STAT: RUN Mask        */
-#define CCU1_CLK_USB1_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_USB1_STAT: AUTO Position   */
-#define CCU1_CLK_USB1_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos)                   /*!< CCU1 CLK_USB1_STAT: AUTO Mask       */
-#define CCU1_CLK_USB1_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */
-#define CCU1_CLK_USB1_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask     */
-
-// ------------------------------------  CCU1_CLK_SPI_CFG  ----------------------------------------
-#define CCU1_CLK_SPI_CFG_RUN_Pos                              0                                                         /*!< CCU1 CLK_SPI_CFG: RUN Position      */
-#define CCU1_CLK_SPI_CFG_RUN_Msk                              (0x01UL << CCU1_CLK_SPI_CFG_RUN_Pos)                      /*!< CCU1 CLK_SPI_CFG: RUN Mask          */
-#define CCU1_CLK_SPI_CFG_AUTO_Pos                             1                                                         /*!< CCU1 CLK_SPI_CFG: AUTO Position     */
-#define CCU1_CLK_SPI_CFG_AUTO_Msk                             (0x01UL << CCU1_CLK_SPI_CFG_AUTO_Pos)                     /*!< CCU1 CLK_SPI_CFG: AUTO Mask         */
-#define CCU1_CLK_SPI_CFG_WAKEUP_Pos                           2                                                         /*!< CCU1 CLK_SPI_CFG: WAKEUP Position   */
-#define CCU1_CLK_SPI_CFG_WAKEUP_Msk                           (0x01UL << CCU1_CLK_SPI_CFG_WAKEUP_Pos)                   /*!< CCU1 CLK_SPI_CFG: WAKEUP Mask       */
-
-// ------------------------------------  CCU1_CLK_SPI_STAT  ---------------------------------------
-#define CCU1_CLK_SPI_STAT_RUN_Pos                             0                                                         /*!< CCU1 CLK_SPI_STAT: RUN Position     */
-#define CCU1_CLK_SPI_STAT_RUN_Msk                             (0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos)                     /*!< CCU1 CLK_SPI_STAT: RUN Mask         */
-#define CCU1_CLK_SPI_STAT_AUTO_Pos                            1                                                         /*!< CCU1 CLK_SPI_STAT: AUTO Position    */
-#define CCU1_CLK_SPI_STAT_AUTO_Msk                            (0x01UL << CCU1_CLK_SPI_STAT_AUTO_Pos)                    /*!< CCU1 CLK_SPI_STAT: AUTO Mask        */
-#define CCU1_CLK_SPI_STAT_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_SPI_STAT: WAKEUP Position  */
-#define CCU1_CLK_SPI_STAT_WAKEUP_Msk                          (0x01UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos)                  /*!< CCU1 CLK_SPI_STAT: WAKEUP Mask      */
-
-// ------------------------------------  CCU1_CLK_VADC_CFG  ---------------------------------------
-#define CCU1_CLK_VADC_CFG_RUN_Pos                             0                                                         /*!< CCU1 CLK_VADC_CFG: RUN Position     */
-#define CCU1_CLK_VADC_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos)                     /*!< CCU1 CLK_VADC_CFG: RUN Mask         */
-#define CCU1_CLK_VADC_CFG_AUTO_Pos                            1                                                         /*!< CCU1 CLK_VADC_CFG: AUTO Position    */
-#define CCU1_CLK_VADC_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos)                    /*!< CCU1 CLK_VADC_CFG: AUTO Mask        */
-#define CCU1_CLK_VADC_CFG_WAKEUP_Pos                          2                                                         /*!< CCU1 CLK_VADC_CFG: WAKEUP Position  */
-#define CCU1_CLK_VADC_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos)                  /*!< CCU1 CLK_VADC_CFG: WAKEUP Mask      */
-
-// -----------------------------------  CCU1_CLK_VADC_STAT  ---------------------------------------
-#define CCU1_CLK_VADC_STAT_RUN_Pos                            0                                                         /*!< CCU1 CLK_VADC_STAT: RUN Position    */
-#define CCU1_CLK_VADC_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos)                    /*!< CCU1 CLK_VADC_STAT: RUN Mask        */
-#define CCU1_CLK_VADC_STAT_AUTO_Pos                           1                                                         /*!< CCU1 CLK_VADC_STAT: AUTO Position   */
-#define CCU1_CLK_VADC_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos)                   /*!< CCU1 CLK_VADC_STAT: AUTO Mask       */
-#define CCU1_CLK_VADC_STAT_WAKEUP_Pos                         2                                                         /*!< CCU1 CLK_VADC_STAT: WAKEUP Position */
-#define CCU1_CLK_VADC_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos)                 /*!< CCU1 CLK_VADC_STAT: WAKEUP Mask     */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 CCU2 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------------  CCU2_PM  --------------------------------------------
-#define CCU2_PM_PD_Pos                                        0                                                         /*!< CCU2 PM: PD Position                */
-#define CCU2_PM_PD_Msk                                        (0x01UL << CCU2_PM_PD_Pos)                                /*!< CCU2 PM: PD Mask                    */
-
-// -------------------------------------  CCU2_BASE_STAT  -----------------------------------------
-#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos                     1                                                         /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */
-#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */
-#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos                     2                                                         /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */
-#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */
-#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos                     3                                                         /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */
-#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */
-#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos                     4                                                         /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */
-#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos)             /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */
-#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos                      5                                                         /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */
-#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos)              /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask  */
-#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos                      6                                                         /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */
-#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos)              /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask  */
-
-// ------------------------------------  CCU2_CLK_APLL_CFG  ---------------------------------------
-#define CCU2_CLK_APLL_CFG_RUN_Pos                             0                                                         /*!< CCU2 CLK_APLL_CFG: RUN Position     */
-#define CCU2_CLK_APLL_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_APLL_CFG_RUN_Pos)                     /*!< CCU2 CLK_APLL_CFG: RUN Mask         */
-#define CCU2_CLK_APLL_CFG_AUTO_Pos                            1                                                         /*!< CCU2 CLK_APLL_CFG: AUTO Position    */
-#define CCU2_CLK_APLL_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_APLL_CFG_AUTO_Pos)                    /*!< CCU2 CLK_APLL_CFG: AUTO Mask        */
-#define CCU2_CLK_APLL_CFG_WAKEUP_Pos                          2                                                         /*!< CCU2 CLK_APLL_CFG: WAKEUP Position  */
-#define CCU2_CLK_APLL_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_APLL_CFG_WAKEUP_Pos)                  /*!< CCU2 CLK_APLL_CFG: WAKEUP Mask      */
-
-// -----------------------------------  CCU2_CLK_APLL_STAT  ---------------------------------------
-#define CCU2_CLK_APLL_STAT_RUN_Pos                            0                                                         /*!< CCU2 CLK_APLL_STAT: RUN Position    */
-#define CCU2_CLK_APLL_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos)                    /*!< CCU2 CLK_APLL_STAT: RUN Mask        */
-#define CCU2_CLK_APLL_STAT_AUTO_Pos                           1                                                         /*!< CCU2 CLK_APLL_STAT: AUTO Position   */
-#define CCU2_CLK_APLL_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos)                   /*!< CCU2 CLK_APLL_STAT: AUTO Mask       */
-#define CCU2_CLK_APLL_STAT_WAKEUP_Pos                         2                                                         /*!< CCU2 CLK_APLL_STAT: WAKEUP Position */
-#define CCU2_CLK_APLL_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos)                 /*!< CCU2 CLK_APLL_STAT: WAKEUP Mask     */
-
-// --------------------------------  CCU2_CLK_APB2_USART3_CFG  ------------------------------------
-#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */
-#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos)              /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask  */
-#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */
-#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */
-#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */
-#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */
-
-// --------------------------------  CCU2_CLK_APB2_USART3_STAT  -----------------------------------
-#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */
-#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos)             /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */
-#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */
-#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */
-#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */
-#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */
-
-// --------------------------------  CCU2_CLK_APB2_USART2_CFG  ------------------------------------
-#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */
-#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos)              /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask  */
-#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */
-#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */
-#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */
-#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */
-
-// --------------------------------  CCU2_CLK_APB2_USART2_STAT  -----------------------------------
-#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */
-#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos)             /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */
-#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */
-#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */
-#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */
-#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */
-
-// -------------------------------  CCU2_CLK_APB0_UART1_BUS_CFG  ----------------------------------
-#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos                   0                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */
-#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos)           /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */
-#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos                  1                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */
-#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk                  (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos)          /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */
-#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos                2                                                         /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */
-#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk                (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos)        /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */
-
-// --------------------------------  CCU2_CLK_APB0_UART1_STAT  ------------------------------------
-#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */
-#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos)              /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask  */
-#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */
-#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos)             /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */
-#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */
-#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos)           /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */
-
-// --------------------------------  CCU2_CLK_APB0_USART0_CFG  ------------------------------------
-#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos                      0                                                         /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */
-#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos)              /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask  */
-#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos                     1                                                         /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */
-#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos)             /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */
-#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos                   2                                                         /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */
-#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos)           /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */
-
-// --------------------------------  CCU2_CLK_APB0_USART0_STAT  -----------------------------------
-#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos                     0                                                         /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */
-#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos)             /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */
-#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos                    1                                                         /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */
-#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos)            /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */
-#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos                  2                                                         /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */
-#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos)          /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU2_CLK_APB2_SSP1_CFG  -------------------------------------
-#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos                        0                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */
-#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos)                /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask    */
-#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos                       1                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */
-#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos)               /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask   */
-#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos                     2                                                         /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */
-#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos)             /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU2_CLK_APB2_SSP1_STAT  ------------------------------------
-#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos                       0                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */
-#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos)               /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask   */
-#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos                      1                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */
-#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos)              /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask  */
-#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos                    2                                                         /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */
-#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos)            /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */
-
-// ---------------------------------  CCU2_CLK_APB0_SSP0_CFG  -------------------------------------
-#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos                        0                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */
-#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos)                /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask    */
-#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos                       1                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */
-#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos)               /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask   */
-#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos                     2                                                         /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */
-#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos)             /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */
-
-// ---------------------------------  CCU2_CLK_APB0_SSP0_STAT  ------------------------------------
-#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos                       0                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */
-#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos)               /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask   */
-#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos                      1                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */
-#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos)              /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask  */
-#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos                    2                                                         /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */
-#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos)            /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */
-
-// ------------------------------------  CCU2_CLK_SDIO_CFG  ---------------------------------------
-#define CCU2_CLK_SDIO_CFG_RUN_Pos                             0                                                         /*!< CCU2 CLK_SDIO_CFG: RUN Position     */
-#define CCU2_CLK_SDIO_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos)                     /*!< CCU2 CLK_SDIO_CFG: RUN Mask         */
-#define CCU2_CLK_SDIO_CFG_AUTO_Pos                            1                                                         /*!< CCU2 CLK_SDIO_CFG: AUTO Position    */
-#define CCU2_CLK_SDIO_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos)                    /*!< CCU2 CLK_SDIO_CFG: AUTO Mask        */
-#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos                          2                                                         /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position  */
-#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos)                  /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask      */
-
-// -----------------------------------  CCU2_CLK_SDIO_STAT  ---------------------------------------
-#define CCU2_CLK_SDIO_STAT_RUN_Pos                            0                                                         /*!< CCU2 CLK_SDIO_STAT: RUN Position    */
-#define CCU2_CLK_SDIO_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos)                    /*!< CCU2 CLK_SDIO_STAT: RUN Mask        */
-#define CCU2_CLK_SDIO_STAT_AUTO_Pos                           1                                                         /*!< CCU2 CLK_SDIO_STAT: AUTO Position   */
-#define CCU2_CLK_SDIO_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos)                   /*!< CCU2 CLK_SDIO_STAT: AUTO Mask       */
-#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos                         2                                                         /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */
-#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos)                 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask     */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  RGU Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -------------------------------------  RGU_RESET_CTRL0  ----------------------------------------
-#define RGU_RESET_CTRL0_CORE_RST_Pos                          0                                                         /*!< RGU RESET_CTRL0: CORE_RST Position  */
-#define RGU_RESET_CTRL0_CORE_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos)                  /*!< RGU RESET_CTRL0: CORE_RST Mask      */
-#define RGU_RESET_CTRL0_PERIPH_RST_Pos                        1                                                         /*!< RGU RESET_CTRL0: PERIPH_RST Position */
-#define RGU_RESET_CTRL0_PERIPH_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos)                /*!< RGU RESET_CTRL0: PERIPH_RST Mask    */
-#define RGU_RESET_CTRL0_MASTER_RST_Pos                        2                                                         /*!< RGU RESET_CTRL0: MASTER_RST Position */
-#define RGU_RESET_CTRL0_MASTER_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos)                /*!< RGU RESET_CTRL0: MASTER_RST Mask    */
-#define RGU_RESET_CTRL0_WWDT_RST_Pos                          4                                                         /*!< RGU RESET_CTRL0: WWDT_RST Position  */
-#define RGU_RESET_CTRL0_WWDT_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos)                  /*!< RGU RESET_CTRL0: WWDT_RST Mask      */
-#define RGU_RESET_CTRL0_CREG_RST_Pos                          5                                                         /*!< RGU RESET_CTRL0: CREG_RST Position  */
-#define RGU_RESET_CTRL0_CREG_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos)                  /*!< RGU RESET_CTRL0: CREG_RST Mask      */
-#define RGU_RESET_CTRL0_BUS_RST_Pos                           8                                                         /*!< RGU RESET_CTRL0: BUS_RST Position   */
-#define RGU_RESET_CTRL0_BUS_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos)                   /*!< RGU RESET_CTRL0: BUS_RST Mask       */
-#define RGU_RESET_CTRL0_SCU_RST_Pos                           9                                                         /*!< RGU RESET_CTRL0: SCU_RST Position   */
-#define RGU_RESET_CTRL0_SCU_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos)                   /*!< RGU RESET_CTRL0: SCU_RST Mask       */
-#define RGU_RESET_CTRL0_PINMUX_RST_Pos                        10                                                        /*!< RGU RESET_CTRL0: PINMUX_RST Position */
-#define RGU_RESET_CTRL0_PINMUX_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos)                /*!< RGU RESET_CTRL0: PINMUX_RST Mask    */
-#define RGU_RESET_CTRL0_M4_RST_Pos                            13                                                        /*!< RGU RESET_CTRL0: M4_RST Position    */
-#define RGU_RESET_CTRL0_M4_RST_Msk                            (0x01UL << RGU_RESET_CTRL0_M4_RST_Pos)                    /*!< RGU RESET_CTRL0: M4_RST Mask        */
-#define RGU_RESET_CTRL0_LCD_RST_Pos                           16                                                        /*!< RGU RESET_CTRL0: LCD_RST Position   */
-#define RGU_RESET_CTRL0_LCD_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos)                   /*!< RGU RESET_CTRL0: LCD_RST Mask       */
-#define RGU_RESET_CTRL0_USB0_RST_Pos                          17                                                        /*!< RGU RESET_CTRL0: USB0_RST Position  */
-#define RGU_RESET_CTRL0_USB0_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos)                  /*!< RGU RESET_CTRL0: USB0_RST Mask      */
-#define RGU_RESET_CTRL0_USB1_RST_Pos                          18                                                        /*!< RGU RESET_CTRL0: USB1_RST Position  */
-#define RGU_RESET_CTRL0_USB1_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos)                  /*!< RGU RESET_CTRL0: USB1_RST Mask      */
-#define RGU_RESET_CTRL0_DMA_RST_Pos                           19                                                        /*!< RGU RESET_CTRL0: DMA_RST Position   */
-#define RGU_RESET_CTRL0_DMA_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos)                   /*!< RGU RESET_CTRL0: DMA_RST Mask       */
-#define RGU_RESET_CTRL0_SDIO_RST_Pos                          20                                                        /*!< RGU RESET_CTRL0: SDIO_RST Position  */
-#define RGU_RESET_CTRL0_SDIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos)                  /*!< RGU RESET_CTRL0: SDIO_RST Mask      */
-#define RGU_RESET_CTRL0_EMC_RST_Pos                           21                                                        /*!< RGU RESET_CTRL0: EMC_RST Position   */
-#define RGU_RESET_CTRL0_EMC_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos)                   /*!< RGU RESET_CTRL0: EMC_RST Mask       */
-#define RGU_RESET_CTRL0_ETHERNET_RST_Pos                      22                                                        /*!< RGU RESET_CTRL0: ETHERNET_RST Position */
-#define RGU_RESET_CTRL0_ETHERNET_RST_Msk                      (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos)              /*!< RGU RESET_CTRL0: ETHERNET_RST Mask  */
-#define RGU_RESET_CTRL0_GPIO_RST_Pos                          28                                                        /*!< RGU RESET_CTRL0: GPIO_RST Position  */
-#define RGU_RESET_CTRL0_GPIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos)                  /*!< RGU RESET_CTRL0: GPIO_RST Mask      */
-
-// -------------------------------------  RGU_RESET_CTRL1  ----------------------------------------
-#define RGU_RESET_CTRL1_TIMER0_RST_Pos                        0                                                         /*!< RGU RESET_CTRL1: TIMER0_RST Position */
-#define RGU_RESET_CTRL1_TIMER0_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER0_RST Mask    */
-#define RGU_RESET_CTRL1_TIMER1_RST_Pos                        1                                                         /*!< RGU RESET_CTRL1: TIMER1_RST Position */
-#define RGU_RESET_CTRL1_TIMER1_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER1_RST Mask    */
-#define RGU_RESET_CTRL1_TIMER2_RST_Pos                        2                                                         /*!< RGU RESET_CTRL1: TIMER2_RST Position */
-#define RGU_RESET_CTRL1_TIMER2_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER2_RST Mask    */
-#define RGU_RESET_CTRL1_TIMER3_RST_Pos                        3                                                         /*!< RGU RESET_CTRL1: TIMER3_RST Position */
-#define RGU_RESET_CTRL1_TIMER3_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos)                /*!< RGU RESET_CTRL1: TIMER3_RST Mask    */
-#define RGU_RESET_CTRL1_RITIMER_RST_Pos                       4                                                         /*!< RGU RESET_CTRL1: RITIMER_RST Position */
-#define RGU_RESET_CTRL1_RITIMER_RST_Msk                       (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos)               /*!< RGU RESET_CTRL1: RITIMER_RST Mask   */
-#define RGU_RESET_CTRL1_SCT_RST_Pos                           5                                                         /*!< RGU RESET_CTRL1: SCT_RST Position   */
-#define RGU_RESET_CTRL1_SCT_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos)                   /*!< RGU RESET_CTRL1: SCT_RST Mask       */
-#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos                    6                                                         /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */
-#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk                    (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos)            /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */
-#define RGU_RESET_CTRL1_QEI_RST_Pos                           7                                                         /*!< RGU RESET_CTRL1: QEI_RST Position   */
-#define RGU_RESET_CTRL1_QEI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos)                   /*!< RGU RESET_CTRL1: QEI_RST Mask       */
-#define RGU_RESET_CTRL1_ADC0_RST_Pos                          8                                                         /*!< RGU RESET_CTRL1: ADC0_RST Position  */
-#define RGU_RESET_CTRL1_ADC0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos)                  /*!< RGU RESET_CTRL1: ADC0_RST Mask      */
-#define RGU_RESET_CTRL1_ADC1_RST_Pos                          9                                                         /*!< RGU RESET_CTRL1: ADC1_RST Position  */
-#define RGU_RESET_CTRL1_ADC1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos)                  /*!< RGU RESET_CTRL1: ADC1_RST Mask      */
-#define RGU_RESET_CTRL1_DAC_RST_Pos                           10                                                        /*!< RGU RESET_CTRL1: DAC_RST Position   */
-#define RGU_RESET_CTRL1_DAC_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos)                   /*!< RGU RESET_CTRL1: DAC_RST Mask       */
-#define RGU_RESET_CTRL1_UART0_RST_Pos                         12                                                        /*!< RGU RESET_CTRL1: UART0_RST Position */
-#define RGU_RESET_CTRL1_UART0_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos)                 /*!< RGU RESET_CTRL1: UART0_RST Mask     */
-#define RGU_RESET_CTRL1_UART1_RST_Pos                         13                                                        /*!< RGU RESET_CTRL1: UART1_RST Position */
-#define RGU_RESET_CTRL1_UART1_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos)                 /*!< RGU RESET_CTRL1: UART1_RST Mask     */
-#define RGU_RESET_CTRL1_UART2_RST_Pos                         14                                                        /*!< RGU RESET_CTRL1: UART2_RST Position */
-#define RGU_RESET_CTRL1_UART2_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos)                 /*!< RGU RESET_CTRL1: UART2_RST Mask     */
-#define RGU_RESET_CTRL1_UART3_RST_Pos                         15                                                        /*!< RGU RESET_CTRL1: UART3_RST Position */
-#define RGU_RESET_CTRL1_UART3_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos)                 /*!< RGU RESET_CTRL1: UART3_RST Mask     */
-#define RGU_RESET_CTRL1_I2C0_RST_Pos                          16                                                        /*!< RGU RESET_CTRL1: I2C0_RST Position  */
-#define RGU_RESET_CTRL1_I2C0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos)                  /*!< RGU RESET_CTRL1: I2C0_RST Mask      */
-#define RGU_RESET_CTRL1_I2C1_RST_Pos                          17                                                        /*!< RGU RESET_CTRL1: I2C1_RST Position  */
-#define RGU_RESET_CTRL1_I2C1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos)                  /*!< RGU RESET_CTRL1: I2C1_RST Mask      */
-#define RGU_RESET_CTRL1_SSP0_RST_Pos                          18                                                        /*!< RGU RESET_CTRL1: SSP0_RST Position  */
-#define RGU_RESET_CTRL1_SSP0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos)                  /*!< RGU RESET_CTRL1: SSP0_RST Mask      */
-#define RGU_RESET_CTRL1_SSP1_RST_Pos                          19                                                        /*!< RGU RESET_CTRL1: SSP1_RST Position  */
-#define RGU_RESET_CTRL1_SSP1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos)                  /*!< RGU RESET_CTRL1: SSP1_RST Mask      */
-#define RGU_RESET_CTRL1_I2S_RST_Pos                           20                                                        /*!< RGU RESET_CTRL1: I2S_RST Position   */
-#define RGU_RESET_CTRL1_I2S_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos)                   /*!< RGU RESET_CTRL1: I2S_RST Mask       */
-#define RGU_RESET_CTRL1_SPIFI_RST_Pos                         21                                                        /*!< RGU RESET_CTRL1: SPIFI_RST Position */
-#define RGU_RESET_CTRL1_SPIFI_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos)                 /*!< RGU RESET_CTRL1: SPIFI_RST Mask     */
-#define RGU_RESET_CTRL1_CAN1_RST_Pos                          22                                                        /*!< RGU RESET_CTRL1: CAN1_RST Position  */
-#define RGU_RESET_CTRL1_CAN1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos)                  /*!< RGU RESET_CTRL1: CAN1_RST Mask      */
-#define RGU_RESET_CTRL1_CAN0_RST_Pos                          23                                                        /*!< RGU RESET_CTRL1: CAN0_RST Position  */
-#define RGU_RESET_CTRL1_CAN0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos)                  /*!< RGU RESET_CTRL1: CAN0_RST Mask      */
-#define RGU_RESET_CTRL1_M0APP_RST_Pos                         24                                                        /*!< RGU RESET_CTRL1: M0APP_RST Position */
-#define RGU_RESET_CTRL1_M0APP_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_M0APP_RST_Pos)                 /*!< RGU RESET_CTRL1: M0APP_RST Mask     */
-#define RGU_RESET_CTRL1_SGPIO_RST_Pos                         25                                                        /*!< RGU RESET_CTRL1: SGPIO_RST Position */
-#define RGU_RESET_CTRL1_SGPIO_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SGPIO_RST_Pos)                 /*!< RGU RESET_CTRL1: SGPIO_RST Mask     */
-#define RGU_RESET_CTRL1_SPI_RST_Pos                           26                                                        /*!< RGU RESET_CTRL1: SPI_RST Position   */
-#define RGU_RESET_CTRL1_SPI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SPI_RST_Pos)                   /*!< RGU RESET_CTRL1: SPI_RST Mask       */
-
-// ------------------------------------  RGU_RESET_STATUS0  ---------------------------------------
-#define RGU_RESET_STATUS0_CORE_RST_Pos                        0                                                         /*!< RGU RESET_STATUS0: CORE_RST Position */
-#define RGU_RESET_STATUS0_CORE_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos)                /*!< RGU RESET_STATUS0: CORE_RST Mask    */
-#define RGU_RESET_STATUS0_PERIPH_RST_Pos                      2                                                         /*!< RGU RESET_STATUS0: PERIPH_RST Position */
-#define RGU_RESET_STATUS0_PERIPH_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos)              /*!< RGU RESET_STATUS0: PERIPH_RST Mask  */
-#define RGU_RESET_STATUS0_MASTER_RST_Pos                      4                                                         /*!< RGU RESET_STATUS0: MASTER_RST Position */
-#define RGU_RESET_STATUS0_MASTER_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos)              /*!< RGU RESET_STATUS0: MASTER_RST Mask  */
-#define RGU_RESET_STATUS0_WWDT_RST_Pos                        8                                                         /*!< RGU RESET_STATUS0: WWDT_RST Position */
-#define RGU_RESET_STATUS0_WWDT_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos)                /*!< RGU RESET_STATUS0: WWDT_RST Mask    */
-#define RGU_RESET_STATUS0_CREG_RST_Pos                        10                                                        /*!< RGU RESET_STATUS0: CREG_RST Position */
-#define RGU_RESET_STATUS0_CREG_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos)                /*!< RGU RESET_STATUS0: CREG_RST Mask    */
-#define RGU_RESET_STATUS0_BUS_RST_Pos                         16                                                        /*!< RGU RESET_STATUS0: BUS_RST Position */
-#define RGU_RESET_STATUS0_BUS_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos)                 /*!< RGU RESET_STATUS0: BUS_RST Mask     */
-#define RGU_RESET_STATUS0_SCU_RST_Pos                         18                                                        /*!< RGU RESET_STATUS0: SCU_RST Position */
-#define RGU_RESET_STATUS0_SCU_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos)                 /*!< RGU RESET_STATUS0: SCU_RST Mask     */
-#define RGU_RESET_STATUS0_M4_RST_Pos                          26                                                        /*!< RGU RESET_STATUS0: M4_RST Position  */
-#define RGU_RESET_STATUS0_M4_RST_Msk                          (0x03UL << RGU_RESET_STATUS0_M4_RST_Pos)                  /*!< RGU RESET_STATUS0: M4_RST Mask      */
-
-// ------------------------------------  RGU_RESET_STATUS1  ---------------------------------------
-#define RGU_RESET_STATUS1_LCD_RST_Pos                         0                                                         /*!< RGU RESET_STATUS1: LCD_RST Position */
-#define RGU_RESET_STATUS1_LCD_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos)                 /*!< RGU RESET_STATUS1: LCD_RST Mask     */
-#define RGU_RESET_STATUS1_USB0_RST_Pos                        2                                                         /*!< RGU RESET_STATUS1: USB0_RST Position */
-#define RGU_RESET_STATUS1_USB0_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos)                /*!< RGU RESET_STATUS1: USB0_RST Mask    */
-#define RGU_RESET_STATUS1_USB1_RST_Pos                        4                                                         /*!< RGU RESET_STATUS1: USB1_RST Position */
-#define RGU_RESET_STATUS1_USB1_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos)                /*!< RGU RESET_STATUS1: USB1_RST Mask    */
-#define RGU_RESET_STATUS1_DMA_RST_Pos                         6                                                         /*!< RGU RESET_STATUS1: DMA_RST Position */
-#define RGU_RESET_STATUS1_DMA_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos)                 /*!< RGU RESET_STATUS1: DMA_RST Mask     */
-#define RGU_RESET_STATUS1_SDIO_RST_Pos                        8                                                         /*!< RGU RESET_STATUS1: SDIO_RST Position */
-#define RGU_RESET_STATUS1_SDIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos)                /*!< RGU RESET_STATUS1: SDIO_RST Mask    */
-#define RGU_RESET_STATUS1_EMC_RST_Pos                         10                                                        /*!< RGU RESET_STATUS1: EMC_RST Position */
-#define RGU_RESET_STATUS1_EMC_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos)                 /*!< RGU RESET_STATUS1: EMC_RST Mask     */
-#define RGU_RESET_STATUS1_ETHERNET_RST_Pos                    12                                                        /*!< RGU RESET_STATUS1: ETHERNET_RST Position */
-#define RGU_RESET_STATUS1_ETHERNET_RST_Msk                    (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos)            /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */
-#define RGU_RESET_STATUS1_GPIO_RST_Pos                        24                                                        /*!< RGU RESET_STATUS1: GPIO_RST Position */
-#define RGU_RESET_STATUS1_GPIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos)                /*!< RGU RESET_STATUS1: GPIO_RST Mask    */
-
-// ------------------------------------  RGU_RESET_STATUS2  ---------------------------------------
-#define RGU_RESET_STATUS2_TIMER0_RST_Pos                      0                                                         /*!< RGU RESET_STATUS2: TIMER0_RST Position */
-#define RGU_RESET_STATUS2_TIMER0_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER0_RST Mask  */
-#define RGU_RESET_STATUS2_TIMER1_RST_Pos                      2                                                         /*!< RGU RESET_STATUS2: TIMER1_RST Position */
-#define RGU_RESET_STATUS2_TIMER1_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER1_RST Mask  */
-#define RGU_RESET_STATUS2_TIMER2_RST_Pos                      4                                                         /*!< RGU RESET_STATUS2: TIMER2_RST Position */
-#define RGU_RESET_STATUS2_TIMER2_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER2_RST Mask  */
-#define RGU_RESET_STATUS2_TIMER3_RST_Pos                      6                                                         /*!< RGU RESET_STATUS2: TIMER3_RST Position */
-#define RGU_RESET_STATUS2_TIMER3_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos)              /*!< RGU RESET_STATUS2: TIMER3_RST Mask  */
-#define RGU_RESET_STATUS2_RITIMER_RST_Pos                     8                                                         /*!< RGU RESET_STATUS2: RITIMER_RST Position */
-#define RGU_RESET_STATUS2_RITIMER_RST_Msk                     (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos)             /*!< RGU RESET_STATUS2: RITIMER_RST Mask */
-#define RGU_RESET_STATUS2_SCT_RST_Pos                         10                                                        /*!< RGU RESET_STATUS2: SCT_RST Position */
-#define RGU_RESET_STATUS2_SCT_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos)                 /*!< RGU RESET_STATUS2: SCT_RST Mask     */
-#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos                  12                                                        /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */
-#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk                  (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos)          /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */
-#define RGU_RESET_STATUS2_QEI_RST_Pos                         14                                                        /*!< RGU RESET_STATUS2: QEI_RST Position */
-#define RGU_RESET_STATUS2_QEI_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos)                 /*!< RGU RESET_STATUS2: QEI_RST Mask     */
-#define RGU_RESET_STATUS2_ADC0_RST_Pos                        16                                                        /*!< RGU RESET_STATUS2: ADC0_RST Position */
-#define RGU_RESET_STATUS2_ADC0_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos)                /*!< RGU RESET_STATUS2: ADC0_RST Mask    */
-#define RGU_RESET_STATUS2_ADC1_RST_Pos                        18                                                        /*!< RGU RESET_STATUS2: ADC1_RST Position */
-#define RGU_RESET_STATUS2_ADC1_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos)                /*!< RGU RESET_STATUS2: ADC1_RST Mask    */
-#define RGU_RESET_STATUS2_DAC_RST_Pos                         20                                                        /*!< RGU RESET_STATUS2: DAC_RST Position */
-#define RGU_RESET_STATUS2_DAC_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos)                 /*!< RGU RESET_STATUS2: DAC_RST Mask     */
-#define RGU_RESET_STATUS2_UART0_RST_Pos                       24                                                        /*!< RGU RESET_STATUS2: UART0_RST Position */
-#define RGU_RESET_STATUS2_UART0_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos)               /*!< RGU RESET_STATUS2: UART0_RST Mask   */
-#define RGU_RESET_STATUS2_UART1_RST_Pos                       26                                                        /*!< RGU RESET_STATUS2: UART1_RST Position */
-#define RGU_RESET_STATUS2_UART1_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos)               /*!< RGU RESET_STATUS2: UART1_RST Mask   */
-#define RGU_RESET_STATUS2_UART2_RST_Pos                       28                                                        /*!< RGU RESET_STATUS2: UART2_RST Position */
-#define RGU_RESET_STATUS2_UART2_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos)               /*!< RGU RESET_STATUS2: UART2_RST Mask   */
-#define RGU_RESET_STATUS2_UART3_RST_Pos                       30                                                        /*!< RGU RESET_STATUS2: UART3_RST Position */
-#define RGU_RESET_STATUS2_UART3_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos)               /*!< RGU RESET_STATUS2: UART3_RST Mask   */
-
-// ------------------------------------  RGU_RESET_STATUS3  ---------------------------------------
-#define RGU_RESET_STATUS3_I2C0_RST_Pos                        0                                                         /*!< RGU RESET_STATUS3: I2C0_RST Position */
-#define RGU_RESET_STATUS3_I2C0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos)                /*!< RGU RESET_STATUS3: I2C0_RST Mask    */
-#define RGU_RESET_STATUS3_I2C1_RST_Pos                        2                                                         /*!< RGU RESET_STATUS3: I2C1_RST Position */
-#define RGU_RESET_STATUS3_I2C1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos)                /*!< RGU RESET_STATUS3: I2C1_RST Mask    */
-#define RGU_RESET_STATUS3_SSP0_RST_Pos                        4                                                         /*!< RGU RESET_STATUS3: SSP0_RST Position */
-#define RGU_RESET_STATUS3_SSP0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos)                /*!< RGU RESET_STATUS3: SSP0_RST Mask    */
-#define RGU_RESET_STATUS3_SSP1_RST_Pos                        6                                                         /*!< RGU RESET_STATUS3: SSP1_RST Position */
-#define RGU_RESET_STATUS3_SSP1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos)                /*!< RGU RESET_STATUS3: SSP1_RST Mask    */
-#define RGU_RESET_STATUS3_I2S_RST_Pos                         8                                                         /*!< RGU RESET_STATUS3: I2S_RST Position */
-#define RGU_RESET_STATUS3_I2S_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos)                 /*!< RGU RESET_STATUS3: I2S_RST Mask     */
-#define RGU_RESET_STATUS3_SPIFI_RST_Pos                       10                                                        /*!< RGU RESET_STATUS3: SPIFI_RST Position */
-#define RGU_RESET_STATUS3_SPIFI_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos)               /*!< RGU RESET_STATUS3: SPIFI_RST Mask   */
-#define RGU_RESET_STATUS3_CAN1_RST_Pos                        12                                                        /*!< RGU RESET_STATUS3: CAN1_RST Position */
-#define RGU_RESET_STATUS3_CAN1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos)                /*!< RGU RESET_STATUS3: CAN1_RST Mask    */
-#define RGU_RESET_STATUS3_CAN0_RST_Pos                        14                                                        /*!< RGU RESET_STATUS3: CAN0_RST Position */
-#define RGU_RESET_STATUS3_CAN0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos)                /*!< RGU RESET_STATUS3: CAN0_RST Mask    */
-#define RGU_RESET_STATUS3_M0APP_RST_Pos                       16                                                        /*!< RGU RESET_STATUS3: M0APP_RST Position */
-#define RGU_RESET_STATUS3_M0APP_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_M0APP_RST_Pos)               /*!< RGU RESET_STATUS3: M0APP_RST Mask   */
-#define RGU_RESET_STATUS3_SGPIO_RST_Pos                       18                                                        /*!< RGU RESET_STATUS3: SGPIO_RST Position */
-#define RGU_RESET_STATUS3_SGPIO_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SGPIO_RST_Pos)               /*!< RGU RESET_STATUS3: SGPIO_RST Mask   */
-#define RGU_RESET_STATUS3_SPI_RST_Pos                         20                                                        /*!< RGU RESET_STATUS3: SPI_RST Position */
-#define RGU_RESET_STATUS3_SPI_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_SPI_RST_Pos)                 /*!< RGU RESET_STATUS3: SPI_RST Mask     */
-
-// --------------------------------  RGU_RESET_ACTIVE_STATUS0  ------------------------------------
-#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos                 0                                                         /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos               1                                                         /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos               2                                                         /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos                 4                                                         /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos                 5                                                         /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos                  8                                                         /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos                  9                                                         /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos               10                                                        /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos                   13                                                        /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk                   (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos)           /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos                  16                                                        /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos                 17                                                        /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos                 18                                                        /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos                  19                                                        /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos                 20                                                        /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos                  21                                                        /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos             22                                                        /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk             (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos)     /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos                 28                                                        /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */
-#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */
-
-// --------------------------------  RGU_RESET_ACTIVE_STATUS1  ------------------------------------
-#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos               0                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos               1                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos               2                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos               3                                                         /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos)       /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos              4                                                         /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk              (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos)      /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos                  5                                                         /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos           6                                                         /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk           (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos)   /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos                  7                                                         /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos                 8                                                         /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos                 9                                                         /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos                  10                                                        /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos                12                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos                13                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos                14                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos                15                                                        /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos                 16                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos                 17                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos                 18                                                        /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos                 19                                                        /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos                  20                                                        /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos                21                                                        /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos                 22                                                        /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos                 23                                                        /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos)         /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos                24                                                        /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos                25                                                        /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos)        /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Mask */
-#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos                  26                                                        /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Position */
-#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos)          /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Mask */
-
-// -----------------------------------  RGU_RESET_EXT_STAT0  --------------------------------------
-#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos                     0                                                         /*!< RGU RESET_EXT_STAT0: EXT_RESET Position */
-#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos)             /*!< RGU RESET_EXT_STAT0: EXT_RESET Mask */
-#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos                     4                                                         /*!< RGU RESET_EXT_STAT0: BOD_RESET Position */
-#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos)             /*!< RGU RESET_EXT_STAT0: BOD_RESET Mask */
-#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos                    5                                                         /*!< RGU RESET_EXT_STAT0: WWDT_RESET Position */
-#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos)            /*!< RGU RESET_EXT_STAT0: WWDT_RESET Mask */
-
-// -----------------------------------  RGU_RESET_EXT_STAT1  --------------------------------------
-#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */
-#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */
-
-// -----------------------------------  RGU_RESET_EXT_STAT2  --------------------------------------
-#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */
-
-// -----------------------------------  RGU_RESET_EXT_STAT4  --------------------------------------
-#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT4: CORE_RESET Position */
-#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT4: CORE_RESET Mask */
-
-// -----------------------------------  RGU_RESET_EXT_STAT5  --------------------------------------
-#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos                    1                                                         /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */
-#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos)            /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */
-
-// -----------------------------------  RGU_RESET_EXT_STAT8  --------------------------------------
-#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */
-
-// -----------------------------------  RGU_RESET_EXT_STAT9  --------------------------------------
-#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos              2                                                         /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos)      /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT13  --------------------------------------
-#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */
-#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT16  --------------------------------------
-#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */
-#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT17  --------------------------------------
-#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */
-#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT18  --------------------------------------
-#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */
-#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT19  --------------------------------------
-#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */
-#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT20  --------------------------------------
-#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */
-#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT21  --------------------------------------
-#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */
-#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT22  --------------------------------------
-#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */
-#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT23  --------------------------------------
-#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos                 3                                                         /*!< RGU RESET_EXT_STAT23: MASTER_RESET Position */
-#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos)         /*!< RGU RESET_EXT_STAT23: MASTER_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT28  --------------------------------------
-#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT32  --------------------------------------
-#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT33  --------------------------------------
-#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT34  --------------------------------------
-#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT35  --------------------------------------
-#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT36  --------------------------------------
-#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT37  --------------------------------------
-#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT38  --------------------------------------
-#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT39  --------------------------------------
-#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT40  --------------------------------------
-#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT41  --------------------------------------
-#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT42  --------------------------------------
-#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT44  --------------------------------------
-#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT45  --------------------------------------
-#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT46  --------------------------------------
-#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT47  --------------------------------------
-#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT48  --------------------------------------
-#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT49  --------------------------------------
-#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT50  --------------------------------------
-#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT51  --------------------------------------
-#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT52  --------------------------------------
-#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT53  --------------------------------------
-#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT54  --------------------------------------
-#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */
-
-// ----------------------------------  RGU_RESET_EXT_STAT55  --------------------------------------
-#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos             2                                                         /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */
-#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos)     /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 WWDT Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  WWDT_MOD  --------------------------------------------
-#define WWDT_MOD_WDEN_Pos                                     0                                                         /*!< WWDT MOD: WDEN Position             */
-#define WWDT_MOD_WDEN_Msk                                     (0x01UL << WWDT_MOD_WDEN_Pos)                             /*!< WWDT MOD: WDEN Mask                 */
-#define WWDT_MOD_WDRESET_Pos                                  1                                                         /*!< WWDT MOD: WDRESET Position          */
-#define WWDT_MOD_WDRESET_Msk                                  (0x01UL << WWDT_MOD_WDRESET_Pos)                          /*!< WWDT MOD: WDRESET Mask              */
-#define WWDT_MOD_WDTOF_Pos                                    2                                                         /*!< WWDT MOD: WDTOF Position            */
-#define WWDT_MOD_WDTOF_Msk                                    (0x01UL << WWDT_MOD_WDTOF_Pos)                            /*!< WWDT MOD: WDTOF Mask                */
-#define WWDT_MOD_WDINT_Pos                                    3                                                         /*!< WWDT MOD: WDINT Position            */
-#define WWDT_MOD_WDINT_Msk                                    (0x01UL << WWDT_MOD_WDINT_Pos)                            /*!< WWDT MOD: WDINT Mask                */
-#define WWDT_MOD_WDPROTECT_Pos                                4                                                         /*!< WWDT MOD: WDPROTECT Position        */
-#define WWDT_MOD_WDPROTECT_Msk                                (0x01UL << WWDT_MOD_WDPROTECT_Pos)                        /*!< WWDT MOD: WDPROTECT Mask            */
-
-// -----------------------------------------  WWDT_TC  --------------------------------------------
-#define WWDT_TC_WDTC_Pos                                      0                                                         /*!< WWDT TC: WDTC Position              */
-#define WWDT_TC_WDTC_Msk                                      (0x00ffffffUL << WWDT_TC_WDTC_Pos)                        /*!< WWDT TC: WDTC Mask                  */
-
-// ----------------------------------------  WWDT_FEED  -------------------------------------------
-#define WWDT_FEED_Feed_Pos                                    0                                                         /*!< WWDT FEED: Feed Position            */
-#define WWDT_FEED_Feed_Msk                                    (0x000000ffUL << WWDT_FEED_Feed_Pos)                      /*!< WWDT FEED: Feed Mask                */
-
-// -----------------------------------------  WWDT_TV  --------------------------------------------
-#define WWDT_TV_Count_Pos                                     0                                                         /*!< WWDT TV: Count Position             */
-#define WWDT_TV_Count_Msk                                     (0x00ffffffUL << WWDT_TV_Count_Pos)                       /*!< WWDT TV: Count Mask                 */
-
-// --------------------------------------  WWDT_WARNINT  ------------------------------------------
-#define WWDT_WARNINT_WDWARNINT_Pos                            0                                                         /*!< WWDT WARNINT: WDWARNINT Position    */
-#define WWDT_WARNINT_WDWARNINT_Msk                            (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos)              /*!< WWDT WARNINT: WDWARNINT Mask        */
-
-// ---------------------------------------  WWDT_WINDOW  ------------------------------------------
-#define WWDT_WINDOW_WDWINDOW_Pos                              0                                                         /*!< WWDT WINDOW: WDWINDOW Position      */
-#define WWDT_WINDOW_WDWINDOW_Msk                              (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos)                /*!< WWDT WINDOW: WDWINDOW Mask          */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                USART0 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  USART0_RBR  -------------------------------------------
-#define USART0_RBR_RBR_Pos                                    0                                                         /*!< USART0 RBR: RBR Position            */
-#define USART0_RBR_RBR_Msk                                    (0x000000ffUL << USART0_RBR_RBR_Pos)                      /*!< USART0 RBR: RBR Mask                */
-
-// ---------------------------------------  USART0_THR  -------------------------------------------
-#define USART0_THR_THR_Pos                                    0                                                         /*!< USART0 THR: THR Position            */
-#define USART0_THR_THR_Msk                                    (0x000000ffUL << USART0_THR_THR_Pos)                      /*!< USART0 THR: THR Mask                */
-
-// ---------------------------------------  USART0_DLL  -------------------------------------------
-#define USART0_DLL_DLLSB_Pos                                  0                                                         /*!< USART0 DLL: DLLSB Position          */
-#define USART0_DLL_DLLSB_Msk                                  (0x000000ffUL << USART0_DLL_DLLSB_Pos)                    /*!< USART0 DLL: DLLSB Mask              */
-
-// ---------------------------------------  USART0_DLM  -------------------------------------------
-#define USART0_DLM_DLMSB_Pos                                  0                                                         /*!< USART0 DLM: DLMSB Position          */
-#define USART0_DLM_DLMSB_Msk                                  (0x000000ffUL << USART0_DLM_DLMSB_Pos)                    /*!< USART0 DLM: DLMSB Mask              */
-
-// ---------------------------------------  USART0_IER  -------------------------------------------
-#define USART0_IER_RBRIE_Pos                                  0                                                         /*!< USART0 IER: RBRIE Position          */
-#define USART0_IER_RBRIE_Msk                                  (0x01UL << USART0_IER_RBRIE_Pos)                          /*!< USART0 IER: RBRIE Mask              */
-#define USART0_IER_THREIE_Pos                                 1                                                         /*!< USART0 IER: THREIE Position         */
-#define USART0_IER_THREIE_Msk                                 (0x01UL << USART0_IER_THREIE_Pos)                         /*!< USART0 IER: THREIE Mask             */
-#define USART0_IER_RXIE_Pos                                   2                                                         /*!< USART0 IER: RXIE Position           */
-#define USART0_IER_RXIE_Msk                                   (0x01UL << USART0_IER_RXIE_Pos)                           /*!< USART0 IER: RXIE Mask               */
-#define USART0_IER_ABEOINTEN_Pos                              8                                                         /*!< USART0 IER: ABEOINTEN Position      */
-#define USART0_IER_ABEOINTEN_Msk                              (0x01UL << USART0_IER_ABEOINTEN_Pos)                      /*!< USART0 IER: ABEOINTEN Mask          */
-#define USART0_IER_ABTOINTEN_Pos                              9                                                         /*!< USART0 IER: ABTOINTEN Position      */
-#define USART0_IER_ABTOINTEN_Msk                              (0x01UL << USART0_IER_ABTOINTEN_Pos)                      /*!< USART0 IER: ABTOINTEN Mask          */
-
-// ---------------------------------------  USART0_IIR  -------------------------------------------
-#define USART0_IIR_INTSTATUS_Pos                              0                                                         /*!< USART0 IIR: INTSTATUS Position      */
-#define USART0_IIR_INTSTATUS_Msk                              (0x01UL << USART0_IIR_INTSTATUS_Pos)                      /*!< USART0 IIR: INTSTATUS Mask          */
-#define USART0_IIR_INTID_Pos                                  1                                                         /*!< USART0 IIR: INTID Position          */
-#define USART0_IIR_INTID_Msk                                  (0x07UL << USART0_IIR_INTID_Pos)                          /*!< USART0 IIR: INTID Mask              */
-#define USART0_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART0 IIR: FIFOENABLE Position     */
-#define USART0_IIR_FIFOENABLE_Msk                             (0x03UL << USART0_IIR_FIFOENABLE_Pos)                     /*!< USART0 IIR: FIFOENABLE Mask         */
-#define USART0_IIR_ABEOINT_Pos                                8                                                         /*!< USART0 IIR: ABEOINT Position        */
-#define USART0_IIR_ABEOINT_Msk                                (0x01UL << USART0_IIR_ABEOINT_Pos)                        /*!< USART0 IIR: ABEOINT Mask            */
-#define USART0_IIR_ABTOINT_Pos                                9                                                         /*!< USART0 IIR: ABTOINT Position        */
-#define USART0_IIR_ABTOINT_Msk                                (0x01UL << USART0_IIR_ABTOINT_Pos)                        /*!< USART0 IIR: ABTOINT Mask            */
-
-// ---------------------------------------  USART0_FCR  -------------------------------------------
-#define USART0_FCR_FIFOEN_Pos                                 0                                                         /*!< USART0 FCR: FIFOEN Position         */
-#define USART0_FCR_FIFOEN_Msk                                 (0x01UL << USART0_FCR_FIFOEN_Pos)                         /*!< USART0 FCR: FIFOEN Mask             */
-#define USART0_FCR_RXFIFORES_Pos                              1                                                         /*!< USART0 FCR: RXFIFORES Position      */
-#define USART0_FCR_RXFIFORES_Msk                              (0x01UL << USART0_FCR_RXFIFORES_Pos)                      /*!< USART0 FCR: RXFIFORES Mask          */
-#define USART0_FCR_TXFIFORES_Pos                              2                                                         /*!< USART0 FCR: TXFIFORES Position      */
-#define USART0_FCR_TXFIFORES_Msk                              (0x01UL << USART0_FCR_TXFIFORES_Pos)                      /*!< USART0 FCR: TXFIFORES Mask          */
-#define USART0_FCR_DMAMODE_Pos                                3                                                         /*!< USART0 FCR: DMAMODE Position        */
-#define USART0_FCR_DMAMODE_Msk                                (0x01UL << USART0_FCR_DMAMODE_Pos)                        /*!< USART0 FCR: DMAMODE Mask            */
-#define USART0_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART0 FCR: RXTRIGLVL Position      */
-#define USART0_FCR_RXTRIGLVL_Msk                              (0x03UL << USART0_FCR_RXTRIGLVL_Pos)                      /*!< USART0 FCR: RXTRIGLVL Mask          */
-
-// ---------------------------------------  USART0_LCR  -------------------------------------------
-#define USART0_LCR_WLS_Pos                                    0                                                         /*!< USART0 LCR: WLS Position            */
-#define USART0_LCR_WLS_Msk                                    (0x03UL << USART0_LCR_WLS_Pos)                            /*!< USART0 LCR: WLS Mask                */
-#define USART0_LCR_SBS_Pos                                    2                                                         /*!< USART0 LCR: SBS Position            */
-#define USART0_LCR_SBS_Msk                                    (0x01UL << USART0_LCR_SBS_Pos)                            /*!< USART0 LCR: SBS Mask                */
-#define USART0_LCR_PE_Pos                                     3                                                         /*!< USART0 LCR: PE Position             */
-#define USART0_LCR_PE_Msk                                     (0x01UL << USART0_LCR_PE_Pos)                             /*!< USART0 LCR: PE Mask                 */
-#define USART0_LCR_PS_Pos                                     4                                                         /*!< USART0 LCR: PS Position             */
-#define USART0_LCR_PS_Msk                                     (0x03UL << USART0_LCR_PS_Pos)                             /*!< USART0 LCR: PS Mask                 */
-#define USART0_LCR_BC_Pos                                     6                                                         /*!< USART0 LCR: BC Position             */
-#define USART0_LCR_BC_Msk                                     (0x01UL << USART0_LCR_BC_Pos)                             /*!< USART0 LCR: BC Mask                 */
-#define USART0_LCR_DLAB_Pos                                   7                                                         /*!< USART0 LCR: DLAB Position           */
-#define USART0_LCR_DLAB_Msk                                   (0x01UL << USART0_LCR_DLAB_Pos)                           /*!< USART0 LCR: DLAB Mask               */
-
-// ---------------------------------------  USART0_LSR  -------------------------------------------
-#define USART0_LSR_RDR_Pos                                    0                                                         /*!< USART0 LSR: RDR Position            */
-#define USART0_LSR_RDR_Msk                                    (0x01UL << USART0_LSR_RDR_Pos)                            /*!< USART0 LSR: RDR Mask                */
-#define USART0_LSR_OE_Pos                                     1                                                         /*!< USART0 LSR: OE Position             */
-#define USART0_LSR_OE_Msk                                     (0x01UL << USART0_LSR_OE_Pos)                             /*!< USART0 LSR: OE Mask                 */
-#define USART0_LSR_PE_Pos                                     2                                                         /*!< USART0 LSR: PE Position             */
-#define USART0_LSR_PE_Msk                                     (0x01UL << USART0_LSR_PE_Pos)                             /*!< USART0 LSR: PE Mask                 */
-#define USART0_LSR_FE_Pos                                     3                                                         /*!< USART0 LSR: FE Position             */
-#define USART0_LSR_FE_Msk                                     (0x01UL << USART0_LSR_FE_Pos)                             /*!< USART0 LSR: FE Mask                 */
-#define USART0_LSR_BI_Pos                                     4                                                         /*!< USART0 LSR: BI Position             */
-#define USART0_LSR_BI_Msk                                     (0x01UL << USART0_LSR_BI_Pos)                             /*!< USART0 LSR: BI Mask                 */
-#define USART0_LSR_THRE_Pos                                   5                                                         /*!< USART0 LSR: THRE Position           */
-#define USART0_LSR_THRE_Msk                                   (0x01UL << USART0_LSR_THRE_Pos)                           /*!< USART0 LSR: THRE Mask               */
-#define USART0_LSR_TEMT_Pos                                   6                                                         /*!< USART0 LSR: TEMT Position           */
-#define USART0_LSR_TEMT_Msk                                   (0x01UL << USART0_LSR_TEMT_Pos)                           /*!< USART0 LSR: TEMT Mask               */
-#define USART0_LSR_RXFE_Pos                                   7                                                         /*!< USART0 LSR: RXFE Position           */
-#define USART0_LSR_RXFE_Msk                                   (0x01UL << USART0_LSR_RXFE_Pos)                           /*!< USART0 LSR: RXFE Mask               */
-#define USART0_LSR_TXERR_Pos                                  8                                                         /*!< USART0 LSR: TXERR Position          */
-#define USART0_LSR_TXERR_Msk                                  (0x01UL << USART0_LSR_TXERR_Pos)                          /*!< USART0 LSR: TXERR Mask              */
-
-// ---------------------------------------  USART0_SCR  -------------------------------------------
-#define USART0_SCR_PAD_Pos                                    0                                                         /*!< USART0 SCR: PAD Position            */
-#define USART0_SCR_PAD_Msk                                    (0x000000ffUL << USART0_SCR_PAD_Pos)                      /*!< USART0 SCR: PAD Mask                */
-
-// ---------------------------------------  USART0_ACR  -------------------------------------------
-#define USART0_ACR_START_Pos                                  0                                                         /*!< USART0 ACR: START Position          */
-#define USART0_ACR_START_Msk                                  (0x01UL << USART0_ACR_START_Pos)                          /*!< USART0 ACR: START Mask              */
-#define USART0_ACR_MODE_Pos                                   1                                                         /*!< USART0 ACR: MODE Position           */
-#define USART0_ACR_MODE_Msk                                   (0x01UL << USART0_ACR_MODE_Pos)                           /*!< USART0 ACR: MODE Mask               */
-#define USART0_ACR_AUTORESTART_Pos                            2                                                         /*!< USART0 ACR: AUTORESTART Position    */
-#define USART0_ACR_AUTORESTART_Msk                            (0x01UL << USART0_ACR_AUTORESTART_Pos)                    /*!< USART0 ACR: AUTORESTART Mask        */
-#define USART0_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART0 ACR: ABEOINTCLR Position     */
-#define USART0_ACR_ABEOINTCLR_Msk                             (0x01UL << USART0_ACR_ABEOINTCLR_Pos)                     /*!< USART0 ACR: ABEOINTCLR Mask         */
-#define USART0_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART0 ACR: ABTOINTCLR Position     */
-#define USART0_ACR_ABTOINTCLR_Msk                             (0x01UL << USART0_ACR_ABTOINTCLR_Pos)                     /*!< USART0 ACR: ABTOINTCLR Mask         */
-
-// ---------------------------------------  USART0_ICR  -------------------------------------------
-#define USART0_ICR_IRDAEN_Pos                                 0                                                         /*!< USART0 ICR: IRDAEN Position         */
-#define USART0_ICR_IRDAEN_Msk                                 (0x01UL << USART0_ICR_IRDAEN_Pos)                         /*!< USART0 ICR: IRDAEN Mask             */
-#define USART0_ICR_IRDAINV_Pos                                1                                                         /*!< USART0 ICR: IRDAINV Position        */
-#define USART0_ICR_IRDAINV_Msk                                (0x01UL << USART0_ICR_IRDAINV_Pos)                        /*!< USART0 ICR: IRDAINV Mask            */
-#define USART0_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART0 ICR: FIXPULSEEN Position     */
-#define USART0_ICR_FIXPULSEEN_Msk                             (0x01UL << USART0_ICR_FIXPULSEEN_Pos)                     /*!< USART0 ICR: FIXPULSEEN Mask         */
-#define USART0_ICR_PULSEDIV_Pos                               3                                                         /*!< USART0 ICR: PULSEDIV Position       */
-#define USART0_ICR_PULSEDIV_Msk                               (0x07UL << USART0_ICR_PULSEDIV_Pos)                       /*!< USART0 ICR: PULSEDIV Mask           */
-
-// ---------------------------------------  USART0_FDR  -------------------------------------------
-#define USART0_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART0 FDR: DIVADDVAL Position      */
-#define USART0_FDR_DIVADDVAL_Msk                              (0x0fUL << USART0_FDR_DIVADDVAL_Pos)                      /*!< USART0 FDR: DIVADDVAL Mask          */
-#define USART0_FDR_MULVAL_Pos                                 4                                                         /*!< USART0 FDR: MULVAL Position         */
-#define USART0_FDR_MULVAL_Msk                                 (0x0fUL << USART0_FDR_MULVAL_Pos)                         /*!< USART0 FDR: MULVAL Mask             */
-
-// ---------------------------------------  USART0_OSR  -------------------------------------------
-#define USART0_OSR_OSFRAC_Pos                                 1                                                         /*!< USART0 OSR: OSFRAC Position         */
-#define USART0_OSR_OSFRAC_Msk                                 (0x07UL << USART0_OSR_OSFRAC_Pos)                         /*!< USART0 OSR: OSFRAC Mask             */
-#define USART0_OSR_OSINT_Pos                                  4                                                         /*!< USART0 OSR: OSINT Position          */
-#define USART0_OSR_OSINT_Msk                                  (0x0fUL << USART0_OSR_OSINT_Pos)                          /*!< USART0 OSR: OSINT Mask              */
-#define USART0_OSR_FDINT_Pos                                  8                                                         /*!< USART0 OSR: FDINT Position          */
-#define USART0_OSR_FDINT_Msk                                  (0x7fUL << USART0_OSR_FDINT_Pos)                          /*!< USART0 OSR: FDINT Mask              */
-
-// ---------------------------------------  USART0_HDEN  ------------------------------------------
-#define USART0_HDEN_HDEN_Pos                                  0                                                         /*!< USART0 HDEN: HDEN Position          */
-#define USART0_HDEN_HDEN_Msk                                  (0x01UL << USART0_HDEN_HDEN_Pos)                          /*!< USART0 HDEN: HDEN Mask              */
-
-// -------------------------------------  USART0_SCICTRL  -----------------------------------------
-#define USART0_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART0 SCICTRL: SCIEN Position      */
-#define USART0_SCICTRL_SCIEN_Msk                              (0x01UL << USART0_SCICTRL_SCIEN_Pos)                      /*!< USART0 SCICTRL: SCIEN Mask          */
-#define USART0_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART0 SCICTRL: NACKDIS Position    */
-#define USART0_SCICTRL_NACKDIS_Msk                            (0x01UL << USART0_SCICTRL_NACKDIS_Pos)                    /*!< USART0 SCICTRL: NACKDIS Mask        */
-#define USART0_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART0 SCICTRL: PROTSEL Position    */
-#define USART0_SCICTRL_PROTSEL_Msk                            (0x01UL << USART0_SCICTRL_PROTSEL_Pos)                    /*!< USART0 SCICTRL: PROTSEL Mask        */
-#define USART0_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART0 SCICTRL: TXRETRY Position    */
-#define USART0_SCICTRL_TXRETRY_Msk                            (0x07UL << USART0_SCICTRL_TXRETRY_Pos)                    /*!< USART0 SCICTRL: TXRETRY Mask        */
-#define USART0_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART0 SCICTRL: GUARDTIME Position  */
-#define USART0_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos)            /*!< USART0 SCICTRL: GUARDTIME Mask      */
-
-// ------------------------------------  USART0_RS485CTRL  ----------------------------------------
-#define USART0_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART0 RS485CTRL: NMMEN Position    */
-#define USART0_RS485CTRL_NMMEN_Msk                            (0x01UL << USART0_RS485CTRL_NMMEN_Pos)                    /*!< USART0 RS485CTRL: NMMEN Mask        */
-#define USART0_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART0 RS485CTRL: RXDIS Position    */
-#define USART0_RS485CTRL_RXDIS_Msk                            (0x01UL << USART0_RS485CTRL_RXDIS_Pos)                    /*!< USART0 RS485CTRL: RXDIS Mask        */
-#define USART0_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART0 RS485CTRL: AADEN Position    */
-#define USART0_RS485CTRL_AADEN_Msk                            (0x01UL << USART0_RS485CTRL_AADEN_Pos)                    /*!< USART0 RS485CTRL: AADEN Mask        */
-#define USART0_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART0 RS485CTRL: DCTRL Position    */
-#define USART0_RS485CTRL_DCTRL_Msk                            (0x01UL << USART0_RS485CTRL_DCTRL_Pos)                    /*!< USART0 RS485CTRL: DCTRL Mask        */
-#define USART0_RS485CTRL_OINV_Pos                             5                                                         /*!< USART0 RS485CTRL: OINV Position     */
-#define USART0_RS485CTRL_OINV_Msk                             (0x01UL << USART0_RS485CTRL_OINV_Pos)                     /*!< USART0 RS485CTRL: OINV Mask         */
-
-// ----------------------------------  USART0_RS485ADRMATCH  --------------------------------------
-#define USART0_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART0 RS485ADRMATCH: ADRMATCH Position */
-#define USART0_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */
-
-// -------------------------------------  USART0_RS485DLY  ----------------------------------------
-#define USART0_RS485DLY_DLY_Pos                               0                                                         /*!< USART0 RS485DLY: DLY Position       */
-#define USART0_RS485DLY_DLY_Msk                               (0x000000ffUL << USART0_RS485DLY_DLY_Pos)                 /*!< USART0 RS485DLY: DLY Mask           */
-
-// -------------------------------------  USART0_SYNCCTRL  ----------------------------------------
-#define USART0_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART0 SYNCCTRL: SYNC Position      */
-#define USART0_SYNCCTRL_SYNC_Msk                              (0x01UL << USART0_SYNCCTRL_SYNC_Pos)                      /*!< USART0 SYNCCTRL: SYNC Mask          */
-#define USART0_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART0 SYNCCTRL: CSRC Position      */
-#define USART0_SYNCCTRL_CSRC_Msk                              (0x01UL << USART0_SYNCCTRL_CSRC_Pos)                      /*!< USART0 SYNCCTRL: CSRC Mask          */
-#define USART0_SYNCCTRL_FES_Pos                               2                                                         /*!< USART0 SYNCCTRL: FES Position       */
-#define USART0_SYNCCTRL_FES_Msk                               (0x01UL << USART0_SYNCCTRL_FES_Pos)                       /*!< USART0 SYNCCTRL: FES Mask           */
-#define USART0_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART0 SYNCCTRL: TSBYPASS Position  */
-#define USART0_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART0 SYNCCTRL: TSBYPASS Mask      */
-#define USART0_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART0 SYNCCTRL: CSCEN Position     */
-#define USART0_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART0_SYNCCTRL_CSCEN_Pos)                     /*!< USART0 SYNCCTRL: CSCEN Mask         */
-#define USART0_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART0 SYNCCTRL: SSSDIS Position    */
-#define USART0_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos)                    /*!< USART0 SYNCCTRL: SSSDIS Mask        */
-#define USART0_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART0 SYNCCTRL: CCCLR Position     */
-#define USART0_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART0_SYNCCTRL_CCCLR_Pos)                     /*!< USART0 SYNCCTRL: CCCLR Mask         */
-
-// ---------------------------------------  USART0_TER  -------------------------------------------
-#define USART0_TER_TXEN_Pos                                   0                                                         /*!< USART0 TER: TXEN Position           */
-#define USART0_TER_TXEN_Msk                                   (0x01UL << USART0_TER_TXEN_Pos)                           /*!< USART0 TER: TXEN Mask               */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                USART2 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  USART2_DLL  -------------------------------------------
-#define USART2_DLL_DLLSB_Pos                                  0                                                         /*!< USART2 DLL: DLLSB Position          */
-#define USART2_DLL_DLLSB_Msk                                  (0x000000ffUL << USART2_DLL_DLLSB_Pos)                    /*!< USART2 DLL: DLLSB Mask              */
-
-// ---------------------------------------  USART2_THR  -------------------------------------------
-#define USART2_THR_THR_Pos                                    0                                                         /*!< USART2 THR: THR Position            */
-#define USART2_THR_THR_Msk                                    (0x000000ffUL << USART2_THR_THR_Pos)                      /*!< USART2 THR: THR Mask                */
-
-// ---------------------------------------  USART2_RBR  -------------------------------------------
-#define USART2_RBR_RBR_Pos                                    0                                                         /*!< USART2 RBR: RBR Position            */
-#define USART2_RBR_RBR_Msk                                    (0x000000ffUL << USART2_RBR_RBR_Pos)                      /*!< USART2 RBR: RBR Mask                */
-
-// ---------------------------------------  USART2_IER  -------------------------------------------
-#define USART2_IER_RBRIE_Pos                                  0                                                         /*!< USART2 IER: RBRIE Position          */
-#define USART2_IER_RBRIE_Msk                                  (0x01UL << USART2_IER_RBRIE_Pos)                          /*!< USART2 IER: RBRIE Mask              */
-#define USART2_IER_THREIE_Pos                                 1                                                         /*!< USART2 IER: THREIE Position         */
-#define USART2_IER_THREIE_Msk                                 (0x01UL << USART2_IER_THREIE_Pos)                         /*!< USART2 IER: THREIE Mask             */
-#define USART2_IER_RXIE_Pos                                   2                                                         /*!< USART2 IER: RXIE Position           */
-#define USART2_IER_RXIE_Msk                                   (0x01UL << USART2_IER_RXIE_Pos)                           /*!< USART2 IER: RXIE Mask               */
-#define USART2_IER_ABEOINTEN_Pos                              8                                                         /*!< USART2 IER: ABEOINTEN Position      */
-#define USART2_IER_ABEOINTEN_Msk                              (0x01UL << USART2_IER_ABEOINTEN_Pos)                      /*!< USART2 IER: ABEOINTEN Mask          */
-#define USART2_IER_ABTOINTEN_Pos                              9                                                         /*!< USART2 IER: ABTOINTEN Position      */
-#define USART2_IER_ABTOINTEN_Msk                              (0x01UL << USART2_IER_ABTOINTEN_Pos)                      /*!< USART2 IER: ABTOINTEN Mask          */
-
-// ---------------------------------------  USART2_DLM  -------------------------------------------
-#define USART2_DLM_DLMSB_Pos                                  0                                                         /*!< USART2 DLM: DLMSB Position          */
-#define USART2_DLM_DLMSB_Msk                                  (0x000000ffUL << USART2_DLM_DLMSB_Pos)                    /*!< USART2 DLM: DLMSB Mask              */
-
-// ---------------------------------------  USART2_FCR  -------------------------------------------
-#define USART2_FCR_FIFOEN_Pos                                 0                                                         /*!< USART2 FCR: FIFOEN Position         */
-#define USART2_FCR_FIFOEN_Msk                                 (0x01UL << USART2_FCR_FIFOEN_Pos)                         /*!< USART2 FCR: FIFOEN Mask             */
-#define USART2_FCR_RXFIFORES_Pos                              1                                                         /*!< USART2 FCR: RXFIFORES Position      */
-#define USART2_FCR_RXFIFORES_Msk                              (0x01UL << USART2_FCR_RXFIFORES_Pos)                      /*!< USART2 FCR: RXFIFORES Mask          */
-#define USART2_FCR_TXFIFORES_Pos                              2                                                         /*!< USART2 FCR: TXFIFORES Position      */
-#define USART2_FCR_TXFIFORES_Msk                              (0x01UL << USART2_FCR_TXFIFORES_Pos)                      /*!< USART2 FCR: TXFIFORES Mask          */
-#define USART2_FCR_DMAMODE_Pos                                3                                                         /*!< USART2 FCR: DMAMODE Position        */
-#define USART2_FCR_DMAMODE_Msk                                (0x01UL << USART2_FCR_DMAMODE_Pos)                        /*!< USART2 FCR: DMAMODE Mask            */
-#define USART2_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART2 FCR: RXTRIGLVL Position      */
-#define USART2_FCR_RXTRIGLVL_Msk                              (0x03UL << USART2_FCR_RXTRIGLVL_Pos)                      /*!< USART2 FCR: RXTRIGLVL Mask          */
-
-// ---------------------------------------  USART2_IIR  -------------------------------------------
-#define USART2_IIR_INTSTATUS_Pos                              0                                                         /*!< USART2 IIR: INTSTATUS Position      */
-#define USART2_IIR_INTSTATUS_Msk                              (0x01UL << USART2_IIR_INTSTATUS_Pos)                      /*!< USART2 IIR: INTSTATUS Mask          */
-#define USART2_IIR_INTID_Pos                                  1                                                         /*!< USART2 IIR: INTID Position          */
-#define USART2_IIR_INTID_Msk                                  (0x07UL << USART2_IIR_INTID_Pos)                          /*!< USART2 IIR: INTID Mask              */
-#define USART2_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART2 IIR: FIFOENABLE Position     */
-#define USART2_IIR_FIFOENABLE_Msk                             (0x03UL << USART2_IIR_FIFOENABLE_Pos)                     /*!< USART2 IIR: FIFOENABLE Mask         */
-#define USART2_IIR_ABEOINT_Pos                                8                                                         /*!< USART2 IIR: ABEOINT Position        */
-#define USART2_IIR_ABEOINT_Msk                                (0x01UL << USART2_IIR_ABEOINT_Pos)                        /*!< USART2 IIR: ABEOINT Mask            */
-#define USART2_IIR_ABTOINT_Pos                                9                                                         /*!< USART2 IIR: ABTOINT Position        */
-#define USART2_IIR_ABTOINT_Msk                                (0x01UL << USART2_IIR_ABTOINT_Pos)                        /*!< USART2 IIR: ABTOINT Mask            */
-
-// ---------------------------------------  USART2_LCR  -------------------------------------------
-#define USART2_LCR_WLS_Pos                                    0                                                         /*!< USART2 LCR: WLS Position            */
-#define USART2_LCR_WLS_Msk                                    (0x03UL << USART2_LCR_WLS_Pos)                            /*!< USART2 LCR: WLS Mask                */
-#define USART2_LCR_SBS_Pos                                    2                                                         /*!< USART2 LCR: SBS Position            */
-#define USART2_LCR_SBS_Msk                                    (0x01UL << USART2_LCR_SBS_Pos)                            /*!< USART2 LCR: SBS Mask                */
-#define USART2_LCR_PE_Pos                                     3                                                         /*!< USART2 LCR: PE Position             */
-#define USART2_LCR_PE_Msk                                     (0x01UL << USART2_LCR_PE_Pos)                             /*!< USART2 LCR: PE Mask                 */
-#define USART2_LCR_PS_Pos                                     4                                                         /*!< USART2 LCR: PS Position             */
-#define USART2_LCR_PS_Msk                                     (0x03UL << USART2_LCR_PS_Pos)                             /*!< USART2 LCR: PS Mask                 */
-#define USART2_LCR_BC_Pos                                     6                                                         /*!< USART2 LCR: BC Position             */
-#define USART2_LCR_BC_Msk                                     (0x01UL << USART2_LCR_BC_Pos)                             /*!< USART2 LCR: BC Mask                 */
-#define USART2_LCR_DLAB_Pos                                   7                                                         /*!< USART2 LCR: DLAB Position           */
-#define USART2_LCR_DLAB_Msk                                   (0x01UL << USART2_LCR_DLAB_Pos)                           /*!< USART2 LCR: DLAB Mask               */
-
-// ---------------------------------------  USART2_LSR  -------------------------------------------
-#define USART2_LSR_RDR_Pos                                    0                                                         /*!< USART2 LSR: RDR Position            */
-#define USART2_LSR_RDR_Msk                                    (0x01UL << USART2_LSR_RDR_Pos)                            /*!< USART2 LSR: RDR Mask                */
-#define USART2_LSR_OE_Pos                                     1                                                         /*!< USART2 LSR: OE Position             */
-#define USART2_LSR_OE_Msk                                     (0x01UL << USART2_LSR_OE_Pos)                             /*!< USART2 LSR: OE Mask                 */
-#define USART2_LSR_PE_Pos                                     2                                                         /*!< USART2 LSR: PE Position             */
-#define USART2_LSR_PE_Msk                                     (0x01UL << USART2_LSR_PE_Pos)                             /*!< USART2 LSR: PE Mask                 */
-#define USART2_LSR_FE_Pos                                     3                                                         /*!< USART2 LSR: FE Position             */
-#define USART2_LSR_FE_Msk                                     (0x01UL << USART2_LSR_FE_Pos)                             /*!< USART2 LSR: FE Mask                 */
-#define USART2_LSR_BI_Pos                                     4                                                         /*!< USART2 LSR: BI Position             */
-#define USART2_LSR_BI_Msk                                     (0x01UL << USART2_LSR_BI_Pos)                             /*!< USART2 LSR: BI Mask                 */
-#define USART2_LSR_THRE_Pos                                   5                                                         /*!< USART2 LSR: THRE Position           */
-#define USART2_LSR_THRE_Msk                                   (0x01UL << USART2_LSR_THRE_Pos)                           /*!< USART2 LSR: THRE Mask               */
-#define USART2_LSR_TEMT_Pos                                   6                                                         /*!< USART2 LSR: TEMT Position           */
-#define USART2_LSR_TEMT_Msk                                   (0x01UL << USART2_LSR_TEMT_Pos)                           /*!< USART2 LSR: TEMT Mask               */
-#define USART2_LSR_RXFE_Pos                                   7                                                         /*!< USART2 LSR: RXFE Position           */
-#define USART2_LSR_RXFE_Msk                                   (0x01UL << USART2_LSR_RXFE_Pos)                           /*!< USART2 LSR: RXFE Mask               */
-#define USART2_LSR_TXERR_Pos                                  8                                                         /*!< USART2 LSR: TXERR Position          */
-#define USART2_LSR_TXERR_Msk                                  (0x01UL << USART2_LSR_TXERR_Pos)                          /*!< USART2 LSR: TXERR Mask              */
-
-// ---------------------------------------  USART2_SCR  -------------------------------------------
-#define USART2_SCR_PAD_Pos                                    0                                                         /*!< USART2 SCR: PAD Position            */
-#define USART2_SCR_PAD_Msk                                    (0x000000ffUL << USART2_SCR_PAD_Pos)                      /*!< USART2 SCR: PAD Mask                */
-
-// ---------------------------------------  USART2_ACR  -------------------------------------------
-#define USART2_ACR_START_Pos                                  0                                                         /*!< USART2 ACR: START Position          */
-#define USART2_ACR_START_Msk                                  (0x01UL << USART2_ACR_START_Pos)                          /*!< USART2 ACR: START Mask              */
-#define USART2_ACR_MODE_Pos                                   1                                                         /*!< USART2 ACR: MODE Position           */
-#define USART2_ACR_MODE_Msk                                   (0x01UL << USART2_ACR_MODE_Pos)                           /*!< USART2 ACR: MODE Mask               */
-#define USART2_ACR_AUTORESTART_Pos                            2                                                         /*!< USART2 ACR: AUTORESTART Position    */
-#define USART2_ACR_AUTORESTART_Msk                            (0x01UL << USART2_ACR_AUTORESTART_Pos)                    /*!< USART2 ACR: AUTORESTART Mask        */
-#define USART2_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART2 ACR: ABEOINTCLR Position     */
-#define USART2_ACR_ABEOINTCLR_Msk                             (0x01UL << USART2_ACR_ABEOINTCLR_Pos)                     /*!< USART2 ACR: ABEOINTCLR Mask         */
-#define USART2_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART2 ACR: ABTOINTCLR Position     */
-#define USART2_ACR_ABTOINTCLR_Msk                             (0x01UL << USART2_ACR_ABTOINTCLR_Pos)                     /*!< USART2 ACR: ABTOINTCLR Mask         */
-
-// ---------------------------------------  USART2_ICR  -------------------------------------------
-#define USART2_ICR_IRDAEN_Pos                                 0                                                         /*!< USART2 ICR: IRDAEN Position         */
-#define USART2_ICR_IRDAEN_Msk                                 (0x01UL << USART2_ICR_IRDAEN_Pos)                         /*!< USART2 ICR: IRDAEN Mask             */
-#define USART2_ICR_IRDAINV_Pos                                1                                                         /*!< USART2 ICR: IRDAINV Position        */
-#define USART2_ICR_IRDAINV_Msk                                (0x01UL << USART2_ICR_IRDAINV_Pos)                        /*!< USART2 ICR: IRDAINV Mask            */
-#define USART2_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART2 ICR: FIXPULSEEN Position     */
-#define USART2_ICR_FIXPULSEEN_Msk                             (0x01UL << USART2_ICR_FIXPULSEEN_Pos)                     /*!< USART2 ICR: FIXPULSEEN Mask         */
-#define USART2_ICR_PULSEDIV_Pos                               3                                                         /*!< USART2 ICR: PULSEDIV Position       */
-#define USART2_ICR_PULSEDIV_Msk                               (0x07UL << USART2_ICR_PULSEDIV_Pos)                       /*!< USART2 ICR: PULSEDIV Mask           */
-
-// ---------------------------------------  USART2_FDR  -------------------------------------------
-#define USART2_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART2 FDR: DIVADDVAL Position      */
-#define USART2_FDR_DIVADDVAL_Msk                              (0x0fUL << USART2_FDR_DIVADDVAL_Pos)                      /*!< USART2 FDR: DIVADDVAL Mask          */
-#define USART2_FDR_MULVAL_Pos                                 4                                                         /*!< USART2 FDR: MULVAL Position         */
-#define USART2_FDR_MULVAL_Msk                                 (0x0fUL << USART2_FDR_MULVAL_Pos)                         /*!< USART2 FDR: MULVAL Mask             */
-
-// ---------------------------------------  USART2_OSR  -------------------------------------------
-#define USART2_OSR_OSFRAC_Pos                                 1                                                         /*!< USART2 OSR: OSFRAC Position         */
-#define USART2_OSR_OSFRAC_Msk                                 (0x07UL << USART2_OSR_OSFRAC_Pos)                         /*!< USART2 OSR: OSFRAC Mask             */
-#define USART2_OSR_OSINT_Pos                                  4                                                         /*!< USART2 OSR: OSINT Position          */
-#define USART2_OSR_OSINT_Msk                                  (0x0fUL << USART2_OSR_OSINT_Pos)                          /*!< USART2 OSR: OSINT Mask              */
-#define USART2_OSR_FDINT_Pos                                  8                                                         /*!< USART2 OSR: FDINT Position          */
-#define USART2_OSR_FDINT_Msk                                  (0x7fUL << USART2_OSR_FDINT_Pos)                          /*!< USART2 OSR: FDINT Mask              */
-
-// ---------------------------------------  USART2_HDEN  ------------------------------------------
-#define USART2_HDEN_HDEN_Pos                                  0                                                         /*!< USART2 HDEN: HDEN Position          */
-#define USART2_HDEN_HDEN_Msk                                  (0x01UL << USART2_HDEN_HDEN_Pos)                          /*!< USART2 HDEN: HDEN Mask              */
-
-// -------------------------------------  USART2_SCICTRL  -----------------------------------------
-#define USART2_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART2 SCICTRL: SCIEN Position      */
-#define USART2_SCICTRL_SCIEN_Msk                              (0x01UL << USART2_SCICTRL_SCIEN_Pos)                      /*!< USART2 SCICTRL: SCIEN Mask          */
-#define USART2_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART2 SCICTRL: NACKDIS Position    */
-#define USART2_SCICTRL_NACKDIS_Msk                            (0x01UL << USART2_SCICTRL_NACKDIS_Pos)                    /*!< USART2 SCICTRL: NACKDIS Mask        */
-#define USART2_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART2 SCICTRL: PROTSEL Position    */
-#define USART2_SCICTRL_PROTSEL_Msk                            (0x01UL << USART2_SCICTRL_PROTSEL_Pos)                    /*!< USART2 SCICTRL: PROTSEL Mask        */
-#define USART2_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART2 SCICTRL: TXRETRY Position    */
-#define USART2_SCICTRL_TXRETRY_Msk                            (0x07UL << USART2_SCICTRL_TXRETRY_Pos)                    /*!< USART2 SCICTRL: TXRETRY Mask        */
-#define USART2_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART2 SCICTRL: GUARDTIME Position  */
-#define USART2_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos)            /*!< USART2 SCICTRL: GUARDTIME Mask      */
-
-// ------------------------------------  USART2_RS485CTRL  ----------------------------------------
-#define USART2_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART2 RS485CTRL: NMMEN Position    */
-#define USART2_RS485CTRL_NMMEN_Msk                            (0x01UL << USART2_RS485CTRL_NMMEN_Pos)                    /*!< USART2 RS485CTRL: NMMEN Mask        */
-#define USART2_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART2 RS485CTRL: RXDIS Position    */
-#define USART2_RS485CTRL_RXDIS_Msk                            (0x01UL << USART2_RS485CTRL_RXDIS_Pos)                    /*!< USART2 RS485CTRL: RXDIS Mask        */
-#define USART2_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART2 RS485CTRL: AADEN Position    */
-#define USART2_RS485CTRL_AADEN_Msk                            (0x01UL << USART2_RS485CTRL_AADEN_Pos)                    /*!< USART2 RS485CTRL: AADEN Mask        */
-#define USART2_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART2 RS485CTRL: DCTRL Position    */
-#define USART2_RS485CTRL_DCTRL_Msk                            (0x01UL << USART2_RS485CTRL_DCTRL_Pos)                    /*!< USART2 RS485CTRL: DCTRL Mask        */
-#define USART2_RS485CTRL_OINV_Pos                             5                                                         /*!< USART2 RS485CTRL: OINV Position     */
-#define USART2_RS485CTRL_OINV_Msk                             (0x01UL << USART2_RS485CTRL_OINV_Pos)                     /*!< USART2 RS485CTRL: OINV Mask         */
-
-// ----------------------------------  USART2_RS485ADRMATCH  --------------------------------------
-#define USART2_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART2 RS485ADRMATCH: ADRMATCH Position */
-#define USART2_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */
-
-// -------------------------------------  USART2_RS485DLY  ----------------------------------------
-#define USART2_RS485DLY_DLY_Pos                               0                                                         /*!< USART2 RS485DLY: DLY Position       */
-#define USART2_RS485DLY_DLY_Msk                               (0x000000ffUL << USART2_RS485DLY_DLY_Pos)                 /*!< USART2 RS485DLY: DLY Mask           */
-
-// -------------------------------------  USART2_SYNCCTRL  ----------------------------------------
-#define USART2_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART2 SYNCCTRL: SYNC Position      */
-#define USART2_SYNCCTRL_SYNC_Msk                              (0x01UL << USART2_SYNCCTRL_SYNC_Pos)                      /*!< USART2 SYNCCTRL: SYNC Mask          */
-#define USART2_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART2 SYNCCTRL: CSRC Position      */
-#define USART2_SYNCCTRL_CSRC_Msk                              (0x01UL << USART2_SYNCCTRL_CSRC_Pos)                      /*!< USART2 SYNCCTRL: CSRC Mask          */
-#define USART2_SYNCCTRL_FES_Pos                               2                                                         /*!< USART2 SYNCCTRL: FES Position       */
-#define USART2_SYNCCTRL_FES_Msk                               (0x01UL << USART2_SYNCCTRL_FES_Pos)                       /*!< USART2 SYNCCTRL: FES Mask           */
-#define USART2_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART2 SYNCCTRL: TSBYPASS Position  */
-#define USART2_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART2 SYNCCTRL: TSBYPASS Mask      */
-#define USART2_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART2 SYNCCTRL: CSCEN Position     */
-#define USART2_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART2_SYNCCTRL_CSCEN_Pos)                     /*!< USART2 SYNCCTRL: CSCEN Mask         */
-#define USART2_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART2 SYNCCTRL: SSSDIS Position    */
-#define USART2_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos)                    /*!< USART2 SYNCCTRL: SSSDIS Mask        */
-#define USART2_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART2 SYNCCTRL: CCCLR Position     */
-#define USART2_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART2_SYNCCTRL_CCCLR_Pos)                     /*!< USART2 SYNCCTRL: CCCLR Mask         */
-
-// ---------------------------------------  USART2_TER  -------------------------------------------
-#define USART2_TER_TXEN_Pos                                   0                                                         /*!< USART2 TER: TXEN Position           */
-#define USART2_TER_TXEN_Msk                                   (0x01UL << USART2_TER_TXEN_Pos)                           /*!< USART2 TER: TXEN Mask               */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                USART3 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  USART3_DLL  -------------------------------------------
-#define USART3_DLL_DLLSB_Pos                                  0                                                         /*!< USART3 DLL: DLLSB Position          */
-#define USART3_DLL_DLLSB_Msk                                  (0x000000ffUL << USART3_DLL_DLLSB_Pos)                    /*!< USART3 DLL: DLLSB Mask              */
-
-// ---------------------------------------  USART3_THR  -------------------------------------------
-#define USART3_THR_THR_Pos                                    0                                                         /*!< USART3 THR: THR Position            */
-#define USART3_THR_THR_Msk                                    (0x000000ffUL << USART3_THR_THR_Pos)                      /*!< USART3 THR: THR Mask                */
-
-// ---------------------------------------  USART3_RBR  -------------------------------------------
-#define USART3_RBR_RBR_Pos                                    0                                                         /*!< USART3 RBR: RBR Position            */
-#define USART3_RBR_RBR_Msk                                    (0x000000ffUL << USART3_RBR_RBR_Pos)                      /*!< USART3 RBR: RBR Mask                */
-
-// ---------------------------------------  USART3_IER  -------------------------------------------
-#define USART3_IER_RBRIE_Pos                                  0                                                         /*!< USART3 IER: RBRIE Position          */
-#define USART3_IER_RBRIE_Msk                                  (0x01UL << USART3_IER_RBRIE_Pos)                          /*!< USART3 IER: RBRIE Mask              */
-#define USART3_IER_THREIE_Pos                                 1                                                         /*!< USART3 IER: THREIE Position         */
-#define USART3_IER_THREIE_Msk                                 (0x01UL << USART3_IER_THREIE_Pos)                         /*!< USART3 IER: THREIE Mask             */
-#define USART3_IER_RXIE_Pos                                   2                                                         /*!< USART3 IER: RXIE Position           */
-#define USART3_IER_RXIE_Msk                                   (0x01UL << USART3_IER_RXIE_Pos)                           /*!< USART3 IER: RXIE Mask               */
-#define USART3_IER_ABEOINTEN_Pos                              8                                                         /*!< USART3 IER: ABEOINTEN Position      */
-#define USART3_IER_ABEOINTEN_Msk                              (0x01UL << USART3_IER_ABEOINTEN_Pos)                      /*!< USART3 IER: ABEOINTEN Mask          */
-#define USART3_IER_ABTOINTEN_Pos                              9                                                         /*!< USART3 IER: ABTOINTEN Position      */
-#define USART3_IER_ABTOINTEN_Msk                              (0x01UL << USART3_IER_ABTOINTEN_Pos)                      /*!< USART3 IER: ABTOINTEN Mask          */
-
-// ---------------------------------------  USART3_DLM  -------------------------------------------
-#define USART3_DLM_DLMSB_Pos                                  0                                                         /*!< USART3 DLM: DLMSB Position          */
-#define USART3_DLM_DLMSB_Msk                                  (0x000000ffUL << USART3_DLM_DLMSB_Pos)                    /*!< USART3 DLM: DLMSB Mask              */
-
-// ---------------------------------------  USART3_FCR  -------------------------------------------
-#define USART3_FCR_FIFOEN_Pos                                 0                                                         /*!< USART3 FCR: FIFOEN Position         */
-#define USART3_FCR_FIFOEN_Msk                                 (0x01UL << USART3_FCR_FIFOEN_Pos)                         /*!< USART3 FCR: FIFOEN Mask             */
-#define USART3_FCR_RXFIFORES_Pos                              1                                                         /*!< USART3 FCR: RXFIFORES Position      */
-#define USART3_FCR_RXFIFORES_Msk                              (0x01UL << USART3_FCR_RXFIFORES_Pos)                      /*!< USART3 FCR: RXFIFORES Mask          */
-#define USART3_FCR_TXFIFORES_Pos                              2                                                         /*!< USART3 FCR: TXFIFORES Position      */
-#define USART3_FCR_TXFIFORES_Msk                              (0x01UL << USART3_FCR_TXFIFORES_Pos)                      /*!< USART3 FCR: TXFIFORES Mask          */
-#define USART3_FCR_DMAMODE_Pos                                3                                                         /*!< USART3 FCR: DMAMODE Position        */
-#define USART3_FCR_DMAMODE_Msk                                (0x01UL << USART3_FCR_DMAMODE_Pos)                        /*!< USART3 FCR: DMAMODE Mask            */
-#define USART3_FCR_RXTRIGLVL_Pos                              6                                                         /*!< USART3 FCR: RXTRIGLVL Position      */
-#define USART3_FCR_RXTRIGLVL_Msk                              (0x03UL << USART3_FCR_RXTRIGLVL_Pos)                      /*!< USART3 FCR: RXTRIGLVL Mask          */
-
-// ---------------------------------------  USART3_IIR  -------------------------------------------
-#define USART3_IIR_INTSTATUS_Pos                              0                                                         /*!< USART3 IIR: INTSTATUS Position      */
-#define USART3_IIR_INTSTATUS_Msk                              (0x01UL << USART3_IIR_INTSTATUS_Pos)                      /*!< USART3 IIR: INTSTATUS Mask          */
-#define USART3_IIR_INTID_Pos                                  1                                                         /*!< USART3 IIR: INTID Position          */
-#define USART3_IIR_INTID_Msk                                  (0x07UL << USART3_IIR_INTID_Pos)                          /*!< USART3 IIR: INTID Mask              */
-#define USART3_IIR_FIFOENABLE_Pos                             6                                                         /*!< USART3 IIR: FIFOENABLE Position     */
-#define USART3_IIR_FIFOENABLE_Msk                             (0x03UL << USART3_IIR_FIFOENABLE_Pos)                     /*!< USART3 IIR: FIFOENABLE Mask         */
-#define USART3_IIR_ABEOINT_Pos                                8                                                         /*!< USART3 IIR: ABEOINT Position        */
-#define USART3_IIR_ABEOINT_Msk                                (0x01UL << USART3_IIR_ABEOINT_Pos)                        /*!< USART3 IIR: ABEOINT Mask            */
-#define USART3_IIR_ABTOINT_Pos                                9                                                         /*!< USART3 IIR: ABTOINT Position        */
-#define USART3_IIR_ABTOINT_Msk                                (0x01UL << USART3_IIR_ABTOINT_Pos)                        /*!< USART3 IIR: ABTOINT Mask            */
-
-// ---------------------------------------  USART3_LCR  -------------------------------------------
-#define USART3_LCR_WLS_Pos                                    0                                                         /*!< USART3 LCR: WLS Position            */
-#define USART3_LCR_WLS_Msk                                    (0x03UL << USART3_LCR_WLS_Pos)                            /*!< USART3 LCR: WLS Mask                */
-#define USART3_LCR_SBS_Pos                                    2                                                         /*!< USART3 LCR: SBS Position            */
-#define USART3_LCR_SBS_Msk                                    (0x01UL << USART3_LCR_SBS_Pos)                            /*!< USART3 LCR: SBS Mask                */
-#define USART3_LCR_PE_Pos                                     3                                                         /*!< USART3 LCR: PE Position             */
-#define USART3_LCR_PE_Msk                                     (0x01UL << USART3_LCR_PE_Pos)                             /*!< USART3 LCR: PE Mask                 */
-#define USART3_LCR_PS_Pos                                     4                                                         /*!< USART3 LCR: PS Position             */
-#define USART3_LCR_PS_Msk                                     (0x03UL << USART3_LCR_PS_Pos)                             /*!< USART3 LCR: PS Mask                 */
-#define USART3_LCR_BC_Pos                                     6                                                         /*!< USART3 LCR: BC Position             */
-#define USART3_LCR_BC_Msk                                     (0x01UL << USART3_LCR_BC_Pos)                             /*!< USART3 LCR: BC Mask                 */
-#define USART3_LCR_DLAB_Pos                                   7                                                         /*!< USART3 LCR: DLAB Position           */
-#define USART3_LCR_DLAB_Msk                                   (0x01UL << USART3_LCR_DLAB_Pos)                           /*!< USART3 LCR: DLAB Mask               */
-
-// ---------------------------------------  USART3_LSR  -------------------------------------------
-#define USART3_LSR_RDR_Pos                                    0                                                         /*!< USART3 LSR: RDR Position            */
-#define USART3_LSR_RDR_Msk                                    (0x01UL << USART3_LSR_RDR_Pos)                            /*!< USART3 LSR: RDR Mask                */
-#define USART3_LSR_OE_Pos                                     1                                                         /*!< USART3 LSR: OE Position             */
-#define USART3_LSR_OE_Msk                                     (0x01UL << USART3_LSR_OE_Pos)                             /*!< USART3 LSR: OE Mask                 */
-#define USART3_LSR_PE_Pos                                     2                                                         /*!< USART3 LSR: PE Position             */
-#define USART3_LSR_PE_Msk                                     (0x01UL << USART3_LSR_PE_Pos)                             /*!< USART3 LSR: PE Mask                 */
-#define USART3_LSR_FE_Pos                                     3                                                         /*!< USART3 LSR: FE Position             */
-#define USART3_LSR_FE_Msk                                     (0x01UL << USART3_LSR_FE_Pos)                             /*!< USART3 LSR: FE Mask                 */
-#define USART3_LSR_BI_Pos                                     4                                                         /*!< USART3 LSR: BI Position             */
-#define USART3_LSR_BI_Msk                                     (0x01UL << USART3_LSR_BI_Pos)                             /*!< USART3 LSR: BI Mask                 */
-#define USART3_LSR_THRE_Pos                                   5                                                         /*!< USART3 LSR: THRE Position           */
-#define USART3_LSR_THRE_Msk                                   (0x01UL << USART3_LSR_THRE_Pos)                           /*!< USART3 LSR: THRE Mask               */
-#define USART3_LSR_TEMT_Pos                                   6                                                         /*!< USART3 LSR: TEMT Position           */
-#define USART3_LSR_TEMT_Msk                                   (0x01UL << USART3_LSR_TEMT_Pos)                           /*!< USART3 LSR: TEMT Mask               */
-#define USART3_LSR_RXFE_Pos                                   7                                                         /*!< USART3 LSR: RXFE Position           */
-#define USART3_LSR_RXFE_Msk                                   (0x01UL << USART3_LSR_RXFE_Pos)                           /*!< USART3 LSR: RXFE Mask               */
-#define USART3_LSR_TXERR_Pos                                  8                                                         /*!< USART3 LSR: TXERR Position          */
-#define USART3_LSR_TXERR_Msk                                  (0x01UL << USART3_LSR_TXERR_Pos)                          /*!< USART3 LSR: TXERR Mask              */
-
-// ---------------------------------------  USART3_SCR  -------------------------------------------
-#define USART3_SCR_PAD_Pos                                    0                                                         /*!< USART3 SCR: PAD Position            */
-#define USART3_SCR_PAD_Msk                                    (0x000000ffUL << USART3_SCR_PAD_Pos)                      /*!< USART3 SCR: PAD Mask                */
-
-// ---------------------------------------  USART3_ACR  -------------------------------------------
-#define USART3_ACR_START_Pos                                  0                                                         /*!< USART3 ACR: START Position          */
-#define USART3_ACR_START_Msk                                  (0x01UL << USART3_ACR_START_Pos)                          /*!< USART3 ACR: START Mask              */
-#define USART3_ACR_MODE_Pos                                   1                                                         /*!< USART3 ACR: MODE Position           */
-#define USART3_ACR_MODE_Msk                                   (0x01UL << USART3_ACR_MODE_Pos)                           /*!< USART3 ACR: MODE Mask               */
-#define USART3_ACR_AUTORESTART_Pos                            2                                                         /*!< USART3 ACR: AUTORESTART Position    */
-#define USART3_ACR_AUTORESTART_Msk                            (0x01UL << USART3_ACR_AUTORESTART_Pos)                    /*!< USART3 ACR: AUTORESTART Mask        */
-#define USART3_ACR_ABEOINTCLR_Pos                             8                                                         /*!< USART3 ACR: ABEOINTCLR Position     */
-#define USART3_ACR_ABEOINTCLR_Msk                             (0x01UL << USART3_ACR_ABEOINTCLR_Pos)                     /*!< USART3 ACR: ABEOINTCLR Mask         */
-#define USART3_ACR_ABTOINTCLR_Pos                             9                                                         /*!< USART3 ACR: ABTOINTCLR Position     */
-#define USART3_ACR_ABTOINTCLR_Msk                             (0x01UL << USART3_ACR_ABTOINTCLR_Pos)                     /*!< USART3 ACR: ABTOINTCLR Mask         */
-
-// ---------------------------------------  USART3_ICR  -------------------------------------------
-#define USART3_ICR_IRDAEN_Pos                                 0                                                         /*!< USART3 ICR: IRDAEN Position         */
-#define USART3_ICR_IRDAEN_Msk                                 (0x01UL << USART3_ICR_IRDAEN_Pos)                         /*!< USART3 ICR: IRDAEN Mask             */
-#define USART3_ICR_IRDAINV_Pos                                1                                                         /*!< USART3 ICR: IRDAINV Position        */
-#define USART3_ICR_IRDAINV_Msk                                (0x01UL << USART3_ICR_IRDAINV_Pos)                        /*!< USART3 ICR: IRDAINV Mask            */
-#define USART3_ICR_FIXPULSEEN_Pos                             2                                                         /*!< USART3 ICR: FIXPULSEEN Position     */
-#define USART3_ICR_FIXPULSEEN_Msk                             (0x01UL << USART3_ICR_FIXPULSEEN_Pos)                     /*!< USART3 ICR: FIXPULSEEN Mask         */
-#define USART3_ICR_PULSEDIV_Pos                               3                                                         /*!< USART3 ICR: PULSEDIV Position       */
-#define USART3_ICR_PULSEDIV_Msk                               (0x07UL << USART3_ICR_PULSEDIV_Pos)                       /*!< USART3 ICR: PULSEDIV Mask           */
-
-// ---------------------------------------  USART3_FDR  -------------------------------------------
-#define USART3_FDR_DIVADDVAL_Pos                              0                                                         /*!< USART3 FDR: DIVADDVAL Position      */
-#define USART3_FDR_DIVADDVAL_Msk                              (0x0fUL << USART3_FDR_DIVADDVAL_Pos)                      /*!< USART3 FDR: DIVADDVAL Mask          */
-#define USART3_FDR_MULVAL_Pos                                 4                                                         /*!< USART3 FDR: MULVAL Position         */
-#define USART3_FDR_MULVAL_Msk                                 (0x0fUL << USART3_FDR_MULVAL_Pos)                         /*!< USART3 FDR: MULVAL Mask             */
-
-// ---------------------------------------  USART3_OSR  -------------------------------------------
-#define USART3_OSR_OSFRAC_Pos                                 1                                                         /*!< USART3 OSR: OSFRAC Position         */
-#define USART3_OSR_OSFRAC_Msk                                 (0x07UL << USART3_OSR_OSFRAC_Pos)                         /*!< USART3 OSR: OSFRAC Mask             */
-#define USART3_OSR_OSINT_Pos                                  4                                                         /*!< USART3 OSR: OSINT Position          */
-#define USART3_OSR_OSINT_Msk                                  (0x0fUL << USART3_OSR_OSINT_Pos)                          /*!< USART3 OSR: OSINT Mask              */
-#define USART3_OSR_FDINT_Pos                                  8                                                         /*!< USART3 OSR: FDINT Position          */
-#define USART3_OSR_FDINT_Msk                                  (0x7fUL << USART3_OSR_FDINT_Pos)                          /*!< USART3 OSR: FDINT Mask              */
-
-// ---------------------------------------  USART3_HDEN  ------------------------------------------
-#define USART3_HDEN_HDEN_Pos                                  0                                                         /*!< USART3 HDEN: HDEN Position          */
-#define USART3_HDEN_HDEN_Msk                                  (0x01UL << USART3_HDEN_HDEN_Pos)                          /*!< USART3 HDEN: HDEN Mask              */
-
-// -------------------------------------  USART3_SCICTRL  -----------------------------------------
-#define USART3_SCICTRL_SCIEN_Pos                              0                                                         /*!< USART3 SCICTRL: SCIEN Position      */
-#define USART3_SCICTRL_SCIEN_Msk                              (0x01UL << USART3_SCICTRL_SCIEN_Pos)                      /*!< USART3 SCICTRL: SCIEN Mask          */
-#define USART3_SCICTRL_NACKDIS_Pos                            1                                                         /*!< USART3 SCICTRL: NACKDIS Position    */
-#define USART3_SCICTRL_NACKDIS_Msk                            (0x01UL << USART3_SCICTRL_NACKDIS_Pos)                    /*!< USART3 SCICTRL: NACKDIS Mask        */
-#define USART3_SCICTRL_PROTSEL_Pos                            2                                                         /*!< USART3 SCICTRL: PROTSEL Position    */
-#define USART3_SCICTRL_PROTSEL_Msk                            (0x01UL << USART3_SCICTRL_PROTSEL_Pos)                    /*!< USART3 SCICTRL: PROTSEL Mask        */
-#define USART3_SCICTRL_TXRETRY_Pos                            5                                                         /*!< USART3 SCICTRL: TXRETRY Position    */
-#define USART3_SCICTRL_TXRETRY_Msk                            (0x07UL << USART3_SCICTRL_TXRETRY_Pos)                    /*!< USART3 SCICTRL: TXRETRY Mask        */
-#define USART3_SCICTRL_GUARDTIME_Pos                          8                                                         /*!< USART3 SCICTRL: GUARDTIME Position  */
-#define USART3_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos)            /*!< USART3 SCICTRL: GUARDTIME Mask      */
-
-// ------------------------------------  USART3_RS485CTRL  ----------------------------------------
-#define USART3_RS485CTRL_NMMEN_Pos                            0                                                         /*!< USART3 RS485CTRL: NMMEN Position    */
-#define USART3_RS485CTRL_NMMEN_Msk                            (0x01UL << USART3_RS485CTRL_NMMEN_Pos)                    /*!< USART3 RS485CTRL: NMMEN Mask        */
-#define USART3_RS485CTRL_RXDIS_Pos                            1                                                         /*!< USART3 RS485CTRL: RXDIS Position    */
-#define USART3_RS485CTRL_RXDIS_Msk                            (0x01UL << USART3_RS485CTRL_RXDIS_Pos)                    /*!< USART3 RS485CTRL: RXDIS Mask        */
-#define USART3_RS485CTRL_AADEN_Pos                            2                                                         /*!< USART3 RS485CTRL: AADEN Position    */
-#define USART3_RS485CTRL_AADEN_Msk                            (0x01UL << USART3_RS485CTRL_AADEN_Pos)                    /*!< USART3 RS485CTRL: AADEN Mask        */
-#define USART3_RS485CTRL_DCTRL_Pos                            4                                                         /*!< USART3 RS485CTRL: DCTRL Position    */
-#define USART3_RS485CTRL_DCTRL_Msk                            (0x01UL << USART3_RS485CTRL_DCTRL_Pos)                    /*!< USART3 RS485CTRL: DCTRL Mask        */
-#define USART3_RS485CTRL_OINV_Pos                             5                                                         /*!< USART3 RS485CTRL: OINV Position     */
-#define USART3_RS485CTRL_OINV_Msk                             (0x01UL << USART3_RS485CTRL_OINV_Pos)                     /*!< USART3 RS485CTRL: OINV Mask         */
-
-// ----------------------------------  USART3_RS485ADRMATCH  --------------------------------------
-#define USART3_RS485ADRMATCH_ADRMATCH_Pos                     0                                                         /*!< USART3 RS485ADRMATCH: ADRMATCH Position */
-#define USART3_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos)       /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */
-
-// -------------------------------------  USART3_RS485DLY  ----------------------------------------
-#define USART3_RS485DLY_DLY_Pos                               0                                                         /*!< USART3 RS485DLY: DLY Position       */
-#define USART3_RS485DLY_DLY_Msk                               (0x000000ffUL << USART3_RS485DLY_DLY_Pos)                 /*!< USART3 RS485DLY: DLY Mask           */
-
-// -------------------------------------  USART3_SYNCCTRL  ----------------------------------------
-#define USART3_SYNCCTRL_SYNC_Pos                              0                                                         /*!< USART3 SYNCCTRL: SYNC Position      */
-#define USART3_SYNCCTRL_SYNC_Msk                              (0x01UL << USART3_SYNCCTRL_SYNC_Pos)                      /*!< USART3 SYNCCTRL: SYNC Mask          */
-#define USART3_SYNCCTRL_CSRC_Pos                              1                                                         /*!< USART3 SYNCCTRL: CSRC Position      */
-#define USART3_SYNCCTRL_CSRC_Msk                              (0x01UL << USART3_SYNCCTRL_CSRC_Pos)                      /*!< USART3 SYNCCTRL: CSRC Mask          */
-#define USART3_SYNCCTRL_FES_Pos                               2                                                         /*!< USART3 SYNCCTRL: FES Position       */
-#define USART3_SYNCCTRL_FES_Msk                               (0x01UL << USART3_SYNCCTRL_FES_Pos)                       /*!< USART3 SYNCCTRL: FES Mask           */
-#define USART3_SYNCCTRL_TSBYPASS_Pos                          3                                                         /*!< USART3 SYNCCTRL: TSBYPASS Position  */
-#define USART3_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos)                  /*!< USART3 SYNCCTRL: TSBYPASS Mask      */
-#define USART3_SYNCCTRL_CSCEN_Pos                             4                                                         /*!< USART3 SYNCCTRL: CSCEN Position     */
-#define USART3_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART3_SYNCCTRL_CSCEN_Pos)                     /*!< USART3 SYNCCTRL: CSCEN Mask         */
-#define USART3_SYNCCTRL_SSSDIS_Pos                            5                                                         /*!< USART3 SYNCCTRL: SSSDIS Position    */
-#define USART3_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos)                    /*!< USART3 SYNCCTRL: SSSDIS Mask        */
-#define USART3_SYNCCTRL_CCCLR_Pos                             6                                                         /*!< USART3 SYNCCTRL: CCCLR Position     */
-#define USART3_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART3_SYNCCTRL_CCCLR_Pos)                     /*!< USART3 SYNCCTRL: CCCLR Mask         */
-
-// ---------------------------------------  USART3_TER  -------------------------------------------
-#define USART3_TER_TXEN_Pos                                   0                                                         /*!< USART3 TER: TXEN Position           */
-#define USART3_TER_TXEN_Msk                                   (0x01UL << USART3_TER_TXEN_Pos)                           /*!< USART3 TER: TXEN Mask               */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 UART1 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  UART1_RBR  -------------------------------------------
-#define UART1_RBR_RBR_Pos                                     0                                                         /*!< UART1 RBR: RBR Position             */
-#define UART1_RBR_RBR_Msk                                     (0x000000ffUL << UART1_RBR_RBR_Pos)                       /*!< UART1 RBR: RBR Mask                 */
-
-// ----------------------------------------  UART1_THR  -------------------------------------------
-#define UART1_THR_THR_Pos                                     0                                                         /*!< UART1 THR: THR Position             */
-#define UART1_THR_THR_Msk                                     (0x000000ffUL << UART1_THR_THR_Pos)                       /*!< UART1 THR: THR Mask                 */
-
-// ----------------------------------------  UART1_DLL  -------------------------------------------
-#define UART1_DLL_DLLSB_Pos                                   0                                                         /*!< UART1 DLL: DLLSB Position           */
-#define UART1_DLL_DLLSB_Msk                                   (0x000000ffUL << UART1_DLL_DLLSB_Pos)                     /*!< UART1 DLL: DLLSB Mask               */
-
-// ----------------------------------------  UART1_DLM  -------------------------------------------
-#define UART1_DLM_DLMSB_Pos                                   0                                                         /*!< UART1 DLM: DLMSB Position           */
-#define UART1_DLM_DLMSB_Msk                                   (0x000000ffUL << UART1_DLM_DLMSB_Pos)                     /*!< UART1 DLM: DLMSB Mask               */
-
-// ----------------------------------------  UART1_IER  -------------------------------------------
-#define UART1_IER_RBRIE_Pos                                   0                                                         /*!< UART1 IER: RBRIE Position           */
-#define UART1_IER_RBRIE_Msk                                   (0x01UL << UART1_IER_RBRIE_Pos)                           /*!< UART1 IER: RBRIE Mask               */
-#define UART1_IER_THREIE_Pos                                  1                                                         /*!< UART1 IER: THREIE Position          */
-#define UART1_IER_THREIE_Msk                                  (0x01UL << UART1_IER_THREIE_Pos)                          /*!< UART1 IER: THREIE Mask              */
-#define UART1_IER_RXIE_Pos                                    2                                                         /*!< UART1 IER: RXIE Position            */
-#define UART1_IER_RXIE_Msk                                    (0x01UL << UART1_IER_RXIE_Pos)                            /*!< UART1 IER: RXIE Mask                */
-#define UART1_IER_MSIE_Pos                                    3                                                         /*!< UART1 IER: MSIE Position            */
-#define UART1_IER_MSIE_Msk                                    (0x01UL << UART1_IER_MSIE_Pos)                            /*!< UART1 IER: MSIE Mask                */
-#define UART1_IER_CTSIE_Pos                                   7                                                         /*!< UART1 IER: CTSIE Position           */
-#define UART1_IER_CTSIE_Msk                                   (0x01UL << UART1_IER_CTSIE_Pos)                           /*!< UART1 IER: CTSIE Mask               */
-#define UART1_IER_ABEOIE_Pos                                  8                                                         /*!< UART1 IER: ABEOIE Position          */
-#define UART1_IER_ABEOIE_Msk                                  (0x01UL << UART1_IER_ABEOIE_Pos)                          /*!< UART1 IER: ABEOIE Mask              */
-#define UART1_IER_ABTOIE_Pos                                  9                                                         /*!< UART1 IER: ABTOIE Position          */
-#define UART1_IER_ABTOIE_Msk                                  (0x01UL << UART1_IER_ABTOIE_Pos)                          /*!< UART1 IER: ABTOIE Mask              */
-
-// ----------------------------------------  UART1_IIR  -------------------------------------------
-#define UART1_IIR_INTSTATUS_Pos                               0                                                         /*!< UART1 IIR: INTSTATUS Position       */
-#define UART1_IIR_INTSTATUS_Msk                               (0x01UL << UART1_IIR_INTSTATUS_Pos)                       /*!< UART1 IIR: INTSTATUS Mask           */
-#define UART1_IIR_INTID_Pos                                   1                                                         /*!< UART1 IIR: INTID Position           */
-#define UART1_IIR_INTID_Msk                                   (0x07UL << UART1_IIR_INTID_Pos)                           /*!< UART1 IIR: INTID Mask               */
-#define UART1_IIR_FIFOENABLE_Pos                              6                                                         /*!< UART1 IIR: FIFOENABLE Position      */
-#define UART1_IIR_FIFOENABLE_Msk                              (0x03UL << UART1_IIR_FIFOENABLE_Pos)                      /*!< UART1 IIR: FIFOENABLE Mask          */
-#define UART1_IIR_ABEOINT_Pos                                 8                                                         /*!< UART1 IIR: ABEOINT Position         */
-#define UART1_IIR_ABEOINT_Msk                                 (0x01UL << UART1_IIR_ABEOINT_Pos)                         /*!< UART1 IIR: ABEOINT Mask             */
-#define UART1_IIR_ABTOINT_Pos                                 9                                                         /*!< UART1 IIR: ABTOINT Position         */
-#define UART1_IIR_ABTOINT_Msk                                 (0x01UL << UART1_IIR_ABTOINT_Pos)                         /*!< UART1 IIR: ABTOINT Mask             */
-
-// ----------------------------------------  UART1_FCR  -------------------------------------------
-#define UART1_FCR_FIFOEN_Pos                                  0                                                         /*!< UART1 FCR: FIFOEN Position          */
-#define UART1_FCR_FIFOEN_Msk                                  (0x01UL << UART1_FCR_FIFOEN_Pos)                          /*!< UART1 FCR: FIFOEN Mask              */
-#define UART1_FCR_RXFIFORES_Pos                               1                                                         /*!< UART1 FCR: RXFIFORES Position       */
-#define UART1_FCR_RXFIFORES_Msk                               (0x01UL << UART1_FCR_RXFIFORES_Pos)                       /*!< UART1 FCR: RXFIFORES Mask           */
-#define UART1_FCR_TXFIFORES_Pos                               2                                                         /*!< UART1 FCR: TXFIFORES Position       */
-#define UART1_FCR_TXFIFORES_Msk                               (0x01UL << UART1_FCR_TXFIFORES_Pos)                       /*!< UART1 FCR: TXFIFORES Mask           */
-#define UART1_FCR_DMAMODE_Pos                                 3                                                         /*!< UART1 FCR: DMAMODE Position         */
-#define UART1_FCR_DMAMODE_Msk                                 (0x01UL << UART1_FCR_DMAMODE_Pos)                         /*!< UART1 FCR: DMAMODE Mask             */
-#define UART1_FCR_RXTRIGLVL_Pos                               6                                                         /*!< UART1 FCR: RXTRIGLVL Position       */
-#define UART1_FCR_RXTRIGLVL_Msk                               (0x03UL << UART1_FCR_RXTRIGLVL_Pos)                       /*!< UART1 FCR: RXTRIGLVL Mask           */
-
-// ----------------------------------------  UART1_LCR  -------------------------------------------
-#define UART1_LCR_WLS_Pos                                     0                                                         /*!< UART1 LCR: WLS Position             */
-#define UART1_LCR_WLS_Msk                                     (0x03UL << UART1_LCR_WLS_Pos)                             /*!< UART1 LCR: WLS Mask                 */
-#define UART1_LCR_SBS_Pos                                     2                                                         /*!< UART1 LCR: SBS Position             */
-#define UART1_LCR_SBS_Msk                                     (0x01UL << UART1_LCR_SBS_Pos)                             /*!< UART1 LCR: SBS Mask                 */
-#define UART1_LCR_PE_Pos                                      3                                                         /*!< UART1 LCR: PE Position              */
-#define UART1_LCR_PE_Msk                                      (0x01UL << UART1_LCR_PE_Pos)                              /*!< UART1 LCR: PE Mask                  */
-#define UART1_LCR_PS_Pos                                      4                                                         /*!< UART1 LCR: PS Position              */
-#define UART1_LCR_PS_Msk                                      (0x03UL << UART1_LCR_PS_Pos)                              /*!< UART1 LCR: PS Mask                  */
-#define UART1_LCR_BC_Pos                                      6                                                         /*!< UART1 LCR: BC Position              */
-#define UART1_LCR_BC_Msk                                      (0x01UL << UART1_LCR_BC_Pos)                              /*!< UART1 LCR: BC Mask                  */
-#define UART1_LCR_DLAB_Pos                                    7                                                         /*!< UART1 LCR: DLAB Position            */
-#define UART1_LCR_DLAB_Msk                                    (0x01UL << UART1_LCR_DLAB_Pos)                            /*!< UART1 LCR: DLAB Mask                */
-
-// ----------------------------------------  UART1_MCR  -------------------------------------------
-#define UART1_MCR_DTRCTRL_Pos                                 0                                                         /*!< UART1 MCR: DTRCTRL Position         */
-#define UART1_MCR_DTRCTRL_Msk                                 (0x01UL << UART1_MCR_DTRCTRL_Pos)                         /*!< UART1 MCR: DTRCTRL Mask             */
-#define UART1_MCR_RTSCTRL_Pos                                 1                                                         /*!< UART1 MCR: RTSCTRL Position         */
-#define UART1_MCR_RTSCTRL_Msk                                 (0x01UL << UART1_MCR_RTSCTRL_Pos)                         /*!< UART1 MCR: RTSCTRL Mask             */
-#define UART1_MCR_LMS_Pos                                     4                                                         /*!< UART1 MCR: LMS Position             */
-#define UART1_MCR_LMS_Msk                                     (0x01UL << UART1_MCR_LMS_Pos)                             /*!< UART1 MCR: LMS Mask                 */
-#define UART1_MCR_RTSEN_Pos                                   6                                                         /*!< UART1 MCR: RTSEN Position           */
-#define UART1_MCR_RTSEN_Msk                                   (0x01UL << UART1_MCR_RTSEN_Pos)                           /*!< UART1 MCR: RTSEN Mask               */
-#define UART1_MCR_CTSEN_Pos                                   7                                                         /*!< UART1 MCR: CTSEN Position           */
-#define UART1_MCR_CTSEN_Msk                                   (0x01UL << UART1_MCR_CTSEN_Pos)                           /*!< UART1 MCR: CTSEN Mask               */
-
-// ----------------------------------------  UART1_LSR  -------------------------------------------
-#define UART1_LSR_RDR_Pos                                     0                                                         /*!< UART1 LSR: RDR Position             */
-#define UART1_LSR_RDR_Msk                                     (0x01UL << UART1_LSR_RDR_Pos)                             /*!< UART1 LSR: RDR Mask                 */
-#define UART1_LSR_OE_Pos                                      1                                                         /*!< UART1 LSR: OE Position              */
-#define UART1_LSR_OE_Msk                                      (0x01UL << UART1_LSR_OE_Pos)                              /*!< UART1 LSR: OE Mask                  */
-#define UART1_LSR_PE_Pos                                      2                                                         /*!< UART1 LSR: PE Position              */
-#define UART1_LSR_PE_Msk                                      (0x01UL << UART1_LSR_PE_Pos)                              /*!< UART1 LSR: PE Mask                  */
-#define UART1_LSR_FE_Pos                                      3                                                         /*!< UART1 LSR: FE Position              */
-#define UART1_LSR_FE_Msk                                      (0x01UL << UART1_LSR_FE_Pos)                              /*!< UART1 LSR: FE Mask                  */
-#define UART1_LSR_BI_Pos                                      4                                                         /*!< UART1 LSR: BI Position              */
-#define UART1_LSR_BI_Msk                                      (0x01UL << UART1_LSR_BI_Pos)                              /*!< UART1 LSR: BI Mask                  */
-#define UART1_LSR_THRE_Pos                                    5                                                         /*!< UART1 LSR: THRE Position            */
-#define UART1_LSR_THRE_Msk                                    (0x01UL << UART1_LSR_THRE_Pos)                            /*!< UART1 LSR: THRE Mask                */
-#define UART1_LSR_TEMT_Pos                                    6                                                         /*!< UART1 LSR: TEMT Position            */
-#define UART1_LSR_TEMT_Msk                                    (0x01UL << UART1_LSR_TEMT_Pos)                            /*!< UART1 LSR: TEMT Mask                */
-#define UART1_LSR_RXFE_Pos                                    7                                                         /*!< UART1 LSR: RXFE Position            */
-#define UART1_LSR_RXFE_Msk                                    (0x01UL << UART1_LSR_RXFE_Pos)                            /*!< UART1 LSR: RXFE Mask                */
-
-// ----------------------------------------  UART1_MSR  -------------------------------------------
-#define UART1_MSR_DCTS_Pos                                    0                                                         /*!< UART1 MSR: DCTS Position            */
-#define UART1_MSR_DCTS_Msk                                    (0x01UL << UART1_MSR_DCTS_Pos)                            /*!< UART1 MSR: DCTS Mask                */
-#define UART1_MSR_DDSR_Pos                                    1                                                         /*!< UART1 MSR: DDSR Position            */
-#define UART1_MSR_DDSR_Msk                                    (0x01UL << UART1_MSR_DDSR_Pos)                            /*!< UART1 MSR: DDSR Mask                */
-#define UART1_MSR_TERI_Pos                                    2                                                         /*!< UART1 MSR: TERI Position            */
-#define UART1_MSR_TERI_Msk                                    (0x01UL << UART1_MSR_TERI_Pos)                            /*!< UART1 MSR: TERI Mask                */
-#define UART1_MSR_DDCD_Pos                                    3                                                         /*!< UART1 MSR: DDCD Position            */
-#define UART1_MSR_DDCD_Msk                                    (0x01UL << UART1_MSR_DDCD_Pos)                            /*!< UART1 MSR: DDCD Mask                */
-#define UART1_MSR_CTS_Pos                                     4                                                         /*!< UART1 MSR: CTS Position             */
-#define UART1_MSR_CTS_Msk                                     (0x01UL << UART1_MSR_CTS_Pos)                             /*!< UART1 MSR: CTS Mask                 */
-#define UART1_MSR_DSR_Pos                                     5                                                         /*!< UART1 MSR: DSR Position             */
-#define UART1_MSR_DSR_Msk                                     (0x01UL << UART1_MSR_DSR_Pos)                             /*!< UART1 MSR: DSR Mask                 */
-#define UART1_MSR_RI_Pos                                      6                                                         /*!< UART1 MSR: RI Position              */
-#define UART1_MSR_RI_Msk                                      (0x01UL << UART1_MSR_RI_Pos)                              /*!< UART1 MSR: RI Mask                  */
-#define UART1_MSR_DCD_Pos                                     7                                                         /*!< UART1 MSR: DCD Position             */
-#define UART1_MSR_DCD_Msk                                     (0x01UL << UART1_MSR_DCD_Pos)                             /*!< UART1 MSR: DCD Mask                 */
-
-// ----------------------------------------  UART1_SCR  -------------------------------------------
-#define UART1_SCR_Pad_Pos                                     0                                                         /*!< UART1 SCR: Pad Position             */
-#define UART1_SCR_Pad_Msk                                     (0x000000ffUL << UART1_SCR_Pad_Pos)                       /*!< UART1 SCR: Pad Mask                 */
-
-// ----------------------------------------  UART1_ACR  -------------------------------------------
-#define UART1_ACR_START_Pos                                   0                                                         /*!< UART1 ACR: START Position           */
-#define UART1_ACR_START_Msk                                   (0x01UL << UART1_ACR_START_Pos)                           /*!< UART1 ACR: START Mask               */
-#define UART1_ACR_MODE_Pos                                    1                                                         /*!< UART1 ACR: MODE Position            */
-#define UART1_ACR_MODE_Msk                                    (0x01UL << UART1_ACR_MODE_Pos)                            /*!< UART1 ACR: MODE Mask                */
-#define UART1_ACR_AUTORESTART_Pos                             2                                                         /*!< UART1 ACR: AUTORESTART Position     */
-#define UART1_ACR_AUTORESTART_Msk                             (0x01UL << UART1_ACR_AUTORESTART_Pos)                     /*!< UART1 ACR: AUTORESTART Mask         */
-#define UART1_ACR_ABEOINTCLR_Pos                              8                                                         /*!< UART1 ACR: ABEOINTCLR Position      */
-#define UART1_ACR_ABEOINTCLR_Msk                              (0x01UL << UART1_ACR_ABEOINTCLR_Pos)                      /*!< UART1 ACR: ABEOINTCLR Mask          */
-#define UART1_ACR_ABTOINTCLR_Pos                              9                                                         /*!< UART1 ACR: ABTOINTCLR Position      */
-#define UART1_ACR_ABTOINTCLR_Msk                              (0x01UL << UART1_ACR_ABTOINTCLR_Pos)                      /*!< UART1 ACR: ABTOINTCLR Mask          */
-
-// ----------------------------------------  UART1_FDR  -------------------------------------------
-#define UART1_FDR_DIVADDVAL_Pos                               0                                                         /*!< UART1 FDR: DIVADDVAL Position       */
-#define UART1_FDR_DIVADDVAL_Msk                               (0x0fUL << UART1_FDR_DIVADDVAL_Pos)                       /*!< UART1 FDR: DIVADDVAL Mask           */
-#define UART1_FDR_MULVAL_Pos                                  4                                                         /*!< UART1 FDR: MULVAL Position          */
-#define UART1_FDR_MULVAL_Msk                                  (0x0fUL << UART1_FDR_MULVAL_Pos)                          /*!< UART1 FDR: MULVAL Mask              */
-
-// ----------------------------------------  UART1_TER  -------------------------------------------
-#define UART1_TER_TXEN_Pos                                    7                                                         /*!< UART1 TER: TXEN Position            */
-#define UART1_TER_TXEN_Msk                                    (0x01UL << UART1_TER_TXEN_Pos)                            /*!< UART1 TER: TXEN Mask                */
-
-// -------------------------------------  UART1_RS485CTRL  ----------------------------------------
-#define UART1_RS485CTRL_NMMEN_Pos                             0                                                         /*!< UART1 RS485CTRL: NMMEN Position     */
-#define UART1_RS485CTRL_NMMEN_Msk                             (0x01UL << UART1_RS485CTRL_NMMEN_Pos)                     /*!< UART1 RS485CTRL: NMMEN Mask         */
-#define UART1_RS485CTRL_RXDIS_Pos                             1                                                         /*!< UART1 RS485CTRL: RXDIS Position     */
-#define UART1_RS485CTRL_RXDIS_Msk                             (0x01UL << UART1_RS485CTRL_RXDIS_Pos)                     /*!< UART1 RS485CTRL: RXDIS Mask         */
-#define UART1_RS485CTRL_AADEN_Pos                             2                                                         /*!< UART1 RS485CTRL: AADEN Position     */
-#define UART1_RS485CTRL_AADEN_Msk                             (0x01UL << UART1_RS485CTRL_AADEN_Pos)                     /*!< UART1 RS485CTRL: AADEN Mask         */
-#define UART1_RS485CTRL_SEL_Pos                               3                                                         /*!< UART1 RS485CTRL: SEL Position       */
-#define UART1_RS485CTRL_SEL_Msk                               (0x01UL << UART1_RS485CTRL_SEL_Pos)                       /*!< UART1 RS485CTRL: SEL Mask           */
-#define UART1_RS485CTRL_DCTRL_Pos                             4                                                         /*!< UART1 RS485CTRL: DCTRL Position     */
-#define UART1_RS485CTRL_DCTRL_Msk                             (0x01UL << UART1_RS485CTRL_DCTRL_Pos)                     /*!< UART1 RS485CTRL: DCTRL Mask         */
-#define UART1_RS485CTRL_OINV_Pos                              5                                                         /*!< UART1 RS485CTRL: OINV Position      */
-#define UART1_RS485CTRL_OINV_Msk                              (0x01UL << UART1_RS485CTRL_OINV_Pos)                      /*!< UART1 RS485CTRL: OINV Mask          */
-
-// -----------------------------------  UART1_RS485ADRMATCH  --------------------------------------
-#define UART1_RS485ADRMATCH_ADRMATCH_Pos                      0                                                         /*!< UART1 RS485ADRMATCH: ADRMATCH Position */
-#define UART1_RS485ADRMATCH_ADRMATCH_Msk                      (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos)        /*!< UART1 RS485ADRMATCH: ADRMATCH Mask  */
-
-// -------------------------------------  UART1_RS485DLY  -----------------------------------------
-#define UART1_RS485DLY_DLY_Pos                                0                                                         /*!< UART1 RS485DLY: DLY Position        */
-#define UART1_RS485DLY_DLY_Msk                                (0x000000ffUL << UART1_RS485DLY_DLY_Pos)                  /*!< UART1 RS485DLY: DLY Mask            */
-
-// --------------------------------------  UART1_FIFOLVL  -----------------------------------------
-#define UART1_FIFOLVL_RXFIFILVL_Pos                           0                                                         /*!< UART1 FIFOLVL: RXFIFILVL Position   */
-#define UART1_FIFOLVL_RXFIFILVL_Msk                           (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos)                   /*!< UART1 FIFOLVL: RXFIFILVL Mask       */
-#define UART1_FIFOLVL_TXFIFOLVL_Pos                           8                                                         /*!< UART1 FIFOLVL: TXFIFOLVL Position   */
-#define UART1_FIFOLVL_TXFIFOLVL_Msk                           (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos)                   /*!< UART1 FIFOLVL: TXFIFOLVL Mask       */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 SSP0 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  SSP0_CR0  --------------------------------------------
-#define SSP0_CR0_DSS_Pos                                      0                                                         /*!< SSP0 CR0: DSS Position              */
-#define SSP0_CR0_DSS_Msk                                      (0x0fUL << SSP0_CR0_DSS_Pos)                              /*!< SSP0 CR0: DSS Mask                  */
-#define SSP0_CR0_FRF_Pos                                      4                                                         /*!< SSP0 CR0: FRF Position              */
-#define SSP0_CR0_FRF_Msk                                      (0x03UL << SSP0_CR0_FRF_Pos)                              /*!< SSP0 CR0: FRF Mask                  */
-#define SSP0_CR0_CPOL_Pos                                     6                                                         /*!< SSP0 CR0: CPOL Position             */
-#define SSP0_CR0_CPOL_Msk                                     (0x01UL << SSP0_CR0_CPOL_Pos)                             /*!< SSP0 CR0: CPOL Mask                 */
-#define SSP0_CR0_CPHA_Pos                                     7                                                         /*!< SSP0 CR0: CPHA Position             */
-#define SSP0_CR0_CPHA_Msk                                     (0x01UL << SSP0_CR0_CPHA_Pos)                             /*!< SSP0 CR0: CPHA Mask                 */
-#define SSP0_CR0_SCR_Pos                                      8                                                         /*!< SSP0 CR0: SCR Position              */
-#define SSP0_CR0_SCR_Msk                                      (0x000000ffUL << SSP0_CR0_SCR_Pos)                        /*!< SSP0 CR0: SCR Mask                  */
-
-// ----------------------------------------  SSP0_CR1  --------------------------------------------
-#define SSP0_CR1_LBM_Pos                                      0                                                         /*!< SSP0 CR1: LBM Position              */
-#define SSP0_CR1_LBM_Msk                                      (0x01UL << SSP0_CR1_LBM_Pos)                              /*!< SSP0 CR1: LBM Mask                  */
-#define SSP0_CR1_SSE_Pos                                      1                                                         /*!< SSP0 CR1: SSE Position              */
-#define SSP0_CR1_SSE_Msk                                      (0x01UL << SSP0_CR1_SSE_Pos)                              /*!< SSP0 CR1: SSE Mask                  */
-#define SSP0_CR1_MS_Pos                                       2                                                         /*!< SSP0 CR1: MS Position               */
-#define SSP0_CR1_MS_Msk                                       (0x01UL << SSP0_CR1_MS_Pos)                               /*!< SSP0 CR1: MS Mask                   */
-#define SSP0_CR1_SOD_Pos                                      3                                                         /*!< SSP0 CR1: SOD Position              */
-#define SSP0_CR1_SOD_Msk                                      (0x01UL << SSP0_CR1_SOD_Pos)                              /*!< SSP0 CR1: SOD Mask                  */
-
-// -----------------------------------------  SSP0_DR  --------------------------------------------
-#define SSP0_DR_DATA_Pos                                      0                                                         /*!< SSP0 DR: DATA Position              */
-#define SSP0_DR_DATA_Msk                                      (0x0000ffffUL << SSP0_DR_DATA_Pos)                        /*!< SSP0 DR: DATA Mask                  */
-
-// -----------------------------------------  SSP0_SR  --------------------------------------------
-#define SSP0_SR_TFE_Pos                                       0                                                         /*!< SSP0 SR: TFE Position               */
-#define SSP0_SR_TFE_Msk                                       (0x01UL << SSP0_SR_TFE_Pos)                               /*!< SSP0 SR: TFE Mask                   */
-#define SSP0_SR_TNF_Pos                                       1                                                         /*!< SSP0 SR: TNF Position               */
-#define SSP0_SR_TNF_Msk                                       (0x01UL << SSP0_SR_TNF_Pos)                               /*!< SSP0 SR: TNF Mask                   */
-#define SSP0_SR_RNE_Pos                                       2                                                         /*!< SSP0 SR: RNE Position               */
-#define SSP0_SR_RNE_Msk                                       (0x01UL << SSP0_SR_RNE_Pos)                               /*!< SSP0 SR: RNE Mask                   */
-#define SSP0_SR_RFF_Pos                                       3                                                         /*!< SSP0 SR: RFF Position               */
-#define SSP0_SR_RFF_Msk                                       (0x01UL << SSP0_SR_RFF_Pos)                               /*!< SSP0 SR: RFF Mask                   */
-#define SSP0_SR_BSY_Pos                                       4                                                         /*!< SSP0 SR: BSY Position               */
-#define SSP0_SR_BSY_Msk                                       (0x01UL << SSP0_SR_BSY_Pos)                               /*!< SSP0 SR: BSY Mask                   */
-
-// ----------------------------------------  SSP0_CPSR  -------------------------------------------
-#define SSP0_CPSR_CPSDVSR_Pos                                 0                                                         /*!< SSP0 CPSR: CPSDVSR Position         */
-#define SSP0_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos)                   /*!< SSP0 CPSR: CPSDVSR Mask             */
-
-// ----------------------------------------  SSP0_IMSC  -------------------------------------------
-#define SSP0_IMSC_RORIM_Pos                                   0                                                         /*!< SSP0 IMSC: RORIM Position           */
-#define SSP0_IMSC_RORIM_Msk                                   (0x01UL << SSP0_IMSC_RORIM_Pos)                           /*!< SSP0 IMSC: RORIM Mask               */
-#define SSP0_IMSC_RTIM_Pos                                    1                                                         /*!< SSP0 IMSC: RTIM Position            */
-#define SSP0_IMSC_RTIM_Msk                                    (0x01UL << SSP0_IMSC_RTIM_Pos)                            /*!< SSP0 IMSC: RTIM Mask                */
-#define SSP0_IMSC_RXIM_Pos                                    2                                                         /*!< SSP0 IMSC: RXIM Position            */
-#define SSP0_IMSC_RXIM_Msk                                    (0x01UL << SSP0_IMSC_RXIM_Pos)                            /*!< SSP0 IMSC: RXIM Mask                */
-#define SSP0_IMSC_TXIM_Pos                                    3                                                         /*!< SSP0 IMSC: TXIM Position            */
-#define SSP0_IMSC_TXIM_Msk                                    (0x01UL << SSP0_IMSC_TXIM_Pos)                            /*!< SSP0 IMSC: TXIM Mask                */
-
-// ----------------------------------------  SSP0_RIS  --------------------------------------------
-#define SSP0_RIS_RORRIS_Pos                                   0                                                         /*!< SSP0 RIS: RORRIS Position           */
-#define SSP0_RIS_RORRIS_Msk                                   (0x01UL << SSP0_RIS_RORRIS_Pos)                           /*!< SSP0 RIS: RORRIS Mask               */
-#define SSP0_RIS_RTRIS_Pos                                    1                                                         /*!< SSP0 RIS: RTRIS Position            */
-#define SSP0_RIS_RTRIS_Msk                                    (0x01UL << SSP0_RIS_RTRIS_Pos)                            /*!< SSP0 RIS: RTRIS Mask                */
-#define SSP0_RIS_RXRIS_Pos                                    2                                                         /*!< SSP0 RIS: RXRIS Position            */
-#define SSP0_RIS_RXRIS_Msk                                    (0x01UL << SSP0_RIS_RXRIS_Pos)                            /*!< SSP0 RIS: RXRIS Mask                */
-#define SSP0_RIS_TXRIS_Pos                                    3                                                         /*!< SSP0 RIS: TXRIS Position            */
-#define SSP0_RIS_TXRIS_Msk                                    (0x01UL << SSP0_RIS_TXRIS_Pos)                            /*!< SSP0 RIS: TXRIS Mask                */
-
-// ----------------------------------------  SSP0_MIS  --------------------------------------------
-#define SSP0_MIS_RORMIS_Pos                                   0                                                         /*!< SSP0 MIS: RORMIS Position           */
-#define SSP0_MIS_RORMIS_Msk                                   (0x01UL << SSP0_MIS_RORMIS_Pos)                           /*!< SSP0 MIS: RORMIS Mask               */
-#define SSP0_MIS_RTMIS_Pos                                    1                                                         /*!< SSP0 MIS: RTMIS Position            */
-#define SSP0_MIS_RTMIS_Msk                                    (0x01UL << SSP0_MIS_RTMIS_Pos)                            /*!< SSP0 MIS: RTMIS Mask                */
-#define SSP0_MIS_RXMIS_Pos                                    2                                                         /*!< SSP0 MIS: RXMIS Position            */
-#define SSP0_MIS_RXMIS_Msk                                    (0x01UL << SSP0_MIS_RXMIS_Pos)                            /*!< SSP0 MIS: RXMIS Mask                */
-#define SSP0_MIS_TXMIS_Pos                                    3                                                         /*!< SSP0 MIS: TXMIS Position            */
-#define SSP0_MIS_TXMIS_Msk                                    (0x01UL << SSP0_MIS_TXMIS_Pos)                            /*!< SSP0 MIS: TXMIS Mask                */
-
-// ----------------------------------------  SSP0_ICR  --------------------------------------------
-#define SSP0_ICR_RORIC_Pos                                    0                                                         /*!< SSP0 ICR: RORIC Position            */
-#define SSP0_ICR_RORIC_Msk                                    (0x01UL << SSP0_ICR_RORIC_Pos)                            /*!< SSP0 ICR: RORIC Mask                */
-#define SSP0_ICR_RTIC_Pos                                     1                                                         /*!< SSP0 ICR: RTIC Position             */
-#define SSP0_ICR_RTIC_Msk                                     (0x01UL << SSP0_ICR_RTIC_Pos)                             /*!< SSP0 ICR: RTIC Mask                 */
-
-// ---------------------------------------  SSP0_DMACR  -------------------------------------------
-#define SSP0_DMACR_RXDMAE_Pos                                 0                                                         /*!< SSP0 DMACR: RXDMAE Position         */
-#define SSP0_DMACR_RXDMAE_Msk                                 (0x01UL << SSP0_DMACR_RXDMAE_Pos)                         /*!< SSP0 DMACR: RXDMAE Mask             */
-#define SSP0_DMACR_TXDMAE_Pos                                 1                                                         /*!< SSP0 DMACR: TXDMAE Position         */
-#define SSP0_DMACR_TXDMAE_Msk                                 (0x01UL << SSP0_DMACR_TXDMAE_Pos)                         /*!< SSP0 DMACR: TXDMAE Mask             */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 SSP1 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  SSP1_CR0  --------------------------------------------
-#define SSP1_CR0_DSS_Pos                                      0                                                         /*!< SSP1 CR0: DSS Position              */
-#define SSP1_CR0_DSS_Msk                                      (0x0fUL << SSP1_CR0_DSS_Pos)                              /*!< SSP1 CR0: DSS Mask                  */
-#define SSP1_CR0_FRF_Pos                                      4                                                         /*!< SSP1 CR0: FRF Position              */
-#define SSP1_CR0_FRF_Msk                                      (0x03UL << SSP1_CR0_FRF_Pos)                              /*!< SSP1 CR0: FRF Mask                  */
-#define SSP1_CR0_CPOL_Pos                                     6                                                         /*!< SSP1 CR0: CPOL Position             */
-#define SSP1_CR0_CPOL_Msk                                     (0x01UL << SSP1_CR0_CPOL_Pos)                             /*!< SSP1 CR0: CPOL Mask                 */
-#define SSP1_CR0_CPHA_Pos                                     7                                                         /*!< SSP1 CR0: CPHA Position             */
-#define SSP1_CR0_CPHA_Msk                                     (0x01UL << SSP1_CR0_CPHA_Pos)                             /*!< SSP1 CR0: CPHA Mask                 */
-#define SSP1_CR0_SCR_Pos                                      8                                                         /*!< SSP1 CR0: SCR Position              */
-#define SSP1_CR0_SCR_Msk                                      (0x000000ffUL << SSP1_CR0_SCR_Pos)                        /*!< SSP1 CR0: SCR Mask                  */
-
-// ----------------------------------------  SSP1_CR1  --------------------------------------------
-#define SSP1_CR1_LBM_Pos                                      0                                                         /*!< SSP1 CR1: LBM Position              */
-#define SSP1_CR1_LBM_Msk                                      (0x01UL << SSP1_CR1_LBM_Pos)                              /*!< SSP1 CR1: LBM Mask                  */
-#define SSP1_CR1_SSE_Pos                                      1                                                         /*!< SSP1 CR1: SSE Position              */
-#define SSP1_CR1_SSE_Msk                                      (0x01UL << SSP1_CR1_SSE_Pos)                              /*!< SSP1 CR1: SSE Mask                  */
-#define SSP1_CR1_MS_Pos                                       2                                                         /*!< SSP1 CR1: MS Position               */
-#define SSP1_CR1_MS_Msk                                       (0x01UL << SSP1_CR1_MS_Pos)                               /*!< SSP1 CR1: MS Mask                   */
-#define SSP1_CR1_SOD_Pos                                      3                                                         /*!< SSP1 CR1: SOD Position              */
-#define SSP1_CR1_SOD_Msk                                      (0x01UL << SSP1_CR1_SOD_Pos)                              /*!< SSP1 CR1: SOD Mask                  */
-
-// -----------------------------------------  SSP1_DR  --------------------------------------------
-#define SSP1_DR_DATA_Pos                                      0                                                         /*!< SSP1 DR: DATA Position              */
-#define SSP1_DR_DATA_Msk                                      (0x0000ffffUL << SSP1_DR_DATA_Pos)                        /*!< SSP1 DR: DATA Mask                  */
-
-// -----------------------------------------  SSP1_SR  --------------------------------------------
-#define SSP1_SR_TFE_Pos                                       0                                                         /*!< SSP1 SR: TFE Position               */
-#define SSP1_SR_TFE_Msk                                       (0x01UL << SSP1_SR_TFE_Pos)                               /*!< SSP1 SR: TFE Mask                   */
-#define SSP1_SR_TNF_Pos                                       1                                                         /*!< SSP1 SR: TNF Position               */
-#define SSP1_SR_TNF_Msk                                       (0x01UL << SSP1_SR_TNF_Pos)                               /*!< SSP1 SR: TNF Mask                   */
-#define SSP1_SR_RNE_Pos                                       2                                                         /*!< SSP1 SR: RNE Position               */
-#define SSP1_SR_RNE_Msk                                       (0x01UL << SSP1_SR_RNE_Pos)                               /*!< SSP1 SR: RNE Mask                   */
-#define SSP1_SR_RFF_Pos                                       3                                                         /*!< SSP1 SR: RFF Position               */
-#define SSP1_SR_RFF_Msk                                       (0x01UL << SSP1_SR_RFF_Pos)                               /*!< SSP1 SR: RFF Mask                   */
-#define SSP1_SR_BSY_Pos                                       4                                                         /*!< SSP1 SR: BSY Position               */
-#define SSP1_SR_BSY_Msk                                       (0x01UL << SSP1_SR_BSY_Pos)                               /*!< SSP1 SR: BSY Mask                   */
-
-// ----------------------------------------  SSP1_CPSR  -------------------------------------------
-#define SSP1_CPSR_CPSDVSR_Pos                                 0                                                         /*!< SSP1 CPSR: CPSDVSR Position         */
-#define SSP1_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos)                   /*!< SSP1 CPSR: CPSDVSR Mask             */
-
-// ----------------------------------------  SSP1_IMSC  -------------------------------------------
-#define SSP1_IMSC_RORIM_Pos                                   0                                                         /*!< SSP1 IMSC: RORIM Position           */
-#define SSP1_IMSC_RORIM_Msk                                   (0x01UL << SSP1_IMSC_RORIM_Pos)                           /*!< SSP1 IMSC: RORIM Mask               */
-#define SSP1_IMSC_RTIM_Pos                                    1                                                         /*!< SSP1 IMSC: RTIM Position            */
-#define SSP1_IMSC_RTIM_Msk                                    (0x01UL << SSP1_IMSC_RTIM_Pos)                            /*!< SSP1 IMSC: RTIM Mask                */
-#define SSP1_IMSC_RXIM_Pos                                    2                                                         /*!< SSP1 IMSC: RXIM Position            */
-#define SSP1_IMSC_RXIM_Msk                                    (0x01UL << SSP1_IMSC_RXIM_Pos)                            /*!< SSP1 IMSC: RXIM Mask                */
-#define SSP1_IMSC_TXIM_Pos                                    3                                                         /*!< SSP1 IMSC: TXIM Position            */
-#define SSP1_IMSC_TXIM_Msk                                    (0x01UL << SSP1_IMSC_TXIM_Pos)                            /*!< SSP1 IMSC: TXIM Mask                */
-
-// ----------------------------------------  SSP1_RIS  --------------------------------------------
-#define SSP1_RIS_RORRIS_Pos                                   0                                                         /*!< SSP1 RIS: RORRIS Position           */
-#define SSP1_RIS_RORRIS_Msk                                   (0x01UL << SSP1_RIS_RORRIS_Pos)                           /*!< SSP1 RIS: RORRIS Mask               */
-#define SSP1_RIS_RTRIS_Pos                                    1                                                         /*!< SSP1 RIS: RTRIS Position            */
-#define SSP1_RIS_RTRIS_Msk                                    (0x01UL << SSP1_RIS_RTRIS_Pos)                            /*!< SSP1 RIS: RTRIS Mask                */
-#define SSP1_RIS_RXRIS_Pos                                    2                                                         /*!< SSP1 RIS: RXRIS Position            */
-#define SSP1_RIS_RXRIS_Msk                                    (0x01UL << SSP1_RIS_RXRIS_Pos)                            /*!< SSP1 RIS: RXRIS Mask                */
-#define SSP1_RIS_TXRIS_Pos                                    3                                                         /*!< SSP1 RIS: TXRIS Position            */
-#define SSP1_RIS_TXRIS_Msk                                    (0x01UL << SSP1_RIS_TXRIS_Pos)                            /*!< SSP1 RIS: TXRIS Mask                */
-
-// ----------------------------------------  SSP1_MIS  --------------------------------------------
-#define SSP1_MIS_RORMIS_Pos                                   0                                                         /*!< SSP1 MIS: RORMIS Position           */
-#define SSP1_MIS_RORMIS_Msk                                   (0x01UL << SSP1_MIS_RORMIS_Pos)                           /*!< SSP1 MIS: RORMIS Mask               */
-#define SSP1_MIS_RTMIS_Pos                                    1                                                         /*!< SSP1 MIS: RTMIS Position            */
-#define SSP1_MIS_RTMIS_Msk                                    (0x01UL << SSP1_MIS_RTMIS_Pos)                            /*!< SSP1 MIS: RTMIS Mask                */
-#define SSP1_MIS_RXMIS_Pos                                    2                                                         /*!< SSP1 MIS: RXMIS Position            */
-#define SSP1_MIS_RXMIS_Msk                                    (0x01UL << SSP1_MIS_RXMIS_Pos)                            /*!< SSP1 MIS: RXMIS Mask                */
-#define SSP1_MIS_TXMIS_Pos                                    3                                                         /*!< SSP1 MIS: TXMIS Position            */
-#define SSP1_MIS_TXMIS_Msk                                    (0x01UL << SSP1_MIS_TXMIS_Pos)                            /*!< SSP1 MIS: TXMIS Mask                */
-
-// ----------------------------------------  SSP1_ICR  --------------------------------------------
-#define SSP1_ICR_RORIC_Pos                                    0                                                         /*!< SSP1 ICR: RORIC Position            */
-#define SSP1_ICR_RORIC_Msk                                    (0x01UL << SSP1_ICR_RORIC_Pos)                            /*!< SSP1 ICR: RORIC Mask                */
-#define SSP1_ICR_RTIC_Pos                                     1                                                         /*!< SSP1 ICR: RTIC Position             */
-#define SSP1_ICR_RTIC_Msk                                     (0x01UL << SSP1_ICR_RTIC_Pos)                             /*!< SSP1 ICR: RTIC Mask                 */
-
-// ---------------------------------------  SSP1_DMACR  -------------------------------------------
-#define SSP1_DMACR_RXDMAE_Pos                                 0                                                         /*!< SSP1 DMACR: RXDMAE Position         */
-#define SSP1_DMACR_RXDMAE_Msk                                 (0x01UL << SSP1_DMACR_RXDMAE_Pos)                         /*!< SSP1 DMACR: RXDMAE Mask             */
-#define SSP1_DMACR_TXDMAE_Pos                                 1                                                         /*!< SSP1 DMACR: TXDMAE Position         */
-#define SSP1_DMACR_TXDMAE_Msk                                 (0x01UL << SSP1_DMACR_TXDMAE_Pos)                         /*!< SSP1 DMACR: TXDMAE Mask             */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                TIMER0 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  TIMER0_IR  -------------------------------------------
-#define TIMER0_IR_MR0INT_Pos                                  0                                                         /*!< TIMER0 IR: MR0INT Position          */
-#define TIMER0_IR_MR0INT_Msk                                  (0x01UL << TIMER0_IR_MR0INT_Pos)                          /*!< TIMER0 IR: MR0INT Mask              */
-#define TIMER0_IR_MR1INT_Pos                                  1                                                         /*!< TIMER0 IR: MR1INT Position          */
-#define TIMER0_IR_MR1INT_Msk                                  (0x01UL << TIMER0_IR_MR1INT_Pos)                          /*!< TIMER0 IR: MR1INT Mask              */
-#define TIMER0_IR_MR2INT_Pos                                  2                                                         /*!< TIMER0 IR: MR2INT Position          */
-#define TIMER0_IR_MR2INT_Msk                                  (0x01UL << TIMER0_IR_MR2INT_Pos)                          /*!< TIMER0 IR: MR2INT Mask              */
-#define TIMER0_IR_MR3INT_Pos                                  3                                                         /*!< TIMER0 IR: MR3INT Position          */
-#define TIMER0_IR_MR3INT_Msk                                  (0x01UL << TIMER0_IR_MR3INT_Pos)                          /*!< TIMER0 IR: MR3INT Mask              */
-#define TIMER0_IR_CR0INT_Pos                                  4                                                         /*!< TIMER0 IR: CR0INT Position          */
-#define TIMER0_IR_CR0INT_Msk                                  (0x01UL << TIMER0_IR_CR0INT_Pos)                          /*!< TIMER0 IR: CR0INT Mask              */
-#define TIMER0_IR_CR1INT_Pos                                  5                                                         /*!< TIMER0 IR: CR1INT Position          */
-#define TIMER0_IR_CR1INT_Msk                                  (0x01UL << TIMER0_IR_CR1INT_Pos)                          /*!< TIMER0 IR: CR1INT Mask              */
-#define TIMER0_IR_CR2INT_Pos                                  6                                                         /*!< TIMER0 IR: CR2INT Position          */
-#define TIMER0_IR_CR2INT_Msk                                  (0x01UL << TIMER0_IR_CR2INT_Pos)                          /*!< TIMER0 IR: CR2INT Mask              */
-#define TIMER0_IR_CR3INT_Pos                                  7                                                         /*!< TIMER0 IR: CR3INT Position          */
-#define TIMER0_IR_CR3INT_Msk                                  (0x01UL << TIMER0_IR_CR3INT_Pos)                          /*!< TIMER0 IR: CR3INT Mask              */
-
-// ---------------------------------------  TIMER0_TCR  -------------------------------------------
-#define TIMER0_TCR_CEN_Pos                                    0                                                         /*!< TIMER0 TCR: CEN Position            */
-#define TIMER0_TCR_CEN_Msk                                    (0x01UL << TIMER0_TCR_CEN_Pos)                            /*!< TIMER0 TCR: CEN Mask                */
-#define TIMER0_TCR_CRST_Pos                                   1                                                         /*!< TIMER0 TCR: CRST Position           */
-#define TIMER0_TCR_CRST_Msk                                   (0x01UL << TIMER0_TCR_CRST_Pos)                           /*!< TIMER0 TCR: CRST Mask               */
-
-// ----------------------------------------  TIMER0_TC  -------------------------------------------
-#define TIMER0_TC_TC_Pos                                      0                                                         /*!< TIMER0 TC: TC Position              */
-#define TIMER0_TC_TC_Msk                                      (0xffffffffUL << TIMER0_TC_TC_Pos)                        /*!< TIMER0 TC: TC Mask                  */
-
-// ----------------------------------------  TIMER0_PR  -------------------------------------------
-#define TIMER0_PR_PM_Pos                                      0                                                         /*!< TIMER0 PR: PM Position              */
-#define TIMER0_PR_PM_Msk                                      (0xffffffffUL << TIMER0_PR_PM_Pos)                        /*!< TIMER0 PR: PM Mask                  */
-
-// ----------------------------------------  TIMER0_PC  -------------------------------------------
-#define TIMER0_PC_PC_Pos                                      0                                                         /*!< TIMER0 PC: PC Position              */
-#define TIMER0_PC_PC_Msk                                      (0xffffffffUL << TIMER0_PC_PC_Pos)                        /*!< TIMER0 PC: PC Mask                  */
-
-// ---------------------------------------  TIMER0_MCR  -------------------------------------------
-#define TIMER0_MCR_MR0I_Pos                                   0                                                         /*!< TIMER0 MCR: MR0I Position           */
-#define TIMER0_MCR_MR0I_Msk                                   (0x01UL << TIMER0_MCR_MR0I_Pos)                           /*!< TIMER0 MCR: MR0I Mask               */
-#define TIMER0_MCR_MR0R_Pos                                   1                                                         /*!< TIMER0 MCR: MR0R Position           */
-#define TIMER0_MCR_MR0R_Msk                                   (0x01UL << TIMER0_MCR_MR0R_Pos)                           /*!< TIMER0 MCR: MR0R Mask               */
-#define TIMER0_MCR_MR0S_Pos                                   2                                                         /*!< TIMER0 MCR: MR0S Position           */
-#define TIMER0_MCR_MR0S_Msk                                   (0x01UL << TIMER0_MCR_MR0S_Pos)                           /*!< TIMER0 MCR: MR0S Mask               */
-#define TIMER0_MCR_MR1I_Pos                                   3                                                         /*!< TIMER0 MCR: MR1I Position           */
-#define TIMER0_MCR_MR1I_Msk                                   (0x01UL << TIMER0_MCR_MR1I_Pos)                           /*!< TIMER0 MCR: MR1I Mask               */
-#define TIMER0_MCR_MR1R_Pos                                   4                                                         /*!< TIMER0 MCR: MR1R Position           */
-#define TIMER0_MCR_MR1R_Msk                                   (0x01UL << TIMER0_MCR_MR1R_Pos)                           /*!< TIMER0 MCR: MR1R Mask               */
-#define TIMER0_MCR_MR1S_Pos                                   5                                                         /*!< TIMER0 MCR: MR1S Position           */
-#define TIMER0_MCR_MR1S_Msk                                   (0x01UL << TIMER0_MCR_MR1S_Pos)                           /*!< TIMER0 MCR: MR1S Mask               */
-#define TIMER0_MCR_MR2I_Pos                                   6                                                         /*!< TIMER0 MCR: MR2I Position           */
-#define TIMER0_MCR_MR2I_Msk                                   (0x01UL << TIMER0_MCR_MR2I_Pos)                           /*!< TIMER0 MCR: MR2I Mask               */
-#define TIMER0_MCR_MR2R_Pos                                   7                                                         /*!< TIMER0 MCR: MR2R Position           */
-#define TIMER0_MCR_MR2R_Msk                                   (0x01UL << TIMER0_MCR_MR2R_Pos)                           /*!< TIMER0 MCR: MR2R Mask               */
-#define TIMER0_MCR_MR2S_Pos                                   8                                                         /*!< TIMER0 MCR: MR2S Position           */
-#define TIMER0_MCR_MR2S_Msk                                   (0x01UL << TIMER0_MCR_MR2S_Pos)                           /*!< TIMER0 MCR: MR2S Mask               */
-#define TIMER0_MCR_MR3I_Pos                                   9                                                         /*!< TIMER0 MCR: MR3I Position           */
-#define TIMER0_MCR_MR3I_Msk                                   (0x01UL << TIMER0_MCR_MR3I_Pos)                           /*!< TIMER0 MCR: MR3I Mask               */
-#define TIMER0_MCR_MR3R_Pos                                   10                                                        /*!< TIMER0 MCR: MR3R Position           */
-#define TIMER0_MCR_MR3R_Msk                                   (0x01UL << TIMER0_MCR_MR3R_Pos)                           /*!< TIMER0 MCR: MR3R Mask               */
-#define TIMER0_MCR_MR3S_Pos                                   11                                                        /*!< TIMER0 MCR: MR3S Position           */
-#define TIMER0_MCR_MR3S_Msk                                   (0x01UL << TIMER0_MCR_MR3S_Pos)                           /*!< TIMER0 MCR: MR3S Mask               */
-
-// ---------------------------------------  TIMER0_MR0  -------------------------------------------
-#define TIMER0_MR0_MATCH_Pos                                  0                                                         /*!< TIMER0 MR0: MATCH Position          */
-#define TIMER0_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR0_MATCH_Pos)                    /*!< TIMER0 MR0: MATCH Mask              */
-
-// ---------------------------------------  TIMER0_MR1  -------------------------------------------
-#define TIMER0_MR1_MATCH_Pos                                  0                                                         /*!< TIMER0 MR1: MATCH Position          */
-#define TIMER0_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR1_MATCH_Pos)                    /*!< TIMER0 MR1: MATCH Mask              */
-
-// ---------------------------------------  TIMER0_MR2  -------------------------------------------
-#define TIMER0_MR2_MATCH_Pos                                  0                                                         /*!< TIMER0 MR2: MATCH Position          */
-#define TIMER0_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR2_MATCH_Pos)                    /*!< TIMER0 MR2: MATCH Mask              */
-
-// ---------------------------------------  TIMER0_MR3  -------------------------------------------
-#define TIMER0_MR3_MATCH_Pos                                  0                                                         /*!< TIMER0 MR3: MATCH Position          */
-#define TIMER0_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR3_MATCH_Pos)                    /*!< TIMER0 MR3: MATCH Mask              */
-
-// ---------------------------------------  TIMER0_CCR  -------------------------------------------
-#define TIMER0_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER0 CCR: CAP0RE Position         */
-#define TIMER0_CCR_CAP0RE_Msk                                 (0x01UL << TIMER0_CCR_CAP0RE_Pos)                         /*!< TIMER0 CCR: CAP0RE Mask             */
-#define TIMER0_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER0 CCR: CAP0FE Position         */
-#define TIMER0_CCR_CAP0FE_Msk                                 (0x01UL << TIMER0_CCR_CAP0FE_Pos)                         /*!< TIMER0 CCR: CAP0FE Mask             */
-#define TIMER0_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER0 CCR: CAP0I Position          */
-#define TIMER0_CCR_CAP0I_Msk                                  (0x01UL << TIMER0_CCR_CAP0I_Pos)                          /*!< TIMER0 CCR: CAP0I Mask              */
-#define TIMER0_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER0 CCR: CAP1RE Position         */
-#define TIMER0_CCR_CAP1RE_Msk                                 (0x01UL << TIMER0_CCR_CAP1RE_Pos)                         /*!< TIMER0 CCR: CAP1RE Mask             */
-#define TIMER0_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER0 CCR: CAP1FE Position         */
-#define TIMER0_CCR_CAP1FE_Msk                                 (0x01UL << TIMER0_CCR_CAP1FE_Pos)                         /*!< TIMER0 CCR: CAP1FE Mask             */
-#define TIMER0_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER0 CCR: CAP1I Position          */
-#define TIMER0_CCR_CAP1I_Msk                                  (0x01UL << TIMER0_CCR_CAP1I_Pos)                          /*!< TIMER0 CCR: CAP1I Mask              */
-#define TIMER0_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER0 CCR: CAP2RE Position         */
-#define TIMER0_CCR_CAP2RE_Msk                                 (0x01UL << TIMER0_CCR_CAP2RE_Pos)                         /*!< TIMER0 CCR: CAP2RE Mask             */
-#define TIMER0_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER0 CCR: CAP2FE Position         */
-#define TIMER0_CCR_CAP2FE_Msk                                 (0x01UL << TIMER0_CCR_CAP2FE_Pos)                         /*!< TIMER0 CCR: CAP2FE Mask             */
-#define TIMER0_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER0 CCR: CAP2I Position          */
-#define TIMER0_CCR_CAP2I_Msk                                  (0x01UL << TIMER0_CCR_CAP2I_Pos)                          /*!< TIMER0 CCR: CAP2I Mask              */
-#define TIMER0_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER0 CCR: CAP3RE Position         */
-#define TIMER0_CCR_CAP3RE_Msk                                 (0x01UL << TIMER0_CCR_CAP3RE_Pos)                         /*!< TIMER0 CCR: CAP3RE Mask             */
-#define TIMER0_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER0 CCR: CAP3FE Position         */
-#define TIMER0_CCR_CAP3FE_Msk                                 (0x01UL << TIMER0_CCR_CAP3FE_Pos)                         /*!< TIMER0 CCR: CAP3FE Mask             */
-#define TIMER0_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER0 CCR: CAP3I Position          */
-#define TIMER0_CCR_CAP3I_Msk                                  (0x01UL << TIMER0_CCR_CAP3I_Pos)                          /*!< TIMER0 CCR: CAP3I Mask              */
-
-// ---------------------------------------  TIMER0_CR0  -------------------------------------------
-#define TIMER0_CR0_CAP_Pos                                    0                                                         /*!< TIMER0 CR0: CAP Position            */
-#define TIMER0_CR0_CAP_Msk                                    (0xffffffffUL << TIMER0_CR0_CAP_Pos)                      /*!< TIMER0 CR0: CAP Mask                */
-
-// ---------------------------------------  TIMER0_CR1  -------------------------------------------
-#define TIMER0_CR1_CAP_Pos                                    0                                                         /*!< TIMER0 CR1: CAP Position            */
-#define TIMER0_CR1_CAP_Msk                                    (0xffffffffUL << TIMER0_CR1_CAP_Pos)                      /*!< TIMER0 CR1: CAP Mask                */
-
-// ---------------------------------------  TIMER0_CR2  -------------------------------------------
-#define TIMER0_CR2_CAP_Pos                                    0                                                         /*!< TIMER0 CR2: CAP Position            */
-#define TIMER0_CR2_CAP_Msk                                    (0xffffffffUL << TIMER0_CR2_CAP_Pos)                      /*!< TIMER0 CR2: CAP Mask                */
-
-// ---------------------------------------  TIMER0_CR3  -------------------------------------------
-#define TIMER0_CR3_CAP_Pos                                    0                                                         /*!< TIMER0 CR3: CAP Position            */
-#define TIMER0_CR3_CAP_Msk                                    (0xffffffffUL << TIMER0_CR3_CAP_Pos)                      /*!< TIMER0 CR3: CAP Mask                */
-
-// ---------------------------------------  TIMER0_EMR  -------------------------------------------
-#define TIMER0_EMR_EM0_Pos                                    0                                                         /*!< TIMER0 EMR: EM0 Position            */
-#define TIMER0_EMR_EM0_Msk                                    (0x01UL << TIMER0_EMR_EM0_Pos)                            /*!< TIMER0 EMR: EM0 Mask                */
-#define TIMER0_EMR_EM1_Pos                                    1                                                         /*!< TIMER0 EMR: EM1 Position            */
-#define TIMER0_EMR_EM1_Msk                                    (0x01UL << TIMER0_EMR_EM1_Pos)                            /*!< TIMER0 EMR: EM1 Mask                */
-#define TIMER0_EMR_EM2_Pos                                    2                                                         /*!< TIMER0 EMR: EM2 Position            */
-#define TIMER0_EMR_EM2_Msk                                    (0x01UL << TIMER0_EMR_EM2_Pos)                            /*!< TIMER0 EMR: EM2 Mask                */
-#define TIMER0_EMR_EM3_Pos                                    3                                                         /*!< TIMER0 EMR: EM3 Position            */
-#define TIMER0_EMR_EM3_Msk                                    (0x01UL << TIMER0_EMR_EM3_Pos)                            /*!< TIMER0 EMR: EM3 Mask                */
-#define TIMER0_EMR_EMC0_Pos                                   4                                                         /*!< TIMER0 EMR: EMC0 Position           */
-#define TIMER0_EMR_EMC0_Msk                                   (0x03UL << TIMER0_EMR_EMC0_Pos)                           /*!< TIMER0 EMR: EMC0 Mask               */
-#define TIMER0_EMR_EMC1_Pos                                   6                                                         /*!< TIMER0 EMR: EMC1 Position           */
-#define TIMER0_EMR_EMC1_Msk                                   (0x03UL << TIMER0_EMR_EMC1_Pos)                           /*!< TIMER0 EMR: EMC1 Mask               */
-#define TIMER0_EMR_EMC2_Pos                                   8                                                         /*!< TIMER0 EMR: EMC2 Position           */
-#define TIMER0_EMR_EMC2_Msk                                   (0x03UL << TIMER0_EMR_EMC2_Pos)                           /*!< TIMER0 EMR: EMC2 Mask               */
-#define TIMER0_EMR_EMC3_Pos                                   10                                                        /*!< TIMER0 EMR: EMC3 Position           */
-#define TIMER0_EMR_EMC3_Msk                                   (0x03UL << TIMER0_EMR_EMC3_Pos)                           /*!< TIMER0 EMR: EMC3 Mask               */
-
-// ---------------------------------------  TIMER0_CTCR  ------------------------------------------
-#define TIMER0_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER0 CTCR: CTMODE Position        */
-#define TIMER0_CTCR_CTMODE_Msk                                (0x03UL << TIMER0_CTCR_CTMODE_Pos)                        /*!< TIMER0 CTCR: CTMODE Mask            */
-#define TIMER0_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER0 CTCR: CINSEL Position        */
-#define TIMER0_CTCR_CINSEL_Msk                                (0x03UL << TIMER0_CTCR_CINSEL_Pos)                        /*!< TIMER0 CTCR: CINSEL Mask            */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                TIMER1 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  TIMER1_IR  -------------------------------------------
-#define TIMER1_IR_MR0INT_Pos                                  0                                                         /*!< TIMER1 IR: MR0INT Position          */
-#define TIMER1_IR_MR0INT_Msk                                  (0x01UL << TIMER1_IR_MR0INT_Pos)                          /*!< TIMER1 IR: MR0INT Mask              */
-#define TIMER1_IR_MR1INT_Pos                                  1                                                         /*!< TIMER1 IR: MR1INT Position          */
-#define TIMER1_IR_MR1INT_Msk                                  (0x01UL << TIMER1_IR_MR1INT_Pos)                          /*!< TIMER1 IR: MR1INT Mask              */
-#define TIMER1_IR_MR2INT_Pos                                  2                                                         /*!< TIMER1 IR: MR2INT Position          */
-#define TIMER1_IR_MR2INT_Msk                                  (0x01UL << TIMER1_IR_MR2INT_Pos)                          /*!< TIMER1 IR: MR2INT Mask              */
-#define TIMER1_IR_MR3INT_Pos                                  3                                                         /*!< TIMER1 IR: MR3INT Position          */
-#define TIMER1_IR_MR3INT_Msk                                  (0x01UL << TIMER1_IR_MR3INT_Pos)                          /*!< TIMER1 IR: MR3INT Mask              */
-#define TIMER1_IR_CR0INT_Pos                                  4                                                         /*!< TIMER1 IR: CR0INT Position          */
-#define TIMER1_IR_CR0INT_Msk                                  (0x01UL << TIMER1_IR_CR0INT_Pos)                          /*!< TIMER1 IR: CR0INT Mask              */
-#define TIMER1_IR_CR1INT_Pos                                  5                                                         /*!< TIMER1 IR: CR1INT Position          */
-#define TIMER1_IR_CR1INT_Msk                                  (0x01UL << TIMER1_IR_CR1INT_Pos)                          /*!< TIMER1 IR: CR1INT Mask              */
-#define TIMER1_IR_CR2INT_Pos                                  6                                                         /*!< TIMER1 IR: CR2INT Position          */
-#define TIMER1_IR_CR2INT_Msk                                  (0x01UL << TIMER1_IR_CR2INT_Pos)                          /*!< TIMER1 IR: CR2INT Mask              */
-#define TIMER1_IR_CR3INT_Pos                                  7                                                         /*!< TIMER1 IR: CR3INT Position          */
-#define TIMER1_IR_CR3INT_Msk                                  (0x01UL << TIMER1_IR_CR3INT_Pos)                          /*!< TIMER1 IR: CR3INT Mask              */
-
-// ---------------------------------------  TIMER1_TCR  -------------------------------------------
-#define TIMER1_TCR_CEN_Pos                                    0                                                         /*!< TIMER1 TCR: CEN Position            */
-#define TIMER1_TCR_CEN_Msk                                    (0x01UL << TIMER1_TCR_CEN_Pos)                            /*!< TIMER1 TCR: CEN Mask                */
-#define TIMER1_TCR_CRST_Pos                                   1                                                         /*!< TIMER1 TCR: CRST Position           */
-#define TIMER1_TCR_CRST_Msk                                   (0x01UL << TIMER1_TCR_CRST_Pos)                           /*!< TIMER1 TCR: CRST Mask               */
-
-// ----------------------------------------  TIMER1_TC  -------------------------------------------
-#define TIMER1_TC_TC_Pos                                      0                                                         /*!< TIMER1 TC: TC Position              */
-#define TIMER1_TC_TC_Msk                                      (0xffffffffUL << TIMER1_TC_TC_Pos)                        /*!< TIMER1 TC: TC Mask                  */
-
-// ----------------------------------------  TIMER1_PR  -------------------------------------------
-#define TIMER1_PR_PM_Pos                                      0                                                         /*!< TIMER1 PR: PM Position              */
-#define TIMER1_PR_PM_Msk                                      (0xffffffffUL << TIMER1_PR_PM_Pos)                        /*!< TIMER1 PR: PM Mask                  */
-
-// ----------------------------------------  TIMER1_PC  -------------------------------------------
-#define TIMER1_PC_PC_Pos                                      0                                                         /*!< TIMER1 PC: PC Position              */
-#define TIMER1_PC_PC_Msk                                      (0xffffffffUL << TIMER1_PC_PC_Pos)                        /*!< TIMER1 PC: PC Mask                  */
-
-// ---------------------------------------  TIMER1_MCR  -------------------------------------------
-#define TIMER1_MCR_MR0I_Pos                                   0                                                         /*!< TIMER1 MCR: MR0I Position           */
-#define TIMER1_MCR_MR0I_Msk                                   (0x01UL << TIMER1_MCR_MR0I_Pos)                           /*!< TIMER1 MCR: MR0I Mask               */
-#define TIMER1_MCR_MR0R_Pos                                   1                                                         /*!< TIMER1 MCR: MR0R Position           */
-#define TIMER1_MCR_MR0R_Msk                                   (0x01UL << TIMER1_MCR_MR0R_Pos)                           /*!< TIMER1 MCR: MR0R Mask               */
-#define TIMER1_MCR_MR0S_Pos                                   2                                                         /*!< TIMER1 MCR: MR0S Position           */
-#define TIMER1_MCR_MR0S_Msk                                   (0x01UL << TIMER1_MCR_MR0S_Pos)                           /*!< TIMER1 MCR: MR0S Mask               */
-#define TIMER1_MCR_MR1I_Pos                                   3                                                         /*!< TIMER1 MCR: MR1I Position           */
-#define TIMER1_MCR_MR1I_Msk                                   (0x01UL << TIMER1_MCR_MR1I_Pos)                           /*!< TIMER1 MCR: MR1I Mask               */
-#define TIMER1_MCR_MR1R_Pos                                   4                                                         /*!< TIMER1 MCR: MR1R Position           */
-#define TIMER1_MCR_MR1R_Msk                                   (0x01UL << TIMER1_MCR_MR1R_Pos)                           /*!< TIMER1 MCR: MR1R Mask               */
-#define TIMER1_MCR_MR1S_Pos                                   5                                                         /*!< TIMER1 MCR: MR1S Position           */
-#define TIMER1_MCR_MR1S_Msk                                   (0x01UL << TIMER1_MCR_MR1S_Pos)                           /*!< TIMER1 MCR: MR1S Mask               */
-#define TIMER1_MCR_MR2I_Pos                                   6                                                         /*!< TIMER1 MCR: MR2I Position           */
-#define TIMER1_MCR_MR2I_Msk                                   (0x01UL << TIMER1_MCR_MR2I_Pos)                           /*!< TIMER1 MCR: MR2I Mask               */
-#define TIMER1_MCR_MR2R_Pos                                   7                                                         /*!< TIMER1 MCR: MR2R Position           */
-#define TIMER1_MCR_MR2R_Msk                                   (0x01UL << TIMER1_MCR_MR2R_Pos)                           /*!< TIMER1 MCR: MR2R Mask               */
-#define TIMER1_MCR_MR2S_Pos                                   8                                                         /*!< TIMER1 MCR: MR2S Position           */
-#define TIMER1_MCR_MR2S_Msk                                   (0x01UL << TIMER1_MCR_MR2S_Pos)                           /*!< TIMER1 MCR: MR2S Mask               */
-#define TIMER1_MCR_MR3I_Pos                                   9                                                         /*!< TIMER1 MCR: MR3I Position           */
-#define TIMER1_MCR_MR3I_Msk                                   (0x01UL << TIMER1_MCR_MR3I_Pos)                           /*!< TIMER1 MCR: MR3I Mask               */
-#define TIMER1_MCR_MR3R_Pos                                   10                                                        /*!< TIMER1 MCR: MR3R Position           */
-#define TIMER1_MCR_MR3R_Msk                                   (0x01UL << TIMER1_MCR_MR3R_Pos)                           /*!< TIMER1 MCR: MR3R Mask               */
-#define TIMER1_MCR_MR3S_Pos                                   11                                                        /*!< TIMER1 MCR: MR3S Position           */
-#define TIMER1_MCR_MR3S_Msk                                   (0x01UL << TIMER1_MCR_MR3S_Pos)                           /*!< TIMER1 MCR: MR3S Mask               */
-
-// ---------------------------------------  TIMER1_MR0  -------------------------------------------
-#define TIMER1_MR0_MATCH_Pos                                  0                                                         /*!< TIMER1 MR0: MATCH Position          */
-#define TIMER1_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR0_MATCH_Pos)                    /*!< TIMER1 MR0: MATCH Mask              */
-
-// ---------------------------------------  TIMER1_MR1  -------------------------------------------
-#define TIMER1_MR1_MATCH_Pos                                  0                                                         /*!< TIMER1 MR1: MATCH Position          */
-#define TIMER1_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR1_MATCH_Pos)                    /*!< TIMER1 MR1: MATCH Mask              */
-
-// ---------------------------------------  TIMER1_MR2  -------------------------------------------
-#define TIMER1_MR2_MATCH_Pos                                  0                                                         /*!< TIMER1 MR2: MATCH Position          */
-#define TIMER1_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR2_MATCH_Pos)                    /*!< TIMER1 MR2: MATCH Mask              */
-
-// ---------------------------------------  TIMER1_MR3  -------------------------------------------
-#define TIMER1_MR3_MATCH_Pos                                  0                                                         /*!< TIMER1 MR3: MATCH Position          */
-#define TIMER1_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR3_MATCH_Pos)                    /*!< TIMER1 MR3: MATCH Mask              */
-
-// ---------------------------------------  TIMER1_CCR  -------------------------------------------
-#define TIMER1_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER1 CCR: CAP0RE Position         */
-#define TIMER1_CCR_CAP0RE_Msk                                 (0x01UL << TIMER1_CCR_CAP0RE_Pos)                         /*!< TIMER1 CCR: CAP0RE Mask             */
-#define TIMER1_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER1 CCR: CAP0FE Position         */
-#define TIMER1_CCR_CAP0FE_Msk                                 (0x01UL << TIMER1_CCR_CAP0FE_Pos)                         /*!< TIMER1 CCR: CAP0FE Mask             */
-#define TIMER1_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER1 CCR: CAP0I Position          */
-#define TIMER1_CCR_CAP0I_Msk                                  (0x01UL << TIMER1_CCR_CAP0I_Pos)                          /*!< TIMER1 CCR: CAP0I Mask              */
-#define TIMER1_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER1 CCR: CAP1RE Position         */
-#define TIMER1_CCR_CAP1RE_Msk                                 (0x01UL << TIMER1_CCR_CAP1RE_Pos)                         /*!< TIMER1 CCR: CAP1RE Mask             */
-#define TIMER1_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER1 CCR: CAP1FE Position         */
-#define TIMER1_CCR_CAP1FE_Msk                                 (0x01UL << TIMER1_CCR_CAP1FE_Pos)                         /*!< TIMER1 CCR: CAP1FE Mask             */
-#define TIMER1_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER1 CCR: CAP1I Position          */
-#define TIMER1_CCR_CAP1I_Msk                                  (0x01UL << TIMER1_CCR_CAP1I_Pos)                          /*!< TIMER1 CCR: CAP1I Mask              */
-#define TIMER1_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER1 CCR: CAP2RE Position         */
-#define TIMER1_CCR_CAP2RE_Msk                                 (0x01UL << TIMER1_CCR_CAP2RE_Pos)                         /*!< TIMER1 CCR: CAP2RE Mask             */
-#define TIMER1_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER1 CCR: CAP2FE Position         */
-#define TIMER1_CCR_CAP2FE_Msk                                 (0x01UL << TIMER1_CCR_CAP2FE_Pos)                         /*!< TIMER1 CCR: CAP2FE Mask             */
-#define TIMER1_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER1 CCR: CAP2I Position          */
-#define TIMER1_CCR_CAP2I_Msk                                  (0x01UL << TIMER1_CCR_CAP2I_Pos)                          /*!< TIMER1 CCR: CAP2I Mask              */
-#define TIMER1_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER1 CCR: CAP3RE Position         */
-#define TIMER1_CCR_CAP3RE_Msk                                 (0x01UL << TIMER1_CCR_CAP3RE_Pos)                         /*!< TIMER1 CCR: CAP3RE Mask             */
-#define TIMER1_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER1 CCR: CAP3FE Position         */
-#define TIMER1_CCR_CAP3FE_Msk                                 (0x01UL << TIMER1_CCR_CAP3FE_Pos)                         /*!< TIMER1 CCR: CAP3FE Mask             */
-#define TIMER1_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER1 CCR: CAP3I Position          */
-#define TIMER1_CCR_CAP3I_Msk                                  (0x01UL << TIMER1_CCR_CAP3I_Pos)                          /*!< TIMER1 CCR: CAP3I Mask              */
-
-// ---------------------------------------  TIMER1_CR0  -------------------------------------------
-#define TIMER1_CR0_CAP_Pos                                    0                                                         /*!< TIMER1 CR0: CAP Position            */
-#define TIMER1_CR0_CAP_Msk                                    (0xffffffffUL << TIMER1_CR0_CAP_Pos)                      /*!< TIMER1 CR0: CAP Mask                */
-
-// ---------------------------------------  TIMER1_CR1  -------------------------------------------
-#define TIMER1_CR1_CAP_Pos                                    0                                                         /*!< TIMER1 CR1: CAP Position            */
-#define TIMER1_CR1_CAP_Msk                                    (0xffffffffUL << TIMER1_CR1_CAP_Pos)                      /*!< TIMER1 CR1: CAP Mask                */
-
-// ---------------------------------------  TIMER1_CR2  -------------------------------------------
-#define TIMER1_CR2_CAP_Pos                                    0                                                         /*!< TIMER1 CR2: CAP Position            */
-#define TIMER1_CR2_CAP_Msk                                    (0xffffffffUL << TIMER1_CR2_CAP_Pos)                      /*!< TIMER1 CR2: CAP Mask                */
-
-// ---------------------------------------  TIMER1_CR3  -------------------------------------------
-#define TIMER1_CR3_CAP_Pos                                    0                                                         /*!< TIMER1 CR3: CAP Position            */
-#define TIMER1_CR3_CAP_Msk                                    (0xffffffffUL << TIMER1_CR3_CAP_Pos)                      /*!< TIMER1 CR3: CAP Mask                */
-
-// ---------------------------------------  TIMER1_EMR  -------------------------------------------
-#define TIMER1_EMR_EM0_Pos                                    0                                                         /*!< TIMER1 EMR: EM0 Position            */
-#define TIMER1_EMR_EM0_Msk                                    (0x01UL << TIMER1_EMR_EM0_Pos)                            /*!< TIMER1 EMR: EM0 Mask                */
-#define TIMER1_EMR_EM1_Pos                                    1                                                         /*!< TIMER1 EMR: EM1 Position            */
-#define TIMER1_EMR_EM1_Msk                                    (0x01UL << TIMER1_EMR_EM1_Pos)                            /*!< TIMER1 EMR: EM1 Mask                */
-#define TIMER1_EMR_EM2_Pos                                    2                                                         /*!< TIMER1 EMR: EM2 Position            */
-#define TIMER1_EMR_EM2_Msk                                    (0x01UL << TIMER1_EMR_EM2_Pos)                            /*!< TIMER1 EMR: EM2 Mask                */
-#define TIMER1_EMR_EM3_Pos                                    3                                                         /*!< TIMER1 EMR: EM3 Position            */
-#define TIMER1_EMR_EM3_Msk                                    (0x01UL << TIMER1_EMR_EM3_Pos)                            /*!< TIMER1 EMR: EM3 Mask                */
-#define TIMER1_EMR_EMC0_Pos                                   4                                                         /*!< TIMER1 EMR: EMC0 Position           */
-#define TIMER1_EMR_EMC0_Msk                                   (0x03UL << TIMER1_EMR_EMC0_Pos)                           /*!< TIMER1 EMR: EMC0 Mask               */
-#define TIMER1_EMR_EMC1_Pos                                   6                                                         /*!< TIMER1 EMR: EMC1 Position           */
-#define TIMER1_EMR_EMC1_Msk                                   (0x03UL << TIMER1_EMR_EMC1_Pos)                           /*!< TIMER1 EMR: EMC1 Mask               */
-#define TIMER1_EMR_EMC2_Pos                                   8                                                         /*!< TIMER1 EMR: EMC2 Position           */
-#define TIMER1_EMR_EMC2_Msk                                   (0x03UL << TIMER1_EMR_EMC2_Pos)                           /*!< TIMER1 EMR: EMC2 Mask               */
-#define TIMER1_EMR_EMC3_Pos                                   10                                                        /*!< TIMER1 EMR: EMC3 Position           */
-#define TIMER1_EMR_EMC3_Msk                                   (0x03UL << TIMER1_EMR_EMC3_Pos)                           /*!< TIMER1 EMR: EMC3 Mask               */
-
-// ---------------------------------------  TIMER1_CTCR  ------------------------------------------
-#define TIMER1_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER1 CTCR: CTMODE Position        */
-#define TIMER1_CTCR_CTMODE_Msk                                (0x03UL << TIMER1_CTCR_CTMODE_Pos)                        /*!< TIMER1 CTCR: CTMODE Mask            */
-#define TIMER1_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER1 CTCR: CINSEL Position        */
-#define TIMER1_CTCR_CINSEL_Msk                                (0x03UL << TIMER1_CTCR_CINSEL_Pos)                        /*!< TIMER1 CTCR: CINSEL Mask            */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                TIMER2 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  TIMER2_IR  -------------------------------------------
-#define TIMER2_IR_MR0INT_Pos                                  0                                                         /*!< TIMER2 IR: MR0INT Position          */
-#define TIMER2_IR_MR0INT_Msk                                  (0x01UL << TIMER2_IR_MR0INT_Pos)                          /*!< TIMER2 IR: MR0INT Mask              */
-#define TIMER2_IR_MR1INT_Pos                                  1                                                         /*!< TIMER2 IR: MR1INT Position          */
-#define TIMER2_IR_MR1INT_Msk                                  (0x01UL << TIMER2_IR_MR1INT_Pos)                          /*!< TIMER2 IR: MR1INT Mask              */
-#define TIMER2_IR_MR2INT_Pos                                  2                                                         /*!< TIMER2 IR: MR2INT Position          */
-#define TIMER2_IR_MR2INT_Msk                                  (0x01UL << TIMER2_IR_MR2INT_Pos)                          /*!< TIMER2 IR: MR2INT Mask              */
-#define TIMER2_IR_MR3INT_Pos                                  3                                                         /*!< TIMER2 IR: MR3INT Position          */
-#define TIMER2_IR_MR3INT_Msk                                  (0x01UL << TIMER2_IR_MR3INT_Pos)                          /*!< TIMER2 IR: MR3INT Mask              */
-#define TIMER2_IR_CR0INT_Pos                                  4                                                         /*!< TIMER2 IR: CR0INT Position          */
-#define TIMER2_IR_CR0INT_Msk                                  (0x01UL << TIMER2_IR_CR0INT_Pos)                          /*!< TIMER2 IR: CR0INT Mask              */
-#define TIMER2_IR_CR1INT_Pos                                  5                                                         /*!< TIMER2 IR: CR1INT Position          */
-#define TIMER2_IR_CR1INT_Msk                                  (0x01UL << TIMER2_IR_CR1INT_Pos)                          /*!< TIMER2 IR: CR1INT Mask              */
-#define TIMER2_IR_CR2INT_Pos                                  6                                                         /*!< TIMER2 IR: CR2INT Position          */
-#define TIMER2_IR_CR2INT_Msk                                  (0x01UL << TIMER2_IR_CR2INT_Pos)                          /*!< TIMER2 IR: CR2INT Mask              */
-#define TIMER2_IR_CR3INT_Pos                                  7                                                         /*!< TIMER2 IR: CR3INT Position          */
-#define TIMER2_IR_CR3INT_Msk                                  (0x01UL << TIMER2_IR_CR3INT_Pos)                          /*!< TIMER2 IR: CR3INT Mask              */
-
-// ---------------------------------------  TIMER2_TCR  -------------------------------------------
-#define TIMER2_TCR_CEN_Pos                                    0                                                         /*!< TIMER2 TCR: CEN Position            */
-#define TIMER2_TCR_CEN_Msk                                    (0x01UL << TIMER2_TCR_CEN_Pos)                            /*!< TIMER2 TCR: CEN Mask                */
-#define TIMER2_TCR_CRST_Pos                                   1                                                         /*!< TIMER2 TCR: CRST Position           */
-#define TIMER2_TCR_CRST_Msk                                   (0x01UL << TIMER2_TCR_CRST_Pos)                           /*!< TIMER2 TCR: CRST Mask               */
-
-// ----------------------------------------  TIMER2_TC  -------------------------------------------
-#define TIMER2_TC_TC_Pos                                      0                                                         /*!< TIMER2 TC: TC Position              */
-#define TIMER2_TC_TC_Msk                                      (0xffffffffUL << TIMER2_TC_TC_Pos)                        /*!< TIMER2 TC: TC Mask                  */
-
-// ----------------------------------------  TIMER2_PR  -------------------------------------------
-#define TIMER2_PR_PM_Pos                                      0                                                         /*!< TIMER2 PR: PM Position              */
-#define TIMER2_PR_PM_Msk                                      (0xffffffffUL << TIMER2_PR_PM_Pos)                        /*!< TIMER2 PR: PM Mask                  */
-
-// ----------------------------------------  TIMER2_PC  -------------------------------------------
-#define TIMER2_PC_PC_Pos                                      0                                                         /*!< TIMER2 PC: PC Position              */
-#define TIMER2_PC_PC_Msk                                      (0xffffffffUL << TIMER2_PC_PC_Pos)                        /*!< TIMER2 PC: PC Mask                  */
-
-// ---------------------------------------  TIMER2_MCR  -------------------------------------------
-#define TIMER2_MCR_MR0I_Pos                                   0                                                         /*!< TIMER2 MCR: MR0I Position           */
-#define TIMER2_MCR_MR0I_Msk                                   (0x01UL << TIMER2_MCR_MR0I_Pos)                           /*!< TIMER2 MCR: MR0I Mask               */
-#define TIMER2_MCR_MR0R_Pos                                   1                                                         /*!< TIMER2 MCR: MR0R Position           */
-#define TIMER2_MCR_MR0R_Msk                                   (0x01UL << TIMER2_MCR_MR0R_Pos)                           /*!< TIMER2 MCR: MR0R Mask               */
-#define TIMER2_MCR_MR0S_Pos                                   2                                                         /*!< TIMER2 MCR: MR0S Position           */
-#define TIMER2_MCR_MR0S_Msk                                   (0x01UL << TIMER2_MCR_MR0S_Pos)                           /*!< TIMER2 MCR: MR0S Mask               */
-#define TIMER2_MCR_MR1I_Pos                                   3                                                         /*!< TIMER2 MCR: MR1I Position           */
-#define TIMER2_MCR_MR1I_Msk                                   (0x01UL << TIMER2_MCR_MR1I_Pos)                           /*!< TIMER2 MCR: MR1I Mask               */
-#define TIMER2_MCR_MR1R_Pos                                   4                                                         /*!< TIMER2 MCR: MR1R Position           */
-#define TIMER2_MCR_MR1R_Msk                                   (0x01UL << TIMER2_MCR_MR1R_Pos)                           /*!< TIMER2 MCR: MR1R Mask               */
-#define TIMER2_MCR_MR1S_Pos                                   5                                                         /*!< TIMER2 MCR: MR1S Position           */
-#define TIMER2_MCR_MR1S_Msk                                   (0x01UL << TIMER2_MCR_MR1S_Pos)                           /*!< TIMER2 MCR: MR1S Mask               */
-#define TIMER2_MCR_MR2I_Pos                                   6                                                         /*!< TIMER2 MCR: MR2I Position           */
-#define TIMER2_MCR_MR2I_Msk                                   (0x01UL << TIMER2_MCR_MR2I_Pos)                           /*!< TIMER2 MCR: MR2I Mask               */
-#define TIMER2_MCR_MR2R_Pos                                   7                                                         /*!< TIMER2 MCR: MR2R Position           */
-#define TIMER2_MCR_MR2R_Msk                                   (0x01UL << TIMER2_MCR_MR2R_Pos)                           /*!< TIMER2 MCR: MR2R Mask               */
-#define TIMER2_MCR_MR2S_Pos                                   8                                                         /*!< TIMER2 MCR: MR2S Position           */
-#define TIMER2_MCR_MR2S_Msk                                   (0x01UL << TIMER2_MCR_MR2S_Pos)                           /*!< TIMER2 MCR: MR2S Mask               */
-#define TIMER2_MCR_MR3I_Pos                                   9                                                         /*!< TIMER2 MCR: MR3I Position           */
-#define TIMER2_MCR_MR3I_Msk                                   (0x01UL << TIMER2_MCR_MR3I_Pos)                           /*!< TIMER2 MCR: MR3I Mask               */
-#define TIMER2_MCR_MR3R_Pos                                   10                                                        /*!< TIMER2 MCR: MR3R Position           */
-#define TIMER2_MCR_MR3R_Msk                                   (0x01UL << TIMER2_MCR_MR3R_Pos)                           /*!< TIMER2 MCR: MR3R Mask               */
-#define TIMER2_MCR_MR3S_Pos                                   11                                                        /*!< TIMER2 MCR: MR3S Position           */
-#define TIMER2_MCR_MR3S_Msk                                   (0x01UL << TIMER2_MCR_MR3S_Pos)                           /*!< TIMER2 MCR: MR3S Mask               */
-
-// ---------------------------------------  TIMER2_MR0  -------------------------------------------
-#define TIMER2_MR0_MATCH_Pos                                  0                                                         /*!< TIMER2 MR0: MATCH Position          */
-#define TIMER2_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR0_MATCH_Pos)                    /*!< TIMER2 MR0: MATCH Mask              */
-
-// ---------------------------------------  TIMER2_MR1  -------------------------------------------
-#define TIMER2_MR1_MATCH_Pos                                  0                                                         /*!< TIMER2 MR1: MATCH Position          */
-#define TIMER2_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR1_MATCH_Pos)                    /*!< TIMER2 MR1: MATCH Mask              */
-
-// ---------------------------------------  TIMER2_MR2  -------------------------------------------
-#define TIMER2_MR2_MATCH_Pos                                  0                                                         /*!< TIMER2 MR2: MATCH Position          */
-#define TIMER2_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR2_MATCH_Pos)                    /*!< TIMER2 MR2: MATCH Mask              */
-
-// ---------------------------------------  TIMER2_MR3  -------------------------------------------
-#define TIMER2_MR3_MATCH_Pos                                  0                                                         /*!< TIMER2 MR3: MATCH Position          */
-#define TIMER2_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR3_MATCH_Pos)                    /*!< TIMER2 MR3: MATCH Mask              */
-
-// ---------------------------------------  TIMER2_CCR  -------------------------------------------
-#define TIMER2_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER2 CCR: CAP0RE Position         */
-#define TIMER2_CCR_CAP0RE_Msk                                 (0x01UL << TIMER2_CCR_CAP0RE_Pos)                         /*!< TIMER2 CCR: CAP0RE Mask             */
-#define TIMER2_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER2 CCR: CAP0FE Position         */
-#define TIMER2_CCR_CAP0FE_Msk                                 (0x01UL << TIMER2_CCR_CAP0FE_Pos)                         /*!< TIMER2 CCR: CAP0FE Mask             */
-#define TIMER2_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER2 CCR: CAP0I Position          */
-#define TIMER2_CCR_CAP0I_Msk                                  (0x01UL << TIMER2_CCR_CAP0I_Pos)                          /*!< TIMER2 CCR: CAP0I Mask              */
-#define TIMER2_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER2 CCR: CAP1RE Position         */
-#define TIMER2_CCR_CAP1RE_Msk                                 (0x01UL << TIMER2_CCR_CAP1RE_Pos)                         /*!< TIMER2 CCR: CAP1RE Mask             */
-#define TIMER2_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER2 CCR: CAP1FE Position         */
-#define TIMER2_CCR_CAP1FE_Msk                                 (0x01UL << TIMER2_CCR_CAP1FE_Pos)                         /*!< TIMER2 CCR: CAP1FE Mask             */
-#define TIMER2_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER2 CCR: CAP1I Position          */
-#define TIMER2_CCR_CAP1I_Msk                                  (0x01UL << TIMER2_CCR_CAP1I_Pos)                          /*!< TIMER2 CCR: CAP1I Mask              */
-#define TIMER2_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER2 CCR: CAP2RE Position         */
-#define TIMER2_CCR_CAP2RE_Msk                                 (0x01UL << TIMER2_CCR_CAP2RE_Pos)                         /*!< TIMER2 CCR: CAP2RE Mask             */
-#define TIMER2_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER2 CCR: CAP2FE Position         */
-#define TIMER2_CCR_CAP2FE_Msk                                 (0x01UL << TIMER2_CCR_CAP2FE_Pos)                         /*!< TIMER2 CCR: CAP2FE Mask             */
-#define TIMER2_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER2 CCR: CAP2I Position          */
-#define TIMER2_CCR_CAP2I_Msk                                  (0x01UL << TIMER2_CCR_CAP2I_Pos)                          /*!< TIMER2 CCR: CAP2I Mask              */
-#define TIMER2_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER2 CCR: CAP3RE Position         */
-#define TIMER2_CCR_CAP3RE_Msk                                 (0x01UL << TIMER2_CCR_CAP3RE_Pos)                         /*!< TIMER2 CCR: CAP3RE Mask             */
-#define TIMER2_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER2 CCR: CAP3FE Position         */
-#define TIMER2_CCR_CAP3FE_Msk                                 (0x01UL << TIMER2_CCR_CAP3FE_Pos)                         /*!< TIMER2 CCR: CAP3FE Mask             */
-#define TIMER2_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER2 CCR: CAP3I Position          */
-#define TIMER2_CCR_CAP3I_Msk                                  (0x01UL << TIMER2_CCR_CAP3I_Pos)                          /*!< TIMER2 CCR: CAP3I Mask              */
-
-// ---------------------------------------  TIMER2_CR0  -------------------------------------------
-#define TIMER2_CR0_CAP_Pos                                    0                                                         /*!< TIMER2 CR0: CAP Position            */
-#define TIMER2_CR0_CAP_Msk                                    (0xffffffffUL << TIMER2_CR0_CAP_Pos)                      /*!< TIMER2 CR0: CAP Mask                */
-
-// ---------------------------------------  TIMER2_CR1  -------------------------------------------
-#define TIMER2_CR1_CAP_Pos                                    0                                                         /*!< TIMER2 CR1: CAP Position            */
-#define TIMER2_CR1_CAP_Msk                                    (0xffffffffUL << TIMER2_CR1_CAP_Pos)                      /*!< TIMER2 CR1: CAP Mask                */
-
-// ---------------------------------------  TIMER2_CR2  -------------------------------------------
-#define TIMER2_CR2_CAP_Pos                                    0                                                         /*!< TIMER2 CR2: CAP Position            */
-#define TIMER2_CR2_CAP_Msk                                    (0xffffffffUL << TIMER2_CR2_CAP_Pos)                      /*!< TIMER2 CR2: CAP Mask                */
-
-// ---------------------------------------  TIMER2_CR3  -------------------------------------------
-#define TIMER2_CR3_CAP_Pos                                    0                                                         /*!< TIMER2 CR3: CAP Position            */
-#define TIMER2_CR3_CAP_Msk                                    (0xffffffffUL << TIMER2_CR3_CAP_Pos)                      /*!< TIMER2 CR3: CAP Mask                */
-
-// ---------------------------------------  TIMER2_EMR  -------------------------------------------
-#define TIMER2_EMR_EM0_Pos                                    0                                                         /*!< TIMER2 EMR: EM0 Position            */
-#define TIMER2_EMR_EM0_Msk                                    (0x01UL << TIMER2_EMR_EM0_Pos)                            /*!< TIMER2 EMR: EM0 Mask                */
-#define TIMER2_EMR_EM1_Pos                                    1                                                         /*!< TIMER2 EMR: EM1 Position            */
-#define TIMER2_EMR_EM1_Msk                                    (0x01UL << TIMER2_EMR_EM1_Pos)                            /*!< TIMER2 EMR: EM1 Mask                */
-#define TIMER2_EMR_EM2_Pos                                    2                                                         /*!< TIMER2 EMR: EM2 Position            */
-#define TIMER2_EMR_EM2_Msk                                    (0x01UL << TIMER2_EMR_EM2_Pos)                            /*!< TIMER2 EMR: EM2 Mask                */
-#define TIMER2_EMR_EM3_Pos                                    3                                                         /*!< TIMER2 EMR: EM3 Position            */
-#define TIMER2_EMR_EM3_Msk                                    (0x01UL << TIMER2_EMR_EM3_Pos)                            /*!< TIMER2 EMR: EM3 Mask                */
-#define TIMER2_EMR_EMC0_Pos                                   4                                                         /*!< TIMER2 EMR: EMC0 Position           */
-#define TIMER2_EMR_EMC0_Msk                                   (0x03UL << TIMER2_EMR_EMC0_Pos)                           /*!< TIMER2 EMR: EMC0 Mask               */
-#define TIMER2_EMR_EMC1_Pos                                   6                                                         /*!< TIMER2 EMR: EMC1 Position           */
-#define TIMER2_EMR_EMC1_Msk                                   (0x03UL << TIMER2_EMR_EMC1_Pos)                           /*!< TIMER2 EMR: EMC1 Mask               */
-#define TIMER2_EMR_EMC2_Pos                                   8                                                         /*!< TIMER2 EMR: EMC2 Position           */
-#define TIMER2_EMR_EMC2_Msk                                   (0x03UL << TIMER2_EMR_EMC2_Pos)                           /*!< TIMER2 EMR: EMC2 Mask               */
-#define TIMER2_EMR_EMC3_Pos                                   10                                                        /*!< TIMER2 EMR: EMC3 Position           */
-#define TIMER2_EMR_EMC3_Msk                                   (0x03UL << TIMER2_EMR_EMC3_Pos)                           /*!< TIMER2 EMR: EMC3 Mask               */
-
-// ---------------------------------------  TIMER2_CTCR  ------------------------------------------
-#define TIMER2_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER2 CTCR: CTMODE Position        */
-#define TIMER2_CTCR_CTMODE_Msk                                (0x03UL << TIMER2_CTCR_CTMODE_Pos)                        /*!< TIMER2 CTCR: CTMODE Mask            */
-#define TIMER2_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER2 CTCR: CINSEL Position        */
-#define TIMER2_CTCR_CINSEL_Msk                                (0x03UL << TIMER2_CTCR_CINSEL_Pos)                        /*!< TIMER2 CTCR: CINSEL Mask            */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                TIMER3 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  TIMER3_IR  -------------------------------------------
-#define TIMER3_IR_MR0INT_Pos                                  0                                                         /*!< TIMER3 IR: MR0INT Position          */
-#define TIMER3_IR_MR0INT_Msk                                  (0x01UL << TIMER3_IR_MR0INT_Pos)                          /*!< TIMER3 IR: MR0INT Mask              */
-#define TIMER3_IR_MR1INT_Pos                                  1                                                         /*!< TIMER3 IR: MR1INT Position          */
-#define TIMER3_IR_MR1INT_Msk                                  (0x01UL << TIMER3_IR_MR1INT_Pos)                          /*!< TIMER3 IR: MR1INT Mask              */
-#define TIMER3_IR_MR2INT_Pos                                  2                                                         /*!< TIMER3 IR: MR2INT Position          */
-#define TIMER3_IR_MR2INT_Msk                                  (0x01UL << TIMER3_IR_MR2INT_Pos)                          /*!< TIMER3 IR: MR2INT Mask              */
-#define TIMER3_IR_MR3INT_Pos                                  3                                                         /*!< TIMER3 IR: MR3INT Position          */
-#define TIMER3_IR_MR3INT_Msk                                  (0x01UL << TIMER3_IR_MR3INT_Pos)                          /*!< TIMER3 IR: MR3INT Mask              */
-#define TIMER3_IR_CR0INT_Pos                                  4                                                         /*!< TIMER3 IR: CR0INT Position          */
-#define TIMER3_IR_CR0INT_Msk                                  (0x01UL << TIMER3_IR_CR0INT_Pos)                          /*!< TIMER3 IR: CR0INT Mask              */
-#define TIMER3_IR_CR1INT_Pos                                  5                                                         /*!< TIMER3 IR: CR1INT Position          */
-#define TIMER3_IR_CR1INT_Msk                                  (0x01UL << TIMER3_IR_CR1INT_Pos)                          /*!< TIMER3 IR: CR1INT Mask              */
-#define TIMER3_IR_CR2INT_Pos                                  6                                                         /*!< TIMER3 IR: CR2INT Position          */
-#define TIMER3_IR_CR2INT_Msk                                  (0x01UL << TIMER3_IR_CR2INT_Pos)                          /*!< TIMER3 IR: CR2INT Mask              */
-#define TIMER3_IR_CR3INT_Pos                                  7                                                         /*!< TIMER3 IR: CR3INT Position          */
-#define TIMER3_IR_CR3INT_Msk                                  (0x01UL << TIMER3_IR_CR3INT_Pos)                          /*!< TIMER3 IR: CR3INT Mask              */
-
-// ---------------------------------------  TIMER3_TCR  -------------------------------------------
-#define TIMER3_TCR_CEN_Pos                                    0                                                         /*!< TIMER3 TCR: CEN Position            */
-#define TIMER3_TCR_CEN_Msk                                    (0x01UL << TIMER3_TCR_CEN_Pos)                            /*!< TIMER3 TCR: CEN Mask                */
-#define TIMER3_TCR_CRST_Pos                                   1                                                         /*!< TIMER3 TCR: CRST Position           */
-#define TIMER3_TCR_CRST_Msk                                   (0x01UL << TIMER3_TCR_CRST_Pos)                           /*!< TIMER3 TCR: CRST Mask               */
-
-// ----------------------------------------  TIMER3_TC  -------------------------------------------
-#define TIMER3_TC_TC_Pos                                      0                                                         /*!< TIMER3 TC: TC Position              */
-#define TIMER3_TC_TC_Msk                                      (0xffffffffUL << TIMER3_TC_TC_Pos)                        /*!< TIMER3 TC: TC Mask                  */
-
-// ----------------------------------------  TIMER3_PR  -------------------------------------------
-#define TIMER3_PR_PM_Pos                                      0                                                         /*!< TIMER3 PR: PM Position              */
-#define TIMER3_PR_PM_Msk                                      (0xffffffffUL << TIMER3_PR_PM_Pos)                        /*!< TIMER3 PR: PM Mask                  */
-
-// ----------------------------------------  TIMER3_PC  -------------------------------------------
-#define TIMER3_PC_PC_Pos                                      0                                                         /*!< TIMER3 PC: PC Position              */
-#define TIMER3_PC_PC_Msk                                      (0xffffffffUL << TIMER3_PC_PC_Pos)                        /*!< TIMER3 PC: PC Mask                  */
-
-// ---------------------------------------  TIMER3_MCR  -------------------------------------------
-#define TIMER3_MCR_MR0I_Pos                                   0                                                         /*!< TIMER3 MCR: MR0I Position           */
-#define TIMER3_MCR_MR0I_Msk                                   (0x01UL << TIMER3_MCR_MR0I_Pos)                           /*!< TIMER3 MCR: MR0I Mask               */
-#define TIMER3_MCR_MR0R_Pos                                   1                                                         /*!< TIMER3 MCR: MR0R Position           */
-#define TIMER3_MCR_MR0R_Msk                                   (0x01UL << TIMER3_MCR_MR0R_Pos)                           /*!< TIMER3 MCR: MR0R Mask               */
-#define TIMER3_MCR_MR0S_Pos                                   2                                                         /*!< TIMER3 MCR: MR0S Position           */
-#define TIMER3_MCR_MR0S_Msk                                   (0x01UL << TIMER3_MCR_MR0S_Pos)                           /*!< TIMER3 MCR: MR0S Mask               */
-#define TIMER3_MCR_MR1I_Pos                                   3                                                         /*!< TIMER3 MCR: MR1I Position           */
-#define TIMER3_MCR_MR1I_Msk                                   (0x01UL << TIMER3_MCR_MR1I_Pos)                           /*!< TIMER3 MCR: MR1I Mask               */
-#define TIMER3_MCR_MR1R_Pos                                   4                                                         /*!< TIMER3 MCR: MR1R Position           */
-#define TIMER3_MCR_MR1R_Msk                                   (0x01UL << TIMER3_MCR_MR1R_Pos)                           /*!< TIMER3 MCR: MR1R Mask               */
-#define TIMER3_MCR_MR1S_Pos                                   5                                                         /*!< TIMER3 MCR: MR1S Position           */
-#define TIMER3_MCR_MR1S_Msk                                   (0x01UL << TIMER3_MCR_MR1S_Pos)                           /*!< TIMER3 MCR: MR1S Mask               */
-#define TIMER3_MCR_MR2I_Pos                                   6                                                         /*!< TIMER3 MCR: MR2I Position           */
-#define TIMER3_MCR_MR2I_Msk                                   (0x01UL << TIMER3_MCR_MR2I_Pos)                           /*!< TIMER3 MCR: MR2I Mask               */
-#define TIMER3_MCR_MR2R_Pos                                   7                                                         /*!< TIMER3 MCR: MR2R Position           */
-#define TIMER3_MCR_MR2R_Msk                                   (0x01UL << TIMER3_MCR_MR2R_Pos)                           /*!< TIMER3 MCR: MR2R Mask               */
-#define TIMER3_MCR_MR2S_Pos                                   8                                                         /*!< TIMER3 MCR: MR2S Position           */
-#define TIMER3_MCR_MR2S_Msk                                   (0x01UL << TIMER3_MCR_MR2S_Pos)                           /*!< TIMER3 MCR: MR2S Mask               */
-#define TIMER3_MCR_MR3I_Pos                                   9                                                         /*!< TIMER3 MCR: MR3I Position           */
-#define TIMER3_MCR_MR3I_Msk                                   (0x01UL << TIMER3_MCR_MR3I_Pos)                           /*!< TIMER3 MCR: MR3I Mask               */
-#define TIMER3_MCR_MR3R_Pos                                   10                                                        /*!< TIMER3 MCR: MR3R Position           */
-#define TIMER3_MCR_MR3R_Msk                                   (0x01UL << TIMER3_MCR_MR3R_Pos)                           /*!< TIMER3 MCR: MR3R Mask               */
-#define TIMER3_MCR_MR3S_Pos                                   11                                                        /*!< TIMER3 MCR: MR3S Position           */
-#define TIMER3_MCR_MR3S_Msk                                   (0x01UL << TIMER3_MCR_MR3S_Pos)                           /*!< TIMER3 MCR: MR3S Mask               */
-
-// ---------------------------------------  TIMER3_MR0  -------------------------------------------
-#define TIMER3_MR0_MATCH_Pos                                  0                                                         /*!< TIMER3 MR0: MATCH Position          */
-#define TIMER3_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR0_MATCH_Pos)                    /*!< TIMER3 MR0: MATCH Mask              */
-
-// ---------------------------------------  TIMER3_MR1  -------------------------------------------
-#define TIMER3_MR1_MATCH_Pos                                  0                                                         /*!< TIMER3 MR1: MATCH Position          */
-#define TIMER3_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR1_MATCH_Pos)                    /*!< TIMER3 MR1: MATCH Mask              */
-
-// ---------------------------------------  TIMER3_MR2  -------------------------------------------
-#define TIMER3_MR2_MATCH_Pos                                  0                                                         /*!< TIMER3 MR2: MATCH Position          */
-#define TIMER3_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR2_MATCH_Pos)                    /*!< TIMER3 MR2: MATCH Mask              */
-
-// ---------------------------------------  TIMER3_MR3  -------------------------------------------
-#define TIMER3_MR3_MATCH_Pos                                  0                                                         /*!< TIMER3 MR3: MATCH Position          */
-#define TIMER3_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR3_MATCH_Pos)                    /*!< TIMER3 MR3: MATCH Mask              */
-
-// ---------------------------------------  TIMER3_CCR  -------------------------------------------
-#define TIMER3_CCR_CAP0RE_Pos                                 0                                                         /*!< TIMER3 CCR: CAP0RE Position         */
-#define TIMER3_CCR_CAP0RE_Msk                                 (0x01UL << TIMER3_CCR_CAP0RE_Pos)                         /*!< TIMER3 CCR: CAP0RE Mask             */
-#define TIMER3_CCR_CAP0FE_Pos                                 1                                                         /*!< TIMER3 CCR: CAP0FE Position         */
-#define TIMER3_CCR_CAP0FE_Msk                                 (0x01UL << TIMER3_CCR_CAP0FE_Pos)                         /*!< TIMER3 CCR: CAP0FE Mask             */
-#define TIMER3_CCR_CAP0I_Pos                                  2                                                         /*!< TIMER3 CCR: CAP0I Position          */
-#define TIMER3_CCR_CAP0I_Msk                                  (0x01UL << TIMER3_CCR_CAP0I_Pos)                          /*!< TIMER3 CCR: CAP0I Mask              */
-#define TIMER3_CCR_CAP1RE_Pos                                 3                                                         /*!< TIMER3 CCR: CAP1RE Position         */
-#define TIMER3_CCR_CAP1RE_Msk                                 (0x01UL << TIMER3_CCR_CAP1RE_Pos)                         /*!< TIMER3 CCR: CAP1RE Mask             */
-#define TIMER3_CCR_CAP1FE_Pos                                 4                                                         /*!< TIMER3 CCR: CAP1FE Position         */
-#define TIMER3_CCR_CAP1FE_Msk                                 (0x01UL << TIMER3_CCR_CAP1FE_Pos)                         /*!< TIMER3 CCR: CAP1FE Mask             */
-#define TIMER3_CCR_CAP1I_Pos                                  5                                                         /*!< TIMER3 CCR: CAP1I Position          */
-#define TIMER3_CCR_CAP1I_Msk                                  (0x01UL << TIMER3_CCR_CAP1I_Pos)                          /*!< TIMER3 CCR: CAP1I Mask              */
-#define TIMER3_CCR_CAP2RE_Pos                                 6                                                         /*!< TIMER3 CCR: CAP2RE Position         */
-#define TIMER3_CCR_CAP2RE_Msk                                 (0x01UL << TIMER3_CCR_CAP2RE_Pos)                         /*!< TIMER3 CCR: CAP2RE Mask             */
-#define TIMER3_CCR_CAP2FE_Pos                                 7                                                         /*!< TIMER3 CCR: CAP2FE Position         */
-#define TIMER3_CCR_CAP2FE_Msk                                 (0x01UL << TIMER3_CCR_CAP2FE_Pos)                         /*!< TIMER3 CCR: CAP2FE Mask             */
-#define TIMER3_CCR_CAP2I_Pos                                  8                                                         /*!< TIMER3 CCR: CAP2I Position          */
-#define TIMER3_CCR_CAP2I_Msk                                  (0x01UL << TIMER3_CCR_CAP2I_Pos)                          /*!< TIMER3 CCR: CAP2I Mask              */
-#define TIMER3_CCR_CAP3RE_Pos                                 9                                                         /*!< TIMER3 CCR: CAP3RE Position         */
-#define TIMER3_CCR_CAP3RE_Msk                                 (0x01UL << TIMER3_CCR_CAP3RE_Pos)                         /*!< TIMER3 CCR: CAP3RE Mask             */
-#define TIMER3_CCR_CAP3FE_Pos                                 10                                                        /*!< TIMER3 CCR: CAP3FE Position         */
-#define TIMER3_CCR_CAP3FE_Msk                                 (0x01UL << TIMER3_CCR_CAP3FE_Pos)                         /*!< TIMER3 CCR: CAP3FE Mask             */
-#define TIMER3_CCR_CAP3I_Pos                                  11                                                        /*!< TIMER3 CCR: CAP3I Position          */
-#define TIMER3_CCR_CAP3I_Msk                                  (0x01UL << TIMER3_CCR_CAP3I_Pos)                          /*!< TIMER3 CCR: CAP3I Mask              */
-
-// ---------------------------------------  TIMER3_CR0  -------------------------------------------
-#define TIMER3_CR0_CAP_Pos                                    0                                                         /*!< TIMER3 CR0: CAP Position            */
-#define TIMER3_CR0_CAP_Msk                                    (0xffffffffUL << TIMER3_CR0_CAP_Pos)                      /*!< TIMER3 CR0: CAP Mask                */
-
-// ---------------------------------------  TIMER3_CR1  -------------------------------------------
-#define TIMER3_CR1_CAP_Pos                                    0                                                         /*!< TIMER3 CR1: CAP Position            */
-#define TIMER3_CR1_CAP_Msk                                    (0xffffffffUL << TIMER3_CR1_CAP_Pos)                      /*!< TIMER3 CR1: CAP Mask                */
-
-// ---------------------------------------  TIMER3_CR2  -------------------------------------------
-#define TIMER3_CR2_CAP_Pos                                    0                                                         /*!< TIMER3 CR2: CAP Position            */
-#define TIMER3_CR2_CAP_Msk                                    (0xffffffffUL << TIMER3_CR2_CAP_Pos)                      /*!< TIMER3 CR2: CAP Mask                */
-
-// ---------------------------------------  TIMER3_CR3  -------------------------------------------
-#define TIMER3_CR3_CAP_Pos                                    0                                                         /*!< TIMER3 CR3: CAP Position            */
-#define TIMER3_CR3_CAP_Msk                                    (0xffffffffUL << TIMER3_CR3_CAP_Pos)                      /*!< TIMER3 CR3: CAP Mask                */
-
-// ---------------------------------------  TIMER3_EMR  -------------------------------------------
-#define TIMER3_EMR_EM0_Pos                                    0                                                         /*!< TIMER3 EMR: EM0 Position            */
-#define TIMER3_EMR_EM0_Msk                                    (0x01UL << TIMER3_EMR_EM0_Pos)                            /*!< TIMER3 EMR: EM0 Mask                */
-#define TIMER3_EMR_EM1_Pos                                    1                                                         /*!< TIMER3 EMR: EM1 Position            */
-#define TIMER3_EMR_EM1_Msk                                    (0x01UL << TIMER3_EMR_EM1_Pos)                            /*!< TIMER3 EMR: EM1 Mask                */
-#define TIMER3_EMR_EM2_Pos                                    2                                                         /*!< TIMER3 EMR: EM2 Position            */
-#define TIMER3_EMR_EM2_Msk                                    (0x01UL << TIMER3_EMR_EM2_Pos)                            /*!< TIMER3 EMR: EM2 Mask                */
-#define TIMER3_EMR_EM3_Pos                                    3                                                         /*!< TIMER3 EMR: EM3 Position            */
-#define TIMER3_EMR_EM3_Msk                                    (0x01UL << TIMER3_EMR_EM3_Pos)                            /*!< TIMER3 EMR: EM3 Mask                */
-#define TIMER3_EMR_EMC0_Pos                                   4                                                         /*!< TIMER3 EMR: EMC0 Position           */
-#define TIMER3_EMR_EMC0_Msk                                   (0x03UL << TIMER3_EMR_EMC0_Pos)                           /*!< TIMER3 EMR: EMC0 Mask               */
-#define TIMER3_EMR_EMC1_Pos                                   6                                                         /*!< TIMER3 EMR: EMC1 Position           */
-#define TIMER3_EMR_EMC1_Msk                                   (0x03UL << TIMER3_EMR_EMC1_Pos)                           /*!< TIMER3 EMR: EMC1 Mask               */
-#define TIMER3_EMR_EMC2_Pos                                   8                                                         /*!< TIMER3 EMR: EMC2 Position           */
-#define TIMER3_EMR_EMC2_Msk                                   (0x03UL << TIMER3_EMR_EMC2_Pos)                           /*!< TIMER3 EMR: EMC2 Mask               */
-#define TIMER3_EMR_EMC3_Pos                                   10                                                        /*!< TIMER3 EMR: EMC3 Position           */
-#define TIMER3_EMR_EMC3_Msk                                   (0x03UL << TIMER3_EMR_EMC3_Pos)                           /*!< TIMER3 EMR: EMC3 Mask               */
-
-// ---------------------------------------  TIMER3_CTCR  ------------------------------------------
-#define TIMER3_CTCR_CTMODE_Pos                                0                                                         /*!< TIMER3 CTCR: CTMODE Position        */
-#define TIMER3_CTCR_CTMODE_Msk                                (0x03UL << TIMER3_CTCR_CTMODE_Pos)                        /*!< TIMER3 CTCR: CTMODE Mask            */
-#define TIMER3_CTCR_CINSEL_Pos                                2                                                         /*!< TIMER3 CTCR: CINSEL Position        */
-#define TIMER3_CTCR_CINSEL_Msk                                (0x03UL << TIMER3_CTCR_CINSEL_Pos)                        /*!< TIMER3 CTCR: CINSEL Mask            */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  SCU Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  SCU_SFSP0_0  ------------------------------------------
-#define SCU_SFSP0_0_MODE_Pos                                  0                                                         /*!< SCU SFSP0_0: MODE Position          */
-#define SCU_SFSP0_0_MODE_Msk                                  (0x07UL << SCU_SFSP0_0_MODE_Pos)                          /*!< SCU SFSP0_0: MODE Mask              */
-#define SCU_SFSP0_0_EPD_Pos                                   3                                                         /*!< SCU SFSP0_0: EPD Position           */
-#define SCU_SFSP0_0_EPD_Msk                                   (0x01UL << SCU_SFSP0_0_EPD_Pos)                           /*!< SCU SFSP0_0: EPD Mask               */
-#define SCU_SFSP0_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP0_0: EPUN Position          */
-#define SCU_SFSP0_0_EPUN_Msk                                  (0x01UL << SCU_SFSP0_0_EPUN_Pos)                          /*!< SCU SFSP0_0: EPUN Mask              */
-#define SCU_SFSP0_0_EHS_Pos                                   5                                                         /*!< SCU SFSP0_0: EHS Position           */
-#define SCU_SFSP0_0_EHS_Msk                                   (0x01UL << SCU_SFSP0_0_EHS_Pos)                           /*!< SCU SFSP0_0: EHS Mask               */
-#define SCU_SFSP0_0_EZI_Pos                                   6                                                         /*!< SCU SFSP0_0: EZI Position           */
-#define SCU_SFSP0_0_EZI_Msk                                   (0x01UL << SCU_SFSP0_0_EZI_Pos)                           /*!< SCU SFSP0_0: EZI Mask               */
-
-// ---------------------------------------  SCU_SFSP0_1  ------------------------------------------
-#define SCU_SFSP0_1_MODE_Pos                                  0                                                         /*!< SCU SFSP0_1: MODE Position          */
-#define SCU_SFSP0_1_MODE_Msk                                  (0x07UL << SCU_SFSP0_1_MODE_Pos)                          /*!< SCU SFSP0_1: MODE Mask              */
-#define SCU_SFSP0_1_EPD_Pos                                   3                                                         /*!< SCU SFSP0_1: EPD Position           */
-#define SCU_SFSP0_1_EPD_Msk                                   (0x01UL << SCU_SFSP0_1_EPD_Pos)                           /*!< SCU SFSP0_1: EPD Mask               */
-#define SCU_SFSP0_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP0_1: EPUN Position          */
-#define SCU_SFSP0_1_EPUN_Msk                                  (0x01UL << SCU_SFSP0_1_EPUN_Pos)                          /*!< SCU SFSP0_1: EPUN Mask              */
-#define SCU_SFSP0_1_EHS_Pos                                   5                                                         /*!< SCU SFSP0_1: EHS Position           */
-#define SCU_SFSP0_1_EHS_Msk                                   (0x01UL << SCU_SFSP0_1_EHS_Pos)                           /*!< SCU SFSP0_1: EHS Mask               */
-#define SCU_SFSP0_1_EZI_Pos                                   6                                                         /*!< SCU SFSP0_1: EZI Position           */
-#define SCU_SFSP0_1_EZI_Msk                                   (0x01UL << SCU_SFSP0_1_EZI_Pos)                           /*!< SCU SFSP0_1: EZI Mask               */
-
-// ---------------------------------------  SCU_SFSP1_0  ------------------------------------------
-#define SCU_SFSP1_0_MODE_Pos                                  0                                                         /*!< SCU SFSP1_0: MODE Position          */
-#define SCU_SFSP1_0_MODE_Msk                                  (0x07UL << SCU_SFSP1_0_MODE_Pos)                          /*!< SCU SFSP1_0: MODE Mask              */
-#define SCU_SFSP1_0_EPD_Pos                                   3                                                         /*!< SCU SFSP1_0: EPD Position           */
-#define SCU_SFSP1_0_EPD_Msk                                   (0x01UL << SCU_SFSP1_0_EPD_Pos)                           /*!< SCU SFSP1_0: EPD Mask               */
-#define SCU_SFSP1_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_0: EPUN Position          */
-#define SCU_SFSP1_0_EPUN_Msk                                  (0x01UL << SCU_SFSP1_0_EPUN_Pos)                          /*!< SCU SFSP1_0: EPUN Mask              */
-#define SCU_SFSP1_0_EHS_Pos                                   5                                                         /*!< SCU SFSP1_0: EHS Position           */
-#define SCU_SFSP1_0_EHS_Msk                                   (0x01UL << SCU_SFSP1_0_EHS_Pos)                           /*!< SCU SFSP1_0: EHS Mask               */
-#define SCU_SFSP1_0_EZI_Pos                                   6                                                         /*!< SCU SFSP1_0: EZI Position           */
-#define SCU_SFSP1_0_EZI_Msk                                   (0x01UL << SCU_SFSP1_0_EZI_Pos)                           /*!< SCU SFSP1_0: EZI Mask               */
-#define SCU_SFSP1_0_EHD_Pos                                   8                                                         /*!< SCU SFSP1_0: EHD Position           */
-#define SCU_SFSP1_0_EHD_Msk                                   (0x03UL << SCU_SFSP1_0_EHD_Pos)                           /*!< SCU SFSP1_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP1_1  ------------------------------------------
-#define SCU_SFSP1_1_MODE_Pos                                  0                                                         /*!< SCU SFSP1_1: MODE Position          */
-#define SCU_SFSP1_1_MODE_Msk                                  (0x07UL << SCU_SFSP1_1_MODE_Pos)                          /*!< SCU SFSP1_1: MODE Mask              */
-#define SCU_SFSP1_1_EPD_Pos                                   3                                                         /*!< SCU SFSP1_1: EPD Position           */
-#define SCU_SFSP1_1_EPD_Msk                                   (0x01UL << SCU_SFSP1_1_EPD_Pos)                           /*!< SCU SFSP1_1: EPD Mask               */
-#define SCU_SFSP1_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_1: EPUN Position          */
-#define SCU_SFSP1_1_EPUN_Msk                                  (0x01UL << SCU_SFSP1_1_EPUN_Pos)                          /*!< SCU SFSP1_1: EPUN Mask              */
-#define SCU_SFSP1_1_EHS_Pos                                   5                                                         /*!< SCU SFSP1_1: EHS Position           */
-#define SCU_SFSP1_1_EHS_Msk                                   (0x01UL << SCU_SFSP1_1_EHS_Pos)                           /*!< SCU SFSP1_1: EHS Mask               */
-#define SCU_SFSP1_1_EZI_Pos                                   6                                                         /*!< SCU SFSP1_1: EZI Position           */
-#define SCU_SFSP1_1_EZI_Msk                                   (0x01UL << SCU_SFSP1_1_EZI_Pos)                           /*!< SCU SFSP1_1: EZI Mask               */
-#define SCU_SFSP1_1_EHD_Pos                                   8                                                         /*!< SCU SFSP1_1: EHD Position           */
-#define SCU_SFSP1_1_EHD_Msk                                   (0x03UL << SCU_SFSP1_1_EHD_Pos)                           /*!< SCU SFSP1_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP1_2  ------------------------------------------
-#define SCU_SFSP1_2_MODE_Pos                                  0                                                         /*!< SCU SFSP1_2: MODE Position          */
-#define SCU_SFSP1_2_MODE_Msk                                  (0x07UL << SCU_SFSP1_2_MODE_Pos)                          /*!< SCU SFSP1_2: MODE Mask              */
-#define SCU_SFSP1_2_EPD_Pos                                   3                                                         /*!< SCU SFSP1_2: EPD Position           */
-#define SCU_SFSP1_2_EPD_Msk                                   (0x01UL << SCU_SFSP1_2_EPD_Pos)                           /*!< SCU SFSP1_2: EPD Mask               */
-#define SCU_SFSP1_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_2: EPUN Position          */
-#define SCU_SFSP1_2_EPUN_Msk                                  (0x01UL << SCU_SFSP1_2_EPUN_Pos)                          /*!< SCU SFSP1_2: EPUN Mask              */
-#define SCU_SFSP1_2_EHS_Pos                                   5                                                         /*!< SCU SFSP1_2: EHS Position           */
-#define SCU_SFSP1_2_EHS_Msk                                   (0x01UL << SCU_SFSP1_2_EHS_Pos)                           /*!< SCU SFSP1_2: EHS Mask               */
-#define SCU_SFSP1_2_EZI_Pos                                   6                                                         /*!< SCU SFSP1_2: EZI Position           */
-#define SCU_SFSP1_2_EZI_Msk                                   (0x01UL << SCU_SFSP1_2_EZI_Pos)                           /*!< SCU SFSP1_2: EZI Mask               */
-#define SCU_SFSP1_2_EHD_Pos                                   8                                                         /*!< SCU SFSP1_2: EHD Position           */
-#define SCU_SFSP1_2_EHD_Msk                                   (0x03UL << SCU_SFSP1_2_EHD_Pos)                           /*!< SCU SFSP1_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP1_3  ------------------------------------------
-#define SCU_SFSP1_3_MODE_Pos                                  0                                                         /*!< SCU SFSP1_3: MODE Position          */
-#define SCU_SFSP1_3_MODE_Msk                                  (0x07UL << SCU_SFSP1_3_MODE_Pos)                          /*!< SCU SFSP1_3: MODE Mask              */
-#define SCU_SFSP1_3_EPD_Pos                                   3                                                         /*!< SCU SFSP1_3: EPD Position           */
-#define SCU_SFSP1_3_EPD_Msk                                   (0x01UL << SCU_SFSP1_3_EPD_Pos)                           /*!< SCU SFSP1_3: EPD Mask               */
-#define SCU_SFSP1_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_3: EPUN Position          */
-#define SCU_SFSP1_3_EPUN_Msk                                  (0x01UL << SCU_SFSP1_3_EPUN_Pos)                          /*!< SCU SFSP1_3: EPUN Mask              */
-#define SCU_SFSP1_3_EHS_Pos                                   5                                                         /*!< SCU SFSP1_3: EHS Position           */
-#define SCU_SFSP1_3_EHS_Msk                                   (0x01UL << SCU_SFSP1_3_EHS_Pos)                           /*!< SCU SFSP1_3: EHS Mask               */
-#define SCU_SFSP1_3_EZI_Pos                                   6                                                         /*!< SCU SFSP1_3: EZI Position           */
-#define SCU_SFSP1_3_EZI_Msk                                   (0x01UL << SCU_SFSP1_3_EZI_Pos)                           /*!< SCU SFSP1_3: EZI Mask               */
-#define SCU_SFSP1_3_EHD_Pos                                   8                                                         /*!< SCU SFSP1_3: EHD Position           */
-#define SCU_SFSP1_3_EHD_Msk                                   (0x03UL << SCU_SFSP1_3_EHD_Pos)                           /*!< SCU SFSP1_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP1_4  ------------------------------------------
-#define SCU_SFSP1_4_MODE_Pos                                  0                                                         /*!< SCU SFSP1_4: MODE Position          */
-#define SCU_SFSP1_4_MODE_Msk                                  (0x07UL << SCU_SFSP1_4_MODE_Pos)                          /*!< SCU SFSP1_4: MODE Mask              */
-#define SCU_SFSP1_4_EPD_Pos                                   3                                                         /*!< SCU SFSP1_4: EPD Position           */
-#define SCU_SFSP1_4_EPD_Msk                                   (0x01UL << SCU_SFSP1_4_EPD_Pos)                           /*!< SCU SFSP1_4: EPD Mask               */
-#define SCU_SFSP1_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_4: EPUN Position          */
-#define SCU_SFSP1_4_EPUN_Msk                                  (0x01UL << SCU_SFSP1_4_EPUN_Pos)                          /*!< SCU SFSP1_4: EPUN Mask              */
-#define SCU_SFSP1_4_EHS_Pos                                   5                                                         /*!< SCU SFSP1_4: EHS Position           */
-#define SCU_SFSP1_4_EHS_Msk                                   (0x01UL << SCU_SFSP1_4_EHS_Pos)                           /*!< SCU SFSP1_4: EHS Mask               */
-#define SCU_SFSP1_4_EZI_Pos                                   6                                                         /*!< SCU SFSP1_4: EZI Position           */
-#define SCU_SFSP1_4_EZI_Msk                                   (0x01UL << SCU_SFSP1_4_EZI_Pos)                           /*!< SCU SFSP1_4: EZI Mask               */
-#define SCU_SFSP1_4_EHD_Pos                                   8                                                         /*!< SCU SFSP1_4: EHD Position           */
-#define SCU_SFSP1_4_EHD_Msk                                   (0x03UL << SCU_SFSP1_4_EHD_Pos)                           /*!< SCU SFSP1_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP1_5  ------------------------------------------
-#define SCU_SFSP1_5_MODE_Pos                                  0                                                         /*!< SCU SFSP1_5: MODE Position          */
-#define SCU_SFSP1_5_MODE_Msk                                  (0x07UL << SCU_SFSP1_5_MODE_Pos)                          /*!< SCU SFSP1_5: MODE Mask              */
-#define SCU_SFSP1_5_EPD_Pos                                   3                                                         /*!< SCU SFSP1_5: EPD Position           */
-#define SCU_SFSP1_5_EPD_Msk                                   (0x01UL << SCU_SFSP1_5_EPD_Pos)                           /*!< SCU SFSP1_5: EPD Mask               */
-#define SCU_SFSP1_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_5: EPUN Position          */
-#define SCU_SFSP1_5_EPUN_Msk                                  (0x01UL << SCU_SFSP1_5_EPUN_Pos)                          /*!< SCU SFSP1_5: EPUN Mask              */
-#define SCU_SFSP1_5_EHS_Pos                                   5                                                         /*!< SCU SFSP1_5: EHS Position           */
-#define SCU_SFSP1_5_EHS_Msk                                   (0x01UL << SCU_SFSP1_5_EHS_Pos)                           /*!< SCU SFSP1_5: EHS Mask               */
-#define SCU_SFSP1_5_EZI_Pos                                   6                                                         /*!< SCU SFSP1_5: EZI Position           */
-#define SCU_SFSP1_5_EZI_Msk                                   (0x01UL << SCU_SFSP1_5_EZI_Pos)                           /*!< SCU SFSP1_5: EZI Mask               */
-#define SCU_SFSP1_5_EHD_Pos                                   8                                                         /*!< SCU SFSP1_5: EHD Position           */
-#define SCU_SFSP1_5_EHD_Msk                                   (0x03UL << SCU_SFSP1_5_EHD_Pos)                           /*!< SCU SFSP1_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP1_6  ------------------------------------------
-#define SCU_SFSP1_6_MODE_Pos                                  0                                                         /*!< SCU SFSP1_6: MODE Position          */
-#define SCU_SFSP1_6_MODE_Msk                                  (0x07UL << SCU_SFSP1_6_MODE_Pos)                          /*!< SCU SFSP1_6: MODE Mask              */
-#define SCU_SFSP1_6_EPD_Pos                                   3                                                         /*!< SCU SFSP1_6: EPD Position           */
-#define SCU_SFSP1_6_EPD_Msk                                   (0x01UL << SCU_SFSP1_6_EPD_Pos)                           /*!< SCU SFSP1_6: EPD Mask               */
-#define SCU_SFSP1_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_6: EPUN Position          */
-#define SCU_SFSP1_6_EPUN_Msk                                  (0x01UL << SCU_SFSP1_6_EPUN_Pos)                          /*!< SCU SFSP1_6: EPUN Mask              */
-#define SCU_SFSP1_6_EHS_Pos                                   5                                                         /*!< SCU SFSP1_6: EHS Position           */
-#define SCU_SFSP1_6_EHS_Msk                                   (0x01UL << SCU_SFSP1_6_EHS_Pos)                           /*!< SCU SFSP1_6: EHS Mask               */
-#define SCU_SFSP1_6_EZI_Pos                                   6                                                         /*!< SCU SFSP1_6: EZI Position           */
-#define SCU_SFSP1_6_EZI_Msk                                   (0x01UL << SCU_SFSP1_6_EZI_Pos)                           /*!< SCU SFSP1_6: EZI Mask               */
-#define SCU_SFSP1_6_EHD_Pos                                   8                                                         /*!< SCU SFSP1_6: EHD Position           */
-#define SCU_SFSP1_6_EHD_Msk                                   (0x03UL << SCU_SFSP1_6_EHD_Pos)                           /*!< SCU SFSP1_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP1_7  ------------------------------------------
-#define SCU_SFSP1_7_MODE_Pos                                  0                                                         /*!< SCU SFSP1_7: MODE Position          */
-#define SCU_SFSP1_7_MODE_Msk                                  (0x07UL << SCU_SFSP1_7_MODE_Pos)                          /*!< SCU SFSP1_7: MODE Mask              */
-#define SCU_SFSP1_7_EPD_Pos                                   3                                                         /*!< SCU SFSP1_7: EPD Position           */
-#define SCU_SFSP1_7_EPD_Msk                                   (0x01UL << SCU_SFSP1_7_EPD_Pos)                           /*!< SCU SFSP1_7: EPD Mask               */
-#define SCU_SFSP1_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_7: EPUN Position          */
-#define SCU_SFSP1_7_EPUN_Msk                                  (0x01UL << SCU_SFSP1_7_EPUN_Pos)                          /*!< SCU SFSP1_7: EPUN Mask              */
-#define SCU_SFSP1_7_EHS_Pos                                   5                                                         /*!< SCU SFSP1_7: EHS Position           */
-#define SCU_SFSP1_7_EHS_Msk                                   (0x01UL << SCU_SFSP1_7_EHS_Pos)                           /*!< SCU SFSP1_7: EHS Mask               */
-#define SCU_SFSP1_7_EZI_Pos                                   6                                                         /*!< SCU SFSP1_7: EZI Position           */
-#define SCU_SFSP1_7_EZI_Msk                                   (0x01UL << SCU_SFSP1_7_EZI_Pos)                           /*!< SCU SFSP1_7: EZI Mask               */
-#define SCU_SFSP1_7_EHD_Pos                                   8                                                         /*!< SCU SFSP1_7: EHD Position           */
-#define SCU_SFSP1_7_EHD_Msk                                   (0x03UL << SCU_SFSP1_7_EHD_Pos)                           /*!< SCU SFSP1_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP1_8  ------------------------------------------
-#define SCU_SFSP1_8_MODE_Pos                                  0                                                         /*!< SCU SFSP1_8: MODE Position          */
-#define SCU_SFSP1_8_MODE_Msk                                  (0x07UL << SCU_SFSP1_8_MODE_Pos)                          /*!< SCU SFSP1_8: MODE Mask              */
-#define SCU_SFSP1_8_EPD_Pos                                   3                                                         /*!< SCU SFSP1_8: EPD Position           */
-#define SCU_SFSP1_8_EPD_Msk                                   (0x01UL << SCU_SFSP1_8_EPD_Pos)                           /*!< SCU SFSP1_8: EPD Mask               */
-#define SCU_SFSP1_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_8: EPUN Position          */
-#define SCU_SFSP1_8_EPUN_Msk                                  (0x01UL << SCU_SFSP1_8_EPUN_Pos)                          /*!< SCU SFSP1_8: EPUN Mask              */
-#define SCU_SFSP1_8_EHS_Pos                                   5                                                         /*!< SCU SFSP1_8: EHS Position           */
-#define SCU_SFSP1_8_EHS_Msk                                   (0x01UL << SCU_SFSP1_8_EHS_Pos)                           /*!< SCU SFSP1_8: EHS Mask               */
-#define SCU_SFSP1_8_EZI_Pos                                   6                                                         /*!< SCU SFSP1_8: EZI Position           */
-#define SCU_SFSP1_8_EZI_Msk                                   (0x01UL << SCU_SFSP1_8_EZI_Pos)                           /*!< SCU SFSP1_8: EZI Mask               */
-#define SCU_SFSP1_8_EHD_Pos                                   8                                                         /*!< SCU SFSP1_8: EHD Position           */
-#define SCU_SFSP1_8_EHD_Msk                                   (0x03UL << SCU_SFSP1_8_EHD_Pos)                           /*!< SCU SFSP1_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP1_9  ------------------------------------------
-#define SCU_SFSP1_9_MODE_Pos                                  0                                                         /*!< SCU SFSP1_9: MODE Position          */
-#define SCU_SFSP1_9_MODE_Msk                                  (0x07UL << SCU_SFSP1_9_MODE_Pos)                          /*!< SCU SFSP1_9: MODE Mask              */
-#define SCU_SFSP1_9_EPD_Pos                                   3                                                         /*!< SCU SFSP1_9: EPD Position           */
-#define SCU_SFSP1_9_EPD_Msk                                   (0x01UL << SCU_SFSP1_9_EPD_Pos)                           /*!< SCU SFSP1_9: EPD Mask               */
-#define SCU_SFSP1_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP1_9: EPUN Position          */
-#define SCU_SFSP1_9_EPUN_Msk                                  (0x01UL << SCU_SFSP1_9_EPUN_Pos)                          /*!< SCU SFSP1_9: EPUN Mask              */
-#define SCU_SFSP1_9_EHS_Pos                                   5                                                         /*!< SCU SFSP1_9: EHS Position           */
-#define SCU_SFSP1_9_EHS_Msk                                   (0x01UL << SCU_SFSP1_9_EHS_Pos)                           /*!< SCU SFSP1_9: EHS Mask               */
-#define SCU_SFSP1_9_EZI_Pos                                   6                                                         /*!< SCU SFSP1_9: EZI Position           */
-#define SCU_SFSP1_9_EZI_Msk                                   (0x01UL << SCU_SFSP1_9_EZI_Pos)                           /*!< SCU SFSP1_9: EZI Mask               */
-#define SCU_SFSP1_9_EHD_Pos                                   8                                                         /*!< SCU SFSP1_9: EHD Position           */
-#define SCU_SFSP1_9_EHD_Msk                                   (0x03UL << SCU_SFSP1_9_EHD_Pos)                           /*!< SCU SFSP1_9: EHD Mask               */
-
-// --------------------------------------  SCU_SFSP1_10  ------------------------------------------
-#define SCU_SFSP1_10_MODE_Pos                                 0                                                         /*!< SCU SFSP1_10: MODE Position         */
-#define SCU_SFSP1_10_MODE_Msk                                 (0x07UL << SCU_SFSP1_10_MODE_Pos)                         /*!< SCU SFSP1_10: MODE Mask             */
-#define SCU_SFSP1_10_EPD_Pos                                  3                                                         /*!< SCU SFSP1_10: EPD Position          */
-#define SCU_SFSP1_10_EPD_Msk                                  (0x01UL << SCU_SFSP1_10_EPD_Pos)                          /*!< SCU SFSP1_10: EPD Mask              */
-#define SCU_SFSP1_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_10: EPUN Position         */
-#define SCU_SFSP1_10_EPUN_Msk                                 (0x01UL << SCU_SFSP1_10_EPUN_Pos)                         /*!< SCU SFSP1_10: EPUN Mask             */
-#define SCU_SFSP1_10_EHS_Pos                                  5                                                         /*!< SCU SFSP1_10: EHS Position          */
-#define SCU_SFSP1_10_EHS_Msk                                  (0x01UL << SCU_SFSP1_10_EHS_Pos)                          /*!< SCU SFSP1_10: EHS Mask              */
-#define SCU_SFSP1_10_EZI_Pos                                  6                                                         /*!< SCU SFSP1_10: EZI Position          */
-#define SCU_SFSP1_10_EZI_Msk                                  (0x01UL << SCU_SFSP1_10_EZI_Pos)                          /*!< SCU SFSP1_10: EZI Mask              */
-#define SCU_SFSP1_10_EHD_Pos                                  8                                                         /*!< SCU SFSP1_10: EHD Position          */
-#define SCU_SFSP1_10_EHD_Msk                                  (0x03UL << SCU_SFSP1_10_EHD_Pos)                          /*!< SCU SFSP1_10: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_11  ------------------------------------------
-#define SCU_SFSP1_11_MODE_Pos                                 0                                                         /*!< SCU SFSP1_11: MODE Position         */
-#define SCU_SFSP1_11_MODE_Msk                                 (0x07UL << SCU_SFSP1_11_MODE_Pos)                         /*!< SCU SFSP1_11: MODE Mask             */
-#define SCU_SFSP1_11_EPD_Pos                                  3                                                         /*!< SCU SFSP1_11: EPD Position          */
-#define SCU_SFSP1_11_EPD_Msk                                  (0x01UL << SCU_SFSP1_11_EPD_Pos)                          /*!< SCU SFSP1_11: EPD Mask              */
-#define SCU_SFSP1_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_11: EPUN Position         */
-#define SCU_SFSP1_11_EPUN_Msk                                 (0x01UL << SCU_SFSP1_11_EPUN_Pos)                         /*!< SCU SFSP1_11: EPUN Mask             */
-#define SCU_SFSP1_11_EHS_Pos                                  5                                                         /*!< SCU SFSP1_11: EHS Position          */
-#define SCU_SFSP1_11_EHS_Msk                                  (0x01UL << SCU_SFSP1_11_EHS_Pos)                          /*!< SCU SFSP1_11: EHS Mask              */
-#define SCU_SFSP1_11_EZI_Pos                                  6                                                         /*!< SCU SFSP1_11: EZI Position          */
-#define SCU_SFSP1_11_EZI_Msk                                  (0x01UL << SCU_SFSP1_11_EZI_Pos)                          /*!< SCU SFSP1_11: EZI Mask              */
-#define SCU_SFSP1_11_EHD_Pos                                  8                                                         /*!< SCU SFSP1_11: EHD Position          */
-#define SCU_SFSP1_11_EHD_Msk                                  (0x03UL << SCU_SFSP1_11_EHD_Pos)                          /*!< SCU SFSP1_11: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_12  ------------------------------------------
-#define SCU_SFSP1_12_MODE_Pos                                 0                                                         /*!< SCU SFSP1_12: MODE Position         */
-#define SCU_SFSP1_12_MODE_Msk                                 (0x07UL << SCU_SFSP1_12_MODE_Pos)                         /*!< SCU SFSP1_12: MODE Mask             */
-#define SCU_SFSP1_12_EPD_Pos                                  3                                                         /*!< SCU SFSP1_12: EPD Position          */
-#define SCU_SFSP1_12_EPD_Msk                                  (0x01UL << SCU_SFSP1_12_EPD_Pos)                          /*!< SCU SFSP1_12: EPD Mask              */
-#define SCU_SFSP1_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_12: EPUN Position         */
-#define SCU_SFSP1_12_EPUN_Msk                                 (0x01UL << SCU_SFSP1_12_EPUN_Pos)                         /*!< SCU SFSP1_12: EPUN Mask             */
-#define SCU_SFSP1_12_EHS_Pos                                  5                                                         /*!< SCU SFSP1_12: EHS Position          */
-#define SCU_SFSP1_12_EHS_Msk                                  (0x01UL << SCU_SFSP1_12_EHS_Pos)                          /*!< SCU SFSP1_12: EHS Mask              */
-#define SCU_SFSP1_12_EZI_Pos                                  6                                                         /*!< SCU SFSP1_12: EZI Position          */
-#define SCU_SFSP1_12_EZI_Msk                                  (0x01UL << SCU_SFSP1_12_EZI_Pos)                          /*!< SCU SFSP1_12: EZI Mask              */
-#define SCU_SFSP1_12_EHD_Pos                                  8                                                         /*!< SCU SFSP1_12: EHD Position          */
-#define SCU_SFSP1_12_EHD_Msk                                  (0x03UL << SCU_SFSP1_12_EHD_Pos)                          /*!< SCU SFSP1_12: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_13  ------------------------------------------
-#define SCU_SFSP1_13_MODE_Pos                                 0                                                         /*!< SCU SFSP1_13: MODE Position         */
-#define SCU_SFSP1_13_MODE_Msk                                 (0x07UL << SCU_SFSP1_13_MODE_Pos)                         /*!< SCU SFSP1_13: MODE Mask             */
-#define SCU_SFSP1_13_EPD_Pos                                  3                                                         /*!< SCU SFSP1_13: EPD Position          */
-#define SCU_SFSP1_13_EPD_Msk                                  (0x01UL << SCU_SFSP1_13_EPD_Pos)                          /*!< SCU SFSP1_13: EPD Mask              */
-#define SCU_SFSP1_13_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_13: EPUN Position         */
-#define SCU_SFSP1_13_EPUN_Msk                                 (0x01UL << SCU_SFSP1_13_EPUN_Pos)                         /*!< SCU SFSP1_13: EPUN Mask             */
-#define SCU_SFSP1_13_EHS_Pos                                  5                                                         /*!< SCU SFSP1_13: EHS Position          */
-#define SCU_SFSP1_13_EHS_Msk                                  (0x01UL << SCU_SFSP1_13_EHS_Pos)                          /*!< SCU SFSP1_13: EHS Mask              */
-#define SCU_SFSP1_13_EZI_Pos                                  6                                                         /*!< SCU SFSP1_13: EZI Position          */
-#define SCU_SFSP1_13_EZI_Msk                                  (0x01UL << SCU_SFSP1_13_EZI_Pos)                          /*!< SCU SFSP1_13: EZI Mask              */
-#define SCU_SFSP1_13_EHD_Pos                                  8                                                         /*!< SCU SFSP1_13: EHD Position          */
-#define SCU_SFSP1_13_EHD_Msk                                  (0x03UL << SCU_SFSP1_13_EHD_Pos)                          /*!< SCU SFSP1_13: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_14  ------------------------------------------
-#define SCU_SFSP1_14_MODE_Pos                                 0                                                         /*!< SCU SFSP1_14: MODE Position         */
-#define SCU_SFSP1_14_MODE_Msk                                 (0x07UL << SCU_SFSP1_14_MODE_Pos)                         /*!< SCU SFSP1_14: MODE Mask             */
-#define SCU_SFSP1_14_EPD_Pos                                  3                                                         /*!< SCU SFSP1_14: EPD Position          */
-#define SCU_SFSP1_14_EPD_Msk                                  (0x01UL << SCU_SFSP1_14_EPD_Pos)                          /*!< SCU SFSP1_14: EPD Mask              */
-#define SCU_SFSP1_14_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_14: EPUN Position         */
-#define SCU_SFSP1_14_EPUN_Msk                                 (0x01UL << SCU_SFSP1_14_EPUN_Pos)                         /*!< SCU SFSP1_14: EPUN Mask             */
-#define SCU_SFSP1_14_EHS_Pos                                  5                                                         /*!< SCU SFSP1_14: EHS Position          */
-#define SCU_SFSP1_14_EHS_Msk                                  (0x01UL << SCU_SFSP1_14_EHS_Pos)                          /*!< SCU SFSP1_14: EHS Mask              */
-#define SCU_SFSP1_14_EZI_Pos                                  6                                                         /*!< SCU SFSP1_14: EZI Position          */
-#define SCU_SFSP1_14_EZI_Msk                                  (0x01UL << SCU_SFSP1_14_EZI_Pos)                          /*!< SCU SFSP1_14: EZI Mask              */
-#define SCU_SFSP1_14_EHD_Pos                                  8                                                         /*!< SCU SFSP1_14: EHD Position          */
-#define SCU_SFSP1_14_EHD_Msk                                  (0x03UL << SCU_SFSP1_14_EHD_Pos)                          /*!< SCU SFSP1_14: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_15  ------------------------------------------
-#define SCU_SFSP1_15_MODE_Pos                                 0                                                         /*!< SCU SFSP1_15: MODE Position         */
-#define SCU_SFSP1_15_MODE_Msk                                 (0x07UL << SCU_SFSP1_15_MODE_Pos)                         /*!< SCU SFSP1_15: MODE Mask             */
-#define SCU_SFSP1_15_EPD_Pos                                  3                                                         /*!< SCU SFSP1_15: EPD Position          */
-#define SCU_SFSP1_15_EPD_Msk                                  (0x01UL << SCU_SFSP1_15_EPD_Pos)                          /*!< SCU SFSP1_15: EPD Mask              */
-#define SCU_SFSP1_15_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_15: EPUN Position         */
-#define SCU_SFSP1_15_EPUN_Msk                                 (0x01UL << SCU_SFSP1_15_EPUN_Pos)                         /*!< SCU SFSP1_15: EPUN Mask             */
-#define SCU_SFSP1_15_EHS_Pos                                  5                                                         /*!< SCU SFSP1_15: EHS Position          */
-#define SCU_SFSP1_15_EHS_Msk                                  (0x01UL << SCU_SFSP1_15_EHS_Pos)                          /*!< SCU SFSP1_15: EHS Mask              */
-#define SCU_SFSP1_15_EZI_Pos                                  6                                                         /*!< SCU SFSP1_15: EZI Position          */
-#define SCU_SFSP1_15_EZI_Msk                                  (0x01UL << SCU_SFSP1_15_EZI_Pos)                          /*!< SCU SFSP1_15: EZI Mask              */
-#define SCU_SFSP1_15_EHD_Pos                                  8                                                         /*!< SCU SFSP1_15: EHD Position          */
-#define SCU_SFSP1_15_EHD_Msk                                  (0x03UL << SCU_SFSP1_15_EHD_Pos)                          /*!< SCU SFSP1_15: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_16  ------------------------------------------
-#define SCU_SFSP1_16_MODE_Pos                                 0                                                         /*!< SCU SFSP1_16: MODE Position         */
-#define SCU_SFSP1_16_MODE_Msk                                 (0x07UL << SCU_SFSP1_16_MODE_Pos)                         /*!< SCU SFSP1_16: MODE Mask             */
-#define SCU_SFSP1_16_EPD_Pos                                  3                                                         /*!< SCU SFSP1_16: EPD Position          */
-#define SCU_SFSP1_16_EPD_Msk                                  (0x01UL << SCU_SFSP1_16_EPD_Pos)                          /*!< SCU SFSP1_16: EPD Mask              */
-#define SCU_SFSP1_16_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_16: EPUN Position         */
-#define SCU_SFSP1_16_EPUN_Msk                                 (0x01UL << SCU_SFSP1_16_EPUN_Pos)                         /*!< SCU SFSP1_16: EPUN Mask             */
-#define SCU_SFSP1_16_EHS_Pos                                  5                                                         /*!< SCU SFSP1_16: EHS Position          */
-#define SCU_SFSP1_16_EHS_Msk                                  (0x01UL << SCU_SFSP1_16_EHS_Pos)                          /*!< SCU SFSP1_16: EHS Mask              */
-#define SCU_SFSP1_16_EZI_Pos                                  6                                                         /*!< SCU SFSP1_16: EZI Position          */
-#define SCU_SFSP1_16_EZI_Msk                                  (0x01UL << SCU_SFSP1_16_EZI_Pos)                          /*!< SCU SFSP1_16: EZI Mask              */
-#define SCU_SFSP1_16_EHD_Pos                                  8                                                         /*!< SCU SFSP1_16: EHD Position          */
-#define SCU_SFSP1_16_EHD_Msk                                  (0x03UL << SCU_SFSP1_16_EHD_Pos)                          /*!< SCU SFSP1_16: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_17  ------------------------------------------
-#define SCU_SFSP1_17_MODE_Pos                                 0                                                         /*!< SCU SFSP1_17: MODE Position         */
-#define SCU_SFSP1_17_MODE_Msk                                 (0x07UL << SCU_SFSP1_17_MODE_Pos)                         /*!< SCU SFSP1_17: MODE Mask             */
-#define SCU_SFSP1_17_EPD_Pos                                  3                                                         /*!< SCU SFSP1_17: EPD Position          */
-#define SCU_SFSP1_17_EPD_Msk                                  (0x01UL << SCU_SFSP1_17_EPD_Pos)                          /*!< SCU SFSP1_17: EPD Mask              */
-#define SCU_SFSP1_17_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_17: EPUN Position         */
-#define SCU_SFSP1_17_EPUN_Msk                                 (0x01UL << SCU_SFSP1_17_EPUN_Pos)                         /*!< SCU SFSP1_17: EPUN Mask             */
-#define SCU_SFSP1_17_EHS_Pos                                  5                                                         /*!< SCU SFSP1_17: EHS Position          */
-#define SCU_SFSP1_17_EHS_Msk                                  (0x01UL << SCU_SFSP1_17_EHS_Pos)                          /*!< SCU SFSP1_17: EHS Mask              */
-#define SCU_SFSP1_17_EZI_Pos                                  6                                                         /*!< SCU SFSP1_17: EZI Position          */
-#define SCU_SFSP1_17_EZI_Msk                                  (0x01UL << SCU_SFSP1_17_EZI_Pos)                          /*!< SCU SFSP1_17: EZI Mask              */
-#define SCU_SFSP1_17_EHD_Pos                                  8                                                         /*!< SCU SFSP1_17: EHD Position          */
-#define SCU_SFSP1_17_EHD_Msk                                  (0x03UL << SCU_SFSP1_17_EHD_Pos)                          /*!< SCU SFSP1_17: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_18  ------------------------------------------
-#define SCU_SFSP1_18_MODE_Pos                                 0                                                         /*!< SCU SFSP1_18: MODE Position         */
-#define SCU_SFSP1_18_MODE_Msk                                 (0x07UL << SCU_SFSP1_18_MODE_Pos)                         /*!< SCU SFSP1_18: MODE Mask             */
-#define SCU_SFSP1_18_EPD_Pos                                  3                                                         /*!< SCU SFSP1_18: EPD Position          */
-#define SCU_SFSP1_18_EPD_Msk                                  (0x01UL << SCU_SFSP1_18_EPD_Pos)                          /*!< SCU SFSP1_18: EPD Mask              */
-#define SCU_SFSP1_18_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_18: EPUN Position         */
-#define SCU_SFSP1_18_EPUN_Msk                                 (0x01UL << SCU_SFSP1_18_EPUN_Pos)                         /*!< SCU SFSP1_18: EPUN Mask             */
-#define SCU_SFSP1_18_EHS_Pos                                  5                                                         /*!< SCU SFSP1_18: EHS Position          */
-#define SCU_SFSP1_18_EHS_Msk                                  (0x01UL << SCU_SFSP1_18_EHS_Pos)                          /*!< SCU SFSP1_18: EHS Mask              */
-#define SCU_SFSP1_18_EZI_Pos                                  6                                                         /*!< SCU SFSP1_18: EZI Position          */
-#define SCU_SFSP1_18_EZI_Msk                                  (0x01UL << SCU_SFSP1_18_EZI_Pos)                          /*!< SCU SFSP1_18: EZI Mask              */
-#define SCU_SFSP1_18_EHD_Pos                                  8                                                         /*!< SCU SFSP1_18: EHD Position          */
-#define SCU_SFSP1_18_EHD_Msk                                  (0x03UL << SCU_SFSP1_18_EHD_Pos)                          /*!< SCU SFSP1_18: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_19  ------------------------------------------
-#define SCU_SFSP1_19_MODE_Pos                                 0                                                         /*!< SCU SFSP1_19: MODE Position         */
-#define SCU_SFSP1_19_MODE_Msk                                 (0x07UL << SCU_SFSP1_19_MODE_Pos)                         /*!< SCU SFSP1_19: MODE Mask             */
-#define SCU_SFSP1_19_EPD_Pos                                  3                                                         /*!< SCU SFSP1_19: EPD Position          */
-#define SCU_SFSP1_19_EPD_Msk                                  (0x01UL << SCU_SFSP1_19_EPD_Pos)                          /*!< SCU SFSP1_19: EPD Mask              */
-#define SCU_SFSP1_19_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_19: EPUN Position         */
-#define SCU_SFSP1_19_EPUN_Msk                                 (0x01UL << SCU_SFSP1_19_EPUN_Pos)                         /*!< SCU SFSP1_19: EPUN Mask             */
-#define SCU_SFSP1_19_EHS_Pos                                  5                                                         /*!< SCU SFSP1_19: EHS Position          */
-#define SCU_SFSP1_19_EHS_Msk                                  (0x01UL << SCU_SFSP1_19_EHS_Pos)                          /*!< SCU SFSP1_19: EHS Mask              */
-#define SCU_SFSP1_19_EZI_Pos                                  6                                                         /*!< SCU SFSP1_19: EZI Position          */
-#define SCU_SFSP1_19_EZI_Msk                                  (0x01UL << SCU_SFSP1_19_EZI_Pos)                          /*!< SCU SFSP1_19: EZI Mask              */
-#define SCU_SFSP1_19_EHD_Pos                                  8                                                         /*!< SCU SFSP1_19: EHD Position          */
-#define SCU_SFSP1_19_EHD_Msk                                  (0x03UL << SCU_SFSP1_19_EHD_Pos)                          /*!< SCU SFSP1_19: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP1_20  ------------------------------------------
-#define SCU_SFSP1_20_MODE_Pos                                 0                                                         /*!< SCU SFSP1_20: MODE Position         */
-#define SCU_SFSP1_20_MODE_Msk                                 (0x07UL << SCU_SFSP1_20_MODE_Pos)                         /*!< SCU SFSP1_20: MODE Mask             */
-#define SCU_SFSP1_20_EPD_Pos                                  3                                                         /*!< SCU SFSP1_20: EPD Position          */
-#define SCU_SFSP1_20_EPD_Msk                                  (0x01UL << SCU_SFSP1_20_EPD_Pos)                          /*!< SCU SFSP1_20: EPD Mask              */
-#define SCU_SFSP1_20_EPUN_Pos                                 4                                                         /*!< SCU SFSP1_20: EPUN Position         */
-#define SCU_SFSP1_20_EPUN_Msk                                 (0x01UL << SCU_SFSP1_20_EPUN_Pos)                         /*!< SCU SFSP1_20: EPUN Mask             */
-#define SCU_SFSP1_20_EHS_Pos                                  5                                                         /*!< SCU SFSP1_20: EHS Position          */
-#define SCU_SFSP1_20_EHS_Msk                                  (0x01UL << SCU_SFSP1_20_EHS_Pos)                          /*!< SCU SFSP1_20: EHS Mask              */
-#define SCU_SFSP1_20_EZI_Pos                                  6                                                         /*!< SCU SFSP1_20: EZI Position          */
-#define SCU_SFSP1_20_EZI_Msk                                  (0x01UL << SCU_SFSP1_20_EZI_Pos)                          /*!< SCU SFSP1_20: EZI Mask              */
-#define SCU_SFSP1_20_EHD_Pos                                  8                                                         /*!< SCU SFSP1_20: EHD Position          */
-#define SCU_SFSP1_20_EHD_Msk                                  (0x03UL << SCU_SFSP1_20_EHD_Pos)                          /*!< SCU SFSP1_20: EHD Mask              */
-
-// ---------------------------------------  SCU_SFSP2_0  ------------------------------------------
-#define SCU_SFSP2_0_MODE_Pos                                  0                                                         /*!< SCU SFSP2_0: MODE Position          */
-#define SCU_SFSP2_0_MODE_Msk                                  (0x07UL << SCU_SFSP2_0_MODE_Pos)                          /*!< SCU SFSP2_0: MODE Mask              */
-#define SCU_SFSP2_0_EPD_Pos                                   3                                                         /*!< SCU SFSP2_0: EPD Position           */
-#define SCU_SFSP2_0_EPD_Msk                                   (0x01UL << SCU_SFSP2_0_EPD_Pos)                           /*!< SCU SFSP2_0: EPD Mask               */
-#define SCU_SFSP2_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_0: EPUN Position          */
-#define SCU_SFSP2_0_EPUN_Msk                                  (0x01UL << SCU_SFSP2_0_EPUN_Pos)                          /*!< SCU SFSP2_0: EPUN Mask              */
-#define SCU_SFSP2_0_EHS_Pos                                   5                                                         /*!< SCU SFSP2_0: EHS Position           */
-#define SCU_SFSP2_0_EHS_Msk                                   (0x01UL << SCU_SFSP2_0_EHS_Pos)                           /*!< SCU SFSP2_0: EHS Mask               */
-#define SCU_SFSP2_0_EZI_Pos                                   6                                                         /*!< SCU SFSP2_0: EZI Position           */
-#define SCU_SFSP2_0_EZI_Msk                                   (0x01UL << SCU_SFSP2_0_EZI_Pos)                           /*!< SCU SFSP2_0: EZI Mask               */
-#define SCU_SFSP2_0_EHD_Pos                                   8                                                         /*!< SCU SFSP2_0: EHD Position           */
-#define SCU_SFSP2_0_EHD_Msk                                   (0x03UL << SCU_SFSP2_0_EHD_Pos)                           /*!< SCU SFSP2_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP2_1  ------------------------------------------
-#define SCU_SFSP2_1_MODE_Pos                                  0                                                         /*!< SCU SFSP2_1: MODE Position          */
-#define SCU_SFSP2_1_MODE_Msk                                  (0x07UL << SCU_SFSP2_1_MODE_Pos)                          /*!< SCU SFSP2_1: MODE Mask              */
-#define SCU_SFSP2_1_EPD_Pos                                   3                                                         /*!< SCU SFSP2_1: EPD Position           */
-#define SCU_SFSP2_1_EPD_Msk                                   (0x01UL << SCU_SFSP2_1_EPD_Pos)                           /*!< SCU SFSP2_1: EPD Mask               */
-#define SCU_SFSP2_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_1: EPUN Position          */
-#define SCU_SFSP2_1_EPUN_Msk                                  (0x01UL << SCU_SFSP2_1_EPUN_Pos)                          /*!< SCU SFSP2_1: EPUN Mask              */
-#define SCU_SFSP2_1_EHS_Pos                                   5                                                         /*!< SCU SFSP2_1: EHS Position           */
-#define SCU_SFSP2_1_EHS_Msk                                   (0x01UL << SCU_SFSP2_1_EHS_Pos)                           /*!< SCU SFSP2_1: EHS Mask               */
-#define SCU_SFSP2_1_EZI_Pos                                   6                                                         /*!< SCU SFSP2_1: EZI Position           */
-#define SCU_SFSP2_1_EZI_Msk                                   (0x01UL << SCU_SFSP2_1_EZI_Pos)                           /*!< SCU SFSP2_1: EZI Mask               */
-#define SCU_SFSP2_1_EHD_Pos                                   8                                                         /*!< SCU SFSP2_1: EHD Position           */
-#define SCU_SFSP2_1_EHD_Msk                                   (0x03UL << SCU_SFSP2_1_EHD_Pos)                           /*!< SCU SFSP2_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP2_2  ------------------------------------------
-#define SCU_SFSP2_2_MODE_Pos                                  0                                                         /*!< SCU SFSP2_2: MODE Position          */
-#define SCU_SFSP2_2_MODE_Msk                                  (0x07UL << SCU_SFSP2_2_MODE_Pos)                          /*!< SCU SFSP2_2: MODE Mask              */
-#define SCU_SFSP2_2_EPD_Pos                                   3                                                         /*!< SCU SFSP2_2: EPD Position           */
-#define SCU_SFSP2_2_EPD_Msk                                   (0x01UL << SCU_SFSP2_2_EPD_Pos)                           /*!< SCU SFSP2_2: EPD Mask               */
-#define SCU_SFSP2_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_2: EPUN Position          */
-#define SCU_SFSP2_2_EPUN_Msk                                  (0x01UL << SCU_SFSP2_2_EPUN_Pos)                          /*!< SCU SFSP2_2: EPUN Mask              */
-#define SCU_SFSP2_2_EHS_Pos                                   5                                                         /*!< SCU SFSP2_2: EHS Position           */
-#define SCU_SFSP2_2_EHS_Msk                                   (0x01UL << SCU_SFSP2_2_EHS_Pos)                           /*!< SCU SFSP2_2: EHS Mask               */
-#define SCU_SFSP2_2_EZI_Pos                                   6                                                         /*!< SCU SFSP2_2: EZI Position           */
-#define SCU_SFSP2_2_EZI_Msk                                   (0x01UL << SCU_SFSP2_2_EZI_Pos)                           /*!< SCU SFSP2_2: EZI Mask               */
-#define SCU_SFSP2_2_EHD_Pos                                   8                                                         /*!< SCU SFSP2_2: EHD Position           */
-#define SCU_SFSP2_2_EHD_Msk                                   (0x03UL << SCU_SFSP2_2_EHD_Pos)                           /*!< SCU SFSP2_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP2_3  ------------------------------------------
-#define SCU_SFSP2_3_MODE_Pos                                  0                                                         /*!< SCU SFSP2_3: MODE Position          */
-#define SCU_SFSP2_3_MODE_Msk                                  (0x07UL << SCU_SFSP2_3_MODE_Pos)                          /*!< SCU SFSP2_3: MODE Mask              */
-#define SCU_SFSP2_3_EPD_Pos                                   3                                                         /*!< SCU SFSP2_3: EPD Position           */
-#define SCU_SFSP2_3_EPD_Msk                                   (0x01UL << SCU_SFSP2_3_EPD_Pos)                           /*!< SCU SFSP2_3: EPD Mask               */
-#define SCU_SFSP2_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_3: EPUN Position          */
-#define SCU_SFSP2_3_EPUN_Msk                                  (0x01UL << SCU_SFSP2_3_EPUN_Pos)                          /*!< SCU SFSP2_3: EPUN Mask              */
-#define SCU_SFSP2_3_EHS_Pos                                   5                                                         /*!< SCU SFSP2_3: EHS Position           */
-#define SCU_SFSP2_3_EHS_Msk                                   (0x01UL << SCU_SFSP2_3_EHS_Pos)                           /*!< SCU SFSP2_3: EHS Mask               */
-#define SCU_SFSP2_3_EZI_Pos                                   6                                                         /*!< SCU SFSP2_3: EZI Position           */
-#define SCU_SFSP2_3_EZI_Msk                                   (0x01UL << SCU_SFSP2_3_EZI_Pos)                           /*!< SCU SFSP2_3: EZI Mask               */
-#define SCU_SFSP2_3_EHD_Pos                                   8                                                         /*!< SCU SFSP2_3: EHD Position           */
-#define SCU_SFSP2_3_EHD_Msk                                   (0x03UL << SCU_SFSP2_3_EHD_Pos)                           /*!< SCU SFSP2_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP2_4  ------------------------------------------
-#define SCU_SFSP2_4_MODE_Pos                                  0                                                         /*!< SCU SFSP2_4: MODE Position          */
-#define SCU_SFSP2_4_MODE_Msk                                  (0x07UL << SCU_SFSP2_4_MODE_Pos)                          /*!< SCU SFSP2_4: MODE Mask              */
-#define SCU_SFSP2_4_EPD_Pos                                   3                                                         /*!< SCU SFSP2_4: EPD Position           */
-#define SCU_SFSP2_4_EPD_Msk                                   (0x01UL << SCU_SFSP2_4_EPD_Pos)                           /*!< SCU SFSP2_4: EPD Mask               */
-#define SCU_SFSP2_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_4: EPUN Position          */
-#define SCU_SFSP2_4_EPUN_Msk                                  (0x01UL << SCU_SFSP2_4_EPUN_Pos)                          /*!< SCU SFSP2_4: EPUN Mask              */
-#define SCU_SFSP2_4_EHS_Pos                                   5                                                         /*!< SCU SFSP2_4: EHS Position           */
-#define SCU_SFSP2_4_EHS_Msk                                   (0x01UL << SCU_SFSP2_4_EHS_Pos)                           /*!< SCU SFSP2_4: EHS Mask               */
-#define SCU_SFSP2_4_EZI_Pos                                   6                                                         /*!< SCU SFSP2_4: EZI Position           */
-#define SCU_SFSP2_4_EZI_Msk                                   (0x01UL << SCU_SFSP2_4_EZI_Pos)                           /*!< SCU SFSP2_4: EZI Mask               */
-#define SCU_SFSP2_4_EHD_Pos                                   8                                                         /*!< SCU SFSP2_4: EHD Position           */
-#define SCU_SFSP2_4_EHD_Msk                                   (0x03UL << SCU_SFSP2_4_EHD_Pos)                           /*!< SCU SFSP2_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP2_5  ------------------------------------------
-#define SCU_SFSP2_5_MODE_Pos                                  0                                                         /*!< SCU SFSP2_5: MODE Position          */
-#define SCU_SFSP2_5_MODE_Msk                                  (0x07UL << SCU_SFSP2_5_MODE_Pos)                          /*!< SCU SFSP2_5: MODE Mask              */
-#define SCU_SFSP2_5_EPD_Pos                                   3                                                         /*!< SCU SFSP2_5: EPD Position           */
-#define SCU_SFSP2_5_EPD_Msk                                   (0x01UL << SCU_SFSP2_5_EPD_Pos)                           /*!< SCU SFSP2_5: EPD Mask               */
-#define SCU_SFSP2_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_5: EPUN Position          */
-#define SCU_SFSP2_5_EPUN_Msk                                  (0x01UL << SCU_SFSP2_5_EPUN_Pos)                          /*!< SCU SFSP2_5: EPUN Mask              */
-#define SCU_SFSP2_5_EHS_Pos                                   5                                                         /*!< SCU SFSP2_5: EHS Position           */
-#define SCU_SFSP2_5_EHS_Msk                                   (0x01UL << SCU_SFSP2_5_EHS_Pos)                           /*!< SCU SFSP2_5: EHS Mask               */
-#define SCU_SFSP2_5_EZI_Pos                                   6                                                         /*!< SCU SFSP2_5: EZI Position           */
-#define SCU_SFSP2_5_EZI_Msk                                   (0x01UL << SCU_SFSP2_5_EZI_Pos)                           /*!< SCU SFSP2_5: EZI Mask               */
-#define SCU_SFSP2_5_EHD_Pos                                   8                                                         /*!< SCU SFSP2_5: EHD Position           */
-#define SCU_SFSP2_5_EHD_Msk                                   (0x03UL << SCU_SFSP2_5_EHD_Pos)                           /*!< SCU SFSP2_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP2_6  ------------------------------------------
-#define SCU_SFSP2_6_MODE_Pos                                  0                                                         /*!< SCU SFSP2_6: MODE Position          */
-#define SCU_SFSP2_6_MODE_Msk                                  (0x07UL << SCU_SFSP2_6_MODE_Pos)                          /*!< SCU SFSP2_6: MODE Mask              */
-#define SCU_SFSP2_6_EPD_Pos                                   3                                                         /*!< SCU SFSP2_6: EPD Position           */
-#define SCU_SFSP2_6_EPD_Msk                                   (0x01UL << SCU_SFSP2_6_EPD_Pos)                           /*!< SCU SFSP2_6: EPD Mask               */
-#define SCU_SFSP2_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_6: EPUN Position          */
-#define SCU_SFSP2_6_EPUN_Msk                                  (0x01UL << SCU_SFSP2_6_EPUN_Pos)                          /*!< SCU SFSP2_6: EPUN Mask              */
-#define SCU_SFSP2_6_EHS_Pos                                   5                                                         /*!< SCU SFSP2_6: EHS Position           */
-#define SCU_SFSP2_6_EHS_Msk                                   (0x01UL << SCU_SFSP2_6_EHS_Pos)                           /*!< SCU SFSP2_6: EHS Mask               */
-#define SCU_SFSP2_6_EZI_Pos                                   6                                                         /*!< SCU SFSP2_6: EZI Position           */
-#define SCU_SFSP2_6_EZI_Msk                                   (0x01UL << SCU_SFSP2_6_EZI_Pos)                           /*!< SCU SFSP2_6: EZI Mask               */
-#define SCU_SFSP2_6_EHD_Pos                                   8                                                         /*!< SCU SFSP2_6: EHD Position           */
-#define SCU_SFSP2_6_EHD_Msk                                   (0x03UL << SCU_SFSP2_6_EHD_Pos)                           /*!< SCU SFSP2_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP2_7  ------------------------------------------
-#define SCU_SFSP2_7_MODE_Pos                                  0                                                         /*!< SCU SFSP2_7: MODE Position          */
-#define SCU_SFSP2_7_MODE_Msk                                  (0x07UL << SCU_SFSP2_7_MODE_Pos)                          /*!< SCU SFSP2_7: MODE Mask              */
-#define SCU_SFSP2_7_EPD_Pos                                   3                                                         /*!< SCU SFSP2_7: EPD Position           */
-#define SCU_SFSP2_7_EPD_Msk                                   (0x01UL << SCU_SFSP2_7_EPD_Pos)                           /*!< SCU SFSP2_7: EPD Mask               */
-#define SCU_SFSP2_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_7: EPUN Position          */
-#define SCU_SFSP2_7_EPUN_Msk                                  (0x01UL << SCU_SFSP2_7_EPUN_Pos)                          /*!< SCU SFSP2_7: EPUN Mask              */
-#define SCU_SFSP2_7_EHS_Pos                                   5                                                         /*!< SCU SFSP2_7: EHS Position           */
-#define SCU_SFSP2_7_EHS_Msk                                   (0x01UL << SCU_SFSP2_7_EHS_Pos)                           /*!< SCU SFSP2_7: EHS Mask               */
-#define SCU_SFSP2_7_EZI_Pos                                   6                                                         /*!< SCU SFSP2_7: EZI Position           */
-#define SCU_SFSP2_7_EZI_Msk                                   (0x01UL << SCU_SFSP2_7_EZI_Pos)                           /*!< SCU SFSP2_7: EZI Mask               */
-#define SCU_SFSP2_7_EHD_Pos                                   8                                                         /*!< SCU SFSP2_7: EHD Position           */
-#define SCU_SFSP2_7_EHD_Msk                                   (0x03UL << SCU_SFSP2_7_EHD_Pos)                           /*!< SCU SFSP2_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP2_8  ------------------------------------------
-#define SCU_SFSP2_8_MODE_Pos                                  0                                                         /*!< SCU SFSP2_8: MODE Position          */
-#define SCU_SFSP2_8_MODE_Msk                                  (0x07UL << SCU_SFSP2_8_MODE_Pos)                          /*!< SCU SFSP2_8: MODE Mask              */
-#define SCU_SFSP2_8_EPD_Pos                                   3                                                         /*!< SCU SFSP2_8: EPD Position           */
-#define SCU_SFSP2_8_EPD_Msk                                   (0x01UL << SCU_SFSP2_8_EPD_Pos)                           /*!< SCU SFSP2_8: EPD Mask               */
-#define SCU_SFSP2_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_8: EPUN Position          */
-#define SCU_SFSP2_8_EPUN_Msk                                  (0x01UL << SCU_SFSP2_8_EPUN_Pos)                          /*!< SCU SFSP2_8: EPUN Mask              */
-#define SCU_SFSP2_8_EHS_Pos                                   5                                                         /*!< SCU SFSP2_8: EHS Position           */
-#define SCU_SFSP2_8_EHS_Msk                                   (0x01UL << SCU_SFSP2_8_EHS_Pos)                           /*!< SCU SFSP2_8: EHS Mask               */
-#define SCU_SFSP2_8_EZI_Pos                                   6                                                         /*!< SCU SFSP2_8: EZI Position           */
-#define SCU_SFSP2_8_EZI_Msk                                   (0x01UL << SCU_SFSP2_8_EZI_Pos)                           /*!< SCU SFSP2_8: EZI Mask               */
-#define SCU_SFSP2_8_EHD_Pos                                   8                                                         /*!< SCU SFSP2_8: EHD Position           */
-#define SCU_SFSP2_8_EHD_Msk                                   (0x03UL << SCU_SFSP2_8_EHD_Pos)                           /*!< SCU SFSP2_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP2_9  ------------------------------------------
-#define SCU_SFSP2_9_MODE_Pos                                  0                                                         /*!< SCU SFSP2_9: MODE Position          */
-#define SCU_SFSP2_9_MODE_Msk                                  (0x07UL << SCU_SFSP2_9_MODE_Pos)                          /*!< SCU SFSP2_9: MODE Mask              */
-#define SCU_SFSP2_9_EPD_Pos                                   3                                                         /*!< SCU SFSP2_9: EPD Position           */
-#define SCU_SFSP2_9_EPD_Msk                                   (0x01UL << SCU_SFSP2_9_EPD_Pos)                           /*!< SCU SFSP2_9: EPD Mask               */
-#define SCU_SFSP2_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP2_9: EPUN Position          */
-#define SCU_SFSP2_9_EPUN_Msk                                  (0x01UL << SCU_SFSP2_9_EPUN_Pos)                          /*!< SCU SFSP2_9: EPUN Mask              */
-#define SCU_SFSP2_9_EHS_Pos                                   5                                                         /*!< SCU SFSP2_9: EHS Position           */
-#define SCU_SFSP2_9_EHS_Msk                                   (0x01UL << SCU_SFSP2_9_EHS_Pos)                           /*!< SCU SFSP2_9: EHS Mask               */
-#define SCU_SFSP2_9_EZI_Pos                                   6                                                         /*!< SCU SFSP2_9: EZI Position           */
-#define SCU_SFSP2_9_EZI_Msk                                   (0x01UL << SCU_SFSP2_9_EZI_Pos)                           /*!< SCU SFSP2_9: EZI Mask               */
-#define SCU_SFSP2_9_EHD_Pos                                   8                                                         /*!< SCU SFSP2_9: EHD Position           */
-#define SCU_SFSP2_9_EHD_Msk                                   (0x03UL << SCU_SFSP2_9_EHD_Pos)                           /*!< SCU SFSP2_9: EHD Mask               */
-
-// --------------------------------------  SCU_SFSP2_10  ------------------------------------------
-#define SCU_SFSP2_10_MODE_Pos                                 0                                                         /*!< SCU SFSP2_10: MODE Position         */
-#define SCU_SFSP2_10_MODE_Msk                                 (0x07UL << SCU_SFSP2_10_MODE_Pos)                         /*!< SCU SFSP2_10: MODE Mask             */
-#define SCU_SFSP2_10_EPD_Pos                                  3                                                         /*!< SCU SFSP2_10: EPD Position          */
-#define SCU_SFSP2_10_EPD_Msk                                  (0x01UL << SCU_SFSP2_10_EPD_Pos)                          /*!< SCU SFSP2_10: EPD Mask              */
-#define SCU_SFSP2_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_10: EPUN Position         */
-#define SCU_SFSP2_10_EPUN_Msk                                 (0x01UL << SCU_SFSP2_10_EPUN_Pos)                         /*!< SCU SFSP2_10: EPUN Mask             */
-#define SCU_SFSP2_10_EHS_Pos                                  5                                                         /*!< SCU SFSP2_10: EHS Position          */
-#define SCU_SFSP2_10_EHS_Msk                                  (0x01UL << SCU_SFSP2_10_EHS_Pos)                          /*!< SCU SFSP2_10: EHS Mask              */
-#define SCU_SFSP2_10_EZI_Pos                                  6                                                         /*!< SCU SFSP2_10: EZI Position          */
-#define SCU_SFSP2_10_EZI_Msk                                  (0x01UL << SCU_SFSP2_10_EZI_Pos)                          /*!< SCU SFSP2_10: EZI Mask              */
-#define SCU_SFSP2_10_EHD_Pos                                  8                                                         /*!< SCU SFSP2_10: EHD Position          */
-#define SCU_SFSP2_10_EHD_Msk                                  (0x03UL << SCU_SFSP2_10_EHD_Pos)                          /*!< SCU SFSP2_10: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP2_11  ------------------------------------------
-#define SCU_SFSP2_11_MODE_Pos                                 0                                                         /*!< SCU SFSP2_11: MODE Position         */
-#define SCU_SFSP2_11_MODE_Msk                                 (0x07UL << SCU_SFSP2_11_MODE_Pos)                         /*!< SCU SFSP2_11: MODE Mask             */
-#define SCU_SFSP2_11_EPD_Pos                                  3                                                         /*!< SCU SFSP2_11: EPD Position          */
-#define SCU_SFSP2_11_EPD_Msk                                  (0x01UL << SCU_SFSP2_11_EPD_Pos)                          /*!< SCU SFSP2_11: EPD Mask              */
-#define SCU_SFSP2_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_11: EPUN Position         */
-#define SCU_SFSP2_11_EPUN_Msk                                 (0x01UL << SCU_SFSP2_11_EPUN_Pos)                         /*!< SCU SFSP2_11: EPUN Mask             */
-#define SCU_SFSP2_11_EHS_Pos                                  5                                                         /*!< SCU SFSP2_11: EHS Position          */
-#define SCU_SFSP2_11_EHS_Msk                                  (0x01UL << SCU_SFSP2_11_EHS_Pos)                          /*!< SCU SFSP2_11: EHS Mask              */
-#define SCU_SFSP2_11_EZI_Pos                                  6                                                         /*!< SCU SFSP2_11: EZI Position          */
-#define SCU_SFSP2_11_EZI_Msk                                  (0x01UL << SCU_SFSP2_11_EZI_Pos)                          /*!< SCU SFSP2_11: EZI Mask              */
-#define SCU_SFSP2_11_EHD_Pos                                  8                                                         /*!< SCU SFSP2_11: EHD Position          */
-#define SCU_SFSP2_11_EHD_Msk                                  (0x03UL << SCU_SFSP2_11_EHD_Pos)                          /*!< SCU SFSP2_11: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP2_12  ------------------------------------------
-#define SCU_SFSP2_12_MODE_Pos                                 0                                                         /*!< SCU SFSP2_12: MODE Position         */
-#define SCU_SFSP2_12_MODE_Msk                                 (0x07UL << SCU_SFSP2_12_MODE_Pos)                         /*!< SCU SFSP2_12: MODE Mask             */
-#define SCU_SFSP2_12_EPD_Pos                                  3                                                         /*!< SCU SFSP2_12: EPD Position          */
-#define SCU_SFSP2_12_EPD_Msk                                  (0x01UL << SCU_SFSP2_12_EPD_Pos)                          /*!< SCU SFSP2_12: EPD Mask              */
-#define SCU_SFSP2_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_12: EPUN Position         */
-#define SCU_SFSP2_12_EPUN_Msk                                 (0x01UL << SCU_SFSP2_12_EPUN_Pos)                         /*!< SCU SFSP2_12: EPUN Mask             */
-#define SCU_SFSP2_12_EHS_Pos                                  5                                                         /*!< SCU SFSP2_12: EHS Position          */
-#define SCU_SFSP2_12_EHS_Msk                                  (0x01UL << SCU_SFSP2_12_EHS_Pos)                          /*!< SCU SFSP2_12: EHS Mask              */
-#define SCU_SFSP2_12_EZI_Pos                                  6                                                         /*!< SCU SFSP2_12: EZI Position          */
-#define SCU_SFSP2_12_EZI_Msk                                  (0x01UL << SCU_SFSP2_12_EZI_Pos)                          /*!< SCU SFSP2_12: EZI Mask              */
-#define SCU_SFSP2_12_EHD_Pos                                  8                                                         /*!< SCU SFSP2_12: EHD Position          */
-#define SCU_SFSP2_12_EHD_Msk                                  (0x03UL << SCU_SFSP2_12_EHD_Pos)                          /*!< SCU SFSP2_12: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP2_13  ------------------------------------------
-#define SCU_SFSP2_13_MODE_Pos                                 0                                                         /*!< SCU SFSP2_13: MODE Position         */
-#define SCU_SFSP2_13_MODE_Msk                                 (0x07UL << SCU_SFSP2_13_MODE_Pos)                         /*!< SCU SFSP2_13: MODE Mask             */
-#define SCU_SFSP2_13_EPD_Pos                                  3                                                         /*!< SCU SFSP2_13: EPD Position          */
-#define SCU_SFSP2_13_EPD_Msk                                  (0x01UL << SCU_SFSP2_13_EPD_Pos)                          /*!< SCU SFSP2_13: EPD Mask              */
-#define SCU_SFSP2_13_EPUN_Pos                                 4                                                         /*!< SCU SFSP2_13: EPUN Position         */
-#define SCU_SFSP2_13_EPUN_Msk                                 (0x01UL << SCU_SFSP2_13_EPUN_Pos)                         /*!< SCU SFSP2_13: EPUN Mask             */
-#define SCU_SFSP2_13_EHS_Pos                                  5                                                         /*!< SCU SFSP2_13: EHS Position          */
-#define SCU_SFSP2_13_EHS_Msk                                  (0x01UL << SCU_SFSP2_13_EHS_Pos)                          /*!< SCU SFSP2_13: EHS Mask              */
-#define SCU_SFSP2_13_EZI_Pos                                  6                                                         /*!< SCU SFSP2_13: EZI Position          */
-#define SCU_SFSP2_13_EZI_Msk                                  (0x01UL << SCU_SFSP2_13_EZI_Pos)                          /*!< SCU SFSP2_13: EZI Mask              */
-#define SCU_SFSP2_13_EHD_Pos                                  8                                                         /*!< SCU SFSP2_13: EHD Position          */
-#define SCU_SFSP2_13_EHD_Msk                                  (0x03UL << SCU_SFSP2_13_EHD_Pos)                          /*!< SCU SFSP2_13: EHD Mask              */
-
-// ---------------------------------------  SCU_SFSP3_0  ------------------------------------------
-#define SCU_SFSP3_0_MODE_Pos                                  0                                                         /*!< SCU SFSP3_0: MODE Position          */
-#define SCU_SFSP3_0_MODE_Msk                                  (0x07UL << SCU_SFSP3_0_MODE_Pos)                          /*!< SCU SFSP3_0: MODE Mask              */
-#define SCU_SFSP3_0_EPD_Pos                                   3                                                         /*!< SCU SFSP3_0: EPD Position           */
-#define SCU_SFSP3_0_EPD_Msk                                   (0x01UL << SCU_SFSP3_0_EPD_Pos)                           /*!< SCU SFSP3_0: EPD Mask               */
-#define SCU_SFSP3_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_0: EPUN Position          */
-#define SCU_SFSP3_0_EPUN_Msk                                  (0x01UL << SCU_SFSP3_0_EPUN_Pos)                          /*!< SCU SFSP3_0: EPUN Mask              */
-#define SCU_SFSP3_0_EHS_Pos                                   5                                                         /*!< SCU SFSP3_0: EHS Position           */
-#define SCU_SFSP3_0_EHS_Msk                                   (0x01UL << SCU_SFSP3_0_EHS_Pos)                           /*!< SCU SFSP3_0: EHS Mask               */
-#define SCU_SFSP3_0_EZI_Pos                                   6                                                         /*!< SCU SFSP3_0: EZI Position           */
-#define SCU_SFSP3_0_EZI_Msk                                   (0x01UL << SCU_SFSP3_0_EZI_Pos)                           /*!< SCU SFSP3_0: EZI Mask               */
-#define SCU_SFSP3_0_EHD_Pos                                   8                                                         /*!< SCU SFSP3_0: EHD Position           */
-#define SCU_SFSP3_0_EHD_Msk                                   (0x03UL << SCU_SFSP3_0_EHD_Pos)                           /*!< SCU SFSP3_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP3_1  ------------------------------------------
-#define SCU_SFSP3_1_MODE_Pos                                  0                                                         /*!< SCU SFSP3_1: MODE Position          */
-#define SCU_SFSP3_1_MODE_Msk                                  (0x07UL << SCU_SFSP3_1_MODE_Pos)                          /*!< SCU SFSP3_1: MODE Mask              */
-#define SCU_SFSP3_1_EPD_Pos                                   3                                                         /*!< SCU SFSP3_1: EPD Position           */
-#define SCU_SFSP3_1_EPD_Msk                                   (0x01UL << SCU_SFSP3_1_EPD_Pos)                           /*!< SCU SFSP3_1: EPD Mask               */
-#define SCU_SFSP3_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_1: EPUN Position          */
-#define SCU_SFSP3_1_EPUN_Msk                                  (0x01UL << SCU_SFSP3_1_EPUN_Pos)                          /*!< SCU SFSP3_1: EPUN Mask              */
-#define SCU_SFSP3_1_EHS_Pos                                   5                                                         /*!< SCU SFSP3_1: EHS Position           */
-#define SCU_SFSP3_1_EHS_Msk                                   (0x01UL << SCU_SFSP3_1_EHS_Pos)                           /*!< SCU SFSP3_1: EHS Mask               */
-#define SCU_SFSP3_1_EZI_Pos                                   6                                                         /*!< SCU SFSP3_1: EZI Position           */
-#define SCU_SFSP3_1_EZI_Msk                                   (0x01UL << SCU_SFSP3_1_EZI_Pos)                           /*!< SCU SFSP3_1: EZI Mask               */
-#define SCU_SFSP3_1_EHD_Pos                                   8                                                         /*!< SCU SFSP3_1: EHD Position           */
-#define SCU_SFSP3_1_EHD_Msk                                   (0x03UL << SCU_SFSP3_1_EHD_Pos)                           /*!< SCU SFSP3_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP3_2  ------------------------------------------
-#define SCU_SFSP3_2_MODE_Pos                                  0                                                         /*!< SCU SFSP3_2: MODE Position          */
-#define SCU_SFSP3_2_MODE_Msk                                  (0x07UL << SCU_SFSP3_2_MODE_Pos)                          /*!< SCU SFSP3_2: MODE Mask              */
-#define SCU_SFSP3_2_EPD_Pos                                   3                                                         /*!< SCU SFSP3_2: EPD Position           */
-#define SCU_SFSP3_2_EPD_Msk                                   (0x01UL << SCU_SFSP3_2_EPD_Pos)                           /*!< SCU SFSP3_2: EPD Mask               */
-#define SCU_SFSP3_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_2: EPUN Position          */
-#define SCU_SFSP3_2_EPUN_Msk                                  (0x01UL << SCU_SFSP3_2_EPUN_Pos)                          /*!< SCU SFSP3_2: EPUN Mask              */
-#define SCU_SFSP3_2_EHS_Pos                                   5                                                         /*!< SCU SFSP3_2: EHS Position           */
-#define SCU_SFSP3_2_EHS_Msk                                   (0x01UL << SCU_SFSP3_2_EHS_Pos)                           /*!< SCU SFSP3_2: EHS Mask               */
-#define SCU_SFSP3_2_EZI_Pos                                   6                                                         /*!< SCU SFSP3_2: EZI Position           */
-#define SCU_SFSP3_2_EZI_Msk                                   (0x01UL << SCU_SFSP3_2_EZI_Pos)                           /*!< SCU SFSP3_2: EZI Mask               */
-#define SCU_SFSP3_2_EHD_Pos                                   8                                                         /*!< SCU SFSP3_2: EHD Position           */
-#define SCU_SFSP3_2_EHD_Msk                                   (0x03UL << SCU_SFSP3_2_EHD_Pos)                           /*!< SCU SFSP3_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP3_3  ------------------------------------------
-#define SCU_SFSP3_3_MODE_Pos                                  0                                                         /*!< SCU SFSP3_3: MODE Position          */
-#define SCU_SFSP3_3_MODE_Msk                                  (0x07UL << SCU_SFSP3_3_MODE_Pos)                          /*!< SCU SFSP3_3: MODE Mask              */
-#define SCU_SFSP3_3_EPD_Pos                                   3                                                         /*!< SCU SFSP3_3: EPD Position           */
-#define SCU_SFSP3_3_EPD_Msk                                   (0x01UL << SCU_SFSP3_3_EPD_Pos)                           /*!< SCU SFSP3_3: EPD Mask               */
-#define SCU_SFSP3_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_3: EPUN Position          */
-#define SCU_SFSP3_3_EPUN_Msk                                  (0x01UL << SCU_SFSP3_3_EPUN_Pos)                          /*!< SCU SFSP3_3: EPUN Mask              */
-#define SCU_SFSP3_3_EHS_Pos                                   5                                                         /*!< SCU SFSP3_3: EHS Position           */
-#define SCU_SFSP3_3_EHS_Msk                                   (0x01UL << SCU_SFSP3_3_EHS_Pos)                           /*!< SCU SFSP3_3: EHS Mask               */
-#define SCU_SFSP3_3_EZI_Pos                                   6                                                         /*!< SCU SFSP3_3: EZI Position           */
-#define SCU_SFSP3_3_EZI_Msk                                   (0x01UL << SCU_SFSP3_3_EZI_Pos)                           /*!< SCU SFSP3_3: EZI Mask               */
-#define SCU_SFSP3_3_EHD_Pos                                   8                                                         /*!< SCU SFSP3_3: EHD Position           */
-#define SCU_SFSP3_3_EHD_Msk                                   (0x03UL << SCU_SFSP3_3_EHD_Pos)                           /*!< SCU SFSP3_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP3_4  ------------------------------------------
-#define SCU_SFSP3_4_MODE_Pos                                  0                                                         /*!< SCU SFSP3_4: MODE Position          */
-#define SCU_SFSP3_4_MODE_Msk                                  (0x07UL << SCU_SFSP3_4_MODE_Pos)                          /*!< SCU SFSP3_4: MODE Mask              */
-#define SCU_SFSP3_4_EPD_Pos                                   3                                                         /*!< SCU SFSP3_4: EPD Position           */
-#define SCU_SFSP3_4_EPD_Msk                                   (0x01UL << SCU_SFSP3_4_EPD_Pos)                           /*!< SCU SFSP3_4: EPD Mask               */
-#define SCU_SFSP3_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_4: EPUN Position          */
-#define SCU_SFSP3_4_EPUN_Msk                                  (0x01UL << SCU_SFSP3_4_EPUN_Pos)                          /*!< SCU SFSP3_4: EPUN Mask              */
-#define SCU_SFSP3_4_EHS_Pos                                   5                                                         /*!< SCU SFSP3_4: EHS Position           */
-#define SCU_SFSP3_4_EHS_Msk                                   (0x01UL << SCU_SFSP3_4_EHS_Pos)                           /*!< SCU SFSP3_4: EHS Mask               */
-#define SCU_SFSP3_4_EZI_Pos                                   6                                                         /*!< SCU SFSP3_4: EZI Position           */
-#define SCU_SFSP3_4_EZI_Msk                                   (0x01UL << SCU_SFSP3_4_EZI_Pos)                           /*!< SCU SFSP3_4: EZI Mask               */
-#define SCU_SFSP3_4_EHD_Pos                                   8                                                         /*!< SCU SFSP3_4: EHD Position           */
-#define SCU_SFSP3_4_EHD_Msk                                   (0x03UL << SCU_SFSP3_4_EHD_Pos)                           /*!< SCU SFSP3_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP3_5  ------------------------------------------
-#define SCU_SFSP3_5_MODE_Pos                                  0                                                         /*!< SCU SFSP3_5: MODE Position          */
-#define SCU_SFSP3_5_MODE_Msk                                  (0x07UL << SCU_SFSP3_5_MODE_Pos)                          /*!< SCU SFSP3_5: MODE Mask              */
-#define SCU_SFSP3_5_EPD_Pos                                   3                                                         /*!< SCU SFSP3_5: EPD Position           */
-#define SCU_SFSP3_5_EPD_Msk                                   (0x01UL << SCU_SFSP3_5_EPD_Pos)                           /*!< SCU SFSP3_5: EPD Mask               */
-#define SCU_SFSP3_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_5: EPUN Position          */
-#define SCU_SFSP3_5_EPUN_Msk                                  (0x01UL << SCU_SFSP3_5_EPUN_Pos)                          /*!< SCU SFSP3_5: EPUN Mask              */
-#define SCU_SFSP3_5_EHS_Pos                                   5                                                         /*!< SCU SFSP3_5: EHS Position           */
-#define SCU_SFSP3_5_EHS_Msk                                   (0x01UL << SCU_SFSP3_5_EHS_Pos)                           /*!< SCU SFSP3_5: EHS Mask               */
-#define SCU_SFSP3_5_EZI_Pos                                   6                                                         /*!< SCU SFSP3_5: EZI Position           */
-#define SCU_SFSP3_5_EZI_Msk                                   (0x01UL << SCU_SFSP3_5_EZI_Pos)                           /*!< SCU SFSP3_5: EZI Mask               */
-#define SCU_SFSP3_5_EHD_Pos                                   8                                                         /*!< SCU SFSP3_5: EHD Position           */
-#define SCU_SFSP3_5_EHD_Msk                                   (0x03UL << SCU_SFSP3_5_EHD_Pos)                           /*!< SCU SFSP3_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP3_6  ------------------------------------------
-#define SCU_SFSP3_6_MODE_Pos                                  0                                                         /*!< SCU SFSP3_6: MODE Position          */
-#define SCU_SFSP3_6_MODE_Msk                                  (0x07UL << SCU_SFSP3_6_MODE_Pos)                          /*!< SCU SFSP3_6: MODE Mask              */
-#define SCU_SFSP3_6_EPD_Pos                                   3                                                         /*!< SCU SFSP3_6: EPD Position           */
-#define SCU_SFSP3_6_EPD_Msk                                   (0x01UL << SCU_SFSP3_6_EPD_Pos)                           /*!< SCU SFSP3_6: EPD Mask               */
-#define SCU_SFSP3_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_6: EPUN Position          */
-#define SCU_SFSP3_6_EPUN_Msk                                  (0x01UL << SCU_SFSP3_6_EPUN_Pos)                          /*!< SCU SFSP3_6: EPUN Mask              */
-#define SCU_SFSP3_6_EHS_Pos                                   5                                                         /*!< SCU SFSP3_6: EHS Position           */
-#define SCU_SFSP3_6_EHS_Msk                                   (0x01UL << SCU_SFSP3_6_EHS_Pos)                           /*!< SCU SFSP3_6: EHS Mask               */
-#define SCU_SFSP3_6_EZI_Pos                                   6                                                         /*!< SCU SFSP3_6: EZI Position           */
-#define SCU_SFSP3_6_EZI_Msk                                   (0x01UL << SCU_SFSP3_6_EZI_Pos)                           /*!< SCU SFSP3_6: EZI Mask               */
-#define SCU_SFSP3_6_EHD_Pos                                   8                                                         /*!< SCU SFSP3_6: EHD Position           */
-#define SCU_SFSP3_6_EHD_Msk                                   (0x03UL << SCU_SFSP3_6_EHD_Pos)                           /*!< SCU SFSP3_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP3_7  ------------------------------------------
-#define SCU_SFSP3_7_MODE_Pos                                  0                                                         /*!< SCU SFSP3_7: MODE Position          */
-#define SCU_SFSP3_7_MODE_Msk                                  (0x07UL << SCU_SFSP3_7_MODE_Pos)                          /*!< SCU SFSP3_7: MODE Mask              */
-#define SCU_SFSP3_7_EPD_Pos                                   3                                                         /*!< SCU SFSP3_7: EPD Position           */
-#define SCU_SFSP3_7_EPD_Msk                                   (0x01UL << SCU_SFSP3_7_EPD_Pos)                           /*!< SCU SFSP3_7: EPD Mask               */
-#define SCU_SFSP3_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_7: EPUN Position          */
-#define SCU_SFSP3_7_EPUN_Msk                                  (0x01UL << SCU_SFSP3_7_EPUN_Pos)                          /*!< SCU SFSP3_7: EPUN Mask              */
-#define SCU_SFSP3_7_EHS_Pos                                   5                                                         /*!< SCU SFSP3_7: EHS Position           */
-#define SCU_SFSP3_7_EHS_Msk                                   (0x01UL << SCU_SFSP3_7_EHS_Pos)                           /*!< SCU SFSP3_7: EHS Mask               */
-#define SCU_SFSP3_7_EZI_Pos                                   6                                                         /*!< SCU SFSP3_7: EZI Position           */
-#define SCU_SFSP3_7_EZI_Msk                                   (0x01UL << SCU_SFSP3_7_EZI_Pos)                           /*!< SCU SFSP3_7: EZI Mask               */
-#define SCU_SFSP3_7_EHD_Pos                                   8                                                         /*!< SCU SFSP3_7: EHD Position           */
-#define SCU_SFSP3_7_EHD_Msk                                   (0x03UL << SCU_SFSP3_7_EHD_Pos)                           /*!< SCU SFSP3_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP3_8  ------------------------------------------
-#define SCU_SFSP3_8_MODE_Pos                                  0                                                         /*!< SCU SFSP3_8: MODE Position          */
-#define SCU_SFSP3_8_MODE_Msk                                  (0x07UL << SCU_SFSP3_8_MODE_Pos)                          /*!< SCU SFSP3_8: MODE Mask              */
-#define SCU_SFSP3_8_EPD_Pos                                   3                                                         /*!< SCU SFSP3_8: EPD Position           */
-#define SCU_SFSP3_8_EPD_Msk                                   (0x01UL << SCU_SFSP3_8_EPD_Pos)                           /*!< SCU SFSP3_8: EPD Mask               */
-#define SCU_SFSP3_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP3_8: EPUN Position          */
-#define SCU_SFSP3_8_EPUN_Msk                                  (0x01UL << SCU_SFSP3_8_EPUN_Pos)                          /*!< SCU SFSP3_8: EPUN Mask              */
-#define SCU_SFSP3_8_EHS_Pos                                   5                                                         /*!< SCU SFSP3_8: EHS Position           */
-#define SCU_SFSP3_8_EHS_Msk                                   (0x01UL << SCU_SFSP3_8_EHS_Pos)                           /*!< SCU SFSP3_8: EHS Mask               */
-#define SCU_SFSP3_8_EZI_Pos                                   6                                                         /*!< SCU SFSP3_8: EZI Position           */
-#define SCU_SFSP3_8_EZI_Msk                                   (0x01UL << SCU_SFSP3_8_EZI_Pos)                           /*!< SCU SFSP3_8: EZI Mask               */
-#define SCU_SFSP3_8_EHD_Pos                                   8                                                         /*!< SCU SFSP3_8: EHD Position           */
-#define SCU_SFSP3_8_EHD_Msk                                   (0x03UL << SCU_SFSP3_8_EHD_Pos)                           /*!< SCU SFSP3_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_0  ------------------------------------------
-#define SCU_SFSP4_0_MODE_Pos                                  0                                                         /*!< SCU SFSP4_0: MODE Position          */
-#define SCU_SFSP4_0_MODE_Msk                                  (0x07UL << SCU_SFSP4_0_MODE_Pos)                          /*!< SCU SFSP4_0: MODE Mask              */
-#define SCU_SFSP4_0_EPD_Pos                                   3                                                         /*!< SCU SFSP4_0: EPD Position           */
-#define SCU_SFSP4_0_EPD_Msk                                   (0x01UL << SCU_SFSP4_0_EPD_Pos)                           /*!< SCU SFSP4_0: EPD Mask               */
-#define SCU_SFSP4_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_0: EPUN Position          */
-#define SCU_SFSP4_0_EPUN_Msk                                  (0x01UL << SCU_SFSP4_0_EPUN_Pos)                          /*!< SCU SFSP4_0: EPUN Mask              */
-#define SCU_SFSP4_0_EHS_Pos                                   5                                                         /*!< SCU SFSP4_0: EHS Position           */
-#define SCU_SFSP4_0_EHS_Msk                                   (0x01UL << SCU_SFSP4_0_EHS_Pos)                           /*!< SCU SFSP4_0: EHS Mask               */
-#define SCU_SFSP4_0_EZI_Pos                                   6                                                         /*!< SCU SFSP4_0: EZI Position           */
-#define SCU_SFSP4_0_EZI_Msk                                   (0x01UL << SCU_SFSP4_0_EZI_Pos)                           /*!< SCU SFSP4_0: EZI Mask               */
-#define SCU_SFSP4_0_EHD_Pos                                   8                                                         /*!< SCU SFSP4_0: EHD Position           */
-#define SCU_SFSP4_0_EHD_Msk                                   (0x03UL << SCU_SFSP4_0_EHD_Pos)                           /*!< SCU SFSP4_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_1  ------------------------------------------
-#define SCU_SFSP4_1_MODE_Pos                                  0                                                         /*!< SCU SFSP4_1: MODE Position          */
-#define SCU_SFSP4_1_MODE_Msk                                  (0x07UL << SCU_SFSP4_1_MODE_Pos)                          /*!< SCU SFSP4_1: MODE Mask              */
-#define SCU_SFSP4_1_EPD_Pos                                   3                                                         /*!< SCU SFSP4_1: EPD Position           */
-#define SCU_SFSP4_1_EPD_Msk                                   (0x01UL << SCU_SFSP4_1_EPD_Pos)                           /*!< SCU SFSP4_1: EPD Mask               */
-#define SCU_SFSP4_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_1: EPUN Position          */
-#define SCU_SFSP4_1_EPUN_Msk                                  (0x01UL << SCU_SFSP4_1_EPUN_Pos)                          /*!< SCU SFSP4_1: EPUN Mask              */
-#define SCU_SFSP4_1_EHS_Pos                                   5                                                         /*!< SCU SFSP4_1: EHS Position           */
-#define SCU_SFSP4_1_EHS_Msk                                   (0x01UL << SCU_SFSP4_1_EHS_Pos)                           /*!< SCU SFSP4_1: EHS Mask               */
-#define SCU_SFSP4_1_EZI_Pos                                   6                                                         /*!< SCU SFSP4_1: EZI Position           */
-#define SCU_SFSP4_1_EZI_Msk                                   (0x01UL << SCU_SFSP4_1_EZI_Pos)                           /*!< SCU SFSP4_1: EZI Mask               */
-#define SCU_SFSP4_1_EHD_Pos                                   8                                                         /*!< SCU SFSP4_1: EHD Position           */
-#define SCU_SFSP4_1_EHD_Msk                                   (0x03UL << SCU_SFSP4_1_EHD_Pos)                           /*!< SCU SFSP4_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_2  ------------------------------------------
-#define SCU_SFSP4_2_MODE_Pos                                  0                                                         /*!< SCU SFSP4_2: MODE Position          */
-#define SCU_SFSP4_2_MODE_Msk                                  (0x07UL << SCU_SFSP4_2_MODE_Pos)                          /*!< SCU SFSP4_2: MODE Mask              */
-#define SCU_SFSP4_2_EPD_Pos                                   3                                                         /*!< SCU SFSP4_2: EPD Position           */
-#define SCU_SFSP4_2_EPD_Msk                                   (0x01UL << SCU_SFSP4_2_EPD_Pos)                           /*!< SCU SFSP4_2: EPD Mask               */
-#define SCU_SFSP4_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_2: EPUN Position          */
-#define SCU_SFSP4_2_EPUN_Msk                                  (0x01UL << SCU_SFSP4_2_EPUN_Pos)                          /*!< SCU SFSP4_2: EPUN Mask              */
-#define SCU_SFSP4_2_EHS_Pos                                   5                                                         /*!< SCU SFSP4_2: EHS Position           */
-#define SCU_SFSP4_2_EHS_Msk                                   (0x01UL << SCU_SFSP4_2_EHS_Pos)                           /*!< SCU SFSP4_2: EHS Mask               */
-#define SCU_SFSP4_2_EZI_Pos                                   6                                                         /*!< SCU SFSP4_2: EZI Position           */
-#define SCU_SFSP4_2_EZI_Msk                                   (0x01UL << SCU_SFSP4_2_EZI_Pos)                           /*!< SCU SFSP4_2: EZI Mask               */
-#define SCU_SFSP4_2_EHD_Pos                                   8                                                         /*!< SCU SFSP4_2: EHD Position           */
-#define SCU_SFSP4_2_EHD_Msk                                   (0x03UL << SCU_SFSP4_2_EHD_Pos)                           /*!< SCU SFSP4_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_3  ------------------------------------------
-#define SCU_SFSP4_3_MODE_Pos                                  0                                                         /*!< SCU SFSP4_3: MODE Position          */
-#define SCU_SFSP4_3_MODE_Msk                                  (0x07UL << SCU_SFSP4_3_MODE_Pos)                          /*!< SCU SFSP4_3: MODE Mask              */
-#define SCU_SFSP4_3_EPD_Pos                                   3                                                         /*!< SCU SFSP4_3: EPD Position           */
-#define SCU_SFSP4_3_EPD_Msk                                   (0x01UL << SCU_SFSP4_3_EPD_Pos)                           /*!< SCU SFSP4_3: EPD Mask               */
-#define SCU_SFSP4_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_3: EPUN Position          */
-#define SCU_SFSP4_3_EPUN_Msk                                  (0x01UL << SCU_SFSP4_3_EPUN_Pos)                          /*!< SCU SFSP4_3: EPUN Mask              */
-#define SCU_SFSP4_3_EHS_Pos                                   5                                                         /*!< SCU SFSP4_3: EHS Position           */
-#define SCU_SFSP4_3_EHS_Msk                                   (0x01UL << SCU_SFSP4_3_EHS_Pos)                           /*!< SCU SFSP4_3: EHS Mask               */
-#define SCU_SFSP4_3_EZI_Pos                                   6                                                         /*!< SCU SFSP4_3: EZI Position           */
-#define SCU_SFSP4_3_EZI_Msk                                   (0x01UL << SCU_SFSP4_3_EZI_Pos)                           /*!< SCU SFSP4_3: EZI Mask               */
-#define SCU_SFSP4_3_EHD_Pos                                   8                                                         /*!< SCU SFSP4_3: EHD Position           */
-#define SCU_SFSP4_3_EHD_Msk                                   (0x03UL << SCU_SFSP4_3_EHD_Pos)                           /*!< SCU SFSP4_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_4  ------------------------------------------
-#define SCU_SFSP4_4_MODE_Pos                                  0                                                         /*!< SCU SFSP4_4: MODE Position          */
-#define SCU_SFSP4_4_MODE_Msk                                  (0x07UL << SCU_SFSP4_4_MODE_Pos)                          /*!< SCU SFSP4_4: MODE Mask              */
-#define SCU_SFSP4_4_EPD_Pos                                   3                                                         /*!< SCU SFSP4_4: EPD Position           */
-#define SCU_SFSP4_4_EPD_Msk                                   (0x01UL << SCU_SFSP4_4_EPD_Pos)                           /*!< SCU SFSP4_4: EPD Mask               */
-#define SCU_SFSP4_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_4: EPUN Position          */
-#define SCU_SFSP4_4_EPUN_Msk                                  (0x01UL << SCU_SFSP4_4_EPUN_Pos)                          /*!< SCU SFSP4_4: EPUN Mask              */
-#define SCU_SFSP4_4_EHS_Pos                                   5                                                         /*!< SCU SFSP4_4: EHS Position           */
-#define SCU_SFSP4_4_EHS_Msk                                   (0x01UL << SCU_SFSP4_4_EHS_Pos)                           /*!< SCU SFSP4_4: EHS Mask               */
-#define SCU_SFSP4_4_EZI_Pos                                   6                                                         /*!< SCU SFSP4_4: EZI Position           */
-#define SCU_SFSP4_4_EZI_Msk                                   (0x01UL << SCU_SFSP4_4_EZI_Pos)                           /*!< SCU SFSP4_4: EZI Mask               */
-#define SCU_SFSP4_4_EHD_Pos                                   8                                                         /*!< SCU SFSP4_4: EHD Position           */
-#define SCU_SFSP4_4_EHD_Msk                                   (0x03UL << SCU_SFSP4_4_EHD_Pos)                           /*!< SCU SFSP4_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_5  ------------------------------------------
-#define SCU_SFSP4_5_MODE_Pos                                  0                                                         /*!< SCU SFSP4_5: MODE Position          */
-#define SCU_SFSP4_5_MODE_Msk                                  (0x07UL << SCU_SFSP4_5_MODE_Pos)                          /*!< SCU SFSP4_5: MODE Mask              */
-#define SCU_SFSP4_5_EPD_Pos                                   3                                                         /*!< SCU SFSP4_5: EPD Position           */
-#define SCU_SFSP4_5_EPD_Msk                                   (0x01UL << SCU_SFSP4_5_EPD_Pos)                           /*!< SCU SFSP4_5: EPD Mask               */
-#define SCU_SFSP4_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_5: EPUN Position          */
-#define SCU_SFSP4_5_EPUN_Msk                                  (0x01UL << SCU_SFSP4_5_EPUN_Pos)                          /*!< SCU SFSP4_5: EPUN Mask              */
-#define SCU_SFSP4_5_EHS_Pos                                   5                                                         /*!< SCU SFSP4_5: EHS Position           */
-#define SCU_SFSP4_5_EHS_Msk                                   (0x01UL << SCU_SFSP4_5_EHS_Pos)                           /*!< SCU SFSP4_5: EHS Mask               */
-#define SCU_SFSP4_5_EZI_Pos                                   6                                                         /*!< SCU SFSP4_5: EZI Position           */
-#define SCU_SFSP4_5_EZI_Msk                                   (0x01UL << SCU_SFSP4_5_EZI_Pos)                           /*!< SCU SFSP4_5: EZI Mask               */
-#define SCU_SFSP4_5_EHD_Pos                                   8                                                         /*!< SCU SFSP4_5: EHD Position           */
-#define SCU_SFSP4_5_EHD_Msk                                   (0x03UL << SCU_SFSP4_5_EHD_Pos)                           /*!< SCU SFSP4_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_6  ------------------------------------------
-#define SCU_SFSP4_6_MODE_Pos                                  0                                                         /*!< SCU SFSP4_6: MODE Position          */
-#define SCU_SFSP4_6_MODE_Msk                                  (0x07UL << SCU_SFSP4_6_MODE_Pos)                          /*!< SCU SFSP4_6: MODE Mask              */
-#define SCU_SFSP4_6_EPD_Pos                                   3                                                         /*!< SCU SFSP4_6: EPD Position           */
-#define SCU_SFSP4_6_EPD_Msk                                   (0x01UL << SCU_SFSP4_6_EPD_Pos)                           /*!< SCU SFSP4_6: EPD Mask               */
-#define SCU_SFSP4_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_6: EPUN Position          */
-#define SCU_SFSP4_6_EPUN_Msk                                  (0x01UL << SCU_SFSP4_6_EPUN_Pos)                          /*!< SCU SFSP4_6: EPUN Mask              */
-#define SCU_SFSP4_6_EHS_Pos                                   5                                                         /*!< SCU SFSP4_6: EHS Position           */
-#define SCU_SFSP4_6_EHS_Msk                                   (0x01UL << SCU_SFSP4_6_EHS_Pos)                           /*!< SCU SFSP4_6: EHS Mask               */
-#define SCU_SFSP4_6_EZI_Pos                                   6                                                         /*!< SCU SFSP4_6: EZI Position           */
-#define SCU_SFSP4_6_EZI_Msk                                   (0x01UL << SCU_SFSP4_6_EZI_Pos)                           /*!< SCU SFSP4_6: EZI Mask               */
-#define SCU_SFSP4_6_EHD_Pos                                   8                                                         /*!< SCU SFSP4_6: EHD Position           */
-#define SCU_SFSP4_6_EHD_Msk                                   (0x03UL << SCU_SFSP4_6_EHD_Pos)                           /*!< SCU SFSP4_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_7  ------------------------------------------
-#define SCU_SFSP4_7_MODE_Pos                                  0                                                         /*!< SCU SFSP4_7: MODE Position          */
-#define SCU_SFSP4_7_MODE_Msk                                  (0x07UL << SCU_SFSP4_7_MODE_Pos)                          /*!< SCU SFSP4_7: MODE Mask              */
-#define SCU_SFSP4_7_EPD_Pos                                   3                                                         /*!< SCU SFSP4_7: EPD Position           */
-#define SCU_SFSP4_7_EPD_Msk                                   (0x01UL << SCU_SFSP4_7_EPD_Pos)                           /*!< SCU SFSP4_7: EPD Mask               */
-#define SCU_SFSP4_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_7: EPUN Position          */
-#define SCU_SFSP4_7_EPUN_Msk                                  (0x01UL << SCU_SFSP4_7_EPUN_Pos)                          /*!< SCU SFSP4_7: EPUN Mask              */
-#define SCU_SFSP4_7_EHS_Pos                                   5                                                         /*!< SCU SFSP4_7: EHS Position           */
-#define SCU_SFSP4_7_EHS_Msk                                   (0x01UL << SCU_SFSP4_7_EHS_Pos)                           /*!< SCU SFSP4_7: EHS Mask               */
-#define SCU_SFSP4_7_EZI_Pos                                   6                                                         /*!< SCU SFSP4_7: EZI Position           */
-#define SCU_SFSP4_7_EZI_Msk                                   (0x01UL << SCU_SFSP4_7_EZI_Pos)                           /*!< SCU SFSP4_7: EZI Mask               */
-#define SCU_SFSP4_7_EHD_Pos                                   8                                                         /*!< SCU SFSP4_7: EHD Position           */
-#define SCU_SFSP4_7_EHD_Msk                                   (0x03UL << SCU_SFSP4_7_EHD_Pos)                           /*!< SCU SFSP4_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_8  ------------------------------------------
-#define SCU_SFSP4_8_MODE_Pos                                  0                                                         /*!< SCU SFSP4_8: MODE Position          */
-#define SCU_SFSP4_8_MODE_Msk                                  (0x07UL << SCU_SFSP4_8_MODE_Pos)                          /*!< SCU SFSP4_8: MODE Mask              */
-#define SCU_SFSP4_8_EPD_Pos                                   3                                                         /*!< SCU SFSP4_8: EPD Position           */
-#define SCU_SFSP4_8_EPD_Msk                                   (0x01UL << SCU_SFSP4_8_EPD_Pos)                           /*!< SCU SFSP4_8: EPD Mask               */
-#define SCU_SFSP4_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_8: EPUN Position          */
-#define SCU_SFSP4_8_EPUN_Msk                                  (0x01UL << SCU_SFSP4_8_EPUN_Pos)                          /*!< SCU SFSP4_8: EPUN Mask              */
-#define SCU_SFSP4_8_EHS_Pos                                   5                                                         /*!< SCU SFSP4_8: EHS Position           */
-#define SCU_SFSP4_8_EHS_Msk                                   (0x01UL << SCU_SFSP4_8_EHS_Pos)                           /*!< SCU SFSP4_8: EHS Mask               */
-#define SCU_SFSP4_8_EZI_Pos                                   6                                                         /*!< SCU SFSP4_8: EZI Position           */
-#define SCU_SFSP4_8_EZI_Msk                                   (0x01UL << SCU_SFSP4_8_EZI_Pos)                           /*!< SCU SFSP4_8: EZI Mask               */
-#define SCU_SFSP4_8_EHD_Pos                                   8                                                         /*!< SCU SFSP4_8: EHD Position           */
-#define SCU_SFSP4_8_EHD_Msk                                   (0x03UL << SCU_SFSP4_8_EHD_Pos)                           /*!< SCU SFSP4_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP4_9  ------------------------------------------
-#define SCU_SFSP4_9_MODE_Pos                                  0                                                         /*!< SCU SFSP4_9: MODE Position          */
-#define SCU_SFSP4_9_MODE_Msk                                  (0x07UL << SCU_SFSP4_9_MODE_Pos)                          /*!< SCU SFSP4_9: MODE Mask              */
-#define SCU_SFSP4_9_EPD_Pos                                   3                                                         /*!< SCU SFSP4_9: EPD Position           */
-#define SCU_SFSP4_9_EPD_Msk                                   (0x01UL << SCU_SFSP4_9_EPD_Pos)                           /*!< SCU SFSP4_9: EPD Mask               */
-#define SCU_SFSP4_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP4_9: EPUN Position          */
-#define SCU_SFSP4_9_EPUN_Msk                                  (0x01UL << SCU_SFSP4_9_EPUN_Pos)                          /*!< SCU SFSP4_9: EPUN Mask              */
-#define SCU_SFSP4_9_EHS_Pos                                   5                                                         /*!< SCU SFSP4_9: EHS Position           */
-#define SCU_SFSP4_9_EHS_Msk                                   (0x01UL << SCU_SFSP4_9_EHS_Pos)                           /*!< SCU SFSP4_9: EHS Mask               */
-#define SCU_SFSP4_9_EZI_Pos                                   6                                                         /*!< SCU SFSP4_9: EZI Position           */
-#define SCU_SFSP4_9_EZI_Msk                                   (0x01UL << SCU_SFSP4_9_EZI_Pos)                           /*!< SCU SFSP4_9: EZI Mask               */
-#define SCU_SFSP4_9_EHD_Pos                                   8                                                         /*!< SCU SFSP4_9: EHD Position           */
-#define SCU_SFSP4_9_EHD_Msk                                   (0x03UL << SCU_SFSP4_9_EHD_Pos)                           /*!< SCU SFSP4_9: EHD Mask               */
-
-// --------------------------------------  SCU_SFSP4_10  ------------------------------------------
-#define SCU_SFSP4_10_MODE_Pos                                 0                                                         /*!< SCU SFSP4_10: MODE Position         */
-#define SCU_SFSP4_10_MODE_Msk                                 (0x07UL << SCU_SFSP4_10_MODE_Pos)                         /*!< SCU SFSP4_10: MODE Mask             */
-#define SCU_SFSP4_10_EPD_Pos                                  3                                                         /*!< SCU SFSP4_10: EPD Position          */
-#define SCU_SFSP4_10_EPD_Msk                                  (0x01UL << SCU_SFSP4_10_EPD_Pos)                          /*!< SCU SFSP4_10: EPD Mask              */
-#define SCU_SFSP4_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP4_10: EPUN Position         */
-#define SCU_SFSP4_10_EPUN_Msk                                 (0x01UL << SCU_SFSP4_10_EPUN_Pos)                         /*!< SCU SFSP4_10: EPUN Mask             */
-#define SCU_SFSP4_10_EHS_Pos                                  5                                                         /*!< SCU SFSP4_10: EHS Position          */
-#define SCU_SFSP4_10_EHS_Msk                                  (0x01UL << SCU_SFSP4_10_EHS_Pos)                          /*!< SCU SFSP4_10: EHS Mask              */
-#define SCU_SFSP4_10_EZI_Pos                                  6                                                         /*!< SCU SFSP4_10: EZI Position          */
-#define SCU_SFSP4_10_EZI_Msk                                  (0x01UL << SCU_SFSP4_10_EZI_Pos)                          /*!< SCU SFSP4_10: EZI Mask              */
-#define SCU_SFSP4_10_EHD_Pos                                  8                                                         /*!< SCU SFSP4_10: EHD Position          */
-#define SCU_SFSP4_10_EHD_Msk                                  (0x03UL << SCU_SFSP4_10_EHD_Pos)                          /*!< SCU SFSP4_10: EHD Mask              */
-
-// ---------------------------------------  SCU_SFSP5_0  ------------------------------------------
-#define SCU_SFSP5_0_MODE_Pos                                  0                                                         /*!< SCU SFSP5_0: MODE Position          */
-#define SCU_SFSP5_0_MODE_Msk                                  (0x07UL << SCU_SFSP5_0_MODE_Pos)                          /*!< SCU SFSP5_0: MODE Mask              */
-#define SCU_SFSP5_0_EPD_Pos                                   3                                                         /*!< SCU SFSP5_0: EPD Position           */
-#define SCU_SFSP5_0_EPD_Msk                                   (0x01UL << SCU_SFSP5_0_EPD_Pos)                           /*!< SCU SFSP5_0: EPD Mask               */
-#define SCU_SFSP5_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_0: EPUN Position          */
-#define SCU_SFSP5_0_EPUN_Msk                                  (0x01UL << SCU_SFSP5_0_EPUN_Pos)                          /*!< SCU SFSP5_0: EPUN Mask              */
-#define SCU_SFSP5_0_EHS_Pos                                   5                                                         /*!< SCU SFSP5_0: EHS Position           */
-#define SCU_SFSP5_0_EHS_Msk                                   (0x01UL << SCU_SFSP5_0_EHS_Pos)                           /*!< SCU SFSP5_0: EHS Mask               */
-#define SCU_SFSP5_0_EZI_Pos                                   6                                                         /*!< SCU SFSP5_0: EZI Position           */
-#define SCU_SFSP5_0_EZI_Msk                                   (0x01UL << SCU_SFSP5_0_EZI_Pos)                           /*!< SCU SFSP5_0: EZI Mask               */
-#define SCU_SFSP5_0_EHD_Pos                                   8                                                         /*!< SCU SFSP5_0: EHD Position           */
-#define SCU_SFSP5_0_EHD_Msk                                   (0x03UL << SCU_SFSP5_0_EHD_Pos)                           /*!< SCU SFSP5_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP5_1  ------------------------------------------
-#define SCU_SFSP5_1_MODE_Pos                                  0                                                         /*!< SCU SFSP5_1: MODE Position          */
-#define SCU_SFSP5_1_MODE_Msk                                  (0x07UL << SCU_SFSP5_1_MODE_Pos)                          /*!< SCU SFSP5_1: MODE Mask              */
-#define SCU_SFSP5_1_EPD_Pos                                   3                                                         /*!< SCU SFSP5_1: EPD Position           */
-#define SCU_SFSP5_1_EPD_Msk                                   (0x01UL << SCU_SFSP5_1_EPD_Pos)                           /*!< SCU SFSP5_1: EPD Mask               */
-#define SCU_SFSP5_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_1: EPUN Position          */
-#define SCU_SFSP5_1_EPUN_Msk                                  (0x01UL << SCU_SFSP5_1_EPUN_Pos)                          /*!< SCU SFSP5_1: EPUN Mask              */
-#define SCU_SFSP5_1_EHS_Pos                                   5                                                         /*!< SCU SFSP5_1: EHS Position           */
-#define SCU_SFSP5_1_EHS_Msk                                   (0x01UL << SCU_SFSP5_1_EHS_Pos)                           /*!< SCU SFSP5_1: EHS Mask               */
-#define SCU_SFSP5_1_EZI_Pos                                   6                                                         /*!< SCU SFSP5_1: EZI Position           */
-#define SCU_SFSP5_1_EZI_Msk                                   (0x01UL << SCU_SFSP5_1_EZI_Pos)                           /*!< SCU SFSP5_1: EZI Mask               */
-#define SCU_SFSP5_1_EHD_Pos                                   8                                                         /*!< SCU SFSP5_1: EHD Position           */
-#define SCU_SFSP5_1_EHD_Msk                                   (0x03UL << SCU_SFSP5_1_EHD_Pos)                           /*!< SCU SFSP5_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP5_2  ------------------------------------------
-#define SCU_SFSP5_2_MODE_Pos                                  0                                                         /*!< SCU SFSP5_2: MODE Position          */
-#define SCU_SFSP5_2_MODE_Msk                                  (0x07UL << SCU_SFSP5_2_MODE_Pos)                          /*!< SCU SFSP5_2: MODE Mask              */
-#define SCU_SFSP5_2_EPD_Pos                                   3                                                         /*!< SCU SFSP5_2: EPD Position           */
-#define SCU_SFSP5_2_EPD_Msk                                   (0x01UL << SCU_SFSP5_2_EPD_Pos)                           /*!< SCU SFSP5_2: EPD Mask               */
-#define SCU_SFSP5_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_2: EPUN Position          */
-#define SCU_SFSP5_2_EPUN_Msk                                  (0x01UL << SCU_SFSP5_2_EPUN_Pos)                          /*!< SCU SFSP5_2: EPUN Mask              */
-#define SCU_SFSP5_2_EHS_Pos                                   5                                                         /*!< SCU SFSP5_2: EHS Position           */
-#define SCU_SFSP5_2_EHS_Msk                                   (0x01UL << SCU_SFSP5_2_EHS_Pos)                           /*!< SCU SFSP5_2: EHS Mask               */
-#define SCU_SFSP5_2_EZI_Pos                                   6                                                         /*!< SCU SFSP5_2: EZI Position           */
-#define SCU_SFSP5_2_EZI_Msk                                   (0x01UL << SCU_SFSP5_2_EZI_Pos)                           /*!< SCU SFSP5_2: EZI Mask               */
-#define SCU_SFSP5_2_EHD_Pos                                   8                                                         /*!< SCU SFSP5_2: EHD Position           */
-#define SCU_SFSP5_2_EHD_Msk                                   (0x03UL << SCU_SFSP5_2_EHD_Pos)                           /*!< SCU SFSP5_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP5_3  ------------------------------------------
-#define SCU_SFSP5_3_MODE_Pos                                  0                                                         /*!< SCU SFSP5_3: MODE Position          */
-#define SCU_SFSP5_3_MODE_Msk                                  (0x07UL << SCU_SFSP5_3_MODE_Pos)                          /*!< SCU SFSP5_3: MODE Mask              */
-#define SCU_SFSP5_3_EPD_Pos                                   3                                                         /*!< SCU SFSP5_3: EPD Position           */
-#define SCU_SFSP5_3_EPD_Msk                                   (0x01UL << SCU_SFSP5_3_EPD_Pos)                           /*!< SCU SFSP5_3: EPD Mask               */
-#define SCU_SFSP5_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_3: EPUN Position          */
-#define SCU_SFSP5_3_EPUN_Msk                                  (0x01UL << SCU_SFSP5_3_EPUN_Pos)                          /*!< SCU SFSP5_3: EPUN Mask              */
-#define SCU_SFSP5_3_EHS_Pos                                   5                                                         /*!< SCU SFSP5_3: EHS Position           */
-#define SCU_SFSP5_3_EHS_Msk                                   (0x01UL << SCU_SFSP5_3_EHS_Pos)                           /*!< SCU SFSP5_3: EHS Mask               */
-#define SCU_SFSP5_3_EZI_Pos                                   6                                                         /*!< SCU SFSP5_3: EZI Position           */
-#define SCU_SFSP5_3_EZI_Msk                                   (0x01UL << SCU_SFSP5_3_EZI_Pos)                           /*!< SCU SFSP5_3: EZI Mask               */
-#define SCU_SFSP5_3_EHD_Pos                                   8                                                         /*!< SCU SFSP5_3: EHD Position           */
-#define SCU_SFSP5_3_EHD_Msk                                   (0x03UL << SCU_SFSP5_3_EHD_Pos)                           /*!< SCU SFSP5_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP5_4  ------------------------------------------
-#define SCU_SFSP5_4_MODE_Pos                                  0                                                         /*!< SCU SFSP5_4: MODE Position          */
-#define SCU_SFSP5_4_MODE_Msk                                  (0x07UL << SCU_SFSP5_4_MODE_Pos)                          /*!< SCU SFSP5_4: MODE Mask              */
-#define SCU_SFSP5_4_EPD_Pos                                   3                                                         /*!< SCU SFSP5_4: EPD Position           */
-#define SCU_SFSP5_4_EPD_Msk                                   (0x01UL << SCU_SFSP5_4_EPD_Pos)                           /*!< SCU SFSP5_4: EPD Mask               */
-#define SCU_SFSP5_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_4: EPUN Position          */
-#define SCU_SFSP5_4_EPUN_Msk                                  (0x01UL << SCU_SFSP5_4_EPUN_Pos)                          /*!< SCU SFSP5_4: EPUN Mask              */
-#define SCU_SFSP5_4_EHS_Pos                                   5                                                         /*!< SCU SFSP5_4: EHS Position           */
-#define SCU_SFSP5_4_EHS_Msk                                   (0x01UL << SCU_SFSP5_4_EHS_Pos)                           /*!< SCU SFSP5_4: EHS Mask               */
-#define SCU_SFSP5_4_EZI_Pos                                   6                                                         /*!< SCU SFSP5_4: EZI Position           */
-#define SCU_SFSP5_4_EZI_Msk                                   (0x01UL << SCU_SFSP5_4_EZI_Pos)                           /*!< SCU SFSP5_4: EZI Mask               */
-#define SCU_SFSP5_4_EHD_Pos                                   8                                                         /*!< SCU SFSP5_4: EHD Position           */
-#define SCU_SFSP5_4_EHD_Msk                                   (0x03UL << SCU_SFSP5_4_EHD_Pos)                           /*!< SCU SFSP5_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP5_5  ------------------------------------------
-#define SCU_SFSP5_5_MODE_Pos                                  0                                                         /*!< SCU SFSP5_5: MODE Position          */
-#define SCU_SFSP5_5_MODE_Msk                                  (0x07UL << SCU_SFSP5_5_MODE_Pos)                          /*!< SCU SFSP5_5: MODE Mask              */
-#define SCU_SFSP5_5_EPD_Pos                                   3                                                         /*!< SCU SFSP5_5: EPD Position           */
-#define SCU_SFSP5_5_EPD_Msk                                   (0x01UL << SCU_SFSP5_5_EPD_Pos)                           /*!< SCU SFSP5_5: EPD Mask               */
-#define SCU_SFSP5_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_5: EPUN Position          */
-#define SCU_SFSP5_5_EPUN_Msk                                  (0x01UL << SCU_SFSP5_5_EPUN_Pos)                          /*!< SCU SFSP5_5: EPUN Mask              */
-#define SCU_SFSP5_5_EHS_Pos                                   5                                                         /*!< SCU SFSP5_5: EHS Position           */
-#define SCU_SFSP5_5_EHS_Msk                                   (0x01UL << SCU_SFSP5_5_EHS_Pos)                           /*!< SCU SFSP5_5: EHS Mask               */
-#define SCU_SFSP5_5_EZI_Pos                                   6                                                         /*!< SCU SFSP5_5: EZI Position           */
-#define SCU_SFSP5_5_EZI_Msk                                   (0x01UL << SCU_SFSP5_5_EZI_Pos)                           /*!< SCU SFSP5_5: EZI Mask               */
-#define SCU_SFSP5_5_EHD_Pos                                   8                                                         /*!< SCU SFSP5_5: EHD Position           */
-#define SCU_SFSP5_5_EHD_Msk                                   (0x03UL << SCU_SFSP5_5_EHD_Pos)                           /*!< SCU SFSP5_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP5_6  ------------------------------------------
-#define SCU_SFSP5_6_MODE_Pos                                  0                                                         /*!< SCU SFSP5_6: MODE Position          */
-#define SCU_SFSP5_6_MODE_Msk                                  (0x07UL << SCU_SFSP5_6_MODE_Pos)                          /*!< SCU SFSP5_6: MODE Mask              */
-#define SCU_SFSP5_6_EPD_Pos                                   3                                                         /*!< SCU SFSP5_6: EPD Position           */
-#define SCU_SFSP5_6_EPD_Msk                                   (0x01UL << SCU_SFSP5_6_EPD_Pos)                           /*!< SCU SFSP5_6: EPD Mask               */
-#define SCU_SFSP5_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_6: EPUN Position          */
-#define SCU_SFSP5_6_EPUN_Msk                                  (0x01UL << SCU_SFSP5_6_EPUN_Pos)                          /*!< SCU SFSP5_6: EPUN Mask              */
-#define SCU_SFSP5_6_EHS_Pos                                   5                                                         /*!< SCU SFSP5_6: EHS Position           */
-#define SCU_SFSP5_6_EHS_Msk                                   (0x01UL << SCU_SFSP5_6_EHS_Pos)                           /*!< SCU SFSP5_6: EHS Mask               */
-#define SCU_SFSP5_6_EZI_Pos                                   6                                                         /*!< SCU SFSP5_6: EZI Position           */
-#define SCU_SFSP5_6_EZI_Msk                                   (0x01UL << SCU_SFSP5_6_EZI_Pos)                           /*!< SCU SFSP5_6: EZI Mask               */
-#define SCU_SFSP5_6_EHD_Pos                                   8                                                         /*!< SCU SFSP5_6: EHD Position           */
-#define SCU_SFSP5_6_EHD_Msk                                   (0x03UL << SCU_SFSP5_6_EHD_Pos)                           /*!< SCU SFSP5_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP5_7  ------------------------------------------
-#define SCU_SFSP5_7_MODE_Pos                                  0                                                         /*!< SCU SFSP5_7: MODE Position          */
-#define SCU_SFSP5_7_MODE_Msk                                  (0x07UL << SCU_SFSP5_7_MODE_Pos)                          /*!< SCU SFSP5_7: MODE Mask              */
-#define SCU_SFSP5_7_EPD_Pos                                   3                                                         /*!< SCU SFSP5_7: EPD Position           */
-#define SCU_SFSP5_7_EPD_Msk                                   (0x01UL << SCU_SFSP5_7_EPD_Pos)                           /*!< SCU SFSP5_7: EPD Mask               */
-#define SCU_SFSP5_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP5_7: EPUN Position          */
-#define SCU_SFSP5_7_EPUN_Msk                                  (0x01UL << SCU_SFSP5_7_EPUN_Pos)                          /*!< SCU SFSP5_7: EPUN Mask              */
-#define SCU_SFSP5_7_EHS_Pos                                   5                                                         /*!< SCU SFSP5_7: EHS Position           */
-#define SCU_SFSP5_7_EHS_Msk                                   (0x01UL << SCU_SFSP5_7_EHS_Pos)                           /*!< SCU SFSP5_7: EHS Mask               */
-#define SCU_SFSP5_7_EZI_Pos                                   6                                                         /*!< SCU SFSP5_7: EZI Position           */
-#define SCU_SFSP5_7_EZI_Msk                                   (0x01UL << SCU_SFSP5_7_EZI_Pos)                           /*!< SCU SFSP5_7: EZI Mask               */
-#define SCU_SFSP5_7_EHD_Pos                                   8                                                         /*!< SCU SFSP5_7: EHD Position           */
-#define SCU_SFSP5_7_EHD_Msk                                   (0x03UL << SCU_SFSP5_7_EHD_Pos)                           /*!< SCU SFSP5_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_0  ------------------------------------------
-#define SCU_SFSP6_0_MODE_Pos                                  0                                                         /*!< SCU SFSP6_0: MODE Position          */
-#define SCU_SFSP6_0_MODE_Msk                                  (0x07UL << SCU_SFSP6_0_MODE_Pos)                          /*!< SCU SFSP6_0: MODE Mask              */
-#define SCU_SFSP6_0_EPD_Pos                                   3                                                         /*!< SCU SFSP6_0: EPD Position           */
-#define SCU_SFSP6_0_EPD_Msk                                   (0x01UL << SCU_SFSP6_0_EPD_Pos)                           /*!< SCU SFSP6_0: EPD Mask               */
-#define SCU_SFSP6_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_0: EPUN Position          */
-#define SCU_SFSP6_0_EPUN_Msk                                  (0x01UL << SCU_SFSP6_0_EPUN_Pos)                          /*!< SCU SFSP6_0: EPUN Mask              */
-#define SCU_SFSP6_0_EHS_Pos                                   5                                                         /*!< SCU SFSP6_0: EHS Position           */
-#define SCU_SFSP6_0_EHS_Msk                                   (0x01UL << SCU_SFSP6_0_EHS_Pos)                           /*!< SCU SFSP6_0: EHS Mask               */
-#define SCU_SFSP6_0_EZI_Pos                                   6                                                         /*!< SCU SFSP6_0: EZI Position           */
-#define SCU_SFSP6_0_EZI_Msk                                   (0x01UL << SCU_SFSP6_0_EZI_Pos)                           /*!< SCU SFSP6_0: EZI Mask               */
-#define SCU_SFSP6_0_EHD_Pos                                   8                                                         /*!< SCU SFSP6_0: EHD Position           */
-#define SCU_SFSP6_0_EHD_Msk                                   (0x03UL << SCU_SFSP6_0_EHD_Pos)                           /*!< SCU SFSP6_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_1  ------------------------------------------
-#define SCU_SFSP6_1_MODE_Pos                                  0                                                         /*!< SCU SFSP6_1: MODE Position          */
-#define SCU_SFSP6_1_MODE_Msk                                  (0x07UL << SCU_SFSP6_1_MODE_Pos)                          /*!< SCU SFSP6_1: MODE Mask              */
-#define SCU_SFSP6_1_EPD_Pos                                   3                                                         /*!< SCU SFSP6_1: EPD Position           */
-#define SCU_SFSP6_1_EPD_Msk                                   (0x01UL << SCU_SFSP6_1_EPD_Pos)                           /*!< SCU SFSP6_1: EPD Mask               */
-#define SCU_SFSP6_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_1: EPUN Position          */
-#define SCU_SFSP6_1_EPUN_Msk                                  (0x01UL << SCU_SFSP6_1_EPUN_Pos)                          /*!< SCU SFSP6_1: EPUN Mask              */
-#define SCU_SFSP6_1_EHS_Pos                                   5                                                         /*!< SCU SFSP6_1: EHS Position           */
-#define SCU_SFSP6_1_EHS_Msk                                   (0x01UL << SCU_SFSP6_1_EHS_Pos)                           /*!< SCU SFSP6_1: EHS Mask               */
-#define SCU_SFSP6_1_EZI_Pos                                   6                                                         /*!< SCU SFSP6_1: EZI Position           */
-#define SCU_SFSP6_1_EZI_Msk                                   (0x01UL << SCU_SFSP6_1_EZI_Pos)                           /*!< SCU SFSP6_1: EZI Mask               */
-#define SCU_SFSP6_1_EHD_Pos                                   8                                                         /*!< SCU SFSP6_1: EHD Position           */
-#define SCU_SFSP6_1_EHD_Msk                                   (0x03UL << SCU_SFSP6_1_EHD_Pos)                           /*!< SCU SFSP6_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_2  ------------------------------------------
-#define SCU_SFSP6_2_MODE_Pos                                  0                                                         /*!< SCU SFSP6_2: MODE Position          */
-#define SCU_SFSP6_2_MODE_Msk                                  (0x07UL << SCU_SFSP6_2_MODE_Pos)                          /*!< SCU SFSP6_2: MODE Mask              */
-#define SCU_SFSP6_2_EPD_Pos                                   3                                                         /*!< SCU SFSP6_2: EPD Position           */
-#define SCU_SFSP6_2_EPD_Msk                                   (0x01UL << SCU_SFSP6_2_EPD_Pos)                           /*!< SCU SFSP6_2: EPD Mask               */
-#define SCU_SFSP6_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_2: EPUN Position          */
-#define SCU_SFSP6_2_EPUN_Msk                                  (0x01UL << SCU_SFSP6_2_EPUN_Pos)                          /*!< SCU SFSP6_2: EPUN Mask              */
-#define SCU_SFSP6_2_EHS_Pos                                   5                                                         /*!< SCU SFSP6_2: EHS Position           */
-#define SCU_SFSP6_2_EHS_Msk                                   (0x01UL << SCU_SFSP6_2_EHS_Pos)                           /*!< SCU SFSP6_2: EHS Mask               */
-#define SCU_SFSP6_2_EZI_Pos                                   6                                                         /*!< SCU SFSP6_2: EZI Position           */
-#define SCU_SFSP6_2_EZI_Msk                                   (0x01UL << SCU_SFSP6_2_EZI_Pos)                           /*!< SCU SFSP6_2: EZI Mask               */
-#define SCU_SFSP6_2_EHD_Pos                                   8                                                         /*!< SCU SFSP6_2: EHD Position           */
-#define SCU_SFSP6_2_EHD_Msk                                   (0x03UL << SCU_SFSP6_2_EHD_Pos)                           /*!< SCU SFSP6_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_3  ------------------------------------------
-#define SCU_SFSP6_3_MODE_Pos                                  0                                                         /*!< SCU SFSP6_3: MODE Position          */
-#define SCU_SFSP6_3_MODE_Msk                                  (0x07UL << SCU_SFSP6_3_MODE_Pos)                          /*!< SCU SFSP6_3: MODE Mask              */
-#define SCU_SFSP6_3_EPD_Pos                                   3                                                         /*!< SCU SFSP6_3: EPD Position           */
-#define SCU_SFSP6_3_EPD_Msk                                   (0x01UL << SCU_SFSP6_3_EPD_Pos)                           /*!< SCU SFSP6_3: EPD Mask               */
-#define SCU_SFSP6_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_3: EPUN Position          */
-#define SCU_SFSP6_3_EPUN_Msk                                  (0x01UL << SCU_SFSP6_3_EPUN_Pos)                          /*!< SCU SFSP6_3: EPUN Mask              */
-#define SCU_SFSP6_3_EHS_Pos                                   5                                                         /*!< SCU SFSP6_3: EHS Position           */
-#define SCU_SFSP6_3_EHS_Msk                                   (0x01UL << SCU_SFSP6_3_EHS_Pos)                           /*!< SCU SFSP6_3: EHS Mask               */
-#define SCU_SFSP6_3_EZI_Pos                                   6                                                         /*!< SCU SFSP6_3: EZI Position           */
-#define SCU_SFSP6_3_EZI_Msk                                   (0x01UL << SCU_SFSP6_3_EZI_Pos)                           /*!< SCU SFSP6_3: EZI Mask               */
-#define SCU_SFSP6_3_EHD_Pos                                   8                                                         /*!< SCU SFSP6_3: EHD Position           */
-#define SCU_SFSP6_3_EHD_Msk                                   (0x03UL << SCU_SFSP6_3_EHD_Pos)                           /*!< SCU SFSP6_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_4  ------------------------------------------
-#define SCU_SFSP6_4_MODE_Pos                                  0                                                         /*!< SCU SFSP6_4: MODE Position          */
-#define SCU_SFSP6_4_MODE_Msk                                  (0x07UL << SCU_SFSP6_4_MODE_Pos)                          /*!< SCU SFSP6_4: MODE Mask              */
-#define SCU_SFSP6_4_EPD_Pos                                   3                                                         /*!< SCU SFSP6_4: EPD Position           */
-#define SCU_SFSP6_4_EPD_Msk                                   (0x01UL << SCU_SFSP6_4_EPD_Pos)                           /*!< SCU SFSP6_4: EPD Mask               */
-#define SCU_SFSP6_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_4: EPUN Position          */
-#define SCU_SFSP6_4_EPUN_Msk                                  (0x01UL << SCU_SFSP6_4_EPUN_Pos)                          /*!< SCU SFSP6_4: EPUN Mask              */
-#define SCU_SFSP6_4_EHS_Pos                                   5                                                         /*!< SCU SFSP6_4: EHS Position           */
-#define SCU_SFSP6_4_EHS_Msk                                   (0x01UL << SCU_SFSP6_4_EHS_Pos)                           /*!< SCU SFSP6_4: EHS Mask               */
-#define SCU_SFSP6_4_EZI_Pos                                   6                                                         /*!< SCU SFSP6_4: EZI Position           */
-#define SCU_SFSP6_4_EZI_Msk                                   (0x01UL << SCU_SFSP6_4_EZI_Pos)                           /*!< SCU SFSP6_4: EZI Mask               */
-#define SCU_SFSP6_4_EHD_Pos                                   8                                                         /*!< SCU SFSP6_4: EHD Position           */
-#define SCU_SFSP6_4_EHD_Msk                                   (0x03UL << SCU_SFSP6_4_EHD_Pos)                           /*!< SCU SFSP6_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_5  ------------------------------------------
-#define SCU_SFSP6_5_MODE_Pos                                  0                                                         /*!< SCU SFSP6_5: MODE Position          */
-#define SCU_SFSP6_5_MODE_Msk                                  (0x07UL << SCU_SFSP6_5_MODE_Pos)                          /*!< SCU SFSP6_5: MODE Mask              */
-#define SCU_SFSP6_5_EPD_Pos                                   3                                                         /*!< SCU SFSP6_5: EPD Position           */
-#define SCU_SFSP6_5_EPD_Msk                                   (0x01UL << SCU_SFSP6_5_EPD_Pos)                           /*!< SCU SFSP6_5: EPD Mask               */
-#define SCU_SFSP6_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_5: EPUN Position          */
-#define SCU_SFSP6_5_EPUN_Msk                                  (0x01UL << SCU_SFSP6_5_EPUN_Pos)                          /*!< SCU SFSP6_5: EPUN Mask              */
-#define SCU_SFSP6_5_EHS_Pos                                   5                                                         /*!< SCU SFSP6_5: EHS Position           */
-#define SCU_SFSP6_5_EHS_Msk                                   (0x01UL << SCU_SFSP6_5_EHS_Pos)                           /*!< SCU SFSP6_5: EHS Mask               */
-#define SCU_SFSP6_5_EZI_Pos                                   6                                                         /*!< SCU SFSP6_5: EZI Position           */
-#define SCU_SFSP6_5_EZI_Msk                                   (0x01UL << SCU_SFSP6_5_EZI_Pos)                           /*!< SCU SFSP6_5: EZI Mask               */
-#define SCU_SFSP6_5_EHD_Pos                                   8                                                         /*!< SCU SFSP6_5: EHD Position           */
-#define SCU_SFSP6_5_EHD_Msk                                   (0x03UL << SCU_SFSP6_5_EHD_Pos)                           /*!< SCU SFSP6_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_6  ------------------------------------------
-#define SCU_SFSP6_6_MODE_Pos                                  0                                                         /*!< SCU SFSP6_6: MODE Position          */
-#define SCU_SFSP6_6_MODE_Msk                                  (0x07UL << SCU_SFSP6_6_MODE_Pos)                          /*!< SCU SFSP6_6: MODE Mask              */
-#define SCU_SFSP6_6_EPD_Pos                                   3                                                         /*!< SCU SFSP6_6: EPD Position           */
-#define SCU_SFSP6_6_EPD_Msk                                   (0x01UL << SCU_SFSP6_6_EPD_Pos)                           /*!< SCU SFSP6_6: EPD Mask               */
-#define SCU_SFSP6_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_6: EPUN Position          */
-#define SCU_SFSP6_6_EPUN_Msk                                  (0x01UL << SCU_SFSP6_6_EPUN_Pos)                          /*!< SCU SFSP6_6: EPUN Mask              */
-#define SCU_SFSP6_6_EHS_Pos                                   5                                                         /*!< SCU SFSP6_6: EHS Position           */
-#define SCU_SFSP6_6_EHS_Msk                                   (0x01UL << SCU_SFSP6_6_EHS_Pos)                           /*!< SCU SFSP6_6: EHS Mask               */
-#define SCU_SFSP6_6_EZI_Pos                                   6                                                         /*!< SCU SFSP6_6: EZI Position           */
-#define SCU_SFSP6_6_EZI_Msk                                   (0x01UL << SCU_SFSP6_6_EZI_Pos)                           /*!< SCU SFSP6_6: EZI Mask               */
-#define SCU_SFSP6_6_EHD_Pos                                   8                                                         /*!< SCU SFSP6_6: EHD Position           */
-#define SCU_SFSP6_6_EHD_Msk                                   (0x03UL << SCU_SFSP6_6_EHD_Pos)                           /*!< SCU SFSP6_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_7  ------------------------------------------
-#define SCU_SFSP6_7_MODE_Pos                                  0                                                         /*!< SCU SFSP6_7: MODE Position          */
-#define SCU_SFSP6_7_MODE_Msk                                  (0x07UL << SCU_SFSP6_7_MODE_Pos)                          /*!< SCU SFSP6_7: MODE Mask              */
-#define SCU_SFSP6_7_EPD_Pos                                   3                                                         /*!< SCU SFSP6_7: EPD Position           */
-#define SCU_SFSP6_7_EPD_Msk                                   (0x01UL << SCU_SFSP6_7_EPD_Pos)                           /*!< SCU SFSP6_7: EPD Mask               */
-#define SCU_SFSP6_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_7: EPUN Position          */
-#define SCU_SFSP6_7_EPUN_Msk                                  (0x01UL << SCU_SFSP6_7_EPUN_Pos)                          /*!< SCU SFSP6_7: EPUN Mask              */
-#define SCU_SFSP6_7_EHS_Pos                                   5                                                         /*!< SCU SFSP6_7: EHS Position           */
-#define SCU_SFSP6_7_EHS_Msk                                   (0x01UL << SCU_SFSP6_7_EHS_Pos)                           /*!< SCU SFSP6_7: EHS Mask               */
-#define SCU_SFSP6_7_EZI_Pos                                   6                                                         /*!< SCU SFSP6_7: EZI Position           */
-#define SCU_SFSP6_7_EZI_Msk                                   (0x01UL << SCU_SFSP6_7_EZI_Pos)                           /*!< SCU SFSP6_7: EZI Mask               */
-#define SCU_SFSP6_7_EHD_Pos                                   8                                                         /*!< SCU SFSP6_7: EHD Position           */
-#define SCU_SFSP6_7_EHD_Msk                                   (0x03UL << SCU_SFSP6_7_EHD_Pos)                           /*!< SCU SFSP6_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_8  ------------------------------------------
-#define SCU_SFSP6_8_MODE_Pos                                  0                                                         /*!< SCU SFSP6_8: MODE Position          */
-#define SCU_SFSP6_8_MODE_Msk                                  (0x07UL << SCU_SFSP6_8_MODE_Pos)                          /*!< SCU SFSP6_8: MODE Mask              */
-#define SCU_SFSP6_8_EPD_Pos                                   3                                                         /*!< SCU SFSP6_8: EPD Position           */
-#define SCU_SFSP6_8_EPD_Msk                                   (0x01UL << SCU_SFSP6_8_EPD_Pos)                           /*!< SCU SFSP6_8: EPD Mask               */
-#define SCU_SFSP6_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_8: EPUN Position          */
-#define SCU_SFSP6_8_EPUN_Msk                                  (0x01UL << SCU_SFSP6_8_EPUN_Pos)                          /*!< SCU SFSP6_8: EPUN Mask              */
-#define SCU_SFSP6_8_EHS_Pos                                   5                                                         /*!< SCU SFSP6_8: EHS Position           */
-#define SCU_SFSP6_8_EHS_Msk                                   (0x01UL << SCU_SFSP6_8_EHS_Pos)                           /*!< SCU SFSP6_8: EHS Mask               */
-#define SCU_SFSP6_8_EZI_Pos                                   6                                                         /*!< SCU SFSP6_8: EZI Position           */
-#define SCU_SFSP6_8_EZI_Msk                                   (0x01UL << SCU_SFSP6_8_EZI_Pos)                           /*!< SCU SFSP6_8: EZI Mask               */
-#define SCU_SFSP6_8_EHD_Pos                                   8                                                         /*!< SCU SFSP6_8: EHD Position           */
-#define SCU_SFSP6_8_EHD_Msk                                   (0x03UL << SCU_SFSP6_8_EHD_Pos)                           /*!< SCU SFSP6_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP6_9  ------------------------------------------
-#define SCU_SFSP6_9_MODE_Pos                                  0                                                         /*!< SCU SFSP6_9: MODE Position          */
-#define SCU_SFSP6_9_MODE_Msk                                  (0x07UL << SCU_SFSP6_9_MODE_Pos)                          /*!< SCU SFSP6_9: MODE Mask              */
-#define SCU_SFSP6_9_EPD_Pos                                   3                                                         /*!< SCU SFSP6_9: EPD Position           */
-#define SCU_SFSP6_9_EPD_Msk                                   (0x01UL << SCU_SFSP6_9_EPD_Pos)                           /*!< SCU SFSP6_9: EPD Mask               */
-#define SCU_SFSP6_9_EPUN_Pos                                  4                                                         /*!< SCU SFSP6_9: EPUN Position          */
-#define SCU_SFSP6_9_EPUN_Msk                                  (0x01UL << SCU_SFSP6_9_EPUN_Pos)                          /*!< SCU SFSP6_9: EPUN Mask              */
-#define SCU_SFSP6_9_EHS_Pos                                   5                                                         /*!< SCU SFSP6_9: EHS Position           */
-#define SCU_SFSP6_9_EHS_Msk                                   (0x01UL << SCU_SFSP6_9_EHS_Pos)                           /*!< SCU SFSP6_9: EHS Mask               */
-#define SCU_SFSP6_9_EZI_Pos                                   6                                                         /*!< SCU SFSP6_9: EZI Position           */
-#define SCU_SFSP6_9_EZI_Msk                                   (0x01UL << SCU_SFSP6_9_EZI_Pos)                           /*!< SCU SFSP6_9: EZI Mask               */
-#define SCU_SFSP6_9_EHD_Pos                                   8                                                         /*!< SCU SFSP6_9: EHD Position           */
-#define SCU_SFSP6_9_EHD_Msk                                   (0x03UL << SCU_SFSP6_9_EHD_Pos)                           /*!< SCU SFSP6_9: EHD Mask               */
-
-// --------------------------------------  SCU_SFSP6_10  ------------------------------------------
-#define SCU_SFSP6_10_MODE_Pos                                 0                                                         /*!< SCU SFSP6_10: MODE Position         */
-#define SCU_SFSP6_10_MODE_Msk                                 (0x07UL << SCU_SFSP6_10_MODE_Pos)                         /*!< SCU SFSP6_10: MODE Mask             */
-#define SCU_SFSP6_10_EPD_Pos                                  3                                                         /*!< SCU SFSP6_10: EPD Position          */
-#define SCU_SFSP6_10_EPD_Msk                                  (0x01UL << SCU_SFSP6_10_EPD_Pos)                          /*!< SCU SFSP6_10: EPD Mask              */
-#define SCU_SFSP6_10_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_10: EPUN Position         */
-#define SCU_SFSP6_10_EPUN_Msk                                 (0x01UL << SCU_SFSP6_10_EPUN_Pos)                         /*!< SCU SFSP6_10: EPUN Mask             */
-#define SCU_SFSP6_10_EHS_Pos                                  5                                                         /*!< SCU SFSP6_10: EHS Position          */
-#define SCU_SFSP6_10_EHS_Msk                                  (0x01UL << SCU_SFSP6_10_EHS_Pos)                          /*!< SCU SFSP6_10: EHS Mask              */
-#define SCU_SFSP6_10_EZI_Pos                                  6                                                         /*!< SCU SFSP6_10: EZI Position          */
-#define SCU_SFSP6_10_EZI_Msk                                  (0x01UL << SCU_SFSP6_10_EZI_Pos)                          /*!< SCU SFSP6_10: EZI Mask              */
-#define SCU_SFSP6_10_EHD_Pos                                  8                                                         /*!< SCU SFSP6_10: EHD Position          */
-#define SCU_SFSP6_10_EHD_Msk                                  (0x03UL << SCU_SFSP6_10_EHD_Pos)                          /*!< SCU SFSP6_10: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP6_11  ------------------------------------------
-#define SCU_SFSP6_11_MODE_Pos                                 0                                                         /*!< SCU SFSP6_11: MODE Position         */
-#define SCU_SFSP6_11_MODE_Msk                                 (0x07UL << SCU_SFSP6_11_MODE_Pos)                         /*!< SCU SFSP6_11: MODE Mask             */
-#define SCU_SFSP6_11_EPD_Pos                                  3                                                         /*!< SCU SFSP6_11: EPD Position          */
-#define SCU_SFSP6_11_EPD_Msk                                  (0x01UL << SCU_SFSP6_11_EPD_Pos)                          /*!< SCU SFSP6_11: EPD Mask              */
-#define SCU_SFSP6_11_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_11: EPUN Position         */
-#define SCU_SFSP6_11_EPUN_Msk                                 (0x01UL << SCU_SFSP6_11_EPUN_Pos)                         /*!< SCU SFSP6_11: EPUN Mask             */
-#define SCU_SFSP6_11_EHS_Pos                                  5                                                         /*!< SCU SFSP6_11: EHS Position          */
-#define SCU_SFSP6_11_EHS_Msk                                  (0x01UL << SCU_SFSP6_11_EHS_Pos)                          /*!< SCU SFSP6_11: EHS Mask              */
-#define SCU_SFSP6_11_EZI_Pos                                  6                                                         /*!< SCU SFSP6_11: EZI Position          */
-#define SCU_SFSP6_11_EZI_Msk                                  (0x01UL << SCU_SFSP6_11_EZI_Pos)                          /*!< SCU SFSP6_11: EZI Mask              */
-#define SCU_SFSP6_11_EHD_Pos                                  8                                                         /*!< SCU SFSP6_11: EHD Position          */
-#define SCU_SFSP6_11_EHD_Msk                                  (0x03UL << SCU_SFSP6_11_EHD_Pos)                          /*!< SCU SFSP6_11: EHD Mask              */
-
-// --------------------------------------  SCU_SFSP6_12  ------------------------------------------
-#define SCU_SFSP6_12_MODE_Pos                                 0                                                         /*!< SCU SFSP6_12: MODE Position         */
-#define SCU_SFSP6_12_MODE_Msk                                 (0x07UL << SCU_SFSP6_12_MODE_Pos)                         /*!< SCU SFSP6_12: MODE Mask             */
-#define SCU_SFSP6_12_EPD_Pos                                  3                                                         /*!< SCU SFSP6_12: EPD Position          */
-#define SCU_SFSP6_12_EPD_Msk                                  (0x01UL << SCU_SFSP6_12_EPD_Pos)                          /*!< SCU SFSP6_12: EPD Mask              */
-#define SCU_SFSP6_12_EPUN_Pos                                 4                                                         /*!< SCU SFSP6_12: EPUN Position         */
-#define SCU_SFSP6_12_EPUN_Msk                                 (0x01UL << SCU_SFSP6_12_EPUN_Pos)                         /*!< SCU SFSP6_12: EPUN Mask             */
-#define SCU_SFSP6_12_EHS_Pos                                  5                                                         /*!< SCU SFSP6_12: EHS Position          */
-#define SCU_SFSP6_12_EHS_Msk                                  (0x01UL << SCU_SFSP6_12_EHS_Pos)                          /*!< SCU SFSP6_12: EHS Mask              */
-#define SCU_SFSP6_12_EZI_Pos                                  6                                                         /*!< SCU SFSP6_12: EZI Position          */
-#define SCU_SFSP6_12_EZI_Msk                                  (0x01UL << SCU_SFSP6_12_EZI_Pos)                          /*!< SCU SFSP6_12: EZI Mask              */
-#define SCU_SFSP6_12_EHD_Pos                                  8                                                         /*!< SCU SFSP6_12: EHD Position          */
-#define SCU_SFSP6_12_EHD_Msk                                  (0x03UL << SCU_SFSP6_12_EHD_Pos)                          /*!< SCU SFSP6_12: EHD Mask              */
-
-// ---------------------------------------  SCU_SFSP7_0  ------------------------------------------
-#define SCU_SFSP7_0_MODE_Pos                                  0                                                         /*!< SCU SFSP7_0: MODE Position          */
-#define SCU_SFSP7_0_MODE_Msk                                  (0x07UL << SCU_SFSP7_0_MODE_Pos)                          /*!< SCU SFSP7_0: MODE Mask              */
-#define SCU_SFSP7_0_EPD_Pos                                   3                                                         /*!< SCU SFSP7_0: EPD Position           */
-#define SCU_SFSP7_0_EPD_Msk                                   (0x01UL << SCU_SFSP7_0_EPD_Pos)                           /*!< SCU SFSP7_0: EPD Mask               */
-#define SCU_SFSP7_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_0: EPUN Position          */
-#define SCU_SFSP7_0_EPUN_Msk                                  (0x01UL << SCU_SFSP7_0_EPUN_Pos)                          /*!< SCU SFSP7_0: EPUN Mask              */
-#define SCU_SFSP7_0_EHS_Pos                                   5                                                         /*!< SCU SFSP7_0: EHS Position           */
-#define SCU_SFSP7_0_EHS_Msk                                   (0x01UL << SCU_SFSP7_0_EHS_Pos)                           /*!< SCU SFSP7_0: EHS Mask               */
-#define SCU_SFSP7_0_EZI_Pos                                   6                                                         /*!< SCU SFSP7_0: EZI Position           */
-#define SCU_SFSP7_0_EZI_Msk                                   (0x01UL << SCU_SFSP7_0_EZI_Pos)                           /*!< SCU SFSP7_0: EZI Mask               */
-#define SCU_SFSP7_0_EHD_Pos                                   8                                                         /*!< SCU SFSP7_0: EHD Position           */
-#define SCU_SFSP7_0_EHD_Msk                                   (0x03UL << SCU_SFSP7_0_EHD_Pos)                           /*!< SCU SFSP7_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP7_1  ------------------------------------------
-#define SCU_SFSP7_1_MODE_Pos                                  0                                                         /*!< SCU SFSP7_1: MODE Position          */
-#define SCU_SFSP7_1_MODE_Msk                                  (0x07UL << SCU_SFSP7_1_MODE_Pos)                          /*!< SCU SFSP7_1: MODE Mask              */
-#define SCU_SFSP7_1_EPD_Pos                                   3                                                         /*!< SCU SFSP7_1: EPD Position           */
-#define SCU_SFSP7_1_EPD_Msk                                   (0x01UL << SCU_SFSP7_1_EPD_Pos)                           /*!< SCU SFSP7_1: EPD Mask               */
-#define SCU_SFSP7_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_1: EPUN Position          */
-#define SCU_SFSP7_1_EPUN_Msk                                  (0x01UL << SCU_SFSP7_1_EPUN_Pos)                          /*!< SCU SFSP7_1: EPUN Mask              */
-#define SCU_SFSP7_1_EHS_Pos                                   5                                                         /*!< SCU SFSP7_1: EHS Position           */
-#define SCU_SFSP7_1_EHS_Msk                                   (0x01UL << SCU_SFSP7_1_EHS_Pos)                           /*!< SCU SFSP7_1: EHS Mask               */
-#define SCU_SFSP7_1_EZI_Pos                                   6                                                         /*!< SCU SFSP7_1: EZI Position           */
-#define SCU_SFSP7_1_EZI_Msk                                   (0x01UL << SCU_SFSP7_1_EZI_Pos)                           /*!< SCU SFSP7_1: EZI Mask               */
-#define SCU_SFSP7_1_EHD_Pos                                   8                                                         /*!< SCU SFSP7_1: EHD Position           */
-#define SCU_SFSP7_1_EHD_Msk                                   (0x03UL << SCU_SFSP7_1_EHD_Pos)                           /*!< SCU SFSP7_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP7_2  ------------------------------------------
-#define SCU_SFSP7_2_MODE_Pos                                  0                                                         /*!< SCU SFSP7_2: MODE Position          */
-#define SCU_SFSP7_2_MODE_Msk                                  (0x07UL << SCU_SFSP7_2_MODE_Pos)                          /*!< SCU SFSP7_2: MODE Mask              */
-#define SCU_SFSP7_2_EPD_Pos                                   3                                                         /*!< SCU SFSP7_2: EPD Position           */
-#define SCU_SFSP7_2_EPD_Msk                                   (0x01UL << SCU_SFSP7_2_EPD_Pos)                           /*!< SCU SFSP7_2: EPD Mask               */
-#define SCU_SFSP7_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_2: EPUN Position          */
-#define SCU_SFSP7_2_EPUN_Msk                                  (0x01UL << SCU_SFSP7_2_EPUN_Pos)                          /*!< SCU SFSP7_2: EPUN Mask              */
-#define SCU_SFSP7_2_EHS_Pos                                   5                                                         /*!< SCU SFSP7_2: EHS Position           */
-#define SCU_SFSP7_2_EHS_Msk                                   (0x01UL << SCU_SFSP7_2_EHS_Pos)                           /*!< SCU SFSP7_2: EHS Mask               */
-#define SCU_SFSP7_2_EZI_Pos                                   6                                                         /*!< SCU SFSP7_2: EZI Position           */
-#define SCU_SFSP7_2_EZI_Msk                                   (0x01UL << SCU_SFSP7_2_EZI_Pos)                           /*!< SCU SFSP7_2: EZI Mask               */
-#define SCU_SFSP7_2_EHD_Pos                                   8                                                         /*!< SCU SFSP7_2: EHD Position           */
-#define SCU_SFSP7_2_EHD_Msk                                   (0x03UL << SCU_SFSP7_2_EHD_Pos)                           /*!< SCU SFSP7_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP7_3  ------------------------------------------
-#define SCU_SFSP7_3_MODE_Pos                                  0                                                         /*!< SCU SFSP7_3: MODE Position          */
-#define SCU_SFSP7_3_MODE_Msk                                  (0x07UL << SCU_SFSP7_3_MODE_Pos)                          /*!< SCU SFSP7_3: MODE Mask              */
-#define SCU_SFSP7_3_EPD_Pos                                   3                                                         /*!< SCU SFSP7_3: EPD Position           */
-#define SCU_SFSP7_3_EPD_Msk                                   (0x01UL << SCU_SFSP7_3_EPD_Pos)                           /*!< SCU SFSP7_3: EPD Mask               */
-#define SCU_SFSP7_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_3: EPUN Position          */
-#define SCU_SFSP7_3_EPUN_Msk                                  (0x01UL << SCU_SFSP7_3_EPUN_Pos)                          /*!< SCU SFSP7_3: EPUN Mask              */
-#define SCU_SFSP7_3_EHS_Pos                                   5                                                         /*!< SCU SFSP7_3: EHS Position           */
-#define SCU_SFSP7_3_EHS_Msk                                   (0x01UL << SCU_SFSP7_3_EHS_Pos)                           /*!< SCU SFSP7_3: EHS Mask               */
-#define SCU_SFSP7_3_EZI_Pos                                   6                                                         /*!< SCU SFSP7_3: EZI Position           */
-#define SCU_SFSP7_3_EZI_Msk                                   (0x01UL << SCU_SFSP7_3_EZI_Pos)                           /*!< SCU SFSP7_3: EZI Mask               */
-#define SCU_SFSP7_3_EHD_Pos                                   8                                                         /*!< SCU SFSP7_3: EHD Position           */
-#define SCU_SFSP7_3_EHD_Msk                                   (0x03UL << SCU_SFSP7_3_EHD_Pos)                           /*!< SCU SFSP7_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP7_4  ------------------------------------------
-#define SCU_SFSP7_4_MODE_Pos                                  0                                                         /*!< SCU SFSP7_4: MODE Position          */
-#define SCU_SFSP7_4_MODE_Msk                                  (0x07UL << SCU_SFSP7_4_MODE_Pos)                          /*!< SCU SFSP7_4: MODE Mask              */
-#define SCU_SFSP7_4_EPD_Pos                                   3                                                         /*!< SCU SFSP7_4: EPD Position           */
-#define SCU_SFSP7_4_EPD_Msk                                   (0x01UL << SCU_SFSP7_4_EPD_Pos)                           /*!< SCU SFSP7_4: EPD Mask               */
-#define SCU_SFSP7_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_4: EPUN Position          */
-#define SCU_SFSP7_4_EPUN_Msk                                  (0x01UL << SCU_SFSP7_4_EPUN_Pos)                          /*!< SCU SFSP7_4: EPUN Mask              */
-#define SCU_SFSP7_4_EHS_Pos                                   5                                                         /*!< SCU SFSP7_4: EHS Position           */
-#define SCU_SFSP7_4_EHS_Msk                                   (0x01UL << SCU_SFSP7_4_EHS_Pos)                           /*!< SCU SFSP7_4: EHS Mask               */
-#define SCU_SFSP7_4_EZI_Pos                                   6                                                         /*!< SCU SFSP7_4: EZI Position           */
-#define SCU_SFSP7_4_EZI_Msk                                   (0x01UL << SCU_SFSP7_4_EZI_Pos)                           /*!< SCU SFSP7_4: EZI Mask               */
-#define SCU_SFSP7_4_EHD_Pos                                   8                                                         /*!< SCU SFSP7_4: EHD Position           */
-#define SCU_SFSP7_4_EHD_Msk                                   (0x03UL << SCU_SFSP7_4_EHD_Pos)                           /*!< SCU SFSP7_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP7_5  ------------------------------------------
-#define SCU_SFSP7_5_MODE_Pos                                  0                                                         /*!< SCU SFSP7_5: MODE Position          */
-#define SCU_SFSP7_5_MODE_Msk                                  (0x07UL << SCU_SFSP7_5_MODE_Pos)                          /*!< SCU SFSP7_5: MODE Mask              */
-#define SCU_SFSP7_5_EPD_Pos                                   3                                                         /*!< SCU SFSP7_5: EPD Position           */
-#define SCU_SFSP7_5_EPD_Msk                                   (0x01UL << SCU_SFSP7_5_EPD_Pos)                           /*!< SCU SFSP7_5: EPD Mask               */
-#define SCU_SFSP7_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_5: EPUN Position          */
-#define SCU_SFSP7_5_EPUN_Msk                                  (0x01UL << SCU_SFSP7_5_EPUN_Pos)                          /*!< SCU SFSP7_5: EPUN Mask              */
-#define SCU_SFSP7_5_EHS_Pos                                   5                                                         /*!< SCU SFSP7_5: EHS Position           */
-#define SCU_SFSP7_5_EHS_Msk                                   (0x01UL << SCU_SFSP7_5_EHS_Pos)                           /*!< SCU SFSP7_5: EHS Mask               */
-#define SCU_SFSP7_5_EZI_Pos                                   6                                                         /*!< SCU SFSP7_5: EZI Position           */
-#define SCU_SFSP7_5_EZI_Msk                                   (0x01UL << SCU_SFSP7_5_EZI_Pos)                           /*!< SCU SFSP7_5: EZI Mask               */
-#define SCU_SFSP7_5_EHD_Pos                                   8                                                         /*!< SCU SFSP7_5: EHD Position           */
-#define SCU_SFSP7_5_EHD_Msk                                   (0x03UL << SCU_SFSP7_5_EHD_Pos)                           /*!< SCU SFSP7_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP7_6  ------------------------------------------
-#define SCU_SFSP7_6_MODE_Pos                                  0                                                         /*!< SCU SFSP7_6: MODE Position          */
-#define SCU_SFSP7_6_MODE_Msk                                  (0x07UL << SCU_SFSP7_6_MODE_Pos)                          /*!< SCU SFSP7_6: MODE Mask              */
-#define SCU_SFSP7_6_EPD_Pos                                   3                                                         /*!< SCU SFSP7_6: EPD Position           */
-#define SCU_SFSP7_6_EPD_Msk                                   (0x01UL << SCU_SFSP7_6_EPD_Pos)                           /*!< SCU SFSP7_6: EPD Mask               */
-#define SCU_SFSP7_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_6: EPUN Position          */
-#define SCU_SFSP7_6_EPUN_Msk                                  (0x01UL << SCU_SFSP7_6_EPUN_Pos)                          /*!< SCU SFSP7_6: EPUN Mask              */
-#define SCU_SFSP7_6_EHS_Pos                                   5                                                         /*!< SCU SFSP7_6: EHS Position           */
-#define SCU_SFSP7_6_EHS_Msk                                   (0x01UL << SCU_SFSP7_6_EHS_Pos)                           /*!< SCU SFSP7_6: EHS Mask               */
-#define SCU_SFSP7_6_EZI_Pos                                   6                                                         /*!< SCU SFSP7_6: EZI Position           */
-#define SCU_SFSP7_6_EZI_Msk                                   (0x01UL << SCU_SFSP7_6_EZI_Pos)                           /*!< SCU SFSP7_6: EZI Mask               */
-#define SCU_SFSP7_6_EHD_Pos                                   8                                                         /*!< SCU SFSP7_6: EHD Position           */
-#define SCU_SFSP7_6_EHD_Msk                                   (0x03UL << SCU_SFSP7_6_EHD_Pos)                           /*!< SCU SFSP7_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP7_7  ------------------------------------------
-#define SCU_SFSP7_7_MODE_Pos                                  0                                                         /*!< SCU SFSP7_7: MODE Position          */
-#define SCU_SFSP7_7_MODE_Msk                                  (0x07UL << SCU_SFSP7_7_MODE_Pos)                          /*!< SCU SFSP7_7: MODE Mask              */
-#define SCU_SFSP7_7_EPD_Pos                                   3                                                         /*!< SCU SFSP7_7: EPD Position           */
-#define SCU_SFSP7_7_EPD_Msk                                   (0x01UL << SCU_SFSP7_7_EPD_Pos)                           /*!< SCU SFSP7_7: EPD Mask               */
-#define SCU_SFSP7_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP7_7: EPUN Position          */
-#define SCU_SFSP7_7_EPUN_Msk                                  (0x01UL << SCU_SFSP7_7_EPUN_Pos)                          /*!< SCU SFSP7_7: EPUN Mask              */
-#define SCU_SFSP7_7_EHS_Pos                                   5                                                         /*!< SCU SFSP7_7: EHS Position           */
-#define SCU_SFSP7_7_EHS_Msk                                   (0x01UL << SCU_SFSP7_7_EHS_Pos)                           /*!< SCU SFSP7_7: EHS Mask               */
-#define SCU_SFSP7_7_EZI_Pos                                   6                                                         /*!< SCU SFSP7_7: EZI Position           */
-#define SCU_SFSP7_7_EZI_Msk                                   (0x01UL << SCU_SFSP7_7_EZI_Pos)                           /*!< SCU SFSP7_7: EZI Mask               */
-#define SCU_SFSP7_7_EHD_Pos                                   8                                                         /*!< SCU SFSP7_7: EHD Position           */
-#define SCU_SFSP7_7_EHD_Msk                                   (0x03UL << SCU_SFSP7_7_EHD_Pos)                           /*!< SCU SFSP7_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP8_0  ------------------------------------------
-#define SCU_SFSP8_0_MODE_Pos                                  0                                                         /*!< SCU SFSP8_0: MODE Position          */
-#define SCU_SFSP8_0_MODE_Msk                                  (0x07UL << SCU_SFSP8_0_MODE_Pos)                          /*!< SCU SFSP8_0: MODE Mask              */
-#define SCU_SFSP8_0_EPD_Pos                                   3                                                         /*!< SCU SFSP8_0: EPD Position           */
-#define SCU_SFSP8_0_EPD_Msk                                   (0x01UL << SCU_SFSP8_0_EPD_Pos)                           /*!< SCU SFSP8_0: EPD Mask               */
-#define SCU_SFSP8_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_0: EPUN Position          */
-#define SCU_SFSP8_0_EPUN_Msk                                  (0x01UL << SCU_SFSP8_0_EPUN_Pos)                          /*!< SCU SFSP8_0: EPUN Mask              */
-#define SCU_SFSP8_0_EHS_Pos                                   5                                                         /*!< SCU SFSP8_0: EHS Position           */
-#define SCU_SFSP8_0_EHS_Msk                                   (0x01UL << SCU_SFSP8_0_EHS_Pos)                           /*!< SCU SFSP8_0: EHS Mask               */
-#define SCU_SFSP8_0_EZI_Pos                                   6                                                         /*!< SCU SFSP8_0: EZI Position           */
-#define SCU_SFSP8_0_EZI_Msk                                   (0x01UL << SCU_SFSP8_0_EZI_Pos)                           /*!< SCU SFSP8_0: EZI Mask               */
-#define SCU_SFSP8_0_EHD_Pos                                   8                                                         /*!< SCU SFSP8_0: EHD Position           */
-#define SCU_SFSP8_0_EHD_Msk                                   (0x03UL << SCU_SFSP8_0_EHD_Pos)                           /*!< SCU SFSP8_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP8_1  ------------------------------------------
-#define SCU_SFSP8_1_MODE_Pos                                  0                                                         /*!< SCU SFSP8_1: MODE Position          */
-#define SCU_SFSP8_1_MODE_Msk                                  (0x07UL << SCU_SFSP8_1_MODE_Pos)                          /*!< SCU SFSP8_1: MODE Mask              */
-#define SCU_SFSP8_1_EPD_Pos                                   3                                                         /*!< SCU SFSP8_1: EPD Position           */
-#define SCU_SFSP8_1_EPD_Msk                                   (0x01UL << SCU_SFSP8_1_EPD_Pos)                           /*!< SCU SFSP8_1: EPD Mask               */
-#define SCU_SFSP8_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_1: EPUN Position          */
-#define SCU_SFSP8_1_EPUN_Msk                                  (0x01UL << SCU_SFSP8_1_EPUN_Pos)                          /*!< SCU SFSP8_1: EPUN Mask              */
-#define SCU_SFSP8_1_EHS_Pos                                   5                                                         /*!< SCU SFSP8_1: EHS Position           */
-#define SCU_SFSP8_1_EHS_Msk                                   (0x01UL << SCU_SFSP8_1_EHS_Pos)                           /*!< SCU SFSP8_1: EHS Mask               */
-#define SCU_SFSP8_1_EZI_Pos                                   6                                                         /*!< SCU SFSP8_1: EZI Position           */
-#define SCU_SFSP8_1_EZI_Msk                                   (0x01UL << SCU_SFSP8_1_EZI_Pos)                           /*!< SCU SFSP8_1: EZI Mask               */
-#define SCU_SFSP8_1_EHD_Pos                                   8                                                         /*!< SCU SFSP8_1: EHD Position           */
-#define SCU_SFSP8_1_EHD_Msk                                   (0x03UL << SCU_SFSP8_1_EHD_Pos)                           /*!< SCU SFSP8_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP8_2  ------------------------------------------
-#define SCU_SFSP8_2_MODE_Pos                                  0                                                         /*!< SCU SFSP8_2: MODE Position          */
-#define SCU_SFSP8_2_MODE_Msk                                  (0x07UL << SCU_SFSP8_2_MODE_Pos)                          /*!< SCU SFSP8_2: MODE Mask              */
-#define SCU_SFSP8_2_EPD_Pos                                   3                                                         /*!< SCU SFSP8_2: EPD Position           */
-#define SCU_SFSP8_2_EPD_Msk                                   (0x01UL << SCU_SFSP8_2_EPD_Pos)                           /*!< SCU SFSP8_2: EPD Mask               */
-#define SCU_SFSP8_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_2: EPUN Position          */
-#define SCU_SFSP8_2_EPUN_Msk                                  (0x01UL << SCU_SFSP8_2_EPUN_Pos)                          /*!< SCU SFSP8_2: EPUN Mask              */
-#define SCU_SFSP8_2_EHS_Pos                                   5                                                         /*!< SCU SFSP8_2: EHS Position           */
-#define SCU_SFSP8_2_EHS_Msk                                   (0x01UL << SCU_SFSP8_2_EHS_Pos)                           /*!< SCU SFSP8_2: EHS Mask               */
-#define SCU_SFSP8_2_EZI_Pos                                   6                                                         /*!< SCU SFSP8_2: EZI Position           */
-#define SCU_SFSP8_2_EZI_Msk                                   (0x01UL << SCU_SFSP8_2_EZI_Pos)                           /*!< SCU SFSP8_2: EZI Mask               */
-#define SCU_SFSP8_2_EHD_Pos                                   8                                                         /*!< SCU SFSP8_2: EHD Position           */
-#define SCU_SFSP8_2_EHD_Msk                                   (0x03UL << SCU_SFSP8_2_EHD_Pos)                           /*!< SCU SFSP8_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP8_3  ------------------------------------------
-#define SCU_SFSP8_3_MODE_Pos                                  0                                                         /*!< SCU SFSP8_3: MODE Position          */
-#define SCU_SFSP8_3_MODE_Msk                                  (0x07UL << SCU_SFSP8_3_MODE_Pos)                          /*!< SCU SFSP8_3: MODE Mask              */
-#define SCU_SFSP8_3_EPD_Pos                                   3                                                         /*!< SCU SFSP8_3: EPD Position           */
-#define SCU_SFSP8_3_EPD_Msk                                   (0x01UL << SCU_SFSP8_3_EPD_Pos)                           /*!< SCU SFSP8_3: EPD Mask               */
-#define SCU_SFSP8_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_3: EPUN Position          */
-#define SCU_SFSP8_3_EPUN_Msk                                  (0x01UL << SCU_SFSP8_3_EPUN_Pos)                          /*!< SCU SFSP8_3: EPUN Mask              */
-#define SCU_SFSP8_3_EHS_Pos                                   5                                                         /*!< SCU SFSP8_3: EHS Position           */
-#define SCU_SFSP8_3_EHS_Msk                                   (0x01UL << SCU_SFSP8_3_EHS_Pos)                           /*!< SCU SFSP8_3: EHS Mask               */
-#define SCU_SFSP8_3_EZI_Pos                                   6                                                         /*!< SCU SFSP8_3: EZI Position           */
-#define SCU_SFSP8_3_EZI_Msk                                   (0x01UL << SCU_SFSP8_3_EZI_Pos)                           /*!< SCU SFSP8_3: EZI Mask               */
-#define SCU_SFSP8_3_EHD_Pos                                   8                                                         /*!< SCU SFSP8_3: EHD Position           */
-#define SCU_SFSP8_3_EHD_Msk                                   (0x03UL << SCU_SFSP8_3_EHD_Pos)                           /*!< SCU SFSP8_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP8_4  ------------------------------------------
-#define SCU_SFSP8_4_MODE_Pos                                  0                                                         /*!< SCU SFSP8_4: MODE Position          */
-#define SCU_SFSP8_4_MODE_Msk                                  (0x07UL << SCU_SFSP8_4_MODE_Pos)                          /*!< SCU SFSP8_4: MODE Mask              */
-#define SCU_SFSP8_4_EPD_Pos                                   3                                                         /*!< SCU SFSP8_4: EPD Position           */
-#define SCU_SFSP8_4_EPD_Msk                                   (0x01UL << SCU_SFSP8_4_EPD_Pos)                           /*!< SCU SFSP8_4: EPD Mask               */
-#define SCU_SFSP8_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_4: EPUN Position          */
-#define SCU_SFSP8_4_EPUN_Msk                                  (0x01UL << SCU_SFSP8_4_EPUN_Pos)                          /*!< SCU SFSP8_4: EPUN Mask              */
-#define SCU_SFSP8_4_EHS_Pos                                   5                                                         /*!< SCU SFSP8_4: EHS Position           */
-#define SCU_SFSP8_4_EHS_Msk                                   (0x01UL << SCU_SFSP8_4_EHS_Pos)                           /*!< SCU SFSP8_4: EHS Mask               */
-#define SCU_SFSP8_4_EZI_Pos                                   6                                                         /*!< SCU SFSP8_4: EZI Position           */
-#define SCU_SFSP8_4_EZI_Msk                                   (0x01UL << SCU_SFSP8_4_EZI_Pos)                           /*!< SCU SFSP8_4: EZI Mask               */
-#define SCU_SFSP8_4_EHD_Pos                                   8                                                         /*!< SCU SFSP8_4: EHD Position           */
-#define SCU_SFSP8_4_EHD_Msk                                   (0x03UL << SCU_SFSP8_4_EHD_Pos)                           /*!< SCU SFSP8_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP8_5  ------------------------------------------
-#define SCU_SFSP8_5_MODE_Pos                                  0                                                         /*!< SCU SFSP8_5: MODE Position          */
-#define SCU_SFSP8_5_MODE_Msk                                  (0x07UL << SCU_SFSP8_5_MODE_Pos)                          /*!< SCU SFSP8_5: MODE Mask              */
-#define SCU_SFSP8_5_EPD_Pos                                   3                                                         /*!< SCU SFSP8_5: EPD Position           */
-#define SCU_SFSP8_5_EPD_Msk                                   (0x01UL << SCU_SFSP8_5_EPD_Pos)                           /*!< SCU SFSP8_5: EPD Mask               */
-#define SCU_SFSP8_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_5: EPUN Position          */
-#define SCU_SFSP8_5_EPUN_Msk                                  (0x01UL << SCU_SFSP8_5_EPUN_Pos)                          /*!< SCU SFSP8_5: EPUN Mask              */
-#define SCU_SFSP8_5_EHS_Pos                                   5                                                         /*!< SCU SFSP8_5: EHS Position           */
-#define SCU_SFSP8_5_EHS_Msk                                   (0x01UL << SCU_SFSP8_5_EHS_Pos)                           /*!< SCU SFSP8_5: EHS Mask               */
-#define SCU_SFSP8_5_EZI_Pos                                   6                                                         /*!< SCU SFSP8_5: EZI Position           */
-#define SCU_SFSP8_5_EZI_Msk                                   (0x01UL << SCU_SFSP8_5_EZI_Pos)                           /*!< SCU SFSP8_5: EZI Mask               */
-#define SCU_SFSP8_5_EHD_Pos                                   8                                                         /*!< SCU SFSP8_5: EHD Position           */
-#define SCU_SFSP8_5_EHD_Msk                                   (0x03UL << SCU_SFSP8_5_EHD_Pos)                           /*!< SCU SFSP8_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP8_6  ------------------------------------------
-#define SCU_SFSP8_6_MODE_Pos                                  0                                                         /*!< SCU SFSP8_6: MODE Position          */
-#define SCU_SFSP8_6_MODE_Msk                                  (0x07UL << SCU_SFSP8_6_MODE_Pos)                          /*!< SCU SFSP8_6: MODE Mask              */
-#define SCU_SFSP8_6_EPD_Pos                                   3                                                         /*!< SCU SFSP8_6: EPD Position           */
-#define SCU_SFSP8_6_EPD_Msk                                   (0x01UL << SCU_SFSP8_6_EPD_Pos)                           /*!< SCU SFSP8_6: EPD Mask               */
-#define SCU_SFSP8_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_6: EPUN Position          */
-#define SCU_SFSP8_6_EPUN_Msk                                  (0x01UL << SCU_SFSP8_6_EPUN_Pos)                          /*!< SCU SFSP8_6: EPUN Mask              */
-#define SCU_SFSP8_6_EHS_Pos                                   5                                                         /*!< SCU SFSP8_6: EHS Position           */
-#define SCU_SFSP8_6_EHS_Msk                                   (0x01UL << SCU_SFSP8_6_EHS_Pos)                           /*!< SCU SFSP8_6: EHS Mask               */
-#define SCU_SFSP8_6_EZI_Pos                                   6                                                         /*!< SCU SFSP8_6: EZI Position           */
-#define SCU_SFSP8_6_EZI_Msk                                   (0x01UL << SCU_SFSP8_6_EZI_Pos)                           /*!< SCU SFSP8_6: EZI Mask               */
-#define SCU_SFSP8_6_EHD_Pos                                   8                                                         /*!< SCU SFSP8_6: EHD Position           */
-#define SCU_SFSP8_6_EHD_Msk                                   (0x03UL << SCU_SFSP8_6_EHD_Pos)                           /*!< SCU SFSP8_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP8_7  ------------------------------------------
-#define SCU_SFSP8_7_MODE_Pos                                  0                                                         /*!< SCU SFSP8_7: MODE Position          */
-#define SCU_SFSP8_7_MODE_Msk                                  (0x07UL << SCU_SFSP8_7_MODE_Pos)                          /*!< SCU SFSP8_7: MODE Mask              */
-#define SCU_SFSP8_7_EPD_Pos                                   3                                                         /*!< SCU SFSP8_7: EPD Position           */
-#define SCU_SFSP8_7_EPD_Msk                                   (0x01UL << SCU_SFSP8_7_EPD_Pos)                           /*!< SCU SFSP8_7: EPD Mask               */
-#define SCU_SFSP8_7_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_7: EPUN Position          */
-#define SCU_SFSP8_7_EPUN_Msk                                  (0x01UL << SCU_SFSP8_7_EPUN_Pos)                          /*!< SCU SFSP8_7: EPUN Mask              */
-#define SCU_SFSP8_7_EHS_Pos                                   5                                                         /*!< SCU SFSP8_7: EHS Position           */
-#define SCU_SFSP8_7_EHS_Msk                                   (0x01UL << SCU_SFSP8_7_EHS_Pos)                           /*!< SCU SFSP8_7: EHS Mask               */
-#define SCU_SFSP8_7_EZI_Pos                                   6                                                         /*!< SCU SFSP8_7: EZI Position           */
-#define SCU_SFSP8_7_EZI_Msk                                   (0x01UL << SCU_SFSP8_7_EZI_Pos)                           /*!< SCU SFSP8_7: EZI Mask               */
-#define SCU_SFSP8_7_EHD_Pos                                   8                                                         /*!< SCU SFSP8_7: EHD Position           */
-#define SCU_SFSP8_7_EHD_Msk                                   (0x03UL << SCU_SFSP8_7_EHD_Pos)                           /*!< SCU SFSP8_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP8_8  ------------------------------------------
-#define SCU_SFSP8_8_MODE_Pos                                  0                                                         /*!< SCU SFSP8_8: MODE Position          */
-#define SCU_SFSP8_8_MODE_Msk                                  (0x07UL << SCU_SFSP8_8_MODE_Pos)                          /*!< SCU SFSP8_8: MODE Mask              */
-#define SCU_SFSP8_8_EPD_Pos                                   3                                                         /*!< SCU SFSP8_8: EPD Position           */
-#define SCU_SFSP8_8_EPD_Msk                                   (0x01UL << SCU_SFSP8_8_EPD_Pos)                           /*!< SCU SFSP8_8: EPD Mask               */
-#define SCU_SFSP8_8_EPUN_Pos                                  4                                                         /*!< SCU SFSP8_8: EPUN Position          */
-#define SCU_SFSP8_8_EPUN_Msk                                  (0x01UL << SCU_SFSP8_8_EPUN_Pos)                          /*!< SCU SFSP8_8: EPUN Mask              */
-#define SCU_SFSP8_8_EHS_Pos                                   5                                                         /*!< SCU SFSP8_8: EHS Position           */
-#define SCU_SFSP8_8_EHS_Msk                                   (0x01UL << SCU_SFSP8_8_EHS_Pos)                           /*!< SCU SFSP8_8: EHS Mask               */
-#define SCU_SFSP8_8_EZI_Pos                                   6                                                         /*!< SCU SFSP8_8: EZI Position           */
-#define SCU_SFSP8_8_EZI_Msk                                   (0x01UL << SCU_SFSP8_8_EZI_Pos)                           /*!< SCU SFSP8_8: EZI Mask               */
-#define SCU_SFSP8_8_EHD_Pos                                   8                                                         /*!< SCU SFSP8_8: EHD Position           */
-#define SCU_SFSP8_8_EHD_Msk                                   (0x03UL << SCU_SFSP8_8_EHD_Pos)                           /*!< SCU SFSP8_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP9_0  ------------------------------------------
-#define SCU_SFSP9_0_MODE_Pos                                  0                                                         /*!< SCU SFSP9_0: MODE Position          */
-#define SCU_SFSP9_0_MODE_Msk                                  (0x07UL << SCU_SFSP9_0_MODE_Pos)                          /*!< SCU SFSP9_0: MODE Mask              */
-#define SCU_SFSP9_0_EPD_Pos                                   3                                                         /*!< SCU SFSP9_0: EPD Position           */
-#define SCU_SFSP9_0_EPD_Msk                                   (0x01UL << SCU_SFSP9_0_EPD_Pos)                           /*!< SCU SFSP9_0: EPD Mask               */
-#define SCU_SFSP9_0_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_0: EPUN Position          */
-#define SCU_SFSP9_0_EPUN_Msk                                  (0x01UL << SCU_SFSP9_0_EPUN_Pos)                          /*!< SCU SFSP9_0: EPUN Mask              */
-#define SCU_SFSP9_0_EHS_Pos                                   5                                                         /*!< SCU SFSP9_0: EHS Position           */
-#define SCU_SFSP9_0_EHS_Msk                                   (0x01UL << SCU_SFSP9_0_EHS_Pos)                           /*!< SCU SFSP9_0: EHS Mask               */
-#define SCU_SFSP9_0_EZI_Pos                                   6                                                         /*!< SCU SFSP9_0: EZI Position           */
-#define SCU_SFSP9_0_EZI_Msk                                   (0x01UL << SCU_SFSP9_0_EZI_Pos)                           /*!< SCU SFSP9_0: EZI Mask               */
-#define SCU_SFSP9_0_EHD_Pos                                   8                                                         /*!< SCU SFSP9_0: EHD Position           */
-#define SCU_SFSP9_0_EHD_Msk                                   (0x03UL << SCU_SFSP9_0_EHD_Pos)                           /*!< SCU SFSP9_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP9_1  ------------------------------------------
-#define SCU_SFSP9_1_MODE_Pos                                  0                                                         /*!< SCU SFSP9_1: MODE Position          */
-#define SCU_SFSP9_1_MODE_Msk                                  (0x07UL << SCU_SFSP9_1_MODE_Pos)                          /*!< SCU SFSP9_1: MODE Mask              */
-#define SCU_SFSP9_1_EPD_Pos                                   3                                                         /*!< SCU SFSP9_1: EPD Position           */
-#define SCU_SFSP9_1_EPD_Msk                                   (0x01UL << SCU_SFSP9_1_EPD_Pos)                           /*!< SCU SFSP9_1: EPD Mask               */
-#define SCU_SFSP9_1_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_1: EPUN Position          */
-#define SCU_SFSP9_1_EPUN_Msk                                  (0x01UL << SCU_SFSP9_1_EPUN_Pos)                          /*!< SCU SFSP9_1: EPUN Mask              */
-#define SCU_SFSP9_1_EHS_Pos                                   5                                                         /*!< SCU SFSP9_1: EHS Position           */
-#define SCU_SFSP9_1_EHS_Msk                                   (0x01UL << SCU_SFSP9_1_EHS_Pos)                           /*!< SCU SFSP9_1: EHS Mask               */
-#define SCU_SFSP9_1_EZI_Pos                                   6                                                         /*!< SCU SFSP9_1: EZI Position           */
-#define SCU_SFSP9_1_EZI_Msk                                   (0x01UL << SCU_SFSP9_1_EZI_Pos)                           /*!< SCU SFSP9_1: EZI Mask               */
-#define SCU_SFSP9_1_EHD_Pos                                   8                                                         /*!< SCU SFSP9_1: EHD Position           */
-#define SCU_SFSP9_1_EHD_Msk                                   (0x03UL << SCU_SFSP9_1_EHD_Pos)                           /*!< SCU SFSP9_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP9_2  ------------------------------------------
-#define SCU_SFSP9_2_MODE_Pos                                  0                                                         /*!< SCU SFSP9_2: MODE Position          */
-#define SCU_SFSP9_2_MODE_Msk                                  (0x07UL << SCU_SFSP9_2_MODE_Pos)                          /*!< SCU SFSP9_2: MODE Mask              */
-#define SCU_SFSP9_2_EPD_Pos                                   3                                                         /*!< SCU SFSP9_2: EPD Position           */
-#define SCU_SFSP9_2_EPD_Msk                                   (0x01UL << SCU_SFSP9_2_EPD_Pos)                           /*!< SCU SFSP9_2: EPD Mask               */
-#define SCU_SFSP9_2_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_2: EPUN Position          */
-#define SCU_SFSP9_2_EPUN_Msk                                  (0x01UL << SCU_SFSP9_2_EPUN_Pos)                          /*!< SCU SFSP9_2: EPUN Mask              */
-#define SCU_SFSP9_2_EHS_Pos                                   5                                                         /*!< SCU SFSP9_2: EHS Position           */
-#define SCU_SFSP9_2_EHS_Msk                                   (0x01UL << SCU_SFSP9_2_EHS_Pos)                           /*!< SCU SFSP9_2: EHS Mask               */
-#define SCU_SFSP9_2_EZI_Pos                                   6                                                         /*!< SCU SFSP9_2: EZI Position           */
-#define SCU_SFSP9_2_EZI_Msk                                   (0x01UL << SCU_SFSP9_2_EZI_Pos)                           /*!< SCU SFSP9_2: EZI Mask               */
-#define SCU_SFSP9_2_EHD_Pos                                   8                                                         /*!< SCU SFSP9_2: EHD Position           */
-#define SCU_SFSP9_2_EHD_Msk                                   (0x03UL << SCU_SFSP9_2_EHD_Pos)                           /*!< SCU SFSP9_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP9_3  ------------------------------------------
-#define SCU_SFSP9_3_MODE_Pos                                  0                                                         /*!< SCU SFSP9_3: MODE Position          */
-#define SCU_SFSP9_3_MODE_Msk                                  (0x07UL << SCU_SFSP9_3_MODE_Pos)                          /*!< SCU SFSP9_3: MODE Mask              */
-#define SCU_SFSP9_3_EPD_Pos                                   3                                                         /*!< SCU SFSP9_3: EPD Position           */
-#define SCU_SFSP9_3_EPD_Msk                                   (0x01UL << SCU_SFSP9_3_EPD_Pos)                           /*!< SCU SFSP9_3: EPD Mask               */
-#define SCU_SFSP9_3_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_3: EPUN Position          */
-#define SCU_SFSP9_3_EPUN_Msk                                  (0x01UL << SCU_SFSP9_3_EPUN_Pos)                          /*!< SCU SFSP9_3: EPUN Mask              */
-#define SCU_SFSP9_3_EHS_Pos                                   5                                                         /*!< SCU SFSP9_3: EHS Position           */
-#define SCU_SFSP9_3_EHS_Msk                                   (0x01UL << SCU_SFSP9_3_EHS_Pos)                           /*!< SCU SFSP9_3: EHS Mask               */
-#define SCU_SFSP9_3_EZI_Pos                                   6                                                         /*!< SCU SFSP9_3: EZI Position           */
-#define SCU_SFSP9_3_EZI_Msk                                   (0x01UL << SCU_SFSP9_3_EZI_Pos)                           /*!< SCU SFSP9_3: EZI Mask               */
-#define SCU_SFSP9_3_EHD_Pos                                   8                                                         /*!< SCU SFSP9_3: EHD Position           */
-#define SCU_SFSP9_3_EHD_Msk                                   (0x03UL << SCU_SFSP9_3_EHD_Pos)                           /*!< SCU SFSP9_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP9_4  ------------------------------------------
-#define SCU_SFSP9_4_MODE_Pos                                  0                                                         /*!< SCU SFSP9_4: MODE Position          */
-#define SCU_SFSP9_4_MODE_Msk                                  (0x07UL << SCU_SFSP9_4_MODE_Pos)                          /*!< SCU SFSP9_4: MODE Mask              */
-#define SCU_SFSP9_4_EPD_Pos                                   3                                                         /*!< SCU SFSP9_4: EPD Position           */
-#define SCU_SFSP9_4_EPD_Msk                                   (0x01UL << SCU_SFSP9_4_EPD_Pos)                           /*!< SCU SFSP9_4: EPD Mask               */
-#define SCU_SFSP9_4_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_4: EPUN Position          */
-#define SCU_SFSP9_4_EPUN_Msk                                  (0x01UL << SCU_SFSP9_4_EPUN_Pos)                          /*!< SCU SFSP9_4: EPUN Mask              */
-#define SCU_SFSP9_4_EHS_Pos                                   5                                                         /*!< SCU SFSP9_4: EHS Position           */
-#define SCU_SFSP9_4_EHS_Msk                                   (0x01UL << SCU_SFSP9_4_EHS_Pos)                           /*!< SCU SFSP9_4: EHS Mask               */
-#define SCU_SFSP9_4_EZI_Pos                                   6                                                         /*!< SCU SFSP9_4: EZI Position           */
-#define SCU_SFSP9_4_EZI_Msk                                   (0x01UL << SCU_SFSP9_4_EZI_Pos)                           /*!< SCU SFSP9_4: EZI Mask               */
-#define SCU_SFSP9_4_EHD_Pos                                   8                                                         /*!< SCU SFSP9_4: EHD Position           */
-#define SCU_SFSP9_4_EHD_Msk                                   (0x03UL << SCU_SFSP9_4_EHD_Pos)                           /*!< SCU SFSP9_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP9_5  ------------------------------------------
-#define SCU_SFSP9_5_MODE_Pos                                  0                                                         /*!< SCU SFSP9_5: MODE Position          */
-#define SCU_SFSP9_5_MODE_Msk                                  (0x07UL << SCU_SFSP9_5_MODE_Pos)                          /*!< SCU SFSP9_5: MODE Mask              */
-#define SCU_SFSP9_5_EPD_Pos                                   3                                                         /*!< SCU SFSP9_5: EPD Position           */
-#define SCU_SFSP9_5_EPD_Msk                                   (0x01UL << SCU_SFSP9_5_EPD_Pos)                           /*!< SCU SFSP9_5: EPD Mask               */
-#define SCU_SFSP9_5_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_5: EPUN Position          */
-#define SCU_SFSP9_5_EPUN_Msk                                  (0x01UL << SCU_SFSP9_5_EPUN_Pos)                          /*!< SCU SFSP9_5: EPUN Mask              */
-#define SCU_SFSP9_5_EHS_Pos                                   5                                                         /*!< SCU SFSP9_5: EHS Position           */
-#define SCU_SFSP9_5_EHS_Msk                                   (0x01UL << SCU_SFSP9_5_EHS_Pos)                           /*!< SCU SFSP9_5: EHS Mask               */
-#define SCU_SFSP9_5_EZI_Pos                                   6                                                         /*!< SCU SFSP9_5: EZI Position           */
-#define SCU_SFSP9_5_EZI_Msk                                   (0x01UL << SCU_SFSP9_5_EZI_Pos)                           /*!< SCU SFSP9_5: EZI Mask               */
-#define SCU_SFSP9_5_EHD_Pos                                   8                                                         /*!< SCU SFSP9_5: EHD Position           */
-#define SCU_SFSP9_5_EHD_Msk                                   (0x03UL << SCU_SFSP9_5_EHD_Pos)                           /*!< SCU SFSP9_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSP9_6  ------------------------------------------
-#define SCU_SFSP9_6_MODE_Pos                                  0                                                         /*!< SCU SFSP9_6: MODE Position          */
-#define SCU_SFSP9_6_MODE_Msk                                  (0x07UL << SCU_SFSP9_6_MODE_Pos)                          /*!< SCU SFSP9_6: MODE Mask              */
-#define SCU_SFSP9_6_EPD_Pos                                   3                                                         /*!< SCU SFSP9_6: EPD Position           */
-#define SCU_SFSP9_6_EPD_Msk                                   (0x01UL << SCU_SFSP9_6_EPD_Pos)                           /*!< SCU SFSP9_6: EPD Mask               */
-#define SCU_SFSP9_6_EPUN_Pos                                  4                                                         /*!< SCU SFSP9_6: EPUN Position          */
-#define SCU_SFSP9_6_EPUN_Msk                                  (0x01UL << SCU_SFSP9_6_EPUN_Pos)                          /*!< SCU SFSP9_6: EPUN Mask              */
-#define SCU_SFSP9_6_EHS_Pos                                   5                                                         /*!< SCU SFSP9_6: EHS Position           */
-#define SCU_SFSP9_6_EHS_Msk                                   (0x01UL << SCU_SFSP9_6_EHS_Pos)                           /*!< SCU SFSP9_6: EHS Mask               */
-#define SCU_SFSP9_6_EZI_Pos                                   6                                                         /*!< SCU SFSP9_6: EZI Position           */
-#define SCU_SFSP9_6_EZI_Msk                                   (0x01UL << SCU_SFSP9_6_EZI_Pos)                           /*!< SCU SFSP9_6: EZI Mask               */
-#define SCU_SFSP9_6_EHD_Pos                                   8                                                         /*!< SCU SFSP9_6: EHD Position           */
-#define SCU_SFSP9_6_EHD_Msk                                   (0x03UL << SCU_SFSP9_6_EHD_Pos)                           /*!< SCU SFSP9_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPA_0  ------------------------------------------
-#define SCU_SFSPA_0_MODE_Pos                                  0                                                         /*!< SCU SFSPA_0: MODE Position          */
-#define SCU_SFSPA_0_MODE_Msk                                  (0x07UL << SCU_SFSPA_0_MODE_Pos)                          /*!< SCU SFSPA_0: MODE Mask              */
-#define SCU_SFSPA_0_EPD_Pos                                   3                                                         /*!< SCU SFSPA_0: EPD Position           */
-#define SCU_SFSPA_0_EPD_Msk                                   (0x01UL << SCU_SFSPA_0_EPD_Pos)                           /*!< SCU SFSPA_0: EPD Mask               */
-#define SCU_SFSPA_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_0: EPUN Position          */
-#define SCU_SFSPA_0_EPUN_Msk                                  (0x01UL << SCU_SFSPA_0_EPUN_Pos)                          /*!< SCU SFSPA_0: EPUN Mask              */
-#define SCU_SFSPA_0_EHS_Pos                                   5                                                         /*!< SCU SFSPA_0: EHS Position           */
-#define SCU_SFSPA_0_EHS_Msk                                   (0x01UL << SCU_SFSPA_0_EHS_Pos)                           /*!< SCU SFSPA_0: EHS Mask               */
-#define SCU_SFSPA_0_EZI_Pos                                   6                                                         /*!< SCU SFSPA_0: EZI Position           */
-#define SCU_SFSPA_0_EZI_Msk                                   (0x01UL << SCU_SFSPA_0_EZI_Pos)                           /*!< SCU SFSPA_0: EZI Mask               */
-#define SCU_SFSPA_0_EHD_Pos                                   8                                                         /*!< SCU SFSPA_0: EHD Position           */
-#define SCU_SFSPA_0_EHD_Msk                                   (0x03UL << SCU_SFSPA_0_EHD_Pos)                           /*!< SCU SFSPA_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPA_1  ------------------------------------------
-#define SCU_SFSPA_1_MODE_Pos                                  0                                                         /*!< SCU SFSPA_1: MODE Position          */
-#define SCU_SFSPA_1_MODE_Msk                                  (0x07UL << SCU_SFSPA_1_MODE_Pos)                          /*!< SCU SFSPA_1: MODE Mask              */
-#define SCU_SFSPA_1_EPD_Pos                                   3                                                         /*!< SCU SFSPA_1: EPD Position           */
-#define SCU_SFSPA_1_EPD_Msk                                   (0x01UL << SCU_SFSPA_1_EPD_Pos)                           /*!< SCU SFSPA_1: EPD Mask               */
-#define SCU_SFSPA_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_1: EPUN Position          */
-#define SCU_SFSPA_1_EPUN_Msk                                  (0x01UL << SCU_SFSPA_1_EPUN_Pos)                          /*!< SCU SFSPA_1: EPUN Mask              */
-#define SCU_SFSPA_1_EHS_Pos                                   5                                                         /*!< SCU SFSPA_1: EHS Position           */
-#define SCU_SFSPA_1_EHS_Msk                                   (0x01UL << SCU_SFSPA_1_EHS_Pos)                           /*!< SCU SFSPA_1: EHS Mask               */
-#define SCU_SFSPA_1_EZI_Pos                                   6                                                         /*!< SCU SFSPA_1: EZI Position           */
-#define SCU_SFSPA_1_EZI_Msk                                   (0x01UL << SCU_SFSPA_1_EZI_Pos)                           /*!< SCU SFSPA_1: EZI Mask               */
-#define SCU_SFSPA_1_EHD_Pos                                   8                                                         /*!< SCU SFSPA_1: EHD Position           */
-#define SCU_SFSPA_1_EHD_Msk                                   (0x03UL << SCU_SFSPA_1_EHD_Pos)                           /*!< SCU SFSPA_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPA_2  ------------------------------------------
-#define SCU_SFSPA_2_MODE_Pos                                  0                                                         /*!< SCU SFSPA_2: MODE Position          */
-#define SCU_SFSPA_2_MODE_Msk                                  (0x07UL << SCU_SFSPA_2_MODE_Pos)                          /*!< SCU SFSPA_2: MODE Mask              */
-#define SCU_SFSPA_2_EPD_Pos                                   3                                                         /*!< SCU SFSPA_2: EPD Position           */
-#define SCU_SFSPA_2_EPD_Msk                                   (0x01UL << SCU_SFSPA_2_EPD_Pos)                           /*!< SCU SFSPA_2: EPD Mask               */
-#define SCU_SFSPA_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_2: EPUN Position          */
-#define SCU_SFSPA_2_EPUN_Msk                                  (0x01UL << SCU_SFSPA_2_EPUN_Pos)                          /*!< SCU SFSPA_2: EPUN Mask              */
-#define SCU_SFSPA_2_EHS_Pos                                   5                                                         /*!< SCU SFSPA_2: EHS Position           */
-#define SCU_SFSPA_2_EHS_Msk                                   (0x01UL << SCU_SFSPA_2_EHS_Pos)                           /*!< SCU SFSPA_2: EHS Mask               */
-#define SCU_SFSPA_2_EZI_Pos                                   6                                                         /*!< SCU SFSPA_2: EZI Position           */
-#define SCU_SFSPA_2_EZI_Msk                                   (0x01UL << SCU_SFSPA_2_EZI_Pos)                           /*!< SCU SFSPA_2: EZI Mask               */
-#define SCU_SFSPA_2_EHD_Pos                                   8                                                         /*!< SCU SFSPA_2: EHD Position           */
-#define SCU_SFSPA_2_EHD_Msk                                   (0x03UL << SCU_SFSPA_2_EHD_Pos)                           /*!< SCU SFSPA_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPA_3  ------------------------------------------
-#define SCU_SFSPA_3_MODE_Pos                                  0                                                         /*!< SCU SFSPA_3: MODE Position          */
-#define SCU_SFSPA_3_MODE_Msk                                  (0x07UL << SCU_SFSPA_3_MODE_Pos)                          /*!< SCU SFSPA_3: MODE Mask              */
-#define SCU_SFSPA_3_EPD_Pos                                   3                                                         /*!< SCU SFSPA_3: EPD Position           */
-#define SCU_SFSPA_3_EPD_Msk                                   (0x01UL << SCU_SFSPA_3_EPD_Pos)                           /*!< SCU SFSPA_3: EPD Mask               */
-#define SCU_SFSPA_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_3: EPUN Position          */
-#define SCU_SFSPA_3_EPUN_Msk                                  (0x01UL << SCU_SFSPA_3_EPUN_Pos)                          /*!< SCU SFSPA_3: EPUN Mask              */
-#define SCU_SFSPA_3_EHS_Pos                                   5                                                         /*!< SCU SFSPA_3: EHS Position           */
-#define SCU_SFSPA_3_EHS_Msk                                   (0x01UL << SCU_SFSPA_3_EHS_Pos)                           /*!< SCU SFSPA_3: EHS Mask               */
-#define SCU_SFSPA_3_EZI_Pos                                   6                                                         /*!< SCU SFSPA_3: EZI Position           */
-#define SCU_SFSPA_3_EZI_Msk                                   (0x01UL << SCU_SFSPA_3_EZI_Pos)                           /*!< SCU SFSPA_3: EZI Mask               */
-#define SCU_SFSPA_3_EHD_Pos                                   8                                                         /*!< SCU SFSPA_3: EHD Position           */
-#define SCU_SFSPA_3_EHD_Msk                                   (0x03UL << SCU_SFSPA_3_EHD_Pos)                           /*!< SCU SFSPA_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPA_4  ------------------------------------------
-#define SCU_SFSPA_4_MODE_Pos                                  0                                                         /*!< SCU SFSPA_4: MODE Position          */
-#define SCU_SFSPA_4_MODE_Msk                                  (0x07UL << SCU_SFSPA_4_MODE_Pos)                          /*!< SCU SFSPA_4: MODE Mask              */
-#define SCU_SFSPA_4_EPD_Pos                                   3                                                         /*!< SCU SFSPA_4: EPD Position           */
-#define SCU_SFSPA_4_EPD_Msk                                   (0x01UL << SCU_SFSPA_4_EPD_Pos)                           /*!< SCU SFSPA_4: EPD Mask               */
-#define SCU_SFSPA_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPA_4: EPUN Position          */
-#define SCU_SFSPA_4_EPUN_Msk                                  (0x01UL << SCU_SFSPA_4_EPUN_Pos)                          /*!< SCU SFSPA_4: EPUN Mask              */
-#define SCU_SFSPA_4_EHS_Pos                                   5                                                         /*!< SCU SFSPA_4: EHS Position           */
-#define SCU_SFSPA_4_EHS_Msk                                   (0x01UL << SCU_SFSPA_4_EHS_Pos)                           /*!< SCU SFSPA_4: EHS Mask               */
-#define SCU_SFSPA_4_EZI_Pos                                   6                                                         /*!< SCU SFSPA_4: EZI Position           */
-#define SCU_SFSPA_4_EZI_Msk                                   (0x01UL << SCU_SFSPA_4_EZI_Pos)                           /*!< SCU SFSPA_4: EZI Mask               */
-#define SCU_SFSPA_4_EHD_Pos                                   8                                                         /*!< SCU SFSPA_4: EHD Position           */
-#define SCU_SFSPA_4_EHD_Msk                                   (0x03UL << SCU_SFSPA_4_EHD_Pos)                           /*!< SCU SFSPA_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPB_0  ------------------------------------------
-#define SCU_SFSPB_0_MODE_Pos                                  0                                                         /*!< SCU SFSPB_0: MODE Position          */
-#define SCU_SFSPB_0_MODE_Msk                                  (0x07UL << SCU_SFSPB_0_MODE_Pos)                          /*!< SCU SFSPB_0: MODE Mask              */
-#define SCU_SFSPB_0_EPD_Pos                                   3                                                         /*!< SCU SFSPB_0: EPD Position           */
-#define SCU_SFSPB_0_EPD_Msk                                   (0x01UL << SCU_SFSPB_0_EPD_Pos)                           /*!< SCU SFSPB_0: EPD Mask               */
-#define SCU_SFSPB_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_0: EPUN Position          */
-#define SCU_SFSPB_0_EPUN_Msk                                  (0x01UL << SCU_SFSPB_0_EPUN_Pos)                          /*!< SCU SFSPB_0: EPUN Mask              */
-#define SCU_SFSPB_0_EHS_Pos                                   5                                                         /*!< SCU SFSPB_0: EHS Position           */
-#define SCU_SFSPB_0_EHS_Msk                                   (0x01UL << SCU_SFSPB_0_EHS_Pos)                           /*!< SCU SFSPB_0: EHS Mask               */
-#define SCU_SFSPB_0_EZI_Pos                                   6                                                         /*!< SCU SFSPB_0: EZI Position           */
-#define SCU_SFSPB_0_EZI_Msk                                   (0x01UL << SCU_SFSPB_0_EZI_Pos)                           /*!< SCU SFSPB_0: EZI Mask               */
-#define SCU_SFSPB_0_EHD_Pos                                   8                                                         /*!< SCU SFSPB_0: EHD Position           */
-#define SCU_SFSPB_0_EHD_Msk                                   (0x03UL << SCU_SFSPB_0_EHD_Pos)                           /*!< SCU SFSPB_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPB_1  ------------------------------------------
-#define SCU_SFSPB_1_MODE_Pos                                  0                                                         /*!< SCU SFSPB_1: MODE Position          */
-#define SCU_SFSPB_1_MODE_Msk                                  (0x07UL << SCU_SFSPB_1_MODE_Pos)                          /*!< SCU SFSPB_1: MODE Mask              */
-#define SCU_SFSPB_1_EPD_Pos                                   3                                                         /*!< SCU SFSPB_1: EPD Position           */
-#define SCU_SFSPB_1_EPD_Msk                                   (0x01UL << SCU_SFSPB_1_EPD_Pos)                           /*!< SCU SFSPB_1: EPD Mask               */
-#define SCU_SFSPB_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_1: EPUN Position          */
-#define SCU_SFSPB_1_EPUN_Msk                                  (0x01UL << SCU_SFSPB_1_EPUN_Pos)                          /*!< SCU SFSPB_1: EPUN Mask              */
-#define SCU_SFSPB_1_EHS_Pos                                   5                                                         /*!< SCU SFSPB_1: EHS Position           */
-#define SCU_SFSPB_1_EHS_Msk                                   (0x01UL << SCU_SFSPB_1_EHS_Pos)                           /*!< SCU SFSPB_1: EHS Mask               */
-#define SCU_SFSPB_1_EZI_Pos                                   6                                                         /*!< SCU SFSPB_1: EZI Position           */
-#define SCU_SFSPB_1_EZI_Msk                                   (0x01UL << SCU_SFSPB_1_EZI_Pos)                           /*!< SCU SFSPB_1: EZI Mask               */
-#define SCU_SFSPB_1_EHD_Pos                                   8                                                         /*!< SCU SFSPB_1: EHD Position           */
-#define SCU_SFSPB_1_EHD_Msk                                   (0x03UL << SCU_SFSPB_1_EHD_Pos)                           /*!< SCU SFSPB_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPB_2  ------------------------------------------
-#define SCU_SFSPB_2_MODE_Pos                                  0                                                         /*!< SCU SFSPB_2: MODE Position          */
-#define SCU_SFSPB_2_MODE_Msk                                  (0x07UL << SCU_SFSPB_2_MODE_Pos)                          /*!< SCU SFSPB_2: MODE Mask              */
-#define SCU_SFSPB_2_EPD_Pos                                   3                                                         /*!< SCU SFSPB_2: EPD Position           */
-#define SCU_SFSPB_2_EPD_Msk                                   (0x01UL << SCU_SFSPB_2_EPD_Pos)                           /*!< SCU SFSPB_2: EPD Mask               */
-#define SCU_SFSPB_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_2: EPUN Position          */
-#define SCU_SFSPB_2_EPUN_Msk                                  (0x01UL << SCU_SFSPB_2_EPUN_Pos)                          /*!< SCU SFSPB_2: EPUN Mask              */
-#define SCU_SFSPB_2_EHS_Pos                                   5                                                         /*!< SCU SFSPB_2: EHS Position           */
-#define SCU_SFSPB_2_EHS_Msk                                   (0x01UL << SCU_SFSPB_2_EHS_Pos)                           /*!< SCU SFSPB_2: EHS Mask               */
-#define SCU_SFSPB_2_EZI_Pos                                   6                                                         /*!< SCU SFSPB_2: EZI Position           */
-#define SCU_SFSPB_2_EZI_Msk                                   (0x01UL << SCU_SFSPB_2_EZI_Pos)                           /*!< SCU SFSPB_2: EZI Mask               */
-#define SCU_SFSPB_2_EHD_Pos                                   8                                                         /*!< SCU SFSPB_2: EHD Position           */
-#define SCU_SFSPB_2_EHD_Msk                                   (0x03UL << SCU_SFSPB_2_EHD_Pos)                           /*!< SCU SFSPB_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPB_3  ------------------------------------------
-#define SCU_SFSPB_3_MODE_Pos                                  0                                                         /*!< SCU SFSPB_3: MODE Position          */
-#define SCU_SFSPB_3_MODE_Msk                                  (0x07UL << SCU_SFSPB_3_MODE_Pos)                          /*!< SCU SFSPB_3: MODE Mask              */
-#define SCU_SFSPB_3_EPD_Pos                                   3                                                         /*!< SCU SFSPB_3: EPD Position           */
-#define SCU_SFSPB_3_EPD_Msk                                   (0x01UL << SCU_SFSPB_3_EPD_Pos)                           /*!< SCU SFSPB_3: EPD Mask               */
-#define SCU_SFSPB_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_3: EPUN Position          */
-#define SCU_SFSPB_3_EPUN_Msk                                  (0x01UL << SCU_SFSPB_3_EPUN_Pos)                          /*!< SCU SFSPB_3: EPUN Mask              */
-#define SCU_SFSPB_3_EHS_Pos                                   5                                                         /*!< SCU SFSPB_3: EHS Position           */
-#define SCU_SFSPB_3_EHS_Msk                                   (0x01UL << SCU_SFSPB_3_EHS_Pos)                           /*!< SCU SFSPB_3: EHS Mask               */
-#define SCU_SFSPB_3_EZI_Pos                                   6                                                         /*!< SCU SFSPB_3: EZI Position           */
-#define SCU_SFSPB_3_EZI_Msk                                   (0x01UL << SCU_SFSPB_3_EZI_Pos)                           /*!< SCU SFSPB_3: EZI Mask               */
-#define SCU_SFSPB_3_EHD_Pos                                   8                                                         /*!< SCU SFSPB_3: EHD Position           */
-#define SCU_SFSPB_3_EHD_Msk                                   (0x03UL << SCU_SFSPB_3_EHD_Pos)                           /*!< SCU SFSPB_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPB_4  ------------------------------------------
-#define SCU_SFSPB_4_MODE_Pos                                  0                                                         /*!< SCU SFSPB_4: MODE Position          */
-#define SCU_SFSPB_4_MODE_Msk                                  (0x07UL << SCU_SFSPB_4_MODE_Pos)                          /*!< SCU SFSPB_4: MODE Mask              */
-#define SCU_SFSPB_4_EPD_Pos                                   3                                                         /*!< SCU SFSPB_4: EPD Position           */
-#define SCU_SFSPB_4_EPD_Msk                                   (0x01UL << SCU_SFSPB_4_EPD_Pos)                           /*!< SCU SFSPB_4: EPD Mask               */
-#define SCU_SFSPB_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_4: EPUN Position          */
-#define SCU_SFSPB_4_EPUN_Msk                                  (0x01UL << SCU_SFSPB_4_EPUN_Pos)                          /*!< SCU SFSPB_4: EPUN Mask              */
-#define SCU_SFSPB_4_EHS_Pos                                   5                                                         /*!< SCU SFSPB_4: EHS Position           */
-#define SCU_SFSPB_4_EHS_Msk                                   (0x01UL << SCU_SFSPB_4_EHS_Pos)                           /*!< SCU SFSPB_4: EHS Mask               */
-#define SCU_SFSPB_4_EZI_Pos                                   6                                                         /*!< SCU SFSPB_4: EZI Position           */
-#define SCU_SFSPB_4_EZI_Msk                                   (0x01UL << SCU_SFSPB_4_EZI_Pos)                           /*!< SCU SFSPB_4: EZI Mask               */
-#define SCU_SFSPB_4_EHD_Pos                                   8                                                         /*!< SCU SFSPB_4: EHD Position           */
-#define SCU_SFSPB_4_EHD_Msk                                   (0x03UL << SCU_SFSPB_4_EHD_Pos)                           /*!< SCU SFSPB_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPB_5  ------------------------------------------
-#define SCU_SFSPB_5_MODE_Pos                                  0                                                         /*!< SCU SFSPB_5: MODE Position          */
-#define SCU_SFSPB_5_MODE_Msk                                  (0x07UL << SCU_SFSPB_5_MODE_Pos)                          /*!< SCU SFSPB_5: MODE Mask              */
-#define SCU_SFSPB_5_EPD_Pos                                   3                                                         /*!< SCU SFSPB_5: EPD Position           */
-#define SCU_SFSPB_5_EPD_Msk                                   (0x01UL << SCU_SFSPB_5_EPD_Pos)                           /*!< SCU SFSPB_5: EPD Mask               */
-#define SCU_SFSPB_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_5: EPUN Position          */
-#define SCU_SFSPB_5_EPUN_Msk                                  (0x01UL << SCU_SFSPB_5_EPUN_Pos)                          /*!< SCU SFSPB_5: EPUN Mask              */
-#define SCU_SFSPB_5_EHS_Pos                                   5                                                         /*!< SCU SFSPB_5: EHS Position           */
-#define SCU_SFSPB_5_EHS_Msk                                   (0x01UL << SCU_SFSPB_5_EHS_Pos)                           /*!< SCU SFSPB_5: EHS Mask               */
-#define SCU_SFSPB_5_EZI_Pos                                   6                                                         /*!< SCU SFSPB_5: EZI Position           */
-#define SCU_SFSPB_5_EZI_Msk                                   (0x01UL << SCU_SFSPB_5_EZI_Pos)                           /*!< SCU SFSPB_5: EZI Mask               */
-#define SCU_SFSPB_5_EHD_Pos                                   8                                                         /*!< SCU SFSPB_5: EHD Position           */
-#define SCU_SFSPB_5_EHD_Msk                                   (0x03UL << SCU_SFSPB_5_EHD_Pos)                           /*!< SCU SFSPB_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPB_6  ------------------------------------------
-#define SCU_SFSPB_6_MODE_Pos                                  0                                                         /*!< SCU SFSPB_6: MODE Position          */
-#define SCU_SFSPB_6_MODE_Msk                                  (0x07UL << SCU_SFSPB_6_MODE_Pos)                          /*!< SCU SFSPB_6: MODE Mask              */
-#define SCU_SFSPB_6_EPD_Pos                                   3                                                         /*!< SCU SFSPB_6: EPD Position           */
-#define SCU_SFSPB_6_EPD_Msk                                   (0x01UL << SCU_SFSPB_6_EPD_Pos)                           /*!< SCU SFSPB_6: EPD Mask               */
-#define SCU_SFSPB_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPB_6: EPUN Position          */
-#define SCU_SFSPB_6_EPUN_Msk                                  (0x01UL << SCU_SFSPB_6_EPUN_Pos)                          /*!< SCU SFSPB_6: EPUN Mask              */
-#define SCU_SFSPB_6_EHS_Pos                                   5                                                         /*!< SCU SFSPB_6: EHS Position           */
-#define SCU_SFSPB_6_EHS_Msk                                   (0x01UL << SCU_SFSPB_6_EHS_Pos)                           /*!< SCU SFSPB_6: EHS Mask               */
-#define SCU_SFSPB_6_EZI_Pos                                   6                                                         /*!< SCU SFSPB_6: EZI Position           */
-#define SCU_SFSPB_6_EZI_Msk                                   (0x01UL << SCU_SFSPB_6_EZI_Pos)                           /*!< SCU SFSPB_6: EZI Mask               */
-#define SCU_SFSPB_6_EHD_Pos                                   8                                                         /*!< SCU SFSPB_6: EHD Position           */
-#define SCU_SFSPB_6_EHD_Msk                                   (0x03UL << SCU_SFSPB_6_EHD_Pos)                           /*!< SCU SFSPB_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_0  ------------------------------------------
-#define SCU_SFSPC_0_MODE_Pos                                  0                                                         /*!< SCU SFSPC_0: MODE Position          */
-#define SCU_SFSPC_0_MODE_Msk                                  (0x07UL << SCU_SFSPC_0_MODE_Pos)                          /*!< SCU SFSPC_0: MODE Mask              */
-#define SCU_SFSPC_0_EPD_Pos                                   3                                                         /*!< SCU SFSPC_0: EPD Position           */
-#define SCU_SFSPC_0_EPD_Msk                                   (0x01UL << SCU_SFSPC_0_EPD_Pos)                           /*!< SCU SFSPC_0: EPD Mask               */
-#define SCU_SFSPC_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_0: EPUN Position          */
-#define SCU_SFSPC_0_EPUN_Msk                                  (0x01UL << SCU_SFSPC_0_EPUN_Pos)                          /*!< SCU SFSPC_0: EPUN Mask              */
-#define SCU_SFSPC_0_EHS_Pos                                   5                                                         /*!< SCU SFSPC_0: EHS Position           */
-#define SCU_SFSPC_0_EHS_Msk                                   (0x01UL << SCU_SFSPC_0_EHS_Pos)                           /*!< SCU SFSPC_0: EHS Mask               */
-#define SCU_SFSPC_0_EZI_Pos                                   6                                                         /*!< SCU SFSPC_0: EZI Position           */
-#define SCU_SFSPC_0_EZI_Msk                                   (0x01UL << SCU_SFSPC_0_EZI_Pos)                           /*!< SCU SFSPC_0: EZI Mask               */
-#define SCU_SFSPC_0_EHD_Pos                                   8                                                         /*!< SCU SFSPC_0: EHD Position           */
-#define SCU_SFSPC_0_EHD_Msk                                   (0x03UL << SCU_SFSPC_0_EHD_Pos)                           /*!< SCU SFSPC_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_1  ------------------------------------------
-#define SCU_SFSPC_1_MODE_Pos                                  0                                                         /*!< SCU SFSPC_1: MODE Position          */
-#define SCU_SFSPC_1_MODE_Msk                                  (0x07UL << SCU_SFSPC_1_MODE_Pos)                          /*!< SCU SFSPC_1: MODE Mask              */
-#define SCU_SFSPC_1_EPD_Pos                                   3                                                         /*!< SCU SFSPC_1: EPD Position           */
-#define SCU_SFSPC_1_EPD_Msk                                   (0x01UL << SCU_SFSPC_1_EPD_Pos)                           /*!< SCU SFSPC_1: EPD Mask               */
-#define SCU_SFSPC_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_1: EPUN Position          */
-#define SCU_SFSPC_1_EPUN_Msk                                  (0x01UL << SCU_SFSPC_1_EPUN_Pos)                          /*!< SCU SFSPC_1: EPUN Mask              */
-#define SCU_SFSPC_1_EHS_Pos                                   5                                                         /*!< SCU SFSPC_1: EHS Position           */
-#define SCU_SFSPC_1_EHS_Msk                                   (0x01UL << SCU_SFSPC_1_EHS_Pos)                           /*!< SCU SFSPC_1: EHS Mask               */
-#define SCU_SFSPC_1_EZI_Pos                                   6                                                         /*!< SCU SFSPC_1: EZI Position           */
-#define SCU_SFSPC_1_EZI_Msk                                   (0x01UL << SCU_SFSPC_1_EZI_Pos)                           /*!< SCU SFSPC_1: EZI Mask               */
-#define SCU_SFSPC_1_EHD_Pos                                   8                                                         /*!< SCU SFSPC_1: EHD Position           */
-#define SCU_SFSPC_1_EHD_Msk                                   (0x03UL << SCU_SFSPC_1_EHD_Pos)                           /*!< SCU SFSPC_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_2  ------------------------------------------
-#define SCU_SFSPC_2_MODE_Pos                                  0                                                         /*!< SCU SFSPC_2: MODE Position          */
-#define SCU_SFSPC_2_MODE_Msk                                  (0x07UL << SCU_SFSPC_2_MODE_Pos)                          /*!< SCU SFSPC_2: MODE Mask              */
-#define SCU_SFSPC_2_EPD_Pos                                   3                                                         /*!< SCU SFSPC_2: EPD Position           */
-#define SCU_SFSPC_2_EPD_Msk                                   (0x01UL << SCU_SFSPC_2_EPD_Pos)                           /*!< SCU SFSPC_2: EPD Mask               */
-#define SCU_SFSPC_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_2: EPUN Position          */
-#define SCU_SFSPC_2_EPUN_Msk                                  (0x01UL << SCU_SFSPC_2_EPUN_Pos)                          /*!< SCU SFSPC_2: EPUN Mask              */
-#define SCU_SFSPC_2_EHS_Pos                                   5                                                         /*!< SCU SFSPC_2: EHS Position           */
-#define SCU_SFSPC_2_EHS_Msk                                   (0x01UL << SCU_SFSPC_2_EHS_Pos)                           /*!< SCU SFSPC_2: EHS Mask               */
-#define SCU_SFSPC_2_EZI_Pos                                   6                                                         /*!< SCU SFSPC_2: EZI Position           */
-#define SCU_SFSPC_2_EZI_Msk                                   (0x01UL << SCU_SFSPC_2_EZI_Pos)                           /*!< SCU SFSPC_2: EZI Mask               */
-#define SCU_SFSPC_2_EHD_Pos                                   8                                                         /*!< SCU SFSPC_2: EHD Position           */
-#define SCU_SFSPC_2_EHD_Msk                                   (0x03UL << SCU_SFSPC_2_EHD_Pos)                           /*!< SCU SFSPC_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_3  ------------------------------------------
-#define SCU_SFSPC_3_MODE_Pos                                  0                                                         /*!< SCU SFSPC_3: MODE Position          */
-#define SCU_SFSPC_3_MODE_Msk                                  (0x07UL << SCU_SFSPC_3_MODE_Pos)                          /*!< SCU SFSPC_3: MODE Mask              */
-#define SCU_SFSPC_3_EPD_Pos                                   3                                                         /*!< SCU SFSPC_3: EPD Position           */
-#define SCU_SFSPC_3_EPD_Msk                                   (0x01UL << SCU_SFSPC_3_EPD_Pos)                           /*!< SCU SFSPC_3: EPD Mask               */
-#define SCU_SFSPC_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_3: EPUN Position          */
-#define SCU_SFSPC_3_EPUN_Msk                                  (0x01UL << SCU_SFSPC_3_EPUN_Pos)                          /*!< SCU SFSPC_3: EPUN Mask              */
-#define SCU_SFSPC_3_EHS_Pos                                   5                                                         /*!< SCU SFSPC_3: EHS Position           */
-#define SCU_SFSPC_3_EHS_Msk                                   (0x01UL << SCU_SFSPC_3_EHS_Pos)                           /*!< SCU SFSPC_3: EHS Mask               */
-#define SCU_SFSPC_3_EZI_Pos                                   6                                                         /*!< SCU SFSPC_3: EZI Position           */
-#define SCU_SFSPC_3_EZI_Msk                                   (0x01UL << SCU_SFSPC_3_EZI_Pos)                           /*!< SCU SFSPC_3: EZI Mask               */
-#define SCU_SFSPC_3_EHD_Pos                                   8                                                         /*!< SCU SFSPC_3: EHD Position           */
-#define SCU_SFSPC_3_EHD_Msk                                   (0x03UL << SCU_SFSPC_3_EHD_Pos)                           /*!< SCU SFSPC_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_4  ------------------------------------------
-#define SCU_SFSPC_4_MODE_Pos                                  0                                                         /*!< SCU SFSPC_4: MODE Position          */
-#define SCU_SFSPC_4_MODE_Msk                                  (0x07UL << SCU_SFSPC_4_MODE_Pos)                          /*!< SCU SFSPC_4: MODE Mask              */
-#define SCU_SFSPC_4_EPD_Pos                                   3                                                         /*!< SCU SFSPC_4: EPD Position           */
-#define SCU_SFSPC_4_EPD_Msk                                   (0x01UL << SCU_SFSPC_4_EPD_Pos)                           /*!< SCU SFSPC_4: EPD Mask               */
-#define SCU_SFSPC_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_4: EPUN Position          */
-#define SCU_SFSPC_4_EPUN_Msk                                  (0x01UL << SCU_SFSPC_4_EPUN_Pos)                          /*!< SCU SFSPC_4: EPUN Mask              */
-#define SCU_SFSPC_4_EHS_Pos                                   5                                                         /*!< SCU SFSPC_4: EHS Position           */
-#define SCU_SFSPC_4_EHS_Msk                                   (0x01UL << SCU_SFSPC_4_EHS_Pos)                           /*!< SCU SFSPC_4: EHS Mask               */
-#define SCU_SFSPC_4_EZI_Pos                                   6                                                         /*!< SCU SFSPC_4: EZI Position           */
-#define SCU_SFSPC_4_EZI_Msk                                   (0x01UL << SCU_SFSPC_4_EZI_Pos)                           /*!< SCU SFSPC_4: EZI Mask               */
-#define SCU_SFSPC_4_EHD_Pos                                   8                                                         /*!< SCU SFSPC_4: EHD Position           */
-#define SCU_SFSPC_4_EHD_Msk                                   (0x03UL << SCU_SFSPC_4_EHD_Pos)                           /*!< SCU SFSPC_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_5  ------------------------------------------
-#define SCU_SFSPC_5_MODE_Pos                                  0                                                         /*!< SCU SFSPC_5: MODE Position          */
-#define SCU_SFSPC_5_MODE_Msk                                  (0x07UL << SCU_SFSPC_5_MODE_Pos)                          /*!< SCU SFSPC_5: MODE Mask              */
-#define SCU_SFSPC_5_EPD_Pos                                   3                                                         /*!< SCU SFSPC_5: EPD Position           */
-#define SCU_SFSPC_5_EPD_Msk                                   (0x01UL << SCU_SFSPC_5_EPD_Pos)                           /*!< SCU SFSPC_5: EPD Mask               */
-#define SCU_SFSPC_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_5: EPUN Position          */
-#define SCU_SFSPC_5_EPUN_Msk                                  (0x01UL << SCU_SFSPC_5_EPUN_Pos)                          /*!< SCU SFSPC_5: EPUN Mask              */
-#define SCU_SFSPC_5_EHS_Pos                                   5                                                         /*!< SCU SFSPC_5: EHS Position           */
-#define SCU_SFSPC_5_EHS_Msk                                   (0x01UL << SCU_SFSPC_5_EHS_Pos)                           /*!< SCU SFSPC_5: EHS Mask               */
-#define SCU_SFSPC_5_EZI_Pos                                   6                                                         /*!< SCU SFSPC_5: EZI Position           */
-#define SCU_SFSPC_5_EZI_Msk                                   (0x01UL << SCU_SFSPC_5_EZI_Pos)                           /*!< SCU SFSPC_5: EZI Mask               */
-#define SCU_SFSPC_5_EHD_Pos                                   8                                                         /*!< SCU SFSPC_5: EHD Position           */
-#define SCU_SFSPC_5_EHD_Msk                                   (0x03UL << SCU_SFSPC_5_EHD_Pos)                           /*!< SCU SFSPC_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_6  ------------------------------------------
-#define SCU_SFSPC_6_MODE_Pos                                  0                                                         /*!< SCU SFSPC_6: MODE Position          */
-#define SCU_SFSPC_6_MODE_Msk                                  (0x07UL << SCU_SFSPC_6_MODE_Pos)                          /*!< SCU SFSPC_6: MODE Mask              */
-#define SCU_SFSPC_6_EPD_Pos                                   3                                                         /*!< SCU SFSPC_6: EPD Position           */
-#define SCU_SFSPC_6_EPD_Msk                                   (0x01UL << SCU_SFSPC_6_EPD_Pos)                           /*!< SCU SFSPC_6: EPD Mask               */
-#define SCU_SFSPC_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_6: EPUN Position          */
-#define SCU_SFSPC_6_EPUN_Msk                                  (0x01UL << SCU_SFSPC_6_EPUN_Pos)                          /*!< SCU SFSPC_6: EPUN Mask              */
-#define SCU_SFSPC_6_EHS_Pos                                   5                                                         /*!< SCU SFSPC_6: EHS Position           */
-#define SCU_SFSPC_6_EHS_Msk                                   (0x01UL << SCU_SFSPC_6_EHS_Pos)                           /*!< SCU SFSPC_6: EHS Mask               */
-#define SCU_SFSPC_6_EZI_Pos                                   6                                                         /*!< SCU SFSPC_6: EZI Position           */
-#define SCU_SFSPC_6_EZI_Msk                                   (0x01UL << SCU_SFSPC_6_EZI_Pos)                           /*!< SCU SFSPC_6: EZI Mask               */
-#define SCU_SFSPC_6_EHD_Pos                                   8                                                         /*!< SCU SFSPC_6: EHD Position           */
-#define SCU_SFSPC_6_EHD_Msk                                   (0x03UL << SCU_SFSPC_6_EHD_Pos)                           /*!< SCU SFSPC_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_7  ------------------------------------------
-#define SCU_SFSPC_7_MODE_Pos                                  0                                                         /*!< SCU SFSPC_7: MODE Position          */
-#define SCU_SFSPC_7_MODE_Msk                                  (0x07UL << SCU_SFSPC_7_MODE_Pos)                          /*!< SCU SFSPC_7: MODE Mask              */
-#define SCU_SFSPC_7_EPD_Pos                                   3                                                         /*!< SCU SFSPC_7: EPD Position           */
-#define SCU_SFSPC_7_EPD_Msk                                   (0x01UL << SCU_SFSPC_7_EPD_Pos)                           /*!< SCU SFSPC_7: EPD Mask               */
-#define SCU_SFSPC_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_7: EPUN Position          */
-#define SCU_SFSPC_7_EPUN_Msk                                  (0x01UL << SCU_SFSPC_7_EPUN_Pos)                          /*!< SCU SFSPC_7: EPUN Mask              */
-#define SCU_SFSPC_7_EHS_Pos                                   5                                                         /*!< SCU SFSPC_7: EHS Position           */
-#define SCU_SFSPC_7_EHS_Msk                                   (0x01UL << SCU_SFSPC_7_EHS_Pos)                           /*!< SCU SFSPC_7: EHS Mask               */
-#define SCU_SFSPC_7_EZI_Pos                                   6                                                         /*!< SCU SFSPC_7: EZI Position           */
-#define SCU_SFSPC_7_EZI_Msk                                   (0x01UL << SCU_SFSPC_7_EZI_Pos)                           /*!< SCU SFSPC_7: EZI Mask               */
-#define SCU_SFSPC_7_EHD_Pos                                   8                                                         /*!< SCU SFSPC_7: EHD Position           */
-#define SCU_SFSPC_7_EHD_Msk                                   (0x03UL << SCU_SFSPC_7_EHD_Pos)                           /*!< SCU SFSPC_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_8  ------------------------------------------
-#define SCU_SFSPC_8_MODE_Pos                                  0                                                         /*!< SCU SFSPC_8: MODE Position          */
-#define SCU_SFSPC_8_MODE_Msk                                  (0x07UL << SCU_SFSPC_8_MODE_Pos)                          /*!< SCU SFSPC_8: MODE Mask              */
-#define SCU_SFSPC_8_EPD_Pos                                   3                                                         /*!< SCU SFSPC_8: EPD Position           */
-#define SCU_SFSPC_8_EPD_Msk                                   (0x01UL << SCU_SFSPC_8_EPD_Pos)                           /*!< SCU SFSPC_8: EPD Mask               */
-#define SCU_SFSPC_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_8: EPUN Position          */
-#define SCU_SFSPC_8_EPUN_Msk                                  (0x01UL << SCU_SFSPC_8_EPUN_Pos)                          /*!< SCU SFSPC_8: EPUN Mask              */
-#define SCU_SFSPC_8_EHS_Pos                                   5                                                         /*!< SCU SFSPC_8: EHS Position           */
-#define SCU_SFSPC_8_EHS_Msk                                   (0x01UL << SCU_SFSPC_8_EHS_Pos)                           /*!< SCU SFSPC_8: EHS Mask               */
-#define SCU_SFSPC_8_EZI_Pos                                   6                                                         /*!< SCU SFSPC_8: EZI Position           */
-#define SCU_SFSPC_8_EZI_Msk                                   (0x01UL << SCU_SFSPC_8_EZI_Pos)                           /*!< SCU SFSPC_8: EZI Mask               */
-#define SCU_SFSPC_8_EHD_Pos                                   8                                                         /*!< SCU SFSPC_8: EHD Position           */
-#define SCU_SFSPC_8_EHD_Msk                                   (0x03UL << SCU_SFSPC_8_EHD_Pos)                           /*!< SCU SFSPC_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPC_9  ------------------------------------------
-#define SCU_SFSPC_9_MODE_Pos                                  0                                                         /*!< SCU SFSPC_9: MODE Position          */
-#define SCU_SFSPC_9_MODE_Msk                                  (0x07UL << SCU_SFSPC_9_MODE_Pos)                          /*!< SCU SFSPC_9: MODE Mask              */
-#define SCU_SFSPC_9_EPD_Pos                                   3                                                         /*!< SCU SFSPC_9: EPD Position           */
-#define SCU_SFSPC_9_EPD_Msk                                   (0x01UL << SCU_SFSPC_9_EPD_Pos)                           /*!< SCU SFSPC_9: EPD Mask               */
-#define SCU_SFSPC_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPC_9: EPUN Position          */
-#define SCU_SFSPC_9_EPUN_Msk                                  (0x01UL << SCU_SFSPC_9_EPUN_Pos)                          /*!< SCU SFSPC_9: EPUN Mask              */
-#define SCU_SFSPC_9_EHS_Pos                                   5                                                         /*!< SCU SFSPC_9: EHS Position           */
-#define SCU_SFSPC_9_EHS_Msk                                   (0x01UL << SCU_SFSPC_9_EHS_Pos)                           /*!< SCU SFSPC_9: EHS Mask               */
-#define SCU_SFSPC_9_EZI_Pos                                   6                                                         /*!< SCU SFSPC_9: EZI Position           */
-#define SCU_SFSPC_9_EZI_Msk                                   (0x01UL << SCU_SFSPC_9_EZI_Pos)                           /*!< SCU SFSPC_9: EZI Mask               */
-#define SCU_SFSPC_9_EHD_Pos                                   8                                                         /*!< SCU SFSPC_9: EHD Position           */
-#define SCU_SFSPC_9_EHD_Msk                                   (0x03UL << SCU_SFSPC_9_EHD_Pos)                           /*!< SCU SFSPC_9: EHD Mask               */
-
-// --------------------------------------  SCU_SFSPC_10  ------------------------------------------
-#define SCU_SFSPC_10_MODE_Pos                                 0                                                         /*!< SCU SFSPC_10: MODE Position         */
-#define SCU_SFSPC_10_MODE_Msk                                 (0x07UL << SCU_SFSPC_10_MODE_Pos)                         /*!< SCU SFSPC_10: MODE Mask             */
-#define SCU_SFSPC_10_EPD_Pos                                  3                                                         /*!< SCU SFSPC_10: EPD Position          */
-#define SCU_SFSPC_10_EPD_Msk                                  (0x01UL << SCU_SFSPC_10_EPD_Pos)                          /*!< SCU SFSPC_10: EPD Mask              */
-#define SCU_SFSPC_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_10: EPUN Position         */
-#define SCU_SFSPC_10_EPUN_Msk                                 (0x01UL << SCU_SFSPC_10_EPUN_Pos)                         /*!< SCU SFSPC_10: EPUN Mask             */
-#define SCU_SFSPC_10_EHS_Pos                                  5                                                         /*!< SCU SFSPC_10: EHS Position          */
-#define SCU_SFSPC_10_EHS_Msk                                  (0x01UL << SCU_SFSPC_10_EHS_Pos)                          /*!< SCU SFSPC_10: EHS Mask              */
-#define SCU_SFSPC_10_EZI_Pos                                  6                                                         /*!< SCU SFSPC_10: EZI Position          */
-#define SCU_SFSPC_10_EZI_Msk                                  (0x01UL << SCU_SFSPC_10_EZI_Pos)                          /*!< SCU SFSPC_10: EZI Mask              */
-#define SCU_SFSPC_10_EHD_Pos                                  8                                                         /*!< SCU SFSPC_10: EHD Position          */
-#define SCU_SFSPC_10_EHD_Msk                                  (0x03UL << SCU_SFSPC_10_EHD_Pos)                          /*!< SCU SFSPC_10: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPC_11  ------------------------------------------
-#define SCU_SFSPC_11_MODE_Pos                                 0                                                         /*!< SCU SFSPC_11: MODE Position         */
-#define SCU_SFSPC_11_MODE_Msk                                 (0x07UL << SCU_SFSPC_11_MODE_Pos)                         /*!< SCU SFSPC_11: MODE Mask             */
-#define SCU_SFSPC_11_EPD_Pos                                  3                                                         /*!< SCU SFSPC_11: EPD Position          */
-#define SCU_SFSPC_11_EPD_Msk                                  (0x01UL << SCU_SFSPC_11_EPD_Pos)                          /*!< SCU SFSPC_11: EPD Mask              */
-#define SCU_SFSPC_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_11: EPUN Position         */
-#define SCU_SFSPC_11_EPUN_Msk                                 (0x01UL << SCU_SFSPC_11_EPUN_Pos)                         /*!< SCU SFSPC_11: EPUN Mask             */
-#define SCU_SFSPC_11_EHS_Pos                                  5                                                         /*!< SCU SFSPC_11: EHS Position          */
-#define SCU_SFSPC_11_EHS_Msk                                  (0x01UL << SCU_SFSPC_11_EHS_Pos)                          /*!< SCU SFSPC_11: EHS Mask              */
-#define SCU_SFSPC_11_EZI_Pos                                  6                                                         /*!< SCU SFSPC_11: EZI Position          */
-#define SCU_SFSPC_11_EZI_Msk                                  (0x01UL << SCU_SFSPC_11_EZI_Pos)                          /*!< SCU SFSPC_11: EZI Mask              */
-#define SCU_SFSPC_11_EHD_Pos                                  8                                                         /*!< SCU SFSPC_11: EHD Position          */
-#define SCU_SFSPC_11_EHD_Msk                                  (0x03UL << SCU_SFSPC_11_EHD_Pos)                          /*!< SCU SFSPC_11: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPC_12  ------------------------------------------
-#define SCU_SFSPC_12_MODE_Pos                                 0                                                         /*!< SCU SFSPC_12: MODE Position         */
-#define SCU_SFSPC_12_MODE_Msk                                 (0x07UL << SCU_SFSPC_12_MODE_Pos)                         /*!< SCU SFSPC_12: MODE Mask             */
-#define SCU_SFSPC_12_EPD_Pos                                  3                                                         /*!< SCU SFSPC_12: EPD Position          */
-#define SCU_SFSPC_12_EPD_Msk                                  (0x01UL << SCU_SFSPC_12_EPD_Pos)                          /*!< SCU SFSPC_12: EPD Mask              */
-#define SCU_SFSPC_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_12: EPUN Position         */
-#define SCU_SFSPC_12_EPUN_Msk                                 (0x01UL << SCU_SFSPC_12_EPUN_Pos)                         /*!< SCU SFSPC_12: EPUN Mask             */
-#define SCU_SFSPC_12_EHS_Pos                                  5                                                         /*!< SCU SFSPC_12: EHS Position          */
-#define SCU_SFSPC_12_EHS_Msk                                  (0x01UL << SCU_SFSPC_12_EHS_Pos)                          /*!< SCU SFSPC_12: EHS Mask              */
-#define SCU_SFSPC_12_EZI_Pos                                  6                                                         /*!< SCU SFSPC_12: EZI Position          */
-#define SCU_SFSPC_12_EZI_Msk                                  (0x01UL << SCU_SFSPC_12_EZI_Pos)                          /*!< SCU SFSPC_12: EZI Mask              */
-#define SCU_SFSPC_12_EHD_Pos                                  8                                                         /*!< SCU SFSPC_12: EHD Position          */
-#define SCU_SFSPC_12_EHD_Msk                                  (0x03UL << SCU_SFSPC_12_EHD_Pos)                          /*!< SCU SFSPC_12: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPC_13  ------------------------------------------
-#define SCU_SFSPC_13_MODE_Pos                                 0                                                         /*!< SCU SFSPC_13: MODE Position         */
-#define SCU_SFSPC_13_MODE_Msk                                 (0x07UL << SCU_SFSPC_13_MODE_Pos)                         /*!< SCU SFSPC_13: MODE Mask             */
-#define SCU_SFSPC_13_EPD_Pos                                  3                                                         /*!< SCU SFSPC_13: EPD Position          */
-#define SCU_SFSPC_13_EPD_Msk                                  (0x01UL << SCU_SFSPC_13_EPD_Pos)                          /*!< SCU SFSPC_13: EPD Mask              */
-#define SCU_SFSPC_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_13: EPUN Position         */
-#define SCU_SFSPC_13_EPUN_Msk                                 (0x01UL << SCU_SFSPC_13_EPUN_Pos)                         /*!< SCU SFSPC_13: EPUN Mask             */
-#define SCU_SFSPC_13_EHS_Pos                                  5                                                         /*!< SCU SFSPC_13: EHS Position          */
-#define SCU_SFSPC_13_EHS_Msk                                  (0x01UL << SCU_SFSPC_13_EHS_Pos)                          /*!< SCU SFSPC_13: EHS Mask              */
-#define SCU_SFSPC_13_EZI_Pos                                  6                                                         /*!< SCU SFSPC_13: EZI Position          */
-#define SCU_SFSPC_13_EZI_Msk                                  (0x01UL << SCU_SFSPC_13_EZI_Pos)                          /*!< SCU SFSPC_13: EZI Mask              */
-#define SCU_SFSPC_13_EHD_Pos                                  8                                                         /*!< SCU SFSPC_13: EHD Position          */
-#define SCU_SFSPC_13_EHD_Msk                                  (0x03UL << SCU_SFSPC_13_EHD_Pos)                          /*!< SCU SFSPC_13: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPC_14  ------------------------------------------
-#define SCU_SFSPC_14_MODE_Pos                                 0                                                         /*!< SCU SFSPC_14: MODE Position         */
-#define SCU_SFSPC_14_MODE_Msk                                 (0x07UL << SCU_SFSPC_14_MODE_Pos)                         /*!< SCU SFSPC_14: MODE Mask             */
-#define SCU_SFSPC_14_EPD_Pos                                  3                                                         /*!< SCU SFSPC_14: EPD Position          */
-#define SCU_SFSPC_14_EPD_Msk                                  (0x01UL << SCU_SFSPC_14_EPD_Pos)                          /*!< SCU SFSPC_14: EPD Mask              */
-#define SCU_SFSPC_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPC_14: EPUN Position         */
-#define SCU_SFSPC_14_EPUN_Msk                                 (0x01UL << SCU_SFSPC_14_EPUN_Pos)                         /*!< SCU SFSPC_14: EPUN Mask             */
-#define SCU_SFSPC_14_EHS_Pos                                  5                                                         /*!< SCU SFSPC_14: EHS Position          */
-#define SCU_SFSPC_14_EHS_Msk                                  (0x01UL << SCU_SFSPC_14_EHS_Pos)                          /*!< SCU SFSPC_14: EHS Mask              */
-#define SCU_SFSPC_14_EZI_Pos                                  6                                                         /*!< SCU SFSPC_14: EZI Position          */
-#define SCU_SFSPC_14_EZI_Msk                                  (0x01UL << SCU_SFSPC_14_EZI_Pos)                          /*!< SCU SFSPC_14: EZI Mask              */
-#define SCU_SFSPC_14_EHD_Pos                                  8                                                         /*!< SCU SFSPC_14: EHD Position          */
-#define SCU_SFSPC_14_EHD_Msk                                  (0x03UL << SCU_SFSPC_14_EHD_Pos)                          /*!< SCU SFSPC_14: EHD Mask              */
-
-// ---------------------------------------  SCU_SFSPD_0  ------------------------------------------
-#define SCU_SFSPD_0_MODE_Pos                                  0                                                         /*!< SCU SFSPD_0: MODE Position          */
-#define SCU_SFSPD_0_MODE_Msk                                  (0x07UL << SCU_SFSPD_0_MODE_Pos)                          /*!< SCU SFSPD_0: MODE Mask              */
-#define SCU_SFSPD_0_EPD_Pos                                   3                                                         /*!< SCU SFSPD_0: EPD Position           */
-#define SCU_SFSPD_0_EPD_Msk                                   (0x01UL << SCU_SFSPD_0_EPD_Pos)                           /*!< SCU SFSPD_0: EPD Mask               */
-#define SCU_SFSPD_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_0: EPUN Position          */
-#define SCU_SFSPD_0_EPUN_Msk                                  (0x01UL << SCU_SFSPD_0_EPUN_Pos)                          /*!< SCU SFSPD_0: EPUN Mask              */
-#define SCU_SFSPD_0_EHS_Pos                                   5                                                         /*!< SCU SFSPD_0: EHS Position           */
-#define SCU_SFSPD_0_EHS_Msk                                   (0x01UL << SCU_SFSPD_0_EHS_Pos)                           /*!< SCU SFSPD_0: EHS Mask               */
-#define SCU_SFSPD_0_EZI_Pos                                   6                                                         /*!< SCU SFSPD_0: EZI Position           */
-#define SCU_SFSPD_0_EZI_Msk                                   (0x01UL << SCU_SFSPD_0_EZI_Pos)                           /*!< SCU SFSPD_0: EZI Mask               */
-#define SCU_SFSPD_0_EHD_Pos                                   8                                                         /*!< SCU SFSPD_0: EHD Position           */
-#define SCU_SFSPD_0_EHD_Msk                                   (0x03UL << SCU_SFSPD_0_EHD_Pos)                           /*!< SCU SFSPD_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPD_1  ------------------------------------------
-#define SCU_SFSPD_1_MODE_Pos                                  0                                                         /*!< SCU SFSPD_1: MODE Position          */
-#define SCU_SFSPD_1_MODE_Msk                                  (0x07UL << SCU_SFSPD_1_MODE_Pos)                          /*!< SCU SFSPD_1: MODE Mask              */
-#define SCU_SFSPD_1_EPD_Pos                                   3                                                         /*!< SCU SFSPD_1: EPD Position           */
-#define SCU_SFSPD_1_EPD_Msk                                   (0x01UL << SCU_SFSPD_1_EPD_Pos)                           /*!< SCU SFSPD_1: EPD Mask               */
-#define SCU_SFSPD_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_1: EPUN Position          */
-#define SCU_SFSPD_1_EPUN_Msk                                  (0x01UL << SCU_SFSPD_1_EPUN_Pos)                          /*!< SCU SFSPD_1: EPUN Mask              */
-#define SCU_SFSPD_1_EHS_Pos                                   5                                                         /*!< SCU SFSPD_1: EHS Position           */
-#define SCU_SFSPD_1_EHS_Msk                                   (0x01UL << SCU_SFSPD_1_EHS_Pos)                           /*!< SCU SFSPD_1: EHS Mask               */
-#define SCU_SFSPD_1_EZI_Pos                                   6                                                         /*!< SCU SFSPD_1: EZI Position           */
-#define SCU_SFSPD_1_EZI_Msk                                   (0x01UL << SCU_SFSPD_1_EZI_Pos)                           /*!< SCU SFSPD_1: EZI Mask               */
-#define SCU_SFSPD_1_EHD_Pos                                   8                                                         /*!< SCU SFSPD_1: EHD Position           */
-#define SCU_SFSPD_1_EHD_Msk                                   (0x03UL << SCU_SFSPD_1_EHD_Pos)                           /*!< SCU SFSPD_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPD_2  ------------------------------------------
-#define SCU_SFSPD_2_MODE_Pos                                  0                                                         /*!< SCU SFSPD_2: MODE Position          */
-#define SCU_SFSPD_2_MODE_Msk                                  (0x07UL << SCU_SFSPD_2_MODE_Pos)                          /*!< SCU SFSPD_2: MODE Mask              */
-#define SCU_SFSPD_2_EPD_Pos                                   3                                                         /*!< SCU SFSPD_2: EPD Position           */
-#define SCU_SFSPD_2_EPD_Msk                                   (0x01UL << SCU_SFSPD_2_EPD_Pos)                           /*!< SCU SFSPD_2: EPD Mask               */
-#define SCU_SFSPD_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_2: EPUN Position          */
-#define SCU_SFSPD_2_EPUN_Msk                                  (0x01UL << SCU_SFSPD_2_EPUN_Pos)                          /*!< SCU SFSPD_2: EPUN Mask              */
-#define SCU_SFSPD_2_EHS_Pos                                   5                                                         /*!< SCU SFSPD_2: EHS Position           */
-#define SCU_SFSPD_2_EHS_Msk                                   (0x01UL << SCU_SFSPD_2_EHS_Pos)                           /*!< SCU SFSPD_2: EHS Mask               */
-#define SCU_SFSPD_2_EZI_Pos                                   6                                                         /*!< SCU SFSPD_2: EZI Position           */
-#define SCU_SFSPD_2_EZI_Msk                                   (0x01UL << SCU_SFSPD_2_EZI_Pos)                           /*!< SCU SFSPD_2: EZI Mask               */
-#define SCU_SFSPD_2_EHD_Pos                                   8                                                         /*!< SCU SFSPD_2: EHD Position           */
-#define SCU_SFSPD_2_EHD_Msk                                   (0x03UL << SCU_SFSPD_2_EHD_Pos)                           /*!< SCU SFSPD_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPD_3  ------------------------------------------
-#define SCU_SFSPD_3_MODE_Pos                                  0                                                         /*!< SCU SFSPD_3: MODE Position          */
-#define SCU_SFSPD_3_MODE_Msk                                  (0x07UL << SCU_SFSPD_3_MODE_Pos)                          /*!< SCU SFSPD_3: MODE Mask              */
-#define SCU_SFSPD_3_EPD_Pos                                   3                                                         /*!< SCU SFSPD_3: EPD Position           */
-#define SCU_SFSPD_3_EPD_Msk                                   (0x01UL << SCU_SFSPD_3_EPD_Pos)                           /*!< SCU SFSPD_3: EPD Mask               */
-#define SCU_SFSPD_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_3: EPUN Position          */
-#define SCU_SFSPD_3_EPUN_Msk                                  (0x01UL << SCU_SFSPD_3_EPUN_Pos)                          /*!< SCU SFSPD_3: EPUN Mask              */
-#define SCU_SFSPD_3_EHS_Pos                                   5                                                         /*!< SCU SFSPD_3: EHS Position           */
-#define SCU_SFSPD_3_EHS_Msk                                   (0x01UL << SCU_SFSPD_3_EHS_Pos)                           /*!< SCU SFSPD_3: EHS Mask               */
-#define SCU_SFSPD_3_EZI_Pos                                   6                                                         /*!< SCU SFSPD_3: EZI Position           */
-#define SCU_SFSPD_3_EZI_Msk                                   (0x01UL << SCU_SFSPD_3_EZI_Pos)                           /*!< SCU SFSPD_3: EZI Mask               */
-#define SCU_SFSPD_3_EHD_Pos                                   8                                                         /*!< SCU SFSPD_3: EHD Position           */
-#define SCU_SFSPD_3_EHD_Msk                                   (0x03UL << SCU_SFSPD_3_EHD_Pos)                           /*!< SCU SFSPD_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPD_4  ------------------------------------------
-#define SCU_SFSPD_4_MODE_Pos                                  0                                                         /*!< SCU SFSPD_4: MODE Position          */
-#define SCU_SFSPD_4_MODE_Msk                                  (0x07UL << SCU_SFSPD_4_MODE_Pos)                          /*!< SCU SFSPD_4: MODE Mask              */
-#define SCU_SFSPD_4_EPD_Pos                                   3                                                         /*!< SCU SFSPD_4: EPD Position           */
-#define SCU_SFSPD_4_EPD_Msk                                   (0x01UL << SCU_SFSPD_4_EPD_Pos)                           /*!< SCU SFSPD_4: EPD Mask               */
-#define SCU_SFSPD_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_4: EPUN Position          */
-#define SCU_SFSPD_4_EPUN_Msk                                  (0x01UL << SCU_SFSPD_4_EPUN_Pos)                          /*!< SCU SFSPD_4: EPUN Mask              */
-#define SCU_SFSPD_4_EHS_Pos                                   5                                                         /*!< SCU SFSPD_4: EHS Position           */
-#define SCU_SFSPD_4_EHS_Msk                                   (0x01UL << SCU_SFSPD_4_EHS_Pos)                           /*!< SCU SFSPD_4: EHS Mask               */
-#define SCU_SFSPD_4_EZI_Pos                                   6                                                         /*!< SCU SFSPD_4: EZI Position           */
-#define SCU_SFSPD_4_EZI_Msk                                   (0x01UL << SCU_SFSPD_4_EZI_Pos)                           /*!< SCU SFSPD_4: EZI Mask               */
-#define SCU_SFSPD_4_EHD_Pos                                   8                                                         /*!< SCU SFSPD_4: EHD Position           */
-#define SCU_SFSPD_4_EHD_Msk                                   (0x03UL << SCU_SFSPD_4_EHD_Pos)                           /*!< SCU SFSPD_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPD_5  ------------------------------------------
-#define SCU_SFSPD_5_MODE_Pos                                  0                                                         /*!< SCU SFSPD_5: MODE Position          */
-#define SCU_SFSPD_5_MODE_Msk                                  (0x07UL << SCU_SFSPD_5_MODE_Pos)                          /*!< SCU SFSPD_5: MODE Mask              */
-#define SCU_SFSPD_5_EPD_Pos                                   3                                                         /*!< SCU SFSPD_5: EPD Position           */
-#define SCU_SFSPD_5_EPD_Msk                                   (0x01UL << SCU_SFSPD_5_EPD_Pos)                           /*!< SCU SFSPD_5: EPD Mask               */
-#define SCU_SFSPD_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_5: EPUN Position          */
-#define SCU_SFSPD_5_EPUN_Msk                                  (0x01UL << SCU_SFSPD_5_EPUN_Pos)                          /*!< SCU SFSPD_5: EPUN Mask              */
-#define SCU_SFSPD_5_EHS_Pos                                   5                                                         /*!< SCU SFSPD_5: EHS Position           */
-#define SCU_SFSPD_5_EHS_Msk                                   (0x01UL << SCU_SFSPD_5_EHS_Pos)                           /*!< SCU SFSPD_5: EHS Mask               */
-#define SCU_SFSPD_5_EZI_Pos                                   6                                                         /*!< SCU SFSPD_5: EZI Position           */
-#define SCU_SFSPD_5_EZI_Msk                                   (0x01UL << SCU_SFSPD_5_EZI_Pos)                           /*!< SCU SFSPD_5: EZI Mask               */
-#define SCU_SFSPD_5_EHD_Pos                                   8                                                         /*!< SCU SFSPD_5: EHD Position           */
-#define SCU_SFSPD_5_EHD_Msk                                   (0x03UL << SCU_SFSPD_5_EHD_Pos)                           /*!< SCU SFSPD_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPD_6  ------------------------------------------
-#define SCU_SFSPD_6_MODE_Pos                                  0                                                         /*!< SCU SFSPD_6: MODE Position          */
-#define SCU_SFSPD_6_MODE_Msk                                  (0x07UL << SCU_SFSPD_6_MODE_Pos)                          /*!< SCU SFSPD_6: MODE Mask              */
-#define SCU_SFSPD_6_EPD_Pos                                   3                                                         /*!< SCU SFSPD_6: EPD Position           */
-#define SCU_SFSPD_6_EPD_Msk                                   (0x01UL << SCU_SFSPD_6_EPD_Pos)                           /*!< SCU SFSPD_6: EPD Mask               */
-#define SCU_SFSPD_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_6: EPUN Position          */
-#define SCU_SFSPD_6_EPUN_Msk                                  (0x01UL << SCU_SFSPD_6_EPUN_Pos)                          /*!< SCU SFSPD_6: EPUN Mask              */
-#define SCU_SFSPD_6_EHS_Pos                                   5                                                         /*!< SCU SFSPD_6: EHS Position           */
-#define SCU_SFSPD_6_EHS_Msk                                   (0x01UL << SCU_SFSPD_6_EHS_Pos)                           /*!< SCU SFSPD_6: EHS Mask               */
-#define SCU_SFSPD_6_EZI_Pos                                   6                                                         /*!< SCU SFSPD_6: EZI Position           */
-#define SCU_SFSPD_6_EZI_Msk                                   (0x01UL << SCU_SFSPD_6_EZI_Pos)                           /*!< SCU SFSPD_6: EZI Mask               */
-#define SCU_SFSPD_6_EHD_Pos                                   8                                                         /*!< SCU SFSPD_6: EHD Position           */
-#define SCU_SFSPD_6_EHD_Msk                                   (0x03UL << SCU_SFSPD_6_EHD_Pos)                           /*!< SCU SFSPD_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPD_7  ------------------------------------------
-#define SCU_SFSPD_7_MODE_Pos                                  0                                                         /*!< SCU SFSPD_7: MODE Position          */
-#define SCU_SFSPD_7_MODE_Msk                                  (0x07UL << SCU_SFSPD_7_MODE_Pos)                          /*!< SCU SFSPD_7: MODE Mask              */
-#define SCU_SFSPD_7_EPD_Pos                                   3                                                         /*!< SCU SFSPD_7: EPD Position           */
-#define SCU_SFSPD_7_EPD_Msk                                   (0x01UL << SCU_SFSPD_7_EPD_Pos)                           /*!< SCU SFSPD_7: EPD Mask               */
-#define SCU_SFSPD_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_7: EPUN Position          */
-#define SCU_SFSPD_7_EPUN_Msk                                  (0x01UL << SCU_SFSPD_7_EPUN_Pos)                          /*!< SCU SFSPD_7: EPUN Mask              */
-#define SCU_SFSPD_7_EHS_Pos                                   5                                                         /*!< SCU SFSPD_7: EHS Position           */
-#define SCU_SFSPD_7_EHS_Msk                                   (0x01UL << SCU_SFSPD_7_EHS_Pos)                           /*!< SCU SFSPD_7: EHS Mask               */
-#define SCU_SFSPD_7_EZI_Pos                                   6                                                         /*!< SCU SFSPD_7: EZI Position           */
-#define SCU_SFSPD_7_EZI_Msk                                   (0x01UL << SCU_SFSPD_7_EZI_Pos)                           /*!< SCU SFSPD_7: EZI Mask               */
-#define SCU_SFSPD_7_EHD_Pos                                   8                                                         /*!< SCU SFSPD_7: EHD Position           */
-#define SCU_SFSPD_7_EHD_Msk                                   (0x03UL << SCU_SFSPD_7_EHD_Pos)                           /*!< SCU SFSPD_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPD_8  ------------------------------------------
-#define SCU_SFSPD_8_MODE_Pos                                  0                                                         /*!< SCU SFSPD_8: MODE Position          */
-#define SCU_SFSPD_8_MODE_Msk                                  (0x07UL << SCU_SFSPD_8_MODE_Pos)                          /*!< SCU SFSPD_8: MODE Mask              */
-#define SCU_SFSPD_8_EPD_Pos                                   3                                                         /*!< SCU SFSPD_8: EPD Position           */
-#define SCU_SFSPD_8_EPD_Msk                                   (0x01UL << SCU_SFSPD_8_EPD_Pos)                           /*!< SCU SFSPD_8: EPD Mask               */
-#define SCU_SFSPD_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_8: EPUN Position          */
-#define SCU_SFSPD_8_EPUN_Msk                                  (0x01UL << SCU_SFSPD_8_EPUN_Pos)                          /*!< SCU SFSPD_8: EPUN Mask              */
-#define SCU_SFSPD_8_EHS_Pos                                   5                                                         /*!< SCU SFSPD_8: EHS Position           */
-#define SCU_SFSPD_8_EHS_Msk                                   (0x01UL << SCU_SFSPD_8_EHS_Pos)                           /*!< SCU SFSPD_8: EHS Mask               */
-#define SCU_SFSPD_8_EZI_Pos                                   6                                                         /*!< SCU SFSPD_8: EZI Position           */
-#define SCU_SFSPD_8_EZI_Msk                                   (0x01UL << SCU_SFSPD_8_EZI_Pos)                           /*!< SCU SFSPD_8: EZI Mask               */
-#define SCU_SFSPD_8_EHD_Pos                                   8                                                         /*!< SCU SFSPD_8: EHD Position           */
-#define SCU_SFSPD_8_EHD_Msk                                   (0x03UL << SCU_SFSPD_8_EHD_Pos)                           /*!< SCU SFSPD_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPD_9  ------------------------------------------
-#define SCU_SFSPD_9_MODE_Pos                                  0                                                         /*!< SCU SFSPD_9: MODE Position          */
-#define SCU_SFSPD_9_MODE_Msk                                  (0x07UL << SCU_SFSPD_9_MODE_Pos)                          /*!< SCU SFSPD_9: MODE Mask              */
-#define SCU_SFSPD_9_EPD_Pos                                   3                                                         /*!< SCU SFSPD_9: EPD Position           */
-#define SCU_SFSPD_9_EPD_Msk                                   (0x01UL << SCU_SFSPD_9_EPD_Pos)                           /*!< SCU SFSPD_9: EPD Mask               */
-#define SCU_SFSPD_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPD_9: EPUN Position          */
-#define SCU_SFSPD_9_EPUN_Msk                                  (0x01UL << SCU_SFSPD_9_EPUN_Pos)                          /*!< SCU SFSPD_9: EPUN Mask              */
-#define SCU_SFSPD_9_EHS_Pos                                   5                                                         /*!< SCU SFSPD_9: EHS Position           */
-#define SCU_SFSPD_9_EHS_Msk                                   (0x01UL << SCU_SFSPD_9_EHS_Pos)                           /*!< SCU SFSPD_9: EHS Mask               */
-#define SCU_SFSPD_9_EZI_Pos                                   6                                                         /*!< SCU SFSPD_9: EZI Position           */
-#define SCU_SFSPD_9_EZI_Msk                                   (0x01UL << SCU_SFSPD_9_EZI_Pos)                           /*!< SCU SFSPD_9: EZI Mask               */
-#define SCU_SFSPD_9_EHD_Pos                                   8                                                         /*!< SCU SFSPD_9: EHD Position           */
-#define SCU_SFSPD_9_EHD_Msk                                   (0x03UL << SCU_SFSPD_9_EHD_Pos)                           /*!< SCU SFSPD_9: EHD Mask               */
-
-// --------------------------------------  SCU_SFSPD_10  ------------------------------------------
-#define SCU_SFSPD_10_MODE_Pos                                 0                                                         /*!< SCU SFSPD_10: MODE Position         */
-#define SCU_SFSPD_10_MODE_Msk                                 (0x07UL << SCU_SFSPD_10_MODE_Pos)                         /*!< SCU SFSPD_10: MODE Mask             */
-#define SCU_SFSPD_10_EPD_Pos                                  3                                                         /*!< SCU SFSPD_10: EPD Position          */
-#define SCU_SFSPD_10_EPD_Msk                                  (0x01UL << SCU_SFSPD_10_EPD_Pos)                          /*!< SCU SFSPD_10: EPD Mask              */
-#define SCU_SFSPD_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_10: EPUN Position         */
-#define SCU_SFSPD_10_EPUN_Msk                                 (0x01UL << SCU_SFSPD_10_EPUN_Pos)                         /*!< SCU SFSPD_10: EPUN Mask             */
-#define SCU_SFSPD_10_EHS_Pos                                  5                                                         /*!< SCU SFSPD_10: EHS Position          */
-#define SCU_SFSPD_10_EHS_Msk                                  (0x01UL << SCU_SFSPD_10_EHS_Pos)                          /*!< SCU SFSPD_10: EHS Mask              */
-#define SCU_SFSPD_10_EZI_Pos                                  6                                                         /*!< SCU SFSPD_10: EZI Position          */
-#define SCU_SFSPD_10_EZI_Msk                                  (0x01UL << SCU_SFSPD_10_EZI_Pos)                          /*!< SCU SFSPD_10: EZI Mask              */
-#define SCU_SFSPD_10_EHD_Pos                                  8                                                         /*!< SCU SFSPD_10: EHD Position          */
-#define SCU_SFSPD_10_EHD_Msk                                  (0x03UL << SCU_SFSPD_10_EHD_Pos)                          /*!< SCU SFSPD_10: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPD_11  ------------------------------------------
-#define SCU_SFSPD_11_MODE_Pos                                 0                                                         /*!< SCU SFSPD_11: MODE Position         */
-#define SCU_SFSPD_11_MODE_Msk                                 (0x07UL << SCU_SFSPD_11_MODE_Pos)                         /*!< SCU SFSPD_11: MODE Mask             */
-#define SCU_SFSPD_11_EPD_Pos                                  3                                                         /*!< SCU SFSPD_11: EPD Position          */
-#define SCU_SFSPD_11_EPD_Msk                                  (0x01UL << SCU_SFSPD_11_EPD_Pos)                          /*!< SCU SFSPD_11: EPD Mask              */
-#define SCU_SFSPD_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_11: EPUN Position         */
-#define SCU_SFSPD_11_EPUN_Msk                                 (0x01UL << SCU_SFSPD_11_EPUN_Pos)                         /*!< SCU SFSPD_11: EPUN Mask             */
-#define SCU_SFSPD_11_EHS_Pos                                  5                                                         /*!< SCU SFSPD_11: EHS Position          */
-#define SCU_SFSPD_11_EHS_Msk                                  (0x01UL << SCU_SFSPD_11_EHS_Pos)                          /*!< SCU SFSPD_11: EHS Mask              */
-#define SCU_SFSPD_11_EZI_Pos                                  6                                                         /*!< SCU SFSPD_11: EZI Position          */
-#define SCU_SFSPD_11_EZI_Msk                                  (0x01UL << SCU_SFSPD_11_EZI_Pos)                          /*!< SCU SFSPD_11: EZI Mask              */
-#define SCU_SFSPD_11_EHD_Pos                                  8                                                         /*!< SCU SFSPD_11: EHD Position          */
-#define SCU_SFSPD_11_EHD_Msk                                  (0x03UL << SCU_SFSPD_11_EHD_Pos)                          /*!< SCU SFSPD_11: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPD_12  ------------------------------------------
-#define SCU_SFSPD_12_MODE_Pos                                 0                                                         /*!< SCU SFSPD_12: MODE Position         */
-#define SCU_SFSPD_12_MODE_Msk                                 (0x07UL << SCU_SFSPD_12_MODE_Pos)                         /*!< SCU SFSPD_12: MODE Mask             */
-#define SCU_SFSPD_12_EPD_Pos                                  3                                                         /*!< SCU SFSPD_12: EPD Position          */
-#define SCU_SFSPD_12_EPD_Msk                                  (0x01UL << SCU_SFSPD_12_EPD_Pos)                          /*!< SCU SFSPD_12: EPD Mask              */
-#define SCU_SFSPD_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_12: EPUN Position         */
-#define SCU_SFSPD_12_EPUN_Msk                                 (0x01UL << SCU_SFSPD_12_EPUN_Pos)                         /*!< SCU SFSPD_12: EPUN Mask             */
-#define SCU_SFSPD_12_EHS_Pos                                  5                                                         /*!< SCU SFSPD_12: EHS Position          */
-#define SCU_SFSPD_12_EHS_Msk                                  (0x01UL << SCU_SFSPD_12_EHS_Pos)                          /*!< SCU SFSPD_12: EHS Mask              */
-#define SCU_SFSPD_12_EZI_Pos                                  6                                                         /*!< SCU SFSPD_12: EZI Position          */
-#define SCU_SFSPD_12_EZI_Msk                                  (0x01UL << SCU_SFSPD_12_EZI_Pos)                          /*!< SCU SFSPD_12: EZI Mask              */
-#define SCU_SFSPD_12_EHD_Pos                                  8                                                         /*!< SCU SFSPD_12: EHD Position          */
-#define SCU_SFSPD_12_EHD_Msk                                  (0x03UL << SCU_SFSPD_12_EHD_Pos)                          /*!< SCU SFSPD_12: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPD_13  ------------------------------------------
-#define SCU_SFSPD_13_MODE_Pos                                 0                                                         /*!< SCU SFSPD_13: MODE Position         */
-#define SCU_SFSPD_13_MODE_Msk                                 (0x07UL << SCU_SFSPD_13_MODE_Pos)                         /*!< SCU SFSPD_13: MODE Mask             */
-#define SCU_SFSPD_13_EPD_Pos                                  3                                                         /*!< SCU SFSPD_13: EPD Position          */
-#define SCU_SFSPD_13_EPD_Msk                                  (0x01UL << SCU_SFSPD_13_EPD_Pos)                          /*!< SCU SFSPD_13: EPD Mask              */
-#define SCU_SFSPD_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_13: EPUN Position         */
-#define SCU_SFSPD_13_EPUN_Msk                                 (0x01UL << SCU_SFSPD_13_EPUN_Pos)                         /*!< SCU SFSPD_13: EPUN Mask             */
-#define SCU_SFSPD_13_EHS_Pos                                  5                                                         /*!< SCU SFSPD_13: EHS Position          */
-#define SCU_SFSPD_13_EHS_Msk                                  (0x01UL << SCU_SFSPD_13_EHS_Pos)                          /*!< SCU SFSPD_13: EHS Mask              */
-#define SCU_SFSPD_13_EZI_Pos                                  6                                                         /*!< SCU SFSPD_13: EZI Position          */
-#define SCU_SFSPD_13_EZI_Msk                                  (0x01UL << SCU_SFSPD_13_EZI_Pos)                          /*!< SCU SFSPD_13: EZI Mask              */
-#define SCU_SFSPD_13_EHD_Pos                                  8                                                         /*!< SCU SFSPD_13: EHD Position          */
-#define SCU_SFSPD_13_EHD_Msk                                  (0x03UL << SCU_SFSPD_13_EHD_Pos)                          /*!< SCU SFSPD_13: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPD_14  ------------------------------------------
-#define SCU_SFSPD_14_MODE_Pos                                 0                                                         /*!< SCU SFSPD_14: MODE Position         */
-#define SCU_SFSPD_14_MODE_Msk                                 (0x07UL << SCU_SFSPD_14_MODE_Pos)                         /*!< SCU SFSPD_14: MODE Mask             */
-#define SCU_SFSPD_14_EPD_Pos                                  3                                                         /*!< SCU SFSPD_14: EPD Position          */
-#define SCU_SFSPD_14_EPD_Msk                                  (0x01UL << SCU_SFSPD_14_EPD_Pos)                          /*!< SCU SFSPD_14: EPD Mask              */
-#define SCU_SFSPD_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_14: EPUN Position         */
-#define SCU_SFSPD_14_EPUN_Msk                                 (0x01UL << SCU_SFSPD_14_EPUN_Pos)                         /*!< SCU SFSPD_14: EPUN Mask             */
-#define SCU_SFSPD_14_EHS_Pos                                  5                                                         /*!< SCU SFSPD_14: EHS Position          */
-#define SCU_SFSPD_14_EHS_Msk                                  (0x01UL << SCU_SFSPD_14_EHS_Pos)                          /*!< SCU SFSPD_14: EHS Mask              */
-#define SCU_SFSPD_14_EZI_Pos                                  6                                                         /*!< SCU SFSPD_14: EZI Position          */
-#define SCU_SFSPD_14_EZI_Msk                                  (0x01UL << SCU_SFSPD_14_EZI_Pos)                          /*!< SCU SFSPD_14: EZI Mask              */
-#define SCU_SFSPD_14_EHD_Pos                                  8                                                         /*!< SCU SFSPD_14: EHD Position          */
-#define SCU_SFSPD_14_EHD_Msk                                  (0x03UL << SCU_SFSPD_14_EHD_Pos)                          /*!< SCU SFSPD_14: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPD_15  ------------------------------------------
-#define SCU_SFSPD_15_MODE_Pos                                 0                                                         /*!< SCU SFSPD_15: MODE Position         */
-#define SCU_SFSPD_15_MODE_Msk                                 (0x07UL << SCU_SFSPD_15_MODE_Pos)                         /*!< SCU SFSPD_15: MODE Mask             */
-#define SCU_SFSPD_15_EPD_Pos                                  3                                                         /*!< SCU SFSPD_15: EPD Position          */
-#define SCU_SFSPD_15_EPD_Msk                                  (0x01UL << SCU_SFSPD_15_EPD_Pos)                          /*!< SCU SFSPD_15: EPD Mask              */
-#define SCU_SFSPD_15_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_15: EPUN Position         */
-#define SCU_SFSPD_15_EPUN_Msk                                 (0x01UL << SCU_SFSPD_15_EPUN_Pos)                         /*!< SCU SFSPD_15: EPUN Mask             */
-#define SCU_SFSPD_15_EHS_Pos                                  5                                                         /*!< SCU SFSPD_15: EHS Position          */
-#define SCU_SFSPD_15_EHS_Msk                                  (0x01UL << SCU_SFSPD_15_EHS_Pos)                          /*!< SCU SFSPD_15: EHS Mask              */
-#define SCU_SFSPD_15_EZI_Pos                                  6                                                         /*!< SCU SFSPD_15: EZI Position          */
-#define SCU_SFSPD_15_EZI_Msk                                  (0x01UL << SCU_SFSPD_15_EZI_Pos)                          /*!< SCU SFSPD_15: EZI Mask              */
-#define SCU_SFSPD_15_EHD_Pos                                  8                                                         /*!< SCU SFSPD_15: EHD Position          */
-#define SCU_SFSPD_15_EHD_Msk                                  (0x03UL << SCU_SFSPD_15_EHD_Pos)                          /*!< SCU SFSPD_15: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPD_16  ------------------------------------------
-#define SCU_SFSPD_16_MODE_Pos                                 0                                                         /*!< SCU SFSPD_16: MODE Position         */
-#define SCU_SFSPD_16_MODE_Msk                                 (0x07UL << SCU_SFSPD_16_MODE_Pos)                         /*!< SCU SFSPD_16: MODE Mask             */
-#define SCU_SFSPD_16_EPD_Pos                                  3                                                         /*!< SCU SFSPD_16: EPD Position          */
-#define SCU_SFSPD_16_EPD_Msk                                  (0x01UL << SCU_SFSPD_16_EPD_Pos)                          /*!< SCU SFSPD_16: EPD Mask              */
-#define SCU_SFSPD_16_EPUN_Pos                                 4                                                         /*!< SCU SFSPD_16: EPUN Position         */
-#define SCU_SFSPD_16_EPUN_Msk                                 (0x01UL << SCU_SFSPD_16_EPUN_Pos)                         /*!< SCU SFSPD_16: EPUN Mask             */
-#define SCU_SFSPD_16_EHS_Pos                                  5                                                         /*!< SCU SFSPD_16: EHS Position          */
-#define SCU_SFSPD_16_EHS_Msk                                  (0x01UL << SCU_SFSPD_16_EHS_Pos)                          /*!< SCU SFSPD_16: EHS Mask              */
-#define SCU_SFSPD_16_EZI_Pos                                  6                                                         /*!< SCU SFSPD_16: EZI Position          */
-#define SCU_SFSPD_16_EZI_Msk                                  (0x01UL << SCU_SFSPD_16_EZI_Pos)                          /*!< SCU SFSPD_16: EZI Mask              */
-#define SCU_SFSPD_16_EHD_Pos                                  8                                                         /*!< SCU SFSPD_16: EHD Position          */
-#define SCU_SFSPD_16_EHD_Msk                                  (0x03UL << SCU_SFSPD_16_EHD_Pos)                          /*!< SCU SFSPD_16: EHD Mask              */
-
-// ---------------------------------------  SCU_SFSPE_0  ------------------------------------------
-#define SCU_SFSPE_0_MODE_Pos                                  0                                                         /*!< SCU SFSPE_0: MODE Position          */
-#define SCU_SFSPE_0_MODE_Msk                                  (0x07UL << SCU_SFSPE_0_MODE_Pos)                          /*!< SCU SFSPE_0: MODE Mask              */
-#define SCU_SFSPE_0_EPD_Pos                                   3                                                         /*!< SCU SFSPE_0: EPD Position           */
-#define SCU_SFSPE_0_EPD_Msk                                   (0x01UL << SCU_SFSPE_0_EPD_Pos)                           /*!< SCU SFSPE_0: EPD Mask               */
-#define SCU_SFSPE_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_0: EPUN Position          */
-#define SCU_SFSPE_0_EPUN_Msk                                  (0x01UL << SCU_SFSPE_0_EPUN_Pos)                          /*!< SCU SFSPE_0: EPUN Mask              */
-#define SCU_SFSPE_0_EHS_Pos                                   5                                                         /*!< SCU SFSPE_0: EHS Position           */
-#define SCU_SFSPE_0_EHS_Msk                                   (0x01UL << SCU_SFSPE_0_EHS_Pos)                           /*!< SCU SFSPE_0: EHS Mask               */
-#define SCU_SFSPE_0_EZI_Pos                                   6                                                         /*!< SCU SFSPE_0: EZI Position           */
-#define SCU_SFSPE_0_EZI_Msk                                   (0x01UL << SCU_SFSPE_0_EZI_Pos)                           /*!< SCU SFSPE_0: EZI Mask               */
-#define SCU_SFSPE_0_EHD_Pos                                   8                                                         /*!< SCU SFSPE_0: EHD Position           */
-#define SCU_SFSPE_0_EHD_Msk                                   (0x03UL << SCU_SFSPE_0_EHD_Pos)                           /*!< SCU SFSPE_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPE_1  ------------------------------------------
-#define SCU_SFSPE_1_MODE_Pos                                  0                                                         /*!< SCU SFSPE_1: MODE Position          */
-#define SCU_SFSPE_1_MODE_Msk                                  (0x07UL << SCU_SFSPE_1_MODE_Pos)                          /*!< SCU SFSPE_1: MODE Mask              */
-#define SCU_SFSPE_1_EPD_Pos                                   3                                                         /*!< SCU SFSPE_1: EPD Position           */
-#define SCU_SFSPE_1_EPD_Msk                                   (0x01UL << SCU_SFSPE_1_EPD_Pos)                           /*!< SCU SFSPE_1: EPD Mask               */
-#define SCU_SFSPE_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_1: EPUN Position          */
-#define SCU_SFSPE_1_EPUN_Msk                                  (0x01UL << SCU_SFSPE_1_EPUN_Pos)                          /*!< SCU SFSPE_1: EPUN Mask              */
-#define SCU_SFSPE_1_EHS_Pos                                   5                                                         /*!< SCU SFSPE_1: EHS Position           */
-#define SCU_SFSPE_1_EHS_Msk                                   (0x01UL << SCU_SFSPE_1_EHS_Pos)                           /*!< SCU SFSPE_1: EHS Mask               */
-#define SCU_SFSPE_1_EZI_Pos                                   6                                                         /*!< SCU SFSPE_1: EZI Position           */
-#define SCU_SFSPE_1_EZI_Msk                                   (0x01UL << SCU_SFSPE_1_EZI_Pos)                           /*!< SCU SFSPE_1: EZI Mask               */
-#define SCU_SFSPE_1_EHD_Pos                                   8                                                         /*!< SCU SFSPE_1: EHD Position           */
-#define SCU_SFSPE_1_EHD_Msk                                   (0x03UL << SCU_SFSPE_1_EHD_Pos)                           /*!< SCU SFSPE_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPE_2  ------------------------------------------
-#define SCU_SFSPE_2_MODE_Pos                                  0                                                         /*!< SCU SFSPE_2: MODE Position          */
-#define SCU_SFSPE_2_MODE_Msk                                  (0x07UL << SCU_SFSPE_2_MODE_Pos)                          /*!< SCU SFSPE_2: MODE Mask              */
-#define SCU_SFSPE_2_EPD_Pos                                   3                                                         /*!< SCU SFSPE_2: EPD Position           */
-#define SCU_SFSPE_2_EPD_Msk                                   (0x01UL << SCU_SFSPE_2_EPD_Pos)                           /*!< SCU SFSPE_2: EPD Mask               */
-#define SCU_SFSPE_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_2: EPUN Position          */
-#define SCU_SFSPE_2_EPUN_Msk                                  (0x01UL << SCU_SFSPE_2_EPUN_Pos)                          /*!< SCU SFSPE_2: EPUN Mask              */
-#define SCU_SFSPE_2_EHS_Pos                                   5                                                         /*!< SCU SFSPE_2: EHS Position           */
-#define SCU_SFSPE_2_EHS_Msk                                   (0x01UL << SCU_SFSPE_2_EHS_Pos)                           /*!< SCU SFSPE_2: EHS Mask               */
-#define SCU_SFSPE_2_EZI_Pos                                   6                                                         /*!< SCU SFSPE_2: EZI Position           */
-#define SCU_SFSPE_2_EZI_Msk                                   (0x01UL << SCU_SFSPE_2_EZI_Pos)                           /*!< SCU SFSPE_2: EZI Mask               */
-#define SCU_SFSPE_2_EHD_Pos                                   8                                                         /*!< SCU SFSPE_2: EHD Position           */
-#define SCU_SFSPE_2_EHD_Msk                                   (0x03UL << SCU_SFSPE_2_EHD_Pos)                           /*!< SCU SFSPE_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPE_3  ------------------------------------------
-#define SCU_SFSPE_3_MODE_Pos                                  0                                                         /*!< SCU SFSPE_3: MODE Position          */
-#define SCU_SFSPE_3_MODE_Msk                                  (0x07UL << SCU_SFSPE_3_MODE_Pos)                          /*!< SCU SFSPE_3: MODE Mask              */
-#define SCU_SFSPE_3_EPD_Pos                                   3                                                         /*!< SCU SFSPE_3: EPD Position           */
-#define SCU_SFSPE_3_EPD_Msk                                   (0x01UL << SCU_SFSPE_3_EPD_Pos)                           /*!< SCU SFSPE_3: EPD Mask               */
-#define SCU_SFSPE_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_3: EPUN Position          */
-#define SCU_SFSPE_3_EPUN_Msk                                  (0x01UL << SCU_SFSPE_3_EPUN_Pos)                          /*!< SCU SFSPE_3: EPUN Mask              */
-#define SCU_SFSPE_3_EHS_Pos                                   5                                                         /*!< SCU SFSPE_3: EHS Position           */
-#define SCU_SFSPE_3_EHS_Msk                                   (0x01UL << SCU_SFSPE_3_EHS_Pos)                           /*!< SCU SFSPE_3: EHS Mask               */
-#define SCU_SFSPE_3_EZI_Pos                                   6                                                         /*!< SCU SFSPE_3: EZI Position           */
-#define SCU_SFSPE_3_EZI_Msk                                   (0x01UL << SCU_SFSPE_3_EZI_Pos)                           /*!< SCU SFSPE_3: EZI Mask               */
-#define SCU_SFSPE_3_EHD_Pos                                   8                                                         /*!< SCU SFSPE_3: EHD Position           */
-#define SCU_SFSPE_3_EHD_Msk                                   (0x03UL << SCU_SFSPE_3_EHD_Pos)                           /*!< SCU SFSPE_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPE_4  ------------------------------------------
-#define SCU_SFSPE_4_MODE_Pos                                  0                                                         /*!< SCU SFSPE_4: MODE Position          */
-#define SCU_SFSPE_4_MODE_Msk                                  (0x07UL << SCU_SFSPE_4_MODE_Pos)                          /*!< SCU SFSPE_4: MODE Mask              */
-#define SCU_SFSPE_4_EPD_Pos                                   3                                                         /*!< SCU SFSPE_4: EPD Position           */
-#define SCU_SFSPE_4_EPD_Msk                                   (0x01UL << SCU_SFSPE_4_EPD_Pos)                           /*!< SCU SFSPE_4: EPD Mask               */
-#define SCU_SFSPE_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_4: EPUN Position          */
-#define SCU_SFSPE_4_EPUN_Msk                                  (0x01UL << SCU_SFSPE_4_EPUN_Pos)                          /*!< SCU SFSPE_4: EPUN Mask              */
-#define SCU_SFSPE_4_EHS_Pos                                   5                                                         /*!< SCU SFSPE_4: EHS Position           */
-#define SCU_SFSPE_4_EHS_Msk                                   (0x01UL << SCU_SFSPE_4_EHS_Pos)                           /*!< SCU SFSPE_4: EHS Mask               */
-#define SCU_SFSPE_4_EZI_Pos                                   6                                                         /*!< SCU SFSPE_4: EZI Position           */
-#define SCU_SFSPE_4_EZI_Msk                                   (0x01UL << SCU_SFSPE_4_EZI_Pos)                           /*!< SCU SFSPE_4: EZI Mask               */
-#define SCU_SFSPE_4_EHD_Pos                                   8                                                         /*!< SCU SFSPE_4: EHD Position           */
-#define SCU_SFSPE_4_EHD_Msk                                   (0x03UL << SCU_SFSPE_4_EHD_Pos)                           /*!< SCU SFSPE_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPE_5  ------------------------------------------
-#define SCU_SFSPE_5_MODE_Pos                                  0                                                         /*!< SCU SFSPE_5: MODE Position          */
-#define SCU_SFSPE_5_MODE_Msk                                  (0x07UL << SCU_SFSPE_5_MODE_Pos)                          /*!< SCU SFSPE_5: MODE Mask              */
-#define SCU_SFSPE_5_EPD_Pos                                   3                                                         /*!< SCU SFSPE_5: EPD Position           */
-#define SCU_SFSPE_5_EPD_Msk                                   (0x01UL << SCU_SFSPE_5_EPD_Pos)                           /*!< SCU SFSPE_5: EPD Mask               */
-#define SCU_SFSPE_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_5: EPUN Position          */
-#define SCU_SFSPE_5_EPUN_Msk                                  (0x01UL << SCU_SFSPE_5_EPUN_Pos)                          /*!< SCU SFSPE_5: EPUN Mask              */
-#define SCU_SFSPE_5_EHS_Pos                                   5                                                         /*!< SCU SFSPE_5: EHS Position           */
-#define SCU_SFSPE_5_EHS_Msk                                   (0x01UL << SCU_SFSPE_5_EHS_Pos)                           /*!< SCU SFSPE_5: EHS Mask               */
-#define SCU_SFSPE_5_EZI_Pos                                   6                                                         /*!< SCU SFSPE_5: EZI Position           */
-#define SCU_SFSPE_5_EZI_Msk                                   (0x01UL << SCU_SFSPE_5_EZI_Pos)                           /*!< SCU SFSPE_5: EZI Mask               */
-#define SCU_SFSPE_5_EHD_Pos                                   8                                                         /*!< SCU SFSPE_5: EHD Position           */
-#define SCU_SFSPE_5_EHD_Msk                                   (0x03UL << SCU_SFSPE_5_EHD_Pos)                           /*!< SCU SFSPE_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPE_6  ------------------------------------------
-#define SCU_SFSPE_6_MODE_Pos                                  0                                                         /*!< SCU SFSPE_6: MODE Position          */
-#define SCU_SFSPE_6_MODE_Msk                                  (0x07UL << SCU_SFSPE_6_MODE_Pos)                          /*!< SCU SFSPE_6: MODE Mask              */
-#define SCU_SFSPE_6_EPD_Pos                                   3                                                         /*!< SCU SFSPE_6: EPD Position           */
-#define SCU_SFSPE_6_EPD_Msk                                   (0x01UL << SCU_SFSPE_6_EPD_Pos)                           /*!< SCU SFSPE_6: EPD Mask               */
-#define SCU_SFSPE_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_6: EPUN Position          */
-#define SCU_SFSPE_6_EPUN_Msk                                  (0x01UL << SCU_SFSPE_6_EPUN_Pos)                          /*!< SCU SFSPE_6: EPUN Mask              */
-#define SCU_SFSPE_6_EHS_Pos                                   5                                                         /*!< SCU SFSPE_6: EHS Position           */
-#define SCU_SFSPE_6_EHS_Msk                                   (0x01UL << SCU_SFSPE_6_EHS_Pos)                           /*!< SCU SFSPE_6: EHS Mask               */
-#define SCU_SFSPE_6_EZI_Pos                                   6                                                         /*!< SCU SFSPE_6: EZI Position           */
-#define SCU_SFSPE_6_EZI_Msk                                   (0x01UL << SCU_SFSPE_6_EZI_Pos)                           /*!< SCU SFSPE_6: EZI Mask               */
-#define SCU_SFSPE_6_EHD_Pos                                   8                                                         /*!< SCU SFSPE_6: EHD Position           */
-#define SCU_SFSPE_6_EHD_Msk                                   (0x03UL << SCU_SFSPE_6_EHD_Pos)                           /*!< SCU SFSPE_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPE_7  ------------------------------------------
-#define SCU_SFSPE_7_MODE_Pos                                  0                                                         /*!< SCU SFSPE_7: MODE Position          */
-#define SCU_SFSPE_7_MODE_Msk                                  (0x07UL << SCU_SFSPE_7_MODE_Pos)                          /*!< SCU SFSPE_7: MODE Mask              */
-#define SCU_SFSPE_7_EPD_Pos                                   3                                                         /*!< SCU SFSPE_7: EPD Position           */
-#define SCU_SFSPE_7_EPD_Msk                                   (0x01UL << SCU_SFSPE_7_EPD_Pos)                           /*!< SCU SFSPE_7: EPD Mask               */
-#define SCU_SFSPE_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_7: EPUN Position          */
-#define SCU_SFSPE_7_EPUN_Msk                                  (0x01UL << SCU_SFSPE_7_EPUN_Pos)                          /*!< SCU SFSPE_7: EPUN Mask              */
-#define SCU_SFSPE_7_EHS_Pos                                   5                                                         /*!< SCU SFSPE_7: EHS Position           */
-#define SCU_SFSPE_7_EHS_Msk                                   (0x01UL << SCU_SFSPE_7_EHS_Pos)                           /*!< SCU SFSPE_7: EHS Mask               */
-#define SCU_SFSPE_7_EZI_Pos                                   6                                                         /*!< SCU SFSPE_7: EZI Position           */
-#define SCU_SFSPE_7_EZI_Msk                                   (0x01UL << SCU_SFSPE_7_EZI_Pos)                           /*!< SCU SFSPE_7: EZI Mask               */
-#define SCU_SFSPE_7_EHD_Pos                                   8                                                         /*!< SCU SFSPE_7: EHD Position           */
-#define SCU_SFSPE_7_EHD_Msk                                   (0x03UL << SCU_SFSPE_7_EHD_Pos)                           /*!< SCU SFSPE_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPE_8  ------------------------------------------
-#define SCU_SFSPE_8_MODE_Pos                                  0                                                         /*!< SCU SFSPE_8: MODE Position          */
-#define SCU_SFSPE_8_MODE_Msk                                  (0x07UL << SCU_SFSPE_8_MODE_Pos)                          /*!< SCU SFSPE_8: MODE Mask              */
-#define SCU_SFSPE_8_EPD_Pos                                   3                                                         /*!< SCU SFSPE_8: EPD Position           */
-#define SCU_SFSPE_8_EPD_Msk                                   (0x01UL << SCU_SFSPE_8_EPD_Pos)                           /*!< SCU SFSPE_8: EPD Mask               */
-#define SCU_SFSPE_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_8: EPUN Position          */
-#define SCU_SFSPE_8_EPUN_Msk                                  (0x01UL << SCU_SFSPE_8_EPUN_Pos)                          /*!< SCU SFSPE_8: EPUN Mask              */
-#define SCU_SFSPE_8_EHS_Pos                                   5                                                         /*!< SCU SFSPE_8: EHS Position           */
-#define SCU_SFSPE_8_EHS_Msk                                   (0x01UL << SCU_SFSPE_8_EHS_Pos)                           /*!< SCU SFSPE_8: EHS Mask               */
-#define SCU_SFSPE_8_EZI_Pos                                   6                                                         /*!< SCU SFSPE_8: EZI Position           */
-#define SCU_SFSPE_8_EZI_Msk                                   (0x01UL << SCU_SFSPE_8_EZI_Pos)                           /*!< SCU SFSPE_8: EZI Mask               */
-#define SCU_SFSPE_8_EHD_Pos                                   8                                                         /*!< SCU SFSPE_8: EHD Position           */
-#define SCU_SFSPE_8_EHD_Msk                                   (0x03UL << SCU_SFSPE_8_EHD_Pos)                           /*!< SCU SFSPE_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPE_9  ------------------------------------------
-#define SCU_SFSPE_9_MODE_Pos                                  0                                                         /*!< SCU SFSPE_9: MODE Position          */
-#define SCU_SFSPE_9_MODE_Msk                                  (0x07UL << SCU_SFSPE_9_MODE_Pos)                          /*!< SCU SFSPE_9: MODE Mask              */
-#define SCU_SFSPE_9_EPD_Pos                                   3                                                         /*!< SCU SFSPE_9: EPD Position           */
-#define SCU_SFSPE_9_EPD_Msk                                   (0x01UL << SCU_SFSPE_9_EPD_Pos)                           /*!< SCU SFSPE_9: EPD Mask               */
-#define SCU_SFSPE_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPE_9: EPUN Position          */
-#define SCU_SFSPE_9_EPUN_Msk                                  (0x01UL << SCU_SFSPE_9_EPUN_Pos)                          /*!< SCU SFSPE_9: EPUN Mask              */
-#define SCU_SFSPE_9_EHS_Pos                                   5                                                         /*!< SCU SFSPE_9: EHS Position           */
-#define SCU_SFSPE_9_EHS_Msk                                   (0x01UL << SCU_SFSPE_9_EHS_Pos)                           /*!< SCU SFSPE_9: EHS Mask               */
-#define SCU_SFSPE_9_EZI_Pos                                   6                                                         /*!< SCU SFSPE_9: EZI Position           */
-#define SCU_SFSPE_9_EZI_Msk                                   (0x01UL << SCU_SFSPE_9_EZI_Pos)                           /*!< SCU SFSPE_9: EZI Mask               */
-#define SCU_SFSPE_9_EHD_Pos                                   8                                                         /*!< SCU SFSPE_9: EHD Position           */
-#define SCU_SFSPE_9_EHD_Msk                                   (0x03UL << SCU_SFSPE_9_EHD_Pos)                           /*!< SCU SFSPE_9: EHD Mask               */
-
-// --------------------------------------  SCU_SFSPE_10  ------------------------------------------
-#define SCU_SFSPE_10_MODE_Pos                                 0                                                         /*!< SCU SFSPE_10: MODE Position         */
-#define SCU_SFSPE_10_MODE_Msk                                 (0x07UL << SCU_SFSPE_10_MODE_Pos)                         /*!< SCU SFSPE_10: MODE Mask             */
-#define SCU_SFSPE_10_EPD_Pos                                  3                                                         /*!< SCU SFSPE_10: EPD Position          */
-#define SCU_SFSPE_10_EPD_Msk                                  (0x01UL << SCU_SFSPE_10_EPD_Pos)                          /*!< SCU SFSPE_10: EPD Mask              */
-#define SCU_SFSPE_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_10: EPUN Position         */
-#define SCU_SFSPE_10_EPUN_Msk                                 (0x01UL << SCU_SFSPE_10_EPUN_Pos)                         /*!< SCU SFSPE_10: EPUN Mask             */
-#define SCU_SFSPE_10_EHS_Pos                                  5                                                         /*!< SCU SFSPE_10: EHS Position          */
-#define SCU_SFSPE_10_EHS_Msk                                  (0x01UL << SCU_SFSPE_10_EHS_Pos)                          /*!< SCU SFSPE_10: EHS Mask              */
-#define SCU_SFSPE_10_EZI_Pos                                  6                                                         /*!< SCU SFSPE_10: EZI Position          */
-#define SCU_SFSPE_10_EZI_Msk                                  (0x01UL << SCU_SFSPE_10_EZI_Pos)                          /*!< SCU SFSPE_10: EZI Mask              */
-#define SCU_SFSPE_10_EHD_Pos                                  8                                                         /*!< SCU SFSPE_10: EHD Position          */
-#define SCU_SFSPE_10_EHD_Msk                                  (0x03UL << SCU_SFSPE_10_EHD_Pos)                          /*!< SCU SFSPE_10: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPE_11  ------------------------------------------
-#define SCU_SFSPE_11_MODE_Pos                                 0                                                         /*!< SCU SFSPE_11: MODE Position         */
-#define SCU_SFSPE_11_MODE_Msk                                 (0x07UL << SCU_SFSPE_11_MODE_Pos)                         /*!< SCU SFSPE_11: MODE Mask             */
-#define SCU_SFSPE_11_EPD_Pos                                  3                                                         /*!< SCU SFSPE_11: EPD Position          */
-#define SCU_SFSPE_11_EPD_Msk                                  (0x01UL << SCU_SFSPE_11_EPD_Pos)                          /*!< SCU SFSPE_11: EPD Mask              */
-#define SCU_SFSPE_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_11: EPUN Position         */
-#define SCU_SFSPE_11_EPUN_Msk                                 (0x01UL << SCU_SFSPE_11_EPUN_Pos)                         /*!< SCU SFSPE_11: EPUN Mask             */
-#define SCU_SFSPE_11_EHS_Pos                                  5                                                         /*!< SCU SFSPE_11: EHS Position          */
-#define SCU_SFSPE_11_EHS_Msk                                  (0x01UL << SCU_SFSPE_11_EHS_Pos)                          /*!< SCU SFSPE_11: EHS Mask              */
-#define SCU_SFSPE_11_EZI_Pos                                  6                                                         /*!< SCU SFSPE_11: EZI Position          */
-#define SCU_SFSPE_11_EZI_Msk                                  (0x01UL << SCU_SFSPE_11_EZI_Pos)                          /*!< SCU SFSPE_11: EZI Mask              */
-#define SCU_SFSPE_11_EHD_Pos                                  8                                                         /*!< SCU SFSPE_11: EHD Position          */
-#define SCU_SFSPE_11_EHD_Msk                                  (0x03UL << SCU_SFSPE_11_EHD_Pos)                          /*!< SCU SFSPE_11: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPE_12  ------------------------------------------
-#define SCU_SFSPE_12_MODE_Pos                                 0                                                         /*!< SCU SFSPE_12: MODE Position         */
-#define SCU_SFSPE_12_MODE_Msk                                 (0x07UL << SCU_SFSPE_12_MODE_Pos)                         /*!< SCU SFSPE_12: MODE Mask             */
-#define SCU_SFSPE_12_EPD_Pos                                  3                                                         /*!< SCU SFSPE_12: EPD Position          */
-#define SCU_SFSPE_12_EPD_Msk                                  (0x01UL << SCU_SFSPE_12_EPD_Pos)                          /*!< SCU SFSPE_12: EPD Mask              */
-#define SCU_SFSPE_12_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_12: EPUN Position         */
-#define SCU_SFSPE_12_EPUN_Msk                                 (0x01UL << SCU_SFSPE_12_EPUN_Pos)                         /*!< SCU SFSPE_12: EPUN Mask             */
-#define SCU_SFSPE_12_EHS_Pos                                  5                                                         /*!< SCU SFSPE_12: EHS Position          */
-#define SCU_SFSPE_12_EHS_Msk                                  (0x01UL << SCU_SFSPE_12_EHS_Pos)                          /*!< SCU SFSPE_12: EHS Mask              */
-#define SCU_SFSPE_12_EZI_Pos                                  6                                                         /*!< SCU SFSPE_12: EZI Position          */
-#define SCU_SFSPE_12_EZI_Msk                                  (0x01UL << SCU_SFSPE_12_EZI_Pos)                          /*!< SCU SFSPE_12: EZI Mask              */
-#define SCU_SFSPE_12_EHD_Pos                                  8                                                         /*!< SCU SFSPE_12: EHD Position          */
-#define SCU_SFSPE_12_EHD_Msk                                  (0x03UL << SCU_SFSPE_12_EHD_Pos)                          /*!< SCU SFSPE_12: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPE_13  ------------------------------------------
-#define SCU_SFSPE_13_MODE_Pos                                 0                                                         /*!< SCU SFSPE_13: MODE Position         */
-#define SCU_SFSPE_13_MODE_Msk                                 (0x07UL << SCU_SFSPE_13_MODE_Pos)                         /*!< SCU SFSPE_13: MODE Mask             */
-#define SCU_SFSPE_13_EPD_Pos                                  3                                                         /*!< SCU SFSPE_13: EPD Position          */
-#define SCU_SFSPE_13_EPD_Msk                                  (0x01UL << SCU_SFSPE_13_EPD_Pos)                          /*!< SCU SFSPE_13: EPD Mask              */
-#define SCU_SFSPE_13_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_13: EPUN Position         */
-#define SCU_SFSPE_13_EPUN_Msk                                 (0x01UL << SCU_SFSPE_13_EPUN_Pos)                         /*!< SCU SFSPE_13: EPUN Mask             */
-#define SCU_SFSPE_13_EHS_Pos                                  5                                                         /*!< SCU SFSPE_13: EHS Position          */
-#define SCU_SFSPE_13_EHS_Msk                                  (0x01UL << SCU_SFSPE_13_EHS_Pos)                          /*!< SCU SFSPE_13: EHS Mask              */
-#define SCU_SFSPE_13_EZI_Pos                                  6                                                         /*!< SCU SFSPE_13: EZI Position          */
-#define SCU_SFSPE_13_EZI_Msk                                  (0x01UL << SCU_SFSPE_13_EZI_Pos)                          /*!< SCU SFSPE_13: EZI Mask              */
-#define SCU_SFSPE_13_EHD_Pos                                  8                                                         /*!< SCU SFSPE_13: EHD Position          */
-#define SCU_SFSPE_13_EHD_Msk                                  (0x03UL << SCU_SFSPE_13_EHD_Pos)                          /*!< SCU SFSPE_13: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPE_14  ------------------------------------------
-#define SCU_SFSPE_14_MODE_Pos                                 0                                                         /*!< SCU SFSPE_14: MODE Position         */
-#define SCU_SFSPE_14_MODE_Msk                                 (0x07UL << SCU_SFSPE_14_MODE_Pos)                         /*!< SCU SFSPE_14: MODE Mask             */
-#define SCU_SFSPE_14_EPD_Pos                                  3                                                         /*!< SCU SFSPE_14: EPD Position          */
-#define SCU_SFSPE_14_EPD_Msk                                  (0x01UL << SCU_SFSPE_14_EPD_Pos)                          /*!< SCU SFSPE_14: EPD Mask              */
-#define SCU_SFSPE_14_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_14: EPUN Position         */
-#define SCU_SFSPE_14_EPUN_Msk                                 (0x01UL << SCU_SFSPE_14_EPUN_Pos)                         /*!< SCU SFSPE_14: EPUN Mask             */
-#define SCU_SFSPE_14_EHS_Pos                                  5                                                         /*!< SCU SFSPE_14: EHS Position          */
-#define SCU_SFSPE_14_EHS_Msk                                  (0x01UL << SCU_SFSPE_14_EHS_Pos)                          /*!< SCU SFSPE_14: EHS Mask              */
-#define SCU_SFSPE_14_EZI_Pos                                  6                                                         /*!< SCU SFSPE_14: EZI Position          */
-#define SCU_SFSPE_14_EZI_Msk                                  (0x01UL << SCU_SFSPE_14_EZI_Pos)                          /*!< SCU SFSPE_14: EZI Mask              */
-#define SCU_SFSPE_14_EHD_Pos                                  8                                                         /*!< SCU SFSPE_14: EHD Position          */
-#define SCU_SFSPE_14_EHD_Msk                                  (0x03UL << SCU_SFSPE_14_EHD_Pos)                          /*!< SCU SFSPE_14: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPE_15  ------------------------------------------
-#define SCU_SFSPE_15_MODE_Pos                                 0                                                         /*!< SCU SFSPE_15: MODE Position         */
-#define SCU_SFSPE_15_MODE_Msk                                 (0x07UL << SCU_SFSPE_15_MODE_Pos)                         /*!< SCU SFSPE_15: MODE Mask             */
-#define SCU_SFSPE_15_EPD_Pos                                  3                                                         /*!< SCU SFSPE_15: EPD Position          */
-#define SCU_SFSPE_15_EPD_Msk                                  (0x01UL << SCU_SFSPE_15_EPD_Pos)                          /*!< SCU SFSPE_15: EPD Mask              */
-#define SCU_SFSPE_15_EPUN_Pos                                 4                                                         /*!< SCU SFSPE_15: EPUN Position         */
-#define SCU_SFSPE_15_EPUN_Msk                                 (0x01UL << SCU_SFSPE_15_EPUN_Pos)                         /*!< SCU SFSPE_15: EPUN Mask             */
-#define SCU_SFSPE_15_EHS_Pos                                  5                                                         /*!< SCU SFSPE_15: EHS Position          */
-#define SCU_SFSPE_15_EHS_Msk                                  (0x01UL << SCU_SFSPE_15_EHS_Pos)                          /*!< SCU SFSPE_15: EHS Mask              */
-#define SCU_SFSPE_15_EZI_Pos                                  6                                                         /*!< SCU SFSPE_15: EZI Position          */
-#define SCU_SFSPE_15_EZI_Msk                                  (0x01UL << SCU_SFSPE_15_EZI_Pos)                          /*!< SCU SFSPE_15: EZI Mask              */
-#define SCU_SFSPE_15_EHD_Pos                                  8                                                         /*!< SCU SFSPE_15: EHD Position          */
-#define SCU_SFSPE_15_EHD_Msk                                  (0x03UL << SCU_SFSPE_15_EHD_Pos)                          /*!< SCU SFSPE_15: EHD Mask              */
-
-// ---------------------------------------  SCU_SFSPF_0  ------------------------------------------
-#define SCU_SFSPF_0_MODE_Pos                                  0                                                         /*!< SCU SFSPF_0: MODE Position          */
-#define SCU_SFSPF_0_MODE_Msk                                  (0x07UL << SCU_SFSPF_0_MODE_Pos)                          /*!< SCU SFSPF_0: MODE Mask              */
-#define SCU_SFSPF_0_EPD_Pos                                   3                                                         /*!< SCU SFSPF_0: EPD Position           */
-#define SCU_SFSPF_0_EPD_Msk                                   (0x01UL << SCU_SFSPF_0_EPD_Pos)                           /*!< SCU SFSPF_0: EPD Mask               */
-#define SCU_SFSPF_0_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_0: EPUN Position          */
-#define SCU_SFSPF_0_EPUN_Msk                                  (0x01UL << SCU_SFSPF_0_EPUN_Pos)                          /*!< SCU SFSPF_0: EPUN Mask              */
-#define SCU_SFSPF_0_EHS_Pos                                   5                                                         /*!< SCU SFSPF_0: EHS Position           */
-#define SCU_SFSPF_0_EHS_Msk                                   (0x01UL << SCU_SFSPF_0_EHS_Pos)                           /*!< SCU SFSPF_0: EHS Mask               */
-#define SCU_SFSPF_0_EZI_Pos                                   6                                                         /*!< SCU SFSPF_0: EZI Position           */
-#define SCU_SFSPF_0_EZI_Msk                                   (0x01UL << SCU_SFSPF_0_EZI_Pos)                           /*!< SCU SFSPF_0: EZI Mask               */
-#define SCU_SFSPF_0_EHD_Pos                                   8                                                         /*!< SCU SFSPF_0: EHD Position           */
-#define SCU_SFSPF_0_EHD_Msk                                   (0x03UL << SCU_SFSPF_0_EHD_Pos)                           /*!< SCU SFSPF_0: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPF_1  ------------------------------------------
-#define SCU_SFSPF_1_MODE_Pos                                  0                                                         /*!< SCU SFSPF_1: MODE Position          */
-#define SCU_SFSPF_1_MODE_Msk                                  (0x07UL << SCU_SFSPF_1_MODE_Pos)                          /*!< SCU SFSPF_1: MODE Mask              */
-#define SCU_SFSPF_1_EPD_Pos                                   3                                                         /*!< SCU SFSPF_1: EPD Position           */
-#define SCU_SFSPF_1_EPD_Msk                                   (0x01UL << SCU_SFSPF_1_EPD_Pos)                           /*!< SCU SFSPF_1: EPD Mask               */
-#define SCU_SFSPF_1_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_1: EPUN Position          */
-#define SCU_SFSPF_1_EPUN_Msk                                  (0x01UL << SCU_SFSPF_1_EPUN_Pos)                          /*!< SCU SFSPF_1: EPUN Mask              */
-#define SCU_SFSPF_1_EHS_Pos                                   5                                                         /*!< SCU SFSPF_1: EHS Position           */
-#define SCU_SFSPF_1_EHS_Msk                                   (0x01UL << SCU_SFSPF_1_EHS_Pos)                           /*!< SCU SFSPF_1: EHS Mask               */
-#define SCU_SFSPF_1_EZI_Pos                                   6                                                         /*!< SCU SFSPF_1: EZI Position           */
-#define SCU_SFSPF_1_EZI_Msk                                   (0x01UL << SCU_SFSPF_1_EZI_Pos)                           /*!< SCU SFSPF_1: EZI Mask               */
-#define SCU_SFSPF_1_EHD_Pos                                   8                                                         /*!< SCU SFSPF_1: EHD Position           */
-#define SCU_SFSPF_1_EHD_Msk                                   (0x03UL << SCU_SFSPF_1_EHD_Pos)                           /*!< SCU SFSPF_1: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPF_2  ------------------------------------------
-#define SCU_SFSPF_2_MODE_Pos                                  0                                                         /*!< SCU SFSPF_2: MODE Position          */
-#define SCU_SFSPF_2_MODE_Msk                                  (0x07UL << SCU_SFSPF_2_MODE_Pos)                          /*!< SCU SFSPF_2: MODE Mask              */
-#define SCU_SFSPF_2_EPD_Pos                                   3                                                         /*!< SCU SFSPF_2: EPD Position           */
-#define SCU_SFSPF_2_EPD_Msk                                   (0x01UL << SCU_SFSPF_2_EPD_Pos)                           /*!< SCU SFSPF_2: EPD Mask               */
-#define SCU_SFSPF_2_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_2: EPUN Position          */
-#define SCU_SFSPF_2_EPUN_Msk                                  (0x01UL << SCU_SFSPF_2_EPUN_Pos)                          /*!< SCU SFSPF_2: EPUN Mask              */
-#define SCU_SFSPF_2_EHS_Pos                                   5                                                         /*!< SCU SFSPF_2: EHS Position           */
-#define SCU_SFSPF_2_EHS_Msk                                   (0x01UL << SCU_SFSPF_2_EHS_Pos)                           /*!< SCU SFSPF_2: EHS Mask               */
-#define SCU_SFSPF_2_EZI_Pos                                   6                                                         /*!< SCU SFSPF_2: EZI Position           */
-#define SCU_SFSPF_2_EZI_Msk                                   (0x01UL << SCU_SFSPF_2_EZI_Pos)                           /*!< SCU SFSPF_2: EZI Mask               */
-#define SCU_SFSPF_2_EHD_Pos                                   8                                                         /*!< SCU SFSPF_2: EHD Position           */
-#define SCU_SFSPF_2_EHD_Msk                                   (0x03UL << SCU_SFSPF_2_EHD_Pos)                           /*!< SCU SFSPF_2: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPF_3  ------------------------------------------
-#define SCU_SFSPF_3_MODE_Pos                                  0                                                         /*!< SCU SFSPF_3: MODE Position          */
-#define SCU_SFSPF_3_MODE_Msk                                  (0x07UL << SCU_SFSPF_3_MODE_Pos)                          /*!< SCU SFSPF_3: MODE Mask              */
-#define SCU_SFSPF_3_EPD_Pos                                   3                                                         /*!< SCU SFSPF_3: EPD Position           */
-#define SCU_SFSPF_3_EPD_Msk                                   (0x01UL << SCU_SFSPF_3_EPD_Pos)                           /*!< SCU SFSPF_3: EPD Mask               */
-#define SCU_SFSPF_3_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_3: EPUN Position          */
-#define SCU_SFSPF_3_EPUN_Msk                                  (0x01UL << SCU_SFSPF_3_EPUN_Pos)                          /*!< SCU SFSPF_3: EPUN Mask              */
-#define SCU_SFSPF_3_EHS_Pos                                   5                                                         /*!< SCU SFSPF_3: EHS Position           */
-#define SCU_SFSPF_3_EHS_Msk                                   (0x01UL << SCU_SFSPF_3_EHS_Pos)                           /*!< SCU SFSPF_3: EHS Mask               */
-#define SCU_SFSPF_3_EZI_Pos                                   6                                                         /*!< SCU SFSPF_3: EZI Position           */
-#define SCU_SFSPF_3_EZI_Msk                                   (0x01UL << SCU_SFSPF_3_EZI_Pos)                           /*!< SCU SFSPF_3: EZI Mask               */
-#define SCU_SFSPF_3_EHD_Pos                                   8                                                         /*!< SCU SFSPF_3: EHD Position           */
-#define SCU_SFSPF_3_EHD_Msk                                   (0x03UL << SCU_SFSPF_3_EHD_Pos)                           /*!< SCU SFSPF_3: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPF_4  ------------------------------------------
-#define SCU_SFSPF_4_MODE_Pos                                  0                                                         /*!< SCU SFSPF_4: MODE Position          */
-#define SCU_SFSPF_4_MODE_Msk                                  (0x07UL << SCU_SFSPF_4_MODE_Pos)                          /*!< SCU SFSPF_4: MODE Mask              */
-#define SCU_SFSPF_4_EPD_Pos                                   3                                                         /*!< SCU SFSPF_4: EPD Position           */
-#define SCU_SFSPF_4_EPD_Msk                                   (0x01UL << SCU_SFSPF_4_EPD_Pos)                           /*!< SCU SFSPF_4: EPD Mask               */
-#define SCU_SFSPF_4_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_4: EPUN Position          */
-#define SCU_SFSPF_4_EPUN_Msk                                  (0x01UL << SCU_SFSPF_4_EPUN_Pos)                          /*!< SCU SFSPF_4: EPUN Mask              */
-#define SCU_SFSPF_4_EHS_Pos                                   5                                                         /*!< SCU SFSPF_4: EHS Position           */
-#define SCU_SFSPF_4_EHS_Msk                                   (0x01UL << SCU_SFSPF_4_EHS_Pos)                           /*!< SCU SFSPF_4: EHS Mask               */
-#define SCU_SFSPF_4_EZI_Pos                                   6                                                         /*!< SCU SFSPF_4: EZI Position           */
-#define SCU_SFSPF_4_EZI_Msk                                   (0x01UL << SCU_SFSPF_4_EZI_Pos)                           /*!< SCU SFSPF_4: EZI Mask               */
-#define SCU_SFSPF_4_EHD_Pos                                   8                                                         /*!< SCU SFSPF_4: EHD Position           */
-#define SCU_SFSPF_4_EHD_Msk                                   (0x03UL << SCU_SFSPF_4_EHD_Pos)                           /*!< SCU SFSPF_4: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPF_5  ------------------------------------------
-#define SCU_SFSPF_5_MODE_Pos                                  0                                                         /*!< SCU SFSPF_5: MODE Position          */
-#define SCU_SFSPF_5_MODE_Msk                                  (0x07UL << SCU_SFSPF_5_MODE_Pos)                          /*!< SCU SFSPF_5: MODE Mask              */
-#define SCU_SFSPF_5_EPD_Pos                                   3                                                         /*!< SCU SFSPF_5: EPD Position           */
-#define SCU_SFSPF_5_EPD_Msk                                   (0x01UL << SCU_SFSPF_5_EPD_Pos)                           /*!< SCU SFSPF_5: EPD Mask               */
-#define SCU_SFSPF_5_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_5: EPUN Position          */
-#define SCU_SFSPF_5_EPUN_Msk                                  (0x01UL << SCU_SFSPF_5_EPUN_Pos)                          /*!< SCU SFSPF_5: EPUN Mask              */
-#define SCU_SFSPF_5_EHS_Pos                                   5                                                         /*!< SCU SFSPF_5: EHS Position           */
-#define SCU_SFSPF_5_EHS_Msk                                   (0x01UL << SCU_SFSPF_5_EHS_Pos)                           /*!< SCU SFSPF_5: EHS Mask               */
-#define SCU_SFSPF_5_EZI_Pos                                   6                                                         /*!< SCU SFSPF_5: EZI Position           */
-#define SCU_SFSPF_5_EZI_Msk                                   (0x01UL << SCU_SFSPF_5_EZI_Pos)                           /*!< SCU SFSPF_5: EZI Mask               */
-#define SCU_SFSPF_5_EHD_Pos                                   8                                                         /*!< SCU SFSPF_5: EHD Position           */
-#define SCU_SFSPF_5_EHD_Msk                                   (0x03UL << SCU_SFSPF_5_EHD_Pos)                           /*!< SCU SFSPF_5: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPF_6  ------------------------------------------
-#define SCU_SFSPF_6_MODE_Pos                                  0                                                         /*!< SCU SFSPF_6: MODE Position          */
-#define SCU_SFSPF_6_MODE_Msk                                  (0x07UL << SCU_SFSPF_6_MODE_Pos)                          /*!< SCU SFSPF_6: MODE Mask              */
-#define SCU_SFSPF_6_EPD_Pos                                   3                                                         /*!< SCU SFSPF_6: EPD Position           */
-#define SCU_SFSPF_6_EPD_Msk                                   (0x01UL << SCU_SFSPF_6_EPD_Pos)                           /*!< SCU SFSPF_6: EPD Mask               */
-#define SCU_SFSPF_6_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_6: EPUN Position          */
-#define SCU_SFSPF_6_EPUN_Msk                                  (0x01UL << SCU_SFSPF_6_EPUN_Pos)                          /*!< SCU SFSPF_6: EPUN Mask              */
-#define SCU_SFSPF_6_EHS_Pos                                   5                                                         /*!< SCU SFSPF_6: EHS Position           */
-#define SCU_SFSPF_6_EHS_Msk                                   (0x01UL << SCU_SFSPF_6_EHS_Pos)                           /*!< SCU SFSPF_6: EHS Mask               */
-#define SCU_SFSPF_6_EZI_Pos                                   6                                                         /*!< SCU SFSPF_6: EZI Position           */
-#define SCU_SFSPF_6_EZI_Msk                                   (0x01UL << SCU_SFSPF_6_EZI_Pos)                           /*!< SCU SFSPF_6: EZI Mask               */
-#define SCU_SFSPF_6_EHD_Pos                                   8                                                         /*!< SCU SFSPF_6: EHD Position           */
-#define SCU_SFSPF_6_EHD_Msk                                   (0x03UL << SCU_SFSPF_6_EHD_Pos)                           /*!< SCU SFSPF_6: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPF_7  ------------------------------------------
-#define SCU_SFSPF_7_MODE_Pos                                  0                                                         /*!< SCU SFSPF_7: MODE Position          */
-#define SCU_SFSPF_7_MODE_Msk                                  (0x07UL << SCU_SFSPF_7_MODE_Pos)                          /*!< SCU SFSPF_7: MODE Mask              */
-#define SCU_SFSPF_7_EPD_Pos                                   3                                                         /*!< SCU SFSPF_7: EPD Position           */
-#define SCU_SFSPF_7_EPD_Msk                                   (0x01UL << SCU_SFSPF_7_EPD_Pos)                           /*!< SCU SFSPF_7: EPD Mask               */
-#define SCU_SFSPF_7_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_7: EPUN Position          */
-#define SCU_SFSPF_7_EPUN_Msk                                  (0x01UL << SCU_SFSPF_7_EPUN_Pos)                          /*!< SCU SFSPF_7: EPUN Mask              */
-#define SCU_SFSPF_7_EHS_Pos                                   5                                                         /*!< SCU SFSPF_7: EHS Position           */
-#define SCU_SFSPF_7_EHS_Msk                                   (0x01UL << SCU_SFSPF_7_EHS_Pos)                           /*!< SCU SFSPF_7: EHS Mask               */
-#define SCU_SFSPF_7_EZI_Pos                                   6                                                         /*!< SCU SFSPF_7: EZI Position           */
-#define SCU_SFSPF_7_EZI_Msk                                   (0x01UL << SCU_SFSPF_7_EZI_Pos)                           /*!< SCU SFSPF_7: EZI Mask               */
-#define SCU_SFSPF_7_EHD_Pos                                   8                                                         /*!< SCU SFSPF_7: EHD Position           */
-#define SCU_SFSPF_7_EHD_Msk                                   (0x03UL << SCU_SFSPF_7_EHD_Pos)                           /*!< SCU SFSPF_7: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPF_8  ------------------------------------------
-#define SCU_SFSPF_8_MODE_Pos                                  0                                                         /*!< SCU SFSPF_8: MODE Position          */
-#define SCU_SFSPF_8_MODE_Msk                                  (0x07UL << SCU_SFSPF_8_MODE_Pos)                          /*!< SCU SFSPF_8: MODE Mask              */
-#define SCU_SFSPF_8_EPD_Pos                                   3                                                         /*!< SCU SFSPF_8: EPD Position           */
-#define SCU_SFSPF_8_EPD_Msk                                   (0x01UL << SCU_SFSPF_8_EPD_Pos)                           /*!< SCU SFSPF_8: EPD Mask               */
-#define SCU_SFSPF_8_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_8: EPUN Position          */
-#define SCU_SFSPF_8_EPUN_Msk                                  (0x01UL << SCU_SFSPF_8_EPUN_Pos)                          /*!< SCU SFSPF_8: EPUN Mask              */
-#define SCU_SFSPF_8_EHS_Pos                                   5                                                         /*!< SCU SFSPF_8: EHS Position           */
-#define SCU_SFSPF_8_EHS_Msk                                   (0x01UL << SCU_SFSPF_8_EHS_Pos)                           /*!< SCU SFSPF_8: EHS Mask               */
-#define SCU_SFSPF_8_EZI_Pos                                   6                                                         /*!< SCU SFSPF_8: EZI Position           */
-#define SCU_SFSPF_8_EZI_Msk                                   (0x01UL << SCU_SFSPF_8_EZI_Pos)                           /*!< SCU SFSPF_8: EZI Mask               */
-#define SCU_SFSPF_8_EHD_Pos                                   8                                                         /*!< SCU SFSPF_8: EHD Position           */
-#define SCU_SFSPF_8_EHD_Msk                                   (0x03UL << SCU_SFSPF_8_EHD_Pos)                           /*!< SCU SFSPF_8: EHD Mask               */
-
-// ---------------------------------------  SCU_SFSPF_9  ------------------------------------------
-#define SCU_SFSPF_9_MODE_Pos                                  0                                                         /*!< SCU SFSPF_9: MODE Position          */
-#define SCU_SFSPF_9_MODE_Msk                                  (0x07UL << SCU_SFSPF_9_MODE_Pos)                          /*!< SCU SFSPF_9: MODE Mask              */
-#define SCU_SFSPF_9_EPD_Pos                                   3                                                         /*!< SCU SFSPF_9: EPD Position           */
-#define SCU_SFSPF_9_EPD_Msk                                   (0x01UL << SCU_SFSPF_9_EPD_Pos)                           /*!< SCU SFSPF_9: EPD Mask               */
-#define SCU_SFSPF_9_EPUN_Pos                                  4                                                         /*!< SCU SFSPF_9: EPUN Position          */
-#define SCU_SFSPF_9_EPUN_Msk                                  (0x01UL << SCU_SFSPF_9_EPUN_Pos)                          /*!< SCU SFSPF_9: EPUN Mask              */
-#define SCU_SFSPF_9_EHS_Pos                                   5                                                         /*!< SCU SFSPF_9: EHS Position           */
-#define SCU_SFSPF_9_EHS_Msk                                   (0x01UL << SCU_SFSPF_9_EHS_Pos)                           /*!< SCU SFSPF_9: EHS Mask               */
-#define SCU_SFSPF_9_EZI_Pos                                   6                                                         /*!< SCU SFSPF_9: EZI Position           */
-#define SCU_SFSPF_9_EZI_Msk                                   (0x01UL << SCU_SFSPF_9_EZI_Pos)                           /*!< SCU SFSPF_9: EZI Mask               */
-#define SCU_SFSPF_9_EHD_Pos                                   8                                                         /*!< SCU SFSPF_9: EHD Position           */
-#define SCU_SFSPF_9_EHD_Msk                                   (0x03UL << SCU_SFSPF_9_EHD_Pos)                           /*!< SCU SFSPF_9: EHD Mask               */
-
-// --------------------------------------  SCU_SFSPF_10  ------------------------------------------
-#define SCU_SFSPF_10_MODE_Pos                                 0                                                         /*!< SCU SFSPF_10: MODE Position         */
-#define SCU_SFSPF_10_MODE_Msk                                 (0x07UL << SCU_SFSPF_10_MODE_Pos)                         /*!< SCU SFSPF_10: MODE Mask             */
-#define SCU_SFSPF_10_EPD_Pos                                  3                                                         /*!< SCU SFSPF_10: EPD Position          */
-#define SCU_SFSPF_10_EPD_Msk                                  (0x01UL << SCU_SFSPF_10_EPD_Pos)                          /*!< SCU SFSPF_10: EPD Mask              */
-#define SCU_SFSPF_10_EPUN_Pos                                 4                                                         /*!< SCU SFSPF_10: EPUN Position         */
-#define SCU_SFSPF_10_EPUN_Msk                                 (0x01UL << SCU_SFSPF_10_EPUN_Pos)                         /*!< SCU SFSPF_10: EPUN Mask             */
-#define SCU_SFSPF_10_EHS_Pos                                  5                                                         /*!< SCU SFSPF_10: EHS Position          */
-#define SCU_SFSPF_10_EHS_Msk                                  (0x01UL << SCU_SFSPF_10_EHS_Pos)                          /*!< SCU SFSPF_10: EHS Mask              */
-#define SCU_SFSPF_10_EZI_Pos                                  6                                                         /*!< SCU SFSPF_10: EZI Position          */
-#define SCU_SFSPF_10_EZI_Msk                                  (0x01UL << SCU_SFSPF_10_EZI_Pos)                          /*!< SCU SFSPF_10: EZI Mask              */
-#define SCU_SFSPF_10_EHD_Pos                                  8                                                         /*!< SCU SFSPF_10: EHD Position          */
-#define SCU_SFSPF_10_EHD_Msk                                  (0x03UL << SCU_SFSPF_10_EHD_Pos)                          /*!< SCU SFSPF_10: EHD Mask              */
-
-// --------------------------------------  SCU_SFSPF_11  ------------------------------------------
-#define SCU_SFSPF_11_MODE_Pos                                 0                                                         /*!< SCU SFSPF_11: MODE Position         */
-#define SCU_SFSPF_11_MODE_Msk                                 (0x07UL << SCU_SFSPF_11_MODE_Pos)                         /*!< SCU SFSPF_11: MODE Mask             */
-#define SCU_SFSPF_11_EPD_Pos                                  3                                                         /*!< SCU SFSPF_11: EPD Position          */
-#define SCU_SFSPF_11_EPD_Msk                                  (0x01UL << SCU_SFSPF_11_EPD_Pos)                          /*!< SCU SFSPF_11: EPD Mask              */
-#define SCU_SFSPF_11_EPUN_Pos                                 4                                                         /*!< SCU SFSPF_11: EPUN Position         */
-#define SCU_SFSPF_11_EPUN_Msk                                 (0x01UL << SCU_SFSPF_11_EPUN_Pos)                         /*!< SCU SFSPF_11: EPUN Mask             */
-#define SCU_SFSPF_11_EHS_Pos                                  5                                                         /*!< SCU SFSPF_11: EHS Position          */
-#define SCU_SFSPF_11_EHS_Msk                                  (0x01UL << SCU_SFSPF_11_EHS_Pos)                          /*!< SCU SFSPF_11: EHS Mask              */
-#define SCU_SFSPF_11_EZI_Pos                                  6                                                         /*!< SCU SFSPF_11: EZI Position          */
-#define SCU_SFSPF_11_EZI_Msk                                  (0x01UL << SCU_SFSPF_11_EZI_Pos)                          /*!< SCU SFSPF_11: EZI Mask              */
-#define SCU_SFSPF_11_EHD_Pos                                  8                                                         /*!< SCU SFSPF_11: EHD Position          */
-#define SCU_SFSPF_11_EHD_Msk                                  (0x03UL << SCU_SFSPF_11_EHD_Pos)                          /*!< SCU SFSPF_11: EHD Mask              */
-
-// --------------------------------------  SCU_SFSCLK_0  ------------------------------------------
-#define SCU_SFSCLK_0_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_0: MODE Position         */
-#define SCU_SFSCLK_0_MODE_Msk                                 (0x07UL << SCU_SFSCLK_0_MODE_Pos)                         /*!< SCU SFSCLK_0: MODE Mask             */
-#define SCU_SFSCLK_0_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_0: EPD Position          */
-#define SCU_SFSCLK_0_EPD_Msk                                  (0x01UL << SCU_SFSCLK_0_EPD_Pos)                          /*!< SCU SFSCLK_0: EPD Mask              */
-#define SCU_SFSCLK_0_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_0: EPUN Position         */
-#define SCU_SFSCLK_0_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_0_EPUN_Pos)                         /*!< SCU SFSCLK_0: EPUN Mask             */
-#define SCU_SFSCLK_0_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_0: EHS Position          */
-#define SCU_SFSCLK_0_EHS_Msk                                  (0x01UL << SCU_SFSCLK_0_EHS_Pos)                          /*!< SCU SFSCLK_0: EHS Mask              */
-#define SCU_SFSCLK_0_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_0: EZI Position          */
-#define SCU_SFSCLK_0_EZI_Msk                                  (0x01UL << SCU_SFSCLK_0_EZI_Pos)                          /*!< SCU SFSCLK_0: EZI Mask              */
-#define SCU_SFSCLK_0_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_0: EHD Position          */
-#define SCU_SFSCLK_0_EHD_Msk                                  (0x03UL << SCU_SFSCLK_0_EHD_Pos)                          /*!< SCU SFSCLK_0: EHD Mask              */
-
-// --------------------------------------  SCU_SFSCLK_1  ------------------------------------------
-#define SCU_SFSCLK_1_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_1: MODE Position         */
-#define SCU_SFSCLK_1_MODE_Msk                                 (0x07UL << SCU_SFSCLK_1_MODE_Pos)                         /*!< SCU SFSCLK_1: MODE Mask             */
-#define SCU_SFSCLK_1_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_1: EPD Position          */
-#define SCU_SFSCLK_1_EPD_Msk                                  (0x01UL << SCU_SFSCLK_1_EPD_Pos)                          /*!< SCU SFSCLK_1: EPD Mask              */
-#define SCU_SFSCLK_1_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_1: EPUN Position         */
-#define SCU_SFSCLK_1_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_1_EPUN_Pos)                         /*!< SCU SFSCLK_1: EPUN Mask             */
-#define SCU_SFSCLK_1_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_1: EHS Position          */
-#define SCU_SFSCLK_1_EHS_Msk                                  (0x01UL << SCU_SFSCLK_1_EHS_Pos)                          /*!< SCU SFSCLK_1: EHS Mask              */
-#define SCU_SFSCLK_1_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_1: EZI Position          */
-#define SCU_SFSCLK_1_EZI_Msk                                  (0x01UL << SCU_SFSCLK_1_EZI_Pos)                          /*!< SCU SFSCLK_1: EZI Mask              */
-#define SCU_SFSCLK_1_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_1: EHD Position          */
-#define SCU_SFSCLK_1_EHD_Msk                                  (0x03UL << SCU_SFSCLK_1_EHD_Pos)                          /*!< SCU SFSCLK_1: EHD Mask              */
-
-// --------------------------------------  SCU_SFSCLK_2  ------------------------------------------
-#define SCU_SFSCLK_2_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_2: MODE Position         */
-#define SCU_SFSCLK_2_MODE_Msk                                 (0x07UL << SCU_SFSCLK_2_MODE_Pos)                         /*!< SCU SFSCLK_2: MODE Mask             */
-#define SCU_SFSCLK_2_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_2: EPD Position          */
-#define SCU_SFSCLK_2_EPD_Msk                                  (0x01UL << SCU_SFSCLK_2_EPD_Pos)                          /*!< SCU SFSCLK_2: EPD Mask              */
-#define SCU_SFSCLK_2_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_2: EPUN Position         */
-#define SCU_SFSCLK_2_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_2_EPUN_Pos)                         /*!< SCU SFSCLK_2: EPUN Mask             */
-#define SCU_SFSCLK_2_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_2: EHS Position          */
-#define SCU_SFSCLK_2_EHS_Msk                                  (0x01UL << SCU_SFSCLK_2_EHS_Pos)                          /*!< SCU SFSCLK_2: EHS Mask              */
-#define SCU_SFSCLK_2_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_2: EZI Position          */
-#define SCU_SFSCLK_2_EZI_Msk                                  (0x01UL << SCU_SFSCLK_2_EZI_Pos)                          /*!< SCU SFSCLK_2: EZI Mask              */
-#define SCU_SFSCLK_2_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_2: EHD Position          */
-#define SCU_SFSCLK_2_EHD_Msk                                  (0x03UL << SCU_SFSCLK_2_EHD_Pos)                          /*!< SCU SFSCLK_2: EHD Mask              */
-
-// --------------------------------------  SCU_SFSCLK_3  ------------------------------------------
-#define SCU_SFSCLK_3_MODE_Pos                                 0                                                         /*!< SCU SFSCLK_3: MODE Position         */
-#define SCU_SFSCLK_3_MODE_Msk                                 (0x07UL << SCU_SFSCLK_3_MODE_Pos)                         /*!< SCU SFSCLK_3: MODE Mask             */
-#define SCU_SFSCLK_3_EPD_Pos                                  3                                                         /*!< SCU SFSCLK_3: EPD Position          */
-#define SCU_SFSCLK_3_EPD_Msk                                  (0x01UL << SCU_SFSCLK_3_EPD_Pos)                          /*!< SCU SFSCLK_3: EPD Mask              */
-#define SCU_SFSCLK_3_EPUN_Pos                                 4                                                         /*!< SCU SFSCLK_3: EPUN Position         */
-#define SCU_SFSCLK_3_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_3_EPUN_Pos)                         /*!< SCU SFSCLK_3: EPUN Mask             */
-#define SCU_SFSCLK_3_EHS_Pos                                  5                                                         /*!< SCU SFSCLK_3: EHS Position          */
-#define SCU_SFSCLK_3_EHS_Msk                                  (0x01UL << SCU_SFSCLK_3_EHS_Pos)                          /*!< SCU SFSCLK_3: EHS Mask              */
-#define SCU_SFSCLK_3_EZI_Pos                                  6                                                         /*!< SCU SFSCLK_3: EZI Position          */
-#define SCU_SFSCLK_3_EZI_Msk                                  (0x01UL << SCU_SFSCLK_3_EZI_Pos)                          /*!< SCU SFSCLK_3: EZI Mask              */
-#define SCU_SFSCLK_3_EHD_Pos                                  8                                                         /*!< SCU SFSCLK_3: EHD Position          */
-#define SCU_SFSCLK_3_EHD_Msk                                  (0x03UL << SCU_SFSCLK_3_EHD_Pos)                          /*!< SCU SFSCLK_3: EHD Mask              */
-
-// ---------------------------------------  SCU_SFSUSB  -------------------------------------------
-#define SCU_SFSUSB_USB_AIM_Pos                                0                                                         /*!< SCU SFSUSB: USB_AIM Position        */
-#define SCU_SFSUSB_USB_AIM_Msk                                (0x01UL << SCU_SFSUSB_USB_AIM_Pos)                        /*!< SCU SFSUSB: USB_AIM Mask            */
-#define SCU_SFSUSB_USB_ESEA_Pos                               1                                                         /*!< SCU SFSUSB: USB_ESEA Position       */
-#define SCU_SFSUSB_USB_ESEA_Msk                               (0x01UL << SCU_SFSUSB_USB_ESEA_Pos)                       /*!< SCU SFSUSB: USB_ESEA Mask           */
-
-// ---------------------------------------  SCU_SFSI2C0  ------------------------------------------
-#define SCU_SFSI2C0_SDA_EHS_Pos                               0                                                         /*!< SCU SFSI2C0: SDA_EHS Position       */
-#define SCU_SFSI2C0_SDA_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos)                       /*!< SCU SFSI2C0: SDA_EHS Mask           */
-#define SCU_SFSI2C0_SCL_EHS_Pos                               1                                                         /*!< SCU SFSI2C0: SCL_EHS Position       */
-#define SCU_SFSI2C0_SCL_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos)                       /*!< SCU SFSI2C0: SCL_EHS Mask           */
-#define SCU_SFSI2C0_SCL_ECS_Pos                               2                                                         /*!< SCU SFSI2C0: SCL_ECS Position       */
-#define SCU_SFSI2C0_SCL_ECS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos)                       /*!< SCU SFSI2C0: SCL_ECS Mask           */
-
-// ---------------------------------------  SCU_ENAIO0  -------------------------------------------
-#define SCU_ENAIO0_ADC0_0_Pos                                 0                                                         /*!< SCU ENAIO0: ADC0_0 Position         */
-#define SCU_ENAIO0_ADC0_0_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_0_Pos)                         /*!< SCU ENAIO0: ADC0_0 Mask             */
-#define SCU_ENAIO0_ADC0_1_Pos                                 1                                                         /*!< SCU ENAIO0: ADC0_1 Position         */
-#define SCU_ENAIO0_ADC0_1_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_1_Pos)                         /*!< SCU ENAIO0: ADC0_1 Mask             */
-#define SCU_ENAIO0_ADC0_2_Pos                                 2                                                         /*!< SCU ENAIO0: ADC0_2 Position         */
-#define SCU_ENAIO0_ADC0_2_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_2_Pos)                         /*!< SCU ENAIO0: ADC0_2 Mask             */
-#define SCU_ENAIO0_ADC0_3_Pos                                 3                                                         /*!< SCU ENAIO0: ADC0_3 Position         */
-#define SCU_ENAIO0_ADC0_3_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_3_Pos)                         /*!< SCU ENAIO0: ADC0_3 Mask             */
-#define SCU_ENAIO0_ADC0_4_Pos                                 4                                                         /*!< SCU ENAIO0: ADC0_4 Position         */
-#define SCU_ENAIO0_ADC0_4_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_4_Pos)                         /*!< SCU ENAIO0: ADC0_4 Mask             */
-#define SCU_ENAIO0_ADC0_5_Pos                                 5                                                         /*!< SCU ENAIO0: ADC0_5 Position         */
-#define SCU_ENAIO0_ADC0_5_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_5_Pos)                         /*!< SCU ENAIO0: ADC0_5 Mask             */
-#define SCU_ENAIO0_ADC0_6_Pos                                 6                                                         /*!< SCU ENAIO0: ADC0_6 Position         */
-#define SCU_ENAIO0_ADC0_6_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_6_Pos)                         /*!< SCU ENAIO0: ADC0_6 Mask             */
-
-// ---------------------------------------  SCU_ENAIO1  -------------------------------------------
-#define SCU_ENAIO1_ADC1_0_Pos                                 0                                                         /*!< SCU ENAIO1: ADC1_0 Position         */
-#define SCU_ENAIO1_ADC1_0_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_0_Pos)                         /*!< SCU ENAIO1: ADC1_0 Mask             */
-#define SCU_ENAIO1_ADC1_1_Pos                                 1                                                         /*!< SCU ENAIO1: ADC1_1 Position         */
-#define SCU_ENAIO1_ADC1_1_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_1_Pos)                         /*!< SCU ENAIO1: ADC1_1 Mask             */
-#define SCU_ENAIO1_ADC1_2_Pos                                 2                                                         /*!< SCU ENAIO1: ADC1_2 Position         */
-#define SCU_ENAIO1_ADC1_2_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_2_Pos)                         /*!< SCU ENAIO1: ADC1_2 Mask             */
-#define SCU_ENAIO1_ADC1_3_Pos                                 3                                                         /*!< SCU ENAIO1: ADC1_3 Position         */
-#define SCU_ENAIO1_ADC1_3_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_3_Pos)                         /*!< SCU ENAIO1: ADC1_3 Mask             */
-#define SCU_ENAIO1_ADC1_4_Pos                                 4                                                         /*!< SCU ENAIO1: ADC1_4 Position         */
-#define SCU_ENAIO1_ADC1_4_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_4_Pos)                         /*!< SCU ENAIO1: ADC1_4 Mask             */
-#define SCU_ENAIO1_ADC1_5_Pos                                 5                                                         /*!< SCU ENAIO1: ADC1_5 Position         */
-#define SCU_ENAIO1_ADC1_5_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_5_Pos)                         /*!< SCU ENAIO1: ADC1_5 Mask             */
-#define SCU_ENAIO1_ADC1_6_Pos                                 6                                                         /*!< SCU ENAIO1: ADC1_6 Position         */
-#define SCU_ENAIO1_ADC1_6_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_6_Pos)                         /*!< SCU ENAIO1: ADC1_6 Mask             */
-#define SCU_ENAIO1_ADC1_7_Pos                                 7                                                         /*!< SCU ENAIO1: ADC1_7 Position         */
-#define SCU_ENAIO1_ADC1_7_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_7_Pos)                         /*!< SCU ENAIO1: ADC1_7 Mask             */
-
-// ---------------------------------------  SCU_ENAIO2  -------------------------------------------
-#define SCU_ENAIO2_DAC_Pos                                    0                                                         /*!< SCU ENAIO2: DAC Position            */
-#define SCU_ENAIO2_DAC_Msk                                    (0x01UL << SCU_ENAIO2_DAC_Pos)                            /*!< SCU ENAIO2: DAC Mask                */
-#define SCU_ENAIO2_BG_Pos                                     4                                                         /*!< SCU ENAIO2: BG Position             */
-#define SCU_ENAIO2_BG_Msk                                     (0x01UL << SCU_ENAIO2_BG_Pos)                             /*!< SCU ENAIO2: BG Mask                 */
-
-// -------------------------------------  SCU_EMCDELAYCLK  ----------------------------------------
-#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos                        0                                                         /*!< SCU EMCDELAYCLK: CLK0_DELAY Position */
-#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK0_DELAY Mask    */
-#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos                        4                                                         /*!< SCU EMCDELAYCLK: CLK1_DELAY Position */
-#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK1_DELAY Mask    */
-#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos                        8                                                         /*!< SCU EMCDELAYCLK: CLK2_DELAY Position */
-#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK2_DELAY Mask    */
-#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos                        12                                                        /*!< SCU EMCDELAYCLK: CLK3_DELAY Position */
-#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CLK3_DELAY Mask    */
-#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos                        16                                                        /*!< SCU EMCDELAYCLK: CKE0_DELAY Position */
-#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE0_DELAY Mask    */
-#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos                        20                                                        /*!< SCU EMCDELAYCLK: CKE1_DELAY Position */
-#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE1_DELAY Mask    */
-#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos                        24                                                        /*!< SCU EMCDELAYCLK: CKE2_DELAY Position */
-#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE2_DELAY Mask    */
-#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos                        28                                                        /*!< SCU EMCDELAYCLK: CKE3_DELAY Position */
-#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos)                /*!< SCU EMCDELAYCLK: CKE3_DELAY Mask    */
-
-// --------------------------------------  SCU_PINTSEL0  ------------------------------------------
-#define SCU_PINTSEL0_INTPIN0_Pos                              0                                                         /*!< SCU PINTSEL0: INTPIN0 Position      */
-#define SCU_PINTSEL0_INTPIN0_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos)                      /*!< SCU PINTSEL0: INTPIN0 Mask          */
-#define SCU_PINTSEL0_PORTSEL0_Pos                             5                                                         /*!< SCU PINTSEL0: PORTSEL0 Position     */
-#define SCU_PINTSEL0_PORTSEL0_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos)                     /*!< SCU PINTSEL0: PORTSEL0 Mask         */
-#define SCU_PINTSEL0_INTPIN1_Pos                              8                                                         /*!< SCU PINTSEL0: INTPIN1 Position      */
-#define SCU_PINTSEL0_INTPIN1_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos)                      /*!< SCU PINTSEL0: INTPIN1 Mask          */
-#define SCU_PINTSEL0_PORTSEL1_Pos                             13                                                        /*!< SCU PINTSEL0: PORTSEL1 Position     */
-#define SCU_PINTSEL0_PORTSEL1_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos)                     /*!< SCU PINTSEL0: PORTSEL1 Mask         */
-#define SCU_PINTSEL0_INTPIN2_Pos                              16                                                        /*!< SCU PINTSEL0: INTPIN2 Position      */
-#define SCU_PINTSEL0_INTPIN2_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos)                      /*!< SCU PINTSEL0: INTPIN2 Mask          */
-#define SCU_PINTSEL0_PORTSEL2_Pos                             21                                                        /*!< SCU PINTSEL0: PORTSEL2 Position     */
-#define SCU_PINTSEL0_PORTSEL2_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos)                     /*!< SCU PINTSEL0: PORTSEL2 Mask         */
-#define SCU_PINTSEL0_INTPIN3_Pos                              24                                                        /*!< SCU PINTSEL0: INTPIN3 Position      */
-#define SCU_PINTSEL0_INTPIN3_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos)                      /*!< SCU PINTSEL0: INTPIN3 Mask          */
-#define SCU_PINTSEL0_PORTSEL3_Pos                             29                                                        /*!< SCU PINTSEL0: PORTSEL3 Position     */
-#define SCU_PINTSEL0_PORTSEL3_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos)                     /*!< SCU PINTSEL0: PORTSEL3 Mask         */
-
-// --------------------------------------  SCU_PINTSEL1  ------------------------------------------
-#define SCU_PINTSEL1_INTPIN4_Pos                              0                                                         /*!< SCU PINTSEL1: INTPIN4 Position      */
-#define SCU_PINTSEL1_INTPIN4_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos)                      /*!< SCU PINTSEL1: INTPIN4 Mask          */
-#define SCU_PINTSEL1_PORTSEL4_Pos                             5                                                         /*!< SCU PINTSEL1: PORTSEL4 Position     */
-#define SCU_PINTSEL1_PORTSEL4_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos)                     /*!< SCU PINTSEL1: PORTSEL4 Mask         */
-#define SCU_PINTSEL1_INTPIN5_Pos                              8                                                         /*!< SCU PINTSEL1: INTPIN5 Position      */
-#define SCU_PINTSEL1_INTPIN5_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos)                      /*!< SCU PINTSEL1: INTPIN5 Mask          */
-#define SCU_PINTSEL1_PORTSEL5_Pos                             13                                                        /*!< SCU PINTSEL1: PORTSEL5 Position     */
-#define SCU_PINTSEL1_PORTSEL5_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos)                     /*!< SCU PINTSEL1: PORTSEL5 Mask         */
-#define SCU_PINTSEL1_INTPIN6_Pos                              16                                                        /*!< SCU PINTSEL1: INTPIN6 Position      */
-#define SCU_PINTSEL1_INTPIN6_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos)                      /*!< SCU PINTSEL1: INTPIN6 Mask          */
-#define SCU_PINTSEL1_PORTSEL6_Pos                             21                                                        /*!< SCU PINTSEL1: PORTSEL6 Position     */
-#define SCU_PINTSEL1_PORTSEL6_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos)                     /*!< SCU PINTSEL1: PORTSEL6 Mask         */
-#define SCU_PINTSEL1_INTPIN7_Pos                              24                                                        /*!< SCU PINTSEL1: INTPIN7 Position      */
-#define SCU_PINTSEL1_INTPIN7_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos)                      /*!< SCU PINTSEL1: INTPIN7 Mask          */
-#define SCU_PINTSEL1_PORTSEL7_Pos                             29                                                        /*!< SCU PINTSEL1: PORTSEL7 Position     */
-#define SCU_PINTSEL1_PORTSEL7_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos)                     /*!< SCU PINTSEL1: PORTSEL7 Mask         */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                             GPIO_PIN_INT Position & Mask                             -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ------------------------------------  GPIO_PIN_INT_ISEL  ---------------------------------------
-#define GPIO_PIN_INT_ISEL_PMODE0_Pos                          0                                                         /*!< GPIO_PIN_INT ISEL: PMODE0 Position  */
-#define GPIO_PIN_INT_ISEL_PMODE0_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE0 Mask      */
-#define GPIO_PIN_INT_ISEL_PMODE1_Pos                          1                                                         /*!< GPIO_PIN_INT ISEL: PMODE1 Position  */
-#define GPIO_PIN_INT_ISEL_PMODE1_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE1 Mask      */
-#define GPIO_PIN_INT_ISEL_PMODE2_Pos                          2                                                         /*!< GPIO_PIN_INT ISEL: PMODE2 Position  */
-#define GPIO_PIN_INT_ISEL_PMODE2_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE2 Mask      */
-#define GPIO_PIN_INT_ISEL_PMODE3_Pos                          3                                                         /*!< GPIO_PIN_INT ISEL: PMODE3 Position  */
-#define GPIO_PIN_INT_ISEL_PMODE3_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE3 Mask      */
-#define GPIO_PIN_INT_ISEL_PMODE4_Pos                          4                                                         /*!< GPIO_PIN_INT ISEL: PMODE4 Position  */
-#define GPIO_PIN_INT_ISEL_PMODE4_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE4 Mask      */
-#define GPIO_PIN_INT_ISEL_PMODE5_Pos                          5                                                         /*!< GPIO_PIN_INT ISEL: PMODE5 Position  */
-#define GPIO_PIN_INT_ISEL_PMODE5_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE5 Mask      */
-#define GPIO_PIN_INT_ISEL_PMODE6_Pos                          6                                                         /*!< GPIO_PIN_INT ISEL: PMODE6 Position  */
-#define GPIO_PIN_INT_ISEL_PMODE6_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE6 Mask      */
-#define GPIO_PIN_INT_ISEL_PMODE7_Pos                          7                                                         /*!< GPIO_PIN_INT ISEL: PMODE7 Position  */
-#define GPIO_PIN_INT_ISEL_PMODE7_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos)                  /*!< GPIO_PIN_INT ISEL: PMODE7 Mask      */
-
-// ------------------------------------  GPIO_PIN_INT_IENR  ---------------------------------------
-#define GPIO_PIN_INT_IENR_ENRL0_Pos                           0                                                         /*!< GPIO_PIN_INT IENR: ENRL0 Position   */
-#define GPIO_PIN_INT_IENR_ENRL0_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL0 Mask       */
-#define GPIO_PIN_INT_IENR_ENRL1_Pos                           1                                                         /*!< GPIO_PIN_INT IENR: ENRL1 Position   */
-#define GPIO_PIN_INT_IENR_ENRL1_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL1 Mask       */
-#define GPIO_PIN_INT_IENR_ENRL2_Pos                           2                                                         /*!< GPIO_PIN_INT IENR: ENRL2 Position   */
-#define GPIO_PIN_INT_IENR_ENRL2_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL2 Mask       */
-#define GPIO_PIN_INT_IENR_ENRL3_Pos                           3                                                         /*!< GPIO_PIN_INT IENR: ENRL3 Position   */
-#define GPIO_PIN_INT_IENR_ENRL3_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL3 Mask       */
-#define GPIO_PIN_INT_IENR_ENRL4_Pos                           4                                                         /*!< GPIO_PIN_INT IENR: ENRL4 Position   */
-#define GPIO_PIN_INT_IENR_ENRL4_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL4 Mask       */
-#define GPIO_PIN_INT_IENR_ENRL5_Pos                           5                                                         /*!< GPIO_PIN_INT IENR: ENRL5 Position   */
-#define GPIO_PIN_INT_IENR_ENRL5_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL5 Mask       */
-#define GPIO_PIN_INT_IENR_ENRL6_Pos                           6                                                         /*!< GPIO_PIN_INT IENR: ENRL6 Position   */
-#define GPIO_PIN_INT_IENR_ENRL6_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL6 Mask       */
-#define GPIO_PIN_INT_IENR_ENRL7_Pos                           7                                                         /*!< GPIO_PIN_INT IENR: ENRL7 Position   */
-#define GPIO_PIN_INT_IENR_ENRL7_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos)                   /*!< GPIO_PIN_INT IENR: ENRL7 Mask       */
-
-// -----------------------------------  GPIO_PIN_INT_SIENR  ---------------------------------------
-#define GPIO_PIN_INT_SIENR_SETENRL0_Pos                       0                                                         /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */
-#define GPIO_PIN_INT_SIENR_SETENRL0_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask   */
-#define GPIO_PIN_INT_SIENR_SETENRL1_Pos                       1                                                         /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */
-#define GPIO_PIN_INT_SIENR_SETENRL1_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask   */
-#define GPIO_PIN_INT_SIENR_SETENRL2_Pos                       2                                                         /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */
-#define GPIO_PIN_INT_SIENR_SETENRL2_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask   */
-#define GPIO_PIN_INT_SIENR_SETENRL3_Pos                       3                                                         /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */
-#define GPIO_PIN_INT_SIENR_SETENRL3_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask   */
-#define GPIO_PIN_INT_SIENR_SETENRL4_Pos                       4                                                         /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */
-#define GPIO_PIN_INT_SIENR_SETENRL4_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask   */
-#define GPIO_PIN_INT_SIENR_SETENRL5_Pos                       5                                                         /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */
-#define GPIO_PIN_INT_SIENR_SETENRL5_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask   */
-#define GPIO_PIN_INT_SIENR_SETENRL6_Pos                       6                                                         /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */
-#define GPIO_PIN_INT_SIENR_SETENRL6_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask   */
-#define GPIO_PIN_INT_SIENR_SETENRL7_Pos                       7                                                         /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */
-#define GPIO_PIN_INT_SIENR_SETENRL7_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos)               /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask   */
-
-// -----------------------------------  GPIO_PIN_INT_CIENR  ---------------------------------------
-#define GPIO_PIN_INT_CIENR_CENRL0_Pos                         0                                                         /*!< GPIO_PIN_INT CIENR: CENRL0 Position */
-#define GPIO_PIN_INT_CIENR_CENRL0_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL0 Mask     */
-#define GPIO_PIN_INT_CIENR_CENRL1_Pos                         1                                                         /*!< GPIO_PIN_INT CIENR: CENRL1 Position */
-#define GPIO_PIN_INT_CIENR_CENRL1_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL1 Mask     */
-#define GPIO_PIN_INT_CIENR_CENRL2_Pos                         2                                                         /*!< GPIO_PIN_INT CIENR: CENRL2 Position */
-#define GPIO_PIN_INT_CIENR_CENRL2_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL2 Mask     */
-#define GPIO_PIN_INT_CIENR_CENRL3_Pos                         3                                                         /*!< GPIO_PIN_INT CIENR: CENRL3 Position */
-#define GPIO_PIN_INT_CIENR_CENRL3_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL3 Mask     */
-#define GPIO_PIN_INT_CIENR_CENRL4_Pos                         4                                                         /*!< GPIO_PIN_INT CIENR: CENRL4 Position */
-#define GPIO_PIN_INT_CIENR_CENRL4_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL4 Mask     */
-#define GPIO_PIN_INT_CIENR_CENRL5_Pos                         5                                                         /*!< GPIO_PIN_INT CIENR: CENRL5 Position */
-#define GPIO_PIN_INT_CIENR_CENRL5_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL5 Mask     */
-#define GPIO_PIN_INT_CIENR_CENRL6_Pos                         6                                                         /*!< GPIO_PIN_INT CIENR: CENRL6 Position */
-#define GPIO_PIN_INT_CIENR_CENRL6_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL6 Mask     */
-#define GPIO_PIN_INT_CIENR_CENRL7_Pos                         7                                                         /*!< GPIO_PIN_INT CIENR: CENRL7 Position */
-#define GPIO_PIN_INT_CIENR_CENRL7_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos)                 /*!< GPIO_PIN_INT CIENR: CENRL7 Mask     */
-
-// ------------------------------------  GPIO_PIN_INT_IENF  ---------------------------------------
-#define GPIO_PIN_INT_IENF_ENAF0_Pos                           0                                                         /*!< GPIO_PIN_INT IENF: ENAF0 Position   */
-#define GPIO_PIN_INT_IENF_ENAF0_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF0 Mask       */
-#define GPIO_PIN_INT_IENF_ENAF1_Pos                           1                                                         /*!< GPIO_PIN_INT IENF: ENAF1 Position   */
-#define GPIO_PIN_INT_IENF_ENAF1_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF1 Mask       */
-#define GPIO_PIN_INT_IENF_ENAF2_Pos                           2                                                         /*!< GPIO_PIN_INT IENF: ENAF2 Position   */
-#define GPIO_PIN_INT_IENF_ENAF2_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF2 Mask       */
-#define GPIO_PIN_INT_IENF_ENAF3_Pos                           3                                                         /*!< GPIO_PIN_INT IENF: ENAF3 Position   */
-#define GPIO_PIN_INT_IENF_ENAF3_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF3 Mask       */
-#define GPIO_PIN_INT_IENF_ENAF4_Pos                           4                                                         /*!< GPIO_PIN_INT IENF: ENAF4 Position   */
-#define GPIO_PIN_INT_IENF_ENAF4_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF4 Mask       */
-#define GPIO_PIN_INT_IENF_ENAF5_Pos                           5                                                         /*!< GPIO_PIN_INT IENF: ENAF5 Position   */
-#define GPIO_PIN_INT_IENF_ENAF5_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF5 Mask       */
-#define GPIO_PIN_INT_IENF_ENAF6_Pos                           6                                                         /*!< GPIO_PIN_INT IENF: ENAF6 Position   */
-#define GPIO_PIN_INT_IENF_ENAF6_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF6 Mask       */
-#define GPIO_PIN_INT_IENF_ENAF7_Pos                           7                                                         /*!< GPIO_PIN_INT IENF: ENAF7 Position   */
-#define GPIO_PIN_INT_IENF_ENAF7_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos)                   /*!< GPIO_PIN_INT IENF: ENAF7 Mask       */
-
-// -----------------------------------  GPIO_PIN_INT_SIENF  ---------------------------------------
-#define GPIO_PIN_INT_SIENF_SETENAF0_Pos                       0                                                         /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */
-#define GPIO_PIN_INT_SIENF_SETENAF0_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask   */
-#define GPIO_PIN_INT_SIENF_SETENAF1_Pos                       1                                                         /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */
-#define GPIO_PIN_INT_SIENF_SETENAF1_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask   */
-#define GPIO_PIN_INT_SIENF_SETENAF2_Pos                       2                                                         /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */
-#define GPIO_PIN_INT_SIENF_SETENAF2_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask   */
-#define GPIO_PIN_INT_SIENF_SETENAF3_Pos                       3                                                         /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */
-#define GPIO_PIN_INT_SIENF_SETENAF3_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask   */
-#define GPIO_PIN_INT_SIENF_SETENAF4_Pos                       4                                                         /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */
-#define GPIO_PIN_INT_SIENF_SETENAF4_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask   */
-#define GPIO_PIN_INT_SIENF_SETENAF5_Pos                       5                                                         /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */
-#define GPIO_PIN_INT_SIENF_SETENAF5_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask   */
-#define GPIO_PIN_INT_SIENF_SETENAF6_Pos                       6                                                         /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */
-#define GPIO_PIN_INT_SIENF_SETENAF6_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask   */
-#define GPIO_PIN_INT_SIENF_SETENAF7_Pos                       7                                                         /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */
-#define GPIO_PIN_INT_SIENF_SETENAF7_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos)               /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask   */
-
-// -----------------------------------  GPIO_PIN_INT_CIENF  ---------------------------------------
-#define GPIO_PIN_INT_CIENF_CENAF0_Pos                         0                                                         /*!< GPIO_PIN_INT CIENF: CENAF0 Position */
-#define GPIO_PIN_INT_CIENF_CENAF0_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF0 Mask     */
-#define GPIO_PIN_INT_CIENF_CENAF1_Pos                         1                                                         /*!< GPIO_PIN_INT CIENF: CENAF1 Position */
-#define GPIO_PIN_INT_CIENF_CENAF1_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF1 Mask     */
-#define GPIO_PIN_INT_CIENF_CENAF2_Pos                         2                                                         /*!< GPIO_PIN_INT CIENF: CENAF2 Position */
-#define GPIO_PIN_INT_CIENF_CENAF2_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF2 Mask     */
-#define GPIO_PIN_INT_CIENF_CENAF3_Pos                         3                                                         /*!< GPIO_PIN_INT CIENF: CENAF3 Position */
-#define GPIO_PIN_INT_CIENF_CENAF3_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF3 Mask     */
-#define GPIO_PIN_INT_CIENF_CENAF4_Pos                         4                                                         /*!< GPIO_PIN_INT CIENF: CENAF4 Position */
-#define GPIO_PIN_INT_CIENF_CENAF4_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF4 Mask     */
-#define GPIO_PIN_INT_CIENF_CENAF5_Pos                         5                                                         /*!< GPIO_PIN_INT CIENF: CENAF5 Position */
-#define GPIO_PIN_INT_CIENF_CENAF5_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF5 Mask     */
-#define GPIO_PIN_INT_CIENF_CENAF6_Pos                         6                                                         /*!< GPIO_PIN_INT CIENF: CENAF6 Position */
-#define GPIO_PIN_INT_CIENF_CENAF6_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF6 Mask     */
-#define GPIO_PIN_INT_CIENF_CENAF7_Pos                         7                                                         /*!< GPIO_PIN_INT CIENF: CENAF7 Position */
-#define GPIO_PIN_INT_CIENF_CENAF7_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos)                 /*!< GPIO_PIN_INT CIENF: CENAF7 Mask     */
-
-// ------------------------------------  GPIO_PIN_INT_RISE  ---------------------------------------
-#define GPIO_PIN_INT_RISE_RDET0_Pos                           0                                                         /*!< GPIO_PIN_INT RISE: RDET0 Position   */
-#define GPIO_PIN_INT_RISE_RDET0_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos)                   /*!< GPIO_PIN_INT RISE: RDET0 Mask       */
-#define GPIO_PIN_INT_RISE_RDET1_Pos                           1                                                         /*!< GPIO_PIN_INT RISE: RDET1 Position   */
-#define GPIO_PIN_INT_RISE_RDET1_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos)                   /*!< GPIO_PIN_INT RISE: RDET1 Mask       */
-#define GPIO_PIN_INT_RISE_RDET2_Pos                           2                                                         /*!< GPIO_PIN_INT RISE: RDET2 Position   */
-#define GPIO_PIN_INT_RISE_RDET2_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos)                   /*!< GPIO_PIN_INT RISE: RDET2 Mask       */
-#define GPIO_PIN_INT_RISE_RDET3_Pos                           3                                                         /*!< GPIO_PIN_INT RISE: RDET3 Position   */
-#define GPIO_PIN_INT_RISE_RDET3_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos)                   /*!< GPIO_PIN_INT RISE: RDET3 Mask       */
-#define GPIO_PIN_INT_RISE_RDET4_Pos                           4                                                         /*!< GPIO_PIN_INT RISE: RDET4 Position   */
-#define GPIO_PIN_INT_RISE_RDET4_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos)                   /*!< GPIO_PIN_INT RISE: RDET4 Mask       */
-#define GPIO_PIN_INT_RISE_RDET5_Pos                           5                                                         /*!< GPIO_PIN_INT RISE: RDET5 Position   */
-#define GPIO_PIN_INT_RISE_RDET5_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos)                   /*!< GPIO_PIN_INT RISE: RDET5 Mask       */
-#define GPIO_PIN_INT_RISE_RDET6_Pos                           6                                                         /*!< GPIO_PIN_INT RISE: RDET6 Position   */
-#define GPIO_PIN_INT_RISE_RDET6_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos)                   /*!< GPIO_PIN_INT RISE: RDET6 Mask       */
-#define GPIO_PIN_INT_RISE_RDET7_Pos                           7                                                         /*!< GPIO_PIN_INT RISE: RDET7 Position   */
-#define GPIO_PIN_INT_RISE_RDET7_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos)                   /*!< GPIO_PIN_INT RISE: RDET7 Mask       */
-
-// ------------------------------------  GPIO_PIN_INT_FALL  ---------------------------------------
-#define GPIO_PIN_INT_FALL_FDET0_Pos                           0                                                         /*!< GPIO_PIN_INT FALL: FDET0 Position   */
-#define GPIO_PIN_INT_FALL_FDET0_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos)                   /*!< GPIO_PIN_INT FALL: FDET0 Mask       */
-#define GPIO_PIN_INT_FALL_FDET1_Pos                           1                                                         /*!< GPIO_PIN_INT FALL: FDET1 Position   */
-#define GPIO_PIN_INT_FALL_FDET1_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos)                   /*!< GPIO_PIN_INT FALL: FDET1 Mask       */
-#define GPIO_PIN_INT_FALL_FDET2_Pos                           2                                                         /*!< GPIO_PIN_INT FALL: FDET2 Position   */
-#define GPIO_PIN_INT_FALL_FDET2_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos)                   /*!< GPIO_PIN_INT FALL: FDET2 Mask       */
-#define GPIO_PIN_INT_FALL_FDET3_Pos                           3                                                         /*!< GPIO_PIN_INT FALL: FDET3 Position   */
-#define GPIO_PIN_INT_FALL_FDET3_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos)                   /*!< GPIO_PIN_INT FALL: FDET3 Mask       */
-#define GPIO_PIN_INT_FALL_FDET4_Pos                           4                                                         /*!< GPIO_PIN_INT FALL: FDET4 Position   */
-#define GPIO_PIN_INT_FALL_FDET4_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos)                   /*!< GPIO_PIN_INT FALL: FDET4 Mask       */
-#define GPIO_PIN_INT_FALL_FDET5_Pos                           5                                                         /*!< GPIO_PIN_INT FALL: FDET5 Position   */
-#define GPIO_PIN_INT_FALL_FDET5_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos)                   /*!< GPIO_PIN_INT FALL: FDET5 Mask       */
-#define GPIO_PIN_INT_FALL_FDET6_Pos                           6                                                         /*!< GPIO_PIN_INT FALL: FDET6 Position   */
-#define GPIO_PIN_INT_FALL_FDET6_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos)                   /*!< GPIO_PIN_INT FALL: FDET6 Mask       */
-#define GPIO_PIN_INT_FALL_FDET7_Pos                           7                                                         /*!< GPIO_PIN_INT FALL: FDET7 Position   */
-#define GPIO_PIN_INT_FALL_FDET7_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos)                   /*!< GPIO_PIN_INT FALL: FDET7 Mask       */
-
-// ------------------------------------  GPIO_PIN_INT_IST  ----------------------------------------
-#define GPIO_PIN_INT_IST_PSTAT0_Pos                           0                                                         /*!< GPIO_PIN_INT IST: PSTAT0 Position   */
-#define GPIO_PIN_INT_IST_PSTAT0_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT0 Mask       */
-#define GPIO_PIN_INT_IST_PSTAT1_Pos                           1                                                         /*!< GPIO_PIN_INT IST: PSTAT1 Position   */
-#define GPIO_PIN_INT_IST_PSTAT1_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT1 Mask       */
-#define GPIO_PIN_INT_IST_PSTAT2_Pos                           2                                                         /*!< GPIO_PIN_INT IST: PSTAT2 Position   */
-#define GPIO_PIN_INT_IST_PSTAT2_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT2 Mask       */
-#define GPIO_PIN_INT_IST_PSTAT3_Pos                           3                                                         /*!< GPIO_PIN_INT IST: PSTAT3 Position   */
-#define GPIO_PIN_INT_IST_PSTAT3_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT3 Mask       */
-#define GPIO_PIN_INT_IST_PSTAT4_Pos                           4                                                         /*!< GPIO_PIN_INT IST: PSTAT4 Position   */
-#define GPIO_PIN_INT_IST_PSTAT4_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT4 Mask       */
-#define GPIO_PIN_INT_IST_PSTAT5_Pos                           5                                                         /*!< GPIO_PIN_INT IST: PSTAT5 Position   */
-#define GPIO_PIN_INT_IST_PSTAT5_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT5 Mask       */
-#define GPIO_PIN_INT_IST_PSTAT6_Pos                           6                                                         /*!< GPIO_PIN_INT IST: PSTAT6 Position   */
-#define GPIO_PIN_INT_IST_PSTAT6_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT6 Mask       */
-#define GPIO_PIN_INT_IST_PSTAT7_Pos                           7                                                         /*!< GPIO_PIN_INT IST: PSTAT7 Position   */
-#define GPIO_PIN_INT_IST_PSTAT7_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos)                   /*!< GPIO_PIN_INT IST: PSTAT7 Mask       */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                            GPIO_GROUP_INTn Position & Mask                           -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------  GPIO_GROUP_INTn_CTRL  --------------------------------------
-#define GPIO_GROUP_INTn_CTRL_INT_Pos                          0                                                         /*!< GPIO_GROUP_INTn CTRL: INT Position  */
-#define GPIO_GROUP_INTn_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos)                  /*!< GPIO_GROUP_INTn CTRL: INT Mask      */
-#define GPIO_GROUP_INTn_CTRL_COMB_Pos                         1                                                         /*!< GPIO_GROUP_INTn CTRL: COMB Position */
-#define GPIO_GROUP_INTn_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos)                 /*!< GPIO_GROUP_INTn CTRL: COMB Mask     */
-#define GPIO_GROUP_INTn_CTRL_TRIG_Pos                         2                                                         /*!< GPIO_GROUP_INTn CTRL: TRIG Position */
-#define GPIO_GROUP_INTn_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos)                 /*!< GPIO_GROUP_INTn CTRL: TRIG Mask     */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_POL0  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */
-#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_POL1  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */
-#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_POL2  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */
-#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_POL3  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */
-#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_POL4  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */
-#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_POL5  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */
-#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_POL6  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */
-#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_POL7  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos)           /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */
-#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos)          /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_ENA0  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_ENA1  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_ENA2  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_ENA3  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_ENA4  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_ENA5  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_ENA6  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INTn_PORT_ENA7  -----------------------------------
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos)           /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos)          /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                            GPIO_GROUP_INT1 Position & Mask                           -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------  GPIO_GROUP_INT1_CTRL  --------------------------------------
-#define GPIO_GROUP_INT1_CTRL_INT_Pos                          0                                                         /*!< GPIO_GROUP_INT1 CTRL: INT Position  */
-#define GPIO_GROUP_INT1_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos)                  /*!< GPIO_GROUP_INT1 CTRL: INT Mask      */
-#define GPIO_GROUP_INT1_CTRL_COMB_Pos                         1                                                         /*!< GPIO_GROUP_INT1 CTRL: COMB Position */
-#define GPIO_GROUP_INT1_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos)                 /*!< GPIO_GROUP_INT1 CTRL: COMB Mask     */
-#define GPIO_GROUP_INT1_CTRL_TRIG_Pos                         2                                                         /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */
-#define GPIO_GROUP_INT1_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos)                 /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask     */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_POL0  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */
-#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_POL1  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */
-#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_POL2  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */
-#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_POL3  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */
-#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_POL4  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */
-#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_POL5  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */
-#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_POL6  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */
-#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_POL7  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */
-#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_ENA0  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_ENA1  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_ENA2  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_ENA3  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_ENA4  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_ENA5  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_ENA6  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */
-
-// --------------------------------  GPIO_GROUP_INT1_PORT_ENA7  -----------------------------------
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos                   0                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos                   1                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos                   2                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos                   3                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos                   4                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos                   5                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos                   6                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos                   7                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos                   8                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos                   9                                                         /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos)           /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos                  10                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos                  11                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos                  12                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos                  13                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos                  14                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos                  15                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos                  16                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos                  17                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos                  18                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos                  19                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos                  20                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos                  21                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos                  22                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos                  23                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos                  24                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos                  25                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos                  26                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos                  27                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos                  28                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos                  29                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos                  30                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos                  31                                                        /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos)          /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 MCPWM Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  MCPWM_CON  -------------------------------------------
-#define MCPWM_CON_RUN0_Pos                                    0                                                         /*!< MCPWM CON: RUN0 Position            */
-#define MCPWM_CON_RUN0_Msk                                    (0x01UL << MCPWM_CON_RUN0_Pos)                            /*!< MCPWM CON: RUN0 Mask                */
-#define MCPWM_CON_CENTER0_Pos                                 1                                                         /*!< MCPWM CON: CENTER0 Position         */
-#define MCPWM_CON_CENTER0_Msk                                 (0x01UL << MCPWM_CON_CENTER0_Pos)                         /*!< MCPWM CON: CENTER0 Mask             */
-#define MCPWM_CON_POLA0_Pos                                   2                                                         /*!< MCPWM CON: POLA0 Position           */
-#define MCPWM_CON_POLA0_Msk                                   (0x01UL << MCPWM_CON_POLA0_Pos)                           /*!< MCPWM CON: POLA0 Mask               */
-#define MCPWM_CON_DTE0_Pos                                    3                                                         /*!< MCPWM CON: DTE0 Position            */
-#define MCPWM_CON_DTE0_Msk                                    (0x01UL << MCPWM_CON_DTE0_Pos)                            /*!< MCPWM CON: DTE0 Mask                */
-#define MCPWM_CON_DISUP0_Pos                                  4                                                         /*!< MCPWM CON: DISUP0 Position          */
-#define MCPWM_CON_DISUP0_Msk                                  (0x01UL << MCPWM_CON_DISUP0_Pos)                          /*!< MCPWM CON: DISUP0 Mask              */
-#define MCPWM_CON_RUN1_Pos                                    8                                                         /*!< MCPWM CON: RUN1 Position            */
-#define MCPWM_CON_RUN1_Msk                                    (0x01UL << MCPWM_CON_RUN1_Pos)                            /*!< MCPWM CON: RUN1 Mask                */
-#define MCPWM_CON_CENTER1_Pos                                 9                                                         /*!< MCPWM CON: CENTER1 Position         */
-#define MCPWM_CON_CENTER1_Msk                                 (0x01UL << MCPWM_CON_CENTER1_Pos)                         /*!< MCPWM CON: CENTER1 Mask             */
-#define MCPWM_CON_POLA1_Pos                                   10                                                        /*!< MCPWM CON: POLA1 Position           */
-#define MCPWM_CON_POLA1_Msk                                   (0x01UL << MCPWM_CON_POLA1_Pos)                           /*!< MCPWM CON: POLA1 Mask               */
-#define MCPWM_CON_DTE1_Pos                                    11                                                        /*!< MCPWM CON: DTE1 Position            */
-#define MCPWM_CON_DTE1_Msk                                    (0x01UL << MCPWM_CON_DTE1_Pos)                            /*!< MCPWM CON: DTE1 Mask                */
-#define MCPWM_CON_DISUP1_Pos                                  12                                                        /*!< MCPWM CON: DISUP1 Position          */
-#define MCPWM_CON_DISUP1_Msk                                  (0x01UL << MCPWM_CON_DISUP1_Pos)                          /*!< MCPWM CON: DISUP1 Mask              */
-#define MCPWM_CON_RUN2_Pos                                    16                                                        /*!< MCPWM CON: RUN2 Position            */
-#define MCPWM_CON_RUN2_Msk                                    (0x01UL << MCPWM_CON_RUN2_Pos)                            /*!< MCPWM CON: RUN2 Mask                */
-#define MCPWM_CON_CENTER2_Pos                                 17                                                        /*!< MCPWM CON: CENTER2 Position         */
-#define MCPWM_CON_CENTER2_Msk                                 (0x01UL << MCPWM_CON_CENTER2_Pos)                         /*!< MCPWM CON: CENTER2 Mask             */
-#define MCPWM_CON_POLA2_Pos                                   18                                                        /*!< MCPWM CON: POLA2 Position           */
-#define MCPWM_CON_POLA2_Msk                                   (0x01UL << MCPWM_CON_POLA2_Pos)                           /*!< MCPWM CON: POLA2 Mask               */
-#define MCPWM_CON_DTE2_Pos                                    19                                                        /*!< MCPWM CON: DTE2 Position            */
-#define MCPWM_CON_DTE2_Msk                                    (0x01UL << MCPWM_CON_DTE2_Pos)                            /*!< MCPWM CON: DTE2 Mask                */
-#define MCPWM_CON_DISUP2_Pos                                  20                                                        /*!< MCPWM CON: DISUP2 Position          */
-#define MCPWM_CON_DISUP2_Msk                                  (0x01UL << MCPWM_CON_DISUP2_Pos)                          /*!< MCPWM CON: DISUP2 Mask              */
-#define MCPWM_CON_INVBDC_Pos                                  29                                                        /*!< MCPWM CON: INVBDC Position          */
-#define MCPWM_CON_INVBDC_Msk                                  (0x01UL << MCPWM_CON_INVBDC_Pos)                          /*!< MCPWM CON: INVBDC Mask              */
-#define MCPWM_CON_ACMODE_Pos                                  30                                                        /*!< MCPWM CON: ACMODE Position          */
-#define MCPWM_CON_ACMODE_Msk                                  (0x01UL << MCPWM_CON_ACMODE_Pos)                          /*!< MCPWM CON: ACMODE Mask              */
-#define MCPWM_CON_DCMODE_Pos                                  31                                                        /*!< MCPWM CON: DCMODE Position          */
-#define MCPWM_CON_DCMODE_Msk                                  (0x01UL << MCPWM_CON_DCMODE_Pos)                          /*!< MCPWM CON: DCMODE Mask              */
-
-// --------------------------------------  MCPWM_CON_SET  -----------------------------------------
-#define MCPWM_CON_SET_RUN0_SET_Pos                            0                                                         /*!< MCPWM CON_SET: RUN0_SET Position    */
-#define MCPWM_CON_SET_RUN0_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos)                    /*!< MCPWM CON_SET: RUN0_SET Mask        */
-#define MCPWM_CON_SET_CENTER0_SET_Pos                         1                                                         /*!< MCPWM CON_SET: CENTER0_SET Position */
-#define MCPWM_CON_SET_CENTER0_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos)                 /*!< MCPWM CON_SET: CENTER0_SET Mask     */
-#define MCPWM_CON_SET_POLA0_SET_Pos                           2                                                         /*!< MCPWM CON_SET: POLA0_SET Position   */
-#define MCPWM_CON_SET_POLA0_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos)                   /*!< MCPWM CON_SET: POLA0_SET Mask       */
-#define MCPWM_CON_SET_DTE0_SET_Pos                            3                                                         /*!< MCPWM CON_SET: DTE0_SET Position    */
-#define MCPWM_CON_SET_DTE0_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos)                    /*!< MCPWM CON_SET: DTE0_SET Mask        */
-#define MCPWM_CON_SET_DISUP0_SET_Pos                          4                                                         /*!< MCPWM CON_SET: DISUP0_SET Position  */
-#define MCPWM_CON_SET_DISUP0_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos)                  /*!< MCPWM CON_SET: DISUP0_SET Mask      */
-#define MCPWM_CON_SET_RUN1_SET_Pos                            8                                                         /*!< MCPWM CON_SET: RUN1_SET Position    */
-#define MCPWM_CON_SET_RUN1_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos)                    /*!< MCPWM CON_SET: RUN1_SET Mask        */
-#define MCPWM_CON_SET_CENTER1_SET_Pos                         9                                                         /*!< MCPWM CON_SET: CENTER1_SET Position */
-#define MCPWM_CON_SET_CENTER1_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos)                 /*!< MCPWM CON_SET: CENTER1_SET Mask     */
-#define MCPWM_CON_SET_POLA1_SET_Pos                           10                                                        /*!< MCPWM CON_SET: POLA1_SET Position   */
-#define MCPWM_CON_SET_POLA1_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos)                   /*!< MCPWM CON_SET: POLA1_SET Mask       */
-#define MCPWM_CON_SET_DTE1_SET_Pos                            11                                                        /*!< MCPWM CON_SET: DTE1_SET Position    */
-#define MCPWM_CON_SET_DTE1_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos)                    /*!< MCPWM CON_SET: DTE1_SET Mask        */
-#define MCPWM_CON_SET_DISUP1_SET_Pos                          12                                                        /*!< MCPWM CON_SET: DISUP1_SET Position  */
-#define MCPWM_CON_SET_DISUP1_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos)                  /*!< MCPWM CON_SET: DISUP1_SET Mask      */
-#define MCPWM_CON_SET_RUN2_SET_Pos                            16                                                        /*!< MCPWM CON_SET: RUN2_SET Position    */
-#define MCPWM_CON_SET_RUN2_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos)                    /*!< MCPWM CON_SET: RUN2_SET Mask        */
-#define MCPWM_CON_SET_CENTER2_SET_Pos                         17                                                        /*!< MCPWM CON_SET: CENTER2_SET Position */
-#define MCPWM_CON_SET_CENTER2_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos)                 /*!< MCPWM CON_SET: CENTER2_SET Mask     */
-#define MCPWM_CON_SET_POLA2_SET_Pos                           18                                                        /*!< MCPWM CON_SET: POLA2_SET Position   */
-#define MCPWM_CON_SET_POLA2_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos)                   /*!< MCPWM CON_SET: POLA2_SET Mask       */
-#define MCPWM_CON_SET_DTE2_SET_Pos                            19                                                        /*!< MCPWM CON_SET: DTE2_SET Position    */
-#define MCPWM_CON_SET_DTE2_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos)                    /*!< MCPWM CON_SET: DTE2_SET Mask        */
-#define MCPWM_CON_SET_DISUP2_SET_Pos                          20                                                        /*!< MCPWM CON_SET: DISUP2_SET Position  */
-#define MCPWM_CON_SET_DISUP2_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos)                  /*!< MCPWM CON_SET: DISUP2_SET Mask      */
-#define MCPWM_CON_SET_INVBDC_SET_Pos                          29                                                        /*!< MCPWM CON_SET: INVBDC_SET Position  */
-#define MCPWM_CON_SET_INVBDC_SET_Msk                          (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos)                  /*!< MCPWM CON_SET: INVBDC_SET Mask      */
-#define MCPWM_CON_SET_ACMODE_SET_Pos                          30                                                        /*!< MCPWM CON_SET: ACMODE_SET Position  */
-#define MCPWM_CON_SET_ACMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos)                  /*!< MCPWM CON_SET: ACMODE_SET Mask      */
-#define MCPWM_CON_SET_DCMODE_SET_Pos                          31                                                        /*!< MCPWM CON_SET: DCMODE_SET Position  */
-#define MCPWM_CON_SET_DCMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos)                  /*!< MCPWM CON_SET: DCMODE_SET Mask      */
-
-// --------------------------------------  MCPWM_CON_CLR  -----------------------------------------
-#define MCPWM_CON_CLR_RUN0_CLR_Pos                            0                                                         /*!< MCPWM CON_CLR: RUN0_CLR Position    */
-#define MCPWM_CON_CLR_RUN0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN0_CLR Mask        */
-#define MCPWM_CON_CLR_CENTER0_CLR_Pos                         1                                                         /*!< MCPWM CON_CLR: CENTER0_CLR Position */
-#define MCPWM_CON_CLR_CENTER0_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER0_CLR Mask     */
-#define MCPWM_CON_CLR_POLA0_CLR_Pos                           2                                                         /*!< MCPWM CON_CLR: POLA0_CLR Position   */
-#define MCPWM_CON_CLR_POLA0_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA0_CLR Mask       */
-#define MCPWM_CON_CLR_DTE0_CLR_Pos                            3                                                         /*!< MCPWM CON_CLR: DTE0_CLR Position    */
-#define MCPWM_CON_CLR_DTE0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE0_CLR Mask        */
-#define MCPWM_CON_CLR_DISUP0_CLR_Pos                          4                                                         /*!< MCPWM CON_CLR: DISUP0_CLR Position  */
-#define MCPWM_CON_CLR_DISUP0_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP0_CLR Mask      */
-#define MCPWM_CON_CLR_RUN1_CLR_Pos                            8                                                         /*!< MCPWM CON_CLR: RUN1_CLR Position    */
-#define MCPWM_CON_CLR_RUN1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN1_CLR Mask        */
-#define MCPWM_CON_CLR_CENTER1_CLR_Pos                         9                                                         /*!< MCPWM CON_CLR: CENTER1_CLR Position */
-#define MCPWM_CON_CLR_CENTER1_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER1_CLR Mask     */
-#define MCPWM_CON_CLR_POLA1_CLR_Pos                           10                                                        /*!< MCPWM CON_CLR: POLA1_CLR Position   */
-#define MCPWM_CON_CLR_POLA1_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA1_CLR Mask       */
-#define MCPWM_CON_CLR_DTE1_CLR_Pos                            11                                                        /*!< MCPWM CON_CLR: DTE1_CLR Position    */
-#define MCPWM_CON_CLR_DTE1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE1_CLR Mask        */
-#define MCPWM_CON_CLR_DISUP1_CLR_Pos                          12                                                        /*!< MCPWM CON_CLR: DISUP1_CLR Position  */
-#define MCPWM_CON_CLR_DISUP1_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP1_CLR Mask      */
-#define MCPWM_CON_CLR_RUN2_CLR_Pos                            16                                                        /*!< MCPWM CON_CLR: RUN2_CLR Position    */
-#define MCPWM_CON_CLR_RUN2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos)                    /*!< MCPWM CON_CLR: RUN2_CLR Mask        */
-#define MCPWM_CON_CLR_CENTER2_CLR_Pos                         17                                                        /*!< MCPWM CON_CLR: CENTER2_CLR Position */
-#define MCPWM_CON_CLR_CENTER2_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos)                 /*!< MCPWM CON_CLR: CENTER2_CLR Mask     */
-#define MCPWM_CON_CLR_POLA2_CLR_Pos                           18                                                        /*!< MCPWM CON_CLR: POLA2_CLR Position   */
-#define MCPWM_CON_CLR_POLA2_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos)                   /*!< MCPWM CON_CLR: POLA2_CLR Mask       */
-#define MCPWM_CON_CLR_DTE2_CLR_Pos                            19                                                        /*!< MCPWM CON_CLR: DTE2_CLR Position    */
-#define MCPWM_CON_CLR_DTE2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos)                    /*!< MCPWM CON_CLR: DTE2_CLR Mask        */
-#define MCPWM_CON_CLR_DISUP2_CLR_Pos                          20                                                        /*!< MCPWM CON_CLR: DISUP2_CLR Position  */
-#define MCPWM_CON_CLR_DISUP2_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos)                  /*!< MCPWM CON_CLR: DISUP2_CLR Mask      */
-#define MCPWM_CON_CLR_INVBDC_CLR_Pos                          29                                                        /*!< MCPWM CON_CLR: INVBDC_CLR Position  */
-#define MCPWM_CON_CLR_INVBDC_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos)                  /*!< MCPWM CON_CLR: INVBDC_CLR Mask      */
-#define MCPWM_CON_CLR_ACMOD_CLR_Pos                           30                                                        /*!< MCPWM CON_CLR: ACMOD_CLR Position   */
-#define MCPWM_CON_CLR_ACMOD_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos)                   /*!< MCPWM CON_CLR: ACMOD_CLR Mask       */
-#define MCPWM_CON_CLR_DCMODE_CLR_Pos                          31                                                        /*!< MCPWM CON_CLR: DCMODE_CLR Position  */
-#define MCPWM_CON_CLR_DCMODE_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos)                  /*!< MCPWM CON_CLR: DCMODE_CLR Mask      */
-
-// --------------------------------------  MCPWM_CAPCON  ------------------------------------------
-#define MCPWM_CAPCON_CAP0MCI0_RE_Pos                          0                                                         /*!< MCPWM CAPCON: CAP0MCI0_RE Position  */
-#define MCPWM_CAPCON_CAP0MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI0_RE Mask      */
-#define MCPWM_CAPCON_CAP0MCI0_FE_Pos                          1                                                         /*!< MCPWM CAPCON: CAP0MCI0_FE Position  */
-#define MCPWM_CAPCON_CAP0MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI0_FE Mask      */
-#define MCPWM_CAPCON_CAP0MCI1_RE_Pos                          2                                                         /*!< MCPWM CAPCON: CAP0MCI1_RE Position  */
-#define MCPWM_CAPCON_CAP0MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI1_RE Mask      */
-#define MCPWM_CAPCON_CAP0MCI1_FE_Pos                          3                                                         /*!< MCPWM CAPCON: CAP0MCI1_FE Position  */
-#define MCPWM_CAPCON_CAP0MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI1_FE Mask      */
-#define MCPWM_CAPCON_CAP0MCI2_RE_Pos                          4                                                         /*!< MCPWM CAPCON: CAP0MCI2_RE Position  */
-#define MCPWM_CAPCON_CAP0MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI2_RE Mask      */
-#define MCPWM_CAPCON_CAP0MCI2_FE_Pos                          5                                                         /*!< MCPWM CAPCON: CAP0MCI2_FE Position  */
-#define MCPWM_CAPCON_CAP0MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP0MCI2_FE Mask      */
-#define MCPWM_CAPCON_CAP1MCI0_RE_Pos                          6                                                         /*!< MCPWM CAPCON: CAP1MCI0_RE Position  */
-#define MCPWM_CAPCON_CAP1MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI0_RE Mask      */
-#define MCPWM_CAPCON_CAP1MCI0_FE_Pos                          7                                                         /*!< MCPWM CAPCON: CAP1MCI0_FE Position  */
-#define MCPWM_CAPCON_CAP1MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI0_FE Mask      */
-#define MCPWM_CAPCON_CAP1MCI1_RE_Pos                          8                                                         /*!< MCPWM CAPCON: CAP1MCI1_RE Position  */
-#define MCPWM_CAPCON_CAP1MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI1_RE Mask      */
-#define MCPWM_CAPCON_CAP1MCI1_FE_Pos                          9                                                         /*!< MCPWM CAPCON: CAP1MCI1_FE Position  */
-#define MCPWM_CAPCON_CAP1MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI1_FE Mask      */
-#define MCPWM_CAPCON_CAP1MCI2_RE_Pos                          10                                                        /*!< MCPWM CAPCON: CAP1MCI2_RE Position  */
-#define MCPWM_CAPCON_CAP1MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI2_RE Mask      */
-#define MCPWM_CAPCON_CAP1MCI2_FE_Pos                          11                                                        /*!< MCPWM CAPCON: CAP1MCI2_FE Position  */
-#define MCPWM_CAPCON_CAP1MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP1MCI2_FE Mask      */
-#define MCPWM_CAPCON_CAP2MCI0_RE_Pos                          12                                                        /*!< MCPWM CAPCON: CAP2MCI0_RE Position  */
-#define MCPWM_CAPCON_CAP2MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI0_RE Mask      */
-#define MCPWM_CAPCON_CAP2MCI0_FE_Pos                          13                                                        /*!< MCPWM CAPCON: CAP2MCI0_FE Position  */
-#define MCPWM_CAPCON_CAP2MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI0_FE Mask      */
-#define MCPWM_CAPCON_CAP2MCI1_RE_Pos                          14                                                        /*!< MCPWM CAPCON: CAP2MCI1_RE Position  */
-#define MCPWM_CAPCON_CAP2MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI1_RE Mask      */
-#define MCPWM_CAPCON_CAP2MCI1_FE_Pos                          15                                                        /*!< MCPWM CAPCON: CAP2MCI1_FE Position  */
-#define MCPWM_CAPCON_CAP2MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI1_FE Mask      */
-#define MCPWM_CAPCON_CAP2MCI2_RE_Pos                          16                                                        /*!< MCPWM CAPCON: CAP2MCI2_RE Position  */
-#define MCPWM_CAPCON_CAP2MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI2_RE Mask      */
-#define MCPWM_CAPCON_CAP2MCI2_FE_Pos                          17                                                        /*!< MCPWM CAPCON: CAP2MCI2_FE Position  */
-#define MCPWM_CAPCON_CAP2MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos)                  /*!< MCPWM CAPCON: CAP2MCI2_FE Mask      */
-#define MCPWM_CAPCON_RT0_Pos                                  18                                                        /*!< MCPWM CAPCON: RT0 Position          */
-#define MCPWM_CAPCON_RT0_Msk                                  (0x01UL << MCPWM_CAPCON_RT0_Pos)                          /*!< MCPWM CAPCON: RT0 Mask              */
-#define MCPWM_CAPCON_RT1_Pos                                  19                                                        /*!< MCPWM CAPCON: RT1 Position          */
-#define MCPWM_CAPCON_RT1_Msk                                  (0x01UL << MCPWM_CAPCON_RT1_Pos)                          /*!< MCPWM CAPCON: RT1 Mask              */
-#define MCPWM_CAPCON_RT2_Pos                                  20                                                        /*!< MCPWM CAPCON: RT2 Position          */
-#define MCPWM_CAPCON_RT2_Msk                                  (0x01UL << MCPWM_CAPCON_RT2_Pos)                          /*!< MCPWM CAPCON: RT2 Mask              */
-#define MCPWM_CAPCON_HNFCAP0_Pos                              21                                                        /*!< MCPWM CAPCON: HNFCAP0 Position      */
-#define MCPWM_CAPCON_HNFCAP0_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP0_Pos)                      /*!< MCPWM CAPCON: HNFCAP0 Mask          */
-#define MCPWM_CAPCON_HNFCAP1_Pos                              22                                                        /*!< MCPWM CAPCON: HNFCAP1 Position      */
-#define MCPWM_CAPCON_HNFCAP1_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP1_Pos)                      /*!< MCPWM CAPCON: HNFCAP1 Mask          */
-#define MCPWM_CAPCON_HNFCAP2_Pos                              23                                                        /*!< MCPWM CAPCON: HNFCAP2 Position      */
-#define MCPWM_CAPCON_HNFCAP2_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP2_Pos)                      /*!< MCPWM CAPCON: HNFCAP2 Mask          */
-
-// ------------------------------------  MCPWM_CAPCON_SET  ----------------------------------------
-#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos                  0                                                         /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */
-#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos                  1                                                         /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */
-#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos                  2                                                         /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */
-#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos                  3                                                         /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */
-#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos                  4                                                         /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */
-#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos                  5                                                         /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */
-#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos                  6                                                         /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */
-#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos                  7                                                         /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */
-#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos                  8                                                         /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */
-#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos                  9                                                         /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */
-#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos                  10                                                        /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */
-#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos                  11                                                        /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */
-#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos                  12                                                        /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */
-#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos                  13                                                        /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */
-#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos                  14                                                        /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */
-#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos                  15                                                        /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */
-#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos                  16                                                        /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */
-#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */
-#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos                  17                                                        /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */
-#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos)          /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */
-#define MCPWM_CAPCON_SET_RT0_SET_Pos                          18                                                        /*!< MCPWM CAPCON_SET: RT0_SET Position  */
-#define MCPWM_CAPCON_SET_RT0_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT0_SET Mask      */
-#define MCPWM_CAPCON_SET_RT1_SET_Pos                          19                                                        /*!< MCPWM CAPCON_SET: RT1_SET Position  */
-#define MCPWM_CAPCON_SET_RT1_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT1_SET Mask      */
-#define MCPWM_CAPCON_SET_RT2_SET_Pos                          20                                                        /*!< MCPWM CAPCON_SET: RT2_SET Position  */
-#define MCPWM_CAPCON_SET_RT2_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos)                  /*!< MCPWM CAPCON_SET: RT2_SET Mask      */
-#define MCPWM_CAPCON_SET_HNFCAP0_SET_Pos                      21                                                        /*!< MCPWM CAPCON_SET: HNFCAP0_SET Position */
-#define MCPWM_CAPCON_SET_HNFCAP0_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP0_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP0_SET Mask  */
-#define MCPWM_CAPCON_SET_HNFCAP1_SET_Pos                      22                                                        /*!< MCPWM CAPCON_SET: HNFCAP1_SET Position */
-#define MCPWM_CAPCON_SET_HNFCAP1_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP1_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP1_SET Mask  */
-#define MCPWM_CAPCON_SET_HNFCAP2_SET_Pos                      23                                                        /*!< MCPWM CAPCON_SET: HNFCAP2_SET Position */
-#define MCPWM_CAPCON_SET_HNFCAP2_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP2_SET_Pos)              /*!< MCPWM CAPCON_SET: HNFCAP2_SET Mask  */
-
-// ------------------------------------  MCPWM_CAPCON_CLR  ----------------------------------------
-#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos                  0                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos                  1                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos                  2                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos                  3                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos                  4                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos                  5                                                         /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos                  6                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos                  7                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos                  8                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos                  9                                                         /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos                  10                                                        /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos                  11                                                        /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos                  12                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos                  13                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos                  14                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos                  15                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos                  16                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */
-#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos                  17                                                        /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */
-#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos)          /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */
-#define MCPWM_CAPCON_CLR_RT0_CLR_Pos                          18                                                        /*!< MCPWM CAPCON_CLR: RT0_CLR Position  */
-#define MCPWM_CAPCON_CLR_RT0_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT0_CLR Mask      */
-#define MCPWM_CAPCON_CLR_RT1_CLR_Pos                          19                                                        /*!< MCPWM CAPCON_CLR: RT1_CLR Position  */
-#define MCPWM_CAPCON_CLR_RT1_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT1_CLR Mask      */
-#define MCPWM_CAPCON_CLR_RT2_CLR_Pos                          20                                                        /*!< MCPWM CAPCON_CLR: RT2_CLR Position  */
-#define MCPWM_CAPCON_CLR_RT2_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos)                  /*!< MCPWM CAPCON_CLR: RT2_CLR Mask      */
-#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos                      21                                                        /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Position */
-#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Mask  */
-#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos                      22                                                        /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Position */
-#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Mask  */
-#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos                      23                                                        /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Position */
-#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos)              /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Mask  */
-
-// ----------------------------------------  MCPWM_TC0  -------------------------------------------
-#define MCPWM_TC0_MCTC_Pos                                    0                                                         /*!< MCPWM TC0: MCTC Position            */
-#define MCPWM_TC0_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC0_MCTC_Pos)                      /*!< MCPWM TC0: MCTC Mask                */
-
-// ----------------------------------------  MCPWM_TC1  -------------------------------------------
-#define MCPWM_TC1_MCTC_Pos                                    0                                                         /*!< MCPWM TC1: MCTC Position            */
-#define MCPWM_TC1_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC1_MCTC_Pos)                      /*!< MCPWM TC1: MCTC Mask                */
-
-// ----------------------------------------  MCPWM_TC2  -------------------------------------------
-#define MCPWM_TC2_MCTC_Pos                                    0                                                         /*!< MCPWM TC2: MCTC Position            */
-#define MCPWM_TC2_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC2_MCTC_Pos)                      /*!< MCPWM TC2: MCTC Mask                */
-
-// ---------------------------------------  MCPWM_LIM0  -------------------------------------------
-#define MCPWM_LIM0_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM0: MCLIM Position          */
-#define MCPWM_LIM0_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos)                    /*!< MCPWM LIM0: MCLIM Mask              */
-
-// ---------------------------------------  MCPWM_LIM1  -------------------------------------------
-#define MCPWM_LIM1_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM1: MCLIM Position          */
-#define MCPWM_LIM1_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos)                    /*!< MCPWM LIM1: MCLIM Mask              */
-
-// ---------------------------------------  MCPWM_LIM2  -------------------------------------------
-#define MCPWM_LIM2_MCLIM_Pos                                  0                                                         /*!< MCPWM LIM2: MCLIM Position          */
-#define MCPWM_LIM2_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos)                    /*!< MCPWM LIM2: MCLIM Mask              */
-
-// ---------------------------------------  MCPWM_MAT0  -------------------------------------------
-#define MCPWM_MAT0_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT0: MCMAT Position          */
-#define MCPWM_MAT0_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos)                    /*!< MCPWM MAT0: MCMAT Mask              */
-
-// ---------------------------------------  MCPWM_MAT1  -------------------------------------------
-#define MCPWM_MAT1_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT1: MCMAT Position          */
-#define MCPWM_MAT1_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos)                    /*!< MCPWM MAT1: MCMAT Mask              */
-
-// ---------------------------------------  MCPWM_MAT2  -------------------------------------------
-#define MCPWM_MAT2_MCMAT_Pos                                  0                                                         /*!< MCPWM MAT2: MCMAT Position          */
-#define MCPWM_MAT2_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos)                    /*!< MCPWM MAT2: MCMAT Mask              */
-
-// ----------------------------------------  MCPWM_DT  --------------------------------------------
-#define MCPWM_DT_DT0_Pos                                      0                                                         /*!< MCPWM DT: DT0 Position              */
-#define MCPWM_DT_DT0_Msk                                      (0x000003ffUL << MCPWM_DT_DT0_Pos)                        /*!< MCPWM DT: DT0 Mask                  */
-#define MCPWM_DT_DT1_Pos                                      10                                                        /*!< MCPWM DT: DT1 Position              */
-#define MCPWM_DT_DT1_Msk                                      (0x000003ffUL << MCPWM_DT_DT1_Pos)                        /*!< MCPWM DT: DT1 Mask                  */
-#define MCPWM_DT_DT2_Pos                                      20                                                        /*!< MCPWM DT: DT2 Position              */
-#define MCPWM_DT_DT2_Msk                                      (0x000003ffUL << MCPWM_DT_DT2_Pos)                        /*!< MCPWM DT: DT2 Mask                  */
-
-// ----------------------------------------  MCPWM_CCP  -------------------------------------------
-#define MCPWM_CCP_CCPA0_Pos                                   0                                                         /*!< MCPWM CCP: CCPA0 Position           */
-#define MCPWM_CCP_CCPA0_Msk                                   (0x01UL << MCPWM_CCP_CCPA0_Pos)                           /*!< MCPWM CCP: CCPA0 Mask               */
-#define MCPWM_CCP_CCPB0_Pos                                   1                                                         /*!< MCPWM CCP: CCPB0 Position           */
-#define MCPWM_CCP_CCPB0_Msk                                   (0x01UL << MCPWM_CCP_CCPB0_Pos)                           /*!< MCPWM CCP: CCPB0 Mask               */
-#define MCPWM_CCP_CCPA1_Pos                                   2                                                         /*!< MCPWM CCP: CCPA1 Position           */
-#define MCPWM_CCP_CCPA1_Msk                                   (0x01UL << MCPWM_CCP_CCPA1_Pos)                           /*!< MCPWM CCP: CCPA1 Mask               */
-#define MCPWM_CCP_CCPB1_Pos                                   3                                                         /*!< MCPWM CCP: CCPB1 Position           */
-#define MCPWM_CCP_CCPB1_Msk                                   (0x01UL << MCPWM_CCP_CCPB1_Pos)                           /*!< MCPWM CCP: CCPB1 Mask               */
-#define MCPWM_CCP_CCPA2_Pos                                   4                                                         /*!< MCPWM CCP: CCPA2 Position           */
-#define MCPWM_CCP_CCPA2_Msk                                   (0x01UL << MCPWM_CCP_CCPA2_Pos)                           /*!< MCPWM CCP: CCPA2 Mask               */
-#define MCPWM_CCP_CCPB2_Pos                                   5                                                         /*!< MCPWM CCP: CCPB2 Position           */
-#define MCPWM_CCP_CCPB2_Msk                                   (0x01UL << MCPWM_CCP_CCPB2_Pos)                           /*!< MCPWM CCP: CCPB2 Mask               */
-
-// ---------------------------------------  MCPWM_CAP0  -------------------------------------------
-#define MCPWM_CAP0_CAP_Pos                                    0                                                         /*!< MCPWM CAP0: CAP Position            */
-#define MCPWM_CAP0_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP0_CAP_Pos)                      /*!< MCPWM CAP0: CAP Mask                */
-
-// ---------------------------------------  MCPWM_CAP1  -------------------------------------------
-#define MCPWM_CAP1_CAP_Pos                                    0                                                         /*!< MCPWM CAP1: CAP Position            */
-#define MCPWM_CAP1_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP1_CAP_Pos)                      /*!< MCPWM CAP1: CAP Mask                */
-
-// ---------------------------------------  MCPWM_CAP2  -------------------------------------------
-#define MCPWM_CAP2_CAP_Pos                                    0                                                         /*!< MCPWM CAP2: CAP Position            */
-#define MCPWM_CAP2_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP2_CAP_Pos)                      /*!< MCPWM CAP2: CAP Mask                */
-
-// ---------------------------------------  MCPWM_INTEN  ------------------------------------------
-#define MCPWM_INTEN_ILIM0_Pos                                 0                                                         /*!< MCPWM INTEN: ILIM0 Position         */
-#define MCPWM_INTEN_ILIM0_Msk                                 (0x01UL << MCPWM_INTEN_ILIM0_Pos)                         /*!< MCPWM INTEN: ILIM0 Mask             */
-#define MCPWM_INTEN_IMAT0_Pos                                 1                                                         /*!< MCPWM INTEN: IMAT0 Position         */
-#define MCPWM_INTEN_IMAT0_Msk                                 (0x01UL << MCPWM_INTEN_IMAT0_Pos)                         /*!< MCPWM INTEN: IMAT0 Mask             */
-#define MCPWM_INTEN_ICAP0_Pos                                 2                                                         /*!< MCPWM INTEN: ICAP0 Position         */
-#define MCPWM_INTEN_ICAP0_Msk                                 (0x01UL << MCPWM_INTEN_ICAP0_Pos)                         /*!< MCPWM INTEN: ICAP0 Mask             */
-#define MCPWM_INTEN_ILIM1_Pos                                 4                                                         /*!< MCPWM INTEN: ILIM1 Position         */
-#define MCPWM_INTEN_ILIM1_Msk                                 (0x01UL << MCPWM_INTEN_ILIM1_Pos)                         /*!< MCPWM INTEN: ILIM1 Mask             */
-#define MCPWM_INTEN_IMAT1_Pos                                 5                                                         /*!< MCPWM INTEN: IMAT1 Position         */
-#define MCPWM_INTEN_IMAT1_Msk                                 (0x01UL << MCPWM_INTEN_IMAT1_Pos)                         /*!< MCPWM INTEN: IMAT1 Mask             */
-#define MCPWM_INTEN_ICAP1_Pos                                 6                                                         /*!< MCPWM INTEN: ICAP1 Position         */
-#define MCPWM_INTEN_ICAP1_Msk                                 (0x01UL << MCPWM_INTEN_ICAP1_Pos)                         /*!< MCPWM INTEN: ICAP1 Mask             */
-#define MCPWM_INTEN_ILIM2_Pos                                 8                                                         /*!< MCPWM INTEN: ILIM2 Position         */
-#define MCPWM_INTEN_ILIM2_Msk                                 (0x01UL << MCPWM_INTEN_ILIM2_Pos)                         /*!< MCPWM INTEN: ILIM2 Mask             */
-#define MCPWM_INTEN_IMAT2_Pos                                 9                                                         /*!< MCPWM INTEN: IMAT2 Position         */
-#define MCPWM_INTEN_IMAT2_Msk                                 (0x01UL << MCPWM_INTEN_IMAT2_Pos)                         /*!< MCPWM INTEN: IMAT2 Mask             */
-#define MCPWM_INTEN_ICAP2_Pos                                 10                                                        /*!< MCPWM INTEN: ICAP2 Position         */
-#define MCPWM_INTEN_ICAP2_Msk                                 (0x01UL << MCPWM_INTEN_ICAP2_Pos)                         /*!< MCPWM INTEN: ICAP2 Mask             */
-#define MCPWM_INTEN_ABORT_Pos                                 15                                                        /*!< MCPWM INTEN: ABORT Position         */
-#define MCPWM_INTEN_ABORT_Msk                                 (0x01UL << MCPWM_INTEN_ABORT_Pos)                         /*!< MCPWM INTEN: ABORT Mask             */
-
-// -------------------------------------  MCPWM_INTEN_SET  ----------------------------------------
-#define MCPWM_INTEN_SET_ILIM0_SET_Pos                         0                                                         /*!< MCPWM INTEN_SET: ILIM0_SET Position */
-#define MCPWM_INTEN_SET_ILIM0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM0_SET Mask     */
-#define MCPWM_INTEN_SET_IMAT0_SET_Pos                         1                                                         /*!< MCPWM INTEN_SET: IMAT0_SET Position */
-#define MCPWM_INTEN_SET_IMAT0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT0_SET Mask     */
-#define MCPWM_INTEN_SET_ICAP0_SET_Pos                         2                                                         /*!< MCPWM INTEN_SET: ICAP0_SET Position */
-#define MCPWM_INTEN_SET_ICAP0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP0_SET Mask     */
-#define MCPWM_INTEN_SET_ILIM1_SET_Pos                         4                                                         /*!< MCPWM INTEN_SET: ILIM1_SET Position */
-#define MCPWM_INTEN_SET_ILIM1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM1_SET Mask     */
-#define MCPWM_INTEN_SET_IMAT1_SET_Pos                         5                                                         /*!< MCPWM INTEN_SET: IMAT1_SET Position */
-#define MCPWM_INTEN_SET_IMAT1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT1_SET Mask     */
-#define MCPWM_INTEN_SET_ICAP1_SET_Pos                         6                                                         /*!< MCPWM INTEN_SET: ICAP1_SET Position */
-#define MCPWM_INTEN_SET_ICAP1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP1_SET Mask     */
-#define MCPWM_INTEN_SET_ILIM2_SET_Pos                         9                                                         /*!< MCPWM INTEN_SET: ILIM2_SET Position */
-#define MCPWM_INTEN_SET_ILIM2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos)                 /*!< MCPWM INTEN_SET: ILIM2_SET Mask     */
-#define MCPWM_INTEN_SET_IMAT2_SET_Pos                         10                                                        /*!< MCPWM INTEN_SET: IMAT2_SET Position */
-#define MCPWM_INTEN_SET_IMAT2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos)                 /*!< MCPWM INTEN_SET: IMAT2_SET Mask     */
-#define MCPWM_INTEN_SET_ICAP2_SET_Pos                         11                                                        /*!< MCPWM INTEN_SET: ICAP2_SET Position */
-#define MCPWM_INTEN_SET_ICAP2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos)                 /*!< MCPWM INTEN_SET: ICAP2_SET Mask     */
-#define MCPWM_INTEN_SET_ABORT_SET_Pos                         15                                                        /*!< MCPWM INTEN_SET: ABORT_SET Position */
-#define MCPWM_INTEN_SET_ABORT_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos)                 /*!< MCPWM INTEN_SET: ABORT_SET Mask     */
-
-// -------------------------------------  MCPWM_INTEN_CLR  ----------------------------------------
-#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos                         0                                                         /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */
-#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask     */
-#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos                         1                                                         /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */
-#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask     */
-#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos                         2                                                         /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */
-#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask     */
-#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos                         4                                                         /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */
-#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask     */
-#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos                         5                                                         /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */
-#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask     */
-#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos                         6                                                         /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */
-#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask     */
-#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos                         8                                                         /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */
-#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask     */
-#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos                         9                                                         /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */
-#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask     */
-#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos                         10                                                        /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */
-#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask     */
-#define MCPWM_INTEN_CLR_ABORT_CLR_Pos                         15                                                        /*!< MCPWM INTEN_CLR: ABORT_CLR Position */
-#define MCPWM_INTEN_CLR_ABORT_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos)                 /*!< MCPWM INTEN_CLR: ABORT_CLR Mask     */
-
-// --------------------------------------  MCPWM_CNTCON  ------------------------------------------
-#define MCPWM_CNTCON_TC0MCI0_RE_Pos                           0                                                         /*!< MCPWM CNTCON: TC0MCI0_RE Position   */
-#define MCPWM_CNTCON_TC0MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI0_RE Mask       */
-#define MCPWM_CNTCON_TC0MCI0_FE_Pos                           1                                                         /*!< MCPWM CNTCON: TC0MCI0_FE Position   */
-#define MCPWM_CNTCON_TC0MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI0_FE Mask       */
-#define MCPWM_CNTCON_TC0MCI1_RE_Pos                           2                                                         /*!< MCPWM CNTCON: TC0MCI1_RE Position   */
-#define MCPWM_CNTCON_TC0MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI1_RE Mask       */
-#define MCPWM_CNTCON_TC0MCI1_FE_Pos                           3                                                         /*!< MCPWM CNTCON: TC0MCI1_FE Position   */
-#define MCPWM_CNTCON_TC0MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI1_FE Mask       */
-#define MCPWM_CNTCON_TC0MCI2_RE_Pos                           4                                                         /*!< MCPWM CNTCON: TC0MCI2_RE Position   */
-#define MCPWM_CNTCON_TC0MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC0MCI2_RE Mask       */
-#define MCPWM_CNTCON_TC0MCI2_FE_Pos                           5                                                         /*!< MCPWM CNTCON: TC0MCI2_FE Position   */
-#define MCPWM_CNTCON_TC0MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC0MCI2_FE Mask       */
-#define MCPWM_CNTCON_TC1MCI0_RE_Pos                           6                                                         /*!< MCPWM CNTCON: TC1MCI0_RE Position   */
-#define MCPWM_CNTCON_TC1MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI0_RE Mask       */
-#define MCPWM_CNTCON_TC1MCI0_FE_Pos                           7                                                         /*!< MCPWM CNTCON: TC1MCI0_FE Position   */
-#define MCPWM_CNTCON_TC1MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI0_FE Mask       */
-#define MCPWM_CNTCON_TC1MCI1_RE_Pos                           8                                                         /*!< MCPWM CNTCON: TC1MCI1_RE Position   */
-#define MCPWM_CNTCON_TC1MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI1_RE Mask       */
-#define MCPWM_CNTCON_TC1MCI1_FE_Pos                           9                                                         /*!< MCPWM CNTCON: TC1MCI1_FE Position   */
-#define MCPWM_CNTCON_TC1MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI1_FE Mask       */
-#define MCPWM_CNTCON_TC1MCI2_RE_Pos                           10                                                        /*!< MCPWM CNTCON: TC1MCI2_RE Position   */
-#define MCPWM_CNTCON_TC1MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC1MCI2_RE Mask       */
-#define MCPWM_CNTCON_TC1MCI2_FE_Pos                           11                                                        /*!< MCPWM CNTCON: TC1MCI2_FE Position   */
-#define MCPWM_CNTCON_TC1MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC1MCI2_FE Mask       */
-#define MCPWM_CNTCON_TC2MCI0_RE_Pos                           12                                                        /*!< MCPWM CNTCON: TC2MCI0_RE Position   */
-#define MCPWM_CNTCON_TC2MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI0_RE Mask       */
-#define MCPWM_CNTCON_TC2MCI0_FE_Pos                           13                                                        /*!< MCPWM CNTCON: TC2MCI0_FE Position   */
-#define MCPWM_CNTCON_TC2MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI0_FE Mask       */
-#define MCPWM_CNTCON_TC2MCI1_RE_Pos                           14                                                        /*!< MCPWM CNTCON: TC2MCI1_RE Position   */
-#define MCPWM_CNTCON_TC2MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI1_RE Mask       */
-#define MCPWM_CNTCON_TC2MCI1_FE_Pos                           15                                                        /*!< MCPWM CNTCON: TC2MCI1_FE Position   */
-#define MCPWM_CNTCON_TC2MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI1_FE Mask       */
-#define MCPWM_CNTCON_TC2MCI2_RE_Pos                           16                                                        /*!< MCPWM CNTCON: TC2MCI2_RE Position   */
-#define MCPWM_CNTCON_TC2MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos)                   /*!< MCPWM CNTCON: TC2MCI2_RE Mask       */
-#define MCPWM_CNTCON_TC2MCI2_FE_Pos                           17                                                        /*!< MCPWM CNTCON: TC2MCI2_FE Position   */
-#define MCPWM_CNTCON_TC2MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos)                   /*!< MCPWM CNTCON: TC2MCI2_FE Mask       */
-#define MCPWM_CNTCON_CNTR0_Pos                                29                                                        /*!< MCPWM CNTCON: CNTR0 Position        */
-#define MCPWM_CNTCON_CNTR0_Msk                                (0x01UL << MCPWM_CNTCON_CNTR0_Pos)                        /*!< MCPWM CNTCON: CNTR0 Mask            */
-#define MCPWM_CNTCON_CNTR1_Pos                                30                                                        /*!< MCPWM CNTCON: CNTR1 Position        */
-#define MCPWM_CNTCON_CNTR1_Msk                                (0x01UL << MCPWM_CNTCON_CNTR1_Pos)                        /*!< MCPWM CNTCON: CNTR1 Mask            */
-#define MCPWM_CNTCON_CNTR2_Pos                                31                                                        /*!< MCPWM CNTCON: CNTR2 Position        */
-#define MCPWM_CNTCON_CNTR2_Msk                                (0x01UL << MCPWM_CNTCON_CNTR2_Pos)                        /*!< MCPWM CNTCON: CNTR2 Mask            */
-
-// ------------------------------------  MCPWM_CNTCON_SET  ----------------------------------------
-#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos                   0                                                         /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */
-#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */
-#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos                   1                                                         /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */
-#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */
-#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos                   2                                                         /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */
-#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */
-#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos                   3                                                         /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */
-#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */
-#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos                   4                                                         /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */
-#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */
-#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos                   5                                                         /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */
-#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */
-#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos                   6                                                         /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */
-#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */
-#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos                   7                                                         /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */
-#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */
-#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos                   8                                                         /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */
-#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */
-#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos                   9                                                         /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */
-#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */
-#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos                   10                                                        /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */
-#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */
-#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos                   11                                                        /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */
-#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */
-#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos                   12                                                        /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */
-#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */
-#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos                   13                                                        /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */
-#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */
-#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos                   14                                                        /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */
-#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */
-#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos                   15                                                        /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */
-#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */
-#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos                   16                                                        /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */
-#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */
-#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos                   17                                                        /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */
-#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos)           /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */
-#define MCPWM_CNTCON_SET_CNTR0_SET_Pos                        29                                                        /*!< MCPWM CNTCON_SET: CNTR0_SET Position */
-#define MCPWM_CNTCON_SET_CNTR0_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR0_SET Mask    */
-#define MCPWM_CNTCON_SET_CNTR1_SET_Pos                        30                                                        /*!< MCPWM CNTCON_SET: CNTR1_SET Position */
-#define MCPWM_CNTCON_SET_CNTR1_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR1_SET Mask    */
-#define MCPWM_CNTCON_SET_CNTR2_SET_Pos                        31                                                        /*!< MCPWM CNTCON_SET: CNTR2_SET Position */
-#define MCPWM_CNTCON_SET_CNTR2_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos)                /*!< MCPWM CNTCON_SET: CNTR2_SET Mask    */
-
-// ------------------------------------  MCPWM_CNTCON_CLR  ----------------------------------------
-#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos                   0                                                         /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos                   1                                                         /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos                   2                                                         /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos                   3                                                         /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos                       4                                                         /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */
-#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk                       (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos)               /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask   */
-#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos                   5                                                         /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos                   6                                                         /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos                   7                                                         /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos                   8                                                         /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos                   9                                                         /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos                   10                                                        /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos                   11                                                        /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos                   12                                                        /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos                   13                                                        /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos                   14                                                        /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos                   15                                                        /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos                   16                                                        /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */
-#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos                   17                                                        /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */
-#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos)           /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */
-#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos                        29                                                        /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */
-#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask    */
-#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos                        30                                                        /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */
-#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask    */
-#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos                        31                                                        /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */
-#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos)                /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask    */
-
-// ---------------------------------------  MCPWM_INTF  -------------------------------------------
-#define MCPWM_INTF_ILIM0_F_Pos                                0                                                         /*!< MCPWM INTF: ILIM0_F Position        */
-#define MCPWM_INTF_ILIM0_F_Msk                                (0x01UL << MCPWM_INTF_ILIM0_F_Pos)                        /*!< MCPWM INTF: ILIM0_F Mask            */
-#define MCPWM_INTF_IMAT0_F_Pos                                1                                                         /*!< MCPWM INTF: IMAT0_F Position        */
-#define MCPWM_INTF_IMAT0_F_Msk                                (0x01UL << MCPWM_INTF_IMAT0_F_Pos)                        /*!< MCPWM INTF: IMAT0_F Mask            */
-#define MCPWM_INTF_ICAP0_F_Pos                                2                                                         /*!< MCPWM INTF: ICAP0_F Position        */
-#define MCPWM_INTF_ICAP0_F_Msk                                (0x01UL << MCPWM_INTF_ICAP0_F_Pos)                        /*!< MCPWM INTF: ICAP0_F Mask            */
-#define MCPWM_INTF_ILIM1_F_Pos                                4                                                         /*!< MCPWM INTF: ILIM1_F Position        */
-#define MCPWM_INTF_ILIM1_F_Msk                                (0x01UL << MCPWM_INTF_ILIM1_F_Pos)                        /*!< MCPWM INTF: ILIM1_F Mask            */
-#define MCPWM_INTF_IMAT1_F_Pos                                5                                                         /*!< MCPWM INTF: IMAT1_F Position        */
-#define MCPWM_INTF_IMAT1_F_Msk                                (0x01UL << MCPWM_INTF_IMAT1_F_Pos)                        /*!< MCPWM INTF: IMAT1_F Mask            */
-#define MCPWM_INTF_ICAP1_F_Pos                                6                                                         /*!< MCPWM INTF: ICAP1_F Position        */
-#define MCPWM_INTF_ICAP1_F_Msk                                (0x01UL << MCPWM_INTF_ICAP1_F_Pos)                        /*!< MCPWM INTF: ICAP1_F Mask            */
-#define MCPWM_INTF_ILIM2_F_Pos                                8                                                         /*!< MCPWM INTF: ILIM2_F Position        */
-#define MCPWM_INTF_ILIM2_F_Msk                                (0x01UL << MCPWM_INTF_ILIM2_F_Pos)                        /*!< MCPWM INTF: ILIM2_F Mask            */
-#define MCPWM_INTF_IMAT2_F_Pos                                9                                                         /*!< MCPWM INTF: IMAT2_F Position        */
-#define MCPWM_INTF_IMAT2_F_Msk                                (0x01UL << MCPWM_INTF_IMAT2_F_Pos)                        /*!< MCPWM INTF: IMAT2_F Mask            */
-#define MCPWM_INTF_ICAP2_F_Pos                                10                                                        /*!< MCPWM INTF: ICAP2_F Position        */
-#define MCPWM_INTF_ICAP2_F_Msk                                (0x01UL << MCPWM_INTF_ICAP2_F_Pos)                        /*!< MCPWM INTF: ICAP2_F Mask            */
-#define MCPWM_INTF_ABORT_F_Pos                                15                                                        /*!< MCPWM INTF: ABORT_F Position        */
-#define MCPWM_INTF_ABORT_F_Msk                                (0x01UL << MCPWM_INTF_ABORT_F_Pos)                        /*!< MCPWM INTF: ABORT_F Mask            */
-
-// -------------------------------------  MCPWM_INTF_SET  -----------------------------------------
-#define MCPWM_INTF_SET_ILIM0_F_SET_Pos                        0                                                         /*!< MCPWM INTF_SET: ILIM0_F_SET Position */
-#define MCPWM_INTF_SET_ILIM0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM0_F_SET Mask    */
-#define MCPWM_INTF_SET_IMAT0_F_SET_Pos                        1                                                         /*!< MCPWM INTF_SET: IMAT0_F_SET Position */
-#define MCPWM_INTF_SET_IMAT0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT0_F_SET Mask    */
-#define MCPWM_INTF_SET_ICAP0_F_SET_Pos                        2                                                         /*!< MCPWM INTF_SET: ICAP0_F_SET Position */
-#define MCPWM_INTF_SET_ICAP0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP0_F_SET Mask    */
-#define MCPWM_INTF_SET_ILIM1_F_SET_Pos                        4                                                         /*!< MCPWM INTF_SET: ILIM1_F_SET Position */
-#define MCPWM_INTF_SET_ILIM1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM1_F_SET Mask    */
-#define MCPWM_INTF_SET_IMAT1_F_SET_Pos                        5                                                         /*!< MCPWM INTF_SET: IMAT1_F_SET Position */
-#define MCPWM_INTF_SET_IMAT1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT1_F_SET Mask    */
-#define MCPWM_INTF_SET_ICAP1_F_SET_Pos                        6                                                         /*!< MCPWM INTF_SET: ICAP1_F_SET Position */
-#define MCPWM_INTF_SET_ICAP1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP1_F_SET Mask    */
-#define MCPWM_INTF_SET_ILIM2_F_SET_Pos                        8                                                         /*!< MCPWM INTF_SET: ILIM2_F_SET Position */
-#define MCPWM_INTF_SET_ILIM2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos)                /*!< MCPWM INTF_SET: ILIM2_F_SET Mask    */
-#define MCPWM_INTF_SET_IMAT2_F_SET_Pos                        9                                                         /*!< MCPWM INTF_SET: IMAT2_F_SET Position */
-#define MCPWM_INTF_SET_IMAT2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos)                /*!< MCPWM INTF_SET: IMAT2_F_SET Mask    */
-#define MCPWM_INTF_SET_ICAP2_F_SET_Pos                        10                                                        /*!< MCPWM INTF_SET: ICAP2_F_SET Position */
-#define MCPWM_INTF_SET_ICAP2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos)                /*!< MCPWM INTF_SET: ICAP2_F_SET Mask    */
-#define MCPWM_INTF_SET_ABORT_F_SET_Pos                        15                                                        /*!< MCPWM INTF_SET: ABORT_F_SET Position */
-#define MCPWM_INTF_SET_ABORT_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos)                /*!< MCPWM INTF_SET: ABORT_F_SET Mask    */
-
-// -------------------------------------  MCPWM_INTF_CLR  -----------------------------------------
-#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos                        0                                                         /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */
-#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask    */
-#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos                        1                                                         /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */
-#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask    */
-#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos                        2                                                         /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */
-#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask    */
-#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos                        4                                                         /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */
-#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask    */
-#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos                        5                                                         /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */
-#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask    */
-#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos                        6                                                         /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */
-#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask    */
-#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos                        8                                                         /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */
-#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask    */
-#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos                        9                                                         /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */
-#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask    */
-#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos                        10                                                        /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */
-#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask    */
-#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos                        15                                                        /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */
-#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos)                /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask    */
-
-// --------------------------------------  MCPWM_CAP_CLR  -----------------------------------------
-#define MCPWM_CAP_CLR_CAP_CLR0_Pos                            0                                                         /*!< MCPWM CAP_CLR: CAP_CLR0 Position    */
-#define MCPWM_CAP_CLR_CAP_CLR0_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR0 Mask        */
-#define MCPWM_CAP_CLR_CAP_CLR1_Pos                            1                                                         /*!< MCPWM CAP_CLR: CAP_CLR1 Position    */
-#define MCPWM_CAP_CLR_CAP_CLR1_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR1 Mask        */
-#define MCPWM_CAP_CLR_CAP_CLR2_Pos                            2                                                         /*!< MCPWM CAP_CLR: CAP_CLR2 Position    */
-#define MCPWM_CAP_CLR_CAP_CLR2_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos)                    /*!< MCPWM CAP_CLR: CAP_CLR2 Mask        */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 I2C0 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  I2C0_CONSET  ------------------------------------------
-#define I2C0_CONSET_AA_Pos                                    2                                                         /*!< I2C0 CONSET: AA Position            */
-#define I2C0_CONSET_AA_Msk                                    (0x01UL << I2C0_CONSET_AA_Pos)                            /*!< I2C0 CONSET: AA Mask                */
-#define I2C0_CONSET_SI_Pos                                    3                                                         /*!< I2C0 CONSET: SI Position            */
-#define I2C0_CONSET_SI_Msk                                    (0x01UL << I2C0_CONSET_SI_Pos)                            /*!< I2C0 CONSET: SI Mask                */
-#define I2C0_CONSET_STO_Pos                                   4                                                         /*!< I2C0 CONSET: STO Position           */
-#define I2C0_CONSET_STO_Msk                                   (0x01UL << I2C0_CONSET_STO_Pos)                           /*!< I2C0 CONSET: STO Mask               */
-#define I2C0_CONSET_STA_Pos                                   5                                                         /*!< I2C0 CONSET: STA Position           */
-#define I2C0_CONSET_STA_Msk                                   (0x01UL << I2C0_CONSET_STA_Pos)                           /*!< I2C0 CONSET: STA Mask               */
-#define I2C0_CONSET_I2EN_Pos                                  6                                                         /*!< I2C0 CONSET: I2EN Position          */
-#define I2C0_CONSET_I2EN_Msk                                  (0x01UL << I2C0_CONSET_I2EN_Pos)                          /*!< I2C0 CONSET: I2EN Mask              */
-
-// ----------------------------------------  I2C0_STAT  -------------------------------------------
-#define I2C0_STAT_Status_Pos                                  3                                                         /*!< I2C0 STAT: Status Position          */
-#define I2C0_STAT_Status_Msk                                  (0x1fUL << I2C0_STAT_Status_Pos)                          /*!< I2C0 STAT: Status Mask              */
-
-// ----------------------------------------  I2C0_DAT  --------------------------------------------
-#define I2C0_DAT_Data_Pos                                     0                                                         /*!< I2C0 DAT: Data Position             */
-#define I2C0_DAT_Data_Msk                                     (0x000000ffUL << I2C0_DAT_Data_Pos)                       /*!< I2C0 DAT: Data Mask                 */
-
-// ----------------------------------------  I2C0_ADR0  -------------------------------------------
-#define I2C0_ADR0_GC_Pos                                      0                                                         /*!< I2C0 ADR0: GC Position              */
-#define I2C0_ADR0_GC_Msk                                      (0x01UL << I2C0_ADR0_GC_Pos)                              /*!< I2C0 ADR0: GC Mask                  */
-#define I2C0_ADR0_Address_Pos                                 1                                                         /*!< I2C0 ADR0: Address Position         */
-#define I2C0_ADR0_Address_Msk                                 (0x7fUL << I2C0_ADR0_Address_Pos)                         /*!< I2C0 ADR0: Address Mask             */
-
-// ----------------------------------------  I2C0_SCLH  -------------------------------------------
-#define I2C0_SCLH_SCLH_Pos                                    0                                                         /*!< I2C0 SCLH: SCLH Position            */
-#define I2C0_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C0_SCLH_SCLH_Pos)                      /*!< I2C0 SCLH: SCLH Mask                */
-
-// ----------------------------------------  I2C0_SCLL  -------------------------------------------
-#define I2C0_SCLL_SCLL_Pos                                    0                                                         /*!< I2C0 SCLL: SCLL Position            */
-#define I2C0_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C0_SCLL_SCLL_Pos)                      /*!< I2C0 SCLL: SCLL Mask                */
-
-// ---------------------------------------  I2C0_CONCLR  ------------------------------------------
-#define I2C0_CONCLR_AAC_Pos                                   2                                                         /*!< I2C0 CONCLR: AAC Position           */
-#define I2C0_CONCLR_AAC_Msk                                   (0x01UL << I2C0_CONCLR_AAC_Pos)                           /*!< I2C0 CONCLR: AAC Mask               */
-#define I2C0_CONCLR_SIC_Pos                                   3                                                         /*!< I2C0 CONCLR: SIC Position           */
-#define I2C0_CONCLR_SIC_Msk                                   (0x01UL << I2C0_CONCLR_SIC_Pos)                           /*!< I2C0 CONCLR: SIC Mask               */
-#define I2C0_CONCLR_STAC_Pos                                  5                                                         /*!< I2C0 CONCLR: STAC Position          */
-#define I2C0_CONCLR_STAC_Msk                                  (0x01UL << I2C0_CONCLR_STAC_Pos)                          /*!< I2C0 CONCLR: STAC Mask              */
-#define I2C0_CONCLR_I2ENC_Pos                                 6                                                         /*!< I2C0 CONCLR: I2ENC Position         */
-#define I2C0_CONCLR_I2ENC_Msk                                 (0x01UL << I2C0_CONCLR_I2ENC_Pos)                         /*!< I2C0 CONCLR: I2ENC Mask             */
-
-// ---------------------------------------  I2C0_MMCTRL  ------------------------------------------
-#define I2C0_MMCTRL_MM_ENA_Pos                                0                                                         /*!< I2C0 MMCTRL: MM_ENA Position        */
-#define I2C0_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C0_MMCTRL_MM_ENA_Pos)                        /*!< I2C0 MMCTRL: MM_ENA Mask            */
-#define I2C0_MMCTRL_ENA_SCL_Pos                               1                                                         /*!< I2C0 MMCTRL: ENA_SCL Position       */
-#define I2C0_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos)                       /*!< I2C0 MMCTRL: ENA_SCL Mask           */
-#define I2C0_MMCTRL_MATCH_ALL_Pos                             2                                                         /*!< I2C0 MMCTRL: MATCH_ALL Position     */
-#define I2C0_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos)                     /*!< I2C0 MMCTRL: MATCH_ALL Mask         */
-
-// ----------------------------------------  I2C0_ADR1  -------------------------------------------
-#define I2C0_ADR1_GC_Pos                                      0                                                         /*!< I2C0 ADR1: GC Position              */
-#define I2C0_ADR1_GC_Msk                                      (0x01UL << I2C0_ADR1_GC_Pos)                              /*!< I2C0 ADR1: GC Mask                  */
-#define I2C0_ADR1_Address_Pos                                 1                                                         /*!< I2C0 ADR1: Address Position         */
-#define I2C0_ADR1_Address_Msk                                 (0x7fUL << I2C0_ADR1_Address_Pos)                         /*!< I2C0 ADR1: Address Mask             */
-
-// ----------------------------------------  I2C0_ADR2  -------------------------------------------
-#define I2C0_ADR2_GC_Pos                                      0                                                         /*!< I2C0 ADR2: GC Position              */
-#define I2C0_ADR2_GC_Msk                                      (0x01UL << I2C0_ADR2_GC_Pos)                              /*!< I2C0 ADR2: GC Mask                  */
-#define I2C0_ADR2_Address_Pos                                 1                                                         /*!< I2C0 ADR2: Address Position         */
-#define I2C0_ADR2_Address_Msk                                 (0x7fUL << I2C0_ADR2_Address_Pos)                         /*!< I2C0 ADR2: Address Mask             */
-
-// ----------------------------------------  I2C0_ADR3  -------------------------------------------
-#define I2C0_ADR3_GC_Pos                                      0                                                         /*!< I2C0 ADR3: GC Position              */
-#define I2C0_ADR3_GC_Msk                                      (0x01UL << I2C0_ADR3_GC_Pos)                              /*!< I2C0 ADR3: GC Mask                  */
-#define I2C0_ADR3_Address_Pos                                 1                                                         /*!< I2C0 ADR3: Address Position         */
-#define I2C0_ADR3_Address_Msk                                 (0x7fUL << I2C0_ADR3_Address_Pos)                         /*!< I2C0 ADR3: Address Mask             */
-
-// ------------------------------------  I2C0_DATA_BUFFER  ----------------------------------------
-#define I2C0_DATA_BUFFER_Data_Pos                             0                                                         /*!< I2C0 DATA_BUFFER: Data Position     */
-#define I2C0_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos)               /*!< I2C0 DATA_BUFFER: Data Mask         */
-
-// ---------------------------------------  I2C0_MASK0  -------------------------------------------
-#define I2C0_MASK0_MASK_Pos                                   1                                                         /*!< I2C0 MASK0: MASK Position           */
-#define I2C0_MASK0_MASK_Msk                                   (0x7fUL << I2C0_MASK0_MASK_Pos)                           /*!< I2C0 MASK0: MASK Mask               */
-
-// ---------------------------------------  I2C0_MASK1  -------------------------------------------
-#define I2C0_MASK1_MASK_Pos                                   1                                                         /*!< I2C0 MASK1: MASK Position           */
-#define I2C0_MASK1_MASK_Msk                                   (0x7fUL << I2C0_MASK1_MASK_Pos)                           /*!< I2C0 MASK1: MASK Mask               */
-
-// ---------------------------------------  I2C0_MASK2  -------------------------------------------
-#define I2C0_MASK2_MASK_Pos                                   1                                                         /*!< I2C0 MASK2: MASK Position           */
-#define I2C0_MASK2_MASK_Msk                                   (0x7fUL << I2C0_MASK2_MASK_Pos)                           /*!< I2C0 MASK2: MASK Mask               */
-
-// ---------------------------------------  I2C0_MASK3  -------------------------------------------
-#define I2C0_MASK3_MASK_Pos                                   1                                                         /*!< I2C0 MASK3: MASK Position           */
-#define I2C0_MASK3_MASK_Msk                                   (0x7fUL << I2C0_MASK3_MASK_Pos)                           /*!< I2C0 MASK3: MASK Mask               */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 I2C1 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  I2C1_CONSET  ------------------------------------------
-#define I2C1_CONSET_AA_Pos                                    2                                                         /*!< I2C1 CONSET: AA Position            */
-#define I2C1_CONSET_AA_Msk                                    (0x01UL << I2C1_CONSET_AA_Pos)                            /*!< I2C1 CONSET: AA Mask                */
-#define I2C1_CONSET_SI_Pos                                    3                                                         /*!< I2C1 CONSET: SI Position            */
-#define I2C1_CONSET_SI_Msk                                    (0x01UL << I2C1_CONSET_SI_Pos)                            /*!< I2C1 CONSET: SI Mask                */
-#define I2C1_CONSET_STO_Pos                                   4                                                         /*!< I2C1 CONSET: STO Position           */
-#define I2C1_CONSET_STO_Msk                                   (0x01UL << I2C1_CONSET_STO_Pos)                           /*!< I2C1 CONSET: STO Mask               */
-#define I2C1_CONSET_STA_Pos                                   5                                                         /*!< I2C1 CONSET: STA Position           */
-#define I2C1_CONSET_STA_Msk                                   (0x01UL << I2C1_CONSET_STA_Pos)                           /*!< I2C1 CONSET: STA Mask               */
-#define I2C1_CONSET_I2EN_Pos                                  6                                                         /*!< I2C1 CONSET: I2EN Position          */
-#define I2C1_CONSET_I2EN_Msk                                  (0x01UL << I2C1_CONSET_I2EN_Pos)                          /*!< I2C1 CONSET: I2EN Mask              */
-
-// ----------------------------------------  I2C1_STAT  -------------------------------------------
-#define I2C1_STAT_Status_Pos                                  3                                                         /*!< I2C1 STAT: Status Position          */
-#define I2C1_STAT_Status_Msk                                  (0x1fUL << I2C1_STAT_Status_Pos)                          /*!< I2C1 STAT: Status Mask              */
-
-// ----------------------------------------  I2C1_DAT  --------------------------------------------
-#define I2C1_DAT_Data_Pos                                     0                                                         /*!< I2C1 DAT: Data Position             */
-#define I2C1_DAT_Data_Msk                                     (0x000000ffUL << I2C1_DAT_Data_Pos)                       /*!< I2C1 DAT: Data Mask                 */
-
-// ----------------------------------------  I2C1_ADR0  -------------------------------------------
-#define I2C1_ADR0_GC_Pos                                      0                                                         /*!< I2C1 ADR0: GC Position              */
-#define I2C1_ADR0_GC_Msk                                      (0x01UL << I2C1_ADR0_GC_Pos)                              /*!< I2C1 ADR0: GC Mask                  */
-#define I2C1_ADR0_Address_Pos                                 1                                                         /*!< I2C1 ADR0: Address Position         */
-#define I2C1_ADR0_Address_Msk                                 (0x7fUL << I2C1_ADR0_Address_Pos)                         /*!< I2C1 ADR0: Address Mask             */
-
-// ----------------------------------------  I2C1_SCLH  -------------------------------------------
-#define I2C1_SCLH_SCLH_Pos                                    0                                                         /*!< I2C1 SCLH: SCLH Position            */
-#define I2C1_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C1_SCLH_SCLH_Pos)                      /*!< I2C1 SCLH: SCLH Mask                */
-
-// ----------------------------------------  I2C1_SCLL  -------------------------------------------
-#define I2C1_SCLL_SCLL_Pos                                    0                                                         /*!< I2C1 SCLL: SCLL Position            */
-#define I2C1_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C1_SCLL_SCLL_Pos)                      /*!< I2C1 SCLL: SCLL Mask                */
-
-// ---------------------------------------  I2C1_CONCLR  ------------------------------------------
-#define I2C1_CONCLR_AAC_Pos                                   2                                                         /*!< I2C1 CONCLR: AAC Position           */
-#define I2C1_CONCLR_AAC_Msk                                   (0x01UL << I2C1_CONCLR_AAC_Pos)                           /*!< I2C1 CONCLR: AAC Mask               */
-#define I2C1_CONCLR_SIC_Pos                                   3                                                         /*!< I2C1 CONCLR: SIC Position           */
-#define I2C1_CONCLR_SIC_Msk                                   (0x01UL << I2C1_CONCLR_SIC_Pos)                           /*!< I2C1 CONCLR: SIC Mask               */
-#define I2C1_CONCLR_STAC_Pos                                  5                                                         /*!< I2C1 CONCLR: STAC Position          */
-#define I2C1_CONCLR_STAC_Msk                                  (0x01UL << I2C1_CONCLR_STAC_Pos)                          /*!< I2C1 CONCLR: STAC Mask              */
-#define I2C1_CONCLR_I2ENC_Pos                                 6                                                         /*!< I2C1 CONCLR: I2ENC Position         */
-#define I2C1_CONCLR_I2ENC_Msk                                 (0x01UL << I2C1_CONCLR_I2ENC_Pos)                         /*!< I2C1 CONCLR: I2ENC Mask             */
-
-// ---------------------------------------  I2C1_MMCTRL  ------------------------------------------
-#define I2C1_MMCTRL_MM_ENA_Pos                                0                                                         /*!< I2C1 MMCTRL: MM_ENA Position        */
-#define I2C1_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C1_MMCTRL_MM_ENA_Pos)                        /*!< I2C1 MMCTRL: MM_ENA Mask            */
-#define I2C1_MMCTRL_ENA_SCL_Pos                               1                                                         /*!< I2C1 MMCTRL: ENA_SCL Position       */
-#define I2C1_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos)                       /*!< I2C1 MMCTRL: ENA_SCL Mask           */
-#define I2C1_MMCTRL_MATCH_ALL_Pos                             2                                                         /*!< I2C1 MMCTRL: MATCH_ALL Position     */
-#define I2C1_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos)                     /*!< I2C1 MMCTRL: MATCH_ALL Mask         */
-
-// ----------------------------------------  I2C1_ADR1  -------------------------------------------
-#define I2C1_ADR1_GC_Pos                                      0                                                         /*!< I2C1 ADR1: GC Position              */
-#define I2C1_ADR1_GC_Msk                                      (0x01UL << I2C1_ADR1_GC_Pos)                              /*!< I2C1 ADR1: GC Mask                  */
-#define I2C1_ADR1_Address_Pos                                 1                                                         /*!< I2C1 ADR1: Address Position         */
-#define I2C1_ADR1_Address_Msk                                 (0x7fUL << I2C1_ADR1_Address_Pos)                         /*!< I2C1 ADR1: Address Mask             */
-
-// ----------------------------------------  I2C1_ADR2  -------------------------------------------
-#define I2C1_ADR2_GC_Pos                                      0                                                         /*!< I2C1 ADR2: GC Position              */
-#define I2C1_ADR2_GC_Msk                                      (0x01UL << I2C1_ADR2_GC_Pos)                              /*!< I2C1 ADR2: GC Mask                  */
-#define I2C1_ADR2_Address_Pos                                 1                                                         /*!< I2C1 ADR2: Address Position         */
-#define I2C1_ADR2_Address_Msk                                 (0x7fUL << I2C1_ADR2_Address_Pos)                         /*!< I2C1 ADR2: Address Mask             */
-
-// ----------------------------------------  I2C1_ADR3  -------------------------------------------
-#define I2C1_ADR3_GC_Pos                                      0                                                         /*!< I2C1 ADR3: GC Position              */
-#define I2C1_ADR3_GC_Msk                                      (0x01UL << I2C1_ADR3_GC_Pos)                              /*!< I2C1 ADR3: GC Mask                  */
-#define I2C1_ADR3_Address_Pos                                 1                                                         /*!< I2C1 ADR3: Address Position         */
-#define I2C1_ADR3_Address_Msk                                 (0x7fUL << I2C1_ADR3_Address_Pos)                         /*!< I2C1 ADR3: Address Mask             */
-
-// ------------------------------------  I2C1_DATA_BUFFER  ----------------------------------------
-#define I2C1_DATA_BUFFER_Data_Pos                             0                                                         /*!< I2C1 DATA_BUFFER: Data Position     */
-#define I2C1_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos)               /*!< I2C1 DATA_BUFFER: Data Mask         */
-
-// ---------------------------------------  I2C1_MASK0  -------------------------------------------
-#define I2C1_MASK0_MASK_Pos                                   1                                                         /*!< I2C1 MASK0: MASK Position           */
-#define I2C1_MASK0_MASK_Msk                                   (0x7fUL << I2C1_MASK0_MASK_Pos)                           /*!< I2C1 MASK0: MASK Mask               */
-
-// ---------------------------------------  I2C1_MASK1  -------------------------------------------
-#define I2C1_MASK1_MASK_Pos                                   1                                                         /*!< I2C1 MASK1: MASK Position           */
-#define I2C1_MASK1_MASK_Msk                                   (0x7fUL << I2C1_MASK1_MASK_Pos)                           /*!< I2C1 MASK1: MASK Mask               */
-
-// ---------------------------------------  I2C1_MASK2  -------------------------------------------
-#define I2C1_MASK2_MASK_Pos                                   1                                                         /*!< I2C1 MASK2: MASK Position           */
-#define I2C1_MASK2_MASK_Msk                                   (0x7fUL << I2C1_MASK2_MASK_Pos)                           /*!< I2C1 MASK2: MASK Mask               */
-
-// ---------------------------------------  I2C1_MASK3  -------------------------------------------
-#define I2C1_MASK3_MASK_Pos                                   1                                                         /*!< I2C1 MASK3: MASK Position           */
-#define I2C1_MASK3_MASK_Msk                                   (0x7fUL << I2C1_MASK3_MASK_Pos)                           /*!< I2C1 MASK3: MASK Mask               */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 I2S0 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  I2S0_DAO  --------------------------------------------
-#define I2S0_DAO_WORDWIDTH_Pos                                0                                                         /*!< I2S0 DAO: WORDWIDTH Position        */
-#define I2S0_DAO_WORDWIDTH_Msk                                (0x03UL << I2S0_DAO_WORDWIDTH_Pos)                        /*!< I2S0 DAO: WORDWIDTH Mask            */
-#define I2S0_DAO_MONO_Pos                                     2                                                         /*!< I2S0 DAO: MONO Position             */
-#define I2S0_DAO_MONO_Msk                                     (0x01UL << I2S0_DAO_MONO_Pos)                             /*!< I2S0 DAO: MONO Mask                 */
-#define I2S0_DAO_STOP_Pos                                     3                                                         /*!< I2S0 DAO: STOP Position             */
-#define I2S0_DAO_STOP_Msk                                     (0x01UL << I2S0_DAO_STOP_Pos)                             /*!< I2S0 DAO: STOP Mask                 */
-#define I2S0_DAO_RESET_Pos                                    4                                                         /*!< I2S0 DAO: RESET Position            */
-#define I2S0_DAO_RESET_Msk                                    (0x01UL << I2S0_DAO_RESET_Pos)                            /*!< I2S0 DAO: RESET Mask                */
-#define I2S0_DAO_WS_SEL_Pos                                   5                                                         /*!< I2S0 DAO: WS_SEL Position           */
-#define I2S0_DAO_WS_SEL_Msk                                   (0x01UL << I2S0_DAO_WS_SEL_Pos)                           /*!< I2S0 DAO: WS_SEL Mask               */
-#define I2S0_DAO_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S0 DAO: WS_HALFPERIOD Position    */
-#define I2S0_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos)              /*!< I2S0 DAO: WS_HALFPERIOD Mask        */
-#define I2S0_DAO_MUTE_Pos                                     15                                                        /*!< I2S0 DAO: MUTE Position             */
-#define I2S0_DAO_MUTE_Msk                                     (0x01UL << I2S0_DAO_MUTE_Pos)                             /*!< I2S0 DAO: MUTE Mask                 */
-
-// ----------------------------------------  I2S0_DAI  --------------------------------------------
-#define I2S0_DAI_WORDWIDTH_Pos                                0                                                         /*!< I2S0 DAI: WORDWIDTH Position        */
-#define I2S0_DAI_WORDWIDTH_Msk                                (0x03UL << I2S0_DAI_WORDWIDTH_Pos)                        /*!< I2S0 DAI: WORDWIDTH Mask            */
-#define I2S0_DAI_MONO_Pos                                     2                                                         /*!< I2S0 DAI: MONO Position             */
-#define I2S0_DAI_MONO_Msk                                     (0x01UL << I2S0_DAI_MONO_Pos)                             /*!< I2S0 DAI: MONO Mask                 */
-#define I2S0_DAI_STOP_Pos                                     3                                                         /*!< I2S0 DAI: STOP Position             */
-#define I2S0_DAI_STOP_Msk                                     (0x01UL << I2S0_DAI_STOP_Pos)                             /*!< I2S0 DAI: STOP Mask                 */
-#define I2S0_DAI_RESET_Pos                                    4                                                         /*!< I2S0 DAI: RESET Position            */
-#define I2S0_DAI_RESET_Msk                                    (0x01UL << I2S0_DAI_RESET_Pos)                            /*!< I2S0 DAI: RESET Mask                */
-#define I2S0_DAI_WS_SEL_Pos                                   5                                                         /*!< I2S0 DAI: WS_SEL Position           */
-#define I2S0_DAI_WS_SEL_Msk                                   (0x01UL << I2S0_DAI_WS_SEL_Pos)                           /*!< I2S0 DAI: WS_SEL Mask               */
-#define I2S0_DAI_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S0 DAI: WS_HALFPERIOD Position    */
-#define I2S0_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos)              /*!< I2S0 DAI: WS_HALFPERIOD Mask        */
-
-// ---------------------------------------  I2S0_TXFIFO  ------------------------------------------
-#define I2S0_TXFIFO_I2STXFIFO_Pos                             0                                                         /*!< I2S0 TXFIFO: I2STXFIFO Position     */
-#define I2S0_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos)               /*!< I2S0 TXFIFO: I2STXFIFO Mask         */
-
-// ---------------------------------------  I2S0_RXFIFO  ------------------------------------------
-#define I2S0_RXFIFO_I2SRXFIFO_Pos                             0                                                         /*!< I2S0 RXFIFO: I2SRXFIFO Position     */
-#define I2S0_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos)               /*!< I2S0 RXFIFO: I2SRXFIFO Mask         */
-
-// ---------------------------------------  I2S0_STATE  -------------------------------------------
-#define I2S0_STATE_IRQ_Pos                                    0                                                         /*!< I2S0 STATE: IRQ Position            */
-#define I2S0_STATE_IRQ_Msk                                    (0x01UL << I2S0_STATE_IRQ_Pos)                            /*!< I2S0 STATE: IRQ Mask                */
-#define I2S0_STATE_DMAREQ1_Pos                                1                                                         /*!< I2S0 STATE: DMAREQ1 Position        */
-#define I2S0_STATE_DMAREQ1_Msk                                (0x01UL << I2S0_STATE_DMAREQ1_Pos)                        /*!< I2S0 STATE: DMAREQ1 Mask            */
-#define I2S0_STATE_DMAREQ2_Pos                                2                                                         /*!< I2S0 STATE: DMAREQ2 Position        */
-#define I2S0_STATE_DMAREQ2_Msk                                (0x01UL << I2S0_STATE_DMAREQ2_Pos)                        /*!< I2S0 STATE: DMAREQ2 Mask            */
-#define I2S0_STATE_RX_LEVEL_Pos                               8                                                         /*!< I2S0 STATE: RX_LEVEL Position       */
-#define I2S0_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_RX_LEVEL_Pos)                       /*!< I2S0 STATE: RX_LEVEL Mask           */
-#define I2S0_STATE_TX_LEVEL_Pos                               16                                                        /*!< I2S0 STATE: TX_LEVEL Position       */
-#define I2S0_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_TX_LEVEL_Pos)                       /*!< I2S0 STATE: TX_LEVEL Mask           */
-
-// ----------------------------------------  I2S0_DMA1  -------------------------------------------
-#define I2S0_DMA1_RX_DMA1_ENABLE_Pos                          0                                                         /*!< I2S0 DMA1: RX_DMA1_ENABLE Position  */
-#define I2S0_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos)                  /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask      */
-#define I2S0_DMA1_TX_DMA1_ENABLE_Pos                          1                                                         /*!< I2S0 DMA1: TX_DMA1_ENABLE Position  */
-#define I2S0_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos)                  /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask      */
-#define I2S0_DMA1_RX_DEPTH_DMA1_Pos                           8                                                         /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position   */
-#define I2S0_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos)                   /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask       */
-#define I2S0_DMA1_TX_DEPTH_DMA1_Pos                           16                                                        /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position   */
-#define I2S0_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos)                   /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask       */
-
-// ----------------------------------------  I2S0_DMA2  -------------------------------------------
-#define I2S0_DMA2_RX_DMA2_ENABLE_Pos                          0                                                         /*!< I2S0 DMA2: RX_DMA2_ENABLE Position  */
-#define I2S0_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos)                  /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask      */
-#define I2S0_DMA2_TX_DMA2_ENABLE_Pos                          1                                                         /*!< I2S0 DMA2: TX_DMA2_ENABLE Position  */
-#define I2S0_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos)                  /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask      */
-#define I2S0_DMA2_RX_DEPTH_DMA2_Pos                           8                                                         /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position   */
-#define I2S0_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos)                   /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask       */
-#define I2S0_DMA2_TX_DEPTH_DMA2_Pos                           16                                                        /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position   */
-#define I2S0_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos)                   /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask       */
-
-// ----------------------------------------  I2S0_IRQ  --------------------------------------------
-#define I2S0_IRQ_RX_IRQ_ENABLE_Pos                            0                                                         /*!< I2S0 IRQ: RX_IRQ_ENABLE Position    */
-#define I2S0_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos)                    /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask        */
-#define I2S0_IRQ_TX_IRQ_ENABLE_Pos                            1                                                         /*!< I2S0 IRQ: TX_IRQ_ENABLE Position    */
-#define I2S0_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos)                    /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask        */
-#define I2S0_IRQ_RX_DEPTH_IRQ_Pos                             8                                                         /*!< I2S0 IRQ: RX_DEPTH_IRQ Position     */
-#define I2S0_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos)                     /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask         */
-#define I2S0_IRQ_TX_DEPTH_IRQ_Pos                             16                                                        /*!< I2S0 IRQ: TX_DEPTH_IRQ Position     */
-#define I2S0_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos)                     /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask         */
-
-// ---------------------------------------  I2S0_TXRATE  ------------------------------------------
-#define I2S0_TXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S0 TXRATE: Y_DIVIDER Position     */
-#define I2S0_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos)               /*!< I2S0 TXRATE: Y_DIVIDER Mask         */
-#define I2S0_TXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S0 TXRATE: X_DIVIDER Position     */
-#define I2S0_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos)               /*!< I2S0 TXRATE: X_DIVIDER Mask         */
-
-// ---------------------------------------  I2S0_RXRATE  ------------------------------------------
-#define I2S0_RXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S0 RXRATE: Y_DIVIDER Position     */
-#define I2S0_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos)               /*!< I2S0 RXRATE: Y_DIVIDER Mask         */
-#define I2S0_RXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S0 RXRATE: X_DIVIDER Position     */
-#define I2S0_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos)               /*!< I2S0 RXRATE: X_DIVIDER Mask         */
-
-// -------------------------------------  I2S0_TXBITRATE  -----------------------------------------
-#define I2S0_TXBITRATE_TX_BITRATE_Pos                         0                                                         /*!< I2S0 TXBITRATE: TX_BITRATE Position */
-#define I2S0_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos)                 /*!< I2S0 TXBITRATE: TX_BITRATE Mask     */
-
-// -------------------------------------  I2S0_RXBITRATE  -----------------------------------------
-#define I2S0_RXBITRATE_RX_BITRATE_Pos                         0                                                         /*!< I2S0 RXBITRATE: RX_BITRATE Position */
-#define I2S0_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos)                 /*!< I2S0 RXBITRATE: RX_BITRATE Mask     */
-
-// ---------------------------------------  I2S0_TXMODE  ------------------------------------------
-#define I2S0_TXMODE_TXCLKSEL_Pos                              0                                                         /*!< I2S0 TXMODE: TXCLKSEL Position      */
-#define I2S0_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos)                      /*!< I2S0 TXMODE: TXCLKSEL Mask          */
-#define I2S0_TXMODE_TX4PIN_Pos                                2                                                         /*!< I2S0 TXMODE: TX4PIN Position        */
-#define I2S0_TXMODE_TX4PIN_Msk                                (0x01UL << I2S0_TXMODE_TX4PIN_Pos)                        /*!< I2S0 TXMODE: TX4PIN Mask            */
-#define I2S0_TXMODE_TXMCENA_Pos                               3                                                         /*!< I2S0 TXMODE: TXMCENA Position       */
-#define I2S0_TXMODE_TXMCENA_Msk                               (0x01UL << I2S0_TXMODE_TXMCENA_Pos)                       /*!< I2S0 TXMODE: TXMCENA Mask           */
-
-// ---------------------------------------  I2S0_RXMODE  ------------------------------------------
-#define I2S0_RXMODE_RXCLKSEL_Pos                              0                                                         /*!< I2S0 RXMODE: RXCLKSEL Position      */
-#define I2S0_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos)                      /*!< I2S0 RXMODE: RXCLKSEL Mask          */
-#define I2S0_RXMODE_RX4PIN_Pos                                2                                                         /*!< I2S0 RXMODE: RX4PIN Position        */
-#define I2S0_RXMODE_RX4PIN_Msk                                (0x01UL << I2S0_RXMODE_RX4PIN_Pos)                        /*!< I2S0 RXMODE: RX4PIN Mask            */
-#define I2S0_RXMODE_RXMCENA_Pos                               3                                                         /*!< I2S0 RXMODE: RXMCENA Position       */
-#define I2S0_RXMODE_RXMCENA_Msk                               (0x01UL << I2S0_RXMODE_RXMCENA_Pos)                       /*!< I2S0 RXMODE: RXMCENA Mask           */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 I2S1 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ----------------------------------------  I2S1_DAO  --------------------------------------------
-#define I2S1_DAO_WORDWIDTH_Pos                                0                                                         /*!< I2S1 DAO: WORDWIDTH Position        */
-#define I2S1_DAO_WORDWIDTH_Msk                                (0x03UL << I2S1_DAO_WORDWIDTH_Pos)                        /*!< I2S1 DAO: WORDWIDTH Mask            */
-#define I2S1_DAO_MONO_Pos                                     2                                                         /*!< I2S1 DAO: MONO Position             */
-#define I2S1_DAO_MONO_Msk                                     (0x01UL << I2S1_DAO_MONO_Pos)                             /*!< I2S1 DAO: MONO Mask                 */
-#define I2S1_DAO_STOP_Pos                                     3                                                         /*!< I2S1 DAO: STOP Position             */
-#define I2S1_DAO_STOP_Msk                                     (0x01UL << I2S1_DAO_STOP_Pos)                             /*!< I2S1 DAO: STOP Mask                 */
-#define I2S1_DAO_RESET_Pos                                    4                                                         /*!< I2S1 DAO: RESET Position            */
-#define I2S1_DAO_RESET_Msk                                    (0x01UL << I2S1_DAO_RESET_Pos)                            /*!< I2S1 DAO: RESET Mask                */
-#define I2S1_DAO_WS_SEL_Pos                                   5                                                         /*!< I2S1 DAO: WS_SEL Position           */
-#define I2S1_DAO_WS_SEL_Msk                                   (0x01UL << I2S1_DAO_WS_SEL_Pos)                           /*!< I2S1 DAO: WS_SEL Mask               */
-#define I2S1_DAO_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S1 DAO: WS_HALFPERIOD Position    */
-#define I2S1_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos)              /*!< I2S1 DAO: WS_HALFPERIOD Mask        */
-#define I2S1_DAO_MUTE_Pos                                     15                                                        /*!< I2S1 DAO: MUTE Position             */
-#define I2S1_DAO_MUTE_Msk                                     (0x01UL << I2S1_DAO_MUTE_Pos)                             /*!< I2S1 DAO: MUTE Mask                 */
-
-// ----------------------------------------  I2S1_DAI  --------------------------------------------
-#define I2S1_DAI_WORDWIDTH_Pos                                0                                                         /*!< I2S1 DAI: WORDWIDTH Position        */
-#define I2S1_DAI_WORDWIDTH_Msk                                (0x03UL << I2S1_DAI_WORDWIDTH_Pos)                        /*!< I2S1 DAI: WORDWIDTH Mask            */
-#define I2S1_DAI_MONO_Pos                                     2                                                         /*!< I2S1 DAI: MONO Position             */
-#define I2S1_DAI_MONO_Msk                                     (0x01UL << I2S1_DAI_MONO_Pos)                             /*!< I2S1 DAI: MONO Mask                 */
-#define I2S1_DAI_STOP_Pos                                     3                                                         /*!< I2S1 DAI: STOP Position             */
-#define I2S1_DAI_STOP_Msk                                     (0x01UL << I2S1_DAI_STOP_Pos)                             /*!< I2S1 DAI: STOP Mask                 */
-#define I2S1_DAI_RESET_Pos                                    4                                                         /*!< I2S1 DAI: RESET Position            */
-#define I2S1_DAI_RESET_Msk                                    (0x01UL << I2S1_DAI_RESET_Pos)                            /*!< I2S1 DAI: RESET Mask                */
-#define I2S1_DAI_WS_SEL_Pos                                   5                                                         /*!< I2S1 DAI: WS_SEL Position           */
-#define I2S1_DAI_WS_SEL_Msk                                   (0x01UL << I2S1_DAI_WS_SEL_Pos)                           /*!< I2S1 DAI: WS_SEL Mask               */
-#define I2S1_DAI_WS_HALFPERIOD_Pos                            6                                                         /*!< I2S1 DAI: WS_HALFPERIOD Position    */
-#define I2S1_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos)              /*!< I2S1 DAI: WS_HALFPERIOD Mask        */
-
-// ---------------------------------------  I2S1_TXFIFO  ------------------------------------------
-#define I2S1_TXFIFO_I2STXFIFO_Pos                             0                                                         /*!< I2S1 TXFIFO: I2STXFIFO Position     */
-#define I2S1_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos)               /*!< I2S1 TXFIFO: I2STXFIFO Mask         */
-
-// ---------------------------------------  I2S1_RXFIFO  ------------------------------------------
-#define I2S1_RXFIFO_I2SRXFIFO_Pos                             0                                                         /*!< I2S1 RXFIFO: I2SRXFIFO Position     */
-#define I2S1_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos)               /*!< I2S1 RXFIFO: I2SRXFIFO Mask         */
-
-// ---------------------------------------  I2S1_STATE  -------------------------------------------
-#define I2S1_STATE_IRQ_Pos                                    0                                                         /*!< I2S1 STATE: IRQ Position            */
-#define I2S1_STATE_IRQ_Msk                                    (0x01UL << I2S1_STATE_IRQ_Pos)                            /*!< I2S1 STATE: IRQ Mask                */
-#define I2S1_STATE_DMAREQ1_Pos                                1                                                         /*!< I2S1 STATE: DMAREQ1 Position        */
-#define I2S1_STATE_DMAREQ1_Msk                                (0x01UL << I2S1_STATE_DMAREQ1_Pos)                        /*!< I2S1 STATE: DMAREQ1 Mask            */
-#define I2S1_STATE_DMAREQ2_Pos                                2                                                         /*!< I2S1 STATE: DMAREQ2 Position        */
-#define I2S1_STATE_DMAREQ2_Msk                                (0x01UL << I2S1_STATE_DMAREQ2_Pos)                        /*!< I2S1 STATE: DMAREQ2 Mask            */
-#define I2S1_STATE_RX_LEVEL_Pos                               8                                                         /*!< I2S1 STATE: RX_LEVEL Position       */
-#define I2S1_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_RX_LEVEL_Pos)                       /*!< I2S1 STATE: RX_LEVEL Mask           */
-#define I2S1_STATE_TX_LEVEL_Pos                               16                                                        /*!< I2S1 STATE: TX_LEVEL Position       */
-#define I2S1_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_TX_LEVEL_Pos)                       /*!< I2S1 STATE: TX_LEVEL Mask           */
-
-// ----------------------------------------  I2S1_DMA1  -------------------------------------------
-#define I2S1_DMA1_RX_DMA1_ENABLE_Pos                          0                                                         /*!< I2S1 DMA1: RX_DMA1_ENABLE Position  */
-#define I2S1_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos)                  /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask      */
-#define I2S1_DMA1_TX_DMA1_ENABLE_Pos                          1                                                         /*!< I2S1 DMA1: TX_DMA1_ENABLE Position  */
-#define I2S1_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos)                  /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask      */
-#define I2S1_DMA1_RX_DEPTH_DMA1_Pos                           8                                                         /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position   */
-#define I2S1_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos)                   /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask       */
-#define I2S1_DMA1_TX_DEPTH_DMA1_Pos                           16                                                        /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position   */
-#define I2S1_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos)                   /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask       */
-
-// ----------------------------------------  I2S1_DMA2  -------------------------------------------
-#define I2S1_DMA2_RX_DMA2_ENABLE_Pos                          0                                                         /*!< I2S1 DMA2: RX_DMA2_ENABLE Position  */
-#define I2S1_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos)                  /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask      */
-#define I2S1_DMA2_TX_DMA2_ENABLE_Pos                          1                                                         /*!< I2S1 DMA2: TX_DMA2_ENABLE Position  */
-#define I2S1_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos)                  /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask      */
-#define I2S1_DMA2_RX_DEPTH_DMA2_Pos                           8                                                         /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position   */
-#define I2S1_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos)                   /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask       */
-#define I2S1_DMA2_TX_DEPTH_DMA2_Pos                           16                                                        /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position   */
-#define I2S1_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos)                   /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask       */
-
-// ----------------------------------------  I2S1_IRQ  --------------------------------------------
-#define I2S1_IRQ_RX_IRQ_ENABLE_Pos                            0                                                         /*!< I2S1 IRQ: RX_IRQ_ENABLE Position    */
-#define I2S1_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos)                    /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask        */
-#define I2S1_IRQ_TX_IRQ_ENABLE_Pos                            1                                                         /*!< I2S1 IRQ: TX_IRQ_ENABLE Position    */
-#define I2S1_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos)                    /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask        */
-#define I2S1_IRQ_RX_DEPTH_IRQ_Pos                             8                                                         /*!< I2S1 IRQ: RX_DEPTH_IRQ Position     */
-#define I2S1_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos)                     /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask         */
-#define I2S1_IRQ_TX_DEPTH_IRQ_Pos                             16                                                        /*!< I2S1 IRQ: TX_DEPTH_IRQ Position     */
-#define I2S1_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos)                     /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask         */
-
-// ---------------------------------------  I2S1_TXRATE  ------------------------------------------
-#define I2S1_TXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S1 TXRATE: Y_DIVIDER Position     */
-#define I2S1_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos)               /*!< I2S1 TXRATE: Y_DIVIDER Mask         */
-#define I2S1_TXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S1 TXRATE: X_DIVIDER Position     */
-#define I2S1_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos)               /*!< I2S1 TXRATE: X_DIVIDER Mask         */
-
-// ---------------------------------------  I2S1_RXRATE  ------------------------------------------
-#define I2S1_RXRATE_Y_DIVIDER_Pos                             0                                                         /*!< I2S1 RXRATE: Y_DIVIDER Position     */
-#define I2S1_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos)               /*!< I2S1 RXRATE: Y_DIVIDER Mask         */
-#define I2S1_RXRATE_X_DIVIDER_Pos                             8                                                         /*!< I2S1 RXRATE: X_DIVIDER Position     */
-#define I2S1_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos)               /*!< I2S1 RXRATE: X_DIVIDER Mask         */
-
-// -------------------------------------  I2S1_TXBITRATE  -----------------------------------------
-#define I2S1_TXBITRATE_TX_BITRATE_Pos                         0                                                         /*!< I2S1 TXBITRATE: TX_BITRATE Position */
-#define I2S1_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos)                 /*!< I2S1 TXBITRATE: TX_BITRATE Mask     */
-
-// -------------------------------------  I2S1_RXBITRATE  -----------------------------------------
-#define I2S1_RXBITRATE_RX_BITRATE_Pos                         0                                                         /*!< I2S1 RXBITRATE: RX_BITRATE Position */
-#define I2S1_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos)                 /*!< I2S1 RXBITRATE: RX_BITRATE Mask     */
-
-// ---------------------------------------  I2S1_TXMODE  ------------------------------------------
-#define I2S1_TXMODE_TXCLKSEL_Pos                              0                                                         /*!< I2S1 TXMODE: TXCLKSEL Position      */
-#define I2S1_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos)                      /*!< I2S1 TXMODE: TXCLKSEL Mask          */
-#define I2S1_TXMODE_TX4PIN_Pos                                2                                                         /*!< I2S1 TXMODE: TX4PIN Position        */
-#define I2S1_TXMODE_TX4PIN_Msk                                (0x01UL << I2S1_TXMODE_TX4PIN_Pos)                        /*!< I2S1 TXMODE: TX4PIN Mask            */
-#define I2S1_TXMODE_TXMCENA_Pos                               3                                                         /*!< I2S1 TXMODE: TXMCENA Position       */
-#define I2S1_TXMODE_TXMCENA_Msk                               (0x01UL << I2S1_TXMODE_TXMCENA_Pos)                       /*!< I2S1 TXMODE: TXMCENA Mask           */
-
-// ---------------------------------------  I2S1_RXMODE  ------------------------------------------
-#define I2S1_RXMODE_RXCLKSEL_Pos                              0                                                         /*!< I2S1 RXMODE: RXCLKSEL Position      */
-#define I2S1_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos)                      /*!< I2S1 RXMODE: RXCLKSEL Mask          */
-#define I2S1_RXMODE_RX4PIN_Pos                                2                                                         /*!< I2S1 RXMODE: RX4PIN Position        */
-#define I2S1_RXMODE_RX4PIN_Msk                                (0x01UL << I2S1_RXMODE_RX4PIN_Pos)                        /*!< I2S1 RXMODE: RX4PIN Mask            */
-#define I2S1_RXMODE_RXMCENA_Pos                               3                                                         /*!< I2S1 RXMODE: RXMCENA Position       */
-#define I2S1_RXMODE_RXMCENA_Msk                               (0x01UL << I2S1_RXMODE_RXMCENA_Pos)                       /*!< I2S1 RXMODE: RXMCENA Mask           */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                C_CAN1 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  C_CAN1_CNTL  ------------------------------------------
-#define C_CAN1_CNTL_INIT_Pos                                  0                                                         /*!< C_CAN1 CNTL: INIT Position          */
-#define C_CAN1_CNTL_INIT_Msk                                  (0x01UL << C_CAN1_CNTL_INIT_Pos)                          /*!< C_CAN1 CNTL: INIT Mask              */
-#define C_CAN1_CNTL_IE_Pos                                    1                                                         /*!< C_CAN1 CNTL: IE Position            */
-#define C_CAN1_CNTL_IE_Msk                                    (0x01UL << C_CAN1_CNTL_IE_Pos)                            /*!< C_CAN1 CNTL: IE Mask                */
-#define C_CAN1_CNTL_SIE_Pos                                   2                                                         /*!< C_CAN1 CNTL: SIE Position           */
-#define C_CAN1_CNTL_SIE_Msk                                   (0x01UL << C_CAN1_CNTL_SIE_Pos)                           /*!< C_CAN1 CNTL: SIE Mask               */
-#define C_CAN1_CNTL_EIE_Pos                                   3                                                         /*!< C_CAN1 CNTL: EIE Position           */
-#define C_CAN1_CNTL_EIE_Msk                                   (0x01UL << C_CAN1_CNTL_EIE_Pos)                           /*!< C_CAN1 CNTL: EIE Mask               */
-#define C_CAN1_CNTL_DAR_Pos                                   5                                                         /*!< C_CAN1 CNTL: DAR Position           */
-#define C_CAN1_CNTL_DAR_Msk                                   (0x01UL << C_CAN1_CNTL_DAR_Pos)                           /*!< C_CAN1 CNTL: DAR Mask               */
-#define C_CAN1_CNTL_CCE_Pos                                   6                                                         /*!< C_CAN1 CNTL: CCE Position           */
-#define C_CAN1_CNTL_CCE_Msk                                   (0x01UL << C_CAN1_CNTL_CCE_Pos)                           /*!< C_CAN1 CNTL: CCE Mask               */
-#define C_CAN1_CNTL_TEST_Pos                                  7                                                         /*!< C_CAN1 CNTL: TEST Position          */
-#define C_CAN1_CNTL_TEST_Msk                                  (0x01UL << C_CAN1_CNTL_TEST_Pos)                          /*!< C_CAN1 CNTL: TEST Mask              */
-
-// ---------------------------------------  C_CAN1_STAT  ------------------------------------------
-#define C_CAN1_STAT_LEC_Pos                                   0                                                         /*!< C_CAN1 STAT: LEC Position           */
-#define C_CAN1_STAT_LEC_Msk                                   (0x07UL << C_CAN1_STAT_LEC_Pos)                           /*!< C_CAN1 STAT: LEC Mask               */
-#define C_CAN1_STAT_TXOK_Pos                                  3                                                         /*!< C_CAN1 STAT: TXOK Position          */
-#define C_CAN1_STAT_TXOK_Msk                                  (0x01UL << C_CAN1_STAT_TXOK_Pos)                          /*!< C_CAN1 STAT: TXOK Mask              */
-#define C_CAN1_STAT_RXOK_Pos                                  4                                                         /*!< C_CAN1 STAT: RXOK Position          */
-#define C_CAN1_STAT_RXOK_Msk                                  (0x01UL << C_CAN1_STAT_RXOK_Pos)                          /*!< C_CAN1 STAT: RXOK Mask              */
-#define C_CAN1_STAT_EPASS_Pos                                 5                                                         /*!< C_CAN1 STAT: EPASS Position         */
-#define C_CAN1_STAT_EPASS_Msk                                 (0x01UL << C_CAN1_STAT_EPASS_Pos)                         /*!< C_CAN1 STAT: EPASS Mask             */
-#define C_CAN1_STAT_EWARN_Pos                                 6                                                         /*!< C_CAN1 STAT: EWARN Position         */
-#define C_CAN1_STAT_EWARN_Msk                                 (0x01UL << C_CAN1_STAT_EWARN_Pos)                         /*!< C_CAN1 STAT: EWARN Mask             */
-#define C_CAN1_STAT_BOFF_Pos                                  7                                                         /*!< C_CAN1 STAT: BOFF Position          */
-#define C_CAN1_STAT_BOFF_Msk                                  (0x01UL << C_CAN1_STAT_BOFF_Pos)                          /*!< C_CAN1 STAT: BOFF Mask              */
-
-// ----------------------------------------  C_CAN1_EC  -------------------------------------------
-#define C_CAN1_EC_TEC_7_0_Pos                                 0                                                         /*!< C_CAN1 EC: TEC_7_0 Position         */
-#define C_CAN1_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos)                   /*!< C_CAN1 EC: TEC_7_0 Mask             */
-#define C_CAN1_EC_REC_6_0_Pos                                 8                                                         /*!< C_CAN1 EC: REC_6_0 Position         */
-#define C_CAN1_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN1_EC_REC_6_0_Pos)                         /*!< C_CAN1 EC: REC_6_0 Mask             */
-#define C_CAN1_EC_RP_Pos                                      15                                                        /*!< C_CAN1 EC: RP Position              */
-#define C_CAN1_EC_RP_Msk                                      (0x01UL << C_CAN1_EC_RP_Pos)                              /*!< C_CAN1 EC: RP Mask                  */
-
-// ----------------------------------------  C_CAN1_BT  -------------------------------------------
-#define C_CAN1_BT_BRP_Pos                                     0                                                         /*!< C_CAN1 BT: BRP Position             */
-#define C_CAN1_BT_BRP_Msk                                     (0x3fUL << C_CAN1_BT_BRP_Pos)                             /*!< C_CAN1 BT: BRP Mask                 */
-#define C_CAN1_BT_SJW_Pos                                     6                                                         /*!< C_CAN1 BT: SJW Position             */
-#define C_CAN1_BT_SJW_Msk                                     (0x03UL << C_CAN1_BT_SJW_Pos)                             /*!< C_CAN1 BT: SJW Mask                 */
-#define C_CAN1_BT_TSEG1_Pos                                   8                                                         /*!< C_CAN1 BT: TSEG1 Position           */
-#define C_CAN1_BT_TSEG1_Msk                                   (0x0fUL << C_CAN1_BT_TSEG1_Pos)                           /*!< C_CAN1 BT: TSEG1 Mask               */
-#define C_CAN1_BT_TSEG2_Pos                                   12                                                        /*!< C_CAN1 BT: TSEG2 Position           */
-#define C_CAN1_BT_TSEG2_Msk                                   (0x07UL << C_CAN1_BT_TSEG2_Pos)                           /*!< C_CAN1 BT: TSEG2 Mask               */
-
-// ---------------------------------------  C_CAN1_INT  -------------------------------------------
-#define C_CAN1_INT_INTID15_0_Pos                              0                                                         /*!< C_CAN1 INT: INTID15_0 Position      */
-#define C_CAN1_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos)                /*!< C_CAN1 INT: INTID15_0 Mask          */
-
-// ---------------------------------------  C_CAN1_TEST  ------------------------------------------
-#define C_CAN1_TEST_BASIC_Pos                                 2                                                         /*!< C_CAN1 TEST: BASIC Position         */
-#define C_CAN1_TEST_BASIC_Msk                                 (0x01UL << C_CAN1_TEST_BASIC_Pos)                         /*!< C_CAN1 TEST: BASIC Mask             */
-#define C_CAN1_TEST_SILENT_Pos                                3                                                         /*!< C_CAN1 TEST: SILENT Position        */
-#define C_CAN1_TEST_SILENT_Msk                                (0x01UL << C_CAN1_TEST_SILENT_Pos)                        /*!< C_CAN1 TEST: SILENT Mask            */
-#define C_CAN1_TEST_LBACK_Pos                                 4                                                         /*!< C_CAN1 TEST: LBACK Position         */
-#define C_CAN1_TEST_LBACK_Msk                                 (0x01UL << C_CAN1_TEST_LBACK_Pos)                         /*!< C_CAN1 TEST: LBACK Mask             */
-#define C_CAN1_TEST_TX1_0_Pos                                 5                                                         /*!< C_CAN1 TEST: TX1_0 Position         */
-#define C_CAN1_TEST_TX1_0_Msk                                 (0x03UL << C_CAN1_TEST_TX1_0_Pos)                         /*!< C_CAN1 TEST: TX1_0 Mask             */
-#define C_CAN1_TEST_RX_Pos                                    7                                                         /*!< C_CAN1 TEST: RX Position            */
-#define C_CAN1_TEST_RX_Msk                                    (0x01UL << C_CAN1_TEST_RX_Pos)                            /*!< C_CAN1 TEST: RX Mask                */
-
-// ---------------------------------------  C_CAN1_BRPE  ------------------------------------------
-#define C_CAN1_BRPE_BRPE_Pos                                  0                                                         /*!< C_CAN1 BRPE: BRPE Position          */
-#define C_CAN1_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN1_BRPE_BRPE_Pos)                          /*!< C_CAN1 BRPE: BRPE Mask              */
-
-// ------------------------------------  C_CAN1_IF1_CMDREQ  ---------------------------------------
-#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */
-#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask     */
-#define C_CAN1_IF1_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN1 IF1_CMDREQ: BUSY Position    */
-#define C_CAN1_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos)                    /*!< C_CAN1 IF1_CMDREQ: BUSY Mask        */
-
-// -----------------------------------  C_CAN1_IF1_CMDMSK_W  --------------------------------------
-#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */
-#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask    */
-#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */
-#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask    */
-#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */
-#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask    */
-#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */
-#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */
-#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position  */
-#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask      */
-#define C_CAN1_IF1_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN1 IF1_CMDMSK_W: ARB Position   */
-#define C_CAN1_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos)                   /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask       */
-#define C_CAN1_IF1_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN1 IF1_CMDMSK_W: MASK Position  */
-#define C_CAN1_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos)                  /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask      */
-#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */
-#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask     */
-
-// -----------------------------------  C_CAN1_IF1_CMDMSK_R  --------------------------------------
-#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */
-#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask    */
-#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */
-#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask    */
-#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */
-#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask    */
-#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */
-#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */
-#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position  */
-#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask      */
-#define C_CAN1_IF1_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN1 IF1_CMDMSK_R: ARB Position   */
-#define C_CAN1_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos)                   /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask       */
-#define C_CAN1_IF1_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN1 IF1_CMDMSK_R: MASK Position  */
-#define C_CAN1_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos)                  /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask      */
-#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */
-#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask     */
-
-// -------------------------------------  C_CAN1_IF1_MSK1  ----------------------------------------
-#define C_CAN1_IF1_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN1 IF1_MSK1: MSK15_0 Position   */
-#define C_CAN1_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos)             /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask       */
-
-// -------------------------------------  C_CAN1_IF1_MSK2  ----------------------------------------
-#define C_CAN1_IF1_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN1 IF1_MSK2: MSK28_16 Position  */
-#define C_CAN1_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos)            /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask      */
-#define C_CAN1_IF1_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN1 IF1_MSK2: MDIR Position      */
-#define C_CAN1_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos)                      /*!< C_CAN1 IF1_MSK2: MDIR Mask          */
-#define C_CAN1_IF1_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN1 IF1_MSK2: MXTD Position      */
-#define C_CAN1_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos)                      /*!< C_CAN1 IF1_MSK2: MXTD Mask          */
-
-// -------------------------------------  C_CAN1_IF1_ARB1  ----------------------------------------
-#define C_CAN1_IF1_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN1 IF1_ARB1: ID15_0 Position    */
-#define C_CAN1_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos)              /*!< C_CAN1 IF1_ARB1: ID15_0 Mask        */
-
-// -------------------------------------  C_CAN1_IF1_ARB2  ----------------------------------------
-#define C_CAN1_IF1_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN1 IF1_ARB2: ID28_16 Position   */
-#define C_CAN1_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos)             /*!< C_CAN1 IF1_ARB2: ID28_16 Mask       */
-#define C_CAN1_IF1_ARB2_DIR_Pos                               13                                                        /*!< C_CAN1 IF1_ARB2: DIR Position       */
-#define C_CAN1_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos)                       /*!< C_CAN1 IF1_ARB2: DIR Mask           */
-#define C_CAN1_IF1_ARB2_XTD_Pos                               14                                                        /*!< C_CAN1 IF1_ARB2: XTD Position       */
-#define C_CAN1_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos)                       /*!< C_CAN1 IF1_ARB2: XTD Mask           */
-#define C_CAN1_IF1_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN1 IF1_ARB2: MSGVAL Position    */
-#define C_CAN1_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos)                    /*!< C_CAN1 IF1_ARB2: MSGVAL Mask        */
-
-// ------------------------------------  C_CAN1_IF1_MCTRL  ----------------------------------------
-#define C_CAN1_IF1_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position   */
-#define C_CAN1_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos)                   /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask       */
-#define C_CAN1_IF1_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN1 IF1_MCTRL: EOB Position      */
-#define C_CAN1_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos)                      /*!< C_CAN1 IF1_MCTRL: EOB Mask          */
-#define C_CAN1_IF1_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN1 IF1_MCTRL: TXRQST Position   */
-#define C_CAN1_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos)                   /*!< C_CAN1 IF1_MCTRL: TXRQST Mask       */
-#define C_CAN1_IF1_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN1 IF1_MCTRL: RMTEN Position    */
-#define C_CAN1_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos)                    /*!< C_CAN1 IF1_MCTRL: RMTEN Mask        */
-#define C_CAN1_IF1_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN1 IF1_MCTRL: RXIE Position     */
-#define C_CAN1_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos)                     /*!< C_CAN1 IF1_MCTRL: RXIE Mask         */
-#define C_CAN1_IF1_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN1 IF1_MCTRL: TXIE Position     */
-#define C_CAN1_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos)                     /*!< C_CAN1 IF1_MCTRL: TXIE Mask         */
-#define C_CAN1_IF1_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN1 IF1_MCTRL: UMASK Position    */
-#define C_CAN1_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos)                    /*!< C_CAN1 IF1_MCTRL: UMASK Mask        */
-#define C_CAN1_IF1_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN1 IF1_MCTRL: INTPND Position   */
-#define C_CAN1_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos)                   /*!< C_CAN1 IF1_MCTRL: INTPND Mask       */
-#define C_CAN1_IF1_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN1 IF1_MCTRL: MSGLST Position   */
-#define C_CAN1_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos)                   /*!< C_CAN1 IF1_MCTRL: MSGLST Mask       */
-#define C_CAN1_IF1_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN1 IF1_MCTRL: NEWDAT Position   */
-#define C_CAN1_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos)                   /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask       */
-
-// -------------------------------------  C_CAN1_IF1_DA1  -----------------------------------------
-#define C_CAN1_IF1_DA1_DATA0_Pos                              0                                                         /*!< C_CAN1 IF1_DA1: DATA0 Position      */
-#define C_CAN1_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos)                /*!< C_CAN1 IF1_DA1: DATA0 Mask          */
-#define C_CAN1_IF1_DA1_DATA1_Pos                              8                                                         /*!< C_CAN1 IF1_DA1: DATA1 Position      */
-#define C_CAN1_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos)                /*!< C_CAN1 IF1_DA1: DATA1 Mask          */
-
-// -------------------------------------  C_CAN1_IF1_DA2  -----------------------------------------
-#define C_CAN1_IF1_DA2_DATA2_Pos                              0                                                         /*!< C_CAN1 IF1_DA2: DATA2 Position      */
-#define C_CAN1_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos)                /*!< C_CAN1 IF1_DA2: DATA2 Mask          */
-#define C_CAN1_IF1_DA2_DATA3_Pos                              8                                                         /*!< C_CAN1 IF1_DA2: DATA3 Position      */
-#define C_CAN1_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos)                /*!< C_CAN1 IF1_DA2: DATA3 Mask          */
-
-// -------------------------------------  C_CAN1_IF1_DB1  -----------------------------------------
-#define C_CAN1_IF1_DB1_DATA4_Pos                              0                                                         /*!< C_CAN1 IF1_DB1: DATA4 Position      */
-#define C_CAN1_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos)                /*!< C_CAN1 IF1_DB1: DATA4 Mask          */
-#define C_CAN1_IF1_DB1_DATA5_Pos                              8                                                         /*!< C_CAN1 IF1_DB1: DATA5 Position      */
-#define C_CAN1_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos)                /*!< C_CAN1 IF1_DB1: DATA5 Mask          */
-
-// -------------------------------------  C_CAN1_IF1_DB2  -----------------------------------------
-#define C_CAN1_IF1_DB2_DATA6_Pos                              0                                                         /*!< C_CAN1 IF1_DB2: DATA6 Position      */
-#define C_CAN1_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos)                /*!< C_CAN1 IF1_DB2: DATA6 Mask          */
-#define C_CAN1_IF1_DB2_DATA7_Pos                              8                                                         /*!< C_CAN1 IF1_DB2: DATA7 Position      */
-#define C_CAN1_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos)                /*!< C_CAN1 IF1_DB2: DATA7 Mask          */
-
-// ------------------------------------  C_CAN1_IF2_CMDREQ  ---------------------------------------
-#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */
-#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask     */
-#define C_CAN1_IF2_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN1 IF2_CMDREQ: BUSY Position    */
-#define C_CAN1_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos)                    /*!< C_CAN1 IF2_CMDREQ: BUSY Mask        */
-
-// -----------------------------------  C_CAN1_IF2_CMDMSK_W  --------------------------------------
-#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */
-#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask    */
-#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */
-#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask    */
-#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */
-#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask    */
-#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */
-#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */
-#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position  */
-#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask      */
-#define C_CAN1_IF2_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN1 IF2_CMDMSK_W: ARB Position   */
-#define C_CAN1_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos)                   /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask       */
-#define C_CAN1_IF2_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN1 IF2_CMDMSK_W: MASK Position  */
-#define C_CAN1_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos)                  /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask      */
-#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */
-#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask     */
-
-// -----------------------------------  C_CAN1_IF2_CMDMSK_R  --------------------------------------
-#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */
-#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask    */
-#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */
-#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask    */
-#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */
-#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask    */
-#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */
-#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */
-#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position  */
-#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask      */
-#define C_CAN1_IF2_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN1 IF2_CMDMSK_R: ARB Position   */
-#define C_CAN1_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos)                   /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask       */
-#define C_CAN1_IF2_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN1 IF2_CMDMSK_R: MASK Position  */
-#define C_CAN1_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos)                  /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask      */
-#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */
-#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask     */
-
-// -------------------------------------  C_CAN1_IF2_MSK1  ----------------------------------------
-#define C_CAN1_IF2_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN1 IF2_MSK1: MSK15_0 Position   */
-#define C_CAN1_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos)             /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask       */
-
-// -------------------------------------  C_CAN1_IF2_MSK2  ----------------------------------------
-#define C_CAN1_IF2_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN1 IF2_MSK2: MSK28_16 Position  */
-#define C_CAN1_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos)            /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask      */
-#define C_CAN1_IF2_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN1 IF2_MSK2: MDIR Position      */
-#define C_CAN1_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos)                      /*!< C_CAN1 IF2_MSK2: MDIR Mask          */
-#define C_CAN1_IF2_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN1 IF2_MSK2: MXTD Position      */
-#define C_CAN1_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos)                      /*!< C_CAN1 IF2_MSK2: MXTD Mask          */
-
-// -------------------------------------  C_CAN1_IF2_ARB1  ----------------------------------------
-#define C_CAN1_IF2_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN1 IF2_ARB1: ID15_0 Position    */
-#define C_CAN1_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos)              /*!< C_CAN1 IF2_ARB1: ID15_0 Mask        */
-
-// -------------------------------------  C_CAN1_IF2_ARB2  ----------------------------------------
-#define C_CAN1_IF2_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN1 IF2_ARB2: ID28_16 Position   */
-#define C_CAN1_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos)             /*!< C_CAN1 IF2_ARB2: ID28_16 Mask       */
-#define C_CAN1_IF2_ARB2_DIR_Pos                               13                                                        /*!< C_CAN1 IF2_ARB2: DIR Position       */
-#define C_CAN1_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos)                       /*!< C_CAN1 IF2_ARB2: DIR Mask           */
-#define C_CAN1_IF2_ARB2_XTD_Pos                               14                                                        /*!< C_CAN1 IF2_ARB2: XTD Position       */
-#define C_CAN1_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos)                       /*!< C_CAN1 IF2_ARB2: XTD Mask           */
-#define C_CAN1_IF2_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN1 IF2_ARB2: MSGVAL Position    */
-#define C_CAN1_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos)                    /*!< C_CAN1 IF2_ARB2: MSGVAL Mask        */
-
-// ------------------------------------  C_CAN1_IF2_MCTRL  ----------------------------------------
-#define C_CAN1_IF2_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position   */
-#define C_CAN1_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos)                   /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask       */
-#define C_CAN1_IF2_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN1 IF2_MCTRL: EOB Position      */
-#define C_CAN1_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos)                      /*!< C_CAN1 IF2_MCTRL: EOB Mask          */
-#define C_CAN1_IF2_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN1 IF2_MCTRL: TXRQST Position   */
-#define C_CAN1_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos)                   /*!< C_CAN1 IF2_MCTRL: TXRQST Mask       */
-#define C_CAN1_IF2_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN1 IF2_MCTRL: RMTEN Position    */
-#define C_CAN1_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos)                    /*!< C_CAN1 IF2_MCTRL: RMTEN Mask        */
-#define C_CAN1_IF2_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN1 IF2_MCTRL: RXIE Position     */
-#define C_CAN1_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos)                     /*!< C_CAN1 IF2_MCTRL: RXIE Mask         */
-#define C_CAN1_IF2_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN1 IF2_MCTRL: TXIE Position     */
-#define C_CAN1_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos)                     /*!< C_CAN1 IF2_MCTRL: TXIE Mask         */
-#define C_CAN1_IF2_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN1 IF2_MCTRL: UMASK Position    */
-#define C_CAN1_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos)                    /*!< C_CAN1 IF2_MCTRL: UMASK Mask        */
-#define C_CAN1_IF2_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN1 IF2_MCTRL: INTPND Position   */
-#define C_CAN1_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos)                   /*!< C_CAN1 IF2_MCTRL: INTPND Mask       */
-#define C_CAN1_IF2_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN1 IF2_MCTRL: MSGLST Position   */
-#define C_CAN1_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos)                   /*!< C_CAN1 IF2_MCTRL: MSGLST Mask       */
-#define C_CAN1_IF2_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN1 IF2_MCTRL: NEWDAT Position   */
-#define C_CAN1_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos)                   /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask       */
-
-// -------------------------------------  C_CAN1_IF2_DA1  -----------------------------------------
-#define C_CAN1_IF2_DA1_DATA0_Pos                              0                                                         /*!< C_CAN1 IF2_DA1: DATA0 Position      */
-#define C_CAN1_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos)                /*!< C_CAN1 IF2_DA1: DATA0 Mask          */
-#define C_CAN1_IF2_DA1_DATA1_Pos                              8                                                         /*!< C_CAN1 IF2_DA1: DATA1 Position      */
-#define C_CAN1_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos)                /*!< C_CAN1 IF2_DA1: DATA1 Mask          */
-
-// -------------------------------------  C_CAN1_IF2_DA2  -----------------------------------------
-#define C_CAN1_IF2_DA2_DATA2_Pos                              0                                                         /*!< C_CAN1 IF2_DA2: DATA2 Position      */
-#define C_CAN1_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos)                /*!< C_CAN1 IF2_DA2: DATA2 Mask          */
-#define C_CAN1_IF2_DA2_DATA3_Pos                              8                                                         /*!< C_CAN1 IF2_DA2: DATA3 Position      */
-#define C_CAN1_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos)                /*!< C_CAN1 IF2_DA2: DATA3 Mask          */
-
-// -------------------------------------  C_CAN1_IF2_DB1  -----------------------------------------
-#define C_CAN1_IF2_DB1_DATA4_Pos                              0                                                         /*!< C_CAN1 IF2_DB1: DATA4 Position      */
-#define C_CAN1_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos)                /*!< C_CAN1 IF2_DB1: DATA4 Mask          */
-#define C_CAN1_IF2_DB1_DATA5_Pos                              8                                                         /*!< C_CAN1 IF2_DB1: DATA5 Position      */
-#define C_CAN1_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos)                /*!< C_CAN1 IF2_DB1: DATA5 Mask          */
-
-// -------------------------------------  C_CAN1_IF2_DB2  -----------------------------------------
-#define C_CAN1_IF2_DB2_DATA6_Pos                              0                                                         /*!< C_CAN1 IF2_DB2: DATA6 Position      */
-#define C_CAN1_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos)                /*!< C_CAN1 IF2_DB2: DATA6 Mask          */
-#define C_CAN1_IF2_DB2_DATA7_Pos                              8                                                         /*!< C_CAN1 IF2_DB2: DATA7 Position      */
-#define C_CAN1_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos)                /*!< C_CAN1 IF2_DB2: DATA7 Mask          */
-
-// --------------------------------------  C_CAN1_TXREQ1  -----------------------------------------
-#define C_CAN1_TXREQ1_TXRQST16_1_Pos                          0                                                         /*!< C_CAN1 TXREQ1: TXRQST16_1 Position  */
-#define C_CAN1_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos)            /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask      */
-
-// --------------------------------------  C_CAN1_TXREQ2  -----------------------------------------
-#define C_CAN1_TXREQ2_TXRQST32_17_Pos                         0                                                         /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */
-#define C_CAN1_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos)           /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask     */
-
-// ---------------------------------------  C_CAN1_ND1  -------------------------------------------
-#define C_CAN1_ND1_NEWDAT16_1_Pos                             0                                                         /*!< C_CAN1 ND1: NEWDAT16_1 Position     */
-#define C_CAN1_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos)               /*!< C_CAN1 ND1: NEWDAT16_1 Mask         */
-
-// ---------------------------------------  C_CAN1_ND2  -------------------------------------------
-#define C_CAN1_ND2_NEWDAT32_17_Pos                            0                                                         /*!< C_CAN1 ND2: NEWDAT32_17 Position    */
-#define C_CAN1_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos)              /*!< C_CAN1 ND2: NEWDAT32_17 Mask        */
-
-// ---------------------------------------  C_CAN1_IR1  -------------------------------------------
-#define C_CAN1_IR1_INTPND16_1_Pos                             0                                                         /*!< C_CAN1 IR1: INTPND16_1 Position     */
-#define C_CAN1_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos)               /*!< C_CAN1 IR1: INTPND16_1 Mask         */
-
-// ---------------------------------------  C_CAN1_IR2  -------------------------------------------
-#define C_CAN1_IR2_INTPND32_17_Pos                            0                                                         /*!< C_CAN1 IR2: INTPND32_17 Position    */
-#define C_CAN1_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos)              /*!< C_CAN1 IR2: INTPND32_17 Mask        */
-
-// --------------------------------------  C_CAN1_MSGV1  ------------------------------------------
-#define C_CAN1_MSGV1_MSGVAL16_1_Pos                           0                                                         /*!< C_CAN1 MSGV1: MSGVAL16_1 Position   */
-#define C_CAN1_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos)             /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask       */
-
-// --------------------------------------  C_CAN1_MSGV2  ------------------------------------------
-#define C_CAN1_MSGV2_MSGVAL32_17_Pos                          0                                                         /*!< C_CAN1 MSGV2: MSGVAL32_17 Position  */
-#define C_CAN1_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos)            /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask      */
-
-// --------------------------------------  C_CAN1_CLKDIV  -----------------------------------------
-#define C_CAN1_CLKDIV_CLKDIVVAL_Pos                           0                                                         /*!< C_CAN1 CLKDIV: CLKDIVVAL Position   */
-#define C_CAN1_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos)                   /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask       */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                RITIMER Position & Mask                               -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -------------------------------------  RITIMER_COMPVAL  ----------------------------------------
-#define RITIMER_COMPVAL_RICOMP_Pos                            0                                                         /*!< RITIMER COMPVAL: RICOMP Position    */
-#define RITIMER_COMPVAL_RICOMP_Msk                            (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos)              /*!< RITIMER COMPVAL: RICOMP Mask        */
-
-// --------------------------------------  RITIMER_MASK  ------------------------------------------
-#define RITIMER_MASK_RIMASK_Pos                               0                                                         /*!< RITIMER MASK: RIMASK Position       */
-#define RITIMER_MASK_RIMASK_Msk                               (0xffffffffUL << RITIMER_MASK_RIMASK_Pos)                 /*!< RITIMER MASK: RIMASK Mask           */
-
-// --------------------------------------  RITIMER_CTRL  ------------------------------------------
-#define RITIMER_CTRL_RITINT_Pos                               0                                                         /*!< RITIMER CTRL: RITINT Position       */
-#define RITIMER_CTRL_RITINT_Msk                               (0x01UL << RITIMER_CTRL_RITINT_Pos)                       /*!< RITIMER CTRL: RITINT Mask           */
-#define RITIMER_CTRL_RITENCLR_Pos                             1                                                         /*!< RITIMER CTRL: RITENCLR Position     */
-#define RITIMER_CTRL_RITENCLR_Msk                             (0x01UL << RITIMER_CTRL_RITENCLR_Pos)                     /*!< RITIMER CTRL: RITENCLR Mask         */
-#define RITIMER_CTRL_RITENBR_Pos                              2                                                         /*!< RITIMER CTRL: RITENBR Position      */
-#define RITIMER_CTRL_RITENBR_Msk                              (0x01UL << RITIMER_CTRL_RITENBR_Pos)                      /*!< RITIMER CTRL: RITENBR Mask          */
-#define RITIMER_CTRL_RITEN_Pos                                3                                                         /*!< RITIMER CTRL: RITEN Position        */
-#define RITIMER_CTRL_RITEN_Msk                                (0x01UL << RITIMER_CTRL_RITEN_Pos)                        /*!< RITIMER CTRL: RITEN Mask            */
-
-// -------------------------------------  RITIMER_COUNTER  ----------------------------------------
-#define RITIMER_COUNTER_RICOUNTER_Pos                         0                                                         /*!< RITIMER COUNTER: RICOUNTER Position */
-#define RITIMER_COUNTER_RICOUNTER_Msk                         (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos)           /*!< RITIMER COUNTER: RICOUNTER Mask     */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  QEI Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------------  QEI_CON  --------------------------------------------
-#define QEI_CON_RESP_Pos                                      0                                                         /*!< QEI CON: RESP Position              */
-#define QEI_CON_RESP_Msk                                      (0x01UL << QEI_CON_RESP_Pos)                              /*!< QEI CON: RESP Mask                  */
-#define QEI_CON_RESPI_Pos                                     1                                                         /*!< QEI CON: RESPI Position             */
-#define QEI_CON_RESPI_Msk                                     (0x01UL << QEI_CON_RESPI_Pos)                             /*!< QEI CON: RESPI Mask                 */
-#define QEI_CON_RESV_Pos                                      2                                                         /*!< QEI CON: RESV Position              */
-#define QEI_CON_RESV_Msk                                      (0x01UL << QEI_CON_RESV_Pos)                              /*!< QEI CON: RESV Mask                  */
-#define QEI_CON_RESI_Pos                                      3                                                         /*!< QEI CON: RESI Position              */
-#define QEI_CON_RESI_Msk                                      (0x01UL << QEI_CON_RESI_Pos)                              /*!< QEI CON: RESI Mask                  */
-
-// ----------------------------------------  QEI_STAT  --------------------------------------------
-#define QEI_STAT_DIR_Pos                                      0                                                         /*!< QEI STAT: DIR Position              */
-#define QEI_STAT_DIR_Msk                                      (0x01UL << QEI_STAT_DIR_Pos)                              /*!< QEI STAT: DIR Mask                  */
-
-// ----------------------------------------  QEI_CONF  --------------------------------------------
-#define QEI_CONF_DIRINV_Pos                                   0                                                         /*!< QEI CONF: DIRINV Position           */
-#define QEI_CONF_DIRINV_Msk                                   (0x01UL << QEI_CONF_DIRINV_Pos)                           /*!< QEI CONF: DIRINV Mask               */
-#define QEI_CONF_SIGMODE_Pos                                  1                                                         /*!< QEI CONF: SIGMODE Position          */
-#define QEI_CONF_SIGMODE_Msk                                  (0x01UL << QEI_CONF_SIGMODE_Pos)                          /*!< QEI CONF: SIGMODE Mask              */
-#define QEI_CONF_CAPMODE_Pos                                  2                                                         /*!< QEI CONF: CAPMODE Position          */
-#define QEI_CONF_CAPMODE_Msk                                  (0x01UL << QEI_CONF_CAPMODE_Pos)                          /*!< QEI CONF: CAPMODE Mask              */
-#define QEI_CONF_INVINX_Pos                                   3                                                         /*!< QEI CONF: INVINX Position           */
-#define QEI_CONF_INVINX_Msk                                   (0x01UL << QEI_CONF_INVINX_Pos)                           /*!< QEI CONF: INVINX Mask               */
-#define QEI_CONF_CRESPI_Pos                                   4                                                         /*!< QEI CONF: CRESPI Position           */
-#define QEI_CONF_CRESPI_Msk                                   (0x01UL << QEI_CONF_CRESPI_Pos)                           /*!< QEI CONF: CRESPI Mask               */
-#define QEI_CONF_INXGATE_Pos                                  16                                                        /*!< QEI CONF: INXGATE Position          */
-#define QEI_CONF_INXGATE_Msk                                  (0x0fUL << QEI_CONF_INXGATE_Pos)                          /*!< QEI CONF: INXGATE Mask              */
-
-// -----------------------------------------  QEI_POS  --------------------------------------------
-#define QEI_POS_POS_Pos                                       0                                                         /*!< QEI POS: POS Position               */
-#define QEI_POS_POS_Msk                                       (0xffffffffUL << QEI_POS_POS_Pos)                         /*!< QEI POS: POS Mask                   */
-
-// ---------------------------------------  QEI_MAXPOS  -------------------------------------------
-#define QEI_MAXPOS_MAXPOS_Pos                                 0                                                         /*!< QEI MAXPOS: MAXPOS Position         */
-#define QEI_MAXPOS_MAXPOS_Msk                                 (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos)                   /*!< QEI MAXPOS: MAXPOS Mask             */
-
-// ---------------------------------------  QEI_CMPOS0  -------------------------------------------
-#define QEI_CMPOS0_PCMP0_Pos                                  0                                                         /*!< QEI CMPOS0: PCMP0 Position          */
-#define QEI_CMPOS0_PCMP0_Msk                                  (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos)                    /*!< QEI CMPOS0: PCMP0 Mask              */
-
-// ---------------------------------------  QEI_CMPOS1  -------------------------------------------
-#define QEI_CMPOS1_PCMP1_Pos                                  0                                                         /*!< QEI CMPOS1: PCMP1 Position          */
-#define QEI_CMPOS1_PCMP1_Msk                                  (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos)                    /*!< QEI CMPOS1: PCMP1 Mask              */
-
-// ---------------------------------------  QEI_CMPOS2  -------------------------------------------
-#define QEI_CMPOS2_PCMP2_Pos                                  0                                                         /*!< QEI CMPOS2: PCMP2 Position          */
-#define QEI_CMPOS2_PCMP2_Msk                                  (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos)                    /*!< QEI CMPOS2: PCMP2 Mask              */
-
-// ---------------------------------------  QEI_INXCNT  -------------------------------------------
-#define QEI_INXCNT_ENCPOS_Pos                                 0                                                         /*!< QEI INXCNT: ENCPOS Position         */
-#define QEI_INXCNT_ENCPOS_Msk                                 (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos)                   /*!< QEI INXCNT: ENCPOS Mask             */
-
-// ---------------------------------------  QEI_INXCMP0  ------------------------------------------
-#define QEI_INXCMP0_ICMP0_Pos                                 0                                                         /*!< QEI INXCMP0: ICMP0 Position         */
-#define QEI_INXCMP0_ICMP0_Msk                                 (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos)                   /*!< QEI INXCMP0: ICMP0 Mask             */
-
-// ----------------------------------------  QEI_LOAD  --------------------------------------------
-#define QEI_LOAD_VELLOAD_Pos                                  0                                                         /*!< QEI LOAD: VELLOAD Position          */
-#define QEI_LOAD_VELLOAD_Msk                                  (0xffffffffUL << QEI_LOAD_VELLOAD_Pos)                    /*!< QEI LOAD: VELLOAD Mask              */
-
-// ----------------------------------------  QEI_TIME  --------------------------------------------
-#define QEI_TIME_VELVAL_Pos                                   0                                                         /*!< QEI TIME: VELVAL Position           */
-#define QEI_TIME_VELVAL_Msk                                   (0xffffffffUL << QEI_TIME_VELVAL_Pos)                     /*!< QEI TIME: VELVAL Mask               */
-
-// -----------------------------------------  QEI_VEL  --------------------------------------------
-#define QEI_VEL_VELPC_Pos                                     0                                                         /*!< QEI VEL: VELPC Position             */
-#define QEI_VEL_VELPC_Msk                                     (0xffffffffUL << QEI_VEL_VELPC_Pos)                       /*!< QEI VEL: VELPC Mask                 */
-
-// -----------------------------------------  QEI_CAP  --------------------------------------------
-#define QEI_CAP_VELCAP_Pos                                    0                                                         /*!< QEI CAP: VELCAP Position            */
-#define QEI_CAP_VELCAP_Msk                                    (0xffffffffUL << QEI_CAP_VELCAP_Pos)                      /*!< QEI CAP: VELCAP Mask                */
-
-// ---------------------------------------  QEI_VELCOMP  ------------------------------------------
-#define QEI_VELCOMP_VELCMP_Pos                                0                                                         /*!< QEI VELCOMP: VELCMP Position        */
-#define QEI_VELCOMP_VELCMP_Msk                                (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos)                  /*!< QEI VELCOMP: VELCMP Mask            */
-
-// --------------------------------------  QEI_FILTERPHA  -----------------------------------------
-#define QEI_FILTERPHA_FILTA_Pos                               0                                                         /*!< QEI FILTERPHA: FILTA Position       */
-#define QEI_FILTERPHA_FILTA_Msk                               (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos)                 /*!< QEI FILTERPHA: FILTA Mask           */
-
-// --------------------------------------  QEI_FILTERPHB  -----------------------------------------
-#define QEI_FILTERPHB_FILTB_Pos                               0                                                         /*!< QEI FILTERPHB: FILTB Position       */
-#define QEI_FILTERPHB_FILTB_Msk                               (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos)                 /*!< QEI FILTERPHB: FILTB Mask           */
-
-// --------------------------------------  QEI_FILTERINX  -----------------------------------------
-#define QEI_FILTERINX_FITLINX_Pos                             0                                                         /*!< QEI FILTERINX: FITLINX Position     */
-#define QEI_FILTERINX_FITLINX_Msk                             (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos)               /*!< QEI FILTERINX: FITLINX Mask         */
-
-// ---------------------------------------  QEI_WINDOW  -------------------------------------------
-#define QEI_WINDOW_WINDOW_Pos                                 0                                                         /*!< QEI WINDOW: WINDOW Position         */
-#define QEI_WINDOW_WINDOW_Msk                                 (0xffffffffUL << QEI_WINDOW_WINDOW_Pos)                   /*!< QEI WINDOW: WINDOW Mask             */
-
-// ---------------------------------------  QEI_INXCMP1  ------------------------------------------
-#define QEI_INXCMP1_ICMP1_Pos                                 0                                                         /*!< QEI INXCMP1: ICMP1 Position         */
-#define QEI_INXCMP1_ICMP1_Msk                                 (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos)                   /*!< QEI INXCMP1: ICMP1 Mask             */
-
-// ---------------------------------------  QEI_INXCMP2  ------------------------------------------
-#define QEI_INXCMP2_ICMP2_Pos                                 0                                                         /*!< QEI INXCMP2: ICMP2 Position         */
-#define QEI_INXCMP2_ICMP2_Msk                                 (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos)                   /*!< QEI INXCMP2: ICMP2 Mask             */
-
-// -----------------------------------------  QEI_IEC  --------------------------------------------
-#define QEI_IEC_INX_EN_Pos                                    0                                                         /*!< QEI IEC: INX_EN Position            */
-#define QEI_IEC_INX_EN_Msk                                    (0x01UL << QEI_IEC_INX_EN_Pos)                            /*!< QEI IEC: INX_EN Mask                */
-#define QEI_IEC_TIM_EN_Pos                                    1                                                         /*!< QEI IEC: TIM_EN Position            */
-#define QEI_IEC_TIM_EN_Msk                                    (0x01UL << QEI_IEC_TIM_EN_Pos)                            /*!< QEI IEC: TIM_EN Mask                */
-#define QEI_IEC_VELC_EN_Pos                                   2                                                         /*!< QEI IEC: VELC_EN Position           */
-#define QEI_IEC_VELC_EN_Msk                                   (0x01UL << QEI_IEC_VELC_EN_Pos)                           /*!< QEI IEC: VELC_EN Mask               */
-#define QEI_IEC_DIR_EN_Pos                                    3                                                         /*!< QEI IEC: DIR_EN Position            */
-#define QEI_IEC_DIR_EN_Msk                                    (0x01UL << QEI_IEC_DIR_EN_Pos)                            /*!< QEI IEC: DIR_EN Mask                */
-#define QEI_IEC_ERR_EN_Pos                                    4                                                         /*!< QEI IEC: ERR_EN Position            */
-#define QEI_IEC_ERR_EN_Msk                                    (0x01UL << QEI_IEC_ERR_EN_Pos)                            /*!< QEI IEC: ERR_EN Mask                */
-#define QEI_IEC_ENCLK_EN_Pos                                  5                                                         /*!< QEI IEC: ENCLK_EN Position          */
-#define QEI_IEC_ENCLK_EN_Msk                                  (0x01UL << QEI_IEC_ENCLK_EN_Pos)                          /*!< QEI IEC: ENCLK_EN Mask              */
-#define QEI_IEC_POS0_Int_Pos                                  6                                                         /*!< QEI IEC: POS0_Int Position          */
-#define QEI_IEC_POS0_Int_Msk                                  (0x01UL << QEI_IEC_POS0_Int_Pos)                          /*!< QEI IEC: POS0_Int Mask              */
-#define QEI_IEC_POS1_Int_Pos                                  7                                                         /*!< QEI IEC: POS1_Int Position          */
-#define QEI_IEC_POS1_Int_Msk                                  (0x01UL << QEI_IEC_POS1_Int_Pos)                          /*!< QEI IEC: POS1_Int Mask              */
-#define QEI_IEC_POS2_Int_Pos                                  8                                                         /*!< QEI IEC: POS2_Int Position          */
-#define QEI_IEC_POS2_Int_Msk                                  (0x01UL << QEI_IEC_POS2_Int_Pos)                          /*!< QEI IEC: POS2_Int Mask              */
-#define QEI_IEC_REV_Int_Pos                                   9                                                         /*!< QEI IEC: REV_Int Position           */
-#define QEI_IEC_REV_Int_Msk                                   (0x01UL << QEI_IEC_REV_Int_Pos)                           /*!< QEI IEC: REV_Int Mask               */
-#define QEI_IEC_POS0REV_Int_Pos                               10                                                        /*!< QEI IEC: POS0REV_Int Position       */
-#define QEI_IEC_POS0REV_Int_Msk                               (0x01UL << QEI_IEC_POS0REV_Int_Pos)                       /*!< QEI IEC: POS0REV_Int Mask           */
-#define QEI_IEC_POS1REV_Int_Pos                               11                                                        /*!< QEI IEC: POS1REV_Int Position       */
-#define QEI_IEC_POS1REV_Int_Msk                               (0x01UL << QEI_IEC_POS1REV_Int_Pos)                       /*!< QEI IEC: POS1REV_Int Mask           */
-#define QEI_IEC_POS2REV_Int_Pos                               12                                                        /*!< QEI IEC: POS2REV_Int Position       */
-#define QEI_IEC_POS2REV_Int_Msk                               (0x01UL << QEI_IEC_POS2REV_Int_Pos)                       /*!< QEI IEC: POS2REV_Int Mask           */
-#define QEI_IEC_REV1_Int_Pos                                  13                                                        /*!< QEI IEC: REV1_Int Position          */
-#define QEI_IEC_REV1_Int_Msk                                  (0x01UL << QEI_IEC_REV1_Int_Pos)                          /*!< QEI IEC: REV1_Int Mask              */
-#define QEI_IEC_REV2_Int_Pos                                  14                                                        /*!< QEI IEC: REV2_Int Position          */
-#define QEI_IEC_REV2_Int_Msk                                  (0x01UL << QEI_IEC_REV2_Int_Pos)                          /*!< QEI IEC: REV2_Int Mask              */
-#define QEI_IEC_MAXPOS_Int_Pos                                15                                                        /*!< QEI IEC: MAXPOS_Int Position        */
-#define QEI_IEC_MAXPOS_Int_Msk                                (0x01UL << QEI_IEC_MAXPOS_Int_Pos)                        /*!< QEI IEC: MAXPOS_Int Mask            */
-
-// -----------------------------------------  QEI_IES  --------------------------------------------
-#define QEI_IES_INX_EN_Pos                                    0                                                         /*!< QEI IES: INX_EN Position            */
-#define QEI_IES_INX_EN_Msk                                    (0x01UL << QEI_IES_INX_EN_Pos)                            /*!< QEI IES: INX_EN Mask                */
-#define QEI_IES_TIM_EN_Pos                                    1                                                         /*!< QEI IES: TIM_EN Position            */
-#define QEI_IES_TIM_EN_Msk                                    (0x01UL << QEI_IES_TIM_EN_Pos)                            /*!< QEI IES: TIM_EN Mask                */
-#define QEI_IES_VELC_EN_Pos                                   2                                                         /*!< QEI IES: VELC_EN Position           */
-#define QEI_IES_VELC_EN_Msk                                   (0x01UL << QEI_IES_VELC_EN_Pos)                           /*!< QEI IES: VELC_EN Mask               */
-#define QEI_IES_DIR_EN_Pos                                    3                                                         /*!< QEI IES: DIR_EN Position            */
-#define QEI_IES_DIR_EN_Msk                                    (0x01UL << QEI_IES_DIR_EN_Pos)                            /*!< QEI IES: DIR_EN Mask                */
-#define QEI_IES_ERR_EN_Pos                                    4                                                         /*!< QEI IES: ERR_EN Position            */
-#define QEI_IES_ERR_EN_Msk                                    (0x01UL << QEI_IES_ERR_EN_Pos)                            /*!< QEI IES: ERR_EN Mask                */
-#define QEI_IES_ENCLK_EN_Pos                                  5                                                         /*!< QEI IES: ENCLK_EN Position          */
-#define QEI_IES_ENCLK_EN_Msk                                  (0x01UL << QEI_IES_ENCLK_EN_Pos)                          /*!< QEI IES: ENCLK_EN Mask              */
-#define QEI_IES_POS0_Int_Pos                                  6                                                         /*!< QEI IES: POS0_Int Position          */
-#define QEI_IES_POS0_Int_Msk                                  (0x01UL << QEI_IES_POS0_Int_Pos)                          /*!< QEI IES: POS0_Int Mask              */
-#define QEI_IES_POS1_Int_Pos                                  7                                                         /*!< QEI IES: POS1_Int Position          */
-#define QEI_IES_POS1_Int_Msk                                  (0x01UL << QEI_IES_POS1_Int_Pos)                          /*!< QEI IES: POS1_Int Mask              */
-#define QEI_IES_POS2_Int_Pos                                  8                                                         /*!< QEI IES: POS2_Int Position          */
-#define QEI_IES_POS2_Int_Msk                                  (0x01UL << QEI_IES_POS2_Int_Pos)                          /*!< QEI IES: POS2_Int Mask              */
-#define QEI_IES_REV_Int_Pos                                   9                                                         /*!< QEI IES: REV_Int Position           */
-#define QEI_IES_REV_Int_Msk                                   (0x01UL << QEI_IES_REV_Int_Pos)                           /*!< QEI IES: REV_Int Mask               */
-#define QEI_IES_POS0REV_Int_Pos                               10                                                        /*!< QEI IES: POS0REV_Int Position       */
-#define QEI_IES_POS0REV_Int_Msk                               (0x01UL << QEI_IES_POS0REV_Int_Pos)                       /*!< QEI IES: POS0REV_Int Mask           */
-#define QEI_IES_POS1REV_Int_Pos                               11                                                        /*!< QEI IES: POS1REV_Int Position       */
-#define QEI_IES_POS1REV_Int_Msk                               (0x01UL << QEI_IES_POS1REV_Int_Pos)                       /*!< QEI IES: POS1REV_Int Mask           */
-#define QEI_IES_POS2REV_Int_Pos                               12                                                        /*!< QEI IES: POS2REV_Int Position       */
-#define QEI_IES_POS2REV_Int_Msk                               (0x01UL << QEI_IES_POS2REV_Int_Pos)                       /*!< QEI IES: POS2REV_Int Mask           */
-#define QEI_IES_REV1_Int_Pos                                  13                                                        /*!< QEI IES: REV1_Int Position          */
-#define QEI_IES_REV1_Int_Msk                                  (0x01UL << QEI_IES_REV1_Int_Pos)                          /*!< QEI IES: REV1_Int Mask              */
-#define QEI_IES_REV2_Int_Pos                                  14                                                        /*!< QEI IES: REV2_Int Position          */
-#define QEI_IES_REV2_Int_Msk                                  (0x01UL << QEI_IES_REV2_Int_Pos)                          /*!< QEI IES: REV2_Int Mask              */
-#define QEI_IES_MAXPOS_Int_Pos                                15                                                        /*!< QEI IES: MAXPOS_Int Position        */
-#define QEI_IES_MAXPOS_Int_Msk                                (0x01UL << QEI_IES_MAXPOS_Int_Pos)                        /*!< QEI IES: MAXPOS_Int Mask            */
-
-// ---------------------------------------  QEI_INTSTAT  ------------------------------------------
-#define QEI_INTSTAT_INX_Int_Pos                               0                                                         /*!< QEI INTSTAT: INX_Int Position       */
-#define QEI_INTSTAT_INX_Int_Msk                               (0x01UL << QEI_INTSTAT_INX_Int_Pos)                       /*!< QEI INTSTAT: INX_Int Mask           */
-#define QEI_INTSTAT_TIM_Int_Pos                               1                                                         /*!< QEI INTSTAT: TIM_Int Position       */
-#define QEI_INTSTAT_TIM_Int_Msk                               (0x01UL << QEI_INTSTAT_TIM_Int_Pos)                       /*!< QEI INTSTAT: TIM_Int Mask           */
-#define QEI_INTSTAT_VELC_Int_Pos                              2                                                         /*!< QEI INTSTAT: VELC_Int Position      */
-#define QEI_INTSTAT_VELC_Int_Msk                              (0x01UL << QEI_INTSTAT_VELC_Int_Pos)                      /*!< QEI INTSTAT: VELC_Int Mask          */
-#define QEI_INTSTAT_DIR_Int_Pos                               3                                                         /*!< QEI INTSTAT: DIR_Int Position       */
-#define QEI_INTSTAT_DIR_Int_Msk                               (0x01UL << QEI_INTSTAT_DIR_Int_Pos)                       /*!< QEI INTSTAT: DIR_Int Mask           */
-#define QEI_INTSTAT_ERR_Int_Pos                               4                                                         /*!< QEI INTSTAT: ERR_Int Position       */
-#define QEI_INTSTAT_ERR_Int_Msk                               (0x01UL << QEI_INTSTAT_ERR_Int_Pos)                       /*!< QEI INTSTAT: ERR_Int Mask           */
-#define QEI_INTSTAT_ENCLK_Int_Pos                             5                                                         /*!< QEI INTSTAT: ENCLK_Int Position     */
-#define QEI_INTSTAT_ENCLK_Int_Msk                             (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos)                     /*!< QEI INTSTAT: ENCLK_Int Mask         */
-#define QEI_INTSTAT_POS0_Int_Pos                              6                                                         /*!< QEI INTSTAT: POS0_Int Position      */
-#define QEI_INTSTAT_POS0_Int_Msk                              (0x01UL << QEI_INTSTAT_POS0_Int_Pos)                      /*!< QEI INTSTAT: POS0_Int Mask          */
-#define QEI_INTSTAT_POS1_Int_Pos                              7                                                         /*!< QEI INTSTAT: POS1_Int Position      */
-#define QEI_INTSTAT_POS1_Int_Msk                              (0x01UL << QEI_INTSTAT_POS1_Int_Pos)                      /*!< QEI INTSTAT: POS1_Int Mask          */
-#define QEI_INTSTAT_POS2_Int_Pos                              8                                                         /*!< QEI INTSTAT: POS2_Int Position      */
-#define QEI_INTSTAT_POS2_Int_Msk                              (0x01UL << QEI_INTSTAT_POS2_Int_Pos)                      /*!< QEI INTSTAT: POS2_Int Mask          */
-#define QEI_INTSTAT_REV_Int_Pos                               9                                                         /*!< QEI INTSTAT: REV_Int Position       */
-#define QEI_INTSTAT_REV_Int_Msk                               (0x01UL << QEI_INTSTAT_REV_Int_Pos)                       /*!< QEI INTSTAT: REV_Int Mask           */
-#define QEI_INTSTAT_POS0REV_Int_Pos                           10                                                        /*!< QEI INTSTAT: POS0REV_Int Position   */
-#define QEI_INTSTAT_POS0REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos)                   /*!< QEI INTSTAT: POS0REV_Int Mask       */
-#define QEI_INTSTAT_POS1REV_Int_Pos                           11                                                        /*!< QEI INTSTAT: POS1REV_Int Position   */
-#define QEI_INTSTAT_POS1REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos)                   /*!< QEI INTSTAT: POS1REV_Int Mask       */
-#define QEI_INTSTAT_POS2REV_Int_Pos                           12                                                        /*!< QEI INTSTAT: POS2REV_Int Position   */
-#define QEI_INTSTAT_POS2REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos)                   /*!< QEI INTSTAT: POS2REV_Int Mask       */
-#define QEI_INTSTAT_REV1_Int_Pos                              13                                                        /*!< QEI INTSTAT: REV1_Int Position      */
-#define QEI_INTSTAT_REV1_Int_Msk                              (0x01UL << QEI_INTSTAT_REV1_Int_Pos)                      /*!< QEI INTSTAT: REV1_Int Mask          */
-#define QEI_INTSTAT_REV2_Int_Pos                              14                                                        /*!< QEI INTSTAT: REV2_Int Position      */
-#define QEI_INTSTAT_REV2_Int_Msk                              (0x01UL << QEI_INTSTAT_REV2_Int_Pos)                      /*!< QEI INTSTAT: REV2_Int Mask          */
-#define QEI_INTSTAT_MAXPOS_Int_Pos                            15                                                        /*!< QEI INTSTAT: MAXPOS_Int Position    */
-#define QEI_INTSTAT_MAXPOS_Int_Msk                            (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos)                    /*!< QEI INTSTAT: MAXPOS_Int Mask        */
-
-// -----------------------------------------  QEI_IE  ---------------------------------------------
-#define QEI_IE_INX_Int_Pos                                    0                                                         /*!< QEI IE: INX_Int Position            */
-#define QEI_IE_INX_Int_Msk                                    (0x01UL << QEI_IE_INX_Int_Pos)                            /*!< QEI IE: INX_Int Mask                */
-#define QEI_IE_TIM_Int_Pos                                    1                                                         /*!< QEI IE: TIM_Int Position            */
-#define QEI_IE_TIM_Int_Msk                                    (0x01UL << QEI_IE_TIM_Int_Pos)                            /*!< QEI IE: TIM_Int Mask                */
-#define QEI_IE_VELC_Int_Pos                                   2                                                         /*!< QEI IE: VELC_Int Position           */
-#define QEI_IE_VELC_Int_Msk                                   (0x01UL << QEI_IE_VELC_Int_Pos)                           /*!< QEI IE: VELC_Int Mask               */
-#define QEI_IE_DIR_Int_Pos                                    3                                                         /*!< QEI IE: DIR_Int Position            */
-#define QEI_IE_DIR_Int_Msk                                    (0x01UL << QEI_IE_DIR_Int_Pos)                            /*!< QEI IE: DIR_Int Mask                */
-#define QEI_IE_ERR_Int_Pos                                    4                                                         /*!< QEI IE: ERR_Int Position            */
-#define QEI_IE_ERR_Int_Msk                                    (0x01UL << QEI_IE_ERR_Int_Pos)                            /*!< QEI IE: ERR_Int Mask                */
-#define QEI_IE_ENCLK_Int_Pos                                  5                                                         /*!< QEI IE: ENCLK_Int Position          */
-#define QEI_IE_ENCLK_Int_Msk                                  (0x01UL << QEI_IE_ENCLK_Int_Pos)                          /*!< QEI IE: ENCLK_Int Mask              */
-#define QEI_IE_POS0_Int_Pos                                   6                                                         /*!< QEI IE: POS0_Int Position           */
-#define QEI_IE_POS0_Int_Msk                                   (0x01UL << QEI_IE_POS0_Int_Pos)                           /*!< QEI IE: POS0_Int Mask               */
-#define QEI_IE_POS1_Int_Pos                                   7                                                         /*!< QEI IE: POS1_Int Position           */
-#define QEI_IE_POS1_Int_Msk                                   (0x01UL << QEI_IE_POS1_Int_Pos)                           /*!< QEI IE: POS1_Int Mask               */
-#define QEI_IE_POS2_Int_Pos                                   8                                                         /*!< QEI IE: POS2_Int Position           */
-#define QEI_IE_POS2_Int_Msk                                   (0x01UL << QEI_IE_POS2_Int_Pos)                           /*!< QEI IE: POS2_Int Mask               */
-#define QEI_IE_REV_Int_Pos                                    9                                                         /*!< QEI IE: REV_Int Position            */
-#define QEI_IE_REV_Int_Msk                                    (0x01UL << QEI_IE_REV_Int_Pos)                            /*!< QEI IE: REV_Int Mask                */
-#define QEI_IE_POS0REV_Int_Pos                                10                                                        /*!< QEI IE: POS0REV_Int Position        */
-#define QEI_IE_POS0REV_Int_Msk                                (0x01UL << QEI_IE_POS0REV_Int_Pos)                        /*!< QEI IE: POS0REV_Int Mask            */
-#define QEI_IE_POS1REV_Int_Pos                                11                                                        /*!< QEI IE: POS1REV_Int Position        */
-#define QEI_IE_POS1REV_Int_Msk                                (0x01UL << QEI_IE_POS1REV_Int_Pos)                        /*!< QEI IE: POS1REV_Int Mask            */
-#define QEI_IE_POS2REV_Int_Pos                                12                                                        /*!< QEI IE: POS2REV_Int Position        */
-#define QEI_IE_POS2REV_Int_Msk                                (0x01UL << QEI_IE_POS2REV_Int_Pos)                        /*!< QEI IE: POS2REV_Int Mask            */
-#define QEI_IE_REV1_Int_Pos                                   13                                                        /*!< QEI IE: REV1_Int Position           */
-#define QEI_IE_REV1_Int_Msk                                   (0x01UL << QEI_IE_REV1_Int_Pos)                           /*!< QEI IE: REV1_Int Mask               */
-#define QEI_IE_REV2_Int_Pos                                   14                                                        /*!< QEI IE: REV2_Int Position           */
-#define QEI_IE_REV2_Int_Msk                                   (0x01UL << QEI_IE_REV2_Int_Pos)                           /*!< QEI IE: REV2_Int Mask               */
-#define QEI_IE_MAXPOS_Int_Pos                                 15                                                        /*!< QEI IE: MAXPOS_Int Position         */
-#define QEI_IE_MAXPOS_Int_Msk                                 (0x01UL << QEI_IE_MAXPOS_Int_Pos)                         /*!< QEI IE: MAXPOS_Int Mask             */
-
-// -----------------------------------------  QEI_CLR  --------------------------------------------
-#define QEI_CLR_INX_Int_Pos                                   0                                                         /*!< QEI CLR: INX_Int Position           */
-#define QEI_CLR_INX_Int_Msk                                   (0x01UL << QEI_CLR_INX_Int_Pos)                           /*!< QEI CLR: INX_Int Mask               */
-#define QEI_CLR_TIM_Int_Pos                                   1                                                         /*!< QEI CLR: TIM_Int Position           */
-#define QEI_CLR_TIM_Int_Msk                                   (0x01UL << QEI_CLR_TIM_Int_Pos)                           /*!< QEI CLR: TIM_Int Mask               */
-#define QEI_CLR_VELC_Int_Pos                                  2                                                         /*!< QEI CLR: VELC_Int Position          */
-#define QEI_CLR_VELC_Int_Msk                                  (0x01UL << QEI_CLR_VELC_Int_Pos)                          /*!< QEI CLR: VELC_Int Mask              */
-#define QEI_CLR_DIR_Int_Pos                                   3                                                         /*!< QEI CLR: DIR_Int Position           */
-#define QEI_CLR_DIR_Int_Msk                                   (0x01UL << QEI_CLR_DIR_Int_Pos)                           /*!< QEI CLR: DIR_Int Mask               */
-#define QEI_CLR_ERR_Int_Pos                                   4                                                         /*!< QEI CLR: ERR_Int Position           */
-#define QEI_CLR_ERR_Int_Msk                                   (0x01UL << QEI_CLR_ERR_Int_Pos)                           /*!< QEI CLR: ERR_Int Mask               */
-#define QEI_CLR_ENCLK_Int_Pos                                 5                                                         /*!< QEI CLR: ENCLK_Int Position         */
-#define QEI_CLR_ENCLK_Int_Msk                                 (0x01UL << QEI_CLR_ENCLK_Int_Pos)                         /*!< QEI CLR: ENCLK_Int Mask             */
-#define QEI_CLR_POS0_Int_Pos                                  6                                                         /*!< QEI CLR: POS0_Int Position          */
-#define QEI_CLR_POS0_Int_Msk                                  (0x01UL << QEI_CLR_POS0_Int_Pos)                          /*!< QEI CLR: POS0_Int Mask              */
-#define QEI_CLR_POS1_Int_Pos                                  7                                                         /*!< QEI CLR: POS1_Int Position          */
-#define QEI_CLR_POS1_Int_Msk                                  (0x01UL << QEI_CLR_POS1_Int_Pos)                          /*!< QEI CLR: POS1_Int Mask              */
-#define QEI_CLR_POS2_Int_Pos                                  8                                                         /*!< QEI CLR: POS2_Int Position          */
-#define QEI_CLR_POS2_Int_Msk                                  (0x01UL << QEI_CLR_POS2_Int_Pos)                          /*!< QEI CLR: POS2_Int Mask              */
-#define QEI_CLR_REV_Int_Pos                                   9                                                         /*!< QEI CLR: REV_Int Position           */
-#define QEI_CLR_REV_Int_Msk                                   (0x01UL << QEI_CLR_REV_Int_Pos)                           /*!< QEI CLR: REV_Int Mask               */
-#define QEI_CLR_POS0REV_Int_Pos                               10                                                        /*!< QEI CLR: POS0REV_Int Position       */
-#define QEI_CLR_POS0REV_Int_Msk                               (0x01UL << QEI_CLR_POS0REV_Int_Pos)                       /*!< QEI CLR: POS0REV_Int Mask           */
-#define QEI_CLR_POS1REV_Int_Pos                               11                                                        /*!< QEI CLR: POS1REV_Int Position       */
-#define QEI_CLR_POS1REV_Int_Msk                               (0x01UL << QEI_CLR_POS1REV_Int_Pos)                       /*!< QEI CLR: POS1REV_Int Mask           */
-#define QEI_CLR_REV1_Int_Pos                                  13                                                        /*!< QEI CLR: REV1_Int Position          */
-#define QEI_CLR_REV1_Int_Msk                                  (0x01UL << QEI_CLR_REV1_Int_Pos)                          /*!< QEI CLR: REV1_Int Mask              */
-#define QEI_CLR_REV2_Int_Pos                                  14                                                        /*!< QEI CLR: REV2_Int Position          */
-#define QEI_CLR_REV2_Int_Msk                                  (0x01UL << QEI_CLR_REV2_Int_Pos)                          /*!< QEI CLR: REV2_Int Mask              */
-#define QEI_CLR_MAXPOS_Int_Pos                                15                                                        /*!< QEI CLR: MAXPOS_Int Position        */
-#define QEI_CLR_MAXPOS_Int_Msk                                (0x01UL << QEI_CLR_MAXPOS_Int_Pos)                        /*!< QEI CLR: MAXPOS_Int Mask            */
-
-// -----------------------------------------  QEI_SET  --------------------------------------------
-#define QEI_SET_INX_Int_Pos                                   0                                                         /*!< QEI SET: INX_Int Position           */
-#define QEI_SET_INX_Int_Msk                                   (0x01UL << QEI_SET_INX_Int_Pos)                           /*!< QEI SET: INX_Int Mask               */
-#define QEI_SET_TIM_Int_Pos                                   1                                                         /*!< QEI SET: TIM_Int Position           */
-#define QEI_SET_TIM_Int_Msk                                   (0x01UL << QEI_SET_TIM_Int_Pos)                           /*!< QEI SET: TIM_Int Mask               */
-#define QEI_SET_VELC_Int_Pos                                  2                                                         /*!< QEI SET: VELC_Int Position          */
-#define QEI_SET_VELC_Int_Msk                                  (0x01UL << QEI_SET_VELC_Int_Pos)                          /*!< QEI SET: VELC_Int Mask              */
-#define QEI_SET_DIR_Int_Pos                                   3                                                         /*!< QEI SET: DIR_Int Position           */
-#define QEI_SET_DIR_Int_Msk                                   (0x01UL << QEI_SET_DIR_Int_Pos)                           /*!< QEI SET: DIR_Int Mask               */
-#define QEI_SET_ERR_Int_Pos                                   4                                                         /*!< QEI SET: ERR_Int Position           */
-#define QEI_SET_ERR_Int_Msk                                   (0x01UL << QEI_SET_ERR_Int_Pos)                           /*!< QEI SET: ERR_Int Mask               */
-#define QEI_SET_ENCLK_Int_Pos                                 5                                                         /*!< QEI SET: ENCLK_Int Position         */
-#define QEI_SET_ENCLK_Int_Msk                                 (0x01UL << QEI_SET_ENCLK_Int_Pos)                         /*!< QEI SET: ENCLK_Int Mask             */
-#define QEI_SET_POS0_Int_Pos                                  6                                                         /*!< QEI SET: POS0_Int Position          */
-#define QEI_SET_POS0_Int_Msk                                  (0x01UL << QEI_SET_POS0_Int_Pos)                          /*!< QEI SET: POS0_Int Mask              */
-#define QEI_SET_POS1_Int_Pos                                  7                                                         /*!< QEI SET: POS1_Int Position          */
-#define QEI_SET_POS1_Int_Msk                                  (0x01UL << QEI_SET_POS1_Int_Pos)                          /*!< QEI SET: POS1_Int Mask              */
-#define QEI_SET_POS2_Int_Pos                                  8                                                         /*!< QEI SET: POS2_Int Position          */
-#define QEI_SET_POS2_Int_Msk                                  (0x01UL << QEI_SET_POS2_Int_Pos)                          /*!< QEI SET: POS2_Int Mask              */
-#define QEI_SET_REV_Int_Pos                                   9                                                         /*!< QEI SET: REV_Int Position           */
-#define QEI_SET_REV_Int_Msk                                   (0x01UL << QEI_SET_REV_Int_Pos)                           /*!< QEI SET: REV_Int Mask               */
-#define QEI_SET_POS0REV_Int_Pos                               10                                                        /*!< QEI SET: POS0REV_Int Position       */
-#define QEI_SET_POS0REV_Int_Msk                               (0x01UL << QEI_SET_POS0REV_Int_Pos)                       /*!< QEI SET: POS0REV_Int Mask           */
-#define QEI_SET_POS1REV_Int_Pos                               11                                                        /*!< QEI SET: POS1REV_Int Position       */
-#define QEI_SET_POS1REV_Int_Msk                               (0x01UL << QEI_SET_POS1REV_Int_Pos)                       /*!< QEI SET: POS1REV_Int Mask           */
-#define QEI_SET_POS2REV_Int_Pos                               12                                                        /*!< QEI SET: POS2REV_Int Position       */
-#define QEI_SET_POS2REV_Int_Msk                               (0x01UL << QEI_SET_POS2REV_Int_Pos)                       /*!< QEI SET: POS2REV_Int Mask           */
-#define QEI_SET_REV1_Int_Pos                                  13                                                        /*!< QEI SET: REV1_Int Position          */
-#define QEI_SET_REV1_Int_Msk                                  (0x01UL << QEI_SET_REV1_Int_Pos)                          /*!< QEI SET: REV1_Int Mask              */
-#define QEI_SET_REV2_Int_Pos                                  14                                                        /*!< QEI SET: REV2_Int Position          */
-#define QEI_SET_REV2_Int_Msk                                  (0x01UL << QEI_SET_REV2_Int_Pos)                          /*!< QEI SET: REV2_Int Mask              */
-#define QEI_SET_MAXPOS_Int_Pos                                15                                                        /*!< QEI SET: MAXPOS_Int Position        */
-#define QEI_SET_MAXPOS_Int_Msk                                (0x01UL << QEI_SET_MAXPOS_Int_Pos)                        /*!< QEI SET: MAXPOS_Int Mask            */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 GIMA Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -------------------------------------  GIMA_CAP0_0_IN  -----------------------------------------
-#define GIMA_CAP0_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_0_IN: INV Position        */
-#define GIMA_CAP0_0_IN_INV_Msk                                (0x01UL << GIMA_CAP0_0_IN_INV_Pos)                        /*!< GIMA CAP0_0_IN: INV Mask            */
-#define GIMA_CAP0_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_0_IN: EDGE Position       */
-#define GIMA_CAP0_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos)                       /*!< GIMA CAP0_0_IN: EDGE Mask           */
-#define GIMA_CAP0_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_0_IN: SYNCH Position      */
-#define GIMA_CAP0_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos)                      /*!< GIMA CAP0_0_IN: SYNCH Mask          */
-#define GIMA_CAP0_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_0_IN: PULSE Position      */
-#define GIMA_CAP0_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos)                      /*!< GIMA CAP0_0_IN: PULSE Mask          */
-#define GIMA_CAP0_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_0_IN: SELECT Position     */
-#define GIMA_CAP0_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos)                     /*!< GIMA CAP0_0_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP0_1_IN  -----------------------------------------
-#define GIMA_CAP0_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_1_IN: INV Position        */
-#define GIMA_CAP0_1_IN_INV_Msk                                (0x01UL << GIMA_CAP0_1_IN_INV_Pos)                        /*!< GIMA CAP0_1_IN: INV Mask            */
-#define GIMA_CAP0_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_1_IN: EDGE Position       */
-#define GIMA_CAP0_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos)                       /*!< GIMA CAP0_1_IN: EDGE Mask           */
-#define GIMA_CAP0_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_1_IN: SYNCH Position      */
-#define GIMA_CAP0_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos)                      /*!< GIMA CAP0_1_IN: SYNCH Mask          */
-#define GIMA_CAP0_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_1_IN: PULSE Position      */
-#define GIMA_CAP0_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos)                      /*!< GIMA CAP0_1_IN: PULSE Mask          */
-#define GIMA_CAP0_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_1_IN: SELECT Position     */
-#define GIMA_CAP0_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos)                     /*!< GIMA CAP0_1_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP0_2_IN  -----------------------------------------
-#define GIMA_CAP0_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_2_IN: INV Position        */
-#define GIMA_CAP0_2_IN_INV_Msk                                (0x01UL << GIMA_CAP0_2_IN_INV_Pos)                        /*!< GIMA CAP0_2_IN: INV Mask            */
-#define GIMA_CAP0_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_2_IN: EDGE Position       */
-#define GIMA_CAP0_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos)                       /*!< GIMA CAP0_2_IN: EDGE Mask           */
-#define GIMA_CAP0_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_2_IN: SYNCH Position      */
-#define GIMA_CAP0_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos)                      /*!< GIMA CAP0_2_IN: SYNCH Mask          */
-#define GIMA_CAP0_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_2_IN: PULSE Position      */
-#define GIMA_CAP0_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos)                      /*!< GIMA CAP0_2_IN: PULSE Mask          */
-#define GIMA_CAP0_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_2_IN: SELECT Position     */
-#define GIMA_CAP0_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos)                     /*!< GIMA CAP0_2_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP0_3_IN  -----------------------------------------
-#define GIMA_CAP0_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP0_3_IN: INV Position        */
-#define GIMA_CAP0_3_IN_INV_Msk                                (0x01UL << GIMA_CAP0_3_IN_INV_Pos)                        /*!< GIMA CAP0_3_IN: INV Mask            */
-#define GIMA_CAP0_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP0_3_IN: EDGE Position       */
-#define GIMA_CAP0_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos)                       /*!< GIMA CAP0_3_IN: EDGE Mask           */
-#define GIMA_CAP0_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP0_3_IN: SYNCH Position      */
-#define GIMA_CAP0_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos)                      /*!< GIMA CAP0_3_IN: SYNCH Mask          */
-#define GIMA_CAP0_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP0_3_IN: PULSE Position      */
-#define GIMA_CAP0_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos)                      /*!< GIMA CAP0_3_IN: PULSE Mask          */
-#define GIMA_CAP0_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP0_3_IN: SELECT Position     */
-#define GIMA_CAP0_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos)                     /*!< GIMA CAP0_3_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP1_0_IN  -----------------------------------------
-#define GIMA_CAP1_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_0_IN: INV Position        */
-#define GIMA_CAP1_0_IN_INV_Msk                                (0x01UL << GIMA_CAP1_0_IN_INV_Pos)                        /*!< GIMA CAP1_0_IN: INV Mask            */
-#define GIMA_CAP1_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_0_IN: EDGE Position       */
-#define GIMA_CAP1_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos)                       /*!< GIMA CAP1_0_IN: EDGE Mask           */
-#define GIMA_CAP1_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_0_IN: SYNCH Position      */
-#define GIMA_CAP1_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos)                      /*!< GIMA CAP1_0_IN: SYNCH Mask          */
-#define GIMA_CAP1_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_0_IN: PULSE Position      */
-#define GIMA_CAP1_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos)                      /*!< GIMA CAP1_0_IN: PULSE Mask          */
-#define GIMA_CAP1_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_0_IN: SELECT Position     */
-#define GIMA_CAP1_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos)                     /*!< GIMA CAP1_0_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP1_1_IN  -----------------------------------------
-#define GIMA_CAP1_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_1_IN: INV Position        */
-#define GIMA_CAP1_1_IN_INV_Msk                                (0x01UL << GIMA_CAP1_1_IN_INV_Pos)                        /*!< GIMA CAP1_1_IN: INV Mask            */
-#define GIMA_CAP1_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_1_IN: EDGE Position       */
-#define GIMA_CAP1_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos)                       /*!< GIMA CAP1_1_IN: EDGE Mask           */
-#define GIMA_CAP1_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_1_IN: SYNCH Position      */
-#define GIMA_CAP1_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos)                      /*!< GIMA CAP1_1_IN: SYNCH Mask          */
-#define GIMA_CAP1_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_1_IN: PULSE Position      */
-#define GIMA_CAP1_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos)                      /*!< GIMA CAP1_1_IN: PULSE Mask          */
-#define GIMA_CAP1_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_1_IN: SELECT Position     */
-#define GIMA_CAP1_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos)                     /*!< GIMA CAP1_1_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP1_2_IN  -----------------------------------------
-#define GIMA_CAP1_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_2_IN: INV Position        */
-#define GIMA_CAP1_2_IN_INV_Msk                                (0x01UL << GIMA_CAP1_2_IN_INV_Pos)                        /*!< GIMA CAP1_2_IN: INV Mask            */
-#define GIMA_CAP1_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_2_IN: EDGE Position       */
-#define GIMA_CAP1_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos)                       /*!< GIMA CAP1_2_IN: EDGE Mask           */
-#define GIMA_CAP1_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_2_IN: SYNCH Position      */
-#define GIMA_CAP1_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos)                      /*!< GIMA CAP1_2_IN: SYNCH Mask          */
-#define GIMA_CAP1_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_2_IN: PULSE Position      */
-#define GIMA_CAP1_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos)                      /*!< GIMA CAP1_2_IN: PULSE Mask          */
-#define GIMA_CAP1_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_2_IN: SELECT Position     */
-#define GIMA_CAP1_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos)                     /*!< GIMA CAP1_2_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP1_3_IN  -----------------------------------------
-#define GIMA_CAP1_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP1_3_IN: INV Position        */
-#define GIMA_CAP1_3_IN_INV_Msk                                (0x01UL << GIMA_CAP1_3_IN_INV_Pos)                        /*!< GIMA CAP1_3_IN: INV Mask            */
-#define GIMA_CAP1_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP1_3_IN: EDGE Position       */
-#define GIMA_CAP1_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos)                       /*!< GIMA CAP1_3_IN: EDGE Mask           */
-#define GIMA_CAP1_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP1_3_IN: SYNCH Position      */
-#define GIMA_CAP1_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos)                      /*!< GIMA CAP1_3_IN: SYNCH Mask          */
-#define GIMA_CAP1_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP1_3_IN: PULSE Position      */
-#define GIMA_CAP1_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos)                      /*!< GIMA CAP1_3_IN: PULSE Mask          */
-#define GIMA_CAP1_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP1_3_IN: SELECT Position     */
-#define GIMA_CAP1_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos)                     /*!< GIMA CAP1_3_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP2_0_IN  -----------------------------------------
-#define GIMA_CAP2_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_0_IN: INV Position        */
-#define GIMA_CAP2_0_IN_INV_Msk                                (0x01UL << GIMA_CAP2_0_IN_INV_Pos)                        /*!< GIMA CAP2_0_IN: INV Mask            */
-#define GIMA_CAP2_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_0_IN: EDGE Position       */
-#define GIMA_CAP2_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos)                       /*!< GIMA CAP2_0_IN: EDGE Mask           */
-#define GIMA_CAP2_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_0_IN: SYNCH Position      */
-#define GIMA_CAP2_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos)                      /*!< GIMA CAP2_0_IN: SYNCH Mask          */
-#define GIMA_CAP2_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_0_IN: PULSE Position      */
-#define GIMA_CAP2_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos)                      /*!< GIMA CAP2_0_IN: PULSE Mask          */
-#define GIMA_CAP2_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_0_IN: SELECT Position     */
-#define GIMA_CAP2_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos)                     /*!< GIMA CAP2_0_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP2_1_IN  -----------------------------------------
-#define GIMA_CAP2_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_1_IN: INV Position        */
-#define GIMA_CAP2_1_IN_INV_Msk                                (0x01UL << GIMA_CAP2_1_IN_INV_Pos)                        /*!< GIMA CAP2_1_IN: INV Mask            */
-#define GIMA_CAP2_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_1_IN: EDGE Position       */
-#define GIMA_CAP2_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos)                       /*!< GIMA CAP2_1_IN: EDGE Mask           */
-#define GIMA_CAP2_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_1_IN: SYNCH Position      */
-#define GIMA_CAP2_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos)                      /*!< GIMA CAP2_1_IN: SYNCH Mask          */
-#define GIMA_CAP2_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_1_IN: PULSE Position      */
-#define GIMA_CAP2_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos)                      /*!< GIMA CAP2_1_IN: PULSE Mask          */
-#define GIMA_CAP2_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_1_IN: SELECT Position     */
-#define GIMA_CAP2_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos)                     /*!< GIMA CAP2_1_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP2_2_IN  -----------------------------------------
-#define GIMA_CAP2_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_2_IN: INV Position        */
-#define GIMA_CAP2_2_IN_INV_Msk                                (0x01UL << GIMA_CAP2_2_IN_INV_Pos)                        /*!< GIMA CAP2_2_IN: INV Mask            */
-#define GIMA_CAP2_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_2_IN: EDGE Position       */
-#define GIMA_CAP2_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos)                       /*!< GIMA CAP2_2_IN: EDGE Mask           */
-#define GIMA_CAP2_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_2_IN: SYNCH Position      */
-#define GIMA_CAP2_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos)                      /*!< GIMA CAP2_2_IN: SYNCH Mask          */
-#define GIMA_CAP2_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_2_IN: PULSE Position      */
-#define GIMA_CAP2_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos)                      /*!< GIMA CAP2_2_IN: PULSE Mask          */
-#define GIMA_CAP2_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_2_IN: SELECT Position     */
-#define GIMA_CAP2_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos)                     /*!< GIMA CAP2_2_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP2_3_IN  -----------------------------------------
-#define GIMA_CAP2_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP2_3_IN: INV Position        */
-#define GIMA_CAP2_3_IN_INV_Msk                                (0x01UL << GIMA_CAP2_3_IN_INV_Pos)                        /*!< GIMA CAP2_3_IN: INV Mask            */
-#define GIMA_CAP2_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP2_3_IN: EDGE Position       */
-#define GIMA_CAP2_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos)                       /*!< GIMA CAP2_3_IN: EDGE Mask           */
-#define GIMA_CAP2_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP2_3_IN: SYNCH Position      */
-#define GIMA_CAP2_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos)                      /*!< GIMA CAP2_3_IN: SYNCH Mask          */
-#define GIMA_CAP2_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP2_3_IN: PULSE Position      */
-#define GIMA_CAP2_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos)                      /*!< GIMA CAP2_3_IN: PULSE Mask          */
-#define GIMA_CAP2_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP2_3_IN: SELECT Position     */
-#define GIMA_CAP2_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos)                     /*!< GIMA CAP2_3_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP3_0_IN  -----------------------------------------
-#define GIMA_CAP3_0_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_0_IN: INV Position        */
-#define GIMA_CAP3_0_IN_INV_Msk                                (0x01UL << GIMA_CAP3_0_IN_INV_Pos)                        /*!< GIMA CAP3_0_IN: INV Mask            */
-#define GIMA_CAP3_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_0_IN: EDGE Position       */
-#define GIMA_CAP3_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos)                       /*!< GIMA CAP3_0_IN: EDGE Mask           */
-#define GIMA_CAP3_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_0_IN: SYNCH Position      */
-#define GIMA_CAP3_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos)                      /*!< GIMA CAP3_0_IN: SYNCH Mask          */
-#define GIMA_CAP3_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_0_IN: PULSE Position      */
-#define GIMA_CAP3_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos)                      /*!< GIMA CAP3_0_IN: PULSE Mask          */
-#define GIMA_CAP3_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_0_IN: SELECT Position     */
-#define GIMA_CAP3_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos)                     /*!< GIMA CAP3_0_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP3_1_IN  -----------------------------------------
-#define GIMA_CAP3_1_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_1_IN: INV Position        */
-#define GIMA_CAP3_1_IN_INV_Msk                                (0x01UL << GIMA_CAP3_1_IN_INV_Pos)                        /*!< GIMA CAP3_1_IN: INV Mask            */
-#define GIMA_CAP3_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_1_IN: EDGE Position       */
-#define GIMA_CAP3_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos)                       /*!< GIMA CAP3_1_IN: EDGE Mask           */
-#define GIMA_CAP3_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_1_IN: SYNCH Position      */
-#define GIMA_CAP3_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos)                      /*!< GIMA CAP3_1_IN: SYNCH Mask          */
-#define GIMA_CAP3_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_1_IN: PULSE Position      */
-#define GIMA_CAP3_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos)                      /*!< GIMA CAP3_1_IN: PULSE Mask          */
-#define GIMA_CAP3_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_1_IN: SELECT Position     */
-#define GIMA_CAP3_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos)                     /*!< GIMA CAP3_1_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP3_2_IN  -----------------------------------------
-#define GIMA_CAP3_2_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_2_IN: INV Position        */
-#define GIMA_CAP3_2_IN_INV_Msk                                (0x01UL << GIMA_CAP3_2_IN_INV_Pos)                        /*!< GIMA CAP3_2_IN: INV Mask            */
-#define GIMA_CAP3_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_2_IN: EDGE Position       */
-#define GIMA_CAP3_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos)                       /*!< GIMA CAP3_2_IN: EDGE Mask           */
-#define GIMA_CAP3_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_2_IN: SYNCH Position      */
-#define GIMA_CAP3_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos)                      /*!< GIMA CAP3_2_IN: SYNCH Mask          */
-#define GIMA_CAP3_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_2_IN: PULSE Position      */
-#define GIMA_CAP3_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos)                      /*!< GIMA CAP3_2_IN: PULSE Mask          */
-#define GIMA_CAP3_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_2_IN: SELECT Position     */
-#define GIMA_CAP3_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos)                     /*!< GIMA CAP3_2_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CAP3_3_IN  -----------------------------------------
-#define GIMA_CAP3_3_IN_INV_Pos                                0                                                         /*!< GIMA CAP3_3_IN: INV Position        */
-#define GIMA_CAP3_3_IN_INV_Msk                                (0x01UL << GIMA_CAP3_3_IN_INV_Pos)                        /*!< GIMA CAP3_3_IN: INV Mask            */
-#define GIMA_CAP3_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CAP3_3_IN: EDGE Position       */
-#define GIMA_CAP3_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos)                       /*!< GIMA CAP3_3_IN: EDGE Mask           */
-#define GIMA_CAP3_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CAP3_3_IN: SYNCH Position      */
-#define GIMA_CAP3_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos)                      /*!< GIMA CAP3_3_IN: SYNCH Mask          */
-#define GIMA_CAP3_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CAP3_3_IN: PULSE Position      */
-#define GIMA_CAP3_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos)                      /*!< GIMA CAP3_3_IN: PULSE Mask          */
-#define GIMA_CAP3_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CAP3_3_IN: SELECT Position     */
-#define GIMA_CAP3_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos)                     /*!< GIMA CAP3_3_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CTIN_0_IN  -----------------------------------------
-#define GIMA_CTIN_0_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_0_IN: INV Position        */
-#define GIMA_CTIN_0_IN_INV_Msk                                (0x01UL << GIMA_CTIN_0_IN_INV_Pos)                        /*!< GIMA CTIN_0_IN: INV Mask            */
-#define GIMA_CTIN_0_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_0_IN: EDGE Position       */
-#define GIMA_CTIN_0_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos)                       /*!< GIMA CTIN_0_IN: EDGE Mask           */
-#define GIMA_CTIN_0_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_0_IN: SYNCH Position      */
-#define GIMA_CTIN_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos)                      /*!< GIMA CTIN_0_IN: SYNCH Mask          */
-#define GIMA_CTIN_0_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_0_IN: PULSE Position      */
-#define GIMA_CTIN_0_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos)                      /*!< GIMA CTIN_0_IN: PULSE Mask          */
-#define GIMA_CTIN_0_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_0_IN: SELECT Position     */
-#define GIMA_CTIN_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos)                     /*!< GIMA CTIN_0_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CTIN_1_IN  -----------------------------------------
-#define GIMA_CTIN_1_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_1_IN: INV Position        */
-#define GIMA_CTIN_1_IN_INV_Msk                                (0x01UL << GIMA_CTIN_1_IN_INV_Pos)                        /*!< GIMA CTIN_1_IN: INV Mask            */
-#define GIMA_CTIN_1_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_1_IN: EDGE Position       */
-#define GIMA_CTIN_1_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos)                       /*!< GIMA CTIN_1_IN: EDGE Mask           */
-#define GIMA_CTIN_1_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_1_IN: SYNCH Position      */
-#define GIMA_CTIN_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos)                      /*!< GIMA CTIN_1_IN: SYNCH Mask          */
-#define GIMA_CTIN_1_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_1_IN: PULSE Position      */
-#define GIMA_CTIN_1_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos)                      /*!< GIMA CTIN_1_IN: PULSE Mask          */
-#define GIMA_CTIN_1_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_1_IN: SELECT Position     */
-#define GIMA_CTIN_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos)                     /*!< GIMA CTIN_1_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CTIN_2_IN  -----------------------------------------
-#define GIMA_CTIN_2_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_2_IN: INV Position        */
-#define GIMA_CTIN_2_IN_INV_Msk                                (0x01UL << GIMA_CTIN_2_IN_INV_Pos)                        /*!< GIMA CTIN_2_IN: INV Mask            */
-#define GIMA_CTIN_2_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_2_IN: EDGE Position       */
-#define GIMA_CTIN_2_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos)                       /*!< GIMA CTIN_2_IN: EDGE Mask           */
-#define GIMA_CTIN_2_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_2_IN: SYNCH Position      */
-#define GIMA_CTIN_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos)                      /*!< GIMA CTIN_2_IN: SYNCH Mask          */
-#define GIMA_CTIN_2_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_2_IN: PULSE Position      */
-#define GIMA_CTIN_2_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos)                      /*!< GIMA CTIN_2_IN: PULSE Mask          */
-#define GIMA_CTIN_2_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_2_IN: SELECT Position     */
-#define GIMA_CTIN_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos)                     /*!< GIMA CTIN_2_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CTIN_3_IN  -----------------------------------------
-#define GIMA_CTIN_3_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_3_IN: INV Position        */
-#define GIMA_CTIN_3_IN_INV_Msk                                (0x01UL << GIMA_CTIN_3_IN_INV_Pos)                        /*!< GIMA CTIN_3_IN: INV Mask            */
-#define GIMA_CTIN_3_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_3_IN: EDGE Position       */
-#define GIMA_CTIN_3_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos)                       /*!< GIMA CTIN_3_IN: EDGE Mask           */
-#define GIMA_CTIN_3_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_3_IN: SYNCH Position      */
-#define GIMA_CTIN_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos)                      /*!< GIMA CTIN_3_IN: SYNCH Mask          */
-#define GIMA_CTIN_3_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_3_IN: PULSE Position      */
-#define GIMA_CTIN_3_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos)                      /*!< GIMA CTIN_3_IN: PULSE Mask          */
-#define GIMA_CTIN_3_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_3_IN: SELECT Position     */
-#define GIMA_CTIN_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos)                     /*!< GIMA CTIN_3_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CTIN_4_IN  -----------------------------------------
-#define GIMA_CTIN_4_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_4_IN: INV Position        */
-#define GIMA_CTIN_4_IN_INV_Msk                                (0x01UL << GIMA_CTIN_4_IN_INV_Pos)                        /*!< GIMA CTIN_4_IN: INV Mask            */
-#define GIMA_CTIN_4_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_4_IN: EDGE Position       */
-#define GIMA_CTIN_4_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos)                       /*!< GIMA CTIN_4_IN: EDGE Mask           */
-#define GIMA_CTIN_4_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_4_IN: SYNCH Position      */
-#define GIMA_CTIN_4_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos)                      /*!< GIMA CTIN_4_IN: SYNCH Mask          */
-#define GIMA_CTIN_4_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_4_IN: PULSE Position      */
-#define GIMA_CTIN_4_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos)                      /*!< GIMA CTIN_4_IN: PULSE Mask          */
-#define GIMA_CTIN_4_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_4_IN: SELECT Position     */
-#define GIMA_CTIN_4_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos)                     /*!< GIMA CTIN_4_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CTIN_5_IN  -----------------------------------------
-#define GIMA_CTIN_5_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_5_IN: INV Position        */
-#define GIMA_CTIN_5_IN_INV_Msk                                (0x01UL << GIMA_CTIN_5_IN_INV_Pos)                        /*!< GIMA CTIN_5_IN: INV Mask            */
-#define GIMA_CTIN_5_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_5_IN: EDGE Position       */
-#define GIMA_CTIN_5_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos)                       /*!< GIMA CTIN_5_IN: EDGE Mask           */
-#define GIMA_CTIN_5_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_5_IN: SYNCH Position      */
-#define GIMA_CTIN_5_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos)                      /*!< GIMA CTIN_5_IN: SYNCH Mask          */
-#define GIMA_CTIN_5_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_5_IN: PULSE Position      */
-#define GIMA_CTIN_5_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos)                      /*!< GIMA CTIN_5_IN: PULSE Mask          */
-#define GIMA_CTIN_5_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_5_IN: SELECT Position     */
-#define GIMA_CTIN_5_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos)                     /*!< GIMA CTIN_5_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CTIN_6_IN  -----------------------------------------
-#define GIMA_CTIN_6_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_6_IN: INV Position        */
-#define GIMA_CTIN_6_IN_INV_Msk                                (0x01UL << GIMA_CTIN_6_IN_INV_Pos)                        /*!< GIMA CTIN_6_IN: INV Mask            */
-#define GIMA_CTIN_6_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_6_IN: EDGE Position       */
-#define GIMA_CTIN_6_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos)                       /*!< GIMA CTIN_6_IN: EDGE Mask           */
-#define GIMA_CTIN_6_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_6_IN: SYNCH Position      */
-#define GIMA_CTIN_6_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos)                      /*!< GIMA CTIN_6_IN: SYNCH Mask          */
-#define GIMA_CTIN_6_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_6_IN: PULSE Position      */
-#define GIMA_CTIN_6_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos)                      /*!< GIMA CTIN_6_IN: PULSE Mask          */
-#define GIMA_CTIN_6_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_6_IN: SELECT Position     */
-#define GIMA_CTIN_6_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos)                     /*!< GIMA CTIN_6_IN: SELECT Mask         */
-
-// -------------------------------------  GIMA_CTIN_7_IN  -----------------------------------------
-#define GIMA_CTIN_7_IN_INV_Pos                                0                                                         /*!< GIMA CTIN_7_IN: INV Position        */
-#define GIMA_CTIN_7_IN_INV_Msk                                (0x01UL << GIMA_CTIN_7_IN_INV_Pos)                        /*!< GIMA CTIN_7_IN: INV Mask            */
-#define GIMA_CTIN_7_IN_EDGE_Pos                               1                                                         /*!< GIMA CTIN_7_IN: EDGE Position       */
-#define GIMA_CTIN_7_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos)                       /*!< GIMA CTIN_7_IN: EDGE Mask           */
-#define GIMA_CTIN_7_IN_SYNCH_Pos                              2                                                         /*!< GIMA CTIN_7_IN: SYNCH Position      */
-#define GIMA_CTIN_7_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos)                      /*!< GIMA CTIN_7_IN: SYNCH Mask          */
-#define GIMA_CTIN_7_IN_PULSE_Pos                              3                                                         /*!< GIMA CTIN_7_IN: PULSE Position      */
-#define GIMA_CTIN_7_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos)                      /*!< GIMA CTIN_7_IN: PULSE Mask          */
-#define GIMA_CTIN_7_IN_SELECT_Pos                             4                                                         /*!< GIMA CTIN_7_IN: SELECT Position     */
-#define GIMA_CTIN_7_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos)                     /*!< GIMA CTIN_7_IN: SELECT Mask         */
-
-// ----------------------------------  GIMA_VADC_TRIGGER_IN  --------------------------------------
-#define GIMA_VADC_TRIGGER_IN_INV_Pos                          0                                                         /*!< GIMA VADC_TRIGGER_IN: INV Position  */
-#define GIMA_VADC_TRIGGER_IN_INV_Msk                          (0x01UL << GIMA_VADC_TRIGGER_IN_INV_Pos)                  /*!< GIMA VADC_TRIGGER_IN: INV Mask      */
-#define GIMA_VADC_TRIGGER_IN_EDGE_Pos                         1                                                         /*!< GIMA VADC_TRIGGER_IN: EDGE Position */
-#define GIMA_VADC_TRIGGER_IN_EDGE_Msk                         (0x01UL << GIMA_VADC_TRIGGER_IN_EDGE_Pos)                 /*!< GIMA VADC_TRIGGER_IN: EDGE Mask     */
-#define GIMA_VADC_TRIGGER_IN_SYNCH_Pos                        2                                                         /*!< GIMA VADC_TRIGGER_IN: SYNCH Position */
-#define GIMA_VADC_TRIGGER_IN_SYNCH_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_SYNCH_Pos)                /*!< GIMA VADC_TRIGGER_IN: SYNCH Mask    */
-#define GIMA_VADC_TRIGGER_IN_PULSE_Pos                        3                                                         /*!< GIMA VADC_TRIGGER_IN: PULSE Position */
-#define GIMA_VADC_TRIGGER_IN_PULSE_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_PULSE_Pos)                /*!< GIMA VADC_TRIGGER_IN: PULSE Mask    */
-#define GIMA_VADC_TRIGGER_IN_SELECT_Pos                       4                                                         /*!< GIMA VADC_TRIGGER_IN: SELECT Position */
-#define GIMA_VADC_TRIGGER_IN_SELECT_Msk                       (0x0fUL << GIMA_VADC_TRIGGER_IN_SELECT_Pos)               /*!< GIMA VADC_TRIGGER_IN: SELECT Mask   */
-
-// ---------------------------------  GIMA_EVENTROUTER_13_IN  -------------------------------------
-#define GIMA_EVENTROUTER_13_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_13_IN: INV Position */
-#define GIMA_EVENTROUTER_13_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos)                /*!< GIMA EVENTROUTER_13_IN: INV Mask    */
-#define GIMA_EVENTROUTER_13_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_13_IN: EDGE Position */
-#define GIMA_EVENTROUTER_13_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_13_IN: EDGE Mask   */
-#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */
-#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask  */
-#define GIMA_EVENTROUTER_13_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_13_IN: PULSE Position */
-#define GIMA_EVENTROUTER_13_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_13_IN: PULSE Mask  */
-#define GIMA_EVENTROUTER_13_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_13_IN: SELECT Position */
-#define GIMA_EVENTROUTER_13_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */
-
-// ---------------------------------  GIMA_EVENTROUTER_14_IN  -------------------------------------
-#define GIMA_EVENTROUTER_14_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_14_IN: INV Position */
-#define GIMA_EVENTROUTER_14_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos)                /*!< GIMA EVENTROUTER_14_IN: INV Mask    */
-#define GIMA_EVENTROUTER_14_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_14_IN: EDGE Position */
-#define GIMA_EVENTROUTER_14_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_14_IN: EDGE Mask   */
-#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */
-#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask  */
-#define GIMA_EVENTROUTER_14_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_14_IN: PULSE Position */
-#define GIMA_EVENTROUTER_14_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_14_IN: PULSE Mask  */
-#define GIMA_EVENTROUTER_14_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_14_IN: SELECT Position */
-#define GIMA_EVENTROUTER_14_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */
-
-// ---------------------------------  GIMA_EVENTROUTER_16_IN  -------------------------------------
-#define GIMA_EVENTROUTER_16_IN_INV_Pos                        0                                                         /*!< GIMA EVENTROUTER_16_IN: INV Position */
-#define GIMA_EVENTROUTER_16_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos)                /*!< GIMA EVENTROUTER_16_IN: INV Mask    */
-#define GIMA_EVENTROUTER_16_IN_EDGE_Pos                       1                                                         /*!< GIMA EVENTROUTER_16_IN: EDGE Position */
-#define GIMA_EVENTROUTER_16_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos)               /*!< GIMA EVENTROUTER_16_IN: EDGE Mask   */
-#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos                      2                                                         /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */
-#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos)              /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask  */
-#define GIMA_EVENTROUTER_16_IN_PULSE_Pos                      3                                                         /*!< GIMA EVENTROUTER_16_IN: PULSE Position */
-#define GIMA_EVENTROUTER_16_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos)              /*!< GIMA EVENTROUTER_16_IN: PULSE Mask  */
-#define GIMA_EVENTROUTER_16_IN_SELECT_Pos                     4                                                         /*!< GIMA EVENTROUTER_16_IN: SELECT Position */
-#define GIMA_EVENTROUTER_16_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos)             /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */
-
-// ------------------------------------  GIMA_ADCSTART0_IN  ---------------------------------------
-#define GIMA_ADCSTART0_IN_INV_Pos                             0                                                         /*!< GIMA ADCSTART0_IN: INV Position     */
-#define GIMA_ADCSTART0_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART0_IN_INV_Pos)                     /*!< GIMA ADCSTART0_IN: INV Mask         */
-#define GIMA_ADCSTART0_IN_EDGE_Pos                            1                                                         /*!< GIMA ADCSTART0_IN: EDGE Position    */
-#define GIMA_ADCSTART0_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos)                    /*!< GIMA ADCSTART0_IN: EDGE Mask        */
-#define GIMA_ADCSTART0_IN_SYNCH_Pos                           2                                                         /*!< GIMA ADCSTART0_IN: SYNCH Position   */
-#define GIMA_ADCSTART0_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos)                   /*!< GIMA ADCSTART0_IN: SYNCH Mask       */
-#define GIMA_ADCSTART0_IN_PULSE_Pos                           3                                                         /*!< GIMA ADCSTART0_IN: PULSE Position   */
-#define GIMA_ADCSTART0_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos)                   /*!< GIMA ADCSTART0_IN: PULSE Mask       */
-#define GIMA_ADCSTART0_IN_SELECT_Pos                          4                                                         /*!< GIMA ADCSTART0_IN: SELECT Position  */
-#define GIMA_ADCSTART0_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos)                  /*!< GIMA ADCSTART0_IN: SELECT Mask      */
-
-// ------------------------------------  GIMA_ADCSTART1_IN  ---------------------------------------
-#define GIMA_ADCSTART1_IN_INV_Pos                             0                                                         /*!< GIMA ADCSTART1_IN: INV Position     */
-#define GIMA_ADCSTART1_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART1_IN_INV_Pos)                     /*!< GIMA ADCSTART1_IN: INV Mask         */
-#define GIMA_ADCSTART1_IN_EDGE_Pos                            1                                                         /*!< GIMA ADCSTART1_IN: EDGE Position    */
-#define GIMA_ADCSTART1_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos)                    /*!< GIMA ADCSTART1_IN: EDGE Mask        */
-#define GIMA_ADCSTART1_IN_SYNCH_Pos                           2                                                         /*!< GIMA ADCSTART1_IN: SYNCH Position   */
-#define GIMA_ADCSTART1_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos)                   /*!< GIMA ADCSTART1_IN: SYNCH Mask       */
-#define GIMA_ADCSTART1_IN_PULSE_Pos                           3                                                         /*!< GIMA ADCSTART1_IN: PULSE Position   */
-#define GIMA_ADCSTART1_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos)                   /*!< GIMA ADCSTART1_IN: PULSE Mask       */
-#define GIMA_ADCSTART1_IN_SELECT_Pos                          4                                                         /*!< GIMA ADCSTART1_IN: SELECT Position  */
-#define GIMA_ADCSTART1_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos)                  /*!< GIMA ADCSTART1_IN: SELECT Mask      */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  DAC Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------------  DAC_CR  ---------------------------------------------
-#define DAC_CR_VALUE_Pos                                      6                                                         /*!< DAC CR: VALUE Position              */
-#define DAC_CR_VALUE_Msk                                      (0x000003ffUL << DAC_CR_VALUE_Pos)                        /*!< DAC CR: VALUE Mask                  */
-#define DAC_CR_BIAS_Pos                                       16                                                        /*!< DAC CR: BIAS Position               */
-#define DAC_CR_BIAS_Msk                                       (0x01UL << DAC_CR_BIAS_Pos)                               /*!< DAC CR: BIAS Mask                   */
-
-// ----------------------------------------  DAC_CTRL  --------------------------------------------
-#define DAC_CTRL_INT_DMA_REQ_Pos                              0                                                         /*!< DAC CTRL: INT_DMA_REQ Position      */
-#define DAC_CTRL_INT_DMA_REQ_Msk                              (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos)                      /*!< DAC CTRL: INT_DMA_REQ Mask          */
-#define DAC_CTRL_DBLBUF_ENA_Pos                               1                                                         /*!< DAC CTRL: DBLBUF_ENA Position       */
-#define DAC_CTRL_DBLBUF_ENA_Msk                               (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos)                       /*!< DAC CTRL: DBLBUF_ENA Mask           */
-#define DAC_CTRL_CNT_ENA_Pos                                  2                                                         /*!< DAC CTRL: CNT_ENA Position          */
-#define DAC_CTRL_CNT_ENA_Msk                                  (0x01UL << DAC_CTRL_CNT_ENA_Pos)                          /*!< DAC CTRL: CNT_ENA Mask              */
-#define DAC_CTRL_DMA_ENA_Pos                                  3                                                         /*!< DAC CTRL: DMA_ENA Position          */
-#define DAC_CTRL_DMA_ENA_Msk                                  (0x01UL << DAC_CTRL_DMA_ENA_Pos)                          /*!< DAC CTRL: DMA_ENA Mask              */
-
-// ---------------------------------------  DAC_CNTVAL  -------------------------------------------
-#define DAC_CNTVAL_VALUE_Pos                                  0                                                         /*!< DAC CNTVAL: VALUE Position          */
-#define DAC_CNTVAL_VALUE_Msk                                  (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos)                    /*!< DAC CNTVAL: VALUE Mask              */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                C_CAN0 Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// ---------------------------------------  C_CAN0_CNTL  ------------------------------------------
-#define C_CAN0_CNTL_INIT_Pos                                  0                                                         /*!< C_CAN0 CNTL: INIT Position          */
-#define C_CAN0_CNTL_INIT_Msk                                  (0x01UL << C_CAN0_CNTL_INIT_Pos)                          /*!< C_CAN0 CNTL: INIT Mask              */
-#define C_CAN0_CNTL_IE_Pos                                    1                                                         /*!< C_CAN0 CNTL: IE Position            */
-#define C_CAN0_CNTL_IE_Msk                                    (0x01UL << C_CAN0_CNTL_IE_Pos)                            /*!< C_CAN0 CNTL: IE Mask                */
-#define C_CAN0_CNTL_SIE_Pos                                   2                                                         /*!< C_CAN0 CNTL: SIE Position           */
-#define C_CAN0_CNTL_SIE_Msk                                   (0x01UL << C_CAN0_CNTL_SIE_Pos)                           /*!< C_CAN0 CNTL: SIE Mask               */
-#define C_CAN0_CNTL_EIE_Pos                                   3                                                         /*!< C_CAN0 CNTL: EIE Position           */
-#define C_CAN0_CNTL_EIE_Msk                                   (0x01UL << C_CAN0_CNTL_EIE_Pos)                           /*!< C_CAN0 CNTL: EIE Mask               */
-#define C_CAN0_CNTL_DAR_Pos                                   5                                                         /*!< C_CAN0 CNTL: DAR Position           */
-#define C_CAN0_CNTL_DAR_Msk                                   (0x01UL << C_CAN0_CNTL_DAR_Pos)                           /*!< C_CAN0 CNTL: DAR Mask               */
-#define C_CAN0_CNTL_CCE_Pos                                   6                                                         /*!< C_CAN0 CNTL: CCE Position           */
-#define C_CAN0_CNTL_CCE_Msk                                   (0x01UL << C_CAN0_CNTL_CCE_Pos)                           /*!< C_CAN0 CNTL: CCE Mask               */
-#define C_CAN0_CNTL_TEST_Pos                                  7                                                         /*!< C_CAN0 CNTL: TEST Position          */
-#define C_CAN0_CNTL_TEST_Msk                                  (0x01UL << C_CAN0_CNTL_TEST_Pos)                          /*!< C_CAN0 CNTL: TEST Mask              */
-
-// ---------------------------------------  C_CAN0_STAT  ------------------------------------------
-#define C_CAN0_STAT_LEC_Pos                                   0                                                         /*!< C_CAN0 STAT: LEC Position           */
-#define C_CAN0_STAT_LEC_Msk                                   (0x07UL << C_CAN0_STAT_LEC_Pos)                           /*!< C_CAN0 STAT: LEC Mask               */
-#define C_CAN0_STAT_TXOK_Pos                                  3                                                         /*!< C_CAN0 STAT: TXOK Position          */
-#define C_CAN0_STAT_TXOK_Msk                                  (0x01UL << C_CAN0_STAT_TXOK_Pos)                          /*!< C_CAN0 STAT: TXOK Mask              */
-#define C_CAN0_STAT_RXOK_Pos                                  4                                                         /*!< C_CAN0 STAT: RXOK Position          */
-#define C_CAN0_STAT_RXOK_Msk                                  (0x01UL << C_CAN0_STAT_RXOK_Pos)                          /*!< C_CAN0 STAT: RXOK Mask              */
-#define C_CAN0_STAT_EPASS_Pos                                 5                                                         /*!< C_CAN0 STAT: EPASS Position         */
-#define C_CAN0_STAT_EPASS_Msk                                 (0x01UL << C_CAN0_STAT_EPASS_Pos)                         /*!< C_CAN0 STAT: EPASS Mask             */
-#define C_CAN0_STAT_EWARN_Pos                                 6                                                         /*!< C_CAN0 STAT: EWARN Position         */
-#define C_CAN0_STAT_EWARN_Msk                                 (0x01UL << C_CAN0_STAT_EWARN_Pos)                         /*!< C_CAN0 STAT: EWARN Mask             */
-#define C_CAN0_STAT_BOFF_Pos                                  7                                                         /*!< C_CAN0 STAT: BOFF Position          */
-#define C_CAN0_STAT_BOFF_Msk                                  (0x01UL << C_CAN0_STAT_BOFF_Pos)                          /*!< C_CAN0 STAT: BOFF Mask              */
-
-// ----------------------------------------  C_CAN0_EC  -------------------------------------------
-#define C_CAN0_EC_TEC_7_0_Pos                                 0                                                         /*!< C_CAN0 EC: TEC_7_0 Position         */
-#define C_CAN0_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos)                   /*!< C_CAN0 EC: TEC_7_0 Mask             */
-#define C_CAN0_EC_REC_6_0_Pos                                 8                                                         /*!< C_CAN0 EC: REC_6_0 Position         */
-#define C_CAN0_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN0_EC_REC_6_0_Pos)                         /*!< C_CAN0 EC: REC_6_0 Mask             */
-#define C_CAN0_EC_RP_Pos                                      15                                                        /*!< C_CAN0 EC: RP Position              */
-#define C_CAN0_EC_RP_Msk                                      (0x01UL << C_CAN0_EC_RP_Pos)                              /*!< C_CAN0 EC: RP Mask                  */
-
-// ----------------------------------------  C_CAN0_BT  -------------------------------------------
-#define C_CAN0_BT_BRP_Pos                                     0                                                         /*!< C_CAN0 BT: BRP Position             */
-#define C_CAN0_BT_BRP_Msk                                     (0x3fUL << C_CAN0_BT_BRP_Pos)                             /*!< C_CAN0 BT: BRP Mask                 */
-#define C_CAN0_BT_SJW_Pos                                     6                                                         /*!< C_CAN0 BT: SJW Position             */
-#define C_CAN0_BT_SJW_Msk                                     (0x03UL << C_CAN0_BT_SJW_Pos)                             /*!< C_CAN0 BT: SJW Mask                 */
-#define C_CAN0_BT_TSEG1_Pos                                   8                                                         /*!< C_CAN0 BT: TSEG1 Position           */
-#define C_CAN0_BT_TSEG1_Msk                                   (0x0fUL << C_CAN0_BT_TSEG1_Pos)                           /*!< C_CAN0 BT: TSEG1 Mask               */
-#define C_CAN0_BT_TSEG2_Pos                                   12                                                        /*!< C_CAN0 BT: TSEG2 Position           */
-#define C_CAN0_BT_TSEG2_Msk                                   (0x07UL << C_CAN0_BT_TSEG2_Pos)                           /*!< C_CAN0 BT: TSEG2 Mask               */
-
-// ---------------------------------------  C_CAN0_INT  -------------------------------------------
-#define C_CAN0_INT_INTID15_0_Pos                              0                                                         /*!< C_CAN0 INT: INTID15_0 Position      */
-#define C_CAN0_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos)                /*!< C_CAN0 INT: INTID15_0 Mask          */
-
-// ---------------------------------------  C_CAN0_TEST  ------------------------------------------
-#define C_CAN0_TEST_BASIC_Pos                                 2                                                         /*!< C_CAN0 TEST: BASIC Position         */
-#define C_CAN0_TEST_BASIC_Msk                                 (0x01UL << C_CAN0_TEST_BASIC_Pos)                         /*!< C_CAN0 TEST: BASIC Mask             */
-#define C_CAN0_TEST_SILENT_Pos                                3                                                         /*!< C_CAN0 TEST: SILENT Position        */
-#define C_CAN0_TEST_SILENT_Msk                                (0x01UL << C_CAN0_TEST_SILENT_Pos)                        /*!< C_CAN0 TEST: SILENT Mask            */
-#define C_CAN0_TEST_LBACK_Pos                                 4                                                         /*!< C_CAN0 TEST: LBACK Position         */
-#define C_CAN0_TEST_LBACK_Msk                                 (0x01UL << C_CAN0_TEST_LBACK_Pos)                         /*!< C_CAN0 TEST: LBACK Mask             */
-#define C_CAN0_TEST_TX1_0_Pos                                 5                                                         /*!< C_CAN0 TEST: TX1_0 Position         */
-#define C_CAN0_TEST_TX1_0_Msk                                 (0x03UL << C_CAN0_TEST_TX1_0_Pos)                         /*!< C_CAN0 TEST: TX1_0 Mask             */
-#define C_CAN0_TEST_RX_Pos                                    7                                                         /*!< C_CAN0 TEST: RX Position            */
-#define C_CAN0_TEST_RX_Msk                                    (0x01UL << C_CAN0_TEST_RX_Pos)                            /*!< C_CAN0 TEST: RX Mask                */
-
-// ---------------------------------------  C_CAN0_BRPE  ------------------------------------------
-#define C_CAN0_BRPE_BRPE_Pos                                  0                                                         /*!< C_CAN0 BRPE: BRPE Position          */
-#define C_CAN0_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN0_BRPE_BRPE_Pos)                          /*!< C_CAN0 BRPE: BRPE Mask              */
-
-// ------------------------------------  C_CAN0_IF1_CMDREQ  ---------------------------------------
-#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */
-#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask     */
-#define C_CAN0_IF1_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN0 IF1_CMDREQ: BUSY Position    */
-#define C_CAN0_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos)                    /*!< C_CAN0 IF1_CMDREQ: BUSY Mask        */
-
-// -----------------------------------  C_CAN0_IF1_CMDMSK_R  --------------------------------------
-#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */
-#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask    */
-#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */
-#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask    */
-#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */
-#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask    */
-#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */
-#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */
-#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position  */
-#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask      */
-#define C_CAN0_IF1_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN0 IF1_CMDMSK_R: ARB Position   */
-#define C_CAN0_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos)                   /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask       */
-#define C_CAN0_IF1_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN0 IF1_CMDMSK_R: MASK Position  */
-#define C_CAN0_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos)                  /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask      */
-#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */
-#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask     */
-
-// -----------------------------------  C_CAN0_IF1_CMDMSK_W  --------------------------------------
-#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */
-#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask    */
-#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */
-#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask    */
-#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */
-#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask    */
-#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */
-#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */
-#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position  */
-#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask      */
-#define C_CAN0_IF1_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN0 IF1_CMDMSK_W: ARB Position   */
-#define C_CAN0_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos)                   /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask       */
-#define C_CAN0_IF1_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN0 IF1_CMDMSK_W: MASK Position  */
-#define C_CAN0_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos)                  /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask      */
-#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */
-#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask     */
-
-// -------------------------------------  C_CAN0_IF1_MSK1  ----------------------------------------
-#define C_CAN0_IF1_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN0 IF1_MSK1: MSK15_0 Position   */
-#define C_CAN0_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos)             /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask       */
-
-// -------------------------------------  C_CAN0_IF1_MSK2  ----------------------------------------
-#define C_CAN0_IF1_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN0 IF1_MSK2: MSK28_16 Position  */
-#define C_CAN0_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos)            /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask      */
-#define C_CAN0_IF1_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN0 IF1_MSK2: MDIR Position      */
-#define C_CAN0_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos)                      /*!< C_CAN0 IF1_MSK2: MDIR Mask          */
-#define C_CAN0_IF1_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN0 IF1_MSK2: MXTD Position      */
-#define C_CAN0_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos)                      /*!< C_CAN0 IF1_MSK2: MXTD Mask          */
-
-// -------------------------------------  C_CAN0_IF1_ARB1  ----------------------------------------
-#define C_CAN0_IF1_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN0 IF1_ARB1: ID15_0 Position    */
-#define C_CAN0_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos)              /*!< C_CAN0 IF1_ARB1: ID15_0 Mask        */
-
-// -------------------------------------  C_CAN0_IF1_ARB2  ----------------------------------------
-#define C_CAN0_IF1_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN0 IF1_ARB2: ID28_16 Position   */
-#define C_CAN0_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos)             /*!< C_CAN0 IF1_ARB2: ID28_16 Mask       */
-#define C_CAN0_IF1_ARB2_DIR_Pos                               13                                                        /*!< C_CAN0 IF1_ARB2: DIR Position       */
-#define C_CAN0_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos)                       /*!< C_CAN0 IF1_ARB2: DIR Mask           */
-#define C_CAN0_IF1_ARB2_XTD_Pos                               14                                                        /*!< C_CAN0 IF1_ARB2: XTD Position       */
-#define C_CAN0_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos)                       /*!< C_CAN0 IF1_ARB2: XTD Mask           */
-#define C_CAN0_IF1_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN0 IF1_ARB2: MSGVAL Position    */
-#define C_CAN0_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos)                    /*!< C_CAN0 IF1_ARB2: MSGVAL Mask        */
-
-// ------------------------------------  C_CAN0_IF1_MCTRL  ----------------------------------------
-#define C_CAN0_IF1_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position   */
-#define C_CAN0_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos)                   /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask       */
-#define C_CAN0_IF1_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN0 IF1_MCTRL: EOB Position      */
-#define C_CAN0_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos)                      /*!< C_CAN0 IF1_MCTRL: EOB Mask          */
-#define C_CAN0_IF1_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN0 IF1_MCTRL: TXRQST Position   */
-#define C_CAN0_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos)                   /*!< C_CAN0 IF1_MCTRL: TXRQST Mask       */
-#define C_CAN0_IF1_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN0 IF1_MCTRL: RMTEN Position    */
-#define C_CAN0_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos)                    /*!< C_CAN0 IF1_MCTRL: RMTEN Mask        */
-#define C_CAN0_IF1_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN0 IF1_MCTRL: RXIE Position     */
-#define C_CAN0_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos)                     /*!< C_CAN0 IF1_MCTRL: RXIE Mask         */
-#define C_CAN0_IF1_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN0 IF1_MCTRL: TXIE Position     */
-#define C_CAN0_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos)                     /*!< C_CAN0 IF1_MCTRL: TXIE Mask         */
-#define C_CAN0_IF1_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN0 IF1_MCTRL: UMASK Position    */
-#define C_CAN0_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos)                    /*!< C_CAN0 IF1_MCTRL: UMASK Mask        */
-#define C_CAN0_IF1_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN0 IF1_MCTRL: INTPND Position   */
-#define C_CAN0_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos)                   /*!< C_CAN0 IF1_MCTRL: INTPND Mask       */
-#define C_CAN0_IF1_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN0 IF1_MCTRL: MSGLST Position   */
-#define C_CAN0_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos)                   /*!< C_CAN0 IF1_MCTRL: MSGLST Mask       */
-#define C_CAN0_IF1_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN0 IF1_MCTRL: NEWDAT Position   */
-#define C_CAN0_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos)                   /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask       */
-
-// -------------------------------------  C_CAN0_IF1_DA1  -----------------------------------------
-#define C_CAN0_IF1_DA1_DATA0_Pos                              0                                                         /*!< C_CAN0 IF1_DA1: DATA0 Position      */
-#define C_CAN0_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos)                /*!< C_CAN0 IF1_DA1: DATA0 Mask          */
-#define C_CAN0_IF1_DA1_DATA1_Pos                              8                                                         /*!< C_CAN0 IF1_DA1: DATA1 Position      */
-#define C_CAN0_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos)                /*!< C_CAN0 IF1_DA1: DATA1 Mask          */
-
-// -------------------------------------  C_CAN0_IF1_DA2  -----------------------------------------
-#define C_CAN0_IF1_DA2_DATA2_Pos                              0                                                         /*!< C_CAN0 IF1_DA2: DATA2 Position      */
-#define C_CAN0_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos)                /*!< C_CAN0 IF1_DA2: DATA2 Mask          */
-#define C_CAN0_IF1_DA2_DATA3_Pos                              8                                                         /*!< C_CAN0 IF1_DA2: DATA3 Position      */
-#define C_CAN0_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos)                /*!< C_CAN0 IF1_DA2: DATA3 Mask          */
-
-// -------------------------------------  C_CAN0_IF1_DB1  -----------------------------------------
-#define C_CAN0_IF1_DB1_DATA4_Pos                              0                                                         /*!< C_CAN0 IF1_DB1: DATA4 Position      */
-#define C_CAN0_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos)                /*!< C_CAN0 IF1_DB1: DATA4 Mask          */
-#define C_CAN0_IF1_DB1_DATA5_Pos                              8                                                         /*!< C_CAN0 IF1_DB1: DATA5 Position      */
-#define C_CAN0_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos)                /*!< C_CAN0 IF1_DB1: DATA5 Mask          */
-
-// -------------------------------------  C_CAN0_IF1_DB2  -----------------------------------------
-#define C_CAN0_IF1_DB2_DATA6_Pos                              0                                                         /*!< C_CAN0 IF1_DB2: DATA6 Position      */
-#define C_CAN0_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos)                /*!< C_CAN0 IF1_DB2: DATA6 Mask          */
-#define C_CAN0_IF1_DB2_DATA7_Pos                              8                                                         /*!< C_CAN0 IF1_DB2: DATA7 Position      */
-#define C_CAN0_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos)                /*!< C_CAN0 IF1_DB2: DATA7 Mask          */
-
-// ------------------------------------  C_CAN0_IF2_CMDREQ  ---------------------------------------
-#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos                         0                                                         /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */
-#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos)                 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask     */
-#define C_CAN0_IF2_CMDREQ_BUSY_Pos                            15                                                        /*!< C_CAN0 IF2_CMDREQ: BUSY Position    */
-#define C_CAN0_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos)                    /*!< C_CAN0 IF2_CMDREQ: BUSY Mask        */
-
-// -----------------------------------  C_CAN0_IF2_CMDMSK_R  --------------------------------------
-#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */
-#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask    */
-#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */
-#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask    */
-#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos                        2                                                         /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */
-#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos)                /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask    */
-#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */
-#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos)             /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */
-#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos                          4                                                         /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position  */
-#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos)                  /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask      */
-#define C_CAN0_IF2_CMDMSK_R_ARB_Pos                           5                                                         /*!< C_CAN0 IF2_CMDMSK_R: ARB Position   */
-#define C_CAN0_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos)                   /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask       */
-#define C_CAN0_IF2_CMDMSK_R_MASK_Pos                          6                                                         /*!< C_CAN0 IF2_CMDMSK_R: MASK Position  */
-#define C_CAN0_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos)                  /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask      */
-#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */
-#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos)                 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask     */
-
-// -----------------------------------  C_CAN0_IF2_CMDMSK_W  --------------------------------------
-#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos                        0                                                         /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */
-#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask    */
-#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos                        1                                                         /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */
-#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask    */
-#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos                        2                                                         /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */
-#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos)                /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask    */
-#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos                     3                                                         /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */
-#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos)             /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */
-#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos                          4                                                         /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position  */
-#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos)                  /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask      */
-#define C_CAN0_IF2_CMDMSK_W_ARB_Pos                           5                                                         /*!< C_CAN0 IF2_CMDMSK_W: ARB Position   */
-#define C_CAN0_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos)                   /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask       */
-#define C_CAN0_IF2_CMDMSK_W_MASK_Pos                          6                                                         /*!< C_CAN0 IF2_CMDMSK_W: MASK Position  */
-#define C_CAN0_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos)                  /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask      */
-#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos                         7                                                         /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */
-#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos)                 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask     */
-
-// -------------------------------------  C_CAN0_IF2_MSK1  ----------------------------------------
-#define C_CAN0_IF2_MSK1_MSK15_0_Pos                           0                                                         /*!< C_CAN0 IF2_MSK1: MSK15_0 Position   */
-#define C_CAN0_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos)             /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask       */
-
-// -------------------------------------  C_CAN0_IF2_MSK2  ----------------------------------------
-#define C_CAN0_IF2_MSK2_MSK28_16_Pos                          0                                                         /*!< C_CAN0 IF2_MSK2: MSK28_16 Position  */
-#define C_CAN0_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos)            /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask      */
-#define C_CAN0_IF2_MSK2_MDIR_Pos                              14                                                        /*!< C_CAN0 IF2_MSK2: MDIR Position      */
-#define C_CAN0_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos)                      /*!< C_CAN0 IF2_MSK2: MDIR Mask          */
-#define C_CAN0_IF2_MSK2_MXTD_Pos                              15                                                        /*!< C_CAN0 IF2_MSK2: MXTD Position      */
-#define C_CAN0_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos)                      /*!< C_CAN0 IF2_MSK2: MXTD Mask          */
-
-// -------------------------------------  C_CAN0_IF2_ARB1  ----------------------------------------
-#define C_CAN0_IF2_ARB1_ID15_0_Pos                            0                                                         /*!< C_CAN0 IF2_ARB1: ID15_0 Position    */
-#define C_CAN0_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos)              /*!< C_CAN0 IF2_ARB1: ID15_0 Mask        */
-
-// -------------------------------------  C_CAN0_IF2_ARB2  ----------------------------------------
-#define C_CAN0_IF2_ARB2_ID28_16_Pos                           0                                                         /*!< C_CAN0 IF2_ARB2: ID28_16 Position   */
-#define C_CAN0_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos)             /*!< C_CAN0 IF2_ARB2: ID28_16 Mask       */
-#define C_CAN0_IF2_ARB2_DIR_Pos                               13                                                        /*!< C_CAN0 IF2_ARB2: DIR Position       */
-#define C_CAN0_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos)                       /*!< C_CAN0 IF2_ARB2: DIR Mask           */
-#define C_CAN0_IF2_ARB2_XTD_Pos                               14                                                        /*!< C_CAN0 IF2_ARB2: XTD Position       */
-#define C_CAN0_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos)                       /*!< C_CAN0 IF2_ARB2: XTD Mask           */
-#define C_CAN0_IF2_ARB2_MSGVAL_Pos                            15                                                        /*!< C_CAN0 IF2_ARB2: MSGVAL Position    */
-#define C_CAN0_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos)                    /*!< C_CAN0 IF2_ARB2: MSGVAL Mask        */
-
-// ------------------------------------  C_CAN0_IF2_MCTRL  ----------------------------------------
-#define C_CAN0_IF2_MCTRL_DLC3_0_Pos                           0                                                         /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position   */
-#define C_CAN0_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos)                   /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask       */
-#define C_CAN0_IF2_MCTRL_EOB_Pos                              7                                                         /*!< C_CAN0 IF2_MCTRL: EOB Position      */
-#define C_CAN0_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos)                      /*!< C_CAN0 IF2_MCTRL: EOB Mask          */
-#define C_CAN0_IF2_MCTRL_TXRQST_Pos                           8                                                         /*!< C_CAN0 IF2_MCTRL: TXRQST Position   */
-#define C_CAN0_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos)                   /*!< C_CAN0 IF2_MCTRL: TXRQST Mask       */
-#define C_CAN0_IF2_MCTRL_RMTEN_Pos                            9                                                         /*!< C_CAN0 IF2_MCTRL: RMTEN Position    */
-#define C_CAN0_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos)                    /*!< C_CAN0 IF2_MCTRL: RMTEN Mask        */
-#define C_CAN0_IF2_MCTRL_RXIE_Pos                             10                                                        /*!< C_CAN0 IF2_MCTRL: RXIE Position     */
-#define C_CAN0_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos)                     /*!< C_CAN0 IF2_MCTRL: RXIE Mask         */
-#define C_CAN0_IF2_MCTRL_TXIE_Pos                             11                                                        /*!< C_CAN0 IF2_MCTRL: TXIE Position     */
-#define C_CAN0_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos)                     /*!< C_CAN0 IF2_MCTRL: TXIE Mask         */
-#define C_CAN0_IF2_MCTRL_UMASK_Pos                            12                                                        /*!< C_CAN0 IF2_MCTRL: UMASK Position    */
-#define C_CAN0_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos)                    /*!< C_CAN0 IF2_MCTRL: UMASK Mask        */
-#define C_CAN0_IF2_MCTRL_INTPND_Pos                           13                                                        /*!< C_CAN0 IF2_MCTRL: INTPND Position   */
-#define C_CAN0_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos)                   /*!< C_CAN0 IF2_MCTRL: INTPND Mask       */
-#define C_CAN0_IF2_MCTRL_MSGLST_Pos                           14                                                        /*!< C_CAN0 IF2_MCTRL: MSGLST Position   */
-#define C_CAN0_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos)                   /*!< C_CAN0 IF2_MCTRL: MSGLST Mask       */
-#define C_CAN0_IF2_MCTRL_NEWDAT_Pos                           15                                                        /*!< C_CAN0 IF2_MCTRL: NEWDAT Position   */
-#define C_CAN0_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos)                   /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask       */
-
-// -------------------------------------  C_CAN0_IF2_DA1  -----------------------------------------
-#define C_CAN0_IF2_DA1_DATA0_Pos                              0                                                         /*!< C_CAN0 IF2_DA1: DATA0 Position      */
-#define C_CAN0_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos)                /*!< C_CAN0 IF2_DA1: DATA0 Mask          */
-#define C_CAN0_IF2_DA1_DATA1_Pos                              8                                                         /*!< C_CAN0 IF2_DA1: DATA1 Position      */
-#define C_CAN0_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos)                /*!< C_CAN0 IF2_DA1: DATA1 Mask          */
-
-// -------------------------------------  C_CAN0_IF2_DA2  -----------------------------------------
-#define C_CAN0_IF2_DA2_DATA2_Pos                              0                                                         /*!< C_CAN0 IF2_DA2: DATA2 Position      */
-#define C_CAN0_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos)                /*!< C_CAN0 IF2_DA2: DATA2 Mask          */
-#define C_CAN0_IF2_DA2_DATA3_Pos                              8                                                         /*!< C_CAN0 IF2_DA2: DATA3 Position      */
-#define C_CAN0_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos)                /*!< C_CAN0 IF2_DA2: DATA3 Mask          */
-
-// -------------------------------------  C_CAN0_IF2_DB1  -----------------------------------------
-#define C_CAN0_IF2_DB1_DATA4_Pos                              0                                                         /*!< C_CAN0 IF2_DB1: DATA4 Position      */
-#define C_CAN0_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos)                /*!< C_CAN0 IF2_DB1: DATA4 Mask          */
-#define C_CAN0_IF2_DB1_DATA5_Pos                              8                                                         /*!< C_CAN0 IF2_DB1: DATA5 Position      */
-#define C_CAN0_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos)                /*!< C_CAN0 IF2_DB1: DATA5 Mask          */
-
-// -------------------------------------  C_CAN0_IF2_DB2  -----------------------------------------
-#define C_CAN0_IF2_DB2_DATA6_Pos                              0                                                         /*!< C_CAN0 IF2_DB2: DATA6 Position      */
-#define C_CAN0_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos)                /*!< C_CAN0 IF2_DB2: DATA6 Mask          */
-#define C_CAN0_IF2_DB2_DATA7_Pos                              8                                                         /*!< C_CAN0 IF2_DB2: DATA7 Position      */
-#define C_CAN0_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos)                /*!< C_CAN0 IF2_DB2: DATA7 Mask          */
-
-// --------------------------------------  C_CAN0_TXREQ1  -----------------------------------------
-#define C_CAN0_TXREQ1_TXRQST16_1_Pos                          0                                                         /*!< C_CAN0 TXREQ1: TXRQST16_1 Position  */
-#define C_CAN0_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos)            /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask      */
-
-// --------------------------------------  C_CAN0_TXREQ2  -----------------------------------------
-#define C_CAN0_TXREQ2_TXRQST32_17_Pos                         0                                                         /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */
-#define C_CAN0_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos)           /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask     */
-
-// ---------------------------------------  C_CAN0_ND1  -------------------------------------------
-#define C_CAN0_ND1_NEWDAT16_1_Pos                             0                                                         /*!< C_CAN0 ND1: NEWDAT16_1 Position     */
-#define C_CAN0_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos)               /*!< C_CAN0 ND1: NEWDAT16_1 Mask         */
-
-// ---------------------------------------  C_CAN0_ND2  -------------------------------------------
-#define C_CAN0_ND2_NEWDAT32_17_Pos                            0                                                         /*!< C_CAN0 ND2: NEWDAT32_17 Position    */
-#define C_CAN0_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos)              /*!< C_CAN0 ND2: NEWDAT32_17 Mask        */
-
-// ---------------------------------------  C_CAN0_IR1  -------------------------------------------
-#define C_CAN0_IR1_INTPND16_1_Pos                             0                                                         /*!< C_CAN0 IR1: INTPND16_1 Position     */
-#define C_CAN0_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos)               /*!< C_CAN0 IR1: INTPND16_1 Mask         */
-
-// ---------------------------------------  C_CAN0_IR2  -------------------------------------------
-#define C_CAN0_IR2_INTPND32_17_Pos                            0                                                         /*!< C_CAN0 IR2: INTPND32_17 Position    */
-#define C_CAN0_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos)              /*!< C_CAN0 IR2: INTPND32_17 Mask        */
-
-// --------------------------------------  C_CAN0_MSGV1  ------------------------------------------
-#define C_CAN0_MSGV1_MSGVAL16_1_Pos                           0                                                         /*!< C_CAN0 MSGV1: MSGVAL16_1 Position   */
-#define C_CAN0_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos)             /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask       */
-
-// --------------------------------------  C_CAN0_MSGV2  ------------------------------------------
-#define C_CAN0_MSGV2_MSGVAL32_17_Pos                          0                                                         /*!< C_CAN0 MSGV2: MSGVAL32_17 Position  */
-#define C_CAN0_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos)            /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask      */
-
-// --------------------------------------  C_CAN0_CLKDIV  -----------------------------------------
-#define C_CAN0_CLKDIV_CLKDIVVAL_Pos                           0                                                         /*!< C_CAN0 CLKDIV: CLKDIVVAL Position   */
-#define C_CAN0_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos)                   /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask       */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 ADC0 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------------  ADC0_CR  --------------------------------------------
-#define ADC0_CR_SEL_Pos                                       0                                                         /*!< ADC0 CR: SEL Position               */
-#define ADC0_CR_SEL_Msk                                       (0x000000ffUL << ADC0_CR_SEL_Pos)                         /*!< ADC0 CR: SEL Mask                   */
-#define ADC0_CR_CLKDIV_Pos                                    8                                                         /*!< ADC0 CR: CLKDIV Position            */
-#define ADC0_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC0_CR_CLKDIV_Pos)                      /*!< ADC0 CR: CLKDIV Mask                */
-#define ADC0_CR_BURST_Pos                                     16                                                        /*!< ADC0 CR: BURST Position             */
-#define ADC0_CR_BURST_Msk                                     (0x01UL << ADC0_CR_BURST_Pos)                             /*!< ADC0 CR: BURST Mask                 */
-#define ADC0_CR_CLKS_Pos                                      17                                                        /*!< ADC0 CR: CLKS Position              */
-#define ADC0_CR_CLKS_Msk                                      (0x07UL << ADC0_CR_CLKS_Pos)                              /*!< ADC0 CR: CLKS Mask                  */
-#define ADC0_CR_PDN_Pos                                       21                                                        /*!< ADC0 CR: PDN Position               */
-#define ADC0_CR_PDN_Msk                                       (0x01UL << ADC0_CR_PDN_Pos)                               /*!< ADC0 CR: PDN Mask                   */
-#define ADC0_CR_START_Pos                                     24                                                        /*!< ADC0 CR: START Position             */
-#define ADC0_CR_START_Msk                                     (0x07UL << ADC0_CR_START_Pos)                             /*!< ADC0 CR: START Mask                 */
-#define ADC0_CR_EDGE_Pos                                      27                                                        /*!< ADC0 CR: EDGE Position              */
-#define ADC0_CR_EDGE_Msk                                      (0x01UL << ADC0_CR_EDGE_Pos)                              /*!< ADC0 CR: EDGE Mask                  */
-
-// ----------------------------------------  ADC0_GDR  --------------------------------------------
-#define ADC0_GDR_V_VREF_Pos                                   6                                                         /*!< ADC0 GDR: V_VREF Position           */
-#define ADC0_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC0_GDR_V_VREF_Pos)                     /*!< ADC0 GDR: V_VREF Mask               */
-#define ADC0_GDR_CHN_Pos                                      24                                                        /*!< ADC0 GDR: CHN Position              */
-#define ADC0_GDR_CHN_Msk                                      (0x07UL << ADC0_GDR_CHN_Pos)                              /*!< ADC0 GDR: CHN Mask                  */
-#define ADC0_GDR_OVERRUN_Pos                                  30                                                        /*!< ADC0 GDR: OVERRUN Position          */
-#define ADC0_GDR_OVERRUN_Msk                                  (0x01UL << ADC0_GDR_OVERRUN_Pos)                          /*!< ADC0 GDR: OVERRUN Mask              */
-#define ADC0_GDR_DONE_Pos                                     31                                                        /*!< ADC0 GDR: DONE Position             */
-#define ADC0_GDR_DONE_Msk                                     (0x01UL << ADC0_GDR_DONE_Pos)                             /*!< ADC0 GDR: DONE Mask                 */
-
-// ---------------------------------------  ADC0_INTEN  -------------------------------------------
-#define ADC0_INTEN_ADINTEN_Pos                                0                                                         /*!< ADC0 INTEN: ADINTEN Position        */
-#define ADC0_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos)                  /*!< ADC0 INTEN: ADINTEN Mask            */
-#define ADC0_INTEN_ADGINTEN_Pos                               8                                                         /*!< ADC0 INTEN: ADGINTEN Position       */
-#define ADC0_INTEN_ADGINTEN_Msk                               (0x01UL << ADC0_INTEN_ADGINTEN_Pos)                       /*!< ADC0 INTEN: ADGINTEN Mask           */
-
-// ----------------------------------------  ADC0_DR0  --------------------------------------------
-#define ADC0_DR0_V_VREF_Pos                                   6                                                         /*!< ADC0 DR0: V_VREF Position           */
-#define ADC0_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR0_V_VREF_Pos)                     /*!< ADC0 DR0: V_VREF Mask               */
-#define ADC0_DR0_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR0: OVERRUN Position          */
-#define ADC0_DR0_OVERRUN_Msk                                  (0x01UL << ADC0_DR0_OVERRUN_Pos)                          /*!< ADC0 DR0: OVERRUN Mask              */
-#define ADC0_DR0_DONE_Pos                                     31                                                        /*!< ADC0 DR0: DONE Position             */
-#define ADC0_DR0_DONE_Msk                                     (0x01UL << ADC0_DR0_DONE_Pos)                             /*!< ADC0 DR0: DONE Mask                 */
-
-// ----------------------------------------  ADC0_DR1  --------------------------------------------
-#define ADC0_DR1_V_VREF_Pos                                   6                                                         /*!< ADC0 DR1: V_VREF Position           */
-#define ADC0_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR1_V_VREF_Pos)                     /*!< ADC0 DR1: V_VREF Mask               */
-#define ADC0_DR1_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR1: OVERRUN Position          */
-#define ADC0_DR1_OVERRUN_Msk                                  (0x01UL << ADC0_DR1_OVERRUN_Pos)                          /*!< ADC0 DR1: OVERRUN Mask              */
-#define ADC0_DR1_DONE_Pos                                     31                                                        /*!< ADC0 DR1: DONE Position             */
-#define ADC0_DR1_DONE_Msk                                     (0x01UL << ADC0_DR1_DONE_Pos)                             /*!< ADC0 DR1: DONE Mask                 */
-
-// ----------------------------------------  ADC0_DR2  --------------------------------------------
-#define ADC0_DR2_V_VREF_Pos                                   6                                                         /*!< ADC0 DR2: V_VREF Position           */
-#define ADC0_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR2_V_VREF_Pos)                     /*!< ADC0 DR2: V_VREF Mask               */
-#define ADC0_DR2_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR2: OVERRUN Position          */
-#define ADC0_DR2_OVERRUN_Msk                                  (0x01UL << ADC0_DR2_OVERRUN_Pos)                          /*!< ADC0 DR2: OVERRUN Mask              */
-#define ADC0_DR2_DONE_Pos                                     31                                                        /*!< ADC0 DR2: DONE Position             */
-#define ADC0_DR2_DONE_Msk                                     (0x01UL << ADC0_DR2_DONE_Pos)                             /*!< ADC0 DR2: DONE Mask                 */
-
-// ----------------------------------------  ADC0_DR3  --------------------------------------------
-#define ADC0_DR3_V_VREF_Pos                                   6                                                         /*!< ADC0 DR3: V_VREF Position           */
-#define ADC0_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR3_V_VREF_Pos)                     /*!< ADC0 DR3: V_VREF Mask               */
-#define ADC0_DR3_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR3: OVERRUN Position          */
-#define ADC0_DR3_OVERRUN_Msk                                  (0x01UL << ADC0_DR3_OVERRUN_Pos)                          /*!< ADC0 DR3: OVERRUN Mask              */
-#define ADC0_DR3_DONE_Pos                                     31                                                        /*!< ADC0 DR3: DONE Position             */
-#define ADC0_DR3_DONE_Msk                                     (0x01UL << ADC0_DR3_DONE_Pos)                             /*!< ADC0 DR3: DONE Mask                 */
-
-// ----------------------------------------  ADC0_DR4  --------------------------------------------
-#define ADC0_DR4_V_VREF_Pos                                   6                                                         /*!< ADC0 DR4: V_VREF Position           */
-#define ADC0_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR4_V_VREF_Pos)                     /*!< ADC0 DR4: V_VREF Mask               */
-#define ADC0_DR4_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR4: OVERRUN Position          */
-#define ADC0_DR4_OVERRUN_Msk                                  (0x01UL << ADC0_DR4_OVERRUN_Pos)                          /*!< ADC0 DR4: OVERRUN Mask              */
-#define ADC0_DR4_DONE_Pos                                     31                                                        /*!< ADC0 DR4: DONE Position             */
-#define ADC0_DR4_DONE_Msk                                     (0x01UL << ADC0_DR4_DONE_Pos)                             /*!< ADC0 DR4: DONE Mask                 */
-
-// ----------------------------------------  ADC0_DR5  --------------------------------------------
-#define ADC0_DR5_V_VREF_Pos                                   6                                                         /*!< ADC0 DR5: V_VREF Position           */
-#define ADC0_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR5_V_VREF_Pos)                     /*!< ADC0 DR5: V_VREF Mask               */
-#define ADC0_DR5_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR5: OVERRUN Position          */
-#define ADC0_DR5_OVERRUN_Msk                                  (0x01UL << ADC0_DR5_OVERRUN_Pos)                          /*!< ADC0 DR5: OVERRUN Mask              */
-#define ADC0_DR5_DONE_Pos                                     31                                                        /*!< ADC0 DR5: DONE Position             */
-#define ADC0_DR5_DONE_Msk                                     (0x01UL << ADC0_DR5_DONE_Pos)                             /*!< ADC0 DR5: DONE Mask                 */
-
-// ----------------------------------------  ADC0_DR6  --------------------------------------------
-#define ADC0_DR6_V_VREF_Pos                                   6                                                         /*!< ADC0 DR6: V_VREF Position           */
-#define ADC0_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR6_V_VREF_Pos)                     /*!< ADC0 DR6: V_VREF Mask               */
-#define ADC0_DR6_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR6: OVERRUN Position          */
-#define ADC0_DR6_OVERRUN_Msk                                  (0x01UL << ADC0_DR6_OVERRUN_Pos)                          /*!< ADC0 DR6: OVERRUN Mask              */
-#define ADC0_DR6_DONE_Pos                                     31                                                        /*!< ADC0 DR6: DONE Position             */
-#define ADC0_DR6_DONE_Msk                                     (0x01UL << ADC0_DR6_DONE_Pos)                             /*!< ADC0 DR6: DONE Mask                 */
-
-// ----------------------------------------  ADC0_DR7  --------------------------------------------
-#define ADC0_DR7_V_VREF_Pos                                   6                                                         /*!< ADC0 DR7: V_VREF Position           */
-#define ADC0_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR7_V_VREF_Pos)                     /*!< ADC0 DR7: V_VREF Mask               */
-#define ADC0_DR7_OVERRUN_Pos                                  30                                                        /*!< ADC0 DR7: OVERRUN Position          */
-#define ADC0_DR7_OVERRUN_Msk                                  (0x01UL << ADC0_DR7_OVERRUN_Pos)                          /*!< ADC0 DR7: OVERRUN Mask              */
-#define ADC0_DR7_DONE_Pos                                     31                                                        /*!< ADC0 DR7: DONE Position             */
-#define ADC0_DR7_DONE_Msk                                     (0x01UL << ADC0_DR7_DONE_Pos)                             /*!< ADC0 DR7: DONE Mask                 */
-
-// ----------------------------------------  ADC0_STAT  -------------------------------------------
-#define ADC0_STAT_DONE_Pos                                    0                                                         /*!< ADC0 STAT: DONE Position            */
-#define ADC0_STAT_DONE_Msk                                    (0x000000ffUL << ADC0_STAT_DONE_Pos)                      /*!< ADC0 STAT: DONE Mask                */
-#define ADC0_STAT_OVERUN_Pos                                  8                                                         /*!< ADC0 STAT: OVERUN Position          */
-#define ADC0_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC0_STAT_OVERUN_Pos)                    /*!< ADC0 STAT: OVERUN Mask              */
-#define ADC0_STAT_ADINT_Pos                                   16                                                        /*!< ADC0 STAT: ADINT Position           */
-#define ADC0_STAT_ADINT_Msk                                   (0x01UL << ADC0_STAT_ADINT_Pos)                           /*!< ADC0 STAT: ADINT Mask               */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 ADC1 Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------------  ADC1_CR  --------------------------------------------
-#define ADC1_CR_SEL_Pos                                       0                                                         /*!< ADC1 CR: SEL Position               */
-#define ADC1_CR_SEL_Msk                                       (0x000000ffUL << ADC1_CR_SEL_Pos)                         /*!< ADC1 CR: SEL Mask                   */
-#define ADC1_CR_CLKDIV_Pos                                    8                                                         /*!< ADC1 CR: CLKDIV Position            */
-#define ADC1_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC1_CR_CLKDIV_Pos)                      /*!< ADC1 CR: CLKDIV Mask                */
-#define ADC1_CR_BURST_Pos                                     16                                                        /*!< ADC1 CR: BURST Position             */
-#define ADC1_CR_BURST_Msk                                     (0x01UL << ADC1_CR_BURST_Pos)                             /*!< ADC1 CR: BURST Mask                 */
-#define ADC1_CR_CLKS_Pos                                      17                                                        /*!< ADC1 CR: CLKS Position              */
-#define ADC1_CR_CLKS_Msk                                      (0x07UL << ADC1_CR_CLKS_Pos)                              /*!< ADC1 CR: CLKS Mask                  */
-#define ADC1_CR_PDN_Pos                                       21                                                        /*!< ADC1 CR: PDN Position               */
-#define ADC1_CR_PDN_Msk                                       (0x01UL << ADC1_CR_PDN_Pos)                               /*!< ADC1 CR: PDN Mask                   */
-#define ADC1_CR_START_Pos                                     24                                                        /*!< ADC1 CR: START Position             */
-#define ADC1_CR_START_Msk                                     (0x07UL << ADC1_CR_START_Pos)                             /*!< ADC1 CR: START Mask                 */
-#define ADC1_CR_EDGE_Pos                                      27                                                        /*!< ADC1 CR: EDGE Position              */
-#define ADC1_CR_EDGE_Msk                                      (0x01UL << ADC1_CR_EDGE_Pos)                              /*!< ADC1 CR: EDGE Mask                  */
-
-// ----------------------------------------  ADC1_GDR  --------------------------------------------
-#define ADC1_GDR_V_VREF_Pos                                   6                                                         /*!< ADC1 GDR: V_VREF Position           */
-#define ADC1_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC1_GDR_V_VREF_Pos)                     /*!< ADC1 GDR: V_VREF Mask               */
-#define ADC1_GDR_CHN_Pos                                      24                                                        /*!< ADC1 GDR: CHN Position              */
-#define ADC1_GDR_CHN_Msk                                      (0x07UL << ADC1_GDR_CHN_Pos)                              /*!< ADC1 GDR: CHN Mask                  */
-#define ADC1_GDR_OVERRUN_Pos                                  30                                                        /*!< ADC1 GDR: OVERRUN Position          */
-#define ADC1_GDR_OVERRUN_Msk                                  (0x01UL << ADC1_GDR_OVERRUN_Pos)                          /*!< ADC1 GDR: OVERRUN Mask              */
-#define ADC1_GDR_DONE_Pos                                     31                                                        /*!< ADC1 GDR: DONE Position             */
-#define ADC1_GDR_DONE_Msk                                     (0x01UL << ADC1_GDR_DONE_Pos)                             /*!< ADC1 GDR: DONE Mask                 */
-
-// ---------------------------------------  ADC1_INTEN  -------------------------------------------
-#define ADC1_INTEN_ADINTEN_Pos                                0                                                         /*!< ADC1 INTEN: ADINTEN Position        */
-#define ADC1_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos)                  /*!< ADC1 INTEN: ADINTEN Mask            */
-#define ADC1_INTEN_ADGINTEN_Pos                               8                                                         /*!< ADC1 INTEN: ADGINTEN Position       */
-#define ADC1_INTEN_ADGINTEN_Msk                               (0x01UL << ADC1_INTEN_ADGINTEN_Pos)                       /*!< ADC1 INTEN: ADGINTEN Mask           */
-
-// ----------------------------------------  ADC1_DR0  --------------------------------------------
-#define ADC1_DR0_V_VREF_Pos                                   6                                                         /*!< ADC1 DR0: V_VREF Position           */
-#define ADC1_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR0_V_VREF_Pos)                     /*!< ADC1 DR0: V_VREF Mask               */
-#define ADC1_DR0_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR0: OVERRUN Position          */
-#define ADC1_DR0_OVERRUN_Msk                                  (0x01UL << ADC1_DR0_OVERRUN_Pos)                          /*!< ADC1 DR0: OVERRUN Mask              */
-#define ADC1_DR0_DONE_Pos                                     31                                                        /*!< ADC1 DR0: DONE Position             */
-#define ADC1_DR0_DONE_Msk                                     (0x01UL << ADC1_DR0_DONE_Pos)                             /*!< ADC1 DR0: DONE Mask                 */
-
-// ----------------------------------------  ADC1_DR1  --------------------------------------------
-#define ADC1_DR1_V_VREF_Pos                                   6                                                         /*!< ADC1 DR1: V_VREF Position           */
-#define ADC1_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR1_V_VREF_Pos)                     /*!< ADC1 DR1: V_VREF Mask               */
-#define ADC1_DR1_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR1: OVERRUN Position          */
-#define ADC1_DR1_OVERRUN_Msk                                  (0x01UL << ADC1_DR1_OVERRUN_Pos)                          /*!< ADC1 DR1: OVERRUN Mask              */
-#define ADC1_DR1_DONE_Pos                                     31                                                        /*!< ADC1 DR1: DONE Position             */
-#define ADC1_DR1_DONE_Msk                                     (0x01UL << ADC1_DR1_DONE_Pos)                             /*!< ADC1 DR1: DONE Mask                 */
-
-// ----------------------------------------  ADC1_DR2  --------------------------------------------
-#define ADC1_DR2_V_VREF_Pos                                   6                                                         /*!< ADC1 DR2: V_VREF Position           */
-#define ADC1_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR2_V_VREF_Pos)                     /*!< ADC1 DR2: V_VREF Mask               */
-#define ADC1_DR2_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR2: OVERRUN Position          */
-#define ADC1_DR2_OVERRUN_Msk                                  (0x01UL << ADC1_DR2_OVERRUN_Pos)                          /*!< ADC1 DR2: OVERRUN Mask              */
-#define ADC1_DR2_DONE_Pos                                     31                                                        /*!< ADC1 DR2: DONE Position             */
-#define ADC1_DR2_DONE_Msk                                     (0x01UL << ADC1_DR2_DONE_Pos)                             /*!< ADC1 DR2: DONE Mask                 */
-
-// ----------------------------------------  ADC1_DR3  --------------------------------------------
-#define ADC1_DR3_V_VREF_Pos                                   6                                                         /*!< ADC1 DR3: V_VREF Position           */
-#define ADC1_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR3_V_VREF_Pos)                     /*!< ADC1 DR3: V_VREF Mask               */
-#define ADC1_DR3_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR3: OVERRUN Position          */
-#define ADC1_DR3_OVERRUN_Msk                                  (0x01UL << ADC1_DR3_OVERRUN_Pos)                          /*!< ADC1 DR3: OVERRUN Mask              */
-#define ADC1_DR3_DONE_Pos                                     31                                                        /*!< ADC1 DR3: DONE Position             */
-#define ADC1_DR3_DONE_Msk                                     (0x01UL << ADC1_DR3_DONE_Pos)                             /*!< ADC1 DR3: DONE Mask                 */
-
-// ----------------------------------------  ADC1_DR4  --------------------------------------------
-#define ADC1_DR4_V_VREF_Pos                                   6                                                         /*!< ADC1 DR4: V_VREF Position           */
-#define ADC1_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR4_V_VREF_Pos)                     /*!< ADC1 DR4: V_VREF Mask               */
-#define ADC1_DR4_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR4: OVERRUN Position          */
-#define ADC1_DR4_OVERRUN_Msk                                  (0x01UL << ADC1_DR4_OVERRUN_Pos)                          /*!< ADC1 DR4: OVERRUN Mask              */
-#define ADC1_DR4_DONE_Pos                                     31                                                        /*!< ADC1 DR4: DONE Position             */
-#define ADC1_DR4_DONE_Msk                                     (0x01UL << ADC1_DR4_DONE_Pos)                             /*!< ADC1 DR4: DONE Mask                 */
-
-// ----------------------------------------  ADC1_DR5  --------------------------------------------
-#define ADC1_DR5_V_VREF_Pos                                   6                                                         /*!< ADC1 DR5: V_VREF Position           */
-#define ADC1_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR5_V_VREF_Pos)                     /*!< ADC1 DR5: V_VREF Mask               */
-#define ADC1_DR5_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR5: OVERRUN Position          */
-#define ADC1_DR5_OVERRUN_Msk                                  (0x01UL << ADC1_DR5_OVERRUN_Pos)                          /*!< ADC1 DR5: OVERRUN Mask              */
-#define ADC1_DR5_DONE_Pos                                     31                                                        /*!< ADC1 DR5: DONE Position             */
-#define ADC1_DR5_DONE_Msk                                     (0x01UL << ADC1_DR5_DONE_Pos)                             /*!< ADC1 DR5: DONE Mask                 */
-
-// ----------------------------------------  ADC1_DR6  --------------------------------------------
-#define ADC1_DR6_V_VREF_Pos                                   6                                                         /*!< ADC1 DR6: V_VREF Position           */
-#define ADC1_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR6_V_VREF_Pos)                     /*!< ADC1 DR6: V_VREF Mask               */
-#define ADC1_DR6_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR6: OVERRUN Position          */
-#define ADC1_DR6_OVERRUN_Msk                                  (0x01UL << ADC1_DR6_OVERRUN_Pos)                          /*!< ADC1 DR6: OVERRUN Mask              */
-#define ADC1_DR6_DONE_Pos                                     31                                                        /*!< ADC1 DR6: DONE Position             */
-#define ADC1_DR6_DONE_Msk                                     (0x01UL << ADC1_DR6_DONE_Pos)                             /*!< ADC1 DR6: DONE Mask                 */
-
-// ----------------------------------------  ADC1_DR7  --------------------------------------------
-#define ADC1_DR7_V_VREF_Pos                                   6                                                         /*!< ADC1 DR7: V_VREF Position           */
-#define ADC1_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR7_V_VREF_Pos)                     /*!< ADC1 DR7: V_VREF Mask               */
-#define ADC1_DR7_OVERRUN_Pos                                  30                                                        /*!< ADC1 DR7: OVERRUN Position          */
-#define ADC1_DR7_OVERRUN_Msk                                  (0x01UL << ADC1_DR7_OVERRUN_Pos)                          /*!< ADC1 DR7: OVERRUN Mask              */
-#define ADC1_DR7_DONE_Pos                                     31                                                        /*!< ADC1 DR7: DONE Position             */
-#define ADC1_DR7_DONE_Msk                                     (0x01UL << ADC1_DR7_DONE_Pos)                             /*!< ADC1 DR7: DONE Mask                 */
-
-// ----------------------------------------  ADC1_STAT  -------------------------------------------
-#define ADC1_STAT_DONE_Pos                                    0                                                         /*!< ADC1 STAT: DONE Position            */
-#define ADC1_STAT_DONE_Msk                                    (0x000000ffUL << ADC1_STAT_DONE_Pos)                      /*!< ADC1 STAT: DONE Mask                */
-#define ADC1_STAT_OVERUN_Pos                                  8                                                         /*!< ADC1 STAT: OVERUN Position          */
-#define ADC1_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC1_STAT_OVERUN_Pos)                    /*!< ADC1 STAT: OVERUN Mask              */
-#define ADC1_STAT_ADINT_Pos                                   16                                                        /*!< ADC1 STAT: ADINT Position           */
-#define ADC1_STAT_ADINT_Msk                                   (0x01UL << ADC1_STAT_ADINT_Pos)                           /*!< ADC1 STAT: ADINT Mask               */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                               GPIO_PORT Position & Mask                              -----
-// ------------------------------------------------------------------------------------------------
-
-
-// --------------------------------------  GPIO_PORT_B0  ------------------------------------------
-#define GPIO_PORT_B0_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B0: PBYTE Position        */
-#define GPIO_PORT_B0_PBYTE_Msk                                (0x01UL << GPIO_PORT_B0_PBYTE_Pos)                        /*!< GPIO_PORT B0: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B1  ------------------------------------------
-#define GPIO_PORT_B1_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B1: PBYTE Position        */
-#define GPIO_PORT_B1_PBYTE_Msk                                (0x01UL << GPIO_PORT_B1_PBYTE_Pos)                        /*!< GPIO_PORT B1: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B2  ------------------------------------------
-#define GPIO_PORT_B2_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B2: PBYTE Position        */
-#define GPIO_PORT_B2_PBYTE_Msk                                (0x01UL << GPIO_PORT_B2_PBYTE_Pos)                        /*!< GPIO_PORT B2: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B3  ------------------------------------------
-#define GPIO_PORT_B3_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B3: PBYTE Position        */
-#define GPIO_PORT_B3_PBYTE_Msk                                (0x01UL << GPIO_PORT_B3_PBYTE_Pos)                        /*!< GPIO_PORT B3: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B4  ------------------------------------------
-#define GPIO_PORT_B4_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B4: PBYTE Position        */
-#define GPIO_PORT_B4_PBYTE_Msk                                (0x01UL << GPIO_PORT_B4_PBYTE_Pos)                        /*!< GPIO_PORT B4: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B5  ------------------------------------------
-#define GPIO_PORT_B5_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B5: PBYTE Position        */
-#define GPIO_PORT_B5_PBYTE_Msk                                (0x01UL << GPIO_PORT_B5_PBYTE_Pos)                        /*!< GPIO_PORT B5: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B6  ------------------------------------------
-#define GPIO_PORT_B6_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B6: PBYTE Position        */
-#define GPIO_PORT_B6_PBYTE_Msk                                (0x01UL << GPIO_PORT_B6_PBYTE_Pos)                        /*!< GPIO_PORT B6: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B7  ------------------------------------------
-#define GPIO_PORT_B7_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B7: PBYTE Position        */
-#define GPIO_PORT_B7_PBYTE_Msk                                (0x01UL << GPIO_PORT_B7_PBYTE_Pos)                        /*!< GPIO_PORT B7: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B8  ------------------------------------------
-#define GPIO_PORT_B8_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B8: PBYTE Position        */
-#define GPIO_PORT_B8_PBYTE_Msk                                (0x01UL << GPIO_PORT_B8_PBYTE_Pos)                        /*!< GPIO_PORT B8: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B9  ------------------------------------------
-#define GPIO_PORT_B9_PBYTE_Pos                                0                                                         /*!< GPIO_PORT B9: PBYTE Position        */
-#define GPIO_PORT_B9_PBYTE_Msk                                (0x01UL << GPIO_PORT_B9_PBYTE_Pos)                        /*!< GPIO_PORT B9: PBYTE Mask            */
-
-// --------------------------------------  GPIO_PORT_B10  -----------------------------------------
-#define GPIO_PORT_B10_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B10: PBYTE Position       */
-#define GPIO_PORT_B10_PBYTE_Msk                               (0x01UL << GPIO_PORT_B10_PBYTE_Pos)                       /*!< GPIO_PORT B10: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B11  -----------------------------------------
-#define GPIO_PORT_B11_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B11: PBYTE Position       */
-#define GPIO_PORT_B11_PBYTE_Msk                               (0x01UL << GPIO_PORT_B11_PBYTE_Pos)                       /*!< GPIO_PORT B11: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B12  -----------------------------------------
-#define GPIO_PORT_B12_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B12: PBYTE Position       */
-#define GPIO_PORT_B12_PBYTE_Msk                               (0x01UL << GPIO_PORT_B12_PBYTE_Pos)                       /*!< GPIO_PORT B12: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B13  -----------------------------------------
-#define GPIO_PORT_B13_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B13: PBYTE Position       */
-#define GPIO_PORT_B13_PBYTE_Msk                               (0x01UL << GPIO_PORT_B13_PBYTE_Pos)                       /*!< GPIO_PORT B13: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B14  -----------------------------------------
-#define GPIO_PORT_B14_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B14: PBYTE Position       */
-#define GPIO_PORT_B14_PBYTE_Msk                               (0x01UL << GPIO_PORT_B14_PBYTE_Pos)                       /*!< GPIO_PORT B14: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B15  -----------------------------------------
-#define GPIO_PORT_B15_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B15: PBYTE Position       */
-#define GPIO_PORT_B15_PBYTE_Msk                               (0x01UL << GPIO_PORT_B15_PBYTE_Pos)                       /*!< GPIO_PORT B15: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B16  -----------------------------------------
-#define GPIO_PORT_B16_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B16: PBYTE Position       */
-#define GPIO_PORT_B16_PBYTE_Msk                               (0x01UL << GPIO_PORT_B16_PBYTE_Pos)                       /*!< GPIO_PORT B16: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B17  -----------------------------------------
-#define GPIO_PORT_B17_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B17: PBYTE Position       */
-#define GPIO_PORT_B17_PBYTE_Msk                               (0x01UL << GPIO_PORT_B17_PBYTE_Pos)                       /*!< GPIO_PORT B17: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B18  -----------------------------------------
-#define GPIO_PORT_B18_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B18: PBYTE Position       */
-#define GPIO_PORT_B18_PBYTE_Msk                               (0x01UL << GPIO_PORT_B18_PBYTE_Pos)                       /*!< GPIO_PORT B18: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B19  -----------------------------------------
-#define GPIO_PORT_B19_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B19: PBYTE Position       */
-#define GPIO_PORT_B19_PBYTE_Msk                               (0x01UL << GPIO_PORT_B19_PBYTE_Pos)                       /*!< GPIO_PORT B19: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B20  -----------------------------------------
-#define GPIO_PORT_B20_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B20: PBYTE Position       */
-#define GPIO_PORT_B20_PBYTE_Msk                               (0x01UL << GPIO_PORT_B20_PBYTE_Pos)                       /*!< GPIO_PORT B20: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B21  -----------------------------------------
-#define GPIO_PORT_B21_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B21: PBYTE Position       */
-#define GPIO_PORT_B21_PBYTE_Msk                               (0x01UL << GPIO_PORT_B21_PBYTE_Pos)                       /*!< GPIO_PORT B21: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B22  -----------------------------------------
-#define GPIO_PORT_B22_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B22: PBYTE Position       */
-#define GPIO_PORT_B22_PBYTE_Msk                               (0x01UL << GPIO_PORT_B22_PBYTE_Pos)                       /*!< GPIO_PORT B22: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B23  -----------------------------------------
-#define GPIO_PORT_B23_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B23: PBYTE Position       */
-#define GPIO_PORT_B23_PBYTE_Msk                               (0x01UL << GPIO_PORT_B23_PBYTE_Pos)                       /*!< GPIO_PORT B23: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B24  -----------------------------------------
-#define GPIO_PORT_B24_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B24: PBYTE Position       */
-#define GPIO_PORT_B24_PBYTE_Msk                               (0x01UL << GPIO_PORT_B24_PBYTE_Pos)                       /*!< GPIO_PORT B24: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B25  -----------------------------------------
-#define GPIO_PORT_B25_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B25: PBYTE Position       */
-#define GPIO_PORT_B25_PBYTE_Msk                               (0x01UL << GPIO_PORT_B25_PBYTE_Pos)                       /*!< GPIO_PORT B25: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B26  -----------------------------------------
-#define GPIO_PORT_B26_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B26: PBYTE Position       */
-#define GPIO_PORT_B26_PBYTE_Msk                               (0x01UL << GPIO_PORT_B26_PBYTE_Pos)                       /*!< GPIO_PORT B26: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B27  -----------------------------------------
-#define GPIO_PORT_B27_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B27: PBYTE Position       */
-#define GPIO_PORT_B27_PBYTE_Msk                               (0x01UL << GPIO_PORT_B27_PBYTE_Pos)                       /*!< GPIO_PORT B27: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B28  -----------------------------------------
-#define GPIO_PORT_B28_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B28: PBYTE Position       */
-#define GPIO_PORT_B28_PBYTE_Msk                               (0x01UL << GPIO_PORT_B28_PBYTE_Pos)                       /*!< GPIO_PORT B28: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B29  -----------------------------------------
-#define GPIO_PORT_B29_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B29: PBYTE Position       */
-#define GPIO_PORT_B29_PBYTE_Msk                               (0x01UL << GPIO_PORT_B29_PBYTE_Pos)                       /*!< GPIO_PORT B29: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B30  -----------------------------------------
-#define GPIO_PORT_B30_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B30: PBYTE Position       */
-#define GPIO_PORT_B30_PBYTE_Msk                               (0x01UL << GPIO_PORT_B30_PBYTE_Pos)                       /*!< GPIO_PORT B30: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B31  -----------------------------------------
-#define GPIO_PORT_B31_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B31: PBYTE Position       */
-#define GPIO_PORT_B31_PBYTE_Msk                               (0x01UL << GPIO_PORT_B31_PBYTE_Pos)                       /*!< GPIO_PORT B31: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B32  -----------------------------------------
-#define GPIO_PORT_B32_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B32: PBYTE Position       */
-#define GPIO_PORT_B32_PBYTE_Msk                               (0x01UL << GPIO_PORT_B32_PBYTE_Pos)                       /*!< GPIO_PORT B32: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B33  -----------------------------------------
-#define GPIO_PORT_B33_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B33: PBYTE Position       */
-#define GPIO_PORT_B33_PBYTE_Msk                               (0x01UL << GPIO_PORT_B33_PBYTE_Pos)                       /*!< GPIO_PORT B33: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B34  -----------------------------------------
-#define GPIO_PORT_B34_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B34: PBYTE Position       */
-#define GPIO_PORT_B34_PBYTE_Msk                               (0x01UL << GPIO_PORT_B34_PBYTE_Pos)                       /*!< GPIO_PORT B34: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B35  -----------------------------------------
-#define GPIO_PORT_B35_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B35: PBYTE Position       */
-#define GPIO_PORT_B35_PBYTE_Msk                               (0x01UL << GPIO_PORT_B35_PBYTE_Pos)                       /*!< GPIO_PORT B35: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B36  -----------------------------------------
-#define GPIO_PORT_B36_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B36: PBYTE Position       */
-#define GPIO_PORT_B36_PBYTE_Msk                               (0x01UL << GPIO_PORT_B36_PBYTE_Pos)                       /*!< GPIO_PORT B36: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B37  -----------------------------------------
-#define GPIO_PORT_B37_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B37: PBYTE Position       */
-#define GPIO_PORT_B37_PBYTE_Msk                               (0x01UL << GPIO_PORT_B37_PBYTE_Pos)                       /*!< GPIO_PORT B37: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B38  -----------------------------------------
-#define GPIO_PORT_B38_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B38: PBYTE Position       */
-#define GPIO_PORT_B38_PBYTE_Msk                               (0x01UL << GPIO_PORT_B38_PBYTE_Pos)                       /*!< GPIO_PORT B38: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B39  -----------------------------------------
-#define GPIO_PORT_B39_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B39: PBYTE Position       */
-#define GPIO_PORT_B39_PBYTE_Msk                               (0x01UL << GPIO_PORT_B39_PBYTE_Pos)                       /*!< GPIO_PORT B39: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B40  -----------------------------------------
-#define GPIO_PORT_B40_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B40: PBYTE Position       */
-#define GPIO_PORT_B40_PBYTE_Msk                               (0x01UL << GPIO_PORT_B40_PBYTE_Pos)                       /*!< GPIO_PORT B40: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B41  -----------------------------------------
-#define GPIO_PORT_B41_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B41: PBYTE Position       */
-#define GPIO_PORT_B41_PBYTE_Msk                               (0x01UL << GPIO_PORT_B41_PBYTE_Pos)                       /*!< GPIO_PORT B41: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B42  -----------------------------------------
-#define GPIO_PORT_B42_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B42: PBYTE Position       */
-#define GPIO_PORT_B42_PBYTE_Msk                               (0x01UL << GPIO_PORT_B42_PBYTE_Pos)                       /*!< GPIO_PORT B42: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B43  -----------------------------------------
-#define GPIO_PORT_B43_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B43: PBYTE Position       */
-#define GPIO_PORT_B43_PBYTE_Msk                               (0x01UL << GPIO_PORT_B43_PBYTE_Pos)                       /*!< GPIO_PORT B43: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B44  -----------------------------------------
-#define GPIO_PORT_B44_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B44: PBYTE Position       */
-#define GPIO_PORT_B44_PBYTE_Msk                               (0x01UL << GPIO_PORT_B44_PBYTE_Pos)                       /*!< GPIO_PORT B44: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B45  -----------------------------------------
-#define GPIO_PORT_B45_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B45: PBYTE Position       */
-#define GPIO_PORT_B45_PBYTE_Msk                               (0x01UL << GPIO_PORT_B45_PBYTE_Pos)                       /*!< GPIO_PORT B45: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B46  -----------------------------------------
-#define GPIO_PORT_B46_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B46: PBYTE Position       */
-#define GPIO_PORT_B46_PBYTE_Msk                               (0x01UL << GPIO_PORT_B46_PBYTE_Pos)                       /*!< GPIO_PORT B46: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B47  -----------------------------------------
-#define GPIO_PORT_B47_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B47: PBYTE Position       */
-#define GPIO_PORT_B47_PBYTE_Msk                               (0x01UL << GPIO_PORT_B47_PBYTE_Pos)                       /*!< GPIO_PORT B47: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B48  -----------------------------------------
-#define GPIO_PORT_B48_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B48: PBYTE Position       */
-#define GPIO_PORT_B48_PBYTE_Msk                               (0x01UL << GPIO_PORT_B48_PBYTE_Pos)                       /*!< GPIO_PORT B48: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B49  -----------------------------------------
-#define GPIO_PORT_B49_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B49: PBYTE Position       */
-#define GPIO_PORT_B49_PBYTE_Msk                               (0x01UL << GPIO_PORT_B49_PBYTE_Pos)                       /*!< GPIO_PORT B49: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B50  -----------------------------------------
-#define GPIO_PORT_B50_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B50: PBYTE Position       */
-#define GPIO_PORT_B50_PBYTE_Msk                               (0x01UL << GPIO_PORT_B50_PBYTE_Pos)                       /*!< GPIO_PORT B50: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B51  -----------------------------------------
-#define GPIO_PORT_B51_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B51: PBYTE Position       */
-#define GPIO_PORT_B51_PBYTE_Msk                               (0x01UL << GPIO_PORT_B51_PBYTE_Pos)                       /*!< GPIO_PORT B51: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B52  -----------------------------------------
-#define GPIO_PORT_B52_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B52: PBYTE Position       */
-#define GPIO_PORT_B52_PBYTE_Msk                               (0x01UL << GPIO_PORT_B52_PBYTE_Pos)                       /*!< GPIO_PORT B52: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B53  -----------------------------------------
-#define GPIO_PORT_B53_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B53: PBYTE Position       */
-#define GPIO_PORT_B53_PBYTE_Msk                               (0x01UL << GPIO_PORT_B53_PBYTE_Pos)                       /*!< GPIO_PORT B53: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B54  -----------------------------------------
-#define GPIO_PORT_B54_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B54: PBYTE Position       */
-#define GPIO_PORT_B54_PBYTE_Msk                               (0x01UL << GPIO_PORT_B54_PBYTE_Pos)                       /*!< GPIO_PORT B54: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B55  -----------------------------------------
-#define GPIO_PORT_B55_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B55: PBYTE Position       */
-#define GPIO_PORT_B55_PBYTE_Msk                               (0x01UL << GPIO_PORT_B55_PBYTE_Pos)                       /*!< GPIO_PORT B55: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B56  -----------------------------------------
-#define GPIO_PORT_B56_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B56: PBYTE Position       */
-#define GPIO_PORT_B56_PBYTE_Msk                               (0x01UL << GPIO_PORT_B56_PBYTE_Pos)                       /*!< GPIO_PORT B56: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B57  -----------------------------------------
-#define GPIO_PORT_B57_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B57: PBYTE Position       */
-#define GPIO_PORT_B57_PBYTE_Msk                               (0x01UL << GPIO_PORT_B57_PBYTE_Pos)                       /*!< GPIO_PORT B57: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B58  -----------------------------------------
-#define GPIO_PORT_B58_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B58: PBYTE Position       */
-#define GPIO_PORT_B58_PBYTE_Msk                               (0x01UL << GPIO_PORT_B58_PBYTE_Pos)                       /*!< GPIO_PORT B58: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B59  -----------------------------------------
-#define GPIO_PORT_B59_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B59: PBYTE Position       */
-#define GPIO_PORT_B59_PBYTE_Msk                               (0x01UL << GPIO_PORT_B59_PBYTE_Pos)                       /*!< GPIO_PORT B59: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B60  -----------------------------------------
-#define GPIO_PORT_B60_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B60: PBYTE Position       */
-#define GPIO_PORT_B60_PBYTE_Msk                               (0x01UL << GPIO_PORT_B60_PBYTE_Pos)                       /*!< GPIO_PORT B60: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B61  -----------------------------------------
-#define GPIO_PORT_B61_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B61: PBYTE Position       */
-#define GPIO_PORT_B61_PBYTE_Msk                               (0x01UL << GPIO_PORT_B61_PBYTE_Pos)                       /*!< GPIO_PORT B61: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B62  -----------------------------------------
-#define GPIO_PORT_B62_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B62: PBYTE Position       */
-#define GPIO_PORT_B62_PBYTE_Msk                               (0x01UL << GPIO_PORT_B62_PBYTE_Pos)                       /*!< GPIO_PORT B62: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B63  -----------------------------------------
-#define GPIO_PORT_B63_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B63: PBYTE Position       */
-#define GPIO_PORT_B63_PBYTE_Msk                               (0x01UL << GPIO_PORT_B63_PBYTE_Pos)                       /*!< GPIO_PORT B63: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B64  -----------------------------------------
-#define GPIO_PORT_B64_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B64: PBYTE Position       */
-#define GPIO_PORT_B64_PBYTE_Msk                               (0x01UL << GPIO_PORT_B64_PBYTE_Pos)                       /*!< GPIO_PORT B64: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B65  -----------------------------------------
-#define GPIO_PORT_B65_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B65: PBYTE Position       */
-#define GPIO_PORT_B65_PBYTE_Msk                               (0x01UL << GPIO_PORT_B65_PBYTE_Pos)                       /*!< GPIO_PORT B65: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B66  -----------------------------------------
-#define GPIO_PORT_B66_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B66: PBYTE Position       */
-#define GPIO_PORT_B66_PBYTE_Msk                               (0x01UL << GPIO_PORT_B66_PBYTE_Pos)                       /*!< GPIO_PORT B66: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B67  -----------------------------------------
-#define GPIO_PORT_B67_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B67: PBYTE Position       */
-#define GPIO_PORT_B67_PBYTE_Msk                               (0x01UL << GPIO_PORT_B67_PBYTE_Pos)                       /*!< GPIO_PORT B67: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B68  -----------------------------------------
-#define GPIO_PORT_B68_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B68: PBYTE Position       */
-#define GPIO_PORT_B68_PBYTE_Msk                               (0x01UL << GPIO_PORT_B68_PBYTE_Pos)                       /*!< GPIO_PORT B68: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B69  -----------------------------------------
-#define GPIO_PORT_B69_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B69: PBYTE Position       */
-#define GPIO_PORT_B69_PBYTE_Msk                               (0x01UL << GPIO_PORT_B69_PBYTE_Pos)                       /*!< GPIO_PORT B69: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B70  -----------------------------------------
-#define GPIO_PORT_B70_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B70: PBYTE Position       */
-#define GPIO_PORT_B70_PBYTE_Msk                               (0x01UL << GPIO_PORT_B70_PBYTE_Pos)                       /*!< GPIO_PORT B70: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B71  -----------------------------------------
-#define GPIO_PORT_B71_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B71: PBYTE Position       */
-#define GPIO_PORT_B71_PBYTE_Msk                               (0x01UL << GPIO_PORT_B71_PBYTE_Pos)                       /*!< GPIO_PORT B71: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B72  -----------------------------------------
-#define GPIO_PORT_B72_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B72: PBYTE Position       */
-#define GPIO_PORT_B72_PBYTE_Msk                               (0x01UL << GPIO_PORT_B72_PBYTE_Pos)                       /*!< GPIO_PORT B72: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B73  -----------------------------------------
-#define GPIO_PORT_B73_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B73: PBYTE Position       */
-#define GPIO_PORT_B73_PBYTE_Msk                               (0x01UL << GPIO_PORT_B73_PBYTE_Pos)                       /*!< GPIO_PORT B73: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B74  -----------------------------------------
-#define GPIO_PORT_B74_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B74: PBYTE Position       */
-#define GPIO_PORT_B74_PBYTE_Msk                               (0x01UL << GPIO_PORT_B74_PBYTE_Pos)                       /*!< GPIO_PORT B74: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B75  -----------------------------------------
-#define GPIO_PORT_B75_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B75: PBYTE Position       */
-#define GPIO_PORT_B75_PBYTE_Msk                               (0x01UL << GPIO_PORT_B75_PBYTE_Pos)                       /*!< GPIO_PORT B75: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B76  -----------------------------------------
-#define GPIO_PORT_B76_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B76: PBYTE Position       */
-#define GPIO_PORT_B76_PBYTE_Msk                               (0x01UL << GPIO_PORT_B76_PBYTE_Pos)                       /*!< GPIO_PORT B76: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B77  -----------------------------------------
-#define GPIO_PORT_B77_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B77: PBYTE Position       */
-#define GPIO_PORT_B77_PBYTE_Msk                               (0x01UL << GPIO_PORT_B77_PBYTE_Pos)                       /*!< GPIO_PORT B77: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B78  -----------------------------------------
-#define GPIO_PORT_B78_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B78: PBYTE Position       */
-#define GPIO_PORT_B78_PBYTE_Msk                               (0x01UL << GPIO_PORT_B78_PBYTE_Pos)                       /*!< GPIO_PORT B78: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B79  -----------------------------------------
-#define GPIO_PORT_B79_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B79: PBYTE Position       */
-#define GPIO_PORT_B79_PBYTE_Msk                               (0x01UL << GPIO_PORT_B79_PBYTE_Pos)                       /*!< GPIO_PORT B79: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B80  -----------------------------------------
-#define GPIO_PORT_B80_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B80: PBYTE Position       */
-#define GPIO_PORT_B80_PBYTE_Msk                               (0x01UL << GPIO_PORT_B80_PBYTE_Pos)                       /*!< GPIO_PORT B80: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B81  -----------------------------------------
-#define GPIO_PORT_B81_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B81: PBYTE Position       */
-#define GPIO_PORT_B81_PBYTE_Msk                               (0x01UL << GPIO_PORT_B81_PBYTE_Pos)                       /*!< GPIO_PORT B81: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B82  -----------------------------------------
-#define GPIO_PORT_B82_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B82: PBYTE Position       */
-#define GPIO_PORT_B82_PBYTE_Msk                               (0x01UL << GPIO_PORT_B82_PBYTE_Pos)                       /*!< GPIO_PORT B82: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B83  -----------------------------------------
-#define GPIO_PORT_B83_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B83: PBYTE Position       */
-#define GPIO_PORT_B83_PBYTE_Msk                               (0x01UL << GPIO_PORT_B83_PBYTE_Pos)                       /*!< GPIO_PORT B83: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B84  -----------------------------------------
-#define GPIO_PORT_B84_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B84: PBYTE Position       */
-#define GPIO_PORT_B84_PBYTE_Msk                               (0x01UL << GPIO_PORT_B84_PBYTE_Pos)                       /*!< GPIO_PORT B84: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B85  -----------------------------------------
-#define GPIO_PORT_B85_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B85: PBYTE Position       */
-#define GPIO_PORT_B85_PBYTE_Msk                               (0x01UL << GPIO_PORT_B85_PBYTE_Pos)                       /*!< GPIO_PORT B85: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B86  -----------------------------------------
-#define GPIO_PORT_B86_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B86: PBYTE Position       */
-#define GPIO_PORT_B86_PBYTE_Msk                               (0x01UL << GPIO_PORT_B86_PBYTE_Pos)                       /*!< GPIO_PORT B86: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B87  -----------------------------------------
-#define GPIO_PORT_B87_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B87: PBYTE Position       */
-#define GPIO_PORT_B87_PBYTE_Msk                               (0x01UL << GPIO_PORT_B87_PBYTE_Pos)                       /*!< GPIO_PORT B87: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B88  -----------------------------------------
-#define GPIO_PORT_B88_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B88: PBYTE Position       */
-#define GPIO_PORT_B88_PBYTE_Msk                               (0x01UL << GPIO_PORT_B88_PBYTE_Pos)                       /*!< GPIO_PORT B88: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B89  -----------------------------------------
-#define GPIO_PORT_B89_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B89: PBYTE Position       */
-#define GPIO_PORT_B89_PBYTE_Msk                               (0x01UL << GPIO_PORT_B89_PBYTE_Pos)                       /*!< GPIO_PORT B89: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B90  -----------------------------------------
-#define GPIO_PORT_B90_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B90: PBYTE Position       */
-#define GPIO_PORT_B90_PBYTE_Msk                               (0x01UL << GPIO_PORT_B90_PBYTE_Pos)                       /*!< GPIO_PORT B90: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B91  -----------------------------------------
-#define GPIO_PORT_B91_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B91: PBYTE Position       */
-#define GPIO_PORT_B91_PBYTE_Msk                               (0x01UL << GPIO_PORT_B91_PBYTE_Pos)                       /*!< GPIO_PORT B91: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B92  -----------------------------------------
-#define GPIO_PORT_B92_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B92: PBYTE Position       */
-#define GPIO_PORT_B92_PBYTE_Msk                               (0x01UL << GPIO_PORT_B92_PBYTE_Pos)                       /*!< GPIO_PORT B92: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B93  -----------------------------------------
-#define GPIO_PORT_B93_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B93: PBYTE Position       */
-#define GPIO_PORT_B93_PBYTE_Msk                               (0x01UL << GPIO_PORT_B93_PBYTE_Pos)                       /*!< GPIO_PORT B93: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B94  -----------------------------------------
-#define GPIO_PORT_B94_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B94: PBYTE Position       */
-#define GPIO_PORT_B94_PBYTE_Msk                               (0x01UL << GPIO_PORT_B94_PBYTE_Pos)                       /*!< GPIO_PORT B94: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B95  -----------------------------------------
-#define GPIO_PORT_B95_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B95: PBYTE Position       */
-#define GPIO_PORT_B95_PBYTE_Msk                               (0x01UL << GPIO_PORT_B95_PBYTE_Pos)                       /*!< GPIO_PORT B95: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B96  -----------------------------------------
-#define GPIO_PORT_B96_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B96: PBYTE Position       */
-#define GPIO_PORT_B96_PBYTE_Msk                               (0x01UL << GPIO_PORT_B96_PBYTE_Pos)                       /*!< GPIO_PORT B96: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B97  -----------------------------------------
-#define GPIO_PORT_B97_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B97: PBYTE Position       */
-#define GPIO_PORT_B97_PBYTE_Msk                               (0x01UL << GPIO_PORT_B97_PBYTE_Pos)                       /*!< GPIO_PORT B97: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B98  -----------------------------------------
-#define GPIO_PORT_B98_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B98: PBYTE Position       */
-#define GPIO_PORT_B98_PBYTE_Msk                               (0x01UL << GPIO_PORT_B98_PBYTE_Pos)                       /*!< GPIO_PORT B98: PBYTE Mask           */
-
-// --------------------------------------  GPIO_PORT_B99  -----------------------------------------
-#define GPIO_PORT_B99_PBYTE_Pos                               0                                                         /*!< GPIO_PORT B99: PBYTE Position       */
-#define GPIO_PORT_B99_PBYTE_Msk                               (0x01UL << GPIO_PORT_B99_PBYTE_Pos)                       /*!< GPIO_PORT B99: PBYTE Mask           */
-
-// -------------------------------------  GPIO_PORT_B100  -----------------------------------------
-#define GPIO_PORT_B100_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B100: PBYTE Position      */
-#define GPIO_PORT_B100_PBYTE_Msk                              (0x01UL << GPIO_PORT_B100_PBYTE_Pos)                      /*!< GPIO_PORT B100: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B101  -----------------------------------------
-#define GPIO_PORT_B101_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B101: PBYTE Position      */
-#define GPIO_PORT_B101_PBYTE_Msk                              (0x01UL << GPIO_PORT_B101_PBYTE_Pos)                      /*!< GPIO_PORT B101: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B102  -----------------------------------------
-#define GPIO_PORT_B102_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B102: PBYTE Position      */
-#define GPIO_PORT_B102_PBYTE_Msk                              (0x01UL << GPIO_PORT_B102_PBYTE_Pos)                      /*!< GPIO_PORT B102: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B103  -----------------------------------------
-#define GPIO_PORT_B103_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B103: PBYTE Position      */
-#define GPIO_PORT_B103_PBYTE_Msk                              (0x01UL << GPIO_PORT_B103_PBYTE_Pos)                      /*!< GPIO_PORT B103: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B104  -----------------------------------------
-#define GPIO_PORT_B104_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B104: PBYTE Position      */
-#define GPIO_PORT_B104_PBYTE_Msk                              (0x01UL << GPIO_PORT_B104_PBYTE_Pos)                      /*!< GPIO_PORT B104: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B105  -----------------------------------------
-#define GPIO_PORT_B105_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B105: PBYTE Position      */
-#define GPIO_PORT_B105_PBYTE_Msk                              (0x01UL << GPIO_PORT_B105_PBYTE_Pos)                      /*!< GPIO_PORT B105: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B106  -----------------------------------------
-#define GPIO_PORT_B106_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B106: PBYTE Position      */
-#define GPIO_PORT_B106_PBYTE_Msk                              (0x01UL << GPIO_PORT_B106_PBYTE_Pos)                      /*!< GPIO_PORT B106: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B107  -----------------------------------------
-#define GPIO_PORT_B107_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B107: PBYTE Position      */
-#define GPIO_PORT_B107_PBYTE_Msk                              (0x01UL << GPIO_PORT_B107_PBYTE_Pos)                      /*!< GPIO_PORT B107: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B108  -----------------------------------------
-#define GPIO_PORT_B108_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B108: PBYTE Position      */
-#define GPIO_PORT_B108_PBYTE_Msk                              (0x01UL << GPIO_PORT_B108_PBYTE_Pos)                      /*!< GPIO_PORT B108: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B109  -----------------------------------------
-#define GPIO_PORT_B109_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B109: PBYTE Position      */
-#define GPIO_PORT_B109_PBYTE_Msk                              (0x01UL << GPIO_PORT_B109_PBYTE_Pos)                      /*!< GPIO_PORT B109: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B110  -----------------------------------------
-#define GPIO_PORT_B110_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B110: PBYTE Position      */
-#define GPIO_PORT_B110_PBYTE_Msk                              (0x01UL << GPIO_PORT_B110_PBYTE_Pos)                      /*!< GPIO_PORT B110: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B111  -----------------------------------------
-#define GPIO_PORT_B111_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B111: PBYTE Position      */
-#define GPIO_PORT_B111_PBYTE_Msk                              (0x01UL << GPIO_PORT_B111_PBYTE_Pos)                      /*!< GPIO_PORT B111: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B112  -----------------------------------------
-#define GPIO_PORT_B112_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B112: PBYTE Position      */
-#define GPIO_PORT_B112_PBYTE_Msk                              (0x01UL << GPIO_PORT_B112_PBYTE_Pos)                      /*!< GPIO_PORT B112: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B113  -----------------------------------------
-#define GPIO_PORT_B113_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B113: PBYTE Position      */
-#define GPIO_PORT_B113_PBYTE_Msk                              (0x01UL << GPIO_PORT_B113_PBYTE_Pos)                      /*!< GPIO_PORT B113: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B114  -----------------------------------------
-#define GPIO_PORT_B114_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B114: PBYTE Position      */
-#define GPIO_PORT_B114_PBYTE_Msk                              (0x01UL << GPIO_PORT_B114_PBYTE_Pos)                      /*!< GPIO_PORT B114: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B115  -----------------------------------------
-#define GPIO_PORT_B115_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B115: PBYTE Position      */
-#define GPIO_PORT_B115_PBYTE_Msk                              (0x01UL << GPIO_PORT_B115_PBYTE_Pos)                      /*!< GPIO_PORT B115: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B116  -----------------------------------------
-#define GPIO_PORT_B116_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B116: PBYTE Position      */
-#define GPIO_PORT_B116_PBYTE_Msk                              (0x01UL << GPIO_PORT_B116_PBYTE_Pos)                      /*!< GPIO_PORT B116: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B117  -----------------------------------------
-#define GPIO_PORT_B117_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B117: PBYTE Position      */
-#define GPIO_PORT_B117_PBYTE_Msk                              (0x01UL << GPIO_PORT_B117_PBYTE_Pos)                      /*!< GPIO_PORT B117: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B118  -----------------------------------------
-#define GPIO_PORT_B118_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B118: PBYTE Position      */
-#define GPIO_PORT_B118_PBYTE_Msk                              (0x01UL << GPIO_PORT_B118_PBYTE_Pos)                      /*!< GPIO_PORT B118: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B119  -----------------------------------------
-#define GPIO_PORT_B119_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B119: PBYTE Position      */
-#define GPIO_PORT_B119_PBYTE_Msk                              (0x01UL << GPIO_PORT_B119_PBYTE_Pos)                      /*!< GPIO_PORT B119: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B120  -----------------------------------------
-#define GPIO_PORT_B120_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B120: PBYTE Position      */
-#define GPIO_PORT_B120_PBYTE_Msk                              (0x01UL << GPIO_PORT_B120_PBYTE_Pos)                      /*!< GPIO_PORT B120: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B121  -----------------------------------------
-#define GPIO_PORT_B121_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B121: PBYTE Position      */
-#define GPIO_PORT_B121_PBYTE_Msk                              (0x01UL << GPIO_PORT_B121_PBYTE_Pos)                      /*!< GPIO_PORT B121: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B122  -----------------------------------------
-#define GPIO_PORT_B122_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B122: PBYTE Position      */
-#define GPIO_PORT_B122_PBYTE_Msk                              (0x01UL << GPIO_PORT_B122_PBYTE_Pos)                      /*!< GPIO_PORT B122: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B123  -----------------------------------------
-#define GPIO_PORT_B123_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B123: PBYTE Position      */
-#define GPIO_PORT_B123_PBYTE_Msk                              (0x01UL << GPIO_PORT_B123_PBYTE_Pos)                      /*!< GPIO_PORT B123: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B124  -----------------------------------------
-#define GPIO_PORT_B124_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B124: PBYTE Position      */
-#define GPIO_PORT_B124_PBYTE_Msk                              (0x01UL << GPIO_PORT_B124_PBYTE_Pos)                      /*!< GPIO_PORT B124: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B125  -----------------------------------------
-#define GPIO_PORT_B125_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B125: PBYTE Position      */
-#define GPIO_PORT_B125_PBYTE_Msk                              (0x01UL << GPIO_PORT_B125_PBYTE_Pos)                      /*!< GPIO_PORT B125: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B126  -----------------------------------------
-#define GPIO_PORT_B126_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B126: PBYTE Position      */
-#define GPIO_PORT_B126_PBYTE_Msk                              (0x01UL << GPIO_PORT_B126_PBYTE_Pos)                      /*!< GPIO_PORT B126: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B127  -----------------------------------------
-#define GPIO_PORT_B127_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B127: PBYTE Position      */
-#define GPIO_PORT_B127_PBYTE_Msk                              (0x01UL << GPIO_PORT_B127_PBYTE_Pos)                      /*!< GPIO_PORT B127: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B128  -----------------------------------------
-#define GPIO_PORT_B128_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B128: PBYTE Position      */
-#define GPIO_PORT_B128_PBYTE_Msk                              (0x01UL << GPIO_PORT_B128_PBYTE_Pos)                      /*!< GPIO_PORT B128: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B129  -----------------------------------------
-#define GPIO_PORT_B129_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B129: PBYTE Position      */
-#define GPIO_PORT_B129_PBYTE_Msk                              (0x01UL << GPIO_PORT_B129_PBYTE_Pos)                      /*!< GPIO_PORT B129: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B130  -----------------------------------------
-#define GPIO_PORT_B130_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B130: PBYTE Position      */
-#define GPIO_PORT_B130_PBYTE_Msk                              (0x01UL << GPIO_PORT_B130_PBYTE_Pos)                      /*!< GPIO_PORT B130: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B131  -----------------------------------------
-#define GPIO_PORT_B131_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B131: PBYTE Position      */
-#define GPIO_PORT_B131_PBYTE_Msk                              (0x01UL << GPIO_PORT_B131_PBYTE_Pos)                      /*!< GPIO_PORT B131: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B132  -----------------------------------------
-#define GPIO_PORT_B132_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B132: PBYTE Position      */
-#define GPIO_PORT_B132_PBYTE_Msk                              (0x01UL << GPIO_PORT_B132_PBYTE_Pos)                      /*!< GPIO_PORT B132: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B133  -----------------------------------------
-#define GPIO_PORT_B133_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B133: PBYTE Position      */
-#define GPIO_PORT_B133_PBYTE_Msk                              (0x01UL << GPIO_PORT_B133_PBYTE_Pos)                      /*!< GPIO_PORT B133: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B134  -----------------------------------------
-#define GPIO_PORT_B134_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B134: PBYTE Position      */
-#define GPIO_PORT_B134_PBYTE_Msk                              (0x01UL << GPIO_PORT_B134_PBYTE_Pos)                      /*!< GPIO_PORT B134: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B135  -----------------------------------------
-#define GPIO_PORT_B135_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B135: PBYTE Position      */
-#define GPIO_PORT_B135_PBYTE_Msk                              (0x01UL << GPIO_PORT_B135_PBYTE_Pos)                      /*!< GPIO_PORT B135: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B136  -----------------------------------------
-#define GPIO_PORT_B136_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B136: PBYTE Position      */
-#define GPIO_PORT_B136_PBYTE_Msk                              (0x01UL << GPIO_PORT_B136_PBYTE_Pos)                      /*!< GPIO_PORT B136: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B137  -----------------------------------------
-#define GPIO_PORT_B137_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B137: PBYTE Position      */
-#define GPIO_PORT_B137_PBYTE_Msk                              (0x01UL << GPIO_PORT_B137_PBYTE_Pos)                      /*!< GPIO_PORT B137: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B138  -----------------------------------------
-#define GPIO_PORT_B138_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B138: PBYTE Position      */
-#define GPIO_PORT_B138_PBYTE_Msk                              (0x01UL << GPIO_PORT_B138_PBYTE_Pos)                      /*!< GPIO_PORT B138: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B139  -----------------------------------------
-#define GPIO_PORT_B139_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B139: PBYTE Position      */
-#define GPIO_PORT_B139_PBYTE_Msk                              (0x01UL << GPIO_PORT_B139_PBYTE_Pos)                      /*!< GPIO_PORT B139: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B140  -----------------------------------------
-#define GPIO_PORT_B140_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B140: PBYTE Position      */
-#define GPIO_PORT_B140_PBYTE_Msk                              (0x01UL << GPIO_PORT_B140_PBYTE_Pos)                      /*!< GPIO_PORT B140: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B141  -----------------------------------------
-#define GPIO_PORT_B141_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B141: PBYTE Position      */
-#define GPIO_PORT_B141_PBYTE_Msk                              (0x01UL << GPIO_PORT_B141_PBYTE_Pos)                      /*!< GPIO_PORT B141: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B142  -----------------------------------------
-#define GPIO_PORT_B142_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B142: PBYTE Position      */
-#define GPIO_PORT_B142_PBYTE_Msk                              (0x01UL << GPIO_PORT_B142_PBYTE_Pos)                      /*!< GPIO_PORT B142: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B143  -----------------------------------------
-#define GPIO_PORT_B143_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B143: PBYTE Position      */
-#define GPIO_PORT_B143_PBYTE_Msk                              (0x01UL << GPIO_PORT_B143_PBYTE_Pos)                      /*!< GPIO_PORT B143: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B144  -----------------------------------------
-#define GPIO_PORT_B144_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B144: PBYTE Position      */
-#define GPIO_PORT_B144_PBYTE_Msk                              (0x01UL << GPIO_PORT_B144_PBYTE_Pos)                      /*!< GPIO_PORT B144: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B145  -----------------------------------------
-#define GPIO_PORT_B145_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B145: PBYTE Position      */
-#define GPIO_PORT_B145_PBYTE_Msk                              (0x01UL << GPIO_PORT_B145_PBYTE_Pos)                      /*!< GPIO_PORT B145: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B146  -----------------------------------------
-#define GPIO_PORT_B146_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B146: PBYTE Position      */
-#define GPIO_PORT_B146_PBYTE_Msk                              (0x01UL << GPIO_PORT_B146_PBYTE_Pos)                      /*!< GPIO_PORT B146: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B147  -----------------------------------------
-#define GPIO_PORT_B147_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B147: PBYTE Position      */
-#define GPIO_PORT_B147_PBYTE_Msk                              (0x01UL << GPIO_PORT_B147_PBYTE_Pos)                      /*!< GPIO_PORT B147: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B148  -----------------------------------------
-#define GPIO_PORT_B148_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B148: PBYTE Position      */
-#define GPIO_PORT_B148_PBYTE_Msk                              (0x01UL << GPIO_PORT_B148_PBYTE_Pos)                      /*!< GPIO_PORT B148: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B149  -----------------------------------------
-#define GPIO_PORT_B149_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B149: PBYTE Position      */
-#define GPIO_PORT_B149_PBYTE_Msk                              (0x01UL << GPIO_PORT_B149_PBYTE_Pos)                      /*!< GPIO_PORT B149: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B150  -----------------------------------------
-#define GPIO_PORT_B150_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B150: PBYTE Position      */
-#define GPIO_PORT_B150_PBYTE_Msk                              (0x01UL << GPIO_PORT_B150_PBYTE_Pos)                      /*!< GPIO_PORT B150: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B151  -----------------------------------------
-#define GPIO_PORT_B151_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B151: PBYTE Position      */
-#define GPIO_PORT_B151_PBYTE_Msk                              (0x01UL << GPIO_PORT_B151_PBYTE_Pos)                      /*!< GPIO_PORT B151: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B152  -----------------------------------------
-#define GPIO_PORT_B152_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B152: PBYTE Position      */
-#define GPIO_PORT_B152_PBYTE_Msk                              (0x01UL << GPIO_PORT_B152_PBYTE_Pos)                      /*!< GPIO_PORT B152: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B153  -----------------------------------------
-#define GPIO_PORT_B153_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B153: PBYTE Position      */
-#define GPIO_PORT_B153_PBYTE_Msk                              (0x01UL << GPIO_PORT_B153_PBYTE_Pos)                      /*!< GPIO_PORT B153: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B154  -----------------------------------------
-#define GPIO_PORT_B154_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B154: PBYTE Position      */
-#define GPIO_PORT_B154_PBYTE_Msk                              (0x01UL << GPIO_PORT_B154_PBYTE_Pos)                      /*!< GPIO_PORT B154: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B155  -----------------------------------------
-#define GPIO_PORT_B155_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B155: PBYTE Position      */
-#define GPIO_PORT_B155_PBYTE_Msk                              (0x01UL << GPIO_PORT_B155_PBYTE_Pos)                      /*!< GPIO_PORT B155: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B156  -----------------------------------------
-#define GPIO_PORT_B156_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B156: PBYTE Position      */
-#define GPIO_PORT_B156_PBYTE_Msk                              (0x01UL << GPIO_PORT_B156_PBYTE_Pos)                      /*!< GPIO_PORT B156: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B157  -----------------------------------------
-#define GPIO_PORT_B157_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B157: PBYTE Position      */
-#define GPIO_PORT_B157_PBYTE_Msk                              (0x01UL << GPIO_PORT_B157_PBYTE_Pos)                      /*!< GPIO_PORT B157: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B158  -----------------------------------------
-#define GPIO_PORT_B158_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B158: PBYTE Position      */
-#define GPIO_PORT_B158_PBYTE_Msk                              (0x01UL << GPIO_PORT_B158_PBYTE_Pos)                      /*!< GPIO_PORT B158: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B159  -----------------------------------------
-#define GPIO_PORT_B159_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B159: PBYTE Position      */
-#define GPIO_PORT_B159_PBYTE_Msk                              (0x01UL << GPIO_PORT_B159_PBYTE_Pos)                      /*!< GPIO_PORT B159: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B160  -----------------------------------------
-#define GPIO_PORT_B160_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B160: PBYTE Position      */
-#define GPIO_PORT_B160_PBYTE_Msk                              (0x01UL << GPIO_PORT_B160_PBYTE_Pos)                      /*!< GPIO_PORT B160: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B161  -----------------------------------------
-#define GPIO_PORT_B161_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B161: PBYTE Position      */
-#define GPIO_PORT_B161_PBYTE_Msk                              (0x01UL << GPIO_PORT_B161_PBYTE_Pos)                      /*!< GPIO_PORT B161: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B162  -----------------------------------------
-#define GPIO_PORT_B162_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B162: PBYTE Position      */
-#define GPIO_PORT_B162_PBYTE_Msk                              (0x01UL << GPIO_PORT_B162_PBYTE_Pos)                      /*!< GPIO_PORT B162: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B163  -----------------------------------------
-#define GPIO_PORT_B163_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B163: PBYTE Position      */
-#define GPIO_PORT_B163_PBYTE_Msk                              (0x01UL << GPIO_PORT_B163_PBYTE_Pos)                      /*!< GPIO_PORT B163: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B164  -----------------------------------------
-#define GPIO_PORT_B164_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B164: PBYTE Position      */
-#define GPIO_PORT_B164_PBYTE_Msk                              (0x01UL << GPIO_PORT_B164_PBYTE_Pos)                      /*!< GPIO_PORT B164: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B165  -----------------------------------------
-#define GPIO_PORT_B165_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B165: PBYTE Position      */
-#define GPIO_PORT_B165_PBYTE_Msk                              (0x01UL << GPIO_PORT_B165_PBYTE_Pos)                      /*!< GPIO_PORT B165: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B166  -----------------------------------------
-#define GPIO_PORT_B166_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B166: PBYTE Position      */
-#define GPIO_PORT_B166_PBYTE_Msk                              (0x01UL << GPIO_PORT_B166_PBYTE_Pos)                      /*!< GPIO_PORT B166: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B167  -----------------------------------------
-#define GPIO_PORT_B167_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B167: PBYTE Position      */
-#define GPIO_PORT_B167_PBYTE_Msk                              (0x01UL << GPIO_PORT_B167_PBYTE_Pos)                      /*!< GPIO_PORT B167: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B168  -----------------------------------------
-#define GPIO_PORT_B168_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B168: PBYTE Position      */
-#define GPIO_PORT_B168_PBYTE_Msk                              (0x01UL << GPIO_PORT_B168_PBYTE_Pos)                      /*!< GPIO_PORT B168: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B169  -----------------------------------------
-#define GPIO_PORT_B169_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B169: PBYTE Position      */
-#define GPIO_PORT_B169_PBYTE_Msk                              (0x01UL << GPIO_PORT_B169_PBYTE_Pos)                      /*!< GPIO_PORT B169: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B170  -----------------------------------------
-#define GPIO_PORT_B170_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B170: PBYTE Position      */
-#define GPIO_PORT_B170_PBYTE_Msk                              (0x01UL << GPIO_PORT_B170_PBYTE_Pos)                      /*!< GPIO_PORT B170: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B171  -----------------------------------------
-#define GPIO_PORT_B171_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B171: PBYTE Position      */
-#define GPIO_PORT_B171_PBYTE_Msk                              (0x01UL << GPIO_PORT_B171_PBYTE_Pos)                      /*!< GPIO_PORT B171: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B172  -----------------------------------------
-#define GPIO_PORT_B172_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B172: PBYTE Position      */
-#define GPIO_PORT_B172_PBYTE_Msk                              (0x01UL << GPIO_PORT_B172_PBYTE_Pos)                      /*!< GPIO_PORT B172: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B173  -----------------------------------------
-#define GPIO_PORT_B173_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B173: PBYTE Position      */
-#define GPIO_PORT_B173_PBYTE_Msk                              (0x01UL << GPIO_PORT_B173_PBYTE_Pos)                      /*!< GPIO_PORT B173: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B174  -----------------------------------------
-#define GPIO_PORT_B174_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B174: PBYTE Position      */
-#define GPIO_PORT_B174_PBYTE_Msk                              (0x01UL << GPIO_PORT_B174_PBYTE_Pos)                      /*!< GPIO_PORT B174: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B175  -----------------------------------------
-#define GPIO_PORT_B175_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B175: PBYTE Position      */
-#define GPIO_PORT_B175_PBYTE_Msk                              (0x01UL << GPIO_PORT_B175_PBYTE_Pos)                      /*!< GPIO_PORT B175: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B176  -----------------------------------------
-#define GPIO_PORT_B176_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B176: PBYTE Position      */
-#define GPIO_PORT_B176_PBYTE_Msk                              (0x01UL << GPIO_PORT_B176_PBYTE_Pos)                      /*!< GPIO_PORT B176: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B177  -----------------------------------------
-#define GPIO_PORT_B177_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B177: PBYTE Position      */
-#define GPIO_PORT_B177_PBYTE_Msk                              (0x01UL << GPIO_PORT_B177_PBYTE_Pos)                      /*!< GPIO_PORT B177: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B178  -----------------------------------------
-#define GPIO_PORT_B178_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B178: PBYTE Position      */
-#define GPIO_PORT_B178_PBYTE_Msk                              (0x01UL << GPIO_PORT_B178_PBYTE_Pos)                      /*!< GPIO_PORT B178: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B179  -----------------------------------------
-#define GPIO_PORT_B179_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B179: PBYTE Position      */
-#define GPIO_PORT_B179_PBYTE_Msk                              (0x01UL << GPIO_PORT_B179_PBYTE_Pos)                      /*!< GPIO_PORT B179: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B180  -----------------------------------------
-#define GPIO_PORT_B180_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B180: PBYTE Position      */
-#define GPIO_PORT_B180_PBYTE_Msk                              (0x01UL << GPIO_PORT_B180_PBYTE_Pos)                      /*!< GPIO_PORT B180: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B181  -----------------------------------------
-#define GPIO_PORT_B181_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B181: PBYTE Position      */
-#define GPIO_PORT_B181_PBYTE_Msk                              (0x01UL << GPIO_PORT_B181_PBYTE_Pos)                      /*!< GPIO_PORT B181: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B182  -----------------------------------------
-#define GPIO_PORT_B182_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B182: PBYTE Position      */
-#define GPIO_PORT_B182_PBYTE_Msk                              (0x01UL << GPIO_PORT_B182_PBYTE_Pos)                      /*!< GPIO_PORT B182: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B183  -----------------------------------------
-#define GPIO_PORT_B183_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B183: PBYTE Position      */
-#define GPIO_PORT_B183_PBYTE_Msk                              (0x01UL << GPIO_PORT_B183_PBYTE_Pos)                      /*!< GPIO_PORT B183: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B184  -----------------------------------------
-#define GPIO_PORT_B184_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B184: PBYTE Position      */
-#define GPIO_PORT_B184_PBYTE_Msk                              (0x01UL << GPIO_PORT_B184_PBYTE_Pos)                      /*!< GPIO_PORT B184: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B185  -----------------------------------------
-#define GPIO_PORT_B185_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B185: PBYTE Position      */
-#define GPIO_PORT_B185_PBYTE_Msk                              (0x01UL << GPIO_PORT_B185_PBYTE_Pos)                      /*!< GPIO_PORT B185: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B186  -----------------------------------------
-#define GPIO_PORT_B186_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B186: PBYTE Position      */
-#define GPIO_PORT_B186_PBYTE_Msk                              (0x01UL << GPIO_PORT_B186_PBYTE_Pos)                      /*!< GPIO_PORT B186: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B187  -----------------------------------------
-#define GPIO_PORT_B187_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B187: PBYTE Position      */
-#define GPIO_PORT_B187_PBYTE_Msk                              (0x01UL << GPIO_PORT_B187_PBYTE_Pos)                      /*!< GPIO_PORT B187: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B188  -----------------------------------------
-#define GPIO_PORT_B188_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B188: PBYTE Position      */
-#define GPIO_PORT_B188_PBYTE_Msk                              (0x01UL << GPIO_PORT_B188_PBYTE_Pos)                      /*!< GPIO_PORT B188: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B189  -----------------------------------------
-#define GPIO_PORT_B189_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B189: PBYTE Position      */
-#define GPIO_PORT_B189_PBYTE_Msk                              (0x01UL << GPIO_PORT_B189_PBYTE_Pos)                      /*!< GPIO_PORT B189: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B190  -----------------------------------------
-#define GPIO_PORT_B190_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B190: PBYTE Position      */
-#define GPIO_PORT_B190_PBYTE_Msk                              (0x01UL << GPIO_PORT_B190_PBYTE_Pos)                      /*!< GPIO_PORT B190: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B191  -----------------------------------------
-#define GPIO_PORT_B191_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B191: PBYTE Position      */
-#define GPIO_PORT_B191_PBYTE_Msk                              (0x01UL << GPIO_PORT_B191_PBYTE_Pos)                      /*!< GPIO_PORT B191: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B192  -----------------------------------------
-#define GPIO_PORT_B192_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B192: PBYTE Position      */
-#define GPIO_PORT_B192_PBYTE_Msk                              (0x01UL << GPIO_PORT_B192_PBYTE_Pos)                      /*!< GPIO_PORT B192: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B193  -----------------------------------------
-#define GPIO_PORT_B193_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B193: PBYTE Position      */
-#define GPIO_PORT_B193_PBYTE_Msk                              (0x01UL << GPIO_PORT_B193_PBYTE_Pos)                      /*!< GPIO_PORT B193: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B194  -----------------------------------------
-#define GPIO_PORT_B194_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B194: PBYTE Position      */
-#define GPIO_PORT_B194_PBYTE_Msk                              (0x01UL << GPIO_PORT_B194_PBYTE_Pos)                      /*!< GPIO_PORT B194: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B195  -----------------------------------------
-#define GPIO_PORT_B195_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B195: PBYTE Position      */
-#define GPIO_PORT_B195_PBYTE_Msk                              (0x01UL << GPIO_PORT_B195_PBYTE_Pos)                      /*!< GPIO_PORT B195: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B196  -----------------------------------------
-#define GPIO_PORT_B196_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B196: PBYTE Position      */
-#define GPIO_PORT_B196_PBYTE_Msk                              (0x01UL << GPIO_PORT_B196_PBYTE_Pos)                      /*!< GPIO_PORT B196: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B197  -----------------------------------------
-#define GPIO_PORT_B197_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B197: PBYTE Position      */
-#define GPIO_PORT_B197_PBYTE_Msk                              (0x01UL << GPIO_PORT_B197_PBYTE_Pos)                      /*!< GPIO_PORT B197: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B198  -----------------------------------------
-#define GPIO_PORT_B198_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B198: PBYTE Position      */
-#define GPIO_PORT_B198_PBYTE_Msk                              (0x01UL << GPIO_PORT_B198_PBYTE_Pos)                      /*!< GPIO_PORT B198: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B199  -----------------------------------------
-#define GPIO_PORT_B199_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B199: PBYTE Position      */
-#define GPIO_PORT_B199_PBYTE_Msk                              (0x01UL << GPIO_PORT_B199_PBYTE_Pos)                      /*!< GPIO_PORT B199: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B200  -----------------------------------------
-#define GPIO_PORT_B200_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B200: PBYTE Position      */
-#define GPIO_PORT_B200_PBYTE_Msk                              (0x01UL << GPIO_PORT_B200_PBYTE_Pos)                      /*!< GPIO_PORT B200: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B201  -----------------------------------------
-#define GPIO_PORT_B201_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B201: PBYTE Position      */
-#define GPIO_PORT_B201_PBYTE_Msk                              (0x01UL << GPIO_PORT_B201_PBYTE_Pos)                      /*!< GPIO_PORT B201: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B202  -----------------------------------------
-#define GPIO_PORT_B202_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B202: PBYTE Position      */
-#define GPIO_PORT_B202_PBYTE_Msk                              (0x01UL << GPIO_PORT_B202_PBYTE_Pos)                      /*!< GPIO_PORT B202: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B203  -----------------------------------------
-#define GPIO_PORT_B203_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B203: PBYTE Position      */
-#define GPIO_PORT_B203_PBYTE_Msk                              (0x01UL << GPIO_PORT_B203_PBYTE_Pos)                      /*!< GPIO_PORT B203: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B204  -----------------------------------------
-#define GPIO_PORT_B204_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B204: PBYTE Position      */
-#define GPIO_PORT_B204_PBYTE_Msk                              (0x01UL << GPIO_PORT_B204_PBYTE_Pos)                      /*!< GPIO_PORT B204: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B205  -----------------------------------------
-#define GPIO_PORT_B205_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B205: PBYTE Position      */
-#define GPIO_PORT_B205_PBYTE_Msk                              (0x01UL << GPIO_PORT_B205_PBYTE_Pos)                      /*!< GPIO_PORT B205: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B206  -----------------------------------------
-#define GPIO_PORT_B206_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B206: PBYTE Position      */
-#define GPIO_PORT_B206_PBYTE_Msk                              (0x01UL << GPIO_PORT_B206_PBYTE_Pos)                      /*!< GPIO_PORT B206: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B207  -----------------------------------------
-#define GPIO_PORT_B207_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B207: PBYTE Position      */
-#define GPIO_PORT_B207_PBYTE_Msk                              (0x01UL << GPIO_PORT_B207_PBYTE_Pos)                      /*!< GPIO_PORT B207: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B208  -----------------------------------------
-#define GPIO_PORT_B208_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B208: PBYTE Position      */
-#define GPIO_PORT_B208_PBYTE_Msk                              (0x01UL << GPIO_PORT_B208_PBYTE_Pos)                      /*!< GPIO_PORT B208: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B209  -----------------------------------------
-#define GPIO_PORT_B209_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B209: PBYTE Position      */
-#define GPIO_PORT_B209_PBYTE_Msk                              (0x01UL << GPIO_PORT_B209_PBYTE_Pos)                      /*!< GPIO_PORT B209: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B210  -----------------------------------------
-#define GPIO_PORT_B210_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B210: PBYTE Position      */
-#define GPIO_PORT_B210_PBYTE_Msk                              (0x01UL << GPIO_PORT_B210_PBYTE_Pos)                      /*!< GPIO_PORT B210: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B211  -----------------------------------------
-#define GPIO_PORT_B211_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B211: PBYTE Position      */
-#define GPIO_PORT_B211_PBYTE_Msk                              (0x01UL << GPIO_PORT_B211_PBYTE_Pos)                      /*!< GPIO_PORT B211: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B212  -----------------------------------------
-#define GPIO_PORT_B212_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B212: PBYTE Position      */
-#define GPIO_PORT_B212_PBYTE_Msk                              (0x01UL << GPIO_PORT_B212_PBYTE_Pos)                      /*!< GPIO_PORT B212: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B213  -----------------------------------------
-#define GPIO_PORT_B213_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B213: PBYTE Position      */
-#define GPIO_PORT_B213_PBYTE_Msk                              (0x01UL << GPIO_PORT_B213_PBYTE_Pos)                      /*!< GPIO_PORT B213: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B214  -----------------------------------------
-#define GPIO_PORT_B214_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B214: PBYTE Position      */
-#define GPIO_PORT_B214_PBYTE_Msk                              (0x01UL << GPIO_PORT_B214_PBYTE_Pos)                      /*!< GPIO_PORT B214: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B215  -----------------------------------------
-#define GPIO_PORT_B215_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B215: PBYTE Position      */
-#define GPIO_PORT_B215_PBYTE_Msk                              (0x01UL << GPIO_PORT_B215_PBYTE_Pos)                      /*!< GPIO_PORT B215: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B216  -----------------------------------------
-#define GPIO_PORT_B216_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B216: PBYTE Position      */
-#define GPIO_PORT_B216_PBYTE_Msk                              (0x01UL << GPIO_PORT_B216_PBYTE_Pos)                      /*!< GPIO_PORT B216: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B217  -----------------------------------------
-#define GPIO_PORT_B217_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B217: PBYTE Position      */
-#define GPIO_PORT_B217_PBYTE_Msk                              (0x01UL << GPIO_PORT_B217_PBYTE_Pos)                      /*!< GPIO_PORT B217: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B218  -----------------------------------------
-#define GPIO_PORT_B218_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B218: PBYTE Position      */
-#define GPIO_PORT_B218_PBYTE_Msk                              (0x01UL << GPIO_PORT_B218_PBYTE_Pos)                      /*!< GPIO_PORT B218: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B219  -----------------------------------------
-#define GPIO_PORT_B219_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B219: PBYTE Position      */
-#define GPIO_PORT_B219_PBYTE_Msk                              (0x01UL << GPIO_PORT_B219_PBYTE_Pos)                      /*!< GPIO_PORT B219: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B220  -----------------------------------------
-#define GPIO_PORT_B220_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B220: PBYTE Position      */
-#define GPIO_PORT_B220_PBYTE_Msk                              (0x01UL << GPIO_PORT_B220_PBYTE_Pos)                      /*!< GPIO_PORT B220: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B221  -----------------------------------------
-#define GPIO_PORT_B221_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B221: PBYTE Position      */
-#define GPIO_PORT_B221_PBYTE_Msk                              (0x01UL << GPIO_PORT_B221_PBYTE_Pos)                      /*!< GPIO_PORT B221: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B222  -----------------------------------------
-#define GPIO_PORT_B222_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B222: PBYTE Position      */
-#define GPIO_PORT_B222_PBYTE_Msk                              (0x01UL << GPIO_PORT_B222_PBYTE_Pos)                      /*!< GPIO_PORT B222: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B223  -----------------------------------------
-#define GPIO_PORT_B223_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B223: PBYTE Position      */
-#define GPIO_PORT_B223_PBYTE_Msk                              (0x01UL << GPIO_PORT_B223_PBYTE_Pos)                      /*!< GPIO_PORT B223: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B224  -----------------------------------------
-#define GPIO_PORT_B224_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B224: PBYTE Position      */
-#define GPIO_PORT_B224_PBYTE_Msk                              (0x01UL << GPIO_PORT_B224_PBYTE_Pos)                      /*!< GPIO_PORT B224: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B225  -----------------------------------------
-#define GPIO_PORT_B225_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B225: PBYTE Position      */
-#define GPIO_PORT_B225_PBYTE_Msk                              (0x01UL << GPIO_PORT_B225_PBYTE_Pos)                      /*!< GPIO_PORT B225: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B226  -----------------------------------------
-#define GPIO_PORT_B226_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B226: PBYTE Position      */
-#define GPIO_PORT_B226_PBYTE_Msk                              (0x01UL << GPIO_PORT_B226_PBYTE_Pos)                      /*!< GPIO_PORT B226: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B227  -----------------------------------------
-#define GPIO_PORT_B227_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B227: PBYTE Position      */
-#define GPIO_PORT_B227_PBYTE_Msk                              (0x01UL << GPIO_PORT_B227_PBYTE_Pos)                      /*!< GPIO_PORT B227: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B228  -----------------------------------------
-#define GPIO_PORT_B228_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B228: PBYTE Position      */
-#define GPIO_PORT_B228_PBYTE_Msk                              (0x01UL << GPIO_PORT_B228_PBYTE_Pos)                      /*!< GPIO_PORT B228: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B229  -----------------------------------------
-#define GPIO_PORT_B229_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B229: PBYTE Position      */
-#define GPIO_PORT_B229_PBYTE_Msk                              (0x01UL << GPIO_PORT_B229_PBYTE_Pos)                      /*!< GPIO_PORT B229: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B230  -----------------------------------------
-#define GPIO_PORT_B230_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B230: PBYTE Position      */
-#define GPIO_PORT_B230_PBYTE_Msk                              (0x01UL << GPIO_PORT_B230_PBYTE_Pos)                      /*!< GPIO_PORT B230: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B231  -----------------------------------------
-#define GPIO_PORT_B231_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B231: PBYTE Position      */
-#define GPIO_PORT_B231_PBYTE_Msk                              (0x01UL << GPIO_PORT_B231_PBYTE_Pos)                      /*!< GPIO_PORT B231: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B232  -----------------------------------------
-#define GPIO_PORT_B232_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B232: PBYTE Position      */
-#define GPIO_PORT_B232_PBYTE_Msk                              (0x01UL << GPIO_PORT_B232_PBYTE_Pos)                      /*!< GPIO_PORT B232: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B233  -----------------------------------------
-#define GPIO_PORT_B233_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B233: PBYTE Position      */
-#define GPIO_PORT_B233_PBYTE_Msk                              (0x01UL << GPIO_PORT_B233_PBYTE_Pos)                      /*!< GPIO_PORT B233: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B234  -----------------------------------------
-#define GPIO_PORT_B234_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B234: PBYTE Position      */
-#define GPIO_PORT_B234_PBYTE_Msk                              (0x01UL << GPIO_PORT_B234_PBYTE_Pos)                      /*!< GPIO_PORT B234: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B235  -----------------------------------------
-#define GPIO_PORT_B235_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B235: PBYTE Position      */
-#define GPIO_PORT_B235_PBYTE_Msk                              (0x01UL << GPIO_PORT_B235_PBYTE_Pos)                      /*!< GPIO_PORT B235: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B236  -----------------------------------------
-#define GPIO_PORT_B236_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B236: PBYTE Position      */
-#define GPIO_PORT_B236_PBYTE_Msk                              (0x01UL << GPIO_PORT_B236_PBYTE_Pos)                      /*!< GPIO_PORT B236: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B237  -----------------------------------------
-#define GPIO_PORT_B237_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B237: PBYTE Position      */
-#define GPIO_PORT_B237_PBYTE_Msk                              (0x01UL << GPIO_PORT_B237_PBYTE_Pos)                      /*!< GPIO_PORT B237: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B238  -----------------------------------------
-#define GPIO_PORT_B238_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B238: PBYTE Position      */
-#define GPIO_PORT_B238_PBYTE_Msk                              (0x01UL << GPIO_PORT_B238_PBYTE_Pos)                      /*!< GPIO_PORT B238: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B239  -----------------------------------------
-#define GPIO_PORT_B239_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B239: PBYTE Position      */
-#define GPIO_PORT_B239_PBYTE_Msk                              (0x01UL << GPIO_PORT_B239_PBYTE_Pos)                      /*!< GPIO_PORT B239: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B240  -----------------------------------------
-#define GPIO_PORT_B240_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B240: PBYTE Position      */
-#define GPIO_PORT_B240_PBYTE_Msk                              (0x01UL << GPIO_PORT_B240_PBYTE_Pos)                      /*!< GPIO_PORT B240: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B241  -----------------------------------------
-#define GPIO_PORT_B241_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B241: PBYTE Position      */
-#define GPIO_PORT_B241_PBYTE_Msk                              (0x01UL << GPIO_PORT_B241_PBYTE_Pos)                      /*!< GPIO_PORT B241: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B242  -----------------------------------------
-#define GPIO_PORT_B242_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B242: PBYTE Position      */
-#define GPIO_PORT_B242_PBYTE_Msk                              (0x01UL << GPIO_PORT_B242_PBYTE_Pos)                      /*!< GPIO_PORT B242: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B243  -----------------------------------------
-#define GPIO_PORT_B243_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B243: PBYTE Position      */
-#define GPIO_PORT_B243_PBYTE_Msk                              (0x01UL << GPIO_PORT_B243_PBYTE_Pos)                      /*!< GPIO_PORT B243: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B244  -----------------------------------------
-#define GPIO_PORT_B244_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B244: PBYTE Position      */
-#define GPIO_PORT_B244_PBYTE_Msk                              (0x01UL << GPIO_PORT_B244_PBYTE_Pos)                      /*!< GPIO_PORT B244: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B245  -----------------------------------------
-#define GPIO_PORT_B245_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B245: PBYTE Position      */
-#define GPIO_PORT_B245_PBYTE_Msk                              (0x01UL << GPIO_PORT_B245_PBYTE_Pos)                      /*!< GPIO_PORT B245: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B246  -----------------------------------------
-#define GPIO_PORT_B246_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B246: PBYTE Position      */
-#define GPIO_PORT_B246_PBYTE_Msk                              (0x01UL << GPIO_PORT_B246_PBYTE_Pos)                      /*!< GPIO_PORT B246: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B247  -----------------------------------------
-#define GPIO_PORT_B247_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B247: PBYTE Position      */
-#define GPIO_PORT_B247_PBYTE_Msk                              (0x01UL << GPIO_PORT_B247_PBYTE_Pos)                      /*!< GPIO_PORT B247: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B248  -----------------------------------------
-#define GPIO_PORT_B248_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B248: PBYTE Position      */
-#define GPIO_PORT_B248_PBYTE_Msk                              (0x01UL << GPIO_PORT_B248_PBYTE_Pos)                      /*!< GPIO_PORT B248: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B249  -----------------------------------------
-#define GPIO_PORT_B249_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B249: PBYTE Position      */
-#define GPIO_PORT_B249_PBYTE_Msk                              (0x01UL << GPIO_PORT_B249_PBYTE_Pos)                      /*!< GPIO_PORT B249: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B250  -----------------------------------------
-#define GPIO_PORT_B250_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B250: PBYTE Position      */
-#define GPIO_PORT_B250_PBYTE_Msk                              (0x01UL << GPIO_PORT_B250_PBYTE_Pos)                      /*!< GPIO_PORT B250: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B251  -----------------------------------------
-#define GPIO_PORT_B251_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B251: PBYTE Position      */
-#define GPIO_PORT_B251_PBYTE_Msk                              (0x01UL << GPIO_PORT_B251_PBYTE_Pos)                      /*!< GPIO_PORT B251: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B252  -----------------------------------------
-#define GPIO_PORT_B252_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B252: PBYTE Position      */
-#define GPIO_PORT_B252_PBYTE_Msk                              (0x01UL << GPIO_PORT_B252_PBYTE_Pos)                      /*!< GPIO_PORT B252: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B253  -----------------------------------------
-#define GPIO_PORT_B253_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B253: PBYTE Position      */
-#define GPIO_PORT_B253_PBYTE_Msk                              (0x01UL << GPIO_PORT_B253_PBYTE_Pos)                      /*!< GPIO_PORT B253: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B254  -----------------------------------------
-#define GPIO_PORT_B254_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B254: PBYTE Position      */
-#define GPIO_PORT_B254_PBYTE_Msk                              (0x01UL << GPIO_PORT_B254_PBYTE_Pos)                      /*!< GPIO_PORT B254: PBYTE Mask          */
-
-// -------------------------------------  GPIO_PORT_B255  -----------------------------------------
-#define GPIO_PORT_B255_PBYTE_Pos                              0                                                         /*!< GPIO_PORT B255: PBYTE Position      */
-#define GPIO_PORT_B255_PBYTE_Msk                              (0x01UL << GPIO_PORT_B255_PBYTE_Pos)                      /*!< GPIO_PORT B255: PBYTE Mask          */
-
-// --------------------------------------  GPIO_PORT_W0  ------------------------------------------
-#define GPIO_PORT_W0_PWORD_Pos                                0                                                         /*!< GPIO_PORT W0: PWORD Position        */
-#define GPIO_PORT_W0_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W0_PWORD_Pos)                  /*!< GPIO_PORT W0: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W1  ------------------------------------------
-#define GPIO_PORT_W1_PWORD_Pos                                0                                                         /*!< GPIO_PORT W1: PWORD Position        */
-#define GPIO_PORT_W1_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W1_PWORD_Pos)                  /*!< GPIO_PORT W1: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W2  ------------------------------------------
-#define GPIO_PORT_W2_PWORD_Pos                                0                                                         /*!< GPIO_PORT W2: PWORD Position        */
-#define GPIO_PORT_W2_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W2_PWORD_Pos)                  /*!< GPIO_PORT W2: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W3  ------------------------------------------
-#define GPIO_PORT_W3_PWORD_Pos                                0                                                         /*!< GPIO_PORT W3: PWORD Position        */
-#define GPIO_PORT_W3_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W3_PWORD_Pos)                  /*!< GPIO_PORT W3: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W4  ------------------------------------------
-#define GPIO_PORT_W4_PWORD_Pos                                0                                                         /*!< GPIO_PORT W4: PWORD Position        */
-#define GPIO_PORT_W4_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W4_PWORD_Pos)                  /*!< GPIO_PORT W4: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W5  ------------------------------------------
-#define GPIO_PORT_W5_PWORD_Pos                                0                                                         /*!< GPIO_PORT W5: PWORD Position        */
-#define GPIO_PORT_W5_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W5_PWORD_Pos)                  /*!< GPIO_PORT W5: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W6  ------------------------------------------
-#define GPIO_PORT_W6_PWORD_Pos                                0                                                         /*!< GPIO_PORT W6: PWORD Position        */
-#define GPIO_PORT_W6_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W6_PWORD_Pos)                  /*!< GPIO_PORT W6: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W7  ------------------------------------------
-#define GPIO_PORT_W7_PWORD_Pos                                0                                                         /*!< GPIO_PORT W7: PWORD Position        */
-#define GPIO_PORT_W7_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W7_PWORD_Pos)                  /*!< GPIO_PORT W7: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W8  ------------------------------------------
-#define GPIO_PORT_W8_PWORD_Pos                                0                                                         /*!< GPIO_PORT W8: PWORD Position        */
-#define GPIO_PORT_W8_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W8_PWORD_Pos)                  /*!< GPIO_PORT W8: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W9  ------------------------------------------
-#define GPIO_PORT_W9_PWORD_Pos                                0                                                         /*!< GPIO_PORT W9: PWORD Position        */
-#define GPIO_PORT_W9_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W9_PWORD_Pos)                  /*!< GPIO_PORT W9: PWORD Mask            */
-
-// --------------------------------------  GPIO_PORT_W10  -----------------------------------------
-#define GPIO_PORT_W10_PWORD_Pos                               0                                                         /*!< GPIO_PORT W10: PWORD Position       */
-#define GPIO_PORT_W10_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W10_PWORD_Pos)                 /*!< GPIO_PORT W10: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W11  -----------------------------------------
-#define GPIO_PORT_W11_PWORD_Pos                               0                                                         /*!< GPIO_PORT W11: PWORD Position       */
-#define GPIO_PORT_W11_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W11_PWORD_Pos)                 /*!< GPIO_PORT W11: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W12  -----------------------------------------
-#define GPIO_PORT_W12_PWORD_Pos                               0                                                         /*!< GPIO_PORT W12: PWORD Position       */
-#define GPIO_PORT_W12_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W12_PWORD_Pos)                 /*!< GPIO_PORT W12: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W13  -----------------------------------------
-#define GPIO_PORT_W13_PWORD_Pos                               0                                                         /*!< GPIO_PORT W13: PWORD Position       */
-#define GPIO_PORT_W13_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W13_PWORD_Pos)                 /*!< GPIO_PORT W13: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W14  -----------------------------------------
-#define GPIO_PORT_W14_PWORD_Pos                               0                                                         /*!< GPIO_PORT W14: PWORD Position       */
-#define GPIO_PORT_W14_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W14_PWORD_Pos)                 /*!< GPIO_PORT W14: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W15  -----------------------------------------
-#define GPIO_PORT_W15_PWORD_Pos                               0                                                         /*!< GPIO_PORT W15: PWORD Position       */
-#define GPIO_PORT_W15_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W15_PWORD_Pos)                 /*!< GPIO_PORT W15: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W16  -----------------------------------------
-#define GPIO_PORT_W16_PWORD_Pos                               0                                                         /*!< GPIO_PORT W16: PWORD Position       */
-#define GPIO_PORT_W16_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W16_PWORD_Pos)                 /*!< GPIO_PORT W16: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W17  -----------------------------------------
-#define GPIO_PORT_W17_PWORD_Pos                               0                                                         /*!< GPIO_PORT W17: PWORD Position       */
-#define GPIO_PORT_W17_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W17_PWORD_Pos)                 /*!< GPIO_PORT W17: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W18  -----------------------------------------
-#define GPIO_PORT_W18_PWORD_Pos                               0                                                         /*!< GPIO_PORT W18: PWORD Position       */
-#define GPIO_PORT_W18_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W18_PWORD_Pos)                 /*!< GPIO_PORT W18: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W19  -----------------------------------------
-#define GPIO_PORT_W19_PWORD_Pos                               0                                                         /*!< GPIO_PORT W19: PWORD Position       */
-#define GPIO_PORT_W19_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W19_PWORD_Pos)                 /*!< GPIO_PORT W19: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W20  -----------------------------------------
-#define GPIO_PORT_W20_PWORD_Pos                               0                                                         /*!< GPIO_PORT W20: PWORD Position       */
-#define GPIO_PORT_W20_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W20_PWORD_Pos)                 /*!< GPIO_PORT W20: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W21  -----------------------------------------
-#define GPIO_PORT_W21_PWORD_Pos                               0                                                         /*!< GPIO_PORT W21: PWORD Position       */
-#define GPIO_PORT_W21_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W21_PWORD_Pos)                 /*!< GPIO_PORT W21: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W22  -----------------------------------------
-#define GPIO_PORT_W22_PWORD_Pos                               0                                                         /*!< GPIO_PORT W22: PWORD Position       */
-#define GPIO_PORT_W22_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W22_PWORD_Pos)                 /*!< GPIO_PORT W22: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W23  -----------------------------------------
-#define GPIO_PORT_W23_PWORD_Pos                               0                                                         /*!< GPIO_PORT W23: PWORD Position       */
-#define GPIO_PORT_W23_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W23_PWORD_Pos)                 /*!< GPIO_PORT W23: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W24  -----------------------------------------
-#define GPIO_PORT_W24_PWORD_Pos                               0                                                         /*!< GPIO_PORT W24: PWORD Position       */
-#define GPIO_PORT_W24_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W24_PWORD_Pos)                 /*!< GPIO_PORT W24: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W25  -----------------------------------------
-#define GPIO_PORT_W25_PWORD_Pos                               0                                                         /*!< GPIO_PORT W25: PWORD Position       */
-#define GPIO_PORT_W25_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W25_PWORD_Pos)                 /*!< GPIO_PORT W25: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W26  -----------------------------------------
-#define GPIO_PORT_W26_PWORD_Pos                               0                                                         /*!< GPIO_PORT W26: PWORD Position       */
-#define GPIO_PORT_W26_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W26_PWORD_Pos)                 /*!< GPIO_PORT W26: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W27  -----------------------------------------
-#define GPIO_PORT_W27_PWORD_Pos                               0                                                         /*!< GPIO_PORT W27: PWORD Position       */
-#define GPIO_PORT_W27_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W27_PWORD_Pos)                 /*!< GPIO_PORT W27: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W28  -----------------------------------------
-#define GPIO_PORT_W28_PWORD_Pos                               0                                                         /*!< GPIO_PORT W28: PWORD Position       */
-#define GPIO_PORT_W28_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W28_PWORD_Pos)                 /*!< GPIO_PORT W28: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W29  -----------------------------------------
-#define GPIO_PORT_W29_PWORD_Pos                               0                                                         /*!< GPIO_PORT W29: PWORD Position       */
-#define GPIO_PORT_W29_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W29_PWORD_Pos)                 /*!< GPIO_PORT W29: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W30  -----------------------------------------
-#define GPIO_PORT_W30_PWORD_Pos                               0                                                         /*!< GPIO_PORT W30: PWORD Position       */
-#define GPIO_PORT_W30_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W30_PWORD_Pos)                 /*!< GPIO_PORT W30: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W31  -----------------------------------------
-#define GPIO_PORT_W31_PWORD_Pos                               0                                                         /*!< GPIO_PORT W31: PWORD Position       */
-#define GPIO_PORT_W31_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W31_PWORD_Pos)                 /*!< GPIO_PORT W31: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W32  -----------------------------------------
-#define GPIO_PORT_W32_PWORD_Pos                               0                                                         /*!< GPIO_PORT W32: PWORD Position       */
-#define GPIO_PORT_W32_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W32_PWORD_Pos)                 /*!< GPIO_PORT W32: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W33  -----------------------------------------
-#define GPIO_PORT_W33_PWORD_Pos                               0                                                         /*!< GPIO_PORT W33: PWORD Position       */
-#define GPIO_PORT_W33_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W33_PWORD_Pos)                 /*!< GPIO_PORT W33: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W34  -----------------------------------------
-#define GPIO_PORT_W34_PWORD_Pos                               0                                                         /*!< GPIO_PORT W34: PWORD Position       */
-#define GPIO_PORT_W34_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W34_PWORD_Pos)                 /*!< GPIO_PORT W34: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W35  -----------------------------------------
-#define GPIO_PORT_W35_PWORD_Pos                               0                                                         /*!< GPIO_PORT W35: PWORD Position       */
-#define GPIO_PORT_W35_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W35_PWORD_Pos)                 /*!< GPIO_PORT W35: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W36  -----------------------------------------
-#define GPIO_PORT_W36_PWORD_Pos                               0                                                         /*!< GPIO_PORT W36: PWORD Position       */
-#define GPIO_PORT_W36_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W36_PWORD_Pos)                 /*!< GPIO_PORT W36: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W37  -----------------------------------------
-#define GPIO_PORT_W37_PWORD_Pos                               0                                                         /*!< GPIO_PORT W37: PWORD Position       */
-#define GPIO_PORT_W37_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W37_PWORD_Pos)                 /*!< GPIO_PORT W37: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W38  -----------------------------------------
-#define GPIO_PORT_W38_PWORD_Pos                               0                                                         /*!< GPIO_PORT W38: PWORD Position       */
-#define GPIO_PORT_W38_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W38_PWORD_Pos)                 /*!< GPIO_PORT W38: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W39  -----------------------------------------
-#define GPIO_PORT_W39_PWORD_Pos                               0                                                         /*!< GPIO_PORT W39: PWORD Position       */
-#define GPIO_PORT_W39_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W39_PWORD_Pos)                 /*!< GPIO_PORT W39: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W40  -----------------------------------------
-#define GPIO_PORT_W40_PWORD_Pos                               0                                                         /*!< GPIO_PORT W40: PWORD Position       */
-#define GPIO_PORT_W40_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W40_PWORD_Pos)                 /*!< GPIO_PORT W40: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W41  -----------------------------------------
-#define GPIO_PORT_W41_PWORD_Pos                               0                                                         /*!< GPIO_PORT W41: PWORD Position       */
-#define GPIO_PORT_W41_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W41_PWORD_Pos)                 /*!< GPIO_PORT W41: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W42  -----------------------------------------
-#define GPIO_PORT_W42_PWORD_Pos                               0                                                         /*!< GPIO_PORT W42: PWORD Position       */
-#define GPIO_PORT_W42_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W42_PWORD_Pos)                 /*!< GPIO_PORT W42: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W43  -----------------------------------------
-#define GPIO_PORT_W43_PWORD_Pos                               0                                                         /*!< GPIO_PORT W43: PWORD Position       */
-#define GPIO_PORT_W43_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W43_PWORD_Pos)                 /*!< GPIO_PORT W43: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W44  -----------------------------------------
-#define GPIO_PORT_W44_PWORD_Pos                               0                                                         /*!< GPIO_PORT W44: PWORD Position       */
-#define GPIO_PORT_W44_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W44_PWORD_Pos)                 /*!< GPIO_PORT W44: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W45  -----------------------------------------
-#define GPIO_PORT_W45_PWORD_Pos                               0                                                         /*!< GPIO_PORT W45: PWORD Position       */
-#define GPIO_PORT_W45_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W45_PWORD_Pos)                 /*!< GPIO_PORT W45: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W46  -----------------------------------------
-#define GPIO_PORT_W46_PWORD_Pos                               0                                                         /*!< GPIO_PORT W46: PWORD Position       */
-#define GPIO_PORT_W46_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W46_PWORD_Pos)                 /*!< GPIO_PORT W46: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W47  -----------------------------------------
-#define GPIO_PORT_W47_PWORD_Pos                               0                                                         /*!< GPIO_PORT W47: PWORD Position       */
-#define GPIO_PORT_W47_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W47_PWORD_Pos)                 /*!< GPIO_PORT W47: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W48  -----------------------------------------
-#define GPIO_PORT_W48_PWORD_Pos                               0                                                         /*!< GPIO_PORT W48: PWORD Position       */
-#define GPIO_PORT_W48_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W48_PWORD_Pos)                 /*!< GPIO_PORT W48: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W49  -----------------------------------------
-#define GPIO_PORT_W49_PWORD_Pos                               0                                                         /*!< GPIO_PORT W49: PWORD Position       */
-#define GPIO_PORT_W49_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W49_PWORD_Pos)                 /*!< GPIO_PORT W49: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W50  -----------------------------------------
-#define GPIO_PORT_W50_PWORD_Pos                               0                                                         /*!< GPIO_PORT W50: PWORD Position       */
-#define GPIO_PORT_W50_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W50_PWORD_Pos)                 /*!< GPIO_PORT W50: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W51  -----------------------------------------
-#define GPIO_PORT_W51_PWORD_Pos                               0                                                         /*!< GPIO_PORT W51: PWORD Position       */
-#define GPIO_PORT_W51_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W51_PWORD_Pos)                 /*!< GPIO_PORT W51: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W52  -----------------------------------------
-#define GPIO_PORT_W52_PWORD_Pos                               0                                                         /*!< GPIO_PORT W52: PWORD Position       */
-#define GPIO_PORT_W52_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W52_PWORD_Pos)                 /*!< GPIO_PORT W52: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W53  -----------------------------------------
-#define GPIO_PORT_W53_PWORD_Pos                               0                                                         /*!< GPIO_PORT W53: PWORD Position       */
-#define GPIO_PORT_W53_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W53_PWORD_Pos)                 /*!< GPIO_PORT W53: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W54  -----------------------------------------
-#define GPIO_PORT_W54_PWORD_Pos                               0                                                         /*!< GPIO_PORT W54: PWORD Position       */
-#define GPIO_PORT_W54_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W54_PWORD_Pos)                 /*!< GPIO_PORT W54: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W55  -----------------------------------------
-#define GPIO_PORT_W55_PWORD_Pos                               0                                                         /*!< GPIO_PORT W55: PWORD Position       */
-#define GPIO_PORT_W55_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W55_PWORD_Pos)                 /*!< GPIO_PORT W55: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W56  -----------------------------------------
-#define GPIO_PORT_W56_PWORD_Pos                               0                                                         /*!< GPIO_PORT W56: PWORD Position       */
-#define GPIO_PORT_W56_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W56_PWORD_Pos)                 /*!< GPIO_PORT W56: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W57  -----------------------------------------
-#define GPIO_PORT_W57_PWORD_Pos                               0                                                         /*!< GPIO_PORT W57: PWORD Position       */
-#define GPIO_PORT_W57_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W57_PWORD_Pos)                 /*!< GPIO_PORT W57: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W58  -----------------------------------------
-#define GPIO_PORT_W58_PWORD_Pos                               0                                                         /*!< GPIO_PORT W58: PWORD Position       */
-#define GPIO_PORT_W58_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W58_PWORD_Pos)                 /*!< GPIO_PORT W58: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W59  -----------------------------------------
-#define GPIO_PORT_W59_PWORD_Pos                               0                                                         /*!< GPIO_PORT W59: PWORD Position       */
-#define GPIO_PORT_W59_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W59_PWORD_Pos)                 /*!< GPIO_PORT W59: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W60  -----------------------------------------
-#define GPIO_PORT_W60_PWORD_Pos                               0                                                         /*!< GPIO_PORT W60: PWORD Position       */
-#define GPIO_PORT_W60_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W60_PWORD_Pos)                 /*!< GPIO_PORT W60: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W61  -----------------------------------------
-#define GPIO_PORT_W61_PWORD_Pos                               0                                                         /*!< GPIO_PORT W61: PWORD Position       */
-#define GPIO_PORT_W61_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W61_PWORD_Pos)                 /*!< GPIO_PORT W61: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W62  -----------------------------------------
-#define GPIO_PORT_W62_PWORD_Pos                               0                                                         /*!< GPIO_PORT W62: PWORD Position       */
-#define GPIO_PORT_W62_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W62_PWORD_Pos)                 /*!< GPIO_PORT W62: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W63  -----------------------------------------
-#define GPIO_PORT_W63_PWORD_Pos                               0                                                         /*!< GPIO_PORT W63: PWORD Position       */
-#define GPIO_PORT_W63_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W63_PWORD_Pos)                 /*!< GPIO_PORT W63: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W64  -----------------------------------------
-#define GPIO_PORT_W64_PWORD_Pos                               0                                                         /*!< GPIO_PORT W64: PWORD Position       */
-#define GPIO_PORT_W64_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W64_PWORD_Pos)                 /*!< GPIO_PORT W64: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W65  -----------------------------------------
-#define GPIO_PORT_W65_PWORD_Pos                               0                                                         /*!< GPIO_PORT W65: PWORD Position       */
-#define GPIO_PORT_W65_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W65_PWORD_Pos)                 /*!< GPIO_PORT W65: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W66  -----------------------------------------
-#define GPIO_PORT_W66_PWORD_Pos                               0                                                         /*!< GPIO_PORT W66: PWORD Position       */
-#define GPIO_PORT_W66_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W66_PWORD_Pos)                 /*!< GPIO_PORT W66: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W67  -----------------------------------------
-#define GPIO_PORT_W67_PWORD_Pos                               0                                                         /*!< GPIO_PORT W67: PWORD Position       */
-#define GPIO_PORT_W67_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W67_PWORD_Pos)                 /*!< GPIO_PORT W67: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W68  -----------------------------------------
-#define GPIO_PORT_W68_PWORD_Pos                               0                                                         /*!< GPIO_PORT W68: PWORD Position       */
-#define GPIO_PORT_W68_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W68_PWORD_Pos)                 /*!< GPIO_PORT W68: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W69  -----------------------------------------
-#define GPIO_PORT_W69_PWORD_Pos                               0                                                         /*!< GPIO_PORT W69: PWORD Position       */
-#define GPIO_PORT_W69_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W69_PWORD_Pos)                 /*!< GPIO_PORT W69: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W70  -----------------------------------------
-#define GPIO_PORT_W70_PWORD_Pos                               0                                                         /*!< GPIO_PORT W70: PWORD Position       */
-#define GPIO_PORT_W70_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W70_PWORD_Pos)                 /*!< GPIO_PORT W70: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W71  -----------------------------------------
-#define GPIO_PORT_W71_PWORD_Pos                               0                                                         /*!< GPIO_PORT W71: PWORD Position       */
-#define GPIO_PORT_W71_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W71_PWORD_Pos)                 /*!< GPIO_PORT W71: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W72  -----------------------------------------
-#define GPIO_PORT_W72_PWORD_Pos                               0                                                         /*!< GPIO_PORT W72: PWORD Position       */
-#define GPIO_PORT_W72_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W72_PWORD_Pos)                 /*!< GPIO_PORT W72: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W73  -----------------------------------------
-#define GPIO_PORT_W73_PWORD_Pos                               0                                                         /*!< GPIO_PORT W73: PWORD Position       */
-#define GPIO_PORT_W73_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W73_PWORD_Pos)                 /*!< GPIO_PORT W73: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W74  -----------------------------------------
-#define GPIO_PORT_W74_PWORD_Pos                               0                                                         /*!< GPIO_PORT W74: PWORD Position       */
-#define GPIO_PORT_W74_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W74_PWORD_Pos)                 /*!< GPIO_PORT W74: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W75  -----------------------------------------
-#define GPIO_PORT_W75_PWORD_Pos                               0                                                         /*!< GPIO_PORT W75: PWORD Position       */
-#define GPIO_PORT_W75_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W75_PWORD_Pos)                 /*!< GPIO_PORT W75: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W76  -----------------------------------------
-#define GPIO_PORT_W76_PWORD_Pos                               0                                                         /*!< GPIO_PORT W76: PWORD Position       */
-#define GPIO_PORT_W76_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W76_PWORD_Pos)                 /*!< GPIO_PORT W76: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W77  -----------------------------------------
-#define GPIO_PORT_W77_PWORD_Pos                               0                                                         /*!< GPIO_PORT W77: PWORD Position       */
-#define GPIO_PORT_W77_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W77_PWORD_Pos)                 /*!< GPIO_PORT W77: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W78  -----------------------------------------
-#define GPIO_PORT_W78_PWORD_Pos                               0                                                         /*!< GPIO_PORT W78: PWORD Position       */
-#define GPIO_PORT_W78_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W78_PWORD_Pos)                 /*!< GPIO_PORT W78: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W79  -----------------------------------------
-#define GPIO_PORT_W79_PWORD_Pos                               0                                                         /*!< GPIO_PORT W79: PWORD Position       */
-#define GPIO_PORT_W79_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W79_PWORD_Pos)                 /*!< GPIO_PORT W79: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W80  -----------------------------------------
-#define GPIO_PORT_W80_PWORD_Pos                               0                                                         /*!< GPIO_PORT W80: PWORD Position       */
-#define GPIO_PORT_W80_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W80_PWORD_Pos)                 /*!< GPIO_PORT W80: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W81  -----------------------------------------
-#define GPIO_PORT_W81_PWORD_Pos                               0                                                         /*!< GPIO_PORT W81: PWORD Position       */
-#define GPIO_PORT_W81_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W81_PWORD_Pos)                 /*!< GPIO_PORT W81: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W82  -----------------------------------------
-#define GPIO_PORT_W82_PWORD_Pos                               0                                                         /*!< GPIO_PORT W82: PWORD Position       */
-#define GPIO_PORT_W82_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W82_PWORD_Pos)                 /*!< GPIO_PORT W82: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W83  -----------------------------------------
-#define GPIO_PORT_W83_PWORD_Pos                               0                                                         /*!< GPIO_PORT W83: PWORD Position       */
-#define GPIO_PORT_W83_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W83_PWORD_Pos)                 /*!< GPIO_PORT W83: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W84  -----------------------------------------
-#define GPIO_PORT_W84_PWORD_Pos                               0                                                         /*!< GPIO_PORT W84: PWORD Position       */
-#define GPIO_PORT_W84_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W84_PWORD_Pos)                 /*!< GPIO_PORT W84: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W85  -----------------------------------------
-#define GPIO_PORT_W85_PWORD_Pos                               0                                                         /*!< GPIO_PORT W85: PWORD Position       */
-#define GPIO_PORT_W85_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W85_PWORD_Pos)                 /*!< GPIO_PORT W85: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W86  -----------------------------------------
-#define GPIO_PORT_W86_PWORD_Pos                               0                                                         /*!< GPIO_PORT W86: PWORD Position       */
-#define GPIO_PORT_W86_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W86_PWORD_Pos)                 /*!< GPIO_PORT W86: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W87  -----------------------------------------
-#define GPIO_PORT_W87_PWORD_Pos                               0                                                         /*!< GPIO_PORT W87: PWORD Position       */
-#define GPIO_PORT_W87_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W87_PWORD_Pos)                 /*!< GPIO_PORT W87: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W88  -----------------------------------------
-#define GPIO_PORT_W88_PWORD_Pos                               0                                                         /*!< GPIO_PORT W88: PWORD Position       */
-#define GPIO_PORT_W88_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W88_PWORD_Pos)                 /*!< GPIO_PORT W88: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W89  -----------------------------------------
-#define GPIO_PORT_W89_PWORD_Pos                               0                                                         /*!< GPIO_PORT W89: PWORD Position       */
-#define GPIO_PORT_W89_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W89_PWORD_Pos)                 /*!< GPIO_PORT W89: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W90  -----------------------------------------
-#define GPIO_PORT_W90_PWORD_Pos                               0                                                         /*!< GPIO_PORT W90: PWORD Position       */
-#define GPIO_PORT_W90_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W90_PWORD_Pos)                 /*!< GPIO_PORT W90: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W91  -----------------------------------------
-#define GPIO_PORT_W91_PWORD_Pos                               0                                                         /*!< GPIO_PORT W91: PWORD Position       */
-#define GPIO_PORT_W91_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W91_PWORD_Pos)                 /*!< GPIO_PORT W91: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W92  -----------------------------------------
-#define GPIO_PORT_W92_PWORD_Pos                               0                                                         /*!< GPIO_PORT W92: PWORD Position       */
-#define GPIO_PORT_W92_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W92_PWORD_Pos)                 /*!< GPIO_PORT W92: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W93  -----------------------------------------
-#define GPIO_PORT_W93_PWORD_Pos                               0                                                         /*!< GPIO_PORT W93: PWORD Position       */
-#define GPIO_PORT_W93_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W93_PWORD_Pos)                 /*!< GPIO_PORT W93: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W94  -----------------------------------------
-#define GPIO_PORT_W94_PWORD_Pos                               0                                                         /*!< GPIO_PORT W94: PWORD Position       */
-#define GPIO_PORT_W94_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W94_PWORD_Pos)                 /*!< GPIO_PORT W94: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W95  -----------------------------------------
-#define GPIO_PORT_W95_PWORD_Pos                               0                                                         /*!< GPIO_PORT W95: PWORD Position       */
-#define GPIO_PORT_W95_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W95_PWORD_Pos)                 /*!< GPIO_PORT W95: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W96  -----------------------------------------
-#define GPIO_PORT_W96_PWORD_Pos                               0                                                         /*!< GPIO_PORT W96: PWORD Position       */
-#define GPIO_PORT_W96_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W96_PWORD_Pos)                 /*!< GPIO_PORT W96: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W97  -----------------------------------------
-#define GPIO_PORT_W97_PWORD_Pos                               0                                                         /*!< GPIO_PORT W97: PWORD Position       */
-#define GPIO_PORT_W97_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W97_PWORD_Pos)                 /*!< GPIO_PORT W97: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W98  -----------------------------------------
-#define GPIO_PORT_W98_PWORD_Pos                               0                                                         /*!< GPIO_PORT W98: PWORD Position       */
-#define GPIO_PORT_W98_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W98_PWORD_Pos)                 /*!< GPIO_PORT W98: PWORD Mask           */
-
-// --------------------------------------  GPIO_PORT_W99  -----------------------------------------
-#define GPIO_PORT_W99_PWORD_Pos                               0                                                         /*!< GPIO_PORT W99: PWORD Position       */
-#define GPIO_PORT_W99_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W99_PWORD_Pos)                 /*!< GPIO_PORT W99: PWORD Mask           */
-
-// -------------------------------------  GPIO_PORT_W100  -----------------------------------------
-#define GPIO_PORT_W100_PWORD_Pos                              0                                                         /*!< GPIO_PORT W100: PWORD Position      */
-#define GPIO_PORT_W100_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W100_PWORD_Pos)                /*!< GPIO_PORT W100: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W101  -----------------------------------------
-#define GPIO_PORT_W101_PWORD_Pos                              0                                                         /*!< GPIO_PORT W101: PWORD Position      */
-#define GPIO_PORT_W101_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W101_PWORD_Pos)                /*!< GPIO_PORT W101: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W102  -----------------------------------------
-#define GPIO_PORT_W102_PWORD_Pos                              0                                                         /*!< GPIO_PORT W102: PWORD Position      */
-#define GPIO_PORT_W102_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W102_PWORD_Pos)                /*!< GPIO_PORT W102: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W103  -----------------------------------------
-#define GPIO_PORT_W103_PWORD_Pos                              0                                                         /*!< GPIO_PORT W103: PWORD Position      */
-#define GPIO_PORT_W103_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W103_PWORD_Pos)                /*!< GPIO_PORT W103: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W104  -----------------------------------------
-#define GPIO_PORT_W104_PWORD_Pos                              0                                                         /*!< GPIO_PORT W104: PWORD Position      */
-#define GPIO_PORT_W104_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W104_PWORD_Pos)                /*!< GPIO_PORT W104: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W105  -----------------------------------------
-#define GPIO_PORT_W105_PWORD_Pos                              0                                                         /*!< GPIO_PORT W105: PWORD Position      */
-#define GPIO_PORT_W105_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W105_PWORD_Pos)                /*!< GPIO_PORT W105: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W106  -----------------------------------------
-#define GPIO_PORT_W106_PWORD_Pos                              0                                                         /*!< GPIO_PORT W106: PWORD Position      */
-#define GPIO_PORT_W106_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W106_PWORD_Pos)                /*!< GPIO_PORT W106: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W107  -----------------------------------------
-#define GPIO_PORT_W107_PWORD_Pos                              0                                                         /*!< GPIO_PORT W107: PWORD Position      */
-#define GPIO_PORT_W107_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W107_PWORD_Pos)                /*!< GPIO_PORT W107: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W108  -----------------------------------------
-#define GPIO_PORT_W108_PWORD_Pos                              0                                                         /*!< GPIO_PORT W108: PWORD Position      */
-#define GPIO_PORT_W108_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W108_PWORD_Pos)                /*!< GPIO_PORT W108: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W109  -----------------------------------------
-#define GPIO_PORT_W109_PWORD_Pos                              0                                                         /*!< GPIO_PORT W109: PWORD Position      */
-#define GPIO_PORT_W109_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W109_PWORD_Pos)                /*!< GPIO_PORT W109: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W110  -----------------------------------------
-#define GPIO_PORT_W110_PWORD_Pos                              0                                                         /*!< GPIO_PORT W110: PWORD Position      */
-#define GPIO_PORT_W110_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W110_PWORD_Pos)                /*!< GPIO_PORT W110: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W111  -----------------------------------------
-#define GPIO_PORT_W111_PWORD_Pos                              0                                                         /*!< GPIO_PORT W111: PWORD Position      */
-#define GPIO_PORT_W111_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W111_PWORD_Pos)                /*!< GPIO_PORT W111: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W112  -----------------------------------------
-#define GPIO_PORT_W112_PWORD_Pos                              0                                                         /*!< GPIO_PORT W112: PWORD Position      */
-#define GPIO_PORT_W112_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W112_PWORD_Pos)                /*!< GPIO_PORT W112: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W113  -----------------------------------------
-#define GPIO_PORT_W113_PWORD_Pos                              0                                                         /*!< GPIO_PORT W113: PWORD Position      */
-#define GPIO_PORT_W113_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W113_PWORD_Pos)                /*!< GPIO_PORT W113: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W114  -----------------------------------------
-#define GPIO_PORT_W114_PWORD_Pos                              0                                                         /*!< GPIO_PORT W114: PWORD Position      */
-#define GPIO_PORT_W114_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W114_PWORD_Pos)                /*!< GPIO_PORT W114: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W115  -----------------------------------------
-#define GPIO_PORT_W115_PWORD_Pos                              0                                                         /*!< GPIO_PORT W115: PWORD Position      */
-#define GPIO_PORT_W115_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W115_PWORD_Pos)                /*!< GPIO_PORT W115: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W116  -----------------------------------------
-#define GPIO_PORT_W116_PWORD_Pos                              0                                                         /*!< GPIO_PORT W116: PWORD Position      */
-#define GPIO_PORT_W116_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W116_PWORD_Pos)                /*!< GPIO_PORT W116: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W117  -----------------------------------------
-#define GPIO_PORT_W117_PWORD_Pos                              0                                                         /*!< GPIO_PORT W117: PWORD Position      */
-#define GPIO_PORT_W117_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W117_PWORD_Pos)                /*!< GPIO_PORT W117: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W118  -----------------------------------------
-#define GPIO_PORT_W118_PWORD_Pos                              0                                                         /*!< GPIO_PORT W118: PWORD Position      */
-#define GPIO_PORT_W118_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W118_PWORD_Pos)                /*!< GPIO_PORT W118: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W119  -----------------------------------------
-#define GPIO_PORT_W119_PWORD_Pos                              0                                                         /*!< GPIO_PORT W119: PWORD Position      */
-#define GPIO_PORT_W119_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W119_PWORD_Pos)                /*!< GPIO_PORT W119: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W120  -----------------------------------------
-#define GPIO_PORT_W120_PWORD_Pos                              0                                                         /*!< GPIO_PORT W120: PWORD Position      */
-#define GPIO_PORT_W120_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W120_PWORD_Pos)                /*!< GPIO_PORT W120: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W121  -----------------------------------------
-#define GPIO_PORT_W121_PWORD_Pos                              0                                                         /*!< GPIO_PORT W121: PWORD Position      */
-#define GPIO_PORT_W121_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W121_PWORD_Pos)                /*!< GPIO_PORT W121: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W122  -----------------------------------------
-#define GPIO_PORT_W122_PWORD_Pos                              0                                                         /*!< GPIO_PORT W122: PWORD Position      */
-#define GPIO_PORT_W122_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W122_PWORD_Pos)                /*!< GPIO_PORT W122: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W123  -----------------------------------------
-#define GPIO_PORT_W123_PWORD_Pos                              0                                                         /*!< GPIO_PORT W123: PWORD Position      */
-#define GPIO_PORT_W123_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W123_PWORD_Pos)                /*!< GPIO_PORT W123: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W124  -----------------------------------------
-#define GPIO_PORT_W124_PWORD_Pos                              0                                                         /*!< GPIO_PORT W124: PWORD Position      */
-#define GPIO_PORT_W124_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W124_PWORD_Pos)                /*!< GPIO_PORT W124: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W125  -----------------------------------------
-#define GPIO_PORT_W125_PWORD_Pos                              0                                                         /*!< GPIO_PORT W125: PWORD Position      */
-#define GPIO_PORT_W125_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W125_PWORD_Pos)                /*!< GPIO_PORT W125: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W126  -----------------------------------------
-#define GPIO_PORT_W126_PWORD_Pos                              0                                                         /*!< GPIO_PORT W126: PWORD Position      */
-#define GPIO_PORT_W126_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W126_PWORD_Pos)                /*!< GPIO_PORT W126: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W127  -----------------------------------------
-#define GPIO_PORT_W127_PWORD_Pos                              0                                                         /*!< GPIO_PORT W127: PWORD Position      */
-#define GPIO_PORT_W127_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W127_PWORD_Pos)                /*!< GPIO_PORT W127: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W128  -----------------------------------------
-#define GPIO_PORT_W128_PWORD_Pos                              0                                                         /*!< GPIO_PORT W128: PWORD Position      */
-#define GPIO_PORT_W128_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W128_PWORD_Pos)                /*!< GPIO_PORT W128: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W129  -----------------------------------------
-#define GPIO_PORT_W129_PWORD_Pos                              0                                                         /*!< GPIO_PORT W129: PWORD Position      */
-#define GPIO_PORT_W129_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W129_PWORD_Pos)                /*!< GPIO_PORT W129: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W130  -----------------------------------------
-#define GPIO_PORT_W130_PWORD_Pos                              0                                                         /*!< GPIO_PORT W130: PWORD Position      */
-#define GPIO_PORT_W130_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W130_PWORD_Pos)                /*!< GPIO_PORT W130: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W131  -----------------------------------------
-#define GPIO_PORT_W131_PWORD_Pos                              0                                                         /*!< GPIO_PORT W131: PWORD Position      */
-#define GPIO_PORT_W131_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W131_PWORD_Pos)                /*!< GPIO_PORT W131: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W132  -----------------------------------------
-#define GPIO_PORT_W132_PWORD_Pos                              0                                                         /*!< GPIO_PORT W132: PWORD Position      */
-#define GPIO_PORT_W132_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W132_PWORD_Pos)                /*!< GPIO_PORT W132: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W133  -----------------------------------------
-#define GPIO_PORT_W133_PWORD_Pos                              0                                                         /*!< GPIO_PORT W133: PWORD Position      */
-#define GPIO_PORT_W133_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W133_PWORD_Pos)                /*!< GPIO_PORT W133: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W134  -----------------------------------------
-#define GPIO_PORT_W134_PWORD_Pos                              0                                                         /*!< GPIO_PORT W134: PWORD Position      */
-#define GPIO_PORT_W134_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W134_PWORD_Pos)                /*!< GPIO_PORT W134: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W135  -----------------------------------------
-#define GPIO_PORT_W135_PWORD_Pos                              0                                                         /*!< GPIO_PORT W135: PWORD Position      */
-#define GPIO_PORT_W135_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W135_PWORD_Pos)                /*!< GPIO_PORT W135: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W136  -----------------------------------------
-#define GPIO_PORT_W136_PWORD_Pos                              0                                                         /*!< GPIO_PORT W136: PWORD Position      */
-#define GPIO_PORT_W136_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W136_PWORD_Pos)                /*!< GPIO_PORT W136: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W137  -----------------------------------------
-#define GPIO_PORT_W137_PWORD_Pos                              0                                                         /*!< GPIO_PORT W137: PWORD Position      */
-#define GPIO_PORT_W137_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W137_PWORD_Pos)                /*!< GPIO_PORT W137: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W138  -----------------------------------------
-#define GPIO_PORT_W138_PWORD_Pos                              0                                                         /*!< GPIO_PORT W138: PWORD Position      */
-#define GPIO_PORT_W138_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W138_PWORD_Pos)                /*!< GPIO_PORT W138: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W139  -----------------------------------------
-#define GPIO_PORT_W139_PWORD_Pos                              0                                                         /*!< GPIO_PORT W139: PWORD Position      */
-#define GPIO_PORT_W139_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W139_PWORD_Pos)                /*!< GPIO_PORT W139: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W140  -----------------------------------------
-#define GPIO_PORT_W140_PWORD_Pos                              0                                                         /*!< GPIO_PORT W140: PWORD Position      */
-#define GPIO_PORT_W140_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W140_PWORD_Pos)                /*!< GPIO_PORT W140: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W141  -----------------------------------------
-#define GPIO_PORT_W141_PWORD_Pos                              0                                                         /*!< GPIO_PORT W141: PWORD Position      */
-#define GPIO_PORT_W141_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W141_PWORD_Pos)                /*!< GPIO_PORT W141: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W142  -----------------------------------------
-#define GPIO_PORT_W142_PWORD_Pos                              0                                                         /*!< GPIO_PORT W142: PWORD Position      */
-#define GPIO_PORT_W142_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W142_PWORD_Pos)                /*!< GPIO_PORT W142: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W143  -----------------------------------------
-#define GPIO_PORT_W143_PWORD_Pos                              0                                                         /*!< GPIO_PORT W143: PWORD Position      */
-#define GPIO_PORT_W143_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W143_PWORD_Pos)                /*!< GPIO_PORT W143: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W144  -----------------------------------------
-#define GPIO_PORT_W144_PWORD_Pos                              0                                                         /*!< GPIO_PORT W144: PWORD Position      */
-#define GPIO_PORT_W144_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W144_PWORD_Pos)                /*!< GPIO_PORT W144: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W145  -----------------------------------------
-#define GPIO_PORT_W145_PWORD_Pos                              0                                                         /*!< GPIO_PORT W145: PWORD Position      */
-#define GPIO_PORT_W145_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W145_PWORD_Pos)                /*!< GPIO_PORT W145: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W146  -----------------------------------------
-#define GPIO_PORT_W146_PWORD_Pos                              0                                                         /*!< GPIO_PORT W146: PWORD Position      */
-#define GPIO_PORT_W146_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W146_PWORD_Pos)                /*!< GPIO_PORT W146: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W147  -----------------------------------------
-#define GPIO_PORT_W147_PWORD_Pos                              0                                                         /*!< GPIO_PORT W147: PWORD Position      */
-#define GPIO_PORT_W147_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W147_PWORD_Pos)                /*!< GPIO_PORT W147: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W148  -----------------------------------------
-#define GPIO_PORT_W148_PWORD_Pos                              0                                                         /*!< GPIO_PORT W148: PWORD Position      */
-#define GPIO_PORT_W148_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W148_PWORD_Pos)                /*!< GPIO_PORT W148: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W149  -----------------------------------------
-#define GPIO_PORT_W149_PWORD_Pos                              0                                                         /*!< GPIO_PORT W149: PWORD Position      */
-#define GPIO_PORT_W149_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W149_PWORD_Pos)                /*!< GPIO_PORT W149: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W150  -----------------------------------------
-#define GPIO_PORT_W150_PWORD_Pos                              0                                                         /*!< GPIO_PORT W150: PWORD Position      */
-#define GPIO_PORT_W150_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W150_PWORD_Pos)                /*!< GPIO_PORT W150: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W151  -----------------------------------------
-#define GPIO_PORT_W151_PWORD_Pos                              0                                                         /*!< GPIO_PORT W151: PWORD Position      */
-#define GPIO_PORT_W151_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W151_PWORD_Pos)                /*!< GPIO_PORT W151: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W152  -----------------------------------------
-#define GPIO_PORT_W152_PWORD_Pos                              0                                                         /*!< GPIO_PORT W152: PWORD Position      */
-#define GPIO_PORT_W152_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W152_PWORD_Pos)                /*!< GPIO_PORT W152: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W153  -----------------------------------------
-#define GPIO_PORT_W153_PWORD_Pos                              0                                                         /*!< GPIO_PORT W153: PWORD Position      */
-#define GPIO_PORT_W153_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W153_PWORD_Pos)                /*!< GPIO_PORT W153: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W154  -----------------------------------------
-#define GPIO_PORT_W154_PWORD_Pos                              0                                                         /*!< GPIO_PORT W154: PWORD Position      */
-#define GPIO_PORT_W154_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W154_PWORD_Pos)                /*!< GPIO_PORT W154: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W155  -----------------------------------------
-#define GPIO_PORT_W155_PWORD_Pos                              0                                                         /*!< GPIO_PORT W155: PWORD Position      */
-#define GPIO_PORT_W155_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W155_PWORD_Pos)                /*!< GPIO_PORT W155: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W156  -----------------------------------------
-#define GPIO_PORT_W156_PWORD_Pos                              0                                                         /*!< GPIO_PORT W156: PWORD Position      */
-#define GPIO_PORT_W156_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W156_PWORD_Pos)                /*!< GPIO_PORT W156: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W157  -----------------------------------------
-#define GPIO_PORT_W157_PWORD_Pos                              0                                                         /*!< GPIO_PORT W157: PWORD Position      */
-#define GPIO_PORT_W157_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W157_PWORD_Pos)                /*!< GPIO_PORT W157: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W158  -----------------------------------------
-#define GPIO_PORT_W158_PWORD_Pos                              0                                                         /*!< GPIO_PORT W158: PWORD Position      */
-#define GPIO_PORT_W158_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W158_PWORD_Pos)                /*!< GPIO_PORT W158: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W159  -----------------------------------------
-#define GPIO_PORT_W159_PWORD_Pos                              0                                                         /*!< GPIO_PORT W159: PWORD Position      */
-#define GPIO_PORT_W159_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W159_PWORD_Pos)                /*!< GPIO_PORT W159: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W160  -----------------------------------------
-#define GPIO_PORT_W160_PWORD_Pos                              0                                                         /*!< GPIO_PORT W160: PWORD Position      */
-#define GPIO_PORT_W160_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W160_PWORD_Pos)                /*!< GPIO_PORT W160: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W161  -----------------------------------------
-#define GPIO_PORT_W161_PWORD_Pos                              0                                                         /*!< GPIO_PORT W161: PWORD Position      */
-#define GPIO_PORT_W161_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W161_PWORD_Pos)                /*!< GPIO_PORT W161: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W162  -----------------------------------------
-#define GPIO_PORT_W162_PWORD_Pos                              0                                                         /*!< GPIO_PORT W162: PWORD Position      */
-#define GPIO_PORT_W162_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W162_PWORD_Pos)                /*!< GPIO_PORT W162: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W163  -----------------------------------------
-#define GPIO_PORT_W163_PWORD_Pos                              0                                                         /*!< GPIO_PORT W163: PWORD Position      */
-#define GPIO_PORT_W163_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W163_PWORD_Pos)                /*!< GPIO_PORT W163: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W164  -----------------------------------------
-#define GPIO_PORT_W164_PWORD_Pos                              0                                                         /*!< GPIO_PORT W164: PWORD Position      */
-#define GPIO_PORT_W164_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W164_PWORD_Pos)                /*!< GPIO_PORT W164: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W165  -----------------------------------------
-#define GPIO_PORT_W165_PWORD_Pos                              0                                                         /*!< GPIO_PORT W165: PWORD Position      */
-#define GPIO_PORT_W165_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W165_PWORD_Pos)                /*!< GPIO_PORT W165: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W166  -----------------------------------------
-#define GPIO_PORT_W166_PWORD_Pos                              0                                                         /*!< GPIO_PORT W166: PWORD Position      */
-#define GPIO_PORT_W166_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W166_PWORD_Pos)                /*!< GPIO_PORT W166: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W167  -----------------------------------------
-#define GPIO_PORT_W167_PWORD_Pos                              0                                                         /*!< GPIO_PORT W167: PWORD Position      */
-#define GPIO_PORT_W167_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W167_PWORD_Pos)                /*!< GPIO_PORT W167: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W168  -----------------------------------------
-#define GPIO_PORT_W168_PWORD_Pos                              0                                                         /*!< GPIO_PORT W168: PWORD Position      */
-#define GPIO_PORT_W168_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W168_PWORD_Pos)                /*!< GPIO_PORT W168: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W169  -----------------------------------------
-#define GPIO_PORT_W169_PWORD_Pos                              0                                                         /*!< GPIO_PORT W169: PWORD Position      */
-#define GPIO_PORT_W169_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W169_PWORD_Pos)                /*!< GPIO_PORT W169: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W170  -----------------------------------------
-#define GPIO_PORT_W170_PWORD_Pos                              0                                                         /*!< GPIO_PORT W170: PWORD Position      */
-#define GPIO_PORT_W170_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W170_PWORD_Pos)                /*!< GPIO_PORT W170: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W171  -----------------------------------------
-#define GPIO_PORT_W171_PWORD_Pos                              0                                                         /*!< GPIO_PORT W171: PWORD Position      */
-#define GPIO_PORT_W171_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W171_PWORD_Pos)                /*!< GPIO_PORT W171: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W172  -----------------------------------------
-#define GPIO_PORT_W172_PWORD_Pos                              0                                                         /*!< GPIO_PORT W172: PWORD Position      */
-#define GPIO_PORT_W172_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W172_PWORD_Pos)                /*!< GPIO_PORT W172: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W173  -----------------------------------------
-#define GPIO_PORT_W173_PWORD_Pos                              0                                                         /*!< GPIO_PORT W173: PWORD Position      */
-#define GPIO_PORT_W173_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W173_PWORD_Pos)                /*!< GPIO_PORT W173: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W174  -----------------------------------------
-#define GPIO_PORT_W174_PWORD_Pos                              0                                                         /*!< GPIO_PORT W174: PWORD Position      */
-#define GPIO_PORT_W174_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W174_PWORD_Pos)                /*!< GPIO_PORT W174: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W175  -----------------------------------------
-#define GPIO_PORT_W175_PWORD_Pos                              0                                                         /*!< GPIO_PORT W175: PWORD Position      */
-#define GPIO_PORT_W175_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W175_PWORD_Pos)                /*!< GPIO_PORT W175: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W176  -----------------------------------------
-#define GPIO_PORT_W176_PWORD_Pos                              0                                                         /*!< GPIO_PORT W176: PWORD Position      */
-#define GPIO_PORT_W176_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W176_PWORD_Pos)                /*!< GPIO_PORT W176: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W177  -----------------------------------------
-#define GPIO_PORT_W177_PWORD_Pos                              0                                                         /*!< GPIO_PORT W177: PWORD Position      */
-#define GPIO_PORT_W177_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W177_PWORD_Pos)                /*!< GPIO_PORT W177: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W178  -----------------------------------------
-#define GPIO_PORT_W178_PWORD_Pos                              0                                                         /*!< GPIO_PORT W178: PWORD Position      */
-#define GPIO_PORT_W178_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W178_PWORD_Pos)                /*!< GPIO_PORT W178: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W179  -----------------------------------------
-#define GPIO_PORT_W179_PWORD_Pos                              0                                                         /*!< GPIO_PORT W179: PWORD Position      */
-#define GPIO_PORT_W179_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W179_PWORD_Pos)                /*!< GPIO_PORT W179: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W180  -----------------------------------------
-#define GPIO_PORT_W180_PWORD_Pos                              0                                                         /*!< GPIO_PORT W180: PWORD Position      */
-#define GPIO_PORT_W180_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W180_PWORD_Pos)                /*!< GPIO_PORT W180: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W181  -----------------------------------------
-#define GPIO_PORT_W181_PWORD_Pos                              0                                                         /*!< GPIO_PORT W181: PWORD Position      */
-#define GPIO_PORT_W181_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W181_PWORD_Pos)                /*!< GPIO_PORT W181: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W182  -----------------------------------------
-#define GPIO_PORT_W182_PWORD_Pos                              0                                                         /*!< GPIO_PORT W182: PWORD Position      */
-#define GPIO_PORT_W182_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W182_PWORD_Pos)                /*!< GPIO_PORT W182: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W183  -----------------------------------------
-#define GPIO_PORT_W183_PWORD_Pos                              0                                                         /*!< GPIO_PORT W183: PWORD Position      */
-#define GPIO_PORT_W183_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W183_PWORD_Pos)                /*!< GPIO_PORT W183: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W184  -----------------------------------------
-#define GPIO_PORT_W184_PWORD_Pos                              0                                                         /*!< GPIO_PORT W184: PWORD Position      */
-#define GPIO_PORT_W184_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W184_PWORD_Pos)                /*!< GPIO_PORT W184: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W185  -----------------------------------------
-#define GPIO_PORT_W185_PWORD_Pos                              0                                                         /*!< GPIO_PORT W185: PWORD Position      */
-#define GPIO_PORT_W185_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W185_PWORD_Pos)                /*!< GPIO_PORT W185: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W186  -----------------------------------------
-#define GPIO_PORT_W186_PWORD_Pos                              0                                                         /*!< GPIO_PORT W186: PWORD Position      */
-#define GPIO_PORT_W186_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W186_PWORD_Pos)                /*!< GPIO_PORT W186: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W187  -----------------------------------------
-#define GPIO_PORT_W187_PWORD_Pos                              0                                                         /*!< GPIO_PORT W187: PWORD Position      */
-#define GPIO_PORT_W187_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W187_PWORD_Pos)                /*!< GPIO_PORT W187: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W188  -----------------------------------------
-#define GPIO_PORT_W188_PWORD_Pos                              0                                                         /*!< GPIO_PORT W188: PWORD Position      */
-#define GPIO_PORT_W188_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W188_PWORD_Pos)                /*!< GPIO_PORT W188: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W189  -----------------------------------------
-#define GPIO_PORT_W189_PWORD_Pos                              0                                                         /*!< GPIO_PORT W189: PWORD Position      */
-#define GPIO_PORT_W189_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W189_PWORD_Pos)                /*!< GPIO_PORT W189: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W190  -----------------------------------------
-#define GPIO_PORT_W190_PWORD_Pos                              0                                                         /*!< GPIO_PORT W190: PWORD Position      */
-#define GPIO_PORT_W190_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W190_PWORD_Pos)                /*!< GPIO_PORT W190: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W191  -----------------------------------------
-#define GPIO_PORT_W191_PWORD_Pos                              0                                                         /*!< GPIO_PORT W191: PWORD Position      */
-#define GPIO_PORT_W191_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W191_PWORD_Pos)                /*!< GPIO_PORT W191: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W192  -----------------------------------------
-#define GPIO_PORT_W192_PWORD_Pos                              0                                                         /*!< GPIO_PORT W192: PWORD Position      */
-#define GPIO_PORT_W192_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W192_PWORD_Pos)                /*!< GPIO_PORT W192: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W193  -----------------------------------------
-#define GPIO_PORT_W193_PWORD_Pos                              0                                                         /*!< GPIO_PORT W193: PWORD Position      */
-#define GPIO_PORT_W193_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W193_PWORD_Pos)                /*!< GPIO_PORT W193: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W194  -----------------------------------------
-#define GPIO_PORT_W194_PWORD_Pos                              0                                                         /*!< GPIO_PORT W194: PWORD Position      */
-#define GPIO_PORT_W194_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W194_PWORD_Pos)                /*!< GPIO_PORT W194: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W195  -----------------------------------------
-#define GPIO_PORT_W195_PWORD_Pos                              0                                                         /*!< GPIO_PORT W195: PWORD Position      */
-#define GPIO_PORT_W195_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W195_PWORD_Pos)                /*!< GPIO_PORT W195: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W196  -----------------------------------------
-#define GPIO_PORT_W196_PWORD_Pos                              0                                                         /*!< GPIO_PORT W196: PWORD Position      */
-#define GPIO_PORT_W196_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W196_PWORD_Pos)                /*!< GPIO_PORT W196: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W197  -----------------------------------------
-#define GPIO_PORT_W197_PWORD_Pos                              0                                                         /*!< GPIO_PORT W197: PWORD Position      */
-#define GPIO_PORT_W197_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W197_PWORD_Pos)                /*!< GPIO_PORT W197: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W198  -----------------------------------------
-#define GPIO_PORT_W198_PWORD_Pos                              0                                                         /*!< GPIO_PORT W198: PWORD Position      */
-#define GPIO_PORT_W198_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W198_PWORD_Pos)                /*!< GPIO_PORT W198: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W199  -----------------------------------------
-#define GPIO_PORT_W199_PWORD_Pos                              0                                                         /*!< GPIO_PORT W199: PWORD Position      */
-#define GPIO_PORT_W199_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W199_PWORD_Pos)                /*!< GPIO_PORT W199: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W200  -----------------------------------------
-#define GPIO_PORT_W200_PWORD_Pos                              0                                                         /*!< GPIO_PORT W200: PWORD Position      */
-#define GPIO_PORT_W200_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W200_PWORD_Pos)                /*!< GPIO_PORT W200: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W201  -----------------------------------------
-#define GPIO_PORT_W201_PWORD_Pos                              0                                                         /*!< GPIO_PORT W201: PWORD Position      */
-#define GPIO_PORT_W201_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W201_PWORD_Pos)                /*!< GPIO_PORT W201: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W202  -----------------------------------------
-#define GPIO_PORT_W202_PWORD_Pos                              0                                                         /*!< GPIO_PORT W202: PWORD Position      */
-#define GPIO_PORT_W202_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W202_PWORD_Pos)                /*!< GPIO_PORT W202: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W203  -----------------------------------------
-#define GPIO_PORT_W203_PWORD_Pos                              0                                                         /*!< GPIO_PORT W203: PWORD Position      */
-#define GPIO_PORT_W203_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W203_PWORD_Pos)                /*!< GPIO_PORT W203: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W204  -----------------------------------------
-#define GPIO_PORT_W204_PWORD_Pos                              0                                                         /*!< GPIO_PORT W204: PWORD Position      */
-#define GPIO_PORT_W204_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W204_PWORD_Pos)                /*!< GPIO_PORT W204: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W205  -----------------------------------------
-#define GPIO_PORT_W205_PWORD_Pos                              0                                                         /*!< GPIO_PORT W205: PWORD Position      */
-#define GPIO_PORT_W205_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W205_PWORD_Pos)                /*!< GPIO_PORT W205: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W206  -----------------------------------------
-#define GPIO_PORT_W206_PWORD_Pos                              0                                                         /*!< GPIO_PORT W206: PWORD Position      */
-#define GPIO_PORT_W206_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W206_PWORD_Pos)                /*!< GPIO_PORT W206: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W207  -----------------------------------------
-#define GPIO_PORT_W207_PWORD_Pos                              0                                                         /*!< GPIO_PORT W207: PWORD Position      */
-#define GPIO_PORT_W207_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W207_PWORD_Pos)                /*!< GPIO_PORT W207: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W208  -----------------------------------------
-#define GPIO_PORT_W208_PWORD_Pos                              0                                                         /*!< GPIO_PORT W208: PWORD Position      */
-#define GPIO_PORT_W208_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W208_PWORD_Pos)                /*!< GPIO_PORT W208: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W209  -----------------------------------------
-#define GPIO_PORT_W209_PWORD_Pos                              0                                                         /*!< GPIO_PORT W209: PWORD Position      */
-#define GPIO_PORT_W209_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W209_PWORD_Pos)                /*!< GPIO_PORT W209: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W210  -----------------------------------------
-#define GPIO_PORT_W210_PWORD_Pos                              0                                                         /*!< GPIO_PORT W210: PWORD Position      */
-#define GPIO_PORT_W210_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W210_PWORD_Pos)                /*!< GPIO_PORT W210: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W211  -----------------------------------------
-#define GPIO_PORT_W211_PWORD_Pos                              0                                                         /*!< GPIO_PORT W211: PWORD Position      */
-#define GPIO_PORT_W211_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W211_PWORD_Pos)                /*!< GPIO_PORT W211: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W212  -----------------------------------------
-#define GPIO_PORT_W212_PWORD_Pos                              0                                                         /*!< GPIO_PORT W212: PWORD Position      */
-#define GPIO_PORT_W212_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W212_PWORD_Pos)                /*!< GPIO_PORT W212: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W213  -----------------------------------------
-#define GPIO_PORT_W213_PWORD_Pos                              0                                                         /*!< GPIO_PORT W213: PWORD Position      */
-#define GPIO_PORT_W213_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W213_PWORD_Pos)                /*!< GPIO_PORT W213: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W214  -----------------------------------------
-#define GPIO_PORT_W214_PWORD_Pos                              0                                                         /*!< GPIO_PORT W214: PWORD Position      */
-#define GPIO_PORT_W214_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W214_PWORD_Pos)                /*!< GPIO_PORT W214: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W215  -----------------------------------------
-#define GPIO_PORT_W215_PWORD_Pos                              0                                                         /*!< GPIO_PORT W215: PWORD Position      */
-#define GPIO_PORT_W215_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W215_PWORD_Pos)                /*!< GPIO_PORT W215: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W216  -----------------------------------------
-#define GPIO_PORT_W216_PWORD_Pos                              0                                                         /*!< GPIO_PORT W216: PWORD Position      */
-#define GPIO_PORT_W216_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W216_PWORD_Pos)                /*!< GPIO_PORT W216: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W217  -----------------------------------------
-#define GPIO_PORT_W217_PWORD_Pos                              0                                                         /*!< GPIO_PORT W217: PWORD Position      */
-#define GPIO_PORT_W217_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W217_PWORD_Pos)                /*!< GPIO_PORT W217: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W218  -----------------------------------------
-#define GPIO_PORT_W218_PWORD_Pos                              0                                                         /*!< GPIO_PORT W218: PWORD Position      */
-#define GPIO_PORT_W218_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W218_PWORD_Pos)                /*!< GPIO_PORT W218: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W219  -----------------------------------------
-#define GPIO_PORT_W219_PWORD_Pos                              0                                                         /*!< GPIO_PORT W219: PWORD Position      */
-#define GPIO_PORT_W219_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W219_PWORD_Pos)                /*!< GPIO_PORT W219: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W220  -----------------------------------------
-#define GPIO_PORT_W220_PWORD_Pos                              0                                                         /*!< GPIO_PORT W220: PWORD Position      */
-#define GPIO_PORT_W220_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W220_PWORD_Pos)                /*!< GPIO_PORT W220: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W221  -----------------------------------------
-#define GPIO_PORT_W221_PWORD_Pos                              0                                                         /*!< GPIO_PORT W221: PWORD Position      */
-#define GPIO_PORT_W221_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W221_PWORD_Pos)                /*!< GPIO_PORT W221: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W222  -----------------------------------------
-#define GPIO_PORT_W222_PWORD_Pos                              0                                                         /*!< GPIO_PORT W222: PWORD Position      */
-#define GPIO_PORT_W222_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W222_PWORD_Pos)                /*!< GPIO_PORT W222: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W223  -----------------------------------------
-#define GPIO_PORT_W223_PWORD_Pos                              0                                                         /*!< GPIO_PORT W223: PWORD Position      */
-#define GPIO_PORT_W223_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W223_PWORD_Pos)                /*!< GPIO_PORT W223: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W224  -----------------------------------------
-#define GPIO_PORT_W224_PWORD_Pos                              0                                                         /*!< GPIO_PORT W224: PWORD Position      */
-#define GPIO_PORT_W224_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W224_PWORD_Pos)                /*!< GPIO_PORT W224: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W225  -----------------------------------------
-#define GPIO_PORT_W225_PWORD_Pos                              0                                                         /*!< GPIO_PORT W225: PWORD Position      */
-#define GPIO_PORT_W225_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W225_PWORD_Pos)                /*!< GPIO_PORT W225: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W226  -----------------------------------------
-#define GPIO_PORT_W226_PWORD_Pos                              0                                                         /*!< GPIO_PORT W226: PWORD Position      */
-#define GPIO_PORT_W226_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W226_PWORD_Pos)                /*!< GPIO_PORT W226: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W227  -----------------------------------------
-#define GPIO_PORT_W227_PWORD_Pos                              0                                                         /*!< GPIO_PORT W227: PWORD Position      */
-#define GPIO_PORT_W227_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W227_PWORD_Pos)                /*!< GPIO_PORT W227: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W228  -----------------------------------------
-#define GPIO_PORT_W228_PWORD_Pos                              0                                                         /*!< GPIO_PORT W228: PWORD Position      */
-#define GPIO_PORT_W228_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W228_PWORD_Pos)                /*!< GPIO_PORT W228: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W229  -----------------------------------------
-#define GPIO_PORT_W229_PWORD_Pos                              0                                                         /*!< GPIO_PORT W229: PWORD Position      */
-#define GPIO_PORT_W229_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W229_PWORD_Pos)                /*!< GPIO_PORT W229: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W230  -----------------------------------------
-#define GPIO_PORT_W230_PWORD_Pos                              0                                                         /*!< GPIO_PORT W230: PWORD Position      */
-#define GPIO_PORT_W230_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W230_PWORD_Pos)                /*!< GPIO_PORT W230: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W231  -----------------------------------------
-#define GPIO_PORT_W231_PWORD_Pos                              0                                                         /*!< GPIO_PORT W231: PWORD Position      */
-#define GPIO_PORT_W231_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W231_PWORD_Pos)                /*!< GPIO_PORT W231: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W232  -----------------------------------------
-#define GPIO_PORT_W232_PWORD_Pos                              0                                                         /*!< GPIO_PORT W232: PWORD Position      */
-#define GPIO_PORT_W232_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W232_PWORD_Pos)                /*!< GPIO_PORT W232: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W233  -----------------------------------------
-#define GPIO_PORT_W233_PWORD_Pos                              0                                                         /*!< GPIO_PORT W233: PWORD Position      */
-#define GPIO_PORT_W233_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W233_PWORD_Pos)                /*!< GPIO_PORT W233: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W234  -----------------------------------------
-#define GPIO_PORT_W234_PWORD_Pos                              0                                                         /*!< GPIO_PORT W234: PWORD Position      */
-#define GPIO_PORT_W234_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W234_PWORD_Pos)                /*!< GPIO_PORT W234: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W235  -----------------------------------------
-#define GPIO_PORT_W235_PWORD_Pos                              0                                                         /*!< GPIO_PORT W235: PWORD Position      */
-#define GPIO_PORT_W235_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W235_PWORD_Pos)                /*!< GPIO_PORT W235: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W236  -----------------------------------------
-#define GPIO_PORT_W236_PWORD_Pos                              0                                                         /*!< GPIO_PORT W236: PWORD Position      */
-#define GPIO_PORT_W236_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W236_PWORD_Pos)                /*!< GPIO_PORT W236: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W237  -----------------------------------------
-#define GPIO_PORT_W237_PWORD_Pos                              0                                                         /*!< GPIO_PORT W237: PWORD Position      */
-#define GPIO_PORT_W237_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W237_PWORD_Pos)                /*!< GPIO_PORT W237: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W238  -----------------------------------------
-#define GPIO_PORT_W238_PWORD_Pos                              0                                                         /*!< GPIO_PORT W238: PWORD Position      */
-#define GPIO_PORT_W238_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W238_PWORD_Pos)                /*!< GPIO_PORT W238: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W239  -----------------------------------------
-#define GPIO_PORT_W239_PWORD_Pos                              0                                                         /*!< GPIO_PORT W239: PWORD Position      */
-#define GPIO_PORT_W239_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W239_PWORD_Pos)                /*!< GPIO_PORT W239: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W240  -----------------------------------------
-#define GPIO_PORT_W240_PWORD_Pos                              0                                                         /*!< GPIO_PORT W240: PWORD Position      */
-#define GPIO_PORT_W240_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W240_PWORD_Pos)                /*!< GPIO_PORT W240: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W241  -----------------------------------------
-#define GPIO_PORT_W241_PWORD_Pos                              0                                                         /*!< GPIO_PORT W241: PWORD Position      */
-#define GPIO_PORT_W241_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W241_PWORD_Pos)                /*!< GPIO_PORT W241: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W242  -----------------------------------------
-#define GPIO_PORT_W242_PWORD_Pos                              0                                                         /*!< GPIO_PORT W242: PWORD Position      */
-#define GPIO_PORT_W242_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W242_PWORD_Pos)                /*!< GPIO_PORT W242: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W243  -----------------------------------------
-#define GPIO_PORT_W243_PWORD_Pos                              0                                                         /*!< GPIO_PORT W243: PWORD Position      */
-#define GPIO_PORT_W243_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W243_PWORD_Pos)                /*!< GPIO_PORT W243: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W244  -----------------------------------------
-#define GPIO_PORT_W244_PWORD_Pos                              0                                                         /*!< GPIO_PORT W244: PWORD Position      */
-#define GPIO_PORT_W244_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W244_PWORD_Pos)                /*!< GPIO_PORT W244: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W245  -----------------------------------------
-#define GPIO_PORT_W245_PWORD_Pos                              0                                                         /*!< GPIO_PORT W245: PWORD Position      */
-#define GPIO_PORT_W245_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W245_PWORD_Pos)                /*!< GPIO_PORT W245: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W246  -----------------------------------------
-#define GPIO_PORT_W246_PWORD_Pos                              0                                                         /*!< GPIO_PORT W246: PWORD Position      */
-#define GPIO_PORT_W246_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W246_PWORD_Pos)                /*!< GPIO_PORT W246: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W247  -----------------------------------------
-#define GPIO_PORT_W247_PWORD_Pos                              0                                                         /*!< GPIO_PORT W247: PWORD Position      */
-#define GPIO_PORT_W247_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W247_PWORD_Pos)                /*!< GPIO_PORT W247: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W248  -----------------------------------------
-#define GPIO_PORT_W248_PWORD_Pos                              0                                                         /*!< GPIO_PORT W248: PWORD Position      */
-#define GPIO_PORT_W248_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W248_PWORD_Pos)                /*!< GPIO_PORT W248: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W249  -----------------------------------------
-#define GPIO_PORT_W249_PWORD_Pos                              0                                                         /*!< GPIO_PORT W249: PWORD Position      */
-#define GPIO_PORT_W249_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W249_PWORD_Pos)                /*!< GPIO_PORT W249: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W250  -----------------------------------------
-#define GPIO_PORT_W250_PWORD_Pos                              0                                                         /*!< GPIO_PORT W250: PWORD Position      */
-#define GPIO_PORT_W250_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W250_PWORD_Pos)                /*!< GPIO_PORT W250: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W251  -----------------------------------------
-#define GPIO_PORT_W251_PWORD_Pos                              0                                                         /*!< GPIO_PORT W251: PWORD Position      */
-#define GPIO_PORT_W251_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W251_PWORD_Pos)                /*!< GPIO_PORT W251: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W252  -----------------------------------------
-#define GPIO_PORT_W252_PWORD_Pos                              0                                                         /*!< GPIO_PORT W252: PWORD Position      */
-#define GPIO_PORT_W252_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W252_PWORD_Pos)                /*!< GPIO_PORT W252: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W253  -----------------------------------------
-#define GPIO_PORT_W253_PWORD_Pos                              0                                                         /*!< GPIO_PORT W253: PWORD Position      */
-#define GPIO_PORT_W253_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W253_PWORD_Pos)                /*!< GPIO_PORT W253: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W254  -----------------------------------------
-#define GPIO_PORT_W254_PWORD_Pos                              0                                                         /*!< GPIO_PORT W254: PWORD Position      */
-#define GPIO_PORT_W254_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W254_PWORD_Pos)                /*!< GPIO_PORT W254: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_W255  -----------------------------------------
-#define GPIO_PORT_W255_PWORD_Pos                              0                                                         /*!< GPIO_PORT W255: PWORD Position      */
-#define GPIO_PORT_W255_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W255_PWORD_Pos)                /*!< GPIO_PORT W255: PWORD Mask          */
-
-// -------------------------------------  GPIO_PORT_DIR0  -----------------------------------------
-#define GPIO_PORT_DIR0_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR0: DIRP0 Position      */
-#define GPIO_PORT_DIR0_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP0_Pos)                      /*!< GPIO_PORT DIR0: DIRP0 Mask          */
-#define GPIO_PORT_DIR0_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR0: DIRP1 Position      */
-#define GPIO_PORT_DIR0_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP1_Pos)                      /*!< GPIO_PORT DIR0: DIRP1 Mask          */
-#define GPIO_PORT_DIR0_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR0: DIRP2 Position      */
-#define GPIO_PORT_DIR0_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP2_Pos)                      /*!< GPIO_PORT DIR0: DIRP2 Mask          */
-#define GPIO_PORT_DIR0_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR0: DIRP3 Position      */
-#define GPIO_PORT_DIR0_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP3_Pos)                      /*!< GPIO_PORT DIR0: DIRP3 Mask          */
-#define GPIO_PORT_DIR0_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR0: DIRP4 Position      */
-#define GPIO_PORT_DIR0_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP4_Pos)                      /*!< GPIO_PORT DIR0: DIRP4 Mask          */
-#define GPIO_PORT_DIR0_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR0: DIRP5 Position      */
-#define GPIO_PORT_DIR0_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP5_Pos)                      /*!< GPIO_PORT DIR0: DIRP5 Mask          */
-#define GPIO_PORT_DIR0_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR0: DIRP6 Position      */
-#define GPIO_PORT_DIR0_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP6_Pos)                      /*!< GPIO_PORT DIR0: DIRP6 Mask          */
-#define GPIO_PORT_DIR0_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR0: DIRP7 Position      */
-#define GPIO_PORT_DIR0_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP7_Pos)                      /*!< GPIO_PORT DIR0: DIRP7 Mask          */
-#define GPIO_PORT_DIR0_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR0: DIRP8 Position      */
-#define GPIO_PORT_DIR0_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP8_Pos)                      /*!< GPIO_PORT DIR0: DIRP8 Mask          */
-#define GPIO_PORT_DIR0_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR0: DIRP9 Position      */
-#define GPIO_PORT_DIR0_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP9_Pos)                      /*!< GPIO_PORT DIR0: DIRP9 Mask          */
-#define GPIO_PORT_DIR0_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR0: DIRP10 Position     */
-#define GPIO_PORT_DIR0_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP10_Pos)                     /*!< GPIO_PORT DIR0: DIRP10 Mask         */
-#define GPIO_PORT_DIR0_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR0: DIRP11 Position     */
-#define GPIO_PORT_DIR0_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP11_Pos)                     /*!< GPIO_PORT DIR0: DIRP11 Mask         */
-#define GPIO_PORT_DIR0_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR0: DIRP12 Position     */
-#define GPIO_PORT_DIR0_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP12_Pos)                     /*!< GPIO_PORT DIR0: DIRP12 Mask         */
-#define GPIO_PORT_DIR0_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR0: DIRP13 Position     */
-#define GPIO_PORT_DIR0_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP13_Pos)                     /*!< GPIO_PORT DIR0: DIRP13 Mask         */
-#define GPIO_PORT_DIR0_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR0: DIRP14 Position     */
-#define GPIO_PORT_DIR0_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP14_Pos)                     /*!< GPIO_PORT DIR0: DIRP14 Mask         */
-#define GPIO_PORT_DIR0_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR0: DIRP15 Position     */
-#define GPIO_PORT_DIR0_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP15_Pos)                     /*!< GPIO_PORT DIR0: DIRP15 Mask         */
-#define GPIO_PORT_DIR0_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR0: DIRP16 Position     */
-#define GPIO_PORT_DIR0_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP16_Pos)                     /*!< GPIO_PORT DIR0: DIRP16 Mask         */
-#define GPIO_PORT_DIR0_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR0: DIRP17 Position     */
-#define GPIO_PORT_DIR0_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP17_Pos)                     /*!< GPIO_PORT DIR0: DIRP17 Mask         */
-#define GPIO_PORT_DIR0_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR0: DIRP18 Position     */
-#define GPIO_PORT_DIR0_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP18_Pos)                     /*!< GPIO_PORT DIR0: DIRP18 Mask         */
-#define GPIO_PORT_DIR0_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR0: DIRP19 Position     */
-#define GPIO_PORT_DIR0_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP19_Pos)                     /*!< GPIO_PORT DIR0: DIRP19 Mask         */
-#define GPIO_PORT_DIR0_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR0: DIRP20 Position     */
-#define GPIO_PORT_DIR0_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP20_Pos)                     /*!< GPIO_PORT DIR0: DIRP20 Mask         */
-#define GPIO_PORT_DIR0_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR0: DIRP21 Position     */
-#define GPIO_PORT_DIR0_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP21_Pos)                     /*!< GPIO_PORT DIR0: DIRP21 Mask         */
-#define GPIO_PORT_DIR0_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR0: DIRP22 Position     */
-#define GPIO_PORT_DIR0_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP22_Pos)                     /*!< GPIO_PORT DIR0: DIRP22 Mask         */
-#define GPIO_PORT_DIR0_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR0: DIRP23 Position     */
-#define GPIO_PORT_DIR0_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP23_Pos)                     /*!< GPIO_PORT DIR0: DIRP23 Mask         */
-#define GPIO_PORT_DIR0_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR0: DIRP24 Position     */
-#define GPIO_PORT_DIR0_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP24_Pos)                     /*!< GPIO_PORT DIR0: DIRP24 Mask         */
-#define GPIO_PORT_DIR0_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR0: DIRP25 Position     */
-#define GPIO_PORT_DIR0_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP25_Pos)                     /*!< GPIO_PORT DIR0: DIRP25 Mask         */
-#define GPIO_PORT_DIR0_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR0: DIRP26 Position     */
-#define GPIO_PORT_DIR0_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP26_Pos)                     /*!< GPIO_PORT DIR0: DIRP26 Mask         */
-#define GPIO_PORT_DIR0_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR0: DIRP27 Position     */
-#define GPIO_PORT_DIR0_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP27_Pos)                     /*!< GPIO_PORT DIR0: DIRP27 Mask         */
-#define GPIO_PORT_DIR0_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR0: DIRP28 Position     */
-#define GPIO_PORT_DIR0_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP28_Pos)                     /*!< GPIO_PORT DIR0: DIRP28 Mask         */
-#define GPIO_PORT_DIR0_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR0: DIRP29 Position     */
-#define GPIO_PORT_DIR0_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP29_Pos)                     /*!< GPIO_PORT DIR0: DIRP29 Mask         */
-#define GPIO_PORT_DIR0_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR0: DIRP30 Position     */
-#define GPIO_PORT_DIR0_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP30_Pos)                     /*!< GPIO_PORT DIR0: DIRP30 Mask         */
-#define GPIO_PORT_DIR0_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR0: DIRP31 Position     */
-#define GPIO_PORT_DIR0_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP31_Pos)                     /*!< GPIO_PORT DIR0: DIRP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_DIR1  -----------------------------------------
-#define GPIO_PORT_DIR1_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR1: DIRP0 Position      */
-#define GPIO_PORT_DIR1_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP0_Pos)                      /*!< GPIO_PORT DIR1: DIRP0 Mask          */
-#define GPIO_PORT_DIR1_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR1: DIRP1 Position      */
-#define GPIO_PORT_DIR1_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP1_Pos)                      /*!< GPIO_PORT DIR1: DIRP1 Mask          */
-#define GPIO_PORT_DIR1_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR1: DIRP2 Position      */
-#define GPIO_PORT_DIR1_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP2_Pos)                      /*!< GPIO_PORT DIR1: DIRP2 Mask          */
-#define GPIO_PORT_DIR1_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR1: DIRP3 Position      */
-#define GPIO_PORT_DIR1_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP3_Pos)                      /*!< GPIO_PORT DIR1: DIRP3 Mask          */
-#define GPIO_PORT_DIR1_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR1: DIRP4 Position      */
-#define GPIO_PORT_DIR1_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP4_Pos)                      /*!< GPIO_PORT DIR1: DIRP4 Mask          */
-#define GPIO_PORT_DIR1_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR1: DIRP5 Position      */
-#define GPIO_PORT_DIR1_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP5_Pos)                      /*!< GPIO_PORT DIR1: DIRP5 Mask          */
-#define GPIO_PORT_DIR1_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR1: DIRP6 Position      */
-#define GPIO_PORT_DIR1_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP6_Pos)                      /*!< GPIO_PORT DIR1: DIRP6 Mask          */
-#define GPIO_PORT_DIR1_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR1: DIRP7 Position      */
-#define GPIO_PORT_DIR1_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP7_Pos)                      /*!< GPIO_PORT DIR1: DIRP7 Mask          */
-#define GPIO_PORT_DIR1_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR1: DIRP8 Position      */
-#define GPIO_PORT_DIR1_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP8_Pos)                      /*!< GPIO_PORT DIR1: DIRP8 Mask          */
-#define GPIO_PORT_DIR1_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR1: DIRP9 Position      */
-#define GPIO_PORT_DIR1_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP9_Pos)                      /*!< GPIO_PORT DIR1: DIRP9 Mask          */
-#define GPIO_PORT_DIR1_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR1: DIRP10 Position     */
-#define GPIO_PORT_DIR1_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP10_Pos)                     /*!< GPIO_PORT DIR1: DIRP10 Mask         */
-#define GPIO_PORT_DIR1_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR1: DIRP11 Position     */
-#define GPIO_PORT_DIR1_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP11_Pos)                     /*!< GPIO_PORT DIR1: DIRP11 Mask         */
-#define GPIO_PORT_DIR1_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR1: DIRP12 Position     */
-#define GPIO_PORT_DIR1_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP12_Pos)                     /*!< GPIO_PORT DIR1: DIRP12 Mask         */
-#define GPIO_PORT_DIR1_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR1: DIRP13 Position     */
-#define GPIO_PORT_DIR1_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP13_Pos)                     /*!< GPIO_PORT DIR1: DIRP13 Mask         */
-#define GPIO_PORT_DIR1_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR1: DIRP14 Position     */
-#define GPIO_PORT_DIR1_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP14_Pos)                     /*!< GPIO_PORT DIR1: DIRP14 Mask         */
-#define GPIO_PORT_DIR1_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR1: DIRP15 Position     */
-#define GPIO_PORT_DIR1_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP15_Pos)                     /*!< GPIO_PORT DIR1: DIRP15 Mask         */
-#define GPIO_PORT_DIR1_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR1: DIRP16 Position     */
-#define GPIO_PORT_DIR1_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP16_Pos)                     /*!< GPIO_PORT DIR1: DIRP16 Mask         */
-#define GPIO_PORT_DIR1_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR1: DIRP17 Position     */
-#define GPIO_PORT_DIR1_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP17_Pos)                     /*!< GPIO_PORT DIR1: DIRP17 Mask         */
-#define GPIO_PORT_DIR1_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR1: DIRP18 Position     */
-#define GPIO_PORT_DIR1_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP18_Pos)                     /*!< GPIO_PORT DIR1: DIRP18 Mask         */
-#define GPIO_PORT_DIR1_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR1: DIRP19 Position     */
-#define GPIO_PORT_DIR1_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP19_Pos)                     /*!< GPIO_PORT DIR1: DIRP19 Mask         */
-#define GPIO_PORT_DIR1_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR1: DIRP20 Position     */
-#define GPIO_PORT_DIR1_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP20_Pos)                     /*!< GPIO_PORT DIR1: DIRP20 Mask         */
-#define GPIO_PORT_DIR1_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR1: DIRP21 Position     */
-#define GPIO_PORT_DIR1_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP21_Pos)                     /*!< GPIO_PORT DIR1: DIRP21 Mask         */
-#define GPIO_PORT_DIR1_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR1: DIRP22 Position     */
-#define GPIO_PORT_DIR1_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP22_Pos)                     /*!< GPIO_PORT DIR1: DIRP22 Mask         */
-#define GPIO_PORT_DIR1_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR1: DIRP23 Position     */
-#define GPIO_PORT_DIR1_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP23_Pos)                     /*!< GPIO_PORT DIR1: DIRP23 Mask         */
-#define GPIO_PORT_DIR1_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR1: DIRP24 Position     */
-#define GPIO_PORT_DIR1_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP24_Pos)                     /*!< GPIO_PORT DIR1: DIRP24 Mask         */
-#define GPIO_PORT_DIR1_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR1: DIRP25 Position     */
-#define GPIO_PORT_DIR1_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP25_Pos)                     /*!< GPIO_PORT DIR1: DIRP25 Mask         */
-#define GPIO_PORT_DIR1_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR1: DIRP26 Position     */
-#define GPIO_PORT_DIR1_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP26_Pos)                     /*!< GPIO_PORT DIR1: DIRP26 Mask         */
-#define GPIO_PORT_DIR1_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR1: DIRP27 Position     */
-#define GPIO_PORT_DIR1_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP27_Pos)                     /*!< GPIO_PORT DIR1: DIRP27 Mask         */
-#define GPIO_PORT_DIR1_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR1: DIRP28 Position     */
-#define GPIO_PORT_DIR1_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP28_Pos)                     /*!< GPIO_PORT DIR1: DIRP28 Mask         */
-#define GPIO_PORT_DIR1_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR1: DIRP29 Position     */
-#define GPIO_PORT_DIR1_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP29_Pos)                     /*!< GPIO_PORT DIR1: DIRP29 Mask         */
-#define GPIO_PORT_DIR1_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR1: DIRP30 Position     */
-#define GPIO_PORT_DIR1_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP30_Pos)                     /*!< GPIO_PORT DIR1: DIRP30 Mask         */
-#define GPIO_PORT_DIR1_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR1: DIRP31 Position     */
-#define GPIO_PORT_DIR1_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP31_Pos)                     /*!< GPIO_PORT DIR1: DIRP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_DIR2  -----------------------------------------
-#define GPIO_PORT_DIR2_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR2: DIRP0 Position      */
-#define GPIO_PORT_DIR2_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP0_Pos)                      /*!< GPIO_PORT DIR2: DIRP0 Mask          */
-#define GPIO_PORT_DIR2_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR2: DIRP1 Position      */
-#define GPIO_PORT_DIR2_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP1_Pos)                      /*!< GPIO_PORT DIR2: DIRP1 Mask          */
-#define GPIO_PORT_DIR2_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR2: DIRP2 Position      */
-#define GPIO_PORT_DIR2_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP2_Pos)                      /*!< GPIO_PORT DIR2: DIRP2 Mask          */
-#define GPIO_PORT_DIR2_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR2: DIRP3 Position      */
-#define GPIO_PORT_DIR2_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP3_Pos)                      /*!< GPIO_PORT DIR2: DIRP3 Mask          */
-#define GPIO_PORT_DIR2_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR2: DIRP4 Position      */
-#define GPIO_PORT_DIR2_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP4_Pos)                      /*!< GPIO_PORT DIR2: DIRP4 Mask          */
-#define GPIO_PORT_DIR2_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR2: DIRP5 Position      */
-#define GPIO_PORT_DIR2_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP5_Pos)                      /*!< GPIO_PORT DIR2: DIRP5 Mask          */
-#define GPIO_PORT_DIR2_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR2: DIRP6 Position      */
-#define GPIO_PORT_DIR2_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP6_Pos)                      /*!< GPIO_PORT DIR2: DIRP6 Mask          */
-#define GPIO_PORT_DIR2_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR2: DIRP7 Position      */
-#define GPIO_PORT_DIR2_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP7_Pos)                      /*!< GPIO_PORT DIR2: DIRP7 Mask          */
-#define GPIO_PORT_DIR2_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR2: DIRP8 Position      */
-#define GPIO_PORT_DIR2_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP8_Pos)                      /*!< GPIO_PORT DIR2: DIRP8 Mask          */
-#define GPIO_PORT_DIR2_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR2: DIRP9 Position      */
-#define GPIO_PORT_DIR2_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP9_Pos)                      /*!< GPIO_PORT DIR2: DIRP9 Mask          */
-#define GPIO_PORT_DIR2_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR2: DIRP10 Position     */
-#define GPIO_PORT_DIR2_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP10_Pos)                     /*!< GPIO_PORT DIR2: DIRP10 Mask         */
-#define GPIO_PORT_DIR2_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR2: DIRP11 Position     */
-#define GPIO_PORT_DIR2_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP11_Pos)                     /*!< GPIO_PORT DIR2: DIRP11 Mask         */
-#define GPIO_PORT_DIR2_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR2: DIRP12 Position     */
-#define GPIO_PORT_DIR2_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP12_Pos)                     /*!< GPIO_PORT DIR2: DIRP12 Mask         */
-#define GPIO_PORT_DIR2_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR2: DIRP13 Position     */
-#define GPIO_PORT_DIR2_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP13_Pos)                     /*!< GPIO_PORT DIR2: DIRP13 Mask         */
-#define GPIO_PORT_DIR2_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR2: DIRP14 Position     */
-#define GPIO_PORT_DIR2_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP14_Pos)                     /*!< GPIO_PORT DIR2: DIRP14 Mask         */
-#define GPIO_PORT_DIR2_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR2: DIRP15 Position     */
-#define GPIO_PORT_DIR2_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP15_Pos)                     /*!< GPIO_PORT DIR2: DIRP15 Mask         */
-#define GPIO_PORT_DIR2_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR2: DIRP16 Position     */
-#define GPIO_PORT_DIR2_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP16_Pos)                     /*!< GPIO_PORT DIR2: DIRP16 Mask         */
-#define GPIO_PORT_DIR2_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR2: DIRP17 Position     */
-#define GPIO_PORT_DIR2_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP17_Pos)                     /*!< GPIO_PORT DIR2: DIRP17 Mask         */
-#define GPIO_PORT_DIR2_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR2: DIRP18 Position     */
-#define GPIO_PORT_DIR2_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP18_Pos)                     /*!< GPIO_PORT DIR2: DIRP18 Mask         */
-#define GPIO_PORT_DIR2_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR2: DIRP19 Position     */
-#define GPIO_PORT_DIR2_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP19_Pos)                     /*!< GPIO_PORT DIR2: DIRP19 Mask         */
-#define GPIO_PORT_DIR2_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR2: DIRP20 Position     */
-#define GPIO_PORT_DIR2_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP20_Pos)                     /*!< GPIO_PORT DIR2: DIRP20 Mask         */
-#define GPIO_PORT_DIR2_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR2: DIRP21 Position     */
-#define GPIO_PORT_DIR2_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP21_Pos)                     /*!< GPIO_PORT DIR2: DIRP21 Mask         */
-#define GPIO_PORT_DIR2_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR2: DIRP22 Position     */
-#define GPIO_PORT_DIR2_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP22_Pos)                     /*!< GPIO_PORT DIR2: DIRP22 Mask         */
-#define GPIO_PORT_DIR2_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR2: DIRP23 Position     */
-#define GPIO_PORT_DIR2_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP23_Pos)                     /*!< GPIO_PORT DIR2: DIRP23 Mask         */
-#define GPIO_PORT_DIR2_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR2: DIRP24 Position     */
-#define GPIO_PORT_DIR2_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP24_Pos)                     /*!< GPIO_PORT DIR2: DIRP24 Mask         */
-#define GPIO_PORT_DIR2_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR2: DIRP25 Position     */
-#define GPIO_PORT_DIR2_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP25_Pos)                     /*!< GPIO_PORT DIR2: DIRP25 Mask         */
-#define GPIO_PORT_DIR2_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR2: DIRP26 Position     */
-#define GPIO_PORT_DIR2_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP26_Pos)                     /*!< GPIO_PORT DIR2: DIRP26 Mask         */
-#define GPIO_PORT_DIR2_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR2: DIRP27 Position     */
-#define GPIO_PORT_DIR2_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP27_Pos)                     /*!< GPIO_PORT DIR2: DIRP27 Mask         */
-#define GPIO_PORT_DIR2_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR2: DIRP28 Position     */
-#define GPIO_PORT_DIR2_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP28_Pos)                     /*!< GPIO_PORT DIR2: DIRP28 Mask         */
-#define GPIO_PORT_DIR2_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR2: DIRP29 Position     */
-#define GPIO_PORT_DIR2_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP29_Pos)                     /*!< GPIO_PORT DIR2: DIRP29 Mask         */
-#define GPIO_PORT_DIR2_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR2: DIRP30 Position     */
-#define GPIO_PORT_DIR2_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP30_Pos)                     /*!< GPIO_PORT DIR2: DIRP30 Mask         */
-#define GPIO_PORT_DIR2_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR2: DIRP31 Position     */
-#define GPIO_PORT_DIR2_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP31_Pos)                     /*!< GPIO_PORT DIR2: DIRP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_DIR3  -----------------------------------------
-#define GPIO_PORT_DIR3_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR3: DIRP0 Position      */
-#define GPIO_PORT_DIR3_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP0_Pos)                      /*!< GPIO_PORT DIR3: DIRP0 Mask          */
-#define GPIO_PORT_DIR3_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR3: DIRP1 Position      */
-#define GPIO_PORT_DIR3_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP1_Pos)                      /*!< GPIO_PORT DIR3: DIRP1 Mask          */
-#define GPIO_PORT_DIR3_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR3: DIRP2 Position      */
-#define GPIO_PORT_DIR3_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP2_Pos)                      /*!< GPIO_PORT DIR3: DIRP2 Mask          */
-#define GPIO_PORT_DIR3_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR3: DIRP3 Position      */
-#define GPIO_PORT_DIR3_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP3_Pos)                      /*!< GPIO_PORT DIR3: DIRP3 Mask          */
-#define GPIO_PORT_DIR3_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR3: DIRP4 Position      */
-#define GPIO_PORT_DIR3_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP4_Pos)                      /*!< GPIO_PORT DIR3: DIRP4 Mask          */
-#define GPIO_PORT_DIR3_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR3: DIRP5 Position      */
-#define GPIO_PORT_DIR3_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP5_Pos)                      /*!< GPIO_PORT DIR3: DIRP5 Mask          */
-#define GPIO_PORT_DIR3_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR3: DIRP6 Position      */
-#define GPIO_PORT_DIR3_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP6_Pos)                      /*!< GPIO_PORT DIR3: DIRP6 Mask          */
-#define GPIO_PORT_DIR3_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR3: DIRP7 Position      */
-#define GPIO_PORT_DIR3_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP7_Pos)                      /*!< GPIO_PORT DIR3: DIRP7 Mask          */
-#define GPIO_PORT_DIR3_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR3: DIRP8 Position      */
-#define GPIO_PORT_DIR3_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP8_Pos)                      /*!< GPIO_PORT DIR3: DIRP8 Mask          */
-#define GPIO_PORT_DIR3_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR3: DIRP9 Position      */
-#define GPIO_PORT_DIR3_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP9_Pos)                      /*!< GPIO_PORT DIR3: DIRP9 Mask          */
-#define GPIO_PORT_DIR3_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR3: DIRP10 Position     */
-#define GPIO_PORT_DIR3_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP10_Pos)                     /*!< GPIO_PORT DIR3: DIRP10 Mask         */
-#define GPIO_PORT_DIR3_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR3: DIRP11 Position     */
-#define GPIO_PORT_DIR3_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP11_Pos)                     /*!< GPIO_PORT DIR3: DIRP11 Mask         */
-#define GPIO_PORT_DIR3_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR3: DIRP12 Position     */
-#define GPIO_PORT_DIR3_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP12_Pos)                     /*!< GPIO_PORT DIR3: DIRP12 Mask         */
-#define GPIO_PORT_DIR3_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR3: DIRP13 Position     */
-#define GPIO_PORT_DIR3_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP13_Pos)                     /*!< GPIO_PORT DIR3: DIRP13 Mask         */
-#define GPIO_PORT_DIR3_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR3: DIRP14 Position     */
-#define GPIO_PORT_DIR3_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP14_Pos)                     /*!< GPIO_PORT DIR3: DIRP14 Mask         */
-#define GPIO_PORT_DIR3_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR3: DIRP15 Position     */
-#define GPIO_PORT_DIR3_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP15_Pos)                     /*!< GPIO_PORT DIR3: DIRP15 Mask         */
-#define GPIO_PORT_DIR3_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR3: DIRP16 Position     */
-#define GPIO_PORT_DIR3_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP16_Pos)                     /*!< GPIO_PORT DIR3: DIRP16 Mask         */
-#define GPIO_PORT_DIR3_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR3: DIRP17 Position     */
-#define GPIO_PORT_DIR3_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP17_Pos)                     /*!< GPIO_PORT DIR3: DIRP17 Mask         */
-#define GPIO_PORT_DIR3_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR3: DIRP18 Position     */
-#define GPIO_PORT_DIR3_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP18_Pos)                     /*!< GPIO_PORT DIR3: DIRP18 Mask         */
-#define GPIO_PORT_DIR3_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR3: DIRP19 Position     */
-#define GPIO_PORT_DIR3_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP19_Pos)                     /*!< GPIO_PORT DIR3: DIRP19 Mask         */
-#define GPIO_PORT_DIR3_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR3: DIRP20 Position     */
-#define GPIO_PORT_DIR3_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP20_Pos)                     /*!< GPIO_PORT DIR3: DIRP20 Mask         */
-#define GPIO_PORT_DIR3_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR3: DIRP21 Position     */
-#define GPIO_PORT_DIR3_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP21_Pos)                     /*!< GPIO_PORT DIR3: DIRP21 Mask         */
-#define GPIO_PORT_DIR3_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR3: DIRP22 Position     */
-#define GPIO_PORT_DIR3_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP22_Pos)                     /*!< GPIO_PORT DIR3: DIRP22 Mask         */
-#define GPIO_PORT_DIR3_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR3: DIRP23 Position     */
-#define GPIO_PORT_DIR3_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP23_Pos)                     /*!< GPIO_PORT DIR3: DIRP23 Mask         */
-#define GPIO_PORT_DIR3_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR3: DIRP24 Position     */
-#define GPIO_PORT_DIR3_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP24_Pos)                     /*!< GPIO_PORT DIR3: DIRP24 Mask         */
-#define GPIO_PORT_DIR3_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR3: DIRP25 Position     */
-#define GPIO_PORT_DIR3_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP25_Pos)                     /*!< GPIO_PORT DIR3: DIRP25 Mask         */
-#define GPIO_PORT_DIR3_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR3: DIRP26 Position     */
-#define GPIO_PORT_DIR3_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP26_Pos)                     /*!< GPIO_PORT DIR3: DIRP26 Mask         */
-#define GPIO_PORT_DIR3_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR3: DIRP27 Position     */
-#define GPIO_PORT_DIR3_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP27_Pos)                     /*!< GPIO_PORT DIR3: DIRP27 Mask         */
-#define GPIO_PORT_DIR3_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR3: DIRP28 Position     */
-#define GPIO_PORT_DIR3_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP28_Pos)                     /*!< GPIO_PORT DIR3: DIRP28 Mask         */
-#define GPIO_PORT_DIR3_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR3: DIRP29 Position     */
-#define GPIO_PORT_DIR3_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP29_Pos)                     /*!< GPIO_PORT DIR3: DIRP29 Mask         */
-#define GPIO_PORT_DIR3_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR3: DIRP30 Position     */
-#define GPIO_PORT_DIR3_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP30_Pos)                     /*!< GPIO_PORT DIR3: DIRP30 Mask         */
-#define GPIO_PORT_DIR3_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR3: DIRP31 Position     */
-#define GPIO_PORT_DIR3_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP31_Pos)                     /*!< GPIO_PORT DIR3: DIRP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_DIR4  -----------------------------------------
-#define GPIO_PORT_DIR4_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR4: DIRP0 Position      */
-#define GPIO_PORT_DIR4_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP0_Pos)                      /*!< GPIO_PORT DIR4: DIRP0 Mask          */
-#define GPIO_PORT_DIR4_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR4: DIRP1 Position      */
-#define GPIO_PORT_DIR4_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP1_Pos)                      /*!< GPIO_PORT DIR4: DIRP1 Mask          */
-#define GPIO_PORT_DIR4_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR4: DIRP2 Position      */
-#define GPIO_PORT_DIR4_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP2_Pos)                      /*!< GPIO_PORT DIR4: DIRP2 Mask          */
-#define GPIO_PORT_DIR4_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR4: DIRP3 Position      */
-#define GPIO_PORT_DIR4_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP3_Pos)                      /*!< GPIO_PORT DIR4: DIRP3 Mask          */
-#define GPIO_PORT_DIR4_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR4: DIRP4 Position      */
-#define GPIO_PORT_DIR4_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP4_Pos)                      /*!< GPIO_PORT DIR4: DIRP4 Mask          */
-#define GPIO_PORT_DIR4_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR4: DIRP5 Position      */
-#define GPIO_PORT_DIR4_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP5_Pos)                      /*!< GPIO_PORT DIR4: DIRP5 Mask          */
-#define GPIO_PORT_DIR4_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR4: DIRP6 Position      */
-#define GPIO_PORT_DIR4_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP6_Pos)                      /*!< GPIO_PORT DIR4: DIRP6 Mask          */
-#define GPIO_PORT_DIR4_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR4: DIRP7 Position      */
-#define GPIO_PORT_DIR4_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP7_Pos)                      /*!< GPIO_PORT DIR4: DIRP7 Mask          */
-#define GPIO_PORT_DIR4_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR4: DIRP8 Position      */
-#define GPIO_PORT_DIR4_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP8_Pos)                      /*!< GPIO_PORT DIR4: DIRP8 Mask          */
-#define GPIO_PORT_DIR4_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR4: DIRP9 Position      */
-#define GPIO_PORT_DIR4_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP9_Pos)                      /*!< GPIO_PORT DIR4: DIRP9 Mask          */
-#define GPIO_PORT_DIR4_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR4: DIRP10 Position     */
-#define GPIO_PORT_DIR4_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP10_Pos)                     /*!< GPIO_PORT DIR4: DIRP10 Mask         */
-#define GPIO_PORT_DIR4_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR4: DIRP11 Position     */
-#define GPIO_PORT_DIR4_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP11_Pos)                     /*!< GPIO_PORT DIR4: DIRP11 Mask         */
-#define GPIO_PORT_DIR4_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR4: DIRP12 Position     */
-#define GPIO_PORT_DIR4_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP12_Pos)                     /*!< GPIO_PORT DIR4: DIRP12 Mask         */
-#define GPIO_PORT_DIR4_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR4: DIRP13 Position     */
-#define GPIO_PORT_DIR4_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP13_Pos)                     /*!< GPIO_PORT DIR4: DIRP13 Mask         */
-#define GPIO_PORT_DIR4_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR4: DIRP14 Position     */
-#define GPIO_PORT_DIR4_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP14_Pos)                     /*!< GPIO_PORT DIR4: DIRP14 Mask         */
-#define GPIO_PORT_DIR4_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR4: DIRP15 Position     */
-#define GPIO_PORT_DIR4_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP15_Pos)                     /*!< GPIO_PORT DIR4: DIRP15 Mask         */
-#define GPIO_PORT_DIR4_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR4: DIRP16 Position     */
-#define GPIO_PORT_DIR4_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP16_Pos)                     /*!< GPIO_PORT DIR4: DIRP16 Mask         */
-#define GPIO_PORT_DIR4_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR4: DIRP17 Position     */
-#define GPIO_PORT_DIR4_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP17_Pos)                     /*!< GPIO_PORT DIR4: DIRP17 Mask         */
-#define GPIO_PORT_DIR4_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR4: DIRP18 Position     */
-#define GPIO_PORT_DIR4_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP18_Pos)                     /*!< GPIO_PORT DIR4: DIRP18 Mask         */
-#define GPIO_PORT_DIR4_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR4: DIRP19 Position     */
-#define GPIO_PORT_DIR4_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP19_Pos)                     /*!< GPIO_PORT DIR4: DIRP19 Mask         */
-#define GPIO_PORT_DIR4_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR4: DIRP20 Position     */
-#define GPIO_PORT_DIR4_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP20_Pos)                     /*!< GPIO_PORT DIR4: DIRP20 Mask         */
-#define GPIO_PORT_DIR4_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR4: DIRP21 Position     */
-#define GPIO_PORT_DIR4_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP21_Pos)                     /*!< GPIO_PORT DIR4: DIRP21 Mask         */
-#define GPIO_PORT_DIR4_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR4: DIRP22 Position     */
-#define GPIO_PORT_DIR4_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP22_Pos)                     /*!< GPIO_PORT DIR4: DIRP22 Mask         */
-#define GPIO_PORT_DIR4_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR4: DIRP23 Position     */
-#define GPIO_PORT_DIR4_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP23_Pos)                     /*!< GPIO_PORT DIR4: DIRP23 Mask         */
-#define GPIO_PORT_DIR4_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR4: DIRP24 Position     */
-#define GPIO_PORT_DIR4_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP24_Pos)                     /*!< GPIO_PORT DIR4: DIRP24 Mask         */
-#define GPIO_PORT_DIR4_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR4: DIRP25 Position     */
-#define GPIO_PORT_DIR4_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP25_Pos)                     /*!< GPIO_PORT DIR4: DIRP25 Mask         */
-#define GPIO_PORT_DIR4_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR4: DIRP26 Position     */
-#define GPIO_PORT_DIR4_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP26_Pos)                     /*!< GPIO_PORT DIR4: DIRP26 Mask         */
-#define GPIO_PORT_DIR4_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR4: DIRP27 Position     */
-#define GPIO_PORT_DIR4_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP27_Pos)                     /*!< GPIO_PORT DIR4: DIRP27 Mask         */
-#define GPIO_PORT_DIR4_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR4: DIRP28 Position     */
-#define GPIO_PORT_DIR4_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP28_Pos)                     /*!< GPIO_PORT DIR4: DIRP28 Mask         */
-#define GPIO_PORT_DIR4_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR4: DIRP29 Position     */
-#define GPIO_PORT_DIR4_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP29_Pos)                     /*!< GPIO_PORT DIR4: DIRP29 Mask         */
-#define GPIO_PORT_DIR4_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR4: DIRP30 Position     */
-#define GPIO_PORT_DIR4_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP30_Pos)                     /*!< GPIO_PORT DIR4: DIRP30 Mask         */
-#define GPIO_PORT_DIR4_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR4: DIRP31 Position     */
-#define GPIO_PORT_DIR4_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP31_Pos)                     /*!< GPIO_PORT DIR4: DIRP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_DIR5  -----------------------------------------
-#define GPIO_PORT_DIR5_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR5: DIRP0 Position      */
-#define GPIO_PORT_DIR5_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP0_Pos)                      /*!< GPIO_PORT DIR5: DIRP0 Mask          */
-#define GPIO_PORT_DIR5_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR5: DIRP1 Position      */
-#define GPIO_PORT_DIR5_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP1_Pos)                      /*!< GPIO_PORT DIR5: DIRP1 Mask          */
-#define GPIO_PORT_DIR5_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR5: DIRP2 Position      */
-#define GPIO_PORT_DIR5_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP2_Pos)                      /*!< GPIO_PORT DIR5: DIRP2 Mask          */
-#define GPIO_PORT_DIR5_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR5: DIRP3 Position      */
-#define GPIO_PORT_DIR5_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP3_Pos)                      /*!< GPIO_PORT DIR5: DIRP3 Mask          */
-#define GPIO_PORT_DIR5_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR5: DIRP4 Position      */
-#define GPIO_PORT_DIR5_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP4_Pos)                      /*!< GPIO_PORT DIR5: DIRP4 Mask          */
-#define GPIO_PORT_DIR5_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR5: DIRP5 Position      */
-#define GPIO_PORT_DIR5_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP5_Pos)                      /*!< GPIO_PORT DIR5: DIRP5 Mask          */
-#define GPIO_PORT_DIR5_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR5: DIRP6 Position      */
-#define GPIO_PORT_DIR5_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP6_Pos)                      /*!< GPIO_PORT DIR5: DIRP6 Mask          */
-#define GPIO_PORT_DIR5_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR5: DIRP7 Position      */
-#define GPIO_PORT_DIR5_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP7_Pos)                      /*!< GPIO_PORT DIR5: DIRP7 Mask          */
-#define GPIO_PORT_DIR5_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR5: DIRP8 Position      */
-#define GPIO_PORT_DIR5_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP8_Pos)                      /*!< GPIO_PORT DIR5: DIRP8 Mask          */
-#define GPIO_PORT_DIR5_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR5: DIRP9 Position      */
-#define GPIO_PORT_DIR5_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP9_Pos)                      /*!< GPIO_PORT DIR5: DIRP9 Mask          */
-#define GPIO_PORT_DIR5_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR5: DIRP10 Position     */
-#define GPIO_PORT_DIR5_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP10_Pos)                     /*!< GPIO_PORT DIR5: DIRP10 Mask         */
-#define GPIO_PORT_DIR5_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR5: DIRP11 Position     */
-#define GPIO_PORT_DIR5_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP11_Pos)                     /*!< GPIO_PORT DIR5: DIRP11 Mask         */
-#define GPIO_PORT_DIR5_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR5: DIRP12 Position     */
-#define GPIO_PORT_DIR5_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP12_Pos)                     /*!< GPIO_PORT DIR5: DIRP12 Mask         */
-#define GPIO_PORT_DIR5_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR5: DIRP13 Position     */
-#define GPIO_PORT_DIR5_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP13_Pos)                     /*!< GPIO_PORT DIR5: DIRP13 Mask         */
-#define GPIO_PORT_DIR5_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR5: DIRP14 Position     */
-#define GPIO_PORT_DIR5_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP14_Pos)                     /*!< GPIO_PORT DIR5: DIRP14 Mask         */
-#define GPIO_PORT_DIR5_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR5: DIRP15 Position     */
-#define GPIO_PORT_DIR5_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP15_Pos)                     /*!< GPIO_PORT DIR5: DIRP15 Mask         */
-#define GPIO_PORT_DIR5_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR5: DIRP16 Position     */
-#define GPIO_PORT_DIR5_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP16_Pos)                     /*!< GPIO_PORT DIR5: DIRP16 Mask         */
-#define GPIO_PORT_DIR5_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR5: DIRP17 Position     */
-#define GPIO_PORT_DIR5_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP17_Pos)                     /*!< GPIO_PORT DIR5: DIRP17 Mask         */
-#define GPIO_PORT_DIR5_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR5: DIRP18 Position     */
-#define GPIO_PORT_DIR5_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP18_Pos)                     /*!< GPIO_PORT DIR5: DIRP18 Mask         */
-#define GPIO_PORT_DIR5_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR5: DIRP19 Position     */
-#define GPIO_PORT_DIR5_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP19_Pos)                     /*!< GPIO_PORT DIR5: DIRP19 Mask         */
-#define GPIO_PORT_DIR5_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR5: DIRP20 Position     */
-#define GPIO_PORT_DIR5_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP20_Pos)                     /*!< GPIO_PORT DIR5: DIRP20 Mask         */
-#define GPIO_PORT_DIR5_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR5: DIRP21 Position     */
-#define GPIO_PORT_DIR5_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP21_Pos)                     /*!< GPIO_PORT DIR5: DIRP21 Mask         */
-#define GPIO_PORT_DIR5_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR5: DIRP22 Position     */
-#define GPIO_PORT_DIR5_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP22_Pos)                     /*!< GPIO_PORT DIR5: DIRP22 Mask         */
-#define GPIO_PORT_DIR5_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR5: DIRP23 Position     */
-#define GPIO_PORT_DIR5_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP23_Pos)                     /*!< GPIO_PORT DIR5: DIRP23 Mask         */
-#define GPIO_PORT_DIR5_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR5: DIRP24 Position     */
-#define GPIO_PORT_DIR5_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP24_Pos)                     /*!< GPIO_PORT DIR5: DIRP24 Mask         */
-#define GPIO_PORT_DIR5_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR5: DIRP25 Position     */
-#define GPIO_PORT_DIR5_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP25_Pos)                     /*!< GPIO_PORT DIR5: DIRP25 Mask         */
-#define GPIO_PORT_DIR5_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR5: DIRP26 Position     */
-#define GPIO_PORT_DIR5_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP26_Pos)                     /*!< GPIO_PORT DIR5: DIRP26 Mask         */
-#define GPIO_PORT_DIR5_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR5: DIRP27 Position     */
-#define GPIO_PORT_DIR5_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP27_Pos)                     /*!< GPIO_PORT DIR5: DIRP27 Mask         */
-#define GPIO_PORT_DIR5_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR5: DIRP28 Position     */
-#define GPIO_PORT_DIR5_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP28_Pos)                     /*!< GPIO_PORT DIR5: DIRP28 Mask         */
-#define GPIO_PORT_DIR5_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR5: DIRP29 Position     */
-#define GPIO_PORT_DIR5_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP29_Pos)                     /*!< GPIO_PORT DIR5: DIRP29 Mask         */
-#define GPIO_PORT_DIR5_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR5: DIRP30 Position     */
-#define GPIO_PORT_DIR5_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP30_Pos)                     /*!< GPIO_PORT DIR5: DIRP30 Mask         */
-#define GPIO_PORT_DIR5_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR5: DIRP31 Position     */
-#define GPIO_PORT_DIR5_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP31_Pos)                     /*!< GPIO_PORT DIR5: DIRP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_DIR6  -----------------------------------------
-#define GPIO_PORT_DIR6_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR6: DIRP0 Position      */
-#define GPIO_PORT_DIR6_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP0_Pos)                      /*!< GPIO_PORT DIR6: DIRP0 Mask          */
-#define GPIO_PORT_DIR6_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR6: DIRP1 Position      */
-#define GPIO_PORT_DIR6_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP1_Pos)                      /*!< GPIO_PORT DIR6: DIRP1 Mask          */
-#define GPIO_PORT_DIR6_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR6: DIRP2 Position      */
-#define GPIO_PORT_DIR6_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP2_Pos)                      /*!< GPIO_PORT DIR6: DIRP2 Mask          */
-#define GPIO_PORT_DIR6_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR6: DIRP3 Position      */
-#define GPIO_PORT_DIR6_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP3_Pos)                      /*!< GPIO_PORT DIR6: DIRP3 Mask          */
-#define GPIO_PORT_DIR6_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR6: DIRP4 Position      */
-#define GPIO_PORT_DIR6_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP4_Pos)                      /*!< GPIO_PORT DIR6: DIRP4 Mask          */
-#define GPIO_PORT_DIR6_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR6: DIRP5 Position      */
-#define GPIO_PORT_DIR6_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP5_Pos)                      /*!< GPIO_PORT DIR6: DIRP5 Mask          */
-#define GPIO_PORT_DIR6_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR6: DIRP6 Position      */
-#define GPIO_PORT_DIR6_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP6_Pos)                      /*!< GPIO_PORT DIR6: DIRP6 Mask          */
-#define GPIO_PORT_DIR6_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR6: DIRP7 Position      */
-#define GPIO_PORT_DIR6_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP7_Pos)                      /*!< GPIO_PORT DIR6: DIRP7 Mask          */
-#define GPIO_PORT_DIR6_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR6: DIRP8 Position      */
-#define GPIO_PORT_DIR6_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP8_Pos)                      /*!< GPIO_PORT DIR6: DIRP8 Mask          */
-#define GPIO_PORT_DIR6_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR6: DIRP9 Position      */
-#define GPIO_PORT_DIR6_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP9_Pos)                      /*!< GPIO_PORT DIR6: DIRP9 Mask          */
-#define GPIO_PORT_DIR6_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR6: DIRP10 Position     */
-#define GPIO_PORT_DIR6_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP10_Pos)                     /*!< GPIO_PORT DIR6: DIRP10 Mask         */
-#define GPIO_PORT_DIR6_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR6: DIRP11 Position     */
-#define GPIO_PORT_DIR6_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP11_Pos)                     /*!< GPIO_PORT DIR6: DIRP11 Mask         */
-#define GPIO_PORT_DIR6_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR6: DIRP12 Position     */
-#define GPIO_PORT_DIR6_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP12_Pos)                     /*!< GPIO_PORT DIR6: DIRP12 Mask         */
-#define GPIO_PORT_DIR6_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR6: DIRP13 Position     */
-#define GPIO_PORT_DIR6_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP13_Pos)                     /*!< GPIO_PORT DIR6: DIRP13 Mask         */
-#define GPIO_PORT_DIR6_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR6: DIRP14 Position     */
-#define GPIO_PORT_DIR6_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP14_Pos)                     /*!< GPIO_PORT DIR6: DIRP14 Mask         */
-#define GPIO_PORT_DIR6_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR6: DIRP15 Position     */
-#define GPIO_PORT_DIR6_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP15_Pos)                     /*!< GPIO_PORT DIR6: DIRP15 Mask         */
-#define GPIO_PORT_DIR6_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR6: DIRP16 Position     */
-#define GPIO_PORT_DIR6_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP16_Pos)                     /*!< GPIO_PORT DIR6: DIRP16 Mask         */
-#define GPIO_PORT_DIR6_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR6: DIRP17 Position     */
-#define GPIO_PORT_DIR6_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP17_Pos)                     /*!< GPIO_PORT DIR6: DIRP17 Mask         */
-#define GPIO_PORT_DIR6_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR6: DIRP18 Position     */
-#define GPIO_PORT_DIR6_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP18_Pos)                     /*!< GPIO_PORT DIR6: DIRP18 Mask         */
-#define GPIO_PORT_DIR6_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR6: DIRP19 Position     */
-#define GPIO_PORT_DIR6_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP19_Pos)                     /*!< GPIO_PORT DIR6: DIRP19 Mask         */
-#define GPIO_PORT_DIR6_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR6: DIRP20 Position     */
-#define GPIO_PORT_DIR6_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP20_Pos)                     /*!< GPIO_PORT DIR6: DIRP20 Mask         */
-#define GPIO_PORT_DIR6_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR6: DIRP21 Position     */
-#define GPIO_PORT_DIR6_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP21_Pos)                     /*!< GPIO_PORT DIR6: DIRP21 Mask         */
-#define GPIO_PORT_DIR6_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR6: DIRP22 Position     */
-#define GPIO_PORT_DIR6_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP22_Pos)                     /*!< GPIO_PORT DIR6: DIRP22 Mask         */
-#define GPIO_PORT_DIR6_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR6: DIRP23 Position     */
-#define GPIO_PORT_DIR6_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP23_Pos)                     /*!< GPIO_PORT DIR6: DIRP23 Mask         */
-#define GPIO_PORT_DIR6_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR6: DIRP24 Position     */
-#define GPIO_PORT_DIR6_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP24_Pos)                     /*!< GPIO_PORT DIR6: DIRP24 Mask         */
-#define GPIO_PORT_DIR6_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR6: DIRP25 Position     */
-#define GPIO_PORT_DIR6_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP25_Pos)                     /*!< GPIO_PORT DIR6: DIRP25 Mask         */
-#define GPIO_PORT_DIR6_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR6: DIRP26 Position     */
-#define GPIO_PORT_DIR6_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP26_Pos)                     /*!< GPIO_PORT DIR6: DIRP26 Mask         */
-#define GPIO_PORT_DIR6_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR6: DIRP27 Position     */
-#define GPIO_PORT_DIR6_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP27_Pos)                     /*!< GPIO_PORT DIR6: DIRP27 Mask         */
-#define GPIO_PORT_DIR6_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR6: DIRP28 Position     */
-#define GPIO_PORT_DIR6_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP28_Pos)                     /*!< GPIO_PORT DIR6: DIRP28 Mask         */
-#define GPIO_PORT_DIR6_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR6: DIRP29 Position     */
-#define GPIO_PORT_DIR6_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP29_Pos)                     /*!< GPIO_PORT DIR6: DIRP29 Mask         */
-#define GPIO_PORT_DIR6_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR6: DIRP30 Position     */
-#define GPIO_PORT_DIR6_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP30_Pos)                     /*!< GPIO_PORT DIR6: DIRP30 Mask         */
-#define GPIO_PORT_DIR6_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR6: DIRP31 Position     */
-#define GPIO_PORT_DIR6_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP31_Pos)                     /*!< GPIO_PORT DIR6: DIRP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_DIR7  -----------------------------------------
-#define GPIO_PORT_DIR7_DIRP0_Pos                              0                                                         /*!< GPIO_PORT DIR7: DIRP0 Position      */
-#define GPIO_PORT_DIR7_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP0_Pos)                      /*!< GPIO_PORT DIR7: DIRP0 Mask          */
-#define GPIO_PORT_DIR7_DIRP1_Pos                              1                                                         /*!< GPIO_PORT DIR7: DIRP1 Position      */
-#define GPIO_PORT_DIR7_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP1_Pos)                      /*!< GPIO_PORT DIR7: DIRP1 Mask          */
-#define GPIO_PORT_DIR7_DIRP2_Pos                              2                                                         /*!< GPIO_PORT DIR7: DIRP2 Position      */
-#define GPIO_PORT_DIR7_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP2_Pos)                      /*!< GPIO_PORT DIR7: DIRP2 Mask          */
-#define GPIO_PORT_DIR7_DIRP3_Pos                              3                                                         /*!< GPIO_PORT DIR7: DIRP3 Position      */
-#define GPIO_PORT_DIR7_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP3_Pos)                      /*!< GPIO_PORT DIR7: DIRP3 Mask          */
-#define GPIO_PORT_DIR7_DIRP4_Pos                              4                                                         /*!< GPIO_PORT DIR7: DIRP4 Position      */
-#define GPIO_PORT_DIR7_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP4_Pos)                      /*!< GPIO_PORT DIR7: DIRP4 Mask          */
-#define GPIO_PORT_DIR7_DIRP5_Pos                              5                                                         /*!< GPIO_PORT DIR7: DIRP5 Position      */
-#define GPIO_PORT_DIR7_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP5_Pos)                      /*!< GPIO_PORT DIR7: DIRP5 Mask          */
-#define GPIO_PORT_DIR7_DIRP6_Pos                              6                                                         /*!< GPIO_PORT DIR7: DIRP6 Position      */
-#define GPIO_PORT_DIR7_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP6_Pos)                      /*!< GPIO_PORT DIR7: DIRP6 Mask          */
-#define GPIO_PORT_DIR7_DIRP7_Pos                              7                                                         /*!< GPIO_PORT DIR7: DIRP7 Position      */
-#define GPIO_PORT_DIR7_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP7_Pos)                      /*!< GPIO_PORT DIR7: DIRP7 Mask          */
-#define GPIO_PORT_DIR7_DIRP8_Pos                              8                                                         /*!< GPIO_PORT DIR7: DIRP8 Position      */
-#define GPIO_PORT_DIR7_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP8_Pos)                      /*!< GPIO_PORT DIR7: DIRP8 Mask          */
-#define GPIO_PORT_DIR7_DIRP9_Pos                              9                                                         /*!< GPIO_PORT DIR7: DIRP9 Position      */
-#define GPIO_PORT_DIR7_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP9_Pos)                      /*!< GPIO_PORT DIR7: DIRP9 Mask          */
-#define GPIO_PORT_DIR7_DIRP10_Pos                             10                                                        /*!< GPIO_PORT DIR7: DIRP10 Position     */
-#define GPIO_PORT_DIR7_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP10_Pos)                     /*!< GPIO_PORT DIR7: DIRP10 Mask         */
-#define GPIO_PORT_DIR7_DIRP11_Pos                             11                                                        /*!< GPIO_PORT DIR7: DIRP11 Position     */
-#define GPIO_PORT_DIR7_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP11_Pos)                     /*!< GPIO_PORT DIR7: DIRP11 Mask         */
-#define GPIO_PORT_DIR7_DIRP12_Pos                             12                                                        /*!< GPIO_PORT DIR7: DIRP12 Position     */
-#define GPIO_PORT_DIR7_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP12_Pos)                     /*!< GPIO_PORT DIR7: DIRP12 Mask         */
-#define GPIO_PORT_DIR7_DIRP13_Pos                             13                                                        /*!< GPIO_PORT DIR7: DIRP13 Position     */
-#define GPIO_PORT_DIR7_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP13_Pos)                     /*!< GPIO_PORT DIR7: DIRP13 Mask         */
-#define GPIO_PORT_DIR7_DIRP14_Pos                             14                                                        /*!< GPIO_PORT DIR7: DIRP14 Position     */
-#define GPIO_PORT_DIR7_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP14_Pos)                     /*!< GPIO_PORT DIR7: DIRP14 Mask         */
-#define GPIO_PORT_DIR7_DIRP15_Pos                             15                                                        /*!< GPIO_PORT DIR7: DIRP15 Position     */
-#define GPIO_PORT_DIR7_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP15_Pos)                     /*!< GPIO_PORT DIR7: DIRP15 Mask         */
-#define GPIO_PORT_DIR7_DIRP16_Pos                             16                                                        /*!< GPIO_PORT DIR7: DIRP16 Position     */
-#define GPIO_PORT_DIR7_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP16_Pos)                     /*!< GPIO_PORT DIR7: DIRP16 Mask         */
-#define GPIO_PORT_DIR7_DIRP17_Pos                             17                                                        /*!< GPIO_PORT DIR7: DIRP17 Position     */
-#define GPIO_PORT_DIR7_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP17_Pos)                     /*!< GPIO_PORT DIR7: DIRP17 Mask         */
-#define GPIO_PORT_DIR7_DIRP18_Pos                             18                                                        /*!< GPIO_PORT DIR7: DIRP18 Position     */
-#define GPIO_PORT_DIR7_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP18_Pos)                     /*!< GPIO_PORT DIR7: DIRP18 Mask         */
-#define GPIO_PORT_DIR7_DIRP19_Pos                             19                                                        /*!< GPIO_PORT DIR7: DIRP19 Position     */
-#define GPIO_PORT_DIR7_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP19_Pos)                     /*!< GPIO_PORT DIR7: DIRP19 Mask         */
-#define GPIO_PORT_DIR7_DIRP20_Pos                             20                                                        /*!< GPIO_PORT DIR7: DIRP20 Position     */
-#define GPIO_PORT_DIR7_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP20_Pos)                     /*!< GPIO_PORT DIR7: DIRP20 Mask         */
-#define GPIO_PORT_DIR7_DIRP21_Pos                             21                                                        /*!< GPIO_PORT DIR7: DIRP21 Position     */
-#define GPIO_PORT_DIR7_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP21_Pos)                     /*!< GPIO_PORT DIR7: DIRP21 Mask         */
-#define GPIO_PORT_DIR7_DIRP22_Pos                             22                                                        /*!< GPIO_PORT DIR7: DIRP22 Position     */
-#define GPIO_PORT_DIR7_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP22_Pos)                     /*!< GPIO_PORT DIR7: DIRP22 Mask         */
-#define GPIO_PORT_DIR7_DIRP23_Pos                             23                                                        /*!< GPIO_PORT DIR7: DIRP23 Position     */
-#define GPIO_PORT_DIR7_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP23_Pos)                     /*!< GPIO_PORT DIR7: DIRP23 Mask         */
-#define GPIO_PORT_DIR7_DIRP24_Pos                             24                                                        /*!< GPIO_PORT DIR7: DIRP24 Position     */
-#define GPIO_PORT_DIR7_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP24_Pos)                     /*!< GPIO_PORT DIR7: DIRP24 Mask         */
-#define GPIO_PORT_DIR7_DIRP25_Pos                             25                                                        /*!< GPIO_PORT DIR7: DIRP25 Position     */
-#define GPIO_PORT_DIR7_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP25_Pos)                     /*!< GPIO_PORT DIR7: DIRP25 Mask         */
-#define GPIO_PORT_DIR7_DIRP26_Pos                             26                                                        /*!< GPIO_PORT DIR7: DIRP26 Position     */
-#define GPIO_PORT_DIR7_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP26_Pos)                     /*!< GPIO_PORT DIR7: DIRP26 Mask         */
-#define GPIO_PORT_DIR7_DIRP27_Pos                             27                                                        /*!< GPIO_PORT DIR7: DIRP27 Position     */
-#define GPIO_PORT_DIR7_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP27_Pos)                     /*!< GPIO_PORT DIR7: DIRP27 Mask         */
-#define GPIO_PORT_DIR7_DIRP28_Pos                             28                                                        /*!< GPIO_PORT DIR7: DIRP28 Position     */
-#define GPIO_PORT_DIR7_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP28_Pos)                     /*!< GPIO_PORT DIR7: DIRP28 Mask         */
-#define GPIO_PORT_DIR7_DIRP29_Pos                             29                                                        /*!< GPIO_PORT DIR7: DIRP29 Position     */
-#define GPIO_PORT_DIR7_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP29_Pos)                     /*!< GPIO_PORT DIR7: DIRP29 Mask         */
-#define GPIO_PORT_DIR7_DIRP30_Pos                             30                                                        /*!< GPIO_PORT DIR7: DIRP30 Position     */
-#define GPIO_PORT_DIR7_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP30_Pos)                     /*!< GPIO_PORT DIR7: DIRP30 Mask         */
-#define GPIO_PORT_DIR7_DIRP31_Pos                             31                                                        /*!< GPIO_PORT DIR7: DIRP31 Position     */
-#define GPIO_PORT_DIR7_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP31_Pos)                     /*!< GPIO_PORT DIR7: DIRP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_MASK0  ----------------------------------------
-#define GPIO_PORT_MASK0_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK0: MASKP0 Position    */
-#define GPIO_PORT_MASK0_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP0_Pos)                    /*!< GPIO_PORT MASK0: MASKP0 Mask        */
-#define GPIO_PORT_MASK0_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK0: MASKP1 Position    */
-#define GPIO_PORT_MASK0_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP1_Pos)                    /*!< GPIO_PORT MASK0: MASKP1 Mask        */
-#define GPIO_PORT_MASK0_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK0: MASKP2 Position    */
-#define GPIO_PORT_MASK0_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP2_Pos)                    /*!< GPIO_PORT MASK0: MASKP2 Mask        */
-#define GPIO_PORT_MASK0_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK0: MASKP3 Position    */
-#define GPIO_PORT_MASK0_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP3_Pos)                    /*!< GPIO_PORT MASK0: MASKP3 Mask        */
-#define GPIO_PORT_MASK0_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK0: MASKP4 Position    */
-#define GPIO_PORT_MASK0_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP4_Pos)                    /*!< GPIO_PORT MASK0: MASKP4 Mask        */
-#define GPIO_PORT_MASK0_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK0: MASKP5 Position    */
-#define GPIO_PORT_MASK0_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP5_Pos)                    /*!< GPIO_PORT MASK0: MASKP5 Mask        */
-#define GPIO_PORT_MASK0_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK0: MASKP6 Position    */
-#define GPIO_PORT_MASK0_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP6_Pos)                    /*!< GPIO_PORT MASK0: MASKP6 Mask        */
-#define GPIO_PORT_MASK0_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK0: MASKP7 Position    */
-#define GPIO_PORT_MASK0_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP7_Pos)                    /*!< GPIO_PORT MASK0: MASKP7 Mask        */
-#define GPIO_PORT_MASK0_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK0: MASKP8 Position    */
-#define GPIO_PORT_MASK0_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP8_Pos)                    /*!< GPIO_PORT MASK0: MASKP8 Mask        */
-#define GPIO_PORT_MASK0_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK0: MASKP9 Position    */
-#define GPIO_PORT_MASK0_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP9_Pos)                    /*!< GPIO_PORT MASK0: MASKP9 Mask        */
-#define GPIO_PORT_MASK0_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK0: MASKP10 Position   */
-#define GPIO_PORT_MASK0_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP10_Pos)                   /*!< GPIO_PORT MASK0: MASKP10 Mask       */
-#define GPIO_PORT_MASK0_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK0: MASKP11 Position   */
-#define GPIO_PORT_MASK0_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP11_Pos)                   /*!< GPIO_PORT MASK0: MASKP11 Mask       */
-#define GPIO_PORT_MASK0_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK0: MASKP12 Position   */
-#define GPIO_PORT_MASK0_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP12_Pos)                   /*!< GPIO_PORT MASK0: MASKP12 Mask       */
-#define GPIO_PORT_MASK0_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK0: MASKP13 Position   */
-#define GPIO_PORT_MASK0_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP13_Pos)                   /*!< GPIO_PORT MASK0: MASKP13 Mask       */
-#define GPIO_PORT_MASK0_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK0: MASKP14 Position   */
-#define GPIO_PORT_MASK0_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP14_Pos)                   /*!< GPIO_PORT MASK0: MASKP14 Mask       */
-#define GPIO_PORT_MASK0_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK0: MASKP15 Position   */
-#define GPIO_PORT_MASK0_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP15_Pos)                   /*!< GPIO_PORT MASK0: MASKP15 Mask       */
-#define GPIO_PORT_MASK0_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK0: MASKP16 Position   */
-#define GPIO_PORT_MASK0_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP16_Pos)                   /*!< GPIO_PORT MASK0: MASKP16 Mask       */
-#define GPIO_PORT_MASK0_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK0: MASKP17 Position   */
-#define GPIO_PORT_MASK0_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP17_Pos)                   /*!< GPIO_PORT MASK0: MASKP17 Mask       */
-#define GPIO_PORT_MASK0_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK0: MASKP18 Position   */
-#define GPIO_PORT_MASK0_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP18_Pos)                   /*!< GPIO_PORT MASK0: MASKP18 Mask       */
-#define GPIO_PORT_MASK0_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK0: MASKP19 Position   */
-#define GPIO_PORT_MASK0_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP19_Pos)                   /*!< GPIO_PORT MASK0: MASKP19 Mask       */
-#define GPIO_PORT_MASK0_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK0: MASKP20 Position   */
-#define GPIO_PORT_MASK0_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP20_Pos)                   /*!< GPIO_PORT MASK0: MASKP20 Mask       */
-#define GPIO_PORT_MASK0_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK0: MASKP21 Position   */
-#define GPIO_PORT_MASK0_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP21_Pos)                   /*!< GPIO_PORT MASK0: MASKP21 Mask       */
-#define GPIO_PORT_MASK0_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK0: MASKP22 Position   */
-#define GPIO_PORT_MASK0_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP22_Pos)                   /*!< GPIO_PORT MASK0: MASKP22 Mask       */
-#define GPIO_PORT_MASK0_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK0: MASKP23 Position   */
-#define GPIO_PORT_MASK0_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP23_Pos)                   /*!< GPIO_PORT MASK0: MASKP23 Mask       */
-#define GPIO_PORT_MASK0_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK0: MASKP24 Position   */
-#define GPIO_PORT_MASK0_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP24_Pos)                   /*!< GPIO_PORT MASK0: MASKP24 Mask       */
-#define GPIO_PORT_MASK0_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK0: MASKP25 Position   */
-#define GPIO_PORT_MASK0_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP25_Pos)                   /*!< GPIO_PORT MASK0: MASKP25 Mask       */
-#define GPIO_PORT_MASK0_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK0: MASKP26 Position   */
-#define GPIO_PORT_MASK0_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP26_Pos)                   /*!< GPIO_PORT MASK0: MASKP26 Mask       */
-#define GPIO_PORT_MASK0_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK0: MASKP27 Position   */
-#define GPIO_PORT_MASK0_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP27_Pos)                   /*!< GPIO_PORT MASK0: MASKP27 Mask       */
-#define GPIO_PORT_MASK0_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK0: MASKP28 Position   */
-#define GPIO_PORT_MASK0_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP28_Pos)                   /*!< GPIO_PORT MASK0: MASKP28 Mask       */
-#define GPIO_PORT_MASK0_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK0: MASKP29 Position   */
-#define GPIO_PORT_MASK0_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP29_Pos)                   /*!< GPIO_PORT MASK0: MASKP29 Mask       */
-#define GPIO_PORT_MASK0_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK0: MASKP30 Position   */
-#define GPIO_PORT_MASK0_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP30_Pos)                   /*!< GPIO_PORT MASK0: MASKP30 Mask       */
-#define GPIO_PORT_MASK0_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK0: MASKP31 Position   */
-#define GPIO_PORT_MASK0_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP31_Pos)                   /*!< GPIO_PORT MASK0: MASKP31 Mask       */
-
-// -------------------------------------  GPIO_PORT_MASK1  ----------------------------------------
-#define GPIO_PORT_MASK1_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK1: MASKP0 Position    */
-#define GPIO_PORT_MASK1_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP0_Pos)                    /*!< GPIO_PORT MASK1: MASKP0 Mask        */
-#define GPIO_PORT_MASK1_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK1: MASKP1 Position    */
-#define GPIO_PORT_MASK1_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP1_Pos)                    /*!< GPIO_PORT MASK1: MASKP1 Mask        */
-#define GPIO_PORT_MASK1_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK1: MASKP2 Position    */
-#define GPIO_PORT_MASK1_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP2_Pos)                    /*!< GPIO_PORT MASK1: MASKP2 Mask        */
-#define GPIO_PORT_MASK1_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK1: MASKP3 Position    */
-#define GPIO_PORT_MASK1_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP3_Pos)                    /*!< GPIO_PORT MASK1: MASKP3 Mask        */
-#define GPIO_PORT_MASK1_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK1: MASKP4 Position    */
-#define GPIO_PORT_MASK1_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP4_Pos)                    /*!< GPIO_PORT MASK1: MASKP4 Mask        */
-#define GPIO_PORT_MASK1_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK1: MASKP5 Position    */
-#define GPIO_PORT_MASK1_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP5_Pos)                    /*!< GPIO_PORT MASK1: MASKP5 Mask        */
-#define GPIO_PORT_MASK1_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK1: MASKP6 Position    */
-#define GPIO_PORT_MASK1_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP6_Pos)                    /*!< GPIO_PORT MASK1: MASKP6 Mask        */
-#define GPIO_PORT_MASK1_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK1: MASKP7 Position    */
-#define GPIO_PORT_MASK1_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP7_Pos)                    /*!< GPIO_PORT MASK1: MASKP7 Mask        */
-#define GPIO_PORT_MASK1_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK1: MASKP8 Position    */
-#define GPIO_PORT_MASK1_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP8_Pos)                    /*!< GPIO_PORT MASK1: MASKP8 Mask        */
-#define GPIO_PORT_MASK1_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK1: MASKP9 Position    */
-#define GPIO_PORT_MASK1_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP9_Pos)                    /*!< GPIO_PORT MASK1: MASKP9 Mask        */
-#define GPIO_PORT_MASK1_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK1: MASKP10 Position   */
-#define GPIO_PORT_MASK1_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP10_Pos)                   /*!< GPIO_PORT MASK1: MASKP10 Mask       */
-#define GPIO_PORT_MASK1_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK1: MASKP11 Position   */
-#define GPIO_PORT_MASK1_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP11_Pos)                   /*!< GPIO_PORT MASK1: MASKP11 Mask       */
-#define GPIO_PORT_MASK1_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK1: MASKP12 Position   */
-#define GPIO_PORT_MASK1_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP12_Pos)                   /*!< GPIO_PORT MASK1: MASKP12 Mask       */
-#define GPIO_PORT_MASK1_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK1: MASKP13 Position   */
-#define GPIO_PORT_MASK1_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP13_Pos)                   /*!< GPIO_PORT MASK1: MASKP13 Mask       */
-#define GPIO_PORT_MASK1_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK1: MASKP14 Position   */
-#define GPIO_PORT_MASK1_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP14_Pos)                   /*!< GPIO_PORT MASK1: MASKP14 Mask       */
-#define GPIO_PORT_MASK1_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK1: MASKP15 Position   */
-#define GPIO_PORT_MASK1_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP15_Pos)                   /*!< GPIO_PORT MASK1: MASKP15 Mask       */
-#define GPIO_PORT_MASK1_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK1: MASKP16 Position   */
-#define GPIO_PORT_MASK1_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP16_Pos)                   /*!< GPIO_PORT MASK1: MASKP16 Mask       */
-#define GPIO_PORT_MASK1_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK1: MASKP17 Position   */
-#define GPIO_PORT_MASK1_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP17_Pos)                   /*!< GPIO_PORT MASK1: MASKP17 Mask       */
-#define GPIO_PORT_MASK1_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK1: MASKP18 Position   */
-#define GPIO_PORT_MASK1_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP18_Pos)                   /*!< GPIO_PORT MASK1: MASKP18 Mask       */
-#define GPIO_PORT_MASK1_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK1: MASKP19 Position   */
-#define GPIO_PORT_MASK1_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP19_Pos)                   /*!< GPIO_PORT MASK1: MASKP19 Mask       */
-#define GPIO_PORT_MASK1_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK1: MASKP20 Position   */
-#define GPIO_PORT_MASK1_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP20_Pos)                   /*!< GPIO_PORT MASK1: MASKP20 Mask       */
-#define GPIO_PORT_MASK1_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK1: MASKP21 Position   */
-#define GPIO_PORT_MASK1_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP21_Pos)                   /*!< GPIO_PORT MASK1: MASKP21 Mask       */
-#define GPIO_PORT_MASK1_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK1: MASKP22 Position   */
-#define GPIO_PORT_MASK1_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP22_Pos)                   /*!< GPIO_PORT MASK1: MASKP22 Mask       */
-#define GPIO_PORT_MASK1_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK1: MASKP23 Position   */
-#define GPIO_PORT_MASK1_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP23_Pos)                   /*!< GPIO_PORT MASK1: MASKP23 Mask       */
-#define GPIO_PORT_MASK1_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK1: MASKP24 Position   */
-#define GPIO_PORT_MASK1_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP24_Pos)                   /*!< GPIO_PORT MASK1: MASKP24 Mask       */
-#define GPIO_PORT_MASK1_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK1: MASKP25 Position   */
-#define GPIO_PORT_MASK1_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP25_Pos)                   /*!< GPIO_PORT MASK1: MASKP25 Mask       */
-#define GPIO_PORT_MASK1_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK1: MASKP26 Position   */
-#define GPIO_PORT_MASK1_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP26_Pos)                   /*!< GPIO_PORT MASK1: MASKP26 Mask       */
-#define GPIO_PORT_MASK1_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK1: MASKP27 Position   */
-#define GPIO_PORT_MASK1_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP27_Pos)                   /*!< GPIO_PORT MASK1: MASKP27 Mask       */
-#define GPIO_PORT_MASK1_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK1: MASKP28 Position   */
-#define GPIO_PORT_MASK1_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP28_Pos)                   /*!< GPIO_PORT MASK1: MASKP28 Mask       */
-#define GPIO_PORT_MASK1_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK1: MASKP29 Position   */
-#define GPIO_PORT_MASK1_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP29_Pos)                   /*!< GPIO_PORT MASK1: MASKP29 Mask       */
-#define GPIO_PORT_MASK1_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK1: MASKP30 Position   */
-#define GPIO_PORT_MASK1_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP30_Pos)                   /*!< GPIO_PORT MASK1: MASKP30 Mask       */
-#define GPIO_PORT_MASK1_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK1: MASKP31 Position   */
-#define GPIO_PORT_MASK1_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP31_Pos)                   /*!< GPIO_PORT MASK1: MASKP31 Mask       */
-
-// -------------------------------------  GPIO_PORT_MASK2  ----------------------------------------
-#define GPIO_PORT_MASK2_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK2: MASKP0 Position    */
-#define GPIO_PORT_MASK2_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP0_Pos)                    /*!< GPIO_PORT MASK2: MASKP0 Mask        */
-#define GPIO_PORT_MASK2_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK2: MASKP1 Position    */
-#define GPIO_PORT_MASK2_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP1_Pos)                    /*!< GPIO_PORT MASK2: MASKP1 Mask        */
-#define GPIO_PORT_MASK2_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK2: MASKP2 Position    */
-#define GPIO_PORT_MASK2_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP2_Pos)                    /*!< GPIO_PORT MASK2: MASKP2 Mask        */
-#define GPIO_PORT_MASK2_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK2: MASKP3 Position    */
-#define GPIO_PORT_MASK2_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP3_Pos)                    /*!< GPIO_PORT MASK2: MASKP3 Mask        */
-#define GPIO_PORT_MASK2_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK2: MASKP4 Position    */
-#define GPIO_PORT_MASK2_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP4_Pos)                    /*!< GPIO_PORT MASK2: MASKP4 Mask        */
-#define GPIO_PORT_MASK2_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK2: MASKP5 Position    */
-#define GPIO_PORT_MASK2_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP5_Pos)                    /*!< GPIO_PORT MASK2: MASKP5 Mask        */
-#define GPIO_PORT_MASK2_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK2: MASKP6 Position    */
-#define GPIO_PORT_MASK2_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP6_Pos)                    /*!< GPIO_PORT MASK2: MASKP6 Mask        */
-#define GPIO_PORT_MASK2_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK2: MASKP7 Position    */
-#define GPIO_PORT_MASK2_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP7_Pos)                    /*!< GPIO_PORT MASK2: MASKP7 Mask        */
-#define GPIO_PORT_MASK2_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK2: MASKP8 Position    */
-#define GPIO_PORT_MASK2_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP8_Pos)                    /*!< GPIO_PORT MASK2: MASKP8 Mask        */
-#define GPIO_PORT_MASK2_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK2: MASKP9 Position    */
-#define GPIO_PORT_MASK2_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP9_Pos)                    /*!< GPIO_PORT MASK2: MASKP9 Mask        */
-#define GPIO_PORT_MASK2_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK2: MASKP10 Position   */
-#define GPIO_PORT_MASK2_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP10_Pos)                   /*!< GPIO_PORT MASK2: MASKP10 Mask       */
-#define GPIO_PORT_MASK2_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK2: MASKP11 Position   */
-#define GPIO_PORT_MASK2_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP11_Pos)                   /*!< GPIO_PORT MASK2: MASKP11 Mask       */
-#define GPIO_PORT_MASK2_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK2: MASKP12 Position   */
-#define GPIO_PORT_MASK2_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP12_Pos)                   /*!< GPIO_PORT MASK2: MASKP12 Mask       */
-#define GPIO_PORT_MASK2_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK2: MASKP13 Position   */
-#define GPIO_PORT_MASK2_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP13_Pos)                   /*!< GPIO_PORT MASK2: MASKP13 Mask       */
-#define GPIO_PORT_MASK2_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK2: MASKP14 Position   */
-#define GPIO_PORT_MASK2_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP14_Pos)                   /*!< GPIO_PORT MASK2: MASKP14 Mask       */
-#define GPIO_PORT_MASK2_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK2: MASKP15 Position   */
-#define GPIO_PORT_MASK2_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP15_Pos)                   /*!< GPIO_PORT MASK2: MASKP15 Mask       */
-#define GPIO_PORT_MASK2_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK2: MASKP16 Position   */
-#define GPIO_PORT_MASK2_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP16_Pos)                   /*!< GPIO_PORT MASK2: MASKP16 Mask       */
-#define GPIO_PORT_MASK2_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK2: MASKP17 Position   */
-#define GPIO_PORT_MASK2_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP17_Pos)                   /*!< GPIO_PORT MASK2: MASKP17 Mask       */
-#define GPIO_PORT_MASK2_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK2: MASKP18 Position   */
-#define GPIO_PORT_MASK2_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP18_Pos)                   /*!< GPIO_PORT MASK2: MASKP18 Mask       */
-#define GPIO_PORT_MASK2_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK2: MASKP19 Position   */
-#define GPIO_PORT_MASK2_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP19_Pos)                   /*!< GPIO_PORT MASK2: MASKP19 Mask       */
-#define GPIO_PORT_MASK2_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK2: MASKP20 Position   */
-#define GPIO_PORT_MASK2_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP20_Pos)                   /*!< GPIO_PORT MASK2: MASKP20 Mask       */
-#define GPIO_PORT_MASK2_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK2: MASKP21 Position   */
-#define GPIO_PORT_MASK2_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP21_Pos)                   /*!< GPIO_PORT MASK2: MASKP21 Mask       */
-#define GPIO_PORT_MASK2_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK2: MASKP22 Position   */
-#define GPIO_PORT_MASK2_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP22_Pos)                   /*!< GPIO_PORT MASK2: MASKP22 Mask       */
-#define GPIO_PORT_MASK2_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK2: MASKP23 Position   */
-#define GPIO_PORT_MASK2_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP23_Pos)                   /*!< GPIO_PORT MASK2: MASKP23 Mask       */
-#define GPIO_PORT_MASK2_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK2: MASKP24 Position   */
-#define GPIO_PORT_MASK2_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP24_Pos)                   /*!< GPIO_PORT MASK2: MASKP24 Mask       */
-#define GPIO_PORT_MASK2_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK2: MASKP25 Position   */
-#define GPIO_PORT_MASK2_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP25_Pos)                   /*!< GPIO_PORT MASK2: MASKP25 Mask       */
-#define GPIO_PORT_MASK2_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK2: MASKP26 Position   */
-#define GPIO_PORT_MASK2_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP26_Pos)                   /*!< GPIO_PORT MASK2: MASKP26 Mask       */
-#define GPIO_PORT_MASK2_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK2: MASKP27 Position   */
-#define GPIO_PORT_MASK2_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP27_Pos)                   /*!< GPIO_PORT MASK2: MASKP27 Mask       */
-#define GPIO_PORT_MASK2_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK2: MASKP28 Position   */
-#define GPIO_PORT_MASK2_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP28_Pos)                   /*!< GPIO_PORT MASK2: MASKP28 Mask       */
-#define GPIO_PORT_MASK2_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK2: MASKP29 Position   */
-#define GPIO_PORT_MASK2_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP29_Pos)                   /*!< GPIO_PORT MASK2: MASKP29 Mask       */
-#define GPIO_PORT_MASK2_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK2: MASKP30 Position   */
-#define GPIO_PORT_MASK2_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP30_Pos)                   /*!< GPIO_PORT MASK2: MASKP30 Mask       */
-#define GPIO_PORT_MASK2_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK2: MASKP31 Position   */
-#define GPIO_PORT_MASK2_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP31_Pos)                   /*!< GPIO_PORT MASK2: MASKP31 Mask       */
-
-// -------------------------------------  GPIO_PORT_MASK3  ----------------------------------------
-#define GPIO_PORT_MASK3_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK3: MASKP0 Position    */
-#define GPIO_PORT_MASK3_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP0_Pos)                    /*!< GPIO_PORT MASK3: MASKP0 Mask        */
-#define GPIO_PORT_MASK3_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK3: MASKP1 Position    */
-#define GPIO_PORT_MASK3_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP1_Pos)                    /*!< GPIO_PORT MASK3: MASKP1 Mask        */
-#define GPIO_PORT_MASK3_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK3: MASKP2 Position    */
-#define GPIO_PORT_MASK3_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP2_Pos)                    /*!< GPIO_PORT MASK3: MASKP2 Mask        */
-#define GPIO_PORT_MASK3_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK3: MASKP3 Position    */
-#define GPIO_PORT_MASK3_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP3_Pos)                    /*!< GPIO_PORT MASK3: MASKP3 Mask        */
-#define GPIO_PORT_MASK3_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK3: MASKP4 Position    */
-#define GPIO_PORT_MASK3_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP4_Pos)                    /*!< GPIO_PORT MASK3: MASKP4 Mask        */
-#define GPIO_PORT_MASK3_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK3: MASKP5 Position    */
-#define GPIO_PORT_MASK3_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP5_Pos)                    /*!< GPIO_PORT MASK3: MASKP5 Mask        */
-#define GPIO_PORT_MASK3_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK3: MASKP6 Position    */
-#define GPIO_PORT_MASK3_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP6_Pos)                    /*!< GPIO_PORT MASK3: MASKP6 Mask        */
-#define GPIO_PORT_MASK3_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK3: MASKP7 Position    */
-#define GPIO_PORT_MASK3_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP7_Pos)                    /*!< GPIO_PORT MASK3: MASKP7 Mask        */
-#define GPIO_PORT_MASK3_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK3: MASKP8 Position    */
-#define GPIO_PORT_MASK3_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP8_Pos)                    /*!< GPIO_PORT MASK3: MASKP8 Mask        */
-#define GPIO_PORT_MASK3_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK3: MASKP9 Position    */
-#define GPIO_PORT_MASK3_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP9_Pos)                    /*!< GPIO_PORT MASK3: MASKP9 Mask        */
-#define GPIO_PORT_MASK3_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK3: MASKP10 Position   */
-#define GPIO_PORT_MASK3_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP10_Pos)                   /*!< GPIO_PORT MASK3: MASKP10 Mask       */
-#define GPIO_PORT_MASK3_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK3: MASKP11 Position   */
-#define GPIO_PORT_MASK3_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP11_Pos)                   /*!< GPIO_PORT MASK3: MASKP11 Mask       */
-#define GPIO_PORT_MASK3_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK3: MASKP12 Position   */
-#define GPIO_PORT_MASK3_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP12_Pos)                   /*!< GPIO_PORT MASK3: MASKP12 Mask       */
-#define GPIO_PORT_MASK3_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK3: MASKP13 Position   */
-#define GPIO_PORT_MASK3_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP13_Pos)                   /*!< GPIO_PORT MASK3: MASKP13 Mask       */
-#define GPIO_PORT_MASK3_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK3: MASKP14 Position   */
-#define GPIO_PORT_MASK3_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP14_Pos)                   /*!< GPIO_PORT MASK3: MASKP14 Mask       */
-#define GPIO_PORT_MASK3_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK3: MASKP15 Position   */
-#define GPIO_PORT_MASK3_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP15_Pos)                   /*!< GPIO_PORT MASK3: MASKP15 Mask       */
-#define GPIO_PORT_MASK3_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK3: MASKP16 Position   */
-#define GPIO_PORT_MASK3_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP16_Pos)                   /*!< GPIO_PORT MASK3: MASKP16 Mask       */
-#define GPIO_PORT_MASK3_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK3: MASKP17 Position   */
-#define GPIO_PORT_MASK3_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP17_Pos)                   /*!< GPIO_PORT MASK3: MASKP17 Mask       */
-#define GPIO_PORT_MASK3_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK3: MASKP18 Position   */
-#define GPIO_PORT_MASK3_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP18_Pos)                   /*!< GPIO_PORT MASK3: MASKP18 Mask       */
-#define GPIO_PORT_MASK3_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK3: MASKP19 Position   */
-#define GPIO_PORT_MASK3_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP19_Pos)                   /*!< GPIO_PORT MASK3: MASKP19 Mask       */
-#define GPIO_PORT_MASK3_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK3: MASKP20 Position   */
-#define GPIO_PORT_MASK3_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP20_Pos)                   /*!< GPIO_PORT MASK3: MASKP20 Mask       */
-#define GPIO_PORT_MASK3_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK3: MASKP21 Position   */
-#define GPIO_PORT_MASK3_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP21_Pos)                   /*!< GPIO_PORT MASK3: MASKP21 Mask       */
-#define GPIO_PORT_MASK3_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK3: MASKP22 Position   */
-#define GPIO_PORT_MASK3_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP22_Pos)                   /*!< GPIO_PORT MASK3: MASKP22 Mask       */
-#define GPIO_PORT_MASK3_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK3: MASKP23 Position   */
-#define GPIO_PORT_MASK3_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP23_Pos)                   /*!< GPIO_PORT MASK3: MASKP23 Mask       */
-#define GPIO_PORT_MASK3_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK3: MASKP24 Position   */
-#define GPIO_PORT_MASK3_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP24_Pos)                   /*!< GPIO_PORT MASK3: MASKP24 Mask       */
-#define GPIO_PORT_MASK3_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK3: MASKP25 Position   */
-#define GPIO_PORT_MASK3_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP25_Pos)                   /*!< GPIO_PORT MASK3: MASKP25 Mask       */
-#define GPIO_PORT_MASK3_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK3: MASKP26 Position   */
-#define GPIO_PORT_MASK3_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP26_Pos)                   /*!< GPIO_PORT MASK3: MASKP26 Mask       */
-#define GPIO_PORT_MASK3_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK3: MASKP27 Position   */
-#define GPIO_PORT_MASK3_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP27_Pos)                   /*!< GPIO_PORT MASK3: MASKP27 Mask       */
-#define GPIO_PORT_MASK3_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK3: MASKP28 Position   */
-#define GPIO_PORT_MASK3_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP28_Pos)                   /*!< GPIO_PORT MASK3: MASKP28 Mask       */
-#define GPIO_PORT_MASK3_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK3: MASKP29 Position   */
-#define GPIO_PORT_MASK3_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP29_Pos)                   /*!< GPIO_PORT MASK3: MASKP29 Mask       */
-#define GPIO_PORT_MASK3_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK3: MASKP30 Position   */
-#define GPIO_PORT_MASK3_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP30_Pos)                   /*!< GPIO_PORT MASK3: MASKP30 Mask       */
-#define GPIO_PORT_MASK3_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK3: MASKP31 Position   */
-#define GPIO_PORT_MASK3_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP31_Pos)                   /*!< GPIO_PORT MASK3: MASKP31 Mask       */
-
-// -------------------------------------  GPIO_PORT_MASK4  ----------------------------------------
-#define GPIO_PORT_MASK4_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK4: MASKP0 Position    */
-#define GPIO_PORT_MASK4_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP0_Pos)                    /*!< GPIO_PORT MASK4: MASKP0 Mask        */
-#define GPIO_PORT_MASK4_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK4: MASKP1 Position    */
-#define GPIO_PORT_MASK4_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP1_Pos)                    /*!< GPIO_PORT MASK4: MASKP1 Mask        */
-#define GPIO_PORT_MASK4_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK4: MASKP2 Position    */
-#define GPIO_PORT_MASK4_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP2_Pos)                    /*!< GPIO_PORT MASK4: MASKP2 Mask        */
-#define GPIO_PORT_MASK4_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK4: MASKP3 Position    */
-#define GPIO_PORT_MASK4_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP3_Pos)                    /*!< GPIO_PORT MASK4: MASKP3 Mask        */
-#define GPIO_PORT_MASK4_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK4: MASKP4 Position    */
-#define GPIO_PORT_MASK4_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP4_Pos)                    /*!< GPIO_PORT MASK4: MASKP4 Mask        */
-#define GPIO_PORT_MASK4_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK4: MASKP5 Position    */
-#define GPIO_PORT_MASK4_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP5_Pos)                    /*!< GPIO_PORT MASK4: MASKP5 Mask        */
-#define GPIO_PORT_MASK4_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK4: MASKP6 Position    */
-#define GPIO_PORT_MASK4_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP6_Pos)                    /*!< GPIO_PORT MASK4: MASKP6 Mask        */
-#define GPIO_PORT_MASK4_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK4: MASKP7 Position    */
-#define GPIO_PORT_MASK4_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP7_Pos)                    /*!< GPIO_PORT MASK4: MASKP7 Mask        */
-#define GPIO_PORT_MASK4_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK4: MASKP8 Position    */
-#define GPIO_PORT_MASK4_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP8_Pos)                    /*!< GPIO_PORT MASK4: MASKP8 Mask        */
-#define GPIO_PORT_MASK4_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK4: MASKP9 Position    */
-#define GPIO_PORT_MASK4_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP9_Pos)                    /*!< GPIO_PORT MASK4: MASKP9 Mask        */
-#define GPIO_PORT_MASK4_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK4: MASKP10 Position   */
-#define GPIO_PORT_MASK4_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP10_Pos)                   /*!< GPIO_PORT MASK4: MASKP10 Mask       */
-#define GPIO_PORT_MASK4_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK4: MASKP11 Position   */
-#define GPIO_PORT_MASK4_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP11_Pos)                   /*!< GPIO_PORT MASK4: MASKP11 Mask       */
-#define GPIO_PORT_MASK4_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK4: MASKP12 Position   */
-#define GPIO_PORT_MASK4_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP12_Pos)                   /*!< GPIO_PORT MASK4: MASKP12 Mask       */
-#define GPIO_PORT_MASK4_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK4: MASKP13 Position   */
-#define GPIO_PORT_MASK4_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP13_Pos)                   /*!< GPIO_PORT MASK4: MASKP13 Mask       */
-#define GPIO_PORT_MASK4_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK4: MASKP14 Position   */
-#define GPIO_PORT_MASK4_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP14_Pos)                   /*!< GPIO_PORT MASK4: MASKP14 Mask       */
-#define GPIO_PORT_MASK4_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK4: MASKP15 Position   */
-#define GPIO_PORT_MASK4_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP15_Pos)                   /*!< GPIO_PORT MASK4: MASKP15 Mask       */
-#define GPIO_PORT_MASK4_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK4: MASKP16 Position   */
-#define GPIO_PORT_MASK4_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP16_Pos)                   /*!< GPIO_PORT MASK4: MASKP16 Mask       */
-#define GPIO_PORT_MASK4_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK4: MASKP17 Position   */
-#define GPIO_PORT_MASK4_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP17_Pos)                   /*!< GPIO_PORT MASK4: MASKP17 Mask       */
-#define GPIO_PORT_MASK4_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK4: MASKP18 Position   */
-#define GPIO_PORT_MASK4_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP18_Pos)                   /*!< GPIO_PORT MASK4: MASKP18 Mask       */
-#define GPIO_PORT_MASK4_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK4: MASKP19 Position   */
-#define GPIO_PORT_MASK4_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP19_Pos)                   /*!< GPIO_PORT MASK4: MASKP19 Mask       */
-#define GPIO_PORT_MASK4_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK4: MASKP20 Position   */
-#define GPIO_PORT_MASK4_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP20_Pos)                   /*!< GPIO_PORT MASK4: MASKP20 Mask       */
-#define GPIO_PORT_MASK4_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK4: MASKP21 Position   */
-#define GPIO_PORT_MASK4_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP21_Pos)                   /*!< GPIO_PORT MASK4: MASKP21 Mask       */
-#define GPIO_PORT_MASK4_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK4: MASKP22 Position   */
-#define GPIO_PORT_MASK4_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP22_Pos)                   /*!< GPIO_PORT MASK4: MASKP22 Mask       */
-#define GPIO_PORT_MASK4_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK4: MASKP23 Position   */
-#define GPIO_PORT_MASK4_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP23_Pos)                   /*!< GPIO_PORT MASK4: MASKP23 Mask       */
-#define GPIO_PORT_MASK4_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK4: MASKP24 Position   */
-#define GPIO_PORT_MASK4_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP24_Pos)                   /*!< GPIO_PORT MASK4: MASKP24 Mask       */
-#define GPIO_PORT_MASK4_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK4: MASKP25 Position   */
-#define GPIO_PORT_MASK4_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP25_Pos)                   /*!< GPIO_PORT MASK4: MASKP25 Mask       */
-#define GPIO_PORT_MASK4_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK4: MASKP26 Position   */
-#define GPIO_PORT_MASK4_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP26_Pos)                   /*!< GPIO_PORT MASK4: MASKP26 Mask       */
-#define GPIO_PORT_MASK4_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK4: MASKP27 Position   */
-#define GPIO_PORT_MASK4_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP27_Pos)                   /*!< GPIO_PORT MASK4: MASKP27 Mask       */
-#define GPIO_PORT_MASK4_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK4: MASKP28 Position   */
-#define GPIO_PORT_MASK4_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP28_Pos)                   /*!< GPIO_PORT MASK4: MASKP28 Mask       */
-#define GPIO_PORT_MASK4_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK4: MASKP29 Position   */
-#define GPIO_PORT_MASK4_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP29_Pos)                   /*!< GPIO_PORT MASK4: MASKP29 Mask       */
-#define GPIO_PORT_MASK4_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK4: MASKP30 Position   */
-#define GPIO_PORT_MASK4_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP30_Pos)                   /*!< GPIO_PORT MASK4: MASKP30 Mask       */
-#define GPIO_PORT_MASK4_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK4: MASKP31 Position   */
-#define GPIO_PORT_MASK4_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP31_Pos)                   /*!< GPIO_PORT MASK4: MASKP31 Mask       */
-
-// -------------------------------------  GPIO_PORT_MASK5  ----------------------------------------
-#define GPIO_PORT_MASK5_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK5: MASKP0 Position    */
-#define GPIO_PORT_MASK5_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP0_Pos)                    /*!< GPIO_PORT MASK5: MASKP0 Mask        */
-#define GPIO_PORT_MASK5_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK5: MASKP1 Position    */
-#define GPIO_PORT_MASK5_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP1_Pos)                    /*!< GPIO_PORT MASK5: MASKP1 Mask        */
-#define GPIO_PORT_MASK5_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK5: MASKP2 Position    */
-#define GPIO_PORT_MASK5_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP2_Pos)                    /*!< GPIO_PORT MASK5: MASKP2 Mask        */
-#define GPIO_PORT_MASK5_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK5: MASKP3 Position    */
-#define GPIO_PORT_MASK5_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP3_Pos)                    /*!< GPIO_PORT MASK5: MASKP3 Mask        */
-#define GPIO_PORT_MASK5_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK5: MASKP4 Position    */
-#define GPIO_PORT_MASK5_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP4_Pos)                    /*!< GPIO_PORT MASK5: MASKP4 Mask        */
-#define GPIO_PORT_MASK5_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK5: MASKP5 Position    */
-#define GPIO_PORT_MASK5_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP5_Pos)                    /*!< GPIO_PORT MASK5: MASKP5 Mask        */
-#define GPIO_PORT_MASK5_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK5: MASKP6 Position    */
-#define GPIO_PORT_MASK5_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP6_Pos)                    /*!< GPIO_PORT MASK5: MASKP6 Mask        */
-#define GPIO_PORT_MASK5_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK5: MASKP7 Position    */
-#define GPIO_PORT_MASK5_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP7_Pos)                    /*!< GPIO_PORT MASK5: MASKP7 Mask        */
-#define GPIO_PORT_MASK5_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK5: MASKP8 Position    */
-#define GPIO_PORT_MASK5_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP8_Pos)                    /*!< GPIO_PORT MASK5: MASKP8 Mask        */
-#define GPIO_PORT_MASK5_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK5: MASKP9 Position    */
-#define GPIO_PORT_MASK5_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP9_Pos)                    /*!< GPIO_PORT MASK5: MASKP9 Mask        */
-#define GPIO_PORT_MASK5_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK5: MASKP10 Position   */
-#define GPIO_PORT_MASK5_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP10_Pos)                   /*!< GPIO_PORT MASK5: MASKP10 Mask       */
-#define GPIO_PORT_MASK5_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK5: MASKP11 Position   */
-#define GPIO_PORT_MASK5_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP11_Pos)                   /*!< GPIO_PORT MASK5: MASKP11 Mask       */
-#define GPIO_PORT_MASK5_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK5: MASKP12 Position   */
-#define GPIO_PORT_MASK5_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP12_Pos)                   /*!< GPIO_PORT MASK5: MASKP12 Mask       */
-#define GPIO_PORT_MASK5_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK5: MASKP13 Position   */
-#define GPIO_PORT_MASK5_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP13_Pos)                   /*!< GPIO_PORT MASK5: MASKP13 Mask       */
-#define GPIO_PORT_MASK5_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK5: MASKP14 Position   */
-#define GPIO_PORT_MASK5_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP14_Pos)                   /*!< GPIO_PORT MASK5: MASKP14 Mask       */
-#define GPIO_PORT_MASK5_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK5: MASKP15 Position   */
-#define GPIO_PORT_MASK5_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP15_Pos)                   /*!< GPIO_PORT MASK5: MASKP15 Mask       */
-#define GPIO_PORT_MASK5_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK5: MASKP16 Position   */
-#define GPIO_PORT_MASK5_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP16_Pos)                   /*!< GPIO_PORT MASK5: MASKP16 Mask       */
-#define GPIO_PORT_MASK5_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK5: MASKP17 Position   */
-#define GPIO_PORT_MASK5_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP17_Pos)                   /*!< GPIO_PORT MASK5: MASKP17 Mask       */
-#define GPIO_PORT_MASK5_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK5: MASKP18 Position   */
-#define GPIO_PORT_MASK5_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP18_Pos)                   /*!< GPIO_PORT MASK5: MASKP18 Mask       */
-#define GPIO_PORT_MASK5_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK5: MASKP19 Position   */
-#define GPIO_PORT_MASK5_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP19_Pos)                   /*!< GPIO_PORT MASK5: MASKP19 Mask       */
-#define GPIO_PORT_MASK5_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK5: MASKP20 Position   */
-#define GPIO_PORT_MASK5_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP20_Pos)                   /*!< GPIO_PORT MASK5: MASKP20 Mask       */
-#define GPIO_PORT_MASK5_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK5: MASKP21 Position   */
-#define GPIO_PORT_MASK5_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP21_Pos)                   /*!< GPIO_PORT MASK5: MASKP21 Mask       */
-#define GPIO_PORT_MASK5_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK5: MASKP22 Position   */
-#define GPIO_PORT_MASK5_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP22_Pos)                   /*!< GPIO_PORT MASK5: MASKP22 Mask       */
-#define GPIO_PORT_MASK5_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK5: MASKP23 Position   */
-#define GPIO_PORT_MASK5_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP23_Pos)                   /*!< GPIO_PORT MASK5: MASKP23 Mask       */
-#define GPIO_PORT_MASK5_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK5: MASKP24 Position   */
-#define GPIO_PORT_MASK5_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP24_Pos)                   /*!< GPIO_PORT MASK5: MASKP24 Mask       */
-#define GPIO_PORT_MASK5_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK5: MASKP25 Position   */
-#define GPIO_PORT_MASK5_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP25_Pos)                   /*!< GPIO_PORT MASK5: MASKP25 Mask       */
-#define GPIO_PORT_MASK5_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK5: MASKP26 Position   */
-#define GPIO_PORT_MASK5_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP26_Pos)                   /*!< GPIO_PORT MASK5: MASKP26 Mask       */
-#define GPIO_PORT_MASK5_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK5: MASKP27 Position   */
-#define GPIO_PORT_MASK5_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP27_Pos)                   /*!< GPIO_PORT MASK5: MASKP27 Mask       */
-#define GPIO_PORT_MASK5_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK5: MASKP28 Position   */
-#define GPIO_PORT_MASK5_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP28_Pos)                   /*!< GPIO_PORT MASK5: MASKP28 Mask       */
-#define GPIO_PORT_MASK5_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK5: MASKP29 Position   */
-#define GPIO_PORT_MASK5_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP29_Pos)                   /*!< GPIO_PORT MASK5: MASKP29 Mask       */
-#define GPIO_PORT_MASK5_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK5: MASKP30 Position   */
-#define GPIO_PORT_MASK5_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP30_Pos)                   /*!< GPIO_PORT MASK5: MASKP30 Mask       */
-#define GPIO_PORT_MASK5_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK5: MASKP31 Position   */
-#define GPIO_PORT_MASK5_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP31_Pos)                   /*!< GPIO_PORT MASK5: MASKP31 Mask       */
-
-// -------------------------------------  GPIO_PORT_MASK6  ----------------------------------------
-#define GPIO_PORT_MASK6_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK6: MASKP0 Position    */
-#define GPIO_PORT_MASK6_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP0_Pos)                    /*!< GPIO_PORT MASK6: MASKP0 Mask        */
-#define GPIO_PORT_MASK6_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK6: MASKP1 Position    */
-#define GPIO_PORT_MASK6_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP1_Pos)                    /*!< GPIO_PORT MASK6: MASKP1 Mask        */
-#define GPIO_PORT_MASK6_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK6: MASKP2 Position    */
-#define GPIO_PORT_MASK6_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP2_Pos)                    /*!< GPIO_PORT MASK6: MASKP2 Mask        */
-#define GPIO_PORT_MASK6_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK6: MASKP3 Position    */
-#define GPIO_PORT_MASK6_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP3_Pos)                    /*!< GPIO_PORT MASK6: MASKP3 Mask        */
-#define GPIO_PORT_MASK6_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK6: MASKP4 Position    */
-#define GPIO_PORT_MASK6_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP4_Pos)                    /*!< GPIO_PORT MASK6: MASKP4 Mask        */
-#define GPIO_PORT_MASK6_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK6: MASKP5 Position    */
-#define GPIO_PORT_MASK6_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP5_Pos)                    /*!< GPIO_PORT MASK6: MASKP5 Mask        */
-#define GPIO_PORT_MASK6_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK6: MASKP6 Position    */
-#define GPIO_PORT_MASK6_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP6_Pos)                    /*!< GPIO_PORT MASK6: MASKP6 Mask        */
-#define GPIO_PORT_MASK6_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK6: MASKP7 Position    */
-#define GPIO_PORT_MASK6_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP7_Pos)                    /*!< GPIO_PORT MASK6: MASKP7 Mask        */
-#define GPIO_PORT_MASK6_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK6: MASKP8 Position    */
-#define GPIO_PORT_MASK6_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP8_Pos)                    /*!< GPIO_PORT MASK6: MASKP8 Mask        */
-#define GPIO_PORT_MASK6_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK6: MASKP9 Position    */
-#define GPIO_PORT_MASK6_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP9_Pos)                    /*!< GPIO_PORT MASK6: MASKP9 Mask        */
-#define GPIO_PORT_MASK6_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK6: MASKP10 Position   */
-#define GPIO_PORT_MASK6_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP10_Pos)                   /*!< GPIO_PORT MASK6: MASKP10 Mask       */
-#define GPIO_PORT_MASK6_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK6: MASKP11 Position   */
-#define GPIO_PORT_MASK6_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP11_Pos)                   /*!< GPIO_PORT MASK6: MASKP11 Mask       */
-#define GPIO_PORT_MASK6_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK6: MASKP12 Position   */
-#define GPIO_PORT_MASK6_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP12_Pos)                   /*!< GPIO_PORT MASK6: MASKP12 Mask       */
-#define GPIO_PORT_MASK6_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK6: MASKP13 Position   */
-#define GPIO_PORT_MASK6_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP13_Pos)                   /*!< GPIO_PORT MASK6: MASKP13 Mask       */
-#define GPIO_PORT_MASK6_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK6: MASKP14 Position   */
-#define GPIO_PORT_MASK6_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP14_Pos)                   /*!< GPIO_PORT MASK6: MASKP14 Mask       */
-#define GPIO_PORT_MASK6_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK6: MASKP15 Position   */
-#define GPIO_PORT_MASK6_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP15_Pos)                   /*!< GPIO_PORT MASK6: MASKP15 Mask       */
-#define GPIO_PORT_MASK6_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK6: MASKP16 Position   */
-#define GPIO_PORT_MASK6_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP16_Pos)                   /*!< GPIO_PORT MASK6: MASKP16 Mask       */
-#define GPIO_PORT_MASK6_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK6: MASKP17 Position   */
-#define GPIO_PORT_MASK6_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP17_Pos)                   /*!< GPIO_PORT MASK6: MASKP17 Mask       */
-#define GPIO_PORT_MASK6_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK6: MASKP18 Position   */
-#define GPIO_PORT_MASK6_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP18_Pos)                   /*!< GPIO_PORT MASK6: MASKP18 Mask       */
-#define GPIO_PORT_MASK6_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK6: MASKP19 Position   */
-#define GPIO_PORT_MASK6_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP19_Pos)                   /*!< GPIO_PORT MASK6: MASKP19 Mask       */
-#define GPIO_PORT_MASK6_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK6: MASKP20 Position   */
-#define GPIO_PORT_MASK6_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP20_Pos)                   /*!< GPIO_PORT MASK6: MASKP20 Mask       */
-#define GPIO_PORT_MASK6_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK6: MASKP21 Position   */
-#define GPIO_PORT_MASK6_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP21_Pos)                   /*!< GPIO_PORT MASK6: MASKP21 Mask       */
-#define GPIO_PORT_MASK6_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK6: MASKP22 Position   */
-#define GPIO_PORT_MASK6_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP22_Pos)                   /*!< GPIO_PORT MASK6: MASKP22 Mask       */
-#define GPIO_PORT_MASK6_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK6: MASKP23 Position   */
-#define GPIO_PORT_MASK6_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP23_Pos)                   /*!< GPIO_PORT MASK6: MASKP23 Mask       */
-#define GPIO_PORT_MASK6_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK6: MASKP24 Position   */
-#define GPIO_PORT_MASK6_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP24_Pos)                   /*!< GPIO_PORT MASK6: MASKP24 Mask       */
-#define GPIO_PORT_MASK6_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK6: MASKP25 Position   */
-#define GPIO_PORT_MASK6_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP25_Pos)                   /*!< GPIO_PORT MASK6: MASKP25 Mask       */
-#define GPIO_PORT_MASK6_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK6: MASKP26 Position   */
-#define GPIO_PORT_MASK6_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP26_Pos)                   /*!< GPIO_PORT MASK6: MASKP26 Mask       */
-#define GPIO_PORT_MASK6_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK6: MASKP27 Position   */
-#define GPIO_PORT_MASK6_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP27_Pos)                   /*!< GPIO_PORT MASK6: MASKP27 Mask       */
-#define GPIO_PORT_MASK6_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK6: MASKP28 Position   */
-#define GPIO_PORT_MASK6_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP28_Pos)                   /*!< GPIO_PORT MASK6: MASKP28 Mask       */
-#define GPIO_PORT_MASK6_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK6: MASKP29 Position   */
-#define GPIO_PORT_MASK6_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP29_Pos)                   /*!< GPIO_PORT MASK6: MASKP29 Mask       */
-#define GPIO_PORT_MASK6_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK6: MASKP30 Position   */
-#define GPIO_PORT_MASK6_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP30_Pos)                   /*!< GPIO_PORT MASK6: MASKP30 Mask       */
-#define GPIO_PORT_MASK6_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK6: MASKP31 Position   */
-#define GPIO_PORT_MASK6_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP31_Pos)                   /*!< GPIO_PORT MASK6: MASKP31 Mask       */
-
-// -------------------------------------  GPIO_PORT_MASK7  ----------------------------------------
-#define GPIO_PORT_MASK7_MASKP0_Pos                            0                                                         /*!< GPIO_PORT MASK7: MASKP0 Position    */
-#define GPIO_PORT_MASK7_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP0_Pos)                    /*!< GPIO_PORT MASK7: MASKP0 Mask        */
-#define GPIO_PORT_MASK7_MASKP1_Pos                            1                                                         /*!< GPIO_PORT MASK7: MASKP1 Position    */
-#define GPIO_PORT_MASK7_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP1_Pos)                    /*!< GPIO_PORT MASK7: MASKP1 Mask        */
-#define GPIO_PORT_MASK7_MASKP2_Pos                            2                                                         /*!< GPIO_PORT MASK7: MASKP2 Position    */
-#define GPIO_PORT_MASK7_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP2_Pos)                    /*!< GPIO_PORT MASK7: MASKP2 Mask        */
-#define GPIO_PORT_MASK7_MASKP3_Pos                            3                                                         /*!< GPIO_PORT MASK7: MASKP3 Position    */
-#define GPIO_PORT_MASK7_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP3_Pos)                    /*!< GPIO_PORT MASK7: MASKP3 Mask        */
-#define GPIO_PORT_MASK7_MASKP4_Pos                            4                                                         /*!< GPIO_PORT MASK7: MASKP4 Position    */
-#define GPIO_PORT_MASK7_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP4_Pos)                    /*!< GPIO_PORT MASK7: MASKP4 Mask        */
-#define GPIO_PORT_MASK7_MASKP5_Pos                            5                                                         /*!< GPIO_PORT MASK7: MASKP5 Position    */
-#define GPIO_PORT_MASK7_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP5_Pos)                    /*!< GPIO_PORT MASK7: MASKP5 Mask        */
-#define GPIO_PORT_MASK7_MASKP6_Pos                            6                                                         /*!< GPIO_PORT MASK7: MASKP6 Position    */
-#define GPIO_PORT_MASK7_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP6_Pos)                    /*!< GPIO_PORT MASK7: MASKP6 Mask        */
-#define GPIO_PORT_MASK7_MASKP7_Pos                            7                                                         /*!< GPIO_PORT MASK7: MASKP7 Position    */
-#define GPIO_PORT_MASK7_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP7_Pos)                    /*!< GPIO_PORT MASK7: MASKP7 Mask        */
-#define GPIO_PORT_MASK7_MASKP8_Pos                            8                                                         /*!< GPIO_PORT MASK7: MASKP8 Position    */
-#define GPIO_PORT_MASK7_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP8_Pos)                    /*!< GPIO_PORT MASK7: MASKP8 Mask        */
-#define GPIO_PORT_MASK7_MASKP9_Pos                            9                                                         /*!< GPIO_PORT MASK7: MASKP9 Position    */
-#define GPIO_PORT_MASK7_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP9_Pos)                    /*!< GPIO_PORT MASK7: MASKP9 Mask        */
-#define GPIO_PORT_MASK7_MASKP10_Pos                           10                                                        /*!< GPIO_PORT MASK7: MASKP10 Position   */
-#define GPIO_PORT_MASK7_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP10_Pos)                   /*!< GPIO_PORT MASK7: MASKP10 Mask       */
-#define GPIO_PORT_MASK7_MASKP11_Pos                           11                                                        /*!< GPIO_PORT MASK7: MASKP11 Position   */
-#define GPIO_PORT_MASK7_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP11_Pos)                   /*!< GPIO_PORT MASK7: MASKP11 Mask       */
-#define GPIO_PORT_MASK7_MASKP12_Pos                           12                                                        /*!< GPIO_PORT MASK7: MASKP12 Position   */
-#define GPIO_PORT_MASK7_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP12_Pos)                   /*!< GPIO_PORT MASK7: MASKP12 Mask       */
-#define GPIO_PORT_MASK7_MASKP13_Pos                           13                                                        /*!< GPIO_PORT MASK7: MASKP13 Position   */
-#define GPIO_PORT_MASK7_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP13_Pos)                   /*!< GPIO_PORT MASK7: MASKP13 Mask       */
-#define GPIO_PORT_MASK7_MASKP14_Pos                           14                                                        /*!< GPIO_PORT MASK7: MASKP14 Position   */
-#define GPIO_PORT_MASK7_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP14_Pos)                   /*!< GPIO_PORT MASK7: MASKP14 Mask       */
-#define GPIO_PORT_MASK7_MASKP15_Pos                           15                                                        /*!< GPIO_PORT MASK7: MASKP15 Position   */
-#define GPIO_PORT_MASK7_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP15_Pos)                   /*!< GPIO_PORT MASK7: MASKP15 Mask       */
-#define GPIO_PORT_MASK7_MASKP16_Pos                           16                                                        /*!< GPIO_PORT MASK7: MASKP16 Position   */
-#define GPIO_PORT_MASK7_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP16_Pos)                   /*!< GPIO_PORT MASK7: MASKP16 Mask       */
-#define GPIO_PORT_MASK7_MASKP17_Pos                           17                                                        /*!< GPIO_PORT MASK7: MASKP17 Position   */
-#define GPIO_PORT_MASK7_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP17_Pos)                   /*!< GPIO_PORT MASK7: MASKP17 Mask       */
-#define GPIO_PORT_MASK7_MASKP18_Pos                           18                                                        /*!< GPIO_PORT MASK7: MASKP18 Position   */
-#define GPIO_PORT_MASK7_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP18_Pos)                   /*!< GPIO_PORT MASK7: MASKP18 Mask       */
-#define GPIO_PORT_MASK7_MASKP19_Pos                           19                                                        /*!< GPIO_PORT MASK7: MASKP19 Position   */
-#define GPIO_PORT_MASK7_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP19_Pos)                   /*!< GPIO_PORT MASK7: MASKP19 Mask       */
-#define GPIO_PORT_MASK7_MASKP20_Pos                           20                                                        /*!< GPIO_PORT MASK7: MASKP20 Position   */
-#define GPIO_PORT_MASK7_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP20_Pos)                   /*!< GPIO_PORT MASK7: MASKP20 Mask       */
-#define GPIO_PORT_MASK7_MASKP21_Pos                           21                                                        /*!< GPIO_PORT MASK7: MASKP21 Position   */
-#define GPIO_PORT_MASK7_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP21_Pos)                   /*!< GPIO_PORT MASK7: MASKP21 Mask       */
-#define GPIO_PORT_MASK7_MASKP22_Pos                           22                                                        /*!< GPIO_PORT MASK7: MASKP22 Position   */
-#define GPIO_PORT_MASK7_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP22_Pos)                   /*!< GPIO_PORT MASK7: MASKP22 Mask       */
-#define GPIO_PORT_MASK7_MASKP23_Pos                           23                                                        /*!< GPIO_PORT MASK7: MASKP23 Position   */
-#define GPIO_PORT_MASK7_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP23_Pos)                   /*!< GPIO_PORT MASK7: MASKP23 Mask       */
-#define GPIO_PORT_MASK7_MASKP24_Pos                           24                                                        /*!< GPIO_PORT MASK7: MASKP24 Position   */
-#define GPIO_PORT_MASK7_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP24_Pos)                   /*!< GPIO_PORT MASK7: MASKP24 Mask       */
-#define GPIO_PORT_MASK7_MASKP25_Pos                           25                                                        /*!< GPIO_PORT MASK7: MASKP25 Position   */
-#define GPIO_PORT_MASK7_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP25_Pos)                   /*!< GPIO_PORT MASK7: MASKP25 Mask       */
-#define GPIO_PORT_MASK7_MASKP26_Pos                           26                                                        /*!< GPIO_PORT MASK7: MASKP26 Position   */
-#define GPIO_PORT_MASK7_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP26_Pos)                   /*!< GPIO_PORT MASK7: MASKP26 Mask       */
-#define GPIO_PORT_MASK7_MASKP27_Pos                           27                                                        /*!< GPIO_PORT MASK7: MASKP27 Position   */
-#define GPIO_PORT_MASK7_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP27_Pos)                   /*!< GPIO_PORT MASK7: MASKP27 Mask       */
-#define GPIO_PORT_MASK7_MASKP28_Pos                           28                                                        /*!< GPIO_PORT MASK7: MASKP28 Position   */
-#define GPIO_PORT_MASK7_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP28_Pos)                   /*!< GPIO_PORT MASK7: MASKP28 Mask       */
-#define GPIO_PORT_MASK7_MASKP29_Pos                           29                                                        /*!< GPIO_PORT MASK7: MASKP29 Position   */
-#define GPIO_PORT_MASK7_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP29_Pos)                   /*!< GPIO_PORT MASK7: MASKP29 Mask       */
-#define GPIO_PORT_MASK7_MASKP30_Pos                           30                                                        /*!< GPIO_PORT MASK7: MASKP30 Position   */
-#define GPIO_PORT_MASK7_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP30_Pos)                   /*!< GPIO_PORT MASK7: MASKP30 Mask       */
-#define GPIO_PORT_MASK7_MASKP31_Pos                           31                                                        /*!< GPIO_PORT MASK7: MASKP31 Position   */
-#define GPIO_PORT_MASK7_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP31_Pos)                   /*!< GPIO_PORT MASK7: MASKP31 Mask       */
-
-// -------------------------------------  GPIO_PORT_PIN0  -----------------------------------------
-#define GPIO_PORT_PIN0_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN0: PORT0 Position      */
-#define GPIO_PORT_PIN0_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT0_Pos)                      /*!< GPIO_PORT PIN0: PORT0 Mask          */
-#define GPIO_PORT_PIN0_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN0: PORT1 Position      */
-#define GPIO_PORT_PIN0_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT1_Pos)                      /*!< GPIO_PORT PIN0: PORT1 Mask          */
-#define GPIO_PORT_PIN0_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN0: PORT2 Position      */
-#define GPIO_PORT_PIN0_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT2_Pos)                      /*!< GPIO_PORT PIN0: PORT2 Mask          */
-#define GPIO_PORT_PIN0_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN0: PORT3 Position      */
-#define GPIO_PORT_PIN0_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT3_Pos)                      /*!< GPIO_PORT PIN0: PORT3 Mask          */
-#define GPIO_PORT_PIN0_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN0: PORT4 Position      */
-#define GPIO_PORT_PIN0_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT4_Pos)                      /*!< GPIO_PORT PIN0: PORT4 Mask          */
-#define GPIO_PORT_PIN0_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN0: PORT5 Position      */
-#define GPIO_PORT_PIN0_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT5_Pos)                      /*!< GPIO_PORT PIN0: PORT5 Mask          */
-#define GPIO_PORT_PIN0_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN0: PORT6 Position      */
-#define GPIO_PORT_PIN0_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT6_Pos)                      /*!< GPIO_PORT PIN0: PORT6 Mask          */
-#define GPIO_PORT_PIN0_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN0: PORT7 Position      */
-#define GPIO_PORT_PIN0_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT7_Pos)                      /*!< GPIO_PORT PIN0: PORT7 Mask          */
-#define GPIO_PORT_PIN0_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN0: PORT8 Position      */
-#define GPIO_PORT_PIN0_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT8_Pos)                      /*!< GPIO_PORT PIN0: PORT8 Mask          */
-#define GPIO_PORT_PIN0_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN0: PORT9 Position      */
-#define GPIO_PORT_PIN0_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT9_Pos)                      /*!< GPIO_PORT PIN0: PORT9 Mask          */
-#define GPIO_PORT_PIN0_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN0: PORT10 Position     */
-#define GPIO_PORT_PIN0_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT10_Pos)                     /*!< GPIO_PORT PIN0: PORT10 Mask         */
-#define GPIO_PORT_PIN0_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN0: PORT11 Position     */
-#define GPIO_PORT_PIN0_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT11_Pos)                     /*!< GPIO_PORT PIN0: PORT11 Mask         */
-#define GPIO_PORT_PIN0_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN0: PORT12 Position     */
-#define GPIO_PORT_PIN0_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT12_Pos)                     /*!< GPIO_PORT PIN0: PORT12 Mask         */
-#define GPIO_PORT_PIN0_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN0: PORT13 Position     */
-#define GPIO_PORT_PIN0_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT13_Pos)                     /*!< GPIO_PORT PIN0: PORT13 Mask         */
-#define GPIO_PORT_PIN0_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN0: PORT14 Position     */
-#define GPIO_PORT_PIN0_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT14_Pos)                     /*!< GPIO_PORT PIN0: PORT14 Mask         */
-#define GPIO_PORT_PIN0_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN0: PORT15 Position     */
-#define GPIO_PORT_PIN0_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT15_Pos)                     /*!< GPIO_PORT PIN0: PORT15 Mask         */
-#define GPIO_PORT_PIN0_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN0: PORT16 Position     */
-#define GPIO_PORT_PIN0_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT16_Pos)                     /*!< GPIO_PORT PIN0: PORT16 Mask         */
-#define GPIO_PORT_PIN0_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN0: PORT17 Position     */
-#define GPIO_PORT_PIN0_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT17_Pos)                     /*!< GPIO_PORT PIN0: PORT17 Mask         */
-#define GPIO_PORT_PIN0_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN0: PORT18 Position     */
-#define GPIO_PORT_PIN0_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT18_Pos)                     /*!< GPIO_PORT PIN0: PORT18 Mask         */
-#define GPIO_PORT_PIN0_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN0: PORT19 Position     */
-#define GPIO_PORT_PIN0_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT19_Pos)                     /*!< GPIO_PORT PIN0: PORT19 Mask         */
-#define GPIO_PORT_PIN0_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN0: PORT20 Position     */
-#define GPIO_PORT_PIN0_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT20_Pos)                     /*!< GPIO_PORT PIN0: PORT20 Mask         */
-#define GPIO_PORT_PIN0_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN0: PORT21 Position     */
-#define GPIO_PORT_PIN0_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT21_Pos)                     /*!< GPIO_PORT PIN0: PORT21 Mask         */
-#define GPIO_PORT_PIN0_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN0: PORT22 Position     */
-#define GPIO_PORT_PIN0_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT22_Pos)                     /*!< GPIO_PORT PIN0: PORT22 Mask         */
-#define GPIO_PORT_PIN0_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN0: PORT23 Position     */
-#define GPIO_PORT_PIN0_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT23_Pos)                     /*!< GPIO_PORT PIN0: PORT23 Mask         */
-#define GPIO_PORT_PIN0_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN0: PORT24 Position     */
-#define GPIO_PORT_PIN0_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT24_Pos)                     /*!< GPIO_PORT PIN0: PORT24 Mask         */
-#define GPIO_PORT_PIN0_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN0: PORT25 Position     */
-#define GPIO_PORT_PIN0_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT25_Pos)                     /*!< GPIO_PORT PIN0: PORT25 Mask         */
-#define GPIO_PORT_PIN0_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN0: PORT26 Position     */
-#define GPIO_PORT_PIN0_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT26_Pos)                     /*!< GPIO_PORT PIN0: PORT26 Mask         */
-#define GPIO_PORT_PIN0_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN0: PORT27 Position     */
-#define GPIO_PORT_PIN0_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT27_Pos)                     /*!< GPIO_PORT PIN0: PORT27 Mask         */
-#define GPIO_PORT_PIN0_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN0: PORT28 Position     */
-#define GPIO_PORT_PIN0_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT28_Pos)                     /*!< GPIO_PORT PIN0: PORT28 Mask         */
-#define GPIO_PORT_PIN0_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN0: PORT29 Position     */
-#define GPIO_PORT_PIN0_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT29_Pos)                     /*!< GPIO_PORT PIN0: PORT29 Mask         */
-#define GPIO_PORT_PIN0_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN0: PORT30 Position     */
-#define GPIO_PORT_PIN0_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT30_Pos)                     /*!< GPIO_PORT PIN0: PORT30 Mask         */
-#define GPIO_PORT_PIN0_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN0: PORT31 Position     */
-#define GPIO_PORT_PIN0_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT31_Pos)                     /*!< GPIO_PORT PIN0: PORT31 Mask         */
-
-// -------------------------------------  GPIO_PORT_PIN1  -----------------------------------------
-#define GPIO_PORT_PIN1_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN1: PORT0 Position      */
-#define GPIO_PORT_PIN1_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT0_Pos)                      /*!< GPIO_PORT PIN1: PORT0 Mask          */
-#define GPIO_PORT_PIN1_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN1: PORT1 Position      */
-#define GPIO_PORT_PIN1_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT1_Pos)                      /*!< GPIO_PORT PIN1: PORT1 Mask          */
-#define GPIO_PORT_PIN1_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN1: PORT2 Position      */
-#define GPIO_PORT_PIN1_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT2_Pos)                      /*!< GPIO_PORT PIN1: PORT2 Mask          */
-#define GPIO_PORT_PIN1_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN1: PORT3 Position      */
-#define GPIO_PORT_PIN1_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT3_Pos)                      /*!< GPIO_PORT PIN1: PORT3 Mask          */
-#define GPIO_PORT_PIN1_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN1: PORT4 Position      */
-#define GPIO_PORT_PIN1_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT4_Pos)                      /*!< GPIO_PORT PIN1: PORT4 Mask          */
-#define GPIO_PORT_PIN1_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN1: PORT5 Position      */
-#define GPIO_PORT_PIN1_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT5_Pos)                      /*!< GPIO_PORT PIN1: PORT5 Mask          */
-#define GPIO_PORT_PIN1_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN1: PORT6 Position      */
-#define GPIO_PORT_PIN1_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT6_Pos)                      /*!< GPIO_PORT PIN1: PORT6 Mask          */
-#define GPIO_PORT_PIN1_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN1: PORT7 Position      */
-#define GPIO_PORT_PIN1_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT7_Pos)                      /*!< GPIO_PORT PIN1: PORT7 Mask          */
-#define GPIO_PORT_PIN1_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN1: PORT8 Position      */
-#define GPIO_PORT_PIN1_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT8_Pos)                      /*!< GPIO_PORT PIN1: PORT8 Mask          */
-#define GPIO_PORT_PIN1_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN1: PORT9 Position      */
-#define GPIO_PORT_PIN1_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT9_Pos)                      /*!< GPIO_PORT PIN1: PORT9 Mask          */
-#define GPIO_PORT_PIN1_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN1: PORT10 Position     */
-#define GPIO_PORT_PIN1_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT10_Pos)                     /*!< GPIO_PORT PIN1: PORT10 Mask         */
-#define GPIO_PORT_PIN1_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN1: PORT11 Position     */
-#define GPIO_PORT_PIN1_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT11_Pos)                     /*!< GPIO_PORT PIN1: PORT11 Mask         */
-#define GPIO_PORT_PIN1_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN1: PORT12 Position     */
-#define GPIO_PORT_PIN1_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT12_Pos)                     /*!< GPIO_PORT PIN1: PORT12 Mask         */
-#define GPIO_PORT_PIN1_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN1: PORT13 Position     */
-#define GPIO_PORT_PIN1_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT13_Pos)                     /*!< GPIO_PORT PIN1: PORT13 Mask         */
-#define GPIO_PORT_PIN1_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN1: PORT14 Position     */
-#define GPIO_PORT_PIN1_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT14_Pos)                     /*!< GPIO_PORT PIN1: PORT14 Mask         */
-#define GPIO_PORT_PIN1_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN1: PORT15 Position     */
-#define GPIO_PORT_PIN1_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT15_Pos)                     /*!< GPIO_PORT PIN1: PORT15 Mask         */
-#define GPIO_PORT_PIN1_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN1: PORT16 Position     */
-#define GPIO_PORT_PIN1_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT16_Pos)                     /*!< GPIO_PORT PIN1: PORT16 Mask         */
-#define GPIO_PORT_PIN1_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN1: PORT17 Position     */
-#define GPIO_PORT_PIN1_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT17_Pos)                     /*!< GPIO_PORT PIN1: PORT17 Mask         */
-#define GPIO_PORT_PIN1_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN1: PORT18 Position     */
-#define GPIO_PORT_PIN1_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT18_Pos)                     /*!< GPIO_PORT PIN1: PORT18 Mask         */
-#define GPIO_PORT_PIN1_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN1: PORT19 Position     */
-#define GPIO_PORT_PIN1_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT19_Pos)                     /*!< GPIO_PORT PIN1: PORT19 Mask         */
-#define GPIO_PORT_PIN1_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN1: PORT20 Position     */
-#define GPIO_PORT_PIN1_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT20_Pos)                     /*!< GPIO_PORT PIN1: PORT20 Mask         */
-#define GPIO_PORT_PIN1_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN1: PORT21 Position     */
-#define GPIO_PORT_PIN1_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT21_Pos)                     /*!< GPIO_PORT PIN1: PORT21 Mask         */
-#define GPIO_PORT_PIN1_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN1: PORT22 Position     */
-#define GPIO_PORT_PIN1_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT22_Pos)                     /*!< GPIO_PORT PIN1: PORT22 Mask         */
-#define GPIO_PORT_PIN1_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN1: PORT23 Position     */
-#define GPIO_PORT_PIN1_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT23_Pos)                     /*!< GPIO_PORT PIN1: PORT23 Mask         */
-#define GPIO_PORT_PIN1_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN1: PORT24 Position     */
-#define GPIO_PORT_PIN1_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT24_Pos)                     /*!< GPIO_PORT PIN1: PORT24 Mask         */
-#define GPIO_PORT_PIN1_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN1: PORT25 Position     */
-#define GPIO_PORT_PIN1_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT25_Pos)                     /*!< GPIO_PORT PIN1: PORT25 Mask         */
-#define GPIO_PORT_PIN1_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN1: PORT26 Position     */
-#define GPIO_PORT_PIN1_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT26_Pos)                     /*!< GPIO_PORT PIN1: PORT26 Mask         */
-#define GPIO_PORT_PIN1_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN1: PORT27 Position     */
-#define GPIO_PORT_PIN1_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT27_Pos)                     /*!< GPIO_PORT PIN1: PORT27 Mask         */
-#define GPIO_PORT_PIN1_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN1: PORT28 Position     */
-#define GPIO_PORT_PIN1_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT28_Pos)                     /*!< GPIO_PORT PIN1: PORT28 Mask         */
-#define GPIO_PORT_PIN1_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN1: PORT29 Position     */
-#define GPIO_PORT_PIN1_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT29_Pos)                     /*!< GPIO_PORT PIN1: PORT29 Mask         */
-#define GPIO_PORT_PIN1_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN1: PORT30 Position     */
-#define GPIO_PORT_PIN1_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT30_Pos)                     /*!< GPIO_PORT PIN1: PORT30 Mask         */
-#define GPIO_PORT_PIN1_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN1: PORT31 Position     */
-#define GPIO_PORT_PIN1_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT31_Pos)                     /*!< GPIO_PORT PIN1: PORT31 Mask         */
-
-// -------------------------------------  GPIO_PORT_PIN2  -----------------------------------------
-#define GPIO_PORT_PIN2_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN2: PORT0 Position      */
-#define GPIO_PORT_PIN2_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT0_Pos)                      /*!< GPIO_PORT PIN2: PORT0 Mask          */
-#define GPIO_PORT_PIN2_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN2: PORT1 Position      */
-#define GPIO_PORT_PIN2_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT1_Pos)                      /*!< GPIO_PORT PIN2: PORT1 Mask          */
-#define GPIO_PORT_PIN2_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN2: PORT2 Position      */
-#define GPIO_PORT_PIN2_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT2_Pos)                      /*!< GPIO_PORT PIN2: PORT2 Mask          */
-#define GPIO_PORT_PIN2_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN2: PORT3 Position      */
-#define GPIO_PORT_PIN2_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT3_Pos)                      /*!< GPIO_PORT PIN2: PORT3 Mask          */
-#define GPIO_PORT_PIN2_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN2: PORT4 Position      */
-#define GPIO_PORT_PIN2_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT4_Pos)                      /*!< GPIO_PORT PIN2: PORT4 Mask          */
-#define GPIO_PORT_PIN2_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN2: PORT5 Position      */
-#define GPIO_PORT_PIN2_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT5_Pos)                      /*!< GPIO_PORT PIN2: PORT5 Mask          */
-#define GPIO_PORT_PIN2_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN2: PORT6 Position      */
-#define GPIO_PORT_PIN2_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT6_Pos)                      /*!< GPIO_PORT PIN2: PORT6 Mask          */
-#define GPIO_PORT_PIN2_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN2: PORT7 Position      */
-#define GPIO_PORT_PIN2_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT7_Pos)                      /*!< GPIO_PORT PIN2: PORT7 Mask          */
-#define GPIO_PORT_PIN2_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN2: PORT8 Position      */
-#define GPIO_PORT_PIN2_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT8_Pos)                      /*!< GPIO_PORT PIN2: PORT8 Mask          */
-#define GPIO_PORT_PIN2_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN2: PORT9 Position      */
-#define GPIO_PORT_PIN2_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT9_Pos)                      /*!< GPIO_PORT PIN2: PORT9 Mask          */
-#define GPIO_PORT_PIN2_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN2: PORT10 Position     */
-#define GPIO_PORT_PIN2_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT10_Pos)                     /*!< GPIO_PORT PIN2: PORT10 Mask         */
-#define GPIO_PORT_PIN2_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN2: PORT11 Position     */
-#define GPIO_PORT_PIN2_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT11_Pos)                     /*!< GPIO_PORT PIN2: PORT11 Mask         */
-#define GPIO_PORT_PIN2_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN2: PORT12 Position     */
-#define GPIO_PORT_PIN2_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT12_Pos)                     /*!< GPIO_PORT PIN2: PORT12 Mask         */
-#define GPIO_PORT_PIN2_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN2: PORT13 Position     */
-#define GPIO_PORT_PIN2_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT13_Pos)                     /*!< GPIO_PORT PIN2: PORT13 Mask         */
-#define GPIO_PORT_PIN2_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN2: PORT14 Position     */
-#define GPIO_PORT_PIN2_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT14_Pos)                     /*!< GPIO_PORT PIN2: PORT14 Mask         */
-#define GPIO_PORT_PIN2_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN2: PORT15 Position     */
-#define GPIO_PORT_PIN2_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT15_Pos)                     /*!< GPIO_PORT PIN2: PORT15 Mask         */
-#define GPIO_PORT_PIN2_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN2: PORT16 Position     */
-#define GPIO_PORT_PIN2_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT16_Pos)                     /*!< GPIO_PORT PIN2: PORT16 Mask         */
-#define GPIO_PORT_PIN2_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN2: PORT17 Position     */
-#define GPIO_PORT_PIN2_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT17_Pos)                     /*!< GPIO_PORT PIN2: PORT17 Mask         */
-#define GPIO_PORT_PIN2_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN2: PORT18 Position     */
-#define GPIO_PORT_PIN2_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT18_Pos)                     /*!< GPIO_PORT PIN2: PORT18 Mask         */
-#define GPIO_PORT_PIN2_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN2: PORT19 Position     */
-#define GPIO_PORT_PIN2_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT19_Pos)                     /*!< GPIO_PORT PIN2: PORT19 Mask         */
-#define GPIO_PORT_PIN2_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN2: PORT20 Position     */
-#define GPIO_PORT_PIN2_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT20_Pos)                     /*!< GPIO_PORT PIN2: PORT20 Mask         */
-#define GPIO_PORT_PIN2_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN2: PORT21 Position     */
-#define GPIO_PORT_PIN2_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT21_Pos)                     /*!< GPIO_PORT PIN2: PORT21 Mask         */
-#define GPIO_PORT_PIN2_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN2: PORT22 Position     */
-#define GPIO_PORT_PIN2_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT22_Pos)                     /*!< GPIO_PORT PIN2: PORT22 Mask         */
-#define GPIO_PORT_PIN2_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN2: PORT23 Position     */
-#define GPIO_PORT_PIN2_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT23_Pos)                     /*!< GPIO_PORT PIN2: PORT23 Mask         */
-#define GPIO_PORT_PIN2_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN2: PORT24 Position     */
-#define GPIO_PORT_PIN2_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT24_Pos)                     /*!< GPIO_PORT PIN2: PORT24 Mask         */
-#define GPIO_PORT_PIN2_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN2: PORT25 Position     */
-#define GPIO_PORT_PIN2_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT25_Pos)                     /*!< GPIO_PORT PIN2: PORT25 Mask         */
-#define GPIO_PORT_PIN2_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN2: PORT26 Position     */
-#define GPIO_PORT_PIN2_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT26_Pos)                     /*!< GPIO_PORT PIN2: PORT26 Mask         */
-#define GPIO_PORT_PIN2_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN2: PORT27 Position     */
-#define GPIO_PORT_PIN2_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT27_Pos)                     /*!< GPIO_PORT PIN2: PORT27 Mask         */
-#define GPIO_PORT_PIN2_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN2: PORT28 Position     */
-#define GPIO_PORT_PIN2_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT28_Pos)                     /*!< GPIO_PORT PIN2: PORT28 Mask         */
-#define GPIO_PORT_PIN2_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN2: PORT29 Position     */
-#define GPIO_PORT_PIN2_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT29_Pos)                     /*!< GPIO_PORT PIN2: PORT29 Mask         */
-#define GPIO_PORT_PIN2_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN2: PORT30 Position     */
-#define GPIO_PORT_PIN2_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT30_Pos)                     /*!< GPIO_PORT PIN2: PORT30 Mask         */
-#define GPIO_PORT_PIN2_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN2: PORT31 Position     */
-#define GPIO_PORT_PIN2_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT31_Pos)                     /*!< GPIO_PORT PIN2: PORT31 Mask         */
-
-// -------------------------------------  GPIO_PORT_PIN3  -----------------------------------------
-#define GPIO_PORT_PIN3_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN3: PORT0 Position      */
-#define GPIO_PORT_PIN3_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT0_Pos)                      /*!< GPIO_PORT PIN3: PORT0 Mask          */
-#define GPIO_PORT_PIN3_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN3: PORT1 Position      */
-#define GPIO_PORT_PIN3_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT1_Pos)                      /*!< GPIO_PORT PIN3: PORT1 Mask          */
-#define GPIO_PORT_PIN3_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN3: PORT2 Position      */
-#define GPIO_PORT_PIN3_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT2_Pos)                      /*!< GPIO_PORT PIN3: PORT2 Mask          */
-#define GPIO_PORT_PIN3_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN3: PORT3 Position      */
-#define GPIO_PORT_PIN3_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT3_Pos)                      /*!< GPIO_PORT PIN3: PORT3 Mask          */
-#define GPIO_PORT_PIN3_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN3: PORT4 Position      */
-#define GPIO_PORT_PIN3_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT4_Pos)                      /*!< GPIO_PORT PIN3: PORT4 Mask          */
-#define GPIO_PORT_PIN3_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN3: PORT5 Position      */
-#define GPIO_PORT_PIN3_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT5_Pos)                      /*!< GPIO_PORT PIN3: PORT5 Mask          */
-#define GPIO_PORT_PIN3_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN3: PORT6 Position      */
-#define GPIO_PORT_PIN3_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT6_Pos)                      /*!< GPIO_PORT PIN3: PORT6 Mask          */
-#define GPIO_PORT_PIN3_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN3: PORT7 Position      */
-#define GPIO_PORT_PIN3_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT7_Pos)                      /*!< GPIO_PORT PIN3: PORT7 Mask          */
-#define GPIO_PORT_PIN3_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN3: PORT8 Position      */
-#define GPIO_PORT_PIN3_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT8_Pos)                      /*!< GPIO_PORT PIN3: PORT8 Mask          */
-#define GPIO_PORT_PIN3_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN3: PORT9 Position      */
-#define GPIO_PORT_PIN3_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT9_Pos)                      /*!< GPIO_PORT PIN3: PORT9 Mask          */
-#define GPIO_PORT_PIN3_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN3: PORT10 Position     */
-#define GPIO_PORT_PIN3_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT10_Pos)                     /*!< GPIO_PORT PIN3: PORT10 Mask         */
-#define GPIO_PORT_PIN3_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN3: PORT11 Position     */
-#define GPIO_PORT_PIN3_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT11_Pos)                     /*!< GPIO_PORT PIN3: PORT11 Mask         */
-#define GPIO_PORT_PIN3_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN3: PORT12 Position     */
-#define GPIO_PORT_PIN3_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT12_Pos)                     /*!< GPIO_PORT PIN3: PORT12 Mask         */
-#define GPIO_PORT_PIN3_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN3: PORT13 Position     */
-#define GPIO_PORT_PIN3_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT13_Pos)                     /*!< GPIO_PORT PIN3: PORT13 Mask         */
-#define GPIO_PORT_PIN3_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN3: PORT14 Position     */
-#define GPIO_PORT_PIN3_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT14_Pos)                     /*!< GPIO_PORT PIN3: PORT14 Mask         */
-#define GPIO_PORT_PIN3_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN3: PORT15 Position     */
-#define GPIO_PORT_PIN3_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT15_Pos)                     /*!< GPIO_PORT PIN3: PORT15 Mask         */
-#define GPIO_PORT_PIN3_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN3: PORT16 Position     */
-#define GPIO_PORT_PIN3_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT16_Pos)                     /*!< GPIO_PORT PIN3: PORT16 Mask         */
-#define GPIO_PORT_PIN3_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN3: PORT17 Position     */
-#define GPIO_PORT_PIN3_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT17_Pos)                     /*!< GPIO_PORT PIN3: PORT17 Mask         */
-#define GPIO_PORT_PIN3_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN3: PORT18 Position     */
-#define GPIO_PORT_PIN3_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT18_Pos)                     /*!< GPIO_PORT PIN3: PORT18 Mask         */
-#define GPIO_PORT_PIN3_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN3: PORT19 Position     */
-#define GPIO_PORT_PIN3_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT19_Pos)                     /*!< GPIO_PORT PIN3: PORT19 Mask         */
-#define GPIO_PORT_PIN3_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN3: PORT20 Position     */
-#define GPIO_PORT_PIN3_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT20_Pos)                     /*!< GPIO_PORT PIN3: PORT20 Mask         */
-#define GPIO_PORT_PIN3_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN3: PORT21 Position     */
-#define GPIO_PORT_PIN3_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT21_Pos)                     /*!< GPIO_PORT PIN3: PORT21 Mask         */
-#define GPIO_PORT_PIN3_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN3: PORT22 Position     */
-#define GPIO_PORT_PIN3_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT22_Pos)                     /*!< GPIO_PORT PIN3: PORT22 Mask         */
-#define GPIO_PORT_PIN3_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN3: PORT23 Position     */
-#define GPIO_PORT_PIN3_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT23_Pos)                     /*!< GPIO_PORT PIN3: PORT23 Mask         */
-#define GPIO_PORT_PIN3_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN3: PORT24 Position     */
-#define GPIO_PORT_PIN3_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT24_Pos)                     /*!< GPIO_PORT PIN3: PORT24 Mask         */
-#define GPIO_PORT_PIN3_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN3: PORT25 Position     */
-#define GPIO_PORT_PIN3_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT25_Pos)                     /*!< GPIO_PORT PIN3: PORT25 Mask         */
-#define GPIO_PORT_PIN3_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN3: PORT26 Position     */
-#define GPIO_PORT_PIN3_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT26_Pos)                     /*!< GPIO_PORT PIN3: PORT26 Mask         */
-#define GPIO_PORT_PIN3_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN3: PORT27 Position     */
-#define GPIO_PORT_PIN3_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT27_Pos)                     /*!< GPIO_PORT PIN3: PORT27 Mask         */
-#define GPIO_PORT_PIN3_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN3: PORT28 Position     */
-#define GPIO_PORT_PIN3_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT28_Pos)                     /*!< GPIO_PORT PIN3: PORT28 Mask         */
-#define GPIO_PORT_PIN3_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN3: PORT29 Position     */
-#define GPIO_PORT_PIN3_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT29_Pos)                     /*!< GPIO_PORT PIN3: PORT29 Mask         */
-#define GPIO_PORT_PIN3_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN3: PORT30 Position     */
-#define GPIO_PORT_PIN3_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT30_Pos)                     /*!< GPIO_PORT PIN3: PORT30 Mask         */
-#define GPIO_PORT_PIN3_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN3: PORT31 Position     */
-#define GPIO_PORT_PIN3_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT31_Pos)                     /*!< GPIO_PORT PIN3: PORT31 Mask         */
-
-// -------------------------------------  GPIO_PORT_PIN4  -----------------------------------------
-#define GPIO_PORT_PIN4_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN4: PORT0 Position      */
-#define GPIO_PORT_PIN4_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT0_Pos)                      /*!< GPIO_PORT PIN4: PORT0 Mask          */
-#define GPIO_PORT_PIN4_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN4: PORT1 Position      */
-#define GPIO_PORT_PIN4_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT1_Pos)                      /*!< GPIO_PORT PIN4: PORT1 Mask          */
-#define GPIO_PORT_PIN4_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN4: PORT2 Position      */
-#define GPIO_PORT_PIN4_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT2_Pos)                      /*!< GPIO_PORT PIN4: PORT2 Mask          */
-#define GPIO_PORT_PIN4_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN4: PORT3 Position      */
-#define GPIO_PORT_PIN4_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT3_Pos)                      /*!< GPIO_PORT PIN4: PORT3 Mask          */
-#define GPIO_PORT_PIN4_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN4: PORT4 Position      */
-#define GPIO_PORT_PIN4_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT4_Pos)                      /*!< GPIO_PORT PIN4: PORT4 Mask          */
-#define GPIO_PORT_PIN4_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN4: PORT5 Position      */
-#define GPIO_PORT_PIN4_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT5_Pos)                      /*!< GPIO_PORT PIN4: PORT5 Mask          */
-#define GPIO_PORT_PIN4_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN4: PORT6 Position      */
-#define GPIO_PORT_PIN4_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT6_Pos)                      /*!< GPIO_PORT PIN4: PORT6 Mask          */
-#define GPIO_PORT_PIN4_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN4: PORT7 Position      */
-#define GPIO_PORT_PIN4_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT7_Pos)                      /*!< GPIO_PORT PIN4: PORT7 Mask          */
-#define GPIO_PORT_PIN4_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN4: PORT8 Position      */
-#define GPIO_PORT_PIN4_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT8_Pos)                      /*!< GPIO_PORT PIN4: PORT8 Mask          */
-#define GPIO_PORT_PIN4_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN4: PORT9 Position      */
-#define GPIO_PORT_PIN4_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT9_Pos)                      /*!< GPIO_PORT PIN4: PORT9 Mask          */
-#define GPIO_PORT_PIN4_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN4: PORT10 Position     */
-#define GPIO_PORT_PIN4_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT10_Pos)                     /*!< GPIO_PORT PIN4: PORT10 Mask         */
-#define GPIO_PORT_PIN4_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN4: PORT11 Position     */
-#define GPIO_PORT_PIN4_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT11_Pos)                     /*!< GPIO_PORT PIN4: PORT11 Mask         */
-#define GPIO_PORT_PIN4_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN4: PORT12 Position     */
-#define GPIO_PORT_PIN4_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT12_Pos)                     /*!< GPIO_PORT PIN4: PORT12 Mask         */
-#define GPIO_PORT_PIN4_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN4: PORT13 Position     */
-#define GPIO_PORT_PIN4_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT13_Pos)                     /*!< GPIO_PORT PIN4: PORT13 Mask         */
-#define GPIO_PORT_PIN4_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN4: PORT14 Position     */
-#define GPIO_PORT_PIN4_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT14_Pos)                     /*!< GPIO_PORT PIN4: PORT14 Mask         */
-#define GPIO_PORT_PIN4_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN4: PORT15 Position     */
-#define GPIO_PORT_PIN4_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT15_Pos)                     /*!< GPIO_PORT PIN4: PORT15 Mask         */
-#define GPIO_PORT_PIN4_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN4: PORT16 Position     */
-#define GPIO_PORT_PIN4_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT16_Pos)                     /*!< GPIO_PORT PIN4: PORT16 Mask         */
-#define GPIO_PORT_PIN4_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN4: PORT17 Position     */
-#define GPIO_PORT_PIN4_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT17_Pos)                     /*!< GPIO_PORT PIN4: PORT17 Mask         */
-#define GPIO_PORT_PIN4_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN4: PORT18 Position     */
-#define GPIO_PORT_PIN4_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT18_Pos)                     /*!< GPIO_PORT PIN4: PORT18 Mask         */
-#define GPIO_PORT_PIN4_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN4: PORT19 Position     */
-#define GPIO_PORT_PIN4_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT19_Pos)                     /*!< GPIO_PORT PIN4: PORT19 Mask         */
-#define GPIO_PORT_PIN4_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN4: PORT20 Position     */
-#define GPIO_PORT_PIN4_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT20_Pos)                     /*!< GPIO_PORT PIN4: PORT20 Mask         */
-#define GPIO_PORT_PIN4_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN4: PORT21 Position     */
-#define GPIO_PORT_PIN4_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT21_Pos)                     /*!< GPIO_PORT PIN4: PORT21 Mask         */
-#define GPIO_PORT_PIN4_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN4: PORT22 Position     */
-#define GPIO_PORT_PIN4_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT22_Pos)                     /*!< GPIO_PORT PIN4: PORT22 Mask         */
-#define GPIO_PORT_PIN4_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN4: PORT23 Position     */
-#define GPIO_PORT_PIN4_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT23_Pos)                     /*!< GPIO_PORT PIN4: PORT23 Mask         */
-#define GPIO_PORT_PIN4_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN4: PORT24 Position     */
-#define GPIO_PORT_PIN4_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT24_Pos)                     /*!< GPIO_PORT PIN4: PORT24 Mask         */
-#define GPIO_PORT_PIN4_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN4: PORT25 Position     */
-#define GPIO_PORT_PIN4_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT25_Pos)                     /*!< GPIO_PORT PIN4: PORT25 Mask         */
-#define GPIO_PORT_PIN4_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN4: PORT26 Position     */
-#define GPIO_PORT_PIN4_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT26_Pos)                     /*!< GPIO_PORT PIN4: PORT26 Mask         */
-#define GPIO_PORT_PIN4_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN4: PORT27 Position     */
-#define GPIO_PORT_PIN4_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT27_Pos)                     /*!< GPIO_PORT PIN4: PORT27 Mask         */
-#define GPIO_PORT_PIN4_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN4: PORT28 Position     */
-#define GPIO_PORT_PIN4_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT28_Pos)                     /*!< GPIO_PORT PIN4: PORT28 Mask         */
-#define GPIO_PORT_PIN4_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN4: PORT29 Position     */
-#define GPIO_PORT_PIN4_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT29_Pos)                     /*!< GPIO_PORT PIN4: PORT29 Mask         */
-#define GPIO_PORT_PIN4_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN4: PORT30 Position     */
-#define GPIO_PORT_PIN4_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT30_Pos)                     /*!< GPIO_PORT PIN4: PORT30 Mask         */
-#define GPIO_PORT_PIN4_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN4: PORT31 Position     */
-#define GPIO_PORT_PIN4_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT31_Pos)                     /*!< GPIO_PORT PIN4: PORT31 Mask         */
-
-// -------------------------------------  GPIO_PORT_PIN5  -----------------------------------------
-#define GPIO_PORT_PIN5_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN5: PORT0 Position      */
-#define GPIO_PORT_PIN5_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT0_Pos)                      /*!< GPIO_PORT PIN5: PORT0 Mask          */
-#define GPIO_PORT_PIN5_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN5: PORT1 Position      */
-#define GPIO_PORT_PIN5_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT1_Pos)                      /*!< GPIO_PORT PIN5: PORT1 Mask          */
-#define GPIO_PORT_PIN5_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN5: PORT2 Position      */
-#define GPIO_PORT_PIN5_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT2_Pos)                      /*!< GPIO_PORT PIN5: PORT2 Mask          */
-#define GPIO_PORT_PIN5_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN5: PORT3 Position      */
-#define GPIO_PORT_PIN5_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT3_Pos)                      /*!< GPIO_PORT PIN5: PORT3 Mask          */
-#define GPIO_PORT_PIN5_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN5: PORT4 Position      */
-#define GPIO_PORT_PIN5_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT4_Pos)                      /*!< GPIO_PORT PIN5: PORT4 Mask          */
-#define GPIO_PORT_PIN5_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN5: PORT5 Position      */
-#define GPIO_PORT_PIN5_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT5_Pos)                      /*!< GPIO_PORT PIN5: PORT5 Mask          */
-#define GPIO_PORT_PIN5_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN5: PORT6 Position      */
-#define GPIO_PORT_PIN5_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT6_Pos)                      /*!< GPIO_PORT PIN5: PORT6 Mask          */
-#define GPIO_PORT_PIN5_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN5: PORT7 Position      */
-#define GPIO_PORT_PIN5_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT7_Pos)                      /*!< GPIO_PORT PIN5: PORT7 Mask          */
-#define GPIO_PORT_PIN5_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN5: PORT8 Position      */
-#define GPIO_PORT_PIN5_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT8_Pos)                      /*!< GPIO_PORT PIN5: PORT8 Mask          */
-#define GPIO_PORT_PIN5_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN5: PORT9 Position      */
-#define GPIO_PORT_PIN5_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT9_Pos)                      /*!< GPIO_PORT PIN5: PORT9 Mask          */
-#define GPIO_PORT_PIN5_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN5: PORT10 Position     */
-#define GPIO_PORT_PIN5_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT10_Pos)                     /*!< GPIO_PORT PIN5: PORT10 Mask         */
-#define GPIO_PORT_PIN5_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN5: PORT11 Position     */
-#define GPIO_PORT_PIN5_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT11_Pos)                     /*!< GPIO_PORT PIN5: PORT11 Mask         */
-#define GPIO_PORT_PIN5_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN5: PORT12 Position     */
-#define GPIO_PORT_PIN5_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT12_Pos)                     /*!< GPIO_PORT PIN5: PORT12 Mask         */
-#define GPIO_PORT_PIN5_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN5: PORT13 Position     */
-#define GPIO_PORT_PIN5_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT13_Pos)                     /*!< GPIO_PORT PIN5: PORT13 Mask         */
-#define GPIO_PORT_PIN5_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN5: PORT14 Position     */
-#define GPIO_PORT_PIN5_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT14_Pos)                     /*!< GPIO_PORT PIN5: PORT14 Mask         */
-#define GPIO_PORT_PIN5_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN5: PORT15 Position     */
-#define GPIO_PORT_PIN5_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT15_Pos)                     /*!< GPIO_PORT PIN5: PORT15 Mask         */
-#define GPIO_PORT_PIN5_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN5: PORT16 Position     */
-#define GPIO_PORT_PIN5_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT16_Pos)                     /*!< GPIO_PORT PIN5: PORT16 Mask         */
-#define GPIO_PORT_PIN5_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN5: PORT17 Position     */
-#define GPIO_PORT_PIN5_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT17_Pos)                     /*!< GPIO_PORT PIN5: PORT17 Mask         */
-#define GPIO_PORT_PIN5_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN5: PORT18 Position     */
-#define GPIO_PORT_PIN5_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT18_Pos)                     /*!< GPIO_PORT PIN5: PORT18 Mask         */
-#define GPIO_PORT_PIN5_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN5: PORT19 Position     */
-#define GPIO_PORT_PIN5_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT19_Pos)                     /*!< GPIO_PORT PIN5: PORT19 Mask         */
-#define GPIO_PORT_PIN5_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN5: PORT20 Position     */
-#define GPIO_PORT_PIN5_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT20_Pos)                     /*!< GPIO_PORT PIN5: PORT20 Mask         */
-#define GPIO_PORT_PIN5_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN5: PORT21 Position     */
-#define GPIO_PORT_PIN5_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT21_Pos)                     /*!< GPIO_PORT PIN5: PORT21 Mask         */
-#define GPIO_PORT_PIN5_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN5: PORT22 Position     */
-#define GPIO_PORT_PIN5_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT22_Pos)                     /*!< GPIO_PORT PIN5: PORT22 Mask         */
-#define GPIO_PORT_PIN5_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN5: PORT23 Position     */
-#define GPIO_PORT_PIN5_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT23_Pos)                     /*!< GPIO_PORT PIN5: PORT23 Mask         */
-#define GPIO_PORT_PIN5_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN5: PORT24 Position     */
-#define GPIO_PORT_PIN5_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT24_Pos)                     /*!< GPIO_PORT PIN5: PORT24 Mask         */
-#define GPIO_PORT_PIN5_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN5: PORT25 Position     */
-#define GPIO_PORT_PIN5_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT25_Pos)                     /*!< GPIO_PORT PIN5: PORT25 Mask         */
-#define GPIO_PORT_PIN5_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN5: PORT26 Position     */
-#define GPIO_PORT_PIN5_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT26_Pos)                     /*!< GPIO_PORT PIN5: PORT26 Mask         */
-#define GPIO_PORT_PIN5_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN5: PORT27 Position     */
-#define GPIO_PORT_PIN5_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT27_Pos)                     /*!< GPIO_PORT PIN5: PORT27 Mask         */
-#define GPIO_PORT_PIN5_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN5: PORT28 Position     */
-#define GPIO_PORT_PIN5_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT28_Pos)                     /*!< GPIO_PORT PIN5: PORT28 Mask         */
-#define GPIO_PORT_PIN5_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN5: PORT29 Position     */
-#define GPIO_PORT_PIN5_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT29_Pos)                     /*!< GPIO_PORT PIN5: PORT29 Mask         */
-#define GPIO_PORT_PIN5_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN5: PORT30 Position     */
-#define GPIO_PORT_PIN5_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT30_Pos)                     /*!< GPIO_PORT PIN5: PORT30 Mask         */
-#define GPIO_PORT_PIN5_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN5: PORT31 Position     */
-#define GPIO_PORT_PIN5_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT31_Pos)                     /*!< GPIO_PORT PIN5: PORT31 Mask         */
-
-// -------------------------------------  GPIO_PORT_PIN6  -----------------------------------------
-#define GPIO_PORT_PIN6_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN6: PORT0 Position      */
-#define GPIO_PORT_PIN6_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT0_Pos)                      /*!< GPIO_PORT PIN6: PORT0 Mask          */
-#define GPIO_PORT_PIN6_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN6: PORT1 Position      */
-#define GPIO_PORT_PIN6_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT1_Pos)                      /*!< GPIO_PORT PIN6: PORT1 Mask          */
-#define GPIO_PORT_PIN6_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN6: PORT2 Position      */
-#define GPIO_PORT_PIN6_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT2_Pos)                      /*!< GPIO_PORT PIN6: PORT2 Mask          */
-#define GPIO_PORT_PIN6_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN6: PORT3 Position      */
-#define GPIO_PORT_PIN6_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT3_Pos)                      /*!< GPIO_PORT PIN6: PORT3 Mask          */
-#define GPIO_PORT_PIN6_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN6: PORT4 Position      */
-#define GPIO_PORT_PIN6_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT4_Pos)                      /*!< GPIO_PORT PIN6: PORT4 Mask          */
-#define GPIO_PORT_PIN6_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN6: PORT5 Position      */
-#define GPIO_PORT_PIN6_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT5_Pos)                      /*!< GPIO_PORT PIN6: PORT5 Mask          */
-#define GPIO_PORT_PIN6_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN6: PORT6 Position      */
-#define GPIO_PORT_PIN6_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT6_Pos)                      /*!< GPIO_PORT PIN6: PORT6 Mask          */
-#define GPIO_PORT_PIN6_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN6: PORT7 Position      */
-#define GPIO_PORT_PIN6_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT7_Pos)                      /*!< GPIO_PORT PIN6: PORT7 Mask          */
-#define GPIO_PORT_PIN6_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN6: PORT8 Position      */
-#define GPIO_PORT_PIN6_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT8_Pos)                      /*!< GPIO_PORT PIN6: PORT8 Mask          */
-#define GPIO_PORT_PIN6_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN6: PORT9 Position      */
-#define GPIO_PORT_PIN6_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT9_Pos)                      /*!< GPIO_PORT PIN6: PORT9 Mask          */
-#define GPIO_PORT_PIN6_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN6: PORT10 Position     */
-#define GPIO_PORT_PIN6_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT10_Pos)                     /*!< GPIO_PORT PIN6: PORT10 Mask         */
-#define GPIO_PORT_PIN6_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN6: PORT11 Position     */
-#define GPIO_PORT_PIN6_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT11_Pos)                     /*!< GPIO_PORT PIN6: PORT11 Mask         */
-#define GPIO_PORT_PIN6_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN6: PORT12 Position     */
-#define GPIO_PORT_PIN6_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT12_Pos)                     /*!< GPIO_PORT PIN6: PORT12 Mask         */
-#define GPIO_PORT_PIN6_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN6: PORT13 Position     */
-#define GPIO_PORT_PIN6_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT13_Pos)                     /*!< GPIO_PORT PIN6: PORT13 Mask         */
-#define GPIO_PORT_PIN6_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN6: PORT14 Position     */
-#define GPIO_PORT_PIN6_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT14_Pos)                     /*!< GPIO_PORT PIN6: PORT14 Mask         */
-#define GPIO_PORT_PIN6_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN6: PORT15 Position     */
-#define GPIO_PORT_PIN6_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT15_Pos)                     /*!< GPIO_PORT PIN6: PORT15 Mask         */
-#define GPIO_PORT_PIN6_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN6: PORT16 Position     */
-#define GPIO_PORT_PIN6_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT16_Pos)                     /*!< GPIO_PORT PIN6: PORT16 Mask         */
-#define GPIO_PORT_PIN6_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN6: PORT17 Position     */
-#define GPIO_PORT_PIN6_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT17_Pos)                     /*!< GPIO_PORT PIN6: PORT17 Mask         */
-#define GPIO_PORT_PIN6_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN6: PORT18 Position     */
-#define GPIO_PORT_PIN6_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT18_Pos)                     /*!< GPIO_PORT PIN6: PORT18 Mask         */
-#define GPIO_PORT_PIN6_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN6: PORT19 Position     */
-#define GPIO_PORT_PIN6_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT19_Pos)                     /*!< GPIO_PORT PIN6: PORT19 Mask         */
-#define GPIO_PORT_PIN6_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN6: PORT20 Position     */
-#define GPIO_PORT_PIN6_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT20_Pos)                     /*!< GPIO_PORT PIN6: PORT20 Mask         */
-#define GPIO_PORT_PIN6_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN6: PORT21 Position     */
-#define GPIO_PORT_PIN6_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT21_Pos)                     /*!< GPIO_PORT PIN6: PORT21 Mask         */
-#define GPIO_PORT_PIN6_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN6: PORT22 Position     */
-#define GPIO_PORT_PIN6_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT22_Pos)                     /*!< GPIO_PORT PIN6: PORT22 Mask         */
-#define GPIO_PORT_PIN6_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN6: PORT23 Position     */
-#define GPIO_PORT_PIN6_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT23_Pos)                     /*!< GPIO_PORT PIN6: PORT23 Mask         */
-#define GPIO_PORT_PIN6_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN6: PORT24 Position     */
-#define GPIO_PORT_PIN6_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT24_Pos)                     /*!< GPIO_PORT PIN6: PORT24 Mask         */
-#define GPIO_PORT_PIN6_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN6: PORT25 Position     */
-#define GPIO_PORT_PIN6_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT25_Pos)                     /*!< GPIO_PORT PIN6: PORT25 Mask         */
-#define GPIO_PORT_PIN6_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN6: PORT26 Position     */
-#define GPIO_PORT_PIN6_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT26_Pos)                     /*!< GPIO_PORT PIN6: PORT26 Mask         */
-#define GPIO_PORT_PIN6_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN6: PORT27 Position     */
-#define GPIO_PORT_PIN6_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT27_Pos)                     /*!< GPIO_PORT PIN6: PORT27 Mask         */
-#define GPIO_PORT_PIN6_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN6: PORT28 Position     */
-#define GPIO_PORT_PIN6_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT28_Pos)                     /*!< GPIO_PORT PIN6: PORT28 Mask         */
-#define GPIO_PORT_PIN6_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN6: PORT29 Position     */
-#define GPIO_PORT_PIN6_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT29_Pos)                     /*!< GPIO_PORT PIN6: PORT29 Mask         */
-#define GPIO_PORT_PIN6_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN6: PORT30 Position     */
-#define GPIO_PORT_PIN6_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT30_Pos)                     /*!< GPIO_PORT PIN6: PORT30 Mask         */
-#define GPIO_PORT_PIN6_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN6: PORT31 Position     */
-#define GPIO_PORT_PIN6_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT31_Pos)                     /*!< GPIO_PORT PIN6: PORT31 Mask         */
-
-// -------------------------------------  GPIO_PORT_PIN7  -----------------------------------------
-#define GPIO_PORT_PIN7_PORT0_Pos                              0                                                         /*!< GPIO_PORT PIN7: PORT0 Position      */
-#define GPIO_PORT_PIN7_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT0_Pos)                      /*!< GPIO_PORT PIN7: PORT0 Mask          */
-#define GPIO_PORT_PIN7_PORT1_Pos                              1                                                         /*!< GPIO_PORT PIN7: PORT1 Position      */
-#define GPIO_PORT_PIN7_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT1_Pos)                      /*!< GPIO_PORT PIN7: PORT1 Mask          */
-#define GPIO_PORT_PIN7_PORT2_Pos                              2                                                         /*!< GPIO_PORT PIN7: PORT2 Position      */
-#define GPIO_PORT_PIN7_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT2_Pos)                      /*!< GPIO_PORT PIN7: PORT2 Mask          */
-#define GPIO_PORT_PIN7_PORT3_Pos                              3                                                         /*!< GPIO_PORT PIN7: PORT3 Position      */
-#define GPIO_PORT_PIN7_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT3_Pos)                      /*!< GPIO_PORT PIN7: PORT3 Mask          */
-#define GPIO_PORT_PIN7_PORT4_Pos                              4                                                         /*!< GPIO_PORT PIN7: PORT4 Position      */
-#define GPIO_PORT_PIN7_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT4_Pos)                      /*!< GPIO_PORT PIN7: PORT4 Mask          */
-#define GPIO_PORT_PIN7_PORT5_Pos                              5                                                         /*!< GPIO_PORT PIN7: PORT5 Position      */
-#define GPIO_PORT_PIN7_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT5_Pos)                      /*!< GPIO_PORT PIN7: PORT5 Mask          */
-#define GPIO_PORT_PIN7_PORT6_Pos                              6                                                         /*!< GPIO_PORT PIN7: PORT6 Position      */
-#define GPIO_PORT_PIN7_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT6_Pos)                      /*!< GPIO_PORT PIN7: PORT6 Mask          */
-#define GPIO_PORT_PIN7_PORT7_Pos                              7                                                         /*!< GPIO_PORT PIN7: PORT7 Position      */
-#define GPIO_PORT_PIN7_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT7_Pos)                      /*!< GPIO_PORT PIN7: PORT7 Mask          */
-#define GPIO_PORT_PIN7_PORT8_Pos                              8                                                         /*!< GPIO_PORT PIN7: PORT8 Position      */
-#define GPIO_PORT_PIN7_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT8_Pos)                      /*!< GPIO_PORT PIN7: PORT8 Mask          */
-#define GPIO_PORT_PIN7_PORT9_Pos                              9                                                         /*!< GPIO_PORT PIN7: PORT9 Position      */
-#define GPIO_PORT_PIN7_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT9_Pos)                      /*!< GPIO_PORT PIN7: PORT9 Mask          */
-#define GPIO_PORT_PIN7_PORT10_Pos                             10                                                        /*!< GPIO_PORT PIN7: PORT10 Position     */
-#define GPIO_PORT_PIN7_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT10_Pos)                     /*!< GPIO_PORT PIN7: PORT10 Mask         */
-#define GPIO_PORT_PIN7_PORT11_Pos                             11                                                        /*!< GPIO_PORT PIN7: PORT11 Position     */
-#define GPIO_PORT_PIN7_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT11_Pos)                     /*!< GPIO_PORT PIN7: PORT11 Mask         */
-#define GPIO_PORT_PIN7_PORT12_Pos                             12                                                        /*!< GPIO_PORT PIN7: PORT12 Position     */
-#define GPIO_PORT_PIN7_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT12_Pos)                     /*!< GPIO_PORT PIN7: PORT12 Mask         */
-#define GPIO_PORT_PIN7_PORT13_Pos                             13                                                        /*!< GPIO_PORT PIN7: PORT13 Position     */
-#define GPIO_PORT_PIN7_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT13_Pos)                     /*!< GPIO_PORT PIN7: PORT13 Mask         */
-#define GPIO_PORT_PIN7_PORT14_Pos                             14                                                        /*!< GPIO_PORT PIN7: PORT14 Position     */
-#define GPIO_PORT_PIN7_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT14_Pos)                     /*!< GPIO_PORT PIN7: PORT14 Mask         */
-#define GPIO_PORT_PIN7_PORT15_Pos                             15                                                        /*!< GPIO_PORT PIN7: PORT15 Position     */
-#define GPIO_PORT_PIN7_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT15_Pos)                     /*!< GPIO_PORT PIN7: PORT15 Mask         */
-#define GPIO_PORT_PIN7_PORT16_Pos                             16                                                        /*!< GPIO_PORT PIN7: PORT16 Position     */
-#define GPIO_PORT_PIN7_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT16_Pos)                     /*!< GPIO_PORT PIN7: PORT16 Mask         */
-#define GPIO_PORT_PIN7_PORT17_Pos                             17                                                        /*!< GPIO_PORT PIN7: PORT17 Position     */
-#define GPIO_PORT_PIN7_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT17_Pos)                     /*!< GPIO_PORT PIN7: PORT17 Mask         */
-#define GPIO_PORT_PIN7_PORT18_Pos                             18                                                        /*!< GPIO_PORT PIN7: PORT18 Position     */
-#define GPIO_PORT_PIN7_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT18_Pos)                     /*!< GPIO_PORT PIN7: PORT18 Mask         */
-#define GPIO_PORT_PIN7_PORT19_Pos                             19                                                        /*!< GPIO_PORT PIN7: PORT19 Position     */
-#define GPIO_PORT_PIN7_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT19_Pos)                     /*!< GPIO_PORT PIN7: PORT19 Mask         */
-#define GPIO_PORT_PIN7_PORT20_Pos                             20                                                        /*!< GPIO_PORT PIN7: PORT20 Position     */
-#define GPIO_PORT_PIN7_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT20_Pos)                     /*!< GPIO_PORT PIN7: PORT20 Mask         */
-#define GPIO_PORT_PIN7_PORT21_Pos                             21                                                        /*!< GPIO_PORT PIN7: PORT21 Position     */
-#define GPIO_PORT_PIN7_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT21_Pos)                     /*!< GPIO_PORT PIN7: PORT21 Mask         */
-#define GPIO_PORT_PIN7_PORT22_Pos                             22                                                        /*!< GPIO_PORT PIN7: PORT22 Position     */
-#define GPIO_PORT_PIN7_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT22_Pos)                     /*!< GPIO_PORT PIN7: PORT22 Mask         */
-#define GPIO_PORT_PIN7_PORT23_Pos                             23                                                        /*!< GPIO_PORT PIN7: PORT23 Position     */
-#define GPIO_PORT_PIN7_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT23_Pos)                     /*!< GPIO_PORT PIN7: PORT23 Mask         */
-#define GPIO_PORT_PIN7_PORT24_Pos                             24                                                        /*!< GPIO_PORT PIN7: PORT24 Position     */
-#define GPIO_PORT_PIN7_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT24_Pos)                     /*!< GPIO_PORT PIN7: PORT24 Mask         */
-#define GPIO_PORT_PIN7_PORT25_Pos                             25                                                        /*!< GPIO_PORT PIN7: PORT25 Position     */
-#define GPIO_PORT_PIN7_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT25_Pos)                     /*!< GPIO_PORT PIN7: PORT25 Mask         */
-#define GPIO_PORT_PIN7_PORT26_Pos                             26                                                        /*!< GPIO_PORT PIN7: PORT26 Position     */
-#define GPIO_PORT_PIN7_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT26_Pos)                     /*!< GPIO_PORT PIN7: PORT26 Mask         */
-#define GPIO_PORT_PIN7_PORT27_Pos                             27                                                        /*!< GPIO_PORT PIN7: PORT27 Position     */
-#define GPIO_PORT_PIN7_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT27_Pos)                     /*!< GPIO_PORT PIN7: PORT27 Mask         */
-#define GPIO_PORT_PIN7_PORT28_Pos                             28                                                        /*!< GPIO_PORT PIN7: PORT28 Position     */
-#define GPIO_PORT_PIN7_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT28_Pos)                     /*!< GPIO_PORT PIN7: PORT28 Mask         */
-#define GPIO_PORT_PIN7_PORT29_Pos                             29                                                        /*!< GPIO_PORT PIN7: PORT29 Position     */
-#define GPIO_PORT_PIN7_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT29_Pos)                     /*!< GPIO_PORT PIN7: PORT29 Mask         */
-#define GPIO_PORT_PIN7_PORT30_Pos                             30                                                        /*!< GPIO_PORT PIN7: PORT30 Position     */
-#define GPIO_PORT_PIN7_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT30_Pos)                     /*!< GPIO_PORT PIN7: PORT30 Mask         */
-#define GPIO_PORT_PIN7_PORT31_Pos                             31                                                        /*!< GPIO_PORT PIN7: PORT31 Position     */
-#define GPIO_PORT_PIN7_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT31_Pos)                     /*!< GPIO_PORT PIN7: PORT31 Mask         */
-
-// -------------------------------------  GPIO_PORT_MPIN0  ----------------------------------------
-#define GPIO_PORT_MPIN0_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN0: MPORTP0 Position   */
-#define GPIO_PORT_MPIN0_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP0 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN0: MPORTP1 Position   */
-#define GPIO_PORT_MPIN0_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP1 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN0: MPORTP2 Position   */
-#define GPIO_PORT_MPIN0_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP2 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN0: MPORTP3 Position   */
-#define GPIO_PORT_MPIN0_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP3 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN0: MPORTP4 Position   */
-#define GPIO_PORT_MPIN0_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP4 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN0: MPORTP5 Position   */
-#define GPIO_PORT_MPIN0_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP5 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN0: MPORTP6 Position   */
-#define GPIO_PORT_MPIN0_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP6 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN0: MPORTP7 Position   */
-#define GPIO_PORT_MPIN0_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP7 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN0: MPORTP8 Position   */
-#define GPIO_PORT_MPIN0_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP8 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN0: MPORTP9 Position   */
-#define GPIO_PORT_MPIN0_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN0: MPORTP9 Mask       */
-#define GPIO_PORT_MPIN0_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN0: MPORTP10 Position  */
-#define GPIO_PORT_MPIN0_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP10 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN0: MPORTP11 Position  */
-#define GPIO_PORT_MPIN0_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP11 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN0: MPORTP12 Position  */
-#define GPIO_PORT_MPIN0_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP12 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN0: MPORTP13 Position  */
-#define GPIO_PORT_MPIN0_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP13 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN0: MPORTP14 Position  */
-#define GPIO_PORT_MPIN0_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP14 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN0: MPORTP15 Position  */
-#define GPIO_PORT_MPIN0_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP15 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN0: MPORTP16 Position  */
-#define GPIO_PORT_MPIN0_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP16 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN0: MPORTP17 Position  */
-#define GPIO_PORT_MPIN0_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP17 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN0: MPORTP18 Position  */
-#define GPIO_PORT_MPIN0_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP18 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN0: MPORTP19 Position  */
-#define GPIO_PORT_MPIN0_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP19 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN0: MPORTP20 Position  */
-#define GPIO_PORT_MPIN0_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP20 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN0: MPORTP21 Position  */
-#define GPIO_PORT_MPIN0_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP21 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN0: MPORTP22 Position  */
-#define GPIO_PORT_MPIN0_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP22 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN0: MPORTP23 Position  */
-#define GPIO_PORT_MPIN0_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP23 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN0: MPORTP24 Position  */
-#define GPIO_PORT_MPIN0_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP24 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN0: MPORTP25 Position  */
-#define GPIO_PORT_MPIN0_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP25 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN0: MPORTP26 Position  */
-#define GPIO_PORT_MPIN0_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP26 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN0: MPORTP27 Position  */
-#define GPIO_PORT_MPIN0_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP27 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN0: MPORTP28 Position  */
-#define GPIO_PORT_MPIN0_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP28 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN0: MPORTP29 Position  */
-#define GPIO_PORT_MPIN0_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP29 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN0: MPORTP30 Position  */
-#define GPIO_PORT_MPIN0_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP30 Mask      */
-#define GPIO_PORT_MPIN0_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN0: MPORTP31 Position  */
-#define GPIO_PORT_MPIN0_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN0: MPORTP31 Mask      */
-
-// -------------------------------------  GPIO_PORT_MPIN1  ----------------------------------------
-#define GPIO_PORT_MPIN1_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN1: MPORTP0 Position   */
-#define GPIO_PORT_MPIN1_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP0 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN1: MPORTP1 Position   */
-#define GPIO_PORT_MPIN1_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP1 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN1: MPORTP2 Position   */
-#define GPIO_PORT_MPIN1_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP2 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN1: MPORTP3 Position   */
-#define GPIO_PORT_MPIN1_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP3 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN1: MPORTP4 Position   */
-#define GPIO_PORT_MPIN1_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP4 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN1: MPORTP5 Position   */
-#define GPIO_PORT_MPIN1_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP5 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN1: MPORTP6 Position   */
-#define GPIO_PORT_MPIN1_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP6 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN1: MPORTP7 Position   */
-#define GPIO_PORT_MPIN1_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP7 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN1: MPORTP8 Position   */
-#define GPIO_PORT_MPIN1_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP8 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN1: MPORTP9 Position   */
-#define GPIO_PORT_MPIN1_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN1: MPORTP9 Mask       */
-#define GPIO_PORT_MPIN1_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN1: MPORTP10 Position  */
-#define GPIO_PORT_MPIN1_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP10 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN1: MPORTP11 Position  */
-#define GPIO_PORT_MPIN1_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP11 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN1: MPORTP12 Position  */
-#define GPIO_PORT_MPIN1_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP12 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN1: MPORTP13 Position  */
-#define GPIO_PORT_MPIN1_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP13 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN1: MPORTP14 Position  */
-#define GPIO_PORT_MPIN1_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP14 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN1: MPORTP15 Position  */
-#define GPIO_PORT_MPIN1_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP15 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN1: MPORTP16 Position  */
-#define GPIO_PORT_MPIN1_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP16 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN1: MPORTP17 Position  */
-#define GPIO_PORT_MPIN1_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP17 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN1: MPORTP18 Position  */
-#define GPIO_PORT_MPIN1_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP18 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN1: MPORTP19 Position  */
-#define GPIO_PORT_MPIN1_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP19 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN1: MPORTP20 Position  */
-#define GPIO_PORT_MPIN1_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP20 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN1: MPORTP21 Position  */
-#define GPIO_PORT_MPIN1_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP21 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN1: MPORTP22 Position  */
-#define GPIO_PORT_MPIN1_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP22 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN1: MPORTP23 Position  */
-#define GPIO_PORT_MPIN1_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP23 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN1: MPORTP24 Position  */
-#define GPIO_PORT_MPIN1_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP24 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN1: MPORTP25 Position  */
-#define GPIO_PORT_MPIN1_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP25 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN1: MPORTP26 Position  */
-#define GPIO_PORT_MPIN1_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP26 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN1: MPORTP27 Position  */
-#define GPIO_PORT_MPIN1_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP27 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN1: MPORTP28 Position  */
-#define GPIO_PORT_MPIN1_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP28 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN1: MPORTP29 Position  */
-#define GPIO_PORT_MPIN1_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP29 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN1: MPORTP30 Position  */
-#define GPIO_PORT_MPIN1_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP30 Mask      */
-#define GPIO_PORT_MPIN1_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN1: MPORTP31 Position  */
-#define GPIO_PORT_MPIN1_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN1: MPORTP31 Mask      */
-
-// -------------------------------------  GPIO_PORT_MPIN2  ----------------------------------------
-#define GPIO_PORT_MPIN2_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN2: MPORTP0 Position   */
-#define GPIO_PORT_MPIN2_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP0 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN2: MPORTP1 Position   */
-#define GPIO_PORT_MPIN2_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP1 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN2: MPORTP2 Position   */
-#define GPIO_PORT_MPIN2_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP2 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN2: MPORTP3 Position   */
-#define GPIO_PORT_MPIN2_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP3 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN2: MPORTP4 Position   */
-#define GPIO_PORT_MPIN2_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP4 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN2: MPORTP5 Position   */
-#define GPIO_PORT_MPIN2_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP5 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN2: MPORTP6 Position   */
-#define GPIO_PORT_MPIN2_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP6 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN2: MPORTP7 Position   */
-#define GPIO_PORT_MPIN2_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP7 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN2: MPORTP8 Position   */
-#define GPIO_PORT_MPIN2_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP8 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN2: MPORTP9 Position   */
-#define GPIO_PORT_MPIN2_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN2: MPORTP9 Mask       */
-#define GPIO_PORT_MPIN2_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN2: MPORTP10 Position  */
-#define GPIO_PORT_MPIN2_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP10 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN2: MPORTP11 Position  */
-#define GPIO_PORT_MPIN2_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP11 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN2: MPORTP12 Position  */
-#define GPIO_PORT_MPIN2_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP12 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN2: MPORTP13 Position  */
-#define GPIO_PORT_MPIN2_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP13 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN2: MPORTP14 Position  */
-#define GPIO_PORT_MPIN2_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP14 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN2: MPORTP15 Position  */
-#define GPIO_PORT_MPIN2_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP15 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN2: MPORTP16 Position  */
-#define GPIO_PORT_MPIN2_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP16 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN2: MPORTP17 Position  */
-#define GPIO_PORT_MPIN2_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP17 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN2: MPORTP18 Position  */
-#define GPIO_PORT_MPIN2_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP18 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN2: MPORTP19 Position  */
-#define GPIO_PORT_MPIN2_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP19 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN2: MPORTP20 Position  */
-#define GPIO_PORT_MPIN2_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP20 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN2: MPORTP21 Position  */
-#define GPIO_PORT_MPIN2_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP21 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN2: MPORTP22 Position  */
-#define GPIO_PORT_MPIN2_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP22 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN2: MPORTP23 Position  */
-#define GPIO_PORT_MPIN2_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP23 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN2: MPORTP24 Position  */
-#define GPIO_PORT_MPIN2_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP24 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN2: MPORTP25 Position  */
-#define GPIO_PORT_MPIN2_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP25 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN2: MPORTP26 Position  */
-#define GPIO_PORT_MPIN2_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP26 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN2: MPORTP27 Position  */
-#define GPIO_PORT_MPIN2_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP27 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN2: MPORTP28 Position  */
-#define GPIO_PORT_MPIN2_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP28 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN2: MPORTP29 Position  */
-#define GPIO_PORT_MPIN2_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP29 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN2: MPORTP30 Position  */
-#define GPIO_PORT_MPIN2_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP30 Mask      */
-#define GPIO_PORT_MPIN2_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN2: MPORTP31 Position  */
-#define GPIO_PORT_MPIN2_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN2: MPORTP31 Mask      */
-
-// -------------------------------------  GPIO_PORT_MPIN3  ----------------------------------------
-#define GPIO_PORT_MPIN3_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN3: MPORTP0 Position   */
-#define GPIO_PORT_MPIN3_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP0 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN3: MPORTP1 Position   */
-#define GPIO_PORT_MPIN3_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP1 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN3: MPORTP2 Position   */
-#define GPIO_PORT_MPIN3_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP2 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN3: MPORTP3 Position   */
-#define GPIO_PORT_MPIN3_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP3 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN3: MPORTP4 Position   */
-#define GPIO_PORT_MPIN3_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP4 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN3: MPORTP5 Position   */
-#define GPIO_PORT_MPIN3_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP5 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN3: MPORTP6 Position   */
-#define GPIO_PORT_MPIN3_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP6 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN3: MPORTP7 Position   */
-#define GPIO_PORT_MPIN3_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP7 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN3: MPORTP8 Position   */
-#define GPIO_PORT_MPIN3_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP8 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN3: MPORTP9 Position   */
-#define GPIO_PORT_MPIN3_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN3: MPORTP9 Mask       */
-#define GPIO_PORT_MPIN3_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN3: MPORTP10 Position  */
-#define GPIO_PORT_MPIN3_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP10 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN3: MPORTP11 Position  */
-#define GPIO_PORT_MPIN3_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP11 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN3: MPORTP12 Position  */
-#define GPIO_PORT_MPIN3_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP12 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN3: MPORTP13 Position  */
-#define GPIO_PORT_MPIN3_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP13 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN3: MPORTP14 Position  */
-#define GPIO_PORT_MPIN3_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP14 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN3: MPORTP15 Position  */
-#define GPIO_PORT_MPIN3_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP15 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN3: MPORTP16 Position  */
-#define GPIO_PORT_MPIN3_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP16 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN3: MPORTP17 Position  */
-#define GPIO_PORT_MPIN3_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP17 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN3: MPORTP18 Position  */
-#define GPIO_PORT_MPIN3_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP18 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN3: MPORTP19 Position  */
-#define GPIO_PORT_MPIN3_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP19 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN3: MPORTP20 Position  */
-#define GPIO_PORT_MPIN3_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP20 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN3: MPORTP21 Position  */
-#define GPIO_PORT_MPIN3_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP21 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN3: MPORTP22 Position  */
-#define GPIO_PORT_MPIN3_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP22 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN3: MPORTP23 Position  */
-#define GPIO_PORT_MPIN3_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP23 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN3: MPORTP24 Position  */
-#define GPIO_PORT_MPIN3_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP24 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN3: MPORTP25 Position  */
-#define GPIO_PORT_MPIN3_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP25 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN3: MPORTP26 Position  */
-#define GPIO_PORT_MPIN3_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP26 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN3: MPORTP27 Position  */
-#define GPIO_PORT_MPIN3_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP27 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN3: MPORTP28 Position  */
-#define GPIO_PORT_MPIN3_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP28 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN3: MPORTP29 Position  */
-#define GPIO_PORT_MPIN3_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP29 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN3: MPORTP30 Position  */
-#define GPIO_PORT_MPIN3_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP30 Mask      */
-#define GPIO_PORT_MPIN3_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN3: MPORTP31 Position  */
-#define GPIO_PORT_MPIN3_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN3: MPORTP31 Mask      */
-
-// -------------------------------------  GPIO_PORT_MPIN4  ----------------------------------------
-#define GPIO_PORT_MPIN4_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN4: MPORTP0 Position   */
-#define GPIO_PORT_MPIN4_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP0 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN4: MPORTP1 Position   */
-#define GPIO_PORT_MPIN4_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP1 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN4: MPORTP2 Position   */
-#define GPIO_PORT_MPIN4_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP2 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN4: MPORTP3 Position   */
-#define GPIO_PORT_MPIN4_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP3 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN4: MPORTP4 Position   */
-#define GPIO_PORT_MPIN4_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP4 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN4: MPORTP5 Position   */
-#define GPIO_PORT_MPIN4_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP5 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN4: MPORTP6 Position   */
-#define GPIO_PORT_MPIN4_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP6 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN4: MPORTP7 Position   */
-#define GPIO_PORT_MPIN4_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP7 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN4: MPORTP8 Position   */
-#define GPIO_PORT_MPIN4_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP8 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN4: MPORTP9 Position   */
-#define GPIO_PORT_MPIN4_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN4: MPORTP9 Mask       */
-#define GPIO_PORT_MPIN4_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN4: MPORTP10 Position  */
-#define GPIO_PORT_MPIN4_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP10 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN4: MPORTP11 Position  */
-#define GPIO_PORT_MPIN4_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP11 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN4: MPORTP12 Position  */
-#define GPIO_PORT_MPIN4_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP12 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN4: MPORTP13 Position  */
-#define GPIO_PORT_MPIN4_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP13 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN4: MPORTP14 Position  */
-#define GPIO_PORT_MPIN4_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP14 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN4: MPORTP15 Position  */
-#define GPIO_PORT_MPIN4_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP15 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN4: MPORTP16 Position  */
-#define GPIO_PORT_MPIN4_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP16 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN4: MPORTP17 Position  */
-#define GPIO_PORT_MPIN4_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP17 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN4: MPORTP18 Position  */
-#define GPIO_PORT_MPIN4_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP18 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN4: MPORTP19 Position  */
-#define GPIO_PORT_MPIN4_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP19 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN4: MPORTP20 Position  */
-#define GPIO_PORT_MPIN4_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP20 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN4: MPORTP21 Position  */
-#define GPIO_PORT_MPIN4_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP21 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN4: MPORTP22 Position  */
-#define GPIO_PORT_MPIN4_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP22 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN4: MPORTP23 Position  */
-#define GPIO_PORT_MPIN4_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP23 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN4: MPORTP24 Position  */
-#define GPIO_PORT_MPIN4_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP24 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN4: MPORTP25 Position  */
-#define GPIO_PORT_MPIN4_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP25 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN4: MPORTP26 Position  */
-#define GPIO_PORT_MPIN4_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP26 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN4: MPORTP27 Position  */
-#define GPIO_PORT_MPIN4_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP27 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN4: MPORTP28 Position  */
-#define GPIO_PORT_MPIN4_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP28 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN4: MPORTP29 Position  */
-#define GPIO_PORT_MPIN4_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP29 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN4: MPORTP30 Position  */
-#define GPIO_PORT_MPIN4_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP30 Mask      */
-#define GPIO_PORT_MPIN4_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN4: MPORTP31 Position  */
-#define GPIO_PORT_MPIN4_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN4: MPORTP31 Mask      */
-
-// -------------------------------------  GPIO_PORT_MPIN5  ----------------------------------------
-#define GPIO_PORT_MPIN5_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN5: MPORTP0 Position   */
-#define GPIO_PORT_MPIN5_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP0 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN5: MPORTP1 Position   */
-#define GPIO_PORT_MPIN5_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP1 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN5: MPORTP2 Position   */
-#define GPIO_PORT_MPIN5_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP2 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN5: MPORTP3 Position   */
-#define GPIO_PORT_MPIN5_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP3 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN5: MPORTP4 Position   */
-#define GPIO_PORT_MPIN5_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP4 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN5: MPORTP5 Position   */
-#define GPIO_PORT_MPIN5_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP5 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN5: MPORTP6 Position   */
-#define GPIO_PORT_MPIN5_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP6 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN5: MPORTP7 Position   */
-#define GPIO_PORT_MPIN5_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP7 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN5: MPORTP8 Position   */
-#define GPIO_PORT_MPIN5_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP8 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN5: MPORTP9 Position   */
-#define GPIO_PORT_MPIN5_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN5: MPORTP9 Mask       */
-#define GPIO_PORT_MPIN5_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN5: MPORTP10 Position  */
-#define GPIO_PORT_MPIN5_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP10 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN5: MPORTP11 Position  */
-#define GPIO_PORT_MPIN5_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP11 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN5: MPORTP12 Position  */
-#define GPIO_PORT_MPIN5_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP12 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN5: MPORTP13 Position  */
-#define GPIO_PORT_MPIN5_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP13 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN5: MPORTP14 Position  */
-#define GPIO_PORT_MPIN5_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP14 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN5: MPORTP15 Position  */
-#define GPIO_PORT_MPIN5_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP15 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN5: MPORTP16 Position  */
-#define GPIO_PORT_MPIN5_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP16 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN5: MPORTP17 Position  */
-#define GPIO_PORT_MPIN5_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP17 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN5: MPORTP18 Position  */
-#define GPIO_PORT_MPIN5_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP18 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN5: MPORTP19 Position  */
-#define GPIO_PORT_MPIN5_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP19 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN5: MPORTP20 Position  */
-#define GPIO_PORT_MPIN5_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP20 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN5: MPORTP21 Position  */
-#define GPIO_PORT_MPIN5_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP21 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN5: MPORTP22 Position  */
-#define GPIO_PORT_MPIN5_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP22 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN5: MPORTP23 Position  */
-#define GPIO_PORT_MPIN5_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP23 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN5: MPORTP24 Position  */
-#define GPIO_PORT_MPIN5_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP24 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN5: MPORTP25 Position  */
-#define GPIO_PORT_MPIN5_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP25 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN5: MPORTP26 Position  */
-#define GPIO_PORT_MPIN5_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP26 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN5: MPORTP27 Position  */
-#define GPIO_PORT_MPIN5_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP27 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN5: MPORTP28 Position  */
-#define GPIO_PORT_MPIN5_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP28 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN5: MPORTP29 Position  */
-#define GPIO_PORT_MPIN5_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP29 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN5: MPORTP30 Position  */
-#define GPIO_PORT_MPIN5_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP30 Mask      */
-#define GPIO_PORT_MPIN5_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN5: MPORTP31 Position  */
-#define GPIO_PORT_MPIN5_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN5: MPORTP31 Mask      */
-
-// -------------------------------------  GPIO_PORT_MPIN6  ----------------------------------------
-#define GPIO_PORT_MPIN6_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN6: MPORTP0 Position   */
-#define GPIO_PORT_MPIN6_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP0 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN6: MPORTP1 Position   */
-#define GPIO_PORT_MPIN6_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP1 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN6: MPORTP2 Position   */
-#define GPIO_PORT_MPIN6_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP2 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN6: MPORTP3 Position   */
-#define GPIO_PORT_MPIN6_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP3 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN6: MPORTP4 Position   */
-#define GPIO_PORT_MPIN6_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP4 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN6: MPORTP5 Position   */
-#define GPIO_PORT_MPIN6_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP5 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN6: MPORTP6 Position   */
-#define GPIO_PORT_MPIN6_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP6 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN6: MPORTP7 Position   */
-#define GPIO_PORT_MPIN6_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP7 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN6: MPORTP8 Position   */
-#define GPIO_PORT_MPIN6_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP8 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN6: MPORTP9 Position   */
-#define GPIO_PORT_MPIN6_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN6: MPORTP9 Mask       */
-#define GPIO_PORT_MPIN6_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN6: MPORTP10 Position  */
-#define GPIO_PORT_MPIN6_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP10 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN6: MPORTP11 Position  */
-#define GPIO_PORT_MPIN6_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP11 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN6: MPORTP12 Position  */
-#define GPIO_PORT_MPIN6_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP12 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN6: MPORTP13 Position  */
-#define GPIO_PORT_MPIN6_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP13 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN6: MPORTP14 Position  */
-#define GPIO_PORT_MPIN6_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP14 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN6: MPORTP15 Position  */
-#define GPIO_PORT_MPIN6_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP15 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN6: MPORTP16 Position  */
-#define GPIO_PORT_MPIN6_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP16 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN6: MPORTP17 Position  */
-#define GPIO_PORT_MPIN6_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP17 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN6: MPORTP18 Position  */
-#define GPIO_PORT_MPIN6_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP18 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN6: MPORTP19 Position  */
-#define GPIO_PORT_MPIN6_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP19 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN6: MPORTP20 Position  */
-#define GPIO_PORT_MPIN6_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP20 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN6: MPORTP21 Position  */
-#define GPIO_PORT_MPIN6_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP21 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN6: MPORTP22 Position  */
-#define GPIO_PORT_MPIN6_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP22 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN6: MPORTP23 Position  */
-#define GPIO_PORT_MPIN6_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP23 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN6: MPORTP24 Position  */
-#define GPIO_PORT_MPIN6_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP24 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN6: MPORTP25 Position  */
-#define GPIO_PORT_MPIN6_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP25 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN6: MPORTP26 Position  */
-#define GPIO_PORT_MPIN6_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP26 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN6: MPORTP27 Position  */
-#define GPIO_PORT_MPIN6_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP27 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN6: MPORTP28 Position  */
-#define GPIO_PORT_MPIN6_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP28 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN6: MPORTP29 Position  */
-#define GPIO_PORT_MPIN6_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP29 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN6: MPORTP30 Position  */
-#define GPIO_PORT_MPIN6_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP30 Mask      */
-#define GPIO_PORT_MPIN6_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN6: MPORTP31 Position  */
-#define GPIO_PORT_MPIN6_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN6: MPORTP31 Mask      */
-
-// -------------------------------------  GPIO_PORT_MPIN7  ----------------------------------------
-#define GPIO_PORT_MPIN7_MPORTP0_Pos                           0                                                         /*!< GPIO_PORT MPIN7: MPORTP0 Position   */
-#define GPIO_PORT_MPIN7_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP0_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP0 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP1_Pos                           1                                                         /*!< GPIO_PORT MPIN7: MPORTP1 Position   */
-#define GPIO_PORT_MPIN7_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP1_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP1 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP2_Pos                           2                                                         /*!< GPIO_PORT MPIN7: MPORTP2 Position   */
-#define GPIO_PORT_MPIN7_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP2_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP2 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP3_Pos                           3                                                         /*!< GPIO_PORT MPIN7: MPORTP3 Position   */
-#define GPIO_PORT_MPIN7_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP3_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP3 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP4_Pos                           4                                                         /*!< GPIO_PORT MPIN7: MPORTP4 Position   */
-#define GPIO_PORT_MPIN7_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP4_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP4 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP5_Pos                           5                                                         /*!< GPIO_PORT MPIN7: MPORTP5 Position   */
-#define GPIO_PORT_MPIN7_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP5_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP5 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP6_Pos                           6                                                         /*!< GPIO_PORT MPIN7: MPORTP6 Position   */
-#define GPIO_PORT_MPIN7_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP6_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP6 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP7_Pos                           7                                                         /*!< GPIO_PORT MPIN7: MPORTP7 Position   */
-#define GPIO_PORT_MPIN7_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP7_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP7 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP8_Pos                           8                                                         /*!< GPIO_PORT MPIN7: MPORTP8 Position   */
-#define GPIO_PORT_MPIN7_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP8_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP8 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP9_Pos                           9                                                         /*!< GPIO_PORT MPIN7: MPORTP9 Position   */
-#define GPIO_PORT_MPIN7_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP9_Pos)                   /*!< GPIO_PORT MPIN7: MPORTP9 Mask       */
-#define GPIO_PORT_MPIN7_MPORTP10_Pos                          10                                                        /*!< GPIO_PORT MPIN7: MPORTP10 Position  */
-#define GPIO_PORT_MPIN7_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP10_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP10 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP11_Pos                          11                                                        /*!< GPIO_PORT MPIN7: MPORTP11 Position  */
-#define GPIO_PORT_MPIN7_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP11_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP11 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP12_Pos                          12                                                        /*!< GPIO_PORT MPIN7: MPORTP12 Position  */
-#define GPIO_PORT_MPIN7_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP12_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP12 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP13_Pos                          13                                                        /*!< GPIO_PORT MPIN7: MPORTP13 Position  */
-#define GPIO_PORT_MPIN7_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP13_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP13 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP14_Pos                          14                                                        /*!< GPIO_PORT MPIN7: MPORTP14 Position  */
-#define GPIO_PORT_MPIN7_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP14_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP14 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP15_Pos                          15                                                        /*!< GPIO_PORT MPIN7: MPORTP15 Position  */
-#define GPIO_PORT_MPIN7_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP15_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP15 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP16_Pos                          16                                                        /*!< GPIO_PORT MPIN7: MPORTP16 Position  */
-#define GPIO_PORT_MPIN7_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP16_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP16 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP17_Pos                          17                                                        /*!< GPIO_PORT MPIN7: MPORTP17 Position  */
-#define GPIO_PORT_MPIN7_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP17_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP17 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP18_Pos                          18                                                        /*!< GPIO_PORT MPIN7: MPORTP18 Position  */
-#define GPIO_PORT_MPIN7_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP18_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP18 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP19_Pos                          19                                                        /*!< GPIO_PORT MPIN7: MPORTP19 Position  */
-#define GPIO_PORT_MPIN7_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP19_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP19 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP20_Pos                          20                                                        /*!< GPIO_PORT MPIN7: MPORTP20 Position  */
-#define GPIO_PORT_MPIN7_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP20_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP20 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP21_Pos                          21                                                        /*!< GPIO_PORT MPIN7: MPORTP21 Position  */
-#define GPIO_PORT_MPIN7_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP21_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP21 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP22_Pos                          22                                                        /*!< GPIO_PORT MPIN7: MPORTP22 Position  */
-#define GPIO_PORT_MPIN7_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP22_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP22 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP23_Pos                          23                                                        /*!< GPIO_PORT MPIN7: MPORTP23 Position  */
-#define GPIO_PORT_MPIN7_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP23_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP23 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP24_Pos                          24                                                        /*!< GPIO_PORT MPIN7: MPORTP24 Position  */
-#define GPIO_PORT_MPIN7_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP24_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP24 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP25_Pos                          25                                                        /*!< GPIO_PORT MPIN7: MPORTP25 Position  */
-#define GPIO_PORT_MPIN7_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP25_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP25 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP26_Pos                          26                                                        /*!< GPIO_PORT MPIN7: MPORTP26 Position  */
-#define GPIO_PORT_MPIN7_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP26_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP26 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP27_Pos                          27                                                        /*!< GPIO_PORT MPIN7: MPORTP27 Position  */
-#define GPIO_PORT_MPIN7_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP27_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP27 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP28_Pos                          28                                                        /*!< GPIO_PORT MPIN7: MPORTP28 Position  */
-#define GPIO_PORT_MPIN7_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP28_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP28 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP29_Pos                          29                                                        /*!< GPIO_PORT MPIN7: MPORTP29 Position  */
-#define GPIO_PORT_MPIN7_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP29_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP29 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP30_Pos                          30                                                        /*!< GPIO_PORT MPIN7: MPORTP30 Position  */
-#define GPIO_PORT_MPIN7_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP30_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP30 Mask      */
-#define GPIO_PORT_MPIN7_MPORTP31_Pos                          31                                                        /*!< GPIO_PORT MPIN7: MPORTP31 Position  */
-#define GPIO_PORT_MPIN7_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP31_Pos)                  /*!< GPIO_PORT MPIN7: MPORTP31 Mask      */
-
-// -------------------------------------  GPIO_PORT_SET0  -----------------------------------------
-#define GPIO_PORT_SET0_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET0: SETP0 Position      */
-#define GPIO_PORT_SET0_SETP0_Msk                              (0x01UL << GPIO_PORT_SET0_SETP0_Pos)                      /*!< GPIO_PORT SET0: SETP0 Mask          */
-#define GPIO_PORT_SET0_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET0: SETP1 Position      */
-#define GPIO_PORT_SET0_SETP1_Msk                              (0x01UL << GPIO_PORT_SET0_SETP1_Pos)                      /*!< GPIO_PORT SET0: SETP1 Mask          */
-#define GPIO_PORT_SET0_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET0: SETP2 Position      */
-#define GPIO_PORT_SET0_SETP2_Msk                              (0x01UL << GPIO_PORT_SET0_SETP2_Pos)                      /*!< GPIO_PORT SET0: SETP2 Mask          */
-#define GPIO_PORT_SET0_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET0: SETP3 Position      */
-#define GPIO_PORT_SET0_SETP3_Msk                              (0x01UL << GPIO_PORT_SET0_SETP3_Pos)                      /*!< GPIO_PORT SET0: SETP3 Mask          */
-#define GPIO_PORT_SET0_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET0: SETP4 Position      */
-#define GPIO_PORT_SET0_SETP4_Msk                              (0x01UL << GPIO_PORT_SET0_SETP4_Pos)                      /*!< GPIO_PORT SET0: SETP4 Mask          */
-#define GPIO_PORT_SET0_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET0: SETP5 Position      */
-#define GPIO_PORT_SET0_SETP5_Msk                              (0x01UL << GPIO_PORT_SET0_SETP5_Pos)                      /*!< GPIO_PORT SET0: SETP5 Mask          */
-#define GPIO_PORT_SET0_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET0: SETP6 Position      */
-#define GPIO_PORT_SET0_SETP6_Msk                              (0x01UL << GPIO_PORT_SET0_SETP6_Pos)                      /*!< GPIO_PORT SET0: SETP6 Mask          */
-#define GPIO_PORT_SET0_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET0: SETP7 Position      */
-#define GPIO_PORT_SET0_SETP7_Msk                              (0x01UL << GPIO_PORT_SET0_SETP7_Pos)                      /*!< GPIO_PORT SET0: SETP7 Mask          */
-#define GPIO_PORT_SET0_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET0: SETP8 Position      */
-#define GPIO_PORT_SET0_SETP8_Msk                              (0x01UL << GPIO_PORT_SET0_SETP8_Pos)                      /*!< GPIO_PORT SET0: SETP8 Mask          */
-#define GPIO_PORT_SET0_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET0: SETP9 Position      */
-#define GPIO_PORT_SET0_SETP9_Msk                              (0x01UL << GPIO_PORT_SET0_SETP9_Pos)                      /*!< GPIO_PORT SET0: SETP9 Mask          */
-#define GPIO_PORT_SET0_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET0: SETP10 Position     */
-#define GPIO_PORT_SET0_SETP10_Msk                             (0x01UL << GPIO_PORT_SET0_SETP10_Pos)                     /*!< GPIO_PORT SET0: SETP10 Mask         */
-#define GPIO_PORT_SET0_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET0: SETP11 Position     */
-#define GPIO_PORT_SET0_SETP11_Msk                             (0x01UL << GPIO_PORT_SET0_SETP11_Pos)                     /*!< GPIO_PORT SET0: SETP11 Mask         */
-#define GPIO_PORT_SET0_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET0: SETP12 Position     */
-#define GPIO_PORT_SET0_SETP12_Msk                             (0x01UL << GPIO_PORT_SET0_SETP12_Pos)                     /*!< GPIO_PORT SET0: SETP12 Mask         */
-#define GPIO_PORT_SET0_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET0: SETP13 Position     */
-#define GPIO_PORT_SET0_SETP13_Msk                             (0x01UL << GPIO_PORT_SET0_SETP13_Pos)                     /*!< GPIO_PORT SET0: SETP13 Mask         */
-#define GPIO_PORT_SET0_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET0: SETP14 Position     */
-#define GPIO_PORT_SET0_SETP14_Msk                             (0x01UL << GPIO_PORT_SET0_SETP14_Pos)                     /*!< GPIO_PORT SET0: SETP14 Mask         */
-#define GPIO_PORT_SET0_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET0: SETP15 Position     */
-#define GPIO_PORT_SET0_SETP15_Msk                             (0x01UL << GPIO_PORT_SET0_SETP15_Pos)                     /*!< GPIO_PORT SET0: SETP15 Mask         */
-#define GPIO_PORT_SET0_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET0: SETP16 Position     */
-#define GPIO_PORT_SET0_SETP16_Msk                             (0x01UL << GPIO_PORT_SET0_SETP16_Pos)                     /*!< GPIO_PORT SET0: SETP16 Mask         */
-#define GPIO_PORT_SET0_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET0: SETP17 Position     */
-#define GPIO_PORT_SET0_SETP17_Msk                             (0x01UL << GPIO_PORT_SET0_SETP17_Pos)                     /*!< GPIO_PORT SET0: SETP17 Mask         */
-#define GPIO_PORT_SET0_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET0: SETP18 Position     */
-#define GPIO_PORT_SET0_SETP18_Msk                             (0x01UL << GPIO_PORT_SET0_SETP18_Pos)                     /*!< GPIO_PORT SET0: SETP18 Mask         */
-#define GPIO_PORT_SET0_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET0: SETP19 Position     */
-#define GPIO_PORT_SET0_SETP19_Msk                             (0x01UL << GPIO_PORT_SET0_SETP19_Pos)                     /*!< GPIO_PORT SET0: SETP19 Mask         */
-#define GPIO_PORT_SET0_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET0: SETP20 Position     */
-#define GPIO_PORT_SET0_SETP20_Msk                             (0x01UL << GPIO_PORT_SET0_SETP20_Pos)                     /*!< GPIO_PORT SET0: SETP20 Mask         */
-#define GPIO_PORT_SET0_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET0: SETP21 Position     */
-#define GPIO_PORT_SET0_SETP21_Msk                             (0x01UL << GPIO_PORT_SET0_SETP21_Pos)                     /*!< GPIO_PORT SET0: SETP21 Mask         */
-#define GPIO_PORT_SET0_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET0: SETP22 Position     */
-#define GPIO_PORT_SET0_SETP22_Msk                             (0x01UL << GPIO_PORT_SET0_SETP22_Pos)                     /*!< GPIO_PORT SET0: SETP22 Mask         */
-#define GPIO_PORT_SET0_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET0: SETP23 Position     */
-#define GPIO_PORT_SET0_SETP23_Msk                             (0x01UL << GPIO_PORT_SET0_SETP23_Pos)                     /*!< GPIO_PORT SET0: SETP23 Mask         */
-#define GPIO_PORT_SET0_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET0: SETP24 Position     */
-#define GPIO_PORT_SET0_SETP24_Msk                             (0x01UL << GPIO_PORT_SET0_SETP24_Pos)                     /*!< GPIO_PORT SET0: SETP24 Mask         */
-#define GPIO_PORT_SET0_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET0: SETP25 Position     */
-#define GPIO_PORT_SET0_SETP25_Msk                             (0x01UL << GPIO_PORT_SET0_SETP25_Pos)                     /*!< GPIO_PORT SET0: SETP25 Mask         */
-#define GPIO_PORT_SET0_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET0: SETP26 Position     */
-#define GPIO_PORT_SET0_SETP26_Msk                             (0x01UL << GPIO_PORT_SET0_SETP26_Pos)                     /*!< GPIO_PORT SET0: SETP26 Mask         */
-#define GPIO_PORT_SET0_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET0: SETP27 Position     */
-#define GPIO_PORT_SET0_SETP27_Msk                             (0x01UL << GPIO_PORT_SET0_SETP27_Pos)                     /*!< GPIO_PORT SET0: SETP27 Mask         */
-#define GPIO_PORT_SET0_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET0: SETP28 Position     */
-#define GPIO_PORT_SET0_SETP28_Msk                             (0x01UL << GPIO_PORT_SET0_SETP28_Pos)                     /*!< GPIO_PORT SET0: SETP28 Mask         */
-#define GPIO_PORT_SET0_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET0: SETP29 Position     */
-#define GPIO_PORT_SET0_SETP29_Msk                             (0x01UL << GPIO_PORT_SET0_SETP29_Pos)                     /*!< GPIO_PORT SET0: SETP29 Mask         */
-#define GPIO_PORT_SET0_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET0: SETP30 Position     */
-#define GPIO_PORT_SET0_SETP30_Msk                             (0x01UL << GPIO_PORT_SET0_SETP30_Pos)                     /*!< GPIO_PORT SET0: SETP30 Mask         */
-#define GPIO_PORT_SET0_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET0: SETP31 Position     */
-#define GPIO_PORT_SET0_SETP31_Msk                             (0x01UL << GPIO_PORT_SET0_SETP31_Pos)                     /*!< GPIO_PORT SET0: SETP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_SET1  -----------------------------------------
-#define GPIO_PORT_SET1_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET1: SETP0 Position      */
-#define GPIO_PORT_SET1_SETP0_Msk                              (0x01UL << GPIO_PORT_SET1_SETP0_Pos)                      /*!< GPIO_PORT SET1: SETP0 Mask          */
-#define GPIO_PORT_SET1_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET1: SETP1 Position      */
-#define GPIO_PORT_SET1_SETP1_Msk                              (0x01UL << GPIO_PORT_SET1_SETP1_Pos)                      /*!< GPIO_PORT SET1: SETP1 Mask          */
-#define GPIO_PORT_SET1_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET1: SETP2 Position      */
-#define GPIO_PORT_SET1_SETP2_Msk                              (0x01UL << GPIO_PORT_SET1_SETP2_Pos)                      /*!< GPIO_PORT SET1: SETP2 Mask          */
-#define GPIO_PORT_SET1_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET1: SETP3 Position      */
-#define GPIO_PORT_SET1_SETP3_Msk                              (0x01UL << GPIO_PORT_SET1_SETP3_Pos)                      /*!< GPIO_PORT SET1: SETP3 Mask          */
-#define GPIO_PORT_SET1_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET1: SETP4 Position      */
-#define GPIO_PORT_SET1_SETP4_Msk                              (0x01UL << GPIO_PORT_SET1_SETP4_Pos)                      /*!< GPIO_PORT SET1: SETP4 Mask          */
-#define GPIO_PORT_SET1_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET1: SETP5 Position      */
-#define GPIO_PORT_SET1_SETP5_Msk                              (0x01UL << GPIO_PORT_SET1_SETP5_Pos)                      /*!< GPIO_PORT SET1: SETP5 Mask          */
-#define GPIO_PORT_SET1_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET1: SETP6 Position      */
-#define GPIO_PORT_SET1_SETP6_Msk                              (0x01UL << GPIO_PORT_SET1_SETP6_Pos)                      /*!< GPIO_PORT SET1: SETP6 Mask          */
-#define GPIO_PORT_SET1_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET1: SETP7 Position      */
-#define GPIO_PORT_SET1_SETP7_Msk                              (0x01UL << GPIO_PORT_SET1_SETP7_Pos)                      /*!< GPIO_PORT SET1: SETP7 Mask          */
-#define GPIO_PORT_SET1_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET1: SETP8 Position      */
-#define GPIO_PORT_SET1_SETP8_Msk                              (0x01UL << GPIO_PORT_SET1_SETP8_Pos)                      /*!< GPIO_PORT SET1: SETP8 Mask          */
-#define GPIO_PORT_SET1_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET1: SETP9 Position      */
-#define GPIO_PORT_SET1_SETP9_Msk                              (0x01UL << GPIO_PORT_SET1_SETP9_Pos)                      /*!< GPIO_PORT SET1: SETP9 Mask          */
-#define GPIO_PORT_SET1_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET1: SETP10 Position     */
-#define GPIO_PORT_SET1_SETP10_Msk                             (0x01UL << GPIO_PORT_SET1_SETP10_Pos)                     /*!< GPIO_PORT SET1: SETP10 Mask         */
-#define GPIO_PORT_SET1_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET1: SETP11 Position     */
-#define GPIO_PORT_SET1_SETP11_Msk                             (0x01UL << GPIO_PORT_SET1_SETP11_Pos)                     /*!< GPIO_PORT SET1: SETP11 Mask         */
-#define GPIO_PORT_SET1_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET1: SETP12 Position     */
-#define GPIO_PORT_SET1_SETP12_Msk                             (0x01UL << GPIO_PORT_SET1_SETP12_Pos)                     /*!< GPIO_PORT SET1: SETP12 Mask         */
-#define GPIO_PORT_SET1_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET1: SETP13 Position     */
-#define GPIO_PORT_SET1_SETP13_Msk                             (0x01UL << GPIO_PORT_SET1_SETP13_Pos)                     /*!< GPIO_PORT SET1: SETP13 Mask         */
-#define GPIO_PORT_SET1_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET1: SETP14 Position     */
-#define GPIO_PORT_SET1_SETP14_Msk                             (0x01UL << GPIO_PORT_SET1_SETP14_Pos)                     /*!< GPIO_PORT SET1: SETP14 Mask         */
-#define GPIO_PORT_SET1_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET1: SETP15 Position     */
-#define GPIO_PORT_SET1_SETP15_Msk                             (0x01UL << GPIO_PORT_SET1_SETP15_Pos)                     /*!< GPIO_PORT SET1: SETP15 Mask         */
-#define GPIO_PORT_SET1_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET1: SETP16 Position     */
-#define GPIO_PORT_SET1_SETP16_Msk                             (0x01UL << GPIO_PORT_SET1_SETP16_Pos)                     /*!< GPIO_PORT SET1: SETP16 Mask         */
-#define GPIO_PORT_SET1_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET1: SETP17 Position     */
-#define GPIO_PORT_SET1_SETP17_Msk                             (0x01UL << GPIO_PORT_SET1_SETP17_Pos)                     /*!< GPIO_PORT SET1: SETP17 Mask         */
-#define GPIO_PORT_SET1_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET1: SETP18 Position     */
-#define GPIO_PORT_SET1_SETP18_Msk                             (0x01UL << GPIO_PORT_SET1_SETP18_Pos)                     /*!< GPIO_PORT SET1: SETP18 Mask         */
-#define GPIO_PORT_SET1_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET1: SETP19 Position     */
-#define GPIO_PORT_SET1_SETP19_Msk                             (0x01UL << GPIO_PORT_SET1_SETP19_Pos)                     /*!< GPIO_PORT SET1: SETP19 Mask         */
-#define GPIO_PORT_SET1_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET1: SETP20 Position     */
-#define GPIO_PORT_SET1_SETP20_Msk                             (0x01UL << GPIO_PORT_SET1_SETP20_Pos)                     /*!< GPIO_PORT SET1: SETP20 Mask         */
-#define GPIO_PORT_SET1_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET1: SETP21 Position     */
-#define GPIO_PORT_SET1_SETP21_Msk                             (0x01UL << GPIO_PORT_SET1_SETP21_Pos)                     /*!< GPIO_PORT SET1: SETP21 Mask         */
-#define GPIO_PORT_SET1_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET1: SETP22 Position     */
-#define GPIO_PORT_SET1_SETP22_Msk                             (0x01UL << GPIO_PORT_SET1_SETP22_Pos)                     /*!< GPIO_PORT SET1: SETP22 Mask         */
-#define GPIO_PORT_SET1_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET1: SETP23 Position     */
-#define GPIO_PORT_SET1_SETP23_Msk                             (0x01UL << GPIO_PORT_SET1_SETP23_Pos)                     /*!< GPIO_PORT SET1: SETP23 Mask         */
-#define GPIO_PORT_SET1_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET1: SETP24 Position     */
-#define GPIO_PORT_SET1_SETP24_Msk                             (0x01UL << GPIO_PORT_SET1_SETP24_Pos)                     /*!< GPIO_PORT SET1: SETP24 Mask         */
-#define GPIO_PORT_SET1_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET1: SETP25 Position     */
-#define GPIO_PORT_SET1_SETP25_Msk                             (0x01UL << GPIO_PORT_SET1_SETP25_Pos)                     /*!< GPIO_PORT SET1: SETP25 Mask         */
-#define GPIO_PORT_SET1_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET1: SETP26 Position     */
-#define GPIO_PORT_SET1_SETP26_Msk                             (0x01UL << GPIO_PORT_SET1_SETP26_Pos)                     /*!< GPIO_PORT SET1: SETP26 Mask         */
-#define GPIO_PORT_SET1_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET1: SETP27 Position     */
-#define GPIO_PORT_SET1_SETP27_Msk                             (0x01UL << GPIO_PORT_SET1_SETP27_Pos)                     /*!< GPIO_PORT SET1: SETP27 Mask         */
-#define GPIO_PORT_SET1_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET1: SETP28 Position     */
-#define GPIO_PORT_SET1_SETP28_Msk                             (0x01UL << GPIO_PORT_SET1_SETP28_Pos)                     /*!< GPIO_PORT SET1: SETP28 Mask         */
-#define GPIO_PORT_SET1_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET1: SETP29 Position     */
-#define GPIO_PORT_SET1_SETP29_Msk                             (0x01UL << GPIO_PORT_SET1_SETP29_Pos)                     /*!< GPIO_PORT SET1: SETP29 Mask         */
-#define GPIO_PORT_SET1_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET1: SETP30 Position     */
-#define GPIO_PORT_SET1_SETP30_Msk                             (0x01UL << GPIO_PORT_SET1_SETP30_Pos)                     /*!< GPIO_PORT SET1: SETP30 Mask         */
-#define GPIO_PORT_SET1_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET1: SETP31 Position     */
-#define GPIO_PORT_SET1_SETP31_Msk                             (0x01UL << GPIO_PORT_SET1_SETP31_Pos)                     /*!< GPIO_PORT SET1: SETP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_SET2  -----------------------------------------
-#define GPIO_PORT_SET2_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET2: SETP0 Position      */
-#define GPIO_PORT_SET2_SETP0_Msk                              (0x01UL << GPIO_PORT_SET2_SETP0_Pos)                      /*!< GPIO_PORT SET2: SETP0 Mask          */
-#define GPIO_PORT_SET2_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET2: SETP1 Position      */
-#define GPIO_PORT_SET2_SETP1_Msk                              (0x01UL << GPIO_PORT_SET2_SETP1_Pos)                      /*!< GPIO_PORT SET2: SETP1 Mask          */
-#define GPIO_PORT_SET2_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET2: SETP2 Position      */
-#define GPIO_PORT_SET2_SETP2_Msk                              (0x01UL << GPIO_PORT_SET2_SETP2_Pos)                      /*!< GPIO_PORT SET2: SETP2 Mask          */
-#define GPIO_PORT_SET2_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET2: SETP3 Position      */
-#define GPIO_PORT_SET2_SETP3_Msk                              (0x01UL << GPIO_PORT_SET2_SETP3_Pos)                      /*!< GPIO_PORT SET2: SETP3 Mask          */
-#define GPIO_PORT_SET2_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET2: SETP4 Position      */
-#define GPIO_PORT_SET2_SETP4_Msk                              (0x01UL << GPIO_PORT_SET2_SETP4_Pos)                      /*!< GPIO_PORT SET2: SETP4 Mask          */
-#define GPIO_PORT_SET2_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET2: SETP5 Position      */
-#define GPIO_PORT_SET2_SETP5_Msk                              (0x01UL << GPIO_PORT_SET2_SETP5_Pos)                      /*!< GPIO_PORT SET2: SETP5 Mask          */
-#define GPIO_PORT_SET2_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET2: SETP6 Position      */
-#define GPIO_PORT_SET2_SETP6_Msk                              (0x01UL << GPIO_PORT_SET2_SETP6_Pos)                      /*!< GPIO_PORT SET2: SETP6 Mask          */
-#define GPIO_PORT_SET2_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET2: SETP7 Position      */
-#define GPIO_PORT_SET2_SETP7_Msk                              (0x01UL << GPIO_PORT_SET2_SETP7_Pos)                      /*!< GPIO_PORT SET2: SETP7 Mask          */
-#define GPIO_PORT_SET2_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET2: SETP8 Position      */
-#define GPIO_PORT_SET2_SETP8_Msk                              (0x01UL << GPIO_PORT_SET2_SETP8_Pos)                      /*!< GPIO_PORT SET2: SETP8 Mask          */
-#define GPIO_PORT_SET2_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET2: SETP9 Position      */
-#define GPIO_PORT_SET2_SETP9_Msk                              (0x01UL << GPIO_PORT_SET2_SETP9_Pos)                      /*!< GPIO_PORT SET2: SETP9 Mask          */
-#define GPIO_PORT_SET2_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET2: SETP10 Position     */
-#define GPIO_PORT_SET2_SETP10_Msk                             (0x01UL << GPIO_PORT_SET2_SETP10_Pos)                     /*!< GPIO_PORT SET2: SETP10 Mask         */
-#define GPIO_PORT_SET2_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET2: SETP11 Position     */
-#define GPIO_PORT_SET2_SETP11_Msk                             (0x01UL << GPIO_PORT_SET2_SETP11_Pos)                     /*!< GPIO_PORT SET2: SETP11 Mask         */
-#define GPIO_PORT_SET2_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET2: SETP12 Position     */
-#define GPIO_PORT_SET2_SETP12_Msk                             (0x01UL << GPIO_PORT_SET2_SETP12_Pos)                     /*!< GPIO_PORT SET2: SETP12 Mask         */
-#define GPIO_PORT_SET2_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET2: SETP13 Position     */
-#define GPIO_PORT_SET2_SETP13_Msk                             (0x01UL << GPIO_PORT_SET2_SETP13_Pos)                     /*!< GPIO_PORT SET2: SETP13 Mask         */
-#define GPIO_PORT_SET2_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET2: SETP14 Position     */
-#define GPIO_PORT_SET2_SETP14_Msk                             (0x01UL << GPIO_PORT_SET2_SETP14_Pos)                     /*!< GPIO_PORT SET2: SETP14 Mask         */
-#define GPIO_PORT_SET2_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET2: SETP15 Position     */
-#define GPIO_PORT_SET2_SETP15_Msk                             (0x01UL << GPIO_PORT_SET2_SETP15_Pos)                     /*!< GPIO_PORT SET2: SETP15 Mask         */
-#define GPIO_PORT_SET2_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET2: SETP16 Position     */
-#define GPIO_PORT_SET2_SETP16_Msk                             (0x01UL << GPIO_PORT_SET2_SETP16_Pos)                     /*!< GPIO_PORT SET2: SETP16 Mask         */
-#define GPIO_PORT_SET2_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET2: SETP17 Position     */
-#define GPIO_PORT_SET2_SETP17_Msk                             (0x01UL << GPIO_PORT_SET2_SETP17_Pos)                     /*!< GPIO_PORT SET2: SETP17 Mask         */
-#define GPIO_PORT_SET2_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET2: SETP18 Position     */
-#define GPIO_PORT_SET2_SETP18_Msk                             (0x01UL << GPIO_PORT_SET2_SETP18_Pos)                     /*!< GPIO_PORT SET2: SETP18 Mask         */
-#define GPIO_PORT_SET2_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET2: SETP19 Position     */
-#define GPIO_PORT_SET2_SETP19_Msk                             (0x01UL << GPIO_PORT_SET2_SETP19_Pos)                     /*!< GPIO_PORT SET2: SETP19 Mask         */
-#define GPIO_PORT_SET2_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET2: SETP20 Position     */
-#define GPIO_PORT_SET2_SETP20_Msk                             (0x01UL << GPIO_PORT_SET2_SETP20_Pos)                     /*!< GPIO_PORT SET2: SETP20 Mask         */
-#define GPIO_PORT_SET2_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET2: SETP21 Position     */
-#define GPIO_PORT_SET2_SETP21_Msk                             (0x01UL << GPIO_PORT_SET2_SETP21_Pos)                     /*!< GPIO_PORT SET2: SETP21 Mask         */
-#define GPIO_PORT_SET2_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET2: SETP22 Position     */
-#define GPIO_PORT_SET2_SETP22_Msk                             (0x01UL << GPIO_PORT_SET2_SETP22_Pos)                     /*!< GPIO_PORT SET2: SETP22 Mask         */
-#define GPIO_PORT_SET2_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET2: SETP23 Position     */
-#define GPIO_PORT_SET2_SETP23_Msk                             (0x01UL << GPIO_PORT_SET2_SETP23_Pos)                     /*!< GPIO_PORT SET2: SETP23 Mask         */
-#define GPIO_PORT_SET2_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET2: SETP24 Position     */
-#define GPIO_PORT_SET2_SETP24_Msk                             (0x01UL << GPIO_PORT_SET2_SETP24_Pos)                     /*!< GPIO_PORT SET2: SETP24 Mask         */
-#define GPIO_PORT_SET2_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET2: SETP25 Position     */
-#define GPIO_PORT_SET2_SETP25_Msk                             (0x01UL << GPIO_PORT_SET2_SETP25_Pos)                     /*!< GPIO_PORT SET2: SETP25 Mask         */
-#define GPIO_PORT_SET2_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET2: SETP26 Position     */
-#define GPIO_PORT_SET2_SETP26_Msk                             (0x01UL << GPIO_PORT_SET2_SETP26_Pos)                     /*!< GPIO_PORT SET2: SETP26 Mask         */
-#define GPIO_PORT_SET2_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET2: SETP27 Position     */
-#define GPIO_PORT_SET2_SETP27_Msk                             (0x01UL << GPIO_PORT_SET2_SETP27_Pos)                     /*!< GPIO_PORT SET2: SETP27 Mask         */
-#define GPIO_PORT_SET2_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET2: SETP28 Position     */
-#define GPIO_PORT_SET2_SETP28_Msk                             (0x01UL << GPIO_PORT_SET2_SETP28_Pos)                     /*!< GPIO_PORT SET2: SETP28 Mask         */
-#define GPIO_PORT_SET2_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET2: SETP29 Position     */
-#define GPIO_PORT_SET2_SETP29_Msk                             (0x01UL << GPIO_PORT_SET2_SETP29_Pos)                     /*!< GPIO_PORT SET2: SETP29 Mask         */
-#define GPIO_PORT_SET2_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET2: SETP30 Position     */
-#define GPIO_PORT_SET2_SETP30_Msk                             (0x01UL << GPIO_PORT_SET2_SETP30_Pos)                     /*!< GPIO_PORT SET2: SETP30 Mask         */
-#define GPIO_PORT_SET2_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET2: SETP31 Position     */
-#define GPIO_PORT_SET2_SETP31_Msk                             (0x01UL << GPIO_PORT_SET2_SETP31_Pos)                     /*!< GPIO_PORT SET2: SETP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_SET3  -----------------------------------------
-#define GPIO_PORT_SET3_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET3: SETP0 Position      */
-#define GPIO_PORT_SET3_SETP0_Msk                              (0x01UL << GPIO_PORT_SET3_SETP0_Pos)                      /*!< GPIO_PORT SET3: SETP0 Mask          */
-#define GPIO_PORT_SET3_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET3: SETP1 Position      */
-#define GPIO_PORT_SET3_SETP1_Msk                              (0x01UL << GPIO_PORT_SET3_SETP1_Pos)                      /*!< GPIO_PORT SET3: SETP1 Mask          */
-#define GPIO_PORT_SET3_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET3: SETP2 Position      */
-#define GPIO_PORT_SET3_SETP2_Msk                              (0x01UL << GPIO_PORT_SET3_SETP2_Pos)                      /*!< GPIO_PORT SET3: SETP2 Mask          */
-#define GPIO_PORT_SET3_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET3: SETP3 Position      */
-#define GPIO_PORT_SET3_SETP3_Msk                              (0x01UL << GPIO_PORT_SET3_SETP3_Pos)                      /*!< GPIO_PORT SET3: SETP3 Mask          */
-#define GPIO_PORT_SET3_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET3: SETP4 Position      */
-#define GPIO_PORT_SET3_SETP4_Msk                              (0x01UL << GPIO_PORT_SET3_SETP4_Pos)                      /*!< GPIO_PORT SET3: SETP4 Mask          */
-#define GPIO_PORT_SET3_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET3: SETP5 Position      */
-#define GPIO_PORT_SET3_SETP5_Msk                              (0x01UL << GPIO_PORT_SET3_SETP5_Pos)                      /*!< GPIO_PORT SET3: SETP5 Mask          */
-#define GPIO_PORT_SET3_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET3: SETP6 Position      */
-#define GPIO_PORT_SET3_SETP6_Msk                              (0x01UL << GPIO_PORT_SET3_SETP6_Pos)                      /*!< GPIO_PORT SET3: SETP6 Mask          */
-#define GPIO_PORT_SET3_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET3: SETP7 Position      */
-#define GPIO_PORT_SET3_SETP7_Msk                              (0x01UL << GPIO_PORT_SET3_SETP7_Pos)                      /*!< GPIO_PORT SET3: SETP7 Mask          */
-#define GPIO_PORT_SET3_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET3: SETP8 Position      */
-#define GPIO_PORT_SET3_SETP8_Msk                              (0x01UL << GPIO_PORT_SET3_SETP8_Pos)                      /*!< GPIO_PORT SET3: SETP8 Mask          */
-#define GPIO_PORT_SET3_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET3: SETP9 Position      */
-#define GPIO_PORT_SET3_SETP9_Msk                              (0x01UL << GPIO_PORT_SET3_SETP9_Pos)                      /*!< GPIO_PORT SET3: SETP9 Mask          */
-#define GPIO_PORT_SET3_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET3: SETP10 Position     */
-#define GPIO_PORT_SET3_SETP10_Msk                             (0x01UL << GPIO_PORT_SET3_SETP10_Pos)                     /*!< GPIO_PORT SET3: SETP10 Mask         */
-#define GPIO_PORT_SET3_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET3: SETP11 Position     */
-#define GPIO_PORT_SET3_SETP11_Msk                             (0x01UL << GPIO_PORT_SET3_SETP11_Pos)                     /*!< GPIO_PORT SET3: SETP11 Mask         */
-#define GPIO_PORT_SET3_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET3: SETP12 Position     */
-#define GPIO_PORT_SET3_SETP12_Msk                             (0x01UL << GPIO_PORT_SET3_SETP12_Pos)                     /*!< GPIO_PORT SET3: SETP12 Mask         */
-#define GPIO_PORT_SET3_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET3: SETP13 Position     */
-#define GPIO_PORT_SET3_SETP13_Msk                             (0x01UL << GPIO_PORT_SET3_SETP13_Pos)                     /*!< GPIO_PORT SET3: SETP13 Mask         */
-#define GPIO_PORT_SET3_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET3: SETP14 Position     */
-#define GPIO_PORT_SET3_SETP14_Msk                             (0x01UL << GPIO_PORT_SET3_SETP14_Pos)                     /*!< GPIO_PORT SET3: SETP14 Mask         */
-#define GPIO_PORT_SET3_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET3: SETP15 Position     */
-#define GPIO_PORT_SET3_SETP15_Msk                             (0x01UL << GPIO_PORT_SET3_SETP15_Pos)                     /*!< GPIO_PORT SET3: SETP15 Mask         */
-#define GPIO_PORT_SET3_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET3: SETP16 Position     */
-#define GPIO_PORT_SET3_SETP16_Msk                             (0x01UL << GPIO_PORT_SET3_SETP16_Pos)                     /*!< GPIO_PORT SET3: SETP16 Mask         */
-#define GPIO_PORT_SET3_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET3: SETP17 Position     */
-#define GPIO_PORT_SET3_SETP17_Msk                             (0x01UL << GPIO_PORT_SET3_SETP17_Pos)                     /*!< GPIO_PORT SET3: SETP17 Mask         */
-#define GPIO_PORT_SET3_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET3: SETP18 Position     */
-#define GPIO_PORT_SET3_SETP18_Msk                             (0x01UL << GPIO_PORT_SET3_SETP18_Pos)                     /*!< GPIO_PORT SET3: SETP18 Mask         */
-#define GPIO_PORT_SET3_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET3: SETP19 Position     */
-#define GPIO_PORT_SET3_SETP19_Msk                             (0x01UL << GPIO_PORT_SET3_SETP19_Pos)                     /*!< GPIO_PORT SET3: SETP19 Mask         */
-#define GPIO_PORT_SET3_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET3: SETP20 Position     */
-#define GPIO_PORT_SET3_SETP20_Msk                             (0x01UL << GPIO_PORT_SET3_SETP20_Pos)                     /*!< GPIO_PORT SET3: SETP20 Mask         */
-#define GPIO_PORT_SET3_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET3: SETP21 Position     */
-#define GPIO_PORT_SET3_SETP21_Msk                             (0x01UL << GPIO_PORT_SET3_SETP21_Pos)                     /*!< GPIO_PORT SET3: SETP21 Mask         */
-#define GPIO_PORT_SET3_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET3: SETP22 Position     */
-#define GPIO_PORT_SET3_SETP22_Msk                             (0x01UL << GPIO_PORT_SET3_SETP22_Pos)                     /*!< GPIO_PORT SET3: SETP22 Mask         */
-#define GPIO_PORT_SET3_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET3: SETP23 Position     */
-#define GPIO_PORT_SET3_SETP23_Msk                             (0x01UL << GPIO_PORT_SET3_SETP23_Pos)                     /*!< GPIO_PORT SET3: SETP23 Mask         */
-#define GPIO_PORT_SET3_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET3: SETP24 Position     */
-#define GPIO_PORT_SET3_SETP24_Msk                             (0x01UL << GPIO_PORT_SET3_SETP24_Pos)                     /*!< GPIO_PORT SET3: SETP24 Mask         */
-#define GPIO_PORT_SET3_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET3: SETP25 Position     */
-#define GPIO_PORT_SET3_SETP25_Msk                             (0x01UL << GPIO_PORT_SET3_SETP25_Pos)                     /*!< GPIO_PORT SET3: SETP25 Mask         */
-#define GPIO_PORT_SET3_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET3: SETP26 Position     */
-#define GPIO_PORT_SET3_SETP26_Msk                             (0x01UL << GPIO_PORT_SET3_SETP26_Pos)                     /*!< GPIO_PORT SET3: SETP26 Mask         */
-#define GPIO_PORT_SET3_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET3: SETP27 Position     */
-#define GPIO_PORT_SET3_SETP27_Msk                             (0x01UL << GPIO_PORT_SET3_SETP27_Pos)                     /*!< GPIO_PORT SET3: SETP27 Mask         */
-#define GPIO_PORT_SET3_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET3: SETP28 Position     */
-#define GPIO_PORT_SET3_SETP28_Msk                             (0x01UL << GPIO_PORT_SET3_SETP28_Pos)                     /*!< GPIO_PORT SET3: SETP28 Mask         */
-#define GPIO_PORT_SET3_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET3: SETP29 Position     */
-#define GPIO_PORT_SET3_SETP29_Msk                             (0x01UL << GPIO_PORT_SET3_SETP29_Pos)                     /*!< GPIO_PORT SET3: SETP29 Mask         */
-#define GPIO_PORT_SET3_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET3: SETP30 Position     */
-#define GPIO_PORT_SET3_SETP30_Msk                             (0x01UL << GPIO_PORT_SET3_SETP30_Pos)                     /*!< GPIO_PORT SET3: SETP30 Mask         */
-#define GPIO_PORT_SET3_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET3: SETP31 Position     */
-#define GPIO_PORT_SET3_SETP31_Msk                             (0x01UL << GPIO_PORT_SET3_SETP31_Pos)                     /*!< GPIO_PORT SET3: SETP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_SET4  -----------------------------------------
-#define GPIO_PORT_SET4_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET4: SETP0 Position      */
-#define GPIO_PORT_SET4_SETP0_Msk                              (0x01UL << GPIO_PORT_SET4_SETP0_Pos)                      /*!< GPIO_PORT SET4: SETP0 Mask          */
-#define GPIO_PORT_SET4_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET4: SETP1 Position      */
-#define GPIO_PORT_SET4_SETP1_Msk                              (0x01UL << GPIO_PORT_SET4_SETP1_Pos)                      /*!< GPIO_PORT SET4: SETP1 Mask          */
-#define GPIO_PORT_SET4_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET4: SETP2 Position      */
-#define GPIO_PORT_SET4_SETP2_Msk                              (0x01UL << GPIO_PORT_SET4_SETP2_Pos)                      /*!< GPIO_PORT SET4: SETP2 Mask          */
-#define GPIO_PORT_SET4_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET4: SETP3 Position      */
-#define GPIO_PORT_SET4_SETP3_Msk                              (0x01UL << GPIO_PORT_SET4_SETP3_Pos)                      /*!< GPIO_PORT SET4: SETP3 Mask          */
-#define GPIO_PORT_SET4_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET4: SETP4 Position      */
-#define GPIO_PORT_SET4_SETP4_Msk                              (0x01UL << GPIO_PORT_SET4_SETP4_Pos)                      /*!< GPIO_PORT SET4: SETP4 Mask          */
-#define GPIO_PORT_SET4_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET4: SETP5 Position      */
-#define GPIO_PORT_SET4_SETP5_Msk                              (0x01UL << GPIO_PORT_SET4_SETP5_Pos)                      /*!< GPIO_PORT SET4: SETP5 Mask          */
-#define GPIO_PORT_SET4_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET4: SETP6 Position      */
-#define GPIO_PORT_SET4_SETP6_Msk                              (0x01UL << GPIO_PORT_SET4_SETP6_Pos)                      /*!< GPIO_PORT SET4: SETP6 Mask          */
-#define GPIO_PORT_SET4_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET4: SETP7 Position      */
-#define GPIO_PORT_SET4_SETP7_Msk                              (0x01UL << GPIO_PORT_SET4_SETP7_Pos)                      /*!< GPIO_PORT SET4: SETP7 Mask          */
-#define GPIO_PORT_SET4_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET4: SETP8 Position      */
-#define GPIO_PORT_SET4_SETP8_Msk                              (0x01UL << GPIO_PORT_SET4_SETP8_Pos)                      /*!< GPIO_PORT SET4: SETP8 Mask          */
-#define GPIO_PORT_SET4_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET4: SETP9 Position      */
-#define GPIO_PORT_SET4_SETP9_Msk                              (0x01UL << GPIO_PORT_SET4_SETP9_Pos)                      /*!< GPIO_PORT SET4: SETP9 Mask          */
-#define GPIO_PORT_SET4_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET4: SETP10 Position     */
-#define GPIO_PORT_SET4_SETP10_Msk                             (0x01UL << GPIO_PORT_SET4_SETP10_Pos)                     /*!< GPIO_PORT SET4: SETP10 Mask         */
-#define GPIO_PORT_SET4_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET4: SETP11 Position     */
-#define GPIO_PORT_SET4_SETP11_Msk                             (0x01UL << GPIO_PORT_SET4_SETP11_Pos)                     /*!< GPIO_PORT SET4: SETP11 Mask         */
-#define GPIO_PORT_SET4_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET4: SETP12 Position     */
-#define GPIO_PORT_SET4_SETP12_Msk                             (0x01UL << GPIO_PORT_SET4_SETP12_Pos)                     /*!< GPIO_PORT SET4: SETP12 Mask         */
-#define GPIO_PORT_SET4_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET4: SETP13 Position     */
-#define GPIO_PORT_SET4_SETP13_Msk                             (0x01UL << GPIO_PORT_SET4_SETP13_Pos)                     /*!< GPIO_PORT SET4: SETP13 Mask         */
-#define GPIO_PORT_SET4_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET4: SETP14 Position     */
-#define GPIO_PORT_SET4_SETP14_Msk                             (0x01UL << GPIO_PORT_SET4_SETP14_Pos)                     /*!< GPIO_PORT SET4: SETP14 Mask         */
-#define GPIO_PORT_SET4_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET4: SETP15 Position     */
-#define GPIO_PORT_SET4_SETP15_Msk                             (0x01UL << GPIO_PORT_SET4_SETP15_Pos)                     /*!< GPIO_PORT SET4: SETP15 Mask         */
-#define GPIO_PORT_SET4_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET4: SETP16 Position     */
-#define GPIO_PORT_SET4_SETP16_Msk                             (0x01UL << GPIO_PORT_SET4_SETP16_Pos)                     /*!< GPIO_PORT SET4: SETP16 Mask         */
-#define GPIO_PORT_SET4_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET4: SETP17 Position     */
-#define GPIO_PORT_SET4_SETP17_Msk                             (0x01UL << GPIO_PORT_SET4_SETP17_Pos)                     /*!< GPIO_PORT SET4: SETP17 Mask         */
-#define GPIO_PORT_SET4_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET4: SETP18 Position     */
-#define GPIO_PORT_SET4_SETP18_Msk                             (0x01UL << GPIO_PORT_SET4_SETP18_Pos)                     /*!< GPIO_PORT SET4: SETP18 Mask         */
-#define GPIO_PORT_SET4_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET4: SETP19 Position     */
-#define GPIO_PORT_SET4_SETP19_Msk                             (0x01UL << GPIO_PORT_SET4_SETP19_Pos)                     /*!< GPIO_PORT SET4: SETP19 Mask         */
-#define GPIO_PORT_SET4_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET4: SETP20 Position     */
-#define GPIO_PORT_SET4_SETP20_Msk                             (0x01UL << GPIO_PORT_SET4_SETP20_Pos)                     /*!< GPIO_PORT SET4: SETP20 Mask         */
-#define GPIO_PORT_SET4_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET4: SETP21 Position     */
-#define GPIO_PORT_SET4_SETP21_Msk                             (0x01UL << GPIO_PORT_SET4_SETP21_Pos)                     /*!< GPIO_PORT SET4: SETP21 Mask         */
-#define GPIO_PORT_SET4_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET4: SETP22 Position     */
-#define GPIO_PORT_SET4_SETP22_Msk                             (0x01UL << GPIO_PORT_SET4_SETP22_Pos)                     /*!< GPIO_PORT SET4: SETP22 Mask         */
-#define GPIO_PORT_SET4_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET4: SETP23 Position     */
-#define GPIO_PORT_SET4_SETP23_Msk                             (0x01UL << GPIO_PORT_SET4_SETP23_Pos)                     /*!< GPIO_PORT SET4: SETP23 Mask         */
-#define GPIO_PORT_SET4_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET4: SETP24 Position     */
-#define GPIO_PORT_SET4_SETP24_Msk                             (0x01UL << GPIO_PORT_SET4_SETP24_Pos)                     /*!< GPIO_PORT SET4: SETP24 Mask         */
-#define GPIO_PORT_SET4_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET4: SETP25 Position     */
-#define GPIO_PORT_SET4_SETP25_Msk                             (0x01UL << GPIO_PORT_SET4_SETP25_Pos)                     /*!< GPIO_PORT SET4: SETP25 Mask         */
-#define GPIO_PORT_SET4_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET4: SETP26 Position     */
-#define GPIO_PORT_SET4_SETP26_Msk                             (0x01UL << GPIO_PORT_SET4_SETP26_Pos)                     /*!< GPIO_PORT SET4: SETP26 Mask         */
-#define GPIO_PORT_SET4_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET4: SETP27 Position     */
-#define GPIO_PORT_SET4_SETP27_Msk                             (0x01UL << GPIO_PORT_SET4_SETP27_Pos)                     /*!< GPIO_PORT SET4: SETP27 Mask         */
-#define GPIO_PORT_SET4_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET4: SETP28 Position     */
-#define GPIO_PORT_SET4_SETP28_Msk                             (0x01UL << GPIO_PORT_SET4_SETP28_Pos)                     /*!< GPIO_PORT SET4: SETP28 Mask         */
-#define GPIO_PORT_SET4_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET4: SETP29 Position     */
-#define GPIO_PORT_SET4_SETP29_Msk                             (0x01UL << GPIO_PORT_SET4_SETP29_Pos)                     /*!< GPIO_PORT SET4: SETP29 Mask         */
-#define GPIO_PORT_SET4_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET4: SETP30 Position     */
-#define GPIO_PORT_SET4_SETP30_Msk                             (0x01UL << GPIO_PORT_SET4_SETP30_Pos)                     /*!< GPIO_PORT SET4: SETP30 Mask         */
-#define GPIO_PORT_SET4_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET4: SETP31 Position     */
-#define GPIO_PORT_SET4_SETP31_Msk                             (0x01UL << GPIO_PORT_SET4_SETP31_Pos)                     /*!< GPIO_PORT SET4: SETP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_SET5  -----------------------------------------
-#define GPIO_PORT_SET5_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET5: SETP0 Position      */
-#define GPIO_PORT_SET5_SETP0_Msk                              (0x01UL << GPIO_PORT_SET5_SETP0_Pos)                      /*!< GPIO_PORT SET5: SETP0 Mask          */
-#define GPIO_PORT_SET5_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET5: SETP1 Position      */
-#define GPIO_PORT_SET5_SETP1_Msk                              (0x01UL << GPIO_PORT_SET5_SETP1_Pos)                      /*!< GPIO_PORT SET5: SETP1 Mask          */
-#define GPIO_PORT_SET5_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET5: SETP2 Position      */
-#define GPIO_PORT_SET5_SETP2_Msk                              (0x01UL << GPIO_PORT_SET5_SETP2_Pos)                      /*!< GPIO_PORT SET5: SETP2 Mask          */
-#define GPIO_PORT_SET5_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET5: SETP3 Position      */
-#define GPIO_PORT_SET5_SETP3_Msk                              (0x01UL << GPIO_PORT_SET5_SETP3_Pos)                      /*!< GPIO_PORT SET5: SETP3 Mask          */
-#define GPIO_PORT_SET5_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET5: SETP4 Position      */
-#define GPIO_PORT_SET5_SETP4_Msk                              (0x01UL << GPIO_PORT_SET5_SETP4_Pos)                      /*!< GPIO_PORT SET5: SETP4 Mask          */
-#define GPIO_PORT_SET5_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET5: SETP5 Position      */
-#define GPIO_PORT_SET5_SETP5_Msk                              (0x01UL << GPIO_PORT_SET5_SETP5_Pos)                      /*!< GPIO_PORT SET5: SETP5 Mask          */
-#define GPIO_PORT_SET5_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET5: SETP6 Position      */
-#define GPIO_PORT_SET5_SETP6_Msk                              (0x01UL << GPIO_PORT_SET5_SETP6_Pos)                      /*!< GPIO_PORT SET5: SETP6 Mask          */
-#define GPIO_PORT_SET5_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET5: SETP7 Position      */
-#define GPIO_PORT_SET5_SETP7_Msk                              (0x01UL << GPIO_PORT_SET5_SETP7_Pos)                      /*!< GPIO_PORT SET5: SETP7 Mask          */
-#define GPIO_PORT_SET5_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET5: SETP8 Position      */
-#define GPIO_PORT_SET5_SETP8_Msk                              (0x01UL << GPIO_PORT_SET5_SETP8_Pos)                      /*!< GPIO_PORT SET5: SETP8 Mask          */
-#define GPIO_PORT_SET5_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET5: SETP9 Position      */
-#define GPIO_PORT_SET5_SETP9_Msk                              (0x01UL << GPIO_PORT_SET5_SETP9_Pos)                      /*!< GPIO_PORT SET5: SETP9 Mask          */
-#define GPIO_PORT_SET5_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET5: SETP10 Position     */
-#define GPIO_PORT_SET5_SETP10_Msk                             (0x01UL << GPIO_PORT_SET5_SETP10_Pos)                     /*!< GPIO_PORT SET5: SETP10 Mask         */
-#define GPIO_PORT_SET5_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET5: SETP11 Position     */
-#define GPIO_PORT_SET5_SETP11_Msk                             (0x01UL << GPIO_PORT_SET5_SETP11_Pos)                     /*!< GPIO_PORT SET5: SETP11 Mask         */
-#define GPIO_PORT_SET5_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET5: SETP12 Position     */
-#define GPIO_PORT_SET5_SETP12_Msk                             (0x01UL << GPIO_PORT_SET5_SETP12_Pos)                     /*!< GPIO_PORT SET5: SETP12 Mask         */
-#define GPIO_PORT_SET5_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET5: SETP13 Position     */
-#define GPIO_PORT_SET5_SETP13_Msk                             (0x01UL << GPIO_PORT_SET5_SETP13_Pos)                     /*!< GPIO_PORT SET5: SETP13 Mask         */
-#define GPIO_PORT_SET5_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET5: SETP14 Position     */
-#define GPIO_PORT_SET5_SETP14_Msk                             (0x01UL << GPIO_PORT_SET5_SETP14_Pos)                     /*!< GPIO_PORT SET5: SETP14 Mask         */
-#define GPIO_PORT_SET5_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET5: SETP15 Position     */
-#define GPIO_PORT_SET5_SETP15_Msk                             (0x01UL << GPIO_PORT_SET5_SETP15_Pos)                     /*!< GPIO_PORT SET5: SETP15 Mask         */
-#define GPIO_PORT_SET5_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET5: SETP16 Position     */
-#define GPIO_PORT_SET5_SETP16_Msk                             (0x01UL << GPIO_PORT_SET5_SETP16_Pos)                     /*!< GPIO_PORT SET5: SETP16 Mask         */
-#define GPIO_PORT_SET5_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET5: SETP17 Position     */
-#define GPIO_PORT_SET5_SETP17_Msk                             (0x01UL << GPIO_PORT_SET5_SETP17_Pos)                     /*!< GPIO_PORT SET5: SETP17 Mask         */
-#define GPIO_PORT_SET5_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET5: SETP18 Position     */
-#define GPIO_PORT_SET5_SETP18_Msk                             (0x01UL << GPIO_PORT_SET5_SETP18_Pos)                     /*!< GPIO_PORT SET5: SETP18 Mask         */
-#define GPIO_PORT_SET5_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET5: SETP19 Position     */
-#define GPIO_PORT_SET5_SETP19_Msk                             (0x01UL << GPIO_PORT_SET5_SETP19_Pos)                     /*!< GPIO_PORT SET5: SETP19 Mask         */
-#define GPIO_PORT_SET5_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET5: SETP20 Position     */
-#define GPIO_PORT_SET5_SETP20_Msk                             (0x01UL << GPIO_PORT_SET5_SETP20_Pos)                     /*!< GPIO_PORT SET5: SETP20 Mask         */
-#define GPIO_PORT_SET5_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET5: SETP21 Position     */
-#define GPIO_PORT_SET5_SETP21_Msk                             (0x01UL << GPIO_PORT_SET5_SETP21_Pos)                     /*!< GPIO_PORT SET5: SETP21 Mask         */
-#define GPIO_PORT_SET5_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET5: SETP22 Position     */
-#define GPIO_PORT_SET5_SETP22_Msk                             (0x01UL << GPIO_PORT_SET5_SETP22_Pos)                     /*!< GPIO_PORT SET5: SETP22 Mask         */
-#define GPIO_PORT_SET5_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET5: SETP23 Position     */
-#define GPIO_PORT_SET5_SETP23_Msk                             (0x01UL << GPIO_PORT_SET5_SETP23_Pos)                     /*!< GPIO_PORT SET5: SETP23 Mask         */
-#define GPIO_PORT_SET5_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET5: SETP24 Position     */
-#define GPIO_PORT_SET5_SETP24_Msk                             (0x01UL << GPIO_PORT_SET5_SETP24_Pos)                     /*!< GPIO_PORT SET5: SETP24 Mask         */
-#define GPIO_PORT_SET5_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET5: SETP25 Position     */
-#define GPIO_PORT_SET5_SETP25_Msk                             (0x01UL << GPIO_PORT_SET5_SETP25_Pos)                     /*!< GPIO_PORT SET5: SETP25 Mask         */
-#define GPIO_PORT_SET5_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET5: SETP26 Position     */
-#define GPIO_PORT_SET5_SETP26_Msk                             (0x01UL << GPIO_PORT_SET5_SETP26_Pos)                     /*!< GPIO_PORT SET5: SETP26 Mask         */
-#define GPIO_PORT_SET5_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET5: SETP27 Position     */
-#define GPIO_PORT_SET5_SETP27_Msk                             (0x01UL << GPIO_PORT_SET5_SETP27_Pos)                     /*!< GPIO_PORT SET5: SETP27 Mask         */
-#define GPIO_PORT_SET5_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET5: SETP28 Position     */
-#define GPIO_PORT_SET5_SETP28_Msk                             (0x01UL << GPIO_PORT_SET5_SETP28_Pos)                     /*!< GPIO_PORT SET5: SETP28 Mask         */
-#define GPIO_PORT_SET5_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET5: SETP29 Position     */
-#define GPIO_PORT_SET5_SETP29_Msk                             (0x01UL << GPIO_PORT_SET5_SETP29_Pos)                     /*!< GPIO_PORT SET5: SETP29 Mask         */
-#define GPIO_PORT_SET5_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET5: SETP30 Position     */
-#define GPIO_PORT_SET5_SETP30_Msk                             (0x01UL << GPIO_PORT_SET5_SETP30_Pos)                     /*!< GPIO_PORT SET5: SETP30 Mask         */
-#define GPIO_PORT_SET5_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET5: SETP31 Position     */
-#define GPIO_PORT_SET5_SETP31_Msk                             (0x01UL << GPIO_PORT_SET5_SETP31_Pos)                     /*!< GPIO_PORT SET5: SETP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_SET6  -----------------------------------------
-#define GPIO_PORT_SET6_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET6: SETP0 Position      */
-#define GPIO_PORT_SET6_SETP0_Msk                              (0x01UL << GPIO_PORT_SET6_SETP0_Pos)                      /*!< GPIO_PORT SET6: SETP0 Mask          */
-#define GPIO_PORT_SET6_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET6: SETP1 Position      */
-#define GPIO_PORT_SET6_SETP1_Msk                              (0x01UL << GPIO_PORT_SET6_SETP1_Pos)                      /*!< GPIO_PORT SET6: SETP1 Mask          */
-#define GPIO_PORT_SET6_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET6: SETP2 Position      */
-#define GPIO_PORT_SET6_SETP2_Msk                              (0x01UL << GPIO_PORT_SET6_SETP2_Pos)                      /*!< GPIO_PORT SET6: SETP2 Mask          */
-#define GPIO_PORT_SET6_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET6: SETP3 Position      */
-#define GPIO_PORT_SET6_SETP3_Msk                              (0x01UL << GPIO_PORT_SET6_SETP3_Pos)                      /*!< GPIO_PORT SET6: SETP3 Mask          */
-#define GPIO_PORT_SET6_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET6: SETP4 Position      */
-#define GPIO_PORT_SET6_SETP4_Msk                              (0x01UL << GPIO_PORT_SET6_SETP4_Pos)                      /*!< GPIO_PORT SET6: SETP4 Mask          */
-#define GPIO_PORT_SET6_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET6: SETP5 Position      */
-#define GPIO_PORT_SET6_SETP5_Msk                              (0x01UL << GPIO_PORT_SET6_SETP5_Pos)                      /*!< GPIO_PORT SET6: SETP5 Mask          */
-#define GPIO_PORT_SET6_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET6: SETP6 Position      */
-#define GPIO_PORT_SET6_SETP6_Msk                              (0x01UL << GPIO_PORT_SET6_SETP6_Pos)                      /*!< GPIO_PORT SET6: SETP6 Mask          */
-#define GPIO_PORT_SET6_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET6: SETP7 Position      */
-#define GPIO_PORT_SET6_SETP7_Msk                              (0x01UL << GPIO_PORT_SET6_SETP7_Pos)                      /*!< GPIO_PORT SET6: SETP7 Mask          */
-#define GPIO_PORT_SET6_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET6: SETP8 Position      */
-#define GPIO_PORT_SET6_SETP8_Msk                              (0x01UL << GPIO_PORT_SET6_SETP8_Pos)                      /*!< GPIO_PORT SET6: SETP8 Mask          */
-#define GPIO_PORT_SET6_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET6: SETP9 Position      */
-#define GPIO_PORT_SET6_SETP9_Msk                              (0x01UL << GPIO_PORT_SET6_SETP9_Pos)                      /*!< GPIO_PORT SET6: SETP9 Mask          */
-#define GPIO_PORT_SET6_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET6: SETP10 Position     */
-#define GPIO_PORT_SET6_SETP10_Msk                             (0x01UL << GPIO_PORT_SET6_SETP10_Pos)                     /*!< GPIO_PORT SET6: SETP10 Mask         */
-#define GPIO_PORT_SET6_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET6: SETP11 Position     */
-#define GPIO_PORT_SET6_SETP11_Msk                             (0x01UL << GPIO_PORT_SET6_SETP11_Pos)                     /*!< GPIO_PORT SET6: SETP11 Mask         */
-#define GPIO_PORT_SET6_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET6: SETP12 Position     */
-#define GPIO_PORT_SET6_SETP12_Msk                             (0x01UL << GPIO_PORT_SET6_SETP12_Pos)                     /*!< GPIO_PORT SET6: SETP12 Mask         */
-#define GPIO_PORT_SET6_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET6: SETP13 Position     */
-#define GPIO_PORT_SET6_SETP13_Msk                             (0x01UL << GPIO_PORT_SET6_SETP13_Pos)                     /*!< GPIO_PORT SET6: SETP13 Mask         */
-#define GPIO_PORT_SET6_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET6: SETP14 Position     */
-#define GPIO_PORT_SET6_SETP14_Msk                             (0x01UL << GPIO_PORT_SET6_SETP14_Pos)                     /*!< GPIO_PORT SET6: SETP14 Mask         */
-#define GPIO_PORT_SET6_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET6: SETP15 Position     */
-#define GPIO_PORT_SET6_SETP15_Msk                             (0x01UL << GPIO_PORT_SET6_SETP15_Pos)                     /*!< GPIO_PORT SET6: SETP15 Mask         */
-#define GPIO_PORT_SET6_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET6: SETP16 Position     */
-#define GPIO_PORT_SET6_SETP16_Msk                             (0x01UL << GPIO_PORT_SET6_SETP16_Pos)                     /*!< GPIO_PORT SET6: SETP16 Mask         */
-#define GPIO_PORT_SET6_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET6: SETP17 Position     */
-#define GPIO_PORT_SET6_SETP17_Msk                             (0x01UL << GPIO_PORT_SET6_SETP17_Pos)                     /*!< GPIO_PORT SET6: SETP17 Mask         */
-#define GPIO_PORT_SET6_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET6: SETP18 Position     */
-#define GPIO_PORT_SET6_SETP18_Msk                             (0x01UL << GPIO_PORT_SET6_SETP18_Pos)                     /*!< GPIO_PORT SET6: SETP18 Mask         */
-#define GPIO_PORT_SET6_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET6: SETP19 Position     */
-#define GPIO_PORT_SET6_SETP19_Msk                             (0x01UL << GPIO_PORT_SET6_SETP19_Pos)                     /*!< GPIO_PORT SET6: SETP19 Mask         */
-#define GPIO_PORT_SET6_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET6: SETP20 Position     */
-#define GPIO_PORT_SET6_SETP20_Msk                             (0x01UL << GPIO_PORT_SET6_SETP20_Pos)                     /*!< GPIO_PORT SET6: SETP20 Mask         */
-#define GPIO_PORT_SET6_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET6: SETP21 Position     */
-#define GPIO_PORT_SET6_SETP21_Msk                             (0x01UL << GPIO_PORT_SET6_SETP21_Pos)                     /*!< GPIO_PORT SET6: SETP21 Mask         */
-#define GPIO_PORT_SET6_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET6: SETP22 Position     */
-#define GPIO_PORT_SET6_SETP22_Msk                             (0x01UL << GPIO_PORT_SET6_SETP22_Pos)                     /*!< GPIO_PORT SET6: SETP22 Mask         */
-#define GPIO_PORT_SET6_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET6: SETP23 Position     */
-#define GPIO_PORT_SET6_SETP23_Msk                             (0x01UL << GPIO_PORT_SET6_SETP23_Pos)                     /*!< GPIO_PORT SET6: SETP23 Mask         */
-#define GPIO_PORT_SET6_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET6: SETP24 Position     */
-#define GPIO_PORT_SET6_SETP24_Msk                             (0x01UL << GPIO_PORT_SET6_SETP24_Pos)                     /*!< GPIO_PORT SET6: SETP24 Mask         */
-#define GPIO_PORT_SET6_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET6: SETP25 Position     */
-#define GPIO_PORT_SET6_SETP25_Msk                             (0x01UL << GPIO_PORT_SET6_SETP25_Pos)                     /*!< GPIO_PORT SET6: SETP25 Mask         */
-#define GPIO_PORT_SET6_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET6: SETP26 Position     */
-#define GPIO_PORT_SET6_SETP26_Msk                             (0x01UL << GPIO_PORT_SET6_SETP26_Pos)                     /*!< GPIO_PORT SET6: SETP26 Mask         */
-#define GPIO_PORT_SET6_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET6: SETP27 Position     */
-#define GPIO_PORT_SET6_SETP27_Msk                             (0x01UL << GPIO_PORT_SET6_SETP27_Pos)                     /*!< GPIO_PORT SET6: SETP27 Mask         */
-#define GPIO_PORT_SET6_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET6: SETP28 Position     */
-#define GPIO_PORT_SET6_SETP28_Msk                             (0x01UL << GPIO_PORT_SET6_SETP28_Pos)                     /*!< GPIO_PORT SET6: SETP28 Mask         */
-#define GPIO_PORT_SET6_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET6: SETP29 Position     */
-#define GPIO_PORT_SET6_SETP29_Msk                             (0x01UL << GPIO_PORT_SET6_SETP29_Pos)                     /*!< GPIO_PORT SET6: SETP29 Mask         */
-#define GPIO_PORT_SET6_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET6: SETP30 Position     */
-#define GPIO_PORT_SET6_SETP30_Msk                             (0x01UL << GPIO_PORT_SET6_SETP30_Pos)                     /*!< GPIO_PORT SET6: SETP30 Mask         */
-#define GPIO_PORT_SET6_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET6: SETP31 Position     */
-#define GPIO_PORT_SET6_SETP31_Msk                             (0x01UL << GPIO_PORT_SET6_SETP31_Pos)                     /*!< GPIO_PORT SET6: SETP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_SET7  -----------------------------------------
-#define GPIO_PORT_SET7_SETP0_Pos                              0                                                         /*!< GPIO_PORT SET7: SETP0 Position      */
-#define GPIO_PORT_SET7_SETP0_Msk                              (0x01UL << GPIO_PORT_SET7_SETP0_Pos)                      /*!< GPIO_PORT SET7: SETP0 Mask          */
-#define GPIO_PORT_SET7_SETP1_Pos                              1                                                         /*!< GPIO_PORT SET7: SETP1 Position      */
-#define GPIO_PORT_SET7_SETP1_Msk                              (0x01UL << GPIO_PORT_SET7_SETP1_Pos)                      /*!< GPIO_PORT SET7: SETP1 Mask          */
-#define GPIO_PORT_SET7_SETP2_Pos                              2                                                         /*!< GPIO_PORT SET7: SETP2 Position      */
-#define GPIO_PORT_SET7_SETP2_Msk                              (0x01UL << GPIO_PORT_SET7_SETP2_Pos)                      /*!< GPIO_PORT SET7: SETP2 Mask          */
-#define GPIO_PORT_SET7_SETP3_Pos                              3                                                         /*!< GPIO_PORT SET7: SETP3 Position      */
-#define GPIO_PORT_SET7_SETP3_Msk                              (0x01UL << GPIO_PORT_SET7_SETP3_Pos)                      /*!< GPIO_PORT SET7: SETP3 Mask          */
-#define GPIO_PORT_SET7_SETP4_Pos                              4                                                         /*!< GPIO_PORT SET7: SETP4 Position      */
-#define GPIO_PORT_SET7_SETP4_Msk                              (0x01UL << GPIO_PORT_SET7_SETP4_Pos)                      /*!< GPIO_PORT SET7: SETP4 Mask          */
-#define GPIO_PORT_SET7_SETP5_Pos                              5                                                         /*!< GPIO_PORT SET7: SETP5 Position      */
-#define GPIO_PORT_SET7_SETP5_Msk                              (0x01UL << GPIO_PORT_SET7_SETP5_Pos)                      /*!< GPIO_PORT SET7: SETP5 Mask          */
-#define GPIO_PORT_SET7_SETP6_Pos                              6                                                         /*!< GPIO_PORT SET7: SETP6 Position      */
-#define GPIO_PORT_SET7_SETP6_Msk                              (0x01UL << GPIO_PORT_SET7_SETP6_Pos)                      /*!< GPIO_PORT SET7: SETP6 Mask          */
-#define GPIO_PORT_SET7_SETP7_Pos                              7                                                         /*!< GPIO_PORT SET7: SETP7 Position      */
-#define GPIO_PORT_SET7_SETP7_Msk                              (0x01UL << GPIO_PORT_SET7_SETP7_Pos)                      /*!< GPIO_PORT SET7: SETP7 Mask          */
-#define GPIO_PORT_SET7_SETP8_Pos                              8                                                         /*!< GPIO_PORT SET7: SETP8 Position      */
-#define GPIO_PORT_SET7_SETP8_Msk                              (0x01UL << GPIO_PORT_SET7_SETP8_Pos)                      /*!< GPIO_PORT SET7: SETP8 Mask          */
-#define GPIO_PORT_SET7_SETP9_Pos                              9                                                         /*!< GPIO_PORT SET7: SETP9 Position      */
-#define GPIO_PORT_SET7_SETP9_Msk                              (0x01UL << GPIO_PORT_SET7_SETP9_Pos)                      /*!< GPIO_PORT SET7: SETP9 Mask          */
-#define GPIO_PORT_SET7_SETP10_Pos                             10                                                        /*!< GPIO_PORT SET7: SETP10 Position     */
-#define GPIO_PORT_SET7_SETP10_Msk                             (0x01UL << GPIO_PORT_SET7_SETP10_Pos)                     /*!< GPIO_PORT SET7: SETP10 Mask         */
-#define GPIO_PORT_SET7_SETP11_Pos                             11                                                        /*!< GPIO_PORT SET7: SETP11 Position     */
-#define GPIO_PORT_SET7_SETP11_Msk                             (0x01UL << GPIO_PORT_SET7_SETP11_Pos)                     /*!< GPIO_PORT SET7: SETP11 Mask         */
-#define GPIO_PORT_SET7_SETP12_Pos                             12                                                        /*!< GPIO_PORT SET7: SETP12 Position     */
-#define GPIO_PORT_SET7_SETP12_Msk                             (0x01UL << GPIO_PORT_SET7_SETP12_Pos)                     /*!< GPIO_PORT SET7: SETP12 Mask         */
-#define GPIO_PORT_SET7_SETP13_Pos                             13                                                        /*!< GPIO_PORT SET7: SETP13 Position     */
-#define GPIO_PORT_SET7_SETP13_Msk                             (0x01UL << GPIO_PORT_SET7_SETP13_Pos)                     /*!< GPIO_PORT SET7: SETP13 Mask         */
-#define GPIO_PORT_SET7_SETP14_Pos                             14                                                        /*!< GPIO_PORT SET7: SETP14 Position     */
-#define GPIO_PORT_SET7_SETP14_Msk                             (0x01UL << GPIO_PORT_SET7_SETP14_Pos)                     /*!< GPIO_PORT SET7: SETP14 Mask         */
-#define GPIO_PORT_SET7_SETP15_Pos                             15                                                        /*!< GPIO_PORT SET7: SETP15 Position     */
-#define GPIO_PORT_SET7_SETP15_Msk                             (0x01UL << GPIO_PORT_SET7_SETP15_Pos)                     /*!< GPIO_PORT SET7: SETP15 Mask         */
-#define GPIO_PORT_SET7_SETP16_Pos                             16                                                        /*!< GPIO_PORT SET7: SETP16 Position     */
-#define GPIO_PORT_SET7_SETP16_Msk                             (0x01UL << GPIO_PORT_SET7_SETP16_Pos)                     /*!< GPIO_PORT SET7: SETP16 Mask         */
-#define GPIO_PORT_SET7_SETP17_Pos                             17                                                        /*!< GPIO_PORT SET7: SETP17 Position     */
-#define GPIO_PORT_SET7_SETP17_Msk                             (0x01UL << GPIO_PORT_SET7_SETP17_Pos)                     /*!< GPIO_PORT SET7: SETP17 Mask         */
-#define GPIO_PORT_SET7_SETP18_Pos                             18                                                        /*!< GPIO_PORT SET7: SETP18 Position     */
-#define GPIO_PORT_SET7_SETP18_Msk                             (0x01UL << GPIO_PORT_SET7_SETP18_Pos)                     /*!< GPIO_PORT SET7: SETP18 Mask         */
-#define GPIO_PORT_SET7_SETP19_Pos                             19                                                        /*!< GPIO_PORT SET7: SETP19 Position     */
-#define GPIO_PORT_SET7_SETP19_Msk                             (0x01UL << GPIO_PORT_SET7_SETP19_Pos)                     /*!< GPIO_PORT SET7: SETP19 Mask         */
-#define GPIO_PORT_SET7_SETP20_Pos                             20                                                        /*!< GPIO_PORT SET7: SETP20 Position     */
-#define GPIO_PORT_SET7_SETP20_Msk                             (0x01UL << GPIO_PORT_SET7_SETP20_Pos)                     /*!< GPIO_PORT SET7: SETP20 Mask         */
-#define GPIO_PORT_SET7_SETP21_Pos                             21                                                        /*!< GPIO_PORT SET7: SETP21 Position     */
-#define GPIO_PORT_SET7_SETP21_Msk                             (0x01UL << GPIO_PORT_SET7_SETP21_Pos)                     /*!< GPIO_PORT SET7: SETP21 Mask         */
-#define GPIO_PORT_SET7_SETP22_Pos                             22                                                        /*!< GPIO_PORT SET7: SETP22 Position     */
-#define GPIO_PORT_SET7_SETP22_Msk                             (0x01UL << GPIO_PORT_SET7_SETP22_Pos)                     /*!< GPIO_PORT SET7: SETP22 Mask         */
-#define GPIO_PORT_SET7_SETP23_Pos                             23                                                        /*!< GPIO_PORT SET7: SETP23 Position     */
-#define GPIO_PORT_SET7_SETP23_Msk                             (0x01UL << GPIO_PORT_SET7_SETP23_Pos)                     /*!< GPIO_PORT SET7: SETP23 Mask         */
-#define GPIO_PORT_SET7_SETP24_Pos                             24                                                        /*!< GPIO_PORT SET7: SETP24 Position     */
-#define GPIO_PORT_SET7_SETP24_Msk                             (0x01UL << GPIO_PORT_SET7_SETP24_Pos)                     /*!< GPIO_PORT SET7: SETP24 Mask         */
-#define GPIO_PORT_SET7_SETP25_Pos                             25                                                        /*!< GPIO_PORT SET7: SETP25 Position     */
-#define GPIO_PORT_SET7_SETP25_Msk                             (0x01UL << GPIO_PORT_SET7_SETP25_Pos)                     /*!< GPIO_PORT SET7: SETP25 Mask         */
-#define GPIO_PORT_SET7_SETP26_Pos                             26                                                        /*!< GPIO_PORT SET7: SETP26 Position     */
-#define GPIO_PORT_SET7_SETP26_Msk                             (0x01UL << GPIO_PORT_SET7_SETP26_Pos)                     /*!< GPIO_PORT SET7: SETP26 Mask         */
-#define GPIO_PORT_SET7_SETP27_Pos                             27                                                        /*!< GPIO_PORT SET7: SETP27 Position     */
-#define GPIO_PORT_SET7_SETP27_Msk                             (0x01UL << GPIO_PORT_SET7_SETP27_Pos)                     /*!< GPIO_PORT SET7: SETP27 Mask         */
-#define GPIO_PORT_SET7_SETP28_Pos                             28                                                        /*!< GPIO_PORT SET7: SETP28 Position     */
-#define GPIO_PORT_SET7_SETP28_Msk                             (0x01UL << GPIO_PORT_SET7_SETP28_Pos)                     /*!< GPIO_PORT SET7: SETP28 Mask         */
-#define GPIO_PORT_SET7_SETP29_Pos                             29                                                        /*!< GPIO_PORT SET7: SETP29 Position     */
-#define GPIO_PORT_SET7_SETP29_Msk                             (0x01UL << GPIO_PORT_SET7_SETP29_Pos)                     /*!< GPIO_PORT SET7: SETP29 Mask         */
-#define GPIO_PORT_SET7_SETP30_Pos                             30                                                        /*!< GPIO_PORT SET7: SETP30 Position     */
-#define GPIO_PORT_SET7_SETP30_Msk                             (0x01UL << GPIO_PORT_SET7_SETP30_Pos)                     /*!< GPIO_PORT SET7: SETP30 Mask         */
-#define GPIO_PORT_SET7_SETP31_Pos                             31                                                        /*!< GPIO_PORT SET7: SETP31 Position     */
-#define GPIO_PORT_SET7_SETP31_Msk                             (0x01UL << GPIO_PORT_SET7_SETP31_Pos)                     /*!< GPIO_PORT SET7: SETP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_CLR0  -----------------------------------------
-#define GPIO_PORT_CLR0_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR0: CLRP00 Position     */
-#define GPIO_PORT_CLR0_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP00_Pos)                     /*!< GPIO_PORT CLR0: CLRP00 Mask         */
-#define GPIO_PORT_CLR0_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR0: CLRP01 Position     */
-#define GPIO_PORT_CLR0_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP01_Pos)                     /*!< GPIO_PORT CLR0: CLRP01 Mask         */
-#define GPIO_PORT_CLR0_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR0: CLRP02 Position     */
-#define GPIO_PORT_CLR0_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP02_Pos)                     /*!< GPIO_PORT CLR0: CLRP02 Mask         */
-#define GPIO_PORT_CLR0_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR0: CLRP03 Position     */
-#define GPIO_PORT_CLR0_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP03_Pos)                     /*!< GPIO_PORT CLR0: CLRP03 Mask         */
-#define GPIO_PORT_CLR0_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR0: CLRP04 Position     */
-#define GPIO_PORT_CLR0_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP04_Pos)                     /*!< GPIO_PORT CLR0: CLRP04 Mask         */
-#define GPIO_PORT_CLR0_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR0: CLRP05 Position     */
-#define GPIO_PORT_CLR0_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP05_Pos)                     /*!< GPIO_PORT CLR0: CLRP05 Mask         */
-#define GPIO_PORT_CLR0_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR0: CLRP06 Position     */
-#define GPIO_PORT_CLR0_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP06_Pos)                     /*!< GPIO_PORT CLR0: CLRP06 Mask         */
-#define GPIO_PORT_CLR0_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR0: CLRP07 Position     */
-#define GPIO_PORT_CLR0_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP07_Pos)                     /*!< GPIO_PORT CLR0: CLRP07 Mask         */
-#define GPIO_PORT_CLR0_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR0: CLRP08 Position     */
-#define GPIO_PORT_CLR0_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP08_Pos)                     /*!< GPIO_PORT CLR0: CLRP08 Mask         */
-#define GPIO_PORT_CLR0_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR0: CLRP09 Position     */
-#define GPIO_PORT_CLR0_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP09_Pos)                     /*!< GPIO_PORT CLR0: CLRP09 Mask         */
-#define GPIO_PORT_CLR0_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR0: CLRP010 Position    */
-#define GPIO_PORT_CLR0_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP010_Pos)                    /*!< GPIO_PORT CLR0: CLRP010 Mask        */
-#define GPIO_PORT_CLR0_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR0: CLRP011 Position    */
-#define GPIO_PORT_CLR0_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP011_Pos)                    /*!< GPIO_PORT CLR0: CLRP011 Mask        */
-#define GPIO_PORT_CLR0_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR0: CLRP012 Position    */
-#define GPIO_PORT_CLR0_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP012_Pos)                    /*!< GPIO_PORT CLR0: CLRP012 Mask        */
-#define GPIO_PORT_CLR0_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR0: CLRP013 Position    */
-#define GPIO_PORT_CLR0_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP013_Pos)                    /*!< GPIO_PORT CLR0: CLRP013 Mask        */
-#define GPIO_PORT_CLR0_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR0: CLRP014 Position    */
-#define GPIO_PORT_CLR0_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP014_Pos)                    /*!< GPIO_PORT CLR0: CLRP014 Mask        */
-#define GPIO_PORT_CLR0_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR0: CLRP015 Position    */
-#define GPIO_PORT_CLR0_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP015_Pos)                    /*!< GPIO_PORT CLR0: CLRP015 Mask        */
-#define GPIO_PORT_CLR0_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR0: CLRP016 Position    */
-#define GPIO_PORT_CLR0_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP016_Pos)                    /*!< GPIO_PORT CLR0: CLRP016 Mask        */
-#define GPIO_PORT_CLR0_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR0: CLRP017 Position    */
-#define GPIO_PORT_CLR0_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP017_Pos)                    /*!< GPIO_PORT CLR0: CLRP017 Mask        */
-#define GPIO_PORT_CLR0_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR0: CLRP018 Position    */
-#define GPIO_PORT_CLR0_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP018_Pos)                    /*!< GPIO_PORT CLR0: CLRP018 Mask        */
-#define GPIO_PORT_CLR0_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR0: CLRP019 Position    */
-#define GPIO_PORT_CLR0_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP019_Pos)                    /*!< GPIO_PORT CLR0: CLRP019 Mask        */
-#define GPIO_PORT_CLR0_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR0: CLRP020 Position    */
-#define GPIO_PORT_CLR0_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP020_Pos)                    /*!< GPIO_PORT CLR0: CLRP020 Mask        */
-#define GPIO_PORT_CLR0_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR0: CLRP021 Position    */
-#define GPIO_PORT_CLR0_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP021_Pos)                    /*!< GPIO_PORT CLR0: CLRP021 Mask        */
-#define GPIO_PORT_CLR0_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR0: CLRP022 Position    */
-#define GPIO_PORT_CLR0_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP022_Pos)                    /*!< GPIO_PORT CLR0: CLRP022 Mask        */
-#define GPIO_PORT_CLR0_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR0: CLRP023 Position    */
-#define GPIO_PORT_CLR0_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP023_Pos)                    /*!< GPIO_PORT CLR0: CLRP023 Mask        */
-#define GPIO_PORT_CLR0_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR0: CLRP024 Position    */
-#define GPIO_PORT_CLR0_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP024_Pos)                    /*!< GPIO_PORT CLR0: CLRP024 Mask        */
-#define GPIO_PORT_CLR0_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR0: CLRP025 Position    */
-#define GPIO_PORT_CLR0_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP025_Pos)                    /*!< GPIO_PORT CLR0: CLRP025 Mask        */
-#define GPIO_PORT_CLR0_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR0: CLRP026 Position    */
-#define GPIO_PORT_CLR0_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP026_Pos)                    /*!< GPIO_PORT CLR0: CLRP026 Mask        */
-#define GPIO_PORT_CLR0_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR0: CLRP027 Position    */
-#define GPIO_PORT_CLR0_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP027_Pos)                    /*!< GPIO_PORT CLR0: CLRP027 Mask        */
-#define GPIO_PORT_CLR0_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR0: CLRP028 Position    */
-#define GPIO_PORT_CLR0_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP028_Pos)                    /*!< GPIO_PORT CLR0: CLRP028 Mask        */
-#define GPIO_PORT_CLR0_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR0: CLRP029 Position    */
-#define GPIO_PORT_CLR0_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP029_Pos)                    /*!< GPIO_PORT CLR0: CLRP029 Mask        */
-#define GPIO_PORT_CLR0_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR0: CLRP030 Position    */
-#define GPIO_PORT_CLR0_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP030_Pos)                    /*!< GPIO_PORT CLR0: CLRP030 Mask        */
-#define GPIO_PORT_CLR0_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR0: CLRP031 Position    */
-#define GPIO_PORT_CLR0_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP031_Pos)                    /*!< GPIO_PORT CLR0: CLRP031 Mask        */
-
-// -------------------------------------  GPIO_PORT_CLR1  -----------------------------------------
-#define GPIO_PORT_CLR1_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR1: CLRP00 Position     */
-#define GPIO_PORT_CLR1_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP00_Pos)                     /*!< GPIO_PORT CLR1: CLRP00 Mask         */
-#define GPIO_PORT_CLR1_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR1: CLRP01 Position     */
-#define GPIO_PORT_CLR1_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP01_Pos)                     /*!< GPIO_PORT CLR1: CLRP01 Mask         */
-#define GPIO_PORT_CLR1_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR1: CLRP02 Position     */
-#define GPIO_PORT_CLR1_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP02_Pos)                     /*!< GPIO_PORT CLR1: CLRP02 Mask         */
-#define GPIO_PORT_CLR1_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR1: CLRP03 Position     */
-#define GPIO_PORT_CLR1_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP03_Pos)                     /*!< GPIO_PORT CLR1: CLRP03 Mask         */
-#define GPIO_PORT_CLR1_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR1: CLRP04 Position     */
-#define GPIO_PORT_CLR1_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP04_Pos)                     /*!< GPIO_PORT CLR1: CLRP04 Mask         */
-#define GPIO_PORT_CLR1_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR1: CLRP05 Position     */
-#define GPIO_PORT_CLR1_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP05_Pos)                     /*!< GPIO_PORT CLR1: CLRP05 Mask         */
-#define GPIO_PORT_CLR1_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR1: CLRP06 Position     */
-#define GPIO_PORT_CLR1_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP06_Pos)                     /*!< GPIO_PORT CLR1: CLRP06 Mask         */
-#define GPIO_PORT_CLR1_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR1: CLRP07 Position     */
-#define GPIO_PORT_CLR1_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP07_Pos)                     /*!< GPIO_PORT CLR1: CLRP07 Mask         */
-#define GPIO_PORT_CLR1_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR1: CLRP08 Position     */
-#define GPIO_PORT_CLR1_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP08_Pos)                     /*!< GPIO_PORT CLR1: CLRP08 Mask         */
-#define GPIO_PORT_CLR1_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR1: CLRP09 Position     */
-#define GPIO_PORT_CLR1_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP09_Pos)                     /*!< GPIO_PORT CLR1: CLRP09 Mask         */
-#define GPIO_PORT_CLR1_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR1: CLRP010 Position    */
-#define GPIO_PORT_CLR1_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP010_Pos)                    /*!< GPIO_PORT CLR1: CLRP010 Mask        */
-#define GPIO_PORT_CLR1_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR1: CLRP011 Position    */
-#define GPIO_PORT_CLR1_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP011_Pos)                    /*!< GPIO_PORT CLR1: CLRP011 Mask        */
-#define GPIO_PORT_CLR1_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR1: CLRP012 Position    */
-#define GPIO_PORT_CLR1_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP012_Pos)                    /*!< GPIO_PORT CLR1: CLRP012 Mask        */
-#define GPIO_PORT_CLR1_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR1: CLRP013 Position    */
-#define GPIO_PORT_CLR1_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP013_Pos)                    /*!< GPIO_PORT CLR1: CLRP013 Mask        */
-#define GPIO_PORT_CLR1_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR1: CLRP014 Position    */
-#define GPIO_PORT_CLR1_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP014_Pos)                    /*!< GPIO_PORT CLR1: CLRP014 Mask        */
-#define GPIO_PORT_CLR1_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR1: CLRP015 Position    */
-#define GPIO_PORT_CLR1_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP015_Pos)                    /*!< GPIO_PORT CLR1: CLRP015 Mask        */
-#define GPIO_PORT_CLR1_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR1: CLRP016 Position    */
-#define GPIO_PORT_CLR1_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP016_Pos)                    /*!< GPIO_PORT CLR1: CLRP016 Mask        */
-#define GPIO_PORT_CLR1_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR1: CLRP017 Position    */
-#define GPIO_PORT_CLR1_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP017_Pos)                    /*!< GPIO_PORT CLR1: CLRP017 Mask        */
-#define GPIO_PORT_CLR1_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR1: CLRP018 Position    */
-#define GPIO_PORT_CLR1_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP018_Pos)                    /*!< GPIO_PORT CLR1: CLRP018 Mask        */
-#define GPIO_PORT_CLR1_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR1: CLRP019 Position    */
-#define GPIO_PORT_CLR1_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP019_Pos)                    /*!< GPIO_PORT CLR1: CLRP019 Mask        */
-#define GPIO_PORT_CLR1_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR1: CLRP020 Position    */
-#define GPIO_PORT_CLR1_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP020_Pos)                    /*!< GPIO_PORT CLR1: CLRP020 Mask        */
-#define GPIO_PORT_CLR1_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR1: CLRP021 Position    */
-#define GPIO_PORT_CLR1_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP021_Pos)                    /*!< GPIO_PORT CLR1: CLRP021 Mask        */
-#define GPIO_PORT_CLR1_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR1: CLRP022 Position    */
-#define GPIO_PORT_CLR1_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP022_Pos)                    /*!< GPIO_PORT CLR1: CLRP022 Mask        */
-#define GPIO_PORT_CLR1_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR1: CLRP023 Position    */
-#define GPIO_PORT_CLR1_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP023_Pos)                    /*!< GPIO_PORT CLR1: CLRP023 Mask        */
-#define GPIO_PORT_CLR1_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR1: CLRP024 Position    */
-#define GPIO_PORT_CLR1_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP024_Pos)                    /*!< GPIO_PORT CLR1: CLRP024 Mask        */
-#define GPIO_PORT_CLR1_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR1: CLRP025 Position    */
-#define GPIO_PORT_CLR1_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP025_Pos)                    /*!< GPIO_PORT CLR1: CLRP025 Mask        */
-#define GPIO_PORT_CLR1_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR1: CLRP026 Position    */
-#define GPIO_PORT_CLR1_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP026_Pos)                    /*!< GPIO_PORT CLR1: CLRP026 Mask        */
-#define GPIO_PORT_CLR1_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR1: CLRP027 Position    */
-#define GPIO_PORT_CLR1_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP027_Pos)                    /*!< GPIO_PORT CLR1: CLRP027 Mask        */
-#define GPIO_PORT_CLR1_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR1: CLRP028 Position    */
-#define GPIO_PORT_CLR1_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP028_Pos)                    /*!< GPIO_PORT CLR1: CLRP028 Mask        */
-#define GPIO_PORT_CLR1_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR1: CLRP029 Position    */
-#define GPIO_PORT_CLR1_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP029_Pos)                    /*!< GPIO_PORT CLR1: CLRP029 Mask        */
-#define GPIO_PORT_CLR1_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR1: CLRP030 Position    */
-#define GPIO_PORT_CLR1_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP030_Pos)                    /*!< GPIO_PORT CLR1: CLRP030 Mask        */
-#define GPIO_PORT_CLR1_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR1: CLRP031 Position    */
-#define GPIO_PORT_CLR1_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP031_Pos)                    /*!< GPIO_PORT CLR1: CLRP031 Mask        */
-
-// -------------------------------------  GPIO_PORT_CLR2  -----------------------------------------
-#define GPIO_PORT_CLR2_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR2: CLRP00 Position     */
-#define GPIO_PORT_CLR2_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP00_Pos)                     /*!< GPIO_PORT CLR2: CLRP00 Mask         */
-#define GPIO_PORT_CLR2_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR2: CLRP01 Position     */
-#define GPIO_PORT_CLR2_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP01_Pos)                     /*!< GPIO_PORT CLR2: CLRP01 Mask         */
-#define GPIO_PORT_CLR2_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR2: CLRP02 Position     */
-#define GPIO_PORT_CLR2_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP02_Pos)                     /*!< GPIO_PORT CLR2: CLRP02 Mask         */
-#define GPIO_PORT_CLR2_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR2: CLRP03 Position     */
-#define GPIO_PORT_CLR2_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP03_Pos)                     /*!< GPIO_PORT CLR2: CLRP03 Mask         */
-#define GPIO_PORT_CLR2_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR2: CLRP04 Position     */
-#define GPIO_PORT_CLR2_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP04_Pos)                     /*!< GPIO_PORT CLR2: CLRP04 Mask         */
-#define GPIO_PORT_CLR2_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR2: CLRP05 Position     */
-#define GPIO_PORT_CLR2_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP05_Pos)                     /*!< GPIO_PORT CLR2: CLRP05 Mask         */
-#define GPIO_PORT_CLR2_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR2: CLRP06 Position     */
-#define GPIO_PORT_CLR2_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP06_Pos)                     /*!< GPIO_PORT CLR2: CLRP06 Mask         */
-#define GPIO_PORT_CLR2_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR2: CLRP07 Position     */
-#define GPIO_PORT_CLR2_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP07_Pos)                     /*!< GPIO_PORT CLR2: CLRP07 Mask         */
-#define GPIO_PORT_CLR2_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR2: CLRP08 Position     */
-#define GPIO_PORT_CLR2_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP08_Pos)                     /*!< GPIO_PORT CLR2: CLRP08 Mask         */
-#define GPIO_PORT_CLR2_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR2: CLRP09 Position     */
-#define GPIO_PORT_CLR2_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP09_Pos)                     /*!< GPIO_PORT CLR2: CLRP09 Mask         */
-#define GPIO_PORT_CLR2_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR2: CLRP010 Position    */
-#define GPIO_PORT_CLR2_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP010_Pos)                    /*!< GPIO_PORT CLR2: CLRP010 Mask        */
-#define GPIO_PORT_CLR2_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR2: CLRP011 Position    */
-#define GPIO_PORT_CLR2_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP011_Pos)                    /*!< GPIO_PORT CLR2: CLRP011 Mask        */
-#define GPIO_PORT_CLR2_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR2: CLRP012 Position    */
-#define GPIO_PORT_CLR2_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP012_Pos)                    /*!< GPIO_PORT CLR2: CLRP012 Mask        */
-#define GPIO_PORT_CLR2_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR2: CLRP013 Position    */
-#define GPIO_PORT_CLR2_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP013_Pos)                    /*!< GPIO_PORT CLR2: CLRP013 Mask        */
-#define GPIO_PORT_CLR2_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR2: CLRP014 Position    */
-#define GPIO_PORT_CLR2_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP014_Pos)                    /*!< GPIO_PORT CLR2: CLRP014 Mask        */
-#define GPIO_PORT_CLR2_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR2: CLRP015 Position    */
-#define GPIO_PORT_CLR2_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP015_Pos)                    /*!< GPIO_PORT CLR2: CLRP015 Mask        */
-#define GPIO_PORT_CLR2_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR2: CLRP016 Position    */
-#define GPIO_PORT_CLR2_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP016_Pos)                    /*!< GPIO_PORT CLR2: CLRP016 Mask        */
-#define GPIO_PORT_CLR2_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR2: CLRP017 Position    */
-#define GPIO_PORT_CLR2_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP017_Pos)                    /*!< GPIO_PORT CLR2: CLRP017 Mask        */
-#define GPIO_PORT_CLR2_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR2: CLRP018 Position    */
-#define GPIO_PORT_CLR2_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP018_Pos)                    /*!< GPIO_PORT CLR2: CLRP018 Mask        */
-#define GPIO_PORT_CLR2_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR2: CLRP019 Position    */
-#define GPIO_PORT_CLR2_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP019_Pos)                    /*!< GPIO_PORT CLR2: CLRP019 Mask        */
-#define GPIO_PORT_CLR2_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR2: CLRP020 Position    */
-#define GPIO_PORT_CLR2_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP020_Pos)                    /*!< GPIO_PORT CLR2: CLRP020 Mask        */
-#define GPIO_PORT_CLR2_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR2: CLRP021 Position    */
-#define GPIO_PORT_CLR2_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP021_Pos)                    /*!< GPIO_PORT CLR2: CLRP021 Mask        */
-#define GPIO_PORT_CLR2_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR2: CLRP022 Position    */
-#define GPIO_PORT_CLR2_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP022_Pos)                    /*!< GPIO_PORT CLR2: CLRP022 Mask        */
-#define GPIO_PORT_CLR2_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR2: CLRP023 Position    */
-#define GPIO_PORT_CLR2_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP023_Pos)                    /*!< GPIO_PORT CLR2: CLRP023 Mask        */
-#define GPIO_PORT_CLR2_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR2: CLRP024 Position    */
-#define GPIO_PORT_CLR2_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP024_Pos)                    /*!< GPIO_PORT CLR2: CLRP024 Mask        */
-#define GPIO_PORT_CLR2_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR2: CLRP025 Position    */
-#define GPIO_PORT_CLR2_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP025_Pos)                    /*!< GPIO_PORT CLR2: CLRP025 Mask        */
-#define GPIO_PORT_CLR2_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR2: CLRP026 Position    */
-#define GPIO_PORT_CLR2_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP026_Pos)                    /*!< GPIO_PORT CLR2: CLRP026 Mask        */
-#define GPIO_PORT_CLR2_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR2: CLRP027 Position    */
-#define GPIO_PORT_CLR2_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP027_Pos)                    /*!< GPIO_PORT CLR2: CLRP027 Mask        */
-#define GPIO_PORT_CLR2_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR2: CLRP028 Position    */
-#define GPIO_PORT_CLR2_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP028_Pos)                    /*!< GPIO_PORT CLR2: CLRP028 Mask        */
-#define GPIO_PORT_CLR2_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR2: CLRP029 Position    */
-#define GPIO_PORT_CLR2_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP029_Pos)                    /*!< GPIO_PORT CLR2: CLRP029 Mask        */
-#define GPIO_PORT_CLR2_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR2: CLRP030 Position    */
-#define GPIO_PORT_CLR2_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP030_Pos)                    /*!< GPIO_PORT CLR2: CLRP030 Mask        */
-#define GPIO_PORT_CLR2_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR2: CLRP031 Position    */
-#define GPIO_PORT_CLR2_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP031_Pos)                    /*!< GPIO_PORT CLR2: CLRP031 Mask        */
-
-// -------------------------------------  GPIO_PORT_CLR3  -----------------------------------------
-#define GPIO_PORT_CLR3_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR3: CLRP00 Position     */
-#define GPIO_PORT_CLR3_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP00_Pos)                     /*!< GPIO_PORT CLR3: CLRP00 Mask         */
-#define GPIO_PORT_CLR3_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR3: CLRP01 Position     */
-#define GPIO_PORT_CLR3_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP01_Pos)                     /*!< GPIO_PORT CLR3: CLRP01 Mask         */
-#define GPIO_PORT_CLR3_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR3: CLRP02 Position     */
-#define GPIO_PORT_CLR3_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP02_Pos)                     /*!< GPIO_PORT CLR3: CLRP02 Mask         */
-#define GPIO_PORT_CLR3_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR3: CLRP03 Position     */
-#define GPIO_PORT_CLR3_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP03_Pos)                     /*!< GPIO_PORT CLR3: CLRP03 Mask         */
-#define GPIO_PORT_CLR3_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR3: CLRP04 Position     */
-#define GPIO_PORT_CLR3_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP04_Pos)                     /*!< GPIO_PORT CLR3: CLRP04 Mask         */
-#define GPIO_PORT_CLR3_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR3: CLRP05 Position     */
-#define GPIO_PORT_CLR3_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP05_Pos)                     /*!< GPIO_PORT CLR3: CLRP05 Mask         */
-#define GPIO_PORT_CLR3_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR3: CLRP06 Position     */
-#define GPIO_PORT_CLR3_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP06_Pos)                     /*!< GPIO_PORT CLR3: CLRP06 Mask         */
-#define GPIO_PORT_CLR3_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR3: CLRP07 Position     */
-#define GPIO_PORT_CLR3_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP07_Pos)                     /*!< GPIO_PORT CLR3: CLRP07 Mask         */
-#define GPIO_PORT_CLR3_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR3: CLRP08 Position     */
-#define GPIO_PORT_CLR3_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP08_Pos)                     /*!< GPIO_PORT CLR3: CLRP08 Mask         */
-#define GPIO_PORT_CLR3_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR3: CLRP09 Position     */
-#define GPIO_PORT_CLR3_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP09_Pos)                     /*!< GPIO_PORT CLR3: CLRP09 Mask         */
-#define GPIO_PORT_CLR3_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR3: CLRP010 Position    */
-#define GPIO_PORT_CLR3_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP010_Pos)                    /*!< GPIO_PORT CLR3: CLRP010 Mask        */
-#define GPIO_PORT_CLR3_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR3: CLRP011 Position    */
-#define GPIO_PORT_CLR3_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP011_Pos)                    /*!< GPIO_PORT CLR3: CLRP011 Mask        */
-#define GPIO_PORT_CLR3_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR3: CLRP012 Position    */
-#define GPIO_PORT_CLR3_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP012_Pos)                    /*!< GPIO_PORT CLR3: CLRP012 Mask        */
-#define GPIO_PORT_CLR3_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR3: CLRP013 Position    */
-#define GPIO_PORT_CLR3_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP013_Pos)                    /*!< GPIO_PORT CLR3: CLRP013 Mask        */
-#define GPIO_PORT_CLR3_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR3: CLRP014 Position    */
-#define GPIO_PORT_CLR3_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP014_Pos)                    /*!< GPIO_PORT CLR3: CLRP014 Mask        */
-#define GPIO_PORT_CLR3_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR3: CLRP015 Position    */
-#define GPIO_PORT_CLR3_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP015_Pos)                    /*!< GPIO_PORT CLR3: CLRP015 Mask        */
-#define GPIO_PORT_CLR3_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR3: CLRP016 Position    */
-#define GPIO_PORT_CLR3_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP016_Pos)                    /*!< GPIO_PORT CLR3: CLRP016 Mask        */
-#define GPIO_PORT_CLR3_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR3: CLRP017 Position    */
-#define GPIO_PORT_CLR3_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP017_Pos)                    /*!< GPIO_PORT CLR3: CLRP017 Mask        */
-#define GPIO_PORT_CLR3_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR3: CLRP018 Position    */
-#define GPIO_PORT_CLR3_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP018_Pos)                    /*!< GPIO_PORT CLR3: CLRP018 Mask        */
-#define GPIO_PORT_CLR3_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR3: CLRP019 Position    */
-#define GPIO_PORT_CLR3_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP019_Pos)                    /*!< GPIO_PORT CLR3: CLRP019 Mask        */
-#define GPIO_PORT_CLR3_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR3: CLRP020 Position    */
-#define GPIO_PORT_CLR3_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP020_Pos)                    /*!< GPIO_PORT CLR3: CLRP020 Mask        */
-#define GPIO_PORT_CLR3_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR3: CLRP021 Position    */
-#define GPIO_PORT_CLR3_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP021_Pos)                    /*!< GPIO_PORT CLR3: CLRP021 Mask        */
-#define GPIO_PORT_CLR3_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR3: CLRP022 Position    */
-#define GPIO_PORT_CLR3_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP022_Pos)                    /*!< GPIO_PORT CLR3: CLRP022 Mask        */
-#define GPIO_PORT_CLR3_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR3: CLRP023 Position    */
-#define GPIO_PORT_CLR3_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP023_Pos)                    /*!< GPIO_PORT CLR3: CLRP023 Mask        */
-#define GPIO_PORT_CLR3_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR3: CLRP024 Position    */
-#define GPIO_PORT_CLR3_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP024_Pos)                    /*!< GPIO_PORT CLR3: CLRP024 Mask        */
-#define GPIO_PORT_CLR3_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR3: CLRP025 Position    */
-#define GPIO_PORT_CLR3_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP025_Pos)                    /*!< GPIO_PORT CLR3: CLRP025 Mask        */
-#define GPIO_PORT_CLR3_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR3: CLRP026 Position    */
-#define GPIO_PORT_CLR3_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP026_Pos)                    /*!< GPIO_PORT CLR3: CLRP026 Mask        */
-#define GPIO_PORT_CLR3_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR3: CLRP027 Position    */
-#define GPIO_PORT_CLR3_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP027_Pos)                    /*!< GPIO_PORT CLR3: CLRP027 Mask        */
-#define GPIO_PORT_CLR3_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR3: CLRP028 Position    */
-#define GPIO_PORT_CLR3_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP028_Pos)                    /*!< GPIO_PORT CLR3: CLRP028 Mask        */
-#define GPIO_PORT_CLR3_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR3: CLRP029 Position    */
-#define GPIO_PORT_CLR3_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP029_Pos)                    /*!< GPIO_PORT CLR3: CLRP029 Mask        */
-#define GPIO_PORT_CLR3_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR3: CLRP030 Position    */
-#define GPIO_PORT_CLR3_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP030_Pos)                    /*!< GPIO_PORT CLR3: CLRP030 Mask        */
-#define GPIO_PORT_CLR3_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR3: CLRP031 Position    */
-#define GPIO_PORT_CLR3_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP031_Pos)                    /*!< GPIO_PORT CLR3: CLRP031 Mask        */
-
-// -------------------------------------  GPIO_PORT_CLR4  -----------------------------------------
-#define GPIO_PORT_CLR4_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR4: CLRP00 Position     */
-#define GPIO_PORT_CLR4_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP00_Pos)                     /*!< GPIO_PORT CLR4: CLRP00 Mask         */
-#define GPIO_PORT_CLR4_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR4: CLRP01 Position     */
-#define GPIO_PORT_CLR4_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP01_Pos)                     /*!< GPIO_PORT CLR4: CLRP01 Mask         */
-#define GPIO_PORT_CLR4_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR4: CLRP02 Position     */
-#define GPIO_PORT_CLR4_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP02_Pos)                     /*!< GPIO_PORT CLR4: CLRP02 Mask         */
-#define GPIO_PORT_CLR4_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR4: CLRP03 Position     */
-#define GPIO_PORT_CLR4_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP03_Pos)                     /*!< GPIO_PORT CLR4: CLRP03 Mask         */
-#define GPIO_PORT_CLR4_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR4: CLRP04 Position     */
-#define GPIO_PORT_CLR4_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP04_Pos)                     /*!< GPIO_PORT CLR4: CLRP04 Mask         */
-#define GPIO_PORT_CLR4_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR4: CLRP05 Position     */
-#define GPIO_PORT_CLR4_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP05_Pos)                     /*!< GPIO_PORT CLR4: CLRP05 Mask         */
-#define GPIO_PORT_CLR4_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR4: CLRP06 Position     */
-#define GPIO_PORT_CLR4_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP06_Pos)                     /*!< GPIO_PORT CLR4: CLRP06 Mask         */
-#define GPIO_PORT_CLR4_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR4: CLRP07 Position     */
-#define GPIO_PORT_CLR4_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP07_Pos)                     /*!< GPIO_PORT CLR4: CLRP07 Mask         */
-#define GPIO_PORT_CLR4_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR4: CLRP08 Position     */
-#define GPIO_PORT_CLR4_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP08_Pos)                     /*!< GPIO_PORT CLR4: CLRP08 Mask         */
-#define GPIO_PORT_CLR4_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR4: CLRP09 Position     */
-#define GPIO_PORT_CLR4_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP09_Pos)                     /*!< GPIO_PORT CLR4: CLRP09 Mask         */
-#define GPIO_PORT_CLR4_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR4: CLRP010 Position    */
-#define GPIO_PORT_CLR4_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP010_Pos)                    /*!< GPIO_PORT CLR4: CLRP010 Mask        */
-#define GPIO_PORT_CLR4_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR4: CLRP011 Position    */
-#define GPIO_PORT_CLR4_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP011_Pos)                    /*!< GPIO_PORT CLR4: CLRP011 Mask        */
-#define GPIO_PORT_CLR4_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR4: CLRP012 Position    */
-#define GPIO_PORT_CLR4_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP012_Pos)                    /*!< GPIO_PORT CLR4: CLRP012 Mask        */
-#define GPIO_PORT_CLR4_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR4: CLRP013 Position    */
-#define GPIO_PORT_CLR4_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP013_Pos)                    /*!< GPIO_PORT CLR4: CLRP013 Mask        */
-#define GPIO_PORT_CLR4_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR4: CLRP014 Position    */
-#define GPIO_PORT_CLR4_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP014_Pos)                    /*!< GPIO_PORT CLR4: CLRP014 Mask        */
-#define GPIO_PORT_CLR4_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR4: CLRP015 Position    */
-#define GPIO_PORT_CLR4_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP015_Pos)                    /*!< GPIO_PORT CLR4: CLRP015 Mask        */
-#define GPIO_PORT_CLR4_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR4: CLRP016 Position    */
-#define GPIO_PORT_CLR4_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP016_Pos)                    /*!< GPIO_PORT CLR4: CLRP016 Mask        */
-#define GPIO_PORT_CLR4_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR4: CLRP017 Position    */
-#define GPIO_PORT_CLR4_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP017_Pos)                    /*!< GPIO_PORT CLR4: CLRP017 Mask        */
-#define GPIO_PORT_CLR4_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR4: CLRP018 Position    */
-#define GPIO_PORT_CLR4_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP018_Pos)                    /*!< GPIO_PORT CLR4: CLRP018 Mask        */
-#define GPIO_PORT_CLR4_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR4: CLRP019 Position    */
-#define GPIO_PORT_CLR4_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP019_Pos)                    /*!< GPIO_PORT CLR4: CLRP019 Mask        */
-#define GPIO_PORT_CLR4_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR4: CLRP020 Position    */
-#define GPIO_PORT_CLR4_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP020_Pos)                    /*!< GPIO_PORT CLR4: CLRP020 Mask        */
-#define GPIO_PORT_CLR4_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR4: CLRP021 Position    */
-#define GPIO_PORT_CLR4_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP021_Pos)                    /*!< GPIO_PORT CLR4: CLRP021 Mask        */
-#define GPIO_PORT_CLR4_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR4: CLRP022 Position    */
-#define GPIO_PORT_CLR4_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP022_Pos)                    /*!< GPIO_PORT CLR4: CLRP022 Mask        */
-#define GPIO_PORT_CLR4_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR4: CLRP023 Position    */
-#define GPIO_PORT_CLR4_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP023_Pos)                    /*!< GPIO_PORT CLR4: CLRP023 Mask        */
-#define GPIO_PORT_CLR4_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR4: CLRP024 Position    */
-#define GPIO_PORT_CLR4_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP024_Pos)                    /*!< GPIO_PORT CLR4: CLRP024 Mask        */
-#define GPIO_PORT_CLR4_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR4: CLRP025 Position    */
-#define GPIO_PORT_CLR4_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP025_Pos)                    /*!< GPIO_PORT CLR4: CLRP025 Mask        */
-#define GPIO_PORT_CLR4_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR4: CLRP026 Position    */
-#define GPIO_PORT_CLR4_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP026_Pos)                    /*!< GPIO_PORT CLR4: CLRP026 Mask        */
-#define GPIO_PORT_CLR4_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR4: CLRP027 Position    */
-#define GPIO_PORT_CLR4_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP027_Pos)                    /*!< GPIO_PORT CLR4: CLRP027 Mask        */
-#define GPIO_PORT_CLR4_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR4: CLRP028 Position    */
-#define GPIO_PORT_CLR4_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP028_Pos)                    /*!< GPIO_PORT CLR4: CLRP028 Mask        */
-#define GPIO_PORT_CLR4_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR4: CLRP029 Position    */
-#define GPIO_PORT_CLR4_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP029_Pos)                    /*!< GPIO_PORT CLR4: CLRP029 Mask        */
-#define GPIO_PORT_CLR4_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR4: CLRP030 Position    */
-#define GPIO_PORT_CLR4_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP030_Pos)                    /*!< GPIO_PORT CLR4: CLRP030 Mask        */
-#define GPIO_PORT_CLR4_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR4: CLRP031 Position    */
-#define GPIO_PORT_CLR4_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP031_Pos)                    /*!< GPIO_PORT CLR4: CLRP031 Mask        */
-
-// -------------------------------------  GPIO_PORT_CLR5  -----------------------------------------
-#define GPIO_PORT_CLR5_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR5: CLRP00 Position     */
-#define GPIO_PORT_CLR5_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP00_Pos)                     /*!< GPIO_PORT CLR5: CLRP00 Mask         */
-#define GPIO_PORT_CLR5_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR5: CLRP01 Position     */
-#define GPIO_PORT_CLR5_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP01_Pos)                     /*!< GPIO_PORT CLR5: CLRP01 Mask         */
-#define GPIO_PORT_CLR5_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR5: CLRP02 Position     */
-#define GPIO_PORT_CLR5_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP02_Pos)                     /*!< GPIO_PORT CLR5: CLRP02 Mask         */
-#define GPIO_PORT_CLR5_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR5: CLRP03 Position     */
-#define GPIO_PORT_CLR5_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP03_Pos)                     /*!< GPIO_PORT CLR5: CLRP03 Mask         */
-#define GPIO_PORT_CLR5_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR5: CLRP04 Position     */
-#define GPIO_PORT_CLR5_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP04_Pos)                     /*!< GPIO_PORT CLR5: CLRP04 Mask         */
-#define GPIO_PORT_CLR5_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR5: CLRP05 Position     */
-#define GPIO_PORT_CLR5_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP05_Pos)                     /*!< GPIO_PORT CLR5: CLRP05 Mask         */
-#define GPIO_PORT_CLR5_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR5: CLRP06 Position     */
-#define GPIO_PORT_CLR5_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP06_Pos)                     /*!< GPIO_PORT CLR5: CLRP06 Mask         */
-#define GPIO_PORT_CLR5_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR5: CLRP07 Position     */
-#define GPIO_PORT_CLR5_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP07_Pos)                     /*!< GPIO_PORT CLR5: CLRP07 Mask         */
-#define GPIO_PORT_CLR5_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR5: CLRP08 Position     */
-#define GPIO_PORT_CLR5_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP08_Pos)                     /*!< GPIO_PORT CLR5: CLRP08 Mask         */
-#define GPIO_PORT_CLR5_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR5: CLRP09 Position     */
-#define GPIO_PORT_CLR5_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP09_Pos)                     /*!< GPIO_PORT CLR5: CLRP09 Mask         */
-#define GPIO_PORT_CLR5_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR5: CLRP010 Position    */
-#define GPIO_PORT_CLR5_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP010_Pos)                    /*!< GPIO_PORT CLR5: CLRP010 Mask        */
-#define GPIO_PORT_CLR5_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR5: CLRP011 Position    */
-#define GPIO_PORT_CLR5_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP011_Pos)                    /*!< GPIO_PORT CLR5: CLRP011 Mask        */
-#define GPIO_PORT_CLR5_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR5: CLRP012 Position    */
-#define GPIO_PORT_CLR5_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP012_Pos)                    /*!< GPIO_PORT CLR5: CLRP012 Mask        */
-#define GPIO_PORT_CLR5_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR5: CLRP013 Position    */
-#define GPIO_PORT_CLR5_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP013_Pos)                    /*!< GPIO_PORT CLR5: CLRP013 Mask        */
-#define GPIO_PORT_CLR5_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR5: CLRP014 Position    */
-#define GPIO_PORT_CLR5_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP014_Pos)                    /*!< GPIO_PORT CLR5: CLRP014 Mask        */
-#define GPIO_PORT_CLR5_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR5: CLRP015 Position    */
-#define GPIO_PORT_CLR5_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP015_Pos)                    /*!< GPIO_PORT CLR5: CLRP015 Mask        */
-#define GPIO_PORT_CLR5_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR5: CLRP016 Position    */
-#define GPIO_PORT_CLR5_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP016_Pos)                    /*!< GPIO_PORT CLR5: CLRP016 Mask        */
-#define GPIO_PORT_CLR5_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR5: CLRP017 Position    */
-#define GPIO_PORT_CLR5_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP017_Pos)                    /*!< GPIO_PORT CLR5: CLRP017 Mask        */
-#define GPIO_PORT_CLR5_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR5: CLRP018 Position    */
-#define GPIO_PORT_CLR5_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP018_Pos)                    /*!< GPIO_PORT CLR5: CLRP018 Mask        */
-#define GPIO_PORT_CLR5_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR5: CLRP019 Position    */
-#define GPIO_PORT_CLR5_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP019_Pos)                    /*!< GPIO_PORT CLR5: CLRP019 Mask        */
-#define GPIO_PORT_CLR5_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR5: CLRP020 Position    */
-#define GPIO_PORT_CLR5_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP020_Pos)                    /*!< GPIO_PORT CLR5: CLRP020 Mask        */
-#define GPIO_PORT_CLR5_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR5: CLRP021 Position    */
-#define GPIO_PORT_CLR5_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP021_Pos)                    /*!< GPIO_PORT CLR5: CLRP021 Mask        */
-#define GPIO_PORT_CLR5_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR5: CLRP022 Position    */
-#define GPIO_PORT_CLR5_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP022_Pos)                    /*!< GPIO_PORT CLR5: CLRP022 Mask        */
-#define GPIO_PORT_CLR5_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR5: CLRP023 Position    */
-#define GPIO_PORT_CLR5_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP023_Pos)                    /*!< GPIO_PORT CLR5: CLRP023 Mask        */
-#define GPIO_PORT_CLR5_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR5: CLRP024 Position    */
-#define GPIO_PORT_CLR5_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP024_Pos)                    /*!< GPIO_PORT CLR5: CLRP024 Mask        */
-#define GPIO_PORT_CLR5_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR5: CLRP025 Position    */
-#define GPIO_PORT_CLR5_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP025_Pos)                    /*!< GPIO_PORT CLR5: CLRP025 Mask        */
-#define GPIO_PORT_CLR5_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR5: CLRP026 Position    */
-#define GPIO_PORT_CLR5_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP026_Pos)                    /*!< GPIO_PORT CLR5: CLRP026 Mask        */
-#define GPIO_PORT_CLR5_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR5: CLRP027 Position    */
-#define GPIO_PORT_CLR5_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP027_Pos)                    /*!< GPIO_PORT CLR5: CLRP027 Mask        */
-#define GPIO_PORT_CLR5_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR5: CLRP028 Position    */
-#define GPIO_PORT_CLR5_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP028_Pos)                    /*!< GPIO_PORT CLR5: CLRP028 Mask        */
-#define GPIO_PORT_CLR5_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR5: CLRP029 Position    */
-#define GPIO_PORT_CLR5_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP029_Pos)                    /*!< GPIO_PORT CLR5: CLRP029 Mask        */
-#define GPIO_PORT_CLR5_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR5: CLRP030 Position    */
-#define GPIO_PORT_CLR5_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP030_Pos)                    /*!< GPIO_PORT CLR5: CLRP030 Mask        */
-#define GPIO_PORT_CLR5_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR5: CLRP031 Position    */
-#define GPIO_PORT_CLR5_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP031_Pos)                    /*!< GPIO_PORT CLR5: CLRP031 Mask        */
-
-// -------------------------------------  GPIO_PORT_CLR6  -----------------------------------------
-#define GPIO_PORT_CLR6_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR6: CLRP00 Position     */
-#define GPIO_PORT_CLR6_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP00_Pos)                     /*!< GPIO_PORT CLR6: CLRP00 Mask         */
-#define GPIO_PORT_CLR6_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR6: CLRP01 Position     */
-#define GPIO_PORT_CLR6_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP01_Pos)                     /*!< GPIO_PORT CLR6: CLRP01 Mask         */
-#define GPIO_PORT_CLR6_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR6: CLRP02 Position     */
-#define GPIO_PORT_CLR6_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP02_Pos)                     /*!< GPIO_PORT CLR6: CLRP02 Mask         */
-#define GPIO_PORT_CLR6_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR6: CLRP03 Position     */
-#define GPIO_PORT_CLR6_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP03_Pos)                     /*!< GPIO_PORT CLR6: CLRP03 Mask         */
-#define GPIO_PORT_CLR6_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR6: CLRP04 Position     */
-#define GPIO_PORT_CLR6_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP04_Pos)                     /*!< GPIO_PORT CLR6: CLRP04 Mask         */
-#define GPIO_PORT_CLR6_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR6: CLRP05 Position     */
-#define GPIO_PORT_CLR6_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP05_Pos)                     /*!< GPIO_PORT CLR6: CLRP05 Mask         */
-#define GPIO_PORT_CLR6_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR6: CLRP06 Position     */
-#define GPIO_PORT_CLR6_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP06_Pos)                     /*!< GPIO_PORT CLR6: CLRP06 Mask         */
-#define GPIO_PORT_CLR6_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR6: CLRP07 Position     */
-#define GPIO_PORT_CLR6_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP07_Pos)                     /*!< GPIO_PORT CLR6: CLRP07 Mask         */
-#define GPIO_PORT_CLR6_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR6: CLRP08 Position     */
-#define GPIO_PORT_CLR6_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP08_Pos)                     /*!< GPIO_PORT CLR6: CLRP08 Mask         */
-#define GPIO_PORT_CLR6_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR6: CLRP09 Position     */
-#define GPIO_PORT_CLR6_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP09_Pos)                     /*!< GPIO_PORT CLR6: CLRP09 Mask         */
-#define GPIO_PORT_CLR6_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR6: CLRP010 Position    */
-#define GPIO_PORT_CLR6_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP010_Pos)                    /*!< GPIO_PORT CLR6: CLRP010 Mask        */
-#define GPIO_PORT_CLR6_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR6: CLRP011 Position    */
-#define GPIO_PORT_CLR6_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP011_Pos)                    /*!< GPIO_PORT CLR6: CLRP011 Mask        */
-#define GPIO_PORT_CLR6_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR6: CLRP012 Position    */
-#define GPIO_PORT_CLR6_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP012_Pos)                    /*!< GPIO_PORT CLR6: CLRP012 Mask        */
-#define GPIO_PORT_CLR6_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR6: CLRP013 Position    */
-#define GPIO_PORT_CLR6_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP013_Pos)                    /*!< GPIO_PORT CLR6: CLRP013 Mask        */
-#define GPIO_PORT_CLR6_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR6: CLRP014 Position    */
-#define GPIO_PORT_CLR6_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP014_Pos)                    /*!< GPIO_PORT CLR6: CLRP014 Mask        */
-#define GPIO_PORT_CLR6_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR6: CLRP015 Position    */
-#define GPIO_PORT_CLR6_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP015_Pos)                    /*!< GPIO_PORT CLR6: CLRP015 Mask        */
-#define GPIO_PORT_CLR6_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR6: CLRP016 Position    */
-#define GPIO_PORT_CLR6_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP016_Pos)                    /*!< GPIO_PORT CLR6: CLRP016 Mask        */
-#define GPIO_PORT_CLR6_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR6: CLRP017 Position    */
-#define GPIO_PORT_CLR6_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP017_Pos)                    /*!< GPIO_PORT CLR6: CLRP017 Mask        */
-#define GPIO_PORT_CLR6_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR6: CLRP018 Position    */
-#define GPIO_PORT_CLR6_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP018_Pos)                    /*!< GPIO_PORT CLR6: CLRP018 Mask        */
-#define GPIO_PORT_CLR6_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR6: CLRP019 Position    */
-#define GPIO_PORT_CLR6_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP019_Pos)                    /*!< GPIO_PORT CLR6: CLRP019 Mask        */
-#define GPIO_PORT_CLR6_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR6: CLRP020 Position    */
-#define GPIO_PORT_CLR6_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP020_Pos)                    /*!< GPIO_PORT CLR6: CLRP020 Mask        */
-#define GPIO_PORT_CLR6_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR6: CLRP021 Position    */
-#define GPIO_PORT_CLR6_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP021_Pos)                    /*!< GPIO_PORT CLR6: CLRP021 Mask        */
-#define GPIO_PORT_CLR6_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR6: CLRP022 Position    */
-#define GPIO_PORT_CLR6_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP022_Pos)                    /*!< GPIO_PORT CLR6: CLRP022 Mask        */
-#define GPIO_PORT_CLR6_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR6: CLRP023 Position    */
-#define GPIO_PORT_CLR6_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP023_Pos)                    /*!< GPIO_PORT CLR6: CLRP023 Mask        */
-#define GPIO_PORT_CLR6_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR6: CLRP024 Position    */
-#define GPIO_PORT_CLR6_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP024_Pos)                    /*!< GPIO_PORT CLR6: CLRP024 Mask        */
-#define GPIO_PORT_CLR6_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR6: CLRP025 Position    */
-#define GPIO_PORT_CLR6_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP025_Pos)                    /*!< GPIO_PORT CLR6: CLRP025 Mask        */
-#define GPIO_PORT_CLR6_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR6: CLRP026 Position    */
-#define GPIO_PORT_CLR6_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP026_Pos)                    /*!< GPIO_PORT CLR6: CLRP026 Mask        */
-#define GPIO_PORT_CLR6_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR6: CLRP027 Position    */
-#define GPIO_PORT_CLR6_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP027_Pos)                    /*!< GPIO_PORT CLR6: CLRP027 Mask        */
-#define GPIO_PORT_CLR6_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR6: CLRP028 Position    */
-#define GPIO_PORT_CLR6_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP028_Pos)                    /*!< GPIO_PORT CLR6: CLRP028 Mask        */
-#define GPIO_PORT_CLR6_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR6: CLRP029 Position    */
-#define GPIO_PORT_CLR6_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP029_Pos)                    /*!< GPIO_PORT CLR6: CLRP029 Mask        */
-#define GPIO_PORT_CLR6_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR6: CLRP030 Position    */
-#define GPIO_PORT_CLR6_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP030_Pos)                    /*!< GPIO_PORT CLR6: CLRP030 Mask        */
-#define GPIO_PORT_CLR6_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR6: CLRP031 Position    */
-#define GPIO_PORT_CLR6_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP031_Pos)                    /*!< GPIO_PORT CLR6: CLRP031 Mask        */
-
-// -------------------------------------  GPIO_PORT_CLR7  -----------------------------------------
-#define GPIO_PORT_CLR7_CLRP00_Pos                             0                                                         /*!< GPIO_PORT CLR7: CLRP00 Position     */
-#define GPIO_PORT_CLR7_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP00_Pos)                     /*!< GPIO_PORT CLR7: CLRP00 Mask         */
-#define GPIO_PORT_CLR7_CLRP01_Pos                             1                                                         /*!< GPIO_PORT CLR7: CLRP01 Position     */
-#define GPIO_PORT_CLR7_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP01_Pos)                     /*!< GPIO_PORT CLR7: CLRP01 Mask         */
-#define GPIO_PORT_CLR7_CLRP02_Pos                             2                                                         /*!< GPIO_PORT CLR7: CLRP02 Position     */
-#define GPIO_PORT_CLR7_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP02_Pos)                     /*!< GPIO_PORT CLR7: CLRP02 Mask         */
-#define GPIO_PORT_CLR7_CLRP03_Pos                             3                                                         /*!< GPIO_PORT CLR7: CLRP03 Position     */
-#define GPIO_PORT_CLR7_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP03_Pos)                     /*!< GPIO_PORT CLR7: CLRP03 Mask         */
-#define GPIO_PORT_CLR7_CLRP04_Pos                             4                                                         /*!< GPIO_PORT CLR7: CLRP04 Position     */
-#define GPIO_PORT_CLR7_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP04_Pos)                     /*!< GPIO_PORT CLR7: CLRP04 Mask         */
-#define GPIO_PORT_CLR7_CLRP05_Pos                             5                                                         /*!< GPIO_PORT CLR7: CLRP05 Position     */
-#define GPIO_PORT_CLR7_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP05_Pos)                     /*!< GPIO_PORT CLR7: CLRP05 Mask         */
-#define GPIO_PORT_CLR7_CLRP06_Pos                             6                                                         /*!< GPIO_PORT CLR7: CLRP06 Position     */
-#define GPIO_PORT_CLR7_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP06_Pos)                     /*!< GPIO_PORT CLR7: CLRP06 Mask         */
-#define GPIO_PORT_CLR7_CLRP07_Pos                             7                                                         /*!< GPIO_PORT CLR7: CLRP07 Position     */
-#define GPIO_PORT_CLR7_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP07_Pos)                     /*!< GPIO_PORT CLR7: CLRP07 Mask         */
-#define GPIO_PORT_CLR7_CLRP08_Pos                             8                                                         /*!< GPIO_PORT CLR7: CLRP08 Position     */
-#define GPIO_PORT_CLR7_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP08_Pos)                     /*!< GPIO_PORT CLR7: CLRP08 Mask         */
-#define GPIO_PORT_CLR7_CLRP09_Pos                             9                                                         /*!< GPIO_PORT CLR7: CLRP09 Position     */
-#define GPIO_PORT_CLR7_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP09_Pos)                     /*!< GPIO_PORT CLR7: CLRP09 Mask         */
-#define GPIO_PORT_CLR7_CLRP010_Pos                            10                                                        /*!< GPIO_PORT CLR7: CLRP010 Position    */
-#define GPIO_PORT_CLR7_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP010_Pos)                    /*!< GPIO_PORT CLR7: CLRP010 Mask        */
-#define GPIO_PORT_CLR7_CLRP011_Pos                            11                                                        /*!< GPIO_PORT CLR7: CLRP011 Position    */
-#define GPIO_PORT_CLR7_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP011_Pos)                    /*!< GPIO_PORT CLR7: CLRP011 Mask        */
-#define GPIO_PORT_CLR7_CLRP012_Pos                            12                                                        /*!< GPIO_PORT CLR7: CLRP012 Position    */
-#define GPIO_PORT_CLR7_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP012_Pos)                    /*!< GPIO_PORT CLR7: CLRP012 Mask        */
-#define GPIO_PORT_CLR7_CLRP013_Pos                            13                                                        /*!< GPIO_PORT CLR7: CLRP013 Position    */
-#define GPIO_PORT_CLR7_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP013_Pos)                    /*!< GPIO_PORT CLR7: CLRP013 Mask        */
-#define GPIO_PORT_CLR7_CLRP014_Pos                            14                                                        /*!< GPIO_PORT CLR7: CLRP014 Position    */
-#define GPIO_PORT_CLR7_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP014_Pos)                    /*!< GPIO_PORT CLR7: CLRP014 Mask        */
-#define GPIO_PORT_CLR7_CLRP015_Pos                            15                                                        /*!< GPIO_PORT CLR7: CLRP015 Position    */
-#define GPIO_PORT_CLR7_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP015_Pos)                    /*!< GPIO_PORT CLR7: CLRP015 Mask        */
-#define GPIO_PORT_CLR7_CLRP016_Pos                            16                                                        /*!< GPIO_PORT CLR7: CLRP016 Position    */
-#define GPIO_PORT_CLR7_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP016_Pos)                    /*!< GPIO_PORT CLR7: CLRP016 Mask        */
-#define GPIO_PORT_CLR7_CLRP017_Pos                            17                                                        /*!< GPIO_PORT CLR7: CLRP017 Position    */
-#define GPIO_PORT_CLR7_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP017_Pos)                    /*!< GPIO_PORT CLR7: CLRP017 Mask        */
-#define GPIO_PORT_CLR7_CLRP018_Pos                            18                                                        /*!< GPIO_PORT CLR7: CLRP018 Position    */
-#define GPIO_PORT_CLR7_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP018_Pos)                    /*!< GPIO_PORT CLR7: CLRP018 Mask        */
-#define GPIO_PORT_CLR7_CLRP019_Pos                            19                                                        /*!< GPIO_PORT CLR7: CLRP019 Position    */
-#define GPIO_PORT_CLR7_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP019_Pos)                    /*!< GPIO_PORT CLR7: CLRP019 Mask        */
-#define GPIO_PORT_CLR7_CLRP020_Pos                            20                                                        /*!< GPIO_PORT CLR7: CLRP020 Position    */
-#define GPIO_PORT_CLR7_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP020_Pos)                    /*!< GPIO_PORT CLR7: CLRP020 Mask        */
-#define GPIO_PORT_CLR7_CLRP021_Pos                            21                                                        /*!< GPIO_PORT CLR7: CLRP021 Position    */
-#define GPIO_PORT_CLR7_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP021_Pos)                    /*!< GPIO_PORT CLR7: CLRP021 Mask        */
-#define GPIO_PORT_CLR7_CLRP022_Pos                            22                                                        /*!< GPIO_PORT CLR7: CLRP022 Position    */
-#define GPIO_PORT_CLR7_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP022_Pos)                    /*!< GPIO_PORT CLR7: CLRP022 Mask        */
-#define GPIO_PORT_CLR7_CLRP023_Pos                            23                                                        /*!< GPIO_PORT CLR7: CLRP023 Position    */
-#define GPIO_PORT_CLR7_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP023_Pos)                    /*!< GPIO_PORT CLR7: CLRP023 Mask        */
-#define GPIO_PORT_CLR7_CLRP024_Pos                            24                                                        /*!< GPIO_PORT CLR7: CLRP024 Position    */
-#define GPIO_PORT_CLR7_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP024_Pos)                    /*!< GPIO_PORT CLR7: CLRP024 Mask        */
-#define GPIO_PORT_CLR7_CLRP025_Pos                            25                                                        /*!< GPIO_PORT CLR7: CLRP025 Position    */
-#define GPIO_PORT_CLR7_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP025_Pos)                    /*!< GPIO_PORT CLR7: CLRP025 Mask        */
-#define GPIO_PORT_CLR7_CLRP026_Pos                            26                                                        /*!< GPIO_PORT CLR7: CLRP026 Position    */
-#define GPIO_PORT_CLR7_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP026_Pos)                    /*!< GPIO_PORT CLR7: CLRP026 Mask        */
-#define GPIO_PORT_CLR7_CLRP027_Pos                            27                                                        /*!< GPIO_PORT CLR7: CLRP027 Position    */
-#define GPIO_PORT_CLR7_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP027_Pos)                    /*!< GPIO_PORT CLR7: CLRP027 Mask        */
-#define GPIO_PORT_CLR7_CLRP028_Pos                            28                                                        /*!< GPIO_PORT CLR7: CLRP028 Position    */
-#define GPIO_PORT_CLR7_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP028_Pos)                    /*!< GPIO_PORT CLR7: CLRP028 Mask        */
-#define GPIO_PORT_CLR7_CLRP029_Pos                            29                                                        /*!< GPIO_PORT CLR7: CLRP029 Position    */
-#define GPIO_PORT_CLR7_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP029_Pos)                    /*!< GPIO_PORT CLR7: CLRP029 Mask        */
-#define GPIO_PORT_CLR7_CLRP030_Pos                            30                                                        /*!< GPIO_PORT CLR7: CLRP030 Position    */
-#define GPIO_PORT_CLR7_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP030_Pos)                    /*!< GPIO_PORT CLR7: CLRP030 Mask        */
-#define GPIO_PORT_CLR7_CLRP031_Pos                            31                                                        /*!< GPIO_PORT CLR7: CLRP031 Position    */
-#define GPIO_PORT_CLR7_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP031_Pos)                    /*!< GPIO_PORT CLR7: CLRP031 Mask        */
-
-// -------------------------------------  GPIO_PORT_NOT0  -----------------------------------------
-#define GPIO_PORT_NOT0_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT0: NOTP0 Position      */
-#define GPIO_PORT_NOT0_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP0_Pos)                      /*!< GPIO_PORT NOT0: NOTP0 Mask          */
-#define GPIO_PORT_NOT0_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT0: NOTP1 Position      */
-#define GPIO_PORT_NOT0_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP1_Pos)                      /*!< GPIO_PORT NOT0: NOTP1 Mask          */
-#define GPIO_PORT_NOT0_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT0: NOTP2 Position      */
-#define GPIO_PORT_NOT0_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP2_Pos)                      /*!< GPIO_PORT NOT0: NOTP2 Mask          */
-#define GPIO_PORT_NOT0_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT0: NOTP3 Position      */
-#define GPIO_PORT_NOT0_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP3_Pos)                      /*!< GPIO_PORT NOT0: NOTP3 Mask          */
-#define GPIO_PORT_NOT0_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT0: NOTP4 Position      */
-#define GPIO_PORT_NOT0_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP4_Pos)                      /*!< GPIO_PORT NOT0: NOTP4 Mask          */
-#define GPIO_PORT_NOT0_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT0: NOTP5 Position      */
-#define GPIO_PORT_NOT0_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP5_Pos)                      /*!< GPIO_PORT NOT0: NOTP5 Mask          */
-#define GPIO_PORT_NOT0_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT0: NOTP6 Position      */
-#define GPIO_PORT_NOT0_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP6_Pos)                      /*!< GPIO_PORT NOT0: NOTP6 Mask          */
-#define GPIO_PORT_NOT0_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT0: NOTP7 Position      */
-#define GPIO_PORT_NOT0_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP7_Pos)                      /*!< GPIO_PORT NOT0: NOTP7 Mask          */
-#define GPIO_PORT_NOT0_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT0: NOTP8 Position      */
-#define GPIO_PORT_NOT0_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP8_Pos)                      /*!< GPIO_PORT NOT0: NOTP8 Mask          */
-#define GPIO_PORT_NOT0_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT0: NOTP9 Position      */
-#define GPIO_PORT_NOT0_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP9_Pos)                      /*!< GPIO_PORT NOT0: NOTP9 Mask          */
-#define GPIO_PORT_NOT0_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT0: NOTP10 Position     */
-#define GPIO_PORT_NOT0_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP10_Pos)                     /*!< GPIO_PORT NOT0: NOTP10 Mask         */
-#define GPIO_PORT_NOT0_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT0: NOTP11 Position     */
-#define GPIO_PORT_NOT0_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP11_Pos)                     /*!< GPIO_PORT NOT0: NOTP11 Mask         */
-#define GPIO_PORT_NOT0_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT0: NOTP12 Position     */
-#define GPIO_PORT_NOT0_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP12_Pos)                     /*!< GPIO_PORT NOT0: NOTP12 Mask         */
-#define GPIO_PORT_NOT0_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT0: NOTP13 Position     */
-#define GPIO_PORT_NOT0_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP13_Pos)                     /*!< GPIO_PORT NOT0: NOTP13 Mask         */
-#define GPIO_PORT_NOT0_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT0: NOTP14 Position     */
-#define GPIO_PORT_NOT0_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP14_Pos)                     /*!< GPIO_PORT NOT0: NOTP14 Mask         */
-#define GPIO_PORT_NOT0_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT0: NOTP15 Position     */
-#define GPIO_PORT_NOT0_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP15_Pos)                     /*!< GPIO_PORT NOT0: NOTP15 Mask         */
-#define GPIO_PORT_NOT0_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT0: NOTP16 Position     */
-#define GPIO_PORT_NOT0_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP16_Pos)                     /*!< GPIO_PORT NOT0: NOTP16 Mask         */
-#define GPIO_PORT_NOT0_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT0: NOTP17 Position     */
-#define GPIO_PORT_NOT0_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP17_Pos)                     /*!< GPIO_PORT NOT0: NOTP17 Mask         */
-#define GPIO_PORT_NOT0_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT0: NOTP18 Position     */
-#define GPIO_PORT_NOT0_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP18_Pos)                     /*!< GPIO_PORT NOT0: NOTP18 Mask         */
-#define GPIO_PORT_NOT0_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT0: NOTP19 Position     */
-#define GPIO_PORT_NOT0_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP19_Pos)                     /*!< GPIO_PORT NOT0: NOTP19 Mask         */
-#define GPIO_PORT_NOT0_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT0: NOTP20 Position     */
-#define GPIO_PORT_NOT0_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP20_Pos)                     /*!< GPIO_PORT NOT0: NOTP20 Mask         */
-#define GPIO_PORT_NOT0_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT0: NOTP21 Position     */
-#define GPIO_PORT_NOT0_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP21_Pos)                     /*!< GPIO_PORT NOT0: NOTP21 Mask         */
-#define GPIO_PORT_NOT0_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT0: NOTP22 Position     */
-#define GPIO_PORT_NOT0_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP22_Pos)                     /*!< GPIO_PORT NOT0: NOTP22 Mask         */
-#define GPIO_PORT_NOT0_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT0: NOTP23 Position     */
-#define GPIO_PORT_NOT0_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP23_Pos)                     /*!< GPIO_PORT NOT0: NOTP23 Mask         */
-#define GPIO_PORT_NOT0_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT0: NOTP24 Position     */
-#define GPIO_PORT_NOT0_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP24_Pos)                     /*!< GPIO_PORT NOT0: NOTP24 Mask         */
-#define GPIO_PORT_NOT0_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT0: NOTP25 Position     */
-#define GPIO_PORT_NOT0_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP25_Pos)                     /*!< GPIO_PORT NOT0: NOTP25 Mask         */
-#define GPIO_PORT_NOT0_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT0: NOTP26 Position     */
-#define GPIO_PORT_NOT0_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP26_Pos)                     /*!< GPIO_PORT NOT0: NOTP26 Mask         */
-#define GPIO_PORT_NOT0_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT0: NOTP27 Position     */
-#define GPIO_PORT_NOT0_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP27_Pos)                     /*!< GPIO_PORT NOT0: NOTP27 Mask         */
-#define GPIO_PORT_NOT0_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT0: NOTP28 Position     */
-#define GPIO_PORT_NOT0_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP28_Pos)                     /*!< GPIO_PORT NOT0: NOTP28 Mask         */
-#define GPIO_PORT_NOT0_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT0: NOTP29 Position     */
-#define GPIO_PORT_NOT0_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP29_Pos)                     /*!< GPIO_PORT NOT0: NOTP29 Mask         */
-#define GPIO_PORT_NOT0_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT0: NOTP30 Position     */
-#define GPIO_PORT_NOT0_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP30_Pos)                     /*!< GPIO_PORT NOT0: NOTP30 Mask         */
-#define GPIO_PORT_NOT0_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT0: NOTP31 Position     */
-#define GPIO_PORT_NOT0_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP31_Pos)                     /*!< GPIO_PORT NOT0: NOTP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_NOT1  -----------------------------------------
-#define GPIO_PORT_NOT1_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT1: NOTP0 Position      */
-#define GPIO_PORT_NOT1_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP0_Pos)                      /*!< GPIO_PORT NOT1: NOTP0 Mask          */
-#define GPIO_PORT_NOT1_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT1: NOTP1 Position      */
-#define GPIO_PORT_NOT1_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP1_Pos)                      /*!< GPIO_PORT NOT1: NOTP1 Mask          */
-#define GPIO_PORT_NOT1_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT1: NOTP2 Position      */
-#define GPIO_PORT_NOT1_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP2_Pos)                      /*!< GPIO_PORT NOT1: NOTP2 Mask          */
-#define GPIO_PORT_NOT1_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT1: NOTP3 Position      */
-#define GPIO_PORT_NOT1_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP3_Pos)                      /*!< GPIO_PORT NOT1: NOTP3 Mask          */
-#define GPIO_PORT_NOT1_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT1: NOTP4 Position      */
-#define GPIO_PORT_NOT1_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP4_Pos)                      /*!< GPIO_PORT NOT1: NOTP4 Mask          */
-#define GPIO_PORT_NOT1_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT1: NOTP5 Position      */
-#define GPIO_PORT_NOT1_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP5_Pos)                      /*!< GPIO_PORT NOT1: NOTP5 Mask          */
-#define GPIO_PORT_NOT1_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT1: NOTP6 Position      */
-#define GPIO_PORT_NOT1_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP6_Pos)                      /*!< GPIO_PORT NOT1: NOTP6 Mask          */
-#define GPIO_PORT_NOT1_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT1: NOTP7 Position      */
-#define GPIO_PORT_NOT1_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP7_Pos)                      /*!< GPIO_PORT NOT1: NOTP7 Mask          */
-#define GPIO_PORT_NOT1_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT1: NOTP8 Position      */
-#define GPIO_PORT_NOT1_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP8_Pos)                      /*!< GPIO_PORT NOT1: NOTP8 Mask          */
-#define GPIO_PORT_NOT1_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT1: NOTP9 Position      */
-#define GPIO_PORT_NOT1_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP9_Pos)                      /*!< GPIO_PORT NOT1: NOTP9 Mask          */
-#define GPIO_PORT_NOT1_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT1: NOTP10 Position     */
-#define GPIO_PORT_NOT1_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP10_Pos)                     /*!< GPIO_PORT NOT1: NOTP10 Mask         */
-#define GPIO_PORT_NOT1_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT1: NOTP11 Position     */
-#define GPIO_PORT_NOT1_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP11_Pos)                     /*!< GPIO_PORT NOT1: NOTP11 Mask         */
-#define GPIO_PORT_NOT1_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT1: NOTP12 Position     */
-#define GPIO_PORT_NOT1_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP12_Pos)                     /*!< GPIO_PORT NOT1: NOTP12 Mask         */
-#define GPIO_PORT_NOT1_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT1: NOTP13 Position     */
-#define GPIO_PORT_NOT1_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP13_Pos)                     /*!< GPIO_PORT NOT1: NOTP13 Mask         */
-#define GPIO_PORT_NOT1_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT1: NOTP14 Position     */
-#define GPIO_PORT_NOT1_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP14_Pos)                     /*!< GPIO_PORT NOT1: NOTP14 Mask         */
-#define GPIO_PORT_NOT1_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT1: NOTP15 Position     */
-#define GPIO_PORT_NOT1_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP15_Pos)                     /*!< GPIO_PORT NOT1: NOTP15 Mask         */
-#define GPIO_PORT_NOT1_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT1: NOTP16 Position     */
-#define GPIO_PORT_NOT1_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP16_Pos)                     /*!< GPIO_PORT NOT1: NOTP16 Mask         */
-#define GPIO_PORT_NOT1_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT1: NOTP17 Position     */
-#define GPIO_PORT_NOT1_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP17_Pos)                     /*!< GPIO_PORT NOT1: NOTP17 Mask         */
-#define GPIO_PORT_NOT1_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT1: NOTP18 Position     */
-#define GPIO_PORT_NOT1_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP18_Pos)                     /*!< GPIO_PORT NOT1: NOTP18 Mask         */
-#define GPIO_PORT_NOT1_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT1: NOTP19 Position     */
-#define GPIO_PORT_NOT1_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP19_Pos)                     /*!< GPIO_PORT NOT1: NOTP19 Mask         */
-#define GPIO_PORT_NOT1_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT1: NOTP20 Position     */
-#define GPIO_PORT_NOT1_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP20_Pos)                     /*!< GPIO_PORT NOT1: NOTP20 Mask         */
-#define GPIO_PORT_NOT1_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT1: NOTP21 Position     */
-#define GPIO_PORT_NOT1_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP21_Pos)                     /*!< GPIO_PORT NOT1: NOTP21 Mask         */
-#define GPIO_PORT_NOT1_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT1: NOTP22 Position     */
-#define GPIO_PORT_NOT1_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP22_Pos)                     /*!< GPIO_PORT NOT1: NOTP22 Mask         */
-#define GPIO_PORT_NOT1_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT1: NOTP23 Position     */
-#define GPIO_PORT_NOT1_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP23_Pos)                     /*!< GPIO_PORT NOT1: NOTP23 Mask         */
-#define GPIO_PORT_NOT1_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT1: NOTP24 Position     */
-#define GPIO_PORT_NOT1_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP24_Pos)                     /*!< GPIO_PORT NOT1: NOTP24 Mask         */
-#define GPIO_PORT_NOT1_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT1: NOTP25 Position     */
-#define GPIO_PORT_NOT1_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP25_Pos)                     /*!< GPIO_PORT NOT1: NOTP25 Mask         */
-#define GPIO_PORT_NOT1_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT1: NOTP26 Position     */
-#define GPIO_PORT_NOT1_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP26_Pos)                     /*!< GPIO_PORT NOT1: NOTP26 Mask         */
-#define GPIO_PORT_NOT1_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT1: NOTP27 Position     */
-#define GPIO_PORT_NOT1_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP27_Pos)                     /*!< GPIO_PORT NOT1: NOTP27 Mask         */
-#define GPIO_PORT_NOT1_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT1: NOTP28 Position     */
-#define GPIO_PORT_NOT1_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP28_Pos)                     /*!< GPIO_PORT NOT1: NOTP28 Mask         */
-#define GPIO_PORT_NOT1_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT1: NOTP29 Position     */
-#define GPIO_PORT_NOT1_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP29_Pos)                     /*!< GPIO_PORT NOT1: NOTP29 Mask         */
-#define GPIO_PORT_NOT1_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT1: NOTP30 Position     */
-#define GPIO_PORT_NOT1_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP30_Pos)                     /*!< GPIO_PORT NOT1: NOTP30 Mask         */
-#define GPIO_PORT_NOT1_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT1: NOTP31 Position     */
-#define GPIO_PORT_NOT1_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP31_Pos)                     /*!< GPIO_PORT NOT1: NOTP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_NOT2  -----------------------------------------
-#define GPIO_PORT_NOT2_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT2: NOTP0 Position      */
-#define GPIO_PORT_NOT2_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP0_Pos)                      /*!< GPIO_PORT NOT2: NOTP0 Mask          */
-#define GPIO_PORT_NOT2_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT2: NOTP1 Position      */
-#define GPIO_PORT_NOT2_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP1_Pos)                      /*!< GPIO_PORT NOT2: NOTP1 Mask          */
-#define GPIO_PORT_NOT2_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT2: NOTP2 Position      */
-#define GPIO_PORT_NOT2_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP2_Pos)                      /*!< GPIO_PORT NOT2: NOTP2 Mask          */
-#define GPIO_PORT_NOT2_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT2: NOTP3 Position      */
-#define GPIO_PORT_NOT2_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP3_Pos)                      /*!< GPIO_PORT NOT2: NOTP3 Mask          */
-#define GPIO_PORT_NOT2_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT2: NOTP4 Position      */
-#define GPIO_PORT_NOT2_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP4_Pos)                      /*!< GPIO_PORT NOT2: NOTP4 Mask          */
-#define GPIO_PORT_NOT2_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT2: NOTP5 Position      */
-#define GPIO_PORT_NOT2_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP5_Pos)                      /*!< GPIO_PORT NOT2: NOTP5 Mask          */
-#define GPIO_PORT_NOT2_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT2: NOTP6 Position      */
-#define GPIO_PORT_NOT2_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP6_Pos)                      /*!< GPIO_PORT NOT2: NOTP6 Mask          */
-#define GPIO_PORT_NOT2_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT2: NOTP7 Position      */
-#define GPIO_PORT_NOT2_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP7_Pos)                      /*!< GPIO_PORT NOT2: NOTP7 Mask          */
-#define GPIO_PORT_NOT2_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT2: NOTP8 Position      */
-#define GPIO_PORT_NOT2_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP8_Pos)                      /*!< GPIO_PORT NOT2: NOTP8 Mask          */
-#define GPIO_PORT_NOT2_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT2: NOTP9 Position      */
-#define GPIO_PORT_NOT2_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP9_Pos)                      /*!< GPIO_PORT NOT2: NOTP9 Mask          */
-#define GPIO_PORT_NOT2_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT2: NOTP10 Position     */
-#define GPIO_PORT_NOT2_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP10_Pos)                     /*!< GPIO_PORT NOT2: NOTP10 Mask         */
-#define GPIO_PORT_NOT2_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT2: NOTP11 Position     */
-#define GPIO_PORT_NOT2_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP11_Pos)                     /*!< GPIO_PORT NOT2: NOTP11 Mask         */
-#define GPIO_PORT_NOT2_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT2: NOTP12 Position     */
-#define GPIO_PORT_NOT2_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP12_Pos)                     /*!< GPIO_PORT NOT2: NOTP12 Mask         */
-#define GPIO_PORT_NOT2_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT2: NOTP13 Position     */
-#define GPIO_PORT_NOT2_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP13_Pos)                     /*!< GPIO_PORT NOT2: NOTP13 Mask         */
-#define GPIO_PORT_NOT2_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT2: NOTP14 Position     */
-#define GPIO_PORT_NOT2_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP14_Pos)                     /*!< GPIO_PORT NOT2: NOTP14 Mask         */
-#define GPIO_PORT_NOT2_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT2: NOTP15 Position     */
-#define GPIO_PORT_NOT2_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP15_Pos)                     /*!< GPIO_PORT NOT2: NOTP15 Mask         */
-#define GPIO_PORT_NOT2_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT2: NOTP16 Position     */
-#define GPIO_PORT_NOT2_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP16_Pos)                     /*!< GPIO_PORT NOT2: NOTP16 Mask         */
-#define GPIO_PORT_NOT2_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT2: NOTP17 Position     */
-#define GPIO_PORT_NOT2_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP17_Pos)                     /*!< GPIO_PORT NOT2: NOTP17 Mask         */
-#define GPIO_PORT_NOT2_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT2: NOTP18 Position     */
-#define GPIO_PORT_NOT2_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP18_Pos)                     /*!< GPIO_PORT NOT2: NOTP18 Mask         */
-#define GPIO_PORT_NOT2_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT2: NOTP19 Position     */
-#define GPIO_PORT_NOT2_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP19_Pos)                     /*!< GPIO_PORT NOT2: NOTP19 Mask         */
-#define GPIO_PORT_NOT2_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT2: NOTP20 Position     */
-#define GPIO_PORT_NOT2_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP20_Pos)                     /*!< GPIO_PORT NOT2: NOTP20 Mask         */
-#define GPIO_PORT_NOT2_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT2: NOTP21 Position     */
-#define GPIO_PORT_NOT2_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP21_Pos)                     /*!< GPIO_PORT NOT2: NOTP21 Mask         */
-#define GPIO_PORT_NOT2_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT2: NOTP22 Position     */
-#define GPIO_PORT_NOT2_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP22_Pos)                     /*!< GPIO_PORT NOT2: NOTP22 Mask         */
-#define GPIO_PORT_NOT2_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT2: NOTP23 Position     */
-#define GPIO_PORT_NOT2_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP23_Pos)                     /*!< GPIO_PORT NOT2: NOTP23 Mask         */
-#define GPIO_PORT_NOT2_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT2: NOTP24 Position     */
-#define GPIO_PORT_NOT2_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP24_Pos)                     /*!< GPIO_PORT NOT2: NOTP24 Mask         */
-#define GPIO_PORT_NOT2_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT2: NOTP25 Position     */
-#define GPIO_PORT_NOT2_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP25_Pos)                     /*!< GPIO_PORT NOT2: NOTP25 Mask         */
-#define GPIO_PORT_NOT2_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT2: NOTP26 Position     */
-#define GPIO_PORT_NOT2_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP26_Pos)                     /*!< GPIO_PORT NOT2: NOTP26 Mask         */
-#define GPIO_PORT_NOT2_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT2: NOTP27 Position     */
-#define GPIO_PORT_NOT2_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP27_Pos)                     /*!< GPIO_PORT NOT2: NOTP27 Mask         */
-#define GPIO_PORT_NOT2_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT2: NOTP28 Position     */
-#define GPIO_PORT_NOT2_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP28_Pos)                     /*!< GPIO_PORT NOT2: NOTP28 Mask         */
-#define GPIO_PORT_NOT2_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT2: NOTP29 Position     */
-#define GPIO_PORT_NOT2_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP29_Pos)                     /*!< GPIO_PORT NOT2: NOTP29 Mask         */
-#define GPIO_PORT_NOT2_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT2: NOTP30 Position     */
-#define GPIO_PORT_NOT2_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP30_Pos)                     /*!< GPIO_PORT NOT2: NOTP30 Mask         */
-#define GPIO_PORT_NOT2_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT2: NOTP31 Position     */
-#define GPIO_PORT_NOT2_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP31_Pos)                     /*!< GPIO_PORT NOT2: NOTP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_NOT3  -----------------------------------------
-#define GPIO_PORT_NOT3_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT3: NOTP0 Position      */
-#define GPIO_PORT_NOT3_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP0_Pos)                      /*!< GPIO_PORT NOT3: NOTP0 Mask          */
-#define GPIO_PORT_NOT3_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT3: NOTP1 Position      */
-#define GPIO_PORT_NOT3_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP1_Pos)                      /*!< GPIO_PORT NOT3: NOTP1 Mask          */
-#define GPIO_PORT_NOT3_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT3: NOTP2 Position      */
-#define GPIO_PORT_NOT3_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP2_Pos)                      /*!< GPIO_PORT NOT3: NOTP2 Mask          */
-#define GPIO_PORT_NOT3_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT3: NOTP3 Position      */
-#define GPIO_PORT_NOT3_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP3_Pos)                      /*!< GPIO_PORT NOT3: NOTP3 Mask          */
-#define GPIO_PORT_NOT3_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT3: NOTP4 Position      */
-#define GPIO_PORT_NOT3_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP4_Pos)                      /*!< GPIO_PORT NOT3: NOTP4 Mask          */
-#define GPIO_PORT_NOT3_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT3: NOTP5 Position      */
-#define GPIO_PORT_NOT3_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP5_Pos)                      /*!< GPIO_PORT NOT3: NOTP5 Mask          */
-#define GPIO_PORT_NOT3_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT3: NOTP6 Position      */
-#define GPIO_PORT_NOT3_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP6_Pos)                      /*!< GPIO_PORT NOT3: NOTP6 Mask          */
-#define GPIO_PORT_NOT3_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT3: NOTP7 Position      */
-#define GPIO_PORT_NOT3_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP7_Pos)                      /*!< GPIO_PORT NOT3: NOTP7 Mask          */
-#define GPIO_PORT_NOT3_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT3: NOTP8 Position      */
-#define GPIO_PORT_NOT3_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP8_Pos)                      /*!< GPIO_PORT NOT3: NOTP8 Mask          */
-#define GPIO_PORT_NOT3_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT3: NOTP9 Position      */
-#define GPIO_PORT_NOT3_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP9_Pos)                      /*!< GPIO_PORT NOT3: NOTP9 Mask          */
-#define GPIO_PORT_NOT3_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT3: NOTP10 Position     */
-#define GPIO_PORT_NOT3_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP10_Pos)                     /*!< GPIO_PORT NOT3: NOTP10 Mask         */
-#define GPIO_PORT_NOT3_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT3: NOTP11 Position     */
-#define GPIO_PORT_NOT3_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP11_Pos)                     /*!< GPIO_PORT NOT3: NOTP11 Mask         */
-#define GPIO_PORT_NOT3_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT3: NOTP12 Position     */
-#define GPIO_PORT_NOT3_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP12_Pos)                     /*!< GPIO_PORT NOT3: NOTP12 Mask         */
-#define GPIO_PORT_NOT3_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT3: NOTP13 Position     */
-#define GPIO_PORT_NOT3_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP13_Pos)                     /*!< GPIO_PORT NOT3: NOTP13 Mask         */
-#define GPIO_PORT_NOT3_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT3: NOTP14 Position     */
-#define GPIO_PORT_NOT3_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP14_Pos)                     /*!< GPIO_PORT NOT3: NOTP14 Mask         */
-#define GPIO_PORT_NOT3_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT3: NOTP15 Position     */
-#define GPIO_PORT_NOT3_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP15_Pos)                     /*!< GPIO_PORT NOT3: NOTP15 Mask         */
-#define GPIO_PORT_NOT3_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT3: NOTP16 Position     */
-#define GPIO_PORT_NOT3_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP16_Pos)                     /*!< GPIO_PORT NOT3: NOTP16 Mask         */
-#define GPIO_PORT_NOT3_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT3: NOTP17 Position     */
-#define GPIO_PORT_NOT3_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP17_Pos)                     /*!< GPIO_PORT NOT3: NOTP17 Mask         */
-#define GPIO_PORT_NOT3_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT3: NOTP18 Position     */
-#define GPIO_PORT_NOT3_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP18_Pos)                     /*!< GPIO_PORT NOT3: NOTP18 Mask         */
-#define GPIO_PORT_NOT3_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT3: NOTP19 Position     */
-#define GPIO_PORT_NOT3_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP19_Pos)                     /*!< GPIO_PORT NOT3: NOTP19 Mask         */
-#define GPIO_PORT_NOT3_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT3: NOTP20 Position     */
-#define GPIO_PORT_NOT3_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP20_Pos)                     /*!< GPIO_PORT NOT3: NOTP20 Mask         */
-#define GPIO_PORT_NOT3_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT3: NOTP21 Position     */
-#define GPIO_PORT_NOT3_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP21_Pos)                     /*!< GPIO_PORT NOT3: NOTP21 Mask         */
-#define GPIO_PORT_NOT3_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT3: NOTP22 Position     */
-#define GPIO_PORT_NOT3_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP22_Pos)                     /*!< GPIO_PORT NOT3: NOTP22 Mask         */
-#define GPIO_PORT_NOT3_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT3: NOTP23 Position     */
-#define GPIO_PORT_NOT3_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP23_Pos)                     /*!< GPIO_PORT NOT3: NOTP23 Mask         */
-#define GPIO_PORT_NOT3_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT3: NOTP24 Position     */
-#define GPIO_PORT_NOT3_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP24_Pos)                     /*!< GPIO_PORT NOT3: NOTP24 Mask         */
-#define GPIO_PORT_NOT3_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT3: NOTP25 Position     */
-#define GPIO_PORT_NOT3_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP25_Pos)                     /*!< GPIO_PORT NOT3: NOTP25 Mask         */
-#define GPIO_PORT_NOT3_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT3: NOTP26 Position     */
-#define GPIO_PORT_NOT3_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP26_Pos)                     /*!< GPIO_PORT NOT3: NOTP26 Mask         */
-#define GPIO_PORT_NOT3_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT3: NOTP27 Position     */
-#define GPIO_PORT_NOT3_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP27_Pos)                     /*!< GPIO_PORT NOT3: NOTP27 Mask         */
-#define GPIO_PORT_NOT3_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT3: NOTP28 Position     */
-#define GPIO_PORT_NOT3_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP28_Pos)                     /*!< GPIO_PORT NOT3: NOTP28 Mask         */
-#define GPIO_PORT_NOT3_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT3: NOTP29 Position     */
-#define GPIO_PORT_NOT3_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP29_Pos)                     /*!< GPIO_PORT NOT3: NOTP29 Mask         */
-#define GPIO_PORT_NOT3_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT3: NOTP30 Position     */
-#define GPIO_PORT_NOT3_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP30_Pos)                     /*!< GPIO_PORT NOT3: NOTP30 Mask         */
-#define GPIO_PORT_NOT3_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT3: NOTP31 Position     */
-#define GPIO_PORT_NOT3_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP31_Pos)                     /*!< GPIO_PORT NOT3: NOTP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_NOT4  -----------------------------------------
-#define GPIO_PORT_NOT4_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT4: NOTP0 Position      */
-#define GPIO_PORT_NOT4_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP0_Pos)                      /*!< GPIO_PORT NOT4: NOTP0 Mask          */
-#define GPIO_PORT_NOT4_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT4: NOTP1 Position      */
-#define GPIO_PORT_NOT4_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP1_Pos)                      /*!< GPIO_PORT NOT4: NOTP1 Mask          */
-#define GPIO_PORT_NOT4_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT4: NOTP2 Position      */
-#define GPIO_PORT_NOT4_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP2_Pos)                      /*!< GPIO_PORT NOT4: NOTP2 Mask          */
-#define GPIO_PORT_NOT4_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT4: NOTP3 Position      */
-#define GPIO_PORT_NOT4_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP3_Pos)                      /*!< GPIO_PORT NOT4: NOTP3 Mask          */
-#define GPIO_PORT_NOT4_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT4: NOTP4 Position      */
-#define GPIO_PORT_NOT4_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP4_Pos)                      /*!< GPIO_PORT NOT4: NOTP4 Mask          */
-#define GPIO_PORT_NOT4_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT4: NOTP5 Position      */
-#define GPIO_PORT_NOT4_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP5_Pos)                      /*!< GPIO_PORT NOT4: NOTP5 Mask          */
-#define GPIO_PORT_NOT4_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT4: NOTP6 Position      */
-#define GPIO_PORT_NOT4_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP6_Pos)                      /*!< GPIO_PORT NOT4: NOTP6 Mask          */
-#define GPIO_PORT_NOT4_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT4: NOTP7 Position      */
-#define GPIO_PORT_NOT4_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP7_Pos)                      /*!< GPIO_PORT NOT4: NOTP7 Mask          */
-#define GPIO_PORT_NOT4_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT4: NOTP8 Position      */
-#define GPIO_PORT_NOT4_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP8_Pos)                      /*!< GPIO_PORT NOT4: NOTP8 Mask          */
-#define GPIO_PORT_NOT4_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT4: NOTP9 Position      */
-#define GPIO_PORT_NOT4_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP9_Pos)                      /*!< GPIO_PORT NOT4: NOTP9 Mask          */
-#define GPIO_PORT_NOT4_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT4: NOTP10 Position     */
-#define GPIO_PORT_NOT4_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP10_Pos)                     /*!< GPIO_PORT NOT4: NOTP10 Mask         */
-#define GPIO_PORT_NOT4_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT4: NOTP11 Position     */
-#define GPIO_PORT_NOT4_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP11_Pos)                     /*!< GPIO_PORT NOT4: NOTP11 Mask         */
-#define GPIO_PORT_NOT4_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT4: NOTP12 Position     */
-#define GPIO_PORT_NOT4_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP12_Pos)                     /*!< GPIO_PORT NOT4: NOTP12 Mask         */
-#define GPIO_PORT_NOT4_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT4: NOTP13 Position     */
-#define GPIO_PORT_NOT4_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP13_Pos)                     /*!< GPIO_PORT NOT4: NOTP13 Mask         */
-#define GPIO_PORT_NOT4_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT4: NOTP14 Position     */
-#define GPIO_PORT_NOT4_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP14_Pos)                     /*!< GPIO_PORT NOT4: NOTP14 Mask         */
-#define GPIO_PORT_NOT4_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT4: NOTP15 Position     */
-#define GPIO_PORT_NOT4_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP15_Pos)                     /*!< GPIO_PORT NOT4: NOTP15 Mask         */
-#define GPIO_PORT_NOT4_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT4: NOTP16 Position     */
-#define GPIO_PORT_NOT4_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP16_Pos)                     /*!< GPIO_PORT NOT4: NOTP16 Mask         */
-#define GPIO_PORT_NOT4_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT4: NOTP17 Position     */
-#define GPIO_PORT_NOT4_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP17_Pos)                     /*!< GPIO_PORT NOT4: NOTP17 Mask         */
-#define GPIO_PORT_NOT4_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT4: NOTP18 Position     */
-#define GPIO_PORT_NOT4_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP18_Pos)                     /*!< GPIO_PORT NOT4: NOTP18 Mask         */
-#define GPIO_PORT_NOT4_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT4: NOTP19 Position     */
-#define GPIO_PORT_NOT4_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP19_Pos)                     /*!< GPIO_PORT NOT4: NOTP19 Mask         */
-#define GPIO_PORT_NOT4_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT4: NOTP20 Position     */
-#define GPIO_PORT_NOT4_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP20_Pos)                     /*!< GPIO_PORT NOT4: NOTP20 Mask         */
-#define GPIO_PORT_NOT4_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT4: NOTP21 Position     */
-#define GPIO_PORT_NOT4_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP21_Pos)                     /*!< GPIO_PORT NOT4: NOTP21 Mask         */
-#define GPIO_PORT_NOT4_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT4: NOTP22 Position     */
-#define GPIO_PORT_NOT4_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP22_Pos)                     /*!< GPIO_PORT NOT4: NOTP22 Mask         */
-#define GPIO_PORT_NOT4_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT4: NOTP23 Position     */
-#define GPIO_PORT_NOT4_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP23_Pos)                     /*!< GPIO_PORT NOT4: NOTP23 Mask         */
-#define GPIO_PORT_NOT4_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT4: NOTP24 Position     */
-#define GPIO_PORT_NOT4_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP24_Pos)                     /*!< GPIO_PORT NOT4: NOTP24 Mask         */
-#define GPIO_PORT_NOT4_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT4: NOTP25 Position     */
-#define GPIO_PORT_NOT4_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP25_Pos)                     /*!< GPIO_PORT NOT4: NOTP25 Mask         */
-#define GPIO_PORT_NOT4_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT4: NOTP26 Position     */
-#define GPIO_PORT_NOT4_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP26_Pos)                     /*!< GPIO_PORT NOT4: NOTP26 Mask         */
-#define GPIO_PORT_NOT4_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT4: NOTP27 Position     */
-#define GPIO_PORT_NOT4_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP27_Pos)                     /*!< GPIO_PORT NOT4: NOTP27 Mask         */
-#define GPIO_PORT_NOT4_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT4: NOTP28 Position     */
-#define GPIO_PORT_NOT4_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP28_Pos)                     /*!< GPIO_PORT NOT4: NOTP28 Mask         */
-#define GPIO_PORT_NOT4_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT4: NOTP29 Position     */
-#define GPIO_PORT_NOT4_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP29_Pos)                     /*!< GPIO_PORT NOT4: NOTP29 Mask         */
-#define GPIO_PORT_NOT4_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT4: NOTP30 Position     */
-#define GPIO_PORT_NOT4_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP30_Pos)                     /*!< GPIO_PORT NOT4: NOTP30 Mask         */
-#define GPIO_PORT_NOT4_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT4: NOTP31 Position     */
-#define GPIO_PORT_NOT4_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP31_Pos)                     /*!< GPIO_PORT NOT4: NOTP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_NOT5  -----------------------------------------
-#define GPIO_PORT_NOT5_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT5: NOTP0 Position      */
-#define GPIO_PORT_NOT5_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP0_Pos)                      /*!< GPIO_PORT NOT5: NOTP0 Mask          */
-#define GPIO_PORT_NOT5_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT5: NOTP1 Position      */
-#define GPIO_PORT_NOT5_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP1_Pos)                      /*!< GPIO_PORT NOT5: NOTP1 Mask          */
-#define GPIO_PORT_NOT5_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT5: NOTP2 Position      */
-#define GPIO_PORT_NOT5_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP2_Pos)                      /*!< GPIO_PORT NOT5: NOTP2 Mask          */
-#define GPIO_PORT_NOT5_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT5: NOTP3 Position      */
-#define GPIO_PORT_NOT5_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP3_Pos)                      /*!< GPIO_PORT NOT5: NOTP3 Mask          */
-#define GPIO_PORT_NOT5_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT5: NOTP4 Position      */
-#define GPIO_PORT_NOT5_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP4_Pos)                      /*!< GPIO_PORT NOT5: NOTP4 Mask          */
-#define GPIO_PORT_NOT5_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT5: NOTP5 Position      */
-#define GPIO_PORT_NOT5_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP5_Pos)                      /*!< GPIO_PORT NOT5: NOTP5 Mask          */
-#define GPIO_PORT_NOT5_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT5: NOTP6 Position      */
-#define GPIO_PORT_NOT5_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP6_Pos)                      /*!< GPIO_PORT NOT5: NOTP6 Mask          */
-#define GPIO_PORT_NOT5_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT5: NOTP7 Position      */
-#define GPIO_PORT_NOT5_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP7_Pos)                      /*!< GPIO_PORT NOT5: NOTP7 Mask          */
-#define GPIO_PORT_NOT5_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT5: NOTP8 Position      */
-#define GPIO_PORT_NOT5_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP8_Pos)                      /*!< GPIO_PORT NOT5: NOTP8 Mask          */
-#define GPIO_PORT_NOT5_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT5: NOTP9 Position      */
-#define GPIO_PORT_NOT5_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP9_Pos)                      /*!< GPIO_PORT NOT5: NOTP9 Mask          */
-#define GPIO_PORT_NOT5_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT5: NOTP10 Position     */
-#define GPIO_PORT_NOT5_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP10_Pos)                     /*!< GPIO_PORT NOT5: NOTP10 Mask         */
-#define GPIO_PORT_NOT5_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT5: NOTP11 Position     */
-#define GPIO_PORT_NOT5_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP11_Pos)                     /*!< GPIO_PORT NOT5: NOTP11 Mask         */
-#define GPIO_PORT_NOT5_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT5: NOTP12 Position     */
-#define GPIO_PORT_NOT5_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP12_Pos)                     /*!< GPIO_PORT NOT5: NOTP12 Mask         */
-#define GPIO_PORT_NOT5_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT5: NOTP13 Position     */
-#define GPIO_PORT_NOT5_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP13_Pos)                     /*!< GPIO_PORT NOT5: NOTP13 Mask         */
-#define GPIO_PORT_NOT5_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT5: NOTP14 Position     */
-#define GPIO_PORT_NOT5_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP14_Pos)                     /*!< GPIO_PORT NOT5: NOTP14 Mask         */
-#define GPIO_PORT_NOT5_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT5: NOTP15 Position     */
-#define GPIO_PORT_NOT5_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP15_Pos)                     /*!< GPIO_PORT NOT5: NOTP15 Mask         */
-#define GPIO_PORT_NOT5_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT5: NOTP16 Position     */
-#define GPIO_PORT_NOT5_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP16_Pos)                     /*!< GPIO_PORT NOT5: NOTP16 Mask         */
-#define GPIO_PORT_NOT5_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT5: NOTP17 Position     */
-#define GPIO_PORT_NOT5_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP17_Pos)                     /*!< GPIO_PORT NOT5: NOTP17 Mask         */
-#define GPIO_PORT_NOT5_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT5: NOTP18 Position     */
-#define GPIO_PORT_NOT5_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP18_Pos)                     /*!< GPIO_PORT NOT5: NOTP18 Mask         */
-#define GPIO_PORT_NOT5_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT5: NOTP19 Position     */
-#define GPIO_PORT_NOT5_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP19_Pos)                     /*!< GPIO_PORT NOT5: NOTP19 Mask         */
-#define GPIO_PORT_NOT5_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT5: NOTP20 Position     */
-#define GPIO_PORT_NOT5_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP20_Pos)                     /*!< GPIO_PORT NOT5: NOTP20 Mask         */
-#define GPIO_PORT_NOT5_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT5: NOTP21 Position     */
-#define GPIO_PORT_NOT5_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP21_Pos)                     /*!< GPIO_PORT NOT5: NOTP21 Mask         */
-#define GPIO_PORT_NOT5_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT5: NOTP22 Position     */
-#define GPIO_PORT_NOT5_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP22_Pos)                     /*!< GPIO_PORT NOT5: NOTP22 Mask         */
-#define GPIO_PORT_NOT5_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT5: NOTP23 Position     */
-#define GPIO_PORT_NOT5_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP23_Pos)                     /*!< GPIO_PORT NOT5: NOTP23 Mask         */
-#define GPIO_PORT_NOT5_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT5: NOTP24 Position     */
-#define GPIO_PORT_NOT5_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP24_Pos)                     /*!< GPIO_PORT NOT5: NOTP24 Mask         */
-#define GPIO_PORT_NOT5_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT5: NOTP25 Position     */
-#define GPIO_PORT_NOT5_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP25_Pos)                     /*!< GPIO_PORT NOT5: NOTP25 Mask         */
-#define GPIO_PORT_NOT5_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT5: NOTP26 Position     */
-#define GPIO_PORT_NOT5_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP26_Pos)                     /*!< GPIO_PORT NOT5: NOTP26 Mask         */
-#define GPIO_PORT_NOT5_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT5: NOTP27 Position     */
-#define GPIO_PORT_NOT5_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP27_Pos)                     /*!< GPIO_PORT NOT5: NOTP27 Mask         */
-#define GPIO_PORT_NOT5_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT5: NOTP28 Position     */
-#define GPIO_PORT_NOT5_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP28_Pos)                     /*!< GPIO_PORT NOT5: NOTP28 Mask         */
-#define GPIO_PORT_NOT5_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT5: NOTP29 Position     */
-#define GPIO_PORT_NOT5_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP29_Pos)                     /*!< GPIO_PORT NOT5: NOTP29 Mask         */
-#define GPIO_PORT_NOT5_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT5: NOTP30 Position     */
-#define GPIO_PORT_NOT5_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP30_Pos)                     /*!< GPIO_PORT NOT5: NOTP30 Mask         */
-#define GPIO_PORT_NOT5_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT5: NOTP31 Position     */
-#define GPIO_PORT_NOT5_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP31_Pos)                     /*!< GPIO_PORT NOT5: NOTP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_NOT6  -----------------------------------------
-#define GPIO_PORT_NOT6_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT6: NOTP0 Position      */
-#define GPIO_PORT_NOT6_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP0_Pos)                      /*!< GPIO_PORT NOT6: NOTP0 Mask          */
-#define GPIO_PORT_NOT6_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT6: NOTP1 Position      */
-#define GPIO_PORT_NOT6_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP1_Pos)                      /*!< GPIO_PORT NOT6: NOTP1 Mask          */
-#define GPIO_PORT_NOT6_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT6: NOTP2 Position      */
-#define GPIO_PORT_NOT6_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP2_Pos)                      /*!< GPIO_PORT NOT6: NOTP2 Mask          */
-#define GPIO_PORT_NOT6_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT6: NOTP3 Position      */
-#define GPIO_PORT_NOT6_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP3_Pos)                      /*!< GPIO_PORT NOT6: NOTP3 Mask          */
-#define GPIO_PORT_NOT6_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT6: NOTP4 Position      */
-#define GPIO_PORT_NOT6_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP4_Pos)                      /*!< GPIO_PORT NOT6: NOTP4 Mask          */
-#define GPIO_PORT_NOT6_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT6: NOTP5 Position      */
-#define GPIO_PORT_NOT6_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP5_Pos)                      /*!< GPIO_PORT NOT6: NOTP5 Mask          */
-#define GPIO_PORT_NOT6_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT6: NOTP6 Position      */
-#define GPIO_PORT_NOT6_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP6_Pos)                      /*!< GPIO_PORT NOT6: NOTP6 Mask          */
-#define GPIO_PORT_NOT6_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT6: NOTP7 Position      */
-#define GPIO_PORT_NOT6_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP7_Pos)                      /*!< GPIO_PORT NOT6: NOTP7 Mask          */
-#define GPIO_PORT_NOT6_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT6: NOTP8 Position      */
-#define GPIO_PORT_NOT6_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP8_Pos)                      /*!< GPIO_PORT NOT6: NOTP8 Mask          */
-#define GPIO_PORT_NOT6_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT6: NOTP9 Position      */
-#define GPIO_PORT_NOT6_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP9_Pos)                      /*!< GPIO_PORT NOT6: NOTP9 Mask          */
-#define GPIO_PORT_NOT6_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT6: NOTP10 Position     */
-#define GPIO_PORT_NOT6_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP10_Pos)                     /*!< GPIO_PORT NOT6: NOTP10 Mask         */
-#define GPIO_PORT_NOT6_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT6: NOTP11 Position     */
-#define GPIO_PORT_NOT6_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP11_Pos)                     /*!< GPIO_PORT NOT6: NOTP11 Mask         */
-#define GPIO_PORT_NOT6_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT6: NOTP12 Position     */
-#define GPIO_PORT_NOT6_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP12_Pos)                     /*!< GPIO_PORT NOT6: NOTP12 Mask         */
-#define GPIO_PORT_NOT6_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT6: NOTP13 Position     */
-#define GPIO_PORT_NOT6_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP13_Pos)                     /*!< GPIO_PORT NOT6: NOTP13 Mask         */
-#define GPIO_PORT_NOT6_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT6: NOTP14 Position     */
-#define GPIO_PORT_NOT6_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP14_Pos)                     /*!< GPIO_PORT NOT6: NOTP14 Mask         */
-#define GPIO_PORT_NOT6_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT6: NOTP15 Position     */
-#define GPIO_PORT_NOT6_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP15_Pos)                     /*!< GPIO_PORT NOT6: NOTP15 Mask         */
-#define GPIO_PORT_NOT6_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT6: NOTP16 Position     */
-#define GPIO_PORT_NOT6_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP16_Pos)                     /*!< GPIO_PORT NOT6: NOTP16 Mask         */
-#define GPIO_PORT_NOT6_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT6: NOTP17 Position     */
-#define GPIO_PORT_NOT6_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP17_Pos)                     /*!< GPIO_PORT NOT6: NOTP17 Mask         */
-#define GPIO_PORT_NOT6_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT6: NOTP18 Position     */
-#define GPIO_PORT_NOT6_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP18_Pos)                     /*!< GPIO_PORT NOT6: NOTP18 Mask         */
-#define GPIO_PORT_NOT6_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT6: NOTP19 Position     */
-#define GPIO_PORT_NOT6_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP19_Pos)                     /*!< GPIO_PORT NOT6: NOTP19 Mask         */
-#define GPIO_PORT_NOT6_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT6: NOTP20 Position     */
-#define GPIO_PORT_NOT6_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP20_Pos)                     /*!< GPIO_PORT NOT6: NOTP20 Mask         */
-#define GPIO_PORT_NOT6_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT6: NOTP21 Position     */
-#define GPIO_PORT_NOT6_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP21_Pos)                     /*!< GPIO_PORT NOT6: NOTP21 Mask         */
-#define GPIO_PORT_NOT6_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT6: NOTP22 Position     */
-#define GPIO_PORT_NOT6_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP22_Pos)                     /*!< GPIO_PORT NOT6: NOTP22 Mask         */
-#define GPIO_PORT_NOT6_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT6: NOTP23 Position     */
-#define GPIO_PORT_NOT6_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP23_Pos)                     /*!< GPIO_PORT NOT6: NOTP23 Mask         */
-#define GPIO_PORT_NOT6_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT6: NOTP24 Position     */
-#define GPIO_PORT_NOT6_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP24_Pos)                     /*!< GPIO_PORT NOT6: NOTP24 Mask         */
-#define GPIO_PORT_NOT6_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT6: NOTP25 Position     */
-#define GPIO_PORT_NOT6_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP25_Pos)                     /*!< GPIO_PORT NOT6: NOTP25 Mask         */
-#define GPIO_PORT_NOT6_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT6: NOTP26 Position     */
-#define GPIO_PORT_NOT6_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP26_Pos)                     /*!< GPIO_PORT NOT6: NOTP26 Mask         */
-#define GPIO_PORT_NOT6_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT6: NOTP27 Position     */
-#define GPIO_PORT_NOT6_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP27_Pos)                     /*!< GPIO_PORT NOT6: NOTP27 Mask         */
-#define GPIO_PORT_NOT6_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT6: NOTP28 Position     */
-#define GPIO_PORT_NOT6_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP28_Pos)                     /*!< GPIO_PORT NOT6: NOTP28 Mask         */
-#define GPIO_PORT_NOT6_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT6: NOTP29 Position     */
-#define GPIO_PORT_NOT6_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP29_Pos)                     /*!< GPIO_PORT NOT6: NOTP29 Mask         */
-#define GPIO_PORT_NOT6_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT6: NOTP30 Position     */
-#define GPIO_PORT_NOT6_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP30_Pos)                     /*!< GPIO_PORT NOT6: NOTP30 Mask         */
-#define GPIO_PORT_NOT6_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT6: NOTP31 Position     */
-#define GPIO_PORT_NOT6_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP31_Pos)                     /*!< GPIO_PORT NOT6: NOTP31 Mask         */
-
-// -------------------------------------  GPIO_PORT_NOT7  -----------------------------------------
-#define GPIO_PORT_NOT7_NOTP0_Pos                              0                                                         /*!< GPIO_PORT NOT7: NOTP0 Position      */
-#define GPIO_PORT_NOT7_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP0_Pos)                      /*!< GPIO_PORT NOT7: NOTP0 Mask          */
-#define GPIO_PORT_NOT7_NOTP1_Pos                              1                                                         /*!< GPIO_PORT NOT7: NOTP1 Position      */
-#define GPIO_PORT_NOT7_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP1_Pos)                      /*!< GPIO_PORT NOT7: NOTP1 Mask          */
-#define GPIO_PORT_NOT7_NOTP2_Pos                              2                                                         /*!< GPIO_PORT NOT7: NOTP2 Position      */
-#define GPIO_PORT_NOT7_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP2_Pos)                      /*!< GPIO_PORT NOT7: NOTP2 Mask          */
-#define GPIO_PORT_NOT7_NOTP3_Pos                              3                                                         /*!< GPIO_PORT NOT7: NOTP3 Position      */
-#define GPIO_PORT_NOT7_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP3_Pos)                      /*!< GPIO_PORT NOT7: NOTP3 Mask          */
-#define GPIO_PORT_NOT7_NOTP4_Pos                              4                                                         /*!< GPIO_PORT NOT7: NOTP4 Position      */
-#define GPIO_PORT_NOT7_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP4_Pos)                      /*!< GPIO_PORT NOT7: NOTP4 Mask          */
-#define GPIO_PORT_NOT7_NOTP5_Pos                              5                                                         /*!< GPIO_PORT NOT7: NOTP5 Position      */
-#define GPIO_PORT_NOT7_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP5_Pos)                      /*!< GPIO_PORT NOT7: NOTP5 Mask          */
-#define GPIO_PORT_NOT7_NOTP6_Pos                              6                                                         /*!< GPIO_PORT NOT7: NOTP6 Position      */
-#define GPIO_PORT_NOT7_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP6_Pos)                      /*!< GPIO_PORT NOT7: NOTP6 Mask          */
-#define GPIO_PORT_NOT7_NOTP7_Pos                              7                                                         /*!< GPIO_PORT NOT7: NOTP7 Position      */
-#define GPIO_PORT_NOT7_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP7_Pos)                      /*!< GPIO_PORT NOT7: NOTP7 Mask          */
-#define GPIO_PORT_NOT7_NOTP8_Pos                              8                                                         /*!< GPIO_PORT NOT7: NOTP8 Position      */
-#define GPIO_PORT_NOT7_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP8_Pos)                      /*!< GPIO_PORT NOT7: NOTP8 Mask          */
-#define GPIO_PORT_NOT7_NOTP9_Pos                              9                                                         /*!< GPIO_PORT NOT7: NOTP9 Position      */
-#define GPIO_PORT_NOT7_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP9_Pos)                      /*!< GPIO_PORT NOT7: NOTP9 Mask          */
-#define GPIO_PORT_NOT7_NOTP10_Pos                             10                                                        /*!< GPIO_PORT NOT7: NOTP10 Position     */
-#define GPIO_PORT_NOT7_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP10_Pos)                     /*!< GPIO_PORT NOT7: NOTP10 Mask         */
-#define GPIO_PORT_NOT7_NOTP11_Pos                             11                                                        /*!< GPIO_PORT NOT7: NOTP11 Position     */
-#define GPIO_PORT_NOT7_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP11_Pos)                     /*!< GPIO_PORT NOT7: NOTP11 Mask         */
-#define GPIO_PORT_NOT7_NOTP12_Pos                             12                                                        /*!< GPIO_PORT NOT7: NOTP12 Position     */
-#define GPIO_PORT_NOT7_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP12_Pos)                     /*!< GPIO_PORT NOT7: NOTP12 Mask         */
-#define GPIO_PORT_NOT7_NOTP13_Pos                             13                                                        /*!< GPIO_PORT NOT7: NOTP13 Position     */
-#define GPIO_PORT_NOT7_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP13_Pos)                     /*!< GPIO_PORT NOT7: NOTP13 Mask         */
-#define GPIO_PORT_NOT7_NOTP14_Pos                             14                                                        /*!< GPIO_PORT NOT7: NOTP14 Position     */
-#define GPIO_PORT_NOT7_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP14_Pos)                     /*!< GPIO_PORT NOT7: NOTP14 Mask         */
-#define GPIO_PORT_NOT7_NOTP15_Pos                             15                                                        /*!< GPIO_PORT NOT7: NOTP15 Position     */
-#define GPIO_PORT_NOT7_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP15_Pos)                     /*!< GPIO_PORT NOT7: NOTP15 Mask         */
-#define GPIO_PORT_NOT7_NOTP16_Pos                             16                                                        /*!< GPIO_PORT NOT7: NOTP16 Position     */
-#define GPIO_PORT_NOT7_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP16_Pos)                     /*!< GPIO_PORT NOT7: NOTP16 Mask         */
-#define GPIO_PORT_NOT7_NOTP17_Pos                             17                                                        /*!< GPIO_PORT NOT7: NOTP17 Position     */
-#define GPIO_PORT_NOT7_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP17_Pos)                     /*!< GPIO_PORT NOT7: NOTP17 Mask         */
-#define GPIO_PORT_NOT7_NOTP18_Pos                             18                                                        /*!< GPIO_PORT NOT7: NOTP18 Position     */
-#define GPIO_PORT_NOT7_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP18_Pos)                     /*!< GPIO_PORT NOT7: NOTP18 Mask         */
-#define GPIO_PORT_NOT7_NOTP19_Pos                             19                                                        /*!< GPIO_PORT NOT7: NOTP19 Position     */
-#define GPIO_PORT_NOT7_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP19_Pos)                     /*!< GPIO_PORT NOT7: NOTP19 Mask         */
-#define GPIO_PORT_NOT7_NOTP20_Pos                             20                                                        /*!< GPIO_PORT NOT7: NOTP20 Position     */
-#define GPIO_PORT_NOT7_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP20_Pos)                     /*!< GPIO_PORT NOT7: NOTP20 Mask         */
-#define GPIO_PORT_NOT7_NOTP21_Pos                             21                                                        /*!< GPIO_PORT NOT7: NOTP21 Position     */
-#define GPIO_PORT_NOT7_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP21_Pos)                     /*!< GPIO_PORT NOT7: NOTP21 Mask         */
-#define GPIO_PORT_NOT7_NOTP22_Pos                             22                                                        /*!< GPIO_PORT NOT7: NOTP22 Position     */
-#define GPIO_PORT_NOT7_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP22_Pos)                     /*!< GPIO_PORT NOT7: NOTP22 Mask         */
-#define GPIO_PORT_NOT7_NOTP23_Pos                             23                                                        /*!< GPIO_PORT NOT7: NOTP23 Position     */
-#define GPIO_PORT_NOT7_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP23_Pos)                     /*!< GPIO_PORT NOT7: NOTP23 Mask         */
-#define GPIO_PORT_NOT7_NOTP24_Pos                             24                                                        /*!< GPIO_PORT NOT7: NOTP24 Position     */
-#define GPIO_PORT_NOT7_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP24_Pos)                     /*!< GPIO_PORT NOT7: NOTP24 Mask         */
-#define GPIO_PORT_NOT7_NOTP25_Pos                             25                                                        /*!< GPIO_PORT NOT7: NOTP25 Position     */
-#define GPIO_PORT_NOT7_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP25_Pos)                     /*!< GPIO_PORT NOT7: NOTP25 Mask         */
-#define GPIO_PORT_NOT7_NOTP26_Pos                             26                                                        /*!< GPIO_PORT NOT7: NOTP26 Position     */
-#define GPIO_PORT_NOT7_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP26_Pos)                     /*!< GPIO_PORT NOT7: NOTP26 Mask         */
-#define GPIO_PORT_NOT7_NOTP27_Pos                             27                                                        /*!< GPIO_PORT NOT7: NOTP27 Position     */
-#define GPIO_PORT_NOT7_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP27_Pos)                     /*!< GPIO_PORT NOT7: NOTP27 Mask         */
-#define GPIO_PORT_NOT7_NOTP28_Pos                             28                                                        /*!< GPIO_PORT NOT7: NOTP28 Position     */
-#define GPIO_PORT_NOT7_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP28_Pos)                     /*!< GPIO_PORT NOT7: NOTP28 Mask         */
-#define GPIO_PORT_NOT7_NOTP29_Pos                             29                                                        /*!< GPIO_PORT NOT7: NOTP29 Position     */
-#define GPIO_PORT_NOT7_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP29_Pos)                     /*!< GPIO_PORT NOT7: NOTP29 Mask         */
-#define GPIO_PORT_NOT7_NOTP30_Pos                             30                                                        /*!< GPIO_PORT NOT7: NOTP30 Position     */
-#define GPIO_PORT_NOT7_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP30_Pos)                     /*!< GPIO_PORT NOT7: NOTP30 Mask         */
-#define GPIO_PORT_NOT7_NOTP31_Pos                             31                                                        /*!< GPIO_PORT NOT7: NOTP31 Position     */
-#define GPIO_PORT_NOT7_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP31_Pos)                     /*!< GPIO_PORT NOT7: NOTP31 Mask         */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                  SPI Position & Mask                                 -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------------  SPI_CR  ---------------------------------------------
-#define SPI_CR_BITENABLE_Pos                                  2                                                         /*!< SPI CR: BITENABLE Position          */
-#define SPI_CR_BITENABLE_Msk                                  (0x01UL << SPI_CR_BITENABLE_Pos)                          /*!< SPI CR: BITENABLE Mask              */
-#define SPI_CR_CPHA_Pos                                       3                                                         /*!< SPI CR: CPHA Position               */
-#define SPI_CR_CPHA_Msk                                       (0x01UL << SPI_CR_CPHA_Pos)                               /*!< SPI CR: CPHA Mask                   */
-#define SPI_CR_CPOL_Pos                                       4                                                         /*!< SPI CR: CPOL Position               */
-#define SPI_CR_CPOL_Msk                                       (0x01UL << SPI_CR_CPOL_Pos)                               /*!< SPI CR: CPOL Mask                   */
-#define SPI_CR_MSTR_Pos                                       5                                                         /*!< SPI CR: MSTR Position               */
-#define SPI_CR_MSTR_Msk                                       (0x01UL << SPI_CR_MSTR_Pos)                               /*!< SPI CR: MSTR Mask                   */
-#define SPI_CR_LSBF_Pos                                       6                                                         /*!< SPI CR: LSBF Position               */
-#define SPI_CR_LSBF_Msk                                       (0x01UL << SPI_CR_LSBF_Pos)                               /*!< SPI CR: LSBF Mask                   */
-#define SPI_CR_SPIE_Pos                                       7                                                         /*!< SPI CR: SPIE Position               */
-#define SPI_CR_SPIE_Msk                                       (0x01UL << SPI_CR_SPIE_Pos)                               /*!< SPI CR: SPIE Mask                   */
-#define SPI_CR_BITS_Pos                                       8                                                         /*!< SPI CR: BITS Position               */
-#define SPI_CR_BITS_Msk                                       (0x0fUL << SPI_CR_BITS_Pos)                               /*!< SPI CR: BITS Mask                   */
-
-// -----------------------------------------  SPI_SR  ---------------------------------------------
-#define SPI_SR_ABRT_Pos                                       3                                                         /*!< SPI SR: ABRT Position               */
-#define SPI_SR_ABRT_Msk                                       (0x01UL << SPI_SR_ABRT_Pos)                               /*!< SPI SR: ABRT Mask                   */
-#define SPI_SR_MODF_Pos                                       4                                                         /*!< SPI SR: MODF Position               */
-#define SPI_SR_MODF_Msk                                       (0x01UL << SPI_SR_MODF_Pos)                               /*!< SPI SR: MODF Mask                   */
-#define SPI_SR_ROVR_Pos                                       5                                                         /*!< SPI SR: ROVR Position               */
-#define SPI_SR_ROVR_Msk                                       (0x01UL << SPI_SR_ROVR_Pos)                               /*!< SPI SR: ROVR Mask                   */
-#define SPI_SR_WCOL_Pos                                       6                                                         /*!< SPI SR: WCOL Position               */
-#define SPI_SR_WCOL_Msk                                       (0x01UL << SPI_SR_WCOL_Pos)                               /*!< SPI SR: WCOL Mask                   */
-#define SPI_SR_SPIF_Pos                                       7                                                         /*!< SPI SR: SPIF Position               */
-#define SPI_SR_SPIF_Msk                                       (0x01UL << SPI_SR_SPIF_Pos)                               /*!< SPI SR: SPIF Mask                   */
-
-// -----------------------------------------  SPI_DR  ---------------------------------------------
-#define SPI_DR_DATALOW_Pos                                    0                                                         /*!< SPI DR: DATALOW Position            */
-#define SPI_DR_DATALOW_Msk                                    (0x000000ffUL << SPI_DR_DATALOW_Pos)                      /*!< SPI DR: DATALOW Mask                */
-#define SPI_DR_DATAHIGH_Pos                                   8                                                         /*!< SPI DR: DATAHIGH Position           */
-#define SPI_DR_DATAHIGH_Msk                                   (0x000000ffUL << SPI_DR_DATAHIGH_Pos)                     /*!< SPI DR: DATAHIGH Mask               */
-
-// -----------------------------------------  SPI_CCR  --------------------------------------------
-#define SPI_CCR_COUNTER_Pos                                   0                                                         /*!< SPI CCR: COUNTER Position           */
-#define SPI_CCR_COUNTER_Msk                                   (0x000000ffUL << SPI_CCR_COUNTER_Pos)                     /*!< SPI CCR: COUNTER Mask               */
-
-// -----------------------------------------  SPI_TCR  --------------------------------------------
-#define SPI_TCR_TEST_Pos                                      1                                                         /*!< SPI TCR: TEST Position              */
-#define SPI_TCR_TEST_Msk                                      (0x7fUL << SPI_TCR_TEST_Pos)                              /*!< SPI TCR: TEST Mask                  */
-
-// -----------------------------------------  SPI_TSR  --------------------------------------------
-#define SPI_TSR_ABRT_Pos                                      3                                                         /*!< SPI TSR: ABRT Position              */
-#define SPI_TSR_ABRT_Msk                                      (0x01UL << SPI_TSR_ABRT_Pos)                              /*!< SPI TSR: ABRT Mask                  */
-#define SPI_TSR_MODF_Pos                                      4                                                         /*!< SPI TSR: MODF Position              */
-#define SPI_TSR_MODF_Msk                                      (0x01UL << SPI_TSR_MODF_Pos)                              /*!< SPI TSR: MODF Mask                  */
-#define SPI_TSR_ROVR_Pos                                      5                                                         /*!< SPI TSR: ROVR Position              */
-#define SPI_TSR_ROVR_Msk                                      (0x01UL << SPI_TSR_ROVR_Pos)                              /*!< SPI TSR: ROVR Mask                  */
-#define SPI_TSR_WCOL_Pos                                      6                                                         /*!< SPI TSR: WCOL Position              */
-#define SPI_TSR_WCOL_Msk                                      (0x01UL << SPI_TSR_WCOL_Pos)                              /*!< SPI TSR: WCOL Mask                  */
-#define SPI_TSR_SPIF_Pos                                      7                                                         /*!< SPI TSR: SPIF Position              */
-#define SPI_TSR_SPIF_Msk                                      (0x01UL << SPI_TSR_SPIF_Pos)                              /*!< SPI TSR: SPIF Mask                  */
-
-// -----------------------------------------  SPI_INT  --------------------------------------------
-#define SPI_INT_SPIF_Pos                                      0                                                         /*!< SPI INT: SPIF Position              */
-#define SPI_INT_SPIF_Msk                                      (0x01UL << SPI_INT_SPIF_Pos)                              /*!< SPI INT: SPIF Mask                  */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 SGPIO Position & Mask                                -----
-// ------------------------------------------------------------------------------------------------
-
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG0  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG1  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG2  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG3  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG4  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG5  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG6  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG7  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG8  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG9  ---------------------------------------
-#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos                      0                                                         /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Mask  */
-#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos                       4                                                         /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos)               /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Mask   */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG10  --------------------------------------
-#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Mask */
-#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Mask  */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG11  --------------------------------------
-#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Mask */
-#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Mask  */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG12  --------------------------------------
-#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Mask */
-#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Mask  */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG13  --------------------------------------
-#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Mask */
-#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Mask  */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG14  --------------------------------------
-#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Mask */
-#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Mask  */
-
-// -----------------------------------  SGPIO_OUT_MUX_CFG15  --------------------------------------
-#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos                     0                                                         /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Position */
-#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos)             /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Mask */
-#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos                      4                                                         /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Position */
-#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos)              /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Mask  */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG0  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG1  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG2  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG3  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG4  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG5  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG6  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG7  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG8  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG9  --------------------------------------
-#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos               0                                                         /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos          1                                                         /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos        3                                                         /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos               5                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos)       /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos           7                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos)   /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos         9                                                         /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos                11                                                        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos)        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos                 12                                                        /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos)         /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG10  -------------------------------------
-#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG11  -------------------------------------
-#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG12  -------------------------------------
-#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG13  -------------------------------------
-#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG14  -------------------------------------
-#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SGPIO_MUX_CFG15  -------------------------------------
-#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos              0                                                         /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos)      /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos         1                                                         /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos       3                                                         /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos              5                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos)      /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos          7                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos)  /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos        9                                                         /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Position */
-#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Mask */
-#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos               11                                                        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Position */
-#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos)       /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Mask */
-#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos                12                                                        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Position */
-#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos)        /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG0  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG1  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG2  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG3  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG4  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG5  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG6  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG7  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG8  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG9  --------------------------------------
-#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos                   0                                                         /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos)           /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos             1                                                         /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos)     /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos                  2                                                         /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos                  3                                                         /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos)          /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos            4                                                         /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos                6                                                         /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos)        /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos                8                                                         /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos)        /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG10  -------------------------------------
-#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG11  -------------------------------------
-#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG12  -------------------------------------
-#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG13  -------------------------------------
-#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG14  -------------------------------------
-#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Mask */
-
-// ----------------------------------  SGPIO_SLICE_MUX_CFG15  -------------------------------------
-#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos                  0                                                         /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Position */
-#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos)          /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos            1                                                         /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos)    /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos                 2                                                         /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Position */
-#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos)         /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos                 3                                                         /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Position */
-#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos)         /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Mask */
-#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos           4                                                         /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Position */
-#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos)   /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos               6                                                         /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Position */
-#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos)       /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Mask */
-#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos               8                                                         /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Position */
-#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos)       /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Mask */
-
-// ---------------------------------------  SGPIO_REG0  -------------------------------------------
-#define SGPIO_REG0_REG_Pos                                    0                                                         /*!< SGPIO REG0: REG Position            */
-#define SGPIO_REG0_REG_Msk                                    (0xffffffffUL << SGPIO_REG0_REG_Pos)                      /*!< SGPIO REG0: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG1  -------------------------------------------
-#define SGPIO_REG1_REG_Pos                                    0                                                         /*!< SGPIO REG1: REG Position            */
-#define SGPIO_REG1_REG_Msk                                    (0xffffffffUL << SGPIO_REG1_REG_Pos)                      /*!< SGPIO REG1: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG2  -------------------------------------------
-#define SGPIO_REG2_REG_Pos                                    0                                                         /*!< SGPIO REG2: REG Position            */
-#define SGPIO_REG2_REG_Msk                                    (0xffffffffUL << SGPIO_REG2_REG_Pos)                      /*!< SGPIO REG2: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG3  -------------------------------------------
-#define SGPIO_REG3_REG_Pos                                    0                                                         /*!< SGPIO REG3: REG Position            */
-#define SGPIO_REG3_REG_Msk                                    (0xffffffffUL << SGPIO_REG3_REG_Pos)                      /*!< SGPIO REG3: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG4  -------------------------------------------
-#define SGPIO_REG4_REG_Pos                                    0                                                         /*!< SGPIO REG4: REG Position            */
-#define SGPIO_REG4_REG_Msk                                    (0xffffffffUL << SGPIO_REG4_REG_Pos)                      /*!< SGPIO REG4: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG5  -------------------------------------------
-#define SGPIO_REG5_REG_Pos                                    0                                                         /*!< SGPIO REG5: REG Position            */
-#define SGPIO_REG5_REG_Msk                                    (0xffffffffUL << SGPIO_REG5_REG_Pos)                      /*!< SGPIO REG5: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG6  -------------------------------------------
-#define SGPIO_REG6_REG_Pos                                    0                                                         /*!< SGPIO REG6: REG Position            */
-#define SGPIO_REG6_REG_Msk                                    (0xffffffffUL << SGPIO_REG6_REG_Pos)                      /*!< SGPIO REG6: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG7  -------------------------------------------
-#define SGPIO_REG7_REG_Pos                                    0                                                         /*!< SGPIO REG7: REG Position            */
-#define SGPIO_REG7_REG_Msk                                    (0xffffffffUL << SGPIO_REG7_REG_Pos)                      /*!< SGPIO REG7: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG8  -------------------------------------------
-#define SGPIO_REG8_REG_Pos                                    0                                                         /*!< SGPIO REG8: REG Position            */
-#define SGPIO_REG8_REG_Msk                                    (0xffffffffUL << SGPIO_REG8_REG_Pos)                      /*!< SGPIO REG8: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG9  -------------------------------------------
-#define SGPIO_REG9_REG_Pos                                    0                                                         /*!< SGPIO REG9: REG Position            */
-#define SGPIO_REG9_REG_Msk                                    (0xffffffffUL << SGPIO_REG9_REG_Pos)                      /*!< SGPIO REG9: REG Mask                */
-
-// ---------------------------------------  SGPIO_REG10  ------------------------------------------
-#define SGPIO_REG10_REG_Pos                                   0                                                         /*!< SGPIO REG10: REG Position           */
-#define SGPIO_REG10_REG_Msk                                   (0xffffffffUL << SGPIO_REG10_REG_Pos)                     /*!< SGPIO REG10: REG Mask               */
-
-// ---------------------------------------  SGPIO_REG11  ------------------------------------------
-#define SGPIO_REG11_REG_Pos                                   0                                                         /*!< SGPIO REG11: REG Position           */
-#define SGPIO_REG11_REG_Msk                                   (0xffffffffUL << SGPIO_REG11_REG_Pos)                     /*!< SGPIO REG11: REG Mask               */
-
-// ---------------------------------------  SGPIO_REG12  ------------------------------------------
-#define SGPIO_REG12_REG_Pos                                   0                                                         /*!< SGPIO REG12: REG Position           */
-#define SGPIO_REG12_REG_Msk                                   (0xffffffffUL << SGPIO_REG12_REG_Pos)                     /*!< SGPIO REG12: REG Mask               */
-
-// ---------------------------------------  SGPIO_REG13  ------------------------------------------
-#define SGPIO_REG13_REG_Pos                                   0                                                         /*!< SGPIO REG13: REG Position           */
-#define SGPIO_REG13_REG_Msk                                   (0xffffffffUL << SGPIO_REG13_REG_Pos)                     /*!< SGPIO REG13: REG Mask               */
-
-// ---------------------------------------  SGPIO_REG14  ------------------------------------------
-#define SGPIO_REG14_REG_Pos                                   0                                                         /*!< SGPIO REG14: REG Position           */
-#define SGPIO_REG14_REG_Msk                                   (0xffffffffUL << SGPIO_REG14_REG_Pos)                     /*!< SGPIO REG14: REG Mask               */
-
-// ---------------------------------------  SGPIO_REG15  ------------------------------------------
-#define SGPIO_REG15_REG_Pos                                   0                                                         /*!< SGPIO REG15: REG Position           */
-#define SGPIO_REG15_REG_Msk                                   (0xffffffffUL << SGPIO_REG15_REG_Pos)                     /*!< SGPIO REG15: REG Mask               */
-
-// --------------------------------------  SGPIO_REG_SS0  -----------------------------------------
-#define SGPIO_REG_SS0_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS0: REG_SS Position      */
-#define SGPIO_REG_SS0_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS0_REG_SS_Pos)                /*!< SGPIO REG_SS0: REG_SS Mask          */
-
-// --------------------------------------  SGPIO_REG_SS1  -----------------------------------------
-#define SGPIO_REG_SS1_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS1: REG_SS Position      */
-#define SGPIO_REG_SS1_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS1_REG_SS_Pos)                /*!< SGPIO REG_SS1: REG_SS Mask          */
-
-// --------------------------------------  SGPIO_REG_SS2  -----------------------------------------
-#define SGPIO_REG_SS2_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS2: REG_SS Position      */
-#define SGPIO_REG_SS2_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS2_REG_SS_Pos)                /*!< SGPIO REG_SS2: REG_SS Mask          */
-
-// --------------------------------------  SGPIO_REG_SS3  -----------------------------------------
-#define SGPIO_REG_SS3_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS3: REG_SS Position      */
-#define SGPIO_REG_SS3_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS3_REG_SS_Pos)                /*!< SGPIO REG_SS3: REG_SS Mask          */
-
-// --------------------------------------  SGPIO_REG_SS4  -----------------------------------------
-#define SGPIO_REG_SS4_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS4: REG_SS Position      */
-#define SGPIO_REG_SS4_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS4_REG_SS_Pos)                /*!< SGPIO REG_SS4: REG_SS Mask          */
-
-// --------------------------------------  SGPIO_REG_SS5  -----------------------------------------
-#define SGPIO_REG_SS5_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS5: REG_SS Position      */
-#define SGPIO_REG_SS5_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS5_REG_SS_Pos)                /*!< SGPIO REG_SS5: REG_SS Mask          */
-
-// --------------------------------------  SGPIO_REG_SS6  -----------------------------------------
-#define SGPIO_REG_SS6_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS6: REG_SS Position      */
-#define SGPIO_REG_SS6_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS6_REG_SS_Pos)                /*!< SGPIO REG_SS6: REG_SS Mask          */
-
-// --------------------------------------  SGPIO_REG_SS7  -----------------------------------------
-#define SGPIO_REG_SS7_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS7: REG_SS Position      */
-#define SGPIO_REG_SS7_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS7_REG_SS_Pos)                /*!< SGPIO REG_SS7: REG_SS Mask          */
-
-// --------------------------------------  SGPIO_REG_SS8  -----------------------------------------
-#define SGPIO_REG_SS8_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS8: REG_SS Position      */
-#define SGPIO_REG_SS8_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS8_REG_SS_Pos)                /*!< SGPIO REG_SS8: REG_SS Mask          */
-
-// --------------------------------------  SGPIO_REG_SS9  -----------------------------------------
-#define SGPIO_REG_SS9_REG_SS_Pos                              0                                                         /*!< SGPIO REG_SS9: REG_SS Position      */
-#define SGPIO_REG_SS9_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS9_REG_SS_Pos)                /*!< SGPIO REG_SS9: REG_SS Mask          */
-
-// -------------------------------------  SGPIO_REG_SS10  -----------------------------------------
-#define SGPIO_REG_SS10_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS10: REG_SS Position     */
-#define SGPIO_REG_SS10_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS10_REG_SS_Pos)               /*!< SGPIO REG_SS10: REG_SS Mask         */
-
-// -------------------------------------  SGPIO_REG_SS11  -----------------------------------------
-#define SGPIO_REG_SS11_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS11: REG_SS Position     */
-#define SGPIO_REG_SS11_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS11_REG_SS_Pos)               /*!< SGPIO REG_SS11: REG_SS Mask         */
-
-// -------------------------------------  SGPIO_REG_SS12  -----------------------------------------
-#define SGPIO_REG_SS12_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS12: REG_SS Position     */
-#define SGPIO_REG_SS12_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS12_REG_SS_Pos)               /*!< SGPIO REG_SS12: REG_SS Mask         */
-
-// -------------------------------------  SGPIO_REG_SS13  -----------------------------------------
-#define SGPIO_REG_SS13_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS13: REG_SS Position     */
-#define SGPIO_REG_SS13_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS13_REG_SS_Pos)               /*!< SGPIO REG_SS13: REG_SS Mask         */
-
-// -------------------------------------  SGPIO_REG_SS14  -----------------------------------------
-#define SGPIO_REG_SS14_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS14: REG_SS Position     */
-#define SGPIO_REG_SS14_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS14_REG_SS_Pos)               /*!< SGPIO REG_SS14: REG_SS Mask         */
-
-// -------------------------------------  SGPIO_REG_SS15  -----------------------------------------
-#define SGPIO_REG_SS15_REG_SS_Pos                             0                                                         /*!< SGPIO REG_SS15: REG_SS Position     */
-#define SGPIO_REG_SS15_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS15_REG_SS_Pos)               /*!< SGPIO REG_SS15: REG_SS Mask         */
-
-// --------------------------------------  SGPIO_PRESET0  -----------------------------------------
-#define SGPIO_PRESET0_PRESET_Pos                              0                                                         /*!< SGPIO PRESET0: PRESET Position      */
-#define SGPIO_PRESET0_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET0_PRESET_Pos)                /*!< SGPIO PRESET0: PRESET Mask          */
-
-// --------------------------------------  SGPIO_PRESET1  -----------------------------------------
-#define SGPIO_PRESET1_PRESET_Pos                              0                                                         /*!< SGPIO PRESET1: PRESET Position      */
-#define SGPIO_PRESET1_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET1_PRESET_Pos)                /*!< SGPIO PRESET1: PRESET Mask          */
-
-// --------------------------------------  SGPIO_PRESET2  -----------------------------------------
-#define SGPIO_PRESET2_PRESET_Pos                              0                                                         /*!< SGPIO PRESET2: PRESET Position      */
-#define SGPIO_PRESET2_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET2_PRESET_Pos)                /*!< SGPIO PRESET2: PRESET Mask          */
-
-// --------------------------------------  SGPIO_PRESET3  -----------------------------------------
-#define SGPIO_PRESET3_PRESET_Pos                              0                                                         /*!< SGPIO PRESET3: PRESET Position      */
-#define SGPIO_PRESET3_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET3_PRESET_Pos)                /*!< SGPIO PRESET3: PRESET Mask          */
-
-// --------------------------------------  SGPIO_PRESET4  -----------------------------------------
-#define SGPIO_PRESET4_PRESET_Pos                              0                                                         /*!< SGPIO PRESET4: PRESET Position      */
-#define SGPIO_PRESET4_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET4_PRESET_Pos)                /*!< SGPIO PRESET4: PRESET Mask          */
-
-// --------------------------------------  SGPIO_PRESET5  -----------------------------------------
-#define SGPIO_PRESET5_PRESET_Pos                              0                                                         /*!< SGPIO PRESET5: PRESET Position      */
-#define SGPIO_PRESET5_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET5_PRESET_Pos)                /*!< SGPIO PRESET5: PRESET Mask          */
-
-// --------------------------------------  SGPIO_PRESET6  -----------------------------------------
-#define SGPIO_PRESET6_PRESET_Pos                              0                                                         /*!< SGPIO PRESET6: PRESET Position      */
-#define SGPIO_PRESET6_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET6_PRESET_Pos)                /*!< SGPIO PRESET6: PRESET Mask          */
-
-// --------------------------------------  SGPIO_PRESET7  -----------------------------------------
-#define SGPIO_PRESET7_PRESET_Pos                              0                                                         /*!< SGPIO PRESET7: PRESET Position      */
-#define SGPIO_PRESET7_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET7_PRESET_Pos)                /*!< SGPIO PRESET7: PRESET Mask          */
-
-// --------------------------------------  SGPIO_PRESET8  -----------------------------------------
-#define SGPIO_PRESET8_PRESET_Pos                              0                                                         /*!< SGPIO PRESET8: PRESET Position      */
-#define SGPIO_PRESET8_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET8_PRESET_Pos)                /*!< SGPIO PRESET8: PRESET Mask          */
-
-// --------------------------------------  SGPIO_PRESET9  -----------------------------------------
-#define SGPIO_PRESET9_PRESET_Pos                              0                                                         /*!< SGPIO PRESET9: PRESET Position      */
-#define SGPIO_PRESET9_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET9_PRESET_Pos)                /*!< SGPIO PRESET9: PRESET Mask          */
-
-// -------------------------------------  SGPIO_PRESET10  -----------------------------------------
-#define SGPIO_PRESET10_PRESET_Pos                             0                                                         /*!< SGPIO PRESET10: PRESET Position     */
-#define SGPIO_PRESET10_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET10_PRESET_Pos)               /*!< SGPIO PRESET10: PRESET Mask         */
-
-// -------------------------------------  SGPIO_PRESET11  -----------------------------------------
-#define SGPIO_PRESET11_PRESET_Pos                             0                                                         /*!< SGPIO PRESET11: PRESET Position     */
-#define SGPIO_PRESET11_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET11_PRESET_Pos)               /*!< SGPIO PRESET11: PRESET Mask         */
-
-// -------------------------------------  SGPIO_PRESET12  -----------------------------------------
-#define SGPIO_PRESET12_PRESET_Pos                             0                                                         /*!< SGPIO PRESET12: PRESET Position     */
-#define SGPIO_PRESET12_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET12_PRESET_Pos)               /*!< SGPIO PRESET12: PRESET Mask         */
-
-// -------------------------------------  SGPIO_PRESET13  -----------------------------------------
-#define SGPIO_PRESET13_PRESET_Pos                             0                                                         /*!< SGPIO PRESET13: PRESET Position     */
-#define SGPIO_PRESET13_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET13_PRESET_Pos)               /*!< SGPIO PRESET13: PRESET Mask         */
-
-// -------------------------------------  SGPIO_PRESET14  -----------------------------------------
-#define SGPIO_PRESET14_PRESET_Pos                             0                                                         /*!< SGPIO PRESET14: PRESET Position     */
-#define SGPIO_PRESET14_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET14_PRESET_Pos)               /*!< SGPIO PRESET14: PRESET Mask         */
-
-// -------------------------------------  SGPIO_PRESET15  -----------------------------------------
-#define SGPIO_PRESET15_PRESET_Pos                             0                                                         /*!< SGPIO PRESET15: PRESET Position     */
-#define SGPIO_PRESET15_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET15_PRESET_Pos)               /*!< SGPIO PRESET15: PRESET Mask         */
-
-// --------------------------------------  SGPIO_COUNT0  ------------------------------------------
-#define SGPIO_COUNT0_COUNT_Pos                                0                                                         /*!< SGPIO COUNT0: COUNT Position        */
-#define SGPIO_COUNT0_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT0_COUNT_Pos)                  /*!< SGPIO COUNT0: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT1  ------------------------------------------
-#define SGPIO_COUNT1_COUNT_Pos                                0                                                         /*!< SGPIO COUNT1: COUNT Position        */
-#define SGPIO_COUNT1_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT1_COUNT_Pos)                  /*!< SGPIO COUNT1: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT2  ------------------------------------------
-#define SGPIO_COUNT2_COUNT_Pos                                0                                                         /*!< SGPIO COUNT2: COUNT Position        */
-#define SGPIO_COUNT2_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT2_COUNT_Pos)                  /*!< SGPIO COUNT2: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT3  ------------------------------------------
-#define SGPIO_COUNT3_COUNT_Pos                                0                                                         /*!< SGPIO COUNT3: COUNT Position        */
-#define SGPIO_COUNT3_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT3_COUNT_Pos)                  /*!< SGPIO COUNT3: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT4  ------------------------------------------
-#define SGPIO_COUNT4_COUNT_Pos                                0                                                         /*!< SGPIO COUNT4: COUNT Position        */
-#define SGPIO_COUNT4_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT4_COUNT_Pos)                  /*!< SGPIO COUNT4: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT5  ------------------------------------------
-#define SGPIO_COUNT5_COUNT_Pos                                0                                                         /*!< SGPIO COUNT5: COUNT Position        */
-#define SGPIO_COUNT5_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT5_COUNT_Pos)                  /*!< SGPIO COUNT5: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT6  ------------------------------------------
-#define SGPIO_COUNT6_COUNT_Pos                                0                                                         /*!< SGPIO COUNT6: COUNT Position        */
-#define SGPIO_COUNT6_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT6_COUNT_Pos)                  /*!< SGPIO COUNT6: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT7  ------------------------------------------
-#define SGPIO_COUNT7_COUNT_Pos                                0                                                         /*!< SGPIO COUNT7: COUNT Position        */
-#define SGPIO_COUNT7_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT7_COUNT_Pos)                  /*!< SGPIO COUNT7: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT8  ------------------------------------------
-#define SGPIO_COUNT8_COUNT_Pos                                0                                                         /*!< SGPIO COUNT8: COUNT Position        */
-#define SGPIO_COUNT8_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT8_COUNT_Pos)                  /*!< SGPIO COUNT8: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT9  ------------------------------------------
-#define SGPIO_COUNT9_COUNT_Pos                                0                                                         /*!< SGPIO COUNT9: COUNT Position        */
-#define SGPIO_COUNT9_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT9_COUNT_Pos)                  /*!< SGPIO COUNT9: COUNT Mask            */
-
-// --------------------------------------  SGPIO_COUNT10  -----------------------------------------
-#define SGPIO_COUNT10_COUNT_Pos                               0                                                         /*!< SGPIO COUNT10: COUNT Position       */
-#define SGPIO_COUNT10_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT10_COUNT_Pos)                 /*!< SGPIO COUNT10: COUNT Mask           */
-
-// --------------------------------------  SGPIO_COUNT11  -----------------------------------------
-#define SGPIO_COUNT11_COUNT_Pos                               0                                                         /*!< SGPIO COUNT11: COUNT Position       */
-#define SGPIO_COUNT11_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT11_COUNT_Pos)                 /*!< SGPIO COUNT11: COUNT Mask           */
-
-// --------------------------------------  SGPIO_COUNT12  -----------------------------------------
-#define SGPIO_COUNT12_COUNT_Pos                               0                                                         /*!< SGPIO COUNT12: COUNT Position       */
-#define SGPIO_COUNT12_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT12_COUNT_Pos)                 /*!< SGPIO COUNT12: COUNT Mask           */
-
-// --------------------------------------  SGPIO_COUNT13  -----------------------------------------
-#define SGPIO_COUNT13_COUNT_Pos                               0                                                         /*!< SGPIO COUNT13: COUNT Position       */
-#define SGPIO_COUNT13_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT13_COUNT_Pos)                 /*!< SGPIO COUNT13: COUNT Mask           */
-
-// --------------------------------------  SGPIO_COUNT14  -----------------------------------------
-#define SGPIO_COUNT14_COUNT_Pos                               0                                                         /*!< SGPIO COUNT14: COUNT Position       */
-#define SGPIO_COUNT14_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT14_COUNT_Pos)                 /*!< SGPIO COUNT14: COUNT Mask           */
-
-// --------------------------------------  SGPIO_COUNT15  -----------------------------------------
-#define SGPIO_COUNT15_COUNT_Pos                               0                                                         /*!< SGPIO COUNT15: COUNT Position       */
-#define SGPIO_COUNT15_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT15_COUNT_Pos)                 /*!< SGPIO COUNT15: COUNT Mask           */
-
-// ---------------------------------------  SGPIO_POS0  -------------------------------------------
-#define SGPIO_POS0_POS_Pos                                    0                                                         /*!< SGPIO POS0: POS Position            */
-#define SGPIO_POS0_POS_Msk                                    (0x000000ffUL << SGPIO_POS0_POS_Pos)                      /*!< SGPIO POS0: POS Mask                */
-#define SGPIO_POS0_POS_RESET_Pos                              8                                                         /*!< SGPIO POS0: POS_RESET Position      */
-#define SGPIO_POS0_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS0_POS_RESET_Pos)                /*!< SGPIO POS0: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS1  -------------------------------------------
-#define SGPIO_POS1_POS_Pos                                    0                                                         /*!< SGPIO POS1: POS Position            */
-#define SGPIO_POS1_POS_Msk                                    (0x000000ffUL << SGPIO_POS1_POS_Pos)                      /*!< SGPIO POS1: POS Mask                */
-#define SGPIO_POS1_POS_RESET_Pos                              8                                                         /*!< SGPIO POS1: POS_RESET Position      */
-#define SGPIO_POS1_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS1_POS_RESET_Pos)                /*!< SGPIO POS1: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS2  -------------------------------------------
-#define SGPIO_POS2_POS_Pos                                    0                                                         /*!< SGPIO POS2: POS Position            */
-#define SGPIO_POS2_POS_Msk                                    (0x000000ffUL << SGPIO_POS2_POS_Pos)                      /*!< SGPIO POS2: POS Mask                */
-#define SGPIO_POS2_POS_RESET_Pos                              8                                                         /*!< SGPIO POS2: POS_RESET Position      */
-#define SGPIO_POS2_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS2_POS_RESET_Pos)                /*!< SGPIO POS2: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS3  -------------------------------------------
-#define SGPIO_POS3_POS_Pos                                    0                                                         /*!< SGPIO POS3: POS Position            */
-#define SGPIO_POS3_POS_Msk                                    (0x000000ffUL << SGPIO_POS3_POS_Pos)                      /*!< SGPIO POS3: POS Mask                */
-#define SGPIO_POS3_POS_RESET_Pos                              8                                                         /*!< SGPIO POS3: POS_RESET Position      */
-#define SGPIO_POS3_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS3_POS_RESET_Pos)                /*!< SGPIO POS3: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS4  -------------------------------------------
-#define SGPIO_POS4_POS_Pos                                    0                                                         /*!< SGPIO POS4: POS Position            */
-#define SGPIO_POS4_POS_Msk                                    (0x000000ffUL << SGPIO_POS4_POS_Pos)                      /*!< SGPIO POS4: POS Mask                */
-#define SGPIO_POS4_POS_RESET_Pos                              8                                                         /*!< SGPIO POS4: POS_RESET Position      */
-#define SGPIO_POS4_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS4_POS_RESET_Pos)                /*!< SGPIO POS4: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS5  -------------------------------------------
-#define SGPIO_POS5_POS_Pos                                    0                                                         /*!< SGPIO POS5: POS Position            */
-#define SGPIO_POS5_POS_Msk                                    (0x000000ffUL << SGPIO_POS5_POS_Pos)                      /*!< SGPIO POS5: POS Mask                */
-#define SGPIO_POS5_POS_RESET_Pos                              8                                                         /*!< SGPIO POS5: POS_RESET Position      */
-#define SGPIO_POS5_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS5_POS_RESET_Pos)                /*!< SGPIO POS5: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS6  -------------------------------------------
-#define SGPIO_POS6_POS_Pos                                    0                                                         /*!< SGPIO POS6: POS Position            */
-#define SGPIO_POS6_POS_Msk                                    (0x000000ffUL << SGPIO_POS6_POS_Pos)                      /*!< SGPIO POS6: POS Mask                */
-#define SGPIO_POS6_POS_RESET_Pos                              8                                                         /*!< SGPIO POS6: POS_RESET Position      */
-#define SGPIO_POS6_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS6_POS_RESET_Pos)                /*!< SGPIO POS6: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS7  -------------------------------------------
-#define SGPIO_POS7_POS_Pos                                    0                                                         /*!< SGPIO POS7: POS Position            */
-#define SGPIO_POS7_POS_Msk                                    (0x000000ffUL << SGPIO_POS7_POS_Pos)                      /*!< SGPIO POS7: POS Mask                */
-#define SGPIO_POS7_POS_RESET_Pos                              8                                                         /*!< SGPIO POS7: POS_RESET Position      */
-#define SGPIO_POS7_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS7_POS_RESET_Pos)                /*!< SGPIO POS7: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS8  -------------------------------------------
-#define SGPIO_POS8_POS_Pos                                    0                                                         /*!< SGPIO POS8: POS Position            */
-#define SGPIO_POS8_POS_Msk                                    (0x000000ffUL << SGPIO_POS8_POS_Pos)                      /*!< SGPIO POS8: POS Mask                */
-#define SGPIO_POS8_POS_RESET_Pos                              8                                                         /*!< SGPIO POS8: POS_RESET Position      */
-#define SGPIO_POS8_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS8_POS_RESET_Pos)                /*!< SGPIO POS8: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS9  -------------------------------------------
-#define SGPIO_POS9_POS_Pos                                    0                                                         /*!< SGPIO POS9: POS Position            */
-#define SGPIO_POS9_POS_Msk                                    (0x000000ffUL << SGPIO_POS9_POS_Pos)                      /*!< SGPIO POS9: POS Mask                */
-#define SGPIO_POS9_POS_RESET_Pos                              8                                                         /*!< SGPIO POS9: POS_RESET Position      */
-#define SGPIO_POS9_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS9_POS_RESET_Pos)                /*!< SGPIO POS9: POS_RESET Mask          */
-
-// ---------------------------------------  SGPIO_POS10  ------------------------------------------
-#define SGPIO_POS10_POS_Pos                                   0                                                         /*!< SGPIO POS10: POS Position           */
-#define SGPIO_POS10_POS_Msk                                   (0x000000ffUL << SGPIO_POS10_POS_Pos)                     /*!< SGPIO POS10: POS Mask               */
-#define SGPIO_POS10_POS_RESET_Pos                             8                                                         /*!< SGPIO POS10: POS_RESET Position     */
-#define SGPIO_POS10_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS10_POS_RESET_Pos)               /*!< SGPIO POS10: POS_RESET Mask         */
-
-// ---------------------------------------  SGPIO_POS11  ------------------------------------------
-#define SGPIO_POS11_POS_Pos                                   0                                                         /*!< SGPIO POS11: POS Position           */
-#define SGPIO_POS11_POS_Msk                                   (0x000000ffUL << SGPIO_POS11_POS_Pos)                     /*!< SGPIO POS11: POS Mask               */
-#define SGPIO_POS11_POS_RESET_Pos                             8                                                         /*!< SGPIO POS11: POS_RESET Position     */
-#define SGPIO_POS11_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS11_POS_RESET_Pos)               /*!< SGPIO POS11: POS_RESET Mask         */
-
-// ---------------------------------------  SGPIO_POS12  ------------------------------------------
-#define SGPIO_POS12_POS_Pos                                   0                                                         /*!< SGPIO POS12: POS Position           */
-#define SGPIO_POS12_POS_Msk                                   (0x000000ffUL << SGPIO_POS12_POS_Pos)                     /*!< SGPIO POS12: POS Mask               */
-#define SGPIO_POS12_POS_RESET_Pos                             8                                                         /*!< SGPIO POS12: POS_RESET Position     */
-#define SGPIO_POS12_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS12_POS_RESET_Pos)               /*!< SGPIO POS12: POS_RESET Mask         */
-
-// ---------------------------------------  SGPIO_POS13  ------------------------------------------
-#define SGPIO_POS13_POS_Pos                                   0                                                         /*!< SGPIO POS13: POS Position           */
-#define SGPIO_POS13_POS_Msk                                   (0x000000ffUL << SGPIO_POS13_POS_Pos)                     /*!< SGPIO POS13: POS Mask               */
-#define SGPIO_POS13_POS_RESET_Pos                             8                                                         /*!< SGPIO POS13: POS_RESET Position     */
-#define SGPIO_POS13_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS13_POS_RESET_Pos)               /*!< SGPIO POS13: POS_RESET Mask         */
-
-// ---------------------------------------  SGPIO_POS14  ------------------------------------------
-#define SGPIO_POS14_POS_Pos                                   0                                                         /*!< SGPIO POS14: POS Position           */
-#define SGPIO_POS14_POS_Msk                                   (0x000000ffUL << SGPIO_POS14_POS_Pos)                     /*!< SGPIO POS14: POS Mask               */
-#define SGPIO_POS14_POS_RESET_Pos                             8                                                         /*!< SGPIO POS14: POS_RESET Position     */
-#define SGPIO_POS14_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS14_POS_RESET_Pos)               /*!< SGPIO POS14: POS_RESET Mask         */
-
-// ---------------------------------------  SGPIO_POS15  ------------------------------------------
-#define SGPIO_POS15_POS_Pos                                   0                                                         /*!< SGPIO POS15: POS Position           */
-#define SGPIO_POS15_POS_Msk                                   (0x000000ffUL << SGPIO_POS15_POS_Pos)                     /*!< SGPIO POS15: POS Mask               */
-#define SGPIO_POS15_POS_RESET_Pos                             8                                                         /*!< SGPIO POS15: POS_RESET Position     */
-#define SGPIO_POS15_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS15_POS_RESET_Pos)               /*!< SGPIO POS15: POS_RESET Mask         */
-
-// --------------------------------------  SGPIO_MASK_A  ------------------------------------------
-#define SGPIO_MASK_A_MASK_A0_Pos                              0                                                         /*!< SGPIO MASK_A: MASK_A0 Position      */
-#define SGPIO_MASK_A_MASK_A0_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A0_Pos)                      /*!< SGPIO MASK_A: MASK_A0 Mask          */
-#define SGPIO_MASK_A_MASK_A1_Pos                              1                                                         /*!< SGPIO MASK_A: MASK_A1 Position      */
-#define SGPIO_MASK_A_MASK_A1_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A1_Pos)                      /*!< SGPIO MASK_A: MASK_A1 Mask          */
-#define SGPIO_MASK_A_MASK_A2_Pos                              2                                                         /*!< SGPIO MASK_A: MASK_A2 Position      */
-#define SGPIO_MASK_A_MASK_A2_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A2_Pos)                      /*!< SGPIO MASK_A: MASK_A2 Mask          */
-#define SGPIO_MASK_A_MASK_A3_Pos                              3                                                         /*!< SGPIO MASK_A: MASK_A3 Position      */
-#define SGPIO_MASK_A_MASK_A3_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A3_Pos)                      /*!< SGPIO MASK_A: MASK_A3 Mask          */
-#define SGPIO_MASK_A_MASK_A4_Pos                              4                                                         /*!< SGPIO MASK_A: MASK_A4 Position      */
-#define SGPIO_MASK_A_MASK_A4_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A4_Pos)                      /*!< SGPIO MASK_A: MASK_A4 Mask          */
-#define SGPIO_MASK_A_MASK_A5_Pos                              5                                                         /*!< SGPIO MASK_A: MASK_A5 Position      */
-#define SGPIO_MASK_A_MASK_A5_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A5_Pos)                      /*!< SGPIO MASK_A: MASK_A5 Mask          */
-#define SGPIO_MASK_A_MASK_A6_Pos                              6                                                         /*!< SGPIO MASK_A: MASK_A6 Position      */
-#define SGPIO_MASK_A_MASK_A6_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A6_Pos)                      /*!< SGPIO MASK_A: MASK_A6 Mask          */
-#define SGPIO_MASK_A_MASK_A7_Pos                              7                                                         /*!< SGPIO MASK_A: MASK_A7 Position      */
-#define SGPIO_MASK_A_MASK_A7_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A7_Pos)                      /*!< SGPIO MASK_A: MASK_A7 Mask          */
-#define SGPIO_MASK_A_MASK_A8_Pos                              8                                                         /*!< SGPIO MASK_A: MASK_A8 Position      */
-#define SGPIO_MASK_A_MASK_A8_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A8_Pos)                      /*!< SGPIO MASK_A: MASK_A8 Mask          */
-#define SGPIO_MASK_A_MASK_A9_Pos                              9                                                         /*!< SGPIO MASK_A: MASK_A9 Position      */
-#define SGPIO_MASK_A_MASK_A9_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A9_Pos)                      /*!< SGPIO MASK_A: MASK_A9 Mask          */
-#define SGPIO_MASK_A_MASK_A10_Pos                             10                                                        /*!< SGPIO MASK_A: MASK_A10 Position     */
-#define SGPIO_MASK_A_MASK_A10_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A10_Pos)                     /*!< SGPIO MASK_A: MASK_A10 Mask         */
-#define SGPIO_MASK_A_MASK_A11_Pos                             11                                                        /*!< SGPIO MASK_A: MASK_A11 Position     */
-#define SGPIO_MASK_A_MASK_A11_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A11_Pos)                     /*!< SGPIO MASK_A: MASK_A11 Mask         */
-#define SGPIO_MASK_A_MASK_A12_Pos                             12                                                        /*!< SGPIO MASK_A: MASK_A12 Position     */
-#define SGPIO_MASK_A_MASK_A12_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A12_Pos)                     /*!< SGPIO MASK_A: MASK_A12 Mask         */
-#define SGPIO_MASK_A_MASK_A13_Pos                             13                                                        /*!< SGPIO MASK_A: MASK_A13 Position     */
-#define SGPIO_MASK_A_MASK_A13_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A13_Pos)                     /*!< SGPIO MASK_A: MASK_A13 Mask         */
-#define SGPIO_MASK_A_MASK_A14_Pos                             14                                                        /*!< SGPIO MASK_A: MASK_A14 Position     */
-#define SGPIO_MASK_A_MASK_A14_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A14_Pos)                     /*!< SGPIO MASK_A: MASK_A14 Mask         */
-#define SGPIO_MASK_A_MASK_A15_Pos                             15                                                        /*!< SGPIO MASK_A: MASK_A15 Position     */
-#define SGPIO_MASK_A_MASK_A15_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A15_Pos)                     /*!< SGPIO MASK_A: MASK_A15 Mask         */
-#define SGPIO_MASK_A_MASK_A16_Pos                             16                                                        /*!< SGPIO MASK_A: MASK_A16 Position     */
-#define SGPIO_MASK_A_MASK_A16_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A16_Pos)                     /*!< SGPIO MASK_A: MASK_A16 Mask         */
-#define SGPIO_MASK_A_MASK_A17_Pos                             17                                                        /*!< SGPIO MASK_A: MASK_A17 Position     */
-#define SGPIO_MASK_A_MASK_A17_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A17_Pos)                     /*!< SGPIO MASK_A: MASK_A17 Mask         */
-#define SGPIO_MASK_A_MASK_A18_Pos                             18                                                        /*!< SGPIO MASK_A: MASK_A18 Position     */
-#define SGPIO_MASK_A_MASK_A18_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A18_Pos)                     /*!< SGPIO MASK_A: MASK_A18 Mask         */
-#define SGPIO_MASK_A_MASK_A19_Pos                             19                                                        /*!< SGPIO MASK_A: MASK_A19 Position     */
-#define SGPIO_MASK_A_MASK_A19_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A19_Pos)                     /*!< SGPIO MASK_A: MASK_A19 Mask         */
-#define SGPIO_MASK_A_MASK_A20_Pos                             20                                                        /*!< SGPIO MASK_A: MASK_A20 Position     */
-#define SGPIO_MASK_A_MASK_A20_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A20_Pos)                     /*!< SGPIO MASK_A: MASK_A20 Mask         */
-#define SGPIO_MASK_A_MASK_A21_Pos                             21                                                        /*!< SGPIO MASK_A: MASK_A21 Position     */
-#define SGPIO_MASK_A_MASK_A21_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A21_Pos)                     /*!< SGPIO MASK_A: MASK_A21 Mask         */
-#define SGPIO_MASK_A_MASK_A22_Pos                             22                                                        /*!< SGPIO MASK_A: MASK_A22 Position     */
-#define SGPIO_MASK_A_MASK_A22_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A22_Pos)                     /*!< SGPIO MASK_A: MASK_A22 Mask         */
-#define SGPIO_MASK_A_MASK_A23_Pos                             23                                                        /*!< SGPIO MASK_A: MASK_A23 Position     */
-#define SGPIO_MASK_A_MASK_A23_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A23_Pos)                     /*!< SGPIO MASK_A: MASK_A23 Mask         */
-#define SGPIO_MASK_A_MASK_A24_Pos                             24                                                        /*!< SGPIO MASK_A: MASK_A24 Position     */
-#define SGPIO_MASK_A_MASK_A24_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A24_Pos)                     /*!< SGPIO MASK_A: MASK_A24 Mask         */
-#define SGPIO_MASK_A_MASK_A25_Pos                             25                                                        /*!< SGPIO MASK_A: MASK_A25 Position     */
-#define SGPIO_MASK_A_MASK_A25_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A25_Pos)                     /*!< SGPIO MASK_A: MASK_A25 Mask         */
-#define SGPIO_MASK_A_MASK_A26_Pos                             26                                                        /*!< SGPIO MASK_A: MASK_A26 Position     */
-#define SGPIO_MASK_A_MASK_A26_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A26_Pos)                     /*!< SGPIO MASK_A: MASK_A26 Mask         */
-#define SGPIO_MASK_A_MASK_A27_Pos                             27                                                        /*!< SGPIO MASK_A: MASK_A27 Position     */
-#define SGPIO_MASK_A_MASK_A27_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A27_Pos)                     /*!< SGPIO MASK_A: MASK_A27 Mask         */
-#define SGPIO_MASK_A_MASK_A28_Pos                             28                                                        /*!< SGPIO MASK_A: MASK_A28 Position     */
-#define SGPIO_MASK_A_MASK_A28_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A28_Pos)                     /*!< SGPIO MASK_A: MASK_A28 Mask         */
-#define SGPIO_MASK_A_MASK_A29_Pos                             29                                                        /*!< SGPIO MASK_A: MASK_A29 Position     */
-#define SGPIO_MASK_A_MASK_A29_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A29_Pos)                     /*!< SGPIO MASK_A: MASK_A29 Mask         */
-#define SGPIO_MASK_A_MASK_A30_Pos                             30                                                        /*!< SGPIO MASK_A: MASK_A30 Position     */
-#define SGPIO_MASK_A_MASK_A30_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A30_Pos)                     /*!< SGPIO MASK_A: MASK_A30 Mask         */
-#define SGPIO_MASK_A_MASK_A31_Pos                             31                                                        /*!< SGPIO MASK_A: MASK_A31 Position     */
-#define SGPIO_MASK_A_MASK_A31_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A31_Pos)                     /*!< SGPIO MASK_A: MASK_A31 Mask         */
-
-// --------------------------------------  SGPIO_MASK_H  ------------------------------------------
-#define SGPIO_MASK_H_MASK_H0_Pos                              0                                                         /*!< SGPIO MASK_H: MASK_H0 Position      */
-#define SGPIO_MASK_H_MASK_H0_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H0_Pos)                      /*!< SGPIO MASK_H: MASK_H0 Mask          */
-#define SGPIO_MASK_H_MASK_H1_Pos                              1                                                         /*!< SGPIO MASK_H: MASK_H1 Position      */
-#define SGPIO_MASK_H_MASK_H1_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H1_Pos)                      /*!< SGPIO MASK_H: MASK_H1 Mask          */
-#define SGPIO_MASK_H_MASK_H2_Pos                              2                                                         /*!< SGPIO MASK_H: MASK_H2 Position      */
-#define SGPIO_MASK_H_MASK_H2_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H2_Pos)                      /*!< SGPIO MASK_H: MASK_H2 Mask          */
-#define SGPIO_MASK_H_MASK_H3_Pos                              3                                                         /*!< SGPIO MASK_H: MASK_H3 Position      */
-#define SGPIO_MASK_H_MASK_H3_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H3_Pos)                      /*!< SGPIO MASK_H: MASK_H3 Mask          */
-#define SGPIO_MASK_H_MASK_H4_Pos                              4                                                         /*!< SGPIO MASK_H: MASK_H4 Position      */
-#define SGPIO_MASK_H_MASK_H4_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H4_Pos)                      /*!< SGPIO MASK_H: MASK_H4 Mask          */
-#define SGPIO_MASK_H_MASK_H5_Pos                              5                                                         /*!< SGPIO MASK_H: MASK_H5 Position      */
-#define SGPIO_MASK_H_MASK_H5_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H5_Pos)                      /*!< SGPIO MASK_H: MASK_H5 Mask          */
-#define SGPIO_MASK_H_MASK_H6_Pos                              6                                                         /*!< SGPIO MASK_H: MASK_H6 Position      */
-#define SGPIO_MASK_H_MASK_H6_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H6_Pos)                      /*!< SGPIO MASK_H: MASK_H6 Mask          */
-#define SGPIO_MASK_H_MASK_H7_Pos                              7                                                         /*!< SGPIO MASK_H: MASK_H7 Position      */
-#define SGPIO_MASK_H_MASK_H7_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H7_Pos)                      /*!< SGPIO MASK_H: MASK_H7 Mask          */
-#define SGPIO_MASK_H_MASK_H8_Pos                              8                                                         /*!< SGPIO MASK_H: MASK_H8 Position      */
-#define SGPIO_MASK_H_MASK_H8_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H8_Pos)                      /*!< SGPIO MASK_H: MASK_H8 Mask          */
-#define SGPIO_MASK_H_MASK_H9_Pos                              9                                                         /*!< SGPIO MASK_H: MASK_H9 Position      */
-#define SGPIO_MASK_H_MASK_H9_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H9_Pos)                      /*!< SGPIO MASK_H: MASK_H9 Mask          */
-#define SGPIO_MASK_H_MASK_H10_Pos                             10                                                        /*!< SGPIO MASK_H: MASK_H10 Position     */
-#define SGPIO_MASK_H_MASK_H10_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H10_Pos)                     /*!< SGPIO MASK_H: MASK_H10 Mask         */
-#define SGPIO_MASK_H_MASK_H11_Pos                             11                                                        /*!< SGPIO MASK_H: MASK_H11 Position     */
-#define SGPIO_MASK_H_MASK_H11_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H11_Pos)                     /*!< SGPIO MASK_H: MASK_H11 Mask         */
-#define SGPIO_MASK_H_MASK_H12_Pos                             12                                                        /*!< SGPIO MASK_H: MASK_H12 Position     */
-#define SGPIO_MASK_H_MASK_H12_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H12_Pos)                     /*!< SGPIO MASK_H: MASK_H12 Mask         */
-#define SGPIO_MASK_H_MASK_H13_Pos                             13                                                        /*!< SGPIO MASK_H: MASK_H13 Position     */
-#define SGPIO_MASK_H_MASK_H13_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H13_Pos)                     /*!< SGPIO MASK_H: MASK_H13 Mask         */
-#define SGPIO_MASK_H_MASK_H14_Pos                             14                                                        /*!< SGPIO MASK_H: MASK_H14 Position     */
-#define SGPIO_MASK_H_MASK_H14_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H14_Pos)                     /*!< SGPIO MASK_H: MASK_H14 Mask         */
-#define SGPIO_MASK_H_MASK_H15_Pos                             15                                                        /*!< SGPIO MASK_H: MASK_H15 Position     */
-#define SGPIO_MASK_H_MASK_H15_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H15_Pos)                     /*!< SGPIO MASK_H: MASK_H15 Mask         */
-#define SGPIO_MASK_H_MASK_H16_Pos                             16                                                        /*!< SGPIO MASK_H: MASK_H16 Position     */
-#define SGPIO_MASK_H_MASK_H16_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H16_Pos)                     /*!< SGPIO MASK_H: MASK_H16 Mask         */
-#define SGPIO_MASK_H_MASK_H17_Pos                             17                                                        /*!< SGPIO MASK_H: MASK_H17 Position     */
-#define SGPIO_MASK_H_MASK_H17_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H17_Pos)                     /*!< SGPIO MASK_H: MASK_H17 Mask         */
-#define SGPIO_MASK_H_MASK_H18_Pos                             18                                                        /*!< SGPIO MASK_H: MASK_H18 Position     */
-#define SGPIO_MASK_H_MASK_H18_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H18_Pos)                     /*!< SGPIO MASK_H: MASK_H18 Mask         */
-#define SGPIO_MASK_H_MASK_H19_Pos                             19                                                        /*!< SGPIO MASK_H: MASK_H19 Position     */
-#define SGPIO_MASK_H_MASK_H19_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H19_Pos)                     /*!< SGPIO MASK_H: MASK_H19 Mask         */
-#define SGPIO_MASK_H_MASK_H20_Pos                             20                                                        /*!< SGPIO MASK_H: MASK_H20 Position     */
-#define SGPIO_MASK_H_MASK_H20_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H20_Pos)                     /*!< SGPIO MASK_H: MASK_H20 Mask         */
-#define SGPIO_MASK_H_MASK_H21_Pos                             21                                                        /*!< SGPIO MASK_H: MASK_H21 Position     */
-#define SGPIO_MASK_H_MASK_H21_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H21_Pos)                     /*!< SGPIO MASK_H: MASK_H21 Mask         */
-#define SGPIO_MASK_H_MASK_H22_Pos                             22                                                        /*!< SGPIO MASK_H: MASK_H22 Position     */
-#define SGPIO_MASK_H_MASK_H22_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H22_Pos)                     /*!< SGPIO MASK_H: MASK_H22 Mask         */
-#define SGPIO_MASK_H_MASK_H23_Pos                             23                                                        /*!< SGPIO MASK_H: MASK_H23 Position     */
-#define SGPIO_MASK_H_MASK_H23_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H23_Pos)                     /*!< SGPIO MASK_H: MASK_H23 Mask         */
-#define SGPIO_MASK_H_MASK_H24_Pos                             24                                                        /*!< SGPIO MASK_H: MASK_H24 Position     */
-#define SGPIO_MASK_H_MASK_H24_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H24_Pos)                     /*!< SGPIO MASK_H: MASK_H24 Mask         */
-#define SGPIO_MASK_H_MASK_H25_Pos                             25                                                        /*!< SGPIO MASK_H: MASK_H25 Position     */
-#define SGPIO_MASK_H_MASK_H25_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H25_Pos)                     /*!< SGPIO MASK_H: MASK_H25 Mask         */
-#define SGPIO_MASK_H_MASK_H26_Pos                             26                                                        /*!< SGPIO MASK_H: MASK_H26 Position     */
-#define SGPIO_MASK_H_MASK_H26_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H26_Pos)                     /*!< SGPIO MASK_H: MASK_H26 Mask         */
-#define SGPIO_MASK_H_MASK_H27_Pos                             27                                                        /*!< SGPIO MASK_H: MASK_H27 Position     */
-#define SGPIO_MASK_H_MASK_H27_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H27_Pos)                     /*!< SGPIO MASK_H: MASK_H27 Mask         */
-#define SGPIO_MASK_H_MASK_H28_Pos                             28                                                        /*!< SGPIO MASK_H: MASK_H28 Position     */
-#define SGPIO_MASK_H_MASK_H28_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H28_Pos)                     /*!< SGPIO MASK_H: MASK_H28 Mask         */
-#define SGPIO_MASK_H_MASK_H29_Pos                             29                                                        /*!< SGPIO MASK_H: MASK_H29 Position     */
-#define SGPIO_MASK_H_MASK_H29_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H29_Pos)                     /*!< SGPIO MASK_H: MASK_H29 Mask         */
-#define SGPIO_MASK_H_MASK_H30_Pos                             30                                                        /*!< SGPIO MASK_H: MASK_H30 Position     */
-#define SGPIO_MASK_H_MASK_H30_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H30_Pos)                     /*!< SGPIO MASK_H: MASK_H30 Mask         */
-#define SGPIO_MASK_H_MASK_H31_Pos                             31                                                        /*!< SGPIO MASK_H: MASK_H31 Position     */
-#define SGPIO_MASK_H_MASK_H31_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H31_Pos)                     /*!< SGPIO MASK_H: MASK_H31 Mask         */
-
-// --------------------------------------  SGPIO_MASK_I  ------------------------------------------
-#define SGPIO_MASK_I_MASK_I0_Pos                              0                                                         /*!< SGPIO MASK_I: MASK_I0 Position      */
-#define SGPIO_MASK_I_MASK_I0_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I0_Pos)                      /*!< SGPIO MASK_I: MASK_I0 Mask          */
-#define SGPIO_MASK_I_MASK_I1_Pos                              1                                                         /*!< SGPIO MASK_I: MASK_I1 Position      */
-#define SGPIO_MASK_I_MASK_I1_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I1_Pos)                      /*!< SGPIO MASK_I: MASK_I1 Mask          */
-#define SGPIO_MASK_I_MASK_I2_Pos                              2                                                         /*!< SGPIO MASK_I: MASK_I2 Position      */
-#define SGPIO_MASK_I_MASK_I2_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I2_Pos)                      /*!< SGPIO MASK_I: MASK_I2 Mask          */
-#define SGPIO_MASK_I_MASK_I3_Pos                              3                                                         /*!< SGPIO MASK_I: MASK_I3 Position      */
-#define SGPIO_MASK_I_MASK_I3_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I3_Pos)                      /*!< SGPIO MASK_I: MASK_I3 Mask          */
-#define SGPIO_MASK_I_MASK_I4_Pos                              4                                                         /*!< SGPIO MASK_I: MASK_I4 Position      */
-#define SGPIO_MASK_I_MASK_I4_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I4_Pos)                      /*!< SGPIO MASK_I: MASK_I4 Mask          */
-#define SGPIO_MASK_I_MASK_I5_Pos                              5                                                         /*!< SGPIO MASK_I: MASK_I5 Position      */
-#define SGPIO_MASK_I_MASK_I5_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I5_Pos)                      /*!< SGPIO MASK_I: MASK_I5 Mask          */
-#define SGPIO_MASK_I_MASK_I6_Pos                              6                                                         /*!< SGPIO MASK_I: MASK_I6 Position      */
-#define SGPIO_MASK_I_MASK_I6_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I6_Pos)                      /*!< SGPIO MASK_I: MASK_I6 Mask          */
-#define SGPIO_MASK_I_MASK_I7_Pos                              7                                                         /*!< SGPIO MASK_I: MASK_I7 Position      */
-#define SGPIO_MASK_I_MASK_I7_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I7_Pos)                      /*!< SGPIO MASK_I: MASK_I7 Mask          */
-#define SGPIO_MASK_I_MASK_I8_Pos                              8                                                         /*!< SGPIO MASK_I: MASK_I8 Position      */
-#define SGPIO_MASK_I_MASK_I8_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I8_Pos)                      /*!< SGPIO MASK_I: MASK_I8 Mask          */
-#define SGPIO_MASK_I_MASK_I9_Pos                              9                                                         /*!< SGPIO MASK_I: MASK_I9 Position      */
-#define SGPIO_MASK_I_MASK_I9_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I9_Pos)                      /*!< SGPIO MASK_I: MASK_I9 Mask          */
-#define SGPIO_MASK_I_MASK_I10_Pos                             10                                                        /*!< SGPIO MASK_I: MASK_I10 Position     */
-#define SGPIO_MASK_I_MASK_I10_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I10_Pos)                     /*!< SGPIO MASK_I: MASK_I10 Mask         */
-#define SGPIO_MASK_I_MASK_I11_Pos                             11                                                        /*!< SGPIO MASK_I: MASK_I11 Position     */
-#define SGPIO_MASK_I_MASK_I11_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I11_Pos)                     /*!< SGPIO MASK_I: MASK_I11 Mask         */
-#define SGPIO_MASK_I_MASK_I12_Pos                             12                                                        /*!< SGPIO MASK_I: MASK_I12 Position     */
-#define SGPIO_MASK_I_MASK_I12_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I12_Pos)                     /*!< SGPIO MASK_I: MASK_I12 Mask         */
-#define SGPIO_MASK_I_MASK_I13_Pos                             13                                                        /*!< SGPIO MASK_I: MASK_I13 Position     */
-#define SGPIO_MASK_I_MASK_I13_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I13_Pos)                     /*!< SGPIO MASK_I: MASK_I13 Mask         */
-#define SGPIO_MASK_I_MASK_I14_Pos                             14                                                        /*!< SGPIO MASK_I: MASK_I14 Position     */
-#define SGPIO_MASK_I_MASK_I14_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I14_Pos)                     /*!< SGPIO MASK_I: MASK_I14 Mask         */
-#define SGPIO_MASK_I_MASK_I15_Pos                             15                                                        /*!< SGPIO MASK_I: MASK_I15 Position     */
-#define SGPIO_MASK_I_MASK_I15_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I15_Pos)                     /*!< SGPIO MASK_I: MASK_I15 Mask         */
-#define SGPIO_MASK_I_MASK_I16_Pos                             16                                                        /*!< SGPIO MASK_I: MASK_I16 Position     */
-#define SGPIO_MASK_I_MASK_I16_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I16_Pos)                     /*!< SGPIO MASK_I: MASK_I16 Mask         */
-#define SGPIO_MASK_I_MASK_I17_Pos                             17                                                        /*!< SGPIO MASK_I: MASK_I17 Position     */
-#define SGPIO_MASK_I_MASK_I17_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I17_Pos)                     /*!< SGPIO MASK_I: MASK_I17 Mask         */
-#define SGPIO_MASK_I_MASK_I18_Pos                             18                                                        /*!< SGPIO MASK_I: MASK_I18 Position     */
-#define SGPIO_MASK_I_MASK_I18_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I18_Pos)                     /*!< SGPIO MASK_I: MASK_I18 Mask         */
-#define SGPIO_MASK_I_MASK_I19_Pos                             19                                                        /*!< SGPIO MASK_I: MASK_I19 Position     */
-#define SGPIO_MASK_I_MASK_I19_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I19_Pos)                     /*!< SGPIO MASK_I: MASK_I19 Mask         */
-#define SGPIO_MASK_I_MASK_I20_Pos                             20                                                        /*!< SGPIO MASK_I: MASK_I20 Position     */
-#define SGPIO_MASK_I_MASK_I20_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I20_Pos)                     /*!< SGPIO MASK_I: MASK_I20 Mask         */
-#define SGPIO_MASK_I_MASK_I21_Pos                             21                                                        /*!< SGPIO MASK_I: MASK_I21 Position     */
-#define SGPIO_MASK_I_MASK_I21_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I21_Pos)                     /*!< SGPIO MASK_I: MASK_I21 Mask         */
-#define SGPIO_MASK_I_MASK_I22_Pos                             22                                                        /*!< SGPIO MASK_I: MASK_I22 Position     */
-#define SGPIO_MASK_I_MASK_I22_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I22_Pos)                     /*!< SGPIO MASK_I: MASK_I22 Mask         */
-#define SGPIO_MASK_I_MASK_I23_Pos                             23                                                        /*!< SGPIO MASK_I: MASK_I23 Position     */
-#define SGPIO_MASK_I_MASK_I23_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I23_Pos)                     /*!< SGPIO MASK_I: MASK_I23 Mask         */
-#define SGPIO_MASK_I_MASK_I24_Pos                             24                                                        /*!< SGPIO MASK_I: MASK_I24 Position     */
-#define SGPIO_MASK_I_MASK_I24_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I24_Pos)                     /*!< SGPIO MASK_I: MASK_I24 Mask         */
-#define SGPIO_MASK_I_MASK_I25_Pos                             25                                                        /*!< SGPIO MASK_I: MASK_I25 Position     */
-#define SGPIO_MASK_I_MASK_I25_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I25_Pos)                     /*!< SGPIO MASK_I: MASK_I25 Mask         */
-#define SGPIO_MASK_I_MASK_I26_Pos                             26                                                        /*!< SGPIO MASK_I: MASK_I26 Position     */
-#define SGPIO_MASK_I_MASK_I26_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I26_Pos)                     /*!< SGPIO MASK_I: MASK_I26 Mask         */
-#define SGPIO_MASK_I_MASK_I27_Pos                             27                                                        /*!< SGPIO MASK_I: MASK_I27 Position     */
-#define SGPIO_MASK_I_MASK_I27_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I27_Pos)                     /*!< SGPIO MASK_I: MASK_I27 Mask         */
-#define SGPIO_MASK_I_MASK_I28_Pos                             28                                                        /*!< SGPIO MASK_I: MASK_I28 Position     */
-#define SGPIO_MASK_I_MASK_I28_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I28_Pos)                     /*!< SGPIO MASK_I: MASK_I28 Mask         */
-#define SGPIO_MASK_I_MASK_I29_Pos                             29                                                        /*!< SGPIO MASK_I: MASK_I29 Position     */
-#define SGPIO_MASK_I_MASK_I29_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I29_Pos)                     /*!< SGPIO MASK_I: MASK_I29 Mask         */
-#define SGPIO_MASK_I_MASK_I30_Pos                             30                                                        /*!< SGPIO MASK_I: MASK_I30 Position     */
-#define SGPIO_MASK_I_MASK_I30_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I30_Pos)                     /*!< SGPIO MASK_I: MASK_I30 Mask         */
-#define SGPIO_MASK_I_MASK_I31_Pos                             31                                                        /*!< SGPIO MASK_I: MASK_I31 Position     */
-#define SGPIO_MASK_I_MASK_I31_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I31_Pos)                     /*!< SGPIO MASK_I: MASK_I31 Mask         */
-
-// --------------------------------------  SGPIO_MASK_P  ------------------------------------------
-#define SGPIO_MASK_P_MASK_P0_Pos                              0                                                         /*!< SGPIO MASK_P: MASK_P0 Position      */
-#define SGPIO_MASK_P_MASK_P0_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P0_Pos)                      /*!< SGPIO MASK_P: MASK_P0 Mask          */
-#define SGPIO_MASK_P_MASK_P1_Pos                              1                                                         /*!< SGPIO MASK_P: MASK_P1 Position      */
-#define SGPIO_MASK_P_MASK_P1_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P1_Pos)                      /*!< SGPIO MASK_P: MASK_P1 Mask          */
-#define SGPIO_MASK_P_MASK_P2_Pos                              2                                                         /*!< SGPIO MASK_P: MASK_P2 Position      */
-#define SGPIO_MASK_P_MASK_P2_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P2_Pos)                      /*!< SGPIO MASK_P: MASK_P2 Mask          */
-#define SGPIO_MASK_P_MASK_P3_Pos                              3                                                         /*!< SGPIO MASK_P: MASK_P3 Position      */
-#define SGPIO_MASK_P_MASK_P3_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P3_Pos)                      /*!< SGPIO MASK_P: MASK_P3 Mask          */
-#define SGPIO_MASK_P_MASK_P4_Pos                              4                                                         /*!< SGPIO MASK_P: MASK_P4 Position      */
-#define SGPIO_MASK_P_MASK_P4_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P4_Pos)                      /*!< SGPIO MASK_P: MASK_P4 Mask          */
-#define SGPIO_MASK_P_MASK_P5_Pos                              5                                                         /*!< SGPIO MASK_P: MASK_P5 Position      */
-#define SGPIO_MASK_P_MASK_P5_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P5_Pos)                      /*!< SGPIO MASK_P: MASK_P5 Mask          */
-#define SGPIO_MASK_P_MASK_P6_Pos                              6                                                         /*!< SGPIO MASK_P: MASK_P6 Position      */
-#define SGPIO_MASK_P_MASK_P6_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P6_Pos)                      /*!< SGPIO MASK_P: MASK_P6 Mask          */
-#define SGPIO_MASK_P_MASK_P7_Pos                              7                                                         /*!< SGPIO MASK_P: MASK_P7 Position      */
-#define SGPIO_MASK_P_MASK_P7_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P7_Pos)                      /*!< SGPIO MASK_P: MASK_P7 Mask          */
-#define SGPIO_MASK_P_MASK_P8_Pos                              8                                                         /*!< SGPIO MASK_P: MASK_P8 Position      */
-#define SGPIO_MASK_P_MASK_P8_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P8_Pos)                      /*!< SGPIO MASK_P: MASK_P8 Mask          */
-#define SGPIO_MASK_P_MASK_P9_Pos                              9                                                         /*!< SGPIO MASK_P: MASK_P9 Position      */
-#define SGPIO_MASK_P_MASK_P9_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P9_Pos)                      /*!< SGPIO MASK_P: MASK_P9 Mask          */
-#define SGPIO_MASK_P_MASK_P10_Pos                             10                                                        /*!< SGPIO MASK_P: MASK_P10 Position     */
-#define SGPIO_MASK_P_MASK_P10_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P10_Pos)                     /*!< SGPIO MASK_P: MASK_P10 Mask         */
-#define SGPIO_MASK_P_MASK_P11_Pos                             11                                                        /*!< SGPIO MASK_P: MASK_P11 Position     */
-#define SGPIO_MASK_P_MASK_P11_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P11_Pos)                     /*!< SGPIO MASK_P: MASK_P11 Mask         */
-#define SGPIO_MASK_P_MASK_P12_Pos                             12                                                        /*!< SGPIO MASK_P: MASK_P12 Position     */
-#define SGPIO_MASK_P_MASK_P12_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P12_Pos)                     /*!< SGPIO MASK_P: MASK_P12 Mask         */
-#define SGPIO_MASK_P_MASK_P13_Pos                             13                                                        /*!< SGPIO MASK_P: MASK_P13 Position     */
-#define SGPIO_MASK_P_MASK_P13_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P13_Pos)                     /*!< SGPIO MASK_P: MASK_P13 Mask         */
-#define SGPIO_MASK_P_MASK_P14_Pos                             14                                                        /*!< SGPIO MASK_P: MASK_P14 Position     */
-#define SGPIO_MASK_P_MASK_P14_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P14_Pos)                     /*!< SGPIO MASK_P: MASK_P14 Mask         */
-#define SGPIO_MASK_P_MASK_P15_Pos                             15                                                        /*!< SGPIO MASK_P: MASK_P15 Position     */
-#define SGPIO_MASK_P_MASK_P15_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P15_Pos)                     /*!< SGPIO MASK_P: MASK_P15 Mask         */
-#define SGPIO_MASK_P_MASK_P16_Pos                             16                                                        /*!< SGPIO MASK_P: MASK_P16 Position     */
-#define SGPIO_MASK_P_MASK_P16_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P16_Pos)                     /*!< SGPIO MASK_P: MASK_P16 Mask         */
-#define SGPIO_MASK_P_MASK_P17_Pos                             17                                                        /*!< SGPIO MASK_P: MASK_P17 Position     */
-#define SGPIO_MASK_P_MASK_P17_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P17_Pos)                     /*!< SGPIO MASK_P: MASK_P17 Mask         */
-#define SGPIO_MASK_P_MASK_P18_Pos                             18                                                        /*!< SGPIO MASK_P: MASK_P18 Position     */
-#define SGPIO_MASK_P_MASK_P18_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P18_Pos)                     /*!< SGPIO MASK_P: MASK_P18 Mask         */
-#define SGPIO_MASK_P_MASK_P19_Pos                             19                                                        /*!< SGPIO MASK_P: MASK_P19 Position     */
-#define SGPIO_MASK_P_MASK_P19_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P19_Pos)                     /*!< SGPIO MASK_P: MASK_P19 Mask         */
-#define SGPIO_MASK_P_MASK_P20_Pos                             20                                                        /*!< SGPIO MASK_P: MASK_P20 Position     */
-#define SGPIO_MASK_P_MASK_P20_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P20_Pos)                     /*!< SGPIO MASK_P: MASK_P20 Mask         */
-#define SGPIO_MASK_P_MASK_P21_Pos                             21                                                        /*!< SGPIO MASK_P: MASK_P21 Position     */
-#define SGPIO_MASK_P_MASK_P21_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P21_Pos)                     /*!< SGPIO MASK_P: MASK_P21 Mask         */
-#define SGPIO_MASK_P_MASK_P22_Pos                             22                                                        /*!< SGPIO MASK_P: MASK_P22 Position     */
-#define SGPIO_MASK_P_MASK_P22_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P22_Pos)                     /*!< SGPIO MASK_P: MASK_P22 Mask         */
-#define SGPIO_MASK_P_MASK_P23_Pos                             23                                                        /*!< SGPIO MASK_P: MASK_P23 Position     */
-#define SGPIO_MASK_P_MASK_P23_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P23_Pos)                     /*!< SGPIO MASK_P: MASK_P23 Mask         */
-#define SGPIO_MASK_P_MASK_P24_Pos                             24                                                        /*!< SGPIO MASK_P: MASK_P24 Position     */
-#define SGPIO_MASK_P_MASK_P24_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P24_Pos)                     /*!< SGPIO MASK_P: MASK_P24 Mask         */
-#define SGPIO_MASK_P_MASK_P25_Pos                             25                                                        /*!< SGPIO MASK_P: MASK_P25 Position     */
-#define SGPIO_MASK_P_MASK_P25_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P25_Pos)                     /*!< SGPIO MASK_P: MASK_P25 Mask         */
-#define SGPIO_MASK_P_MASK_P26_Pos                             26                                                        /*!< SGPIO MASK_P: MASK_P26 Position     */
-#define SGPIO_MASK_P_MASK_P26_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P26_Pos)                     /*!< SGPIO MASK_P: MASK_P26 Mask         */
-#define SGPIO_MASK_P_MASK_P27_Pos                             27                                                        /*!< SGPIO MASK_P: MASK_P27 Position     */
-#define SGPIO_MASK_P_MASK_P27_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P27_Pos)                     /*!< SGPIO MASK_P: MASK_P27 Mask         */
-#define SGPIO_MASK_P_MASK_P28_Pos                             28                                                        /*!< SGPIO MASK_P: MASK_P28 Position     */
-#define SGPIO_MASK_P_MASK_P28_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P28_Pos)                     /*!< SGPIO MASK_P: MASK_P28 Mask         */
-#define SGPIO_MASK_P_MASK_P29_Pos                             29                                                        /*!< SGPIO MASK_P: MASK_P29 Position     */
-#define SGPIO_MASK_P_MASK_P29_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P29_Pos)                     /*!< SGPIO MASK_P: MASK_P29 Mask         */
-#define SGPIO_MASK_P_MASK_P30_Pos                             30                                                        /*!< SGPIO MASK_P: MASK_P30 Position     */
-#define SGPIO_MASK_P_MASK_P30_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P30_Pos)                     /*!< SGPIO MASK_P: MASK_P30 Mask         */
-#define SGPIO_MASK_P_MASK_P31_Pos                             31                                                        /*!< SGPIO MASK_P: MASK_P31 Position     */
-#define SGPIO_MASK_P_MASK_P31_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P31_Pos)                     /*!< SGPIO MASK_P: MASK_P31 Mask         */
-
-// ------------------------------------  SGPIO_GPIO_INREG  ----------------------------------------
-#define SGPIO_GPIO_INREG_GPIO_IN0_Pos                         0                                                         /*!< SGPIO GPIO_INREG: GPIO_IN0 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN0_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN0_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN0 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN1_Pos                         1                                                         /*!< SGPIO GPIO_INREG: GPIO_IN1 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN1_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN1_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN1 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN2_Pos                         2                                                         /*!< SGPIO GPIO_INREG: GPIO_IN2 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN2_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN2_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN2 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN3_Pos                         3                                                         /*!< SGPIO GPIO_INREG: GPIO_IN3 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN3_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN3_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN3 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN4_Pos                         4                                                         /*!< SGPIO GPIO_INREG: GPIO_IN4 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN4_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN4_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN4 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN5_Pos                         5                                                         /*!< SGPIO GPIO_INREG: GPIO_IN5 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN5_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN5_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN5 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN6_Pos                         6                                                         /*!< SGPIO GPIO_INREG: GPIO_IN6 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN6_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN6_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN6 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN7_Pos                         7                                                         /*!< SGPIO GPIO_INREG: GPIO_IN7 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN7_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN7_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN7 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN8_Pos                         8                                                         /*!< SGPIO GPIO_INREG: GPIO_IN8 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN8_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN8_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN8 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN9_Pos                         9                                                         /*!< SGPIO GPIO_INREG: GPIO_IN9 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN9_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN9_Pos)                 /*!< SGPIO GPIO_INREG: GPIO_IN9 Mask     */
-#define SGPIO_GPIO_INREG_GPIO_IN10_Pos                        10                                                        /*!< SGPIO GPIO_INREG: GPIO_IN10 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN10_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN10_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN10 Mask    */
-#define SGPIO_GPIO_INREG_GPIO_IN11_Pos                        11                                                        /*!< SGPIO GPIO_INREG: GPIO_IN11 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN11_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN11_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN11 Mask    */
-#define SGPIO_GPIO_INREG_GPIO_IN12_Pos                        12                                                        /*!< SGPIO GPIO_INREG: GPIO_IN12 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN12_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN12_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN12 Mask    */
-#define SGPIO_GPIO_INREG_GPIO_IN13_Pos                        13                                                        /*!< SGPIO GPIO_INREG: GPIO_IN13 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN13_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN13_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN13 Mask    */
-#define SGPIO_GPIO_INREG_GPIO_IN14_Pos                        14                                                        /*!< SGPIO GPIO_INREG: GPIO_IN14 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN14_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN14_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN14 Mask    */
-#define SGPIO_GPIO_INREG_GPIO_IN15_Pos                        15                                                        /*!< SGPIO GPIO_INREG: GPIO_IN15 Position */
-#define SGPIO_GPIO_INREG_GPIO_IN15_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN15_Pos)                /*!< SGPIO GPIO_INREG: GPIO_IN15 Mask    */
-
-// ------------------------------------  SGPIO_GPIO_OUTREG  ---------------------------------------
-#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos                       0                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos                       1                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos                       2                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos                       3                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos                       4                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos                       5                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos                       6                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos                       7                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos                       8                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos                       9                                                         /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos)               /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Mask   */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos                      10                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Mask  */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos                      11                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Mask  */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos                      12                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Mask  */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos                      13                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Mask  */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos                      14                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Mask  */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos                      15                                                        /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Position */
-#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos)              /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Mask  */
-
-// ------------------------------------  SGPIO_GPIO_OENREG  ---------------------------------------
-#define SGPIO_GPIO_OENREG_GPIO_OE0_Pos                        0                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE0 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE0_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE0_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE0 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE1_Pos                        1                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE1 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE1_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE1_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE1 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE2_Pos                        2                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE2 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE2_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE2_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE2 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE3_Pos                        3                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE3 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE3_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE3_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE3 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE4_Pos                        4                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE4 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE4_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE4_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE4 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE5_Pos                        5                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE5 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE5_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE5_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE5 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE6_Pos                        6                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE6 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE6_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE6_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE6 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE7_Pos                        7                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE7 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE7_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE7_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE7 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE8_Pos                        8                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE8 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE8_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE8_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE8 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE9_Pos                        9                                                         /*!< SGPIO GPIO_OENREG: GPIO_OE9 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE9_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE9_Pos)                /*!< SGPIO GPIO_OENREG: GPIO_OE9 Mask    */
-#define SGPIO_GPIO_OENREG_GPIO_OE10_Pos                       10                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE10 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE10_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE10_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE10 Mask   */
-#define SGPIO_GPIO_OENREG_GPIO_OE11_Pos                       11                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE11 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE11_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE11_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE11 Mask   */
-#define SGPIO_GPIO_OENREG_GPIO_OE12_Pos                       12                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE12 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE12_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE12_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE12 Mask   */
-#define SGPIO_GPIO_OENREG_GPIO_OE13_Pos                       13                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE13 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE13_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE13_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE13 Mask   */
-#define SGPIO_GPIO_OENREG_GPIO_OE14_Pos                       14                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE14 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE14_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE14_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE14 Mask   */
-#define SGPIO_GPIO_OENREG_GPIO_OE15_Pos                       15                                                        /*!< SGPIO GPIO_OENREG: GPIO_OE15 Position */
-#define SGPIO_GPIO_OENREG_GPIO_OE15_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE15_Pos)               /*!< SGPIO GPIO_OENREG: GPIO_OE15 Mask   */
-
-// -----------------------------------  SGPIO_CTRL_ENABLED  ---------------------------------------
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos                  0                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos                  1                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos                  2                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos                  3                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos                  4                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos                  5                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos                  6                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos                  7                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos                  8                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos                  9                                                         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos)          /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos                 10                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos                 11                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos                 12                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos                 13                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos                 14                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Mask */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos                 15                                                        /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Position */
-#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos)         /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Mask */
-
-// -----------------------------------  SGPIO_CTRL_DISABLED  --------------------------------------
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos               0                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos               1                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos               2                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos               3                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos               4                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos               5                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos               6                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos               7                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos               8                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos               9                                                         /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos)       /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos              10                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos              11                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos              12                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos              13                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos              14                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Mask */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos              15                                                        /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Position */
-#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos)      /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Mask */
-
-// -------------------------------------  SGPIO_CLR_EN_0  -----------------------------------------
-#define SGPIO_CLR_EN_0_CLR_SCI0_Pos                           0                                                         /*!< SGPIO CLR_EN_0: CLR_SCI0 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI0_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI0_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI0 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI1_Pos                           1                                                         /*!< SGPIO CLR_EN_0: CLR_SCI1 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI1_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI1_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI1 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI2_Pos                           2                                                         /*!< SGPIO CLR_EN_0: CLR_SCI2 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI2_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI2_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI2 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI3_Pos                           3                                                         /*!< SGPIO CLR_EN_0: CLR_SCI3 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI3_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI3_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI3 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI4_Pos                           4                                                         /*!< SGPIO CLR_EN_0: CLR_SCI4 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI4_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI4_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI4 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI5_Pos                           5                                                         /*!< SGPIO CLR_EN_0: CLR_SCI5 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI5_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI5_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI5 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI6_Pos                           6                                                         /*!< SGPIO CLR_EN_0: CLR_SCI6 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI6_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI6_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI6 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI7_Pos                           7                                                         /*!< SGPIO CLR_EN_0: CLR_SCI7 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI7_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI7_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI7 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI8_Pos                           8                                                         /*!< SGPIO CLR_EN_0: CLR_SCI8 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI8_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI8_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI8 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI9_Pos                           9                                                         /*!< SGPIO CLR_EN_0: CLR_SCI9 Position   */
-#define SGPIO_CLR_EN_0_CLR_SCI9_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI9_Pos)                   /*!< SGPIO CLR_EN_0: CLR_SCI9 Mask       */
-#define SGPIO_CLR_EN_0_CLR_SCI10_Pos                          10                                                        /*!< SGPIO CLR_EN_0: CLR_SCI10 Position  */
-#define SGPIO_CLR_EN_0_CLR_SCI10_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI10_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI10 Mask      */
-#define SGPIO_CLR_EN_0_CLR_SCI11_Pos                          11                                                        /*!< SGPIO CLR_EN_0: CLR_SCI11 Position  */
-#define SGPIO_CLR_EN_0_CLR_SCI11_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI11_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI11 Mask      */
-#define SGPIO_CLR_EN_0_CLR_SCI12_Pos                          12                                                        /*!< SGPIO CLR_EN_0: CLR_SCI12 Position  */
-#define SGPIO_CLR_EN_0_CLR_SCI12_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI12_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI12 Mask      */
-#define SGPIO_CLR_EN_0_CLR_SCI13_Pos                          13                                                        /*!< SGPIO CLR_EN_0: CLR_SCI13 Position  */
-#define SGPIO_CLR_EN_0_CLR_SCI13_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI13_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI13 Mask      */
-#define SGPIO_CLR_EN_0_CLR_SCI14_Pos                          14                                                        /*!< SGPIO CLR_EN_0: CLR_SCI14 Position  */
-#define SGPIO_CLR_EN_0_CLR_SCI14_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI14_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI14 Mask      */
-#define SGPIO_CLR_EN_0_CLR_SCI15_Pos                          15                                                        /*!< SGPIO CLR_EN_0: CLR_SCI15 Position  */
-#define SGPIO_CLR_EN_0_CLR_SCI15_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI15_Pos)                  /*!< SGPIO CLR_EN_0: CLR_SCI15 Mask      */
-
-// -------------------------------------  SGPIO_SET_EN_0  -----------------------------------------
-#define SGPIO_SET_EN_0_SET_SCI0_Pos                           0                                                         /*!< SGPIO SET_EN_0: SET_SCI0 Position   */
-#define SGPIO_SET_EN_0_SET_SCI0_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI0_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI0 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI1_Pos                           1                                                         /*!< SGPIO SET_EN_0: SET_SCI1 Position   */
-#define SGPIO_SET_EN_0_SET_SCI1_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI1_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI1 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI2_Pos                           2                                                         /*!< SGPIO SET_EN_0: SET_SCI2 Position   */
-#define SGPIO_SET_EN_0_SET_SCI2_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI2_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI2 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI3_Pos                           3                                                         /*!< SGPIO SET_EN_0: SET_SCI3 Position   */
-#define SGPIO_SET_EN_0_SET_SCI3_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI3_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI3 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI4_Pos                           4                                                         /*!< SGPIO SET_EN_0: SET_SCI4 Position   */
-#define SGPIO_SET_EN_0_SET_SCI4_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI4_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI4 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI5_Pos                           5                                                         /*!< SGPIO SET_EN_0: SET_SCI5 Position   */
-#define SGPIO_SET_EN_0_SET_SCI5_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI5_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI5 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI6_Pos                           6                                                         /*!< SGPIO SET_EN_0: SET_SCI6 Position   */
-#define SGPIO_SET_EN_0_SET_SCI6_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI6_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI6 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI7_Pos                           7                                                         /*!< SGPIO SET_EN_0: SET_SCI7 Position   */
-#define SGPIO_SET_EN_0_SET_SCI7_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI7_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI7 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI8_Pos                           8                                                         /*!< SGPIO SET_EN_0: SET_SCI8 Position   */
-#define SGPIO_SET_EN_0_SET_SCI8_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI8_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI8 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI9_Pos                           9                                                         /*!< SGPIO SET_EN_0: SET_SCI9 Position   */
-#define SGPIO_SET_EN_0_SET_SCI9_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI9_Pos)                   /*!< SGPIO SET_EN_0: SET_SCI9 Mask       */
-#define SGPIO_SET_EN_0_SET_SCI10_Pos                          10                                                        /*!< SGPIO SET_EN_0: SET_SCI10 Position  */
-#define SGPIO_SET_EN_0_SET_SCI10_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI10_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI10 Mask      */
-#define SGPIO_SET_EN_0_SET_SCI11_Pos                          11                                                        /*!< SGPIO SET_EN_0: SET_SCI11 Position  */
-#define SGPIO_SET_EN_0_SET_SCI11_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI11_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI11 Mask      */
-#define SGPIO_SET_EN_0_SET_SCI12_Pos                          12                                                        /*!< SGPIO SET_EN_0: SET_SCI12 Position  */
-#define SGPIO_SET_EN_0_SET_SCI12_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI12_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI12 Mask      */
-#define SGPIO_SET_EN_0_SET_SCI13_Pos                          13                                                        /*!< SGPIO SET_EN_0: SET_SCI13 Position  */
-#define SGPIO_SET_EN_0_SET_SCI13_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI13_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI13 Mask      */
-#define SGPIO_SET_EN_0_SET_SCI14_Pos                          14                                                        /*!< SGPIO SET_EN_0: SET_SCI14 Position  */
-#define SGPIO_SET_EN_0_SET_SCI14_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI14_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI14 Mask      */
-#define SGPIO_SET_EN_0_SET_SCI15_Pos                          15                                                        /*!< SGPIO SET_EN_0: SET_SCI15 Position  */
-#define SGPIO_SET_EN_0_SET_SCI15_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI15_Pos)                  /*!< SGPIO SET_EN_0: SET_SCI15 Mask      */
-
-// -------------------------------------  SGPIO_ENABLE_0  -----------------------------------------
-#define SGPIO_ENABLE_0_ENABLE_SCI0_Pos                        0                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI0 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI0_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI0_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI0 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI1_Pos                        1                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI1 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI1_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI1_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI1 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI2_Pos                        2                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI2 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI2_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI2_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI2 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI3_Pos                        3                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI3 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI3_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI3_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI3 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI4_Pos                        4                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI4 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI4_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI4_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI4 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI5_Pos                        5                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI5 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI5_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI5_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI5 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI6_Pos                        6                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI6 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI6_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI6_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI6 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI7_Pos                        7                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI7 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI7_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI7_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI7 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI8_Pos                        8                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI8 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI8_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI8_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI8 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI9_Pos                        9                                                         /*!< SGPIO ENABLE_0: ENABLE_SCI9 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI9_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI9_Pos)                /*!< SGPIO ENABLE_0: ENABLE_SCI9 Mask    */
-#define SGPIO_ENABLE_0_ENABLE_SCI10_Pos                       10                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI10 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI10_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI10_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI10 Mask   */
-#define SGPIO_ENABLE_0_ENABLE_SCI11_Pos                       11                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI11 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI11_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI11_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI11 Mask   */
-#define SGPIO_ENABLE_0_ENABLE_SCI12_Pos                       12                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI12 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI12_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI12_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI12 Mask   */
-#define SGPIO_ENABLE_0_ENABLE_SCI13_Pos                       13                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI13 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI13_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI13_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI13 Mask   */
-#define SGPIO_ENABLE_0_ENABLE_SCI14_Pos                       14                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI14 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI14_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI14_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI14 Mask   */
-#define SGPIO_ENABLE_0_ENABLE_SCI15_Pos                       15                                                        /*!< SGPIO ENABLE_0: ENABLE_SCI15 Position */
-#define SGPIO_ENABLE_0_ENABLE_SCI15_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI15_Pos)               /*!< SGPIO ENABLE_0: ENABLE_SCI15 Mask   */
-
-// -------------------------------------  SGPIO_STATUS_0  -----------------------------------------
-#define SGPIO_STATUS_0_STATUS_SCI0_Pos                        0                                                         /*!< SGPIO STATUS_0: STATUS_SCI0 Position */
-#define SGPIO_STATUS_0_STATUS_SCI0_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI0_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI0 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI1_Pos                        1                                                         /*!< SGPIO STATUS_0: STATUS_SCI1 Position */
-#define SGPIO_STATUS_0_STATUS_SCI1_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI1_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI1 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI2_Pos                        2                                                         /*!< SGPIO STATUS_0: STATUS_SCI2 Position */
-#define SGPIO_STATUS_0_STATUS_SCI2_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI2_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI2 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI3_Pos                        3                                                         /*!< SGPIO STATUS_0: STATUS_SCI3 Position */
-#define SGPIO_STATUS_0_STATUS_SCI3_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI3_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI3 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI4_Pos                        4                                                         /*!< SGPIO STATUS_0: STATUS_SCI4 Position */
-#define SGPIO_STATUS_0_STATUS_SCI4_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI4_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI4 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI5_Pos                        5                                                         /*!< SGPIO STATUS_0: STATUS_SCI5 Position */
-#define SGPIO_STATUS_0_STATUS_SCI5_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI5_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI5 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI6_Pos                        6                                                         /*!< SGPIO STATUS_0: STATUS_SCI6 Position */
-#define SGPIO_STATUS_0_STATUS_SCI6_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI6_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI6 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI7_Pos                        7                                                         /*!< SGPIO STATUS_0: STATUS_SCI7 Position */
-#define SGPIO_STATUS_0_STATUS_SCI7_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI7_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI7 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI8_Pos                        8                                                         /*!< SGPIO STATUS_0: STATUS_SCI8 Position */
-#define SGPIO_STATUS_0_STATUS_SCI8_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI8_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI8 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI9_Pos                        9                                                         /*!< SGPIO STATUS_0: STATUS_SCI9 Position */
-#define SGPIO_STATUS_0_STATUS_SCI9_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI9_Pos)                /*!< SGPIO STATUS_0: STATUS_SCI9 Mask    */
-#define SGPIO_STATUS_0_STATUS_SCI10_Pos                       10                                                        /*!< SGPIO STATUS_0: STATUS_SCI10 Position */
-#define SGPIO_STATUS_0_STATUS_SCI10_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI10_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI10 Mask   */
-#define SGPIO_STATUS_0_STATUS_SCI11_Pos                       11                                                        /*!< SGPIO STATUS_0: STATUS_SCI11 Position */
-#define SGPIO_STATUS_0_STATUS_SCI11_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI11_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI11 Mask   */
-#define SGPIO_STATUS_0_STATUS_SCI12_Pos                       12                                                        /*!< SGPIO STATUS_0: STATUS_SCI12 Position */
-#define SGPIO_STATUS_0_STATUS_SCI12_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI12_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI12 Mask   */
-#define SGPIO_STATUS_0_STATUS_SCI13_Pos                       13                                                        /*!< SGPIO STATUS_0: STATUS_SCI13 Position */
-#define SGPIO_STATUS_0_STATUS_SCI13_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI13_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI13 Mask   */
-#define SGPIO_STATUS_0_STATUS_SCI14_Pos                       14                                                        /*!< SGPIO STATUS_0: STATUS_SCI14 Position */
-#define SGPIO_STATUS_0_STATUS_SCI14_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI14_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI14 Mask   */
-#define SGPIO_STATUS_0_STATUS_SCI15_Pos                       15                                                        /*!< SGPIO STATUS_0: STATUS_SCI15 Position */
-#define SGPIO_STATUS_0_STATUS_SCI15_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI15_Pos)               /*!< SGPIO STATUS_0: STATUS_SCI15 Mask   */
-
-// -----------------------------------  SGPIO_CTR_STATUS_0  ---------------------------------------
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos)        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Mask */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Position */
-#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos)       /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Mask */
-
-// -----------------------------------  SGPIO_SET_STATUS_0  ---------------------------------------
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos                0                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos                1                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos                2                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos                3                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos                4                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos                5                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos                6                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos                7                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos                8                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos                9                                                         /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos)        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos               10                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos               11                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos               12                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos               13                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos               14                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Mask */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos               15                                                        /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Position */
-#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos)       /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Mask */
-
-// -------------------------------------  SGPIO_CLR_EN_1  -----------------------------------------
-#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos                        0                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos                        1                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos                        2                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos                        3                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos                        4                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos                        5                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos                        6                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos                        7                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos                        8                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos                        9                                                         /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos)                /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Mask    */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos                       10                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Mask   */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos                       11                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Mask   */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos                       12                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Mask   */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos                       13                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Mask   */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos                       14                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Mask   */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos                       15                                                        /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Position */
-#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos)               /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Mask   */
-
-// -------------------------------------  SGPIO_SET_EN_1  -----------------------------------------
-#define SGPIO_SET_EN_1_SET_EN_CCI0_Pos                        0                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI0 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI0_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI0_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI0 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI1_Pos                        1                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI1 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI1_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI1_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI1 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI2_Pos                        2                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI2 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI2_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI2_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI2 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI3_Pos                        3                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI3 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI3_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI3_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI3 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI4_Pos                        4                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI4 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI4_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI4_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI4 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI5_Pos                        5                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI5 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI5_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI5_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI5 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI6_Pos                        6                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI6 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI6_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI6_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI6 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI7_Pos                        7                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI7 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI7_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI7_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI7 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI8_Pos                        8                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI8 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI8_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI8_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI8 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI9_Pos                        9                                                         /*!< SGPIO SET_EN_1: SET_EN_CCI9 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI9_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI9_Pos)                /*!< SGPIO SET_EN_1: SET_EN_CCI9 Mask    */
-#define SGPIO_SET_EN_1_SET_EN_CCI10_Pos                       10                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI10 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI10_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI10_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI10 Mask   */
-#define SGPIO_SET_EN_1_SET_EN_CCI11_Pos                       11                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI11 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI11_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI11_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI11 Mask   */
-#define SGPIO_SET_EN_1_SET_EN_CCI12_Pos                       12                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI12 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI12_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI12_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI12 Mask   */
-#define SGPIO_SET_EN_1_SET_EN_CCI13_Pos                       13                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI13 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI13_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI13_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI13 Mask   */
-#define SGPIO_SET_EN_1_SET_EN_CCI14_Pos                       14                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI14 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI14_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI14_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI14 Mask   */
-#define SGPIO_SET_EN_1_SET_EN_CCI15_Pos                       15                                                        /*!< SGPIO SET_EN_1: SET_EN_CCI15 Position */
-#define SGPIO_SET_EN_1_SET_EN_CCI15_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI15_Pos)               /*!< SGPIO SET_EN_1: SET_EN_CCI15 Mask   */
-
-// -------------------------------------  SGPIO_ENABLE_1  -----------------------------------------
-#define SGPIO_ENABLE_1_ENABLE_CCI0_Pos                        0                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI0 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI0_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI0_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI0 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI1_Pos                        1                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI1 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI1_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI1_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI1 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI2_Pos                        2                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI2 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI2_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI2_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI2 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI3_Pos                        3                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI3 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI3_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI3_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI3 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI4_Pos                        4                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI4 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI4_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI4_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI4 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI5_Pos                        5                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI5 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI5_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI5_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI5 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI6_Pos                        6                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI6 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI6_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI6_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI6 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI7_Pos                        7                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI7 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI7_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI7_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI7 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI8_Pos                        8                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI8 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI8_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI8_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI8 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI9_Pos                        9                                                         /*!< SGPIO ENABLE_1: ENABLE_CCI9 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI9_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI9_Pos)                /*!< SGPIO ENABLE_1: ENABLE_CCI9 Mask    */
-#define SGPIO_ENABLE_1_ENABLE_CCI10_Pos                       10                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI10 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI10_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI10_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI10 Mask   */
-#define SGPIO_ENABLE_1_ENABLE_CCI11_Pos                       11                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI11 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI11_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI11_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI11 Mask   */
-#define SGPIO_ENABLE_1_ENABLE_CCI12_Pos                       12                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI12 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI12_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI12_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI12 Mask   */
-#define SGPIO_ENABLE_1_ENABLE_CCI13_Pos                       13                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI13 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI13_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI13_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI13 Mask   */
-#define SGPIO_ENABLE_1_ENABLE_CCI14_Pos                       14                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI14 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI14_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI14_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI14 Mask   */
-#define SGPIO_ENABLE_1_ENABLE_CCI15_Pos                       15                                                        /*!< SGPIO ENABLE_1: ENABLE_CCI15 Position */
-#define SGPIO_ENABLE_1_ENABLE_CCI15_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI15_Pos)               /*!< SGPIO ENABLE_1: ENABLE_CCI15 Mask   */
-
-// -------------------------------------  SGPIO_STATUS_1  -----------------------------------------
-#define SGPIO_STATUS_1_STATUS_CCI0_Pos                        0                                                         /*!< SGPIO STATUS_1: STATUS_CCI0 Position */
-#define SGPIO_STATUS_1_STATUS_CCI0_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI0_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI0 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI1_Pos                        1                                                         /*!< SGPIO STATUS_1: STATUS_CCI1 Position */
-#define SGPIO_STATUS_1_STATUS_CCI1_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI1_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI1 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI2_Pos                        2                                                         /*!< SGPIO STATUS_1: STATUS_CCI2 Position */
-#define SGPIO_STATUS_1_STATUS_CCI2_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI2_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI2 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI3_Pos                        3                                                         /*!< SGPIO STATUS_1: STATUS_CCI3 Position */
-#define SGPIO_STATUS_1_STATUS_CCI3_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI3_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI3 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI4_Pos                        4                                                         /*!< SGPIO STATUS_1: STATUS_CCI4 Position */
-#define SGPIO_STATUS_1_STATUS_CCI4_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI4_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI4 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI5_Pos                        5                                                         /*!< SGPIO STATUS_1: STATUS_CCI5 Position */
-#define SGPIO_STATUS_1_STATUS_CCI5_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI5_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI5 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI6_Pos                        6                                                         /*!< SGPIO STATUS_1: STATUS_CCI6 Position */
-#define SGPIO_STATUS_1_STATUS_CCI6_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI6_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI6 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI7_Pos                        7                                                         /*!< SGPIO STATUS_1: STATUS_CCI7 Position */
-#define SGPIO_STATUS_1_STATUS_CCI7_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI7_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI7 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI8_Pos                        8                                                         /*!< SGPIO STATUS_1: STATUS_CCI8 Position */
-#define SGPIO_STATUS_1_STATUS_CCI8_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI8_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI8 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI9_Pos                        9                                                         /*!< SGPIO STATUS_1: STATUS_CCI9 Position */
-#define SGPIO_STATUS_1_STATUS_CCI9_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI9_Pos)                /*!< SGPIO STATUS_1: STATUS_CCI9 Mask    */
-#define SGPIO_STATUS_1_STATUS_CCI10_Pos                       10                                                        /*!< SGPIO STATUS_1: STATUS_CCI10 Position */
-#define SGPIO_STATUS_1_STATUS_CCI10_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI10_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI10 Mask   */
-#define SGPIO_STATUS_1_STATUS_CCI11_Pos                       11                                                        /*!< SGPIO STATUS_1: STATUS_CCI11 Position */
-#define SGPIO_STATUS_1_STATUS_CCI11_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI11_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI11 Mask   */
-#define SGPIO_STATUS_1_STATUS_CCI12_Pos                       12                                                        /*!< SGPIO STATUS_1: STATUS_CCI12 Position */
-#define SGPIO_STATUS_1_STATUS_CCI12_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI12_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI12 Mask   */
-#define SGPIO_STATUS_1_STATUS_CCI13_Pos                       13                                                        /*!< SGPIO STATUS_1: STATUS_CCI13 Position */
-#define SGPIO_STATUS_1_STATUS_CCI13_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI13_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI13 Mask   */
-#define SGPIO_STATUS_1_STATUS_CCI14_Pos                       14                                                        /*!< SGPIO STATUS_1: STATUS_CCI14 Position */
-#define SGPIO_STATUS_1_STATUS_CCI14_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI14_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI14 Mask   */
-#define SGPIO_STATUS_1_STATUS_CCI15_Pos                       15                                                        /*!< SGPIO STATUS_1: STATUS_CCI15 Position */
-#define SGPIO_STATUS_1_STATUS_CCI15_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI15_Pos)               /*!< SGPIO STATUS_1: STATUS_CCI15 Mask   */
-
-// -----------------------------------  SGPIO_CTR_STATUS_1  ---------------------------------------
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos)        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Mask */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Position */
-#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos)       /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Mask */
-
-// -----------------------------------  SGPIO_SET_STATUS_1  ---------------------------------------
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos                0                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos                1                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos                2                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos                3                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos                4                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos                5                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos                6                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos                7                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos                8                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos                9                                                         /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos)        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos               10                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos               11                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos               12                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos               13                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos               14                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Mask */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos               15                                                        /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Position */
-#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos)       /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Mask */
-
-// -------------------------------------  SGPIO_CLR_EN_2  -----------------------------------------
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos                       0                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos                       1                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos                       2                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos                       3                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos                       4                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos                       5                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos                       6                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos                       7                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos                       8                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos                       9                                                         /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos)               /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Mask   */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos                      10                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Mask  */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos                      11                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Mask  */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos                      12                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Mask  */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos                      13                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Mask  */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos                      14                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Mask  */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos                      15                                                        /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Position */
-#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos)              /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Mask  */
-
-// -------------------------------------  SGPIO_SET_EN_2  -----------------------------------------
-#define SGPIO_SET_EN_2_SET_EN_PMI0_Pos                        0                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI0 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI0_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI0_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI0 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI1_Pos                        1                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI1 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI1_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI1_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI1 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI2_Pos                        2                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI2 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI2_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI2_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI2 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI3_Pos                        3                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI3 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI3_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI3_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI3 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI4_Pos                        4                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI4 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI4_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI4_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI4 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI5_Pos                        5                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI5 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI5_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI5_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI5 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI6_Pos                        6                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI6 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI6_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI6_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI6 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI7_Pos                        7                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI7 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI7_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI7_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI7 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI8_Pos                        8                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI8 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI8_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI8_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI8 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI9_Pos                        9                                                         /*!< SGPIO SET_EN_2: SET_EN_PMI9 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI9_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI9_Pos)                /*!< SGPIO SET_EN_2: SET_EN_PMI9 Mask    */
-#define SGPIO_SET_EN_2_SET_EN_PMI10_Pos                       10                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI10 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI10_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI10_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI10 Mask   */
-#define SGPIO_SET_EN_2_SET_EN_PMI11_Pos                       11                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI11 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI11_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI11_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI11 Mask   */
-#define SGPIO_SET_EN_2_SET_EN_PMI12_Pos                       12                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI12 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI12_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI12_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI12 Mask   */
-#define SGPIO_SET_EN_2_SET_EN_PMI13_Pos                       13                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI13 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI13_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI13_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI13 Mask   */
-#define SGPIO_SET_EN_2_SET_EN_PMI14_Pos                       14                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI14 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI14_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI14_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI14 Mask   */
-#define SGPIO_SET_EN_2_SET_EN_PMI15_Pos                       15                                                        /*!< SGPIO SET_EN_2: SET_EN_PMI15 Position */
-#define SGPIO_SET_EN_2_SET_EN_PMI15_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI15_Pos)               /*!< SGPIO SET_EN_2: SET_EN_PMI15 Mask   */
-
-// -------------------------------------  SGPIO_ENABLE_2  -----------------------------------------
-#define SGPIO_ENABLE_2_ENABLE_PMI0_Pos                        0                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI0 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI0_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI0_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI0 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI1_Pos                        1                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI1 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI1_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI1_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI1 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI2_Pos                        2                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI2 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI2_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI2_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI2 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI3_Pos                        3                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI3 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI3_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI3_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI3 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI4_Pos                        4                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI4 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI4_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI4_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI4 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI5_Pos                        5                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI5 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI5_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI5_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI5 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI6_Pos                        6                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI6 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI6_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI6_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI6 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI7_Pos                        7                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI7 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI7_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI7_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI7 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI8_Pos                        8                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI8 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI8_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI8_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI8 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI9_Pos                        9                                                         /*!< SGPIO ENABLE_2: ENABLE_PMI9 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI9_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI9_Pos)                /*!< SGPIO ENABLE_2: ENABLE_PMI9 Mask    */
-#define SGPIO_ENABLE_2_ENABLE_PMI10_Pos                       10                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI10 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI10_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI10_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI10 Mask   */
-#define SGPIO_ENABLE_2_ENABLE_PMI11_Pos                       11                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI11 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI11_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI11_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI11 Mask   */
-#define SGPIO_ENABLE_2_ENABLE_PMI12_Pos                       12                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI12 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI12_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI12_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI12 Mask   */
-#define SGPIO_ENABLE_2_ENABLE_PMI13_Pos                       13                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI13 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI13_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI13_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI13 Mask   */
-#define SGPIO_ENABLE_2_ENABLE_PMI14_Pos                       14                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI14 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI14_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI14_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI14 Mask   */
-#define SGPIO_ENABLE_2_ENABLE_PMI15_Pos                       15                                                        /*!< SGPIO ENABLE_2: ENABLE_PMI15 Position */
-#define SGPIO_ENABLE_2_ENABLE_PMI15_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI15_Pos)               /*!< SGPIO ENABLE_2: ENABLE_PMI15 Mask   */
-
-// -------------------------------------  SGPIO_STATUS_2  -----------------------------------------
-#define SGPIO_STATUS_2_STATUS_PMI0_Pos                        0                                                         /*!< SGPIO STATUS_2: STATUS_PMI0 Position */
-#define SGPIO_STATUS_2_STATUS_PMI0_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI0_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI0 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI1_Pos                        1                                                         /*!< SGPIO STATUS_2: STATUS_PMI1 Position */
-#define SGPIO_STATUS_2_STATUS_PMI1_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI1_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI1 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI2_Pos                        2                                                         /*!< SGPIO STATUS_2: STATUS_PMI2 Position */
-#define SGPIO_STATUS_2_STATUS_PMI2_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI2_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI2 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI3_Pos                        3                                                         /*!< SGPIO STATUS_2: STATUS_PMI3 Position */
-#define SGPIO_STATUS_2_STATUS_PMI3_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI3_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI3 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI4_Pos                        4                                                         /*!< SGPIO STATUS_2: STATUS_PMI4 Position */
-#define SGPIO_STATUS_2_STATUS_PMI4_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI4_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI4 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI5_Pos                        5                                                         /*!< SGPIO STATUS_2: STATUS_PMI5 Position */
-#define SGPIO_STATUS_2_STATUS_PMI5_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI5_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI5 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI6_Pos                        6                                                         /*!< SGPIO STATUS_2: STATUS_PMI6 Position */
-#define SGPIO_STATUS_2_STATUS_PMI6_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI6_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI6 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI7_Pos                        7                                                         /*!< SGPIO STATUS_2: STATUS_PMI7 Position */
-#define SGPIO_STATUS_2_STATUS_PMI7_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI7_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI7 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI8_Pos                        8                                                         /*!< SGPIO STATUS_2: STATUS_PMI8 Position */
-#define SGPIO_STATUS_2_STATUS_PMI8_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI8_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI8 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI9_Pos                        9                                                         /*!< SGPIO STATUS_2: STATUS_PMI9 Position */
-#define SGPIO_STATUS_2_STATUS_PMI9_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI9_Pos)                /*!< SGPIO STATUS_2: STATUS_PMI9 Mask    */
-#define SGPIO_STATUS_2_STATUS_PMI10_Pos                       10                                                        /*!< SGPIO STATUS_2: STATUS_PMI10 Position */
-#define SGPIO_STATUS_2_STATUS_PMI10_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI10_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI10 Mask   */
-#define SGPIO_STATUS_2_STATUS_PMI11_Pos                       11                                                        /*!< SGPIO STATUS_2: STATUS_PMI11 Position */
-#define SGPIO_STATUS_2_STATUS_PMI11_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI11_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI11 Mask   */
-#define SGPIO_STATUS_2_STATUS_PMI12_Pos                       12                                                        /*!< SGPIO STATUS_2: STATUS_PMI12 Position */
-#define SGPIO_STATUS_2_STATUS_PMI12_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI12_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI12 Mask   */
-#define SGPIO_STATUS_2_STATUS_PMI13_Pos                       13                                                        /*!< SGPIO STATUS_2: STATUS_PMI13 Position */
-#define SGPIO_STATUS_2_STATUS_PMI13_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI13_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI13 Mask   */
-#define SGPIO_STATUS_2_STATUS_PMI14_Pos                       14                                                        /*!< SGPIO STATUS_2: STATUS_PMI14 Position */
-#define SGPIO_STATUS_2_STATUS_PMI14_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI14_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI14 Mask   */
-#define SGPIO_STATUS_2_STATUS_PMI15_Pos                       15                                                        /*!< SGPIO STATUS_2: STATUS_PMI15 Position */
-#define SGPIO_STATUS_2_STATUS_PMI15_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI15_Pos)               /*!< SGPIO STATUS_2: STATUS_PMI15 Mask   */
-
-// -----------------------------------  SGPIO_CTR_STATUS_2  ---------------------------------------
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos                0                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos                1                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos                2                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos                3                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos                4                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos                5                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos                6                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos                7                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos                8                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos                9                                                         /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos)        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos               10                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos               11                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos               12                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos               13                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos               14                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Mask */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos               15                                                        /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Position */
-#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos)       /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Mask */
-
-// -----------------------------------  SGPIO_SET_STATUS_2  ---------------------------------------
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos                0                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos                1                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos                2                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos                3                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos                4                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos                5                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos                6                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos                7                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos                8                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos                9                                                         /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos)        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos               10                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos               11                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos               12                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos               13                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos               14                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Mask */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos               15                                                        /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Position */
-#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos)       /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Mask */
-
-// -------------------------------------  SGPIO_CLR_EN_3  -----------------------------------------
-#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos                       0                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos                       1                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos                       2                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos                       3                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos                       4                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos                       5                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos                       6                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos                       7                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos                       8                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos                       9                                                         /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos)               /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Mask   */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos                      10                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Mask  */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos                      11                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Mask  */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos                      12                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Mask  */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos                      13                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Mask  */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos                      14                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Mask  */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos                      15                                                        /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Position */
-#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos)              /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Mask  */
-
-// -------------------------------------  SGPIO_SET_EN_3  -----------------------------------------
-#define SGPIO_SET_EN_3_SET_EN_INPI0_Pos                       0                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI0 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI0_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI0_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI0 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI1_Pos                       1                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI1 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI1_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI1_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI1 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI2_Pos                       2                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI2 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI2_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI2_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI2 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI3_Pos                       3                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI3 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI3_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI3_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI3 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI4_Pos                       4                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI4 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI4_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI4_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI4 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI5_Pos                       5                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI5 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI5_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI5_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI5 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI6_Pos                       6                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI6 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI6_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI6_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI6 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI7_Pos                       7                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI7 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI7_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI7_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI7 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI8_Pos                       8                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI8 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI8_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI8_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI8 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI9_Pos                       9                                                         /*!< SGPIO SET_EN_3: SET_EN_INPI9 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI9_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI9_Pos)               /*!< SGPIO SET_EN_3: SET_EN_INPI9 Mask   */
-#define SGPIO_SET_EN_3_SET_EN_INPI10_Pos                      10                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI10 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI10_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI10_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI10 Mask  */
-#define SGPIO_SET_EN_3_SET_EN_INPI11_Pos                      11                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI11 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI11_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI11_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI11 Mask  */
-#define SGPIO_SET_EN_3_SET_EN_INPI12_Pos                      12                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI12 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI12_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI12_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI12 Mask  */
-#define SGPIO_SET_EN_3_SET_EN_INPI13_Pos                      13                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI13 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI13_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI13_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI13 Mask  */
-#define SGPIO_SET_EN_3_SET_EN_INPI14_Pos                      14                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI14 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI14_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI14_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI14 Mask  */
-#define SGPIO_SET_EN_3_SET_EN_INPI15_Pos                      15                                                        /*!< SGPIO SET_EN_3: SET_EN_INPI15 Position */
-#define SGPIO_SET_EN_3_SET_EN_INPI15_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI15_Pos)              /*!< SGPIO SET_EN_3: SET_EN_INPI15 Mask  */
-
-// -------------------------------------  SGPIO_ENABLE_3  -----------------------------------------
-#define SGPIO_ENABLE_3_ENABLE3_INPI0_Pos                      0                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI0_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI0_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI1_Pos                      1                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI1_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI1_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI2_Pos                      2                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI2_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI2_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI3_Pos                      3                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI3_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI3_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI4_Pos                      4                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI4_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI4_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI5_Pos                      5                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI5_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI5_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI6_Pos                      6                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI6_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI6_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI7_Pos                      7                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI7_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI7_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI8_Pos                      8                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI8_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI8_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI9_Pos                      9                                                         /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI9_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI9_Pos)              /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Mask  */
-#define SGPIO_ENABLE_3_ENABLE3_INPI10_Pos                     10                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI10_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI10_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Mask */
-#define SGPIO_ENABLE_3_ENABLE3_INPI11_Pos                     11                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI11_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI11_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Mask */
-#define SGPIO_ENABLE_3_ENABLE3_INPI12_Pos                     12                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI12_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI12_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Mask */
-#define SGPIO_ENABLE_3_ENABLE3_INPI13_Pos                     13                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI13_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI13_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Mask */
-#define SGPIO_ENABLE_3_ENABLE3_INPI14_Pos                     14                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI14_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI14_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Mask */
-#define SGPIO_ENABLE_3_ENABLE3_INPI15_Pos                     15                                                        /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Position */
-#define SGPIO_ENABLE_3_ENABLE3_INPI15_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI15_Pos)             /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Mask */
-
-// -------------------------------------  SGPIO_STATUS_3  -----------------------------------------
-#define SGPIO_STATUS_3_STATUS_INPI0_Pos                       0                                                         /*!< SGPIO STATUS_3: STATUS_INPI0 Position */
-#define SGPIO_STATUS_3_STATUS_INPI0_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI0_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI0 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI1_Pos                       1                                                         /*!< SGPIO STATUS_3: STATUS_INPI1 Position */
-#define SGPIO_STATUS_3_STATUS_INPI1_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI1_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI1 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI2_Pos                       2                                                         /*!< SGPIO STATUS_3: STATUS_INPI2 Position */
-#define SGPIO_STATUS_3_STATUS_INPI2_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI2_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI2 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI3_Pos                       3                                                         /*!< SGPIO STATUS_3: STATUS_INPI3 Position */
-#define SGPIO_STATUS_3_STATUS_INPI3_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI3_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI3 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI4_Pos                       4                                                         /*!< SGPIO STATUS_3: STATUS_INPI4 Position */
-#define SGPIO_STATUS_3_STATUS_INPI4_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI4_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI4 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI5_Pos                       5                                                         /*!< SGPIO STATUS_3: STATUS_INPI5 Position */
-#define SGPIO_STATUS_3_STATUS_INPI5_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI5_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI5 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI6_Pos                       6                                                         /*!< SGPIO STATUS_3: STATUS_INPI6 Position */
-#define SGPIO_STATUS_3_STATUS_INPI6_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI6_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI6 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI7_Pos                       7                                                         /*!< SGPIO STATUS_3: STATUS_INPI7 Position */
-#define SGPIO_STATUS_3_STATUS_INPI7_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI7_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI7 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI8_Pos                       8                                                         /*!< SGPIO STATUS_3: STATUS_INPI8 Position */
-#define SGPIO_STATUS_3_STATUS_INPI8_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI8_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI8 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI9_Pos                       9                                                         /*!< SGPIO STATUS_3: STATUS_INPI9 Position */
-#define SGPIO_STATUS_3_STATUS_INPI9_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI9_Pos)               /*!< SGPIO STATUS_3: STATUS_INPI9 Mask   */
-#define SGPIO_STATUS_3_STATUS_INPI10_Pos                      10                                                        /*!< SGPIO STATUS_3: STATUS_INPI10 Position */
-#define SGPIO_STATUS_3_STATUS_INPI10_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI10_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI10 Mask  */
-#define SGPIO_STATUS_3_STATUS_INPI11_Pos                      11                                                        /*!< SGPIO STATUS_3: STATUS_INPI11 Position */
-#define SGPIO_STATUS_3_STATUS_INPI11_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI11_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI11 Mask  */
-#define SGPIO_STATUS_3_STATUS_INPI12_Pos                      12                                                        /*!< SGPIO STATUS_3: STATUS_INPI12 Position */
-#define SGPIO_STATUS_3_STATUS_INPI12_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI12_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI12 Mask  */
-#define SGPIO_STATUS_3_STATUS_INPI13_Pos                      13                                                        /*!< SGPIO STATUS_3: STATUS_INPI13 Position */
-#define SGPIO_STATUS_3_STATUS_INPI13_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI13_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI13 Mask  */
-#define SGPIO_STATUS_3_STATUS_INPI14_Pos                      14                                                        /*!< SGPIO STATUS_3: STATUS_INPI14 Position */
-#define SGPIO_STATUS_3_STATUS_INPI14_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI14_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI14 Mask  */
-#define SGPIO_STATUS_3_STATUS_INPI15_Pos                      15                                                        /*!< SGPIO STATUS_3: STATUS_INPI15 Position */
-#define SGPIO_STATUS_3_STATUS_INPI15_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI15_Pos)              /*!< SGPIO STATUS_3: STATUS_INPI15 Mask  */
-
-// -----------------------------------  SGPIO_CTR_STATUS_3  ---------------------------------------
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos               0                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos               1                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos               2                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos               3                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos               4                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos               5                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos               6                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos               7                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos               8                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos               9                                                         /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos)       /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos              10                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos              11                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos              12                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos              13                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos              14                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Mask */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos              15                                                        /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Position */
-#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos)      /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Mask */
-
-// -----------------------------------  SGPIO_SET_STATUS_3  ---------------------------------------
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos               0                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos               1                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos               2                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos               3                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos               4                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos               5                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos               6                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos               7                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos               8                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos               9                                                         /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos)       /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos              10                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos              11                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos              12                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos              13                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos              14                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Mask */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos              15                                                        /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Position */
-#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos)      /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Mask */
-
-#endif
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 Peripheral memory map                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_SCT_BASE              0x40000000
-#define LPC_GPDMA_BASE            0x40002000
-#define LPC_SDMMC_BASE            0x40004000
-#define LPC_EMC_BASE              0x40005000
-#define LPC_USB0_BASE             0x40006000
-#define LPC_USB1_BASE             0x40007000
-#define LPC_LCD_BASE              0x40008000
-#define LPC_ETHERNET_BASE         0x40010000
-#define LPC_ATIMER_BASE           0x40040000
-#define LPC_REGFILE_BASE          0x40041000
-#define LPC_PMC_BASE              0x40042000
-#define LPC_CREG_BASE             0x40043000
-#define LPC_EVENTROUTER_BASE      0x40044000
-#define LPC_RTC_BASE              0x40046000
-#define LPC_CGU_BASE              0x40050000
-#define LPC_CCU1_BASE             0x40051000
-#define LPC_CCU2_BASE             0x40052000
-#define LPC_RGU_BASE              0x40053000
-#define LPC_WWDT_BASE             0x40080000
-#define LPC_USART0_BASE           0x40081000
-#define LPC_USART2_BASE           0x400C1000
-#define LPC_USART3_BASE           0x400C2000
-#define LPC_UART1_BASE            0x40082000
-#define LPC_SSP0_BASE             0x40083000
-#define LPC_SSP1_BASE             0x400C5000
-#define LPC_TIMER0_BASE           0x40084000
-#define LPC_TIMER1_BASE           0x40085000
-#define LPC_TIMER2_BASE           0x400C3000
-#define LPC_TIMER3_BASE           0x400C4000
-#define LPC_SCU_BASE              0x40086000
-#define LPC_GPIO_PIN_INT_BASE     0x40087000
-#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
-#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
-#define LPC_MCPWM_BASE            0x400A0000
-#define LPC_I2C0_BASE             0x400A1000
-#define LPC_I2C1_BASE             0x400E0000
-#define LPC_I2S0_BASE             0x400A2000
-#define LPC_I2S1_BASE             0x400A3000
-#define LPC_C_CAN1_BASE           0x400A4000
-#define LPC_RITIMER_BASE          0x400C0000
-#define LPC_QEI_BASE              0x400C6000
-#define LPC_GIMA_BASE             0x400C7000
-#define LPC_DAC_BASE              0x400E1000
-#define LPC_C_CAN0_BASE           0x400E2000
-#define LPC_ADC0_BASE             0x400E3000
-#define LPC_ADC1_BASE             0x400E4000
-#define LPC_GPIO_PORT_BASE        0x400F4000
-#define LPC_SPI_BASE              0x40100000
-#define LPC_SGPIO_BASE            0x40101000
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                Peripheral declaration                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_SCT                   ((LPC_SCT_Type            *) LPC_SCT_BASE)
-#define LPC_GPDMA                 ((LPC_GPDMA_Type          *) LPC_GPDMA_BASE)
-#define LPC_SDMMC                 ((LPC_SDMMC_Type          *) LPC_SDMMC_BASE)
-#define LPC_EMC                   ((LPC_EMC_Type            *) LPC_EMC_BASE)
-#define LPC_USB0                  ((LPC_USB0_Type           *) LPC_USB0_BASE)
-#define LPC_USB1                  ((LPC_USB1_Type           *) LPC_USB1_BASE)
-#define LPC_LCD                   ((LPC_LCD_Type            *) LPC_LCD_BASE)
-#define LPC_ETHERNET              ((LPC_ETHERNET_Type       *) LPC_ETHERNET_BASE)
-#define LPC_ATIMER                ((LPC_ATIMER_Type         *) LPC_ATIMER_BASE)
-#define LPC_REGFILE               ((LPC_REGFILE_Type        *) LPC_REGFILE_BASE)
-#define LPC_PMC                   ((LPC_PMC_Type            *) LPC_PMC_BASE)
-#define LPC_CREG                  ((LPC_CREG_Type           *) LPC_CREG_BASE)
-#define LPC_EVENTROUTER           ((LPC_EVENTROUTER_Type    *) LPC_EVENTROUTER_BASE)
-#define LPC_RTC                   ((LPC_RTC_Type            *) LPC_RTC_BASE)
-#define LPC_CGU                   ((LPC_CGU_Type            *) LPC_CGU_BASE)
-#define LPC_CCU1                  ((LPC_CCU1_Type           *) LPC_CCU1_BASE)
-#define LPC_CCU2                  ((LPC_CCU2_Type           *) LPC_CCU2_BASE)
-#define LPC_RGU                   ((LPC_RGU_Type            *) LPC_RGU_BASE)
-#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
-#define LPC_USART0                ((LPC_USARTn_Type         *) LPC_USART0_BASE)
-#define LPC_USART2                ((LPC_USARTn_Type         *) LPC_USART2_BASE)
-#define LPC_USART3                ((LPC_USARTn_Type         *) LPC_USART3_BASE)
-#define LPC_UART1                 ((LPC_UART1_Type          *) LPC_UART1_BASE)
-#define LPC_SSP0                  ((LPC_SSPn_Type           *) LPC_SSP0_BASE)
-#define LPC_SSP1                  ((LPC_SSPn_Type           *) LPC_SSP1_BASE)
-#define LPC_TIMER0                ((LPC_TIMERn_Type         *) LPC_TIMER0_BASE)
-#define LPC_TIMER1                ((LPC_TIMERn_Type         *) LPC_TIMER1_BASE)
-#define LPC_TIMER2                ((LPC_TIMERn_Type         *) LPC_TIMER2_BASE)
-#define LPC_TIMER3                ((LPC_TIMERn_Type         *) LPC_TIMER3_BASE)
-#define LPC_SCU                   ((LPC_SCU_Type            *) LPC_SCU_BASE)
-#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_MCPWM                 ((LPC_MCPWM_Type          *) LPC_MCPWM_BASE)
-#define LPC_I2C0                  ((LPC_I2Cn_Type           *) LPC_I2C0_BASE)
-#define LPC_I2C1                  ((LPC_I2Cn_Type           *) LPC_I2C1_BASE)
-#define LPC_I2S0                  ((LPC_I2Sn_Type           *) LPC_I2S0_BASE)
-#define LPC_I2S1                  ((LPC_I2Sn_Type           *) LPC_I2S1_BASE)
-#define LPC_C_CAN1                ((LPC_C_CANn_Type         *) LPC_C_CAN1_BASE)
-#define LPC_RITIMER               ((LPC_RITIMER_Type        *) LPC_RITIMER_BASE)
-#define LPC_QEI                   ((LPC_QEI_Type            *) LPC_QEI_BASE)
-#define LPC_GIMA                  ((LPC_GIMA_Type           *) LPC_GIMA_BASE)
-#define LPC_DAC                   ((LPC_DAC_Type            *) LPC_DAC_BASE)
-#define LPC_C_CAN0                ((LPC_C_CANn_Type         *) LPC_C_CAN0_BASE)
-#define LPC_ADC0                  ((LPC_ADCn_Type           *) LPC_ADC0_BASE)
-#define LPC_ADC1                  ((LPC_ADCn_Type           *) LPC_ADC1_BASE)
-#define LPC_GPIO_PORT             ((LPC_GPIO_PORT_Type      *) LPC_GPIO_PORT_BASE)
-#define LPC_SPI                   ((LPC_SPI_Type            *) LPC_SPI_BASE)
-#define LPC_SGPIO                 ((LPC_SGPIO_Type          *) LPC_SGPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group LPC43xx */
-/** @} */ /* End of group (null) */
-
-#ifdef __cplusplus
-}
-#endif 
-
-
-#endif  // __LPC43xx_H__
-
diff --git a/os/hal/platforms/LPC43xx/dac_lld.c b/os/hal/platforms/LPC43xx/dac_lld.c
deleted file mode 100644
index cff431fdf..000000000
--- a/os/hal/platforms/LPC43xx/dac_lld.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC43xx DAC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/dac_lld.c
- * @brief   LPC43xx DAC subsystem low level driver source.
- *
- * @addtogroup DAC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief CHN1 driver identifier.*/
-DACDriver DACD1;
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-static lpc_dma_lli_config_t lpc_dac_lli[2] __attribute__((aligned(0x10)));
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-
-/**
- * @brief   Shared end/half-of-tx service routine.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void dac_serve_dma_interrupt(DACDriver *dacp, uint32_t flags) {
-
-  if ((flags & (1 << LPC_DAC_DMA_CHANNEL)) != 0) {
-    _dac_isr_error_code(dacp, flags);  /* DMA errors handling.*/
-  }
-  else {
-    if (dacp->half_buffer == false) {
-      _dac_isr_half_code(dacp);
-      dacp->half_buffer = true;
-    }
-    else {
-      _dac_isr_full_code(dacp);
-      dacp->half_buffer = false;
-    }
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level DAC driver initialization.
- *
- * @notapi
- */
-void dac_lld_init(void) {
-  dacObjectInit(&DACD1);
-}
-
-/**
- * @brief   Configures and activates the DAC peripheral.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_start(DACDriver *dacp) {
-
-  if (dacp->state == DAC_STOP) {
-
-    LPC_CCU1->CLK_APB3_DAC_CFG = 1;     /* Enable clock. */
-    LPC_DAC->CR = 0;
-    LPC_DAC->CTRL = 0;
-    LPC_DAC->CNTVAL = LPC_BASE_APB3_CLK/dacp->config->frequency;
-
-    dmaMuxSet(PERIPHERAL15, 0);
-    dmaChannelAllocate(LPC_DAC_DMA_CHANNEL, \
-                     (lpc_dmaisr_t)dac_serve_dma_interrupt, \
-                     (void *)dacp);
-
-  }
-}
-
-/**
- * @brief   Deactivates the DAC peripheral.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_stop(DACDriver *dacp) {
-
-  /* If in ready state then disables the DAC clock.*/
-  if (dacp->state == DAC_READY) {
-
-    /* DMA disable.*/
-    dmaChannelDisable(LPC_DAC_DMA_CHANNEL);
-    dmaChannelRelease(LPC_DAC_DMA_CHANNEL);
-
-    LPC_DAC->CTRL = 0;                  /* Disable DAC */
-    LPC_CCU1->CLK_APB3_DAC_CFG = 0;     /* Disable clock. */
-  }
-}
-
-/**
- * @brief   Sends data over the DAC bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void dac_lld_start_conversion(DACDriver *dacp) {
-
-  dacp->half_buffer  = false;
-  uint32_t dma_ch_config;
-
-  /* DMA configuration */
-  lpc_dac_lli[0].srcaddr = (uint32_t) &dacp->samples[0];
-  lpc_dac_lli[0].dstaddr = (uint32_t)&LPC_DAC->CR;
-  lpc_dac_lli[0].lli = (uint32_t) &lpc_dac_lli[1];
-  lpc_dac_lli[0].control =
-    DMA_CTRL_TRANSFER_SIZE(dacp->depth/2)                   |
-    DMA_CTRL_SRC_BSIZE_1                                    |
-    DMA_CTRL_DST_BSIZE_1                                    |
-    DMA_CTRL_SRC_WIDTH_WORD                                 |
-    DMA_CTRL_DST_WIDTH_WORD                                 |
-    DMA_CTRL_SRC_AHBM0                                      |
-    DMA_CTRL_DST_AHBM1                                      |
-    DMA_CTRL_SRC_INC                                        |
-    DMA_CTRL_DST_NOINC                                      |
-    DMA_CTRL_PROT1_USER                                     |
-    DMA_CTRL_PROT2_NONBUFF                                  |
-    DMA_CTRL_PROT3_NONCACHE                                 |
-    DMA_CTRL_INT;
-
-  lpc_dac_lli[1].srcaddr = (uint32_t) &dacp->samples[dacp->depth/2];
-  lpc_dac_lli[1].dstaddr = lpc_dac_lli[0].dstaddr;
-  lpc_dac_lli[1].control = lpc_dac_lli[0].control;
-
-  if (dacp->grpp->circular == true) {
-    lpc_dac_lli[1].lli = (uint32_t) &lpc_dac_lli[0];
-  }
-  else {
-    lpc_dac_lli[1].lli = 0;
-  }
-
-  dma_ch_config =
-    DMA_CFG_CH_ENABLE                |
-    DMA_CFG_DST_PERIPH(PERIPHERAL15) |
-    DMA_CFG_FCTRL_M2P                |
-    DMA_CFG_IE                       |
-    DMA_CFG_ITC;
-
-  dmaChannelSrcAddr(LPC_DAC_DMA_CHANNEL, lpc_dac_lli[0].srcaddr);
-  dmaChannelDstAddr(LPC_DAC_DMA_CHANNEL, lpc_dac_lli[0].dstaddr);
-  dmaChannelLinkedList(LPC_DAC_DMA_CHANNEL, lpc_dac_lli[0].lli, DMA_LLI_AHBM0);
-  dmaChannelControl(LPC_DAC_DMA_CHANNEL, lpc_dac_lli[0].control);
-  dmaChannelConfig(LPC_DAC_DMA_CHANNEL, dma_ch_config);
-
-  LPC_DAC->CTRL = DACCTRL_DMA_ENA | DACCTRL_CNT_ENA | DACCTRL_DBLBUF_ENA;
-}
-
-void dac_lld_stop_conversion(DACDriver *dacp) {
-
-  /* If in active state then disables the DAC.*/
-  if (dacp->state == DAC_ACTIVE) {
-
-    /* DMA disable.*/
-    dmaChannelDisable(LPC_DAC_DMA_CHANNEL);
-  }
-};
-
-#endif /* HAL_USE_DAC */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/dac_lld.h b/os/hal/platforms/LPC43xx/dac_lld.h
deleted file mode 100644
index 8b1b3ffcc..000000000
--- a/os/hal/platforms/LPC43xx/dac_lld.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC43xx DAC driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/dac_lld.h
- * @brief   LPC43xx DAC subsystem low level driver header.
- *
- * @addtogroup DAC
- * @{
- */
-
-#ifndef _DAC_LLD_H_
-#define _DAC_LLD_H_
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define DACR_BIAS                   (1UL << 16)
-
-#define DACCTRL_INT_DMA_REQ         (1UL << 0)
-#define DACCTRL_DBLBUF_ENA          (1UL << 1)
-#define DACCTRL_CNT_ENA             (1UL << 2)
-#define DACCTRL_DMA_ENA             (1UL << 3)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-
-/**
- * @brief   DMA stream used for DAC CHN1 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(LPC_DAC_DMA_CHANNEL) || defined(__DOXYGEN__)
-#define LPC_DAC_DMA_CHANNEL             DMA_CHANNEL5
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !defined(LPC_DMA_REQUIRED)
-#define LPC_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an DAC driver.
- */
-typedef struct DACDriver DACDriver;
-
-/**
- * @brief   Type representing a DAC sample.
- */
-typedef uint32_t dacsample_t;
-
-/**
- * @brief   DAC notification callback type.
- *
- * @param[in] dacp      pointer to the @p DACDriver object triggering the
- *                      callback
- */
-typedef void (*dacendcallback_t)(DACDriver *dacp, const dacsample_t * samples, size_t pos);
-
-/**
- * @brief   DAC notification callback type.
- *
- * @param[in] dacp      pointer to the @p DACDriver object triggering the
- *                      callback
- */
-typedef void (*dacerrcallback_t)(DACDriver *dacp, uint32_t flags);
-
-/**
- * @brief   DAC Conversion group structure.
- */
-typedef struct {
-  /**
-   * @brief Number of DAC channels.
-   */
-  uint16_t              num_channels;
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  dacendcallback_t     end_cb;
-  /**
-   * @brief Error handling callback or @p NULL.
-   */
-  dacerrcallback_t      error_cb;
-  /**
-   * @brief Error handling callback or @p NULL.
-   */
-  bool      circular;
-
-} DACConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   Timer frequency in Hz.
-   */
-  uint32_t                  frequency;
-  /* End of the mandatory fields.*/
-} DACConfig;
-
-/**
- * @brief   Structure representing a DAC driver.
- */
-struct DACDriver {
-  /**
-   * @brief Driver state.
-   */
-  dacstate_t                state;
-  /**
-   * @brief Conversion group.
-   */
-  const DACConversionGroup *grpp;
-  /**
-   * @brief Samples buffer pointer.
-   */
-  const dacsample_t *samples;
-  /**
-   * @brief Samples buffer size.
-   */
-  uint16_t depth;
-  /**
-   * @brief Current configuration data.
-   */
-  const DACConfig           *config;
-#if DAC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif /* DAC_USE_WAIT */
-#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* DAC_USE_MUTUAL_EXCLUSION */
-#if defined(DAC_DRIVER_EXT_FIELDS)
-  DAC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Half buffer indicator.
-   */
-  bool_t                    half_buffer;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-extern DACDriver DACD1;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dac_lld_init(void);
-  void dac_lld_start(DACDriver *dacp);
-  void dac_lld_stop(DACDriver *dacp);
-  void dac_lld_start_conversion(DACDriver *dacp);
-  void dac_lld_stop_conversion(DACDriver *dacp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_DAC */
-
-#endif /* _DAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/gpt_lld.c b/os/hal/platforms/LPC43xx/gpt_lld.c
deleted file mode 100644
index e9789e871..000000000
--- a/os/hal/platforms/LPC43xx/gpt_lld.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/gpt_lld.c
- * @brief   LPC43xx GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver identifier.
- * @note    The driver GPT1 allocates the complex timer TIM0 when enabled.
- */
-#if LPC_GPT_USE_TIM0 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief   GPT2 driver identifier.
- * @note    The driver GPT2 allocates the timer TIM1 when enabled.
- */
-#if LPC_GPT_USE_TIM1 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief   GPT3 driver identifier.
- * @note    The driver GPT3 allocates the timer TIM2 when enabled.
- */
-#if LPC_GPT_USE_TIM2 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/**
- * @brief   GPT4 driver identifier.
- * @note    The driver GPT4 allocates the timer TIM3 when enabled.
- */
-#if LPC_GPT_USE_TIM3 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
-  gptp->tmr->IR = 1;                        /* Clear interrupt on match MR0.*/
-  if (gptp->state == GPT_ONESHOT) {
-    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
-    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
-  }
-  gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC_GPT_USE_TIM0
-/**
- * @brief   TIM0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector70) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC_GPT_USE_TIM0 */
-
-#if LPC_GPT_USE_TIM1
-/**
- * @brief   TIM1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector74) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC_GPT_USE_TIM0 */
-
-#if LPC_GPT_USE_TIM2
-/**
- * @brief   TIM2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector78) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC_GPT_USE_TIM2 */
-
-#if LPC_GPT_USE_TIM3
-/**
- * @brief   TIM3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector7C) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* LPC_GPT_USE_TIM3 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if LPC_GPT_USE_TIM0
-  /* Driver initialization.*/
-  GPTD1.tmr = LPC_TIMER0;
-  gptObjectInit(&GPTD1);
-#endif
-
-#if LPC_GPT_USE_TIM1
-  /* Driver initialization.*/
-  GPTD2.tmr = LPC_TIMER1;
-  gptObjectInit(&GPTD2);
-#endif
-
-#if LPC_GPT_USE_TIM2
-  /* Driver initialization.*/
-  GPTD3.tmr = LPC_TIMER2;
-  gptObjectInit(&GPTD3);
-#endif
-
-#if LPC_GPT_USE_TIM3
-  /* Driver initialization.*/
-  GPTD4.tmr = LPC_TIMER3;
-  gptObjectInit(&GPTD4);
-#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-  uint32_t pr;
-
-  if (gptp->state == GPT_STOP) {
-    /* Clock activation.*/
-#if LPC_GPT_USE_TIM0
-    if (&GPTD1 == gptp) {
-      LPC_CCU1->CLK_M4_TIMER0_CFG = 1;
-      nvicEnableVector(TIMER0_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC_GPT_USE_TIM1
-    if (&GPTD2 == gptp) {
-      LPC_CCU1->CLK_M4_TIMER1_CFG = 1;
-      nvicEnableVector(TIMER1_IRQn, CORTEX_PRIORITY_MASK(3));
-    }
-#endif
-#if LPC_GPT_USE_TIM2
-    if (&GPTD3 == gptp) {
-      LPC_CCU1->CLK_M4_TIMER2_CFG = 1;
-      nvicEnableVector(TIMER2_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-#if LPC_GPT_USE_TIM3
-    if (&GPTD4 == gptp) {
-      LPC_CCU1->CLK_M4_TIMER3_CFG = 1;
-      nvicEnableVector(TIMER3_IRQn, CORTEX_PRIORITY_MASK(2));
-    }
-#endif
-  }
-
-  /* Prescaler value calculation.*/
-  pr = (uint16_t)((LPC_BASE_M4_CLK/ gptp->config->frequency) - 1);
-  chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC_BASE_M4_CLK,
-              "gpt_lld_start(), #1", "invalid frequency");
-
-  /* Timer configuration.*/
-  gptp->tmr->PR  = pr;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
-  if (gptp->state == GPT_READY) {
-    gptp->tmr->MCR = 0;
-    gptp->tmr->TCR = 0;
-
-#if LPC_GPT_USE_TIM0
-    if (&GPTD1 == gptp) {
-      nvicDisableVector(TIMER0_IRQn);
-      LPC_CCU1->CLK_M4_TIMER0_CFG = 0;
-    }
-#endif
-#if LPC_GPT_USE_TIM1
-    if (&GPTD2 == gptp) {
-      nvicDisableVector(TIMER1_IRQn);
-      LPC_CCU1->CLK_M4_TIMER1_CFG = 0;
-    }
-#endif
-#if LPC_GPT_USE_TIM2
-    if (&GPTD3 == gptp) {
-      nvicDisableVector(TIMER2_IRQn);
-      LPC_CCU1->CLK_M4_TIMER2_CFG = 0;
-    }
-#endif
-#if LPC_GPT_USE_TIM3
-    if (&GPTD4 == gptp) {
-      nvicDisableVector(TIMER3_IRQn);
-      LPC_CCU1->CLK_M4_TIMER3_CFG = 0;
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR[0] = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 3;                       /* IRQ and clr TC on match MR0. */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 0;
-  gptp->tmr->TCR = 0;
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->MR[0] = interval - 1;
-  gptp->tmr->IR  = 1;
-  gptp->tmr->MCR = 4;                       /* Stop TC on match MR0.        */
-  gptp->tmr->TCR = 2;                       /* Reset counter and prescaler. */
-  gptp->tmr->TCR = 1;                       /* Timer enabled.               */
-  while (gptp->tmr->TCR & 1)
-    ;
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/gpt_lld.h b/os/hal/platforms/LPC43xx/gpt_lld.h
deleted file mode 100644
index 22e706ab3..000000000
--- a/os/hal/platforms/LPC43xx/gpt_lld.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/gpt_lld.h
- * @brief   LPC43xx GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver enable switch.
- * @details If set to @p TRUE the support for GPT1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_GPT_USE_TIM0) || defined(__DOXYGEN__)
-#define LPC_GPT_USE_TIM0              TRUE
-#endif
-
-/**
- * @brief   GPT2 driver enable switch.
- * @details If set to @p TRUE the support for GPT2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_GPT_USE_TIM1) || defined(__DOXYGEN__)
-#define LPC_GPT_USE_TIM1              TRUE
-#endif
-
-/**
- * @brief   GPT3 driver enable switch.
- * @details If set to @p TRUE the support for GPT3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_GPT_USE_TIM2) || defined(__DOXYGEN__)
-#define LPC_GPT_USE_TIM2              TRUE
-#endif
-
-/**
- * @brief   GPT4 driver enable switch.
- * @details If set to @p TRUE the support for GPT4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_GPT_USE_TIM3) || defined(__DOXYGEN__)
-#define LPC_GPT_USE_TIM3              TRUE
-#endif
-
-/**
- * @brief   GPT1 interrupt priority level setting.
- */
-#if !defined(LPC_GPT_TIM0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_GPT_TIM0_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT2 interrupt priority level setting.
- */
-#if !defined(LPC_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_GPT_TIM1_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT3 interrupt priority level setting.
- */
-#if !defined(LPC_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_GPT_TIM2_IRQ_PRIORITY     2
-#endif
-
-/**
- * @brief   GPT4 interrupt priority level setting.
- */
-#if !defined(LPC_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_GPT_TIM3_IRQ_PRIORITY     2
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !LPC_GPT_USE_TIM0 && !LPC_GPT_USE_TIM1 &&                   \
-    !LPC_GPT_USE_TIM2 && !LPC_GPT_USE_TIM3
-#error "GPT driver activated but no CT peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Timer base clock.
-   */
-  uint32_t                  clock;
-  /**
-   * @brief Pointer to the LPC_TIMERx registers block.
-   */
-  LPC_TIMERn_Type           *tmr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC_GPT_USE_TIM0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if LPC_GPT_USE_TIM1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if LPC_GPT_USE_TIM2 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#if LPC_GPT_USE_TIM3 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/hal_lld.c b/os/hal/platforms/LPC43xx/hal_lld.c
deleted file mode 100644
index bbf11b2a2..000000000
--- a/os/hal/platforms/LPC43xx/hal_lld.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC43xx HAL driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/hal_lld.c
- * @brief   LPC43xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/**
- * @brief   Register missing in NXP header file.
- */
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-#define LPC_IDIV_ARRAY_NUM            5
-#define LPC_BASE_CLK_ARRAY_NUM        27
-
-const uint32_t lpc_idiv[LPC_IDIV_ARRAY_NUM] = {
-  (((uint32_t)LPC_IDIVA_SRC) << 24) | (LPC_IDIVA_DIV << 2) | (!LPC_IDIVA_ENABLE),
-  (((uint32_t)LPC_IDIVB_SRC) << 24) | (LPC_IDIVB_DIV << 2) | (!LPC_IDIVB_ENABLE),
-  (((uint32_t)LPC_IDIVC_SRC) << 24) | (LPC_IDIVC_DIV << 2) | (!LPC_IDIVC_ENABLE),
-  (((uint32_t)LPC_IDIVD_SRC) << 24) | (LPC_IDIVD_DIV << 2) | (!LPC_IDIVD_ENABLE),
-  (((uint32_t)LPC_IDIVE_SRC) << 24) | (LPC_IDIVE_DIV << 2) | (!LPC_IDIVE_ENABLE)
-};
-
-const uint32_t lpc_base_clk[LPC_BASE_CLK_ARRAY_NUM] = {
-  (CLK_SEL_PLL0USB << 24) | (!LPC_BASE_USB0_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_PERIPH_CLK_SRC) << 24) | (!LPC_BASE_PERIPH_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_USB1_CLK_SRC) << 24) | (!LPC_BASE_USB1_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_M4_CLK_SRC) << 24) | (!LPC_BASE_M4_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_SPIFI_CLK_SRC) << 24) | (!LPC_BASE_SPIFI_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_SPI_CLK_SRC) << 24) | (!LPC_BASE_SPI_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_PHY_RX_CLK_SRC) << 24) | (!LPC_BASE_PHY_RX_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_PHY_TX_CLK_SRC) << 24) | (!LPC_BASE_PHY_TX_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_APB1_CLK_SRC) << 24) | (!LPC_BASE_APB1_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_APB3_CLK_SRC) << 24) | (!LPC_BASE_APB3_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_LCD_CLK_SRC) << 24) | (!LPC_BASE_LCD_CLK_ENABLE),
-  0,
-  (((uint32_t)LPC_BASE_SDIO_CLK_SRC) << 24) | (!LPC_BASE_SDIO_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_SSP0_CLK_SRC) << 24) | (!LPC_BASE_SSP0_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_SSP1_CLK_SRC) << 24) | (!LPC_BASE_SSP1_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_UART0_CLK_SRC) << 24) | (!LPC_BASE_UART0_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_UART1_CLK_SRC) << 24) | (!LPC_BASE_UART1_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_UART2_CLK_SRC) << 24) | (!LPC_BASE_UART2_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_UART3_CLK_SRC) << 24) | (!LPC_BASE_UART3_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_OUT_CLK_SRC) << 24) | (!LPC_BASE_OUT_CLK_ENABLE),
-  0,
-  0,
-  0,
-  0,
-  (((uint32_t)LPC_BASE_APLL_CLK_SRC) << 24) | (!LPC_BASE_APLL_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_CGU_OUT0_CLK_SRC) << 24) | (!LPC_BASE_CGU_OUT0_CLK_ENABLE),
-  (((uint32_t)LPC_BASE_CGU_OUT1_CLK_SRC) << 24) | (!LPC_BASE_CGU_OUT1_CLK_ENABLE)
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* SysTick initialization using the system clock.*/
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
-  SysTick->LOAD = LPC_BASE_M4_CLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-
-  /* DWT cycle counter enable.*/
-  SCS_DEMCR |= SCS_DEMCR_TRCENA;
-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
-
-#if defined(LPC_DMA_REQUIRED)
-  dmaInit();
-#endif
-}
-
-/**
- * @brief   LPC43xx clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void lpc_clock_init(void) {
-
-  uint32_t i;
-  volatile uint32_t * preg;
-
-#if !LPC_FLASHLESS
-  /* Flash wait states setting.*/
-  preg = (volatile uint32_t *) 0x40043120;                          /* FLASHCFGA */
-  *preg = (1UL<< 31) | (LPC_FLASHCFG_FLASHTIM << 12) | 0x3A;
-  *(preg + 1)= (1UL<< 31) | (LPC_FLASHCFG_FLASHTIM << 12) | 0x3A;   /* FLASHCFGB 0x40043124 */
-#endif
-
-  /* System oscillator initialization if required.*/
-#if LPC_XTAL_ENABLE
-  LPC_CGU->XTAL_OSC_CTRL = (LPC_OSCRANGE << 2);         /* Enable Main oscillator */
-  for(i = 0; i < 1000000; i++)
-    ;                                                   /* Wait for main oscillator to be ready */
-
-  LPC_CGU->BASE_M4_CLK = (CLK_SEL_XTAL << 24);          /* Select the crystal oscillator */
-                                                        /* as clock source for BASE_M4_CLK */
-#else
-  LPC_CGU->BASE_M4_CLK = (CLK_SEL_IRC << 24);          /* Select IRC as clock source for BASE_M4_CLK */
-#endif
-
-  LPC_CGU->PLL1_CTRL = 0;                               /* Power-down PLL1 enabled by Boot ROM */
-
-#if LPC_PLL1_ENABLE /* PLL1 works in direct or non-integer mode. */
-  /* Set PLL1 to FCLKOUT/2 */
-  LPC_CGU->PLL1_CTRL = (1UL << 24) | (LPC_PLL1_CTRL_MSEL << 16) |
-                      (LPC_PLL1_CTRL_NSEL << 12);
-
-  while (!(LPC_CGU->PLL1_STAT & 0x01))
-        ;                                               /* Wait for PLL1 locked */
-
-  LPC_CGU->BASE_M4_CLK = (CLK_SEL_PLL1 << 24);          /* Select PPL1 clock as source for BASE_M4_CLK. */
-
-  for(i = 0; i < 200000; i++)
-      ;                                                 /* Wait */
-
-#if LPC_PLL1_POSTDIV_ENABLE
-  LPC_CGU->PLL1_CTRL |= (LPC_PLL1_CTRL_PSEL << 8);
-#else
-  LPC_CGU->PLL1_CTRL |= (1UL << 7);                     /* Set PLL1 to FCLKOUT > 156 MHz*/
-#endif
-#endif /* LPC_PLL1_ENABLE == TRUE */
-
-  /* Config integer dividers. */
-  preg = &LPC_CGU->IDIVA_CTRL;
-  for (i = 0; i < LPC_IDIV_ARRAY_NUM; i++) {
-    *preg = lpc_idiv[i];
-    preg++;
-  }
-
-  /* Config base clocks. */
-  preg = &LPC_CGU->BASE_USB0_CLK;
-    for (i = 0; i < LPC_BASE_CLK_ARRAY_NUM; i++) {
-      *preg = lpc_base_clk[i];
-      preg++;
-  }
-
-#if LPC_PLL0USB0_ENABLE
-#error "PPL0USB0 not supported."
-#endif /* LPC_PLL0USB_ENABLE == TRUE */
-
-#if LPC_PLL0AUDIO_ENABLE
-#error "PLL0AUDIO not supported."
-#endif /* LPC_PLL0AUDIO == TRUE */
-}
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/hal_lld.h b/os/hal/platforms/LPC43xx/hal_lld.h
deleted file mode 100644
index 06bd3bf43..000000000
--- a/os/hal/platforms/LPC43xx/hal_lld.h
+++ /dev/null
@@ -1,1511 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC43xx HAL driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/hal_lld.h
- * @brief   HAL subsystem low level driver header template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "LPC43xx.h"
-#include "nvic.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME           "LPC43xx"
-
-#define IRCOSCCLK               12000000UL	    /**< High speed internal clock. */
-
-#define CLK_SEL_32KHZ           0x00000000
-#define CLK_SEL_IRC             0x00000001
-#define CLK_SEL_ENET_RX_CLK     0x00000002
-#define CLK_SEL_ENET_TX_CLK     0x00000003
-#define CLK_SEL_GP_CLKIN        0x00000004
-#define CLK_SEL_XTAL            0x00000006
-#define CLK_SEL_PLL0USB         0x00000007
-#define CLK_SEL_PLL0AUDIO       0x00000008
-#define CLK_SEL_PLL1            0x00000009
-#define CLK_SEL_IDIVA           0x0000000C
-#define CLK_SEL_IDIVB           0x0000000D
-#define CLK_SEL_IDIVC           0x0000000E
-#define CLK_SEL_IDIVD           0x0000000F
-#define CLK_SEL_IDIVE           0x00000010
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Crystal oscillator enable.
- */
-#if !defined(LPC_XTAL_ENABLE) || defined(__DOXYGEN__)
-#define LPC_XTAL_ENABLE                 TRUE
-#endif
-
-/**
- * @brief   PLL1 enable.
- */
-#if !defined(LPC_PLL1_ENABLE) || defined(__DOXYGEN__)
-#define LPC_PLL1_ENABLE                 TRUE
-#endif
-
-/**
- * @brief   PLL1 multiplier.
- * @note    Final frequency must not exceed the CCO ratings.
- */
-#if !defined(LPC_PLL1_MUL) || defined(__DOXYGEN__)
-#define LPC_PLL1_MUL                    17
-#endif
-
-/**
- * @brief   PLL1 pre-divider.
- * @note    The value must be in the 1..4 range and the final frequency
- *          must not exceed the CCO ratings.
- */
-#if !defined(LPC_PLL1_PREDIV) || defined(__DOXYGEN__)
-#define LPC_PLL1_PREDIV                 1
-#endif
-
-/**
- * @brief   PLL1 post-divider enable.
- */
-#if !defined(LPC_PLL1_POSTDIV_ENABLE) || defined(__DOXYGEN__)
-#define LPC_PLL1_POSTDIV_ENABLE         FALSE
-#endif
-
-/**
- * @brief   PLL1 post-divider.
- * @note    The value must be 2, 4, 8 or 16.
- */
-#if !defined(LPC_PLL1_POSTDIV) || defined(__DOXYGEN__)
-#define LPC_PLL1_POSTDIV                2
-#endif
-
-/**
- * @brief   USB0 PLL0 enable.
- */
-#if !defined(LPC_PLL0USB_ENABLE) || defined(__DOXYGEN__)
-#define LPC_PLL0USB_ENABLE              FALSE
-#endif
-
-/**
- * @brief   Audio PLL0 enable.
- */
-#if !defined(LPC_PLL0AUDIO_ENABLE) || defined(__DOXYGEN__)
-#define LPC_PLL0AUDIO_ENABLE            FALSE
-#endif
-
-/**
- * @brief   IDIVA clock divider enable.
- */
-#if !defined(LPC_IDIVA_ENABLE) || defined(__DOXYGEN__)
-#define LPC_IDIVA_ENABLE                FALSE
-#endif
-
-/**
- * @brief   IDIVA clock divider source.
- */
-#if !defined(LPC_IDIVA_SRC) || defined(__DOXYGEN__)
-#define LPC_IDIVA_SRC                   CLK_SEL_IRC
-#endif
-
-/**
- * @brief   IDIVA clock divider.
- */
-#if !defined(LPC_IDIVA_DIV) || defined(__DOXYGEN__)
-#define LPC_IDIVA_DIV                   1
-#endif
-
-/**
- * @brief   IDIVB clock divider enable.
- */
-#if !defined(LPC_IDIVB_ENABLE) || defined(__DOXYGEN__)
-#define LPC_IDIVB_ENABLE                FALSE
-#endif
-
-/**
- * @brief   IDIVB clock divider source.
- */
-#if !defined(LPC_IDIVB_SRC) || defined(__DOXYGEN__)
-#define LPC_IDIVB_SRC                   CLK_SEL_IRC
-#endif
-
-/**
- * @brief   IDIVB clock divider.
- */
-#if !defined(LPC_IDIVB_DIV) || defined(__DOXYGEN__)
-#define LPC_IDIVB_DIV                   1
-#endif
-
-/**
- * @brief   IDIVC clock divider enable.
- */
-#if !defined(LPC_IDIVC_ENABLE) || defined(__DOXYGEN__)
-#define LPC_IDIVC_ENABLE                TRUE
-#endif
-
-/**
- * @brief   IDIVC clock divider source.
- */
-#if !defined(LPC_IDIVC_SRC) || defined(__DOXYGEN__)
-#define LPC_IDIVC_SRC                   CLK_SEL_PLL1
-#endif
-
-/**
- * @brief   IDIVC clock divider.
- */
-#if !defined(LPC_IDIVC_DIV) || defined(__DOXYGEN__)
-#define LPC_IDIVC_DIV                   3
-#endif
-
-/**
- * @brief   IDIVD clock divider enable.
- */
-#if !defined(LPC_IDIVD_ENABLE) || defined(__DOXYGEN__)
-#define LPC_IDIVD_ENABLE                FALSE
-#endif
-
-/**
- * @brief   IDIVD clock divider source.
- */
-#if !defined(LPC_IDIVD_SRC) || defined(__DOXYGEN__)
-#define LPC_IDIVD_SRC                   CLK_SEL_IRC
-#endif
-
-/**
- * @brief   IDIVD clock divider.
- */
-#if !defined(LPC_IDIVD_DIV) || defined(__DOXYGEN__)
-#define LPC_IDIVD_DIV                   1
-#endif
-
-/**
- * @brief   IDIVE clock divider enable.
- */
-#if !defined(LPC_IDIVE_ENABLE) || defined(__DOXYGEN__)
-#define LPC_IDIVE_ENABLE                FALSE
-#endif
-
-/**
- * @brief   IDIVE clock divider source.
- */
-#if !defined(LPC_IDIVE_SRC) || defined(__DOXYGEN__)
-#define LPC_IDIVE_SRC                   CLK_SEL_IRC
-#endif
-
-/**
- * @brief   IDIVE clock divider.
- */
-#if !defined(LPC_IDIVE_DIV) || defined(__DOXYGEN__)
-#define LPC_IDIVE_DIV                   1
-#endif
-
-/**
- * @brief   Base M4 clock enable.
- * @note    Must be always enabled.
- */
-#if !defined(LPC_BASE_M4_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_M4_CLK_ENABLE          TRUE
-#endif
-
-/**
- * @brief   Base USB0 clock enable.
- */
-#if !defined(LPC_BASE_USB0_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_USB0_CLK_ENABLE        FALSE
-#endif
-
-/**
- * @brief   Base peripheral clock enable.
- * @note    Base clock for Cortex-M0SUB subsystem, SGPIO.
- */
-#if !defined(LPC_BASE_PERIPH_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_PERIPH_CLK_ENABLE      TRUE
-#endif
-
-/**
- * @brief   Base peripheral clock source.
- */
-#if !defined(LPC_BASE_PERIPH_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_PERIPH_CLK_SRC         CLK_SEL_PLL1
-#endif
-
-/**
- * @brief   Base USB1 clock enable.
- */
-#if !defined(LPC_BASE_USB1_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_USB1_CLK_ENABLE        FALSE
-#endif
-
-/**
- * @brief   Base USB1 clock source.
- */
-#if !defined(LPC_BASE_USB1_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_USB1_CLK_SRC           CLK_SEL_PLL1
-#endif
-
-/**
- * @brief   Base SPIFI clock enable.
- */
-#if !defined(LPC_BASE_SPIFI_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_SPIFI_CLK_ENABLE       TRUE
-#endif
-
-/**
- * @brief   Base SPIFI clock source.
- */
-#if !defined(LPC_BASE_SPIFI_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_SPIFI_CLK_SRC          CLK_SEL_PLL1
-#endif
-
-/**
- * @brief   Base SPI clock enable.
- */
-#if !defined(LPC_BASE_SPI_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_SPI_CLK_ENABLE         TRUE
-#endif
-
-/**
- * @brief   Base SPI clock source.
- */
-#if !defined(LPC_BASE_SPI_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_SPI_CLK_SRC            CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base Ethernet PHY Receive clock enable.
- */
-#if !defined(LPC_BASE_PHY_RX_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_PHY_RX_CLK_ENABLE      TRUE
-#endif
-
-/**
- * @brief   Base Ethernet PHY Receive clock source.
- */
-#if !defined(LPC_BASE_PHY_RX_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_PHY_RX_CLK_SRC         CLK_SEL_IDIVC
-#endif
-
-/**
- * @brief   Base Ethernet PHY Transmit clock enable.
- */
-#if !defined(LPC_BASE_PHY_TX_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_PHY_TX_CLK_ENABLE      TRUE
-#endif
-
-/**
- * @brief   Base Ethernet PHY Transmit clock source.
- */
-#if !defined(LPC_BASE_PHY_TX_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_PHY_TX_CLK_SRC         CLK_SEL_IDIVC
-#endif
-
-/**
- * @brief   Base APB1 clock enable.
- * @note    Base clock for I2C0, I2S, CAN1.
- */
-#if !defined(LPC_BASE_APB1_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_APB1_CLK_ENABLE        TRUE
-#endif
-
-/**
- * @brief   Base APB1 clock source.
- */
-#if !defined(LPC_BASE_APB1_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_APB1_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base APB3 clock enable.
- * @note    Base clock for I2C1, DAC, ADC0, ADC1, CAN0.
- */
-#if !defined(LPC_BASE_APB3_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_APB3_CLK_ENABLE        TRUE
-#endif
-
-/**
- * @brief   Base APB3 clock source.
- */
-#if !defined(LPC_BASE_APB3_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_APB3_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base LCD clock enable.
- */
-#if !defined(LPC_BASE_LCD_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_LCD_CLK_ENABLE         FALSE
-#endif
-
-/**
- * @brief   Base LCD clock source.
- */
-#if !defined(LPC_BASE_LCD_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_LCD_CLK_SRC            CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base SDIO clock enable.
- */
-#if !defined(LPC_BASE_SDIO_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_SDIO_CLK_ENABLE        FALSE
-#endif
-
-/**
- * @brief   Base SDIO clock source.
- */
-#if !defined(LPC_BASE_SDIO_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_SDIO_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base SSP0 clock enable.
- */
-#if !defined(LPC_BASE_SSP0_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_SSP0_CLK_ENABLE        TRUE
-#endif
-
-/**
- * @brief   Base SSP0 clock source.
- */
-#if !defined(LPC_BASE_SSP0_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_SSP0_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base SSP1 clock enable.
- */
-#if !defined(LPC_BASE_SSP1_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_SSP1_CLK_ENABLE        TRUE
-#endif
-
-/**
- * @brief   Base SSP1 clock source.
- */
-#if !defined(LPC_BASE_SSP1_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_SSP1_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base UART0 clock enable.
- */
-#if !defined(LPC_BASE_UART0_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_UART0_CLK_ENABLE        TRUE
-#endif
-
-/**
- * @brief   Base UART0 clock source.
- */
-#if !defined(LPC_BASE_UART0_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_UART0_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base UART1 clock enable.
- */
-#if !defined(LPC_BASE_UART1_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_UART1_CLK_ENABLE        TRUE
-#endif
-
-/**
- * @brief   Base UART1 clock source.
- */
-#if !defined(LPC_BASE_UART1_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_UART1_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base UART2 clock enable.
- */
-#if !defined(LPC_BASE_UART2_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_UART2_CLK_ENABLE        TRUE
-#endif
-
-/**
- * @brief   Base UART2 clock source.
- */
-#if !defined(LPC_BASE_UART2_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_UART2_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base UART3 clock enable.
- */
-#if !defined(LPC_BASE_UART3_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_UART3_CLK_ENABLE        TRUE
-#endif
-
-/**
- * @brief   Base UART3 clock source.
- */
-#if !defined(LPC_BASE_UART3_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_UART3_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base OUT clock enable.
- */
-#if !defined(LPC_BASE_OUT_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_OUT_CLK_ENABLE         FALSE
-#endif
-
-/**
- * @brief   Base OUT clock source.
- */
-#if !defined(LPC_BASE_OUT_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_OUT_CLK_SRC            CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base APLL clock enable.
- */
-#if !defined(LPC_BASE_APLL_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_APLL_CLK_ENABLE        FALSE
-#endif
-
-/**
- * @brief   Base APLL clock source.
- */
-#if !defined(LPC_BASE_APLL_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_APLL_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base CGU OUT0 clock enable.
- */
-#if !defined(LPC_BASE_CGU_OUT0_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_CGU_OUT0_CLK_ENABLE        FALSE
-#endif
-
-/**
- * @brief   Base CGU OUT0 clock source.
- */
-#if !defined(LPC_BASE_CGU_OUT0_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_CGU_OUT0_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/**
- * @brief   Base CGU OUT1 clock enable.
- */
-#if !defined(LPC_BASE_CGU_OUT1_CLK_ENABLE) || defined(__DOXYGEN__)
-#define LPC_BASE_CGU_OUT1_CLK_ENABLE        FALSE
-#endif
-
-/**
- * @brief   Base CGU OUT1 clock source.
- */
-#if !defined(LPC_BASE_CGU_OUT1_CLK_SRC) || defined(__DOXYGEN__)
-#define LPC_BASE_CGU_OUT1_CLK_SRC           CLK_SEL_IRC
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Calculated OSCRANGE setting.
- */
-#if (XTAL < 18000000) || defined(__DOXYGEN__)
-#define LPC_OSCRANGE        0
-#else
-#define LPC_OSCRANGE        1
-#endif
-
-/**
- * @brief   PLL1 FCLKIN frequency select.
- */
-#if LPC_XTAL_ENABLE
-#define LPC_PLL1_FCLKIN     XTAL
-#else
-#define LPC_PLL1_FCLKIN     IRCOSCCLK
-#endif
-
-/**
- * @brief   MSEL mask in PLL1_CTRL register.
- */
-#if (((LPC_PLL1_MUL) >= 1) && ((LPC_PLL1_MUL) <= 256))|| defined(__DOXYGEN__)
-#define LPC_PLL1_CTRL_MSEL ((LPC_PLL1_MUL) - 1)
-#else
-#error "Invalid LPC_PLL1_MULL value."
-#endif
-
-/**
- * @brief   NSEL mask in PLL1_CTRL register.
- */
-#if (((LPC_PLL1_PREDIV) >= 1) && ((LPC_PLL1_PREDIV) <= 4)) || defined(__DOXYGEN__)
-#define LPC_PLL1_CTRL_NSEL ((LPC_PLL1_PREDIV) - 1)
-#else
-#error "Invalid LPC_PLL1_PREDIV value (1 to 4 accepted)."
-#endif
-
-/**
- * @brief   PSEL mask in PLL1_CTRL register.
- */
-#if ((LPC_PLL1_POSTDIV) == 2) || ((LPC_PLL1_POSTDIV) == 4) || ((LPC_PLL1_POSTDIV) == 8) ||\
-    ((LPC_PLL1_POSTDIV) == 16) || defined(__DOXYGEN__)
-#define LPC_PLL1_CTRL_PSEL (((LPC_PLL1_POSTDIV) / 2) - 1)
-#else
-#error "Invalid LPC_PLL1_POSTDIV  value (2, 4, 6, 8 accepted)."
-#endif
-
-/**
- * @brief   CCO frequency.
- */
-#define  LPC_PLL1_CCO   (((LPC_PLL1_MUL) *    \
-                              LPC_PLL1_FCLKIN)/(LPC_PLL1_PREDIV))
-
-#if (LPC_PLL1_CCO < 156000000) || (LPC_PLL1_CCO > 320000000)
-#error "CCO frequency out of the acceptable range (156...320)."
-#endif
-
-/**
- * @brief   PLL1 clock frequency.
- */
-#if LPC_PLL1_ENABLE && LPC_PLL1_POSTDIV_ENABLE
-#define  LPC_PLL1_CLK     (LPC_PLL1_CCO / (LPC_PLL1_POSTDIV))
-#elif LPC_PLL1_ENABLE
-#define  LPC_PLL1_CLK     LPC_PLL1_CCO
-#endif
-
-/**
- * @brief   CPU clock frequency.
- */
-#if LPC_PLL1_ENABLE
-#define  LPC_BASE_M4_CLK        LPC_PLL1_CLK
-#define  LPC_BASE_M4_CLK_SRC    CLK_SEL_PLL1
-#elif LPC_XTAL_ENABLE
-#define  LPC_BASE_M4_CLK        XTAL
-#define  LPC_BASE_M4_CLK_SRC    CLK_SEL_XTAL
-#else
-#define  LPC_BASE_M4_CLK        IRCOSCCLK
-#define  LPC_BASE_M4_CLK_SRC    CLK_SEL_IRC
-#endif
-
-/**
- * @brief   CPU clock frequency range check.
- * @note 	Max clock for LPC43xx is 204 MHz.
- */
-#if (LPC_BASE_M4_CLK  > 204000000) || defined(__DOXYGEN__)
-#error "CPU Clock out of range."
-#endif
-
-#if (!LPC_FLASHLESS) || defined(__DOXYGEN__)
-/**
- * @brief   Flash wait states.
- */
-#if (LPC_BASE_M4_CLK <= 21000000) || defined(__DOXYGEN__)
-#define LPC_FLASHCFG_FLASHTIM   0UL
-#elif LPC_BASE_M4_CLK <= 43000000
-#define LPC_FLASHCFG_FLASHTIM   1UL
-#elif LPC_BASE_M4_CLK <= 64000000
-#define LPC_FLASHCFG_FLASHTIM   2UL
-#elif LPC_BASE_M4_CLK <= 86000000
-#define LPC_FLASHCFG_FLASHTIM   3UL
-#elif LPC_BASE_M4_CLK <= 107000000
-#define LPC_FLASHCFG_FLASHTIM   4UL
-#elif LPC_BASE_M4_CLK <= 129000000
-#define LPC_FLASHCFG_FLASHTIM   5UL
-#elif LPC_BASE_M4_CLK <= 150000000
-#define LPC_FLASHCFG_FLASHTIM   6UL
-#elif LPC_BASE_M4_CLK <= 172000000
-#define LPC_FLASHCFG_FLASHTIM   7UL
-#elif LPC_BASE_M4_CLK <= 193000000
-#define LPC_FLASHCFG_FLASHTIM   8UL
-#else
-#define LPC_FLASHCFG_FLASHTIM   9UL
-#endif
-#endif
-
-/**
- * @brief   CPU clock frequency.
- */
-#if LPC_IDIVA_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_IDIVA_CLK     RTC_XTAL/LPC_IDIVA_DIV
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IRC
-#define  LPC_IDIVA_CLK     IRCOSCCLK/LPC_IDIVA_DIV
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_IDIVA_CLK     ENET_RX_CLK/LPC_IDIVA_DIV
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_IDIVA_CLK     ENET_TX_CLK/LPC_IDIVA_DIV
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_IDIVA_CLK     GP_CLKIN_CLK/LPC_IDIVA_DIV
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_IDIVA_CLK     XTAL/LPC_IDIVA_DIV
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_IDIVA_CLK source can't be PLL0USB."
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_IDIVA_CLK     LPC_PLL0AUDIO_CLK/LPC_IDIVA_DIV
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_IDIVA_CLK     LPC_PLL1_CLK/LPC_IDIVA_DIV
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVA
-#error   "LPC_IDIVA_CLK source can't be IDIVA_CLK."
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVB
-#error   "LPC_IDIVA_CLK source can't be IDIVB_CLK."
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVC
-#error   "LPC_IDIVA_CLK source can't be IDIVC_CLK."
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVD
-#error   "LPC_IDIVA_CLK source can't be IDIVD_CLK."
-#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVE
-#error   "LPC_IDIVA_CLK source can't be IDIVE_CLK."
-#else
-#error  "LPC_IDIVA_CLK wrong clock source."
-#endif
-
-#if LPC_IDIVB_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_IDIVB_CLK     RTC_XTAL/LPC_IDIVB_DIV
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IRC
-#define  LPC_IDIVB_CLK     IRCOSCCLK/LPC_IDIVB_DIV
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_IDIVB_CLK     ENET_RX_CLK/LPC_IDIVB_DIV
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_IDIVB_CLK     ENET_TX_CLK/LPC_IDIVB_DIV
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_IDIVB_CLK     GP_CLKIN_CLK/LPC_IDIVB_DIV
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_IDIVB_CLK     XTAL/LPC_IDIVB_DIV
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_IDIVB_CLK source can't be PLL0USB."
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_IDIVB_CLK     LPC_PLL0AUDIO_CLK/LPC_IDIVB_DIV
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_IDIVB_CLK     LPC_PLL1_CLK/LPC_IDIVB_DIV
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_IDIVB_CLK     LPC_IDIVA_CLK/LPC_IDIVB_DIV
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVB
-#error   "LPC_IDIVB_CLK source can't be IDIVB_CLK."
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVC
-#error   "LPC_IDIVB_CLK source can't be IDIVC_CLK."
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVD
-#error   "LPC_IDIVB_CLK source can't be IDIVD_CLK."
-#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVE
-#error   "LPC_IDIVB_CLK source can't be IDIVE_CLK."
-#else
-#error  "LPC_IDIVB_CLK wrong clock source."
-#endif
-
-#if LPC_IDIVC_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_IDIVC_CLK     RTC_XTAL/LPC_IDIVC_DIV
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IRC
-#define  LPC_IDIVC_CLK     IRCOSCCLK/LPC_IDIVC_DIV
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_IDIVC_CLK     ENET_RX_CLK/LPC_IDIVC_DIV
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_IDIVC_CLK     ENET_TX_CLK/LPC_IDIVC_DIV
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_IDIVC_CLK     GP_CLKIN_CLK/LPC_IDIVC_DIV
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_IDIVC_CLK     XTAL/LPC_IDIVC_DIV
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_IDIVC_CLK source can't be PLL0USB."
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_IDIVC_CLK     LPC_PLL0AUDIO_CLK/LPC_IDIVC_DIV
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_IDIVC_CLK     LPC_PLL1_CLK/LPC_IDIVC_DIV
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_IDIVC_CLK     LPC_IDIVA_CLK/LPC_IDIVC_DIV
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVB
-#error   "LPC_IDIVC_CLK source can't be IDIVB_CLK."
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVC
-#error   "LPC_IDIVC_CLK source can't be IDIVC_CLK."
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVD
-#error   "LPC_IDIVC_CLK source can't be IDIVD_CLK."
-#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVE
-#error   "LPC_IDIVC_CLK source can't be IDIVE_CLK."
-#else
-#error  "LPC_IDIVC_CLK wrong clock source."
-#endif
-
-#if LPC_IDIVD_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_IDIVD_CLK     RTC_XTAL/LPC_IDIVD_DIV
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IRC
-#define  LPC_IDIVD_CLK     IRCOSCCLK/LPC_IDIVD_DIV
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_IDIVD_CLK     ENET_RX_CLK/LPC_IDIVD_DIV
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_IDIVD_CLK     ENET_TX_CLK/LPC_IDIVD_DIV
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_IDIVD_CLK     GP_CLKIN_CLK/LPC_IDIVD_DIV
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_IDIVD_CLK     XTAL/LPC_IDIVD_DIV
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_IDIVD_CLK source can't be PLL0USB."
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_IDIVD_CLK     LPC_PLL0AUDIO_CLK/LPC_IDIVD_DIV
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_IDIVD_CLK     LPC_PLL1_CLK/LPC_IDIVD_DIV
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_IDIVD_CLK     LPC_IDIVA_CLK/LPC_IDIVD_DIV
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVB
-#error   "LPC_IDIVD_CLK source can't be IDIVB_CLK."
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVC
-#error   "LPC_IDIVD_CLK source can't be IDIVC_CLK."
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVD
-#error   "LPC_IDIVD_CLK source can't be IDIVD_CLK."
-#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVE
-#error   "LPC_IDIVD_CLK source can't be IDIVE_CLK."
-#else
-#error  "LPC_IDIVD_CLK wrong clock source."
-#endif
-
-#if LPC_IDIVE_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_IDIVE_CLK     RTC_XTAL/LPC_IDIVE_DIV
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IRC
-#define  LPC_IDIVE_CLK     IRCOSCCLK/LPC_IDIVE_DIV
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_IDIVE_CLK     ENET_RX_CLK/LPC_IDIVE_DIV
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_IDIVE_CLK     ENET_TX_CLK/LPC_IDIVE_DIV
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_IDIVE_CLK     GP_CLKIN_CLK/LPC_IDIVE_DIV
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_IDIVE_CLK     XTAL/LPC_IDIVE_DIV
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_IDIVE_CLK source can't be PLL0USB."
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_IDIVE_CLK     LPC_PLL0AUDIO_CLK/LPC_IDIVE_DIV
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_IDIVE_CLK     LPC_PLL1_CLK/LPC_IDIVE_DIV
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_IDIVE_CLK     LPC_IDIVA_CLK/LPC_IDIVE_DIV
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVB
-#error   "LPC_IDIVE_CLK source can't be IDIVB_CLK."
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVC
-#error   "LPC_IDIVE_CLK source can't be IDIVC_CLK."
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVD
-#error   "LPC_IDIVE_CLK source can't be IDIVD_CLK."
-#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVE
-#error   "LPC_IDIVE_CLK source can't be IDIVE_CLK."
-#else
-#error  "LPC_IDIVE_CLK wrong clock source."
-#endif
-
-/**
- * @brief   Peripheral clocks frequency.
- */
-#if LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_PERIPH_CLK     RTC_XTAL
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_PERIPH_CLK     IRCOSCCLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_PERIPH_CLK     ENET_RX_CLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_PERIPH_CLK     ENET_TX_CLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_PERIPH_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_PERIPH_CLK     XTAL
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_PERIPH_CLK source can't be PLL0USB."
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_PERIPH_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_PERIPH_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_PERIPH_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_PERIPH_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_PERIPH_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_PERIPH_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_PERIPH_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_PERIPH_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_USB1_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_USB1_CLK     RTC_XTAL
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_USB1_CLK     IRCOSCCLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_USB1_CLK     ENET_RX_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_USB1_CLK     ENET_TX_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_USB1_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_USB1_CLK     XTAL
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_PLL0USB
-#define  LPC_BASE_USB1_CLK     LPC_PLL0USB_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_USB1_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_USB1_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_USB1_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_USB1_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_USB1_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_USB1_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_USB1_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_USB1_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_SPIFI_CLK     RTC_XTAL
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_SPIFI_CLK     IRCOSCCLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_SPIFI_CLK     ENET_RX_CLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_SPIFI_CLK     ENET_TX_CLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_SPIFI_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_SPIFI_CLK     XTAL
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_SPIFI_CLK source can't be PLL0USB."
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_SPIFI_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_SPIFI_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_SPIFI_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_SPIFI_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_SPIFI_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_SPIFI_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_SPIFI_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_SPIFI_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_SPI_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_SPI_CLK     RTC_XTAL
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_SPI_CLK     IRCOSCCLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_SPI_CLK     ENET_RX_CLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_SPI_CLK     ENET_TX_CLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_SPI_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_SPI_CLK     XTAL
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_SPI_CLK source can't be PLL0USB."
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_SPI_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_SPI_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_SPI_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_SPI_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_SPI_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_SPI_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_SPI_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_SPI_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_PHY_RX_CLK     RTC_XTAL
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_PHY_RX_CLK     IRCOSCCLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_PHY_RX_CLK     ENET_RX_CLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_PHY_RX_CLK     ENET_TX_CLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_PHY_RX_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_PHY_RX_CLK     XTAL
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_PHY_RX_CLK source can't be PLL0USB."
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_PHY_RX_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_PHY_RX_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_PHY_RX_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_PHY_RX_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_PHY_RX_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_PHY_RX_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_PHY_RX_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_PHY_RX_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_PHY_TX_CLK     RTC_XTAL
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_PHY_TX_CLK     IRCOSCCLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_PHY_TX_CLK     ENET_RX_CLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_PHY_TX_CLK     ENET_TX_CLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_PHY_TX_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_PHY_TX_CLK     XTAL
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_PHY_TX_CLK source can't be PLL0USB."
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_PHY_TX_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_PHY_TX_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_PHY_TX_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_PHY_TX_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_PHY_TX_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_PHY_TX_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_PHY_TX_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_PHY_TX_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_APB1_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_APB1_CLK     RTC_XTAL
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_APB1_CLK     IRCOSCCLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_APB1_CLK     ENET_RX_CLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_APB1_CLK     ENET_TX_CLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_APB1_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_APB1_CLK     XTAL
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_APB1_CLK source can't be PLL0USB."
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_APB1_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_APB1_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_APB1_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_APB1_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_APB1_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_APB1_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_APB1_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_APB1_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_APB3_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_APB3_CLK     RTC_XTAL
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_APB3_CLK     IRCOSCCLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_APB3_CLK     ENET_RX_CLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_APB3_CLK     ENET_TX_CLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_APB3_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_APB3_CLK     XTAL
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_APB3_CLK source can't be PLL0USB."
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_APB3_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_APB3_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_APB3_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_APB3_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_APB3_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_APB3_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_APB3_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_APB3_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_LCD_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_LCD_CLK     RTC_XTAL
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_LCD_CLK     IRCOSCCLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_LCD_CLK     ENET_RX_CLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_LCD_CLK     ENET_TX_CLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_LCD_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_LCD_CLK     XTAL
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_LCD_CLK source can't be PLL0USB."
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_LCD_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_LCD_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_LCD_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_LCD_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_LCD_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_LCD_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_LCD_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_LCD_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_SDIO_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_SDIO_CLK     RTC_XTAL
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_SDIO_CLK     IRCOSCCLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_SDIO_CLK     ENET_RX_CLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_SDIO_CLK     ENET_TX_CLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_SDIO_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_SDIO_CLK     XTAL
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_SDIO_CLK source can't be PLL0USB."
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_SDIO_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_SDIO_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_SDIO_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_SDIO_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_SDIO_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_SDIO_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_SDIO_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_SDIO_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_SSP0_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_SSP0_CLK     RTC_XTAL
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_SSP0_CLK     IRCOSCCLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_SSP0_CLK     ENET_RX_CLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_SSP0_CLK     ENET_TX_CLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_SSP0_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_SSP0_CLK     XTAL
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_SSP0_CLK source can't be PLL0USB."
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_SSP0_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_SSP0_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_SSP0_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_SSP0_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_SSP0_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_SSP0_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_SSP0_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_SSP0_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_SSP1_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_SSP1_CLK     RTC_XTAL
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_SSP1_CLK     IRCOSCCLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_SSP1_CLK     ENET_RX_CLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_SSP1_CLK     ENET_TX_CLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_SSP1_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_SSP1_CLK     XTAL
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_SSP1_CLK source can't be PLL0USB."
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_SSP1_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_SSP1_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_SSP1_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_SSP1_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_SSP1_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_SSP1_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_SSP1_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_SSP1_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_UART0_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_UART0_CLK     RTC_XTAL
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_UART0_CLK     IRCOSCCLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_UART0_CLK     ENET_RX_CLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_UART0_CLK     ENET_TX_CLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_UART0_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_UART0_CLK     XTAL
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_UART0_CLK source can't be PLL0USB."
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_UART0_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_UART0_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_UART0_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_UART0_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_UART0_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_UART0_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_UART0_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_UART0_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_UART1_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_UART1_CLK     RTC_XTAL
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_UART1_CLK     IRCOSCCLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_UART1_CLK     ENET_RX_CLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_UART1_CLK     ENET_TX_CLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_UART1_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_UART1_CLK     XTAL
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_UART1_CLK source can't be PLL0USB."
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_UART1_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_UART1_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_UART1_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_UART1_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_UART1_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_UART1_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_UART1_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_UART1_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_UART2_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_UART2_CLK     RTC_XTAL
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_UART2_CLK     IRCOSCCLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_UART2_CLK     ENET_RX_CLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_UART2_CLK     ENET_TX_CLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_UART2_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_UART2_CLK     XTAL
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_UART2_CLK source can't be PLL0USB."
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_UART2_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_UART2_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_UART2_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_UART2_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_UART2_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_UART2_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_UART2_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_UART2_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_UART3_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_UART3_CLK     RTC_XTAL
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_UART3_CLK     IRCOSCCLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_UART3_CLK     ENET_RX_CLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_UART3_CLK     ENET_TX_CLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_UART3_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_UART3_CLK     XTAL
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_UART3_CLK source can't be PLL0USB."
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_UART3_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_UART3_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_UART3_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_UART3_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_UART3_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_UART3_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_UART3_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_UART3_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_OUT_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_OUT_CLK     RTC_XTAL
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_OUT_CLK     IRCOSCCLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_OUT_CLK     ENET_RX_CLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_OUT_CLK     ENET_TX_CLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_OUT_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_OUT_CLK     XTAL
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_OUT_CLK source can't be PLL0USB."
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_OUT_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_OUT_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_OUT_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_OUT_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_OUT_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_OUT_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_OUT_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_OUT_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_APLL_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_APLL_CLK     RTC_XTAL
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_APLL_CLK     IRCOSCCLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_APLL_CLK     ENET_RX_CLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_APLL_CLK     ENET_TX_CLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_APLL_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_APLL_CLK     XTAL
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_APLL_CLK source can't be PLL0USB."
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_APLL_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_APLL_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_APLL_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_APLL_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_APLL_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_APLL_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_APLL_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_APLL_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_CGU_OUT0_CLK     RTC_XTAL
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_CGU_OUT0_CLK     IRCOSCCLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_CGU_OUT0_CLK     ENET_RX_CLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_CGU_OUT0_CLK     ENET_TX_CLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_CGU_OUT0_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_CGU_OUT0_CLK     XTAL
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_CGU_OUT0_CLK source can't be PLL0USB."
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_CGU_OUT0_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_CGU_OUT0_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_CGU_OUT0_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_CGU_OUT0_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_CGU_OUT0_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_CGU_OUT0_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_CGU_OUT0_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_CGU_OUT0_CLK wrong clock source."
-#endif
-
-#if LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_32KHZ
-#define  LPC_BASE_CGU_OUT1_CLK     RTC_XTAL
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IRC
-#define  LPC_BASE_CGU_OUT1_CLK     IRCOSCCLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_ENET_RX_CLK
-#define  LPC_BASE_CGU_OUT1_CLK     ENET_RX_CLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_ENET_TX_CLK
-#define  LPC_BASE_CGU_OUT1_CLK     ENET_TX_CLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_GP_CLKIN
-#define  LPC_BASE_CGU_OUT1_CLK     GP_CLKIN_CLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_XTAL
-#define  LPC_BASE_CGU_OUT1_CLK     XTAL
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_PLL0USB
-#error   "LPC_BASE_CGU_OUT1_CLK source can't be PLL0USB."
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_PLL0AUDIO
-#define  LPC_BASE_CGU_OUT1_CLK     LPC_PLL0AUDIO_CLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_PLL1
-#define  LPC_BASE_CGU_OUT1_CLK     LPC_PLL1_CLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVA
-#define  LPC_BASE_CGU_OUT1_CLK     LPC_IDIVA_CLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVB
-#define  LPC_BASE_CGU_OUT1_CLK     LPC_IDIVB_CLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVC
-#define  LPC_BASE_CGU_OUT1_CLK     LPC_IDIVC_CLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVD
-#define  LPC_BASE_CGU_OUT1_CLK     LPC_IDIVD_CLK
-#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVE
-#define  LPC_BASE_CGU_OUT1_CLK     LPC_IDIVE_CLK
-#else
-#error  "LPC_BASE_CGU_OUT1_CLK wrong clock source."
-#endif
-
-#define  LPC_CLK_M4_ETHERNET    LPC_BASE_M4_CLK
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This service is implemented by returning the content of the
- *          DWT_CYCCNT register.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value()         DWT_CYCCNT
-
-/**
- * @brief   Realtime counter frequency.
- * @note    The DWT_CYCCNT register is incremented directly by the cpu
- *          clock so this function returns LPC_BASE_M4_CLK.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency()     LPC_BASE_M4_CLK
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#include "lpc43xx_dma.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void lpc_clock_init(void);
-  void lpc_deep_sleep_enter(uint32_t core_type);
-  void lpc_deep_sleep_exit(void);
-  void lpc_deep_power_down_enter(uint32_t core_type);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/lpc43xx_dma.c b/os/hal/platforms/LPC43xx/lpc43xx_dma.c
deleted file mode 100644
index 5a7c8cc70..000000000
--- a/os/hal/platforms/LPC43xx/lpc43xx_dma.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC43xx DMA driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/LPC43xx_dma.c
- * @brief   DMA driver code.
- *
- * @addtogroup LPC43xx_DMA
- * @details DMA sharing helper driver. In the LPC43xx the DMA streams are a
- *          shared resource, this driver allows to allocate and free DMA
- *          streams at runtime in order to allow all the other device
- *          drivers to coordinate the access to the resource.
- * @note    The DMA ISR handlers are all declared into this module because
- *          sharing, the various device drivers can associate a callback to
- *          ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
-   has been enabled.*/
-#if defined(LPC_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-  lpc_dma_channel_config_t * \
-  _lpc_dma_channel_config[LPC_DMA_CHANNELS] = {
-  LPC_GPDMACH0, LPC_GPDMACH1, LPC_GPDMACH2, LPC_GPDMACH3, LPC_GPDMACH4,
-  LPC_GPDMACH5, LPC_GPDMACH6, LPC_GPDMACH7 };
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   DMA ISR redirector type.
- */
-typedef struct {
-  lpc_dmaisr_t      dma_func;       /**< @brief DMA callback function.  */
-  void              *dma_param;     /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief   Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief   DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[LPC_DMA_CHANNELS];
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector48) {
-  uint32_t irq_status;
-  uint32_t err_status;
-  uint8_t i;
-
-  CH_IRQ_PROLOGUE();
-
-  irq_status = LPC_GPDMA->INTTCSTAT;
-  LPC_GPDMA->INTTCCLEAR = irq_status;  /* Clear DMA interrupt flag. */
-  err_status = LPC_GPDMA->INTERRSTAT;
-  LPC_GPDMA->INTERRCLR = err_status;   /* Clear DMA error flag if any. */
-
-  for (i = 0; i < LPC_DMA_CHANNELS; i++) {
-    if (irq_status & (1UL << i)) {
-      if (dma_isr_redir[i].dma_func)
-        dma_isr_redir[i].dma_func(dma_isr_redir[i].dma_param, err_status);
-    }
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   LPC43xx DMA initialization.
- *
- * @init
- */
-void dmaInit(void) {
-  uint8_t i;
-                                                  /* Disable all channels */
-  for (i = 0; i < LPC_DMA_CHANNELS; i++)
-    _lpc_dma_channel_config[i]->config = 0;
-
-  LPC_GPDMA->INTTCCLEAR = 0xFF;
-  LPC_GPDMA->INTERRCLR = 0xFF;
-
-  LPC_GPDMA->CONFIG = DMACCONFIG_E;               /* Enable DMA Controller, little-endian mode */
-  while((LPC_GPDMA->CONFIG & DMACCONFIG_E) != 0x01)
-    ;
-
-  nvicEnableVector(DMA_IRQn, CORTEX_PRIORITY_MASK(LPC_DMA_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Allocates a DMA channel.
- * @details The channel is allocated.
- * @pre     The channel must not be already in use or an error is returned.
- * @post    The channel is allocated and the default ISR handler redirected
- *          to the specified function.
- * @post    The channel must be freed using @p dmaChannelRelease() before it can
- *          be reused with another peripheral.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmach     DMA channel number
- * @param[in] func      handling function pointer, can be @p NULL
- * @param[in] param     a parameter to be passed to the handling function
- * @return              The operation status.
- * @retval FALSE        no error, stream taken.
- * @retval TRUE         error, stream already taken.
- *
- * @special
- */
-bool_t dmaChannelAllocate(lpc_dma_channel_t dmach,
-                         lpc_dmaisr_t func,
-                         void *param) {
-  uint32_t channel;
-  channel = (1UL << dmach);
-
-  /* Checks if the channel is already taken.*/
-  if ((dma_streams_mask & channel) != 0)
-    return TRUE;
-
-  /* Marks the stream as allocated.*/
-  dma_isr_redir[dmach].dma_func  = func;
-  dma_isr_redir[dmach].dma_param = param;
-  dma_streams_mask |= channel;
-
-  return FALSE;
-}
-
-/**
- * @brief   Releases a DMA channel.
- * @details The channel is freed.
- *          Trying to release a unallocated channel is an illegal operation
- *          and is trapped if assertions are enabled.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    The channel is again available.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmach     DMA channel number
- *
- * @special
- */
-void dmaChannelRelease(lpc_dma_channel_t dmach) {
-
-  uint32_t channel;
-  channel = (1UL << dmach);
-
-  /* Check if the streams is not taken.*/
-  chDbgAssert((dma_streams_mask & channel) != 0,
-                "dmaStreamRelease(), #1", "not allocated");
-
-  dma_streams_mask &= ~channel; /* Marks the stream as not allocated.*/
-}
-
-#endif /* LPC_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/lpc43xx_dma.h b/os/hal/platforms/LPC43xx/lpc43xx_dma.h
deleted file mode 100644
index 75e626803..000000000
--- a/os/hal/platforms/LPC43xx/lpc43xx_dma.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-    LPC43xx DMA driver - Copyright (C) 2013 Marcin Jokel
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/LPC43xx_dma.h
- * @brief   DMA driver header.
- *
- * @addtogroup LPC43xx_DMA
- * @{
- */
-
-#ifndef _LPC43xx_DMA_H_
-#define _LPC43xx_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define LPC_GPDMACH0 ((lpc_dma_channel_config_t *) (LPC_GPDMA_BASE + 0x100))
-#define LPC_GPDMACH1 ((lpc_dma_channel_config_t *) (LPC_GPDMA_BASE + 0x120))
-#define LPC_GPDMACH2 ((lpc_dma_channel_config_t *) (LPC_GPDMA_BASE + 0x140))
-#define LPC_GPDMACH3 ((lpc_dma_channel_config_t *) (LPC_GPDMA_BASE + 0x160))
-#define LPC_GPDMACH4 ((lpc_dma_channel_config_t *) (LPC_GPDMA_BASE + 0x180))
-#define LPC_GPDMACH5 ((lpc_dma_channel_config_t *) (LPC_GPDMA_BASE + 0x1A0))
-#define LPC_GPDMACH6 ((lpc_dma_channel_config_t *) (LPC_GPDMA_BASE + 0x1C0))
-#define LPC_GPDMACH7 ((lpc_dma_channel_config_t *) (LPC_GPDMA_BASE + 0x1E0))
-
-#define DMACCONFIG_E                        (1UL << 0)
-#define DMACCONFIG_M                        (1UL << 1)
-
-/**
- * @brief   Total number of DMA streams.
- * @note    This is the total number of streams among all the DMA units.
- */
-#define LPC_DMA_CHANNELS                    8
-
-/**
- * @name    DMA control data configuration
- * @{
- */
-
-/**
- * @brief   DMA transfer size.
- *
- * @param[in] n    DMA transfer size
- */
-#define DMA_CTRL_TRANSFER_SIZE(n)           (n)
-
-/**
- * @brief   DMA source burst size.
- */
-#define DMA_CTRL_SRC_BSIZE_1                (0 << 12)
-#define DMA_CTRL_SRC_BSIZE_4                (1UL << 12)
-#define DMA_CTRL_SRC_BSIZE_8                (2UL << 12)
-#define DMA_CTRL_SRC_BSIZE_16               (3UL << 12)
-#define DMA_CTRL_SRC_BSIZE_32               (4UL << 12)
-#define DMA_CTRL_SRC_BSIZE_64               (5UL << 12)
-#define DMA_CTRL_SRC_BSIZE_128              (6UL << 12)
-#define DMA_CTRL_SRC_BSIZE_256              (7UL << 12)
-
-/**
- * @brief   DMA destination burst size.
- * @{
- */
-#define DMA_CTRL_DST_BSIZE_1                (0 << 15)
-#define DMA_CTRL_DST_BSIZE_4                (1UL << 15)
-#define DMA_CTRL_DST_BSIZE_8                (2UL << 15)
-#define DMA_CTRL_DST_BSIZE_16               (3UL << 15)
-#define DMA_CTRL_DST_BSIZE_32               (4UL << 15)
-#define DMA_CTRL_DST_BSIZE_64               (5UL << 15)
-#define DMA_CTRL_DST_BSIZE_128              (6UL << 15)
-#define DMA_CTRL_DST_BSIZE_256              (7UL << 15)
-/** @} */
-
-/**
- * @name    DMA source transfer width.
- * @{
- */
-#define DMA_CTRL_SRC_WIDTH_BYTE             (0 << 18)
-#define DMA_CTRL_SRC_WIDTH_HWORD            (1UL << 18)
-#define DMA_CTRL_SRC_WIDTH_WORD             (2UL << 18)
-/** @} */
-
-/**
- * @name    DMA destination transfer width.
- * @{
- */
-#define DMA_CTRL_DST_WIDTH_BYTE             (0 << 21)
-#define DMA_CTRL_DST_WIDTH_HWORD            (1UL << 21)
-#define DMA_CTRL_DST_WIDTH_WORD             (2UL << 21)
-
-/**
- * @name    DMA source, source AHB master select.
- * @{
- */
-#define DMA_CTRL_SRC_AHBM0                  (0 << 24)
-#define DMA_CTRL_SRC_AHBM1                  (1 << 24)
-/** @} */
-
-/**
- * @name    DMA destination AHB master select.
- * @{
- */
-#define DMA_CTRL_DST_AHBM0                  (0 << 25)
-#define DMA_CTRL_DST_AHBM1                  (1 << 25)
-/** @} */
-
-/**
- * @name    DMA source increment after each transfer.
- * @{
- */
-#define DMA_CTRL_SRC_NOINC                  (0UL << 26)
-#define DMA_CTRL_SRC_INC                    (1UL << 26)
-
-/**
- * @name    DMA destination increment after each transfer.
- * @{
- */
-#define DMA_CTRL_DST_NOINC                  (0UL << 27)
-#define DMA_CTRL_DST_INC                    (1UL << 27)
-
-/**
- * @name    DMA bus access bits.
- * @{
- */
-#define DMA_CTRL_PROT1_USER                 (0 << 28)
-#define DMA_CTRL_PROT1_PRIV                 (1UL << 28)
-
-#define DMA_CTRL_PROT2_NONBUFF              (0 << 29)
-#define DMA_CTRL_PROT2_BUFF                 (1UL << 29)
-
-#define DMA_CTRL_PROT3_NONCACHE             (0 << 30)
-#define DMA_CTRL_PROT3_CACHE                (1UL << 30)
-/** @} */
-
-/**
- * @name    DMA terminal count interrupt enable.
- * @{
- */
-#define DMA_CTRL_INT                        (1UL << 31)
-/** @} */
-
-/**
- * @name    DMA channel enable.
- * @{
- */
-#define DMA_CFG_CH_ENABLE                   (1UL << 0)
-
-/**
- * @brief   Source peripheral.
- *
- * @param[in] source        source peripheral
- */
-#define DMA_CFG_SRC_PERIPH(src)             ((src) << 1)
-
-/**
- * @brief   Destination peripheral.
- *
- * @param[in] destination   destination peripheral
- */
-#define DMA_CFG_DST_PERIPH(dst)             ((dst) << 6)
-
-/**
- * @name    Flow control and transfer type.
- * @{
- */
-#define DMA_CFG_FCTRL_M2M               (0UL << 11)
-#define DMA_CFG_FCTRL_M2P               (1UL << 11)
-#define DMA_CFG_FCTRL_P2M               (2UL << 11)
-#define DMA_CFG_FCTRL_P2P_DMA_CTRL      (3UL << 11)
-#define DMA_CFG_FCTRL_P2P_DST_CTRL      (4UL << 11)
-#define DMA_CFG_FCTRL_M2P_PER_CTRL      (5UL << 11)
-#define DMA_CFG_FCTRL_P2M_PER_CTRL      (6UL << 11)
-#define DMA_CFG_FCTRL_P2P_SRC_CTRL      (7UL << 11)
-/** @} */
-
-/**
- * @name    Interrupt error mask.
- * @{
- */
-#define DMA_CFG_IE                          (1UL << 14)
-/** @} */
-
-/**
- * @name    Terminal count interrupt mask.
- * @{
- */
-#define DMA_CFG_ITC                         (1UL << 15)
-/** @} */
-
-/**
- * @name    Active.
- * @note    Read only
- * @{
- */
-#define DMA_CFG_ACTIVE                      (1UL << 17)
-/** @} */
-
-/**
- * @name    Halt.
- * @{
- */
-#define DMA_CFG_HALT                        (1UL << 18)
-/** @} */
-/** @} */
-
-/**
- * @name    AHB master select for loading the next LLI.
- * @{
- */
-#define DMA_LLI_AHBM0                        0
-#define DMA_LLI_AHBM1                        1
-/** @} */
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DMA interrupt priority level setting.
- */
-#if !defined(LPC_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_DMA_IRQ_PRIORITY                3
-#endif
-
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-typedef struct {
-  volatile uint32_t srcaddr;        /**< @brief Source address.         */
-  volatile uint32_t dstaddr;        /**< @brief Destination address.    */
-  volatile uint32_t lli;            /**< @brief Linked List Item.       */
-  volatile uint32_t control;        /**< @brief Control.                */
-  volatile uint32_t config;         /**< @brief Configuration.          */
-} lpc_dma_channel_config_t;
-
-typedef struct {
-  volatile uint32_t srcaddr;        /**< @brief Source address.         */
-  volatile uint32_t dstaddr;        /**< @brief Destination address.    */
-  volatile uint32_t lli;            /**< @brief Linked List Item.       */
-  volatile uint32_t control;        /**< @brief Control.                */
-} lpc_dma_lli_config_t;
-
-/**
- * @brief   DMA channel number.
- */
-typedef enum {
-  DMA_CHANNEL0               = 0,
-  DMA_CHANNEL1               = 1,
-  DMA_CHANNEL2               = 2,
-  DMA_CHANNEL3               = 3,
-  DMA_CHANNEL4               = 4,
-  DMA_CHANNEL5               = 5,
-  DMA_CHANNEL6               = 6,
-  DMA_CHANNEL7               = 7
-} lpc_dma_channel_t;
-
- /**
-  * @brief   DMA source or destination type.
-  */
- typedef enum {
-   PERIPHERAL0          = 0,
-   PERIPHERAL1          = 1,
-   PERIPHERAL2          = 2,
-   PERIPHERAL3          = 3,
-   PERIPHERAL4          = 4,
-   PERIPHERAL5          = 5,
-   PERIPHERAL6          = 6,
-   PERIPHERAL7          = 7,
-   PERIPHERAL8          = 8,
-   PERIPHERAL9          = 9,
-   PERIPHERAL10         = 10,
-   PERIPHERAL11         = 11,
-   PERIPHERAL12         = 12,
-   PERIPHERAL13         = 13,
-   PERIPHERAL14         = 14,
-   PERIPHERAL15         = 15
- } lpc_dma_src_dst_t;
-
-/**
- * @brief   LPC DMA ISR function type.
- *
- * @param[in] p         parameter for the registered function
- * @param[in] flags     pre-shifted content of the xISR register, the bits
- *                      are aligned to bit zero
- */
-typedef void (*lpc_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-
-/**
- * @brief   Set dma peripheral connection.
- *
- * @param[in] periphn   dma peripheral connection number
- * @param[in] select    selected peripheral
- *
- * @special
- */
-#define dmaMuxSet(periphn, select)                                          \
-  LPC_CREG->DMAMUX &= ~(3UL << ((periphn) * 2));                            \
-  LPC_CREG->DMAMUX |= (select) << ((periphn) * 2)
-
-/**
- * @brief   Associates a memory source to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] addr      pointer to a source address
- *
- * @special
- */
-#define dmaChannelSrcAddr(dmach, addr)                                     \
-  _lpc_dma_channel_config[dmach]->srcaddr = (uint32_t)(addr)
-
-/**
- * @brief   Associates a memory destination to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] addr      pointer to a destination address
- *
- * @special
- */
-#define dmaChannelDstAddr(dmach, addr)                                    \
-  _lpc_dma_channel_config[dmach]->dstaddr = (uint32_t)(addr)
-
-/**
- * @brief   Associates a linked list item address to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] addr      pointer to a linked list item
- * @param[in] master    AHB master select for loading next LLI, 0 or 1
- *
- * @special
- */
-#define dmaChannelLinkedList(dmach, addr, master)                                 \
-  _lpc_dma_channel_config[dmach]->lli = (((uint32_t)(addr)) | master)
-
-/**
- * @brief   Set control configuration to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] ctrl      control configuration value
- *
- * @special
- */
-#define dmaChannelControl(dmach, ctrl)                                     \
-  _lpc_dma_channel_config[dmach]->control = (ctrl)
-
-/**
- * @brief   Set configuration to a DMA channel.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaStreamAllocate().
- * @post    After use the channel can be released using @p dmaStreamRelease().
- *
- * @param[in] dmach     DMA channel number
- * @param[in] config    dma channel configuration value
- *
- * @special
- */
-#define dmaChannelConfig(dmach, cfg)                                    \
-  _lpc_dma_channel_config[dmach]->config = (cfg)
-
-/**
- * @brief   Trigger DMA software burst transfer request.
- *
- * @param[in] src   peripheral source request
- *
- * @special
- */
-#define dmaSoftBurstRequest(src)                                            \
-  LPC_GPDMA->SOFTBREQ = (1UL << (src))
-
-/**
- * @brief   Trigger DMA software single transfer request.
- *
- * @param[in] src   peripheral source request
- *
- * @special
- */
-#define dmaSoftSingleRequest(src)                                           \
-  LPC_GPDMA->SOFTSREQ = (1UL << (src))
-
-/**
- * @brief   DMA channel enable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- *
- * @special
- */
-#define dmaChannelEnable(dmach)                                            \
-  _lpc_dma_channel_config[dmach]->config |= (DMA_CFG_CH_ENABLE)
-
-/**
- * @brief   DMA channel disable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The channel must have been allocated using @p dmaChannelAllocate().
- * @post    After use the channel can be released using @p dmaChannelRelease().
- *
- * @param[in] dmach     DMA channel number
- *
- * @special
- */
-#define dmaChannelDisable(dmach)                                           \
-  _lpc_dma_channel_config[dmach]->config &= ~(DMA_CFG_CH_ENABLE)
-
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern lpc_dma_channel_config_t * _lpc_dma_channel_config[];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dmaInit(void);
-  bool_t dmaChannelAllocate(lpc_dma_channel_t dmach,
-                           lpc_dmaisr_t func,
-                           void *param);
-  void dmaChannelRelease(lpc_dma_channel_t dmach);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _LPC43xx_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/mac_lld.c b/os/hal/platforms/LPC43xx/mac_lld.c
deleted file mode 100644
index 27799aa6c..000000000
--- a/os/hal/platforms/LPC43xx/mac_lld.c
+++ /dev/null
@@ -1,748 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-  This file has been contributed by:
-                Marcin Jokel.
-  Ported from ChibiOS STM32 mac_lld driver.
-*/
-
-/**
- * @file    LPC43xx/mac_lld.c
- * @brief   LPC43xx low level MAC driver code.
- *
- * @addtogroup MAC
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-#include "mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define BUFFER_SIZE ((((LPC_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
-
-/* MII divider optimal value.*/
-#if (LPC_CLK_M4_ETHERNET >= 150000000)
-#define MAC_MII_ADDR_CR         ETH_MAC_MII_ADDR_CR_DIV_102
-#elif (LPC_CLK_M4_ETHERNET >= 100000000)
-#define MAC_MII_ADDR_CR         ETH_MAC_MII_ADDR_CR_DIV_62
-#elif (LPC_CLK_M4_ETHERNET >= 60000000)
-#define MAC_MII_ADDR_CR         ETH_MAC_MII_ADDR_CR_DIV_42
-#elif (LPC_CLK_M4_ETHERNET >= 35000000)
-#define MAC_MII_ADDR_CR         ETH_MAC_MII_ADDR_CR_DIV_26
-#elif (LPC_CLK_M4_ETHERNET >= 20000000)
-#define MAC_MII_ADDR_CR         ETH_MAC_MII_ADDR_CR_DIV_16
-#else
-#error "LPC_CLK_M4_ETHERNET below minimum frequency for ETH operations (20MHz)"
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Ethernet driver 1.
- */
-MACDriver ETHD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
-                                              0x37, 0x01, 0x10};
-
-static lpc_eth_rx_descriptor_t rd[LPC_MAC_RECEIVE_BUFFERS];
-static lpc_eth_tx_descriptor_t td[LPC_MAC_TRANSMIT_BUFFERS];
-
-static uint32_t rb[LPC_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];
-static uint32_t tb[LPC_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Enable MAC clock.
- */
-static void mac_clk_enable(void) {
-
-    LPC_CGU->BASE_PHY_RX_CLK &= ~(1UL << 0);
-    LPC_CGU->BASE_PHY_TX_CLK &= ~(1UL << 0);
-    LPC_CCU1->CLK_M4_ETHERNET_CFG = 1;
-}
-
-/**
- * @brief   Disable MAC clock.
- */
-static void mac_clk_disable(void) {
-
-    LPC_CGU->BASE_PHY_RX_CLK |= (1UL << 0);
-    LPC_CGU->BASE_PHY_TX_CLK |= (1UL << 0);
-    LPC_CCU1->CLK_M4_ETHERNET_CFG = 0;
-}
-
-/**
- * @brief   Writes a PHY register.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] reg       register number
- * @param[in] value     new register value
- */
-static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) { // OK
-
-  LPC_ETHERNET->MAC_MII_DATA = value;
-  LPC_ETHERNET->MAC_MII_ADDR = macp->phyaddr | (reg << 6) | MAC_MII_ADDR_CR |
-      ETH_MAC_MII_ADDR_W | ETH_MAC_MII_ADDR_GB;
-  while ((LPC_ETHERNET->MAC_MII_ADDR & ETH_MAC_MII_ADDR_GB) != 0)
-    ;
-}
-
-/**
- * @brief   Reads a PHY register.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] reg       register number
- *
- * @return              The PHY register content.
- */
-static uint32_t mii_read(MACDriver *macp, uint32_t reg) { // OK
-
-  LPC_ETHERNET->MAC_MII_ADDR = macp->phyaddr | (reg << 6) | MAC_MII_ADDR_CR | ETH_MAC_MII_ADDR_GB;
-  while ((LPC_ETHERNET->MAC_MII_ADDR & ETH_MAC_MII_ADDR_GB) != 0)
-    ;
-  return LPC_ETHERNET->MAC_MII_DATA;
-}
-
-#if !defined(BOARD_PHY_ADDRESS)
-/**
- * @brief   PHY address detection.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- */
-static void mii_find_phy(MACDriver *macp) { // OK
-  uint32_t i;
-
-#if LPC_MAC_PHY_TIMEOUT > 0
-  halrtcnt_t start = halGetCounterValue();
-  halrtcnt_t timeout  = start + MS2RTT(LPC_MAC_PHY_TIMEOUT);
-  while (halIsCounterWithin(start, timeout)) {
-#endif
-    for (i = 0; i < 31; i++) {
-      macp->phyaddr = i << 11;
-      LPC_ETHERNET->MAC_MII_DATA = (i << 6) | MAC_MII_ADDR_CR;
-      if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
-          ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
-        return;
-      }
-    }
-#if LPC_MAC_PHY_TIMEOUT > 0
-  }
-#endif
-  /* Wrong or defective board.*/
-  chSysHalt();
-}
-#endif
-
-/**
- * @brief   MAC address setup.
- *
- * @param[in] p         pointer to a six bytes buffer containing the MAC
- *                      address
- */
-static void mac_lld_set_address(const uint8_t *p) { // OK
-
-  /* MAC address configuration, only a single address comparator is used,
-     hash table not used.*/
-  LPC_ETHERNET->MAC_ADDR0_HIGH   = ((uint32_t)p[5] << 8) |
-                   ((uint32_t)p[4] << 0);
-  LPC_ETHERNET->MAC_ADDR0_LOW  = ((uint32_t)p[3] << 24) |
-                   ((uint32_t)p[2] << 16) |
-                   ((uint32_t)p[1] << 8) |
-                   ((uint32_t)p[0] << 0);
-  LPC_ETHERNET->MAC_HASHTABLE_HIGH = 0;
-  LPC_ETHERNET->MAC_HASHTABLE_LOW = 0;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-CH_IRQ_HANDLER(Vector54) {  // OK
-  uint32_t dmasr;
-
-  CH_IRQ_PROLOGUE();
-
-  dmasr = LPC_ETHERNET->DMA_STAT;
-  LPC_ETHERNET->DMA_STAT = dmasr; /* Clear status bits.*/
-
-  if (dmasr & ETH_DMA_STAT_RI) {
-    /* Data Received.*/
-    chSysLockFromIsr();
-    chSemResetI(&ETHD1.rdsem, 0);
-#if MAC_USE_EVENTS
-    chEvtBroadcastI(&ETHD1.rdevent);
-#endif
-    chSysUnlockFromIsr();
-  }
-
-  if (dmasr & ETH_DMA_STAT_TI) {
-    /* Data Transmitted.*/
-    chSysLockFromIsr();
-    chSemResetI(&ETHD1.tdsem, 0);
-    chSysUnlockFromIsr();
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level MAC initialization.
- *
- * @notapi
- */
-void mac_lld_init(void) {
-  unsigned i;
-
-  macObjectInit(&ETHD1);
-  ETHD1.link_up = FALSE;
-
-  /* Descriptor tables are initialized in chained mode, note that the first
-     word is not initialized here but in mac_lld_start().*/
-  for (i = 0; i < LPC_MAC_RECEIVE_BUFFERS; i++) {
-    rd[i].rdes1 = LPC_RDES1_RCH | LPC_MAC_BUFFERS_SIZE;
-    rd[i].rdes2 = (uint32_t)rb[i];
-    rd[i].rdes3 = (uint32_t)&rd[(i + 1) % LPC_MAC_RECEIVE_BUFFERS];
-  }
-  for (i = 0; i < LPC_MAC_TRANSMIT_BUFFERS; i++) {
-    td[i].tdes1 = 0;
-    td[i].tdes2 = (uint32_t)tb[i];
-    td[i].tdes3 = (uint32_t)&td[(i + 1) % LPC_MAC_TRANSMIT_BUFFERS];
-  }
-
-  /* Selection of the RMII or MII mode based on info exported by board.h.*/
-
-#if defined(BOARD_PHY_RMII)
-  LPC_CREG->CREG6 |= (4UL << 0);
-#else
-  LPC_CREG->CREG6 &= ~(7UL << 0);
-#endif
-
-  /* Reset of the MAC core.*/
-  LPC_RGU->RESET_CTRL0 = (1UL << 22);
-
-  for (i = 0; i < (LPC_BASE_M4_CLK/IRCOSCCLK + 1); i++)
-    __NOP();        /* Wait. */
-
-  /* MAC clocks temporary activation.*/
-  mac_clk_enable();
-
-  /* PHY address setup.*/
-#if defined(BOARD_PHY_ADDRESS)
-  ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
-#else
-  mii_find_phy(&ETHD1);
-#endif
-
-#if defined(BOARD_PHY_RESET)
-  /* PHY board-specific reset procedure.*/
-  BOARD_PHY_RESET();
-#else
-  /* PHY soft reset procedure.*/
-  mii_write(&ETHD1, MII_BMCR, BMCR_RESET);
-#if defined(BOARD_PHY_RESET_DELAY)
-  halPolledDelay(BOARD_PHY_RESET_DELAY);
-#endif
-  while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)
-    ;
-#endif
-
-#if LPC_MAC_ETH1_CHANGE_PHY_STATE
-  /* PHY in power down mode until the driver will be started.*/
-  mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN);
-#endif
-
-  /* MAC clocks stopped again.*/
-  mac_clk_disable();
-}
-
-/**
- * @brief   Configures and activates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_start(MACDriver *macp) {
-  unsigned i;
-
-  /* Resets the state of all descriptors.*/
-  for (i = 0; i < LPC_MAC_RECEIVE_BUFFERS; i++)
-    rd[i].rdes0 = LPC_RDES0_OWN;
-  macp->rxptr = (lpc_eth_rx_descriptor_t *)rd;
-  for (i = 0; i < LPC_MAC_TRANSMIT_BUFFERS; i++)
-    td[i].tdes0 = LPC_TDES0_TCH;
-  macp->txptr = (lpc_eth_tx_descriptor_t *)td;
-
-  /* MAC clocks activation and commanded reset procedure.*/
-  mac_clk_enable();
-
-  /* PHY in power up mode.*/
-  mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
-
-  LPC_ETHERNET->DMA_BUS_MODE |= ETH_DMA_BUS_MODE_SWR;     /* Software reset. */
-  while(LPC_ETHERNET->DMA_BUS_MODE & ETH_DMA_BUS_MODE_SWR)
-    ;
-
-  /* ISR vector enabled.*/
-  nvicEnableVector(ETHERNET_IRQn,
-                   CORTEX_PRIORITY_MASK(LPC_MAC_ETH1_IRQ_PRIORITY));
-
-  /* MAC configuration.*/
-  LPC_ETHERNET->MAC_FRAME_FILTER = 0;
-  LPC_ETHERNET->MAC_FLOW_CTRL = 0;
-  LPC_ETHERNET->MAC_VLAN_TAG = 0;
-
-  /* MAC address setup.*/
-  if (macp->config->mac_address == NULL)
-    mac_lld_set_address(default_mac_address);
-  else
-    mac_lld_set_address(macp->config->mac_address);
-
-  /* Transmitter and receiver enabled.
-     Note that the complete setup of the MAC is performed when the link
-     status is detected.*/
-  LPC_ETHERNET->MAC_CONFIG = ETH_MAC_CONFIG_RE | ETH_MAC_CONFIG_TE;
-
-  /* DMA configuration:
-     Descriptor chains pointers.*/
-  LPC_ETHERNET->DMA_REC_DES_ADDR = (uint32_t)rd;
-  LPC_ETHERNET->DMA_TRANS_DES_ADDR = (uint32_t)td;
-
-  /* Enabling required interrupt sources.*/
-  LPC_ETHERNET->DMA_STAT = LPC_ETHERNET->DMA_STAT;
-  LPC_ETHERNET->DMA_INT_EN = ETH_DMA_INT_EN_NIE | ETH_DMA_INT_EN_RIE | ETH_DMA_INT_EN_TIE;
-
-  /* DMA general settings.*/
-  LPC_ETHERNET->DMA_BUS_MODE = ETH_DMA_BUS_MODE_AAL | ETH_DMA_BUS_MODE_RPBL(1UL) |
-      ETH_DMA_BUS_MODE_PBL(1UL);
-
-  /* Transmit FIFO flush.*/
-  LPC_ETHERNET->DMA_OP_MODE = ETH_DMA_OP_MODE_FTF;
-  while (LPC_ETHERNET->DMA_OP_MODE & ETH_DMA_OP_MODE_FTF)
-    ;
-
-  /* DMA final configuration and start.*/
-  LPC_ETHERNET->DMA_OP_MODE = ETH_DMA_OP_MODE_TTC_256 | ETH_DMA_OP_MODE_ST |
-      ETH_DMA_OP_MODE_RTC_128 | ETH_DMA_OP_MODE_SR;
-}
-
-/**
- * @brief   Deactivates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_stop(MACDriver *macp) {
-
-  if (macp->state != MAC_STOP) {
-
-    /* MAC and DMA stopped.*/
-    LPC_ETHERNET->MAC_CONFIG = 0;
-    LPC_ETHERNET->DMA_OP_MODE = 0;
-    LPC_ETHERNET->DMA_INT_EN = 0;
-    LPC_ETHERNET->DMA_STAT = LPC_ETHERNET->DMA_STAT;
-
-    /* PHY in power down mode until the driver will be restarted.*/
-    mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
-
-    /* MAC clocks stopped.*/
-    mac_clk_disable();
-
-    /* ISR vector disabled.*/
-    nvicDisableVector(ETHERNET_IRQn);
-  }
-}
-
-/**
- * @brief   Returns a transmission descriptor.
- * @details One of the available transmission descriptors is locked and
- *          returned.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] tdp      pointer to a @p MACTransmitDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                      MACTransmitDescriptor *tdp) {
-  lpc_eth_tx_descriptor_t *tdes;
-
-  if (!macp->link_up)
-    return RDY_TIMEOUT;
-
-  chSysLock();
-
-  /* Get Current TX descriptor.*/
-  tdes = macp->txptr;
-
-  /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
-     another thread.*/
-  if (tdes->tdes0 & (LPC_TDES0_OWN | LPC_TDES0_LOCKED)) {
-    chSysUnlock();
-    return RDY_TIMEOUT;
-  }
-
-  /* Marks the current descriptor as locked using a reserved bit.*/
-  tdes->tdes0 |= LPC_TDES0_LOCKED;
-
-  /* Next TX descriptor to use.*/
-  macp->txptr = (lpc_eth_tx_descriptor_t *)tdes->tdes3;
-
-  chSysUnlock();
-
-  /* Set the buffer size and configuration.*/
-  tdp->offset   = 0;
-  tdp->size     = LPC_MAC_BUFFERS_SIZE;
-  tdp->physdesc = tdes;
-
-  return RDY_OK;
-}
-
-/**
- * @brief   Releases a transmit descriptor and starts the transmission of the
- *          enqueued data as a single frame.
- *
- * @param[in] tdp       the pointer to the @p MACTransmitDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
-
-  chDbgAssert(!(tdp->physdesc->tdes0 & LPC_TDES0_OWN),
-              "mac_lld_release_transmit_descriptor(), #1",
-              "attempt to release descriptor already owned by DMA");
-
-  chSysLock();
-
-  /* Unlocks the descriptor and returns it to the DMA engine.*/
-  tdp->physdesc->tdes1 = tdp->offset;
-  tdp->physdesc->tdes0 = LPC_TDES0_CIC(LPC_MAC_IP_CHECKSUM_OFFLOAD) |
-                         LPC_TDES0_IC | LPC_TDES0_LS | LPC_TDES0_FS |
-                         LPC_TDES0_TCH | LPC_TDES0_OWN;
-
-  /* If the DMA engine is stalled then a restart request is issued.*/
-  if ((LPC_ETHERNET->DMA_STAT & ETH_DMA_STAT_TS) == ETH_DMA_STAT_TS_SUSPEND) {
-    LPC_ETHERNET->DMA_STAT = ETH_DMA_STAT_TU;
-    LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = ETH_DMA_STAT_TU; /* Any value is OK.*/
-  }
-
-  chSysUnlock();
-}
-
-/**
- * @brief   Returns a receive descriptor.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] rdp      pointer to a @p MACReceiveDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                     MACReceiveDescriptor *rdp) {
-  lpc_eth_rx_descriptor_t *rdes;
-
-  chSysLock();
-
-  /* Get Current RX descriptor.*/
-  rdes = macp->rxptr;
-
-  /* Iterates through received frames until a valid one is found, invalid
-     frames are discarded.*/
-  while (!(rdes->rdes0 & LPC_RDES0_OWN)) {
-    if (!(rdes->rdes0 & (LPC_RDES0_AFM | LPC_RDES0_ES))
-#if LPC_MAC_IP_CHECKSUM_OFFLOAD
-        && (rdes->rdes0 & LPC_RDES0_FT)
-        && !(rdes->rdes0 & (LPC_RDES0_IPHCE | LPC_RDES0_PCE))
-#endif
-        && (rdes->rdes0 & LPC_RDES0_FS) && (rdes->rdes0 & LPC_RDES0_LS)) {
-      /* Found a valid one.*/
-      rdp->offset   = 0;
-      rdp->size     = ((rdes->rdes0 & LPC_RDES0_FL_MASK) >> 16) - 4;
-      rdp->physdesc = rdes;
-      macp->rxptr   = (lpc_eth_rx_descriptor_t *)rdes->rdes3;
-
-      chSysUnlock();
-      return RDY_OK;
-    }
-    /* Invalid frame found, purging.*/
-    rdes->rdes0 = LPC_RDES0_OWN;
-    rdes = (lpc_eth_rx_descriptor_t *)rdes->rdes3;
-  }
-
-  /* Next descriptor to check.*/
-  macp->rxptr = rdes;
-
-  chSysUnlock();
-  return RDY_TIMEOUT;
-}
-
-/**
- * @brief   Releases a receive descriptor.
- * @details The descriptor and its buffer are made available for more incoming
- *          frames.
- *
- * @param[in] rdp       the pointer to the @p MACReceiveDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
-
-  chDbgAssert(!(rdp->physdesc->rdes0 & LPC_RDES0_OWN),
-              "mac_lld_release_receive_descriptor(), #1",
-              "attempt to release descriptor already owned by DMA");
-
-  chSysLock();
-
-  /* Give buffer back to the Ethernet DMA.*/
-  rdp->physdesc->rdes0 = LPC_RDES0_OWN;
-
-  /* If the DMA engine is stalled then a restart request is issued.*/
-  if ((LPC_ETHERNET->DMA_STAT & ETH_DMA_STAT_RS) == ETH_DMA_STAT_RS_SUSPEND) {
-    LPC_ETHERNET->DMA_STAT   = ETH_DMA_STAT_RU;
-    LPC_ETHERNET->DMA_REC_POLL_DEMAND = ETH_DMA_STAT_RU; /* Any value is OK.*/
-  }
-
-  chSysUnlock();
-}
-
-/**
- * @brief   Updates and returns the link status.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @return              The link status.
- * @retval TRUE         if the link is active.
- * @retval FALSE        if the link is down.
- *
- * @notapi
- */
-bool_t mac_lld_poll_link_status(MACDriver *macp) {
-  uint32_t maccr, bmsr, bmcr;
-
-  maccr = LPC_ETHERNET->MAC_CONFIG;
-
-  /* PHY CR and SR registers read.*/
-  (void)mii_read(macp, MII_BMSR);
-  bmsr = mii_read(macp, MII_BMSR);
-  bmcr = mii_read(macp, MII_BMCR);
-
-  /* Check on auto-negotiation mode.*/
-  if (bmcr & BMCR_ANENABLE) {
-    uint32_t lpa;
-
-    /* Auto-negotiation must be finished without faults and link established.*/
-    if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
-        (BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
-      return macp->link_up = FALSE;
-
-    /* Auto-negotiation enabled, checks the LPA register.*/
-    lpa = mii_read(macp, MII_LPA);
-
-    /* Check on link speed.*/
-    if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
-      maccr |= ETH_MAC_CONFIG_FES;
-    else
-      maccr &= ~ETH_MAC_CONFIG_FES;
-
-    /* Check on link mode.*/
-    if (lpa & (LPA_10FULL | LPA_100FULL))
-      maccr |= ETH_MAC_CONFIG_DM;
-    else
-      maccr &= ~ETH_MAC_CONFIG_DM;
-  }
-  else {
-    /* Link must be established.*/
-    if (!(bmsr & BMSR_LSTATUS))
-      return macp->link_up = FALSE;
-
-    /* Check on link speed.*/
-    if (bmcr & BMCR_SPEED100)
-      maccr |= ETH_MAC_CONFIG_FES;
-    else
-      maccr &= ~ETH_MAC_CONFIG_FES;
-
-    /* Check on link mode.*/
-    if (bmcr & BMCR_FULLDPLX)
-      maccr |= ETH_MAC_CONFIG_DM;
-    else
-      maccr &= ~ETH_MAC_CONFIG_DM;
-  }
-
-  /* Changes the mode in the MAC.*/
-  LPC_ETHERNET->MAC_CONFIG = maccr;
-
-  /* Returns the link status.*/
-  return macp->link_up = TRUE;
-}
-
-/**
- * @brief   Writes to a transmit descriptor's stream.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf       pointer to the buffer containing the data to be
- *                      written
- * @param[in] size      number of bytes to be written
- * @return              The number of bytes written into the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if the maximum
- *                      frame size is reached.
- *
- * @notapi
- */
-size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                         uint8_t *buf,
-                                         size_t size) {
-
-  chDbgAssert(!(tdp->physdesc->tdes0 & LPC_TDES0_OWN),
-              "mac_lld_write_transmit_descriptor(), #1",
-              "attempt to write descriptor already owned by DMA");
-
-  if (size > tdp->size - tdp->offset)
-    size = tdp->size - tdp->offset;
-
-  if (size > 0) {
-    memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size);
-    tdp->offset += size;
-  }
-  return size;
-}
-
-/**
- * @brief   Reads from a receive descriptor's stream.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[in] buf       pointer to the buffer that will receive the read data
- * @param[in] size      number of bytes to be read
- * @return              The number of bytes read from the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if there are
- *                      no more bytes to read.
- *
- * @notapi
- */
-size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                       uint8_t *buf,
-                                       size_t size) {
-
-  chDbgAssert(!(rdp->physdesc->rdes0 & LPC_RDES0_OWN),
-              "mac_lld_read_receive_descriptor(), #1",
-              "attempt to read descriptor already owned by DMA");
-
-  if (size > rdp->size - rdp->offset)
-    size = rdp->size - rdp->offset;
-
-  if (size > 0) {
-    memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size);
-    rdp->offset += size;
-  }
-  return size;
-}
-
-#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
-/**
- * @brief   Returns a pointer to the next transmit buffer in the descriptor
- *          chain.
- * @note    The API guarantees that enough buffers can be requested to fill
- *          a whole frame.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] size      size of the requested buffer. Specify the frame size
- *                      on the first call then scale the value down subtracting
- *                      the amount of data already copied into the previous
- *                      buffers.
- * @param[out] sizep    pointer to variable receiving the buffer size, it is
- *                      zero when the last buffer has already been returned.
- *                      Note that a returned size lower than the amount
- *                      requested means that more buffers must be requested
- *                      in order to fill the frame data entirely.
- * @return              Pointer to the returned buffer.
- * @retval NULL         if the buffer chain has been entirely scanned.
- *
- * @notapi
- */
-uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
-                                          size_t size,
-                                          size_t *sizep) {
-
-  if (tdp->offset == 0) {
-    *sizep      = tdp->size;
-    tdp->offset = size;
-    return (uint8_t *)tdp->physdesc->tdes2;
-  }
-  *sizep = 0;
-  return NULL;
-}
-
-/**
- * @brief   Returns a pointer to the next receive buffer in the descriptor
- *          chain.
- * @note    The API guarantees that the descriptor chain contains a whole
- *          frame.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[out] sizep    pointer to variable receiving the buffer size, it is
- *                      zero when the last buffer has already been returned.
- * @return              Pointer to the returned buffer.
- * @retval NULL         if the buffer chain has been entirely scanned.
- *
- * @notapi
- */
-const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
-                                               size_t *sizep) {
-
-  if (rdp->size > 0) {
-    *sizep      = rdp->size;
-    rdp->offset = rdp->size;
-    rdp->size   = 0;
-    return (uint8_t *)rdp->physdesc->rdes2;
-  }
-  *sizep = 0;
-  return NULL;
-}
-#endif /* MAC_USE_ZERO_COPY */
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/mac_lld.h b/os/hal/platforms/LPC43xx/mac_lld.h
deleted file mode 100644
index 8f6a1be53..000000000
--- a/os/hal/platforms/LPC43xx/mac_lld.h
+++ /dev/null
@@ -1,687 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-  This file has been contributed by:
-                Marcin Jokel.
-  Ported from ChibiOS STM32 mac_lld driver.
-*/
-
-/**
- * @file    LPC43xx/mac_lld.h
- * @brief   LPC43xx low level MAC driver header.
- *
- * @addtogroup MAC
- * @{
- */
-
-#ifndef _MAC_LLD_H_
-#define _MAC_LLD_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   This implementation supports the zero-copy mode API.
- */
-#define MAC_SUPPORTS_ZERO_COPY      TRUE
-
-/**
- * @name    MAC Configuration register bits
- * @{
- */
-#define ETH_MAC_CONFIG_RE                       (1UL << 2)
-#define ETH_MAC_CONFIG_TE                       (1UL << 3)
-#define ETH_MAC_CONFIG_DF                       (1UL << 4)
-#define ETH_MAC_CONFIG_BL_MIN_N_10              (0UL << 5)
-#define ETH_MAC_CONFIG_BL_MIN_N_8               (1UL << 5)
-#define ETH_MAC_CONFIG_BL_MIN_N_4               (2UL << 5)
-#define ETH_MAC_CONFIG_BL_MIN_N_1               (3UL << 5)
-#define ETH_MAC_CONFIG_ACS                      (1UL << 7)
-#define ETH_MAC_CONFIG_DR                       (1UL << 9)
-#define ETH_MAC_CONFIG_DM                       (1UL << 11)
-#define ETH_MAC_CONFIG_LM                       (1UL << 12)
-#define ETH_MAC_CONFIG_DO                       (1UL << 13)
-#define ETH_MAC_CONFIG_FES                      (1UL << 14)
-#define ETH_MAC_CONFIG_PS                       (1UL << 15)
-#define ETH_MAC_CONFIG_DCRS                     (1UL << 16)
-#define ETH_MAC_CONFIG_IFG_96                   (0UL << 17)
-#define ETH_MAC_CONFIG_IFG_88                   (1UL << 17)
-#define ETH_MAC_CONFIG_IFG_80                   (2UL << 17)
-#define ETH_MAC_CONFIG_IFG_72                   (3UL << 17)
-#define ETH_MAC_CONFIG_IFG_64                   (4UL << 17)
-#define ETH_MAC_CONFIG_IFG_56                   (5UL << 17)
-#define ETH_MAC_CONFIG_IFG_48                   (6UL << 17)
-#define ETH_MAC_CONFIG_IFG_40                   (7UL << 17)
-#define ETH_MAC_CONFIG_JE                       (1UL << 20)
-#define ETH_MAC_CONFIG_JD                       (1UL << 22)
-#define ETH_MAC_CONFIG_WD                       (1UL << 23)
-/** @} */
-
-/**
- * @name    MAC Frame filter register bits
- * @{
- */
-#define ETH_MAC_FRAME_FILTER_PR                 (1UL << 0)
-#define ETH_MAC_FRAME_FILTER_HUC                (1UL << 1)
-#define ETH_MAC_FRAME_FILTER_HMC                (1UL << 2)
-#define ETH_MAC_FRAME_FILTER_DAIF               (1UL << 3)
-#define ETH_MAC_FRAME_FILTER_PM                 (1UL << 4)
-#define ETH_MAC_FRAME_FILTER_DBF                (1UL << 5)
-#define ETH_MAC_FRAME_FILTER_PCF_FILTER_ALL     (1UL << 6)
-#define ETH_MAC_FRAME_FILTER_PCF_FOR_ALL        (1UL << 6)
-#define ETH_MAC_FRAME_FILTER_PCF_FOR_FAIL_ADDR  (1UL << 6)
-#define ETH_MAC_FRAME_FILTER_PCF_FOR_PASS_ADDR  (1UL << 6)
-#define ETH_MAC_FRAME_FILTER_HPF                (1UL << 10)
-#define ETH_MAC_FRAME_FILTER_RA                 (1UL << 31)
-/** @} */
-
-/**
- * @name    MAC MII Address register bits
- * @{
- */
-#define ETH_MAC_MII_ADDR_GB                     (1UL << 0)
-#define ETH_MAC_MII_ADDR_W                      (1UL << 1)
-#define ETH_MAC_MII_ADDR_CR_DIV_42              (0UL << 2)
-#define ETH_MAC_MII_ADDR_CR_DIV_62              (1UL << 2)
-#define ETH_MAC_MII_ADDR_CR_DIV_16              (2UL << 2)
-#define ETH_MAC_MII_ADDR_CR_DIV_26              (3UL << 2)
-#define ETH_MAC_MII_ADDR_CR_DIV_102             (4UL << 2)
-#define ETH_MAC_MII_ADDR_CR_DIV_124             (5UL << 2)
-#define ETH_MAC_MII_ADDR_GR(reg)                ((reg) << 6)
-#define ETH_MAC_MII_ADDR_PA(addr)               ((addr) << 11)
-/** @} */
-
-/**
- * @name     MAC Flow control register bits
- * @{
- */
-#define ETH_MAC_FLOW_CTRL_FCB                   (1UL << 0)
-#define ETH_MAC_FLOW_CTRL_TFE                   (1UL << 1)
-#define ETH_MAC_FLOW_CTRL_RFE                   (1UL << 2)
-#define ETH_MAC_FLOW_CTRL_UP                    (1UL << 3)
-#define ETH_MAC_FLOW_CTRL_PLT(t)                ((t) << 4)
-#define ETH_MAC_FLOW_CTRL_DZPQ                  (1UL << 7)
-#define ETH_MAC_FLOW_CTRL_PT(t)                 ((t) << 16)
-/** @} */
-
-/**
- * @name     MAC VLAN tag register bits
- * @{
- */
-#define ETH_MAC_VLAN_TAG_VL(t)                  ((t) << 0)
-#define ETH_MAC_FLOW_CTRL_ETV                   (1UL << 16)
-/** @} */
-
-/**
- * @name     MAC Debug register bits
- * @{
- */
-#define ETH_MAC_DEBUG_RXIDLESTAT                (1UL << 0)
-#define ETH_MAC_DEBUG_FIFOSTAT0                 (1UL << 1)
-#define ETH_MAC_DEBUG_RXFIFOSTAT1               (1UL << 4)
-#define ETH_MAC_DEBUG_RXFIFOSTAT                (3UL << 5)
-#define ETH_MAC_DEBUG_RXFIFOSTAT_IDLE           (0UL << 5)
-#define ETH_MAC_DEBUG_RXFIFOSTAT_RD_D           (1UL << 5)
-#define ETH_MAC_DEBUG_RXFIFOSTAT_RD_ST          (2UL << 5)
-#define ETH_MAC_DEBUG_RXFIFOSTAT_FLUSH          (3UL << 5)
-#define ETH_MAC_DEBUG_RXFIFOLVL                 (3UL << 8)
-#define ETH_MAC_DEBUG_RXFIFOLVL_EMPTY           (0UL << 8)
-#define ETH_MAC_DEBUG_RXFIFOLVL_BELOW           (1UL << 8)
-#define ETH_MAC_DEBUG_RXFIFOLVL_ABOVE           (2UL << 8)
-#define ETH_MAC_DEBUG_RXFIFOLVL_FULL            (3UL << 8)
-#define ETH_MAC_DEBUG_TXIDLESTAT                (1UL << 16)
-#define ETH_MAC_DEBUG_TXSTAT                    (3UL << 17)
-#define ETH_MAC_DEBUG_TXSTAT_IDLE               (0UL << 17)
-#define ETH_MAC_DEBUG_TXSTAT_WAIT               (1UL << 17)
-#define ETH_MAC_DEBUG_TXSTAT_GEN                (2UL << 17)
-#define ETH_MAC_DEBUG_TXSTAT_TRAN               (3UL << 17)
-#define ETH_MAC_DEBUG_PAUSE                     (1UL << 19)
-#define ETH_MAC_DEBUG_TXFIFOSTAT                (3UL << 20)
-#define ETH_MAC_DEBUG_TXFIFOSTAT_IDLE           (0UL << 20)
-#define ETH_MAC_DEBUG_TXFIFOSTAT_READ           (1UL << 20)
-#define ETH_MAC_DEBUG_TXFIFOSTAT_WAIT           (1UL << 20)
-#define ETH_MAC_DEBUG_TXFIFOSTAT_WRITE          (1UL << 20)
-#define ETH_MAC_DEBUG_TXFIFOSTAT1               (1UL << 22)
-#define ETH_MAC_DEBUG_TXFIFOLVL                 (1UL << 24)
-#define ETH_MAC_DEBUG_TXFIFOFULL                (1UL << 25)
-/** @} */
-
-/**
- * @name      MAC PMT control and status register bits
- * @{
- */
-#define ETH_MAC_PMT_CTRL_STAT_PD                (1UL << 0)
-#define ETH_MAC_PMT_CTRL_STAT_MPE               (1UL << 1)
-#define ETH_MAC_PMT_CTRL_STAT_WFE               (1UL << 2)
-#define ETH_MAC_PMT_CTRL_STAT_MPR               (1UL << 5)
-#define ETH_MAC_PMT_CTRL_STAT_WFR               (1UL << 6)
-#define ETH_MAC_PMT_CTRL_STAT_GU                (1UL << 9)
-#define ETH_MAC_PMT_CTRL_STAT_WFFRPR            (1UL << 31)
-/** @} */
-
-/**
- * @name       MAC Interrupt status register bits
- * @{
- */
-#define ETH_MAC_INTR_PMT                        (1UL << 3)
-#define ETH_MAC_INTR_TS                         (1UL << 9)
-/** @} */
-
-/**
- * @name       MAC Interrupt mask register bits
- * @{
- */
-#define ETH_MAC_INTR_MASK_PMTIM                 (1UL << 3)
-#define ETH_MAC_INTR_MASK_TSIM                  (1UL << 9)
-/** @} */
-
-/**
- * @name        MAC IEEE1588 time stamp control register bits
- * @{
- */
-#define ETH_MAC_TIMESTP_CTRL_TSENA              (1UL << 0)
-#define ETH_MAC_TIMESTP_CTRL_TSCFUPDT           (1UL << 1)
-#define ETH_MAC_TIMESTP_CTRL_TSINIT             (1UL << 2)
-#define ETH_MAC_TIMESTP_CTRL_TSUPDT             (1UL << 3)
-#define ETH_MAC_TIMESTP_CTRL_TSTRIG             (1UL << 4)
-#define ETH_MAC_TIMESTP_CTRL_TSADDREG           (1UL << 5)
-#define ETH_MAC_TIMESTP_CTRL_TSENALL            (1UL << 8)
-#define ETH_MAC_TIMESTP_CTRL_TSCTRLSSR          (1UL << 9)
-#define ETH_MAC_TIMESTP_CTRL_TSVER2ENA          (1UL << 10)
-#define ETH_MAC_TIMESTP_CTRL_TSIPENA            (1UL << 11)
-#define ETH_MAC_TIMESTP_CTRL_TSIPV6ENA          (1UL << 12)
-#define ETH_MAC_TIMESTP_CTRL_TSIPV4ENA          (1UL << 13)
-#define ETH_MAC_TIMESTP_CTRL_TSEVNTENA          (1UL << 14)
-#define ETH_MAC_TIMESTP_CTRL_TSMSTRENA          (1UL << 15)
-#define ETH_MAC_TIMESTP_CTRL_TSCLKTYPE          (3UL << 16)
-#define ETH_MAC_TIMESTP_CTRL_TSCLKTYPE_OCLK     (0UL << 16)
-#define ETH_MAC_TIMESTP_CTRL_TSCLKTYPE_BCLK     (1UL << 16)
-#define ETH_MAC_TIMESTP_CTRL_TSCLKTYPE_ETETCLK  (2UL << 16)
-#define ETH_MAC_TIMESTP_CTRL_TSCLKTYPE_PTPTCLK  (3UL << 16)
-#define ETH_MAC_TIMESTP_CTRL_TSENMACADDR        (1UL << 18)
-/** @} */
-
-/**
- * @name        System time nanoseconds register bits
- * @{
- */
-#define ETH_NANOSECONDS_PSNT                    (1UL << 31)
-/** @} */
-
-/**
- * @name        System time nanoseconds update register bits
- * @{
- */
-#define ETH_NANOSECONDSUPDATE_ADDSUB            (1UL << 31)
-/** @} */
-
-/**
- * @name        Time stamp status register bits
- * @{
- */
-#define ETH_TIMESTAMPSTAT_TSSOVF                (1UL << 0)
-#define ETH_TIMESTAMPSTAT_TSTARGT               (1UL << 1)
-/** @} */
-
-/**
- * @name        DMA Bus mode register bits
- * @{
- */
-#define ETH_DMA_BUS_MODE_SWR                    (1UL << 0)
-#define ETH_DMA_BUS_MODE_DA                     (1UL << 1)
-#define ETH_DMA_BUS_MODE_DSL(len)               ((len) << 2)
-#define ETH_DMA_BUS_MODE_ATDS                   (1UL << 7)
-#define ETH_DMA_BUS_MODE_PBL(len)               ((len) << 8)
-#define ETH_DMA_BUS_MODE_PR                     (3UL << 14)
-#define ETH_DMA_BUS_MODE_PR_1T1                 (0UL << 14)
-#define ETH_DMA_BUS_MODE_PR_2T1                 (1UL << 14)
-#define ETH_DMA_BUS_MODE_PR_3T1                 (2UL << 14)
-#define ETH_DMA_BUS_MODE_PR_4T1                 (3UL << 14)
-#define ETH_DMA_BUS_MODE_FB                     (1UL << 16)
-#define ETH_DMA_BUS_MODE_RPBL(n)                ((n) << 17)
-#define ETH_DMA_BUS_MODE_USP                    (1UL << 23)
-#define ETH_DMA_BUS_MODE_PBL8X                  (1UL << 24)
-#define ETH_DMA_BUS_MODE_AAL                    (1UL << 25)
-#define ETH_DMA_BUS_MODE_MB                     (1UL << 26)
-#define ETH_DMA_BUS_MODE_TXPR                   (1UL << 27)
-/** @} */
-
-/**
- * @name         DMA Status register bits
- * @{
- */
-#define ETH_DMA_STAT_TI                         (1UL << 0)
-#define ETH_DMA_STAT_TPS                        (1UL << 1)
-#define ETH_DMA_STAT_TU                         (1UL << 2)
-#define ETH_DMA_STAT_TJT                        (1UL << 3)
-#define ETH_DMA_STAT_OVF                        (1UL << 4)
-#define ETH_DMA_STAT_UNF                        (1UL << 5)
-#define ETH_DMA_STAT_RI                         (1UL << 6)
-#define ETH_DMA_STAT_RU                         (1UL << 7)
-#define ETH_DMA_STAT_RPS                        (1UL << 8)
-#define ETH_DMA_STAT_RWT                        (1UL << 9)
-#define ETH_DMA_STAT_ETI                        (1UL << 10)
-#define ETH_DMA_STAT_FBI                        (1UL << 13)
-#define ETH_DMA_STAT_ERI                        (1UL << 14)
-#define ETH_DMA_STAT_AIE                        (1UL << 15)
-#define ETH_DMA_STAT_NIS                        (1UL << 16)
-#define ETH_DMA_STAT_RS                         (7UL << 17)
-#define ETH_DMA_STAT_RS_STOP                    (0UL << 17)
-#define ETH_DMA_STAT_RS_RUN_FETCH               (1UL << 17)
-#define ETH_DMA_STAT_RS_RUN_WAIT                (3UL << 17)
-#define ETH_DMA_STAT_RS_SUSPEND                 (4UL << 17)
-#define ETH_DMA_STAT_RS_RUN_CLOSE               (5UL << 17)
-#define ETH_DMA_STAT_RS_TIME_STAMP              (6UL << 17)
-#define ETH_DMA_STAT_RS_RUN_TRANSFER            (7UL << 17)
-#define ETH_DMA_STAT_TS                         (7UL << 20)
-#define ETH_DMA_STAT_TS_STOP                    (0UL << 20)
-#define ETH_DMA_STAT_TS_RUN_FETCH               (1UL << 20)
-#define ETH_DMA_STAT_TS_RUN_WAIT                (2UL << 20)
-#define ETH_DMA_STAT_TS_RUN_READ                (3UL << 20)
-#define ETH_DMA_STAT_TS_TIME_STAMP              (4UL << 20)
-#define ETH_DMA_STAT_TS_SUSPEND                 (6UL << 20)
-#define ETH_DMA_STAT_TS_RUN_CLOSE               (7UL << 20)
-#define ETH_DMA_STAT_EB1                        (1UL << 23)
-#define ETH_DMA_STAT_EB2                        (1UL << 24)
-#define ETH_DMA_STAT_EB3                        (1UL << 25)
-/** @} */
-
-/**
- * @name         DMA Operation mode register bits
- * @{
- */
-#define ETH_DMA_OP_MODE_SR                      (1UL << 1)
-#define ETH_DMA_OP_MODE_OSF                     (1UL << 2)
-#define ETH_DMA_OP_MODE_RTC                     (3UL << 3)
-#define ETH_DMA_OP_MODE_RTC_64                  (0UL << 3)
-#define ETH_DMA_OP_MODE_RTC_32                  (1UL << 3)
-#define ETH_DMA_OP_MODE_RTC_96                  (2UL << 3)
-#define ETH_DMA_OP_MODE_RTC_128                 (3UL << 3)
-#define ETH_DMA_OP_MODE_FUF                     (1UL << 6)
-#define ETH_DMA_OP_MODE_FEF                     (1UL << 7)
-#define ETH_DMA_OP_MODE_ST                      (1UL << 13)
-#define ETH_DMA_OP_MODE_TTC                     (7UL << 14)
-#define ETH_DMA_OP_MODE_TTC_64                  (0UL << 14)
-#define ETH_DMA_OP_MODE_TTC_128                 (1UL << 14)
-#define ETH_DMA_OP_MODE_TTC_192                 (2UL << 14)
-#define ETH_DMA_OP_MODE_TTC_256                 (3UL << 14)
-#define ETH_DMA_OP_MODE_TTC_40                  (4UL << 14)
-#define ETH_DMA_OP_MODE_TTC_32                  (5UL << 14)
-#define ETH_DMA_OP_MODE_TTC_24                  (6UL << 14)
-#define ETH_DMA_OP_MODE_TTC_16                  (7UL << 14)
-#define ETH_DMA_OP_MODE_FTF                     (1UL << 20)
-#define ETH_DMA_OP_MODE_DFF                     (1UL << 24)
-/** @} */
-
-/**
- * @name         DMA Interrupt enable register bits
- * @{
- */
-#define ETH_DMA_INT_EN_TIE                      (1UL << 0)
-#define ETH_DMA_INT_EN_TSE                      (1UL << 1)
-#define ETH_DMA_INT_EN_TUE                      (1UL << 2)
-#define ETH_DMA_INT_EN_TJE                      (1UL << 3)
-#define ETH_DMA_INT_EN_OVE                      (1UL << 4)
-#define ETH_DMA_INT_EN_UNE                      (1UL << 5)
-#define ETH_DMA_INT_EN_RIE                      (1UL << 6)
-#define ETH_DMA_INT_EN_RUE                      (1UL << 7)
-#define ETH_DMA_INT_EN_RSE                      (1UL << 8)
-#define ETH_DMA_INT_EN_RWE                      (1UL << 9)
-#define ETH_DMA_INT_EN_ETE                      (1UL << 10)
-#define ETH_DMA_INT_EN_FBE                      (1UL << 13)
-#define ETH_DMA_INT_EN_ERE                      (1UL << 14)
-#define ETH_DMA_INT_EN_AIE                      (1UL << 15)
-#define ETH_DMA_INT_EN_NIE                      (1UL << 16)
-/** @} */
-
-/**
- * @name         DMA Missed frame and buffer overflow counter register bits
- * @{
- */
-#define ETH_DMA_MFRM_BUFOF_FMC                  0x0000FFFF
-#define ETH_DMA_MFRM_BUFOF_OC                   (1UL << 16)
-#define ETH_DMA_MFRM_BUFOF_FMA                  0x0FFE0000
-#define ETH_DMA_MFRM_BUFOF_OF                   (1UL << 28)
-/** @} */
-
-/**
- * @name    RDES0 constants
- * @{
- */
-#define LPC_RDES0_OWN             0x80000000
-#define LPC_RDES0_AFM             0x40000000
-#define LPC_RDES0_FL_MASK         0x3FFF0000
-#define LPC_RDES0_ES              0x00008000
-#define LPC_RDES0_DESERR          0x00004000
-#define LPC_RDES0_SAF             0x00002000
-#define LPC_RDES0_LE              0x00001000
-#define LPC_RDES0_OE              0x00000800
-#define LPC_RDES0_VLAN            0x00000400
-#define LPC_RDES0_FS              0x00000200
-#define LPC_RDES0_LS              0x00000100
-#define LPC_RDES0_IPHCE           0x00000080
-#define LPC_RDES0_LCO             0x00000040
-#define LPC_RDES0_FT              0x00000020
-#define LPC_RDES0_RWT             0x00000010
-#define LPC_RDES0_RE              0x00000008
-#define LPC_RDES0_DE              0x00000004
-#define LPC_RDES0_CE              0x00000002
-#define LPC_RDES0_PCE             0x00000001
-/** @} */
-
-/**
- * @name    RDES1 constants
- * @{
- */
-#define LPC_RDES1_DIC             0x80000000
-#define LPC_RDES1_RBS2_MASK       0x1FFF0000
-#define LPC_RDES1_RER             0x00008000
-#define LPC_RDES1_RCH             0x00004000
-#define LPC_RDES1_RBS1_MASK       0x00001FFF
-/** @} */
-
-/**
- * @name    TDES0 constants
- * @{
- */
-#define LPC_TDES0_OWN             0x80000000
-#define LPC_TDES0_IC              0x40000000
-#define LPC_TDES0_LS              0x20000000
-#define LPC_TDES0_FS              0x10000000
-#define LPC_TDES0_DC              0x08000000
-#define LPC_TDES0_DP              0x04000000
-#define LPC_TDES0_TTSE            0x02000000
-#define LPC_TDES0_LOCKED          0x01000000 /* NOTE: Pseudo flag.        */
-#define LPC_TDES0_CIC_MASK        0x00C00000
-#define LPC_TDES0_CIC(n)          ((n) << 22)
-#define LPC_TDES0_TER             0x00200000
-#define LPC_TDES0_TCH             0x00100000
-#define LPC_TDES0_TTSS            0x00020000
-#define LPC_TDES0_IHE             0x00010000
-#define LPC_TDES0_ES              0x00008000
-#define LPC_TDES0_JT              0x00004000
-#define LPC_TDES0_FF              0x00002000
-#define LPC_TDES0_IPE             0x00001000
-#define LPC_TDES0_LCA             0x00000800
-#define LPC_TDES0_NC              0x00000400
-#define LPC_TDES0_LCO             0x00000200
-#define LPC_TDES0_EC              0x00000100
-#define LPC_TDES0_VF              0x00000080
-#define LPC_TDES0_CC_MASK         0x00000078
-#define LPC_TDES0_ED              0x00000004
-#define LPC_TDES0_UF              0x00000002
-#define LPC_TDES0_DB              0x00000001
-/** @} */
-
-/**
- * @name    TDES1 constants
- * @{
- */
-#define LPC_TDES1_TBS2_MASK       0x1FFF0000
-#define LPC_TDES1_TBS1_MASK       0x00001FFF
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Number of available transmit buffers.
- */
-#if !defined(LPC_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
-#define LPC_MAC_TRANSMIT_BUFFERS          2
-#endif
-
-/**
- * @brief   Number of available receive buffers.
- */
-#if !defined(LPC_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
-#define LPC_MAC_RECEIVE_BUFFERS           4
-#endif
-
-/**
- * @brief   Maximum supported frame size.
- */
-#if !defined(LPC_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define LPC_MAC_BUFFERS_SIZE              1522
-#endif
-
-/**
- * @brief   PHY detection timeout.
- * @details Timeout, in milliseconds, for PHY address detection, if a PHY
- *          is not detected within the timeout then the driver halts during
- *          initialization. This setting applies only if the PHY address is
- *          not explicitly set in the board header file using
- *          @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
- *          single search path is performed.
- */
-#if !defined(LPC_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
-#define LPC_MAC_PHY_TIMEOUT               100
-#endif
-
-/**
- * @brief   Change the PHY power state inside the driver.
- */
-#if !defined(LPC_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
-#define LPC_MAC_ETH1_CHANGE_PHY_STATE     TRUE
-#endif
-
-/**
- * @brief   ETHD1 interrupt priority level setting.
- */
-#if !defined(LPC_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_MAC_ETH1_IRQ_PRIORITY         13
-#endif
-
-/**
- * @brief   IP checksum offload.
- * @details The following modes are available:
- *          - 0 Function disabled.
- *          - 1 Only IP header checksum calculation and insertion are enabled.
- *          - 2 IP header checksum and payload checksum calculation and
- *              insertion are enabled, but pseudo-header checksum is not
- *              calculated in hardware.
- *          - 3 IP Header checksum and payload checksum calculation and
- *              insertion are enabled, and pseudo-header checksum is
- *              calculated in hardware.
- *          .
- */
-#if !defined(LPC_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
-#define LPC_MAC_IP_CHECKSUM_OFFLOAD       0
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
-#error "LPC_MAC_PHY_TIMEOUT requires the realtime counter service"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of an LPC Ethernet receive descriptor.
- */
-typedef struct {
-  volatile uint32_t     rdes0;
-  volatile uint32_t     rdes1;
-  volatile uint32_t     rdes2;
-  volatile uint32_t     rdes3;
-} lpc_eth_rx_descriptor_t;
-
-/**
- * @brief   Type of an LPC Ethernet transmit descriptor.
- */
-typedef struct {
-  volatile uint32_t     tdes0;
-  volatile uint32_t     tdes1;
-  volatile uint32_t     tdes2;
-  volatile uint32_t     tdes3;
-} lpc_eth_tx_descriptor_t;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief MAC address.
-   */
-  uint8_t               *mac_address;
-  /* End of the mandatory fields.*/
-} MACConfig;
-
-/**
- * @brief   Structure representing a MAC driver.
- */
-struct MACDriver {
-  /**
-   * @brief Driver state.
-   */
-  macstate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const MACConfig       *config;
-  /**
-   * @brief Transmit semaphore.
-   */
-  Semaphore             tdsem;
-  /**
-   * @brief Receive semaphore.
-   */
-  Semaphore             rdsem;
-#if MAC_USE_EVENTS || defined(__DOXYGEN__)
-  /**
-   * @brief Receive event.
-   */
-  EventSource           rdevent;
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Link status flag.
-   */
-  bool_t                link_up;
-  /**
-   * @brief PHY address (pre shifted).
-   */
-  uint32_t phyaddr;
-  /**
-   * @brief Receive next frame pointer.
-   */
-  lpc_eth_rx_descriptor_t *rxptr;
-  /**
-   * @brief Transmit next frame pointer.
-   */
-  lpc_eth_tx_descriptor_t *txptr;
-};
-
-/**
- * @brief   Structure representing a transmit descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current write offset.
-   */
-  size_t                    offset;
-  /**
-   * @brief Available space size.
-   */
-  size_t                    size;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the physical descriptor.
-   */
-  lpc_eth_tx_descriptor_t *physdesc;
-} MACTransmitDescriptor;
-
-/**
- * @brief   Structure representing a receive descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current read offset.
-   */
-  size_t                offset;
-  /**
-   * @brief Available data size.
-   */
-  size_t                size;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the physical descriptor.
-   */
-  lpc_eth_rx_descriptor_t *physdesc;
-} MACReceiveDescriptor;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern MACDriver ETHD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void mac_lld_init(void);
-  void mac_lld_start(MACDriver *macp);
-  void mac_lld_stop(MACDriver *macp);
-  msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                        MACTransmitDescriptor *tdp);
-  void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
-  msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                       MACReceiveDescriptor *rdp);
-  void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
-  bool_t mac_lld_poll_link_status(MACDriver *macp);
-  size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                           uint8_t *buf,
-                                           size_t size);
-  size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                         uint8_t *buf,
-                                         size_t size);
-#if MAC_USE_ZERO_COPY
-  uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
-                                            size_t size,
-                                            size_t *sizep);
-  const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
-                                                 size_t *sizep);
-#endif /* MAC_USE_ZERO_COPY */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _MAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/pal_lld.c b/os/hal/platforms/LPC43xx/pal_lld.c
deleted file mode 100644
index 23de40559..000000000
--- a/os/hal/platforms/LPC43xx/pal_lld.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-  This file has been contributed by:
-                Marcin Jokel.
-*/
-
-/**
- * @file    LPC43xx/pal_lld.c
- * @brief   LPC43xx GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void initgpio(ioportid_t port, const lpc_gpio_setup_t *config) {
-
-	LPC_GPIO_PORT->DIR[port] = config->dir;
-	LPC_GPIO_PORT->MASK[port] = 0;
-	LPC_GPIO_PORT->PIN[port] = config->data;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-/**
- * @brief   LPC43xx I/O ports configuration.
- * @details GPIO unit registers initialization.
- *
- * @param[in] config    the LPC43xx ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  initgpio(GPIO0, &config->P0);
-  initgpio(GPIO1, &config->P1);
-  initgpio(GPIO2, &config->P2);
-  initgpio(GPIO3, &config->P3);
-#if LPC_HAS_GPIO4
-  initgpio(GPIO4, &config->P4);
-#endif
-  initgpio(GPIO5, &config->P5);
-
-#if LPC_HAS_GPIO6
-  initgpio(GPIO6, &config->P6);
-#endif
-
-#if LPC_HAS_GPIO7
-  initgpio(GPIO7, &config->P7);
-#endif
-}
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-uint32_t _pal_lld_readgroup(ioportid_t port,
-                            ioportmask_t mask,
-                            uint32_t offset) {
-
-  uint32_t p;
-
-  LPC_GPIO_PORT->MASK[port] = ~((mask) << offset);
-  p = LPC_GPIO_PORT->MPIN[port];
-  LPC_GPIO_PORT->MASK[port] = 0;
-  return p;
-}
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-void _pal_lld_writegroup(ioportid_t port,
-                         ioportmask_t mask,
-                         uint32_t offset,
-                         uint32_t bits) {
-
-  LPC_GPIO_PORT->MASK[port] = ~((mask) << offset);
-  LPC_GPIO_PORT->MPIN[port] = bits;
-  LPC_GPIO_PORT->MASK[port] = 0;
-}
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    This function does not alter the @p PINSELx registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    LPC_GPIO_PORT->DIR[port] &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    palSetPort(port, PAL_WHOLE_PORT);
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    LPC_GPIO_PORT->DIR[port] |=  mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/pal_lld.h b/os/hal/platforms/LPC43xx/pal_lld.h
deleted file mode 100644
index 29116fc83..000000000
--- a/os/hal/platforms/LPC43xx/pal_lld.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
-  This file has been contributed by:
-                Marcin Jokel.
-*/
-
-/**
- * @file    LPC43xx/pal_lld.h
- * @brief   LPC43xx GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port setup info.
- */
-typedef struct {
-  /** Initial value for PIN register.*/
-  uint32_t      data;
-  /** Initial value for DIR register.*/
-  uint32_t      dir;
-} lpc_gpio_setup_t;
-
-/**
- * @brief   GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    The @p IOCON block is not configured, initially all pins have
- *          enabled pullups and are programmed as GPIO. It is responsibility
- *          of the various drivers to reprogram the pins in the proper mode.
- *          Pins that are not handled by any driver may be programmed in
- *          @p board.c.
- */
-typedef struct {
-  /** @brief GPIO 0 setup data.*/
-  lpc_gpio_setup_t   P0;
-  /** @brief GPIO 1 setup data.*/
-  lpc_gpio_setup_t   P1;
-  /** @brief GPIO 2 setup data.*/
-  lpc_gpio_setup_t   P2;
-  /** @brief GPIO 3 setup data.*/
-  lpc_gpio_setup_t   P3;
-#if LPC_HAS_GPIO4
-  /** @brief GPIO 4 setup data.*/
-  lpc_gpio_setup_t   P4;
-#endif
-  /** @brief GPIO 5 setup data.*/
-  lpc_gpio_setup_t   P5;
-#if LPC_HAS_GPIO6
-  /** @brief GPIO 6 setup data.*/
-  lpc_gpio_setup_t   P6;
-#endif
-#if LPC_HAS_GPIO7
-  /** @brief GPIO 7 setup data.*/
-  lpc_gpio_setup_t   P7;
-#endif
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef uint32_t ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO0 port identifier.
- */
-#define IOPORT1         0
-#define GPIO0           0
-
-/**
- * @brief   GPIO1 port identifier.
- */
-#define IOPORT2         1
-#define GPIO1           1
-
-/**
- * @brief   GPIO2 port identifier.
- */
-#define IOPORT3         2
-#define GPIO2           2
-
-/**
- * @brief   GPIO3 port identifier.
- */
-#define IOPORT4         3
-#define GPIO3           3
-
-/**
- * @brief   GPIO4 port identifier.
- */
-#define IOPORT5         4
-#define GPIO4           4
-
-/**
- * @brief   GPIO5 port identifier.
- */
-#define IOPORT6         5
-#define GPIO5           5
-
-/**
- * @brief   GPIO6 port identifier.
- */
-#define IOPORT7         6
-#define GPIO6           6
-
-/**
- * @brief   GPIO7 port identifier.
- */
-#define IOPORT8         7
-#define GPIO7           7
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) (LPC_GPIO_PORT->PIN[port])
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) (LPC_GPIO_PORT->PIN[port])
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) (LPC_GPIO_PORT->PIN[port] = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) (LPC_GPIO_PORT->SET[port] = (bits))
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) (LPC_GPIO_PORT->CLR[port] = (bits))
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset)                               \
-  _pal_lld_readgroup(port, mask, offset)
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                        \
-  _pal_lld_writegroup(port, mask, offset, bits)
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)                                    \
-  ((bit) == PAL_LOW) ? pal_lld_clearpad(port, pad) :                        \
-  pal_lld_setpad(port, pad)
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-  (LPC_GPIO_PORT->SET[port] = 1UL << (pad))
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-  (LPC_GPIO_PORT->CLR[port] = 1UL << (pad))
-
-/**
- * @brief   Toggles a pad logical state.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad)                                      \
-    (LPC_GPIO_PORT->NOT[port] = 1UL << (pad))
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  uint32_t _pal_lld_readgroup(ioportid_t port,
-                              ioportmask_t mask,
-                              uint32_t offset);
-  void _pal_lld_writegroup(ioportid_t port,
-                           ioportmask_t mask,
-                           uint32_t offset,
-                           uint32_t bits);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/platform.mk b/os/hal/platforms/LPC43xx/platform.mk
deleted file mode 100644
index 16ba4018e..000000000
--- a/os/hal/platforms/LPC43xx/platform.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# List of all the LPC43xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC43xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC43xx/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC43xx/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC43xx/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC43xx/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC43xx/lpc43xx_dma.c \
-              ${CHIBIOS}/os/hal/platforms/LPC43xx/mac_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC43xx/dac_lld.c
-         
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC43xx
diff --git a/os/hal/platforms/LPC43xx/serial_lld.c b/os/hal/platforms/LPC43xx/serial_lld.c
deleted file mode 100644
index 96ea7e3f5..000000000
--- a/os/hal/platforms/LPC43xx/serial_lld.c
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/serial_lld.c
- * @brief   LPC43xx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-#if LPC_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-/** @brief UART1 serial driver identifier.*/
-SerialDriver SD2;
-#endif
-
-#if LPC_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-/** @brief UART2 serial driver identifier.*/
-SerialDriver SD3;
-#endif
-
-#if LPC_SERIAL_USE_UART3 || defined(__DOXYGEN__)
-/** @brief UART3 serial driver identifier.*/
-SerialDriver SD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  LCR_WL8 | LCR_STOP1 | LCR_NOPARITY,
-  FCR_TRIGGER0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   UART initialization.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
-  LPC_USARTn_Type *u = sdp->uart;
-  uint32_t div = 0;
-
-#if LPC_SERIAL_USE_UART0
-  if (&SD1 == sdp) {
-    div = LPC_SERIAL_UART0_PCLK / (config->sc_speed << 4);
-  }
-#endif
-
-#if LPC_SERIAL_USE_UART1
-  if (&SD2 == sdp) {
-    div = LPC_SERIAL_UART1_PCLK / (config->sc_speed << 4);
-  }
-#endif
-
-#if LPC_SERIAL_USE_UART2
-  if (&SD3 == sdp) {
-    div = LPC_SERIAL_UART2_PCLK / (config->sc_speed << 4);
-  }
-#endif
-
-#if LPC_SERIAL_USE_UART3
-  if (&SD4 == sdp) {
-    div = LPC_SERIAL_UART3_PCLK / (config->sc_speed << 4);
-  }
-#endif
-
-  u->LCR = config->sc_lcr | LCR_DLAB;
-  u->DLL = div;
-  u->DLM = div >> 8;
-  u->LCR = config->sc_lcr;
-  u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr;
-  u->ACR = 0;
-  u->FDR = 0x10;
-  u->TER = TER_ENABLE;
-  u->IER = IER_RBR | IER_STATUS;
-}
-
-/**
- * @brief   UART de-initialization.
- *
- * @param[in] u         pointer to an UART I/O block
- */
-static void uart_deinit(LPC_USARTn_Type *u) {
-
-  u->LCR = LCR_DLAB;
-  u->DLL = 1;
-  u->DLM = 0;
-  u->LCR = 0;
-  u->FDR = 0x10;
-  u->IER = 0;
-  u->FCR = FCR_RXRESET | FCR_TXRESET;
-  u->ACR = 0;
-  u->TER = TER_ENABLE;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] err       UART LSR register value
- */
-static void set_error(SerialDriver *sdp, IOREG32 err) {
-  flagsmask_t sts = 0;
-
-  if (err & LSR_OVERRUN)
-    sts |= SD_OVERRUN_ERROR;
-  if (err & LSR_PARITY)
-    sts |= SD_PARITY_ERROR;
-  if (err & LSR_FRAMING)
-    sts |= SD_FRAMING_ERROR;
-  if (err & LSR_BREAK)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- * @note    Tries hard to clear all the pending interrupt sources, we don't
- *          want to go through the whole ISR and have another interrupt soon
- *          after.
- *
- * @param[in] u         pointer to an UART I/O block
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  LPC_USARTn_Type *u = sdp->uart;
-
-  while (TRUE) {
-    switch (u->IIR & IIR_SRC_MASK) {
-    case IIR_SRC_NONE:
-      return;
-    case IIR_SRC_ERROR:
-      set_error(sdp, u->LSR);
-      break;
-    case IIR_SRC_TIMEOUT:
-    case IIR_SRC_RX:
-      chSysLockFromIsr();
-      if (chIQIsEmptyI(&sdp->iqueue))
-        chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
-      chSysUnlockFromIsr();
-      while (u->LSR & LSR_RBR_FULL) {
-        chSysLockFromIsr();
-        if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK)
-          chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
-        chSysUnlockFromIsr();
-      }
-      break;
-    case IIR_SRC_TX:
-      {
-        int i = LPC_SERIAL_FIFO_PRELOAD;
-        do {
-          msg_t b;
-
-          chSysLockFromIsr();
-          b = chOQGetI(&sdp->oqueue);
-          chSysUnlockFromIsr();
-          if (b < Q_OK) {
-            u->IER &= ~IER_THRE;
-            chSysLockFromIsr();
-            chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-            chSysUnlockFromIsr();
-            break;
-          }
-          u->THR = b;
-        } while (--i);
-      }
-      break;
-    default:
-      (void) u->THR;
-      (void) u->RBR;
-    }
-  }
-}
-
-/**
- * @brief   Attempts a TX FIFO preload.
- */
-static void preload(SerialDriver *sdp) {
-  LPC_USARTn_Type *u = sdp->uart;
-
-  if (u->LSR & LSR_THRE) {
-    int i = LPC_SERIAL_FIFO_PRELOAD;
-    do {
-      msg_t b = chOQGetI(&sdp->oqueue);
-      if (b < Q_OK) {
-        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-        return;
-      }
-      u->THR = b;
-    } while (--i);
-  }
-  u->IER |= IER_THRE;
-}
-
-/**
- * @brief   Driver SD1 output notification.
- */
-#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD1);
-}
-#endif
-
-/**
- * @brief   Driver SD2 output notification.
- */
-#if LPC_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD2);
-}
-#endif
-
-/**
- * @brief   Driver SD3 output notification.
- */
-#if LPC_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD3);
-}
-#endif
-
-/**
- * @brief   Driver SD4 output notification.
- */
-#if LPC_SERIAL_USE_UART3 || defined(__DOXYGEN__)
-static void notify4(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD4);
-}
-#endif
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 IRQ handler.
- *
- * @isr
- */
-#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(VectorA0) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   UART1 IRQ handler.
- *
- * @isr
- */
-#if LPC_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(VectorA4) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   UART2 IRQ handler.
- *
- * @isr
- */
-#if LPC_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(VectorA8) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   UART3 IRQ handler.
- *
- * @isr
- */
-#if LPC_SERIAL_USE_UART3 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(VectorAC) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if LPC_SERIAL_USE_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = ( LPC_USARTn_Type*) LPC_USART0;
-#endif
-
-#if LPC_SERIAL_USE_UART1
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.uart = ( LPC_USARTn_Type*) LPC_UART1;
-#endif
-
-#if LPC_SERIAL_USE_UART2
-  sdObjectInit(&SD3, NULL, notify3);
-  SD3.uart = ( LPC_USARTn_Type*) LPC_USART2;
-#endif
-
-#if LPC_SERIAL_USE_UART3
-  sdObjectInit(&SD4, NULL, notify4);
-  SD4.uart = ( LPC_USARTn_Type*) LPC_USART3;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if LPC_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_CCU2->CLK_APB0_USART0_CFG = 1;
-      nvicEnableVector(USART0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC_SERIAL_UART0_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC_SERIAL_USE_UART1
-    if (&SD2 == sdp) {
-      LPC_CCU2->CLK_APB0_UART1_CFG = 1;
-      nvicEnableVector(UART1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC_SERIAL_UART1_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC_SERIAL_USE_UART2
-    if (&SD3 == sdp) {
-      LPC_CCU2->CLK_APB2_USART2_CFG = 1;
-      nvicEnableVector(USART2_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC_SERIAL_UART2_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC_SERIAL_USE_UART3
-    if (&SD4 == sdp) {
-      LPC_CCU2->CLK_APB2_USART3_CFG = 1;
-      nvicEnableVector(USART3_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC_SERIAL_UART3_IRQ_PRIORITY));
-    }
-#endif
-  }
-  uart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the UART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    uart_deinit(sdp->uart);
-#if LPC_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_CCU2->CLK_APB0_USART0_CFG = 0;
-      nvicDisableVector(USART0_IRQn);
-      return;
-    }
-#endif
-
-#if LPC_SERIAL_USE_UART1
-    if (&SD2 == sdp) {
-      LPC_CCU2->CLK_APB0_UART1_CFG = 0;
-      nvicDisableVector(UART1_IRQn);
-      return;
-    }
-#endif
-
-#if LPC_SERIAL_USE_UART2
-    if (&SD3 == sdp) {
-      LPC_CCU2->CLK_APB2_USART2_CFG = 0;
-      nvicDisableVector(USART2_IRQn);
-      return;
-    }
-#endif
-
-#if LPC_SERIAL_USE_UART3
-    if (&SD4 == sdp) {
-      LPC_CCU2->CLK_APB2_USART3_CFG = 0;
-      nvicDisableVector(USART3_IRQn);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/serial_lld.h b/os/hal/platforms/LPC43xx/serial_lld.h
deleted file mode 100644
index cd31566f7..000000000
--- a/os/hal/platforms/LPC43xx/serial_lld.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/serial_lld.h
- * @brief   LPC43xx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define IIR_SRC_MASK    0x0F
-#define IIR_SRC_NONE    0x01
-#define IIR_SRC_MODEM   0x00
-#define IIR_SRC_TX      0x02
-#define IIR_SRC_RX      0x04
-#define IIR_SRC_ERROR   0x06
-#define IIR_SRC_TIMEOUT 0x0C
-
-#define IER_RBR         1
-#define IER_THRE        2
-#define IER_STATUS      4
-
-#define LCR_WL5         0
-#define LCR_WL6         1
-#define LCR_WL7         2
-#define LCR_WL8         3
-#define LCR_STOP1       0
-#define LCR_STOP2       4
-#define LCR_NOPARITY    0
-#define LCR_PARITYODD   0x08
-#define LCR_PARITYEVEN  0x18
-#define LCR_PARITYONE   0x28
-#define LCR_PARITYZERO  0x38
-#define LCR_BREAK_ON    0x40
-#define LCR_DLAB        0x80
-
-#define FCR_ENABLE      1
-#define FCR_RXRESET     2
-#define FCR_TXRESET     4
-#define FCR_TRIGGER0    0
-#define FCR_TRIGGER1    0x40
-#define FCR_TRIGGER2    0x80
-#define FCR_TRIGGER3    0xC0
-
-#define LSR_RBR_FULL    1
-#define LSR_OVERRUN     2
-#define LSR_PARITY      4
-#define LSR_FRAMING     8
-#define LSR_BREAK       0x10
-#define LSR_THRE        0x20
-#define LSR_TEMT        0x40
-#define LSR_RXFE        0x80
-
-#define TER_ENABLE      0x01
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define LPC_SERIAL_USE_UART0            TRUE
-#endif
-
-/**
- * @brief   UART1 driver enable switch.
- * @details If set to @p TRUE the support for UART1 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC_SERIAL_USE_UART1) || defined(__DOXYGEN__)
-#define LPC_SERIAL_USE_UART1            TRUE
-#endif
-
-/**
- * @brief   UART2 driver enable switch.
- * @details If set to @p TRUE the support for UART2 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC_SERIAL_USE_UART2) || defined(__DOXYGEN__)
-#define LPC_SERIAL_USE_UART2            TRUE
-#endif
-
-/**
- * @brief   UART3 driver enable switch.
- * @details If set to @p TRUE the support for UART3 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC_SERIAL_USE_UART3) || defined(__DOXYGEN__)
-#define LPC_SERIAL_USE_UART3            TRUE
-#endif
-
-/**
- * @brief   FIFO preload parameter.
- * @details Configuration parameter, this values defines how many bytes are
- *          preloaded in the HW transmit FIFO for each interrupt, the maximum
- *          value is 16 the minimum is 1.
- * @note    An high value reduces the number of interrupts generated but can
- *          also increase the worst case interrupt response time because the
- *          preload loops.
- */
-#if !defined(LPC_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__)
-#define LPC_SERIAL_FIFO_PRELOAD         16
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(LPC_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_SERIAL_UART0_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   UART1 interrupt priority level setting.
- */
-#if !defined(LPC_SERIAL_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_SERIAL_UART1_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   UART2 interrupt priority level setting.
- */
-#if !defined(LPC_SERIAL_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_SERIAL_UART2_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   UART3 interrupt priority level setting.
- */
-#if !defined(LPC_SERIAL_UART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_SERIAL_UART3_IRQ_PRIORITY   3
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-#if (LPC_SERIAL_FIFO_PRELOAD < 1) || (LPC_SERIAL_FIFO_PRELOAD > 16)
-#error "invalid LPC_SERIAL_FIFO_PRELOAD setting"
-#endif
-
-/**
- * @brief   UART0 clock.
- */
-#define  LPC_SERIAL_UART0_PCLK LPC_BASE_UART0_CLK
-
-/**
- * @brief   UART1 clock.
- */
-#define  LPC_SERIAL_UART1_PCLK LPC_BASE_UART1_CLK
-
-/**
- * @brief   UART2 clock.
- */
-#define  LPC_SERIAL_UART2_PCLK LPC_BASE_UART2_CLK
-
-/**
- * @brief   UART3 clock.
- */
-#define  LPC_SERIAL_UART3_PCLK LPC_BASE_UART3_CLK
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   LPC17xx Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the LCR register.
-   */
-  uint32_t                  sc_lcr;
-  /**
-   * @brief Initialization value for the FCR register.
-   */
-  uint32_t                  sc_fcr;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  LPC_USARTn_Type        *uart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#if LPC_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#if LPC_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-
-#if LPC_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
-extern SerialDriver SD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/spi_lld.c b/os/hal/platforms/LPC43xx/spi_lld.c
deleted file mode 100644
index 8ec56524f..000000000
--- a/os/hal/platforms/LPC43xx/spi_lld.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/spi_lld.c
- * @brief   LPC43xx low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/** @brief SPI2 driver identifier.*/
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Preloads the transmit FIFO.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void ssp_fifo_preload(SPIDriver *spip) {
-  LPC_SSPn_Type *ssp = spip->ssp;
-  uint32_t n = spip->txcnt > LPC_SSP_FIFO_DEPTH ?
-               LPC_SSP_FIFO_DEPTH : spip->txcnt;
-
-  while(((ssp->SR & SR_TNF) != 0) && (n > 0)) {
-    if (spip->txptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        const uint16_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-      else {
-        const uint8_t *p = spip->txptr;
-        ssp->DR = *p++;
-        spip->txptr = p;
-      }
-    }
-    else
-      ssp->DR = 0xFFFFFFFF;
-    n--;
-    spip->txcnt--;
-  }
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void spi_serve_interrupt(SPIDriver *spip) {
-  LPC_SSPn_Type *ssp = spip->ssp;
-
-  if ((ssp->MIS & MIS_ROR) != 0) {
-    /* The overflow condition should never happen because priority is given
-       to receive but a hook macro is provided anyway...*/
-    LPC_SPI_SSP_ERROR_HOOK(spip);
-  }
-  ssp->ICR = ICR_RT | ICR_ROR;
-  while ((ssp->SR & SR_RNE) != 0) {
-    if (spip->rxptr != NULL) {
-      if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) {
-        uint16_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-      else {
-        uint8_t *p = spip->rxptr;
-        *p++ = ssp->DR;
-        spip->rxptr = p;
-      }
-    }
-    else
-      (void)ssp->DR;
-    if (--spip->rxcnt == 0) {
-      chDbgAssert(spip->txcnt == 0,
-                  "spi_serve_interrupt(), #1", "counter out of synch");
-      /* Stops the IRQ sources.*/
-      ssp->IMSC = 0;
-      /* Portable SPI ISR code defined in the high level driver, note, it is
-         a macro.*/
-      _spi_isr_code(spip);
-      return;
-    }
-  }
-  ssp_fifo_preload(spip);
-  if (spip->txcnt == 0)
-    ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__)
-/**
- * @brief   SSP0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector98) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__)
-/**
- * @brief   SSP1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector9C) {
-
-  CH_IRQ_PROLOGUE();
-
-  spi_serve_interrupt(&SPID2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if LPC_SPI_USE_SSP0
-  spiObjectInit(&SPID1);
-  SPID1.ssp = LPC_SSP0;
-#endif /* LPC_SPI_USE_SSP0 */
-
-#if LPC_SPI_USE_SSP1
-  spiObjectInit(&SPID2);
-  SPID2.ssp = LPC_SSP1;
-#endif /* LPC_SPI_USE_SSP0 */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-    /* Clock activation.*/
-#if LPC_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_CCU2->CLK_APB0_SSP0_CFG = 1;
-      nvicEnableVector(SSP0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC_SPI_SSP0_IRQ_PRIORITY));
-    }
-#endif
-#if LPC_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_CCU2->CLK_APB2_SSP1_CFG= 1;
-      nvicEnableVector(SSP1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC_SPI_SSP1_IRQ_PRIORITY));
-    }
-#endif
-  }
-  /* Configuration.*/
-  spip->ssp->CR1  = 0;
-  spip->ssp->ICR  = ICR_RT | ICR_ROR;
-  spip->ssp->CR0  = spip->config->cr0;
-  spip->ssp->CPSR = spip->config->cpsr;
-  spip->ssp->CR1  = CR1_SSE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state != SPI_STOP) {
-    spip->ssp->CR1  = 0;
-    spip->ssp->CR0  = 0;
-    spip->ssp->CPSR = 0;
-#if LPC_SPI_USE_SSP0
-    if (&SPID1 == spip) {
-      LPC_CCU2->CLK_APB0_SSP0_CFG = 0;
-      nvicDisableVector(SSP0_IRQn);
-    }
-#endif
-#if LPC_SPI_USE_SSP1
-    if (&SPID2 == spip) {
-      LPC_CCU2->CLK_APB2_SSP1_CFG= 0;
-      nvicDisableVector(SSP1_IRQn);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->rxptr = NULL;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->rxptr = NULL;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  ssp_fifo_preload(spip);
-  spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->ssp->DR = (uint32_t)frame;
-  while ((spip->ssp->SR & SR_RNE) == 0)
-    ;
-  return (uint16_t)spip->ssp->DR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/spi_lld.h b/os/hal/platforms/LPC43xx/spi_lld.h
deleted file mode 100644
index 0cb2fc4ca..000000000
--- a/os/hal/platforms/LPC43xx/spi_lld.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC43xx/spi_lld.h
- * @brief   LPC43xx low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Hardware FIFO depth.
- */
-#define LPC_SSP_FIFO_DEPTH  8
-
-#define CR0_DSSMASK             0x0F
-#define CR0_DSS4BIT             3
-#define CR0_DSS5BIT             4
-#define CR0_DSS6BIT             5
-#define CR0_DSS7BIT             6
-#define CR0_DSS8BIT             7
-#define CR0_DSS9BIT             8
-#define CR0_DSS10BIT            9
-#define CR0_DSS11BIT            0xA
-#define CR0_DSS12BIT            0xB
-#define CR0_DSS13BIT            0xC
-#define CR0_DSS14BIT            0xD
-#define CR0_DSS15BIT            0xE
-#define CR0_DSS16BIT            0xF
-#define CR0_FRFSPI              0
-#define CR0_FRFSSI              0x10
-#define CR0_FRFMW               0x20
-#define CR0_CPOL                0x40
-#define CR0_CPHA                0x80
-#define CR0_CLOCKRATE(n)        ((n) << 8)
-
-#define CR1_LBM                 1
-#define CR1_SSE                 2
-#define CR1_MS                  4
-#define CR1_SOD                 8
-
-#define SR_TFE                  1
-#define SR_TNF                  2
-#define SR_RNE                  4
-#define SR_RFF                  8
-#define SR_BSY                  16
-
-#define IMSC_ROR                1
-#define IMSC_RT                 2
-#define IMSC_RX                 4
-#define IMSC_TX                 8
-
-#define RIS_ROR                 1
-#define RIS_RT                  2
-#define RIS_RX                  4
-#define RIS_TX                  8
-
-#define MIS_ROR                 1
-#define MIS_RT                  2
-#define MIS_RX                  4
-#define MIS_TX                  8
-
-#define ICR_ROR                 1
-#define ICR_RT                  2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for device SSP0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_SPI_USE_SSP0) || defined(__DOXYGEN__)
-#define LPC_SPI_USE_SSP0                TRUE
-#endif
-
-/**
- * @brief   SPI2 driver enable switch.
- * @details If set to @p TRUE the support for device SSP1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC_SPI_USE_SSP1) || defined(__DOXYGEN__)
-#define LPC_SPI_USE_SSP1                FALSE
-#endif
-
-/**
- * @brief   SSP0 PCLK divider.
- */
-#if !defined(LPC_SPI_SSP0CLKDIV) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP0CLKDIV              1
-#endif
-
-/**
- * @brief   SSP1 PCLK divider.
- */
-#if !defined(LPC_SPI_SSP1CLKDIV) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP1CLKDIV              1
-#endif
-
-/**
- * @brief   SPI0 interrupt priority level setting.
- */
-#if !defined(LPC_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP0_IRQ_PRIORITY       5
-#endif
-
-/**
- * @brief   SPI1 interrupt priority level setting.
- */
-#if !defined(LPC_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP1_IRQ_PRIORITY       5
-#endif
-
-/**
- * @brief   Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(LPC_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__)
-#define LPC_SPI_SSP_ERROR_HOOK(spip)    chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !LPC_SPI_USE_SSP0 && !LPC_SPI_USE_SSP1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-/**
- * @brief   SSP0 clock.
- */
-#define LPC_SPI_SSP0_PCLK               LPC_BASE_SSP0_CLK
-
-/**
- * @brief   SSP1 clock.
- */
-#define LPC_SPI_SSP1_PCLK               LPC_BASE_SSP1_CLK
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief SSP CR0 initialization data.
-   */
-  uint16_t              cr0;
-  /**
-   * @brief SSP CPSR initialization data.
-   */
-  uint32_t              cpsr;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SSP registers block.
-   */
-  LPC_SSPn_Type         *ssp;
-  /**
-   * @brief Number of bytes yet to be received.
-   */
-  uint32_t              rxcnt;
-  /**
-   * @brief Receive pointer or @p NULL.
-   */
-  void                  *rxptr;
-  /**
-   * @brief Number of bytes yet to be transmitted.
-   */
-  uint32_t              txcnt;
-  /**
-   * @brief Transmit pointer or @p NULL.
-   */
-  const void            *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC_SPI_USE_SSP0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if LPC_SPI_USE_SSP1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC43xx/system_LPC43xx.h b/os/hal/platforms/LPC43xx/system_LPC43xx.h
deleted file mode 100644
index a4de111f6..000000000
--- a/os/hal/platforms/LPC43xx/system_LPC43xx.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/**********************************************************************
-* $Id$		system_lpc43xx.h			2011-06-02
-*//**
-* @file		system_lpc43xx.h
-* @brief	Cortex-M3 Device System Header File for NXP lpc43xx Series.
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#ifndef __SYSTEM_lpc43xx_H
-#define __SYSTEM_lpc43xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_lpc43xx_H */
diff --git a/os/hal/platforms/LPC8xx/LPC8xx.h b/os/hal/platforms/LPC8xx/LPC8xx.h
deleted file mode 100644
index 41fe7da21..000000000
--- a/os/hal/platforms/LPC8xx/LPC8xx.h
+++ /dev/null
@@ -1,686 +0,0 @@
-/****************************************************************************
- *   $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694                     $
- *   Project: NXP LPC8xx software example  
- *
- *   Description:
- *     CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for 
- *     NXP LPC800 Device Series 
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-
- * Permission to use, copy, modify, and distribute this software and its 
- * documentation is hereby granted, under NXP Semiconductors' 
- * relevant copyright in the software, without fee, provided that it 
- * is used in conjunction with NXP Semiconductors microcontrollers. This 
- * copyright, permission, and disclaimer notice must appear in all copies of 
- * this code.
-****************************************************************************/
-#ifndef __LPC8xx_H__
-#define __LPC8xx_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
-  This file defines all structures and symbols for LPC8xx:
-    - Registers and bitfields
-    - peripheral base address
-    - PIO definitions
-  @{
-*/
-
-
-/******************************************************************************/
-/*                Processor and Core Peripherals                              */
-/******************************************************************************/
-/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
-  Configuration of the Cortex-M0+ Processor and Core Peripherals
-  @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-typedef enum IRQn
-{
-/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
-  Reset_IRQn                    = -15,    /*!< 1 Reset Vector, invoked on Power up and warm reset*/  
-  NonMaskableInt_IRQn           = -14,    /*!< 2 Non Maskable Interrupt                           */
-  HardFault_IRQn                = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                   */
-  SVCall_IRQn                   = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                     */
-  PendSV_IRQn                   = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                     */
-  SysTick_IRQn                  = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                 */
-
-/******  LPC8xx Specific Interrupt Numbers ********************************************************/
-  SPI0_IRQn                     = 0,        /*!< SPI0                                             */
-  SPI1_IRQn                     = 1,        /*!< SPI1                                             */
-  Reserved0_IRQn                = 2,        /*!< Reserved Interrupt                               */	
-  UART0_IRQn                    = 3,        /*!< USART0                                            */
-  UART1_IRQn                    = 4,        /*!< USART1                                            */
-  UART2_IRQn                    = 5,        /*!< USART2                                            */
-  Reserved1_IRQn                = 6,        /*!< Reserved Interrupt                               */    
-  Reserved2_IRQn                = 7,        /*!< Reserved Interrupt                               */
-  I2C_IRQn                      = 8,        /*!< I2C                                              */
-  SCT_IRQn                      = 9,        /*!< SCT                                              */
-  MRT_IRQn                      = 10,       /*!< MRT                                              */ 
-  CMP_IRQn                      = 11,       /*!< CMP                                              */
-  WDT_IRQn                      = 12,      /*!< WDT                                              */
-  BOD_IRQn                      = 13,       /*!< BOD                                              */
-  Reserved3_IRQn                = 14,       /*!< Reserved Interrupt                               */
-  WKT_IRQn                      = 15,       /*!< WKT Interrupt                                    */
-  Reserved4_IRQn                = 16,       /*!< Reserved Interrupt                               */    
-  Reserved5_IRQn                = 17,       /*!< Reserved Interrupt                               */
-  Reserved6_IRQn                = 18,       /*!< Reserved Interrupt                               */    
-  Reserved7_IRQn                = 19,       /*!< Reserved Interrupt                               */
-  Reserved8_IRQn                = 20,       /*!< Reserved Interrupt                               */    
-  Reserved9_IRQn                = 21,       /*!< Reserved Interrupt                               */
-  Reserved10_IRQn               = 22,       /*!< Reserved Interrupt                               */    
-  Reserved11_IRQn               = 23,       /*!< Reserved Interrupt                               */
-  PININT0_IRQn                  = 24,       /*!< External Interrupt 0                             */
-  PININT1_IRQn                  = 25,       /*!< External Interrupt 1                             */  
-  PININT2_IRQn                  = 26,       /*!< External Interrupt 2                             */
-  PININT3_IRQn                  = 27,       /*!< External Interrupt 3                             */
-  PININT4_IRQn                  = 28,       /*!< External Interrupt 4                             */
-  PININT5_IRQn                  = 29,       /*!< External Interrupt 5                             */
-  PININT6_IRQn                  = 30,       /*!< External Interrupt 6                             */
-  PININT7_IRQn                  = 31,       /*!< External Interrupt 7                             */
-} IRQn_Type;
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
-#define __MPU_PRESENT             0         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-/*@}*/ /* end of group LPC8xx_CMSIS */
-
-
-#include "core_cm0plus.h"                  /* Cortex-M0+ processor and core peripherals          */
-#include "system_LPC8xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral Registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SYSCON) --------------------------------------*/
-/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 System memory remap (R/W) */
-  __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 Peripheral reset control (R/W) */
-  __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 System PLL control (R/W) */
-  __IO uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/W ) */
-       uint32_t RESERVED0[4];
-
-  __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 System oscillator control (R/W) */
-  __IO uint32_t WDTOSCCTRL;             /*!< Offset: 0x024 Watchdog oscillator control (R/W) */            
-       uint32_t RESERVED1[2];
-  __IO uint32_t SYSRSTSTAT;             /*!< Offset: 0x030 System reset status Register (R/W ) */
-       uint32_t RESERVED2[3];
-  __IO uint32_t SYSPLLCLKSEL;           /*!< Offset: 0x040 System PLL clock source select (R/W) */	
-  __IO uint32_t SYSPLLCLKUEN;           /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
-       uint32_t RESERVED3[10];
-
-  __IO uint32_t MAINCLKSEL;             /*!< Offset: 0x070 Main clock source select (R/W) */
-  __IO uint32_t MAINCLKUEN;             /*!< Offset: 0x074 Main clock source update enable (R/W) */
-  __IO uint32_t SYSAHBCLKDIV;           /*!< Offset: 0x078 System AHB clock divider (R/W) */
-       uint32_t RESERVED4[1];
-
-  __IO uint32_t SYSAHBCLKCTRL;          /*!< Offset: 0x080 System AHB clock control (R/W) */
-       uint32_t RESERVED5[4];         
-  __IO uint32_t UARTCLKDIV;             /*!< Offset: 0x094 UART clock divider (R/W) */         
-       uint32_t RESERVED6[18];
-
-  __IO uint32_t CLKOUTSEL;              /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
-  __IO uint32_t CLKOUTUEN;              /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
-  __IO uint32_t CLKOUTDIV;              /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */       
-       uint32_t RESERVED7;
-  __IO uint32_t UARTFRGDIV;             /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */ 
-  __IO uint32_t UARTFRGMULT;             /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */   
-       uint32_t RESERVED8[1];  
-  __IO uint32_t EXTTRACECMD;            /*!< (@ 0x400480FC) External trace buffer command register  */  
-  __IO uint32_t PIOPORCAP0;             /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */  
-       uint32_t RESERVED9[12];
-  __IO uint32_t IOCONCLKDIV[7];       /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
-  __IO uint32_t BODCTRL;                /*!< Offset: 0x150 BOD control (R/W) */
-  __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x154 System tick counter calibration (R/W) */
-       uint32_t RESERVED10[6];
-  __IO uint32_t IRQLATENCY;             /*!< (@ 0x40048170) IRQ delay */
-  __IO uint32_t NMISRC;                 /*!< (@ 0x40048174) NMI Source Control     */
-  __IO uint32_t PINTSEL[8];             /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
-       uint32_t RESERVED11[27];
-  __IO uint32_t STARTERP0;              /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */      
-       uint32_t RESERVED12[3];
-  __IO uint32_t STARTERP1;              /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */      
-       uint32_t RESERVED13[6];
-  __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
-  __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 Power-down states after wake-up (R/W) */        
-  __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 Power-down configuration Register (R/W) */
-       uint32_t RESERVED14[110];
-  __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 Device ID (R/ ) */
-} LPC_SYSCON_TypeDef;
-/*@}*/ /* end of group LPC8xx_SYSCON */
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3  (IOCONFIG)
-  */
-
-typedef struct {                            /*!< (@ 0x40044000) IOCONFIG Structure     */
-  __IO uint32_t PIO0_17;                    /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
-  __IO uint32_t PIO0_13;                    /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
-  __IO uint32_t PIO0_12;                    /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
-  __IO uint32_t PIO0_5;                     /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
-  __IO uint32_t PIO0_4;                     /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
-  __IO uint32_t PIO0_3;                     /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
-  __IO uint32_t PIO0_2;                     /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
-  __IO uint32_t PIO0_11;                    /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
-  __IO uint32_t PIO0_10;                    /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
-  __IO uint32_t PIO0_16;                    /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
-  __IO uint32_t PIO0_15;                    /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
-  __IO uint32_t PIO0_1;                     /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
-  __IO uint32_t Reserved;                   /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
-  __IO uint32_t PIO0_9;                     /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
-  __IO uint32_t PIO0_8;                     /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
-  __IO uint32_t PIO0_7;                     /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
-  __IO uint32_t PIO0_6;                     /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
-  __IO uint32_t PIO0_0;                     /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
-  __IO uint32_t PIO0_14;                    /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
-} LPC_IOCON_TypeDef;
-/*@}*/ /* end of group LPC8xx_IOCON */
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3  (FLASHCTRL)
-  */
-typedef struct {                            /*!< (@ 0x40040000) FLASHCTRL Structure    */
-  __I  uint32_t  RESERVED0[4];
-  __IO uint32_t  FLASHCFG;                          /*!< (@ 0x40040010) Flash configuration register                           */
-  __I  uint32_t  RESERVED1[3];
-  __IO uint32_t  FMSSTART;                          /*!< (@ 0x40040020) Signature start address register                       */
-  __IO uint32_t  FMSSTOP;                           /*!< (@ 0x40040024) Signature stop-address register                        */
-  __I  uint32_t  RESERVED2;
-  __I  uint32_t  FMSW0; 
-} LPC_FLASHCTRL_TypeDef;
-/*@}*/ /* end of group LPC8xx_FLASHCTRL */
-
-
-/*------------- Power Management Unit (PMU) --------------------------*/
-/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t PCON;                   /*!< Offset: 0x000 Power control Register (R/W) */
-  __IO uint32_t GPREG0;                 /*!< Offset: 0x004 General purpose Register 0 (R/W) */
-  __IO uint32_t GPREG1;                 /*!< Offset: 0x008 General purpose Register 1 (R/W) */
-  __IO uint32_t GPREG2;                 /*!< Offset: 0x00C General purpose Register 2 (R/W) */
-  __IO uint32_t GPREG3;                 /*!< Offset: 0x010 General purpose Register 3 (R/W) */
-  __IO uint32_t DPDCTRL;                /*!< Offset: 0x014 Deep power-down control register (R/W) */
-} LPC_PMU_TypeDef;
-/*@}*/ /* end of group LPC8xx_PMU */
-
-
-/*------------- Switch Matrix Port --------------------------*/
-/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port 
-  @{
-*/
-typedef struct
-{
-  union {
-    __IO uint32_t PINASSIGN[9];
-    struct {
-      __IO uint32_t PINASSIGN0;
-      __IO uint32_t PINASSIGN1;
-      __IO uint32_t PINASSIGN2;
-      __IO uint32_t PINASSIGN3;
-      __IO uint32_t PINASSIGN4;
-      __IO uint32_t PINASSIGN5;
-      __IO uint32_t PINASSIGN6;
-      __IO uint32_t PINASSIGN7;
-      __IO uint32_t PINASSIGN8;
-    };
-  };
-  __I  uint32_t  RESERVED0[103];
-  __IO uint32_t  PINENABLE0;
-} LPC_SWM_TypeDef;
-/*@}*/ /* end of group LPC8xx_SWM */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       GPIO_PORT                                      -----
-// ------------------------------------------------------------------------------------------------
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_PORT)
-  */
-
-typedef struct {                            
-  __IO uint8_t B0[18];                   /*!< (@ 0xA0000000) Byte pin registers port 0 */
-  __I  uint16_t RESERVED0[2039];
-  __IO uint32_t W0[18];                  /*!< (@ 0xA0001000) Word pin registers port 0 */
-       uint32_t RESERVED1[1006];
-  __IO uint32_t DIR0;                          /* 0x2000 */
-       uint32_t RESERVED2[31];
-  __IO uint32_t MASK0;                                  /* 0x2080 */
-       uint32_t RESERVED3[31];
-  __IO uint32_t PIN0;                          /* 0x2100 */
-       uint32_t RESERVED4[31];
-  __IO uint32_t MPIN0;                                   /* 0x2180 */
-       uint32_t RESERVED5[31];
-  __IO uint32_t SET0;                         /* 0x2200 */
-       uint32_t RESERVED6[31];
-  __O  uint32_t CLR0;                         /* 0x2280 */
-       uint32_t RESERVED7[31];
-  __O  uint32_t NOT0;                                    /* 0x2300 */
-
-} LPC_GPIO_PORT_TypeDef;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                     PIN_INT                                     -----
-// ------------------------------------------------------------------------------------------------
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (PIN_INT)
-  */
-
-typedef struct {                            /*!< (@ 0xA0004000) PIN_INT Structure */
-  __IO uint32_t ISEL;                       /*!< (@ 0xA0004000) Pin Interrupt Mode register */
-  __IO uint32_t IENR;                       /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
-  __IO uint32_t SIENR;                      /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
-  __IO uint32_t CIENR;                      /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
-  __IO uint32_t IENF;                       /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
-  __IO uint32_t SIENF;                      /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
-  __IO uint32_t CIENF;                      /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
-  __IO uint32_t RISE;                       /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
-  __IO uint32_t FALL;                       /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
-  __IO uint32_t IST;                        /*!< (@ 0xA0004024) Pin Interrupt Status register */
-  __IO uint32_t PMCTRL;                     /*!< (@ 0xA0004028) GPIO pattern match interrupt control register          */
-  __IO uint32_t PMSRC;                      /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
-  __IO uint32_t PMCFG;                      /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
-} LPC_PIN_INT_TypeDef;
-
-
-/*------------- CRC Engine (CRC) -----------------------------------------*/
-/** @addtogroup LPC8xx_CRC 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t MODE;
-  __IO uint32_t SEED;
-  union {
-  __I  uint32_t SUM;
-  __O  uint32_t WR_DATA_DWORD;
-  __O  uint16_t WR_DATA_WORD;
-       uint16_t RESERVED_WORD;
-  __O  uint8_t WR_DATA_BYTE;
-       uint8_t RESERVED_BYTE[3];
-  };
-} LPC_CRC_TypeDef;
-/*@}*/ /* end of group LPC8xx_CRC */
-
-/*------------- Comparator (CMP) --------------------------------------------------*/
-/** @addtogroup LPC8xx_CMP LPC8xx Comparator
-  @{
-*/
-typedef struct {                            /*!< (@ 0x40024000) CMP Structure          */
-  __IO uint32_t  CTRL;                      /*!< (@ 0x40024000) Comparator control register */
-  __IO uint32_t  LAD;                       /*!< (@ 0x40024004) Voltage ladder register */
-} LPC_CMP_TypeDef;
-/*@}*/ /* end of group LPC8xx_CMP */
-
-
-/*------------- Wakeup Timer (WKT) --------------------------------------------------*/
-/** @addtogroup LPC8xx_WKT 
-  @{
-*/
-typedef struct {                            /*!< (@ 0x40028000) WKT Structure          */
-  __IO uint32_t  CTRL;                      /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
-       uint32_t  Reserved[2];
-  __IO uint32_t  COUNT;                     /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
-} LPC_WKT_TypeDef;
-/*@}*/ /* end of group LPC8xx_WKT */
-
-
-/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
-typedef struct {
-__IO uint32_t INTVAL;        							
-__IO uint32_t TIMER;         							
-__IO uint32_t CTRL;          							
-__IO uint32_t STAT;          							
-} MRT_Channel_cfg_Type;
-
-typedef struct {
-  MRT_Channel_cfg_Type Channel[4]; 		
-   uint32_t Reserved0[1]; 				
-  __IO uint32_t IDLE_CH; 			
-  __IO uint32_t IRQ_FLAG; 						
-} LPC_MRT_TypeDef;
-
-
-/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
-/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter 
-  @{
-*/
-/**
-  * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9  (USART)
-  */
-typedef struct
-{
-  __IO uint32_t  CFG;								/* 0x00 */
-  __IO uint32_t  CTRL;
-  __IO uint32_t  STAT;
-  __IO uint32_t  INTENSET;
-  __O  uint32_t  INTENCLR;					/* 0x10 */
-  __I  uint32_t  RXDATA;
-  __I  uint32_t  RXDATA_STAT;
-  __IO uint32_t  TXDATA;
-  __IO uint32_t  BRG;								/* 0x20 */
-  __IO uint32_t  INTSTAT;
-} LPC_USART_TypeDef;
-
-/*@}*/ /* end of group LPC8xx_USART */
-
-
-/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
-/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t  CFG;			    /* 0x00 */
-  __IO uint32_t  DLY;
-  __IO uint32_t  STAT;
-  __IO uint32_t  INTENSET;
-  __O  uint32_t  INTENCLR;		/* 0x10 */
-  __I  uint32_t  RXDAT;
-  __IO uint32_t  TXDATCTL;
-  __IO uint32_t  TXDAT;
-  __IO uint32_t  TXCTRL;		  /* 0x20 */
-  __IO uint32_t  DIV;
-  __I  uint32_t  INTSTAT;
-} LPC_SPI_TypeDef;
-/*@}*/ /* end of group LPC8xx_SPI */
-
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-/** @addtogroup LPC8xx_I2C I2C-Bus Interface 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t  CFG;			  /* 0x00 */
-  __IO uint32_t  STAT;
-  __IO uint32_t  INTENSET;
-  __O  uint32_t  INTENCLR;
-  __IO uint32_t  TIMEOUT;		/* 0x10 */
-  __IO uint32_t  DIV;
-  __IO uint32_t  INTSTAT;
-       uint32_t  Reserved0[1];  
-  __IO uint32_t  MSTCTL;			  /* 0x20 */
-  __IO uint32_t  MSTTIME;
-  __IO uint32_t  MSTDAT;
-       uint32_t  Reserved1[5];
-  __IO uint32_t  SLVCTL;			  /* 0x40 */
-  __IO uint32_t  SLVDAT;
-  __IO uint32_t  SLVADR0;
-  __IO uint32_t  SLVADR1;
-  __IO uint32_t  SLVADR2;			  /* 0x50 */
-  __IO uint32_t  SLVADR3;
-  __IO uint32_t  SLVQUAL0;
-       uint32_t  Reserved2[9];
-  __I  uint32_t  MONRXDAT;			/* 0x80 */		
-} LPC_I2C_TypeDef;
-
-/*@}*/ /* end of group LPC8xx_I2C */
-
-/**
-  * @brief State Configurable Timer (SCT) (SCT)
-  */
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7  (SCT)
-  */
-
-#define CONFIG_SCT_nEV   (6)             /* Number of events */
-#define CONFIG_SCT_nRG   (5)             /* Number of match/compare registers */
-#define CONFIG_SCT_nOU   (4)             /* Number of outputs */
-
-typedef struct
-{
-    __IO  uint32_t CONFIG;              /* 0x000 Configuration Register */
-    union {
-        __IO uint32_t CTRL_U;           /* 0x004 Control Register */
-        struct {
-            __IO uint16_t CTRL_L;       /* 0x004 low control register */
-            __IO uint16_t CTRL_H;       /* 0x006 high control register */
-        };
-    };
-    __IO uint16_t LIMIT_L;              /* 0x008 limit register for counter L */
-    __IO uint16_t LIMIT_H;              /* 0x00A limit register for counter H */
-    __IO uint16_t HALT_L;               /* 0x00C halt register for counter L */
-    __IO uint16_t HALT_H;               /* 0x00E halt register for counter H */
-    __IO uint16_t STOP_L;               /* 0x010 stop register for counter L */
-    __IO uint16_t STOP_H;               /* 0x012 stop register for counter H */
-    __IO uint16_t START_L;              /* 0x014 start register for counter L */
-    __IO uint16_t START_H;              /* 0x016 start register for counter H */
-         uint32_t RESERVED1[10];        /* 0x018-0x03C reserved */
-    union {
-        __IO uint32_t COUNT_U;          /* 0x040 counter register */
-        struct {
-            __IO uint16_t COUNT_L;      /* 0x040 counter register for counter L */
-            __IO uint16_t COUNT_H;      /* 0x042 counter register for counter H */
-        };
-    };
-    __IO uint16_t STATE_L;              /* 0x044 state register for counter L */
-    __IO uint16_t STATE_H;              /* 0x046 state register for counter H */
-    __I  uint32_t INPUT;                /* 0x048 input register */
-    __IO uint16_t REGMODE_L;            /* 0x04C match - capture registers mode register L */
-    __IO uint16_t REGMODE_H;            /* 0x04E match - capture registers mode register H */
-    __IO uint32_t OUTPUT;               /* 0x050 output register */
-    __IO uint32_t OUTPUTDIRCTRL;        /* 0x054 Output counter direction Control Register */
-    __IO uint32_t RES;                  /* 0x058 conflict resolution register */
-         uint32_t RESERVED2[37];        /* 0x05C-0x0EC reserved */
-    __IO uint32_t EVEN;                 /* 0x0F0 event enable register */
-    __IO uint32_t EVFLAG;               /* 0x0F4 event flag register */
-    __IO uint32_t CONEN;                /* 0x0F8 conflict enable register */
-    __IO uint32_t CONFLAG;              /* 0x0FC conflict flag register */
-
-    union {
-        __IO union {                    /* 0x100-... Match / Capture value */
-            uint32_t U;                 /*       SCTMATCH[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTMATCH[i].L  Access to L value */
-                uint16_t H;             /*       SCTMATCH[i].H  Access to H value */
-            };
-        } MATCH[CONFIG_SCT_nRG];
-        __I union {
-            uint32_t U;                 /*       SCTCAP[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTCAP[i].L  Access to H value */
-                uint16_t H;             /*       SCTCAP[i].H  Access to H value */
-            };
-        } CAP[CONFIG_SCT_nRG];
-    };
-
-
-         uint32_t RESERVED3[32-CONFIG_SCT_nRG];      /* ...-0x17C reserved */
-
-    union {
-        __IO uint16_t MATCH_L[CONFIG_SCT_nRG];       /* 0x180-... Match Value L counter */
-        __I  uint16_t CAP_L[CONFIG_SCT_nRG];         /* 0x180-... Capture Value L counter */
-    };
-         uint16_t RESERVED4[32-CONFIG_SCT_nRG];      /* ...-0x1BE reserved */
-    union {
-        __IO uint16_t MATCH_H[CONFIG_SCT_nRG];       /* 0x1C0-... Match Value H counter */
-        __I  uint16_t CAP_H[CONFIG_SCT_nRG];         /* 0x1C0-... Capture Value H counter */
-    };
-		
-         uint16_t RESERVED5[32-CONFIG_SCT_nRG];      /* ...-0x1FE reserved */
-
-		
-    union {
-        __IO union {                    /* 0x200-... Match Reload / Capture Control value */
-            uint32_t U;                 /*       SCTMATCHREL[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTMATCHREL[i].L  Access to L value */
-                uint16_t H;             /*       SCTMATCHREL[i].H  Access to H value */
-            };
-        } MATCHREL[CONFIG_SCT_nRG];
-        __IO union {
-            uint32_t U;                 /*       SCTCAPCTRL[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTCAPCTRL[i].L  Access to H value */
-                uint16_t H;             /*       SCTCAPCTRL[i].H  Access to H value */
-            };
-        } CAPCTRL[CONFIG_SCT_nRG];
-    };
-
-         uint32_t RESERVED6[32-CONFIG_SCT_nRG];      /* ...-0x27C reserved */
-
-    union {
-        __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];    /* 0x280-... Match Reload value L counter */
-        __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];     /* 0x280-... Capture Control value L counter */
-    };
-         uint16_t RESERVED7[32-CONFIG_SCT_nRG];      /* ...-0x2BE reserved */
-    union {
-        __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];    /* 0x2C0-... Match Reload value H counter */
-        __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];     /* 0x2C0-... Capture Control value H counter */
-    };
-         uint16_t RESERVED8[32-CONFIG_SCT_nRG];      /* ...-0x2FE reserved */
-
-    __IO struct {                       /* 0x300-0x3FC  SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
-        uint32_t STATE;                 /* Event State Register */
-        uint32_t CTRL;                  /* Event Control Register */
-    } EVENT[CONFIG_SCT_nEV];
-
-         uint32_t RESERVED9[128-2*CONFIG_SCT_nEV];   /* ...-0x4FC reserved */
-
-    __IO struct {                       /* 0x500-0x57C  SCTOUT[i].SET / SCTOUT[i].CLR */
-        uint32_t SET;                   /* Output n Set Register */
-        uint32_t CLR;                   /* Output n Clear Register */
-    } OUT[CONFIG_SCT_nOU];
-
-         uint32_t RESERVED10[191-2*CONFIG_SCT_nOU];  /* ...-0x7F8 reserved */
-
-    __I  uint32_t MODULECONTENT;        /* 0x7FC Module Content */
-
-} LPC_SCT_TypeDef;
-/*@}*/ /* end of group LPC8xx_SCT */
-
-
-/*------------- Watchdog Timer (WWDT) -----------------------------------------*/
-/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t MOD;                    /*!< Offset: 0x000 Watchdog mode register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
-  __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register (W) */
-  __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R) */
-       uint32_t RESERVED;               /*!< Offset: 0x010 RESERVED                          */
-  __IO uint32_t WARNINT;                /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
-  __IO uint32_t WINDOW;                 /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
-} LPC_WWDT_TypeDef;
-/*@}*/ /* end of group LPC8xx_WDT */
-
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_ROM_BASE          (0x1FFF0000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_AHB_BASE          (0x50000000UL)
-
-/* APB0 peripherals */
-#define LPC_WWDT_BASE         (LPC_APB0_BASE + 0x00000)
-#define LPC_MRT_BASE          (LPC_APB0_BASE + 0x04000)
-#define LPC_WKT_BASE          (LPC_APB0_BASE + 0x08000)
-#define LPC_SWM_BASE          (LPC_APB0_BASE + 0x0C000)
-#define LPC_PMU_BASE          (LPC_APB0_BASE + 0x20000)
-#define LPC_CMP_BASE          (LPC_APB0_BASE + 0x24000)
-
-#define LPC_FLASHCTRL_BASE    (LPC_APB0_BASE + 0x40000)
-#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)
-#define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C_BASE          (LPC_APB0_BASE + 0x50000)
-#define LPC_SPI0_BASE         (LPC_APB0_BASE + 0x58000)
-#define LPC_SPI1_BASE         (LPC_APB0_BASE + 0x5C000)
-#define LPC_USART0_BASE       (LPC_APB0_BASE + 0x64000)
-#define LPC_USART1_BASE       (LPC_APB0_BASE + 0x68000)
-#define LPC_USART2_BASE       (LPC_APB0_BASE + 0x6C000)
-
-/* AHB peripherals                                                            */
-#define LPC_CRC_BASE         (LPC_AHB_BASE + 0x00000)
-#define LPC_SCT_BASE         (LPC_AHB_BASE + 0x04000)
-
-#define LPC_GPIO_PORT_BASE    (0xA0000000)
-#define LPC_PIN_INT_BASE     (LPC_GPIO_PORT_BASE  + 0x4000)
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_WWDT              ((LPC_WWDT_TypeDef   *) LPC_WWDT_BASE  )
-#define LPC_MRT               ((LPC_MRT_TypeDef    *) LPC_MRT_BASE   )
-
-
-#define LPC_WKT               ((LPC_WKT_TypeDef    *) LPC_WKT_BASE   )
-#define LPC_SWM               ((LPC_SWM_TypeDef    *) LPC_SWM_BASE   )
-#define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )
-#define LPC_CMP               ((LPC_CMP_TypeDef    *) LPC_CMP_BASE   )
-
-#define LPC_FLASHCTRL         ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
-#define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )
-#define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
-#define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )
-#define LPC_SPI0              ((LPC_SPI_TypeDef    *) LPC_SPI0_BASE  )
-#define LPC_SPI1              ((LPC_SPI_TypeDef    *) LPC_SPI1_BASE  )
-#define LPC_USART0            ((LPC_USART_TypeDef   *) LPC_USART0_BASE )
-#define LPC_USART1            ((LPC_USART_TypeDef   *) LPC_USART1_BASE )
-#define LPC_USART2            ((LPC_USART_TypeDef   *) LPC_USART2_BASE )
-
-#define LPC_CRC               ((LPC_CRC_TypeDef    *) LPC_CRC_BASE   )
-#define LPC_SCT               ((LPC_SCT_TypeDef    *) LPC_SCT_BASE   )
-
-#define LPC_GPIO_PORT         ((LPC_GPIO_PORT_TypeDef  *) LPC_GPIO_PORT_BASE  )
-#define LPC_PIN_INT          ((LPC_PIN_INT_TypeDef   *) LPC_PIN_INT_BASE  )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __LPC8xx_H__ */
diff --git a/os/hal/platforms/LPC8xx/ext_lld.c b/os/hal/platforms/LPC8xx/ext_lld.c
deleted file mode 100644
index 81e09c717..000000000
--- a/os/hal/platforms/LPC8xx/ext_lld.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/ext_lld.c
- * @brief   LPC8xx EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTD1 driver identifier.
- */
-EXTDriver EXTD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
-  /* Driver initialization.*/
-  extObjectInit(&EXTD1);
-}
-
-/**
- * @brief   Configures and activates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
-  int i;
-
-  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
-  /* Configuration of automatic channels.*/
-  for (i = 0; i < EXT_MAX_CHANNELS; i++)
-    if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
-      ext_lld_channel_enable(extp, i);
-    else
-      ext_lld_channel_disable(extp, i);
-}
-
-/**
- * @brief   Deactivates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-  int i;
-
-  if (extp->state == EXT_ACTIVE)
-    for (i = 0; i < EXT_MAX_CHANNELS; i++)
-      ext_lld_exti_irq_disable(i);
-
-  LPC_PIN_INT->ISEL  = 0;
-  LPC_PIN_INT->CIENR = EXT_CHANNELS_MASK;
-  LPC_PIN_INT->RISE  = EXT_CHANNELS_MASK;
-  LPC_PIN_INT->FALL  = EXT_CHANNELS_MASK;
-  LPC_PIN_INT->IST   = EXT_CHANNELS_MASK;
-
-  /* Leave clock enabled, its shared with GPIO */
-  /*LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<6);*/
-}
-
-/**
- * @brief   Enables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
-  /* program the IOpin for this channel */
-  LPC_SYSCON->PINTSEL[channel] = extp->config->channels[channel].iopin;
-
-  /* Programming edge irq enables */
-  if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
-    LPC_PIN_INT->SIENR =  (1 << channel);
-  else
-    LPC_PIN_INT->CIENR =  (1 << channel);
-
-  if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
-    LPC_PIN_INT->SIENF =  (1 << channel);
-  else
-    LPC_PIN_INT->CIENF =  (1 << channel);
-
-  LPC_PIN_INT->RISE = (1<<channel);
-  LPC_PIN_INT->FALL = (1<<channel);
-  LPC_PIN_INT->IST  = (1<<channel);
-
-  ext_lld_exti_irq_enable( channel );
-}
-
-/**
- * @brief   Disables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-  (void)extp;
-
-  ext_lld_exti_irq_disable(channel);
-
-  LPC_PIN_INT->ISEL &= ~(1 << channel);
-  LPC_PIN_INT->CIENR =  (1 << channel);
-  LPC_PIN_INT->RISE  =  (1 << channel);
-  LPC_PIN_INT->FALL  =  (1 << channel);
-  LPC_PIN_INT->IST   =  (1 << channel);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/ext_lld.h b/os/hal/platforms/LPC8xx/ext_lld.h
deleted file mode 100644
index af0f36b50..000000000
--- a/os/hal/platforms/LPC8xx/ext_lld.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/ext_lld.h
- * @brief   LPC8xx EXT subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_H_
-#define _EXT_LLD_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Available number of EXT channels.
- */
-#define EXT_MAX_CHANNELS    8
-
-/**
- * @brief   Mask of the available channels.
- */
-#define EXT_CHANNELS_MASK   ((1 << EXT_MAX_CHANNELS) - 1)
-
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
-
- * @brief   EXT channel callback reason.
- */
-typedef uint32_t expreason_t;
-
-/**
- * @brief   Type of an EXT generic notification callback.
- *
- * @param[in] extp      pointer to the @p EXPDriver object triggering the
- *                      callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp,
-                              expchannel_t channel,
-                              expreason_t reason);
-
-/**
- * @brief   Channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel mode.
-   */
-  uint8_t              mode;
-  /**
-   * @brief IO Pin.
-   */
-  uint8_t              iopin;
-  /**
-   * @brief Channel callback.
-   */
-  extcallback_t         cb;
-} EXTChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief Channel configurations.
-   */
-  EXTChannelConfig      channels[EXT_MAX_CHANNELS];
-  /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief   Structure representing an EXT driver.
- */
-struct EXTDriver {
-  /**
-   * @brief Driver state.
-   */
-  extstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const EXTConfig           *config;
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_init(void);
-  void ext_lld_start(EXTDriver *extp);
-  void ext_lld_stop(EXTDriver *extp);
-  void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
-  void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/ext_lld_isr.c b/os/hal/platforms/LPC8xx/ext_lld_isr.c
deleted file mode 100644
index 312d61f9f..000000000
--- a/os/hal/platforms/LPC8xx/ext_lld_isr.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/ext_lld_isr.c
- * @brief   LPC8xx EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-static void ext_lld_interrupt( uint32_t n ) {
-  uint32_t reason;
-
-  reason =  ((LPC_PIN_INT->RISE)>> n   ) & 0x01;
-  reason |= ((LPC_PIN_INT->FALL)>>(n-1)) & 0x02;
-  LPC_PIN_INT->RISE = (1<<n);
-  LPC_PIN_INT->FALL = (1<<n);
-  LPC_PIN_INT->IST  = (1<<n);
-  EXTD1.config->channels[n].cb(&EXTD1, n, reason);
-}
-
-/**
- * @brief   EXT[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorA0) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(0);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorA4) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(1);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[2] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorA8) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(2);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[3] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorAC) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(3);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[4] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorB0) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(4);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[5] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorB4) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(5);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[6] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorB8) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(6);
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXT[7] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorBC) {
-
-  CH_IRQ_PROLOGUE();
-  ext_lld_interrupt(7);
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-static const uint8_t LPC8xx_EXT_EXTIn_IRQ_PRIORITY[] =
-    { LPC8xx_EXT_EXTI0_IRQ_PRIORITY,
-      LPC8xx_EXT_EXTI1_IRQ_PRIORITY,
-      LPC8xx_EXT_EXTI2_IRQ_PRIORITY,
-      LPC8xx_EXT_EXTI3_IRQ_PRIORITY,
-      LPC8xx_EXT_EXTI4_IRQ_PRIORITY,
-      LPC8xx_EXT_EXTI5_IRQ_PRIORITY,
-      LPC8xx_EXT_EXTI6_IRQ_PRIORITY,
-      LPC8xx_EXT_EXTI7_IRQ_PRIORITY };
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable( uint32_t exti_n ) {
-
-  nvicEnableVector(PININT0_IRQn + exti_n,
-                   CORTEX_PRIORITY_MASK(LPC8xx_EXT_EXTIn_IRQ_PRIORITY[exti_n]));
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable( uint32_t exti_n ) {
-
-  nvicDisableVector(PININT0_IRQn + exti_n);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/ext_lld_isr.h b/os/hal/platforms/LPC8xx/ext_lld_isr.h
deleted file mode 100644
index c2aa52655..000000000
--- a/os/hal/platforms/LPC8xx/ext_lld_isr.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/ext_lld_isr.h
- * @brief   LPC8xx EXT subsystem low level driver ISR header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_ISR_H_
-#define _EXT_LLD_ISR_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   EXTI0 interrupt priority level setting.
- */
-#if !defined(LPC8xx_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_EXT_EXTI0_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI1 interrupt priority level setting.
- */
-#if !defined(LPC8xx_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_EXT_EXTI1_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI2 interrupt priority level setting.
- */
-#if !defined(LPC8xx_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_EXT_EXTI2_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI3 interrupt priority level setting.
- */
-#if !defined(LPC8xx_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_EXT_EXTI3_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI4 interrupt priority level setting.
- */
-#if !defined(LPC8xx_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_EXT_EXTI4_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI5 interrupt priority level setting.
- */
-#if !defined(LPC8xx_EXT_EXTI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_EXT_EXTI5_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI6 interrupt priority level setting.
- */
-#if !defined(LPC8xx_EXT_EXTI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_EXT_EXTI6_IRQ_PRIORITY      3
-#endif
-
-/**
- * @brief   EXTI7 interrupt priority level setting.
- */
-#if !defined(LPC8xx_EXT_EXTI7_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_EXT_EXTI7_IRQ_PRIORITY      3
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_exti_irq_enable( uint32_t exti_n );
-  void ext_lld_exti_irq_disable( uint32_t exti_n );
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_ISR_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/gpt_lld.c b/os/hal/platforms/LPC8xx/gpt_lld.c
deleted file mode 100644
index 44601272b..000000000
--- a/os/hal/platforms/LPC8xx/gpt_lld.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/gpt_lld.c
- * @brief   LPC8xx GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver identifier.
- * @note    The driver GPT1 allocates MRT channel0 when enabled.
- */
-#if LPC8xx_GPT_USE_MRT0 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief   GPT2 driver identifier.
- * @note    The driver GPT1 allocates MRT channel1 when enabled.
- */
-#if LPC8xx_GPT_USE_MRT1 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief   GPT3 driver identifier.
- * @note    The driver GPT1 allocates MRT channel2 when enabled.
- */
-#if LPC8xx_GPT_USE_MRT2 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/**
- * @brief   GPT4 driver identifier.
- * @note    The driver GPT1 allocates MRT channel3 when enabled.
- */
-#if LPC8xx_GPT_USE_MRT3 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-static uint32_t clk_enabled;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- * @param[in] irq_flag  irq flag bit
- */
-
-static void gpt_lld_serve_interrupt( GPTDriver *gptp ) {
-
-  if (gptp->tmr->STAT & 0x01) {
-    gptp->tmr->STAT |= 0x01;
-
-    if (gptp->state == GPT_ONESHOT) {
-      gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
-    }
-    gptp->config->callback(gptp);
-  }
-  return;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
-
- * @brief   MRT IRQ handler.
- *
- */
-CH_IRQ_HANDLER(Vector68) {
-  CH_IRQ_PROLOGUE();
-  
-#if LPC8xx_GPT_USE_MRT0
-  gpt_lld_serve_interrupt( &GPTD1 );
-#endif
-  
-#if LPC8xx_GPT_USE_MRT1
-  gpt_lld_serve_interrupt( &GPTD2 );
-#endif
-
-#if LPC8xx_GPT_USE_MRT2
-  gpt_lld_serve_interrupt( &GPTD3 );
-#endif
-
-#if LPC8xx_GPT_USE_MRT3
-  gpt_lld_serve_interrupt( &GPTD4 );
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if LPC8xx_GPT_USE_MRT0
-  GPTD1.tmr = &(LPC_MRT->Channel[0]);
-  gptObjectInit(&GPTD1);
-  GPTD1.mask = (1<<0);
-#endif
-
-#if LPC8xx_GPT_USE_MRT1
-  GPTD2.tmr = &(LPC_MRT->Channel[1]);
-  gptObjectInit(&GPTD2);
-  GPTD1.mask = (1<<1);
-#endif
-
-#if LPC8xx_GPT_USE_MRT2
-  GPTD3.tmr = &(LPC_MRT->Channel[2]);
-  gptObjectInit(&GPTD3);
-  GPTD1.mask = (1<<2);
-#endif
-
-#if LPC8xx_GPT_USE_MRT3
-  GPTD4.tmr = &(LPC_MRT->Channel[3]);
-  gptObjectInit(&GPTD4);
-  GPTD1.mask = (1<<3);
-#endif
-
-  clk_enabled = FALSE;
-  return;
-}
-
-/**
- * @brief   Configures and activates a GPT channel.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-
-  if( !clk_enabled ) {
-
-    /* Enable clock & reset MRT */
-    LPC_SYSCON->SYSAHBCLKCTRL |=  (1<<10);
-    LPC_SYSCON->PRESETCTRL    &= ~(1<<7);
-    LPC_SYSCON->PRESETCTRL    |=  (1<<7);
-
-    nvicEnableVector(MRT_IRQn,
-                     CORTEX_PRIORITY_MASK(LPC8xx_GPT_MRT_IRQ_PRIORITY));
-
-    clk_enabled |= gptp->mask;
-  }
-
-  /* Prescaler value calculation.*/
-  gptp->pr = (LPC8xx_SYSCLK / gptp->config->frequency);
-  chDbgAssert((gptp->pr * gptp->config->frequency) == LPC8xx_SYSCLK,
-              "gpt_lld_start(), #1", "invalid frequency");
-
-  /* MRT Channel configuration.*/
-  gptp->tmr->CTRL  = 0;
-  gptp->tmr->STAT |= 1;
-
-}
-
-/**
- * @brief   Deactivates a GPT channel.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
-  /* Shared peripheral - 
-     mark this channel as disabled */
-  clk_enabled &= ~gptp->mask;
-
-  /* All channels disabled? */
-  if( !clk_enabled )
-  {
-    /* Disable periheral */
-    nvicDisableVector(MRT_IRQn);
-    LPC_SYSCON->SYSAHBCLKCTRL &=  ~(1<<10);
-  }
-    
-  return;
-}
-
-/**
- * @brief   Starts the timer in continuous/One shot mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->INTVAL = (1<<31)|((interval*gptp->pr) - 1);
-
-  if (gptp->state == GPT_ONESHOT)
-    gptp->tmr->CTRL = (1<<1)|1;
-  else
-    gptp->tmr->CTRL = 1;
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
-  gptp->tmr->INTVAL = (1<<31);
-  gptp->tmr->CTRL   = 0;
-  gptp->tmr->STAT  |= 1;
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tmr->INTVAL = (1<<31)|((interval*gptp->pr) - 1);
-  gptp->tmr->CTRL = (1<<1);
-
-  while (gptp->tmr->STAT & (1<<1))
-    ;
-
-  gptp->tmr->CTRL   = 0;
-  gptp->tmr->STAT  |= 1;
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/gpt_lld.h b/os/hal/platforms/LPC8xx/gpt_lld.h
deleted file mode 100644
index 73f080f66..000000000
--- a/os/hal/platforms/LPC8xx/gpt_lld.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/gpt_lld.h
- * @brief   LPC8xx GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT1 driver enable switch.
- * @details If set to @p TRUE the support for GPT1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC8xx_GPT_USE_MRT0) || defined(__DOXYGEN__)
-#define LPC8xx_GPT_USE_MRT0              TRUE
-#endif
-
-/**
- * @brief   GPT2 driver enable switch.
- * @details If set to @p TRUE the support for GPT2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC8xx_GPT_USE_MRT1) || defined(__DOXYGEN__)
-#define LPC8xx_GPT_USE_MRT1              FALSE
-#endif
-
-/**
- * @brief   GPT3 driver enable switch.
- * @details If set to @p TRUE the support for GPT3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC8xx_GPT_USE_MRT2) || defined(__DOXYGEN__)
-#define LPC8xx_GPT_USE_MRT2              FALSE
-#endif
-
-/**
- * @brief   GPT4 driver enable switch.
- * @details If set to @p TRUE the support for GPT4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(LPC8xx_GPT_USE_MRT3) || defined(__DOXYGEN__)
-#define LPC8xx_GPT_USE_MRT3              FALSE
-#endif
-
-/**
- * @brief   GPT interrupt priority level setting.
- */
-#if !defined(LPC8xx_GPT_MRT_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_GPT_MRT_IRQ_PRIORITY     2
-#endif
-
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !LPC8xx_GPT_USE_MRT0 && !LPC8xx_GPT_USE_MRT1 &&                   \
-    !LPC8xx_GPT_USE_MRT2 && !LPC8xx_GPT_USE_MRT3
-#error "GPT driver activated but no CT peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the MRT Channelx registers block.
-   */
-  MRT_Channel_cfg_Type           *tmr;
-  /**
-   * @brief Prescaler.
-   */
-  uint32_t                  pr;
-  /**
-   * @brief channel bitmask.
-   */
-  uint32_t                  mask;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Changes the interval of GPT peripheral.
- * @details This function changes the interval of a running GPT unit.
- * @pre     The GPT unit must have been activated using @p gptStart().
- * @pre     The GPT unit must have been running in continuous mode using
- *          @p gptStartContinuous().
- * @post    The GPT unit interval is changed to the new value.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- * @param[in] interval  new cycle time in timer ticks
- * @notapi
- */
-#define gpt_lld_change_interval(gptp, interval)                               \
-  ((gptp)->tmr->INTVAL = ((interval*(gptp)->pr) - 1))
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC8xx_GPT_USE_MRT0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if LPC8xx_GPT_USE_MRT1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if LPC8xx_GPT_USE_MRT2 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#if LPC8xx_GPT_USE_MRT3 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/hal_lld.c b/os/hal/platforms/LPC8xx/hal_lld.c
deleted file mode 100644
index e5170fcc4..000000000
--- a/os/hal/platforms/LPC8xx/hal_lld.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/hal_lld.c
- * @brief   LPC8xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* SysTick initialization using the system clock.*/
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
-  SysTick->LOAD = LPC8xx_SYSCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
- * @brief   LPC8xx clocks and PLL initialization.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void lpc8xx_clock_init(void) {
-  int i;
-
-  /* Enable clocks to IOCON & SWM. */
-  LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<18)|(1<<7));
-
-  /* System oscillator initialization.*/
-#if (LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC)
-  // switch off pull-ups
-  LPC_IOCON->PIO0_8   &= ~(3<<3);
-  LPC_IOCON->PIO0_9   &= ~(3<<3);
-
-  // enable xtalin/xtalout
-  LPC_SWM->PINENABLE0 &= ~(3<<4);
-
-  LPC_SYSCON->SYSOSCCTRL = LPC8xx_SYSOSCCTRL;
-  LPC_SYSCON->PDRUNCFG &= ~(1<<5);              /* System oscillator ON.    */
-  for (i = 0; i<200; i++)
-    __NOP();                                    /* Stabilization delay.     */
-#endif
-
-  /* CLKIN initialization.*/
-#if (LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_CLKIN)
-  // switch off pull-up
-  LPC_IOCON->PIO0_1   &= ~(3<<3);
-
-  // enable clkin
-  LPC_SWM->PINENABLE0 &= ~(1<<7);
-#endif
-
-  /* Always set PLL clock source - 
-     PLL IN can be a main clock source */
-  LPC_SYSCON->SYSPLLCLKSEL = LPC8xx_PLLCLK_SOURCE;
-  LPC_SYSCON->SYSPLLCLKUEN = 1;
-  while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01));     /* Wait Until Updated       */
-
-  /* PLL initialization.*/
-#if LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-  LPC_SYSCON->SYSPLLCTRL = LPC8xx_SYSPLLCTRL_MSEL | LPC8xx_SYSPLLCTRL_PSEL;
-  LPC_SYSCON->PDRUNCFG &= ~(1<<7);            /* System PLL ON.           */
-  while (!(LPC_SYSCON->SYSPLLSTAT & 1))      /* Wait PLL lock.           */
-    ;
-#endif
-
-#if LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
-#error "WatchDog Oscillator not configured! Dont use as main clock source"
-  LPC_SYSCON->WDTOSCCTRL = ??;
-  LPC_SYSCON->PDRUNCFG  &= ~(1<<6);        /* WDT OSC On       */
-  for (i = 0; i<200; i++)
-    __NOP();                                    /* Stabilization delay.     */
-#endif
-
-  /* Flash wait states setting, the code takes care to not touch TBD bits.*/
-  LPC_FLASHCTRL->FLASHCFG = (LPC_FLASHCTRL->FLASHCFG & ~1) |
-                              LPC8xx_FLASHCFG_FLASHTIM;
-
-  /* ABH divider initialization. Set this **before** switching Main clock
-     source to ensure AHB clock stays in spec */
-  LPC_SYSCON->SYSAHBCLKDIV = LPC8xx_SYSABHCLK_DIV;
-
-  /* Main clock source selection.*/
-  LPC_SYSCON->MAINCLKSEL = LPC8xx_MAINCLK_SOURCE;
-  LPC_SYSCON->MAINCLKUEN = 1;
-  while (!(LPC_SYSCON->MAINCLKUEN & 1));     /* Wait switch completion.  */
-
-  /* Disable clocks to IOCON, SWM, FLASHREG & ROM. */
-  LPC_SYSCON->SYSAHBCLKCTRL &= ~((1<<18)|(1<<7)|(1<<3)|(1<<1));
-
-}
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/hal_lld.h b/os/hal/platforms/LPC8xx/hal_lld.h
deleted file mode 100644
index 4f9c06dd2..000000000
--- a/os/hal/platforms/LPC8xx/hal_lld.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/hal_lld.h
- * @brief   HAL subsystem low level driver header template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "LPC8xx.h"
-#include "nvic.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME           "LPC8xx"
-
-#define IRCOSCCLK               12000000    /**< High speed internal clock. */
-#define WDGOSCCLK               ???????     /**< Watchdog internal clock.   */
-
-#define SYSPLLCLKSEL_IRCOSC     0           /**< Internal RC oscillator
-                                                 clock source.              */
-#define SYSPLLCLKSEL_SYSOSC     1           /**< System oscillator clock
-                                                 source.                    */
-#define SYSPLLCLKSEL_CLKIN      3           /**< External CLKIN clock
-                                                 source.                    */
-
-#define SYSMAINCLKSEL_IRCOSC    0           /**< Clock source is IRC.       */
-#define SYSMAINCLKSEL_PLLIN     1           /**< Clock source is PLLIN.     */
-#define SYSMAINCLKSEL_WDGOSC    2           /**< Clock source is WDGOSC.    */
-#define SYSMAINCLKSEL_PLLOUT    3           /**< Clock source is PLLOUT.    */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   System PLL clock source.
- */
-#if !defined(LPC8xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC8xx_PLLCLK_SOURCE               SYSPLLCLKSEL_IRCOSC
-#endif
-
-/**
- * @brief   System PLL multiplier.
- * @note    The value must be in the 1..32 range and the final frequency
- *          must not exceed the CCO ratings.
- */
-#if !defined(LPC8xx_SYSPLL_MUL) || defined(__DOXYGEN__)
-#define LPC8xx_SYSPLL_MUL                  4
-#endif
-
-/**
- * @brief   System PLL divider.
- * @note    The value must be chosen between (2, 4, 8, 16).
- */
-#if !defined(LPC8xx_SYSPLL_DIV) || defined(__DOXYGEN__)
-#define LPC8xx_SYSPLL_DIV                  4
-#endif
-
-/**
- * @brief   System main clock source.
- */
-#if !defined(LPC8xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC8xx_MAINCLK_SOURCE              SYSMAINCLKSEL_PLLOUT
-#endif
-
-/**
- * @brief   AHB clock divider.
- * @note    The value must be chosen between (1...255).
- */
-#if !defined(LPC8xx_SYSABHCLK_DIV) || defined(__DOXYGEN__)
-#define LPC8xx_SYSABHCLK_DIV               1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Calculated SYSOSCCTRL setting.
- */
-#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__)
-#define LPC8xx_SYSOSCCTRL      0
-#else
-#define LPC8xx_SYSOSCCTRL      2
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
-#define LPC8xx_SYSPLLCLKIN     SYSOSCCLK
-#elif LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC
-#define LPC8xx_SYSPLLCLKIN     IRCOSCCLK
-#elif LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_CLKIN
-#define LPC8xx_SYSPLLCLKIN     CLKINCLK
-#else
-#error "invalid LPC8xx_PLLCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   MSEL mask in SYSPLLCTRL register.
- */
-#if (LPC8xx_SYSPLL_MUL >= 1) && (LPC8xx_SYSPLL_MUL <= 32) ||              \
-    defined(__DOXYGEN__)
-#define LPC8xx_SYSPLLCTRL_MSEL (LPC8xx_SYSPLL_MUL - 1)
-#else
-#error "LPC8xx_SYSPLL_MUL out of range (1...32)"
-#endif
-
-/**
- * @brief   PSEL mask in SYSPLLCTRL register.
- */
-#if (LPC8xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
-#define LPC8xx_SYSPLLCTRL_PSEL (0 << 5)
-#elif LPC8xx_SYSPLL_DIV == 4
-#define LPC8xx_SYSPLLCTRL_PSEL (1 << 5)
-#elif LPC8xx_SYSPLL_DIV == 8
-#define LPC8xx_SYSPLLCTRL_PSEL (2 << 5)
-#elif LPC8xx_SYSPLL_DIV == 16
-#define LPC8xx_SYSPLLCTRL_PSEL (3 << 5)
-#else
-#error "invalid LPC8xx_SYSPLL_DIV value (2,4,8,16)"
-#endif
-
-/**
- * @brief   CCO frequency.
- */
-#define  LPC8xx_SYSPLLCCO   (LPC8xx_SYSPLLCLKIN * LPC8xx_SYSPLL_MUL *    \
-                              LPC8xx_SYSPLL_DIV)
-
-#if (LPC8xx_SYSPLLCCO < 156000000) || (LPC8xx_SYSPLLCCO > 320000000)
-#error "CCO frequency out of the acceptable range (156...320MHz)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define  LPC8xx_SYSPLLCLKOUT   (LPC8xx_SYSPLLCCO / LPC8xx_SYSPLL_DIV)
-
-#if (LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__)
-#define LPC8xx_MAINCLK     IRCOSCCLK
-#elif LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
-#define LPC8xx_MAINCLK     LPC8xx_SYSPLLCLKIN
-#elif LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
-#define LPC8xx_MAINCLK     WDGOSCCLK
-#elif LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
-#define LPC8xx_MAINCLK     LPC8xx_SYSPLLCLKOUT
-#else
-#error "invalid LPC8xx_MAINCLK_SOURCE clock source specified"
-#endif
-
-/**
- * @brief   AHB clock.
- */
-#define  LPC8xx_SYSCLK     (LPC8xx_MAINCLK / LPC8xx_SYSABHCLK_DIV)
-#if LPC8xx_SYSCLK > 30000000
-#error "AHB clock frequency out of the acceptable range (30MHz max)"
-#endif
-
-/**
- * @brief   Flash wait states.
- */
-#if (LPC8xx_SYSCLK <= 20000000) || defined(__DOXYGEN__)
-#define LPC8xx_FLASHCFG_FLASHTIM   0
-#else
-#define LPC8xx_FLASHCFG_FLASHTIM   1
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void lpc8xx_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/pal_lld.c b/os/hal/platforms/LPC8xx/pal_lld.c
deleted file mode 100644
index 7f290db8f..000000000
--- a/os/hal/platforms/LPC8xx/pal_lld.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/pal_lld.c
- * @brief   LPC8xx GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-/**
- * @brief   LPC8xx I/O ports configuration.
- * @details GPIO unit registers initialization.
- *
- * @param[in] config    the LPC8xx ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  /* Enable clocks to GPIO */
-  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
-
-  LPC_GPIO_PORT->DIR0 = config->dir;
-  LPC_GPIO_PORT->PIN0 = config->data;
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- *          high state.
- * @note    This function does not alter the @p PINSELx registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-                           
-  switch (mode)
-  {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    port->DIR0 &= ~mask;
-    break;
-
-  case PAL_MODE_UNCONNECTED:
-    palSetPort(port, PAL_WHOLE_PORT);
-    //no break
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->DIR0 |=  mask;
-    break;
-  }
-
-  return;
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/pal_lld.h b/os/hal/platforms/LPC8xx/pal_lld.h
deleted file mode 100644
index f90932fa2..000000000
--- a/os/hal/platforms/LPC8xx/pal_lld.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/pal_lld.h
- * @brief   LPC8xx GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port setup info.
- */
-
-/**
- * @brief   GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    The @p IOCON block is not configured, initially all pins have
- *          enabled pullups and are programmed as GPIO. It is responsibility
- *          of the various drivers to reprogram the pins in the proper mode.
- *          Pins that are not handled by any driver may be programmed in
- *          @p board.c.
- */
-typedef struct {
-  /** Initial value for FIO_PIN register.*/
-  uint32_t      data;
-  /** Initial value for FIO_DIR register.*/
-  uint32_t      dir;
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of the I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0x3FFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef LPC_GPIO_PORT_TypeDef *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO0 port identifier.
- */
-#define IOPORT1         LPC_GPIO_PORT
-#define GPIO0           LPC_GPIO_PORT
-
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->PIN0)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->SET0)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->PIN0 = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->SET0 = (bits))
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) ((port)->CLR0 = (bits))
-
-
-/**
- * @brief   Toggles a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
-
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be XORed on the specified port
- *
- * @api
- */
-#define pal_lld_toggleport(port, bits) ((port)->NOT0 = (bits))
-
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                        \
-  (port)->MASK0 = (~(mask) << (offset));                                     \
-  (port)->MPIN0 = ((bits) << (offset))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)                                    \
-  ((port)->W0[(pad)] = (bit))
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-  ((port)->W0[(pad)] = 1)
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-  ((port)->W0[(pad)] = 0)
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/platform.dox b/os/hal/platforms/LPC8xx/platform.dox
deleted file mode 100644
index 85b60bcad..000000000
--- a/os/hal/platforms/LPC8xx/platform.dox
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup LPC8xx LPC8xx Drivers
- * @details This section describes all the supported drivers on the LPC8xx
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup LPC8xx_HAL LPC8xx Initialization Support
- * @details The LPC8xx HAL support is responsible for system initialization.
- *
- * @section lpc8xx_hal_1 Supported HW resources
- * - SYSCON.
- * - Flash.
- * .
- * @section lpc8xx_hal_2 LPC8xx HAL driver implementation features
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash controller initialization.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * .
- * @ingroup LPC8xx
- */
-
-/**
- * @defgroup LPC8xx_GPT LPC8xx GPT Support
- * @details The LPC8xx GPT driver uses the MRT peripheral.
- *
- * @section lpc8xx_gpt_1 Supported HW resources
- * - MRT.
- * .
- * @section lpc8xx_gpt_2 LPC8xx GPT driver implementation features
- * - Each timer can be independently enabled and programmed.
- * - Programmable MRT interrupt priority level.
- * .
- * @ingroup LPC8xx
- */
-
-/**
- * @defgroup LPC8xx_PAL LPC8xx PAL Support
- * @details The LPC8xx PAL driver uses the GPIO peripheral.
- *
- * @section lpc8xx_pal_1 Supported HW resources
- * - GPIO_PORT.
- * .
- * @section lpc8xx_pal_2 LPC8xx PAL driver implementation features
- * - 18 bits wide ports.
- * - Atomic set/reset functions.
- * - Atomic Toggle functions.
- * - Atomic set+reset function (atomic bus operations).
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section lpc8xx_pal_3 Supported PAL setup modes
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section lpc8xx_pal_4 Suboptimal behavior
- * Some GPIO features are less than optimal:
- * - Group operations are not atomic.
- * - Pull-up and Pull-down resistors cannot be programmed through the PAL
- *   driver and must be programmed separately using the IOCON peripheral.
- * .
- * @ingroup LPC8xx
- */
-
-/**
- * @defgroup LPC8xx_SERIAL LPC8xx Serial Support
- * @details The LPC8xx Serial driver uses the UART peripheral in a
- *          buffered, interrupt driven, implementation.
- *
- * @section lpc8xx_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - UART.
- * .
- * @section lpc8xx_serial_2 LPC8xx Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Fully interrupt driven.
- * - Programmable priority level.
- * .
- * @ingroup LPC8xx
- */
-
diff --git a/os/hal/platforms/LPC8xx/platform.mk b/os/hal/platforms/LPC8xx/platform.mk
deleted file mode 100644
index 31f20d16c..000000000
--- a/os/hal/platforms/LPC8xx/platform.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# List of all the LPC8xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC8xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC8xx/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC8xx/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC8xx/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC8xx/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC8xx/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/LPC8xx/ext_lld_isr.c 
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC8xx
diff --git a/os/hal/platforms/LPC8xx/serial_lld.c b/os/hal/platforms/LPC8xx/serial_lld.c
deleted file mode 100644
index e9b53dc72..000000000
--- a/os/hal/platforms/LPC8xx/serial_lld.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/serial_lld.c
- * @brief   LPC8xx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC8xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-#if LPC8xx_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-/** @brief UART1 serial driver identifier.*/
-SerialDriver SD2;
-#endif
-
-#if LPC8xx_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-/** @brief UART2 serial driver identifier.*/
-SerialDriver SD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  (CFG_DL8 | CFG_NOPARITY | CFG_STOP1)
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] err       UART STAT register value
- */
-static void set_error(SerialDriver *sdp, IOREG32 err) {
-  flagsmask_t sts = 0;
-
-  if (err & STAT_OVERRUN)
-    sts |= SD_OVERRUN_ERROR;
-  if (err & STAT_PARITYERR)
-    sts |= SD_PARITY_ERROR;
-  if (err & STAT_FRAMERR)
-    sts |= SD_FRAMING_ERROR;
-  if (err & STAT_RXBRK)
-    sts |= SD_BREAK_DETECTED;
-
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();  
-}
-
-/**
- * @brief   Common IRQ handler.
- * @note    Tries hard to clear all the pending interrupt sources, we don't
- *          want to go through the whole ISR and have another interrupt soon
- *          after.
- *
- * @param[in] u         pointer to an UART I/O block
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  LPC_USART_TypeDef *u = sdp->uart;
-
-  while (u->INTSTAT) {
-
-    if (u->INTSTAT & STAT_RXRDY) {
-      chSysLockFromIsr();
-      if (chIQIsEmptyI(&sdp->iqueue))
-        chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
-      if (chIQPutI(&sdp->iqueue, u->RXDATA) < Q_OK)
-        chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
-      chSysUnlockFromIsr();
-    }
-
-    if (u->INTSTAT & STAT_TXRDY) {
-      msg_t b;
-
-      chSysLockFromIsr();
-      b = chOQGetI(&sdp->oqueue);
-      chSysUnlockFromIsr();
-
-      if (b < Q_OK) {
-        u->INTENCLR = STAT_TXRDY;
-        chSysLockFromIsr();
-        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-        chSysUnlockFromIsr();
-        break;
-      }
-      else {
-         u->TXDATA = b;
-      }
-    }
-
-    if (u->INTSTAT & (STAT_OVERRUN | STAT_DELTARXBRK |
-                      STAT_FRAMERR | STAT_PARITYERR) ) {
-      IOREG32 stat = u->STAT;
-      set_error(sdp, stat);
-      u->STAT = stat;
-    }
-
-  }
-}
-
-/**
- * @brief   Attempts a TX preload.
- */
-static void preload(SerialDriver *sdp) {
-  LPC_USART_TypeDef *u = sdp->uart;
-
-  if (u->STAT & STAT_TXIDLE) {
-    msg_t b = chOQGetI(&sdp->oqueue);
-    if (b < Q_OK) {
-      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-      return;
-    }
-    u->TXDATA = b;
-  }
-  u->INTENSET = STAT_TXRDY;
-}
-
-/**
- * @brief   Driver output notification.
- */
-#if LPC8xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD1);
-}
-#endif
-
-#if LPC8xx_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD2);
-}
-#endif
-
-#if LPC8xx_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
-  (void)qp;
-  preload(&SD3);
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UARTn IRQ handlers.
- *
- * @isr
- */
-#if LPC8xx_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector4C) {
-
-  CH_IRQ_PROLOGUE();
-  serve_interrupt( &SD1 );
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#if LPC8xx_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector50) {
-
-  CH_IRQ_PROLOGUE();
-  serve_interrupt( &SD2 );
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#if LPC8xx_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Vector54) {
-
-  CH_IRQ_PROLOGUE();
-  serve_interrupt( &SD3 );
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if LPC8xx_SERIAL_USE_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = LPC_USART0;
-#endif
-
-#if LPC8xx_SERIAL_USE_UART1
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.uart = LPC_USART1;
-#endif
-
-#if LPC8xx_SERIAL_USE_UART2
-  sdObjectInit(&SD3, NULL, notify3);
-  SD3.uart = LPC_USART2;
-#endif
-
-  /* Reset fractional baudrate generator */
-  LPC_SYSCON->PRESETCTRL &= ~(1<<2);
-  LPC_SYSCON->PRESETCTRL |=  (1<<2);
-
-  LPC_SYSCON->UARTCLKDIV  = LPC8xx_SERIAL_UARTCLKDIV;
-  LPC_SYSCON->UARTFRGDIV  = LPC8xx_SERIAL_UARTFRGDIV;
-  LPC_SYSCON->UARTFRGMULT = LPC8xx_SERIAL_UARTFRGMULT;
-
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start( SerialDriver *sdp, const SerialConfig *config ) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-
-#if LPC8xx_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1<<14);           // Enable Clk
-      LPC_SYSCON->PRESETCTRL &= ~(1<<3);              // Reset peripheral
-      LPC_SYSCON->PRESETCTRL |=  (1<<3);
-      nvicEnableVector(UART0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC8xx_SERIAL_UART0_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC8xx_SERIAL_USE_UART1
-    if (&SD2 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1<<15);           // Enable Clk
-      LPC_SYSCON->PRESETCTRL &= ~(1<<4);              // Reset peripheral
-      LPC_SYSCON->PRESETCTRL |=  (1<<4);
-      nvicEnableVector(UART1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC8xx_SERIAL_UART1_IRQ_PRIORITY));
-    }
-#endif
-
-#if LPC8xx_SERIAL_USE_UART2
-    if (&SD3 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);           // Enable Clk
-      LPC_SYSCON->PRESETCTRL &= ~(1<<5);              // Reset peripheral
-      LPC_SYSCON->PRESETCTRL |=  (1<<5);
-      nvicEnableVector(UART2_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC8xx_SERIAL_UART2_IRQ_PRIORITY));
-    }
-#endif
-
-  }
-
-  sdp->uart->BRG = (LPC8xx_SERIAL_U_PCLK / (config->sc_speed << 4)) -1;
-  sdp->uart->INTENSET = STAT_FRAMERR | STAT_OVERRUN |
-                        STAT_PARITYERR | STAT_DELTARXBRK |
-                        STAT_RXRDY; 
-  sdp->uart->CFG = config->sc_cfg | CFG_ENA;
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the UART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop( SerialDriver *sdp ) {
-
-  if (sdp->state == SD_READY) {
-    sdp->uart->INTENCLR = STAT_TXRDY | STAT_RXRDY; 
-    sdp->uart->CFG = 0;
-
-#if LPC8xx_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<12);
-      nvicDisableVector(UART0_IRQn);
-      return;
-    }
-#endif
-
-#if LPC8xx_SERIAL_USE_UART1
-    if (&SD2 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<13);
-      nvicDisableVector(UART1_IRQn);
-      return;
-    }
-#endif
-
-#if LPC8xx_SERIAL_USE_UART2
-    if (&SD3 == sdp) {
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<14);
-      nvicDisableVector(UART2_IRQn);
-      return;
-    }
-#endif
-
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/serial_lld.h b/os/hal/platforms/LPC8xx/serial_lld.h
deleted file mode 100644
index 915c4e27e..000000000
--- a/os/hal/platforms/LPC8xx/serial_lld.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/serial_lld.h
- * @brief   LPC8xx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define CFG_ENA               0x0001
-#define CFG_DL7               0x0000
-#define CFG_DL8               0x0004
-#define CFG_DL9               0x0008
-#define CFG_NOPARITY          0x0000
-#define CFG_PARITYEVEN        0x0020
-#define CFG_PARITYODD         0x0030
-#define CFG_STOP1             0x0000
-#define CFG_STOP2             0x0040
-#define CFG_CTSEN             0x0200
-#define CFG_SYNCEN            0x0800
-#define CFG_CLKPOL_FALL       0x0000
-#define CFG_CLKPOL_RISE       0x1000
-#define CFG_SYNC_SLV          0x0000
-#define CFG_SYNC_MAST         0x4000
-#define CFG_LOOP_EN           0x8000
-
-#define CTRL_TXBRKEN          0x0002
-#define CTRL_ADDRDET          0x0004
-#define CTRL_TXDIS            0x0040
-#define CTRL_CC               0x0100
-#define CTRL_CLRCC            0x0200
-
-#define STAT_RXRDY            0x0001
-#define STAT_RXIDLE           0x0002
-#define STAT_TXRDY            0x0004
-#define STAT_TXIDLE           0x0008
-#define STAT_CTS              0x0010
-#define STAT_DELTACTS         0x0020
-#define STAT_TXDIS            0x0040
-#define STAT_OVERRUN          0x0100
-#define STAT_RXBRK            0x0400
-#define STAT_DELTARXBRK       0x0800
-#define STAT_START            0x1000
-#define STAT_FRAMERR          0x2000
-#define STAT_PARITYERR        0x4000
-#define STAT_RXNOISE          0x8000
-
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(LPC8xx_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define LPC8xx_SERIAL_USE_UART0            TRUE
-#endif
-
-/**
- * @brief   UART1 driver enable switch.
- * @details If set to @p TRUE the support for UART1 is included.
- * @note    The default is @p FALSE .
- */
-#if !defined(LPC8xx_SERIAL_USE_UART1) || defined(__DOXYGEN__)
-#define LPC8xx_SERIAL_USE_UART1            FALSE
-#endif
-
-/**
- * @brief   UART2 driver enable switch.
- * @details If set to @p TRUE the support for UART2 is included.
- * @note    The default is @p FALSE .
- */
-#if !defined(LPC8xx_SERIAL_USE_UART2) || defined(__DOXYGEN__)
-#define LPC8xx_SERIAL_USE_UART2            FALSE
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(LPC8xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_SERIAL_UART0_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   UART1 interrupt priority level setting.
- */
-#if !defined(LPC8xx_SERIAL_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_SERIAL_UART1_IRQ_PRIORITY   3
-#endif
-
-/**
- * @brief   UART2 interrupt priority level setting.
- */
-#if !defined(LPC8xx_SERIAL_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_SERIAL_UART2_IRQ_PRIORITY   3
-#endif
-
-
-/**
- * @brief   Uart Baud Clock (U_PCLK).
- * @details The Baud clock rate we would like to achieve.
- * @note    The default is @p 11.0592MHz.
- *          A multiple of 1.8432MHz will give accurate
- *          results at all standard baud rates  .
- */
-#if !defined(LPC8xx_SERIAL_U_PCLK) || defined(__DOXYGEN__)
-#define LPC8xx_SERIAL_U_PCLK           11059200
-#endif
-
-/**
- * @brief   UARTCLKDIV divider.
- */
-#if !defined(LPC8xx_SERIAL_UARTCLKDIV) || defined(__DOXYGEN__)
-#define LPC8xx_SERIAL_UARTCLKDIV      (LPC8xx_MAINCLK/LPC8xx_SERIAL_U_PCLK)
-#endif
-
-// Output from uart clock divider
-#define LPC8xx_UARTDIVCLK             (LPC8xx_MAINCLK/LPC8xx_SERIAL_UARTCLKDIV)
-
-/**
- * @brief   UARTFRGDIV
- * @details Fractional Baud rate generator denominator.
- * @note    If used, *must* be set to 256, otherwise set to 0
- */
-#if !defined(LPC8xx_SERIAL_UARTFRGDIV) || defined(__DOXYGEN__)
- #if (LPC8xx_SERIAL_UARTCLKDIV !=  LPC8xx_SERIAL_U_PCLK)
-  #define LPC8xx_SERIAL_UARTFRGDIV          0xFF
- #else
-  #define LPC8xx_SERIAL_UARTFRGDIV          0x00
- #endif
-#endif
-
-/**
- * @brief   UARTFRGMUL
- * @details Fractional Baud rate generator numerator.
- *          Refer to LPC8xx User Manual 4.6.19 for calculation
- * @note    the *2, +1 and /2 are included to round to the nearest integer.
- */
-#if !defined(LPC8xx_SERIAL_UARTFRGMUL) || defined(__DOXYGEN__)
- #if (LPC8xx_SERIAL_UARTCLKDIV !=  LPC8xx_SERIAL_U_PCLK)
-  #define LPC8xx_SERIAL_UARTFRGMULT    ( ( ( ( (LPC8xx_UARTDIVCLK-            \
-                                               LPC8xx_SERIAL_U_PCLK)          \
-                                             *256*2 )                         \
-                                           /LPC8xx_SERIAL_U_PCLK )            \
-                                         +1 )                                 \
-                                       /2 )
-
- #else
-  #define LPC8xx_SERIAL_UARTFRGMULT   0x00
- #endif
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC8xx_SERIAL_UARTCLKDIV < 1) || (LPC8xx_SERIAL_UARTCLKDIV > 255)
-#error "invalid LPC8xx_SERIAL_UARTCLKDIV setting"
-#endif
-
-#if (LPC8xx_SERIAL_UARTFRGDIV != 0) && (LPC8xx_SERIAL_UARTFRGDIV != 255)
-#error "invalid LPC8xx_SERIAL_UARTFRGDIV setting"
-#endif
-
-#if (LPC8xx_SERIAL_UARTFRGMUL != 0) && (LPC8xx_SERIAL_UARTFRGMUL > 255)
-#error "invalid LPC8xx_SERIAL_UARTFRGMUL setting"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   LPC8xx Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the CFG register.
-   */
-  uint32_t                  sc_cfg;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  LPC_USART_TypeDef        *uart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC8xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#if LPC8xx_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#if LPC8xx_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/spi_lld.c b/os/hal/platforms/LPC8xx/spi_lld.c
deleted file mode 100644
index d5a8a4047..000000000
--- a/os/hal/platforms/LPC8xx/spi_lld.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/spi_lld.c
- * @brief   LPC8xx low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if LPC8xx_SPI_USE_SPI0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-#if LPC8xx_SPI_USE_SPI1 || defined(__DOXYGEN__)
-/** @brief SPI2 driver identifier.*/
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void spi_load_txdata(SPIDriver *spip) {
-
-  LPC_SPI_TypeDef *spi = spip->spi;
-
-  if (--spip->txcnt == 0) {
-    spi->TXCTRL |= SPI_TXCTRL_EOT;
-  }
-
-  if (spip->txptr != NULL) {
-    if ((spi->TXCTRL & SPI_TXCTRL_FLEN_MASK) > SPI_TXCTRL_FLEN(8)) {
-      const uint16_t *p = spip->txptr;
-      spi->TXDAT = *p++;
-      spip->txptr = p;
-    }
-    else {
-      const uint8_t *p = spip->txptr;
-      spi->TXDAT = *p++;
-      spip->txptr = p;
-    }
-  }
-  else
-    spi->TXDAT = 0xffff;
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- */
-static void spi_serve_interrupt(SPIDriver *spip) {
-
-  LPC_SPI_TypeDef *spi = spip->spi;
-
-  if (spi->INTSTAT & (SPI_STAT_RXOV | SPI_STAT_TXUR)) {
-    /* The overflow condition should never happen becausepriority is given
-       to receive but a hook macro is provided anyway...*/
-    LPC8xx_SPI_ERROR_HOOK(spip);
-    spi->STAT = (SPI_STAT_RXOV | SPI_STAT_TXUR);
-  }
-
-  if (spi->INTSTAT & SPI_STAT_TXRDY) {
-    spi_load_txdata( spip );
-  }
-
-  if (spip->txcnt == 0) {
-    spi->INTENCLR = (SPI_STAT_TXRDY | SPI_STAT_TXUR);
-  }
-
-  if (spi->INTSTAT & SPI_STAT_RXRDY) {
-    if (spip->rxptr != NULL) {
-      if ((spi->TXCTRL & SPI_TXCTRL_FLEN_MASK) > SPI_TXCTRL_FLEN(8)) {
-        uint16_t *p = spip->rxptr;
-        *p++ = spi->RXDAT;
-        spip->rxptr = p;
-      }
-      else {
-        uint8_t *p = spip->rxptr;
-        *p++ = spi->RXDAT;
-        spip->rxptr = p;
-      }
-    }
-    else
-      (void)spi->RXDAT;
-      
-    if (--spip->rxcnt == 0) {
-      chDbgAssert(spip->txcnt == 0,
-                  "spi_serve_interrupt(), #1", "counter out of synch");
-      /* Stops the IRQ sources.*/
-      spi->INTENCLR = (SPI_STAT_RXRDY | SPI_STAT_TXRDY |
-                        SPI_STAT_RXOV | SPI_STAT_TXUR);
-
-      /* Portable SPI ISR code defined in the high level driver, note, it is
-         a macro.*/
-      _spi_isr_code(spip);
-      return;
-    }
-  }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if LPC8xx_SPI_USE_SPI0 || defined(__DOXYGEN__)
-/**
- * @brief   SPI0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector40) {
-
-  CH_IRQ_PROLOGUE();
-  spi_serve_interrupt(&SPID1);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if LPC8xx_SPI_USE_SPI1 || defined(__DOXYGEN__)
-/**
- * @brief   SPI1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector44) {
-
-  CH_IRQ_PROLOGUE();
-  spi_serve_interrupt(&SPID2);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if LPC8xx_SPI_USE_SPI0
-  spiObjectInit(&SPID1);
-  SPID1.spi = LPC_SPI0;  
-#endif
-
-#if LPC8xx_SPI_USE_SPI1
-  spiObjectInit(&SPID2);
-  SPID2.spi = LPC_SPI1;
-#endif
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-#if LPC8xx_SPI_USE_SPI0
-    if (&SPID1 == spip) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
-      LPC_SYSCON->PRESETCTRL |= (1<<0);
-      spip->spi->DIV = LPC8xx_SPI_SPI0CLKDIV;
-      nvicEnableVector(SPI0_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC8xx_SPI_SPI0_IRQ_PRIORITY));
-    }
-#endif
-#if LPC8xx_SPI_USE_SPI1
-    if (&SPID2 == spip) {
-      LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
-      LPC_SYSCON->PRESETCTRL |= (1<<1);
-      spip->spi->DIV = LPC8xx_SPI_SPI1CLKDIV;
-      nvicEnableVector(SPI1_IRQn,
-                       CORTEX_PRIORITY_MASK(LPC8xx_SPI_SPI1_IRQ_PRIORITY));
-    }
-#endif
-  }
-
-  spip->spi->DLY    = spip->config->dly;
-  spip->spi->TXCTRL = spip->config->txctrl;
-  spip->spi->STAT   = (SPI_STAT_RXOV | SPI_STAT_TXUR);
-  spip->spi->CFG    = spip->config->cfg | SPI_CFG_ENABLE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state != SPI_STOP) {
-    spip->spi->CFG = 0;
-
-#if LPC8xx_SPI_USE_SPI0
-    if (&SPID1 == spip) {
-      nvicDisableVector(SPI0_IRQn);
-      LPC_SYSCON->PRESETCTRL &= ~(1<<0);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<11);
-    }
-#endif
-
-#if LPC8xx_SPI_USE_SPI1
-    if (&SPID2 == spip) {
-      nvicDisableVector(SPI1_IRQn);
-      LPC_SYSCON->PRESETCTRL &= ~(1<<1);
-      LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<12);
-    }
-#endif
-
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-  /* Hardware controls SSEL */
-  (void)spip;
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-  /* Hardware controls SSEL */
-  (void)spip;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  spip->spi->TXCTRL &= ~SPI_TXCTRL_EOT;
-  spi_load_txdata(spip);
-
-  if (spip->txcnt == 0)
-    spip->spi->INTENSET = (SPI_STAT_RXRDY | SPI_STAT_RXOV);
-  else
-    spip->spi->INTENSET = (SPI_STAT_RXRDY | SPI_STAT_TXRDY |
-                            SPI_STAT_RXOV | SPI_STAT_TXUR);
-  
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spi_lld_exchange( spip, n, NULL, NULL);
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spi_lld_exchange( spip, n, txbuf, NULL);
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spi_lld_exchange( spip, n, NULL, rxbuf);
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->spi->TXCTRL |= SPI_TXCTRL_EOT;
-  spip->spi->TXDAT = frame;
-  while ((spip->spi->STAT & SPI_STAT_RXRDY) == 0)
-    ;
-  return (uint16_t)spip->spi->RXDAT;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/spi_lld.h b/os/hal/platforms/LPC8xx/spi_lld.h
deleted file mode 100644
index 4acd52547..000000000
--- a/os/hal/platforms/LPC8xx/spi_lld.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    LPC8xx/spi_lld.h
- * @brief   LPC8xx low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define SPI_CFG_ENABLE               (1<<0)
-#define SPI_CFG_MASTER               (1<<2)
-#define SPI_CFG_LSBF                 (1<<3)
-#define SPI_CFG_CHPA                 (1<<4)
-#define SPI_CFG_CPOL                 (1<<5)
-#define SPI_CFG_LOOP                 (1<<7)
-#define SPI_CFG_SPOL                 (1<<8)
-
-#define SPI_DLY_PRE(n)               (((n)&0x0f)<< 0)
-#define SPI_DLY_POST(n)              (((n)&0x0f)<< 4)
-#define SPI_DLY_FRAME(n)             (((n)&0x0f)<< 8)
-#define SPI_DLY_TFER(n)              (((n)&0x0f)<<12)
-
-#define SPI_STAT_RXRDY                (1<<0)
-#define SPI_STAT_TXRDY                (1<<1)
-#define SPI_STAT_RXOV                 (1<<2)
-#define SPI_STAT_TXUR                 (1<<3)
-#define SPI_STAT_SSA                  (1<<4)
-#define SPI_STAT_SSD                  (1<<5)
-#define SPI_STAT_STALL                (1<<6)
-#define SPI_STAT_EOT                  (1<<7)
-#define SPI_STAT_IDLE                 (1<<8)
-
-#define SPI_TXCTRL_TXSSELN          (1<<16)
-#define SPI_TXCTRL_EOT              (1<<20)
-#define SPI_TXCTRL_EOF              (1<<21)
-#define SPI_TXCTRL_RXIGNORE         (1<<22)
-#define SPI_TXCTRL_FLEN(n)          (((n)-1)<<24)
-#define SPI_TXCTRL_FLEN_MASK        (0x0f<<24)
-
-
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for device SPI0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC8xx_SPI_USE_SPI0) || defined(__DOXYGEN__)
-#define LPC8xx_SPI_USE_SPI0                TRUE
-#endif
-
-/**
- * @brief   SPI2 driver enable switch.
- * @details If set to @p TRUE the support for device SPI1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(LPC8xx_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define LPC8xx_SPI_USE_SPI1                FALSE
-#endif
-
-/**
- * @brief   SPI0 PCLK divider.
- */
-#if !defined(LPC8xx_SPI_SPI0CLKDIV) || defined(__DOXYGEN__)
-#define LPC8xx_SPI_SPI0CLKDIV              1
-#endif
-
-/**
- * @brief   SPI1 PCLK divider.
- */
-#if !defined(LPC8xx_SPI_SPI1CLKDIV) || defined(__DOXYGEN__)
-#define LPC8xx_SPI_SPI1CLKDIV              1
-#endif
-
-/**
- * @brief   SPI0 interrupt priority level setting.
- */
-#if !defined(LPC8xx_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_SPI_SPI0_IRQ_PRIORITY       1
-#endif
-
-/**
- * @brief   SPI1 interrupt priority level setting.
- */
-#if !defined(LPC8xx_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define LPC8xx_SPI_SPI1_IRQ_PRIORITY       1
-#endif
-
-/**
- * @brief   Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(LPC8xx_SPI_ERROR_HOOK) || defined(__DOXYGEN__)
-#define LPC8xx_SPI_ERROR_HOOK(spip)    chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (LPC8xx_SPI_SPI0CLKDIV < 1) || (LPC8xx_SPI_SPI0CLKDIV > 255)
-#error "invalid LPC8xx_SPI_SSP0CLKDIV setting"
-#endif
-
-#if (LPC8xx_SPI_SPI1CLKDIV < 1) || (LPC8xx_SPI_SPI1CLKDIV > 255)
-#error "invalid LPC8xx_SPI_SSP1CLKDIV setting"
-#endif
-
-#if !LPC8xx_SPI_USE_SPI0 && !LPC8xx_SPI_USE_SPI1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-/**
- * @brief   SPI0 clock.
- */
-#define LPC8xx_SPI_SPI0_PCLK                                               \
-  (LPC8xx_SYSCLK / LPC8xx_SPI_SPI0CLKDIV)
-
-/**
- * @brief   SPI1 clock.
- */
-#define LPC8xx_SPI_SPI1_PCLK                                               \
-  (LPC8xx_SYSCLK / LPC8xx_SPI_SPI1CLKDIV)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-
-  /**
-   * @brief SPI CFG initialization data.
-   */
-  uint16_t              cfg;
-  /**
-   * @brief SPI DLY initialization data.
-   */
-  uint16_t              dly;
-  /**
-   * @brief SPI TXCTRL initialization data.
-   */
-  uint32_t              txctrl;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SPI registers block.
-   */
-  LPC_SPI_TypeDef       *spi;
-  /**
-   * @brief Number of words yet to be received.
-   */
-  uint32_t              rxcnt;
-  /**
-   * @brief Receive pointer or @p NULL.
-   */
-  void                  *rxptr;
-  /**
-   * @brief Number of words yet to be transmitted.
-   */
-  uint32_t              txcnt;
-  /**
-   * @brief Transmit pointer or @p NULL.
-   */
-  const void            *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if LPC8xx_SPI_USE_SPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if LPC8xx_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/LPC8xx/system_LPC8xx.h b/os/hal/platforms/LPC8xx/system_LPC8xx.h
deleted file mode 100644
index 108baa842..000000000
--- a/os/hal/platforms/LPC8xx/system_LPC8xx.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
- * @file:    system_LPC8xx.h
- * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
- *           for the NXP LPC8xx Device Series 
- * @version: V1.0
- * @date:    16. Aug. 2012
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2012 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC8xx_H
-#define __SYSTEM_LPC8xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC8xx_H */
diff --git a/os/hal/platforms/MSP430/hal_lld.c b/os/hal/platforms/MSP430/hal_lld.c
deleted file mode 100644
index 9fc17af0c..000000000
--- a/os/hal/platforms/MSP430/hal_lld.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    MSP430/hal_lld.c
- * @brief   MSP430 HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* RTC initially stopped.*/
-  WDTCTL = 0x5A80;
-
-  /* Clock sources setup.*/
-  DCOCTL  = VAL_DCOCTL;
-  BCSCTL1 = VAL_BCSCTL1;
-#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK
-  do {
-    int i;
-    IFG1 &= ~OFIFG;
-     for (i = 255; i > 0; i--)
-       asm("nop");
-  } while (IFG1 & OFIFG);
-#endif
-  BCSCTL2 = VAL_BCSCTL2;
-}
-
-/** @} */
diff --git a/os/hal/platforms/MSP430/hal_lld.h b/os/hal/platforms/MSP430/hal_lld.h
deleted file mode 100644
index 80ee0d14b..000000000
--- a/os/hal/platforms/MSP430/hal_lld.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    MSP430/hal_lld.h
- * @brief   MSP430 HAL subsystem low level driver header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "msp430.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME   "MSP430"
-
-#define MSP430_CLOCK_SOURCE_XT2CLK  0   /**< @brief XT2CLK clock selector.  */
-#define MSP430_CLOCK_SOURCE_DCOCLK  1   /**< @brief DCOCLK clock selector.  */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Clock source.
- * @details The clock source can be selected from:
- *          - @p MSP430_CLOCK_SOURCE_XT2CLK.
- *          - @p MSP430_CLOCK_SOURCE_DCOCLK.
- *          .
- */
-#if !defined(MSP430_USE_CLOCK) || defined(__DOXYGEN__)
-#define MSP430_USE_CLOCK            MSP430_CLOCK_SOURCE_XT2CLK
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Calculating the derived clock constants.
- */
-#define ACLK                        LFXT1CLK
-#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK
-#define MCLK                        XT2CLK
-#define SMCLK                       (XT2CLK / 8)
-#elif MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_DCOCLK
-#define MCLK                        DCOCLK
-#define SMCLK                       DCOCLK
-#else
-#error "unknown clock source specified"
-#endif
-
-/*
- * Calculating the initialization values.
- */
-#define VAL_DCOCTL                  (DCO0 | DCO1)
-#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_XT2CLK
-#define VAL_BCSCTL1                 (RSEL2)
-#define VAL_BCSCTL2                 (SELM_2 | DIVM_0 | DIVS_3 | SELS)
-#endif
-#if MSP430_USE_CLOCK == MSP430_CLOCK_SOURCE_DCOCLK
-#define VAL_BCSCTL1                 (XT2OFF | RSEL2)
-#define VAL_BCSCTL2                 (SELM_0 | DIVM_0 | DIVS_0)
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/MSP430/pal_lld.c b/os/hal/platforms/MSP430/pal_lld.c
deleted file mode 100644
index 70f848d82..000000000
--- a/os/hal/platforms/MSP430/pal_lld.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    MSP430/pal_lld.c
- * @brief   MSP430 Digital I/O low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   MSP430 I/O ports configuration.
- * @note    The @p PxIFG, @p PxIE and @p PxSEL registers are cleared. @p PxOUT
- *          and @p PxDIR are configured as specified.
- *
- * @param[in] config the MSP430 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__)
-  IOPORT1->iop_full.ie = 0;
-  IOPORT1->iop_full.ifg = 0;
-  IOPORT1->iop_full.sel = 0;
-  IOPORT1->iop_common.out = config->P1Data.out;
-  IOPORT1->iop_common.dir = config->P1Data.dir;
-#endif
-
-#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__)
-  IOPORT2->iop_full.ie = 0;
-  IOPORT2->iop_full.ifg = 0;
-  IOPORT2->iop_full.sel = 0;
-  IOPORT2->iop_common.out = config->P2Data.out;
-  IOPORT2->iop_common.dir = config->P2Data.dir;
-#endif
-
-#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__)
-  IOPORT3->iop_simple.sel = 0;
-  IOPORT3->iop_common.out = config->P3Data.out;
-  IOPORT3->iop_common.dir = config->P3Data.dir;
-#endif
-
-#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__)
-  IOPORT4->iop_simple.sel = 0;
-  IOPORT4->iop_common.out = config->P4Data.out;
-  IOPORT4->iop_common.dir = config->P4Data.dir;
-#endif
-
-#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__)
-  IOPORT5->iop_simple.sel = 0;
-  IOPORT5->iop_common.out = config->P5Data.out;
-  IOPORT5->iop_common.dir = config->P5Data.dir;
-#endif
-
-#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__)
-  IOPORT6->iop_simple.sel = 0;
-  IOPORT6->iop_common.out = config->P6Data.out;
-  IOPORT6->iop_common.dir = config->P6Data.dir;
-#endif
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as output as recommended by
- *          the MSP430x1xx Family User's Guide. Unconnected pads are set to
- *          high logic state by default.
- * @note    This function does not alter the @p PxSEL registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    port->iop_common.dir &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    port->iop_common.out |= mask;
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->iop_common.dir |= mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/MSP430/pal_lld.h b/os/hal/platforms/MSP430/pal_lld.h
deleted file mode 100644
index 39138fba5..000000000
--- a/os/hal/platforms/MSP430/pal_lld.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    MSP430/pal_lld.h
- * @brief   MSP430 Digital I/O low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Simple MSP430 I/O port.
- */
-struct msp430_port_simple_t {
-  volatile uint8_t              in;
-  volatile uint8_t              out;
-  volatile uint8_t              dir;
-  volatile uint8_t              sel;
-};
-
-/**
- * @brief   Full MSP430 I/O port.
- */
-struct msp430_port_full_t {
-  volatile uint8_t              in;
-  volatile uint8_t              out;
-  volatile uint8_t              dir;
-  volatile uint8_t              ifg;
-  volatile uint8_t              ies;
-  volatile uint8_t              ie;
-  volatile uint8_t              sel;
-#if defined(__MSP430_HAS_PORT1_R__) || defined(__MSP430_HAS_PORT2_R__)
-  volatile uint8_t             ren;
-#endif
-};
-
-/**
- * @brief   Simplified MSP430 I/O port representation.
- * @details This structure represents the common part of all the MSP430 I/O
- *          ports.
- */
-struct msp430_port_common {
-  volatile uint8_t              in;
-  volatile uint8_t              out;
-  volatile uint8_t              dir;
-};
-
-/**
- * @brief   Generic MSP430 I/O port.
- */
-typedef union {
-  struct msp430_port_common     iop_common;
-  struct msp430_port_simple_t   iop_simple;
-  struct msp430_port_full_t     iop_full;
-} msp430_ioport_t;
-
-/**
- * @brief   Setup registers common to all the MSP430 ports.
- */
-typedef struct  {
-  volatile uint8_t              out;
-  volatile uint8_t              dir;
-} msp430_dio_setup_t;
-
-/**
- * @brief   MSP430 I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialize the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-#if defined(__MSP430_HAS_PORT1__) ||                                    \
-    defined(__MSP430_HAS_PORT1_R__) ||                                  \
-    defined(__DOXYGEN__)
-  /** @brief Port 1 setup data.*/
-  msp430_dio_setup_t    P1Data;
-#endif
-#if defined(__MSP430_HAS_PORT2__) ||                                    \
-    defined(__MSP430_HAS_PORT2_R__) ||                                  \
-    defined(__DOXYGEN__)
-  /** @brief Port 2 setup data.*/
-  msp430_dio_setup_t    P2Data;
-#endif
-#if defined(__MSP430_HAS_PORT3__) ||                                    \
-    defined(__MSP430_HAS_PORT3_R__) ||                                  \
-    defined(__DOXYGEN__)
-  /** @brief Port 3 setup data.*/
-  msp430_dio_setup_t    P3Data;
-#endif
-#if defined(__MSP430_HAS_PORT4__) ||                                    \
-    defined(__MSP430_HAS_PORT4_R__) ||                                  \
-    defined(__DOXYGEN__)
-  /** @brief Port 4 setup data.*/
-  msp430_dio_setup_t    P4Data;
-#endif
-#if defined(__MSP430_HAS_PORT5__) ||                                    \
-    defined(__MSP430_HAS_PORT5_R__) ||                                  \
-    defined(__DOXYGEN__)
-  /** @brief Port 5 setup data.*/
-  msp430_dio_setup_t    P5Data;
-#endif
-#if defined(__MSP430_HAS_PORT6__) ||                                    \
-    defined(__MSP430_HAS_PORT6_R__) ||                                  \
-    defined(__DOXYGEN__)
-  /** @brief Port 6 setup data.*/
-  msp430_dio_setup_t    P6Data;
-#endif
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 8
-
-/**
- * @brief   Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint8_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint16_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- *          any assumption about it, use the provided macros when populating
- *          variables of this type.
- */
-typedef msp430_ioport_t *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   I/O port A identifier.
- * @details This port identifier is mapped on the MSP430 port 1 (P1).
- */
-#if defined(__MSP430_HAS_PORT1__) ||                                    \
-    defined(__MSP430_HAS_PORT1_R__) ||                                  \
-    defined(__DOXYGEN__)
-#define IOPORT1         ((ioportid_t)P1IN_)
-#endif
-
-/**
- * @brief   I/O port B identifier.
- * @details This port identifier is mapped on the MSP430 port 2 (P2).
- */
-#if defined(__MSP430_HAS_PORT2__) ||                                    \
-    defined(__MSP430_HAS_PORT2_R__) ||                                  \
-    defined(__DOXYGEN__)
-#define IOPORT2         ((ioportid_t)P2IN_)
-#endif
-
-/**
- * @brief   I/O port C identifier.
- * @details This port identifier is mapped on the MSP430 port 3 (P3).
- */
-#if defined(__MSP430_HAS_PORT3__) ||                                    \
-    defined(__MSP430_HAS_PORT3_R__) ||                                  \
-    defined(__DOXYGEN__)
-#define IOPORT3         ((ioportid_t)P3IN_)
-#endif
-
-/**
- * @brief   I/O port D identifier.
- * @details This port identifier is mapped on the MSP430 port 4 (P4).
- */
-#if defined(__MSP430_HAS_PORT4__) ||                                    \
-    defined(__MSP430_HAS_PORT4_R__) ||                                  \
-    defined(__DOXYGEN__)
-#define IOPORT4         ((ioportid_t)P4IN_)
-#endif
-
-/**
- * @brief   I/O port E identifier.
- * @details This port identifier is mapped on the MSP430 port 5 (P5).
- */
-#if defined(__MSP430_HAS_PORT5__) ||                                    \
-    defined(__MSP430_HAS_PORT5_R__) ||                                  \
-    defined(__DOXYGEN__)
-#define IOPORT5         ((ioportid_t)P5IN_)
-#endif
-
-/**
- * @brief   I/O port F identifier.
- * @details This port identifier is mapped on the MSP430 port 6 (P6).
- */
-#if defined(__MSP430_HAS_PORT6__) ||                                    \
-    defined(__MSP430_HAS_PORT6_R__) ||                                  \
-    defined(__DOXYGEN__)
-#define IOPORT6         ((ioportid_t)P6IN_)
-#endif
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- * @details In MSP430 programs all the ports as input.
- *
- * @param[in] config the MSP430 ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- * @details This function is implemented by reading the PxIN register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->iop_common.in)
-
-/**
- * @brief   Reads the output latch.
- * @details This function is implemented by reading the PxOUT register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->iop_common.out)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- * @details This function is implemented by writing the PxOUT register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->iop_common.out = (bits))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as output as recommended by
- *          the MSP430x1xx Family User's Guide.
- * @note    This function does not alter the @p PxSEL registers. Alternate
- *          functions setup must be handled by device-specific code.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _PAL_LLD_H_ */
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/MSP430/platform.dox b/os/hal/platforms/MSP430/platform.dox
deleted file mode 100644
index 131743e66..000000000
--- a/os/hal/platforms/MSP430/platform.dox
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup MSP430_DRIVERS MSP430 Drivers
- * @details This section describes all the supported drivers on the MSP430
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup MSP430_HAL MSP430 Initialization Support
- * @details The MSP430 HAL support is responsible for system initialization.
- *
- * @section msp430_hal_1 Supported HW resources
- * - DCOCTL.
- * - BCSCTL1.
- * - BCSCTL2.
- * .
- * @section msp430_hal_2 MSP430 HAL driver implementation features
- * - Clock source selection.
- * .
- * @ingroup MSP430_DRIVERS
- */
-
-/**
- * @defgroup MSP430_PAL MSP430 PAL Support
- * @details The MSP430 PAL driver uses the PORT peripherals.
- *
- * @section msp430_pal_1 Supported HW resources
- * - PORT1 (where present).
- * - PORT2 (where present).
- * - PORT3 (where present).
- * - PORT4 (where present).
- * - PORT5 (where present).
- * - PORT6 (where present).
- * .
- * @section msp430_pal_2 MSP430 PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 8 bits wide ports.
- * - Atomic set/reset/toggle functions because special MSP430 instruction set.
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section msp430_pal_3 Supported PAL setup modes
- * The MSP430 PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section msp430_pal_4 Suboptimal behavior
- * The MSP430 PORT is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Bus/group writes is not atomic.
- * - Pad/group mode setup is not atomic.
- * .
- * @ingroup MSP430_DRIVERS
- */
-
-/**
- * @defgroup MSP430_SERIAL MSP430 Serial Support
- * @details The MSP430 Serial driver uses the USART peripherals in a
- *          buffered, interrupt driven, implementation.
- *
- * @section msp430_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART0.
- * - USART1.
- * .
- * @section msp430_serial_2 MSP430 Serial driver implementation features
- * - Each USART can be independently enabled and programmed.
- * - Fully interrupt driven.
- * .
- * @ingroup MSP430_DRIVERS
- */
diff --git a/os/hal/platforms/MSP430/platform.mk b/os/hal/platforms/MSP430/platform.mk
deleted file mode 100644
index d0175c1df..000000000
--- a/os/hal/platforms/MSP430/platform.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-# List of all the MSP430 platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/MSP430/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/MSP430/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/MSP430/serial_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/MSP430
diff --git a/os/hal/platforms/MSP430/serial_lld.c b/os/hal/platforms/MSP430/serial_lld.c
deleted file mode 100644
index ed17c45c2..000000000
--- a/os/hal/platforms/MSP430/serial_lld.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    MSP430/serial_lld.c
- * @brief   MSP430 low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if USE_MSP430_USART0 || defined(__DOXYGEN__)
-/** @brief USART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-#if USE_MSP430_USART1 || defined(__DOXYGEN__)
-/** @brief USART1 serial driver identifier.*/
-SerialDriver SD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  UBR(SERIAL_DEFAULT_BITRATE),
-  0,
-  CHAR
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void set_error(SerialDriver *sdp, uint8_t urctl) {
-  flagsmask_t sts = 0;
-
-  if (urctl & OE)
-    sts |= SD_OVERRUN_ERROR;
-  if (urctl & PE)
-    sts |= SD_PARITY_ERROR;
-  if (urctl & FE)
-    sts |= SD_FRAMING_ERROR;
-  if (urctl & BRK)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-#if USE_MSP430_USART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  if (!(U0IE & UTXIE0)) {
-    msg_t b = sdRequestDataI(&SD1);
-    if (b != Q_EMPTY) {
-      U0IE |= UTXIE0;
-      U0TXBUF = (uint8_t)b;
-    }
-  }
-}
-
-/**
- * @brief   USART0 initialization.
- *
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void usart0_init(const SerialConfig *config) {
-
-  U0CTL = SWRST;                            /* Resets the USART.            */
-  /* USART init */
-  U0TCTL = SSEL0 | SSEL1;                   /* SMCLK as clock source.       */
-  U0MCTL = config->sc_mod;                  /* Modulator.                   */
-  U0BR1 = (uint8_t)(config->sc_div >> 8);   /* Divider high.                */
-  U0BR0 = (uint8_t)(config->sc_div >> 0);   /* Divider low.                 */
-  /* Clear USART status.*/
-  (void)U0RXBUF;
-  U0RCTL = 0;
-  /* USART enable.*/
-  U0ME |= UTXE0 + URXE0;                    /* Enables the USART.           */
-  U0CTL = config->sc_ctl & ~SWRST;          /* Various settings.            */
-  U0IE |= URXIE0;                           /* Enables RX interrupt.        */
-}
-
-/**
- * @brief   USART0 de-initialization.
- */
-static void usart0_deinit(void) {
-
-  U0IE &= ~URXIE0;
-  U0CTL = SWRST;
-}
-#endif /* USE_MSP430_USART0 */
-
-#if USE_MSP430_USART1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  if (!(U1IE & UTXIE1)) {
-    msg_t b = sdRequestDataI(&SD2);
-    if (b != Q_EMPTY) {
-      U1IE |= UTXIE1;
-      U1TXBUF = (uint8_t)b;
-    }
-  }
-}
-
-/**
- * @brief   USART1 initialization.
- *
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void usart1_init(const SerialConfig *config) {
-
-  U1CTL = SWRST;                            /* Resets the USART.            */
-  /* USART init.*/
-  U1TCTL = SSEL0 | SSEL1;                   /* SMCLK as clock source.       */
-  U1MCTL = config->sc_mod;                  /* Modulator.                   */
-  U1BR1 = (uint8_t)(config->sc_div >> 8);   /* Divider high.                */
-  U1BR0 = (uint8_t)(config->sc_div >> 0);   /* Divider low.                 */
-  /* Clear USART status.*/
-  (void)U0RXBUF;
-  U1RCTL = 0;
-  /* USART enable.*/
-  U1ME |= UTXE0 + URXE0;                    /* Enables the USART.           */
-  U1CTL = config->sc_ctl & ~SWRST;          /* Various settings.            */
-  U1IE |= URXIE0;                           /* Enables RX interrupt.        */
-}
-
-/**
- * @brief   USART1 de-initialization.
- */
-static void usart1_deinit(void) {
-
-  U1IE &= ~URXIE0;
-  U1CTL = SWRST;
-}
-#endif /* USE_MSP430_USART1 */
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if USE_MSP430_USART0 || defined(__DOXYGEN__)
-/**
- * @brief   USART0 TX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART0TX) {
-  msg_t b;
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  b = sdRequestDataI(&SD1);
-  chSysUnlockFromIsr();
-  if (b < Q_OK)
-    U0IE &= ~UTXIE0;
-  else
-    U0TXBUF = b;
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   USART0 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART0RX) {
-  uint8_t urctl;
-
-  CH_IRQ_PROLOGUE();
-
-  if ((urctl = U0RCTL) & RXERR)
-    set_error(&SD1, urctl);
-  chSysLockFromIsr();
-  sdIncomingDataI(&SD1, U0RXBUF);
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* USE_MSP430_USART0 */
-
-#if USE_MSP430_USART1 || defined(__DOXYGEN__)
-/**
- * @brief   USART1 TX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART1TX_VECTOR) {
-  msg_t b;
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  b = sdRequestDataI(&SD2);
-  chSysUnlockFromIsr();
-  if (b < Q_OK)
-    U1IE &= ~UTXIE1;
-  else
-    U1TXBUF = b;
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   USART1 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART1RX_VECTOR) {
-  uint8_t urctl;
-
-  CH_IRQ_PROLOGUE();
-
-  if ((urctl = U1RCTL) & RXERR)
-    set_error(&SD2, urctl);
-  chSysLockFromIsr();
-  sdIncomingDataI(&SD2, U1RXBUF);
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* USE_MSP430_USART1 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if USE_MSP430_USART0
-  sdObjectInit(&SD1, NULL, notify1);
-#endif
-
-#if USE_MSP430_USART1
-  sdObjectInit(&SD2, NULL, notify2);
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-#if USE_MSP430_USART0
-  if (&SD1 == sdp) {
-    usart0_init(config);
-    return;
-  }
-#endif
-#if USE_MSP430_USART1
-  if (&SD2 == sdp) {
-    usart1_init(config);
-    return;
-  }
-#endif
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-#if USE_MSP430_USART0
-  if (&SD1 == sdp) {
-    usart0_deinit();
-    return;
-  }
-#endif
-#if USE_MSP430_USART1
-  if (&SD2 == sdp) {
-    usart1_deinit();
-    return;
-  }
-#endif
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/MSP430/serial_lld.h b/os/hal/platforms/MSP430/serial_lld.h
deleted file mode 100644
index ae764d739..000000000
--- a/os/hal/platforms/MSP430/serial_lld.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    MSP430/serial_lld.h
- * @brief   MSP430 low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   USART0 driver enable switch.
- * @details If set to @p TRUE the support for USART0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_MSP430_USART0) || defined(__DOXYGEN__)
-#define USE_MSP430_USART0           TRUE
-#endif
-
-/**
- * @brief   USART1 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(USE_MSP430_USART1) || defined(__DOXYGEN__)
-#define USE_MSP430_USART1           TRUE
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   MSP430 Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Initialization value for the UBRx registers.
-   */
-  uint16_t                  sc_div;
-  /**
-   * @brief Initialization value for the MOD register.
-   */
-  uint8_t                   sc_mod;
-  /**
-   * @brief Initialization value for the CTL register.
-   */
-  uint8_t                   sc_ctl;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Macro for baud rate computation.
- * @note    Make sure the final baud rate is within tolerance.
- */
-#define UBR(b) (SMCLK / (b))
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if USE_MSP430_USART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if USE_MSP430_USART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Posix/console.c b/os/hal/platforms/Posix/console.c
deleted file mode 100644
index 28c0b94ce..000000000
--- a/os/hal/platforms/Posix/console.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file console.c
- * @brief Simulator console driver code.
- * @{
- */
-
-#include <stdio.h>
-
-#include "ch.h"
-#include "hal.h"
-#include "console.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief Console driver 1.
- */
-BaseChannel CD1;
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static size_t write(void *ip, const uint8_t *bp, size_t n) {
-  size_t ret;
-
-  (void)ip;
-  ret = fwrite(bp, 1, n, stdout);
-  fflush(stdout);
-  return ret;
-}
-
-static size_t read(void *ip, uint8_t *bp, size_t n) {
-
-  (void)ip;
-  return fread(bp, 1, n, stdin);
-}
-
-static msg_t put(void *ip, uint8_t b) {
-
-  (void)ip;
-
-  fputc(b, stdout);
-  fflush(stdout);
-  return RDY_OK;
-}
-
-static msg_t get(void *ip) {
-
-  (void)ip;
-
-  return fgetc(stdin);
-}
-
-static msg_t putt(void *ip, uint8_t b, systime_t timeout) {
-
-  (void)ip;
-  (void)timeout;
-  fputc(b, stdout);
-  fflush(stdout);
-  return RDY_OK;
-}
-
-static msg_t gett(void *ip, systime_t timeout) {
-
-  (void)ip;
-  (void)timeout;
-  return fgetc(stdin);
-}
-
-static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t timeout) {
-  size_t ret;
-
-  (void)ip;
-  (void)timeout;
-  ret = fwrite(bp, 1, n, stdout);
-  fflush(stdout);
-  return ret;
-}
-
-static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t timeout) {
-
-  (void)ip;
-  (void)timeout;
-  return fread(bp, 1, n, stdin);
-}
-
-static const struct BaseChannelVMT vmt = {
-  write, read, put, get,
-  putt, gett, writet, readt
-};
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-void conInit(void) {
-
-  CD1.vmt = &vmt;
-}
-
-/** @} */
diff --git a/os/hal/platforms/Posix/console.h b/os/hal/platforms/Posix/console.h
deleted file mode 100644
index 491b6f36b..000000000
--- a/os/hal/platforms/Posix/console.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file console.h
- * @brief Simulator console driver header.
- * @{
- */
-
-#ifndef _CONSOLE_H_
-#define _CONSOLE_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-extern BaseChannel CD1;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void conInit(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CONSOLE_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Posix/hal_lld.c b/os/hal/platforms/Posix/hal_lld.c
deleted file mode 100644
index fb1bed779..000000000
--- a/os/hal/platforms/Posix/hal_lld.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Posix/hal_lld.c
- * @brief   Posix HAL subsystem low level driver code.
- *
- * @addtogroup POSIX_HAL
- * @{
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/time.h>
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static struct timeval nextcnt;
-static struct timeval tick = {0, 1000000 / CH_FREQUENCY};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief Low level HAL driver initialization.
- */
-void hal_lld_init(void) {
-
-#if defined(__APPLE__)
-  puts("ChibiOS/RT simulator (OS X)\n");
-#else
-  puts("ChibiOS/RT simulator (Linux)\n");
-#endif
-  gettimeofday(&nextcnt, NULL);
-  timeradd(&nextcnt, &tick, &nextcnt);
-}
-
-/**
- * @brief Interrupt simulation.
- */
-void ChkIntSources(void) {
-  struct timeval tv;
-
-#if HAL_USE_SERIAL
-  if (sd_lld_interrupt_pending()) {
-    dbg_check_lock();
-    if (chSchIsPreemptionRequired())
-      chSchDoReschedule();
-    dbg_check_unlock();
-    return;
-  }
-#endif
-
-  gettimeofday(&tv, NULL);
-  if (timercmp(&tv, &nextcnt, >=)) {
-    timeradd(&nextcnt, &tick, &nextcnt);
-
-    CH_IRQ_PROLOGUE();
-
-    chSysLockFromIsr();
-    chSysTimerHandlerI();
-    chSysUnlockFromIsr();
-
-    CH_IRQ_EPILOGUE();
-
-    dbg_check_lock();
-    if (chSchIsPreemptionRequired())
-      chSchDoReschedule();
-    dbg_check_unlock();
-  }
-}
-
-/** @} */
diff --git a/os/hal/platforms/Posix/hal_lld.h b/os/hal/platforms/Posix/hal_lld.h
deleted file mode 100644
index fd1dd3245..000000000
--- a/os/hal/platforms/Posix/hal_lld.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Posix/hal_lld.h
- * @brief   Posix simulator HAL subsystem low level driver header.
- *
- * @addtogroup POSIX_HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <netdb.h>
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME   "Linux"
-
-#define SOCKET int
-#define INVALID_SOCKET -1
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void ChkIntSources(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Posix/pal_lld.c b/os/hal/platforms/Posix/pal_lld.c
deleted file mode 100644
index 05965722b..000000000
--- a/os/hal/platforms/Posix/pal_lld.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Posix/pal_lld.c
- * @brief   Posix low level simulated PAL driver code.
- *
- * @addtogroup POSIX_PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   VIO1 simulated port.
- */
-sim_vio_port_t vio_port_1;
-
-/**
- * @brief   VIO2 simulated port.
- */
-sim_vio_port_t vio_port_2;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @note This function is not meant to be invoked directly by the application
- *       code.
- * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high
- *       state.
- * @note This function does not alter the @p PINSELx registers. Alternate
- *       functions setup must be handled by device-specific code.
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    port->dir &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    port->latch |= mask;
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->dir |= mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/Posix/pal_lld.h b/os/hal/platforms/Posix/pal_lld.h
deleted file mode 100644
index 439d93f97..000000000
--- a/os/hal/platforms/Posix/pal_lld.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Posix/pal_lld.h
- * @brief   Posix low level simulated PAL driver header.
- *
- * @addtogroup POSIX_PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-#undef PAL_MODE_INPUT_ANALOG
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   VIO port structure.
- */
-typedef struct {
-  /**
-   * @brief   VIO_LATCH register.
-   * @details This register represents the output latch of the VIO port.
-   */
-  uint32_t          latch;
-  /**
-   * @brief   VIO_PIN register.
-   * @details This register represents the logical level at the VIO port
-   *          pin level.
-   */
-  uint32_t          pin;
-  /**
-   * @brief   VIO_DIR register.
-   * @details Direction of the VIO port bits, 0=input, 1=output.
-   */
-  uint32_t          dir;
-} sim_vio_port_t;
-
-/**
- * @brief   Virtual I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-  /**
-   * @brief Virtual port 1 setup data.
-   */
-  sim_vio_port_t    VP1Data;
-  /**
-   * @brief Virtual port 2 setup data.
-   */
-  sim_vio_port_t    VP2Data;
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef sim_vio_port_t *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   VIO port 1 identifier.
- */
-#define IOPORT1         (&vio_port_1)
-
-/**
- * @brief   VIO port 2 identifier.
- */
-#define IOPORT2         (&vio_port_2)
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config)                                                \
-  (vio_port_1 = (config)->VP1Data,                                          \
-   vio_port_2 = (config)->VP2Data)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->pin)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->latch)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->latch = (bits))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-#if !defined(__DOXYGEN__)
-extern sim_vio_port_t vio_port_1;
-extern sim_vio_port_t vio_port_2;
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Posix/platform.mk b/os/hal/platforms/Posix/platform.mk
deleted file mode 100644
index e2e3da821..000000000
--- a/os/hal/platforms/Posix/platform.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-# List of all the Posix platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Posix/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/Posix/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/Posix/serial_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Posix
diff --git a/os/hal/platforms/Posix/serial_lld.c b/os/hal/platforms/Posix/serial_lld.c
deleted file mode 100644
index cfe6792ca..000000000
--- a/os/hal/platforms/Posix/serial_lld.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Posix/serial_lld.c
- * @brief   Posix low level simulated serial driver code.
- *
- * @addtogroup POSIX_SERIAL
- * @{
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <errno.h>
-#include <sys/ioctl.h>
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief Serial driver 1 identifier.*/
-#if USE_SIM_SERIAL1 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-/** @brief Serial driver 2 identifier.*/
-#if USE_SIM_SERIAL2 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-};
-
-static u_long nb = 1;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void init(SerialDriver *sdp, uint16_t port) {
-  struct sockaddr_in sad;
-  struct protoent *prtp;
-  int sockval = 1;
-  socklen_t socklen = sizeof(sockval);
-
-
-  if ((prtp = getprotobyname("tcp")) == NULL) {
-    printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name);
-    goto abort;
-  }
-
-  sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto);
-  if (sdp->com_listen == INVALID_SOCKET) {
-    printf("%s: Error creating simulator socket\n", sdp->com_name);
-    goto abort;
-  }
-
-
-  setsockopt(sdp->com_listen, SOL_SOCKET, SO_REUSEADDR, &sockval, socklen);
-
-  if (ioctl(sdp->com_listen, FIONBIO, &nb) != 0) {
-    printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name);
-    goto abort;
-  }
-
-  memset(&sad, 0, sizeof(sad));
-  sad.sin_family = AF_INET;
-  sad.sin_addr.s_addr = INADDR_ANY;
-  sad.sin_port = htons(port);
-  if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) {
-    printf("%s: Error binding socket\n", sdp->com_name);
-    goto abort;
-  }
-
-  if (listen(sdp->com_listen, 1) != 0) {
-    printf("%s: Error listening socket\n", sdp->com_name);
-    goto abort;
-  }
-  printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port);
-  return;
-
-abort:
-  if (sdp->com_listen != INVALID_SOCKET)
-    close(sdp->com_listen);
-  exit(1);
-}
-
-static bool_t connint(SerialDriver *sdp) {
-
-  if (sdp->com_data == INVALID_SOCKET) {
-    struct sockaddr addr;
-    socklen_t addrlen = sizeof(addr);
-
-    if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET)
-      return FALSE;
-
-    if (ioctl(sdp->com_data, FIONBIO, &nb) != 0) {
-      printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name);
-      goto abort;
-    }
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, CHN_CONNECTED);
-    chSysUnlockFromIsr();
-    return TRUE;
-  }
-  return FALSE;
-abort:
-  if (sdp->com_listen != INVALID_SOCKET)
-    close(sdp->com_listen);
-  if (sdp->com_data != INVALID_SOCKET)
-    close(sdp->com_data);
-  exit(1);
-}
-
-static bool_t inint(SerialDriver *sdp) {
-
-  if (sdp->com_data != INVALID_SOCKET) {
-    int i;
-    uint8_t data[32];
-
-    /*
-     * Input.
-     */
-    int n = recv(sdp->com_data, data, sizeof(data), 0);
-    switch (n) {
-    case 0:
-      close(sdp->com_data);
-      sdp->com_data = INVALID_SOCKET;
-      chSysLockFromIsr();
-      chnAddFlagsI(sdp, CHN_DISCONNECTED);
-      chSysUnlockFromIsr();
-      return FALSE;
-    case INVALID_SOCKET:
-      if (errno == EWOULDBLOCK)
-        return FALSE;
-      close(sdp->com_data);
-      sdp->com_data = INVALID_SOCKET;
-      return FALSE;
-    }
-    for (i = 0; i < n; i++) {
-      chSysLockFromIsr();
-      sdIncomingDataI(sdp, data[i]);
-      chSysUnlockFromIsr();
-    }
-    return TRUE;
-  }
-  return FALSE;
-}
-
-static bool_t outint(SerialDriver *sdp) {
-
-  if (sdp->com_data != INVALID_SOCKET) {
-    int n;
-    uint8_t data[1];
-
-    /*
-     * Input.
-     */
-    chSysLockFromIsr();
-    n = sdRequestDataI(sdp);
-    chSysUnlockFromIsr();
-    if (n < 0)
-      return FALSE;
-    data[0] = (uint8_t)n;
-    n = send(sdp->com_data, data, sizeof(data), 0);
-    switch (n) {
-    case 0:
-      close(sdp->com_data);
-      sdp->com_data = INVALID_SOCKET;
-      chSysLockFromIsr();
-      chnAddFlagsI(sdp, CHN_DISCONNECTED);
-      chSysUnlockFromIsr();
-      return FALSE;
-    case INVALID_SOCKET:
-      if (errno == EWOULDBLOCK)
-        return FALSE;
-      close(sdp->com_data);
-      sdp->com_data = INVALID_SOCKET;
-      return FALSE;
-    }
-    return TRUE;
-  }
-  return FALSE;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- */
-void sd_lld_init(void) {
-
-#if USE_SIM_SERIAL1
-  sdObjectInit(&SD1, NULL, NULL);
-  SD1.com_listen = INVALID_SOCKET;
-  SD1.com_data = INVALID_SOCKET;
-  SD1.com_name = "SD1";
-#endif
-
-#if USE_SIM_SERIAL2
-  sdObjectInit(&SD2, NULL, NULL);
-  SD2.com_listen = INVALID_SOCKET;
-  SD2.com_data = INVALID_SOCKET;
-  SD2.com_name = "SD2";
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-#if USE_SIM_SERIAL1
-  if (sdp == &SD1)
-    init(&SD1, SIM_SD1_PORT);
-#endif
-
-#if USE_SIM_SERIAL2
-  if (sdp == &SD2)
-    init(&SD2, SIM_SD2_PORT);
-#endif
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  (void)sdp;
-}
-
-bool_t sd_lld_interrupt_pending(void) {
-  bool_t b;
-
-  CH_IRQ_PROLOGUE();
-
-  b =  connint(&SD1) || connint(&SD2) ||
-       inint(&SD1)   || inint(&SD2)   ||
-       outint(&SD1)  || outint(&SD2);
-
-  CH_IRQ_EPILOGUE();
-
-  return b;
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/Posix/serial_lld.h b/os/hal/platforms/Posix/serial_lld.h
deleted file mode 100644
index 4c770abe2..000000000
--- a/os/hal/platforms/Posix/serial_lld.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Posix/serial_lld.h
- * @brief   Posix low level simulated serial driver header.
- *
- * @addtogroup POSIX_SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Serial buffers size.
- * @details Configuration parameter, you can change the depth of the queue
- *          buffers depending on the requirements of your application.
- */
-#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define SERIAL_BUFFERS_SIZE         1024
-#endif
-
-/**
- * @brief   SD1 driver enable switch.
- * @details If set to @p TRUE the support for SD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_SIM_SERIAL1) || defined(__DOXYGEN__)
-#define USE_SIM_SERIAL1             TRUE
-#endif
-
-/**
- * @brief   SD2 driver enable switch.
- * @details If set to @p TRUE the support for SD2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_SIM_SERIAL2) || defined(__DOXYGEN__)
-#define USE_SIM_SERIAL2             TRUE
-#endif
-
-/**
- * @brief   Listen port for SD1.
- */
-#if !defined(SD1_PORT) || defined(__DOXYGEN__)
-#define SIM_SD1_PORT                29001
-#endif
-
-/**
- * @brief   Listen port for SD2.
- */
-#if !defined(SD2_PORT) || defined(__DOXYGEN__)
-#define SIM_SD2_PORT                29002
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    This structure content is architecture dependent, each driver
- *          implementation defines its own version and the custom static
- *          initializers.
- */
-typedef struct {
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Listen socket for simulated serial port.*/                             \
-  SOCKET                    com_listen;                                     \
-  /* Data socket for simulated serial port.*/                               \
-  SOCKET                    com_data;                                       \
-  /* Port readable name.*/                                                  \
-  const char                *com_name;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if USE_SIM_SERIAL1 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if USE_SIM_SERIAL2 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-  bool_t sd_lld_interrupt_pending(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/hal_lld.c b/os/hal/platforms/Rx62n/hal_lld.c
deleted file mode 100644
index 61048dd47..000000000
--- a/os/hal/platforms/Rx62n/hal_lld.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/hal_lld.c
- * @brief   RX62N HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-}
-
-/**
- * @brief   RX62N clocks initialization.
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void rx62n_clock_init(void) {
-
-  SYSTEM.SCKCR.LONG = RX62N_SCKCR_ICK | RX62N_SCKCR_PCK | RX62N_SCKCR_BCK
-#if RX62N_SDCLK_OUTPUT_ENABLED == FALSE
-  | (1 << 22)
-#endif
-#if RX62N_BCLK_OUTPUT_ENABLED == FALSE
-  | (1 << 23)
-#endif
-  ;
-}
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/hal_lld.h b/os/hal/platforms/Rx62n/hal_lld.h
deleted file mode 100644
index db3dcc40f..000000000
--- a/os/hal/platforms/Rx62n/hal_lld.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/hal_lld.h
- * @brief   HAL subsystem low level driver header template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "iodefine_gcc62n.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS           FALSE
-
-#define IWDTCLK                           125000 /**< Watchdog internal clock */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   System PLL multiplier.
- * @note    The value is hardware fixed at 8.
- */
-#if defined(__DOXYGEN__)
-#define RX62N_SYSPLL_MUL                  8
-#endif
-
-/**
- * @brief   System PLL divider.
- * @note    The value must be chosen between (1, 2, 4, 8).
- */
-/*
-#if defined(__DOXYGEN__)
-#define RX62N_SYSPLL_DIV                  1
-#endif
-*/
-
-/**
- * @brief   Enables or disables the SDCLK clock output.
- */
-#if !defined(RX62N_SDCLK_OUTPUT_ENABLED) || defined(__DOXYGEN__)
-#define RX62N_SDCLK_OUTPUT_ENABLED        FALSE
-#endif
-
-/**
- * @brief   Enables or disables the BCLK clock output.
- */
-#if !defined(RX62N_BCLK_OUTPUT_ENABLED) || defined(__DOXYGEN__)
-#define RX62N_BCLK_OUTPUT_ENABLED         FALSE
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   ICK mask in SCKCR register.
- */
-#if (RX62N_ICLK_MUL == 1) || defined(__DOXYGEN__)
-#define RX62N_SCKCR_ICK (3 << 24)
-#elif RX62N_ICLK_MUL == 2
-#define RX62N_SCKCR_ICK (2 << 24)
-#elif RX62N_ICLK_MUL == 4
-#define RX62N_SCKCR_ICK (1 << 24)
-#elif RX62N_ICLK_MUL == 8
-#define RX62N_SCKCR_ICK (0 << 24)
-#else
-#error "invalid RX62N_ICLK_MUL value (1,2,4,8), check mcuconf.h"
-#endif
-
-/**
- * @brief   BCK mask in SCKCR register.
- */
-#if (RX62N_BCLK_MUL == 1) || defined(__DOXYGEN__)
-#define RX62N_SCKCR_BCK (3 << 16)
-#elif RX62N_BCLK_MUL == 2
-#define RX62N_SCKCR_BCK (2 << 16)
-#elif RX62N_BCLK_MUL == 4
-#define RX62N_SCKCR_BCK (1 << 16)
-#elif RX62N_BCLK_MUL == 8
-#define RX62N_SCKCR_BCK (0 << 16)
-#else
-#error "invalid RX62N_BCLK_MUL value (1,2,4,8), check mcuconf.h"
-#endif
-
-/**
- * @brief   PCK mask in SCKCR register.
- */
-#if (RX62N_PCLK_MUL == 1) || defined(__DOXYGEN__)
-#define RX62N_SCKCR_PCK (3 << 8)
-#elif RX62N_PCLK_MUL == 2
-#define RX62N_SCKCR_PCK (2 << 8)
-#elif RX62N_PCLK_MUL == 4
-#define RX62N_SCKCR_PCK (1 << 8)
-#elif RX62N_PCLK_MUL == 8
-#define RX62N_SCKCR_PCK (0 << 8)
-#else
-#error "invalid RX62N_PCLK_MUL value (1,2,4,8), check mcuconf.h"
-#endif
-
-/**
- * @brief   System clock.
- */
-#define  RX62N_SYSCLK     (EXTALCLK * RX62N_ICLK_MUL)
-#if (RX62N_SYSCLK < 8000000) || (RX62N_SYSCLK > 100000000)
-#error "System clock frequency out of the acceptable range (8..100MHz max)"
-#endif
-
-/**
- * @brief   Peripheral clock.
- */
-#define  RX62N_PERCLK     (EXTALCLK * RX62N_PCLK_MUL)
-#if (RX62N_PERCLK < 8000000) || (RX62N_PERCLK > 100000000)
-#error "Peripheral clock frequency out of the acceptable range (8..50MHz max)"
-#endif
-
-#if (RX62N_PERCLK > RX62N_SYSCLK)
-#error "Peripheral clock frequency higher than system clock frequency"
-#endif
-
-#if (EXTALCLK < 8000000) || (EXTALCLK > 14000000)
-#error "External crystal frequency out of the acceptable range (8..14MHz max)"
-#endif
-
-/*
- * TODO: check SYSCLK (ICLK) when ethernet controller is used (SYSCLK > 12.5MHz)
- * TODO: check UCLK when USB is used
- * TODO: oscilation stop detection
- */
-
-/*
-Clock frequencies (from manual):
-ICLK: 8..100MHz
-PCLK: 8..50MHz
-BCLK: 8..50MHz or 8..100MHz
-BCLK_OUT: 8..25MHz or 8..50MHz
-SDCLK: 8..50MHz
-UCLK: 48MHz (only when EXTAL = 12MHz)
-SUBCLK: 32768Hz
-IWDTCLK: 125kHz
-ICLK >= PCLK
-ICLK >= BCLK
-*/
-
-#if defined(__DOXYGEN__)
-/**
- * @name    Platform identification
- * @{
- */
-#define PLATFORM_NAME           "RX62N"
-/** @} */
-
-#elif defined(RX62NXADBG) || defined(RX62NXBDBG) ||               \
-      defined(RX62NXADLE) || defined(RX62NXBDLE) ||               \
-      defined(RX62NXADFB) || defined(RX62NXBDFB) ||               \
-      defined(RX62NXADFP) || defined(RX62NXBDFP) ||               \
-      defined(RX62NXADLD) || defined(RX62NXBDLD) ||               \
-      defined(__DOXYGEN__)
-
-#else
-#error "unspecified, unsupported or invalid RX62N platform"
-#endif
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-#if defined(RX62NXADBG) || defined (RX62NXBDBG) || defined(__DOXYGEN__)
-/**
- * @name    RX62NXXDBG capabilities (LFBGA176)
- * @{
- */
-
-#error "unsupported RX62N platform"
-
-/** @} */
-#endif /* defined(RX62NXADBG) || defined(RX62NXBDBG) */
-
-#if defined(RX62NXADLE) || defined (RX62NXBDLE) || defined(__DOXYGEN__)
-/**
- * @name    RX62NXXDLE capabilities (TFLGA145)
- * @{
- */
-
-#error "unsupported RX62N platform"
-
-/** @} */
-#endif /* defined(RX62NXADLE) || defined(RX62NXBDLE) */
-
-#if defined(RX62NXADFB) || defined (RX62NXBDFB) || defined(__DOXYGEN__)
-/**
- * @name    RX62NXXDLE capabilities (LQFP144)
- * @{
- */
-
-#error "unsupported RX62N platform"
-
-/** @} */
-#endif /* defined(RX62NXADFB) || defined(RX62NXBDFB) */
-
-#if defined(RX62NXADFP) || defined (RX62NXBDFP) || defined(__DOXYGEN__)
-/**
- * @name    RX62NXXDFP capabilities (LQFP100)
- * @{
- */
-/* ADC attributes.*/
-#define RX62N_HAS_ADC1          TRUE
-
-/* CAN attributes.*/
-#if defined (RX62NXADFP)
-#define RX62N_HAS_CAN           FALSE
-#else
-#define RX62N_HAS_CAN           TRUE
-#endif
-
-/* DAC attributes.*/
-#define RX62N_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-
-/* ETH attributes.*/
-#define RX62N_HAS_ETH           TRUE
-
-/* EXTI attributes.*/
-//#define RX62N_EXTI_NUM_CHANNELS 18
-
-/* GPIO attributes.*/
-#define RX62N_HAS_PORT0         TRUE
-#define RX62N_HAS_PORT0_OD      TRUE /* Open Drain */
-#define RX62N_HAS_PORT1         TRUE
-#define RX62N_HAS_PORT1_OD      TRUE /* Open Drain */
-#define RX62N_HAS_PORT2         TRUE
-#define RX62N_HAS_PORT2_OD      TRUE /* Open Drain */
-#define RX62N_HAS_PORT3         TRUE
-#define RX62N_HAS_PORT3_OD      TRUE /* Open Drain (P30 to P34) */
-#define RX62N_HAS_PORT4         TRUE
-#define RX62N_HAS_PORT5         TRUE
-#define RX62N_HAS_PORT6         FALSE
-#undef PORT6
-#define RX62N_HAS_PORT7         FALSE
-#undef PORT7
-#define RX62N_HAS_PORT8         FALSE
-#undef PORT8
-#define RX62N_HAS_PORT9         FALSE
-#undef PORT9
-#define RX62N_HAS_PORTA         TRUE
-#define RX62N_HAS_PORTA_PU      TRUE /* pull-up */
-#define RX62N_HAS_PORTB         TRUE
-#define RX62N_HAS_PORTB_PU      TRUE /* pull-up */
-#define RX62N_HAS_PORTC         TRUE
-#define RX62N_HAS_PORTC_OD      TRUE /* Open Drain */
-#define RX62N_HAS_PORTC_PU      TRUE /* Pull-up */
-#define RX62N_HAS_PORTD         TRUE
-#define RX62N_HAS_PORTD_PU      TRUE /* pull-up */
-#define RX62N_HAS_PORTE         TRUE
-#define RX62N_HAS_PORTE_PU      TRUE /* pull-up */
-#define RX62N_HAS_PORTF         FALSE
-#undef PORTF
-#define RX62N_HAS_PORTG         FALSE
-#undef PORTG
-
-/* I2C attributes.*/
-#define RX62N_HAS_I2C1          TRUE
-#define RX62N_HAS_I2C2          TRUE
-
-/* SDIO attributes.*/
-//#define RX62N_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define RX62N_HAS_SPI1          TRUE
-#define RX62N_HAS_SPI2          TRUE
-
-/* TIM attributes.*/
-#define RX62N_HAS_TIM1          TRUE
-#define RX62N_HAS_TIM2          TRUE
-#define RX62N_HAS_TIM3          TRUE
-#define RX62N_HAS_TIM4          TRUE
-#define RX62N_HAS_TIM5          TRUE
-#define RX62N_HAS_TIM6          TRUE
-#define RX62N_HAS_TIM7          TRUE
-#define RX62N_HAS_TIM8          TRUE
-#define RX62N_HAS_TIM9          TRUE
-#define RX62N_HAS_TIM10         TRUE
-#define RX62N_HAS_TIM11         TRUE
-#define RX62N_HAS_TIM12         TRUE
-
-/* USART attributes.*/
-#define RX62N_HAS_USART1        TRUE
-#define RX62N_HAS_USART2        TRUE
-#define RX62N_HAS_USART3        TRUE
-#define RX62N_HAS_USART4        TRUE
-#define RX62N_HAS_USART6        TRUE
-#define RX62N_HAS_USART7        TRUE
-
-/* USB attributes.*/
-/*#define RX62N_HAS_USB           TRUE*/
-/*#define RX62N_HAS_OTG1          TRUE*/
-
-/** @} */
-#endif /* defined(RX62NXADFP) || defined(RX62NXBDFP) */
-
-#if defined(RX62NXADLD) || defined (RX62NXBDLD) || defined(__DOXYGEN__)
-/**
- * @name    RX62NXXDLD capabilities (TFLGA85)
- * @{
- */
-
-#error "unsupported RX62N platform"
-
-/** @} */
-#endif /* defined(RX62NXADLD) || defined(RX62NXBDLD) */
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void rx62n_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/iodefine_gcc62n.h b/os/hal/platforms/Rx62n/iodefine_gcc62n.h
deleted file mode 100644
index 26067fa0c..000000000
--- a/os/hal/platforms/Rx62n/iodefine_gcc62n.h
+++ /dev/null
@@ -1,7317 +0,0 @@
-/***********************************************************************/
-/*                                                                     */
-/*  FILE        :iodefine.h                                            */
-/*  DATE        :Sun, Apr 17, 2011                                     */
-/*  DESCRIPTION :Definition of I/O Register                            */
-/*  CPU TYPE    :RX62N                                                 */
-/*                                                                     */
-/*  This file is Written by Atsu from Tokushu Denshi Kairo Inc.		   */
-/*  NOTE:THIS IS A TYPICAL EXAMPLE.                                    */
-/*                                                                     */
-/***********************************************************************/
-/************************************************************************
-*
-* Device     : RX/RX600/RX62N
-*
-* File Name  : ioedfine.h
-*
-* Abstract   : Definition of I/O Register.
-*
-* History    : 1.00  (2010-02-18)  [Hardware Manual Revision : 0.5]
-*            : 1.01  (2010-04-21)  [Hardware Manual Revision : 0.5]
-*            : 2.00  (2010-08-21)  [Hardware Manual Revision : 1.0]
-*
-* NOTE       : THIS IS A TYPICAL EXAMPLE.
-*
-*  Copyright (C) 2010 Renesas Electronics Corporation and
-*  Renesas Solutions Corp. All rights reserved.
-*
-************************************************************************/
-/********************************************************************************/
-/*                                                                              */
-/*  DESCRIPTION : Definition of ICU Register                                    */
-/*  CPU TYPE    : RX62N                                                         */
-/*                                                                              */
-/*  Usage : IR,DTCER,IER,IPR of ICU Register                                    */
-/*     The following IR, DTCE, IEN, IPR macro functions simplify usage.         */
-/*     The bit access operation is "Bit_Name(interrupt source,name)".           */
-/*     A part of the name can be omitted.                                       */
-/*     for example :                                                            */
-/*       IR(MTU0,TGIA0) = 0;     expands to :                                   */
-/*         ICU.IR[114].BIT.IR = 0;                                              */
-/*                                                                              */
-/*       DTCE(ICU,IRQ0) = 1;     expands to :                                   */
-/*         ICU.DTCER[64].BIT.DTCE = 1;                                          */
-/*                                                                              */
-/*       IEN(CMT0,CMI0) = 1;     expands to :                                   */
-/*         ICU.IER[0x03].BIT.IEN4 = 1;                                          */
-/*                                                                              */
-/*       IPR(MTU1,TGIA1) = 2;    expands to :                                   */
-/*       IPR(MTU1,TGI  ) = 2;    // TGIA1,TGIB1 share IPR level.                */
-/*         ICU.IPR[0x53].BIT.IPR = 2;                                           */
-/*                                                                              */
-/*       IPR(SCI0,ERI0) = 3;     expands to :                                   */
-/*       IPR(SCI0,    ) = 3;     // SCI0 uses single IPR for all sources.       */
-/*         ICU.IPR[0x80].BIT.IPR = 3;                                           */
-/*                                                                              */
-/*  Usage : #pragma interrupt Function_Identifier(vect=**)                      */
-/*     The number of vector is "(interrupt source, name)".                      */
-/*     for example :                                                            */
-/*       #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0))          expands to :  */
-/*         #pragma interrupt INT_IRQ0(vect=64)                                  */
-/*       #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0))    expands to :  */
-/*         #pragma interrupt INT_CMT0_CMI0(vect=28)                             */
-/*       #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0))  expands to :  */
-/*         #pragma interrupt INT_MTU0_TGIA0(vect=114)                           */
-/*                                                                              */
-/*  Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register                          */
-/*     The bit access operation is "MSTP(name)".                                */
-/*     The name that can be used is a macro name defined with "iodefine.h".     */
-/*     for example :                                                            */
-/*       MSTP(TMR2) = 0;    // TMR2,TMR3,TMR23                    expands to :  */
-/*         SYSTEM.MSTPCRA.BIT.MSTPA4  = 0;                                      */
-/*       MSTP(SCI0) = 0;    // SCI0,SMCI0                         expands to :  */
-/*         SYSTEM.MSTPCRB.BIT.MSTPB31 = 0;                                      */
-/*       MSTP(MTU4) = 0;    // MTUA,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to :  */
-/*         SYSTEM.MSTPCRA.BIT.MSTPA9  = 0;                                      */
-/*       MSTP(CMT3) = 0;    // CMT2,CMT3                          expands to :  */
-/*         SYSTEM.MSTPCRA.BIT.MSTPA14 = 0;                                      */
-/*                                                                              */
-/*                                                                              */
-/********************************************************************************/
-#ifndef __RX62NIODEFINE_HEADER__
-#define __RX62NIODEFINE_HEADER__
-// for gcc
-struct st_ad {
-	unsigned short ADDRA;
-	unsigned short ADDRB;
-	unsigned short ADDRC;
-	unsigned short ADDRD;
-	char           wk0[8];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CH:4;
-			unsigned char  :1;
-			unsigned char ADST:1;
-			unsigned char ADIE:1;
-			unsigned char  :1;
-		} BIT;
-	} ADCSR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MODE:2;
-			unsigned char CKS:2;
-			unsigned char  :1;
-			unsigned char TRGS:3;
-		} BIT;
-	} ADCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :7;
-			unsigned char DPSEL:1;
-		} BIT;
-	} ADDPR;
-	unsigned char  ADSSTR;
-	char           wk1[11];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DIAG:2;
-			unsigned char  :6;
-		} BIT;
-	} ADDIAGR;
-};
-
-struct st_bsc {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char STSCLR:1;
-			unsigned char  :7;
-		} BIT;
-	} BERCLR;
-	char           wk0[3];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IGAEN:1;
-			unsigned char TOEN:1;
-			unsigned char  :6;
-			
-			
-		} BIT;
-	} BEREN;
-	char           wk1[3];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IA:1;
-			unsigned char TO:1;
-			unsigned char  :2;
-			unsigned char MST:3;
-			unsigned char  :1;
-		} BIT;
-	} BERSR1;
-	char           wk2[1];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :3;
-			unsigned short ADDR:13;
-		} BIT;
-	} BERSR2;
-	char           wk3[7414];
-	union {
-		unsigned short WORD;
-		struct {
-				unsigned short WRMOD:1;
-				unsigned short  :2;
-				unsigned short EWENB:1;
-				unsigned short  :4;
-				unsigned short PRENB:1;
-				unsigned short PWENB:1;
-				unsigned short  :5;
-				unsigned short PRMOD:1;			
-		} BIT;
-	} CS0MOD;
-	union {
-		unsigned long LONG;
-		struct {
-				unsigned long CSPWWAIT:3;
-				unsigned long  :5;
-				unsigned long CSPRWAIT:3;
-				unsigned long  :5;
-				unsigned long CSWWAIT:5;
-				unsigned long  :3;
-				unsigned long CSRWAIT:5;
-				unsigned long  :3;
-		} BIT;
-	} CS0WCR1;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSROFF:3;
-			unsigned long  :1;
-			unsigned long CSWOFF:3;
-			unsigned long  :1;
-			unsigned long WDOFF:3;
-			unsigned long  :5;
-			unsigned long RDON:3;
-			unsigned long  :1;
-			unsigned long WRON:3;
-			unsigned long  :1;
-			unsigned long WDON:3;
-			unsigned long  :1;
-			unsigned long CSON:3;
-			unsigned long  :1;
-		} BIT;
-	} CS0WCR2;
-	char           wk4[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short WRMOD:1;
-			unsigned short  :2;
-			unsigned short EWENB:1;
-			unsigned short  :4;
-			unsigned short PRENB:1;
-			unsigned short PWENB:1;
-			unsigned short  :5;
-			unsigned short PRMOD:1;
-		} BIT;
-	} CS1MOD;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSPWWAIT:3;
-			unsigned long  :5;
-			unsigned long CSPRWAIT:3;
-			unsigned long  :5;
-			unsigned long CSWWAIT:5;
-			unsigned long  :3;
-			unsigned long CSRWAIT:5;
-			unsigned long  :3;
-		} BIT;
-	} CS1WCR1;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSROFF:3;
-			unsigned long  :1;
-			unsigned long CSWOFF:3;
-			unsigned long  :1;
-			unsigned long WDOFF:3;
-			unsigned long  :5;
-			unsigned long RDON:3;
-			unsigned long  :1;
-			unsigned long WRON:3;
-			unsigned long  :1;
-			unsigned long WDON:3;
-			unsigned long  :1;
-			unsigned long CSON:3;
-			unsigned long  :1;
-		} BIT;
-	} CS1WCR2;
-	char           wk5[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short WRMOD:1;
-			unsigned short  :2;
-			unsigned short EWENB:1;
-			unsigned short  :4;
-			unsigned short PRENB:1;
-			unsigned short PWENB:1;
-			unsigned short  :5;
-			unsigned short PRMOD:1;			
-		} BIT;
-	} CS2MOD;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSPWWAIT:3;
-			unsigned long  :5;
-			unsigned long CSPRWAIT:3;
-			unsigned long  :5;
-			unsigned long CSWWAIT:5;
-			unsigned long  :3;
-			unsigned long CSRWAIT:5;
-			unsigned long  :3;
-		} BIT;
-	} CS2WCR1;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSROFF:3;
-			unsigned long  :1;
-			unsigned long CSWOFF:3;
-			unsigned long  :1;
-			unsigned long WDOFF:3;
-			unsigned long  :5;
-			unsigned long RDON:3;
-			unsigned long  :1;
-			unsigned long WRON:3;
-			unsigned long  :1;
-			unsigned long WDON:3;
-			unsigned long  :1;
-			unsigned long CSON:3;
-			unsigned long  :1;
-		} BIT;
-	} CS2WCR2;
-	char           wk6[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short WRMOD:1;
-			unsigned short  :2;
-			unsigned short EWENB:1;
-			unsigned short  :4;
-			unsigned short PRENB:1;
-			unsigned short PWENB:1;
-			unsigned short  :5;
-			unsigned short PRMOD:1;
-		} BIT;
-	} CS3MOD;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSPWWAIT:3;
-			unsigned long  :5;
-			unsigned long CSPRWAIT:3;
-			unsigned long  :5;
-			unsigned long CSWWAIT:5;
-			unsigned long  :3;
-			unsigned long CSRWAIT:5;
-			unsigned long  :3;
-		} BIT;
-	} CS3WCR1;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSROFF:3;
-			unsigned long  :1;
-			unsigned long CSWOFF:3;
-			unsigned long  :1;
-			unsigned long WDOFF:3;
-			unsigned long  :5;
-			unsigned long RDON:3;
-			unsigned long  :1;
-			unsigned long WRON:3;
-			unsigned long  :1;
-			unsigned long WDON:3;
-			unsigned long  :1;
-			unsigned long CSON:3;
-			unsigned long  :1;
-		} BIT;
-	} CS3WCR2;
-	char           wk7[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short WRMOD:1;
-			unsigned short  :2;
-			unsigned short EWENB:1;
-			unsigned short  :4;
-			unsigned short PRENB:1;
-			unsigned short PWENB:1;
-			unsigned short  :5;
-			unsigned short PRMOD:1;
-		} BIT;
-	} CS4MOD;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSPWWAIT:3;
-			unsigned long  :5;
-			unsigned long CSPRWAIT:3;
-			unsigned long  :5;
-			unsigned long CSWWAIT:5;
-			unsigned long  :3;
-			unsigned long CSRWAIT:5;
-			unsigned long  :3;
-		} BIT;
-	} CS4WCR1;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSROFF:3;
-			unsigned long  :1;
-			unsigned long CSWOFF:3;
-			unsigned long  :1;
-			unsigned long WDOFF:3;
-			unsigned long  :5;
-			unsigned long RDON:3;
-			unsigned long  :1;
-			unsigned long WRON:3;
-			unsigned long  :1;
-			unsigned long WDON:3;
-			unsigned long  :1;
-			unsigned long CSON:3;
-			unsigned long  :1;
-		} BIT;
-	} CS4WCR2;
-	char           wk8[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short WRMOD:1;
-			unsigned short  :2;
-			unsigned short EWENB:1;
-			unsigned short  :4;
-			unsigned short PRENB:1;
-			unsigned short PWENB:1;
-			unsigned short  :5;
-			unsigned short PRMOD:1;
-		} BIT;
-	} CS5MOD;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSPWWAIT:3;
-			unsigned long  :5;
-			unsigned long CSPRWAIT:3;
-			unsigned long  :5;
-			unsigned long CSWWAIT:5;
-			unsigned long  :3;
-			unsigned long CSRWAIT:5;
-			unsigned long  :3;
-		} BIT;
-	} CS5WCR1;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSROFF:3;
-			unsigned long  :1;
-			unsigned long CSWOFF:3;
-			unsigned long  :1;
-			unsigned long WDOFF:3;
-			unsigned long  :5;
-			unsigned long RDON:3;
-			unsigned long  :1;
-			unsigned long WRON:3;
-			unsigned long  :1;
-			unsigned long WDON:3;
-			unsigned long  :1;
-			unsigned long CSON:3;
-			unsigned long  :1;
-		} BIT;
-	} CS5WCR2;
-	char           wk9[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short WRMOD:1;
-			unsigned short  :2;
-			unsigned short EWENB:1;
-			unsigned short  :4;
-			unsigned short PRENB:1;
-			unsigned short PWENB:1;
-			unsigned short  :5;
-			unsigned short PRMOD:1;
-		} BIT;
-	} CS6MOD;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSPWWAIT:3;
-			unsigned long  :5;
-			unsigned long CSPRWAIT:3;
-			unsigned long  :5;
-			unsigned long CSWWAIT:5;
-			unsigned long  :3;
-			unsigned long CSRWAIT:5;
-			unsigned long  :3;
-		} BIT;
-	} CS6WCR1;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSROFF:3;
-			unsigned long  :1;
-			unsigned long CSWOFF:3;
-			unsigned long  :1;
-			unsigned long WDOFF:3;
-			unsigned long  :5;
-			unsigned long RDON:3;
-			unsigned long  :1;
-			unsigned long WRON:3;
-			unsigned long  :1;
-			unsigned long WDON:3;
-			unsigned long  :1;
-			unsigned long CSON:3;
-			unsigned long  :1;
-		} BIT;
-	} CS6WCR2;
-	char           wk10[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short WRMOD:1;
-			unsigned short  :2;
-			unsigned short EWENB:1;
-			unsigned short  :4;
-			unsigned short PRENB:1;
-			unsigned short PWENB:1;
-			unsigned short  :5;
-			unsigned short PRMOD:1;
-		} BIT;
-	} CS7MOD;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSPWWAIT:3;
-			unsigned long  :5;
-			unsigned long CSPRWAIT:3;
-			unsigned long  :5;
-			unsigned long CSWWAIT:5;
-			unsigned long  :3;
-			unsigned long CSRWAIT:5;
-			unsigned long  :3;
-		} BIT;
-	} CS7WCR1;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CSROFF:3;
-			unsigned long  :1;
-			unsigned long CSWOFF:3;
-			unsigned long  :1;
-			unsigned long WDOFF:3;
-			unsigned long  :5;
-			unsigned long RDON:3;
-			unsigned long  :1;
-			unsigned long WRON:3;
-			unsigned long  :1;
-			unsigned long WDON:3;
-			unsigned long  :1;
-			unsigned long CSON:3;
-			unsigned long  :1;
-		} BIT;
-	} CS7WCR2;
-	char           wk11[1926];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short EXENB:1;
-			unsigned short  :3;
-			unsigned short BSIZE:2;
-			unsigned short  :2;
-			unsigned short EMODE:1;
-			unsigned short  :7;
-		} BIT;
-	} CS0CR;
-	char           wk12[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RRCV:4;
-			unsigned short  :4;
-			unsigned short WRCV:4;
-			unsigned short  :4;
-		} BIT;
-	} CS0REC;
-	char           wk13[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short EXENB:1;
-			unsigned short  :3;
-			unsigned short BSIZE:2;
-			unsigned short  :2;
-			unsigned short EMODE:1;
-			unsigned short  :7;
-		} BIT;
-	} CS1CR;
-	char           wk14[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RRCV:4;
-			unsigned short  :4;
-			unsigned short WRCV:4;
-			unsigned short  :4;
-		} BIT;
-	} CS1REC;
-	char           wk15[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short EXENB:1;
-			unsigned short  :3;
-			unsigned short BSIZE:2;
-			unsigned short  :2;
-			unsigned short EMODE:1;
-			unsigned short  :7;
-		} BIT;
-	} CS2CR;
-	char           wk16[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RRCV:4;
-			unsigned short  :4;
-			unsigned short WRCV:4;
-			unsigned short  :4;
-		} BIT;
-	} CS2REC;
-	char           wk17[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short EXENB:1;
-			unsigned short  :3;
-			unsigned short BSIZE:2;
-			unsigned short  :2;
-			unsigned short EMODE:1;
-			unsigned short  :7;
-		} BIT;
-	} CS3CR;
-	char           wk18[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RRCV:4;
-			unsigned short  :4;
-			unsigned short WRCV:4;
-			unsigned short  :4;
-		} BIT;
-	} CS3REC;
-	char           wk19[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short EXENB:1;
-			unsigned short  :3;
-			unsigned short BSIZE:2;
-			unsigned short  :2;
-			unsigned short EMODE:1;
-			unsigned short  :7;
-		} BIT;
-	} CS4CR;
-	char           wk20[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RRCV:4;
-			unsigned short  :4;
-			unsigned short WRCV:4;
-			unsigned short  :4;
-		} BIT;
-	} CS4REC;
-	char           wk21[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short EXENB:1;
-			unsigned short  :3;
-			unsigned short BSIZE:2;
-			unsigned short  :2;
-			unsigned short EMODE:1;
-			unsigned short  :7;
-		} BIT;
-	} CS5CR;
-	char           wk22[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RRCV:4;
-			unsigned short  :4;
-			unsigned short WRCV:4;
-			unsigned short  :4;
-		} BIT;
-	} CS5REC;
-	char           wk23[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short EXENB:1;
-			unsigned short  :3;
-			unsigned short BSIZE:2;
-			unsigned short  :2;
-			unsigned short EMODE:1;
-			unsigned short  :7;
-		} BIT;
-	} CS6CR;
-	char           wk24[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RRCV:4;
-			unsigned short  :4;
-			unsigned short WRCV:4;
-			unsigned short  :4;
-		} BIT;
-	} CS6REC;
-	char           wk25[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short EXENB:1;
-			unsigned short  :3;
-			unsigned short BSIZE:2;
-			unsigned short  :2;
-			unsigned short EMODE:1;
-			unsigned short  :7;
-		} BIT;
-	} CS7CR;
-	char           wk26[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RRCV:4;
-			unsigned short  :4;
-			unsigned short WRCV:4;
-			unsigned short  :4;
-		} BIT;
-	} CS7REC;
-	char           wk27[900];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char EXENB:1;
-			unsigned char  :3;
-			unsigned char BSIZE:2;
-			unsigned char  :2;
-		} BIT;
-	} SDCCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char EMODE:1;
-			unsigned char  :7;
-		} BIT;
-	} SDCMOD;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char BE:1;
-			unsigned char  :7;
-		} BIT;
-	} SDAMOD;
-	char           wk28[13];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SFEN:1;
-			unsigned char  :7;
-		} BIT;
-	} SDSELF;
-	char           wk29[3];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RFC:12;
-			unsigned short REFW:4;
-		} BIT;
-	} SDRFCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char RFEN:1;
-			unsigned char  :7;
-		} BIT;
-	} SDRFEN;
-	char           wk30[9];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char INIRQ:1;
-			unsigned char  :7;
-		} BIT;
-	} SDICR;
-	char           wk31[3];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short ARFI:4;
-			unsigned short ARFC:4;
-			unsigned short PRC:3;
-			unsigned short  :5;
-		} BIT;
-	} SDIR;
-	char           wk32[26];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MXC:2;
-			unsigned char  :6;
-		} BIT;
-	} SDADR;
-	char           wk33[3];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CL:3;
-			unsigned long  :5;
-			unsigned long WR:1;
-			unsigned long RP:3;
-			unsigned long RCD:2;
-			unsigned long  :2;
-			unsigned long RAS:3;
-			unsigned long  :13;
-		} BIT;
-	} SDTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short MR:15;
-			unsigned short  :1;
-		} BIT;
-	} SDMOD;
-	char           wk34[6];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MRSST:1;
-			unsigned char  :2;
-			unsigned char INIST:1;
-			unsigned char SRFST:1;
-			unsigned char  :3;
-		} BIT;
-	} SDSR;
-};
-
-struct st_can {
-	struct {
-		union {
-			unsigned long LONG;
-			struct {
-				unsigned short L;
-				unsigned short H;
-			} WORD;
-			struct {
-				unsigned char LL;
-				unsigned char LH;
-				unsigned char HL;
-				unsigned char HH;
-			} BYTE;
-			struct {
-				unsigned long EID:18;
-				unsigned long SID:11;
-				unsigned long  :1;
-				unsigned long RTR:1;
-				unsigned long IDE:1;
-			} BIT;
-		} ID;
-		union {
-			unsigned short WORD;
-			struct {
-				unsigned char L;
-				unsigned char H;
-			} BYTE;
-/* -- oops!
-			struct {
-				unsigned char DLC:4;
-				unsigned char  :4;
-				unsigned char  :8;
-			
-			} BIT;
-*/
-		} DLC;
-		unsigned char  DATA[8];
-		union {
-			unsigned short WORD;
-			struct {
-				unsigned char TSL;
-				unsigned char TSH;
-			} BYTE;
-		} TS;
-	} MB[32];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned short L;
-			unsigned short H;
-		} WORD;
-		struct {
-			unsigned char LL;
-			unsigned char LH;
-			unsigned char HL;
-			unsigned char HH;
-		} BYTE;
-		struct {
-			unsigned long EID:18;
-			unsigned long SID:11;
-			unsigned long  :3;
-		} BIT;
-	} MKR[8];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned short L;
-			unsigned short H;
-		} WORD;
-		struct {
-			unsigned char LL;
-			unsigned char LH;
-			unsigned char HL;
-			unsigned char HH;
-		} BYTE;
-		struct {
-			unsigned long EID:18;
-			unsigned long SID:11;
-			unsigned long  :1;
-			unsigned long RTR:1;
-			unsigned long IDE:1;
-		} BIT;
-	} FIDCR0;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned short L;
-			unsigned short H;
-		} WORD;
-		struct {
-			unsigned char LL;
-			unsigned char LH;
-			unsigned char HL;
-			unsigned char HH;
-		} BYTE;
-		struct {
-			unsigned long EID:18;
-			unsigned long SID:11;
-			unsigned long  :1;
-			unsigned long RTR:1;
-			unsigned long IDE:1;
-		} BIT;
-	} FIDCR1;
-	unsigned long  MKIVLR;
-	unsigned long  MIER;
-	char           wk0[1008];
-	union {
-		unsigned char BYTE;
-		union {
-			struct {
-				unsigned char SENTDATA:1;
-				unsigned char TRMACTIVE:1;
-				unsigned char TRMABT:1;
-				unsigned char  :1;
-				unsigned char ONESHOT:1;
-				unsigned char  :1;
-				unsigned char RECREQ:1;
-				unsigned char TRMREQ:1;
-			} TX;
-			struct {
-				unsigned char NEWDATA:1;
-				unsigned char INVALDATA:1;
-				unsigned char MSGLOST:1;
-				unsigned char  :5;
-			} RX;
-		} BIT;
-	} MCTL[32];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned char L;
-			unsigned char H;
-		} BYTE;
-		struct {
-			unsigned char MBM:1;
-			unsigned char IDFM:2;
-			unsigned char MLM:1;
-			unsigned char TPM:1;
-			unsigned char TSRC:1;
-			unsigned char TSPS:2;
-			unsigned char CANM:2;
-			unsigned char SLPM:1;
-			unsigned char BOM:2;
-			unsigned char RBOC:1;
-			unsigned char  :2;
-		} BIT;
-	} CTLR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned char L;
-			unsigned char H;
-		} BYTE;
-		struct {
-			unsigned char NDST:1;
-			unsigned char SDST:1;
-			unsigned char RFST:1;
-			unsigned char TFST:1;
-			unsigned char NMLST:1;
-			unsigned char FMLST:1;
-			unsigned char TABST:1;
-			unsigned char EST:1;
-			unsigned char RSTST:1;
-			unsigned char HLTST:1;
-			unsigned char SLPST:1;
-			unsigned char EPST:1;
-			unsigned char BOST:1;
-			unsigned char TRMST:1;
-			unsigned char RECST:1;
-			unsigned char  :1;
-		} BIT;
-	} STR;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned short L;
-			unsigned short H;
-		} WORD;
-		struct {
-			unsigned char LL;
-			unsigned char LH;
-			unsigned char HL;
-			unsigned char HH;
-		} BYTE;
-		struct {
-			unsigned long  :8;
-			unsigned long TSEG2:3;
-			unsigned long  :1;
-			unsigned long SJW:2;
-			unsigned long  :2;
-			unsigned long BRP:10;
-			unsigned long  :2;
-			unsigned long TSEG1:4;
-		} BIT;
-
-	} BCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char RFE:1;
-			unsigned char RFUST:3;
-			unsigned char RFMLF:1;
-			unsigned char RFFST:1;
-			unsigned char RFWST:1;
-			unsigned char RFEST:1;
-		} BIT;
-	} RFCR;
-	unsigned char  RFPCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TFE:1;
-			unsigned char TFUST:3;
-			unsigned char  :2;
-			unsigned char TFFST:1;
-			unsigned char TFEST:1;
-		} BIT;
-	} TFCR;
-	unsigned char  TFPCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char BEIE:1;
-			unsigned char EWIE:1;
-			unsigned char EPIE:1;
-			unsigned char BOEIE:1;
-			unsigned char BORIE:1;
-			unsigned char ORIE:1;
-			unsigned char OLIE:1;
-			unsigned char BLIE:1;
-		} BIT;
-	} EIER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char BEIF:1;
-			unsigned char EWIF:1;
-			unsigned char EPIF:1;
-			unsigned char BOEIF:1;
-			unsigned char BORIF:1;
-			unsigned char ORIF:1;
-			unsigned char OLIF:1;
-			unsigned char BLIF:1;
-		} BIT;
-	} EIFR;
-	unsigned char  RECR;
-	unsigned char  TECR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SEF:1;
-			unsigned char FEF:1;
-			unsigned char AEF:1;
-			unsigned char CEF:1;
-			unsigned char BE1F:1;
-			unsigned char BE0F:1;
-			unsigned char ADEF:1;
-			unsigned char EDPM:1;
-		} BIT;
-	} ECSR;
-	unsigned char  CSSR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MBNST:5;
-			unsigned char  :2;
-			unsigned char SEST:1;
-		} BIT;
-	} MSSR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MBSM:2;
-			unsigned char  :6;
-		} BIT;
-	} MSMR;
-	unsigned short TSR;
-	unsigned short AFSR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TSTE:1;
-			unsigned char TSTM:2;
-			unsigned char  :5;
-		} BIT;
-	} TCR;
-};
-
-struct st_cmt {
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short STR0:1;
-			unsigned short STR1:1;
-			unsigned short  :14;
-		} BIT;
-	} CMSTR0;
-	char           wk0[14];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short STR2:1;
-			unsigned short STR3:1;
-			unsigned short  :14;
-		} BIT;
-	} CMSTR1;
-};
-
-struct st_cmt0 {
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CKS:2;
-			unsigned short  :4;
-			unsigned short CMIE:1;
-			unsigned short  :9;
-		} BIT;
-	} CMCR;
-	unsigned short CMCNT;
-	unsigned short CMCOR;
-};
-
-struct st_crc {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char GPS:2;
-			unsigned char LMS:1;
-			unsigned char  :4;
-			unsigned char DORCLR:1;
-		} BIT;
-	} CRCCR;
-	unsigned char  CRCDIR;
-	unsigned short CRCDOR;
-};
-
-struct st_da {
-	unsigned short DADR0;
-	unsigned short DADR1;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :5;
-			unsigned char DAE:1;
-			unsigned char DAOE0:1;
-			unsigned char DAOE1:1;
-		} BIT;
-	} DACR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :7;
-			unsigned char DPSEL:1;
-		} BIT;
-	} DADPR;
-};
-
-struct st_dmac {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DMST:1;
-			unsigned char  :7;
-		} BIT;
-	} DMAST;
-};
-
-struct st_dmac0 {
-	void          *DMSAR;
-	void          *DMDAR;
-	unsigned long  DMCRA;
-	unsigned short DMCRB;
-	char           wk0[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short DCTG:2;
-			unsigned short  :6;
-			unsigned short SZ:2;
-			unsigned short  :2;
-			unsigned short DTS:2;
-			unsigned short MD:2;
-		} BIT;
-	} DMTMD;
-	char           wk1[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DARIE:1;
-			unsigned char SARIE:1;
-			unsigned char RPTIE:1;
-			unsigned char ESIE:1;
-			unsigned char DTIE:1;
-			unsigned char  :3;
-		} BIT;
-	} DMINT;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short DARA:5;
-			unsigned short  :1;
-			unsigned short DM:2;
-			unsigned short SARA:5;
-			unsigned short  :1;
-			unsigned short SM:2;
-		} BIT;
-	} DMAMD;
-	char           wk2[2];
-	unsigned long  DMOFR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DTE:1;
-			unsigned char  :7;
-		} BIT;
-	} DMCNT;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SWREQ:1;
-			unsigned char  :3;
-			unsigned char CLRS:1;
-			unsigned char  :3;
-		} BIT;
-	} DMREQ;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ESIF:1;
-			unsigned char  :3;
-			unsigned char DTIF:1;
-			unsigned char  :2;
-			unsigned char ACT:1;	
-		} BIT;
-	} DMSTS;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DISEL:1;
-			unsigned char  :7;
-		} BIT;
-	} DMCSL;
-};
-
-struct st_dmac1 {
-	void          *DMSAR;
-	void          *DMDAR;
-	unsigned long  DMCRA;
-	unsigned short DMCRB;
-	char           wk0[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short DCTG:2;
-			unsigned short  :6;
-			unsigned short SZ:2;
-			unsigned short  :2;
-			unsigned short DTS:2;
-			unsigned short MD:2;
-		} BIT;
-	} DMTMD;
-	char           wk1[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DARIE:1;
-			unsigned char SARIE:1;
-			unsigned char RPTIE:1;
-			unsigned char ESIE:1;
-			unsigned char DTIE:1;
-			unsigned char  :3;
-		} BIT;
-	} DMINT;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short DARA:5;
-			unsigned short  :1;
-			unsigned short DM:2;
-			unsigned short SARA:5;
-			unsigned short  :1;
-			unsigned short SM:2;
-		} BIT;
-	} DMAMD;
-	char           wk2[6];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DTE:1;
-			unsigned char  :7;
-		} BIT;
-	} DMCNT;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SWREQ:1;
-			unsigned char  :3;
-			unsigned char CLRS:1;
-			unsigned char  :3;
-		} BIT;
-	} DMREQ;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ESIF:1;
-			unsigned char  :3;
-			unsigned char DTIF:1;
-			unsigned char  :2;
-			unsigned char ACT:1;
-		} BIT;
-	} DMSTS;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DISEL:1;
-			unsigned char  :7;
-		} BIT;
-	} DMCSL;
-};
-
-struct st_dtc {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :4;
-			unsigned char RRS:1;
-			unsigned char  :3;
-		} BIT;
-	} DTCCR;
-	char           wk0[3];
-	void          *DTCVBR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SHORT:1;
-			unsigned char DTCADMOD:7;
-		} BIT;
-	} DTCADMOD;
-	char           wk1[3];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DTCST:1;
-			unsigned char DTCADMOD:7;
-		} BIT;
-	} DTCST;
-	char           wk2[1];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short VECN:8;
-			unsigned short  :7;
-			unsigned short ACT:1;
-		} BIT;
-*/
-	} DTCSTS;
-};
-
-struct st_edmac {
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long SWR:1;
-			unsigned long  :3;
-			unsigned long DL:2;
-			unsigned long DE:1;
-			unsigned long  :25;
-		} BIT;
-	} EDMR;
-	char           wk0[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long TR:1;
-			unsigned long  :31;
-		} BIT;
-	} EDTRR;
-	char           wk1[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long RR:1;
-			unsigned long  :31;
-		} BIT;
-	} EDRRR;
-	char           wk2[4];
-	void          *TDLAR;
-	char           wk3[4];
-	void          *RDLAR;
-	char           wk4[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CERF:1;
-			unsigned long PRE:1;
-			unsigned long RTSF:1;
-			unsigned long RTLF:1;
-			unsigned long RRF:1;
-			unsigned long  :2;
-			unsigned long RMAF:1;
-			unsigned long TRO:1;
-			unsigned long CD:1;
-			unsigned long DLC:1;
-			unsigned long CND:1;
-			unsigned long  :4;
-			unsigned long RFOF:1;
-			unsigned long RDE:1;
-			unsigned long FR:1;
-			unsigned long TFUF:1;
-			unsigned long TDE:1;
-			unsigned long TC:1;
-			unsigned long ECI:1;
-			unsigned long ADE:1;
-			unsigned long RFCOF:1;
-			unsigned long RABT:1;
-			unsigned long TABT:1;
-			unsigned long  :3;
-			unsigned long TWB:1;
-			unsigned long  :1;
-		} BIT;
-	} EESR;
-	char           wk5[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CERFIP:1;
-			unsigned long PREIP:1;
-			unsigned long RTSFIP:1;
-			unsigned long RTLFIP:1;
-			unsigned long RRFIP:1;
-			unsigned long  :2;
-			unsigned long RMAFIP:1;
-			unsigned long TROIP:1;
-			unsigned long CDIP:1;
-			unsigned long DLCIP:1;
-			unsigned long CNDIP:1;
-			unsigned long  :4;
-			unsigned long RFOFIP:1;
-			unsigned long RDEIP:1;
-			unsigned long FRIP:1;
-			unsigned long TFUFIP:1;
-			unsigned long TDEIP:1;
-			unsigned long TCIP:1;
-			unsigned long ECIIP:1;
-			unsigned long ADEIP:1;
-			unsigned long RFCOFIP:1;
-			unsigned long RABTIP:1;
-			unsigned long TABTIP:1;
-			unsigned long  :3;
-			unsigned long TWBIP:1;
-			unsigned long  :1;
-		} BIT;
-	} EESIPR;
-	char           wk6[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long CERFCE:1;
-			unsigned long PRECE:1;
-			unsigned long RTSFCE:1;
-			unsigned long RTLFCE:1;
-			unsigned long RRFCE:1;
-			unsigned long  :2;
-			unsigned long RMAFCE:1;
-			unsigned long TROCE:1;
-			unsigned long CDCE:1;
-			unsigned long DLCCE:1;
-			unsigned long CNDCE:1;
-			unsigned long  :20;
-		} BIT;
-	} TRSCER;
-	char           wk7[4];
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long MFC:16;
-			unsigned long  :16;
-		} BIT;
-*/
-	} RMFCR;
-	char           wk8[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long TFT:11;
-			unsigned long  :21;
-		} BIT;
-	} TFTR;
-	char           wk9[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long RFD:5;
-			unsigned long  :3;
-			unsigned long TFD:5;
-			unsigned long  :19;
-		} BIT;
-	} FDR;
-	char           wk10[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long RNR:1;
-			unsigned long RNC:1;
-			unsigned long :30;
-		} BIT;
-	} RMCR;
-	char           wk11[8];
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long UNDER:16;
-			unsigned long  :16;
-		} BIT;
-*/
-	} TFUCR;
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long OVER:16;
-			unsigned long  :16;
-		} BIT;
-*/
-	} RFOCR;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long ELB:1;
-			unsigned long  :31;
-		} BIT;
-	} IOSR;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long RFDO:3;
-			unsigned long  :13;
-			unsigned long RFFO:3;
-			unsigned long  :13;
-		} BIT;
-	} FCFTR;
-	char           wk12[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long PADR:6;
-			unsigned long  :10;
-			unsigned long PADS:2;
-			unsigned long  :14;
-		} BIT;
-	} RPADIR;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long TIS:1;
-			unsigned long  :3;
-			unsigned long TIM:1;
-			unsigned long  :27;
-		} BIT;
-	} TRIMD;
-	char           wk13[72];
-	void          *RBWAR;
-	void          *RDFAR;
-	char           wk14[4];
-	void          *TBRAR;
-	void          *TDFAR;
-};
-
-struct st_etherc {
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long PRM:1;
-			unsigned long DM:1;
-			unsigned long RTM:1;
-			unsigned long ILB:1;
-			unsigned long  :1;
-			unsigned long TE:1;
-			unsigned long RE:1;
-			unsigned long  :2;
-			unsigned long MPDE:1;
-			unsigned long  :2;
-			unsigned long PRCEF:1;
-			unsigned long  :3;
-			unsigned long TXF:1;
-			unsigned long RXF:1;
-			unsigned long PFR:1;
-			unsigned long ZPE:1;
-			unsigned long TPC:1;
-			unsigned long  :11;
-		} BIT;
-	} ECMR;
-	char           wk0[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long RFL:12;
-			unsigned long  :20;
-		} BIT;
-	} RFLR;
-	char           wk1[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long ICD:1;
-			unsigned long MPD:1;
-			unsigned long LCHNG:1;
-			unsigned long  :1;
-			unsigned long PSRTO:1;
-			unsigned long BFR:1;
-			unsigned long  :26;
-		} BIT;
-	} ECSR;
-	char           wk2[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long ICDIP:1;
-			unsigned long MPDIP:1;
-			unsigned long LCHNGIP:1;
-			unsigned long  :1;
-			unsigned long PSRTOIP:1;
-			unsigned long BFSIPR:1;
-			unsigned long  :26;
-		} BIT;
-	} ECSIPR;
-	char           wk3[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long MDC:1;
-			unsigned long MMD:1;
-			unsigned long MDO:1;
-			unsigned long MDI:1;
-			unsigned long  :28;
-		} BIT;
-	} PIR;
-	char           wk4[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long LMON:1;
-			unsigned long  :31;
-		} BIT;
-	} PSR;
-	char           wk5[20];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long RMD:20;
-			unsigned long  :12;
-		} BIT;
-	} RDMLR;
-	char           wk6[12];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long IPG:5;
-			unsigned long  :27;
-		} BIT;
-	} IPGR;
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long AP:16;
-			unsigned long  :16;
-		} BIT;
-*/
-	} APR;
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long MP:16;
-			unsigned long  :16;
-		} BIT;
-*/
-	} MPR;
-	char           wk7[4];
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long RPAUSE:8;
-			unsigned long  :24;
-		} BIT;
-*/
-	} RFCF;
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long TPAUSE:16;
-			unsigned long  :16;
-		} BIT;
-*/
-	} TPAUSER;
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long TXP:8;
-			unsigned long  :24;
-		} BIT;
-*/
-	} TPAUSECR;
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long BCF:16;
-			unsigned long  :16;
-		} BIT;
-*/
-	} BCFRR;
-	char           wk8[80];
-	unsigned long  MAHR;
-	char           wk9[4];
-	union {
-		unsigned long LONG;
-/* -- oops!
-		struct {
-			unsigned long MA:16;
-			unsigned long  :16;
-		} BIT;
-*/
-	} MALR;
-	char           wk10[4];
-	unsigned long  TROCR;
-	unsigned long  CDCR;
-	unsigned long  LCCR;
-	unsigned long  CNDCR;
-	char           wk11[4];
-	unsigned long  CEFCR;
-	unsigned long  FRECR;
-	unsigned long  TSFRCR;
-	unsigned long  TLFRCR;
-	unsigned long  RFCR;
-	unsigned long  MAFCR;
-};
-
-struct st_exdmac {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DMST:1;
-			unsigned char  :7;
-		} BIT;
-	} EDMAST;
-	char           wk0[479];
-	unsigned long  CLSBR0;
-	unsigned long  CLSBR1;
-	unsigned long  CLSBR2;
-	unsigned long  CLSBR3;
-	unsigned long  CLSBR4;
-	unsigned long  CLSBR5;
-	unsigned long  CLSBR6;
-	unsigned long  CLSBR7;
-};
-
-struct st_exdmac0 {
-	void          *EDMSAR;
-	void          *EDMDAR;
-	unsigned long  EDMCRA;
-	unsigned short EDMCRB;
-	char           wk0[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short DCTG:2;
-			unsigned short  :6;
-			unsigned short SZ:2;
-			unsigned short  :2;
-			unsigned short DTS:2;
-			unsigned short MD:2;
-		} BIT;
-	} EDMTMD;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DACKSEL:1; // ����
-			unsigned char DACKW:1;
-			unsigned char DACKE:1;
-			unsigned char DACKS:1;
-			unsigned char  :4;
-		} BIT;
-	} EDMOMD;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DARIE:1;
-			unsigned char SARIE:1;
-			unsigned char RPTIE:1;
-			unsigned char ESIE:1;
-			unsigned char DTIE:1;
-			unsigned char  :3;
-		} BIT;
-	} EDMINT;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long DARA:5;
-			unsigned long  :1;
-			unsigned long DM:2;
-			unsigned long SARA:5;
-			unsigned long  :1;
-			unsigned long SM:2;
-			unsigned long DIR:1;
-			unsigned long AMS:1;
-			unsigned long  :14;
-		} BIT;
-	} EDMAMD;
-	unsigned long  EDMOFR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DTE:1;
-			unsigned char  :7;
-		} BIT;
-	} EDMCNT;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SWREQ:1;
-			unsigned char  :3;
-			unsigned char CLRS:1;
-			unsigned char  :3;
-		} BIT;
-	} EDMREQ;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ESIF:1;
-			unsigned char  :3;
-			unsigned char DTIF:1;
-			unsigned char  :2;
-			unsigned char ACT:1;
-		} BIT;
-	} EDMSTS;
-	char           wk1[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DREQS:2;
-			unsigned char  :6;
-		} BIT;
-	} EDMRMD;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char EREQ:1;
-			unsigned char  :7;
-		} BIT;
-	} EDMERF;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char PREQ:1;
-			unsigned char  :7;
-		} BIT;
-	} EDMPRF;
-};
-
-struct st_exdmac1 {
-	void          *EDMSAR;
-	void          *EDMDAR;
-	unsigned long  EDMCRA;
-	unsigned short EDMCRB;
-	char           wk0[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short DCTG:2;
-			unsigned short  :6;
-			unsigned short SZ:2;
-			unsigned short  :2;
-			unsigned short DTS:2;
-			unsigned short MD:2;
-		} BIT;
-	} EDMTMD;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DACKSEL:1; // ����
-			unsigned char DACKW:1;
-			unsigned char DACKE:1;
-			unsigned char DACKS:1;
-			unsigned char  :4;
-		} BIT;
-	} EDMOMD;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DARIE:1;
-			unsigned char SARIE:1;
-			unsigned char RPTIE:1;
-			unsigned char ESIE:1;
-			unsigned char DTIE:1;
-			unsigned char  :3;
-		} BIT;
-	} EDMINT;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long DARA:5;
-			unsigned long  :1;
-			unsigned long DM:2;
-			unsigned long SARA:5;
-			unsigned long  :1;
-			unsigned long SM:2;
-			unsigned long DIR:1;
-			unsigned long AMS:1;
-			unsigned long  :14;
-		} BIT;
-	} EDMAMD;
-	char           wk1[4];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DTE:1;
-			unsigned char  :7;
-		} BIT;
-	} EDMCNT;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SWREQ:1;
-			unsigned char  :3;
-			unsigned char CLRS:1;
-			unsigned char  :3;
-		} BIT;
-	} EDMREQ;
-	union {
-		unsigned char BYTE;
-		struct {
-		
-			unsigned char ESIF:1;
-			unsigned char  :3;
-			unsigned char DTIF:1;
-			unsigned char  :2;
-			unsigned char ACT:1;
-		} BIT;
-	} EDMSTS;
-	char           wk2[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DREQS:2;
-			unsigned char  :6;
-		} BIT;
-	} EDMRMD;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char EREQ:1;
-			unsigned char  :7;
-		} BIT;
-	} EDMERF;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char PREQ:1;
-			unsigned char  :7;
-		} BIT;
-	} EDMPRF;
-};
-
-struct st_flash {
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char FLWE:2;
-			unsigned char  :6;
-		} BIT;
-	} FWEPROR;
-	char           wk1[7799160];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char FRDMD:1;
-			unsigned char  :3;
-		} BIT;
-	} FMODR;
-	char           wk2[13];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DFLWPE:1;
-			unsigned char DFLRPE:1;
-			unsigned char  :1;
-			unsigned char DFLAE:1;
-			unsigned char CMDLK:1;
-			unsigned char  :2;
-			unsigned char ROMAE:1;
-		} BIT;
-	} FASTAT;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DFLWPEIE:1;
-			unsigned char DFLRPEIE:1;
-			unsigned char  :1;
-			unsigned char DFLAEIE:1;
-			unsigned char CMDLKIE:1;
-			unsigned char  :2;
-			unsigned char ROMAEIE:1;
-		} BIT;
-	} FAEINT;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char FRDYIE:1;
-			unsigned char  :7;
-		} BIT;
-	} FRDYIE;
-	char           wk3[45];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short DBRE00:1;
-			unsigned short DBRE01:1;
-			unsigned short DBRE02:1;
-			unsigned short DBRE03:1;
-			unsigned short DBRE04:1;
-			unsigned short DBRE05:1;
-			unsigned short DBRE06:1;
-			unsigned short DBRE07:1;
-			unsigned short KEY:8;
-		} BIT;
-*/
-	} DFLRE0;
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short DBRE08:1;
-			unsigned short DBRE09:1;
-			unsigned short DBRE10:1;
-			unsigned short DBRE11:1;
-			unsigned short DBRE12:1;
-			unsigned short DBRE13:1;
-			unsigned short DBRE14:1;
-			unsigned short DBRE15:1;
-			unsigned short KEY:8;
-		} BIT;
-*/
-	} DFLRE1;
-	char           wk4[12];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short DBWE00:1;
-			unsigned short DBWE01:1;
-			unsigned short DBWE02:1;
-			unsigned short DBWE03:1;
-			unsigned short DBWE04:1;
-			unsigned short DBWE05:1;
-			unsigned short DBWE06:1;
-			unsigned short DBWE07:1;
-			unsigned short KEY:8;
-		} BIT;
-*/
-	} DFLWE0;
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short DBWE08:1;
-			unsigned short DBWE09:1;
-			unsigned short DBWE10:1;
-			unsigned short DBWE11:1;
-			unsigned short DBWE12:1;
-			unsigned short DBWE13:1;
-			unsigned short DBWE14:1;
-			unsigned short DBWE15:1;
-			unsigned short KEY:8;
-		} BIT;
-*/
-	} DFLWE1;
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short FCRME:1;
-			unsigned short  :7;
-			unsigned short KEY:8;
-		
-		} BIT;
-*/
-	} FCURAME;
-	char           wk5[15194];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char PRGSPD:1;
-			unsigned char ERSSPD:1;
-			unsigned char  :1;
-			unsigned char SUSRDY:1;
-			unsigned char PRGERR:1;
-			unsigned char ERSERR:1;
-			unsigned char ILGLERR:1;
-			unsigned char FRDY:1;
-		} BIT;
-	} FSTATR0;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :4;
-			unsigned char FLOCKST:1;
-			unsigned char :2;
-			unsigned char FCUERR:1;
-		} BIT;
-	} FSTATR1;
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short FENTRY0:1;
-			unsigned short  :6;
-			unsigned short FENTRYD:1;
-			unsigned short FEKEY:8;
-		} BIT;
-*/
-	} FENTRYR;
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short FPROTCN:1;
-			unsigned short  :7;
-			unsigned short FPKEY:8;
-		} BIT;
-*/
-	} FPROTR;
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short FRESET:1;
-			unsigned short  :7;
-			unsigned short FPKEY:8;
-		} BIT;
-*/
-	} FRESETR;
-	char           wk6[2];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short PCMDR:8;
-			unsigned short CMDR:8;
-		} BIT;
-*/
-	} FCMDR;
-	char           wk7[12];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short ESUSPMD:1;
-			unsigned short  :15;
-		} BIT;
-	} FCPSR;
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short BCSIZE:1;
-			unsigned short  :2;
-			unsigned short BCADR:8;
-			unsigned short  :5;
-		} BIT;
-*/
-	} DFLBCCNT;
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short PEERRST:8;
-			unsigned short  :8;
-		} BIT;
-*/
-	} FPESTAT;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short BCST:1;
-			unsigned short  :15;
-		} BIT;
-	} DFLBCSTAT;
-	char           wk8[24];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short PCKA:8;
-			unsigned short  :8;
-		} BIT;
-*/
-	} PCKAR;
-};
-
-struct st_icu {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IR:1;
-			unsigned char  :7;
-		} BIT;
-	} IR[255];
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DTCE:1;
-			unsigned char  :7;
-		} BIT;
-	} DTCER[255];
-	char           wk1[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IEN0:1;
-			unsigned char IEN1:1;
-			unsigned char IEN2:1;
-			unsigned char IEN3:1;
-			unsigned char IEN4:1;
-			unsigned char IEN5:1;
-			unsigned char IEN6:1;
-			unsigned char IEN7:1;
-		} BIT;
-	} IER[32];
-	char           wk2[192];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SWINT:1;
-			unsigned char  :7;
-		} BIT;
-	} SWINTR;
-	char           wk3[15];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short FVCT:8;
-			unsigned short  :7;
-			unsigned short FIEN:1;
-		} BIT;
-*/
-	} FIR;
-	char           wk4[14];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IPR:4;
-			unsigned char  :4;
-		} BIT;
-	} IPR[144];
-	char           wk5[112];
-	unsigned char  DMRSR0;
-	char           wk6[3];
-	unsigned char  DMRSR1;
-	char           wk7[3];
-	unsigned char  DMRSR2;
-	char           wk8[3];
-	unsigned char  DMRSR3;
-	char           wk9[243];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IRQMD:2;
-			unsigned char  :4;
-		} BIT;
-	} IRQCR[16];
-	char           wk10[112];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NMIST:1;
-			unsigned char LVDST:1;
-			unsigned char OSTST:1;
-			unsigned char  :5;
-		} BIT;
-	} NMISR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NMIEN:1;
-			unsigned char LVDEN:1;
-			unsigned char OSTEN:1;
-			unsigned char :5;
-		} BIT;
-	} NMIER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NMICLR:1;
-			unsigned char  :1;
-			unsigned char OSTCLR:1;
-			unsigned char  :5;
-		} BIT;
-	} NMICLR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :3;
-			unsigned char NMIMD:1;
-			unsigned char  :4;
-		} BIT;
-	} NMICR;
-};
-
-struct st_ioport {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CS0E:1;
-			unsigned char CS1E:1;
-			unsigned char CS2E:1;
-			unsigned char CS3E:1;
-			unsigned char CS4E:1;
-			unsigned char CS5E:1;
-			unsigned char CS6E:1;
-			unsigned char CS7E:1;
-		} BIT;
-	} PF0CSE;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CS4S:2;
-			unsigned char CS5S:2;
-			unsigned char CS6S:2;
-			unsigned char CS7S:2;
-		} BIT;
-	} PF1CSS;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CS0S:1;
-			unsigned char  :1;
-			unsigned char CS1S:2;
-			unsigned char CS2S:2;
-			unsigned char CS3S:2;
-		} BIT;
-	} PF2CSS;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char A16E:1;
-			unsigned char A17E:1;
-			unsigned char A18E:1;
-			unsigned char A19E:1;
-			unsigned char A20E:1;
-			unsigned char A21E:1;
-			unsigned char A22E:1;
-			unsigned char A23E:1;
-		} BIT;
-	} PF3BUS;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ADRLE:2;
-			unsigned char A10E:1;
-			unsigned char A11E:1;
-			unsigned char A12E:1;
-			unsigned char A13E:1;
-			unsigned char A14E:1;
-			unsigned char A15E:1;
-		} BIT;
-	} PF4BUS;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ADRHMS:1;
-			unsigned char  :2;
-			unsigned char DHE:1;
-			unsigned char DH32E:1;
-			unsigned char WR1BC1E:1;
-			unsigned char WR32BC32E:1;
-		} BIT;
-	} PF5BUS;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char WAITS:2;
-			unsigned char  :2;
-			unsigned char MDSDE:1;
-			unsigned char  :1;
-			unsigned char DQM1E:1;
-			unsigned char SDCLKE:1;
-		} BIT;
-	} PF6BUS;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :4;
-			unsigned char EDMA0S:2;
-			unsigned char EDMA1S:2;
-		} BIT;
-	} PF7DMA;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ITS8:1;
-			unsigned char ITS9:1;
-			unsigned char ITS10:1;
-			unsigned char ITS11:1;
-			unsigned char  :1;
-			unsigned char ITS13:1;
-			unsigned char  :1;
-			unsigned char ITS15:1;
-		} BIT;
-	} PF8IRQ;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ITS0:1;
-			unsigned char ITS1:1;
-			unsigned char ITS2:1;
-			unsigned char ITS3:1;
-			unsigned char ITS4:1;
-			unsigned char ITS5:1;
-			unsigned char ITS6:1;
-			unsigned char ITS7:1;
-		} BIT;
-	} PF9IRQ;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ADTRG0S:1;
-			unsigned char :7;
-		} BIT;
-	} PFAADC;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TMR0S:1;
-			unsigned char TMR1S:1;
-			unsigned char TMR2S:1;
-			unsigned char TMR3S:1;
-			unsigned char  :4;
-		} BIT;
-	} PFBTMR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MTUS0:1;
-			unsigned char MTUS1:1;
-			unsigned char MTUS2:1;
-			unsigned char MTUS3:1;
-			unsigned char MTUS4:1;
-			unsigned char MTUS5:1;
-			unsigned char MTUS6:1;
-			unsigned char TCLKS:1;
-		} BIT;
-	} PFCMTU;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :6;
-			unsigned char TCLKS:1;
-			unsigned char MTUS6:1;
-		} BIT;
-	} PFDMTU;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ENETE0:1;
-			unsigned char ENETE1:1;
-			unsigned char ENETE2:1;
-			unsigned char ENETE3:1;
-			unsigned char PHYMODE:1;
-			unsigned char  :2;
-			unsigned char EE:1;
-		} BIT;
-	} PFENET;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :1;
-			unsigned char SCI1S:1;
-			unsigned char SCI2S:1;
-			unsigned char SCI3S:1;
-			unsigned char  :2;
-			unsigned char SCI6S:1;
-			unsigned char  :1;
-		} BIT;
-	} PFFSCI;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char RSPIS:1;
-			unsigned char RSPCKE:1;
-			unsigned char MOSIE:1;
-			unsigned char MISOE:1;
-			unsigned char SSL0E:1;
-			unsigned char SSL1E:1;
-			unsigned char SSL2E:1;
-			unsigned char SSL3E:1;
-		} BIT;
-	} PFGSPI;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char RSPIS:1;
-			unsigned char RSPCKE:1;
-			unsigned char MOSIE:1;
-			unsigned char MISOE:1;
-			unsigned char SSL0E:1;
-			unsigned char SSL1E:1;
-			unsigned char SSL2E:1;
-			unsigned char SSL3E:1;
-		} BIT;
-	} PFHSPI;
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CAN0E:1;
-			unsigned char  :7;
-		} BIT;
-	} PFJCAN;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char USBMD:2;
-			unsigned char PUPHZS:1;
-			unsigned char PDHZS:1;
-			unsigned char USBE:1;
-			unsigned char  :3;
-		} BIT;
-	} PFKUSB;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char USBMD:2;
-			unsigned char PUPHZS:1;
-			unsigned char PDHZS:1;
-			unsigned char USBE:1;
-			unsigned char  :3;
-		} BIT;
-	} PFLUSB;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char POE0E:1;
-			unsigned char POE1E:1;
-			unsigned char POE2E:1;
-			unsigned char POE3E:1;
-			unsigned char POE4E:1;
-			unsigned char POE5E:1;
-			unsigned char POE6E:1;
-			unsigned char POE7E:1;	
-		} BIT;
-	} PFMPOE;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char POE8E:1;
-			unsigned char POE9E:1;
-			unsigned char  :6;
-		} BIT;
-	} PFNPOE;
-};
-
-struct st_iwdt {
-	unsigned char  IWDTRR;
-	char           wk0[1];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short TOPS:2;
-			unsigned short  :2;
-			unsigned short CKS:4;
-			unsigned short  :8;
-		} BIT;
-	} IWDTCR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CNTVAL:14;
-			unsigned short UNDFF:1;
-			unsigned short  :1;
-		} BIT;
-	} IWDTSR;
-};
-
-struct st_mtu0 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TPSC:3;
-			unsigned char CKEG:2;
-			unsigned char CCLR:3;
-		} BIT;
-	} TCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MD:4;
-			unsigned char BFA:1;
-			unsigned char BFB:1;
-			unsigned char BFE:1;
-			unsigned char  :1;
-		} BIT;
-	} TMDR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOA:4;
-			unsigned char IOB:4;
-		} BIT;
-	} TIORH;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOC:4;
-			unsigned char IOD:4;
-		} BIT;
-	} TIORL;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TGIEA:1;
-			unsigned char TGIEB:1;
-			unsigned char TGIEC:1;
-			unsigned char TGIED:1;
-			unsigned char TCIEV:1;
-			unsigned char  :2;
-			unsigned char TTGE:1;
-		} BIT;
-	} TIER;
-	unsigned char  TSR;
-	unsigned short TCNT;
-	unsigned short TGRA;
-	unsigned short TGRB;
-	unsigned short TGRC;
-	unsigned short TGRD;
-	char           wk0[16];
-	unsigned short TGRE;
-	unsigned short TGRF;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TGIEE:1;
-			unsigned char TGIEF:1;
-			unsigned char  :6;
-		} BIT;
-	} TIER2;
-	char           wk1[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TTSA:1;
-			unsigned char TTSB:1;
-			unsigned char TTSE:1;
-			unsigned char  :5;
-		} BIT;
-	} TBTM;
-};
-
-struct st_mtu1 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TPSC:3;
-			unsigned char CKEG:2;
-			unsigned char CCLR:2;
-			unsigned char  :1;
-		} BIT;
-	} TCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MD:4;
-			unsigned char  :4;
-		} BIT;
-	} TMDR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOA:4;
-			unsigned char IOB:4;
-		} BIT;
-	} TIOR;
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TGIEA:1;
-			unsigned char TGIEB:1;
-			unsigned char  :2;
-			unsigned char TCIEV:1;
-			unsigned char TCIEU:1;
-			unsigned char  :1;
-			unsigned char TTGE:1;
-		} BIT;
-	} TIER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :7;
-			unsigned char TCFD:1;
-		} BIT;
-	} TSR;
-	unsigned short TCNT;
-	unsigned short TGRA;
-	unsigned short TGRB;
-	char           wk1[4];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char I1AE:1;
-			unsigned char I1BE:1;
-			unsigned char I2AE:1;
-			unsigned char I2BE:1;
-			unsigned char  :4;
-		} BIT;
-	} TICCR;
-};
-
-struct st_mtu2 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TPSC:3;
-			unsigned char CKEG:2;
-			unsigned char CCLR:2;
-			unsigned char  :1;
-		} BIT;
-	} TCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MD:4;
-			unsigned char  :4;
-		} BIT;
-	} TMDR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOA:4;
-			unsigned char IOB:4;
-		} BIT;
-	} TIOR;
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TGIEA:1;
-			unsigned char TGIEB:1;
-			unsigned char  :2;
-			unsigned char TCIEV:1;
-			unsigned char TCIEU:1;
-			unsigned char  :1;
-			unsigned char TTGE:1;	
-		} BIT;
-	} TIER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :7;
-			unsigned char TCFD:1;
-		} BIT;
-	} TSR;
-	unsigned short TCNT;
-	unsigned short TGRA;
-	unsigned short TGRB;
-};
-
-struct st_mtu3 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TPSC:3;
-			unsigned char CKEG:2;
-			unsigned char CCLR:3;
-		} BIT;
-	} TCR;
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MD:4;
-			unsigned char BFA:1;
-			unsigned char BFB:1;
-			unsigned char  :2;
-		} BIT;
-	} TMDR;
-	char           wk1[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOA:4;
-			unsigned char IOB:4;
-		} BIT;
-	} TIORH;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOC:4;
-			unsigned char IOD:4;
-		} BIT;
-	} TIORL;
-	char           wk2[2];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TGIEA:1;
-			unsigned char TGIEB:1;
-			unsigned char TGIEC:1;
-			unsigned char TGIED:1;
-			unsigned char TCIEV:1;
-			unsigned char :2;
-			unsigned char TTGE:1;
-		} BIT;
-	} TIER;
-	char           wk3[7];
-	unsigned short TCNT;
-	char           wk4[6];
-	unsigned short TGRA;
-	unsigned short TGRB;
-	char           wk5[8];
-	unsigned short TGRC;
-	unsigned short TGRD;
-	char           wk6[4];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :7;
-			unsigned char TCFD:1;
-		} BIT;
-	} TSR;
-	char           wk7[11];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TTSA:1;
-			unsigned char TTSB:1;
-			unsigned char  :6;
-		} BIT;
-	} TBTM;
-};
-
-struct st_mtu4 {
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TPSC:3;
-			unsigned char CKEG:2;
-			unsigned char CCLR:3;
-		} BIT;
-	} TCR;
-	char           wk1[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MD:4;
-			unsigned char BFA:1;
-			unsigned char BFB:1;
-			unsigned char  :2;
-		} BIT;
-	} TMDR;
-	char           wk2[2];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOA:4;
-			unsigned char IOB:4;
-		} BIT;
-	} TIORH;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOC:4;
-			unsigned char IOD:4;
-		} BIT;
-	} TIORL;
-	char           wk3[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TGIEA:1;
-			unsigned char TGIEB:1;
-			unsigned char TGIEC:1;
-			unsigned char TGIED:1;
-			unsigned char TCIEV:1;
-			unsigned char  :1;
-			unsigned char TTGE2:1;
-			unsigned char TTGE:1;
-		} BIT;
-	} TIER;
-	char           wk4[8];
-	unsigned short TCNT;
-	char           wk5[8];
-	unsigned short TGRA;
-	unsigned short TGRB;
-	char           wk6[8];
-	unsigned short TGRC;
-	unsigned short TGRD;
-	char           wk7[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :7;
-			unsigned char TCFD:1;
-		} BIT;
-	} TSR;
-	char           wk8[11];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TTSA:1;
-			unsigned char TTSB:1;
-			unsigned char  :6;
-		} BIT;
-	} TBTM;
-	char           wk9[6];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short ITB4VE:1;
-			unsigned short ITB3AE:1;
-			unsigned short ITA4VE:1;
-			unsigned short ITA3AE:1;
-			unsigned short DT4BE:1;
-			unsigned short UT4BE:1;
-			unsigned short DT4AE:1;
-			unsigned short UT4AE:1;
-			unsigned short  :6;
-			unsigned short BF:2;
-		} BIT;
-	} TADCR;
-	char           wk10[2];
-	unsigned short TADCORA;
-	unsigned short TADCORB;
-	unsigned short TADCOBRA;
-	unsigned short TADCOBRB;
-};
-
-struct st_mtu5 {
-	unsigned short TCNTU;
-	unsigned short TGRU;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TPSC:2;
-			unsigned char  :6;
-		} BIT;
-	} TCRU;
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOC:5;
-			unsigned char  :3;
-		} BIT;
-	} TIORU;
-	char           wk1[9];
-	unsigned short TCNTV;
-	unsigned short TGRV;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TPSC:2;
-			unsigned char  :6;
-		} BIT;
-	} TCRV;
-	char           wk2[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOC:5;
-			unsigned char  :3;
-		} BIT;
-	} TIORV;
-	char           wk3[9];
-	unsigned short TCNTW;
-	unsigned short TGRW;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TPSC:2;
-			unsigned char  :6;
-		} BIT;
-	} TCRW;
-	char           wk4[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char IOC:5;
-			unsigned char  :3;
-		} BIT;
-	} TIORW;
-	char           wk5[11];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TGIE5W:1;
-			unsigned char TGIE5V:1;
-			unsigned char TGIE5U:1;
-			unsigned char  :5;
-		} BIT;
-	} TIER;
-	char           wk6[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CSTW5:1;
-			unsigned char CSTV5:1;
-			unsigned char CSTU5:1;
-			unsigned char  :5;
-		} BIT;
-	} TSTR;
-	char           wk7[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CMPCLR5W:1;
-			unsigned char CMPCLR5V:1;
-			unsigned char CMPCLR5U:1;
-			unsigned char  :5;
-		} BIT;
-	} TCNTCMPCLR;
-};
-
-struct st_mtua {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char OE3B:1;
-			unsigned char OE4A:1;
-			unsigned char OE4B:1;
-			unsigned char OE3D:1;
-			unsigned char OE4C:1;
-			unsigned char OE4D:1;
-			unsigned char  :2;
-		} BIT;
-	} TOER;
-	char           wk0[2];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char UF:1;
-			unsigned char VF:1;
-			unsigned char WF:1;
-			unsigned char FB:1;
-			unsigned char P:1;
-			unsigned char N:1;
-			unsigned char BDC:1;
-			unsigned char  :1;
-		} BIT;
-	} TGCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char OLSP:1;
-			unsigned char OLSN:1;
-			unsigned char TOCS:1;
-			unsigned char TOCL:1;
-			unsigned char  :2;
-			unsigned char PSYE:1;
-			unsigned char  :1;
-		} BIT;
-	} TOCR1;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char OLS1P:1;
-			unsigned char OLS1N:1;
-			unsigned char OLS2P:1;
-			unsigned char OLS2N:1;
-			unsigned char OLS3N:1;
-			unsigned char OLS3P:1;
-			unsigned char BF:2;
-		} BIT;
-	} TOCR2;
-	char           wk1[4];
-	unsigned short TCDR;
-	unsigned short TDDR;
-	char           wk2[8];
-	unsigned short TCNTS;
-	unsigned short TCBR;
-	char           wk3[12];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char T4VCOR:3;
-			unsigned char T4VEN:1;
-			unsigned char T3ACOR:3;
-			unsigned char T3AEN:1;
-		} BIT;
-	} TITCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char T4VCNT:3;
-			unsigned char  :1;
-			unsigned char T3ACNT:3;
-			unsigned char  :1;
-		} BIT;
-	} TITCNT;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char BTE:2;
-			unsigned char  :6;
-		} BIT;
-	} TBTER;
-	char           wk4[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TDER:1;
-			unsigned char  :7;
-		} BIT;
-	} TDER;
-	char           wk5[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char OLS1P:1;
-			unsigned char OLS1N:1;
-			unsigned char OLS2P:1;
-			unsigned char OLS2N:1;
-			unsigned char OLS3P:1;
-			unsigned char OLS3N:1;
-			unsigned char  :2;
-		} BIT;
-	} TOLBR;
-	char           wk6[41];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char WRE:1;
-			unsigned char  :6;
-			unsigned char CCE:1;
-		} BIT;
-	} TWCR;
-	char           wk7[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CST0:1;
-			unsigned char CST1:1;
-			unsigned char CST2:1;
-			unsigned char  :3;
-			unsigned char CST3:1;
-			unsigned char CST4:1;
-		} BIT;
-	} TSTR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SYNC0:1;
-			unsigned char SYNC1:1;
-			unsigned char SYNC2:1;
-			unsigned char  :3;
-			unsigned char SYNC3:1;
-			unsigned char SYNC4:1;
-		} BIT;
-	} TSYR;
-	char           wk8[2];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char RWE:1;
-			unsigned char  :7;
-		} BIT;
-	} TRWER;
-};
-
-struct st_poe {
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short POE0M:2;
-			unsigned short POE1M:2;
-			unsigned short POE2M:2;
-			unsigned short POE3M:2;
-			unsigned short PIE1:1;
-			unsigned short  :3;
-			unsigned short POE0F:1;
-			unsigned short POE1F:1;
-			unsigned short POE2F:1;
-			unsigned short POE3F:1;
-		} BIT;
-	} ICSR1;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :8;
-			unsigned short OIE1:1;
-			unsigned short OCE1:1;
-			unsigned short  :5;
-			unsigned short :5;
-			unsigned short OSF1:1;
-		} BIT;
-	} OCSR1;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short POE4M:2;
-			unsigned short POE5M:2;
-			unsigned short POE6M:2;
-			unsigned short POE7M:2;
-			unsigned short PIE2:1;
-			unsigned short  :3;
-			unsigned short POE4F:1;
-			unsigned short POE5F:1;
-			unsigned short POE6F:1;
-			unsigned short POE7F:1;
-		} BIT;
-	} ICSR2;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :8;
-			unsigned short OIE2:1;
-			unsigned short OCE2:1;
-			unsigned short  :5;
-			unsigned short OSF2:1;
-		} BIT;
-	} OCSR2;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short POE8M:2;
-			unsigned short  :6;
-			unsigned short PIE3:1;
-			unsigned short POE8E:1;
-			unsigned short  :2;
-			unsigned short POE8F:1;
-			unsigned short  :3;
-		} BIT;
-	} ICSR3;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CH34HIZ:1;
-			unsigned char CH0HIZ:1;
-			unsigned char CH910HIZ:1;
-			unsigned char CH6HIZ:1;
-			unsigned char  :4;
-		} BIT;
-	} SPOER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char PE0ZE:1;
-			unsigned char PE1ZE:1;
-			unsigned char PE2ZE:1;
-			unsigned char PE3ZE:1;
-			unsigned char PE4ZE:1;
-			unsigned char PE5ZE:1;
-			unsigned char PE6ZE:1;
-			unsigned char PE7ZE:1;
-		} BIT;
-	} POECR1;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :4;
-			unsigned short P6CZE:1;
-			unsigned short P5CZE:1;
-			unsigned short P4CZE:1;
-			unsigned short  :1;
-			unsigned short P3CZEB:1;
-			unsigned short P2CZEB:1;
-			unsigned short P1CZEB:1;
-			unsigned short  :1;
-			unsigned short P3CZEA:1;
-			unsigned short P2CZEA:1;
-			unsigned short P1CZEA:1;
-			unsigned short  :1;
-
-		} BIT;
-	} POECR2;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short POE9M:2;
-			unsigned short  :6;
-			unsigned short PIE4:1;
-			unsigned short POE9E:1;
-			unsigned short  :2;
-			unsigned short POE9F:1;
-			unsigned short  :3;
-		} BIT;
-	} ICSR4;
-};
-
-struct st_port0 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char  :1;
-			unsigned char B5:1;
-			unsigned char  :1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char  :1;
-			unsigned char B5:1;
-			unsigned char  :1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char  :1;
-			unsigned char B5:1;
-			unsigned char  :1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char  :1;
-			unsigned char B5:1;
-			unsigned char  :1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B7:1;
-			unsigned char  :1;
-			unsigned char B5:1;
-			unsigned char  :1;
-			unsigned char B3:1;
-			unsigned char B2:1;
-			unsigned char B1:1;
-			unsigned char B0:1;
-		} BIT;
-	} ODR;
-};
-
-struct st_port1 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ODR;
-};
-
-struct st_port2 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ODR;
-};
-
-struct st_port3 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char  :3;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char  :3;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char  :2;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char  :3;
-		} BIT;
-	} ICR;
-	char           wk3[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char  :3;
-		} BIT;
-	} ODR;
-};
-
-struct st_port4 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-};
-
-struct st_port5 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-};
-
-struct st_port6 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-};
-
-struct st_port7 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-};
-
-struct st_port8 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char  :2;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char  :2;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char  :2;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char  :2;
-		} BIT;
-	} ICR;
-};
-
-struct st_port9 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[95];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PCR;
-};
-
-struct st_porta {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[95];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PCR;
-};
-
-struct st_portb {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[95];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PCR;
-};
-
-struct st_portc {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ODR;
-	char           wk4[63];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PCR;
-};
-
-struct st_portd {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[95];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PCR;
-};
-
-struct st_porte {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[95];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PCR;
-};
-
-struct st_portf {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char :3;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char :3;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char :3;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char :3;
-		} BIT;
-	} ICR;
-};
-
-struct st_portg {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DDR;
-	char           wk0[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} DR;
-	char           wk1[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PORT;
-	char           wk2[31];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} ICR;
-	char           wk3[95];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char B0:1;
-			unsigned char B1:1;
-			unsigned char B2:1;
-			unsigned char B3:1;
-			unsigned char B4:1;
-			unsigned char B5:1;
-			unsigned char B6:1;
-			unsigned char B7:1;
-		} BIT;
-	} PCR;
-};
-
-struct st_ppg0 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char G0CMS:2;
-			unsigned char G1CMS:2;
-			unsigned char G2CMS:2;
-			unsigned char G3CMS:2;
-		} BIT;
-	} PCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char G0NOV:1;
-			unsigned char G1NOV:1;
-			unsigned char G2NOV:1;
-			unsigned char G3NOV:1;
-			unsigned char G0INV:1;
-			unsigned char G1INV:1;
-			unsigned char G2INV:1;
-			unsigned char G3INV:1;
-		} BIT;
-	} PMR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDER8:1;
-			unsigned char NDER9:1;
-			unsigned char NDER10:1;
-			unsigned char NDER11:1;
-			unsigned char NDER12:1;
-			unsigned char NDER13:1;
-			unsigned char NDER14:1;
-			unsigned char NDER15:1;
-		} BIT;
-	} NDERH;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDER0:1;
-			unsigned char NDER1:1;
-			unsigned char NDER2:1;
-			unsigned char NDER3:1;
-			unsigned char NDER4:1;
-			unsigned char NDER5:1;
-			unsigned char NDER6:1;
-			unsigned char NDER7:1;
-		} BIT;
-	} NDERL;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char POD8:1;
-			unsigned char POD9:1;
-			unsigned char POD10:1;
-			unsigned char POD11:1;
-			unsigned char POD12:1;
-			unsigned char POD13:1;
-			unsigned char POD14:1;
-			unsigned char POD15:1;
-		} BIT;
-	} PODRH;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char POD0:1;
-			unsigned char POD1:1;
-			unsigned char POD2:1;
-			unsigned char POD3:1;
-			unsigned char POD4:1;
-			unsigned char POD5:1;
-			unsigned char POD6:1;
-			unsigned char POD7:1;
-		} BIT;
-	} PODRL;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDR8:1;
-			unsigned char NDR9:1;
-			unsigned char NDR10:1;
-			unsigned char NDR11:1;
-			unsigned char NDR12:1;
-			unsigned char NDR13:1;
-			unsigned char NDR14:1;
-			unsigned char NDR15:1;
-		} BIT;
-	} NDRH;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDR0:1;
-			unsigned char NDR1:1;
-			unsigned char NDR2:1;
-			unsigned char NDR3:1;
-			unsigned char NDR4:1;
-			unsigned char NDR5:1;
-			unsigned char NDR6:1;
-			unsigned char NDR7:1;
-		} BIT;
-	} NDRL;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDR8:1;
-			unsigned char NDR9:1;
-			unsigned char NDR10:1;
-			unsigned char NDR11:1;
-			unsigned char  :4;
-		} BIT;
-	} NDRH2;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDR0:1;
-			unsigned char NDR1:1;
-			unsigned char NDR2:1;
-			unsigned char NDR3:1;
-			unsigned char  :4;
-		} BIT;
-	} NDRL2;
-};
-
-struct st_ppg1 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char PTRSL:1;
-			unsigned char  :7;
-		} BIT;
-	} PTRSLR;
-	char           wk0[5];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char G0CMS:2;
-			unsigned char G1CMS:2;
-			unsigned char G2CMS:2;
-			unsigned char G3CMS:2;
-		} BIT;
-	} PCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char G0NOV:1;
-			unsigned char G1NOV:1;
-			unsigned char G2NOV:1;
-			unsigned char G3NOV:1;
-			unsigned char G0INV:1;
-			unsigned char G1INV:1;
-			unsigned char G2INV:1;
-			unsigned char G3INV:1;
-		} BIT;
-	} PMR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDER24:1;
-			unsigned char NDER25:1;
-			unsigned char NDER26:1;
-			unsigned char NDER27:1;
-			unsigned char NDER28:1;
-			unsigned char NDER29:1;
-			unsigned char NDER30:1;
-			unsigned char NDER31:1;
-		} BIT;
-	} NDERH;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDER16:1;
-			unsigned char NDER17:1;
-			unsigned char NDER18:1;
-			unsigned char NDER19:1;
-			unsigned char NDER20:1;
-			unsigned char NDER21:1;
-			unsigned char NDER22:1;
-			unsigned char NDER23:1;
-		} BIT;
-	} NDERL;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char POD24:1;
-			unsigned char POD25:1;
-			unsigned char POD26:1;
-			unsigned char POD27:1;
-			unsigned char POD28:1;
-			unsigned char POD29:1;
-			unsigned char POD30:1;
-			unsigned char POD31:1;
-		} BIT;
-	} PODRH;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char POD16:1;
-			unsigned char POD17:1;
-			unsigned char POD18:1;
-			unsigned char POD19:1;
-			unsigned char POD20:1;
-			unsigned char POD21:1;
-			unsigned char POD22:1;
-			unsigned char POD23:1;
-		} BIT;
-	} PODRL;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDR24:1;
-			unsigned char NDR25:1;
-			unsigned char NDR26:1;
-			unsigned char NDR27:1;
-			unsigned char NDR28:1;
-			unsigned char NDR29:1;
-			unsigned char NDR30:1;
-			unsigned char NDR31:1;
-		} BIT;
-	} NDRH;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDR16:1;
-			unsigned char NDR17:1;
-			unsigned char NDR18:1;
-			unsigned char NDR19:1;
-			unsigned char NDR20:1;
-			unsigned char NDR21:1;
-			unsigned char NDR22:1;
-			unsigned char NDR23:1;
-		} BIT;
-	} NDRL;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDR24:1;
-			unsigned char NDR25:1;
-			unsigned char NDR26:1;
-			unsigned char NDR27:1;
-			unsigned char :4;
-		} BIT;
-	} NDRH2;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NDR16:1;
-			unsigned char NDR17:1;
-			unsigned char NDR18:1;
-			unsigned char NDR19:1;
-			unsigned char :4;
-		} BIT;
-	} NDRL2;
-};
-
-struct st_riic {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SDAI:1;
-			unsigned char SCLI:1;
-			unsigned char SDAO:1;
-			unsigned char SCLO:1;
-			unsigned char SOWP:1;
-			unsigned char CLO:1;
-			unsigned char IICRST:1;
-			unsigned char ICE:1;
-		} BIT;
-	} ICCR1;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ST:1;
-			unsigned char RS:1;
-			unsigned char SP:1;
-			unsigned char  :1;
-			unsigned char TRS:1;
-			unsigned char MST:1;
-			unsigned char BBSY:1;
-		} BIT;
-	} ICCR2;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char BC:3;
-			unsigned char BCWP:1;
-			unsigned char CKS:3;
-			unsigned char MTWP:1;
-		} BIT;
-	} ICMR1;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TMOS:1;
-			unsigned char TMOL:1;
-			unsigned char TMOH:1;
-			unsigned char  :1;
-			unsigned char SDDL:3;
-			unsigned char DLCS:1;
-		} BIT;
-	} ICMR2;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char NF:2;
-			unsigned char ACKBR:1;
-			unsigned char ACKBT:1;
-			unsigned char ACKWP:1;
-			unsigned char RDRFS:1;
-			unsigned char WAIT:1;
-			unsigned char SMBS:1;
-		} BIT;
-	} ICMR3;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TMOE:1;
-			unsigned char MALE:1;
-			unsigned char NALE:1;
-			unsigned char SALE:1;
-			unsigned char NACKE:1;
-			unsigned char NFE:1;
-			unsigned char SCLE:1;
-			unsigned char FMPE:1;
-		} BIT;
-	} ICFER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SAR0E:1;
-			unsigned char SAR1E:1;
-			unsigned char SAR2E:1;
-			unsigned char GCAE:1;
-			unsigned char  :1;
-			unsigned char DIDE:1;
-			unsigned char  :1;
-			unsigned char HOAE:1;
-		} BIT;
-	} ICSER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TMOIE:1;
-			unsigned char ALIE:1;
-			unsigned char STIE:1;
-			unsigned char SPIE:1;
-			unsigned char NAKIE:1;
-			unsigned char RIE:1;
-			unsigned char TEIE:1;
-			unsigned char TIE:1;
-		} BIT;
-	} ICIER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char AAS0:1;
-			unsigned char AAS1:1;
-			unsigned char AAS2:1;
-			unsigned char GCA:1;
-			unsigned char  :1;
-			unsigned char DID:1;
-			unsigned char  :1;
-			unsigned char HOA:1;
-		} BIT;
-	} ICSR1;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char TMOF:1;
-			unsigned char AL:1;
-			unsigned char START:1;
-			unsigned char STOP:1;
-			unsigned char NACKF:1;
-			unsigned char RDRF:1;
-			unsigned char TEND:1;
-			unsigned char TDRE:1;
-		} BIT;
-	} ICSR2;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SVA0:1;
-			unsigned char SVA:7;
-		} BIT;
-	} SARL0;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char FS:1;
-			unsigned char SVA:2;
-			unsigned char  :5;
-		} BIT;
-	} SARU0;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SVA0:1;
-			unsigned char SVA:7;
-		} BIT;
-	} SARL1;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char FS:1;
-			unsigned char SVA:2;
-			unsigned char  :5;
-		} BIT;
-	} SARU1;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SVA0:1;
-			unsigned char SVA:7;
-		} BIT;
-	} SARL2;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char FS:1;
-			unsigned char SVA:2;
-			unsigned char  :5;
-		} BIT;
-	} SARU2;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char BRL:5;
-			unsigned char  :3;
-		} BIT;
-	} ICBRL;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char BRH:5;
-			unsigned char  :3;
-		} BIT;
-	} ICBRH;
-	unsigned char  ICDRT;
-	unsigned char  ICDRR;
-};
-
-struct st_rspi {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SPMS:1;
-			unsigned char TXMD:1;
-			unsigned char MODFEN:1;
-			unsigned char MSTR:1;
-			unsigned char SPEIE:1;
-			unsigned char SPTIE:1;
-			unsigned char SPE:1;
-			unsigned char SPRIE:1;
-		} BIT;
-	} SPCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SSLP0:1;
-			unsigned char SSLP1:1;
-			unsigned char SSLP2:1;
-			unsigned char SSLP3:1;
-			unsigned char  :4;
-		} BIT;
-	} SSLP;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SPLP:1;
-			unsigned char SPLP2:1;
-			unsigned char SPOM:1;
-			unsigned char  :1;
-			unsigned char MOIFV:1;
-			unsigned char MOIFE:1;
-			unsigned char  :2;
-		} BIT;
-	} SPPCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char OVRF:1;
-			unsigned char IDLNF:1;
-			unsigned char MODF:1;
-			unsigned char PERF:1;
-			unsigned char  :1;
-			unsigned char SPTEF:1;
-			unsigned char  :1;
-			unsigned char SPRF:1;
-		} BIT;
-	} SPSR;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned short L;
-			unsigned short H;
-		} WORD;
-	} SPDR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SPSLN:3;
-			unsigned char  :5;
-		} BIT;
-	} SPSCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SPCP:3;
-			unsigned char  :1;
-			unsigned char SPECM:3;
-			unsigned char  :1;
-		} BIT;
-	} SPSSR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SPR0:1;
-			unsigned char SPR1:1;
-			unsigned char SPR2:1;
-			unsigned char SPR3:1;
-			unsigned char SPR4:1;
-			unsigned char SPR5:1;
-			unsigned char SPR6:1;
-			unsigned char SPR7:1;
-		} BIT;
-	} SPBR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SPFC:2;
-			unsigned char SLSEL:2;
-			unsigned char SPRDTD:1;
-			unsigned char SPLW:1;
-			unsigned char  :2;
-		} BIT;
-	} SPDCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SCKDL:3;
-			unsigned char  :5;
-		} BIT;
-	} SPCKD;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SLNDL:3;
-			unsigned char  :5;
-		} BIT;
-	} SSLND;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SPNDL:3;
-			unsigned char  :5;
-		} BIT;
-	} SPND;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SPPE:1;
-			unsigned char SPOE:1;
-			unsigned char SPIIE:1;
-			unsigned char PTE:1;
-			unsigned char  :4;
-		} BIT;
-	} SPCR2;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CPHA:1;
-			unsigned short CPOL:1;
-			unsigned short BRDV:2;
-			unsigned short SSLA:3;
-			unsigned short SSLKP:1;
-			unsigned short SPB:4;
-			unsigned short LSBF:1;
-			unsigned short SPNDEN:1;
-			unsigned short SLNDEN:1;
-			unsigned short SCKDEN:1;
-		} BIT;
-	} SPCMD0;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CPHA:1;
-			unsigned short CPOL:1;
-			unsigned short BRDV:2;
-			unsigned short SSLA:3;
-			unsigned short SSLKP:1;
-			unsigned short SPB:4;
-			unsigned short LSBF:1;
-			unsigned short SPNDEN:1;
-			unsigned short SLNDEN:1;
-			unsigned short SCKDEN:1;
-		} BIT;
-	} SPCMD1;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CPHA:1;
-			unsigned short CPOL:1;
-			unsigned short BRDV:2;
-			unsigned short SSLA:3;
-			unsigned short SSLKP:1;
-			unsigned short SPB:4;
-			unsigned short LSBF:1;
-			unsigned short SPNDEN:1;
-			unsigned short SLNDEN:1;
-			unsigned short SCKDEN:1;
-		} BIT;
-	} SPCMD2;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CPHA:1;
-			unsigned short CPOL:1;
-			unsigned short BRDV:2;
-			unsigned short SSLA:3;
-			unsigned short SSLKP:1;
-			unsigned short SPB:4;
-			unsigned short LSBF:1;
-			unsigned short SPNDEN:1;
-			unsigned short SLNDEN:1;
-			unsigned short SCKDEN:1;
-		} BIT;
-	} SPCMD3;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CPHA:1;
-			unsigned short CPOL:1;
-			unsigned short BRDV:2;
-			unsigned short SSLA:3;
-			unsigned short SSLKP:1;
-			unsigned short SPB:4;
-			unsigned short LSBF:1;
-			unsigned short SPNDEN:1;
-			unsigned short SLNDEN:1;
-			unsigned short SCKDEN:1;
-		} BIT;
-	} SPCMD4;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CPHA:1;
-			unsigned short CPOL:1;
-			unsigned short BRDV:2;
-			unsigned short SSLA:3;
-			unsigned short SSLKP:1;
-			unsigned short SPB:4;
-			unsigned short LSBF:1;
-			unsigned short SPNDEN:1;
-			unsigned short SLNDEN:1;
-			unsigned short SCKDEN:1;
-		} BIT;
-	} SPCMD5;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CPHA:1;
-			unsigned short CPOL:1;
-			unsigned short BRDV:2;
-			unsigned short SSLA:3;
-			unsigned short SSLKP:1;
-			unsigned short SPB:4;
-			unsigned short LSBF:1;
-			unsigned short SPNDEN:1;
-			unsigned short SLNDEN:1;
-			unsigned short SCKDEN:1;
-		} BIT;
-	} SPCMD6;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CPHA:1;
-			unsigned short CPOL:1;
-			unsigned short BRDV:2;
-			unsigned short SSLA:3;
-			unsigned short SSLKP:1;
-			unsigned short SPB:4;
-			unsigned short LSBF:1;
-			unsigned short SPNDEN:1;
-			unsigned short SLNDEN:1;
-			unsigned short SCKDEN:1;
-		} BIT;
-	} SPCMD7;
-};
-
-struct st_rtc {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char F1HZ:1;
-			unsigned char F2HZ:1;
-			unsigned char F4HZ:1;
-			unsigned char F8HZ:1;
-			unsigned char F16HZ:1;
-			unsigned char F32HZ:1;
-			unsigned char F64HZ:1;
-		} BIT;
-	} R64CNT;
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SEC1:4;
-			unsigned char SEC10:3;
-			unsigned char  :1;
-		} BIT;
-	} RSECCNT;
-	char           wk1[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MIN1:4;
-			unsigned char MIN10:3;
-			unsigned char  :1;
-		} BIT;
-	} RMINCNT;
-	char           wk2[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char HOUR1:4;
-			unsigned char HOUR10:2;
-			unsigned char  :2;
-		} BIT;
-	} RHRCNT;
-	char           wk3[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DAY:3;
-			unsigned char  :5;
-		} BIT;
-	} RWKCNT;
-	char           wk4[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DAY1:4;
-			unsigned char DAY10:2;
-			unsigned char  :2;
-		} BIT;
-	} RDAYCNT;
-	char           wk5[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MON1:4;
-			unsigned char MON10:1;
-			unsigned char  :3;
-		} BIT;
-	} RMONCNT;
-	char           wk6[1];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short YEAR1:4;
-			unsigned short YEAR10:4;
-			unsigned short YEAR100:4;
-			unsigned short YEAR1000:4;
-		} BIT;
-	} RYRCNT;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SEC1:4;
-			unsigned char SEC10:3;
-			unsigned char ENB:1;
-		} BIT;
-	} RSECAR;
-	char           wk7[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MIN1:4;
-			unsigned char MIN10:3;
-			unsigned char ENB:1;
-		} BIT;
-	} RMINAR;
-	char           wk8[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char HOUR1:4;
-			unsigned char HOUR10:2;
-			unsigned char  :1;
-			unsigned char ENB:1;
-		} BIT;
-	} RHRAR;
-	char           wk9[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DAY:3;
-			unsigned char :4;
-			unsigned char ENB:1;
-		} BIT;
-	} RWKAR;
-	char           wk10[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DAY1:4;
-			unsigned char DAY10:2;
-			unsigned char :1;
-			unsigned char ENB:1;
-		} BIT;
-	} RDAYAR;
-	char           wk11[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MON1:4;
-			unsigned char MON10:1;
-			unsigned char  :2;
-			unsigned char ENB:1;
-		} BIT;
-	} RMONAR;
-	char           wk12[1];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short YEAR1:4;
-			unsigned short YEAR10:4;
-			unsigned short YEAR100:4;
-			unsigned short YEAR1000:4;
-		} BIT;
-	} RYRAR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :7;
-			unsigned char ENB:1;
-		} BIT;
-	} RYRAREN;
-	char           wk13[3];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char AIE:1;
-			unsigned char CIE:1;
-			unsigned char PIE:1;
-			unsigned char  :1;
-			unsigned char PES:3;
-			unsigned char  :1;
-		} BIT;
-	} RCR1;
-	char           wk14[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char START:1;
-			unsigned char RESET:1;
-			unsigned char ADJ:1;
-			unsigned char RTCOE:1;
-			unsigned char  :4;
-		} BIT;
-	} RCR2;
-};
-
-struct st_s12ad {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char EXTRG:1;
-			unsigned char TRGE:1;
-			unsigned char CKS:2;
-			unsigned char ADIE:1;
-			unsigned char :1;
-			unsigned char ADCS:1;
-			unsigned char ADST:1;
-		} BIT;
-	} ADCSR;
-	char           wk0[3];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short ANS:8;
-			unsigned short  :8;
-		} BIT;
-*/
-	} ADANS;
-	char           wk1[2];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short ADS:8;
-			unsigned short  :8;
-		} BIT;
-*/
-	} ADADS;
-	char           wk2[2];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ADC:2;
-			unsigned char  :6;
-		} BIT;
-	} ADADC;
-	char           wk3[1];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :5;
-			unsigned short ACE:1;
-			unsigned short  :9;
-			unsigned short ADRFMT:1;
-		} BIT;
-	} ADCER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ADSTRS:4;
-			unsigned char  :4;
-		} BIT;
-	} ADSTRGR;
-	char           wk4[15];
-	unsigned short ADDR0;
-	unsigned short ADDR1;
-	unsigned short ADDR2;
-	unsigned short ADDR3;
-	unsigned short ADDR4;
-	unsigned short ADDR5;
-	unsigned short ADDR6;
-	unsigned short ADDR7;
-};
-
-struct st_sci {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CKS:2;
-			unsigned char MP:1;
-			unsigned char STOP:1;
-			unsigned char PM:1;
-			unsigned char PE:1;
-			unsigned char CHR:1;
-			unsigned char CM:1;
-		} BIT;
-	} SMR;
-	unsigned char  BRR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CKE:2;
-			unsigned char TEIE:1;
-			unsigned char MPIE:1;
-			unsigned char RE:1;
-			unsigned char TE:1;
-			unsigned char RIE:1;
-			unsigned char TIE:1;
-		} BIT;
-	} SCR;
-	unsigned char  TDR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char MPBT:1;
-			unsigned char MPB:1;
-			unsigned char TEND:1;
-			unsigned char PER:1;
-			unsigned char FER:1;
-			unsigned char ORER:1;
-			unsigned char RDRF:1;
-			unsigned char TDRE:1;
-		} BIT;
-	} SSR;
-	unsigned char  RDR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SMIF:1;
-			unsigned char  :1;
-			unsigned char SINV:1;
-			unsigned char SDIR:1;
-			unsigned char  :4;
-		} BIT;
-	} SCMR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char ACS0:1;
-			unsigned char  :3;
-			unsigned char ABCS:1;
-			unsigned char  :3;
-		} BIT;
-	} SEMR;
-};
-
-struct st_smci {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CKS:2;
-			unsigned char BCP:2;
-			unsigned char PM:1;
-			unsigned char PE:1;
-			unsigned char BLK:1;
-			unsigned char GM:1;
-		} BIT;
-	} SMR;
-	unsigned char  BRR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CKE:2;
-			unsigned char TEIE:1;
-			unsigned char  :1;
-			unsigned char RE:1;
-			unsigned char TE:1;
-			unsigned char RIE:1;
-			unsigned char TIE:1;
-		} BIT;
-	} SCR;
-	unsigned char  TDR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :2;
-			unsigned char TEND:1;
-			unsigned char PER:1;
-			unsigned char ERS:1;
-			unsigned char ORER:1;
-			unsigned char RDRF:1;
-			unsigned char TDRE:1;
-		} BIT;
-	} SSR;
-	unsigned char  RDR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SMIF:1;
-			unsigned char  :1;
-			unsigned char SINV:1;
-			unsigned char SDIR:1;
-			unsigned char  :3;
-			unsigned char BCP2:1;
-		} BIT;
-	} SCMR;
-};
-
-struct st_system {
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short MD0:1;
-			unsigned short MD1:1;
-			unsigned short  :5;
-			unsigned short MDE:1;
-			unsigned short  :8;
-		} BIT;
-*/
-	} MDMONR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short IROM:1;
-			unsigned short EXB:1;
-			unsigned short BSW:2;
-			unsigned short BOTS:1;
-			unsigned short  :1;
-			unsigned short UBTS:1;
-			unsigned short  :9;
-		} BIT;
-	} MDSR;
-	char           wk0[2];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short ROME:1;
-			unsigned short EXBE:1;
-			unsigned short  :6;
-			unsigned short KEY:8;
-		} BIT;
-*/
-	} SYSCR0;
-	union {
-		unsigned short WORD;
-		struct {
-		
-			unsigned short RAME:1;
-			unsigned short  :15;
-		} BIT;
-	} SYSCR1;
-	char           wk1[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short STS:5;
-			unsigned short  :1;
-			unsigned short OPE:1;
-			unsigned short SSBY:1;
-		} BIT;
-	} SBYCR;
-	char           wk2[2];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long  :4;
-			unsigned long MSTPA4:1;
-			unsigned long MSTPA5:1;
-			unsigned long  :2;
-			unsigned long MSTPA8:1;
-			unsigned long MSTPA9:1;
-			unsigned long MSTPA10:1;
-			unsigned long MSTPA11:1;
-			unsigned long  :2;
-			unsigned long MSTPA14:1;
-			unsigned long MSTPA15:1;
-			unsigned long  :1;
-			unsigned long MSTPA17:1;
-			unsigned long  :1;
-			unsigned long MSTPA19:1;
-			unsigned long  :2;
-			unsigned long MSTPA22:1;
-			unsigned long MSTPA23:1;
-			unsigned long  :4;
-			unsigned long MSTPA28:1;
-			unsigned long MSTPA29:1;
-			unsigned long  :1;
-			unsigned long ACSE:1;		
-		} BIT;
-	} MSTPCRA;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long MSTPB0:1;
-			unsigned long  :14;
-			unsigned long MSTPB15:1;
-			unsigned long MSTPB16:1;
-			unsigned long MSTPB17:1;
-			unsigned long MSTPB18:1;
-			unsigned long MSTPB19:1;
-			unsigned long MSTPB20:1;
-			unsigned long MSTPB21:1;
-			unsigned long  :1;
-			unsigned long MSTPB23:1;
-			unsigned long  :1;
-			unsigned long MSTPB25:1;
-			unsigned long MSTPB26:1;
-			unsigned long  :1;
-			unsigned long MSTPB28:1;
-			unsigned long MSTPB29:1;
-			unsigned long MSTPB30:1;
-			unsigned long MSTPB31:1;
-		} BIT;
-	} MSTPCRB;
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long MSTPC0:1;
-			unsigned long MSTPC1:1;
-			unsigned long  :30;
-		} BIT;
-	} MSTPCRC;
-	char           wk3[4];
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long  :8;
-			unsigned long PCK:4;
-			unsigned long  :4;
-			unsigned long BCK:4;
-			unsigned long  :2;
-			unsigned long PSTOP0:1;
-			unsigned long PSTOP1:1;
-			unsigned long ICK:4;
-			unsigned long  :4;
-		} BIT;
-	} SCKCR;
-	char           wk4[12];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char BCLKDIV:1;
-			unsigned char  :7;
-		} BIT;
-	} BCKCR;
-	char           wk5[15];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short  :6;
-			unsigned short OSTDF:1;
-			unsigned short OSTDE:1;
-			unsigned short KEY:8;
-		} BIT;
-*/
-	} OSTDCR;
-	char           wk6[49726];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char RAMCUT0:1;
-			unsigned char :3;
-			unsigned char RAMCUT1:1;
-			unsigned char RAMCUT2:1;
-			unsigned char IOKEEP:1;
-			unsigned char DPSBY:1;
-		} BIT;
-	} DPSBYCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char WTSTS:6;
-			unsigned char  :2;
-		} BIT;
-	} DPSWCR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DIRQ0E:1;
-			unsigned char DIRQ1E:1;
-			unsigned char DIRQ2E:1;
-			unsigned char DIRQ3E:1;
-			unsigned char DLVDE:1;
-			unsigned char DRTCE:1;
-			unsigned char DUSBE:1;
-			unsigned char DNMIE:1;
-		} BIT;
-	} DPSIER;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DIRQ0F:1;
-			unsigned char DIRQ1F:1;
-			unsigned char DIRQ2F:1;
-			unsigned char DIRQ3F:1;
-			unsigned char DLVDF:1;
-			unsigned char DRTCFF:1;
-			unsigned char DUSBF:1;
-			unsigned char DNMIF:1;
-		} BIT;
-	} DPSIFR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char DIRQ0EG:1;
-			unsigned char DIRQ1EG:1;
-			unsigned char DIRQ2EG:1;
-			unsigned char DIRQ3EG:1;
-			unsigned char DPSIER:3;
-			unsigned char DNMIEG:1;
-		} BIT;
-	} DPSIEGR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char PORF:1;
-			unsigned char LVD1F:1;
-			unsigned char LVD2F:1;
-			unsigned char DPSIER:4;
-			unsigned char DPSRSTF:1;
-		} BIT;
-	} RSTSR;
-	char           wk7[4];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char SUBSTOP:1;
-			unsigned char DPSIER:7;
-		} BIT;
-	} SUBOSCCR;
-	char           wk8[1];
-	unsigned char  LVDKEYR;
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :2;
-			unsigned char LVD1RI:1;
-			unsigned char LVD1E:1;
-			unsigned char  :2;
-			unsigned char LVD2RI:1;
-			unsigned char LVD2E:1;
-		} BIT;
-	} LVDCR;
-	char           wk9[2];
-	unsigned char  DPSBKR[32];
-};
-
-struct st_tmr0 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :3;
-			unsigned char CCLR:2;
-			unsigned char OVIE:1;
-			unsigned char CMIEA:1;
-			unsigned char CMIEB:1;
-		} BIT;
-	} TCR;
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char OSA:2;
-			unsigned char OSB:2;
-			unsigned char ADTE:1;
-			unsigned char  :3;
-		} BIT;
-	} TCSR;
-	char           wk1[1];
-	unsigned char  TCORA;
-	char           wk2[1];
-	unsigned char  TCORB;
-	char           wk3[1];
-	unsigned char  TCNT;
-	char           wk4[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CKS:3;
-			unsigned char CSS:2;
-			unsigned char  :2;
-			unsigned char TMRIS:1;
-		} BIT;
-	} TCCR;
-};
-
-struct st_tmr1 {
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char  :3;
-			unsigned char CCLR:2;
-			unsigned char OVIE:1;
-			unsigned char CMIEA:1;
-			unsigned char CMIEB:1;
-		} BIT;
-	} TCR;
-	char           wk0[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char OSA:2;
-			unsigned char OSB:2;
-			unsigned char  :4;
-		} BIT;
-	} TCSR;
-	char           wk1[1];
-	unsigned char  TCORA;
-	char           wk2[1];
-	unsigned char  TCORB;
-	char           wk3[1];
-	unsigned char  TCNT;
-	char           wk4[1];
-	union {
-		unsigned char BYTE;
-		struct {
-			unsigned char CKS:3;
-			unsigned char CSS:2;
-			unsigned char  :2;
-			unsigned char TMRIS:1;
-		} BIT;
-	} TCCR;
-};
-
-struct st_tmr01 {
-	unsigned short TCORA;
-	unsigned short TCORB;
-	unsigned short TCNT;
-	unsigned short TCCR;
-};
-
-struct st_usb {
-	union {
-		unsigned long LONG;
-		struct {
-			unsigned long SRPC0:1;
-			unsigned long  :3;
-			unsigned long FIXPHY0:1;
-			unsigned long  :3;
-			unsigned long SRPC1:1;
-			unsigned long  :3;
-			unsigned long FIXPHY1:1;
-			unsigned long  :3;
-			unsigned long DP0:1;
-			unsigned long DM0:1;
-			unsigned long  :2;
-			unsigned long DOVCA0:1;
-			unsigned long DOVCB0:1;
-			unsigned long  :1;
-			unsigned long DVBSTS0:1;
-			unsigned long DP1:1;
-			unsigned long DM1:1;
-			unsigned long  :2;
-			unsigned long DOVCA1:1;
-			unsigned long DOVCB1:1;
-			unsigned long  :1;
-			unsigned long DVSTS1:1;
-		} BIT;
-	} DPUSR0R;
-	union {
-		unsigned long LONG;
-		struct {
-		
-			unsigned long DPINTE0:1;
-			unsigned long DMINTE0:1;
-			unsigned long  :2;
-			unsigned long DOVRCRAE0:1;
-			unsigned long DOVRCRBE0:1;
-			unsigned long  :1;
-			unsigned long DVBSE0:1;
-			unsigned long DPINTE1:1;
-			unsigned long DMINTE1:1;
-			unsigned long  :2;
-			unsigned long DOVRCRAE1:1;
-			unsigned long DOVRCRBE1:1;
-			unsigned long  :1;
-			unsigned long DVBSE1:1;
-			unsigned long DPINT0:1;
-			unsigned long DMINT0:1;
-			unsigned long  :2;
-			unsigned long DOVRCRA0:1;
-			unsigned long DOVRCRB0:1;
-			unsigned long  :1;
-			unsigned long DVBINT0:1;
-			unsigned long DPINT1:1;
-			unsigned long DMINT1:1;
-			unsigned long  :2;
-			unsigned long DOVRCRA1:1;
-			unsigned long DOVRCRB1:1;
-			unsigned long  :1;
-			unsigned long DVBINT1:1;
-		} BIT;
-	} DPUSR1R;
-};
-
-struct st_usb0 {
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short USBE:1;
-			unsigned short  :3;
-			unsigned short DPRPU:1;
-			unsigned short DRPD:1;
-			unsigned short DCFM:1;
-			unsigned short  :3;
-			unsigned short SCKE:1;
-			unsigned short  :5;
-		} BIT;
-	} SYSCFG;
-	char           wk0[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short LNST:2;
-			unsigned short IDMON:1;
-			unsigned short :3;
-			unsigned short HTACT:1;
-			unsigned short :7;
-			unsigned short OVCMON:2;
-		} BIT;
-	} SYSSTS0;
-	char           wk1[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short RHST:3;
-			unsigned short  :1;
-			unsigned short UACT:1;
-			unsigned short RESUME:1;
-			unsigned short USBRST:1;
-			unsigned short RWUPE:1;
-			unsigned short WKUP:1;
-			unsigned short VBUSEN:1;
-			unsigned short EXICEN:1;
-			unsigned short HNPBTOA:1;
-			unsigned short  :4;
-		} BIT;
-	} DVSTCTR0;
-	char           wk2[10];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned char L;
-			unsigned char H;
-		} BYTE;
-	} CFIFO;
-	char           wk3[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned char L;
-			unsigned char H;
-		} BYTE;
-	} D0FIFO;
-	char           wk4[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned char L;
-			unsigned char H;
-		} BYTE;
-	} D1FIFO;
-	char           wk5[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CURPIPE:4;
-			unsigned short  :1;
-			unsigned short ISEL:1;
-			unsigned short  :2;
-			unsigned short BIGEND:1;
-			unsigned short  :1;
-			unsigned short MBW:1;
-			unsigned short  :3;
-			unsigned short REW:1;
-			unsigned short RCNT:1;
-		} BIT;
-	} CFIFOSEL;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short DTLN:9;
-			unsigned short  :4;
-			unsigned short FRDY:1;
-			unsigned short BCLR:1;
-			unsigned short BVAL:1;
-		} BIT;
-	} CFIFOCTR;
-	char           wk6[4];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CURPIPE:4;
-			unsigned short  :4;
-			unsigned short BIGEND:1;
-			unsigned short  :1;
-			unsigned short MBW:1;
-			unsigned short  :1;
-			unsigned short DREQE:1;
-			unsigned short DCLRM:1;
-			unsigned short REW:1;
-			unsigned short RCNT:1;
-		} BIT;
-	} D0FIFOSEL;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short DTLN:9;
-			unsigned short :4;
-			unsigned short FRDY:1;
-			unsigned short BCLR:1;
-			unsigned short BVAL:1;
-		} BIT;
-	} D0FIFOCTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CURPIPE:4;
-			unsigned short  :4;
-			unsigned short BIGEND:1;
-			unsigned short  :1;
-			unsigned short MBW:1;
-			unsigned short  :1;
-			unsigned short DREQE:1;
-			unsigned short DCLRM:1;
-			unsigned short REW:1;
-			unsigned short RCNT:1;
-		} BIT;
-	} D1FIFOSEL;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short DTLN:9;
-			unsigned short  :4;
-			unsigned short FRDY:1;
-			unsigned short BCLR:1;
-			unsigned short BVAL:1;
-		} BIT;
-	} D1FIFOCTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :8;
-			unsigned short BRDYE:1;
-			unsigned short NRDYE:1;
-			unsigned short BEMPE:1;
-			unsigned short CTRE:1;
-			unsigned short DVSE:1;
-			unsigned short SOFE:1;
-			unsigned short RSME:1;
-			unsigned short VBSE:1;
-		} BIT;
-	} INTENB0;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :4;
-			unsigned short SACKE:1;
-			unsigned short SIGNE:1;
-			unsigned short EOFERRE:1;
-			unsigned short  :4;
-			unsigned short ATTCHE:1;
-			unsigned short DTCHE:1;
-			unsigned short  :1;
-			unsigned short BCHGE:1;
-			unsigned short OVRCRE:1;
-		} BIT;
-	} INTENB1;
-	char           wk7[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PIPE0BRDYE:1;
-			unsigned short PIPE1BRDYE:1;
-			unsigned short PIPE2BRDYE:1;
-			unsigned short PIPE3BRDYE:1;
-			unsigned short PIPE4BRDYE:1;
-			unsigned short PIPE5BRDYE:1;
-			unsigned short PIPE6BRDYE:1;
-			unsigned short PIPE7BRDYE:1;
-			unsigned short PIPE8BRDYE:1;
-			unsigned short PIPE9BRDYE:1;
-			unsigned short  :6;
-		} BIT;
-	} BRDYENB;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PIPE0BRDYE:1;
-			unsigned short PIPE1BRDYE:1;
-			unsigned short PIPE2BRDYE:1;
-			unsigned short PIPE3BRDYE:1;
-			unsigned short PIPE4BRDYE:1;
-			unsigned short PIPE5BRDYE:1;
-			unsigned short PIPE6BRDYE:1;
-			unsigned short PIPE7BRDYE:1;
-			unsigned short PIPE8BRDYE:1;
-			unsigned short PIPE9BRDYE:1;
-			unsigned short  :6;
-		} BIT;
-	} NRDYENB;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PIPE0BEMPE:1;
-			unsigned short PIPE1BEMPE:1;
-			unsigned short PIPE2BEMPE:1;
-			unsigned short PIPE3BEMPE:1;
-			unsigned short PIPE4BEMPE:1;
-			unsigned short PIPE5BEMPE:1;
-			unsigned short PIPE6BEMPE:1;
-			unsigned short PIPE7BEMPE:1;
-			unsigned short PIPE8BEMPE:1;
-			unsigned short PIPE9BEMPE:1;
-			unsigned short  :6;
-		} BIT;
-	} BEMPENB;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :4;
-			unsigned short EDGESTS:1;
-			unsigned short  :1;
-			unsigned short BRDYM:1;
-			unsigned short  :1;
-			unsigned short TRNENSEL:1;
-			unsigned short  :7;
-		
-		} BIT;
-	} SOFCFG;
-	char           wk8[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short CTSQ:3;
-			unsigned short VALID:1;
-			unsigned short DVSQ:3;
-			unsigned short VBSTS:1;
-			unsigned short BRDY:1;
-			unsigned short NRDY:1;
-			unsigned short BEMP:1;
-			unsigned short CTRT:1;
-			unsigned short DVST:1;
-			unsigned short SOFR:1;
-			unsigned short RESM:1;
-			unsigned short VBINT:1;
-		} BIT;
-	} INTSTS0;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :4;
-			unsigned short SACK:1;
-			unsigned short SIGN:1;
-			unsigned short EOFERR:1;
-			unsigned short  :4;
-			unsigned short ATTCH:1;
-			unsigned short DTCH:1;
-			unsigned short  :1;
-			unsigned short BCHG:1;
-			unsigned short OVRCR:1;
-		} BIT;
-	} INTSTS1;
-	char           wk9[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PIPE0BRDY:1;
-			unsigned short PIPE1BRDY:1;
-			unsigned short PIPE2BRDY:1;
-			unsigned short PIPE3BRDY:1;
-			unsigned short PIPE4BRDY:1;
-			unsigned short PIPE5BRDY:1;
-			unsigned short PIPE6BRDY:1;
-			unsigned short PIPE7BRDY:1;
-			unsigned short PIPE8BRDY:1;
-			unsigned short PIPE9BRDY:1;
-			unsigned short  :6;
-		} BIT;
-	} BRDYSTS;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PIPE0BRDY:1;
-			unsigned short PIPE1BRDY:1;
-			unsigned short PIPE2BRDY:1;
-			unsigned short PIPE3BRDY:1;
-			unsigned short PIPE4BRDY:1;
-			unsigned short PIPE5BRDY:1;
-			unsigned short PIPE6BRDY:1;
-			unsigned short PIPE7BRDY:1;
-			unsigned short PIPE8BRDY:1;
-			unsigned short PIPE9BRDY:1;
-			unsigned short  :6;
-		} BIT;
-	} NRDYSTS;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PIPE0BENP:1;
-			unsigned short PIPE1BENP:1;
-			unsigned short PIPE2BENP:1;
-			unsigned short PIPE3BENP:1;
-			unsigned short PIPE4BENP:1;
-			unsigned short PIPE5BENP:1;
-			unsigned short PIPE6BENP:1;
-			unsigned short PIPE7BENP:1;
-			unsigned short PIPE8BENP:1;
-			unsigned short PIPE9BENP:1;
-			unsigned short  :6;
-		} BIT;
-	} BEMPSTS;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short FRNM:11;
-			unsigned short  :3;
-			unsigned short CRCE:1;
-			unsigned short OVRN:1;
-		} BIT;
-	} FRMNUM;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :15;
-			unsigned short DVCHG:1;
-		} BIT;
-	} DVCHGR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short USBADDR:7;
-			unsigned short  :1;
-			unsigned short STSRECOV:4;
-			unsigned short  :4;
-		} BIT;
-	} USBADDR;
-	char           wk10[2];
-	union {
-		unsigned short WORD;
-/* -- oops!
-		struct {
-			unsigned short BMREQUESTTYPE:8;
-			unsigned short BREQUEST:8;
-		} BIT;
-*/
-	} USBREQ;
-	unsigned short USBVAL;
-	unsigned short USBINDX;
-	unsigned short USBLENG;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :4;
-			unsigned short DIR:1;
-			unsigned short  :2;
-			unsigned short SHTNAK:1;
-			unsigned short  :8;
-		} BIT;
-	} DCPCFG;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short MXPS:7;
-			unsigned short  :5;
-			unsigned short DEVSEL:4;
-		} BIT;
-	} DCPMAXP;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short CCPL:1;
-			unsigned short  :2;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short  :2;
-			unsigned short SUREQCLR:1;
-			unsigned short  :2;
-			unsigned short SUREQ:1;
-			unsigned short BSTS:1;
-		} BIT;
-	} DCPCTR;
-	char           wk11[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PIPESEL:4;
-			unsigned short  :12;
-		} BIT;
-	} PIPESEL;
-	char           wk12[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short EPNUM:4;
-			unsigned short DIR:1;
-			unsigned short  :2;
-			unsigned short SHTNAK:1;
-			unsigned short  :1;
-			unsigned short DBLB:1;
-			unsigned short BFRE:1;
-			unsigned short  :3;
-			unsigned short TYPE:2;
-		} BIT;
-	} PIPECFG;
-	char           wk13[2];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short MXPS:9;
-			unsigned short  :3;
-			unsigned short DEVSEL:4;
-		} BIT;
-	} PIPEMAXP;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short IITV:3;
-			unsigned short  :9;
-			unsigned short IFIS:1;
-			unsigned short  :3;
-		} BIT;
-	} PIPEPERI;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short  :3;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short ACLRM:1;
-			unsigned short ATREPM:1;
-			unsigned short  :3;
-			unsigned short INBUFM:1;
-			unsigned short BSTS:1;
-		} BIT;
-	} PIPE1CTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short  :3;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short ACLRM:1;
-			unsigned short ATREPM:1;
-			unsigned short  :3;
-			unsigned short INBUFM:1;
-			unsigned short BSTS:1;
-		} BIT;
-	} PIPE2CTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short :3;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short ACLRM:1;
-			unsigned short ATREPM:1;
-			unsigned short :3;
-			unsigned short INBUFM:1;
-			unsigned short BSTS:1;
-		} BIT;
-	} PIPE3CTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short  :3;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short ACLRM:1;
-			unsigned short ATREPM:1;
-			unsigned short  :3;
-			unsigned short INBUFM:1;
-			unsigned short BSTS:1;	
-		} BIT;
-	} PIPE4CTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short  :3;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short ACLRM:1;
-			unsigned short ATREPM:1;
-			unsigned short  :3;
-			unsigned short INBUFM:1;
-			unsigned short BSTS:1;
-		} BIT;
-	} PIPE5CTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short  :3;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short ACLRM:1;
-			unsigned short  :5;
-			unsigned short BSTS:1;
-		} BIT;
-	} PIPE6CTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short  :3;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short ACLRM:1;
-			unsigned short  :5;
-			unsigned short BSTS:1;
-		} BIT;
-	} PIPE7CTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short :3;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short ACLRM:1;
-			unsigned short  :5;
-			unsigned short BSTS:1;		
-		} BIT;
-	} PIPE8CTR;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short PID:2;
-			unsigned short  :3;
-			unsigned short PBUSY:1;
-			unsigned short SQMON:1;
-			unsigned short SQSET:1;
-			unsigned short SQCLR:1;
-			unsigned short ACLRM:1;
-			unsigned short  :5;
-			unsigned short BSTS:1;
-		} BIT;
-	} PIPE9CTR;
-	char           wk14[14];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :8;
-			unsigned short TRCLR:1;
-			unsigned short TRENB:1;
-			unsigned short  :6;
-		} BIT;
-	} PIPE1TRE;
-	unsigned short PIPE1TRN;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :8;
-			unsigned short TRCLR:1;
-			unsigned short TRENB:1;
-			unsigned short  :6;
-		} BIT;
-	} PIPE2TRE;
-	unsigned short PIPE2TRN;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :8;
-			unsigned short TRCLR:1;
-			unsigned short TRENB:1;
-			unsigned short  :6;
-		} BIT;
-	} PIPE3TRE;
-	unsigned short PIPE3TRN;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :8;
-			unsigned short TRCLR:1;
-			unsigned short TRENB:1;
-			unsigned short  :6;
-		} BIT;
-	} PIPE4TRE;
-	unsigned short PIPE4TRN;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :8;
-			unsigned short TRCLR:1;
-			unsigned short TRENB:1;
-			unsigned short  :6;
-		} BIT;
-	} PIPE5TRE;
-	unsigned short PIPE5TRN;
-	char           wk15[44];
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :6;
-			unsigned short USBSPD:2;
-			unsigned short  :8;
-		} BIT;
-	} DEVADD0;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :6;
-			unsigned short USBSPD:2;
-			unsigned short  :8;
-		} BIT;
-	} DEVADD1;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :6;
-			unsigned short USBSPD:2;
-			unsigned short  :8;
-		} BIT;
-	} DEVADD2;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :6;
-			unsigned short USBSPD:2;
-			unsigned short  :8;
-		} BIT;
-	} DEVADD3;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :6;
-			unsigned short USBSPD:2;
-			unsigned short  :8;
-		} BIT;
-	} DEVADD4;
-	union {
-		unsigned short WORD;
-		struct {
-			unsigned short  :6;
-			unsigned short USBSPD:2;
-			unsigned short  :8;
-		} BIT;
-	} DEVADD5;
-};
-
-union un_wdt {
-	struct {
-		union {
-			unsigned char BYTE;
-			struct {
-				unsigned char CKS:3;
-				unsigned char  :2;
-				unsigned char TME:1;
-				unsigned char TMS:1;
-				unsigned char  :1;
-			} BIT;
-		} TCSR;
-		unsigned char  TCNT;
-		char           wk0[1];
-		union {
-			unsigned char BYTE;
-			struct {
-				unsigned char  :6;
-				unsigned char RSTE:1;
-				unsigned char WOVF:1;
-			} BIT;
-		} RSTCSR;
-	} READ;
-	struct {
-		unsigned short WINA;
-		unsigned short WINB;
-	} WRITE;
-};
-
-enum enum_ir {
-IR_BSC_BUSERR=16,IR_FCU_FIFERR=21,IR_FCU_FRDYI=23,
-IR_ICU_SWINT=27,
-IR_CMT0_CMI0,
-IR_CMT1_CMI1,
-IR_CMT2_CMI2,
-IR_CMT3_CMI3,
-IR_ETHER_EINT,
-IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,
-IR_USB1_D0FIFO1=40,IR_USB1_D1FIFO1,IR_USB1_USBI1,
-IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,
-IR_RSPI1_SPEI1,IR_RSPI1_SPRI1,IR_RSPI1_SPTI1,IR_RSPI1_SPII1,
-IR_CAN0_ERS0=56,IR_CAN0_RXF0,IR_CAN0_TXF0,IR_CAN0_RXM0,IR_CAN0_TXM0,
-IR_RTC_PRD=62,IR_RTC_CUP,
-IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15,
-IR_USB_USBR0=90,IR_USB_USBR1,
-IR_RTC_ALM,
-IR_WDT_WOVI=96,
-IR_AD0_ADI0=98,
-IR_AD1_ADI1,
-IR_S12AD_ADI=102,
-IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,
-IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,
-IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,
-IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,
-IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,
-IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,
-IR_MTU6_TGIA6,IR_MTU6_TGIB6,IR_MTU6_TGIC6,IR_MTU6_TGID6,IR_MTU6_TCIV6,IR_MTU6_TGIE6,IR_MTU6_TGIF6,
-IR_MTU7_TGIA7,IR_MTU7_TGIB7,IR_MTU7_TCIV7,IR_MTU7_TCIU7,
-IR_MTU8_TGIA8,IR_MTU8_TGIB8,IR_MTU8_TCIV8,IR_MTU8_TCIU8,
-IR_MTU9_TGIA9,IR_MTU9_TGIB9,IR_MTU9_TGIC9,IR_MTU9_TGID9,IR_MTU9_TCIV9,
-IR_MTU10_TGIA10,IR_MTU10_TGIB10,IR_MTU10_TGIC10,IR_MTU10_TGID10,IR_MTU10_TCIV10,
-IR_MTU11_TGIU11,IR_MTU11_TGIV11,IR_MTU11_TGIW11,
-IR_POE_OEI1,IR_POE_OEI2,IR_POE_OEI3,IR_POE_OEI4,
-IR_TMR0_CMIA0,IR_TMR0_CMIB0,IR_TMR0_OVI0,
-IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1,
-IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2,
-IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3,
-IR_DMAC_DMAC0I=198,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I,
-IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I,
-IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0,
-IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,
-IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2,
-IR_SCI3_ERI3,IR_SCI3_RXI3,IR_SCI3_TXI3,IR_SCI3_TEI3,
-IR_SCI5_ERI5=234,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,
-IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6,
-IR_RIIC0_ICEEI0=246,IR_RIIC0_ICRXI0,IR_RIIC0_ICTXI0,IR_RIIC0_ICTEI0,
-IR_RIIC1_ICEEI1,IR_RIIC1_ICRXI1,IR_RIIC1_ICTXI1,IR_RIIC1_ICTEI1
-};
-
-enum enum_dtce {
-DTCE_ICU_SWINT=27,
-DTCE_CMT0_CMI0,
-DTCE_CMT1_CMI1,
-DTCE_CMT2_CMI2,
-DTCE_CMT3_CMI3,
-DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,
-DTCE_USB1_D0FIFO1=40,DTCE_USB1_D1FIFO1,
-DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,
-DTCE_RSPI1_SPRI1=49,DTCE_RSPI1_SPTI1,
-DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15,
-DTCE_AD0_ADI0=98,
-DTCE_AD1_ADI1,
-DTCE_S12AD_ADI=102,
-DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,
-DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,
-DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,
-DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,
-DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,
-DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,
-DTCE_MTU6_TGIA6,DTCE_MTU6_TGIB6,DTCE_MTU6_TGIC6,DTCE_MTU6_TGID6,
-DTCE_MTU7_TGIA7=149,DTCE_MTU7_TGIB7,
-DTCE_MTU8_TGIA8=153,DTCE_MTU8_TGIB8,
-DTCE_MTU9_TGIA9=157,DTCE_MTU9_TGIB9,DTCE_MTU9_TGIC9,DTCE_MTU9_TGID9,
-DTCE_MTU10_TGIA10=162,DTCE_MTU10_TGIB10,DTCE_MTU10_TGIC10,DTCE_MTU10_TGID10,DTCE_MTU10_TCIV10,
-DTCE_MTU11_TGIU11,DTCE_MTU11_TGIV11,DTCE_MTU11_TGIW11,
-DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0,
-DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1,
-DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2,
-DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3,
-DTCE_DMAC_DMAC0I=198,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I,
-DTCE_EXDMAC_EXDMAC0I,DTCE_EXDMAC_EXDMAC1I,
-DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0,
-DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,
-DTCE_SCI2_RXI2=223,DTCE_SCI2_TXI2,
-DTCE_SCI3_RXI3=227,DTCE_SCI3_TXI3,
-DTCE_SCI5_RXI5=235,DTCE_SCI5_TXI5,
-DTCE_SCI6_RXI6=239,DTCE_SCI6_TXI6,
-DTCE_RIIC0_ICRXI0=247,DTCE_RIIC0_ICTXI0,
-DTCE_RIIC1_ICRXI1=251,DTCE_RIIC1_ICTXI1
-};
-
-enum enum_ier {
-IER_BSC_BUSERR=0x02,
-IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02,
-IER_ICU_SWINT=0x03,
-IER_CMT0_CMI0=0x03,
-IER_CMT1_CMI1=0x03,
-IER_CMT2_CMI2=0x03,
-IER_CMT3_CMI3=0x03,
-IER_ETHER_EINT=0x04,
-IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,
-IER_USB1_D0FIFO1=0x05,IER_USB1_D1FIFO1=0x05,IER_USB1_USBI1=0x05,
-IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,
-IER_RSPI1_SPEI1=0x06,IER_RSPI1_SPRI1=0x06,IER_RSPI1_SPTI1=0x06,IER_RSPI1_SPII1=0x06,
-IER_CAN0_ERS0=0x07,IER_CAN0_RXF0=0x07,IER_CAN0_TXF0=0x07,IER_CAN0_RXM0=0x07,IER_CAN0_TXM0=0x07,
-IER_RTC_PRD=0x07,IER_RTC_CUP=0x07,
-IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09,
-IER_USB_USBR0=0x0B,IER_USB_USBR1=0x0B,
-IER_RTC_ALM=0x0B,
-IER_WDT_WOVI=0x0C,
-IER_AD0_ADI0=0x0C,
-IER_AD1_ADI1=0x0C,
-IER_S12AD_ADI=0x0C,
-IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,
-IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,
-IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,
-IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,
-IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,
-IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x10,
-IER_MTU6_TGIA6=0x11,IER_MTU6_TGIB6=0x11,IER_MTU6_TGIC6=0x12,IER_MTU6_TGID6=0x12,IER_MTU6_TCIV6=0x12,IER_MTU6_TGIE6=0x12,IER_MTU6_TGIF6=0x12,
-IER_MTU7_TGIA7=0x12,IER_MTU7_TGIB7=0x12,IER_MTU7_TCIV7=0x12,IER_MTU7_TCIU7=0x13,
-IER_MTU8_TGIA8=0x13,IER_MTU8_TGIB8=0x13,IER_MTU8_TCIV8=0x13,IER_MTU8_TCIU8=0x13,
-IER_MTU9_TGIA9=0x13,IER_MTU9_TGIB9=0x13,IER_MTU9_TGIC9=0x13,IER_MTU9_TGID9=0x14,IER_MTU9_TCIV9=0x14,
-IER_MTU10_TGIA10=0x14,IER_MTU10_TGIB10=0x14,IER_MTU10_TGIC10=0x14,IER_MTU10_TGID10=0x14,IER_MTU10_TCIV10=0x14,
-IER_MTU11_TGIU11=0x14,IER_MTU11_TGIV11=0x15,IER_MTU11_TGIW11=0x15,
-IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,IER_POE_OEI3=0x15,IER_POE_OEI4=0x15,
-IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16,
-IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16,
-IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16,
-IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17,
-IER_DMAC_DMAC0I=0x18,IER_DMAC_DMAC1I=0x18,IER_DMAC_DMAC2I=0x19,IER_DMAC_DMAC3I=0x19,
-IER_EXDMAC_EXDMAC0I=0x19,IER_EXDMAC_EXDMAC1I=0x19,
-IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B,
-IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,
-IER_SCI2_ERI2=0x1B,IER_SCI2_RXI2=0x1B,IER_SCI2_TXI2=0x1C,IER_SCI2_TEI2=0x1C,
-IER_SCI3_ERI3=0x1C,IER_SCI3_RXI3=0x1C,IER_SCI3_TXI3=0x1C,IER_SCI3_TEI3=0x1C,
-IER_SCI5_ERI5=0x1D,IER_SCI5_RXI5=0x1D,IER_SCI5_TXI5=0x1D,IER_SCI5_TEI5=0x1D,
-IER_SCI6_ERI6=0x1D,IER_SCI6_RXI6=0x1D,IER_SCI6_TXI6=0x1E,IER_SCI6_TEI6=0x1E,
-IER_RIIC0_ICEEI0=0x1E,IER_RIIC0_ICRXI0=0x1E,IER_RIIC0_ICTXI0=0x1F,IER_RIIC0_ICTEI0=0x1F,
-IER_RIIC1_ICEEI1=0x1F,IER_RIIC1_ICRXI1=0x1F,IER_RIIC1_ICTXI1=0x1F,IER_RIIC1_ICTEI1=0x1F
-};
-
-enum enum_ipr {
-IPR_BSC_BUSERR=0x00,
-IPR_FCU_FIFERR=0x01,IPR_FCU_FRDYI=0x02,
-IPR_ICU_SWINT=0x03,
-IPR_CMT0_CMI0=0x04,
-IPR_CMT1_CMI1=0x05,
-IPR_CMT2_CMI2=0x06,
-IPR_CMT3_CMI3=0x07,
-IPR_ETHER_EINT=0x08,
-IPR_USB0_D0FIFO0=0x0C,IPR_USB0_D1FIFO0=0x0D,IPR_USB0_USBI0=0x0E,
-IPR_USB1_D0FIFO1=0x10,IPR_USB1_D1FIFO1=0x11,IPR_USB1_USBI1=0x12,
-IPR_RSPI0_SPEI0=0x14,IPR_RSPI0_SPRI0=0x14,IPR_RSPI0_SPTI0=0x14,IPR_RSPI0_SPII0=0x14,
-IPR_RSPI1_SPEI1=0x15,IPR_RSPI1_SPRI1=0x15,IPR_RSPI1_SPTI1=0x15,IPR_RSPI1_SPII1=0x15,
-IPR_CAN0_ERS0=0x18,IPR_CAN0_RXF0=0x18,IPR_CAN0_TXF0=0x18,IPR_CAN0_RXM0=0x18,IPR_CAN0_TXM0=0x18,
-IPR_RTC_PRD=0x1E,IPR_RTC_CUP=0x1F,
-IPR_ICU_IRQ0=0x20,IPR_ICU_IRQ1=0x21,IPR_ICU_IRQ2=0x22,IPR_ICU_IRQ3=0x23,IPR_ICU_IRQ4=0x24,IPR_ICU_IRQ5=0x25,IPR_ICU_IRQ6=0x26,IPR_ICU_IRQ7=0x27,IPR_ICU_IRQ8=0x28,IPR_ICU_IRQ9=0x29,IPR_ICU_IRQ10=0x2A,IPR_ICU_IRQ11=0x2B,IPR_ICU_IRQ12=0x2C,IPR_ICU_IRQ13=0x2D,IPR_ICU_IRQ14=0x2E,IPR_ICU_IRQ15=0x2F,
-IPR_USB_USBR0=0x3A,IPR_USB_USBR1=0x3B,
-IPR_RTC_ALM=0x3C,
-IPR_WDT_WOVI=0x40,
-IPR_AD0_ADI0=0x44,
-IPR_AD1_ADI1=0x45,
-IPR_S12AD_ADI=0x48,
-IPR_MTU0_TGIA0=0x51,IPR_MTU0_TGIB0=0x51,IPR_MTU0_TGIC0=0x51,IPR_MTU0_TGID0=0x51,IPR_MTU0_TCIV0=0x52,IPR_MTU0_TGIE0=0x52,IPR_MTU0_TGIF0=0x52,
-IPR_MTU1_TGIA1=0x53,IPR_MTU1_TGIB1=0x53,IPR_MTU1_TCIV1=0x54,IPR_MTU1_TCIU1=0x54,
-IPR_MTU2_TGIA2=0x55,IPR_MTU2_TGIB2=0x55,IPR_MTU2_TCIV2=0x56,IPR_MTU2_TCIU2=0x56,
-IPR_MTU3_TGIA3=0x57,IPR_MTU3_TGIB3=0x57,IPR_MTU3_TGIC3=0x57,IPR_MTU3_TGID3=0x57,IPR_MTU3_TCIV3=0x58,
-IPR_MTU4_TGIA4=0x59,IPR_MTU4_TGIB4=0x59,IPR_MTU4_TGIC4=0x59,IPR_MTU4_TGID4=0x59,IPR_MTU4_TCIV4=0x5A,
-IPR_MTU5_TGIU5=0x5B,IPR_MTU5_TGIV5=0x5B,IPR_MTU5_TGIW5=0x5B,
-IPR_MTU6_TGIA6=0x5C,IPR_MTU6_TGIB6=0x5C,IPR_MTU6_TGIC6=0x5C,IPR_MTU6_TGID6=0x5C,IPR_MTU6_TCIV6=0x5D,IPR_MTU6_TGIE6=0x5D,IPR_MTU6_TGIF6=0x5D,
-IPR_MTU7_TGIA7=0x5E,IPR_MTU7_TGIB7=0x5E,IPR_MTU7_TCIV7=0x5F,IPR_MTU7_TCIU7=0x5F,
-IPR_MTU8_TGIA8=0x60,IPR_MTU8_TGIB8=0x60,IPR_MTU8_TCIV8=0x61,IPR_MTU8_TCIU8=0x61,
-IPR_MTU9_TGIA9=0x62,IPR_MTU9_TGIB9=0x62,IPR_MTU9_TGIC9=0x62,IPR_MTU9_TGID9=0x62,IPR_MTU9_TCIV9=0x63,
-IPR_MTU10_TGIA10=0x64,IPR_MTU10_TGIB10=0x64,IPR_MTU10_TGIC10=0x64,IPR_MTU10_TGID10=0x64,IPR_MTU10_TCIV10=0x65,
-IPR_MTU11_TGIU11=0x66,IPR_MTU11_TGIV11=0x66,IPR_MTU11_TGIW11=0x66,
-IPR_POE_OEI1=0x67,IPR_POE_OEI2=0x67,IPR_POE_OEI3=0x67,IPR_POE_OEI4=0x67,
-IPR_TMR0_CMIA0=0x68,IPR_TMR0_CMIB0=0x68,IPR_TMR0_OVI0=0x68,
-IPR_TMR1_CMIA1=0x69,IPR_TMR1_CMIB1=0x69,IPR_TMR1_OVI1=0x69,
-IPR_TMR2_CMIA2=0x6A,IPR_TMR2_CMIB2=0x6A,IPR_TMR2_OVI2=0x6A,
-IPR_TMR3_CMIA3=0x6B,IPR_TMR3_CMIB3=0x6B,IPR_TMR3_OVI3=0x6B,
-IPR_DMAC_DMAC0I=0x70,IPR_DMAC_DMAC1I=0x71,IPR_DMAC_DMAC2I=0x72,IPR_DMAC_DMAC3I=0x73,
-IPR_EXDMAC_EXDMAC0I=0x74,IPR_EXDMAC_EXDMAC1I=0x75,
-IPR_SCI0_ERI0=0x80,IPR_SCI0_RXI0=0x80,IPR_SCI0_TXI0=0x80,IPR_SCI0_TEI0=0x80,
-IPR_SCI1_ERI1=0x81,IPR_SCI1_RXI1=0x81,IPR_SCI1_TXI1=0x81,IPR_SCI1_TEI1=0x81,
-IPR_SCI2_ERI2=0x82,IPR_SCI2_RXI2=0x82,IPR_SCI2_TXI2=0x82,IPR_SCI2_TEI2=0x82,
-IPR_SCI3_ERI3=0x83,IPR_SCI3_RXI3=0x83,IPR_SCI3_TXI3=0x83,IPR_SCI3_TEI3=0x83,
-IPR_SCI5_ERI5=0x85,IPR_SCI5_RXI5=0x85,IPR_SCI5_TXI5=0x85,IPR_SCI5_TEI5=0x85,
-IPR_SCI6_ERI6=0x86,IPR_SCI6_RXI6=0x86,IPR_SCI6_TXI6=0x86,IPR_SCI6_TEI6=0x86,
-IPR_RIIC0_ICEEI0=0x88,IPR_RIIC0_ICRXI0=0x89,IPR_RIIC0_ICTXI0=0x8A,IPR_RIIC0_ICTEI0=0x8B,
-IPR_RIIC1_ICEEI1=0x8C,IPR_RIIC1_ICRXI1=0x8D,IPR_RIIC1_ICTXI1=0x8E,IPR_RIIC1_ICTEI1=0x8F,
-IPR_BSC_=0x00,
-IPR_CMT0_=0x04,
-IPR_CMT1_=0x05,
-IPR_CMT2_=0x06,
-IPR_CMT3_=0x07,
-IPR_ETHER_=0x08,
-IPR_RSPI0_=0x14,
-IPR_RSPI1_=0x15,
-IPR_CAN0_=0x18,
-IPR_WDT_=0x40,
-IPR_AD0_=0x44,
-IPR_AD1_=0x45,
-IPR_S12AD_=0x48,
-IPR_MTU1_TGI=0x53,
-IPR_MTU1_TCI=0x54,
-IPR_MTU2_TGI=0x55,
-IPR_MTU2_TCI=0x56,
-IPR_MTU3_TGI=0x57,
-IPR_MTU4_TGI=0x59,
-IPR_MTU5_=0x5B,
-IPR_MTU5_TGI=0x5B,
-IPR_MTU7_TGI=0x5E,
-IPR_MTU7_TCI=0x5F,
-IPR_MTU8_TGI=0x60,
-IPR_MTU8_TCI=0x61,
-IPR_MTU9_TGI=0x62,
-IPR_MTU10_TGI=0x64,
-IPR_MTU11_=0x66,
-IPR_MTU11_TGI=0x66,
-IPR_POE_=0x67,
-IPR_POE_OEI=0x67,
-IPR_TMR0_=0x68,
-IPR_TMR1_=0x69,
-IPR_TMR2_=0x6A,
-IPR_TMR3_=0x6B,
-IPR_SCI0_=0x80,
-IPR_SCI1_=0x81,
-IPR_SCI2_=0x82,
-IPR_SCI3_=0x83,
-IPR_SCI5_=0x85,
-IPR_SCI6_=0x86
-};
-
-#define	IEN_BSC_BUSERR		IEN0
-#define	IEN_FCU_FIFERR		IEN5
-#define	IEN_FCU_FRDYI		IEN7
-#define	IEN_ICU_SWINT		IEN3
-#define	IEN_CMT0_CMI0		IEN4
-#define	IEN_CMT1_CMI1		IEN5
-#define	IEN_CMT2_CMI2		IEN6
-#define	IEN_CMT3_CMI3		IEN7
-#define	IEN_ETHER_EINT		IEN0
-#define	IEN_USB0_D0FIFO0	IEN4
-#define	IEN_USB0_D1FIFO0	IEN5
-#define	IEN_USB0_USBI0		IEN6
-#define	IEN_USB1_D0FIFO1	IEN0
-#define	IEN_USB1_D1FIFO1	IEN1
-#define	IEN_USB1_USBI1		IEN2
-#define	IEN_RSPI0_SPEI0		IEN4
-#define	IEN_RSPI0_SPRI0		IEN5
-#define	IEN_RSPI0_SPTI0		IEN6
-#define	IEN_RSPI0_SPII0		IEN7
-#define	IEN_RSPI1_SPEI1		IEN0
-#define	IEN_RSPI1_SPRI1		IEN1
-#define	IEN_RSPI1_SPTI1		IEN2
-#define	IEN_RSPI1_SPII1		IEN3
-#define	IEN_CAN0_ERS0		IEN0
-#define	IEN_CAN0_RXF0		IEN1
-#define	IEN_CAN0_TXF0		IEN2
-#define	IEN_CAN0_RXM0		IEN3
-#define	IEN_CAN0_TXM0		IEN4
-#define	IEN_RTC_PRD			IEN6
-#define	IEN_RTC_CUP			IEN7
-#define	IEN_ICU_IRQ0		IEN0
-#define	IEN_ICU_IRQ1		IEN1
-#define	IEN_ICU_IRQ2		IEN2
-#define	IEN_ICU_IRQ3		IEN3
-#define	IEN_ICU_IRQ4		IEN4
-#define	IEN_ICU_IRQ5		IEN5
-#define	IEN_ICU_IRQ6		IEN6
-#define	IEN_ICU_IRQ7		IEN7
-#define	IEN_ICU_IRQ8		IEN0
-#define	IEN_ICU_IRQ9		IEN1
-#define	IEN_ICU_IRQ10		IEN2
-#define	IEN_ICU_IRQ11		IEN3
-#define	IEN_ICU_IRQ12		IEN4
-#define	IEN_ICU_IRQ13		IEN5
-#define	IEN_ICU_IRQ14		IEN6
-#define	IEN_ICU_IRQ15		IEN7
-#define	IEN_USB_USBR0		IEN2
-#define	IEN_USB_USBR1		IEN3
-#define	IEN_RTC_ALM			IEN4
-#define	IEN_WDT_WOVI		IEN0
-#define	IEN_AD0_ADI0		IEN2
-#define	IEN_AD1_ADI1		IEN3
-#define	IEN_S12AD_ADI		IEN6
-#define	IEN_MTU0_TGIA0		IEN2
-#define	IEN_MTU0_TGIB0		IEN3
-#define	IEN_MTU0_TGIC0		IEN4
-#define	IEN_MTU0_TGID0		IEN5
-#define	IEN_MTU0_TCIV0		IEN6
-#define	IEN_MTU0_TGIE0		IEN7
-#define	IEN_MTU0_TGIF0		IEN0
-#define	IEN_MTU1_TGIA1		IEN1
-#define	IEN_MTU1_TGIB1		IEN2
-#define	IEN_MTU1_TCIV1		IEN3
-#define	IEN_MTU1_TCIU1		IEN4
-#define	IEN_MTU2_TGIA2		IEN5
-#define	IEN_MTU2_TGIB2		IEN6
-#define	IEN_MTU2_TCIV2		IEN7
-#define	IEN_MTU2_TCIU2		IEN0
-#define	IEN_MTU3_TGIA3		IEN1
-#define	IEN_MTU3_TGIB3		IEN2
-#define	IEN_MTU3_TGIC3		IEN3
-#define	IEN_MTU3_TGID3		IEN4
-#define	IEN_MTU3_TCIV3		IEN5
-#define	IEN_MTU4_TGIA4		IEN6
-#define	IEN_MTU4_TGIB4		IEN7
-#define	IEN_MTU4_TGIC4		IEN0
-#define	IEN_MTU4_TGID4		IEN1
-#define	IEN_MTU4_TCIV4		IEN2
-#define	IEN_MTU5_TGIU5		IEN3
-#define	IEN_MTU5_TGIV5		IEN4
-#define	IEN_MTU5_TGIW5		IEN7
-#define	IEN_MTU6_TGIA6		IEN6
-#define	IEN_MTU6_TGIB6		IEN7
-#define	IEN_MTU6_TGIC6		IEN0
-#define	IEN_MTU6_TGID6		IEN1
-#define	IEN_MTU6_TCIV6		IEN2
-#define	IEN_MTU6_TGIE6		IEN3
-#define	IEN_MTU6_TGIF6		IEN4
-#define	IEN_MTU7_TGIA7		IEN5
-#define	IEN_MTU7_TGIB7		IEN6
-#define	IEN_MTU7_TCIV7		IEN7
-#define	IEN_MTU7_TCIU7		IEN0
-#define	IEN_MTU8_TGIA8		IEN1
-#define	IEN_MTU8_TGIB8		IEN2
-#define	IEN_MTU8_TCIV8		IEN3
-#define	IEN_MTU8_TCIU8		IEN4
-#define	IEN_MTU9_TGIA9		IEN5
-#define	IEN_MTU9_TGIB9		IEN6
-#define	IEN_MTU9_TGIC9		IEN7
-#define	IEN_MTU9_TGID9		IEN0
-#define	IEN_MTU9_TCIV9		IEN1
-#define	IEN_MTU10_TGIA10	IEN2
-#define	IEN_MTU10_TGIB10	IEN3
-#define	IEN_MTU10_TGIC10	IEN4
-#define	IEN_MTU10_TGID10	IEN5
-#define	IEN_MTU10_TCIV10	IEN6
-#define	IEN_MTU11_TGIU11	IEN7
-#define	IEN_MTU11_TGIV11	IEN0
-#define	IEN_MTU11_TGIW11	IEN1
-#define	IEN_POE_OEI1		IEN2
-#define	IEN_POE_OEI2		IEN3
-#define	IEN_POE_OEI3		IEN4
-#define	IEN_POE_OEI4		IEN5
-#define	IEN_TMR0_CMIA0		IEN6
-#define	IEN_TMR0_CMIB0		IEN7
-#define	IEN_TMR0_OVI0		IEN0
-#define	IEN_TMR1_CMIA1		IEN1
-#define	IEN_TMR1_CMIB1		IEN2
-#define	IEN_TMR1_OVI1		IEN3
-#define	IEN_TMR2_CMIA2		IEN4
-#define	IEN_TMR2_CMIB2		IEN5
-#define	IEN_TMR2_OVI2		IEN6
-#define	IEN_TMR3_CMIA3		IEN7
-#define	IEN_TMR3_CMIB3		IEN0
-#define	IEN_TMR3_OVI3		IEN1
-#define	IEN_DMAC_DMAC0I		IEN6
-#define	IEN_DMAC_DMAC1I		IEN7
-#define	IEN_DMAC_DMAC2I		IEN0
-#define	IEN_DMAC_DMAC3I		IEN1
-#define	IEN_EXDMAC_EXDMAC0I	IEN2
-#define	IEN_EXDMAC_EXDMAC1I	IEN3
-#define	IEN_SCI0_ERI0		IEN6
-#define	IEN_SCI0_RXI0		IEN7
-#define	IEN_SCI0_TXI0		IEN0
-#define	IEN_SCI0_TEI0		IEN1
-#define	IEN_SCI1_ERI1		IEN2
-#define	IEN_SCI1_RXI1		IEN3
-#define	IEN_SCI1_TXI1		IEN4
-#define	IEN_SCI1_TEI1		IEN5
-#define	IEN_SCI2_ERI2		IEN6
-#define	IEN_SCI2_RXI2		IEN7
-#define	IEN_SCI2_TXI2		IEN0
-#define	IEN_SCI2_TEI2		IEN1
-#define	IEN_SCI3_ERI3		IEN2
-#define	IEN_SCI3_RXI3		IEN3
-#define	IEN_SCI3_TXI3		IEN4
-#define	IEN_SCI3_TEI3		IEN5
-#define	IEN_SCI5_ERI5		IEN2
-#define	IEN_SCI5_RXI5		IEN3
-#define	IEN_SCI5_TXI5		IEN4
-#define	IEN_SCI5_TEI5		IEN5
-#define	IEN_SCI6_ERI6		IEN6
-#define	IEN_SCI6_RXI6		IEN7
-#define	IEN_SCI6_TXI6		IEN0
-#define	IEN_SCI6_TEI6		IEN1
-#define	IEN_RIIC0_ICEEI0	IEN6
-#define	IEN_RIIC0_ICRXI0	IEN7
-#define	IEN_RIIC0_ICTXI0	IEN0
-#define	IEN_RIIC0_ICTEI0	IEN1
-#define	IEN_RIIC1_ICEEI1	IEN2
-#define	IEN_RIIC1_ICRXI1	IEN3
-#define	IEN_RIIC1_ICTXI1	IEN4
-#define	IEN_RIIC1_ICTEI1	IEN5
-
-#define	VECT_BSC_BUSERR		16
-#define	VECT_FCU_FIFERR		21
-#define	VECT_FCU_FRDYI		23
-#define	VECT_ICU_SWINT		27
-#define	VECT_CMT0_CMI0		28
-#define	VECT_CMT1_CMI1		29
-#define	VECT_CMT2_CMI2		30
-#define	VECT_CMT3_CMI3		31
-#define	VECT_ETHER_EINT		32
-#define	VECT_USB0_D0FIFO0	36
-#define	VECT_USB0_D1FIFO0	37
-#define	VECT_USB0_USBI0		38
-#define	VECT_USB1_D0FIFO1	40
-#define	VECT_USB1_D1FIFO1	41
-#define	VECT_USB1_USBI1		42
-#define	VECT_RSPI0_SPEI0	44
-#define	VECT_RSPI0_SPRI0	45
-#define	VECT_RSPI0_SPTI0	46
-#define	VECT_RSPI0_SPII0	47
-#define	VECT_RSPI1_SPEI1	48
-#define	VECT_RSPI1_SPRI1	49
-#define	VECT_RSPI1_SPTI1	50
-#define	VECT_RSPI1_SPII1	51
-#define	VECT_CAN0_ERS0		56
-#define	VECT_CAN0_RXF0		57
-#define	VECT_CAN0_TXF0		58
-#define	VECT_CAN0_RXM0		59
-#define	VECT_CAN0_TXM0		60
-#define	VECT_RTC_PRD		62
-#define	VECT_RTC_CUP		63
-#define	VECT_ICU_IRQ0		64
-#define	VECT_ICU_IRQ1		65
-#define	VECT_ICU_IRQ2		66
-#define	VECT_ICU_IRQ3		67
-#define	VECT_ICU_IRQ4		68
-#define	VECT_ICU_IRQ5		69
-#define	VECT_ICU_IRQ6		70
-#define	VECT_ICU_IRQ7		71
-#define	VECT_ICU_IRQ8		72
-#define	VECT_ICU_IRQ9		73
-#define	VECT_ICU_IRQ10		74
-#define	VECT_ICU_IRQ11		75
-#define	VECT_ICU_IRQ12		76
-#define	VECT_ICU_IRQ13		77
-#define	VECT_ICU_IRQ14		78
-#define	VECT_ICU_IRQ15		79
-#define	VECT_USB_USBR0		90
-#define	VECT_USB_USBR1		91
-#define	VECT_RTC_ALM		92
-#define	VECT_WDT_WOVI		96
-#define	VECT_AD0_ADI0		98
-#define	VECT_AD1_ADI1		99
-#define	VECT_S12AD_ADI		102
-#define	VECT_MTU0_TGIA0		114
-#define	VECT_MTU0_TGIB0		115
-#define	VECT_MTU0_TGIC0		116
-#define	VECT_MTU0_TGID0		117
-#define	VECT_MTU0_TCIV0		118
-#define	VECT_MTU0_TGIE0		119
-#define	VECT_MTU0_TGIF0		120
-#define	VECT_MTU1_TGIA1		121
-#define	VECT_MTU1_TGIB1		122
-#define	VECT_MTU1_TCIV1		123
-#define	VECT_MTU1_TCIU1		124
-#define	VECT_MTU2_TGIA2		125
-#define	VECT_MTU2_TGIB2		126
-#define	VECT_MTU2_TCIV2		127
-#define	VECT_MTU2_TCIU2		128
-#define	VECT_MTU3_TGIA3		129
-#define	VECT_MTU3_TGIB3		130
-#define	VECT_MTU3_TGIC3		131
-#define	VECT_MTU3_TGID3		132
-#define	VECT_MTU3_TCIV3		133
-#define	VECT_MTU4_TGIA4		134
-#define	VECT_MTU4_TGIB4		135
-#define	VECT_MTU4_TGIC4		136
-#define	VECT_MTU4_TGID4		137
-#define	VECT_MTU4_TCIV4		138
-#define	VECT_MTU5_TGIU5		139
-#define	VECT_MTU5_TGIV5		140
-#define	VECT_MTU5_TGIW5		141
-#define	VECT_MTU6_TGIA6		142
-#define	VECT_MTU6_TGIB6		143
-#define	VECT_MTU6_TGIC6		144
-#define	VECT_MTU6_TGID6		145
-#define	VECT_MTU6_TCIV6		146
-#define	VECT_MTU6_TGIE6		147
-#define	VECT_MTU6_TGIF6		148
-#define	VECT_MTU7_TGIA7		149
-#define	VECT_MTU7_TGIB7		150
-#define	VECT_MTU7_TCIV7		151
-#define	VECT_MTU7_TCIU7		152
-#define	VECT_MTU8_TGIA8		153
-#define	VECT_MTU8_TGIB8		154
-#define	VECT_MTU8_TCIV8		155
-#define	VECT_MTU8_TCIU8		156
-#define	VECT_MTU9_TGIA9		157
-#define	VECT_MTU9_TGIB9		158
-#define	VECT_MTU9_TGIC9		159
-#define	VECT_MTU9_TGID9		160
-#define	VECT_MTU9_TCIV9		161
-#define	VECT_MTU10_TGIA10	162
-#define	VECT_MTU10_TGIB10	163
-#define	VECT_MTU10_TGIC10	164
-#define	VECT_MTU10_TGID10	165
-#define	VECT_MTU10_TCIV10	166
-#define	VECT_MTU11_TGIU11	167
-#define	VECT_MTU11_TGIV11	168
-#define	VECT_MTU11_TGIW11	169
-#define	VECT_POE_OEI1		170
-#define	VECT_POE_OEI2		171
-#define	VECT_POE_OEI3		172
-#define	VECT_POE_OEI4		173
-#define	VECT_TMR0_CMIA0		174
-#define	VECT_TMR0_CMIB0		175
-#define	VECT_TMR0_OVI0		176
-#define	VECT_TMR1_CMIA1		177
-#define	VECT_TMR1_CMIB1		178
-#define	VECT_TMR1_OVI1		179
-#define	VECT_TMR2_CMIA2		180
-#define	VECT_TMR2_CMIB2		181
-#define	VECT_TMR2_OVI2		182
-#define	VECT_TMR3_CMIA3		183
-#define	VECT_TMR3_CMIB3		184
-#define	VECT_TMR3_OVI3		185
-#define	VECT_DMAC_DMAC0I	198
-#define	VECT_DMAC_DMAC1I	199
-#define	VECT_DMAC_DMAC2I	200
-#define	VECT_DMAC_DMAC3I	201
-#define	VECT_EXDMAC_EXDMAC0I	202
-#define	VECT_EXDMAC_EXDMAC1I	203
-#define	VECT_SCI0_ERI0		214
-#define	VECT_SCI0_RXI0		215
-#define	VECT_SCI0_TXI0		216
-#define	VECT_SCI0_TEI0		217
-#define	VECT_SCI1_ERI1		218
-#define	VECT_SCI1_RXI1		219
-#define	VECT_SCI1_TXI1		220
-#define	VECT_SCI1_TEI1		221
-#define	VECT_SCI2_ERI2		222
-#define	VECT_SCI2_RXI2		223
-#define	VECT_SCI2_TXI2		224
-#define	VECT_SCI2_TEI2		225
-#define	VECT_SCI3_ERI3		226
-#define	VECT_SCI3_RXI3		227
-#define	VECT_SCI3_TXI3		228
-#define	VECT_SCI3_TEI3		229
-#define	VECT_SCI5_ERI5		234
-#define	VECT_SCI5_RXI5		235
-#define	VECT_SCI5_TXI5		236
-#define	VECT_SCI5_TEI5		237
-#define	VECT_SCI6_ERI6		238
-#define	VECT_SCI6_RXI6		239
-#define	VECT_SCI6_TXI6		240
-#define	VECT_SCI6_TEI6		241
-#define	VECT_RIIC0_ICEEI0	246
-#define	VECT_RIIC0_ICRXI0	247
-#define	VECT_RIIC0_ICTXI0	248
-#define	VECT_RIIC0_ICTEI0	249
-#define	VECT_RIIC1_ICEEI1	250
-#define	VECT_RIIC1_ICRXI1	251
-#define	VECT_RIIC1_ICTXI1	252
-#define	VECT_RIIC1_ICTEI1	253
-
-#define	MSTP_EXDMAC	SYSTEM.MSTPCRA.BIT.MSTPA29
-#define	MSTP_DMAC	SYSTEM.MSTPCRA.BIT.MSTPA28
-#define	MSTP_DMAC0	SYSTEM.MSTPCRA.BIT.MSTPA28
-#define	MSTP_DMAC1	SYSTEM.MSTPCRA.BIT.MSTPA28
-#define	MSTP_DMAC2	SYSTEM.MSTPCRA.BIT.MSTPA28
-#define	MSTP_DMAC3	SYSTEM.MSTPCRA.BIT.MSTPA28
-#define	MSTP_DTC	SYSTEM.MSTPCRA.BIT.MSTPA28
-#define	MSTP_AD0	SYSTEM.MSTPCRA.BIT.MSTPA23
-#define	MSTP_AD1	SYSTEM.MSTPCRA.BIT.MSTPA22
-#define	MSTP_DA		SYSTEM.MSTPCRA.BIT.MSTPA19
-#define	MSTP_S12AD	SYSTEM.MSTPCRA.BIT.MSTPA17
-#define	MSTP_CMT0	SYSTEM.MSTPCRA.BIT.MSTPA15
-#define	MSTP_CMT1	SYSTEM.MSTPCRA.BIT.MSTPA15
-#define	MSTP_CMT2	SYSTEM.MSTPCRA.BIT.MSTPA14
-#define	MSTP_CMT3	SYSTEM.MSTPCRA.BIT.MSTPA14
-#define	MSTP_PPG0	SYSTEM.MSTPCRA.BIT.MSTPA11
-#define	MSTP_PPG1	SYSTEM.MSTPCRA.BIT.MSTPA10
-#define	MSTP_MTUA	SYSTEM.MSTPCRA.BIT.MSTPA9
-#define	MSTP_MTU0	SYSTEM.MSTPCRA.BIT.MSTPA9
-#define	MSTP_MTU1	SYSTEM.MSTPCRA.BIT.MSTPA9
-#define	MSTP_MTU2	SYSTEM.MSTPCRA.BIT.MSTPA9
-#define	MSTP_MTU3	SYSTEM.MSTPCRA.BIT.MSTPA9
-#define	MSTP_MTU4	SYSTEM.MSTPCRA.BIT.MSTPA9
-#define	MSTP_MTU5	SYSTEM.MSTPCRA.BIT.MSTPA9
-#define	MSTP_MTUB	SYSTEM.MSTPCRA.BIT.MSTPA8
-#define	MSTP_MTU6	SYSTEM.MSTPCRA.BIT.MSTPA8
-#define	MSTP_MTU7	SYSTEM.MSTPCRA.BIT.MSTPA8
-#define	MSTP_MTU8	SYSTEM.MSTPCRA.BIT.MSTPA8
-#define	MSTP_MTU9	SYSTEM.MSTPCRA.BIT.MSTPA8
-#define	MSTP_MTU10	SYSTEM.MSTPCRA.BIT.MSTPA8
-#define	MSTP_MTU11	SYSTEM.MSTPCRA.BIT.MSTPA8
-#define	MSTP_TMR0	SYSTEM.MSTPCRA.BIT.MSTPA5
-#define	MSTP_TMR1	SYSTEM.MSTPCRA.BIT.MSTPA5
-#define	MSTP_TMR01	SYSTEM.MSTPCRA.BIT.MSTPA5
-#define	MSTP_TMR2	SYSTEM.MSTPCRA.BIT.MSTPA4
-#define	MSTP_TMR3	SYSTEM.MSTPCRA.BIT.MSTPA4
-#define	MSTP_TMR23	SYSTEM.MSTPCRA.BIT.MSTPA4
-#define	MSTP_SCI0	SYSTEM.MSTPCRB.BIT.MSTPB31
-#define	MSTP_SMCI0	SYSTEM.MSTPCRB.BIT.MSTPB31
-#define	MSTP_SCI1	SYSTEM.MSTPCRB.BIT.MSTPB30
-#define	MSTP_SMCI1	SYSTEM.MSTPCRB.BIT.MSTPB30
-#define	MSTP_SCI2	SYSTEM.MSTPCRB.BIT.MSTPB29
-#define	MSTP_SMCI2	SYSTEM.MSTPCRB.BIT.MSTPB29
-#define	MSTP_SCI3	SYSTEM.MSTPCRB.BIT.MSTPB28
-#define	MSTP_SMCI3	SYSTEM.MSTPCRB.BIT.MSTPB28
-#define	MSTP_SCI5	SYSTEM.MSTPCRB.BIT.MSTPB26
-#define	MSTP_SMCI5	SYSTEM.MSTPCRB.BIT.MSTPB26
-#define	MSTP_SCI6	SYSTEM.MSTPCRB.BIT.MSTPB25
-#define	MSTP_SMCI6	SYSTEM.MSTPCRB.BIT.MSTPB25
-#define	MSTP_CRC	SYSTEM.MSTPCRB.BIT.MSTPB23
-#define	MSTP_RIIC0	SYSTEM.MSTPCRB.BIT.MSTPB21
-#define	MSTP_RIIC1	SYSTEM.MSTPCRB.BIT.MSTPB20
-#define	MSTP_USB0	SYSTEM.MSTPCRB.BIT.MSTPB19
-#define	MSTP_USB1	SYSTEM.MSTPCRB.BIT.MSTPB18
-#define	MSTP_RSPI0	SYSTEM.MSTPCRB.BIT.MSTPB17
-#define	MSTP_RSPI1	SYSTEM.MSTPCRB.BIT.MSTPB16
-#define	MSTP_EDMAC	SYSTEM.MSTPCRB.BIT.MSTPB15
-#define	MSTP_CAN0	SYSTEM.MSTPCRB.BIT.MSTPB0
-#define	MSTP_RAM0	SYSTEM.MSTPCRC.BIT.MSTPC1
-#define	MSTP_RAM1	SYSTEM.MSTPCRC.BIT.MSTPC0
-
-#define	__IR( x )		ICU.IR[ IR ## x ].BIT.IR
-#define	 _IR( x )		__IR( x )
-#define	  IR( x , y )	_IR( _ ## x ## _ ## y )
-#define	__DTCE( x )		ICU.DTCER[ DTCE ## x ].BIT.DTCE
-#define	 _DTCE( x )		__DTCE( x )
-#define	  DTCE( x , y )	_DTCE( _ ## x ## _ ## y )
-#define	__IEN( x )		ICU.IER[ IER ## x ].BIT.IEN ## x
-#define	 _IEN( x )		__IEN( x )
-#define	  IEN( x , y )	_IEN( _ ## x ## _ ## y )
-#define	__IPR( x )		ICU.IPR[ IPR ## x ].BIT.IPR
-#define	 _IPR( x )		__IPR( x )
-#define	  IPR( x , y )	_IPR( _ ## x ## _ ## y )
-#define	__VECT( x )		VECT ## x
-#define	 _VECT( x )		__VECT( x )
-#define	  VECT( x , y )	_VECT( _ ## x ## _ ## y )
-#define	__MSTP( x )		MSTP ## x
-#define	 _MSTP( x )		__MSTP( x )
-#define	  MSTP( x )		_MSTP( _ ## x )
-
-#define	AD0		(*(volatile struct st_ad       *)0x88040)
-#define	AD1		(*(volatile struct st_ad       *)0x88060)
-#define	BSC		(*(volatile struct st_bsc      *)0x81300)
-#define	CAN0	(*(volatile struct st_can      *)0x90200)
-#define	CMT		(*(volatile struct st_cmt      *)0x88000)
-#define	CMT0	(*(volatile struct st_cmt0     *)0x88002)
-#define	CMT1	(*(volatile struct st_cmt0     *)0x88008)
-#define	CMT2	(*(volatile struct st_cmt0     *)0x88012)
-#define	CMT3	(*(volatile struct st_cmt0     *)0x88018)
-#define	CRC		(*(volatile struct st_crc      *)0x88280)
-#define	DA		(*(volatile struct st_da       *)0x880C0)
-#define	DMAC	(*(volatile struct st_dmac     *)0x82200)
-#define	DMAC0	(*(volatile struct st_dmac0    *)0x82000)
-#define	DMAC1	(*(volatile struct st_dmac1    *)0x82040)
-#define	DMAC2	(*(volatile struct st_dmac1    *)0x82080)
-#define	DMAC3	(*(volatile struct st_dmac1    *)0x820C0)
-#define	DTC		(*(volatile struct st_dtc      *)0x82400)
-#define	EDMAC	(*(volatile struct st_edmac    *)0xC0000)
-#define	ETHERC	(*(volatile struct st_etherc   *)0xC0100)
-#define	EXDMAC	(*(volatile struct st_exdmac   *)0x82A00)
-#define	EXDMAC0	(*(volatile struct st_exdmac0  *)0x82800)
-#define	EXDMAC1	(*(volatile struct st_exdmac1  *)0x82840)
-#define	FLASH	(*(volatile struct st_flash    *)0x8C288)
-#define	ICU		(*(volatile struct st_icu      *)0x87000)
-#define	IOPORT	(*(volatile struct st_ioport   *)0x8C100)
-#define	IWDT	(*(volatile struct st_iwdt     *)0x88030)
-#define	MTU0	(*(volatile struct st_mtu0     *)0x88700)
-#define	MTU1	(*(volatile struct st_mtu1     *)0x88780)
-#define	MTU2	(*(volatile struct st_mtu2     *)0x88800)
-#define	MTU3	(*(volatile struct st_mtu3     *)0x88600)
-#define	MTU4	(*(volatile struct st_mtu4     *)0x88600)
-#define	MTU5	(*(volatile struct st_mtu5     *)0x88880)
-#define	MTU6	(*(volatile struct st_mtu0     *)0x88B00)
-#define	MTU7	(*(volatile struct st_mtu1     *)0x88B80)
-#define	MTU8	(*(volatile struct st_mtu2     *)0x88C00)
-#define	MTU9	(*(volatile struct st_mtu3     *)0x88A00)
-#define	MTU10	(*(volatile struct st_mtu4     *)0x88A00)
-#define	MTU11	(*(volatile struct st_mtu5     *)0x88C80)
-#define	MTUA	(*(volatile struct st_mtua     *)0x8860A)
-#define	MTUB	(*(volatile struct st_mtua     *)0x88A0A)
-#define	POE		(*(volatile struct st_poe      *)0x88900)
-#define	PORT0	(*(volatile struct st_port0    *)0x8C000)
-#define	PORT1	(*(volatile struct st_port1    *)0x8C001)
-#define	PORT2	(*(volatile struct st_port2    *)0x8C002)
-#define	PORT3	(*(volatile struct st_port3    *)0x8C003)
-#define	PORT4	(*(volatile struct st_port4    *)0x8C004)
-#define	PORT5	(*(volatile struct st_port5    *)0x8C005)
-#define	PORT6	(*(volatile struct st_port6    *)0x8C006)
-#define	PORT7	(*(volatile struct st_port7    *)0x8C007)
-#define	PORT8	(*(volatile struct st_port8    *)0x8C008)
-#define	PORT9	(*(volatile struct st_port9    *)0x8C009)
-#define	PORTA	(*(volatile struct st_porta    *)0x8C00A)
-#define	PORTB	(*(volatile struct st_portb    *)0x8C00B)
-#define	PORTC	(*(volatile struct st_portc    *)0x8C00C)
-#define	PORTD	(*(volatile struct st_portd    *)0x8C00D)
-#define	PORTE	(*(volatile struct st_porte    *)0x8C00E)
-#define	PORTF	(*(volatile struct st_portf    *)0x8C00F)
-#define	PORTG	(*(volatile struct st_portg    *)0x8C010)
-#define	PPG0	(*(volatile struct st_ppg0     *)0x881E6)
-#define	PPG1	(*(volatile struct st_ppg1     *)0x881F0)
-#define	RIIC0	(*(volatile struct st_riic     *)0x88300)
-#define	RIIC1	(*(volatile struct st_riic     *)0x88320)
-#define	RSPI0	(*(volatile struct st_rspi     *)0x88380)
-#define	RSPI1	(*(volatile struct st_rspi     *)0x883A0)
-#define	RTC		(*(volatile struct st_rtc      *)0x8C400)
-#define	S12AD	(*(volatile struct st_s12ad    *)0x89000)
-#define	SCI0	(*(volatile struct st_sci      *)0x88240)
-#define	SCI1	(*(volatile struct st_sci      *)0x88248)
-#define	SCI2	(*(volatile struct st_sci      *)0x88250)
-#define	SCI3	(*(volatile struct st_sci      *)0x88258)
-#define	SCI5	(*(volatile struct st_sci      *)0x88268)
-#define	SCI6	(*(volatile struct st_sci      *)0x88270)
-#define	SMCI0	(*(volatile struct st_smci     *)0x88240)
-#define	SMCI1	(*(volatile struct st_smci     *)0x88248)
-#define	SMCI2	(*(volatile struct st_smci     *)0x88250)
-#define	SMCI3	(*(volatile struct st_smci     *)0x88258)
-#define	SMCI5	(*(volatile struct st_smci     *)0x88268)
-#define	SMCI6	(*(volatile struct st_smci     *)0x88270)
-#define	SYSTEM	(*(volatile struct st_system   *)0x80000)
-#define	TMR0	(*(volatile struct st_tmr0     *)0x88200)
-#define	TMR1	(*(volatile struct st_tmr1     *)0x88201)
-#define	TMR2	(*(volatile struct st_tmr0     *)0x88210)
-#define	TMR3	(*(volatile struct st_tmr1     *)0x88211)
-#define	TMR01	(*(volatile struct st_tmr01    *)0x88204)
-#define	TMR23	(*(volatile struct st_tmr01    *)0x88214)
-#define	USB		(*(volatile struct st_usb      *)0xA0400)
-#define	USB0	(*(volatile struct st_usb0     *)0xA0000)
-#define	USB1	(*(volatile struct st_usb0     *)0xA0200)
-#define	WDT		(*(volatile union un_wdt       *)0x88028)
-#endif
-
diff --git a/os/hal/platforms/Rx62n/mac_lld.c b/os/hal/platforms/Rx62n/mac_lld.c
deleted file mode 100644
index 23788244d..000000000
--- a/os/hal/platforms/Rx62n/mac_lld.c
+++ /dev/null
@@ -1,667 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/mac_lld.c
- * @brief   RX62N low level MAC driver code.
- *
- * @addtogroup MAC
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-#include "mii.h"
-#include "rx62n_mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Ethernet driver 1.
- */
-MACDriver ETHD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
-                                              0x37, 0x01, 0x10};
-
-__attribute__((aligned(16)))
-static rx62n_eth_rx_descriptor_t rd[EDMAC_RECEIVE_DESCRIPTORS];
-__attribute__((aligned(16)))
-static rx62n_eth_tx_descriptor_t td[EDMAC_TRANSMIT_DESCRIPTORS];
-
-__attribute__((aligned(32)))
-static uint8_t rb[EDMAC_RECEIVE_DESCRIPTORS * EDMAC_RECEIVE_BUFFERS_SIZE];
-__attribute__((aligned(32)))
-static uint8_t tb[EDMAC_TRANSMIT_DESCRIPTORS * EDMAC_TRANSMIT_BUFFERS_SIZE];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if !defined(BOARD_PHY_ADDRESS)
-/**
- * @brief   PHY address detection.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- */
-static void mii_find_phy(MACDriver *macp) {
-  uint32_t i;
-#if RX62N_MAC_PHY_TIMEOUT > 0
-  halrtcnt_t start = halGetCounterValue();
-  halrtcnt_t timeout  = start + MS2RTT(RX62N_MAC_PHY_TIMEOUT);
-  while (halIsCounterWithin(start, timeout)) {
-#endif
-    for (i = 0; i < 31; i++) {
-      if ((miiGet(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
-          ((miiGet(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
-        return;
-      }
-    }
-#if RX62N_MAC_PHY_TIMEOUT > 0
-  }
-#endif
-  /* Wrong or defective board.*/
-  chSysHalt();
-}
-#endif
-
-/**
- * @brief   MAC address setup.
- *
- * @param[in] p         pointer to a six bytes buffer containing the MAC
- *                      address
- */
-static void mac_lld_set_address(const uint8_t *p) {
-
-  /* MAC address configuration, only a single address comparator is used,
-     hash table not used.*/
-  ETHERC.MAHR      = ((uint32_t)p[0] << 24) |
-                     ((uint32_t)p[1] << 16) |
-                     ((uint32_t)p[2] << 8) |
-                     ((uint32_t)p[3] << 0);
-  ETHERC.MALR.LONG = ((uint32_t)p[4] << 8) |
-                     ((uint32_t)p[5] << 0);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-static void serve_interrupt_ether1(void) {
-  uint32_t eesr = EDMAC.EESR.LONG;
-
-  if (eesr & (1<<18)) {
-    /* Frame received.*/
-    chSysLockFromIsr();
-    chSemResetI(&ETHD1.rdsem, 0);
-#if MAC_USE_EVENTS
-    chEvtBroadcastI(&ETHD1.rdevent);
-#endif
-    chSysUnlockFromIsr();
-  }
-  if (eesr & (1<<21)) {
-    /* Frame transmitted.*/
-    chSysLockFromIsr();
-    chSemResetI(&ETHD1.tdsem, 0);
-    chSysUnlockFromIsr();
-  }
-  EDMAC.EESR.LONG = 0x47FF0F9F;
-}
-
-CH_IRQ_HANDLER(Excep_ETHER_EINT) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt_ether1();
-
-  CH_IRQ_EPILOGUE();
-}
-
-
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level MAC initialization.
- *
- * @notapi
- */
-void mac_lld_init(void) {
-
-  macObjectInit(&ETHD1);
-  ETHD1.link_up = FALSE;
-
-  /* Selection of the RMII or MII mode based on info exported by board.h.*/
-#if defined(BOARD_PHY_RMII)
-  IOPORT.PFENET.BYTE = (1<<7)|(0<<4)|(1<<1);
-#else
-  IOPORT.PFENET.BYTE = (1<<7)|(1<<4)|(1<<1);
-#endif
-
-  /* MAC clocks temporary activation.*/
-  MSTP(EDMAC) = 0;
-
-  /* Reset of the MAC core.*/
-  EDMAC.EDMR.BIT.SWR = 1;
-  /* TODO: wait 64 cycles, here is 1ms delay */
-  asm volatile ("mov.l   #24000,r2                                  \n\t"
-                "1:                                                 \n\t"
-                "sub     #1,r2                                      \n\t"
-                "bne.b   1b                                         \n\t");
-  EDMAC.EDMR.BIT.DE = 1;
-  /* Clear registers not affected by reset */
-  EDMAC.RMFCR.LONG = 0;
-  EDMAC.TFUCR.LONG = 0;
-  EDMAC.RFOCR.LONG = 0;
-
-  /* PHY address setup.*/
-#if defined(BOARD_PHY_ADDRESS)
-  ETHD1.phyaddr = BOARD_PHY_ADDRESS;
-#else
-  mii_find_phy(&ETHD1);
-#endif
-
-#if defined(BOARD_PHY_RESET)
-  /* PHY board-specific reset procedure.*/
-  BOARD_PHY_RESET();
-#else
-  /* PHY soft reset procedure.*/
-  miiPut(&ETHD1, MII_BMCR, BMCR_RESET);
-#if defined(BOARD_PHY_RESET_DELAY)
-  halPolledDelay(BOARD_PHY_RESET_DELAY);
-#endif
-  while (miiGet(&ETHD1, MII_BMCR) & BMCR_RESET)
-    ;
-#endif
-
-#if RX62N_MAC_ETH1_CHANGE_PHY_STATE
-  /* PHY in power down mode until the driver will be started.*/
-  miiPut(&ETHD1, MII_BMCR, miiGet(&ETHD1, MII_BMCR) | BMCR_PDOWN);
-#endif
-
-  /* MAC clocks stopped again.*/
-  MSTP(EDMAC) = 1;
-}
-
-/**
- * @brief   Configures and activates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_start(MACDriver *macp) {
-  unsigned i;
-
-  /* Resets the state of all descriptors.*/
-  for (i = 0; i < EDMAC_RECEIVE_DESCRIPTORS; i++) {
-    rd[i].rd0 = /*RX62N_RD0_RFP_ONE|*/RX62N_RD0_RACT;
-    rd[i].rd1 = EDMAC_RECEIVE_BUFFERS_SIZE<<16;
-    rd[i].rd2 = (uint32_t)&rb[i * EDMAC_RECEIVE_BUFFERS_SIZE];
-  }
-  rd[i-1].rd0 |= RX62N_RD0_RDLE;
-  macp->rxptr = (rx62n_eth_rx_descriptor_t *)rd;
-  for (i = 0; i < EDMAC_TRANSMIT_DESCRIPTORS; i++) {
-    td[i].td0 = RX62N_TD0_TFP_ONE;
-    td[i].td1 = EDMAC_TRANSMIT_BUFFERS_SIZE<<16;
-    td[i].td2 = (uint32_t)&tb[i * EDMAC_TRANSMIT_BUFFERS_SIZE];
-  }
-  td[i-1].td0 |= RX62N_TD0_TDLE;
-  macp->txptr = (rx62n_eth_tx_descriptor_t *)td;
-
-  /* MAC clocks activation.*/
-  MSTP(EDMAC) = 0;
-
-#if RX62N_MAC_ETH1_CHANGE_PHY_STATE
-  /* PHY in power up mode.*/
-  miiPut(macp, MII_BMCR, miiGet(macp, MII_BMCR) & ~BMCR_PDOWN);
-#endif
-
-  /* MAC configuration.*/
-  ETHERC.RFLR.LONG = RX62N_MAC_BUFFERS_SIZE;
-  /* Clear all status flags.*/
-  ETHERC.ECSR.LONG = 0x37;
-  ETHERC.ECSIPR.LONG = 0;
-  ETHERC.IPGR.LONG = 0x14; /* Initial value.*/
-
-  /* MAC address setup.*/
-  if (macp->config->mac_address == NULL)
-    mac_lld_set_address(default_mac_address);
-  else
-    mac_lld_set_address(macp->config->mac_address);
-
-  /* Transmitter and receiver enabled.
-     Note that the complete setup of the MAC is performed when the link
-     status is detected.*/
-  ETHERC.ECMR.LONG |= (ETHERC_ECMR_RE | ETHERC_ECMR_TE);
-
-  /* ISR vector enabled.*/
-  IEN(ETHER,EINT) = 1;
-  IPR(ETHER,EINT) = RX62N_MAC_ETH1_IRQ_PRIORITY;
-
-  /* DMA configuration:
-     Descriptor list pointers.*/
-  EDMAC.RDLAR = (void *)rd;
-  EDMAC.TDLAR = (void *)td;
-
-  /* Clear all status flags.*/
-  EDMAC.EESR.LONG = 0x47FF0F9F;
-  EDMAC.TFTR.LONG = 0;
-  /* Set FIFO size to 2048.*/
-  EDMAC.FDR.LONG = 0x707;
-  EDMAC.RMCR.LONG = 1;
-  EDMAC.RPADIR.LONG = 0;
-
-  EDMAC.EESIPR.LONG = (1<<21)|(1<<18);
-
-  EDMAC.EDRRR.BIT.RR = 1;
-}
-
-/**
- * @brief   Deactivates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_stop(MACDriver *macp) {
-
-  if (macp->state != MAC_STOP) {
-#if RX62N_MAC_ETH1_CHANGE_PHY_STATE
-    /* PHY in power down mode until the driver will be restarted.*/
-    miiPut(macp, MII_BMCR, miiGet(macp, MII_BMCR) | BMCR_PDOWN);
-#endif
-
-    /* MAC and DMA stopped.*/
-    ETHERC.ECMR.LONG = 0;
-
-    /* MAC clocks stopped.*/
-    MSTP(EDMAC) = 1;
-
-    /* ISR vector disabled.*/
-    IEN(ETHER,EINT) = 0;
-  }
-}
-
-/**
- * @brief   Returns a transmission descriptor.
- * @details One of the available transmission descriptors is locked and
- *          returned.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] tdp      pointer to a @p MACTransmitDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                      MACTransmitDescriptor *tdp) {
-  rx62n_eth_tx_descriptor_t *tdes;
-
-  if (!macp->link_up)
-    return RDY_TIMEOUT;
-
-  chSysLock();
-
-  /* Get Current TX descriptor.*/
-  tdes = macp->txptr;
-
-  /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
-     another thread.*/
-  if ( (tdes->td0 & RX62N_TD0_TACT) || (tdes->td0 & RX62N_TD0_TLOCKED) ) {
-    chSysUnlock();
-    return RDY_TIMEOUT;
-  }
-
-  /* Marks the current descriptor as locked using a reserved bit.*/
-  tdes->td0 |= RX62N_TD0_TLOCKED;
-
-  /* Next TX descriptor to use.*/
-  if (++macp->txptr >= &td[RX62N_MAC_TRANSMIT_BUFFERS]) {
-    macp->txptr = &td[0];
-  }
-
-  chSysUnlock();
-
-  /* Set the buffer size and configuration.*/
-  tdp->offset   = 0;
-  tdp->size     = RX62N_MAC_BUFFERS_SIZE;
-  tdp->physdesc = tdes;
-
-  return RDY_OK;
-}
-
-/**
- * @brief   Releases a transmit descriptor and starts the transmission of the
- *          enqueued data as a single frame.
- *
- * @param[in] tdp       the pointer to the @p MACTransmitDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
-
-  chSysLock();
-
-  /* Unlocks the descriptor and returns it to the DMA engine.*/
-  tdp->physdesc->td1 = tdp->offset<<16;
-  tdp->physdesc->td0 &= ~RX62N_TD0_TLOCKED;
-  tdp->physdesc->td0 |= RX62N_TD0_TACT;
-  if (EDMAC.EDTRR.BIT.TR == 0)
-    EDMAC.EDTRR.BIT.TR = 1;
-
-  chSysUnlock();
-}
-
-/**
- * @brief   Cleans an incomplete frame.
- *
- * @param[in] from      the start position of the incomplete frame
- */
-static void cleanup(MACDriver *macp, rx62n_eth_rx_descriptor_t *from) {
-
-  while (from != macp->rxptr) {
-    from->rd0 = (from->rd0 & RX62N_RD0_RDLE) | RX62N_RD0_RACT;
-    if (++from >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
-      from = rd;
-  }
-}
-
-/**
- * @brief   Returns a receive descriptor.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] rdp      pointer to a @p MACReceiveDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                     MACReceiveDescriptor *rdp) {
-
-  unsigned n;
-  rx62n_eth_rx_descriptor_t *edp;
-  n = EDMAC_RECEIVE_DESCRIPTORS;
-  chSysLock();
-
-  /*
-   * Skips active buffers, if any.
-   */
-skip:
-  while ((n > 0) && (macp->rxptr->rd0 & RX62N_RD0_RACT)) {
-    if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
-      macp->rxptr = rd;
-    n--;
-  }
-#if 0
-  /*
-   * Skips fragments, if any, cleaning them up.
-   */
-  while ((n > 0) && !(macp->rxptr->rd0 & RX62N_RD0_RACT) &&
-                    !(macp->rxptr->rd0 & RX62N_RD0_RFP_SOF)) {
-    macp->rxptr->rd0 = (macp->rxptr->rd0 & RX62N_RD0_RDLE) | RX62N_RD0_RACT;
-    if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
-      macp->rxptr = rd;
-    n--;
-  }
-#endif
-  /*
-   * Now compute the total frame size skipping eventual incomplete frames
-   * or holes...
-   */
-restart:
-  edp = macp->rxptr;
-  while (n > 0) {
-
-    if (macp->rxptr->rd0 & RX62N_RD0_RACT) {
-      /* Empty buffer for some reason... cleaning up the incomplete frame.*/
-      cleanup(macp, edp);
-      goto skip;
-    }
-    if ( ( macp->rxptr->rd0 & (RX62N_RD0_RFP_EOF|RX62N_RD0_RFE) )
-          == (RX62N_RD0_RFP_EOF|RX62N_RD0_RFE) ) {
-      /* End Of Frame found, but erroneous, so cleaning.*/
-      if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
-        macp->rxptr = rd;
-      n++;
-      cleanup(macp, edp);
-      goto skip;
-    }
-    /*
-     * End Of Frame found.
-     */
-    if (macp->rxptr->rd0 & RX62N_RD0_RFP_EOF) {
-      rdp->offset = 0;
-      rdp->size = macp->rxptr->rd1 & 0xFFFF;
-      rdp->physdesc = edp;
-      if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
-        macp->rxptr = rd;
-      if (EDMAC.EDRRR.BIT.RR == 0)
-        EDMAC.EDRRR.BIT.RR = 1;
-      chSysUnlock();
-      return RDY_OK;
-    }
-
-    if ( (macp->rxptr != edp) && (macp->rxptr->rd0 & RX62N_RD0_RFP_MASK) ) {
-      /* Found another start or ... cleaning up the incomplete frame.*/
-      cleanup(macp, edp);
-      goto restart;     /* Another start buffer for some reason... */
-    }
-
-    if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
-      macp->rxptr = rd;
-    n--;
-  }
-  if (EDMAC.EDRRR.BIT.RR == 0)
-    EDMAC.EDRRR.BIT.RR = 1;
-  chSysUnlock();
-  return RDY_TIMEOUT;
-}
-
-/**
- * @brief   Releases a receive descriptor.
- * @details The descriptor and its buffer are made available for more incoming
- *          frames.
- *
- * @param[in] rdp       the pointer to the @p MACReceiveDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
-
-  bool_t done;
-  rx62n_eth_rx_descriptor_t *edp = rdp->physdesc;
-
-  unsigned n = EDMAC_RECEIVE_DESCRIPTORS;
-  chSysLock();
-  do {
-    done = ((edp->rd0 & RX62N_RD0_RFP_EOF) != 0);
-    edp->rd1 = EDMAC_RECEIVE_BUFFERS_SIZE<<16;
-    edp->rd0 = (edp->rd0 & RX62N_RD0_RDLE) | RX62N_RD0_RACT;
-    if (++edp >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
-      edp = rd;
-    n--;
-  }
-  while ((n > 0) && !done);
-  chSysUnlock();
-}
-
-/**
- * @brief   Updates and returns the link status.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @return              The link status.
- * @retval TRUE         if the link is active.
- * @retval FALSE        if the link is down.
- *
- * @notapi
- */
-bool_t mac_lld_poll_link_status(MACDriver *macp) {
-  uint32_t ecmr, bmsr, bmcr;
-
-  ecmr = ETHERC.ECMR.LONG;
-
-  /* PHY CR and SR registers read.*/
-  (void)miiGet(macp, MII_BMSR);
-  bmsr = miiGet(macp, MII_BMSR);
-  bmcr = miiGet(macp, MII_BMCR);
-
-  /* Check on auto-negotiation mode.*/
-  if (bmcr & BMCR_ANENABLE) {
-    uint32_t lpa;
-    /* Auto-negotiation must be finished without faults and link established.*/
-    if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
-        (BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
-      return macp->link_up = FALSE;
-
-    /* Auto-negotiation enabled, checks the LPA register.*/
-    lpa = miiGet(macp, MII_LPA);
-
-    /* Check on link speed.*/
-    if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
-      ecmr |= ETHERC_ECMR_RTM;
-    else
-      ecmr &= ~ETHERC_ECMR_RTM;
-
-    /* Check on link mode.*/
-    if (lpa & (LPA_10FULL | LPA_100FULL))
-      ecmr |= ETHERC_ECMR_DM;
-    else
-      ecmr &= ~ETHERC_ECMR_DM;
-  }
-  else {
-    /* Link must be established.*/
-    if (!(bmsr & BMSR_LSTATUS))
-      return macp->link_up = FALSE;
-
-    /* Check on link speed.*/
-    if (bmcr & BMCR_SPEED100)
-      ecmr |= ETHERC_ECMR_RTM;
-    else
-      ecmr &= ~ETHERC_ECMR_RTM;
-
-    /* Check on link mode.*/
-    if (bmcr & BMCR_FULLDPLX)
-      ecmr |= ETHERC_ECMR_DM;
-    else
-      ecmr &= ~ETHERC_ECMR_DM;
-  }
-
-  /* Changes the mode in the MAC.*/
-  ETHERC.ECMR.LONG = ecmr;
-
-  /* Returns the link status.*/
-  return macp->link_up = TRUE;
-}
-
-/**
- * @brief   Writes to a transmit descriptor's stream.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf       pointer to the buffer containing the data to be
- *                      written
- * @param[in] size      number of bytes to be written
- * @return              The number of bytes written into the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if the maximum
- *                      frame size is reached.
- *
- * @notapi
- */
-size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                         uint8_t *buf,
-                                         size_t size) {
-
-  chDbgAssert(!(tdp->physdesc->td0 & RX62N_TD0_TACT),
-              "mac_lld_write_transmit_descriptor(), #1",
-              "attempt to write descriptor already owned by DMA");
-
-  if (size > tdp->size - tdp->offset)
-    size = tdp->size - tdp->offset;
-
-  if (size > 0) {
-    memcpy((uint8_t *)(tdp->physdesc->td2) + tdp->offset, buf, size);
-    tdp->offset += size;
-  }
-
-  return size;
-}
-
-/**
- * @brief   Reads from a receive descriptor's stream.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[in] buf       pointer to the buffer that will receive the read data
- * @param[in] size      number of bytes to be read
- * @return              The number of bytes read from the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if there are
- *                      no more bytes to read.
- *
- * @notapi
- */
-size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                       uint8_t *buf,
-                                       size_t size) {
-/*
-  chDbgAssert(!(rdp->physdesc->rd0 & RX62N_RD0_RACT),
-              "mac_lld_read_receive_descriptor(), #1",
-              "attempt to read descriptor already owned by DMA");
-*/
-  if (size > rdp->size - rdp->offset)
-    size = rdp->size - rdp->offset;
-  if (size > 0) {
-    uint8_t *src = (uint8_t *)(rdp->physdesc->rd2) +
-                   rdp->offset;
-    uint8_t *limit = (uint8_t *)&rb[EDMAC_RECEIVE_DESCRIPTORS * EDMAC_RECEIVE_BUFFERS_SIZE];
-    if (src >= limit) {
-      src -= EDMAC_RECEIVE_DESCRIPTORS * EDMAC_RECEIVE_BUFFERS_SIZE;
-    }
-    if (src + size > limit ) {
-      memcpy(buf, src, (size_t)(limit - src));
-      memcpy(buf + (size_t)(limit - src), rb, size - (size_t)(limit - src));
-    }
-    else
-      memcpy(buf, src, size);
-    rdp->offset += size;
-  }
-  return size;
-
-}
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/mac_lld.h b/os/hal/platforms/Rx62n/mac_lld.h
deleted file mode 100644
index 66e41dad4..000000000
--- a/os/hal/platforms/Rx62n/mac_lld.h
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/mac_lld.h
- * @brief   RX62N low level MAC driver header.
- *
- * @addtogroup MAC
- * @{
- */
-
-#ifndef _MAC_LLD_H_
-#define _MAC_LLD_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   This implementation supports the zero-copy mode API.
- */
-#define MAC_SUPPORTS_ZERO_COPY              FALSE
-
-/**
- * @brief   Every receive buffer must by aligned on 32-bytes boundary
- *          if multiple buffers used.
- */
-#define EDMAC_RECEIVE_BUFFERS_SIZE          (256)    /* Do not modify */
-
-/**
- * @brief   Every transmit buffer must by aligned on 32-bytes boundary
- *          if multiple buffers used.
- */
-#define EDMAC_TRANSMIT_BUFFERS_SIZE                                           \
-    (((RX62N_MAC_BUFFERS_SIZE - 1) | (32 - 1)) + 1)
-
-#define EDMAC_RECEIVE_DESCRIPTORS                                             \
-    (((((RX62N_MAC_BUFFERS_SIZE - 1) | (EDMAC_RECEIVE_BUFFERS_SIZE - 1)) + 1) \
-      / EDMAC_RECEIVE_BUFFERS_SIZE) * RX62N_MAC_RECEIVE_BUFFERS)
-
-#define EDMAC_TRANSMIT_DESCRIPTORS          RX62N_MAC_TRANSMIT_BUFFERS
-
-/**
- * @name    RD0 constants
- * @{
- */
-#define RX62N_RD0_RFS_MASK                  ((1<<27)-1)
-#define RX62N_RD0_RFE                       (1<<27)
-#define RX62N_RD0_RFP_COF                   (0<<28)
-#define RX62N_RD0_RFP_EOF                   (1<<28)
-#define RX62N_RD0_RFP_SOF                   (2<<28)
-#define RX62N_RD0_RFP_ONE                   (3<<28)
-#define RX62N_RD0_RFP_MASK                  (3<<28)
-#define RX62N_RD0_RDLE                      (1<<30)
-#define RX62N_RD0_RACT                      (1<<31)
-/** @} */
-
-/**
- * @name    RD1 constants
- * @{
- */
-#define RX62N_RD1_RBL(x)                    (x>>16)
-#define RX62N_RD1_RFL(x)                    (x&0xFFFF)
-/** @} */
-
-/**
- * @name    TD0 constants
- * @{
- */
-#define RX62N_TD0_TLOCKED                   (1<<9) /* Not an EDMAC flag.*/
-#define RX62N_TD0_TFS_MASK                  ((1<<26)-1)
-#define RX62N_TD0_TWBI                      (1<<26)
-#define RX62N_TD0_TFE                       (1<<27)
-#define RX62N_TD0_TFP_COF                   (0<<28)
-#define RX62N_TD0_TFP_EOF                   (1<<28)
-#define RX62N_TD0_TFP_SOF                   (2<<28)
-#define RX62N_TD0_TFP_ONE                   (3<<28)
-#define RX62N_TD0_TDLE                      (1<<30)
-#define RX62N_TD0_TACT                      (1<<31)
-/** @} */
-
-/**
- * @name    TDES1 constants
- * @{
- */
-/** @} */
-
-#define ETHERC_ECMR_RE                      (1<<6)
-#define ETHERC_ECMR_TE                      (1<<5)
-#define ETHERC_ECMR_ILB                     (1<<3)
-#define ETHERC_ECMR_RTM                     (1<<2)
-#define ETHERC_ECMR_DM                      (1<<1)
-#define ETHERC_ECMR_PRM                     (1<<0)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Number of available transmit buffers.
- */
-#if !defined(RX62N_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
-#define RX62N_MAC_TRANSMIT_BUFFERS          2
-#endif
-
-/**
- * @brief   Number of available receive buffers.
- */
-#if !defined(RX62N_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
-#define RX62N_MAC_RECEIVE_BUFFERS           2
-#endif
-
-/**
- * @brief   Maximum supported frame size.
- */
-#if !defined(RX62N_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define RX62N_MAC_BUFFERS_SIZE              1536
-#endif
-
-
-/**
- * @brief   PHY detection timeout.
- * @details Timeout, in milliseconds, for PHY address detection, if a PHY
- *          is not detected within the timeout then the driver halts during
- *          initialization. This setting applies only if the PHY address is
- *          not explicitly set in the board header file using
- *          @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
- *          single search path is performed.
- */
-#if !defined(RX62N_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
-#define RX62N_MAC_PHY_TIMEOUT               100
-#endif
-
-/**
- * @brief   Change the PHY power state inside the driver.
- */
-#if !defined(RX62N_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
-#define RX62N_MAC_ETH1_CHANGE_PHY_STATE     TRUE
-#endif
-
-/**
- * @brief   ETHD1 interrupt priority level setting.
- */
-#if !defined(RX62N_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define RX62N_MAC_ETH1_IRQ_PRIORITY         5
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (RX62N_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
-#error "RX62N_MAC_PHY_TIMEOUT requires the realtime counter service"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of an RX62N Ethernet receive descriptor.
- */
-typedef struct {
-  volatile uint32_t     rd0;
-  volatile uint32_t     rd1;
-  volatile uint32_t     rd2;
-  volatile uint32_t     pad;
-} rx62n_eth_rx_descriptor_t;
-
-/**
- * @brief   Type of an RX62N Ethernet transmit descriptor.
- */
-typedef struct {
-  volatile uint32_t     td0;
-  volatile uint32_t     td1;
-  volatile uint32_t     td2;
-  volatile uint32_t     pad;
-} rx62n_eth_tx_descriptor_t;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief MAC address.
-   */
-  uint8_t               *mac_address;
-  /* End of the mandatory fields.*/
-} MACConfig;
-
-/**
- * @brief   Structure representing a MAC driver.
- */
-struct MACDriver {
-  /**
-   * @brief Driver state.
-   */
-  macstate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const MACConfig       *config;
-  /**
-   * @brief Transmit semaphore.
-   */
-  Semaphore             tdsem;
-  /**
-   * @brief Receive semaphore.
-   */
-  Semaphore             rdsem;
-#if MAC_USE_EVENTS || defined(__DOXYGEN__)
-  /**
-   * @brief Receive event.
-   */
-  EventSource           rdevent;
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Link status flag.
-   */
-  bool_t                link_up;
-  /**
-   * @brief PHY address.
-   */
-  uint8_t phyaddr;
-  /**
-   * @brief Receive next frame pointer.
-   */
-  rx62n_eth_rx_descriptor_t *rxptr;
-  /**
-   * @brief Transmit next frame pointer.
-   */
-  rx62n_eth_tx_descriptor_t *txptr;
-};
-
-/**
- * @brief   Structure representing a transmit descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current write offset.
-   */
-  size_t                    offset;
-  /**
-   * @brief Available space size.
-   */
-  size_t                    size;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the physical descriptor.
-   */
-  rx62n_eth_tx_descriptor_t *physdesc;
-} MACTransmitDescriptor;
-
-/**
- * @brief   Structure representing a receive descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current read offset.
-   */
-  size_t                offset;
-  /**
-   * @brief Available data size.
-   */
-  size_t                size;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the physical descriptor.
-   */
-  rx62n_eth_rx_descriptor_t *physdesc;
-} MACReceiveDescriptor;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern MACDriver ETHD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void mac_lld_init(void);
-  void mac_lld_start(MACDriver *macp);
-  void mac_lld_stop(MACDriver *macp);
-  msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                        MACTransmitDescriptor *tdp);
-  void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
-  msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                       MACReceiveDescriptor *rdp);
-  void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
-  bool_t mac_lld_poll_link_status(MACDriver *macp);
-  size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                           uint8_t *buf,
-                                           size_t size);
-  size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                         uint8_t *buf,
-                                         size_t size);
-#if MAC_USE_ZERO_COPY
-  uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
-                                            size_t size,
-                                            size_t *sizep);
-  const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
-                                                 size_t *sizep);
-#endif /* MAC_USE_ZERO_COPY */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _MAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/pal_lld.c b/os/hal/platforms/Rx62n/pal_lld.c
deleted file mode 100644
index 2e8f48ffe..000000000
--- a/os/hal/platforms/Rx62n/pal_lld.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/pal_lld.c
- * @brief   RX62N GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void odrset(ioportid_t port, ioportmask_t mask) {
-
-#if defined(RX62N_HAS_PORT0_OD)
-    if ( port == (ioportid_t)&PORT0 )
-    {
-	  port->ODR |= mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORT1_OD)
-    if ( port == (ioportid_t)&PORT1 )
-    {
-	  port->ODR |= mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORT2_OD)
-    if ( port == (ioportid_t)&PORT2 )
-    {
-	  port->ODR |= mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORT3_OD)
-    if ( port == (ioportid_t)&PORT3 )
-    {
-	  port->ODR |= mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTC_OD)
-    if ( port == (ioportid_t)&PORTC )
-    {
-	  port->ODR |= mask;
-	  return;
-    }
-#endif
-}
-
-static void odrclear(ioportid_t port, ioportmask_t mask) {
-
-#if defined(RX62N_HAS_PORT0_OD)
-    if ( port == (ioportid_t)&PORT0 )
-    {
-	  port->ODR &= ~mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORT1_OD)
-    if ( port == (ioportid_t)&PORT1 )
-    {
-	  port->ODR &= ~mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORT2_OD)
-    if ( port == (ioportid_t)&PORT2 )
-    {
-	  port->ODR &= ~mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORT3_OD)
-    if ( port == (ioportid_t)&PORT3 )
-    {
-	  port->ODR &= ~mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTC_OD)
-    if ( port == (ioportid_t)&PORTC )
-    {
-	  port->ODR &= ~mask;
-	  return;
-    }
-#endif
-}
-
-static void pcrset(ioportid_t port, ioportmask_t mask) {
-#if defined(RX62N_HAS_PORTA_PU)
-    if ( port == (ioportid_t)&PORTA )
-    {
-	  port->PCR |= mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTB_PU)
-    if ( port == (ioportid_t)&PORTB )
-    {
-	  port->PCR |= mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTC_PU)
-    if ( port == (ioportid_t)&PORTC )
-    {
-	  port->PCR |= mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTD_PU)
-    if ( port == (ioportid_t)&PORTD )
-    {
-	  port->PCR |= mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTE_PU)
-    if ( port == (ioportid_t)&PORTE )
-    {
-	  port->PCR |= mask;
-	  return;
-    }
-#endif
-}
-
-static void pcrclear(ioportid_t port, ioportmask_t mask) {
-#if defined(RX62N_HAS_PORTA_PU)
-    if ( port == (ioportid_t)&PORTA )
-    {
-	  port->PCR &= ~mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTB_PU)
-    if ( port == (ioportid_t)&PORTB )
-    {
-	  port->PCR &= ~mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTC_PU)
-    if ( port == (ioportid_t)&PORTC )
-    {
-	  port->PCR &= ~mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTD_PU)
-    if ( port == (ioportid_t)&PORTD )
-    {
-	  port->PCR &= ~mask;
-	  return;
-    }
-#endif
-#if defined(RX62N_HAS_PORTE_PU)
-    if ( port == (ioportid_t)&PORTE )
-    {
-	  port->PCR &= ~mask;
-	  return;
-    }
-#endif
-}
-
-static void initgpio(GPIO_TypeDef *gpiop, const rx62n_gpio_setup_t *config) {
-
-  gpiop->DDR     = config->ddr;
-  gpiop->DR      = config->dr;
-  gpiop->ICR     = config->icr;
-/*
-  gpiop->ODR     = config->odr;
-  gpiop->PCR     = config->pcr;
-*/
-  odrset(gpiop, config->odr);
-  pcrset(gpiop, config->pcr);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   RX62N I/O ports configuration.
- * @param[in] config    the RX62N ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  /*
-   * Enables the GPIO related clocks (always enabled).
-   */
-
-  /*
-   * Initial GPIO setup.
-   */
-  initgpio((GPIO_TypeDef *)&PORT0, &config->P0Data);
-  initgpio((GPIO_TypeDef *)&PORT1, &config->P1Data);
-  initgpio((GPIO_TypeDef *)&PORT2, &config->P2Data);
-  initgpio((GPIO_TypeDef *)&PORT3, &config->P3Data);
-  initgpio((GPIO_TypeDef *)&PORT4, &config->P4Data);
-  initgpio((GPIO_TypeDef *)&PORT5, &config->P5Data);
-#if RX62N_HAS_PORT6
-  initgpio((GPIO_TypeDef *)&PORT6, &config->P6Data);
-#endif
-#if RX62N_HAS_PORT7
-  initgpio((GPIO_TypeDef *)&PORT7, &config->P7Data);
-#endif
-#if RX62N_HAS_PORT8
-  initgpio((GPIO_TypeDef *)&PORT8, &config->P8Data);
-#endif
-#if RX62N_HAS_PORT9
-  initgpio((GPIO_TypeDef *)&PORT9, &config->P9Data);
-#endif
-  initgpio((GPIO_TypeDef *)&PORTA, &config->PAData);
-  initgpio((GPIO_TypeDef *)&PORTB, &config->PBData);
-  initgpio((GPIO_TypeDef *)&PORTC, &config->PCData);
-  initgpio((GPIO_TypeDef *)&PORTD, &config->PDData);
-#if RX62N_HAS_PORTE
-  initgpio((GPIO_TypeDef *)&PORTE, &config->PEData);
-#endif
-#if RX62N_HAS_PORTF
-  initgpio((GPIO_TypeDef *)&PORTF, &config->PFData);
-#endif
-#if RX62N_HAS_PORTG
-  initgpio((GPIO_TypeDef *)&PORTG, &config->PGData);
-#endif
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as input (needs external
-               pull-up or pull-down resistor).
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-  case PAL_MODE_UNCONNECTED:
-    port->DDR &= ~mask;
-    pcrclear(port, mask);
-	break;
-  case PAL_MODE_INPUT_PULLUP:
-    port->DDR &= ~mask;
-    pcrset(port, mask);
-    break;
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->DDR |= mask;
-    odrclear(port, mask);
-    break;
-  case PAL_MODE_OUTPUT_OPENDRAIN:
-    port->DDR |= mask;
-    odrset(port, mask);
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/pal_lld.h b/os/hal/platforms/Rx62n/pal_lld.h
deleted file mode 100644
index 86c60a9e2..000000000
--- a/os/hal/platforms/Rx62n/pal_lld.h
+++ /dev/null
@@ -1,452 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/pal_lld.h
- * @brief   RX62N GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_INPUT_PULLDOWN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   RX62N GPIO registers block.
- */
-typedef struct {
-  volatile uint8_t    DDR;
-  uint8_t             wk0[31];
-  union {
-    volatile uint8_t DR;
-      struct {
-        volatile unsigned char B0:1;
-        volatile unsigned char B1:1;
-        volatile unsigned char B2:1;
-        volatile unsigned char B3:1;
-        volatile unsigned char B4:1;
-        volatile unsigned char B5:1;
-        volatile unsigned char B6:1;
-        volatile unsigned char B7:1;
-    } BIT;
-  };
-  uint8_t             wk1[31];
-  volatile uint8_t    PORT;
-  uint8_t             wk2[31];
-  volatile uint8_t    ICR;
-  uint8_t             wk3[31];
-  volatile uint8_t    ODR;
-  uint8_t             wk4[63];
-  volatile uint8_t    PCR;
-} GPIO_TypeDef;
-
-/**
- * @brief   GPIO port setup info.
- */
-typedef struct {
-  /** Initial value for DDR register.*/
-  uint8_t               ddr;
-  /** Initial value for DR register.*/
-  uint8_t               dr;
-  /** Initial value for ICR register.*/
-  uint8_t               icr;
-  /** Initial value for ODR register.*/
-  uint8_t               odr;
-  /** Initial value for PCR register.*/
-  uint8_t               pcr;
-} rx62n_gpio_setup_t;
-
-/**
- * @brief   RX62N GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialize the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-  /** @brief Port 0 setup data.*/
-  rx62n_gpio_setup_t    P0Data;
-  /** @brief Port 1 setup data.*/
-  rx62n_gpio_setup_t    P1Data;
-  /** @brief Port 2 setup data.*/
-  rx62n_gpio_setup_t    P2Data;
-  /** @brief Port 3 setup data.*/
-  rx62n_gpio_setup_t    P3Data;
-  /** @brief Port 4 setup data.*/
-  rx62n_gpio_setup_t    P4Data;
-  /** @brief Port 5 setup data.*/
-  rx62n_gpio_setup_t    P5Data;
-#if RX62N_HAS_PORT6
-  /** @brief Port 6 setup data.*/
-  rx62n_gpio_setup_t    P6Data;
-#endif
-#if RX62N_HAS_PORT7
-  /** @brief Port 7 setup data.*/
-  rx62n_gpio_setup_t    P7Data;
-#endif
-#if RX62N_HAS_PORT8
-  /** @brief Port 8 setup data.*/
-  rx62n_gpio_setup_t    P8Data;
-#endif
-#if RX62N_HAS_PORT9
-  /** @brief Port 9 setup data.*/
-  rx62n_gpio_setup_t    P9Data;
-#endif
-  /** @brief Port A setup data.*/
-  rx62n_gpio_setup_t    PAData;
-  /** @brief Port B setup data.*/
-  rx62n_gpio_setup_t    PBData;
-  /** @brief Port C setup data.*/
-  rx62n_gpio_setup_t    PCData;
-  /** @brief Port D setup data.*/
-  rx62n_gpio_setup_t    PDData;
-#if RX62N_HAS_PORTE
-  /** @brief Port E setup data.*/
-  rx62n_gpio_setup_t    PEData;
-#endif
-#if RX62N_HAS_PORTx
-  /** @brief Port x setup data.*/
-/*  rx62n_gpio_setup_t    PxData;*/
-#endif
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 8
-
-/**
- * @brief   Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ( (ioportmask_t)( ( 1 << PAL_IOPORTS_WIDTH ) - 1 ) )
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint8_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint8_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- *          any assumption about it, use the provided macros when populating
- *          variables of this type.
- */
-typedef GPIO_TypeDef * ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/* The low level driver wraps the definitions already present in the RX62N   */
-/* iodefine_gcc62n.h.                                                        */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port 0 identifier.
- */
-#if RX62N_HAS_PORT0 || defined(__DOXYGEN__)
-#define GPIO0           ((GPIO_TypeDef *)(&PORT0))
-#define IOPORT1         ((GPIO_TypeDef *)(&PORT0))
-#endif
-
-/**
- * @brief   GPIO port 1 identifier.
- */
-#if RX62N_HAS_PORT1 || defined(__DOXYGEN__)
-#define GPIO1           ((GPIO_TypeDef *)(&PORT1))
-#define IOPORT2         ((GPIO_TypeDef *)(&PORT1))
-#endif
-
-/**
- * @brief   GPIO port 2 identifier.
- */
-#if RX62N_HAS_PORT2 || defined(__DOXYGEN__)
-#define GPIO2           ((GPIO_TypeDef *)(&PORT2))
-#define IOPORT3         ((GPIO_TypeDef *)(&PORT2))
-#endif
-
-/**
- * @brief   GPIO port 3 identifier.
- */
-#if RX62N_HAS_PORT3 || defined(__DOXYGEN__)
-#define GPIO3           ((GPIO_TypeDef *)(&PORT3))
-#define IOPORT4         ((GPIO_TypeDef *)(&PORT3))
-#endif
-
-/**
- * @brief   GPIO port 4 identifier.
- */
-#if RX62N_HAS_PORT4 || defined(__DOXYGEN__)
-#define GPIO4           ((GPIO_TypeDef *)(&PORT4))
-#define IOPORT5         ((GPIO_TypeDef *)(&PORT4))
-#endif
-
-/**
- * @brief   GPIO port 5 identifier.
- */
-#if RX62N_HAS_PORT5 || defined(__DOXYGEN__)
-#define GPIO5           ((GPIO_TypeDef *)(&PORT5))
-#define IOPORT6         ((GPIO_TypeDef *)(&PORT5))
-#endif
-
-/**
- * @brief   GPIO port 6 identifier.
- */
-#if RX62N_HAS_PORT6 || defined(__DOXYGEN__)
-#define GPIO6           ((GPIO_TypeDef *)(&PORT6))
-#define IOPORT7         ((GPIO_TypeDef *)(&PORT6))
-#endif
-
-/**
- * @brief   GPIO port 7 identifier.
- */
-#if RX62N_HAS_PORT7 || defined(__DOXYGEN__)
-#define GPIO7           ((GPIO_TypeDef *)(&PORT7))
-#define IOPORT8         ((GPIO_TypeDef *)(&PORT7))
-#endif
-
-/**
- * @brief   GPIO port 8 identifier.
- */
-#if RX62N_HAS_PORT8 || defined(__DOXYGEN__)
-#define GPIO8           ((GPIO_TypeDef *)(&PORT8))
-#define IOPORT9         ((GPIO_TypeDef *)(&PORT8))
-#endif
-
-/**
- * @brief   GPIO port 9 identifier.
- */
-#if RX62N_HAS_PORT9 || defined(__DOXYGEN__)
-#define GPIO9            ((GPIO_TypeDef *)(&PORT9))
-#define IOPORT10         ((GPIO_TypeDef *)(&PORT9))
-#endif
-
-/**
- * @brief   GPIO port 10 identifier.
- */
-#if RX62N_HAS_PORTA || defined(__DOXYGEN__)
-#define GPIO10           ((GPIO_TypeDef *)(&PORTA))
-#define IOPORT11         ((GPIO_TypeDef *)(&PORTA))
-#endif
-
-/**
- * @brief   GPIO port 11 identifier.
- */
-#if RX62N_HAS_PORTB || defined(__DOXYGEN__)
-#define GPIO11           ((GPIO_TypeDef *)(&PORTB))
-#define IOPORT12         ((GPIO_TypeDef *)(&PORTB))
-#endif
-
-/**
- * @brief   GPIO port 12 identifier.
- */
-#if RX62N_HAS_PORTC || defined(__DOXYGEN__)
-#define GPIO12           ((GPIO_TypeDef *)(&PORTC))
-#define IOPORT13         ((GPIO_TypeDef *)(&PORTC))
-#endif
-
-/**
- * @brief   GPIO port 13 identifier.
- */
-#if RX62N_HAS_PORTD || defined(__DOXYGEN__)
-#define GPIO13           ((GPIO_TypeDef *)(&PORTD))
-#define IOPORT14         ((GPIO_TypeDef *)(&PORTD))
-#endif
-
-/**
- * @brief   GPIO port 14 identifier.
- */
-#if RX62N_HAS_PORTE || defined(__DOXYGEN__)
-#define GPIO14           ((GPIO_TypeDef *)(&PORTE))
-#define IOPORT15         ((GPIO_TypeDef *)(&PORTE))
-#endif
-
-/**
- * @brief   GPIO port 15 identifier.
- */
-#if RX62N_HAS_PORTF || defined(__DOXYGEN__)
-#define GPIO15           ((GPIO_TypeDef *)(&PORTF))
-#define IOPORT16         ((GPIO_TypeDef *)(&PORTF))
-#endif
-
-/**
- * @brief   GPIO port 16 identifier.
- */
-#if RX62N_HAS_PORTG || defined(__DOXYGEN__)
-#define GPIO16           ((GPIO_TypeDef *)(&PORTG))
-#define IOPORT17         ((GPIO_TypeDef *)(&PORTG))
-#endif
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO ports subsystem initialization.
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads an I/O port.
- * @details This function is implemented by reading the GPIO IDR register, the
- *          implementation has no side effects.
- * @note    This function is not meant to be invoked directly by the application
- *          code.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->PORT)
-
-/**
- * @brief   Reads the output latch.
- * @details This function is implemented by reading the GPIO ODR register, the
- *          implementation has no side effects.
- * @note    This function is not meant to be invoked directly by the application
- *          code.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->DR)
-
-/**
- * @brief   Writes on a I/O port.
- * @details This function is implemented by writing the GPIO ODR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->DR = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @details This function is implemented by writing the GPIO BSRR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-/*
-#define pal_lld_setport(port, bits)
-*/
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @details This function is implemented by writing the GPIO BSRR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-/*
-#define pal_lld_clearport(port, bits)
-*/
-
-/**
- * @brief   Writes a group of bits.
- * @details This function is implemented by writing the GPIO BSRR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    the group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group
- *                      width are masked.
- *
- * @notapi
- */
-/*
-#define pal_lld_writegroup(port, mask, offset, bits)
-*/
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/rx62n_mii.c b/os/hal/platforms/Rx62n/rx62n_mii.c
deleted file mode 100644
index 5f3496480..000000000
--- a/os/hal/platforms/Rx62n/rx62n_mii.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/rx62n_mii.c
- * @brief   RX62N low level MII driver code.
- *
- * @addtogroup RX62N_MII
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-#include "rx62n_mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if (RX62N_SYSCLK == 96000000)
-__attribute__((always_inline))
-static inline void delay200ns(void) {
-
-  asm volatile ("mov.l   #5,r2                                      \n\t"
-                "1:                                                 \n\t"
-                "sub     #1,r2                                      \n\t"
-                "bne.b   1b                                         \n\t");
-}
-
-__attribute__((always_inline))
-static inline void delay1ms(void) {
-
-  asm volatile ("mov.l   #24000,r2                                  \n\t"
-                "1:                                                 \n\t"
-                "sub     #1,r2                                      \n\t"
-                "bne.b   1b                                         \n\t");
-}
-#else
-#error Adjust delay200ns and delay1ms for RX62N_SYSCLK other than 96MHz.
-#endif
-
-/**
- * @brief   Write 1 bit to SMI bus.
- *
- * @param[in] b         the bit value
- */
-static void smi_bit_w(uint32_t b) {
-  uint32_t pir = PIR_MMD;
-
-  if (b)
-    pir |= PIR_MDO;
-  ETHERC.PIR.LONG = pir;
-  /* wait 10ns */
-  asm volatile("nop");
-  ETHERC.PIR.LONG = pir | PIR_MDC;
-  delay200ns();
-  ETHERC.PIR.LONG = pir;
-  delay200ns();
-}
-
-/**
- * @brief   Read 1 bit from SMI bus.
- *
- * @return              The bit value.
- */
-static uint32_t smi_bit_r(void) {
-  uint32_t pir = 0;
-
-  ETHERC.PIR.LONG = PIR_MDC;
-  delay200ns();
-  ETHERC.PIR.LONG = 0;
-  delay200ns();
-  if (ETHERC.PIR.LONG & PIR_MDI)
-    pir = 1;
-  return pir;
-}
-
-/**
- * @brief   Release SMI bus.
- */
-static void smi_z0(void) {
-
-  ETHERC.PIR.LONG = PIR_MDC;
-  delay200ns();
-  ETHERC.PIR.LONG = 0;
-  delay200ns();
-}
-
-/**
- * @brief   Write up to 32 bits to SMI bus (MSB first).
- *
- * @note    Writing starts from len-1 bit.
- * @param[in] value     value to write
- * @param[in] len       number of bits
- */
-static void smi_write(uint32_t value, uint8_t len) {
-
-  while (len--)
-    smi_bit_w(value & (1<<len) );
-}
-
-/**
- * @brief   Read up to 16 bits from SMI bus (MSB first).
- *
- * @param[in] len       number of bits
- * @return              The bits value.
- */
-static phyreg_t smi_read(uint8_t len) {
-  phyreg_t value = 0;
-
-  while (len--) {
-    value <<= 1;
-    if (smi_bit_r())
-      value |= 1;
-  }
-  return value;
-}
-
-static phyreg_t mii_read_reg(uint8_t phyaddr, phyaddr_t regaddr) {
-  phyreg_t value;
-
-  /* preamble */
-  smi_write(0xFFFFFFFF, 32);
-  /* start of frame */
-  smi_write(1, 2);
-  /* opcode (read) */
-  smi_write(2, 2);
-  /* phy address */
-  smi_write(phyaddr, 5);
-  /* phy register */
-  smi_write(regaddr, 5);
-  /* turn around */
-  smi_z0();
-  /* phy register */
-  value = smi_read(16);
-  /* idle */
-  smi_z0();
-  return value;
-}
-
-static void mii_write_reg(uint8_t phyaddr, phyaddr_t regaddr, phyreg_t value) {
-
-  /* preamble */
-  smi_write(0xFFFFFFFF, 32);
-  /* start of frame */
-  smi_write(1, 2);
-  /* opcode (write) */
-  smi_write(1, 2);
-  /* phy address */
-  smi_write(phyaddr, 5);
-  /* phy register */
-  smi_write(regaddr, 5);
-  /* turn around */
-  smi_write(1, 2);
-  /* phy register */
-  smi_write(value, 16);
-  /* idle */
-  ETHERC.PIR.LONG = 0;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level MII driver initialization.
- *
- * @notapi
- */
-void miiInit(void) {
-
-}
-
-/**
- * @brief   Resets a PHY device.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void miiReset(MACDriver *macp) {
-
-  (void)macp;
-
-  /*
-   * PHY reset by pulsing the RESET_OUT pin.
-   */
-  ETHERC.PIR.LONG = 0;
-  /* Release PHY pins */
-  IOPORT.PFENET.BYTE = 0;
-  /* Pulse RESET_OUT pin */
-  palClearPad(GPIO10, PORTA_ETH_RESETOUT);
-  delay1ms();
-  palSetPad(GPIO10, PORTA_ETH_RESETOUT);
-  delay1ms();
-  /* Enable Ethernet pins, set RMII mode */
-  IOPORT.PFENET.BYTE = (1<<7)|(0<<4)|(1<<1);
-}
-
-/**
- * @brief   Reads a PHY register through the MII interface.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] addr      the register address
- * @return              The register value.
- *
- * @notapi
- */
-phyreg_t miiGet(MACDriver *macp, phyaddr_t regaddr) {
-
-  (void)macp;
-  return mii_read_reg(macp->phyaddr, regaddr);
-}
-
-/**
- * @brief   Writes a PHY register through the MII interface.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] addr      the register address
- * @param[in] value     the new register value
- *
- * @notapi
- */
-void miiPut(MACDriver *macp, phyaddr_t regaddr, phyreg_t value) {
-
-  (void)macp;
-  mii_write_reg(macp->phyaddr, regaddr, value);
-}
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/rx62n_mii.h b/os/hal/platforms/Rx62n/rx62n_mii.h
deleted file mode 100644
index 1c7cfdf58..000000000
--- a/os/hal/platforms/Rx62n/rx62n_mii.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/rx62n_mii.h
- * @brief   RX62N low level MII driver header.
- *
- * @addtogroup RX62N_MII
- * @{
- */
-
-#ifndef _RX62N_MII_H_
-#define _RX62N_MII_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*
- * PIR bit definitions.
- */
-#define PIR_MDC                (1<<0)
-#define PIR_MMD                (1<<1)
-#define PIR_MDO                (1<<2)
-#define PIR_MDI                (1<<3)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a PHY register value.
- */
-typedef uint16_t phyreg_t;
-
-/**
- * @brief   Type of a PHY register address.
- */
-typedef uint8_t phyaddr_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void miiInit(void);
-  void miiReset(MACDriver *macp);
-  phyreg_t miiGet(MACDriver *macp, phyaddr_t addr);
-  void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _RX62N_MII_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/serial_lld.c b/os/hal/platforms/Rx62n/serial_lld.c
deleted file mode 100644
index fc0e5eca2..000000000
--- a/os/hal/platforms/Rx62n/serial_lld.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/serial_lld.c
- * @brief   RX62N low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if RX62N_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-/** @brief UART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-  .sc_speed = SERIAL_DEFAULT_BITRATE,
-  .sc_scr = 0, /* only bits 0-1 used */
-  .sc_smr = 0,
-  .sc_semr = 0,
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   UART initialization.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] config    the architecture-dependent serial driver configuration
- * @todo Test all possible SMR and SEMR clock settings
- */
-static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
-  volatile struct st_sci *u = sdp->uart;
-
-  uint32_t brr;
-
-  u->SCR.BYTE = config->sc_scr & 0x03;
-  u->SMR.BYTE = config->sc_smr;
-  u->SEMR.BYTE = config->sc_semr;
-  brr = ( 32 << ( 2 * ( config->sc_smr & 3 ) ) ) >> ( ( config->sc_semr & 0x10 ) ? 1 : 0 );
-  brr = RX62N_PERCLK / ( brr * config->sc_speed ) - 1;
-  u->BRR = brr;
-  /* TODO: delay 1-bit interval */
-  u->SCR.BYTE |= 0x70;
-}
-
-/**
- * @brief   UART de-initialization.
- *
- * @param[in] u         pointer to an UART I/O block
- */
-static void uart_deinit(volatile struct st_sci *u) {
-
-  u->SCR.BYTE = 0;
-  u->SMR.BYTE = 0;
-  u->SEMR.BYTE = 0;
-  u->BRR = 0;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       communication channel associated to the UART
- * @param[in] err       UART LSR register value
- */
-static void set_error(SerialDriver *sdp, uint32_t err) {
-
-  flagsmask_t sts = 0;
-
-  if (err & SSR_ORER)
-    sts |= SD_OVERRUN_ERROR;
-  if (err & SSR_PER)
-    sts |= SD_PARITY_ERROR;
-  if (err & SSR_FER)
-    sts |= SD_FRAMING_ERROR;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-
-}
-
-#if RX62N_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-/**
- * @brief   Error IRQ handler.
- *
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt_eri(SerialDriver *sdp) {
-  volatile struct st_sci *u = sdp->uart;
-
-  set_error(sdp, u->SSR.BYTE);
-  u->SSR.BYTE &= ~((1<<3)|(1<<4)|(1<<5)); /* clear error flags */
-}
-
-/**
- * @brief   Receive IRQ handler.
- *
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt_rxi(SerialDriver *sdp) {
-  volatile struct st_sci *u = sdp->uart;
-
-  chSysLockFromIsr();
-  sdIncomingDataI(sdp, u->RDR);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Transmit IRQ handler.
- *
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt_txi(SerialDriver *sdp) {
-  volatile struct st_sci *u = sdp->uart;
-  msg_t b;
-
-  chSysLockFromIsr();
-  if (!u->SSR.BIT.TDRE) {
-    /* forced by notify */
-    chSysUnlockFromIsr();
-    return;
-  }
-  b = chOQGetI(&sdp->oqueue);
-  chSysUnlockFromIsr();
-  if (b < Q_OK) {
-    u->SCR.BIT.TIE = 0;
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-    chSysUnlockFromIsr();
-    return;
-  }
-  u->TDR = b;
-}
-
-/**
- * @brief   Transmission end IRQ handler.
- *
- * @param[in] sdp       communication channel associated to the UART
- */
-static void serve_interrupt_tei(SerialDriver *sdp) {
-
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Driver SD1 output notification.
- */
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  SD1.uart->SCR.BIT.TIE = 1;
-  IR(SCI0,TXI0) = 1;  /* Set Interrupt Enable Register */
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 IRQ handler.
- *
- * @isr
- */
-#if RX62N_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Excep_SCI0_ERI0) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt_eri(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-CH_IRQ_HANDLER(Excep_SCI0_RXI0) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt_rxi(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-CH_IRQ_HANDLER(Excep_SCI0_TXI0) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt_txi(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-CH_IRQ_HANDLER(Excep_SCI0_TEI0) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt_tei(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if RX62N_SERIAL_USE_UART0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.uart = &SCI0;
-  PORT2.ICR.BIT.B1 = 1;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if RX62N_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      MSTP(SCI0) = 0; /* Enable SCI0 (cancel module stop state) */
-      IEN(SCI0,RXI0) = 1;
-      IEN(SCI0,TXI0) = 1;
-      IEN(SCI0,ERI0) = 1;
-      IPR(SCI0,TXI0) = RX62N_SERIAL_UART0_IRQ_PRIORITY;
-    }
-#endif
-  }
-  uart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the UART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    uart_deinit(sdp->uart);
-#if RX62N_SERIAL_USE_UART0
-    if (&SD1 == sdp) {
-      IEN(SCI0,RXI0) = 0;
-      IEN(SCI0,TXI0) = 0;
-      IEN(SCI0,ERI0) = 0;
-      MSTP(SCI0) = 1; /* Disable SCI0 (enter module stop state) */
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/serial_lld.h b/os/hal/platforms/Rx62n/serial_lld.h
deleted file mode 100644
index d8ef0c974..000000000
--- a/os/hal/platforms/Rx62n/serial_lld.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/serial_lld.h
- * @brief   RX62N low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define SSR_ORER                           (1<<5)
-#define SSR_FER                            (1<<4)
-#define SSR_PER                            (1<<3)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART0 driver enable switch.
- * @details If set to @p TRUE the support for UART0 is included.
- * @note    The default is @p TRUE .
- */
-#if !defined(RX62N_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define RX62N_SERIAL_USE_UART0             FALSE
-#endif
-
-/**
- * @brief   UART0 PCLK divider.
- */
-#if !defined(RX62N_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__)
-#define RX62N_SERIAL_UART0CLKDIV           1
-#endif
-
-/**
- * @brief   UART0 interrupt priority level setting.
- */
-#if !defined(RX62N_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define RX62N_SERIAL_UART0_IRQ_PRIORITY    3
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   RX62N8 Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the SCR register.
-   */
-  uint8_t                   sc_scr;
-  /**
-   * @brief Initialization value for the SMR register.
-   */
-  uint8_t                   sc_smr;
-  /**
-   * @brief Initialization value for the SEMR register.
-   */
-  uint8_t                   sc_semr;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  volatile struct st_sci    *uart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if RX62N_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/usb_lld.c b/os/hal/platforms/Rx62n/usb_lld.c
deleted file mode 100644
index d80e2e766..000000000
--- a/os/hal/platforms/Rx62n/usb_lld.c
+++ /dev/null
@@ -1,982 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/usb_lld.c
- * @brief   RX62N USB Driver subsystem low level driver source.
- *
- * @addtogroup USB
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   PIPEnCTR register union.
- */
-typedef union {
-  unsigned short WORD;
-  struct {
-    unsigned short PID:2;
-    unsigned short  :3;
-    unsigned short PBUSY:1;
-    unsigned short SQMON:1;
-    unsigned short SQSET:1;
-    unsigned short SQCLR:1;
-    unsigned short ACLRM:1;
-    unsigned short ATREPM:1;
-    unsigned short  :3;
-    unsigned short INBUFM:1;
-    unsigned short BSTS:1;
-  } BIT;
-} pipectr_t;;
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief USB1 driver identifier.*/
-#if RX62N_USE_USB0 || defined(__DOXYGEN__)
-USBDriver USBD1;
-#endif
-
-/** @brief USB2 driver identifier.*/
-#if RX62N_USE_USB1 || defined(__DOXYGEN__)
-USBDriver USBD2;
-#error "USBD2 is not supported yet"
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   EP0 state.
- * @note    It is an union because IN and OUT endpoints are never used at the
- *          same time for EP0.
- */
-static union {
-  /**
-   * @brief   IN EP0 state.
-   */
-  USBInEndpointState in;
-  /**
-   * @brief   OUT EP0 state.
-   */
-  USBOutEndpointState out;
-} ep0_state;
-
-/**
- * @brief   Buffer for the EP0 setup packets.
- */
-static uint8_t ep0setup_buffer[8];
-
-/**
- * @brief   EP0 initialization structure.
- */
-static const USBEndpointConfig ep0config = {
-  USB_EP_MODE_TYPE_CTRL,
-  _usb_ep0setup,
-  _usb_ep0in,
-  _usb_ep0out,
-  USB_EP0_PACKET_SIZE,
-  USB_EP0_PACKET_SIZE,
-  &ep0_state.in,
-  &ep0_state.out,
-  1,
-  ep0setup_buffer
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-pipectr_t usb_pipectr_read(USBDriver *usbp, usbep_t ep) {
-  volatile pipectr_t *pipe = (pipectr_t *)&usbp->usb->PIPE1CTR;
-
-  return pipe[ep-1];
-}
-
-void usb_pipectr_write(USBDriver *usbp, usbep_t ep, uint16_t p) {
-  volatile pipectr_t *pipe = (pipectr_t *)&usbp->usb->PIPE1CTR;
-
-  pipe[ep-1].WORD = p;
-}
-
-/**
- * @brief   Reads from a dedicated packet buffer.
- *
- * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
- * @param[out] buf      buffer where to copy the packet data
- * @param[in] n         maximum number of bytes to copy. This value must
- *                      not exceed the maximum packet size for this endpoint.
- *
- * @notapi
- */
-static void usb_packet_read_to_buffer(USBDriver *usbp, usbep_t ep,
-                                      uint8_t *buf, size_t n) {
-  uint32_t i;
-
-  usbp->epc[ep]->in_state->transmitted = n;
-  if (ep == 0) {
-    for (i = 0; i < n; i++)
-      usbp->epc[ep]->out_state->mode.linear.rxbuf[i] = usbp->usb->CFIFO.BYTE.L;
-  }
-  else {
-    for (i = 0; i < n; i++)
-      usbp->epc[ep]->out_state->mode.linear.rxbuf[i] = usbp->usb->D0FIFO.BYTE.L;
-  }
-}
-
-/**
- * @brief   Reads from a dedicated packet buffer.
- *
- * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
- * @param[in] iqp       pointer to an @p InputQueue object
- * @param[in] n         maximum number of bytes to copy. This value must
- *                      not exceed the maximum packet size for this endpoint.
- *
- * @notapi
- */
-static void usb_packet_read_to_queue(USBDriver *usbp, usbep_t ep, InputQueue *iqp, size_t n) {
-  size_t nhw = n;
-  uint8_t c;
-
-  while (nhw > 0) {
-    if (ep == 0) {
-        c = usbp->usb->CFIFO.BYTE.L;
-    }
-	else {
-        /* ep 1..9 */
-        c = usbp->usb->D0FIFO.BYTE.L;;
-    }
-    *iqp->q_wrptr++ = c;
-    if (iqp->q_wrptr >= iqp->q_top)
-      iqp->q_wrptr = iqp->q_buffer;
-    nhw--;
-  }
-
-  /* Updating queue.*/
-  chSysLockFromIsr();
-  iqp->q_counter += n;
-  while (notempty(&iqp->q_waiting))
-    chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK;
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Writes to a dedicated packet buffer.
- *
- * @param[in] buf       buffer where to fetch the packet data
- * @param[in] n         maximum number of bytes to copy. This value must
- *                      not exceed the maximum packet size for this endpoint.
- *
- * @notapi
- */
-static void usb_packet_write_from_buffer(USBDriver *usbp, usbep_t ep,
-                                         const uint8_t *buf, size_t n) {
-
-  usbp->epc[ep]->in_state->transmitted = n;
-  if (ep == 0) {
-    while (n--) {
-      usbp->usb->CFIFO.BYTE.L = *buf++;
-    }
-  }
-  else {
-    /* ep 1..9 */
-    usbp->usb->D1FIFO.BYTE.L = *buf++;
-  }
-}
-
-/**
- * @brief   Writes to a dedicated packet buffer.
- *
- * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
- * @param[in] buf       buffer where to fetch the packet data
- * @param[in] n         maximum number of bytes to copy. This value must
- *                      not exceed the maximum packet size for this endpoint.
- *
- * @notapi
- */
-static void usb_packet_write_from_queue(USBDriver *usbp, usbep_t ep,
-                                        OutputQueue *oqp, size_t n) {
-  size_t nhw = n;
-  uint8_t c;
-
-  usbp->epc[ep]->in_state->transmitted = n;
-  while (nhw > 0) {
-    c = *oqp->q_rdptr++;;
-    if (ep == 0) {
-      usbp->usb->CFIFO.BYTE.L = c;
-    }
-	else {
-      /* ep 1..9 */
-      usbp->usb->D1FIFO.BYTE.L = c;
-    }
-    c = c;
-    if (oqp->q_rdptr >= oqp->q_top)
-      oqp->q_rdptr = oqp->q_buffer;
-    nhw--;
-  }
-
-  /* Updating queue. Note, the lock is done in this unusual way because this
-     function can be called from both ISR and thread context so the kind
-     of lock function to be invoked cannot be decided beforehand.*/
-
-  /*
-    TODO: port_lock() doesn't work.*/
-  if (port_enabled()) {
-    dbg_enter_lock();
-    chSysLock();
-
-    oqp->q_counter += n;
-    while (notempty(&oqp->q_waiting))
-      chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
-
-    chSysUnlock();
-    dbg_leave_lock();
-  }
-  else {
-    oqp->q_counter += n;
-    while (notempty(&oqp->q_waiting))
-      chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if RX62N_USE_USB0 || defined(__DOXYGEN__)
-void usb_lld_serve_interrupt(USBDriver *usbp) {
-  uint16_t sts0, sts0clr;
-  uint16_t ep = 0;
-
-  sts0 = usbp->usb->INTSTS0.WORD;
-  sts0clr = (~(sts0 & usbp->usb->INTENB0.WORD))|
-    INTSTS0_VALID|INTSTS0_DVST|INTSTS0_CTRT;
-
-  if (sts0 & INTSTS0_RESM) {
-/*    _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESUME);*/
-  }
-
-  /* USB bus WAKEUP condition handling.*/
-/*
-  if (isr & AT91C_UDP_WAKEUP) {
-    _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP);
-  }
-*/
-  /* SOF handling.*/
-/*
-  if (isr & AT91C_UDP_SOFINT) {
-    _usb_isr_invoke_sof_cb(usbp);
-  }
-*/
-  if (sts0 & INTSTS0_DVST) {
-    usbp->usb->INTSTS0.BIT.DVST = 0;
-    switch (INTSTS0_DVSQ(sts0)) {
-      case DVSQ_POWERED:
-        break;
-      case DVSQ_DEFAULT:
-        if ( !(sts0 & INTSTS0_RESM) && (usbp->last_dvst != DVSQ_ADDRESS) &&
-          (usbp->last_dvst != DVSQ_SUSPENDED_DEF)) {
-          _usb_reset(usbp);
-          _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
-        }
-        break;
-      case DVSQ_ADDRESS:
-        break;
-      case DVSQ_CONFIGURED:
-        break;
-      default:
-        /* Default is suspened state */
-        _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND);
-        break;
-    }
-    usbp->last_dvst = INTSTS0_DVSQ(sts0);
-  }
-
-  if (sts0 & INTSTS0_CTRT) {
-    switch (INTSTS0_CTSQ(sts0)) {
-      case CTSQ_IDLE_OR_SETUP:
-        if (usbp->last_ctsq == CTSQ_READ_STATUS) {
-            _usb_isr_invoke_out_cb(usbp, ep);
-        }
-        else if (usbp->last_ctsq == CTSQ_WRITE_STATUS) {
-            _usb_isr_invoke_in_cb(usbp, ep);
-        }
-        else if (usbp->last_ctsq == CTSQ_NODATA_STATUS) {
-            _usb_isr_invoke_in_cb(usbp, ep);
-        }
-        break;
-      default:
-        break;
-    }
-    usbp->last_ctsq = INTSTS0_CTSQ(sts0);
-    usbp->usb->INTSTS0.BIT.CTRT = 0;
-  }
-
-  if (sts0 & INTSTS0_VALID) {
-    usbp->usb->INTSTS0.BIT.VALID = 0;
-    _usb_isr_invoke_setup_cb(usbp, ep);
-    if (INTSTS0_CTSQ(sts0) == CTSQ_NODATA_STATUS) {
-      usbp->usb->DCPCTR.BIT.PID = PID_BUF;
-      usbp->usb->DCPCTR.BIT.CCPL = 1;
-    }
-  }
-
-  if (sts0 & INTSTS0_BRDY) {
-    /* BRDY */
-    uint16_t brdysts = usbp->usb->BRDYSTS.WORD;
-    const USBEndpointConfig *epcp;
-    size_t n;
-    for (ep=0; ep<USB_MAX_ENDPOINTS; ep++) {
-      if (brdysts & (1<<ep)) {
-        epcp = usbp->epc[ep];
-        if (ep == 0) {
-            n = usbp->usb->CFIFOCTR.BIT.DTLN;
-        }
-        else {
-          if (epcp->out_state) {
-            usbp->usb->PIPESEL.BIT.PIPESEL = ep;
-            do {
-              usbp->usb->D0FIFOSEL.WORD = ep;
-            } while (usbp->usb->D0FIFOSEL.WORD != ep);
-            while (!usbp->usb->D0FIFOCTR.BIT.FRDY);
-            n = usbp->usb->D0FIFOCTR.BIT.DTLN;
-          }
-          else {
-            /* in_state */
-            usbp->usb->PIPESEL.BIT.PIPESEL = ep;
-            do {
-              usbp->usb->D1FIFOSEL.WORD = ep;
-            } while (usbp->usb->D1FIFOSEL.WORD != ep);
-            while (!usbp->usb->D1FIFOCTR.BIT.FRDY);
-            n = 0; /* Omit compiler warning */
-          }
-        }
-        if (epcp->out_state) {
-          /* Reads the packet into the defined buffer.*/
-          if (epcp->out_state->rxqueued) {
-            usb_packet_read_to_queue(usbp, ep,
-              epcp->out_state->mode.queue.rxqueue, n);
-          }
-          else {
-            usb_packet_read_to_buffer(usbp, ep,
-              epcp->out_state->mode.linear.rxbuf, n);
-            epcp->out_state->mode.linear.rxbuf  += n;
-          }
-          /* Transaction data updated.*/
-          epcp->out_state->rxcnt                += n;
-          epcp->out_state->rxsize               -= n;
-          epcp->out_state->rxpkts               -= 1;
-          if (epcp->out_state->rxpkts > 0) {
-            /* Transfer not completed, there are more packets to receive.*/
-          }
-          else {
-            /* Transfer completed, invokes the callback.*/
-            /* Set pipe to NAK */
-            usb_pipectr_write(usbp, ep, PID_NAK);
-            _usb_isr_invoke_out_cb(usbp, ep);
-          }
-        }
-        else {
-          epcp->in_state->txcnt  += epcp->in_state->transmitted;
-          epcp->in_state->txsize -= epcp->in_state->transmitted;
-          if (epcp->in_state->txsize > 0) {
-            /* Transfer not completed, there are more packets to send.*/
-            if (epcp->in_state->txsize > epcp->in_maxsize)
-              n = epcp->in_maxsize;
-            else
-              n = epcp->in_state->txsize;
-
-            if (epcp->in_state->txqueued) {
-              usb_packet_write_from_queue(usbp, ep,
-                epcp->in_state->mode.queue.txqueue, n);
-            }
-            else {
-              epcp->in_state->mode.linear.txbuf += epcp->in_state->transmitted;
-              usb_packet_write_from_buffer(usbp, ep,
-                epcp->in_state->mode.linear.txbuf, n);
-            }
-            chSysLockFromIsr();
-            usb_lld_start_in(usbp, ep);
-            chSysUnlockFromIsr();
-          }
-          else {
-            /* Transfer completed, invokes the callback.*/
-            _usb_isr_invoke_in_cb(usbp, ep);
-          }
-        }
-      }
-    }
-    usbp->usb->BRDYSTS.WORD = ~brdysts;
-  }
-  if (sts0 & INTSTS0_BEMP) {
-    /* BEMP */
-    uint16_t bempsts = usbp->usb->BEMPSTS.WORD;
-    const USBEndpointConfig *epcp;
-    size_t n;
-    ep = 0;
-    epcp = usbp->epc[ep];
-    epcp->in_state->txcnt  += epcp->in_state->transmitted;
-    epcp->in_state->txsize -= epcp->in_state->transmitted;
-    if (epcp->in_state->txsize > 0) {
-      /* Transfer not completed, there are more packets to send.*/
-      if (epcp->in_state->txsize > epcp->in_maxsize)
-        n = epcp->in_maxsize;
-      else
-        n = epcp->in_state->txsize;
-      if (epcp->in_state->txqueued) {
-        usb_packet_write_from_queue(usbp, ep,
-        epcp->in_state->mode.queue.txqueue, n);
-      }
-      else {
-        epcp->in_state->mode.linear.txbuf += epcp->in_state->transmitted;
-        usb_packet_write_from_buffer(usbp, ep,
-        epcp->in_state->mode.linear.txbuf, n);
-      }
-      chSysLockFromIsr();
-      usb_lld_start_in(usbp, ep);
-      chSysUnlockFromIsr();
-    }
-    else {
-      /* Transfer completed, invokes the callback.*/
-      _usb_isr_invoke_in_cb(usbp, ep);
-    }
-    usbp->usb->BEMPSTS.WORD = ~bempsts;
-  }
-  usbp->usb->INTSTS0.WORD = sts0clr;
-}
-#endif
-
-/**
- * @brief   USB interrupt handler.
- *
- * @isr
- */
-#if RX62N_USE_USB0 || defined(__DOXYGEN__)
-CH_IRQ_HANDLER(Excep_USB0_USBI0) {
-
-  CH_IRQ_PROLOGUE();
-  usb_lld_serve_interrupt(&USBD1);
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level USB driver initialization.
- *
- * @notapi
- */
-void usb_lld_init(void) {
-
-#if RX62N_USE_USB0 || defined(__DOXYGEN__)
-  usbObjectInit(&USBD1);
-  USBD1.usb = &USB0;
-#endif
-#if RX62N_USE_USB1 || defined(__DOXYGEN__)
-  usbObjectInit(&USBD2);
-  USBD2.usb = &USB1;
-#endif
-}
-
-/**
- * @brief   Configures and activates the USB peripheral.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_start(USBDriver *usbp) {
-
-  if (usbp->state == USB_STOP) {
-    /* Enable USB peripheral. */
-    if (usbp == &USBD1) {
-      MSTP(USB0) = 0;
-      /* Enable GPIO Pull-up */
-      PORT1.DDR.BIT.B4 = 1;
-      /* Enable USB0 pins functions */
-      IOPORT.PFKUSB.BYTE = 0x14;
-    }
-    /* USB clock activation. */
-    usbp->usb->SYSCFG.BIT.SCKE = 1;
-    /* Select function. */
-    usbp->usb->SYSCFG.BIT.DCFM = 0;
-    /* Enable module operation. */
-    usbp->usb->SYSCFG.BIT.USBE = 1;
-
-    /* Default as powered state */
-    usbp->last_dvst = 0;
-    /* Default as idle stage */
-    usbp->last_ctsq = 0;
-    /* Current FIFO */
-    usbp->current_fifo = 0;
-
-    /* Reset procedure enforced on driver start.*/
-    _usb_reset(usbp);
-  }
-  /* Configuration.*/
-}
-
-/**
- * @brief   Deactivates the USB peripheral.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_stop(USBDriver *usbp) {
-
-  /* If in ready state then disables the USB clock.*/
-  if (usbp->state != USB_STOP) {
-/*    IEN(USB0,USBI0) = 0;*/
-    /* Disable module operation. */
-    usbp->usb->SYSCFG.BIT.USBE = 0;
-    /* Disable USB clock.*/
-    usbp->usb->SYSCFG.BIT.SCKE = 0;
-    /* Disable USB peripheral.*/
-    if (usbp == &USBD1) {
-      MSTP(USB0) = 1;
-    }
-  }
-}
-
-/**
- * @brief   USB low level reset routine.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_reset(USBDriver *usbp) {
-  uint16_t ien = 0;
-
-  if (usbp == &USBD1) {
-    IEN(USB0,USBI0) = 0;
-  }
-  /* Disable interrupts */
-  usbp->usb->INTENB0.WORD = 0;
-  usbp->usb->INTENB1.WORD = 0;
-  usbp->usb->BRDYENB.WORD = 0;
-  usbp->usb->NRDYENB.WORD = 0;
-  usbp->usb->BEMPENB.WORD = 0;
-  /* Clear interrupt status bits */
-  usbp->usb->INTSTS0.WORD = (uint16_t)(~(INTSTS0_VALID|INTSTS0_BRDY|
-    INTSTS0_BEMP|INTSTS0_CTRT|INTSTS0_DVST|INTSTS0_SOFR|INTSTS0_RESM|
-    INTSTS0_VBINT));
-  usbp->usb->INTSTS1.WORD = (uint16_t)(~((1<<4)|(1<<5)|(1<<6)|(1<<11)|(1<<12)|
-    (1<<14)|(1<<15)));
-
-  if (usbp->config->sof_cb != NULL) {
-    ien = INTENB0_SOFE;
-  }
-
-  /* EP0 initialization.*/
-  usbp->epc[0] = &ep0config;
-  usbp->usb->DCPCFG.WORD = 0;
-  usbp->usb->DCPMAXP.WORD = USB_EP0_PACKET_SIZE;
-  usbp->usb->CFIFOSEL.WORD = 0;
-
-  /* Enable the USB interrupts - other interrupts get enabled as the
-  enumeration process progresses. */
-  if (usbp == &USBD1) {
-    IEN(USB0,USBI0) = 1;
-    IPR(USB0,USBI0) = RX62N_USB0_IRQ_PRIORITY;
-  }
-  usbp->usb->INTENB0.WORD =
-    INTENB0_BRDYE|
-    INTENB0_BEMPE|
-    INTENB0_CTRE|
-    INTENB0_DVSE|
-    INTENB0_RSME|
-    ien|
-    0;
-  usbp->usb->BRDYENB.BIT.PIPE0BRDYE = 1;
-  usbp->usb->BEMPENB.BIT.PIPE0BEMPE = 1;
-}
-
-/**
- * @brief   Sets the USB address.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_set_address(USBDriver *usbp) {
-
-  (void)usbp;
-}
-
-/**
- * @brief   Finalizes the USB configuration process.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_end_configuration(USBDriver *usbp) {
-
-  (void)usbp;
-}
-
-/**
- * @brief   Enables an endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
-  uint16_t pipecfg;
-  const USBEndpointConfig *epcp = usbp->epc[ep];
-
-  chDbgAssert(ep > 0, "usb_lld_init_endpoint(), #1", "invalid endpoint");
-  if (ep == 0)
-    return;
-
-/*  usbp->usb->CFIFOSEL.BIT.CURPIPE = 0;*/
-  usbp->usb->PIPESEL.WORD = ep;
-
-  /* Set PID to NAK */
-  usb_pipectr_write(usbp, ep, 0);
-  while (usb_pipectr_read(usbp, ep).BIT.PBUSY);
-  usb_pipectr_write(usbp, ep, PIPECTR_SQCLR|PIPECTR_ACLRM);
-  usb_pipectr_write(usbp, ep, 0);
-/*
-  if (epcp->out_cb != NULL)
-    epcp->out_state->currentBank = 0;
-*/
-  /* Setting the endpoint type.*/
-  switch (epcp->ep_mode & USB_EP_MODE_TYPE) {
-  case USB_EP_MODE_TYPE_ISOC:
-    pipecfg = PIPECFG_TYPE_ISO;
-    break;
-  case USB_EP_MODE_TYPE_BULK:
-    pipecfg = PIPECFG_TYPE_BULK;
-    break;
-  case USB_EP_MODE_TYPE_INTR:
-    pipecfg = PIPECFG_TYPE_INT;
-    break;
-  default:
-    /* No control type allowed */
-    chDbgAssert((epcp->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_CTRL,
-      "usb_lld_init_endpoint(), #2", "invalid endpoint");
-    return;
-  }
-
-  /* Set direction */
-  if (epcp->in_cb != NULL) {
-    usbp->usb->PIPEMAXP.BIT.MXPS = epcp->in_maxsize;
-    pipecfg |= PIPECFG_DIR_IN;
-  }
-  else {
-    usbp->usb->PIPEMAXP.BIT.MXPS = epcp->out_maxsize;
-    pipecfg |= PIPECFG_DIR_OUT;
-  }
-  pipecfg |= ep;
-  usbp->usb->PIPECFG.WORD = pipecfg;
-
-  /* Clear interrupt status flag */
-  usbp->usb->BRDYSTS.WORD &= ~(1<<ep);
-  /* Enable interrupts */
-  usbp->usb->BRDYENB.WORD |= (1<<ep);
-
-  usbp->usb->PIPESEL.WORD = 0;
-}
-
-/**
- * @brief   Disables all the active endpoints except the endpoint zero.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_disable_endpoints(USBDriver *usbp) {
-  usbep_t i;
-
-  /* Disable endpoints interrupt */
-  usbp->usb->BRDYENB.WORD = 1;
-  usbp->usb->BRDYSTS.WORD = ~1;
-  /* Disable endpoints */
-  for (i=0; i<USB_MAX_ENDPOINTS; i++) {
-    usbp->usb->PIPESEL.WORD = i+1;
-    usbp->usb->PIPECFG.BIT.EPNUM = 0;
-  }
-  usbp->usb->PIPESEL.WORD = 0;
-  /* Clear FIFO */
-}
-
-/**
- * @brief   Returns the status of an OUT endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED  The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE   The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
-  usbep_t epPrev = usbp->usb->PIPESEL.BIT.PIPESEL;
-
-  if (ep == 0)
-    return EP_STATUS_ACTIVE;
-  usbp->usb->PIPESEL.BIT.PIPESEL = ep;
-  usbep_t epNum = usbp->usb->PIPECFG.BIT.EPNUM;
-  usbp->usb->PIPESEL.BIT.PIPESEL = epPrev;
-  if (epNum) {
-    if (usb_pipectr_read(usbp, ep).BIT.PID & 2)
-      return EP_STATUS_STALLED;
-  }
-  return EP_STATUS_DISABLED;
-}
-
-/**
- * @brief   Returns the status of an IN endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED  The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE   The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
-
-  return usb_lld_get_status_out(usbp, ep);
-}
-
-/**
- * @brief   Reads a setup packet from the dedicated packet buffer.
- * @details This function must be invoked in the context of the @p setup_cb
- *          callback in order to read the received setup packet.
- * @pre     In order to use this function the endpoint must have been
- *          initialized as a control endpoint.
- * @post    The endpoint is ready to accept another packet.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @param[out] buf      buffer where to copy the packet data
- *
- * @notapi
- */
-void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
-
-  buf[0] = usbp->usb->USBREQ.WORD & 0xFF;
-  buf[1] = (usbp->usb->USBREQ.WORD >> 8) & 0xFF;
-  buf[2] = usbp->usb->USBVAL & 0xFF;
-  buf[3] = (usbp->usb->USBVAL >> 8) & 0xFF;
-  buf[4] = usbp->usb->USBINDX & 0xFF;
-  buf[5] = (usbp->usb->USBINDX >> 8) & 0xFF;
-  buf[6] = usbp->usb->USBLENG & 0xFF;
-  buf[7] = (usbp->usb->USBLENG >> 8) & 0xFF;
-}
-
-/**
- * @brief   Prepares for a receive operation.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
-  USBOutEndpointState *osp = usbp->epc[ep]->out_state;
-
-  /* Transfer initialization.*/
-  if (ep == 0) {
-    do {
-      usbp->usb->CFIFOSEL.BIT.ISEL = 0;
-    } while (usbp->usb->CFIFOSEL.BIT.ISEL);
-    usbp->usb->DCPCTR.BIT.PID = PID_BUF;
-    while (!usbp->usb->CFIFOCTR.BIT.FRDY);
-  }
-  if (osp->rxsize == 0)         /* Special case for zero sized packets.*/
-    osp->rxpkts = 1;
-  else
-    osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
-                             usbp->epc[ep]->out_maxsize);
-}
-
-/**
- * @brief   Prepares for a transmit operation.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
-  size_t n;
-  USBInEndpointState *isp = usbp->epc[ep]->in_state;
-
-  /* Transfer initialization.*/
-  n = isp->txsize;
-  if (n > (size_t)usbp->epc[ep]->in_maxsize)
-    n = (size_t)usbp->epc[ep]->in_maxsize;
-  if (ep == 0) {
-    do {
-      usbp->usb->CFIFOSEL.BIT.ISEL = 1;
-    } while (!usbp->usb->CFIFOSEL.BIT.ISEL);
-    usbp->usb->DCPCTR.BIT.PID = PID_BUF;
-    while (!usbp->usb->CFIFOCTR.BIT.FRDY);
-    if (n == 0)
-      usbp->usb->CFIFOCTR.BIT.BCLR = 1;
-  }
-  else {
-    usbp->usb->PIPESEL.BIT.PIPESEL = ep;
-    do {
-        usbp->usb->D1FIFOSEL.WORD = ep;
-    } while (usbp->usb->D1FIFOSEL.WORD != ep);
-    while (!usbp->usb->D1FIFOCTR.BIT.FRDY);
-    do {
-        usb_pipectr_write(usbp, ep, PID_BUF);
-    } while (usb_pipectr_read(usbp, ep).BIT.PID != PID_BUF);
-  }
-  if (isp->txqueued) {
-    usb_packet_write_from_queue(usbp, ep, isp->mode.queue.txqueue, n);
-  }
-  else {
-    usb_packet_write_from_buffer(usbp, ep, isp->mode.linear.txbuf, n);
-  }
-}
-
-/**
- * @brief   Starts a receive operation on an OUT endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
-
-  if (ep)
-    usb_pipectr_write(usbp, ep, PID_BUF);
-}
-
-/**
- * @brief   Starts a transmit operation on an IN endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
-
-  if (ep == 0) {
-    if (usbp->epc[ep]->in_state->transmitted < usbp->epc[ep]->in_maxsize)
-      usbp->usb->CFIFOCTR.BIT.BVAL = 1;
-  }
-  else {
-    if (usbp->epc[ep]->in_state->transmitted < usbp->epc[ep]->in_maxsize)
-      usbp->usb->D1FIFOCTR.BIT.BVAL = 1;
-  }
-}
-
-/**
- * @brief   Brings an OUT endpoint in the stalled state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
-
-  if (ep == 0) {
-    if (usbp->usb->DCPCTR.BIT.PID == PID_NAK)
-      usbp->usb->DCPCTR.BIT.PID = PID_STALL10;
-    else
-      usbp->usb->DCPCTR.BIT.PID = PID_STALL11;
-  }
-  else {
-    if ( usb_pipectr_read(usbp, ep).BIT.PID == PID_NAK)
-      usb_pipectr_write(usbp, ep, PID_STALL10);
-    else
-      usb_pipectr_write(usbp, ep, PID_STALL11);
-  }
-}
-
-/**
- * @brief   Brings an IN endpoint in the stalled state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
-
-  usb_lld_stall_out(usbp, ep);
-}
-
-/**
- * @brief   Brings an OUT endpoint in the active state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
-
-  if (ep == 0) {
-    if (usbp->usb->DCPCTR.BIT.PID == PID_STALL11)
-      usbp->usb->DCPCTR.BIT.PID = PID_STALL10;
-    usbp->usb->DCPCTR.BIT.PID = PID_NAK;
-  }
-  else {
-    if ( usb_pipectr_read(usbp, ep).BIT.PID == PID_STALL11)
-        usb_pipectr_write(usbp, ep, PID_STALL10);
-    usb_pipectr_write(usbp, ep, PID_NAK);
-  }
-}
-
-/**
- * @brief   Brings an IN endpoint in the active state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
-
-  usb_lld_clear_out(usbp, ep);
-}
-
-#endif /* HAL_USE_USB */
-
-/** @} */
diff --git a/os/hal/platforms/Rx62n/usb_lld.h b/os/hal/platforms/Rx62n/usb_lld.h
deleted file mode 100644
index 20f0e130c..000000000
--- a/os/hal/platforms/Rx62n/usb_lld.h
+++ /dev/null
@@ -1,534 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    RX62N/usb_lld.h
- * @brief   RX62N USB Driver subsystem low level driver header.
- *
- * @addtogroup USB
- * @{
- */
-
-#ifndef _USB_LLD_H_
-#define _USB_LLD_H_
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-#include "iodefine_gcc62n.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Maximum endpoint address.
- * @details This value does not include the endpoint 0 which is always present.
- */
-#define USB_MAX_ENDPOINTS                   9
-
-/**
- * @brief   Maximum endpoint 0 size.
- */
-#define USB_EP0_PACKET_SIZE                 64 /* other values doesn't work ? */
-
-/**
- * @brief   Status stage handling method.
- */
-#define USB_EP0_STATUS_STAGE                USB_EP0_STATUS_STAGE_HW
-
-/**
- * @brief   SET_ADDRESS ack handling method.
- */
-#define USB_SET_ADDRESS_ACK_HANDLING        USB_SET_ADDRESS_ACK_HW
-
-/**
- * @brief   This device requires the address change after the status packet.
- */
-#define USB_SET_ADDRESS_MODE                USB_EARLY_SET_ADDRESS
-
-/**
- * @brief   INTSTS0 bit values.
- */
-#define INTSTS0_VBINT                       (1<<15)
-#define INTSTS0_RESM                        (1<<14)
-#define INTSTS0_SOFR                        (1<<13)
-#define INTSTS0_DVST                        (1<<12)
-#define INTSTS0_CTRT                        (1<<11)
-#define INTSTS0_BEMP                        (1<<10)
-#define INTSTS0_NRDY                        (1<<9)
-#define INTSTS0_BRDY                        (1<<8)
-#define INTSTS0_VBSTS                       (1<<7)
-#define INTSTS0_VALID                       (1<<3)
-#define INTSTS0_DVSQ(x)                     ((x>>4)&7)
-#define INTSTS0_CTSQ(x)                     (x&7)
-
-/**
- * @brief   INTENB0 bit values.
- */
-#define INTENB0_VBSE                        (1<<15)
-#define INTENB0_RSME                        (1<<14)
-#define INTENB0_SOFE                        (1<<13)
-#define INTENB0_DVSE                        (1<<12)
-#define INTENB0_CTRE                        (1<<11)
-#define INTENB0_BEMPE                       (1<<10)
-#define INTENB0_NRDYE                       (1<<9)
-#define INTENB0_BRDYE                       (1<<8)
-
-/**
- * @brief   PID values.
- */
-#define PID_NAK                             0
-#define PID_BUF                             1
-#define PID_STALL10                         2
-#define PID_STALL11                         3
-#define PID_MASK                            3
-
-/**
- * @brief   CTSQ state values.
- */
-#define CTSQ_IDLE_OR_SETUP                  0
-#define CTSQ_READ_DATA                      1
-#define CTSQ_READ_STATUS                    2
-#define CTSQ_WRITE_DATA                     3
-#define CTSQ_WRITE_STATUS                   4
-#define CTSQ_NODATA_STATUS                  5
-#define CTSQ_SEQ_ERROR                      6
-
-/**
- * @brief   DVSQ state values.
- */
-#define DVSQ_POWERED                        0
-#define DVSQ_DEFAULT                        1
-#define DVSQ_ADDRESS                        2
-#define DVSQ_CONFIGURED                     3
-#define DVSQ_SUSPENDED_PWR                  4
-#define DVSQ_SUSPENDED_DEF                  5
-#define DVSQ_SUSPENDED_ADR                  6
-#define DVSQ_SUSPENDED_CFG                  7
-
-/**
- * @brief   PIPECFG bit values.
- */
-#define PIPECFG_TYPE_BULK                   (1<<14)
-#define PIPECFG_TYPE_INT                    (2<<14)
-#define PIPECFG_TYPE_ISO                    (3<<14)
-#define PIPECFG_DIR_OUT                     (0<<4)
-#define PIPECFG_DIR_IN                      (1<<4)
-
-/**
- * @brief   PIPEnCTR bit values.
- */
-#define PIPECTR_SQSET                       (1<<7)
-#define PIPECTR_SQCLR                       (1<<8)
-#define PIPECTR_ACLRM                       (1<<9)
-#define PIPECTR_ATREPM                      (1<<10)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of an IN endpoint state structure.
- */
-typedef struct {
-  /**
-   * @brief   Buffer mode, queue or linear.
-   */
-  bool_t                        txqueued;
-  /**
-   * @brief   Requested transmit transfer size.
-   */
-  size_t                        txsize;
-  /**
-   * @brief   Transmitted bytes so far.
-   */
-  size_t                        txcnt;
-  /**
-   * @brief   Transmitted bytes in last transaction (interrupt).
-   */
-  size_t                        transmitted;
-  union {
-    struct {
-      /**
-       * @brief   Pointer to the transmission linear buffer.
-       */
-      const uint8_t             *txbuf;
-    } linear;
-    struct {
-      /**
-       * @brief   Pointer to the output queue.
-       */
-      OutputQueue               *txqueue;
-    } queue;
-    /* End of the mandatory fields.*/
-  } mode;
-} USBInEndpointState;
-
-/**
- * @brief   Type of an OUT endpoint state structure.
- */
-typedef struct {
-  /**
-   * @brief   Buffer mode, queue or linear.
-   */
-  bool_t                        rxqueued;
-  /**
-   * @brief   Requested receive transfer size.
-   */
-  size_t                        rxsize;
-  /**
-   * @brief   Received bytes so far.
-   */
-  size_t                        rxcnt;
-  union {
-    struct {
-      /**
-       * @brief   Pointer to the receive linear buffer.
-       */
-      uint8_t                   *rxbuf;
-    } linear;
-    struct {
-      /**
-       * @brief   Pointer to the input queue.
-       */
-      InputQueue               *rxqueue;
-    } queue;
-  } mode;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Number of packets to receive.
-   */
-  uint16_t                      rxpkts;
-  /**
-   * @brief   Number of bytes last received.
-   */
-  uint16_t                      rxlast;
-} USBOutEndpointState;
-
-/**
- * @brief   Type of an USB endpoint configuration structure.
- * @note    Platform specific restrictions may apply to endpoints.
- */
-typedef struct {
-  /**
-   * @brief   Type and mode of the endpoint.
-   */
-  uint32_t                      ep_mode;
-  /**
-   * @brief   Setup packet notification callback.
-   * @details This callback is invoked when a setup packet has been
-   *          received.
-   * @post    The application must immediately call @p usbReadPacket() in
-   *          order to access the received packet.
-   * @note    This field is only valid for @p USB_EP_MODE_TYPE_CTRL
-   *          endpoints, it should be set to @p NULL for other endpoint
-   *          types.
-   */
-  usbepcallback_t               setup_cb;
-  /**
-   * @brief   IN endpoint notification callback.
-   * @details This field must be set to @p NULL if the IN endpoint is not
-   *          used.
-   */
-  usbepcallback_t               in_cb;
-  /**
-   * @brief   OUT endpoint notification callback.
-   * @details This field must be set to @p NULL if the OUT endpoint is not
-   *          used.
-   */
-  usbepcallback_t               out_cb;
-  /**
-   * @brief   IN endpoint maximum packet size.
-   * @details This field must be set to zero if the IN endpoint is not
-   *          used.
-   */
-  uint16_t                      in_maxsize;
-  /**
-   * @brief   OUT endpoint maximum packet size.
-   * @details This field must be set to zero if the OUT endpoint is not
-   *          used.
-   */
-  uint16_t                      out_maxsize;
-  /**
-   * @brief   @p USBEndpointState associated to the IN endpoint.
-   * @details This structure maintains the state of the IN endpoint.
-   */
-  USBInEndpointState            *in_state;
-  /**
-   * @brief   @p USBEndpointState associated to the OUT endpoint.
-   * @details This structure maintains the state of the OUT endpoint.
-   */
-  USBOutEndpointState           *out_state;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Reserved field, not currently used.
-   * @note    Initialize this field to 1 in order to be forward compatible.
-   */
-  uint16_t                      ep_buffers;
-  /**
-   * @brief   Pointer to a buffer for setup packets.
-   * @details Setup packets require a dedicated 8-bytes buffer, set this
-   *          field to @p NULL for non-control endpoints.
-   */
-  uint8_t                       *setup_buf;
-} USBEndpointConfig;
-
-/**
- * @brief   Type of an USB driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   USB events callback.
-   * @details This callback is invoked when an USB driver event is registered.
-   */
-  usbeventcb_t                  event_cb;
-  /**
-   * @brief   Device GET_DESCRIPTOR request callback.
-   * @note    This callback is mandatory and cannot be set to @p NULL.
-   */
-  usbgetdescriptor_t            get_descriptor_cb;
-  /**
-   * @brief   Requests hook callback.
-   * @details This hook allows to be notified of standard requests or to
-   *          handle non standard requests.
-   */
-  usbreqhandler_t               requests_hook_cb;
-  /**
-   * @brief   Start Of Frame callback.
-   */
-  usbcallback_t                 sof_cb;
-  /* End of the mandatory fields.*/
-} USBConfig;
-
-/**
- * @brief   Structure representing an USB driver.
- */
-struct USBDriver {
-  /**
-   * @brief   Driver state.
-   */
-  usbstate_t                    state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const USBConfig               *config;
-  /**
-   * @brief   Field available to user, it can be used to associate an
-   *          application-defined handler to the USB driver.
-   */
-  void                          *param;
-  /**
-   * @brief   Bit map of the transmitting IN endpoints.
-   */
-  uint16_t                      transmitting;
-  /**
-   * @brief   Bit map of the receiving OUT endpoints.
-   */
-  uint16_t                      receiving;
-  /**
-   * @brief   Active endpoints configurations.
-   */
-  const USBEndpointConfig       *epc[USB_MAX_ENDPOINTS + 1];
-  /**
-   * @brief   Fields available to user, it can be used to associate an
-   *          application-defined handler to an IN endpoint.
-   * @note    The base index is one, the endpoint zero does not have a
-   *          reserved element in this array.
-   */
-  void                          *in_params[USB_MAX_ENDPOINTS];
-  /**
-   * @brief   Fields available to user, it can be used to associate an
-   *          application-defined handler to an OUT endpoint.
-   * @note    The base index is one, the endpoint zero does not have a
-   *          reserved element in this array.
-   */
-  void                          *out_params[USB_MAX_ENDPOINTS];
-  /**
-   * @brief   Endpoint 0 state.
-   */
-  usbep0state_t                 ep0state;
-  /**
-   * @brief   Next position in the buffer to be transferred through endpoint 0.
-   */
-  uint8_t                       *ep0next;
-  /**
-   * @brief   Number of bytes yet to be transferred through endpoint 0.
-   */
-  size_t                        ep0n;
-  /**
-   * @brief   Endpoint 0 end transaction callback.
-   */
-  usbcallback_t                 ep0endcb;
-  /**
-   * @brief   Setup packet buffer.
-   */
-  uint8_t                       setup[8];
-  /**
-   * @brief   Current USB device status.
-   */
-  uint16_t                      status;
-  /**
-   * @brief   Assigned USB address.
-   */
-  uint8_t                       address;
-  /**
-   * @brief   Current USB device configuration.
-   */
-  uint8_t                       configuration;
-#if defined(USB_DRIVER_EXT_FIELDS)
-  USB_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   USB hardware registers pointer.
-   */
-  volatile struct st_usb0       *usb;
-  /**
-   * @brief   Last USB device status.
-   */
-  uint8_t                       last_dvst;
-  /**
-   * @brief   Last USB control stage.
-   */
-  uint8_t                       last_ctsq;
-  /**
-   * @brief   Current FIFO number (D0 or D1).
-   */
-  uint8_t                       current_fifo;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current frame number.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @return              The current frame number.
- *
- * @notapi
- */
-#define usb_lld_get_frame_number(usbp) ((usbp)->usb->FRMNUM.BIT.FRNM)
-
-/**
- * @brief   Returns the exact size of a receive transaction.
- * @details The received size can be different from the size specified in
- *          @p usbStartReceiveI() because the last packet could have a size
- *          different from the expected one.
- * @pre     The OUT endpoint must have been configured in transaction mode
- *          in order to use this function.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              Received data size.
- *
- * @notapi
- */
-#define usb_lld_get_transaction_size(usbp, ep)                              \
-  ((usbp)->epc[ep]->out_state->rxcnt)
-
-/**
- * @brief   Triggers status stage for control endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-#define usb_lld_end_setup(usbp, ep)                                         \
-  ((usbp)->usb->DCPCTR.BIT.CCPL=1)
-
-/**
- * @brief   Returns the exact size of a received packet.
- * @pre     The OUT endpoint must have been configured in packet mode
- *          in order to use this function.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              Received data size.
- *
- * @notapi
- */
-#define  usb_lld_get_packet_size(usbp, ep)                                  \
-  ((size_t)((usbp)->epc[ep]->out_state->rxlast)
-
-
-/**
- * @brief   Connects the USB device.
- *
- * @api
- */
-#define usb_lld_connect_bus(usbp) ((usbp)->usb->SYSCFG.BIT.DPRPU=1)
-
-/**
- * @brief   Disconnect the USB device.
- *
- * @api
- */
-#define usb_lld_disconnect_bus(usbp) ((usbp)->usb->SYSCFG.BIT.DPRPU=0)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if RX62N_USE_USB0 || defined(__DOXYGEN__)
-extern USBDriver USBD1;
-#endif
-
-#if RX62N_USE_USB1 || defined(__DOXYGEN__)
-extern USBDriver USBD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void usb_lld_init(void);
-  void usb_lld_start(USBDriver *usbp);
-  void usb_lld_stop(USBDriver *usbp);
-  void usb_lld_reset(USBDriver *usbp);
-  void usb_lld_set_address(USBDriver *usbp);
-  void usb_lld_end_configuration(USBDriver *usbp);
-  void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
-  void usb_lld_disable_endpoints(USBDriver *usbp);
-  usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
-  usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
-  void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
-  void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
-  void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
-  void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
-  void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_USB */
-
-#endif /* _USB_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.c b/os/hal/platforms/SPC560BCxx/hal_lld.c
deleted file mode 100644
index 5d14daf27..000000000
--- a/os/hal/platforms/SPC560BCxx/hal_lld.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560BCxx/hal_lld.c
- * @brief   SPC560B/Cxx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PIT channel 3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector59) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  /* Resets the PIT channel 3 IRQ flag.*/
-  PIT.CH[0].TFLG.R = 1;
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-  uint32_t reg;
-
-  /* The system is switched to the RUN0 mode, the default for normal
-     operations.*/
-  if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* INTC initialization, software vector mode, 4 bytes vectors, starting
-     at priority 0.*/
-  INTC.MCR.R        = 0;
-  INTC.CPR.R        = 0;
-  INTC.IACKR.R      = (uint32_t)_vectors;
-
-  /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
-     to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
-     modes.*/
-  INTC.PSR[59].R    = SPC5_PIT0_IRQ_PRIORITY;
-  halSPCSetPeripheralClockMode(92,
-                               SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
-  reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
-  PIT.PITMCR.R      = 1;        /* PIT clock enabled, stop while debugging. */
-  PIT.CH[0].LDVAL.R = reg;
-  PIT.CH[0].CVAL.R  = reg;
-  PIT.CH[0].TFLG.R  = 1;        /* Interrupt flag cleared.                  */
-  PIT.CH[0].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */
-}
-
-/**
- * @brief   SPC560B/Cxx clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h and
- *          @p hal_lld.h
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void spc_clock_init(void) {
-
-  /* Waiting for IRC stabilization before attempting anything else.*/
-  while (!ME.GS.B.S_FIRC)
-    ;
-
-#if !SPC5_NO_INIT
-
-#if SPC5_DISABLE_WATCHDOG
-  /* SWT disabled.*/
-  SWT.SR.R = 0xC520;
-  SWT.SR.R = 0xD928;
-  SWT.CR.R = 0xFF00000A;
-#endif
-
-  /* SSCM initialization. Setting up the most restrictive handling of
-     invalid accesses to peripherals.*/
-  SSCM.ERROR.R = 3;                             /* PAE and RAE bits.        */
-
-  /* RGM errors clearing.*/
-  RGM.FES.R         = 0xFFFF;
-  RGM.DES.R         = 0xFFFF;
-
-  /* Oscillators dividers setup.*/
-  CGM.FIRC_CTL.B.RCDIV   = SPC5_IRCDIV_VALUE - 1;
-  CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
-
-  /* The system must be in DRUN mode on entry, if this is not the case then
-     it is considered a serious anomaly.*/
-  if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-#if defined(SPC5_OSC_BYPASS)
-  /* If the board is equipped with an oscillator instead of a xtal then the
-     bypass must be activated.*/
-  CGM.OSC_CTL.B.OSCBYP = TRUE;
-#endif /* SPC5_OSC_BYPASS */
-
-  /* Setting the various dividers and source selectors.*/
-  CGM.SC_DC[0].R    = SPC5_CGM_SC_DC0;
-  CGM.SC_DC[1].R    = SPC5_CGM_SC_DC1;
-  CGM.SC_DC[2].R    = SPC5_CGM_SC_DC2;
-
-  /* Initialization of the FMPLLs settings.*/
-  CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
-                   ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
-                   (SPC5_FMPLL0_NDIV_VALUE << 16);
-  CGM.FMPLL_MR.R = 0;                           /* TODO: Add a setting.     */
-
-  /* Run modes initialization.*/
-  ME.IS.R           = 8;                        /* Resetting I_ICONF status.*/
-  ME.MER.R          = SPC5_ME_ME_BITS;          /* Enabled run modes.       */
-  ME.TEST.R         = SPC5_ME_TEST_MC_BITS;     /* TEST run mode.           */
-  ME.SAFE.R         = SPC5_ME_SAFE_MC_BITS;     /* SAFE run mode.           */
-  ME.DRUN.R         = SPC5_ME_DRUN_MC_BITS;     /* DRUN run mode.           */
-  ME.RUN[0].R       = SPC5_ME_RUN0_MC_BITS;     /* RUN0 run mode.           */
-  ME.RUN[1].R       = SPC5_ME_RUN1_MC_BITS;     /* RUN1 run mode.           */
-  ME.RUN[2].R       = SPC5_ME_RUN2_MC_BITS;     /* RUN2 run mode.           */
-  ME.RUN[3].R       = SPC5_ME_RUN3_MC_BITS;     /* RUN0 run mode.           */
-  ME.HALT0.R        = SPC5_ME_HALT0_MC_BITS;    /* HALT0 run mode.          */
-  ME.STOP0.R        = SPC5_ME_STOP0_MC_BITS;    /* STOP0 run mode.          */
-  ME.STANDBY0.R     = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode.       */
-  if (ME.IS.B.I_CONF) {
-    /* Configuration rejected.*/
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* Peripherals run and low power modes initialization.*/
-  ME.RUNPC[0].R     = SPC5_ME_RUN_PC0_BITS;
-  ME.RUNPC[1].R     = SPC5_ME_RUN_PC1_BITS;
-  ME.RUNPC[2].R     = SPC5_ME_RUN_PC2_BITS;
-  ME.RUNPC[3].R     = SPC5_ME_RUN_PC3_BITS;
-  ME.RUNPC[4].R     = SPC5_ME_RUN_PC4_BITS;
-  ME.RUNPC[5].R     = SPC5_ME_RUN_PC5_BITS;
-  ME.RUNPC[6].R     = SPC5_ME_RUN_PC6_BITS;
-  ME.RUNPC[7].R     = SPC5_ME_RUN_PC7_BITS;
-  ME.LPPC[0].R      = SPC5_ME_LP_PC0_BITS;
-  ME.LPPC[1].R      = SPC5_ME_LP_PC1_BITS;
-  ME.LPPC[2].R      = SPC5_ME_LP_PC2_BITS;
-  ME.LPPC[3].R      = SPC5_ME_LP_PC3_BITS;
-  ME.LPPC[4].R      = SPC5_ME_LP_PC4_BITS;
-  ME.LPPC[5].R      = SPC5_ME_LP_PC5_BITS;
-  ME.LPPC[6].R      = SPC5_ME_LP_PC6_BITS;
-  ME.LPPC[7].R      = SPC5_ME_LP_PC7_BITS;
-
-  /* CFLASH settings calculated for a maximum clock of 64MHz.*/
-  CFLASH.PFCR0.B.BK0_APC  = 2;
-  CFLASH.PFCR0.B.BK0_RWSC = 2;
-  CFLASH.PFCR1.B.BK1_APC  = 2;
-  CFLASH.PFCR1.B.BK1_RWSC = 2;
-
-  /* Switches again to DRUN mode (current mode) in order to update the
-     settings.*/
-  if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-#endif /* !SPC5_NO_INIT */
-}
-
-/**
- * @brief   Switches the system to the specified run mode.
- *
- * @param[in] mode      one of the possible run modes
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   if the switch operation has been completed.
- * @retval CH_FAILED    if the switch operation failed.
- */
-bool_t halSPCSetRunMode(spc5_runmode_t mode) {
-
-  /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
-  ME.IS.R = 5;
-
-  /* Starts a transition process.*/
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
-
-  /* Waits for the mode switch or an error condition.*/
-  while (TRUE) {
-    uint32_t r = ME.IS.R;
-    if (r & 1)
-      return CH_SUCCESS;
-    if (r & 4)
-      return CH_FAILED;
-  }
-}
-
-/**
- * @brief   Changes the clock mode of a peripheral.
- *
- * @param[in] n         index of the @p PCTL register
- * @param[in] pctl      new value for the @p PCTL register
- *
- * @notapi
- */
-void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
-  uint32_t mode;
-
-  ME.PCTL[n].R = pctl;
-  mode = ME.MCTL.B.TARGET_MODE;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
-}
-
-#if !SPC5_NO_INIT || defined(__DOXYGEN__)
-/**
- * @brief   Returns the system clock under the current run mode.
- *
- * @return              The system clock in Hertz.
- */
-uint32_t halSPCGetSystemClock(void) {
-  uint32_t sysclk;
-
-  sysclk = ME.GS.B.S_SYSCLK;
-  switch (sysclk) {
-  case SPC5_ME_GS_SYSCLK_IRC:
-    return SPC5_IRC_CLK;
-  case SPC5_ME_GS_SYSCLK_DIVIRC:
-    return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
-  case SPC5_ME_GS_SYSCLK_XOSC:
-    return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
-  case SPC5_ME_GS_SYSCLK_DIVXOSC:
-    return SPC5_XOSC_CLK;
-  case SPC5_ME_GS_SYSCLK_FMPLL0:
-    return SPC5_FMPLL0_CLK;
-  default:
-    return 0;
-  }
-}
-#endif /* !SPC5_NO_INIT */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h
deleted file mode 100644
index ddf44dff3..000000000
--- a/os/hal/platforms/SPC560BCxx/hal_lld.h
+++ /dev/null
@@ -1,779 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560BCxx/hal_lld.h
- * @brief   SPC560B/Cxx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - SPC5_XOSC_CLK.
- *          - SPC5_OSC_BYPASS (optionally).
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "xpc560bc.h"
-#include "spc560bc_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @name    Platform identification
- * @{
- */
-#define PLATFORM_NAME               "SPC560B/Cxx Car Body and Convenience"
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum XOSC clock frequency.
- */
-#define SPC5_XOSC_CLK_MAX           16000000
-
-/**
- * @brief   Minimum XOSC clock frequency.
- */
-#define SPC5_XOSC_CLK_MIN           4000000
-
-/**
- * @brief   Maximum SXOSC clock frequency.
- */
-#define SPC5_SXOSC_CLK_MAX          40000
-
-/**
- * @brief   Minimum SXOSC clock frequency.
- */
-#define SPC5_SXOSC_CLK_MIN          32000
-
-/**
- * @brief   Maximum FMPLLs input clock frequency.
- */
-#define SPC5_FMPLLIN_MIN            4000000
-
-/**
- * @brief   Maximum FMPLLs input clock frequency.
- */
-#define SPC5_FMPLLIN_MAX            64000000
-
-/**
- * @brief   Maximum FMPLLs VCO clock frequency.
- */
-#define SPC5_FMPLLVCO_MAX           512000000
-
-/**
- * @brief   Maximum FMPLLs VCO clock frequency.
- */
-#define SPC5_FMPLLVCO_MIN           256000000
-
-/**
- * @brief   Maximum FMPLL0 output clock frequency.
- */
-#define SPC5_FMPLL0_CLK_MAX         64000000
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define SPC5_IRC_CLK                16000000    /**< Internal fast RC
-                                                     oscillator.            */
-#define SPC5_SIRC_CLK               128000      /**< Internal RC slow
-                                                     oscillator.            */
-/** @} */
-
-/**
- * @name    FMPLL_CR register bits definitions
- * @{
- */
-#define SPC5_FMPLL_ODF_DIV2         (0U << 24)
-#define SPC5_FMPLL_ODF_DIV4         (1U << 24)
-#define SPC5_FMPLL_ODF_DIV8         (2U << 24)
-#define SPC5_FMPLL_ODF_DIV16        (3U << 24)
-/** @} */
-
-/**
- * @name    ME_GS register bits definitions
- * @{
- */
-#define SPC5_ME_GS_SYSCLK_MASK      (15U << 0)
-#define SPC5_ME_GS_SYSCLK_IRC       (0U << 0)
-#define SPC5_ME_GS_SYSCLK_DIVIRC    (1U << 0)
-#define SPC5_ME_GS_SYSCLK_XOSC      (2U << 0)
-#define SPC5_ME_GS_SYSCLK_DIVXOSC   (3U << 0)
-#define SPC5_ME_GS_SYSCLK_FMPLL0    (4U << 0)
-/** @} */
-
-/**
- * @name    ME_ME register bits definitions
- * @{
- */
-#define SPC5_ME_ME_RESET            (1U << 0)
-#define SPC5_ME_ME_TEST             (1U << 1)
-#define SPC5_ME_ME_SAFE             (1U << 2)
-#define SPC5_ME_ME_DRUN             (1U << 3)
-#define SPC5_ME_ME_RUN0             (1U << 4)
-#define SPC5_ME_ME_RUN1             (1U << 5)
-#define SPC5_ME_ME_RUN2             (1U << 6)
-#define SPC5_ME_ME_RUN3             (1U << 7)
-#define SPC5_ME_ME_HALT0            (1U << 8)
-#define SPC5_ME_ME_STOP0            (1U << 10)
-#define SPC5_ME_ME_STANDBY0         (1U << 13)
-/** @} */
-
-/**
- * @name    ME_xxx_MC registers bits definitions
- * @{
- */
-#define SPC5_ME_MC_SYSCLK_MASK      (15U << 0)
-#define SPC5_ME_MC_SYSCLK(n)        ((n) << 0)
-#define SPC5_ME_MC_SYSCLK_IRC       SPC5_ME_MC_SYSCLK(0)
-#define SPC5_ME_MC_SYSCLK_DIVIRC    SPC5_ME_MC_SYSCLK(1)
-#define SPC5_ME_MC_SYSCLK_XOSC      SPC5_ME_MC_SYSCLK(2)
-#define SPC5_ME_MC_SYSCLK_DIVXOSC   SPC5_ME_MC_SYSCLK(3)
-#define SPC5_ME_MC_SYSCLK_FMPLL0    SPC5_ME_MC_SYSCLK(4)
-#define SPC5_ME_MC_SYSCLK_DISABLED  SPC5_ME_MC_SYSCLK(15)
-#define SPC5_ME_MC_IRCON            (1U << 4)
-#define SPC5_ME_MC_XOSC0ON          (1U << 5)
-#define SPC5_ME_MC_PLL0ON           (1U << 6)
-#define SPC5_ME_MC_CFLAON_MASK      (3U << 16)
-#define SPC5_ME_MC_CFLAON(n)        ((n) << 16)
-#define SPC5_ME_MC_CFLAON_PD        (1U << 16)
-#define SPC5_ME_MC_CFLAON_LP        (2U << 16)
-#define SPC5_ME_MC_CFLAON_NORMAL    (3U << 16)
-#define SPC5_ME_MC_DFLAON_MASK      (3U << 18)
-#define SPC5_ME_MC_DFLAON(n)        ((n) << 18)
-#define SPC5_ME_MC_DFLAON_PD        (1U << 18)
-#define SPC5_ME_MC_DFLAON_LP        (2U << 18)
-#define SPC5_ME_MC_DFLAON_NORMAL    (3U << 18)
-#define SPC5_ME_MC_MVRON            (1U << 20)
-#define SPC5_ME_MC_PDO              (1U << 23)
-/** @} */
-
-/**
- * @name    ME_MCTL register bits definitions
- * @{
- */
-#define SPC5_ME_MCTL_KEY            0x5AF0U
-#define SPC5_ME_MCTL_KEY_INV        0xA50FU
-#define SPC5_ME_MCTL_MODE_MASK      (15U << 28)
-#define SPC5_ME_MCTL_MODE(n)        ((n) << 28)
-/** @} */
-
-/**
- * @name    ME_RUN_PCx registers bits definitions
- * @{
- */
-#define SPC5_ME_RUN_PC_TEST         (1U << 1)
-#define SPC5_ME_RUN_PC_SAFE         (1U << 2)
-#define SPC5_ME_RUN_PC_DRUN         (1U << 3)
-#define SPC5_ME_RUN_PC_RUN0         (1U << 4)
-#define SPC5_ME_RUN_PC_RUN1         (1U << 5)
-#define SPC5_ME_RUN_PC_RUN2         (1U << 6)
-#define SPC5_ME_RUN_PC_RUN3         (1U << 7)
-/** @} */
-
-/**
- * @name    ME_LP_PCx registers bits definitions
- * @{
- */
-#define SPC5_ME_LP_PC_HALT0         (1U << 8)
-#define SPC5_ME_LP_PC_STOP0         (1U << 10)
-#define SPC5_ME_LP_PC_STANDBY0      (1U << 10)
-/** @} */
-
-/**
- * @name    ME_PCTL registers bits definitions
- * @{
- */
-#define SPC5_ME_PCTL_RUN_MASK       (7U << 0)
-#define SPC5_ME_PCTL_RUN(n)         ((n) << 0)
-#define SPC5_ME_PCTL_LP_MASK        (7U << 3)
-#define SPC5_ME_PCTL_LP(n)          ((n) << 3)
-#define SPC5_ME_PCTL_DBG            (1U << 6)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Disables the clocks initialization in the HAL.
- */
-#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
-#define SPC5_NO_INIT                        FALSE
-#endif
-
-/**
- * @brief   Disables the overclock checks.
- */
-#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
-#define SPC5_ALLOW_OVERCLOCK                FALSE
-#endif
-
-/**
- * @brief   Disables the watchdog on start.
- */
-#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
-#define SPC5_DISABLE_WATCHDOG               TRUE
-#endif
-
-/**
- * @brief   FMPLL0 IDF divider value.
- * @note    The default value is calculated for XOSC=8MHz and PHI=64MHz.
- */
-#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_IDF_VALUE               1
-#endif
-
-/**
- * @brief   FMPLL0 NDIV divider value.
- * @note    The default value is calculated for XOSC=8MHz and PHI=64MHz.
- */
-#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_NDIV_VALUE              32
-#endif
-
-/**
- * @brief   FMPLL0 ODF divider value.
- * @note    The default value is calculated for XOSC=8MHz and PHI=64MHz.
- */
-#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_ODF                     SPC5_FMPLL_ODF_DIV4
-#endif
-
-/**
- * @brief   XOSC divider value.
- * @note    The allowed range is 1...32.
- */
-#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_XOSCDIV_VALUE                  1
-#endif
-
-/**
- * @brief   Fast IRC divider value.
- * @note    The allowed range is 1...32.
- */
-#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_IRCDIV_VALUE                   1
-#endif
-
-/**
- * @brief   Peripherals Set 1 clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PERIPHERAL1_CLK_DIV_VALUE      2
-#endif
-
-/**
- * @brief   Peripherals Set 2 clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PERIPHERAL2_CLK_DIV_VALUE      2
-#endif
-
-/**
- * @brief   Peripherals Set 3 clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PERIPHERAL3_CLK_DIV_VALUE      2
-#endif
-
-/**
- * @brief   Active run modes in ME_ME register.
- * @note    Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
- *          is no need to specify them.
- */
-#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_ME_BITS                     (SPC5_ME_ME_RUN1 |              \
-                                             SPC5_ME_ME_RUN2 |              \
-                                             SPC5_ME_ME_RUN3 |              \
-                                             SPC5_ME_ME_HALT0 |             \
-                                             SPC5_ME_ME_STOP0 |             \
-                                             SPC5_ME_ME_STANDBY0)
-#endif
-
-/**
- * @brief   TEST mode settings.
- */
-#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_TEST_MC_BITS                (SPC5_ME_MC_SYSCLK_IRC |        \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   SAFE mode settings.
- */
-#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_SAFE_MC_BITS                (SPC5_ME_MC_PDO)
-#endif
-
-/**
- * @brief   DRUN mode settings.
- */
-#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_DRUN_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN0 mode settings.
- */
-#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN0_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN1 mode settings.
- */
-#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN1_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN2 mode settings.
- */
-#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN2_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN3 mode settings.
- */
-#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN3_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   HALT0 mode settings.
- */
-#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_HALT0_MC_BITS               (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   STOP0 mode settings.
- */
-#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_STOP0_MC_BITS               (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   STANDBY0 mode settings.
- */
-#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_STANDBY0_MC_BITS            (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   Peripheral mode 0 (run mode).
- * @note    Do not change this setting, it is expected to be the "never run"
- *          mode.
- */
-#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC0_BITS                0
-#endif
-
-/**
- * @brief   Peripheral mode 1 (run mode).
- * @note    Do not change this setting, it is expected to be the "always run"
- *          mode.
- */
-#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC1_BITS                (SPC5_ME_RUN_PC_TEST |          \
-                                             SPC5_ME_RUN_PC_SAFE |          \
-                                             SPC5_ME_RUN_PC_DRUN |          \
-                                             SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 2 (run mode).
- * @note    Do not change this setting, it is expected to be the "only during
- *          normal run" mode.
- */
-#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC2_BITS                (SPC5_ME_RUN_PC_DRUN |          \
-                                             SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 3 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC3_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 4 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC4_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 5 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC5_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 6 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC6_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 7 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC7_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 0 (low power mode).
- * @note    Do not change this setting, it is expected to be the "never run"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC0_BITS                 0
-#endif
-
-/**
- * @brief   Peripheral mode 1 (low power mode).
- * @note    Do not change this setting, it is expected to be the "always run"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC1_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0 |          \
-                                             SPC5_ME_LP_PC_STANDBY0)
-#endif
-
-/**
- * @brief   Peripheral mode 2 (low power mode).
- * @note    Do not change this setting, it is expected to be the "halt only"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC2_BITS                 (SPC5_ME_LP_PC_HALT0)
-#endif
-
-/**
- * @brief   Peripheral mode 3 (low power mode).
- * @note    Do not change this setting, it is expected to be the "stop only"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC3_BITS                 (SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 4 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC4_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 5 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC5_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 6 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC6_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 7 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC7_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   PIT channel 0 IRQ priority.
- * @note    This PIT channel is allocated permanently for system tick
- *          generation.
- */
-#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PIT0_IRQ_PRIORITY              4
-#endif
-
-/**
- * @brief   Clock initialization failure hook.
- * @note    The default is to stop the system and let the RTC restart it.
- * @note    The hook code must not return.
- */
-#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
-#define SPC5_CLOCK_FAILURE_HOOK()           chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(SPC560BCxx_MCUCONF)
-#error "Using a wrong mcuconf.h file, SPC560BCxx_MCUCONF not defined"
-#endif
-
-/* Check on the XOSC frequency.*/
-#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) ||                                  \
-    (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
-#error "invalid SPC5_XOSC_CLK value specified"
-#endif
-
-/* Check on the XOSC divider.*/
-#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
-#error "invalid SPC5_XOSCDIV_VALUE value specified"
-#endif
-
-/* Check on the IRC divider.*/
-#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
-#error "invalid SPC5_IRCDIV_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_IDF_VALUE.*/
-#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
-#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
-#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
-#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_ODF.*/
-#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
-#define SPC5_FMPLL0_ODF_VALUE    2
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
-#define SPC5_FMPLL0_ODF_VALUE    4
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
-#define SPC5_FMPLL0_ODF_VALUE    8
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
-#define SPC5_FMPLL0_ODF_VALUE    16
-#else
-#error "invalid SPC5_FMPLL0_ODF value specified"
-#endif
-
-/**
- * @brief   SPC5_FMPLL0_VCO_CLK clock point.
- */
-#define SPC5_FMPLL0_VCO_CLK                                                 \
-  ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
-
-/* Check on FMPLL0 VCO output.*/
-#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \
-    (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
-#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
-#endif
-
-/**
- * @brief   SPC5_FMPLL0_CLK clock point.
- */
-#define SPC5_FMPLL0_CLK                                                     \
-  (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
-
-/* Check on SPC5_FMPLL0_CLK.*/
-#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
-#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
-#endif
-
-/* Check on the peripherals set 1 clock divider settings.*/
-#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
-#define SPC5_CGM_SC_DC0         0
-#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) &&                              \
-      (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC0         (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
-#else
-#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
-#endif
-
-/* Check on the peripherals set 2 clock divider settings.*/
-#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
-#define SPC5_CGM_SC_DC1         0
-#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) &&                              \
-      (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC1         (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
-#else
-#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
-#endif
-
-/* Check on the peripherals set 3 clock divider settings.*/
-#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
-#define SPC5_CGM_SC_DC2         0
-#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) &&                              \
-      (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC2         (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
-#else
-#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-typedef enum {
-  SPC5_RUNMODE_TEST  = 1,
-  SPC5_RUNMODE_SAFE  = 2,
-  SPC5_RUNMODE_DRUN  = 3,
-  SPC5_RUNMODE_RUN0  = 4,
-  SPC5_RUNMODE_RUN1  = 5,
-  SPC5_RUNMODE_RUN2  = 6,
-  SPC5_RUNMODE_RUN3  = 7,
-  SPC5_RUNMODE_HALT0 = 8,
-  SPC5_RUNMODE_STOP0 = 10
-} spc5_runmode_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#include "spc5_edma.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void spc_clock_init(void);
-  bool_t halSPCSetRunMode(spc5_runmode_t mode);
-  void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
-#if !SPC5_NO_INIT
-  uint32_t halSPCGetSystemClock(void);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560BCxx/platform.mk b/os/hal/platforms/SPC560BCxx/platform.mk
deleted file mode 100644
index 3432a7b16..000000000
--- a/os/hal/platforms/SPC560BCxx/platform.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# List of all the SPC560B/Cxx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1
diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
deleted file mode 100644
index 681e68ca6..000000000
--- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560BCxx/spc560bc_registry.h
- * @brief   SPC560B/Cxx capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _SPC560BC_REGISTRY_H_
-#define _SPC560BC_REGISTRY_H_
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    SPC560B/Cxx capabilities
- * @{
- */
-/* eDMA attributes.*/
-#define SPC5_HAS_EDMA                       FALSE
-
-/* LINFlex attributes.*/
-#define SPC5_HAS_LINFLEX0                   TRUE
-#define SPC5_LINFLEX0_PCTL                  48
-#define SPC5_LINFLEX0_RXI_HANDLER           vector79
-#define SPC5_LINFLEX0_TXI_HANDLER           vector80
-#define SPC5_LINFLEX0_ERR_HANDLER           vector81
-#define SPC5_LINFLEX0_RXI_NUMBER            79
-#define SPC5_LINFLEX0_TXI_NUMBER            80
-#define SPC5_LINFLEX0_ERR_NUMBER            81
-#define SPC5_LINFLEX0_CLK                   (halSPCGetSystemClock() /       \
-                                             SPC5_PERIPHERAL1_CLK_DIV_VALUE)
-
-#define SPC5_HAS_LINFLEX1                   TRUE
-#define SPC5_LINFLEX1_PCTL                  49
-#define SPC5_LINFLEX1_RXI_HANDLER           vector99
-#define SPC5_LINFLEX1_TXI_HANDLER           vector100
-#define SPC5_LINFLEX1_ERR_HANDLER           vector101
-#define SPC5_LINFLEX1_RXI_NUMBER            99
-#define SPC5_LINFLEX1_TXI_NUMBER            100
-#define SPC5_LINFLEX1_ERR_NUMBER            101
-#define SPC5_LINFLEX1_CLK                   (halSPCGetSystemClock() /       \
-                                             SPC5_PERIPHERAL1_CLK_DIV_VALUE)
-
-#define SPC5_HAS_LINFLEX2                   TRUE
-#define SPC5_LINFLEX2_PCTL                  50
-#define SPC5_LINFLEX2_RXI_HANDLER           vector119
-#define SPC5_LINFLEX2_TXI_HANDLER           vector120
-#define SPC5_LINFLEX2_ERR_HANDLER           vector121
-#define SPC5_LINFLEX2_RXI_NUMBER            119
-#define SPC5_LINFLEX2_TXI_NUMBER            120
-#define SPC5_LINFLEX2_ERR_NUMBER            121
-#define SPC5_LINFLEX2_CLK                   (halSPCGetSystemClock() /       \
-                                             SPC5_PERIPHERAL1_CLK_DIV_VALUE)
-
-#define SPC5_HAS_LINFLEX3                   TRUE
-#define SPC5_LINFLEX3_PCTL                  51
-#define SPC5_LINFLEX3_RXI_HANDLER           vector122
-#define SPC5_LINFLEX3_TXI_HANDLER           vector123
-#define SPC5_LINFLEX3_ERR_HANDLER           vector124
-#define SPC5_LINFLEX3_RXI_NUMBER            122
-#define SPC5_LINFLEX3_TXI_NUMBER            123
-#define SPC5_LINFLEX3_ERR_NUMBER            124
-#define SPC5_LINFLEX3_CLK                   (halSPCGetSystemClock() /       \
-                                             SPC5_PERIPHERAL1_CLK_DIV_VALUE)
-
-/* SIUL attributes.*/
-#define SPC5_HAS_SIUL                       TRUE
-#define SPC5_SIUL_PCTL                      68
-#define SPC5_SIUL_NUM_PORTS                 8
-#define SPC5_SIUL_NUM_PCRS                  123
-#define SPC5_SIUL_NUM_PADSELS               32
-#define SPC5_SIUL_SYSTEM_PINS               32,33,121,122
-
-/* eMIOS attributes.*/
-#define SPC5_HAS_EMIOS0                     TRUE
-#define SPC5_EMIOS0_PCTL                    72
-#define SPC5_EMIOS0_GFR_F0F1_HANDLER        vector141
-#define SPC5_EMIOS0_GFR_F2F3_HANDLER        vector142
-#define SPC5_EMIOS0_GFR_F4F5_HANDLER        vector143
-#define SPC5_EMIOS0_GFR_F6F7_HANDLER        vector144
-#define SPC5_EMIOS0_GFR_F8F9_HANDLER        vector145
-#define SPC5_EMIOS0_GFR_F10F11_HANDLER      vector146
-#define SPC5_EMIOS0_GFR_F12F13_HANDLER      vector147
-#define SPC5_EMIOS0_GFR_F14F15_HANDLER      vector148
-#define SPC5_EMIOS0_GFR_F16F17_HANDLER      vector149
-#define SPC5_EMIOS0_GFR_F18F19_HANDLER      vector150
-#define SPC5_EMIOS0_GFR_F20F21_HANDLER      vector151
-#define SPC5_EMIOS0_GFR_F22F23_HANDLER      vector152
-#define SPC5_EMIOS0_GFR_F24F25_HANDLER      vector153
-#define SPC5_EMIOS0_GFR_F26F27_HANDLER      vector154
-#define SPC5_EMIOS0_GFR_F0F1_NUMBER         141
-#define SPC5_EMIOS0_GFR_F2F3_NUMBER         142
-#define SPC5_EMIOS0_GFR_F4F5_NUMBER         143
-#define SPC5_EMIOS0_GFR_F6F7_NUMBER         144
-#define SPC5_EMIOS0_GFR_F8F9_NUMBER         145
-#define SPC5_EMIOS0_GFR_F10F11_NUMBER       146
-#define SPC5_EMIOS0_GFR_F12F13_NUMBER       147
-#define SPC5_EMIOS0_GFR_F14F15_NUMBER       148
-#define SPC5_EMIOS0_GFR_F16F17_NUMBER       149
-#define SPC5_EMIOS0_GFR_F18F19_NUMBER       150
-#define SPC5_EMIOS0_GFR_F20F21_NUMBER       151
-#define SPC5_EMIOS0_GFR_F22F23_NUMBER       152
-#define SPC5_EMIOS0_GFR_F24F25_NUMBER       153
-#define SPC5_EMIOS0_GFR_F26F27_NUMBER       154
-
-#define SPC5_EMIOS0_CLK                     (halSPCGetSystemClock() /         \
-                                             SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
-                                             SPC5_EMIOS0_GPRE_VALUE)
-
-
-#define SPC5_HAS_EMIOS1                     TRUE
-#define SPC5_EMIOS1_PCTL                    73
-#define SPC5_EMIOS1_GFR_F0F1_HANDLER        vector157
-#define SPC5_EMIOS1_GFR_F2F3_HANDLER        vector158
-#define SPC5_EMIOS1_GFR_F4F5_HANDLER        vector159
-#define SPC5_EMIOS1_GFR_F6F7_HANDLER        vector160
-#define SPC5_EMIOS1_GFR_F8F9_HANDLER        vector161
-#define SPC5_EMIOS1_GFR_F10F11_HANDLER      vector162
-#define SPC5_EMIOS1_GFR_F12F13_HANDLER      vector163
-#define SPC5_EMIOS1_GFR_F14F15_HANDLER      vector164
-#define SPC5_EMIOS1_GFR_F16F17_HANDLER      vector165
-#define SPC5_EMIOS1_GFR_F18F19_HANDLER      vector166
-#define SPC5_EMIOS1_GFR_F20F21_HANDLER      vector167
-#define SPC5_EMIOS1_GFR_F22F23_HANDLER      vector168
-#define SPC5_EMIOS1_GFR_F24F25_HANDLER      vector169
-#define SPC5_EMIOS1_GFR_F26F27_HANDLER      vector170
-#define SPC5_EMIOS1_GFR_F0F1_NUMBER         157
-#define SPC5_EMIOS1_GFR_F2F3_NUMBER         158
-#define SPC5_EMIOS1_GFR_F4F5_NUMBER         159
-#define SPC5_EMIOS1_GFR_F6F7_NUMBER         160
-#define SPC5_EMIOS1_GFR_F8F9_NUMBER         161
-#define SPC5_EMIOS1_GFR_F10F11_NUMBER       162
-#define SPC5_EMIOS1_GFR_F12F13_NUMBER       163
-#define SPC5_EMIOS1_GFR_F14F15_NUMBER       164
-#define SPC5_EMIOS1_GFR_F16F17_NUMBER       165
-#define SPC5_EMIOS1_GFR_F18F19_NUMBER       166
-#define SPC5_EMIOS1_GFR_F20F21_NUMBER       167
-#define SPC5_EMIOS1_GFR_F22F23_NUMBER       168
-#define SPC5_EMIOS1_GFR_F24F25_NUMBER       169
-#define SPC5_EMIOS1_GFR_F26F27_NUMBER       170
-
-#define SPC5_EMIOS1_CLK                     (halSPCGetSystemClock() /         \
-                                             SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
-                                             SPC5_EMIOS1_GPRE_VALUE)
-
-/* FlexCAN attributes.*/
-#define SPC5_HAS_FLEXCAN0                                   TRUE
-#define SPC5_FLEXCAN0_PCTL                                  16
-#define SPC5_FLEXCAN0_MB                                    64
-#define SPC5_FLEXCAN0_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER           vector65
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER              vector66
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER             vector68
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER             vector69
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER             vector70
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER             vector71
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER             vector72
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER             vector73
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER            65
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER               66
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER              68
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER              69
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER              70
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER              71
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER              72
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER              73
-#define SPC5_FLEXCAN0_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
-#define SPC5_FLEXCAN0_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
-
-#define SPC5_HAS_FLEXCAN1                                   TRUE
-#define SPC5_FLEXCAN1_PCTL                                  17
-#define SPC5_FLEXCAN1_MB                                    64
-#define SPC5_FLEXCAN1_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER           vector85
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER              vector86
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER             vector88
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER             vector89
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER             vector90
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER             vector91
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER             vector92
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER             vector93
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER            85
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER               86
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER              88
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER              89
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER              90
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER              91
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER              92
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER              93
-#define SPC5_FLEXCAN1_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
-#define SPC5_FLEXCAN1_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
-
-#define SPC5_HAS_FLEXCAN2                                   TRUE
-#define SPC5_FLEXCAN2_PCTL                                  18
-#define SPC5_FLEXCAN2_MB                                    64
-#define SPC5_FLEXCAN2_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER           vector105
-#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER              vector106
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER             vector108
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER             vector109
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER             vector110
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER             vector111
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER             vector112
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER             vector113
-#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER            105
-#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER               106
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER              108
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER              109
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER              110
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER              111
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER              112
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER              113
-#define SPC5_FLEXCAN2_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
-#define SPC5_FLEXCAN2_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
-
-#define SPC5_HAS_FLEXCAN3                                   TRUE
-#define SPC5_FLEXCAN3_PCTL                                  19
-#define SPC5_FLEXCAN3_MB                                    64
-#define SPC5_FLEXCAN3_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER           vector173
-#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER              vector174
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER             vector176
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER             vector177
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER             vector178
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER             vector179
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER             vector180
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER             vector181
-#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER            173
-#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER               174
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER              176
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER              177
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER              178
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER              179
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER              180
-#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER              181
-#define SPC5_FLEXCAN3_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL);
-#define SPC5_FLEXCAN3_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL);
-
-#define SPC5_HAS_FLEXCAN4                                   TRUE
-#define SPC5_FLEXCAN4_PCTL                                  20
-#define SPC5_FLEXCAN4_MB                                    64
-#define SPC5_FLEXCAN4_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER           vector190
-#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER              vector191
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER             vector193
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER             vector194
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER             vector195
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER             vector196
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER             vector197
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER             vector198
-#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER            190
-#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER               191
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER              193
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER              194
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER              195
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER              196
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER              197
-#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER              198
-#define SPC5_FLEXCAN4_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL);
-#define SPC5_FLEXCAN4_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL);
-
-#define SPC5_HAS_FLEXCAN5                                   TRUE
-#define SPC5_FLEXCAN5_PCTL                                  21
-#define SPC5_FLEXCAN5_MB                                    64
-#define SPC5_FLEXCAN5_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER           vector202
-#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER              vector203
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER             vector205
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER             vector206
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER             vector207
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER             vector208
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER             vector209
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER             vector210
-#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER            202
-#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER               203
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER              205
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER              206
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER              207
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER              208
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER              209
-#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER              210
-#define SPC5_FLEXCAN5_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL);
-#define SPC5_FLEXCAN5_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL);
-/** @} */
-
-#endif /* _SPC560BC_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560BCxx/typedefs.h b/os/hal/platforms/SPC560BCxx/typedefs.h
deleted file mode 100644
index 5ab294e4b..000000000
--- a/os/hal/platforms/SPC560BCxx/typedefs.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560BCxx/typedefs.h
- * @brief   Dummy typedefs file.
- */
-
-#ifndef _TYPEDEFS_H_
-#define _TYPEDEFS_H_
-
-#include "chtypes.h"
-
-#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/platforms/SPC560BCxx/xpc560bc.h b/os/hal/platforms/SPC560BCxx/xpc560bc.h
deleted file mode 100644
index 4d7425165..000000000
--- a/os/hal/platforms/SPC560BCxx/xpc560bc.h
+++ /dev/null
@@ -1,3769 +0,0 @@
-/***************************************************************** 
- *
- * FILE        : MPC5604B_0M27V_0100.h
- * 
- * DESCRIPTION : This is the header file describing the register
- *               set for:
- *	             MPC5604B, mask set = 0M27V
- *               SPC560B4, mask set = FB50X20B
- * 
- * COPYRIGHT   :(c) 2009, Freescale & STMicroelectronics 
- * 
- * VERSION     : 01.02 
- * DATE        : 08 MAY 2009 
- * AUTHOR      : b04629 
- * HISTORY     : Original source taken from jdp_0100.h. 
- *               Updated to be compatable with 
- *               - MPC5604B Mask ID 0M27V 
- *               - MPC5604B Reference Manual Rev 3 Draft A
- *               - SPC560B4 Mask ID FB50X20B
- *               - SPC560B4 Reference Manual Rev 3 Draft A
- *
- ******************************************************************/  
-    
-/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ 
-    
-/***************************************************************** 
-* Example instantiation and use:            
-*                                           
-*  <MODULE>.<REGISTER>.B.<BIT> = 1;         
-*  <MODULE>.<REGISTER>.R       = 0x10000000;
-*                                           
-******************************************************************/ 
-    
-#ifndef _MPC5604B_H_
-#define _MPC5604B_H_
-    
-#include "typedefs.h"
-    
-#ifdef  __cplusplus
-extern "C" {
-    
-#endif  /* 
- */
-    
-#ifdef __MWERKS__
-#pragma push
-#pragma ANSI_strict off
-#endif  /* 
- */
-/****************************************************************************/
-/*                          MODULE : ADC                                   */
-/****************************************************************************/
-        struct ADC_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t OWREN:1;
-                vuint32_t WLSIDE:1;
-                vuint32_t MODE:1;
-                  vuint32_t:4;
-                vuint32_t NSTART:1;
-                  vuint32_t:1;
-                vuint32_t JTRGEN:1;
-                vuint32_t JEDGE:1;
-                vuint32_t JSTART:1;
-                  vuint32_t:2;
-                vuint32_t CTUEN:1;
-                  vuint32_t:8;
-                vuint32_t ADCLKSEL:1;
-                vuint32_t ABORTCHAIN:1;
-                vuint32_t ABORT:1;
-                vuint32_t ACK0:1;
-                  vuint32_t:4;
-                vuint32_t PWDN:1;
-            } B;
-        } MCR;                  /* MAIN CONFIGURATION REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:7;
-                vuint32_t NSTART:1;
-                vuint32_t JABORT:1;
-                  vuint32_t:2;
-                vuint32_t JSTART:1;
-                  vuint32_t:3;
-                vuint32_t CTUSTART:1;
-                vuint32_t CHADDR:7;
-                  vuint32_t:3;
-                vuint32_t ACK0:1;
-                  vuint32_t:2;
-                vuint32_t ADCSTATUS:3;
-            } B;
-        } MSR;                  /* MAIN STATUS REGISTER */
-
-        int32_t ADC_reserved1[2];       /* (0x010 - 0x008)/4 = 0x02 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:27;
-                vuint32_t EOCTU:1;
-                vuint32_t JEOC:1;
-                vuint32_t JECH:1;
-                vuint32_t EOC:1;
-                vuint32_t ECH:1;
-            } B;
-        } ISR;                  /* INTERRUPT STATUS REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EOC_CH31:1;
-                vuint32_t EOC_CH30:1;
-                vuint32_t EOC_CH29:1;
-                vuint32_t EOC_CH28:1;
-                vuint32_t EOC_CH27:1;
-                vuint32_t EOC_CH26:1;
-                vuint32_t EOC_CH25:1;
-                vuint32_t EOC_CH24:1;
-                vuint32_t EOC_CH23:1;
-                vuint32_t EOC_CH22:1;
-                vuint32_t EOC_CH21:1;
-                vuint32_t EOC_CH20:1;
-                vuint32_t EOC_CH19:1;
-                vuint32_t EOC_CH18:1;
-                vuint32_t EOC_CH17:1;
-                vuint32_t EOC_CH16:1;
-                vuint32_t EOC_CH15:1;
-                vuint32_t EOC_CH14:1;
-                vuint32_t EOC_CH13:1;
-                vuint32_t EOC_CH12:1;
-                vuint32_t EOC_CH11:1;
-                vuint32_t EOC_CH10:1;
-                vuint32_t EOC_CH9:1;
-                vuint32_t EOC_CH8:1;
-                vuint32_t EOC_CH7:1;
-                vuint32_t EOC_CH6:1;
-                vuint32_t EOC_CH5:1;
-                vuint32_t EOC_CH4:1;
-                vuint32_t EOC_CH3:1;
-                vuint32_t EOC_CH2:1;
-                vuint32_t EOC_CH1:1;
-                vuint32_t EOC_CH0:1;
-            } B;
-        } CEOCFR[3];            /* Channel Pending Register 0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:27;
-                vuint32_t MSKEOCTU:1;
-                vuint32_t MSKJEOC:1;
-                vuint32_t MSKJECH:1;
-                vuint32_t MSKEOC:1;
-                vuint32_t MSKECH:1;
-            } B;
-        } IMR;                  /* INTERRUPT MASK REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CIM31:1;
-                vuint32_t CIM30:1;
-                vuint32_t CIM29:1;
-                vuint32_t CIM28:1;
-                vuint32_t CIM27:1;
-                vuint32_t CIM26:1;
-                vuint32_t CIM25:1;
-                vuint32_t CIM24:1;
-                vuint32_t CIM23:1;
-                vuint32_t CIM22:1;
-                vuint32_t CIM21:1;
-                vuint32_t CIM20:1;
-                vuint32_t CIM19:1;
-                vuint32_t CIM18:1;
-                vuint32_t CIM17:1;
-                vuint32_t CIM16:1;
-                vuint32_t CIM15:1;
-                vuint32_t CIM14:1;
-                vuint32_t CIM13:1;
-                vuint32_t CIM12:1;
-                vuint32_t CIM11:1;
-                vuint32_t CIM10:1;
-                vuint32_t CIM9:1;
-                vuint32_t CIM8:1;
-                vuint32_t CIM7:1;
-                vuint32_t CIM6:1;
-                vuint32_t CIM5:1;
-                vuint32_t CIM4:1;
-                vuint32_t CIM3:1;
-                vuint32_t CIM2:1;
-                vuint32_t CIM1:1;
-                vuint32_t CIM0:1;
-            } B;
-        } CIMR[3];              /* Channel Interrupt Mask Register 0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t WDG3H:1;
-                vuint32_t WDG2H:1;
-                vuint32_t WDG1H:1;
-                vuint32_t WDG0H:1;
-                vuint32_t WDG3L:1;
-                vuint32_t WDG2L:1;
-                vuint32_t WDG1L:1;
-                vuint32_t WDG0L:1;
-            } B;
-        } WTISR;                /* WATCHDOG INTERRUPT THRESHOLD REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t MSKWDG3H:1;
-                vuint32_t MSKWDG2H:1;
-                vuint32_t MSKWDG1H:1;
-                vuint32_t MSKWDG0H:1;
-                vuint32_t MSKWDG3L:1;
-                vuint32_t MSKWDG2L:1;
-                vuint32_t MSKWDG1L:1;
-                vuint32_t MSKWDG0L:1;
-            } B;
-        } WTIMR;                /* WATCHDOG INTERRUPT MASK REGISTER */
-
-        int32_t ADC_reserved2[6];       /* (0x050 - 0x038)/4 = 0x06 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t THREN:1;
-                vuint32_t THRINV:1;
-                  vuint32_t:7;
-                vuint32_t THRCH:7;
-            } B;
-        } TRC[4];               /* ADC THRESHOLD REGISTER REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t THRH:12;
-                  vuint32_t:4;
-                vuint32_t THRL:12;
-            } B;
-        } THRHLR[4];            /* THRESHOLD REGISTER */
-
-        int32_t ADC_reserved3[4];       /* (0x080 - 0x070)/4 = 0x04 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:25;
-                vuint32_t PREVAL2:2;
-                vuint32_t PREVAL1:2;
-                vuint32_t PREVAL0:2;
-                vuint32_t PRECONV:1;
-            } B;
-        } PSCR;                 /* PRESAMPLING CONTROL REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRES31:1;
-                vuint32_t PRES30:1;
-                vuint32_t PRES29:1;
-                vuint32_t PRES28:1;
-                vuint32_t PRES27:1;
-                vuint32_t PRES26:1;
-                vuint32_t PRES25:1;
-                vuint32_t PRES24:1;
-                vuint32_t PRES23:1;
-                vuint32_t PRES22:1;
-                vuint32_t PRES21:1;
-                vuint32_t PRES20:1;
-                vuint32_t PRES19:1;
-                vuint32_t PRES18:1;
-                vuint32_t PRES17:1;
-                vuint32_t PRES16:1;
-                vuint32_t PRES15:1;
-                vuint32_t PRES14:1;
-                vuint32_t PRES13:1;
-                vuint32_t PRES12:1;
-                vuint32_t PRES11:1;
-                vuint32_t PRES10:1;
-                vuint32_t PRES9:1;
-                vuint32_t PRES8:1;
-                vuint32_t PRES7:1;
-                vuint32_t PRES6:1;
-                vuint32_t PRES5:1;
-                vuint32_t PRES4:1;
-                vuint32_t PRES3:1;
-                vuint32_t PRES2:1;
-                vuint32_t PRES1:1;
-                vuint32_t PRES0:1;
-            } B;
-        } PSR[3];               /* PRESAMPLING REGISTER */
-
-        int32_t ADC_reserved4[1];       /* (0x094 - 0x090)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t INPLATCH:1;
-                  vuint32_t:4;
-                vuint32_t INPCMP:2;
-                  vuint32_t:1;
-                vuint32_t INPSAMP:8;
-            } B;
-        } CTR[3];               /* CONVERSION TIMING REGISTER */
-
-        int32_t ADC_reserved5[1];       /* (0x0A4 - 0x0A0)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CH31:1;
-                vuint32_t CH30:1;
-                vuint32_t CH29:1;
-                vuint32_t CH28:1;
-                vuint32_t CH27:1;
-                vuint32_t CH26:1;
-                vuint32_t CH25:1;
-                vuint32_t CH24:1;
-                vuint32_t CH23:1;
-                vuint32_t CH22:1;
-                vuint32_t CH21:1;
-                vuint32_t CH20:1;
-                vuint32_t CH19:1;
-                vuint32_t CH18:1;
-                vuint32_t CH17:1;
-                vuint32_t CH16:1;
-                vuint32_t CH15:1;
-                vuint32_t CH14:1;
-                vuint32_t CH13:1;
-                vuint32_t CH12:1;
-                vuint32_t CH11:1;
-                vuint32_t CH10:1;
-                vuint32_t CH9:1;
-                vuint32_t CH8:1;
-                vuint32_t CH7:1;
-                vuint32_t CH6:1;
-                vuint32_t CH5:1;
-                vuint32_t CH4:1;
-                vuint32_t CH3:1;
-                vuint32_t CH2:1;
-                vuint32_t CH1:1;
-                vuint32_t CH0:1;
-            } B;
-        } NCMR[3];              /* NORMAL CONVERSION MASK REGISTER */
-
-        int32_t ADC_reserved6[1];       /* (0x0B4 - 0x0B0)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CH31:1;
-                vuint32_t CH30:1;
-                vuint32_t CH29:1;
-                vuint32_t CH28:1;
-                vuint32_t CH27:1;
-                vuint32_t CH26:1;
-                vuint32_t CH25:1;
-                vuint32_t CH24:1;
-                vuint32_t CH23:1;
-                vuint32_t CH22:1;
-                vuint32_t CH21:1;
-                vuint32_t CH20:1;
-                vuint32_t CH19:1;
-                vuint32_t CH18:1;
-                vuint32_t CH17:1;
-                vuint32_t CH16:1;
-                vuint32_t CH15:1;
-                vuint32_t CH14:1;
-                vuint32_t CH13:1;
-                vuint32_t CH12:1;
-                vuint32_t CH11:1;
-                vuint32_t CH10:1;
-                vuint32_t CH9:1;
-                vuint32_t CH8:1;
-                vuint32_t CH7:1;
-                vuint32_t CH6:1;
-                vuint32_t CH5:1;
-                vuint32_t CH4:1;
-                vuint32_t CH3:1;
-                vuint32_t CH2:1;
-                vuint32_t CH1:1;
-                vuint32_t CH0:1;
-            } B;
-        } JCMR[3];              /* Injected CONVERSION MASK REGISTER */
-
-        int32_t ADC_reserved7[1];       /* (0x0C4 - 0x0C0)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t DSD:8;
-            } B;
-        } DSDR;                 /* DECODE SIGNALS DELAY REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t PDED:8;
-            } B;
-        } PDEDR;                /* POWER DOWN DELAY REGISTER */
-
-        int32_t ADC_reserved8[13];      /* (0x100 - 0x0CC)/4 = 0x0D */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t VALID:1;
-                vuint32_t OVERW:1;
-                vuint32_t RESULT:2;
-                  vuint32_t:6;
-                vuint32_t CDATA:10;
-            } B;
-        } CDR[96];              /* Channel 0-95 Data REGISTER */
-
-    };                          /* end of ADC_tag */
-/****************************************************************************/
-/*                          MODULE : CANSP                                   */
-/****************************************************************************/
-    struct CANSP_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RX_COMPLETE:1;
-                vuint32_t BUSY:1;
-                vuint32_t ACTIVE_CK:1;
-                  vuint32_t:3;
-                vuint32_t MODE:1;
-                vuint32_t CAN_RX_SEL:3;
-                vuint32_t BRP:5;
-                vuint32_t CAN_SMPLR_EN:1;
-            } B;
-        } CR;                   /* CANSP Control Register */
-
-        union {
-            vuint32_t R;
-        } SR[12];               /* CANSP Sample Register 0 to 11 */
-
-    };                          /* end of CANSP_tag */
-/****************************************************************************/
-/*                     MODULE : CFLASH                                       */
-/****************************************************************************/
-    struct CFLASH_tag {
-        union {                 /* Module Configuration Register */
-            vuint32_t R;
-            struct {
-                vuint32_t EDC:1;
-                  vuint32_t:4;
-                vuint32_t SIZE:3;
-                  vuint32_t:1;
-                vuint32_t LAS:3;
-                  vuint32_t:3;
-                vuint32_t MAS:1;
-                vuint32_t EER:1;
-                vuint32_t RWE:1;
-                  vuint32_t:1;
-                  vuint32_t:1;
-                vuint32_t PEAS:1;
-                vuint32_t DONE:1;
-                vuint32_t PEG:1;
-                  vuint32_t:4;
-                vuint32_t PGM:1;
-                vuint32_t PSUS:1;
-                vuint32_t ERS:1;
-                vuint32_t ESUS:1;
-                vuint32_t EHV:1;
-            } B;
-        } MCR;
-
-        union {                 /* LML Register */
-            vuint32_t R;
-            struct {
-                vuint32_t LME:1;
-                  vuint32_t:10;
-                vuint32_t TSLK:1;
-                  vuint32_t:2;
-                vuint32_t MLK:2;
-                vuint32_t LLK:16;
-            } B;
-        } LML;
-
-        union {                 /* HBL Register */
-            vuint32_t R;
-            struct {
-                vuint32_t HBE:1;
-                  vuint32_t:23;
-                vuint32_t HBLOCK:8;
-            } B;
-        } HBL;
-
-        union {                 /* SLML Register */
-            vuint32_t R;
-            struct {
-                vuint32_t SLE:1;
-                  vuint32_t:10;
-                vuint32_t STSLK:1;
-                  vuint32_t:2;
-                vuint32_t SMK:2;
-                vuint32_t SLK:16;
-            } B;
-        } SLL;
-
-        union {                 /* LMS Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t MSL:2;
-                vuint32_t LSL:16;
-            } B;
-        } LMS;
-
-        union {                 /* High Address Space Block Select Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:26;
-                vuint32_t HSL:6;
-            } B;
-        } HBS;
-
-        union {                 /* Address Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:10;
-                vuint32_t ADD:19;
-                  vuint32_t:3;
-            } B;
-        } ADR;
-
-        union {                 /* CFLASH Configuration Register 0 */
-            vuint32_t R;
-            struct {
-                vuint32_t BK0_APC:5;
-                vuint32_t BK0_WWSC:5;
-                vuint32_t BK0_RWSC:5;
-                vuint32_t BK0_RWWC2:1;
-                vuint32_t BK0_RWWC1:1;
-                vuint32_t B0_P1_BCFG:2;
-                vuint32_t B0_P1_DPFE:1;
-                vuint32_t B0_P1_IPFE:1;
-                vuint32_t B0_P1_PFLM:2;
-                vuint32_t B0_P1_BFE:1;
-                vuint32_t BK0_RWWC0:1;
-                vuint32_t B0_P0_BCFG:2;
-                vuint32_t B0_P0_DPFE:1;
-                vuint32_t B0_P0_IPFE:1;
-                vuint32_t B0_P0_PFLM:2;
-                vuint32_t B0_P0_BFE:1;
-            } B;
-        } PFCR0;
-
-        union {                 /* CFLASH Configuration Register 1 */
-            vuint32_t R;
-            struct {
-                vuint32_t BK1_APC:5;
-                vuint32_t BK1_WWSC:5;
-                vuint32_t BK1_RWSC:5;
-                vuint32_t BK1_RWWC2:1;
-                vuint32_t BK1_RWWC1:1;
-                  vuint32_t:6;
-                vuint32_t B0_P1_BFE:1;
-                vuint32_t BK1_RWWC0:1;
-                  vuint32_t:6;
-                vuint32_t B1_P0_BFE:1;
-            } B;
-        } PFCR1;
-
-        union {                 /* cflash Access Protection Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:6;
-                vuint32_t ARBM:2;
-                vuint32_t M7PFD:1;
-                vuint32_t M6PFD:1;
-                vuint32_t M5PFD:1;
-                vuint32_t M4PFD:1;
-                vuint32_t M3PFD:1;
-                vuint32_t M2PFD:1;
-                vuint32_t M1PFD:1;
-                vuint32_t M0PFD:1;
-                vuint32_t M7AP:2;
-                vuint32_t M6AP:2;
-                vuint32_t M5AP:2;
-                vuint32_t M4AP:2;
-                vuint32_t M3AP:2;
-                vuint32_t M2AP:2;
-                vuint32_t M1AP:2;
-                vuint32_t M0AP:2;
-            } B;
-        } FAPR;
-
-        int32_t CFLASH_reserved0[5];    /* {0x003C-0x0028}/0x4 = 0x05 */
-
-        union {                 /* User Test Register 0 */
-            vuint32_t R;
-            struct {
-                vuint32_t UTE:1;
-                  vuint32_t:7;
-                vuint32_t DSI:8;
-                  vuint32_t:10;
-                vuint32_t MRE:1;
-                vuint32_t MRV:1;
-                vuint32_t EIE:1;
-                vuint32_t AIS:1;
-                vuint32_t AIE:1;
-                vuint32_t AID:1;
-            } B;
-        } UT0;
-
-        union {                 /* User Test Register 1 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT1;
-
-        union {                 /* User Test Register 2 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT2;
-
-        union {                 /* User Multiple Input Signature Register 0-4 */
-            vuint32_t R;
-            struct {
-                vuint32_t MS:32;
-            } B;
-        } UMISR[5];
-
-    };                          /* end of CFLASH_tag */
-/****************************************************************************/
-/*                          MODULE : CGM                                   */
-/****************************************************************************/
-    struct CGM_tag {
-
-        /* The CGM provides a unified register interface, enabling access to 
-
-           all clock sources:
-
-           Base Address | Clock Sources
-
-           -----------------------------
-
-           0xC3FE0000   | FXOSC_CTL
-
-           ----------   | Reserved
-
-           0xC3FE0040   | SXOSC_CTL
-
-           0xC3FE0060   | FIRC_CTL
-
-           0xC3FE0080   | SIRC_CTL
-
-           0xC3FE00A0   | FMPLL_0
-
-           ----------   | Reserved 
-
-           0xC3FE0100   | CMU_0
-
-         */
-    /************************************/
-        /* FXOSC_CTL @ CGM base address + 0x0000 */
-    /************************************/
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t OSCBYP:1;
-                  vuint32_t:7;
-                vuint32_t EOCV:8;
-                vuint32_t M_OSC:1;
-                  vuint32_t:2;
-                vuint32_t OSCDIV:5;
-                vuint32_t I_OSC:1;
-                  vuint32_t:7;
-            } B;
-        } FXOSC_CTL;            /* Fast OSC Control Register */
-
-    /************************************/
-        /* SXOSC_CTL @ CGM base address + 0x0040 */
-    /************************************/
-        int32_t CGM_reserved0[15];      /* (0x040 - 0x004)/4 = 0x0F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t OSCBYP:1;
-                  vuint32_t:7;
-                vuint32_t EOCV:8;
-                vuint32_t M_OSC:1;
-                  vuint32_t:2;
-                vuint32_t OSCDIV:5;
-                vuint32_t I_OSC:1;
-                  vuint32_t:5;
-                vuint32_t S_OSC:1;
-                vuint32_t OSCON:1;
-            } B;
-        } SXOSC_CTL;            /* Slow OSC Control Register */
-
-    /************************************/
-        /* FIRC_CTL @ CGM base address + 0x0060 */
-    /************************************/
-        int32_t CGM_reserved1[7];       /* (0x060 - 0x044)/4 = 0x07 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:10;
-                vuint32_t RCTRIM:6;
-                  vuint32_t:3;
-                vuint32_t RCDIV:5;
-                  vuint32_t:8;
-            } B;
-        } FIRC_CTL;             /* Fast IRC Control Register */
-
-    /****************************************/
-        /* SIRC_CTL @ CGM base address + 0x0080 */
-    /****************************************/
-        int32_t CGM_reserved2[7];       /* (0x080 - 0x064)/4 = 0x07 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:11;
-                vuint32_t RCTRIM:5;
-                  vuint32_t:3;
-                vuint32_t RCDIV:5;
-                  vuint32_t:3;
-                vuint32_t S_SIRC:1;
-                  vuint32_t:3;
-                vuint32_t SIRCON_STDBY:1;
-            } B;
-        } SIRC_CTL;             /* Slow IRC Control Register */
-
-    /*************************************/
-        /* FMPLL @ CGM base address + 0x00A0 */
-    /*************************************/
-        int32_t CGM_reserved3[7];       /* (0x0A0 - 0x084)/4 = 0x07 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:2;
-                vuint32_t IDF:4;
-                vuint32_t ODF:2;
-                  vuint32_t:1;
-                vuint32_t NDIV:7;
-                  vuint32_t:7;
-                vuint32_t EN_PLL_SW:1;
-                vuint32_t MODE:1;
-                vuint32_t UNLOCK_ONCE:1;
-                  vuint32_t:1;
-                vuint32_t I_LOCK:1;
-                vuint32_t S_LOCK:1;
-                vuint32_t PLL_FAIL_MASK:1;
-                vuint32_t PLL_FAIL_FLAG:1;
-                  vuint32_t:1;
-            } B;
-        } FMPLL_CR;             /* FMPLL Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t STRB_BYPASS:1;
-                  vuint32_t:1;
-                vuint32_t SPRD_SEL:1;
-                vuint32_t MOD_PERIOD:13;
-                vuint32_t FM_EN:1;
-                vuint32_t INC_STEP:15;
-            } B;
-        } FMPLL_MR;             /* FMPLL Modulation Register */
-
-    /************************************/
-        /* CMU @ CGM base address + 0x0100  */
-    /************************************/
-        int32_t CGM_reserved5[22];      /* (0x100 - 0x0A8)/4 = 0x16 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t SFM:1;
-                  vuint32_t:13;
-                vuint32_t CLKSEL1:2;
-                  vuint32_t:5;
-                vuint32_t RCDIV:2;
-                vuint32_t CME_A:1;
-            } B;
-        } CMU_CSR;              /* Control Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t FD:20;
-            } B;
-        } CMU_FDR;              /* Frequency Display Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:20;
-                vuint32_t HFREF_A:12;
-            } B;
-        } CMU_HFREFR_A;         /* High Frequency Reference Register PLL_A Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:20;
-                vuint32_t LFREF_A:12;
-            } B;
-        } CMU_LFREFR_A;         /* Low Frequency Reference Register PLL_A Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t FLCI_A:1;
-                vuint32_t FHHI_A:1;
-                vuint32_t FLLI_A:1;
-                vuint32_t OLRI:1;
-            } B;
-        } CMU_ISR;              /* Interrupt Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:32;
-            } B;
-        } CMU_IMR;              /* Interrupt Mask Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t MD:20;
-            } B;
-        } CMU_MDR;              /* Measurement Duration Register */
-
-    /************************************/
-        /* CGM General Registers @ CGM base address + 0x0370 */
-    /************************************/
-        int32_t CGM_reserved7[149];     /* (0x370 - 0x11C)/4 = 0x95 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t EN:1;
-            } B;
-        } OC_EN;                /* Output Clock Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:2;
-                vuint32_t SELDIV:2;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } OCDS_SC;              /* Output Clock Division Select Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELSTAT:4;
-                  vuint32_t:24;
-            } B;
-        } SC_SS;                /* System Clock Select Status */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t DE:1;
-                  vuint8_t:3;
-                vuint8_t DIV:4;
-            } B;
-        } SC_DC[3];             /* System Clock Divider Configuration 0->2 */
-
-    };                          /* end of CGM_tag */
-/****************************************************************************/
-/*                          MODULE : CTU                                   */
-/****************************************************************************/
-    struct CTU_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t TRGIEN:1;
-                vuint32_t TRGI:1;
-                  vuint32_t:6;
-            } B;
-        } CSR;                  /* Control Status Register */
-
-        int32_t CTU_reserved0[11];      /* (0x030 - 0x004)/4 = 0x0B */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t TM:1;
-                  vuint32_t:7;
-                vuint32_t CLR_FLAG:1;
-                  vuint32_t:1;
-                vuint32_t CHANNELVALUE:6;
-            } B;
-        } EVTCFGR[64];          /* Event Configuration Register */
-
-    };                          /* end of CTU_tag */
-/****************************************************************************/
-/*                     MODULE : DFLASH                                       */
-/****************************************************************************/
-    struct DFLASH_tag {
-        union {                 /* Module Configuration Register */
-            vuint32_t R;
-            struct {
-                vuint32_t EDC:1;
-                  vuint32_t:4;
-                vuint32_t SIZE:3;
-                  vuint32_t:1;
-                vuint32_t LAS:3;
-                  vuint32_t:3;
-                vuint32_t MAS:1;
-                vuint32_t EER:1;
-                vuint32_t RWE:1;
-                  vuint32_t:1;
-                  vuint32_t:1;
-                vuint32_t PEAS:1;
-                vuint32_t DONE:1;
-                vuint32_t PEG:1;
-                  vuint32_t:4;
-                vuint32_t PGM:1;
-                vuint32_t PSUS:1;
-                vuint32_t ERS:1;
-                vuint32_t ESUS:1;
-                vuint32_t EHV:1;
-            } B;
-        } MCR;
-
-        union {                 /* LML Register */
-            vuint32_t R;
-            struct {
-                vuint32_t LME:1;
-                  vuint32_t:10;
-                vuint32_t TSLK:1;
-                  vuint32_t:2;
-                vuint32_t MLK:2;
-                vuint32_t LLK:16;
-            } B;
-        } LML;
-
-        union {                 /* HBL Register */
-            vuint32_t R;
-            struct {
-                vuint32_t HBE:1;
-                  vuint32_t:23;
-                vuint32_t HBLOCK:8;
-            } B;
-        } HBL;
-
-        union {                 /* SLML Register */
-            vuint32_t R;
-            struct {
-                vuint32_t SLE:1;
-                  vuint32_t:10;
-                vuint32_t STSLK:1;
-                  vuint32_t:2;
-                vuint32_t SMK:2;
-                vuint32_t SLK:16;
-            } B;
-        } SLL;
-
-        union {                 /* LMS Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t MSL:2;
-                vuint32_t LSL:16;
-            } B;
-        } LMS;
-
-        union {                 /* High Address Space Block Select Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:26;
-                vuint32_t HSL:6;
-            } B;
-        } HBS;
-
-        union {                 /* Address Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:10;
-                vuint32_t ADD:19;
-                  vuint32_t:3;
-            } B;
-        } ADR;
-
-        int32_t Dflash_reserved0[8];    /* {0x003C-0x001C}/0x4 = 0x08 */
-
-        union {                 /* User Test Register 0 */
-            vuint32_t R;
-            struct {
-                vuint32_t UTE:1;
-                  vuint32_t:7;
-                vuint32_t DSI:8;
-                  vuint32_t:10;
-                vuint32_t MRE:1;
-                vuint32_t MRV:1;
-                vuint32_t EIE:1;
-                vuint32_t AIS:1;
-                vuint32_t AIE:1;
-                vuint32_t AID:1;
-            } B;
-        } UT0;
-
-        union {                 /* User Test Register 1 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT1;
-
-        union {                 /* User Test Register 2 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT2;
-
-        union {                 /* User Multiple Input Signature Register 0-4 */
-            vuint32_t R;
-            struct {
-                vuint32_t MS:32;
-            } B;
-        } UMISR[5];
-
-    };                          /* end of Dflash_tag */
-/****************************************************************************/
-/*                          MODULE : DSPI                                   */
-/****************************************************************************/
-    struct DSPI_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MSTR:1;
-                vuint32_t CONT_SCKE:1;
-                vuint32_t DCONF:2;
-                vuint32_t FRZ:1;
-                vuint32_t MTFE:1;
-                vuint32_t PCSSE:1;
-                vuint32_t ROOE:1;
-                  vuint32_t:2;
-                vuint32_t PCSIS5:1;
-                vuint32_t PCSIS4:1;
-                vuint32_t PCSIS3:1;
-                vuint32_t PCSIS2:1;
-                vuint32_t PCSIS1:1;
-                vuint32_t PCSIS0:1;
-                vuint32_t DOZE:1;
-                vuint32_t MDIS:1;
-                vuint32_t DIS_TXF:1;
-                vuint32_t DIS_RXF:1;
-                vuint32_t CLR_TXF:1;
-                vuint32_t CLR_RXF:1;
-                vuint32_t SMPL_PT:2;
-                  vuint32_t:7;
-                vuint32_t HALT:1;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        uint32_t dspi_reserved1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCNT:16;
-                  vuint32_t:16;
-            } B;
-        } TCR;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DBR:1;
-                vuint32_t FMSZ:4;
-                vuint32_t CPOL:1;
-                vuint32_t CPHA:1;
-                vuint32_t LSBFE:1;
-                vuint32_t PCSSCK:2;
-                vuint32_t PASC:2;
-                vuint32_t PDT:2;
-                vuint32_t PBR:2;
-                vuint32_t CSSCK:4;
-                vuint32_t ASC:4;
-                vuint32_t DT:4;
-                vuint32_t BR:4;
-            } B;
-        } CTAR[8];              /* Clock and Transfer Attributes Registers */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCF:1;
-                vuint32_t TXRXS:1;
-                  vuint32_t:1;
-                vuint32_t EOQF:1;
-                vuint32_t TFUF:1;
-                  vuint32_t:1;
-                vuint32_t TFFF:1;
-                  vuint32_t:5;
-                vuint32_t RFOF:1;
-                  vuint32_t:1;
-                vuint32_t RFDF:1;
-                  vuint32_t:1;
-                vuint32_t TXCTR:4;
-                vuint32_t TXNXTPTR:4;
-                vuint32_t RXCTR:4;
-                vuint32_t POPNXTPTR:4;
-            } B;
-        } SR;                   /* Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCFRE:1;
-                  vuint32_t:2;
-                vuint32_t EOQFRE:1;
-                vuint32_t TFUFRE:1;
-                  vuint32_t:1;
-                vuint32_t TFFFRE:1;
-                vuint32_t TFFFDIRS:1;
-                  vuint32_t:4;
-                vuint32_t RFOFRE:1;
-                  vuint32_t:1;
-                vuint32_t RFDFRE:1;
-                vuint32_t RFDFDIRS:1;
-                  vuint32_t:16;
-            } B;
-        } RSER;                 /* DMA/Interrupt Request Select and Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CONT:1;
-                vuint32_t CTAS:3;
-                vuint32_t EOQ:1;
-                vuint32_t CTCNT:1;
-                  vuint32_t:4;
-                vuint32_t PCS5:1;
-                vuint32_t PCS4:1;
-                vuint32_t PCS3:1;
-                vuint32_t PCS2:1;
-                vuint32_t PCS1:1;
-                vuint32_t PCS0:1;
-                vuint32_t TXDATA:16;
-            } B;
-        } PUSHR;                /* PUSH TX FIFO Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXDATA:16;
-            } B;
-        } POPR;                 /* POP RX FIFO Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TXCMD:16;
-                vuint32_t TXDATA:16;
-            } B;
-        } TXFR[4];              /* Transmit FIFO Registers */
-
-        vuint32_t DSPI_reserved_txf[12];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXDATA:16;
-            } B;
-        } RXFR[4];              /* Transmit FIFO Registers */
-
-        vuint32_t DSPI_reserved_rxf[12];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MTOE:1;
-                  vuint32_t:1;
-                vuint32_t MTOCNT:6;
-                  vuint32_t:4;
-                vuint32_t TXSS:1;
-                vuint32_t TPOL:1;
-                vuint32_t TRRE:1;
-                vuint32_t CID:1;
-                vuint32_t DCONT:1;
-                vuint32_t DSICTAS:3;
-                  vuint32_t:6;
-                vuint32_t DPCS5:1;
-                vuint32_t DPCS4:1;
-                vuint32_t DPCS3:1;
-                vuint32_t DPCS2:1;
-                vuint32_t DPCS1:1;
-                vuint32_t DPCS0:1;
-            } B;
-        } DSICR;                /* DSI Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t SER_DATA:16;
-            } B;
-        } SDR;                  /* DSI Serialization Data Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t ASER_DATA:16;
-            } B;
-        } ASDR;                 /* DSI Alternate Serialization Data Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t COMP_DATA:16;
-            } B;
-        } COMPR;                /* DSI Transmit Comparison Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t DESER_DATA:16;
-            } B;
-        } DDR;                  /* DSI deserialization Data Register */
-
-    };                          /* end of DSPI_tag */
-/****************************************************************************/
-/*                          MODULE : ECSM                                   */
-/****************************************************************************/
-    struct ECSM_tag {
-
-        union {
-            vuint16_t R;
-        } PCT;                  /* ECSM Processor Core Type Register */
-
-        union {
-            vuint16_t R;
-        } REV;                  /* ECSM  Revision Register */
-
-        int32_t ECSM_reserved1;
-
-        union {
-            vuint32_t R;
-        } IMC;                  /* ECSM IPS Module Configuration Register */
-
-        int8_t ECSM_reserved2[7];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t ENBWCR:1;
-                  vuint8_t:3;
-                vuint8_t PRILVL:4;
-            } B;
-        } MWCR;                 /* ECSM Miscellaneous Wakeup Control Register */
-
-        int32_t ECSM_reserved3[2];
-        int8_t ECSM_reserved4[3];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t FB0AI:1;
-                vuint8_t FB0SI:1;
-                vuint8_t FB1AI:1;
-                vuint8_t FB1SI:1;
-                  vuint8_t:4;
-            } B;
-        } MIR;                  /* ECSM Miscellaneous Interrupt Register */
-
-        int32_t ECSM_reserved5;
-
-        union {
-            vuint32_t R;
-        } MUDCR;                /* ECSM Miscellaneous User-Defined Control Register */
-
-        int32_t ECSM_reserved6[6];      /* (0x040- 0x028)/4 = 0x06 */
-        int8_t ECSM_reserved7[3];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:2;
-                vuint8_t ER1BR:1;
-                vuint8_t EF1BR:1;
-                  vuint8_t:2;
-                vuint8_t ERNCR:1;
-                vuint8_t EFNCR:1;
-            } B;
-        } ECR;                  /* ECSM ECC Configuration Register */
-
-        int8_t ECSM_reserved8[3];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:2;
-                vuint8_t R1BC:1;
-                vuint8_t F1BC:1;
-                  vuint8_t:2;
-                vuint8_t RNCE:1;
-                vuint8_t FNCE:1;
-            } B;
-        } ESR;                  /* ECSM ECC Status Register */
-
-        int16_t ECSM_reserved9;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:2;
-                vuint16_t FRC1BI:1;
-                vuint16_t FR11BI:1;
-                  vuint16_t:2;
-                vuint16_t FRCNCI:1;
-                vuint16_t FR1NCI:1;
-                  vuint16_t:1;
-                vuint16_t ERRBIT:7;
-            } B;
-        } EEGR;                 /* ECSM ECC Error Generation Register */
-
-        int32_t ECSM_reserved10;
-
-        union {
-            vuint32_t R;
-        } FEAR;                 /* ECSM Flash ECC Address Register */
-
-        int16_t ECSM_reserved11;
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t FEMR:4;
-            } B;
-        } FEMR;                 /* ECSM Flash ECC Master Number Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t WRITE:1;
-                vuint8_t SIZE:3;
-                vuint8_t PROTECTION:4;
-            } B;
-        } FEAT;                 /* ECSM Flash ECC Attributes Register */
-
-        int32_t ECSM_reserved12;
-
-        union {
-            vuint32_t R;
-        } FEDR;                 /* ECSM Flash ECC Data Register */
-
-        union {
-            vuint32_t R;
-        } REAR;                 /* ECSM RAM ECC Address Register */
-
-        int8_t ECSM_reserved13;
-
-        union {
-            vuint8_t R;
-        } RESR;                 /* ECSM RAM ECC Address Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t REMR:4;
-            } B;
-        } REMR;                 /* ECSM RAM ECC Master Number Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t WRITE:1;
-                vuint8_t SIZE:3;
-                vuint8_t PROTECTION:4;
-            } B;
-        } REAT;                 /* ECSM RAM ECC Attributes Register */
-
-        int32_t ECSM_reserved14;
-
-        union {
-            vuint32_t R;
-        } REDR;                 /* ECSM RAM ECC Data Register */
-
-    };                          /* end of ECSM_tag */
-/****************************************************************************/
-/*                          MODULE : EMIOS                                  */
-/****************************************************************************/
-    struct EMIOS_CHANNEL_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t CADR:16;
-            } B;
-        } CADR;                 /* Channel A Data Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t CBDR:16;
-            } B;
-        } CBDR;                 /* Channel B Data Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t CCNTR:16;
-            } B;
-        } CCNTR;                /* Channel Counter Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FREN:1;
-                vuint32_t ODIS:1;
-                vuint32_t ODISSL:2;
-                vuint32_t UCPRE:2;
-                vuint32_t UCPEN:1;
-                vuint32_t DMA:1;
-                  vuint32_t:1;
-                vuint32_t IF:4;
-                vuint32_t FCK:1;
-                vuint32_t FEN:1;
-                  vuint32_t:3;
-                vuint32_t FORCMA:1;
-                vuint32_t FORCMB:1;
-                  vuint32_t:1;
-                vuint32_t BSL:2;
-                vuint32_t EDSEL:1;
-                vuint32_t EDPOL:1;
-                vuint32_t MODE:7;
-            } B;
-        } CCR;                  /* Channel Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t OVR:1;
-                  vuint32_t:15;
-                vuint32_t OVFL:1;
-                  vuint32_t:12;
-                vuint32_t UCIN:1;
-                vuint32_t UCOUT:1;
-                vuint32_t FLAG:1;
-            } B;
-        } CSR;                  /* Channel Status Register */
-
-        union {
-            vuint32_t R;        /* Alternate Channel A Data Register */
-        } ALTCADR;
-
-        uint32_t emios_channel_reserved[2];
-
-    };                          /* end of EMIOS_CHANNEL_tag */
-
-    struct EMIOS_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:1;
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-                vuint32_t GTBE:1;
-                vuint32_t ETB:1;
-                vuint32_t GPREN:1;
-                  vuint32_t:6;
-                vuint32_t SRV:4;
-                vuint32_t GPRE:8;
-                  vuint32_t:8;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t F27:1;
-                vuint32_t F26:1;
-                vuint32_t F25:1;
-                vuint32_t F24:1;
-                vuint32_t F23:1;
-                vuint32_t F22:1;
-                vuint32_t F21:1;
-                vuint32_t F20:1;
-                vuint32_t F19:1;
-                vuint32_t F18:1;
-                vuint32_t F17:1;
-                vuint32_t F16:1;
-                vuint32_t F15:1;
-                vuint32_t F14:1;
-                vuint32_t F13:1;
-                vuint32_t F12:1;
-                vuint32_t F11:1;
-                vuint32_t F10:1;
-                vuint32_t F9:1;
-                vuint32_t F8:1;
-                vuint32_t F7:1;
-                vuint32_t F6:1;
-                vuint32_t F5:1;
-                vuint32_t F4:1;
-                vuint32_t F3:1;
-                vuint32_t F2:1;
-                vuint32_t F1:1;
-                vuint32_t F0:1;
-            } B;
-        } GFR;                  /* Global FLAG Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t OU27:1;
-                vuint32_t OU26:1;
-                vuint32_t OU25:1;
-                vuint32_t OU24:1;
-                vuint32_t OU23:1;
-                vuint32_t OU22:1;
-                vuint32_t OU21:1;
-                vuint32_t OU20:1;
-                vuint32_t OU19:1;
-                vuint32_t OU18:1;
-                vuint32_t OU17:1;
-                vuint32_t OU16:1;
-                vuint32_t OU15:1;
-                vuint32_t OU14:1;
-                vuint32_t OU13:1;
-                vuint32_t OU12:1;
-                vuint32_t OU11:1;
-                vuint32_t OU10:1;
-                vuint32_t OU9:1;
-                vuint32_t OU8:1;
-                vuint32_t OU7:1;
-                vuint32_t OU6:1;
-                vuint32_t OU5:1;
-                vuint32_t OU4:1;
-                vuint32_t OU3:1;
-                vuint32_t OU2:1;
-                vuint32_t OU1:1;
-                vuint32_t OU0:1;
-            } B;
-        } OUDR;                 /* Output Update Disable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t CHDIS27:1;
-                vuint32_t CHDIS26:1;
-                vuint32_t CHDIS25:1;
-                vuint32_t CHDIS24:1;
-                vuint32_t CHDIS23:1;
-                vuint32_t CHDIS22:1;
-                vuint32_t CHDIS21:1;
-                vuint32_t CHDIS20:1;
-                vuint32_t CHDIS19:1;
-                vuint32_t CHDIS18:1;
-                vuint32_t CHDIS17:1;
-                vuint32_t CHDIS16:1;
-                vuint32_t CHDIS15:1;
-                vuint32_t CHDIS14:1;
-                vuint32_t CHDIS13:1;
-                vuint32_t CHDIS12:1;
-                vuint32_t CHDIS11:1;
-                vuint32_t CHDIS10:1;
-                vuint32_t CHDIS9:1;
-                vuint32_t CHDIS8:1;
-                vuint32_t CHDIS7:1;
-                vuint32_t CHDIS6:1;
-                vuint32_t CHDIS5:1;
-                vuint32_t CHDIS4:1;
-                vuint32_t CHDIS3:1;
-                vuint32_t CHDIS2:1;
-                vuint32_t CHDIS1:1;
-                vuint32_t CHDIS0:1;
-            } B;
-        } UCDIS;                /* Disable Channel Register */
-
-        uint32_t emios_reserved1[4];
-
-        struct EMIOS_CHANNEL_tag CH[28];
-
-    };                          /* end of EMIOS_tag */
-/****************************************************************************/
-/*                          MODULE : FlexCAN                                */
-/****************************************************************************/
-    struct FLEXCAN_BUF_t {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t CODE:4;
-                  vuint32_t:1;
-                vuint32_t SRR:1;
-                vuint32_t IDE:1;
-                vuint32_t RTR:1;
-                vuint32_t LENGTH:4;
-                vuint32_t TIMESTAMP:16;
-            } B;
-        } CS;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRIO:3;
-                vuint32_t STD_ID:11;
-                vuint32_t EXT_ID:18;
-            } B;
-        } ID;
-
-        union {
-            vuint8_t B[8];      /* Data buffer in Bytes (8 bits) */
-            vuint16_t H[4];     /* Data buffer in Half-words (16 bits) */
-            vuint32_t W[2];     /* Data buffer in words (32 bits) */
-            vuint32_t R[2];     /* Data buffer in words (32 bits) */
-        } DATA;
-
-    };                          /* end of FLEXCAN_BUF_t */
-
-    struct FLEXCAN_RXFIFO_t {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:9;
-                vuint32_t SRR:1;
-                vuint32_t IDE:1;
-                vuint32_t RTR:1;
-                vuint32_t LENGTH:4;
-                vuint32_t TIMESTAMP:16;
-            } B;
-        } CS;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t STD_ID:11;
-                vuint32_t EXT_ID:18;
-            } B;
-        } ID;
-
-        union {
-            vuint8_t B[8];      /* Data buffer in Bytes (8 bits) */
-            vuint16_t H[4];     /* Data buffer in Half-words (16 bits) */
-            vuint32_t W[2];     /* Data buffer in words (32 bits) */
-            vuint32_t R[2];     /* Data buffer in words (32 bits) */
-        } DATA;
-
-        uint32_t FLEXCAN_RXFIFO_reserved[20];   /* {0x00E0-0x0090}/0x4 = 0x14 */
-
-        union {
-            vuint32_t R;
-        } IDTABLE[8];
-
-    };                          /* end of FLEXCAN_RXFIFO_t */
-
-    struct FLEXCAN_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-                vuint32_t FEN:1;
-                vuint32_t HALT:1;
-                vuint32_t NOTRDY:1;
-                vuint32_t WAKMSK:1;
-                vuint32_t SOFTRST:1;
-                vuint32_t FRZACK:1;
-                vuint32_t SUPV:1;
-                vuint32_t SLFWAK:1;
-                vuint32_t WRNEN:1;
-                vuint32_t LPMACK:1;
-                vuint32_t WAKSRC:1;
-                vuint32_t DOZE:1;
-                vuint32_t SRXDIS:1;
-                vuint32_t BCC:1;
-                  vuint32_t:2;
-                vuint32_t LPRIO_EN:1;
-                vuint32_t AEN:1;
-                  vuint32_t:2;
-                vuint32_t IDAM:2;
-                  vuint32_t:2;
-                vuint32_t MAXMB:6;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRESDIV:8;
-                vuint32_t RJW:2;
-                vuint32_t PSEG1:3;
-                vuint32_t PSEG2:3;
-                vuint32_t BOFFMSK:1;
-                vuint32_t ERRMSK:1;
-                vuint32_t CLKSRC:1;
-                vuint32_t LPB:1;
-                vuint32_t TWRNMSK:1;
-                vuint32_t RWRNMSK:1;
-                  vuint32_t:2;
-                vuint32_t SMP:1;
-                vuint32_t BOFFREC:1;
-                vuint32_t TSYN:1;
-                vuint32_t LBUF:1;
-                vuint32_t LOM:1;
-                vuint32_t PROPSEG:3;
-            } B;
-        } CR;                   /* Control Register */
-
-        union {
-            vuint32_t R;
-        } TIMER;                /* Free Running Timer */
-
-        uint32_t FLEXCAN_reserved1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;
-        } RXGMASK;              /* RX Global Mask */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;
-        } RX14MASK;             /* RX 14 Mask */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;
-        } RX15MASK;             /* RX 15 Mask */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXECNT:8;
-                vuint32_t TXECNT:8;
-            } B;
-        } ECR;                  /* Error Counter Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t TWRNINT:1;
-                vuint32_t RWRNINT:1;
-                vuint32_t BIT1ERR:1;
-                vuint32_t BIT0ERR:1;
-                vuint32_t ACKERR:1;
-                vuint32_t CRCERR:1;
-                vuint32_t FRMERR:1;
-                vuint32_t STFERR:1;
-                vuint32_t TXWRN:1;
-                vuint32_t RXWRN:1;
-                vuint32_t IDLE:1;
-                vuint32_t TXRX:1;
-                vuint32_t FLTCONF:2;
-                  vuint32_t:1;
-                vuint32_t BOFFINT:1;
-                vuint32_t ERRINT:1;
-                vuint32_t WAKINT:1;
-            } B;
-        } ESR;                  /* Error and Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF63M:1;
-                vuint32_t BUF62M:1;
-                vuint32_t BUF61M:1;
-                vuint32_t BUF60M:1;
-                vuint32_t BUF59M:1;
-                vuint32_t BUF58M:1;
-                vuint32_t BUF57M:1;
-                vuint32_t BUF56M:1;
-                vuint32_t BUF55M:1;
-                vuint32_t BUF54M:1;
-                vuint32_t BUF53M:1;
-                vuint32_t BUF52M:1;
-                vuint32_t BUF51M:1;
-                vuint32_t BUF50M:1;
-                vuint32_t BUF49M:1;
-                vuint32_t BUF48M:1;
-                vuint32_t BUF47M:1;
-                vuint32_t BUF46M:1;
-                vuint32_t BUF45M:1;
-                vuint32_t BUF44M:1;
-                vuint32_t BUF43M:1;
-                vuint32_t BUF42M:1;
-                vuint32_t BUF41M:1;
-                vuint32_t BUF40M:1;
-                vuint32_t BUF39M:1;
-                vuint32_t BUF38M:1;
-                vuint32_t BUF37M:1;
-                vuint32_t BUF36M:1;
-                vuint32_t BUF35M:1;
-                vuint32_t BUF34M:1;
-                vuint32_t BUF33M:1;
-                vuint32_t BUF32M:1;
-            } B;
-        } IMRH;                 /* Interruput Masks Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF31M:1;
-                vuint32_t BUF30M:1;
-                vuint32_t BUF29M:1;
-                vuint32_t BUF28M:1;
-                vuint32_t BUF27M:1;
-                vuint32_t BUF26M:1;
-                vuint32_t BUF25M:1;
-                vuint32_t BUF24M:1;
-                vuint32_t BUF23M:1;
-                vuint32_t BUF22M:1;
-                vuint32_t BUF21M:1;
-                vuint32_t BUF20M:1;
-                vuint32_t BUF19M:1;
-                vuint32_t BUF18M:1;
-                vuint32_t BUF17M:1;
-                vuint32_t BUF16M:1;
-                vuint32_t BUF15M:1;
-                vuint32_t BUF14M:1;
-                vuint32_t BUF13M:1;
-                vuint32_t BUF12M:1;
-                vuint32_t BUF11M:1;
-                vuint32_t BUF10M:1;
-                vuint32_t BUF09M:1;
-                vuint32_t BUF08M:1;
-                vuint32_t BUF07M:1;
-                vuint32_t BUF06M:1;
-                vuint32_t BUF05M:1;
-                vuint32_t BUF04M:1;
-                vuint32_t BUF03M:1;
-                vuint32_t BUF02M:1;
-                vuint32_t BUF01M:1;
-                vuint32_t BUF00M:1;
-            } B;
-        } IMRL;                 /* Interruput Masks Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF63I:1;
-                vuint32_t BUF62I:1;
-                vuint32_t BUF61I:1;
-                vuint32_t BUF60I:1;
-                vuint32_t BUF59I:1;
-                vuint32_t BUF58I:1;
-                vuint32_t BUF57I:1;
-                vuint32_t BUF56I:1;
-                vuint32_t BUF55I:1;
-                vuint32_t BUF54I:1;
-                vuint32_t BUF53I:1;
-                vuint32_t BUF52I:1;
-                vuint32_t BUF51I:1;
-                vuint32_t BUF50I:1;
-                vuint32_t BUF49I:1;
-                vuint32_t BUF48I:1;
-                vuint32_t BUF47I:1;
-                vuint32_t BUF46I:1;
-                vuint32_t BUF45I:1;
-                vuint32_t BUF44I:1;
-                vuint32_t BUF43I:1;
-                vuint32_t BUF42I:1;
-                vuint32_t BUF41I:1;
-                vuint32_t BUF40I:1;
-                vuint32_t BUF39I:1;
-                vuint32_t BUF38I:1;
-                vuint32_t BUF37I:1;
-                vuint32_t BUF36I:1;
-                vuint32_t BUF35I:1;
-                vuint32_t BUF34I:1;
-                vuint32_t BUF33I:1;
-                vuint32_t BUF32I:1;
-            } B;
-        } IFRH;                 /* Interruput Flag Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF31I:1;
-                vuint32_t BUF30I:1;
-                vuint32_t BUF29I:1;
-                vuint32_t BUF28I:1;
-                vuint32_t BUF27I:1;
-                vuint32_t BUF26I:1;
-                vuint32_t BUF25I:1;
-                vuint32_t BUF24I:1;
-                vuint32_t BUF23I:1;
-                vuint32_t BUF22I:1;
-                vuint32_t BUF21I:1;
-                vuint32_t BUF20I:1;
-                vuint32_t BUF19I:1;
-                vuint32_t BUF18I:1;
-                vuint32_t BUF17I:1;
-                vuint32_t BUF16I:1;
-                vuint32_t BUF15I:1;
-                vuint32_t BUF14I:1;
-                vuint32_t BUF13I:1;
-                vuint32_t BUF12I:1;
-                vuint32_t BUF11I:1;
-                vuint32_t BUF10I:1;
-                vuint32_t BUF09I:1;
-                vuint32_t BUF08I:1;
-                vuint32_t BUF07I:1;
-                vuint32_t BUF06I:1;
-                vuint32_t BUF05I:1;
-                vuint32_t BUF04I:1;
-                vuint32_t BUF03I:1;
-                vuint32_t BUF02I:1;
-                vuint32_t BUF01I:1;
-                vuint32_t BUF00I:1;
-            } B;
-        } IFRL;                 /* Interruput Flag Register */
-
-        uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */
-
-/****************************************************************************/
-/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure     */
-/****************************************************************************/
-        /* Standard Buffer Structure */
-        struct FLEXCAN_BUF_t BUF[64];
-
-        /* RX FIFO and Buffer Structure */
-        /*struct FLEXCAN_RXFIFO_t RXFIFO; */
-        /*struct FLEXCAN_BUF_t BUF[56];   */
-/****************************************************************************/
-
-        uint32_t FLEXCAN_reserved3[256];        /* {0x0880-0x0480}/0x4 = 0x100 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;
-        } RXIMR[64];            /* RX Individual Mask Registers */
-
-    };                          /* end of FLEXCAN_tag */
-/****************************************************************************/
-/*                          MODULE : i2c                                    */
-/****************************************************************************/
-    struct I2C_tag {
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t ADR:7;
-                  vuint8_t:1;
-            } B;
-        } IBAD;                 /* Module Bus Address Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t IBC:8;
-            } B;
-        } IBFD;                 /* Module Bus Frequency Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t MDIS:1;
-                vuint8_t IBIE:1;
-                vuint8_t MS:1;
-                vuint8_t TX:1;
-                vuint8_t NOACK:1;
-                vuint8_t RSTA:1;
-                vuint8_t DMAEN:1;
-                vuint8_t IBDOZE:1;
-            } B;
-        } IBCR;                 /* Module Bus Control Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t TCF:1;
-                vuint8_t IAAS:1;
-                vuint8_t IBB:1;
-                vuint8_t IBAL:1;
-                  vuint8_t:1;
-                vuint8_t SRW:1;
-                vuint8_t IBIF:1;
-                vuint8_t RXAK:1;
-            } B;
-        } IBSR;                 /* Module Status Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t DATA:8;
-            } B;
-        } IBDR;                 /* Module Data Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t BIIE:1;
-                  vuint8_t:7;
-            } B;
-        } IBIC;                 /* Module Interrupt Configuration Register */
-
-    };                          /* end of I2C_tag */
-/****************************************************************************/
-/*                          MODULE : INTC                                   */
-/****************************************************************************/
-    struct INTC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:26;
-                vuint32_t VTES:1;
-                  vuint32_t:4;
-                vuint32_t HVEN:1;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t PRI:4;
-            } B;
-        } CPR;                  /* Current Priority Register */
-
-        int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t VTBA:21;
-                vuint32_t INTVEC:9;
-                  vuint32_t:2;
-            } B;
-        } IACKR;                /* Interrupt Acknowledge Register */
-
-        int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:32;
-            } B;
-        } EOIR;                 /* End of Interrupt Register */
-
-        int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:6;
-                vuint8_t SET:1;
-                vuint8_t CLR:1;
-            } B;
-        } SSCIR[8];             /* Software Set/Clear Interruput Register */
-
-        uint32_t intc_reserved5[6];     /* (0x040 - 0x028)/4 = 0x06 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t PRI:4;
-            } B;
-        } PSR[512];             /* Software Set/Clear Interrupt Register */
-
-    };                          /* end of INTC_tag */
-/****************************************************************************/
-/*                          MODULE : LINFLEX                                */
-/****************************************************************************/
-
-    struct LINFLEX_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t CCD:1;
-                vuint32_t CFD:1;
-                vuint32_t LASE:1;
-                vuint32_t AWUM:1;
-                vuint32_t MBL:4;
-                vuint32_t BF:1;
-                vuint32_t SLFM:1;
-                vuint32_t LBKM:1;
-                vuint32_t MME:1;
-                vuint32_t SBDT:1;
-                vuint32_t RBLM:1;
-                vuint32_t SLEEP:1;
-                vuint32_t INIT:1;
-            } B;
-        } LINCR1;               /* LINFLEX LIN Control Register 1 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t SZIE:1;
-                vuint32_t OCIE:1;
-                vuint32_t BEIE:1;
-                vuint32_t CEIE:1;
-                vuint32_t HEIE:1;
-                  vuint32_t:2;
-                vuint32_t FEIE:1;
-                vuint32_t BOIE:1;
-                vuint32_t LSIE:1;
-                vuint32_t WUIE:1;
-                vuint32_t DBFIE:1;
-                vuint32_t DBEIE:1;
-                vuint32_t DRIE:1;
-                vuint32_t DTIE:1;
-                vuint32_t HRIE:1;
-            } B;
-        } LINIER;               /* LINFLEX LIN Interrupt Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t LINS:4;
-                  vuint32_t:2;
-                vuint32_t RMB:1;
-                  vuint32_t:1;
-                vuint32_t RBSY:1;
-                vuint32_t RPS:1;
-                vuint32_t WUF:1;
-                vuint32_t DBFF:1;
-                vuint32_t DBEF:1;
-                vuint32_t DRF:1;
-                vuint32_t DTF:1;
-                vuint32_t HRF:1;
-            } B;
-        } LINSR;                /* LINFLEX LIN Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t SZF:1;
-                vuint32_t OCF:1;
-                vuint32_t BEF:1;
-                vuint32_t CEF:1;
-                vuint32_t SFEF:1;
-                vuint32_t SDEF:1;
-                vuint32_t IDPEF:1;
-                vuint32_t FEF:1;
-                vuint32_t BOF:1;
-                  vuint32_t:6;
-                vuint32_t NF:1;
-            } B;
-        } LINESR;               /* LINFLEX LIN Error Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:1;
-                vuint32_t TDFL:2;
-                  vuint32_t:1;
-                vuint32_t RDFL:2;
-                  vuint32_t:4;
-                vuint32_t RXEN:1;
-                vuint32_t TXEN:1;
-                vuint32_t OP:1;
-                vuint32_t PCE:1;
-                vuint32_t WL:1;
-                vuint32_t UART:1;
-            } B;
-        } UARTCR;               /* LINFLEX UART Mode Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t SZF:1;
-                vuint32_t OCF:1;
-                vuint32_t PE:4;
-                vuint32_t RMB:1;
-                vuint32_t FEF:1;
-                vuint32_t BOF:1;
-                vuint32_t RPS:1;
-                vuint32_t WUF:1;
-                  vuint32_t:2;
-                vuint32_t DRF:1;
-                vuint32_t DTF:1;
-                vuint32_t NF:1;
-            } B;
-        } UARTSR;               /* LINFLEX UART Mode Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:5;
-                vuint32_t LTOM:1;
-                vuint32_t IOT:1;
-                vuint32_t TOCE:1;
-                vuint32_t CNT:8;
-            } B;
-        } LINTCSR;              /* LINFLEX LIN Time-Out Control Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t OC2:8;
-                vuint32_t OC1:8;
-            } B;
-        } LINOCR;               /* LINFLEX LIN Output Compare Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:4;
-                vuint32_t RTO:4;
-                  vuint32_t:1;
-                vuint32_t HTO:7;
-            } B;
-        } LINTOCR;              /* LINFLEX LIN Output Compare Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:12;
-                vuint32_t DIV_F:4;
-            } B;
-        } LINFBRR;              /* LINFLEX LIN Fractional Baud Rate Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:3;
-                vuint32_t DIV_M:13;
-            } B;
-        } LINIBRR;              /* LINFLEX LIN Integer Baud Rate Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:8;
-                vuint32_t CF:8;
-            } B;
-        } LINCFR;               /* LINFLEX LIN Checksum Field Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:1;
-                vuint32_t IOBE:1;
-                vuint32_t IOPE:1;
-                vuint32_t WURQ:1;
-                vuint32_t DDRQ:1;
-                vuint32_t DTRQ:1;
-                vuint32_t ABRQ:1;
-                vuint32_t HTRQ:1;
-                  vuint32_t:8;
-            } B;
-        } LINCR2;               /* LINFLEX LIN Control Register 2 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t DFL:6;
-                vuint32_t DIR:1;
-                vuint32_t CCS:1;
-                  vuint32_t:2;
-                vuint32_t ID:6;
-            } B;
-        } BIDR;                 /* LINFLEX Buffer Identifier Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DATA3:8;
-                vuint32_t DATA2:8;
-                vuint32_t DATA1:8;
-                vuint32_t DATA0:8;
-            } B;
-        } BDRL;                 /* LINFLEX Buffer Data Register Least Significant */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DATA7:8;
-                vuint32_t DATA6:8;
-                vuint32_t DATA5:8;
-                vuint32_t DATA4:8;
-            } B;
-        } BDRM;                 /* LINFLEX Buffer Data Register Most Significant */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:8;
-                vuint32_t FACT:8;
-            } B;
-        } IFER;                 /* LINFLEX Identifier Filter Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:12;
-                vuint32_t IFMI:4;
-            } B;
-        } IFMI;                 /* LINFLEX Identifier Filter Match Index Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:12;
-                vuint32_t IFM:4;
-            } B;
-        } IFMR;                 /* LINFLEX Identifier Filter Mode Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t:3;
-                vuint32_t DFL:3;
-                vuint32_t DIR:1;
-                vuint32_t CCS:1;
-                  vuint32_t:2;
-                vuint32_t ID:6;
-            } B;
-        } IFCR[16];             /* LINFLEX Identifier Filter Control Register 0-15 */
-
-    };                          /* end of LINFLEX_tag */
-/****************************************************************************/
-/*                          MODULE : ME                                   */
-/****************************************************************************/
-    struct ME_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t S_CURRENTMODE:4;
-                vuint32_t S_MTRANS:1;
-                vuint32_t S_DC:1;
-                  vuint32_t:2;
-                vuint32_t S_PDO:1;
-                  vuint32_t:2;
-                vuint32_t S_MVR:1;
-                vuint32_t S_DFLA:2;
-                vuint32_t S_CFLA:2;
-                  vuint32_t:9;
-                vuint32_t S_FMPLL:1;
-                vuint32_t S_FXOSC:1;
-                vuint32_t S_FIRC:1;
-                vuint32_t S_SYSCLK:4;
-            } B;
-        } GS;                   /* Global Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TARGET_MODE:4;
-                  vuint32_t:12;
-                vuint32_t KEY:16;
-            } B;
-        } MCTL;                 /* Mode Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:18;
-                vuint32_t STANDBY0:1;
-                  vuint32_t:2;
-                vuint32_t STOP0:1;
-                  vuint32_t:1;
-                vuint32_t HALT0:1;
-                vuint32_t RUN3:1;
-                vuint32_t RUN2:1;
-                vuint32_t RUN1:1;
-                vuint32_t RUN0:1;
-                vuint32_t DRUN:1;
-                vuint32_t SAFE:1;
-                vuint32_t TEST:1;
-                vuint32_t RESET:1;
-            } B;
-        } MER;                  /* Mode Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t I_CONF:1;
-                vuint32_t I_MODE:1;
-                vuint32_t I_SAFE:1;
-                vuint32_t I_MTC:1;
-            } B;
-        } IS;                   /* Interrupt Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t M_CONF:1;
-                vuint32_t M_MODE:1;
-                vuint32_t M_SAFE:1;
-                vuint32_t M_MTC:1;
-            } B;
-        } IM;                   /* Interrupt Mask Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:27;
-                vuint32_t S_MTI:1;
-                vuint32_t S_MRI:1;
-                vuint32_t S_DMA:1;
-                vuint32_t S_NMA:1;
-                vuint32_t S_SEA:1;
-            } B;
-        } IMTS;                 /* Invalid Mode Transition Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t MPH_BUSY:1;
-                  vuint32_t:2;
-                vuint32_t PMC_PROG:1;
-                vuint32_t CORE_DBG:1;
-                  vuint32_t:2;
-                vuint32_t SMR:1;
-                  vuint32_t:1;
-                vuint32_t FMPLL_SC:1;
-                vuint32_t FXOSC_SC:1;
-                vuint32_t FIRC_SC:1;
-                  vuint32_t:1;
-                vuint32_t SYSCLK_SW:1;
-                vuint32_t DFLASH_SC:1;
-                vuint32_t CFLASH_SC:1;
-                vuint32_t CDP_PRPH_0_143:1;
-                  vuint32_t:3;
-                vuint32_t CDP_PRPH_96_127:1;
-                vuint32_t CDP_PRPH_64_95:1;
-                vuint32_t CDP_PRPH_32_63:1;
-                vuint32_t CDP_PRPH_0_31:1;
-            } B;
-        } DMTS;                 /* Invalid Mode Transition Status Register */
-
-        int32_t ME_reserved0;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:9;
-                vuint32_t FMPLLON:1;
-                vuint32_t FXOSC0ON:1;
-                vuint32_t FIRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } RESET;                /* Reset Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:9;
-                vuint32_t FMPLLON:1;
-                vuint32_t FXOSC0ON:1;
-                vuint32_t FIRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } TEST;                 /* Test Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:9;
-                vuint32_t FMPLLON:1;
-                vuint32_t FXOSC0ON:1;
-                vuint32_t FIRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } SAFE;                 /* Safe Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:9;
-                vuint32_t FMPLLON:1;
-                vuint32_t FXOSC0ON:1;
-                vuint32_t FIRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } DRUN;                 /* DRUN Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:9;
-                vuint32_t FMPLLON:1;
-                vuint32_t FXOSC0ON:1;
-                vuint32_t FIRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } RUN[4];               /* RUN 0->4 Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:9;
-                vuint32_t FMPLLON:1;
-                vuint32_t FXOSC0ON:1;
-                vuint32_t FIRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } HALT0;                /* HALT0 Mode Configuration Register */
-
-        int32_t ME_reserved1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:9;
-                vuint32_t FMPLLON:1;
-                vuint32_t FXOSC0ON:1;
-                vuint32_t FIRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } STOP0;                /* STOP0 Mode Configuration Register */
-
-        int32_t ME_reserved2[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:9;
-                vuint32_t FMPLLON:1;
-                vuint32_t FXOSC0ON:1;
-                vuint32_t FIRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } STANDBY0;             /* STANDBY0 Mode Configuration Register */
-
-        int32_t ME_reserved3[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:10;
-                vuint32_t S_FLEXCAN5:1;
-                vuint32_t S_FLEXCAN4:1;
-                vuint32_t S_FLEXCAN3:1;
-                vuint32_t S_FLEXCAN2:1;
-                vuint32_t S_FLEXCAN1:1;
-                vuint32_t S_FLEXCAN0:1;
-                  vuint32_t:9;
-                vuint32_t S_DSPI2:1;
-                vuint32_t S_DSPI1:1;
-                vuint32_t S_DSPI0:1;
-                  vuint32_t:4;
-            } B;
-        } PS0;                  /* Peripheral Status Register 0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t S_CANSAMPLER:1;
-                  vuint32_t:2;
-                vuint32_t S_CTU:1;
-                  vuint32_t:5;
-                vuint32_t S_LINFLEX3:1;
-                vuint32_t S_LINFLEX2:1;
-                vuint32_t S_LINFLEX1:1;
-                vuint32_t S_LINFLEX0:1;
-                  vuint32_t:3;
-                vuint32_t S_I2C:1;
-                  vuint32_t:11;
-                vuint32_t S_ADC:1;
-            } B;
-        } PS1;                  /* Peripheral Status Register 1 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t S_PIT_RTI:1;
-                vuint32_t S_RTC_API:1;
-                  vuint32_t:18;
-                vuint32_t S_EMIOS:1;
-                  vuint32_t:2;
-                vuint32_t S_WKUP:1;
-                vuint32_t S_SIU:1;
-                  vuint32_t:4;
-            } B;
-        } PS2;                  /* Peripheral Status Register 2 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:23;
-                vuint32_t S_CMU:1;
-                  vuint32_t:8;
-            } B;
-        } PS3;                  /* Peripheral Status Register 3 */
-
-        int32_t ME_reserved4[4];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t RUN3:1;
-                vuint32_t RUN2:1;
-                vuint32_t RUN1:1;
-                vuint32_t RUN0:1;
-                vuint32_t DRUN:1;
-                vuint32_t SAFE:1;
-                vuint32_t TEST:1;
-                vuint32_t RESET:1;
-            } B;
-        } RUNPC[8];             /* RUN Peripheral Configuration 0->7 Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:18;
-                vuint32_t STANDBY0:1;
-                  vuint32_t:2;
-                vuint32_t STOP0:1;
-                  vuint32_t:1;
-                vuint32_t HALT0:1;
-                  vuint32_t:8;
-            } B;
-        } LPPC[8];              /* Low Power Peripheral Configuration 0->7 Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t DBG_F:1;
-                vuint8_t LP_CFG:3;
-                vuint8_t RUN_CFG:3;
-            } B;
-        } PCTL[144];            /* Peripheral Control 0->143 Register */
-
-    };                          /* end of ME_tag */
-/****************************************************************************/
-/*                          MODULE : MPU                                    */
-/****************************************************************************/
-    struct MPU_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SPERR:8;
-                  vuint32_t:4;
-                vuint32_t HRL:4;
-                vuint32_t NSP:4;
-                vuint32_t NGRD:4;
-                  vuint32_t:7;
-                vuint32_t VLD:1;
-            } B;
-        } CESR;                 /* Module Control/Error Status Register */
-
-        uint32_t mpu_reserved1[3];      /* (0x010 - 0x004)/4 = 0x03 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EADDR:32;
-            } B;
-        } EAR0;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EACD:16;
-                vuint32_t EPID:8;
-                vuint32_t EMN:4;
-                vuint32_t EATTR:3;
-                vuint32_t ERW:1;
-            } B;
-        } EDR0;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EADDR:32;
-            } B;
-        } EAR1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EACD:16;
-                vuint32_t EPID:8;
-                vuint32_t EMN:4;
-                vuint32_t EATTR:3;
-                vuint32_t ERW:1;
-            } B;
-        } EDR1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EADDR:32;
-            } B;
-        } EAR2;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EACD:16;
-                vuint32_t EPID:8;
-                vuint32_t EMN:4;
-                vuint32_t EATTR:3;
-                vuint32_t ERW:1;
-            } B;
-        } EDR2;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EADDR:32;
-            } B;
-        } EAR3;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EACD:16;
-                vuint32_t EPID:8;
-                vuint32_t EMN:4;
-                vuint32_t EATTR:3;
-                vuint32_t ERW:1;
-            } B;
-        } EDR3;
-
-        uint32_t mpu_reserved2[244];    /* (0x0400 - 0x0030)/4 = 0x0F4 */
-
-        struct {
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t SRTADDR:27;
-                      vuint32_t:5;
-                } B;
-            } WORD0;            /* Region Descriptor n Word 0 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t ENDADDR:27;
-                      vuint32_t:5;
-                } B;
-            } WORD1;            /* Region Descriptor n Word 1 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t M7RE:1;
-                    vuint32_t M7WE:1;
-                    vuint32_t M6RE:1;
-                    vuint32_t M6WE:1;
-                    vuint32_t M5RE:1;
-                    vuint32_t M5WE:1;
-                    vuint32_t M4RE:1;
-                    vuint32_t M4WE:1;
-                    vuint32_t M3PE:1;
-                    vuint32_t M3SM:2;
-                    vuint32_t M3UM:3;
-                    vuint32_t M2PE:1;
-                    vuint32_t M2SM:2;
-                    vuint32_t M2UM:3;
-                    vuint32_t M1PE:1;
-                    vuint32_t M1SM:2;
-                    vuint32_t M1UM:3;
-                    vuint32_t M0PE:1;
-                    vuint32_t M0SM:2;
-                    vuint32_t M0UM:3;
-                } B;
-            } WORD2;            /* Region Descriptor n Word 2 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t PID:8;
-                    vuint32_t PIDMASK:8;
-                      vuint32_t:15;
-                    vuint32_t VLD:1;
-                } B;
-            } WORD3;            /* Region Descriptor n Word 3 */
-
-        } RGD[16];
-
-        uint32_t mpu_reserved3[192];    /* (0x0800 - 0x0500)/4 = 0x0C0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t M7RE:1;
-                vuint32_t M7WE:1;
-                vuint32_t M6RE:1;
-                vuint32_t M6WE:1;
-                vuint32_t M5RE:1;
-                vuint32_t M5WE:1;
-                vuint32_t M4RE:1;
-                vuint32_t M4WE:1;
-                vuint32_t M3PE:1;
-                vuint32_t M3SM:2;
-                vuint32_t M3UM:3;
-                vuint32_t M2PE:1;
-                vuint32_t M2SM:2;
-                vuint32_t M2UM:3;
-                vuint32_t M1PE:1;
-                vuint32_t M1SM:2;
-                vuint32_t M1UM:3;
-                vuint32_t M0PE:1;
-                vuint32_t M0SM:2;
-                vuint32_t M0UM:3;
-            } B;
-        } RGDAAC[16];           /* Region Descriptor Alternate Access Control n */
-
-    };                          /* end of MPU_tag */
-/****************************************************************************/
-/*                          MODULE : PCU                                   */
-/****************************************************************************/
-    struct PCU_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:18;
-                vuint32_t STBY0:1;
-                  vuint32_t:2;
-                vuint32_t STOP0:1;
-                  vuint32_t:1;
-                vuint32_t HALT0:1;
-                vuint32_t RUN3:1;
-                vuint32_t RUN2:1;
-                vuint32_t RUN1:1;
-                vuint32_t RUN0:1;
-                vuint32_t DRUN:1;
-                vuint32_t SAFE:1;
-                vuint32_t TEST:1;
-                vuint32_t RST:1;
-            } B;
-        } PCONF[3];             /* Power domain 0-2 configuration register */
-
-        int32_t PCU_reserved0[13];      /* (0x040 - 0x00C)/4 = 0x0D */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:29;
-                vuint32_t PD2:1;
-                vuint32_t PD1:1;
-                vuint32_t PD0:1;
-            } B;
-        } PSTAT;                /* Power Domain Status Register */
-
-        int32_t PCU_reserved1[15];      /* {0x0080-0x0044}/0x4 = 0xF */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:15;
-                vuint32_t MASK_LVDHV5:1;
-            } B;
-        } VCTL;                 /* Voltage Regulator Control Register */
-
-    };                          /* end of PCU_tag */
-/****************************************************************************/
-/*                          MODULE : pit                                    */
-/****************************************************************************/
-    struct PIT_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:30;
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-            } B;
-        } PITMCR;
-
-        uint32_t pit_reserved1[63];     /* (0x0100 - 0x0004)/4 = 0x3F */
-
-        struct {
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t TSV:32;
-                } B;
-            } LDVAL;
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t TVL:32;
-                } B;
-            } CVAL;
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:30;
-                    vuint32_t TIE:1;
-                    vuint32_t TEN:1;
-                } B;
-            } TCTRL;
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:31;
-                    vuint32_t TIF:1;
-                } B;
-            } TFLG;
-        } CH[6];
-
-    };                          /* end of PIT_tag */
-/****************************************************************************/
-/*                          MODULE : RGM                                   */
-/****************************************************************************/
-    struct RGM_tag {
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t F_EXR:1;
-                  vuint16_t:6;
-                vuint16_t F_FLASH:1;
-                vuint16_t F_LVD45:1;
-                vuint16_t F_CMU_FHL:1;
-                vuint16_t F_CMU_OLR:1;
-                vuint16_t F_FMPLL:1;
-                vuint16_t F_CHKSTOP:1;
-                vuint16_t F_SOFT:1;
-                vuint16_t F_CORE:1;
-                vuint16_t F_JTAG:1;
-            } B;
-        } FES;                  /* Functional Event Status */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t F_POR:1;
-                  vuint16_t:11;
-                vuint16_t F_LVD27:1;
-                vuint16_t F_SWT:1;
-                vuint16_t F_LVD12_PD1:1;
-                vuint16_t F_LVD12_PD0:1;
-            } B;
-        } DES;                  /* Destructive Event Status */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t D_EXR:1;
-                  vuint16_t:6;
-                vuint16_t D_FLASH:1;
-                vuint16_t D_LVD45:1;
-                vuint16_t D_CMU_FHL:1;
-                vuint16_t D_CMU_OLR:1;
-                vuint16_t D_FMPLL:1;
-                vuint16_t D_CHKSTOP:1;
-                vuint16_t D_SOFT:1;
-                vuint16_t D_CORE:1;
-                vuint16_t D_JTAG:1;
-            } B;
-        } FERD;                 /* Functional Event Reset Disable */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t D_POR:1;
-                  vuint16_t:11;
-                vuint16_t D_LVD27:1;
-                vuint16_t D_SWT:1;
-                vuint16_t D_LVD12_PD1:1;
-                vuint16_t D_LVD12_PD0:1;
-            } B;
-        } DERD;                 /* Destructive Event Reset Disable */
-
-        int16_t RGM_reserved0[4];
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t AR_EXR:1;
-                  vuint16_t:6;
-                vuint16_t AR_FLASH:1;
-                vuint16_t AR_LVD45:1;
-                vuint16_t AR_CMU_FHL:1;
-                vuint16_t AR_CMU_OLR:1;
-                vuint16_t AR_FMPLL:1;
-                vuint16_t AR_CHKSTOP:1;
-                vuint16_t AR_SOFT:1;
-                vuint16_t AR_CORE:1;
-                vuint16_t AR_JTAG:1;
-            } B;
-        } FEAR;                 /* Functional Event Alternate Request */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t AR_LVD27:1;
-                vuint16_t AR_SWT:1;
-                vuint16_t AR_LVD12_PD1:1;
-                vuint16_t AR_LVD12_PD0:1;
-            } B;
-        } DEAR;                 /* Destructive Event Alternate Request */
-
-        int16_t RGM_reserved1[2];
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t SS_LVD45:1;
-                vuint16_t SS_CMU_FHL:1;
-                vuint16_t SS_CMU_OLR:1;
-                vuint16_t SS_PLL:1;
-                vuint16_t SS_CHKSTOP:1;
-                vuint16_t SS_SOFT:1;
-                vuint16_t SS_CORE:1;
-                vuint16_t SS_JTAG:1;
-            } B;
-        } FESS;                 /* Functional Event Short Sequence */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t BOOT_FROM_BKP_RAM:1;
-                  vuint16_t:7;
-            } B;
-        } STDBY;                /* STANDBY reset sequence */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t BE_EXR:1;
-                  vuint16_t:6;
-                vuint16_t BE_FLASH:1;
-                vuint16_t BE_LVD45:1;
-                vuint16_t BE_CMU_FHL:1;
-                vuint16_t BE_CMU_OLR:1;
-                vuint16_t BE_FMPLL:1;
-                vuint16_t BE_CHKSTOP:1;
-                vuint16_t BE_SOFT:1;
-                vuint16_t BE_CORE:1;
-                vuint16_t BE_JTAG:1;
-            } B;
-        } FBRE;                 /* Functional Bidirectional Reset Enable */
-
-    };                          /* end of RGM_tag */
-/****************************************************************************/
-/*                          MODULE : RTC                                   */
-/****************************************************************************/
-    struct RTC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SUPV:1;
-                  vuint32_t:31;
-            } B;
-        } RTCSUPV;              /* RTC Supervisor Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CNTEN:1;
-                vuint32_t RTCIE:1;
-                vuint32_t FRZEN:1;
-                vuint32_t ROVREN:1;
-                vuint32_t RTCVAL:12;
-                vuint32_t APIEN:1;
-                vuint32_t APIIE:1;
-                vuint32_t CLKSEL:2;
-                vuint32_t DIV512EN:1;
-                vuint32_t DIV32EN:1;
-                vuint32_t APIVAL:10;
-            } B;
-        } RTCC;                 /* RTC Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:2;
-                vuint32_t RTCF:1;
-                  vuint32_t:15;
-                vuint32_t APIF:1;
-                  vuint32_t:2;
-                vuint32_t ROVRF:1;
-                  vuint32_t:10;
-            } B;
-        } RTCS;                 /* RTC Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RTCCNT:32;
-            } B;
-        } RTCCNT;               /* RTC Counter Register */
-
-    };                          /* end of RTC_tag */
-/****************************************************************************/
-/*                     MODULE : SIU                                         */
-/****************************************************************************/
-    struct SIU_tag {
-
-        int32_t SIU_reserved0;  /* {0x004-0x000}/4 = 0x01 */
-
-        union {                 /* MCU ID Register 1 */
-            vuint32_t R;
-            struct {
-                vuint32_t PARTNUM:16;
-                vuint32_t CSP:1;
-                vuint32_t PKG:5;
-                  vuint32_t:2;
-                vuint32_t MAJOR_MASK:4;
-                vuint32_t MINOR_MASK:4;
-            } B;
-        } MIDR;
-
-        union {                 /* MCU ID Register 2 */
-            vuint32_t R;
-            struct {
-                vuint32_t SF:1;
-                vuint32_t FLASH_SIZE_1:4;
-                vuint32_t FLASH_SIZE_2:4;
-                  vuint32_t:7;
-                vuint32_t PARTNUM:8;
-                  vuint32_t:3;
-                vuint32_t EE:1;
-                  vuint32_t:4;
-            } B;
-        } MIDR2;
-
-        int32_t SIU_reserved1[2];       /* {0x014-0x00C}/4 = 0x02 */
-
-        union {                 /* Interrupt Status Flag Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t EIF15:1;
-                vuint32_t EIF14:1;
-                vuint32_t EIF13:1;
-                vuint32_t EIF12:1;
-                vuint32_t EIF11:1;
-                vuint32_t EIF10:1;
-                vuint32_t EIF9:1;
-                vuint32_t EIF8:1;
-                vuint32_t EIF7:1;
-                vuint32_t EIF6:1;
-                vuint32_t EIF5:1;
-                vuint32_t EIF4:1;
-                vuint32_t EIF3:1;
-                vuint32_t EIF2:1;
-                vuint32_t EIF1:1;
-                vuint32_t EIF0:1;
-            } B;
-        } ISR;
-
-        union {                 /* Interrupt Request Enable Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t EIRE15:1;
-                vuint32_t EIRE14:1;
-                vuint32_t EIRE13:1;
-                vuint32_t EIRE12:1;
-                vuint32_t EIRE11:1;
-                vuint32_t EIRE10:1;
-                vuint32_t EIRE9:1;
-                vuint32_t EIRE8:1;
-                vuint32_t EIRE7:1;
-                vuint32_t EIRE6:1;
-                vuint32_t EIRE5:1;
-                vuint32_t EIRE4:1;
-                vuint32_t EIRE3:1;
-                vuint32_t EIRE2:1;
-                vuint32_t EIRE1:1;
-                vuint32_t EIRE0:1;
-            } B;
-        } IRER;
-
-        int32_t SIU_reserved2[3];       /* {0x028-0x01C}/4 = 0x03 */
-
-        union {                 /* Interrupt Rising-Edge Event Enable Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t IREE15:1;
-                vuint32_t IREE14:1;
-                vuint32_t IREE13:1;
-                vuint32_t IREE12:1;
-                vuint32_t IREE11:1;
-                vuint32_t IREE10:1;
-                vuint32_t IREE9:1;
-                vuint32_t IREE8:1;
-                vuint32_t IREE7:1;
-                vuint32_t IREE6:1;
-                vuint32_t IREE5:1;
-                vuint32_t IREE4:1;
-                vuint32_t IREE3:1;
-                vuint32_t IREE2:1;
-                vuint32_t IREE1:1;
-                vuint32_t IREE0:1;
-            } B;
-        } IREER;
-
-        union {                 /* Interrupt Falling-Edge Event Enable Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t IFEE15:1;
-                vuint32_t IFEE14:1;
-                vuint32_t IFEE13:1;
-                vuint32_t IFEE12:1;
-                vuint32_t IFEE11:1;
-                vuint32_t IFEE10:1;
-                vuint32_t IFEE9:1;
-                vuint32_t IFEE8:1;
-                vuint32_t IFEE7:1;
-                vuint32_t IFEE6:1;
-                vuint32_t IFEE5:1;
-                vuint32_t IFEE4:1;
-                vuint32_t IFEE3:1;
-                vuint32_t IFEE2:1;
-                vuint32_t IFEE1:1;
-                vuint32_t IFEE0:1;
-            } B;
-        } IFEER;
-
-        union {                 /* Interrupt Filter Enable Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t IFE15:1;
-                vuint32_t IFE14:1;
-                vuint32_t IFE13:1;
-                vuint32_t IFE12:1;
-                vuint32_t IFE11:1;
-                vuint32_t IFE10:1;
-                vuint32_t IFE9:1;
-                vuint32_t IFE8:1;
-                vuint32_t IFE7:1;
-                vuint32_t IFE6:1;
-                vuint32_t IFE5:1;
-                vuint32_t IFE4:1;
-                vuint32_t IFE3:1;
-                vuint32_t IFE2:1;
-                vuint32_t IFE1:1;
-                vuint32_t IFE0:1;
-            } B;
-        } IFER;
-
-        int32_t SIU_reserved3[3];       /* {0x040-0x034}/4 = 0x03 */
-
-        union {                 /* Pad Configuration Registers */
-            vuint16_t R;
-            struct {
-                vuint16_t:1;
-                vuint16_t SMC:1;
-                vuint16_t APC:1;
-                  vuint16_t:1;
-                vuint16_t PA:2;
-                vuint16_t OBE:1;
-                vuint16_t IBE:1;
-                  vuint16_t:2;
-                vuint16_t ODE:1;
-                  vuint16_t:2;
-                vuint16_t SRC:1;
-                vuint16_t WPE:1;
-                vuint16_t WPS:1;
-            } B;
-        } PCR[123];
-
-        int32_t SIU_reserved4[242];     /* {0x500-0x136}/0xF2 */
-
-        union {                 /* Pad Selection for Multiplexed Input Register */
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t PADSEL:4;
-            } B;
-        } PSMI[32];
-
-        int32_t SIU_reserved5[56];      /* {0x600-0x520}/4 = 0x38 */
-
-        union {                 /* GPIO Pin Data Output Registers */
-            vuint8_t R;
-            struct {
-                vuint8_t:7;
-                vuint8_t PDO:1;
-            } B;
-        } GPDO[124];
-
-        int32_t SIU_reserved6[97];      /* {0x800-0x67C}/4 = 0x61 */
-
-        union {                 /* GPIO Pin Data Input Registers */
-            vuint8_t R;
-            struct {
-                vuint8_t:7;
-                vuint8_t PDI:1;
-            } B;
-        } GPDI[124];
-
-        int32_t SIU_reserved7[225];     /* {0xC00-0x87C}/0x4 = 0xE1 */
-
-        union {                 /* Parallel GPIO Pin Data Output Register */
-            vuint32_t R;
-            struct {
-                vuint32_t PPD0:32;
-            } B;
-        } PGPDO[4];
-
-        int32_t SIU_reserved8[12];      /* {0xC40-0xC10}/0x4 = 0x0C */
-
-        union {                 /* Parallel GPIO Pin Data Input Register */
-            vuint32_t R;
-            struct {
-                vuint32_t PPDI:32;
-            } B;
-        } PGPDI[4];
-
-        int32_t SIU_reserved9[12];      /* {0xC80-0xC50}/0x4 = 0x0C */
-
-        union {                 /* Masked Parallel GPIO Pin Data Out Register */
-            vuint32_t R;
-            struct {
-                vuint32_t MASK:16;
-                vuint32_t MPPDO:16;
-            } B;
-        } MPGPDO[8];
-
-        int32_t SIU_reserved10[216];    /* {0x1000-0x0CA0}/4 = 0xD8 */
-
-        union {                 /* Interrupt Filter Maximum Counter Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t MAXCNT:4;
-            } B;
-        } IFMC[16];
-
-        int32_t SIU_reserved11[16];     /* {0x1080-0x1040}/4 = 0x10 */
-
-        union {                 /* Interrupt Filter Clock Prescaler Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t IFCP:4;
-            } B;
-        } IFCPR;
-
-    };                          /* end of SIU_tag */
-/****************************************************************************/
-/*                          MODULE : SSCM                                   */
-/****************************************************************************/
-    struct SSCM_tag {
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-                vuint16_t NXEN:1;
-                  vuint16_t:3;
-                vuint16_t BMODE:3;
-                  vuint16_t:1;
-                vuint16_t ABD:1;
-                  vuint16_t:3;
-            } B;
-        } STATUS;               /* Status Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t SRAM_SIZE:5;
-                vuint16_t PRSZ:5;
-                vuint16_t PVLB:1;
-                vuint16_t DTSZ:4;
-                vuint16_t DVLD:1;
-            } B;
-        } MEMCONFIG;            /* System Memory Configuration Register */
-
-        int16_t SSCM_reserved;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:14;
-                vuint16_t PAE:1;
-                vuint16_t RAE:1;
-            } B;
-        } ERROR;                /* Error Configuration Register */
-
-        int16_t SSCM_reserved1[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PWD_HI:32;
-            } B;
-        } PWCMPH;               /* Password Comparison Register High Word */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PWD_LO:32;
-            } B;
-        } PWCMPL;               /* Password Comparison Register Low Word */
-
-    };                          /* end of SSCM_tag */
-/****************************************************************************/
-/*                          MODULE : STM                                   */
-/****************************************************************************/
-    struct STM_CHANNEL_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR;                  /* STM Channel Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR;                  /* STM Channel Interrupt Register */
-
-        union {
-            vuint32_t R;
-        } CMP;                  /* STM Channel Compare Register 0 */
-
-        int32_t STM_CHANNEL_reserved;
-
-    };                          /* end of STM_CHANNEL_tag */
-
-    struct STM_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t CPS:8;
-                  vuint32_t:6;
-                vuint32_t FRZ:1;
-                vuint32_t TEN:1;
-            } B;
-        } CR;                   /* STM Control Register */
-
-        union {
-            vuint32_t R;
-        } CNT;                  /* STM Count Register */
-
-        int32_t STM_reserved[2];
-
-        struct STM_CHANNEL_tag CH[4];
-
-    };                          /* end of STM_tag */
-/****************************************************************************/
-/*                          MODULE : SWT                                   */
-/****************************************************************************/
-    struct SWT_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MAP0:1;
-                vuint32_t MAP1:1;
-                vuint32_t MAP2:1;
-                vuint32_t MAP3:1;
-                vuint32_t MAP4:1;
-                vuint32_t MAP5:1;
-                vuint32_t MAP6:1;
-                vuint32_t MAP7:1;
-                  vuint32_t:15;
-                vuint32_t RIA:1;
-                vuint32_t WND:1;
-                vuint32_t ITR:1;
-                vuint32_t HLK:1;
-                vuint32_t SLK:1;
-                vuint32_t CSL:1;
-                vuint32_t STP:1;
-                vuint32_t FRZ:1;
-                vuint32_t WEN:1;
-            } B;
-        } CR;                   /* SWT Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t TIF:1;
-            } B;
-        } IR;                   /* SWT Interrupt Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WTO:32;
-            } B;
-        } TO;                   /* SWT Time-Out Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WST:32;
-            } B;
-        } WN;                   /* SWT Window Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t WSC:16;
-            } B;
-        } SR;                   /* SWT Service Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CNT:32;
-            } B;
-        } CO;                   /* SWT Counter Output Register */
-
-    };                          /* end of SWT_tag */
-/****************************************************************************/
-/*                          MODULE : WKUP                                   */
-/****************************************************************************/
-    struct WKUP_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NIF0:1;
-                vuint32_t NOVF0:1;
-                  vuint32_t:30;
-            } B;
-        } NSR;                  /* NMI Status Register */
-
-        int32_t WKUP_reserved;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NLOCK:1;
-                vuint32_t NDSS:2;
-                vuint32_t NWRE:1;
-                  vuint32_t:1;
-                vuint32_t NREE:1;
-                vuint32_t NFEE:1;
-                vuint32_t NFE:1;
-                  vuint32_t:24;
-            } B;
-        } NCR;                  /* NMI Configuration Register */
-
-        int32_t WKUP_reserved1[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t EIF:20;
-            } B;
-        } WISR;                 /* Wakeup/Interrupt Status Flag Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t EIRE:20;
-            } B;
-        } IRER;                 /* Interrupt Request Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t WRE:20;
-            } B;
-        } WRER;                 /* Wakeup Request Enable Register */
-
-        int32_t WKUP_reserved2[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t IREE:20;
-            } B;
-        } WIREER;               /* Wakeup/Interrupt Rising-Edge Event Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t IFEE:20;
-            } B;
-        } WIFEER;               /* Wakeup/Interrupt Falling-Edge Event Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t IFE:20;
-            } B;
-        } WIFER;                /* Wakeup/Interrupt Filter Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t IPUE:20;
-            } B;
-        } WIPUER;               /* Wakeup/Interrupt Pullup Enable Register */
-
-    };                          /* end of WKUP_tag */
-/****************************************************************** 
-| defines and macros (scope: module-local) 
-|-----------------------------------------------------------------*/ 
-/* Define instances of modules */ 
-#define ADC       (*(volatile struct ADC_tag *)       0xFFE00000UL)
-#define CAN_0     (*(volatile struct FLEXCAN_tag *)   0xFFFC0000UL)
-#define CAN_1     (*(volatile struct FLEXCAN_tag *)   0xFFFC4000UL)
-#define CAN_2     (*(volatile struct FLEXCAN_tag *)   0xFFFC8000UL)
-#define CAN_3     (*(volatile struct FLEXCAN_tag *)   0xFFFCC000UL)
-#define CAN_4     (*(volatile struct FLEXCAN_tag *)   0xFFFD0000UL)
-#define CAN_5     (*(volatile struct FLEXCAN_tag *)   0xFFFD4000UL)
-#define CANSP     (*(volatile struct CANSP_tag *)     0xFFE70000UL)
-#define CFLASH    (*(volatile struct CFLASH_tag *)    0xC3F88000UL)
-#define CGM       (*(volatile struct CGM_tag *)       0xC3FE0000UL)
-#define CTU       (*(volatile struct CTU_tag *)       0xFFE64000UL)
-#define DFLASH    (*(volatile struct DFLASH_tag *)    0xC3F8C000UL)
-#define DSPI_0    (*(volatile struct DSPI_tag *)      0xFFF90000UL)
-#define DSPI_1    (*(volatile struct DSPI_tag *)      0xFFF94000UL)
-#define DSPI_2    (*(volatile struct DSPI_tag *)      0xFFF98000UL)
-#define DSPI_3    (*(volatile struct DSPI_tag *)      0xFFF9C000UL)
-#define ECSM      (*(volatile struct ECSM_tag *)      0xFFF40000UL)   
-#define EMIOS_0   (*(volatile struct EMIOS_tag *)     0xC3FA0000UL)
-#define EMIOS_1   (*(volatile struct EMIOS_tag *)     0xC3FA4000UL)
-#define I2C       (*(volatile struct I2C_tag *)       0xFFE30000UL)
-#define INTC      (*(volatile struct INTC_tag *)      0xFFF48000UL)  
-#define LINFLEX_0 (*(volatile struct LINFLEX_tag *)   0xFFE40000UL)
-#define LINFLEX_1 (*(volatile struct LINFLEX_tag *)   0xFFE44000UL) 
-#define LINFLEX_2 (*(volatile struct LINFLEX_tag *)   0xFFE48000UL) 
-#define LINFLEX_3 (*(volatile struct LINFLEX_tag *)   0xFFE4C000UL) 
-#define ME        (*(volatile struct ME_tag *)        0xC3FDC000UL)
-#define MPU       (*(volatile struct MPU_tag *)       0xFFF10000UL)
-#define PCU       (*(volatile struct PCU_tag *)       0xC3FE8000UL)
-#define PIT       (*(volatile struct PIT_tag *)       0xC3FF0000UL)
-#define RGM       (*(volatile struct RGM_tag *)       0xC3FE4000UL)
-#define RTC       (*(volatile struct RTC_tag *)       0xC3FEC000UL)
-#define SIU       (*(volatile struct SIU_tag *)       0xC3F90000UL)
-#define SSCM      (*(volatile struct SSCM_tag *)      0xC3FD8000UL) 
-#define STM       (*(volatile struct STM_tag *)       0xFFF3C000UL)
-#define SWT       (*(volatile struct SWT_tag *)       0xFFF38000UL)
-#define WKUP      (*(volatile struct WKUP_tag *)      0xC3F94000UL)  
-     
-#ifdef __MWERKS__
-#pragma pop
-#endif  /* 
- */
-     
-#ifdef  __cplusplus
-} 
-#endif  /* 
- */
- 
-#endif  /* ifdef _MPC5604B_H */
- 
-/* End of file */ 
diff --git a/os/hal/platforms/SPC560Dxx/hal_lld.c b/os/hal/platforms/SPC560Dxx/hal_lld.c
deleted file mode 100644
index 229051979..000000000
--- a/os/hal/platforms/SPC560Dxx/hal_lld.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560Dxx/hal_lld.c
- * @brief   SPC560Dxx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PIT channel 3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector59) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  /* Resets the PIT channel 3 IRQ flag.*/
-  PIT.CH[0].TFLG.R = 1;
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-  uint32_t reg;
-
-  /* The system is switched to the RUN0 mode, the default for normal
-     operations.*/
-  if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* INTC initialization, software vector mode, 4 bytes vectors, starting
-     at priority 0.*/
-  INTC.MCR.R        = 0;
-  INTC.CPR.R        = 0;
-  INTC.IACKR.R      = (uint32_t)_vectors;
-
-  /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
-     to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
-     modes.*/
-  INTC.PSR[59].R    = SPC5_PIT0_IRQ_PRIORITY;
-  halSPCSetPeripheralClockMode(92,
-                               SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
-  reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
-  PIT.PITMCR.R      = 1;        /* PIT clock enabled, stop while debugging. */
-  PIT.CH[0].LDVAL.R = reg;
-  PIT.CH[0].CVAL.R  = reg;
-  PIT.CH[0].TFLG.R  = 1;        /* Interrupt flag cleared.                  */
-  PIT.CH[0].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */
-
-  /* EDMA initialization.*/
-  edmaInit();
-}
-
-/**
- * @brief   SPC560B/Cxx clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h and
- *          @p hal_lld.h
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void spc_clock_init(void) {
-
-  /* Waiting for IRC stabilization before attempting anything else.*/
-  while (!ME.GS.B.S_FIRC)
-    ;
-
-#if !SPC5_NO_INIT
-
-#if SPC5_DISABLE_WATCHDOG
-  /* SWT disabled.*/
-  SWT.SR.R = 0xC520;
-  SWT.SR.R = 0xD928;
-  SWT.CR.R = 0xFF00000A;
-#endif
-
-  /* SSCM initialization. Setting up the most restrictive handling of
-     invalid accesses to peripherals.*/
-  SSCM.ERROR.R = 3;                             /* PAE and RAE bits.        */
-
-  /* RGM errors clearing.*/
-  RGM.FES.R         = 0xFFFF;
-  RGM.DES.R         = 0xFFFF;
-
-  /* Oscillators dividers setup.*/
-  CGM.FIRC_CTL.B.RCDIV   = SPC5_IRCDIV_VALUE - 1;
-  CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
-
-  /* The system must be in DRUN mode on entry, if this is not the case then
-     it is considered a serious anomaly.*/
-  if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-#if defined(SPC5_OSC_BYPASS)
-  /* If the board is equipped with an oscillator instead of a xtal then the
-     bypass must be activated.*/
-  CGM.OSC_CTL.B.OSCBYP = TRUE;
-#endif /* SPC5_OSC_BYPASS */
-
-  /* Setting the various dividers and source selectors.*/
-  CGM.SC_DC0.R     = SPC5_CGM_SC_DC0;
-  CGM.SC_DC1.R     = SPC5_CGM_SC_DC1;
-  CGM.SC_DC2.R     = SPC5_CGM_SC_DC2;
-
-  /* Initialization of the FMPLLs settings.*/
-  CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
-                   ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
-                   (SPC5_FMPLL0_NDIV_VALUE << 16);
-  CGM.FMPLL_MR.R = 0;                           /* TODO: Add a setting.     */
-
-  /* Run modes initialization.*/
-  ME.IS.R           = 8;                        /* Resetting I_ICONF status.*/
-  ME.MER.R          = SPC5_ME_ME_BITS;          /* Enabled run modes.       */
-  ME.TEST.R         = SPC5_ME_TEST_MC_BITS;     /* TEST run mode.           */
-  ME.SAFE.R         = SPC5_ME_SAFE_MC_BITS;     /* SAFE run mode.           */
-  ME.DRUN.R         = SPC5_ME_DRUN_MC_BITS;     /* DRUN run mode.           */
-  ME.RUN[0].R       = SPC5_ME_RUN0_MC_BITS;     /* RUN0 run mode.           */
-  ME.RUN[1].R       = SPC5_ME_RUN1_MC_BITS;     /* RUN1 run mode.           */
-  ME.RUN[2].R       = SPC5_ME_RUN2_MC_BITS;     /* RUN2 run mode.           */
-  ME.RUN[3].R       = SPC5_ME_RUN3_MC_BITS;     /* RUN0 run mode.           */
-  ME.HALT.R        = SPC5_ME_HALT0_MC_BITS;    /* HALT0 run mode.          */
-  ME.STOP.R        = SPC5_ME_STOP0_MC_BITS;    /* STOP0 run mode.          */
-  ME.STANDBY.R     = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode.       */
-  if (ME.IS.B.I_ICONF) {
-    /* Configuration rejected.*/
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* Peripherals run and low power modes initialization.*/
-  ME.RUNPC[0].R     = SPC5_ME_RUN_PC0_BITS;
-  ME.RUNPC[1].R     = SPC5_ME_RUN_PC1_BITS;
-  ME.RUNPC[2].R     = SPC5_ME_RUN_PC2_BITS;
-  ME.RUNPC[3].R     = SPC5_ME_RUN_PC3_BITS;
-  ME.RUNPC[4].R     = SPC5_ME_RUN_PC4_BITS;
-  ME.RUNPC[5].R     = SPC5_ME_RUN_PC5_BITS;
-  ME.RUNPC[6].R     = SPC5_ME_RUN_PC6_BITS;
-  ME.RUNPC[7].R     = SPC5_ME_RUN_PC7_BITS;
-  ME.LPPC[0].R      = SPC5_ME_LP_PC0_BITS;
-  ME.LPPC[1].R      = SPC5_ME_LP_PC1_BITS;
-  ME.LPPC[2].R      = SPC5_ME_LP_PC2_BITS;
-  ME.LPPC[3].R      = SPC5_ME_LP_PC3_BITS;
-  ME.LPPC[4].R      = SPC5_ME_LP_PC4_BITS;
-  ME.LPPC[5].R      = SPC5_ME_LP_PC5_BITS;
-  ME.LPPC[6].R      = SPC5_ME_LP_PC6_BITS;
-  ME.LPPC[7].R      = SPC5_ME_LP_PC7_BITS;
-
-  /* CFLASH settings calculated for a maximum clock of 64MHz.*/
-  CFLASH.PFCR0.B.BK0_APC  = 2;
-  CFLASH.PFCR0.B.BK0_RWSC = 2;
-  CFLASH.PFCR1.B.BK1_APC  = 2;
-  CFLASH.PFCR1.B.BK1_RWSC = 2;
-
-  /* Switches again to DRUN mode (current mode) in order to update the
-     settings.*/
-  if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-#endif /* !SPC5_NO_INIT */
-}
-
-/**
- * @brief   Switches the system to the specified run mode.
- *
- * @param[in] mode      one of the possible run modes
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   if the switch operation has been completed.
- * @retval CH_FAILED    if the switch operation failed.
- */
-bool_t halSPCSetRunMode(spc5_runmode_t mode) {
-
-  /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
-  ME.IS.R = 5;
-
-  /* Starts a transition process.*/
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
-
-  /* Waits for the mode switch or an error condition.*/
-  while (TRUE) {
-    uint32_t r = ME.IS.R;
-    if (r & 1)
-      return CH_SUCCESS;
-    if (r & 4)
-      return CH_FAILED;
-  }
-}
-
-/**
- * @brief   Changes the clock mode of a peripheral.
- *
- * @param[in] n         index of the @p PCTL register
- * @param[in] pctl      new value for the @p PCTL register
- *
- * @notapi
- */
-void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
-  uint32_t mode;
-
-  ME.PCTL[n].R = pctl;
-  mode = ME.MCTL.B.TARGET_MODE;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
-}
-
-#if !SPC5_NO_INIT || defined(__DOXYGEN__)
-/**
- * @brief   Returns the system clock under the current run mode.
- *
- * @return              The system clock in Hertz.
- */
-uint32_t halSPCGetSystemClock(void) {
-  uint32_t sysclk;
-
-  sysclk = ME.GS.B.S_SYSCLK;
-  switch (sysclk) {
-  case SPC5_ME_GS_SYSCLK_IRC:
-    return SPC5_IRC_CLK;
-  case SPC5_ME_GS_SYSCLK_DIVIRC:
-    return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
-  case SPC5_ME_GS_SYSCLK_XOSC:
-    return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
-  case SPC5_ME_GS_SYSCLK_DIVXOSC:
-    return SPC5_XOSC_CLK;
-  case SPC5_ME_GS_SYSCLK_FMPLL0:
-    return SPC5_FMPLL0_CLK;
-  default:
-    return 0;
-  }
-}
-#endif /* !SPC5_NO_INIT */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560Dxx/hal_lld.h b/os/hal/platforms/SPC560Dxx/hal_lld.h
deleted file mode 100644
index 5bc08014c..000000000
--- a/os/hal/platforms/SPC560Dxx/hal_lld.h
+++ /dev/null
@@ -1,769 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560Dxx/hal_lld.h
- * @brief   SPC560Dxx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - SPC5_XOSC_CLK.
- *          - SPC5_OSC_BYPASS (optionally).
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "xpc560d.h"
-#include "spc560d_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @name    Platform identification
- * @{
- */
-#define PLATFORM_NAME               "SPC560Dxx Car Body and Convenience"
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum XOSC clock frequency.
- */
-#define SPC5_XOSC_CLK_MAX           16000000
-
-/**
- * @brief   Minimum XOSC clock frequency.
- */
-#define SPC5_XOSC_CLK_MIN           4000000
-
-/**
- * @brief   Maximum FMPLLs input clock frequency.
- */
-#define SPC5_FMPLLIN_MIN            4000000
-
-/**
- * @brief   Maximum FMPLLs input clock frequency.
- */
-#define SPC5_FMPLLIN_MAX            48000000
-
-/**
- * @brief   Maximum FMPLLs VCO clock frequency.
- */
-#define SPC5_FMPLLVCO_MAX           512000000
-
-/**
- * @brief   Maximum FMPLLs VCO clock frequency.
- */
-#define SPC5_FMPLLVCO_MIN           256000000
-
-/**
- * @brief   Maximum FMPLL0 output clock frequency.
- */
-#define SPC5_FMPLL0_CLK_MAX         48000000
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define SPC5_IRC_CLK                16000000    /**< Internal fast RC
-                                                     oscillator.            */
-#define SPC5_SIRC_CLK               128000      /**< Internal RC slow
-                                                     oscillator.            */
-/** @} */
-
-/**
- * @name    FMPLL_CR register bits definitions
- * @{
- */
-#define SPC5_FMPLL_ODF_DIV2         (0U << 24)
-#define SPC5_FMPLL_ODF_DIV4         (1U << 24)
-#define SPC5_FMPLL_ODF_DIV8         (2U << 24)
-#define SPC5_FMPLL_ODF_DIV16        (3U << 24)
-/** @} */
-
-/**
- * @name    ME_GS register bits definitions
- * @{
- */
-#define SPC5_ME_GS_SYSCLK_MASK      (15U << 0)
-#define SPC5_ME_GS_SYSCLK_IRC       (0U << 0)
-#define SPC5_ME_GS_SYSCLK_DIVIRC    (1U << 0)
-#define SPC5_ME_GS_SYSCLK_XOSC      (2U << 0)
-#define SPC5_ME_GS_SYSCLK_DIVXOSC   (3U << 0)
-#define SPC5_ME_GS_SYSCLK_FMPLL0    (4U << 0)
-/** @} */
-
-/**
- * @name    ME_ME register bits definitions
- * @{
- */
-#define SPC5_ME_ME_RESET            (1U << 0)
-#define SPC5_ME_ME_TEST             (1U << 1)
-#define SPC5_ME_ME_SAFE             (1U << 2)
-#define SPC5_ME_ME_DRUN             (1U << 3)
-#define SPC5_ME_ME_RUN0             (1U << 4)
-#define SPC5_ME_ME_RUN1             (1U << 5)
-#define SPC5_ME_ME_RUN2             (1U << 6)
-#define SPC5_ME_ME_RUN3             (1U << 7)
-#define SPC5_ME_ME_HALT0            (1U << 8)
-#define SPC5_ME_ME_STOP0            (1U << 10)
-#define SPC5_ME_ME_STANDBY0         (1U << 13)
-/** @} */
-
-/**
- * @name    ME_xxx_MC registers bits definitions
- * @{
- */
-#define SPC5_ME_MC_SYSCLK_MASK      (15U << 0)
-#define SPC5_ME_MC_SYSCLK(n)        ((n) << 0)
-#define SPC5_ME_MC_SYSCLK_IRC       SPC5_ME_MC_SYSCLK(0)
-#define SPC5_ME_MC_SYSCLK_DIVIRC    SPC5_ME_MC_SYSCLK(1)
-#define SPC5_ME_MC_SYSCLK_XOSC      SPC5_ME_MC_SYSCLK(2)
-#define SPC5_ME_MC_SYSCLK_DIVXOSC   SPC5_ME_MC_SYSCLK(3)
-#define SPC5_ME_MC_SYSCLK_FMPLL0    SPC5_ME_MC_SYSCLK(4)
-#define SPC5_ME_MC_SYSCLK_DISABLED  SPC5_ME_MC_SYSCLK(15)
-#define SPC5_ME_MC_IRCON            (1U << 4)
-#define SPC5_ME_MC_XOSC0ON          (1U << 5)
-#define SPC5_ME_MC_PLL0ON           (1U << 6)
-#define SPC5_ME_MC_CFLAON_MASK      (3U << 16)
-#define SPC5_ME_MC_CFLAON(n)        ((n) << 16)
-#define SPC5_ME_MC_CFLAON_PD        (1U << 16)
-#define SPC5_ME_MC_CFLAON_LP        (2U << 16)
-#define SPC5_ME_MC_CFLAON_NORMAL    (3U << 16)
-#define SPC5_ME_MC_DFLAON_MASK      (3U << 18)
-#define SPC5_ME_MC_DFLAON(n)        ((n) << 18)
-#define SPC5_ME_MC_DFLAON_PD        (1U << 18)
-#define SPC5_ME_MC_DFLAON_LP        (2U << 18)
-#define SPC5_ME_MC_DFLAON_NORMAL    (3U << 18)
-#define SPC5_ME_MC_MVRON            (1U << 20)
-#define SPC5_ME_MC_PDO              (1U << 23)
-/** @} */
-
-/**
- * @name    ME_MCTL register bits definitions
- * @{
- */
-#define SPC5_ME_MCTL_KEY            0x5AF0U
-#define SPC5_ME_MCTL_KEY_INV        0xA50FU
-#define SPC5_ME_MCTL_MODE_MASK      (15U << 28)
-#define SPC5_ME_MCTL_MODE(n)        ((n) << 28)
-/** @} */
-
-/**
- * @name    ME_RUN_PCx registers bits definitions
- * @{
- */
-#define SPC5_ME_RUN_PC_TEST         (1U << 1)
-#define SPC5_ME_RUN_PC_SAFE         (1U << 2)
-#define SPC5_ME_RUN_PC_DRUN         (1U << 3)
-#define SPC5_ME_RUN_PC_RUN0         (1U << 4)
-#define SPC5_ME_RUN_PC_RUN1         (1U << 5)
-#define SPC5_ME_RUN_PC_RUN2         (1U << 6)
-#define SPC5_ME_RUN_PC_RUN3         (1U << 7)
-/** @} */
-
-/**
- * @name    ME_LP_PCx registers bits definitions
- * @{
- */
-#define SPC5_ME_LP_PC_HALT0         (1U << 8)
-#define SPC5_ME_LP_PC_STOP0         (1U << 10)
-#define SPC5_ME_LP_PC_STANDBY0      (1U << 10)
-/** @} */
-
-/**
- * @name    ME_PCTL registers bits definitions
- * @{
- */
-#define SPC5_ME_PCTL_RUN_MASK       (7U << 0)
-#define SPC5_ME_PCTL_RUN(n)         ((n) << 0)
-#define SPC5_ME_PCTL_LP_MASK        (7U << 3)
-#define SPC5_ME_PCTL_LP(n)          ((n) << 3)
-#define SPC5_ME_PCTL_DBG            (1U << 6)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Disables the clocks initialization in the HAL.
- */
-#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
-#define SPC5_NO_INIT                        FALSE
-#endif
-
-/**
- * @brief   Disables the overclock checks.
- */
-#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
-#define SPC5_ALLOW_OVERCLOCK                FALSE
-#endif
-
-/**
- * @brief   Disables the watchdog on start.
- */
-#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
-#define SPC5_DISABLE_WATCHDOG               TRUE
-#endif
-
-/**
- * @brief   FMPLL0 IDF divider value.
- * @note    The default value is calculated for XOSC=8MHz and PHI=48MHz.
- */
-#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_IDF_VALUE               1
-#endif
-
-/**
- * @brief   FMPLL0 NDIV divider value.
- * @note    The default value is calculated for XOSC=8MHz and PHI=48MHz.
- */
-#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_NDIV_VALUE              48
-#endif
-
-/**
- * @brief   FMPLL0 ODF divider value.
- * @note    The default value is calculated for XOSC=8MHz and PHI=48MHz.
- */
-#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_ODF                     SPC5_FMPLL_ODF_DIV8
-#endif
-
-/**
- * @brief   XOSC divider value.
- * @note    The allowed range is 1...32.
- */
-#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_XOSCDIV_VALUE                  1
-#endif
-
-/**
- * @brief   Fast IRC divider value.
- * @note    The allowed range is 1...32.
- */
-#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_IRCDIV_VALUE                   1
-#endif
-
-/**
- * @brief   Peripherals Set 1 clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PERIPHERAL1_CLK_DIV_VALUE      2
-#endif
-
-/**
- * @brief   Peripherals Set 2 clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PERIPHERAL2_CLK_DIV_VALUE      2
-#endif
-
-/**
- * @brief   Peripherals Set 3 clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PERIPHERAL3_CLK_DIV_VALUE      2
-#endif
-
-/**
- * @brief   Active run modes in ME_ME register.
- * @note    Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
- *          is no need to specify them.
- */
-#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_ME_BITS                     (SPC5_ME_ME_RUN1 |              \
-                                             SPC5_ME_ME_RUN2 |              \
-                                             SPC5_ME_ME_RUN3 |              \
-                                             SPC5_ME_ME_HALT0 |             \
-                                             SPC5_ME_ME_STOP0 |             \
-                                             SPC5_ME_ME_STANDBY0)
-#endif
-
-/**
- * @brief   TEST mode settings.
- */
-#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_TEST_MC_BITS                (SPC5_ME_MC_SYSCLK_IRC |        \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   SAFE mode settings.
- */
-#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_SAFE_MC_BITS                (SPC5_ME_MC_PDO)
-#endif
-
-/**
- * @brief   DRUN mode settings.
- */
-#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_DRUN_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN0 mode settings.
- */
-#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN0_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN1 mode settings.
- */
-#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN1_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN2 mode settings.
- */
-#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN2_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN3 mode settings.
- */
-#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN3_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   HALT0 mode settings.
- */
-#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_HALT0_MC_BITS               (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   STOP0 mode settings.
- */
-#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_STOP0_MC_BITS               (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   STANDBY0 mode settings.
- */
-#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_STANDBY0_MC_BITS            (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   Peripheral mode 0 (run mode).
- * @note    Do not change this setting, it is expected to be the "never run"
- *          mode.
- */
-#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC0_BITS                0
-#endif
-
-/**
- * @brief   Peripheral mode 1 (run mode).
- * @note    Do not change this setting, it is expected to be the "always run"
- *          mode.
- */
-#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC1_BITS                (SPC5_ME_RUN_PC_TEST |          \
-                                             SPC5_ME_RUN_PC_SAFE |          \
-                                             SPC5_ME_RUN_PC_DRUN |          \
-                                             SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 2 (run mode).
- * @note    Do not change this setting, it is expected to be the "only during
- *          normal run" mode.
- */
-#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC2_BITS                (SPC5_ME_RUN_PC_DRUN |          \
-                                             SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 3 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC3_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 4 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC4_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 5 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC5_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 6 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC6_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 7 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC7_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 0 (low power mode).
- * @note    Do not change this setting, it is expected to be the "never run"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC0_BITS                 0
-#endif
-
-/**
- * @brief   Peripheral mode 1 (low power mode).
- * @note    Do not change this setting, it is expected to be the "always run"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC1_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0 |          \
-                                             SPC5_ME_LP_PC_STANDBY0)
-#endif
-
-/**
- * @brief   Peripheral mode 2 (low power mode).
- * @note    Do not change this setting, it is expected to be the "halt only"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC2_BITS                 (SPC5_ME_LP_PC_HALT0)
-#endif
-
-/**
- * @brief   Peripheral mode 3 (low power mode).
- * @note    Do not change this setting, it is expected to be the "stop only"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC3_BITS                 (SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 4 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC4_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 5 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC5_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 6 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC6_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 7 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC7_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   PIT channel 0 IRQ priority.
- * @note    This PIT channel is allocated permanently for system tick
- *          generation.
- */
-#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PIT0_IRQ_PRIORITY              4
-#endif
-
-/**
- * @brief   Clock initialization failure hook.
- * @note    The default is to stop the system and let the RTC restart it.
- * @note    The hook code must not return.
- */
-#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
-#define SPC5_CLOCK_FAILURE_HOOK()           chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(SPC560Dxx_MCUCONF)
-#error "Using a wrong mcuconf.h file, SPC560Dxx_MCUCONF not defined"
-#endif
-
-/* Check on the XOSC frequency.*/
-#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) ||                                  \
-    (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
-#error "invalid SPC5_XOSC_CLK value specified"
-#endif
-
-/* Check on the XOSC divider.*/
-#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
-#error "invalid SPC5_XOSCDIV_VALUE value specified"
-#endif
-
-/* Check on the IRC divider.*/
-#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
-#error "invalid SPC5_IRCDIV_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_IDF_VALUE.*/
-#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
-#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
-#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
-#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_ODF.*/
-#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
-#define SPC5_FMPLL0_ODF_VALUE    2
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
-#define SPC5_FMPLL0_ODF_VALUE    4
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
-#define SPC5_FMPLL0_ODF_VALUE    8
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
-#define SPC5_FMPLL0_ODF_VALUE    16
-#else
-#error "invalid SPC5_FMPLL0_ODF value specified"
-#endif
-
-/**
- * @brief   SPC5_FMPLL0_VCO_CLK clock point.
- */
-#define SPC5_FMPLL0_VCO_CLK                                                 \
-  ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
-
-/* Check on FMPLL0 VCO output.*/
-#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \
-    (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
-#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
-#endif
-
-/**
- * @brief   SPC5_FMPLL0_CLK clock point.
- */
-#define SPC5_FMPLL0_CLK                                                     \
-  (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
-
-/* Check on SPC5_FMPLL0_CLK.*/
-#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
-#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
-#endif
-
-/* Check on the peripherals set 1 clock divider settings.*/
-#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
-#define SPC5_CGM_SC_DC0         0
-#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) &&                              \
-      (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC0         (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
-#else
-#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
-#endif
-
-/* Check on the peripherals set 2 clock divider settings.*/
-#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
-#define SPC5_CGM_SC_DC1         0
-#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) &&                              \
-      (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC1         (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
-#else
-#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
-#endif
-
-/* Check on the peripherals set 3 clock divider settings.*/
-#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
-#define SPC5_CGM_SC_DC2         0
-#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) &&                              \
-      (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC2         (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
-#else
-#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-typedef enum {
-  SPC5_RUNMODE_TEST  = 1,
-  SPC5_RUNMODE_SAFE  = 2,
-  SPC5_RUNMODE_DRUN  = 3,
-  SPC5_RUNMODE_RUN0  = 4,
-  SPC5_RUNMODE_RUN1  = 5,
-  SPC5_RUNMODE_RUN2  = 6,
-  SPC5_RUNMODE_RUN3  = 7,
-  SPC5_RUNMODE_HALT0 = 8,
-  SPC5_RUNMODE_STOP0 = 10
-} spc5_runmode_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#include "spc5_edma.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void spc_clock_init(void);
-  bool_t halSPCSetRunMode(spc5_runmode_t mode);
-  void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
-#if !SPC5_NO_INIT
-  uint32_t halSPCGetSystemClock(void);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560Dxx/platform.mk b/os/hal/platforms/SPC560Dxx/platform.mk
deleted file mode 100644
index 8e6c8d73a..000000000
--- a/os/hal/platforms/SPC560Dxx/platform.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of all the SPC560Dxx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1
diff --git a/os/hal/platforms/SPC560Dxx/spc560d_registry.h b/os/hal/platforms/SPC560Dxx/spc560d_registry.h
deleted file mode 100644
index a3372e513..000000000
--- a/os/hal/platforms/SPC560Dxx/spc560d_registry.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560Dxx/spc560d_registry.h
- * @brief   SPC560Dxx capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _SPC560D_REGISTRY_H_
-#define _SPC560D_REGISTRY_H_
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    SPC560Dxx capabilities
- * @{
- */
-/* DSPI attribures.*/
-#define SPC5_HAS_DSPI0                      TRUE
-#define SPC5_HAS_DSPI1                      TRUE
-#define SPC5_HAS_DSPI2                      FALSE
-#define SPC5_HAS_DSPI3                      FALSE
-#define SPC5_HAS_DSPI4                      FALSE
-#define SPC5_DSPI_FIFO_DEPTH                4
-#define SPC5_DSPI0_PCTL                     4
-#define SPC5_DSPI1_PCTL                     5
-#define SPC5_DSPI0_TX1_DMA_DEV_ID           1
-#define SPC5_DSPI0_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI0_RX_DMA_DEV_ID            2
-#define SPC5_DSPI1_TX1_DMA_DEV_ID           3
-#define SPC5_DSPI1_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI1_RX_DMA_DEV_ID            4
-#define SPC5_DSPI0_TFFF_HANDLER             vector76
-#define SPC5_DSPI0_TFFF_NUMBER              76
-#define SPC5_DSPI1_TFFF_HANDLER             vector96
-#define SPC5_DSPI1_TFFF_NUMBER              96
-#define SPC5_DSPI0_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
-#define SPC5_DSPI0_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
-#define SPC5_DSPI1_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
-#define SPC5_DSPI1_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
-
-/* eDMA attributes.*/
-#define SPC5_HAS_EDMA                       TRUE
-#define SPC5_EDMA_NCHANNELS                 16
-#define SPC5_EDMA_HAS_MUX                   TRUE
-#define SPC5_EDMA_MUX_PCTL                  23
-
-/* LINFlex attributes.*/
-#define SPC5_HAS_LINFLEX0                   TRUE
-#define SPC5_LINFLEX0_PCTL                  48
-#define SPC5_LINFLEX0_RXI_HANDLER           vector79
-#define SPC5_LINFLEX0_TXI_HANDLER           vector80
-#define SPC5_LINFLEX0_ERR_HANDLER           vector81
-#define SPC5_LINFLEX0_RXI_NUMBER            79
-#define SPC5_LINFLEX0_TXI_NUMBER            80
-#define SPC5_LINFLEX0_ERR_NUMBER            81
-#define SPC5_LINFLEX0_CLK                   (halSPCGetSystemClock() /       \
-                                             SPC5_PERIPHERAL1_CLK_DIV_VALUE)
-
-#define SPC5_HAS_LINFLEX1                   TRUE
-#define SPC5_LINFLEX1_PCTL                  49
-#define SPC5_LINFLEX1_RXI_HANDLER           vector99
-#define SPC5_LINFLEX1_TXI_HANDLER           vector100
-#define SPC5_LINFLEX1_ERR_HANDLER           vector101
-#define SPC5_LINFLEX1_RXI_NUMBER            99
-#define SPC5_LINFLEX1_TXI_NUMBER            100
-#define SPC5_LINFLEX1_ERR_NUMBER            101
-#define SPC5_LINFLEX1_CLK                   (halSPCGetSystemClock() /       \
-                                             SPC5_PERIPHERAL1_CLK_DIV_VALUE)
-
-#define SPC5_HAS_LINFLEX2                   TRUE
-#define SPC5_LINFLEX2_PCTL                  50
-#define SPC5_LINFLEX2_RXI_HANDLER           vector119
-#define SPC5_LINFLEX2_TXI_HANDLER           vector120
-#define SPC5_LINFLEX2_ERR_HANDLER           vector121
-#define SPC5_LINFLEX2_RXI_NUMBER            119
-#define SPC5_LINFLEX2_TXI_NUMBER            120
-#define SPC5_LINFLEX2_ERR_NUMBER            121
-#define SPC5_LINFLEX2_CLK                   (halSPCGetSystemClock() /       \
-                                             SPC5_PERIPHERAL1_CLK_DIV_VALUE)
-
-#define SPC5_HAS_LINFLEX3                   FALSE
-
-/* SIUL attributes.*/
-#define SPC5_HAS_SIUL                       TRUE
-#define SPC5_SIUL_PCTL                      68
-#define SPC5_SIUL_NUM_PORTS                 8
-#define SPC5_SIUL_NUM_PCRS                  77
-#define SPC5_SIUL_NUM_PADSELS               63
-#define SPC5_SIUL_SYSTEM_PINS               32,33
-
-/* FlexCAN attributes.*/
-#define SPC5_HAS_FLEXCAN0                                   TRUE
-#define SPC5_FLEXCAN0_PCTL                                  16
-#define SPC5_FLEXCAN0_MB                                    32
-#define SPC5_FLEXCAN0_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER           vector65
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER              vector66
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER             vector68
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER             vector69
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER             vector70
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER             vector71
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER             vector72
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER            65
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER               66
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER              68
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER              69
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER              70
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER              71
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER              72
-#define SPC5_FLEXCAN0_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
-#define SPC5_FLEXCAN0_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
-/** @} */
-
-#endif /* _SPC560D_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560Dxx/typedefs.h b/os/hal/platforms/SPC560Dxx/typedefs.h
deleted file mode 100644
index 290173872..000000000
--- a/os/hal/platforms/SPC560Dxx/typedefs.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560Dxx/typedefs.h
- * @brief   Dummy typedefs file.
- */
-
-#ifndef _TYPEDEFS_H_
-#define _TYPEDEFS_H_
-
-#include "chtypes.h"
-
-#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/platforms/SPC560Dxx/xpc560d.h b/os/hal/platforms/SPC560Dxx/xpc560d.h
deleted file mode 100644
index e511c24c8..000000000
--- a/os/hal/platforms/SPC560Dxx/xpc560d.h
+++ /dev/null
@@ -1,5557 +0,0 @@
-/**************************************************************************** 
- * PROJECT     : MPC5602Dx
- *               
- * FILE        : MPC5602Dx_2.03.h
- * 
- * DESCRIPTION : This is the header file describing the register
- *               set for MPC560xBx family of MCUs. It supports the following devices:
- *
- *				- MPC5602D
- * 
- *
- * COPYRIGHT   :(c) 2012, Freescale
- * 
- * VERSION     : 2.03
- * DATE        : 06.05.2012 
- * AUTHOR      : r23668
- * HISTORY     : New header Based Upon MPC5607B and MPC5606BK. Version 1.04
- * 				0.12 Oct 2011: MPC5606BK
- * 				1.0 Alpha Nov 2011  : MPC560xBx combined header file. Out for Review and comments.
- *				1.01 Jan 2012: Checked with both MPC5607x and MPC5606Bx, no comments recieved. 
-  *				1.04 Mar 2012: Supersedes MPC5607B ver 1.03 and becomes Ver 1.04.
- *			        2.01 Added missing ADC registers CIMR1, CIMR2, PSR1, NCMR1, NCMR2
-  *			        2.02 Added more missing ADC registers CEOCFR2, DMAR1/2, PSR1, DSDR, CDR, CWSEL8-11, CWENR2, AWORR2, NCMR2, JCMR2
-  *                 2.03 Corrected RM discrepancies.
- ***************************************************************** 
- * Copyright:
- *	Freescale Semiconductor, INC. All Rights Reserved.
- *  You are hereby granted a copyright license to use, modify, and
- *  distribute the SOFTWARE so long as this entire notice is
- *  retained without alteration in any modified and/or redistributed
- *  versions, and that such modified versions are clearly identified
- *  as such. No licenses are granted by implication, estoppel or
- *  otherwise under any patents or trademarks of Freescale
- *  Semiconductor, Inc. This software is provided on an "AS IS"
- *  basis and without warranty.
- *
- *  To the maximum extent permitted by applicable law, Freescale
- *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
- *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
- *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
- *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
- *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
- *
- *  To the maximum extent permitted by applicable law, IN NO EVENT
- *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
- *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
- *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
- *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
- *
- *  Freescale Semiconductor assumes no responsibility for the
- *  maintenance and support of this software
- *
- ******************************************************************/
- 
-/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
-
-/***************************************************************** 
-* Example instantiation and use:            
-*                                           
-*  <MODULE>.<REGISTER>.B.<BIT> = 1;         
-*  <MODULE>.<REGISTER>.R       = 0x10000000;
-*                                           
-******************************************************************/
-
-#ifndef _JDP_H_
-#define _JDP_H_
-
-#include "typedefs.h"
-
-#ifdef  __cplusplus
-extern "C" {
-#endif
-
-#ifdef __MWERKS__
-#pragma push
-#pragma ANSI_strict off
-#endif
-
-/****************************************************************************/
-/*                     MODULE : CFLASH (base address - 0xC3F8_8000)         */
-/****************************************************************************/
-    struct CFLASH_tag {
-        union {     /* Module Configuration (Base+0x0000) */
-            vuint32_t R;
-            struct {
-                vuint32_t EDC:1;
-                vuint32_t:4;
-                vuint32_t SIZE:3;
-                vuint32_t:1;
-                vuint32_t LAS:3;
-                vuint32_t:3;
-                vuint32_t MAS:1;
-                vuint32_t EER:1;
-                vuint32_t RWE:1;
-                vuint32_t:2;
-                vuint32_t PEAS:1;
-                vuint32_t DONE:1;
-                vuint32_t PEG:1;
-                vuint32_t:4;
-                vuint32_t PGM:1;
-                vuint32_t PSUS:1;
-                vuint32_t ERS:1;
-                vuint32_t ESUS:1;
-                vuint32_t EHV:1;
-            } B;
-        } MCR;
-
-        union {    /* Low/Mid address block locking (Base+0x0004) */
-            vuint32_t R;
-            struct {
-                vuint32_t LME:1;
-                vuint32_t:10;
-                vuint32_t TSLK:1;
-                vuint32_t:2;
-                vuint32_t MLK:2;
-                vuint32_t:10;
-                vuint32_t LLK:6;
-            } B;
-        } LML;
-
-        union {  /* High address space block locking (Base+0x0008)*/
-            vuint32_t R;
-            struct {
-                vuint32_t HBE:1;
-                vuint32_t :27;
-                vuint32_t HLK:4;
-            } B;
-        } HBL;
-
-        union {    /* Secondary Low/Mid block lock (Base+0x000C)*/
-            vuint32_t R;
-            struct {
-                vuint32_t SLE:1;
-                vuint32_t:10;
-                vuint32_t STSLK:1;
-                vuint32_t:2;
-                vuint32_t SMK:2;
-                vuint32_t:10;
-                vuint32_t SLK:6;
-            } B;
-        } SLL;
-
-        union {    /* Low/Mid address space block sel (Base+0x0010)*/
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t MSL:2;
-                vuint32_t:10;
-                vuint32_t LSL:6;
-            } B;
-        } LMS;
-
-        union {   /* High address Space block select (Base+0x0014)*/
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t HSL:4;
-            } B;
-        } HBS;
-
-        union {   /* Address Register (Base+0x0018) */
-            vuint32_t R;
-            struct {
-                vuint32_t:9;
-                vuint32_t ADD:20;
-                vuint32_t:3;
-            } B;
-        } ADR;
-
-    /* Note the following 3 registers, BIU[0..2] are mirrored to */
-    /*  the code flash configuraiton PFCR[0..2] registers        */
-    /* To make it easier to code, the BIU registers have been    */
-    /*  replaced with the PFCR registers in this header file!    */
-    /* A commented out BIU register is shown for reference!      */
-
-
-    union { /* CFLASH Configuration 0 (Base+0x001C) */
-            vuint32_t R;
-            struct {
-                vuint32_t BK0_APC:5;
-                vuint32_t BK0_WWSC:5;
-                vuint32_t BK0_RWSC:5;
-                vuint32_t BK0_RWWC2:1;
-                vuint32_t BK0_RWWC1:1;
-				vuint32_t :7;
-                vuint32_t BK0_RWWC0:1;
-                vuint32_t B0_P0_BCFG:2;
-                vuint32_t B0_P0_DPFE:1;
-                vuint32_t B0_P0_IPFE:1;
-                vuint32_t B0_P0_PFLM:2;
-                vuint32_t B0_P0_BFE:1;
-            } B;
-        } PFCR0;
-		
-	/* Commented out Bus Interface Unit 0 (Base+0x001C) */
-    /*union {              
-
-        vuint32_t R;
-
-        struct {
-
-            vuint32_t BI0:32;
-
-        } B;
-
-    } BIU0;  */
-        union {   /* CFLASH Configuration Register 1 (Base+0x0020)*/
-            vuint32_t R;
-            struct {
-                vuint32_t BK1_APC:5;
-                vuint32_t BK1_WWSC:5;
-                vuint32_t BK1_RWSC:5;
-                vuint32_t BK1_RWWC2:1;
-                vuint32_t BK1_RWWC1:1;
-                vuint32_t:7;			            
-                vuint32_t BK1_RWWC0:1;
-                vuint32_t:6;
-                vuint32_t B1_P0_BFE:1;
-            } B;
-        } PFCR1;
-	/* Commented out Bus Interface Unit 1 (Base+0x0020) */
-    /*union {                 
-
-        vuint32_t R;
-
-        struct {
-
-            vuint32_t BI1:32;
-
-        } B;
-
-    } BIU1; */
-		
-
-        union {          /* CFLASH Access Protection (Base+0x0024) */
-            vuint32_t R;
-            struct {
-              	vuint32_t:13;
-                vuint32_t M2PFD:1;
-                vuint32_t:1;
-                vuint32_t M0PFD:1;
-                vuint32_t:10;
-                vuint32_t M2AP:2;
-                vuint32_t:2;
-                vuint32_t M0AP:2;
-            } B;
-        } PFAPR;
-		    /* Commented out Bus Interface Unit 2 (Base+0x0024) */
-    /*union {                
-
-        vuint32_t R;
-
-        struct {
-
-            vuint32_t BI2:32;
-
-        } B;
-
-    } BIU2; */
-		
-
-    vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */
-
-        union {     /* User Test 0 (Base+0x003C) */
-            vuint32_t R;
-            struct {
-                vuint32_t UTE:1;
-                vuint32_t:7;
-                vuint32_t DSI:8;
-                vuint32_t:10;
-                vuint32_t MRE:1;
-                vuint32_t MRV:1;
-                vuint32_t EIE:1;
-                vuint32_t AIS:1;
-                vuint32_t AIE:1;
-                vuint32_t AID:1;
-            } B;
-        } UT0;
-
-        union {   /* User Test 1 (Base+0x0040) */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT1;
-
-        union {   /* User Test 2 (Base+0x0044) */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT2;
-
-        union {   /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */
-            vuint32_t R;
-            struct {
-                vuint32_t MS:32;
-            } B;
-        } UMISR[5];
-		
-		 vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/
-
-    };                          /* end of CFLASH_tag */
-	
-/****************************************************************************/
-/*             MODULE : DFLASH (base address - 0xC3F8C000)                 */
-/****************************************************************************/
-    struct DFLASH_tag {
-        union {     /* Module Configuration (Base+0x0000) */
-            vuint32_t R;
-            struct {
-                vuint32_t EDC:1;
-                vuint32_t:4;
-                vuint32_t SIZE:3;
-                vuint32_t:1;
-                vuint32_t LAS:3;
-                vuint32_t:3;
-                vuint32_t MAS:1;
-                vuint32_t EER:1;
-                vuint32_t RWE:1;
-                vuint32_t:2;
-                vuint32_t PEAS:1;
-                vuint32_t DONE:1;
-                vuint32_t PEG:1;
-                vuint32_t:4;
-                vuint32_t PGM:1;
-                vuint32_t PSUS:1;
-                vuint32_t ERS:1;
-                vuint32_t ESUS:1;
-                vuint32_t EHV:1;
-            } B;
-        } MCR;
-
-        union {   	/* Low/Mid address block locking (Base+0x0004) */
-            vuint32_t R;
-            struct {
-                vuint32_t LME:1;
-                vuint32_t:10;
-                vuint32_t TSLK:1;
-                vuint32_t:16;
-                vuint32_t LLK:4;
-            } B;
-        } LML;
-        
-        vuint8_t DFLASH_reserved0[4]; /* Reserved 4 Bytes (+0x0008-0x000B) */
-
-
-        union {   /* Secondary Low/mid block locking (Base+0x000C)*/
-            vuint32_t R;
-            struct {
-                vuint32_t SLE:1;
-                vuint32_t:10;
-                vuint32_t STSLK:1;
-                vuint32_t:16;
-                vuint32_t SLK:4;
-            } B;
-        } SLL;
-
-        union {   /* Low/Mid address space block sel (Base+0x0010)*/
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t LSL:4;
-            } B;
-        } LMS;
-
-	vuint8_t DFLASH_reserved1[4]; /* Reserved 4 Bytes (+0x0014-0x0017)*/
-
-        union {    /* Address Register (Base+0x0018) */
-            vuint32_t R;
-            struct {
-                vuint32_t:9;
-                vuint32_t ADD:20;
-                vuint32_t:3;
-            } B;
-        } ADR;
-
-		vuint8_t DFLASH_reserved2[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */
-
-        union {        /* User Test 0 (Base+0x003C) */
-            vuint32_t R;
-            struct {
-                vuint32_t UTE:1;
-				vuint32_t:7;
-                vuint32_t DSI:8;
-				vuint32_t:10;
-                vuint32_t MRE:1;
-                vuint32_t MRV:1;
-                vuint32_t EIE:1;
-                vuint32_t AIS:1;
-                vuint32_t AIE:1;
-                vuint32_t AID:1;
-            } B;
-        } UT0;
-
-        union {    /* User Test 1 (Base+0x0040) */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT1;
-
-        union {    /* User Test 2 (Base+0x0044) */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT2;
-
-        union {  /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/
-            vuint32_t R;
-            struct {
-                vuint32_t MS:32;
-            } B;
-        } UMISR[5];
-
-    }; /* end of Dflash_tag */
-
-/****************************************************************************/
-/*          MODULE : SIU Lite (tagged as SIU for compatibility)             */
-/****************************************************************************/
-struct SIU_tag {
-
-    vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */
-
-    union { /* MCU ID1 (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t PARTNUM:16;
-            vuint32_t CSP:1;
-            vuint32_t PKG:5;
-            vuint32_t :2;
-            vuint32_t MAJOR_MASK:4;
-            vuint32_t MINOR_MASK:4;
-        } B;
-    } MIDR1;
-
-    union { /* MCU ID2 (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t SF:1;
-            vuint32_t FLASH_SIZE_1:4;
-            vuint32_t FLASH_SIZE_2:4;
-            vuint32_t :7;
-            vuint32_t PARTNUM:8;
-            vuint32_t :3;
-            vuint32_t EE:1;
-            vuint32_t :3;
-            vuint32_t FR:1;
-        } B;
-    } MIDR2;
-
-    vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */
-
-    union { /* Interrupt Status Flag (Base+0x0014)*/
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t EIF23:1;
-            vuint32_t EIF22:1;
-            vuint32_t EIF21:1;
-            vuint32_t EIF20:1;
-            vuint32_t EIF19:1;
-            vuint32_t EIF18:1;
-            vuint32_t EIF17:1;
-            vuint32_t EIF16:1;
-            vuint32_t EIF15:1;
-            vuint32_t EIF14:1;
-            vuint32_t EIF13:1;
-            vuint32_t EIF12:1;
-            vuint32_t EIF11:1;
-            vuint32_t EIF10:1;
-            vuint32_t EIF9:1;
-            vuint32_t EIF8:1;
-            vuint32_t EIF7:1;
-            vuint32_t EIF6:1;
-            vuint32_t EIF5:1;
-            vuint32_t EIF4:1;
-            vuint32_t EIF3:1;
-            vuint32_t EIF2:1;
-            vuint32_t EIF1:1;
-            vuint32_t EIF0:1;
-        } B;
-    } ISR;
-
-    union { /* Interrupt Request Enable (Base+0x0018) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t IRE23:1;
-            vuint32_t IRE22:1;
-            vuint32_t IRE21:1;
-            vuint32_t IRE20:1;
-            vuint32_t IRE19:1;
-            vuint32_t IRE18:1;
-            vuint32_t IRE17:1;
-            vuint32_t IRE16:1;
-            vuint32_t IRE15:1;
-            vuint32_t IRE14:1;
-            vuint32_t IRE13:1;
-            vuint32_t IRE12:1;
-            vuint32_t IRE11:1;
-            vuint32_t IRE10:1;
-            vuint32_t IRE9:1;
-            vuint32_t IRE8:1;
-            vuint32_t IRE7:1;
-            vuint32_t IRE6:1;
-            vuint32_t IRE5:1;
-            vuint32_t IRE4:1;
-            vuint32_t IRE3:1;
-            vuint32_t IRE2:1;
-            vuint32_t IRE1:1;
-            vuint32_t IRE0:1;
-        } B;
-    } IRER;
-
-    vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */
-
-    union { /* Interrupt Rising-Edge Event Enable (+0x0028) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t IREE23:1;
-            vuint32_t IREE22:1;
-            vuint32_t IREE21:1;
-            vuint32_t IREE20:1;
-            vuint32_t IREE19:1;
-            vuint32_t IREE18:1;
-            vuint32_t IREE17:1;
-            vuint32_t IREE16:1;
-            vuint32_t IREE15:1;
-            vuint32_t IREE14:1;
-            vuint32_t IREE13:1;
-            vuint32_t IREE12:1;
-            vuint32_t IREE11:1;
-            vuint32_t IREE10:1;
-            vuint32_t IREE9:1;
-            vuint32_t IREE8:1;
-            vuint32_t IREE7:1;
-            vuint32_t IREE6:1;
-            vuint32_t IREE5:1;
-            vuint32_t IREE4:1;
-            vuint32_t IREE3:1;
-            vuint32_t IREE2:1;
-            vuint32_t IREE1:1;
-            vuint32_t IREE0:1;
-        } B;
-    } IREER;
-
-    union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t IFEE23:1;
-            vuint32_t IFEE22:1;
-            vuint32_t IFEE21:1;
-            vuint32_t IFEE20:1;
-            vuint32_t IFEE19:1;
-            vuint32_t IFEE18:1;
-            vuint32_t IFEE17:1;
-            vuint32_t IFEE16:1;
-            vuint32_t IFEE15:1;
-            vuint32_t IFEE14:1;
-            vuint32_t IFEE13:1;
-            vuint32_t IFEE12:1;
-            vuint32_t IFEE11:1;
-            vuint32_t IFEE10:1;
-            vuint32_t IFEE9:1;
-            vuint32_t IFEE8:1;
-            vuint32_t IFEE7:1;
-            vuint32_t IFEE6:1;
-            vuint32_t IFEE5:1;
-            vuint32_t IFEE4:1;
-            vuint32_t IFEE3:1;
-            vuint32_t IFEE2:1;
-            vuint32_t IFEE1:1;
-            vuint32_t IFEE0:1;
-        } B;
-    } IFEER;
-
-    union { /* Interrupt Filter Enable (Base+0x0030) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t IFE23:1;
-            vuint32_t IFE22:1;
-            vuint32_t IFE21:1;
-            vuint32_t IFE20:1;
-            vuint32_t IFE19:1;
-            vuint32_t IFE18:1;
-            vuint32_t IFE17:1;
-            vuint32_t IFE16:1;
-            vuint32_t IFE15:1;
-            vuint32_t IFE14:1;
-            vuint32_t IFE13:1;
-            vuint32_t IFE12:1;
-            vuint32_t IFE11:1;
-            vuint32_t IFE10:1;
-            vuint32_t IFE9:1;
-            vuint32_t IFE8:1;
-            vuint32_t IFE7:1;
-            vuint32_t IFE6:1;
-            vuint32_t IFE5:1;
-            vuint32_t IFE4:1;
-            vuint32_t IFE3:1;
-            vuint32_t IFE2:1;
-            vuint32_t IFE1:1;
-            vuint32_t IFE0:1;
-        } B;
-    } IFER;
-
-    vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */
-
-    union { /* Pad Configuration 0..148 (Base+0x0040-0x0168)*/
-        vuint16_t R;
-        struct {
-                vuint16_t:1;
-                vuint16_t SMC:1;
-                vuint16_t APC:1;
-                vuint16_t:1;
-                vuint16_t PA:2;
-                vuint16_t OBE:1;
-                vuint16_t IBE:1;
-                vuint16_t:2;
-                vuint16_t ODE:1;
-                vuint16_t:2;
-                vuint16_t SRC:1;
-                vuint16_t WPE:1;
-                vuint16_t WPS:1;
-        } B;
-    } PCR[149];
-
-    vuint8_t SIU_reserved4[918]; /*Reserved 918 Bytes (Base+0x016A-0x04FF) */
-
-    union { /* Pad Selection for Mux Input (0x0500-0x53C) */
-        vuint8_t R;
-        struct {
-            vuint8_t :4;
-            vuint8_t PADSEL:4;
-        } B;
-    } PSMI[64];
-
-    vuint8_t SIU_reserved5[192]; /*Reserved 192 Bytes (Base+0x0540-0x05FF) */
-
-    union { /* GPIO Pad Data Output (Base+0x0600-0x06A0) */
-        vuint8_t R;
-        struct {
-            vuint8_t :7;
-            vuint8_t PDO:1;
-        } B;
-    } GPDO[124]; // only 124 GPD0 registers 
-
-    vuint8_t SIU_reserved6[388]; /*Reserved 388 Bytes 512-124=388 */
-
-    union { /* GPIO Pad Data Input (Base+0x0800-0x08A0) */
-        vuint8_t R;
-        struct {
-            vuint8_t :7;
-            vuint8_t PDI:1;
-        } B;
-    } GPDI[124]; // only 152 GPD0 registers 
-
-    vuint8_t SIU_reserved7[900]; /*Reserved 900 Bytes 1024-124=900 */
-
-    union { /* Parallel GPIO Pad Data Out 0-4 (0x0C00-0xC010) */
-        vuint32_t R;
-        struct {
-            vuint32_t PPD0:32;
-        } B;
-    } PGPDO[5];
-
-    vuint8_t SIU_reserved8[44]; /* Reserved 44 Bytes (Base+0x0C14-0x0C3F) */
-
-    union { /* Parallel GPIO Pad Data In 0-4 (0x0C40-0x0C50) */
-        vuint32_t R;
-        struct {
-            vuint32_t PPDI:32;
-        } B;
-    } PGPDI[5];
-
-    vuint8_t SIU_reserved9[44]; /* Reserved 44 Bytes (Base+0x0C54-0x0C7F) */
-
-    union { /* Masked Parallel GPIO Pad Data Out 0-9 (0x0C80-0x0CA4) */
-        vuint32_t R;
-        struct {
-            vuint32_t MASK:16;
-            vuint32_t MPPDO:16;
-        } B;
-    } MPGPDO[10];
-
-    vuint8_t SIU_reserved10[856]; /*Reserved 844 Bytes (Base+0x0CA8-0x0FFF)*/
-
-    union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :28;
-            vuint32_t MAXCNT:4;
-        } B;
-    } IFMC[24];
-
-    vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F)*/
-
-    union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */
-        vuint32_t R;
-        struct {
-            vuint32_t :28;
-            vuint32_t IFCP:4;
-        } B;
-    } IFCPR;
-
-    vuint8_t SIU_reserved12[12156]; /* Reserved 12156 Bytes (+0x1084-0x3FFF)*/
-
-}; /* end of SIU_tag */
-
-/****************************************************************************/
-/*                          MODULE : WKUP                                   */
-/****************************************************************************/
-struct WKUP_tag{
-
-    union { /* NMI Status Flag (Base+0x0000) */
-        vuint32_t R;
-        struct {
-			vuint32_t NIF0:1;  
-			vuint32_t NOVF0:1;
-			vuint32_t :30;
-        } B;
-    } NSR;
-
-    vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */
-
-    union { /* NMI Configuration (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t NLOCK0:1;
-            vuint32_t NDSS0:2;
-            vuint32_t NWRE0:1;
-            vuint32_t :1;
-            vuint32_t NREE0:1;
-            vuint32_t NFEE0:1;
-            vuint32_t NFE0:1;
-            vuint32_t :24;
-        } B;
-    } NCR;
-
-    vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */
-
-    union { /* Wakeup/Interrup status flag (Base+0x0014) */
-        vuint32_t R;
-        struct {
-            vuint32_t :3;
-			vuint32_t EIF:29;
-        } B;
-    } WISR;
-
-    union { /* Interrupt Request Enable (Base+0x0018) */
-        vuint32_t R;
-        struct {
-            vuint32_t :3;
-			vuint32_t EIRE:29; 
-        } B;
-    } IRER;
-
-    union { /* Wakeup Request Enable (Base+0x001C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :3;
-			vuint32_t WRE:29;
-        } B;
-    } WRER;
-
-    vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */
-
-    union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */
-        vuint32_t R;
-        struct {
-            vuint32_t :3;
-			vuint32_t IREE:29;
-        } B;
-    } WIREER;
-
-    union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :3;
-			vuint32_t IFEE:29;
-        } B;
-    } WIFEER;
-
-    union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */
-        vuint32_t R;
-        struct {
-            vuint32_t :3;
-			vuint32_t IFE:29;
-        } B;
-    } WIFER;
-
-    union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */
-        vuint32_t R;
-        struct {
-            vuint32_t :3;
-			vuint32_t IPUE:29;
-        } B;
-    } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
-
-    vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */
-
-}; /* end of WKUP_tag */
-
-/****************************************************************************/
-/* MODULE : EMIOS (base address - eMIOS0 0xC3FA_0000; eMIOS1 0xC3FA_4000)   */
-/****************************************************************************/
-
-struct EMIOS_CHANNEL_tag{
-
-    union { /* Channel A Data (UCn Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t A:16;
-        } B;
-    } CADR;
-
-    union { /* Channel B Data (UCn Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t B:16;
-        } B;
-    } CBDR;
-
-    union { /* Channel Counter (UCn Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t C:16;
-        } B;
-    } CCNTR;
-
-    union { /* Channel Control (UCn Base+0x000C) */
-        vuint32_t R;
-        struct {
-            vuint32_t FREN:1;
-            vuint32_t :3;
-            vuint32_t UCPRE:2;
-            vuint32_t UCPEN:1;
-            vuint32_t DMA:1;
-            vuint32_t :1;
-            vuint32_t IF:4;
-            vuint32_t FCK:1;
-            vuint32_t FEN:1;
-            vuint32_t :3;
-            vuint32_t FORCMA:1;
-            vuint32_t FORCMB:1;
-            vuint32_t :1;
-            vuint32_t BSL:2;
-            vuint32_t EDSEL:1;
-            vuint32_t EDPOL:1;
-            vuint32_t MODE:7;
-        } B;
-    } CCR;
-
-    union { /* Channel Status (UCn Base+0x0010) */
-        vuint32_t R;
-        struct {
-            vuint32_t OVR:1;
-            vuint32_t :15;
-            vuint32_t OVFL:1;
-            vuint32_t :12;
-            vuint32_t UCIN:1;
-            vuint32_t UCOUT:1;
-            vuint32_t FLAG:1;
-        } B;
-    } CSR;
-
-    union { /* Alternate Channel A Data (UCn Base+0x0014) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t ALTA:16;
-        } B;
-    } ALTCADR;
-
-    vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */
-
-}; /* end of EMIOS_CHANNEL_tag */
-
-
-struct EMIOS_tag{
-
-    union { /* Module Configuration (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t :1;
-            vuint32_t MDIS:1;
-            vuint32_t FRZ:1;
-            vuint32_t GTBE:1;
-            vuint32_t :1;
-            vuint32_t GPREN:1;
-            vuint32_t :10;
-            vuint32_t GPRE:8;
-            vuint32_t :8;
-        } B;
-    } MCR;
-
-    union { /* Global Flag (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t F31:1;
-            vuint32_t F30:1;
-            vuint32_t F29:1;
-            vuint32_t F28:1;
-            vuint32_t F27:1;
-            vuint32_t F26:1;
-            vuint32_t F25:1;
-            vuint32_t F24:1;
-            vuint32_t F23:1;
-            vuint32_t F22:1;
-            vuint32_t F21:1;
-            vuint32_t F20:1;
-            vuint32_t F19:1;
-            vuint32_t F18:1;
-            vuint32_t F17:1;
-            vuint32_t F16:1;
-            vuint32_t F15:1;
-            vuint32_t F14:1;
-            vuint32_t F13:1;
-            vuint32_t F12:1;
-            vuint32_t F11:1;
-            vuint32_t F10:1;
-            vuint32_t F9:1;
-            vuint32_t F8:1;
-            vuint32_t F7:1;
-            vuint32_t F6:1;
-            vuint32_t F5:1;
-            vuint32_t F4:1;
-            vuint32_t F3:1;
-            vuint32_t F2:1;
-            vuint32_t F1:1;
-            vuint32_t F0:1;
-        } B;
-    } GFR;
-
-    union { /* Output Update Disable (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t OU31:1;
-            vuint32_t OU30:1;
-            vuint32_t OU29:1;
-            vuint32_t OU28:1;
-            vuint32_t OU27:1;
-            vuint32_t OU26:1;
-            vuint32_t OU25:1;
-            vuint32_t OU24:1;
-            vuint32_t OU23:1;
-            vuint32_t OU22:1;
-            vuint32_t OU21:1;
-            vuint32_t OU20:1;
-            vuint32_t OU19:1;
-            vuint32_t OU18:1;
-            vuint32_t OU17:1;
-            vuint32_t OU16:1;
-            vuint32_t OU15:1;
-            vuint32_t OU14:1;
-            vuint32_t OU13:1;
-            vuint32_t OU12:1;
-            vuint32_t OU11:1;
-            vuint32_t OU10:1;
-            vuint32_t OU9:1;
-            vuint32_t OU8:1;
-            vuint32_t OU7:1;
-            vuint32_t OU6:1;
-            vuint32_t OU5:1;
-            vuint32_t OU4:1;
-            vuint32_t OU3:1;
-            vuint32_t OU2:1;
-            vuint32_t OU1:1;
-            vuint32_t OU0:1;
-        } B;
-    } OUDR;
-
-    union { /* Disable Channel (Base+0x000F) */
-        vuint32_t R;
-        struct {
-            vuint32_t CHDIS31:1;
-            vuint32_t CHDIS30:1;
-            vuint32_t CHDIS29:1;
-            vuint32_t CHDIS28:1;
-            vuint32_t CHDIS27:1;
-            vuint32_t CHDIS26:1;
-            vuint32_t CHDIS25:1;
-            vuint32_t CHDIS24:1;
-            vuint32_t CHDIS23:1;
-            vuint32_t CHDIS22:1;
-            vuint32_t CHDIS21:1;
-            vuint32_t CHDIS20:1;
-            vuint32_t CHDIS19:1;
-            vuint32_t CHDIS18:1;
-            vuint32_t CHDIS17:1;
-            vuint32_t CHDIS16:1;
-            vuint32_t CHDIS15:1;
-            vuint32_t CHDIS14:1;
-            vuint32_t CHDIS13:1;
-            vuint32_t CHDIS12:1;
-            vuint32_t CHDIS11:1;
-            vuint32_t CHDIS10:1;
-            vuint32_t CHDIS9:1;
-            vuint32_t CHDIS8:1;
-            vuint32_t CHDIS7:1;
-            vuint32_t CHDIS6:1;
-            vuint32_t CHDIS5:1;
-            vuint32_t CHDIS4:1;
-            vuint32_t CHDIS3:1;
-            vuint32_t CHDIS2:1;
-            vuint32_t CHDIS1:1;
-            vuint32_t CHDIS0:1;
-        } B;
-    } UCDIS;
-
-    vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */
-
-    struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */
-
-    vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */
-
-}; /* end of EMIOS_tag */
-
-/****************************************************************************/
-/*                          MODULE : SSCM                                    */
-/****************************************************************************/
-struct SSCM_tag{
-
-    union { /* Status (Base+0x0000) */
-        vuint16_t R;
-        struct {
-               vuint16_t:5;
-               vuint16_t PUB:1;  
-               vuint16_t SEC:1;
-               vuint16_t:1;
-               vuint16_t BMODE:3;
-               vuint16_t:5;
-        } B;
-    } STATUS;
-
-    union { /* System Memory Configuration (Base+0x002) */
-        vuint16_t R;
-        struct {
-				vuint16_t:5;
-                vuint16_t PRSZ:5;
-                vuint16_t PVLB:1;
-                vuint16_t DTSZ:4;
-                vuint16_t DVLD:1;
-        } B;
-    } MEMCONFIG;
-
-    vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */
-
-    union { /* Error Configuration (Base+0x0006) */
-        vuint16_t R;
-        struct {
-            vuint16_t :14;
-            vuint16_t PAE:1;
-            vuint16_t RAE:1;
-        } B;
-    } ERROR;
-
-   union { /* Debug Status Port (Base+0x0008) */
-        vuint16_t R;
-        struct {
-            vuint16_t :13;
-            vuint16_t DEBUG_MODE:3;
-        } B;
-    } DEBUGPORT;
-
-    vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */
-
-    union { /* Password Comparison High Word (Base+0x000C) */
-      vuint32_t R;
-      struct {
-            vuint32_t PWD_HI:32;
-        } B;
-    } PWCMPH;
-
-    union { /* Password Comparison Low Word (Base+0x0010)*/
-        vuint32_t R;
-        struct {
-            vuint32_t PWD_LO:32;
-        } B;
-    } PWCMPL;
-
-}; /* end of SSCM_tag */
-
-/****************************************************************************/
-/*                          MODULE : ME                                   */
-/****************************************************************************/
-struct ME_tag{
-
-    union { /* Global Status (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t S_CURRENTMODE:4;
-            vuint32_t S_MTRANS:1;
-            vuint32_t S_DC:1;
-            vuint32_t :2;
-            vuint32_t S_PDO:1;
-            vuint32_t :2;
-            vuint32_t S_MVR:1;
-            vuint32_t S_DFLA:2;
-            vuint32_t S_CFLA:2;
-            vuint32_t :9;
-            vuint32_t S_FMPLL:1;
-            vuint32_t S_FXOSC:1;
-            vuint32_t S_FIRC:1;
-            vuint32_t S_SYSCLK:4;
-        } B;
-    } GS;
-
-    union { /* Mode Control (Base+0x004) */
-        vuint32_t R;
-        struct {
-            vuint32_t TARGET_MODE:4;
-            vuint32_t :12;
-            vuint32_t KEY:16;
-        } B;
-    } MCTL;
-
-    union { /* Mode Enable (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t :18;
-            vuint32_t STANDBY:1;
-            vuint32_t :2;
-            vuint32_t STOP:1;
-            vuint32_t :1;
-            vuint32_t HALT:1;
-            vuint32_t RUN3:1;
-            vuint32_t RUN2:1;
-            vuint32_t RUN1:1;
-            vuint32_t RUN:1;
-            vuint32_t DRUN:1;
-            vuint32_t SAFE:1;
-            vuint32_t TEST:1;
-            vuint32_t RESET:1;
-        } B;
-    } MER;
-
-    union { /* Interrupt Status (Base+0x000C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :28;
-            vuint32_t I_ICONF:1;
-            vuint32_t I_IMODE:1;
-            vuint32_t I_SAFE:1;
-            vuint32_t I_MTC:1;
-        } B;
-    } IS;
-
-    union { /* Interrupt Mask (Base+0x0010) */
-        vuint32_t R;
-        struct {
-            vuint32_t :28;
-            vuint32_t M_ICONF:1;
-            vuint32_t M_IMODE:1;
-            vuint32_t M_SAFE:1;
-            vuint32_t M_MTC:1;
-        } B;
-    } IM;
-
-    union { /* Invalid Mode Transition Status (Base+0x0014) */
-        vuint32_t R;
-        struct {
-            vuint32_t :27;
-            vuint32_t S_MTI:1;
-            vuint32_t S_MRI:1;
-            vuint32_t S_DMA:1;
-            vuint32_t S_NMA:1;
-            vuint32_t S_SEA:1;
-        } B;
-    } IMTS;
-
-    union { /* Debug Mode Transition Status (Base+0x0018) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t MPH_BUSY:1;
-            vuint32_t :2;
-            vuint32_t PMC_PROG:1;
-            vuint32_t CORE_DBG:1;
-            vuint32_t :2;
-            vuint32_t SMR:1;
-            vuint32_t :1;
-            vuint32_t FMPLL_SC:1;
-            vuint32_t FXOSC_SC:1;
-            vuint32_t FIRC_SC:1;
-            vuint32_t :1;
-            vuint32_t SYSCLK_SW:1;
-            vuint32_t DFLASH_SC:1;
-            vuint32_t CFLASH_SC:1;
-            vuint32_t CDP_PRPH_0_143:1;
-            vuint32_t :3;
-            vuint32_t CDP_PRPH_96_127:1;
-            vuint32_t CDP_PRPH_64_95:1;
-            vuint32_t CDP_PRPH_32_63:1;
-            vuint32_t CDP_PRPH_0_31:1;
-        } B;
-    } DMTS;
-
-    vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */
-
-    union { /* Reset Mode Configuration (Base+0x0020) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t PDO:1;
-            vuint32_t :2;
-            vuint32_t MVRON:1;
-            vuint32_t DFLAON:2;
-            vuint32_t CFLAON:2;
-            vuint32_t :9;
-            vuint32_t FMPLLON:1;
-            vuint32_t FXOSCON:1;
-            vuint32_t FIRCON:1;
-            vuint32_t SYSCLK:4;
-        } B;
-    } RESET;
-
-    union { /* Test Mode Configuration (Base+0x0024) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t PDO:1;
-            vuint32_t :2;
-            vuint32_t MVRON:1;
-            vuint32_t DFLAON:2;
-            vuint32_t CFLAON:2;
-            vuint32_t :9;
-            vuint32_t FMPLLON:1;
-            vuint32_t FXOSCON:1;
-            vuint32_t FIRCON:1;
-            vuint32_t SYSCLK:4;
-        } B;
-    } TEST;
-
-    union { /* Safe Mode Configuration (Base+0x0028) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t PDO:1;
-            vuint32_t :2;
-            vuint32_t MVRON:1;
-            vuint32_t DFLAON:2;
-            vuint32_t CFLAON:2;
-            vuint32_t :9;
-            vuint32_t FMPLLON:1;
-            vuint32_t FXOSCON:1;
-            vuint32_t FIRCON:1;
-            vuint32_t SYSCLK:4;
-        } B;
-    } SAFE;
-
-    union { /* DRUN Mode Configuration (Base+0x002C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t PDO:1;
-            vuint32_t :2;
-            vuint32_t MVRON:1;
-            vuint32_t DFLAON:2;
-            vuint32_t CFLAON:2;
-            vuint32_t :9;
-            vuint32_t FMPLLON:1;
-            vuint32_t FXOSCON:1;
-            vuint32_t FIRCON:1;
-            vuint32_t SYSCLK:4;
-        } B;
-    } DRUN;
-
-    union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t PDO:1;
-            vuint32_t :2;
-            vuint32_t MVRON:1;
-            vuint32_t DFLAON:2;
-            vuint32_t CFLAON:2;
-            vuint32_t :9;
-            vuint32_t FMPLLON:1;
-            vuint32_t FXOSCON:1;
-            vuint32_t FIRCON:1;
-            vuint32_t SYSCLK:4;
-        } B;
-    } RUN[4];
-
-    union { /* HALT Mode Configuration (Base+0x0040) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t PDO:1;
-            vuint32_t :2;
-            vuint32_t MVRON:1;
-            vuint32_t DFLAON:2;
-            vuint32_t CFLAON:2;
-            vuint32_t :9;
-            vuint32_t FMPLLON:1;
-            vuint32_t FXOSCON:1;
-            vuint32_t FIRCON:1;
-            vuint32_t SYSCLK:4;
-        } B;
-    } HALT;
-
-    vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */
-
-    union { /* STOP Mode Configuration (Base+0x0048) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t PDO:1;
-            vuint32_t :2;
-            vuint32_t MVRON:1;
-            vuint32_t DFLAON:2;
-            vuint32_t CFLAON:2;
-            vuint32_t :9;
-            vuint32_t FMPLLON:1;
-            vuint32_t FXOSCON:1;
-            vuint32_t FIRCON:1;
-            vuint32_t SYSCLK:4;
-        } B;
-    } STOP;
-
-    vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */
-
-    union { /* STANDBY Mode Configuration (Base+0x0054) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t PDO:1;
-            vuint32_t :2;
-            vuint32_t MVRON:1;
-            vuint32_t DFLAON:2;
-            vuint32_t CFLAON:2;
-            vuint32_t :9;
-            vuint32_t FMPLLON:1;
-            vuint32_t FXOSCON:1;
-            vuint32_t FIRCON:1;
-            vuint32_t SYSCLK:4;
-        } B;
-    } STANDBY;
-
-    vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */
-
-    union {
-        vuint32_t R;
-        struct { /* Peripheral Status 0 (Base+0x0060) */
-            vuint32_t :8;
-            vuint32_t S_DMA_CH_MUX:1;
-            vuint32_t :6;
-            vuint32_t S_FLEXCAN0:1;
-	    vuint32_t :10;
-            vuint32_t S_DSPI1:1;
-            vuint32_t S_DSPI0:1;
-            vuint32_t :4;
-        } B;
-    } PS0;
-
-    union { /* Peripheral Status 1 (Base+0x0064)*/
-        vuint32_t R;
-        struct {
-            vuint32_t :6;
-            vuint32_t S_CTU:1;
-            vuint32_t :6;
-            vuint32_t S_LINFLEX2:1;
-            vuint32_t S_LINFLEX1:1;
-            vuint32_t S_LINFLEX0:1;
-            vuint32_t :14;
-            vuint32_t S_ADC1:1;
-            vuint32_t :1;
-        } B;
-    } PS1;
-
-    union { /* Peripheral Status 2 (Base+0x0068) */
-        vuint32_t R;
-        struct {
-            vuint32_t :3;
-            vuint32_t S_PIT_RTI:1;
-            vuint32_t S_RTC_API:1;
-            vuint32_t :18;
-            vuint32_t S_EMIOS0:1;
-            vuint32_t :2;
-            vuint32_t S_WKPU:1; 
-            vuint32_t S_SIUL:1;
-            vuint32_t :4;
-        } B;
-    } PS2;
-
-    union { /* Peripheral Status 3 (Base+0x006C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :23;
-            vuint32_t S_CMU:1;
-            vuint32_t :8;
-        } B;
-    } PS3;
-
-    vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */
-
-    union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :24;
-            vuint32_t RUN3:1;
-            vuint32_t RUN2:1;
-            vuint32_t RUN1:1;
-            vuint32_t RUN0:1;
-            vuint32_t DRUN:1;
-            vuint32_t SAFE:1;
-            vuint32_t TEST:1;
-            vuint32_t RESET:1;
-        } B;
-    } RUNPC[8];
-
-    union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */
-      vuint32_t R;
-      struct {
-            vuint32_t :18;
-            vuint32_t STANDBY:1;
-            vuint32_t :2;
-            vuint32_t STOP:1;
-            vuint32_t :1;
-            vuint32_t HALT:1;
-            vuint32_t :8;
-        } B;
-    } LPPC[8];
-
-
-    /* Note on PCTL registers: There are only some PCTL implemented in      */
-    /*  Bolero 1.5M/1M. In order to make the PCTL easily addressable, these      */
-    /*  are defined as an array (ie ME.PCTL[x].R). This means you have      */
-    /*  to be careful when addressing these registers in order not to       */
-    /*  access a PCTL that is not implemented. Following are available:     */
-    /*  104, 92, 91, 73, 72, 69, 68, 60, 57, 55, 53, 52,  51, 50, 49,48,			*/
-  	/*   44, 33, 32, 23, 21-16, 9-4						*/
-
-    union { /* Peripheral Control 0..143 (+0x00C0-0x014F) */
-        vuint8_t R;
-        struct {
-            vuint8_t :1;
-            vuint8_t DBG_F:1;
-            vuint8_t LP_CFG:3;
-            vuint8_t RUN_CFG:3;
-        } B;
-    } PCTL[105];
-
-}; /* end of ME_tag */
-   
-/****************************************************************************/
-/*                          MODULE : CGM                                   */
-/****************************************************************************/
-struct CGM_tag{
-    /*
-    The "CGM" has fairly wide coverage and essentially includes everything in
-
-    chapter 6/7 of the Bolero Reference Manual:
-
-        Base Address | Clock Sources
-
-       -----------------------------	    
-
-        0xC3FE0000   | FXOSC_CTL
-
-        0xC3FE0040   | SXOSC_CTL
-
-        0xC3FE0060   | FIRC_CTL
-
-        0xC3FE0080   | SIRC_CTL
-
-        0xC3FE00A0   | FMPLL
-
-        0xC3FE00C0   | CGM Block 1
-
-        0xC3FE0100   | CMU    
-
-        0xC3FE0120   | CGM Block 2
-
-
-
-        In this header file, "Base" referrs to the 1st address, 0xC3FE_0000 
-
-    */
-    /* FXOSC - 0xC3FE_0000*/
-    union { /* Fast OSC Control (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t OSCBYP:1;
-            vuint32_t :7;
-            vuint32_t EOCV:8;
-            vuint32_t M_OSC:1;
-            vuint32_t :2;
-            vuint32_t OSCDIV:5;
-            vuint32_t I_OSC:1;
-            vuint32_t:7;
-        } B;
-    } FXOSC_CTL;
-
-
-    /* Reserved Space between end of FXOSC and start SXOSC */
-    vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */
-
-
-    /* SXOSC - 0xC3FE_0040*/
-    union { /* Slow Osc Control (Base+0x0040) */
-        vuint32_t R;
-        struct {
-            vuint32_t OSCBYP:1;
-            vuint32_t :7;
-            vuint32_t EOCV:8;
-            vuint32_t M_OSC:1;
-            vuint32_t :2;
-            vuint32_t OSCDIV:5;
-            vuint32_t I_OSC:1;
-            vuint32_t :5;
-            vuint32_t S_OSC:1;
-            vuint32_t OSCON:1;
-        } B;
-    } SXOSC_CTL;
-
-
-    /* Reserved space between end of SXOSC and start of FIRC */
-    vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */
-
-
-    /* FIRC - 0xC3FE_0060 */
-    union { /* Fast IRC Control (Base+0x0060) */
-        vuint32_t R;
-        struct {
-            vuint32_t :10;
-            vuint32_t RCTRIM:6;
-            vuint32_t :3;
-            vuint32_t RCDIV:5;
-			vuint32_t :2;
-			vuint32_t FIRCON_STDBY:1;
-            vuint32_t :5;
-        } B;
-    } FIRC_CTL;
-
-
-    /* Reserved space between end of FIRC and start of SIRC */
-    vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */
-
-
-    /* SIRC - 0xC3FE_0080 */
-    union { /* Slow IRC Control (Base+0x0080) */
-        vuint32_t R;
-        struct {
-            vuint32_t :11;
-            vuint32_t SIRCTRIM:5;
-            vuint32_t :3;
-            vuint32_t SIRCDIV:5;
-            vuint32_t :3;
-            vuint32_t S_SIRC:1;
-            vuint32_t :3;
-            vuint32_t SIRCON_STDBY:1;
-        } B;
-    } SIRC_CTL;
-
-
-    /* Reserved space between end of SIRC and start of FMPLL */
-    vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */
-
-
-    /* FMPLL - 0xC3FE_00A0 */
-    union { /* FMPLL Control (Base+0x00A0) */
-        vuint32_t R;
-        struct {
-			vuint32_t:2;
-			vuint32_t IDF:4;
-			vuint32_t ODF:2;
-			vuint32_t:1;
-			vuint32_t NDIV:7;
-			vuint32_t:7;
-			vuint32_t EN_PLL_SW:1;
-			vuint32_t MODE:1;
-			vuint32_t UNLOCK_ONCE:1;
-			vuint32_t:1;
-			vuint32_t I_LOCK:1;
-			vuint32_t S_LOCK:1;
-			vuint32_t PLL_FAIL_MASK:1;
-			vuint32_t PLL_FAIL_FLAG:1;
-			vuint32_t:1;
-        } B;
-    } FMPLL_CR;
-
-    union { /* FMPLL Modulation (Base+0x00A4) */
-        vuint32_t R;
-        struct {
-            vuint32_t STRB_BYPASS:1;
-            vuint32_t :1;
-            vuint32_t SPRD_SEL:1;
-            vuint32_t MOD_PERIOD:13;
-            vuint32_t FM_EN:1;
-            vuint32_t INC_STEP:15;
-        } B;
-    } FMPLL_MR;
-
-
-    /* Reserved space between end of FMPLL and start of CGM Block 1 */
-    vuint8_t CGM_reserved4[88]; /*Reserved 88 bytes (Base+0x00A8-0x00FF) */
-
-    /* CMU - 0xC3FE_0100 */
-    union { /* CMU Control Status (Base+0x0100) */
-        vuint32_t R;
-        struct {
-            vuint32_t :8;
-            vuint32_t SFM:1;
-            vuint32_t :13;
-            vuint32_t CLKSEL1:2;
-            vuint32_t :5;
-            vuint32_t RCDIV:2;
-            vuint32_t CME_A:1;
-        } B;
-    } CMU_CSR;
-
-    union { /* CMU Frequency Display (Base+0x0104) */
-        vuint32_t R;
-        struct {
-            vuint32_t :12;
-            vuint32_t FD:20;
-        } B;
-    } CMU_FDR;
-
-    union { /* CMU High Freq Reference FMPLL (Base+0x0108) */
-        vuint32_t R;
-        struct {
-            vuint32_t :20;
-            vuint32_t HFREF:12;
-        } B;
-    } CMU_HFREFR;
-
-    union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :20;
-            vuint32_t LFREF:12;
-        } B;
-    } CMU_LFREFR;
-
-    union { /* CMU Interrupt Status (Base+0x0110) */
-        vuint32_t R;
-        struct {
-            vuint32_t :29;
-            vuint32_t FHHI:1;  // *_A not present in RM
-            vuint32_t FLLI:1;  // *_A not present in RM
-            vuint32_t OLRI:1;
-        } B;
-    } CMU_ISR;
-
-    /* Reserved space where IMR was previously positioned */
-    vuint8_t CGM_reserved5[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */
-
-    union { /* CMU Measurement Duration (Base+0x0118) */
-        vuint32_t R;
-        struct {
-            vuint32_t :12;
-            vuint32_t MD:20;
-        } B;
-    } CMU_MDR;
-
-
-    /* Reserved space between end of CMU and start of CGM Block 2 */
-    vuint8_t CGM_reserved6[596]; /*Reserved 596 bytes (Base+0x011C-0x036F) */
-
-    union { /* GCM Output Clock Enable (Base+0x0370) */
-        vuint32_t R;
-        struct {
-            vuint32_t :31;
-            vuint32_t EN:1;
-        } B;
-    } OC_EN;
-
-    union { /* CGM Output Clock Division Sel (Base+0x0374) */
-        vuint32_t R;
-        struct {
-            vuint32_t :2;
-            vuint32_t SELDIV:2;
-            vuint32_t SELCTL:4;
-			vuint32_t :24;
-        } B;
-    } OCDS_SC;
-
-    union { /* CGM System Clock Select Status (Base+0x0378) */
-        vuint32_t R;
-        struct {
-            vuint32_t :4;
-            vuint32_t SELSTAT:4;
-            vuint32_t :24;
-        } B;
-    } SC_SS;
-
-    union { /* CGM Sys Clk Div Config0 (Base+0x037C)       */
-        vuint8_t R;
-        struct {
-            vuint8_t DE0:1;
-            vuint8_t :3;
-            vuint8_t DIV0:4;
-        } B;
-    } SC_DC0;
-
-    union { /* CGM Sys Clk Div Config1 (Base+0x037D)       */
-        vuint8_t R;
-        struct {
-            vuint8_t DE1:1;
-            vuint8_t :3;
-            vuint8_t DIV1:4;
-        } B;
-    } SC_DC1;
-
-    union { /* CGM Sys Clk Div Config1 (Base+0x037E)       */
-        vuint8_t R;
-        struct {
-            vuint8_t DE2:1;
-            vuint8_t :3;
-            vuint8_t DIV2:4;
-        } B;
-    } SC_DC2;
-	
-	vuint8_t CGM_reserved7[1]; /*Reserved 1 byte (Base+0x037F) */
-	
-	 union { /* CGM Aux clock select control register (Base+0x0380) */
-        vuint32_t R;
-        struct {
-            vuint32_t :4;
-            vuint32_t SELCTL:4;
-            vuint32_t :24;
-        } B;
-    } AC0_SC;
-
-    
-
-}; /* end of CGM_tag */
-   
-/****************************************************************************/
-/*                          MODULE : RGM  base address - 0xC3FE_4000        */
-/****************************************************************************/
-struct RGM_tag{
-
-    union { /* Functional Event Status (Base+0x0000) */
-        vuint16_t R;
-        struct {
-            vuint16_t F_EXR:1;
-            vuint16_t :6;
-            vuint16_t F_FLASH:1;
-            vuint16_t F_LVD45:1;
-            vuint16_t F_CMU_FHL:1;
-            vuint16_t F_CMU_OLR:1;
-            vuint16_t F_FMPLL:1;
-            vuint16_t F_CHKSTOP:1;
-            vuint16_t F_SOFT_FUNC :1;
-            vuint16_t F_CORE:1;
-            vuint16_t F_JTAG:1;
-        } B;
-    } FES;
-
-    union { /* Destructive Event Status (Base+0x0002) */
-        vuint16_t R;
-        struct {
-            vuint16_t F_POR:1;
-            vuint16_t :10;
-            vuint16_t F_LVD27_VREG:1;
-			vuint16_t F_LVD27:1;
-            vuint16_t F_SWT:1;
-            vuint16_t F_LVD12_PD1:1;
-            vuint16_t F_LVD12_PD0:1;
-        } B;
-    } DES;
-
-    union { /* Functional Event Reset Disable (+0x0004) */
-        vuint16_t R;
-        struct {
-            vuint16_t D_EXR:1;
-            vuint16_t :6;
-            vuint16_t D_FLASH:1;
-            vuint16_t D_LVD45:1;
-            vuint16_t D_CMU_FHL:1;
-            vuint16_t D_CMU_OLR:1;
-            vuint16_t D_FMPLL:1;
-            vuint16_t D_CHKSTOP:1;
-            vuint16_t D_SOFT_FUNC:1;
-            vuint16_t D_CORE:1;
-            vuint16_t D_JTAG:1;
-        } B;
-    } FERD;
-
-    union { /* Destructive Event Reset Disable (Base+0x0006)*/
-        vuint16_t R;
-        struct {
-            vuint16_t :11;
-            vuint16_t D_LVD27_VREG:1;
-			vuint16_t D_LVD27:1;
-            vuint16_t D_SWT:1;
-            vuint16_t D_LVD12_PD1:1;
-            vuint16_t D_LVD12_PD0:1;
-        } B;
-    } DERD;
-
-    vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */
-
-    union { /* Functional Event Alt Request (Base+0x0010) */
-        vuint16_t R;
-        struct {
-			vuint16_t AR_EXR:1;
-			vuint16_t:6;
-			vuint16_t AR_FLASH:1;
-			vuint16_t AR_LVD45:1;
-			vuint16_t AR_CMU_FHL:1;
-			vuint16_t AR_CMU_OLR:1;
-			vuint16_t AR_FMPLL:1;
-			vuint16_t AR_CHKSTOP:1;
-			vuint16_t AR_SOFT_FUNC:1;
-			vuint16_t AR_CORE:1;
-			vuint16_t AR_JTAG:1;
-        } B;
-    } FEAR;
-	
-	union { /* Destructive Event Alt Request (Base+0x0012) */
-		vuint16_t R;
-		struct {
-			vuint16_t:11;
-			vuint16_t AR_LVD27_VREG:1;
-			vuint16_t AR_LVD27:1;
-			vuint16_t AR_SWT:1;
-			vuint16_t AR_LVD12_PD1:1;
-			vuint16_t AR_LVD12_PD0:1;
-            } B;
-        } DEAR;                 /* Destructive Event Alternate Request */
-
-    vuint8_t RGM_reserved1[4]; /*Reserved 4 bytes (Base+0x0014-0x0017) */
-
-    union { /* Functional Event Short Sequence (+0x0018) */
-        vuint16_t R;
-        struct {
-            vuint16_t SS_EXR:1;
-            vuint16_t :6;
-            vuint16_t SS_FLASH:1;
-            vuint16_t SS_LVD45:1;
-            vuint16_t SS_CMU_FHL:1;
-            vuint16_t SS_CMU_OLR:1;
-            vuint16_t SS_FMPLL:1;
-            vuint16_t SS_CHKSTOP:1;
-            vuint16_t SS_SOFT_FUNC:1;
-            vuint16_t SS_CORE:1;
-            vuint16_t SS_JTAG:1;
-        } B;
-    } FESS;
-
-    union { /* STANDBY reset sequence (Base+0x001A) */
-        vuint16_t R;
-        struct {
-            vuint16_t :8;
-            vuint16_t BOOT_FROM_BKP_RAM:1;
-            vuint16_t :7;
-        } B;
-    } STDBY;
-
-    union { /* Functional Bidirectional Reset En (+0x001C) */
-        vuint16_t R;
-        struct {
-            vuint16_t BE_EXR:1;
-            vuint16_t :6;
-            vuint16_t BE_FLASH:1;
-            vuint16_t BE_LVD45:1;
-            vuint16_t BE_CMU_FHL:1;
-            vuint16_t BE_CMU_OLR:1;
-            vuint16_t BE_FMPLL:1;
-            vuint16_t BE_CHKSTOP:1;
-            vuint16_t BE_SOFT_FUNC:1;
-            vuint16_t BE_CORE:1;
-            vuint16_t BE_JTAG:1;
-        } B;
-    } FBRE;
-
-}; /* end of RGM_tag */
-/****************************************************************************/
-/*                          MODULE : PCU  (base address 0xC3FE_8000)        */
-/****************************************************************************/
-struct PCU_tag{
-
-    union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :18;
-            vuint32_t STBY:1;
-            vuint32_t :2;
-            vuint32_t STOP:1;
-            vuint32_t :1;
-            vuint32_t HALT:1;
-            vuint32_t RUN3:1;
-            vuint32_t RUN2:1;
-            vuint32_t RUN1:1;
-            vuint32_t RUN0:1;
-            vuint32_t DRUN:1;
-            vuint32_t SAFE:1;
-            vuint32_t TEST:1;
-            vuint32_t RST:1;
-        } B;
-    } PCONF[4];
-
-    vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */
-
-    union { /* PCU Power Domain Status (Base+0x0040) */
-        vuint32_t R;
-        struct {
-            vuint32_t :28;
-            vuint32_t PD3:1;
-            vuint32_t PD2:1;
-            vuint32_t PD1:1;
-            vuint32_t PD0:1;
-        } B;
-    } PSTAT;
-
-    vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */
-
-
- /* Following register is from Voltage Regulators chapter of RM */
-
-    union { /* PCU Voltage Regulator Control (Base+0x0080) */
-        vuint32_t R;
-        struct {
-            vuint32_t :31;
-            vuint32_t MASK_LVDHV5:1;
-        } B;
-    } VREG_CTL; /* Changed from VCTL for consistency with other regs here */
-
-	}; /* end of PCU_tag */
-/****************************************************************************/
-/*                          MODULE : RTC/API                                */
-/****************************************************************************/
-struct RTC_tag{
-
-    union { /* RTC Supervisor Control (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t SUPV:1;
-            vuint32_t :31;
-        } B;
-    } RTCSUPV ;
-
-    union { /* RTC Control (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t CNTEN:1;
-            vuint32_t RTCIE:1;
-            vuint32_t FRZEN:1;
-            vuint32_t ROVREN:1;
-            vuint32_t RTCVAL:12;
-            vuint32_t APIEN:1;
-            vuint32_t APIIE:1;
-            vuint32_t CLKSEL:2;
-            vuint32_t DIV512EN:1;
-            vuint32_t DIV32EN:1;
-            vuint32_t APIVAL:10;
-        } B;
-    } RTCC;
-
-    union { /* RTC Status (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t :2;
-            vuint32_t RTCF:1;
-            vuint32_t :15;
-            vuint32_t APIF:1;
-            vuint32_t :2;
-            vuint32_t ROVRF:1;
-            vuint32_t :10;
-        } B;
-    } RTCS;
-
-    union { /* RTC Counter (Base+0x000C) */
-        vuint32_t R;
-        struct {
-            vuint32_t RTCCNT:32;
-        } B;
-    } RTCCNT;
-
-}; /* end of RTC_tag */
-
-/****************************************************************************/
-/*                          MODULE : PIT  (base address - 0xC3FF_FFFF)      */
-/****************************************************************************/
-  struct PIT_tag {
-
-    union { /* PIT Module Control (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t:30;
-            vuint32_t MDIS:1;
-            vuint32_t FRZ:1;
-        } B;
-    } PITMCR;
-
-    vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */
-
-    /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */
-    struct {
-
-        union { /* PIT Timer Load Value (Offset+0x0000) */
-            vuint32_t R;
-            struct {
-                vuint32_t TSV:32;
-            } B;
-        } LDVAL;
-
-        union { /* PIT Current Timer Value (Offset+0x0004) */
-            vuint32_t R;
-            struct {
-                vuint32_t TVL:32;
-            } B;
-        } CVAL;
-
-        union { /* PIT Timer Control (Offset+0x0008) */
-            vuint32_t R;
-            struct {
-                vuint32_t :30;
-                vuint32_t TIE:1;
-                vuint32_t TEN:1;
-            } B;
-        } TCTRL;
-
-        union { /* PIT Timer Control (Offset+0x0008) */
-            vuint32_t R;
-            struct {
-                vuint32_t :31;
-                vuint32_t TIF:1;
-            } B;
-        } TFLG;
-
-    }CH[8]; /* End of PIT Timer Channels */
-
-}; /* end of PIT_tag */	
-
-/****************************************************************************/
-/*                          MODULE : ADC1 (12 Bit)                          */
-/****************************************************************************/
-struct ADC1_tag {
-
-    union { /* ADC1 Main Configuration (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t OWREN:1;
-            vuint32_t WLSIDE:1;
-            vuint32_t MODE:1;
-            vuint32_t:4;
-            vuint32_t NSTART:1;
-            vuint32_t:1;
-            vuint32_t JTRGEN:1;
-            vuint32_t JEDGE:1;
-            vuint32_t JSTART:1;
-            vuint32_t:2;
-            vuint32_t CTUEN:1;
-            vuint32_t:8;
-			vuint32_t ADCLKSEL:1;
-            vuint32_t ABORTCHAIN:1;
-            vuint32_t ABORT:1;
-            vuint32_t ACKO:1;
-            vuint32_t:4;
-            vuint32_t PWDN:1;
-        } B;
-    } MCR;
-
-    union { /* ADC1 Main Status (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t:7;
-            vuint32_t NSTART:1;
-            vuint32_t JABORT:1;
-            vuint32_t:2;
-            vuint32_t JSTART:1;
-            vuint32_t:3;
-            vuint32_t CTUSTART:1;
-            vuint32_t CHADDR:7;
-            vuint32_t:3;
-            vuint32_t ACKO:1;
-            vuint32_t:2;
-            vuint32_t ADCSTATUS:3;
-        } B;
-    } MSR;
-
-    vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
-
-    union { /* ADC1 Interrupt Status (Base+0x0010) */
-        vuint32_t R;
-        struct {
-            vuint32_t:27;
-            vuint32_t EOCTU:1;
-            vuint32_t JEOC:1;
-            vuint32_t JECH:1;
-            vuint32_t EOC:1;
-            vuint32_t ECH:1;
-        } B;
-    } ISR;
-
-    union { /* ADC1 Channel Pending 0 (Base+0x0014) */
-        vuint32_t R; /*      (For precision channels)        */
-        struct {
-            vuint32_t :16;
-            vuint32_t EOC_CH15:1;
-            vuint32_t EOC_CH14:1;
-            vuint32_t EOC_CH13:1;
-            vuint32_t EOC_CH12:1;
-            vuint32_t EOC_CH11:1;
-            vuint32_t EOC_CH10:1;
-            vuint32_t EOC_CH9:1;
-            vuint32_t EOC_CH8:1;
-            vuint32_t EOC_CH7:1;
-            vuint32_t EOC_CH6:1;
-            vuint32_t EOC_CH5:1;
-            vuint32_t EOC_CH4:1;
-            vuint32_t EOC_CH3:1;
-            vuint32_t EOC_CH2:1;
-            vuint32_t EOC_CH1:1;
-            vuint32_t EOC_CH0:1;
-        } B;
-    } CEOCFR0;
-
-    union { /* ADC1 Channel Pending 1 (Base+0x0018) */
-        vuint32_t R; /*      (For standard Channels)         */
-        struct {
-            vuint32_t:19;
-            vuint32_t EOC_CH44:1;
-            vuint32_t EOC_CH43:1;
-            vuint32_t EOC_CH42:1;
-            vuint32_t EOC_CH41:1;
-            vuint32_t EOC_CH40:1;
-            vuint32_t EOC_CH39:1;
-            vuint32_t EOC_CH38:1;
-            vuint32_t EOC_CH37:1;
-            vuint32_t EOC_CH36:1;
-            vuint32_t EOC_CH35:1;
-            vuint32_t EOC_CH34:1;
-            vuint32_t EOC_CH33:1;
-            vuint32_t EOC_CH32:1;
-        } B;
-    } CEOCFR1;
-    
-        union { /* ADC1 Channel Pending 2 (Base+0x001C) */
-        vuint32_t R; /*      (For External Channels)         */
-        struct {
-            vuint32_t EOC_CH95:1;
-            vuint32_t EOC_CH94:1;
-            vuint32_t EOC_CH93:1;
-            vuint32_t EOC_CH92:1;
-            vuint32_t EOC_CH91:1;
-            vuint32_t EOC_CH90:1;
-            vuint32_t EOC_CH89:1;
-            vuint32_t EOC_CH88:1;
-            vuint32_t EOC_CH87:1;
-            vuint32_t EOC_CH86:1;
-            vuint32_t EOC_CH85:1;
-            vuint32_t EOC_CH84:1;
-            vuint32_t EOC_CH83:1;
-            vuint32_t EOC_CH82:1;
-            vuint32_t EOC_CH81:1;
-            vuint32_t EOC_CH80:1;
-            vuint32_t EOC_CH79:1;
-            vuint32_t EOC_CH78:1;
-            vuint32_t EOC_CH77:1;
-            vuint32_t EOC_CH76:1;
-            vuint32_t EOC_CH75:1;
-            vuint32_t EOC_CH74:1;
-            vuint32_t EOC_CH73:1;
-            vuint32_t EOC_CH72:1;
-            vuint32_t EOC_CH71:1;
-            vuint32_t EOC_CH70:1;
-            vuint32_t EOC_CH69:1;
-            vuint32_t EOC_CH68:1;
-            vuint32_t EOC_CH67:1;
-            vuint32_t EOC_CH66:1;
-            vuint32_t EOC_CH65:1;
-            vuint32_t EOC_CH64:1;
-        } B;
-    } CEOCFR2;
-
-
-    union { /* ADC1 Interrupt Mask (Base+0020) */
-        vuint32_t R;
-        struct {
-            vuint32_t:27;
-            vuint32_t MSKEOCTU:1;
-            vuint32_t MSKJEOC:1;
-            vuint32_t MSKJECH:1;
-            vuint32_t MSKEOC:1;
-            vuint32_t MSKECH:1;
-        } B;
-    } IMR;
-
-    union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */
-        vuint32_t R; /*      (For Precision Channels)               */
-        struct {
-            vuint32_t:16;
-            vuint32_t CIM15:1;
-            vuint32_t CIM14:1;
-            vuint32_t CIM13:1;
-            vuint32_t CIM12:1;
-            vuint32_t CIM11:1;
-            vuint32_t CIM10:1;
-            vuint32_t CIM9:1;
-            vuint32_t CIM8:1;
-            vuint32_t CIM7:1;
-            vuint32_t CIM6:1;
-            vuint32_t CIM5:1;
-            vuint32_t CIM4:1;
-            vuint32_t CIM3:1;
-            vuint32_t CIM2:1;
-            vuint32_t CIM1:1;
-            vuint32_t CIM0:1;
-        } B;
-    } CIMR0;
-
-    union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */
-        vuint32_t R; /*      (For Standard Channels)            */
-        struct {
-            vuint32_t:19;
-            vuint32_t CIM44:1;
-            vuint32_t CIM43:1;
-            vuint32_t CIM42:1;
-            vuint32_t CIM41:1;
-            vuint32_t CIM40:1;
-            vuint32_t CIM39:1;
-            vuint32_t CIM38:1;
-            vuint32_t CIM37:1;
-            vuint32_t CIM36:1;
-            vuint32_t CIM35:1;
-            vuint32_t CIM34:1;
-            vuint32_t CIM33:1;
-            vuint32_t CIM32:1;
-        } B;
-    } CIMR1;
-    
-        union { /* ADC1 Channel Interrupt Mask 2 (Base+0x002C) */
-        vuint32_t R; /*      (For External Mux'd Channels)               */
-        struct {
-            vuint32_t CIM95:1;
-            vuint32_t CIM94:1;
-            vuint32_t CIM93:1;
-            vuint32_t CIM92:1;
-            vuint32_t CIM91:1;
-            vuint32_t CIM90:1;
-            vuint32_t CIM89:1;
-            vuint32_t CIM88:1;
-            vuint32_t CIM87:1;
-            vuint32_t CIM86:1;
-            vuint32_t CIM85:1;
-            vuint32_t CIM84:1;
-            vuint32_t CIM83:1;
-            vuint32_t CIM82:1;
-            vuint32_t CIM81:1;
-            vuint32_t CIM80:1;
-            vuint32_t CIM79:1;
-            vuint32_t CIM78:1;
-            vuint32_t CIM77:1;
-            vuint32_t CIM76:1;
-            vuint32_t CIM75:1;
-            vuint32_t CIM74:1;
-            vuint32_t CIM73:1;
-            vuint32_t CIM72:1;
-            vuint32_t CIM71:1;
-            vuint32_t CIM70:1;
-            vuint32_t CIM69:1;
-            vuint32_t CIM68:1;
-            vuint32_t CIM67:1;
-            vuint32_t CIM66:1;
-            vuint32_t CIM65:1;
-            vuint32_t CIM64:1;
-        } B;
-    } CIMR2;
-
-
-    union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/
-        vuint32_t R;
-        struct {
-            vuint32_t:26;
-            vuint32_t WDG2H:1;
-            vuint32_t WDG2L:1;
-            vuint32_t WDG1H:1;
-            vuint32_t WDG1L:1;
-            vuint32_t WDG0H:1;
-            vuint32_t WDG0L:1;
-        } B;
-    } WTISR;
-
-    union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */
-        vuint32_t R;
-        struct {
-            vuint32_t:26;
-            vuint32_t MSKWDG2H:1;
-            vuint32_t MSKWDG2L:1;
-            vuint32_t MSKWDG1H:1;
-            vuint32_t MSKWDG1L:1;
-            vuint32_t MSKWDG0H:1;
-            vuint32_t MSKWDG0L:1;
-        } B;
-    } WTIMR;
-
-    vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */
-
-    union { /* ADC1 DMA Enable (Base+0x0040) */
-        vuint32_t R;
-        struct {
-            vuint32_t:30;
-            vuint32_t DCLR:1;
-            vuint32_t DMAEN:1;
-        } B;
-    } DMAE;
-
-    union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */
-        vuint32_t R; /*      (for precision channels)           */
-        struct {
-          vuint32_t:16;
-            vuint32_t DMA15:1;
-            vuint32_t DMA14:1;
-            vuint32_t DMA13:1;
-            vuint32_t DMA12:1;
-            vuint32_t DMA11:1;
-            vuint32_t DMA10:1;
-            vuint32_t DMA9:1;
-            vuint32_t DMA8:1;
-            vuint32_t DMA7:1;
-            vuint32_t DMA6:1;
-            vuint32_t DMA5:1;
-            vuint32_t DMA4:1;
-            vuint32_t DMA3:1;
-            vuint32_t DMA2:1;
-            vuint32_t DMA1:1;
-            vuint32_t DMA0:1;
-        } B;
-    } DMAR0;
-    
-        union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */
-        vuint32_t R; /*      (for precision channels)           */
-        struct {
-          vuint32_t:19;
-            vuint32_t DMA44:1;
-            vuint32_t DMA43:1;
-            vuint32_t DMA42:1;
-            vuint32_t DMA41:1;
-            vuint32_t DMA40:1;
-            vuint32_t DMA39:1;
-            vuint32_t DMA38:1;
-            vuint32_t DMA37:1;
-            vuint32_t DMA36:1;
-            vuint32_t DMA35:1;
-            vuint32_t DMA34:1;
-            vuint32_t DMA33:1;
-            vuint32_t DMA32:1;
-        } B;
-    } DMAR1;
-    
-        union { /* ADC1 DMA Channel Select 2 (Base+0x004C) */
-        vuint32_t R; /*      (for External channels)           */
-        struct {
-            vuint32_t DMA95:1;
-            vuint32_t DMA94:1;
-            vuint32_t DMA93:1;
-            vuint32_t DMA92:1;
-            vuint32_t DMA91:1;
-            vuint32_t DMA90:1;
-            vuint32_t DMA89:1;
-            vuint32_t DMA88:1;
-            vuint32_t DMA87:1;
-            vuint32_t DMA86:1;
-            vuint32_t DMA85:1;
-            vuint32_t DMA84:1;
-            vuint32_t DMA83:1;
-            vuint32_t DMA82:1;
-            vuint32_t DMA81:1;
-            vuint32_t DMA80:1;
-            vuint32_t DMA79:1;
-            vuint32_t DMA78:1;
-            vuint32_t DMA77:1;
-            vuint32_t DMA76:1;
-            vuint32_t DMA75:1;
-            vuint32_t DMA74:1;
-            vuint32_t DMA73:1;
-            vuint32_t DMA72:1;
-            vuint32_t DMA71:1;
-            vuint32_t DMA70:1;
-            vuint32_t DMA69:1;
-            vuint32_t DMA68:1;
-            vuint32_t DMA67:1;
-            vuint32_t DMA66:1;
-            vuint32_t DMA65:1;
-            vuint32_t DMA64:1;
-        } B;
-    } DMAR2;
-
-    vuint8_t ADC1_reserved4[16]; /* Reserved 16 bytes (Base+0x0048-0x005F) */
-
-    /* Note the threshold registers are not implemented as an array for    */
-    /*  concistency with ADC0 header section                               */
-
-    union { /* ADC1 Threshold  0 (Base+0x0060) */
-        vuint32_t R;
-        struct {
-          vuint32_t:4;
-            vuint32_t THRH:12;
-            vuint32_t:4;
-            vuint32_t THRL:12;
-        } B;
-    } THRHLR0;
-
-    union { /* ADC1 Threshold  1 (Base+0x0064) */
-        vuint32_t R;
-        struct {
-            vuint32_t:4;
-            vuint32_t THRH:12;
-            vuint32_t:4;
-            vuint32_t THRL:12;
-        } B;
-    } THRHLR1;
-
-    union { /* ADC1 Threshold  2 (Base+0x0068) */
-        vuint32_t R;
-        struct {
-          vuint32_t:4;
-            vuint32_t THRH:12;
-            vuint32_t:4;
-            vuint32_t THRL:12;
-        } B;
-    } THRHLR2;
-
-    vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */
-
-    union { /* ADC1 Presampling Control (Base+0x0080) */
-        vuint32_t R;
-        struct {
-          vuint32_t:25;
-            vuint32_t PREVAL2:2;
-            vuint32_t PREVAL1:2;
-            vuint32_t PREVAL0:2;
-            vuint32_t PRECONV:1;
-        } B;
-    } PSCR;
-
-    union { /* ADC1 Presampling 0 (Base+0x0084) */
-        vuint32_t R; /*      (precision channels)        */
-        struct {
-            vuint32_t:16;
-            vuint32_t PRES15:1;
-            vuint32_t PRES14:1;
-            vuint32_t PRES13:1;
-            vuint32_t PRES12:1;
-            vuint32_t PRES11:1;
-            vuint32_t PRES10:1;
-            vuint32_t PRES9:1;
-            vuint32_t PRES8:1;
-            vuint32_t PRES7:1;
-            vuint32_t PRES6:1;
-            vuint32_t PRES5:1;
-            vuint32_t PRES4:1;
-            vuint32_t PRES3:1;
-            vuint32_t PRES2:1;
-            vuint32_t PRES1:1;
-            vuint32_t PRES0:1;
-        } B;
-    } PSR0;
-
-   union { /* ADC1 Presampling 1 (Base+0x0088) */
-        vuint32_t R; /*      (standard channels)         */
-        struct {
-            vuint32_t:19;
-            vuint32_t PRES44:1;
-            vuint32_t PRES43:1;
-            vuint32_t PRES42:1;
-            vuint32_t PRES41:1;
-            vuint32_t PRES40:1;
-            vuint32_t PRES39:1;
-            vuint32_t PRES38:1;
-            vuint32_t PRES37:1;
-            vuint32_t PRES36:1;
-            vuint32_t PRES35:1;
-            vuint32_t PRES34:1;
-            vuint32_t PRES33:1;
-            vuint32_t PRES32:1;
-        } B;
-    } PSR1;
-
-    
-        union { /* ADC1 Presampling 2 (Base+0x008C) */
-        vuint32_t R; /*      (precision channels)        */
-        struct {
-            vuint32_t PRES95:1;
-            vuint32_t PRES94:1;
-            vuint32_t PRES93:1;
-            vuint32_t PRES92:1;
-            vuint32_t PRES91:1;
-            vuint32_t PRES90:1;
-            vuint32_t PRES89:1;
-            vuint32_t PRES88:1;
-            vuint32_t PRES87:1;
-            vuint32_t PRES86:1;
-            vuint32_t PRES85:1;
-            vuint32_t PRES84:1;
-            vuint32_t PRES83:1;
-            vuint32_t PRES82:1;
-            vuint32_t PRES81:1;
-            vuint32_t PRES80:1;
-            vuint32_t PRES79:1;
-            vuint32_t PRES78:1;
-            vuint32_t PRES77:1;
-            vuint32_t PRES76:1;
-            vuint32_t PRES75:1;
-            vuint32_t PRES74:1;
-            vuint32_t PRES73:1;
-            vuint32_t PRES72:1;
-            vuint32_t PRES71:1;
-            vuint32_t PRES70:1;
-            vuint32_t PRES69:1;
-            vuint32_t PRES68:1;
-            vuint32_t PRES67:1;
-            vuint32_t PRES66:1;
-            vuint32_t PRES65:1;
-            vuint32_t PRES64:1;
-        } B;
-    } PSR2;
-
-    
-    vuint8_t ADC1_reserved6[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */
-
-    /* Note the following CTR registers are NOT implemented as an array to */
-    /*  try and maintain some concistency through the header file          */
-    /*  (The registers are however identical)                              */
-
-    union { /* ADC1 Conversion Timing 0 (Base+0x0094) */
-        vuint32_t R; /*      (precision channels)              */
-        struct {
-            vuint32_t:16;
-            vuint32_t INPLATCH:1;
-            vuint32_t:1;
-            vuint32_t OFFSHIFT:2;
-            vuint32_t:1;
-            vuint32_t INPCMP:2;
-            vuint32_t:1;
-            vuint32_t INPSAMP:8;
-        } B;
-    } CTR0;
-
-    union { /* ADC1 Conversion Timing 1 (Base+0x0098) */
-        vuint32_t R; /*      (standard channels)              */
-        struct {
-            vuint32_t:16;
-            vuint32_t INPLATCH:1;
-            vuint32_t:4;
-            vuint32_t INPCMP:2;
-            vuint32_t:1;
-            vuint32_t INPSAMP:8;
-        } B;
-    } CTR1;
-    
-    
-        union { /* ADC1 Conversion Timing 2 (Base+0x009C) */
-        vuint32_t R; /*      (External channels)              */
-        struct {
-            vuint32_t:16;
-            vuint32_t INPLATCH:1;
-            vuint32_t:4;
-            vuint32_t INPCMP:2;
-            vuint32_t:1;
-            vuint32_t INPSAMP:8;
-        } B;
-    } CTR2;
-
-    vuint8_t ADC1_reserved7[8]; /* Reserved 12 bytes (Base+0x009C-0x00A3) */
-
-    union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */
-        vuint32_t R; /*      (precision channels)                  */
-        struct {
-            vuint32_t :16;
-            vuint32_t CH15:1;
-            vuint32_t CH14:1;
-            vuint32_t CH13:1;
-            vuint32_t CH12:1;
-            vuint32_t CH11:1;
-            vuint32_t CH10:1;
-            vuint32_t CH9:1;
-            vuint32_t CH8:1;
-            vuint32_t CH7:1;
-            vuint32_t CH6:1;
-            vuint32_t CH5:1;
-            vuint32_t CH4:1;
-            vuint32_t CH3:1;
-            vuint32_t CH2:1;
-            vuint32_t CH1:1;
-            vuint32_t CH0:1;
-        } B;
-    } NCMR0;
-
-        union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */
-        vuint32_t R; /*      (standard channels)                    */
-        struct {
-            vuint32_t:19;
-            vuint32_t CH44:1;
-            vuint32_t CH43:1;
-            vuint32_t CH42:1;
-            vuint32_t CH41:1;
-            vuint32_t CH40:1;
-            vuint32_t CH39:1;
-            vuint32_t CH38:1;
-            vuint32_t CH37:1;
-            vuint32_t CH36:1;
-            vuint32_t CH35:1;
-            vuint32_t CH34:1;
-            vuint32_t CH33:1;
-            vuint32_t CH32:1;
-        } B;
-    } NCMR1;
-    
-    
-        union { /* ADC1 Normal Conversion Mask 2 (Base+0x00AC) */
-        vuint32_t R; /*      (External channels)                    */
-        struct {
-            vuint32_t CH95:1;
-            vuint32_t CH94:1;
-            vuint32_t CH93:1;
-            vuint32_t CH92:1;
-            vuint32_t CH91:1;
-            vuint32_t CH90:1;
-            vuint32_t CH89:1;
-            vuint32_t CH88:1;
-            vuint32_t CH87:1;
-            vuint32_t CH86:1;
-            vuint32_t CH85:1;
-            vuint32_t CH84:1;
-            vuint32_t CH83:1;
-            vuint32_t CH82:1;
-            vuint32_t CH81:1;
-            vuint32_t CH80:1;
-            vuint32_t CH79:1;
-            vuint32_t CH78:1;
-            vuint32_t CH77:1;
-            vuint32_t CH76:1;
-            vuint32_t CH75:1;
-            vuint32_t CH74:1;
-            vuint32_t CH73:1;
-            vuint32_t CH72:1;
-            vuint32_t CH71:1;
-            vuint32_t CH70:1;
-            vuint32_t CH69:1;
-            vuint32_t CH68:1;
-            vuint32_t CH67:1;
-            vuint32_t CH66:1;
-            vuint32_t CH65:1;
-            vuint32_t CH64:1;
-        } B;
-    } NCMR2;
-
-    vuint8_t ADC1_reserved8[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B4) */
-
-    union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */
-        vuint32_t R; /*      (precision channels)                    */
-        struct {
-            vuint32_t :16;
-            vuint32_t CH15:1;
-            vuint32_t CH14:1;
-            vuint32_t CH13:1;
-            vuint32_t CH12:1;
-            vuint32_t CH11:1;
-            vuint32_t CH10:1;
-            vuint32_t CH9:1;
-            vuint32_t CH8:1;
-            vuint32_t CH7:1;
-            vuint32_t CH6:1;
-            vuint32_t CH5:1;
-            vuint32_t CH4:1;
-            vuint32_t CH3:1;
-            vuint32_t CH2:1;
-            vuint32_t CH1:1;
-            vuint32_t CH0:1;
-        } B;
-    } JCMR0;
-
-        union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */
-        vuint32_t R; /*      (standard channels)                     */
-        struct {
-            vuint32_t :19;
-            vuint32_t CH44:1;
-            vuint32_t CH43:1;
-            vuint32_t CH42:1;
-            vuint32_t CH41:1;
-            vuint32_t CH40:1;
-            vuint32_t CH39:1;
-            vuint32_t CH38:1;
-            vuint32_t CH37:1;
-            vuint32_t CH36:1;
-            vuint32_t CH35:1;
-            vuint32_t CH34:1;
-            vuint32_t CH33:1;
-            vuint32_t CH32:1;
-        } B;
-    } JCMR1;
-    
-    
-        union { /* ADC1 Injected Conversion Mask 2 (Base+0x00BC) */
-        vuint32_t R; /*      (External channels)                    */
-        struct {
-            vuint32_t CH95:1;
-            vuint32_t CH94:1;
-            vuint32_t CH93:1;
-            vuint32_t CH92:1;
-            vuint32_t CH91:1;
-            vuint32_t CH90:1;
-            vuint32_t CH89:1;
-            vuint32_t CH88:1;
-            vuint32_t CH87:1;
-            vuint32_t CH86:1;
-            vuint32_t CH85:1;
-            vuint32_t CH84:1;
-            vuint32_t CH83:1;
-            vuint32_t CH82:1;
-            vuint32_t CH81:1;
-            vuint32_t CH80:1;
-            vuint32_t CH79:1;
-            vuint32_t CH78:1;
-            vuint32_t CH77:1;
-            vuint32_t CH76:1;
-            vuint32_t CH75:1;
-            vuint32_t CH74:1;
-            vuint32_t CH73:1;
-            vuint32_t CH72:1;
-            vuint32_t CH71:1;
-            vuint32_t CH70:1;
-            vuint32_t CH69:1;
-            vuint32_t CH68:1;
-            vuint32_t CH67:1;
-            vuint32_t CH66:1;
-            vuint32_t CH65:1;
-            vuint32_t CH64:1;
-        } B;
-    } JCMR2;
-
-   vuint8_t ADC1_reserved9[4]; /* Reserved 4 bytes (Base+0x00C0=0x00C4) */
-   
-   	union {  /* Decode Signals Delay Register (base+0x00C4)*/
-        vuint32_t R;
-            struct {
-                vuint32_t:20;                
-                vuint32_t DSD:12;
-            } B;
-        } DSDR; 
-	
-	
-	union {  /* Power Down Exit Delay Register (base+0x00C8)*/
-        vuint32_t R;
-            struct {
-                vuint32_t:24;                
-                vuint32_t PDED:8;
-            } B;
-        } PDEDR;     
-
-	vuint8_t ADC1_reserved10[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */		
-
-    union { /* ADC1 Channel 0-39 Data (Base+0x0100-0x019C) */
-        vuint32_t R; /* Note CDR[16..31] and [44..63] are reserved 0x0140-0x017F              */
-        struct {
-            vuint32_t:12;
-            vuint32_t VALID:1;
-            vuint32_t OVERW:1;
-            vuint32_t RESULT:2;
-            vuint32_t:4;
-            vuint32_t CDATA:12;
-        } B;
-    } CDR[96];
-
-    vuint8_t ADC1_reserved11[48]; /* Reserved 48 bytes (Base+0x0280-0x002B0) */
-
-    union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */
-        vuint32_t R; /*      (precision channels)                    */
-        struct {
-            vuint32_t WSEL_CH7:4;
-            vuint32_t WSEL_CH6:4;
-            vuint32_t WSEL_CH5:4;
-            vuint32_t WSEL_CH4:4;
-            vuint32_t WSEL_CH3:4;
-            vuint32_t WSEL_CH2:4;
-            vuint32_t WSEL_CH1:4;
-            vuint32_t WSEL_CH0:4;
-        } B;
-    } CWSELR0;
-
-    union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */
-        vuint32_t R; /*      (precision channels)                    */
-        struct {
-            vuint32_t WSEL_CH15:4;
-            vuint32_t WSEL_CH14:4;
-            vuint32_t WSEL_CH13:4;
-            vuint32_t WSEL_CH12:4;
-            vuint32_t WSEL_CH11:4;
-            vuint32_t WSEL_CH10:4;
-            vuint32_t WSEL_CH9:4;
-            vuint32_t WSEL_CH8:4;
-        } B;
-    } CWSELR1;
-
-    vuint8_t ADC1_reserved12[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */
-
-    union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */
-        vuint32_t R; /*      (standard channels)                     */
-        struct {
-            vuint32_t WSEL_CH39:4;
-            vuint32_t WSEL_CH38:4;
-            vuint32_t WSEL_CH37:4;
-            vuint32_t WSEL_CH36:4;
-            vuint32_t WSEL_CH35:4;
-            vuint32_t WSEL_CH34:4;
-            vuint32_t WSEL_CH33:4;
-            vuint32_t WSEL_CH32:4;
-        } B;
-    } CWSELR4;
-
-        union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */
-        vuint32_t R; /*      (standard channels)                     */
-        struct {
-            vuint32_t:12;
-            vuint32_t WSEL_CH44:4;
-            vuint32_t WSEL_CH43:4;
-            vuint32_t WSEL_CH42:4;
-            vuint32_t WSEL_CH41:4;
-            vuint32_t WSEL_CH40:4;
-        } B;
-    } CWSELR5;
-    
-    vuint8_t ADC1_reserved42[8]; /* Reserved 8 bytes (Base+0x02C8-0x02D0) */
-    
-        union { /* ADC1 Channel Watchdog Select 8 (Base+0x02D0) */
-        vuint32_t R; /*      (standard channels)                     */
-        struct {
-            vuint32_t WSEL_CH71:4;
-            vuint32_t WSEL_CH70:4;
-            vuint32_t WSEL_CH69:4;
-            vuint32_t WSEL_CH68:4;
-            vuint32_t WSEL_CH67:4;
-            vuint32_t WSEL_CH66:4;
-            vuint32_t WSEL_CH65:4;
-            vuint32_t WSEL_CH64:4;
-        } B;
-    } CWSELR8;
-    
-        union { /* ADC1 Channel Watchdog Select 9 (Base+0x02D4) */
-        vuint32_t R; /*      (standard channels)                     */
-        struct {
-            vuint32_t WSEL_CH79:4;
-            vuint32_t WSEL_CH78:4;
-            vuint32_t WSEL_CH77:4;
-            vuint32_t WSEL_CH76:4;
-            vuint32_t WSEL_CH75:4;
-            vuint32_t WSEL_CH74:4;
-            vuint32_t WSEL_CH73:4;
-            vuint32_t WSEL_CH72:4;
-        } B;
-    } CWSELR9;
-    
-        union { /* ADC1 Channel Watchdog Select 10 (Base+0x02D8) */
-        vuint32_t R; /*      (standard channels)                     */
-        struct {
-            vuint32_t WSEL_CH87:4;
-            vuint32_t WSEL_CH86:4;
-            vuint32_t WSEL_CH85:4;
-            vuint32_t WSEL_CH84:4;
-            vuint32_t WSEL_CH83:4;
-            vuint32_t WSEL_CH82:4;
-            vuint32_t WSEL_CH81:4;
-            vuint32_t WSEL_CH80:4;
-        } B;
-    } CWSELR10;
-    
-        union { /* ADC1 Channel Watchdog Select 11 (Base+0x02DC) */
-        vuint32_t R; /*      (standard channels)                     */
-        struct {
-            vuint32_t WSEL_CH95:4;
-            vuint32_t WSEL_CH94:4;
-            vuint32_t WSEL_CH93:4;
-            vuint32_t WSEL_CH92:4;
-            vuint32_t WSEL_CH91:4;
-            vuint32_t WSEL_CH90:4;
-            vuint32_t WSEL_CH89:4;
-            vuint32_t WSEL_CH88:4;
-        } B;
-    } CWSELR11;
-    
-
-    union { /* ADC1 Channel Watchdog Enable0 (Base+0x02E0) */
-        vuint32_t R; /*      (precision channels)                    */
-        struct {
-            vuint32_t :16;
-            vuint32_t CWEN15:1;
-            vuint32_t CWEN14:1;
-            vuint32_t CWEN13:1;
-            vuint32_t CWEN12:1;
-            vuint32_t CWEN11:1;
-            vuint32_t CWEN10:1;
-            vuint32_t CWEN9:1;
-            vuint32_t CWEN8:1;
-            vuint32_t CWEN7:1;
-            vuint32_t CWEN6:1;
-            vuint32_t CWEN5:1;
-            vuint32_t CWEN4:1;
-            vuint32_t CWEN3:1;
-            vuint32_t CWEN2:1;
-            vuint32_t CWEN1:1;
-            vuint32_t CWEN0:1;
-        } B;
-    } CWENR0;
-
-    union { /* ADC1 Channel Watchdog Enable1  (Base++0x02E4) */
-        vuint32_t R; /*      (standard channels)                     */
-        struct {
-            vuint32_t :19;
-            vuint32_t CWEN44:1;
-            vuint32_t CWEN43:1;
-            vuint32_t CWEN42:1;
-            vuint32_t CWEN41:1;
-            vuint32_t CWEN40:1;
-            vuint32_t CWEN39:1;
-            vuint32_t CWEN38:1;
-            vuint32_t CWEN37:1;
-            vuint32_t CWEN36:1;
-            vuint32_t CWEN35:1;
-            vuint32_t CWEN34:1;
-            vuint32_t CWEN33:1;
-            vuint32_t CWEN32:1;
-        } B;
-    } CWENR1;
-    
-        union { /* ADC1 Channel Watchdog Enable2 (Base++0x02E8) */
-        vuint32_t R; /*      (External channels)                     */
-        struct {
-            vuint32_t CWEN95:1;
-            vuint32_t CWEN94:1;
-            vuint32_t CWEN93:1;
-            vuint32_t CWEN92:1;
-            vuint32_t CWEN91:1;
-            vuint32_t CWEN90:1;
-            vuint32_t CWEN89:1;
-            vuint32_t CWEN88:1;
-            vuint32_t CWEN87:1;
-            vuint32_t CWEN86:1;
-            vuint32_t CWEN85:1;
-            vuint32_t CWEN84:1;
-            vuint32_t CWEN83:1;
-            vuint32_t CWEN82:1;
-            vuint32_t CWEN81:1;
-            vuint32_t CWEN80:1;
-            vuint32_t CWEN79:1;
-            vuint32_t CWEN78:1;
-            vuint32_t CWEN77:1;
-            vuint32_t CWEN76:1;
-            vuint32_t CWEN75:1;
-            vuint32_t CWEN74:1;
-            vuint32_t CWEN73:1;
-            vuint32_t CWEN72:1;
-            vuint32_t CWEN71:1;
-            vuint32_t CWEN70:1;
-            vuint32_t CWEN69:1;
-            vuint32_t CWEN68:1;
-            vuint32_t CWEN67:1;
-            vuint32_t CWEN66:1;
-            vuint32_t CWEN65:1;
-            vuint32_t CWEN64:1;
-        } B;
-    } CWENR2;
-
-    vuint8_t ADC1_reserved14[4]; /* Reserved 4 bytes (Base+0x02EC-0x02F0) */
-
-    union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t AWORR_CH15:1;
-            vuint32_t AWORR_CH14:1;
-            vuint32_t AWORR_CH13:1;
-            vuint32_t AWORR_CH12:1;
-            vuint32_t AWORR_CH11:1;
-            vuint32_t AWORR_CH10:1;
-            vuint32_t AWORR_CH9:1;
-            vuint32_t AWORR_CH8:1;
-            vuint32_t AWORR_CH7:1;
-            vuint32_t AWORR_CH6:1;
-            vuint32_t AWORR_CH5:1;
-            vuint32_t AWORR_CH4:1;
-            vuint32_t AWORR_CH3:1;
-            vuint32_t AWORR_CH2:1;
-            vuint32_t AWORR_CH1:1;
-            vuint32_t AWORR_CH0:1;
-        } B;
-    } AWORR0;
-
-    union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */
-        vuint32_t R;
-        struct {
-            vuint32_t :19;
-            vuint32_t AWORR_CH44:1;
-            vuint32_t AWORR_CH43:1;
-            vuint32_t AWORR_CH42:1;
-            vuint32_t AWORR_CH41:1;
-            vuint32_t AWORR_CH40:1;
-            vuint32_t AWORR_CH39:1;
-            vuint32_t AWORR_CH38:1;
-            vuint32_t AWORR_CH37:1;
-            vuint32_t AWORR_CH36:1;
-            vuint32_t AWORR_CH35:1;
-            vuint32_t AWORR_CH34:1;
-            vuint32_t AWORR_CH33:1;
-            vuint32_t AWORR_CH32:1;
-        } B;
-    } AWORR1;
-    
-        union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */
-        vuint32_t R;
-        struct {
-            vuint32_t AWORR_CH95:1;
-            vuint32_t AWORR_CH94:1;
-            vuint32_t AWORR_CH93:1;
-            vuint32_t AWORR_CH92:1;
-            vuint32_t AWORR_CH91:1;
-            vuint32_t AWORR_CH90:1;
-            vuint32_t AWORR_CH89:1;
-            vuint32_t AWORR_CH88:1;
-            vuint32_t AWORR_CH87:1;
-            vuint32_t AWORR_CH86:1;
-            vuint32_t AWORR_CH85:1;
-            vuint32_t AWORR_CH84:1;
-            vuint32_t AWORR_CH83:1;
-            vuint32_t AWORR_CH82:1;
-            vuint32_t AWORR_CH81:1;
-            vuint32_t AWORR_CH80:1;
-            vuint32_t AWORR_CH79:1;
-            vuint32_t AWORR_CH78:1;
-            vuint32_t AWORR_CH77:1;
-            vuint32_t AWORR_CH76:1;
-            vuint32_t AWORR_CH75:1;
-            vuint32_t AWORR_CH74:1;
-            vuint32_t AWORR_CH73:1;
-            vuint32_t AWORR_CH72:1;
-            vuint32_t AWORR_CH71:1;
-            vuint32_t AWORR_CH70:1;
-            vuint32_t AWORR_CH69:1;
-            vuint32_t AWORR_CH68:1;
-            vuint32_t AWORR_CH67:1;
-            vuint32_t AWORR_CH66:1;
-            vuint32_t AWORR_CH65:1;
-            vuint32_t AWORR_CH64:1;
-        } B;
-    } AWORR2;
-
-    vuint8_t ADC1_reserved15[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */
-
-}; /* end of ADC1_tag */ 
-
-/****************************************************************************/
-/*              	MODULE : LINFLEX - non DMA master only                  */
-/****************************************************************************/
-struct LINFLEX_tag {
-
-    union { /* LINFLEX LIN Control 1 (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t CCD:1;
-            vuint32_t CFD:1;
-            vuint32_t LASE:1;
-            vuint32_t AWUM:1;
-            vuint32_t MBL:4;
-            vuint32_t BF:1;
-            vuint32_t SFTM:1;
-            vuint32_t LBKM:1;
-            vuint32_t MME:1;
-            vuint32_t SBDT:1;
-            vuint32_t RBLM:1;
-            vuint32_t SLEEP:1;
-            vuint32_t INIT:1;
-        } B;
-    } LINCR1;
-
-    union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t SZIE:1;
-            vuint32_t OCIE:1;
-            vuint32_t BEIE:1;
-            vuint32_t CEIE:1;
-            vuint32_t HEIE:1;
-            vuint32_t :2;
-            vuint32_t FEIE:1;
-            vuint32_t BOIE:1;
-            vuint32_t LSIE:1;
-            vuint32_t WUIE:1;
-            vuint32_t DBFIE:1;
-            vuint32_t DBEIE:1;
-            vuint32_t DRIE:1;
-            vuint32_t DTIE:1;
-            vuint32_t HRIE:1;
-        } B;
-    } LINIER;
-
-    union { /* LINFLEX LIN Status (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t LINS:4;
-            vuint32_t:2;
-            vuint32_t RMB:1;
-            vuint32_t:1;
-            vuint32_t RBSY:1;
-            vuint32_t RPS:1;
-            vuint32_t WUF:1;
-            vuint32_t DBFF:1;
-            vuint32_t DBEF:1;
-            vuint32_t DRF:1;
-            vuint32_t DTF:1;
-            vuint32_t HRF:1;
-        } B;
-    } LINSR;
-
-    union { /* LINFLEX LIN Error Status (Base+0x000C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t SZF:1;
-            vuint32_t OCF:1;
-            vuint32_t BEF:1;
-            vuint32_t CEF:1;
-            vuint32_t SFEF:1;
-            vuint32_t BDEF:1;
-            vuint32_t IDPEF:1;
-            vuint32_t FEF:1;
-            vuint32_t BOF:1;
-            vuint32_t:6;
-            vuint32_t NF:1;
-        } B;
-    } LINESR;
-
-    union { /* LINFLEX UART Mode Control (Base+0x0010) */
-        vuint32_t R;
-        struct {
-			vuint32_t :16;
-            vuint32_t:1;
-            vuint32_t TDFL:2;
-            vuint32_t:1;
-            vuint32_t RDFL:2;
-            vuint32_t:4;
-            vuint32_t RXEN:1;
-            vuint32_t TXEN:1;
-            vuint32_t OP:1;
-            vuint32_t PCE:1;
-            vuint32_t WL:1;
-            vuint32_t UART:1;       
-		} B;
-    } UARTCR;
-
-    union { /* LINFLEX UART Mode Status (Base+0x0014) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t SZF:1;
-            vuint32_t OCF:1;
-            vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
-            vuint32_t RMB:1;
-            vuint32_t FEF:1;
-            vuint32_t BOF:1;
-            vuint32_t RPS:1;
-            vuint32_t WUF:1;
-			vuint32_t :1;
-            vuint32_t TO:1;
-            vuint32_t DRF:1;
-            vuint32_t DTF:1;
-            vuint32_t NF:1;
-        } B;
-    } UARTSR;
-
-    union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t:5;
-            vuint32_t LTOM:1;
-            vuint32_t IOT:1;
-            vuint32_t TOCE:1;
-            vuint32_t CNT:8;
-        } B;
-    } LINTCSR;
-
-    union { /* LINFLEX LIN Output Compare (Base+0x001C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t OC2:8;
-            vuint32_t OC1:8;
-        } B;
-    } LINOCR;
-
-    union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
-        vuint32_t R;
-        struct {
-            vuint32_t :20;
-            vuint32_t RTO:4;
-            vuint32_t:1;
-            vuint32_t HTO:7;
-        } B;
-    } LINTOCR;
-
-    union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
-        vuint32_t R;
-        struct {
-            vuint32_t:28;
-            vuint32_t DIV_F:4;
-        } B;
-    } LINFBRR;
-
-    union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
-        vuint32_t R;
-        struct {
-            vuint32_t:12;
-            vuint32_t DIV_M:20;
-        } B;
-    } LINIBRR;
-
-    union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
-        vuint32_t R;
-        struct {
-            vuint32_t:24;
-            vuint32_t CF:8;
-        } B;
-    } LINCFR;
-
-    union { /* LINFLEX LIN Control 2 (Base+0x0030) */
-        vuint32_t R;
-        struct {
-            vuint32_t:17;
-            vuint32_t IOBE:1;
-            vuint32_t IOPE:1;
-            vuint32_t WURQ:1;
-            vuint32_t DDRQ:1;
-            vuint32_t DTRQ:1;
-            vuint32_t ABRQ:1;
-            vuint32_t HTRQ:1;
-            vuint32_t:8;
-        } B;
-    } LINCR2;
-
-    union { /* LINFLEX Buffer Identifier (Base+0x0034) */
-        vuint32_t R;
-        struct {
-            vuint32_t:16;
-            vuint32_t DFL:6;
-            vuint32_t DIR:1;
-            vuint32_t CCS:1;
-            vuint32_t:2;
-            vuint32_t ID:6;
-        } B;
-    } BIDR;
-
-    union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
-        vuint32_t R;
-        struct {
-            vuint32_t DATA3:8;
-            vuint32_t DATA2:8;
-            vuint32_t DATA1:8;
-            vuint32_t DATA0:8;
-        } B;
-    } BDRL;
-
-    union { /* LINFLEX Buffer Data MSB (Base+0x003C */
-        vuint32_t R;
-        struct {
-            vuint32_t DATA7:8;
-            vuint32_t DATA6:8;
-            vuint32_t DATA5:8;
-            vuint32_t DATA4:8;
-        } B;
-    } BDRM;
-
-    union { /* LINFLEX Identifier Filter Enable (+0x0040) */
-        vuint32_t R;
-        struct {
-            vuint32_t:24;
-            vuint32_t FACT:8;
-        } B;
-    } IFER;
-
-    union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
-        vuint32_t R;
-        struct {
-            vuint32_t:28;
-            vuint32_t IFMI:4;
-        } B;
-    } IFMI;
-
-    union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
-        vuint32_t R;
-        struct {
-            vuint32_t:27;
-            vuint32_t IFM:5;
-        } B;
-    } IFMR;
-
-    union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
-        vuint32_t R;
-        struct {
-            vuint32_t:16;
-            vuint32_t:3; 	 /* for LINflexD no reseve here*/
-            vuint32_t DFL:3; /* Linflex D - this field is 6 bits (0 and 1), Linflex - this field is 3 bits (2-9 B1.5M) (2-7 B1M) */ 
-            vuint32_t DIR:1;
-            vuint32_t CCS:1;
-            vuint32_t:2;
-            vuint32_t ID:6;
-        } B;
-    } IFCR[16];
-
-  
-}; /* end of LINFLEX_tag */
-
-
-/****************************************************************************/
-/*                MODULE : LINFLEXD0 Master/Slave DMA Enabled     			*/
-/****************************************************************************/
-struct LINFLEXD0_tag {
-
-    union { /* LINFLEX LIN Control 1 (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t CCD:1;
-            vuint32_t CFD:1;
-            vuint32_t LASE:1;
-            vuint32_t AWUM:1;
-            vuint32_t MBL:4;
-            vuint32_t BF:1;
-            vuint32_t SFTM:1;
-            vuint32_t LBKM:1;
-            vuint32_t MME:1;
-            vuint32_t SBDT:1;
-            vuint32_t RBLM:1;
-            vuint32_t SLEEP:1;
-            vuint32_t INIT:1;
-        } B;
-    } LINCR1;
-
-    union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t SZIE:1;
-            vuint32_t OCIE:1;
-            vuint32_t BEIE:1;
-            vuint32_t CEIE:1;
-            vuint32_t HEIE:1;
-            vuint32_t :2;
-            vuint32_t FEIE:1;
-            vuint32_t BOIE:1;
-            vuint32_t LSIE:1;
-            vuint32_t WUIE:1;
-            vuint32_t DBFIE:1;
-            vuint32_t DBEIE:1;
-            vuint32_t DRIE:1;
-            vuint32_t DTIE:1;
-            vuint32_t HRIE:1;
-        } B;
-    } LINIER;
-
-    union { /* LINFLEX LIN Status (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t LINS:4;
-            vuint32_t:2;
-            vuint32_t RMB:1;
-            vuint32_t:1;
-            vuint32_t RBSY:1;
-            vuint32_t RPS:1;
-            vuint32_t WUF:1;
-            vuint32_t DBFF:1;
-            vuint32_t DBEF:1;
-            vuint32_t DRF:1;
-            vuint32_t DTF:1;
-            vuint32_t HRF:1;
-        } B;
-    } LINSR;
-
-    union { /* LINFLEX LIN Error Status (Base+0x000C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t SZF:1;
-            vuint32_t OCF:1;
-            vuint32_t BEF:1;
-            vuint32_t CEF:1;
-            vuint32_t SFEF:1;
-            vuint32_t BDEF:1;
-            vuint32_t IDPEF:1;
-            vuint32_t FEF:1;
-            vuint32_t BOF:1;
-            vuint32_t:6;
-            vuint32_t NF:1;
-        } B;
-    } LINESR;
-
-    union { /* LINFLEX UART Mode Control (Base+0x0010) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t TDFLTFC:3;
-            vuint32_t RDFLTFC:3;
-            vuint32_t RFBM:1;
-			vuint32_t TFBM:1;
-			vuint32_t WL1:1;
-			vuint32_t PC1:1;
-            vuint32_t RXEN:1;
-            vuint32_t TXEN:1;
-            vuint32_t PC0:1;
-            vuint32_t PCE:1;
-            vuint32_t WL0:1;
-            vuint32_t UART:1;
-        } B;
-    } UARTCR;
-
-    union { /* LINFLEX UART Mode Status (Base+0x0014) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t SZF:1;
-            vuint32_t OCF:1;
-            vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
-            vuint32_t RMB:1;
-            vuint32_t FEF:1;
-            vuint32_t BOF:1;
-            vuint32_t RPS:1;
-            vuint32_t WUF:1;
-			vuint32_t :1;
-            vuint32_t TO:1;
-            vuint32_t DRF:1;
-            vuint32_t DTF:1;
-            vuint32_t NF:1;
-        } B;
-    } UARTSR;
-
-    union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t:5;
-            vuint32_t LTOM:1;
-            vuint32_t IOT:1;
-            vuint32_t TOCE:1;
-            vuint32_t CNT:8;
-        } B;
-    } LINTCSR;
-
-    union { /* LINFLEX LIN Output Compare (Base+0x001C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t OC2:8;
-            vuint32_t OC1:8;
-        } B;
-    } LINOCR;
-
-    union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
-        vuint32_t R;
-        struct {
-            vuint32_t :20;
-            vuint32_t RTO:4;
-            vuint32_t:1;
-            vuint32_t HTO:7;
-        } B;
-    } LINTOCR;
-
-    union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
-        vuint32_t R;
-        struct {
-            vuint32_t:28;
-            vuint32_t DIV_F:4;
-        } B;
-    } LINFBRR;
-
-    union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
-        vuint32_t R;
-        struct {
-            vuint32_t:12;
-            vuint32_t DIV_M:20;
-        } B;
-    } LINIBRR;
-
-    union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
-        vuint32_t R;
-        struct {
-            vuint32_t:24;
-            vuint32_t CF:8;
-        } B;
-    } LINCFR;
-
-    union { /* LINFLEX LIN Control 2 (Base+0x0030) */
-        vuint32_t R;
-        struct {
-            vuint32_t:17;
-            vuint32_t IOBE:1;
-            vuint32_t IOPE:1;
-            vuint32_t WURQ:1;
-            vuint32_t DDRQ:1;
-            vuint32_t DTRQ:1;
-            vuint32_t ABRQ:1;
-            vuint32_t HTRQ:1;
-            vuint32_t:8;
-        } B;
-    } LINCR2;
-
-    union { /* LINFLEX Buffer Identifier (Base+0x0034) */
-        vuint32_t R;
-        struct {
-            vuint32_t:16;
-            vuint32_t DFL:6;
-            vuint32_t DIR:1;
-            vuint32_t CCS:1;
-            vuint32_t:2;
-            vuint32_t ID:6;
-        } B;
-    } BIDR;
-
-    union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
-        vuint32_t R;
-        struct {
-            vuint32_t DATA3:8;
-            vuint32_t DATA2:8;
-            vuint32_t DATA1:8;
-            vuint32_t DATA0:8;
-        } B;
-    } BDRL;
-
-    union { /* LINFLEX Buffer Data MSB (Base+0x003C */
-        vuint32_t R;
-        struct {
-            vuint32_t DATA7:8;
-            vuint32_t DATA6:8;
-            vuint32_t DATA5:8;
-            vuint32_t DATA4:8;
-        } B;
-    } BDRM;
-
-    union { /* LINFLEX Identifier Filter Enable (+0x0040) */
-        vuint32_t R;
-        struct {
-            vuint32_t:24;
-            vuint32_t FACT:8;
-        } B;
-    } IFER;
-
-    union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
-        vuint32_t R;
-        struct {
-            vuint32_t:27;
-            vuint32_t IFMI:5;
-        } B;
-    } IFMI;
-
-    union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
-        vuint32_t R;
-        struct {
-            vuint32_t:24;
-            vuint32_t IFM:8;
-        } B;
-    } IFMR;
-
-    union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
-        vuint32_t R;
-        struct {
-            vuint32_t:16;
-            vuint32_t DFL:6;
-            vuint32_t DIR:1;
-            vuint32_t CCS:1;
-            vuint32_t:2;
-            vuint32_t ID:6;
-        } B;
-    } IFCR[16];
-
-    union { /* LINFLEX Global Counter (+0x008C) */
-        vuint32_t R;
-        struct {
-            vuint32_t:26;
-            vuint32_t TDFBM:1;
-            vuint32_t RDFBM:1;
-            vuint32_t TDLIS:1;
-            vuint32_t RDLIS:1;
-            vuint32_t STOP:1;
-            vuint32_t SR:1;
-        } B;
-    } GCR;
-
-    union { /* LINFLEX UART preset timeout (+0x0090) */
-        vuint32_t R;
-        struct {
-            vuint32_t:20;
-            vuint32_t PTO:12;
-        } B;
-    } UARTPTO;
-
-    union { /* LINFLEX UART current timeout (+0x0094) */
-        vuint32_t R;
-        struct {
-            vuint32_t:20;
-            vuint32_t CTO:12;
-        } B;
-    } UARTCTO;
-
-    union { /* LINFLEX DMA Tx Enable (+0x0098) */
-        vuint32_t R;
-        struct {
-            vuint32_t:16;
-            vuint32_t DTE15:1;
-            vuint32_t DTE14:1;
-            vuint32_t DTE13:1;
-            vuint32_t DTE12:1;
-            vuint32_t DTE11:1;
-            vuint32_t DTE10:1;
-            vuint32_t DTE9:1;
-            vuint32_t DTE8:1;
-            vuint32_t DTE7:1;
-            vuint32_t DTE6:1;
-            vuint32_t DTE5:1;
-            vuint32_t DTE4:1;
-            vuint32_t DTE3:1;
-            vuint32_t DTE2:1;
-            vuint32_t DTE1:1;
-            vuint32_t DTE0:1;
-        } B;
-    } DMATXE;
-
-    union { /* LINFLEX DMA RX Enable (+0x009C) */
-        vuint32_t R;
-        struct {
-            vuint32_t:16;
-            vuint32_t DRE15:1;
-            vuint32_t DRE14:1;
-            vuint32_t DRE13:1;
-            vuint32_t DRE12:1;
-            vuint32_t DRE11:1;
-            vuint32_t DRE10:1;
-            vuint32_t DRE9:1;
-            vuint32_t DRE8:1;
-            vuint32_t DRE7:1;
-            vuint32_t DRE6:1;
-            vuint32_t DRE5:1;
-            vuint32_t DRE4:1;
-            vuint32_t DRE3:1;
-            vuint32_t DRE2:1;
-            vuint32_t DRE1:1;
-            vuint32_t DRE0:1;
-        } B;
-    } DMARXE;
-}; /* end of LINFLEXD0_tag */
-/****************************************************************************/
-/*                MODULE : LINFLEXD1 Master only DMA enable       			*/
-/****************************************************************************/
-struct LINFLEXD1_tag {
-
-    union { /* LINFLEX LIN Control 1 (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t CCD:1;
-            vuint32_t CFD:1;
-            vuint32_t LASE:1;
-            vuint32_t AWUM:1;
-            vuint32_t MBL:4;
-            vuint32_t BF:1;
-            vuint32_t SFTM:1;
-            vuint32_t LBKM:1;
-            vuint32_t MME:1;
-            vuint32_t SBDT:1;
-            vuint32_t RBLM:1;
-            vuint32_t SLEEP:1;
-            vuint32_t INIT:1;
-        } B;
-    } LINCR1;
-
-    union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t SZIE:1;
-            vuint32_t OCIE:1;
-            vuint32_t BEIE:1;
-            vuint32_t CEIE:1;
-            vuint32_t HEIE:1;
-            vuint32_t :2;
-            vuint32_t FEIE:1;
-            vuint32_t BOIE:1;
-            vuint32_t LSIE:1;
-            vuint32_t WUIE:1;
-            vuint32_t DBFIE:1;
-            vuint32_t DBEIE:1;
-            vuint32_t DRIE:1;
-            vuint32_t DTIE:1;
-            vuint32_t HRIE:1;
-        } B;
-    } LINIER;
-
-    union { /* LINFLEX LIN Status (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t LINS:4;
-            vuint32_t:2;
-            vuint32_t RMB:1;
-            vuint32_t:1;
-            vuint32_t RBSY:1;
-            vuint32_t RPS:1;
-            vuint32_t WUF:1;
-            vuint32_t DBFF:1;
-            vuint32_t DBEF:1;
-            vuint32_t DRF:1;
-            vuint32_t DTF:1;
-            vuint32_t HRF:1;
-        } B;
-    } LINSR;
-
-    union { /* LINFLEX LIN Error Status (Base+0x000C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t SZF:1;
-            vuint32_t OCF:1;
-            vuint32_t BEF:1;
-            vuint32_t CEF:1;
-            vuint32_t SFEF:1;
-            vuint32_t BDEF:1;
-            vuint32_t IDPEF:1;
-            vuint32_t FEF:1;
-            vuint32_t BOF:1;
-            vuint32_t:6;
-            vuint32_t NF:1;
-        } B;
-    } LINESR;
-
-    union { /* LINFLEX UART Mode Control (Base+0x0010) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t TDFLTFC:3;
-            vuint32_t RDFLTFC:3;
-            vuint32_t RFBM:1;
-			vuint32_t TFBM:1;
-			vuint32_t WL1:1;
-			vuint32_t PC1:1;
-            vuint32_t RXEN:1;
-            vuint32_t TXEN:1;
-            vuint32_t PC0:1;
-            vuint32_t PCE:1;
-            vuint32_t WL0:1;
-            vuint32_t UART:1;
-        } B;
-    } UARTCR;
-
-    union { /* LINFLEX UART Mode Status (Base+0x0014) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t SZF:1;
-            vuint32_t OCF:1;
-            vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
-            vuint32_t RMB:1;
-            vuint32_t FEF:1;
-            vuint32_t BOF:1;
-            vuint32_t RPS:1;
-            vuint32_t WUF:1;
-            vuint32_t:2;
-            vuint32_t DRF:1;
-            vuint32_t DTF:1;
-            vuint32_t NF:1;
-        } B;
-    } UARTSR;
-
-    union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t:5;
-            vuint32_t LTOM:1;
-            vuint32_t IOT:1;
-            vuint32_t TOCE:1;
-            vuint32_t CNT:8;
-        } B;
-    } LINTCSR;
-
-    union { /* LINFLEX LIN Output Compare (Base+0x001C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t OC2:8;
-            vuint32_t OC1:8;
-        } B;
-    } LINOCR;
-
-    union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
-        vuint32_t R;
-        struct {
-            vuint32_t :20;
-            vuint32_t RTO:4;
-            vuint32_t:1;
-            vuint32_t HTO:7;
-        } B;
-    } LINTOCR;
-
-    union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
-        vuint32_t R;
-        struct {
-            vuint32_t:28;
-            vuint32_t DIV_F:4;
-        } B;
-    } LINFBRR;
-
-    union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
-        vuint32_t R;
-        struct {
-            vuint32_t:12;
-            vuint32_t DIV_M:20;
-        } B;
-    } LINIBRR;
-
-    union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
-        vuint32_t R;
-        struct {
-            vuint32_t:24;
-            vuint32_t CF:8;
-        } B;
-    } LINCFR;
-
-    union { /* LINFLEX LIN Control 2 (Base+0x0030) */
-        vuint32_t R;
-        struct {
-            vuint32_t:17;
-            vuint32_t IOBE:1;
-            vuint32_t IOPE:1;
-            vuint32_t WURQ:1;
-            vuint32_t DDRQ:1;
-            vuint32_t DTRQ:1;
-            vuint32_t ABRQ:1;
-            vuint32_t HTRQ:1;
-            vuint32_t:8;
-        } B;
-    } LINCR2;
-
-    union { /* LINFLEX Buffer Identifier (Base+0x0034) */
-        vuint32_t R;
-        struct {
-            vuint32_t:16;
-            vuint32_t DFL:6;
-            vuint32_t DIR:1;
-            vuint32_t CCS:1;
-            vuint32_t:2;
-            vuint32_t ID:6;
-        } B;
-    } BIDR;
-
-    union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
-        vuint32_t R;
-        struct {
-            vuint32_t DATA3:8;
-            vuint32_t DATA2:8;
-            vuint32_t DATA1:8;
-            vuint32_t DATA0:8;
-        } B;
-    } BDRL;
-
-    union { /* LINFLEX Buffer Data MSB (Base+0x003C */
-        vuint32_t R;
-        struct {
-            vuint32_t DATA7:8;
-            vuint32_t DATA6:8;
-            vuint32_t DATA5:8;
-            vuint32_t DATA4:8;
-        } B;
-    } BDRM;
-
-    union { /* LINFLEX Identifier Filter Enable (+0x0040) */
-        vuint32_t R;
-        struct {
-            vuint32_t:24;
-            vuint32_t FACT:8;
-        } B;
-    } IFER;
-
-    union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
-        vuint32_t R;
-        struct {
-            vuint32_t:27;
-            vuint32_t IFMI:5;
-        } B;
-    } IFMI;
-
-    union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
-        vuint32_t R;
-        struct {
-            vuint32_t:24;
-            vuint32_t IFM:8;
-        } B;
-    } IFMR;
-
-/* No IFCR registers on LinFlexD_1 */
-
-    union { /* LINFLEX Global Counter (+0x004C) */
-        vuint32_t R;
-        struct {
-            vuint32_t:26;
-            vuint32_t TDFBM:1;
-            vuint32_t RDFBM:1;
-            vuint32_t TDLIS:1;
-            vuint32_t RDLIS:1;
-            vuint32_t STOP:1;
-            vuint32_t SR:1;
-        } B;
-    } GCR;
-
-    union { /* LINFLEX UART preset timeout (+0x0050) */
-        vuint32_t R;
-        struct {
-            vuint32_t:20;
-            vuint32_t PTO:12;
-        } B;
-    } UARTPTO;
-
-    union { /* LINFLEX UART current timeout (+0x0054) */
-        vuint32_t R;
-        struct {
-            vuint32_t:20;
-            vuint32_t CTO:12;
-        } B;
-    } UARTCTO;
-
-    union { /* LINFLEX DMA Tx Enable (+0x0058) */
-        vuint32_t R;
-        struct {
-            vuint32_t:16;
-            vuint32_t DTE15:1;
-            vuint32_t DTE14:1;
-            vuint32_t DTE13:1;
-            vuint32_t DTE12:1;
-            vuint32_t DTE11:1;
-            vuint32_t DTE10:1;
-            vuint32_t DTE9:1;
-            vuint32_t DTE8:1;
-            vuint32_t DTE7:1;
-            vuint32_t DTE6:1;
-            vuint32_t DTE5:1;
-            vuint32_t DTE4:1;
-            vuint32_t DTE3:1;
-            vuint32_t DTE2:1;
-            vuint32_t DTE1:1;
-            vuint32_t DTE0:1;
-        } B;
-    } DMATXE;
-
-    union { /* LINFLEX DMA RX Enable (+0x005C) */
-        vuint32_t R;
-        struct {
-            vuint32_t:16;
-            vuint32_t DRE15:1;
-            vuint32_t DRE14:1;
-            vuint32_t DRE13:1;
-            vuint32_t DRE12:1;
-            vuint32_t DRE11:1;
-            vuint32_t DRE10:1;
-            vuint32_t DRE9:1;
-            vuint32_t DRE8:1;
-            vuint32_t DRE7:1;
-            vuint32_t DRE6:1;
-            vuint32_t DRE5:1;
-            vuint32_t DRE4:1;
-            vuint32_t DRE3:1;
-            vuint32_t DRE2:1;
-            vuint32_t DRE1:1;
-            vuint32_t DRE0:1;
-        } B;
-    } DMARXE;
-}; /* end of LINFLEXD1_tag */
-   /****************************************************************************/
-/*                          MODULE : CTU Lite(base address - 0xFFE6_4000)   */
-/****************************************************************************/
-struct CTU_tag{
-
-    vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */
-
-    union { /* Event Config 0..63 (Base+0x0030-0x012C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t TM:1;
-            vuint32_t CLR_FLAG:1;
-            vuint32_t :5;
-            vuint32_t ADC_SEL:1;
-            vuint32_t :1;
-            vuint32_t CHANNEL_VALUE:7;
-        } B;
-    } EVTCFGR[64];
-
-
-}; /* end of CTU_tag */
-
-
-/****************************************************************************/
-/*                          MODULE : MPU (base address - 0xFFF1_0000)       */
-/****************************************************************************/
- struct MPU_tag {
-
-    union { /* Control/Error Status (Base+0x0000) */
-        vuint32_t R;
-        struct {
-			vuint32_t SPERR:3;
-			vuint32_t:9;
-			vuint32_t HRL:4;
-			vuint32_t NSP:4;
-			vuint32_t NGRD:4;
-			vuint32_t :7;
-			vuint32_t VLD:1;
-        } B;
-    } CESR;
-
-    vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */
-
-
-   union { /* Error Address Slave Port0 (Base+0x0010) */
-        vuint32_t R;
-        struct {
-            vuint32_t EADDR:32;
-        } B;
-    } EAR0;
-
-    union { /* Error Detail Slave Port0 (Base+0x0014) */
-        vuint32_t R;
-        struct {
-			vuint32_t EACD:8;
-			vuint32_t:8;
-            vuint32_t EPID:8;
-            vuint32_t EMN:4;
-            vuint32_t EATTR:3;
-            vuint32_t ERW:1;
-        } B;
-    } EDR0;
-
-
-    union { /* Error Address Slave Port1 (Base+0x0018) */
-        vuint32_t R;
-        struct {
-            vuint32_t EADDR:32;
-        } B;
-    } EAR1;
-
-    union { /* Error Detail Slave Port1 (Base+0x001C) */
-        vuint32_t R;
-        struct {
-			vuint32_t EACD:8;
-			vuint32_t:8;
-            vuint32_t EPID:8;
-            vuint32_t EMN:4;
-            vuint32_t EATTR:3;
-            vuint32_t ERW:1;
-        } B;
-    } EDR1;
-
-
-    union { /* Error Address Slave Port2 (Base+0x0020) */
-        vuint32_t R;
-        struct {
-            vuint32_t EADDR:32;
-        } B;
-    } EAR2;
-
-    union { /* Error Detail Slave Port2 (Base+0x0024) */
-        vuint32_t R;
-        struct {
-			vuint32_t EACD:8;
-			vuint32_t:8;
-            vuint32_t EPID:8;
-            vuint32_t EMN:4;
-            vuint32_t EATTR:3;
-            vuint32_t ERW:1;
-        } B;
-    } EDR2;
-
-    vuint8_t MPU_reserved1[984]; /* Reserved 984 Bytes (Base+0x0028-0x03FF) */
-
-    struct { /* Region Descriptor 0..15 (Base+0x0400-0x0470) */
-
-        union { /* - Word 0 */
-            vuint32_t R;
-            struct {
-                vuint32_t SRTADDR:27;
-                vuint32_t :5;
-            } B;
-        } WORD0;
-
-        union { /* - Word 1 */
-            vuint32_t R;
-            struct {
-                vuint32_t ENDADDR:27;
-                vuint32_t :5;
-            } B;
-        } WORD1;
-
-       union { /* - Word 2 */
-            vuint32_t R;
-            struct {
-                vuint32_t M7RE:1;
-                vuint32_t M7WE:1;
-                vuint32_t M6RE:1;
-                vuint32_t M6WE:1;
-                vuint32_t M5RE:1;
-                vuint32_t M5WE:1;
-                vuint32_t M4RE:1;
-                vuint32_t M4WE:1;
-                vuint32_t M3PE:1;
-                vuint32_t M3SM:2;
-                vuint32_t M3UM:3;
-                vuint32_t M2PE:1;
-                vuint32_t M2SM:2;
-                vuint32_t M2UM:2;
-				vuint32_t :7;     
-                vuint32_t M0PE:1;
-                vuint32_t M0SM:2;
-                vuint32_t M0UM:3;
-            } B;
-        } WORD2;
-
-        union { /* - Word 3 */
-            vuint32_t R;
-            struct {
-                vuint32_t PID:8;
-                vuint32_t PIDMASK:8;
-                vuint32_t :15;
-                vuint32_t VLD:1;
-            } B;
-        } WORD3;
-
-    }RGD[8]; /* End of Region Descriptor Structure) */
-
-    vuint8_t MPU_reserved2[896]; /* Reserved 896 Bytes (Base+0x0480-0x07FF) */
-
-    union { /* Region Descriptor Alt 0..15 (0x0800-0x081C) */
-        vuint32_t R;
-        struct {
-			vuint32_t M7RE:1;
-			vuint32_t M7WE:1;
-			vuint32_t M6RE:1;
-			vuint32_t M6WE:1;
-			vuint32_t M5RE:1;
-			vuint32_t M5WE:1;
-			vuint32_t M4RE:1;
-			vuint32_t M4WE:1;
-			vuint32_t M3PE:1;
-			vuint32_t M3SM:2;
-			vuint32_t M3UM:3;
-			vuint32_t M2PE:1;
-			vuint32_t M2SM:2;
-			vuint32_t M2UM:2;
-			vuint32_t :7;     
-			vuint32_t M0PE:1;
-			vuint32_t M0SM:2;
-			vuint32_t M0UM:3;
-        } B;
-    } RGDAAC[8];
-
-    vuint8_t MPU_reserved3[14304]; /* Reserved 14304 Bytes (+0x0820-0x03FFF) */
-
-}; /* end of MPU_tag */ 
-
-/****************************************************************************/
-/*                          MODULE : SWT                                   */
-/****************************************************************************/
-struct SWT_tag{
-
-    union { /* SWT Control (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t MAP0:1;
-            vuint32_t MAP1:1;
-            vuint32_t MAP2:1;
-            vuint32_t MAP3:1;
-            vuint32_t MAP4:1;
-            vuint32_t MAP5:1;
-            vuint32_t MAP6:1;
-            vuint32_t MAP7:1;
-            vuint32_t :14;
-            vuint32_t KEY:1;
-            vuint32_t RIA:1;
-            vuint32_t WND:1;
-            vuint32_t ITR:1;
-            vuint32_t HLK:1;
-            vuint32_t SLK:1;
-            vuint32_t CSL:1;
-            vuint32_t STP:1;
-            vuint32_t FRZ:1;
-            vuint32_t WEN:1;
-        } B;
-    } CR;
-
-    union { /* SWT Interrupt (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t :31;
-            vuint32_t TIF:1;
-        } B;
-    } IR;
-
-    union { /* SWT Time-Out (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t WTO:32;
-        } B;
-    } TO;
-
-    union { /* SWT Window (Base+0x000C) */
-        vuint32_t R;
-        struct {
-            vuint32_t WST:32;
-        } B;
-    } WN;
-
-    union { /* SWT Service (Base+0x0010) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t WSC:16;
-        } B;
-    } SR;
-
-    union { /* SWT Counter Output (Base+0x0014) */
-        vuint32_t R;
-        struct {
-            vuint32_t CNT:32;
-        } B;
-    } CO;
-
-}; /* end of SWT_tag */   
-	   
-/****************************************************************************/
-/*                          MODULE : STM                                   */
-/****************************************************************************/
-  struct STM_CHANNEL_tag{
-
-    union { /* STM Channel Control 0..3 */
-        vuint32_t R;
-        struct {
-            vuint32_t :31;
-            vuint32_t CEN:1;
-        } B;
-    } CCR;
-
-    union { /* STM Channel Interrupt 0..3 */
-        vuint32_t R;
-        struct {
-            vuint32_t :31;
-            vuint32_t CIF:1;
-        } B;
-    } CIR;
-
-    union { /* STM Channel Compare 0..3 */
-        vuint32_t R;
-        struct {
-            vuint32_t CMP:32;
-        } B;
-    } CMP;
-
-    vuint8_t STM_CHANNEL_reserved0[4]; /* Reserved 4 bytes between ch reg's */
-
-  }; /* end of STM_CHANNEL_tag */
-
-
-struct STM_tag{
-
-    union { /* STM Control (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t CPS:8;
-            vuint32_t :6;
-            vuint32_t FRZ:1;
-            vuint32_t TEN:1;
-        } B;
-    } CR;
-
-    union { /* STM Count (Base+0x0004) */
-        vuint32_t R;
-    } CNT;
-
-    vuint8_t STM_reserved1[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
-
-    struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */
-
-}; /* end of STM_tag */
-
-/****************************************************************************/
-/*                          MODULE : ECSM                                   */
-/****************************************************************************/
-struct ECSM_tag{
-
-    union { /* ECSM Processor Core Type (Base+0x0000) */
-        vuint16_t R;
-    } PCT;
-
-    union { /* ECSM Revision (Base+0x0002) */
-        vuint16_t R;
-    } REV;
-
-    vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
-
-    union { /* ECSM IPS Module Configuration (Base+0x0008) */
-        vuint32_t R;
-    } IMC;
-
-    vuint8_t ECSM_reserved1[7]; /* Reserved 7 bytes (Base+0x000C-0x0012) */
-
-    union { /* ECSM Miscellaneous Wakeup Control (+0x0013) */
-        vuint8_t R;
-        struct {
-            vuint8_t ENBWCR:1;
-            vuint8_t :3;
-            vuint8_t PRILVL:4;
-        } B;
-    } MWCR;
-
-    vuint8_t ECSM_reserved2[11]; /* Reserved 11 bytes (Base+0x0014-0x001E) */
-
-    union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */
-        vuint8_t R;
-        struct {
-            vuint8_t FB0AI:1;
-            vuint8_t FB0SI:1;
-            vuint8_t FB1AI:1;
-            vuint8_t FB1SI:1;
-            vuint8_t :4;
-        } B;
-    } MIR;
-
-    vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */
-
-    union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/
-            vuint32_t R;
-          } MUDCR;                /* ECSM Miscellaneous User-Defined Control Register */
-
-    vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */
-
-    union { /* ECSM ECC Configuration (Base+0x0043) */
-        vuint8_t R;
-        struct {
-            vuint8_t :2;
-            vuint8_t ER1BR:1;
-            vuint8_t EF1BR:1;
-            vuint8_t :2;
-            vuint8_t ERNCR:1;
-            vuint8_t EFNCR:1;
-        } B;
-    } ECR;
-
-    vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */
-
-    union { /* ECSM ECC Status (Base+0x0047) */
-        vuint8_t R;
-        struct {
-            vuint8_t :2;
-            vuint8_t R1BC:1;
-            vuint8_t F1BC:1;
-            vuint8_t :2;
-            vuint8_t RNCE:1;
-            vuint8_t FNCE:1;
-        } B;
-    } ESR;
-
-    vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */
-
-    union { /* ECSM ECC Error Generation (Base+0x004A) */
-        vuint16_t R;
-        struct {
-            vuint16_t :2;
-            vuint16_t FRC1BI:1;
-            vuint16_t FR11BI:1;
-            vuint16_t :2;
-            vuint16_t FRCNCI:1;
-            vuint16_t FR1NCI:1;
-            vuint16_t :1;
-            vuint16_t ERRBIT:7;
-        } B;
-    } EEGR;
-
-    vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */
-
-    union { /* ECSM Flash ECC Address(Base+0x0050) */
-        vuint32_t R;
-    } FEAR;
-
-    vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */
-
-    union { /* ECSM Flash ECC Master Number (Base+0x0056) */
-        vuint8_t R;
-        struct {
-            vuint8_t :4;
-            vuint8_t FEMR:4;
-        } B;
-    } FEMR;
-
-    union { /* ECSM Flash ECC Attributes (Base+0x0057) */
-        vuint8_t R;
-        struct {
-            vuint8_t WRITE:1;
-			vuint8_t SIZE:3;
-            vuint8_t PROTECTION:4;
-        } B;
-    } FEAT;
-
-    vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */
-
-    union { /* ECSM Flash ECC Data (Base+0x005C) */
-        vuint32_t R;
-    } FEDR;
-
-    union { /* ECSM RAM ECC Address (Base+0x0060) */
-        vuint32_t R;
-    } REAR;
-
-    vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */
-
-    union { /* ECSM RAM ECC Address (Base+0x0065) */
-        vuint8_t R;
-    } RESR;
-
-    union { /* ECSM RAM ECC Master Number (Base+0x0066) */
-        vuint8_t R;
-        struct {
-            vuint8_t :4;
-            vuint8_t REMR:4;
-        } B;
-    } REMR;
-
-    union { /* ECSM RAM ECC Attributes (Base+0x0067) */
-        vuint8_t R;
-        struct {
-            vuint8_t WRITE:1;
-            vuint8_t SIZE:3;
-            vuint8_t PROTECTION:4;
-        } B;
-    } REAT;
-
-    vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */
-
-    union { /* ECSM RAM ECC Data (Base+0x006C) */
-        vuint32_t R;
-    } REDR;
-
-}; /* end of ECSM_tag */
-
-/****************************************************************************/
-/*                          MODULE : eDMA (base address - 0xFFF4_4000)      */
-/****************************************************************************/
-
-   /* There are 4 different TCD structures which should be used based on     */
-  /*  how the DMA is configured as below. CAUTION - Do not mix TCD's        */
-  /*                                                                        */
-  /*  Channel Linking      Minor Loop Mapping     Addressing TCD            */
-  /*       OFF                   OFF               XBAR.TCD[x]              */
-  /*       OFF                   ON                XBAR.ML_TCD[x]           */
-  /*       ON                    OFF               XBAR.CL_TCD[X]           */
-  /*       ON                    ON                XBAR.MLCL_TCD[X]         */
-  /*                                                                        */
-
-    /*for "standard" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=0) */
-  /* (1) - Standard TCD (Channel Linking OFF, Minor Loop mapping OFF        */
-    struct EDMA_TCD_STD_tag {
-
-        vuint32_t SADDR; /* Source address                         */
-
-        vuint16_t SMOD:5; /* Source address modulo                  */
-        vuint16_t SSIZE:3; /* Source data transfer size              */
-        vuint16_t DMOD:5; /* Destination address modulo             */
-        vuint16_t DSIZE:3; /* Destination data transfer size         */
-        vint16_t SOFF; /* Source address signed offset           */
-
-        vuint32_t NBYTES; /* Inner "minor" byte transfer count      */
-
-        vint32_t SLAST; /* Last source address adjustment         */
-
-        vuint32_t DADDR; /* Destination address                    */
-
-        vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
-        vuint16_t CITER:15; /* Current Major iteration count          */
-        vint16_t DOFF; /* Destination address signed offset      */
-
-        vint32_t DLAST_SGA; /* Last desitination address adjustment   */
-
-        vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
-        vuint16_t BITER:15; /* Starting major iteration count         */
-        vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
-        vuint16_t MAJORLINKCH:6; /* Link channel number                    */
-        vuint16_t DONE:1; /* Channel done                           */
-        vuint16_t ACTIVE:1; /* Channel active                         */
-        vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
-        vuint16_t E_SG:1; /* Enable scatter/gather processing       */
-        vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit)   */
-        vuint16_t INT_HALF:1; /* interrupt on Major loop half complete  */
-        vuint16_t INT_MAJ:1; /* interrupt on major loop complete       */
-        vuint16_t START:1; /* Chanel start                           */
-
-    }; /* End of Standard TCD tag                                           */
-
-
-  /* (2) - ML_TCD (Channel Linking OFF, Minor Loop mapping Enabled          */
-  /*      (EMLM = 1)                                                        */
-    struct EDMA_TCD_MLMIRROR_tag {
-
-        vuint32_t SADDR; /* Source address                         */
-
-        vuint16_t SMOD:5; /* Source address modulo                  */
-        vuint16_t SSIZE:3; /* Source data transfer size              */
-        vuint16_t DMOD:5; /* Destination address modulo             */
-        vuint16_t DSIZE:3; /* Destination data transfer size         */
-        vint16_t SOFF; /* Source address signed offset           */
-
-        vuint32_t SMLOE:1; /* Source minor loop offset enabled       */
-        vuint32_t DMLOE:1; /* Destination minor loop offset enable   */
-        vuint32_t MLOFF:20; /* Minor loop offset                      */
-        vuint32_t NBYTES:10; /* Inner "minor" byte transfer count      */
-
-        vint32_t SLAST; /* Last source address adjustment         */
-
-        vuint32_t DADDR; /* Destination address                    */
-
-        vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
-        vuint16_t CITER:15; /* Current Major iteration count          */
-        vint16_t DOFF; /* Destination address signed offset      */
-
-        vint32_t DLAST_SGA; /* Last desitination address adjustment   */
-
-        vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
-        vuint16_t BITER:15; /* Starting major iteration count         */
-        vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
-        vuint16_t MAJORLINKCH:6; /* Link channel number                    */
-        vuint16_t DONE:1; /* Channel done                           */
-        vuint16_t ACTIVE:1; /* Channel active                         */
-        vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
-        vuint16_t E_SG:1; /* Enable scatter/gather processing       */
-        vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit)   */
-        vuint16_t INT_HALF:1; /* interrupt on Major loop half complete  */
-        vuint16_t INT_MAJ:1; /* interrupt on major loop complete       */
-        vuint16_t START:1; /* Chanel start                           */
-
-    }; /* End of EDMA_TCD_MLMIRROR_tag                                      */
-
-    /*for "channel link" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=1)*/
-  /* (3) - CL_TCD (Channel Linking Enabled, Minor Loop mapping OFF          */
-  /*       (CITERE_LINK = BITERE_LINK = 1)                                  */
-    struct EDMA_TCD_CHLINK_tag {
-
-        vuint32_t SADDR; /* Source address                         */
-
-        vuint16_t SMOD:5; /* Source address modulo                  */
-        vuint16_t SSIZE:3; /* Source data transfer size              */
-        vuint16_t DMOD:5; /* Destination address modulo             */
-        vuint16_t DSIZE:3; /* Destination data transfer size         */
-        vint16_t SOFF; /* Source address signed offset           */
-
-        vuint32_t NBYTES; /* Inner "minor" byte transfer count      */
-
-        vint32_t SLAST; /* Last source address adjustment         */
-
-        vuint32_t DADDR; /* Destination address                    */
-
-        vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
-        vuint16_t CITERLINKCH:6; /* Link channel number                    */
-        vuint16_t CITER:9; /* Current Major iteration count          */
-        vint16_t DOFF; /* Destination address signed offset      */
-
-        vint32_t DLAST_SGA; /* Last desitination address adjustment   */
-
-        vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
-        vuint16_t BITERLINKCH:6; /* Link channel number                    */
-        vuint16_t BITER:9; /* Starting Major iteration count         */
-        vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
-        vuint16_t MAJORLINKCH:6; /* Link channel number                    */
-        vuint16_t DONE:1; /* Channel done                           */
-        vuint16_t ACTIVE:1; /* Channel active                         */
-        vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
-        vuint16_t E_SG:1; /* Enable scatter/gather processing       */
-        vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit)   */
-        vuint16_t INT_HALF:1; /* interrupt on Major loop half complete  */
-        vuint16_t INT_MAJ:1; /* interrupt on major loop complete       */
-        vuint16_t START:1; /* Chanel start                           */
-
-    }; /* end of EDMA_TCD_CHLINK_tag                                        */
-
-  /* (4) - CL_TCD (Channel Linking Enabled, Minor Loop mapping Enabled      */
-  /*       (CITERE_LINK = BITERE_LINK = 1, EMLM = 1)                        */
-    struct EDMA_TCD_MLMIRROR_CHLINK_tag {
-
-        vuint32_t SADDR; /* Source address                         */
-
-        vuint16_t SMOD:5; /* Source address modulo                  */
-        vuint16_t SSIZE:3; /* Source data transfer size              */
-        vuint16_t DMOD:5; /* Destination address modulo             */
-        vuint16_t DSIZE:3; /* Destination data transfer size         */
-        vint16_t SOFF; /* Source address signed offset           */
-
-        vuint32_t SMLOE:1; /* Source minor loop offset enabled       */
-        vuint32_t DMLOE:1; /* Destination minor loop offset enable   */
-        vuint32_t MLOFF:20; /* Minor loop offset                      */
-        vuint32_t NBYTES:10; /* Inner "minor" byte transfer count      */
-
-        vint32_t SLAST; /* Last source address adjustment         */
-
-        vuint32_t DADDR; /* Destination address                    */
-
-        vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
-        vuint16_t CITERLINKCH:6; /* Link channel number                    */
-        vuint16_t CITER:9; /* Current Major iteration count          */
-        vint16_t DOFF; /* Destination address signed offset      */
-
-        vint32_t DLAST_SGA; /* Last desitination address adjustment   */
-
-        vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
-        vuint16_t BITERLINKCH:6; /* Link channel number                    */
-        vuint16_t BITER:9; /* Starting Major iteration count         */
-        vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
-        vuint16_t MAJORLINKCH:6; /* Link channel number                    */
-        vuint16_t DONE:1; /* Channel done                           */
-        vuint16_t ACTIVE:1; /* Channel active                         */
-        vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
-        vuint16_t E_SG:1; /* Enable scatter/gather processing       */
-        vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit)   */
-        vuint16_t INT_HALF:1; /* interrupt on Major loop half complete  */
-        vuint16_t INT_MAJ:1; /* interrupt on major loop complete       */
-        vuint16_t START:1; /* Chanel start                           */
-
-    }; /* end of EDMA_TCD_MLMIRROR_CHLINK_tag                               */
-
-struct EDMA_tag {
-
-    union { /* Control (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t :14;
-            vuint32_t CX:1;
-            vuint32_t ECX:1;
-            vuint32_t :6; 
-            vuint32_t GRP0PRI:2;
-            vuint32_t EMLM:1;
-            vuint32_t CLM:1;
-            vuint32_t HALT:1;
-            vuint32_t HOE:1;
-            vuint32_t ERGA:1;
-            vuint32_t ERCA:1;
-            vuint32_t EDBG:1;
-            vuint32_t EBW:1;
-        } B;
-    } CR;
-
-    union { /* Error Status (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t VLD:1;
-            vuint32_t :16;
-            vuint32_t CPE:1;
-            vuint32_t ERRCHN:6;
-            vuint32_t SAE:1;
-            vuint32_t SOE:1;
-            vuint32_t DAE:1;
-            vuint32_t DOE:1;
-            vuint32_t NCE:1;
-            vuint32_t SGE:1;
-            vuint32_t SBE:1;
-            vuint32_t DBE:1;
-        } B;
-    } ESR;
-
-    vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B)*/
-
-    union { /* Enable Request Low Ch15..0 (Base+0x000C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-			vuint32_t ERQ15:1;
-            vuint32_t ERQ14:1;
-            vuint32_t ERQ13:1;
-            vuint32_t ERQ12:1;
-            vuint32_t ERQ11:1;
-            vuint32_t ERQ10:1;
-            vuint32_t ERQ09:1;
-            vuint32_t ERQ08:1;
-            vuint32_t ERQ07:1;
-            vuint32_t ERQ06:1;
-            vuint32_t ERQ05:1;
-            vuint32_t ERQ04:1;
-            vuint32_t ERQ03:1;
-            vuint32_t ERQ02:1;
-            vuint32_t ERQ01:1;
-            vuint32_t ERQ00:1;
-        } B;
-    } ERQRL;
-
-    vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013)*/
-
-    union { /* Enable Error Interrupt Low (Base+0x0014) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-			vuint32_t EEI15:1;
-            vuint32_t EEI14:1;
-            vuint32_t EEI13:1;
-            vuint32_t EEI12:1;
-            vuint32_t EEI11:1;
-            vuint32_t EEI10:1;
-            vuint32_t EEI09:1;
-            vuint32_t EEI08:1;
-            vuint32_t EEI07:1;
-            vuint32_t EEI06:1;
-            vuint32_t EEI05:1;
-            vuint32_t EEI04:1;
-            vuint32_t EEI03:1;
-            vuint32_t EEI02:1;
-            vuint32_t EEI01:1;
-            vuint32_t EEI00:1;
-        } B;
-    } EEIRL;
-
-    union { /* DMA Set Enable Request (Base+0x0018) */
-        vuint8_t R;
-        struct {
-            vuint8_t :1;
-            vuint8_t SERQ:7;
-        } B;
-    } SERQR;
-
-    union { /* DMA Clear Enable Request (Base+0x0019) */
-        vuint8_t R;
-        struct {
-            vuint8_t :1;
-            vuint8_t CERQ:7;
-        } B;
-    } CERQR;
-
-    union { /* DMA Set Enable Error Interrupt (Base+0x001A) */
-        vuint8_t R;
-        struct {
-            vuint8_t :1;
-            vuint8_t SEEI:7;
-        } B;
-    } SEEIR;
-
-    union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */
-        vuint8_t R;
-        struct {
-            vuint8_t:1;
-            vuint8_t CEEI:7;
-        } B;
-    } CEEIR;
-
-    union { /* DMA Clear Interrupt Request (Base+0x001C) */
-        vuint8_t R;
-        struct {
-            vuint8_t :1;
-            vuint8_t CINT:7;
-        } B;
-    } CIRQR;
-
-    union { /* DMA Clear error (Base+0x001D) */
-        vuint8_t R;
-        struct {
-            vuint8_t :1;
-            vuint8_t CERR:7;
-        } B;
-    } CER;
-
-    union { /* DMA Set Start Bit (Base+0x001E) */
-        vuint8_t R;
-        struct {
-            vuint8_t :1;
-            vuint8_t SSB:7;
-        } B;
-    } SSBR;
-
-    union { /* DMA Clear Done Status Bit (Base+0x001F) */
-        vuint8_t R;
-        struct {
-            vuint8_t :1;
-            vuint8_t CDSB:7;
-        } B;
-    } CDSBR;
-
-    vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023)*/
-
-    union { /* DMA Interrupt Req Low Ch15..0 (+0x0024) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-			vuint32_t INT15:1;
-            vuint32_t INT14:1;
-            vuint32_t INT13:1;
-            vuint32_t INT12:1;
-            vuint32_t INT11:1;
-            vuint32_t INT10:1;
-            vuint32_t INT09:1;
-            vuint32_t INT08:1;
-            vuint32_t INT07:1;
-            vuint32_t INT06:1;
-            vuint32_t INT05:1;
-            vuint32_t INT04:1;
-            vuint32_t INT03:1;
-            vuint32_t INT02:1;
-            vuint32_t INT01:1;
-            vuint32_t INT00:1;
-        } B;
-    } IRQRL;
-
-    vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B)*/
-
-    union { /* DMA Error Low Ch15..0 (Base+0x002C)*/
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-			vuint32_t ERR15:1;
-            vuint32_t ERR14:1;
-            vuint32_t ERR13:1;
-            vuint32_t ERR12:1;
-            vuint32_t ERR11:1;
-            vuint32_t ERR10:1;
-            vuint32_t ERR09:1;
-            vuint32_t ERR08:1;
-            vuint32_t ERR07:1;
-            vuint32_t ERR06:1;
-            vuint32_t ERR05:1;
-            vuint32_t ERR04:1;
-            vuint32_t ERR03:1;
-            vuint32_t ERR02:1;
-            vuint32_t ERR01:1;
-            vuint32_t ERR00:1;
-        } B;
-    } ERL;
-
-    vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033)*/
-
-    union { /* DMA Hardware Request Stat Low (Base+0x0034) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-			vuint32_t HRS15:1;
-            vuint32_t HRS14:1;
-            vuint32_t HRS13:1;
-            vuint32_t HRS12:1;
-            vuint32_t HRS11:1;
-            vuint32_t HRS10:1;
-            vuint32_t HRS09:1;
-            vuint32_t HRS08:1;
-            vuint32_t HRS07:1;
-            vuint32_t HRS06:1;
-            vuint32_t HRS05:1;
-            vuint32_t HRS04:1;
-            vuint32_t HRS03:1;
-            vuint32_t HRS02:1;
-            vuint32_t HRS01:1;
-            vuint32_t HRS00:1;
-        } B;
-    } HRSL;
-
-    vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/
-
-    union { /* Channel n Priority (Base+0x0100-0x010F)*/
-        vuint8_t R;
-        struct {
-            vuint8_t ECP:1;
-            vuint8_t DPA:1;
-            vuint8_t GRPPRI:2;
-            vuint8_t CHPRI:4;
-        } B;
-    } CPR[16];
-
-	vuint8_t eDMA_reserved6[3824]; /* Reserved 3808 bytes (+0x0110-0x0FFF) */
-
-    
-union { /* 4 different TCD definitions depending on operating mode    */
-
-        /* Default TCD (Channel Linking and Minor Loop Maping disabled)     */
-        struct EDMA_TCD_STD_tag TCD[16];
-
-        /* ML_TCD (Channel Linking disabled, Minor Loop Mapping enabled)    */
-        struct EDMA_TCD_MLMIRROR_tag ML_TCD[16];
-
-        /* CL_TCD (Channel Linking enabled, Minor Loop Mapping disabled)    */
-        struct EDMA_TCD_CHLINK_tag CL_TCD[16];
-
-        /* MLCL_TCD (Channel Linking enabled, Minor Loop Mapping enabled)   */
-        struct EDMA_TCD_MLMIRROR_CHLINK_tag MLCL_TCD[16];
-     };
-	
-	
-	vuint8_t eDMA_reserved7[28160]; /* Reserved 28160 bytes (+0x1200-0x7FFF) */
-
-}; /* end of EDMA_tag */
-/*************************************************************************/
-/*             MODULE : INTC (base address - 0xFFF4_8000)     			 */
-/*************************************************************************/
-struct INTC_tag {
-
-    union { /* INTC Module Configuration (Base+0x0000) */
-        vuint32_t R;
-        struct {
-			vuint32_t:26;
-			vuint32_t VTES:1;
-			vuint32_t:4;
-			vuint32_t HVEN:1;
-        } B;
-    } MCR;
-
-    vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */
-
-    union { /* INTC Current Priority (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t:28;
-            vuint32_t PRI:4;
-        } B;
-    } CPR;
-	
-	vuint8_t INTC_reserved1[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
-
-    union { /* INTC Interrupt Acknowledge (Base+0x0010) */
-        vuint32_t R;
-        struct {
-            vuint32_t VTBA_PRC0:21;
-            vuint32_t INTVEC_PRC0:9;
-            vuint32_t:2;
-        } B;
-    } IACKR;
-
-	vuint8_t INTC_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */
-	
-    union { /* INTC End Of Interrupt (Base+0x0018) */
-        vuint32_t R;
-        struct {
-            vuint32_t:32;
-        } B;
-    } EOIR;
-
-	vuint8_t INTC_reserved3[4]; /* reserved 4 bytes (Base+0x001C-0x0019) */
-	
-    union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */
-        vuint8_t R;
-        struct {
-            vuint8_t:6;
-            vuint8_t SET:1;
-            vuint8_t CLR:1;
-        } B;
-    } SSCIR[8];
-
-    vuint8_t INTC_reserved4[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */
-
-    union { /* INTC Priority Select (Base+0x0040-0x0128) */
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t PRI:4;
-            } B;
-        } PSR[234]; 
-
-}; /* end of INTC_tag */
-/****************************************************************************/
-/*                          MODULE : DSPI    								*/
-/* Base Addresses: 															*/
-/* DSPI_0 - 0xFFF9_0000                               						*/
-/* DSPI_1 - 0xFFF9_4000                               						*/
-/* DSPI_2 - 0xFFF9_8000                               						*/
-/* DSPI_3 - 0xFFF9_C000                               						*/
-/* DSPI_4 - 0xFFFA_0000                               						*/
-/* DSPI_5 - 0xFFFA_4000                               						*/
-/****************************************************************************/
-struct DSPI_tag{
-
-    union { /* DSPI Module Configuraiton (Base+0x0000) */
-        vuint32_t R;
-        struct {
-            vuint32_t MSTR:1;
-            vuint32_t CONT_SCKE:1;
-            vuint32_t DCONF:2;
-            vuint32_t FRZ:1;
-            vuint32_t MTFE:1;
-            vuint32_t PCSSE:1;
-            vuint32_t ROOE:1;
-            vuint32_t :2; 
-            vuint32_t PCSIS5:1;
-            vuint32_t PCSIS4:1;
-            vuint32_t PCSIS3:1;
-            vuint32_t PCSIS2:1;
-            vuint32_t PCSIS1:1;
-            vuint32_t PCSIS0:1;
-            vuint32_t :1; 
-            vuint32_t MDIS:1;
-            vuint32_t DIS_TXF:1;
-            vuint32_t DIS_RXF:1;
-            vuint32_t CLR_TXF:1;
-            vuint32_t CLR_RXF:1;
-            vuint32_t SMPL_PT:2;
-            vuint32_t :7;
-            vuint32_t HALT:1;
-        } B;
-    } MCR;
-
-	vuint8_t DSPI_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
-
-    union { /* DSPI Transfer Count (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t TCNT:16;
-            vuint32_t :16;
-        } B;
-    } TCR;
-
-    union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */
-        vuint32_t R;
-        struct {
-            vuint32_t DBR:1;
-            vuint32_t FMSZ:4;
-            vuint32_t CPOL:1;
-            vuint32_t CPHA:1;
-            vuint32_t LSBFE:1;
-            vuint32_t PCSSCK:2;
-            vuint32_t PASC:2;
-            vuint32_t PDT:2;
-            vuint32_t PBR:2;
-            vuint32_t CSSCK:4;
-            vuint32_t ASC:4;
-            vuint32_t DT:4;
-            vuint32_t BR:4;
-        } B;
-    } CTAR[6];
-
-    vuint8_t DSPI_reserved1[8]; /* Reserved 4 bytes (Base+0x0024-0x002B) */
-
-    union { /* DSPI Status (Base+0x002C) */
-        vuint32_t R;
-        struct {
-            vuint32_t TCF:1;
-            vuint32_t TXRXS:1;
-            vuint32_t :1;
-            vuint32_t EOQF:1;
-            vuint32_t TFUF:1;
-            vuint32_t :1;
-            vuint32_t TFFF:1;
-            vuint32_t :5;
-            vuint32_t RFOF:1;
-            vuint32_t :1;
-            vuint32_t RFDF:1;
-            vuint32_t :1;
-            vuint32_t TXCTR:4;
-            vuint32_t TXNXTPTR:4;
-            vuint32_t RXCTR:4;
-            vuint32_t POPNXTPTR:4;
-        } B;
-    } SR;
-
-    union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */
-        vuint32_t R;
-        struct {
-            vuint32_t TCFRE:1;
-            vuint32_t :2;
-            vuint32_t EOQFRE:1;
-            vuint32_t TFUFRE:1;
-            vuint32_t :1;
-            vuint32_t TFFFRE:1;
-            vuint32_t TFFFDIRS:1;
-            vuint32_t :4;
-            vuint32_t RFOFRE:1;
-            vuint32_t :1;
-            vuint32_t RFDFRE:1;
-            vuint32_t RFDFDIRS:1;
-            vuint32_t :16;
-        } B;
-    } RSER;
-
-    union { /* DSPI Push TX FIFO (Base+0x0034) */
-        vuint32_t R;
-        struct {
-            vuint32_t CONT:1;
-            vuint32_t CTAS:3;
-            vuint32_t EOQ:1;
-            vuint32_t CTCNT:1;
-            vuint32_t :4; 
-            vuint32_t PCS5:1;
-            vuint32_t PCS4:1;
-            vuint32_t PCS3:1;
-            vuint32_t PCS2:1;
-            vuint32_t PCS1:1;
-            vuint32_t PCS0:1;
-            vuint32_t TXDATA:16;
-        } B;
-    } PUSHR;
-
-    union { /* DSPI Pop RX FIFO (Base+0x0038)             */
-        vuint32_t R;
-        struct {
-            vuint32_t :16; 
-			vuint32_t RXDATA:16; 
-        } B;
-    } POPR;
-
-    union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/
-        vuint32_t R;
-        struct { 
-            vuint32_t TXCMD:16; 
-            vuint32_t TXDATA:16;
-        } B;
-    } TXFR[4];
-
-    vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */
-
-    union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16; 
-			vuint32_t RXDATA:16; 
-        } B;
-    } RXFR[4];
- };                          /* end of DSPI_tag */
- /****************************************************************************/
-/*                          MODULE : FlexCAN                                */
-/* Base Addresses:															*/
-/* FlexCAN_0 - 0xFFFC_0000													*/
-/****************************************************************************/
-struct FLEXCAN_BUF_t{
-
-    union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */
-        vuint32_t R;
-        struct {
-            vuint32_t :4;
-            vuint32_t CODE:4;
-            vuint32_t :1;
-            vuint32_t SRR:1;
-            vuint32_t IDE:1;
-            vuint32_t RTR:1;
-            vuint32_t LENGTH:4;
-            vuint32_t TIMESTAMP:16;
-        } B;
-    } CS;
-
-    union { /* FLEXCAN MBx Identifier (Offset+0x0084) */
-        vuint32_t R;
-        struct {
-            vuint32_t PRIO:3;
-            vuint32_t STD_ID:11;
-            vuint32_t EXT_ID:18;
-        } B;
-    } ID;
-
-    union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */
-        vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
-        vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
-        vuint32_t W[2]; /* Data buffer in words (32 bits) */
-        vuint32_t R[2]; /* Data buffer in words (32 bits) */
-    } DATA;
-
-}; /* end of FLEXCAN_BUF_t */
-
-
-struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */
-
-    union { /* RxFIFO Control & Status (Offset+0x0080) */
-        vuint32_t R;
-        struct {
-            vuint32_t :9;
-            vuint32_t SRR:1;
-            vuint32_t IDE:1;
-            vuint32_t RTR:1;
-            vuint32_t LENGTH:4;
-            vuint32_t TIMESTAMP:16;
-        } B;
-    } CS;
-
-    union { /* RxFIFO Identifier (Offset+0x0084) */
-        vuint32_t R;
-        struct {
-            vuint32_t :3;
-            vuint32_t STD_ID:11;
-            vuint32_t EXT_ID:18;
-        } B;
-    } ID;
-
-    union { /* RxFIFO Data 0..7 (Offset+0x0088) */
-        vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
-        vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
-        vuint32_t W[2]; /* Data buffer in words (32 bits) */
-        vuint32_t R[2]; /* Data buffer in words (32 bits) */
-    } DATA;
-
-    vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/
-
-    union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */
-        vuint32_t R;
-    } IDTABLE[8];
-
-}; /* end of FLEXCAN_RXFIFO_t */
-
-
-struct FLEXCAN_tag{
-
-    union { /* FLEXCAN Module Configuration (Base+0x0000) */
-        vuint32_t R;
-        struct {
-			vuint32_t MDIS:1;
-			vuint32_t FRZ:1;
-			vuint32_t FEN:1;
-			vuint32_t HALT:1;
-			vuint32_t NOTRDY:1;
-			vuint32_t WAKMSK:1;
-			vuint32_t SOFTRST:1;
-			vuint32_t FRZACK:1;
-			vuint32_t SUPV:1;
-			vuint32_t :1;  
-			vuint32_t WRNEN:1;
-			vuint32_t LPMACK:1;
-			vuint32_t WAKSRC:1;
-			vuint32_t :1; 
-			vuint32_t SRXDIS:1;
-			vuint32_t BCC:1;
-			vuint32_t:2;
-			vuint32_t LPRIO_EN:1;
-			vuint32_t AEN:1;
-			vuint32_t:2;
-			vuint32_t IDAM:2;
-			vuint32_t:2;
-			vuint32_t MAXMB:6;
-        } B;
-    } MCR;
-
-    union { /* FLEXCAN Control (Base+0x0004) */
-        vuint32_t R;
-        struct {
-            vuint32_t PRESDIV:8;
-            vuint32_t RJW:2;
-            vuint32_t PSEG1:3;
-            vuint32_t PSEG2:3;
-            vuint32_t BOFFMSK:1;
-            vuint32_t ERRMSK:1;
-            vuint32_t CLKSRC:1;
-            vuint32_t LPB:1;
-            vuint32_t TWRNMSK:1;
-            vuint32_t RWRNMSK:1;
-            vuint32_t :2;
-            vuint32_t SMP:1;
-            vuint32_t BOFFREC:1;
-            vuint32_t TSYN:1;
-            vuint32_t LBUF:1;
-            vuint32_t LOM:1;
-            vuint32_t PROPSEG:3;
-        } B;
-    } CR;
-
-    union { /* FLEXCAN Free Running Timer (Base+0x0008) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t TIMER:16;
-        } B;
-     } TIMER;
-
-    vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
-
-    union { /* FLEXCAN RX Global Mask (Base+0x0010) */
-        vuint32_t R;
-        struct {
-            vuint32_t MI:32;
-        } B;
-     } RXGMASK;
-
-    /*  --- Following 2 registers are included for legacy purposes only --- */
-
-    union { /* FLEXCAN RX 14 Mask (Base+0x0014) */
-        vuint32_t R;
-        struct {
-            vuint32_t MI:32;
-        } B;
-     } RX14MASK;
-
-    union { /* FLEXCAN RX 15 Mask (Base+0x0018) */
-        vuint32_t R;
-        struct {
-            vuint32_t MI:32;
-        } B;
-     } RX15MASK;
-
-    /*  --- */
-
-    union { /* FLEXCAN Error Counter (Base+0x001C) */
-        vuint32_t R;
-        struct {
-            vuint32_t :16;
-            vuint32_t RXECNT:8;
-            vuint32_t TXECNT:8;
-        } B;
-    } ECR;
-
-    union { /* FLEXCAN Error & Status (Base+0x0020) */
-        vuint32_t R;
-        struct {
-            vuint32_t :14;
-            vuint32_t TWRNINT:1;
-            vuint32_t RWRNINT:1;
-            vuint32_t BIT1ERR:1;
-            vuint32_t BIT0ERR:1;
-            vuint32_t ACKERR:1;
-            vuint32_t CRCERR:1;
-            vuint32_t FRMERR:1;
-            vuint32_t STFERR:1;
-            vuint32_t TXWRN:1;
-            vuint32_t RXWRN:1;
-            vuint32_t IDLE:1;
-            vuint32_t TXRX:1;
-            vuint32_t FLTCONF:2;
-            vuint32_t :1;
-            vuint32_t BOFFINT:1;
-            vuint32_t ERRINT:1;
-            vuint32_t :1;
-        } B;
-    } ESR;
-
-    union { /* FLEXCAN Interruput Masks H (Base+0x0024) */
-        vuint32_t R;
-        struct {
-            vuint32_t BUF63M:1;
-            vuint32_t BUF62M:1;
-            vuint32_t BUF61M:1;
-            vuint32_t BUF60M:1;
-            vuint32_t BUF59M:1;
-            vuint32_t BUF58M:1;
-            vuint32_t BUF57M:1;
-            vuint32_t BUF56M:1;
-            vuint32_t BUF55M:1;
-            vuint32_t BUF54M:1;
-            vuint32_t BUF53M:1;
-            vuint32_t BUF52M:1;
-            vuint32_t BUF51M:1;
-            vuint32_t BUF50M:1;
-            vuint32_t BUF49M:1;
-            vuint32_t BUF48M:1;
-            vuint32_t BUF47M:1;
-            vuint32_t BUF46M:1;
-            vuint32_t BUF45M:1;
-            vuint32_t BUF44M:1;
-            vuint32_t BUF43M:1;
-            vuint32_t BUF42M:1;
-            vuint32_t BUF41M:1;
-            vuint32_t BUF40M:1;
-            vuint32_t BUF39M:1;
-            vuint32_t BUF38M:1;
-            vuint32_t BUF37M:1;
-            vuint32_t BUF36M:1;
-            vuint32_t BUF35M:1;
-            vuint32_t BUF34M:1;
-            vuint32_t BUF33M:1;
-            vuint32_t BUF32M:1;
-        } B;
-    } IMRH;
-
-    union { /* FLEXCAN Interruput Masks L (Base+0x0028) */
-        vuint32_t R;
-        struct {
-            vuint32_t BUF31M:1;
-            vuint32_t BUF30M:1;
-            vuint32_t BUF29M:1;
-            vuint32_t BUF28M:1;
-            vuint32_t BUF27M:1;
-            vuint32_t BUF26M:1;
-            vuint32_t BUF25M:1;
-            vuint32_t BUF24M:1;
-            vuint32_t BUF23M:1;
-            vuint32_t BUF22M:1;
-            vuint32_t BUF21M:1;
-            vuint32_t BUF20M:1;
-            vuint32_t BUF19M:1;
-            vuint32_t BUF18M:1;
-            vuint32_t BUF17M:1;
-            vuint32_t BUF16M:1;
-            vuint32_t BUF15M:1;
-            vuint32_t BUF14M:1;
-            vuint32_t BUF13M:1;
-            vuint32_t BUF12M:1;
-            vuint32_t BUF11M:1;
-            vuint32_t BUF10M:1;
-            vuint32_t BUF09M:1;
-            vuint32_t BUF08M:1;
-            vuint32_t BUF07M:1;
-            vuint32_t BUF06M:1;
-            vuint32_t BUF05M:1;
-            vuint32_t BUF04M:1;
-            vuint32_t BUF03M:1;
-            vuint32_t BUF02M:1;
-            vuint32_t BUF01M:1;
-            vuint32_t BUF00M:1;
-        } B;
-    } IMRL;
-
-    union { /* FLEXCAN Interruput Flag H (Base+0x002C) */
-        vuint32_t R;
-        struct {
-            vuint32_t BUF63I:1;
-            vuint32_t BUF62I:1;
-            vuint32_t BUF61I:1;
-            vuint32_t BUF60I:1;
-            vuint32_t BUF59I:1;
-            vuint32_t BUF58I:1;
-            vuint32_t BUF57I:1;
-            vuint32_t BUF56I:1;
-            vuint32_t BUF55I:1;
-            vuint32_t BUF54I:1;
-            vuint32_t BUF53I:1;
-            vuint32_t BUF52I:1;
-            vuint32_t BUF51I:1;
-            vuint32_t BUF50I:1;
-            vuint32_t BUF49I:1;
-            vuint32_t BUF48I:1;
-            vuint32_t BUF47I:1;
-            vuint32_t BUF46I:1;
-            vuint32_t BUF45I:1;
-            vuint32_t BUF44I:1;
-            vuint32_t BUF43I:1;
-            vuint32_t BUF42I:1;
-            vuint32_t BUF41I:1;
-            vuint32_t BUF40I:1;
-            vuint32_t BUF39I:1;
-            vuint32_t BUF38I:1;
-            vuint32_t BUF37I:1;
-            vuint32_t BUF36I:1;
-            vuint32_t BUF35I:1;
-            vuint32_t BUF34I:1;
-            vuint32_t BUF33I:1;
-            vuint32_t BUF32I:1;
-        } B;
-    } IFRH;
-
-    union { /* FLEXCAN Interruput Flag l (Base+0x0030) */
-        vuint32_t R;
-        struct {
-            vuint32_t BUF31I:1;
-            vuint32_t BUF30I:1;
-            vuint32_t BUF29I:1;
-            vuint32_t BUF28I:1;
-            vuint32_t BUF27I:1;
-            vuint32_t BUF26I:1;
-            vuint32_t BUF25I:1;
-            vuint32_t BUF24I:1;
-            vuint32_t BUF23I:1;
-            vuint32_t BUF22I:1;
-            vuint32_t BUF21I:1;
-            vuint32_t BUF20I:1;
-            vuint32_t BUF19I:1;
-            vuint32_t BUF18I:1;
-            vuint32_t BUF17I:1;
-            vuint32_t BUF16I:1;
-            vuint32_t BUF15I:1;
-            vuint32_t BUF14I:1;
-            vuint32_t BUF13I:1;
-            vuint32_t BUF12I:1;
-            vuint32_t BUF11I:1;
-            vuint32_t BUF10I:1;
-            vuint32_t BUF09I:1;
-            vuint32_t BUF08I:1;
-            vuint32_t BUF07I:1;
-            vuint32_t BUF06I:1;
-            vuint32_t BUF05I:1;
-            vuint32_t BUF04I:1;
-            vuint32_t BUF03I:1;
-            vuint32_t BUF02I:1;
-            vuint32_t BUF01I:1;
-            vuint32_t BUF00I:1;
-        } B;
-    } IFRL; /* Interruput Flag Register */
-
-    vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/
-
-/****************************************************************************/
-/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure     */
-/****************************************************************************/
-    /* Standard Buffer Structure */
-    struct FLEXCAN_BUF_t BUF[64];
-
-    /* RX FIFO and Buffer Structure */
-    /*struct FLEXCAN_RXFIFO_t RXFIFO; */
-    /*struct FLEXCAN_BUF_t BUF[56];   */
-/****************************************************************************/
-
-    vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/
-
-    union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */
-        vuint32_t R;
-        struct {
-          vuint32_t MI:32;
-        } B;
-    } RXIMR[64];
-
-}; /* end of FLEXCAN_tag */
-/****************************************************************************/
-/*            MODULE : DMAMUX (base address - 0xFFFD_C000)                  */
-/****************************************************************************/
-    struct DMAMUX_tag {
-    union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */
-        vuint8_t R;
-        struct {
-            vuint8_t ENBL:1;
-            vuint8_t TRIG:1;
-            vuint8_t SOURCE:6;
-            } B;
-        } CHCONFIG[16];         
-
-    };                          /* end of DMAMUX_tag */
-
-/****************************************************************** 
-| defines and macros (scope: module-local) 
-|-----------------------------------------------------------------*/
-/* Define instances of modules */
-
-#define CFLASH    (*(volatile struct CFLASH_tag *)    0xC3F88000UL)
-#define DFLASH    (*(volatile struct DFLASH_tag *)    0xC3F8C000UL)
-#define SIU       (*(volatile struct SIU_tag *)       0xC3F90000UL)
-#define WKUP      (*(volatile struct WKUP_tag *)      0xC3F94000UL)
-#define EMIOS_0   (*(volatile struct EMIOS_tag *)     0xC3FA0000UL)
-#define SSCM      (*(volatile struct SSCM_tag *)      0xC3FD8000UL)
-#define ME        (*(volatile struct ME_tag *)        0xC3FDC000UL)
-#define CGM       (*(volatile struct CGM_tag *)       0xC3FE0000UL)
-#define RGM       (*(volatile struct RGM_tag *)       0xC3FE4000UL)
-#define PCU       (*(volatile struct PCU_tag *)       0xC3FE8000UL)
-#define RTC       (*(volatile struct RTC_tag *)       0xC3FEC000UL)
-#define PIT       (*(volatile struct PIT_tag *)       0xC3FF0000UL)
-#define ADC_1     (*(volatile struct ADC1_tag *)      0xFFE04000UL)
-#define LINFLEX_0 (*(volatile struct LINFLEXD0_tag *) 0xFFE40000UL)
-#define LINFLEX_1 (*(volatile struct LINFLEXD1_tag *) 0xFFE44000UL)
-#define LINFLEX_2 (*(volatile struct LINFLEX_tag *)   0xFFE48000UL)
-#define CTU       (*(volatile struct CTU_tag *)       0xFFE64000UL)
-#define MPU       (*(volatile struct MPU_tag *)       0xFFF10000UL)
-#define SWT       (*(volatile struct SWT_tag *)       0xFFF38000UL)
-#define STM       (*(volatile struct STM_tag *)       0xFFF3C000UL)
-#define ECSM      (*(volatile struct ECSM_tag *)      0xFFF40000UL)
-#define EDMA      (*(volatile struct EDMA_tag *)      0xFFF44000UL) 
-#define INTC      (*(volatile struct INTC_tag *)      0xFFF48000UL)
-#define DSPI_0    (*(volatile struct DSPI_tag *)      0xFFF90000UL)
-#define DSPI_1    (*(volatile struct DSPI_tag *)      0xFFF94000UL)
-#define CAN_0     (*(volatile struct FLEXCAN_tag *)   0xFFFC0000UL)
-#define DMAMUX    (*(volatile struct DMAMUX_tag *)    0xFFFDC000UL)
-
-
-#ifdef __MWERKS__
-#pragma pop
-#endif
-
-#ifdef  __cplusplus
-}
-#endif
-#endif                          
-/* End of file */
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c
deleted file mode 100644
index 799908d46..000000000
--- a/os/hal/platforms/SPC560Pxx/hal_lld.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560Pxx/hal_lld.c
- * @brief   SPC560Pxx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PIT channel 3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector59) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  /* Resets the PIT channel 3 IRQ flag.*/
-  PIT.CH[0].TFLG.R = 1;
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-  uint32_t reg;
-
-  /* The system is switched to the RUN0 mode, the default for normal
-     operations.*/
-  if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* INTC initialization, software vector mode, 4 bytes vectors, starting
-     at priority 0.*/
-  INTC.MCR.R        = 0;
-  INTC.CPR.R        = 0;
-  INTC.IACKR.R      = (uint32_t)_vectors;
-
-  /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
-     to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
-     modes.*/
-  INTC.PSR[59].R    = SPC5_PIT0_IRQ_PRIORITY;
-  halSPCSetPeripheralClockMode(92,
-                               SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
-  reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
-  PIT.PITMCR.R      = 1;        /* PIT clock enabled, stop while debugging. */
-  PIT.CH[0].LDVAL.R = reg;
-  PIT.CH[0].CVAL.R  = reg;
-  PIT.CH[0].TFLG.R  = 1;        /* Interrupt flag cleared.                  */
-  PIT.CH[0].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */
-
-  /* EDMA initialization.*/
-  edmaInit();
-}
-
-/**
- * @brief   SPC560Pxx clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h and
- *          @p hal_lld.h
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void spc_clock_init(void) {
-
-  /* Waiting for IRC stabilization before attempting anything else.*/
-  while (!ME.GS.B.S_RC)
-    ;
-
-#if !SPC5_NO_INIT
-
-#if SPC5_DISABLE_WATCHDOG
-  /* SWT disabled.*/
-  SWT.SR.R = 0xC520;
-  SWT.SR.R = 0xD928;
-  SWT.CR.R = 0xFF00000A;
-#endif
-
-  /* SSCM initialization. Setting up the most restrictive handling of
-     invalid accesses to peripherals.*/
-  SSCM.ERROR.R = 3;                             /* PAE and RAE bits.        */
-
-  /* RGM errors clearing.*/
-  RGM.FES.R         = 0xFFFF;
-  RGM.DES.R         = 0xFFFF;
-
-  /* The system must be in DRUN mode on entry, if this is not the case then
-     it is considered a serious anomaly.*/
-  if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-#if defined(SPC5_OSC_BYPASS)
-  /* If the board is equipped with an oscillator instead of a xtal then the
-     bypass must be activated.*/
-  CGM.OSC_CTL.B.OSCBYP = TRUE;
-#endif /* SPC5_OSC_BYPASS */
-
-  /* Setting the various dividers and source selectors.*/
-#if SPC5_HAS_AC0
-  CGM.AC0DC.R   = SPC5_CGM_AC0_DC0;
-  CGM.AC0SC.R   = SPC5_AUX0CLK_SRC;
-#endif
-#if SPC5_HAS_AC1
-  CGM.AC1DC.R   = SPC5_CGM_AC1_DC0;
-  CGM.AC1SC.R   = SPC5_AUX1CLK_SRC;
-#endif
-#if SPC5_HAS_AC2
-  CGM.AC2DC.R   = SPC5_CGM_AC2_DC0;
-  CGM.AC2SC.R   = SPC5_AUX2CLK_SRC;
-#endif
-#if SPC5_HAS_AC3
-  CGM.AC3DC.R   = SPC5_CGM_AC3_DC0;
-  CGM.AC3SC.R   = SPC5_AUX3CLK_SRC;
-#endif
-
-  /* Enables the XOSC in order to check its functionality before proceeding
-     with the initialization.*/
-  ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC    | SPC5_ME_MC_IRCON         |         \
-              SPC5_ME_MC_XOSC0ON       | SPC5_ME_MC_CFLAON_NORMAL |         \
-              SPC5_ME_MC_DFLAON_NORMAL | SPC5_ME_MC_MVRON;
-  if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* Initialization of the FMPLLs settings.*/
-  CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF |
-                      ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
-                      (SPC5_FMPLL0_NDIV_VALUE << 16);
-  CGM.FMPLL[0].MR.R = 0;                        /* TODO: Add a setting.     */
-#if SPC5_HAS_FMPLL1
-  CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
-                      ((SPC5_FMPLL1_IDF_VALUE - 1) << 26) |
-                      (SPC5_FMPLL1_NDIV_VALUE << 16);
-  CGM.FMPLL[1].MR.R = 0;                        /* TODO: Add a setting.     */
-#endif
-
-  /* Run modes initialization.*/
-  ME.IS.R           = 8;                        /* Resetting I_ICONF status.*/
-  ME.MER.R          = SPC5_ME_ME_BITS;          /* Enabled run modes.       */
-  ME.TEST.R         = SPC5_ME_TEST_MC_BITS;     /* TEST run mode.           */
-  ME.SAFE.R         = SPC5_ME_SAFE_MC_BITS;     /* SAFE run mode.           */
-  ME.DRUN.R         = SPC5_ME_DRUN_MC_BITS;     /* DRUN run mode.           */
-  ME.RUN[0].R       = SPC5_ME_RUN0_MC_BITS;     /* RUN0 run mode.           */
-  ME.RUN[1].R       = SPC5_ME_RUN1_MC_BITS;     /* RUN1 run mode.           */
-  ME.RUN[2].R       = SPC5_ME_RUN2_MC_BITS;     /* RUN2 run mode.           */
-  ME.RUN[3].R       = SPC5_ME_RUN3_MC_BITS;     /* RUN0 run mode.           */
-  ME.HALT0.R        = SPC5_ME_HALT0_MC_BITS;    /* HALT0 run mode.          */
-  ME.STOP0.R        = SPC5_ME_STOP0_MC_BITS;    /* STOP0 run mode.          */
-  if (ME.IS.B.I_CONF) {
-    /* Configuration rejected.*/
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* Peripherals run and low power modes initialization.*/
-  ME.RUNPC[0].R     = SPC5_ME_RUN_PC0_BITS;
-  ME.RUNPC[1].R     = SPC5_ME_RUN_PC1_BITS;
-  ME.RUNPC[2].R     = SPC5_ME_RUN_PC2_BITS;
-  ME.RUNPC[3].R     = SPC5_ME_RUN_PC3_BITS;
-  ME.RUNPC[4].R     = SPC5_ME_RUN_PC4_BITS;
-  ME.RUNPC[5].R     = SPC5_ME_RUN_PC5_BITS;
-  ME.RUNPC[6].R     = SPC5_ME_RUN_PC6_BITS;
-  ME.RUNPC[7].R     = SPC5_ME_RUN_PC7_BITS;
-  ME.LPPC[0].R      = SPC5_ME_LP_PC0_BITS;
-  ME.LPPC[1].R      = SPC5_ME_LP_PC1_BITS;
-  ME.LPPC[2].R      = SPC5_ME_LP_PC2_BITS;
-  ME.LPPC[3].R      = SPC5_ME_LP_PC3_BITS;
-  ME.LPPC[4].R      = SPC5_ME_LP_PC4_BITS;
-  ME.LPPC[5].R      = SPC5_ME_LP_PC5_BITS;
-  ME.LPPC[6].R      = SPC5_ME_LP_PC6_BITS;
-  ME.LPPC[7].R      = SPC5_ME_LP_PC7_BITS;
-
-  /* CFLASH settings calculated for a maximum clock of 64MHz.*/
-  CFLASH.PFCR0.B.BK0_APC  = 2;
-  CFLASH.PFCR0.B.BK0_RWSC = 2;
-  CFLASH.PFCR1.B.BK1_APC  = 2;
-  CFLASH.PFCR1.B.BK1_RWSC = 2;
-
-  /* Switches again to DRUN mode (current mode) in order to update the
-     settings.*/
-  if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-#endif /* !SPC5_NO_INIT */
-}
-
-/**
- * @brief   Switches the system to the specified run mode.
- *
- * @param[in] mode      one of the possible run modes
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   if the switch operation has been completed.
- * @retval CH_FAILED    if the switch operation failed.
- */
-bool_t halSPCSetRunMode(spc5_runmode_t mode) {
-
-  /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
-  ME.IS.R = 5;
-
-  /* Starts a transition process.*/
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
-
-  /* Waits for the mode switch or an error condition.*/
-  while (TRUE) {
-    uint32_t r = ME.IS.R;
-    if (r & 1)
-      return CH_SUCCESS;
-    if (r & 4)
-      return CH_FAILED;
-  }
-}
-
-/**
- * @brief   Changes the clock mode of a peripheral.
- *
- * @param[in] n         index of the @p PCTL register
- * @param[in] pctl      new value for the @p PCTL register
- *
- * @notapi
- */
-void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
-  uint32_t mode;
-
-  ME.PCTL[n].R = pctl;
-  mode = ME.MCTL.B.TARGET_MODE;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
-}
-
-#if !SPC5_NO_INIT || defined(__DOXYGEN__)
-/**
- * @brief   Returns the system clock under the current run mode.
- *
- * @return              The system clock in Hertz.
- */
-uint32_t halSPCGetSystemClock(void) {
-  uint32_t sysclk;
-
-  sysclk = ME.GS.B.S_SYSCLK;
-  switch (sysclk) {
-  case SPC5_ME_GS_SYSCLK_IRC:
-    return SPC5_IRC_CLK;
-  case SPC5_ME_GS_SYSCLK_XOSC:
-    return SPC5_XOSC_CLK;
-  case SPC5_ME_GS_SYSCLK_FMPLL0:
-    return SPC5_FMPLL0_CLK;
-#if SPC5_HAS_FMPLL1
-  case SPC5_ME_GS_SYSCLK_FMPLL1:
-    return SPC5_FMPLL1_CLK;
-#endif
-  default:
-    return 0;
-  }
-}
-#endif /* !SPC5_NO_INIT */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h
deleted file mode 100644
index 4486b76cb..000000000
--- a/os/hal/platforms/SPC560Pxx/hal_lld.h
+++ /dev/null
@@ -1,985 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560Pxx/hal_lld.h
- * @brief   SPC560Pxx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - SPC5_XOSC_CLK.
- *          - SPC5_OSC_BYPASS (optionally).
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "xpc560p.h"
-#include "spc560p_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @name    Platform identification
- * @{
- */
-#if defined(_SPC560PXX_LARGE_) || defined(__DOXYGEN__)
-#define PLATFORM_NAME               "SPC56APxx Chassis and Safety"
-#else
-#define PLATFORM_NAME               "SPC560Pxx Chassis and Safety"
-#endif
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum XOSC clock frequency.
- */
-#define SPC5_XOSC_CLK_MAX           40000000
-
-/**
- * @brief   Minimum XOSC clock frequency.
- */
-#define SPC5_XOSC_CLK_MIN           4000000
-
-/**
- * @brief   Maximum FMPLLs input clock frequency.
- */
-#define SPC5_FMPLLIN_MIN            4000000
-
-/**
- * @brief   Maximum FMPLLs input clock frequency.
- */
-#define SPC5_FMPLLIN_MAX            16000000
-
-/**
- * @brief   Maximum FMPLLs VCO clock frequency.
- */
-#define SPC5_FMPLLVCO_MAX           512000000
-
-/**
- * @brief   Maximum FMPLLs VCO clock frequency.
- */
-#define SPC5_FMPLLVCO_MIN           256000000
-
-/**
- * @brief   Maximum FMPLL0 output clock frequency.
- */
-#define SPC5_FMPLL0_CLK_MAX         64000000
-
-/**
- * @brief   Maximum FMPLL1 output clock frequency.
- * @note    FMPLL1 is not present on all devices.
- */
-#define SPC5_FMPLL1_CLK_MAX         120000000
-
-/**
- * @brief   Maximum FMPLL1 1D1 output clock frequency.
- * @note    FMPLL1 is not present on all devices.
- */
-#define SPC5_FMPLL1_1D1_CLK_MAX     80000000
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define SPC5_IRC_CLK                16000000    /**< Internal RC oscillator.*/
-/** @} */
-
-/**
- * @name    FMPLL_CR register bits definitions
- * @{
- */
-#define SPC5_FMPLL_ODF_DIV2         (0U << 24)
-#define SPC5_FMPLL_ODF_DIV4         (1U << 24)
-#define SPC5_FMPLL_ODF_DIV8         (2U << 24)
-#define SPC5_FMPLL_ODF_DIV16        (3U << 24)
-/** @} */
-
-/**
- * @name    Clock selectors used in the various GCM SC registers
- * @{
- */
-#define SPC5_CGM_SS_MASK            (15U << 24)
-#define SPC5_CGM_SS_IRC             (0U << 24)
-#define SPC5_CGM_SS_XOSC            (2U << 24)
-#define SPC5_CGM_SS_FMPLL0          (4U << 24)
-#define SPC5_CGM_SS_FMPLL1          (5U << 24)
-#define SPC5_CGM_SS_FMPLL1_1D1      (8U << 24)
-/** @} */
-
-/**
- * @name    ME_GS register bits definitions
- * @{
- */
-#define SPC5_ME_GS_SYSCLK_MASK      (15U << 0)
-#define SPC5_ME_GS_SYSCLK_IRC       (0U << 0)
-#define SPC5_ME_GS_SYSCLK_XOSC      (2U << 0)
-#define SPC5_ME_GS_SYSCLK_FMPLL0    (4U << 0)
-#define SPC5_ME_GS_SYSCLK_FMPLL1    (5U << 0)
-/** @} */
-
-/**
- * @name    ME_ME register bits definitions
- * @{
- */
-#define SPC5_ME_ME_RESET            (1U << 0)
-#define SPC5_ME_ME_TEST             (1U << 1)
-#define SPC5_ME_ME_SAFE             (1U << 2)
-#define SPC5_ME_ME_DRUN             (1U << 3)
-#define SPC5_ME_ME_RUN0             (1U << 4)
-#define SPC5_ME_ME_RUN1             (1U << 5)
-#define SPC5_ME_ME_RUN2             (1U << 6)
-#define SPC5_ME_ME_RUN3             (1U << 7)
-#define SPC5_ME_ME_HALT0            (1U << 8)
-#define SPC5_ME_ME_STOP0            (1U << 10)
-/** @} */
-
-/**
- * @name    ME_xxx_MC registers bits definitions
- * @{
- */
-#define SPC5_ME_MC_SYSCLK_MASK      (15U << 0)
-#define SPC5_ME_MC_SYSCLK(n)        ((n) << 0)
-#define SPC5_ME_MC_SYSCLK_IRC       SPC5_ME_MC_SYSCLK(0)
-#define SPC5_ME_MC_SYSCLK_XOSC      SPC5_ME_MC_SYSCLK(2)
-#define SPC5_ME_MC_SYSCLK_FMPLL0    SPC5_ME_MC_SYSCLK(4)
-#define SPC5_ME_MC_SYSCLK_FMPLL1    SPC5_ME_MC_SYSCLK(5)
-#define SPC5_ME_MC_SYSCLK_DISABLED  SPC5_ME_MC_SYSCLK(15)
-#define SPC5_ME_MC_IRCON            (1U << 4)
-#define SPC5_ME_MC_XOSC0ON          (1U << 5)
-#define SPC5_ME_MC_PLL0ON           (1U << 6)
-#define SPC5_ME_MC_PLL1ON           (1U << 7)
-#define SPC5_ME_MC_CFLAON_MASK      (3U << 16)
-#define SPC5_ME_MC_CFLAON(n)        ((n) << 16)
-#define SPC5_ME_MC_CFLAON_PD        (1U << 16)
-#define SPC5_ME_MC_CFLAON_LP        (2U << 16)
-#define SPC5_ME_MC_CFLAON_NORMAL    (3U << 16)
-#define SPC5_ME_MC_DFLAON_MASK      (3U << 18)
-#define SPC5_ME_MC_DFLAON(n)        ((n) << 18)
-#define SPC5_ME_MC_DFLAON_PD        (1U << 18)
-#define SPC5_ME_MC_DFLAON_LP        (2U << 18)
-#define SPC5_ME_MC_DFLAON_NORMAL    (3U << 18)
-#define SPC5_ME_MC_MVRON            (1U << 20)
-#define SPC5_ME_MC_PDO              (1U << 23)
-/** @} */
-
-/**
- * @name    ME_MCTL register bits definitions
- * @{
- */
-#define SPC5_ME_MCTL_KEY            0x5AF0U
-#define SPC5_ME_MCTL_KEY_INV        0xA50FU
-#define SPC5_ME_MCTL_MODE_MASK      (15U << 28)
-#define SPC5_ME_MCTL_MODE(n)        ((n) << 28)
-/** @} */
-
-/**
- * @name    ME_RUN_PCx registers bits definitions
- * @{
- */
-#define SPC5_ME_RUN_PC_TEST         (1U << 1)
-#define SPC5_ME_RUN_PC_SAFE         (1U << 2)
-#define SPC5_ME_RUN_PC_DRUN         (1U << 3)
-#define SPC5_ME_RUN_PC_RUN0         (1U << 4)
-#define SPC5_ME_RUN_PC_RUN1         (1U << 5)
-#define SPC5_ME_RUN_PC_RUN2         (1U << 6)
-#define SPC5_ME_RUN_PC_RUN3         (1U << 7)
-/** @} */
-
-/**
- * @name    ME_LP_PCx registers bits definitions
- * @{
- */
-#define SPC5_ME_LP_PC_HALT0         (1U << 8)
-#define SPC5_ME_LP_PC_STOP0         (1U << 10)
-/** @} */
-
-/**
- * @name    ME_PCTL registers bits definitions
- * @{
- */
-#define SPC5_ME_PCTL_RUN_MASK       (7U << 0)
-#define SPC5_ME_PCTL_RUN(n)         ((n) << 0)
-#define SPC5_ME_PCTL_LP_MASK        (7U << 3)
-#define SPC5_ME_PCTL_LP(n)          ((n) << 3)
-#define SPC5_ME_PCTL_DBG            (1U << 6)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Disables the clocks initialization in the HAL.
- */
-#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
-#define SPC5_NO_INIT                        FALSE
-#endif
-
-/**
- * @brief   Disables the overclock checks.
- */
-#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
-#define SPC5_ALLOW_OVERCLOCK                FALSE
-#endif
-
-/**
- * @brief   Disables the watchdog on start.
- */
-#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
-#define SPC5_DISABLE_WATCHDOG               TRUE
-#endif
-
-/**
- * @brief   FMPLL0 IDF divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=64MHz.
- */
-#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_IDF_VALUE               5
-#endif
-
-/**
- * @brief   FMPLL0 NDIV divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=64MHz.
- */
-#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_NDIV_VALUE              32
-#endif
-
-/**
- * @brief   FMPLL0 ODF divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=64MHz.
- */
-#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_ODF                     SPC5_FMPLL_ODF_DIV4
-#endif
-
-/**
- * @brief   FMPLL1 IDF divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=120MHz.
- */
-#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_IDF_VALUE               5
-#endif
-
-/**
- * @brief   FMPLL1 NDIV divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=120MHz.
- */
-#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_NDIV_VALUE              60
-#endif
-
-/**
- * @brief   FMPLL1 ODF divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=120MHz.
- */
-#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_ODF                     SPC5_FMPLL_ODF_DIV4
-#endif
-
-/**
- * @brief   AUX0 clock source.
- */
-#if !defined(SPC5_AUX0CLK_SRC) || defined(__DOXYGEN__)
-#define SPC5_AUX0CLK_SRC                    SPC5_CGM_SS_FMPLL1
-#endif
-
-/**
- * @brief   Motor Control clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_MCONTROL_DIVIDER_VALUE) || defined(__DOXYGEN__)
-#define SPC5_MCONTROL_DIVIDER_VALUE         2
-#endif
-
-/**
- * @brief   AUX1 clock source.
- * @note    Not configurable, always selects FMPLL1.
- */
-#if !defined(SPC5_AUX1CLK_SRC) || defined(__DOXYGEN__)
-#define SPC5_AUX1CLK_SRC                    0
-#endif
-
-/**
- * @brief   FMPLL1 clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_FMPLL1_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_CLK_DIVIDER_VALUE       2
-#endif
-
-/**
- * @brief   AUX2 clock source.
- */
-#if !defined(SPC5_AUX2CLK_SRC) || defined(__DOXYGEN__)
-#define SPC5_AUX2CLK_SRC                    SPC5_CGM_SS_FMPLL1
-#endif
-
-/**
- * @brief   SP clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_SP_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
-#define SPC5_SP_CLK_DIVIDER_VALUE           2
-#endif
-
-/**
- * @brief   AUX3 clock source.
- */
-#if !defined(SPC5_AUX3CLK_SRC) || defined(__DOXYGEN__)
-#define SPC5_AUX3CLK_SRC                    SPC5_CGM_SS_FMPLL1
-#endif
-
-/**
- * @brief   FR clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_FR_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FR_CLK_DIVIDER_VALUE           2
-#endif
-
-/**
- * @brief   Active run modes in ME_ME register.
- * @note    Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
- *          is no need to specify them.
- */
-#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_ME_BITS                     (SPC5_ME_ME_RUN1 |              \
-                                             SPC5_ME_ME_RUN2 |              \
-                                             SPC5_ME_ME_RUN3 |              \
-                                             SPC5_ME_ME_HALT0 |             \
-                                             SPC5_ME_ME_STOP0)
-#endif
-
-/**
- * @brief   TEST mode settings.
- */
-#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_TEST_MC_BITS                (SPC5_ME_MC_SYSCLK_IRC |        \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   SAFE mode settings.
- */
-#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_SAFE_MC_BITS                (SPC5_ME_MC_PDO)
-#endif
-
-/**
- * @brief   DRUN mode settings.
- */
-#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_DRUN_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN0 mode settings.
- */
-#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN0_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN1 mode settings.
- */
-#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN1_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN2 mode settings.
- */
-#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN2_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN3 mode settings.
- */
-#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN3_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   HALT0 mode settings.
- */
-#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_HALT0_MC_BITS               (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   STOP0 mode settings.
- */
-#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_STOP0_MC_BITS               (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_CFLAON_NORMAL |     \
-                                             SPC5_ME_MC_DFLAON_NORMAL |     \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   Peripheral mode 0 (run mode).
- * @note    Do not change this setting, it is expected to be the "never run"
- *          mode.
- */
-#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC0_BITS                0
-#endif
-
-/**
- * @brief   Peripheral mode 1 (run mode).
- * @note    Do not change this setting, it is expected to be the "always run"
- *          mode.
- */
-#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC1_BITS                (SPC5_ME_RUN_PC_TEST |          \
-                                             SPC5_ME_RUN_PC_SAFE |          \
-                                             SPC5_ME_RUN_PC_DRUN |          \
-                                             SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 2 (run mode).
- * @note    Do not change this setting, it is expected to be the "only during
- *          normal run" mode.
- */
-#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC2_BITS                (SPC5_ME_RUN_PC_DRUN |          \
-                                             SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 3 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC3_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 4 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC4_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 5 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC5_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 6 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC6_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 7 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC7_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 0 (low power mode).
- * @note    Do not change this setting, it is expected to be the "never run"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC0_BITS                 0
-#endif
-
-/**
- * @brief   Peripheral mode 1 (low power mode).
- * @note    Do not change this setting, it is expected to be the "always run"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC1_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 2 (low power mode).
- * @note    Do not change this setting, it is expected to be the "halt only"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC2_BITS                 (SPC5_ME_LP_PC_HALT0)
-#endif
-
-/**
- * @brief   Peripheral mode 3 (low power mode).
- * @note    Do not change this setting, it is expected to be the "stop only"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC3_BITS                 (SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 4 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC4_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 5 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC5_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 6 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC6_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 7 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC7_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   PIT channel 0 IRQ priority.
- * @note    This PIT channel is allocated permanently for system tick
- *          generation.
- */
-#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PIT0_IRQ_PRIORITY              4
-#endif
-
-/**
- * @brief   Clock initialization failure hook.
- * @note    The default is to stop the system and let the RTC restart it.
- * @note    The hook code must not return.
- */
-#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
-#define SPC5_CLOCK_FAILURE_HOOK()           chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(SPC560Pxx_MCUCONF)
-#error "Using a wrong mcuconf.h file, SPC560Pxx_MCUCONF not defined"
-#endif
-
-/* Check on the XOSC frequency.*/
-#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) ||                                  \
-    (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
-#error "invalid SPC5_XOSC_CLK value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_IDF_VALUE.*/
-#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
-#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
-#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
-#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_ODF.*/
-#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
-#define SPC5_FMPLL0_ODF_VALUE    2
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
-#define SPC5_FMPLL0_ODF_VALUE    4
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
-#define SPC5_FMPLL0_ODF_VALUE    8
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
-#define SPC5_FMPLL0_ODF_VALUE    16
-#else
-#error "invalid SPC5_FMPLL0_ODF value specified"
-#endif
-
-/**
- * @brief   SPC5_FMPLL0_VCO_CLK clock point.
- */
-#define SPC5_FMPLL0_VCO_CLK                                                 \
-  ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
-
-/* Check on FMPLL0 VCO output.*/
-#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \
-    (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
-#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
-#endif
-
-/**
- * @brief   SPC5_FMPLL0_CLK clock point.
- */
-#define SPC5_FMPLL0_CLK                                                     \
-  (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
-
-/* Check on SPC5_FMPLL0_CLK.*/
-#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
-#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
-#endif
-
-#if SPC5_HAS_FMPLL1
-/* Check on SPC5_FMPLL1_IDF_VALUE.*/
-#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
-#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL1_NDIV_VALUE.*/
-#if (SPC5_FMPLL1_NDIV_VALUE < 32) || (SPC5_FMPLL1_NDIV_VALUE > 96)
-#error "invalid SPC5_FMPLL1_NDIV_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL1_ODF.*/
-#if (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV2)
-#define SPC5_FMPLL1_ODF_VALUE    2
-#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV4)
-#define SPC5_FMPLL1_ODF_VALUE    4
-#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV8)
-#define SPC5_FMPLL1_ODF_VALUE    8
-#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV16)
-#define SPC5_FMPLL1_ODF_VALUE    16
-#else
-#error "invalid SPC5_FMPLL1_ODF value specified"
-#endif
-
-/**
- * @brief   SPC5_FMPLL1_VCO_CLK clock point.
- */
-#define SPC5_FMPLL1_VCO_CLK                                                 \
-  ((SPC5_XOSC_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
-
-/* Check on FMPLL1 VCO output.*/
-#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \
-    (SPC5_FMPLL1_VCO_CLK > SPC5_FMPLLVCO_MAX)
-#error "SPC5_FMPLL1_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
-#endif
-
-/**
- * @brief   SPC5_FMPLL1_CLK clock point.
- */
-#define SPC5_FMPLL1_CLK                                                     \
-  (SPC5_FMPLL1_VCO_CLK / SPC5_FMPLL1_ODF_VALUE)
-
-/* Check on SPC5_FMPLL1_CLK.*/
-#if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
-#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
-#endif
-#endif /* SPC5_HAS_FMPLL1 */
-
-#if SPC5_HAS_AC0 || defined(__DOXYGEN__)
-/**
- * @brief   AUX0 clock point.
- */
-#if (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
-#define SPC5_AUX0_CLK           SPC5_FMPLL_SRC_IRC
-#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_XOSC
-#define SPC5_AUX0_CLK           SPC5_FMPLL_SRC_XOSC
-#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL0
-#define SPC5_AUX0_CLK           SPC5_FMPLL0_CLK
-#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1
-#define SPC5_AUX0_CLK           SPC5_FMPLL1_CLK
-#else
-#error "invalid SPC5_AUX0CLK_SRC value specified"
-#endif
-
-#if !SPC5_HAS_FMPLL1 && (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1)
-#error "SPC5_AUX0CLK_SRC, FMPLL1 not present"
-#endif
-
-/* Check on the AUX0 divider 0 settings.*/
-#if SPC5_MCONTROL_DIVIDER_VALUE == 0
-#define SPC5_CGM_AC0_DC0        0
-#elif (SPC5_MCONTROL_DIVIDER_VALUE >= 1) && (SPC5_MCONTROL_DIVIDER_VALUE <= 16)
-#define SPC5_CGM_AC0_DC0        ((0x80U | (SPC5_MCONTROL_DIVIDER_VALUE - 1)) << 24)
-#else
-#error "invalid SPC5_MCONTROL_DIVIDER_VALUE value specified"
-#endif
-
-/**
- * @brief   Motor Control clock point.
- */
-#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
-#define SPC5_MCONTROL_CLK       (SPC5_AUX0_CLK / SPC5_MCONTROL_DIVIDER_VALUE)
-#else
-#define SPC5_MCONTROL_CLK       0
-#endif
-#endif /* #if SPC5_HAS_AC0 */
-
-#if SPC5_HAS_AC1 || defined(__DOXYGEN__)
-/**
- * @brief   AUX1 clock point.
- */
-#if (SPC5_AUX1CLK_SRC == 0) || defined(__DOXYGEN__)
-#define SPC5_AUX1_CLK           SPC5_FMPLL1_CLK
-#else
-#error "invalid SPC5_AUX1CLK_SRC value specified"
-#endif
-
-#if !SPC5_HAS_FMPLL1
-#error "SPC5_AUX1_CLK, FMPLL1 not present"
-#endif
-
-/* Check on the AUX1 divider 0 settings.*/
-#if SPC5_FMPLL1_CLK_DIVIDER_VALUE == 0
-#define SPC5_CGM_AC1_DC0        0
-#elif (SPC5_FMPLL1_CLK_DIVIDER_VALUE >= 1) && (SPC5_FMPLL1_CLK_DIVIDER_VALUE <= 16)
-#define SPC5_CGM_AC1_DC0        ((0x80U | (SPC5_FMPLL1_CLK_DIVIDER_VALUE - 1)) << 24)
-#else
-#error "invalid SPC5_FMPLL1_CLK_DIVIDER_VALUE value specified"
-#endif
-
-/**
- * @brief   FMPLL1 clock point.
- */
-#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
-#define SPC5_FMPLL1_DIV_CLK     (SPC5_AUX1_CLK / SPC5_FMPLL1_CLK_DIVIDER_VALUE)
-#else
-#define SPC5_FMPLL1_DIV_CLK     0
-#endif
-#endif /* SPC5_HAS_AC1 */
-
-#if SPC5_HAS_AC2 || defined(__DOXYGEN__)
-/**
- * @brief   AUX2 clock point.
- */
-#if (SPC5_AUX2CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
-#define SPC5_AUX2_CLK           SPC5_FMPLL_SRC_IRC
-#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_XOSC
-#define SPC5_AUX2_CLK           SPC5_FMPLL_SRC_XOSC
-#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL0
-#define SPC5_AUX2_CLK           SPC5_FMPLL0_CLK
-#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1
-#define SPC5_AUX2_CLK           SPC5_FMPLL1_CLK
-#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
-#define SPC5_AUX2_CLK           SPC5_FMPLL1_1D1_CLK
-#else
-#error "invalid SPC5_AUX2CLK_SRC value specified"
-#endif
-
-#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1) ||           \
-                         (SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1_1D1))
-#error "SPC5_AUX2_CLK, FMPLL1 not present"
-#endif
-
-/* Check on the AUX2 divider 0 settings.*/
-#if SPC5_SP_CLK_DIVIDER_VALUE == 0
-#define SPC5_CGM_AC2_DC0        0
-#elif (SPC5_SP_CLK_DIVIDER_VALUE >= 1) && (SPC5_SP_CLK_DIVIDER_VALUE <= 16)
-#define SPC5_CGM_AC2_DC0        ((0x80U | (SPC5_SP_CLK_DIVIDER_VALUE - 1)) << 24)
-#else
-#error "invalid SPC5_SP_CLK_DIVIDER_VALUE value specified"
-#endif
-
-/**
- * @brief   SP clock point.
- */
-#if (SPC5_SP_CLK_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
-#define SPC5_SP_CLK             (SPC5_AUX2_CLK / SPC5_SP_CLK_DIVIDER_VALUE)
-#else
-#define SPC5_SP_CLK             0
-#endif
-#endif /* SPC5_HAS_AC2 */
-
-#if SPC5_HAS_AC3 || defined(__DOXYGEN__)
-/**
- * @brief   AUX3 clock point.
- */
-#if (SPC5_AUX3CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
-#define SPC5_AUX3_CLK           SPC5_FMPLL_SRC_IRC
-#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_XOSC
-#define SPC5_AUX3_CLK           SPC5_FMPLL_SRC_XOSC
-#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL0
-#define SPC5_AUX3_CLK           SPC5_FMPLL0_CLK
-#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL1
-#define SPC5_AUX3_CLK           SPC5_FMPLL1_CLK
-#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
-#define SPC5_AUX3_CLK           SPC5_FMPLL1_1D1_CLK
-#else
-#error "invalid SPC5_AUX3CLK_SRC value specified"
-#endif
-
-#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_AUX3_CLK) ||           \
-                         (SPC5_AUX3_CLK == SPC5_CGM_SS_FMPLL1_1D1))
-#error "SPC5_AUX3_CLK, FMPLL1 not present"
-#endif
-
-/* Check on the AUX3 divider 0 settings.*/
-#if SPC5_FR_CLK_DIVIDER_VALUE == 0
-#define SPC5_CGM_AC3_DC0        0
-#elif (SPC5_FR_CLK_DIVIDER_VALUE >= 1) && (SPC5_FR_CLK_DIVIDER_VALUE <= 16)
-#define SPC5_CGM_AC3_DC0        ((0x80U | (SPC5_FR_CLK_DIVIDER_VALUE - 1)) << 24)
-#else
-#error "invalid SPC5_FR_CLK_DIVIDER_VALUE value specified"
-#endif
-
-/**
- * @brief   FR clock point.
- */
-#if (SPC5_FR_CLK_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
-#define SPC5_FR_CLK             (SPC5_AUX3_CLK / SPC5_FR_CLK_DIVIDER_VALUE)
-#else
-#define SPC5_FR_CLK             0
-#endif
-#endif /* SPC5_HAS_AC3 */
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-typedef enum {
-  SPC5_RUNMODE_TEST  = 1,
-  SPC5_RUNMODE_SAFE  = 2,
-  SPC5_RUNMODE_DRUN  = 3,
-  SPC5_RUNMODE_RUN0  = 4,
-  SPC5_RUNMODE_RUN1  = 5,
-  SPC5_RUNMODE_RUN2  = 6,
-  SPC5_RUNMODE_RUN3  = 7,
-  SPC5_RUNMODE_HALT0 = 8,
-  SPC5_RUNMODE_STOP0 = 10
-} spc5_runmode_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#include "spc5_edma.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void spc_clock_init(void);
-  bool_t halSPCSetRunMode(spc5_runmode_t mode);
-  void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
-#if !SPC5_NO_INIT
-  uint32_t halSPCGetSystemClock(void);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560Pxx/platform.mk b/os/hal/platforms/SPC560Pxx/platform.mk
deleted file mode 100644
index 2e82732d1..000000000
--- a/os/hal/platforms/SPC560Pxx/platform.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# List of all the SPC560Pxx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1
diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h
deleted file mode 100644
index a99413952..000000000
--- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560Pxx/spc560p_registry.h
- * @brief   SPC560Pxx capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _SPC560P_REGISTRY_H_
-#define _SPC560P_REGISTRY_H_
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if defined(_SPC560P34L1_) || defined(_SPC560P34L3_)
-#define _SPC560P34_
-#define _SPC560PXX_SMALL_
-#elif defined(_SPC560P40L1_) || defined(_SPC560P40L3_)
-#define _SPC560P40_
-#define _SPC560PXX_SMALL_
-#elif defined(_SPC560P44L3_) || defined(_SPC560P44L5_)
-#define _SPC560P44_
-#define _SPC560PXX_MEDIUM_
-#elif defined(_SPC560P50L3_) || defined(_SPC560P50L5_)
-#define _SPC560P50_
-#define _SPC560PXX_MEDIUM_
-#elif defined(_SPC560P54L5_) || defined(_SPC56AP54L3_) || defined(_SPC56AP54L5_)
-#define _SPC560P54_
-#define _SPC560PXX_LARGE_
-#elif defined(_SPC560P60L5_) || defined(_SPC56AP60L3_) || defined(_SPC56AP60L5_)
-#define _SPC560P60_
-#define _SPC560PXX_LARGE_
-#else
-#error "SPC56xPxx platform not defined"
-#endif
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    SPC560Pxx capabilities
- * @{
- */
-/* Clock attributes.*/
-#if defined(_SPC560PXX_SMALL_)
-#define SPC5_HAS_FMPLL1                     FALSE
-#define SPC5_HAS_CLOCKOUT                   TRUE
-#define SPC5_HAS_AC0                        FALSE
-#define SPC5_HAS_AC1                        FALSE
-#define SPC5_HAS_AC2                        FALSE
-#define SPC5_HAS_AC3                        FALSE
-
-#elif defined(_SPC560PXX_MEDIUM_)
-#define SPC5_HAS_FMPLL1                     TRUE
-#define SPC5_HAS_CLOCKOUT                   TRUE
-#define SPC5_HAS_AC0                        TRUE
-#define SPC5_HAS_AC1                        TRUE
-#define SPC5_HAS_AC2                        TRUE
-#define SPC5_HAS_AC3                        TRUE
-
-#else /* defined(_SPC560PXX_LARGE_) */
-#define SPC5_HAS_FMPLL1                     FALSE
-#define SPC5_HAS_CLOCKOUT                   TRUE
-#define SPC5_HAS_AC0                        FALSE
-#define SPC5_HAS_AC1                        FALSE
-#define SPC5_HAS_AC2                        FALSE
-#define SPC5_HAS_AC3                        TRUE
-#endif
-
-/* DSPI attribures.*/
-#define SPC5_HAS_DSPI0                      TRUE
-#define SPC5_HAS_DSPI1                      TRUE
-#define SPC5_HAS_DSPI2                      TRUE
-#define SPC5_DSPI_FIFO_DEPTH                5
-#define SPC5_DSPI0_PCTL                     4
-#define SPC5_DSPI1_PCTL                     5
-#define SPC5_DSPI2_PCTL                     6
-#define SPC5_DSPI0_TX1_DMA_DEV_ID           1
-#define SPC5_DSPI0_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI0_RX_DMA_DEV_ID            2
-#define SPC5_DSPI1_TX1_DMA_DEV_ID           3
-#define SPC5_DSPI1_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI1_RX_DMA_DEV_ID            4
-#define SPC5_DSPI2_TX1_DMA_DEV_ID           5
-#define SPC5_DSPI2_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI2_RX_DMA_DEV_ID            6
-#define SPC5_DSPI0_TFFF_HANDLER             vector76
-#define SPC5_DSPI0_TFFF_NUMBER              76
-#define SPC5_DSPI1_TFFF_HANDLER             vector96
-#define SPC5_DSPI1_TFFF_NUMBER              96
-#define SPC5_DSPI2_TFFF_HANDLER             vector116
-#define SPC5_DSPI2_TFFF_NUMBER              116
-#define SPC5_DSPI0_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
-#define SPC5_DSPI0_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
-#define SPC5_DSPI1_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
-#define SPC5_DSPI1_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
-#define SPC5_DSPI2_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
-#define SPC5_DSPI2_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
-
-#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
-#define SPC5_HAS_DSPI3                      TRUE
-#define SPC5_DSPI3_PCTL                     7
-#define SPC5_DSPI3_TX1_DMA_DEV_ID           7
-#define SPC5_DSPI3_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI3_RX_DMA_DEV_ID            8
-#define SPC5_DSPI3_TFFF_HANDLER             vector219
-#define SPC5_DSPI3_TFFF_NUMBER              219
-#define SPC5_DSPI3_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_START_PCTL)
-#define SPC5_DSPI3_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_STOP_PCTL)
-#else
-#define SPC5_HAS_DSPI3                      FALSE
-#endif
-
-#if defined(_SPC560PXX_LARGE_)
-#define SPC5_HAS_DSPI4                      TRUE
-#define SPC5_DSPI4_PCTL                     8
-#define SPC5_DSPI4_TX1_DMA_DEV_ID           15
-#define SPC5_DSPI4_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI4_RX_DMA_DEV_ID            21
-#define SPC5_DSPI4_TFFF_HANDLER             vector258
-#define SPC5_DSPI4_TFFF_NUMBER              258
-#define SPC5_DSPI4_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_START_PCTL)
-#define SPC5_DSPI4_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI4_STOP_PCTL)
-#else
-#define SPC5_HAS_DSPI4                      FALSE
-#endif
-
-/* eDMA attributes.*/
-#define SPC5_HAS_EDMA                       TRUE
-#define SPC5_EDMA_NCHANNELS                 16
-#define SPC5_EDMA_HAS_MUX                   TRUE
-
-/* LINFlex attributes.*/
-#define SPC5_HAS_LINFLEX0                   TRUE
-#define SPC5_LINFLEX0_PCTL                  48
-#define SPC5_LINFLEX0_RXI_HANDLER           vector79
-#define SPC5_LINFLEX0_TXI_HANDLER           vector80
-#define SPC5_LINFLEX0_ERR_HANDLER           vector81
-#define SPC5_LINFLEX0_RXI_NUMBER            79
-#define SPC5_LINFLEX0_TXI_NUMBER            80
-#define SPC5_LINFLEX0_ERR_NUMBER            81
-#define SPC5_LINFLEX0_CLK                   (halSPCGetSystemClock() / 1)
-
-#define SPC5_HAS_LINFLEX1                   TRUE
-#define SPC5_LINFLEX1_PCTL                  49
-#define SPC5_LINFLEX1_RXI_HANDLER           vector99
-#define SPC5_LINFLEX1_TXI_HANDLER           vector100
-#define SPC5_LINFLEX1_ERR_HANDLER           vector101
-#define SPC5_LINFLEX1_RXI_NUMBER            99
-#define SPC5_LINFLEX1_TXI_NUMBER            100
-#define SPC5_LINFLEX1_ERR_NUMBER            101
-#define SPC5_LINFLEX1_CLK                   (halSPCGetSystemClock() / 1)
-
-#define SPC5_HAS_LINFLEX2                   FALSE
-
-#define SPC5_HAS_LINFLEX3                   FALSE
-
-/* SIUL attributes.*/
-#define SPC5_HAS_SIUL                       TRUE
-#define SPC5_SIUL_NUM_PORTS                 8
-#if defined(_SPC560PXX_SMALL_)
-#define SPC5_SIUL_NUM_PCRS                  72
-#else
-#define SPC5_SIUL_NUM_PCRS                  108
-#endif
-#define SPC5_SIUL_NUM_PADSELS               36
-
-/* FlexPWM attributes.*/
-#if defined(_SPC560PXX_SMALL_) || defined(_SPC560PXX_MEDIUM_)
-#define SPC5_HAS_FLEXPWM0                   TRUE
-#define SPC5_FLEXPWM0_PCTL                  41
-#define SPC5_FLEXPWM0_RF0_HANDLER           vector179
-#define SPC5_FLEXPWM0_COF0_HANDLER          vector180
-#define SPC5_FLEXPWM0_CAF0_HANDLER          vector181
-#define SPC5_FLEXPWM0_RF1_HANDLER           vector182
-#define SPC5_FLEXPWM0_COF1_HANDLER          vector183
-#define SPC5_FLEXPWM0_CAF1_HANDLER          vector184
-#define SPC5_FLEXPWM0_RF2_HANDLER           vector185
-#define SPC5_FLEXPWM0_COF2_HANDLER          vector186
-#define SPC5_FLEXPWM0_CAF2_HANDLER          vector187
-#define SPC5_FLEXPWM0_RF3_HANDLER           vector188
-#define SPC5_FLEXPWM0_COF3_HANDLER          vector189
-#define SPC5_FLEXPWM0_CAF3_HANDLER          vector190
-#define SPC5_FLEXPWM0_FFLAG_HANDLER         vector191
-#define SPC5_FLEXPWM0_REF_HANDLER           vector192
-#define SPC5_FLEXPWM0_RF0_NUMBER            179
-#define SPC5_FLEXPWM0_COF0_NUMBER           180
-#define SPC5_FLEXPWM0_CAF0_NUMBER           181
-#define SPC5_FLEXPWM0_RF1_NUMBER            182
-#define SPC5_FLEXPWM0_COF1_NUMBER           183
-#define SPC5_FLEXPWM0_CAF1_NUMBER           184
-#define SPC5_FLEXPWM0_RF2_NUMBER            185
-#define SPC5_FLEXPWM0_COF2_NUMBER           186
-#define SPC5_FLEXPWM0_CAF2_NUMBER           187
-#define SPC5_FLEXPWM0_RF3_NUMBER            188
-#define SPC5_FLEXPWM0_COF3_NUMBER           189
-#define SPC5_FLEXPWM0_CAF3_NUMBER           190
-#define SPC5_FLEXPWM0_FFLAG_NUMBER          191
-#define SPC5_FLEXPWM0_REF_NUMBER            192
-#define SPC5_FLEXPWM0_CLK                   SPC5_MCONTROL_CLK
-#else /* defined(_SPC560PXX_LARGE_) */
-#define SPC5_HAS_FLEXPWM0                   FALSE
-#endif /* defined(_SPC560PXX_LARGE_) */
-
-#define SPC5_HAS_FLEXPWM1                   FALSE
-
-/* eTimer attributes.*/
-#define SPC5_HAS_ETIMER0                    TRUE
-#define SPC5_ETIMER0_PCTL                   38
-#define SPC5_ETIMER0_TC0IR_HANDLER          vector157
-#define SPC5_ETIMER0_TC1IR_HANDLER          vector158
-#define SPC5_ETIMER0_TC2IR_HANDLER          vector159
-#define SPC5_ETIMER0_TC3IR_HANDLER          vector160
-#define SPC5_ETIMER0_TC4IR_HANDLER          vector161
-#define SPC5_ETIMER0_TC5IR_HANDLER          vector162
-#define SPC5_ETIMER0_WTIF_HANDLER           vector165
-#define SPC5_ETIMER0_RCF_HANDLER            vector167
-#define SPC5_ETIMER0_TC0IR_NUMBER           157
-#define SPC5_ETIMER0_TC1IR_NUMBER           158
-#define SPC5_ETIMER0_TC2IR_NUMBER           159
-#define SPC5_ETIMER0_TC3IR_NUMBER           160
-#define SPC5_ETIMER0_TC4IR_NUMBER           161
-#define SPC5_ETIMER0_TC5IR_NUMBER           162
-#define SPC5_ETIMER0_WTIF_NUMBER            165
-#define SPC5_ETIMER0_RCF_NUMBER             167
-#define SPC5_ETIMER0_CLK                    SPC5_MCONTROL_CLK
-
-#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
-#define SPC5_HAS_ETIMER1                    TRUE
-#define SPC5_ETIMER1_PCTL                   39
-#define SPC5_ETIMER1_TC0IR_HANDLER          vector168
-#define SPC5_ETIMER1_TC1IR_HANDLER          vector169
-#define SPC5_ETIMER1_TC2IR_HANDLER          vector170
-#define SPC5_ETIMER1_TC3IR_HANDLER          vector171
-#define SPC5_ETIMER1_TC4IR_HANDLER          vector172
-#define SPC5_ETIMER1_TC5IR_HANDLER          vector173
-#define SPC5_ETIMER1_RCF_HANDLER            vector178
-#define SPC5_ETIMER1_TC0IR_NUMBER           168
-#define SPC5_ETIMER1_TC1IR_NUMBER           169
-#define SPC5_ETIMER1_TC2IR_NUMBER           170
-#define SPC5_ETIMER1_TC3IR_NUMBER           171
-#define SPC5_ETIMER1_TC4IR_NUMBER           172
-#define SPC5_ETIMER1_TC5IR_NUMBER           173
-#define SPC5_ETIMER1_RCF_NUMBER             178
-#define SPC5_ETIMER1_CLK                    SPC5_MCONTROL_CLK
-
-#else /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
-#define SPC5_HAS_ETIMER1                    FALSE
-#endif /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
-
-#define SPC5_HAS_ETIMER2                    FALSE
-
-/* FlexCAN attributes.*/
-#define SPC5_HAS_FLEXCAN0                                   TRUE
-#define SPC5_FLEXCAN0_PCTL                                  16
-#define SPC5_FLEXCAN0_MB                                    32
-#define SPC5_FLEXCAN0_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER           vector65
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER              vector66
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER               vector67
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER             vector68
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER             vector69
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER             vector70
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER             vector71
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER             vector72
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER            65
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER               66
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER                67
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER              68
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER              69
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER              70
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER              71
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER              72
-#define SPC5_FLEXCAN0_ENABLE_CLOCK()                                        \
-  halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL)
-#define SPC5_FLEXCAN0_DISABLE_CLOCK()                                       \
-  halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL)
-/** @} */
-
-#endif /* _SPC560P_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC560Pxx/typedefs.h b/os/hal/platforms/SPC560Pxx/typedefs.h
deleted file mode 100644
index 9393cb167..000000000
--- a/os/hal/platforms/SPC560Pxx/typedefs.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC560Pxx/typedefs.h
- * @brief   Dummy typedefs file.
- */
-
-#ifndef _TYPEDEFS_H_
-#define _TYPEDEFS_H_
-
-#include "chtypes.h"
-
-#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/platforms/SPC560Pxx/xpc560p.h b/os/hal/platforms/SPC560Pxx/xpc560p.h
deleted file mode 100644
index 76ea503ca..000000000
--- a/os/hal/platforms/SPC560Pxx/xpc560p.h
+++ /dev/null
@@ -1,7801 +0,0 @@
-/***************************************************************** 
- * PROJECT     : MPC5604P
- * FILE        : 5604P_Header_v1_10.h
- * 
- * DESCRIPTION : This is the header file describing the register
- *               set for the named projects. 
- * 
- * COPYRIGHT   :(c) 2012, Freescale
- * 
- * VERSION	   : 01.10
- * DATE	   : 12.06.2012  
- * AUTHOR       : B16991
- * HISTORY     : Changes: typo fixed in PSR1 register:SCP -> CSP, MCR: PRESCALE->BITRATE (b16991)
- * HISTORY     : Changes: typo fixed in ME register MTC bit, SSCM fix, CMU changes(b16991)
- * HISTORY     : Changes to CTU Module:  CR register (LC->FC), CLR changed to 24 bits  (b16991)
- * HISTORY      : Modified to add reserved space in CTU (b16991)
- * HISTORY      :  Modified to support ADC on Pictus cut 2 - do not distribute! (ttz778)
- * HISTORY      :  Modified to support CRC on Pictus cut 2 - do not distribute! (r60321)
- * HISTORY      :  Modified to support DSPI0 CS7&8 and new FlexPWM naming on Pictus cut 2 (r60321)
- * HISTORY      :  Modified to update MIDR1&2 registers and LINCR1-SFTM and LINESR-BDEF bit on Pictus (r60321)
- * HISTORY      :  Modified to update RGM, CFLASH & DFLASH registers and FlexCAN & CTU Registers on Pictus (r60321)
- * HISTORY      :  Modified to update DSPI Registers (FIFO deep) on Pictus  (b16991)
- *
- ***************************************************************** 
- * Copyright:
- *	Freescale Semiconductor, INC. All Rights Reserved.
- *  You are hereby granted a copyright license to use, modify, and
- *  distribute the SOFTWARE so long as this entire notice is
- *  retained without alteration in any modified and/or redistributed
- *  versions, and that such modified versions are clearly identified
- *  as such. No licenses are granted by implication, estoppel or
- *  otherwise under any patents or trademarks of Freescale
- *  Semiconductor, Inc. This software is provided on an "AS IS"
- *  basis and without warranty.
- *
- *  To the maximum extent permitted by applicable law, Freescale
- *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
- *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
- *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
- *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
- *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
- *
- *  To the maximum extent permitted by applicable law, IN NO EVENT
- *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
- *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
- *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
- *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
- *
- *  Freescale Semiconductor assumes no responsibility for the
- *  maintenance and support of this software
- *
- ******************************************************************/
-/***************************************************************** 
-* Example instantiation and use:            
-*                                           
-*  <MODULE>.<REGISTER>.B.<BIT> = 1;         
-*  <MODULE>.<REGISTER>.R       = 0x10000000;
-*                                           
-******************************************************************/
-
-#ifndef _JDP_H_
-#define _JDP_H_
-
-#include "typedefs.h"
-
-#ifdef  __cplusplus
-extern "C" {
-#endif
-
-#ifdef __MWERKS__
-#pragma push
-#pragma ANSI_strict off
-#endif
-/****************************************************************************/
-/*                          MODULE : ADC                                   */
-/****************************************************************************/
-    struct ADC_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t OWREN:1;
-                vuint32_t WLSIDE:1;
-                vuint32_t MODE:1;
-                vuint32_t EDGLEV:1;
-                vuint32_t TRGEN:1;
-                vuint32_t EDGE:1;
-                vuint32_t XSTRTEN:1;
-                vuint32_t NSTART:1;
-                vuint32_t:1;
-                vuint32_t JTRGEN:1;
-                vuint32_t JEDGE:1;
-                vuint32_t JSTART:1;
-                vuint32_t:2;
-                vuint32_t CTUEN:1;
-                vuint32_t:8;
-                vuint32_t ADCLKSEL:1;
-                vuint32_t ABORTCHAIN:1;
-                vuint32_t ABORT:1;
-                vuint32_t ACK0:1;
-                vuint32_t OFFREFRESH:1;
-                vuint32_t OFFCANC:1;
-                vuint32_t:2;
-                vuint32_t PWDN:1;
-            } B;
-        } MCR;                 /* MAIN CONFIGURATION REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:7;
-                vuint32_t NSTART:1;
-                vuint32_t JABORT:1;
-                vuint32_t:2;
-                vuint32_t JSTART:1;
-                vuint32_t:3;
-                vuint32_t CTUSTART:1;
-                vuint32_t CHADDR:7;
-                vuint32_t:3;
-                vuint32_t ACK0:1;
-                vuint32_t OFFREFRESH:1;
-                vuint32_t OFFCANC:1;
-                vuint32_t ADCSTATUS:3;
-            } B;
-        } MSR;                 /* MAIN STATUS REGISTER */
-
-        int32_t ADC_reserved1[2];       /* (0x008 - 0x00F)/4 = 0x02 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:25;
-                vuint32_t OFFCANCOVR:1;
-                vuint32_t EOFFSET:1;
-                vuint32_t EOCTU:1;
-                vuint32_t JEOC:1;
-                vuint32_t JECH:1;
-                vuint32_t EOC:1;
-                vuint32_t ECH:1;
-            } B;
-        } ISR;                 /* INTERRUPT STATUS REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EOC31:1;
-                vuint32_t EOC30:1;
-                vuint32_t EOC29:1;
-                vuint32_t EOC28:1;
-                vuint32_t EOC27:1;
-                vuint32_t EOC26:1;
-                vuint32_t EOC25:1;
-                vuint32_t EOC24:1;
-                vuint32_t EOC23:1;
-                vuint32_t EOC22:1;
-                vuint32_t EOC21:1;
-                vuint32_t EOC20:1;
-                vuint32_t EOC19:1;
-                vuint32_t EOC18:1;
-                vuint32_t EOC17:1;
-                vuint32_t EOC16:1;
-                vuint32_t EOC15:1;
-                vuint32_t EOC14:1;
-                vuint32_t EOC13:1;
-                vuint32_t EOC12:1;
-                vuint32_t EOC11:1;
-                vuint32_t EOC10:1;
-                vuint32_t EOC9:1;
-                vuint32_t EOC8:1;
-                vuint32_t EOC7:1;
-                vuint32_t EOC6:1;
-                vuint32_t EOC5:1;
-                vuint32_t EOC4:1;
-                vuint32_t EOC3:1;
-                vuint32_t EOC2:1;
-                vuint32_t EOC1:1;
-                vuint32_t EOC0:1;
-            } B;
-        } CEOCFR[3];                 /* Channel Pending Register 0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:25;			//One bit added
-                vuint32_t MSKOFFCANCOVR:1;	//Moved up
-                vuint32_t MSKEOFFSET:1;		//Moved up
-                vuint32_t MSKEOCTU:1;		//New for cut 2
-                vuint32_t MSKJEOC:1;
-                vuint32_t MSKJECH:1;
-                vuint32_t MSKEOC:1;
-                vuint32_t MSKECH:1;
-            } B;
-        } IMR;                  /* INTERRUPT MASK REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CIM31:1;
-                vuint32_t CIM30:1;
-                vuint32_t CIM29:1;
-                vuint32_t CIM28:1;
-                vuint32_t CIM27:1;
-                vuint32_t CIM26:1;
-                vuint32_t CIM25:1;
-                vuint32_t CIM24:1;
-                vuint32_t CIM23:1;
-                vuint32_t CIM22:1;
-                vuint32_t CIM21:1;
-                vuint32_t CIM20:1;
-                vuint32_t CIM19:1;
-                vuint32_t CIM18:1;
-                vuint32_t CIM17:1;
-                vuint32_t CIM16:1;
-                vuint32_t CIM15:1;
-                vuint32_t CIM14:1;
-                vuint32_t CIM13:1;
-                vuint32_t CIM12:1;
-                vuint32_t CIM11:1;
-                vuint32_t CIM10:1;
-                vuint32_t CIM9:1;
-                vuint32_t CIM8:1;
-                vuint32_t CIM7:1;
-                vuint32_t CIM6:1;
-                vuint32_t CIM5:1;
-                vuint32_t CIM4:1;
-                vuint32_t CIM3:1;
-                vuint32_t CIM2:1;
-                vuint32_t CIM1:1;
-                vuint32_t CIM0:1;
-            } B;
-        } CIMR[3];                 /* Channel Interrupt Mask Register 0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t WDG3H:1;
-                vuint32_t WDG2H:1;
-                vuint32_t WDG1H:1;
-                vuint32_t WDG0H:1;
-                vuint32_t WDG3L:1;
-                vuint32_t WDG2L:1;
-                vuint32_t WDG1L:1;
-                vuint32_t WDG0L:1;
-            } B;
-        } WTISR;               /* WATCHDOG INTERRUPT THRESHOLD REGISTER was WDGTHR */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t MSKWDG3H:1;
-                vuint32_t MSKWDG2H:1;
-                vuint32_t MSKWDG1H:1;
-                vuint32_t MSKWDG0H:1;
-                vuint32_t MSKWDG3L:1;
-                vuint32_t MSKWDG2L:1;
-                vuint32_t MSKWDG1L:1;
-                vuint32_t MSKWDG0L:1;
-            } B;
-        } WTIMR;             /* WATCHDOG INTERRUPT MASK REGISTER was IMWDGTHR */
-
-        int32_t ADC_reserved2[2];       /* (0x038 - 0x03F)/4 = 0x02 */
-
-	union {
-            vuint32_t R;
-            struct {
-                vuint32_t:30;			//was 16
-                vuint32_t DCLR:1;		//moved
-                vuint32_t DMAEN:1;		//moved
-            } B;
-        } DMAE;                 /* DMAE REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DMA31:1;	//was unused [16]
-                vuint32_t DMA30:1;
-                vuint32_t DMA29:1;
-                vuint32_t DMA28:1;
-                vuint32_t DMA27:1;
-                vuint32_t DMA26:1;
-                vuint32_t DMA25:1;
-                vuint32_t DMA24:1;
-                vuint32_t DMA23:1;
-                vuint32_t DMA22:1;
-                vuint32_t DMA21:1;
-                vuint32_t DMA20:1;
-                vuint32_t DMA19:1;
-                vuint32_t DMA18:1;
-                vuint32_t DMA17:1;
-                vuint32_t DMA16:1;
-                vuint32_t DMA15:1;
-                vuint32_t DMA14:1;
-                vuint32_t DMA13:1;
-                vuint32_t DMA12:1;
-                vuint32_t DMA11:1;
-                vuint32_t DMA10:1;
-                vuint32_t DMA9:1;
-                vuint32_t DMA8:1;
-                vuint32_t DMA7:1;
-                vuint32_t DMA6:1;
-                vuint32_t DMA5:1;
-                vuint32_t DMA4:1;
-                vuint32_t DMA3:1;
-                vuint32_t DMA2:1;
-                vuint32_t DMA1:1;
-                vuint32_t DMA0:1;
-            } B;
-        } DMAR[3];              /* DMA REGISTER  was [6] */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t THREN:1;
-                vuint32_t THRINV:1;
-                vuint32_t THROP:1;
-                  vuint32_t:6;
-                vuint32_t THRCH:7;
-            } B;
-        } TRC[4];               /* ADC THRESHOLD REGISTER REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {		//were in TRA & TRB
-                vuint32_t:4;
-                vuint32_t THRH:12;
-                vuint32_t:4;
-                vuint32_t THRL:12;
-            } B;
-        } THRHLR[4];               /* THRESHOLD REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {		//were in TRAALT & TRBALT
-                vuint32_t:4;
-                vuint32_t THRH:12;
-                vuint32_t:4;
-                vuint32_t THRL:12;
-            } B;
-        } THRALT[4];            /* ADC THRESHOLD REGISTER REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:25;		//was 26
-                vuint32_t PREVAL2:2;	
-                vuint32_t PREVAL1:2;
-                vuint32_t PREVAL0:2;
-                vuint32_t PREONCE:1;
-            } B;
-        } PSCR;               /* PRESAMPLING CONTROL REGISTER was PREREG */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRES31:1;	//was reserved 16
-                vuint32_t PRES30:1;
-                vuint32_t PRES29:1;
-                vuint32_t PRES28:1;
-                vuint32_t PRES27:1;
-                vuint32_t PRES26:1;
-                vuint32_t PRES25:1;
-                vuint32_t PRES24:1;
-                vuint32_t PRES23:1;
-                vuint32_t PRES22:1;
-                vuint32_t PRES21:1;
-                vuint32_t PRES20:1;
-                vuint32_t PRES19:1;
-                vuint32_t PRES18:1;
-                vuint32_t PRES17:1;
-                vuint32_t PRES16:1;
-                vuint32_t PRES15:1;
-                vuint32_t PRES14:1;
-                vuint32_t PRES13:1;
-                vuint32_t PRES12:1;
-                vuint32_t PRES11:1;
-                vuint32_t PRES10:1;
-                vuint32_t PRES9:1;
-                vuint32_t PRES8:1;
-                vuint32_t PRES7:1;
-                vuint32_t PRES6:1;
-                vuint32_t PRES5:1;
-                vuint32_t PRES4:1;
-                vuint32_t PRES3:1;
-                vuint32_t PRES2:1;
-                vuint32_t PRES1:1;
-                vuint32_t PRES0:1;
-            } B;
-        } PSR[3];              /* PRESAMPLING REGISTER was PRER[6]*/
-
-        int32_t ADC_reserved3[1];       /* (0x090 - 0x093)/4 = 0x01 */
-
-	union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t INPLATCH:1;
-                  vuint32_t:1;
-                vuint32_t OFFSHIFT:2;		//!!! This field only in CTR[0]
-                  vuint32_t:1;
-                vuint32_t INPCMP:2;
-                  vuint32_t:1;
-                vuint32_t INPSAMP:8;
-            } B;
-        } CTR[3];                /* CONVERSION TIMING REGISTER was CT[3] */
-
-        int32_t ADC_reserved4[1];       /* (0x0A0 - 0x0A3)/4 = 0x01 */
-
-	union {
-            vuint32_t R;
-            struct {
-                vuint32_t CH31:1;		//was reserved 16
-                vuint32_t CH30:1;
-                vuint32_t CH29:1;
-                vuint32_t CH28:1;
-                vuint32_t CH27:1;
-                vuint32_t CH26:1;
-                vuint32_t CH25:1;
-                vuint32_t CH24:1;
-                vuint32_t CH23:1;
-                vuint32_t CH22:1;
-                vuint32_t CH21:1;
-                vuint32_t CH20:1;
-                vuint32_t CH19:1;
-                vuint32_t CH18:1;
-                vuint32_t CH17:1;
-                vuint32_t CH16:1;
-                vuint32_t CH15:1;
-                vuint32_t CH14:1;
-                vuint32_t CH13:1;
-                vuint32_t CH12:1;
-                vuint32_t CH11:1;
-                vuint32_t CH10:1;
-                vuint32_t CH9:1;
-                vuint32_t CH8:1;
-                vuint32_t CH7:1;
-                vuint32_t CH6:1;
-                vuint32_t CH5:1;
-                vuint32_t CH4:1;
-                vuint32_t CH3:1;
-                vuint32_t CH2:1;
-                vuint32_t CH1:1;
-                vuint32_t CH0:1;
-            } B;
-        } NCMR[3];              /* NORMAL CONVERSION MASK REGISTER was [6] */
-
-        int32_t ADC_reserved5[1];       /* (0x0B0 - 0x0B3)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CH31:1;		//was reserved 16
-                vuint32_t CH30:1;
-                vuint32_t CH29:1;
-                vuint32_t CH28:1;
-                vuint32_t CH27:1;
-                vuint32_t CH26:1;
-                vuint32_t CH25:1;
-                vuint32_t CH24:1;
-                vuint32_t CH23:1;
-                vuint32_t CH22:1;
-                vuint32_t CH21:1;
-                vuint32_t CH20:1;
-                vuint32_t CH19:1;
-                vuint32_t CH18:1;
-                vuint32_t CH17:1;
-                vuint32_t CH16:1;
-                vuint32_t CH15:1;
-                vuint32_t CH14:1;
-                vuint32_t CH13:1;
-                vuint32_t CH12:1;
-                vuint32_t CH11:1;
-                vuint32_t CH10:1;
-                vuint32_t CH9:1;
-                vuint32_t CH8:1;
-                vuint32_t CH7:1;
-                vuint32_t CH6:1;
-                vuint32_t CH5:1;
-                vuint32_t CH4:1;
-                vuint32_t CH3:1;
-                vuint32_t CH2:1;
-                vuint32_t CH1:1;
-                vuint32_t CH0:1;
-            } B;
-        } JCMR[3];              /* Injected CONVERSION MASK REGISTER was ICMR[6] */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:15;
-                vuint32_t OFFSETLOAD:1;		//new
-                vuint32_t:8;
-                vuint32_t OFFSETWORD:8;
-            } B;
-        } OFFWR;               /* OFFSET WORD REGISTER was OFFREG*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t DSD:8;
-            } B;
-        } DSDR;                  /* DECODE SIGNALS DELAY REGISTER was DSD */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t PDED:8;	//was PDD
-            } B;
-        } PDEDR;                  /* POWER DOWN DELAY REGISTER was PDD */
-
-        int32_t ADC_reserved6[9];       /* (0x0CC - 0x0EF)/4 = 0x09 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TEST_CTL:32;
-            } B;
-        } TCTLR;                 /* Test control REGISTER */
-
-        int32_t ADC_reserved7[3];       /* (0x0F4 - 0x0FF)/4 = 0x03 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t VALID:1;
-                vuint32_t OVERW:1;
-                vuint32_t RESULT:2;
-                vuint32_t:4;
-                vuint32_t CDATA:12;
-            } B;
-        } CDR[96];      /* Channel 0-95 Data REGISTER */
-
-    };                          /* end of ADC_tag */
-/****************************************************************************/
-/*                          MODULE : CANSP                                   */
-/****************************************************************************/
-    struct CANSP_tag {
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t RX_COMPLETE:1;
-                vuint16_t BUSY:1;
-                vuint16_t ACTIVE_CK:1;
-                  vuint16_t:3;
-                vuint16_t MODE:1;
-                vuint16_t CAN_RX_SEL:3;
-                vuint16_t BRP:5;
-                vuint16_t CAN_SMPLR_EN:1;
-            } B;
-        } CR;                   /* CANSP Control Register */
-
-        int16_t CANSP_reserved;
-
-        union {
-            vuint32_t R;
-        } SR[12];               /* CANSP Sample Register 0 to 11 */
-
-    };                          /* end of CANSP_tag */
-/****************************************************************************/
-/*                          MODULE : MCM                                   */
-/****************************************************************************/
-    struct MCM_tag {
-
-        union {
-            vuint16_t R;
-        } PCT;                  /* MCM Processor Core Type Register */
-
-        union {
-            vuint16_t R;
-        } REV;                  /* MCM  Revision Register */
-
-        int32_t MCM_reserved;
-
-        union {
-            vuint32_t R;
-        } MC;                   /* MCM Configuration Register */
-
-        int8_t MCM_reserved1[3];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t POR:1;
-                vuint8_t DIR:1;
-                  vuint8_t:6;
-            } B;
-        } MRSR;                 /* MCM Miscellaneous Reset Status Register */
-
-        int8_t MCM_reserved2[3];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t ENBWCR:1;
-                  vuint8_t:3;
-                vuint8_t PRILVL:4;
-            } B;
-        } MWCR;                 /* MCM Miscellaneous Wakeup Control Register */
-
-        int32_t MCM_reserved3[2];
-        int8_t MCM_reserved4[3];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t FB0AI:1;
-                vuint8_t FB0SI:1;
-                vuint8_t FB1AI:1;
-                vuint8_t FB1SI:1;
-                  vuint8_t:4;
-            } B;
-        } MIR;                  /* MCM Miscellaneous Interrupt Register */
-
-        int32_t MCM_reserved5;
-
-        union {
-            vuint32_t R;
-        } MUDCR;                /* MCM Miscellaneous User-Defined Control Register */
-
-        int32_t MCM_reserved6[6];       /* (0x040- 0x028)/4 = 0x06 */
-        int8_t MCM_reserved7[3];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:2;
-                vuint8_t ER1BR:1;
-                vuint8_t EF1BR:1;
-                  vuint8_t:2;
-                vuint8_t ERNCR:1;
-                vuint8_t EFNCR:1;
-            } B;
-        } ECR;                  /* MCM ECC Configuration Register */
-
-        int8_t MCM_reserved8[3];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:2;
-                vuint8_t R1BC:1;
-                vuint8_t F1BC:1;
-                  vuint8_t:2;
-                vuint8_t RNCE:1;
-                vuint8_t FNCE:1;
-            } B;
-        } ESR;                  /* MCM ECC Status Register */
-
-        int16_t MCM_reserved9;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:2;
-                vuint16_t FRC1BI:1;
-                vuint16_t FR11BI:1;
-                  vuint16_t:2;
-                vuint16_t FRCNCI:1;
-                vuint16_t FR1NCI:1;
-                  vuint16_t:1;
-                vuint16_t ERRBIT:7;
-            } B;
-        } EEGR;                 /* MCM ECC Error Generation Register */
-
-        int32_t MCM_reserved10;
-
-        union {
-            vuint32_t R;
-        } FEAR;                 /* MCM Flash ECC Address Register */
-
-        int16_t MCM_reserved11;
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t FEMR:4;
-            } B;
-        } FEMR;                 /* MCM Flash ECC Master Number Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t WRITE:1;
-                vuint8_t SIZE:3;
-                vuint8_t PROTECTION:4;
-            } B;
-        } FEAT;                 /* MCM Flash ECC Attributes Register */
-
-        int32_t MCM_reserved12;
-
-        union {
-            vuint32_t R;
-        } FEDR;                 /* MCM Flash ECC Data Register */
-
-        union {
-            vuint32_t R;
-        } REAR;                 /* MCM RAM ECC Address Register */
-
-        int8_t MCM_reserved13;
-
-        union {
-            vuint8_t R;
-        } RESR;                 /* MCM RAM ECC Address Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t REMR:4;
-            } B;
-        } REMR;                 /* MCM RAM ECC Master Number Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t WRITE:1;
-                vuint8_t SIZE:3;
-                vuint8_t PROTECTION:4;
-            } B;
-        } REAT;                 /* MCM RAM ECC Attributes Register */
-
-        int32_t MCM_reserved14;
-
-        union {
-            vuint32_t R;
-        } REDR;                 /* MCM RAM ECC Data Register */
-
-    };                          /* end of MCM_tag */
-/****************************************************************************/
-/*                          MODULE : RTC                                   */
-/****************************************************************************/
-    struct RTC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SUPV:1;
-                  vuint32_t:31;
-            } B;
-        } RTCSUPV;              /* RTC Supervisor Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CNTEN:1;
-                vuint32_t RTCIE:1;
-                vuint32_t FRZEN:1;
-                vuint32_t ROVREN:1;
-                vuint32_t RTCVAL:12;
-                vuint32_t APIEN:1;
-                vuint32_t APIE:1;
-                vuint32_t CLKSEL:2;
-                vuint32_t DIV512EN:1;
-                vuint32_t DIV32EN:1;
-                vuint32_t APIVAL:10;
-            } B;
-        } RTCC;                 /* RTC Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:2;
-                vuint32_t RTCF:1;
-                  vuint32_t:15;
-                vuint32_t APIF:1;
-                  vuint32_t:2;
-                vuint32_t ROVRF:1;
-                  vuint32_t:10;
-            } B;
-        } RTCS;                 /* RTC Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RTCCNT:32;
-            } B;
-        } RTCCNT;               /* RTC Counter Register */
-
-    };                          /* end of RTC_tag */
-/****************************************************************************/
-/*                     MODULE : SIU                                         */
-/****************************************************************************/
-    struct SIU_tag {
-
-        int32_t SIU_reserved0;
-
-        union {                 /* MCU ID Register 1 */
-            vuint32_t R;
-            struct {
-                vuint32_t PARTNUM:16;
-		vuint32_t CSP:1;
-                vuint32_t PKG:5;
-		vuint32_t:2;
-                vuint32_t MAJORMASK:4;
-		vuint32_t MINORMASK:4;
-            } B;
-        } MIDR;
-
-        union {                 /* MCU ID Register 2 */
-            vuint32_t R;
-            struct {
-                vuint32_t SF:1;
-                vuint32_t FLASH_SIZE_1:4;
-                vuint32_t FLASH_SIZE_2:4;
-		vuint32_t:7;
-                vuint32_t PARTNUM:8;
-		vuint32_t:3;
-                vuint32_t EE:1;
-		vuint32_t:3;
-		vuint32_t FR:1;
-            } B;
-        } MIDR2;
-
-        int32_t SIU_reserved1[2];
-
-        union {                 /* Interrupt Status Flag Register */
-            vuint32_t R;
-            struct {
-                vuint32_t EIF31:1;
-                vuint32_t EIF30:1;
-                vuint32_t EIF29:1;
-                vuint32_t EIF28:1;
-                vuint32_t EIF27:1;
-                vuint32_t EIF26:1;
-                vuint32_t EIF25:1;
-                vuint32_t EIF24:1;
-                vuint32_t EIF23:1;
-                vuint32_t EIF22:1;
-                vuint32_t EIF21:1;
-                vuint32_t EIF20:1;
-                vuint32_t EIF19:1;
-                vuint32_t EIF18:1;
-                vuint32_t EIF17:1;
-                vuint32_t EIF16:1;
-                vuint32_t EIF15:1;
-                vuint32_t EIF14:1;
-                vuint32_t EIF13:1;
-                vuint32_t EIF12:1;
-                vuint32_t EIF11:1;
-                vuint32_t EIF10:1;
-                vuint32_t EIF9:1;
-                vuint32_t EIF8:1;
-                vuint32_t EIF7:1;
-                vuint32_t EIF6:1;
-                vuint32_t EIF5:1;
-                vuint32_t EIF4:1;
-                vuint32_t EIF3:1;
-                vuint32_t EIF2:1;
-                vuint32_t EIF1:1;
-                vuint32_t EIF0:1;
-            } B;
-        } ISR;
-
-        union {                 /* Interrupt Request Enable Register */
-            vuint32_t R;
-            struct {
-                vuint32_t EIRE31:1;
-                vuint32_t EIRE30:1;
-                vuint32_t EIRE29:1;
-                vuint32_t EIRE28:1;
-                vuint32_t EIRE27:1;
-                vuint32_t EIRE26:1;
-                vuint32_t EIRE25:1;
-                vuint32_t EIRE24:1;
-                vuint32_t EIRE23:1;
-                vuint32_t EIRE22:1;
-                vuint32_t EIRE21:1;
-                vuint32_t EIRE20:1;
-                vuint32_t EIRE19:1;
-                vuint32_t EIRE18:1;
-                vuint32_t EIRE17:1;
-                vuint32_t EIRE16:1;
-                vuint32_t EIRE15:1;
-                vuint32_t EIRE14:1;
-                vuint32_t EIRE13:1;
-                vuint32_t EIRE12:1;
-                vuint32_t EIRE11:1;
-                vuint32_t EIRE10:1;
-                vuint32_t EIRE9:1;
-                vuint32_t EIRE8:1;
-                vuint32_t EIRE7:1;
-                vuint32_t EIRE6:1;
-                vuint32_t EIRE5:1;
-                vuint32_t EIRE4:1;
-                vuint32_t EIRE3:1;
-                vuint32_t EIRE2:1;
-                vuint32_t EIRE1:1;
-                vuint32_t EIRE0:1;
-            } B;
-        } IRER;
-
-        int32_t SIU_reserved2[3];
-
-        union {                 /* Interrupt Rising-Edge Event Enable Register */
-            vuint32_t R;
-            struct {
-                vuint32_t IREE31:1;
-                vuint32_t IREE30:1;
-                vuint32_t IREE29:1;
-                vuint32_t IREE28:1;
-                vuint32_t IREE27:1;
-                vuint32_t IREE26:1;
-                vuint32_t IREE25:1;
-                vuint32_t IREE24:1;
-                vuint32_t IREE23:1;
-                vuint32_t IREE22:1;
-                vuint32_t IREE21:1;
-                vuint32_t IREE20:1;
-                vuint32_t IREE19:1;
-                vuint32_t IREE18:1;
-                vuint32_t IREE17:1;
-                vuint32_t IREE16:1;
-                vuint32_t IREE15:1;
-                vuint32_t IREE14:1;
-                vuint32_t IREE13:1;
-                vuint32_t IREE12:1;
-                vuint32_t IREE11:1;
-                vuint32_t IREE10:1;
-                vuint32_t IREE9:1;
-                vuint32_t IREE8:1;
-                vuint32_t IREE7:1;
-                vuint32_t IREE6:1;
-                vuint32_t IREE5:1;
-                vuint32_t IREE4:1;
-                vuint32_t IREE3:1;
-                vuint32_t IREE2:1;
-                vuint32_t IREE1:1;
-                vuint32_t IREE0:1;
-            } B;
-        } IREER;
-
-        union {                 /* Interrupt Falling-Edge Event Enable Register */
-            vuint32_t R;
-            struct {
-                vuint32_t IFEE31:1;
-                vuint32_t IFEE30:1;
-                vuint32_t IFEE29:1;
-                vuint32_t IFEE28:1;
-                vuint32_t IFEE27:1;
-                vuint32_t IFEE26:1;
-                vuint32_t IFEE25:1;
-                vuint32_t IFEE24:1;
-                vuint32_t IFEE23:1;
-                vuint32_t IFEE22:1;
-                vuint32_t IFEE21:1;
-                vuint32_t IFEE20:1;
-                vuint32_t IFEE19:1;
-                vuint32_t IFEE18:1;
-                vuint32_t IFEE17:1;
-                vuint32_t IFEE16:1;
-                vuint32_t IFEE15:1;
-                vuint32_t IFEE14:1;
-                vuint32_t IFEE13:1;
-                vuint32_t IFEE12:1;
-                vuint32_t IFEE11:1;
-                vuint32_t IFEE10:1;
-                vuint32_t IFEE9:1;
-                vuint32_t IFEE8:1;
-                vuint32_t IFEE7:1;
-                vuint32_t IFEE6:1;
-                vuint32_t IFEE5:1;
-                vuint32_t IFEE4:1;
-                vuint32_t IFEE3:1;
-                vuint32_t IFEE2:1;
-                vuint32_t IFEE1:1;
-                vuint32_t IFEE0:1;
-            } B;
-        } IFEER;
-
-        union {                 /* Interrupt Filter Enable Register */
-            vuint32_t R;
-            struct {
-                vuint32_t IFE31:1;
-                vuint32_t IFE30:1;
-                vuint32_t IFE29:1;
-                vuint32_t IFE28:1;
-                vuint32_t IFE27:1;
-                vuint32_t IFE26:1;
-                vuint32_t IFE25:1;
-                vuint32_t IFE24:1;
-                vuint32_t IFE23:1;
-                vuint32_t IFE22:1;
-                vuint32_t IFE21:1;
-                vuint32_t IFE20:1;
-                vuint32_t IFE19:1;
-                vuint32_t IFE18:1;
-                vuint32_t IFE17:1;
-                vuint32_t IFE16:1;
-                vuint32_t IFE15:1;
-                vuint32_t IFE14:1;
-                vuint32_t IFE13:1;
-                vuint32_t IFE12:1;
-                vuint32_t IFE11:1;
-                vuint32_t IFE10:1;
-                vuint32_t IFE9:1;
-                vuint32_t IFE8:1;
-                vuint32_t IFE7:1;
-                vuint32_t IFE6:1;
-                vuint32_t IFE5:1;
-                vuint32_t IFE4:1;
-                vuint32_t IFE3:1;
-                vuint32_t IFE2:1;
-                vuint32_t IFE1:1;
-                vuint32_t IFE0:1;
-            } B;
-        } IFER;
-
-        int32_t SIU_reserved3[3];
-
-        union {                 /* Pad Configuration Registers */
-            vuint16_t R;
-            struct {
-                vuint16_t:1;
-                vuint16_t SME:1;
-                vuint16_t APC:1;
-                  vuint16_t:1;
-                vuint16_t PA:2;
-                vuint16_t OBE:1;
-                vuint16_t IBE:1;
-                vuint16_t DCS:2;
-                vuint16_t ODE:1;
-                vuint16_t HYS:1;
-                vuint16_t SRC:2;
-                vuint16_t WPE:1;
-                vuint16_t WPS:1;
-            } B;
-        } PCR[512];
-
-        int32_t SIU_reserved4[48];      /* {0x500-0x440}/0x4 */
-
-        union {                 /* Pad Selection for Multiplexed Input Register */
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t PADSEL:4;
-            } B;
-        } PSMI[256];
-
-        union {                 /* GPIO Pin Data Output Registers */
-            vuint8_t R;
-            struct {
-                vuint8_t:7;
-                vuint8_t PDO:1;
-            } B;
-        } GPDO[512];
-
-        union {                 /* GPIO Pin Data Input Registers */
-            vuint8_t R;
-            struct {
-                vuint8_t:7;
-                vuint8_t PDI:1;
-            } B;
-        } GPDI[512];
-
-        int32_t SIU_reserved5[128];     /* {0xC00-0xA00}/0x4 */
-
-        union {                 /* Parallel GPIO Pin Data Output Register */
-            vuint32_t R;
-            struct {
-                vuint32_t PPD0:32;
-            } B;
-        } PGPDO[16];
-
-        union {                 /* Parallel GPIO Pin Data Input Register */
-            vuint32_t R;
-            struct {
-                vuint32_t PPDI:32;
-            } B;
-        } PGPDI[16];
-
-        union {                 /* Masked Parallel GPIO Pin Data Out Register */
-            vuint32_t R;
-            struct {
-                vuint32_t MASK:16;
-                vuint32_t MPPDO:16;
-            } B;
-        } MPGPDO[32];
-
-        int32_t SIU_reserved6[192];     /* {0x1000-0x0D00}/0x4 */
-
-        union {                 /* Interrupt Filter Maximum Counter Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t MAXCNT:4;
-            } B;
-        } IFMC[32];
-
-        union {                 /* Interrupt Filter Clock Prescaler Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t IFCP:4;
-            } B;
-        } IFCPR;
-
-    };                          /* end of SIU_tag */
-/****************************************************************************/
-/*                          MODULE : SSCM                                   */
-/****************************************************************************/
-    struct SSCM_tag {
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-                vuint16_t NXEN:1;
-                  vuint16_t PUB:1;
-                vuint16_t SEC:1;
-                  vuint16_t:1;
-                vuint16_t BMODE:3;
-                vuint16_t:1;
-                vuint16_t ABD:1;
-                  vuint16_t:3;
-            } B;
-        } STATUS;               /* Status Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t SRAMSIZE:5;
-                vuint16_t IFLASHSIZE:5;
-                vuint16_t IVLD:1;
-                vuint16_t DFLASHSIZE:4;
-                vuint16_t DVLD:1;
-            } B;
-        } MEMCONFIG;            /* System Memory Configuration Register */
-
-        int16_t SSCM_reserved;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:14;
-                vuint16_t PAE:1;
-                vuint16_t RAE:1;
-            } B;
-        } ERROR;                /* Error Configuration Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:13;
-                vuint16_t DEBUG_MODE:3;
-            } B;
-        } DEBUGPORT;            /* Debug Status Port Register */
-
-        int16_t SSCM_reserved1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PWD_HI:32;
-            } B;
-        } PWCMPH;               /* Password Comparison Register High Word */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PWD_LO:32;
-            } B;
-        } PWCMPL;               /* Password Comparison Register Low Word */
-
-    };                          /* end of SSCM_tag */
-/****************************************************************************/
-/*                          MODULE : STM                                   */
-/****************************************************************************/
-    struct STM_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t CPS:8;
-                  vuint32_t:6;
-                vuint32_t FRZ:1;
-                vuint32_t TEN:1;
-            } B;
-        } CR0;                  /* STM Control Register */
-
-        union {
-            vuint32_t R;
-        } CNT0;                 /* STM Count Register */
-
-        int32_t STM_reserved[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR0;                 /* STM Channel Control Register 0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR0;                 /* STM Channel Interrupt Register 0 */
-
-        union {
-            vuint32_t R;
-        } CMP0;                 /* STM Channel Compare Register 0 */
-
-        int32_t STM_reserved1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR1;                 /* STM Channel Control Register 1 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR1;                 /* STM Channel Interrupt Register 1 */
-
-        union {
-            vuint32_t R;
-        } CMP1;                 /* STM Channel Compare Register 1 */
-
-        int32_t STM_reserved2;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR2;                 /* STM Channel Control Register 2 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR2;                 /* STM Channel Interrupt Register 2 */
-
-        union {
-            vuint32_t R;
-        } CMP2;                 /* STM Channel Compare Register 2 */
-
-        int32_t STM_reserved3;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR3;                 /* STM Channel Control Register 3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR3;                 /* STM Channel Interrupt Register 3 */
-
-        union {
-            vuint32_t R;
-        } CMP3;                 /* STM Channel Compare Register 3 */
-
-    };                          /* end of STM_tag */
-/****************************************************************************/
-/*                          MODULE : SWT                                   */
-/****************************************************************************/
-    struct SWT_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MAP0:1;
-                vuint32_t MAP1:1;
-                vuint32_t MAP2:1;
-                vuint32_t MAP3:1;
-                vuint32_t MAP4:1;
-                vuint32_t MAP5:1;
-                vuint32_t MAP6:1;
-                vuint32_t MAP7:1;
-                  vuint32_t:15;
-                vuint32_t RIA:1;
-                vuint32_t WND:1;
-                vuint32_t ITR:1;
-                vuint32_t HLK:1;
-                vuint32_t SLK:1;
-                vuint32_t CSL:1;
-                vuint32_t STP:1;
-                vuint32_t FRZ:1;
-                vuint32_t WEN:1;
-            } B;
-        } CR;                   /* SWT Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t TIF:1;
-            } B;
-        } IR;                   /* SWT Interrupt Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WTO:32;
-            } B;
-        } TO;                   /* SWT Time-Out Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WST:32;
-            } B;
-        } WN;                   /* SWT Window Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t WSC:16;
-            } B;
-        } SR;                   /* SWT Service Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CNT:32;
-            } B;
-        } CO;                   /* SWT Counter Output Register */
-
-    };                          /* end of SWT_tag */
-/****************************************************************************/
-/*                          MODULE : WKUP                                   */
-/****************************************************************************/
-    struct WKUP_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NIF0:1;
-                vuint32_t NOVF0:1;
-                  vuint32_t:6;
-                vuint32_t NIF1:1;
-                vuint32_t NOVF1:1;
-                  vuint32_t:6;
-                vuint32_t NIF2:1;
-                vuint32_t NOVF2:1;
-                  vuint32_t:6;
-                vuint32_t NIF3:1;
-                vuint32_t NOVF3:1;
-                  vuint32_t:6;
-            } B;
-        } NSR;                  /* NMI Status Register */
-
-        int32_t WKUP_reserved;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NLOCK0:1;
-                vuint32_t NDSS0:2;
-                vuint32_t NWRE0:1;
-                  vuint32_t:1;
-                vuint32_t NREE0:1;
-                vuint32_t NFEE0:1;
-                vuint32_t NFE0:1;
-                vuint32_t NLOCK1:1;
-                vuint32_t NDSS1:2;
-                vuint32_t NWRE1:1;
-                  vuint32_t:1;
-                vuint32_t NREE1:1;
-                vuint32_t NFEE1:1;
-                vuint32_t NFE1:1;
-                vuint32_t NLOCK2:1;
-                vuint32_t NDSS2:2;
-                vuint32_t NWRE2:1;
-                  vuint32_t:1;
-                vuint32_t NREE2:1;
-                vuint32_t NFEE2:1;
-                vuint32_t NFE2:1;
-                vuint32_t NLOCK3:1;
-                vuint32_t NDSS3:2;
-                vuint32_t NWRE3:1;
-                  vuint32_t:1;
-                vuint32_t NREE3:1;
-                vuint32_t NFEE3:1;
-                vuint32_t NFE3:1;
-            } B;
-        } NCR;                  /* NMI Configuration Register */
-
-        int32_t WKUP_reserved1[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EIF:32;
-            } B;
-        } WISR;                 /* Wakeup/Interrupt Status Flag Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EIRE:32;
-            } B;
-        } IRER;                 /* Interrupt Request Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WRE:32;
-            } B;
-        } WRER;                 /* Wakeup Request Enable Register */
-
-        int32_t WKUP_reserved2[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t IREE:32;
-            } B;
-        } WIREER;               /* Wakeup/Interrupt Rising-Edge Event Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t IFEE:32;
-            } B;
-        } WIFEER;               /* Wakeup/Interrupt Falling-Edge Event Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t IFE:32;
-            } B;
-        } WIFER;                /* Wakeup/Interrupt Filter Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t IPUE:32;
-            } B;
-        } WIPUER;               /* Wakeup/Interrupt Pullup Enable Register */
-
-    };                          /* end of WKUP_tag */
-/****************************************************************************/
-/*                          MODULE : LINFLEX                                */
-/****************************************************************************/
-
-    struct LINFLEX_tag {
-
-        int16_t LINFLEX_reserved1;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CCD:1;
-                vuint16_t CFD:1;
-                vuint16_t LASE:1;
-                vuint16_t AWUM:1;       // LCH vuint16_t AUTOWU:1;
-                vuint16_t MBL:4;
-                vuint16_t BF:1;
-                vuint16_t SFTM:1;
-                vuint16_t LBKM:1;
-                vuint16_t MME:1;
-                vuint16_t SBDT:1;       // LCH vuint16_t SSBL:1;
-                vuint16_t RBLM:1;
-                vuint16_t SLEEP:1;
-                vuint16_t INIT:1;
-            } B;
-        } LINCR1;               /* LINFLEX LIN Control Register 1 */
-
-        int16_t LINFLEX_reserved2;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t SZIE:1;
-                vuint16_t OCIE:1;
-                vuint16_t BEIE:1;
-                vuint16_t CEIE:1;
-                vuint16_t HEIE:1;
-                  vuint16_t:2;
-                vuint16_t FEIE:1;
-                vuint16_t BOIE:1;
-                vuint16_t LSIE:1;
-                vuint16_t WUIE:1;
-                vuint16_t DBFIE:1;
-                vuint16_t DBEIE:1;
-                vuint16_t DRIE:1;
-                vuint16_t DTIE:1;
-                vuint16_t HRIE:1;
-            } B;
-        } LINIER;               /* LINFLEX LIN Interrupt Enable Register */
-
-        int16_t LINFLEX_reserved3;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t LINS:4;
-                  vuint16_t:2;
-                vuint16_t RMB:1;
-                  vuint16_t:1;
-                vuint16_t RBSY:1;       // LCH vuint16_t RXBUSY:1;
-                vuint16_t RPS:1;        // LCH vuint16_t RDI:1;
-                vuint16_t WUF:1;
-                vuint16_t DBFF:1;
-                vuint16_t DBEF:1;
-                vuint16_t DRF:1;
-                vuint16_t DTF:1;
-                vuint16_t HRF:1;
-            } B;
-        } LINSR;                /* LINFLEX LIN Status Register */
-
-        int16_t LINFLEX_reserved4;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t SZF:1;
-                vuint16_t OCF:1;
-                vuint16_t BEF:1;
-                vuint16_t CEF:1;
-                vuint16_t SFEF:1;
-                vuint16_t BDEF:1;
-                vuint16_t IDPEF:1;
-                vuint16_t FEF:1;
-                vuint16_t BOF:1;
-                  vuint16_t:6;
-                vuint16_t NF:1;
-            } B;
-        } LINESR;               /* LINFLEX LIN Error Status Register */
-
-        int16_t LINFLEX_reserved5;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:1;
-                vuint16_t TDFL:2;
-                  vuint16_t:1;
-                vuint16_t RDFL:2;
-                  vuint16_t:4;
-                vuint16_t RXEN:1;
-                vuint16_t TXEN:1;
-                vuint16_t OP:1; //LCH vuint16_t PARITYODD:1;
-                vuint16_t PCE:1;
-                vuint16_t WL:1;
-                vuint16_t UART:1;
-            } B;
-        } UARTCR;               /* LINFLEX UART Mode Control Register */
-
-        int16_t LINFLEX_reserved6;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t SZF:1;
-                vuint16_t OCF:1;
-                vuint16_t PE:4;
-                vuint16_t RMB:1;
-                vuint16_t FEF:1;
-                vuint16_t BOF:1;
-                vuint16_t RPS:1;        // LCH vuint16_t RDI:1;
-                vuint16_t WUF:1;
-                  vuint16_t:2;
-                vuint16_t DRF:1;
-                vuint16_t DTF:1;
-                vuint16_t NF:1;
-            } B;
-        } UARTSR;               /* LINFLEX UART Mode Status Register */
-
-        int16_t LINFLEX_reserved7;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t LTOM:1;       //LCH vuint16_t MODE:1;
-                vuint16_t IOT:1;
-                vuint16_t TOCE:1;
-                vuint16_t CNT:8;
-            } B;
-        } LINTCSR;              /* LINFLEX LIN Time-Out Control Status Register */
-
-        int16_t LINFLEX_reserved8;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t OC2:8;
-                vuint16_t OC1:8;
-            } B;
-        } LINOCR;               /* LINFLEX LIN Output Compare Register */
-
-        int16_t LINFLEX_reserved9;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-                vuint16_t RTO:4;        // LCH vuint16_t RTC:4;
-                  vuint16_t:1;
-                vuint16_t HTO:7;        // LCH vuint16_t HTC:7;
-            } B;
-        } LINTOCR;              /* LINFLEX LIN Output Compare Register */
-
-        int16_t LINFLEX_reserved10;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t DIV_F:4;      // LCH vuint16_t FBR:4;
-            } B;
-        } LINFBRR;              /* LINFLEX LIN Fractional Baud Rate Register */
-
-        int16_t LINFLEX_reserved11;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t DIV_M:13;     // LCH vuint16_t IBR:13;
-            } B;
-        } LINIBRR;              /* LINFLEX LIN Integer Baud Rate Register */
-
-        int16_t LINFLEX_reserved12;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t CF:8;
-            } B;
-        } LINCFR;               /* LINFLEX LIN Checksum Field Register */
-
-        int16_t LINFLEX_reserved13;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:1;
-                vuint16_t IOBE:1;
-                vuint16_t IOPE:1;
-                vuint16_t WURQ:1;
-                vuint16_t DDRQ:1;
-                vuint16_t DTRQ:1;
-                vuint16_t ABRQ:1;
-                vuint16_t HTRQ:1;
-                  vuint16_t:8;
-            } B;
-        } LINCR2;               /* LINFLEX LIN Control Register 2 */
-
-        int16_t LINFLEX_reserved14;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t DFL:6;
-                vuint16_t DIR:1;
-                vuint16_t CCS:1;
-                  vuint16_t:2;  // LCH vuint16_t:1;
-                vuint16_t ID:6;
-            } B;
-        } BIDR;                 /* LINFLEX Buffer Identifier Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DATA3:8;
-                vuint32_t DATA2:8;
-                vuint32_t DATA1:8;
-                vuint32_t DATA0:8;
-            } B;
-        } BDRL;                 /* LINFLEX Buffer Data Register Least Significant */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DATA7:8;
-                vuint32_t DATA6:8;
-                vuint32_t DATA5:8;
-                vuint32_t DATA4:8;
-            } B;
-        } BDRM;                 /* LINFLEX Buffer Data Register Most Significant */
-
-        int16_t LINFLEX_reserved15;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t FACT:8;
-            } B;
-        } IFER;                 /* LINFLEX Identifier Filter Enable Register */
-
-        int16_t LINFLEX_reserved16;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t IFMI:4;
-            } B;
-        } IFMI;                 /* LINFLEX Identifier Filter Match Index Register */
-
-        int16_t LINFLEX_reserved17;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t IFM:4;
-            } B;
-        } IFMR;                 /* LINFLEX Identifier Filter Mode Register */
-
-        int16_t LINFLEX_reserved18;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t DFL:3;
-                vuint16_t DIR:1;
-                vuint16_t CCS:1;
-                  vuint16_t:2;
-                vuint16_t ID:6;
-            } B;
-        } IFCR0;                /* LINFLEX Identifier Filter Control Register 0 */
-
-        int16_t LINFLEX_reserved19;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t DFL:3;
-                vuint16_t DIR:1;
-                vuint16_t CCS:1;
-                  vuint16_t:2;
-                vuint16_t ID:6;
-            } B;
-        } IFCR1;                /* LINFLEX Identifier Filter Control Register 1 */
-
-        int16_t LINFLEX_reserved20;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t DFL:3;
-                vuint16_t DIR:1;
-                vuint16_t CCS:1;
-                  vuint16_t:2;
-                vuint16_t ID:6;
-            } B;
-        } IFCR2;                /* LINFLEX Identifier Filter Control Register 2 */
-
-        int16_t LINFLEX_reserved21;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t DFL:3;
-                vuint16_t DIR:1;
-                vuint16_t CCS:1;
-                  vuint16_t:2;
-                vuint16_t ID:6;
-            } B;
-        } IFCR3;                /* LINFLEX Identifier Filter Control Register 3 */
-
-        int16_t LINFLEX_reserved22;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t DFL:3;
-                vuint16_t DIR:1;
-                vuint16_t CCS:1;
-                  vuint16_t:2;
-                vuint16_t ID:6;
-            } B;
-        } IFCR4;                /* LINFLEX Identifier Filter Control Register 4 */
-
-        int16_t LINFLEX_reserved23;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t DFL:3;
-                vuint16_t DIR:1;
-                vuint16_t CCS:1;
-                  vuint16_t:2;
-                vuint16_t ID:6;
-            } B;
-        } IFCR5;                /* LINFLEX Identifier Filter Control Register 5 */
-
-        int16_t LINFLEX_reserved24;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t DFL:3;
-                vuint16_t DIR:1;
-                vuint16_t CCS:1;
-                  vuint16_t:2;
-                vuint16_t ID:6;
-            } B;
-        } IFCR6;                /* LINFLEX Identifier Filter Control Register 6 */
-
-        int16_t LINFLEX_reserved25;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t DFL:3;
-                vuint16_t DIR:1;
-                vuint16_t CCS:1;
-                  vuint16_t:2;
-                vuint16_t ID:6;
-            } B;
-        } IFCR7;                /* LINFLEX Identifier Filter Control Register 7 */
-
-    };                          /* end of LINFLEX_tag */
-/****************************************************************************/
-/*                          MODULE : ME                                   */
-/****************************************************************************/
-    struct ME_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t S_CURRENTMODE:4;
-                vuint32_t S_MTRANS:1;
-                vuint32_t S_DC:1;
-                  vuint32_t:2;
-                vuint32_t S_PDO:1;
-                  vuint32_t:2;
-                vuint32_t S_MVR:1;
-                vuint32_t S_DFLA:2;
-                vuint32_t S_CFLA:2;
-                  vuint32_t:8;
-                vuint32_t S_PLL1:1;
-                vuint32_t S_PLL0:1;
-                vuint32_t S_OSC:1;
-                vuint32_t S_RC:1;
-                vuint32_t S_SYSCLK:4;
-            } B;
-        } GS;                   /* Global Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TARGET_MODE:4;
-                  vuint32_t:12;
-                vuint32_t KEY:16;
-            } B;
-        } MCTL;                 /* Mode Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:18;
-                vuint32_t STANDBY0:1;
-                  vuint32_t:2;
-                vuint32_t STOP0:1;
-                  vuint32_t:1;
-                vuint32_t HALT0:1;
-                vuint32_t RUN3:1;
-                vuint32_t RUN2:1;
-                vuint32_t RUN1:1;
-                vuint32_t RUN0:1;
-                vuint32_t DRUN:1;
-                vuint32_t SAFE:1;
-                vuint32_t TEST:1;
-                vuint32_t RESET:1;
-            } B;
-        } MER;                  /* Mode Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t I_CONF:1;
-                vuint32_t I_MODE:1;
-                vuint32_t I_SAFE:1;
-                vuint32_t I_MTC:1;
-            } B;
-        } IS;                   /* Interrupt Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t M_CONF:1;
-                vuint32_t M_MODE:1;
-                vuint32_t M_SAFE:1;
-                vuint32_t M_TC:1;
-            } B;
-        } IM;                   /* Interrupt Mask Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:27;
-                vuint32_t S_MTI:1;
-                vuint32_t S_MRI:1;
-                vuint32_t S_DMA:1;
-                vuint32_t S_NMA:1;
-                vuint32_t S_SEA:1;
-            } B;
-        } IMTS;                 /* Invalid Mode Transition Status Register */
-
-        int32_t ME_reserved0[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:8;
-                vuint32_t PLL2ON:1;
-                vuint32_t PLL1ON:1;
-                vuint32_t XOSC0ON:1;
-                vuint32_t IRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } RESET;                /* Reset Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:8;
-                vuint32_t PLL2ON:1;
-                vuint32_t PLL1ON:1;
-                vuint32_t XOSC0ON:1;
-                vuint32_t IRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } TEST;                 /* Test Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:8;
-                vuint32_t PLL2ON:1;
-                vuint32_t PLL1ON:1;
-                vuint32_t XOSC0ON:1;
-                vuint32_t IRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } SAFE;                 /* Safe Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:8;
-                vuint32_t PLL2ON:1;
-                vuint32_t PLL1ON:1;
-                vuint32_t XOSC0ON:1;
-                vuint32_t IRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } DRUN;                 /* DRUN Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:8;
-                vuint32_t PLL2ON:1;
-                vuint32_t PLL1ON:1;
-                vuint32_t XOSC0ON:1;
-                vuint32_t IRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } RUN[4];               /* RUN 0->4 Mode Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:8;
-                vuint32_t PLL2ON:1;
-                vuint32_t PLL1ON:1;
-                vuint32_t XOSC0ON:1;
-                vuint32_t IRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } HALT0;                /* HALT0 Mode Configuration Register */
-
-        int32_t ME_reserved1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:8;
-                vuint32_t PLL2ON:1;
-                vuint32_t PLL1ON:1;
-                vuint32_t XOSC0ON:1;
-                vuint32_t IRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } STOP0;                /* STOP0 Mode Configuration Register */
-
-        int32_t ME_reserved2[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t PDO:1;
-                  vuint32_t:2;
-                vuint32_t MVRON:1;
-                vuint32_t DFLAON:2;
-                vuint32_t CFLAON:2;
-                  vuint32_t:8;
-                vuint32_t PLL2ON:1;
-                vuint32_t PLL1ON:1;
-                vuint32_t XOSC0ON:1;
-                vuint32_t IRCON:1;
-                vuint32_t SYSCLK:4;
-            } B;
-        } STANDBY0;             /* STANDBY0 Mode Configuration Register */
-
-        int32_t ME_reserved3[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PERIPH:32;
-            } B;
-        } PS[4];                /* Peripheral Status 0->4 Register */
-
-        int32_t ME_reserved4[4];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t RUN3:1;
-                vuint32_t RUN2:1;
-                vuint32_t RUN1:1;
-                vuint32_t RUN0:1;
-                vuint32_t DRUN:1;
-                vuint32_t SAFE:1;
-                vuint32_t TEST:1;
-                vuint32_t RESET:1;
-            } B;
-        } RUNPC[8];             /* RUN Peripheral Configuration 0->7 Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:18;
-                vuint32_t STANDBY0:1;
-                  vuint32_t:2;
-                vuint32_t STOP0:1;
-                  vuint32_t:1;
-                vuint32_t HALT0:1;
-                  vuint32_t:8;
-            } B;
-        } LPPC[8];              /* Low Power Peripheral Configuration 0->7 Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t DBG_F:1;
-                vuint8_t LP_CFG:3;
-                vuint8_t RUN_CFG:3;
-            } B;
-        } PCTL[144];            /* Peripheral Control 0->143 Register */
-
-    };                          /* end of ME_tag */
-/****************************************************************************/
-/*                          MODULE : CGM                                   */
-/****************************************************************************/
-    struct CGM_tag {
-
-        /* The CGM provides a unified register interface, enabling access to 
-           all clock sources:
-           
-           Clock Type | Starting Address Map | Associated Clock Sources
-           ------------------------------------------------------------
-           System     | C3FE0000             | OSC_CTL
-           "        | -                    | Reserved
-           "        | C3FE0040             | LPOSC_CTL
-           "        | C3FE0060             | RC_CTL
-           "        | C3FE0080             | LPRC_CTL
-           "        | C3FE00A0             | FMPLL_0
-           "        | C3FE00C0             | FMPLL_1
-           "        | -                    | Reserved
-           MISC       | C3FE0100             | CMU_0 & CMU_1
-           
-         */
-
-    /************************************/
-        /* OSC_CTL @ CGM base address + 0x0000 */
-    /************************************/
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t OSCBYP:1;
-                  vuint32_t:7;
-                vuint32_t EOCV:8;
-                vuint32_t M_OSC:1;
-                  vuint32_t:2;
-                vuint32_t OSCDIV:5;
-                vuint32_t I_OSC:1;
-                  vuint32_t:5;
-                vuint32_t S_OSC:1;
-                vuint32_t OSCON:1;
-            } B;
-        } OSC_CTL;              /* Main OSC Control Register */
-
-    /************************************/
-        /* LPOSC_CTL @ CGM base address + 0x0040 */
-    /************************************/
-        int32_t CGM_reserved0[15];      /* (0x040 - 0x004)/4 = 0x0F */
-        /*int32_t $RESERVED[15]; */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t OSCBYP:1;
-                  vuint32_t:7;
-                vuint32_t EOCV:8;
-                vuint32_t M_OSC:1;
-                  vuint32_t:2;
-                vuint32_t OSCDIV:5;
-                vuint32_t I_OSC:1;
-                  vuint32_t:5;
-                vuint32_t S_OSC:1;
-                vuint32_t OSCON:1;
-            } B;
-        } LPOSC_CTL;            /* Low Power OSC Control Register */
-
-    /************************************/
-        /* RC_CTL @ CGM base address + 0x0060 */
-    /************************************/
-        int32_t CGM_reserved1[7];       /* (0x060 - 0x044)/4 = 0x07 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:10;
-                vuint32_t RCTRIM:6;
-                  vuint32_t:3;
-                vuint32_t RCDIV:5;
-                  vuint32_t:2;
-                vuint32_t S_RC_STDBY:1;
-                  vuint32_t:5;
-            } B;
-        } RC_CTL;               /* RC OSC Control Register */
-
-    /*************************************/
-        /* LPRC_CTL @ CGM base address + 0x0080 */
-    /*************************************/
-        int32_t CGM_reserved2[7];       /* (0x080 - 0x064)/4 = 0x07 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:11;
-                vuint32_t LRCTRIM:5;
-                  vuint32_t:3;
-                vuint32_t LPRCDIV:5;
-                  vuint32_t:3;
-                vuint32_t S_LPRC:1;
-                  vuint32_t:3;
-                vuint32_t LPRCON_STDBY:1;
-            } B;
-        } LPRC_CTL;             /* Low Power RC OSC Control Register */
-
-    /************************************/
-        /* FMPLL_0 @ CGM base address + 0x00A0 */
-        /* FMPLL_1 @ CGM base address + 0x0100 */
-    /************************************/
-        int32_t CGM_reserved3[7];       /* (0x0A0 - 0x084)/4 = 0x07 */
-
-        struct {
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:2;
-                    vuint32_t IDF:4;
-                    vuint32_t ODF:2;
-                      vuint32_t:1;
-                    vuint32_t NDIV:7;
-                      vuint32_t:7;
-                    vuint32_t EN_PLL_SW:1;
-                    vuint32_t MODE:1;
-                    vuint32_t UNLOCK_ONCE:1;
-                      vuint32_t:1;
-                    vuint32_t I_LOCK:1;
-                    vuint32_t S_LOCK:1;
-                    vuint32_t PLL_FAIL_MASK:1;
-                    vuint32_t PLL_FAIL_FLAG:1;
-                      vuint32_t:1;
-                } B;
-            } CR;               /* FMPLL Control Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t STRB_BYPASS:1;
-                      vuint32_t:1;
-                    vuint32_t SPRD_SEL:1;
-                    vuint32_t MOD_PERIOD:13;
-                    vuint32_t FM_EN:1;
-                    vuint32_t INC_STEP:15;
-                } B;
-            } MR;               /* FMPLL Modulation Register */
-
-            int32_t CGM_reserved4[6];   /* (0x0C0 - 0x0A8)/4 = 0x06 */
-            /* (0x0E0 - 0x0C8)/4 = 0x06 */
-
-        } FMPLL[2];
-
-    /************************************/
-        /* CMU @ CGM base address + 0x0100  */
-    /************************************/
-        int32_t CGM_reserved5[8];       /* (0x100 - 0x0E0)/4 = 0x08 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t SFM:1;
-                  vuint32_t:13;
-                vuint32_t CLKSEL1:2;
-                  vuint32_t:5;
-                vuint32_t RCDIV:2;
-                vuint32_t CME_A:1;
-            } B;
-        } CMU_0_CSR;            /* Control Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t FD:20;
-            } B;
-        } CMU_0_FDR;            /* Frequency Display Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:20;
-                vuint32_t HFREF_A:12;
-            } B;
-        } CMU_0_HFREFR_A;       /* High Frequency Reference Register PLL_A Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:20;
-                vuint32_t LFREF_A:12;
-            } B;
-        } CMU_0_LFREFR_A;       /* Low Frequency Reference Register PLL_A Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t FLCI_0:1;
-                vuint32_t FHHI_0:1;
-                vuint32_t FLLI_0:1;
-                vuint32_t OLRI:1;
-            } B;
-        } CMU_0_ISR;            /* Interrupt Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:32;
-            } B;
-        } CMU_0_IMR;            /* Interrupt Mask Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t MD:20;
-            } B;
-        } CMU_0_MDR;            /* Measurement Duration Register */
-
-        int32_t CGM_reserved5A; /* (0x020 - 0x01C)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t SFM:1;
-                  vuint32_t:13;
-                vuint32_t CLKSEL1:2;
-                  vuint32_t:5;
-                vuint32_t RCDIV:2;
-                vuint32_t CME_A:1;
-            } B;
-        } CMU_1_CSR;            /* Control Status Register */
-
-        int32_t CGM_reserved6;  /* (0x028 - 0x024)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:20;
-                vuint32_t HFREF_A:12;
-            } B;
-        } CMU_1_HFREFR_A;       /* High Frequency Reference Register PLL_A Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:20;
-                vuint32_t LFREF_A:12;
-            } B;
-        } CMU_1_LFREFR_A;       /* Low Frequency Reference Register PLL_A Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t FLCI_1:1;
-                vuint32_t FHHI_1:1;
-                vuint32_t FLLI_1:1;
-                  vuint32_t:1;
-            } B;
-        } CMU_1_ISR;            /* Interrupt Status Register */
-
-    /************************************/
-        /* CGM General Registers @ CGM base address + 0x0370 */
-    /************************************/
-        int32_t CGM_reserved7[143];     /* (0x370 - 0x134)/4 = 0x8F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t EN:1;
-            } B;
-        } OCEN;                 /* Output Clock Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:2;
-                vuint32_t SELDIV:2;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } OCDSSC;               /* Output Clock Division Select Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELSTAT:4;
-                  vuint32_t:24;
-            } B;
-        } SCSS;                 /* System Clock Select Status */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } SCDC;                 /* GSystem Clock Divider Configuration 0->4 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC0SC;                /* Aux Clock 0 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC0DC;                /* Aux Clock 0 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC1SC;                /* Aux Clock 1 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC1DC;                /* Aux Clock 1 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC2SC;                /* Aux Clock 2 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC2DC;                /* Aux Clock 2 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC3SC;                /* Aux Clock 3 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC3DC;                /* Aux Clock 3 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC4SC;                /* Aux Clock 4 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC4DC;                /* Aux Clock 4 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC5SC;                /* Aux Clock 5 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC5DC;                /* Aux Clock 5 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC6SC;                /* Aux Clock 6 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC6DC;                /* Aux Clock 6 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC7SC;                /* Aux Clock 7 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC7DC;                /* Aux Clock 7 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC8SC;                /* Aux Clock 8 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC8DC;                /* Aux Clock 8 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC9SC;                /* Aux Clock 9 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC9DC;                /* Aux Clock 9 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC10SC;               /* Aux Clock 10 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC10DC;               /* Aux Clock 10 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC11SC;               /* Aux Clock 11 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC11DC;               /* Aux Clock 11 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC12SC;               /* Aux Clock 12 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC12DC;               /* Aux Clock 12 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC13SC;               /* Aux Clock 13 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC13DC;               /* Aux Clock 13 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC14SC;               /* Aux Clock 14 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC14DC;               /* Aux Clock 14 Divider Configuration 0->3 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t SELCTL:4;
-                  vuint32_t:24;
-            } B;
-        } AC15SC;               /* Aux Clock 15 Select Control */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DE0:1;
-                  vuint32_t:3;
-                vuint32_t DIV0:4;
-                vuint32_t DE1:1;
-                  vuint32_t:3;
-                vuint32_t DIV1:4;
-                vuint32_t DE2:1;
-                  vuint32_t:3;
-                vuint32_t DIV2:4;
-                vuint32_t DE3:1;
-                  vuint32_t:3;
-                vuint32_t DIV3:4;
-            } B;
-        } AC15DC;               /* Aux Clock 15 Divider Configuration 0->3 */
-
-    };                          /* end of CGM_tag */
-/****************************************************************************/
-/*                          MODULE : RGM                                   */
-/****************************************************************************/
-    struct RGM_tag {
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t F_EXR:1;
-                  vuint16_t:3;
-                vuint16_t F_CMU1_FHL:1;
-                  vuint16_t:1;
-                vuint16_t F_PLL1:1;
-                vuint16_t F_FLASH:1;
-                vuint16_t F_LVD45:1;
-                vuint16_t F_CMU0_FHL:1;
-                vuint16_t F_CMU0_OLR:1;
-                vuint16_t F_PLL0:1;
-                vuint16_t F_CHKSTOP:1;
-                vuint16_t F_SOFT:1;
-                vuint16_t F_CORE:1;
-                vuint16_t F_JTAG:1;
-            } B;
-        } FES;                  /* Functional Event Status */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t POR:1;
-                  vuint16_t:7;
-                vuint16_t F_COMP:1;
-                vuint16_t F_LVD27_IO:1;
-                vuint16_t F_LVD27_FLASH:1;
-                vuint16_t F_LVD27_VREG:1;
-                vuint16_t F_LVD27:1;
-                vuint16_t F_SWT:1;
-                vuint16_t F_LVD12_PD1:1;
-                vuint16_t F_LVD12_PD0:1;
-            } B;
-        } DES;                  /* Destructive Event Status */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t D_EXR:1;
-                  vuint16_t:3;
-                vuint16_t D_CMU1_FHL:1;
-                  vuint16_t:1;
-                vuint16_t D_PLL1:1;
-                vuint16_t D_FLASH:1;
-                vuint16_t D_LVD45:1;
-                vuint16_t D_CMU0_FHL:1;
-                vuint16_t D_CMU0_OLR:1;
-                vuint16_t D_PLL0:1;
-                vuint16_t D_CHKSTOP:1;
-                vuint16_t D_SOFT:1;
-                vuint16_t D_CORE:1;
-                vuint16_t D_JTAG:1;
-            } B;
-        } FERD;                 /* Functional Event Reset Disable */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t D_COMP:1;
-                vuint16_t D_LVD27_IO:1;
-                vuint16_t D_LVD27_FLASH:1;
-                vuint16_t D_LVD27_VREG:1;
-                vuint16_t D_LVD27:1;
-                vuint16_t D_SWT:1;
-                vuint16_t D_LVD12_PD1:1;
-                vuint16_t D_LVD12_PD0:1;
-            } B;
-        } DERD;                 /* Destructive Event Reset Disable */
-
-        int16_t RGM_reserved0[4];
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-                vuint16_t AR_CMU1_FHL:1;
-                  vuint16_t:1;
-                vuint16_t AR_PLL1:1;
-                vuint16_t AR_FLASH:1;
-                vuint16_t AR_LVD45:1;
-                vuint16_t AR_CMU0_FHL:1;
-                vuint16_t AR_CMU0_OLR:1;
-                vuint16_t AR_PLL0:1;
-                vuint16_t AR_CHKSTOP:1;
-                vuint16_t AR_SOFT:1;
-                vuint16_t AR_CORE:1;
-                vuint16_t AR_JTAG:1;
-            } B;
-        } FEAR;                 /* Functional Event Alternate Request */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t AR_COMP:1;
-                vuint16_t AR_LVD27_IO:1;
-                vuint16_t AR_LVD27_FLASH:1;
-                vuint16_t AR_LVD27_VREG:1;
-                vuint16_t AR_LVD27:1;
-                vuint16_t AR_SWT:1;
-                vuint16_t AR_LVD12_PD1:1;
-                vuint16_t AR_LVD12_PD0:1;
-            } B;
-        } DEAR;                 /* Destructive Event Alternate Request */
-
-        int16_t RGM_reserved1[2];
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-		vuint16_t SS_CMU1_FHL:1;
-		vuint16_t:1;
-		vuint16_t SS_PLL1:1;
-                vuint16_t SS_FLASH:1;
-                vuint16_t SS_LVD45:1;
-                vuint16_t SS_CMU0_FHL:1;
-                vuint16_t SS_CMU0_OLR:1;
-                vuint16_t SS_PLL0:1;
-                vuint16_t SS_CHKSTOP:1;
-                vuint16_t SS_SOFT:1;
-                vuint16_t SS_CORE:1;
-                vuint16_t SS_JTAG:1;
-            } B;
-        } FESS;                 /* Functional Event Short Sequence */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t BOOT:1;
-                  vuint16_t:4;
-                vuint16_t DRUND_FLA:1;
-                  vuint16_t:1;
-                vuint16_t DRUNC_FLA:1;
-            } B;
-        } STDBY;                /* STANDBY reset sequence */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-		vuint16_t BE_CMU1_FHL:1;
-		vuint16_t:1;
-		vuint16_t BE_PLL1:1;
-                vuint16_t BE_FLASH:1;
-                vuint16_t BE_LVD45:1;
-                vuint16_t BE_CMU0_FHL:1;
-                vuint16_t BE_CMU0_OLR:1;
-                vuint16_t BE_PLL0:1;
-                vuint16_t BE_CHKSTOP:1;
-                vuint16_t BE_SOFT:1;
-                vuint16_t BE_CORE:1;
-                vuint16_t BE_JTAG:1;
-            } B;
-        } FBRE;                 /* Functional Bidirectional Reset Enable */
-
-    };                          /* end of RGM_tag */
-/****************************************************************************/
-/*                          MODULE : PCU                                   */
-/****************************************************************************/
-    struct PCU_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:18;
-                vuint32_t STBY0:1;
-                  vuint32_t:2;
-                vuint32_t STOP0:1;
-                  vuint32_t:1;
-                vuint32_t HALT0:1;
-                vuint32_t RUN3:1;
-                vuint32_t RUN2:1;
-                vuint32_t RUN1:1;
-                vuint32_t RUN0:1;
-                vuint32_t DRUN:1;
-                vuint32_t SAFE:1;
-                vuint32_t TEST:1;
-                vuint32_t RST:1;
-            } B;
-        } PCONF[16];            /* Power domain 0-15 configuration register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t PD15:1;
-                vuint32_t PD14:1;
-                vuint32_t PD13:1;
-                vuint32_t PD12:1;
-                vuint32_t PD11:1;
-                vuint32_t PD10:1;
-                vuint32_t PD9:1;
-                vuint32_t PD8:1;
-                vuint32_t PD7:1;
-                vuint32_t PD6:1;
-                vuint32_t PD5:1;
-                vuint32_t PD4:1;
-                vuint32_t PD3:1;
-                vuint32_t PD2:1;
-                vuint32_t PD1:1;
-                vuint32_t PD0:1;
-            } B;
-        } PSTAT;                /* Power Domain Status Register */
-
-        int32_t PCU_reserved0[15];      /* {0x0080-0x0044}/0x4 = 0xF */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:15;
-                vuint32_t MASK_LVDHV5:1;
-            } B;
-        } VCTL;                 /* Voltage Regulator Control Register */
-
-    };                          /* end of PCU_tag */
-/****************************************************************************/
-/*                          MODULE : FLEXPWM                                   */
-/****************************************************************************/
-    struct FLEXPWM_SUB_tag {
-
-        union {
-            vuint16_t R;
-        } CNT;                  /* Counter Register */
-
-        union {
-            vuint16_t R;
-        } INIT;                 /* Initial Count Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t DBGEN:1;
-                vuint16_t WAITEN:1;
-                vuint16_t INDEP:1;
-                vuint16_t PWMA_INIT:1;
-                vuint16_t PWMB_INIT:1;
-                vuint16_t PWMX_INIT:1;
-                vuint16_t INIT_SEL:2;
-                vuint16_t FRCEN:1;
-                vuint16_t FORCE:1;
-                vuint16_t FORCE_SEL:3;
-                vuint16_t RELOAD_SEL:1;
-                vuint16_t CLK_SEL:2;
-            } B;
-        } CTRL2;                /* Control 2 Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t LDFQ:4;
-                vuint16_t HALF:1;
-                vuint16_t FULL:1;
-                vuint16_t DT:2;
-                  vuint16_t:1;
-                vuint16_t PRSC:3;
-                  vuint16_t:3;
-                vuint16_t DBLEN:1;
-            } B;
-        } CTRL;                 /* Control Register */
-
-        union {
-            vuint16_t R;
-        } VAL[6];               /* Value Register 0->5 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t FRACAEN:1;
-                  vuint16_t:10;
-                vuint16_t FRACADLY:5;
-            } B;
-        } FRACA;                /* Fractional Delay Register A */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t FRACBEN:1;
-                  vuint16_t:10;
-                vuint16_t FRACBDLY:5;
-            } B;
-        } FRACB;                /* Fractional Delay Register B */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t PWMA_IN:1;
-                vuint16_t PWMB_IN:1;
-                vuint16_t PWMX_IN:1;
-                  vuint16_t:2;
-                vuint16_t POLA:1;
-                vuint16_t POLB:1;
-                vuint16_t POLX:1;
-                  vuint16_t:2;
-                vuint16_t PWMAFS:2;
-                vuint16_t PWMBFS:2;
-                vuint16_t PWMXFS:2;
-            } B;
-        } OCTRL;                /* Output Control Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:1;
-                vuint16_t RUF:1;
-                vuint16_t REF:1;
-                vuint16_t RF:1;
-                vuint16_t CFA1:1;
-                vuint16_t CFA0:1;
-                vuint16_t CFB1:1;
-                vuint16_t CFB0:1;
-                vuint16_t CFX1:1;
-                vuint16_t CFX0:1;
-                vuint16_t CMPF:6;
-            } B;
-        } STS;                  /* Status Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:2;
-                vuint16_t REIE:1;
-                vuint16_t RIE:1;
-                  vuint16_t:4;
-                vuint16_t CX1IE:1;
-                vuint16_t CX0IE:1;
-                vuint16_t CMPIE:6;
-            } B;
-        } INTEN;                /* Interrupt Enable Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:6;
-                vuint16_t VALDE:1;
-                vuint16_t FAND:1;
-                vuint16_t CAPTDE:2;
-                vuint16_t CA1DE:1;
-                vuint16_t CA0DE:1;
-                vuint16_t CB1DE:1;
-                vuint16_t CB0DE:1;
-                vuint16_t CX1DE:1;
-                vuint16_t CX0DE:1;
-            } B;
-        } DMAEN;                /* DMA Enable Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:10;
-                vuint16_t OUT_TRIG_EN:6;
-            } B;
-        } TCTRL;                /* Output Trigger Control Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-                vuint16_t DISX:4;
-                vuint16_t DISB:4;
-                vuint16_t DISA:4;
-            } B;
-        } DISMAP;               /* Fault Disable Mapping Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t DTCNT0:11;
-            } B;
-        } DTCNT0;               /* Deadtime Count Register 0 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t DTCNT1:11;
-            } B;
-        } DTCNT1;               /* Deadtime Count Register 1 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CA1CNT:3;
-                vuint16_t CA0CNT:3;
-                vuint16_t CFAWM:2;
-                vuint16_t EDGCNTAEN:1;
-                vuint16_t INPSELA:1;
-                vuint16_t EDGA1:2;
-                vuint16_t EDGA0:2;
-                vuint16_t ONESHOTA:1;
-                vuint16_t ARMA:1;
-            } B;
-        } CAPTCTRLA;            /* Capture Control Register A */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t EDGCNTA:8;
-                vuint16_t EDGCMPA:8;
-            } B;
-        } CAPTCOMPA;            /* Capture Compare Register A */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CB1CNT:3;
-                vuint16_t CB0CNT:3;
-                vuint16_t CFBWM:2;
-                vuint16_t EDGCNTBEN:1;
-                vuint16_t INPSELB:1;
-                vuint16_t EDGB1:2;
-                vuint16_t EDGB0:2;
-                vuint16_t ONESHOTB:1;
-                vuint16_t ARMB:1;
-            } B;
-        } CAPTCTRLB;            /* Capture Control Register B */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t EDGCNTB:8;
-                vuint16_t EDGCMPB:8;
-            } B;
-        } CAPTCOMPB;            /* Capture Compare Register B */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CX1CNT:3;
-                vuint16_t CX0CNT:3;
-                vuint16_t CFXWM:2;
-                vuint16_t EDGCNTX_EN:1;
-                vuint16_t INP_SELX:1;
-                vuint16_t EDGX1:2;
-                vuint16_t EDGX0:2;
-                vuint16_t ONESHOTX:1;
-                vuint16_t ARMX:1;
-            } B;
-        } CAPTCTRLX;            /* Capture Control Register B */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t EDGCNTX:8;
-                vuint16_t EDGCMPX:8;
-            } B;
-        } CAPTCOMPX;            /* Capture Compare Register X */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CAPTVAL0:16;
-            } B;
-        } CVAL0;                /* Capture Value 0 Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t CVAL0CYC:4;
-            } B;
-        } CVAL0C;               /* Capture Value 0 Cycle Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CAPTVAL1:16;
-            } B;
-        } CVAL1;                /* Capture Value 1 Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t CVAL1CYC:4;
-            } B;
-        } CVAL1C;               /* Capture Value 1 Cycle Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CAPTVAL2:16;
-            } B;
-        } CVAL2;                /* Capture Value 2 Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t CVAL2CYC:4;
-            } B;
-        } CVAL2C;               /* Capture Value 2 Cycle Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CAPTVAL3:16;
-            } B;
-        } CVAL3;                /* Capture Value 3 Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t CVAL3CYC:4;
-            } B;
-        } CVAL3C;               /* Capture Value 3 Cycle Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CAPTVAL4:16;
-            } B;
-        } CVAL4;                /* Capture Value 4 Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t CVAL4CYC:4;
-            } B;
-        } CVAL4C;               /* Capture Value 4 Cycle Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CAPTVAL5:16;
-            } B;
-        } CVAL5;                /* Capture Value 5 Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t CVAL5CYC:4;
-            } B;
-        } CVAL5C;               /* Capture Value 5 Cycle Register */
-
-        uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */
-
-    };                          /* end of FLEXPWM_SUB_tag */
-
-    struct FLEXPWM_tag {
-
-        /* eg. FLEXPWM.SUB<[x]>.CNT.R  {x = 0->3} */
-        struct FLEXPWM_SUB_tag SUB[4];
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-                vuint16_t PWMA_EN:4;
-                vuint16_t PWMB_EN:4;
-                vuint16_t PWMX_EN:4;
-            } B;
-        } OUTEN;                /* Output Enable Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-                vuint16_t MASKA:4;
-                vuint16_t MASKB:4;
-                vuint16_t MASKX:4;
-            } B;
-        } MASK;                 /* Output Mask Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t OUTA_3:1;
-                vuint16_t OUTB_3:1;
-                vuint16_t OUTA_2:1;
-                vuint16_t OUTB_2:1;
-                vuint16_t OUTA_1:1;
-                vuint16_t OUTB_1:1;
-                vuint16_t OUTA_0:1;
-                vuint16_t OUTB_0:1;
-            } B;
-        } SWCOUT;               /* Software Controlled Output Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t SELA_3:2;
-                vuint16_t SELB_3:2;
-                vuint16_t SELA_2:2;
-                vuint16_t SELB_2:2;
-                vuint16_t SELA_1:2;
-                vuint16_t SELB_1:2;
-                vuint16_t SELA_0:2;
-                vuint16_t SELB_0:2;
-            } B;
-        } DTSRCSEL;             /* Deadtime Source Select Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t IPOL:4;
-                vuint16_t RUN:4;
-                vuint16_t CLDOK:4;
-                vuint16_t LDOK:4;
-            } B;
-        } MCTRL;                /* Master Control Register */
-
-        int16_t FLEXPWM_reserved1;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t FLVL:4;
-                vuint16_t FAUTO:4;
-                vuint16_t FSAFE:4;
-                vuint16_t FIE:4;
-            } B;
-        } FCTRL;                /* Fault Control Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t FTEST:1;
-                vuint16_t FFPIN:4;
-                  vuint16_t:4;
-                vuint16_t FFLAG:4;
-            } B;
-        } FSTS;                 /* Fault Status Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t FILT_CNT:3;
-                vuint16_t FILT_PER:8;
-            } B;
-        } FFILT;                /* Fault FilterRegister */
-
-    };                          /* end of FLEXPWM_tag */
-/****************************************************************************/
-/*                          MODULE : ETIMER                                   */
-/****************************************************************************/
-    struct ETIMER_CHANNEL_tag {
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t COMP1:16;
-            } B;
-        } COMP1;                /* Compare Register 1 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t COMP2:16;
-            } B;
-        } COMP2;                /* Compare Register 2 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CAPT1:16;
-            } B;
-        } CAPT1;                /* Capture Register 1 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CAPT2:16;
-            } B;
-        } CAPT2;                /* Capture Register 2 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t LOAD:16;
-            } B;
-        } LOAD;                 /* Load Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t HOLD:16;
-            } B;
-        } HOLD;                 /* Hold Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CNTR:16;
-            } B;
-        } CNTR;                 /* Counter Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CNTMODE:3;
-                vuint16_t PRISRC:5;
-                vuint16_t ONCE:1;
-                vuint16_t LENGTH:1;
-                vuint16_t DIR:1;
-                vuint16_t SECSRC:5;
-            } B;
-        } CTRL;                 /* Control Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t OEN:1;
-                vuint16_t RDNT:1;
-                vuint16_t INPUT:1;
-                vuint16_t VAL:1;
-                vuint16_t FORCE:1;
-                vuint16_t COFRC:1;
-                vuint16_t COINIT:2;
-                vuint16_t SIPS:1;
-                vuint16_t PIPS:1;
-                vuint16_t OPS:1;
-                vuint16_t MSTR:1;
-                vuint16_t OUTMODE:4;
-            } B;
-        } CTRL2;                /* Control Register 2 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t STPEN:1;
-                vuint16_t ROC:2;
-                vuint16_t FMODE:1;
-                vuint16_t FDIS:4;
-                vuint16_t C2FCNT:3;
-                vuint16_t C1FCNT:3;
-                vuint16_t DBGEN:2;
-            } B;
-        } CTRL3;                /* Control Register 3 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:6;
-                vuint16_t WDF:1;
-                vuint16_t RCF:1;
-                vuint16_t ICF2:1;
-                vuint16_t ICF1:1;
-                vuint16_t IEHF:1;
-                vuint16_t IELF:1;
-                vuint16_t TOF:1;
-                vuint16_t TCF2:1;
-                vuint16_t TCF1:1;
-                vuint16_t TCF:1;
-            } B;
-        } STS;                  /* Status Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t ICF2DE:1;
-                vuint16_t ICF1DE:1;
-                vuint16_t CMPLD2DE:1;
-                vuint16_t CMPLD1DE:1;
-                  vuint16_t:2;
-                vuint16_t WDFIE:1;
-                vuint16_t RCFIE:1;
-                vuint16_t ICF2IE:1;
-                vuint16_t ICF1IE:1;
-                vuint16_t IEHFIE:1;
-                vuint16_t IELFIE:1;
-                vuint16_t TOFIE:1;
-                vuint16_t TCF2IE:1;
-                vuint16_t TCF1IE:1;
-                vuint16_t TCFIE:1;
-            } B;
-        } INTDMA;               /* Interrupt and DMA Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CMPLD1:16;
-            } B;
-        } CMPLD1;               /* Compare Load Register 1 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CMPLD2:16;
-            } B;
-        } CMPLD2;               /* Compare Load Register 2 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CLC2:3;
-                vuint16_t CLC1:3;
-                vuint16_t CMPMODE:2;
-                vuint16_t CPT2MODE:2;
-                vuint16_t CPT1MODE:2;
-                vuint16_t CFWM:2;
-                vuint16_t ONESHOT:1;
-                vuint16_t ARM:1;
-            } B;
-        } CCCTRL;               /* Compare and Capture Control Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t FILTCNT:3;
-                vuint16_t FILTPER:8;
-            } B;
-        } FILT;                 /* Input Filter Register */
-
-    };                          /* end of ETIMER_CHANNEL_tag */
-
-    struct ETIMER_tag {
-
-        struct ETIMER_CHANNEL_tag CHANNEL[8];
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t WDTOL:16;
-            } B;
-        } WDTOL;                /* Watchdog Time-out Low Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t WDTOH:16;
-            } B;
-        } WDTOH;                /* Watchdog Time-out High Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t FTEST:1;
-                vuint16_t FIE:4;
-                  vuint16_t:4;
-                vuint16_t FLVL:4;
-            } B;
-        } FCTRL;                /* Fault Control Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:4;
-                vuint16_t FFPIN:4;
-                  vuint16_t:4;
-                vuint16_t FFLAG:4;
-            } B;
-        } FSTS;                 /* Fault Status Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t FFILTCNT:3;
-                vuint16_t FFILTPER:8;
-            } B;
-        } FFILT;                /* Fault Filter Register */
-
-        int16_t ETIMER_reserved1;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t ENBL:8;
-            } B;
-        } ENBL;                 /* Channel Enable Register */
-
-        int16_t ETIMER_reserved2;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:11;
-                vuint16_t DREQ:5;
-            } B;
-        } DREQ[4];              /* DMA Request 0->3 Select Register */
-
-    };                          /* end of ETIMER_tag */
-
-/****************************************************************************/
-/*                          MODULE : CTUL                                   */
-/****************************************************************************/
-    struct CTUL_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t PRESC_CONF:4;
-                  vuint32_t:4;
-                vuint32_t TRGIEN:1;
-                vuint32_t TRGI:1;
-                  vuint32_t:2;
-                vuint32_t CNT3_EN:1;
-                vuint32_t CNT2_EN:1;
-                vuint32_t CNT1_EN:1;
-                vuint32_t CNT0_EN:1;
-            } B;
-        } CSR;                  /* Control Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:23;
-                vuint32_t SV:9;
-            } B;
-        } SVR[7];               /* Start Value Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:23;
-                vuint32_t CV:9;
-            } B;
-        } CVR[4];               /* Current Value Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t TM:1;
-                vuint32_t CNT:2;
-                vuint32_t DELAY:3;
-                  vuint32_t:4;
-                vuint32_t CHANNELVALUE:6;
-            } B;
-        } EVTCFGR[64];          /* Event Configuration Register */
-
-    };                          /* end of CTUL_tag */
-/****************************************************************************/
-/*                          MODULE : CTU                                   */
-/****************************************************************************/
-    struct CTU_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t I15_FE:1;
-                vuint32_t I15_RE:1;
-                vuint32_t I14_FE:1;
-                vuint32_t I14_RE:1;
-                vuint32_t I13_FE:1;
-                vuint32_t I13_RE:1;
-                vuint32_t I12_FE:1;
-                vuint32_t I12_RE:1;
-                vuint32_t I11_FE:1;
-                vuint32_t I11_RE:1;
-                vuint32_t I10_FE:1;
-                vuint32_t I10_RE:1;
-                vuint32_t I9_FE:1;
-                vuint32_t I9_RE:1;
-                vuint32_t I8_FE:1;
-                vuint32_t I8_RE:1;
-                vuint32_t I7_FE:1;
-                vuint32_t I7_RE:1;
-                vuint32_t I6_FE:1;
-                vuint32_t I6_RE:1;
-                vuint32_t I5_FE:1;
-                vuint32_t I5_RE:1;
-                vuint32_t I4_FE:1;
-                vuint32_t I4_RE:1;
-                vuint32_t I3_FE:1;
-                vuint32_t I3_RE:1;
-                vuint32_t I2_FE:1;
-                vuint32_t I2_RE:1;
-                vuint32_t I1_FE:1;
-                vuint32_t I1_RE:1;
-                vuint32_t I0_FE:1;
-                vuint32_t I0_RE:1;
-            } B;
-        } TGSISR;               /* -Trigger Generator Subunit Input Selection Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:7;
-                vuint16_t ETTM:1;
-                vuint16_t PRES:2;
-                vuint16_t MRSSM:5;
-                vuint16_t TGSM:1;
-            } B;
-        } TGSCR;                /* Trigger Generator Subunit Control Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t TCRV:16;
-            } B;
-        } TCR[8];               /* Trigger 0->7 Compare Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t TGSCCV:16;
-            } B;
-        } TGSCCR;               /* TGS Counter Compare Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t TGSCRV:16;
-            } B;
-        } TGSCRR;               /* TGS Counter Reload Register */
-
-        uint16_t CTU_reserved0;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t T3INDEX:5;
-                  vuint32_t:3;
-                vuint32_t T2INDEX:5;
-                  vuint32_t:3;
-                vuint32_t T1INDEX:5;
-                  vuint32_t:3;
-                vuint32_t T0INDEX:5;
-            } B;
-        } CLCR1;                /* Command List Control Register 1 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t T7INDEX:5;
-                  vuint32_t:3;
-                vuint32_t T6INDEX:5;
-                  vuint32_t:3;
-                vuint32_t T5INDEX:5;
-                  vuint32_t:3;
-                vuint32_t T4INDEX:5;
-            } B;
-        } CLCR2;                /* Command List Control Register 2 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t T3E:1;
-                vuint32_t T3ETE:1;
-                vuint32_t T3T1E:1;
-                vuint32_t T3T0E:1;
-                vuint32_t T3ADCE:1;
-                  vuint32_t:3;
-                vuint32_t T2E:1;
-                vuint32_t T2ETE:1;
-                vuint32_t T2T1E:1;
-                vuint32_t T2T0E:1;
-                vuint32_t T2ADCE:1;
-                  vuint32_t:3;
-                vuint32_t T1E:1;
-                vuint32_t T1ETE:1;
-                vuint32_t T1T1E:1;
-                vuint32_t T1T0E:1;
-                vuint32_t T1ADCE:1;
-                  vuint32_t:3;
-                vuint32_t T0E:1;
-                vuint32_t T0ETE:1;
-                vuint32_t T0T1E:1;
-                vuint32_t T0T0E:1;
-                vuint32_t T0ADCE:1;
-            } B;
-        } THCR1;                /* Trigger Handler Control Register 1 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t T7E:1;
-                vuint32_t T7ETE:1;
-                vuint32_t T7T1E:1;
-                vuint32_t T7T0E:1;
-                vuint32_t T7ADCE:1;
-                  vuint32_t:3;
-                vuint32_t T6E:1;
-                vuint32_t T6ETE:1;
-                vuint32_t T6T1E:1;
-                vuint32_t T6T0E:1;
-                vuint32_t T6ADCE:1;
-                  vuint32_t:3;
-                vuint32_t T5E:1;
-                vuint32_t T5ETE:1;
-                vuint32_t T5T1E:1;
-                vuint32_t T5T0E:1;
-                vuint32_t T5ADCE:1;
-                  vuint32_t:3;
-                vuint32_t T4E:1;
-                vuint32_t T4ETE:1;
-                vuint32_t T4T1E:1;
-                vuint32_t T4T0E:1;
-                vuint32_t T4ADCE:1;
-            } B;
-        } THCR2;                /* Trigger Handler Control Register 2 */
-
-        /* Single Conversion Mode - Comment for Dual Conversion Mode */
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t CIR:1;
-                vuint16_t FC:1;
-                vuint16_t CMS:1;
-				vuint16_t:1;
-                vuint16_t FIFO:2;
-                  vuint16_t:4;
-                vuint16_t SU:1;
-                  vuint16_t:1;
-                vuint16_t CH:4;
-            } B;
-        } CLR[24];              /* Commands List Register x (double-buffered) (x = 1,...,24) */
-
-        /* Uncomment for Dual Conversion Mode */
-        /*union {                             
-           vuint16_t R;                      
-           struct {                          
-           vuint16_t CIR:1;                
-           vuint16_t FC:1;                 
-           vuint16_t CMS:1;        
-	vuint16_t:1;
-           vuint16_t FIFO:2;      
-	vuint16_t:1;
-           vuint16_t CHB:4;                
-           vuint16_t :1;                   
-           vuint16_t CHA:4;                
-           } B;                              
-           } CLR[24];                                     */
-        /* Commands List Register x (double-buffered) (x = 1,...,24) */
-
-		uint16_t CTU_reserved1[8];
-		
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:12;
-                vuint16_t DMAEN3:1;
-                vuint16_t DMAEN2:1;
-                vuint16_t DMAEN1:1;
-                vuint16_t DMAEN0:1;
-            } B;
-        } CR;                   /* Control Register */
-
-		   uint16_t CTU_reserved2;
-		   
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FIFO_OVERRUN_EN7:1;
-                vuint32_t FIFO_OVERFLOW_EN7:1;
-                vuint32_t FIFO_EMPTY_EN7:1;
-                vuint32_t FIFO_FULL_EN7:1;
-                vuint32_t FIFO_OVERRUN_EN6:1;
-                vuint32_t FIFO_OVERFLOW_EN6:1;
-                vuint32_t FIFO_EMPTY_EN6:1;
-                vuint32_t FIFO_FULL_EN6:1;
-                vuint32_t FIFO_OVERRUN_EN5:1;
-                vuint32_t FIFO_OVERFLOW_EN5:1;
-                vuint32_t FIFO_EMPTY_EN5:1;
-                vuint32_t FIFO_FULL_EN5:1;
-                vuint32_t FIFO_OVERRUN_EN4:1;
-                vuint32_t FIFO_OVERFLOW_EN4:1;
-                vuint32_t FIFO_EMPTY_EN4:1;
-                vuint32_t FIFO_FULL_EN4:1;
-                vuint32_t FIFO_OVERRUN_EN3:1;
-                vuint32_t FIFO_OVERFLOW_EN3:1;
-                vuint32_t FIFO_EMPTY_EN3:1;
-                vuint32_t FIFO_FULL_EN3:1;
-                vuint32_t FIFO_OVERRUN_EN2:1;
-                vuint32_t FIFO_OVERFLOW_EN2:1;
-                vuint32_t FIFO_EMPTY_EN2:1;
-                vuint32_t FIFO_FULL_EN2:1;
-                vuint32_t FIFO_OVERRUN_EN1:1;
-                vuint32_t FIFO_OVERFLOW_EN1:1;
-                vuint32_t FIFO_EMPTY_EN1:1;
-                vuint32_t FIFO_FULL_EN1:1;
-                vuint32_t FIFO_OVERRUN_EN0:1;
-                vuint32_t FIFO_OVERFLOW_EN0:1;
-                vuint32_t FIFO_EMPTY_EN0:1;
-                vuint32_t FIFO_FULL_EN0:1;
-            } B;
-        } FCR;                  /* CONTROL REGISTER FIFO */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t THRESHOLD3:8;
-                vuint32_t THRESHOLD2:8;
-                vuint32_t THRESHOLD1:8;
-                vuint32_t THRESHOLD0:8;
-            } B;
-        } TH1;                  /* Threshold Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t THRESHOLD7:8;
-                vuint32_t THRESHOLD6:8;
-                vuint32_t THRESHOLD5:8;
-                vuint32_t THRESHOLD4:8;
-            } B;
-        } TH2;                  /* Threshold Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FIFO_OVERRUN7:1;
-                vuint32_t FIFO_OVERFLOW7:1;
-                vuint32_t FIFO_EMPTY7:1;
-                vuint32_t FIFO_FULL7:1;
-                vuint32_t FIFO_OVERRUN6:1;
-                vuint32_t FIFO_OVERFLOW6:1;
-                vuint32_t FIFO_EMPTY6:1;
-                vuint32_t FIFO_FULL6:1;
-                vuint32_t FIFO_OVERRUN5:1;
-                vuint32_t FIFO_OVERFLOW5:1;
-                vuint32_t FIFO_EMPTY5:1;
-                vuint32_t FIFO_FULL5:1;
-                vuint32_t FIFO_OVERRUN4:1;
-                vuint32_t FIFO_OVERFLOW4:1;
-                vuint32_t FIFO_EMPTY4:1;
-                vuint32_t FIFO_FULL4:1;
-                vuint32_t FIFO_OVERRUN3:1;
-                vuint32_t FIFO_OVERFLOW3:1;
-                vuint32_t FIFO_EMPTY3:1;
-                vuint32_t FIFO_FULL3:1;
-                vuint32_t FIFO_OVERRUN2:1;
-                vuint32_t FIFO_OVERFLOW2:1;
-                vuint32_t FIFO_EMPTY2:1;
-                vuint32_t FIFO_FULL2:1;
-                vuint32_t FIFO_OVERRUN1:1;
-                vuint32_t FIFO_OVERFLOW1:1;
-                vuint32_t FIFO_EMPTY1:1;
-                vuint32_t FIFO_FULL1:1;
-                vuint32_t FIFO_OVERRUN0:1;
-                vuint32_t FIFO_OVERFLOW0:1;
-                vuint32_t FIFO_EMPTY0:1;
-                vuint32_t FIFO_FULL0:1;
-            } B;
-        } STATUS;               /* STATUS REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:11;
-                vuint32_t NCH:5;
-                  vuint32_t:6;
-                vuint32_t DATA:10;
-            } B;
-        } FRA[8];               /* FIFO RIGHT aligned REGISTER */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:11;
-                vuint32_t NCH:5;
-                vuint32_t DATA:10;
-                  vuint32_t:6;
-            } B;
-        } FLA[8];               /* FIFO LEFT aligned REGISTER */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:7;
-                vuint16_t ETOE:1;
-                vuint16_t T1OE:1;
-                vuint16_t T0OE:1;
-                vuint16_t ADCOE:1;
-                vuint16_t TGSOSM:1;
-                vuint16_t MRSO:1;
-                vuint16_t ICE:1;
-                vuint16_t SMTO:1;
-                vuint16_t MRSRE:1;
-            } B;
-        } CTUEFR;               /* Cross Triggering Unit Error Flag Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:6;
-                vuint16_t ADC:1;
-                vuint16_t T7:1;
-                vuint16_t T6:1;
-                vuint16_t T5:1;
-                vuint16_t T4:1;
-                vuint16_t T3:1;
-                vuint16_t T2:1;
-                vuint16_t T1:1;
-                vuint16_t T0:1;
-                vuint16_t MRS:1;
-            } B;
-        } CTUIFR;               /* Cross Triggering Unit Interrupt Flag Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t T7IE:1;
-                vuint16_t T6IE:1;
-                vuint16_t T5IE:1;
-                vuint16_t T4IE:1;
-                vuint16_t T3IE:1;
-                vuint16_t T2IE:1;
-                vuint16_t T1IE:1;
-                vuint16_t T0IE:1;
-                  vuint16_t:5;
-                vuint16_t MRSDMAE:1;
-                vuint16_t MRSIE:1;
-                vuint16_t IEE:1;
-            } B;
-        } CTUIR;                /* Cross Triggering Unit Interrupt/DMA Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t COTR:8;
-            } B;
-        } COTR;                 /* Control On-Time Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t T7SG:1;
-                vuint16_t T6SG:1;
-                vuint16_t T5SG:1;
-                vuint16_t T4SG:1;
-                vuint16_t T3SG:1;
-                vuint16_t T2SG:1;
-                vuint16_t T1SG:1;
-                vuint16_t T0SG:1;
-                vuint16_t CTUADCRESET:1;
-                vuint16_t CTUODIS:1;
-                vuint16_t FILTERENABLE:1;
-                vuint16_t CGRE:1;
-                vuint16_t FGRE:1;
-                vuint16_t MRSSG:1;
-                vuint16_t GRE:1;
-                vuint16_t TGSISRRE:1;
-            } B;
-        } CTUCR;                /* Cross Triggering Unit Control Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t FILTERVALUE:8;
-            } B;
-        } CTUFILTER;            /* Cross Triggering Unit Digital Filter */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:15;
-                vuint16_t MDIS:1;
-            } B;
-        } CTUPCR;               /* Cross Triggering Unit Power Control */
-
-    };                          /* end of CTU_tag */
-/****************************************************************************/
-/*                          MODULE : FCU                                   */
-/****************************************************************************/
-    struct FCU_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MCL:1;
-                vuint32_t TM:2;
-                  vuint32_t:19;
-                vuint32_t PS:2;
-                vuint32_t FOM:2;
-                vuint32_t FOP:6;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SRF0:1;
-                vuint32_t SRF1:1;
-                vuint32_t SRF2:1;
-                vuint32_t SRF3:1;
-                vuint32_t SRF4:1;
-                vuint32_t SRF5:1;
-                vuint32_t SRF6:1;
-                vuint32_t SRF7:1;
-                vuint32_t SRF8:1;
-                vuint32_t SRF9:1;
-                vuint32_t SRF10:1;
-                vuint32_t SRF11:1;
-                vuint32_t SRF12:1;
-                vuint32_t SRF13:1;
-                vuint32_t SRF14:1;
-                vuint32_t SRF15:1;
-                vuint32_t HRF15:1;
-                vuint32_t HRF14:1;
-                vuint32_t HRF13:1;
-                vuint32_t HRF12:1;
-                vuint32_t HRF11:1;
-                vuint32_t HRF10:1;
-                vuint32_t HRF9:1;
-                vuint32_t HRF8:1;
-                vuint32_t HRF7:1;
-                vuint32_t HRF6:1;
-                vuint32_t HRF5:1;
-                vuint32_t HRF4:1;
-                vuint32_t HRF3:1;
-                vuint32_t HRF2:1;
-                vuint32_t HRF1:1;
-                vuint32_t HRF0:1;
-            } B;
-        } FFR;                  /* Fault Flag Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FRSRF0:1;
-                vuint32_t FRSRF1:1;
-                vuint32_t FRSRF2:1;
-                vuint32_t FRSRF3:1;
-                vuint32_t FRSRF4:1;
-                vuint32_t FRSRF5:1;
-                vuint32_t FRSRF6:1;
-                vuint32_t FRSRF7:1;
-                vuint32_t FRSRF8:1;
-                vuint32_t FRSRF9:1;
-                vuint32_t FRSRF10:1;
-                vuint32_t FRSRF11:1;
-                vuint32_t FRSRF12:1;
-                vuint32_t FRSRF13:1;
-                vuint32_t FRSRF14:1;
-                vuint32_t FRSRF15:1;
-                vuint32_t FRHRF15:1;
-                vuint32_t FRHRF14:1;
-                vuint32_t FRHRF13:1;
-                vuint32_t FRHRF12:1;
-                vuint32_t FRHRF11:1;
-                vuint32_t FRHRF10:1;
-                vuint32_t FRHRF9:1;
-                vuint32_t FRHRF8:1;
-                vuint32_t FRHRF7:1;
-                vuint32_t FRHRF6:1;
-                vuint32_t FRHRF5:1;
-                vuint32_t FRHRF4:1;
-                vuint32_t FRHRF3:1;
-                vuint32_t FRHRF2:1;
-                vuint32_t FRHRF1:1;
-                vuint32_t FRHRF0:1;
-            } B;
-        } FFFR;                 /* Frozen Fault Flag Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:2;
-                vuint32_t FSRF2:1;
-                vuint32_t FSRF3:1;
-                vuint32_t FSRF4:1;
-                vuint32_t FSRF5:1;
-                vuint32_t FSRF6:1;
-                vuint32_t FSRF7:1;
-                vuint32_t FSRF8:1;
-                vuint32_t FSRF9:1;
-                vuint32_t FSRF10:1;
-                vuint32_t FSRF11:1;
-                vuint32_t FSRF12:1;
-                vuint32_t FSRF13:1;
-                vuint32_t FSRF14:1;
-                vuint32_t FSRF15:1;
-                vuint32_t FHRF15:1;
-                vuint32_t FHRF14:1;
-                vuint32_t FHRF13:1;
-                vuint32_t FHRF12:1;
-                vuint32_t FHRF11:1;
-                vuint32_t FHRF10:1;
-                vuint32_t FHRF9:1;
-                vuint32_t FHRF8:1;
-                vuint32_t FHRF7:1;
-                vuint32_t FHRF6:1;
-                vuint32_t FHRF5:1;
-                vuint32_t FHRF4:1;
-                vuint32_t FHRF3:1;
-                vuint32_t FHRF2:1;
-                vuint32_t FHRF1:1;
-                vuint32_t FHRF0:1;
-            } B;
-        } FFGR;                 /* Fake Fault Generation Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ESF0:1;
-                vuint32_t ESF1:1;
-                vuint32_t ESF2:1;
-                vuint32_t ESF3:1;
-                vuint32_t ESF4:1;
-                vuint32_t ESF5:1;
-                vuint32_t ESF6:1;
-                vuint32_t ESF7:1;
-                vuint32_t ESF8:1;
-                vuint32_t ESF9:1;
-                vuint32_t ESF10:1;
-                vuint32_t ESF11:1;
-                vuint32_t ESF12:1;
-                vuint32_t ESF13:1;
-                vuint32_t ESF14:1;
-                vuint32_t ESF15:1;
-                vuint32_t EHF15:1;
-                vuint32_t EHF14:1;
-                vuint32_t EHF13:1;
-                vuint32_t EHF12:1;
-                vuint32_t EHF11:1;
-                vuint32_t EHF10:1;
-                vuint32_t EHF9:1;
-                vuint32_t EHF8:1;
-                vuint32_t EHF7:1;
-                vuint32_t EHF6:1;
-                vuint32_t EHF5:1;
-                vuint32_t EHF4:1;
-                vuint32_t EHF3:1;
-                vuint32_t EHF2:1;
-                vuint32_t EHF1:1;
-                vuint32_t EHF0:1;
-            } B;
-        } FER;                  /* Fault Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t KR:32;
-            } B;
-        } KR;                   /* Fault Collection Unit Key Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TR:32;
-            } B;
-        } TR;                   /* Fault Collection Unit Timeout Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TESF0:1;
-                vuint32_t TESF1:1;
-                vuint32_t TESF2:1;
-                vuint32_t TESF3:1;
-                vuint32_t TESF4:1;
-                vuint32_t TESF5:1;
-                vuint32_t TESF6:1;
-                vuint32_t TESF7:1;
-                vuint32_t TESF8:1;
-                vuint32_t TESF9:1;
-                vuint32_t TESF10:1;
-                vuint32_t TESF11:1;
-                vuint32_t TESF12:1;
-                vuint32_t TESF13:1;
-                vuint32_t TESF14:1;
-                vuint32_t TESF15:1;
-                vuint32_t TEHF15:1;
-                vuint32_t TEHF14:1;
-                vuint32_t TEHF13:1;
-                vuint32_t TEHF12:1;
-                vuint32_t TEHF11:1;
-                vuint32_t TEHF10:1;
-                vuint32_t TEHF9:1;
-                vuint32_t TEHF8:1;
-                vuint32_t TEHF7:1;
-                vuint32_t TEHF6:1;
-                vuint32_t TEHF5:1;
-                vuint32_t TEHF4:1;
-                vuint32_t TEHF3:1;
-                vuint32_t TEHF2:1;
-                vuint32_t TEHF1:1;
-                vuint32_t TEHF0:1;
-            } B;
-        } TER;                  /* Fault Collection Unit Timeout Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t S0:1;
-                vuint32_t S1:1;
-                vuint32_t S2:1;
-                vuint32_t S3:1;
-            } B;
-        } MSR;                  /* Module state register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t MCPS:4;
-                  vuint32_t:12;
-                vuint32_t MCAS:4;
-            } B;
-        } MCSR;                 /* MC state register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t FRMCPS:4;
-                  vuint32_t:12;
-                vuint32_t FRMCAS:4;
-            } B;
-        } FMCSR;                /* Frozen MC State Register */
-
-    };                          /* end of FCU_tag */
-/****************************************************************************/
-/*                          MODULE : SMC - Stepper Motor Control            */
-/****************************************************************************/
-    struct SMC_tag {
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t MCPRE:2;
-                vuint8_t MCSWAI:1;
-                  vuint8_t:1;
-                vuint8_t DITH:1;
-                  vuint8_t:1;
-                vuint8_t MCTOIF:1;
-            } B;
-        } CTL0;                 /* Motor Controller Control Register 0 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t RECIRC:1;
-                  vuint8_t:6;
-                vuint8_t MCTOIE:1;
-            } B;
-        } CTL1;                 /* Motor Controller Control Register 1 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t P:11;
-            } B;
-        } PER;                  /* Motor Controller Period Register */
-
-        int32_t SMC_reserved0[3];       /* (0x010 - 0x004)/4 = 0x01 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t MCOM:2;
-                vuint8_t MCAM:2;
-                  vuint8_t:2;
-                vuint8_t CD:2;
-            } B;
-        } CC[12];               /* Motor Controller Channel Control Register 0->11 */
-
-        int32_t SMC_reserved1;  /* (0x020 - 0x01C)/4 = 0x01 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t S:5;
-                vuint16_t D:11;
-            } B;
-        } DC[12];               /* Motor Controller Duty Cycle Register 0->11 */
-
-        int8_t SMC_reserved2[8];        /* (0x040 - 0x038) = 0x08 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t TOUT:8;
-            } B;
-        } SDTO;                 /* Shortcut detector time-out register  */
-
-        int8_t SMC_reserved3[3];        /* (0x044 - 0x041) = 0x03 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t EN:8;
-            } B;
-        } SDE[3];               /* Shortcut detector enable register 0->2 */
-
-        int8_t SMC_reserved4;   /* (0x048 - 0x047) = 0x01 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t IRQ_EN:8;
-            } B;
-        } SDIEN[3];             /* Shortcut detector interrupt enable register 0->2 */
-
-        int8_t SMC_reserved5;   /* (0x04C - 0x04B) = 0x01 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t IRQ:8;
-            } B;
-        } SDI[3];               /* Shortcut detector interrupt register 0->2 */
-
-    };                          /* end of SMC_tag */
-/****************************************************************************/
-/*                          MODULE : SSD - Stepper Stall Detect             */
-/****************************************************************************/
-    struct SSD_tag {
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t TRIG:1;
-                vuint16_t STEP:2;
-                vuint16_t RCIR:1;
-                vuint16_t ITGDIR:1;
-                vuint16_t BLNDCL:1;
-                vuint16_t ITGDCL:1;
-                vuint16_t RTZE:1;
-                  vuint16_t:1;
-                vuint16_t BLNST:1;
-                vuint16_t ITGST:1;
-                  vuint16_t:3;
-                vuint16_t SDCPU:1;
-                vuint16_t DZDIS:1;
-            } B;
-        } CONTROL;              /* Control & Status Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t BLNIF:1;
-                vuint16_t ITGIF:1;
-                  vuint16_t:5;
-                vuint16_t ACOVIF:1;
-                vuint16_t BLNIE:1;
-                vuint16_t ITGIE:1;
-                  vuint16_t:5;
-                vuint16_t ACOVIE:1;
-            } B;
-        } IRQ;                  /* Interrupt Flag and Enable Register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t ITGACC:16;
-            } B;
-        } ITGACC;               /* Integrator Accumulator register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t DCNT:16;
-            } B;
-        } DCNT;                 /* Down Counter Count register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t BLNCNTLD:16;
-            } B;
-        } BLNCNTLD;             /* Blanking Counter Load register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t ITGCNTLD:16;
-            } B;
-        } ITGCNTLD;             /* Integration Counter Load register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:1;
-                vuint16_t BLNDIV:3;
-                  vuint16_t:1;
-                vuint16_t ITSSDIV:3;
-                  vuint16_t:2;
-                vuint16_t OFFCNC:2;
-                  vuint16_t:1;
-                vuint16_t ACDIV:3;
-            } B;
-        } PRESCALE;             /* Prescaler register */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t TMST:1;
-                vuint16_t ANLOUT:1;
-                vuint16_t ANLIN:1;
-                vuint16_t SSDEN:1;
-                vuint16_t STEP1:1;
-                vuint16_t POL:1;
-                vuint16_t ITG:1;
-                vuint16_t DACHIZ:1;
-                vuint16_t BUFHIZ:1;
-                vuint16_t AMPHIZ:1;
-                vuint16_t RESSHORT:1;
-                vuint16_t ITSSDRV:1;
-                vuint16_t ITSSDRVEN:1;
-                vuint16_t REFDRV:1;
-                vuint16_t REFDRVEN:1;
-            } B;
-        } FNTEST;               /* Functional Test Mode register */
-
-    };                          /* end of SSD_tag */
-/****************************************************************************/
-/*                          MODULE : EMIOS                                  */
-/****************************************************************************/
-    struct EMIOS_CHANNEL_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t CADR:24;
-            } B;
-        } CADR;                 /* Channel A Data Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t CBDR:24;
-            } B;
-        } CBDR;                 /* Channel B Data Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t CCNTR:24;
-            } B;
-        } CCNTR;                /* Channel Counter Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FREN:1;
-                vuint32_t ODIS:1;
-                vuint32_t ODISSL:2;
-                vuint32_t UCPRE:2;
-                vuint32_t UCPEN:1;
-                vuint32_t DMA:1;
-                  vuint32_t:1;
-                vuint32_t IF:4;
-                vuint32_t FCK:1;
-                vuint32_t FEN:1;
-                  vuint32_t:3;
-                vuint32_t FORCMA:1;
-                vuint32_t FORCMB:1;
-                  vuint32_t:1;
-                vuint32_t BSL:2;
-                vuint32_t EDSEL:1;
-                vuint32_t EDPOL:1;
-                vuint32_t MODE:7;
-            } B;
-        } CCR;                  /* Channel Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t OVR:1;
-                  vuint32_t:15;
-                vuint32_t OVFL:1;
-                  vuint32_t:12;
-                vuint32_t UCIN:1;
-                vuint32_t UCOUT:1;
-                vuint32_t FLAG:1;
-            } B;
-        } CSR;                  /* Channel Status Register */
-
-        union {
-            vuint32_t R;        /* Alternate Channel A Data Register */
-        } ALTCADR;
-
-        uint32_t emios_channel_reserved[2];
-
-    };                          /* end of EMIOS_CHANNEL_tag */
-
-    struct EMIOS_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:1;
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-                vuint32_t GTBE:1;
-                vuint32_t ETB:1;
-                vuint32_t GPREN:1;
-                  vuint32_t:6;
-                vuint32_t SRV:4;
-                vuint32_t GPRE:8;
-                  vuint32_t:8;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t F23:1;
-                vuint32_t F22:1;
-                vuint32_t F21:1;
-                vuint32_t F20:1;
-                vuint32_t F19:1;
-                vuint32_t F18:1;
-                vuint32_t F17:1;
-                vuint32_t F16:1;
-                vuint32_t F15:1;
-                vuint32_t F14:1;
-                vuint32_t F13:1;
-                vuint32_t F12:1;
-                vuint32_t F11:1;
-                vuint32_t F10:1;
-                vuint32_t F9:1;
-                vuint32_t F8:1;
-                vuint32_t F7:1;
-                vuint32_t F6:1;
-                vuint32_t F5:1;
-                vuint32_t F4:1;
-                vuint32_t F3:1;
-                vuint32_t F2:1;
-                vuint32_t F1:1;
-                vuint32_t F0:1;
-            } B;
-        } GFR;                  /* Global FLAG Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t OU23:1;
-                vuint32_t OU22:1;
-                vuint32_t OU21:1;
-                vuint32_t OU20:1;
-                vuint32_t OU19:1;
-                vuint32_t OU18:1;
-                vuint32_t OU17:1;
-                vuint32_t OU16:1;
-                vuint32_t OU15:1;
-                vuint32_t OU14:1;
-                vuint32_t OU13:1;
-                vuint32_t OU12:1;
-                vuint32_t OU11:1;
-                vuint32_t OU10:1;
-                vuint32_t OU9:1;
-                vuint32_t OU8:1;
-                vuint32_t OU7:1;
-                vuint32_t OU6:1;
-                vuint32_t OU5:1;
-                vuint32_t OU4:1;
-                vuint32_t OU3:1;
-                vuint32_t OU2:1;
-                vuint32_t OU1:1;
-                vuint32_t OU0:1;
-            } B;
-        } OUDR;                 /* Output Update Disable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t CHDIS23:1;
-                vuint32_t CHDIS22:1;
-                vuint32_t CHDIS21:1;
-                vuint32_t CHDIS20:1;
-                vuint32_t CHDIS19:1;
-                vuint32_t CHDIS18:1;
-                vuint32_t CHDIS17:1;
-                vuint32_t CHDIS16:1;
-                vuint32_t CHDIS15:1;
-                vuint32_t CHDIS14:1;
-                vuint32_t CHDIS13:1;
-                vuint32_t CHDIS12:1;
-                vuint32_t CHDIS11:1;
-                vuint32_t CHDIS10:1;
-                vuint32_t CHDIS9:1;
-                vuint32_t CHDIS8:1;
-                vuint32_t CHDIS7:1;
-                vuint32_t CHDIS6:1;
-                vuint32_t CHDIS5:1;
-                vuint32_t CHDIS4:1;
-                vuint32_t CHDIS3:1;
-                vuint32_t CHDIS2:1;
-                vuint32_t CHDIS1:1;
-                vuint32_t CHDIS0:1;
-            } B;
-        } UCDIS;                /* Disable Channel Register */
-
-        uint32_t emios_reserved1[4];
-
-        struct EMIOS_CHANNEL_tag CH[28];
-
-    };                          /* end of EMIOS_tag */
-/****************************************************************************/
-/*                          MODULE : pit                                    */
-/****************************************************************************/
-    struct PIT_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t FRZ:1;
-            } B;
-        } PITMCR;
-
-        uint32_t pit_reserved1[63];     /* (0x0100 - 0x0004)/4 = 0x3F */
-
-        struct {
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t TSV:32;
-                } B;
-            } LDVAL;
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t TVL:32;
-                } B;
-            } CVAL;
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:30;
-                    vuint32_t TIE:1;
-                    vuint32_t TEN:1;
-                } B;
-            } TCTRL;
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:31;
-                    vuint32_t TIF:1;
-                } B;
-            } TFLG;
-        } CH[6];
-
-    };                          /* end of PIT_tag */
-/****************************************************************************/
-/*                          MODULE : i2c                                    */
-/****************************************************************************/
-    struct I2C_tag {
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t ADR:7;
-                  vuint8_t:1;
-            } B;
-        } IBAD;                 /* Module Bus Address Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t IBC:8;
-            } B;
-        } IBFD;                 /* Module Bus Frequency Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t MDIS:1;
-                vuint8_t IBIE:1;
-                vuint8_t MS:1;
-                vuint8_t TX:1;
-                vuint8_t NOACK:1;
-                vuint8_t RSTA:1;
-                vuint8_t DMAEN:1;
-                vuint8_t IBDOZE:1;
-            } B;
-        } IBCR;                 /* Module Bus Control Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t TCF:1;
-                vuint8_t IAAS:1;
-                vuint8_t IBB:1;
-                vuint8_t IBAL:1;
-                  vuint8_t:1;
-                vuint8_t SRW:1;
-                vuint8_t IBIF:1;
-                vuint8_t RXAK:1;
-            } B;
-        } IBSR;                 /* Module Status Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t DATA:8;
-            } B;
-        } IBDR;                 /* Module Data Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t BIIE:1;
-                  vuint8_t:7;
-            } B;
-        } IBIC;                 /* Module Interrupt Configuration Register */
-
-    };                          /* end of I2C_tag */
-/****************************************************************************/
-/*                          MODULE : MPU                                    */
-/****************************************************************************/
-    struct MPU_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SPERR:8;
-                  vuint32_t:4;
-                vuint32_t HRL:4;
-                vuint32_t NSP:4;
-                vuint32_t NGRD:4;
-                  vuint32_t:7;
-                vuint32_t VLD:1;
-            } B;
-        } CESR;                 /* Module Control/Error Status Register */
-
-        uint32_t mpu_reserved1[3];      /* (0x010 - 0x004)/4 = 0x03 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EADDR:32;
-            } B;
-        } EAR0;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EACD:16;
-                vuint32_t EPID:8;
-                vuint32_t EMN:4;
-                vuint32_t EATTR:3;
-                vuint32_t ERW:1;
-            } B;
-        } EDR0;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EADDR:32;
-            } B;
-        } EAR1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EACD:16;
-                vuint32_t EPID:8;
-                vuint32_t EMN:4;
-                vuint32_t EATTR:3;
-                vuint32_t ERW:1;
-            } B;
-        } EDR1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EADDR:32;
-            } B;
-        } EAR2;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EACD:16;
-                vuint32_t EPID:8;
-                vuint32_t EMN:4;
-                vuint32_t EATTR:3;
-                vuint32_t ERW:1;
-            } B;
-        } EDR2;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EADDR:32;
-            } B;
-        } EAR3;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EACD:16;
-                vuint32_t EPID:8;
-                vuint32_t EMN:4;
-                vuint32_t EATTR:3;
-                vuint32_t ERW:1;
-            } B;
-        } EDR3;
-
-        uint32_t mpu_reserved2[244];    /* (0x0400 - 0x0030)/4 = 0x0F4 */
-
-        struct {
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t SRTADDR:27;
-                      vuint32_t:5;
-                } B;
-            } WORD0;            /* Region Descriptor n Word 0 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t ENDADDR:27;
-                      vuint32_t:5;
-                } B;
-            } WORD1;            /* Region Descriptor n Word 1 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t M7RE:1;
-                    vuint32_t M7WE:1;
-                    vuint32_t M6RE:1;
-                    vuint32_t M6WE:1;
-                    vuint32_t M5RE:1;
-                    vuint32_t M5WE:1;
-                    vuint32_t M4RE:1;
-                    vuint32_t M4WE:1;
-                    vuint32_t M3PE:1;
-                    vuint32_t M3SM:2;
-                    vuint32_t M3UM:3;
-                    vuint32_t M2PE:1;
-                    vuint32_t M2SM:2;
-                    vuint32_t M2UM:3;
-                    vuint32_t M1PE:1;
-                    vuint32_t M1SM:2;
-                    vuint32_t M1UM:3;
-                    vuint32_t M0PE:1;
-                    vuint32_t M0SM:2;
-                    vuint32_t M0UM:3;
-                } B;
-            } WORD2;            /* Region Descriptor n Word 2 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t PID:8;
-                    vuint32_t PIDMASK:8;
-                      vuint32_t:15;
-                    vuint32_t VLD:1;
-                } B;
-            } WORD3;            /* Region Descriptor n Word 3 */
-
-        } RGD[16];
-
-        uint32_t mpu_reserved3[192];    /* (0x0800 - 0x0500)/4 = 0x0C0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t M7RE:1;
-                vuint32_t M7WE:1;
-                vuint32_t M6RE:1;
-                vuint32_t M6WE:1;
-                vuint32_t M5RE:1;
-                vuint32_t M5WE:1;
-                vuint32_t M4RE:1;
-                vuint32_t M4WE:1;
-                vuint32_t M3PE:1;
-                vuint32_t M3SM:2;
-                vuint32_t M3UM:3;
-                vuint32_t M2PE:1;
-                vuint32_t M2SM:2;
-                vuint32_t M2UM:3;
-                vuint32_t M1PE:1;
-                vuint32_t M1SM:2;
-                vuint32_t M1UM:3;
-                vuint32_t M0PE:1;
-                vuint32_t M0SM:2;
-                vuint32_t M0UM:3;
-            } B;
-        } RGDAAC[16];           /* Region Descriptor Alternate Access Control n */
-
-    };                          /* end of MPU_tag */
-/****************************************************************************/
-/*                          MODULE : eDMA                                   */
-/****************************************************************************/
-
-/*for "standard" format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0) */
-    struct EDMA_TCD_STD_tag {
-
-        vuint32_t SADDR;        /* source address */
-
-        vuint16_t SMOD:5;       /* source address modulo */
-        vuint16_t SSIZE:3;      /* source transfer size */
-        vuint16_t DMOD:5;       /* destination address modulo */
-        vuint16_t DSIZE:3;      /* destination transfer size */
-        vint16_t SOFF;          /* signed source address offset */
-
-        vuint32_t NBYTES;       /* inner (�minor�) byte count */
-
-        vint32_t SLAST;         /* last destination address adjustment, or
-                                   scatter/gather address (if e_sg = 1) */
-
-        vuint32_t DADDR;        /* destination address */
-
-        vuint16_t CITERE_LINK:1;
-        vuint16_t CITER:15;
-
-        vint16_t DOFF;          /* signed destination address offset */
-
-        vint32_t DLAST_SGA;
-
-        vuint16_t BITERE_LINK:1;        /* beginning ("major") iteration count */
-        vuint16_t BITER:15;
-
-        vuint16_t BWC:2;        /* bandwidth control */
-        vuint16_t MAJORLINKCH:6;        /* enable channel-to-channel link */
-        vuint16_t DONE:1;       /* channel done */
-        vuint16_t ACTIVE:1;     /* channel active */
-        vuint16_t MAJORE_LINK:1;        /* enable channel-to-channel link */
-        vuint16_t E_SG:1;       /* enable scatter/gather descriptor */
-        vuint16_t D_REQ:1;      /* disable ipd_req when done */
-        vuint16_t INT_HALF:1;   /* interrupt on citer = (biter >> 1) */
-        vuint16_t INT_MAJ:1;    /* interrupt on major loop completion */
-        vuint16_t START:1;      /* explicit channel start */
-
-    };                          /* end of EDMA_TCD_STD_tag */
-
-/*for "channel link" format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1)*/
-    struct EDMA_TCD_CHLINK_tag {
-
-        vuint32_t SADDR;        /* source address */
-
-        vuint16_t SMOD:5;       /* source address modulo */
-        vuint16_t SSIZE:3;      /* source transfer size */
-        vuint16_t DMOD:5;       /* destination address modulo */
-        vuint16_t DSIZE:3;      /* destination transfer size */
-        vint16_t SOFF;          /* signed source address offset */
-
-        vuint32_t NBYTES;       /* inner (�minor�) byte count */
-
-        vint32_t SLAST;         /* last destination address adjustment, or
-                                   scatter/gather address (if e_sg = 1) */
-
-        vuint32_t DADDR;        /* destination address */
-
-        vuint16_t CITERE_LINK:1;
-        vuint16_t CITERLINKCH:6;
-        vuint16_t CITER:9;
-
-        vint16_t DOFF;          /* signed destination address offset */
-
-        vint32_t DLAST_SGA;
-
-        vuint16_t BITERE_LINK:1;        /* beginning (�major�) iteration count */
-        vuint16_t BITERLINKCH:6;
-        vuint16_t BITER:9;
-
-        vuint16_t BWC:2;        /* bandwidth control */
-        vuint16_t MAJORLINKCH:6;        /* enable channel-to-channel link */
-        vuint16_t DONE:1;       /* channel done */
-        vuint16_t ACTIVE:1;     /* channel active */
-        vuint16_t MAJORE_LINK:1;        /* enable channel-to-channel link */
-        vuint16_t E_SG:1;       /* enable scatter/gather descriptor */
-        vuint16_t D_REQ:1;      /* disable ipd_req when done */
-        vuint16_t INT_HALF:1;   /* interrupt on citer = (biter >> 1) */
-        vuint16_t INT_MAJ:1;    /* interrupt on major loop completion */
-        vuint16_t START:1;      /* explicit channel start */
-
-    };                          /* end of EDMA_TCD_CHLINK_tag */
-
-    struct EDMA_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:29;
-                vuint32_t ERCA:1;
-                vuint32_t EDBG:1;
-                  vuint32_t:1;
-            } B;
-        } CR;                   /* Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t VLD:1;
-                  vuint32_t:15;
-                vuint32_t GPE:1;
-                vuint32_t CPE:1;
-                vuint32_t ERRCHN:6;
-                vuint32_t SAE:1;
-                vuint32_t SOE:1;
-                vuint32_t DAE:1;
-                vuint32_t DOE:1;
-                vuint32_t NCE:1;
-                vuint32_t SGE:1;
-                vuint32_t SBE:1;
-                vuint32_t DBE:1;
-            } B;
-        } ESR;                  /* Error Status Register */
-
-        int16_t EDMA_reserved1[3];      /* (0x0E - 0x08)/2 = 0x03 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t ERQ15:1;
-                vuint16_t ERQ14:1;
-                vuint16_t ERQ13:1;
-                vuint16_t ERQ12:1;
-                vuint16_t ERQ11:1;
-                vuint16_t ERQ10:1;
-                vuint16_t ERQ09:1;
-                vuint16_t ERQ08:1;
-                vuint16_t ERQ07:1;
-                vuint16_t ERQ06:1;
-                vuint16_t ERQ05:1;
-                vuint16_t ERQ04:1;
-                vuint16_t ERQ03:1;
-                vuint16_t ERQ02:1;
-                vuint16_t ERQ01:1;
-                vuint16_t ERQ00:1;
-            } B;
-        } ERQRL;                /* DMA Enable Request Register Low */
-
-        int16_t EDMA_reserved2[3];      /* (0x16 - 0x10)/2 = 0x03 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t EEI15:1;
-                vuint16_t EEI14:1;
-                vuint16_t EEI13:1;
-                vuint16_t EEI12:1;
-                vuint16_t EEI11:1;
-                vuint16_t EEI10:1;
-                vuint16_t EEI09:1;
-                vuint16_t EEI08:1;
-                vuint16_t EEI07:1;
-                vuint16_t EEI06:1;
-                vuint16_t EEI05:1;
-                vuint16_t EEI04:1;
-                vuint16_t EEI03:1;
-                vuint16_t EEI02:1;
-                vuint16_t EEI01:1;
-                vuint16_t EEI00:1;
-            } B;
-        } EEIRL;                /* DMA Enable Error Interrupt Register Low */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t SERQ:7;
-            } B;
-        } SERQR;                /* DMA Set Enable Request Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t CERQ:7;
-            } B;
-        } CERQR;                /* DMA Clear Enable Request Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t SEEI:7;
-            } B;
-        } SEEIR;                /* DMA Set Enable Error Interrupt Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t CEEI:7;
-            } B;
-        } CEEIR;                /* DMA Clear Enable Error Interrupt Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t CINT:7;
-            } B;
-        } CIRQR;                /* DMA Clear Interrupt Request Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t CER:7;
-            } B;
-        } CERR;                 /* DMA Clear error Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t SSB:7;
-            } B;
-        } SSBR;                 /* Set Start Bit Register */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:1;
-                vuint8_t CDSB:7;
-            } B;
-        } CDSBR;                /* Clear Done Status Bit Register */
-
-        int16_t EDMA_reserved3[3];      /* (0x26 - 0x20)/2 = 0x03 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t INT15:1;
-                vuint16_t INT14:1;
-                vuint16_t INT13:1;
-                vuint16_t INT12:1;
-                vuint16_t INT11:1;
-                vuint16_t INT10:1;
-                vuint16_t INT09:1;
-                vuint16_t INT08:1;
-                vuint16_t INT07:1;
-                vuint16_t INT06:1;
-                vuint16_t INT05:1;
-                vuint16_t INT04:1;
-                vuint16_t INT03:1;
-                vuint16_t INT02:1;
-                vuint16_t INT01:1;
-                vuint16_t INT00:1;
-            } B;
-        } IRQRL;                /* DMA Interrupt Request Low */
-
-        int16_t EDMA_reserved4[3];      /* (0x2E - 0x28)/2 = 0x03 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t ERR15:1;
-                vuint16_t ERR14:1;
-                vuint16_t ERR13:1;
-                vuint16_t ERR12:1;
-                vuint16_t ERR11:1;
-                vuint16_t ERR10:1;
-                vuint16_t ERR09:1;
-                vuint16_t ERR08:1;
-                vuint16_t ERR07:1;
-                vuint16_t ERR06:1;
-                vuint16_t ERR05:1;
-                vuint16_t ERR04:1;
-                vuint16_t ERR03:1;
-                vuint16_t ERR02:1;
-                vuint16_t ERR01:1;
-                vuint16_t ERR00:1;
-            } B;
-        } ERL;                  /* DMA Error Low */
-
-        int16_t EDMA_reserved5[3];      /* (0x36 - 0x30)/2 = 0x03 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t HRS15:1;
-                vuint16_t HRS14:1;
-                vuint16_t HRS13:1;
-                vuint16_t HRS12:1;
-                vuint16_t HRS11:1;
-                vuint16_t HRS10:1;
-                vuint16_t HRS09:1;
-                vuint16_t HRS08:1;
-                vuint16_t HRS07:1;
-                vuint16_t HRS06:1;
-                vuint16_t HRS05:1;
-                vuint16_t HRS04:1;
-                vuint16_t HRS03:1;
-                vuint16_t HRS02:1;
-                vuint16_t HRS01:1;
-                vuint16_t HRS00:1;
-            } B;
-        } HRSL;                 /* DMA Hardware Request Status Low */
-
-        uint32_t edma_reserved1[50];    /* (0x100 - 0x038)/4 = 0x32 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t ECP:1;
-                vuint8_t DPA:1;
-                vuint8_t GRPPRI:2;
-                vuint8_t CHPRI:4;
-            } B;
-        } CPR[16];              /* Channel n Priority */
-
-        uint32_t edma_reserved2[956];   /* (0x1000 - 0x0110)/4 = 0x3BC */
-
-        struct EDMA_TCD_STD_tag TCD[16];
-        /* struct EDMA_TCD_CHLINK_tag TCD[16]; */
-
-    };                          /* end of EDMA_tag */
-/****************************************************************************/
-/*                          MODULE : INTC                                   */
-/****************************************************************************/
-    struct INTC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:26;
-                vuint32_t VTES:1;
-                  vuint32_t:4;
-                vuint32_t HVEN:1;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t PRI:4;
-            } B;
-        } CPR;                  /* Current Priority Register */
-
-        int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t VTBA:21;
-                vuint32_t INTVEC:9;
-                  vuint32_t:2;
-            } B;
-        } IACKR;                /* Interrupt Acknowledge Register */
-
-        int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:32;
-            } B;
-        } EOIR;                 /* End of Interrupt Register */
-
-        int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:6;
-                vuint8_t SET:1;
-                vuint8_t CLR:1;
-            } B;
-        } SSCIR[8];             /* Software Set/Clear Interruput Register */
-
-        uint32_t intc_reserved5[6];     /* (0x040 - 0x028)/4 = 0x06 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t PRI:4;
-            } B;
-        } PSR[512];             /* Software Set/Clear Interrupt Register */
-
-    };                          /* end of INTC_tag */
-/****************************************************************************/
-/*                          MODULE : DSPI                                   */
-/****************************************************************************/
-    struct DSPI_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MSTR:1;
-                vuint32_t CONT_SCKE:1;
-                vuint32_t DCONF:2;
-                vuint32_t FRZ:1;
-                vuint32_t MTFE:1;
-                vuint32_t PCSSE:1;
-                vuint32_t ROOE:1;
-		vuint32_t PCSIS7:1;
-		vuint32_t PCSIS6:1;
-                vuint32_t PCSIS5:1;
-                vuint32_t PCSIS4:1;
-                vuint32_t PCSIS3:1;
-                vuint32_t PCSIS2:1;
-                vuint32_t PCSIS1:1;
-                vuint32_t PCSIS0:1;
-                vuint32_t:1;
-                vuint32_t MDIS:1;
-                vuint32_t DIS_TXF:1;
-                vuint32_t DIS_RXF:1;
-                vuint32_t CLR_TXF:1;
-                vuint32_t CLR_RXF:1;
-                vuint32_t SMPL_PT:2;
-                  vuint32_t:7;
-                vuint32_t HALT:1;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        uint32_t dspi_reserved1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCNT:16;
-                  vuint32_t:16;
-            } B;
-        } TCR;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DBR:1;
-                vuint32_t FMSZ:4;
-                vuint32_t CPOL:1;
-                vuint32_t CPHA:1;
-                vuint32_t LSBFE:1;
-                vuint32_t PCSSCK:2;
-                vuint32_t PASC:2;
-                vuint32_t PDT:2;
-                vuint32_t PBR:2;
-                vuint32_t CSSCK:4;
-                vuint32_t ASC:4;
-                vuint32_t DT:4;
-                vuint32_t BR:4;
-            } B;
-        } CTAR[8];              /* Clock and Transfer Attributes Registers */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCF:1;
-                vuint32_t TXRXS:1;
-                  vuint32_t:1;
-                vuint32_t EOQF:1;
-                vuint32_t TFUF:1;
-                  vuint32_t:1;
-                vuint32_t TFFF:1;
-                  vuint32_t:5;
-                vuint32_t RFOF:1;
-                  vuint32_t:1;
-                vuint32_t RFDF:1;
-                  vuint32_t:1;
-                vuint32_t TXCTR:4;
-                vuint32_t TXNXTPTR:4;
-                vuint32_t RXCTR:4;
-                vuint32_t POPNXTPTR:4;
-            } B;
-        } SR;                   /* Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCFRE:1;
-                  vuint32_t:2;
-                vuint32_t EOQFRE:1;
-                vuint32_t TFUFRE:1;
-                  vuint32_t:1;
-                vuint32_t TFFFRE:1;
-                vuint32_t TFFFDIRS:1;
-                  vuint32_t:4;
-                vuint32_t RFOFRE:1;
-                  vuint32_t:1;
-                vuint32_t RFDFRE:1;
-                vuint32_t RFDFDIRS:1;
-                  vuint32_t:16;
-            } B;
-        } RSER;                 /* DMA/Interrupt Request Select and Enable Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CONT:1;
-                vuint32_t CTAS:3;
-                vuint32_t EOQ:1;
-                vuint32_t CTCNT:1;
-                  vuint32_t:2;
-		vuint32_t PCS7:1;
-		vuint32_t PCS6:1;
-                vuint32_t PCS5:1;
-                vuint32_t PCS4:1;
-                vuint32_t PCS3:1;
-                vuint32_t PCS2:1;
-                vuint32_t PCS1:1;
-                vuint32_t PCS0:1;
-                vuint32_t TXDATA:16;
-            } B;
-        } PUSHR;                /* PUSH TX FIFO Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXDATA:16;
-            } B;
-        } POPR;                 /* POP RX FIFO Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TXCMD:16;
-                vuint32_t TXDATA:16;
-            } B;
-        } TXFR[5];              /* Transmit FIFO Registers */
-
-        vuint32_t DSPI_reserved_txf[11];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXDATA:16;
-            } B;
-        } RXFR[5];              /* Receive FIFO Registers */
-
-        vuint32_t DSPI_reserved_rxf[12];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MTOE:1;
-                  vuint32_t:1;
-                vuint32_t MTOCNT:6;
-                  vuint32_t:4;
-                vuint32_t TXSS:1;
-                vuint32_t TPOL:1;
-                vuint32_t TRRE:1;
-                vuint32_t CID:1;
-                vuint32_t DCONT:1;
-                vuint32_t DSICTAS:3;
-                  vuint32_t:6;
-                vuint32_t DPCS5:1;
-                vuint32_t DPCS4:1;
-                vuint32_t DPCS3:1;
-                vuint32_t DPCS2:1;
-                vuint32_t DPCS1:1;
-                vuint32_t DPCS0:1;
-            } B;
-        } DSICR;                /* DSI Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t SER_DATA:16;
-            } B;
-        } SDR;                  /* DSI Serialization Data Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t ASER_DATA:16;
-            } B;
-        } ASDR;                 /* DSI Alternate Serialization Data Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t COMP_DATA:16;
-            } B;
-        } COMPR;                /* DSI Transmit Comparison Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t DESER_DATA:16;
-            } B;
-        } DDR;                  /* DSI deserialization Data Register */
-
-    };                          /* end of DSPI_tag */
-/****************************************************************************/
-/*                          MODULE : FlexCAN                                */
-/****************************************************************************/
-    struct FLEXCAN_BUF_t {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t CODE:4;
-                  vuint32_t:1;
-                vuint32_t SRR:1;
-                vuint32_t IDE:1;
-                vuint32_t RTR:1;
-                vuint32_t LENGTH:4;
-                vuint32_t TIMESTAMP:16;
-            } B;
-        } CS;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRIO:3;
-                vuint32_t STD_ID:11;
-                vuint32_t EXT_ID:18;
-            } B;
-        } ID;
-
-        union {
-            /*vuint8_t  B[8]; *//* Data buffer in Bytes (8 bits) */
-            /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
-            vuint32_t W[2];     /* Data buffer in words (32 bits) */
-            /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
-        } DATA;
-
-    };                          /* end of FLEXCAN_BUF_t */
-
-    struct FLEXCAN_RXFIFO_t {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:9;
-                vuint32_t SRR:1;
-                vuint32_t IDE:1;
-                vuint32_t RTR:1;
-                vuint32_t LENGTH:4;
-                vuint32_t TIMESTAMP:16;
-            } B;
-        } CS;
-
-        union {
-            vuint32_t R;
-            struct {
-		vuint32_t:3;
-                vuint32_t STD_ID:11;
-                vuint32_t EXT_ID:18;
-            } B;
-        } ID;
-
-        union {
-            /*vuint8_t  B[8]; *//* Data buffer in Bytes (8 bits) */
-            /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
-            vuint32_t W[2];     /* Data buffer in words (32 bits) */
-            /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
-        } DATA;
-
-        uint32_t FLEXCAN_RXFIFO_reserved[20];   /* {0x00E0-0x0090}/0x4 = 0x14 */
-
-        union {
-            vuint32_t R;
-        } IDTABLE[8];
-
-    };                          /* end of FLEXCAN_RXFIFO_t */
-
-    struct FLEXCAN_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-                vuint32_t FEN:1;
-                vuint32_t HALT:1;
-                vuint32_t NOTRDY:1;
-                vuint32_t WAKMSK:1;
-                vuint32_t SOFTRST:1;
-                vuint32_t FRZACK:1;
-                vuint32_t SUPV:1;
-                vuint32_t SLFWAK:1;
-                vuint32_t WRNEN:1;
-                vuint32_t LPMACK:1;
-                vuint32_t WAKSRC:1;
-                vuint32_t:1;
-                vuint32_t SRXDIS:1;
-                vuint32_t BCC:1;
-                  vuint32_t:2;
-                vuint32_t LPRIO_EN:1;
-                vuint32_t AEN:1;
-                  vuint32_t:2;
-                vuint32_t IDAM:2;
-                  vuint32_t:2;
-                vuint32_t MAXMB:6;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRESDIV:8;
-                vuint32_t RJW:2;
-                vuint32_t PSEG1:3;
-                vuint32_t PSEG2:3;
-                vuint32_t BOFFMSK:1;
-                vuint32_t ERRMSK:1;
-                vuint32_t CLKSRC:1;
-                vuint32_t LPB:1;
-                vuint32_t TWRNMSK:1;
-                vuint32_t RWRNMSK:1;
-                  vuint32_t:2;
-                vuint32_t SMP:1;
-                vuint32_t BOFFREC:1;
-                vuint32_t TSYN:1;
-                vuint32_t LBUF:1;
-                vuint32_t LOM:1;
-                vuint32_t PROPSEG:3;
-            } B;
-        } CR;                   /* Control Register */
-
-        union {
-            vuint32_t R;
-        } TIMER;                /* Free Running Timer */
-
-        uint32_t FLEXCAN_reserved1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;
-        } RXGMASK;              /* RX Global Mask */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;
-        } RX14MASK;             /* RX 14 Mask */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;
-        } RX15MASK;             /* RX 15 Mask */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXECNT:8;
-                vuint32_t TXECNT:8;
-            } B;
-        } ECR;                  /* Error Counter Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t TWRNINT:1;
-                vuint32_t RWRNINT:1;
-                vuint32_t BIT1ERR:1;
-                vuint32_t BIT0ERR:1;
-                vuint32_t ACKERR:1;
-                vuint32_t CRCERR:1;
-                vuint32_t FRMERR:1;
-                vuint32_t STFERR:1;
-                vuint32_t TXWRN:1;
-                vuint32_t RXWRN:1;
-                vuint32_t IDLE:1;
-                vuint32_t TXRX:1;
-                vuint32_t FLTCONF:2;
-                  vuint32_t:1;
-                vuint32_t BOFFINT:1;
-                vuint32_t ERRINT:1;
-                vuint32_t WAKINT:1;
-            } B;
-        } ESR;                  /* Error and Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF63M:1;
-                vuint32_t BUF62M:1;
-                vuint32_t BUF61M:1;
-                vuint32_t BUF60M:1;
-                vuint32_t BUF59M:1;
-                vuint32_t BUF58M:1;
-                vuint32_t BUF57M:1;
-                vuint32_t BUF56M:1;
-                vuint32_t BUF55M:1;
-                vuint32_t BUF54M:1;
-                vuint32_t BUF53M:1;
-                vuint32_t BUF52M:1;
-                vuint32_t BUF51M:1;
-                vuint32_t BUF50M:1;
-                vuint32_t BUF49M:1;
-                vuint32_t BUF48M:1;
-                vuint32_t BUF47M:1;
-                vuint32_t BUF46M:1;
-                vuint32_t BUF45M:1;
-                vuint32_t BUF44M:1;
-                vuint32_t BUF43M:1;
-                vuint32_t BUF42M:1;
-                vuint32_t BUF41M:1;
-                vuint32_t BUF40M:1;
-                vuint32_t BUF39M:1;
-                vuint32_t BUF38M:1;
-                vuint32_t BUF37M:1;
-                vuint32_t BUF36M:1;
-                vuint32_t BUF35M:1;
-                vuint32_t BUF34M:1;
-                vuint32_t BUF33M:1;
-                vuint32_t BUF32M:1;
-            } B;
-        } IMRH;                 /* Interruput Masks Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF31M:1;
-                vuint32_t BUF30M:1;
-                vuint32_t BUF29M:1;
-                vuint32_t BUF28M:1;
-                vuint32_t BUF27M:1;
-                vuint32_t BUF26M:1;
-                vuint32_t BUF25M:1;
-                vuint32_t BUF24M:1;
-                vuint32_t BUF23M:1;
-                vuint32_t BUF22M:1;
-                vuint32_t BUF21M:1;
-                vuint32_t BUF20M:1;
-                vuint32_t BUF19M:1;
-                vuint32_t BUF18M:1;
-                vuint32_t BUF17M:1;
-                vuint32_t BUF16M:1;
-                vuint32_t BUF15M:1;
-                vuint32_t BUF14M:1;
-                vuint32_t BUF13M:1;
-                vuint32_t BUF12M:1;
-                vuint32_t BUF11M:1;
-                vuint32_t BUF10M:1;
-                vuint32_t BUF09M:1;
-                vuint32_t BUF08M:1;
-                vuint32_t BUF07M:1;
-                vuint32_t BUF06M:1;
-                vuint32_t BUF05M:1;
-                vuint32_t BUF04M:1;
-                vuint32_t BUF03M:1;
-                vuint32_t BUF02M:1;
-                vuint32_t BUF01M:1;
-                vuint32_t BUF00M:1;
-            } B;
-        } IMRL;                 /* Interruput Masks Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF63I:1;
-                vuint32_t BUF62I:1;
-                vuint32_t BUF61I:1;
-                vuint32_t BUF60I:1;
-                vuint32_t BUF59I:1;
-                vuint32_t BUF58I:1;
-                vuint32_t BUF57I:1;
-                vuint32_t BUF56I:1;
-                vuint32_t BUF55I:1;
-                vuint32_t BUF54I:1;
-                vuint32_t BUF53I:1;
-                vuint32_t BUF52I:1;
-                vuint32_t BUF51I:1;
-                vuint32_t BUF50I:1;
-                vuint32_t BUF49I:1;
-                vuint32_t BUF48I:1;
-                vuint32_t BUF47I:1;
-                vuint32_t BUF46I:1;
-                vuint32_t BUF45I:1;
-                vuint32_t BUF44I:1;
-                vuint32_t BUF43I:1;
-                vuint32_t BUF42I:1;
-                vuint32_t BUF41I:1;
-                vuint32_t BUF40I:1;
-                vuint32_t BUF39I:1;
-                vuint32_t BUF38I:1;
-                vuint32_t BUF37I:1;
-                vuint32_t BUF36I:1;
-                vuint32_t BUF35I:1;
-                vuint32_t BUF34I:1;
-                vuint32_t BUF33I:1;
-                vuint32_t BUF32I:1;
-            } B;
-        } IFRH;                 /* Interruput Flag Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF31I:1;
-                vuint32_t BUF30I:1;
-                vuint32_t BUF29I:1;
-                vuint32_t BUF28I:1;
-                vuint32_t BUF27I:1;
-                vuint32_t BUF26I:1;
-                vuint32_t BUF25I:1;
-                vuint32_t BUF24I:1;
-                vuint32_t BUF23I:1;
-                vuint32_t BUF22I:1;
-                vuint32_t BUF21I:1;
-                vuint32_t BUF20I:1;
-                vuint32_t BUF19I:1;
-                vuint32_t BUF18I:1;
-                vuint32_t BUF17I:1;
-                vuint32_t BUF16I:1;
-                vuint32_t BUF15I:1;
-                vuint32_t BUF14I:1;
-                vuint32_t BUF13I:1;
-                vuint32_t BUF12I:1;
-                vuint32_t BUF11I:1;
-                vuint32_t BUF10I:1;
-                vuint32_t BUF09I:1;
-                vuint32_t BUF08I:1;
-                vuint32_t BUF07I:1;
-                vuint32_t BUF06I:1;
-                vuint32_t BUF05I:1;
-                vuint32_t BUF04I:1;
-                vuint32_t BUF03I:1;
-                vuint32_t BUF02I:1;
-                vuint32_t BUF01I:1;
-                vuint32_t BUF00I:1;
-            } B;
-        } IFRL;                 /* Interruput Flag Register */
-
-        uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */
-
-/****************************************************************************/
-/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure     */
-/****************************************************************************/
-        /* Standard Buffer Structure */
-        struct FLEXCAN_BUF_t BUF[64];
-
-        /* RX FIFO and Buffer Structure */
-        /*struct FLEXCAN_RXFIFO_t RXFIFO; */
-        /*struct FLEXCAN_BUF_t BUF[56];   */
-/****************************************************************************/
-
-        uint32_t FLEXCAN_reserved3[256];        /* {0x0880-0x0480}/0x4 = 0x100 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;
-        } RXIMR[64];            /* RX Individual Mask Registers */
-
-    };                          /* end of FLEXCAN_tag */
-/****************************************************************************/
-/*                          MODULE : DMAMUX                                 */
-/****************************************************************************/
-    struct DMAMUX_tag {
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t ENBL:1;
-                vuint8_t TRIG:1;
-                vuint8_t SOURCE:6;
-            } B;
-        } CHCONFIG[16];         /* DMA Channel Configuration Register */
-
-    };                          /* end of DMAMUX_tag */
-/****************************************************************************/
-/*                          MODULE : FlexRay                                */
-/****************************************************************************/
-
-    typedef union uMVR {
-        vuint16_t R;
-        struct {
-            vuint16_t CHIVER:8; /* CHI Version Number */
-            vuint16_t PEVER:8;  /* PE Version Number */
-        } B;
-    } MVR_t;
-
-    typedef union uMCR {
-        vuint16_t R;
-        struct {
-            vuint16_t MEN:1;    /* module enable */
-              vuint16_t:1;
-            vuint16_t SCMD:1;   /* single channel mode */
-            vuint16_t CHB:1;    /* channel B enable */
-            vuint16_t CHA:1;    /* channel A enable */
-            vuint16_t SFFE:1;   /* synchronization frame filter enable */
-              vuint16_t:5;
-            vuint16_t CLKSEL:1; /* protocol engine clock source select */
-            vuint16_t BITRATE:3;       /* protocol engine clock prescaler */
-              vuint16_t:1;
-        } B;
-    } MCR_t;
-    typedef union uSTBSCR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-            vuint16_t STBSSEL:7;        /* strobe signal select */
-              vuint16_t:3;
-            vuint16_t ENB:1;    /* strobe signal enable */
-              vuint16_t:2;
-            vuint16_t STBPSEL:2;        /* strobe port select */
-        } B;
-    } STBSCR_t;
-    typedef union uSTBPCR {
-        vuint16_t R;
-        struct {
-            vuint16_t:12;
-            vuint16_t STB3EN:1; /* strobe port enable */
-            vuint16_t STB2EN:1; /* strobe port enable */
-            vuint16_t STB1EN:1; /* strobe port enable */
-            vuint16_t STB0EN:1; /* strobe port enable */
-        } B;
-    } STBPCR_t;
-
-    typedef union uMBDSR {
-        vuint16_t R;
-        struct {
-            vuint16_t:1;
-            vuint16_t MBSEG2DS:7;       /* message buffer segment 2 data size */
-              vuint16_t:1;
-            vuint16_t MBSEG1DS:7;       /* message buffer segment 1 data size */
-        } B;
-    } MBDSR_t;
-
-    typedef union uMBSSUTR {
-        vuint16_t R;
-        struct {
-
-            vuint16_t:2;
-            vuint16_t LAST_MB_SEG1:6;   /* last message buffer control register for message buffer segment 1 */
-              vuint16_t:2;
-            vuint16_t LAST_MB_UTIL:6;   /* last message buffer utilized */
-        } B;
-    } MBSSUTR_t;
-
-    typedef union uPOCR {
-        vuint16_t R;
-        vuint8_t byte[2];
-        struct {
-            vuint16_t WME:1;    /* write mode external correction command */
-              vuint16_t:3;
-            vuint16_t EOC_AP:2; /* external offset correction application */
-            vuint16_t ERC_AP:2; /* external rate correction application */
-            vuint16_t BSY:1;    /* command write busy / write mode command */
-              vuint16_t:3;
-            vuint16_t POCCMD:4; /* protocol command */
-        } B;
-    } POCR_t;
-/* protocol commands */
-    typedef union uGIFER {
-        vuint16_t R;
-        struct {
-            vuint16_t MIF:1;    /* module interrupt flag */
-            vuint16_t PRIF:1;   /* protocol interrupt flag */
-            vuint16_t CHIF:1;   /* CHI interrupt flag */
-            vuint16_t WKUPIF:1; /* wakeup interrupt flag */
-            vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
-            vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
-            vuint16_t RBIF:1;   /* receive message buffer interrupt flag */
-            vuint16_t TBIF:1;   /* transmit buffer interrupt flag */
-            vuint16_t MIE:1;    /* module interrupt enable */
-            vuint16_t PRIE:1;   /* protocol interrupt enable */
-            vuint16_t CHIE:1;   /* CHI interrupt enable */
-            vuint16_t WKUPIE:1; /* wakeup interrupt enable */
-            vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
-            vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
-            vuint16_t RBIE:1;   /* receive message buffer interrupt enable */
-            vuint16_t TBIE:1;   /* transmit buffer interrupt enable */
-        } B;
-    } GIFER_t;
-    typedef union uPIFR0 {
-        vuint16_t R;
-        struct {
-            vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */
-            vuint16_t INTLIF:1; /* internal protocol error interrupt flag */
-            vuint16_t ILCFIF:1; /* illegal protocol configuration flag */
-            vuint16_t CSAIF:1;  /* cold start abort interrupt flag */
-            vuint16_t MRCIF:1;  /* missing rate correctio interrupt flag */
-            vuint16_t MOCIF:1;  /* missing offset correctio interrupt flag */
-            vuint16_t CCLIF:1;  /* clock correction limit reached interrupt flag */
-            vuint16_t MXSIF:1;  /* max sync frames detected interrupt flag */
-            vuint16_t MTXIF:1;  /* media access test symbol received flag */
-            vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
-            vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
-            vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
-            vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
-            vuint16_t TI2IF:1;  /* timer 2 expired interrupt flag */
-            vuint16_t TI1IF:1;  /* timer 1 expired interrupt flag */
-            vuint16_t CYSIF:1;  /* cycle start interrupt flag */
-        } B;
-    } PIFR0_t;
-    typedef union uPIFR1 {
-        vuint16_t R;
-        struct {
-            vuint16_t EMCIF:1;  /* error mode changed interrupt flag */
-            vuint16_t IPCIF:1;  /* illegal protocol command interrupt flag */
-            vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
-            vuint16_t PSCIF:1;  /* Protocol State Changed Interrupt Flag */
-            vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
-            vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
-            vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
-            vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
-              vuint16_t:2;
-            vuint16_t EVTIF:1;  /* even cycle table written interrupt flag */
-            vuint16_t ODTIF:1;  /* odd cycle table written interrupt flag */
-              vuint16_t:4;
-        } B;
-    } PIFR1_t;
-    typedef union uPIER0 {
-        vuint16_t R;
-        struct {
-            vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */
-            vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable  */
-            vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
-            vuint16_t CSAIE:1;  /* cold start abort interrupt enable */
-            vuint16_t MRCIE:1;  /* missing rate correctio interrupt enable */
-            vuint16_t MOCIE:1;  /* missing offset correctio interrupt enable */
-            vuint16_t CCLIE:1;  /* clock correction limit reached interrupt enable */
-            vuint16_t MXSIE:1;  /* max sync frames detected interrupt enable */
-            vuint16_t MTXIE:1;  /* media access test symbol received interrupt enable */
-            vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
-            vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
-            vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
-            vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
-            vuint16_t TI2IE:1;  /* timer 2 expired interrupt enable */
-            vuint16_t TI1IE:1;  /* timer 1 expired interrupt enable */
-            vuint16_t CYSIE:1;  /* cycle start interrupt enable */
-        } B;
-    } PIER0_t;
-    typedef union uPIER1 {
-        vuint16_t R;
-        struct {
-            vuint16_t EMCIE:1;  /* error mode changed interrupt enable */
-            vuint16_t IPCIE:1;  /* illegal protocol command interrupt enable */
-            vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
-            vuint16_t PSCIE:1;  /* Protocol State Changed Interrupt enable */
-            vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
-            vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
-            vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
-            vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
-              vuint16_t:2;
-            vuint16_t EVTIE:1;  /* even cycle table written interrupt enable */
-            vuint16_t ODTIE:1;  /* odd cycle table written interrupt enable */
-              vuint16_t:4;
-        } B;
-    } PIER1_t;
-    typedef union uCHIERFR {
-        vuint16_t R;
-        struct {
-            vuint16_t FRLBEF:1; /* flame lost channel B error flag */
-            vuint16_t FRLAEF:1; /* frame lost channel A error flag */
-            vuint16_t PCMIEF:1; /* command ignored error flag */
-            vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
-            vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
-            vuint16_t MSBEF:1;  /* message buffer search error flag */
-            vuint16_t MBUEF:1;  /* message buffer utilization error flag */
-            vuint16_t LCKEF:1;  /* lock error flag */
-            vuint16_t DBLEF:1;  /* double transmit message buffer lock error flag */
-            vuint16_t SBCFEF:1; /* system bus communication failure error flag */
-            vuint16_t FIDEF:1;  /* frame ID error flag */
-            vuint16_t DPLEF:1;  /* dynamic payload length error flag */
-            vuint16_t SPLEF:1;  /* static payload length error flag */
-            vuint16_t NMLEF:1;  /* network management length error flag */
-            vuint16_t NMFEF:1;  /* network management frame error flag */
-            vuint16_t ILSAEF:1; /* illegal access error flag */
-        } B;
-    } CHIERFR_t;
-    typedef union uMBIVEC {
-        vuint16_t R;
-        struct {
-
-            vuint16_t:2;
-            vuint16_t TBIVEC:6; /* transmit buffer interrupt vector */
-              vuint16_t:2;
-            vuint16_t RBIVEC:6; /* receive buffer interrupt vector */
-        } B;
-    } MBIVEC_t;
-
-    typedef union uPSR0 {
-        vuint16_t R;
-        struct {
-            vuint16_t ERRMODE:2;        /* error mode */
-            vuint16_t SLOTMODE:2;       /* slot mode */
-              vuint16_t:1;
-            vuint16_t PROTSTATE:3;      /* protocol state */
-            vuint16_t SUBSTATE:4;       /* protocol sub state */
-              vuint16_t:1;
-            vuint16_t WAKEUPSTATUS:3;   /* wakeup status */
-        } B;
-    } PSR0_t;
-
-/* protocol states */
-/* protocol sub-states */
-/* wakeup status */
-    typedef union uPSR1 {
-        vuint16_t R;
-        struct {
-            vuint16_t CSAA:1;   /* cold start attempt abort flag */
-            vuint16_t CSP:1;    /* cold start path */
-              vuint16_t:1;
-            vuint16_t REMCSAT:5;        /* remanining coldstart attempts */
-            vuint16_t CPN:1;    /* cold start noise path */
-            vuint16_t HHR:1;    /* host halt request pending */
-            vuint16_t FRZ:1;    /* freeze occured */
-            vuint16_t APTAC:5;  /* allow passive to active counter */
-        } B;
-    } PSR1_t;
-    typedef union uPSR2 {
-        vuint16_t R;
-        struct {
-            vuint16_t NBVB:1;   /* NIT boundary violation on channel B */
-            vuint16_t NSEB:1;   /* NIT syntax error on channel B */
-            vuint16_t STCB:1;   /* symbol window transmit conflict on channel B */
-            vuint16_t SBVB:1;   /* symbol window boundary violation on channel B */
-            vuint16_t SSEB:1;   /* symbol window syntax error on channel B */
-            vuint16_t MTB:1;    /* media access test symbol MTS received on channel B */
-            vuint16_t NBVA:1;   /* NIT boundary violation on channel A */
-            vuint16_t NSEA:1;   /* NIT syntax error on channel A */
-            vuint16_t STCA:1;   /* symbol window transmit conflict on channel A */
-            vuint16_t SBVA:1;   /* symbol window boundary violation on channel A */
-            vuint16_t SSEA:1;   /* symbol window syntax error on channel A */
-            vuint16_t MTA:1;    /* media access test symbol MTS received on channel A */
-            vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
-        } B;
-    } PSR2_t;
-    typedef union uPSR3 {
-        vuint16_t R;
-        struct {
-            vuint16_t:2;
-            vuint16_t WUB:1;    /* wakeup symbol received on channel B */
-            vuint16_t ABVB:1;   /* aggregated boundary violation on channel B */
-            vuint16_t AACB:1;   /* aggregated additional communication on channel B */
-            vuint16_t ACEB:1;   /* aggregated content error on channel B */
-            vuint16_t ASEB:1;   /* aggregated syntax error on channel B */
-            vuint16_t AVFB:1;   /* aggregated valid frame on channel B */
-              vuint16_t:2;
-            vuint16_t WUA:1;    /* wakeup symbol received on channel A */
-            vuint16_t ABVA:1;   /* aggregated boundary violation on channel A */
-            vuint16_t AACA:1;   /* aggregated additional communication on channel A */
-            vuint16_t ACEA:1;   /* aggregated content error on channel A */
-            vuint16_t ASEA:1;   /* aggregated syntax error on channel A */
-            vuint16_t AVFA:1;   /* aggregated valid frame on channel A */
-        } B;
-    } PSR3_t;
-    typedef union uCIFRR {
-        vuint16_t R;
-        struct {
-            vuint16_t:8;
-            vuint16_t MIFR:1;   /* module interrupt flag */
-            vuint16_t PRIFR:1;  /* protocol interrupt flag */
-            vuint16_t CHIFR:1;  /* CHI interrupt flag */
-            vuint16_t WUPIFR:1; /* wakeup interrupt flag */
-            vuint16_t FNEBIFR:1;        /* receive fifo channel B no empty interrupt flag */
-            vuint16_t FNEAIFR:1;        /* receive fifo channel A no empty interrupt flag */
-            vuint16_t RBIFR:1;  /* receive message buffer interrupt flag */
-            vuint16_t TBIFR:1;  /* transmit buffer interrupt flag */
-        } B;
-    } CIFRR_t;
-    typedef union uSFCNTR {
-        vuint16_t R;
-        struct {
-            vuint16_t SFEVB:4;  /* sync frames channel B, even cycle */
-            vuint16_t SFEVA:4;  /* sync frames channel A, even cycle */
-            vuint16_t SFODB:4;  /* sync frames channel B, odd cycle */
-            vuint16_t SFODA:4;  /* sync frames channel A, odd cycle */
-        } B;
-    } SFCNTR_t;
-
-    typedef union uSFTCCSR {
-        vuint16_t R;
-        struct {
-            vuint16_t ELKT:1;   /* even cycle tables lock and unlock trigger */
-            vuint16_t OLKT:1;   /* odd cycle tables lock and unlock trigger */
-            vuint16_t CYCNUM:6; /* cycle number */
-            vuint16_t ELKS:1;   /* even cycle tables lock status */
-            vuint16_t OLKS:1;   /* odd cycle tables lock status */
-            vuint16_t EVAL:1;   /* even cycle tables valid */
-            vuint16_t OVAL:1;   /* odd cycle tables valid */
-              vuint16_t:1;
-            vuint16_t OPT:1;    /*one pair trigger */
-            vuint16_t SDVEN:1;  /* sync frame deviation table enable */
-            vuint16_t SIDEN:1;  /* sync frame ID table enable */
-        } B;
-    } SFTCCSR_t;
-    typedef union uSFIDRFR {
-        vuint16_t R;
-        struct {
-            vuint16_t:6;
-            vuint16_t SYNFRID:10;       /* sync frame rejection ID */
-        } B;
-    } SFIDRFR_t;
-
-    typedef union uTICCR {
-        vuint16_t R;
-        struct {
-            vuint16_t:2;
-            vuint16_t T2CFG:1;  /* timer 2 configuration */
-            vuint16_t T2REP:1;  /* timer 2 repetitive mode */
-              vuint16_t:1;
-            vuint16_t T2SP:1;   /* timer 2 stop */
-            vuint16_t T2TR:1;   /* timer 2 trigger */
-            vuint16_t T2ST:1;   /* timer 2 state */
-              vuint16_t:3;
-            vuint16_t T1REP:1;  /* timer 1 repetitive mode */
-              vuint16_t:1;
-            vuint16_t T1SP:1;   /* timer 1 stop */
-            vuint16_t T1TR:1;   /* timer 1 trigger */
-            vuint16_t T1ST:1;   /* timer 1 state */
-
-        } B;
-    } TICCR_t;
-    typedef union uTI1CYSR {
-        vuint16_t R;
-        struct {
-            vuint16_t:2;
-            vuint16_t TI1CYCVAL:6;      /* timer 1 cycle filter value */
-              vuint16_t:2;
-            vuint16_t TI1CYCMSK:6;      /* timer 1 cycle filter mask */
-
-        } B;
-    } TI1CYSR_t;
-
-    typedef union uSSSR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-              vuint16_t:1;
-            vuint16_t SEL:2;    /* static slot number */
-              vuint16_t:1;
-            vuint16_t SLOTNUMBER:11;    /* selector */
-        } B;
-    } SSSR_t;
-
-    typedef union uSSCCR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-              vuint16_t:1;
-            vuint16_t SEL:2;    /* selector */
-              vuint16_t:1;
-            vuint16_t CNTCFG:2; /* counter configuration */
-            vuint16_t MCY:1;    /* multi cycle selection */
-            vuint16_t VFR:1;    /* valid frame selection */
-            vuint16_t SYF:1;    /* sync frame selection */
-            vuint16_t NUF:1;    /* null frame selection  */
-            vuint16_t SUF:1;    /* startup frame selection */
-            vuint16_t STATUSMASK:4;     /* slot status mask */
-        } B;
-    } SSCCR_t;
-    typedef union uSSR {
-        vuint16_t R;
-        struct {
-            vuint16_t VFB:1;    /* valid frame on channel B */
-            vuint16_t SYB:1;    /* valid sync frame on channel B */
-            vuint16_t NFB:1;    /* valid null frame on channel B */
-            vuint16_t SUB:1;    /* valid startup frame on channel B */
-            vuint16_t SEB:1;    /* syntax error on channel B */
-            vuint16_t CEB:1;    /* content error on channel B */
-            vuint16_t BVB:1;    /* boundary violation on channel B */
-            vuint16_t TCB:1;    /* tx conflict on channel B */
-            vuint16_t VFA:1;    /* valid frame on channel A */
-            vuint16_t SYA:1;    /* valid sync frame on channel A */
-            vuint16_t NFA:1;    /* valid null frame on channel A */
-            vuint16_t SUA:1;    /* valid startup frame on channel A */
-            vuint16_t SEA:1;    /* syntax error on channel A */
-            vuint16_t CEA:1;    /* content error on channel A */
-            vuint16_t BVA:1;    /* boundary violation on channel A */
-            vuint16_t TCA:1;    /* tx conflict on channel A */
-        } B;
-    } SSR_t;
-    typedef union uMTSCFR {
-        vuint16_t R;
-        struct {
-            vuint16_t MTE:1;    /* media access test symbol transmission enable */
-              vuint16_t:1;
-            vuint16_t CYCCNTMSK:6;      /* cycle counter mask */
-              vuint16_t:2;
-            vuint16_t CYCCNTVAL:6;      /* cycle counter value */
-        } B;
-    } MTSCFR_t;
-
-    typedef union uRSBIR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-              vuint16_t:1;
-            vuint16_t SEL:2;    /* selector */
-              vuint16_t:5;
-            vuint16_t RSBIDX:7; /* receive shadow buffer index */
-        } B;
-    } RSBIR_t;
-
-    typedef union uRFDSR {
-        vuint16_t R;
-        struct {
-            vuint16_t FIFODEPTH:8;      /* fifo depth */
-              vuint16_t:1;
-            vuint16_t ENTRYSIZE:7;      /* entry size */
-        } B;
-    } RFDSR_t;
-
-    typedef union uRFRFCFR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-            vuint16_t IBD:1;    /* interval boundary */
-            vuint16_t SEL:2;    /* filter number */
-              vuint16_t:1;
-            vuint16_t SID:11;   /* slot ID */
-        } B;
-    } RFRFCFR_t;
-
-    typedef union uRFRFCTR {
-        vuint16_t R;
-        struct {
-            vuint16_t:4;
-            vuint16_t F3MD:1;   /* filter mode */
-            vuint16_t F2MD:1;   /* filter mode */
-            vuint16_t F1MD:1;   /* filter mode */
-            vuint16_t F0MD:1;   /* filter mode */
-              vuint16_t:4;
-            vuint16_t F3EN:1;   /* filter enable */
-            vuint16_t F2EN:1;   /* filter enable */
-            vuint16_t F1EN:1;   /* filter enable */
-            vuint16_t F0EN:1;   /* filter enable */
-        } B;
-    } RFRFCTR_t;
-    typedef union uPCR0 {
-        vuint16_t R;
-        struct {
-            vuint16_t ACTION_POINT_OFFSET:6;
-            vuint16_t STATIC_SLOT_LENGTH:10;
-        } B;
-    } PCR0_t;
-
-    typedef union uPCR1 {
-        vuint16_t R;
-        struct {
-            vuint16_t:2;
-            vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
-        } B;
-    } PCR1_t;
-
-    typedef union uPCR2 {
-        vuint16_t R;
-        struct {
-            vuint16_t MINISLOT_AFTER_ACTION_POINT:6;
-            vuint16_t NUMBER_OF_STATIC_SLOTS:10;
-        } B;
-    } PCR2_t;
-
-    typedef union uPCR3 {
-        vuint16_t R;
-        struct {
-            vuint16_t WAKEUP_SYMBOL_RX_LOW:6;
-            vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;
-            vuint16_t COLDSTART_ATTEMPTS:5;
-        } B;
-    } PCR3_t;
-
-    typedef union uPCR4 {
-        vuint16_t R;
-        struct {
-            vuint16_t CAS_RX_LOW_MAX:7;
-            vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
-        } B;
-    } PCR4_t;
-
-    typedef union uPCR5 {
-        vuint16_t R;
-        struct {
-            vuint16_t TSS_TRANSMITTER:4;
-            vuint16_t WAKEUP_SYMBOL_TX_LOW:6;
-            vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;
-        } B;
-    } PCR5_t;
-
-    typedef union uPCR6 {
-        vuint16_t R;
-        struct {
-            vuint16_t:1;
-            vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
-            vuint16_t MACRO_INITIAL_OFFSET_A:7;
-        } B;
-    } PCR6_t;
-
-    typedef union uPCR7 {
-        vuint16_t R;
-        struct {
-            vuint16_t DECODING_CORRECTION_B:9;
-            vuint16_t MICRO_PER_MACRO_NOM_HALF:7;
-        } B;
-    } PCR7_t;
-
-    typedef union uPCR8 {
-        vuint16_t R;
-        struct {
-            vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
-            vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
-            vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;
-        } B;
-    } PCR8_t;
-
-    typedef union uPCR9 {
-        vuint16_t R;
-        struct {
-            vuint16_t MINISLOT_EXISTS:1;
-            vuint16_t SYMBOL_WINDOW_EXISTS:1;
-            vuint16_t OFFSET_CORRECTION_OUT:14;
-        } B;
-    } PCR9_t;
-
-    typedef union uPCR10 {
-        vuint16_t R;
-        struct {
-            vuint16_t SINGLE_SLOT_ENABLED:1;
-            vuint16_t WAKEUP_CHANNEL:1;
-            vuint16_t MACRO_PER_CYCLE:14;
-        } B;
-    } PCR10_t;
-
-    typedef union uPCR11 {
-        vuint16_t R;
-        struct {
-            vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;
-            vuint16_t KEY_SLOT_USED_FOR_SYNC:1;
-            vuint16_t OFFSET_CORRECTION_START:14;
-        } B;
-    } PCR11_t;
-
-    typedef union uPCR12 {
-        vuint16_t R;
-        struct {
-            vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
-            vuint16_t KEY_SLOT_HEADER_CRC:11;
-        } B;
-    } PCR12_t;
-
-    typedef union uPCR13 {
-        vuint16_t R;
-        struct {
-            vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
-            vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
-        } B;
-    } PCR13_t;
-
-    typedef union uPCR14 {
-        vuint16_t R;
-        struct {
-            vuint16_t RATE_CORRECTION_OUT:11;
-            vuint16_t LISTEN_TIMEOUT_H:5;
-        } B;
-    } PCR14_t;
-
-    typedef union uPCR15 {
-        vuint16_t R;
-        struct {
-            vuint16_t LISTEN_TIMEOUT_L:16;
-        } B;
-    } PCR15_t;
-
-    typedef union uPCR16 {
-        vuint16_t R;
-        struct {
-            vuint16_t MACRO_INITIAL_OFFSET_B:7;
-            vuint16_t NOISE_LISTEN_TIMEOUT_H:9;
-        } B;
-    } PCR16_t;
-
-    typedef union uPCR17 {
-        vuint16_t R;
-        struct {
-            vuint16_t NOISE_LISTEN_TIMEOUT_L:16;
-        } B;
-    } PCR17_t;
-
-    typedef union uPCR18 {
-        vuint16_t R;
-        struct {
-            vuint16_t WAKEUP_PATTERN:6;
-            vuint16_t KEY_SLOT_ID:10;
-        } B;
-    } PCR18_t;
-
-    typedef union uPCR19 {
-        vuint16_t R;
-        struct {
-            vuint16_t DECODING_CORRECTION_A:9;
-            vuint16_t PAYLOAD_LENGTH_STATIC:7;
-        } B;
-    } PCR19_t;
-
-    typedef union uPCR20 {
-        vuint16_t R;
-        struct {
-            vuint16_t MICRO_INITIAL_OFFSET_B:8;
-            vuint16_t MICRO_INITIAL_OFFSET_A:8;
-        } B;
-    } PCR20_t;
-
-    typedef union uPCR21 {
-        vuint16_t R;
-        struct {
-            vuint16_t EXTERN_RATE_CORRECTION:3;
-            vuint16_t LATEST_TX:13;
-        } B;
-    } PCR21_t;
-
-    typedef union uPCR22 {
-        vuint16_t R;
-        struct {
-            vuint16_t:1;
-            vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
-            vuint16_t MICRO_PER_CYCLE_H:4;
-        } B;
-    } PCR22_t;
-
-    typedef union uPCR23 {
-        vuint16_t R;
-        struct {
-            vuint16_t micro_per_cycle_l:16;
-        } B;
-    } PCR23_t;
-
-    typedef union uPCR24 {
-        vuint16_t R;
-        struct {
-            vuint16_t CLUSTER_DRIFT_DAMPING:5;
-            vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
-            vuint16_t MICRO_PER_CYCLE_MIN_H:4;
-        } B;
-    } PCR24_t;
-
-    typedef union uPCR25 {
-        vuint16_t R;
-        struct {
-            vuint16_t MICRO_PER_CYCLE_MIN_L:16;
-        } B;
-    } PCR25_t;
-
-    typedef union uPCR26 {
-        vuint16_t R;
-        struct {
-            vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
-            vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
-            vuint16_t MICRO_PER_CYCLE_MAX_H:4;
-        } B;
-    } PCR26_t;
-
-    typedef union uPCR27 {
-        vuint16_t R;
-        struct {
-            vuint16_t MICRO_PER_CYCLE_MAX_L:16;
-        } B;
-    } PCR27_t;
-
-    typedef union uPCR28 {
-        vuint16_t R;
-        struct {
-            vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
-            vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
-        } B;
-    } PCR28_t;
-
-    typedef union uPCR29 {
-        vuint16_t R;
-        struct {
-            vuint16_t EXTERN_OFFSET_CORRECTION:3;
-            vuint16_t MINISLOTS_MAX:13;
-        } B;
-    } PCR29_t;
-
-    typedef union uPCR30 {
-        vuint16_t R;
-        struct {
-            vuint16_t:12;
-            vuint16_t SYNC_NODE_MAX:4;
-        } B;
-    } PCR30_t;
-
-    typedef struct uMSG_BUFF_CCS {
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:1;
-                vuint16_t MCM:1;        /* message buffer commit mode */
-                vuint16_t MBT:1;        /* message buffer type */
-                vuint16_t MTD:1;        /* message buffer direction */
-                vuint16_t CMT:1;        /* commit for transmission */
-                vuint16_t EDT:1;        /* enable / disable trigger */
-                vuint16_t LCKT:1;       /* lock request trigger */
-                vuint16_t MBIE:1;       /* message buffer interrupt enable */
-                  vuint16_t:3;
-                vuint16_t DUP:1;        /* data updated  */
-                vuint16_t DVAL:1;       /* data valid */
-                vuint16_t EDS:1;        /* lock status */
-                vuint16_t LCKS:1;       /* enable / disable status */
-                vuint16_t MBIF:1;       /* message buffer interrupt flag */
-            } B;
-        } MBCCSR;
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t MTM:1;        /* message buffer transmission mode */
-                vuint16_t CHNLA:1;      /* channel assignement */
-                vuint16_t CHNLB:1;      /* channel assignement */
-                vuint16_t CCFE:1;       /* cycle counter filter enable */
-                vuint16_t CCFMSK:6;     /* cycle counter filter mask */
-                vuint16_t CCFVAL:6;     /* cycle counter filter value */
-            } B;
-        } MBCCFR;
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t FID:11;       /* frame ID */
-            } B;
-        } MBFIDR;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:9;
-                vuint16_t MBIDX:7;      /* message buffer index */
-            } B;
-        } MBIDXR;
-    } MSG_BUFF_CCS_t;
-    typedef union uSYSBADHR {
-        vuint16_t R;
-    } SYSBADHR_t;
-    typedef union uSYSBADLR {
-        vuint16_t R;
-    } SYSBADLR_t;
-    typedef union uPADR {
-        vuint16_t R;
-    } PADR_t;
-    typedef union uPDAR {
-        vuint16_t R;
-    } PDAR_t;
-    typedef union uCASERCR {
-        vuint16_t R;
-    } CASERCR_t;
-    typedef union uCBSERCR {
-        vuint16_t R;
-    } CBSERCR_t;
-    typedef union uCYCTR {
-        vuint16_t R;
-    } CYCTR_t;
-    typedef union uMTCTR {
-        vuint16_t R;
-    } MTCTR_t;
-    typedef union uSLTCTAR {
-        vuint16_t R;
-    } SLTCTAR_t;
-    typedef union uSLTCTBR {
-        vuint16_t R;
-    } SLTCTBR_t;
-    typedef union uRTCORVR {
-        vuint16_t R;
-    } RTCORVR_t;
-    typedef union uOFCORVR {
-        vuint16_t R;
-    } OFCORVR_t;
-    typedef union uSFTOR {
-        vuint16_t R;
-    } SFTOR_t;
-    typedef union uSFIDAFVR {
-        vuint16_t R;
-    } SFIDAFVR_t;
-    typedef union uSFIDAFMR {
-        vuint16_t R;
-    } SFIDAFMR_t;
-    typedef union uNMVR {
-        vuint16_t R;
-    } NMVR_t;
-    typedef union uNMVLR {
-        vuint16_t R;
-    } NMVLR_t;
-    typedef union uT1MTOR {
-        vuint16_t R;
-    } T1MTOR_t;
-    typedef union uTI2CR0 {
-        vuint16_t R;
-    } TI2CR0_t;
-    typedef union uTI2CR1 {
-        vuint16_t R;
-    } TI2CR1_t;
-    typedef union uSSCR {
-        vuint16_t R;
-    } SSCR_t;
-    typedef union uRFSR {
-        vuint16_t R;
-    } RFSR_t;
-    typedef union uRFSIR {
-        vuint16_t R;
-    } RFSIR_t;
-    typedef union uRFARIR {
-        vuint16_t R;
-    } RFARIR_t;
-    typedef union uRFBRIR {
-        vuint16_t R;
-    } RFBRIR_t;
-    typedef union uRFMIDAFVR {
-        vuint16_t R;
-    } RFMIDAFVR_t;
-    typedef union uRFMIAFMR {
-        vuint16_t R;
-    } RFMIAFMR_t;
-    typedef union uRFFIDRFVR {
-        vuint16_t R;
-    } RFFIDRFVR_t;
-    typedef union uRFFIDRFMR {
-        vuint16_t R;
-    } RFFIDRFMR_t;
-    typedef union uLDTXSLAR {
-        vuint16_t R;
-    } LDTXSLAR_t;
-    typedef union uLDTXSLBR {
-        vuint16_t R;
-    } LDTXSLBR_t;
-
-    typedef struct FR_tag {
-        volatile MVR_t MVR;     /*module version register *//*0  */
-        volatile MCR_t MCR;     /*module configuration register *//*2  */
-        volatile SYSBADHR_t SYSBADHR;   /*system memory base address high register *//*4        */
-        volatile SYSBADLR_t SYSBADLR;   /*system memory base address low register *//*6         */
-        volatile STBSCR_t STBSCR;       /*strobe signal control register *//*8      */
-        volatile STBPCR_t STBPCR;       /*strobe port control register *//*A        */
-        volatile MBDSR_t MBDSR; /*message buffer data size register *//*C  */
-        volatile MBSSUTR_t MBSSUTR;     /*message buffer segment size and utilization register *//*E  */
-        volatile PADR_t PADR;   /*PE address register *//*10 */
-        volatile PDAR_t PDAR;   /*PE data register *//*12 */
-        volatile POCR_t POCR;   /*Protocol operation control register *//*14 */
-        volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
-        volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
-        volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
-        volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
-        volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
-        volatile CHIERFR_t CHIERFR;     /*CHI error flag register *//*20 */
-        volatile MBIVEC_t MBIVEC;       /*message buffer interrupt vector register *//*22 */
-        volatile CASERCR_t CASERCR;     /*channel A status error counter register *//*24 */
-        volatile CBSERCR_t CBSERCR;     /*channel B status error counter register *//*26 */
-        volatile PSR0_t PSR0;   /*protocol status register 0 *//*28 */
-        volatile PSR1_t PSR1;   /*protocol status register 1 *//*2A */
-        volatile PSR2_t PSR2;   /*protocol status register 2 *//*2C */
-        volatile PSR3_t PSR3;   /*protocol status register 3 *//*2E */
-        volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
-        volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
-        volatile SLTCTAR_t SLTCTAR;     /*slot counter channel A register *//*34 */
-        volatile SLTCTBR_t SLTCTBR;     /*slot counter channel B register *//*36 */
-        volatile RTCORVR_t RTCORVR;     /*rate correction value register *//*38 */
-        volatile OFCORVR_t OFCORVR;     /*offset correction value register *//*3A */
-        volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
-        vuint16_t reserved3[1]; /*3E */
-        volatile SFCNTR_t SFCNTR;       /*sync frame counter register *//*40 */
-        volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
-        volatile SFTCCSR_t SFTCCSR;     /*sync frame table configuration, control, status register *//*44 */
-        volatile SFIDRFR_t SFIDRFR;     /*sync frame ID rejection filter register *//*46 */
-        volatile SFIDAFVR_t SFIDAFVR;   /*sync frame ID acceptance filter value regiater *//*48 */
-        volatile SFIDAFMR_t SFIDAFMR;   /*sync frame ID acceptance filter mask register *//*4A */
-        volatile NMVR_t NMVR[6];        /*network management vector registers (12 bytes) *//*4C */
-        volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
-        volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
-        volatile TI1CYSR_t TI1CYSR;     /*timer 1 cycle set register *//*5C */
-        volatile T1MTOR_t T1MTOR;       /*timer 1 macrotick offset register *//*5E */
-        volatile TI2CR0_t TI2CR0;       /*timer 2 configuration register 0 *//*60 */
-        volatile TI2CR1_t TI2CR1;       /*timer 2 configuration register 1 *//*62 */
-        volatile SSSR_t SSSR;   /*slot status selection register *//*64 */
-        volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
-        volatile SSR_t SSR[8];  /*slot status registers 0-7 *//*68 */
-        volatile SSCR_t SSCR[4];        /*slot status counter registers 0-3 *//*78 */
-        volatile MTSCFR_t MTSACFR;      /*mts a config register *//*80 */
-        volatile MTSCFR_t MTSBCFR;      /*mts b config register *//*82 */
-        volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
-        volatile RFSR_t RFSR;   /*receive fifo selection register *//*86 */
-        volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
-        volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
-        volatile RFARIR_t RFARIR;       /*receive fifo a read index register *//*8C */
-        volatile RFBRIR_t RFBRIR;       /*receive fifo b read index register *//*8E */
-        volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
-        volatile RFMIAFMR_t RFMIAFMR;   /*receive fifo message ID acceptance filter mask register *//*92 */
-        volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
-        volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
-        volatile RFRFCFR_t RFRFCFR;     /*receive fifo range filter configuration register *//*98 */
-        volatile RFRFCTR_t RFRFCTR;     /*receive fifo range filter control register *//*9A */
-        volatile LDTXSLAR_t LDTXSLAR;   /*last dynamic transmit slot channel A register *//*9C */
-        volatile LDTXSLBR_t LDTXSLBR;   /*last dynamic transmit slot channel B register *//*9E */
-        volatile PCR0_t PCR0;   /*protocol configuration register 0 *//*A0 */
-        volatile PCR1_t PCR1;   /*protocol configuration register 1 *//*A2 */
-        volatile PCR2_t PCR2;   /*protocol configuration register 2 *//*A4 */
-        volatile PCR3_t PCR3;   /*protocol configuration register 3 *//*A6 */
-        volatile PCR4_t PCR4;   /*protocol configuration register 4 *//*A8 */
-        volatile PCR5_t PCR5;   /*protocol configuration register 5 *//*AA */
-        volatile PCR6_t PCR6;   /*protocol configuration register 6 *//*AC */
-        volatile PCR7_t PCR7;   /*protocol configuration register 7 *//*AE */
-        volatile PCR8_t PCR8;   /*protocol configuration register 8 *//*B0 */
-        volatile PCR9_t PCR9;   /*protocol configuration register 9 *//*B2 */
-        volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
-        volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
-        volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
-        volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
-        volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
-        volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
-        volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
-        volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
-        volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
-        volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
-        volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
-        volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
-        volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
-        volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
-        volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
-        volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
-        volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
-        volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
-        volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
-        volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
-        volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
-        vuint16_t reserved2[17];
-        volatile MSG_BUFF_CCS_t MBCCS[128];     /* message buffer configuration, control & status registers 0-31 *//*100 */
-    } FR_tag_t;
-
-    typedef union uF_HEADER     /* frame header */
-    {
-        struct {
-            vuint16_t:5;
-            vuint16_t HDCRC:11; /* Header CRC */
-              vuint16_t:2;
-            vuint16_t CYCCNT:6; /* Cycle Count */
-              vuint16_t:1;
-            vuint16_t PLDLEN:7; /* Payload Length */
-              vuint16_t:1;
-            vuint16_t PPI:1;    /* Payload Preamble Indicator */
-            vuint16_t NUF:1;    /* Null Frame Indicator */
-            vuint16_t SYF:1;    /* Sync Frame Indicator */
-            vuint16_t SUF:1;    /* Startup Frame Indicator */
-            vuint16_t FID:11;   /* Frame ID */
-        } B;
-        vuint16_t WORDS[3];
-    } F_HEADER_t;
-    typedef union uS_STSTUS     /* slot status */
-    {
-        struct {
-            vuint16_t VFB:1;    /* Valid Frame on channel B */
-            vuint16_t SYB:1;    /* Sync Frame Indicator channel B */
-            vuint16_t NFB:1;    /* Null Frame Indicator channel B */
-            vuint16_t SUB:1;    /* Startup Frame Indicator channel B */
-            vuint16_t SEB:1;    /* Syntax Error on channel B */
-            vuint16_t CEB:1;    /* Content Error on channel B */
-            vuint16_t BVB:1;    /* Boundary Violation on channel B */
-            vuint16_t CH:1;     /* Channel */
-            vuint16_t VFA:1;    /* Valid Frame on channel A */
-            vuint16_t SYA:1;    /* Sync Frame Indicator channel A */
-            vuint16_t NFA:1;    /* Null Frame Indicator channel A */
-            vuint16_t SUA:1;    /* Startup Frame Indicator channel A */
-            vuint16_t SEA:1;    /* Syntax Error on channel A */
-            vuint16_t CEA:1;    /* Content Error on channel A */
-            vuint16_t BVA:1;    /* Boundary Violation on channel A */
-              vuint16_t:1;
-        } RX;
-        struct {
-            vuint16_t VFB:1;    /* Valid Frame on channel B */
-            vuint16_t SYB:1;    /* Sync Frame Indicator channel B */
-            vuint16_t NFB:1;    /* Null Frame Indicator channel B */
-            vuint16_t SUB:1;    /* Startup Frame Indicator channel B */
-            vuint16_t SEB:1;    /* Syntax Error on channel B */
-            vuint16_t CEB:1;    /* Content Error on channel B */
-            vuint16_t BVB:1;    /* Boundary Violation on channel B */
-            vuint16_t TCB:1;    /* Tx Conflict on channel B */
-            vuint16_t VFA:1;    /* Valid Frame on channel A */
-            vuint16_t SYA:1;    /* Sync Frame Indicator channel A */
-            vuint16_t NFA:1;    /* Null Frame Indicator channel A */
-            vuint16_t SUA:1;    /* Startup Frame Indicator channel A */
-            vuint16_t SEA:1;    /* Syntax Error on channel A */
-            vuint16_t CEA:1;    /* Content Error on channel A */
-            vuint16_t BVA:1;    /* Boundary Violation on channel A */
-            vuint16_t TCA:1;    /* Tx Conflict on channel A */
-        } TX;
-        vuint16_t R;
-    } S_STATUS_t;
-
-    typedef struct uMB_HEADER   /* message buffer header */
-    {
-        F_HEADER_t FRAME_HEADER;
-        vuint16_t DATA_OFFSET;
-        S_STATUS_t SLOT_STATUS;
-    } MB_HEADER_t;
-/****************************************************************************/
-/*                          MODULE : LCD                                   */
-/****************************************************************************/
-    struct LCD_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t LCDEN:1;
-                vuint32_t LCDRST:1;
-                vuint32_t LCDRCS:1;
-                vuint32_t DUTY:3;
-                vuint32_t BIAS:1;
-                vuint32_t VLCDS:1;
-                vuint32_t PWR:2;
-                vuint32_t BSTEN:1;
-                vuint32_t BSTSEL:1;
-                vuint32_t BSTAO:1;
-                  vuint32_t:1;
-                vuint32_t LCDINT:1;
-                vuint32_t EOFF:1;
-                vuint32_t NOF:8;
-                  vuint32_t:2;
-                vuint32_t LCDBPA:1;
-                  vuint32_t:2;
-                vuint32_t LCDBPS:3;
-            } B;
-        } CR;                   /* LCD Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t LCLK:4;
-                  vuint32_t:24;
-            } B;
-        } PCR;                  /* LCD Prescaler Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CCEN:1;
-                  vuint32_t:4;
-                vuint32_t LCC:11;
-                  vuint32_t:16;
-            } B;
-        } CCR;                  /* LCD Contrast Control Register */
-
-        int32_t LCD_reserved1;  /* (0x10 - 0x0C)/4 = 0x01 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FP31EN:1;
-                vuint32_t FP30EN:1;
-                vuint32_t FP29EN:1;
-                vuint32_t FP28EN:1;
-                vuint32_t FP27EN:1;
-                vuint32_t FP26EN:1;
-                vuint32_t FP25EN:1;
-                vuint32_t FP24EN:1;
-                vuint32_t FP23EN:1;
-                vuint32_t FP22EN:1;
-                vuint32_t FP21EN:1;
-                vuint32_t FP20EN:1;
-                vuint32_t FP19EN:1;
-                vuint32_t FP18EN:1;
-                vuint32_t FP17EN:1;
-                vuint32_t FP16EN:1;
-                vuint32_t FP15EN:1;
-                vuint32_t FP14EN:1;
-                vuint32_t FP13EN:1;
-                vuint32_t FP12EN:1;
-                vuint32_t FP11EN:1;
-                vuint32_t FP10EN:1;
-                vuint32_t FP9EN:1;
-                vuint32_t FP8EN:1;
-                vuint32_t FP7EN:1;
-                vuint32_t FP6EN:1;
-                vuint32_t FP5EN:1;
-                vuint32_t FP4EN:1;
-                vuint32_t FP3EN:1;
-                vuint32_t FP2EN:1;
-                vuint32_t FP1EN:1;
-                vuint32_t FP0EN:1;
-            } B;
-        } FPENR0;               /* LCD Frontplane Enable Register 0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FP63EN:1;
-                vuint32_t FP62EN:1;
-                vuint32_t FP61EN:1;
-                vuint32_t FP60EN:1;
-                vuint32_t FP59EN:1;
-                vuint32_t FP58EN:1;
-                vuint32_t FP57EN:1;
-                vuint32_t FP56EN:1;
-                vuint32_t FP55EN:1;
-                vuint32_t FP54EN:1;
-                vuint32_t FP53EN:1;
-                vuint32_t FP52EN:1;
-                vuint32_t FP51EN:1;
-                vuint32_t FP50EN:1;
-                vuint32_t FP49EN:1;
-                vuint32_t FP48EN:1;
-                vuint32_t FP47EN:1;
-                vuint32_t FP46EN:1;
-                vuint32_t FP45EN:1;
-                vuint32_t FP44EN:1;
-                vuint32_t FP43EN:1;
-                vuint32_t FP42EN:1;
-                vuint32_t FP41EN:1;
-                vuint32_t FP40EN:1;
-                vuint32_t FP39EN:1;
-                vuint32_t FP38EN:1;
-                vuint32_t FP37EN:1;
-                vuint32_t FP36EN:1;
-                vuint32_t FP35EN:1;
-                vuint32_t FP34EN:1;
-                vuint32_t FP33EN:1;
-                vuint32_t FP32EN:1;
-            } B;
-        } FPENR1;               /* LCD Frontplane Enable Register 1 */
-
-        int32_t LCD_reserved2[2];       /* (0x20 - 0x18)/4 = 0x02 */
-
-        union {
-            vuint32_t R;
-        } RAM[16];              /* LCD RAM Register */
-
-    };                          /* end of LCD_tag */
-/****************************************************************************/
-/*                     MODULE : External Bus Interface (EBI)                */
-/****************************************************************************/
-    struct EBI_CS_tag {
-        union {                 /* Base Register Bank */
-            vuint32_t R;
-            struct {
-                vuint32_t BA:17;
-                  vuint32_t:3;
-                vuint32_t PS:1;
-                  vuint32_t:4;
-                vuint32_t BL:1;
-                vuint32_t WEBS:1;
-                vuint32_t TBDIP:1;
-                  vuint32_t:2;
-                vuint32_t BI:1;
-                vuint32_t V:1;
-            } B;
-        } BR;
-
-        union {                 /* Option Register Bank */
-            vuint32_t R;
-            struct {
-                vuint32_t AM:17;
-                  vuint32_t:7;
-                vuint32_t SCY:4;
-                  vuint32_t:1;
-                vuint32_t BSCY:2;
-                  vuint32_t:1;
-            } B;
-        } OR;
-    };                          /* end of EBI_CS_tag */
-
-    struct EBI_tag {
-        union {                 /* Module Configuration Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:5;
-                vuint32_t SIZEN:1;
-                vuint32_t SIZE:2;
-                  vuint32_t:8;
-                vuint32_t ACGE:1;
-                vuint32_t EXTM:1;
-                vuint32_t EARB:1;
-                vuint32_t EARP:2;
-                  vuint32_t:4;
-                vuint32_t MDIS:1;
-                  vuint32_t:4;
-                vuint32_t AD_MUX:1;
-                vuint32_t DBM:1;
-            } B;
-        } MCR;
-
-        uint32_t EBI_reserved1;
-
-        union {                 /* Transfer Error Status Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:30;
-                vuint32_t TEAF:1;
-                vuint32_t BMTF:1;
-            } B;
-        } TESR;
-
-        union {                 /* Bus Monitor Control Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t BMT:8;
-                vuint32_t BME:1;
-                  vuint32_t:7;
-            } B;
-        } BMCR;
-
-        struct EBI_CS_tag CS[2];
-
-    };                          /* end of EBI_tag */
-/****************************************************************************/
-/*                     MODULE : DFLASH                                       */
-/****************************************************************************/
-    struct DFLASH_tag {
-        union {                 /* Module Configuration Register */
-            vuint32_t R;
-            struct {
-                vuint32_t EDC:1;
-                  vuint32_t:4;
-                vuint32_t SIZE:3;
-                  vuint32_t:1;
-                vuint32_t LAS:3;
-                  vuint32_t:3;
-                vuint32_t MAS:1;
-                vuint32_t EER:1;
-                vuint32_t RWE:1;
-                  vuint32_t:1;
-                  vuint32_t:1;
-                vuint32_t PEAS:1;
-                vuint32_t DONE:1;
-                vuint32_t PEG:1;
-                  vuint32_t:4;
-                vuint32_t PGM:1;
-                vuint32_t PSUS:1;
-                vuint32_t ERS:1;
-                vuint32_t ESUS:1;
-                vuint32_t EHV:1;
-            } B;
-        } MCR;
-
-        union {                 /* LML Register */
-            vuint32_t R;
-            struct {
-                vuint32_t LME:1;
-                  vuint32_t:10;
-                vuint32_t TSLK:1;
-                  vuint32_t:2;
-                vuint32_t MLK:2;
-                vuint32_t LLK:16;
-            } B;
-        } LML;
-
-        union {                 /* HBL Register */
-            vuint32_t R;
-            struct {
-                vuint32_t HBE:1;
-                  vuint32_t:23;
-                vuint32_t HBLOCK:8;
-            } B;
-        } HBL;
-
-        union {                 /* SLML Register */
-            vuint32_t R;
-            struct {
-                vuint32_t SLE:1;
-                  vuint32_t:10;
-                vuint32_t STSLK:1;
-                  vuint32_t:2;
-                vuint32_t SMK:2;
-                vuint32_t SLK:16;
-            } B;
-        } SLL;
-
-        union {                 /* LMS Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t MSL:2;
-                vuint32_t LSL:16;
-            } B;
-        } LMS;
-
-        union {                 /* High Address Space Block Select Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:26;
-                vuint32_t HSL:6;
-            } B;
-        } HBS;
-
-        union {                 /* Address Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:9;
-                vuint32_t ADD:20;
-                  vuint32_t:3;
-            } B;
-        } ADR;
-
-        int32_t Dflash_reserved0[8];    /* {0x003C-0x001C}/0x4 = 0x08 */
-
-        union {                 /* User Test Register 0 */
-            vuint32_t R;
-            struct {
-                vuint32_t UTE:1;
-                  vuint32_t:7;
-                vuint32_t DSI:8;
-                  vuint32_t:10;
-                vuint32_t MRE:1;
-                vuint32_t MRV:1;
-                vuint32_t EIE:1;
-                vuint32_t AIS:1;
-                vuint32_t AIE:1;
-                vuint32_t AID:1;
-            } B;
-        } UT0;
-
-        union {                 /* User Test Register 1 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT1;
-
-        union {                 /* User Test Register 2 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT2;
-
-        union {                 /* User Multiple Input Signature Register 0-4 */
-            vuint32_t R;
-            struct {
-                vuint32_t MS:32;
-            } B;
-        } UMISR[5];
-
-    };                          /* end of Dflash_tag */
-/****************************************************************************/
-/*                     MODULE : CFLASH                                       */
-/****************************************************************************/
-    struct CFLASH_tag {
-        union {                 /* Module Configuration Register */
-            vuint32_t R;
-            struct {
-                vuint32_t EDC:1;
-                  vuint32_t:4;
-                vuint32_t SIZE:3;
-                  vuint32_t:1;
-                vuint32_t LAS:3;
-                  vuint32_t:3;
-                vuint32_t MAS:1;
-                vuint32_t EER:1;
-                vuint32_t RWE:1;
-                  vuint32_t:1;
-                  vuint32_t:1;
-                vuint32_t PEAS:1;
-                vuint32_t DONE:1;
-                vuint32_t PEG:1;
-                  vuint32_t:4;
-                vuint32_t PGM:1;
-                vuint32_t PSUS:1;
-                vuint32_t ERS:1;
-                vuint32_t ESUS:1;
-                vuint32_t EHV:1;
-            } B;
-        } MCR;
-
-        union {                 /* LML Register */
-            vuint32_t R;
-            struct {
-                vuint32_t LME:1;
-                  vuint32_t:10;
-                vuint32_t TSLK:1;
-                  vuint32_t:2;
-                vuint32_t MLK:2;
-                vuint32_t LLK:16;
-            } B;
-        } LML;
-
-        union {                 /* HBL Register */
-            vuint32_t R;
-            struct {
-                vuint32_t HBE:1;
-                  vuint32_t:23;
-                vuint32_t HBLOCK:8;
-            } B;
-        } HBL;
-
-        union {                 /* SLML Register */
-            vuint32_t R;
-            struct {
-                vuint32_t SLE:1;
-                  vuint32_t:10;
-                vuint32_t STSLK:1;
-                  vuint32_t:2;
-                vuint32_t SMK:2;
-                vuint32_t SLK:16;
-            } B;
-        } SLL;
-
-        union {                 /* LMS Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t MSL:2;
-                vuint32_t LSL:16;
-            } B;
-        } LMS;
-
-        union {                 /* High Address Space Block Select Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:26;
-                vuint32_t HSL:6;
-            } B;
-        } HBS;
-
-        union {                 /* Address Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:9;
-                vuint32_t ADD:20;
-                  vuint32_t:3;
-            } B;
-        } ADR;
-
-        union {                 /* CFLASH Configuration Register 0 */
-            vuint32_t R;
-            struct {
-                vuint32_t BK0_APC:5;
-                vuint32_t BK0_WWSC:5;
-                vuint32_t BK0_RWSC:5;
-                vuint32_t BK0_RWWC2:1;
-                vuint32_t BK0_RWWC1:1;
-                vuint32_t B0_P1_BCFG:2;
-                vuint32_t B0_P1_DPFE:1;
-                vuint32_t B0_P1_IPFE:1;
-                vuint32_t B0_P1_PFLM:2;
-                vuint32_t B0_P1_BFE:1;
-                vuint32_t BK0_RWWC0:1;
-                vuint32_t B0_P0_BCFG:2;
-                vuint32_t B0_P0_DPFE:1;
-                vuint32_t B0_P0_IPFE:1;
-                vuint32_t B0_P0_PFLM:2;
-                vuint32_t B0_P0_BFE:1;
-            } B;
-        } PFCR0;
-
-        union {                 /* CFLASH Configuration Register 1 */
-            vuint32_t R;
-            struct {
-                vuint32_t BK1_APC:5;
-                vuint32_t BK1_WWSC:5;
-                vuint32_t BK1_RWSC:5;
-                vuint32_t BK1_RWWC2:1;
-                vuint32_t BK1_RWWC1:1;
-                  vuint32_t:6;
-                vuint32_t B0_P1_BFE:1;
-                vuint32_t BK1_RWWC0:1;
-                  vuint32_t:6;
-                vuint32_t B1_P0_BFE:1;
-            } B;
-        } PFCR1;
-
-        union {                 /* cflash Access Protection Register */
-            vuint32_t R;
-            struct {
-                vuint32_t:6;
-                vuint32_t ARBM:2;
-                vuint32_t M7PFD:1;
-                vuint32_t M6PFD:1;
-                vuint32_t M5PFD:1;
-                vuint32_t M4PFD:1;
-                vuint32_t M3PFD:1;
-                vuint32_t M2PFD:1;
-                vuint32_t M1PFD:1;
-                vuint32_t M0PFD:1;
-                vuint32_t M7AP:2;
-                vuint32_t M6AP:2;
-                vuint32_t M5AP:2;
-                vuint32_t M4AP:2;
-                vuint32_t M3AP:2;
-                vuint32_t M2AP:2;
-                vuint32_t M1AP:2;
-                vuint32_t M0AP:2;
-            } B;
-        } FAPR;
-
-        int32_t CFLASH_reserved0[5];    /* {0x003C-0x0028}/0x4 = 0x05 */
-
-        union {                 /* User Test Register 0 */
-            vuint32_t R;
-            struct {
-                vuint32_t UTE:1;
-                  vuint32_t:7;
-                vuint32_t DSI:8;
-                  vuint32_t:10;
-                vuint32_t MRE:1;
-                vuint32_t MRV:1;
-                vuint32_t EIE:1;
-                vuint32_t AIS:1;
-                vuint32_t AIE:1;
-                vuint32_t AID:1;
-            } B;
-        } UT0;
-
-        union {                 /* User Test Register 1 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT1;
-
-        union {                 /* User Test Register 2 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;
-            } B;
-        } UT2;
-
-        union {                 /* User Multiple Input Signature Register 0-4 */
-            vuint32_t R;
-            struct {
-                vuint32_t MS:32;
-            } B;
-        } UMISR[5];
-
-    };                          /* end of CFLASH_tag */
-    
-/****************************************************************************/
-/*                          MODULE : CRC                                    */
-/****************************************************************************/
-    struct CRC_SUB_tag {
-        union {
-            vuint8_t  B[4];  /* Data buffer in Bytes (8 bits) */
-            vuint16_t H[2];  /* Data buffer in Half-words (16 bits) */
-            vuint32_t W;     /* Data buffer in words (32 bits) */
-            struct {
-                vuint32_t INV:1;
-                vuint32_t SWAP:1;
-                vuint32_t POLYG:1;
-		vuint32_t:29;
-		}BIT;
-        } CRC_CFG;                   /* CRC Configuration Register */
-
-	union {
-            vuint8_t  B[4];  /* Data buffer in Bytes (8 bits) */
-            vuint16_t H[2];  /* Data buffer in Half-words (16 bits) */
-            vuint32_t W;     /* Data buffer in words (32 bits) */
-        } CRC_INP;	     /* CRC Input Register */
-
-	union {
-            vuint8_t  B[4];  /* Data buffer in Bytes (8 bits) */
-            vuint16_t H[2];  /* Data buffer in Half-words (16 bits) */
-            vuint32_t W;     /* Data buffer in words (32 bits) */
-        } CRC_CSTAT;         /*CRC Current Status Register */
-
-	union {
-            vuint8_t  B[4];  /* Data buffer in Bytes (8 bits) */
-            vuint16_t H[2];  /* Data buffer in Half-words (16 bits) */
-            vuint32_t W;     /* Data buffer in words (32 bits) */
-        } CRC_OUTP;          /* CRC Output Register */
-
-    };                          /* end of CRC_tag */
-
-    struct CRC_tag {
-      struct CRC_SUB_tag CNTX[2];
-    };    
-    
-/****************************************************************** 
-| defines and macros (scope: module-local) 
-|-----------------------------------------------------------------*/
-/* Define instances of modules */
-#define ADC_0     (*(volatile struct ADC_tag *)       0xFFE00000UL)
-#define ADC_1     (*(volatile struct ADC_tag *)       0xFFE04000UL)
-#define CAN_0     (*(volatile struct FLEXCAN_tag *)   0xFFFC0000UL)
-#define CAN_1     (*(volatile struct FLEXCAN_tag *)   0xFFFC4000UL)
-#define CAN_2     (*(volatile struct FLEXCAN_tag *)   0xFFFC8000UL)
-#define CAN_3     (*(volatile struct FLEXCAN_tag *)   0xFFFCC000UL)
-#define CAN_4     (*(volatile struct FLEXCAN_tag *)   0xFFFD0000UL)
-#define CAN_5     (*(volatile struct FLEXCAN_tag *)   0xFFFD4000UL)
-#define CANSP     (*(volatile struct CANSP_tag *)     0xFFE70000UL)
-#define CFLASH    (*(volatile struct CFLASH_tag *)    0xC3F88000UL)
-#define CGM       (*(volatile struct CGM_tag *)       0xC3FE0000UL)
-#define CTU_0     (*(volatile struct CTU_tag *)       0xFFE0C000UL)
-#define CTU_1     (*(volatile struct CTU_tag *)       0xFFE10000UL)
-#define CTUL      (*(volatile struct CTUL_tag *)      0xFFE64000UL)
-#define DCU       (*(volatile struct DCU_tag *)       0xFFE7C000UL)
-#define DFLASH    (*(volatile struct DFLASH_tag *)    0xC3F8C000UL)
-#define DMAMUX    (*(volatile struct DMAMUX_tag *)    0xFFFDC000UL)
-#define DSPI_0    (*(volatile struct DSPI_tag *)      0xFFF90000UL)
-#define DSPI_1    (*(volatile struct DSPI_tag *)      0xFFF94000UL)
-#define DSPI_2    (*(volatile struct DSPI_tag *)      0xFFF98000UL)
-#define DSPI_3    (*(volatile struct DSPI_tag *)      0xFFF9C000UL)
-#define EBI       (*(volatile struct EBI_tag *)       0xC3F84000UL)
-#define EDMA      (*(volatile struct EDMA_tag *)      0xFFF44000UL)
-#define EMIOS_0   (*(volatile struct EMIOS_tag *)     0xC3FA0000UL)
-#define EMIOS_1   (*(volatile struct EMIOS_tag *)     0xC3FA4000UL)
-#define ETIMER_0  (*(volatile struct ETIMER_tag *)    0xFFE18000UL)
-#define ETIMER_1  (*(volatile struct ETIMER_tag *)    0xFFE1C000UL)
-#define FCU       (*(volatile struct FCU_tag *)       0xFFE6C000UL)
-#define FLEXPWM_0 (*(volatile struct FLEXPWM_tag *)   0xFFE24000UL)
-#define FLEXPWM_1 (*(volatile struct FLEXPWM_tag *)   0xFFE28000UL)
-#define FR        (*(volatile struct FR_tag *)        0xFFFE0000UL)
-#define I2C_0     (*(volatile struct I2C_tag *)       0xFFE30000UL)
-#define I2C_1     (*(volatile struct I2C_tag *)       0xFFE34000UL)
-#define I2C_2     (*(volatile struct I2C_tag *)       0xFFE38000UL)
-#define I2C_3     (*(volatile struct I2C_tag *)       0xFFE3C000UL)
-#define INTC      (*(volatile struct INTC_tag *)      0xFFF48000UL)
-#define LCD       (*(volatile struct LCD_tag *)       0xFFE74000UL)
-#define LINFLEX_0 (*(volatile struct LINFLEX_tag *)   0xFFE40000UL)
-#define LINFLEX_1 (*(volatile struct LINFLEX_tag *)   0xFFE44000UL)
-#define LINFLEX_2 (*(volatile struct LINFLEX_tag *)   0xFFE48000UL)
-#define LINFLEX_3 (*(volatile struct LINFLEX_tag *)   0xFFE4C000UL)
-#define MCM       (*(volatile struct MCM_tag *)       0xFFF40000UL)
-#define ME        (*(volatile struct ME_tag *)        0xC3FDC000UL)
-#define MPU       (*(volatile struct MPU_tag *)       0xFFF10000UL)
-#define PCU       (*(volatile struct PCU_tag *)       0xC3FE8000UL)
-#define PIT       (*(volatile struct PIT_tag *)       0xC3FF0000UL)
-#define RGM       (*(volatile struct RGM_tag *)       0xC3FE4000UL)
-#define RTC       (*(volatile struct RTC_tag *)       0xC3FEC000UL)
-#define SAFEPORT  (*(volatile struct FLEXCAN_tag *)   0xFFFE8000UL)
-#define SIU       (*(volatile struct SIU_tag *)       0xC3F90000UL)
-#define SMC       (*(volatile struct SMC_tag *)       0xFFE60000UL)
-#define SSCM      (*(volatile struct SSCM_tag *)      0xC3FD8000UL)
-#define SSD_0     (*(volatile struct SSD_tag *)       0xFFE61000UL)
-#define SSD_1     (*(volatile struct SSD_tag *)       0xFFE61800UL)
-#define SSD_2     (*(volatile struct SSD_tag *)       0xFFE62000UL)
-#define SSD_3     (*(volatile struct SSD_tag *)       0xFFE62800UL)
-#define SSD_4     (*(volatile struct SSD_tag *)       0xFFE63000UL)
-#define SSD_5     (*(volatile struct SSD_tag *)       0xFFE63800UL)
-#define STM       (*(volatile struct STM_tag *)       0xFFF3C000UL)
-#define SWT       (*(volatile struct SWT_tag *)       0xFFF38000UL)
-#define WKUP      (*(volatile struct WKUP_tag *)      0xC3F94000UL)
-#define CRC       (*(volatile struct CRC_tag *)       0xFFE68000UL)
-
-#ifdef __MWERKS__
-#pragma pop
-#endif
-
-#ifdef  __cplusplus
-}
-#endif
-#endif                          /* ifdef _JDP_H */
-/* End of file */
diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.c b/os/hal/platforms/SPC563Mxx/hal_lld.c
deleted file mode 100644
index 5eb36bdd4..000000000
--- a/os/hal/platforms/SPC563Mxx/hal_lld.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC563Mxx/hal_lld.c
- * @brief   SPC563Mxx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-  uint32_t n;
-
-  /* FLASH wait states and prefetching setup.*/
-  CFLASH0.BIUCR.R  = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
-  CFLASH0.BIUCR2.R = 0;
-  CFLASH0.PFCR3.R  = 0;
-
-  /* Optimal crossbar settings. The DMA priority is placed above the CPU
-     priority in order to not starve I/O activities while the CPU is
-     executing tight loops (FLASH and SRAM slave ports only).
-     The SRAM is parked on the load/store port, for some unknown reason it
-     is defaulted on the instructions port and this kills performance.*/
-  XBAR.SGPCR3.B.PARK = 4;               /* RAM slave on load/store port.*/
-  XBAR.MPR0.R = 0x00030201;             /* Flash slave port priorities:
-                                            eDMA (1):              0 (highest)
-                                            Core Instructions (0): 1
-                                            Undocumented (2):      2
-                                            Core Data (4):         3        */
-  XBAR.MPR3.R = 0x00030201;             /* SRAM slave port priorities:
-                                            eDMA (1):              0 (highest)
-                                            Core Instructions (0): 1
-                                            Undocumented (2):      2
-                                            Core Data (4):         3        */
-
-  /* Downcounter timer initialized for system tick use, TB enabled for debug
-     and measurements.*/
-  n = SPC5_SYSCLK / CH_FREQUENCY;
-  asm volatile ("li      %%r3, 0            \t\n"
-                "mtspr   284, %%r3          \t\n"   /* Clear TBL register.  */
-                "mtspr   285, %%r3          \t\n"   /* Clear TBU register.  */
-                "mtspr   22, %[n]           \t\n"   /* Init. DEC register.  */
-                "mtspr   54, %[n]           \t\n"   /* Init. DECAR register.*/
-                "li      %%r3, 0x4000       \t\n"   /* TBEN bit.            */
-                "mtspr   1008, %%r3         \t\n"   /* HID0 register.       */
-                "lis     %%r3, 0x0440       \t\n"   /* DIE ARE bits.        */
-                "mtspr   340, %%r3"                 /* TCR register.        */
-                : : [n] "r" (n) : "r3");
-
-  /* INTC initialization, software vector mode, 4 bytes vectors, starting
-     at priority 0.*/
-  INTC.MCR.R   = 0;
-  INTC.CPR.R   = 0;
-  INTC.IACKR.R = (uint32_t)_vectors;
-
-  /* eMIOS initialization.*/
-  EMIOS.MCR.R = (1U << 26) | SPC5_EMIOS_GPRE;       /* GPREN and GPRE.      */
-
-  /* EDMA initialization.*/
-  edmaInit();
-}
-
-/**
- * @brief   SPC563 clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h and
- *          @p hal_lld.h
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void spc_clock_init(void) {
-
-#if !SPC5_NO_INIT
-  /* PLL activation.*/
-  FMPLL.ESYNCR1.B.EMODE     = 1;                    /* Enhanced mode on.    */
-  FMPLL.ESYNCR1.B.CLKCFG   &= 1;                    /* Bypass mode, PLL off.*/
-#if !SPC5_CLK_BYPASS
-  FMPLL.ESYNCR1.B.CLKCFG   |= 2;                    /* PLL on.              */
-  FMPLL.ESYNCR1.B.EPREDIV   = SPC5_CLK_PREDIV;
-  FMPLL.ESYNCR1.B.EMFD      = SPC5_CLK_MFD;
-  FMPLL.ESYNCR2.B.ERFD      = SPC5_CLK_RFD;
-  while (!FMPLL.SYNSR.B.LOCK)
-    ;
-  FMPLL.ESYNCR1.B.CLKCFG   |= 4;                    /* Clock from the PLL.  */
-#endif /* !SPC5_CLK_BYPASS */
-#endif /* !SPC5_NO_INIT */
-}
-
-/** @} */
diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.h b/os/hal/platforms/SPC563Mxx/hal_lld.h
deleted file mode 100644
index 705b94201..000000000
--- a/os/hal/platforms/SPC563Mxx/hal_lld.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC563Mxx/hal_lld.h
- * @brief   SPC563Mxx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - SPC5_XOSC_CLK.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "xpc563m.h"
-#include "spc563m_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME           "SPC563Mxx Powertrain"
-
-/**
- * @name    ESYNCR2 register definitions
- * @{
- */
-#define SPC5_RFD_DIV2           0           /**< Divide VCO frequency by 2. */
-#define SPC5_RFD_DIV4           1           /**< Divide VCO frequency by 4. */
-#define SPC5_RFD_DIV8           2           /**< Divide VCO frequency by 8. */
-#define SPC5_RFD_DIV16          3           /**< Divide VCO frequency by 16.*/
-/** @} */
-
-/**
- * @name    BIUCR register definitions
- * @{
- */
-#define BIUCR_BANK1_TOO         0x01000000  /**< Use settings for bank1 too.*/
-#define BIUCR_MASTER7_PREFETCH  0x00800000  /**< Enable master 7 prefetch.  */
-#define BIUCR_MASTER6_PREFETCH  0x00400000  /**< Enable master 6 prefetch.  */
-#define BIUCR_MASTER5_PREFETCH  0x00200000  /**< Enable master 5 prefetch.  */
-#define BIUCR_MASTER4_PREFETCH  0x00100000  /**< Enable master 4 prefetch.  */
-#define BIUCR_MASTER3_PREFETCH  0x00080000  /**< Enable master 3 prefetch.  */
-#define BIUCR_MASTER2_PREFETCH  0x00040000  /**< Enable master 2 prefetch.  */
-#define BIUCR_MASTER1_PREFETCH  0x00020000  /**< Enable master 1 prefetch.  */
-#define BIUCR_MASTER0_PREFETCH  0x00010000  /**< Enable master 0 prefetch.  */
-#define BIUCR_APC_MASK          0x0000E000  /**< APC field mask.            */
-#define BIUCR_APC_0             (0 << 13)   /**< No additional hold cycles. */
-#define BIUCR_APC_1             (1 << 13)   /**< 1 additional hold cycle.   */
-#define BIUCR_APC_2             (2 << 13)   /**< 2 additional hold cycles.  */
-#define BIUCR_APC_3             (3 << 13)   /**< 3 additional hold cycles.  */
-#define BIUCR_APC_4             (4 << 13)   /**< 4 additional hold cycles.  */
-#define BIUCR_APC_5             (5 << 13)   /**< 5 additional hold cycles.  */
-#define BIUCR_APC_6             (6 << 13)   /**< 6 additional hold cycles.  */
-#define BIUCR_WWSC_MASK         0x00001800  /**< WWSC field mask.           */
-#define BIUCR_WWSC_0            (0 << 11)   /**< No write wait states.      */
-#define BIUCR_WWSC_1            (1 << 11)   /**< 1 write wait state.        */
-#define BIUCR_WWSC_2            (2 << 11)   /**< 2 write wait states.       */
-#define BIUCR_WWSC_3            (3 << 11)   /**< 3 write wait states.       */
-#define BIUCR_RWSC_MASK         0x00001800  /**< RWSC field mask.           */
-#define BIUCR_RWSC_0            (0 << 8)    /**< No read wait states.       */
-#define BIUCR_RWSC_1            (1 << 8)    /**< 1 read wait state.         */
-#define BIUCR_RWSC_2            (2 << 8)    /**< 2 read wait states.        */
-#define BIUCR_RWSC_3            (3 << 8)    /**< 3 read wait states.        */
-#define BIUCR_RWSC_4            (4 << 8)    /**< 4 read wait states.        */
-#define BIUCR_RWSC_5            (5 << 8)    /**< 5 read wait states.        */
-#define BIUCR_RWSC_6            (6 << 8)    /**< 6 read wait states.        */
-#define BIUCR_RWSC_7            (7 << 8)    /**< 7 read wait states.        */
-#define BIUCR_DPFEN             0x00000040  /**< Data prefetch enable.      */
-#define BIUCR_IPFEN             0x00000010  /**< Instr. prefetch enable.    */
-#define BIUCR_PFLIM_MASK        0x00000060  /**< PFLIM field mask.          */
-#define BIUCR_PFLIM_NO          (0 << 1)    /**< No prefetching.            */
-#define BIUCR_PFLIM_ON_MISS     (1 << 1)    /**< Prefetch on miss.          */
-#define BIUCR_PFLIM_ON_HITMISS  (2 << 1)    /**< Prefetch on hit and miss.  */
-#define BIUCR_BFEN              0x00000001  /**< Flash buffering enable.    */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Disables the clocks initialization in the HAL.
- */
-#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
-#define SPC5_NO_INIT                        FALSE
-#endif
-
-/**
- * @brief   Clock bypass.
- * @note    If set to @p TRUE then the PLL is not started and initialized, the
- *          external clock is used as-is and the other clock-related settings
- *          are ignored.
- */
-#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
-#define SPC5_CLK_BYPASS                     FALSE
-#endif
-
-/**
- * @brief   Disables the overclock checks.
- */
-#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
-#define SPC5_ALLOW_OVERCLOCK                FALSE
-#endif
-
-/**
- * @brief   External clock pre-divider.
- * @note    Must be in range 1...15.
- */
-#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_CLK_PREDIV_VALUE               2
-#endif
-
-/**
- * @brief   Multiplication factor divider.
- * @note    Must be in range 32...96.
- */
-#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
-#define SPC5_CLK_MFD_VALUE                  80
-#endif
-
-/**
- * @brief   Reduced frequency divider.
- */
-#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
-#define SPC5_CLK_RFD                        RFD_DIV4
-#endif
-
-/**
- * @brief   Flash buffer and prefetching settings.
- * @note    Please refer to the SPC563M64 reference manual about the meaning
- *          of the following bits, if in doubt DO NOT MODIFY IT.
- * @note    Do not specify the APC, WWSC, RWSC bits in this value because
- *          those are calculated from the system clock and ORed with this
- *          value.
- */
-#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__)
-#define SPC5_FLASH_BIUCR                    (BIUCR_BANK1_TOO |              \
-                                             BIUCR_MASTER4_PREFETCH |       \
-                                             BIUCR_MASTER0_PREFETCH |       \
-                                             BIUCR_DPFEN |                  \
-                                             BIUCR_IPFEN |                  \
-                                             BIUCR_PFLIM_ON_MISS |          \
-                                             BIUCR_BFEN)
-#endif
-
-/**
- * @brief   eMIOS global prescaler value.
- */
-#if !defined(SPC5_EMIOS_GPRE_VALUE) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_GPRE_VALUE               20
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(SPC563Mxx_MCUCONF)
-#error "Using a wrong mcuconf.h file, SPC563Mxx_MCUCONF not defined"
-#endif
-
-#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15)
-#error "invalid SPC5_CLK_PREDIV_VALUE value specified"
-#endif
-
-#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96)
-#error "invalid SPC5_CLK_MFD_VALUE value specified"
-#endif
-
-#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) &&   \
-    (SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16)
-#error "invalid SPC5_CLK_RFD value specified"
-#endif
-
-#if (SPC5_EMIOS_GPRE_VALUE < 1) || (SPC5_EMIOS_GPRE_VALUE > 256)
-#error "invalid SPC5_EMIOS_GPRE_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL input divider.
- */
-#define SPC5_CLK_PREDIV     (SPC5_CLK_PREDIV_VALUE - 1)
-
-/**
- * @brief   PLL multiplier.
- */
-#define SPC5_CLK_MFD        (SPC5_CLK_MFD_VALUE)
-
-/**
- * @brief   PLL output clock.
- */
-#define SPC5_PLLCLK         ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) *      \
-                             SPC5_CLK_MFD_VALUE)
-
-#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000)
-#error "VCO frequency out of the acceptable range (256...512)"
-#endif
-
-/**
- * @brief   PLL output clock.
- */
-#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__)
-#define SPC5_SYSCLK         (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1)))
-#else
-#define SPC5_SYSCLK         SPC5_XOSC_CLK
-#endif
-
-#if (SPC5_SYSCLK > 80000000) && !SPC5_ALLOW_OVERCLOCK
-#error "System clock above maximum rated frequency (80MHz)"
-#endif
-
-/**
- * @brief   Flash wait states are a function of the system clock.
- */
-#if (SPC5_SYSCLK <= 20000000) || defined(__DOXYGEN__)
-#define SPC5_FLASH_WS       (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1)
-#elif SPC5_SYSCLK <= 40000000
-#define SPC5_FLASH_WS       (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1)
-#elif SPC5_SYSCLK <= 64000000
-#define SPC5_FLASH_WS       (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1)
-#else
-#define SPC5_FLASH_WS       (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_1)
-#endif
-
-/**
- * @brief   eMIOS global prescaler setting.
- */
-#define SPC5_EMIOS_GPRE     (SPC5_EMIOS_GPRE_VALUE << 8)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#include "spc5_edma.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void spc_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC563Mxx/platform.dox b/os/hal/platforms/SPC563Mxx/platform.dox
deleted file mode 100644
index 21401e88d..000000000
--- a/os/hal/platforms/SPC563Mxx/platform.dox
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Licensed under ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- *        http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @defgroup SPC563 SPC563Mx Drivers
- * @details This section describes all the supported drivers on the
- *          SPC563Mx/MPC563xM platform and the implementation details
- *          of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup SPC563_HAL SPC563Mx Initialization Support
- * @details The SPC563Mx/MPC563xM HAL support is responsible for system
- *          initialization.
- *
- * @section spc563_hal_1 Supported HW resources
- * - FMPLL.
- * - INTC.
- * - XBAR.
- * - CFLASH0.
- * .
- * @section spc563_hal_2 SPC563Mx HAL driver implementation features
- * - FMPLL startup and stabilization.
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash wait states initialization based on the selected clock options.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * - DMA support initialization.
- * .
- * @ingroup SPC563
- */
-
-/**
- * @defgroup SPC563_SERIAL SPC563Mx Serial Support
- * @details The SPC563Mx/MPC563xM Serial driver uses the ESCI peripherals
- *          in a buffered, interrupt driven, implementation.
- *
- * @section spc563_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - ESCIA.
- * - ESCIB.
- * .
- * @section spc563_serial_2 SPC563Mx Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each ESCI can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable priority levels for each ESCI.
- * .
- * @ingroup SPC563
- */
diff --git a/os/hal/platforms/SPC563Mxx/platform.mk b/os/hal/platforms/SPC563Mxx/platform.mk
deleted file mode 100644
index 5bf53c67b..000000000
--- a/os/hal/platforms/SPC563Mxx/platform.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of all the SPC563Mxx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC563Mxx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC563Mxx \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1
diff --git a/os/hal/platforms/SPC563Mxx/spc563m_registry.h b/os/hal/platforms/SPC563Mxx/spc563m_registry.h
deleted file mode 100644
index 5f467e3fa..000000000
--- a/os/hal/platforms/SPC563Mxx/spc563m_registry.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC563Mxx/spc563m_registry.h
- * @brief   SPC563Mxx capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _SPC563M_REGISTRY_H_
-#define _SPC563M_REGISTRY_H_
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    SPC563Mxx capabilities
- * @{
- */
-/* DSPI attribures.*/
-#define SPC5_HAS_DSPI0                      FALSE
-#define SPC5_HAS_DSPI1                      TRUE
-#define SPC5_HAS_DSPI2                      TRUE
-#define SPC5_HAS_DSPI3                      FALSE
-#define SPC5_HAS_DSPI4                      FALSE
-#define SPC5_DSPI_FIFO_DEPTH                16
-#define SPC5_DSPI1_EOQF_HANDLER             vector132
-#define SPC5_DSPI1_EOQF_NUMBER              132
-#define SPC5_DSPI1_TFFF_HANDLER             vector133
-#define SPC5_DSPI1_TFFF_NUMBER              133
-#define SPC5_DSPI2_EOQF_HANDLER             vector137
-#define SPC5_DSPI2_EOQF_NUMBER              137
-#define SPC5_DSPI2_TFFF_HANDLER             vector138
-#define SPC5_DSPI2_TFFF_NUMBER              138
-#define SPC5_DSPI1_ENABLE_CLOCK()
-#define SPC5_DSPI1_DISABLE_CLOCK()
-#define SPC5_DSPI2_ENABLE_CLOCK()
-#define SPC5_DSPI2_DISABLE_CLOCK()
-
-/* eDMA attributes.*/
-#define SPC5_HAS_EDMA                       TRUE
-#define SPC5_EDMA_NCHANNELS                 32
-#define SPC5_EDMA_HAS_MUX                   FALSE
-#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID        12
-#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID        25
-#define SPC5_SPI_DSPI1_RX_DMA_CH_ID         13
-#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID        14
-#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID        26
-#define SPC5_SPI_DSPI2_RX_DMA_CH_ID         15
-
-/* eQADC attributes.*/
-#define SPC5_HAS_EQADC                      TRUE
-
-/* eSCI attributes.*/
-#define SPC5_HAS_ESCIA                      TRUE
-#define SPC5_ESCIA_HANDLER                  vector146
-#define SPC5_ESCIA_NUMBER                   146
-
-#define SPC5_HAS_ESCIB                      TRUE
-#define SPC5_ESCIB_HANDLER                  vector149
-#define SPC5_ESCIB_NUMBER                   149
-
-#define SPC5_HAS_ESCIC                      FALSE
-
-/* SIU attributes.*/
-#define SPC5_HAS_SIU                        TRUE
-#define SPC5_SIU_SUPPORTS_PORTS             FALSE
-
-/* EMIOS attributes.*/
-#define SPC5_HAS_EMIOS                      TRUE
-
-#define SPC5_EMIOS_NUM_CHANNELS             16
-
-#define SPC5_EMIOS_FLAG_F0_HANDLER          vector51
-#define SPC5_EMIOS_FLAG_F1_HANDLER          vector52
-#define SPC5_EMIOS_FLAG_F2_HANDLER          vector53
-#define SPC5_EMIOS_FLAG_F3_HANDLER          vector54
-#define SPC5_EMIOS_FLAG_F4_HANDLER          vector55
-#define SPC5_EMIOS_FLAG_F5_HANDLER          vector56
-#define SPC5_EMIOS_FLAG_F6_HANDLER          vector57
-#define SPC5_EMIOS_FLAG_F8_HANDLER          vector59
-#define SPC5_EMIOS_FLAG_F9_HANDLER          vector60
-#define SPC5_EMIOS_FLAG_F10_HANDLER         vector61
-#define SPC5_EMIOS_FLAG_F11_HANDLER         vector62
-#define SPC5_EMIOS_FLAG_F12_HANDLER         vector63
-#define SPC5_EMIOS_FLAG_F13_HANDLER         vector64
-#define SPC5_EMIOS_FLAG_F14_HANDLER         vector65
-#define SPC5_EMIOS_FLAG_F15_HANDLER         vector66
-#define SPC5_EMIOS_FLAG_F23_HANDLER         vector209
-#define SPC5_EMIOS_FLAG_F0_NUMBER           51
-#define SPC5_EMIOS_FLAG_F1_NUMBER           52
-#define SPC5_EMIOS_FLAG_F2_NUMBER           53
-#define SPC5_EMIOS_FLAG_F3_NUMBER           54
-#define SPC5_EMIOS_FLAG_F4_NUMBER           55
-#define SPC5_EMIOS_FLAG_F5_NUMBER           56
-#define SPC5_EMIOS_FLAG_F6_NUMBER           57
-#define SPC5_EMIOS_FLAG_F8_NUMBER           59
-#define SPC5_EMIOS_FLAG_F9_NUMBER           60
-#define SPC5_EMIOS_FLAG_F10_NUMBER          61
-#define SPC5_EMIOS_FLAG_F11_NUMBER          62
-#define SPC5_EMIOS_FLAG_F12_NUMBER          63
-#define SPC5_EMIOS_FLAG_F13_NUMBER          64
-#define SPC5_EMIOS_FLAG_F14_NUMBER          65
-#define SPC5_EMIOS_FLAG_F15_NUMBER          66
-#define SPC5_EMIOS_FLAG_F23_NUMBER          209
-
-#define SPC5_EMIOS_CLK                      (SPC5_SYSCLK /                  \
-                                             SPC5_EMIOS_GPRE_VALUE)
-#define SPC5_EMIOS_ENABLE_CLOCK()
-#define SPC5_EMIOS_DISABLE_CLOCK()
-
-/* FlexCAN attributes.*/
-#define SPC5_HAS_FLEXCAN0                                   TRUE
-#define SPC5_FLEXCAN0_MB                                    64
-#define SPC5_FLEXCAN0_SHARED_IRQ                            FALSE
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER              vector152
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER           vector153
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_HANDLER                vector155
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_01_HANDLER                vector156
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_02_HANDLER                vector157
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_03_HANDLER                vector158
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_HANDLER                vector159
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_05_HANDLER                vector160
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_06_HANDLER                vector161
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_07_HANDLER                vector162
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_HANDLER                vector163
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_09_HANDLER                vector164
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_10_HANDLER                vector165
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_11_HANDLER                vector166
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_HANDLER                vector167
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_13_HANDLER                vector168
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_14_HANDLER                vector169
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_15_HANDLER                vector170
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER             vector171
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER             vector172
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER               152
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER            153
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_NUMBER                 155
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_01_NUMBER                 156
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_02_NUMBER                 157
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_03_NUMBER                 158
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_NUMBER                 159
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_05_NUMBER                 160
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_06_NUMBER                 161
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_07_NUMBER                 162
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_NUMBER                 163
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_09_NUMBER                 164
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_10_NUMBER                 165
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_11_NUMBER                 166
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_NUMBER                 167
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_13_NUMBER                 168
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_14_NUMBER                 169
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_15_NUMBER                 170
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER              171
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER              172
-#define SPC5_FLEXCAN0_ENABLE_CLOCK()
-#define SPC5_FLEXCAN0_DISABLE_CLOCK()
-
-#define SPC5_HAS_FLEXCAN1                                   TRUE
-#define SPC5_FLEXCAN1_MB                                    32
-#define SPC5_FLEXCAN1_SHARED_IRQ                            FALSE
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER              vector173
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER           vector174
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_HANDLER                vector176
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_01_HANDLER                vector177
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_02_HANDLER                vector178
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_03_HANDLER                vector179
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_HANDLER                vector180
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_05_HANDLER                vector181
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_06_HANDLER                vector182
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_07_HANDLER                vector183
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_HANDLER                vector184
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_09_HANDLER                vector185
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_10_HANDLER                vector186
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_11_HANDLER                vector187
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_HANDLER                vector188
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_13_HANDLER                vector189
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_14_HANDLER                vector190
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_15_HANDLER                vector191
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER             vector192
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER               173
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER            174
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_NUMBER                 176
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_01_NUMBER                 177
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_02_NUMBER                 178
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_03_NUMBER                 179
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_NUMBER                 180
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_05_NUMBER                 181
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_06_NUMBER                 182
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_07_NUMBER                 183
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_NUMBER                 184
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_09_NUMBER                 185
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_10_NUMBER                 186
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_11_NUMBER                 187
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_NUMBER                 188
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_13_NUMBER                 189
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_14_NUMBER                 190
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_15_NUMBER                 191
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER              192
-#define SPC5_FLEXCAN1_ENABLE_CLOCK()
-#define SPC5_FLEXCAN1_DISABLE_CLOCK()
-/** @} */
-
-#endif /* _SPC563M_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC563Mxx/typedefs.h b/os/hal/platforms/SPC563Mxx/typedefs.h
deleted file mode 100644
index 9c521fb90..000000000
--- a/os/hal/platforms/SPC563Mxx/typedefs.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC563Mxx/typedefs.h
- * @brief   Dummy typedefs file.
- */
-
-#ifndef _TYPEDEFS_H_
-#define _TYPEDEFS_H_
-
-#include "chtypes.h"
-
-#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/platforms/SPC563Mxx/xpc563m.h b/os/hal/platforms/SPC563Mxx/xpc563m.h
deleted file mode 100644
index 8ee2b5787..000000000
--- a/os/hal/platforms/SPC563Mxx/xpc563m.h
+++ /dev/null
@@ -1,4123 +0,0 @@
-/**************************************************************************/ 
-    
-/* FILE NAME: mpc563xm.h                COPYRIGHT (c) Freescale 2008,2009 */ 
-/* VERSION:  2.0                                  All Rights Reserved     */ 
-/*                                                                        */ 
-/* DESCRIPTION:                                                           */ 
-/* This file contain all of the register and bit field definitions for    */ 
-/* MPC563xM. This version supports revision 1.0 and later.                */ 
-/*========================================================================*/ 
-/* UPDATE HISTORY                                                         */ 
-/* REV      AUTHOR      DATE       DESCRIPTION OF CHANGE                  */ 
-/* ---   -----------  ---------    ---------------------                  */ 
-/* 1.0   G. Emerson   31/OCT/07    Initial version.                       */ 
-/* 1.1   G. Emerson   20/DEC/07    Added SYSDIV HLT HLTACK                */ 
-/*                                 Added ESYNCR1 ESYNCR2 SYNFMMR          */ 
-/* 1.2   G. Emerson   31/JAN/08    Change eMIOS channels so there are 24. */ 
-/*                                 8 channels in the middle of the range  */ 
-/*                                 do not exist                           */ 
-/* 1.3   G. Emerson   30/JUL/08    FLEXCAN - Supports FIFO and Buffer.    */ 
-/*                                 RXIMR added                            */ 
-/*                                 FMPLL   - Added FMPLL.SYNFMMR.B.BSY    */ 
-/*                                 SIU     - Added SIU.ISEL0-3            */ 
-/*                                 EMIOS   - Added EMIOS.CH[x].ALTCADR.R  */ 
-/*                                 MCM     - Replaced ECSM with MCM       */ 
-/*                                 removing SWT registers as defined at   */ 
-/*                                 seperate memory location. PFLASH       */ 
-/*                                 registers pre-fixed with P*. Added PCT,*/ 
-/*                                 PLREV, PLAMC, PLASC, IOPMC, MRSR, MWCR.*/ 
-/*                                 PBRIDGE - Removed as no PBRIDGE        */ 
-/*                                 registers.                             */ 
-/*                                 INTC    - Updated number of PSR from   */ 
-/*                                 358 to 360.                            */ 
-/*                                 mpc5500_spr.h - Added RI to MSR and NMI*/ 
-/*                                 to MSCR.                               */ 
-/* 1.4   G. Emerson   30/SEP/08    Add SIU.MIDR2                          */ 
-/*                                 Changes to SIU.MIDR as per RM.         */ 
-/* 1.5                May 2009     Changes to match documentation, removed*/ 
-/*                                 Not released                           */ 
-/* 1.6   K. Odenthal  03/June/09   Update for 1.5M version of the MPC563xM*/ 
-/*       & R. Dees                                                        */ 
-/*                      INTC - All Processor 0 regs matched to previous   */ 
-/*                             version                                    */ 
-/*                      INTC - BCR renamed to MCR to match previous       */ 
-/*                             version                                    */ 
-/*                      INTC - VTES_PRC1 and HVEN_PRC1 added to MCR       */ 
-/*                      INTC - CPR_PRC1, IACKR_PRC1 and EOIR_PRC1         */ 
-/*                             registers added                            */ 
-/*                      INTC - 512 PSR registers instead of 364           */ 
-/*                      ECSM - (Internal - mcm -> ecsm in the source files*/ 
-/*                              for generating the header file            */ 
-/*                      ECSM - All bits and regs got an additional "p" in */ 
-/*                             the name in the user manual for "Platform" */ 
-/*                             -> deleted to match                        */ 
-/*                      ECSM - SWTCR, SWTSR and SWTIR don't exist in      */ 
-/*                             MPC563xM -> deleted                        */ 
-/*                      ECSM - PROTECTION in the URM is one bitfield,     */ 
-/*                             in mop5534 this are four: PROT1-4 ->       */ 
-/*                             changed to match                           */ 
-/*                      EMCM - removed undocumented registers             */ 
-/*                      ECSM - RAM ECC Syndrome is new in MPC563xM -> added */ 
-/*                      XBAR - removed AMPR and ASGPCR registers          */ 
-/*                      XBAR - removed HPE bits for nonexistant masters   */ 
-/*                      EBI - added: D16_31, AD_MUX and SETA bits         */ 
-/*                      EBI - Added reserved register at address 0x4.     */ 
-/*                      EBI - Corrected number of chip selects in for both*/ 
-/*                            the EBI_CS and the CAL_EBI_CS               */ 
-/*                      SIU - corrected number of GPDO registers and      */ 
-/*                            allowed for maximum PCR registers.          */ 
-/*                      SWT - add KEY bit to CR, correct WND (from WNO)   */ 
-/*                      SWT - add SK register                             */ 
-/*                      PMC - moved bits from CFGR to Status Register (SR)*/ 
-/*                      PMC - Added SR                                    */ 
-/*                      DECFIL - Added new bits DSEL, IBIE, OBIE, EDME,   */ 
-/*                            TORE, & TRFE to MCR. Added IBIC, OBIC,      */ 
-/*                            DIVRC, IBIF, OBIF, DIVR to MSR.             */ 
-/*                            changed OUTTEG to OUTTAG in OB              */ 
-/*                            Change COEF to TAG in TAG register          */ 
-/*                      EQADC - removed REDLCCR - not supported           */ 
-/*                      FLASH - Aligned register and bit names with legacy*/ 
-/* 1.7   K. Odenthal  10/November/09                                      */ 
-/*                      SIU    - changed PCR[n].PA from 3 bit to 4 bit    */ 
-/*                      eTPU   - changed WDTR_A.WDM from 1 bit to 2 bits  */ 
-/*                      DECFIL - changed COEF.R and TAP.R from 16 bit to  */ 
-/*                               32 bit                                   */ 
-/* 2.0   K. Odenthal  12/February/2010                                    */ 
-/*                      TSENS  - Temperature Sensor Module added to       */ 
-/*                               header file                              */ 
-/*                      ANSI C Compliance - Register structures have a    */ 
-/*                               Bitfield Tag ('B') tag only if there is  */ 
-/*                               at least one Bitfiels defined. Empty     */ 
-/*                               tags like 'vuint32_t:32;' are not        */ 
-/*                               allowed.                                 */ 
-/*                      DECFIL - removed MXCR register. This register is  */ 
-/*                               not supported on this part               */ 
-/*                      SIU    - SWT_SEL bit added in SIU DIRER register  */ 
-/*                      EDMA   - removed HRSL, HRSH and GPOR registers.   */ 
-/*                               Those registers are not supported in     */ 
-/*                               that part.                               */ 
-/*                      ESCI   - removed LDBG and DSF bits from LCR       */ 
-/*                               registers. Those bits are not supported  */ 
-/*                               in that part.                            */ 
-/*                               Those registers are not supported in     */ 
-/*                               that part.                               */ 
-/**************************************************************************/ 
-/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ 
-    
-#ifndef _MPC563M_H_
-#define _MPC563M_H_
-    
-#include "typedefs.h"
-    
-#ifdef  __cplusplus
-extern "C" {
-    
-#endif  /* 
- */
-    
-#ifdef __MWERKS__
-#pragma push
-#pragma ANSI_strict off
-#endif  /* 
- */
-    
-/****************************************************************************/
-/*                     MODULE : FMPLL                                       */
-/****************************************************************************/
-        struct FMPLL_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:1;
-                vuint32_t PREDIV:3;
-                vuint32_t MFD:5;
-                  vuint32_t:1;
-                vuint32_t RFD:3;
-                vuint32_t LOCEN:1;
-                vuint32_t LOLRE:1;
-                vuint32_t LOCRE:1;
-                  vuint32_t:1;  /* Reserved in MPC563xM 
-
-                                   Deleted for legacy header version [mpc5534.h]: 
-
-                                   <vuint32_t DISCLK:1> */
-                vuint32_t LOLIRQ:1;
-                vuint32_t LOCIRQ:1;
-                  vuint32_t:13; /* Reserved in MPC563xM 
-
-                                   Deleted for legacy header version [mpc5534.h]:
-
-                                   <vuint32_t RATE:1 > 
-
-                                   <vuint32_t DEPTH:2>
-
-                                   <vuint32_t EXP:10 > */
-            } B;
-        } SYNCR;
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:22;
-                vuint32_t LOLF:1;
-                vuint32_t LOC:1;
-                vuint32_t MODE:1;
-                vuint32_t PLLSEL:1;
-                vuint32_t PLLREF:1;
-                vuint32_t LOCKS:1;
-                vuint32_t LOCK:1;
-                vuint32_t LOCF:1;
-                  vuint32_t:2;  /* Reserved in MPC563xM
-
-                                   Deleted for legacy header version [mpc5534.h]:
-
-                                   <vuint32_t CALDONE:1>
-
-                                   <vuint32_t CALPASS:1> */
-            } B;
-        } SYNSR;
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EMODE:1;
-                vuint32_t CLKCFG:3;
-                  vuint32_t:8;
-                vuint32_t EPREDIV:4;
-                  vuint32_t:9;
-                vuint32_t EMFD:7;
-            } B;
-        } ESYNCR1;              /* Enhanced Synthesizer Control Register 1 (ESYNCR1) (new in MPC563xM) Offset 0x0008 */
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t LOCEN:1;
-                vuint32_t LOLRE:1;
-                vuint32_t LOCRE:1;
-                vuint32_t LOLIRQ:1;
-                vuint32_t LOCIRQ:1;
-                  vuint32_t:17;
-                vuint32_t ERFD:2;
-            } B;
-        } ESYNCR2;              /* Enhanced Synthesizer Control Register 2 (ESYNCR2) (new in MPC563xM) Offset 0x000C */
-        int32_t FMPLL_reserved0[2];
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BSY:1;
-                vuint32_t MODEN:1;
-                vuint32_t MODSEL:1;
-                vuint32_t MODPERIOD:13;
-                  vuint32_t:1;
-                vuint32_t INCSTEP:15;
-            } B;
-        } SYNFMMR;              /* Synthesizer FM Modulation Register (SYNFMMR) (new in MPC563xM) Offset 0x0018 */
-    };
-/****************************************************************************/
-/*                     MODULE : EBI                                      */
-/****************************************************************************/
-    struct CS_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BA:17;        /*  */
-                  vuint32_t:3;  /*  */
-                vuint32_t PS:1; /*  */
-                  vuint32_t:3;  /*  */
-                vuint32_t AD_MUX:1;     /* new in MPC563xM */
-                vuint32_t BL:1; /*  */
-                vuint32_t WEBS:1;       /*  */
-                vuint32_t TBDIP:1;      /*  */
-                  vuint32_t:1;  /*  */
-                vuint32_t SETA:1;       /* new in MPC563xM */
-                vuint32_t BI:1; /*  */
-                vuint32_t V:1;  /*  */
-            } B;
-        } BR;                   /* <URM>EBI_BR</URM>  */
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t AM:17;        /*  */
-                  vuint32_t:7;  /*  */
-                vuint32_t SCY:4;        /*  */
-                  vuint32_t:1;  /*  */
-                vuint32_t BSCY:2;       /*  */
-                  vuint32_t:1;  /*  */
-            } B;
-        } OR;                   /* <URM>EBI_OR</URM> */
-    };
-    struct CAL_CS_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BA:17;        /*  */
-                  vuint32_t:3;  /*  */
-                vuint32_t PS:1; /*  */
-                  vuint32_t:3;  /*  */
-                vuint32_t AD_MUX:1;     /* new in MPC563xM */
-                vuint32_t BL:1; /*  */
-                vuint32_t WEBS:1;       /*  */
-                vuint32_t TBDIP:1;      /*  */
-                  vuint32_t:1;  /*  */
-                vuint32_t SETA:1;       /* new in MPC563xM */
-                vuint32_t BI:1; /*  */
-                vuint32_t V:1;  /*  */
-            } B;
-        } BR;                   /* <URM>EBI_CAL_BR</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t AM:17;        /*  */
-                  vuint32_t:7;  /*  */
-                vuint32_t SCY:4;        /*  */
-                  vuint32_t:1;  /*  */
-                vuint32_t BSCY:2;       /*  */
-                  vuint32_t:1;  /*  */
-            } B;
-        } OR;                   /* <URM>EBI_CAL_OR</URM> */
-
-    };
-
-    struct EBI_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:5;    /*  */
-                vuint32_t SIZEEN:1;     /* <URM>SIZEN</URM> */
-                vuint32_t SIZE:2;       /*  */
-                  vuint32_t:8;  /*  */
-                vuint32_t ACGE:1;       /*  */
-                vuint32_t EXTM:1;       /*  */
-                vuint32_t EARB:1;       /*  */
-                vuint32_t EARP:2;       /*  */
-                  vuint32_t:4;  /*  */
-                vuint32_t MDIS:1;       /*  */
-                  vuint32_t:3;  /*  */
-                vuint32_t D16_31:1;     /* new in MPC563xM */
-                vuint32_t AD_MUX:1;     /* new in MPC563xM */
-                vuint32_t DBM:1;        /*  */
-            } B;
-        } MCR;                  /* EBI Module Configuration Register (MCR) <URM>EBI_MCR</URM> @baseaddress + 0x00 */
-
-        uint32_t EBI_reserved1[1];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:30;   /*  */
-                vuint32_t TEAF:1;       /*  */
-                vuint32_t BMTF:1;       /*  */
-            } B;
-        } TESR;                 /* EBI Transfer Error Status Register (TESR) <URM>EBI_TESR</URM> @baseaddress + 0x08 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;   /*  */
-                vuint32_t BMT:8;        /*  */
-                vuint32_t BME:1;        /*  */
-                  vuint32_t:7;  /*  */
-            } B;
-        } BMCR;                 /* <URM>EBI_BMCR</URM> @baseaddress + 0x0C */
-
-        struct CS_tag CS[4];
-
-        uint32_t EBI_reserved2[4];
-
-        /* Calibration registers */
-        struct CAL_CS_tag CAL_CS[4];
-
-    };                          /* end of EBI_tag */
-/****************************************************************************/
-/*                     MODULE : FLASH                                       */
-/****************************************************************************/
-/* 3 flash modules implemented.                                             */
-/*       HBL and HBS not used in Bank 0 / Array 0                           */
-/*       LML, SLL, LMS, PFCR1, PFAPR, PFCR2, and PFCR3 not used in          */
-/*       Bank 1 / Array 1 or Bank 1 / Array 3                                 */
-/****************************************************************************/
-    struct FLASH_tag {
-        union {                 /* Module Configuration Register (MCR)@baseaddress + 0x00 */
-            vuint32_t R;
-            struct {
-                vuint32_t EDC:1;        /* ECC Data Correction (Read/Clear) */
-                  vuint32_t:4;  /* Reserved */
-                vuint32_t SIZE:3;       /* Array Size (Read Only) */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t LAS:3;        /* Low Address Space (Read Only) */
-                  vuint32_t:3;  /* Reserved */
-                vuint32_t MAS:1;        /* Mid Address Space (Read Only) */
-                vuint32_t EER:1;        /* ECC Event Error (Read/Clear) *//* <LEGACY> BBEPE and EPE </LEGACY> */
-                vuint32_t RWE:1;        /* Read While Write Event Error (Read/Clear) */
-                  vuint32_t:2;  /* Reserved */
-                vuint32_t PEAS:1;       /* Program/Erase Access Space (Read Only) */
-                vuint32_t DONE:1;       /* Status (Read Only) */
-                vuint32_t PEG:1;        /* Program/Erase Good (Read Only) */
-                  vuint32_t:4;  /* Reserved *//* <LEGACY> RSD PEG STOP RSVD </LEGACY> */
-                vuint32_t PGM:1;        /* Program (Read/Write) */
-                vuint32_t PSUS:1;       /* Program Suspend (Read/Write) */
-                vuint32_t ERS:1;        /* Erase (Read/Write) */
-                vuint32_t ESUS:1;       /* Erase Suspend (Read/Write) */
-                vuint32_t EHV:1;        /* Enable High Voltage (Read/Write) */
-            } B;
-        } MCR;
-
-        union {                 /* Low/Mid-Address Space Block Locking Register (LML)@baseaddress + 0x04 */
-            vuint32_t R;
-            struct {
-                vuint32_t LME:1;        /* Low/Mid address space block enable (Read Only) */
-                  vuint32_t:10; /* Reserved */
-                vuint32_t SLOCK:1;      /*<URM>SLK</URM> *//* Shadow address space block lock (Read/Write) */
-                  vuint32_t:2;  /* Reserved */
-                vuint32_t MLOCK:2;      /*<URM>MLK</URM> *//* Mid address space block lock (Read/Write) */
-                  vuint32_t:8;  /* Reserved */
-                vuint32_t LLOCK:8;      /*<URM>LLK</URM> *//* Low address space block lock (Read/Write) */
-            } B;
-        } LMLR;                 /*<URM>LML</URM> */
-
-        union {                 /* High-Address Space Block Locking Register (HBL) - @baseaddress + 0x08 */
-            vuint32_t R;
-            struct {
-                vuint32_t HBE:1;        /* High address space Block Enable (Read Only) */
-                  vuint32_t:27; /* Reserved */
-                vuint32_t HBLOCK:4;     /* High address space block lock (Read/Write) */
-            } B;
-        } HLR;                  /*<URM>HBL</URM> */
-
-        union {                 /* Secondary Low/Mid-Address Space Block Locking Register (SLL)@baseaddress + 0x0C */
-            vuint32_t R;
-            struct {
-                vuint32_t SLE:1;        /* Secondary low/mid address space block enable (Read Only) */
-                  vuint32_t:10; /* Reserved */
-                vuint32_t SSLOCK:1;     /*<URM>SSLK</URM> *//* Secondary shadow address space block lock (Read/Write) */
-                  vuint32_t:2;  /* Reserved */
-                vuint32_t SMLOCK:2;     /*<URM>SMK</URM> *//* Secondary mid address space block lock (Read/Write) */
-                  vuint32_t:8;  /* Reserved */
-                vuint32_t SLLOCK:8;     /*<URM>SLK</URM> *//* Secondary low address space block lock (Read/Write) */
-            } B;
-        } SLMLR;                /*<URM>SLL</URM> */
-
-        union {                 /* Low/Mid-Address Space Block Select Register (LMS)@baseaddress + 0x10 */
-            vuint32_t R;
-            struct {
-                vuint32_t:14;   /* Reserved */
-                vuint32_t MSEL:2;       /*<URM>MSL</URM> *//* Mid address space block select (Read/Write) */
-                  vuint32_t:8;  /* Reserved */
-                vuint32_t LSEL:8;       /*<URM>LSL</URM> *//* Low address space block select (Read/Write) */
-            } B;
-        } LMSR;                 /*<URM>LMS</URM> */
-
-        union {                 /* High-Address Space Block Select Register (HBS) - not used@baseaddress + 0x14 */
-            vuint32_t R;
-            struct {
-                vuint32_t:28;   /* Reserved */
-                vuint32_t HBSEL:4;      /*<URM>HSL</URM> *//* High address space block select (Read/Write) */
-            } B;
-        } HSR;                  /*<URM>HBS</URM> */
-
-        union {                 /* Address Register (ADR)@baseaddress + 0x18 */
-            vuint32_t R;
-            struct {
-                vuint32_t SAD:1;        /* Shadow address (Read Only) */
-                  vuint32_t:10; /* Reserved */
-                vuint32_t ADDR:18;      /*<URM>AD</URM> *//* Address 20-3 (Read Only) */
-                  vuint32_t:3;  /* Reserved */
-            } B;
-        } AR;                   /*<URM>ADR</URM> */
-
-        union {                 /* @baseaddress + 0x1C */
-            vuint32_t R;
-            struct {
-                vuint32_t:7;    /* Reserved */
-                vuint32_t GCE:1;        /* Global Configuration Enable (Read/Write) */
-                  vuint32_t:4;  /* Reserved */
-                vuint32_t M3PFE:1;      /* Master 3 Prefetch Enable (Read/Write) */
-                vuint32_t M2PFE:1;      /* Master 2 Prefetch Enable (Read/Write) */
-                vuint32_t M1PFE:1;      /* Master 1 Prefetch Enable (Read/Write) */
-                vuint32_t M0PFE:1;      /* Master 0 Prefetch Enable (Read/Write) */
-                vuint32_t APC:3;        /* Address Pipelining Control (Read/Write) */
-                vuint32_t WWSC:2;       /* Write Wait State Control (Read/Write) */
-                vuint32_t RWSC:3;       /* Read Wait State Control (Read/Write) */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t DPFEN:1;      /*<URM>DPFE</URM> *//* Data Prefetch Enable (Read/Write) */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t IPFEN:1;      /*<URM>IPFE</URM> *//* Instruction Prefetch Enable (Read/Write) */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t PFLIM:2;      /* Prefetch Limit (Read/Write) */
-                vuint32_t BFEN:1;       /*<URM>BFE</URM> *//* Buffer Enable (Read/Write) */
-            } B;
-        } BIUCR;                /*<URM>PFCR1</URM> */
-
-        union {                 /* @baseaddress + 0x20 */
-            vuint32_t R;
-            struct {
-                vuint32_t:24;   /* Reserved */
-                vuint32_t M3AP:2;       /* Master 3 Access Protection (Read/Write) */
-                vuint32_t M2AP:2;       /* Master 2 Access Protection (Read/Write) */
-                vuint32_t M1AP:2;       /* Master 1 Access Protection (Read/Write) */
-                vuint32_t M0AP:2;       /* Master 0 Access Protection (Read/Write) */
-            } B;
-        } BIUAPR;               /*<URM>PFAPR</URM> */
-
-        union {                 /* @baseaddress + 0x24 */
-            vuint32_t R;
-            struct {
-                vuint32_t LBCFG:2;      /* Line Buffer Configuration (Read/Write) */
-                  vuint32_t:30; /* Reserved */
-            } B;
-        } BIUCR2;
-
-        union {                 /* @baseaddress + 0x28 */
-            vuint32_t R;
-            struct {
-                vuint32_t:25;   /* Reserved */
-                vuint32_t B1_DPFE:1;    /* Bank1 Data Prefetch Enable (Read/Write) */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t B1_IPFE:1;    /* Bank1 Instruction Prefetch Enable (Read/Write) */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t B1_PFLIM:2;   /* Bank1 Prefetch Limit (Read/Write) */
-                vuint32_t B1_BFE:1;     /* Bank1 Buffer Enable (Read/Write) */
-            } B;
-        } PFCR3;
-
-        int32_t FLASH_reserverd_89[4];
-
-        union {                 /* User Test 0 (UT0) register@baseaddress + 0x3c */
-            vuint32_t R;
-            struct {
-                vuint32_t UTE:1;        /* User test enable (Read/Clear) */
-                vuint32_t SBCE:1;       /* Single bit correction enable (Read/Clear) */
-                  vuint32_t:6;  /* Reserved */
-                vuint32_t DSI:8;        /* Data syndrome input (Read/Write) */
-                  vuint32_t:9;  /* Reserved */
-                  vuint32_t:1;  /* Reserved (Read/Write) */
-                vuint32_t MRE:1;        /* Margin Read Enable (Read/Write) */
-                vuint32_t MRV:1;        /* Margin Read Value (Read/Write) */
-                vuint32_t EIE:1;        /* ECC data Input Enable (Read/Write) */
-                vuint32_t AIS:1;        /* Array Integrity Sequence (Read/Write) */
-                vuint32_t AIE:1;        /* Array Integrity Enable (Read/Write) */
-                vuint32_t AID:1;        /* Array Integrity Done (Read Only) */
-            } B;
-        } UT0;
-
-        union {                 /* User Test 1 (UT1) register@baseaddress + 0x40 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;       /* Data Array Input (Read/Write) */
-            } B;
-        } UT1;
-
-        union {                 /* User Test 2 (UT2) register@baseaddress + 0x44 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;       /* Data Array Input (Read/Write) */
-            } B;
-        } UT2;
-
-        union {                 /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */
-            vuint32_t R;
-            struct {
-                vuint32_t MS:32;        /* Multiple input Signature (Read/Write) */
-            } B;
-        } UMISR[5];
-
-    };                          /* end of FLASH_tag */
-/****************************************************************************/
-/*                     MODULE : SIU                                      */
-/****************************************************************************/
-    struct SIU_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t S_F:1;        /* Identifies the Manufacturer <URM>S/F</URM> */
-                vuint32_t FLASH_SIZE_1:4;       /* Define major Flash memory size (see Table 15-4 for details) <URM>Flash Size 1</URM> */
-                vuint32_t FLASH_SIZE_2:4;       /* Define Flash memory size, small granularity (see Table 15-5 for details) <URM>Flash Size 1</URM> */
-                vuint32_t TEMP_RANGE:2; /* Define maximum operating range <URM>Temp Range</URM> */
-                  vuint32_t:1;  /* Reserved for future enhancements */
-                vuint32_t MAX_FREQ:2;   /* Define maximum device speed <URM>Max Freq</URM> */
-                  vuint32_t:1;  /* Reserved for future enhancements */
-                vuint32_t SUPPLY:1;     /* Defines if the part is 5V or 3V <URM>Supply</URM> */
-                vuint32_t PART_NUMBER:8;        /* Contain the ASCII representation of the character that indicates the product <URM>Part Number</URM> */
-                vuint32_t TBD:1;        /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */
-                  vuint32_t:2;  /* Reserved for future enhancements */
-                vuint32_t EE:1; /* Indicates if Data Flash is present */
-                  vuint32_t:3;  /* Reserved for future enhancements */
-                vuint32_t FR:1; /* Indicates if Data FlexRay is present */
-            } B;
-        } MIDR2;                /* MCU ID Register 2  <URM>SIU_MIDR2</URM> @baseaddress + 0x4 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PARTNUM:16;   /* Device part number: 0x5633 */
-                vuint32_t CSP:1;        /* CSP configuration (new in MPC563xM) */
-                vuint32_t PKG:5;        /* Indicate the package the die is mounted in. (new in MPC563xM)  */
-                  vuint32_t:2;  /* Reserved */
-                vuint32_t MASKNUM:8;    /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */
-            } B;
-        } MIDR;                 /* MCU ID Register (MIDR) <URM>SIU_MIDR</URM> @baseaddress + 0x8 */
-
-        union {
-            vuint32_t R;
-        } TST;                  /* SIU Test Register (SIU_TST) <URM>SIU_TST</URM> @baseaddress + 0xC */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PORS:1;       /*  Power-On Reset Status */
-                vuint32_t ERS:1;        /*  External Reset Status */
-                vuint32_t LLRS:1;       /*  Loss of Lock Reset Status */
-                vuint32_t LCRS:1;       /*  Loss of Clock Reset Status */
-                vuint32_t WDRS:1;       /*  Watchdog Timer/Debug Reset Status */
-                vuint32_t CRS:1;        /*  Checkstop Reset Status */
-                vuint32_t SWTRS:1;      /*  Software Watchdog Timer Reset Status (new in MPC563xM) */
-                  vuint32_t:7;  /*  */
-                vuint32_t SSRS:1;       /*  Software System Reset Status */
-                vuint32_t SERF:1;       /*  Software External Reset Flag */
-                vuint32_t WKPCFG:1;     /*  Weak Pull Configuration Pin Status */
-                  vuint32_t:11; /*  */
-                vuint32_t ABR:1;        /*  Auto Baud Rate (new in MPC563xM) */
-                vuint32_t BOOTCFG:2;    /*  Reset Configuration Pin Status  */
-                vuint32_t RGF:1;        /*  RESET Glitch Flag */
-            } B;
-        } RSR;                  /* Reset Status Register (SIU_RSR) <URM>SIU_RSR</URM> @baseaddress + 0x10 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SSR:1;        /*  Software System Reset */
-                vuint32_t SER:1;        /*  Software External Reset */
-                  vuint32_t:14; /*  */
-                vuint32_t CRE:1;        /*  Checkstop Reset Enable */
-                  vuint32_t:15; /*  */
-            } B;
-        } SRCR;                 /* System Reset Control Register (SRCR) <URM>SIU_SRCR</URM> @baseaddress + 0x14 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NMI:1;        /* Non-Maskable Interrupt Flag (new in MPC563xM) */
-                  vuint32_t:7;  /*  */
-                vuint32_t SWT:1;        /* Software Watch Dog Timer Interrupt Flag, from platform (new in MPC563xM) */
-                  vuint32_t:7;  /*  */
-                vuint32_t EIF15:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF14:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF13:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF12:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF11:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF10:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF9:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF8:1;       /* External Interrupt Request Flag x */
-                  vuint32_t:3;  /* (reserved in MPC563xM) */
-                vuint32_t EIF4:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF3:1;       /* External Interrupt Request Flag x */
-                  vuint32_t:2;  /* (reserved in MPC563xM) */
-                vuint32_t EIF0:1;       /* External Interrupt Request Flag x */
-            } B;
-        } EISR;                 /* SIU External Interrupt Status Register (EISR) <URM>SIU_EISR</URM> @baseaddress + 0x18 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NMI_SEL:1;    /* NMI Interrupt Platform Input Selection (new in MPC563xM) */
-                  vuint32_t:7;  /*  */
-                vuint32_t SWT_SEL:1;
-                  vuint32_t:7;
-                vuint32_t EIRE15:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE14:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE13:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE12:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE11:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE10:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE9:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE8:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE7:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE6:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE5:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE4:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE3:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE2:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE1:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE0:1;      /* External DMA/Interrupt Request Enable x */
-            } B;
-        } DIRER;                /* DMA/Interrupt Request Enable Register (DIRER) <URM>SIU_DIRER</URM> @baseaddress + 0x1C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;   /*  */
-                vuint32_t DIRS3:1;      /* DMA/Interrupt Request Select x */
-                  vuint32_t:2;  /* reserved in MPC563xM */
-                vuint32_t DIRS0:1;      /* DMA/Interrupt Request Select x */
-            } B;
-        } DIRSR;                /* DMA/Interrupt Request Select Register (DIRSR) <URM>SIU_DIRSR</URM> @baseaddress + 0x20 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;   /*  */
-                vuint32_t OVF15:1;      /* Overrun Flag x */
-                vuint32_t OVF14:1;      /* Overrun Flag x */
-                vuint32_t OVF13:1;      /* Overrun Flag x */
-                vuint32_t OVF12:1;      /* Overrun Flag x */
-                vuint32_t OVF11:1;      /* Overrun Flag x */
-                vuint32_t OVF10:1;      /* Overrun Flag x */
-                vuint32_t OVF9:1;       /* Overrun Flag x */
-                vuint32_t OVF8:1;       /* Overrun Flag x */
-                  vuint32_t:3;  /* reserved in MPC563xM */
-                vuint32_t OVF4:1;       /* Overrun Flag x */
-                vuint32_t OVF3:1;       /* Overrun Flag x */
-                  vuint32_t:2;  /* reserved in MPC563xM */
-                vuint32_t OVF0:1;       /* Overrun Flag x */
-            } B;
-        } OSR;                  /* Overrun Status Register (OSR) <URM>SIU_OSR</URM> @baseaddress + 0x24 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;   /*  */
-                vuint32_t ORE15:1;      /* Overrun Request Enable x */
-                vuint32_t ORE14:1;      /* Overrun Request Enable x */
-                vuint32_t ORE13:1;      /* Overrun Request Enable x */
-                vuint32_t ORE12:1;      /* Overrun Request Enable x */
-                vuint32_t ORE11:1;      /* Overrun Request Enable x */
-                vuint32_t ORE10:1;      /* Overrun Request Enable x */
-                vuint32_t ORE9:1;       /* Overrun Request Enable x */
-                vuint32_t ORE8:1;       /* Overrun Request Enable x */
-                  vuint32_t:3;  /* reserved in MPC563xM */
-                vuint32_t ORE4:1;       /* Overrun Request Enable x */
-                vuint32_t ORE3:1;       /* Overrun Request Enable x */
-                  vuint32_t:2;  /* reserved in MPC563xM */
-                vuint32_t ORE0:1;       /* Overrun Request Enable x */
-            } B;
-        } ORER;                 /* Overrun Request Enable Register (ORER) <URM>SIU_ORER</URM> @baseaddress + 0x28 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NMIRE:1;      /* NMI Rising-Edge Event Enable x (new in MPC563xM) */
-                  vuint32_t:15; /* reserved in MPC563xM */
-                vuint32_t IREE15:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE14:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE13:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE12:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE11:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE10:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE9:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE8:1;      /* IRQ Rising-Edge Event Enable x */
-                  vuint32_t:3;  /* reserved in MPC563xM */
-                vuint32_t IREE4:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE3:1;      /* IRQ Rising-Edge Event Enable x */
-                  vuint32_t:2;  /* reserved in MPC563xM */
-                vuint32_t IREE0:1;      /* IRQ Rising-Edge Event Enable x */
-            } B;
-        } IREER;                /* External IRQ Rising-Edge Event Enable Register (IREER) <URM>SIU_IREER</URM> @baseaddress + 0x2C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NMIFE:1;      /* NMI Falling-Edge Event Enable x (new in MPC563xM) */
-                vuint32_t Reserverd:15; /*  */
-                vuint32_t IFEE15:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE14:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE13:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE12:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE11:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE10:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE9:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE8:1;      /* IRQ Falling-Edge Event Enable x */
-                  vuint32_t:3;  /* reserved in MPC563xM */
-                vuint32_t IFEE4:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE3:1;      /* IRQ Falling-Edge Event Enable x */
-                  vuint32_t:2;  /* reserved in MPC563xM */
-                vuint32_t IFEE0:1;      /* IRQ Falling-Edge Event Enable x */
-            } B;
-        } IFEER;                /* External IRQ Falling-Edge Event Enable Regi (IFEER) <URM>SIU_IFEER</URM> @baseaddress + 0x30 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;   /*  */
-                vuint32_t DFL:4;        /* Digital Filter Length */
-            } B;
-        } IDFR;                 /* External IRQ Digital Filter Register (IDFR) <URM>SIU_IDFR</URM> @baseaddress + 0x40 */
-
-        int32_t SIU_reserverd_153[3];
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:2;    /*  */
-                vuint16_t PA:4; /*  */
-                vuint16_t OBE:1;        /*  */
-                vuint16_t IBE:1;        /*  */
-                vuint16_t DSC:2;        /*  */
-                vuint16_t ODE:1;        /*  */
-                vuint16_t HYS:1;        /*  */
-                vuint16_t SRC:2;        /*  */
-                vuint16_t WPE:1;        /*  */
-                vuint16_t WPS:1;        /*  */
-            } B;
-        } PCR[512];             /* Pad Configuration Register  (PCR) <URM>SIU_PCR</URM> @baseaddress + 0x600 */
-
-        int32_t SIU_reserverd_164[112];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:7;     /*  */
-                vuint8_t PDO:1; /*  */
-            } B;
-        } GPDO[512];            /* GPIO Pin Data Output Register (GPDO) <URM>SIU_GDPO</URM> @baseaddress + 0x800 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:7;     /*  */
-                vuint8_t PDI:1; /*  */
-            } B;
-        } GPDI[256];            /* GPIO Pin Data Input Register (GDPI) <URM>SIU_GDPI</URM> @baseaddress + 0x900 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TSEL5:2;      /* eQADC Trigger 5 Input */
-                vuint32_t TSEL4:2;      /* eQADC Trigger 4 Input */
-                vuint32_t TSEL3:2;      /* eQADC Trigger 3 Input */
-                vuint32_t TSEL2:2;      /* eQADC Trigger 4 Input */
-                vuint32_t TSEL1:2;      /* eQADC Trigger 1 Input */
-                vuint32_t TSEL0:2;      /* eQADC Trigger 0 Input */
-                  vuint32_t:20; /*  */
-            } B;
-        } ETISR;                /* eQADC Trigger Input Select Register (ETISR) <URM>SIU_ETISR</URM> @baseaddress + 0x904 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ESEL15:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL14:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL13:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL12:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL11:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL10:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL9:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL8:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL7:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL6:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL5:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL4:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL3:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL2:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL1:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL0:2;      /* External IRQ Input Select x */
-            } B;
-        } EIISR;                /* External IRQ Input Select Register (EIISR) <URM>SIU_EIISR</URM> @baseaddress + 0x908 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;    /* reserved in MPC563xM */
-                vuint32_t SINSELB:2;    /* DSPI_B Data Input Select <URM>SIN-SELB</URM> */
-                vuint32_t SSSELB:2;     /* DSPI_B Slave Select Input Select <URM>SS-SELB</URM> */
-                vuint32_t SCKSELB:2;    /* DSPI_B Clock Input Select <URM>SCK-SELB</URM> */
-                vuint32_t TRIGSELB:2;   /* DSPI_B Trigger Input Select <URM>TRIG-SELB</URM> */
-                vuint32_t SINSELC:2;    /* DSPI_C Data Input Select <URM>SIN-SELC</URM> */
-                vuint32_t SSSELC:2;     /* DSPI_C Slave Select Input Select <URM>SSSELC</URM> */
-                vuint32_t SCKSELC:2;    /* DSPI_C Clock Input Select <URM>SCK-SELC</URM> */
-                vuint32_t TRIGSELC:2;   /* DSPI_C Trigger Input Select <URM>TRIG-SELC</URM> */
-                  vuint32_t:8;  /* reserved in MPC563xM */
-            } B;
-        } DISR;                 /* DSPI Input Select Register (DISR) <URM>SIU_DISR</URM> @baseaddress + 0x90c */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:2;    /*  */
-                vuint32_t ETSEL5:5;     /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL5</URM> */
-                vuint32_t ETSEL4:5;     /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL4</URM> */
-                vuint32_t ETSEL3:5;     /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL3</URM> */
-                vuint32_t ETSEL2:5;     /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL2</URM> */
-                vuint32_t ETSEL1:5;     /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL1</URM> */
-                vuint32_t ETSEL0:5;     /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL0</URM> */
-            } B;
-        } ISEL3;                /* MUX Select Register 3 (ISEL3) (new in MPC563xM) <URM>SIU_ISEL3</URM> @baseaddress + 0x920 */
-
-        int32_t SIU_reserverd_214[4];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:11;   /*  */
-                vuint32_t ESEL5:1;      /* <URM>eSEL5</URM> */
-                  vuint32_t:3;  /*  */
-                vuint32_t ESEL4:1;      /* <URM>eSEL4</URM> */
-                  vuint32_t:3;  /*  */
-                vuint32_t ESEL3:1;      /* <URM>eSEL3</URM> */
-                  vuint32_t:3;  /*  */
-                vuint32_t ESEL2:1;      /* <URM>eSEL2</URM> */
-                  vuint32_t:3;  /*  */
-                vuint32_t ESEL1:1;      /* <URM>eSEL1</URM> */
-                  vuint32_t:3;  /*  */
-                vuint32_t ESEL0:1;      /* <URM>eSEL0</URM> */
-            } B;
-        } ISEL8;                /* MUX Select Register 8 (ISEL8) (new in MPC563xM) <URM>SIU_ISEL8</URM> @baseaddress + 0x924 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:27;   /*  */
-                vuint32_t ETSEL0A:5;    /* <URM>eTSEL0A</URM> */
-            } B;
-        } ISEL9;                /* MUX Select Register 9(ISEL9) <URM>SIU_ISEL9</URM> @baseaddress + 0x980 */
-
-        int32_t SIU_reserverd_230[22];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;   /*  */
-                vuint32_t MATCH:1;      /*  Compare Register Match */
-                vuint32_t DISNEX:1;     /*  Disable Nexus */
-                  vuint32_t:14; /*  */
-                vuint32_t CRSE:1;       /*  Calibration Reflection Suppression Enable (new in MPC563xM) */
-                  vuint32_t:1;  /*  */
-            } B;
-        } CCR;                  /* Chip Configuration Register (CCR) <URM>SIU_CCR</URM> @baseaddress + 0x984 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;   /* The ENGDIV bit is reserved in MPC563xM */
-                vuint32_t EBTS:1;       /* External Bus Tap Select */
-                  vuint32_t:1;  /*  */
-                vuint32_t EBDF:2;       /* External Bus Division Factor */
-            } B;
-        } ECCR;                 /* External Clock Control Register (ECCR) <URM>SIU_ECCR</URM> @baseaddress + 0x988 */
-
-        union {
-            vuint32_t R;
-        } CARH;                 /* Compare A High Register (CARH) <URM>SIU_CMPAH</URM> @baseaddress + 0x98C */
-
-        union {
-            vuint32_t R;
-        } CARL;                 /* Compare A Low Register (CARL) <URM>SIU_CMPAL</URM> @baseaddress + 0x990 */
-
-        union {
-            vuint32_t R;
-        } CBRH;                 /* Compare B High Register (CBRH) <URM>SIU_CMPBH</URM> @baseaddress + 0x994 */
-
-        union {
-            vuint32_t R;
-        } CBRL;                 /* Compare B Low Register (CBRL)  <URM>SIU_CMPBL</URM> @baseaddress + 0x9A0 */
-
-        int32_t SIU_reserverd_250[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:27;   /* Reserved */
-                vuint32_t BYPASS:1;     /* Bypass bit <URM>BY-PASS</URM> */
-                vuint32_t SYSCLKDIV:2;  /* System Clock Divide <URM>SYS-CLKDIV</URM> */
-                  vuint32_t:2;  /* Reserved */
-            } B;
-        } SYSDIV;               /* System Clock Register (SYSDIV) (new in MPC563xM) <URM>SIU_SYSDIV</URM>  @baseaddress + 0x9A4 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CPUSTP:1;     /* CPU stop request. When asserted, a stop request is sent to the following modules: */
-                  vuint32_t:2;  /* Reserved */
-                vuint32_t SWTSTP:1;     /* SWT stop request. When asserted, a stop request is sent to the Software Watchdog */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t TPUSTP:1;     /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */
-                vuint32_t NPCSTP:1;     /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */
-                vuint32_t EBISTP:1;     /* EBI stop request. When asserted, a stop request is sent to the external bus */
-                vuint32_t ADCSTP:1;     /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t MIOSSTP:1;    /* Stop mode request */
-                vuint32_t DFILSTP:1;    /* Decimation filter stop request. When asserted, a stop request is sent to the */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t PITSTP:1;     /* PIT stop request. When asserted, a stop request is sent to the periodical internal */
-                  vuint32_t:3;  /* Reserved */
-                vuint32_t CNCSTP:1;     /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t CNASTP:1;     /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t SPICSTP:1;    /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */
-                vuint32_t SPIBSTP:1;    /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */
-                  vuint32_t:7;  /* Reserved */
-                vuint32_t SCIBSTP:1;    /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */
-                vuint32_t SCIASTP:1;    /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */
-            } B;
-        } HLT;                  /* Halt Register (HLT) (new in MPC563xM) <URM>SIU_HLT</URM> @baseaddress + 0x9A8 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CPUACK:1;     /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                  vuint32_t:2;  /* Reserved */
-                vuint32_t SWTACK:1;     /* SWT stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t TPUACK:1;     /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t NPCACK:1;     /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t EBIACK:1;     /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t ADCACK:1;     /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t MIOSACK:1;    /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t DFILACK:1;    /* Decimation filter stop acknowledge. When asserted, indicates that a stop */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t PITACK:1;     /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                  vuint32_t:3;  /* Reserved */
-                vuint32_t CNCACK:1;     /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t CNAACK:1;     /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t SPICACK:1;    /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t SPIBACK:1;    /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                  vuint32_t:7;  /* Reserved */
-                vuint32_t SCIBACK:1;    /* eSCI B stop acknowledge */
-                vuint32_t SCIAACK:1;    /* eSCI A stop acknowledge. */
-            } B;
-        } HLTACK;               /* Halt Acknowledge Register (HLTACK) (new in MPC563xM) <URM>SIU_HLTACK</URM> @baseaddress + 0x9ac */
-
-        int32_t SIU_reserved3[21];
-
-    };                          /* end of SIU_tag */
-/****************************************************************************/
-/*                     MODULE : EMIOS                                      */
-/****************************************************************************/
-    struct EMIOS_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DOZEEN:1;     /* new in MPC563xM */
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-                vuint32_t GTBE:1;
-                vuint32_t ETB:1;
-                vuint32_t GPREN:1;
-                  vuint32_t:6;
-                vuint32_t SRV:4;
-                vuint32_t GPRE:8;
-                  vuint32_t:8;
-            } B;
-        } MCR;                  /* Module Configuration Register <URM>EMIOSMCR</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t F23:1;
-                vuint32_t F22:1;
-                vuint32_t F21:1;
-                vuint32_t F20:1;
-                vuint32_t F19:1;
-                vuint32_t F18:1;
-                vuint32_t F17:1;
-                vuint32_t F16:1;
-                vuint32_t F15:1;
-                vuint32_t F14:1;
-                vuint32_t F13:1;
-                vuint32_t F12:1;
-                vuint32_t F11:1;
-                vuint32_t F10:1;
-                vuint32_t F9:1;
-                vuint32_t F8:1;
-                vuint32_t F7:1;
-                vuint32_t F6:1;
-                vuint32_t F5:1;
-                vuint32_t F4:1;
-                vuint32_t F3:1;
-                vuint32_t F2:1;
-                vuint32_t F1:1;
-                vuint32_t F0:1;
-            } B;
-        } GFR;                  /* Global FLAG Register  <URM>EMIOSGFLAG</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t OU23:1;
-                vuint32_t OU22:1;
-                vuint32_t OU21:1;
-                vuint32_t OU20:1;
-                vuint32_t OU19:1;
-                vuint32_t OU18:1;
-                vuint32_t OU17:1;
-                vuint32_t OU16:1;
-                vuint32_t OU15:1;
-                vuint32_t OU14:1;
-                vuint32_t OU13:1;
-                vuint32_t OU12:1;
-                vuint32_t OU11:1;
-                vuint32_t OU10:1;
-                vuint32_t OU9:1;
-                vuint32_t OU8:1;
-                vuint32_t OU7:1;
-                vuint32_t OU6:1;
-                vuint32_t OU5:1;
-                vuint32_t OU4:1;
-                vuint32_t OU3:1;
-                vuint32_t OU2:1;
-                vuint32_t OU1:1;
-                vuint32_t OU0:1;
-            } B;
-        } OUDR;                 /* Output Update Disable Register  <URM>EMIOSOUDIS</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;    /*  */
-                vuint32_t CHDIS23:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS22:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS21:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS20:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS19:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS18:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS17:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS16:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS15:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS14:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS13:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS12:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS11:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS10:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS9:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS8:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS7:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS6:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS5:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS4:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS3:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS2:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS1:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS0:1;     /* Enable Channel [n] bit */
-            } B;
-        } UCDIS;                /* Disable Channel (EMIOSUCDIS) <URM>EMIOSUCDIS</URM> (new in MPC563xM) @baseaddress + 0x0C */
-
-        int32_t EMIOS_reserverd_30[4];
-
-        struct {
-            union {
-                vuint32_t R;    /* Channel A Data Register */
-            } CADR;             /* <URM>EMIOSA</URM> */
-
-            union {
-                vuint32_t R;    /* Channel B Data Register */
-            } CBDR;             /* <URM>EMIOSB</URM> */
-
-            union {
-                vuint32_t R;    /* Channel Counter Register */
-            } CCNTR;            /* <URM>EMIOSCNT</URM> */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t FREN:1;
-                    vuint32_t ODIS:1;
-                    vuint32_t ODISSL:2;
-                    vuint32_t UCPRE:2;
-                    vuint32_t UCPREN:1;
-                    vuint32_t DMA:1;
-                      vuint32_t:1;
-                    vuint32_t IF:4;
-                    vuint32_t FCK:1;
-                    vuint32_t FEN:1;
-                      vuint32_t:3;
-                    vuint32_t FORCMA:1;
-                    vuint32_t FORCMB:1;
-                      vuint32_t:1;
-                    vuint32_t BSL:2;
-                    vuint32_t EDSEL:1;
-                    vuint32_t EDPOL:1;
-                    vuint32_t MODE:7;
-                } B;
-            } CCR;              /* Channel Control Register  <URM>EMIOSC</URM> */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t OVR:1;
-                      vuint32_t:15;
-                    vuint32_t OVFL:1;
-                      vuint32_t:12;
-                    vuint32_t UCIN:1;
-                    vuint32_t UCOUT:1;
-                    vuint32_t FLAG:1;
-                } B;
-            } CSR;              /* Channel Status Register <URM>EMIOSS</URM> */
-
-            union {
-                vuint32_t R;    /* Alternate Channel A Data Register */
-            } ALTA;             /* new in MPC563xM <URM>EMIOSALTA</URM> */
-
-            uint32_t emios_channel_reserved[2];
-
-        } CH[24];
-
-    };                          /* end of EMIOS_tag */
-/****************************************************************************/
-/*                     MODULE : ETPU                                      */
-/****************************************************************************/
-    struct ETPU_tag {           /* offset 0x0000 */
-        union {                 /* eTPU module configuration register@baseaddress + 0x00 */
-            vuint32_t R;
-            struct {
-                vuint32_t GEC:1;        /*  Global Exception Clear  */
-                vuint32_t SDMERR:1;     /*  */
-                vuint32_t WDTOA:1;      /*  */
-                vuint32_t WDTOB:1;      /*  */
-                vuint32_t MGE1:1;       /* <URM>MGEA</URM> */
-                vuint32_t MGE2:1;       /* <URM>MGEB</URM> */
-                vuint32_t ILF1:1;       /* Invalid instruction flag eTPU A. <URM>ILFFA</URM> */
-                vuint32_t ILF2:1;       /* Invalid instruction flag eTPU B. <URM>ILFFB</URM> */
-                vuint32_t SCMERR:1;     /* . */
-                  vuint32_t:2;  /*  */
-                vuint32_t SCMSIZE:5;    /*  Shared Code Memory size  */
-                  vuint32_t:4;  /*  */
-                vuint32_t SCMMISC:1;    /*  SCM MISC Flag  */
-                vuint32_t SCMMISF:1;    /*  SCM MISC Flag  */
-                vuint32_t SCMMISEN:1;   /*  SCM MISC Enable  */
-                  vuint32_t:2;  /*  */
-                vuint32_t VIS:1;        /*  SCM Visability  */
-                  vuint32_t:5;  /*  */
-                vuint32_t GTBE:1;       /*  Global Time Base Enable  */
-            } B;
-        } MCR;                  /* <URM>ETPU_MCR</URM> */
-
-        /* offset 0x0004 */
-        union {                 /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */
-            vuint32_t R;
-            struct {
-                vuint32_t STS:1;        /*  Start Status bit  */
-                vuint32_t CTBASE:5;     /*  Channel Transfer Base  */
-                vuint32_t PBASE:10;     /*  Parameter Buffer Base Address  <URM>PBBASE</URM> */
-                vuint32_t PWIDTH:1;     /*  Parameter Width  */
-                vuint32_t PARAM0:7;     /*  Channel Parameter 0  <URM>PARM0</URM> */
-                vuint32_t WR:1; /*  */
-                vuint32_t PARAM1:7;     /*  Channel Parameter 1  <URM>PARM1</URM> */
-            } B;
-        } CDCR;                 /*<URM>ETPU_CDCR</URM> */
-
-        vuint32_t ETPU_reserved_0;
-
-        /* offset 0x000C */
-        union {                 /* eTPU MISC Compare Register@baseaddress + 0x0c */
-            vuint32_t R;
-            struct {
-                vuint32_t ETPUMISCCMP:32;       /* Expected multiple input signature calculator compare register value. <URM>EMISCCMP</URM> */
-            } B;
-        } MISCCMPR /*<URM>ETPU_MISCCMPR</URM> */ ;
-
-        /* offset 0x0010 */
-        union {                 /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */
-            vuint32_t R;
-            struct {
-                vuint32_t ETPUSCMOFFDATA:32;    /* SCM Off-range read data value. */
-            } B;
-        } SCMOFFDATAR;          /*<URM>ETPU_SCMOFFDATAR</URM> */
-
-        /* offset 0x0014 */
-        union {                 /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */
-            vuint32_t R;
-            struct {
-                vuint32_t FEND:1;       /*  Force END  */
-                vuint32_t MDIS:1;       /*  Low power Stop  */
-                  vuint32_t:1;  /*  */
-                vuint32_t STF:1;        /*  Stop Flag  */
-                  vuint32_t:4;  /*  */
-                vuint32_t HLTF:1;       /*  Halt Mode Flag  */
-                  vuint32_t:3;  /*  */
-                vuint32_t FCSS:1;
-                vuint32_t FPSCK:3;      /*  Filter Prescaler Clock Control  */
-                vuint32_t CDFC:2;       /*  */
-                  vuint32_t:1;  /*  */
-                vuint32_t ERBA:5;       /*  */
-                vuint32_t SPPDIS:1;     /*  */
-                  vuint32_t:2;  /*  */
-                vuint32_t ETB:5;        /*  Entry Table Base  */
-            } B;
-        } ECR_A;                /*<URM>ETPU_ECR</URM> */
-
-        vuint32_t ETPU_reserved_1[2];
-
-        /* offset 0x0020 */
-        union {                 /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */
-            vuint32_t R;
-            struct {
-                vuint32_t TCR2CTL:3;    /*  TCR2 Clock/Gate Control  */
-                vuint32_t TCRCF:2;      /*  TCRCLK Signal Filter Control  */
-                vuint32_t AM:2; /*  Angle Mode  */
-                  vuint32_t:3;  /*  */
-                vuint32_t TCR2P:6;      /*  TCR2 Prescaler Control  */
-                vuint32_t TCR1CTL:2;    /*  TCR1 Clock/Gate Control  */
-                vuint32_t TCR1CS:1;     /*  */
-                  vuint32_t:5;  /*  */
-                vuint32_t TCR1P:8;      /*  TCR1 Prescaler Control  */
-            } B;
-        } TBCR_A;               /*<URM>ETPU_TBCR</URM> */
-
-        /* offset 0x0024 */
-        union {                 /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */
-            vuint32_t R;
-            struct {
-                vuint32_t:8;    /*  */
-                vuint32_t TCR1:24;      /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */
-            } B;
-        } TB1R_A;               /*<URM>ETPU_TB1R</URM> */
-
-        /* offset 0x0028 */
-        union {                 /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */
-            vuint32_t R;
-            struct {
-                vuint32_t:8;    /*  */
-                vuint32_t TCR2:24;      /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */
-            } B;
-        } TB2R_A;               /*<URM>ETPU_TB2R</URM> */
-
-        /* offset 0x002C */
-        union {                 /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */
-            vuint32_t R;
-            struct {
-                vuint32_t REN1:1;       /*  Resource Enable TCR1  */
-                vuint32_t RSC1:1;       /*  Resource Control TCR1  */
-                  vuint32_t:2;  /*  */
-                vuint32_t SERVER_ID1:4; /*  */
-                  vuint32_t:4;  /*  */
-                vuint32_t SRV1:4;       /*  Resource Server Slot  */
-                vuint32_t REN2:1;       /*  Resource Enable TCR2  */
-                vuint32_t RSC2:1;       /*  Resource Control TCR2  */
-                  vuint32_t:2;  /*  */
-                vuint32_t SERVER_ID2:4; /*  */
-                  vuint32_t:4;  /*  */
-                vuint32_t SRV2:4;       /*  Resource Server Slot  */
-            } B;
-        } REDCR_A;              /*<URM>ETPU_REDCR</URM> */
-
-        vuint32_t ETPU_reserved_2[12];
-
-        /* offset 0x0060 */
-        union {                 /* ETPU1 WDTR Register */
-            vuint32_t R;
-            struct {
-                vuint32_t WDM:2;
-                  vuint32_t:14;
-                vuint32_t WDCNT:16;
-            } B;
-        } WDTR_A;
-
-        vuint32_t ETPU1_reserved_3;
-
-        /* offset 0x0068 */
-        union {                 /* ETPU1 IDLE Register */
-            vuint32_t R;
-            struct {
-                vuint32_t IDLE_CNT:31;
-                vuint32_t ICLR:1;
-            } B;
-        } IDLE_A;
-
-        vuint32_t ETPU_reserved_4[101];
-
-        /* offset 0x0200 */
-        union {                 /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */
-            vuint32_t R;
-            struct {
-                vuint32_t CIS31:1;      /*  Channel 31 Interrut Status  */
-                vuint32_t CIS30:1;      /*  Channel 30 Interrut Status  */
-                vuint32_t CIS29:1;      /*  Channel 29 Interrut Status  */
-                vuint32_t CIS28:1;      /*  Channel 28 Interrut Status  */
-                vuint32_t CIS27:1;      /*  Channel 27 Interrut Status  */
-                vuint32_t CIS26:1;      /*  Channel 26 Interrut Status  */
-                vuint32_t CIS25:1;      /*  Channel 25 Interrut Status  */
-                vuint32_t CIS24:1;      /*  Channel 24 Interrut Status  */
-                vuint32_t CIS23:1;      /*  Channel 23 Interrut Status  */
-                vuint32_t CIS22:1;      /*  Channel 22 Interrut Status  */
-                vuint32_t CIS21:1;      /*  Channel 21 Interrut Status  */
-                vuint32_t CIS20:1;      /*  Channel 20 Interrut Status  */
-                vuint32_t CIS19:1;      /*  Channel 19 Interrut Status  */
-                vuint32_t CIS18:1;      /*  Channel 18 Interrut Status  */
-                vuint32_t CIS17:1;      /*  Channel 17 Interrut Status  */
-                vuint32_t CIS16:1;      /*  Channel 16 Interrut Status  */
-                vuint32_t CIS15:1;      /*  Channel 15 Interrut Status  */
-                vuint32_t CIS14:1;      /*  Channel 14 Interrut Status  */
-                vuint32_t CIS13:1;      /*  Channel 13 Interrut Status  */
-                vuint32_t CIS12:1;      /*  Channel 12 Interrut Status  */
-                vuint32_t CIS11:1;      /*  Channel 11 Interrut Status  */
-                vuint32_t CIS10:1;      /*  Channel 10 Interrut Status  */
-                vuint32_t CIS9:1;       /*  Channel 9 Interrut Status  */
-                vuint32_t CIS8:1;       /*  Channel 8 Interrut Status  */
-                vuint32_t CIS7:1;       /*  Channel 7 Interrut Status  */
-                vuint32_t CIS6:1;       /*  Channel 6 Interrut Status  */
-                vuint32_t CIS5:1;       /*  Channel 5 Interrut Status  */
-                vuint32_t CIS4:1;       /*  Channel 4 Interrut Status  */
-                vuint32_t CIS3:1;       /*  Channel 3 Interrut Status  */
-                vuint32_t CIS2:1;       /*  Channel 2 Interrut Status  */
-                vuint32_t CIS1:1;       /*  Channel 1 Interrut Status  */
-                vuint32_t CIS0:1;       /*  Channel 0 Interrut Status  */
-            } B;
-        } CISR_A;               /* <URM>ETPU_CISR</URM> */
-
-        int32_t ETPU_reserved_5[3];
-
-        /* offset 0x0210 */
-        union {                 /* @baseaddress + 0x210 */
-            vuint32_t R;
-            struct {
-                vuint32_t DTRS31:1;     /*  Channel 31 Data Transfer Request Status  */
-                vuint32_t DTRS30:1;     /*  Channel 30 Data Transfer Request Status  */
-                vuint32_t DTRS29:1;     /*  Channel 29 Data Transfer Request Status  */
-                vuint32_t DTRS28:1;     /*  Channel 28 Data Transfer Request Status  */
-                vuint32_t DTRS27:1;     /*  Channel 27 Data Transfer Request Status  */
-                vuint32_t DTRS26:1;     /*  Channel 26 Data Transfer Request Status  */
-                vuint32_t DTRS25:1;     /*  Channel 25 Data Transfer Request Status  */
-                vuint32_t DTRS24:1;     /*  Channel 24 Data Transfer Request Status  */
-                vuint32_t DTRS23:1;     /*  Channel 23 Data Transfer Request Status  */
-                vuint32_t DTRS22:1;     /*  Channel 22 Data Transfer Request Status  */
-                vuint32_t DTRS21:1;     /*  Channel 21 Data Transfer Request Status  */
-                vuint32_t DTRS20:1;     /*  Channel 20 Data Transfer Request Status  */
-                vuint32_t DTRS19:1;     /*  Channel 19 Data Transfer Request Status  */
-                vuint32_t DTRS18:1;     /*  Channel 18 Data Transfer Request Status  */
-                vuint32_t DTRS17:1;     /*  Channel 17 Data Transfer Request Status  */
-                vuint32_t DTRS16:1;     /*  Channel 16 Data Transfer Request Status  */
-                vuint32_t DTRS15:1;     /*  Channel 15 Data Transfer Request Status  */
-                vuint32_t DTRS14:1;     /*  Channel 14 Data Transfer Request Status  */
-                vuint32_t DTRS13:1;     /*  Channel 13 Data Transfer Request Status  */
-                vuint32_t DTRS12:1;     /*  Channel 12 Data Transfer Request Status  */
-                vuint32_t DTRS11:1;     /*  Channel 11 Data Transfer Request Status  */
-                vuint32_t DTRS10:1;     /*  Channel 10 Data Transfer Request Status  */
-                vuint32_t DTRS9:1;      /*  Channel 9 Data Transfer Request Status  */
-                vuint32_t DTRS8:1;      /*  Channel 8 Data Transfer Request Status  */
-                vuint32_t DTRS7:1;      /*  Channel 7 Data Transfer Request Status  */
-                vuint32_t DTRS6:1;      /*  Channel 6 Data Transfer Request Status  */
-                vuint32_t DTRS5:1;      /*  Channel 5 Data Transfer Request Status  */
-                vuint32_t DTRS4:1;      /*  Channel 4 Data Transfer Request Status  */
-                vuint32_t DTRS3:1;      /*  Channel 3 Data Transfer Request Status  */
-                vuint32_t DTRS2:1;      /*  Channel 2 Data Transfer Request Status  */
-                vuint32_t DTRS1:1;      /*  Channel 1 Data Transfer Request Status  */
-                vuint32_t DTRS0:1;      /*  Channel 0 Data Transfer Request Status  */
-            } B;
-        } CDTRSR_A;             /* <URM>ETPU_CDTRSR</URM> */
-
-        int32_t ETPU_reserved_6[3];
-
-        /* offset 0x0220 */
-        union {                 /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */
-            vuint32_t R;
-            struct {
-                vuint32_t CIOS31:1;     /*  Channel 31 Interruput Overflow Status  */
-                vuint32_t CIOS30:1;     /*  Channel 30 Interruput Overflow Status  */
-                vuint32_t CIOS29:1;     /*  Channel 29 Interruput Overflow Status  */
-                vuint32_t CIOS28:1;     /*  Channel 28 Interruput Overflow Status  */
-                vuint32_t CIOS27:1;     /*  Channel 27 Interruput Overflow Status  */
-                vuint32_t CIOS26:1;     /*  Channel 26 Interruput Overflow Status  */
-                vuint32_t CIOS25:1;     /*  Channel 25 Interruput Overflow Status  */
-                vuint32_t CIOS24:1;     /*  Channel 24 Interruput Overflow Status  */
-                vuint32_t CIOS23:1;     /*  Channel 23 Interruput Overflow Status  */
-                vuint32_t CIOS22:1;     /*  Channel 22 Interruput Overflow Status  */
-                vuint32_t CIOS21:1;     /*  Channel 21 Interruput Overflow Status  */
-                vuint32_t CIOS20:1;     /*  Channel 20 Interruput Overflow Status  */
-                vuint32_t CIOS19:1;     /*  Channel 19 Interruput Overflow Status  */
-                vuint32_t CIOS18:1;     /*  Channel 18 Interruput Overflow Status  */
-                vuint32_t CIOS17:1;     /*  Channel 17 Interruput Overflow Status  */
-                vuint32_t CIOS16:1;     /*  Channel 16 Interruput Overflow Status  */
-                vuint32_t CIOS15:1;     /*  Channel 15 Interruput Overflow Status  */
-                vuint32_t CIOS14:1;     /*  Channel 14 Interruput Overflow Status  */
-                vuint32_t CIOS13:1;     /*  Channel 13 Interruput Overflow Status  */
-                vuint32_t CIOS12:1;     /*  Channel 12 Interruput Overflow Status  */
-                vuint32_t CIOS11:1;     /*  Channel 11 Interruput Overflow Status  */
-                vuint32_t CIOS10:1;     /*  Channel 10 Interruput Overflow Status  */
-                vuint32_t CIOS9:1;      /*  Channel 9 Interruput Overflow Status  */
-                vuint32_t CIOS8:1;      /*  Channel 8 Interruput Overflow Status  */
-                vuint32_t CIOS7:1;      /*  Channel 7 Interruput Overflow Status  */
-                vuint32_t CIOS6:1;      /*  Channel 6 Interruput Overflow Status  */
-                vuint32_t CIOS5:1;      /*  Channel 5 Interruput Overflow Status  */
-                vuint32_t CIOS4:1;      /*  Channel 4 Interruput Overflow Status  */
-                vuint32_t CIOS3:1;      /*  Channel 3 Interruput Overflow Status  */
-                vuint32_t CIOS2:1;      /*  Channel 2 Interruput Overflow Status  */
-                vuint32_t CIOS1:1;      /*  Channel 1 Interruput Overflow Status  */
-                vuint32_t CIOS0:1;      /*  Channel 0 Interruput Overflow Status  */
-            } B;
-        } CIOSR_A;              /* <URM>ETPU_CIOSR</URM> */
-
-        int32_t ETPU_reserved_7[3];
-
-        /* offset 0x0230 */
-        union {                 /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */
-            vuint32_t R;
-            struct {
-                vuint32_t DTROS31:1;    /*  Channel 31 Data Transfer Overflow Status  */
-                vuint32_t DTROS30:1;    /*  Channel 30 Data Transfer Overflow Status  */
-                vuint32_t DTROS29:1;    /*  Channel 29 Data Transfer Overflow Status  */
-                vuint32_t DTROS28:1;    /*  Channel 28 Data Transfer Overflow Status  */
-                vuint32_t DTROS27:1;    /*  Channel 27 Data Transfer Overflow Status  */
-                vuint32_t DTROS26:1;    /*  Channel 26 Data Transfer Overflow Status  */
-                vuint32_t DTROS25:1;    /*  Channel 25 Data Transfer Overflow Status  */
-                vuint32_t DTROS24:1;    /*  Channel 24 Data Transfer Overflow Status  */
-                vuint32_t DTROS23:1;    /*  Channel 23 Data Transfer Overflow Status  */
-                vuint32_t DTROS22:1;    /*  Channel 22 Data Transfer Overflow Status  */
-                vuint32_t DTROS21:1;    /*  Channel 21 Data Transfer Overflow Status  */
-                vuint32_t DTROS20:1;    /*  Channel 20 Data Transfer Overflow Status  */
-                vuint32_t DTROS19:1;    /*  Channel 19 Data Transfer Overflow Status  */
-                vuint32_t DTROS18:1;    /*  Channel 18 Data Transfer Overflow Status  */
-                vuint32_t DTROS17:1;    /*  Channel 17 Data Transfer Overflow Status  */
-                vuint32_t DTROS16:1;    /*  Channel 16 Data Transfer Overflow Status  */
-                vuint32_t DTROS15:1;    /*  Channel 15 Data Transfer Overflow Status  */
-                vuint32_t DTROS14:1;    /*  Channel 14 Data Transfer Overflow Status  */
-                vuint32_t DTROS13:1;    /*  Channel 13 Data Transfer Overflow Status  */
-                vuint32_t DTROS12:1;    /*  Channel 12 Data Transfer Overflow Status  */
-                vuint32_t DTROS11:1;    /*  Channel 11 Data Transfer Overflow Status  */
-                vuint32_t DTROS10:1;    /*  Channel 10 Data Transfer Overflow Status  */
-                vuint32_t DTROS9:1;     /*  Channel 9 Data Transfer Overflow Status  */
-                vuint32_t DTROS8:1;     /*  Channel 8 Data Transfer Overflow Status  */
-                vuint32_t DTROS7:1;     /*  Channel 7 Data Transfer Overflow Status  */
-                vuint32_t DTROS6:1;     /*  Channel 6 Data Transfer Overflow Status  */
-                vuint32_t DTROS5:1;     /*  Channel 5 Data Transfer Overflow Status  */
-                vuint32_t DTROS4:1;     /*  Channel 4 Data Transfer Overflow Status  */
-                vuint32_t DTROS3:1;     /*  Channel 3 Data Transfer Overflow Status  */
-                vuint32_t DTROS2:1;     /*  Channel 2 Data Transfer Overflow Status  */
-                vuint32_t DTROS1:1;     /*  Channel 1 Data Transfer Overflow Status  */
-                vuint32_t DTROS0:1;     /*  Channel 0 Data Transfer Overflow Status  */
-            } B;
-        } CDTROSR_A;            /* <URM>ETPU_CDTROSR</URM> */
-
-        int32_t ETPU_reserved_8[3];
-
-        /* offset 0x0240 */
-        union {                 /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */
-            vuint32_t R;
-            struct {
-                vuint32_t CIE31:1;      /*  Channel 31 Interruput Enable  */
-                vuint32_t CIE30:1;      /*  Channel 30 Interruput Enable  */
-                vuint32_t CIE29:1;      /*  Channel 29 Interruput Enable  */
-                vuint32_t CIE28:1;      /*  Channel 28 Interruput Enable  */
-                vuint32_t CIE27:1;      /*  Channel 27 Interruput Enable  */
-                vuint32_t CIE26:1;      /*  Channel 26 Interruput Enable  */
-                vuint32_t CIE25:1;      /*  Channel 25 Interruput Enable  */
-                vuint32_t CIE24:1;      /*  Channel 24 Interruput Enable  */
-                vuint32_t CIE23:1;      /*  Channel 23 Interruput Enable  */
-                vuint32_t CIE22:1;      /*  Channel 22 Interruput Enable  */
-                vuint32_t CIE21:1;      /*  Channel 21 Interruput Enable  */
-                vuint32_t CIE20:1;      /*  Channel 20 Interruput Enable  */
-                vuint32_t CIE19:1;      /*  Channel 19 Interruput Enable  */
-                vuint32_t CIE18:1;      /*  Channel 18 Interruput Enable  */
-                vuint32_t CIE17:1;      /*  Channel 17 Interruput Enable  */
-                vuint32_t CIE16:1;      /*  Channel 16 Interruput Enable  */
-                vuint32_t CIE15:1;      /*  Channel 15 Interruput Enable  */
-                vuint32_t CIE14:1;      /*  Channel 14 Interruput Enable  */
-                vuint32_t CIE13:1;      /*  Channel 13 Interruput Enable  */
-                vuint32_t CIE12:1;      /*  Channel 12 Interruput Enable  */
-                vuint32_t CIE11:1;      /*  Channel 11 Interruput Enable  */
-                vuint32_t CIE10:1;      /*  Channel 10 Interruput Enable  */
-                vuint32_t CIE9:1;       /*  Channel 9 Interruput Enable  */
-                vuint32_t CIE8:1;       /*  Channel 8 Interruput Enable  */
-                vuint32_t CIE7:1;       /*  Channel 7 Interruput Enable  */
-                vuint32_t CIE6:1;       /*  Channel 6 Interruput Enable  */
-                vuint32_t CIE5:1;       /*  Channel 5 Interruput Enable  */
-                vuint32_t CIE4:1;       /*  Channel 4 Interruput Enable  */
-                vuint32_t CIE3:1;       /*  Channel 3 Interruput Enable  */
-                vuint32_t CIE2:1;       /*  Channel 2 Interruput Enable  */
-                vuint32_t CIE1:1;       /*  Channel 1 Interruput Enable  */
-                vuint32_t CIE0:1;       /*  Channel 0 Interruput Enable  */
-            } B;
-        } CIER_A;               /* <URM>ETPU_CIER</URM> */
-
-        int32_t ETPU_reserved_9[3];
-
-        /* offset 0x0250 */
-        union {                 /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */
-            vuint32_t R;
-            struct {
-                vuint32_t DTRE31:1;     /*  Channel 31 Data Transfer Request Enable  */
-                vuint32_t DTRE30:1;     /*  Channel 30 Data Transfer Request Enable  */
-                vuint32_t DTRE29:1;     /*  Channel 29 Data Transfer Request Enable  */
-                vuint32_t DTRE28:1;     /*  Channel 28 Data Transfer Request Enable  */
-                vuint32_t DTRE27:1;     /*  Channel 27 Data Transfer Request Enable  */
-                vuint32_t DTRE26:1;     /*  Channel 26 Data Transfer Request Enable  */
-                vuint32_t DTRE25:1;     /*  Channel 25 Data Transfer Request Enable  */
-                vuint32_t DTRE24:1;     /*  Channel 24 Data Transfer Request Enable  */
-                vuint32_t DTRE23:1;     /*  Channel 23 Data Transfer Request Enable  */
-                vuint32_t DTRE22:1;     /*  Channel 22 Data Transfer Request Enable  */
-                vuint32_t DTRE21:1;     /*  Channel 21 Data Transfer Request Enable  */
-                vuint32_t DTRE20:1;     /*  Channel 20 Data Transfer Request Enable  */
-                vuint32_t DTRE19:1;     /*  Channel 19 Data Transfer Request Enable  */
-                vuint32_t DTRE18:1;     /*  Channel 18 Data Transfer Request Enable  */
-                vuint32_t DTRE17:1;     /*  Channel 17 Data Transfer Request Enable  */
-                vuint32_t DTRE16:1;     /*  Channel 16 Data Transfer Request Enable  */
-                vuint32_t DTRE15:1;     /*  Channel 15 Data Transfer Request Enable  */
-                vuint32_t DTRE14:1;     /*  Channel 14 Data Transfer Request Enable  */
-                vuint32_t DTRE13:1;     /*  Channel 13 Data Transfer Request Enable  */
-                vuint32_t DTRE12:1;     /*  Channel 12 Data Transfer Request Enable  */
-                vuint32_t DTRE11:1;     /*  Channel 11 Data Transfer Request Enable  */
-                vuint32_t DTRE10:1;     /*  Channel 10 Data Transfer Request Enable  */
-                vuint32_t DTRE9:1;      /*  Channel 9 Data Transfer Request Enable  */
-                vuint32_t DTRE8:1;      /*  Channel 8 Data Transfer Request Enable  */
-                vuint32_t DTRE7:1;      /*  Channel 7 Data Transfer Request Enable  */
-                vuint32_t DTRE6:1;      /*  Channel 6 Data Transfer Request Enable  */
-                vuint32_t DTRE5:1;      /*  Channel 5 Data Transfer Request Enable  */
-                vuint32_t DTRE4:1;      /*  Channel 4 Data Transfer Request Enable  */
-                vuint32_t DTRE3:1;      /*  Channel 3 Data Transfer Request Enable  */
-                vuint32_t DTRE2:1;      /*  Channel 2 Data Transfer Request Enable  */
-                vuint32_t DTRE1:1;      /*  Channel 1 Data Transfer Request Enable  */
-                vuint32_t DTRE0:1;      /*  Channel 0 Data Transfer Request Enable  */
-            } B;
-        } CDTRER_A;             /* <URM>ETPU_CDTRER</URM> */
-
-        int32_t ETPU_reserved_10[3];
-
-        /* offset 0x0260 */
-        union {                 /* ETPUWDSR - eTPU Watchdog Status Register */
-            vuint32_t R;
-            struct {
-                vuint32_t WDS31:1;      /*  Channel 31 Data Transfer Request Enable  */
-                vuint32_t WDS30:1;      /*  Channel 30 Data Transfer Request Enable  */
-                vuint32_t WDS29:1;      /*  Channel 29 Data Transfer Request Enable  */
-                vuint32_t WDS28:1;      /*  Channel 28 Data Transfer Request Enable  */
-                vuint32_t WDS27:1;      /*  Channel 27 Data Transfer Request Enable  */
-                vuint32_t WDS26:1;      /*  Channel 26 Data Transfer Request Enable  */
-                vuint32_t WDS25:1;      /*  Channel 25 Data Transfer Request Enable  */
-                vuint32_t WDS24:1;      /*  Channel 24 Data Transfer Request Enable  */
-                vuint32_t WDS23:1;      /*  Channel 23 Data Transfer Request Enable  */
-                vuint32_t WDS22:1;      /*  Channel 22 Data Transfer Request Enable  */
-                vuint32_t WDS21:1;      /*  Channel 21 Data Transfer Request Enable  */
-                vuint32_t WDS20:1;      /*  Channel 20 Data Transfer Request Enable  */
-                vuint32_t WDS19:1;      /*  Channel 19 Data Transfer Request Enable  */
-                vuint32_t WDS18:1;      /*  Channel 18 Data Transfer Request Enable  */
-                vuint32_t WDS17:1;      /*  Channel 17 Data Transfer Request Enable  */
-                vuint32_t WDS16:1;      /*  Channel 16 Data Transfer Request Enable  */
-                vuint32_t WDS15:1;      /*  Channel 15 Data Transfer Request Enable  */
-                vuint32_t WDS14:1;      /*  Channel 14 Data Transfer Request Enable  */
-                vuint32_t WDS13:1;      /*  Channel 13 Data Transfer Request Enable  */
-                vuint32_t WDS12:1;      /*  Channel 12 Data Transfer Request Enable  */
-                vuint32_t WDS11:1;      /*  Channel 11 Data Transfer Request Enable  */
-                vuint32_t WDS10:1;      /*  Channel 10 Data Transfer Request Enable  */
-                vuint32_t WDS9:1;       /*  Channel 9 Data Transfer Request Enable  */
-                vuint32_t WDS8:1;       /*  Channel 8 Data Transfer Request Enable  */
-                vuint32_t WDS7:1;       /*  Channel 7 Data Transfer Request Enable  */
-                vuint32_t WDS6:1;       /*  Channel 6 Data Transfer Request Enable  */
-                vuint32_t WDS5:1;       /*  Channel 5 Data Transfer Request Enable  */
-                vuint32_t WDS4:1;       /*  Channel 4 Data Transfer Request Enable  */
-                vuint32_t WDS3:1;       /*  Channel 3 Data Transfer Request Enable  */
-                vuint32_t WDS2:1;       /*  Channel 2 Data Transfer Request Enable  */
-                vuint32_t WDS1:1;       /*  Channel 1 Data Transfer Request Enable  */
-                vuint32_t WDS0:1;       /*  Channel 0 Data Transfer Request Enable  */
-            } B;
-        } WDSR_A;
-
-        int32_t ETPU_reserved_11[7];
-
-        /* offset 0x0280 */
-        union {                 /* ETPUCPSSR - eTPU Channel Pending Service Status Register */
-            vuint32_t R;
-            struct {
-                vuint32_t SR31:1;       /*  Channel 31 Data Transfer Request Enable  */
-                vuint32_t SR30:1;       /*  Channel 30 Data Transfer Request Enable  */
-                vuint32_t SR29:1;       /*  Channel 29 Data Transfer Request Enable  */
-                vuint32_t SR28:1;       /*  Channel 28 Data Transfer Request Enable  */
-                vuint32_t SR27:1;       /*  Channel 27 Data Transfer Request Enable  */
-                vuint32_t SR26:1;       /*  Channel 26 Data Transfer Request Enable  */
-                vuint32_t SR25:1;       /*  Channel 25 Data Transfer Request Enable  */
-                vuint32_t SR24:1;       /*  Channel 24 Data Transfer Request Enable  */
-                vuint32_t SR23:1;       /*  Channel 23 Data Transfer Request Enable  */
-                vuint32_t SR22:1;       /*  Channel 22 Data Transfer Request Enable  */
-                vuint32_t SR21:1;       /*  Channel 21 Data Transfer Request Enable  */
-                vuint32_t SR20:1;       /*  Channel 20 Data Transfer Request Enable  */
-                vuint32_t SR19:1;       /*  Channel 19 Data Transfer Request Enable  */
-                vuint32_t SR18:1;       /*  Channel 18 Data Transfer Request Enable  */
-                vuint32_t SR17:1;       /*  Channel 17 Data Transfer Request Enable  */
-                vuint32_t SR16:1;       /*  Channel 16 Data Transfer Request Enable  */
-                vuint32_t SR15:1;       /*  Channel 15 Data Transfer Request Enable  */
-                vuint32_t SR14:1;       /*  Channel 14 Data Transfer Request Enable  */
-                vuint32_t SR13:1;       /*  Channel 13 Data Transfer Request Enable  */
-                vuint32_t SR12:1;       /*  Channel 12 Data Transfer Request Enable  */
-                vuint32_t SR11:1;       /*  Channel 11 Data Transfer Request Enable  */
-                vuint32_t SR10:1;       /*  Channel 10 Data Transfer Request Enable  */
-                vuint32_t SR9:1;        /*  Channel 9 Data Transfer Request Enable  */
-                vuint32_t SR8:1;        /*  Channel 8 Data Transfer Request Enable  */
-                vuint32_t SR7:1;        /*  Channel 7 Data Transfer Request Enable  */
-                vuint32_t SR6:1;        /*  Channel 6 Data Transfer Request Enable  */
-                vuint32_t SR5:1;        /*  Channel 5 Data Transfer Request Enable  */
-                vuint32_t SR4:1;        /*  Channel 4 Data Transfer Request Enable  */
-                vuint32_t SR3:1;        /*  Channel 3 Data Transfer Request Enable  */
-                vuint32_t SR2:1;        /*  Channel 2 Data Transfer Request Enable  */
-                vuint32_t SR1:1;        /*  Channel 1 Data Transfer Request Enable  */
-                vuint32_t SR0:1;        /*  Channel 0 Data Transfer Request Enable  */
-            } B;
-        } CPSSR_A;              /* <URM>ETPU_CPSSR</URM> */
-
-        int32_t ETPU_reserved_12[3];
-
-        /* offset 0x0290 */
-        union {                 /* ETPUCSSR - eTPU Channel Service Status Register */
-            vuint32_t R;
-            struct {
-                vuint32_t SS31:1;       /*  Channel 31 Data Transfer Request Enable  */
-                vuint32_t SS30:1;       /*  Channel 30 Data Transfer Request Enable  */
-                vuint32_t SS29:1;       /*  Channel 29 Data Transfer Request Enable  */
-                vuint32_t SS28:1;       /*  Channel 28 Data Transfer Request Enable  */
-                vuint32_t SS27:1;       /*  Channel 27 Data Transfer Request Enable  */
-                vuint32_t SS26:1;       /*  Channel 26 Data Transfer Request Enable  */
-                vuint32_t SS25:1;       /*  Channel 25 Data Transfer Request Enable  */
-                vuint32_t SS24:1;       /*  Channel 24 Data Transfer Request Enable  */
-                vuint32_t SS23:1;       /*  Channel 23 Data Transfer Request Enable  */
-                vuint32_t SS22:1;       /*  Channel 22 Data Transfer Request Enable  */
-                vuint32_t SS21:1;       /*  Channel 21 Data Transfer Request Enable  */
-                vuint32_t SS20:1;       /*  Channel 20 Data Transfer Request Enable  */
-                vuint32_t SS19:1;       /*  Channel 19 Data Transfer Request Enable  */
-                vuint32_t SS18:1;       /*  Channel 18 Data Transfer Request Enable  */
-                vuint32_t SS17:1;       /*  Channel 17 Data Transfer Request Enable  */
-                vuint32_t SS16:1;       /*  Channel 16 Data Transfer Request Enable  */
-                vuint32_t SS15:1;       /*  Channel 15 Data Transfer Request Enable  */
-                vuint32_t SS14:1;       /*  Channel 14 Data Transfer Request Enable  */
-                vuint32_t SS13:1;       /*  Channel 13 Data Transfer Request Enable  */
-                vuint32_t SS12:1;       /*  Channel 12 Data Transfer Request Enable  */
-                vuint32_t SS11:1;       /*  Channel 11 Data Transfer Request Enable  */
-                vuint32_t SS10:1;       /*  Channel 10 Data Transfer Request Enable  */
-                vuint32_t SS9:1;        /*  Channel 9 Data Transfer Request Enable  */
-                vuint32_t SS8:1;        /*  Channel 8 Data Transfer Request Enable  */
-                vuint32_t SS7:1;        /*  Channel 7 Data Transfer Request Enable  */
-                vuint32_t SS6:1;        /*  Channel 6 Data Transfer Request Enable  */
-                vuint32_t SS5:1;        /*  Channel 5 Data Transfer Request Enable  */
-                vuint32_t SS4:1;        /*  Channel 4 Data Transfer Request Enable  */
-                vuint32_t SS3:1;        /*  Channel 3 Data Transfer Request Enable  */
-                vuint32_t SS2:1;        /*  Channel 2 Data Transfer Request Enable  */
-                vuint32_t SS1:1;        /*  Channel 1 Data Transfer Request Enable  */
-                vuint32_t SS0:1;        /*  Channel 0 Data Transfer Request Enable  */
-            } B;
-        } CSSR_A;               /* <URM>ETPU_CSSR</URM> */
-
-        int32_t ETPU_reserved_13[3];
-        int32_t ETPU_reserved_14[88];
-
-/***************************** Channels ********************************/
-/* Note not all devices implement all channels or even 2 engines       */
-/* Each eTPU engine can implement 64 channels, however most devcies    */
-/* only implemnet 32 channels. The eTPU block can implement 1 or 2     */
-/* engines per instantiation                                           */
-/***********************************************************************/
-
-        struct {
-            union {             /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */
-                vuint32_t R;
-                struct {
-                    vuint32_t CIE:1;    /*  Channel Interruput Enable  */
-                    vuint32_t DTRE:1;   /*  Data Transfer Request Enable  */
-                    vuint32_t CPR:2;    /*  Channel Priority  */
-                      vuint32_t:2;      /*  */
-                    vuint32_t ETPD:1;   /*  This bit selects which channel signal, input or output, is used in the entry point selection */
-                    vuint32_t ETCS:1;   /*  Entry Table Condition Select  */
-                      vuint32_t:3;      /*  */
-                    vuint32_t CFS:5;    /*  Channel Function Select  */
-                    vuint32_t ODIS:1;   /*  Output disable  */
-                    vuint32_t OPOL:1;   /*  output polarity  */
-                      vuint32_t:3;      /*  */
-                    vuint32_t CPBA:11;  /*  Channel Parameter Base Address  */
-                } B;
-            } CR;               /* <URM>ETPU_CnCR</URM> */
-
-            union {             /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */
-                vuint32_t R;
-                struct {
-                    vuint32_t CIS:1;    /*  Channel Interruput Status  */
-                    vuint32_t CIOS:1;   /*  Channel Interruput Overflow Status  */
-                      vuint32_t:6;      /*  */
-                    vuint32_t DTRS:1;   /*  Data Transfer Status  */
-                    vuint32_t DTROS:1;  /*  Data Transfer Overflow Status  */
-                      vuint32_t:6;      /*  */
-                    vuint32_t IPS:1;    /*  Input Pin State  */
-                    vuint32_t OPS:1;    /*  Output Pin State  */
-                    vuint32_t OBE:1;    /*  Output Pin State  */
-                      vuint32_t:11;     /*  */
-                    vuint32_t FM1:1;    /* Function mode */
-                    vuint32_t FM0:1;    /* Function mode */
-                } B;
-            } SCR;              /* <URM>ETPU_CnSCR</URM> */
-
-            union {             /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */
-                vuint32_t R;
-                struct {
-                    vuint32_t:29;       /*  Host Service Request  */
-                    vuint32_t HSR:3;    /*  */
-                } B;
-            } HSRR;             /* <URM>ETPU_CnHSRR</URM> */
-            int32_t ETPU_reserved_18;
-
-        } CHAN[127];
-                 /**** Note: Not all channels implemented on all devices. Up 64 can be implemented on */
-    };                          /* end of ETPU_tag */
-/****************************************************************************/
-/*                     MODULE : XBAR                                      */
-/****************************************************************************/
-    struct XBAR_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;    /* Master 7 Priority - Not implemented */
-                vuint32_t:4;    /* Master 6 Priority - Not implemented */
-                vuint32_t:4;    /* Master 5 Priority - Not implemented */
-                vuint32_t:1;    /*  */
-                vuint32_t MSTR4:3;      /* Master 4 Priority - Core load/store & Nexus port */
-                  vuint32_t:4;  /* Master 3 Priority - Not implemented */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR2:3;      /* Master 2 Priority - Unused implemented master port */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR1:3;      /* Master 1 Priority - eDMA */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR0:3;      /* Master 0 Priority - e200z335 core Instruction */
-            } B;
-        } MPR0;                 /* Master Priority Register for Slave port 0 @baseaddress + 0x00  - Flash */
-
-        int32_t XBAR_reserverd_35[3];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RO:1; /* Read Only */
-                vuint32_t HLP:1;        /* Halt Low Priority (new in MPC563xM) */
-                  vuint32_t:6;  /* Slave General Purpose Control Register Reserved */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                vuint32_t HPE4:1;       /* High Priority Enable (new in MPC563xM) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                vuint32_t HPE2:1;       /* High Priority Enable (new in MPC563xM) */
-                vuint32_t HPE1:1;       /* High Priority Enable (new in MPC563xM) */
-                vuint32_t HPE0:1;       /* High Priority Enable (new in MPC563xM) */
-                  vuint32_t:6;  /*  */
-                vuint32_t ARB:2;        /* Arbitration Mode */
-                  vuint32_t:2;  /*  */
-                vuint32_t PCTL:2;       /* Parking Control */
-                  vuint32_t:1;  /*  */
-                vuint32_t PARK:3;       /* PARK */
-            } B;
-        } SGPCR0;               /* Slave General Purpose Control Register 0 @baseaddress + 0x10 */
-
-        int32_t XBAR_reserverd_71[59];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;    /* Master 7 Priority - Not implemented */
-                vuint32_t:4;    /* Master 6 Priority - Not implemented */
-                vuint32_t:4;    /* Master 5 Priority - Not implemented */
-                vuint32_t:1;    /*  */
-                vuint32_t MSTR4:3;      /* Master 4 Priority - Core load/store & Nexus port */
-                  vuint32_t:4;  /* Master 3 Priority - Not implemented */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR2:3;      /* Master 2 Priority - Unused implemented master port */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR1:3;      /* Master 1 Priority - eDMA */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR0:3;      /* Master 0 Priority - e200z335 core Instruction */
-            } B;
-        } MPR1;                 /* Master Priority Register for Slave port 1 @baseaddress + 0x100 */
-
-        int32_t XBAR_reserverd_105[3];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RO:1; /* Read Only */
-                vuint32_t HLP:1;        /* Halt Low Priority (new in MPC563xM) */
-                  vuint32_t:6;  /* Slave General Purpose Control Register Reserved */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                vuint32_t HPE4:1;       /* High Priority Enable (new in MPC563xM) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                vuint32_t HPE2:1;       /* High Priority Enable (new in MPC563xM) */
-                vuint32_t HPE1:1;       /* High Priority Enable (new in MPC563xM) */
-                vuint32_t HPE0:1;       /* High Priority Enable (new in MPC563xM) */
-                  vuint32_t:6;  /*  */
-                vuint32_t ARB:2;        /* Arbitration Mode */
-                  vuint32_t:2;  /*  */
-                vuint32_t PCTL:2;       /* Parking Control */
-                  vuint32_t:1;  /*  */
-                vuint32_t PARK:3;       /* PARK */
-            } B;
-        } SGPCR1;               /* Slave General Purpose Control Register 1 @baseaddress + 0x110 */
-
-        int32_t XBAR_reserverd_141[59];
-
-/* Slave General Purpose Control Register 2 @baseaddress + 0x210  - not implemented */
-
-        int32_t XBAR_reserverd_211[64];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;    /* Master 7 Priority - Not implemented */
-                vuint32_t:4;    /* Master 6 Priority - Not implemented */
-                vuint32_t:4;    /* Master 5 Priority - Not implemented */
-                vuint32_t:1;    /*  */
-                vuint32_t MSTR4:3;      /* Master 4 Priority - Core load/store & Nexus port */
-                  vuint32_t:4;  /* Master 3 Priority - Not implemented */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR2:3;      /* Master 2 Priority - Unused implemented master port */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR1:3;      /* Master 1 Priority - eDMA */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR0:3;      /* Master 0 Priority - e200z335 core Instruction */
-            } B;
-        } MPR3;                 /* Master Priority Register for Slave port 3 @baseaddress + 0x300 */
-
-        int32_t XBAR_reserverd_245[3];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RO:1; /* Read Only */
-                vuint32_t HLP:1;        /* Halt Low Priority (new in MPC563xM) */
-                  vuint32_t:6;  /* Slave General Purpose Control Register Reserved */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                vuint32_t HPE4:1;       /* High Priority Enable (new in MPC563xM) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                vuint32_t HPE2:1;       /* High Priority Enable (new in MPC563xM) */
-                vuint32_t HPE1:1;       /* High Priority Enable (new in MPC563xM) */
-                vuint32_t HPE0:1;       /* High Priority Enable (new in MPC563xM) */
-                  vuint32_t:6;  /*  */
-                vuint32_t ARB:2;        /* Arbitration Mode */
-                  vuint32_t:2;  /*  */
-                vuint32_t PCTL:2;       /* Parking Control */
-                  vuint32_t:1;  /*  */
-                vuint32_t PARK:3;       /* PARK */
-            } B;
-        } SGPCR3;               /* Slave General Purpose Control Register 3 @baseaddress + 0x310 */
-
-        int32_t XBAR_reserverd_281[59];
-
-        /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */
-
-        int32_t XBAR_reserverd_351[64];
-
-        /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */
-
-        int32_t XBAR_reserverd_421[64];
-
-        /* Slave Port 6 not implemented @baseaddress + 0x610 */
-
-        int32_t XBAR_reserverd_491[64];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;    /* Master 7 Priority - Not implemented */
-                vuint32_t:4;    /* Master 6 Priority - Not implemented */
-                vuint32_t:4;    /* Master 5 Priority - Not implemented */
-                vuint32_t:1;    /*  */
-                vuint32_t MSTR4:3;      /* Master 4 Priority - Core load/store & Nexus port */
-                  vuint32_t:4;  /* Master 3 Priority - Not implemented */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR2:3;      /* Master 2 Priority - Unused implemented master port */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR1:3;      /* Master 1 Priority - eDMA */
-                  vuint32_t:1;  /*  */
-                vuint32_t MSTR0:3;      /* Master 0 Priority - e200z335 core Instruction */
-            } B;
-        } MPR7;                 /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */
-
-        int32_t XBAR_reserverd_525[3];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RO:1; /* Read Only */
-                vuint32_t HLP:1;        /* Halt Low Priority (new in MPC563xM) */
-                  vuint32_t:6;  /* Slave General Purpose Control Register Reserved */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                vuint32_t HPE4:1;       /* High Priority Enable (new in MPC563xM) */
-                  vuint32_t:1;  /* High Priority Enable (new in MPC563xM - not implemented) */
-                vuint32_t HPE2:1;       /* High Priority Enable (new in MPC563xM) */
-                vuint32_t HPE1:1;       /* High Priority Enable (new in MPC563xM) */
-                vuint32_t HPE0:1;       /* High Priority Enable (new in MPC563xM) */
-                  vuint32_t:6;  /*  */
-                vuint32_t ARB:2;        /* Arbitration Mode */
-                  vuint32_t:2;  /*  */
-                vuint32_t PCTL:2;       /* Parking Control */
-                  vuint32_t:1;  /*  */
-                vuint32_t PARK:3;       /* PARK */
-            } B;
-        } SGPCR7;               /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */
-
-        int32_t XBAR_reserverd_561[59];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:29;   /*  */
-                vuint32_t AULB:3;       /* Arbitrate on Undefined Length Bursts */
-            } B;
-        } MGPCR0;               /* Master General Purpose Control Register 0 @baseaddress + 0x800 */
-
-        int32_t XBAR_reserverd_564[63];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:29;   /*  */
-                vuint32_t AULB:3;       /* Arbitrate on Undefined Length Bursts */
-            } B;
-        } MGPCR1;               /* Master General Purpose Control Register 1 @baseaddress + 0x900 */
-
-        int32_t XBAR_reserverd_567[63];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:29;   /*  */
-                vuint32_t AULB:3;       /* Arbitrate on Undefined Length Bursts */
-            } B;
-        } MGPCR2;               /* Master General Purpose Control Register 2 @baseaddress + 0xA00 */
-
-        int32_t XBAR_reserverd_570[63];
-
-        /* Master General Purpose Control Register 3 not implemented @baseaddress + 0xB00 */
-
-        int32_t XBAR_reserverd_573[64];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:29;   /*  */
-                vuint32_t AULB:3;       /* Arbitrate on Undefined Length Bursts */
-            } B;
-        } MGPCR4;               /* Master General Purpose Control Register 4 @baseaddress + 0xC00 */
-
-        int32_t XBAR_reserverd_576[64];
-
-        /* Master General Purpose Control Register 5 not implemented @baseaddress + 0xD00 */
-
-        int32_t XBAR_reserverd_579[64];
-
-        /* Master General Purpose Control Register 6 not implemented @baseaddress + 0xE00 */
-
-        int32_t XBAR_reserverd_582[64];
-
-        /* Master General Purpose Control Register 7 not implemented @baseaddress + 0xF00 */
-
-    };                          /* end of XBAR_tag */
-/****************************************************************************/
-/*                     MODULE : ECSM                                       */
-/****************************************************************************/
-    struct ECSM_tag {
-        /* SWTCR, SWTSR and SWTIR don't exist in MPC563xM */
-        uint32_t ecsm_reserved1[16];
-
-        uint8_t ecsm_reserved3[3];      /* base + 0x40 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:6;
-                vuint8_t ERNCR:1;       /* <URM>EPRNCR</URM> */
-                vuint8_t EFNCR:1;       /* <URM>EPFNCR</URM> */
-            } B;
-        } ECR;                  /* ECC Configuration Register */
-
-        uint8_t ecsm_reserved4[3];      /* base + 0x44 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:6;
-                vuint8_t RNCE:1;        /* <URM>PRNCE</URM> */
-                vuint8_t FNCE:1;        /* <URM>PFNCE</URM> */
-            } B;
-        } ESR;                  /* ECC Status Register */
-
-        /* EEGR don't exist in MPC563xM */
-        uint32_t ecsm_reserved4a[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FEAR:32;      /* <URM>PFEAR</URM> */
-            } B;
-        } FEAR;                 /* Flash ECC Address Register <URM>PFEAR</URM> - 0x50 */
-
-        uint16_t ecsm_reserved4b;
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t FEMR:4;        /* <URM>PFEMR</URM> */
-            } B;
-        } FEMR;                 /* Flash ECC Master Register <URM>PFEMR</URM> */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t WRITE:1;
-                vuint8_t SIZE:3;
-                vuint8_t PROT0:1;       /* <URM>PROTECTION</URM> */
-                vuint8_t PROT1:1;       /* <URM>PROTECTION</URM> */
-                vuint8_t PROT2:1;       /* <URM>PROTECTION</URM> */
-                vuint8_t PROT3:1;       /* <URM>PROTECTION</URM> */
-            } B;
-        } FEAT;                 /* Flash ECC Attributes Register <URM>PFEAT</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FEDH:32;      /* <URM>PFEDR</URM> */
-            } B;
-        } FEDRH;                /* Flash ECC Data High Register <URM>PFEDRH</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FEDL:32;      /* <URM>PFEDR</URM> */
-            } B;
-        } FEDRL;                /* Flash ECC Data Low Register <URM>PFEDRL</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t REAR:32;      /* <URM>PREAR</URM> */
-            } B;
-        } REAR;                 /* RAM ECC Address <URM>PREAR</URM> */
-
-        uint8_t ecsm_reserved5;
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t PRESR:8;
-            } B;
-        } PRESR;                /* RAM ECC Syndrome (new in MPC563xM) */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t REMR:4;        /* <URM>PREMR</URM> */
-            } B;
-        } REMR;                 /* RAM ECC Master <URM>PREMR</URM> */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t WRITE:1;
-                vuint8_t SIZE:3;
-                vuint8_t PROT0:1;       /* <URM>PROTECTION</URM> */
-                vuint8_t PROT1:1;       /* <URM>PROTECTION</URM> */
-                vuint8_t PROT2:1;       /* <URM>PROTECTION</URM> */
-                vuint8_t PROT3:1;       /* <URM>PROTECTION</URM> */
-            } B;
-        } REAT;                 /*  RAM ECC Attributes Register <URM>PREAT</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t REDH:32;      /* <URM>PREDR</URM> */
-            } B;
-        } REDRH;                /* RAM ECC Data High Register <URM>PREDRH</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t REDL:32;      /* <URM>PREDR</URM> */
-            } B;
-        } REDRL;                /* RAMECC Data Low Register <URM>PREDRL</URM> */
-
-    };
-/****************************************************************************/
-/*                     MODULE : EDMA                                      */
-/****************************************************************************/
-    struct EDMA_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;   /* Reserved */
-                vuint32_t CX:1; /* Cancel Transfer (new in MPC563xM) */
-                vuint32_t ECX:1;        /* Error Cancel Transfer (new in MPC563xM) */
-                vuint32_t GRP3PRI:2;    /* Channel Group 3 Priority (new in MPC563xM) */
-                vuint32_t GRP2PRI:2;    /* Channel Group 2 Priority (new in MPC563xM) */
-                vuint32_t GRP1PRI:2;    /* Channel Group 1 Priority */
-                vuint32_t GRP0PRI:2;    /* Channel Group 0 Priority */
-                vuint32_t EMLM:1;       /* Enable Minor Loop Mapping (new in MPC563xM) */
-                vuint32_t CLM:1;        /* Continuous Link Mode (new in MPC563xM) */
-                vuint32_t HALT:1;       /* Halt DMA Operations (new in MPC563xM) */
-                vuint32_t HOE:1;        /* Halt On Error (new in MPC563xM) */
-                vuint32_t ERGA:1;       /* Enable Round Robin Group Arbitration */
-                vuint32_t ERCA:1;       /* Enable Round Robin Channel Arbitration */
-                vuint32_t EDBG:1;       /* Enable Debug */
-                vuint32_t EBW:1;        /* Enable Buffered Writes */
-            } B;
-        } CR;                   /* DMA Control Register <URM>DMACR</URM> @baseaddress + 0x0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t VLD:1;        /* Logical OR of all DMAERRH */
-
-                  vuint32_t:14; /* Reserved */
-                vuint32_t ECX:1;        /* (new in MPC563xM) */
-                vuint32_t GPE:1;        /* Group Priority Error */
-                vuint32_t CPE:1;        /* Channel Priority Error  */
-                vuint32_t ERRCHN:6;     /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */
-                vuint32_t SAE:1;        /* Source Address Error 0  */
-                vuint32_t SOE:1;        /* Source Offset Error */
-                vuint32_t DAE:1;        /* Destination Address Error */
-                vuint32_t DOE:1;        /* Destination Offset Error */
-                vuint32_t NCE:1;        /* Nbytes/Citer Configuration Error */
-                vuint32_t SGE:1;        /* Scatter/Gather Configuration Error */
-                vuint32_t SBE:1;        /* Source Bus Error */
-                vuint32_t DBE:1;        /* Destination Bus Error  */
-
-            } B;
-        } ESR;                  /* <URM>DMAES</URM> Error Status Register */
-
-        uint32_t edma_reserved_erqrh;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ERQ31:1;
-                vuint32_t ERQ30:1;
-                vuint32_t ERQ29:1;
-                vuint32_t ERQ28:1;
-                vuint32_t ERQ27:1;
-                vuint32_t ERQ26:1;
-                vuint32_t ERQ25:1;
-                vuint32_t ERQ24:1;
-                vuint32_t ERQ23:1;
-                vuint32_t ERQ22:1;
-                vuint32_t ERQ21:1;
-                vuint32_t ERQ20:1;
-                vuint32_t ERQ19:1;
-                vuint32_t ERQ18:1;
-                vuint32_t ERQ17:1;
-                vuint32_t ERQ16:1;
-                vuint32_t ERQ15:1;
-                vuint32_t ERQ14:1;
-                vuint32_t ERQ13:1;
-                vuint32_t ERQ12:1;
-                vuint32_t ERQ11:1;
-                vuint32_t ERQ10:1;
-                vuint32_t ERQ09:1;
-                vuint32_t ERQ08:1;
-                vuint32_t ERQ07:1;
-                vuint32_t ERQ06:1;
-                vuint32_t ERQ05:1;
-                vuint32_t ERQ04:1;
-                vuint32_t ERQ03:1;
-                vuint32_t ERQ02:1;
-                vuint32_t ERQ01:1;
-                vuint32_t ERQ00:1;
-            } B;
-        } ERQRL;                /* <URM>DMAERQL</URM> ,DMA Enable Request Register Low */
-
-        uint32_t edma_reserved_eeirh;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EEI31:1;
-                vuint32_t EEI30:1;
-                vuint32_t EEI29:1;
-                vuint32_t EEI28:1;
-                vuint32_t EEI27:1;
-                vuint32_t EEI26:1;
-                vuint32_t EEI25:1;
-                vuint32_t EEI24:1;
-                vuint32_t EEI23:1;
-                vuint32_t EEI22:1;
-                vuint32_t EEI21:1;
-                vuint32_t EEI20:1;
-                vuint32_t EEI19:1;
-                vuint32_t EEI18:1;
-                vuint32_t EEI17:1;
-                vuint32_t EEI16:1;
-                vuint32_t EEI15:1;
-                vuint32_t EEI14:1;
-                vuint32_t EEI13:1;
-                vuint32_t EEI12:1;
-                vuint32_t EEI11:1;
-                vuint32_t EEI10:1;
-                vuint32_t EEI09:1;
-                vuint32_t EEI08:1;
-                vuint32_t EEI07:1;
-                vuint32_t EEI06:1;
-                vuint32_t EEI05:1;
-                vuint32_t EEI04:1;
-                vuint32_t EEI03:1;
-                vuint32_t EEI02:1;
-                vuint32_t EEI01:1;
-                vuint32_t EEI00:1;
-            } B;
-        } EEIRL;                /* <URM>DMAEEIL</URM> , DMA Enable Error Interrupt Register Low */
-
-        union {
-            vuint8_t R;
-            vuint8_t B;         /* <URM>NOP:1 SERQ:7</URM> */
-        } SERQR;                /* <URM>DMASERQ</URM> , DMA Set Enable Request Register */
-
-        union {
-            vuint8_t R;
-            vuint8_t B;         /* <URM>NOP:1 CERQ:7</URM> */
-        } CERQR;                /* <URM>DMACERQ</URM> , DMA Clear Enable Request Register */
-
-        union {
-            vuint8_t R;
-            vuint8_t B;         /* <URM>NOP:1 SEEI:7</URM> */
-        } SEEIR;                /* <URM>DMASEEI</URM> , DMA Set Enable Error Interrupt Register */
-
-        union {
-            vuint8_t R;
-            vuint8_t B;         /* <URM>NOP:1 CEEI:7</URM> */
-        } CEEIR;                /* <URM>DMACEEI</URM> , DMA Clear Enable Error Interrupt Register */
-
-        union {
-            vuint8_t R;
-            vuint8_t B;         /* <URM>NOP:1 CINT:7</URM> */
-        } CIRQR;                /* <URM>DMACINT</URM> , DMA Clear Interrupt Request Register */
-
-        union {
-            vuint8_t R;
-            vuint8_t B;         /* <URM>NOP:1 CERR:7</URM> */
-        } CER;                  /* <URM>DMACERR</URM> , DMA Clear error Register */
-
-        union {
-            vuint8_t R;
-            vuint8_t B;         /* <URM>NOP:1 SSRT:7</URM> */
-        } SSBR;                 /* <URM>DMASSRT</URM> , Set Start Bit Register */
-
-        union {
-            vuint8_t R;
-            vuint8_t B;         /* <URM>NOP:1 CDNE:7</URM> */
-        } CDSBR;                /* <URM>DMACDNE</URM> , Clear Done Status Bit Register */
-
-        uint32_t edma_reserved_irqrh;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t INT31:1;
-                vuint32_t INT30:1;
-                vuint32_t INT29:1;
-                vuint32_t INT28:1;
-                vuint32_t INT27:1;
-                vuint32_t INT26:1;
-                vuint32_t INT25:1;
-                vuint32_t INT24:1;
-                vuint32_t INT23:1;
-                vuint32_t INT22:1;
-                vuint32_t INT21:1;
-                vuint32_t INT20:1;
-                vuint32_t INT19:1;
-                vuint32_t INT18:1;
-                vuint32_t INT17:1;
-                vuint32_t INT16:1;
-                vuint32_t INT15:1;
-                vuint32_t INT14:1;
-                vuint32_t INT13:1;
-                vuint32_t INT12:1;
-                vuint32_t INT11:1;
-                vuint32_t INT10:1;
-                vuint32_t INT09:1;
-                vuint32_t INT08:1;
-                vuint32_t INT07:1;
-                vuint32_t INT06:1;
-                vuint32_t INT05:1;
-                vuint32_t INT04:1;
-                vuint32_t INT03:1;
-                vuint32_t INT02:1;
-                vuint32_t INT01:1;
-                vuint32_t INT00:1;
-            } B;
-        } IRQRL;                /* <URM>DMAINTL</URM> , DMA Interrupt Request Low */
-
-        uint32_t edma_reserved_erh;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ERR31:1;
-                vuint32_t ERR30:1;
-                vuint32_t ERR29:1;
-                vuint32_t ERR28:1;
-                vuint32_t ERR27:1;
-                vuint32_t ERR26:1;
-                vuint32_t ERR25:1;
-                vuint32_t ERR24:1;
-                vuint32_t ERR23:1;
-                vuint32_t ERR22:1;
-                vuint32_t ERR21:1;
-                vuint32_t ERR20:1;
-                vuint32_t ERR19:1;
-                vuint32_t ERR18:1;
-                vuint32_t ERR17:1;
-                vuint32_t ERR16:1;
-                vuint32_t ERR15:1;
-                vuint32_t ERR14:1;
-                vuint32_t ERR13:1;
-                vuint32_t ERR12:1;
-                vuint32_t ERR11:1;
-                vuint32_t ERR10:1;
-                vuint32_t ERR09:1;
-                vuint32_t ERR08:1;
-                vuint32_t ERR07:1;
-                vuint32_t ERR06:1;
-                vuint32_t ERR05:1;
-                vuint32_t ERR04:1;
-                vuint32_t ERR03:1;
-                vuint32_t ERR02:1;
-                vuint32_t ERR01:1;
-                vuint32_t ERR00:1;
-            } B;
-        } ERL;                  /* <URM>DMAERRL</URM> , DMA Error Low */
-
-        int32_t edma_reserverd_hrsh[1];
-
-        int32_t edma_reserverd_hrsl[1];
-
-        int32_t edma_reserverd_gpor[1];
-
-        int32_t EDMA_reserverd_223[49];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t ECP:1;
-                vuint8_t DPA:1;
-                vuint8_t GRPPRI:2;
-                vuint8_t CHPRI:4;
-            } B;
-        } CPR[64];              /* <URM>DCHPRI [32]</URM> , Channel n Priority */
-
-        uint32_t edma_reserved2[944];
-
-/****************************************************************************/
-/*       DMA2 Transfer Control Descriptor                                   */
-/****************************************************************************/
-
-        struct tcd_t {          /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */
-            vuint32_t SADDR;    /* source address */
-
-            vuint16_t SMOD:5;   /* source address modulo */
-            vuint16_t SSIZE:3;  /* source transfer size */
-            vuint16_t DMOD:5;   /* destination address modulo */
-            vuint16_t DSIZE:3;  /* destination transfer size */
-            vint16_t SOFF;      /* signed source address offset */
-            vuint32_t NBYTES;   /* inner (�minor�) byte count */
-            vint32_t SLAST;     /* last destination address adjustment, or
-
-                                   scatter/gather address (if e_sg = 1) */
-            vuint32_t DADDR;    /* destination address */
-            vuint16_t CITERE_LINK:1;
-            vuint16_t CITER:15;
-            vint16_t DOFF;      /* signed destination address offset */
-            vint32_t DLAST_SGA;
-            vuint16_t BITERE_LINK:1;    /* beginning ("major") iteration count */
-            vuint16_t BITER:15;
-            vuint16_t BWC:2;    /* bandwidth control */
-            vuint16_t MAJORLINKCH:6;    /* enable channel-to-channel link */
-            vuint16_t DONE:1;   /* channel done */
-            vuint16_t ACTIVE:1; /* channel active */
-            vuint16_t MAJORE_LINK:1;    /* enable channel-to-channel link */
-            vuint16_t E_SG:1;   /* enable scatter/gather descriptor */
-            vuint16_t D_REQ:1;  /* disable ipd_req when done */
-            vuint16_t INT_HALF:1;       /* interrupt on citer = (biter >> 1) */
-            vuint16_t INT_MAJ:1;        /* interrupt on major loop completion */
-            vuint16_t START:1;  /* explicit channel start */
-        } TCD[64];              /* <URM>TCD [32]</URM> , transfer_control_descriptor */
-    };
-
-    struct EDMA_TCD_alt1_tag {  /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */
-
-        struct tcd_alt1_t {
-            vuint32_t SADDR;    /* source address */
-
-            vuint16_t SMOD:5;   /* source address modulo */
-            vuint16_t SSIZE:3;  /* source transfer size */
-            vuint16_t DMOD:5;   /* destination address modulo */
-            vuint16_t DSIZE:3;  /* destination transfer size */
-            vint16_t SOFF;      /* signed source address offset */
-            vuint32_t NBYTES;   /* inner (�minor�) byte count */
-            vint32_t SLAST;     /* last destination address adjustment, or
-
-                                   scatter/gather address (if e_sg = 1) */
-            vuint32_t DADDR;    /* destination address */
-            vuint16_t CITERE_LINK:1;
-            vuint16_t CITERLINKCH:6;
-            vuint16_t CITER:9;
-            vint16_t DOFF;      /* signed destination address offset */
-            vint32_t DLAST_SGA;
-            vuint16_t BITERE_LINK:1;    /* beginning (�major�) iteration count */
-            vuint16_t BITERLINKCH:6;
-            vuint16_t BITER:9;
-            vuint16_t BWC:2;    /* bandwidth control */
-            vuint16_t MAJORLINKCH:6;    /* enable channel-to-channel link */
-            vuint16_t DONE:1;   /* channel done */
-            vuint16_t ACTIVE:1; /* channel active */
-            vuint16_t MAJORE_LINK:1;    /* enable channel-to-channel link */
-            vuint16_t E_SG:1;   /* enable scatter/gather descriptor */
-            vuint16_t D_REQ:1;  /* disable ipd_req when done */
-            vuint16_t INT_HALF:1;       /* interrupt on citer = (biter >> 1) */
-            vuint16_t INT_MAJ:1;        /* interrupt on major loop completion */
-            vuint16_t START:1;  /* explicit channel start */
-        } TCD[64];              /* <URM>TCD [32]</URM> , transfer_control_descriptor */
-    };
-
-/****************************************************************************/
-/*                     MODULE : INTC                                      */
-/****************************************************************************/
-    struct INTC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:18;   /* Reserved */
-                vuint32_t VTES_PRC1:1;  /* Vector Table Entry Size for PRC1 (new in MPC563xM) */
-                  vuint32_t:4;  /* Reserved */
-                vuint32_t HVEN_PRC1:1;  /* Hardware Vector Enable for PRC1 (new in MPC563xM) */
-                  vuint32_t:2;  /* Reserved */
-                vuint32_t VTES:1;       /* Vector Table Entry Size for PRC0 <URM>VTES_PRC0</URM> */
-                  vuint32_t:4;  /* Reserved */
-                vuint32_t HVEN:1;       /* Hardware Vector Enable for PRC0 <URM>HVEN_PRC0</URM> */
-            } B;
-        } MCR;                  /* INTC Module Configuration Register (MCR) <URM>INTC_BCR</URM> @baseaddress + 0x00 */
-        int32_t INTC_reserverd_10[1];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;   /* Reserved */
-                vuint32_t PRI:4;        /* Priority */
-            } B;
-        } CPR;                  /* INTC Current Priority Register for Processor 0 (CPR) <URM>INTC_CPR_PRC0</URM> @baseaddress + 0x08 */
-
-        int32_t INTC_reserved_1;        /* CPR_PRC1 - INTC Current Priority Register for Processor 1 (CPR_PRC1) <URM>INTC_CPR_PRC1</URM> @baseaddress + 0x0c */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t VTBA:21;      /* Vector Table Base Address <URM>VTBA_PRC0</URM> */
-                vuint32_t INTVEC:9;     /* Interrupt Vector <URM>INTVEC_PRC0</URM> */
-                  vuint32_t:2;  /* Reserved */
-            } B;
-        } IACKR;                /* INTC Interrupt Acknowledge Register for Processor 0 (IACKR) <URM>INTC_IACKR_PRC0</URM> @baseaddress + 0x10 */
-
-        int32_t INTC_reserverd_2;       /* IACKR_PRC1 - INTC Interrupt Acknowledge Register for Processor 1 (IACKR_PRC1) <URM>INTC_IACKR_PRC1</URM> @baseaddress + 0x14 */
-
-        union {
-            vuint32_t R;
-        } EOIR;                 /* INTC End of Interrupt Register for Processor 0 (EOIR) <URM>INTC_EOIR_PRC0</URM> @baseaddress + 0x18 */
-
-        int32_t INTC_reserverd_3;       /* EOIR_PRC1 -  INTC End of Interrupt Register for Processor 1 (EOIR_PRC1) <URM>INTC_EOIR_PRC1</URM> @baseaddress + 0x1C */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:6;     /* Reserved */
-                vuint8_t SET:1; /* Set Flag bits */
-                vuint8_t CLR:1; /* Clear Flag bits */
-            } B;
-        } SSCIR[8];             /* INTC Software Set/Clear Interrupt Registers (SSCIR) <URM>INTC_SSCIRn</URM> @baseaddress + 0x20 */
-
-        int32_t INTC_reserverd_32[6];
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t PRC_SEL:2;     /* Processor Select (new in MPC563xM) */
-                  vuint8_t:2;   /* Reserved */
-                vuint8_t PRI:4; /* Priority Select */
-            } B;
-        } PSR[512];             /* INTC Priority Select Registers (PSR) <URM>INTC_PSR</URM> @baseaddress + 0x40 */
-
-    };                          /* end of INTC_tag */
-/****************************************************************************/
-/*                          MODULE : EQADC                                  */
-/****************************************************************************/
-    struct EQADC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t ICEA0:1;
-                vuint32_t ICEA1:1;
-                  vuint32_t:1;
-                vuint32_t ESSIE:2;
-                  vuint32_t:1;
-                vuint32_t DBG:2;
-            } B;
-        } MCR;                  /* Module Configuration Register <URM>EQADC_MCR</URM> */
-
-        int32_t EQADC_reserved00;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:6;
-                vuint32_t NMF:26;
-            } B;
-        } NMSFR;                /* Null Message Send Format Register <URM>EQADC_NMSFR</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t DFL:4;
-            } B;
-        } ETDFR;                /* External Trigger Digital Filter Register  <URM>EQADC_ETDFR</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFPUSH:32;    /* <URM>CF_PUSH</URM> */
-            } B;
-        } CFPR[6];              /* CFIFO Push Registers <URM>EQADC_CFPR</URM> */
-
-        uint32_t eqadc_reserved1;
-
-        uint32_t eqadc_reserved2;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RFPOP:16;     /* <URM>RF_POP</URM> */
-            } B;
-        } RFPR[6];              /* Result FIFO Pop Registers <URM>EQADC_RFPR</URM> */
-
-        uint32_t eqadc_reserved3;
-
-        uint32_t eqadc_reserved4;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t CFEE0:1;
-                vuint16_t STRME0:1;
-                vuint16_t SSE:1;
-                vuint16_t CFINV:1;
-                  vuint16_t:1;
-                vuint16_t MODE:4;
-                vuint16_t AMODE0:4;     /* CFIFO0 only */
-            } B;
-        } CFCR[6];              /* CFIFO Control Registers <URM>EQADC_CFCR</URM> */
-
-        uint32_t eqadc_reserved5;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t NCIE:1;
-                vuint16_t TORIE:1;
-                vuint16_t PIE:1;
-                vuint16_t EOQIE:1;
-                vuint16_t CFUIE:1;
-                  vuint16_t:1;
-                vuint16_t CFFE:1;
-                vuint16_t CFFS:1;
-                  vuint16_t:4;
-                vuint16_t RFOIE:1;
-                  vuint16_t:1;
-                vuint16_t RFDE:1;
-                vuint16_t RFDS:1;
-            } B;
-        } IDCR[6];              /* Interrupt and DMA Control Registers <URM>EQADC_IDCR</URM> */
-
-        uint32_t eqadc_reserved6;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NCF:1;
-                vuint32_t TORF:1;
-                vuint32_t PF:1;
-                vuint32_t EOQF:1;
-                vuint32_t CFUF:1;
-                vuint32_t SSS:1;
-                vuint32_t CFFF:1;
-                  vuint32_t:5;
-                vuint32_t RFOF:1;
-                  vuint32_t:1;
-                vuint32_t RFDF:1;
-                  vuint32_t:1;
-                vuint32_t CFCTR:4;
-                vuint32_t TNXTPTR:4;
-                vuint32_t RFCTR:4;
-                vuint32_t POPNXTPTR:4;
-            } B;
-        } FISR[6];              /* FIFO and Interrupt Status Registers <URM>EQADC_FISR</URM> */
-
-        uint32_t eqadc_reserved7;
-
-        uint32_t eqadc_reserved8;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t TCCF:11;      /* <URM>TC_CF</URM> */
-            } B;
-        } CFTCR[6];             /* CFIFO Transfer Counter Registers <URM>EQADC_CFTCR</URM> */
-
-        uint32_t eqadc_reserved9;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFS0:2;       /* <URM>CFS0_TCB0</URM> */
-                vuint32_t CFS1:2;       /* <URM>CFS1_TCB0</URM> */
-                vuint32_t CFS2:2;       /* <URM>CFS2_TCB0</URM> */
-                vuint32_t CFS3:2;       /* <URM>CFS3_TCB0</URM> */
-                vuint32_t CFS4:2;       /* <URM>CFS4_TCB0</URM> */
-                vuint32_t CFS5:2;       /* <URM>CFS5_TCB0</URM> */
-                  vuint32_t:5;
-                vuint32_t LCFTCB0:4;
-                vuint32_t TC_LCFTCB0:11;
-            } B;
-        } CFSSR0;               /* CFIFO Status Register 0 <URM>EQADC_CFSSR0</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFS0:2;       /* <URM>CFS0_TCB1</URM> */
-                vuint32_t CFS1:2;       /* <URM>CFS1_TCB1</URM> */
-                vuint32_t CFS2:2;       /* <URM>CFS2_TCB1</URM> */
-                vuint32_t CFS3:2;       /* <URM>CFS3_TCB1</URM> */
-                vuint32_t CFS4:2;       /* <URM>CFS4_TCB1</URM> */
-                vuint32_t CFS5:2;       /* <URM>CFS5_TCB1</URM> */
-                  vuint32_t:5;
-                vuint32_t LCFTCB1:4;
-                vuint32_t TC_LCFTCB1:11;
-            } B;
-        } CFSSR1;               /* CFIFO Status Register 1 <URM>EQADC_CFSSR1</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFS0:2;       /* <URM>CFS0_TSSI</URM> */
-                vuint32_t CFS1:2;       /* <URM>CFS1_TSSI</URM> */
-                vuint32_t CFS2:2;       /* <URM>CFS2_TSSI</URM> */
-                vuint32_t CFS3:2;       /* <URM>CFS3_TSSI</URM> */
-                vuint32_t CFS4:2;       /* <URM>CFS4_TSSI</URM> */
-                vuint32_t CFS5:2;       /* <URM>CFS5_TSSI</URM> */
-                  vuint32_t:4;
-                vuint32_t ECBNI:1;
-                vuint32_t LCFTSSI:4;
-                vuint32_t TC_LCFTSSI:11;
-            } B;
-        } CFSSR2;               /* CFIFO Status Register 2 <URM>EQADC_CFSSR2</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFS0:2;
-                vuint32_t CFS1:2;
-                vuint32_t CFS2:2;
-                vuint32_t CFS3:2;
-                vuint32_t CFS4:2;
-                vuint32_t CFS5:2;
-                  vuint32_t:20;
-            } B;
-        } CFSR;                 /* <URM>EQADC_CFSR</URM> */
-
-        uint32_t eqadc_reserved11;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:21;
-                vuint32_t MDT:3;
-                  vuint32_t:4;
-                vuint32_t BR:4;
-            } B;
-        } SSICR;                /* SSI Control Register <URM>EQADC_SSICR</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RDV:1;
-                  vuint32_t:5;
-                vuint32_t RDATA:26;
-            } B;
-        } SSIRDR;               /* SSI Recieve Data Register <URM>EQADC_SSIRDR</URM> @ baseaddress + 0xB8 */
-
-        uint32_t eqadc_reserved11b[5];
-
-        uint32_t eqadc_reserved15;      /* EQADC Red Line Client Configuration Register @ baseaddress + 0xD0  */
-        /* REDLCCR is not implemented in the MPC563xM */
-
-        uint32_t eqadc_reserved12[11];
-
-        struct {
-            union {
-                vuint32_t R;
-
-                /*<URM>B.CFIFOx_DATAw</URM> */
-
-            } R[4];             /*<URM>EQADC_CFxRw<URM> */
-
-            union {
-                vuint32_t R;
-                /*<URM>B.CFIFOx_EDATAw</URM> */
-            } EDATA[4];         /*<URM>EQADC_CFxERw</URM> (new in MPC563xM) */
-
-            uint32_t eqadc_reserved13[8];
-
-        } CF[6];
-
-        uint32_t eqadc_reserved14[32];
-
-        struct {
-            union {
-                vuint32_t R;
-                /*<URM>RFIFOx_DATAw</URM> */
-            } R[4];             /*<URM>EQADC_RFxRw</URM> */
-
-            uint32_t eqadc_reserved15[12];
-
-        } RF[6];
-
-    };
-    /****************************************************************************/
-/*                          MODULE : DSPI                                   */
-/****************************************************************************/
-    struct DSPI_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MSTR:1;
-                vuint32_t CONT_SCKE:1;
-                vuint32_t DCONF:2;
-                vuint32_t FRZ:1;
-                vuint32_t MTFE:1;
-                vuint32_t PCSSE:1;
-                vuint32_t ROOE:1;
-                vuint32_t PCSIS7:1;     /* new in MPC563xM */
-                vuint32_t PCSIS6:1;     /* new in MPC563xM */
-                vuint32_t PCSIS5:1;
-                vuint32_t PCSIS4:1;
-                vuint32_t PCSIS3:1;
-                vuint32_t PCSIS2:1;
-                vuint32_t PCSIS1:1;
-                vuint32_t PCSIS0:1;
-                vuint32_t DOZE:1;
-                vuint32_t MDIS:1;
-                vuint32_t DIS_TXF:1;
-                vuint32_t DIS_RXF:1;
-                vuint32_t CLR_TXF:1;
-                vuint32_t CLR_RXF:1;
-                vuint32_t SMPL_PT:2;
-                  vuint32_t:7;
-                vuint32_t HALT:1;
-            } B;
-        } MCR;                  /* Module Configuration Register <URM>DSPI_MCR</URM> @baseaddress + 0x00 */
-
-        uint32_t dspi_reserved1;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCNT:16;      /* <URM>SPI_TCNT</URM> */
-                  vuint32_t:16;
-            } B;
-        } TCR;                  /* DSPI Transfer Count Register  <URM>DSPI_TCR</URM> @baseaddress + 0x08 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DBR:1;
-                vuint32_t FMSZ:4;
-                vuint32_t CPOL:1;
-                vuint32_t CPHA:1;
-                vuint32_t LSBFE:1;
-                vuint32_t PCSSCK:2;
-                vuint32_t PASC:2;
-                vuint32_t PDT:2;
-                vuint32_t PBR:2;
-                vuint32_t CSSCK:4;
-                vuint32_t ASC:4;
-                vuint32_t DT:4;
-                vuint32_t BR:4;
-            } B;
-        } CTAR[8];              /* Clock and Transfer Attributes Registers <URM>DSPI_CTARx</URM> @baseaddress + 0x0C - 0x28 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCF:1;
-                vuint32_t TXRXS:1;
-                  vuint32_t:1;
-                vuint32_t EOQF:1;
-                vuint32_t TFUF:1;
-                  vuint32_t:1;
-                vuint32_t TFFF:1;
-                  vuint32_t:5;
-                vuint32_t RFOF:1;
-                  vuint32_t:1;
-                vuint32_t RFDF:1;
-                  vuint32_t:1;
-                vuint32_t TXCTR:4;
-                vuint32_t TXNXTPTR:4;
-                vuint32_t RXCTR:4;
-                vuint32_t POPNXTPTR:4;
-            } B;
-        } SR;                   /* Status Register <URM>DSPI_SR</URM> @baseaddress + 0x2C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCFRE:1;      /*<URM>TCF_RE</URM> */
-                  vuint32_t:2;
-                vuint32_t EOQFRE:1;     /*<URM>EQQF_RE</URM> */
-                vuint32_t TFUFRE:1;     /*<URM>TFUF_RE</URM> */
-                  vuint32_t:1;
-                vuint32_t TFFFRE:1;     /*<URM>TFFF_RE</URM> */
-                vuint32_t TFFFDIRS:1;   /*<URM>TFFF_DIRS</URM> */
-                  vuint32_t:4;
-                vuint32_t RFOFRE:1;     /*<URM>RFOF_RE</URM> */
-                  vuint32_t:1;
-                vuint32_t RFDFRE:1;     /*<URM>RFDF_RE</URM> */
-                vuint32_t RFDFDIRS:1;   /*<URM>RFDF_DIRS</URM> */
-                  vuint32_t:16;
-            } B;
-        } RSER;                 /* DMA/Interrupt Request Select and Enable Register <URM>DSPI_RSER</URM> @baseaddress + 0x30 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CONT:1;
-                vuint32_t CTAS:3;
-                vuint32_t EOQ:1;
-                vuint32_t CTCNT:1;
-                  vuint32_t:2;
-                vuint32_t PCS7:1;       /* new in MPC563xM */
-                vuint32_t PCS6:1;       /* new in MPC563xM */
-                vuint32_t PCS5:1;
-                vuint32_t PCS4:1;
-                vuint32_t PCS3:1;
-                vuint32_t PCS2:1;
-                vuint32_t PCS1:1;
-                vuint32_t PCS0:1;
-                vuint32_t TXDATA:16;
-            } B;
-        } PUSHR;                /* PUSH TX FIFO Register <URM>DSPI_PUSHR</URM> @baseaddress + 0x34 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXDATA:16;
-            } B;
-        } POPR;                 /* POP RX FIFO Register <URM>DSPI_POPR</URM> @baseaddress + 0x38 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TXCMD:16;
-                vuint32_t TXDATA:16;
-            } B;
-        } TXFR[4];              /* Transmit FIFO Registers <URM>DSPI_TXFRx</URM> @baseaddress + 0x3c - 0x78 */
-
-        vuint32_t DSPI_reserved_txf[12];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXDATA:16;
-            } B;
-        } RXFR[4];              /* Transmit FIFO Registers <URM>DSPI_RXFRx</URM> @baseaddress + 0x7c - 0xB8 */
-
-        vuint32_t DSPI_reserved_rxf[12];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MTOE:1;
-                  vuint32_t:1;
-                vuint32_t MTOCNT:6;
-                  vuint32_t:3;
-                vuint32_t TSBC:1;
-                vuint32_t TXSS:1;
-                vuint32_t TPOL:1;
-                vuint32_t TRRE:1;
-                vuint32_t CID:1;
-                vuint32_t DCONT:1;
-                vuint32_t DSICTAS:3;
-                  vuint32_t:4;
-                vuint32_t DPCS7:1;
-                vuint32_t DPCS6:1;
-                vuint32_t DPCS5:1;
-                vuint32_t DPCS4:1;
-                vuint32_t DPCS3:1;
-                vuint32_t DPCS2:1;
-                vuint32_t DPCS1:1;
-                vuint32_t DPCS0:1;
-            } B;
-        } DSICR;                /* DSI Configuration Register <URM>DSPI_DSICR</URM> @baseaddress + 0xBC */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SER_DATA:32;  /* 32bit instead of 16 in MPC563xM */
-            } B;
-        } SDR;                  /* DSI Serialization Data Register <URM>DSPI_SDR</URM> @baseaddress + 0xC0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ASER_DATA:32; /* 32bit instead of 16 in MPC563xM */
-            } B;
-        } ASDR;                 /* DSI Alternate Serialization Data Register <URM>DSPI_ASDR</URM> @baseaddress + 0xC4 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t COMP_DATA:32; /* 32bit instead of 16 in MPC563xM */
-            } B;
-        } COMPR;                /* DSI Transmit Comparison Register <URM>DSPI_COMPR</URM> @baseaddress + 0xC8 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DESER_DATA:32;        /* 32bit instead of 16 in MPC563xM */
-            } B;
-        } DDR;                  /* DSI deserialization Data Register <URM>DSPI_DDR</URM> @baseaddress + 0xCC */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t TSBCNT:5;
-                  vuint32_t:16;
-                vuint32_t DPCS1_7:1;
-                vuint32_t DPCS1_6:1;
-                vuint32_t DPCS1_5:1;
-                vuint32_t DPCS1_4:1;
-                vuint32_t DPCS1_3:1;
-                vuint32_t DPCS1_2:1;
-                vuint32_t DPCS1_1:1;
-                vuint32_t DPCS1_0:1;
-            } B;
-        } DSICR1;               /* DSI Configuration Register 1 <URM>DSPI_DSICR1</URM> @baseaddress + 0xD0 */
-
-    };
-/****************************************************************************/
-/*                          MODULE : eSCI                                   */
-/****************************************************************************/
-    struct ESCI_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t SBR:13;
-                vuint32_t LOOPS:1;
-                  vuint32_t:1;  /* Reserved in MPC563xM */
-                vuint32_t RSRC:1;
-                vuint32_t M:1;
-                vuint32_t WAKE:1;
-                vuint32_t ILT:1;
-                vuint32_t PE:1;
-                vuint32_t PT:1;
-                vuint32_t TIE:1;
-                vuint32_t TCIE:1;
-                vuint32_t RIE:1;
-                vuint32_t ILIE:1;
-                vuint32_t TE:1;
-                vuint32_t RE:1;
-                vuint32_t RWU:1;
-                vuint32_t SBK:1;
-            } B;
-        } CR1;                  /* Control Register 1 <URM>SCIBDH, SCIBDL, SCICR1, SCICR2</URM> @baseaddress + 0x00 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t MDIS:1;
-                vuint16_t FBR:1;
-                vuint16_t BSTP:1;
-                vuint16_t IEBERR:1;     /* <URM>BERIE</URM> */
-                vuint16_t RXDMA:1;
-                vuint16_t TXDMA:1;
-                vuint16_t BRK13:1;      /* <URM>BRCL</URM> */
-                vuint16_t TXDIR:1;
-                vuint16_t BESM13:1;     /* <URM>BESM</URM> */
-                vuint16_t SBSTP:1;      /* <URM>BESTP</URM> */
-                vuint16_t RXPOL:1;
-                vuint16_t PMSK:1;
-                vuint16_t ORIE:1;
-                vuint16_t NFIE:1;
-                vuint16_t FEIE:1;
-                vuint16_t PFIE:1;
-            } B;
-        } CR2;                  /* Control Register 2 <URM>SCICR3, SCICR4</URM>  @baseaddress + 0x04 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t R8:1; /* <URM>RN</URM> */
-                vuint16_t T8:1; /* <URM>TN</URM> */
-                vuint16_t ERR:1;
-                  vuint16_t:1;
-                vuint16_t R:4;
-                vuint8_t D;
-            } B;
-        } DR;                   /* Data Register <URM>SCIDRH, SCIDRL</URM>  @baseaddress + 0x06 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TDRE:1;
-                vuint32_t TC:1;
-                vuint32_t RDRF:1;
-                vuint32_t IDLE:1;
-                vuint32_t OR:1;
-                vuint32_t NF:1;
-                vuint32_t FE:1;
-                vuint32_t PF:1;
-                  vuint32_t:3;
-                vuint32_t BERR:1;
-                  vuint32_t:2;
-                vuint32_t TACT:1;
-                vuint32_t RAF:1;        /* <URM>RACT</URM> */
-                vuint32_t RXRDY:1;
-                vuint32_t TXRDY:1;
-                vuint32_t LWAKE:1;
-                vuint32_t STO:1;
-                vuint32_t PBERR:1;
-                vuint32_t CERR:1;
-                vuint32_t CKERR:1;
-                vuint32_t FRC:1;
-                  vuint32_t:6;
-                vuint32_t UREQ:1;
-                vuint32_t OVFL:1;
-            } B;
-        } SR;                   /* Status Register <URM>SCISR1, SCIRSR2, LINSTAT1, LINSTAT2 </URM>  @baseaddress + 0x08 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t LRES:1;
-                vuint32_t WU:1;
-                vuint32_t WUD0:1;
-                vuint32_t WUD1:1;
-                  vuint32_t:2;  /* reserved: LDBG and DSF not longer supported */
-                vuint32_t PRTY:1;
-                vuint32_t LIN:1;
-                vuint32_t RXIE:1;
-                vuint32_t TXIE:1;
-                vuint32_t WUIE:1;
-                vuint32_t STIE:1;
-                vuint32_t PBIE:1;
-                vuint32_t CIE:1;
-                vuint32_t CKIE:1;
-                vuint32_t FCIE:1;
-                  vuint32_t:6;
-                vuint32_t UQIE:1;
-                vuint32_t OFIE:1;
-                  vuint32_t:8;
-            } B;
-        } LCR;                  /* LIN Control Register <URM>LINCTRL1, LINCTRL2, LINCTRL3 </URM>  @baseaddress + 0x0C  */
-
-        union {
-            vuint32_t R;
-        } LTR;                  /* LIN Transmit Register <URM>LINTX</URM>  @baseaddress + 0x10 */
-
-        union {
-            vuint32_t R;
-        } LRR;                  /* LIN Recieve Register <URM>LINRX</URM>  @baseaddress + 0x14 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t P:16;
-                  vuint32_t:3;
-                vuint32_t SYNM:1;
-                vuint32_t EROE:1;
-                vuint32_t ERFE:1;
-                vuint32_t ERPE:1;
-                vuint32_t M2:1;
-                  vuint32_t:8;
-            } B;
-        } LPR;                  /* LIN CRC Polynom Register  <URM>LINCRCP1, LINCRCP2, SCICR5</URM>  @baseaddress + 0x18 */
-
-    };
-/****************************************************************************/
-/*                          MODULE : eSCI                                   */
-/****************************************************************************/
-    struct ESCI_12_13_bit_tag {
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t R8:1;
-                vuint16_t T8:1;
-                vuint16_t ERR:1;
-                  vuint16_t:1;
-                vuint16_t D:12;
-            } B;
-        } DR;                   /* Data Register */
-    };
-/****************************************************************************/
-/*                          MODULE : FlexCAN                                */
-/****************************************************************************/
-    struct FLEXCAN_BUF_t {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t CODE:4;
-                  vuint32_t:1;
-                vuint32_t SRR:1;
-                vuint32_t IDE:1;
-                vuint32_t RTR:1;
-                vuint32_t LENGTH:4;
-                vuint32_t TIMESTAMP:16;
-            } B;
-        } CS;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRIO:3;
-                vuint32_t STD_ID:11;
-                vuint32_t EXT_ID:18;
-            } B;
-        } ID;
-
-        union {
-            /*vuint8_t  B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */
-            /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */
-            vuint32_t W[2];     /* Data buffer in words (32 bits) */
-            /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */
-        } DATA;
-
-    };                          /* end of FLEXCAN_BUF_t */
-
-    struct FLEXCAN_RXFIFO_t {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:9;
-                vuint32_t SRR:1;
-                vuint32_t IDE:1;
-                vuint32_t RTR:1;
-                vuint32_t LENGTH:4;
-                vuint32_t TIMESTAMP:16;
-            } B;
-        } CS;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t STD_ID:11;
-                vuint32_t EXT_ID:18;
-            } B;
-        } ID;
-
-        union {
-            /*vuint8_t  B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */
-            /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */
-            vuint32_t W[2];     /* Data buffer in words (32 bits) */
-            /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */
-        } DATA;
-
-        uint32_t FLEXCAN_RXFIFO_reserved[20];   /* {0x00E0-0x0090}/0x4 = 0x14 */
-
-        union {
-            vuint32_t R;
-        } IDTABLE[8];
-
-    };                          /* end of FLEXCAN_RXFIFO_t */
-
-    struct FLEXCAN2_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-                vuint32_t FEN:1;        /* new in MPC563xM */
-                vuint32_t HALT:1;
-                vuint32_t NOTRDY:1;     /* <URM>NOT_RDY</URM> */
-                vuint32_t WAK_MSK:1;    /* new in MPC563xM */
-                vuint32_t SOFTRST:1;    /* <URM>SOFT_RST</URM> */
-                vuint32_t FRZACK:1;     /* <URM>FRZ_ACK</URM> */
-                vuint32_t SUPV:1;       /* new in MPC563xM */
-                vuint32_t SLF_WAK:1;    /* new in MPC563xM */
-
-                vuint32_t WRNEN:1;      /* <URM>WRN_EN</URM> */
-
-                vuint32_t MDISACK:1;    /* <URM>LPM_ACK</URM> */
-                vuint32_t WAK_SRC:1;    /* new in MPC563xM */
-                vuint32_t DOZE:1;       /* new in MPC563xM */
-
-                vuint32_t SRXDIS:1;     /* <URM>SRX_DIS</URM> */
-                vuint32_t MBFEN:1;      /* <URM>BCC</URM> */
-                  vuint32_t:2;
-
-                vuint32_t LPRIO_EN:1;   /* new in MPC563xM */
-                vuint32_t AEN:1;        /* new in MPC563xM */
-                  vuint32_t:2;
-                vuint32_t IDAM:2;       /* new in MPC563xM */
-                  vuint32_t:2;
-
-                vuint32_t MAXMB:6;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRESDIV:8;
-                vuint32_t RJW:2;
-                vuint32_t PSEG1:3;
-                vuint32_t PSEG2:3;
-                vuint32_t BOFFMSK:1;    /* <URM>BOFF_MSK</URM> */
-                vuint32_t ERRMSK:1;     /* <URM>ERR_MSK</URM> */
-                vuint32_t CLKSRC:1;     /* <URM>CLK_SRC</URM> */
-                vuint32_t LPB:1;
-                vuint32_t TWRNMSK:1;    /* <URM>TWRN_MSK</URM> */
-                vuint32_t RWRNMSK:1;    /* <URM>RWRN_MSK</URM> */
-                  vuint32_t:2;
-                vuint32_t SMP:1;
-                vuint32_t BOFFREC:1;    /* <URM>BOFF_REC</URM> */
-                vuint32_t TSYN:1;
-                vuint32_t LBUF:1;
-                vuint32_t LOM:1;
-                vuint32_t PROPSEG:3;
-            } B;                /* Control Register */
-        } CR;                   /* <URM>CTRL</URM> */
-
-        union {
-            vuint32_t R;
-        } TIMER;                /* Free Running Timer */
-
-        int32_t FLEXCAN_reserved00;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t MI:29;
-            } B;
-        } RXGMASK;              /* RX Global Mask */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t MI:29;
-            } B;
-        } RX14MASK;             /* RX 14 Mask */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t MI:29;
-            } B;
-        } RX15MASK;             /* RX 15 Mask */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXECNT:8;
-                vuint32_t TXECNT:8;
-            } B;
-        } ECR;                  /* Error Counter Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t TWRNINT:1;    /* <URM>TWRN_INT</URM> */
-                vuint32_t RWRNINT:1;    /* <URM>RWRN_INT</URM> */
-                vuint32_t BIT1ERR:1;    /* <URM>BIT1_ERR</URM> */
-                vuint32_t BIT0ERR:1;    /* <URM>BIT0_ERR</URM> */
-                vuint32_t ACKERR:1;     /* <URM>ACK_ERR</URM> */
-                vuint32_t CRCERR:1;     /* <URM>CRC_ERR</URM> */
-                vuint32_t FRMERR:1;     /* <URM>FRM_ERR</URM> */
-                vuint32_t STFERR:1;     /* <URM>STF_ERR</URM> */
-                vuint32_t TXWRN:1;      /* <URM>TX_WRN</URM> */
-                vuint32_t RXWRN:1;      /* <URM>RX_WRN</URM> */
-                vuint32_t IDLE:1;
-                vuint32_t TXRX:1;
-                vuint32_t FLTCONF:2;    /* <URM>FLT_CONF</URM> */
-                  vuint32_t:1;
-                vuint32_t BOFFINT:1;    /* <URM>BOFF_INT</URM> */
-                vuint32_t ERRINT:1;     /* <URM>ERR_INT</URM> */
-                vuint32_t WAK_INT:1;    /* new in MPC563xM */
-            } B;
-        } ESR;                  /* Error and Status Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF63M:1;
-                vuint32_t BUF62M:1;
-                vuint32_t BUF61M:1;
-                vuint32_t BUF60M:1;
-                vuint32_t BUF59M:1;
-                vuint32_t BUF58M:1;
-                vuint32_t BUF57M:1;
-                vuint32_t BUF56M:1;
-                vuint32_t BUF55M:1;
-                vuint32_t BUF54M:1;
-                vuint32_t BUF53M:1;
-                vuint32_t BUF52M:1;
-                vuint32_t BUF51M:1;
-                vuint32_t BUF50M:1;
-                vuint32_t BUF49M:1;
-                vuint32_t BUF48M:1;
-                vuint32_t BUF47M:1;
-                vuint32_t BUF46M:1;
-                vuint32_t BUF45M:1;
-                vuint32_t BUF44M:1;
-                vuint32_t BUF43M:1;
-                vuint32_t BUF42M:1;
-                vuint32_t BUF41M:1;
-                vuint32_t BUF40M:1;
-                vuint32_t BUF39M:1;
-                vuint32_t BUF38M:1;
-                vuint32_t BUF37M:1;
-                vuint32_t BUF36M:1;
-                vuint32_t BUF35M:1;
-                vuint32_t BUF34M:1;
-                vuint32_t BUF33M:1;
-                vuint32_t BUF32M:1;
-            } B;                /* Interruput Masks Register */
-        } IMRH;                 /* <URM>IMASK2</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF31M:1;
-                vuint32_t BUF30M:1;
-                vuint32_t BUF29M:1;
-                vuint32_t BUF28M:1;
-                vuint32_t BUF27M:1;
-                vuint32_t BUF26M:1;
-                vuint32_t BUF25M:1;
-                vuint32_t BUF24M:1;
-                vuint32_t BUF23M:1;
-                vuint32_t BUF22M:1;
-                vuint32_t BUF21M:1;
-                vuint32_t BUF20M:1;
-                vuint32_t BUF19M:1;
-                vuint32_t BUF18M:1;
-                vuint32_t BUF17M:1;
-                vuint32_t BUF16M:1;
-                vuint32_t BUF15M:1;
-                vuint32_t BUF14M:1;
-                vuint32_t BUF13M:1;
-                vuint32_t BUF12M:1;
-                vuint32_t BUF11M:1;
-                vuint32_t BUF10M:1;
-                vuint32_t BUF09M:1;
-                vuint32_t BUF08M:1;
-                vuint32_t BUF07M:1;
-                vuint32_t BUF06M:1;
-                vuint32_t BUF05M:1;
-                vuint32_t BUF04M:1;
-                vuint32_t BUF03M:1;
-                vuint32_t BUF02M:1;
-                vuint32_t BUF01M:1;
-                vuint32_t BUF00M:1;
-            } B;                /* Interruput Masks Register */
-        } IMRL;                 /* <URM>IMASK1</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF63I:1;
-                vuint32_t BUF62I:1;
-                vuint32_t BUF61I:1;
-                vuint32_t BUF60I:1;
-                vuint32_t BUF59I:1;
-                vuint32_t BUF58I:1;
-                vuint32_t BUF57I:1;
-                vuint32_t BUF56I:1;
-                vuint32_t BUF55I:1;
-                vuint32_t BUF54I:1;
-                vuint32_t BUF53I:1;
-                vuint32_t BUF52I:1;
-                vuint32_t BUF51I:1;
-                vuint32_t BUF50I:1;
-                vuint32_t BUF49I:1;
-                vuint32_t BUF48I:1;
-                vuint32_t BUF47I:1;
-                vuint32_t BUF46I:1;
-                vuint32_t BUF45I:1;
-                vuint32_t BUF44I:1;
-                vuint32_t BUF43I:1;
-                vuint32_t BUF42I:1;
-                vuint32_t BUF41I:1;
-                vuint32_t BUF40I:1;
-                vuint32_t BUF39I:1;
-                vuint32_t BUF38I:1;
-                vuint32_t BUF37I:1;
-                vuint32_t BUF36I:1;
-                vuint32_t BUF35I:1;
-                vuint32_t BUF34I:1;
-                vuint32_t BUF33I:1;
-                vuint32_t BUF32I:1;
-            } B;                /* Interruput Flag Register */
-        } IFRH;                 /* <URM>IFLAG2</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF31I:1;
-                vuint32_t BUF30I:1;
-                vuint32_t BUF29I:1;
-                vuint32_t BUF28I:1;
-                vuint32_t BUF27I:1;
-                vuint32_t BUF26I:1;
-                vuint32_t BUF25I:1;
-                vuint32_t BUF24I:1;
-                vuint32_t BUF23I:1;
-                vuint32_t BUF22I:1;
-                vuint32_t BUF21I:1;
-                vuint32_t BUF20I:1;
-                vuint32_t BUF19I:1;
-                vuint32_t BUF18I:1;
-                vuint32_t BUF17I:1;
-                vuint32_t BUF16I:1;
-                vuint32_t BUF15I:1;
-                vuint32_t BUF14I:1;
-                vuint32_t BUF13I:1;
-                vuint32_t BUF12I:1;
-                vuint32_t BUF11I:1;
-                vuint32_t BUF10I:1;
-                vuint32_t BUF09I:1;
-                vuint32_t BUF08I:1;
-                vuint32_t BUF07I:1;
-                vuint32_t BUF06I:1;
-                vuint32_t BUF05I:1;
-                vuint32_t BUF04I:1;
-                vuint32_t BUF03I:1;
-                vuint32_t BUF02I:1;
-                vuint32_t BUF01I:1;
-                vuint32_t BUF00I:1;
-            } B;                /* Interruput Flag Register */
-        } IFRL;                 /* <URM>IFLAG1</URM> */
-
-        uint32_t flexcan2_reserved2[19];
-
-/****************************************************************************/
-/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure     */
-/****************************************************************************/
-        /* Standard Buffer Structure */
-        struct FLEXCAN_BUF_t BUF[64];
-
-        /* RX FIFO and Buffer Structure *//* New options in MPC563xM */
-        /*struct FLEXCAN_RXFIFO_t RXFIFO; */
-        /*struct FLEXCAN_BUF_t BUF[56];   */
-/****************************************************************************/
-
-        uint32_t FLEXCAN_reserved3[256];        /* {0x0880-0x0480}/0x4 = 0x100 *//* (New in MPC563xM) Address Base + 0x0034 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;                /* RX Individual Mask Registers */
-        } RXIMR[64];            /* (New in MPC563xM) Address Base + 0x0880 */
-
-    };                          /* end of FLEXCAN_tag */
-/****************************************************************************/
-/*                     MODULE : Decimation Filter (DECFIL)                  */
-/****************************************************************************/
-    struct DECFIL_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MDIS:1;
-                vuint32_t FREN:1;
-                  vuint32_t:1;
-                vuint32_t FRZ:1;
-                vuint32_t SRES:1;
-                  vuint32_t:2;  /* CASCD not supported in MPC563xM */
-                vuint32_t IDEN:1;
-                vuint32_t ODEN:1;
-                vuint32_t ERREN:1;
-                  vuint32_t:1;
-                vuint32_t FTYPE:2;
-                  vuint32_t:1;
-                vuint32_t SCAL:2;
-                  vuint32_t:1;
-                vuint32_t SAT:1;
-                vuint32_t ISEL:1;
-                  vuint32_t:1;  /* MIXM does not appear to be implemented on the MPC563xM */
-                vuint32_t DEC_RATE:4;
-                  vuint32_t:1;  /* SDIE not supported in MPC563xM */
-                vuint32_t DSEL:1;
-                vuint32_t IBIE:1;
-                vuint32_t OBIE:1;
-                vuint32_t EDME:1;
-                vuint32_t TORE:1;
-                vuint32_t TMODE:2;      /* the LSB of TMODE is always 0 on the MPC563xM */
-            } B;
-        } MCR;                  /* Configuration Register <URM>DECFILTER_MCR</URM> @baseaddress + 0x00 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BSY:1;
-                  vuint32_t:1;
-                vuint32_t DEC_COUNTER:4;
-                vuint32_t IDFC:1;
-                vuint32_t ODFC:1;
-                vuint32_t SDFC:1;       /* SDFC not supported in MPC563xM */
-                vuint32_t IBIC:1;
-                vuint32_t OBIC:1;
-                vuint32_t SVRC:1;       /* SVRC not supported in MPC563xM */
-                vuint32_t DIVRC:1;
-                vuint32_t OVFC:1;
-                vuint32_t OVRC:1;
-                vuint32_t IVRC:1;
-                  vuint32_t:6;
-                vuint32_t IDF:1;
-                vuint32_t ODF:1;
-                vuint32_t SDF:1;        /* SDF not supported in MPC563xM */
-                vuint32_t IBIF:1;
-                vuint32_t OBIF:1;
-                vuint32_t SVR:1;        /* SVR not supported in MPC563xM */
-                vuint32_t DIVR:1;
-                vuint32_t OVF:1;
-                vuint32_t OVR:1;
-                vuint32_t IVR:1;
-            } B;
-        } MSR;                  /* Status Register <URM>DECFILTER_MSR</URM> @baseaddress + 0x04 */
-
-        /* Module Extended Config.Register - not siupported on the MPC563xM <URM>DECFILTER_MXCR</URM> @baseaddress + 0x08  */
-
-        uint32_t decfil_reserved1[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t INTAG:4;
-                  vuint32_t:6;
-                vuint32_t PREFILL:1;
-                vuint32_t FLUSH:1;
-                vuint32_t INPBUF:16;
-            } B;
-        } IB;                   /* Interface Input Buffer <URM>DECFILTER_IB</URM> @baseaddress + 0x10  */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t OUTTAG:4;
-                vuint32_t OUTBUF:16;
-            } B;
-        } OB;                   /* Interface Output Buffer <URM>DECFILTER_OB</URM> @baseaddress + 0x14  */
-
-        uint32_t decfil_reserved2[2];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t COEF:24;
-            } B;
-        } COEF[9];              /* Filter Coefficient Registers <URM>DECFILTER_COEFx</URM> @baseaddress + 0x20 - 0x40  */
-
-        uint32_t decfil_reserved3[13];
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t TAP:24;
-            } B;
-        } TAP[8];               /* Filter TAP Registers <URM>DECFILTER_TAPx</URM> @baseaddress + 0x78 - 0x94 */
-
-        uint32_t decfil_reserved4[14];
-
-        /* 0x0D0 */
-        union {
-            vuint16_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t SAMP_DATA:16;
-            } B;
-        } EDID;                 /* Filter EDID Registers <URM>DECFILTER_EDID</URM> @baseaddress + 0xD0 */
-
-        uint32_t decfil_reserved5[3];
-
-        /* 0x0E0 */
-        uint32_t decfil_reserved6;
-        /* Filter FINTVAL Registers - Not supported on MPC563xM <URM>DECFILTER_FINTVAL</URM> @baseaddress + 0xE0 */
-
-        /* 0x0E4 */
-        uint32_t decfil_reserved7;
-        /* Filter FINTCNT Registers - Not supported on MPC563xM <URM>DECFILTER_FINTCNT</URM> @baseaddress + 0xE4 */
-
-        /* 0x0E8 */
-        uint32_t decfil_reserved8;
-        /* Filter CINTVAL Registers - Not supported on MPC563xM <URM>DECFILTER_CINTVAL</URM> @baseaddress + 0xE8 */
-
-        /* 0x0EC */
-        uint32_t decfil_reserved9;
-        /* Filter CINTCNT Registers - Not supported on MPC563xM <URM>DECFILTER_CINTCNT</URM> @baseaddress + 0xEC */
-
-    };
-/****************************************************************************/
-/*                     MODULE : Periodic Interval Timer (PIT)               */
-/****************************************************************************/
-    struct PIT_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:29;
-                vuint32_t MDIS_RTI:1;
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-            } B;
-        } PITMCR;               /* PIT Module Control Register */
-
-        uint32_t pit_reserved1[59];
-
-        struct {
-            union {
-                vuint32_t R;    /* <URM>TSVn</URM> */
-            } LDVAL;            /* Timer Load Value Register */
-
-            union {
-                vuint32_t R;    /* <URM>TVLn</URM> */
-            } CVAL;             /* Current Timer Value Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:30;
-                    vuint32_t TIE:1;
-                    vuint32_t TEN:1;
-                } B;
-            } TCTRL;            /* Timer Control Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:31;
-                    vuint32_t TIF:1;
-                } B;
-            } TFLG;             /* Timer Flag Register */
-        } RTI;                  /* RTI Channel */
-
-        struct {
-            union {
-                vuint32_t R;
-            } LDVAL;            /* Timer Load Value Register */
-
-            union {
-                vuint32_t R;
-            } CVAL;             /* Current Timer Value Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:30;
-                    vuint32_t TIE:1;
-                    vuint32_t TEN:1;
-                } B;
-            } TCTRL;            /* Timer Control Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:31;
-                    vuint32_t TIF:1;
-                } B;
-            } TFLG;             /* Timer Flag Register */
-        } TIMER[4];             /* Timer Channels */
-
-    };
-/****************************************************************************/
-/*                     MODULE : System Timer Module (STM)                   */
-/****************************************************************************/
-    struct STM_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t CPS:8;
-                  vuint32_t:6;
-                vuint32_t FRZ:1;
-                vuint32_t TEN:1;
-            } B;
-        } CR;                   /* STM Control Register <URM>STM_CR</URM> (new in MPC563xM) Offset 0x0000 */
-
-        union {
-            vuint32_t R;
-        } CNT;                  /* STM Count Register <URM>STM_CNT</URM> (new in MPC563xM) Offset Offset 0x0004 */
-
-        uint32_t stm_reserved1[2];      /* Reserved (new in MPC563xM) Offset Offset 0x0008 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR0;                 /* STM Channel Control Register <URM>STM_CCR0</URM> (new in MPC563xM) Offset 0x0010 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR0;                 /* STM Channel Interrupt Register <URM>STM_CIR0</URM> (new in MPC563xM) Offset 0x0014 */
-
-        union {
-            vuint32_t R;
-        } CMP0;                 /* STM Channel Compare Register <URM>STM_CMP0</URM> (new in MPC563xM) Offset Offset 0x0018 */
-
-        uint32_t stm_reserved2; /* Reserved (new in MPC563xM) Offset Offset 0x001C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR1;                 /* STM Channel Control Register <URM>STM_CCR1</URM> (new in MPC563xM) Offset 0x0020 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR1;                 /* STM Channel Interrupt Register <URM>STM_CIR1</URM> (new in MPC563xM) Offset 0x0024 */
-
-        union {
-            vuint32_t R;
-        } CMP1;                 /* STM Channel Compare Register <URM>STM_CMP1</URM> (new in MPC563xM) Offset Offset 0x0028 */
-
-        uint32_t stm_reserved3; /* Reserved (new in MPC563xM) Offset Offset 0x002C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR2;                 /* STM Channel Control Register <URM>STM_CCR2</URM> (new in MPC563xM) Offset 0x0030 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR2;                 /* STM Channel Interrupt Register <URM>STM_CIR2</URM> (new in MPC563xM) Offset 0x0034 */
-
-        union {
-            vuint32_t R;
-        } CMP2;                 /* STM Channel Compare Register <URM>STM_CMP2</URM> (new in MPC563xM) Offset Offset 0x0038 */
-
-        uint32_t stm_reserved4; /* Reserved (new in MPC563xM) Offset Offset 0x003C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR3;                 /* STM Channel Control Register <URM>STM_CCR3</URM> (new in MPC563xM) Offset 0x0040 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR3;                 /* STM Channel Interrupt Register <URM>STM_CIR3</URM> (new in MPC563xM) Offset 0x0044 */
-
-        union {
-            vuint32_t R;
-        } CMP3;                 /* STM Channel Compare Register <URM>STM_CMP3</URM> (new in MPC563xM) Offset Offset 0x0048 */
-
-        uint32_t stm_reserved5; /* Reserved (new in MPC563xM) Offset Offset 0x004C */
-    };
-
-/****************************************************************************/
-/*                     MODULE : SWT                                         */
-/****************************************************************************/
-
-    struct SWT_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MAP0:1;
-                vuint32_t MAP1:1;
-                vuint32_t MAP2:1;
-                vuint32_t MAP3:1;
-                vuint32_t MAP4:1;
-                vuint32_t MAP5:1;
-                vuint32_t MAP6:1;
-                vuint32_t MAP7:1;
-                  vuint32_t:14;
-                vuint32_t KEY:1;
-                vuint32_t RIA:1;
-                vuint32_t WND:1;
-                vuint32_t ITR:1;
-                vuint32_t HLK:1;
-                vuint32_t SLK:1;
-                vuint32_t CSL:1;
-                vuint32_t STP:1;
-                vuint32_t FRZ:1;
-                vuint32_t WEN:1;
-            } B;
-        } MCR;                  /*<URM>SWT_CR</URM> *//* Module Configuration Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t TIF:1;
-            } B;
-        } IR;                   /* Interrupt register <URM>SWT_IR</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WTO:32;
-            } B;
-        } TO;                   /* Timeout register <URM>SWT_TO</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WST:32;
-
-            } B;
-        } WN;                   /* Window register <URM>SWT_WN</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t WSC:16;
-            } B;
-        } SR;                   /* Service register <URM>SWT_SR</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CNT:32;
-            } B;
-        } CO;                   /* Counter output register <URM>SWT_CO</URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t SK:16;
-            } B;
-        } SK;                   /* Service key register <URM>SWT_SK</URM> */
-    };
-/****************************************************************************/
-/*                     MODULE : Power Management Controller (PMC)           */
-/****************************************************************************/
-    struct PMC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t LVRER:1;      /* <URM> LVIRR </URM> */
-                vuint32_t LVREH:1;      /* <URM> LVIHR </URM> */
-                vuint32_t LVRE50:1;     /* <URM> LVI5R </URM> */
-                vuint32_t LVRE33:1;     /* <URM> LVI3R </URM> */
-                vuint32_t LVREC:1;      /* <URM> LVI1R </URM> */
-                  vuint32_t:3;
-                vuint32_t LVIER:1;      /* <URM> LVIRE </URM> */
-                vuint32_t LVIEH:1;      /* <URM> LVIHE </URM> */
-                vuint32_t LVIE50:1;     /* <URM> LVI5E </URM> */
-                vuint32_t LVIE33:1;     /* <URM> LVI3E </URM> */
-                vuint32_t LVIC:1;       /* <URM> LVI1E </URM> */
-                  vuint32_t:2;
-                vuint32_t TLK:1;
-                  vuint32_t:16;
-            } B;
-        } MCR;                  /* Module Configuration register <URM> CFGR </URM> */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t LVDREGTRIM:4; /* <URM> LVI50TRIM </URM> */
-                vuint32_t VDD33TRIM:4;  /* <URM> BV33TRIM </URM> */
-                vuint32_t LVD33TRIM:4;  /* <URM> LVI33TRIM </URM> */
-                vuint32_t VDDCTRIM:4;   /* <URM> V12TRIM </URM> */
-                vuint32_t LVDCTRIM:4;   /* <URM> LVI33TRIM </URM> */
-            } B;
-        } TRIMR;                /* Trimming register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:5;
-                vuint32_t LVFVSTBY:1;
-                vuint32_t BGRDY:1;      /* <URM> BGS1 </URM> */
-                vuint32_t BGTS:1;       /* <URM> BGS2 </URM> */
-                  vuint32_t:5;
-                vuint32_t LVFCSTBY:1;
-                  vuint32_t:1;
-                vuint32_t V33DIS:1;     /* 3.3V Regulator Disable <URM> V33S </URM> */
-                vuint32_t LVFCR:1;      /* Clear LVFR <URM> LVIRC </URM> */
-                vuint32_t LVFCH:1;      /* Clear LVFH <URM> LVIHC </URM> */
-                vuint32_t LVFC50:1;     /* Clear LVF5 <URM> LVI5 </URM> */
-                vuint32_t LVFC33:1;     /* Clear LVF3 <URM> LVI3 </URM> */
-                vuint32_t LVFCC:1;      /* Clear LVFC <URM> LVI1 </URM> */
-                  vuint32_t:3;
-                vuint32_t LVFR:1;       /* Low Voltage Flag Reset Supply <URM> LVIRF </URM> */
-                vuint32_t LVFH:1;       /* Low Voltage Flag VDDEH Supply <URM> LVIHF </URM> */
-                vuint32_t LVF50:1;      /* Low Voltage Flag 5V Supply <URM> LVI5F </URM> */
-                vuint32_t LVF33:1;      /* Low Voltage Flag 3.3V Supply <URM> LVI3F </URM> */
-                vuint32_t LVFC:1;       /* Low Voltage Flag Core (1.2V) <URM> LVI1F </URM> */
-                  vuint32_t:3;
-
-            } B;
-        } SR;                   /* status register */
-    };
-/****************************************************************************/
-/*                          MODULE : TSENS (Temperature Sensor)             */
-/****************************************************************************/
-
-    struct TSENS_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TSCV2:16;
-                vuint32_t TSCV1:16;
-            } B;
-        } TCCR0;                /* Temperature Sensor Calibration B @baseaddress + 0x00 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t TSCV3:16;
-            } B;
-        } TCCR1;                /* Temperature Sensor Calibration A @baseaddress + 0x04 */
-
-        uint32_t TSENS_reserved0008[16382];     /* 0x0008-0xFFFF */
-
-    };
-     
-/* Define memories */ 
-/* Comments need to be moved for different memory sizes */ 
-     
-#define SRAM_START    0x40000000
-        /*#define SRAM_SIZE     0xC000        48K SRAM */ 
-        /*#define SRAM_SIZE     0x10000       64K SRAM */ 
-#define SRAM_SIZE     0x17800        /* 94K SRAM */
-        /*#define SRAM_END      0x4000BFFF    48K SRAM */ 
-        /*#define SRAM_END      0x4000FFFF    64K SRAM */ 
-#define SRAM_END      0x400177FF     /* 94K SRAM */
-     
-#define FLASH_START   0x0
-        /*#define FLASH_SIZE  0x100000          1M Flash */ 
-#define FLASH_SIZE    0x180000       /* 1.5M Flash */
-        /*#define FLASH_END   0xFFFFF           1M Flash */ 
-#define FLASH_END     0x17FFFF       /* 1.5M Flash */
-     
-/* Shadow Flash start and end address */ 
-#define FLASH_SHADOW_START 0x00FFC000  
-#define FLASH_SHADOW_SIZE  0x4000
-#define FLASH_SHADOW_END 0x00FFFFFF
-     
-/* Define instances of modules */ 
-#define FMPLL     (*( volatile struct FMPLL_tag *)     0xC3F80000)
-#define EBI       (*( volatile struct EBI_tag *)       0xC3F84000)
-#define CFLASH0   (*( volatile struct FLASH_tag *)     0xC3F88000)
-#define CFLASH1   (*( volatile struct FLASH_tag *)     0xC3FB0000)
-#define CFLASH2   (*( volatile struct FLASH_tag *)     0xC3FB4000)
-#define SIU       (*( volatile struct SIU_tag *)       0xC3F90000)
-     
-#define EMIOS     (*( volatile struct EMIOS_tag *)     0xC3FA0000)
-#define PMC       (*( volatile struct PMC_tag *)       0xC3FBC000)
-#define ETPU      (*( volatile struct ETPU_tag *)      0xC3FC0000)
-#define ETPU_DATA_RAM  (*( uint32_t *)                 0xC3FC8000)
-#define ETPU_DATA_RAM_EXT  (*( uint32_t *)             0xC3FCC000)
-#define ETPU_DATA_RAM_END                 0xC3FC8BFC
-#define CODE_RAM       (*( uint32_t *)                 0xC3FD0000)
-#define ETPU_CODE_RAM  (*( uint32_t *)                 0xC3FD0000)
-#define PIT       (*( volatile struct PIT_tag *)       0xC3FF0000)
-     
-#define XBAR      (*( volatile struct XBAR_tag *)      0xFFF04000)
-#define SWT       (*( volatile struct SWT_tag *)       0xFFF38000)
-#define STM       (*( volatile struct STM_tag *)       0xFFF3C000)
-#define ECSM       (*( volatile struct ECSM_tag *)     0xFFF40000)
-#define EDMA      (*( volatile struct EDMA_tag *)      0xFFF44000)
-#define INTC      (*( volatile struct INTC_tag *)      0xFFF48000)
-     
-#define EQADC     (*( volatile struct EQADC_tag *)     0xFFF80000)
-#define DECFIL    (*( volatile struct DECFIL_tag *)    0xFFF88000)
-     
-#define DSPI_B    (*( volatile struct DSPI_tag *)      0xFFF94000)
-#define DSPI_C    (*( volatile struct DSPI_tag *)      0xFFF98000)
-     
-#define ESCI_A    (*( volatile struct ESCI_tag *)      0xFFFB0000)
-#define ESCI_A_12_13    (*( volatile struct ESCI_12_13_bit_tag *)      0xFFFB0006)
-#define ESCI_B    (*( volatile struct ESCI_tag *)      0xFFFB4000)
-#define ESCI_B_12_13    (*( volatile struct ESCI_12_13_bit_tag *)      0xFFFB4006)
-     
-#define CAN_A     (*( volatile struct FLEXCAN2_tag *)  0xFFFC0000)
-#define CAN_C     (*( volatile struct FLEXCAN2_tag *)  0xFFFC8000)
-     
-#define TSENS    (*( volatile struct TSENS_tag *)      0xFFFEC000)
-     
-#ifdef __MWERKS__
-#pragma pop
-#endif  /* 
- */
-     
-#ifdef  __cplusplus
-} 
-#endif  /* 
- */
- 
-#endif  /* ifdef _MPC563M_H */
-/*********************************************************************
- *
- * Copyright:
- *	Freescale Semiconductor, INC. All Rights Reserved.
- *  You are hereby granted a copyright license to use, modify, and
- *  distribute the SOFTWARE so long as this entire notice is
- *  retained without alteration in any modified and/or redistributed
- *  versions, and that such modified versions are clearly identified
- *  as such. No licenses are granted by implication, estoppel or
- *  otherwise under any patents or trademarks of Freescale
- *  Semiconductor, Inc. This software is provided on an "AS IS"
- *  basis and without warranty.
- *
- *  To the maximum extent permitted by applicable law, Freescale
- *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
- *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
- *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
- *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
- *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
- *
- *  To the maximum extent permitted by applicable law, IN NO EVENT
- *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
- *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
- *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
- *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
- *
- *  Freescale Semiconductor assumes no responsibility for the
- *  maintenance and support of this software
- *
- ********************************************************************/ 
- 
diff --git a/os/hal/platforms/SPC564Axx/hal_lld.c b/os/hal/platforms/SPC564Axx/hal_lld.c
deleted file mode 100644
index 4c665ee25..000000000
--- a/os/hal/platforms/SPC564Axx/hal_lld.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC564Axx/hal_lld.c
- * @brief   SPC564Axx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-  uint32_t n;
-
-  /* The SRAM is parked on the load/store port, for some unknown reason it
-     is defaulted on the instructions port and this kills performance.*/
-  XBAR.SGPCR2.B.PARK = 1;               /* RAM slave on load/store port.*/
-
-  /* The DMA priority is placed above the CPU priority in order to not
-     starve I/O activities while the CPU is executing tight loops (FLASH
-     and SRAM slave ports only).*/
-#if !defined(_SPC564A70_)
-  XBAR.MPR0.R = 0x34000021;             /* Flash slave port priorities:
-                                            eDMA (4):              0 (highest)
-                                            Core Instructions (0): 1
-                                            Core Data (1):         2
-                                            EBI (7):               3
-                                            Flexray (6):           4        */
-  XBAR.MPR2.R = 0x34000021;             /* SRAM slave port priorities:
-                                            eDMA (4):              0 (highest)
-                                            Core Instructions (0): 1
-                                            Core Data (1):         2
-                                            EBI (7):               3
-                                            FlexRay (6):           4        */
-#else /* defined(_SPC564A70_) */
-  XBAR.MPR0.R = 0x03000021;             /* Flash slave port priorities:
-                                            eDMA (4):              0 (highest)
-                                            Core Instructions (0): 1
-                                            Core Data (1):         2
-                                            Flexray (6):           3        */
-  XBAR.MPR2.R = 0x03000021;             /* SRAM slave port priorities:
-                                            eDMA (4):              0 (highest)
-                                            Core Instructions (0): 1
-                                            Core Data (1):         2
-                                            FlexRay (6):           3        */
-#endif /* defined(_SPC564A70_) */
-
-  /* Decrementer timer initialized for system tick use, note, it is
-     initialized here because in the OSAL layer the system clock frequency
-     is not yet known.*/
-  n = SPC5_SYSCLK / CH_FREQUENCY;
-  asm volatile ("mtspr   22, %[n]           \t\n"   /* Init. DEC register.  */
-                "mtspr   54, %[n]           \t\n"   /* Init. DECAR register.*/
-                "lis     %%r3, 0x0440       \t\n"   /* DIE ARE bits.        */
-                "mtspr   340, %%r3"                 /* TCR register.        */
-                : : [n] "r" (n) : "r3");
-
-  /* TB counter enabled for debug and measurements.*/
-  asm volatile ("li      %%r3, 0x4000       \t\n"   /* TBEN bit.            */
-                "mtspr   1008, %%r3"                /* HID0 register.       */
-                : : : "r3");
-
-  /* INTC initialization, software vector mode, 4 bytes vectors, starting
-     at priority 0.*/
-  INTC.MCR.R   = 0;
-  INTC.CPR.R   = 0;
-  INTC.IACKR.R = (uint32_t)_vectors;
-
-  /* eMIOS initialization.*/
-  EMIOS.MCR.R = (1U << 26) | SPC5_EMIOS_GPRE;       /* GPREN and GPRE.      */
-
-  /* EDMA initialization.*/
-  edmaInit();
-}
-
-/**
- * @brief   SPC563 clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h and
- *          @p hal_lld.h
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void spc_clock_init(void) {
-
-  /* Setting up RAM/Flash wait states and the prefetching bits.*/
-  ECSM.MUDCR.R = SPC5_RAM_WS;
-  FLASH_A.BIUCR.R  = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
-  FLASH_A.BIUCR2.R = 0;
-#if !defined(_SPC564A70_)
-  /* The second controller is only present in Andorra 3M or 4M.*/
-  FLASH_B.BIUCR.R  = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
-  FLASH_B.BIUCR2.R = 0;
-#endif /* !defined(_SPC564A70_) */
-
-#if !SPC5_NO_INIT
-  /* PLL activation.*/
-  FMPLL.ESYNCR1.B.EMODE     = 1;                    /* Enhanced mode on.    */
-  FMPLL.ESYNCR1.B.CLKCFG   &= 1;                    /* Bypass mode, PLL off.*/
-#if !SPC5_CLK_BYPASS
-  FMPLL.ESYNCR1.B.CLKCFG   |= 2;                    /* PLL on.              */
-  FMPLL.ESYNCR1.B.EPREDIV   = SPC5_CLK_PREDIV;
-  FMPLL.ESYNCR1.B.EMFD      = SPC5_CLK_MFD;
-  FMPLL.ESYNCR2.B.ERFD      = SPC5_CLK_RFD;
-  while (!FMPLL.SYNSR.B.LOCK)
-    ;
-  FMPLL.ESYNCR1.B.CLKCFG   |= 4;                    /* Clock from the PLL.  */
-#endif /* !SPC5_CLK_BYPASS */
-#endif /* !SPC5_NO_INIT */
-}
-
-/** @} */
diff --git a/os/hal/platforms/SPC564Axx/hal_lld.h b/os/hal/platforms/SPC564Axx/hal_lld.h
deleted file mode 100644
index 093400f7b..000000000
--- a/os/hal/platforms/SPC564Axx/hal_lld.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC564Axx/hal_lld.h
- * @brief   SPC564Axx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - SPC5_XOSC_CLK.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "xpc564a.h"
-#include "spc564a_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME           "SPC564Axx Powertrain"
-
-/**
- * @name    ESYNCR2 register definitions
- * @{
- */
-#define SPC5_RFD_DIV2           0           /**< Divide VCO frequency by 2. */
-#define SPC5_RFD_DIV4           1           /**< Divide VCO frequency by 4. */
-#define SPC5_RFD_DIV8           2           /**< Divide VCO frequency by 8. */
-#define SPC5_RFD_DIV16          3           /**< Divide VCO frequency by 16.*/
-/** @} */
-
-/**
- * @name    BIUCR register definitions
- * @{
- */
-#define BIUCR_BANK1_TOO         0x01000000  /**< Use settings for bank1 too.*/
-#define BIUCR_MASTER7_PREFETCH  0x00800000  /**< Enable master 7 prefetch.  */
-#define BIUCR_MASTER6_PREFETCH  0x00400000  /**< Enable master 6 prefetch.  */
-#define BIUCR_MASTER5_PREFETCH  0x00200000  /**< Enable master 5 prefetch.  */
-#define BIUCR_MASTER4_PREFETCH  0x00100000  /**< Enable master 4 prefetch.  */
-#define BIUCR_MASTER3_PREFETCH  0x00080000  /**< Enable master 3 prefetch.  */
-#define BIUCR_MASTER2_PREFETCH  0x00040000  /**< Enable master 2 prefetch.  */
-#define BIUCR_MASTER1_PREFETCH  0x00020000  /**< Enable master 1 prefetch.  */
-#define BIUCR_MASTER0_PREFETCH  0x00010000  /**< Enable master 0 prefetch.  */
-#define BIUCR_APC_MASK          0x0000E000  /**< APC field mask.            */
-#define BIUCR_APC_0             (0 << 13)   /**< No additional hold cycles. */
-#define BIUCR_APC_1             (1 << 13)   /**< 1 additional hold cycle.   */
-#define BIUCR_APC_2             (2 << 13)   /**< 2 additional hold cycles.  */
-#define BIUCR_APC_3             (3 << 13)   /**< 3 additional hold cycles.  */
-#define BIUCR_APC_4             (4 << 13)   /**< 4 additional hold cycles.  */
-#define BIUCR_APC_5             (5 << 13)   /**< 5 additional hold cycles.  */
-#define BIUCR_APC_6             (6 << 13)   /**< 6 additional hold cycles.  */
-#define BIUCR_WWSC_MASK         0x00001800  /**< WWSC field mask.           */
-#define BIUCR_WWSC_0            (0 << 11)   /**< No write wait states.      */
-#define BIUCR_WWSC_1            (1 << 11)   /**< 1 write wait state.        */
-#define BIUCR_WWSC_2            (2 << 11)   /**< 2 write wait states.       */
-#define BIUCR_WWSC_3            (3 << 11)   /**< 3 write wait states.       */
-#define BIUCR_RWSC_MASK         0x00001800  /**< RWSC field mask.           */
-#define BIUCR_RWSC_0            (0 << 8)    /**< No read wait states.       */
-#define BIUCR_RWSC_1            (1 << 8)    /**< 1 read wait state.         */
-#define BIUCR_RWSC_2            (2 << 8)    /**< 2 read wait states.        */
-#define BIUCR_RWSC_3            (3 << 8)    /**< 3 read wait states.        */
-#define BIUCR_RWSC_4            (4 << 8)    /**< 4 read wait states.        */
-#define BIUCR_RWSC_5            (5 << 8)    /**< 5 read wait states.        */
-#define BIUCR_RWSC_6            (6 << 8)    /**< 6 read wait states.        */
-#define BIUCR_RWSC_7            (7 << 8)    /**< 7 read wait states.        */
-#define BIUCR_DPFEN             0x00000040  /**< Data prefetch enable.      */
-#define BIUCR_IPFEN             0x00000010  /**< Instr. prefetch enable.    */
-#define BIUCR_PFLIM_MASK        0x00000060  /**< PFLIM field mask.          */
-#define BIUCR_PFLIM_NO          (0 << 1)    /**< No prefetching.            */
-#define BIUCR_PFLIM_ON_MISS     (1 << 1)    /**< Prefetch on miss.          */
-#define BIUCR_PFLIM_ON_HITMISS  (2 << 1)    /**< Prefetch on hit and miss.  */
-#define BIUCR_BFEN              0x00000001  /**< Flash buffering enable.    */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Disables the clocks initialization in the HAL.
- */
-#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
-#define SPC5_NO_INIT                        FALSE
-#endif
-
-/**
- * @brief   Clock bypass.
- * @note    If set to @p TRUE then the PLL is not started and initialized, the
- *          external clock is used as-is and the other clock-related settings
- *          are ignored.
- */
-#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
-#define SPC5_CLK_BYPASS                     FALSE
-#endif
-
-/**
- * @brief   Disables the overclock checks.
- */
-#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
-#define SPC5_ALLOW_OVERCLOCK                FALSE
-#endif
-
-/**
- * @brief   External clock pre-divider.
- * @note    Must be in range 1...15.
- */
-#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_CLK_PREDIV_VALUE               2
-#endif
-
-/**
- * @brief   Multiplication factor divider.
- * @note    Must be in range 32...96.
- */
-#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
-#define SPC5_CLK_MFD_VALUE                  75
-#endif
-
-/**
- * @brief   Reduced frequency divider.
- */
-#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
-#define SPC5_CLK_RFD                        RFD_DIV2
-#endif
-
-/**
- * @brief   Flash buffer and prefetching settings.
- * @note    Please refer to the SPC564Axx reference manual about the meaning
- *          of the following bits, if in doubt DO NOT MODIFY IT.
- * @note    Do not specify the APC, WWSC, RWSC bits in this value because
- *          those are calculated from the system clock and ORed with this
- *          value.
- */
-#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__)
-#define SPC5_FLASH_BIUCR                    (BIUCR_BANK1_TOO |              \
-                                             BIUCR_MASTER4_PREFETCH |       \
-                                             BIUCR_MASTER0_PREFETCH |       \
-                                             BIUCR_DPFEN |                  \
-                                             BIUCR_IPFEN |                  \
-                                             BIUCR_PFLIM_ON_MISS |          \
-                                             BIUCR_BFEN)
-#endif
-
-/**
- * @brief   eMIOS global prescaler value.
- */
-#if !defined(SPC5_EMIOS_GPRE_VALUE) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_GPRE_VALUE               20
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(SPC564Axx_MCUCONF)
-#error "Using a wrong mcuconf.h file, SPC564Axx_MCUCONF not defined"
-#endif
-
-#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15)
-#error "invalid SPC5_CLK_PREDIV_VALUE value specified"
-#endif
-
-#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96)
-#error "invalid SPC5_CLK_MFD_VALUE value specified"
-#endif
-
-#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) &&   \
-    (SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16)
-#error "invalid SPC5_CLK_RFD value specified"
-#endif
-
-#if (SPC5_EMIOS_GPRE_VALUE < 1) || (SPC5_EMIOS_GPRE_VALUE > 256)
-#error "invalid SPC5_EMIOS_GPRE_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL input divider.
- */
-#define SPC5_CLK_PREDIV     (SPC5_CLK_PREDIV_VALUE - 1)
-
-/**
- * @brief   PLL multiplier.
- */
-#define SPC5_CLK_MFD        (SPC5_CLK_MFD_VALUE)
-
-/**
- * @brief   PLL output clock.
- */
-#define SPC5_PLLCLK         ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) *      \
-                             SPC5_CLK_MFD_VALUE)
-
-#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000)
-#error "VCO frequency out of the acceptable range (256...512)"
-#endif
-
-/**
- * @brief   PLL output clock.
- */
-#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__)
-#define SPC5_SYSCLK         (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1)))
-#else
-#define SPC5_SYSCLK         SPC5_XOSC_CLK
-#endif
-
-#if (SPC5_SYSCLK > 150000000) && !SPC5_ALLOW_OVERCLOCK
-#error "System clock above maximum rated frequency (150MHz)"
-#endif
-
-/**
- * @brief   Flash wait states are a function of the system clock.
- */
-#if (SPC5_SYSCLK <= 20000000) || defined(__DOXYGEN__)
-#define SPC5_FLASH_WS       (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_3)
-#elif SPC5_SYSCLK <= 61000000
-#define SPC5_FLASH_WS       (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_3)
-#elif SPC5_SYSCLK <= 90000000
-#define SPC5_FLASH_WS       (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_3)
-#elif SPC5_SYSCLK <= 123000000
-#define SPC5_FLASH_WS       (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_3)
-#else
-#define SPC5_FLASH_WS       (BIUCR_APC_4 | BIUCR_RWSC_4 | BIUCR_WWSC_3)
-#endif
-
-/**
- * @brief   RAM wait states are a function of the system clock.
- */
-#if (SPC5_SYSCLK <= 98000000) || defined(__DOXYGEN__)
-#define SPC5_RAM_WS         0
-#else
-#define SPC5_RAM_WS         0x40000000
-#endif
-
-/**
- * @brief   eMIOS global prescaler setting.
- */
-#define SPC5_EMIOS_GPRE     (SPC5_EMIOS_GPRE_VALUE << 8)
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#include "spc5_edma.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void spc_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC564Axx/platform.mk b/os/hal/platforms/SPC564Axx/platform.mk
deleted file mode 100644
index 6abcecaec..000000000
--- a/os/hal/platforms/SPC564Axx/platform.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of all the SPC564Axx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC564Axx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC564Axx \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1
diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h
deleted file mode 100644
index 6619b82d3..000000000
--- a/os/hal/platforms/SPC564Axx/spc564a_registry.h
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC564Axx/spc564a_registry.h
- * @brief   SPC564Axx capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _SPC564A_REGISTRY_H_
-#define _SPC564A_REGISTRY_H_
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if defined(_SPC564A70B4_) || defined(_SPC564A70L7_)
-#define _SPC564A70_
-#elif defined(_SPC564A74B4_) || defined(_SPC564A74L7_)
-#define _SPC564A74_
-#elif defined(_SPC564A80B4_) || defined(_SPC564A80L7_)
-#define _SPC564A80_
-#else
-#error "SPC564Axx platform not defined"
-#endif
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    SPC564Axx capabilities
- * @{
- */
-/* DSPI attribures.*/
-#define SPC5_HAS_DSPI0                      FALSE
-#define SPC5_HAS_DSPI1                      TRUE
-#define SPC5_HAS_DSPI2                      TRUE
-#define SPC5_HAS_DSPI3                      TRUE
-#define SPC5_HAS_DSPI4                      FALSE
-#define SPC5_DSPI_FIFO_DEPTH                16
-#define SPC5_DSPI1_EOQF_HANDLER             vector132
-#define SPC5_DSPI1_EOQF_NUMBER              132
-#define SPC5_DSPI1_TFFF_HANDLER             vector133
-#define SPC5_DSPI1_TFFF_NUMBER              133
-#define SPC5_DSPI2_EOQF_HANDLER             vector137
-#define SPC5_DSPI2_EOQF_NUMBER              137
-#define SPC5_DSPI2_TFFF_HANDLER             vector138
-#define SPC5_DSPI2_TFFF_NUMBER              138
-#define SPC5_DSPI3_EOQF_HANDLER             vector142
-#define SPC5_DSPI3_EOQF_NUMBER              142
-#define SPC5_DSPI3_TFFF_HANDLER             vector143
-#define SPC5_DSPI3_TFFF_NUMBER              143
-#define SPC5_DSPI1_ENABLE_CLOCK()
-#define SPC5_DSPI1_DISABLE_CLOCK()
-#define SPC5_DSPI2_ENABLE_CLOCK()
-#define SPC5_DSPI2_DISABLE_CLOCK()
-#define SPC5_DSPI3_ENABLE_CLOCK()
-#define SPC5_DSPI3_DISABLE_CLOCK()
-
-/* eDMA attributes.*/
-#define SPC5_HAS_EDMA                       TRUE
-#define SPC5_EDMA_NCHANNELS                 64
-#define SPC5_EDMA_HAS_MUX                   FALSE
-#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID        12
-#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID        24
-#define SPC5_SPI_DSPI1_RX_DMA_CH_ID         13
-#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID        14
-#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID        25
-#define SPC5_SPI_DSPI2_RX_DMA_CH_ID         15
-#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID        16
-#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID        26
-#define SPC5_SPI_DSPI3_RX_DMA_CH_ID         17
-
-/* eQADC attributes.*/
-#define SPC5_HAS_EQADC                      TRUE
-
-/* eSCI attributes.*/
-#define SPC5_HAS_ESCIA                      TRUE
-#define SPC5_ESCIA_HANDLER                  vector146
-#define SPC5_ESCIA_NUMBER                   146
-
-#define SPC5_HAS_ESCIB                      TRUE
-#define SPC5_ESCIB_HANDLER                  vector149
-#define SPC5_ESCIB_NUMBER                   149
-
-#define SPC5_HAS_ESCIC                      TRUE
-#define SPC5_ESCIC_HANDLER                  vector473
-#define SPC5_ESCIC_NUMBER                   473
-
-/* SIU attributes.*/
-#define SPC5_HAS_SIU                        TRUE
-#define SPC5_SIU_SUPPORTS_PORTS             FALSE
-
-/* EMIOS attributes.*/
-#define SPC5_HAS_EMIOS                      TRUE
-
-#define SPC5_EMIOS_NUM_CHANNELS		        24
-
-#define SPC5_EMIOS_FLAG_F0_HANDLER          vector51
-#define SPC5_EMIOS_FLAG_F1_HANDLER          vector52
-#define SPC5_EMIOS_FLAG_F2_HANDLER          vector53
-#define SPC5_EMIOS_FLAG_F3_HANDLER          vector54
-#define SPC5_EMIOS_FLAG_F4_HANDLER          vector55
-#define SPC5_EMIOS_FLAG_F5_HANDLER          vector56
-#define SPC5_EMIOS_FLAG_F6_HANDLER          vector57
-#define SPC5_EMIOS_FLAG_F7_HANDLER          vector58
-#define SPC5_EMIOS_FLAG_F8_HANDLER          vector59
-#define SPC5_EMIOS_FLAG_F9_HANDLER          vector60
-#define SPC5_EMIOS_FLAG_F10_HANDLER         vector61
-#define SPC5_EMIOS_FLAG_F11_HANDLER         vector62
-#define SPC5_EMIOS_FLAG_F12_HANDLER         vector63
-#define SPC5_EMIOS_FLAG_F13_HANDLER         vector64
-#define SPC5_EMIOS_FLAG_F14_HANDLER         vector65
-#define SPC5_EMIOS_FLAG_F15_HANDLER         vector66
-#define SPC5_EMIOS_FLAG_F16_HANDLER         vector202
-#define SPC5_EMIOS_FLAG_F17_HANDLER         vector203
-#define SPC5_EMIOS_FLAG_F18_HANDLER         vector204
-#define SPC5_EMIOS_FLAG_F19_HANDLER         vector205
-#define SPC5_EMIOS_FLAG_F20_HANDLER         vector206
-#define SPC5_EMIOS_FLAG_F21_HANDLER         vector207
-#define SPC5_EMIOS_FLAG_F22_HANDLER         vector208
-#define SPC5_EMIOS_FLAG_F23_HANDLER         vector209
-#define SPC5_EMIOS_FLAG_F0_NUMBER           51
-#define SPC5_EMIOS_FLAG_F1_NUMBER           52
-#define SPC5_EMIOS_FLAG_F2_NUMBER           53
-#define SPC5_EMIOS_FLAG_F3_NUMBER           54
-#define SPC5_EMIOS_FLAG_F4_NUMBER           55
-#define SPC5_EMIOS_FLAG_F5_NUMBER           56
-#define SPC5_EMIOS_FLAG_F6_NUMBER           57
-#define SPC5_EMIOS_FLAG_F7_NUMBER           58
-#define SPC5_EMIOS_FLAG_F8_NUMBER           59
-#define SPC5_EMIOS_FLAG_F9_NUMBER           60
-#define SPC5_EMIOS_FLAG_F10_NUMBER          61
-#define SPC5_EMIOS_FLAG_F11_NUMBER          62
-#define SPC5_EMIOS_FLAG_F12_NUMBER          63
-#define SPC5_EMIOS_FLAG_F13_NUMBER          64
-#define SPC5_EMIOS_FLAG_F14_NUMBER          65
-#define SPC5_EMIOS_FLAG_F15_NUMBER          66
-#define SPC5_EMIOS_FLAG_F16_NUMBER          202
-#define SPC5_EMIOS_FLAG_F17_NUMBER          203
-#define SPC5_EMIOS_FLAG_F18_NUMBER          204
-#define SPC5_EMIOS_FLAG_F19_NUMBER          205
-#define SPC5_EMIOS_FLAG_F20_NUMBER          206
-#define SPC5_EMIOS_FLAG_F21_NUMBER          207
-#define SPC5_EMIOS_FLAG_F22_NUMBER          208
-#define SPC5_EMIOS_FLAG_F23_NUMBER          209
-
-#define SPC5_EMIOS_CLK                      (SPC5_SYSCLK /                  \
-                                             SPC5_EMIOS_GPRE_VALUE)
-#define SPC5_EMIOS_ENABLE_CLOCK()
-#define SPC5_EMIOS_DISABLE_CLOCK()
-
-/* FlexCAN attributes.*/
-#define SPC5_HAS_FLEXCAN0                                   TRUE
-#define SPC5_FLEXCAN0_MB                                    64
-#define SPC5_FLEXCAN0_SHARED_IRQ                            FALSE
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER              vector152
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER           vector153
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_HANDLER                vector155
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_01_HANDLER                vector156
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_02_HANDLER                vector157
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_03_HANDLER                vector158
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_HANDLER                vector159
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_05_HANDLER                vector160
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_06_HANDLER                vector161
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_07_HANDLER                vector162
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_HANDLER                vector163
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_09_HANDLER                vector164
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_10_HANDLER                vector165
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_11_HANDLER                vector166
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_HANDLER                vector167
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_13_HANDLER                vector168
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_14_HANDLER                vector169
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_15_HANDLER                vector170
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER             vector171
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER             vector172
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER               152
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER            153
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_NUMBER                 155
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_01_NUMBER                 156
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_02_NUMBER                 157
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_03_NUMBER                 158
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_NUMBER                 159
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_05_NUMBER                 160
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_06_NUMBER                 161
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_07_NUMBER                 162
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_NUMBER                 163
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_09_NUMBER                 164
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_10_NUMBER                 165
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_11_NUMBER                 166
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_NUMBER                 167
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_13_NUMBER                 168
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_14_NUMBER                 169
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_15_NUMBER                 170
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER              171
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER              172
-#define SPC5_FLEXCAN0_ENABLE_CLOCK()
-#define SPC5_FLEXCAN0_DISABLE_CLOCK()
-
-#define SPC5_HAS_FLEXCAN1                                   TRUE
-#define SPC5_FLEXCAN1_MB                                    64
-#define SPC5_FLEXCAN1_SHARED_IRQ                            FALSE
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER              vector173
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER           vector174
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_HANDLER                vector176
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_01_HANDLER                vector177
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_02_HANDLER                vector178
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_03_HANDLER                vector179
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_HANDLER                vector180
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_05_HANDLER                vector181
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_06_HANDLER                vector182
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_07_HANDLER                vector183
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_HANDLER                vector184
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_09_HANDLER                vector185
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_10_HANDLER                vector186
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_11_HANDLER                vector187
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_HANDLER                vector188
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_13_HANDLER                vector189
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_14_HANDLER                vector190
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_15_HANDLER                vector191
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER             vector192
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER             vector193
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER               173
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER            174
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_NUMBER                 176
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_01_NUMBER                 177
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_02_NUMBER                 178
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_03_NUMBER                 179
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_NUMBER                 180
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_05_NUMBER                 181
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_06_NUMBER                 182
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_07_NUMBER                 183
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_NUMBER                 184
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_09_NUMBER                 185
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_10_NUMBER                 186
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_11_NUMBER                 187
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_NUMBER                 188
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_13_NUMBER                 189
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_14_NUMBER                 190
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_15_NUMBER                 191
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER              192
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER              193
-#define SPC5_FLEXCAN1_ENABLE_CLOCK()
-#define SPC5_FLEXCAN1_DISABLE_CLOCK()
-
-#define SPC5_HAS_FLEXCAN2                                   TRUE
-#define SPC5_FLEXCAN2_MB                                    64
-#define SPC5_FLEXCAN2_SHARED_IRQ                            FALSE
-#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER              vector280
-#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER           vector281
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_HANDLER                vector283
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_01_HANDLER                vector284
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_02_HANDLER                vector285
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_03_HANDLER                vector286
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_HANDLER                vector287
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_05_HANDLER                vector288
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_06_HANDLER                vector289
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_07_HANDLER                vector290
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_HANDLER                vector291
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_09_HANDLER                vector292
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_10_HANDLER                vector293
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_11_HANDLER                vector294
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_HANDLER                vector295
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_13_HANDLER                vector296
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_14_HANDLER                vector297
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_15_HANDLER                vector298
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER             vector299
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER             vector300
-#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER               280
-#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER            281
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_NUMBER                 283
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_01_NUMBER                 284
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_02_NUMBER                 285
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_03_NUMBER                 286
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_NUMBER                 287
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_05_NUMBER                 288
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_06_NUMBER                 289
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_07_NUMBER                 290
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_NUMBER                 291
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_09_NUMBER                 292
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_10_NUMBER                 293
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_11_NUMBER                 294
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_NUMBER                 295
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_13_NUMBER                 296
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_14_NUMBER                 297
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_15_NUMBER                 298
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER              299
-#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER              300
-#define SPC5_FLEXCAN2_ENABLE_CLOCK()
-#define SPC5_FLEXCAN2_DISABLE_CLOCK()
-/** @} */
-
-#endif /* _SPC564A_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC564Axx/typedefs.h b/os/hal/platforms/SPC564Axx/typedefs.h
deleted file mode 100644
index c0eccf4e8..000000000
--- a/os/hal/platforms/SPC564Axx/typedefs.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC564Axx/typedefs.h
- * @brief   Dummy typedefs file.
- */
-
-#ifndef _TYPEDEFS_H_
-#define _TYPEDEFS_H_
-
-#include "chtypes.h"
-
-#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/platforms/SPC564Axx/xpc564a.h b/os/hal/platforms/SPC564Axx/xpc564a.h
deleted file mode 100644
index 24c159e13..000000000
--- a/os/hal/platforms/SPC564Axx/xpc564a.h
+++ /dev/null
@@ -1,6377 +0,0 @@
-/**************************************************************************/
-/* FILE NAME: MPC5644A.h      COPYRIGHT(c) Freescale & STMicroelectronics */
-/* VERSION:  0.5                           2010 - All Rights Reserved     */
-/*                                                                        */
-/* DESCRIPTION:                                                           */
-/* This file contains all of the register and bit field definitions for   */
-/* MPC5644A.                                                              */
-/*========================================================================*/
-/* UPDATE HISTORY                                                         */
-/* REV      AUTHOR      DATE       DESCRIPTION OF CHANGE                  */
-/* ---   -----------  ---------    ---------------------                  */
-/* 0.1   R. MORAN     10/Aug/09    Initial Alpha version.                 */
-/* 0.2   R. Moran     09/Nov/09    Several Updates:                       */
-/*                                 - XBAR - MPR/SGPCR'3' changed to '2'   */
-/*                                 - CFCR, IDCR, CFTCR array sizes altered*/
-/*                                 - IDIS,CASCD added to DEC_Filter MCR   */
-/*                                 - WDM fields changed in eTPU_WDTR reg  */
-/*                                 - Additional ECSM registers added      */
-/* 0.3   R. Moran     14/Jan/10    Several Updates:                       */
-/*                                 - Flash User Test Register implemented */
-/*                                 - MPU.EDR[3] register removed          */
-/*                                 - Minor Loop TCD bits implemented      */                                   
-/*                                 - Temperature Sensor implemented       */                                   
-/*                                 - DSPI.MCR.B.PES implemented           */ 
-/* 0.4   R. Moran     30/Mar/10    - Added DTS Module Registers           */
-/*                                 - Added Reaction Module                */ 
-/*								   - eQADC REDLCCR register				  */            
-/*								   - Temp Sensor TCCR0 corrected 		  */
-/*								   - CFTCR definition changed             */
-/*                                 - EBI CAL_BR/OR updated                */
-/*                                 - XBAR MPR0,1,3,7 fixed master fields  */
-/*                                 - Decimation filter updated to support */
-/*                                   Integration filter and rev2 changes  */
-/* 0.5	 I. Harris	  25/May/10    - Updated ECSM_ESR with 1bit cor. fld  */
-/*								   - Updated ECSM_ECR with 1bit cor. ena  */
-/*								   - Corrected ECSM_MUDR endianness		  */
-/*								   - Corrected ECSM_MWCR ENBWCR field name*/
-/*								   - Updated SIU_IREEx fields			  */
-/*                                 - Added EBI_MCR DBM field              */
-/*								   - Added PBRIDGE Registers			  */
-/*                                 - Added SIU EMPCR0 Register            */
-/*                                 - Included FlexCAN RXFIFO structure    */
-/**************************************************************************/
-
-/**************************************************************************/
-/* Example instantiation and use:                                         */
-/*                                                                        */
-/*  <MODULE>.<REGISTER>.B.<BIT> = 1;                                      */
-/*  <MODULE>.<REGISTER>.R       = 0x10000000;                             */
-/*                                                                        */
-/**************************************************************************/
-
-#ifndef _MPC5644_H_
-#define _MPC5644_H_
-
-#include "typedefs.h"
-
-#ifdef  __cplusplus
-extern "C" {
-#endif
-
-#ifdef __MWERKS__
-#pragma push
-#pragma ANSI_strict off
-#endif
-
-/****************************************************************************/
-/*       DMA2 Transfer Control Descriptor                                   */
-/****************************************************************************/
-
-    struct EDMA_TCD_STD_tag {          /* for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */
-            /* 00 */
-            vuint32_t SADDR;    /* Source Address */
-    
-            /* 04 */            /* Transfer Attributes */
-            vuint16_t SMOD:5;   /* Source Address Modulo */
-            vuint16_t SSIZE:3;  /* Source Data Transfer Size */
-            vuint16_t DMOD:5;   /* Destination Address Modulo */
-            vuint16_t DSIZE:3;  /* Destination Data Transfer Size */
-    
-            /* 06 */
-            vint16_t SOFF;      /* Signed Source Address Offset */
-    
-            /* 08 */
-            vuint32_t NBYTES;   /* Inner ("Minor") Byte Transfer Count */
-    
-            /* 0C */
-            vint32_t SLAST;     /* Last Source Address Adjustment */
-    
-            /* 10 */
-            vuint32_t DADDR;    /* Destination Address */
-    
-            /* 14 */
-            vuint16_t CITERE_LINK:1;     /* Enable Channel-to-Channel        */
-                                         /* Linking on Minor Loop Completion */
-            vuint16_t CITER:15;          /* Current Major Iteration Count    */
-    
-            /* 16 */
-            vint16_t DOFF;      /* Signed Destination Address Offset */
-    
-            /* 18 */
-            vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or  */
-                                /* Scatter/Gather Address (if E_SG = 1)     */
-    
-            /* 1C */
-            vuint16_t BITERE_LINK:1;    /* Enable Channel-to-Channel           */
-                                        /* Linking on Minor Loop Complete      */
-            vuint16_t BITER:15;         /* Starting ("Major") Iteration Count */
-    
-            /* 1E */                    /* Channel Control/Status */
-            vuint16_t BWC:2;            /* Bandwidth Control */
-            vuint16_t MAJORLINKCH:6;    /* Link Channel Number */
-            vuint16_t DONE:1;           /* Channel Done */
-            vuint16_t ACTIVE:1;
-            vuint16_t MAJORE_LINK:1;    /* Enable Channel-to-Channel Link */
-            vuint16_t E_SG:1;           /* Enable Scatter/Gather Descriptor */
-            vuint16_t D_REQ:1;          /* Disable IPD_REQ When Done */
-            vuint16_t INT_HALF:1;       /* Interrupt on CITER = (BITER >> 1) */
-            vuint16_t INT_MAJ:1;        /* Interrupt on Major Loop Completion */
-            vuint16_t START:1;          /* Explicit Channel Start */
-    };
-
-    
-
-    struct EDMA_TCD_alt1_tag {  /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */
-
-            /* 00 */
-            vuint32_t SADDR;    /* Source Address */
-
-            /* 04 */            /* Transfer Attributes */
-            vuint16_t SMOD:5;   /* Source Address Modulo */
-            vuint16_t SSIZE:3;  /* Source Data Transfer Size */
-            vuint16_t DMOD:5;   /* Destination Address Modulo */
-            vuint16_t DSIZE:3;  /* Destination Data Transfer Size */
-
-            /* 06 */
-            vint16_t SOFF;      /* Signed Source Address Offset */
-
-            /* 08 */
-            vuint32_t NBYTES;   /* Inner ("Minor") Byte Transfer Count */
-
-            /* 0C */
-            vint32_t SLAST;     /* Last Source Address Adjustment */
-
-            /* 10 */
-            vuint32_t DADDR;    /* Destination Address */
-
-            /* 14 */
-            vuint16_t CITERE_LINK:1;     /* Enable Channel-to-Channel        */
-                                         /* Linking on Minor Loop Completion */
-            vuint16_t CITERLINKCH:6;     /* Link Channel Number              */
-            vuint16_t CITER:9;           /* Current Major Iteration Count    */
-
-            /* 16 */
-            vint16_t DOFF;      /* Signed Destination Address Offset */
-
-            /* 18 */
-            vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or  */
-                                /* Scatter/Gather Address (if E_SG = 1)     */
-
-            /* 1C */
-            vuint16_t BITERE_LINK:1;    /* Enable Channel-to-Channel           */
-                                        /* Linking on Minor Loop Complete      */
-            vuint16_t BITERLINKCH:6;    /* Link Channel Number                 */
-            vuint16_t BITER:9;          /* Starting ("Major") Iteration Count  */
-
-            /* 1E */                    /* Channel Control/Status */
-            vuint16_t BWC:2;            /* Bandwidth Control */
-            vuint16_t MAJORLINKCH:6;    /* Link Channel Number */
-            vuint16_t DONE:1;           /* Channel Done */
-            vuint16_t ACTIVE:1;         /* Channel Active */
-            vuint16_t MAJORE_LINK:1;    /* Enable Channel-to-Channel Link */
-            vuint16_t E_SG:1;           /* Enable Scatter/Gather Descriptor */
-            vuint16_t D_REQ:1;          /* Disable IPD_REQ When Done */
-            vuint16_t INT_HALF:1;       /* Interrupt on CITER = (BITER >> 1) */
-            vuint16_t INT_MAJ:1;        /* Interrupt on Major Loop Completion */
-            vuint16_t START:1;          /* Explicit Channel Start */
-    };
-
-    struct EDMA_TCD_alt2_tag {  /*       for alternate format TCDs (when EDMA.EMLM=1) */
-
-            vuint32_t SADDR;    /* source address */
-
-            vuint16_t SMOD:5;   /* source address modulo */
-            vuint16_t SSIZE:3;  /* source transfer size */
-            vuint16_t DMOD:5;   /* destination address modulo */
-            vuint16_t DSIZE:3;  /* destination transfer size */
-            vint16_t SOFF;      /* signed source address offset */
-
-            vuint16_t SMLOE:1;  /* Source minor loop offset enable */
-            vuint16_t DMLOE:1;  /* Destination minor loop offset enable */
-            vuint32_t MLOFF:20; /* Minor loop Offset */
-            vuint16_t NBYTES:10;        /* inner (�minor�) byte count */
-
-            vint32_t SLAST;     /* last destination address adjustment, or
-
-                                   scatter/gather address (if e_sg = 1) */
-            vuint32_t DADDR;    /* destination address */
-
-            vuint16_t CITERE_LINK:1;
-            vuint16_t CITER:15;
-
-            vint16_t DOFF;      /* signed destination address offset */
-
-            vint32_t DLAST_SGA;
-
-            vuint16_t BITERE_LINK:1;    /* beginning ("major") iteration count */
-            vuint16_t BITER:15;
-
-            vuint16_t BWC:2;    /* bandwidth control */
-            vuint16_t MAJORLINKCH:6;    /* enable channel-to-channel link */
-            vuint16_t DONE:1;   /* channel done */
-            vuint16_t ACTIVE:1; /* channel active */
-            vuint16_t MAJORE_LINK:1;    /* enable channel-to-channel link */
-            vuint16_t E_SG:1;   /* enable scatter/gather descriptor */
-            vuint16_t D_REQ:1;  /* disable ipd_req when done */
-            vuint16_t INT_HALF:1;       /* interrupt on citer = (biter >> 1) */
-            vuint16_t INT_MAJ:1;        /* interrupt on major loop completion */
-            vuint16_t START:1;  /* explicit channel start */
-    };
-    
-
-/****************************************************************************/
-/*                          MODULE : eDMA                                   */
-/****************************************************************************/
-
-    struct EDMA_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;           /* Reserved */
-                vuint32_t CX:1;         /* Cancel Transfer */
-                vuint32_t ECX:1;        /* Error Cancel Transfer  */
-                vuint32_t GRP3PRI:2;    /* Channel Group 3 Priority  */
-                vuint32_t GRP2PRI:2;    /* Channel Group 2 Priority  */
-                vuint32_t GRP1PRI:2;    /* Channel Group 1 Priority  */
-                vuint32_t GRP0PRI:2;    /* Channel Group 0 Priority  */
-                vuint32_t EMLM:1;       /* Enable Minor Loop Mapping */
-                vuint32_t CLM:1;        /* Continuous Link Mode */
-                vuint32_t HALT:1;       /* Halt DMA Operations  */
-                vuint32_t HOE:1;        /* Halt On Error */
-                vuint32_t ERGA:1;       /* Enable Round Robin Group Arbitration */
-                vuint32_t ERCA:1;       /* Enable Round Robin Channel Arbitration */
-                vuint32_t EDBG:1;       /* Enable Debug */
-                vuint32_t:1;            /* Enable Buffered Writes */
-            } B;
-        } CR;                /* DMA Control Register @baseaddress + 0x0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t VLD:1;        /* Logical OR of all DMAERRH */
-                vuint32_t:14;           /* Reserved */
-                vuint32_t ECX:1;        /* Transfer Canceled */
-                vuint32_t GPE:1;        /* Group Priority Error */
-                vuint32_t CPE:1;        /* Channel Priority Error  */
-                vuint32_t ERRCHN:6;     /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */
-                vuint32_t SAE:1;        /* Source Address Error 0  */
-                vuint32_t SOE:1;        /* Source Offset Error */
-                vuint32_t DAE:1;        /* Destination Address Error */
-                vuint32_t DOE:1;        /* Destination Offset Error */
-                vuint32_t NCE:1;        /* Nbytes/Citer Configuration Error */
-                vuint32_t SGE:1;        /* Scatter/Gather Configuration Error */
-                vuint32_t SBE:1;        /* Source Bus Error */
-                vuint32_t DBE:1;        /* Destination Bus Error  */
-            } B;
-        } ESR;               /* Error Status Register @baseaddress + 0x4 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ERQ63:1;
-                vuint32_t ERQ62:1;
-                vuint32_t ERQ61:1;
-                vuint32_t ERQ60:1;
-                vuint32_t ERQ59:1;
-                vuint32_t ERQ58:1;
-                vuint32_t ERQ57:1;
-                vuint32_t ERQ56:1;
-                vuint32_t ERQ55:1;
-                vuint32_t ERQ54:1;
-                vuint32_t ERQ53:1;
-                vuint32_t ERQ52:1;
-                vuint32_t ERQ51:1;
-                vuint32_t ERQ50:1;
-                vuint32_t ERQ49:1;
-                vuint32_t ERQ48:1;
-                vuint32_t ERQ47:1;
-                vuint32_t ERQ46:1;
-                vuint32_t ERQ45:1;
-                vuint32_t ERQ44:1;
-                vuint32_t ERQ43:1;
-                vuint32_t ERQ42:1;
-                vuint32_t ERQ41:1;
-                vuint32_t ERQ40:1;
-                vuint32_t ERQ39:1;
-                vuint32_t ERQ38:1;
-                vuint32_t ERQ37:1;
-                vuint32_t ERQ36:1;
-                vuint32_t ERQ35:1;
-                vuint32_t ERQ34:1;
-                vuint32_t ERQ33:1;
-                vuint32_t ERQ32:1;
-            } B;
-        } ERQRH;              /* DMA Enable Request Register High @baseaddress + 0x8*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ERQ31:1;
-                vuint32_t ERQ30:1;
-                vuint32_t ERQ29:1;
-                vuint32_t ERQ28:1;
-                vuint32_t ERQ27:1;
-                vuint32_t ERQ26:1;
-                vuint32_t ERQ25:1;
-                vuint32_t ERQ24:1;
-                vuint32_t ERQ23:1;
-                vuint32_t ERQ22:1;
-                vuint32_t ERQ21:1;
-                vuint32_t ERQ20:1;
-                vuint32_t ERQ19:1;
-                vuint32_t ERQ18:1;
-                vuint32_t ERQ17:1;
-                vuint32_t ERQ16:1;
-                vuint32_t ERQ15:1;
-                vuint32_t ERQ14:1;
-                vuint32_t ERQ13:1;
-                vuint32_t ERQ12:1;
-                vuint32_t ERQ11:1;
-                vuint32_t ERQ10:1;
-                vuint32_t ERQ09:1;
-                vuint32_t ERQ08:1;
-                vuint32_t ERQ07:1;
-                vuint32_t ERQ06:1;
-                vuint32_t ERQ05:1;
-                vuint32_t ERQ04:1;
-                vuint32_t ERQ03:1;
-                vuint32_t ERQ02:1;
-                vuint32_t ERQ01:1;
-                vuint32_t ERQ00:1;
-            } B;
-        } ERQRL;              /* DMA Enable Request Register Low @baseaddress + 0xC*/
-
-        union {
-            vuint32_t R;
-            struct {
-
-                vuint32_t EEI63:1;
-                vuint32_t EEI62:1;
-                vuint32_t EEI61:1;
-                vuint32_t EEI60:1;
-                vuint32_t EEI59:1;
-                vuint32_t EEI58:1;
-                vuint32_t EEI57:1;
-                vuint32_t EEI56:1;
-                vuint32_t EEI55:1;
-                vuint32_t EEI54:1;
-                vuint32_t EEI53:1;
-                vuint32_t EEI52:1;
-                vuint32_t EEI51:1;
-                vuint32_t EEI50:1;
-                vuint32_t EEI49:1;
-                vuint32_t EEI48:1;
-                vuint32_t EEI47:1;
-                vuint32_t EEI46:1;
-                vuint32_t EEI45:1;
-                vuint32_t EEI44:1;
-                vuint32_t EEI43:1;
-                vuint32_t EEI42:1;
-                vuint32_t EEI41:1;
-                vuint32_t EEI40:1;
-                vuint32_t EEI39:1;
-                vuint32_t EEI38:1;
-                vuint32_t EEI37:1;
-                vuint32_t EEI36:1;
-                vuint32_t EEI35:1;
-                vuint32_t EEI34:1;
-                vuint32_t EEI33:1;
-                vuint32_t EEI32:1;
-            } B;
-        } EEIRH;              /* DMA Enable Error Interrupt Register High @baseaddress + 0x10*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EEI31:1;
-                vuint32_t EEI30:1;
-                vuint32_t EEI29:1;
-                vuint32_t EEI28:1;
-                vuint32_t EEI27:1;
-                vuint32_t EEI26:1;
-                vuint32_t EEI25:1;
-                vuint32_t EEI24:1;
-                vuint32_t EEI23:1;
-                vuint32_t EEI22:1;
-                vuint32_t EEI21:1;
-                vuint32_t EEI20:1;
-                vuint32_t EEI19:1;
-                vuint32_t EEI18:1;
-                vuint32_t EEI17:1;
-                vuint32_t EEI16:1;
-                vuint32_t EEI15:1;
-                vuint32_t EEI14:1;
-                vuint32_t EEI13:1;
-                vuint32_t EEI12:1;
-                vuint32_t EEI11:1;
-                vuint32_t EEI10:1;
-                vuint32_t EEI09:1;
-                vuint32_t EEI08:1;
-                vuint32_t EEI07:1;
-                vuint32_t EEI06:1;
-                vuint32_t EEI05:1;
-                vuint32_t EEI04:1;
-                vuint32_t EEI03:1;
-                vuint32_t EEI02:1;
-                vuint32_t EEI01:1;
-                vuint32_t EEI00:1;
-            } B;
-        } EEIRL;              /* DMA Enable Error Interrupt Register Low @baseaddress + 0x14*/
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t NOP:1;
-                vuint8_t SERQ:7;
-            } B;
-        } SERQR;              /* DMA Set Enable Request Register @baseaddress + 0x18*/
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t NOP:1;
-                vuint8_t CERQ:7;
-            } B;
-        } CERQR;              /* DMA Clear Enable Request Register @baseaddress + 0x19*/
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t NOP:1;
-                vuint8_t SEEI:7;
-            } B;
-        } SEEIR;              /* DMA Set Enable Error Interrupt Register @baseaddress + 0x1A*/
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t NOP:1;
-                vuint8_t CEEI:7;
-            } B;
-        } CEEIR;              /* DMA Clear Enable Error Interrupt Register @baseaddress + 0x1B*/
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t NOP:1;
-                vuint8_t CINT:7;
-            } B;
-        } CIRQR;              /* DMA Clear Interrupt Request Register @baseaddress + 0x1C */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t NOP:1;
-                vuint8_t CERR:7;
-            } B;
-        } CER;                /* DMA Clear error Register @baseaddress + 0x1D */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t NOP:1;
-                vuint8_t SSB:7;
-            } B;
-        } SSBR;               /* Set Start Bit Register @baseaddress + 0x1E */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t NOP:1;
-                vuint8_t CDSB:7;
-            } B;
-        } CDSBR;              /* Clear Done Status Bit Register @baseaddress + 0x1F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t INT63:1;
-                vuint32_t INT62:1;
-                vuint32_t INT61:1;
-                vuint32_t INT60:1;
-                vuint32_t INT59:1;
-                vuint32_t INT58:1;
-                vuint32_t INT57:1;
-                vuint32_t INT56:1;
-                vuint32_t INT55:1;
-                vuint32_t INT54:1;
-                vuint32_t INT53:1;
-                vuint32_t INT52:1;
-                vuint32_t INT51:1;
-                vuint32_t INT50:1;
-                vuint32_t INT49:1;
-                vuint32_t INT48:1;
-                vuint32_t INT47:1;
-                vuint32_t INT46:1;
-                vuint32_t INT45:1;
-                vuint32_t INT44:1;
-                vuint32_t INT43:1;
-                vuint32_t INT42:1;
-                vuint32_t INT41:1;
-                vuint32_t INT40:1;
-                vuint32_t INT39:1;
-                vuint32_t INT38:1;
-                vuint32_t INT37:1;
-                vuint32_t INT36:1;
-                vuint32_t INT35:1;
-                vuint32_t INT34:1;
-                vuint32_t INT33:1;
-                vuint32_t INT32:1;
-            } B;
-        } IRQRH;              /* DMA Interrupt Request High @baseaddress + 0x20 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t INT31:1;
-                vuint32_t INT30:1;
-                vuint32_t INT29:1;
-                vuint32_t INT28:1;
-                vuint32_t INT27:1;
-                vuint32_t INT26:1;
-                vuint32_t INT25:1;
-                vuint32_t INT24:1;
-                vuint32_t INT23:1;
-                vuint32_t INT22:1;
-                vuint32_t INT21:1;
-                vuint32_t INT20:1;
-                vuint32_t INT19:1;
-                vuint32_t INT18:1;
-                vuint32_t INT17:1;
-                vuint32_t INT16:1;
-                vuint32_t INT15:1;
-                vuint32_t INT14:1;
-                vuint32_t INT13:1;
-                vuint32_t INT12:1;
-                vuint32_t INT11:1;
-                vuint32_t INT10:1;
-                vuint32_t INT09:1;
-                vuint32_t INT08:1;
-                vuint32_t INT07:1;
-                vuint32_t INT06:1;
-                vuint32_t INT05:1;
-                vuint32_t INT04:1;
-                vuint32_t INT03:1;
-                vuint32_t INT02:1;
-                vuint32_t INT01:1;
-                vuint32_t INT00:1;
-            } B;
-        } IRQRL;              /* DMA Interrupt Request Low @baseaddress + 0x24 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ERR63:1;
-                vuint32_t ERR62:1;
-                vuint32_t ERR61:1;
-                vuint32_t ERR60:1;
-                vuint32_t ERR59:1;
-                vuint32_t ERR58:1;
-                vuint32_t ERR57:1;
-                vuint32_t ERR56:1;
-                vuint32_t ERR55:1;
-                vuint32_t ERR54:1;
-                vuint32_t ERR53:1;
-                vuint32_t ERR52:1;
-                vuint32_t ERR51:1;
-                vuint32_t ERR50:1;
-                vuint32_t ERR49:1;
-                vuint32_t ERR48:1;
-                vuint32_t ERR47:1;
-                vuint32_t ERR46:1;
-                vuint32_t ERR45:1;
-                vuint32_t ERR44:1;
-                vuint32_t ERR43:1;
-                vuint32_t ERR42:1;
-                vuint32_t ERR41:1;
-                vuint32_t ERR40:1;
-                vuint32_t ERR39:1;
-                vuint32_t ERR38:1;
-                vuint32_t ERR37:1;
-                vuint32_t ERR36:1;
-                vuint32_t ERR35:1;
-                vuint32_t ERR34:1;
-                vuint32_t ERR33:1;
-                vuint32_t ERR32:1;
-            } B;
-        } ERH;                /* DMA Error High @baseaddress + 0x28 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ERR31:1;
-                vuint32_t ERR30:1;
-                vuint32_t ERR29:1;
-                vuint32_t ERR28:1;
-                vuint32_t ERR27:1;
-                vuint32_t ERR26:1;
-                vuint32_t ERR25:1;
-                vuint32_t ERR24:1;
-                vuint32_t ERR23:1;
-                vuint32_t ERR22:1;
-                vuint32_t ERR21:1;
-                vuint32_t ERR20:1;
-                vuint32_t ERR19:1;
-                vuint32_t ERR18:1;
-                vuint32_t ERR17:1;
-                vuint32_t ERR16:1;
-                vuint32_t ERR15:1;
-                vuint32_t ERR14:1;
-                vuint32_t ERR13:1;
-                vuint32_t ERR12:1;
-                vuint32_t ERR11:1;
-                vuint32_t ERR10:1;
-                vuint32_t ERR09:1;
-                vuint32_t ERR08:1;
-                vuint32_t ERR07:1;
-                vuint32_t ERR06:1;
-                vuint32_t ERR05:1;
-                vuint32_t ERR04:1;
-                vuint32_t ERR03:1;
-                vuint32_t ERR02:1;
-                vuint32_t ERR01:1;
-                vuint32_t ERR00:1;
-            } B;
-        } ERL;                /* DMA Error Low @baseaddress + 0x2C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t HRS63:1;
-                vuint32_t HRS62:1;
-                vuint32_t HRS61:1;
-                vuint32_t HRS60:1;
-                vuint32_t HRS59:1;
-                vuint32_t HRS58:1;
-                vuint32_t HRS57:1;
-                vuint32_t HRS56:1;
-                vuint32_t HRS55:1;
-                vuint32_t HRS54:1;
-                vuint32_t HRS53:1;
-                vuint32_t HRS52:1;
-                vuint32_t HRS51:1;
-                vuint32_t HRS50:1;
-                vuint32_t HRS49:1;
-                vuint32_t HRS48:1;
-                vuint32_t HRS47:1;
-                vuint32_t HRS46:1;
-                vuint32_t HRS45:1;
-                vuint32_t HRS44:1;
-                vuint32_t HRS43:1;
-                vuint32_t HRS42:1;
-                vuint32_t HRS41:1;
-                vuint32_t HRS40:1;
-                vuint32_t HRS39:1;
-                vuint32_t HRS38:1;
-                vuint32_t HRS37:1;
-                vuint32_t HRS36:1;
-                vuint32_t HRS35:1;
-                vuint32_t HRS34:1;
-                vuint32_t HRS33:1;
-                vuint32_t HRS32:1;
-            } B;
-        } HRSH;               /* hardware request status high @baseaddress + 0x30 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t HRS31:1;
-                vuint32_t HRS30:1;
-                vuint32_t HRS29:1;
-                vuint32_t HRS28:1;
-                vuint32_t HRS27:1;
-                vuint32_t HRS26:1;
-                vuint32_t HRS25:1;
-                vuint32_t HRS24:1;
-                vuint32_t HRS23:1;
-                vuint32_t HRS22:1;
-                vuint32_t HRS21:1;
-                vuint32_t HRS20:1;
-                vuint32_t HRS19:1;
-                vuint32_t HRS18:1;
-                vuint32_t HRS17:1;
-                vuint32_t HRS16:1;
-                vuint32_t HRS15:1;
-                vuint32_t HRS14:1;
-                vuint32_t HRS13:1;
-                vuint32_t HRS12:1;
-                vuint32_t HRS11:1;
-                vuint32_t HRS10:1;
-                vuint32_t HRS09:1;
-                vuint32_t HRS08:1;
-                vuint32_t HRS07:1;
-                vuint32_t HRS06:1;
-                vuint32_t HRS05:1;
-                vuint32_t HRS04:1;
-                vuint32_t HRS03:1;
-                vuint32_t HRS02:1;
-                vuint32_t HRS01:1;
-                vuint32_t HRS00:1;
-            } B;
-        } HRSL;               /* hardware request status low @baseaddress + 0x34 */
-
-        uint32_t eDMA_reserved0038[50];  /* 0x0038-0x00FF */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t ECP:1;
-                vuint8_t DPA:1;
-                vuint8_t GRPPRI:2;
-                vuint8_t CHPRI:4;
-            } B;
-        } CPR[64];            /* Channel n Priority @baseaddress + 0x100 */
-
-        uint32_t eDMA_reserved0140[944];  /* 0x0140-0x0FFF */
-        
-        /* Select one of the following declarations depending on the DMA mode chosen */
-        struct EDMA_TCD_STD_tag TCD[64];              /* Standard Format   */
-        /* struct EDMA_TCD_alt1_tag TCD[64]; */       /* CITER/BITER Link  */
-        /* struct EDMA_TCD_alt2_tag TCD[64]; */       /* Minor Loop Offset */
-        
-        };
-
-
-
-/****************************************************************************/
-/*                     MODULE : XBAR                                      */
-/****************************************************************************/
-    struct XBAR_tag {
-        union {
-            vuint32_t R;
-            struct {
-                  vuint32_t:1;
-                vuint32_t MSTR7:3;      /* Master 7 Priority - Reserved */
-                  vuint32_t:1;          
-                vuint32_t MSTR6:3;      /* Master 6 Priority - FlexRay */  
-                  vuint32_t:4;			/* Master 5 Priority - Not implemented */
-                  vuint32_t:1;
-                vuint32_t MSTR4:3;      /* Master 4 Priority - eDMA */
-                  vuint32_t:4;          /* Master 3 Priority - Not implemented */
-                  vuint32_t:4;          /* Master 2 Priority - Not implemented */
-                  vuint32_t:1;
-                vuint32_t MSTR1:3;      /* Master 1 Priority - e200z4 Core load/store & Nexus port  */
-                  vuint32_t:1;
-                vuint32_t MSTR0:3;      /* Master 0 Priority - e200z4 core Instruction */
-            } B;
-        } MPR0;                 /* Master Priority Register for Slave port 0 (Flash) @baseaddress + 0x00 */
-
-        int32_t XBAR_reserved_0004[3];      /* 0x0004 - 0x000F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RO:1;
-                vuint32_t HLP:1;        /* Halt Low Priority */
-                  vuint32_t:6;
-                vuint32_t HPE7:1;       /* High Priority Enable */
-                vuint32_t HPE6:1;       /* High Priority Enable */
-                  vuint32_t:1;
-                vuint32_t HPE4:1;       /* High Priority Enable */
-                  vuint32_t:1;
-                  vuint32_t:1;
-                vuint32_t HPE1:1;       /* High Priority Enable */
-                vuint32_t HPE0:1;       /* High Priority Enable */
-                  vuint32_t:6;
-                vuint32_t ARB:2;
-                vuint32_t:2;
-                vuint32_t PCTL:2;
-                vuint32_t:1;
-                vuint32_t PARK:3;
-            } B;
-        } SGPCR0;               /* Slave General Purpose Control Register 0 (Flash) @baseaddress + 0x10 */
-
-        int32_t XBAR_reserved_0014[59];     /* 0x0014 - 0x01FF */
-
-        union {
-            vuint32_t R;
-            struct {
-                  vuint32_t:1;
-                vuint32_t MSTR7:3;      /* Master 7 Priority - Reserved */
-                  vuint32_t:1;          
-                vuint32_t MSTR6:3;      /* Master 6 Priority - FlexRay */  
-                  vuint32_t:4;			/* Master 5 Priority - Not implemented */
-                  vuint32_t:1;
-                vuint32_t MSTR4:3;      /* Master 4 Priority - eDMA */
-                  vuint32_t:4;          /* Master 3 Priority - Not implemented */
-                  vuint32_t:4;          /* Master 2 Priority - Not implemented */
-                  vuint32_t:1;
-                vuint32_t MSTR1:3;      /* Master 1 Priority - e200z4 Core load/store & Nexus port  */
-                  vuint32_t:1;
-                vuint32_t MSTR0:3;      /* Master 0 Priority - e200z4 core Instruction */
-            } B;
-        } MPR1;                 /* Master Priority Register for Slave port 1 (EBI) @baseaddress + 0x100 */
-
-        int32_t XBAR_reserved_0100[3];      /* 0x0100 - 0x010F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RO:1;
-                vuint32_t HLP:1;        /* Halt Low Priority */
-                  vuint32_t:6;
-                vuint32_t HPE7:1;       /* High Priority Enable */
-                vuint32_t HPE6:1;       /* High Priority Enable */
-                  vuint32_t:1;
-                vuint32_t HPE4:1;       /* High Priority Enable */
-                  vuint32_t:1;
-                  vuint32_t:1;
-                vuint32_t HPE1:1;       /* High Priority Enable */
-                vuint32_t HPE0:1;       /* High Priority Enable */
-                  vuint32_t:6;
-                vuint32_t ARB:2;
-                vuint32_t:2;
-                vuint32_t PCTL:2;
-                vuint32_t:1;
-                vuint32_t PARK:3;
-            } B;
-        } SGPCR1;               /* Slave General Purpose Control Register 1 (EBI) @baseaddress + 0x110 */
-
-        int32_t XBAR_reserved_0114[59]; /* 0x0114 - 0x01FF */
-
-        union {
-            vuint32_t R;
-            struct {
-                  vuint32_t:1;
-                vuint32_t MSTR7:3;      /* Master 7 Priority - Reserved */
-                  vuint32_t:1;          
-                vuint32_t MSTR6:3;      /* Master 6 Priority - FlexRay */  
-                  vuint32_t:4;			/* Master 5 Priority - Not implemented */
-                  vuint32_t:1;
-                vuint32_t MSTR4:3;      /* Master 4 Priority - eDMA */
-                  vuint32_t:4;          /* Master 3 Priority - Not implemented */
-                  vuint32_t:4;          /* Master 2 Priority - Not implemented */
-                  vuint32_t:1;
-                vuint32_t MSTR1:3;      /* Master 1 Priority - e200z4 Core load/store & Nexus port  */
-                  vuint32_t:1;
-                vuint32_t MSTR0:3;      /* Master 0 Priority - e200z4 core Instruction */
-            } B;
-        } MPR2;                 /* Master Priority Register for Slave port 2 (RAM) @baseaddress + 0x200 */
-
-        int32_t XBAR_reserved_0204[3];      /* 0x0204 - 0x020F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RO:1;
-                vuint32_t HLP:1;        /* Halt Low Priority */
-                  vuint32_t:6;
-                vuint32_t HPE7:1;       /* High Priority Enable */
-                vuint32_t HPE6:1;       /* High Priority Enable */
-                  vuint32_t:1;
-                vuint32_t HPE4:1;       /* High Priority Enable */
-                  vuint32_t:1;
-                  vuint32_t:1;
-                vuint32_t HPE1:1;       /* High Priority Enable */
-                vuint32_t HPE0:1;       /* High Priority Enable */
-                  vuint32_t:6;
-                vuint32_t ARB:2;
-                vuint32_t:2;
-                vuint32_t PCTL:2;
-                vuint32_t:1;
-                vuint32_t PARK:3;
-            } B;
-        } SGPCR2;               /* Slave General Purpose Control Register 2 (RAM)@baseaddress + 0x210 */
-
-        int32_t XBAR_reserved_0214[59];     /* 0x0214 - 0x02FF */
-
-        /* Slave General Purpose Control Register 3 @baseaddress + 0x310 - not implemented */
-
-        int32_t XBAR_reserved_0300[64];     /* 0x0300 - 0x03FF */
-
-        /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */
-
-        int32_t XBAR_reserved_0400[64];     /* 0x0400 - 0x04FF */
-
-        /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */
-
-        int32_t XBAR_reserved_0500[64];     /* 0x0500 - 0x05FF */
-
-        /* Slave Port 6 not implemented @baseaddress + 0x610 */
-
-        int32_t XBAR_reserved_0600[64];     /* 0x0600 - 0x06FF */
-
-        union {
-            vuint32_t R;
-            struct {
-                  vuint32_t:1;
-                vuint32_t MSTR7:3;      /* Master 7 Priority - Reserved */
-                  vuint32_t:1;          
-                vuint32_t MSTR6:3;      /* Master 6 Priority - FlexRay */  
-                  vuint32_t:4;			/* Master 5 Priority - Not implemented */
-                  vuint32_t:1;
-                vuint32_t MSTR4:3;      /* Master 4 Priority - eDMA */
-                  vuint32_t:4;          /* Master 3 Priority - Not implemented */
-                  vuint32_t:4;          /* Master 2 Priority - Not implemented */
-                  vuint32_t:1;
-                vuint32_t MSTR1:3;      /* Master 1 Priority - e200z4 Core load/store & Nexus port  */
-                  vuint32_t:1;
-                vuint32_t MSTR0:3;      /* Master 0 Priority - e200z4 core Instruction */
-            } B;
-        } MPR7;                 /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */
-
-        int32_t XBAR_reserved_0704[3];          /* 0x0704 - 0x070F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RO:1;
-                vuint32_t HLP:1;        /* Halt Low Priority */
-                  vuint32_t:6;
-                vuint32_t HPE7:1;       /* High Priority Enable */
-                vuint32_t HPE6:1;       /* High Priority Enable */
-                  vuint32_t:1;
-                vuint32_t HPE4:1;       /* High Priority Enable */
-                  vuint32_t:1;
-                  vuint32_t:1;
-                vuint32_t HPE1:1;       /* High Priority Enable */
-                vuint32_t HPE0:1;       /* High Priority Enable */
-                  vuint32_t:6;
-                vuint32_t ARB:2;
-                vuint32_t:2;
-                vuint32_t PCTL:2;
-                vuint32_t:1;
-                vuint32_t PARK:3;
-            } B;
-        } SGPCR7;               /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */
-
-        int32_t XBAR_reserved_0714[59];         /* 0x0714 - 0x07FF */
-
-        int32_t XBAR_reserved_0800[3584];       /* 0x0800-0x3FFF */
-
-    };
-
-
-/****************************************************************************/
-/*                          MODULE : PBRIDGE Peripheral Bridge            */
-/****************************************************************************/
-
-	struct PBRIDGE_tag {
-		
-		union {                               /* Master Privilege Registers 0-7 @baseaddress + 0x00*/
-            vuint32_t R;
-			struct {
-				 vuint32_t:1;      
-				vuint32_t  MTR0:1;      /* z4 core: Master 0 Trusted for Reads */
-				vuint32_t  MTW0:1;      /* z4 core: Master 0 Trusted for Writes */
-				vuint32_t  MPL0:1;      /* z4 core: Master 0 Priviledge Level */
-				 vuint32_t:13;      
-				vuint32_t  MTR4:1;      /* DMA: Master 4 Trusted for Reads */
-				vuint32_t  MTW4:1;      /* DMA: Master 4 Trusted for Writes */
-				vuint32_t  MPL4:1;      /* DMA: Master 4 Priviledge Level */
-				 vuint32_t:5;      
-				vuint32_t  MTR6:1;      /* FlexRay: Master 6 Trusted for Reads */
-				vuint32_t  MTW6:1;      /* FlexRay: Master 6 Trusted for Writes */
-				vuint32_t  MPL6:1;      /* FlexRay: Master 6 Priviledge Level */
-				 vuint32_t:1;      
-				vuint32_t  MTR7:1;      /* EBI: Master 7 Trusted for Reads */
-				vuint32_t  MTW7:1;      /* EBI: Master 7 Trusted for Writes */
-				vuint32_t  MPL7:1;      /* EBI: Master 7 Priviledge Level */
-            } B;
-        } MPCR;
-		
-		union {                               /* Master Privilege Registers 8-15 @baseaddress + 0x04*/
-            vuint32_t R;
-			struct {
-                 vuint32_t:1;      
-				vuint32_t  MTR0:1;      /* Nexus: Master 8 Trusted for Reads */
-				vuint32_t  MTW0:1;      /* Nexus: Master 8 Trusted for Writes */
-				vuint32_t  MPL0:1;      /* Nexus: Master 8 Priviledge Level */
-				 vuint32_t:28;      
-            } B;
-        } MPCR1;
-		
-		uint32_t PRIDGE_reserved0008[6];        /* 0x0008-0x001F */
-		
-		union {                             /* Peripheral Access Conrol Registers 0-7 @baseaddress + 0x20*/
-            vuint32_t R;
-			struct {
-				 vuint32_t:5;    
-				vuint32_t  SP1:1;        /* Crossbar: Supervisor Protect */
-				vuint32_t  WP1:1;        /* Crossbar: Write Protect */
-				vuint32_t  TP1:1;        /* Crossbar: Trusted Protect */
-				 vuint32_t:9;      
-				vuint32_t  SP4:1;        /* MPU: Supervisor Protect */
-				vuint32_t  WP4:1;        /* MPU: Write Protect */
-				vuint32_t  TP4:1;        /* MPU: Trusted Protect */
-				 vuint32_t:12;  
-            } B;
-        } PACR0;
-		
-		union {                             /* Peripheral Access Conrol Registers 8-15 @baseaddress + 0x24*/
-            vuint32_t R;
-			struct {
-				vuint32_t:25;    
-				vuint32_t  SP6:1;        /* SWT: Supervisor Protect */
-				vuint32_t  WP6:1;        /* SWT: Write Protect */
-				vuint32_t  TP6:1;        /* SWT: Trusted Protect */
-				 vuint32_t:1;      
-				vuint32_t  SP7:1;        /* STM: Supervisor Protect */
-				vuint32_t  WP7:1;        /* STM: Write Protect */
-				vuint32_t  TP7:1;        /* STM: Trusted Protect */ 
-            } B;
-        } PACR1;
-		
-		union {                             /* Peripheral Access Conrol Registers 16-23 @baseaddress + 0x28*/
-            vuint32_t R;
-			struct {
-				vuint32_t:1;    
-				vuint32_t  SP0:1;        /* ECSM: Supervisor Protect */
-				vuint32_t  WP0:1;        /* ECSM: Write Protect */
-				vuint32_t  TP0:1;        /* ECSM: Trusted Protect */
-				 vuint32_t:1;      
-				vuint32_t  SP1:1;        /* DMA: Supervisor Protect */
-				vuint32_t  WP1:1;        /* DMA: Write Protect */
-				vuint32_t  TP1:1;        /* DMA: Trusted Protect */ 
-				 vuint32_t:1;      
-				vuint32_t  SP2:1;        /* INTC: Supervisor Protect */
-				vuint32_t  WP2:1;        /* INTC: Write Protect */
-				vuint32_t  TP2:1;        /* INTC: Trusted Protect */ 
-				 vuint32_t:20; 
-            } B;
-        } PACR2;
-		
-		union {                             /* Peripheral Access Conrol Registers 24-31 @baseaddress + 0x2C*/
-            vuint32_t R;
-			struct {
-				 vuint32_t:32;    
-			} B;
-        } PACR3;
-		
-		uint32_t PRIDGE_reserved0030[4];        /* 0x0030-0x003C */
-		
-		union {                             /* Off-Platform Access Control Registers 0-7 @baseaddress + 0x40*/
-            vuint32_t R;
-			struct {
-                 vuint32_t:1;      
-				vuint32_t  SP0:1;       /* eQADC: Supervisor Protect */
-				vuint32_t  WP0:1;       /* eQADC: Write Protect */
-				vuint32_t  TP0:1;       /* eQADC: Trusted Protect */
-				 vuint32_t:5; 
-				vuint32_t  SP2:1;       /* Dec Filter A: Supervisor Protect */
-				vuint32_t  WP2:1;       /* Dec Filter A: Write Protect */
-				vuint32_t  TP2:1;       /* Dec Filter A: Trusted Protect */
-				vuint32_t:1;       
-				vuint32_t  SP3:1;       /* Dec Filter B: Supervisor Protect */
-				vuint32_t  WP3:1;       /* Dec Filter B: Write Protect */
-				vuint32_t  TP3:1;       /* Dec Filter B: Trusted Protect */
-				vuint32_t:5;       
-				vuint32_t  SP5:1;       /* DSPIB: Supervisor Protect */
-				vuint32_t  WP5:1;       /* DSPIB: Write Protect */
-				vuint32_t  TP5:1;       /* DSPIB: Trusted Protect */
-				vuint32_t:1;     
-				vuint32_t  SP6:1;       /* DSPIC: Supervisor Protect */
-				vuint32_t  WP6:1;       /* DSPIC: Write Protect */
-				vuint32_t  TP6:1;       /* DSPIC: Trusted Protect */
-				vuint32_t:1; 
-				vuint32_t  SP7:1;       /* DSPID: Supervisor Protect */
-				vuint32_t  WP7:1;       /* DSPID: Write Protect */
-				vuint32_t  TP7:1;       /* DSPID: Trusted Protect */
-            } B;
-        } OPACR0;
-		
-		union {   							/* Off-Platform Access Control Registers 8-15 @baseaddress + 0x44*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:17;      
-				vuint32_t  SP4:1;      /* eSCIA: Supervisor Protect */
-				vuint32_t  WP4:1;      /* eSCIA: Write Protect */
-				vuint32_t  TP4:1;      /* eSCIA: Trusted Protect */
-				 vuint32_t:1;    
-				vuint32_t  SP5:1;      /* eSCIB: Supervisor Protect */
-				vuint32_t  WP5:1;      /* eSCIB: Write Protect */
-				vuint32_t  TP5:1;      /* eSCIB: Trusted Protect */
-				 vuint32_t:1;   
-				vuint32_t  SP6:1;      /* eSCIC: Supervisor Protect */
-				vuint32_t  WP6:1;      /* eSCIC: Write Protect */
-				vuint32_t  TP6:1;      /* eSCIC: Trusted Protect */
-				 vuint32_t:4;
-			} B;
-        } OPACR1;	 
-		   
-		union {   							/* Off-Platform Access Control Registers 16-23 @baseaddress + 0x48*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:1;      
-				vuint32_t  SP0:1;      /* FlexCANA: Supervisor Protect */
-				vuint32_t  WP0:1;      /* FlexCANA: Write Protect */
-				vuint32_t  TP0:1;      /* FlexCANA: Trusted Protect */
-				 vuint32_t:1;    
-				vuint32_t  SP1:1;      /* FlexCANB: Supervisor Protect */
-				vuint32_t  WP1:1;      /* FlexCANB: Write Protect */
-				vuint32_t  TP1:1;      /* FlexCANB: Trusted Protect */
-				 vuint32_t:1;   
-				vuint32_t  SP2:1;      /* FlexCANC: Supervisor Protect */
-				vuint32_t  WP2:1;      /* FlexCANC: Write Protect */
-				vuint32_t  TP2:1;      /* FlexCANC: Trusted Protect */
-				 vuint32_t:20;
-			} B;
-		} OPACR2;
-		   
-		union {   							/* Off-Platform Access Control Registers 24-31 @baseaddress + 0x4C*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:1;      
-				vuint32_t  SP0:1;      /* FlexRay: Supervisor Protect */
-				vuint32_t  WP0:1;      /* FlexRay: Write Protect */
-				vuint32_t  TP0:1;      /* FlexRay: Trusted Protect */
-				 vuint32_t:9;    
-				vuint32_t  SP3:1;      /* SIM: Supervisor Protect */
-				vuint32_t  WP3:1;      /* SIM: Write Protect */
-				vuint32_t  TP3:1;      /* SIM: Trusted Protect */
-				 vuint32_t:13;   
-				vuint32_t  SP7:1;      /* BAM: Supervisor Protect */
-				vuint32_t  WP7:1;      /* BAM: Write Protect */
-				vuint32_t  TP7:1;      /* BAM: Trusted Protect */
-			} B;
-		} OPACR3;
-		
-		union {   							/* Off-Platform Access Control Registers 32-39 @baseaddress + 0x50*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:32;      
-			} B;
-		} OPACR4;
-		
-		union {   							/* Off-Platform Access Control Registers 40-47 @baseaddress + 0x54*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:32;      
-			} B;
-		} OPACR5;
-		
-		union {   							/* Off-Platform Access Control Registers 48-55 @baseaddress + 0x58*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:32;      
-			} B;
-		} OPACR6;
-		
-		union {   							/* Off-Platform Access Control Registers 56-63 @baseaddress + 0x5C*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:9;  
-				vuint32_t  SP2:1;      /* CRC: Supervisor Protect */
-				vuint32_t  WP2:1;      /* CRC: Write Protect */
-				vuint32_t  TP2:1;      /* CRC: Trusted Protect */
-				 vuint32_t:20; 
-			} B;
-		} OPACR7;
-		
-		union {   							/* Off-Platform Access Control Registers 64-71 @baseaddress + 0x60*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:1;  
-				vuint32_t  SP0:1;      /* FMPLL: Supervisor Protect */
-				vuint32_t  WP0:1;      /* FMPLL: Write Protect */
-				vuint32_t  TP0:1;      /* FMPLL: Trusted Protect */
-				 vuint32_t:1;  
-				vuint32_t  SP1:1;      /* EBI: Supervisor Protect */
-				vuint32_t  WP1:1;      /* EBI: Write Protect */
-				vuint32_t  TP1:1;      /* EBI: Trusted Protect */
-				 vuint32_t:1;  
-				vuint32_t  SP2:1;      /* FlashA: Supervisor Protect */
-				vuint32_t  WP2:1;      /* FlashA: Write Protect */
-				vuint32_t  TP2:1;      /* FlashA: Trusted Protect */
-				 vuint32_t:1;  
-				vuint32_t  SP3:1;      /* FlashB: Supervisor Protect */
-				vuint32_t  WP3:1;      /* FlashB: Write Protect */
-				vuint32_t  TP3:1;      /* FlashB: Trusted Protect */
-				 vuint32_t:1;  
-				vuint32_t  SP4:1;      /* SIU: Supervisor Protect */
-				vuint32_t  WP4:1;      /* SIU: Write Protect */
-				vuint32_t  TP4:1;      /* SIU: Trusted Protect */
-				 vuint32_t:9;  
-				vuint32_t  SP7:1;      /* DTS: Supervisor Protect */
-				vuint32_t  WP7:1;      /* DTS: Write Protect */
-				vuint32_t  TP7:1;      /* DTS: Trusted Protect */
-			} B;
-		} OPACR8;
-		
-		union {   							/* Off-Platform Access Control Registers 72-79 @baseaddress + 0x64*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:1;  
-				vuint32_t  SP0:1;      /* eMIOS: Supervisor Protect */
-				vuint32_t  WP0:1;      /* eMIOS: Write Protect */
-				vuint32_t  TP0:1;      /* eMIOS: Trusted Protect */
-				 vuint32_t:25;  
-				vuint32_t  SP7:1;      /* PMC: Supervisor Protect */
-				vuint32_t  WP7:1;      /* PMC: Write Protect */
-				vuint32_t  TP7:1;      /* PMC: Trusted Protect */
-			} B;
-		} OPACR9;
-		
-		union {   							/* Off-Platform Access Control Registers 80-87 @baseaddress + 0x68*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:1;  
-				vuint32_t  SP0:1;      /* eTPU2: Supervisor Protect */
-				vuint32_t  WP0:1;      /* eTPU2: Write Protect */
-				vuint32_t  TP0:1;      /* eTPU2: Trusted Protect */
-				 vuint32_t:1;  
-				vuint32_t  SP1:1;      /* REACM: Supervisor Protect */
-				vuint32_t  WP1:1;      /* REACM: Write Protect */
-				vuint32_t  TP1:1;      /* REACM: Trusted Protect */
-				 vuint32_t:1;  
-				vuint32_t  SP2:1;      /* eTPU PRAM: Supervisor Protect */
-				vuint32_t  WP2:1;      /* eTPU PRAM: Write Protect */
-				vuint32_t  TP2:1;      /* eTPU PRAM: Trusted Protect */
-				 vuint32_t:1;  
-				vuint32_t  SP3:1;      /* eTPU PRAM mirror: Supervisor Protect */
-				vuint32_t  WP3:1;      /* eTPU PRAM mirror: Write Protect */
-				vuint32_t  TP3:1;      /* eTPU PRAM mirror: Trusted Protect */
-				 vuint32_t:1;  
-				vuint32_t  SP4:1;      /* eTPU CRAM: Supervisor Protect */
-				vuint32_t  WP4:1;      /* eTPU CRAM: Write Protect */
-				vuint32_t  TP4:1;      /* eTPU CRAM: Trusted Protect */
-				 vuint32_t:12;  
-			} B;
-		} OPACR10;
-		
-		union {   							/* Off-Platform Access Control Registers 88-95 @baseaddress + 0x6C*/
-			vuint32_t R;
-			struct {
-				 vuint32_t:17;  
-				vuint32_t  SP4:1;      /* PIT: Supervisor Protect */
-				vuint32_t  WP4:1;      /* PIT: Write Protect */
-				vuint32_t  TP4:1;      /* PIT: Trusted Protect */
-				 vuint32_t:12; 
-			} B;
-		} OPACR11;
-		
-		uint32_t PRIDGE_reserved0070[4068];        /* 0x0070-0x3FFF */
-		
-	};
-
-/****************************************************************************/
-/*                     MODULE : FLASH                                       */
-/****************************************************************************/
-
-    struct FLASH_tag {
-
-        union {                             /* Module Configuration Register @baseaddress + 0x00*/
-            vuint32_t R;
-            struct {
-                vuint32_t:5;
-                vuint32_t SIZE:3;
-                vuint32_t:1;
-                vuint32_t LAS:3;
-                vuint32_t:3;
-                vuint32_t MAS:1;
-                vuint32_t EER:1;
-                vuint32_t RWE:1;
-                vuint32_t SBC:1;
-                vuint32_t:1;
-                vuint32_t PEAS:1;
-                vuint32_t DONE:1;
-                vuint32_t PEG:1;
-                vuint32_t:4;
-                vuint32_t PGM:1;
-                vuint32_t PSUS:1;
-                vuint32_t ERS:1;
-                vuint32_t ESUS:1;
-                vuint32_t EHV:1;
-            } B;
-        } MCR;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t LME:1;
-                vuint32_t:10;
-                vuint32_t SLOCK:1;
-                vuint32_t:2;
-                vuint32_t MLOCK:2;
-                vuint32_t:6;
-                vuint32_t LLOCK:10;
-            } B;                            /* Low/Mid Address Space Block Locking Register @baseaddress + 0x04*/
-        } LMLR;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t HBE:1;
-                vuint32_t:25;
-                vuint32_t HBLOCK:6;
-            } B;
-        } HLR;                              /* High Address Space Block Locking Register @baseaddress + 0x08*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SLE:1;
-                vuint32_t:10;
-                vuint32_t SSLOCK:1;
-                vuint32_t:2;
-                vuint32_t SMLOCK:2;
-                vuint32_t:6;
-                vuint32_t SLLOCK:10;
-            } B;
-        } SLMLR;                            /* Secondary Low/Mid Block Locking Register @baseaddress + 0x0C*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t MSEL:2;
-                vuint32_t:6;
-                vuint32_t LSEL:10;
-            } B;
-        } LMSR;                             /* Low/Mid Address Space Block Select Register @baseaddress + 0x10*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:26;
-                vuint32_t HBSEL:6;
-            } B;
-        } HSR;                              /* High Address Space Block Select Register @baseaddress + 0x14*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SAD:1;
-                vuint32_t:13;
-                vuint32_t ADDR:15;
-                vuint32_t:3;
-            } B;
-        } AR;                               /* Address Register @baseaddress + 0x18*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:7;
-                vuint32_t:1;           /* Reserved */
-                vuint32_t:1;           /* EBI Testing - Reserved */
-                vuint32_t M6PFE:1;     /* FlexRay  */
-                vuint32_t:1;           /* Reserved */
-                vuint32_t M4PFE:1;     /* eDMA     */
-                vuint32_t:1;           /* Reserved */
-                vuint32_t:1;           /* Reserved */
-                vuint32_t M1PFE:1;     /* z4 Core Load/Store  */
-                vuint32_t M0PFE:1;     /* z4 Core Instruction */
-                vuint32_t APC:3;
-                vuint32_t WWSC:2;
-                vuint32_t RWSC:3;
-                vuint32_t:1;
-                vuint32_t DPFEN:1;
-                vuint32_t:1;
-                vuint32_t IPFEN:1;
-                vuint32_t:1;
-                vuint32_t PFLIM:2;
-                vuint32_t BFEN:1;
-            } B;
-        } BIUCR;                            /* Bus Interface Unit Configuration Register 1 @baseaddress + 0x1C*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t:2;          /* Reserved */
-                vuint32_t:2;          /* EBI Testing - Reserved */
-                vuint32_t M6AP:2;     /* FlexRay  */
-                vuint32_t:2;          /* Reserved */
-                vuint32_t M4AP:2;     /* eDMA_A   */
-                vuint32_t:2;          /* Reserved */
-                vuint32_t:2;          /* Reserved */
-                vuint32_t M1AP:2;     /* z4 Core Load/Store  */
-                vuint32_t M0AP:2;     /* z4 Core Instruction */
-            } B;
-        } BIUAPR;                           /*Bus Interface Unit Access Protection Register @baseaddress + 0x20*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t LBCFG:2;
-                vuint32_t:30;
-            } B;
-        } BIUCR2;                           /* Bus Interface Unit Configuration Register 2 @baseaddress + 0x24*/
-
-        uint32_t FLASH_reserved0028[5];  /* 0x0028-0x003B */
-        
-        union {                 /* User Test 0 (UT0) register@baseaddress + 0x3C */
-            vuint32_t R;
-            struct {
-                vuint32_t UTE:1;        /* User test enable (Read/Clear) */
-                vuint32_t SBCE:1;       /* Single bit correction enable (Read/Clear) */
-                  vuint32_t:6;  /* Reserved */
-                vuint32_t DSI:8;        /* Data syndrome input (Read/Write) */
-                  vuint32_t:9;  /* Reserved */
-                  vuint32_t:1;  /* Reserved (Read/Write) */
-                vuint32_t MRE:1;        /* Margin Read Enable (Read/Write) */
-                vuint32_t MRV:1;        /* Margin Read Value (Read/Write) */
-                vuint32_t EIE:1;        /* ECC data Input Enable (Read/Write) */
-                vuint32_t AIS:1;        /* Array Integrity Sequence (Read/Write) */
-                vuint32_t AIE:1;        /* Array Integrity Enable (Read/Write) */
-                vuint32_t AID:1;        /* Array Integrity Done (Read Only) */
-            } B;
-        } UT0;
-
-        union {                 /* User Test 1 (UT1) register@baseaddress + 0x40 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;       /* Data Array Input (Read/Write) */
-            } B;
-        } UT1;
-
-        union {                 /* User Test 2 (UT2) register@baseaddress + 0x44 */
-            vuint32_t R;
-            struct {
-                vuint32_t DAI:32;       /* Data Array Input (Read/Write) */
-            } B;
-        } UT2;
-
-        union {                 /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */
-            vuint32_t R;
-            struct {
-                vuint32_t MS:32;        /* Multiple input Signature (Read/Write) */
-            } B;
-        } UMISR[5];
-        
-        uint32_t FLASH_reserved005C[4073];  /* 0x005C-0x3FFF */
-    };
-
-    
-    
-
-/****************************************************************************/
-/*                     MODULE : EBI                                         */
-/****************************************************************************/
-    struct CS_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BA:17;
-                vuint32_t:3;
-                vuint32_t PS:1;
-                vuint32_t:3;
-                vuint32_t AD_MUX:1;
-                vuint32_t BL:1;
-                vuint32_t WEBS:1;
-                vuint32_t TBDIP:1;
-                vuint32_t:1;
-                vuint32_t SETA:1;
-                vuint32_t BI:1;
-                vuint32_t V:1;
-            } B;
-        } BR;                           /* EBI Base Registers (BR) @baseaddress + 0x10 - 0x28 */
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t AM:17;
-                vuint32_t:7;
-                vuint32_t SCY:4;
-                vuint32_t:1;
-                vuint32_t BSCY:2;
-                vuint32_t:1;
-            } B;
-        } OR;                           /* EBI Option Registers (OR) @baseaddress + 0x14 - 0x2C */
-    };
-    struct CAL_CS_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BA:17;
-                vuint32_t:3;
-                vuint32_t PS:1;
-                vuint32_t:3;
-                vuint32_t AD_MUX:1;
-                vuint32_t BL:1;
-                vuint32_t WEBS:1;
-                vuint32_t TBDIP:1;
-                vuint32_t:1;
-                vuint32_t SETA:1;
-                vuint32_t BI:1;	
-                vuint32_t V:1;
-            } B;
-        } BR;                           /* EBI CAL Base Registers (CAL_BR) @baseaddress + 0x40 - 0x58 */
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t AM:17;
-                vuint32_t:7;
-                vuint32_t SCY:4;
-                vuint32_t:1;
-                vuint32_t BSCY:2;
-                vuint32_t:1;
-
-            } B;
-        } OR;                           /* EBI CAL Option Registers (CAL_OR) @baseaddress + 0x44 - 0x5C */
-    };
-
-
-    struct EBI_tag {
-        union {
-            vuint32_t R;
-            struct {
-                 vuint32_t:16;
-                vuint32_t ACGE:1;
-                 vuint32_t:8;
-                vuint32_t MDIS:1;
-                 vuint32_t:3;
-                vuint32_t D16_31:1;
-                vuint32_t AD_MUX:1;
-                vuint32_t DBM:1;
-            } B;
-        } MCR;                          /* EBI Module Configuration Register (MCR) @baseaddress + 0x00 */
-        
-		uint32_t EBI_reserved0004[1];   /* 0x0004-0x0008 */
-        
-		union {
-            vuint32_t R;
-            struct {
-                 vuint32_t:31;
-                vuint32_t BMTF:1;
-            } B;
-        } TESR;                         /* EBI Transfer Error Status Register (TESR) @baseaddress + 0x08 */
-        
-		union {
-            vuint32_t R;
-            struct {
-                 vuint32_t:16;
-                vuint32_t BMT:8;
-                vuint32_t BME:1;
-                  vuint32_t:7;
-            } B;
-        } BMCR;                         /* EBI Bus Montior Control Register (BMCR) @baseaddress + 0x0C */
-
-        struct CS_tag CS[4];            /* EBI CS Registers (BR / OR) @baseaddress + 0x10 - 0x2C */
-
-        uint32_t EBI_reserved0030[4];   /* 0x0030 - 0x003C */
-
-        struct CAL_CS_tag CAL_CS[4];    /* EBI CAL_CS Registers (CAL_BR / CAL_OR) @baseaddress + 0x40 - 0x5C */
-    };
-
-
-/****************************************************************************/
-/*                     MODULE : INTC                                      */
-/****************************************************************************/
-    struct INTC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:18;   /* Reserved */
-                  vuint32_t:1;  /* Reserved */
-                  vuint32_t:4;  /* Reserved */
-                  vuint32_t:1;  /* Reserved */
-                  vuint32_t:2;  /* Reserved */
-                vuint32_t VTES:1;       /* Vector Table Entry Size */
-                  vuint32_t:4;  /* Reserved */
-                vuint32_t HVEN:1;       /* Hardware Vector Enable */
-            } B;
-        } MCR;                  /* INTC Module Configuration Register (MCR) @baseaddress + 0x00 */
-
-        int32_t INTC_Reserved_0004[1];     /* 0x0004 - 0x0007 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;   /* Reserved */
-                vuint32_t PRI:4;        /* Priority */
-            } B;
-        } CPR;                  /* INTC Current Priority Register (CPR) @baseaddress + 0x08 */
-
-        int32_t INTC_reserved_000C;        /* 0x000C - 0x000F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t VTBA:21;      /* Vector Table Base Address */
-                vuint32_t INTVEC:9;     /* Interrupt Vector */
-                  vuint32_t:2;          /* Reserved */
-            } B;
-        } IACKR;                /* INTC Interrupt Acknowledge Register (IACKR) @baseaddress + 0x10 */
-
-        int32_t INTC_Reserved_0014;       /* 0x0014 - 0x00017 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:32;   /* Reserved */
-            } B;
-        } EOIR;                 /* INTC End of Interrupt Register (EOIR) @baseaddress + 0x18 */
-
-        int32_t INTC_Reserved_001C;       /* 0x001C - 0x001F */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:6;     /* Reserved */
-                vuint8_t SET:1; /* Set Flag bits */
-                vuint8_t CLR:1; /* Clear Flag bits */
-            } B;
-        } SSCIR[8];             /* INTC Software Set/Clear Interrupt Registers (SSCIR) @baseaddress + 0x20 */
-
-        int32_t INTC_Reserved_0028[6];     /* 0x0028 - 0x003F */
-
-        union {
-            vuint8_t R;
-            struct {
-                  vuint8_t:2;   /* Reserved */
-                  vuint8_t:2;   /* Reserved */
-                vuint8_t PRI:4; /* Priority Select */
-            } B;
-        } PSR[512];             /* INTC Priority Select Registers (PSR) @baseaddress + 0x40 */
-
-    };
-
-
-/****************************************************************************/
-/*                     MODULE : SIU                                      */
-/****************************************************************************/
-    struct SIU_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t S_F:1;                /* Identifies the Manufacturer */
-                vuint32_t FLASH_SIZE_1:4;       /* Define major Flash memory size (see Table 15-4 for details) */
-                vuint32_t FLASH_SIZE_2:4;       /* Define Flash memory size, small granularity  */
-                vuint32_t TEMP_RANGE:2;         /* Define maximum operating range  */
-                  vuint32_t:1;                  /* Reserved for future enhancements */
-                vuint32_t MAX_FREQ:2;           /* Define maximum device speed  */
-                  vuint32_t:1;                  /* Reserved for future enhancements */
-                vuint32_t SUPPLY:1;             /* Defines if the part is 5V or 3V  */
-                vuint32_t PART_NUMBER:8;        /* Contain the ASCII representation of the character that indicates the product  */
-                vuint32_t TBD:1;                /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */
-                  vuint32_t:2;                  /* Reserved for future enhancements */
-                vuint32_t EE:1;                 /* Indicates if Data Flash is present */
-                  vuint32_t:3;                  /* Reserved for future enhancements */
-                vuint32_t FR:1;                 /* Indicates if Data FlexRay is present */
-            } B;
-        } MIDR2;                /* MCU ID Register 2  @baseaddress + 0x0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PARTNUM:16;   /* Device part number */
-                vuint32_t CSP:1;        /* CSP configuration */
-                vuint32_t PKG:5;        /* Indicate the package the die is mounted in. */
-                  vuint32_t:2;          /* Reserved */
-                vuint32_t MASKNUM:8;    /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */
-            } B;
-        } MIDR;                 /* MCU ID Register (MIDR) @baseaddress + 0x4 */
-
-        int32_t SIU_Reserved_0008;     /* 0x0008 - 0x000B */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PORS:1;       /*  Power-On Reset Status */
-                vuint32_t ERS:1;        /*  External Reset Status */
-                vuint32_t LLRS:1;       /*  Loss of Lock Reset Status */
-                vuint32_t LCRS:1;       /*  Loss of Clock Reset Status */
-                vuint32_t WDRS:1;       /*  Watchdog Timer/Debug Reset Status */
-                vuint32_t :1;
-                vuint32_t SWTRS:1;      /*  Software Watchdog Timer Reset Status */
-                  vuint32_t:7;
-                vuint32_t SSRS:1;       /*  Software System Reset Status */
-                vuint32_t SERF:1;       /*  Software External Reset Flag */
-                vuint32_t WKPCFG:1;     /*  Weak Pull Configuration Pin Status */
-                  vuint32_t:11;
-                vuint32_t ABR:1;        /*  Auto Baud Rate */
-                vuint32_t BOOTCFG:2;    /*  Reset Configuration Pin Status  */
-                vuint32_t RGF:1;        /*  RESET Glitch Flag */
-            } B;
-        } RSR;                  /* Reset Status Register (SIU_RSR) @baseaddress + 0xC */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SSR:1;        /*  Software System Reset */
-                vuint32_t SER:1;        /*  Software External Reset */
-                  vuint32_t:14;
-                  vuint32_t:1;
-                  vuint32_t:15;
-            } B;
-        } SRCR;                 /* System Reset Control Register (SRCR) @baseaddress + 0x10 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NMI:1;        /* Non-Maskable Interrupt Flag */
-                  vuint32_t:7;  /*  */
-                vuint32_t SWT:1;        /* Software Watch Dog Timer Interrupt Flag, from platform */
-                  vuint32_t:7;  /*  */
-                vuint32_t EIF15:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF14:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF13:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF12:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF11:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF10:1;      /* External Interrupt Request Flag x */
-                vuint32_t EIF9:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF8:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF7:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF6:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF5:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF4:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF3:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF2:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF1:1;       /* External Interrupt Request Flag x */
-                vuint32_t EIF0:1;       /* External Interrupt Request Flag x */
-            } B;
-        } EISR;                 /* SIU External Interrupt Status Register (EISR) @baseaddress + 0x14 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NMI_SEL:1;    /* NMI Interrupt Platform Input Selection */
-                  vuint32_t:7;
-                vuint32_t NMISEL0:1;    /* SWT Interrupt Platform Input Selection */
-                  vuint32_t:7;
-                vuint32_t EIRE15:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE14:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE13:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE12:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE11:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE10:1;     /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE9:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE8:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE7:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE6:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE5:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE4:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE3:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE2:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE1:1;      /* External DMA/Interrupt Request Enable x */
-                vuint32_t EIRE0:1;      /* External DMA/Interrupt Request Enable x */
-            } B;
-        } DIRER;                /* DMA/Interrupt Request Enable Register (DIRER) @baseaddress + 0x18 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;   /*  */
-                vuint32_t DIRS3:1;      /* DMA/Interrupt Request Select x */
-                vuint32_t DIRS2:1;      /* DMA/Interrupt Request Select x */
-                vuint32_t DIRS1:1;      /* DMA/Interrupt Request Select x */
-                vuint32_t DIRS0:1;      /* DMA/Interrupt Request Select x */
-            } B;
-        } DIRSR;                /* DMA/Interrupt Request Select Register (DIRSR) @baseaddress + 0x1C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;   /*  */
-                vuint32_t OVF15:1;      /* Overrun Flag x */
-                vuint32_t OVF14:1;      /* Overrun Flag x */
-                vuint32_t OVF13:1;      /* Overrun Flag x */
-                vuint32_t OVF12:1;      /* Overrun Flag x */
-                vuint32_t OVF11:1;      /* Overrun Flag x */
-                vuint32_t OVF10:1;      /* Overrun Flag x */
-                vuint32_t OVF9:1;       /* Overrun Flag x */
-                vuint32_t OVF8:1;       /* Overrun Flag x */
-                vuint32_t OVF7:1;       /* Overrun Flag x */
-                vuint32_t OVF6:1;       /* Overrun Flag x */
-                vuint32_t OVF5:1;       /* Overrun Flag x */
-                vuint32_t OVF4:1;       /* Overrun Flag x */
-                vuint32_t OVF3:1;       /* Overrun Flag x */
-                vuint32_t OVF2:1;       /* Overrun Flag x */
-                vuint32_t OVF1:1;       /* Overrun Flag x */
-                vuint32_t OVF0:1;       /* Overrun Flag x */
-            } B;
-        } OSR;                  /* Overrun Status Register (OSR) @baseaddress + 0x20 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t ORE15:1;      /* Overrun Request Enable x */
-                vuint32_t ORE14:1;      /* Overrun Request Enable x */
-                vuint32_t ORE13:1;      /* Overrun Request Enable x */
-                vuint32_t ORE12:1;      /* Overrun Request Enable x */
-                vuint32_t ORE11:1;      /* Overrun Request Enable x */
-                vuint32_t ORE10:1;      /* Overrun Request Enable x */
-                vuint32_t ORE9:1;       /* Overrun Request Enable x */
-                vuint32_t ORE8:1;       /* Overrun Request Enable x */
-                vuint32_t ORE7:1;       /* Overrun Request Enable x */
-                vuint32_t ORE6:1;       /* Overrun Request Enable x */
-                vuint32_t ORE5:1;       /* Overrun Request Enable x */
-                vuint32_t ORE4:1;       /* Overrun Request Enable x */
-                vuint32_t ORE3:1;       /* Overrun Request Enable x */
-                vuint32_t ORE2:1;       /* Overrun Request Enable x */
-                vuint32_t ORE1:1;       /* Overrun Request Enable x */
-                vuint32_t ORE0:1;       /* Overrun Request Enable x */
-            } B;
-        } ORER;                 /* Overrun Request Enable Register (ORER) @baseaddress + 0x24 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NMIRE:1;      /* NMI Rising-Edge Event Enable x  */
-                 vuint32_t:7; 
-				vuint32_t NMIRE0:1;     /* NMI Falling-Edge Event Enable (SWT) x */
-                 vuint32_t:7; 
-				vuint32_t IREE15:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE14:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE13:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE12:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE11:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE10:1;     /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE9:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE8:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE7:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE6:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE5:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE4:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE3:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE2:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE1:1;      /* IRQ Rising-Edge Event Enable x */
-                vuint32_t IREE0:1;      /* IRQ Rising-Edge Event Enable x */
-            } B;
-        } IREER;                /* External IRQ Rising-Edge Event Enable Register (IREER)  @baseaddress + 0x28 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NMIFE:1;      /* NMI Falling-Edge Event Enable (NMI Input) x */
-                 vuint32_t:7; 
-				vuint32_t NMIFE0:1;     /* NMI Falling-Edge Event Enable (SWT) x */
-                 vuint32_t:7; 
-				vuint32_t IFEE15:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE14:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE13:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE12:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE11:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE10:1;     /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE9:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE8:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE7:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE6:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE5:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE4:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE3:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE2:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE1:1;      /* IRQ Falling-Edge Event Enable x */
-                vuint32_t IFEE0:1;      /* IRQ Falling-Edge Event Enable x */
-            } B;
-        } IFEER;                /* External IRQ Falling-Edge Event Enable Regi (IFEER) @baseaddress + 0x2C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t DFL:4;        /* Digital Filter Length */
-            } B;
-        } IDFR;                 /* External IRQ Digital Filter Register (IDFR) @baseaddress + 0x30 */
-
-        int32_t SIU_Reserved_0034[3];      /* 0x0034 - 0x003F */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t PA:3;
-                vuint16_t OBE:1;
-                vuint16_t IBE:1;
-                vuint16_t DSC:2;
-                vuint16_t ODE:1;
-                vuint16_t HYS:1;
-                vuint16_t SRC:2;
-                vuint16_t WPE:1;
-                vuint16_t WPS:1;
-            } B;
-        } PCR[512];             /* Pad Configuration Register  (PCR) @baseaddress + 0x40 */
-
-        int32_t SIU_Reserved_0374[112];    /* 0x0374 - 0x05FF */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:7;
-                vuint8_t PDO:1;
-            } B;
-        } GPDO[512];            /* GPIO Pin Data Output Register (GPDO) @baseaddress + 0x600 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:7;
-                vuint8_t PDI:1;
-            } B;
-        } GPDI[256];            /* GPIO Pin Data Input Register (GDPI) @baseaddress + 0x800 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TSEL5:2;      /* eQADC Trigger 5 Input */
-                vuint32_t TSEL4:2;      /* eQADC Trigger 4 Input */
-                vuint32_t TSEL3:2;      /* eQADC Trigger 3 Input */
-                vuint32_t TSEL2:2;      /* eQADC Trigger 4 Input */
-                vuint32_t TSEL1:2;      /* eQADC Trigger 1 Input */
-                vuint32_t TSEL0:2;      /* eQADC Trigger 0 Input */
-                  vuint32_t:20; /*  */
-            } B;
-        } ETISR;                /* eQADC Trigger Input Select Register (ETISR) @baseaddress + 0x900 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ESEL15:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL14:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL13:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL12:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL11:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL10:2;     /* External IRQ Input Select x */
-                vuint32_t ESEL9:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL8:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL7:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL6:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL5:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL4:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL3:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL2:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL1:2;      /* External IRQ Input Select x */
-                vuint32_t ESEL0:2;      /* External IRQ Input Select x */
-            } B;
-        } EIISR;                /* External IRQ Input Select Register (EIISR) @baseaddress + 0x904 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t SINSELB:2;    /* DSPI_B Data Input Select  */
-                vuint32_t SSSELB:2;     /* DSPI_B Slave Select Input Select */
-                vuint32_t SCKSELB:2;    /* DSPI_B Clock Input Select */
-                vuint32_t TRIGSELB:2;   /* DSPI_B Trigger Input Select */
-                vuint32_t SINSELC:2;    /* DSPI_C Data Input Select */
-                vuint32_t SSSELC:2;     /* DSPI_C Slave Select Input Select */
-                vuint32_t SCKSELC:2;    /* DSPI_C Clock Input Select */
-                vuint32_t TRIGSELC:2;   /* DSPI_C Trigger Input Select  */
-                vuint32_t SINSELD:2;    /* DSPI_D Data Input Select */
-                vuint32_t SSSELD:2;     /* DSPI_D Slave Select Input Select */
-                vuint32_t SCKSELD:2;    /* DSPI_D Clock Input Select */
-                vuint32_t TRIGSELD:2;   /* DSPI_D Trigger Input Select  */
-            } B;
-        } DISR;                 /* DSPI Input Select Register (DISR) @baseaddress + 0x908 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:2;    /*  */
-                vuint32_t ETSEL5:5;     /* eQADC queue X Enhanced Trigger Selection */
-                vuint32_t ETSEL4:5;     /* eQADC queue X Enhanced Trigger Selection */
-                vuint32_t ETSEL3:5;     /* eQADC queue X Enhanced Trigger Selection */
-                vuint32_t ETSEL2:5;     /* eQADC queue X Enhanced Trigger Selection */
-                vuint32_t ETSEL1:5;     /* eQADC queue X Enhanced Trigger Selection */
-                vuint32_t ETSEL0:5;     /* eQADC queue X Enhanced Trigger Selection */
-            } B;
-        } ISEL3;                /* MUX Select Register 3 (ISEL3) @baseaddress + 0x90C */
-
-        int32_t SIU_Reserved_0910[4];      /* 0x0910 - 0x091F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:11;
-                vuint32_t ESEL5:1;
-                  vuint32_t:3;
-                vuint32_t ESEL4:1;
-                  vuint32_t:3;
-                vuint32_t ESEL3:1;
-                  vuint32_t:3;
-                vuint32_t ESEL2:1;
-                  vuint32_t:3;
-                vuint32_t ESEL1:1;
-                  vuint32_t:3;
-                vuint32_t ESEL0:1;
-            } B;
-        } ISEL8;                /* MUX Select Register 8 (ISEL8) @baseaddress + 0x920 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:27;
-                vuint32_t ETSEL0A:5;
-            } B;
-        } ISEL9;                /* MUX Select Register 9(ISEL9) @baseaddress + 0x924 */
-
-        int32_t SIU_Reserved_0928[22];     /* 0x0928 - 0x097F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t MATCH:1;      /*  Compare Register Match */
-                vuint32_t DISNEX:1;     /*  Disable Nexus */
-                  vuint32_t:14;
-                vuint32_t CRSE:1;       /*  Calibration Reflection Suppression Enable */
-                  vuint32_t:1;
-            } B;
-        } CCR;                  /* Chip Configuration Register (CCR) @baseaddress + 0x980 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:18;
-                vuint32_t ENGDIV:6;
-                vuint32_t ENGSSE:1;
-                  vuint32_t:3;
-                vuint32_t EBTS:1;
-                  vuint32_t:1;
-                vuint32_t EBDF:2;
-            } B;
-        } ECCR;                 /* External Clock Control Register (ECCR) @baseaddress + 0x984 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CMPAH:32;
-            } B;
-        } CARH;                 /* Compare A High Register (CARH) @baseaddress + 0x988 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CMPAL:32;
-            } B;
-        } CARL;                 /* Compare A Low Register (CARL) @baseaddress + 0x98C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CMPBH:32;
-            } B;
-        } CBRH;                 /* Compare B High Register (CBRH) @baseaddress + 0x990 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CMPBL:32;
-            } B;
-        } CBRL;                 /* Compare B Low Register (CBRL) @baseaddress + 0x994 */
-
-        int32_t SIU_Reserved_0998[2];      /* 0x0998 - 0x099F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:15;
-                vuint32_t CAN_SRC:1;    /* CAN 2:1 Mode */
-                vuint32_t:11;
-                vuint32_t BYPASS:1;     /* Bypass bit  */
-                vuint32_t SYSCLKDIV:2;  /* System Clock Divide */
-                  vuint32_t:2;
-            } B;
-        } SYSDIV;               /* System Clock Register (SYSDIV) @baseaddress + 0x9A0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CPUSTP:1;     /* CPU stop request. When asserted, a stop request is sent to the following modules: */
-                  vuint32_t:2;  /* Reserved */
-                  vuint32_t:1;
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t TPUSTP:1;     /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */
-                vuint32_t NPCSTP:1;     /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */
-                vuint32_t EBISTP:1;     /* EBI stop request. When asserted, a stop request is sent to the external bus */
-                vuint32_t ADCSTP:1;     /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t MIOSSTP:1;    /* Stop mode request */
-                vuint32_t DFILSTP:1;    /* Decimation filter stop request. When asserted, a stop request is sent to the */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t PITSTP:1;     /* PIT stop request. When asserted, a stop request is sent to the periodical internal */
-                  vuint32_t:3;  /* Reserved */
-                vuint32_t CNCSTP:1;     /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */
-                vuint32_t CNBSTP:1;     /* FlexCAN B stop request. When asserted, a stop request is sent to the FlexCAN B */
-                vuint32_t CNASTP:1;     /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */
-                vuint32_t SPIDSTP:1;    /* DSPI D stop request. When asserted, a stop request is sent to the DSPI D. */
-                vuint32_t SPICSTP:1;    /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */
-                vuint32_t SPIBSTP:1;    /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */
-                  vuint32_t:6;  /* Reserved */
-                vuint32_t SCICSTP:1;    /* eSCI C stop request. When asserted, a stop request is sent to the eSCI C module. */
-                vuint32_t SCIBSTP:1;    /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */
-                vuint32_t SCIASTP:1;    /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */
-            } B;
-        } HLT;                  /* Halt Register (HLT) @baseaddress + 0x9A4 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CPUACK:1;     /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                  vuint32_t:2;  /* Reserved */
-                  vuint32_t:1;
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t TPUACK:1;     /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t NPCACK:1;     /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t EBIACK:1;     /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t ADCACK:1;     /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t MIOSACK:1;    /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t DFILACK:1;    /* Decimation filter stop acknowledge. When asserted, indicates that a stop */
-                  vuint32_t:1;  /* Reserved */
-                vuint32_t PITACK:1;     /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                  vuint32_t:3;  /* Reserved */
-                vuint32_t CNCACK:1;     /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */
-                vuint32_t CNBACK:1;     /* FlexCAN B stop acknowledge. When asserted, indicates that a stop acknowledge */
-                vuint32_t CNAACK:1;     /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */
-                vuint32_t SPIDACK:1;    /* DSPI D stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t SPICACK:1;    /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                vuint32_t SPIBACK:1;    /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */
-                  vuint32_t:6;  /* Reserved */
-                vuint32_t SCICACK:1;    /* eSCI C stop acknowledge */
-                vuint32_t SCIBACK:1;    /* eSCI B stop acknowledge */
-                vuint32_t SCIAACK:1;    /* eSCI A stop acknowledge. */
-            } B;
-        } HLTACK;               /* Halt Acknowledge Register (HLTACK) @baseaddress + 0x9A8 */
-
-        int32_t SIU_reserved09AC[2];       /* 0x09AC - 0x09B0 */
-		
-		 union {
-            vuint32_t R;
-            struct {
-				vuint32_t EXT_PID_EN:1;     /* External PID Selection Enable */
-                vuint32_t EXT_PID_SYNC0:1;  /* External PID Synchronization 0 */
-                 vuint32_t:28;              /* Reserved */
-				vuint32_t EXT_PID6:1;       /* EXT_PID6 */
-                vuint32_t EXT_PID7:1;       /* EXT_PID7 */
-			} B;
-		} EMPCR0;				/* Core MMU PID Control Register (EMPCR0) @baseaddress + 0x9B4 */
-		
-		int32_t SIU_reserved09B8[19];       /* 0x09B8 - 0x09B0 */
-		
-    };
-
-/****************************************************************************/
-/*                     MODULE : FMPLL                                       */
-/****************************************************************************/
-    struct FMPLL_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:1;
-                vuint32_t PREDIV:3;
-                vuint32_t MFD:5;
-                  vuint32_t:1;
-                vuint32_t RFD:3;
-                vuint32_t LOCEN:1;
-                vuint32_t LOLRE:1;
-                vuint32_t LOCRE:1;
-                  vuint32_t:1;
-                vuint32_t LOLIRQ:1;
-                vuint32_t LOCIRQ:1;
-                  vuint32_t:13;
-            } B;
-        } SYNCR;                /* Synthesizer Control Register (SYNCR) @baseaddress + 0x0000 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:22;
-                vuint32_t LOLF:1;
-                vuint32_t LOC:1;
-                vuint32_t MODE:1;
-                vuint32_t PLLSEL:1;
-                vuint32_t PLLREF:1;
-                vuint32_t LOCKS:1;
-                vuint32_t LOCK:1;
-                vuint32_t LOCF:1;
-                  vuint32_t:2;
-            } B;
-        } SYNSR;                /* Synthesizer Status Register (SYNSR) @baseaddress + 0x0004 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t EMODE:1;
-                vuint32_t CLKCFG:3;
-                  vuint32_t:8;
-                vuint32_t EPREDIV:4;
-                  vuint32_t:9;
-                vuint32_t EMFD:7;
-            } B;
-        } ESYNCR1;              /* Enhanced Synthesizer Control Register 1 (ESYNCR1) @baseaddress + 0x0008 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t LOCEN:1;
-                vuint32_t LOLRE:1;
-                vuint32_t LOCRE:1;
-                vuint32_t LOLIRQ:1;
-                vuint32_t LOCIRQ:1;
-                  vuint32_t:17;
-                vuint32_t ERFD:2;
-            } B;
-        } ESYNCR2;              /* Enhanced Synthesizer Control Register 2 (ESYNCR2) @baseaddress + 0x000C */
-
-        int32_t FMPLL_reserved0010[2];      /* 0x0010-0x0017 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BSY:1;
-                vuint32_t MODEN:1;
-                vuint32_t MODSEL:1;
-                vuint32_t MODPERIOD:13;
-                  vuint32_t:1;
-                vuint32_t INCSTEP:15;
-            } B;
-        } SYNFMMR;              /* Synthesizer FM Modulation Register (SYNFMMR) @baseaddress + 0x0018 */
-    };
-
-
-/****************************************************************************/
-/*                     MODULE : ECSM                                       */
-/****************************************************************************/
-    struct ECSM_tag {
-
-        union {                /* Processor core type */
-            vuint16_t R;
-        } PCT;
-        
-        union {                /* Platform revision */
-            vuint16_t R;
-        } REV;
-        
-        union {                /* AXBS Master Configuration */
-            vuint16_t R;
-        } AMC;
-        
-        union {                /* AXBS Slave Configuration */
-            vuint16_t R;
-        } ASC;
-        
-        union {                 /* IPS Module Configuration */
-            vuint32_t R;
-        } IMC;
-        
-        uint8_t ECSM_reserved000C[3];  /* 0x000C-0x000E */
-        
-        union {                 /* Miscellaneous Reset Status Register */
-            vuint8_t R;
-            struct {
-                vuint8_t POR:1;
-                vuint8_t DIR:1;
-                vuint8_t SWTR:1;
-                 vuint8_t:5;
-            } B;
-        } MRSR;
-
-        uint8_t ECSM_reserved0010[3];   /* 0x0010-0x0012 */
-        
-        union {                         /* Miscellaneous Wakeup Control */
-            vuint8_t R;
-            struct {
-                vuint8_t ENBWCR:1;
-                 vuint8_t:3;
-                vuint8_t PRILVL:4;
-            } B;
-        } MWCR;
-                
-        uint32_t ecsm_reserved0014[4];  /* 0x0014 - 0x0023 */
-        
-        union {                         /* Miscellaneous User Defined Control */
-            vuint32_t R;
-            struct {
-                 vuint32_t:1;
-                vuint32_t SWSC:1;
-                 vuint32_t:30;
-            } B;
-        } MUDCR;
-
-        uint32_t ecsm_reserved0028[6];      /* 0x0028 - 0x003C*/
-        
-        uint8_t ecsm_reserved0040[3];       /* 0x0040 - 0x0042*/
-
-        union {
-            vuint8_t R;
-            struct {
-                 vuint8_t:2;
-				vuint8_t ER1BR:1;
-                vuint8_t EF1BR:1;
-                 vuint8_t:2;
-                vuint8_t ERNCR:1;
-                vuint8_t EFNCR:1;
-            } B;
-        } ECR;                  /* ECC Configuration Register @baseaddress + 0x43 */
-
-        uint8_t ecsm_reserved0044[3];      /* 0x0044 - 0x0046*/
-
-        union {
-            vuint8_t R;
-            struct {
-                 vuint8_t:2;
-				vuint8_t R1BC:1;
-                vuint8_t F1BC:1;
-                 vuint8_t:2;
-				vuint8_t RNCE:1;
-                vuint8_t FNCE:1;
-            } B;
-        } ESR;                  /* ECC Status Register @baseaddress + 0x47 */
-
-        uint8_t ecsm_reserved0048[2];      /* 0x0048 - 0x0049*/
-        
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t FRCAP:1;
-                vuint16_t:1;
-                vuint16_t FRC1BI:1;
-                vuint16_t FR11BI:1;
-                vuint16_t:2;
-                vuint16_t FRCNCI:1;
-                vuint16_t FR1NCI:1;
-                vuint16_t:1;
-                vuint16_t ERRBIT:7;
-            } B;
-        } EEGR;                 /* ECC Error Generation Register @baseaddress + 0x4A */
-        
-        uint32_t ecsm_reserved004C;      /* 0x004C - 0x004F*/
-                
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FEAR:32;
-            } B;
-        } FEAR;                 /* Flash ECC Address Register @baseaddress + 0x50 */
-
-        uint16_t ecsm_reserved0054;          /* 0x0054 - 0x0055*/
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t FEMR:4;
-            } B;
-        } FEMR;                 /* Flash ECC Master Register @baseaddress + 0x56 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t WRITE:1;
-                vuint8_t SIZE:3;
-                vuint8_t PROT0:1;
-                vuint8_t PROT1:1;
-                vuint8_t PROT2:1;
-                vuint8_t PROT3:1;
-            } B;
-        } FEAT;                 /* Flash ECC Attributes Register @baseaddress + 0x57 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FEDH:32;
-            } B;
-        } FEDRH;                /* Flash ECC Data High Register @baseaddress + 0x58 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FEDL:32;
-            } B;
-        } FEDRL;                /* Flash ECC Data Low Register @baseaddress + 0x5C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t REAR:32;
-            } B;
-        } REAR;                 /* RAM ECC Address @baseaddress + 0x60 */
-
-        uint8_t ecsm_reserved0064;          /* 0x0064 - 0x0065*/
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t PRESR:8;
-            } B;
-        } PRESR;                /* RAM ECC Syndrome @baseaddress + 0x65 */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t:4;
-                vuint8_t REMR:4;
-            } B;
-        } REMR;                 /* RAM ECC Master @baseaddress + 0x66  */
-
-        union {
-            vuint8_t R;
-            struct {
-                vuint8_t WRITE:1;
-                vuint8_t SIZE:3;
-                vuint8_t PROT0:1;
-                vuint8_t PROT1:1;
-                vuint8_t PROT2:1;
-                vuint8_t PROT3:1;
-            } B;
-        } REAT;                 /*  RAM ECC Attributes Register @baseaddress + 0x67 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t REDH:32;
-            } B;
-        } REDRH;                /* RAM ECC Data High Register @baseaddress + 0x68 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t REDL:32;
-            } B;
-        } REDRL;                /* RAMECC Data Low Register @baseaddress + 0x6C */
-
-    };
-
-/****************************************************************************/
-/*                     MODULE : System Timer Module (STM)                   */
-/****************************************************************************/
-    struct STM_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t CPS:8;
-                  vuint32_t:6;
-                vuint32_t FRZ:1;
-                vuint32_t TEN:1;
-            } B;
-        } CR;                   /* STM Control Register @baseaddress + 0x0000 */
-
-        union {
-            vuint32_t R;
-        } CNT;                  /* STM Count Register @baseaddress + 0x0004 */
-
-        uint32_t stm_reserved0008[2];      /* 0x0008 - 0x000F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR0;                 /* STM Channel Control Register @baseaddress + 0x0010 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR0;                 /* STM Channel Interrupt Register @baseaddress + 0x0014 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CMP;
-            } B;
-        } CMP0;                 /* STM Channel Compare Register @baseaddress + 0x0018 */
-
-        uint32_t stm_reserved001C; /* 0x001C - 0x001F*/
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR1;                 /* STM Channel Control Register @baseaddress + 0x0020 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR1;                 /* STM Channel Interrupt Register @baseaddress + 0x0024 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CMP;
-            } B;
-        } CMP1;                 /* STM Channel Compare Register @baseaddress + 0x0028 */
-
-        uint32_t stm_reserved002C; /* 0x002C - 0x002F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR2;                 /* STM Channel Control Register @baseaddress + 0x0030 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR2;                 /* STM Channel Interrupt Register @baseaddress + 0x0034 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CMP;
-            } B;
-        } CMP2;                 /* STM Channel Compare Register @baseaddress + 0x0038 */
-
-        uint32_t stm_reserved003C; /* 0x003C - 0x003F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CEN:1;
-            } B;
-        } CCR3;                 /* STM Channel Control Register @baseaddress + 0x0040 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t CIF:1;
-            } B;
-        } CIR3;                 /* STM Channel Interrupt Register @baseaddress + 0x0044 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CMP;
-            } B;
-        } CMP3;                 /* STM Channel Compare Register @baseaddress + 0x0048 */
-
-        uint32_t stm_reserved004C; /* 0x004C - 0x004F */
-    };
-
-
-/****************************************************************************/
-/*                     MODULE : SWT                                         */
-/****************************************************************************/
-
-    struct SWT_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MAP0:1;
-                vuint32_t MAP1:1;
-                vuint32_t MAP2:1;
-                vuint32_t MAP3:1;
-                vuint32_t MAP4:1;
-                vuint32_t MAP5:1;
-                vuint32_t MAP6:1;
-                vuint32_t MAP7:1;
-                  vuint32_t:14;
-                vuint32_t KEY:1;
-                vuint32_t RIA:1;
-                vuint32_t WND:1;
-                vuint32_t ITR:1;
-                vuint32_t HLK:1;
-                vuint32_t SLK:1;
-                vuint32_t CSL:1;
-                vuint32_t STP:1;
-                vuint32_t FRZ:1;
-                vuint32_t WEN:1;
-            } B;
-        } MCR;                  /* Module Configuration Register @baseaddress + 0x00 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:31;
-                vuint32_t TIF:1;
-            } B;
-        } IR;                   /* Interrupt register @baseaddress + 0x04 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WTO:32;
-            } B;
-        } TO;                   /* Timeout register @baseaddress + 0x08 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WST:32;
-
-            } B;
-        } WN;                   /* Window register @baseaddress + 0x0C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t WSC:16;
-            } B;
-        } SR;                   /* Service register @baseaddress + 0x10 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CNT:32;
-            } B;
-        } CO;                   /* Counter output register @baseaddress + 0x14 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t SK:16;
-            } B;
-        } SK;                   /* Service key register @baseaddress + 0x18 */
-    };
-
-/****************************************************************************/
-/*                     MODULE : EMIOS                                      */
-/****************************************************************************/
-    struct EMIOS_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DOZEEN:1;
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-                vuint32_t GTBE:1;
-                vuint32_t ETB:1;
-                vuint32_t GPREN:1;
-                vuint32_t:6;
-                vuint32_t SRV:4;
-                vuint32_t GPRE:8;
-                vuint32_t:8;
-            } B;
-        } MCR;                  /* Module Configuration Register @baseaddress + 0x00 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t F23:1;
-                vuint32_t F22:1;
-                vuint32_t F21:1;
-                vuint32_t F20:1;
-                vuint32_t F19:1;
-                vuint32_t F18:1;
-                vuint32_t F17:1;
-                vuint32_t F16:1;
-                vuint32_t F15:1;
-                vuint32_t F14:1;
-                vuint32_t F13:1;
-                vuint32_t F12:1;
-                vuint32_t F11:1;
-                vuint32_t F10:1;
-                vuint32_t F9:1;
-                vuint32_t F8:1;
-                vuint32_t F7:1;
-                vuint32_t F6:1;
-                vuint32_t F5:1;
-                vuint32_t F4:1;
-                vuint32_t F3:1;
-                vuint32_t F2:1;
-                vuint32_t F1:1;
-                vuint32_t F0:1;
-            } B;
-        } GFR;                  /* Global FLAG Register @baseaddress + 0x04 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t OU23:1;
-                vuint32_t OU22:1;
-                vuint32_t OU21:1;
-                vuint32_t OU20:1;
-                vuint32_t OU19:1;
-                vuint32_t OU18:1;
-                vuint32_t OU17:1;
-                vuint32_t OU16:1;
-                vuint32_t OU15:1;
-                vuint32_t OU14:1;
-                vuint32_t OU13:1;
-                vuint32_t OU12:1;
-                vuint32_t OU11:1;
-                vuint32_t OU10:1;
-                vuint32_t OU9:1;
-                vuint32_t OU8:1;
-                vuint32_t OU7:1;
-                vuint32_t OU6:1;
-                vuint32_t OU5:1;
-                vuint32_t OU4:1;
-                vuint32_t OU3:1;
-                vuint32_t OU2:1;
-                vuint32_t OU1:1;
-                vuint32_t OU0:1;
-            } B;
-        } OUDR;                 /* Output Update Disable Register @baseaddress + 0x08 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;    /*  */
-                vuint32_t CHDIS23:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS22:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS21:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS20:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS19:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS18:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS17:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS16:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS15:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS14:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS13:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS12:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS11:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS10:1;    /* Enable Channel [n] bit */
-                vuint32_t CHDIS9:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS8:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS7:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS6:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS5:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS4:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS3:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS2:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS1:1;     /* Enable Channel [n] bit */
-                vuint32_t CHDIS0:1;     /* Enable Channel [n] bit */
-            } B;
-        } UCDIS;                /* Disable Channel (EMIOSUCDIS) @baseaddress + 0x0C */
-
-        int32_t EMIOS_Reserved_0010[4];    /* 0x0010 - 0x001F */
-
-        struct {
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t A;
-                }B;
-            } CADR;             /* Channel A Data Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t B;
-                }B;
-            } CBDR;             /* Channel B Data Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t C;
-                }B;
-            } CCNTR;            /* Channel Counter Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t FREN:1;
-                    vuint32_t ODIS:1;
-                    vuint32_t ODISSL:2;
-                    vuint32_t UCPRE:2;
-                    vuint32_t UCPREN:1;
-                    vuint32_t DMA:1;
-                    vuint32_t:1;
-                    vuint32_t IF:4;
-                    vuint32_t FCK:1;
-                    vuint32_t FEN:1;
-                    vuint32_t:3;
-                    vuint32_t FORCMA:1;
-                    vuint32_t FORCMB:1;
-                    vuint32_t:1;
-                    vuint32_t BSL:2;
-                    vuint32_t EDSEL:1;
-                    vuint32_t EDPOL:1;
-                    vuint32_t MODE:7;
-                } B;
-            } CCR;              /* Channel Control Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t OVR:1;
-                      vuint32_t:15;
-                    vuint32_t OVFL:1;
-                      vuint32_t:12;
-                    vuint32_t UCIN:1;
-                    vuint32_t UCOUT:1;
-                    vuint32_t FLAG:1;
-                } B;
-            } CSR;              /* Channel Status Register */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t ALTA;
-                } B;
-            } ALTA;             /* Alternate Channel A Data Register */
-
-            uint32_t emios_channel_reserved[2];
-
-        } CH[24];
-
-    };
-
-/****************************************************************************/
-/*                     MODULE : ETPU                                      */
-/****************************************************************************/
-    struct ETPU_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t GEC:1;        /*  Global Exception Clear  */
-                vuint32_t SDMERR:1;     /*  */
-                vuint32_t WDTOA:1;      /*  */
-                vuint32_t WDTOB:1;      /*  */
-                vuint32_t MGE1:1;       /* */
-                vuint32_t MGE2:1;       /* */
-                vuint32_t ILF1:1;       /* Invalid instruction flag eTPU A.  */
-                vuint32_t ILF2:1;       /* Invalid instruction flag eTPU B.  */
-                vuint32_t SCMERR:1;     /* . */
-                  vuint32_t:2;  /*  */
-                vuint32_t SCMSIZE:5;    /*  Shared Code Memory size  */
-                  vuint32_t:4;  /*  */
-                vuint32_t SCMMISC:1;    /*  SCM MISC Flag  */
-                vuint32_t SCMMISF:1;    /*  SCM MISC Flag  */
-                vuint32_t SCMMISEN:1;   /*  SCM MISC Enable  */
-                  vuint32_t:2;  /*  */
-                vuint32_t VIS:1;        /*  SCM Visability  */
-                  vuint32_t:5;  /*  */
-                vuint32_t GTBE:1;       /*  Global Time Base Enable  */
-            } B;
-        } MCR;                  /* eTPU module configuration register@baseaddress + 0x00 */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t STS:1;        /*  Start Status bit  */
-                vuint32_t CTBASE:5;     /*  Channel Transfer Base  */
-                vuint32_t PBASE:10;     /*  Parameter Buffer Base Address */
-                vuint32_t PWIDTH:1;     /*  Parameter Width  */
-                vuint32_t PARAM0:7;     /*  Channel Parameter 0  */
-                vuint32_t WR:1; /*  */
-                vuint32_t PARAM1:7;     /*  Channel Parameter 1  */
-            } B;
-        } CDCR;                 /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */
-
-        vuint32_t ETPU_reserved_0008;   /* 0x0008 - 0x000B */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ETPUMISCCMP:32;       /* Expected multiple input signature calculator compare register value.  */
-            } B;
-        } MISCCMPR;             /* eTPU MISC Compare Register@baseaddress + 0x0c */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ETPUSCMOFFDATA:32;    /* SCM Off-range read data value. */
-            } B;
-        } SCMOFFDATAR;          /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t FEND:1;       /*  Force END  */
-                vuint32_t MDIS:1;       /*  Low power Stop  */
-                  vuint32_t:1;  /*  */
-                vuint32_t STF:1;        /*  Stop Flag  */
-                  vuint32_t:4;  /*  */
-                vuint32_t HLTF:1;       /*  Halt Mode Flag  */
-                  vuint32_t:3;  /*  */
-                vuint32_t FCSS:1;
-                vuint32_t FPSCK:3;      /*  Filter Prescaler Clock Control  */
-                vuint32_t CDFC:2;       /*  */
-                  vuint32_t:1;  /*  */
-                vuint32_t ERBA:5;       /*  */
-                vuint32_t SPPDIS:1;     /*  */
-                  vuint32_t:2;  /*  */
-                vuint32_t ETB:5;        /*  Entry Table Base  */
-            } B;
-        } ECR_A;               /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */
-
-        vuint32_t ETPU_reserved_0018[2];        /* 0x0018 - 0x001B */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCR2CTL:3;    /*  TCR2 Clock/Gate Control  */
-                vuint32_t TCRCF:2;      /*  TCRCLK Signal Filter Control  */
-                vuint32_t AM:2; /*  Angle Mode  */
-                  vuint32_t:3;  /*  */
-                vuint32_t TCR2P:6;      /*  TCR2 Prescaler Control  */
-                vuint32_t TCR1CTL:2;    /*  TCR1 Clock/Gate Control  */
-                vuint32_t TCR1CS:1;     /*  */
-                  vuint32_t:5;  /*  */
-                vuint32_t TCR1P:8;      /*  TCR1 Prescaler Control  */
-            } B;
-        } TBCR_A;                       /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */
-
-        /* offset 0x0024 */
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;    /*  */
-                vuint32_t TCR1:24;      /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */
-            } B;
-        } TB1R_A;                /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */
-
-        /* offset 0x0028 */
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;    /*  */
-                vuint32_t TCR2:24;      /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */
-            } B;
-        } TB2R_A;               /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t REN1:1;       /*  Resource Enable TCR1  */
-                vuint32_t RSC1:1;       /*  Resource Control TCR1  */
-                  vuint32_t:2;  /*  */
-                vuint32_t SERVER_ID1:4; /*  */
-                  vuint32_t:4;  /*  */
-                vuint32_t SRV1:4;       /*  Resource Server Slot  */
-                vuint32_t REN2:1;       /*  Resource Enable TCR2  */
-                vuint32_t RSC2:1;       /*  Resource Control TCR2  */
-                  vuint32_t:2;  /*  */
-                vuint32_t SERVER_ID2:4; /*  */
-                  vuint32_t:4;  /*  */
-                vuint32_t SRV2:4;       /*  Resource Server Slot  */
-            } B;
-        } REDCR_A;                 /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */
-
-        vuint32_t ETPU_reserved_0030[12];       /* 0x0030 - 0x005F */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WDM:2;
-                  vuint32_t:14;
-                vuint32_t WDCNT:16;
-            } B;
-        } WDTR_A;                 /* ETPU1 WDTR Register @baseaddress + 0x60 */
-
-        vuint32_t ETPU1_reserved_0064;  /* 0x0064 - 0x0067 */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t IDLE_CNT:31;
-                vuint32_t ICLR:1;
-            } B;
-        } IDLE_A;                  /* ETPU1 IDLE Register @baseaddress + 0x68 */
-
-        vuint32_t ETPU_reserved_006C[101];      /* 0x006C - 0x01FF */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CIS31:1;      /*  Channel 31 Interrut Status  */
-                vuint32_t CIS30:1;      /*  Channel 30 Interrut Status  */
-                vuint32_t CIS29:1;      /*  Channel 29 Interrut Status  */
-                vuint32_t CIS28:1;      /*  Channel 28 Interrut Status  */
-                vuint32_t CIS27:1;      /*  Channel 27 Interrut Status  */
-                vuint32_t CIS26:1;      /*  Channel 26 Interrut Status  */
-                vuint32_t CIS25:1;      /*  Channel 25 Interrut Status  */
-                vuint32_t CIS24:1;      /*  Channel 24 Interrut Status  */
-                vuint32_t CIS23:1;      /*  Channel 23 Interrut Status  */
-                vuint32_t CIS22:1;      /*  Channel 22 Interrut Status  */
-                vuint32_t CIS21:1;      /*  Channel 21 Interrut Status  */
-                vuint32_t CIS20:1;      /*  Channel 20 Interrut Status  */
-                vuint32_t CIS19:1;      /*  Channel 19 Interrut Status  */
-                vuint32_t CIS18:1;      /*  Channel 18 Interrut Status  */
-                vuint32_t CIS17:1;      /*  Channel 17 Interrut Status  */
-                vuint32_t CIS16:1;      /*  Channel 16 Interrut Status  */
-                vuint32_t CIS15:1;      /*  Channel 15 Interrut Status  */
-                vuint32_t CIS14:1;      /*  Channel 14 Interrut Status  */
-                vuint32_t CIS13:1;      /*  Channel 13 Interrut Status  */
-                vuint32_t CIS12:1;      /*  Channel 12 Interrut Status  */
-                vuint32_t CIS11:1;      /*  Channel 11 Interrut Status  */
-                vuint32_t CIS10:1;      /*  Channel 10 Interrut Status  */
-                vuint32_t CIS9:1;       /*  Channel 9 Interrut Status  */
-                vuint32_t CIS8:1;       /*  Channel 8 Interrut Status  */
-                vuint32_t CIS7:1;       /*  Channel 7 Interrut Status  */
-                vuint32_t CIS6:1;       /*  Channel 6 Interrut Status  */
-                vuint32_t CIS5:1;       /*  Channel 5 Interrut Status  */
-                vuint32_t CIS4:1;       /*  Channel 4 Interrut Status  */
-                vuint32_t CIS3:1;       /*  Channel 3 Interrut Status  */
-                vuint32_t CIS2:1;       /*  Channel 2 Interrut Status  */
-                vuint32_t CIS1:1;       /*  Channel 1 Interrut Status  */
-                vuint32_t CIS0:1;       /*  Channel 0 Interrut Status  */
-            } B;
-        } CISR_A;               /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */
-
-        int32_t ETPU_reserved_0204[3];      /* 0x0204 - 0x20F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DTRS31:1;     /*  Channel 31 Data Transfer Request Status  */
-                vuint32_t DTRS30:1;     /*  Channel 30 Data Transfer Request Status  */
-                vuint32_t DTRS29:1;     /*  Channel 29 Data Transfer Request Status  */
-                vuint32_t DTRS28:1;     /*  Channel 28 Data Transfer Request Status  */
-                vuint32_t DTRS27:1;     /*  Channel 27 Data Transfer Request Status  */
-                vuint32_t DTRS26:1;     /*  Channel 26 Data Transfer Request Status  */
-                vuint32_t DTRS25:1;     /*  Channel 25 Data Transfer Request Status  */
-                vuint32_t DTRS24:1;     /*  Channel 24 Data Transfer Request Status  */
-                vuint32_t DTRS23:1;     /*  Channel 23 Data Transfer Request Status  */
-                vuint32_t DTRS22:1;     /*  Channel 22 Data Transfer Request Status  */
-                vuint32_t DTRS21:1;     /*  Channel 21 Data Transfer Request Status  */
-                vuint32_t DTRS20:1;     /*  Channel 20 Data Transfer Request Status  */
-                vuint32_t DTRS19:1;     /*  Channel 19 Data Transfer Request Status  */
-                vuint32_t DTRS18:1;     /*  Channel 18 Data Transfer Request Status  */
-                vuint32_t DTRS17:1;     /*  Channel 17 Data Transfer Request Status  */
-                vuint32_t DTRS16:1;     /*  Channel 16 Data Transfer Request Status  */
-                vuint32_t DTRS15:1;     /*  Channel 15 Data Transfer Request Status  */
-                vuint32_t DTRS14:1;     /*  Channel 14 Data Transfer Request Status  */
-                vuint32_t DTRS13:1;     /*  Channel 13 Data Transfer Request Status  */
-                vuint32_t DTRS12:1;     /*  Channel 12 Data Transfer Request Status  */
-                vuint32_t DTRS11:1;     /*  Channel 11 Data Transfer Request Status  */
-                vuint32_t DTRS10:1;     /*  Channel 10 Data Transfer Request Status  */
-                vuint32_t DTRS9:1;      /*  Channel 9 Data Transfer Request Status  */
-                vuint32_t DTRS8:1;      /*  Channel 8 Data Transfer Request Status  */
-                vuint32_t DTRS7:1;      /*  Channel 7 Data Transfer Request Status  */
-                vuint32_t DTRS6:1;      /*  Channel 6 Data Transfer Request Status  */
-                vuint32_t DTRS5:1;      /*  Channel 5 Data Transfer Request Status  */
-                vuint32_t DTRS4:1;      /*  Channel 4 Data Transfer Request Status  */
-                vuint32_t DTRS3:1;      /*  Channel 3 Data Transfer Request Status  */
-                vuint32_t DTRS2:1;      /*  Channel 2 Data Transfer Request Status  */
-                vuint32_t DTRS1:1;      /*  Channel 1 Data Transfer Request Status  */
-                vuint32_t DTRS0:1;      /*  Channel 0 Data Transfer Request Status  */
-            } B;
-        } CDTRSR_A;             /* eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR) @baseaddress + 0x210 */
-
-        int32_t ETPU_reserved_0214[3];      /* 0x0214 - 0x021F */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CIOS31:1;     /*  Channel 31 Interruput Overflow Status  */
-                vuint32_t CIOS30:1;     /*  Channel 30 Interruput Overflow Status  */
-                vuint32_t CIOS29:1;     /*  Channel 29 Interruput Overflow Status  */
-                vuint32_t CIOS28:1;     /*  Channel 28 Interruput Overflow Status  */
-                vuint32_t CIOS27:1;     /*  Channel 27 Interruput Overflow Status  */
-                vuint32_t CIOS26:1;     /*  Channel 26 Interruput Overflow Status  */
-                vuint32_t CIOS25:1;     /*  Channel 25 Interruput Overflow Status  */
-                vuint32_t CIOS24:1;     /*  Channel 24 Interruput Overflow Status  */
-                vuint32_t CIOS23:1;     /*  Channel 23 Interruput Overflow Status  */
-                vuint32_t CIOS22:1;     /*  Channel 22 Interruput Overflow Status  */
-                vuint32_t CIOS21:1;     /*  Channel 21 Interruput Overflow Status  */
-                vuint32_t CIOS20:1;     /*  Channel 20 Interruput Overflow Status  */
-                vuint32_t CIOS19:1;     /*  Channel 19 Interruput Overflow Status  */
-                vuint32_t CIOS18:1;     /*  Channel 18 Interruput Overflow Status  */
-                vuint32_t CIOS17:1;     /*  Channel 17 Interruput Overflow Status  */
-                vuint32_t CIOS16:1;     /*  Channel 16 Interruput Overflow Status  */
-                vuint32_t CIOS15:1;     /*  Channel 15 Interruput Overflow Status  */
-                vuint32_t CIOS14:1;     /*  Channel 14 Interruput Overflow Status  */
-                vuint32_t CIOS13:1;     /*  Channel 13 Interruput Overflow Status  */
-                vuint32_t CIOS12:1;     /*  Channel 12 Interruput Overflow Status  */
-                vuint32_t CIOS11:1;     /*  Channel 11 Interruput Overflow Status  */
-                vuint32_t CIOS10:1;     /*  Channel 10 Interruput Overflow Status  */
-                vuint32_t CIOS9:1;      /*  Channel 9 Interruput Overflow Status  */
-                vuint32_t CIOS8:1;      /*  Channel 8 Interruput Overflow Status  */
-                vuint32_t CIOS7:1;      /*  Channel 7 Interruput Overflow Status  */
-                vuint32_t CIOS6:1;      /*  Channel 6 Interruput Overflow Status  */
-                vuint32_t CIOS5:1;      /*  Channel 5 Interruput Overflow Status  */
-                vuint32_t CIOS4:1;      /*  Channel 4 Interruput Overflow Status  */
-                vuint32_t CIOS3:1;      /*  Channel 3 Interruput Overflow Status  */
-                vuint32_t CIOS2:1;      /*  Channel 2 Interruput Overflow Status  */
-                vuint32_t CIOS1:1;      /*  Channel 1 Interruput Overflow Status  */
-                vuint32_t CIOS0:1;      /*  Channel 0 Interruput Overflow Status  */
-            } B;
-        } CIOSR_A;              /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */
-
-        int32_t ETPU_reserved_0224[3];      /* 0x0224 - 0x022F */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DTROS31:1;    /*  Channel 31 Data Transfer Overflow Status  */
-                vuint32_t DTROS30:1;    /*  Channel 30 Data Transfer Overflow Status  */
-                vuint32_t DTROS29:1;    /*  Channel 29 Data Transfer Overflow Status  */
-                vuint32_t DTROS28:1;    /*  Channel 28 Data Transfer Overflow Status  */
-                vuint32_t DTROS27:1;    /*  Channel 27 Data Transfer Overflow Status  */
-                vuint32_t DTROS26:1;    /*  Channel 26 Data Transfer Overflow Status  */
-                vuint32_t DTROS25:1;    /*  Channel 25 Data Transfer Overflow Status  */
-                vuint32_t DTROS24:1;    /*  Channel 24 Data Transfer Overflow Status  */
-                vuint32_t DTROS23:1;    /*  Channel 23 Data Transfer Overflow Status  */
-                vuint32_t DTROS22:1;    /*  Channel 22 Data Transfer Overflow Status  */
-                vuint32_t DTROS21:1;    /*  Channel 21 Data Transfer Overflow Status  */
-                vuint32_t DTROS20:1;    /*  Channel 20 Data Transfer Overflow Status  */
-                vuint32_t DTROS19:1;    /*  Channel 19 Data Transfer Overflow Status  */
-                vuint32_t DTROS18:1;    /*  Channel 18 Data Transfer Overflow Status  */
-                vuint32_t DTROS17:1;    /*  Channel 17 Data Transfer Overflow Status  */
-                vuint32_t DTROS16:1;    /*  Channel 16 Data Transfer Overflow Status  */
-                vuint32_t DTROS15:1;    /*  Channel 15 Data Transfer Overflow Status  */
-                vuint32_t DTROS14:1;    /*  Channel 14 Data Transfer Overflow Status  */
-                vuint32_t DTROS13:1;    /*  Channel 13 Data Transfer Overflow Status  */
-                vuint32_t DTROS12:1;    /*  Channel 12 Data Transfer Overflow Status  */
-                vuint32_t DTROS11:1;    /*  Channel 11 Data Transfer Overflow Status  */
-                vuint32_t DTROS10:1;    /*  Channel 10 Data Transfer Overflow Status  */
-                vuint32_t DTROS9:1;     /*  Channel 9 Data Transfer Overflow Status  */
-                vuint32_t DTROS8:1;     /*  Channel 8 Data Transfer Overflow Status  */
-                vuint32_t DTROS7:1;     /*  Channel 7 Data Transfer Overflow Status  */
-                vuint32_t DTROS6:1;     /*  Channel 6 Data Transfer Overflow Status  */
-                vuint32_t DTROS5:1;     /*  Channel 5 Data Transfer Overflow Status  */
-                vuint32_t DTROS4:1;     /*  Channel 4 Data Transfer Overflow Status  */
-                vuint32_t DTROS3:1;     /*  Channel 3 Data Transfer Overflow Status  */
-                vuint32_t DTROS2:1;     /*  Channel 2 Data Transfer Overflow Status  */
-                vuint32_t DTROS1:1;     /*  Channel 1 Data Transfer Overflow Status  */
-                vuint32_t DTROS0:1;     /*  Channel 0 Data Transfer Overflow Status  */
-            } B;
-        } CDTROSR_A;            /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */
-
-        int32_t ETPU_reserved_0234[3];      /* 0x0234 - 0x023F */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CIE31:1;      /*  Channel 31 Interruput Enable  */
-                vuint32_t CIE30:1;      /*  Channel 30 Interruput Enable  */
-                vuint32_t CIE29:1;      /*  Channel 29 Interruput Enable  */
-                vuint32_t CIE28:1;      /*  Channel 28 Interruput Enable  */
-                vuint32_t CIE27:1;      /*  Channel 27 Interruput Enable  */
-                vuint32_t CIE26:1;      /*  Channel 26 Interruput Enable  */
-                vuint32_t CIE25:1;      /*  Channel 25 Interruput Enable  */
-                vuint32_t CIE24:1;      /*  Channel 24 Interruput Enable  */
-                vuint32_t CIE23:1;      /*  Channel 23 Interruput Enable  */
-                vuint32_t CIE22:1;      /*  Channel 22 Interruput Enable  */
-                vuint32_t CIE21:1;      /*  Channel 21 Interruput Enable  */
-                vuint32_t CIE20:1;      /*  Channel 20 Interruput Enable  */
-                vuint32_t CIE19:1;      /*  Channel 19 Interruput Enable  */
-                vuint32_t CIE18:1;      /*  Channel 18 Interruput Enable  */
-                vuint32_t CIE17:1;      /*  Channel 17 Interruput Enable  */
-                vuint32_t CIE16:1;      /*  Channel 16 Interruput Enable  */
-                vuint32_t CIE15:1;      /*  Channel 15 Interruput Enable  */
-                vuint32_t CIE14:1;      /*  Channel 14 Interruput Enable  */
-                vuint32_t CIE13:1;      /*  Channel 13 Interruput Enable  */
-                vuint32_t CIE12:1;      /*  Channel 12 Interruput Enable  */
-                vuint32_t CIE11:1;      /*  Channel 11 Interruput Enable  */
-                vuint32_t CIE10:1;      /*  Channel 10 Interruput Enable  */
-                vuint32_t CIE9:1;       /*  Channel 9 Interruput Enable  */
-                vuint32_t CIE8:1;       /*  Channel 8 Interruput Enable  */
-                vuint32_t CIE7:1;       /*  Channel 7 Interruput Enable  */
-                vuint32_t CIE6:1;       /*  Channel 6 Interruput Enable  */
-                vuint32_t CIE5:1;       /*  Channel 5 Interruput Enable  */
-                vuint32_t CIE4:1;       /*  Channel 4 Interruput Enable  */
-                vuint32_t CIE3:1;       /*  Channel 3 Interruput Enable  */
-                vuint32_t CIE2:1;       /*  Channel 2 Interruput Enable  */
-                vuint32_t CIE1:1;       /*  Channel 1 Interruput Enable  */
-                vuint32_t CIE0:1;       /*  Channel 0 Interruput Enable  */
-            } B;
-        } CIER_A;               /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */
-
-        int32_t ETPU_reserved_0244[3];      /* 0x0244 - 0x25F */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DTRE31:1;     /*  Channel 31 Data Transfer Request Enable  */
-                vuint32_t DTRE30:1;     /*  Channel 30 Data Transfer Request Enable  */
-                vuint32_t DTRE29:1;     /*  Channel 29 Data Transfer Request Enable  */
-                vuint32_t DTRE28:1;     /*  Channel 28 Data Transfer Request Enable  */
-                vuint32_t DTRE27:1;     /*  Channel 27 Data Transfer Request Enable  */
-                vuint32_t DTRE26:1;     /*  Channel 26 Data Transfer Request Enable  */
-                vuint32_t DTRE25:1;     /*  Channel 25 Data Transfer Request Enable  */
-                vuint32_t DTRE24:1;     /*  Channel 24 Data Transfer Request Enable  */
-                vuint32_t DTRE23:1;     /*  Channel 23 Data Transfer Request Enable  */
-                vuint32_t DTRE22:1;     /*  Channel 22 Data Transfer Request Enable  */
-                vuint32_t DTRE21:1;     /*  Channel 21 Data Transfer Request Enable  */
-                vuint32_t DTRE20:1;     /*  Channel 20 Data Transfer Request Enable  */
-                vuint32_t DTRE19:1;     /*  Channel 19 Data Transfer Request Enable  */
-                vuint32_t DTRE18:1;     /*  Channel 18 Data Transfer Request Enable  */
-                vuint32_t DTRE17:1;     /*  Channel 17 Data Transfer Request Enable  */
-                vuint32_t DTRE16:1;     /*  Channel 16 Data Transfer Request Enable  */
-                vuint32_t DTRE15:1;     /*  Channel 15 Data Transfer Request Enable  */
-                vuint32_t DTRE14:1;     /*  Channel 14 Data Transfer Request Enable  */
-                vuint32_t DTRE13:1;     /*  Channel 13 Data Transfer Request Enable  */
-                vuint32_t DTRE12:1;     /*  Channel 12 Data Transfer Request Enable  */
-                vuint32_t DTRE11:1;     /*  Channel 11 Data Transfer Request Enable  */
-                vuint32_t DTRE10:1;     /*  Channel 10 Data Transfer Request Enable  */
-                vuint32_t DTRE9:1;      /*  Channel 9 Data Transfer Request Enable  */
-                vuint32_t DTRE8:1;      /*  Channel 8 Data Transfer Request Enable  */
-                vuint32_t DTRE7:1;      /*  Channel 7 Data Transfer Request Enable  */
-                vuint32_t DTRE6:1;      /*  Channel 6 Data Transfer Request Enable  */
-                vuint32_t DTRE5:1;      /*  Channel 5 Data Transfer Request Enable  */
-                vuint32_t DTRE4:1;      /*  Channel 4 Data Transfer Request Enable  */
-                vuint32_t DTRE3:1;      /*  Channel 3 Data Transfer Request Enable  */
-                vuint32_t DTRE2:1;      /*  Channel 2 Data Transfer Request Enable  */
-                vuint32_t DTRE1:1;      /*  Channel 1 Data Transfer Request Enable  */
-                vuint32_t DTRE0:1;      /*  Channel 0 Data Transfer Request Enable  */
-            } B;
-        } CDTRER_A;             /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */
-
-        int32_t ETPU_reserved_0254[3];      /* 0x0254 - 0x025F */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t WDS31:1;      /*  Channel 31 Data Transfer Request Enable  */
-                vuint32_t WDS30:1;      /*  Channel 30 Data Transfer Request Enable  */
-                vuint32_t WDS29:1;      /*  Channel 29 Data Transfer Request Enable  */
-                vuint32_t WDS28:1;      /*  Channel 28 Data Transfer Request Enable  */
-                vuint32_t WDS27:1;      /*  Channel 27 Data Transfer Request Enable  */
-                vuint32_t WDS26:1;      /*  Channel 26 Data Transfer Request Enable  */
-                vuint32_t WDS25:1;      /*  Channel 25 Data Transfer Request Enable  */
-                vuint32_t WDS24:1;      /*  Channel 24 Data Transfer Request Enable  */
-                vuint32_t WDS23:1;      /*  Channel 23 Data Transfer Request Enable  */
-                vuint32_t WDS22:1;      /*  Channel 22 Data Transfer Request Enable  */
-                vuint32_t WDS21:1;      /*  Channel 21 Data Transfer Request Enable  */
-                vuint32_t WDS20:1;      /*  Channel 20 Data Transfer Request Enable  */
-                vuint32_t WDS19:1;      /*  Channel 19 Data Transfer Request Enable  */
-                vuint32_t WDS18:1;      /*  Channel 18 Data Transfer Request Enable  */
-                vuint32_t WDS17:1;      /*  Channel 17 Data Transfer Request Enable  */
-                vuint32_t WDS16:1;      /*  Channel 16 Data Transfer Request Enable  */
-                vuint32_t WDS15:1;      /*  Channel 15 Data Transfer Request Enable  */
-                vuint32_t WDS14:1;      /*  Channel 14 Data Transfer Request Enable  */
-                vuint32_t WDS13:1;      /*  Channel 13 Data Transfer Request Enable  */
-                vuint32_t WDS12:1;      /*  Channel 12 Data Transfer Request Enable  */
-                vuint32_t WDS11:1;      /*  Channel 11 Data Transfer Request Enable  */
-                vuint32_t WDS10:1;      /*  Channel 10 Data Transfer Request Enable  */
-                vuint32_t WDS9:1;       /*  Channel 9 Data Transfer Request Enable  */
-                vuint32_t WDS8:1;       /*  Channel 8 Data Transfer Request Enable  */
-                vuint32_t WDS7:1;       /*  Channel 7 Data Transfer Request Enable  */
-                vuint32_t WDS6:1;       /*  Channel 6 Data Transfer Request Enable  */
-                vuint32_t WDS5:1;       /*  Channel 5 Data Transfer Request Enable  */
-                vuint32_t WDS4:1;       /*  Channel 4 Data Transfer Request Enable  */
-                vuint32_t WDS3:1;       /*  Channel 3 Data Transfer Request Enable  */
-                vuint32_t WDS2:1;       /*  Channel 2 Data Transfer Request Enable  */
-                vuint32_t WDS1:1;       /*  Channel 1 Data Transfer Request Enable  */
-                vuint32_t WDS0:1;       /*  Channel 0 Data Transfer Request Enable  */
-            } B;
-        } WDSR_A;              /* ETPUWDSR - eTPU Watchdog Status Register @baseaddress + 0x260 */
-
-        int32_t ETPU_reserved_0264[7];      /* 0x0264 - 0x027F */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SR31:1;       /*  Channel 31 Data Transfer Request Enable  */
-                vuint32_t SR30:1;       /*  Channel 30 Data Transfer Request Enable  */
-                vuint32_t SR29:1;       /*  Channel 29 Data Transfer Request Enable  */
-                vuint32_t SR28:1;       /*  Channel 28 Data Transfer Request Enable  */
-                vuint32_t SR27:1;       /*  Channel 27 Data Transfer Request Enable  */
-                vuint32_t SR26:1;       /*  Channel 26 Data Transfer Request Enable  */
-                vuint32_t SR25:1;       /*  Channel 25 Data Transfer Request Enable  */
-                vuint32_t SR24:1;       /*  Channel 24 Data Transfer Request Enable  */
-                vuint32_t SR23:1;       /*  Channel 23 Data Transfer Request Enable  */
-                vuint32_t SR22:1;       /*  Channel 22 Data Transfer Request Enable  */
-                vuint32_t SR21:1;       /*  Channel 21 Data Transfer Request Enable  */
-                vuint32_t SR20:1;       /*  Channel 20 Data Transfer Request Enable  */
-                vuint32_t SR19:1;       /*  Channel 19 Data Transfer Request Enable  */
-                vuint32_t SR18:1;       /*  Channel 18 Data Transfer Request Enable  */
-                vuint32_t SR17:1;       /*  Channel 17 Data Transfer Request Enable  */
-                vuint32_t SR16:1;       /*  Channel 16 Data Transfer Request Enable  */
-                vuint32_t SR15:1;       /*  Channel 15 Data Transfer Request Enable  */
-                vuint32_t SR14:1;       /*  Channel 14 Data Transfer Request Enable  */
-                vuint32_t SR13:1;       /*  Channel 13 Data Transfer Request Enable  */
-                vuint32_t SR12:1;       /*  Channel 12 Data Transfer Request Enable  */
-                vuint32_t SR11:1;       /*  Channel 11 Data Transfer Request Enable  */
-                vuint32_t SR10:1;       /*  Channel 10 Data Transfer Request Enable  */
-                vuint32_t SR9:1;        /*  Channel 9 Data Transfer Request Enable  */
-                vuint32_t SR8:1;        /*  Channel 8 Data Transfer Request Enable  */
-                vuint32_t SR7:1;        /*  Channel 7 Data Transfer Request Enable  */
-                vuint32_t SR6:1;        /*  Channel 6 Data Transfer Request Enable  */
-                vuint32_t SR5:1;        /*  Channel 5 Data Transfer Request Enable  */
-                vuint32_t SR4:1;        /*  Channel 4 Data Transfer Request Enable  */
-                vuint32_t SR3:1;        /*  Channel 3 Data Transfer Request Enable  */
-                vuint32_t SR2:1;        /*  Channel 2 Data Transfer Request Enable  */
-                vuint32_t SR1:1;        /*  Channel 1 Data Transfer Request Enable  */
-                vuint32_t SR0:1;        /*  Channel 0 Data Transfer Request Enable  */
-            } B;
-        } CPSSR_A;              /* ETPUCPSSR - eTPU Channel Pending Service Status Register @baseaddress + 0x280  */
-
-        int32_t ETPU_reserved_0x0284[3];        /* 0x0284 - 0x028F  */
-
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SS31:1;       /*  Channel 31 Data Transfer Request Enable  */
-                vuint32_t SS30:1;       /*  Channel 30 Data Transfer Request Enable  */
-                vuint32_t SS29:1;       /*  Channel 29 Data Transfer Request Enable  */
-                vuint32_t SS28:1;       /*  Channel 28 Data Transfer Request Enable  */
-                vuint32_t SS27:1;       /*  Channel 27 Data Transfer Request Enable  */
-                vuint32_t SS26:1;       /*  Channel 26 Data Transfer Request Enable  */
-                vuint32_t SS25:1;       /*  Channel 25 Data Transfer Request Enable  */
-                vuint32_t SS24:1;       /*  Channel 24 Data Transfer Request Enable  */
-                vuint32_t SS23:1;       /*  Channel 23 Data Transfer Request Enable  */
-                vuint32_t SS22:1;       /*  Channel 22 Data Transfer Request Enable  */
-                vuint32_t SS21:1;       /*  Channel 21 Data Transfer Request Enable  */
-                vuint32_t SS20:1;       /*  Channel 20 Data Transfer Request Enable  */
-                vuint32_t SS19:1;       /*  Channel 19 Data Transfer Request Enable  */
-                vuint32_t SS18:1;       /*  Channel 18 Data Transfer Request Enable  */
-                vuint32_t SS17:1;       /*  Channel 17 Data Transfer Request Enable  */
-                vuint32_t SS16:1;       /*  Channel 16 Data Transfer Request Enable  */
-                vuint32_t SS15:1;       /*  Channel 15 Data Transfer Request Enable  */
-                vuint32_t SS14:1;       /*  Channel 14 Data Transfer Request Enable  */
-                vuint32_t SS13:1;       /*  Channel 13 Data Transfer Request Enable  */
-                vuint32_t SS12:1;       /*  Channel 12 Data Transfer Request Enable  */
-                vuint32_t SS11:1;       /*  Channel 11 Data Transfer Request Enable  */
-                vuint32_t SS10:1;       /*  Channel 10 Data Transfer Request Enable  */
-                vuint32_t SS9:1;        /*  Channel 9 Data Transfer Request Enable  */
-                vuint32_t SS8:1;        /*  Channel 8 Data Transfer Request Enable  */
-                vuint32_t SS7:1;        /*  Channel 7 Data Transfer Request Enable  */
-                vuint32_t SS6:1;        /*  Channel 6 Data Transfer Request Enable  */
-                vuint32_t SS5:1;        /*  Channel 5 Data Transfer Request Enable  */
-                vuint32_t SS4:1;        /*  Channel 4 Data Transfer Request Enable  */
-                vuint32_t SS3:1;        /*  Channel 3 Data Transfer Request Enable  */
-                vuint32_t SS2:1;        /*  Channel 2 Data Transfer Request Enable  */
-                vuint32_t SS1:1;        /*  Channel 1 Data Transfer Request Enable  */
-                vuint32_t SS0:1;        /*  Channel 0 Data Transfer Request Enable  */
-            } B;
-        } CSSR_A;               /* ETPUCSSR - eTPU Channel Service Status Register @baseaddress + 0x290  */
-
-        int32_t ETPU_reserved_0294[91];         /* 0x0294 - 0x03FF */
-
-
-/***************************** Channels ********************************/
-/* Note not all devices implement all channels or even 2 engines       */
-/* Each eTPU engine can implement 64 channels, however most devcies    */
-/* only implemnet 32 channels. The eTPU block can implement 1 or 2     */
-/* engines per instantiation                                           */
-/***********************************************************************/
-
-        struct {
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t CIE:1;    /*  Channel Interruput Enable  */
-                    vuint32_t DTRE:1;   /*  Data Transfer Request Enable  */
-                    vuint32_t CPR:2;    /*  Channel Priority  */
-                      vuint32_t:2;      /*  */
-                    vuint32_t ETPD:1;   /*  This bit selects which channel signal, input or output, is used in the entry point selection */
-                    vuint32_t ETCS:1;   /*  Entry Table Condition Select  */
-                      vuint32_t:3;      /*  */
-                    vuint32_t CFS:5;    /*  Channel Function Select  */
-                    vuint32_t ODIS:1;   /*  Output disable  */
-                    vuint32_t OPOL:1;   /*  output polarity  */
-                      vuint32_t:3;      /*  */
-                    vuint32_t CPBA:11;  /*  Channel Parameter Base Address  */
-                } B;
-            } CR;               /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t CIS:1;    /*  Channel Interruput Status  */
-                    vuint32_t CIOS:1;   /*  Channel Interruput Overflow Status  */
-                      vuint32_t:6;      /*  */
-                    vuint32_t DTRS:1;   /*  Data Transfer Status  */
-                    vuint32_t DTROS:1;  /*  Data Transfer Overflow Status  */
-                      vuint32_t:6;      /*  */
-                    vuint32_t IPS:1;    /*  Input Pin State  */
-                    vuint32_t OPS:1;    /*  Output Pin State  */
-                    vuint32_t OBE:1;    /*  Output Pin State  */
-                      vuint32_t:11;     /*  */
-                    vuint32_t FM1:1;    /* Function mode */
-                    vuint32_t FM0:1;    /* Function mode */
-                } B;
-            } SCR;              /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:29;       /*  Host Service Request  */
-                    vuint32_t HSR:3;    /*  */
-                } B;
-            } HSRR;             /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */
-
-            int32_t ETPU_reserved_0C;       /* CHAN Base + 0x0C */
-
-        } CHAN[127];
-                 /**** Note: Not all channels implemented on all devices. *******/
-    };
-
-/****************************************************************************/
-/*                          MODULE : EQADC                                  */
-/****************************************************************************/
-    struct EQADC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:24;
-                vuint32_t ICEA0:1;
-                vuint32_t ICEA1:1;
-                  vuint32_t:1;
-                vuint32_t ESSIE:2;
-                  vuint32_t:1;
-                vuint32_t DBG:2;
-            } B;
-        } MCR;                  /* Module Configuration Register */
-
-        int32_t EQADC_reserved0004;     /* 0x0004 - 0x0007 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:6;
-                vuint32_t NMF:26;
-            } B;
-        } NMSFR;                /* Null Message Send Format Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:28;
-                vuint32_t DFL:4;
-            } B;
-        } ETDFR;                /* External Trigger Digital Filter Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFPUSH:32;
-            } B;
-        } CFPR[6];              /* CFIFO Push Registers */
-
-        uint32_t eqadc_reserved1;
-
-        uint32_t eqadc_reserved2;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RFPOP:16;
-            } B;
-        } RFPR[6];              /* Result FIFO Pop Registers*/
-
-        uint32_t eqadc_reserved3;
-
-        uint32_t eqadc_reserved4;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:3;
-                vuint16_t CFEE0:1;
-                vuint16_t STRME0:1;
-                vuint16_t SSE:1;
-                vuint16_t CFINV:1;
-                  vuint16_t:1;
-                vuint16_t MODE:4;
-                vuint16_t AMODE0:4;     /* CFIFO0 only */
-            } B;
-        } CFCR[6];              /* CFIFO Control Registers */
-
-        uint32_t eqadc_reserved5;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t NCIE:1;
-                vuint16_t TORIE:1;
-                vuint16_t PIE:1;
-                vuint16_t EOQIE:1;
-                vuint16_t CFUIE:1;
-                  vuint16_t:1;
-                vuint16_t CFFE:1;
-                vuint16_t CFFS:1;
-                  vuint16_t:4;
-                vuint16_t RFOIE:1;
-                  vuint16_t:1;
-                vuint16_t RFDE:1;
-                vuint16_t RFDS:1;
-            } B;
-        } IDCR[6];              /* Interrupt and DMA Control Registers */
-
-        uint32_t eqadc_reserved6;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t NCF:1;
-                vuint32_t TORF:1;
-                vuint32_t PF:1;
-                vuint32_t EOQF:1;
-                vuint32_t CFUF:1;
-                vuint32_t SSS:1;
-                vuint32_t CFFF:1;
-                  vuint32_t:5;
-                vuint32_t RFOF:1;
-                  vuint32_t:1;
-                vuint32_t RFDF:1;
-                  vuint32_t:1;
-                vuint32_t CFCTR:4;
-                vuint32_t TNXTPTR:4;
-                vuint32_t RFCTR:4;
-                vuint32_t POPNXTPTR:4;
-            } B;
-        } FISR[6];              /* FIFO and Interrupt Status Registers */
-
-        uint32_t eqadc_reserved7;
-
-        uint32_t eqadc_reserved8;
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t TCCF:11;
-            } B;
-        } CFTCR[6];             /* CFIFO Transfer Counter Registers */
-
-        uint32_t eqadc_reserved9;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFS0:2;
-                vuint32_t CFS1:2;
-                vuint32_t CFS2:2;
-                vuint32_t CFS3:2;
-                vuint32_t CFS4:2;
-                vuint32_t CFS5:2;
-                  vuint32_t:5;
-                vuint32_t LCFTCB0:4;
-                vuint32_t TC_LCFTCB0:11;
-            } B;
-        } CFSSR0;               /* CFIFO Status Register 0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFS0:2;
-                vuint32_t CFS1:2;
-                vuint32_t CFS2:2;
-                vuint32_t CFS3:2;
-                vuint32_t CFS4:2;
-                vuint32_t CFS5:2;
-                  vuint32_t:5;
-                vuint32_t LCFTCB1:4;
-                vuint32_t TC_LCFTCB1:11;
-            } B;
-        } CFSSR1;               /* CFIFO Status Register 1 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFS0:2;
-                vuint32_t CFS1:2;
-                vuint32_t CFS2:2;
-                vuint32_t CFS3:2;
-                vuint32_t CFS4:2;
-                vuint32_t CFS5:2;
-                  vuint32_t:4;
-                vuint32_t ECBNI:1;
-                vuint32_t LCFTSSI:4;
-                vuint32_t TC_LCFTSSI:11;
-            } B;
-        } CFSSR2;               /* CFIFO Status Register 2 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CFS0:2;
-                vuint32_t CFS1:2;
-                vuint32_t CFS2:2;
-                vuint32_t CFS3:2;
-                vuint32_t CFS4:2;
-                vuint32_t CFS5:2;
-                  vuint32_t:20;
-            } B;
-        } CFSR;
-
-        uint32_t eqadc_reserved11;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:21;
-                vuint32_t MDT:3;
-                  vuint32_t:4;
-                vuint32_t BR:4;
-            } B;
-        } SSICR;                /* SSI Control Register */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t RDV:1;
-                  vuint32_t:5;
-                vuint32_t RDATA:26;
-            } B;
-        } SSIRDR;               /* SSI Recieve Data Register @ baseaddress + 0xB8 */
-
-        uint32_t eqadc_reserved11b[5];
-
-        union {
-            vuint32_t R;
-            struct {
-                 vuint32_t:16;
-                vuint32_t REDBS2:4;
-                vuint32_t SRV2:4;
-                vuint32_t REDBS1:4;
-                vuint32_t SRV1:4;
-            } B;
-        } REDLCCR;               /* STAC Bus Clent Configuration Register @ baseaddress + 0xD0 */
-
-
-        uint32_t eqadc_reserved12[11];
-
-        struct {
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:32;
-                } B;
-            } R[4];
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:32;
-                } B;
-            } EDATA[4];
-
-            uint32_t eqadc_reserved13[8];
-
-        } CF[6];
-
-        uint32_t eqadc_reserved14[32];
-
-        struct {
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:32;
-                } B;
-            } R[4];
-
-            uint32_t eqadc_reserved15[12];
-
-        } RF[6];
-
-    };
-
-/****************************************************************************/
-/*                     MODULE : Decimation Filter (DECFIL)                  */
-/****************************************************************************/
-    struct DECFIL_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MDIS:1;
-                vuint32_t FREN:1;
-                  vuint32_t:1;
-                vuint32_t FRZ:1;
-                vuint32_t SRES:1;
-                vuint32_t CASCD:2;
-                vuint32_t IDEN:1;
-                vuint32_t ODEN:1;
-                vuint32_t ERREN:1;
-                  vuint32_t:1;
-                vuint32_t FTYPE:2;
-                  vuint32_t:1;
-                vuint32_t SCAL:2;
-                vuint32_t IDIS:1;
-                vuint32_t SAT:1;
-                vuint32_t ISEL:1;
-                vuint32_t MIXM:1;
-                vuint32_t DEC_RATE:4;
-                vuint32_t SDIE:1;
-                vuint32_t DSEL:1;
-                vuint32_t IBIE:1;
-                vuint32_t OBIE:1;
-                vuint32_t EDME:1;
-                vuint32_t TORE:1;
-                vuint32_t TMODE:2;
-            } B;
-        } MCR;                  /* Configuration Register @baseaddress + 0x00 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BSY:1;
-                  vuint32_t:1;
-                vuint32_t DEC_COUNTER:4;
-                vuint32_t IDFC:1;
-                vuint32_t ODFC:1;
-                  vuint32_t:1;
-                vuint32_t IBIC:1;
-                vuint32_t OBIC:1;
-                  vuint32_t:1;
-                vuint32_t DIVRC:1;
-                vuint32_t OVFC:1;
-                vuint32_t OVRC:1;
-                vuint32_t IVRC:1;
-                  vuint32_t:6;
-                vuint32_t IDF:1;
-                vuint32_t ODF:1;
-                  vuint32_t:1;
-                vuint32_t IBIF:1;
-                vuint32_t OBIF:1;
-                  vuint32_t:1;
-                vuint32_t DIVR:1;
-                vuint32_t OVF:1;
-                vuint32_t OVR:1;
-                vuint32_t IVR:1;
-            } B;
-        } MSR;                  /* Status Register @baseaddress + 0x04 */
-
- 		union {
-            vuint32_t R;
-            struct {
-                vuint32_t SDMAE:1;
-                vuint32_t SSIG:1;
-                vuint32_t SSAT:1;
-                vuint32_t SCSAT:1;
-                  vuint32_t:10;
-                vuint32_t SRQ:1;
-                vuint32_t SZRO:1;  
-                vuint32_t SISEL:1;  
-                  vuint32_t:1;
-                vuint32_t SZROSEL:2;    
-                  vuint32_t:2;
-                vuint32_t SHLTSEL:2;      
-                  vuint32_t:1;
-                vuint32_t SRQSEL:3;        
-                  vuint32_t:2;
-                vuint32_t SENSEL:2;          
-            } B;
-        } MXCR;                   /* Extended Config Register @baseaddress + 0x8  */
-        
-        union {
-            vuint32_t R;
-            struct {
-                  vuint32_t:7;
-                vuint32_t SDFC:1;
-                  vuint32_t:2;
-                vuint32_t SSEC:1;
-                vuint32_t SCEC:1;
-                  vuint32_t:1;
-                vuint32_t SSOVFC:1;
-                vuint32_t SCOVFC:1;
-                vuint32_t SVRC:1;  
-                  vuint32_t:7;
-                vuint32_t SDF:1;
-                  vuint32_t:2;
-                vuint32_t SSE:1;
-                vuint32_t SCE:1;
-                  vuint32_t:1;
-                vuint32_t SSOVF:1;
-                vuint32_t SCOVF:1;
-                vuint32_t SVR:1;    
-            } B;
-        } MXSR;                   /* Extended Status Register @baseaddress + 0xC  */       
-        
-
-        union {
-            vuint32_t R;
-            struct {
-                  vuint32_t:4;
-                vuint32_t INTAG:4;  
-                  vuint32_t:6;
-                vuint32_t PREFILL:1;
-                vuint32_t FLUSH:1;
-                vuint32_t INPBUF:16;
-            } B;
-        } IB;                   /* Interface Input Buffer @baseaddress + 0x10  */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t OUTTAG:4;
-                vuint32_t OUTBUF:16;
-            } B;
-        } OB;                   /* Interface Output Buffer @baseaddress + 0x14  */
-
-        uint32_t decfil_reserved0018[2];        /* 0x0018 - 0x001F */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t COEF:24;
-            } B;
-        } COEF[9];              /* Filter Coefficient Registers @baseaddress + 0x20 - 0x40  */
-
-        uint32_t decfil_reserved0044[13];       /* 0x0044 - 0x0077 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:8;
-                vuint32_t TAP:24;
-            } B;
-        } TAP[8];               /* Filter TAP Registers @baseaddress + 0x78 - 0x94 */
-
-        uint32_t decfil_reserved00D0[14];       /* 0x00D0 - 0x00D3 */
-
-        /* 0x0D0 */
-        union {
-            vuint16_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t SAMP_DATA:16;
-            } B;
-        } EDID;                 /* Filter EDID Registers @baseaddress + 0xD0 */
-
-        uint32_t decfil_reserved00D4[3];    /* 0x00D4 - 0x00DF */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SUM_VALUE:1;
-            } B;
-        } FINTVAL;                   /* Final Integr. Value Register @baseaddress + 0xE0  */       
-
-       union {
-            vuint32_t R;
-            struct {
-                vuint32_t COUNT:1;
-            } B;
-        } FINTCNT;                   /* Final Integr. Count Register @baseaddress + 0xE0  */       
-
-       union {
-            vuint32_t R;
-            struct {
-                vuint32_t SUM_VALUE:1;
-            } B;
-        } CINTVAL;                   /* Current Integr. Value Register @baseaddress + 0xE0  */       
-
-       union {
-            vuint32_t R;
-            struct {
-                vuint32_t COUNT:1;
-            } B;
-        } CINTCNT;                   /* Current Integr. Count Register @baseaddress + 0xE0  */       
-
-    };
-
-/****************************************************************************/
-/*                          MODULE : CRC                                   */
-/****************************************************************************/
-   struct CRC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:29;
-                vuint32_t POLY:1;
-                vuint32_t SWAP:1;
-                vuint32_t INV:1;
-            } B;
-        } CFG;                      /* Configuration Register @baseaddress + 0x00 */
-
-        union {
-            vuint32_t R;
-            struct{
-                vuint32_t INP:32;
-            } B;
-        } INP;                      /* Input Register @baseaddress + 0x04 */
-
-        union {
-            vuint32_t R;
-            struct{
-                vuint32_t CSTAT:32;
-            } B;
-        } CSTAT;                    /* Current Status Register @baseaddress + 0x08 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t OUTP:32;
-            } B;
-        } OUTP;                     /* Output Register @baseaddress + 0x0C */
-    };
-
-/****************************************************************************/
-/*                          MODULE : DSPI                                   */
-/****************************************************************************/
-    struct DSPI_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MSTR:1;
-                vuint32_t CONT_SCKE:1;
-                vuint32_t DCONF:2;
-                vuint32_t FRZ:1;
-                vuint32_t MTFE:1;
-                vuint32_t PCSSE:1;
-                vuint32_t ROOE:1;
-                vuint32_t PCSIS7:1;
-                vuint32_t PCSIS6:1;
-                vuint32_t PCSIS5:1;
-                vuint32_t PCSIS4:1;
-                vuint32_t PCSIS3:1;
-                vuint32_t PCSIS2:1;
-                vuint32_t PCSIS1:1;
-                vuint32_t PCSIS0:1;
-                vuint32_t DOZE:1;
-                vuint32_t MDIS:1;
-                vuint32_t DIS_TXF:1;
-                vuint32_t DIS_RXF:1;
-                vuint32_t CLR_TXF:1;
-                vuint32_t CLR_RXF:1;
-                vuint32_t SMPL_PT:2;
-                  vuint32_t:6;
-                vuint32_t PES:1;  
-                vuint32_t HALT:1;
-            } B;
-        } MCR;                  /* Module Configuration Register @baseaddress + 0x00 */
-
-        uint32_t dspi_reserved0004;         /* 0x0004-0x008 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCNT:16;
-                  vuint32_t:16;
-            } B;
-        } TCR;                  /* DSPI Transfer Count Register  @baseaddress + 0x08 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DBR:1;
-                vuint32_t FMSZ:4;
-                vuint32_t CPOL:1;
-                vuint32_t CPHA:1;
-                vuint32_t LSBFE:1;
-                vuint32_t PCSSCK:2;
-                vuint32_t PASC:2;
-                vuint32_t PDT:2;
-                vuint32_t PBR:2;
-                vuint32_t CSSCK:4;
-                vuint32_t ASC:4;
-                vuint32_t DT:4;
-                vuint32_t BR:4;
-            } B;
-        } CTAR[8];              /* Clock and Transfer Attributes Registers @baseaddress + 0x0C - 0x28 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCF:1;
-                vuint32_t TXRXS:1;
-                  vuint32_t:1;
-                vuint32_t EOQF:1;
-                vuint32_t TFUF:1;
-                  vuint32_t:1;
-                vuint32_t TFFF:1;
-                  vuint32_t:2;
-                vuint32_t DPEF:1;
-                vuint32_t SPEF:1;
-                vuint32_t DDIF:1;
-                vuint32_t RFOF:1;
-                  vuint32_t:1;
-                vuint32_t RFDF:1;
-                  vuint32_t:1;
-                vuint32_t TXCTR:4;
-                vuint32_t TXNXTPTR:4;
-                vuint32_t RXCTR:4;
-                vuint32_t POPNXTPTR:4;
-            } B;
-        } SR;                   /* Status Register @baseaddress + 0x2C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TCFRE:1;
-                  vuint32_t:2;
-                vuint32_t EOQFRE:1;
-                vuint32_t TFUFRE:1;
-                  vuint32_t:1;
-                vuint32_t TFFFRE:1;
-                vuint32_t TFFFDIRS:1;
-                  vuint32_t:1;
-                vuint32_t DPEFRE:1;
-                vuint32_t SPEFRE:1;
-                vuint32_t DDIFRE:1;  
-                vuint32_t RFOFRE:1;
-                  vuint32_t:1;
-                vuint32_t RFDFRE:1;
-                vuint32_t RFDFDIRS:1;
-                  vuint32_t:16;
-            } B;
-        } RSER;                 /* DMA/Interrupt Request Select and Enable Register @baseaddress + 0x30 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t CONT:1;
-                vuint32_t CTAS:3;
-                vuint32_t EOQ:1;
-                vuint32_t CTCNT:1;
-                vuint32_t PE:1;
-                vuint32_t PP:1;
-                vuint32_t PCS7:1;       /* new in MPC563xM */
-                vuint32_t PCS6:1;       /* new in MPC563xM */
-                vuint32_t PCS5:1;
-                vuint32_t PCS4:1;
-                vuint32_t PCS3:1;
-                vuint32_t PCS2:1;
-                vuint32_t PCS1:1;
-                vuint32_t PCS0:1;
-                vuint32_t TXDATA:16;
-            } B;
-        } PUSHR;                /* PUSH TX FIFO Register @baseaddress + 0x34 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXDATA:16;
-            } B;
-        } POPR;                 /* POP RX FIFO Register @baseaddress + 0x38 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TXCMD:16;
-                vuint32_t TXDATA:16;
-            } B;
-        } TXFR[4];              /* Transmit FIFO Registers @baseaddress + 0x3c - 0x78 */
-
-        vuint32_t DSPI_reserved_004C[12];   /* 0x004C-0x0078 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXDATA:16;
-            } B;
-        } RXFR[4];              /* Transmit FIFO Registers @baseaddress + 0x7c - 0xB8 */
-
-        vuint32_t DSPI_reserved_008C[12];   /* 0x008C-0x00B8 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MTOE:1;
-                vuint32_t FMSZ4:1;
-                vuint32_t MTOCNT:6;
-                  vuint32_t:3;
-                vuint32_t TSBC:1;
-                vuint32_t TXSS:1;
-                vuint32_t TPOL:1;
-                vuint32_t TRRE:1;
-                vuint32_t CID:1;
-                vuint32_t DCONT:1;
-                vuint32_t DSICTAS:3;
-                  vuint32_t:4;
-                vuint32_t DPCS7:1;
-                vuint32_t DPCS6:1;
-                vuint32_t DPCS5:1;
-                vuint32_t DPCS4:1;
-                vuint32_t DPCS3:1;
-                vuint32_t DPCS2:1;
-                vuint32_t DPCS1:1;
-                vuint32_t DPCS0:1;
-            } B;
-        } DSICR;                /* DSI Configuration Register @baseaddress + 0xBC */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t SER_DATA:32;
-            } B;
-        } SDR;                  /* DSI Serialization Data Register @baseaddress + 0xC0 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t ASER_DATA:32;
-            } B;
-        } ASDR;                 /* DSI Alternate Serialization Data Register @baseaddress + 0xC4 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t COMP_DATA:32;
-            } B;
-        } COMPR;                /* DSI Transmit Comparison Register @baseaddress + 0xC8 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t DESER_DATA:32;
-            } B;
-        } DDR;                  /* DSI deserialization Data Register @baseaddress + 0xCC */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t TSBCNT:5;
-                  vuint32_t:16;
-                vuint32_t DPCS1_7:1;
-                vuint32_t DPCS1_6:1;
-                vuint32_t DPCS1_5:1;
-                vuint32_t DPCS1_4:1;
-                vuint32_t DPCS1_3:1;
-                vuint32_t DPCS1_2:1;
-                vuint32_t DPCS1_1:1;
-                vuint32_t DPCS1_0:1;
-            } B;
-        } DSICR1;               /* DSI Configuration Register 1 @baseaddress + 0xD0 */
-
-    };
-
-/****************************************************************************/
-/*                          MODULE : eSCI                                   */
-/****************************************************************************/
-    struct ESCI_tag {
-        union {
-            vuint32_t R;
-            struct {
-                  vuint32_t:3;
-                vuint32_t SBR:13;
-                vuint32_t LOOPS:1;
-                  vuint32_t:1;
-                vuint32_t RSRC:1;
-                vuint32_t M:1;
-                vuint32_t WAKE:1;
-                vuint32_t ILT:1;
-                vuint32_t PE:1;
-                vuint32_t PT:1;
-                vuint32_t TIE:1;
-                vuint32_t TCIE:1;
-                vuint32_t RIE:1;
-                vuint32_t ILIE:1;
-                vuint32_t TE:1;
-                vuint32_t RE:1;
-                vuint32_t RWU:1;
-                vuint32_t SBK:1;
-            } B;
-        } CR1;                  /* Control Register 1  @baseaddress + 0x00 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t MDIS:1;
-                vuint16_t FBR:1;
-                vuint16_t BSTP:1;
-                vuint16_t IEBERR:1;
-                vuint16_t RXDMA:1;
-                vuint16_t TXDMA:1;
-                vuint16_t BRK13:1;
-                vuint16_t TXDIR:1;
-                vuint16_t BESM13:1;
-                vuint16_t SBSTP:1;
-                vuint16_t RXPOL:1;
-                vuint16_t PMSK:1;
-                vuint16_t ORIE:1;
-                vuint16_t NFIE:1;
-                vuint16_t FEIE:1;
-                vuint16_t PFIE:1;
-            } B;
-        } CR2;                  /* Control Register 2 @baseaddress + 0x04 */
-
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t R8:1;
-                vuint16_t T8:1;
-                vuint16_t ERR:1;
-                  vuint16_t:1;
-                vuint16_t R:4;
-                vuint8_t D;
-            } B;
-        } DR;                   /* Data Register @baseaddress + 0x06 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t TDRE:1;
-                vuint32_t TC:1;
-                vuint32_t RDRF:1;
-                vuint32_t IDLE:1;
-                vuint32_t OR:1;
-                vuint32_t NF:1;
-                vuint32_t FE:1;
-                vuint32_t PF:1;
-                  vuint32_t:3;
-                vuint32_t BERR:1;
-                  vuint32_t:2;
-                vuint32_t TACT:1;
-                vuint32_t RAF:1;
-                vuint32_t RXRDY:1;
-                vuint32_t TXRDY:1;
-                vuint32_t LWAKE:1;
-                vuint32_t STO:1;
-                vuint32_t PBERR:1;
-                vuint32_t CERR:1;
-                vuint32_t CKERR:1;
-                vuint32_t FRC:1;
-                  vuint32_t:6;
-                vuint32_t UREQ:1;
-                vuint32_t OVFL:1;
-            } B;
-        } SR;                   /* Status Register   @baseaddress + 0x08 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t LRES:1;
-                vuint32_t WU:1;
-                vuint32_t WUD0:1;
-                vuint32_t WUD1:1;
-                vuint32_t LDBG:1;
-                vuint32_t DSF:1;
-                vuint32_t PRTY:1;
-                vuint32_t LIN:1;
-                vuint32_t RXIE:1;
-                vuint32_t TXIE:1;
-                vuint32_t WUIE:1;
-                vuint32_t STIE:1;
-                vuint32_t PBIE:1;
-                vuint32_t CIE:1;
-                vuint32_t CKIE:1;
-                vuint32_t FCIE:1;
-                  vuint32_t:6;
-                vuint32_t UQIE:1;
-                vuint32_t OFIE:1;
-                  vuint32_t:8;
-            } B;
-        } LCR;                  /* LIN Control Register @baseaddress + 0x0C  */
-
-        union {
-            vuint32_t R;
-        } LTR;                  /* LIN Transmit Register @baseaddress + 0x10 */
-
-        union {
-            vuint32_t R;
-        } LRR;                  /* LIN Recieve Register @baseaddress + 0x14 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t P:16;
-                  vuint32_t:3;
-                vuint32_t SYNM:1;
-                vuint32_t EROE:1;
-                vuint32_t ERFE:1;
-                vuint32_t ERPE:1;
-                vuint32_t M2:1;
-                  vuint32_t:8;
-            } B;
-        } LPR;                  /* LIN CRC Polynom Register  @baseaddress + 0x18 */
-
-    };
-/****************************************************************************/
-/*                          MODULE : eSCI                                   */
-/****************************************************************************/
-    struct ESCI_12_13_bit_tag {
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t R8:1;
-                vuint16_t T8:1;
-                vuint16_t ERR:1;
-                  vuint16_t:1;
-                vuint16_t D:12;
-            } B;
-        } DR;                   /* Data Register */
-    };
-
-/****************************************************************************/
-/*                          MODULE : FlexCAN                                */
-/****************************************************************************/
-    struct FLEXCAN_BUF_t {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:4;
-                vuint32_t CODE:4;
-                  vuint32_t:1;
-                vuint32_t SRR:1;
-                vuint32_t IDE:1;
-                vuint32_t RTR:1;
-                vuint32_t LENGTH:4;
-                vuint32_t TIMESTAMP:16;
-            } B;
-        } CS;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRIO:3;
-                vuint32_t STD_ID:11;
-                vuint32_t EXT_ID:18;
-            } B;
-        } ID;
-
-        union {
-            /*vuint8_t  B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */
-            /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */
-            vuint32_t W[2];     /* Data buffer in words (32 bits) */
-            /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */
-        } DATA;
-
-    };                          /* end of FLEXCAN_BUF_t */
-
-    struct FLEXCAN_RXFIFO_t {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:9;
-                vuint32_t SRR:1;
-                vuint32_t IDE:1;
-                vuint32_t RTR:1;
-                vuint32_t LENGTH:4;
-                vuint32_t TIMESTAMP:16;
-            } B;
-        } CS;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t STD_ID:11;
-                vuint32_t EXT_ID:18;
-            } B;
-        } ID;
-
-        union {
-            /*vuint8_t  B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */
-            /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */
-            vuint32_t W[2];     /* Data buffer in words (32 bits) */
-            /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */
-        } DATA;
-
-        uint32_t FLEXCAN_RXFIFO_reserved[20];   /* {0x00E0-0x0090}/0x4 = 0x14 */
-
-        union {
-            vuint32_t R;
-        } IDTABLE[8];
-
-    };                          /* end of FLEXCAN_RXFIFO_t */
-
-    struct FLEXCAN2_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-                vuint32_t FEN:1;
-                vuint32_t HALT:1;
-                vuint32_t NOTRDY:1;
-                vuint32_t WAK_MSK:1;
-                vuint32_t SOFTRST:1;
-                vuint32_t FRZACK:1;
-                vuint32_t SUPV:1;
-                vuint32_t SLF_WAK:1;
-
-                vuint32_t WRNEN:1;
-
-                vuint32_t MDISACK:1;
-                vuint32_t WAK_SRC:1;
-                vuint32_t DOZE:1;
-
-                vuint32_t SRXDIS:1;
-                vuint32_t MBFEN:1;
-                  vuint32_t:2;
-
-                vuint32_t LPRIO_EN:1;
-                vuint32_t AEN:1;
-                  vuint32_t:2;
-                vuint32_t IDAM:2;
-                  vuint32_t:2;
-
-                vuint32_t MAXMB:6;
-            } B;
-        } MCR;                  /* Module Configuration Register @baseaddress + 0x00 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t PRESDIV:8;
-                vuint32_t RJW:2;
-                vuint32_t PSEG1:3;
-                vuint32_t PSEG2:3;
-                vuint32_t BOFFMSK:1;
-                vuint32_t ERRMSK:1;
-                vuint32_t CLKSRC:1;
-                vuint32_t LPB:1;
-                vuint32_t TWRNMSK:1;
-                vuint32_t RWRNMSK:1;
-                  vuint32_t:2;
-                vuint32_t SMP:1;
-                vuint32_t BOFFREC:1;
-                vuint32_t TSYN:1;
-                vuint32_t LBUF:1;
-                vuint32_t LOM:1;
-                vuint32_t PROPSEG:3;
-            } B;                /* Control Register @baseaddress + 0x04 */
-        } CR;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t TIMER:16;
-            } B;
-        } TIMER;                /* Free Running Timer @baseaddress + 0x08 */
-
-        int32_t FLEXCAN_reserved00;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t MI:29;
-            } B;
-        } RXGMASK;              /* RX Global Mask @baseaddress + 0x0C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t MI:29;
-            } B;
-        } RX14MASK;             /* RX 14 Mask @baseaddress + 0x10 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:3;
-                vuint32_t MI:29;
-            } B;
-        } RX15MASK;             /* RX 15 Mask @baseaddress + 0x14 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:16;
-                vuint32_t RXECNT:8;
-                vuint32_t TXECNT:8;
-            } B;
-        } ECR;                  /* Error Counter Register @baseaddress + 0x18 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:14;
-                vuint32_t TWRNINT:1;
-                vuint32_t RWRNINT:1;
-                vuint32_t BIT1ERR:1;
-                vuint32_t BIT0ERR:1;
-                vuint32_t ACKERR:1;
-                vuint32_t CRCERR:1;
-                vuint32_t FRMERR:1;
-                vuint32_t STFERR:1;
-                vuint32_t TXWRN:1;
-                vuint32_t RXWRN:1;
-                vuint32_t IDLE:1;
-                vuint32_t TXRX:1;
-                vuint32_t FLTCONF:2;
-                  vuint32_t:1;
-                vuint32_t BOFFINT:1;
-                vuint32_t ERRINT:1;
-                vuint32_t WAK_INT:1;
-            } B;
-        } ESR;                  /* Error and Status Register @baseaddress + 0x1C */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF63M:1;
-                vuint32_t BUF62M:1;
-                vuint32_t BUF61M:1;
-                vuint32_t BUF60M:1;
-                vuint32_t BUF59M:1;
-                vuint32_t BUF58M:1;
-                vuint32_t BUF57M:1;
-                vuint32_t BUF56M:1;
-                vuint32_t BUF55M:1;
-                vuint32_t BUF54M:1;
-                vuint32_t BUF53M:1;
-                vuint32_t BUF52M:1;
-                vuint32_t BUF51M:1;
-                vuint32_t BUF50M:1;
-                vuint32_t BUF49M:1;
-                vuint32_t BUF48M:1;
-                vuint32_t BUF47M:1;
-                vuint32_t BUF46M:1;
-                vuint32_t BUF45M:1;
-                vuint32_t BUF44M:1;
-                vuint32_t BUF43M:1;
-                vuint32_t BUF42M:1;
-                vuint32_t BUF41M:1;
-                vuint32_t BUF40M:1;
-                vuint32_t BUF39M:1;
-                vuint32_t BUF38M:1;
-                vuint32_t BUF37M:1;
-                vuint32_t BUF36M:1;
-                vuint32_t BUF35M:1;
-                vuint32_t BUF34M:1;
-                vuint32_t BUF33M:1;
-                vuint32_t BUF32M:1;
-            } B;                /* Interruput Masks Register @baseaddress + 0x20 */
-        } IMRH;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF31M:1;
-                vuint32_t BUF30M:1;
-                vuint32_t BUF29M:1;
-                vuint32_t BUF28M:1;
-                vuint32_t BUF27M:1;
-                vuint32_t BUF26M:1;
-                vuint32_t BUF25M:1;
-                vuint32_t BUF24M:1;
-                vuint32_t BUF23M:1;
-                vuint32_t BUF22M:1;
-                vuint32_t BUF21M:1;
-                vuint32_t BUF20M:1;
-                vuint32_t BUF19M:1;
-                vuint32_t BUF18M:1;
-                vuint32_t BUF17M:1;
-                vuint32_t BUF16M:1;
-                vuint32_t BUF15M:1;
-                vuint32_t BUF14M:1;
-                vuint32_t BUF13M:1;
-                vuint32_t BUF12M:1;
-                vuint32_t BUF11M:1;
-                vuint32_t BUF10M:1;
-                vuint32_t BUF09M:1;
-                vuint32_t BUF08M:1;
-                vuint32_t BUF07M:1;
-                vuint32_t BUF06M:1;
-                vuint32_t BUF05M:1;
-                vuint32_t BUF04M:1;
-                vuint32_t BUF03M:1;
-                vuint32_t BUF02M:1;
-                vuint32_t BUF01M:1;
-                vuint32_t BUF00M:1;
-            } B;                /* Interruput Masks Register @baseaddress + 0x24 */
-        } IMRL;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF63I:1;
-                vuint32_t BUF62I:1;
-                vuint32_t BUF61I:1;
-                vuint32_t BUF60I:1;
-                vuint32_t BUF59I:1;
-                vuint32_t BUF58I:1;
-                vuint32_t BUF57I:1;
-                vuint32_t BUF56I:1;
-                vuint32_t BUF55I:1;
-                vuint32_t BUF54I:1;
-                vuint32_t BUF53I:1;
-                vuint32_t BUF52I:1;
-                vuint32_t BUF51I:1;
-                vuint32_t BUF50I:1;
-                vuint32_t BUF49I:1;
-                vuint32_t BUF48I:1;
-                vuint32_t BUF47I:1;
-                vuint32_t BUF46I:1;
-                vuint32_t BUF45I:1;
-                vuint32_t BUF44I:1;
-                vuint32_t BUF43I:1;
-                vuint32_t BUF42I:1;
-                vuint32_t BUF41I:1;
-                vuint32_t BUF40I:1;
-                vuint32_t BUF39I:1;
-                vuint32_t BUF38I:1;
-                vuint32_t BUF37I:1;
-                vuint32_t BUF36I:1;
-                vuint32_t BUF35I:1;
-                vuint32_t BUF34I:1;
-                vuint32_t BUF33I:1;
-                vuint32_t BUF32I:1;
-            } B;                /* Interruput Flag Register @baseaddress + 0x28 */
-        } IFRH;
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t BUF31I:1;
-                vuint32_t BUF30I:1;
-                vuint32_t BUF29I:1;
-                vuint32_t BUF28I:1;
-                vuint32_t BUF27I:1;
-                vuint32_t BUF26I:1;
-                vuint32_t BUF25I:1;
-                vuint32_t BUF24I:1;
-                vuint32_t BUF23I:1;
-                vuint32_t BUF22I:1;
-                vuint32_t BUF21I:1;
-                vuint32_t BUF20I:1;
-                vuint32_t BUF19I:1;
-                vuint32_t BUF18I:1;
-                vuint32_t BUF17I:1;
-                vuint32_t BUF16I:1;
-                vuint32_t BUF15I:1;
-                vuint32_t BUF14I:1;
-                vuint32_t BUF13I:1;
-                vuint32_t BUF12I:1;
-                vuint32_t BUF11I:1;
-                vuint32_t BUF10I:1;
-                vuint32_t BUF09I:1;
-                vuint32_t BUF08I:1;
-                vuint32_t BUF07I:1;
-                vuint32_t BUF06I:1;
-                vuint32_t BUF05I:1;
-                vuint32_t BUF04I:1;
-                vuint32_t BUF03I:1;
-                vuint32_t BUF02I:1;
-                vuint32_t BUF01I:1;
-                vuint32_t BUF00I:1;
-            } B;                /* Interruput Flag Register @baseaddress + 0x2C */
-        } IFRL;
-
-        uint32_t flexcan2_reserved2[19];
-
-/****************************************************************************/
-/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure     */
-/****************************************************************************/
-        /* Standard Buffer Structure */
-        struct FLEXCAN_BUF_t BUF[64];
-
-        /* RX FIFO and Buffer Structure */
-        /*struct FLEXCAN_RXFIFO_t RXFIFO; */
-        /*struct FLEXCAN_BUF_t BUF[56];   */
-/****************************************************************************/
-
-        uint32_t FLEXCAN_reserved3[256];        /* {0x0880-0x0480}/0x4 = 0x100 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t MI:32;
-            } B;                /* RX Individual Mask Registers @baseaddress + 0x0880 */
-        } RXIMR[64];
-
-    };                          /* end of FLEXCAN_tag */
-
-/****************************************************************************/
-/*                     MODULE : Periodic Interval Timer (PIT)               */
-/****************************************************************************/
-    struct PIT_tag {
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:29;
-                vuint32_t MDIS_RTI:1;
-                vuint32_t MDIS:1;
-                vuint32_t FRZ:1;
-            } B;
-        } PITMCR;               /* PIT Module Control Register @baseaddress + 0x00 */
-
-        uint32_t pit_reserved1[59];
-
-        struct {
-            union {
-                vuint32_t R;
-            } LDVAL;            /* Timer Load Value Register @baseaddress + 0xF0 */
-
-            union {
-                vuint32_t R;
-            } CVAL;             /* Current Timer Value Register @baseaddress + 0xF4 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:30;
-                    vuint32_t TIE:1;
-                    vuint32_t TEN:1;
-                } B;
-            } TCTRL;            /* Timer Control Register @baseaddress + 0xF8 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:31;
-                    vuint32_t TIF:1;
-                } B;
-            } TFLG;             /* Timer Flag Register */
-        } RTI;                  /* RTI Channel @baseaddress + 0xFC */
-
-        struct {
-            union {
-                vuint32_t R;
-            } LDVAL;            /* Timer Load Value Register @baseaddress + CH + 0x0 */
-
-            union {
-                vuint32_t R;
-            } CVAL;             /* Current Timer Value Register @baseaddress + CH + 0x4 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:30;
-                    vuint32_t TIE:1;
-                    vuint32_t TEN:1;
-                } B;
-            } TCTRL;            /* Timer Control Register @baseaddress + CH + 0x8 */
-
-            union {
-                vuint32_t R;
-                struct {
-                    vuint32_t:31;
-                    vuint32_t TIF:1;
-                } B;
-            } TFLG;             /* Timer Flag Register @baseaddress + CH + 0xC */
-        } TIMER[4];             /* Timer Channels @baseaddress + 0x100 */
-
-    };
-
-/****************************************************************************/
-/*                          MODULE : FlexRay                                */
-/****************************************************************************/
-
-    typedef union uMVR {
-        vuint16_t R;
-        struct {
-            vuint16_t CHIVER:8; /* CHI Version Number */
-            vuint16_t PEVER:8;  /* PE Version Number */
-        } B;
-    } MVR_t;
-
-    typedef union uMCR {
-        vuint16_t R;
-        struct {
-            vuint16_t MEN:1;    /* module enable */
-              vuint16_t:1;
-            vuint16_t SCMD:1;   /* single channel mode */
-            vuint16_t CHB:1;    /* channel B enable */
-            vuint16_t CHA:1;    /* channel A enable */
-            vuint16_t SFFE:1;   /* synchronization frame filter enable */
-              vuint16_t:5;
-            vuint16_t CLKSEL:1; /* protocol engine clock source select */
-            vuint16_t PRESCALE:3;       /* protocol engine clock prescaler */
-              vuint16_t:1;
-        } B;
-    } MCR_t;
-
-    typedef union uSTBSCR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-            vuint16_t STBSSEL:7;        /* strobe signal select */
-              vuint16_t:3;
-            vuint16_t ENB:1;    /* strobe signal enable */
-              vuint16_t:2;
-            vuint16_t STBPSEL:2;        /* strobe port select */
-        } B;
-    } STBSCR_t;
-    typedef union uSTBPCR {
-        vuint16_t R;
-        struct {
-            vuint16_t:12;
-            vuint16_t STB3EN:1; /* strobe port enable */
-            vuint16_t STB2EN:1; /* strobe port enable */
-            vuint16_t STB1EN:1; /* strobe port enable */
-            vuint16_t STB0EN:1; /* strobe port enable */
-        } B;
-    } STBPCR_t;
-
-    typedef union uMBDSR {
-        vuint16_t R;
-        struct {
-            vuint16_t:1;
-            vuint16_t MBSEG2DS:7;       /* message buffer segment 2 data size */
-              vuint16_t:1;
-            vuint16_t MBSEG1DS:7;       /* message buffer segment 1 data size */
-        } B;
-    } MBDSR_t;
-    typedef union uMBSSUTR {
-        vuint16_t R;
-        struct {
-
-            vuint16_t:1;
-            vuint16_t LAST_MB_SEG1:7;   /* last message buffer control register for message buffer segment 1 */
-              vuint16_t:1;
-            vuint16_t LAST_MB_UTIL:7;   /* last message buffer utilized */
-        } B;
-    } MBSSUTR_t;
-
-    typedef union uPOCR {
-        vuint16_t R;
-        vuint8_t byte[2];
-        struct {
-            vuint16_t WME:1;    /* write mode external correction command */
-              vuint16_t:3;
-            vuint16_t EOC_AP:2; /* external offset correction application */
-            vuint16_t ERC_AP:2; /* external rate correction application */
-            vuint16_t BSY:1;    /* command write busy / write mode command */
-              vuint16_t:3;
-            vuint16_t POCCMD:4; /* protocol command */
-        } B;
-    } POCR_t;
-/* protocol commands */
-    typedef union uGIFER {
-        vuint16_t R;
-        struct {
-            vuint16_t MIF:1;    /* module interrupt flag */
-            vuint16_t PRIF:1;   /* protocol interrupt flag */
-            vuint16_t CHIF:1;   /* CHI interrupt flag */
-            vuint16_t WKUPIF:1; /* wakeup interrupt flag */
-            vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
-            vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
-            vuint16_t RBIF:1;   /* receive message buffer interrupt flag */
-            vuint16_t TBIF:1;   /* transmit buffer interrupt flag */
-            vuint16_t MIE:1;    /* module interrupt enable */
-            vuint16_t PRIE:1;   /* protocol interrupt enable */
-            vuint16_t CHIE:1;   /* CHI interrupt enable */
-            vuint16_t WKUPIE:1; /* wakeup interrupt enable */
-            vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
-            vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
-            vuint16_t RBIE:1;   /* receive message buffer interrupt enable */
-            vuint16_t TBIE:1;   /* transmit buffer interrupt enable */
-        } B;
-    } GIFER_t;
-    typedef union uPIFR0 {
-        vuint16_t R;
-        struct {
-            vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */
-            vuint16_t INTLIF:1; /* internal protocol error interrupt flag */
-            vuint16_t ILCFIF:1; /* illegal protocol configuration flag */
-            vuint16_t CSAIF:1;  /* cold start abort interrupt flag */
-            vuint16_t MRCIF:1;  /* missing rate correctio interrupt flag */
-            vuint16_t MOCIF:1;  /* missing offset correctio interrupt flag */
-            vuint16_t CCLIF:1;  /* clock correction limit reached interrupt flag */
-            vuint16_t MXSIF:1;  /* max sync frames detected interrupt flag */
-            vuint16_t MTXIF:1;  /* media access test symbol received flag */
-            vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
-            vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
-            vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
-            vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
-            vuint16_t TI2IF:1;  /* timer 2 expired interrupt flag */
-            vuint16_t TI1IF:1;  /* timer 1 expired interrupt flag */
-            vuint16_t CYSIF:1;  /* cycle start interrupt flag */
-        } B;
-    } PIFR0_t;
-    typedef union uPIFR1 {
-        vuint16_t R;
-        struct {
-            vuint16_t EMCIF:1;  /* error mode changed interrupt flag */
-            vuint16_t IPCIF:1;  /* illegal protocol command interrupt flag */
-            vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
-            vuint16_t PSCIF:1;  /* Protocol State Changed Interrupt Flag */
-            vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
-            vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
-            vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
-            vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
-              vuint16_t:2;
-            vuint16_t EVTIF:1;  /* even cycle table written interrupt flag */
-            vuint16_t ODTIF:1;  /* odd cycle table written interrupt flag */
-              vuint16_t:4;
-        } B;
-    } PIFR1_t;
-    typedef union uPIER0 {
-        vuint16_t R;
-        struct {
-            vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */
-            vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable  */
-            vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
-            vuint16_t CSAIE:1;  /* cold start abort interrupt enable */
-            vuint16_t MRCIE:1;  /* missing rate correctio interrupt enable */
-            vuint16_t MOCIE:1;  /* missing offset correctio interrupt enable */
-            vuint16_t CCLIE:1;  /* clock correction limit reached interrupt enable */
-            vuint16_t MXSIE:1;  /* max sync frames detected interrupt enable */
-            vuint16_t MTXIE:1;  /* media access test symbol received interrupt enable */
-            vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
-            vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
-            vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
-            vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
-            vuint16_t TI2IE:1;  /* timer 2 expired interrupt enable */
-            vuint16_t TI1IE:1;  /* timer 1 expired interrupt enable */
-            vuint16_t CYSIE:1;  /* cycle start interrupt enable */
-        } B;
-    } PIER0_t;
-    typedef union uPIER1 {
-        vuint16_t R;
-        struct {
-            vuint16_t EMCIE:1;  /* error mode changed interrupt enable */
-            vuint16_t IPCIE:1;  /* illegal protocol command interrupt enable */
-            vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
-            vuint16_t PSCIE:1;  /* Protocol State Changed Interrupt enable */
-            vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
-            vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
-            vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
-            vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
-              vuint16_t:2;
-            vuint16_t EVTIE:1;  /* even cycle table written interrupt enable */
-            vuint16_t ODTIE:1;  /* odd cycle table written interrupt enable */
-              vuint16_t:4;
-        } B;
-    } PIER1_t;
-    typedef union uCHIERFR {
-        vuint16_t R;
-        struct {
-            vuint16_t FRLBEF:1; /* flame lost channel B error flag */
-            vuint16_t FRLAEF:1; /* frame lost channel A error flag */
-            vuint16_t PCMIEF:1; /* command ignored error flag */
-            vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
-            vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
-            vuint16_t MSBEF:1;  /* message buffer search error flag */
-            vuint16_t MBUEF:1;  /* message buffer utilization error flag */
-            vuint16_t LCKEF:1;  /* lock error flag */
-            vuint16_t DBLEF:1;  /* double transmit message buffer lock error flag */
-            vuint16_t SBCFEF:1; /* system bus communication failure error flag */
-            vuint16_t FIDEF:1;  /* frame ID error flag */
-            vuint16_t DPLEF:1;  /* dynamic payload length error flag */
-            vuint16_t SPLEF:1;  /* static payload length error flag */
-            vuint16_t NMLEF:1;  /* network management length error flag */
-            vuint16_t NMFEF:1;  /* network management frame error flag */
-            vuint16_t ILSAEF:1; /* illegal access error flag */
-        } B;
-    } CHIERFR_t;
-    typedef union uMBIVEC {
-        vuint16_t R;
-        struct {
-
-            vuint16_t:1;
-            vuint16_t TBIVEC:7; /* transmit buffer interrupt vector */
-              vuint16_t:1;
-            vuint16_t RBIVEC:7; /* receive buffer interrupt vector */
-        } B;
-    } MBIVEC_t;
-
-    typedef union uPSR0 {
-        vuint16_t R;
-        struct {
-            vuint16_t ERRMODE:2;        /* error mode */
-            vuint16_t SLOTMODE:2;       /* slot mode */
-              vuint16_t:1;
-            vuint16_t PROTSTATE:3;      /* protocol state */
-            vuint16_t SUBSTATE:4;       /* protocol sub state */
-              vuint16_t:1;
-            vuint16_t WAKEUPSTATUS:3;   /* wakeup status */
-        } B;
-    } PSR0_t;
-
-/* protocol states */
-/* protocol sub-states */
-/* wakeup status */
-    typedef union uPSR1 {
-        vuint16_t R;
-        struct {
-            vuint16_t CSAA:1;   /* cold start attempt abort flag */
-            vuint16_t SCP:1;    /* cold start path */
-              vuint16_t:1;
-            vuint16_t REMCSAT:5;        /* remanining coldstart attempts */
-            vuint16_t CPN:1;    /* cold start noise path */
-            vuint16_t HHR:1;    /* host halt request pending */
-            vuint16_t FRZ:1;    /* freeze occured */
-            vuint16_t APTAC:5;  /* allow passive to active counter */
-        } B;
-    } PSR1_t;
-    typedef union uPSR2 {
-        vuint16_t R;
-        struct {
-            vuint16_t NBVB:1;   /* NIT boundary violation on channel B */
-            vuint16_t NSEB:1;   /* NIT syntax error on channel B */
-            vuint16_t STCB:1;   /* symbol window transmit conflict on channel B */
-            vuint16_t SBVB:1;   /* symbol window boundary violation on channel B */
-            vuint16_t SSEB:1;   /* symbol window syntax error on channel B */
-            vuint16_t MTB:1;    /* media access test symbol MTS received on channel B */
-            vuint16_t NBVA:1;   /* NIT boundary violation on channel A */
-            vuint16_t NSEA:1;   /* NIT syntax error on channel A */
-            vuint16_t STCA:1;   /* symbol window transmit conflict on channel A */
-            vuint16_t SBVA:1;   /* symbol window boundary violation on channel A */
-            vuint16_t SSEA:1;   /* symbol window syntax error on channel A */
-            vuint16_t MTA:1;    /* media access test symbol MTS received on channel A */
-            vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
-        } B;
-    } PSR2_t;
-    typedef union uPSR3 {
-        vuint16_t R;
-        struct {
-            vuint16_t:2;
-            vuint16_t WUB:1;    /* wakeup symbol received on channel B */
-            vuint16_t ABVB:1;   /* aggregated boundary violation on channel B */
-            vuint16_t AACB:1;   /* aggregated additional communication on channel B */
-            vuint16_t ACEB:1;   /* aggregated content error on channel B */
-            vuint16_t ASEB:1;   /* aggregated syntax error on channel B */
-            vuint16_t AVFB:1;   /* aggregated valid frame on channel B */
-              vuint16_t:2;
-            vuint16_t WUA:1;    /* wakeup symbol received on channel A */
-            vuint16_t ABVA:1;   /* aggregated boundary violation on channel A */
-            vuint16_t AACA:1;   /* aggregated additional communication on channel A */
-            vuint16_t ACEA:1;   /* aggregated content error on channel A */
-            vuint16_t ASEA:1;   /* aggregated syntax error on channel A */
-            vuint16_t AVFA:1;   /* aggregated valid frame on channel A */
-        } B;
-    } PSR3_t;
-    typedef union uCIFRR {
-        vuint16_t R;
-        struct {
-            vuint16_t:8;
-            vuint16_t MIFR:1;   /* module interrupt flag */
-            vuint16_t PRIFR:1;  /* protocol interrupt flag */
-            vuint16_t CHIFR:1;  /* CHI interrupt flag */
-            vuint16_t WUPIFR:1; /* wakeup interrupt flag */
-            vuint16_t FNEBIFR:1;        /* receive fifo channel B no empty interrupt flag */
-            vuint16_t FNEAIFR:1;        /* receive fifo channel A no empty interrupt flag */
-            vuint16_t RBIFR:1;  /* receive message buffer interrupt flag */
-            vuint16_t TBIFR:1;  /* transmit buffer interrupt flag */
-        } B;
-    } CIFRR_t;
-    typedef union uSFCNTR {
-        vuint16_t R;
-        struct {
-            vuint16_t SFEVB:4;  /* sync frames channel B, even cycle */
-            vuint16_t SFEVA:4;  /* sync frames channel A, even cycle */
-            vuint16_t SFODB:4;  /* sync frames channel B, odd cycle */
-            vuint16_t SFODA:4;  /* sync frames channel A, odd cycle */
-        } B;
-    } SFCNTR_t;
-
-    typedef union uSFTCCSR {
-        vuint16_t R;
-        struct {
-            vuint16_t ELKT:1;   /* even cycle tables lock and unlock trigger */
-            vuint16_t OLKT:1;   /* odd cycle tables lock and unlock trigger */
-            vuint16_t CYCNUM:6; /* cycle number */
-            vuint16_t ELKS:1;   /* even cycle tables lock status */
-            vuint16_t OLKS:1;   /* odd cycle tables lock status */
-            vuint16_t EVAL:1;   /* even cycle tables valid */
-            vuint16_t OVAL:1;   /* odd cycle tables valid */
-              vuint16_t:1;
-            vuint16_t OPT:1;    /*one pair trigger */
-            vuint16_t SDVEN:1;  /* sync frame deviation table enable */
-            vuint16_t SIDEN:1;  /* sync frame ID table enable */
-        } B;
-    } SFTCCSR_t;
-    typedef union uSFIDRFR {
-        vuint16_t R;
-        struct {
-            vuint16_t:6;
-            vuint16_t SYNFRID:10;       /* sync frame rejection ID */
-        } B;
-    } SFIDRFR_t;
-
-    typedef union uTICCR {
-        vuint16_t R;
-        struct {
-            vuint16_t:2;
-            vuint16_t T2CFG:1;  /* timer 2 configuration */
-            vuint16_t T2REP:1;  /* timer 2 repetitive mode */
-              vuint16_t:1;
-            vuint16_t T2SP:1;   /* timer 2 stop */
-            vuint16_t T2TR:1;   /* timer 2 trigger */
-            vuint16_t T2ST:1;   /* timer 2 state */
-              vuint16_t:3;
-            vuint16_t T1REP:1;  /* timer 1 repetitive mode */
-              vuint16_t:1;
-            vuint16_t T1SP:1;   /* timer 1 stop */
-            vuint16_t T1TR:1;   /* timer 1 trigger */
-            vuint16_t T1ST:1;   /* timer 1 state */
-
-        } B;
-    } TICCR_t;
-    typedef union uTI1CYSR {
-        vuint16_t R;
-        struct {
-            vuint16_t:2;
-            vuint16_t TI1CYCVAL:6;      /* timer 1 cycle filter value */
-              vuint16_t:2;
-            vuint16_t TI1CYCMSK:6;      /* timer 1 cycle filter mask */
-
-        } B;
-    } TI1CYSR_t;
-
-    typedef union uSSSR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-              vuint16_t:1;
-            vuint16_t SEL:2;    /* static slot number */
-              vuint16_t:1;
-            vuint16_t SLOTNUMBER:11;    /* selector */
-        } B;
-    } SSSR_t;
-
-    typedef union uSSCCR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-              vuint16_t:1;
-            vuint16_t SEL:2;    /* selector */
-              vuint16_t:1;
-            vuint16_t CNTCFG:2; /* counter configuration */
-            vuint16_t MCY:1;    /* multi cycle selection */
-            vuint16_t VFR:1;    /* valid frame selection */
-            vuint16_t SYF:1;    /* sync frame selection */
-            vuint16_t NUF:1;    /* null frame selection  */
-            vuint16_t SUF:1;    /* startup frame selection */
-            vuint16_t STATUSMASK:4;     /* slot status mask */
-        } B;
-    } SSCCR_t;
-    typedef union uSSR {
-        vuint16_t R;
-        struct {
-            vuint16_t VFB:1;    /* valid frame on channel B */
-            vuint16_t SYB:1;    /* valid sync frame on channel B */
-            vuint16_t NFB:1;    /* valid null frame on channel B */
-            vuint16_t SUB:1;    /* valid startup frame on channel B */
-            vuint16_t SEB:1;    /* syntax error on channel B */
-            vuint16_t CEB:1;    /* content error on channel B */
-            vuint16_t BVB:1;    /* boundary violation on channel B */
-            vuint16_t TCB:1;    /* tx conflict on channel B */
-            vuint16_t VFA:1;    /* valid frame on channel A */
-            vuint16_t SYA:1;    /* valid sync frame on channel A */
-            vuint16_t NFA:1;    /* valid null frame on channel A */
-            vuint16_t SUA:1;    /* valid startup frame on channel A */
-            vuint16_t SEA:1;    /* syntax error on channel A */
-            vuint16_t CEA:1;    /* content error on channel A */
-            vuint16_t BVA:1;    /* boundary violation on channel A */
-            vuint16_t TCA:1;    /* tx conflict on channel A */
-        } B;
-    } SSR_t;
-    typedef union uMTSCFR {
-        vuint16_t R;
-        struct {
-            vuint16_t MTE:1;    /* media access test symbol transmission enable */
-              vuint16_t:1;
-            vuint16_t CYCCNTMSK:6;      /* cycle counter mask */
-              vuint16_t:2;
-            vuint16_t CYCCNTVAL:6;      /* cycle counter value */
-        } B;
-    } MTSCFR_t;
-    typedef union uRSBIR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-              vuint16_t:1;
-            vuint16_t SEL:2;    /* selector */
-              vuint16_t:4;
-            vuint16_t RSBIDX:8; /* receive shadow buffer index */
-        } B;
-    } RSBIR_t;
-    typedef union uRFDSR {
-        vuint16_t R;
-        struct {
-            vuint16_t FIFODEPTH:8;      /* fifo depth */
-              vuint16_t:1;
-            vuint16_t ENTRYSIZE:7;      /* entry size */
-        } B;
-    } RFDSR_t;
-
-    typedef union uRFRFCFR {
-        vuint16_t R;
-        struct {
-            vuint16_t WMD:1;    /* write mode */
-            vuint16_t IBD:1;    /* interval boundary */
-            vuint16_t SEL:2;    /* filter number */
-              vuint16_t:1;
-            vuint16_t SID:11;   /* slot ID */
-        } B;
-    } RFRFCFR_t;
-
-    typedef union uRFRFCTR {
-        vuint16_t R;
-        struct {
-            vuint16_t:4;
-            vuint16_t F3MD:1;   /* filter mode */
-            vuint16_t F2MD:1;   /* filter mode */
-            vuint16_t F1MD:1;   /* filter mode */
-            vuint16_t F0MD:1;   /* filter mode */
-              vuint16_t:4;
-            vuint16_t F3EN:1;   /* filter enable */
-            vuint16_t F2EN:1;   /* filter enable */
-            vuint16_t F1EN:1;   /* filter enable */
-            vuint16_t F0EN:1;   /* filter enable */
-        } B;
-    } RFRFCTR_t;
-    typedef union uPCR0 {
-        vuint16_t R;
-        struct {
-            vuint16_t ACTION_POINT_OFFSET:6;
-            vuint16_t STATIC_SLOT_LENGTH:10;
-        } B;
-    } PCR0_t;
-
-    typedef union uPCR1 {
-        vuint16_t R;
-        struct {
-            vuint16_t:2;
-            vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
-        } B;
-    } PCR1_t;
-
-    typedef union uPCR2 {
-        vuint16_t R;
-        struct {
-            vuint16_t MINISLOT_AFTER_ACTION_POINT:6;
-            vuint16_t NUMBER_OF_STATIC_SLOTS:10;
-        } B;
-    } PCR2_t;
-
-    typedef union uPCR3 {
-        vuint16_t R;
-        struct {
-            vuint16_t WAKEUP_SYMBOL_RX_LOW:6;
-            vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;
-            vuint16_t COLDSTART_ATTEMPTS:5;
-        } B;
-    } PCR3_t;
-
-    typedef union uPCR4 {
-        vuint16_t R;
-        struct {
-            vuint16_t CAS_RX_LOW_MAX:7;
-            vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
-        } B;
-    } PCR4_t;
-
-    typedef union uPCR5 {
-        vuint16_t R;
-        struct {
-            vuint16_t TSS_TRANSMITTER:4;
-            vuint16_t WAKEUP_SYMBOL_TX_LOW:6;
-            vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;
-        } B;
-    } PCR5_t;
-
-    typedef union uPCR6 {
-        vuint16_t R;
-        struct {
-            vuint16_t:1;
-            vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
-            vuint16_t MACRO_INITIAL_OFFSET_A:7;
-        } B;
-    } PCR6_t;
-
-    typedef union uPCR7 {
-        vuint16_t R;
-        struct {
-            vuint16_t DECODING_CORRECTION_B:9;
-            vuint16_t MICRO_PER_MACRO_NOM_HALF:7;
-        } B;
-    } PCR7_t;
-
-    typedef union uPCR8 {
-        vuint16_t R;
-        struct {
-            vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
-            vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
-            vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;
-        } B;
-    } PCR8_t;
-
-    typedef union uPCR9 {
-        vuint16_t R;
-        struct {
-            vuint16_t MINISLOT_EXISTS:1;
-            vuint16_t SYMBOL_WINDOW_EXISTS:1;
-            vuint16_t OFFSET_CORRECTION_OUT:14;
-        } B;
-    } PCR9_t;
-
-    typedef union uPCR10 {
-        vuint16_t R;
-        struct {
-            vuint16_t SINGLE_SLOT_ENABLED:1;
-            vuint16_t WAKEUP_CHANNEL:1;
-            vuint16_t MACRO_PER_CYCLE:14;
-        } B;
-    } PCR10_t;
-
-    typedef union uPCR11 {
-        vuint16_t R;
-        struct {
-            vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;
-            vuint16_t KEY_SLOT_USED_FOR_SYNC:1;
-            vuint16_t OFFSET_CORRECTION_START:14;
-        } B;
-    } PCR11_t;
-
-    typedef union uPCR12 {
-        vuint16_t R;
-        struct {
-            vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
-            vuint16_t KEY_SLOT_HEADER_CRC:11;
-        } B;
-    } PCR12_t;
-
-    typedef union uPCR13 {
-        vuint16_t R;
-        struct {
-            vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
-            vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
-        } B;
-    } PCR13_t;
-
-    typedef union uPCR14 {
-        vuint16_t R;
-        struct {
-            vuint16_t RATE_CORRECTION_OUT:11;
-            vuint16_t LISTEN_TIMEOUT_H:5;
-        } B;
-    } PCR14_t;
-
-    typedef union uPCR15 {
-        vuint16_t R;
-        struct {
-            vuint16_t LISTEN_TIMEOUT_L:16;
-        } B;
-    } PCR15_t;
-
-    typedef union uPCR16 {
-        vuint16_t R;
-        struct {
-            vuint16_t MACRO_INITIAL_OFFSET_B:7;
-            vuint16_t NOISE_LISTEN_TIMEOUT_H:9;
-        } B;
-    } PCR16_t;
-
-    typedef union uPCR17 {
-        vuint16_t R;
-        struct {
-            vuint16_t NOISE_LISTEN_TIMEOUT_L:16;
-        } B;
-    } PCR17_t;
-
-    typedef union uPCR18 {
-        vuint16_t R;
-        struct {
-            vuint16_t WAKEUP_PATTERN:6;
-            vuint16_t KEY_SLOT_ID:10;
-        } B;
-    } PCR18_t;
-
-    typedef union uPCR19 {
-        vuint16_t R;
-        struct {
-            vuint16_t DECODING_CORRECTION_A:9;
-            vuint16_t PAYLOAD_LENGTH_STATIC:7;
-        } B;
-    } PCR19_t;
-
-    typedef union uPCR20 {
-        vuint16_t R;
-        struct {
-            vuint16_t MICRO_INITIAL_OFFSET_B:8;
-            vuint16_t MICRO_INITIAL_OFFSET_A:8;
-        } B;
-    } PCR20_t;
-
-    typedef union uPCR21 {
-        vuint16_t R;
-        struct {
-            vuint16_t EXTERN_RATE_CORRECTION:3;
-            vuint16_t LATEST_TX:13;
-        } B;
-    } PCR21_t;
-
-    typedef union uPCR22 {
-        vuint16_t R;
-        struct {
-            vuint16_t:1;
-            vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
-            vuint16_t MICRO_PER_CYCLE_H:4;
-        } B;
-    } PCR22_t;
-
-    typedef union uPCR23 {
-        vuint16_t R;
-        struct {
-            vuint16_t micro_per_cycle_l:16;
-        } B;
-    } PCR23_t;
-
-    typedef union uPCR24 {
-        vuint16_t R;
-        struct {
-            vuint16_t CLUSTER_DRIFT_DAMPING:5;
-            vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
-            vuint16_t MICRO_PER_CYCLE_MIN_H:4;
-        } B;
-    } PCR24_t;
-
-    typedef union uPCR25 {
-        vuint16_t R;
-        struct {
-            vuint16_t MICRO_PER_CYCLE_MIN_L:16;
-        } B;
-    } PCR25_t;
-
-    typedef union uPCR26 {
-        vuint16_t R;
-        struct {
-            vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
-            vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
-            vuint16_t MICRO_PER_CYCLE_MAX_H:4;
-        } B;
-    } PCR26_t;
-
-    typedef union uPCR27 {
-        vuint16_t R;
-        struct {
-            vuint16_t MICRO_PER_CYCLE_MAX_L:16;
-        } B;
-    } PCR27_t;
-
-    typedef union uPCR28 {
-        vuint16_t R;
-        struct {
-            vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
-            vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
-        } B;
-    } PCR28_t;
-
-    typedef union uPCR29 {
-        vuint16_t R;
-        struct {
-            vuint16_t EXTERN_OFFSET_CORRECTION:3;
-            vuint16_t MINISLOTS_MAX:13;
-        } B;
-    } PCR29_t;
-
-    typedef union uPCR30 {
-        vuint16_t R;
-        struct {
-            vuint16_t:12;
-            vuint16_t SYNC_NODE_MAX:4;
-        } B;
-    } PCR30_t;
-
-    typedef struct uMSG_BUFF_CCS {
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:1;
-                vuint16_t MCM:1;        /* message buffer commit mode */
-                vuint16_t MBT:1;        /* message buffer type */
-                vuint16_t MTD:1;        /* message buffer direction */
-                vuint16_t CMT:1;        /* commit for transmission */
-                vuint16_t EDT:1;        /* enable / disable trigger */
-                vuint16_t LCKT:1;       /* lock request trigger */
-                vuint16_t MBIE:1;       /* message buffer interrupt enable */
-                  vuint16_t:3;
-                vuint16_t DUP:1;        /* data updated  */
-                vuint16_t DVAL:1;       /* data valid */
-                vuint16_t EDS:1;        /* lock status */
-                vuint16_t LCKS:1;       /* enable / disable status */
-                vuint16_t MBIF:1;       /* message buffer interrupt flag */
-            } B;
-        } MBCCSR;
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t MTM:1;        /* message buffer transmission mode */
-                vuint16_t CHNLA:1;      /* channel assignement */
-                vuint16_t CHNLB:1;      /* channel assignement */
-                vuint16_t CCFE:1;       /* cycle counter filter enable */
-                vuint16_t CCFMSK:6;     /* cycle counter filter mask */
-                vuint16_t CCFVAL:6;     /* cycle counter filter value */
-            } B;
-        } MBCCFR;
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:5;
-                vuint16_t FID:11;       /* frame ID */
-            } B;
-        } MBFIDR;
-        union {
-            vuint16_t R;
-            struct {
-                vuint16_t:8;
-                vuint16_t MBIDX:8;      /* message buffer index */
-            } B;
-        } MBIDXR;
-    } MSG_BUFF_CCS_t;
-    typedef union uSYSBADHR {
-        vuint16_t R;
-    } SYSBADHR_t;
-    typedef union uSYSBADLR {
-        vuint16_t R;
-    } SYSBADLR_t;
-    typedef union uPDAR {
-        vuint16_t R;
-    } PDAR_t;
-    typedef union uCASERCR {
-        vuint16_t R;
-    } CASERCR_t;
-    typedef union uCBSERCR {
-        vuint16_t R;
-    } CBSERCR_t;
-    typedef union uCYCTR {
-        vuint16_t R;
-    } CYCTR_t;
-    typedef union uMTCTR {
-        vuint16_t R;
-    } MTCTR_t;
-    typedef union uSLTCTAR {
-        vuint16_t R;
-    } SLTCTAR_t;
-    typedef union uSLTCTBR {
-        vuint16_t R;
-    } SLTCTBR_t;
-    typedef union uRTCORVR {
-        vuint16_t R;
-    } RTCORVR_t;
-    typedef union uOFCORVR {
-        vuint16_t R;
-    } OFCORVR_t;
-    typedef union uSFTOR {
-        vuint16_t R;
-    } SFTOR_t;
-    typedef union uSFIDAFVR {
-        vuint16_t R;
-    } SFIDAFVR_t;
-    typedef union uSFIDAFMR {
-        vuint16_t R;
-    } SFIDAFMR_t;
-    typedef union uNMVR {
-        vuint16_t R;
-    } NMVR_t;
-    typedef union uNMVLR {
-        vuint16_t R;
-    } NMVLR_t;
-    typedef union uT1MTOR {
-        vuint16_t R;
-    } T1MTOR_t;
-    typedef union uTI2CR0 {
-        vuint16_t R;
-    } TI2CR0_t;
-    typedef union uTI2CR1 {
-        vuint16_t R;
-    } TI2CR1_t;
-    typedef union uSSCR {
-        vuint16_t R;
-    } SSCR_t;
-    typedef union uRFSR {
-        vuint16_t R;
-    } RFSR_t;
-    typedef union uRFSIR {
-        vuint16_t R;
-    } RFSIR_t;
-    typedef union uRFARIR {
-        vuint16_t R;
-    } RFARIR_t;
-    typedef union uRFBRIR {
-        vuint16_t R;
-    } RFBRIR_t;
-    typedef union uRFMIDAFVR {
-        vuint16_t R;
-    } RFMIDAFVR_t;
-    typedef union uRFMIAFMR {
-        vuint16_t R;
-    } RFMIAFMR_t;
-    typedef union uRFFIDRFVR {
-        vuint16_t R;
-    } RFFIDRFVR_t;
-    typedef union uRFFIDRFMR {
-        vuint16_t R;
-    } RFFIDRFMR_t;
-    typedef union uLDTXSLAR {
-        vuint16_t R;
-    } LDTXSLAR_t;
-    typedef union uLDTXSLBR {
-        vuint16_t R;
-    } LDTXSLBR_t;
-
-    typedef struct FR_tag {
-        volatile MVR_t MVR;     /*module version register *//*0  */
-        volatile MCR_t MCR;     /*module configuration register *//*2  */
-        volatile SYSBADHR_t SYSBADHR;   /*system memory base address high register *//*4        */
-        volatile SYSBADLR_t SYSBADLR;   /*system memory base address low register *//*6         */
-        volatile STBSCR_t STBSCR;       /*strobe signal control register *//*8      */
-        volatile STBPCR_t STBPCR;       /*strobe port control register *//*A        */
-        volatile MBDSR_t MBDSR; /*message buffer data size register *//*C  */
-        volatile MBSSUTR_t MBSSUTR;     /*message buffer segment size and utilization register *//*E  */
-        vuint16_t reserved3a[1];        /*10 */
-        volatile PDAR_t PDAR;   /*PE data register *//*12 */
-        volatile POCR_t POCR;   /*Protocol operation control register *//*14 */
-        volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
-        volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
-        volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
-        volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
-        volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
-        volatile CHIERFR_t CHIERFR;     /*CHI error flag register *//*20 */
-        volatile MBIVEC_t MBIVEC;       /*message buffer interrupt vector register *//*22 */
-        volatile CASERCR_t CASERCR;     /*channel A status error counter register *//*24 */
-        volatile CBSERCR_t CBSERCR;     /*channel B status error counter register *//*26 */
-        volatile PSR0_t PSR0;   /*protocol status register 0 *//*28 */
-        volatile PSR1_t PSR1;   /*protocol status register 1 *//*2A */
-        volatile PSR2_t PSR2;   /*protocol status register 2 *//*2C */
-        volatile PSR3_t PSR3;   /*protocol status register 3 *//*2E */
-        volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
-        volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
-        volatile SLTCTAR_t SLTCTAR;     /*slot counter channel A register *//*34 */
-        volatile SLTCTBR_t SLTCTBR;     /*slot counter channel B register *//*36 */
-        volatile RTCORVR_t RTCORVR;     /*rate correction value register *//*38 */
-        volatile OFCORVR_t OFCORVR;     /*offset correction value register *//*3A */
-        volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
-        vuint16_t reserved3[1]; /*3E */
-        volatile SFCNTR_t SFCNTR;       /*sync frame counter register *//*40 */
-        volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
-        volatile SFTCCSR_t SFTCCSR;     /*sync frame table configuration, control, status register *//*44 */
-        volatile SFIDRFR_t SFIDRFR;     /*sync frame ID rejection filter register *//*46 */
-        volatile SFIDAFVR_t SFIDAFVR;   /*sync frame ID acceptance filter value regiater *//*48 */
-        volatile SFIDAFMR_t SFIDAFMR;   /*sync frame ID acceptance filter mask register *//*4A */
-        volatile NMVR_t NMVR[6];        /*network management vector registers (12 bytes) *//*4C */
-        volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
-        volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
-        volatile TI1CYSR_t TI1CYSR;     /*timer 1 cycle set register *//*5C */
-        volatile T1MTOR_t T1MTOR;       /*timer 1 macrotick offset register *//*5E */
-        volatile TI2CR0_t TI2CR0;       /*timer 2 configuration register 0 *//*60 */
-        volatile TI2CR1_t TI2CR1;       /*timer 2 configuration register 1 *//*62 */
-        volatile SSSR_t SSSR;   /*slot status selection register *//*64 */
-        volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
-        volatile SSR_t SSR[8];  /*slot status registers 0-7 *//*68 */
-        volatile SSCR_t SSCR[4];        /*slot status counter registers 0-3 *//*78 */
-        volatile MTSCFR_t MTSACFR;      /*mts a config register *//*80 */
-        volatile MTSCFR_t MTSBCFR;      /*mts b config register *//*82 */
-        volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
-        volatile RFSR_t RFSR;   /*receive fifo selection register *//*86 */
-        volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
-        volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
-        volatile RFARIR_t RFARIR;       /*receive fifo a read index register *//*8C */
-        volatile RFBRIR_t RFBRIR;       /*receive fifo b read index register *//*8E */
-        volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
-        volatile RFMIAFMR_t RFMIAFMR;   /*receive fifo message ID acceptance filter mask register *//*92 */
-        volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
-        volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
-        volatile RFRFCFR_t RFRFCFR;     /*receive fifo range filter configuration register *//*98 */
-        volatile RFRFCTR_t RFRFCTR;     /*receive fifo range filter control register *//*9A */
-        volatile LDTXSLAR_t LDTXSLAR;   /*last dynamic transmit slot channel A register *//*9C */
-        volatile LDTXSLBR_t LDTXSLBR;   /*last dynamic transmit slot channel B register *//*9E */
-        volatile PCR0_t PCR0;   /*protocol configuration register 0 *//*A0 */
-        volatile PCR1_t PCR1;   /*protocol configuration register 1 *//*A2 */
-        volatile PCR2_t PCR2;   /*protocol configuration register 2 *//*A4 */
-        volatile PCR3_t PCR3;   /*protocol configuration register 3 *//*A6 */
-        volatile PCR4_t PCR4;   /*protocol configuration register 4 *//*A8 */
-        volatile PCR5_t PCR5;   /*protocol configuration register 5 *//*AA */
-        volatile PCR6_t PCR6;   /*protocol configuration register 6 *//*AC */
-        volatile PCR7_t PCR7;   /*protocol configuration register 7 *//*AE */
-        volatile PCR8_t PCR8;   /*protocol configuration register 8 *//*B0 */
-        volatile PCR9_t PCR9;   /*protocol configuration register 9 *//*B2 */
-        volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
-        volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
-        volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
-        volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
-        volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
-        volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
-        volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
-        volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
-        volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
-        volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
-        volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
-        volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
-        volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
-        volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
-        volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
-        volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
-        volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
-        volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
-        volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
-        volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
-        volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
-        vuint16_t reserved2[17];
-        volatile MSG_BUFF_CCS_t MBCCS[128];     /* message buffer configuration, control & status registers 0-31 *//*100 */
-    } FR_tag_t;
-
-    typedef union uF_HEADER     /* frame header */
-    {
-        struct {
-            vuint16_t:5;
-            vuint16_t HDCRC:11; /* Header CRC */
-              vuint16_t:2;
-            vuint16_t CYCCNT:6; /* Cycle Count */
-              vuint16_t:1;
-            vuint16_t PLDLEN:7; /* Payload Length */
-              vuint16_t:1;
-            vuint16_t PPI:1;    /* Payload Preamble Indicator */
-            vuint16_t NUF:1;    /* Null Frame Indicator */
-            vuint16_t SYF:1;    /* Sync Frame Indicator */
-            vuint16_t SUF:1;    /* Startup Frame Indicator */
-            vuint16_t FID:11;   /* Frame ID */
-        } B;
-        vuint16_t WORDS[3];
-    } F_HEADER_t;
-    typedef union uS_STSTUS     /* slot status */
-    {
-        struct {
-            vuint16_t VFB:1;    /* Valid Frame on channel B */
-            vuint16_t SYB:1;    /* Sync Frame Indicator channel B */
-            vuint16_t NFB:1;    /* Null Frame Indicator channel B */
-            vuint16_t SUB:1;    /* Startup Frame Indicator channel B */
-            vuint16_t SEB:1;    /* Syntax Error on channel B */
-            vuint16_t CEB:1;    /* Content Error on channel B */
-            vuint16_t BVB:1;    /* Boundary Violation on channel B */
-            vuint16_t CH:1;     /* Channel */
-            vuint16_t VFA:1;    /* Valid Frame on channel A */
-            vuint16_t SYA:1;    /* Sync Frame Indicator channel A */
-            vuint16_t NFA:1;    /* Null Frame Indicator channel A */
-            vuint16_t SUA:1;    /* Startup Frame Indicator channel A */
-            vuint16_t SEA:1;    /* Syntax Error on channel A */
-            vuint16_t CEA:1;    /* Content Error on channel A */
-            vuint16_t BVA:1;    /* Boundary Violation on channel A */
-              vuint16_t:1;
-        } RX;
-        struct {
-            vuint16_t VFB:1;    /* Valid Frame on channel B */
-            vuint16_t SYB:1;    /* Sync Frame Indicator channel B */
-            vuint16_t NFB:1;    /* Null Frame Indicator channel B */
-            vuint16_t SUB:1;    /* Startup Frame Indicator channel B */
-            vuint16_t SEB:1;    /* Syntax Error on channel B */
-            vuint16_t CEB:1;    /* Content Error on channel B */
-            vuint16_t BVB:1;    /* Boundary Violation on channel B */
-            vuint16_t TCB:1;    /* Tx Conflict on channel B */
-            vuint16_t VFA:1;    /* Valid Frame on channel A */
-            vuint16_t SYA:1;    /* Sync Frame Indicator channel A */
-            vuint16_t NFA:1;    /* Null Frame Indicator channel A */
-            vuint16_t SUA:1;    /* Startup Frame Indicator channel A */
-            vuint16_t SEA:1;    /* Syntax Error on channel A */
-            vuint16_t CEA:1;    /* Content Error on channel A */
-            vuint16_t BVA:1;    /* Boundary Violation on channel A */
-            vuint16_t TCA:1;    /* Tx Conflict on channel A */
-        } TX;
-        vuint16_t R;
-    } S_STATUS_t;
-
-    typedef struct uMB_HEADER   /* message buffer header */
-    {
-        F_HEADER_t FRAME_HEADER;
-        vuint16_t DATA_OFFSET;
-        S_STATUS_t SLOT_STATUS;
-    } MB_HEADER_t;
-
-/****************************************************************************/
-/*                     MODULE : Power Management Controller (PMC)           */
-/****************************************************************************/
-    struct PMC_tag {
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t LVRER:1;
-                vuint32_t LVREH:1;
-                vuint32_t LVRE50:1;
-                vuint32_t LVRE33:1;
-                vuint32_t LVREC:1;
-                  vuint32_t:3;
-                vuint32_t LVIER:1;
-                vuint32_t LVIEH:1;
-                vuint32_t LVIE50:1;
-                vuint32_t LVIE33:1;
-                vuint32_t LVIC:1;
-                  vuint32_t:2;
-                vuint32_t TLK:1;
-                  vuint32_t:16;
-            } B;
-        } MCR;                  /* Module Configuration register @baseaddress + 0x00 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:12;
-                vuint32_t LVDREGTRIM:4;
-                vuint32_t VDD33TRIM:4;
-                vuint32_t LVD33TRIM:4;
-                vuint32_t VDDCTRIM:4;
-                vuint32_t LVDCTRIM:4;
-            } B;
-        } TRIMR;                /* Trimming register @baseaddress + 0x00 */
-
-        union {
-            vuint32_t R;
-            struct {
-                vuint32_t:5;
-                vuint32_t LVFVSTBY:1;
-                vuint32_t BGRDY:1;
-                vuint32_t BGTS:1;
-                  vuint32_t:5;
-                vuint32_t LVFCSTBY:1;
-                  vuint32_t:1;
-                vuint32_t V33DIS:1;
-                vuint32_t LVFCR:1;
-                vuint32_t LVFCH:1;
-                vuint32_t LVFC50:1;
-                vuint32_t LVFC33:1;
-                vuint32_t LVFCC:1;
-                  vuint32_t:3;
-                vuint32_t LVFR:1;
-                vuint32_t LVFH:1;
-                vuint32_t LVF50:1;
-                vuint32_t LVF33:1;
-                vuint32_t LVFC:1;
-                  vuint32_t:3;
-
-            } B;
-        } SR;                   /* status register @baseaddress + 0x00 */
-    };
-
-/****************************************************************************/
-/*                          MODULE : MPU                                    */
-/****************************************************************************/
-
-    struct MPU_tag {
-
-        union {                 /* Module Control/Error Status Register */
-            vuint32_t R;
-            struct {
-                vuint32_t SPERR:8;
-                  vuint32_t:4;
-                vuint32_t HRL:4;
-                vuint32_t NSP:4;
-                vuint32_t NRGD:4;
-                  vuint32_t:7;
-                vuint32_t VLD:1;
-            } B;
-        } CESR;
-
-        uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */
-
-        struct {
-            union {             /* MPU Error Address Registers */
-                vuint32_t R;
-                struct {
-                    vuint32_t EADDR:32;
-                } B;
-            } EAR;
-
-            union {             /* MPU Error Detail Registers */
-                vuint32_t R;
-                struct {
-                    vuint32_t EACD:16;
-                    vuint32_t EPID:8;
-                    vuint32_t EMN:4;
-                    vuint32_t EATTR:3;
-                    vuint32_t ERW:1;
-                } B;
-            } EDR;
-        } PORT[2];
-
-        uint32_t MPU_reserved0020[248];  /* 0x0020-0x03FF */
-
-        struct {
-            union {            /* Region Descriptor n Word 0 */
-                vuint32_t R;
-                struct {
-                    vuint32_t SRTADDR:27;
-                    vuint32_t:5;
-                } B;
-            } WORD0;
-
-            union {            /* Region Descriptor n Word 1 */
-                vuint32_t R;
-                struct {
-                    vuint32_t ENDADDR:27;
-                    vuint32_t:5;
-                } B;
-            } WORD1;
-
-            union {            /* Region Descriptor n Word 2 */
-                vuint32_t R;
-                struct {
-                    vuint32_t M7RE:1;
-                    vuint32_t M7WE:1;
-                    vuint32_t M6RE:1;
-                    vuint32_t M6WE:1;
-                    vuint32_t:2;
-                    vuint32_t M4RE:1;
-                    vuint32_t M4WE:1;
-                    vuint32_t M3PE:1;
-                    vuint32_t M3SM:2;
-                    vuint32_t M3UM:3;
-                    vuint32_t M2PE:1;
-                    vuint32_t M2SM:2;
-                    vuint32_t M2UM:3;
-                    vuint32_t M1PE:1;
-                    vuint32_t M1SM:2;
-                    vuint32_t M1UM:3;
-                    vuint32_t M0PE:1;
-                    vuint32_t M0SM:2;
-                    vuint32_t M0UM:3;
-                } B;
-            } WORD2;
-
-            union {            /* Region Descriptor n Word 3 */
-                vuint32_t R;
-                struct {
-                    vuint32_t PID:8;
-                    vuint32_t PIDMASK:8;
-                      vuint32_t:15;
-                    vuint32_t VLD:1;
-                } B;
-            } WORD3;
-        } RGD[16];
-
-        uint32_t MPU_reserved0500[192];  /* 0x0500-0x07FF */
-
-        union {           /* Region Descriptor Alternate Access Control n */
-            vuint32_t R;
-            struct {
-                vuint32_t M7RE:1;
-                vuint32_t M7WE:1;
-                vuint32_t M6RE:1;
-                vuint32_t M6WE:1;
-                vuint32_t:2;
-                vuint32_t M4RE:1;
-                vuint32_t M4WE:1;
-                vuint32_t M3PE:1;
-                vuint32_t M3SM:2;
-                vuint32_t M3UM:3;
-                vuint32_t M2PE:1;
-                vuint32_t M2SM:2;
-                vuint32_t M2UM:3;
-                vuint32_t M1PE:1;
-                vuint32_t M1SM:2;
-                vuint32_t M1UM:3;
-                vuint32_t M0PE:1;
-                vuint32_t M0SM:2;
-                vuint32_t M0UM:3;
-            } B;
-        } RGDAAC[16];
-
-        uint32_t MPU_reserved0840[3568];  /* 0x0840-0x3FFF */
-
-    };
-
-/****************************************************************************/
-/*                          MODULE : TSENS (Temperature Sensor)             */
-/****************************************************************************/
-
-    struct TSENS_tag {
-
-        union {                
-            vuint32_t R;
-            struct {
-                vuint32_t TSCV2:16;
-                vuint32_t TSCV1:16;
-            } B;
-        } TCCR0;                 /* Temperature Sensor Calibration B @baseaddress + 0x00 */
-
-        union {                
-            vuint32_t R;
-            struct {
-                 vuint32_t:16;
-                vuint32_t TSCV3:16;
-            } B;    
-        } TCCR1;                 /* Temperature Sensor Calibration A @baseaddress + 0x04 */
-        
-        uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */
-
-    };
-
-/****************************************************************************/
-/*					   MODULE : DTS (Development Trigger Semaphor)          */
-/****************************************************************************/
-    struct DTS_tag {
-	    
-	  union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:31;
-	      	  vuint32_t DTS_EN:1;
-		  }B;  
-  	  } ENABLE; 					/* DTS Output Enable Register @baseaddress + 0x0 */
-
-	  union {
-		  vuint32_t R;
-		  struct{
-			  vuint32_t AD31:1;
-			  vuint32_t AD30:1;
-			  vuint32_t AD29:1;
-			  vuint32_t AD28:1;
-			  vuint32_t AD27:1;
-			  vuint32_t AD26:1;
-			  vuint32_t AD25:1;
-			  vuint32_t AD24:1;
-			  vuint32_t AD23:1;
-			  vuint32_t AD22:1;
-			  vuint32_t AD21:1;
-			  vuint32_t AD20:1;
-			  vuint32_t AD19:1;
-			  vuint32_t AD18:1;
-			  vuint32_t AD17:1;
-			  vuint32_t AD16:1;
-			  vuint32_t AD15:1;
-			  vuint32_t AD14:1;
-			  vuint32_t AD13:1;
-			  vuint32_t AD12:1;
-			  vuint32_t AD11:1;
-			  vuint32_t AD10:1;
-			  vuint32_t AD9:1;
-			  vuint32_t AD8:1;
-			  vuint32_t AD7:1;
-			  vuint32_t AD6:1;
-			  vuint32_t AD5:1;
-			  vuint32_t AD4:1;
-			  vuint32_t AD3:1;
-			  vuint32_t AD2:1;
-			  vuint32_t AD1:1;
-			  vuint32_t AD0:1;
-		  }B;  
-  	  } STARTUP;					/* DTS Startup Register @baseaddress + 0x4 */
-	  
-	  union {
-		  vuint32_t R;
-		  struct {
-			  vuint32_t ST31:1;
-			  vuint32_t ST30:1;
-			  vuint32_t ST29:1;
-			  vuint32_t ST28:1;
-			  vuint32_t ST27:1;
-			  vuint32_t ST26:1;
-			  vuint32_t ST25:1;
-			  vuint32_t ST24:1;
-			  vuint32_t ST23:1;
-			  vuint32_t ST22:1;
-			  vuint32_t ST21:1;
-			  vuint32_t ST20:1;
-			  vuint32_t ST19:1;
-			  vuint32_t ST18:1;
-			  vuint32_t ST17:1;
-			  vuint32_t ST16:1;
-			  vuint32_t ST15:1;
-			  vuint32_t ST14:1;
-			  vuint32_t ST13:1;
-			  vuint32_t ST12:1;
-			  vuint32_t ST11:1;
-			  vuint32_t ST10:1;
-			  vuint32_t ST9:1;
-			  vuint32_t ST8:1;
-			  vuint32_t ST7:1;
-			  vuint32_t ST6:1;
-			  vuint32_t ST5:1;
-			  vuint32_t ST4:1;
-			  vuint32_t ST3:1;
-			  vuint32_t ST2:1;
-			  vuint32_t ST1:1;
-			  vuint32_t ST0:1;
-		  }B;  
-      } SEMAPHORE;				/* DTS Semaphore Register @baseaddress + 0x8 */
-	  
-	  uint32_t DTS_reserved000C[16381]; /* 0x000C-0xFFFF */	    
-   
-    };
-    
-/****************************************************************************/
-/*					   MODULE : REACM (Reaction Module)          			*/
-/****************************************************************************/
-    struct REACM_tag {
-	    
-	  union {
-		  vuint32_t R;
-		  struct {
-		  	  vuint32_t OVRC:1;
-		  	  vuint32_t MDIS:1;
-		  	  vuint32_t FRZ:1;
-			   vuint32_t:1;
-			  vuint32_t FREN:1;
-			  vuint32_t TPREN:1;
-			  vuint32_t HPREN:1;
-			  vuint32_t GIEN:1;
-			  vuint32_t OVREN:1; 
-	      	   vuint32_t:23;
-		  } B;  
-      } MCR; 					/* REACM Module Configuration @baseaddress + 0x0 */
-    
-      union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:4;
-	      	  vuint32_t HPRE:12;
-	      	   vuint32_t:8;
-	      	  vuint32_t TPRE:8;
-		  } B;  
-      } TCR; 					/* REACM Timer Configuration @baseaddress + 0x4 */
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:6;
-	      	  vuint32_t WREN1:1;
-	      	  vuint32_t WREN0:1;
-	      	   vuint32_t:12;
-	      	  vuint32_t THRADC1:4; 
-	      	   vuint32_t:4;
-	      	  vuint32_t THRADC0:4; 
-		  } B;  
-      } THRR; 					/* REACM Threshold Router @baseaddress + 0x8 */
-      
-      uint32_t REACM_reserved000C[1]; /* 0x000C-0x000F */
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:12;
-		  	  vuint32_t ADC_TAG:4; 
-	      	  vuint32_t ADC_RESULT:16;
-		  } B;  
-      } SINR; 					/* REACM ADC Sensor Input Register @baseaddress + 0x10 */
-      
-      uint32_t REACM_reserved0014[3]; /* 0x0014-0x0001F */
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	  vuint32_t OVR:1;
-			   vuint32_t:26;
-	      	  vuint32_t EF4:1;
-	      	  vuint32_t EF3:1;
-	      	  vuint32_t EF2:1;
-	      	  vuint32_t EF1:1;
-	      	  vuint32_t EF0:1;
-		  } B;  
-      } GEFR; 					/* REACM Global Error Flag @baseaddress + 0x20 */
-      
-	  uint32_t REACM_reserved0024[55]; /* 0x0024-0x00FF */      
-	  
-	  struct {
-	  	  union {
-			  vuint32_t R;
-			  struct {
-			  	  vuint32_t CHEN:2;
-			  	  vuint32_t SWMC:1;
-			  	  vuint32_t MAXLEN:1;
-			  	  vuint32_t OCDFEN:1;
-			  	  vuint32_t SCDFEN:1;
-			  	  vuint32_t TAEREN:1;
-			  	  vuint32_t SQEREN:1;
-			  	  vuint32_t RAEREN:1;
-				   vuint32_t:1;
-		      	  vuint32_t CHOFF:1;
-		      	   vuint32_t:2;
-		      	  vuint32_t DOFF:3;
-		      	   vuint32_t:5;
-		      	  vuint32_t BSB:3;
-		      	   vuint32_t:2;
-		      	  vuint32_t MODULATION_ADDR:6;
-			  } B;  
-	      } CR; 					/* REACM Channel n Configuration @baseaddress + 0x100 + (n*0x10) + 0x0 */
-	      
-		  union {
-			  vuint32_t R;
-			  struct {
-			  	   vuint32_t:2;
-		      	  vuint32_t MODACT:1;
-		      	  vuint32_t MAXL:1;
-		      	  vuint32_t OCDF:1;
-		      	  vuint32_t SCDF:1;
-		      	  vuint32_t TAER:1;
-		      	  vuint32_t SQER:1;
-		      	  vuint32_t RAER:1;
-		      	  vuint32_t CHOUT:3;
-		      	   vuint32_t:7;
-		      	  vuint32_t MAXLC:1;
-		      	  vuint32_t OCDFC:1;
-		      	  vuint32_t SCDFC:1;
-		      	  vuint32_t TAERC:1;
-		      	  vuint32_t SQERC:1;
-		      	  vuint32_t RAERC:1; 
-		      	   vuint32_t:1;
-		      	  vuint32_t MODULATION_POINTER:6; 
-			  } B;  
-	      } SR; 					/* REACM Channel n Status @baseaddress + 0x100 + (n*0x10) + 0x4 */
-		  
-	      union {
-			  vuint32_t R;
-			  struct {
-		      	   vuint32_t:12;
-		      	  vuint32_t ADCR:4;
-		      	   vuint32_t:12;
-		      	  vuint32_t CHIR:4;
-			  } B;  
-	      } RR; 					/* REACM Channel n Router @baseaddress + 0x100 + (n*0x10) + 0x8 */
-	      
-	      uint32_t REACM_reserved01xC; /* 0x01xC-0x01xF */      
-	      
-      } CH[6];
-
-      uint32_t REACM_reserved0160[104]; /* 0x0160-0x02FF */      
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:16;
-	      	  vuint32_t SHARED_TIMER:16;
-		  } B;  
-      } STBK[16]; 					/* REACM Shared Timer Bank @baseaddress + 0x300 */
-      
-      uint32_t REACM_reserved0340[16]; /* 0x0340-0x037F */      
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:20;
-	      	  vuint32_t HOLD_OFF:12;
-		  } B;  
-      } HOTBK[16]; 					/* REACM Hold-off Timer Bank @baseaddress + 0x380 */
-      
-      uint32_t REACM_reserved03C0[16]; /* 0x03C0-0x03FF */      
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:16;
-	      	  vuint32_t THRESHOLD_VALUE:16;
-		  } B;  
-      } THBK[32]; 					/* REACM Threshold Timer Bank @baseaddress + 0x400 */
-      
-      uint32_t REACM_reserved0480[96]; /* 0x0480-0x05FF */      
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:16;
-	      	  vuint32_t ADC_MAX_LIMIT:16;
-		  } B;  
-      } ADCMAX; 					/* REACM ADC Result Max Limit Check @baseaddress + 0x600 */
-      
-      uint32_t REACM_reserved0604[31]; /* 0x0604-0x067F */      
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:20;
-	      	  vuint32_t RANGE_PWD:12;
-		  } B;  
-      } RANGEPWD; 					/* REACM Modulation Range Pulse Width @baseaddress + 0x680 */
-      
-      uint32_t REACM_reserved0684[15]; /* 0x0684-0x06BF */      
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	   vuint32_t:20;
-	      	  vuint32_t MIN_PWD:12;
-		  } B;  
-      } MINPWD; 					/* REACM Modulation Minimum Pulse Width @baseaddress + 0x6C0 */
-      
-      uint32_t REACM_reserved06C4[15]; /* 0x06C4-0x06FF */      
-      
-      union {
-		  vuint32_t R;
-		  struct {
-		  	  vuint32_t LOOP:1;
-		  	  vuint32_t IOSS:1;
-			   vuint32_t:1;
-	      	  vuint32_t MM:2;
-	      	   vuint32_t:1;
-	      	  vuint32_t SM:2;
-	      	   vuint32_t:1;
-	      	  vuint32_t HOD:3;
-	      	   vuint32_t:1;
-	      	  vuint32_t LOD:3;
-	      	   vuint32_t:1;
-	      	  vuint32_t THRESPT:6;
-	      	  vuint32_t STPT:4;
-	      	   vuint32_t:1;
-	      	  vuint32_t HDOFFTPT:4;
-		  } B;  
-      } MWBK[64]; 					/* REACM Modulation Control Word Bank @baseaddress + 0x700 */
-     
-	};
-
-
-
-    
-/* Define memories */
-
-#define SRAM_START    0x40000000
-#define SRAM_SIZE        0x30000
-#define SRAM_END      0x4002FFFF
-
-#define FLASH_START   0x00000000
-#define FLASH_SIZE      0x400000
-#define FLASH_END     0x003FFFFF
-
-/* Define instances of modules */
-#define FMPLL     (*( volatile struct FMPLL_tag *)      0xC3F80000)
-#define EBI       (*( volatile struct EBI_tag *)        0xC3F84000)
-#define FLASH_A   (*( volatile struct FLASH_tag *)      0xC3F88000)
-#define FLASH_B   (*( volatile struct FLASH_tag *)      0xC3F8C000)
-#define SIU       (*( volatile struct SIU_tag *)        0xC3F90000)
-#define DTS       (*( volatile struct DTS_tag *)        0xC3F9C000)
-
-#define EMIOS     (*( volatile struct EMIOS_tag *)      0xC3FA0000)
-#define PMC       (*( volatile struct PMC_tag *)        0xC3FBC000)
-
-#define ETPU      (*( volatile struct ETPU_tag *)       0xC3FC0000)
-#define ETPU_DATA_RAM      (*( uint32_t *)              0xC3FC8000)
-#define ETPU_DATA_RAM_END                               0xC3FC8BFC
-#define ETPU_DATA_RAM_EXT  (*( uint32_t *)              0xC3FCC000)
-#define CODE_RAM           (*( uint32_t *)              0xC3FD0000)
-#define ETPU_CODE_RAM      (*( uint32_t *)              0xC3FD0000)
-
-#define REACM	  (*( volatile struct REACM_tag *)      0xC3FC7000)
-
-#define PIT       (*( volatile struct PIT_tag *)        0xC3FF0000)
-
-#define CRC       (*( volatile struct CRC_tag *)        0xFFE68000)
-
-#define PBRIDGE   (*( volatile struct PBRIDGE_tag *)    0xFFF00000)
-#define XBAR      (*( volatile struct XBAR_tag *)       0xFFF04000)
-#define MPU       (*( volatile struct MPU_tag *)        0xFFF10000)
-#define SWT       (*( volatile struct SWT_tag *)        0xFFF38000)
-#define STM       (*( volatile struct STM_tag *)        0xFFF3C000)
-#define ECSM      (*( volatile struct ECSM_tag *)       0xFFF40000)
-#define EDMA      (*( volatile struct EDMA_tag *)       0xFFF44000)
-#define INTC      (*( volatile struct INTC_tag *)       0xFFF48000)
-
-#define EQADC     (*( volatile struct EQADC_tag *)      0xFFF80000)
-
-#define DECFIL_A   (*( volatile struct DECFIL_tag *)      0xFFF88000)
-#define DECFIL_B   (*( volatile struct DECFIL_tag *)      0xFFF8C000)
-
-#define DSPI_B    (*( volatile struct DSPI_tag *)       0xFFF94000)
-#define DSPI_C    (*( volatile struct DSPI_tag *)       0xFFF98000)
-#define DSPI_D    (*( volatile struct DSPI_tag *)       0xFFF9C000)
-
-#define ESCI_A    (*( volatile struct ESCI_tag *)       0xFFFB0000)
-#define ESCI_B    (*( volatile struct ESCI_tag *)       0xFFFB4000)
-#define ESCI_C    (*( volatile struct ESCI_tag *)       0xFFFB8000)
-
-#define CAN_A     (*( volatile struct FLEXCAN2_tag *)   0xFFFC0000)
-#define CAN_B     (*( volatile struct FLEXCAN2_tag *)   0xFFFC4000)
-#define CAN_C     (*( volatile struct FLEXCAN2_tag *)   0xFFFC8000)
-
-#define FR        (*( volatile struct FR_tag *)         0xFFFE0000)
-#define TSENS     (*( volatile struct TSENS_tag *)      0xFFFEC000)
-
-
-#ifdef __MWERKS__
-#pragma pop
-#endif
-
-#ifdef  __cplusplus
-}
-#endif
-#endif                          /* ifdef _MPC5644_H */
-
-/*********************************************************************
- *
- * Copyright:
- *  Freescale Semiconductor, INC. & STMicroelectronics All Rights Reserved.
- *  You are hereby granted a copyright license to use, modify, and
- *  distribute the SOFTWARE so long as this entire notice is
- *  retained without alteration in any modified and/or redistributed
- *  versions, and that such modified versions are clearly identified
- *  as such. No licenses are granted by implication, estoppel or
- *  otherwise under any patents or trademarks of Freescale
- *  Semiconductor, Inc. This software is provided on an "AS IS"
- *  basis and without warranty.
- *
- *  To the maximum extent permitted by applicable law, Freescale
- *  Semiconductor & STMicroelectronics DISCLAIMS ALL WARRANTIES WHETHER 
- *  EXPRESS OR IMPLIED,INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR 
- *  FITNESS FOR A PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
- *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
- *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
- *
- *  To the maximum extent permitted by applicable law, IN NO EVENT
- *  SHALL Freescale Semiconductor or STMicroelectronics BE LIABLE FOR ANY 
- *  DAMAGES WHATSOEVER (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
- *  BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, 
- *  OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
- *
- *  Freescale Semiconductor & STMicroelectronics assumes no responsibility 
- *  for the maintenance and support of this software
- *
- ********************************************************************/
diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c
deleted file mode 100644
index 4a3976f50..000000000
--- a/os/hal/platforms/SPC56ELxx/hal_lld.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC56ELxx/hal_lld.c
- * @brief   SPC56ELxx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-  uint32_t n;
-
-  /* The system is switched to the RUN0 mode, the default for normal
-     operations.*/
-  if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* Decrementer timer initialized for system tick use, note, it is
-     initialized here because in the OSAL layer the system clock frequency
-     is not yet known.*/
-  n = halSPCGetSystemClock() / CH_FREQUENCY;
-  asm volatile ("mtspr   22, %[n]           \t\n"   /* Init. DEC register.  */
-                "mtspr   54, %[n]           \t\n"   /* Init. DECAR register.*/
-                "lis     %%r3, 0x0440       \t\n"   /* DIE ARE bits.        */
-                "mtspr   340, %%r3"                 /* TCR register.        */
-                : : [n] "r" (n) : "r3");
-
-  /* TB counter enabled for debug and measurements.*/
-  asm volatile ("li      %%r3, 0x4000       \t\n"   /* TBEN bit.            */
-                "mtspr   1008, %%r3"                /* HID0 register.       */
-                : : : "r3");
-
-  /* INTC initialization, software vector mode, 4 bytes vectors, starting
-     at priority 0.*/
-  INTC.MCR.R        = 0;
-  INTC.CPR.R        = 0;
-  INTC.IACKR.R      = (uint32_t)_vectors;
-
-  /* EDMA initialization.*/
-  edmaInit();
-}
-
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This service is implemented by returning the content of the
- *          DWT_CYCCNT register.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @notapi
- */
-halrtcnt_t hal_lld_get_counter_value(void) {
-  halrtcnt_t cnt;
-
-  asm volatile ("mfspr %0, 284" : "=r" (cnt));
-  return cnt;
-}
-
-/**
- * @brief   SPC56ELxx early initialization.
- * @note    All the involved constants come from the file @p board.h and
- *          @p hal_lld.h
- * @note    This function must be invoked only after the system reset.
- *
- * @special
- */
-void spc_early_init(void) {
-
-  /* Waiting for IRC stabilization before attempting anything else.*/
-  while (!ME.GS.B.S_IRCOSC)
-    ;
-
-#if !SPC5_NO_INIT
-
-#if SPC5_DISABLE_WATCHDOG
-  /* SWT disabled.*/
-  SWT.SR.R = 0xC520;
-  SWT.SR.R = 0xD928;
-  SWT.CR.R = 0xFF00000A;
-#endif
-
-  /* Enabling peripheral bridges to allow any operation.*/
-  AIPS.MPROT.R      = 0x77777777;
-  AIPS.PACR0_7.R    = 0;
-  AIPS.PACR8_15.R   = 0;
-  AIPS.PACR16_23.R  = 0;
-  AIPS.PACR24_31.R  = 0;
-  AIPS.OPACR0_7.R   = 0;
-  AIPS.OPACR8_15.R  = 0;
-  AIPS.OPACR16_23.R = 0;
-  AIPS.OPACR24_31.R = 0;
-  AIPS.OPACR32_39.R = 0;
-  AIPS.OPACR40_47.R = 0;
-  AIPS.OPACR48_55.R = 0;
-  AIPS.OPACR56_63.R = 0;
-  AIPS.OPACR64_71.R = 0;
-  AIPS.OPACR72_79.R = 0;
-  AIPS.OPACR80_87.R = 0;
-  AIPS.OPACR88_95.R = 0;
-
-  /* SSCM initialization. Setting up the most restrictive handling of
-     invalid accesses to peripherals.*/
-  SSCM.ERROR.R = 3;                             /* PAE and RAE bits.        */
-
-  /* FCCU CF errors clearing.*/
-  FCCU.CFK.R        = 0x618B7A50;
-  FCCU.CFS[0].R     = 0xFFFFFFFF;
-  while (FCCU.CTRL.B.OPS != 3)
-    ;
-  FCCU.CFK.R        = 0x618B7A50;
-  FCCU.CFS[1].R     = 0xFFFFFFFF;
-  while (FCCU.CTRL.B.OPS != 3)
-    ;
-
-  /* FCCU NCF errors clearing.*/
-  FCCU.NCFK.R       = 0xAB3498FE;
-  FCCU.NCFS[0].R    = 0xFFFFFFFF;
-  while (FCCU.CTRL.B.OPS != 3)
-    ;
-
-  /* RGM errors clearing.*/
-  RGM.FES.R         = 0xFFFF;
-  RGM.DES.R         = 0xFFFF;
-
-  /* The system must be in DRUN mode on entry, if this is not the case then
-     it is considered a serious anomaly.*/
-  if (ME.GS.B.S_CURRENT_MODE != SPC5_RUNMODE_DRUN) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-#if defined(SPC5_OSC_BYPASS)
-  /* If the board is equipped with an oscillator instead of a crystal then the
-     bypass must be activated.*/
-  CGM.OSC_CTL.B.OSCBYP = TRUE;
-#endif /* SPC5_OSC_BYPASS */
-
-  /* Setting the various dividers and source selectors.*/
-  CGM.SC_DC0.R    = SPC5_CGM_SC_DC0;
-  CGM.AC0_DC0_3.R = SPC5_CGM_AC0_DC0 | SPC5_CGM_AC0_DC1;
-  CGM.AC0_SC.R    = SPC5_AUX0CLK_SRC;
-  CGM.AC1_DC0_3.R = SPC5_CGM_AC1_DC0;
-  CGM.AC1_SC.R    = SPC5_AUX1CLK_SRC;
-  CGM.AC2_DC0_3.R = SPC5_CGM_AC2_DC0;
-  CGM.AC2_SC.R    = SPC5_AUX2CLK_SRC;
-  CGM.AC3_SC.R    = SPC5_FMPLL0_CLK_SRC;
-  CGM.AC4_SC.R    = SPC5_FMPLL1_CLK_SRC;
-
-  /* Enables the XOSC in order to check its functionality before proceeding
-     with the initialization.*/
-  ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | SPC5_ME_MC_XOSC0ON |           \
-              SPC5_ME_MC_FLAON_NORMAL | SPC5_ME_MC_MVRON;
-  if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* Initialization of the FMPLLs settings.
-     TODO: Add settings for the MR registers.*/
-  CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF |
-                      ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
-                      (SPC5_FMPLL0_NDIV_VALUE << 16);
-  CGM.FMPLL[0].MR.R = 0;
-  CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
-                      ((SPC5_FMPLL1_IDF_VALUE - 1) << 26) |
-                      (SPC5_FMPLL1_NDIV_VALUE << 16);
-  CGM.FMPLL[1].MR.R = 0;
-
-  /* Run modes initialization, note writes to the MC registers are verified
-     by a protection mechanism, the operation success is verified at the
-     end of the sequence.*/
-  ME.IS.R           = 8;                        /* Resetting I_ICONF status.*/
-  ME.MER.R          = SPC5_ME_ME_BITS;          /* Enabled run modes.       */
-  ME.SAFE.R         = SPC5_ME_SAFE_MC_BITS;     /* SAFE run mode.           */
-  ME.DRUN.R         = SPC5_ME_DRUN_MC_BITS;     /* DRUN run mode.           */
-  ME.RUN[0].R       = SPC5_ME_RUN0_MC_BITS;     /* RUN0 run mode.           */
-  ME.RUN[1].R       = SPC5_ME_RUN1_MC_BITS;     /* RUN1 run mode.           */
-  ME.RUN[2].R       = SPC5_ME_RUN2_MC_BITS;     /* RUN2 run mode.           */
-  ME.RUN[3].R       = SPC5_ME_RUN3_MC_BITS;     /* RUN0 run mode.           */
-  ME.HALT0.R        = SPC5_ME_HALT0_MC_BITS;    /* HALT0 run mode.          */
-  ME.STOP0.R        = SPC5_ME_STOP0_MC_BITS;    /* STOP0 run mode.          */
-  if (ME.IS.B.I_ICONF) {
-    /* Configuration rejected.*/
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-  /* Peripherals run and low power modes initialization.*/
-  ME.RUNPC[0].R     = SPC5_ME_RUN_PC0_BITS;
-  ME.RUNPC[1].R     = SPC5_ME_RUN_PC1_BITS;
-  ME.RUNPC[2].R     = SPC5_ME_RUN_PC2_BITS;
-  ME.RUNPC[3].R     = SPC5_ME_RUN_PC3_BITS;
-  ME.RUNPC[4].R     = SPC5_ME_RUN_PC4_BITS;
-  ME.RUNPC[5].R     = SPC5_ME_RUN_PC5_BITS;
-  ME.RUNPC[6].R     = SPC5_ME_RUN_PC6_BITS;
-  ME.RUNPC[7].R     = SPC5_ME_RUN_PC7_BITS;
-  ME.LPPC[0].R      = SPC5_ME_LP_PC0_BITS;
-  ME.LPPC[1].R      = SPC5_ME_LP_PC1_BITS;
-  ME.LPPC[2].R      = SPC5_ME_LP_PC2_BITS;
-  ME.LPPC[3].R      = SPC5_ME_LP_PC3_BITS;
-  ME.LPPC[4].R      = SPC5_ME_LP_PC4_BITS;
-  ME.LPPC[5].R      = SPC5_ME_LP_PC5_BITS;
-  ME.LPPC[6].R      = SPC5_ME_LP_PC6_BITS;
-  ME.LPPC[7].R      = SPC5_ME_LP_PC7_BITS;
-
-  /* CFLASH settings initialized for a maximum clock of 120MHz.*/
-  CFLASH.PFCR0.B.B02_APC  = 3;
-  CFLASH.PFCR0.B.B02_WWSC = 3;
-  CFLASH.PFCR0.B.B02_RWSC = 3;
-
-  /* Switches again to DRUN mode (current mode) in order to update the
-     settings.*/
-  if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
-    SPC5_CLOCK_FAILURE_HOOK();
-  }
-
-#endif /* !SPC5_NO_INIT */
-}
-
-/**
- * @brief   Switches the system to the specified run mode.
- *
- * @param[in] mode      one of the possible run modes
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   if the switch operation has been completed.
- * @retval CH_FAILED    if the switch operation failed.
- */
-bool_t halSPCSetRunMode(spc5_runmode_t mode) {
-
-  /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
-  ME.IS.R = 5;
-
-  /* Starts a transition process.*/
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
-
-  /* Waits for the mode switch or an error condition.*/
-  while (TRUE) {
-    uint32_t r = ME.IS.R;
-    if (r & 1)
-      return CH_SUCCESS;
-    if (r & 4)
-      return CH_FAILED;
-  }
-}
-
-/**
- * @brief   Changes the clock mode of a peripheral.
- *
- * @param[in] n         index of the @p PCTL register
- * @param[in] pctl      new value for the @p PCTL register
- *
- * @notapi
- */
-void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
-  uint32_t mode;
-
-  ME.PCTL[n].R = pctl;
-  mode = ME.MCTL.B.TARGET_MODE;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
-  ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
-}
-
-#if !SPC5_NO_INIT || defined(__DOXYGEN__)
-/**
- * @brief   Returns the system clock under the current run mode.
- *
- * @return              The system clock in Hertz.
- */
-uint32_t halSPCGetSystemClock(void) {
-  uint32_t sysclk;
-
-  sysclk = ME.GS.B.S_SYSCLK;
-  switch (sysclk) {
-  case SPC5_ME_GS_SYSCLK_IRC:
-    return SPC5_IRC_CLK;
-  case SPC5_ME_GS_SYSCLK_XOSC:
-    return SPC5_XOSC_CLK;
-  case SPC5_ME_GS_SYSCLK_FMPLL0:
-    return SPC5_FMPLL0_CLK;
-  default:
-    return 0;
-  }
-}
-#endif /* !SPC5_NO_INIT */
-
-/** @} */
diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.h b/os/hal/platforms/SPC56ELxx/hal_lld.h
deleted file mode 100644
index 0c3266bce..000000000
--- a/os/hal/platforms/SPC56ELxx/hal_lld.h
+++ /dev/null
@@ -1,983 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC56ELxx/hal_lld.h
- * @brief   SPC56ELxx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - SPC5_XOSC_CLK.
- *          - SPC5_OSC_BYPASS (optionally).
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "xpc56el.h"
-#include "spc56el_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS     TRUE
-
-/**
- * @name    Platform identification
- * @{
- */
-#define PLATFORM_NAME               "SPC56ELxx Chassis and Safety"
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum XOSC clock frequency.
- */
-#define SPC5_XOSC_CLK_MAX           40000000
-
-/**
- * @brief   Minimum XOSC clock frequency.
- */
-#define SPC5_XOSC_CLK_MIN           4000000
-
-/**
- * @brief   Maximum FMPLLs input clock frequency.
- */
-#define SPC5_FMPLLIN_MIN            4000000
-
-/**
- * @brief   Maximum FMPLLs input clock frequency.
- */
-#define SPC5_FMPLLIN_MAX            40000000
-
-/**
- * @brief   Maximum FMPLLs VCO clock frequency.
- */
-#define SPC5_FMPLLVCO_MAX           512000000
-
-/**
- * @brief   Maximum FMPLLs VCO clock frequency.
- */
-#define SPC5_FMPLLVCO_MIN           256000000
-
-/**
- * @brief   Maximum FMPLL0 output clock frequency.
- */
-#define SPC5_FMPLL0_CLK_MAX         120000000
-
-/**
- * @brief   Maximum FMPLL1 output clock frequency.
- */
-#define SPC5_FMPLL1_CLK_MAX         120000000
-
-/**
- * @brief   Maximum FMPLL1 1D1 output clock frequency.
- */
-#define SPC5_FMPLL1_1D1_CLK_MAX     80000000
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define SPC5_IRC_CLK                16000000    /**< Internal RC oscillator.*/
-/** @} */
-
-/**
- * @name    FMPLLs register bits definitions
- * @{
- */
-#define SPC5_FMPLL_SRC_IRC          (0U << 24)
-#define SPC5_FMPLL_SRC_XOSC         (1U << 24)
-/** @} */
-
-/**
- * @name    FMPLL_CR register bits definitions
- * @{
- */
-#define SPC5_FMPLL_ODF_DIV2         (0U << 24)
-#define SPC5_FMPLL_ODF_DIV4         (1U << 24)
-#define SPC5_FMPLL_ODF_DIV8         (2U << 24)
-#define SPC5_FMPLL_ODF_DIV16        (3U << 24)
-/** @} */
-
-/**
- * @name    Clock selectors used in the various GCM SC registers
- * @{
- */
-#define SPC5_CGM_SS_MASK            (15U << 24)
-#define SPC5_CGM_SS_IRC             (0U << 24)
-#define SPC5_CGM_SS_XOSC            (2U << 24)
-#define SPC5_CGM_SS_FMPLL0          (4U << 24)
-#define SPC5_CGM_SS_FMPLL1          (5U << 24)
-#define SPC5_CGM_SS_FMPLL1_1D1      (8U << 24)
-/** @} */
-
-/**
- * @name    ME_GS register bits definitions
- * @{
- */
-#define SPC5_ME_GS_SYSCLK_MASK      (15U << 0)
-#define SPC5_ME_GS_SYSCLK_IRC       (0U << 0)
-#define SPC5_ME_GS_SYSCLK_XOSC      (2U << 0)
-#define SPC5_ME_GS_SYSCLK_FMPLL0    (4U << 0)
-/** @} */
-
-/**
- * @name    ME_ME register bits definitions
- * @{
- */
-#define SPC5_ME_ME_RESET            (1U << 0)
-#define SPC5_ME_ME_SAFE             (1U << 2)
-#define SPC5_ME_ME_DRUN             (1U << 3)
-#define SPC5_ME_ME_RUN0             (1U << 4)
-#define SPC5_ME_ME_RUN1             (1U << 5)
-#define SPC5_ME_ME_RUN2             (1U << 6)
-#define SPC5_ME_ME_RUN3             (1U << 7)
-#define SPC5_ME_ME_HALT0            (1U << 8)
-#define SPC5_ME_ME_STOP0            (1U << 10)
-/** @} */
-
-/**
- * @name    ME_xxx_MC registers bits definitions
- * @{
- */
-#define SPC5_ME_MC_SYSCLK_MASK      (15U << 0)
-#define SPC5_ME_MC_SYSCLK(n)        ((n) << 0)
-#define SPC5_ME_MC_SYSCLK_IRC       SPC5_ME_MC_SYSCLK(0)
-#define SPC5_ME_MC_SYSCLK_XOSC      SPC5_ME_MC_SYSCLK(2)
-#define SPC5_ME_MC_SYSCLK_FMPLL0    SPC5_ME_MC_SYSCLK(4)
-#define SPC5_ME_MC_SYSCLK_DISABLED  SPC5_ME_MC_SYSCLK(15)
-#define SPC5_ME_MC_IRCON            (1U << 4)
-#define SPC5_ME_MC_XOSC0ON          (1U << 5)
-#define SPC5_ME_MC_PLL0ON           (1U << 6)
-#define SPC5_ME_MC_PLL1ON           (1U << 7)
-#define SPC5_ME_MC_FLAON_MASK       ((3U << 16) | (3U << 18))
-#define SPC5_ME_MC_FLAON(n)         (((n) << 16) | ((n) << 18))
-#define SPC5_ME_MC_FLAON_PD         ((1U << 16) | (1U << 18))
-#define SPC5_ME_MC_FLAON_LP         ((2U << 16) | (2U << 18))
-#define SPC5_ME_MC_FLAON_NORMAL     ((3U << 16) | (3U << 18))
-#define SPC5_ME_MC_MVRON            (1U << 20)
-#define SPC5_ME_MC_PDO              (1U << 23)
-/** @} */
-
-/**
- * @name    ME_MCTL register bits definitions
- * @{
- */
-#define SPC5_ME_MCTL_KEY            0x5AF0U
-#define SPC5_ME_MCTL_KEY_INV        0xA50FU
-#define SPC5_ME_MCTL_MODE_MASK      (15U << 28)
-#define SPC5_ME_MCTL_MODE(n)        ((n) << 28)
-/** @} */
-
-/**
- * @name    ME_RUN_PCx registers bits definitions
- * @{
- */
-#define SPC5_ME_RUN_PC_SAFE         (1U << 2)
-#define SPC5_ME_RUN_PC_DRUN         (1U << 3)
-#define SPC5_ME_RUN_PC_RUN0         (1U << 4)
-#define SPC5_ME_RUN_PC_RUN1         (1U << 5)
-#define SPC5_ME_RUN_PC_RUN2         (1U << 6)
-#define SPC5_ME_RUN_PC_RUN3         (1U << 7)
-/** @} */
-
-/**
- * @name    ME_LP_PCx registers bits definitions
- * @{
- */
-#define SPC5_ME_LP_PC_HALT0         (1U << 8)
-#define SPC5_ME_LP_PC_STOP0         (1U << 10)
-/** @} */
-
-/**
- * @name    ME_PCTL registers bits definitions
- * @{
- */
-#define SPC5_ME_PCTL_RUN_MASK       (7U << 0)
-#define SPC5_ME_PCTL_RUN(n)         ((n) << 0)
-#define SPC5_ME_PCTL_LP_MASK        (7U << 3)
-#define SPC5_ME_PCTL_LP(n)          ((n) << 3)
-#define SPC5_ME_PCTL_DBG            (1U << 6)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Disables the clocks initialization in the HAL.
- */
-#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
-#define SPC5_NO_INIT                        FALSE
-#endif
-
-/**
- * @brief   Disables the overclock checks.
- */
-#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
-#define SPC5_ALLOW_OVERCLOCK                FALSE
-#endif
-
-/**
- * @brief   Disables the watchdog on start.
- */
-#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
-#define SPC5_DISABLE_WATCHDOG               TRUE
-#endif
-
-/**
- * @brief   FMPLL0 Clock source.
- */
-#if !defined(SPC5_FMPLL0_CLK_SRC) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_CLK_SRC                 SPC5_FMPLL_SRC_XOSC
-#endif
-
-/**
- * @brief   FMPLL0 IDF divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=120MHz.
- */
-#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_IDF_VALUE               5
-#endif
-
-/**
- * @brief   FMPLL0 NDIV divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=120MHz.
- */
-#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_NDIV_VALUE              60
-#endif
-
-/**
- * @brief   FMPLL0 ODF divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=120MHz.
- */
-#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_ODF                     SPC5_FMPLL_ODF_DIV4
-#endif
-
-/**
- * @brief   FMPLL1 Clock source.
- */
-#if !defined(SPC5_FMPLL1_CLK_SRC) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_CLK_SRC                 SPC5_FMPLL_SRC_XOSC
-#endif
-
-/**
- * @brief   FMPLL1 IDF divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=120MHz.
- */
-#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_IDF_VALUE               5
-#endif
-
-/**
- * @brief   FMPLL1 NDIV divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=120MHz.
- */
-#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_NDIV_VALUE              60
-#endif
-
-/**
- * @brief   FMPLL1 ODF divider value.
- * @note    The default value is calculated for XOSC=40MHz and PHI=120MHz.
- */
-#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_ODF                     SPC5_FMPLL_ODF_DIV4
-#endif
-
-/**
- * @brief   System clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_SYSCLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
-#define SPC5_SYSCLK_DIVIDER_VALUE           2
-#endif
-
-/**
- * @brief   AUX0 clock source.
- */
-#if !defined(SPC5_AUX0CLK_SRC) || defined(__DOXYGEN__)
-#define SPC5_AUX0CLK_SRC                    SPC5_CGM_SS_FMPLL1
-#endif
-
-/**
- * @brief   Motor Control clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_MCONTROL_DIVIDER_VALUE) || defined(__DOXYGEN__)
-#define SPC5_MCONTROL_DIVIDER_VALUE         2
-#endif
-
-/**
- * @brief   SWG clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_SWG_DIVIDER_VALUE) || defined(__DOXYGEN__)
-#define SPC5_SWG_DIVIDER_VALUE              2
-#endif
-
-/**
- * @brief   AUX1 clock source.
- * @note    Used by Flexray.
- */
-#if !defined(SPC5_AUX1CLK_SRC) || defined(__DOXYGEN__)
-#define SPC5_AUX1CLK_SRC                    SPC5_CGM_SS_FMPLL1
-#endif
-
-/**
- * @brief   Flexray clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_FLEXRAY_DIVIDER_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FLEXRAY_DIVIDER_VALUE          2
-#endif
-
-/**
- * @brief   AUX2 clock source.
- * @note    Used by FlexCAN.
- */
-#if !defined(SPC5_AUX2CLK_SRC) || defined(__DOXYGEN__)
-#define SPC5_AUX2CLK_SRC                    SPC5_CGM_SS_FMPLL1
-#endif
-
-/**
- * @brief   FlexCAN clock divider value.
- * @note    Zero means disabled clock.
- */
-#if !defined(SPC5_FLEXCAN_DIVIDER_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_DIVIDER_VALUE          2
-#endif
-
-/**
- * @brief   Active run modes in ME_ME register.
- * @note    Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
- *          is no need to specify them.
- */
-#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_ME_BITS                     (SPC5_ME_ME_RUN1 |              \
-                                             SPC5_ME_ME_RUN2 |              \
-                                             SPC5_ME_ME_RUN3 |              \
-                                             SPC5_ME_ME_HALT0 |             \
-                                             SPC5_ME_ME_STOP0)
-#endif
-
-/**
- * @brief   SAFE mode settings.
- */
-#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_SAFE_MC_BITS                (SPC5_ME_MC_PDO)
-#endif
-
-/**
- * @brief   DRUN mode settings.
- */
-#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_DRUN_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_PLL1ON |            \
-                                             SPC5_ME_MC_FLAON_NORMAL |      \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN0 mode settings.
- */
-#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN0_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_PLL1ON |            \
-                                             SPC5_ME_MC_FLAON_NORMAL |      \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN1 mode settings.
- */
-#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN1_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_PLL1ON |            \
-                                             SPC5_ME_MC_FLAON_NORMAL |      \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN2 mode settings.
- */
-#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN2_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_PLL1ON |            \
-                                             SPC5_ME_MC_FLAON_NORMAL |      \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   RUN3 mode settings.
- */
-#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN3_MC_BITS                (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_PLL1ON |            \
-                                             SPC5_ME_MC_FLAON_NORMAL |      \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   HALT0 mode settings.
- */
-#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_HALT0_MC_BITS               (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_PLL1ON |            \
-                                             SPC5_ME_MC_FLAON_NORMAL |      \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   STOP0 mode settings.
- */
-#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_STOP0_MC_BITS               (SPC5_ME_MC_SYSCLK_FMPLL0 |     \
-                                             SPC5_ME_MC_IRCON |             \
-                                             SPC5_ME_MC_XOSC0ON |           \
-                                             SPC5_ME_MC_PLL0ON |            \
-                                             SPC5_ME_MC_PLL1ON |            \
-                                             SPC5_ME_MC_FLAON_NORMAL |      \
-                                             SPC5_ME_MC_MVRON)
-#endif
-
-/**
- * @brief   Peripheral mode 0 (run mode).
- * @note    Do not change this setting, it is expected to be the "never run"
- *          mode.
- */
-#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC0_BITS                0
-#endif
-
-/**
- * @brief   Peripheral mode 1 (run mode).
- * @note    Do not change this setting, it is expected to be the "always run"
- *          mode.
- */
-#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC1_BITS                (SPC5_ME_RUN_PC_SAFE |          \
-                                             SPC5_ME_RUN_PC_DRUN |          \
-                                             SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 2 (run mode).
- * @note    Do not change this setting, it is expected to be the "only during
- *          normal run" mode.
- */
-#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC2_BITS                (SPC5_ME_RUN_PC_DRUN |          \
-                                             SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 3 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC3_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 4 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC4_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 5 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC5_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 6 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC6_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 7 (run mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC7_BITS                (SPC5_ME_RUN_PC_RUN0 |          \
-                                             SPC5_ME_RUN_PC_RUN1 |          \
-                                             SPC5_ME_RUN_PC_RUN2 |          \
-                                             SPC5_ME_RUN_PC_RUN3)
-#endif
-
-/**
- * @brief   Peripheral mode 0 (low power mode).
- * @note    Do not change this setting, it is expected to be the "never run"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC0_BITS                 0
-#endif
-
-/**
- * @brief   Peripheral mode 1 (low power mode).
- * @note    Do not change this setting, it is expected to be the "always run"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC1_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 2 (low power mode).
- * @note    Do not change this setting, it is expected to be the "halt only"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC2_BITS                 (SPC5_ME_LP_PC_HALT0)
-#endif
-
-/**
- * @brief   Peripheral mode 3 (low power mode).
- * @note    Do not change this setting, it is expected to be the "stop only"
- *          mode.
- */
-#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC3_BITS                 (SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 4 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC4_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 5 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC5_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 6 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC6_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Peripheral mode 7 (low power mode).
- * @note    Not defined, available to application-specific modes.
- */
-#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC7_BITS                 (SPC5_ME_LP_PC_HALT0 |          \
-                                             SPC5_ME_LP_PC_STOP0)
-#endif
-
-/**
- * @brief   Clock initialization failure hook.
- * @note    The default is to stop the system and let the RTC restart it.
- * @note    The hook code must not return.
- */
-#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
-#define SPC5_CLOCK_FAILURE_HOOK()           chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(SPC56ELxx_MCUCONF)
-#error "Using a wrong mcuconf.h file, SPC56ELxx_MCUCONF not defined"
-#endif
-
-/* Check on the XOSC frequency.*/
-#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) ||                                  \
-    (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
-#error "invalid SPC5_XOSC_CLK value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_CLOCK_SOURCE.*/
-#if SPC5_FMPLL0_CLK_SRC == SPC5_FMPLL_SRC_IRC
-#define SPC5_FMPLL0_INPUT_CLK   SPC5_IRC_CLK
-#elif SPC5_FMPLL0_CLK_SRC == SPC5_FMPLL_SRC_XOSC
-#define SPC5_FMPLL0_INPUT_CLK   SPC5_XOSC_CLK
-#else
-#error "invalid SPC5_FMPLL0_CLK_SRC value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_IDF_VALUE.*/
-#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
-#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
-#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
-#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL0_ODF.*/
-#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
-#define SPC5_FMPLL0_ODF_VALUE    2
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
-#define SPC5_FMPLL0_ODF_VALUE    4
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
-#define SPC5_FMPLL0_ODF_VALUE    8
-#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
-#define SPC5_FMPLL0_ODF_VALUE    16
-#else
-#error "invalid SPC5_FMPLL0_ODF value specified"
-#endif
-
-/**
- * @brief   SPC5_FMPLL0_VCO_CLK clock point.
- */
-#define SPC5_FMPLL0_VCO_CLK                                                 \
-  ((SPC5_FMPLL0_INPUT_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
-
-/* Check on FMPLL0 VCO output.*/
-#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \
-    (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
-#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
-#endif
-
-/**
- * @brief   SPC5_FMPLL0_CLK clock point.
- */
-#define SPC5_FMPLL0_CLK                                                     \
-  (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
-
-/* Check on SPC5_FMPLL0_CLK.*/
-#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
-#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
-#endif
-
-/* Check on SPC5_FMPLL1_CLOCK_SOURCE.*/
-#if SPC5_FMPLL1_CLK_SRC == SPC5_FMPLL_SRC_IRC
-#define SPC5_FMPLL1_INPUT_CLK   SPC5_IRC_CLK
-#elif SPC5_FMPLL1_CLK_SRC == SPC5_FMPLL_SRC_XOSC
-#define SPC5_FMPLL1_INPUT_CLK   SPC5_XOSC_CLK
-#else
-#error "invalid SPC5_FMPLL1_CLK_SRC value specified"
-#endif
-
-/* Check on SPC5_FMPLL1_IDF_VALUE.*/
-#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
-#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL1_NDIV_VALUE.*/
-#if (SPC5_FMPLL1_NDIV_VALUE < 32) || (SPC5_FMPLL1_NDIV_VALUE > 96)
-#error "invalid SPC5_FMPLL1_NDIV_VALUE value specified"
-#endif
-
-/* Check on SPC5_FMPLL1_ODF.*/
-#if (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV2)
-#define SPC5_FMPLL1_ODF_VALUE   2
-#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV4)
-#define SPC5_FMPLL1_ODF_VALUE   4
-#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV8)
-#define SPC5_FMPLL1_ODF_VALUE   8
-#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV16)
-#define SPC5_FMPLL1_ODF_VALUE   16
-#else
-#error "invalid SPC5_FMPLL1_ODF value specified"
-#endif
-
-/**
- * @brief   SPC5_FMPLL1_VCO_CLK clock point.
- */
-#define SPC5_FMPLL1_VCO_CLK                                                 \
-  ((SPC5_FMPLL1_INPUT_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
-
-/* Check on FMPLL1 VCO output.*/
-#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \
-    (SPC5_FMPLL1_VCO_CLK > SPC5_FMPLLVCO_MAX)
-#error "SPC5_FMPLL1_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
-#endif
-
-/**
- * @brief   SPC5_FMPLL1_CLK clock point.
- */
-#define SPC5_FMPLL1_CLK                                                     \
-  (SPC5_FMPLL1_VCO_CLK / SPC5_FMPLL1_ODF_VALUE)
-
-/**
- * @brief   SPC5_FMPLL1_1D1_CLK clock point.
- */
-#define SPC5_FMPLL1_1D1_CLK                                                 \
-  (SPC5_FMPLL1_VCO_CLK / 6)
-
-/* Check on SPC5_FMPLL1_CLK.*/
-#if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
-#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
-#endif
-
-/* Check on the system divider settings.*/
-#if SPC5_SYSCLK_DIVIDER_VALUE == 0
-#define SPC5_CGM_SC_DC0         0
-#elif (SPC5_SYSCLK_DIVIDER_VALUE >= 1) && (SPC5_SYSCLK_DIVIDER_VALUE <= 16)
-#define SPC5_CGM_SC_DC0         (0x80 | (SPC5_SYSCLK_DIVIDER_VALUE - 1))
-#else
-#error "invalid SPC5_SYSCLK_DIVIDER_VALUE value specified"
-#endif
-
-/**
- * @brief   AUX0 clock point.
- */
-#if (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
-#define SPC5_AUX0_CLK           SPC5_FMPLL_SRC_IRC
-#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_XOSC
-#define SPC5_AUX0_CLK           SPC5_FMPLL_SRC_XOSC
-#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL0
-#define SPC5_AUX0_CLK           SPC5_FMPLL0_CLK
-#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1
-#define SPC5_AUX0_CLK           SPC5_FMPLL1_CLK
-#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
-#define SPC5_AUX0_CLK           SPC5_FMPLL1_1D1_CLK
-#else
-#error "invalid SPC5_AUX0CLK_SRC value specified"
-#endif
-
-/* Check on the AUX0 divider 0 settings.*/
-#if SPC5_MCONTROL_DIVIDER_VALUE == 0
-#define SPC5_CGM_AC0_DC0        0
-#elif (SPC5_MCONTROL_DIVIDER_VALUE >= 1) && (SPC5_MCONTROL_DIVIDER_VALUE <= 16)
-#define SPC5_CGM_AC0_DC0        ((0x80U | (SPC5_MCONTROL_DIVIDER_VALUE - 1)) << 24)
-#else
-#error "invalid SPC5_MCONTROL_DIVIDER_VALUE value specified"
-#endif
-
-/* Check on the AUX0 divider 1 settings.*/
-#if SPC5_SWG_DIVIDER_VALUE == 0
-#define SPC5_CGM_AC0_DC1        0
-#elif (SPC5_SWG_DIVIDER_VALUE >= 1) && (SPC5_SWG_DIVIDER_VALUE <= 16)
-#define SPC5_CGM_AC0_DC1        ((0x80U | (SPC5_SWG_DIVIDER_VALUE - 1)) << 16)
-#else
-#error "invalid SPC5_SWG_DIVIDER_VALUE value specified"
-#endif
-
-/**
- * @brief   Motor Control clock point.
- */
-#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
-#define SPC5_MCONTROL_CLK       (SPC5_AUX0_CLK / SPC5_MCONTROL_DIVIDER_VALUE)
-#else
-#define SPC5_MCONTROL_CLK       0
-#endif
-
-/**
- * @brief   SWG clock point.
- */
-#if (SPC5_SWG_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
-#define SPC5_SWG_CLK            (SPC5_AUX0_CLK / SPC5_SWG_DIVIDER_VALUE)
-#else
-#define SPC5_SWG_CLK            0
-#endif
-
-/**
- * @brief   AUX1 clock point.
- */
-#if (SPC5_AUX1CLK_SRC == SPC5_CGM_SS_FMPLL0) || defined(__DOXYGEN__)
-#define SPC5_AUX1_CLK           SPC5_FMPLL0_CLK
-#elif SPC5_AUX1CLK_SRC == SPC5_CGM_SS_FMPLL1
-#define SPC5_AUX1_CLK           SPC5_FMPLL1_CLK
-#elif SPC5_AUX1CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
-#define SPC5_AUX1_CLK           SPC5_FMPLL1_1D1_CLK
-#else
-#error "invalid SPC5_AUX1CLK_SRC value specified"
-#endif
-
-/* Check on the AUX1 divider 0 settings.*/
-#if SPC5_FLEXRAY_DIVIDER_VALUE == 0
-#define SPC5_CGM_AC1_DC0        0
-#elif (SPC5_FLEXRAY_DIVIDER_VALUE >= 1) && (SPC5_FLEXRAY_DIVIDER_VALUE <= 16)
-#define SPC5_CGM_AC1_DC0        ((0x80U | (SPC5_FLEXRAY_DIVIDER_VALUE - 1)) << 24)
-#else
-#error "invalid SPC5_FLEXRAY_DIVIDER_VALUE value specified"
-#endif
-
-/**
- * @brief   Flexray clock point.
- */
-#if (SPC5_FLEXRAY_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
-#define SPC5_FLEXRAY_CLK        (SPC5_AUX2_CLK / SPC5_FLEXRAY_DIVIDER_VALUE)
-#else
-#define SPC5_FLEXRAY_CLK        0
-#endif
-
-/**
- * @brief   AUX2 clock point.
- */
-#if (SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL0) || defined(__DOXYGEN__)
-#define SPC5_AUX2_CLK           SPC5_FMPLL0_CLK
-#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1
-#define SPC5_AUX2_CLK           SPC5_FMPLL1_CLK
-#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
-#define SPC5_AUX2_CLK           SPC5_FMPLL1_1D1_CLK
-#else
-#error "invalid SPC5_AUX2CLK_SRC value specified"
-#endif
-
-/* Check on the AUX2 divider 0 settings.*/
-#if SPC5_FLEXCAN_DIVIDER_VALUE == 0
-#define SPC5_CGM_AC2_DC0        0
-#elif (SPC5_FLEXCAN_DIVIDER_VALUE >= 1) && (SPC5_FLEXCAN_DIVIDER_VALUE <= 16)
-#define SPC5_CGM_AC2_DC0        ((0x80U | (SPC5_FLEXCAN_DIVIDER_VALUE - 1)) << 24)
-#else
-#error "invalid SPC5_FLEXCAN_DIVIDER_VALUE value specified"
-#endif
-
-/**
- * @brief   FlexCAN clock point.
- */
-#if (SPC5_FLEXCAN_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
-#define SPC5_FLEXCAN_CLK        (SPC5_AUX2_CLK / SPC5_FLEXCAN_DIVIDER_VALUE)
-#else
-#define SPC5_FLEXCAN_CLK        0
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief   Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/**
- * @brief   Run modes.
- */
-typedef enum {
-  SPC5_RUNMODE_SAFE  = 2,
-  SPC5_RUNMODE_DRUN  = 3,
-  SPC5_RUNMODE_RUN0  = 4,
-  SPC5_RUNMODE_RUN1  = 5,
-  SPC5_RUNMODE_RUN2  = 6,
-  SPC5_RUNMODE_RUN3  = 7,
-  SPC5_RUNMODE_HALT0 = 8,
-  SPC5_RUNMODE_STOP0 = 10
-} spc5_runmode_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Realtime counter frequency.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() (halclock_t)halSPCGetSystemClock()
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#include "spc5_edma.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  halrtcnt_t hal_lld_get_counter_value(void);
-  void spc_early_init(void);
-  bool_t halSPCSetRunMode(spc5_runmode_t mode);
-  void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
-#if !SPC5_NO_INIT
-  uint32_t halSPCGetSystemClock(void);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC56ELxx/platform.mk b/os/hal/platforms/SPC56ELxx/platform.mk
deleted file mode 100644
index 07f558c7c..000000000
--- a/os/hal/platforms/SPC56ELxx/platform.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# List of all the SPC56ELxx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
-              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1
diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h
deleted file mode 100644
index 7553510bc..000000000
--- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC56ELxx/spc56el_registry.h
- * @brief   SPC56ELxx capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _SPC56EL_REGISTRY_H_
-#define _SPC56EL_REGISTRY_H_
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    SPC56ELxx capabilities
- * @{
- */
-/* eDMA attributes.*/
-#define SPC5_HAS_EDMA                       TRUE
-#define SPC5_EDMA_NCHANNELS                 16
-#define SPC5_EDMA_HAS_MUX                   TRUE
-
-/* DSPI attribures.*/
-#define SPC5_HAS_DSPI0                      TRUE
-#define SPC5_HAS_DSPI1                      TRUE
-#define SPC5_HAS_DSPI2                      TRUE
-#define SPC5_HAS_DSPI3                      FALSE
-#define SPC5_HAS_DSPI4                      FALSE
-#define SPC5_DSPI_FIFO_DEPTH                5
-#define SPC5_DSPI0_PCTL                     4
-#define SPC5_DSPI1_PCTL                     5
-#define SPC5_DSPI2_PCTL                     6
-#define SPC5_DSPI0_TX1_DMA_DEV_ID           1
-#define SPC5_DSPI0_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI0_RX_DMA_DEV_ID            2
-#define SPC5_DSPI1_TX1_DMA_DEV_ID           3
-#define SPC5_DSPI1_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI1_RX_DMA_DEV_ID            4
-#define SPC5_DSPI2_TX1_DMA_DEV_ID           5
-#define SPC5_DSPI2_TX2_DMA_DEV_ID           0
-#define SPC5_DSPI2_RX_DMA_DEV_ID            6
-#define SPC5_DSPI0_TFFF_HANDLER             vector76
-#define SPC5_DSPI0_TFFF_NUMBER              76
-#define SPC5_DSPI1_TFFF_HANDLER             vector96
-#define SPC5_DSPI1_TFFF_NUMBER              96
-#define SPC5_DSPI2_TFFF_HANDLER             vector116
-#define SPC5_DSPI2_TFFF_NUMBER              116
-#define SPC5_DSPI0_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
-#define SPC5_DSPI0_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
-#define SPC5_DSPI1_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
-#define SPC5_DSPI1_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
-#define SPC5_DSPI2_ENABLE_CLOCK()                                           \
-  halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
-#define SPC5_DSPI2_DISABLE_CLOCK()                                          \
-  halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
-
-/* LINFlex attributes.*/
-#define SPC5_HAS_LINFLEX0                   TRUE
-#define SPC5_LINFLEX0_PCTL                  48
-#define SPC5_LINFLEX0_RXI_HANDLER           vector79
-#define SPC5_LINFLEX0_TXI_HANDLER           vector80
-#define SPC5_LINFLEX0_ERR_HANDLER           vector81
-#define SPC5_LINFLEX0_RXI_NUMBER            79
-#define SPC5_LINFLEX0_TXI_NUMBER            80
-#define SPC5_LINFLEX0_ERR_NUMBER            81
-#define SPC5_LINFLEX0_CLK                   (halSPCGetSystemClock() /       \
-                                             SPC5_SYSCLK_DIVIDER_VALUE)
-
-#define SPC5_HAS_LINFLEX1                   TRUE
-#define SPC5_LINFLEX1_PCTL                  49
-#define SPC5_LINFLEX1_RXI_HANDLER           vector99
-#define SPC5_LINFLEX1_TXI_HANDLER           vector100
-#define SPC5_LINFLEX1_ERR_HANDLER           vector101
-#define SPC5_LINFLEX1_RXI_NUMBER            99
-#define SPC5_LINFLEX1_TXI_NUMBER            100
-#define SPC5_LINFLEX1_ERR_NUMBER            101
-#define SPC5_LINFLEX1_CLK                   (halSPCGetSystemClock() /       \
-                                             SPC5_SYSCLK_DIVIDER_VALUE)
-
-#define SPC5_HAS_LINFLEX2                   FALSE
-
-#define SPC5_HAS_LINFLEX3                   FALSE
-
-/* SIUL attributes.*/
-#define SPC5_HAS_SIUL                       TRUE
-#define SPC5_SIUL_NUM_PORTS                 8
-#define SPC5_SIUL_NUM_PCRS                  133
-#define SPC5_SIUL_NUM_PADSELS               44
-/** @} */
-
-/* FlexPWM attributes.*/
-#define SPC5_HAS_FLEXPWM0                   TRUE
-#define SPC5_FLEXPWM0_PCTL                  41
-#define SPC5_FLEXPWM0_RF0_HANDLER           vector179
-#define SPC5_FLEXPWM0_COF0_HANDLER          vector180
-#define SPC5_FLEXPWM0_CAF0_HANDLER          vector181
-#define SPC5_FLEXPWM0_RF1_HANDLER           vector182
-#define SPC5_FLEXPWM0_COF1_HANDLER          vector183
-#define SPC5_FLEXPWM0_CAF1_HANDLER          vector184
-#define SPC5_FLEXPWM0_RF2_HANDLER           vector185
-#define SPC5_FLEXPWM0_COF2_HANDLER          vector186
-#define SPC5_FLEXPWM0_CAF2_HANDLER          vector187
-#define SPC5_FLEXPWM0_RF3_HANDLER           vector188
-#define SPC5_FLEXPWM0_COF3_HANDLER          vector189
-#define SPC5_FLEXPWM0_CAF3_HANDLER          vector190
-#define SPC5_FLEXPWM0_FFLAG_HANDLER         vector191
-#define SPC5_FLEXPWM0_REF_HANDLER           vector192
-#define SPC5_FLEXPWM0_RF0_NUMBER            179
-#define SPC5_FLEXPWM0_COF0_NUMBER           180
-#define SPC5_FLEXPWM0_CAF0_NUMBER           181
-#define SPC5_FLEXPWM0_RF1_NUMBER            182
-#define SPC5_FLEXPWM0_COF1_NUMBER           183
-#define SPC5_FLEXPWM0_CAF1_NUMBER           184
-#define SPC5_FLEXPWM0_RF2_NUMBER            185
-#define SPC5_FLEXPWM0_COF2_NUMBER           186
-#define SPC5_FLEXPWM0_CAF2_NUMBER           187
-#define SPC5_FLEXPWM0_RF3_NUMBER            188
-#define SPC5_FLEXPWM0_COF3_NUMBER           189
-#define SPC5_FLEXPWM0_CAF3_NUMBER           190
-#define SPC5_FLEXPWM0_FFLAG_NUMBER          191
-#define SPC5_FLEXPWM0_REF_NUMBER            192
-#define SPC5_FLEXPWM0_CLK                   SPC5_MCONTROL_CLK
-
-#define SPC5_HAS_FLEXPWM1                   TRUE
-#define SPC5_FLEXPWM1_PCTL                  42
-#define SPC5_FLEXPWM1_RF0_HANDLER           vector233
-#define SPC5_FLEXPWM1_COF0_HANDLER          vector234
-#define SPC5_FLEXPWM1_CAF0_HANDLER          vector235
-#define SPC5_FLEXPWM1_RF1_HANDLER           vector236
-#define SPC5_FLEXPWM1_COF1_HANDLER          vector237
-#define SPC5_FLEXPWM1_CAF1_HANDLER          vector238
-#define SPC5_FLEXPWM1_RF2_HANDLER           vector239
-#define SPC5_FLEXPWM1_COF2_HANDLER          vector240
-#define SPC5_FLEXPWM1_CAF2_HANDLER          vector241
-#define SPC5_FLEXPWM1_RF3_HANDLER           vector242
-#define SPC5_FLEXPWM1_COF3_HANDLER          vector243
-#define SPC5_FLEXPWM1_CAF3_HANDLER          vector244
-#define SPC5_FLEXPWM1_FFLAG_HANDLER         vector245
-#define SPC5_FLEXPWM1_REF_HANDLER           vector246
-#define SPC5_FLEXPWM1_RF0_NUMBER            233
-#define SPC5_FLEXPWM1_COF0_NUMBER           234
-#define SPC5_FLEXPWM1_CAF0_NUMBER           235
-#define SPC5_FLEXPWM1_RF1_NUMBER            236
-#define SPC5_FLEXPWM1_COF1_NUMBER           237
-#define SPC5_FLEXPWM1_CAF1_NUMBER           238
-#define SPC5_FLEXPWM1_RF2_NUMBER            239
-#define SPC5_FLEXPWM1_COF2_NUMBER           240
-#define SPC5_FLEXPWM1_CAF2_NUMBER           241
-#define SPC5_FLEXPWM1_RF3_NUMBER            242
-#define SPC5_FLEXPWM1_COF3_NUMBER           243
-#define SPC5_FLEXPWM1_CAF3_NUMBER           244
-#define SPC5_FLEXPWM1_FFLAG_NUMBER          245
-#define SPC5_FLEXPWM1_REF_NUMBER            246
-#define SPC5_FLEXPWM1_CLK                   SPC5_MCONTROL_CLK
-
-/* eTimer attributes.*/
-#define SPC5_HAS_ETIMER0                    TRUE
-#define SPC5_ETIMER0_PCTL                   38
-#define SPC5_ETIMER0_TC0IR_HANDLER          vector157
-#define SPC5_ETIMER0_TC1IR_HANDLER          vector158
-#define SPC5_ETIMER0_TC2IR_HANDLER          vector159
-#define SPC5_ETIMER0_TC3IR_HANDLER          vector160
-#define SPC5_ETIMER0_TC4IR_HANDLER          vector161
-#define SPC5_ETIMER0_TC5IR_HANDLER          vector162
-#define SPC5_ETIMER0_WTIF_HANDLER           vector165
-#define SPC5_ETIMER0_RCF_HANDLER            vector167
-#define SPC5_ETIMER0_TC0IR_NUMBER           157
-#define SPC5_ETIMER0_TC1IR_NUMBER           158
-#define SPC5_ETIMER0_TC2IR_NUMBER           159
-#define SPC5_ETIMER0_TC3IR_NUMBER           160
-#define SPC5_ETIMER0_TC4IR_NUMBER           161
-#define SPC5_ETIMER0_TC5IR_NUMBER           162
-#define SPC5_ETIMER0_WTIF_NUMBER            165
-#define SPC5_ETIMER0_RCF_NUMBER             167
-#define SPC5_ETIMER0_CLK                    SPC5_MCONTROL_CLK
-
-#define SPC5_HAS_ETIMER1                    TRUE
-#define SPC5_ETIMER1_PCTL                   39
-#define SPC5_ETIMER1_TC0IR_HANDLER          vector168
-#define SPC5_ETIMER1_TC1IR_HANDLER          vector169
-#define SPC5_ETIMER1_TC2IR_HANDLER          vector170
-#define SPC5_ETIMER1_TC3IR_HANDLER          vector171
-#define SPC5_ETIMER1_TC4IR_HANDLER          vector172
-#define SPC5_ETIMER1_TC5IR_HANDLER          vector173
-#define SPC5_ETIMER1_RCF_HANDLER            vector178
-#define SPC5_ETIMER1_TC0IR_NUMBER           168
-#define SPC5_ETIMER1_TC1IR_NUMBER           169
-#define SPC5_ETIMER1_TC2IR_NUMBER           170
-#define SPC5_ETIMER1_TC3IR_NUMBER           171
-#define SPC5_ETIMER1_TC4IR_NUMBER           172
-#define SPC5_ETIMER1_TC5IR_NUMBER           173
-#define SPC5_ETIMER1_RCF_NUMBER             178
-#define SPC5_ETIMER1_CLK                    SPC5_MCONTROL_CLK
-
-#define SPC5_HAS_ETIMER2                    TRUE
-#define SPC5_ETIMER2_PCTL                   40
-#define SPC5_ETIMER2_TC0IR_HANDLER          vector222
-#define SPC5_ETIMER2_TC1IR_HANDLER          vector223
-#define SPC5_ETIMER2_TC2IR_HANDLER          vector224
-#define SPC5_ETIMER2_TC3IR_HANDLER          vector225
-#define SPC5_ETIMER2_TC4IR_HANDLER          vector226
-#define SPC5_ETIMER2_TC5IR_HANDLER          vector227
-#define SPC5_ETIMER2_RCF_HANDLER            vector232
-#define SPC5_ETIMER2_TC0IR_NUMBER           222
-#define SPC5_ETIMER2_TC1IR_NUMBER           223
-#define SPC5_ETIMER2_TC2IR_NUMBER           224
-#define SPC5_ETIMER2_TC3IR_NUMBER           225
-#define SPC5_ETIMER2_TC4IR_NUMBER           226
-#define SPC5_ETIMER2_TC5IR_NUMBER           227
-#define SPC5_ETIMER2_RCF_NUMBER             232
-#define SPC5_ETIMER2_CLK                    SPC5_MCONTROL_CLK
-
-/* FlexCAN attributes.*/
-#define SPC5_HAS_FLEXCAN0                                   TRUE
-#define SPC5_FLEXCAN0_PCTL                                  16
-#define SPC5_FLEXCAN0_MB                                    32
-#define SPC5_FLEXCAN0_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER           vector65
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER              vector66
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER               vector67
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER             vector68
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER             vector69
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER             vector70
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER             vector71
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER             vector72
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER            65
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER               66
-#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER                67
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER              68
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER              69
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER              70
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER              71
-#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER              72
-#define SPC5_FLEXCAN0_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
-#define SPC5_FLEXCAN0_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
-
-#define SPC5_HAS_FLEXCAN1                                   TRUE
-#define SPC5_FLEXCAN1_PCTL                                  17
-#define SPC5_FLEXCAN1_MB                                    32
-#define SPC5_FLEXCAN1_SHARED_IRQ                            TRUE
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER           vector85
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER              vector86
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_HANDLER               vector87
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER             vector88
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER             vector89
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER             vector90
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER             vector91
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER             vector92
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER            85
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER               86
-#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_NUMBER                87
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER              88
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER              89
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER              90
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER              91
-#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER              92
-#define SPC5_FLEXCAN1_ENABLE_CLOCK()                        halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
-#define SPC5_FLEXCAN1_DISABLE_CLOCK()                       halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
-/** @} */
-
-#endif /* _SPC56EL_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC56ELxx/typedefs.h b/os/hal/platforms/SPC56ELxx/typedefs.h
deleted file mode 100644
index ca81e4b84..000000000
--- a/os/hal/platforms/SPC56ELxx/typedefs.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC56ELxx/typedefs.h
- * @brief   Dummy typedefs file.
- */
-
-#ifndef _TYPEDEFS_H_
-#define _TYPEDEFS_H_
-
-#include "chtypes.h"
-
-#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/platforms/SPC56ELxx/xpc56el.h b/os/hal/platforms/SPC56ELxx/xpc56el.h
deleted file mode 100644
index 5d9dfefcc..000000000
--- a/os/hal/platforms/SPC56ELxx/xpc56el.h
+++ /dev/null
@@ -1,20796 +0,0 @@
-/****************************************************************************\
- * PROJECT     : MPC5643L
- * FILE        : mpc5643l.h
- * 
- * DESCRIPTION : This is the header file describing the register
- *               set for the named projects. 
- * 
- * COPYRIGHT   : (c) 2009, Freescale Semiconductor & ST Microelectronics 
- * 
- * VERSION     : 1.01
- * DATE        : Thu Oct  8 13:53:51 CEST 2009
- * AUTHOR      : generated from IP-XACT database
- * HISTORY     : Preliminary release.
-\****************************************************************************/
-
-/*   >>>>  NOTE! this file is auto-generated please do not edit it!  <<<<   */
-
-/****************************************************************************\
- * Example instantiation and use:            
- *                                           
- *  <MODULE>.<REGISTER>.B.<BIT> = 1;         
- *  <MODULE>.<REGISTER>.R       = 0x10000000;
- *                                           
-\****************************************************************************/
-
-
-#ifndef _leopard_H_  /* prevents multiple inclusions of this file */
-#define _leopard_H_
-
-#include "typedefs.h"
-
-#ifdef  __cplusplus
-extern "C" {
-#endif
-
-#ifdef __MWERKS__
-#pragma push
-#pragma ANSI_strict off
-#endif
-
-/* #define USE_FIELD_ALIASES_CFLASH */
-/* #define USE_FIELD_ALIASES_SIUL */
-/* #define USE_FIELD_ALIASES_SSCM */
-/* #define USE_FIELD_ALIASES_ME */
-/* #define USE_FIELD_ALIASES_RGM */
-/* #define USE_FIELD_ALIASES_ADC */
-/* #define USE_FIELD_ALIASES_CTU */
-/* #define USE_FIELD_ALIASES_mcTIMER */
-/* #define USE_FIELD_ALIASES_mcPWM */
-/* #define USE_FIELD_ALIASES_LINFLEX */
-/* #define USE_FIELD_ALIASES_SPP_MCM */
-/* #define USE_FIELD_ALIASES_INTC */
-/* #define USE_FIELD_ALIASES_DSPI */
-/* #define USE_FIELD_ALIASES_FLEXCAN */
-/* #define USE_FIELD_ALIASES_FR */
-
-/****************************************************************/
-/*                                                              */
-/* Global definitions and aliases */
-/*                                                              */
-/****************************************************************/
- 
-/*
-   Platform blocks that are only accessible by the second core (core 1) when
-    the device is in DPM mode. The block definition is equivalent to the one
-    for the first core (core 0) and reuses the related block structure.
-
-   NOTE: the <block_name>_1 defines are the preferred method for programming
- */
-#define  AIPS_1        (*(volatile struct AIPS_tag*)     0x8FF00000UL)
-#define  MAX_1         (*(volatile struct MAX_tag*)      0x8FF04000UL)
-#define  MPU_1         (*(volatile struct MPU_tag*)      0x8FF10000UL)
-#define  SEMA4_1       (*(volatile struct SEMA4_tag*)    0x8FF24000UL)
-#define  SWT_1         (*(volatile struct SWT_tag*)      0x8FF38000UL)
-#define  STM_1         (*(volatile struct STM_tag*)      0x8FF3C000UL)
-#define  SPP_MCM_1     (*(volatile struct SPP_MCM_tag*)  0x8FF40000UL)
-#define  SPP_DMA2_1    (*(volatile struct SPP_DMA2_tag*) 0x8FF44000UL)
-#define  INTC_1        (*(volatile struct INTC_tag*)     0x8FF48000UL)  
-
-/*
-   Platform blocks that are only accessible by the second core (core 1) when
-    the device is in DPM mode. The block definition is equivalent to the one
-    for the first core (core 0) and reuses the related block structure.
-
-   NOTE: the <block_name>_DPM defines are deprecated, use <block_name>_1 for
-         programming the corresponding blocks for new code instead.
- */
-#define  AIPS_DPM      AIPS_1
-#define  MAX_DPM       MAX_1
-#define  MPU_DPM       MPU_1
-#define  SEMA4_DPM     SEMA4_1
-#define  SWT_DPM       SWT_1
-#define  STM_DPM       STM_1
-#define  SPP_MCM_DPM   SPP_MCM_1
-#define  SPP_DMA2_DPM  SPP_DMA2_1
-#define  INTC_DPM      INTC_1
-
-/* Aliases for Pictus Module names */
-#define CAN_0     	FLEXCAN_A 
-#define CAN_1     	FLEXCAN_B 
-#define CTU_0     	CTU   
-#define DFLASH    	CRC   
-#define DMAMUX    	DMA_CH_MUX 
-#define DSPI_0    	DSPI_A 
-#define DSPI_1    	DSPI_B 
-#define DSPI_2    	DSPI_C 
-#define EDMA      	SPP_DMA2 
-#define ETIMER_0  	mcTIMER0
-#define ETIMER_1  	mcTIMER1 
-#define FLEXPWM_0 	mcPWM_A 
-#define FLEXPWM_1 	mcPWM_B 
-#define LINFLEX_0 	LINFLEX0 
-#define LINFLEX_1 	LINFLEX1 
-#define MCM_       	SPP_MCM 
-#define PIT       	PIT_RTI 
-#define SIU       	SIUL  
-#define WKUP      	WKPU 
-/****************************************************************/
-/*                                                              */
-/* Module: CFLASH_SHADOW  */
-/*                                                              */
-/****************************************************************/
-
-
-   /* Register layout for all registers NVPWD... */
-
-   typedef union {   /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  PWD:32;            /* PassWorD */
-      } B;
-   } CFLASH_SHADOW_NVPWD_32B_tag;
-
-
-   /* Register layout for all registers NVSCI... */
-
-   typedef union {   /* NVSCI - Non Volatile System Censoring Information Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  SC:16;             /* Serial Censorship Control Word */
-         vuint32_t  CW:16;             /* Censorship Control Word */
-      } B;
-   } CFLASH_SHADOW_NVSCI_32B_tag;
-
-   typedef union {   /* Non Volatile LML Default Value */
-      vuint32_t R;
-   } CFLASH_SHADOW_NVLML_32B_tag;
-
-   typedef union {   /* Non Volatile HBL Default Value */
-      vuint32_t R;
-   } CFLASH_SHADOW_NVHBL_32B_tag;
-
-   typedef union {   /* Non Volatile SLL Default Value */
-      vuint32_t R;
-   } CFLASH_SHADOW_NVSLL_32B_tag;
-
-
-   /* Register layout for all registers NVBIU... */
-
-   typedef union {   /* Non Volatile Bus Interface Unit Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  BI:32;             /* Bus interface Unit */
-      } B;
-   } CFLASH_SHADOW_NVBIU_32B_tag;
-
-   typedef union {   /* NVUSRO - Non Volatile USeR Options Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  UO:32;             /* User Options */
-      } B;
-   } CFLASH_SHADOW_NVUSRO_32B_tag;
-
-
-   typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag {
-
-                             /* Non Volatile Bus Interface Unit Register */
-      CFLASH_SHADOW_NVBIU_32B_tag NVBIU;  /* relative offset: 0x0000 */
-      int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4];
-
-   } CFLASH_SHADOW_BIU_DEFAULTS_tag;
-
-
-   typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */
-      int8_t CFLASH_SHADOW_reserved_0000_C[15832];
-      union {
-         /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
-         CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2];  /* offset: 0x3DD8  (0x0004 x 2) */
-
-         struct {
-         /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
-            CFLASH_SHADOW_NVPWD_32B_tag NVPWD0;  /* offset: 0x3DD8 size: 32 bit */
-            CFLASH_SHADOW_NVPWD_32B_tag NVPWD1;  /* offset: 0x3DDC size: 32 bit */
-         };
-
-      };
-      union {
-           /* NVSCI - Non Volatile System Censoring Information Register */
-         CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2];  /* offset: 0x3DE0  (0x0004 x 2) */
-
-         struct {
-           /* NVSCI - Non Volatile System Censoring Information Register */
-            CFLASH_SHADOW_NVSCI_32B_tag NVSCI0;  /* offset: 0x3DE0 size: 32 bit */
-            CFLASH_SHADOW_NVSCI_32B_tag NVSCI1;  /* offset: 0x3DE4 size: 32 bit */
-         };
-
-      };
-                                       /* Non Volatile LML Default Value */
-      CFLASH_SHADOW_NVLML_32B_tag NVLML;   /* offset: 0x3DE8 size: 32 bit */
-      int8_t CFLASH_SHADOW_reserved_3DEC[4];
-                                       /* Non Volatile HBL Default Value */
-      CFLASH_SHADOW_NVHBL_32B_tag NVHBL;   /* offset: 0x3DF0 size: 32 bit */
-      int8_t CFLASH_SHADOW_reserved_3DF4[4];
-                                       /* Non Volatile SLL Default Value */
-      CFLASH_SHADOW_NVSLL_32B_tag NVSLL;   /* offset: 0x3DF8 size: 32 bit */
-      int8_t CFLASH_SHADOW_reserved_3DFC_C[4];
-      union {
-                                           /*  Register set BIU_DEFAULTS */
-         CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3];  /* offset: 0x3E00  (0x0008 x 3) */
-
-         struct {
-                             /* Non Volatile Bus Interface Unit Register */
-            CFLASH_SHADOW_NVBIU_32B_tag NVBIU2;  /* offset: 0x3E00 size: 32 bit */
-            int8_t CFLASH_SHADOW_reserved_3E04_I1[4];
-            CFLASH_SHADOW_NVBIU_32B_tag NVBIU3;  /* offset: 0x3E08 size: 32 bit */
-            int8_t CFLASH_SHADOW_reserved_3E0C_I1[4];
-            CFLASH_SHADOW_NVBIU_32B_tag NVBIU4;  /* offset: 0x3E10 size: 32 bit */
-            int8_t CFLASH_SHADOW_reserved_3E14_E1[4];
-         };
-
-      };
-                          /* NVUSRO - Non Volatile USeR Options Register */
-      CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO;  /* offset: 0x3E18 size: 32 bit */
-   } CFLASH_SHADOW_tag;
-
-
-#define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: CFLASH  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* MCR - Module Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:5;
-         vuint32_t  SIZE:3;            /* Array Space Size */
-         vuint32_t:1;
-         vuint32_t  LAS:3;             /* Low Address Space */
-         vuint32_t:3;
-         vuint32_t  MAS:1;             /* Mid Address Space Configuration */
-         vuint32_t  EER:1;             /* ECC Event Error */
-         vuint32_t  RWE:1;             /* Read-while-Write Event Error */
-         vuint32_t  SBC:1;             /* Single Bit Correction */
-         vuint32_t:1;
-         vuint32_t  PEAS:1;            /* Program/Erase Access Space */
-         vuint32_t  DONE:1;            /* modify operation DONE */
-         vuint32_t  PEG:1;             /* Program/Erase Good */
-         vuint32_t:4;
-         vuint32_t  PGM:1;             /* Program Bit */
-         vuint32_t  PSUS:1;            /* Program Suspend */
-         vuint32_t  ERS:1;             /* Erase Bit */
-         vuint32_t  ESUS:1;            /* Erase Suspend */
-         vuint32_t  EHV:1;             /* Enable High Voltage */
-      } B;
-   } CFLASH_MCR_32B_tag;
-
-   typedef union {   /* LML - Low/Mid Address Space Block Locking Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  LME:1;             /* Low/Mid Address Space Block Enable */
-         vuint32_t:10;
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  SLOCK:1;           /* Shadow Address Space Block Lock */
-#else
-         vuint32_t  TSLK:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  MLOCK:2;           /* Mid Address Space Block Lock */
-#else
-         vuint32_t  MLK:2;               /* deprecated name - please avoid */
-#endif
-         vuint32_t:6;
-         vuint32_t  LLOCK:10;          /* Low Address Space Block Lock */
-      } B;
-   } CFLASH_LML_32B_tag;
-
-   typedef union {   /* HBL - High Address Space Block Locking Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  HBE:1;             /* High Address Space Block Enable */
-         vuint32_t:25;
-         vuint32_t  HLOCK:6;           /* High Address Space Block Lock */
-      } B;
-   } CFLASH_HBL_32B_tag;
-
-   typedef union {   /* SLL - Secondary Low/Mid Address Space Block Locking Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  SLE:1;             /* Secondary Low/Mid Address Space Block Enable */
-         vuint32_t:10;
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  SSLOCK:1;          /* Secondary Shadow Address Space Block Lock */
-#else
-         vuint32_t  STSLK:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  SMLOCK:2;          /* Secondary Mid Address Space Block Lock */
-#else
-         vuint32_t  SMK:2;               /* deprecated name - please avoid */
-#endif
-         vuint32_t:6;
-         vuint32_t  SLLOCK:10;         /* Secondary Low Address Space Block Lock */
-      } B;
-   } CFLASH_SLL_32B_tag;
-
-   typedef union {   /* LMS - Low/Mid Address Space Block Select Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:14;
-         vuint32_t  MSL:2;             /* Mid Address Space Block Select */
-         vuint32_t:6;
-         vuint32_t  LSL:10;            /* Low Address Space Block Select */
-      } B;
-   } CFLASH_LMS_32B_tag;
-
-   typedef union {   /* HBS - High Address Space Block Select Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:26;
-         vuint32_t  HSL:6;             /* High Address Space Block Select */
-      } B;
-   } CFLASH_HBS_32B_tag;
-
-   typedef union {   /* ADR - Address Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  SAD:1;             /* Shadow Address */
-         vuint32_t:10;
-         vuint32_t  ADDR:18;           /* Address */
-         vuint32_t:3;
-      } B;
-   } CFLASH_ADR_32B_tag;
-
-   typedef union {   /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_APC:5;         /* Bank0+2 Address Pipelining Control */
-#else
-         vuint32_t  BK0_APC:5;          /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_WWSC:5;        /* Bank0+2 Write Wait State Control */
-#else
-         vuint32_t  BK0_WWSC:5;          /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_RWSC:5;        /* Bank0+2 Read Wait State Control */
-#else
-         vuint32_t  BK0_RWSC:5;          /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_RWWC2:1;       /* Bank 0+2 Read While Write Control, bit 2 */
-#else
-         vuint32_t  BK0_RWWC2:1;         /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_RWWC1:1;       /* Bank 0+2 Read While Write Control, bit 1 */
-#else
-         vuint32_t  BK0_RWWC1:1;         /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P1_BCFG:2;     /* Bank0+2 Port 1 Page Buffer Configuration */
-#else
-         vuint32_t  B0_P1_BCFG:2;        /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P1_DPFE:1;     /* Bank0+2 Port 1 Data Prefetch Enable */
-#else
-         vuint32_t  B0_P1_DPFE:1;        /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P1_IPFE:1;     /* Bank0+2 Port 1 Inst Prefetch Enable */
-#else
-         vuint32_t  B0_P1_IPFE:1;        /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P1_PFLM:2;     /* Bank0+2 Port 1 Prefetch Limit */
-#else
-         vuint32_t  B0_P1_PFLM:2;        /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P1_BFE:1;      /* Bank0+2 Port 1 Buffer Enable */
-#else
-         vuint32_t  B0_P1_BFE:1;         /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_RWWC0:1;       /* Bank 0+2 Read While Write Control, bit 0 */
-#else
-         vuint32_t  BK0_RWWC0:1;         /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P0_BCFG:2;     /* Bank0+2 Port 0 Page Buffer Configuration */
-#else
-         vuint32_t  B0_P0_BCFG:2;        /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P0_DPFE:1;     /* Bank0+2 Port 0 Data Prefetch Enable */
-#else
-         vuint32_t  B0_P0_DPFE:1;        /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P0_IPFE:1;     /* Bank0+2 Port 0 Inst Prefetch Enable */
-#else
-         vuint32_t  B0_P0_IPFE:1;        /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P0_PFLM:2;     /* Bank0+2 Port 0 Prefetch Limit */
-#else
-         vuint32_t  B0_P0_PFLM:2;        /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  B02_P0_BFE:1;      /* Bank0+2 Port 0 Buffer Enable */
-#else
-         vuint32_t  B0_P0_BFE:1;         /* deprecated name - please avoid */
-#endif
-      } B;
-   } CFLASH_PFCR0_32B_tag;
-
-
-   /* Register layout for all registers BIU... */
-
-   typedef union {   /* Bus Interface Unit Register */
-      vuint32_t R;
-   } CFLASH_BIU_32B_tag;
-
-   typedef union {   /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_CFLASH         
-         vuint32_t  B1_APC:5;          /* Bank 1 Address Pipelining Control */          
-         vuint32_t  B1_WWSC:5;         /* Bank 1 Write Wait State Control */            
-         vuint32_t  B1_RWSC:5;         /* Bank 1 Read Wait State Control */             
-         vuint32_t  B1_RWWC2:1;        /* Bank1 Read While Write Control, bit 2 */      
-         vuint32_t  B1_RWWC1:1;        /* Bank1 Read While Write Control, bit 1 */      
-         vuint32_t:6;                                                                   
-         vuint32_t  B1_P1_BFE:1;       /* Bank 1 Port 1 Buffer Enable */                
-         vuint32_t  B1_RWWC0:1;        /* Bank1 Read While Write Control, bit 0 */      
-         vuint32_t:6;                                                                   
-         vuint32_t  B1_P0_BFE:1;       /* Bank 1 Port 0 Buffer Enable */
-#else         
-         vuint32_t BK1_APC:5;
-         vuint32_t BK1_WWSC:5;
-         vuint32_t BK1_RWSC:5;
-         vuint32_t BK1_RWWC2:1;
-         vuint32_t BK1_RWWC1:1;
-         vuint32_t:6;
-         vuint32_t B0_P1_BFE:1;
-         vuint32_t BK1_RWWC0:1;
-         vuint32_t:6;
-         vuint32_t B1_P0_BFE:1;               
-#endif
-      } B;
-   } CFLASH_PFCR1_32B_tag;
-
-   typedef union {   /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:6;
-         vuint32_t  ARBM:2;            /* Arbitration Mode */
-         vuint32_t  M7PFD:1;           /* Master x Prefetch Disable */
-         vuint32_t  M6PFD:1;           /* Master x Prefetch Disable */
-         vuint32_t  M5PFD:1;           /* Master x Prefetch Disable */
-         vuint32_t  M4PFD:1;           /* Master x Prefetch Disable */
-         vuint32_t  M3PFD:1;           /* Master x Prefetch Disable */
-         vuint32_t  M2PFD:1;           /* Master x Prefetch Disable */
-         vuint32_t  M1PFD:1;           /* Master x Prefetch Disable */
-         vuint32_t  M0PFD:1;           /* Master x Prefetch Disable */
-         vuint32_t  M7AP:2;            /* Master 7 Access Protection */
-         vuint32_t  M6AP:2;            /* Master 6 Access Protection */
-         vuint32_t  M5AP:2;            /* Master 5 Access Protection */
-         vuint32_t  M4AP:2;            /* Master 4 Access Protection */
-         vuint32_t  M3AP:2;            /* Master 3 Access Protection */
-         vuint32_t  M2AP:2;            /* Master 2 Access Protection */
-         vuint32_t  M1AP:2;            /* Master 1 Access Protection */
-         vuint32_t  M0AP:2;            /* Master 0 Access Protection */
-      } B;
-   } CFLASH_PFAPR_32B_tag;
-
-   typedef union {   /* UT0 - User Test Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  UTE:1;             /* User Test Enable */
-         vuint32_t  SBCE:1;            /* Single Bit Correction Enable */
-         vuint32_t:6;
-         vuint32_t  DSI:8;             /* Data Syndrome Input */
-         vuint32_t:10;
-         vuint32_t  MRE:1;             /* Margin Read Enable */
-         vuint32_t  MRV:1;             /* Margin Read Value */
-         vuint32_t  EIE:1;             /* ECC Data Input Enable */
-         vuint32_t  AIS:1;             /* Array Integrity Sequence */
-         vuint32_t  AIE:1;             /* Array Integrity Enable */
-         vuint32_t  AID:1;             /* Array Integrity Done */
-      } B;
-   } CFLASH_UT0_32B_tag;
-
-   typedef union {   /* UT1 - User Test Register */
-      vuint32_t R;
-   } CFLASH_UT1_32B_tag;
-
-   typedef union {   /* UT2 - User Test Register */
-      vuint32_t R;
-   } CFLASH_UT2_32B_tag;
-
-
-   /* Register layout for all registers UM... */
-
-   typedef union {   /* UM - User Multiple Input Signature Register */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_CFLASH
-         vuint32_t  MISR:32;           /* Multiple Input Signature */
-#else		 
-         vuint32_t  MS:32;         /* deprecated - please avoid */
-#endif
-      } B;
-   } CFLASH_UM_32B_tag;
-
-
-   /* Register layout for generated register(s) UT... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } CFLASH_UT_32B_tag;
-
-
-   /* Register layout for generated register(s) PFCR... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } CFLASH_PFCR_32B_tag;
-
-
-
-   typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */
-                                  /* MCR - Module Configuration Register */
-      CFLASH_MCR_32B_tag MCR;              /* offset: 0x0000 size: 32 bit */
-                   /* LML - Low/Mid Address Space Block Locking Register */
-      CFLASH_LML_32B_tag LML;              /* offset: 0x0004 size: 32 bit */
-                      /* HBL - High Address Space Block Locking Register */
-      CFLASH_HBL_32B_tag HBL;              /* offset: 0x0008 size: 32 bit */
-         /* SLL - Secondary Low/Mid Address Space Block Locking Register */
-      CFLASH_SLL_32B_tag SLL;              /* offset: 0x000C size: 32 bit */
-                    /* LMS - Low/Mid Address Space Block Select Register */
-      CFLASH_LMS_32B_tag LMS;              /* offset: 0x0010 size: 32 bit */
-                       /* HBS - High Address Space Block Select Register */
-      CFLASH_HBS_32B_tag HBS;              /* offset: 0x0014 size: 32 bit */
-                                               /* ADR - Address Register */
-      CFLASH_ADR_32B_tag ADR;              /* offset: 0x0018 size: 32 bit */
-      union {
-         struct {
-                                                                     /*  */
-            CFLASH_PFCR_32B_tag PFCR[2];   /* offset: 0x001C  (0x0004 x 2) */
-            int8_t CFLASH_reserved_0024_E0[12];
-         };
-
-                                          /* Bus Interface Unit Register */
-         CFLASH_BIU_32B_tag BIU[5];        /* offset: 0x001C  (0x0004 x 5) */
-
-         struct {
-                                          /* Bus Interface Unit Register */
-            CFLASH_BIU_32B_tag BIU0;       /* offset: 0x001C size: 32 bit */
-            CFLASH_BIU_32B_tag BIU1;       /* offset: 0x0020 size: 32 bit */
-            CFLASH_BIU_32B_tag BIU2;       /* offset: 0x0024 size: 32 bit */
-            CFLASH_BIU_32B_tag BIU3;       /* offset: 0x0028 size: 32 bit */
-            CFLASH_BIU_32B_tag BIU4;       /* offset: 0x002C size: 32 bit */
-         };
-
-         struct {
-            int8_t CFLASH_reserved_001C_I3[8];
-            CFLASH_PFAPR_32B_tag FAPR;     /* deprecated - please avoid */
-            int8_t CFLASH_reserved_0028_E3[8];
-         };
-
-         struct {
-          /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
-            CFLASH_PFCR0_32B_tag PFCR0;    /* offset: 0x001C size: 32 bit */
-          /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
-            CFLASH_PFCR1_32B_tag PFCR1;    /* offset: 0x0020 size: 32 bit */
-          /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
-            CFLASH_PFAPR_32B_tag PFAPR;    /* offset: 0x0024 size: 32 bit */
-            int8_t CFLASH_reserved_0028_E4[8];
-         };
-
-      };
-      int8_t CFLASH_reserved_0030_C[12];
-      union {
-         CFLASH_UT_32B_tag UT[3];          /* offset: 0x003C  (0x0004 x 3) */
-
-         struct {
-                                             /* UT0 - User Test Register */
-            CFLASH_UT0_32B_tag UT0;        /* offset: 0x003C size: 32 bit */
-                                             /* UT1 - User Test Register */
-            CFLASH_UT1_32B_tag UT1;        /* offset: 0x0040 size: 32 bit */
-                                             /* UT2 - User Test Register */
-            CFLASH_UT2_32B_tag UT2;        /* offset: 0x0044 size: 32 bit */
-         };
-
-      };
-      union {
-         CFLASH_UM_32B_tag UMISR[5];       /* offset: 0x0048  (0x0004 x 5) */
-
-                          /* UM - User Multiple Input Signature Register */
-         CFLASH_UM_32B_tag UM[5];          /* offset: 0x0048  (0x0004 x 5) */
-
-         struct {
-                          /* UM - User Multiple Input Signature Register */
-            CFLASH_UM_32B_tag UM0;         /* offset: 0x0048 size: 32 bit */
-            CFLASH_UM_32B_tag UM1;         /* offset: 0x004C size: 32 bit */
-            CFLASH_UM_32B_tag UM2;         /* offset: 0x0050 size: 32 bit */
-            CFLASH_UM_32B_tag UM3;         /* offset: 0x0054 size: 32 bit */
-            CFLASH_UM_32B_tag UM4;         /* offset: 0x0058 size: 32 bit */
-         };
-
-      };
-   } CFLASH_tag;
-
-
-#define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: SIUL  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* MIDR1 - MCU ID Register #1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  PARTNUM:16;        /* MCU Part Number */
-         vuint32_t  CSP:1;             /* CSP Package */
-         vuint32_t  PKG:5;             /* Package Settings */
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_SIUL
-         vuint32_t  MAJOR_MASK:4;      /* Major Mask Revision */
-#else
-         vuint32_t  MAJORMASK:4;         /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_SIUL
-         vuint32_t  MINOR_MASK:4;      /* Minor Mask Revision */
-#else
-         vuint32_t  MINORMASK:4;         /* deprecated name - please avoid */
-#endif
-      } B;
-   } SIUL_MIDR1_32B_tag;
-
-   typedef union {   /* MIDR2 - MCU ID Register #2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  SF:1;              /* Manufacturer */
-         vuint32_t  FLASH_SIZE_1:4;    /* Coarse Flash Memory Size */
-         vuint32_t  FLASH_SIZE_2:4;    /* Fine Flash Memory Size */
-         vuint32_t:7;
-#ifndef USE_FIELD_ALIASES_SIUL
-         vuint32_t  PARTNUM2:8;        /* MCU Part Number */
-#else
-         vuint32_t  PARTNUM:8;           /* deprecated name - please avoid */
-#endif
-         vuint32_t  TBD:1;             /* Optional Bit */
-         vuint32_t:2;
-         vuint32_t  EE:1;              /* Data Flash Present */
-         vuint32_t:3;
-         vuint32_t  FR:1;              /* Flexray Present */
-      } B;
-   } SIUL_MIDR2_32B_tag;
-
-   typedef union {   /* ISR - Interrupt Status Flag Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  EIF31:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF30:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF29:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF28:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF27:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF26:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF25:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF24:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF23:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF22:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF21:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF20:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF19:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF18:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF17:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF16:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF15:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF14:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF13:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF12:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF11:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF10:1;           /* External Interrupt Status Flag */
-         vuint32_t  EIF9:1;            /* External Interrupt Status Flag */
-         vuint32_t  EIF8:1;            /* External Interrupt Status Flag */
-         vuint32_t  EIF7:1;            /* External Interrupt Status Flag */
-         vuint32_t  EIF6:1;            /* External Interrupt Status Flag */
-         vuint32_t  EIF5:1;            /* External Interrupt Status Flag */
-         vuint32_t  EIF4:1;            /* External Interrupt Status Flag */
-         vuint32_t  EIF3:1;            /* External Interrupt Status Flag */
-         vuint32_t  EIF2:1;            /* External Interrupt Status Flag */
-         vuint32_t  EIF1:1;            /* External Interrupt Status Flag */
-         vuint32_t  EIF0:1;            /* External Interrupt Status Flag */
-      } B;
-   } SIUL_ISR_32B_tag;
-
-   typedef union {   /* IRER - Interrupt Request Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  EIRE31:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE30:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE29:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE28:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE27:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE26:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE25:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE24:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE23:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE22:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE21:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE20:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE19:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE18:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE17:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE16:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE15:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE14:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE13:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE12:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE11:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE10:1;          /* Enable External Interrupt Requests */
-         vuint32_t  EIRE9:1;           /* Enable External Interrupt Requests */
-         vuint32_t  EIRE8:1;           /* Enable External Interrupt Requests */
-         vuint32_t  EIRE7:1;           /* Enable External Interrupt Requests */
-         vuint32_t  EIRE6:1;           /* Enable External Interrupt Requests */
-         vuint32_t  EIRE5:1;           /* Enable External Interrupt Requests */
-         vuint32_t  EIRE4:1;           /* Enable External Interrupt Requests */
-         vuint32_t  EIRE3:1;           /* Enable External Interrupt Requests */
-         vuint32_t  EIRE2:1;           /* Enable External Interrupt Requests */
-         vuint32_t  EIRE1:1;           /* Enable External Interrupt Requests */
-         vuint32_t  EIRE0:1;           /* Enable External Interrupt Requests */
-      } B;
-   } SIUL_IRER_32B_tag;
-
-   typedef union {   /* IREER - Interrupt Rising Edge Event Enable */
-      vuint32_t R;
-      struct {
-         vuint32_t  IREE31:1;          /* Enable rising-edge events */
-         vuint32_t  IREE30:1;          /* Enable rising-edge events */
-         vuint32_t  IREE29:1;          /* Enable rising-edge events */
-         vuint32_t  IREE28:1;          /* Enable rising-edge events */
-         vuint32_t  IREE27:1;          /* Enable rising-edge events */
-         vuint32_t  IREE26:1;          /* Enable rising-edge events */
-         vuint32_t  IREE25:1;          /* Enable rising-edge events */
-         vuint32_t  IREE24:1;          /* Enable rising-edge events */
-         vuint32_t  IREE23:1;          /* Enable rising-edge events */
-         vuint32_t  IREE22:1;          /* Enable rising-edge events */
-         vuint32_t  IREE21:1;          /* Enable rising-edge events */
-         vuint32_t  IREE20:1;          /* Enable rising-edge events */
-         vuint32_t  IREE19:1;          /* Enable rising-edge events */
-         vuint32_t  IREE18:1;          /* Enable rising-edge events */
-         vuint32_t  IREE17:1;          /* Enable rising-edge events */
-         vuint32_t  IREE16:1;          /* Enable rising-edge events */
-         vuint32_t  IREE15:1;          /* Enable rising-edge events */
-         vuint32_t  IREE14:1;          /* Enable rising-edge events */
-         vuint32_t  IREE13:1;          /* Enable rising-edge events */
-         vuint32_t  IREE12:1;          /* Enable rising-edge events */
-         vuint32_t  IREE11:1;          /* Enable rising-edge events */
-         vuint32_t  IREE10:1;          /* Enable rising-edge events */
-         vuint32_t  IREE9:1;           /* Enable rising-edge events */
-         vuint32_t  IREE8:1;           /* Enable rising-edge events */
-         vuint32_t  IREE7:1;           /* Enable rising-edge events */
-         vuint32_t  IREE6:1;           /* Enable rising-edge events */
-         vuint32_t  IREE5:1;           /* Enable rising-edge events */
-         vuint32_t  IREE4:1;           /* Enable rising-edge events */
-         vuint32_t  IREE3:1;           /* Enable rising-edge events */
-         vuint32_t  IREE2:1;           /* Enable rising-edge events */
-         vuint32_t  IREE1:1;           /* Enable rising-edge events */
-         vuint32_t  IREE0:1;           /* Enable rising-edge events */
-      } B;
-   } SIUL_IREER_32B_tag;
-
-   typedef union {   /* IFEER - Interrupt Falling-Edge Event Enable */
-      vuint32_t R;
-      struct {
-         vuint32_t  IFEE31:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE30:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE29:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE28:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE27:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE26:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE25:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE24:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE23:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE22:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE21:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE20:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE19:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE18:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE17:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE16:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE15:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE14:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE13:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE12:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE11:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE10:1;          /* Enable Falling Edge Events */
-         vuint32_t  IFEE9:1;           /* Enable Falling Edge Events */
-         vuint32_t  IFEE8:1;           /* Enable Falling Edge Events */
-         vuint32_t  IFEE7:1;           /* Enable Falling Edge Events */
-         vuint32_t  IFEE6:1;           /* Enable Falling Edge Events */
-         vuint32_t  IFEE5:1;           /* Enable Falling Edge Events */
-         vuint32_t  IFEE4:1;           /* Enable Falling Edge Events */
-         vuint32_t  IFEE3:1;           /* Enable Falling Edge Events */
-         vuint32_t  IFEE2:1;           /* Enable Falling Edge Events */
-         vuint32_t  IFEE1:1;           /* Enable Falling Edge Events */
-         vuint32_t  IFEE0:1;           /* Enable Falling Edge Events */
-      } B;
-   } SIUL_IFEER_32B_tag;
-
-   typedef union {   /* IFER Interrupt Filter Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  IFE31:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE30:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE29:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE28:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE27:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE26:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE25:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE24:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE23:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE22:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE21:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE20:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE19:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE18:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE17:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE16:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE15:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE14:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE13:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE12:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE11:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE10:1;           /* Enable Digital Glitch Filter */
-         vuint32_t  IFE9:1;            /* Enable Digital Glitch Filter */
-         vuint32_t  IFE8:1;            /* Enable Digital Glitch Filter */
-         vuint32_t  IFE7:1;            /* Enable Digital Glitch Filter */
-         vuint32_t  IFE6:1;            /* Enable Digital Glitch Filter */
-         vuint32_t  IFE5:1;            /* Enable Digital Glitch Filter */
-         vuint32_t  IFE4:1;            /* Enable Digital Glitch Filter */
-         vuint32_t  IFE3:1;            /* Enable Digital Glitch Filter */
-         vuint32_t  IFE2:1;            /* Enable Digital Glitch Filter */
-         vuint32_t  IFE1:1;            /* Enable Digital Glitch Filter */
-         vuint32_t  IFE0:1;            /* Enable Digital Glitch Filter */
-      } B;
-   } SIUL_IFER_32B_tag;
-
-
-   /* Register layout for all registers PCR... */
-
-   typedef union {   /* PCR - Pad Configuration Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:1;
-#ifndef USE_FIELD_ALIASES_SIUL
-         vuint16_t  SMC:1;             /* Safe Mode Control */
-#else
-         vuint16_t  SME:1;               /* deprecated name - please avoid */
-#endif
-         vuint16_t  APC:1;             /* Analog Pad Control */
-         vuint16_t:1;
-         vuint16_t  PA:2;              /* Pad Output Assignment */
-         vuint16_t  OBE:1;             /* Output Buffer Enable */
-         vuint16_t  IBE:1;             /* Input Buffer Enable */
-#ifndef USE_FIELD_ALIASES_SIUL
-         vuint16_t  DSC:2;             /* Drive Strength Control */
-#else
-         vuint16_t  DCS:2;               /* deprecated name - please avoid */
-#endif
-         vuint16_t  ODE:1;             /* Open Drain Output Enable */
-         vuint16_t  HYS:1;             /* Input Hysteresis */
-         vuint16_t  SRC:2;             /* Slew Rate Control */
-         vuint16_t  WPE:1;             /* Weak Pull Up/Down Enable */
-         vuint16_t  WPS:1;             /* Weak Pull Up/Down Select */
-      } B;
-   } SIUL_PCR_16B_tag;
-
-
-   /* Register layout for all registers PSMI... */
-
-   typedef union {   /* PSMI - Pad Selection for Multiplexed Inputs */
-      vuint8_t R;
-      struct {
-         vuint8_t:4;
-         vuint8_t   PADSEL:4;          /* Pad selection for pin */
-      } B;
-   } SIUL_PSMI_8B_tag;
-
-
-   /* Register layout for all registers PSMI... */
-
-   typedef union {   /* PSMI - Pad Selection for Multiplexed Inputs */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  PADSEL0:4;         /* Pad selection for pin */
-         vuint32_t:4;
-         vuint32_t  PADSEL1:4;         /* Pad selection for pin */
-         vuint32_t:4;
-         vuint32_t  PADSEL2:4;         /* Pad selection for pin */
-         vuint32_t:4;
-         vuint32_t  PADSEL3:4;         /* Pad selection for pin */
-      } B;
-   } SIUL_PSMI_32B_tag;
-
-
-   /* Register layout for all registers GPDO... */
-
-   typedef union {   /* GPDO - GPIO Pad Data Output Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:7;
-         vuint8_t   PDO:1;             /* Pad Data Out */
-      } B;
-   } SIUL_GPDO_8B_tag;
-
-
-   /* Register layout for all registers GPDO... */
-
-   typedef union {   /* GPDO - GPIO Pad Data Output Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:7;
-         vuint32_t  PDO0:1;            /* Pad Data Out */
-         vuint32_t:7;
-         vuint32_t  PDO1:1;            /* Pad Data Out */
-         vuint32_t:7;
-         vuint32_t  PDO2:1;            /* Pad Data Out */
-         vuint32_t:7;
-         vuint32_t  PDO3:1;            /* Pad Data Out */
-      } B;
-   } SIUL_GPDO_32B_tag;
-
-
-   /* Register layout for all registers GPDI... */
-
-   typedef union {   /* GPDI - GPIO Pad Data Input Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:7;
-         vuint8_t   PDI:1;             /* Pad Data In */
-      } B;
-   } SIUL_GPDI_8B_tag;
-
-
-   /* Register layout for all registers GPDI... */
-
-   typedef union {   /* GPDI - GPIO Pad Data Input Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:7;
-         vuint32_t  PDI0:1;            /* Pad Data In */
-         vuint32_t:7;
-         vuint32_t  PDI1:1;            /* Pad Data In */
-         vuint32_t:7;
-         vuint32_t  PDI2:1;            /* Pad Data In */
-         vuint32_t:7;
-         vuint32_t  PDI3:1;            /* Pad Data In */
-      } B;
-   } SIUL_GPDI_32B_tag;
-
-
-   /* Register layout for all registers PGPDO... */
-
-   typedef union {   /* PGPDO - Parallel GPIO Pad Data Out Register */
-      vuint16_t R;
-   } SIUL_PGPDO_16B_tag;
-
-
-   /* Register layout for all registers PGPDI... */
-
-   typedef union {   /* PGPDI - Parallel GPIO Pad Data In Register */
-      vuint16_t R;
-   } SIUL_PGPDI_16B_tag;
-
-
-   /* Register layout for all registers MPGPDO... */
-
-   typedef union {   /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  MASK:16;           /* Mask Field */
-         vuint32_t  MPPDO:16;          /* Masked Parallel Pad Data Out */
-      } B;
-   } SIUL_MPGPDO_32B_tag;
-
-
-   /* Register layout for all registers IFMC... */
-
-   typedef union {   /* IFMC - Interrupt Filter Maximum Counter Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-         vuint32_t  MAXCNT:4;          /* Maximum Interrupt Filter Counter Setting */
-      } B;
-   } SIUL_IFMC_32B_tag;
-
-   typedef union {   /* IFCPR - Inerrupt Filter Clock Prescaler Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-         vuint32_t  IFCP:4;            /* Interrupt Filter Clock Prescaler Setting */
-      } B;
-   } SIUL_IFCPR_32B_tag;
-
-
-
-   typedef struct SIUL_struct_tag { /* start of SIUL_tag */
-      int8_t SIUL_reserved_0000_C[4];
-      union {
-         SIUL_MIDR1_32B_tag MIDR;          /* deprecated - please avoid */
-
-                                           /* MIDR1 - MCU ID Register #1 */
-         SIUL_MIDR1_32B_tag MIDR1;         /* offset: 0x0004 size: 32 bit */
-
-      };
-                                           /* MIDR2 - MCU ID Register #2 */
-      SIUL_MIDR2_32B_tag MIDR2;            /* offset: 0x0008 size: 32 bit */
-      int8_t SIUL_reserved_000C[8];
-                                 /* ISR - Interrupt Status Flag Register */
-      SIUL_ISR_32B_tag ISR;                /* offset: 0x0014 size: 32 bit */
-                             /* IRER - Interrupt Request Enable Register */
-      SIUL_IRER_32B_tag IRER;              /* offset: 0x0018 size: 32 bit */
-      int8_t SIUL_reserved_001C[12];
-                           /* IREER - Interrupt Rising Edge Event Enable */
-      SIUL_IREER_32B_tag IREER;            /* offset: 0x0028 size: 32 bit */
-                          /* IFEER - Interrupt Falling-Edge Event Enable */
-      SIUL_IFEER_32B_tag IFEER;            /* offset: 0x002C size: 32 bit */
-                                /* IFER Interrupt Filter Enable Register */
-      SIUL_IFER_32B_tag IFER;              /* offset: 0x0030 size: 32 bit */
-      int8_t SIUL_reserved_0034_C[12];
-      union {
-                                     /* PCR - Pad Configuration Register */
-         SIUL_PCR_16B_tag PCR[512];        /* offset: 0x0040  (0x0002 x 512) */
-
-         struct {
-                                     /* PCR - Pad Configuration Register */
-            SIUL_PCR_16B_tag PCR0;         /* offset: 0x0040 size: 16 bit */
-            SIUL_PCR_16B_tag PCR1;         /* offset: 0x0042 size: 16 bit */
-            SIUL_PCR_16B_tag PCR2;         /* offset: 0x0044 size: 16 bit */
-            SIUL_PCR_16B_tag PCR3;         /* offset: 0x0046 size: 16 bit */
-            SIUL_PCR_16B_tag PCR4;         /* offset: 0x0048 size: 16 bit */
-            SIUL_PCR_16B_tag PCR5;         /* offset: 0x004A size: 16 bit */
-            SIUL_PCR_16B_tag PCR6;         /* offset: 0x004C size: 16 bit */
-            SIUL_PCR_16B_tag PCR7;         /* offset: 0x004E size: 16 bit */
-            SIUL_PCR_16B_tag PCR8;         /* offset: 0x0050 size: 16 bit */
-            SIUL_PCR_16B_tag PCR9;         /* offset: 0x0052 size: 16 bit */
-            SIUL_PCR_16B_tag PCR10;        /* offset: 0x0054 size: 16 bit */
-            SIUL_PCR_16B_tag PCR11;        /* offset: 0x0056 size: 16 bit */
-            SIUL_PCR_16B_tag PCR12;        /* offset: 0x0058 size: 16 bit */
-            SIUL_PCR_16B_tag PCR13;        /* offset: 0x005A size: 16 bit */
-            SIUL_PCR_16B_tag PCR14;        /* offset: 0x005C size: 16 bit */
-            SIUL_PCR_16B_tag PCR15;        /* offset: 0x005E size: 16 bit */
-            SIUL_PCR_16B_tag PCR16;        /* offset: 0x0060 size: 16 bit */
-            SIUL_PCR_16B_tag PCR17;        /* offset: 0x0062 size: 16 bit */
-            SIUL_PCR_16B_tag PCR18;        /* offset: 0x0064 size: 16 bit */
-            SIUL_PCR_16B_tag PCR19;        /* offset: 0x0066 size: 16 bit */
-            SIUL_PCR_16B_tag PCR20;        /* offset: 0x0068 size: 16 bit */
-            SIUL_PCR_16B_tag PCR21;        /* offset: 0x006A size: 16 bit */
-            SIUL_PCR_16B_tag PCR22;        /* offset: 0x006C size: 16 bit */
-            SIUL_PCR_16B_tag PCR23;        /* offset: 0x006E size: 16 bit */
-            SIUL_PCR_16B_tag PCR24;        /* offset: 0x0070 size: 16 bit */
-            SIUL_PCR_16B_tag PCR25;        /* offset: 0x0072 size: 16 bit */
-            SIUL_PCR_16B_tag PCR26;        /* offset: 0x0074 size: 16 bit */
-            SIUL_PCR_16B_tag PCR27;        /* offset: 0x0076 size: 16 bit */
-            SIUL_PCR_16B_tag PCR28;        /* offset: 0x0078 size: 16 bit */
-            SIUL_PCR_16B_tag PCR29;        /* offset: 0x007A size: 16 bit */
-            SIUL_PCR_16B_tag PCR30;        /* offset: 0x007C size: 16 bit */
-            SIUL_PCR_16B_tag PCR31;        /* offset: 0x007E size: 16 bit */
-            SIUL_PCR_16B_tag PCR32;        /* offset: 0x0080 size: 16 bit */
-            SIUL_PCR_16B_tag PCR33;        /* offset: 0x0082 size: 16 bit */
-            SIUL_PCR_16B_tag PCR34;        /* offset: 0x0084 size: 16 bit */
-            SIUL_PCR_16B_tag PCR35;        /* offset: 0x0086 size: 16 bit */
-            SIUL_PCR_16B_tag PCR36;        /* offset: 0x0088 size: 16 bit */
-            SIUL_PCR_16B_tag PCR37;        /* offset: 0x008A size: 16 bit */
-            SIUL_PCR_16B_tag PCR38;        /* offset: 0x008C size: 16 bit */
-            SIUL_PCR_16B_tag PCR39;        /* offset: 0x008E size: 16 bit */
-            SIUL_PCR_16B_tag PCR40;        /* offset: 0x0090 size: 16 bit */
-            SIUL_PCR_16B_tag PCR41;        /* offset: 0x0092 size: 16 bit */
-            SIUL_PCR_16B_tag PCR42;        /* offset: 0x0094 size: 16 bit */
-            SIUL_PCR_16B_tag PCR43;        /* offset: 0x0096 size: 16 bit */
-            SIUL_PCR_16B_tag PCR44;        /* offset: 0x0098 size: 16 bit */
-            SIUL_PCR_16B_tag PCR45;        /* offset: 0x009A size: 16 bit */
-            SIUL_PCR_16B_tag PCR46;        /* offset: 0x009C size: 16 bit */
-            SIUL_PCR_16B_tag PCR47;        /* offset: 0x009E size: 16 bit */
-            SIUL_PCR_16B_tag PCR48;        /* offset: 0x00A0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR49;        /* offset: 0x00A2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR50;        /* offset: 0x00A4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR51;        /* offset: 0x00A6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR52;        /* offset: 0x00A8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR53;        /* offset: 0x00AA size: 16 bit */
-            SIUL_PCR_16B_tag PCR54;        /* offset: 0x00AC size: 16 bit */
-            SIUL_PCR_16B_tag PCR55;        /* offset: 0x00AE size: 16 bit */
-            SIUL_PCR_16B_tag PCR56;        /* offset: 0x00B0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR57;        /* offset: 0x00B2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR58;        /* offset: 0x00B4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR59;        /* offset: 0x00B6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR60;        /* offset: 0x00B8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR61;        /* offset: 0x00BA size: 16 bit */
-            SIUL_PCR_16B_tag PCR62;        /* offset: 0x00BC size: 16 bit */
-            SIUL_PCR_16B_tag PCR63;        /* offset: 0x00BE size: 16 bit */
-            SIUL_PCR_16B_tag PCR64;        /* offset: 0x00C0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR65;        /* offset: 0x00C2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR66;        /* offset: 0x00C4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR67;        /* offset: 0x00C6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR68;        /* offset: 0x00C8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR69;        /* offset: 0x00CA size: 16 bit */
-            SIUL_PCR_16B_tag PCR70;        /* offset: 0x00CC size: 16 bit */
-            SIUL_PCR_16B_tag PCR71;        /* offset: 0x00CE size: 16 bit */
-            SIUL_PCR_16B_tag PCR72;        /* offset: 0x00D0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR73;        /* offset: 0x00D2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR74;        /* offset: 0x00D4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR75;        /* offset: 0x00D6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR76;        /* offset: 0x00D8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR77;        /* offset: 0x00DA size: 16 bit */
-            SIUL_PCR_16B_tag PCR78;        /* offset: 0x00DC size: 16 bit */
-            SIUL_PCR_16B_tag PCR79;        /* offset: 0x00DE size: 16 bit */
-            SIUL_PCR_16B_tag PCR80;        /* offset: 0x00E0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR81;        /* offset: 0x00E2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR82;        /* offset: 0x00E4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR83;        /* offset: 0x00E6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR84;        /* offset: 0x00E8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR85;        /* offset: 0x00EA size: 16 bit */
-            SIUL_PCR_16B_tag PCR86;        /* offset: 0x00EC size: 16 bit */
-            SIUL_PCR_16B_tag PCR87;        /* offset: 0x00EE size: 16 bit */
-            SIUL_PCR_16B_tag PCR88;        /* offset: 0x00F0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR89;        /* offset: 0x00F2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR90;        /* offset: 0x00F4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR91;        /* offset: 0x00F6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR92;        /* offset: 0x00F8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR93;        /* offset: 0x00FA size: 16 bit */
-            SIUL_PCR_16B_tag PCR94;        /* offset: 0x00FC size: 16 bit */
-            SIUL_PCR_16B_tag PCR95;        /* offset: 0x00FE size: 16 bit */
-            SIUL_PCR_16B_tag PCR96;        /* offset: 0x0100 size: 16 bit */
-            SIUL_PCR_16B_tag PCR97;        /* offset: 0x0102 size: 16 bit */
-            SIUL_PCR_16B_tag PCR98;        /* offset: 0x0104 size: 16 bit */
-            SIUL_PCR_16B_tag PCR99;        /* offset: 0x0106 size: 16 bit */
-            SIUL_PCR_16B_tag PCR100;       /* offset: 0x0108 size: 16 bit */
-            SIUL_PCR_16B_tag PCR101;       /* offset: 0x010A size: 16 bit */
-            SIUL_PCR_16B_tag PCR102;       /* offset: 0x010C size: 16 bit */
-            SIUL_PCR_16B_tag PCR103;       /* offset: 0x010E size: 16 bit */
-            SIUL_PCR_16B_tag PCR104;       /* offset: 0x0110 size: 16 bit */
-            SIUL_PCR_16B_tag PCR105;       /* offset: 0x0112 size: 16 bit */
-            SIUL_PCR_16B_tag PCR106;       /* offset: 0x0114 size: 16 bit */
-            SIUL_PCR_16B_tag PCR107;       /* offset: 0x0116 size: 16 bit */
-            SIUL_PCR_16B_tag PCR108;       /* offset: 0x0118 size: 16 bit */
-            SIUL_PCR_16B_tag PCR109;       /* offset: 0x011A size: 16 bit */
-            SIUL_PCR_16B_tag PCR110;       /* offset: 0x011C size: 16 bit */
-            SIUL_PCR_16B_tag PCR111;       /* offset: 0x011E size: 16 bit */
-            SIUL_PCR_16B_tag PCR112;       /* offset: 0x0120 size: 16 bit */
-            SIUL_PCR_16B_tag PCR113;       /* offset: 0x0122 size: 16 bit */
-            SIUL_PCR_16B_tag PCR114;       /* offset: 0x0124 size: 16 bit */
-            SIUL_PCR_16B_tag PCR115;       /* offset: 0x0126 size: 16 bit */
-            SIUL_PCR_16B_tag PCR116;       /* offset: 0x0128 size: 16 bit */
-            SIUL_PCR_16B_tag PCR117;       /* offset: 0x012A size: 16 bit */
-            SIUL_PCR_16B_tag PCR118;       /* offset: 0x012C size: 16 bit */
-            SIUL_PCR_16B_tag PCR119;       /* offset: 0x012E size: 16 bit */
-            SIUL_PCR_16B_tag PCR120;       /* offset: 0x0130 size: 16 bit */
-            SIUL_PCR_16B_tag PCR121;       /* offset: 0x0132 size: 16 bit */
-            SIUL_PCR_16B_tag PCR122;       /* offset: 0x0134 size: 16 bit */
-            SIUL_PCR_16B_tag PCR123;       /* offset: 0x0136 size: 16 bit */
-            SIUL_PCR_16B_tag PCR124;       /* offset: 0x0138 size: 16 bit */
-            SIUL_PCR_16B_tag PCR125;       /* offset: 0x013A size: 16 bit */
-            SIUL_PCR_16B_tag PCR126;       /* offset: 0x013C size: 16 bit */
-            SIUL_PCR_16B_tag PCR127;       /* offset: 0x013E size: 16 bit */
-            SIUL_PCR_16B_tag PCR128;       /* offset: 0x0140 size: 16 bit */
-            SIUL_PCR_16B_tag PCR129;       /* offset: 0x0142 size: 16 bit */
-            SIUL_PCR_16B_tag PCR130;       /* offset: 0x0144 size: 16 bit */
-            SIUL_PCR_16B_tag PCR131;       /* offset: 0x0146 size: 16 bit */
-            SIUL_PCR_16B_tag PCR132;       /* offset: 0x0148 size: 16 bit */
-            SIUL_PCR_16B_tag PCR133;       /* offset: 0x014A size: 16 bit */
-            SIUL_PCR_16B_tag PCR134;       /* offset: 0x014C size: 16 bit */
-            SIUL_PCR_16B_tag PCR135;       /* offset: 0x014E size: 16 bit */
-            SIUL_PCR_16B_tag PCR136;       /* offset: 0x0150 size: 16 bit */
-            SIUL_PCR_16B_tag PCR137;       /* offset: 0x0152 size: 16 bit */
-            SIUL_PCR_16B_tag PCR138;       /* offset: 0x0154 size: 16 bit */
-            SIUL_PCR_16B_tag PCR139;       /* offset: 0x0156 size: 16 bit */
-            SIUL_PCR_16B_tag PCR140;       /* offset: 0x0158 size: 16 bit */
-            SIUL_PCR_16B_tag PCR141;       /* offset: 0x015A size: 16 bit */
-            SIUL_PCR_16B_tag PCR142;       /* offset: 0x015C size: 16 bit */
-            SIUL_PCR_16B_tag PCR143;       /* offset: 0x015E size: 16 bit */
-            SIUL_PCR_16B_tag PCR144;       /* offset: 0x0160 size: 16 bit */
-            SIUL_PCR_16B_tag PCR145;       /* offset: 0x0162 size: 16 bit */
-            SIUL_PCR_16B_tag PCR146;       /* offset: 0x0164 size: 16 bit */
-            SIUL_PCR_16B_tag PCR147;       /* offset: 0x0166 size: 16 bit */
-            SIUL_PCR_16B_tag PCR148;       /* offset: 0x0168 size: 16 bit */
-            SIUL_PCR_16B_tag PCR149;       /* offset: 0x016A size: 16 bit */
-            SIUL_PCR_16B_tag PCR150;       /* offset: 0x016C size: 16 bit */
-            SIUL_PCR_16B_tag PCR151;       /* offset: 0x016E size: 16 bit */
-            SIUL_PCR_16B_tag PCR152;       /* offset: 0x0170 size: 16 bit */
-            SIUL_PCR_16B_tag PCR153;       /* offset: 0x0172 size: 16 bit */
-            SIUL_PCR_16B_tag PCR154;       /* offset: 0x0174 size: 16 bit */
-            SIUL_PCR_16B_tag PCR155;       /* offset: 0x0176 size: 16 bit */
-            SIUL_PCR_16B_tag PCR156;       /* offset: 0x0178 size: 16 bit */
-            SIUL_PCR_16B_tag PCR157;       /* offset: 0x017A size: 16 bit */
-            SIUL_PCR_16B_tag PCR158;       /* offset: 0x017C size: 16 bit */
-            SIUL_PCR_16B_tag PCR159;       /* offset: 0x017E size: 16 bit */
-            SIUL_PCR_16B_tag PCR160;       /* offset: 0x0180 size: 16 bit */
-            SIUL_PCR_16B_tag PCR161;       /* offset: 0x0182 size: 16 bit */
-            SIUL_PCR_16B_tag PCR162;       /* offset: 0x0184 size: 16 bit */
-            SIUL_PCR_16B_tag PCR163;       /* offset: 0x0186 size: 16 bit */
-            SIUL_PCR_16B_tag PCR164;       /* offset: 0x0188 size: 16 bit */
-            SIUL_PCR_16B_tag PCR165;       /* offset: 0x018A size: 16 bit */
-            SIUL_PCR_16B_tag PCR166;       /* offset: 0x018C size: 16 bit */
-            SIUL_PCR_16B_tag PCR167;       /* offset: 0x018E size: 16 bit */
-            SIUL_PCR_16B_tag PCR168;       /* offset: 0x0190 size: 16 bit */
-            SIUL_PCR_16B_tag PCR169;       /* offset: 0x0192 size: 16 bit */
-            SIUL_PCR_16B_tag PCR170;       /* offset: 0x0194 size: 16 bit */
-            SIUL_PCR_16B_tag PCR171;       /* offset: 0x0196 size: 16 bit */
-            SIUL_PCR_16B_tag PCR172;       /* offset: 0x0198 size: 16 bit */
-            SIUL_PCR_16B_tag PCR173;       /* offset: 0x019A size: 16 bit */
-            SIUL_PCR_16B_tag PCR174;       /* offset: 0x019C size: 16 bit */
-            SIUL_PCR_16B_tag PCR175;       /* offset: 0x019E size: 16 bit */
-            SIUL_PCR_16B_tag PCR176;       /* offset: 0x01A0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR177;       /* offset: 0x01A2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR178;       /* offset: 0x01A4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR179;       /* offset: 0x01A6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR180;       /* offset: 0x01A8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR181;       /* offset: 0x01AA size: 16 bit */
-            SIUL_PCR_16B_tag PCR182;       /* offset: 0x01AC size: 16 bit */
-            SIUL_PCR_16B_tag PCR183;       /* offset: 0x01AE size: 16 bit */
-            SIUL_PCR_16B_tag PCR184;       /* offset: 0x01B0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR185;       /* offset: 0x01B2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR186;       /* offset: 0x01B4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR187;       /* offset: 0x01B6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR188;       /* offset: 0x01B8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR189;       /* offset: 0x01BA size: 16 bit */
-            SIUL_PCR_16B_tag PCR190;       /* offset: 0x01BC size: 16 bit */
-            SIUL_PCR_16B_tag PCR191;       /* offset: 0x01BE size: 16 bit */
-            SIUL_PCR_16B_tag PCR192;       /* offset: 0x01C0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR193;       /* offset: 0x01C2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR194;       /* offset: 0x01C4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR195;       /* offset: 0x01C6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR196;       /* offset: 0x01C8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR197;       /* offset: 0x01CA size: 16 bit */
-            SIUL_PCR_16B_tag PCR198;       /* offset: 0x01CC size: 16 bit */
-            SIUL_PCR_16B_tag PCR199;       /* offset: 0x01CE size: 16 bit */
-            SIUL_PCR_16B_tag PCR200;       /* offset: 0x01D0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR201;       /* offset: 0x01D2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR202;       /* offset: 0x01D4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR203;       /* offset: 0x01D6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR204;       /* offset: 0x01D8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR205;       /* offset: 0x01DA size: 16 bit */
-            SIUL_PCR_16B_tag PCR206;       /* offset: 0x01DC size: 16 bit */
-            SIUL_PCR_16B_tag PCR207;       /* offset: 0x01DE size: 16 bit */
-            SIUL_PCR_16B_tag PCR208;       /* offset: 0x01E0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR209;       /* offset: 0x01E2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR210;       /* offset: 0x01E4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR211;       /* offset: 0x01E6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR212;       /* offset: 0x01E8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR213;       /* offset: 0x01EA size: 16 bit */
-            SIUL_PCR_16B_tag PCR214;       /* offset: 0x01EC size: 16 bit */
-            SIUL_PCR_16B_tag PCR215;       /* offset: 0x01EE size: 16 bit */
-            SIUL_PCR_16B_tag PCR216;       /* offset: 0x01F0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR217;       /* offset: 0x01F2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR218;       /* offset: 0x01F4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR219;       /* offset: 0x01F6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR220;       /* offset: 0x01F8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR221;       /* offset: 0x01FA size: 16 bit */
-            SIUL_PCR_16B_tag PCR222;       /* offset: 0x01FC size: 16 bit */
-            SIUL_PCR_16B_tag PCR223;       /* offset: 0x01FE size: 16 bit */
-            SIUL_PCR_16B_tag PCR224;       /* offset: 0x0200 size: 16 bit */
-            SIUL_PCR_16B_tag PCR225;       /* offset: 0x0202 size: 16 bit */
-            SIUL_PCR_16B_tag PCR226;       /* offset: 0x0204 size: 16 bit */
-            SIUL_PCR_16B_tag PCR227;       /* offset: 0x0206 size: 16 bit */
-            SIUL_PCR_16B_tag PCR228;       /* offset: 0x0208 size: 16 bit */
-            SIUL_PCR_16B_tag PCR229;       /* offset: 0x020A size: 16 bit */
-            SIUL_PCR_16B_tag PCR230;       /* offset: 0x020C size: 16 bit */
-            SIUL_PCR_16B_tag PCR231;       /* offset: 0x020E size: 16 bit */
-            SIUL_PCR_16B_tag PCR232;       /* offset: 0x0210 size: 16 bit */
-            SIUL_PCR_16B_tag PCR233;       /* offset: 0x0212 size: 16 bit */
-            SIUL_PCR_16B_tag PCR234;       /* offset: 0x0214 size: 16 bit */
-            SIUL_PCR_16B_tag PCR235;       /* offset: 0x0216 size: 16 bit */
-            SIUL_PCR_16B_tag PCR236;       /* offset: 0x0218 size: 16 bit */
-            SIUL_PCR_16B_tag PCR237;       /* offset: 0x021A size: 16 bit */
-            SIUL_PCR_16B_tag PCR238;       /* offset: 0x021C size: 16 bit */
-            SIUL_PCR_16B_tag PCR239;       /* offset: 0x021E size: 16 bit */
-            SIUL_PCR_16B_tag PCR240;       /* offset: 0x0220 size: 16 bit */
-            SIUL_PCR_16B_tag PCR241;       /* offset: 0x0222 size: 16 bit */
-            SIUL_PCR_16B_tag PCR242;       /* offset: 0x0224 size: 16 bit */
-            SIUL_PCR_16B_tag PCR243;       /* offset: 0x0226 size: 16 bit */
-            SIUL_PCR_16B_tag PCR244;       /* offset: 0x0228 size: 16 bit */
-            SIUL_PCR_16B_tag PCR245;       /* offset: 0x022A size: 16 bit */
-            SIUL_PCR_16B_tag PCR246;       /* offset: 0x022C size: 16 bit */
-            SIUL_PCR_16B_tag PCR247;       /* offset: 0x022E size: 16 bit */
-            SIUL_PCR_16B_tag PCR248;       /* offset: 0x0230 size: 16 bit */
-            SIUL_PCR_16B_tag PCR249;       /* offset: 0x0232 size: 16 bit */
-            SIUL_PCR_16B_tag PCR250;       /* offset: 0x0234 size: 16 bit */
-            SIUL_PCR_16B_tag PCR251;       /* offset: 0x0236 size: 16 bit */
-            SIUL_PCR_16B_tag PCR252;       /* offset: 0x0238 size: 16 bit */
-            SIUL_PCR_16B_tag PCR253;       /* offset: 0x023A size: 16 bit */
-            SIUL_PCR_16B_tag PCR254;       /* offset: 0x023C size: 16 bit */
-            SIUL_PCR_16B_tag PCR255;       /* offset: 0x023E size: 16 bit */
-            SIUL_PCR_16B_tag PCR256;       /* offset: 0x0240 size: 16 bit */
-            SIUL_PCR_16B_tag PCR257;       /* offset: 0x0242 size: 16 bit */
-            SIUL_PCR_16B_tag PCR258;       /* offset: 0x0244 size: 16 bit */
-            SIUL_PCR_16B_tag PCR259;       /* offset: 0x0246 size: 16 bit */
-            SIUL_PCR_16B_tag PCR260;       /* offset: 0x0248 size: 16 bit */
-            SIUL_PCR_16B_tag PCR261;       /* offset: 0x024A size: 16 bit */
-            SIUL_PCR_16B_tag PCR262;       /* offset: 0x024C size: 16 bit */
-            SIUL_PCR_16B_tag PCR263;       /* offset: 0x024E size: 16 bit */
-            SIUL_PCR_16B_tag PCR264;       /* offset: 0x0250 size: 16 bit */
-            SIUL_PCR_16B_tag PCR265;       /* offset: 0x0252 size: 16 bit */
-            SIUL_PCR_16B_tag PCR266;       /* offset: 0x0254 size: 16 bit */
-            SIUL_PCR_16B_tag PCR267;       /* offset: 0x0256 size: 16 bit */
-            SIUL_PCR_16B_tag PCR268;       /* offset: 0x0258 size: 16 bit */
-            SIUL_PCR_16B_tag PCR269;       /* offset: 0x025A size: 16 bit */
-            SIUL_PCR_16B_tag PCR270;       /* offset: 0x025C size: 16 bit */
-            SIUL_PCR_16B_tag PCR271;       /* offset: 0x025E size: 16 bit */
-            SIUL_PCR_16B_tag PCR272;       /* offset: 0x0260 size: 16 bit */
-            SIUL_PCR_16B_tag PCR273;       /* offset: 0x0262 size: 16 bit */
-            SIUL_PCR_16B_tag PCR274;       /* offset: 0x0264 size: 16 bit */
-            SIUL_PCR_16B_tag PCR275;       /* offset: 0x0266 size: 16 bit */
-            SIUL_PCR_16B_tag PCR276;       /* offset: 0x0268 size: 16 bit */
-            SIUL_PCR_16B_tag PCR277;       /* offset: 0x026A size: 16 bit */
-            SIUL_PCR_16B_tag PCR278;       /* offset: 0x026C size: 16 bit */
-            SIUL_PCR_16B_tag PCR279;       /* offset: 0x026E size: 16 bit */
-            SIUL_PCR_16B_tag PCR280;       /* offset: 0x0270 size: 16 bit */
-            SIUL_PCR_16B_tag PCR281;       /* offset: 0x0272 size: 16 bit */
-            SIUL_PCR_16B_tag PCR282;       /* offset: 0x0274 size: 16 bit */
-            SIUL_PCR_16B_tag PCR283;       /* offset: 0x0276 size: 16 bit */
-            SIUL_PCR_16B_tag PCR284;       /* offset: 0x0278 size: 16 bit */
-            SIUL_PCR_16B_tag PCR285;       /* offset: 0x027A size: 16 bit */
-            SIUL_PCR_16B_tag PCR286;       /* offset: 0x027C size: 16 bit */
-            SIUL_PCR_16B_tag PCR287;       /* offset: 0x027E size: 16 bit */
-            SIUL_PCR_16B_tag PCR288;       /* offset: 0x0280 size: 16 bit */
-            SIUL_PCR_16B_tag PCR289;       /* offset: 0x0282 size: 16 bit */
-            SIUL_PCR_16B_tag PCR290;       /* offset: 0x0284 size: 16 bit */
-            SIUL_PCR_16B_tag PCR291;       /* offset: 0x0286 size: 16 bit */
-            SIUL_PCR_16B_tag PCR292;       /* offset: 0x0288 size: 16 bit */
-            SIUL_PCR_16B_tag PCR293;       /* offset: 0x028A size: 16 bit */
-            SIUL_PCR_16B_tag PCR294;       /* offset: 0x028C size: 16 bit */
-            SIUL_PCR_16B_tag PCR295;       /* offset: 0x028E size: 16 bit */
-            SIUL_PCR_16B_tag PCR296;       /* offset: 0x0290 size: 16 bit */
-            SIUL_PCR_16B_tag PCR297;       /* offset: 0x0292 size: 16 bit */
-            SIUL_PCR_16B_tag PCR298;       /* offset: 0x0294 size: 16 bit */
-            SIUL_PCR_16B_tag PCR299;       /* offset: 0x0296 size: 16 bit */
-            SIUL_PCR_16B_tag PCR300;       /* offset: 0x0298 size: 16 bit */
-            SIUL_PCR_16B_tag PCR301;       /* offset: 0x029A size: 16 bit */
-            SIUL_PCR_16B_tag PCR302;       /* offset: 0x029C size: 16 bit */
-            SIUL_PCR_16B_tag PCR303;       /* offset: 0x029E size: 16 bit */
-            SIUL_PCR_16B_tag PCR304;       /* offset: 0x02A0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR305;       /* offset: 0x02A2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR306;       /* offset: 0x02A4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR307;       /* offset: 0x02A6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR308;       /* offset: 0x02A8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR309;       /* offset: 0x02AA size: 16 bit */
-            SIUL_PCR_16B_tag PCR310;       /* offset: 0x02AC size: 16 bit */
-            SIUL_PCR_16B_tag PCR311;       /* offset: 0x02AE size: 16 bit */
-            SIUL_PCR_16B_tag PCR312;       /* offset: 0x02B0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR313;       /* offset: 0x02B2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR314;       /* offset: 0x02B4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR315;       /* offset: 0x02B6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR316;       /* offset: 0x02B8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR317;       /* offset: 0x02BA size: 16 bit */
-            SIUL_PCR_16B_tag PCR318;       /* offset: 0x02BC size: 16 bit */
-            SIUL_PCR_16B_tag PCR319;       /* offset: 0x02BE size: 16 bit */
-            SIUL_PCR_16B_tag PCR320;       /* offset: 0x02C0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR321;       /* offset: 0x02C2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR322;       /* offset: 0x02C4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR323;       /* offset: 0x02C6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR324;       /* offset: 0x02C8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR325;       /* offset: 0x02CA size: 16 bit */
-            SIUL_PCR_16B_tag PCR326;       /* offset: 0x02CC size: 16 bit */
-            SIUL_PCR_16B_tag PCR327;       /* offset: 0x02CE size: 16 bit */
-            SIUL_PCR_16B_tag PCR328;       /* offset: 0x02D0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR329;       /* offset: 0x02D2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR330;       /* offset: 0x02D4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR331;       /* offset: 0x02D6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR332;       /* offset: 0x02D8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR333;       /* offset: 0x02DA size: 16 bit */
-            SIUL_PCR_16B_tag PCR334;       /* offset: 0x02DC size: 16 bit */
-            SIUL_PCR_16B_tag PCR335;       /* offset: 0x02DE size: 16 bit */
-            SIUL_PCR_16B_tag PCR336;       /* offset: 0x02E0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR337;       /* offset: 0x02E2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR338;       /* offset: 0x02E4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR339;       /* offset: 0x02E6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR340;       /* offset: 0x02E8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR341;       /* offset: 0x02EA size: 16 bit */
-            SIUL_PCR_16B_tag PCR342;       /* offset: 0x02EC size: 16 bit */
-            SIUL_PCR_16B_tag PCR343;       /* offset: 0x02EE size: 16 bit */
-            SIUL_PCR_16B_tag PCR344;       /* offset: 0x02F0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR345;       /* offset: 0x02F2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR346;       /* offset: 0x02F4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR347;       /* offset: 0x02F6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR348;       /* offset: 0x02F8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR349;       /* offset: 0x02FA size: 16 bit */
-            SIUL_PCR_16B_tag PCR350;       /* offset: 0x02FC size: 16 bit */
-            SIUL_PCR_16B_tag PCR351;       /* offset: 0x02FE size: 16 bit */
-            SIUL_PCR_16B_tag PCR352;       /* offset: 0x0300 size: 16 bit */
-            SIUL_PCR_16B_tag PCR353;       /* offset: 0x0302 size: 16 bit */
-            SIUL_PCR_16B_tag PCR354;       /* offset: 0x0304 size: 16 bit */
-            SIUL_PCR_16B_tag PCR355;       /* offset: 0x0306 size: 16 bit */
-            SIUL_PCR_16B_tag PCR356;       /* offset: 0x0308 size: 16 bit */
-            SIUL_PCR_16B_tag PCR357;       /* offset: 0x030A size: 16 bit */
-            SIUL_PCR_16B_tag PCR358;       /* offset: 0x030C size: 16 bit */
-            SIUL_PCR_16B_tag PCR359;       /* offset: 0x030E size: 16 bit */
-            SIUL_PCR_16B_tag PCR360;       /* offset: 0x0310 size: 16 bit */
-            SIUL_PCR_16B_tag PCR361;       /* offset: 0x0312 size: 16 bit */
-            SIUL_PCR_16B_tag PCR362;       /* offset: 0x0314 size: 16 bit */
-            SIUL_PCR_16B_tag PCR363;       /* offset: 0x0316 size: 16 bit */
-            SIUL_PCR_16B_tag PCR364;       /* offset: 0x0318 size: 16 bit */
-            SIUL_PCR_16B_tag PCR365;       /* offset: 0x031A size: 16 bit */
-            SIUL_PCR_16B_tag PCR366;       /* offset: 0x031C size: 16 bit */
-            SIUL_PCR_16B_tag PCR367;       /* offset: 0x031E size: 16 bit */
-            SIUL_PCR_16B_tag PCR368;       /* offset: 0x0320 size: 16 bit */
-            SIUL_PCR_16B_tag PCR369;       /* offset: 0x0322 size: 16 bit */
-            SIUL_PCR_16B_tag PCR370;       /* offset: 0x0324 size: 16 bit */
-            SIUL_PCR_16B_tag PCR371;       /* offset: 0x0326 size: 16 bit */
-            SIUL_PCR_16B_tag PCR372;       /* offset: 0x0328 size: 16 bit */
-            SIUL_PCR_16B_tag PCR373;       /* offset: 0x032A size: 16 bit */
-            SIUL_PCR_16B_tag PCR374;       /* offset: 0x032C size: 16 bit */
-            SIUL_PCR_16B_tag PCR375;       /* offset: 0x032E size: 16 bit */
-            SIUL_PCR_16B_tag PCR376;       /* offset: 0x0330 size: 16 bit */
-            SIUL_PCR_16B_tag PCR377;       /* offset: 0x0332 size: 16 bit */
-            SIUL_PCR_16B_tag PCR378;       /* offset: 0x0334 size: 16 bit */
-            SIUL_PCR_16B_tag PCR379;       /* offset: 0x0336 size: 16 bit */
-            SIUL_PCR_16B_tag PCR380;       /* offset: 0x0338 size: 16 bit */
-            SIUL_PCR_16B_tag PCR381;       /* offset: 0x033A size: 16 bit */
-            SIUL_PCR_16B_tag PCR382;       /* offset: 0x033C size: 16 bit */
-            SIUL_PCR_16B_tag PCR383;       /* offset: 0x033E size: 16 bit */
-            SIUL_PCR_16B_tag PCR384;       /* offset: 0x0340 size: 16 bit */
-            SIUL_PCR_16B_tag PCR385;       /* offset: 0x0342 size: 16 bit */
-            SIUL_PCR_16B_tag PCR386;       /* offset: 0x0344 size: 16 bit */
-            SIUL_PCR_16B_tag PCR387;       /* offset: 0x0346 size: 16 bit */
-            SIUL_PCR_16B_tag PCR388;       /* offset: 0x0348 size: 16 bit */
-            SIUL_PCR_16B_tag PCR389;       /* offset: 0x034A size: 16 bit */
-            SIUL_PCR_16B_tag PCR390;       /* offset: 0x034C size: 16 bit */
-            SIUL_PCR_16B_tag PCR391;       /* offset: 0x034E size: 16 bit */
-            SIUL_PCR_16B_tag PCR392;       /* offset: 0x0350 size: 16 bit */
-            SIUL_PCR_16B_tag PCR393;       /* offset: 0x0352 size: 16 bit */
-            SIUL_PCR_16B_tag PCR394;       /* offset: 0x0354 size: 16 bit */
-            SIUL_PCR_16B_tag PCR395;       /* offset: 0x0356 size: 16 bit */
-            SIUL_PCR_16B_tag PCR396;       /* offset: 0x0358 size: 16 bit */
-            SIUL_PCR_16B_tag PCR397;       /* offset: 0x035A size: 16 bit */
-            SIUL_PCR_16B_tag PCR398;       /* offset: 0x035C size: 16 bit */
-            SIUL_PCR_16B_tag PCR399;       /* offset: 0x035E size: 16 bit */
-            SIUL_PCR_16B_tag PCR400;       /* offset: 0x0360 size: 16 bit */
-            SIUL_PCR_16B_tag PCR401;       /* offset: 0x0362 size: 16 bit */
-            SIUL_PCR_16B_tag PCR402;       /* offset: 0x0364 size: 16 bit */
-            SIUL_PCR_16B_tag PCR403;       /* offset: 0x0366 size: 16 bit */
-            SIUL_PCR_16B_tag PCR404;       /* offset: 0x0368 size: 16 bit */
-            SIUL_PCR_16B_tag PCR405;       /* offset: 0x036A size: 16 bit */
-            SIUL_PCR_16B_tag PCR406;       /* offset: 0x036C size: 16 bit */
-            SIUL_PCR_16B_tag PCR407;       /* offset: 0x036E size: 16 bit */
-            SIUL_PCR_16B_tag PCR408;       /* offset: 0x0370 size: 16 bit */
-            SIUL_PCR_16B_tag PCR409;       /* offset: 0x0372 size: 16 bit */
-            SIUL_PCR_16B_tag PCR410;       /* offset: 0x0374 size: 16 bit */
-            SIUL_PCR_16B_tag PCR411;       /* offset: 0x0376 size: 16 bit */
-            SIUL_PCR_16B_tag PCR412;       /* offset: 0x0378 size: 16 bit */
-            SIUL_PCR_16B_tag PCR413;       /* offset: 0x037A size: 16 bit */
-            SIUL_PCR_16B_tag PCR414;       /* offset: 0x037C size: 16 bit */
-            SIUL_PCR_16B_tag PCR415;       /* offset: 0x037E size: 16 bit */
-            SIUL_PCR_16B_tag PCR416;       /* offset: 0x0380 size: 16 bit */
-            SIUL_PCR_16B_tag PCR417;       /* offset: 0x0382 size: 16 bit */
-            SIUL_PCR_16B_tag PCR418;       /* offset: 0x0384 size: 16 bit */
-            SIUL_PCR_16B_tag PCR419;       /* offset: 0x0386 size: 16 bit */
-            SIUL_PCR_16B_tag PCR420;       /* offset: 0x0388 size: 16 bit */
-            SIUL_PCR_16B_tag PCR421;       /* offset: 0x038A size: 16 bit */
-            SIUL_PCR_16B_tag PCR422;       /* offset: 0x038C size: 16 bit */
-            SIUL_PCR_16B_tag PCR423;       /* offset: 0x038E size: 16 bit */
-            SIUL_PCR_16B_tag PCR424;       /* offset: 0x0390 size: 16 bit */
-            SIUL_PCR_16B_tag PCR425;       /* offset: 0x0392 size: 16 bit */
-            SIUL_PCR_16B_tag PCR426;       /* offset: 0x0394 size: 16 bit */
-            SIUL_PCR_16B_tag PCR427;       /* offset: 0x0396 size: 16 bit */
-            SIUL_PCR_16B_tag PCR428;       /* offset: 0x0398 size: 16 bit */
-            SIUL_PCR_16B_tag PCR429;       /* offset: 0x039A size: 16 bit */
-            SIUL_PCR_16B_tag PCR430;       /* offset: 0x039C size: 16 bit */
-            SIUL_PCR_16B_tag PCR431;       /* offset: 0x039E size: 16 bit */
-            SIUL_PCR_16B_tag PCR432;       /* offset: 0x03A0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR433;       /* offset: 0x03A2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR434;       /* offset: 0x03A4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR435;       /* offset: 0x03A6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR436;       /* offset: 0x03A8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR437;       /* offset: 0x03AA size: 16 bit */
-            SIUL_PCR_16B_tag PCR438;       /* offset: 0x03AC size: 16 bit */
-            SIUL_PCR_16B_tag PCR439;       /* offset: 0x03AE size: 16 bit */
-            SIUL_PCR_16B_tag PCR440;       /* offset: 0x03B0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR441;       /* offset: 0x03B2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR442;       /* offset: 0x03B4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR443;       /* offset: 0x03B6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR444;       /* offset: 0x03B8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR445;       /* offset: 0x03BA size: 16 bit */
-            SIUL_PCR_16B_tag PCR446;       /* offset: 0x03BC size: 16 bit */
-            SIUL_PCR_16B_tag PCR447;       /* offset: 0x03BE size: 16 bit */
-            SIUL_PCR_16B_tag PCR448;       /* offset: 0x03C0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR449;       /* offset: 0x03C2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR450;       /* offset: 0x03C4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR451;       /* offset: 0x03C6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR452;       /* offset: 0x03C8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR453;       /* offset: 0x03CA size: 16 bit */
-            SIUL_PCR_16B_tag PCR454;       /* offset: 0x03CC size: 16 bit */
-            SIUL_PCR_16B_tag PCR455;       /* offset: 0x03CE size: 16 bit */
-            SIUL_PCR_16B_tag PCR456;       /* offset: 0x03D0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR457;       /* offset: 0x03D2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR458;       /* offset: 0x03D4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR459;       /* offset: 0x03D6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR460;       /* offset: 0x03D8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR461;       /* offset: 0x03DA size: 16 bit */
-            SIUL_PCR_16B_tag PCR462;       /* offset: 0x03DC size: 16 bit */
-            SIUL_PCR_16B_tag PCR463;       /* offset: 0x03DE size: 16 bit */
-            SIUL_PCR_16B_tag PCR464;       /* offset: 0x03E0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR465;       /* offset: 0x03E2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR466;       /* offset: 0x03E4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR467;       /* offset: 0x03E6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR468;       /* offset: 0x03E8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR469;       /* offset: 0x03EA size: 16 bit */
-            SIUL_PCR_16B_tag PCR470;       /* offset: 0x03EC size: 16 bit */
-            SIUL_PCR_16B_tag PCR471;       /* offset: 0x03EE size: 16 bit */
-            SIUL_PCR_16B_tag PCR472;       /* offset: 0x03F0 size: 16 bit */
-            SIUL_PCR_16B_tag PCR473;       /* offset: 0x03F2 size: 16 bit */
-            SIUL_PCR_16B_tag PCR474;       /* offset: 0x03F4 size: 16 bit */
-            SIUL_PCR_16B_tag PCR475;       /* offset: 0x03F6 size: 16 bit */
-            SIUL_PCR_16B_tag PCR476;       /* offset: 0x03F8 size: 16 bit */
-            SIUL_PCR_16B_tag PCR477;       /* offset: 0x03FA size: 16 bit */
-            SIUL_PCR_16B_tag PCR478;       /* offset: 0x03FC size: 16 bit */
-            SIUL_PCR_16B_tag PCR479;       /* offset: 0x03FE size: 16 bit */
-            SIUL_PCR_16B_tag PCR480;       /* offset: 0x0400 size: 16 bit */
-            SIUL_PCR_16B_tag PCR481;       /* offset: 0x0402 size: 16 bit */
-            SIUL_PCR_16B_tag PCR482;       /* offset: 0x0404 size: 16 bit */
-            SIUL_PCR_16B_tag PCR483;       /* offset: 0x0406 size: 16 bit */
-            SIUL_PCR_16B_tag PCR484;       /* offset: 0x0408 size: 16 bit */
-            SIUL_PCR_16B_tag PCR485;       /* offset: 0x040A size: 16 bit */
-            SIUL_PCR_16B_tag PCR486;       /* offset: 0x040C size: 16 bit */
-            SIUL_PCR_16B_tag PCR487;       /* offset: 0x040E size: 16 bit */
-            SIUL_PCR_16B_tag PCR488;       /* offset: 0x0410 size: 16 bit */
-            SIUL_PCR_16B_tag PCR489;       /* offset: 0x0412 size: 16 bit */
-            SIUL_PCR_16B_tag PCR490;       /* offset: 0x0414 size: 16 bit */
-            SIUL_PCR_16B_tag PCR491;       /* offset: 0x0416 size: 16 bit */
-            SIUL_PCR_16B_tag PCR492;       /* offset: 0x0418 size: 16 bit */
-            SIUL_PCR_16B_tag PCR493;       /* offset: 0x041A size: 16 bit */
-            SIUL_PCR_16B_tag PCR494;       /* offset: 0x041C size: 16 bit */
-            SIUL_PCR_16B_tag PCR495;       /* offset: 0x041E size: 16 bit */
-            SIUL_PCR_16B_tag PCR496;       /* offset: 0x0420 size: 16 bit */
-            SIUL_PCR_16B_tag PCR497;       /* offset: 0x0422 size: 16 bit */
-            SIUL_PCR_16B_tag PCR498;       /* offset: 0x0424 size: 16 bit */
-            SIUL_PCR_16B_tag PCR499;       /* offset: 0x0426 size: 16 bit */
-            SIUL_PCR_16B_tag PCR500;       /* offset: 0x0428 size: 16 bit */
-            SIUL_PCR_16B_tag PCR501;       /* offset: 0x042A size: 16 bit */
-            SIUL_PCR_16B_tag PCR502;       /* offset: 0x042C size: 16 bit */
-            SIUL_PCR_16B_tag PCR503;       /* offset: 0x042E size: 16 bit */
-            SIUL_PCR_16B_tag PCR504;       /* offset: 0x0430 size: 16 bit */
-            SIUL_PCR_16B_tag PCR505;       /* offset: 0x0432 size: 16 bit */
-            SIUL_PCR_16B_tag PCR506;       /* offset: 0x0434 size: 16 bit */
-            SIUL_PCR_16B_tag PCR507;       /* offset: 0x0436 size: 16 bit */
-            SIUL_PCR_16B_tag PCR508;       /* offset: 0x0438 size: 16 bit */
-            SIUL_PCR_16B_tag PCR509;       /* offset: 0x043A size: 16 bit */
-            SIUL_PCR_16B_tag PCR510;       /* offset: 0x043C size: 16 bit */
-            SIUL_PCR_16B_tag PCR511;       /* offset: 0x043E size: 16 bit */
-         };
-
-      };
-      int8_t SIUL_reserved_0440_C[192];
-      union {
-                          /* PSMI - Pad Selection for Multiplexed Inputs */
-         SIUL_PSMI_32B_tag PSMI_32B[64];   /* offset: 0x0500  (0x0004 x 64) */
-
-                          /* PSMI - Pad Selection for Multiplexed Inputs */
-         SIUL_PSMI_8B_tag PSMI[256];       /* offset: 0x0500  (0x0001 x 256) */
-
-         struct {
-                          /* PSMI - Pad Selection for Multiplexed Inputs */
-            SIUL_PSMI_32B_tag PSMI0_3;     /* offset: 0x0500 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI4_7;     /* offset: 0x0504 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI8_11;    /* offset: 0x0508 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI12_15;   /* offset: 0x050C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI16_19;   /* offset: 0x0510 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI20_23;   /* offset: 0x0514 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI24_27;   /* offset: 0x0518 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI28_31;   /* offset: 0x051C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI32_35;   /* offset: 0x0520 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI36_39;   /* offset: 0x0524 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI40_43;   /* offset: 0x0528 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI44_47;   /* offset: 0x052C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI48_51;   /* offset: 0x0530 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI52_55;   /* offset: 0x0534 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI56_59;   /* offset: 0x0538 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI60_63;   /* offset: 0x053C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI64_67;   /* offset: 0x0540 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI68_71;   /* offset: 0x0544 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI72_75;   /* offset: 0x0548 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI76_79;   /* offset: 0x054C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI80_83;   /* offset: 0x0550 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI84_87;   /* offset: 0x0554 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI88_91;   /* offset: 0x0558 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI92_95;   /* offset: 0x055C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI96_99;   /* offset: 0x0560 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI100_103;  /* offset: 0x0564 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI104_107;  /* offset: 0x0568 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI108_111;  /* offset: 0x056C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI112_115;  /* offset: 0x0570 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI116_119;  /* offset: 0x0574 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI120_123;  /* offset: 0x0578 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI124_127;  /* offset: 0x057C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI128_131;  /* offset: 0x0580 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI132_135;  /* offset: 0x0584 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI136_139;  /* offset: 0x0588 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI140_143;  /* offset: 0x058C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI144_147;  /* offset: 0x0590 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI148_151;  /* offset: 0x0594 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI152_155;  /* offset: 0x0598 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI156_159;  /* offset: 0x059C size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI160_163;  /* offset: 0x05A0 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI164_167;  /* offset: 0x05A4 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI168_171;  /* offset: 0x05A8 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI172_175;  /* offset: 0x05AC size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI176_179;  /* offset: 0x05B0 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI180_183;  /* offset: 0x05B4 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI184_187;  /* offset: 0x05B8 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI188_191;  /* offset: 0x05BC size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI192_195;  /* offset: 0x05C0 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI196_199;  /* offset: 0x05C4 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI200_203;  /* offset: 0x05C8 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI204_207;  /* offset: 0x05CC size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI208_211;  /* offset: 0x05D0 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI212_215;  /* offset: 0x05D4 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI216_219;  /* offset: 0x05D8 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI220_223;  /* offset: 0x05DC size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI224_227;  /* offset: 0x05E0 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI228_231;  /* offset: 0x05E4 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI232_235;  /* offset: 0x05E8 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI236_239;  /* offset: 0x05EC size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI240_243;  /* offset: 0x05F0 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI244_247;  /* offset: 0x05F4 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI248_251;  /* offset: 0x05F8 size: 32 bit */
-            SIUL_PSMI_32B_tag PSMI252_255;  /* offset: 0x05FC size: 32 bit */
-         };
-
-         struct {
-                          /* PSMI - Pad Selection for Multiplexed Inputs */
-            SIUL_PSMI_8B_tag PSMI0;        /* offset: 0x0500 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI1;        /* offset: 0x0501 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI2;        /* offset: 0x0502 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI3;        /* offset: 0x0503 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI4;        /* offset: 0x0504 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI5;        /* offset: 0x0505 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI6;        /* offset: 0x0506 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI7;        /* offset: 0x0507 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI8;        /* offset: 0x0508 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI9;        /* offset: 0x0509 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI10;       /* offset: 0x050A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI11;       /* offset: 0x050B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI12;       /* offset: 0x050C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI13;       /* offset: 0x050D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI14;       /* offset: 0x050E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI15;       /* offset: 0x050F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI16;       /* offset: 0x0510 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI17;       /* offset: 0x0511 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI18;       /* offset: 0x0512 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI19;       /* offset: 0x0513 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI20;       /* offset: 0x0514 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI21;       /* offset: 0x0515 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI22;       /* offset: 0x0516 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI23;       /* offset: 0x0517 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI24;       /* offset: 0x0518 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI25;       /* offset: 0x0519 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI26;       /* offset: 0x051A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI27;       /* offset: 0x051B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI28;       /* offset: 0x051C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI29;       /* offset: 0x051D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI30;       /* offset: 0x051E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI31;       /* offset: 0x051F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI32;       /* offset: 0x0520 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI33;       /* offset: 0x0521 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI34;       /* offset: 0x0522 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI35;       /* offset: 0x0523 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI36;       /* offset: 0x0524 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI37;       /* offset: 0x0525 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI38;       /* offset: 0x0526 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI39;       /* offset: 0x0527 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI40;       /* offset: 0x0528 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI41;       /* offset: 0x0529 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI42;       /* offset: 0x052A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI43;       /* offset: 0x052B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI44;       /* offset: 0x052C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI45;       /* offset: 0x052D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI46;       /* offset: 0x052E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI47;       /* offset: 0x052F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI48;       /* offset: 0x0530 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI49;       /* offset: 0x0531 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI50;       /* offset: 0x0532 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI51;       /* offset: 0x0533 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI52;       /* offset: 0x0534 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI53;       /* offset: 0x0535 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI54;       /* offset: 0x0536 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI55;       /* offset: 0x0537 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI56;       /* offset: 0x0538 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI57;       /* offset: 0x0539 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI58;       /* offset: 0x053A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI59;       /* offset: 0x053B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI60;       /* offset: 0x053C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI61;       /* offset: 0x053D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI62;       /* offset: 0x053E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI63;       /* offset: 0x053F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI64;       /* offset: 0x0540 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI65;       /* offset: 0x0541 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI66;       /* offset: 0x0542 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI67;       /* offset: 0x0543 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI68;       /* offset: 0x0544 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI69;       /* offset: 0x0545 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI70;       /* offset: 0x0546 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI71;       /* offset: 0x0547 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI72;       /* offset: 0x0548 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI73;       /* offset: 0x0549 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI74;       /* offset: 0x054A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI75;       /* offset: 0x054B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI76;       /* offset: 0x054C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI77;       /* offset: 0x054D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI78;       /* offset: 0x054E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI79;       /* offset: 0x054F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI80;       /* offset: 0x0550 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI81;       /* offset: 0x0551 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI82;       /* offset: 0x0552 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI83;       /* offset: 0x0553 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI84;       /* offset: 0x0554 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI85;       /* offset: 0x0555 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI86;       /* offset: 0x0556 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI87;       /* offset: 0x0557 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI88;       /* offset: 0x0558 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI89;       /* offset: 0x0559 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI90;       /* offset: 0x055A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI91;       /* offset: 0x055B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI92;       /* offset: 0x055C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI93;       /* offset: 0x055D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI94;       /* offset: 0x055E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI95;       /* offset: 0x055F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI96;       /* offset: 0x0560 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI97;       /* offset: 0x0561 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI98;       /* offset: 0x0562 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI99;       /* offset: 0x0563 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI100;      /* offset: 0x0564 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI101;      /* offset: 0x0565 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI102;      /* offset: 0x0566 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI103;      /* offset: 0x0567 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI104;      /* offset: 0x0568 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI105;      /* offset: 0x0569 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI106;      /* offset: 0x056A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI107;      /* offset: 0x056B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI108;      /* offset: 0x056C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI109;      /* offset: 0x056D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI110;      /* offset: 0x056E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI111;      /* offset: 0x056F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI112;      /* offset: 0x0570 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI113;      /* offset: 0x0571 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI114;      /* offset: 0x0572 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI115;      /* offset: 0x0573 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI116;      /* offset: 0x0574 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI117;      /* offset: 0x0575 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI118;      /* offset: 0x0576 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI119;      /* offset: 0x0577 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI120;      /* offset: 0x0578 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI121;      /* offset: 0x0579 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI122;      /* offset: 0x057A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI123;      /* offset: 0x057B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI124;      /* offset: 0x057C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI125;      /* offset: 0x057D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI126;      /* offset: 0x057E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI127;      /* offset: 0x057F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI128;      /* offset: 0x0580 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI129;      /* offset: 0x0581 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI130;      /* offset: 0x0582 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI131;      /* offset: 0x0583 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI132;      /* offset: 0x0584 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI133;      /* offset: 0x0585 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI134;      /* offset: 0x0586 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI135;      /* offset: 0x0587 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI136;      /* offset: 0x0588 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI137;      /* offset: 0x0589 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI138;      /* offset: 0x058A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI139;      /* offset: 0x058B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI140;      /* offset: 0x058C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI141;      /* offset: 0x058D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI142;      /* offset: 0x058E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI143;      /* offset: 0x058F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI144;      /* offset: 0x0590 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI145;      /* offset: 0x0591 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI146;      /* offset: 0x0592 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI147;      /* offset: 0x0593 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI148;      /* offset: 0x0594 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI149;      /* offset: 0x0595 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI150;      /* offset: 0x0596 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI151;      /* offset: 0x0597 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI152;      /* offset: 0x0598 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI153;      /* offset: 0x0599 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI154;      /* offset: 0x059A size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI155;      /* offset: 0x059B size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI156;      /* offset: 0x059C size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI157;      /* offset: 0x059D size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI158;      /* offset: 0x059E size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI159;      /* offset: 0x059F size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI160;      /* offset: 0x05A0 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI161;      /* offset: 0x05A1 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI162;      /* offset: 0x05A2 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI163;      /* offset: 0x05A3 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI164;      /* offset: 0x05A4 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI165;      /* offset: 0x05A5 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI166;      /* offset: 0x05A6 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI167;      /* offset: 0x05A7 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI168;      /* offset: 0x05A8 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI169;      /* offset: 0x05A9 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI170;      /* offset: 0x05AA size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI171;      /* offset: 0x05AB size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI172;      /* offset: 0x05AC size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI173;      /* offset: 0x05AD size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI174;      /* offset: 0x05AE size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI175;      /* offset: 0x05AF size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI176;      /* offset: 0x05B0 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI177;      /* offset: 0x05B1 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI178;      /* offset: 0x05B2 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI179;      /* offset: 0x05B3 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI180;      /* offset: 0x05B4 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI181;      /* offset: 0x05B5 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI182;      /* offset: 0x05B6 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI183;      /* offset: 0x05B7 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI184;      /* offset: 0x05B8 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI185;      /* offset: 0x05B9 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI186;      /* offset: 0x05BA size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI187;      /* offset: 0x05BB size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI188;      /* offset: 0x05BC size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI189;      /* offset: 0x05BD size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI190;      /* offset: 0x05BE size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI191;      /* offset: 0x05BF size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI192;      /* offset: 0x05C0 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI193;      /* offset: 0x05C1 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI194;      /* offset: 0x05C2 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI195;      /* offset: 0x05C3 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI196;      /* offset: 0x05C4 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI197;      /* offset: 0x05C5 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI198;      /* offset: 0x05C6 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI199;      /* offset: 0x05C7 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI200;      /* offset: 0x05C8 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI201;      /* offset: 0x05C9 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI202;      /* offset: 0x05CA size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI203;      /* offset: 0x05CB size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI204;      /* offset: 0x05CC size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI205;      /* offset: 0x05CD size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI206;      /* offset: 0x05CE size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI207;      /* offset: 0x05CF size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI208;      /* offset: 0x05D0 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI209;      /* offset: 0x05D1 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI210;      /* offset: 0x05D2 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI211;      /* offset: 0x05D3 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI212;      /* offset: 0x05D4 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI213;      /* offset: 0x05D5 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI214;      /* offset: 0x05D6 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI215;      /* offset: 0x05D7 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI216;      /* offset: 0x05D8 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI217;      /* offset: 0x05D9 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI218;      /* offset: 0x05DA size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI219;      /* offset: 0x05DB size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI220;      /* offset: 0x05DC size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI221;      /* offset: 0x05DD size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI222;      /* offset: 0x05DE size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI223;      /* offset: 0x05DF size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI224;      /* offset: 0x05E0 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI225;      /* offset: 0x05E1 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI226;      /* offset: 0x05E2 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI227;      /* offset: 0x05E3 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI228;      /* offset: 0x05E4 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI229;      /* offset: 0x05E5 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI230;      /* offset: 0x05E6 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI231;      /* offset: 0x05E7 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI232;      /* offset: 0x05E8 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI233;      /* offset: 0x05E9 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI234;      /* offset: 0x05EA size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI235;      /* offset: 0x05EB size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI236;      /* offset: 0x05EC size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI237;      /* offset: 0x05ED size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI238;      /* offset: 0x05EE size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI239;      /* offset: 0x05EF size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI240;      /* offset: 0x05F0 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI241;      /* offset: 0x05F1 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI242;      /* offset: 0x05F2 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI243;      /* offset: 0x05F3 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI244;      /* offset: 0x05F4 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI245;      /* offset: 0x05F5 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI246;      /* offset: 0x05F6 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI247;      /* offset: 0x05F7 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI248;      /* offset: 0x05F8 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI249;      /* offset: 0x05F9 size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI250;      /* offset: 0x05FA size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI251;      /* offset: 0x05FB size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI252;      /* offset: 0x05FC size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI253;      /* offset: 0x05FD size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI254;      /* offset: 0x05FE size: 8 bit */
-            SIUL_PSMI_8B_tag PSMI255;      /* offset: 0x05FF size: 8 bit */
-         };
-
-      };
-      union {
-                                 /* GPDO - GPIO Pad Data Output Register */
-         SIUL_GPDO_32B_tag GPDO_32B[128];  /* offset: 0x0600  (0x0004 x 128) */
-
-                                 /* GPDO - GPIO Pad Data Output Register */
-         SIUL_GPDO_8B_tag GPDO[512];       /* offset: 0x0600  (0x0001 x 512) */
-
-         struct {
-                                 /* GPDO - GPIO Pad Data Output Register */
-            SIUL_GPDO_32B_tag GPDO0_3;     /* offset: 0x0600 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO4_7;     /* offset: 0x0604 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO8_11;    /* offset: 0x0608 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO12_15;   /* offset: 0x060C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO16_19;   /* offset: 0x0610 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO20_23;   /* offset: 0x0614 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO24_27;   /* offset: 0x0618 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO28_31;   /* offset: 0x061C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO32_35;   /* offset: 0x0620 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO36_39;   /* offset: 0x0624 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO40_43;   /* offset: 0x0628 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO44_47;   /* offset: 0x062C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO48_51;   /* offset: 0x0630 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO52_55;   /* offset: 0x0634 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO56_59;   /* offset: 0x0638 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO60_63;   /* offset: 0x063C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO64_67;   /* offset: 0x0640 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO68_71;   /* offset: 0x0644 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO72_75;   /* offset: 0x0648 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO76_79;   /* offset: 0x064C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO80_83;   /* offset: 0x0650 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO84_87;   /* offset: 0x0654 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO88_91;   /* offset: 0x0658 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO92_95;   /* offset: 0x065C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO96_99;   /* offset: 0x0660 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO100_103;  /* offset: 0x0664 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO104_107;  /* offset: 0x0668 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO108_111;  /* offset: 0x066C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO112_115;  /* offset: 0x0670 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO116_119;  /* offset: 0x0674 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO120_123;  /* offset: 0x0678 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO124_127;  /* offset: 0x067C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO128_131;  /* offset: 0x0680 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO132_135;  /* offset: 0x0684 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO136_139;  /* offset: 0x0688 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO140_143;  /* offset: 0x068C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO144_147;  /* offset: 0x0690 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO148_151;  /* offset: 0x0694 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO152_155;  /* offset: 0x0698 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO156_159;  /* offset: 0x069C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO160_163;  /* offset: 0x06A0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO164_167;  /* offset: 0x06A4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO168_171;  /* offset: 0x06A8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO172_175;  /* offset: 0x06AC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO176_179;  /* offset: 0x06B0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO180_183;  /* offset: 0x06B4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO184_187;  /* offset: 0x06B8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO188_191;  /* offset: 0x06BC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO192_195;  /* offset: 0x06C0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO196_199;  /* offset: 0x06C4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO200_203;  /* offset: 0x06C8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO204_207;  /* offset: 0x06CC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO208_211;  /* offset: 0x06D0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO212_215;  /* offset: 0x06D4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO216_219;  /* offset: 0x06D8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO220_223;  /* offset: 0x06DC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO224_227;  /* offset: 0x06E0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO228_231;  /* offset: 0x06E4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO232_235;  /* offset: 0x06E8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO236_239;  /* offset: 0x06EC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO240_243;  /* offset: 0x06F0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO244_247;  /* offset: 0x06F4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO248_251;  /* offset: 0x06F8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO252_255;  /* offset: 0x06FC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO256_259;  /* offset: 0x0700 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO260_263;  /* offset: 0x0704 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO264_267;  /* offset: 0x0708 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO268_271;  /* offset: 0x070C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO272_275;  /* offset: 0x0710 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO276_279;  /* offset: 0x0714 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO280_283;  /* offset: 0x0718 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO284_287;  /* offset: 0x071C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO288_291;  /* offset: 0x0720 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO292_295;  /* offset: 0x0724 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO296_299;  /* offset: 0x0728 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO300_303;  /* offset: 0x072C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO304_307;  /* offset: 0x0730 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO308_311;  /* offset: 0x0734 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO312_315;  /* offset: 0x0738 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO316_319;  /* offset: 0x073C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO320_323;  /* offset: 0x0740 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO324_327;  /* offset: 0x0744 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO328_331;  /* offset: 0x0748 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO332_335;  /* offset: 0x074C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO336_339;  /* offset: 0x0750 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO340_343;  /* offset: 0x0754 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO344_347;  /* offset: 0x0758 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO348_351;  /* offset: 0x075C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO352_355;  /* offset: 0x0760 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO356_359;  /* offset: 0x0764 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO360_363;  /* offset: 0x0768 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO364_367;  /* offset: 0x076C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO368_371;  /* offset: 0x0770 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO372_375;  /* offset: 0x0774 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO376_379;  /* offset: 0x0778 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO380_383;  /* offset: 0x077C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO384_387;  /* offset: 0x0780 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO388_391;  /* offset: 0x0784 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO392_395;  /* offset: 0x0788 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO396_399;  /* offset: 0x078C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO400_403;  /* offset: 0x0790 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO404_407;  /* offset: 0x0794 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO408_411;  /* offset: 0x0798 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO412_415;  /* offset: 0x079C size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO416_419;  /* offset: 0x07A0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO420_423;  /* offset: 0x07A4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO424_427;  /* offset: 0x07A8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO428_431;  /* offset: 0x07AC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO432_435;  /* offset: 0x07B0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO436_439;  /* offset: 0x07B4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO440_443;  /* offset: 0x07B8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO444_447;  /* offset: 0x07BC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO448_451;  /* offset: 0x07C0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO452_455;  /* offset: 0x07C4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO456_459;  /* offset: 0x07C8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO460_463;  /* offset: 0x07CC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO464_467;  /* offset: 0x07D0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO468_471;  /* offset: 0x07D4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO472_475;  /* offset: 0x07D8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO476_479;  /* offset: 0x07DC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO480_483;  /* offset: 0x07E0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO484_487;  /* offset: 0x07E4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO488_491;  /* offset: 0x07E8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO492_495;  /* offset: 0x07EC size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO496_499;  /* offset: 0x07F0 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO500_503;  /* offset: 0x07F4 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO504_507;  /* offset: 0x07F8 size: 32 bit */
-            SIUL_GPDO_32B_tag GPDO508_511;  /* offset: 0x07FC size: 32 bit */
-         };
-
-         struct {
-                                 /* GPDO - GPIO Pad Data Output Register */
-            SIUL_GPDO_8B_tag GPDO0;        /* offset: 0x0600 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO1;        /* offset: 0x0601 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO2;        /* offset: 0x0602 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO3;        /* offset: 0x0603 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO4;        /* offset: 0x0604 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO5;        /* offset: 0x0605 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO6;        /* offset: 0x0606 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO7;        /* offset: 0x0607 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO8;        /* offset: 0x0608 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO9;        /* offset: 0x0609 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO10;       /* offset: 0x060A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO11;       /* offset: 0x060B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO12;       /* offset: 0x060C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO13;       /* offset: 0x060D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO14;       /* offset: 0x060E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO15;       /* offset: 0x060F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO16;       /* offset: 0x0610 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO17;       /* offset: 0x0611 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO18;       /* offset: 0x0612 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO19;       /* offset: 0x0613 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO20;       /* offset: 0x0614 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO21;       /* offset: 0x0615 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO22;       /* offset: 0x0616 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO23;       /* offset: 0x0617 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO24;       /* offset: 0x0618 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO25;       /* offset: 0x0619 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO26;       /* offset: 0x061A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO27;       /* offset: 0x061B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO28;       /* offset: 0x061C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO29;       /* offset: 0x061D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO30;       /* offset: 0x061E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO31;       /* offset: 0x061F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO32;       /* offset: 0x0620 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO33;       /* offset: 0x0621 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO34;       /* offset: 0x0622 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO35;       /* offset: 0x0623 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO36;       /* offset: 0x0624 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO37;       /* offset: 0x0625 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO38;       /* offset: 0x0626 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO39;       /* offset: 0x0627 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO40;       /* offset: 0x0628 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO41;       /* offset: 0x0629 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO42;       /* offset: 0x062A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO43;       /* offset: 0x062B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO44;       /* offset: 0x062C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO45;       /* offset: 0x062D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO46;       /* offset: 0x062E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO47;       /* offset: 0x062F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO48;       /* offset: 0x0630 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO49;       /* offset: 0x0631 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO50;       /* offset: 0x0632 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO51;       /* offset: 0x0633 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO52;       /* offset: 0x0634 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO53;       /* offset: 0x0635 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO54;       /* offset: 0x0636 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO55;       /* offset: 0x0637 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO56;       /* offset: 0x0638 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO57;       /* offset: 0x0639 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO58;       /* offset: 0x063A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO59;       /* offset: 0x063B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO60;       /* offset: 0x063C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO61;       /* offset: 0x063D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO62;       /* offset: 0x063E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO63;       /* offset: 0x063F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO64;       /* offset: 0x0640 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO65;       /* offset: 0x0641 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO66;       /* offset: 0x0642 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO67;       /* offset: 0x0643 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO68;       /* offset: 0x0644 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO69;       /* offset: 0x0645 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO70;       /* offset: 0x0646 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO71;       /* offset: 0x0647 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO72;       /* offset: 0x0648 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO73;       /* offset: 0x0649 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO74;       /* offset: 0x064A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO75;       /* offset: 0x064B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO76;       /* offset: 0x064C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO77;       /* offset: 0x064D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO78;       /* offset: 0x064E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO79;       /* offset: 0x064F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO80;       /* offset: 0x0650 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO81;       /* offset: 0x0651 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO82;       /* offset: 0x0652 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO83;       /* offset: 0x0653 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO84;       /* offset: 0x0654 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO85;       /* offset: 0x0655 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO86;       /* offset: 0x0656 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO87;       /* offset: 0x0657 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO88;       /* offset: 0x0658 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO89;       /* offset: 0x0659 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO90;       /* offset: 0x065A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO91;       /* offset: 0x065B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO92;       /* offset: 0x065C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO93;       /* offset: 0x065D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO94;       /* offset: 0x065E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO95;       /* offset: 0x065F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO96;       /* offset: 0x0660 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO97;       /* offset: 0x0661 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO98;       /* offset: 0x0662 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO99;       /* offset: 0x0663 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO100;      /* offset: 0x0664 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO101;      /* offset: 0x0665 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO108;      /* offset: 0x066C size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO111;      /* offset: 0x066F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO112;      /* offset: 0x0670 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO113;      /* offset: 0x0671 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO116;      /* offset: 0x0674 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO117;      /* offset: 0x0675 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO122;      /* offset: 0x067A size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO124;      /* offset: 0x067C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO125;      /* offset: 0x067D size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO127;      /* offset: 0x067F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO128;      /* offset: 0x0680 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO134;      /* offset: 0x0686 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO135;      /* offset: 0x0687 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO136;      /* offset: 0x0688 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO137;      /* offset: 0x0689 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO139;      /* offset: 0x068B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO140;      /* offset: 0x068C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO141;      /* offset: 0x068D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO142;      /* offset: 0x068E size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO144;      /* offset: 0x0690 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO145;      /* offset: 0x0691 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO146;      /* offset: 0x0692 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO147;      /* offset: 0x0693 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO148;      /* offset: 0x0694 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO149;      /* offset: 0x0695 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO150;      /* offset: 0x0696 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO151;      /* offset: 0x0697 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO152;      /* offset: 0x0698 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO153;      /* offset: 0x0699 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO154;      /* offset: 0x069A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO155;      /* offset: 0x069B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO156;      /* offset: 0x069C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO157;      /* offset: 0x069D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO158;      /* offset: 0x069E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO159;      /* offset: 0x069F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO160;      /* offset: 0x06A0 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO161;      /* offset: 0x06A1 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO162;      /* offset: 0x06A2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO163;      /* offset: 0x06A3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO164;      /* offset: 0x06A4 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO165;      /* offset: 0x06A5 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO166;      /* offset: 0x06A6 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO167;      /* offset: 0x06A7 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO168;      /* offset: 0x06A8 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO169;      /* offset: 0x06A9 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO170;      /* offset: 0x06AA size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO172;      /* offset: 0x06AC size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO173;      /* offset: 0x06AD size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO174;      /* offset: 0x06AE size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO175;      /* offset: 0x06AF size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO177;      /* offset: 0x06B1 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO178;      /* offset: 0x06B2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO179;      /* offset: 0x06B3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO180;      /* offset: 0x06B4 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO181;      /* offset: 0x06B5 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO184;      /* offset: 0x06B8 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO185;      /* offset: 0x06B9 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO186;      /* offset: 0x06BA size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO188;      /* offset: 0x06BC size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO189;      /* offset: 0x06BD size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO191;      /* offset: 0x06BF size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO193;      /* offset: 0x06C1 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO194;      /* offset: 0x06C2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO195;      /* offset: 0x06C3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO196;      /* offset: 0x06C4 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO197;      /* offset: 0x06C5 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO198;      /* offset: 0x06C6 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO199;      /* offset: 0x06C7 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO201;      /* offset: 0x06C9 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO206;      /* offset: 0x06CE size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO207;      /* offset: 0x06CF size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO210;      /* offset: 0x06D2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO211;      /* offset: 0x06D3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO212;      /* offset: 0x06D4 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO217;      /* offset: 0x06D9 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO218;      /* offset: 0x06DA size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO226;      /* offset: 0x06E2 size: 8 bit */
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-            SIUL_GPDO_8B_tag GPDO338;      /* offset: 0x0752 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO339;      /* offset: 0x0753 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO340;      /* offset: 0x0754 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO341;      /* offset: 0x0755 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO342;      /* offset: 0x0756 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO343;      /* offset: 0x0757 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO344;      /* offset: 0x0758 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO345;      /* offset: 0x0759 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO346;      /* offset: 0x075A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO347;      /* offset: 0x075B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO348;      /* offset: 0x075C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO349;      /* offset: 0x075D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO350;      /* offset: 0x075E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO351;      /* offset: 0x075F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO352;      /* offset: 0x0760 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO353;      /* offset: 0x0761 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO354;      /* offset: 0x0762 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO355;      /* offset: 0x0763 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO356;      /* offset: 0x0764 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO357;      /* offset: 0x0765 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO358;      /* offset: 0x0766 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO359;      /* offset: 0x0767 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO360;      /* offset: 0x0768 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO361;      /* offset: 0x0769 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO362;      /* offset: 0x076A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO363;      /* offset: 0x076B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO364;      /* offset: 0x076C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO365;      /* offset: 0x076D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO366;      /* offset: 0x076E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO367;      /* offset: 0x076F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO368;      /* offset: 0x0770 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO369;      /* offset: 0x0771 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO370;      /* offset: 0x0772 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO371;      /* offset: 0x0773 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO372;      /* offset: 0x0774 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO373;      /* offset: 0x0775 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO374;      /* offset: 0x0776 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO375;      /* offset: 0x0777 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO376;      /* offset: 0x0778 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO377;      /* offset: 0x0779 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO378;      /* offset: 0x077A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO379;      /* offset: 0x077B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO380;      /* offset: 0x077C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO381;      /* offset: 0x077D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO382;      /* offset: 0x077E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO383;      /* offset: 0x077F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO384;      /* offset: 0x0780 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO385;      /* offset: 0x0781 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO386;      /* offset: 0x0782 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO387;      /* offset: 0x0783 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO388;      /* offset: 0x0784 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO389;      /* offset: 0x0785 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO390;      /* offset: 0x0786 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO391;      /* offset: 0x0787 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO392;      /* offset: 0x0788 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO393;      /* offset: 0x0789 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO394;      /* offset: 0x078A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO395;      /* offset: 0x078B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO396;      /* offset: 0x078C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO397;      /* offset: 0x078D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO398;      /* offset: 0x078E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO399;      /* offset: 0x078F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO400;      /* offset: 0x0790 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO401;      /* offset: 0x0791 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO402;      /* offset: 0x0792 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO403;      /* offset: 0x0793 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO404;      /* offset: 0x0794 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO405;      /* offset: 0x0795 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO406;      /* offset: 0x0796 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO407;      /* offset: 0x0797 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO408;      /* offset: 0x0798 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO409;      /* offset: 0x0799 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO410;      /* offset: 0x079A size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO411;      /* offset: 0x079B size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO412;      /* offset: 0x079C size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO413;      /* offset: 0x079D size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO414;      /* offset: 0x079E size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO415;      /* offset: 0x079F size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO416;      /* offset: 0x07A0 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO417;      /* offset: 0x07A1 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO418;      /* offset: 0x07A2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO419;      /* offset: 0x07A3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO420;      /* offset: 0x07A4 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO421;      /* offset: 0x07A5 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO422;      /* offset: 0x07A6 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO423;      /* offset: 0x07A7 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO424;      /* offset: 0x07A8 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO425;      /* offset: 0x07A9 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO426;      /* offset: 0x07AA size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO427;      /* offset: 0x07AB size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO428;      /* offset: 0x07AC size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO429;      /* offset: 0x07AD size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO430;      /* offset: 0x07AE size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO431;      /* offset: 0x07AF size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO432;      /* offset: 0x07B0 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO433;      /* offset: 0x07B1 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO434;      /* offset: 0x07B2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO435;      /* offset: 0x07B3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO436;      /* offset: 0x07B4 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO437;      /* offset: 0x07B5 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO438;      /* offset: 0x07B6 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO439;      /* offset: 0x07B7 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO440;      /* offset: 0x07B8 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO441;      /* offset: 0x07B9 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO442;      /* offset: 0x07BA size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO443;      /* offset: 0x07BB size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO444;      /* offset: 0x07BC size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO445;      /* offset: 0x07BD size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO446;      /* offset: 0x07BE size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO447;      /* offset: 0x07BF size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO448;      /* offset: 0x07C0 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO449;      /* offset: 0x07C1 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO450;      /* offset: 0x07C2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO451;      /* offset: 0x07C3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO452;      /* offset: 0x07C4 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO453;      /* offset: 0x07C5 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO454;      /* offset: 0x07C6 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO455;      /* offset: 0x07C7 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO456;      /* offset: 0x07C8 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO457;      /* offset: 0x07C9 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO458;      /* offset: 0x07CA size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO459;      /* offset: 0x07CB size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO460;      /* offset: 0x07CC size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO461;      /* offset: 0x07CD size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO462;      /* offset: 0x07CE size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO463;      /* offset: 0x07CF size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO464;      /* offset: 0x07D0 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO465;      /* offset: 0x07D1 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO466;      /* offset: 0x07D2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO467;      /* offset: 0x07D3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO468;      /* offset: 0x07D4 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO469;      /* offset: 0x07D5 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO470;      /* offset: 0x07D6 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO471;      /* offset: 0x07D7 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO472;      /* offset: 0x07D8 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO473;      /* offset: 0x07D9 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO474;      /* offset: 0x07DA size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO475;      /* offset: 0x07DB size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO476;      /* offset: 0x07DC size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO477;      /* offset: 0x07DD size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO478;      /* offset: 0x07DE size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO479;      /* offset: 0x07DF size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO480;      /* offset: 0x07E0 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO481;      /* offset: 0x07E1 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO482;      /* offset: 0x07E2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO483;      /* offset: 0x07E3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO484;      /* offset: 0x07E4 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO485;      /* offset: 0x07E5 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO486;      /* offset: 0x07E6 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO487;      /* offset: 0x07E7 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO488;      /* offset: 0x07E8 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO489;      /* offset: 0x07E9 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO490;      /* offset: 0x07EA size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO491;      /* offset: 0x07EB size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO492;      /* offset: 0x07EC size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO493;      /* offset: 0x07ED size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO494;      /* offset: 0x07EE size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO495;      /* offset: 0x07EF size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO496;      /* offset: 0x07F0 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO497;      /* offset: 0x07F1 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO498;      /* offset: 0x07F2 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO499;      /* offset: 0x07F3 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO500;      /* offset: 0x07F4 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO501;      /* offset: 0x07F5 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO502;      /* offset: 0x07F6 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO503;      /* offset: 0x07F7 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO504;      /* offset: 0x07F8 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO505;      /* offset: 0x07F9 size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO506;      /* offset: 0x07FA size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO507;      /* offset: 0x07FB size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO508;      /* offset: 0x07FC size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO509;      /* offset: 0x07FD size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO510;      /* offset: 0x07FE size: 8 bit */
-            SIUL_GPDO_8B_tag GPDO511;      /* offset: 0x07FF size: 8 bit */
-         };
-
-      };
-      union {
-                                  /* GPDI - GPIO Pad Data Input Register */
-         SIUL_GPDI_32B_tag GPDI_32B[128];  /* offset: 0x0800  (0x0004 x 128) */
-
-                                  /* GPDI - GPIO Pad Data Input Register */
-         SIUL_GPDI_8B_tag GPDI[512];       /* offset: 0x0800  (0x0001 x 512) */
-
-         struct {
-                                  /* GPDI - GPIO Pad Data Input Register */
-            SIUL_GPDI_32B_tag GPDI0_3;     /* offset: 0x0800 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI4_7;     /* offset: 0x0804 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI8_11;    /* offset: 0x0808 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI12_15;   /* offset: 0x080C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI16_19;   /* offset: 0x0810 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI20_23;   /* offset: 0x0814 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI24_27;   /* offset: 0x0818 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI28_31;   /* offset: 0x081C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI32_35;   /* offset: 0x0820 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI36_39;   /* offset: 0x0824 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI40_43;   /* offset: 0x0828 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI44_47;   /* offset: 0x082C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI48_51;   /* offset: 0x0830 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI52_55;   /* offset: 0x0834 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI56_59;   /* offset: 0x0838 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI60_63;   /* offset: 0x083C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI64_67;   /* offset: 0x0840 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI68_71;   /* offset: 0x0844 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI72_75;   /* offset: 0x0848 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI76_79;   /* offset: 0x084C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI80_83;   /* offset: 0x0850 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI84_87;   /* offset: 0x0854 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI88_91;   /* offset: 0x0858 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI92_95;   /* offset: 0x085C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI96_99;   /* offset: 0x0860 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI100_103;  /* offset: 0x0864 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI104_107;  /* offset: 0x0868 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI108_111;  /* offset: 0x086C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI112_115;  /* offset: 0x0870 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI116_119;  /* offset: 0x0874 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI120_123;  /* offset: 0x0878 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI124_127;  /* offset: 0x087C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI128_131;  /* offset: 0x0880 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI132_135;  /* offset: 0x0884 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI136_139;  /* offset: 0x0888 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI140_143;  /* offset: 0x088C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI144_147;  /* offset: 0x0890 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI148_151;  /* offset: 0x0894 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI152_155;  /* offset: 0x0898 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI156_159;  /* offset: 0x089C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI160_163;  /* offset: 0x08A0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI164_167;  /* offset: 0x08A4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI168_171;  /* offset: 0x08A8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI172_175;  /* offset: 0x08AC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI176_179;  /* offset: 0x08B0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI180_183;  /* offset: 0x08B4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI184_187;  /* offset: 0x08B8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI188_191;  /* offset: 0x08BC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI192_195;  /* offset: 0x08C0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI196_199;  /* offset: 0x08C4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI200_203;  /* offset: 0x08C8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI204_207;  /* offset: 0x08CC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI208_211;  /* offset: 0x08D0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI212_215;  /* offset: 0x08D4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI216_219;  /* offset: 0x08D8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI220_223;  /* offset: 0x08DC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI224_227;  /* offset: 0x08E0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI228_231;  /* offset: 0x08E4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI232_235;  /* offset: 0x08E8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI236_239;  /* offset: 0x08EC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI240_243;  /* offset: 0x08F0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI244_247;  /* offset: 0x08F4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI248_251;  /* offset: 0x08F8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI252_255;  /* offset: 0x08FC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI256_259;  /* offset: 0x0900 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI260_263;  /* offset: 0x0904 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI264_267;  /* offset: 0x0908 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI268_271;  /* offset: 0x090C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI272_275;  /* offset: 0x0910 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI276_279;  /* offset: 0x0914 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI280_283;  /* offset: 0x0918 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI284_287;  /* offset: 0x091C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI288_291;  /* offset: 0x0920 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI292_295;  /* offset: 0x0924 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI296_299;  /* offset: 0x0928 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI300_303;  /* offset: 0x092C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI304_307;  /* offset: 0x0930 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI308_311;  /* offset: 0x0934 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI312_315;  /* offset: 0x0938 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI316_319;  /* offset: 0x093C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI320_323;  /* offset: 0x0940 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI324_327;  /* offset: 0x0944 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI328_331;  /* offset: 0x0948 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI332_335;  /* offset: 0x094C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI336_339;  /* offset: 0x0950 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI340_343;  /* offset: 0x0954 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI344_347;  /* offset: 0x0958 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI348_351;  /* offset: 0x095C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI352_355;  /* offset: 0x0960 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI356_359;  /* offset: 0x0964 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI360_363;  /* offset: 0x0968 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI364_367;  /* offset: 0x096C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI368_371;  /* offset: 0x0970 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI372_375;  /* offset: 0x0974 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI376_379;  /* offset: 0x0978 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI380_383;  /* offset: 0x097C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI384_387;  /* offset: 0x0980 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI388_391;  /* offset: 0x0984 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI392_395;  /* offset: 0x0988 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI396_399;  /* offset: 0x098C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI400_403;  /* offset: 0x0990 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI404_407;  /* offset: 0x0994 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI408_411;  /* offset: 0x0998 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI412_415;  /* offset: 0x099C size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI416_419;  /* offset: 0x09A0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI420_423;  /* offset: 0x09A4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI424_427;  /* offset: 0x09A8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI428_431;  /* offset: 0x09AC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI432_435;  /* offset: 0x09B0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI436_439;  /* offset: 0x09B4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI440_443;  /* offset: 0x09B8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI444_447;  /* offset: 0x09BC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI448_451;  /* offset: 0x09C0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI452_455;  /* offset: 0x09C4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI456_459;  /* offset: 0x09C8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI460_463;  /* offset: 0x09CC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI464_467;  /* offset: 0x09D0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI468_471;  /* offset: 0x09D4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI472_475;  /* offset: 0x09D8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI476_479;  /* offset: 0x09DC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI480_483;  /* offset: 0x09E0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI484_487;  /* offset: 0x09E4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI488_491;  /* offset: 0x09E8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI492_495;  /* offset: 0x09EC size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI496_499;  /* offset: 0x09F0 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI500_503;  /* offset: 0x09F4 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI504_507;  /* offset: 0x09F8 size: 32 bit */
-            SIUL_GPDI_32B_tag GPDI508_511;  /* offset: 0x09FC size: 32 bit */
-         };
-
-         struct {
-                                  /* GPDI - GPIO Pad Data Input Register */
-            SIUL_GPDI_8B_tag GPDI0;        /* offset: 0x0800 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI1;        /* offset: 0x0801 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI2;        /* offset: 0x0802 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI3;        /* offset: 0x0803 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI4;        /* offset: 0x0804 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI5;        /* offset: 0x0805 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI6;        /* offset: 0x0806 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI7;        /* offset: 0x0807 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI8;        /* offset: 0x0808 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI9;        /* offset: 0x0809 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI10;       /* offset: 0x080A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI11;       /* offset: 0x080B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI12;       /* offset: 0x080C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI13;       /* offset: 0x080D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI14;       /* offset: 0x080E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI15;       /* offset: 0x080F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI16;       /* offset: 0x0810 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI17;       /* offset: 0x0811 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI18;       /* offset: 0x0812 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI19;       /* offset: 0x0813 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI20;       /* offset: 0x0814 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI21;       /* offset: 0x0815 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI22;       /* offset: 0x0816 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI23;       /* offset: 0x0817 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI24;       /* offset: 0x0818 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI25;       /* offset: 0x0819 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI26;       /* offset: 0x081A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI27;       /* offset: 0x081B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI28;       /* offset: 0x081C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI29;       /* offset: 0x081D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI30;       /* offset: 0x081E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI31;       /* offset: 0x081F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI32;       /* offset: 0x0820 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI33;       /* offset: 0x0821 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI34;       /* offset: 0x0822 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI35;       /* offset: 0x0823 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI36;       /* offset: 0x0824 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI37;       /* offset: 0x0825 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI38;       /* offset: 0x0826 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI39;       /* offset: 0x0827 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI40;       /* offset: 0x0828 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI41;       /* offset: 0x0829 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI42;       /* offset: 0x082A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI43;       /* offset: 0x082B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI44;       /* offset: 0x082C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI45;       /* offset: 0x082D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI46;       /* offset: 0x082E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI47;       /* offset: 0x082F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI48;       /* offset: 0x0830 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI49;       /* offset: 0x0831 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI50;       /* offset: 0x0832 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI51;       /* offset: 0x0833 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI52;       /* offset: 0x0834 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI53;       /* offset: 0x0835 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI54;       /* offset: 0x0836 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI55;       /* offset: 0x0837 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI56;       /* offset: 0x0838 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI57;       /* offset: 0x0839 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI58;       /* offset: 0x083A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI59;       /* offset: 0x083B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI60;       /* offset: 0x083C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI61;       /* offset: 0x083D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI62;       /* offset: 0x083E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI63;       /* offset: 0x083F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI64;       /* offset: 0x0840 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI65;       /* offset: 0x0841 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI66;       /* offset: 0x0842 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI67;       /* offset: 0x0843 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI68;       /* offset: 0x0844 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI69;       /* offset: 0x0845 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI70;       /* offset: 0x0846 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI71;       /* offset: 0x0847 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI72;       /* offset: 0x0848 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI73;       /* offset: 0x0849 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI74;       /* offset: 0x084A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI75;       /* offset: 0x084B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI76;       /* offset: 0x084C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI77;       /* offset: 0x084D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI78;       /* offset: 0x084E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI79;       /* offset: 0x084F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI80;       /* offset: 0x0850 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI81;       /* offset: 0x0851 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI82;       /* offset: 0x0852 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI83;       /* offset: 0x0853 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI84;       /* offset: 0x0854 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI85;       /* offset: 0x0855 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI86;       /* offset: 0x0856 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI87;       /* offset: 0x0857 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI88;       /* offset: 0x0858 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI89;       /* offset: 0x0859 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI90;       /* offset: 0x085A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI91;       /* offset: 0x085B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI92;       /* offset: 0x085C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI93;       /* offset: 0x085D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI94;       /* offset: 0x085E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI95;       /* offset: 0x085F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI96;       /* offset: 0x0860 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI97;       /* offset: 0x0861 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI98;       /* offset: 0x0862 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI99;       /* offset: 0x0863 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI100;      /* offset: 0x0864 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI101;      /* offset: 0x0865 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI102;      /* offset: 0x0866 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI103;      /* offset: 0x0867 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI104;      /* offset: 0x0868 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI105;      /* offset: 0x0869 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI106;      /* offset: 0x086A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI107;      /* offset: 0x086B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI108;      /* offset: 0x086C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI109;      /* offset: 0x086D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI110;      /* offset: 0x086E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI111;      /* offset: 0x086F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI112;      /* offset: 0x0870 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI113;      /* offset: 0x0871 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI114;      /* offset: 0x0872 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI115;      /* offset: 0x0873 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI116;      /* offset: 0x0874 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI117;      /* offset: 0x0875 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI118;      /* offset: 0x0876 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI119;      /* offset: 0x0877 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI120;      /* offset: 0x0878 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI121;      /* offset: 0x0879 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI122;      /* offset: 0x087A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI123;      /* offset: 0x087B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI124;      /* offset: 0x087C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI125;      /* offset: 0x087D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI126;      /* offset: 0x087E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI127;      /* offset: 0x087F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI128;      /* offset: 0x0880 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI129;      /* offset: 0x0881 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI130;      /* offset: 0x0882 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI131;      /* offset: 0x0883 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI132;      /* offset: 0x0884 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI133;      /* offset: 0x0885 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI134;      /* offset: 0x0886 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI135;      /* offset: 0x0887 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI136;      /* offset: 0x0888 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI137;      /* offset: 0x0889 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI138;      /* offset: 0x088A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI139;      /* offset: 0x088B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI140;      /* offset: 0x088C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI141;      /* offset: 0x088D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI142;      /* offset: 0x088E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI143;      /* offset: 0x088F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI144;      /* offset: 0x0890 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI145;      /* offset: 0x0891 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI146;      /* offset: 0x0892 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI147;      /* offset: 0x0893 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI148;      /* offset: 0x0894 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI149;      /* offset: 0x0895 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI150;      /* offset: 0x0896 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI151;      /* offset: 0x0897 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI152;      /* offset: 0x0898 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI153;      /* offset: 0x0899 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI154;      /* offset: 0x089A size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI155;      /* offset: 0x089B size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI156;      /* offset: 0x089C size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI157;      /* offset: 0x089D size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI158;      /* offset: 0x089E size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI159;      /* offset: 0x089F size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI160;      /* offset: 0x08A0 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI161;      /* offset: 0x08A1 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI162;      /* offset: 0x08A2 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI163;      /* offset: 0x08A3 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI164;      /* offset: 0x08A4 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI165;      /* offset: 0x08A5 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI166;      /* offset: 0x08A6 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI167;      /* offset: 0x08A7 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI168;      /* offset: 0x08A8 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI169;      /* offset: 0x08A9 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI170;      /* offset: 0x08AA size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI171;      /* offset: 0x08AB size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI172;      /* offset: 0x08AC size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI173;      /* offset: 0x08AD size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI174;      /* offset: 0x08AE size: 8 bit */
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-            SIUL_GPDI_8B_tag GPDI417;      /* offset: 0x09A1 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI418;      /* offset: 0x09A2 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI419;      /* offset: 0x09A3 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI420;      /* offset: 0x09A4 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI421;      /* offset: 0x09A5 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI422;      /* offset: 0x09A6 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI423;      /* offset: 0x09A7 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI424;      /* offset: 0x09A8 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI425;      /* offset: 0x09A9 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI426;      /* offset: 0x09AA size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI427;      /* offset: 0x09AB size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI428;      /* offset: 0x09AC size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI429;      /* offset: 0x09AD size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI430;      /* offset: 0x09AE size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI431;      /* offset: 0x09AF size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI432;      /* offset: 0x09B0 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI433;      /* offset: 0x09B1 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI434;      /* offset: 0x09B2 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI435;      /* offset: 0x09B3 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI436;      /* offset: 0x09B4 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI437;      /* offset: 0x09B5 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI438;      /* offset: 0x09B6 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI439;      /* offset: 0x09B7 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI440;      /* offset: 0x09B8 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI441;      /* offset: 0x09B9 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI442;      /* offset: 0x09BA size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI443;      /* offset: 0x09BB size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI444;      /* offset: 0x09BC size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI445;      /* offset: 0x09BD size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI446;      /* offset: 0x09BE size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI447;      /* offset: 0x09BF size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI448;      /* offset: 0x09C0 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI449;      /* offset: 0x09C1 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI450;      /* offset: 0x09C2 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI451;      /* offset: 0x09C3 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI452;      /* offset: 0x09C4 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI453;      /* offset: 0x09C5 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI454;      /* offset: 0x09C6 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI455;      /* offset: 0x09C7 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI456;      /* offset: 0x09C8 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI457;      /* offset: 0x09C9 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI458;      /* offset: 0x09CA size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI459;      /* offset: 0x09CB size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI460;      /* offset: 0x09CC size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI461;      /* offset: 0x09CD size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI462;      /* offset: 0x09CE size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI463;      /* offset: 0x09CF size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI464;      /* offset: 0x09D0 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI465;      /* offset: 0x09D1 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI466;      /* offset: 0x09D2 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI467;      /* offset: 0x09D3 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI468;      /* offset: 0x09D4 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI469;      /* offset: 0x09D5 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI470;      /* offset: 0x09D6 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI471;      /* offset: 0x09D7 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI472;      /* offset: 0x09D8 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI473;      /* offset: 0x09D9 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI474;      /* offset: 0x09DA size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI475;      /* offset: 0x09DB size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI476;      /* offset: 0x09DC size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI477;      /* offset: 0x09DD size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI478;      /* offset: 0x09DE size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI479;      /* offset: 0x09DF size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI480;      /* offset: 0x09E0 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI481;      /* offset: 0x09E1 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI482;      /* offset: 0x09E2 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI483;      /* offset: 0x09E3 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI484;      /* offset: 0x09E4 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI485;      /* offset: 0x09E5 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI486;      /* offset: 0x09E6 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI487;      /* offset: 0x09E7 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI488;      /* offset: 0x09E8 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI489;      /* offset: 0x09E9 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI490;      /* offset: 0x09EA size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI491;      /* offset: 0x09EB size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI492;      /* offset: 0x09EC size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI493;      /* offset: 0x09ED size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI494;      /* offset: 0x09EE size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI495;      /* offset: 0x09EF size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI496;      /* offset: 0x09F0 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI497;      /* offset: 0x09F1 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI498;      /* offset: 0x09F2 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI499;      /* offset: 0x09F3 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI500;      /* offset: 0x09F4 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI501;      /* offset: 0x09F5 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI502;      /* offset: 0x09F6 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI503;      /* offset: 0x09F7 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI504;      /* offset: 0x09F8 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI505;      /* offset: 0x09F9 size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI506;      /* offset: 0x09FA size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI507;      /* offset: 0x09FB size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI508;      /* offset: 0x09FC size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI509;      /* offset: 0x09FD size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI510;      /* offset: 0x09FE size: 8 bit */
-            SIUL_GPDI_8B_tag GPDI511;      /* offset: 0x09FF size: 8 bit */
-         };
-
-      };
-      int8_t SIUL_reserved_0A00_C[512];
-      union {
-                          /* PGPDO - Parallel GPIO Pad Data Out Register */
-         SIUL_PGPDO_16B_tag PGPDO[32];     /* offset: 0x0C00  (0x0002 x 32) */
-
-         struct {
-                          /* PGPDO - Parallel GPIO Pad Data Out Register */
-            SIUL_PGPDO_16B_tag PGPDO0;     /* offset: 0x0C00 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO1;     /* offset: 0x0C02 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO2;     /* offset: 0x0C04 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO3;     /* offset: 0x0C06 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO4;     /* offset: 0x0C08 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO5;     /* offset: 0x0C0A size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO6;     /* offset: 0x0C0C size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO7;     /* offset: 0x0C0E size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO8;     /* offset: 0x0C10 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO9;     /* offset: 0x0C12 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO10;    /* offset: 0x0C14 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO11;    /* offset: 0x0C16 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO12;    /* offset: 0x0C18 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO13;    /* offset: 0x0C1A size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO14;    /* offset: 0x0C1C size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO15;    /* offset: 0x0C1E size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO16;    /* offset: 0x0C20 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO17;    /* offset: 0x0C22 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO18;    /* offset: 0x0C24 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO19;    /* offset: 0x0C26 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO20;    /* offset: 0x0C28 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO21;    /* offset: 0x0C2A size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO22;    /* offset: 0x0C2C size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO23;    /* offset: 0x0C2E size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO24;    /* offset: 0x0C30 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO25;    /* offset: 0x0C32 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO26;    /* offset: 0x0C34 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO27;    /* offset: 0x0C36 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO28;    /* offset: 0x0C38 size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO29;    /* offset: 0x0C3A size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO30;    /* offset: 0x0C3C size: 16 bit */
-            SIUL_PGPDO_16B_tag PGPDO31;    /* offset: 0x0C3E size: 16 bit */
-         };
-
-      };
-      union {
-                           /* PGPDI - Parallel GPIO Pad Data In Register */
-         SIUL_PGPDI_16B_tag PGPDI[32];     /* offset: 0x0C40  (0x0002 x 32) */
-
-         struct {
-                           /* PGPDI - Parallel GPIO Pad Data In Register */
-            SIUL_PGPDI_16B_tag PGPDI0;     /* offset: 0x0C40 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI1;     /* offset: 0x0C42 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI2;     /* offset: 0x0C44 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI3;     /* offset: 0x0C46 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI4;     /* offset: 0x0C48 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI5;     /* offset: 0x0C4A size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI6;     /* offset: 0x0C4C size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI7;     /* offset: 0x0C4E size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI8;     /* offset: 0x0C50 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI9;     /* offset: 0x0C52 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI10;    /* offset: 0x0C54 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI11;    /* offset: 0x0C56 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI12;    /* offset: 0x0C58 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI13;    /* offset: 0x0C5A size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI14;    /* offset: 0x0C5C size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI15;    /* offset: 0x0C5E size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI16;    /* offset: 0x0C60 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI17;    /* offset: 0x0C62 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI18;    /* offset: 0x0C64 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI19;    /* offset: 0x0C66 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI20;    /* offset: 0x0C68 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI21;    /* offset: 0x0C6A size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI22;    /* offset: 0x0C6C size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI23;    /* offset: 0x0C6E size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI24;    /* offset: 0x0C70 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI25;    /* offset: 0x0C72 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI26;    /* offset: 0x0C74 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI27;    /* offset: 0x0C76 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI28;    /* offset: 0x0C78 size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI29;    /* offset: 0x0C7A size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI30;    /* offset: 0x0C7C size: 16 bit */
-            SIUL_PGPDI_16B_tag PGPDI31;    /* offset: 0x0C7E size: 16 bit */
-         };
-
-      };
-      union {
-                  /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
-         SIUL_MPGPDO_32B_tag MPGPDO[32];   /* offset: 0x0C80  (0x0004 x 32) */
-
-         struct {
-                  /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
-            SIUL_MPGPDO_32B_tag MPGPDO0;   /* offset: 0x0C80 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO1;   /* offset: 0x0C84 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO2;   /* offset: 0x0C88 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO3;   /* offset: 0x0C8C size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO4;   /* offset: 0x0C90 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO5;   /* offset: 0x0C94 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO6;   /* offset: 0x0C98 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO7;   /* offset: 0x0C9C size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO8;   /* offset: 0x0CA0 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO9;   /* offset: 0x0CA4 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO10;  /* offset: 0x0CA8 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO11;  /* offset: 0x0CAC size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO12;  /* offset: 0x0CB0 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO13;  /* offset: 0x0CB4 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO14;  /* offset: 0x0CB8 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO15;  /* offset: 0x0CBC size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO16;  /* offset: 0x0CC0 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO17;  /* offset: 0x0CC4 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO18;  /* offset: 0x0CC8 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO19;  /* offset: 0x0CCC size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO20;  /* offset: 0x0CD0 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO21;  /* offset: 0x0CD4 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO22;  /* offset: 0x0CD8 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO23;  /* offset: 0x0CDC size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO24;  /* offset: 0x0CE0 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO25;  /* offset: 0x0CE4 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO26;  /* offset: 0x0CE8 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO27;  /* offset: 0x0CEC size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO28;  /* offset: 0x0CF0 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO29;  /* offset: 0x0CF4 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO30;  /* offset: 0x0CF8 size: 32 bit */
-            SIUL_MPGPDO_32B_tag MPGPDO31;  /* offset: 0x0CFC size: 32 bit */
-         };
-
-      };
-      int8_t SIUL_reserved_0D00_C[768];
-      union {
-                     /* IFMC - Interrupt Filter Maximum Counter Register */
-         SIUL_IFMC_32B_tag IFMC[32];       /* offset: 0x1000  (0x0004 x 32) */
-
-         struct {
-                     /* IFMC - Interrupt Filter Maximum Counter Register */
-            SIUL_IFMC_32B_tag IFMC0;       /* offset: 0x1000 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC1;       /* offset: 0x1004 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC2;       /* offset: 0x1008 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC3;       /* offset: 0x100C size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC4;       /* offset: 0x1010 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC5;       /* offset: 0x1014 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC6;       /* offset: 0x1018 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC7;       /* offset: 0x101C size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC8;       /* offset: 0x1020 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC9;       /* offset: 0x1024 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC10;      /* offset: 0x1028 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC11;      /* offset: 0x102C size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC12;      /* offset: 0x1030 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC13;      /* offset: 0x1034 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC14;      /* offset: 0x1038 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC15;      /* offset: 0x103C size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC16;      /* offset: 0x1040 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC17;      /* offset: 0x1044 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC18;      /* offset: 0x1048 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC19;      /* offset: 0x104C size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC20;      /* offset: 0x1050 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC21;      /* offset: 0x1054 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC22;      /* offset: 0x1058 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC23;      /* offset: 0x105C size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC24;      /* offset: 0x1060 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC25;      /* offset: 0x1064 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC26;      /* offset: 0x1068 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC27;      /* offset: 0x106C size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC28;      /* offset: 0x1070 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC29;      /* offset: 0x1074 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC30;      /* offset: 0x1078 size: 32 bit */
-            SIUL_IFMC_32B_tag IFMC31;      /* offset: 0x107C size: 32 bit */
-         };
-
-      };
-                     /* IFCPR - Inerrupt Filter Clock Prescaler Register */
-      SIUL_IFCPR_32B_tag IFCPR;            /* offset: 0x1080 size: 32 bit */
-   } SIUL_tag;
-
-
-#define SIUL  (*(volatile SIUL_tag *) 0xC3F90000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: WKPU  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* WKPU_NSR - NMI Status Flag Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  NIF0:1;            /* NMI Status Flag 0 */
-         vuint32_t  NOVF0:1;           /* NMI Overrun Status Flag 0 */
-         vuint32_t:6;
-         vuint32_t  NIF1:1;            /* NMI Status Flag 1 */
-         vuint32_t  NOVF1:1;           /* NMI Overrun Status Flag 1 */
-         vuint32_t:6;
-         vuint32_t  NIF2:1;            /* NMI Status Flag 2 */
-         vuint32_t  NOVF2:1;           /* NMI Overrun Status Flag 2 */
-         vuint32_t:6;
-         vuint32_t  NIF3:1;            /* NMI Status Flag 3 */
-         vuint32_t  NOVF3:1;           /* NMI Overrun Status Flag 3 */
-         vuint32_t:6;
-      } B;
-   } WKPU_NSR_32B_tag;
-
-   typedef union {   /* WKPU_NCR - NMI Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  NLOCK0:1;          /* NMI Configuration Lock Register 0 */
-         vuint32_t  NDSS0:2;           /* NMI Desination Source Select 0 */
-         vuint32_t  NWRE0:1;           /* NMI Wakeup Request Enable 0 */
-         vuint32_t:1;
-         vuint32_t  NREE0:1;           /* NMI Rising Edge Events Enable 0 */
-         vuint32_t  NFEE0:1;           /* NMI Falling Edge Events Enable 0 */
-         vuint32_t  NFE0:1;            /* NMI Filter Enable 0 */
-         vuint32_t  NLOCK1:1;          /* NMI Configuration Lock Register 1 */
-         vuint32_t  NDSS1:2;           /* NMI Desination Source Select 1 */
-         vuint32_t  NWRE1:1;           /* NMI Wakeup Request Enable 1 */
-         vuint32_t:1;
-         vuint32_t  NREE1:1;           /* NMI Rising Edge Events Enable 1 */
-         vuint32_t  NFEE1:1;           /* NMI Falling Edge Events Enable 1 */
-         vuint32_t  NFE1:1;            /* NMI Filter Enable 1 */
-         vuint32_t  NLOCK2:1;          /* NMI Configuration Lock Register 2 */
-         vuint32_t  NDSS2:2;           /* NMI Desination Source Select 2 */
-         vuint32_t  NWRE2:1;           /* NMI Wakeup Request Enable 2 */
-         vuint32_t:1;
-         vuint32_t  NREE2:1;           /* NMI Rising Edge Events Enable 2 */
-         vuint32_t  NFEE2:1;           /* NMI Falling Edge Events Enable 2 */
-         vuint32_t  NFE2:1;            /* NMI Filter Enable 2 */
-         vuint32_t  NLOCK3:1;          /* NMI Configuration Lock Register 3 */
-         vuint32_t  NDSS3:2;           /* NMI Desination Source Select 3 */
-         vuint32_t  NWRE3:1;           /* NMI Wakeup Request Enable 3 */
-         vuint32_t:1;
-         vuint32_t  NREE3:1;           /* NMI Rising Edge Events Enable 3 */
-         vuint32_t  NFEE3:1;           /* NMI Falling Edge Events Enable 3 */
-         vuint32_t  NFE3:1;            /* NMI Filter Enable 3 */
-      } B;
-   } WKPU_NCR_32B_tag;
-
-   typedef union {   /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  EIF:32;            /* External Wakeup/Interrupt Status Flag */
-      } B;
-   } WKPU_WISR_32B_tag;
-
-   typedef union {   /* WKPU_IRER - Interrupt Request Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  EIRE:32;           /* Enable External Interrupt Requests */
-      } B;
-   } WKPU_IRER_32B_tag;
-
-   typedef union {   /* WKPU_WRER - Wakeup Request Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  WRE:32;            /* Enable Wakeup requests to the mode entry module */
-      } B;
-   } WKPU_WRER_32B_tag;
-
-   typedef union {   /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  IREE:32;           /* Enable rising-edge events to cause EIF[x] to be set */
-      } B;
-   } WKPU_WIREER_32B_tag;
-
-   typedef union {   /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  IFEE:32;           /* Enable Falling-edge events to cause EIF[x] to be set */
-      } B;
-   } WKPU_WIFEER_32B_tag;
-
-   typedef union {   /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  IFE:32;            /* Enable Digital glitch filter on the interrupt pad input */
-      } B;
-   } WKPU_WIFER_32B_tag;
-
-   typedef union {   /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  IPUE:32;           /* Enable a pullup on the interrupt pad input */
-      } B;
-   } WKPU_WIPUER_32B_tag;
-
-
-
-   typedef struct WKPU_struct_tag { /* start of WKPU_tag */
-                                  /* WKPU_NSR - NMI Status Flag Register */
-      WKPU_NSR_32B_tag NSR;                /* offset: 0x0000 size: 32 bit */
-      int8_t WKPU_reserved_0004[4];
-                                /* WKPU_NCR - NMI Configuration Register */
-      WKPU_NCR_32B_tag NCR;                /* offset: 0x0008 size: 32 bit */
-      int8_t WKPU_reserved_000C[8];
-                    /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
-      WKPU_WISR_32B_tag WISR;              /* offset: 0x0014 size: 32 bit */
-                        /* WKPU_IRER - Interrupt Request Enable Register */
-      WKPU_IRER_32B_tag IRER;              /* offset: 0x0018 size: 32 bit */
-                           /* WKPU_WRER - Wakeup Request Enable Register */
-      WKPU_WRER_32B_tag WRER;              /* offset: 0x001C size: 32 bit */
-      int8_t WKPU_reserved_0020[8];
-     /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
-      WKPU_WIREER_32B_tag WIREER;          /* offset: 0x0028 size: 32 bit */
-    /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
-      WKPU_WIFEER_32B_tag WIFEER;          /* offset: 0x002C size: 32 bit */
-                 /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
-      WKPU_WIFER_32B_tag WIFER;            /* offset: 0x0030 size: 32 bit */
-                /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
-      WKPU_WIPUER_32B_tag WIPUER;          /* offset: 0x0034 size: 32 bit */
-   } WKPU_tag;
-
-
-#define WKPU  (*(volatile WKPU_tag *) 0xC3F94000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: SSCM  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* SSCM_STATUS - System Status Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  LSM:1;             /* Lock Step Mode */
-         vuint16_t:2;
-         vuint16_t  NXEN1:1;           /* Processor 1 Nexus enabled */
-         vuint16_t  NXEN:1;            /* Processor 0 Nexus enabled */
-         vuint16_t  PUB:1;             /* Public Serial Access Status */
-         vuint16_t  SEC:1;             /* Security Status */
-         vuint16_t:1;
-         vuint16_t  BMODE:3;           /* Device Boot Mode */
-#ifndef USE_FIELD_ALIASES_SSCM
-         vuint16_t  VLE:1;             /* Variable Length Instruction Mode */
-#else
-         vuint16_t  DMID:1;              /* deprecated name - please avoid */
-#endif
-         vuint16_t  ABD:1;             /* Autobaud detection */
-         vuint16_t:3;
-      } B;
-   } SSCM_STATUS_16B_tag;
-
-   typedef union {   /* SSCM_MEMCONFIG - System Memory Configuration Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  JPIN:10;           /* JTAG Part ID Number */
-         vuint16_t  IVLD:1;            /* Instruction Flash Valid */
-         vuint16_t  MREV:4;            /* Minor Mask Revision */
-         vuint16_t  DVLD:1;            /* Data Flash Valid */
-      } B;
-   } SSCM_MEMCONFIG_16B_tag;
-
-   typedef union {   /* SSCM_ERROR - Error Configuration */
-      vuint16_t R;
-      struct {
-         vuint16_t:14;
-         vuint16_t  PAE:1;             /* Peripheral Bus Abort Enable */
-         vuint16_t  RAE:1;             /* Register Bus Abort Enable */
-      } B;
-   } SSCM_ERROR_16B_tag;
-
-   typedef union {   /* SSCM_DEBUGPORT - Debug Status Port Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:13;
-         vuint16_t  DEBUG_MODE:3;      /* Debug Status Port Mode */
-      } B;
-   } SSCM_DEBUGPORT_16B_tag;
-
-   typedef union {   /* SSCM_PWCMPH - Password Comparison Register High */
-      vuint32_t R;
-      struct {
-         vuint32_t  PWD_HI:32;         /* Password High */
-      } B;
-   } SSCM_PWCMPH_32B_tag;
-
-   typedef union {   /* SSCM_PWCMPL - Password Comparison Register Low */
-      vuint32_t R;
-      struct {
-         vuint32_t  PWD_LO:32;         /* Password Low */
-      } B;
-   } SSCM_PWCMPL_32B_tag;
-
-   typedef union {   /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  P2BOOT:30;         /* boot location 2nd processor */
-         vuint32_t  DVLE:1;            /* VLE mode for 2nd processor */
-         vuint32_t:1;
-      } B;
-   } SSCM_DPMBOOT_32B_tag;
-
-   typedef union {   /* SSCM_DPMKEY - Boot Key Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  KEY:32;            /* Boot Control Key */
-      } B;
-   } SSCM_DPMKEY_32B_tag;
-
-   typedef union {   /* SSCM_UOPS - User Option Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  UOPT:32;           /* User Option Bits */
-      } B;
-   } SSCM_UOPS_32B_tag;
-
-   typedef union {   /* SSCM_SCTR - SSCM Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:29;
-         vuint32_t  TFE:1;             /* Test Flash Enable */
-         vuint32_t  DSL:1;             /* Disable Software-Controlled MBIST */
-         vuint32_t  DSM:1;             /* Disable Software-Controlled LBIST */
-      } B;
-   } SSCM_SCTR_32B_tag;
-
-   typedef union {   /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  TINFO0:32;         /* General purpose TestFlash word 0 */
-      } B;
-   } SSCM_TF_INFO0_32B_tag;
-
-   typedef union {   /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  TINFO1:32;         /* General purpose TestFlash word 1 */
-      } B;
-   } SSCM_TF_INFO1_32B_tag;
-
-   typedef union {   /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  TINFO2:32;         /* General purpose TestFlash word 2 */
-      } B;
-   } SSCM_TF_INFO2_32B_tag;
-
-   typedef union {   /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  TINFO3:32;         /* General purpose TestFlash word */
-      } B;
-   } SSCM_TF_INFO3_32B_tag;
-
-
-
-   typedef struct SSCM_struct_tag { /* start of SSCM_tag */
-                                 /* SSCM_STATUS - System Status Register */
-      SSCM_STATUS_16B_tag STATUS;          /* offset: 0x0000 size: 16 bit */
-                /* SSCM_MEMCONFIG - System Memory Configuration Register */
-      SSCM_MEMCONFIG_16B_tag MEMCONFIG;    /* offset: 0x0002 size: 16 bit */
-      int8_t SSCM_reserved_0004[2];
-                                     /* SSCM_ERROR - Error Configuration */
-      SSCM_ERROR_16B_tag ERROR;            /* offset: 0x0006 size: 16 bit */
-                          /* SSCM_DEBUGPORT - Debug Status Port Register */
-      SSCM_DEBUGPORT_16B_tag DEBUGPORT;    /* offset: 0x0008 size: 16 bit */
-      int8_t SSCM_reserved_000A[2];
-                      /* SSCM_PWCMPH - Password Comparison Register High */
-      SSCM_PWCMPH_32B_tag PWCMPH;          /* offset: 0x000C size: 32 bit */
-                       /* SSCM_PWCMPL - Password Comparison Register Low */
-      SSCM_PWCMPL_32B_tag PWCMPL;          /* offset: 0x0010 size: 32 bit */
-      int8_t SSCM_reserved_0014[4];
-                      /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
-      SSCM_DPMBOOT_32B_tag DPMBOOT;        /* offset: 0x0018 size: 32 bit */
-                                      /* SSCM_DPMKEY - Boot Key Register */
-      SSCM_DPMKEY_32B_tag DPMKEY;          /* offset: 0x001C size: 32 bit */
-                              /* SSCM_UOPS - User Option Status Register */
-      SSCM_UOPS_32B_tag UOPS;              /* offset: 0x0020 size: 32 bit */
-                                    /* SSCM_SCTR - SSCM Control Register */
-      SSCM_SCTR_32B_tag SCTR;              /* offset: 0x0024 size: 32 bit */
-                     /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
-      SSCM_TF_INFO0_32B_tag TF_INFO0;      /* offset: 0x0028 size: 32 bit */
-                     /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
-      SSCM_TF_INFO1_32B_tag TF_INFO1;      /* offset: 0x002C size: 32 bit */
-                     /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
-      SSCM_TF_INFO2_32B_tag TF_INFO2;      /* offset: 0x0030 size: 32 bit */
-                     /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
-      SSCM_TF_INFO3_32B_tag TF_INFO3;      /* offset: 0x0034 size: 32 bit */
-   } SSCM_tag;
-
-
-#define SSCM  (*(volatile SSCM_tag *) 0xC3FD8000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: ME  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* ME_GS - Global Status Register */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  S_CURRENT_MODE:4;   /* Current device mode status */
-#else
-         vuint32_t  S_CURRENTMODE:4;     /* deprecated name - please avoid */
-#endif
-         vuint32_t  S_MTRANS:1;        /* Mode transition status */
-         vuint32_t:3;
-         vuint32_t  S_PDO:1;           /* Output power-down status */
-         vuint32_t:2;
-         vuint32_t  S_MVR:1;           /* Main voltage regulator status */
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  S_FLA:2;           /* Flash availability status */
-#else
-         vuint32_t  S_CFLA:2;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:8;
-         vuint32_t  S_PLL1:1;          /* Secondary PLL status */
-         vuint32_t  S_PLL0:1;          /* System PLL status */
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  S_XOSC:1;          /* System crystal oscillator status */
-#else
-         vuint32_t  S_OSC:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  S_IRCOSC:1;        /* System RC oscillator status */
-#else
-         vuint32_t  S_RC:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t  S_SYSCLK:4;        /* System clock switch status */
-      } B;
-   } ME_GS_32B_tag;
-
-   typedef union {   /* ME_MCTL - Mode Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  TARGET_MODE:4;     /* Target device mode */
-         vuint32_t:12;
-         vuint32_t  KEY:16;            /* Control key */
-      } B;
-   } ME_MCTL_32B_tag;
-
-   typedef union {   /* ME_MEN - Mode Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:21;
-         vuint32_t  STOP0:1;           /* STOP0 mode enable */
-         vuint32_t:1;
-         vuint32_t  HALT0:1;           /* HALT0 mode enable */
-         vuint32_t  RUN3:1;            /* RUN3 mode enable */
-         vuint32_t  RUN2:1;            /* RUN2 mode enable */
-         vuint32_t  RUN1:1;            /* RUN1 mode enable */
-         vuint32_t  RUN0:1;            /* RUN0 mode enable */
-         vuint32_t  DRUN:1;            /* DRUN mode enable */
-         vuint32_t  SAFE:1;            /* SAFE mode enable */
-         vuint32_t:1;
-         vuint32_t  RESET:1;           /* RESET mode enable */
-      } B;
-   } ME_MEN_32B_tag;
-
-   typedef union {   /* ME_IS - Interrupt Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  I_ICONF:1;         /* Invalid mode config interrupt */
-#else
-         vuint32_t  I_CONF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  I_IMODE:1;         /* Invalid mode interrupt */
-#else
-         vuint32_t  I_MODE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  I_SAFE:1;          /* SAFE mode interrupt */
-#else
-         vuint32_t  I_AFE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  I_MTC:1;           /* Mode transition complete interrupt */
-#else
-         vuint32_t  I_TC:1;              /* deprecated name - please avoid */
-#endif
-      } B;
-   } ME_IS_32B_tag;
-
-   typedef union {   /* ME_IM - Interrupt Mask Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  M_ICONF:1;         /* Invalid mode config interrupt mask */
-#else
-         vuint32_t  M_CONF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  M_IMODE:1;         /* Invalid mode interrupt mask */
-#else
-         vuint32_t  M_MODE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  M_SAFE:1;          /* SAFE mode interrupt mask */
-#else
-         vuint32_t  M_AFE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  M_MTC:1;           /* Mode transition complete interrupt mask */
-#else
-         vuint32_t  M_TC:1;              /* deprecated name - please avoid */
-#endif
-      } B;
-   } ME_IM_32B_tag;
-
-   typedef union {   /* ME_IMTS - Invalid Mode Transition Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:27;
-         vuint32_t  S_MTI:1;           /* Mode Transition Illegal status */
-         vuint32_t  S_MRI:1;           /* Mode Request Illegal status */
-         vuint32_t  S_DMA:1;           /* Disabled Mode Access status */
-         vuint32_t  S_NMA:1;           /* Non-existing Mode Access status */
-         vuint32_t  S_SEA:1;           /* Safe Event Active status */
-      } B;
-   } ME_IMTS_32B_tag;
-
-   typedef union {   /* ME_DMTS - Debug Mode Transition Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  PREVIOUS_MODE:4;   /* Previous Device Mode */
-         vuint32_t:4;
-         vuint32_t  MPH_BUSY:1;        /* MC_ME/MC_PCU Handshake Busy Indicator */
-         vuint32_t:2;
-         vuint32_t  PMC_PROG:1;        /* MC_PCU Mode Change in Process Indicator */
-         vuint32_t  CORE_DBG:1;        /* Processor is in Debug Mode Indicator */
-         vuint32_t:2;
-         vuint32_t  SMR:1;             /* SAFE Mode Request */
-         vuint32_t:1;
-         vuint32_t  VREG_CSRC_SC:1;    /* Main VREG Clock Source State Change Indicator */
-         vuint32_t  CSRC_CSRC_SC:1;    /* Other Clock Source State Change Indicator */
-         vuint32_t  IRCOSC_SC:1;       /* IRCOSC State Change Indicator */
-         vuint32_t  SCSRC_SC:1;        /* Secondary System Clock Sources State Change Indicator */
-         vuint32_t  SYSCLK_SW:1;       /* System Clock Switching pending Status Indicator */
-         vuint32_t:1;
-         vuint32_t  FLASH_SC:1;        /* FLASH State Change Indicator */
-         vuint32_t  CDP_PRPH_0_143:1;   /* Clock Disable Process Pending Status for Periph. 0-143 */
-         vuint32_t:4;
-         vuint32_t  CDP_PRPH_64_95:1;   /* Clock Disable Process Pending Status for Periph. 64-95 */
-         vuint32_t  CDP_PRPH_32_63:1;   /* Clock Disable Process Pending Status for Periph. 32-63 */
-         vuint32_t  CDP_PRPH_0_31:1;   /* Clock Disable Process Pending Status for Periph. 0-31 */
-      } B;
-   } ME_DMTS_32B_tag;
-
-   typedef union {   /* ME_RESET_MC - RESET Mode Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:8;
-         vuint32_t  PDO:1;             /* IOs output power-down control */
-         vuint32_t:2;
-         vuint32_t  MVRON:1;           /* Main voltage regulator control */
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  FLAON:2;           /* Code flash power-down control */
-#else
-         vuint32_t  CFLAON:2;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:8;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL1ON:1;          /* Secondary system clock source [8..0] control */
-#else
-         vuint32_t  PLL2ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL0ON:1;          /* System PLL control */
-#else
-         vuint32_t  PLL1ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  XOSCON:1;          /* System crystal oscillator control */
-#else
-         vuint32_t  XOSC0ON:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  IRCOSCON:1;        /* System RC oscillator control */
-#else
-         vuint32_t  IRCON:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t  SYSCLK:4;          /* System clock switch control */
-      } B;
-   } ME_RESET_MC_32B_tag;
-
-   typedef union {   /* ME_SAFE_MC - Mode Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:8;
-         vuint32_t  PDO:1;             /* IOs output power-down control */
-         vuint32_t:2;
-         vuint32_t  MVRON:1;           /* Main voltage regulator control */
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  FLAON:2;           /* Code flash power-down control */
-#else
-         vuint32_t  CFLAON:2;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:8;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL1ON:1;          /* Secondary system clock source [8..0] control */
-#else
-         vuint32_t  PLL2ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL0ON:1;          /* System PLL control */
-#else
-         vuint32_t  PLL1ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  XOSCON:1;          /* System crystal oscillator control */
-#else
-         vuint32_t  XOSC0ON:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  IRCOSCON:1;        /* System RC oscillator control */
-#else
-         vuint32_t  IRCON:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t  SYSCLK:4;          /* System clock switch control */
-      } B;
-   } ME_SAFE_MC_32B_tag;
-
-   typedef union {   /* ME_DRUN_MC - DRUN Mode Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:8;
-         vuint32_t  PDO:1;             /* IOs output power-down control */
-         vuint32_t:2;
-         vuint32_t  MVRON:1;           /* Main voltage regulator control */
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  FLAON:2;           /* Code flash power-down control */
-#else
-         vuint32_t  CFLAON:2;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:8;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL1ON:1;          /* Secondary system clock source [8..0] control */
-#else
-         vuint32_t  PLL2ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL0ON:1;          /* System PLL control */
-#else
-         vuint32_t  PLL1ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  XOSCON:1;          /* System crystal oscillator control */
-#else
-         vuint32_t  XOSC0ON:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  IRCOSCON:1;        /* System RC oscillator control */
-#else
-         vuint32_t  IRCON:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t  SYSCLK:4;          /* System clock switch control */
-      } B;
-   } ME_DRUN_MC_32B_tag;
-
-
-   /* Register layout for all registers RUN_MC... */
-
-   typedef union {   /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t:8;
-         vuint32_t  PDO:1;             /* IOs output power-down control */
-         vuint32_t:2;
-         vuint32_t  MVRON:1;           /* Main voltage regulator control */
-         vuint32_t:2;
-         vuint32_t  FLAON:2;           /* Code flash power-down control */
-         vuint32_t:8;
-         vuint32_t  PLL1ON:1;          /* Secondary system clock source [8..0] control */
-         vuint32_t  PLL0ON:1;          /* System PLL control */
-         vuint32_t  XOSCON:1;          /* System crystal oscillator control */
-         vuint32_t  IRCOSCON:1;        /* System RC oscillator control */
-         vuint32_t  SYSCLK:4;          /* System clock switch control */
-      } B;
-   } ME_RUN_MC_32B_tag;
-
-   typedef union {   /* ME_HALT0_MC - HALT0 Mode Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:8;
-         vuint32_t  PDO:1;             /* IOs output power-down control */
-         vuint32_t:2;
-         vuint32_t  MVRON:1;           /* Main voltage regulator control */
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  FLAON:2;           /* Code flash power-down control */
-#else
-         vuint32_t  CFLAON:2;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:8;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL1ON:1;          /* Secondary system clock source [8..0] control */
-#else
-         vuint32_t  PLL2ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL0ON:1;          /* System PLL control */
-#else
-         vuint32_t  PLL1ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  XOSCON:1;          /* System crystal oscillator control */
-#else
-         vuint32_t  XOSC0ON:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  IRCOSCON:1;        /* System RC oscillator control */
-#else
-         vuint32_t  IRCON:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t  SYSCLK:4;          /* System clock switch control */
-      } B;
-   } ME_HALT0_MC_32B_tag;
-
-   typedef union {   /* ME_STOP0_MC - STOP0 Mode Configration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:8;
-         vuint32_t  PDO:1;             /* IOs output power-down control */
-         vuint32_t:2;
-         vuint32_t  MVRON:1;           /* Main voltage regulator control */
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  FLAON:2;           /* Code flash power-down control */
-#else
-         vuint32_t  CFLAON:2;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:8;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL1ON:1;          /* Secondary system clock source [8..0] control */
-#else
-         vuint32_t  PLL2ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL0ON:1;          /* System PLL control */
-#else
-         vuint32_t  PLL1ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  XOSCON:1;          /* System crystal oscillator control */
-#else
-         vuint32_t  XOSC0ON:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  IRCOSCON:1;        /* System RC oscillator control */
-#else
-         vuint32_t  IRCON:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t  SYSCLK:4;          /* System clock switch control */
-      } B;
-   } ME_STOP0_MC_32B_tag;
-
-   typedef union {   /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:8;
-         vuint32_t  PDO:1;             /* IOs output power-down control */
-         vuint32_t:2;
-         vuint32_t  MVRON:1;           /* Main voltage regulator control */
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  FLAON:2;           /* Code flash power-down control */
-#else
-         vuint32_t  CFLAON:2;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:8;
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL1ON:1;          /* Secondary system clock source [8..0] control */
-#else
-         vuint32_t  PLL2ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  PLL0ON:1;          /* System PLL control */
-#else
-         vuint32_t  PLL1ON:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  XOSCON:1;          /* System crystal oscillator control */
-#else
-         vuint32_t  XOSC0ON:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ME
-         vuint32_t  IRCOSCON:1;        /* System RC oscillator control */
-#else
-         vuint32_t  IRCON:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t  SYSCLK:4;          /* System clock switch control */
-      } B;
-   } ME_STANDBY0_MC_32B_tag;
-
-   typedef union {   /* ME_PS0 - Peripheral Status Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t:7;
-         vuint32_t  S_FLEXRAY:1;       /* FlexRay status */
-         vuint32_t:6;
-         vuint32_t  S_FLEXCAN1:1;      /* FlexCAN1 status */
-         vuint32_t  S_FLEXCAN0:1;      /* FlexCAN0 status */
-         vuint32_t:9;
-         vuint32_t  S_DSPI2:1;         /* DSPI2 status */
-         vuint32_t  S_DSPI1:1;         /* DSPI1 status */
-         vuint32_t  S_DSPI0:1;         /* DSPI0 status */
-         vuint32_t:4;
-      } B;
-   } ME_PS0_32B_tag;
-
-   typedef union {   /* ME_PS1 - Peripheral Status Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t:1;
-         vuint32_t  S_SWG:1;           /* SWG status */
-         vuint32_t:3;
-         vuint32_t  S_CRC:1;           /* CRC status */
-         vuint32_t:8;
-         vuint32_t  S_LIN_FLEX1:1;     /* LinFlex1 status */
-         vuint32_t  S_LIN_FLEX0:1;     /* LinFlex0 status */
-         vuint32_t:5;
-         vuint32_t  S_FLEXPWM1:1;      /* FlexPWM1 status */
-         vuint32_t  S_FLEXPWM0:1;      /* FlexPWM0 status */
-         vuint32_t  S_ETIMER2:1;       /* eTimer2 status */
-         vuint32_t  S_ETIMER1:1;       /* eTimer1 status */
-         vuint32_t  S_ETIMER0:1;       /* eTimer0 status */
-         vuint32_t:2;
-         vuint32_t  S_CTU:1;           /* CTU status */
-         vuint32_t:1;
-         vuint32_t  S_ADC1:1;          /* ADC1 status */
-         vuint32_t  S_ADC0:1;          /* ADC0 status */
-      } B;
-   } ME_PS1_32B_tag;
-
-   typedef union {   /* ME_PS2 - Peripheral Status Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t:3;
-         vuint32_t  S_PIT:1;           /* PIT status */
-         vuint32_t:28;
-      } B;
-   } ME_PS2_32B_tag;
-
-
-   /* Register layout for all registers RUN_PC... */
-
-   typedef union {   /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t:24;
-         vuint32_t  RUN3:1;            /* Peripheral control during RUN3 */
-         vuint32_t  RUN2:1;            /* Peripheral control during RUN2 */
-         vuint32_t  RUN1:1;            /* Peripheral control during RUN1 */
-         vuint32_t  RUN0:1;            /* Peripheral control during RUN0 */
-         vuint32_t  DRUN:1;            /* Peripheral control during DRUN */
-         vuint32_t  SAFE:1;            /* Peripheral control during SAFE */
-         vuint32_t  TEST:1;            /* Peripheral control during TEST */
-         vuint32_t  RESET:1;           /* Peripheral control during RESET */
-      } B;
-   } ME_RUN_PC_32B_tag;
-
-
-   /* Register layout for all registers LP_PC... */
-
-   typedef union {   /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t:21;
-         vuint32_t  STOP0:1;           /* Peripheral control during STOP0 */
-         vuint32_t:1;
-         vuint32_t  HALT0:1;           /* Peripheral control during HALT0 */
-         vuint32_t:8;
-      } B;
-   } ME_LP_PC_32B_tag;
-
-
-   /* Register layout for all registers PCTL... */
-
-   typedef union {   /* ME_PCTL[0...143] - Peripheral Control Registers */
-      vuint8_t R;
-      struct {
-         vuint8_t:1;
-         vuint8_t   DBG_F:1;           /* Peripheral control in debug mode */
-         vuint8_t   LP_CFG:3;          /* Peripheral configuration select for non-RUN modes */
-         vuint8_t   RUN_CFG:3;         /* Peripheral configuration select for RUN modes */
-      } B;
-   } ME_PCTL_8B_tag;
-
-
-
-
-   /* Register layout for generated register(s) PS... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } ME_PS_32B_tag;
-
-
-
-
-
-
-   typedef struct ME_struct_tag { /* start of ME_tag */
-                                       /* ME_GS - Global Status Register */
-      ME_GS_32B_tag GS;                    /* offset: 0x0000 size: 32 bit */
-                                      /* ME_MCTL - Mode Control Register */
-      ME_MCTL_32B_tag MCTL;                /* offset: 0x0004 size: 32 bit */
-      union {
-         ME_MEN_32B_tag MER;               /* deprecated - please avoid */
-
-                                        /* ME_MEN - Mode Enable Register */
-         ME_MEN_32B_tag MEN;               /* offset: 0x0008 size: 32 bit */
-
-      };
-                                    /* ME_IS - Interrupt Status Register */
-      ME_IS_32B_tag IS;                    /* offset: 0x000C size: 32 bit */
-                                      /* ME_IM - Interrupt Mask Register */
-      ME_IM_32B_tag IM;                    /* offset: 0x0010 size: 32 bit */
-                    /* ME_IMTS - Invalid Mode Transition Status Register */
-      ME_IMTS_32B_tag IMTS;                /* offset: 0x0014 size: 32 bit */
-                      /* ME_DMTS - Debug Mode Transition Status Register */
-      ME_DMTS_32B_tag DMTS;                /* offset: 0x0018 size: 32 bit */
-      int8_t ME_reserved_001C_C[4];
-      union {
-                      /* ME_RESET_MC - RESET Mode Configuration Register */
-         ME_RESET_MC_32B_tag RESET_MC;     /* offset: 0x0020 size: 32 bit */
-
-         ME_RESET_MC_32B_tag RESET;        /* deprecated - please avoid */
-
-      };
-      int8_t ME_reserved_0024_C[4];
-      union {
-                             /* ME_SAFE_MC - Mode Configuration Register */
-         ME_SAFE_MC_32B_tag SAFE_MC;       /* offset: 0x0028 size: 32 bit */
-
-         ME_SAFE_MC_32B_tag SAFE;          /* deprecated - please avoid */
-
-      };
-      union {
-                        /* ME_DRUN_MC - DRUN Mode Configuration Register */
-         ME_DRUN_MC_32B_tag DRUN_MC;       /* offset: 0x002C size: 32 bit */
-
-         ME_DRUN_MC_32B_tag DRUN;          /* deprecated - please avoid */
-
-      };
-      union {
-             /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
-         ME_RUN_MC_32B_tag RUN_MC[4];      /* offset: 0x0030  (0x0004 x 4) */
-
-         ME_RUN_MC_32B_tag RUN[4];            /* offset: 0x0030  (0x0004 x 4) */ /* deprecated - please avoid */
-
-         struct {
-             /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
-            ME_RUN_MC_32B_tag RUN0_MC;     /* offset: 0x0030 size: 32 bit */
-            ME_RUN_MC_32B_tag RUN1_MC;     /* offset: 0x0034 size: 32 bit */
-            ME_RUN_MC_32B_tag RUN2_MC;     /* offset: 0x0038 size: 32 bit */
-            ME_RUN_MC_32B_tag RUN3_MC;     /* offset: 0x003C size: 32 bit */
-         };
-
-      };
-      union {
-                      /* ME_HALT0_MC - HALT0 Mode Configuration Register */
-         ME_HALT0_MC_32B_tag HALT0_MC;     /* offset: 0x0040 size: 32 bit */
-
-         ME_HALT0_MC_32B_tag HALT0;        /* deprecated - please avoid */
-
-      };
-      int8_t ME_reserved_0044_C[4];
-      union {
-                       /* ME_STOP0_MC - STOP0 Mode Configration Register */
-         ME_STOP0_MC_32B_tag STOP0_MC;     /* offset: 0x0048 size: 32 bit */
-
-         ME_STOP0_MC_32B_tag STOP0;        /* deprecated - please avoid */
-
-      };
-      int8_t ME_reserved_004C_C[8];
-      union {
-                 /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
-         ME_STANDBY0_MC_32B_tag STANDBY0_MC;  /* offset: 0x0054 size: 32 bit */
-
-         ME_STANDBY0_MC_32B_tag STANDBY0;  /* deprecated - please avoid */
-
-      };
-      int8_t ME_reserved_0058_C[8];
-      union {
-         ME_PS_32B_tag PS[3];              /* offset: 0x0060  (0x0004 x 3) */
-
-         struct {
-                                /* ME_PS0 - Peripheral Status Register 0 */
-            ME_PS0_32B_tag PS0;            /* offset: 0x0060 size: 32 bit */
-                                /* ME_PS1 - Peripheral Status Register 1 */
-            ME_PS1_32B_tag PS1;            /* offset: 0x0064 size: 32 bit */
-                                /* ME_PS2 - Peripheral Status Register 2 */
-            ME_PS2_32B_tag PS2;            /* offset: 0x0068 size: 32 bit */
-         };
-
-      };
-      int8_t ME_reserved_006C_C[20];
-      union {
-         ME_RUN_PC_32B_tag RUNPC[8];       /* offset: 0x0080  (0x0004 x 8) */
-
-            /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
-         ME_RUN_PC_32B_tag RUN_PC[8];      /* offset: 0x0080  (0x0004 x 8) */
-
-         struct {
-            /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
-            ME_RUN_PC_32B_tag RUN_PC0;     /* offset: 0x0080 size: 32 bit */
-            ME_RUN_PC_32B_tag RUN_PC1;     /* offset: 0x0084 size: 32 bit */
-            ME_RUN_PC_32B_tag RUN_PC2;     /* offset: 0x0088 size: 32 bit */
-            ME_RUN_PC_32B_tag RUN_PC3;     /* offset: 0x008C size: 32 bit */
-            ME_RUN_PC_32B_tag RUN_PC4;     /* offset: 0x0090 size: 32 bit */
-            ME_RUN_PC_32B_tag RUN_PC5;     /* offset: 0x0094 size: 32 bit */
-            ME_RUN_PC_32B_tag RUN_PC6;     /* offset: 0x0098 size: 32 bit */
-            ME_RUN_PC_32B_tag RUN_PC7;     /* offset: 0x009C size: 32 bit */
-         };
-
-      };
-      union {
-         ME_LP_PC_32B_tag LPPC[8];          /* offset: 0x00A0  (0x0004 x 8) */
-
-       /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
-         ME_LP_PC_32B_tag LP_PC[8];        /* offset: 0x00A0  (0x0004 x 8) */
-
-         struct {
-       /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
-            ME_LP_PC_32B_tag LP_PC0;       /* offset: 0x00A0 size: 32 bit */
-            ME_LP_PC_32B_tag LP_PC1;       /* offset: 0x00A4 size: 32 bit */
-            ME_LP_PC_32B_tag LP_PC2;       /* offset: 0x00A8 size: 32 bit */
-            ME_LP_PC_32B_tag LP_PC3;       /* offset: 0x00AC size: 32 bit */
-            ME_LP_PC_32B_tag LP_PC4;       /* offset: 0x00B0 size: 32 bit */
-            ME_LP_PC_32B_tag LP_PC5;       /* offset: 0x00B4 size: 32 bit */
-            ME_LP_PC_32B_tag LP_PC6;       /* offset: 0x00B8 size: 32 bit */
-            ME_LP_PC_32B_tag LP_PC7;       /* offset: 0x00BC size: 32 bit */
-         };
-
-      };
-      union {
-                      /* ME_PCTL[0...143] - Peripheral Control Registers */
-         ME_PCTL_8B_tag PCTL[144];         /* offset: 0x00C0  (0x0001 x 144) */
-
-         struct {
-                      /* ME_PCTL[0...143] - Peripheral Control Registers */
-            ME_PCTL_8B_tag PCTL0;          /* offset: 0x00C0 size: 8 bit */
-            ME_PCTL_8B_tag PCTL1;          /* offset: 0x00C1 size: 8 bit */
-            ME_PCTL_8B_tag PCTL2;          /* offset: 0x00C2 size: 8 bit */
-            ME_PCTL_8B_tag PCTL3;          /* offset: 0x00C3 size: 8 bit */
-            ME_PCTL_8B_tag PCTL4;          /* offset: 0x00C4 size: 8 bit */
-            ME_PCTL_8B_tag PCTL5;          /* offset: 0x00C5 size: 8 bit */
-            ME_PCTL_8B_tag PCTL6;          /* offset: 0x00C6 size: 8 bit */
-            ME_PCTL_8B_tag PCTL7;          /* offset: 0x00C7 size: 8 bit */
-            ME_PCTL_8B_tag PCTL8;          /* offset: 0x00C8 size: 8 bit */
-            ME_PCTL_8B_tag PCTL9;          /* offset: 0x00C9 size: 8 bit */
-            ME_PCTL_8B_tag PCTL10;         /* offset: 0x00CA size: 8 bit */
-            ME_PCTL_8B_tag PCTL11;         /* offset: 0x00CB size: 8 bit */
-            ME_PCTL_8B_tag PCTL12;         /* offset: 0x00CC size: 8 bit */
-            ME_PCTL_8B_tag PCTL13;         /* offset: 0x00CD size: 8 bit */
-            ME_PCTL_8B_tag PCTL14;         /* offset: 0x00CE size: 8 bit */
-            ME_PCTL_8B_tag PCTL15;         /* offset: 0x00CF size: 8 bit */
-            ME_PCTL_8B_tag PCTL16;         /* offset: 0x00D0 size: 8 bit */
-            ME_PCTL_8B_tag PCTL17;         /* offset: 0x00D1 size: 8 bit */
-            ME_PCTL_8B_tag PCTL18;         /* offset: 0x00D2 size: 8 bit */
-            ME_PCTL_8B_tag PCTL19;         /* offset: 0x00D3 size: 8 bit */
-            ME_PCTL_8B_tag PCTL20;         /* offset: 0x00D4 size: 8 bit */
-            ME_PCTL_8B_tag PCTL21;         /* offset: 0x00D5 size: 8 bit */
-            ME_PCTL_8B_tag PCTL22;         /* offset: 0x00D6 size: 8 bit */
-            ME_PCTL_8B_tag PCTL23;         /* offset: 0x00D7 size: 8 bit */
-            ME_PCTL_8B_tag PCTL24;         /* offset: 0x00D8 size: 8 bit */
-            ME_PCTL_8B_tag PCTL25;         /* offset: 0x00D9 size: 8 bit */
-            ME_PCTL_8B_tag PCTL26;         /* offset: 0x00DA size: 8 bit */
-            ME_PCTL_8B_tag PCTL27;         /* offset: 0x00DB size: 8 bit */
-            ME_PCTL_8B_tag PCTL28;         /* offset: 0x00DC size: 8 bit */
-            ME_PCTL_8B_tag PCTL29;         /* offset: 0x00DD size: 8 bit */
-            ME_PCTL_8B_tag PCTL30;         /* offset: 0x00DE size: 8 bit */
-            ME_PCTL_8B_tag PCTL31;         /* offset: 0x00DF size: 8 bit */
-            ME_PCTL_8B_tag PCTL32;         /* offset: 0x00E0 size: 8 bit */
-            ME_PCTL_8B_tag PCTL33;         /* offset: 0x00E1 size: 8 bit */
-            ME_PCTL_8B_tag PCTL34;         /* offset: 0x00E2 size: 8 bit */
-            ME_PCTL_8B_tag PCTL35;         /* offset: 0x00E3 size: 8 bit */
-            ME_PCTL_8B_tag PCTL36;         /* offset: 0x00E4 size: 8 bit */
-            ME_PCTL_8B_tag PCTL37;         /* offset: 0x00E5 size: 8 bit */
-            ME_PCTL_8B_tag PCTL38;         /* offset: 0x00E6 size: 8 bit */
-            ME_PCTL_8B_tag PCTL39;         /* offset: 0x00E7 size: 8 bit */
-            ME_PCTL_8B_tag PCTL40;         /* offset: 0x00E8 size: 8 bit */
-            ME_PCTL_8B_tag PCTL41;         /* offset: 0x00E9 size: 8 bit */
-            ME_PCTL_8B_tag PCTL42;         /* offset: 0x00EA size: 8 bit */
-            ME_PCTL_8B_tag PCTL43;         /* offset: 0x00EB size: 8 bit */
-            ME_PCTL_8B_tag PCTL44;         /* offset: 0x00EC size: 8 bit */
-            ME_PCTL_8B_tag PCTL45;         /* offset: 0x00ED size: 8 bit */
-            ME_PCTL_8B_tag PCTL46;         /* offset: 0x00EE size: 8 bit */
-            ME_PCTL_8B_tag PCTL47;         /* offset: 0x00EF size: 8 bit */
-            ME_PCTL_8B_tag PCTL48;         /* offset: 0x00F0 size: 8 bit */
-            ME_PCTL_8B_tag PCTL49;         /* offset: 0x00F1 size: 8 bit */
-            ME_PCTL_8B_tag PCTL50;         /* offset: 0x00F2 size: 8 bit */
-            ME_PCTL_8B_tag PCTL51;         /* offset: 0x00F3 size: 8 bit */
-            ME_PCTL_8B_tag PCTL52;         /* offset: 0x00F4 size: 8 bit */
-            ME_PCTL_8B_tag PCTL53;         /* offset: 0x00F5 size: 8 bit */
-            ME_PCTL_8B_tag PCTL54;         /* offset: 0x00F6 size: 8 bit */
-            ME_PCTL_8B_tag PCTL55;         /* offset: 0x00F7 size: 8 bit */
-            ME_PCTL_8B_tag PCTL56;         /* offset: 0x00F8 size: 8 bit */
-            ME_PCTL_8B_tag PCTL57;         /* offset: 0x00F9 size: 8 bit */
-            ME_PCTL_8B_tag PCTL58;         /* offset: 0x00FA size: 8 bit */
-            ME_PCTL_8B_tag PCTL59;         /* offset: 0x00FB size: 8 bit */
-            ME_PCTL_8B_tag PCTL60;         /* offset: 0x00FC size: 8 bit */
-            ME_PCTL_8B_tag PCTL61;         /* offset: 0x00FD size: 8 bit */
-            ME_PCTL_8B_tag PCTL62;         /* offset: 0x00FE size: 8 bit */
-            ME_PCTL_8B_tag PCTL63;         /* offset: 0x00FF size: 8 bit */
-            ME_PCTL_8B_tag PCTL64;         /* offset: 0x0100 size: 8 bit */
-            ME_PCTL_8B_tag PCTL65;         /* offset: 0x0101 size: 8 bit */
-            ME_PCTL_8B_tag PCTL66;         /* offset: 0x0102 size: 8 bit */
-            ME_PCTL_8B_tag PCTL67;         /* offset: 0x0103 size: 8 bit */
-            ME_PCTL_8B_tag PCTL68;         /* offset: 0x0104 size: 8 bit */
-            ME_PCTL_8B_tag PCTL69;         /* offset: 0x0105 size: 8 bit */
-            ME_PCTL_8B_tag PCTL70;         /* offset: 0x0106 size: 8 bit */
-            ME_PCTL_8B_tag PCTL71;         /* offset: 0x0107 size: 8 bit */
-            ME_PCTL_8B_tag PCTL72;         /* offset: 0x0108 size: 8 bit */
-            ME_PCTL_8B_tag PCTL73;         /* offset: 0x0109 size: 8 bit */
-            ME_PCTL_8B_tag PCTL74;         /* offset: 0x010A size: 8 bit */
-            ME_PCTL_8B_tag PCTL75;         /* offset: 0x010B size: 8 bit */
-            ME_PCTL_8B_tag PCTL76;         /* offset: 0x010C size: 8 bit */
-            ME_PCTL_8B_tag PCTL77;         /* offset: 0x010D size: 8 bit */
-            ME_PCTL_8B_tag PCTL78;         /* offset: 0x010E size: 8 bit */
-            ME_PCTL_8B_tag PCTL79;         /* offset: 0x010F size: 8 bit */
-            ME_PCTL_8B_tag PCTL80;         /* offset: 0x0110 size: 8 bit */
-            ME_PCTL_8B_tag PCTL81;         /* offset: 0x0111 size: 8 bit */
-            ME_PCTL_8B_tag PCTL82;         /* offset: 0x0112 size: 8 bit */
-            ME_PCTL_8B_tag PCTL83;         /* offset: 0x0113 size: 8 bit */
-            ME_PCTL_8B_tag PCTL84;         /* offset: 0x0114 size: 8 bit */
-            ME_PCTL_8B_tag PCTL85;         /* offset: 0x0115 size: 8 bit */
-            ME_PCTL_8B_tag PCTL86;         /* offset: 0x0116 size: 8 bit */
-            ME_PCTL_8B_tag PCTL87;         /* offset: 0x0117 size: 8 bit */
-            ME_PCTL_8B_tag PCTL88;         /* offset: 0x0118 size: 8 bit */
-            ME_PCTL_8B_tag PCTL89;         /* offset: 0x0119 size: 8 bit */
-            ME_PCTL_8B_tag PCTL90;         /* offset: 0x011A size: 8 bit */
-            ME_PCTL_8B_tag PCTL91;         /* offset: 0x011B size: 8 bit */
-            ME_PCTL_8B_tag PCTL92;         /* offset: 0x011C size: 8 bit */
-            ME_PCTL_8B_tag PCTL93;         /* offset: 0x011D size: 8 bit */
-            ME_PCTL_8B_tag PCTL94;         /* offset: 0x011E size: 8 bit */
-            ME_PCTL_8B_tag PCTL95;         /* offset: 0x011F size: 8 bit */
-            ME_PCTL_8B_tag PCTL96;         /* offset: 0x0120 size: 8 bit */
-            ME_PCTL_8B_tag PCTL97;         /* offset: 0x0121 size: 8 bit */
-            ME_PCTL_8B_tag PCTL98;         /* offset: 0x0122 size: 8 bit */
-            ME_PCTL_8B_tag PCTL99;         /* offset: 0x0123 size: 8 bit */
-            ME_PCTL_8B_tag PCTL100;        /* offset: 0x0124 size: 8 bit */
-            ME_PCTL_8B_tag PCTL101;        /* offset: 0x0125 size: 8 bit */
-            ME_PCTL_8B_tag PCTL102;        /* offset: 0x0126 size: 8 bit */
-            ME_PCTL_8B_tag PCTL103;        /* offset: 0x0127 size: 8 bit */
-            ME_PCTL_8B_tag PCTL104;        /* offset: 0x0128 size: 8 bit */
-            ME_PCTL_8B_tag PCTL105;        /* offset: 0x0129 size: 8 bit */
-            ME_PCTL_8B_tag PCTL106;        /* offset: 0x012A size: 8 bit */
-            ME_PCTL_8B_tag PCTL107;        /* offset: 0x012B size: 8 bit */
-            ME_PCTL_8B_tag PCTL108;        /* offset: 0x012C size: 8 bit */
-            ME_PCTL_8B_tag PCTL109;        /* offset: 0x012D size: 8 bit */
-            ME_PCTL_8B_tag PCTL110;        /* offset: 0x012E size: 8 bit */
-            ME_PCTL_8B_tag PCTL111;        /* offset: 0x012F size: 8 bit */
-            ME_PCTL_8B_tag PCTL112;        /* offset: 0x0130 size: 8 bit */
-            ME_PCTL_8B_tag PCTL113;        /* offset: 0x0131 size: 8 bit */
-            ME_PCTL_8B_tag PCTL114;        /* offset: 0x0132 size: 8 bit */
-            ME_PCTL_8B_tag PCTL115;        /* offset: 0x0133 size: 8 bit */
-            ME_PCTL_8B_tag PCTL116;        /* offset: 0x0134 size: 8 bit */
-            ME_PCTL_8B_tag PCTL117;        /* offset: 0x0135 size: 8 bit */
-            ME_PCTL_8B_tag PCTL118;        /* offset: 0x0136 size: 8 bit */
-            ME_PCTL_8B_tag PCTL119;        /* offset: 0x0137 size: 8 bit */
-            ME_PCTL_8B_tag PCTL120;        /* offset: 0x0138 size: 8 bit */
-            ME_PCTL_8B_tag PCTL121;        /* offset: 0x0139 size: 8 bit */
-            ME_PCTL_8B_tag PCTL122;        /* offset: 0x013A size: 8 bit */
-            ME_PCTL_8B_tag PCTL123;        /* offset: 0x013B size: 8 bit */
-            ME_PCTL_8B_tag PCTL124;        /* offset: 0x013C size: 8 bit */
-            ME_PCTL_8B_tag PCTL125;        /* offset: 0x013D size: 8 bit */
-            ME_PCTL_8B_tag PCTL126;        /* offset: 0x013E size: 8 bit */
-            ME_PCTL_8B_tag PCTL127;        /* offset: 0x013F size: 8 bit */
-            ME_PCTL_8B_tag PCTL128;        /* offset: 0x0140 size: 8 bit */
-            ME_PCTL_8B_tag PCTL129;        /* offset: 0x0141 size: 8 bit */
-            ME_PCTL_8B_tag PCTL130;        /* offset: 0x0142 size: 8 bit */
-            ME_PCTL_8B_tag PCTL131;        /* offset: 0x0143 size: 8 bit */
-            ME_PCTL_8B_tag PCTL132;        /* offset: 0x0144 size: 8 bit */
-            ME_PCTL_8B_tag PCTL133;        /* offset: 0x0145 size: 8 bit */
-            ME_PCTL_8B_tag PCTL134;        /* offset: 0x0146 size: 8 bit */
-            ME_PCTL_8B_tag PCTL135;        /* offset: 0x0147 size: 8 bit */
-            ME_PCTL_8B_tag PCTL136;        /* offset: 0x0148 size: 8 bit */
-            ME_PCTL_8B_tag PCTL137;        /* offset: 0x0149 size: 8 bit */
-            ME_PCTL_8B_tag PCTL138;        /* offset: 0x014A size: 8 bit */
-            ME_PCTL_8B_tag PCTL139;        /* offset: 0x014B size: 8 bit */
-            ME_PCTL_8B_tag PCTL140;        /* offset: 0x014C size: 8 bit */
-            ME_PCTL_8B_tag PCTL141;        /* offset: 0x014D size: 8 bit */
-            ME_PCTL_8B_tag PCTL142;        /* offset: 0x014E size: 8 bit */
-            ME_PCTL_8B_tag PCTL143;        /* offset: 0x014F size: 8 bit */
-         };
-
-      };
-   } ME_tag;
-
-
-#define ME    (*(volatile ME_tag *) 0xC3FDC000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: OSC  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* OSC_CTL - Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  OSCBYP:1;          /* High Frequency Oscillator Bypass */
-         vuint32_t:7;
-         vuint32_t  EOCV:8;            /* End of Count Value */
-         vuint32_t  M_OSC:1;           /* High Frequency Oscillator Clock Interrupt Mask */
-         vuint32_t:2;
-         vuint32_t  OSCDIV:5;          /* High Frequency Oscillator Division Factor */
-         vuint32_t  I_OSC:1;           /* High Frequency Oscillator Clock Interrupt */
-         vuint32_t:5;
-         vuint32_t S_OSC:1;
-         vuint32_t OSCON:1;      } B;
-   } OSC_CTL_32B_tag;
-
-
-
-   typedef struct OSC_struct_tag { /* start of OSC_tag */
-                                           /* OSC_CTL - Control Register */
-      OSC_CTL_32B_tag CTL;                 /* offset: 0x0000 size: 32 bit */
-   } OSC_tag;
-
-
-#define OSC   (*(volatile OSC_tag *) 0xC3FE0000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: RC  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* RC_CTL - Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:10;
-         vuint32_t  RCTRIM:6;          /* Main RC Trimming Bits */
-         vuint32_t:3;
-         vuint32_t  RCDIV:5;           /* Main RC Clock Division Factor */
-         vuint32_t:2;
-         vuint32_t  S_RC_STDBY:1;      /* MRC Oscillator Powerdown Status */
-         vuint32_t:5;
-      } B;
-   } RC_CTL_32B_tag;
-
-
-
-   typedef struct RC_struct_tag { /* start of RC_tag */
-                                            /* RC_CTL - Control Register */
-      RC_CTL_32B_tag CTL;                  /* offset: 0x0000 size: 32 bit */
-   } RC_tag;
-
-
-#define RC    (*(volatile RC_tag *) 0xC3FE0060UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: PLLD  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* PLLD_CR - Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:2;
-         vuint32_t  IDF:4;             /* PLL Input Division Factor */
-         vuint32_t  ODF:2;             /* PLL Output Division Factor */
-         vuint32_t:1;
-         vuint32_t  NDIV:7;            /* PLL Loop Division Factor */
-         vuint32_t:7;
-         vuint32_t  EN_PLL_SW:1;       /* Enable Progressive Clock Switching */
-         vuint32_t  MODE:1;            /* Activate 1:1 Mode */
-         vuint32_t  UNLOCK_ONCE:1;     /* PLL Loss of Lock */
-         vuint32_t  M_LOCK:1;          /* Mask for the i_lock Output Interrupt */
-         vuint32_t  I_LOCK:1;          /* PLL Lock Signal Toggle Indicator */
-         vuint32_t  S_LOCK:1;          /* PLL has Aquired Lock */
-         vuint32_t  PLL_FAIL_MASK:1;   /* PLL Fail Mask */
-         vuint32_t  PLL_FAIL_FLAG:1;   /* PLL Fail Flag */
-         vuint32_t  PLL_ON:1;          /* PLL ON Bit */
-      } B;
-   } PLLD_CR_32B_tag;
-
-   typedef union {   /* PLLD_MR - PLLD Modulation Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  STRB_BYPASS:1;     /* Strobe Bypass */
-         vuint32_t:1;
-         vuint32_t  SPRD_SEL:1;        /* Spread Type Selection */
-         vuint32_t  MOD_PERIOD:13;     /* Modulation Period */
-         vuint32_t  SSCG_EN:1;         /* Spread Spectrum Clock Generation Enable */
-         vuint32_t  INC_STEP:15;       /* Increment Step */
-      } B;
-   } PLLD_MR_32B_tag;
-
-
-
-   typedef struct PLLD_struct_tag { /* start of PLLD_tag */
-                                           /* PLLD_CR - Control Register */
-      PLLD_CR_32B_tag CR;                  /* offset: 0x0000 size: 32 bit */
-                                   /* PLLD_MR - PLLD Modulation Register */
-      PLLD_MR_32B_tag MR;                  /* offset: 0x0004 size: 32 bit */
-	  
-	  vuint32_t plld_reserved[6];
-   } PLLD_tag;
-
-
-#define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL)
-#define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: CMU  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* CMU_CSR - Control Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:8;
-         vuint32_t  SFM:1;             /* Start Frequency Measure */
-         vuint32_t:13;
-         vuint32_t  CKSEL1:2;          /* RC Oscillator(s) Selection Bit */
-         vuint32_t:5;
-         vuint32_t  RCDIV:2;           /* RCfast Clock Division Factor */
-         vuint32_t  CME_A:1;           /* PLL_A Clock Monitor Enable */
-      } B;
-   } CMU_CSR_32B_tag;
-
-   typedef union {   /* CMU_FDR - Frequency Display Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:12;
-         vuint32_t  FD:20;             /* Measured Frequency Bits */
-      } B;
-   } CMU_FDR_32B_tag;
-
-   typedef union {   /* CMU_HFREFR_A - High Frequency Reference Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:20;
-         vuint32_t  HFREF_A:12;        /* High Frequency Reference Value */
-      } B;
-   } CMU_HFREFR_A_32B_tag;
-
-   typedef union {   /* CMU_LFREFR_A - Low Frequency Reference Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:20;
-         vuint32_t  LFREF_A:12;        /* Low Frequency Reference Value */
-      } B;
-   } CMU_LFREFR_A_32B_tag;
-
-   typedef union {   /* CMU_ISR - Interrupt Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-         vuint32_t  FLCI_A:1;          /* PLL_A Clock Frequency less than Reference Clock Interrupt */
-         vuint32_t  FHH_AI:1;          /* PLL_A Clock Frequency higher than high Reference Interrupt */
-         vuint32_t  FLLI_A:1;          /* PLL_A Clock Frequency less than low Reference Interrupt */
-         vuint32_t  OLRI:1;            /* Oscillator Frequency less than RC Frequency Interrupt */
-      } B;
-   } CMU_ISR_32B_tag;
-
-   typedef union {   /* CMU_IMR - Interrupt Mask Register */
-      vuint32_t R;
-   } CMU_IMR_32B_tag;
-
-   typedef union {   /* CMU_MDR - Measurement Duration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:12;
-         vuint32_t  MD:20;             /* Measurment Duration Bits */
-      } B;
-   } CMU_MDR_32B_tag;
-
-
-
-   typedef struct CMU_struct_tag { /* start of CMU_tag */
-                                    /* CMU_CSR - Control Status Register */
-      CMU_CSR_32B_tag CSR;                 /* offset: 0x0000 size: 32 bit */
-                                 /* CMU_FDR - Frequency Display Register */
-      CMU_FDR_32B_tag FDR;                 /* offset: 0x0004 size: 32 bit */
-                     /* CMU_HFREFR_A - High Frequency Reference Register */
-      CMU_HFREFR_A_32B_tag HFREFR_A;       /* offset: 0x0008 size: 32 bit */
-                      /* CMU_LFREFR_A - Low Frequency Reference Register */
-      CMU_LFREFR_A_32B_tag LFREFR_A;       /* offset: 0x000C size: 32 bit */
-                                  /* CMU_ISR - Interrupt Status Register */
-      CMU_ISR_32B_tag ISR;                 /* offset: 0x0010 size: 32 bit */
-                                    /* CMU_IMR - Interrupt Mask Register */
-      CMU_IMR_32B_tag IMR;                 /* offset: 0x0014 size: 32 bit */
-                              /* CMU_MDR - Measurement Duration Register */
-      CMU_MDR_32B_tag MDR;                 /* offset: 0x0018 size: 32 bit */
-   } CMU_tag;
-
-
-#define CMU0  (*(volatile CMU_tag *) 0xC3FE0100UL)
-#define CMU1  (*(volatile CMU_tag *) 0xC3FE0120UL)
-#define CMU2  (*(volatile CMU_tag *) 0xC3FE0140UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: CGM  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* Output Clock Enable Register */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint16_t  HALF[2];    /* individual halfwords can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-      struct {
-         vuint32_t:31;
-         vuint32_t  EN:1;              /* Clock Enable Bit */
-      } B;
-   } CGM_OC_EN_32B_tag;
-
-   typedef union {   /* Output Clock Division Select Register */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint16_t  HALF[2];    /* individual halfwords can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-      struct {
-         vuint32_t:2;
-         vuint32_t  SELDIV:2;          /* Output Clock Division Select */
-         vuint32_t  SELCTL:4;          /* Output Clock Source Selection Control */
-         vuint32_t:24;
-      } B;
-   } CGM_OCDS_SC_32B_tag;
-
-   typedef union {   /* System Clock Select Status Register */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint16_t  HALF[2];    /* individual halfwords can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-      struct {
-         vuint32_t:4;
-         vuint32_t  SELSTAT:4;         /* System Clock Source Selection Status */
-         vuint32_t:24;
-      } B;
-   } CGM_SC_SS_32B_tag;
-
-   typedef union {   /* System Clock Divider Configuration Register */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint16_t  HALF[2];    /* individual halfwords can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-      struct {
-         vuint32_t  DE0:1;             /* Divider 0 Enable */
-         vuint32_t:3;
-         vuint32_t  DIV0:4;            /* Divider 0 Value */
-         vuint32_t:24;
-      } B;
-   } CGM_SC_DC0_3_32B_tag;
-
-
-   /* Register layout for all registers SC_DC... */
-
-   typedef union {   /* System Clock Divider Configuration Register */
-      vuint8_t R;
-      struct {
-         vuint8_t   DE:1;              /* Divider Enable */
-         vuint8_t:3;
-         vuint8_t   DIV:4;             /* Divider Division Value */
-      } B;
-   } CGM_SC_DC_8B_tag;
-
-
-   /* Register layout for all registers AC_SC... */
-
-   typedef union {   /* Auxiliary Clock Select Control Registers */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint16_t  HALF[2];    /* individual halfwords can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-      struct {
-         vuint32_t:4;
-         vuint32_t  SELCTL:4;          /* Auxliary Clock Source Selection Control */
-         vuint32_t:24;
-      } B;
-   } CGM_AC_SC_32B_tag;
-
-
-   /* Register layout for all registers AC_DC0_3... */
-
-   typedef union {   /* Auxiliary Clock Divider Configuration Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  DE0:1;             /* Divider 0 Enable */
-         vuint32_t:3;
-         vuint32_t  DIV0:4;            /* Divider 0 Value */
-         vuint32_t  DE1:1;             /* Divider 1 Enable */
-         vuint32_t:3;
-         vuint32_t  DIV1:4;            /* Divider 1 Value */
-         vuint32_t:16;
-      } B;
-   } CGM_AC_DC0_3_32B_tag;
-
-
-   typedef struct CGM_AUXCLK_struct_tag {
-
-                             /* Auxiliary Clock Select Control Registers */
-      CGM_AC_SC_32B_tag AC_SC;            /* relative offset: 0x0000 */
-                      /* Auxiliary Clock Divider Configuration Registers */
-      CGM_AC_DC0_3_32B_tag AC_DC0_3;      /* relative offset: 0x0004 */
-
-   } CGM_AUXCLK_tag;
-
-
-   typedef struct CGM_struct_tag { /* start of CGM_tag */
-      OSC_CTL_32B_tag OSC_CTL;             /* offset: 0x0000 size: 32 bit */
-      int8_t CGM_reserved_0004[92];
-      RC_CTL_32B_tag RC_CTL;               /* offset: 0x0060 size: 32 bit */
-      int8_t CGM_reserved_0064[60];
-      PLLD_tag FMPLL[2];                   /* offset: 0x00A0  (0x0020 x 2) */
-      int8_t CGM_reserved_00E0[32];
-      CMU_CSR_32B_tag CMU_0_CSR;           /* offset: 0x0100 size: 32 bit */
-      CMU_FDR_32B_tag CMU_0_FDR;           /* offset: 0x0104 size: 32 bit */
-      CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A;  /* offset: 0x0108 size: 32 bit */
-      CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A;  /* offset: 0x010C size: 32 bit */
-      CMU_ISR_32B_tag CMU_0_ISR;           /* offset: 0x0110 size: 32 bit */
-      CMU_IMR_32B_tag CMU_0_IMR;           /* offset: 0x0114 size: 32 bit */
-      CMU_MDR_32B_tag CMU_0_MDR;           /* offset: 0x0118 size: 32 bit */
-      int8_t CGM_reserved_011C[4];
-      CMU_CSR_32B_tag CMU_1_CSR;           /* offset: 0x0120 size: 32 bit */
-      int8_t CGM_reserved_0124[4];
-      CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A;  /* offset: 0x0128 size: 32 bit */
-      CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A;  /* offset: 0x012C size: 32 bit */
-      CMU_ISR_32B_tag CMU_1_ISR;           /* offset: 0x0130 size: 32 bit */
-      int8_t CGM_reserved_0134[572];
-                                         /* Output Clock Enable Register */
-      CGM_OC_EN_32B_tag OC_EN;             /* offset: 0x0370 size: 32 bit */
-                                /* Output Clock Division Select Register */
-      CGM_OCDS_SC_32B_tag OCDS_SC;         /* offset: 0x0374 size: 32 bit */
-                                  /* System Clock Select Status Register */
-      CGM_SC_SS_32B_tag SC_SS;             /* offset: 0x0378 size: 32 bit */
-      union {
-         struct {
-                          /* System Clock Divider Configuration Register */
-            CGM_SC_DC_8B_tag SC_DC[2];     /* offset: 0x037C  (0x0001 x 2) */
-            int8_t CGM_reserved_037E_E0[2];
-         };
-
-         struct {
-                          /* System Clock Divider Configuration Register */
-            CGM_SC_DC_8B_tag SC_DC0;       /* offset: 0x037C size: 8 bit */
-            CGM_SC_DC_8B_tag SC_DC1;       /* offset: 0x037D size: 8 bit */
-            int8_t CGM_reserved_037E_E1[2];
-         };
-
-                          /* System Clock Divider Configuration Register */
-         CGM_SC_DC0_3_32B_tag SC_DC0_3;    /* offset: 0x037C size: 32 bit */
-
-      };
-      union {
-                                                 /*  Register set AUXCLK */
-         CGM_AUXCLK_tag AUXCLK[6];         /* offset: 0x0380  (0x0008 x 6) */
-
-         struct {
-                             /* Auxiliary Clock Select Control Registers */
-            CGM_AC_SC_32B_tag AC0_SC;      /* offset: 0x0380 size: 32 bit */
-                      /* Auxiliary Clock Divider Configuration Registers */
-            CGM_AC_DC0_3_32B_tag AC0_DC0_3;  /* offset: 0x0384 size: 32 bit */
-                             /* Auxiliary Clock Select Control Registers */
-            CGM_AC_SC_32B_tag AC1_SC;      /* offset: 0x0388 size: 32 bit */
-                      /* Auxiliary Clock Divider Configuration Registers */
-            CGM_AC_DC0_3_32B_tag AC1_DC0_3;  /* offset: 0x038C size: 32 bit */
-                             /* Auxiliary Clock Select Control Registers */
-            CGM_AC_SC_32B_tag AC2_SC;      /* offset: 0x0390 size: 32 bit */
-                      /* Auxiliary Clock Divider Configuration Registers */
-            CGM_AC_DC0_3_32B_tag AC2_DC0_3;  /* offset: 0x0394 size: 32 bit */
-                             /* Auxiliary Clock Select Control Registers */
-            CGM_AC_SC_32B_tag AC3_SC;      /* offset: 0x0398 size: 32 bit */
-                      /* Auxiliary Clock Divider Configuration Registers */
-            CGM_AC_DC0_3_32B_tag AC3_DC0_3;  /* offset: 0x039C size: 32 bit */
-                             /* Auxiliary Clock Select Control Registers */
-            CGM_AC_SC_32B_tag AC4_SC;      /* offset: 0x03A0 size: 32 bit */
-                      /* Auxiliary Clock Divider Configuration Registers */
-            CGM_AC_DC0_3_32B_tag AC4_DC0_3;  /* offset: 0x03A4 size: 32 bit */
-                             /* Auxiliary Clock Select Control Registers */
-            CGM_AC_SC_32B_tag AC5_SC;      /* offset: 0x03A8 size: 32 bit */
-                      /* Auxiliary Clock Divider Configuration Registers */
-            CGM_AC_DC0_3_32B_tag AC5_DC0_3;  /* offset: 0x03AC size: 32 bit */
-         };
-
-      };
-   } CGM_tag;
-
-
-#define CGM   (*(volatile CGM_tag *) 0xC3FE0000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: RGM  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* Functional Event Status Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  F_EXR:1;           /* Flag for External Reset */
-         vuint16_t  F_FCCU_HARD:1;     /* Flag for FCCU hard reaction request */
-         vuint16_t  F_FCCU_SOFT:1;     /* Flag for FCCU soft reaction request */
-         vuint16_t  F_ST_DONE:1;       /* Flag for self-test completed */
-#ifndef USE_FIELD_ALIASES_RGM
-         vuint16_t  F_CMU12_FHL:1;     /* Flag for CMU 1/2 clock freq. too high/low */
-#else
-         vuint16_t  F_CMU1_FHL:1;        /* deprecated name - please avoid */
-#endif
-         vuint16_t  F_FL_ECC_RCC:1;    /* Flag for Flash, ECC, or lock-step error */
-         vuint16_t  F_PLL1:1;          /* Flag for PLL1 fail */
-         vuint16_t  F_SWT:1;           /* Flag for Software Watchdog Timer */
-         vuint16_t  F_FCCU_SAFE:1;     /* Flag for FCCU SAFE mode request */
-         vuint16_t  F_CMU0_FHL:1;      /* Flag for CMU 0 clock freq. too high/low */
-         vuint16_t  F_CMU0_OLR:1;      /* Flag for oscillator freq. too low */
-         vuint16_t  F_PLL0:1;          /* Flag for PLL0 fail */
-         vuint16_t  F_CWD:1;           /* Flag for Core Watchdog Reset */
-         vuint16_t  F_SOFT:1;          /* Flag for software reset */
-         vuint16_t  F_CORE:1;          /* Flag for core reset */
-         vuint16_t  F_JTAG:1;          /* Flag for JTAG initiated reset */
-      } B;
-   } RGM_FES_16B_tag;
-
-   typedef union {   /* Destructive Event Status Register */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_RGM
-         vuint16_t  F_POR:1;           /* Flag for Power on Reset */
-#else
-         vuint16_t  POR:1;               /* deprecated name - please avoid */
-#endif
-         vuint16_t:7;
-         vuint16_t  F_COMP:1;          /* Flag for comparator error */
-         vuint16_t  F_LVD27_IO:1;      /* Flag for 2.7V low-voltage detected (I/O) */
-         vuint16_t  F_LVD27_FLASH:1;   /* Flag for 2.7V low-voltage detected (Flash) */
-         vuint16_t  F_LVD27_VREG:1;    /* Flag for 2.7V low-voltage detected (VREG) */
-         vuint16_t:2;
-         vuint16_t  F_HVD12:1;         /* Flag for 1.2V high-voltage detected */
-#ifndef USE_FIELD_ALIASES_RGM
-         vuint16_t  F_LVD12:1;         /* Flag for 1.2V low-voltage detected */
-#else
-         vuint16_t  F_LVD12_PD0:1;       /* deprecated name - please avoid */
-#endif
-      } B;
-   } RGM_DES_16B_tag;
-
-   typedef union {   /* Functional Event Reset Disable Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  D_EXR:1;           /* Disable External Pad Event Reset */
-         vuint16_t  D_FCCU_HARD:1;     /* Disable FCCU hard reaction request */
-         vuint16_t  D_FCCU_SOFT:1;     /* Disable FCCU soft reaction request */
-         vuint16_t  D_ST_DONE:1;       /* Disable self-test completed */
-#ifndef USE_FIELD_ALIASES_RGM
-         vuint16_t  D_CMU12_FHL:1;     /* Disable CMU 1/2 clock freq. too high/low */
-#else
-         vuint16_t  D_CMU1_FHL:1;        /* deprecated name - please avoid */
-#endif
-         vuint16_t  D_FL_ECC_RCC:1;    /* Disable Flash, ECC, or lock-step error */
-         vuint16_t  D_PLL1:1;          /* Disable PLL1 fail */
-         vuint16_t  D_SWT:1;           /* Disable Software Watchdog Timer */
-         vuint16_t  D_FCCU_SAFE:1;     /* Disable FCCU SAFE mode request */
-         vuint16_t  D_CMU0_FHL:1;      /* Disable CMU 0 clock freq. too high/low */
-         vuint16_t  D_CMU0_OLR:1;      /* Disable oscillator freq. too low */
-         vuint16_t  D_PLL0:1;          /* Disable PLL0 fail */
-         vuint16_t  D_CWD:1;           /* Disable Core Watchdog Reset */
-         vuint16_t  D_SOFT:1;          /* Disable software reset */
-         vuint16_t  D_CORE:1;          /* Disable core reset */
-         vuint16_t  D_JTAG:1;          /* Disable JTAG initiated reset */
-      } B;
-   } RGM_FERD_16B_tag;
-
-   typedef union {   /* Destructive Event Reset Disable Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:8;
-         vuint16_t  D_COMP:1;          /* Disable comparator error */
-         vuint16_t  D_LVD27_IO:1;      /* Disable 2.7V low-voltage detected (I/O) */
-         vuint16_t  D_LVD27_FLASH:1;   /* Disable 2.7V low-voltage detected (Flash) */
-         vuint16_t  D_LVD27_VREG:1;    /* Disable 2.7V low-voltage detected (VREG) */
-         vuint16_t:2;
-         vuint16_t  D_HVD12:1;         /* Disable 1.2V high-voltage detected */
-#ifndef USE_FIELD_ALIASES_RGM
-         vuint16_t  D_LVD12:1;         /* Disable 1.2V low-voltage detected */
-#else
-         vuint16_t  D_LVD12_PD0:1;       /* deprecated name - please avoid */
-#endif
-      } B;
-   } RGM_DERD_16B_tag;
-
-   typedef union {   /* Functional Event Alternate Request Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:4;
-#ifndef USE_FIELD_ALIASES_RGM
-         vuint16_t  AR_CMU12_FHL:1;    /* Alternate Request for CMU1/2 clock freq. too high/low */
-#else
-         vuint16_t  AR_CMU1_FHL:1;       /* deprecated name - please avoid */
-#endif
-         vuint16_t:1;
-         vuint16_t  AR_PLL1:1;         /* Alternate Request for PLL1 fail */
-         vuint16_t:1;
-         vuint16_t  AR_FCCU_SAVE:1;    /* Alternate Request for FCCU SAFE mode request */
-         vuint16_t  AR_CMU0_FHL:1;     /* Alternate Request for CMU0 clock freq.
- too high/low */
-         vuint16_t  AR_CMU0_OLR:1;     /* Alternate Request for oscillator freq. too low */
-         vuint16_t  AR_PLL0:1;         /* Alternate Request for PLL0 fail */
-         vuint16_t  AR_CWD:1;          /* Alternate Request for core watchdog reset */
-         vuint16_t:3;
-      } B;
-   } RGM_FEAR_16B_tag;
-
-   typedef union {   /* Functional Event Short Sequence Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  SS_EXR:1;          /* Short Sequence for External Reset */
-         vuint16_t  SS_FCCU_HARD:1;    /* Short Sequence for FCCU hard reaction request */
-         vuint16_t  SS_FCCU_SOFT:1;    /* Short Sequence for FCCU soft reaction request */
-         vuint16_t  SS_ST_DONE:1;      /* Short Sequence for self-test completed */
-#ifndef USE_FIELD_ALIASES_RGM
-         vuint16_t  SS_CMU12_FHL:1;    /* Short Sequence for CMU 1/2 clock freq. too high/low */
-#else
-         vuint16_t  SS_CMU1_FHL:1;       /* deprecated name - please avoid */
-#endif
-         vuint16_t  SS_FL_ECC_RCC:1;   /* Short Sequence for Flash, ECC, or lock-step error */
-         vuint16_t  SS_PLL1:1;         /* Short Sequence for PLL1 fail */
-         vuint16_t  SS_SWT:1;          /* Short Sequence for Software Watchdog Timer */
-         vuint16_t:1;
-         vuint16_t  SS_CMU0_FHL:1;     /* Short Sequence for CMU 0 clock freq. too high/low */
-         vuint16_t  SS_CMU0_OLR:1;     /* Short Sequence for oscillator freq. too low */
-         vuint16_t  SS_PLL0:1;         /* Short Sequence for PLL0 fail */
-         vuint16_t  SS_CWD:1;          /* Short Sequence for Core Watchdog Reset */
-         vuint16_t  SS_SOFT:1;         /* Short Sequence for software reset */
-         vuint16_t  SS_CORE:1;         /* Short Sequence for core reset */
-         vuint16_t  SS_JTAG:1;         /* Short Sequence for JTAG initiated reset */
-      } B;
-   } RGM_FESS_16B_tag;
-
-   typedef union {   /* Functional Bidirectional Reset Enable Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  BE_EXR:1;          /* Bidirectional Reset Enable for External Reset */
-         vuint16_t  BE_FCCU_HARD:1;    /* Bidirectional Reset Enable for FCCU hard reaction request */
-         vuint16_t  BE_FCCU_SOFT:1;    /* Bidirectional Reset Enable for FCCU soft reaction request */
-         vuint16_t  BE_ST_DONE:1;      /* Bidirectional Reset Enable for self-test completed */
-#ifndef USE_FIELD_ALIASES_RGM
-         vuint16_t  BE_CMU12_FHL:1;    /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */
-#else
-         vuint16_t  BE_CMU1_FHL:1;       /* deprecated name - please avoid */
-#endif
-         vuint16_t  BE_FL_ECC_RCC:1;   /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */
-         vuint16_t  BE_PLL1:1;         /* Bidirectional Reset Enable for PLL1 fail */
-         vuint16_t  BE_SWT:1;          /* Bidirectional Reset Enable for Software Watchdog Timer */
-         vuint16_t:1;
-         vuint16_t  BE_CMU0_FHL:1;     /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */
-         vuint16_t  BE_CMU0_OLR:1;     /* Bidirectional Reset Enable for oscillator freq. too low */
-         vuint16_t  BE_PLL0:1;         /* Bidirectional Reset Enable for PLL0 fail */
-         vuint16_t  BE_CWD:1;          /* Bidirectional Reset Enable for Core Watchdog Reset */
-         vuint16_t  BE_SOFT:1;         /* Bidirectional Reset Enable for software reset */
-         vuint16_t  BE_CORE:1;         /* Bidirectional Reset Enable for core reset */
-         vuint16_t  BE_JTAG:1;         /* Bidirectional Reset Enable for JTAG initiated reset */
-      } B;
-   } RGM_FBRE_16B_tag;
-
-
-
-   typedef struct RGM_struct_tag { /* start of RGM_tag */
-                                     /* Functional Event Status Register */
-      RGM_FES_16B_tag FES;                 /* offset: 0x0000 size: 16 bit */
-                                    /* Destructive Event Status Register */
-      RGM_DES_16B_tag DES;                 /* offset: 0x0002 size: 16 bit */
-                              /* Functional Event Reset Disable Register */
-      RGM_FERD_16B_tag FERD;               /* offset: 0x0004 size: 16 bit */
-                             /* Destructive Event Reset Disable Register */
-      RGM_DERD_16B_tag DERD;               /* offset: 0x0006 size: 16 bit */
-      int8_t RGM_reserved_0008[8];
-                          /* Functional Event Alternate Request Register */
-      RGM_FEAR_16B_tag FEAR;               /* offset: 0x0010 size: 16 bit */
-      int8_t RGM_reserved_0012[6];
-                             /* Functional Event Short Sequence Register */
-      RGM_FESS_16B_tag FESS;               /* offset: 0x0018 size: 16 bit */
-      int8_t RGM_reserved_001A[2];
-                       /* Functional Bidirectional Reset Enable Register */
-      RGM_FBRE_16B_tag FBRE;               /* offset: 0x001C size: 16 bit */
-   } RGM_tag;
-
-
-#define RGM   (*(volatile RGM_tag *) 0xC3FE4000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: PCU  */
-/*                                                              */
-/****************************************************************/
-
-
-   /* Register layout for all registers PCONF... */
-
-   typedef union {   /* PCU_PCONF[0..15] -  Power Domain #0..#15 Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:18;
-         vuint32_t  STBY0:1;           /* Power domain control during STBY0 */
-         vuint32_t:2;
-         vuint32_t  STOP0:1;           /* Power domain control during STOP0 */
-         vuint32_t:1;
-         vuint32_t  HALT0:1;           /* Power domain control during HALT0 */
-         vuint32_t  RUN3:1;            /* Power domain control during RUN3 */
-         vuint32_t  RUN2:1;            /* Power domain control during RUN2 */
-         vuint32_t  RUN1:1;            /* Power domain control during RUN1 */
-         vuint32_t  RUN0:1;            /* Power domain control during RUN0 */
-         vuint32_t  DRUN:1;            /* Power domain control during DRUN */
-         vuint32_t  SAFE:1;            /* Power domain control during SAFE */
-         vuint32_t  TEST:1;            /* Power domain control during TEST */
-         vuint32_t  RST:1;             /* Power domain control during RST */
-      } B;
-   } PCU_PCONF_32B_tag;
-
-   typedef union {   /* PCU_PSTAT - Power Domain Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  PD15:1;            /* Power Status for Power Domain 15 */
-         vuint32_t  PD14:1;            /* Power Status for Power Domain 14 */
-         vuint32_t  PD13:1;            /* Power Status for Power Domain 13 */
-         vuint32_t  PD12:1;            /* Power Status for Power Domain 12 */
-         vuint32_t  PD11:1;            /* Power Status for Power Domain 11 */
-         vuint32_t  PD10:1;            /* Power Status for Power Domain 10 */
-         vuint32_t  PD9:1;             /* Power Status for Power Domain 9 */
-         vuint32_t  PD8:1;             /* Power Status for Power Domain 8 */
-         vuint32_t  PD7:1;             /* Power Status for Power Domain 7 */
-         vuint32_t  PD6:1;             /* Power Status for Power Domain 6 */
-         vuint32_t  PD5:1;             /* Power Status for Power Domain 5 */
-         vuint32_t  PD4:1;             /* Power Status for Power Domain 4 */
-         vuint32_t  PD3:1;             /* Power Status for Power Domain 3 */
-         vuint32_t  PD2:1;             /* Power Status for Power Domain 2 */
-         vuint32_t  PD1:1;             /* Power Status for Power Domain 1 */
-         vuint32_t  PD0:1;             /* Power Status for Power Domain 0 */
-      } B;
-   } PCU_PSTAT_32B_tag;
-
-
-
-   typedef struct PCU_struct_tag { /* start of PCU_tag */
-      union {
-       /* PCU_PCONF[0..15] -  Power Domain #0..#15 Configuration Register */
-         PCU_PCONF_32B_tag PCONF[16];      /* offset: 0x0000  (0x0004 x 16) */
-
-         struct {
-       /* PCU_PCONF[0..15] -  Power Domain #0..#15 Configuration Register */
-            PCU_PCONF_32B_tag PCONF0;      /* offset: 0x0000 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF1;      /* offset: 0x0004 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF2;      /* offset: 0x0008 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF3;      /* offset: 0x000C size: 32 bit */
-            PCU_PCONF_32B_tag PCONF4;      /* offset: 0x0010 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF5;      /* offset: 0x0014 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF6;      /* offset: 0x0018 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF7;      /* offset: 0x001C size: 32 bit */
-            PCU_PCONF_32B_tag PCONF8;      /* offset: 0x0020 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF9;      /* offset: 0x0024 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF10;     /* offset: 0x0028 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF11;     /* offset: 0x002C size: 32 bit */
-            PCU_PCONF_32B_tag PCONF12;     /* offset: 0x0030 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF13;     /* offset: 0x0034 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF14;     /* offset: 0x0038 size: 32 bit */
-            PCU_PCONF_32B_tag PCONF15;     /* offset: 0x003C size: 32 bit */
-         };
-
-      };
-                             /* PCU_PSTAT - Power Domain Status Register */
-      PCU_PSTAT_32B_tag PSTAT;             /* offset: 0x0040 size: 32 bit */
-   } PCU_tag;
-
-
-#define PCU   (*(volatile PCU_tag *) 0xC3FE8000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: PMUCTRL  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* PMUCTRL_STATHVD - PMU Status Register HVD */
-      vuint32_t R;
-      struct {
-         vuint32_t:11;
-         vuint32_t  HVDT_LPB:5;        /* High Voltage Detector trimming bits LPB bus */
-         vuint32_t:6;
-         vuint32_t  HVD_M:1;           /* High Voltage Detector Main */
-         vuint32_t  HVD_B:1;           /* High Voltage Detector Backup */
-         vuint32_t:4;
-         vuint32_t  HVD_LP:4;          /* High Voltage Detector trimming bits LP bus */
-      } B;
-   } PMUCTRL_STATHVD_32B_tag;
-
-   typedef union {   /* PMUCTRL_STATLVD - PMU Status Register LVD */
-      vuint32_t R;
-      struct {
-         vuint32_t:11;
-         vuint32_t  LVDT_LPB:5;        /* Ligh Voltage Detector trimming bits LPB bus */
-         vuint32_t:6;
-         vuint32_t  LVD_M:1;           /* Ligh Voltage Detector Main */
-         vuint32_t  LVD_B:1;           /* Ligh Voltage Detector Backup */
-         vuint32_t:4;
-         vuint32_t  LVD_LP:4;          /* Ligh Voltage Detector trimming bits LP bus */
-      } B;
-   } PMUCTRL_STATLVD_32B_tag;
-
-   typedef union {   /* PMUCTRL_STATIREG - PMU Status Register IREG */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-         vuint32_t  IIREG_HP:4;        /* Internal ballast REGulator hpreg1 trimming bits */
-      } B;
-   } PMUCTRL_STATIREG_32B_tag;
-
-   typedef union {   /* PMUCTRL_STATEREG - PMU Status Register EREG */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-         vuint32_t  EEREG_HP:4;        /* Internal ballast REGulator hpreg1 trimming bits */
-      } B;
-   } PMUCTRL_STATEREG_32B_tag;
-
-   typedef union {   /* PMUCTRL_STATUS - PMU Status Register STATUS */
-      vuint32_t R;
-      struct {
-         vuint32_t  EBMM:1;            /* External Ballast Management Mode */
-         vuint32_t  AEBD:1;            /* Automatic External Ballast Detection */
-         vuint32_t  ENPN:1;            /* External NPN status flag */
-         vuint32_t:13;
-         vuint32_t  CTB:2;             /* Configuration Trace Bits */
-         vuint32_t:6;
-         vuint32_t  CBS:4;             /* Current BIST Status */
-         vuint32_t  CPCS:4;            /* Current Pmu Configuration Status */
-      } B;
-   } PMUCTRL_STATUS_32B_tag;
-
-   typedef union {   /* PMUCTRL_CTRL - PMU Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:30;
-         vuint32_t  SILHT:2;           /* Start Idle or LVD or HVD BIST Test */
-      } B;
-   } PMUCTRL_CTRL_32B_tag;
-
-   typedef union {   /* PMUCTRL_MASKF - PMU Mask Fault Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  MF_BB:4;           /* Mask Fault Bypass Balast */
-         vuint32_t:28;
-      } B;
-   } PMUCTRL_MASKF_32B_tag;
-
-   typedef union {   /* PMUCTRL_FAULT - PMU Fault Monitor Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  BB_LV:4;           /* Bypass Ballast Low Voltage */
-         vuint32_t:9;
-         vuint32_t  FLNCF:1;           /* FLash voltage monitor Non Critical Fault */
-         vuint32_t  IONCF:1;           /* IO voltage monitor Non Critical Fault */
-         vuint32_t  RENCF:1;           /* REgulator voltage monitor Non Critical Fault */
-         vuint32_t:13;
-         vuint32_t  LHCF:1;            /* Low High voltage detector Critical Fault */
-         vuint32_t  LNCF:1;            /* Low  voltage detector Non Critical Fault */
-         vuint32_t  HNCF:1;            /* High voltage detector Non Critical Fault */
-      } B;
-   } PMUCTRL_FAULT_32B_tag;
-
-   typedef union {   /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:10;
-         vuint32_t  MFVMP:1;           /* Main   Flash     Voltage Monitor interrupt Pending */
-         vuint32_t  BFVMP:1;           /* Backup Flash     Voltage Monitor interrupt Pending */
-         vuint32_t  MIVMP:1;           /* MAin   IO        Voltage Monitor interrupt Pending */
-         vuint32_t  BIVMP:1;           /* Backup IO        Voltage Monitor interrupt Pending */
-         vuint32_t  MRVMP:1;           /* Main   Regulator Voltage Monitor interrupt Pending */
-         vuint32_t  BRVMP:1;           /* Backup Regulator Voltage Monitor interrupt Pending */
-         vuint32_t:12;
-         vuint32_t  MLVDP:1;           /* Main   Low  Voltage Detector error interrupt Pending */
-         vuint32_t  BLVDP:1;           /* Backup Low  Voltage Detector error interrupt Pending */
-         vuint32_t  MHVDP:1;           /* Main   High Voltage Detector error interrupt Pending */
-         vuint32_t  BHVDP:1;           /* Backup High Voltage Detector error interrupt Pending */
-      } B;
-   } PMUCTRL_IRQS_32B_tag;
-
-   typedef union {   /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:10;
-         vuint32_t  MFVME:1;           /* Main   Flash     Voltage Monitor interrupt Enable */
-         vuint32_t  BFVME:1;           /* Backup Flash     Voltage Monitor interrupt Enable */
-         vuint32_t  MIVME:1;           /* MAin   IO        Voltage Monitor interrupt Enable */
-         vuint32_t  BIVME:1;           /* Backup IO        Voltage Monitor interrupt Enable */
-         vuint32_t  MRVME:1;           /* Main   Regulator Voltage Monitor interrupt Enable */
-         vuint32_t  BRVME:1;           /* Backup Regulator Voltage Monitor interrupt Enable */
-         vuint32_t:12;
-         vuint32_t  MLVDE:1;           /* Main   Low  Voltage Detector error interrupt Enable */
-         vuint32_t  BLVDE:1;           /* Backup Low  Voltage Detector error interrupt Enable */
-         vuint32_t  MHVDE:1;           /* Main   High Voltage Detector error interrupt Enable */
-         vuint32_t  BHVDE:1;           /* Backup High Voltage Detector error interrupt Enable */
-      } B;
-   } PMUCTRL_IRQE_32B_tag;
-
-
-
-   typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */
-      int8_t PMUCTRL_reserved_0000[4];
-                            /* PMUCTRL_STATHVD - PMU Status Register HVD */
-      PMUCTRL_STATHVD_32B_tag STATHVD;     /* offset: 0x0004 size: 32 bit */
-                            /* PMUCTRL_STATLVD - PMU Status Register LVD */
-      PMUCTRL_STATLVD_32B_tag STATLVD;     /* offset: 0x0008 size: 32 bit */
-      int8_t PMUCTRL_reserved_000C[20];
-                          /* PMUCTRL_STATIREG - PMU Status Register IREG */
-      PMUCTRL_STATIREG_32B_tag STATIREG;   /* offset: 0x0020 size: 32 bit */
-                          /* PMUCTRL_STATEREG - PMU Status Register EREG */
-      PMUCTRL_STATEREG_32B_tag STATEREG;   /* offset: 0x0024 size: 32 bit */
-      int8_t PMUCTRL_reserved_0028[24];
-                          /* PMUCTRL_STATUS - PMU Status Register STATUS */
-      PMUCTRL_STATUS_32B_tag STATUS;       /* offset: 0x0040 size: 32 bit */
-                                  /* PMUCTRL_CTRL - PMU Control Register */
-      PMUCTRL_CTRL_32B_tag CTRL;           /* offset: 0x0044 size: 32 bit */
-      int8_t PMUCTRL_reserved_0048[40];
-                              /* PMUCTRL_MASKF - PMU Mask Fault Register */
-      PMUCTRL_MASKF_32B_tag MASKF;         /* offset: 0x0070 size: 32 bit */
-                           /* PMUCTRL_FAULT - PMU Fault Monitor Register */
-      PMUCTRL_FAULT_32B_tag FAULT;         /* offset: 0x0074 size: 32 bit */
-                 /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
-      PMUCTRL_IRQS_32B_tag IRQS;           /* offset: 0x0078 size: 32 bit */
-                 /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
-      PMUCTRL_IRQE_32B_tag IRQE;           /* offset: 0x007C size: 32 bit */
-   } PMUCTRL_tag;
-
-
-#define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: PIT_RTI  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* PIT_RTI_PITMCR - PIT Module Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:30;
-         vuint32_t  MDIS:1;            /* Module Disable. Disable the module clock */
-         vuint32_t  FRZ:1;             /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */
-      } B;
-   } PIT_RTI_PITMCR_32B_tag;
-
-
-   /* Register layout for all registers LDVAL... */
-
-   typedef union {   /* PIT_RTI_LDVAL - Timer Load Value Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  TSV:32;            /* Time Start Value Bits */
-      } B;
-   } PIT_RTI_LDVAL_32B_tag;
-
-
-   /* Register layout for all registers CVAL... */
-
-   typedef union {   /* PIT_RTI_CVAL - Current Timer Value Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  TVL:32;            /* Current Timer Value Bits */
-      } B;
-   } PIT_RTI_CVAL_32B_tag;
-
-
-   /* Register layout for all registers TCTRL... */
-
-   typedef union {   /* PIT_RTI_TCTRL - Timer Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:30;
-         vuint32_t  TIE:1;             /* Timer Interrupt Enable Bit */
-         vuint32_t  TEN:1;             /* Timer Enable Bit */
-      } B;
-   } PIT_RTI_TCTRL_32B_tag;
-
-
-   /* Register layout for all registers TFLG... */
-
-   typedef union {   /* PIT_RTI_TFLG - Timer Flag Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:31;
-         vuint32_t  TIF:1;             /* Timer Interrupt Flag Bit */
-      } B;
-   } PIT_RTI_TFLG_32B_tag;
-
-
-   typedef struct PIT_RTI_CHANNEL_struct_tag {
-
-                            /* PIT_RTI_LDVAL - Timer Load Value Register */
-      PIT_RTI_LDVAL_32B_tag LDVAL;        /* relative offset: 0x0000 */
-                          /* PIT_RTI_CVAL - Current Timer Value Register */
-      PIT_RTI_CVAL_32B_tag CVAL;          /* relative offset: 0x0004 */
-                               /* PIT_RTI_TCTRL - Timer Control Register */
-      PIT_RTI_TCTRL_32B_tag TCTRL;        /* relative offset: 0x0008 */
-                                   /* PIT_RTI_TFLG - Timer Flag Register */
-      PIT_RTI_TFLG_32B_tag TFLG;          /* relative offset: 0x000C */
-
-   } PIT_RTI_CHANNEL_tag;
-
-
-   typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */
-                         /* PIT_RTI_PITMCR - PIT Module Control Register */
-      PIT_RTI_PITMCR_32B_tag PITMCR;       /* offset: 0x0000 size: 32 bit */
-      int8_t PIT_RTI_reserved_0004_C[252];
-      union {
-                                                /*  Register set CHANNEL */
-         PIT_RTI_CHANNEL_tag CHANNEL[4];   /* offset: 0x0100  (0x0010 x 4) */
-
-         struct {
-                            /* PIT_RTI_LDVAL - Timer Load Value Register */
-            PIT_RTI_LDVAL_32B_tag LDVAL0;  /* offset: 0x0100 size: 32 bit */
-                          /* PIT_RTI_CVAL - Current Timer Value Register */
-            PIT_RTI_CVAL_32B_tag CVAL0;    /* offset: 0x0104 size: 32 bit */
-                               /* PIT_RTI_TCTRL - Timer Control Register */
-            PIT_RTI_TCTRL_32B_tag TCTRL0;  /* offset: 0x0108 size: 32 bit */
-                                   /* PIT_RTI_TFLG - Timer Flag Register */
-            PIT_RTI_TFLG_32B_tag TFLG0;    /* offset: 0x010C size: 32 bit */
-                            /* PIT_RTI_LDVAL - Timer Load Value Register */
-            PIT_RTI_LDVAL_32B_tag LDVAL1;  /* offset: 0x0110 size: 32 bit */
-                          /* PIT_RTI_CVAL - Current Timer Value Register */
-            PIT_RTI_CVAL_32B_tag CVAL1;    /* offset: 0x0114 size: 32 bit */
-                               /* PIT_RTI_TCTRL - Timer Control Register */
-            PIT_RTI_TCTRL_32B_tag TCTRL1;  /* offset: 0x0118 size: 32 bit */
-                                   /* PIT_RTI_TFLG - Timer Flag Register */
-            PIT_RTI_TFLG_32B_tag TFLG1;    /* offset: 0x011C size: 32 bit */
-                            /* PIT_RTI_LDVAL - Timer Load Value Register */
-            PIT_RTI_LDVAL_32B_tag LDVAL2;  /* offset: 0x0120 size: 32 bit */
-                          /* PIT_RTI_CVAL - Current Timer Value Register */
-            PIT_RTI_CVAL_32B_tag CVAL2;    /* offset: 0x0124 size: 32 bit */
-                               /* PIT_RTI_TCTRL - Timer Control Register */
-            PIT_RTI_TCTRL_32B_tag TCTRL2;  /* offset: 0x0128 size: 32 bit */
-                                   /* PIT_RTI_TFLG - Timer Flag Register */
-            PIT_RTI_TFLG_32B_tag TFLG2;    /* offset: 0x012C size: 32 bit */
-                            /* PIT_RTI_LDVAL - Timer Load Value Register */
-            PIT_RTI_LDVAL_32B_tag LDVAL3;  /* offset: 0x0130 size: 32 bit */
-                          /* PIT_RTI_CVAL - Current Timer Value Register */
-            PIT_RTI_CVAL_32B_tag CVAL3;    /* offset: 0x0134 size: 32 bit */
-                               /* PIT_RTI_TCTRL - Timer Control Register */
-            PIT_RTI_TCTRL_32B_tag TCTRL3;  /* offset: 0x0138 size: 32 bit */
-                                   /* PIT_RTI_TFLG - Timer Flag Register */
-            PIT_RTI_TFLG_32B_tag TFLG3;    /* offset: 0x013C size: 32 bit */
-         };
-
-      };
-   } PIT_RTI_tag;
-
-
-#define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: ADC  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* module configuration register */
-      vuint32_t R;
-      struct {
-         vuint32_t  OWREN:1;           /* Overwrite enable */
-         vuint32_t  WLSIDE:1;          /* Write Left/right Alligned */
-         vuint32_t  MODE:1;            /* One Shot/Scan Mode Selectiom */
-         vuint32_t  EDGLEV:1;          /* edge or level selection for external start trigger */
-         vuint32_t  TRGEN:1;           /* external trigger enable */
-         vuint32_t  EDGE:1;            /* start trigger egde /level detection */
-         vuint32_t  XSTRTEN:1;         /* EXTERNAL START ENABLE */
-         vuint32_t  NSTART:1;          /* start normal conversion */
-         vuint32_t:1;
-         vuint32_t  JTRGEN:1;          /* Injectin External Trigger Enable */
-         vuint32_t  JEDGE:1;           /* start trigger egde /level detection for injected */
-         vuint32_t  JSTART:1;          /* injected conversion start */
-         vuint32_t:2;
-         vuint32_t  CTUEN:1;           /* CTU enabaled */
-         vuint32_t:8;
-         vuint32_t  ADCLKSEL:1;        /* Select which clock for device */
-         vuint32_t  ABORTCHAIN:1;      /* abort chain conversion */
-         vuint32_t  ABORT:1;           /* abort current conversion */
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  ACKO:1;            /* Auto Clock Off Enable */
-#else
-         vuint32_t  ACK0:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t  OFFREFRESH:1;      /* offset phase selection */
-         vuint32_t  OFFCANC:1;         /* offset phase cancellation selection */
-         vuint32_t:2;
-         vuint32_t  PWDN:1;            /* Power Down Enable */
-      } B;
-   } ADC_MCR_32B_tag;
-
-   typedef union {   /* module status register */
-      vuint32_t R;
-      struct {
-         vuint32_t:7;
-         vuint32_t  NSTART:1;          /* normal conversion status */
-         vuint32_t  JABORT:1;          /* Injection chain abort status */
-         vuint32_t:2;
-         vuint32_t  JSTART:1;          /* Injection Start status */
-         vuint32_t:3;
-         vuint32_t  CTUSTART:1;        /* ctu start status */
-         vuint32_t  CHADDR:7;          /* which address conv is goin on */
-         vuint32_t:3;
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  ACKO:1;            /* Auto Clock Off Enable status */
-#else
-         vuint32_t  ACK0:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t  OFFREFRESH:1;      /* offset refresh status */
-         vuint32_t  OFFCANC:1;         /* offset phase cancellation status */
-         vuint32_t  ADCSTATUS:3;       /* status of ADC FSM */
-      } B;
-   } ADC_MSR_32B_tag;
-
-   typedef union {   /* Interrupt status register */
-      vuint32_t R;
-      struct {
-         vuint32_t:25;
-         vuint32_t  OFFCANCOVR:1;      /* Offset cancellation phase over */
-         vuint32_t  EOFFSET:1;         /* error in offset refresh */
-         vuint32_t  EOCTU:1;           /* end of CTU channel conversion */
-         vuint32_t  JEOC:1;            /* end of injected channel conversion */
-         vuint32_t  JECH:1;            /* end ofinjected chain conversion */
-         vuint32_t  EOC:1;             /* end of channel conversion */
-         vuint32_t  ECH:1;             /* end of chain conversion */
-      } B;
-   } ADC_ISR_32B_tag;
-
-   typedef union {   /* CHANNEL PENDING REGISTER 0 */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH31:1;        /* Channel 31 conversion over */
-#else
-         vuint32_t  EOC31:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH30:1;        /* Channel 30 conversion over */
-#else
-         vuint32_t  EOC30:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH29:1;        /* Channel 29 conversion over */
-#else
-         vuint32_t  EOC29:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH28:1;        /* Channel 28 conversion over */
-#else
-         vuint32_t  EOC28:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH27:1;        /* Channel 27 conversion over */
-#else
-         vuint32_t  EOC27:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH26:1;        /* Channel 26 conversion over */
-#else
-         vuint32_t  EOC26:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH25:1;        /* Channel 25 conversion over */
-#else
-         vuint32_t  EOC25:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH24:1;        /* Channel 24 conversion over */
-#else
-         vuint32_t  EOC24:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH23:1;        /* Channel 23 conversion over */
-#else
-         vuint32_t  EOC23:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH22:1;        /* Channel 22 conversion over */
-#else
-         vuint32_t  EOC22:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH21:1;        /* Channel 21 conversion over */
-#else
-         vuint32_t  EOC21:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH20:1;        /* Channel 20 conversion over */
-#else
-         vuint32_t  EOC20:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH19:1;        /* Channel 19 conversion over */
-#else
-         vuint32_t  EOC19:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH18:1;        /* Channel 18 conversion over */
-#else
-         vuint32_t  EOC18:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH17:1;        /* Channel 17 conversion over */
-#else
-         vuint32_t  EOC17:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH16:1;        /* Channel 16 conversion over */
-#else
-         vuint32_t  EOC16:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH15:1;        /* Channel 15 conversion over */
-#else
-         vuint32_t  EOC15:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH14:1;        /* Channel 14 conversion over */
-#else
-         vuint32_t  EOC14:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH13:1;        /* Channel 13 conversion over */
-#else
-         vuint32_t  EOC13:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH12:1;        /* Channel 12 conversion over */
-#else
-         vuint32_t  EOC12:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH11:1;        /* Channel 11 conversion over */
-#else
-         vuint32_t  EOC11:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH10:1;        /* Channel 10 conversion over */
-#else
-         vuint32_t  EOC10:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH9:1;         /* Channel 9 conversion over */
-#else
-         vuint32_t  EOC9:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH8:1;         /* Channel 8 conversion over */
-#else
-         vuint32_t  EOC8:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH7:1;         /* Channel 7 conversion over */
-#else
-         vuint32_t  EOC7:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH6:1;         /* Channel 6 conversion over */
-#else
-         vuint32_t  EOC6:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH5:1;         /* Channel 5 conversion over */
-#else
-         vuint32_t  EOC5:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH4:1;         /* Channel 4 conversion over */
-#else
-         vuint32_t  EOC4:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH3:1;         /* Channel 3 conversion over */
-#else
-         vuint32_t  EOC3:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH2:1;         /* Channel 2 conversion over */
-#else
-         vuint32_t  EOC2:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH1:1;         /* Channel 1 conversion over */
-#else
-         vuint32_t  EOC1:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  EOC_CH0:1;         /* Channel 0 conversion over */
-#else
-         vuint32_t  EOC0:1;              /* deprecated name - please avoid */
-#endif
-      } B;
-   } ADC_CEOCFR0_32B_tag;
-
-   typedef union {   /* CHANNEL PENDING REGISTER 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  EOC_CH63:1;        /* Channel 63 conversion over */
-         vuint32_t  EOC_CH62:1;        /* Channel 62 conversion over */
-         vuint32_t  EOC_CH61:1;        /* Channel 61 conversion over */
-         vuint32_t  EOC_CH60:1;        /* Channel 60 conversion over */
-         vuint32_t  EOC_CH59:1;        /* Channel 59 conversion over */
-         vuint32_t  EOC_CH58:1;        /* Channel 58 conversion over */
-         vuint32_t  EOC_CH57:1;        /* Channel 57 conversion over */
-         vuint32_t  EOC_CH56:1;        /* Channel 56 conversion over */
-         vuint32_t  EOC_CH55:1;        /* Channel 55 conversion over */
-         vuint32_t  EOC_CH54:1;        /* Channel 54 conversion over */
-         vuint32_t  EOC_CH53:1;        /* Channel 53 conversion over */
-         vuint32_t  EOC_CH52:1;        /* Channel 52 conversion over */
-         vuint32_t  EOC_CH51:1;        /* Channel 51 conversion over */
-         vuint32_t  EOC_CH50:1;        /* Channel 50 conversion over */
-         vuint32_t  EOC_CH49:1;        /* Channel 49 conversion over */
-         vuint32_t  EOC_CH48:1;        /* Channel 48 conversion over */
-         vuint32_t  EOC_CH47:1;        /* Channel 47 conversion over */
-         vuint32_t  EOC_CH46:1;        /* Channel 46 conversion over */
-         vuint32_t  EOC_CH45:1;        /* Channel 45 conversion over */
-         vuint32_t  EOC_CH44:1;        /* Channel 44 conversion over */
-         vuint32_t  EOC_CH43:1;        /* Channel 43 conversion over */
-         vuint32_t  EOC_CH42:1;        /* Channel 42 conversion over */
-         vuint32_t  EOC_CH41:1;        /* Channel 41 conversion over */
-         vuint32_t  EOC_CH40:1;        /* Channel 40 conversion over */
-         vuint32_t  EOC_CH39:1;        /* Channel 39 conversion over */
-         vuint32_t  EOC_CH38:1;        /* Channel 38 conversion over */
-         vuint32_t  EOC_CH37:1;        /* Channel 37 conversion over */
-         vuint32_t  EOC_CH36:1;        /* Channel 36 conversion over */
-         vuint32_t  EOC_CH35:1;        /* Channel 35 conversion over */
-         vuint32_t  EOC_CH34:1;        /* Channel 34 conversion over */
-         vuint32_t  EOC_CH33:1;        /* Channel 33 conversion over */
-         vuint32_t  EOC_CH32:1;        /* Channel 32 conversion over */
-      } B;
-   } ADC_CEOCFR1_32B_tag;
-
-   typedef union {   /* CHANNEL PENDING REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  EOC_CH95:1;        /* Channel 95 conversion over */
-         vuint32_t  EOC_CH94:1;        /* Channel 94 conversion over */
-         vuint32_t  EOC_CH93:1;        /* Channel 93 conversion over */
-         vuint32_t  EOC_CH92:1;        /* Channel 92 conversion over */
-         vuint32_t  EOC_CH91:1;        /* Channel 91 conversion over */
-         vuint32_t  EOC_CH90:1;        /* Channel 90 conversion over */
-         vuint32_t  EOC_CH89:1;        /* Channel 89 conversion over */
-         vuint32_t  EOC_CH88:1;        /* Channel 88 conversion over */
-         vuint32_t  EOC_CH87:1;        /* Channel 87 conversion over */
-         vuint32_t  EOC_CH86:1;        /* Channel 86 conversion over */
-         vuint32_t  EOC_CH85:1;        /* Channel 85 conversion over */
-         vuint32_t  EOC_CH84:1;        /* Channel 84 conversion over */
-         vuint32_t  EOC_CH83:1;        /* Channel 83 conversion over */
-         vuint32_t  EOC_CH82:1;        /* Channel 82 conversion over */
-         vuint32_t  EOC_CH81:1;        /* Channel 81 conversion over */
-         vuint32_t  EOC_CH80:1;        /* Channel 80 conversion over */
-         vuint32_t  EOC_CH79:1;        /* Channel 79 conversion over */
-         vuint32_t  EOC_CH78:1;        /* Channel 78 conversion over */
-         vuint32_t  EOC_CH77:1;        /* Channel 77 conversion over */
-         vuint32_t  EOC_CH76:1;        /* Channel 76 conversion over */
-         vuint32_t  EOC_CH75:1;        /* Channel 75 conversion over */
-         vuint32_t  EOC_CH74:1;        /* Channel 74 conversion over */
-         vuint32_t  EOC_CH73:1;        /* Channel 73 conversion over */
-         vuint32_t  EOC_CH72:1;        /* Channel 72 conversion over */
-         vuint32_t  EOC_CH71:1;        /* Channel 71 conversion over */
-         vuint32_t  EOC_CH70:1;        /* Channel 70 conversion over */
-         vuint32_t  EOC_CH69:1;        /* Channel 69 conversion over */
-         vuint32_t  EOC_CH68:1;        /* Channel 68 conversion over */
-         vuint32_t  EOC_CH67:1;        /* Channel 67 conversion over */
-         vuint32_t  EOC_CH66:1;        /* Channel 66 conversion over */
-         vuint32_t  EOC_CH65:1;        /* Channel 65 conversion over */
-         vuint32_t  EOC_CH64:1;        /* Channel 64 conversion over */
-      } B;
-   } ADC_CEOCFR2_32B_tag;
-
-   typedef union {   /* interrupt mask register */
-      vuint32_t R;
-      struct {
-         vuint32_t:25;
-         vuint32_t  MSKOFFCANCOVR:1;   /* mask bit for Calibration over */
-         vuint32_t  MSKEOFFSET:1;      /* mask bit for Error in offset refresh */
-         vuint32_t  MSKEOCTU:1;        /* mask bit for EOCTU */
-         vuint32_t  MSKJEOC:1;         /* mask bit for JEOC */
-         vuint32_t  MSKJECH:1;         /* mask bit for JECH */
-         vuint32_t  MSKEOC:1;          /* mask bit for EOC */
-         vuint32_t  MSKECH:1;          /* mask bit for ECH */
-      } B;
-   } ADC_IMR_32B_tag;
-
-   typedef union {   /* CHANNEL INTERRUPT MASK REGISTER 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CIM31:1;           /* Channel 31 mask register */
-         vuint32_t  CIM30:1;           /* Channel 30 mask register */
-         vuint32_t  CIM29:1;           /* Channel 29 mask register */
-         vuint32_t  CIM28:1;           /* Channel 28 mask register */
-         vuint32_t  CIM27:1;           /* Channel 27 mask register */
-         vuint32_t  CIM26:1;           /* Channel 26 mask register */
-         vuint32_t  CIM25:1;           /* Channel 25 mask register */
-         vuint32_t  CIM24:1;           /* Channel 24 mask register */
-         vuint32_t  CIM23:1;           /* Channel 23 mask register */
-         vuint32_t  CIM22:1;           /* Channel 22 mask register */
-         vuint32_t  CIM21:1;           /* Channel 21 mask register */
-         vuint32_t  CIM20:1;           /* Channel 20 mask register */
-         vuint32_t  CIM19:1;           /* Channel 19 mask register */
-         vuint32_t  CIM18:1;           /* Channel 18 mask register */
-         vuint32_t  CIM17:1;           /* Channel 17 mask register */
-         vuint32_t  CIM16:1;           /* Channel 16 mask register */
-         vuint32_t  CIM15:1;           /* Channel 15 mask register */
-         vuint32_t  CIM14:1;           /* Channel 14 mask register */
-         vuint32_t  CIM13:1;           /* Channel 13 mask register */
-         vuint32_t  CIM12:1;           /* Channel 12 mask register */
-         vuint32_t  CIM11:1;           /* Channel 11 mask register */
-         vuint32_t  CIM10:1;           /* Channel 10 mask register */
-         vuint32_t  CIM9:1;            /* Channel 9  mask register */
-         vuint32_t  CIM8:1;            /* Channel 8  mask register */
-         vuint32_t  CIM7:1;            /* Channel 7  mask register */
-         vuint32_t  CIM6:1;            /* Channel 6  mask register */
-         vuint32_t  CIM5:1;            /* Channel 5  mask register */
-         vuint32_t  CIM4:1;            /* Channel 4  mask register */
-         vuint32_t  CIM3:1;            /* Channel 3  mask register */
-         vuint32_t  CIM2:1;            /* Channel 2  mask register */
-         vuint32_t  CIM1:1;            /* Channel 1  mask register */
-         vuint32_t  CIM0:1;            /* Channel 0  mask register */
-      } B;
-   } ADC_CIMR0_32B_tag;
-
-   typedef union {   /* CHANNEL INTERRUPT MASK REGISTER 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CIM63:1;           /* Channel 63 mask register */
-         vuint32_t  CIM62:1;           /* Channel 62 mask register */
-         vuint32_t  CIM61:1;           /* Channel 61 mask register */
-         vuint32_t  CIM60:1;           /* Channel 60 mask register */
-         vuint32_t  CIM59:1;           /* Channel 59 mask register */
-         vuint32_t  CIM58:1;           /* Channel 58 mask register */
-         vuint32_t  CIM57:1;           /* Channel 57 mask register */
-         vuint32_t  CIM56:1;           /* Channel 56 mask register */
-         vuint32_t  CIM55:1;           /* Channel 55 mask register */
-         vuint32_t  CIM54:1;           /* Channel 54 mask register */
-         vuint32_t  CIM53:1;           /* Channel 53 mask register */
-         vuint32_t  CIM52:1;           /* Channel 52 mask register */
-         vuint32_t  CIM51:1;           /* Channel 51 mask register */
-         vuint32_t  CIM50:1;           /* Channel 50 mask register */
-         vuint32_t  CIM49:1;           /* Channel 49 mask register */
-         vuint32_t  CIM48:1;           /* Channel 48 mask register */
-         vuint32_t  CIM47:1;           /* Channel 47 mask register */
-         vuint32_t  CIM46:1;           /* Channel 46 mask register */
-         vuint32_t  CIM45:1;           /* Channel 45 mask register */
-         vuint32_t  CIM44:1;           /* Channel 44 mask register */
-         vuint32_t  CIM43:1;           /* Channel 43 mask register */
-         vuint32_t  CIM42:1;           /* Channel 42 mask register */
-         vuint32_t  CIM41:1;           /* Channel 41 mask register */
-         vuint32_t  CIM40:1;           /* Channel 40 mask register */
-         vuint32_t  CIM39:1;           /* Channel 39 mask register */
-         vuint32_t  CIM38:1;           /* Channel 38 mask register */
-         vuint32_t  CIM37:1;           /* Channel 37 mask register */
-         vuint32_t  CIM36:1;           /* Channel 36 mask register */
-         vuint32_t  CIM35:1;           /* Channel 35 mask register */
-         vuint32_t  CIM34:1;           /* Channel 34 mask register */
-         vuint32_t  CIM33:1;           /* Channel 33 mask register */
-         vuint32_t  CIM32:1;           /* Channel 32 mask register */
-      } B;
-   } ADC_CIMR1_32B_tag;
-
-   typedef union {   /* CHANNEL INTERRUPT MASK REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CIM95:1;           /* Channel 95 mask register */
-         vuint32_t  CIM94:1;           /* Channel 94 mask register */
-         vuint32_t  CIM93:1;           /* Channel 93 mask register */
-         vuint32_t  CIM92:1;           /* Channel 92 mask register */
-         vuint32_t  CIM91:1;           /* Channel 91 mask register */
-         vuint32_t  CIM90:1;           /* Channel 90 mask register */
-         vuint32_t  CIM89:1;           /* Channel 89 mask register */
-         vuint32_t  CIM88:1;           /* Channel 88 mask register */
-         vuint32_t  CIM87:1;           /* Channel 87 mask register */
-         vuint32_t  CIM86:1;           /* Channel 86 mask register */
-         vuint32_t  CIM85:1;           /* Channel 85 mask register */
-         vuint32_t  CIM84:1;           /* Channel 84 mask register */
-         vuint32_t  CIM83:1;           /* Channel 83 mask register */
-         vuint32_t  CIM82:1;           /* Channel 82 mask register */
-         vuint32_t  CIM81:1;           /* Channel 81 mask register */
-         vuint32_t  CIM80:1;           /* Channel 80 mask register */
-         vuint32_t  CIM79:1;           /* Channel 79 mask register */
-         vuint32_t  CIM78:1;           /* Channel 78 mask register */
-         vuint32_t  CIM77:1;           /* Channel 77 mask register */
-         vuint32_t  CIM76:1;           /* Channel 76 mask register */
-         vuint32_t  CIM75:1;           /* Channel 75 mask register */
-         vuint32_t  CIM74:1;           /* Channel 74 mask register */
-         vuint32_t  CIM73:1;           /* Channel 73 mask register */
-         vuint32_t  CIM72:1;           /* Channel 72 mask register */
-         vuint32_t  CIM71:1;           /* Channel 71 mask register */
-         vuint32_t  CIM70:1;           /* Channel 70 mask register */
-         vuint32_t  CIM69:1;           /* Channel 69 mask register */
-         vuint32_t  CIM68:1;           /* Channel 68 mask register */
-         vuint32_t  CIM67:1;           /* Channel 67 mask register */
-         vuint32_t  CIM66:1;           /* Channel 66 mask register */
-         vuint32_t  CIM65:1;           /* Channel 65 mask register */
-         vuint32_t  CIM64:1;           /* Channel 64 mask register */
-      } B;
-   } ADC_CIMR2_32B_tag;
-
-   typedef union {   /* Watchdog Threshold interrupt status register */
-      vuint32_t R;
-      struct {
-         vuint32_t:24;
-         vuint32_t  WDG3H:1;           /* Interrupt generated on the value being higher than the HTHV 3 */
-         vuint32_t  WDG2H:1;           /* Interrupt generated on the value being higher than the HTHV 2 */
-         vuint32_t  WDG1H:1;           /* Interrupt generated on the value being higher than the HTHV 1 */
-         vuint32_t  WDG0H:1;           /* Interrupt generated on the value being higher than the HTHV 0 */
-         vuint32_t  WDG3L:1;           /* Interrupt generated on the value being lower than the LTHV 3 */
-         vuint32_t  WDG2L:1;           /* Interrupt generated on the value being lower than the LTHV 2 */
-         vuint32_t  WDG1L:1;           /* Interrupt generated on the value being lower than the LTHV 1 */
-         vuint32_t  WDG0L:1;           /* Interrupt generated on the value being lower than the LTHV 0 */
-      } B;
-   } ADC_WTISR_32B_tag;
-
-   typedef union {   /* Watchdog interrupt MASK register */
-      vuint32_t R;
-      struct {
-         vuint32_t:24;
-         vuint32_t  MSKWDG3H:1;        /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */
-         vuint32_t  MSKWDG2H:1;        /* Mask enable for  Interrupt generated on the value being higher than the HTHV 2 */
-         vuint32_t  MSKWDG1H:1;        /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */
-         vuint32_t  MSKWDG0H:1;        /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */
-         vuint32_t  MSKWDG3L:1;        /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */
-         vuint32_t  MSKWDG2L:1;        /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */
-         vuint32_t  MSKWDG1L:1;        /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */
-         vuint32_t  MSKWDG0L:1;        /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */
-      } B;
-   } ADC_WTIMR_32B_tag;
-
-   typedef union {   /* DMAE register */
-      vuint32_t R;
-      struct {
-         vuint32_t:30;
-         vuint32_t  DCLR:1;            /* DMA clear sequence enable */
-         vuint32_t  DMAEN:1;           /* DMA global enable */
-      } B;
-   } ADC_DMAE_32B_tag;
-
-   typedef union {   /* DMA  REGISTER 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  DMA31:1;           /* Channel 31 DMA Enable */
-         vuint32_t  DMA30:1;           /* Channel 30 DMA Enable */
-         vuint32_t  DMA29:1;           /* Channel 29 DMA Enable */
-         vuint32_t  DMA28:1;           /* Channel 28 DMA Enable */
-         vuint32_t  DMA27:1;           /* Channel 27 DMA Enable */
-         vuint32_t  DMA26:1;           /* Channel 26 DMA Enable */
-         vuint32_t  DMA25:1;           /* Channel 25 DMA Enable */
-         vuint32_t  DMA24:1;           /* Channel 24 DMA Enable */
-         vuint32_t  DMA23:1;           /* Channel 23 DMA Enable */
-         vuint32_t  DMA22:1;           /* Channel 22 DMA Enable */
-         vuint32_t  DMA21:1;           /* Channel 21 DMA Enable */
-         vuint32_t  DMA20:1;           /* Channel 20 DMA Enable */
-         vuint32_t  DMA19:1;           /* Channel 19 DMA Enable */
-         vuint32_t  DMA18:1;           /* Channel 18 DMA Enable */
-         vuint32_t  DMA17:1;           /* Channel 17 DMA Enable */
-         vuint32_t  DMA16:1;           /* Channel 16 DMA Enable */
-         vuint32_t  DMA15:1;           /* Channel 15 DMA Enable */
-         vuint32_t  DMA14:1;           /* Channel 14 DMA Enable */
-         vuint32_t  DMA13:1;           /* Channel 13 DMA Enable */
-         vuint32_t  DMA12:1;           /* Channel 12 DMA Enable */
-         vuint32_t  DMA11:1;           /* Channel 11 DMA Enable */
-         vuint32_t  DMA10:1;           /* Channel 10 DMA Enable */
-         vuint32_t  DMA9:1;            /* Channel 9 DMA Enable */
-         vuint32_t  DMA8:1;            /* Channel 8 DMA Enable */
-         vuint32_t  DMA7:1;            /* Channel 7 DMA Enable */
-         vuint32_t  DMA6:1;            /* Channel 6 DMA Enable */
-         vuint32_t  DMA5:1;            /* Channel 5 DMA Enable */
-         vuint32_t  DMA4:1;            /* Channel 4 DMA Enable */
-         vuint32_t  DMA3:1;            /* Channel 3 DMA Enable */
-         vuint32_t  DMA2:1;            /* Channel 2 DMA Enable */
-         vuint32_t  DMA1:1;            /* Channel 1 DMA Enable */
-         vuint32_t  DMA0:1;            /* Channel 0 DMA Enable */
-      } B;
-   } ADC_DMAR0_32B_tag;
-
-   typedef union {   /* DMA REGISTER 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  DMA63:1;           /* Channel 63 DMA Enable */
-         vuint32_t  DMA62:1;           /* Channel 62 DMA Enable */
-         vuint32_t  DMA61:1;           /* Channel 61 DMA Enable */
-         vuint32_t  DMA60:1;           /* Channel 60 DMA Enable */
-         vuint32_t  DMA59:1;           /* Channel 59 DMA Enable */
-         vuint32_t  DMA58:1;           /* Channel 58 DMA Enable */
-         vuint32_t  DMA57:1;           /* Channel 57 DMA Enable */
-         vuint32_t  DMA56:1;           /* Channel 56 DMA Enable */
-         vuint32_t  DMA55:1;           /* Channel 55 DMA Enable */
-         vuint32_t  DMA54:1;           /* Channel 54 DMA Enable */
-         vuint32_t  DMA53:1;           /* Channel 53 DMA Enable */
-         vuint32_t  DMA52:1;           /* Channel 52 DMA Enable */
-         vuint32_t  DMA51:1;           /* Channel 51 DMA Enable */
-         vuint32_t  DMA50:1;           /* Channel 50 DMA Enable */
-         vuint32_t  DMA49:1;           /* Channel 49 DMA Enable */
-         vuint32_t  DMA48:1;           /* Channel 48 DMA Enable */
-         vuint32_t  DMA47:1;           /* Channel 47 DMA Enable */
-         vuint32_t  DMA46:1;           /* Channel 46 DMA Enable */
-         vuint32_t  DMA45:1;           /* Channel 45 DMA Enable */
-         vuint32_t  DMA44:1;           /* Channel 44 DMA Enable */
-         vuint32_t  DMA43:1;           /* Channel 43 DMA Enable */
-         vuint32_t  DMA42:1;           /* Channel 42 DMA Enable */
-         vuint32_t  DMA41:1;           /* Channel 41 DMA Enable */
-         vuint32_t  DMA40:1;           /* Channel 40 DMA Enable */
-         vuint32_t  DMA39:1;           /* Channel 39 DMA Enable */
-         vuint32_t  DMA38:1;           /* Channel 38 DMA Enable */
-         vuint32_t  DMA37:1;           /* Channel 37 DMA Enable */
-         vuint32_t  DMA36:1;           /* Channel 36 DMA Enable */
-         vuint32_t  DMA35:1;           /* Channel 35 DMA Enable */
-         vuint32_t  DMA34:1;           /* Channel 34 DMA Enable */
-         vuint32_t  DMA33:1;           /* Channel 33 DMA Enable */
-         vuint32_t  DMA32:1;           /* Channel 32 DMA Enable */
-      } B;
-   } ADC_DMAR1_32B_tag;
-
-   typedef union {   /* DMA REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  DMA95:1;           /* Channel 95 DMA Enable */
-         vuint32_t  DMA94:1;           /* Channel 94 DMA Enable */
-         vuint32_t  DMA93:1;           /* Channel 93 DMA Enable */
-         vuint32_t  DMA92:1;           /* Channel 92 DMA Enable */
-         vuint32_t  DMA91:1;           /* Channel 91 DMA Enable */
-         vuint32_t  DMA90:1;           /* Channel 90 DMA Enable */
-         vuint32_t  DMA89:1;           /* Channel 89 DMA Enable */
-         vuint32_t  DMA88:1;           /* Channel 88 DMA Enable */
-         vuint32_t  DMA87:1;           /* Channel 87 DMA Enable */
-         vuint32_t  DMA86:1;           /* Channel 86 DMA Enable */
-         vuint32_t  DMA85:1;           /* Channel 85 DMA Enable */
-         vuint32_t  DMA84:1;           /* Channel 84 DMA Enable */
-         vuint32_t  DMA83:1;           /* Channel 83 DMA Enable */
-         vuint32_t  DMA82:1;           /* Channel 82 DMA Enable */
-         vuint32_t  DMA81:1;           /* Channel 81 DMA Enable */
-         vuint32_t  DMA80:1;           /* Channel 80 DMA Enable */
-         vuint32_t  DMA79:1;           /* Channel 79 DMA Enable */
-         vuint32_t  DMA78:1;           /* Channel 78 DMA Enable */
-         vuint32_t  DMA77:1;           /* Channel 77 DMA Enable */
-         vuint32_t  DMA76:1;           /* Channel 76 DMA Enable */
-         vuint32_t  DMA75:1;           /* Channel 75 DMA Enable */
-         vuint32_t  DMA74:1;           /* Channel 74 DMA Enable */
-         vuint32_t  DMA73:1;           /* Channel 73 DMA Enable */
-         vuint32_t  DMA72:1;           /* Channel 72 DMA Enable */
-         vuint32_t  DMA71:1;           /* Channel 71 DMA Enable */
-         vuint32_t  DMA70:1;           /* Channel 70 DMA Enable */
-         vuint32_t  DMA69:1;           /* Channel 69 DMA Enable */
-         vuint32_t  DMA68:1;           /* Channel 68 DMA Enable */
-         vuint32_t  DMA67:1;           /* Channel 67 DMA Enable */
-         vuint32_t  DMA66:1;           /* Channel 66 DMA Enable */
-         vuint32_t  DMA65:1;           /* Channel 65 DMA Enable */
-         vuint32_t  DMA64:1;           /* Channel 64 DMA Enable */
-      } B;
-   } ADC_DMAR2_32B_tag;
-
-
-   /* Register layout for all registers TRC... */
-
-   typedef union {   /* Threshold Control register C */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  THREN:1;           /* Threshold enable */
-         vuint32_t  THRINV:1;          /* invert the output pin */
-         vuint32_t  THROP:1;           /* output pin register */
-         vuint32_t:6;
-         vuint32_t  THRCH:7;           /* Choose channel for threshold register */
-      } B;
-   } ADC_TRC_32B_tag;
-
-
-   /* Register layout for all registers THRHLR... */
-
-   typedef union {   /* Upper Threshold register */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR_32B_tag;
-
-
-   /* Register layout for all registers THRALT... */
-
-   typedef union {   /* alternate Upper Threshold register */
-      vuint32_t R;
-      struct {
-         vuint32_t:6;
-         vuint32_t  THRH:10;           /* high threshold value s */
-         vuint32_t:6;
-         vuint32_t  THRL:10;           /* low threshold value s */
-      } B;
-   } ADC_THRALT_32B_tag;
-
-   typedef union {   /* PRESAMPLING CONTROL REGISTER */
-      vuint32_t R;
-      struct {
-         vuint32_t:25;
-         vuint32_t  PREVAL2:2;         /* INternal Voltage selection for Presampling */
-         vuint32_t  PREVAL1:2;         /* INternal Voltage selection for Presampling */
-         vuint32_t  PREVAL0:2;         /* INternal Voltage selection for Presampling */
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  PRECONV:1;         /* Presampled value */
-#else
-         vuint32_t  PREONCE:1;           /* deprecated name - please avoid */
-#endif
-      } B;
-   } ADC_PSCR_32B_tag;
-
-   typedef union {   /* Presampling  Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  PRES31:1;          /* Channel 31 Presampling  Enable */
-         vuint32_t  PRES30:1;          /* Channel 30 Presampling  Enable */
-         vuint32_t  PRES29:1;          /* Channel 29 Presampling  Enable */
-         vuint32_t  PRES28:1;          /* Channel 28 Presampling  Enable */
-         vuint32_t  PRES27:1;          /* Channel 27 Presampling  Enable */
-         vuint32_t  PRES26:1;          /* Channel 26 Presampling  Enable */
-         vuint32_t  PRES25:1;          /* Channel 25 Presampling  Enable */
-         vuint32_t  PRES24:1;          /* Channel 24 Presampling  Enable */
-         vuint32_t  PRES23:1;          /* Channel 23 Presampling  Enable */
-         vuint32_t  PRES22:1;          /* Channel 22 Presampling  Enable */
-         vuint32_t  PRES21:1;          /* Channel 21 Presampling  Enable */
-         vuint32_t  PRES20:1;          /* Channel 20 Presampling  Enable */
-         vuint32_t  PRES19:1;          /* Channel 19 Presampling  Enable */
-         vuint32_t  PRES18:1;          /* Channel 18 Presampling  Enable */
-         vuint32_t  PRES17:1;          /* Channel 17 Presampling  Enable */
-         vuint32_t  PRES16:1;          /* Channel 16 Presampling  Enable */
-         vuint32_t  PRES15:1;          /* Channel 15   Presampling  Enable */
-         vuint32_t  PRES14:1;          /* Channel 14   Presampling  Enable */
-         vuint32_t  PRES13:1;          /* Channel 13  Presampling   Enable */
-         vuint32_t  PRES12:1;          /* Channel 12   Presampling  Enable */
-         vuint32_t  PRES11:1;          /* Channel 11   Presampling  Enable */
-         vuint32_t  PRES10:1;          /* Channel 10  Presampling   Enable */
-         vuint32_t  PRES9:1;           /* Channel 9 Presampling   Enable */
-         vuint32_t  PRES8:1;           /* Channel 8 Presampling  Enable */
-         vuint32_t  PRES7:1;           /* Channel 7 Presampling    Enable */
-         vuint32_t  PRES6:1;           /* Channel 6 Presampling   Enable */
-         vuint32_t  PRES5:1;           /* Channel 5 Presampling  Enable */
-         vuint32_t  PRES4:1;           /* Channel 4 Presampling  Enable */
-         vuint32_t  PRES3:1;           /* Channel 3 Presampling  Enable */
-         vuint32_t  PRES2:1;           /* Channel 2 Presampling  Enable */
-         vuint32_t  PRES1:1;           /* Channel 1presampling  Enable */
-         vuint32_t  PRES0:1;           /* Channel 0 Presampling  Enable */
-      } B;
-   } ADC_PSR0_32B_tag;
-
-   typedef union {   /* Presampling REGISTER 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  PRES63:1;          /* Channel 63 Presampling  Enable */
-         vuint32_t  PRES62:1;          /* Channel 62 Presampling  Enable */
-         vuint32_t  PRES61:1;          /* Channel 61 Presampling  Enable */
-         vuint32_t  PRES60:1;          /* Channel 60 Presampling  Enable */
-         vuint32_t  PRES59:1;          /* Channel 59 Presampling  Enable */
-         vuint32_t  PRES58:1;          /* Channel 58 Presampling  Enable */
-         vuint32_t  PRES57:1;          /* Channel 57 Presampling  Enable */
-         vuint32_t  PRES56:1;          /* Channel 56 Presampling  Enable */
-         vuint32_t  PRES55:1;          /* Channel 55 Presampling  Enable */
-         vuint32_t  PRES54:1;          /* Channel 54 Presampling  Enable */
-         vuint32_t  PRES53:1;          /* Channel 53 Presampling  Enable */
-         vuint32_t  PRES52:1;          /* Channel 52 Presampling  Enable */
-         vuint32_t  PRES51:1;          /* Channel 51 Presampling  Enable */
-         vuint32_t  PRES50:1;          /* Channel 50 Presampling  Enable */
-         vuint32_t  PRES49:1;          /* Channel 49 Presampling  Enable */
-         vuint32_t  PRES48:1;          /* Channel 48 Presampling  Enable */
-         vuint32_t  PRES47:1;          /* Channel 47 Presampling  Enable */
-         vuint32_t  PRES46:1;          /* Channel 46 Presampling  Enable */
-         vuint32_t  PRES45:1;          /* Channel 45 Presampling  Enable */
-         vuint32_t  PRES44:1;          /* Channel 44 Presampling  Enable */
-         vuint32_t  PRES43:1;          /* Channel 43 Presampling  Enable */
-         vuint32_t  PRES42:1;          /* Channel 42 Presampling  Enable */
-         vuint32_t  PRES41:1;          /* Channel 41 Presampling  Enable */
-         vuint32_t  PRES40:1;          /* Channel 40 Presampling  Enable */
-         vuint32_t  PRES39:1;          /* Channel 39 Presampling  Enable */
-         vuint32_t  PRES38:1;          /* Channel 38 Presampling  Enable */
-         vuint32_t  PRES37:1;          /* Channel 37 Presampling  Enable */
-         vuint32_t  PRES36:1;          /* Channel 36 Presampling  Enable */
-         vuint32_t  PRES35:1;          /* Channel 35 Presampling  Enable */
-         vuint32_t  PRES34:1;          /* Channel 34 Presampling  Enable */
-         vuint32_t  PRES33:1;          /* Channel 33 Presampling  Enable */
-         vuint32_t  PRES32:1;          /* Channel 32 Presampling  Enable */
-      } B;
-   } ADC_PSR1_32B_tag;
-
-   typedef union {   /* Presampling REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  PRES95:1;          /* Channel 95 Presampling  Enable */
-         vuint32_t  PRES94:1;          /* Channel 94 Presampling  Enable */
-         vuint32_t  PRES93:1;          /* Channel 93 Presampling  Enable */
-         vuint32_t  PRES92:1;          /* Channel 92 Presampling  Enable */
-         vuint32_t  PRES91:1;          /* Channel 91 Presampling  Enable */
-         vuint32_t  PRES90:1;          /* Channel 90 Presampling  Enable */
-         vuint32_t  PRES89:1;          /* Channel 89 Presampling  Enable */
-         vuint32_t  PRES88:1;          /* Channel 88 Presampling  Enable */
-         vuint32_t  PRES87:1;          /* Channel 87 Presampling  Enable */
-         vuint32_t  PRES86:1;          /* Channel 86 Presampling  Enable */
-         vuint32_t  PRES85:1;          /* Channel 85 Presampling  Enable */
-         vuint32_t  PRES84:1;          /* Channel 84 Presampling  Enable */
-         vuint32_t  PRES83:1;          /* Channel 83 Presampling  Enable */
-         vuint32_t  PRES82:1;          /* Channel 82 Presampling  Enable */
-         vuint32_t  PRES81:1;          /* Channel 81 Presampling  Enable */
-         vuint32_t  PRES80:1;          /* Channel 80 Presampling  Enable */
-         vuint32_t  PRES79:1;          /* Channel 79 Presampling  Enable */
-         vuint32_t  PRES78:1;          /* Channel 78 Presampling  Enable */
-         vuint32_t  PRES77:1;          /* Channel 77 Presampling  Enable */
-         vuint32_t  PRES76:1;          /* Channel 76 Presampling  Enable */
-         vuint32_t  PRES75:1;          /* Channel 75 Presampling  Enable */
-         vuint32_t  PRES74:1;          /* Channel 74 Presampling  Enable */
-         vuint32_t  PRES73:1;          /* Channel 73 Presampling  Enable */
-         vuint32_t  PRES72:1;          /* Channel 72 Presampling  Enable */
-         vuint32_t  PRES71:1;          /* Channel 71 Presampling  Enable */
-         vuint32_t  PRES70:1;          /* Channel 70 Presampling  Enable */
-         vuint32_t  PRES69:1;          /* Channel 69 Presampling  Enable */
-         vuint32_t  PRES68:1;          /* Channel 68 Presampling  Enable */
-         vuint32_t  PRES67:1;          /* Channel 67 Presampling  Enable */
-         vuint32_t  PRES66:1;          /* Channel 66 Presampling  Enable */
-         vuint32_t  PRES65:1;          /* Channel 65 Presampling  Enable */
-         vuint32_t  PRES64:1;          /* Channel 64 Presampling  Enable */
-      } B;
-   } ADC_PSR2_32B_tag;
-
-
-   /* Register layout for all registers CTR... */
-
-   typedef union {   /* conversion timing register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  INPLATCH:1;        /* configuration bits for the LATCHING PHASE duration */
-         vuint32_t:1;
-         vuint32_t  OFFSHIFT:2;        /* configuration for offset shift characteristics */
-         vuint32_t:1;
-         vuint32_t  INPCMP:2;          /* configuration bits for the COMPARISON duration */
-         vuint32_t:1;
-#ifndef USE_FIELD_ALIASES_ADC
-         vuint32_t  INSAMP:8;          /* configuration bits for the SAMPLING PHASE duration */
-#else		 
-         vuint32_t  INPSAMP:8;
-#endif		 
-      } B;
-   } ADC_CTR_32B_tag;
-
-   typedef union {   /* NORMAL CONVERSION MASK REGISTER 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CH31:1;            /* Channel 31 Normal Sampling Enable */
-         vuint32_t  CH30:1;            /* Channel 30 Normal Sampling Enable */
-         vuint32_t  CH29:1;            /* Channel 29 Normal Sampling Enable */
-         vuint32_t  CH28:1;            /* Channel 28 Normal Sampling Enable */
-         vuint32_t  CH27:1;            /* Channel 27 Normal Sampling Enable */
-         vuint32_t  CH26:1;            /* Channel 26 Normal Sampling Enable */
-         vuint32_t  CH25:1;            /* Channel 25 Normal Sampling Enable */
-         vuint32_t  CH24:1;            /* Channel 24 Normal Sampling Enable */
-         vuint32_t  CH23:1;            /* Channel 23 Normal Sampling Enable */
-         vuint32_t  CH22:1;            /* Channel 22 Normal Sampling Enable */
-         vuint32_t  CH21:1;            /* Channel 21 Normal Sampling Enable */
-         vuint32_t  CH20:1;            /* Channel 20 Normal Sampling Enable */
-         vuint32_t  CH19:1;            /* Channel 19 Normal Sampling Enable */
-         vuint32_t  CH18:1;            /* Channel 18 Normal Sampling Enable */
-         vuint32_t  CH17:1;            /* Channel 17 Normal Sampling Enable */
-         vuint32_t  CH16:1;            /* Channel 16 Normal Sampling Enable */
-         vuint32_t  CH15:1;            /* Channel 15 Normal Sampling Enable */
-         vuint32_t  CH14:1;            /* Channel 14 Normal Sampling Enable */
-         vuint32_t  CH13:1;            /* Channel 13 Normal Sampling Enable */
-         vuint32_t  CH12:1;            /* Channel 12 Normal Sampling Enable */
-         vuint32_t  CH11:1;            /* Channel 11 Normal Sampling Enable */
-         vuint32_t  CH10:1;            /* Channel 10 Normal Sampling Enable */
-         vuint32_t  CH9:1;             /* Channel 9 Normal Sampling Enable */
-         vuint32_t  CH8:1;             /* Channel 8 Normal Sampling Enable */
-         vuint32_t  CH7:1;             /* Channel 7 Normal Sampling Enable */
-         vuint32_t  CH6:1;             /* Channel 6 Normal Sampling Enable */
-         vuint32_t  CH5:1;             /* Channel 5 Normal Sampling Enable */
-         vuint32_t  CH4:1;             /* Channel 4 Normal Sampling Enable */
-         vuint32_t  CH3:1;             /* Channel 3 Normal Sampling Enable */
-         vuint32_t  CH2:1;             /* Channel 2 Normal Sampling Enable */
-         vuint32_t  CH1:1;             /* Channel 1 Normal Sampling Enable */
-         vuint32_t  CH0:1;             /* Channel 0 Normal Sampling Enable */
-      } B;
-   } ADC_NCMR0_32B_tag;
-
-   typedef union {   /* NORMAL CONVERSION MASK REGISTER 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CH63:1;            /* Channel 63 Normal Sampling Enable */
-         vuint32_t  CH62:1;            /* Channel 62 Normal Sampling Enable */
-         vuint32_t  CH61:1;            /* Channel 61 Normal Sampling Enable */
-         vuint32_t  CH60:1;            /* Channel 60 Normal Sampling Enable */
-         vuint32_t  CH59:1;            /* Channel 59 Normal Sampling Enable */
-         vuint32_t  CH58:1;            /* Channel 58 Normal Sampling Enable */
-         vuint32_t  CH57:1;            /* Channel 57 Normal Sampling Enable */
-         vuint32_t  CH56:1;            /* Channel 56 Normal Sampling Enable */
-         vuint32_t  CH55:1;            /* Channel 55 Normal Sampling Enable */
-         vuint32_t  CH54:1;            /* Channel 54 Normal Sampling Enable */
-         vuint32_t  CH53:1;            /* Channel 53 Normal Sampling Enable */
-         vuint32_t  CH52:1;            /* Channel 52 Normal Sampling Enable */
-         vuint32_t  CH51:1;            /* Channel 51 Normal Sampling Enable */
-         vuint32_t  CH50:1;            /* Channel 50 Normal Sampling Enable */
-         vuint32_t  CH49:1;            /* Channel 49 Normal Sampling Enable */
-         vuint32_t  CH48:1;            /* Channel 48 Normal Sampling Enable */
-         vuint32_t  CH47:1;            /* Channel 47 Normal Sampling Enable */
-         vuint32_t  CH46:1;            /* Channel 46 Normal Sampling Enable */
-         vuint32_t  CH45:1;            /* Channel 45 Normal Sampling Enable */
-         vuint32_t  CH44:1;            /* Channel 44 Normal Sampling Enable */
-         vuint32_t  CH43:1;            /* Channel 43 Normal Sampling Enable */
-         vuint32_t  CH42:1;            /* Channel 42 Normal Sampling Enable */
-         vuint32_t  CH41:1;            /* Channel 41 Normal Sampling Enable */
-         vuint32_t  CH40:1;            /* Channel 40 Normal Sampling Enable */
-         vuint32_t  CH39:1;            /* Channel 39 Normal Sampling Enable */
-         vuint32_t  CH38:1;            /* Channel 38 Normal Sampling Enable */
-         vuint32_t  CH37:1;            /* Channel 37 Normal Sampling Enable */
-         vuint32_t  CH36:1;            /* Channel 36 Normal Sampling Enable */
-         vuint32_t  CH35:1;            /* Channel 35 Normal Sampling Enable */
-         vuint32_t  CH34:1;            /* Channel 34 Normal Sampling Enable */
-         vuint32_t  CH33:1;            /* Channel 33 Normal Sampling Enable */
-         vuint32_t  CH32:1;            /* Channel 32 Normal Sampling Enable */
-      } B;
-   } ADC_NCMR1_32B_tag;
-
-   typedef union {   /* NORMAL CONVERSION MASK REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CH95:1;            /* Channel 95 Normal Sampling Enable */
-         vuint32_t  CH94:1;            /* Channel 94 Normal Sampling Enable */
-         vuint32_t  CH93:1;            /* Channel 93 Normal Sampling Enable */
-         vuint32_t  CH92:1;            /* Channel 92 Normal Sampling Enable */
-         vuint32_t  CH91:1;            /* Channel 91 Normal Sampling Enable */
-         vuint32_t  CH90:1;            /* Channel 90 Normal Sampling Enable */
-         vuint32_t  CH89:1;            /* Channel 89 Normal Sampling Enable */
-         vuint32_t  CH88:1;            /* Channel 88 Normal Sampling Enable */
-         vuint32_t  CH87:1;            /* Channel 87 Normal Sampling Enable */
-         vuint32_t  CH86:1;            /* Channel 86 Normal Sampling Enable */
-         vuint32_t  CH85:1;            /* Channel 85 Normal Sampling Enable */
-         vuint32_t  CH84:1;            /* Channel 84 Normal Sampling Enable */
-         vuint32_t  CH83:1;            /* Channel 83 Normal Sampling Enable */
-         vuint32_t  CH82:1;            /* Channel 82 Normal Sampling Enable */
-         vuint32_t  CH81:1;            /* Channel 81 Normal Sampling Enable */
-         vuint32_t  CH80:1;            /* Channel 80 Normal Sampling Enable */
-         vuint32_t  CH79:1;            /* Channel 79 Normal Sampling Enable */
-         vuint32_t  CH78:1;            /* Channel 78 Normal Sampling Enable */
-         vuint32_t  CH77:1;            /* Channel 77 Normal Sampling Enable */
-         vuint32_t  CH76:1;            /* Channel 76 Normal Sampling Enable */
-         vuint32_t  CH75:1;            /* Channel 75 Normal Sampling Enable */
-         vuint32_t  CH74:1;            /* Channel 74 Normal Sampling Enable */
-         vuint32_t  CH73:1;            /* Channel 73 Normal Sampling Enable */
-         vuint32_t  CH72:1;            /* Channel 72 Normal Sampling Enable */
-         vuint32_t  CH71:1;            /* Channel 71 Normal Sampling Enable */
-         vuint32_t  CH70:1;            /* Channel 70 Normal Sampling Enable */
-         vuint32_t  CH69:1;            /* Channel 69 Normal Sampling Enable */
-         vuint32_t  CH68:1;            /* Channel 68 Normal Sampling Enable */
-         vuint32_t  CH67:1;            /* Channel 67 Normal Sampling Enable */
-         vuint32_t  CH66:1;            /* Channel 66 Normal Sampling Enable */
-         vuint32_t  CH65:1;            /* Channel 65 Normal Sampling Enable */
-         vuint32_t  CH64:1;            /* Channel 64 Normal Sampling Enable */
-      } B;
-   } ADC_NCMR2_32B_tag;
-
-   typedef union {   /* Injected Conversion Mask Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CH31:1;            /* Channel 31 Injected Sampling Enable */
-         vuint32_t  CH30:1;            /* Channel 30 Injected Sampling Enable */
-         vuint32_t  CH29:1;            /* Channel 29 Injected Sampling Enable */
-         vuint32_t  CH28:1;            /* Channel 28 Injected Sampling Enable */
-         vuint32_t  CH27:1;            /* Channel 27 Injected Sampling Enable */
-         vuint32_t  CH26:1;            /* Channel 26 Injected Sampling Enable */
-         vuint32_t  CH25:1;            /* Channel 25 Injected Sampling Enable */
-         vuint32_t  CH24:1;            /* Channel 24 Injected Sampling Enable */
-         vuint32_t  CH23:1;            /* Channel 23 Injected Sampling Enable */
-         vuint32_t  CH22:1;            /* Channel 22 Injected Sampling Enable */
-         vuint32_t  CH21:1;            /* Channel 21 Injected Sampling Enable */
-         vuint32_t  CH20:1;            /* Channel 20 Injected Sampling Enable */
-         vuint32_t  CH19:1;            /* Channel 19 Injected Sampling Enable */
-         vuint32_t  CH18:1;            /* Channel 18 Injected Sampling Enable */
-         vuint32_t  CH17:1;            /* Channel 17 Injected Sampling Enable */
-         vuint32_t  CH16:1;            /* Channel 16 Injected Sampling Enable */
-         vuint32_t  CH15:1;            /* Channel 15   Injected Sampling Enable */
-         vuint32_t  CH14:1;            /* Channel 14   Injected Sampling Enable */
-         vuint32_t  CH13:1;            /* Channel 13  Injected  Sampling Enable */
-         vuint32_t  CH12:1;            /* Channel 12   Injected Sampling Enable */
-         vuint32_t  CH11:1;            /* Channel 11   Injected Sampling Enable */
-         vuint32_t  CH10:1;            /* Channel 10  Injected  Sampling Enable */
-         vuint32_t  CH9:1;             /* Channel 9 Injected  Sampling Enable */
-         vuint32_t  CH8:1;             /* Channel 8 Injected Sampling Enable */
-         vuint32_t  CH7:1;             /* Channel 7 Injected   Sampling Enable */
-         vuint32_t  CH6:1;             /* Channel 6 Injected  Sampling Enable */
-         vuint32_t  CH5:1;             /* Channel 5 Injected Sampling Enable */
-         vuint32_t  CH4:1;             /* Channel 4 Injected Sampling Enable */
-         vuint32_t  CH3:1;             /* Channel 3 Injected Sampling Enable */
-         vuint32_t  CH2:1;             /* Channel 2 Injected Sampling Enable */
-         vuint32_t  CH1:1;             /* Channel 1 injected Sampling Enable */
-         vuint32_t  CH0:1;             /* Channel 0 injected Sampling Enable */
-      } B;
-   } ADC_JCMR0_32B_tag;
-
-   typedef union {   /* INJECTED CONVERSION MASK REGISTER 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CH63:1;            /* Channel 63 Injected Sampling Enable */
-         vuint32_t  CH62:1;            /* Channel 62 Injected Sampling Enable */
-         vuint32_t  CH61:1;            /* Channel 61 Injected Sampling Enable */
-         vuint32_t  CH60:1;            /* Channel 60 Injected Sampling Enable */
-         vuint32_t  CH59:1;            /* Channel 59 Injected Sampling Enable */
-         vuint32_t  CH58:1;            /* Channel 58 Injected Sampling Enable */
-         vuint32_t  CH57:1;            /* Channel 57 Injected Sampling Enable */
-         vuint32_t  CH56:1;            /* Channel 56 Injected Sampling Enable */
-         vuint32_t  CH55:1;            /* Channel 55 Injected Sampling Enable */
-         vuint32_t  CH54:1;            /* Channel 54 Injected Sampling Enable */
-         vuint32_t  CH53:1;            /* Channel 53 Injected Sampling Enable */
-         vuint32_t  CH52:1;            /* Channel 52 Injected Sampling Enable */
-         vuint32_t  CH51:1;            /* Channel 51 Injected Sampling Enable */
-         vuint32_t  CH50:1;            /* Channel 50 Injected Sampling Enable */
-         vuint32_t  CH49:1;            /* Channel 49 Injected Sampling Enable */
-         vuint32_t  CH48:1;            /* Channel 48 Injected Sampling Enable */
-         vuint32_t  CH47:1;            /* Channel 47 Injected Sampling Enable */
-         vuint32_t  CH46:1;            /* Channel 46 Injected Sampling Enable */
-         vuint32_t  CH45:1;            /* Channel 45 Injected Sampling Enable */
-         vuint32_t  CH44:1;            /* Channel 44 Injected Sampling Enable */
-         vuint32_t  CH43:1;            /* Channel 43 Injected Sampling Enable */
-         vuint32_t  CH42:1;            /* Channel 42 Injected Sampling Enable */
-         vuint32_t  CH41:1;            /* Channel 41 Injected Sampling Enable */
-         vuint32_t  CH40:1;            /* Channel 40 Injected Sampling Enable */
-         vuint32_t  CH39:1;            /* Channel 39 Injected Sampling Enable */
-         vuint32_t  CH38:1;            /* Channel 38 Injected Sampling Enable */
-         vuint32_t  CH37:1;            /* Channel 37 Injected Sampling Enable */
-         vuint32_t  CH36:1;            /* Channel 36 Injected Sampling Enable */
-         vuint32_t  CH35:1;            /* Channel 35 Injected Sampling Enable */
-         vuint32_t  CH34:1;            /* Channel 34 Injected Sampling Enable */
-         vuint32_t  CH33:1;            /* Channel 33 Injected Sampling Enable */
-         vuint32_t  CH32:1;            /* Channel 32 Injected Sampling Enable */
-      } B;
-   } ADC_JCMR1_32B_tag;
-
-   typedef union {   /* INJECTED CONVERSION MASK REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CH95:1;            /* Channel 95 Injected Sampling Enable */
-         vuint32_t  CH94:1;            /* Channel 94 Injected Sampling Enable */
-         vuint32_t  CH93:1;            /* Channel 93 Injected Sampling Enable */
-         vuint32_t  CH92:1;            /* Channel 92 Injected Sampling Enable */
-         vuint32_t  CH91:1;            /* Channel 91 Injected Sampling Enable */
-         vuint32_t  CH90:1;            /* Channel 90 Injected Sampling Enable */
-         vuint32_t  CH89:1;            /* Channel 89 Injected Sampling Enable */
-         vuint32_t  CH88:1;            /* Channel 88 Injected Sampling Enable */
-         vuint32_t  CH87:1;            /* Channel 87 Injected Sampling Enable */
-         vuint32_t  CH86:1;            /* Channel 86 Injected Sampling Enable */
-         vuint32_t  CH85:1;            /* Channel 85 Injected Sampling Enable */
-         vuint32_t  CH84:1;            /* Channel 84 Injected Sampling Enable */
-         vuint32_t  CH83:1;            /* Channel 83 Injected Sampling Enable */
-         vuint32_t  CH82:1;            /* Channel 82 Injected Sampling Enable */
-         vuint32_t  CH81:1;            /* Channel 81 Injected Sampling Enable */
-         vuint32_t  CH80:1;            /* Channel 80 Injected Sampling Enable */
-         vuint32_t  CH79:1;            /* Channel 79 Injected Sampling Enable */
-         vuint32_t  CH78:1;            /* Channel 78 Injected Sampling Enable */
-         vuint32_t  CH77:1;            /* Channel 77 Injected Sampling Enable */
-         vuint32_t  CH76:1;            /* Channel 76 Injected Sampling Enable */
-         vuint32_t  CH75:1;            /* Channel 75 Injected Sampling Enable */
-         vuint32_t  CH74:1;            /* Channel 74 Injected Sampling Enable */
-         vuint32_t  CH73:1;            /* Channel 73 Injected Sampling Enable */
-         vuint32_t  CH72:1;            /* Channel 72 Injected Sampling Enable */
-         vuint32_t  CH71:1;            /* Channel 71 Injected Sampling Enable */
-         vuint32_t  CH70:1;            /* Channel 70 Injected Sampling Enable */
-         vuint32_t  CH69:1;            /* Channel 69 Injected Sampling Enable */
-         vuint32_t  CH68:1;            /* Channel 68 Injected Sampling Enable */
-         vuint32_t  CH67:1;            /* Channel 67 Injected Sampling Enable */
-         vuint32_t  CH66:1;            /* Channel 66 Injected Sampling Enable */
-         vuint32_t  CH65:1;            /* Channel 65 Injected Sampling Enable */
-         vuint32_t  CH64:1;            /* Channel 64 Injected Sampling Enable */
-      } B;
-   } ADC_JCMR2_32B_tag;
-
-   typedef union {   /* Offset Word Regsiter */
-      vuint32_t R;
-      struct {
-         vuint32_t:15;
-         vuint32_t  OFFSETLOAD:1;      /* load_offset */
-         vuint32_t:8;
-#ifndef USE_FIELD_ALIASES_ADC		 
-         vuint32_t  OFFSET_WORD:8;     /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */
-#else		
-         vuint32_t  OFFSETWORD:8;  
-#endif		 
-      } B;
-   } ADC_OFFWR_32B_tag;
-
-   typedef union {   /* Decode Signal Delay Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:24;
-         vuint32_t  DSD:8;             /* take into account the settling time of the external mux */
-      } B;
-   } ADC_DSDR_32B_tag;
-
-   typedef union {   /* Power Down Dealy Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:24;
-         vuint32_t  PDED:8;            /* The delay between the power down bit reset and the starting of conversion */
-      } B;
-   } ADC_PDEDR_32B_tag;
-
-
-   /* Register layout for all registers CDR... */
-
-   typedef union {   /* CHANNEL DATA REGS */
-      vuint32_t R;
-      struct {
-         vuint32_t:12;
-         vuint32_t  VALID:1;           /* validity of data */
-         vuint32_t  OVERW:1;           /* overwrite data */
-         vuint32_t  RESULT:2;          /* reflects mode conversion */
-         vuint32_t:6;
-         vuint32_t  CDATA:10;          /* Channel 0 converted data */
-      } B;
-   } ADC_CDR_32B_tag;
-
-   typedef union {   /* Upper Threshold register 4 is not contiguous to 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR4_32B_tag;
-
-   typedef union {   /* Upper Threshold register 5 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR5_32B_tag;
-
-   typedef union {   /* Upper Threshold register 6 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR6_32B_tag;
-
-   typedef union {   /* Upper Threshold register 7 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR7_32B_tag;
-
-   typedef union {   /* Upper Threshold register 8 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR8_32B_tag;
-
-   typedef union {   /* Upper Threshold register 9 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR9_32B_tag;
-
-   typedef union {   /* Upper Threshold register 10 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR10_32B_tag;
-
-   typedef union {   /* Upper Threshold register 11 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR11_32B_tag;
-
-   typedef union {   /* Upper Threshold register 12 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR12_32B_tag;
-
-   typedef union {   /* Upper Threshold register 13 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR13_32B_tag;
-
-   typedef union {   /* Upper Threshold register 14 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR14_32B_tag;
-
-   typedef union {   /* Upper Threshold register 15 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* high threshold value s */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* low threshold value s */
-      } B;
-   } ADC_THRHLR15_32B_tag;
-
-
-   /* Register layout for all registers CWSELR... */
-
-   typedef union {   /* Channel Watchdog Select register */
-      vuint32_t R;
-      struct {
-         vuint32_t  WSEL_CH7:4;        /* Channel Watchdog select for channel 7+R*8 */
-         vuint32_t  WSEL_CH6:4;        /* Channel Watchdog select for channel 6+R*8 */
-         vuint32_t  WSEL_CH5:4;        /* Channel Watchdog select for channel 5+R*8 */
-         vuint32_t  WSEL_CH4:4;        /* Channel Watchdog select for channel 4+R*8 */
-         vuint32_t  WSEL_CH3:4;        /* Channel Watchdog select for channel 3+R*8 */
-         vuint32_t  WSEL_CH2:4;        /* Channel Watchdog select for channel 2+R*8 */
-         vuint32_t  WSEL_CH1:4;        /* Channel Watchdog select for channel 1+R*8 */
-         vuint32_t  WSEL_CH0:4;        /* Channel Watchdog select for channel 0+R*8 */
-      } B;
-   } ADC_CWSELR_32B_tag;
-
-
-   /* Register layout for all registers CWENR... */
-
-   typedef union {   /* Channel Watchdog Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  CWEN15PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN14PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN13PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN12PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN11PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN10PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN09PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN08PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN07PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN06PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN05PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN04PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN03PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN02PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN01PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-         vuint32_t  CWEN00PRT32:1;     /* Channel Watchdog Enable 0+R*32 */
-      } B;
-   } ADC_CWENR_32B_tag;
-
-
-   /* Register layout for all registers AWORR... */
-
-   typedef union {   /* Analog Watchdog Out of Range Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  AWOR_CH31:1;       /* Channel 31+R*32 converted data out of range */
-         vuint32_t  AWOR_CH30:1;       /* Channel 30+R*32 converted data out of range */
-         vuint32_t  AWOR_CH29:1;       /* Channel 29+R*32 converted data out of range */
-         vuint32_t  AWOR_CH28:1;       /* Channel 28+R*32 converted data out of range */
-         vuint32_t  AWOR_CH27:1;       /* Channel 27+R*32 converted data out of range */
-         vuint32_t  AWOR_CH26:1;       /* Channel 26+R*32 converted data out of range */
-         vuint32_t  AWOR_CH25:1;       /* Channel 25+R*32 converted data out of range */
-         vuint32_t  AWOR_CH24:1;       /* Channel 24+R*32 converted data out of range */
-         vuint32_t  AWOR_CH23:1;       /* Channel 23+R*32 converted data out of range */
-         vuint32_t  AWOR_CH22:1;       /* Channel 22+R*32 converted data out of range */
-         vuint32_t  AWOR_CH21:1;       /* Channel 21+R*32 converted data out of range */
-         vuint32_t  AWOR_CH20:1;       /* Channel 20+R*32 converted data out of range */
-         vuint32_t  AWOR_CH19:1;       /* Channel 19+R*32 converted data out of range */
-         vuint32_t  AWOR_CH18:1;       /* Channel 18+R*32 converted data out of range */
-         vuint32_t  AWOR_CH17:1;       /* Channel 17+R*32 converted data out of range */
-         vuint32_t  AWOR_CH16:1;       /* Channel 16+R*32 converted data out of range */
-         vuint32_t  AWOR_CH15:1;       /* Channel 15+R*32 converted data out of range */
-         vuint32_t  AWOR_CH14:1;       /* Channel 14+R*32 converted data out of range */
-         vuint32_t  AWOR_CH13:1;       /* Channel 13+R*32 converted data out of range */
-         vuint32_t  AWOR_CH12:1;       /* Channel 12+R*32 converted data out of range */
-         vuint32_t  AWOR_CH11:1;       /* Channel 11+R*32 converted data out of range */
-         vuint32_t  AWOR_CH10:1;       /* Channel 10+R*32 converted data out of range */
-         vuint32_t  AWOR_CH9:1;        /* Channel 9+R*32 converted data out of range */
-         vuint32_t  AWOR_CH8:1;        /* Channel 8+R*32 converted data out of range */
-         vuint32_t  AWOR_CH7:1;        /* Channel 7+R*32 converted data out of range */
-         vuint32_t  AWOR_CH6:1;        /* Channel 6+R*32 converted data out of range */
-         vuint32_t  AWOR_CH5:1;        /* Channel 5+R*32 converted data out of range */
-         vuint32_t  AWOR_CH4:1;        /* Channel 4+R*32 converted data out of range */
-         vuint32_t  AWOR_CH3:1;        /* Channel 3+R*32 converted data out of range */
-         vuint32_t  AWOR_CH2:1;        /* Channel 2+R*32 converted data out of range */
-         vuint32_t  AWOR_CH1:1;        /* Channel 1+R*32 converted data out of range */
-         vuint32_t  AWOR_CH0:1;        /* Channel 0+R*32 converted data out of range */
-      } B;
-   } ADC_AWORR_32B_tag;
-
-   typedef union {   /* SELF TEST CONFIGURATION REGISTER 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  INPSAMP_C:8;       /* Sampling phase duration for the test conversions - algorithm C */
-         vuint32_t  INPSAMP_RC:8;      /* Sampling phase duration for the test conversions - algorithm RC */
-         vuint32_t  INPSAMP_S:8;       /* Sampling phase duration for the test conversions - algorithm S */
-         vuint32_t:5;
-         vuint32_t  ST_INPCMP:2;       /* Configuration bit for comparison phase duration for self test channel */
-         vuint32_t  ST_INPLATCH:1;     /* Configuration bit for Latching phase duration for self test channel */
-      } B;
-   } ADC_STCR1_32B_tag;
-
-   typedef union {   /* SELF TEST CONFIGURATION REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t:5;
-         vuint32_t  SERR:1;            /* Error fault injection bit (write only) */
-         vuint32_t  MSKSTWDTERR:1;     /* Interrupt enable (STSR2.WDTERR status bit) */
-         vuint32_t:1;
-         vuint32_t  MSKST_EOC:1;       /* Interrupt enable bit for STSR2.ST_EOC */
-         vuint32_t:4;
-         vuint32_t  MSKWDG_EOA_C:1;    /* Interrupt enable (WDG_EOA_C status bit) */
-         vuint32_t  MSKWDG_EOA_RC:1;   /* Interrupt enable (WDG_EOA_RC status bit) */
-         vuint32_t  MSKWDG_EOA_S:1;    /* Interrupt enable (WDG_EOA_S status bit) */
-         vuint32_t  MSKERR_C:1;        /* Interrupt enable (ERR_C status bit) */
-         vuint32_t  MSKERR_RC:1;       /* Interrupt enable (ERR_RC status bit) */
-         vuint32_t  MSKERR_S2:1;       /* Interrupt enable (ERR_S2 status bit) */
-         vuint32_t  MSKERR_S1:1;       /* Interrupt enable (ERR_S1 status bit) */
-         vuint32_t  MSKERR_S0:1;       /* Interrupt enable (ERR_S0 status bit) */
-         vuint32_t:3;
-         vuint32_t  EN:1;              /* Self testing channel enable */
-         vuint32_t:4;
-         vuint32_t  FMA_C:1;           /* Fault mapping for the algorithm C */
-         vuint32_t  FMAR_C:1;          /* Fault mapping for the algorithm RC */
-         vuint32_t  FMA_S:1;           /* Fault mapping for the algorithm BGAP */
-      } B;
-   } ADC_STCR2_32B_tag;
-
-   typedef union {   /* SELF TEST CONFIGURATION REGISTER 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t:22;
-         vuint32_t  ALG:2;             /* Algorithm scheduling */
-         vuint32_t:8;
-      } B;
-   } ADC_STCR3_32B_tag;
-
-   typedef union {   /* SELF TEST BAUD RATE REGISTER */
-      vuint32_t R;
-      struct {
-         vuint32_t:13;
-         vuint32_t  WDT:3;             /* Watchdog timer value */
-         vuint32_t:8;
-         vuint32_t  BR:8;              /* Baud rate for the selected algorithm in SCAN mode */
-      } B;
-   } ADC_STBRR_32B_tag;
-
-   typedef union {   /* SELF TEST STATUS REGISTER 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t:6;
-         vuint32_t  WDTERR:1;          /* Watchdog timer error */
-         vuint32_t  OVERWR:1;          /* Overwrite error */
-         vuint32_t  ST_EOC:1;          /* Self test EOC bit */
-         vuint32_t:4;
-         vuint32_t  WDG_EOA_C:1;       /* Algorithm  C completed without error */
-         vuint32_t  WDG_EOA_RC:1;      /* Algorithm RC completed without error */
-         vuint32_t  WDG_EOA_S:1;       /* Algorithm  S completed without error */
-         vuint32_t  ERR_C:1;           /* Error on the self testing channel (algorithm  C) */
-         vuint32_t  ERR_RC:1;          /* Error on the self testing channel (algorithm RC) */
-         vuint32_t  ERR_S2:1;          /* Error on the self testing channel (algorithm SUPPLY, step 2) */
-         vuint32_t  ERR_S1:1;          /* Error on the self testing channel (algorithm SUPPLY, step 1) */
-         vuint32_t  ERR_S0:1;          /* Error on the self testing channel (algorithm SUPPLY, step 0) */
-         vuint32_t:1;
-         vuint32_t  STEP_C:5;          /* Step of algorithm  C when ERR_C  has occurred */
-         vuint32_t  STEP_RC:5;         /* Step of algorithm RC when ERR_RC has occurred */
-      } B;
-   } ADC_STSR1_32B_tag;
-
-   typedef union {   /* SELF TEST STATUS REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  OVFL:1;            /* Overflow bit */
-         vuint32_t:3;
-         vuint32_t  DATA1:12;          /* Test channel converted data when ERR_S1 has occurred */
-         vuint32_t:4;
-         vuint32_t  DATA0:12;          /* Test channel converted data when ERR_S1 has occurred */
-      } B;
-   } ADC_STSR2_32B_tag;
-
-   typedef union {   /* SELF TEST STATUS REGISTER 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  DATA1:12;          /* Test channel converted data when ERR_S0 has occurred */
-         vuint32_t:4;
-         vuint32_t  DATA0:12;          /* Test channel converted data when ERR_S0 has occurred */
-      } B;
-   } ADC_STSR3_32B_tag;
-
-   typedef union {   /* SELF TEST STATUS REGISTER 4 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  DATA1:12;          /* Test channel converted data when ERR_C has occurred */
-         vuint32_t:4;
-         vuint32_t  DATA0:12;          /* Test channel converted data when ERR_C has occurred */
-      } B;
-   } ADC_STSR4_32B_tag;
-
-   typedef union {   /* SELF TEST DATA REGISTER 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t:12;
-         vuint32_t  VALID:1;           /* Valid data */
-         vuint32_t  OVERWR:1;          /* Overwrite data */
-         vuint32_t:6;
-         vuint32_t  TCDATA:12;         /* Test channel converted data */
-      } B;
-   } ADC_STDR1_32B_tag;
-
-   typedef union {   /* SELF TEST DATA REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  FDATA:12;          /* Fractional part of the ratio TEST for algorithm S */
-         vuint32_t  VALID:1;           /* Valid data */
-         vuint32_t  OVERWR:1;          /* Overwrite data */
-         vuint32_t:6;
-         vuint32_t  IDATA:12;          /* Integer part of the ratio TEST for algorithm S */
-      } B;
-   } ADC_STDR2_32B_tag;
-
-   typedef union {   /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  AWDE:1;            /* Analog WatchDog Enable - algorithm S */
-         vuint32_t  WDTE:1;            /* WatchDog Timer Enable - algorithm S */
-         vuint32_t:2;
-         vuint32_t  THRH:12;           /* High threshold value for channel 0 */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* Low threshold value for channel 0 */
-      } B;
-   } ADC_STAW0R_32B_tag;
-
-   typedef union {   /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
-      vuint32_t R;
-      struct {
-         vuint32_t  AWDE:1;            /* Analog WatchDog Enable - algorithm S */
-         vuint32_t:3;
-         vuint32_t  THRH:12;           /* High threshold value for test channel - algorithm S */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* Low threshold value for test channel - algorithm S */
-      } B;
-   } ADC_STAW1AR_32B_tag;
-
-   typedef union {   /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* High threshold value for test channel - algorithm S */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* Low threshold value for test channel - algorithm S */
-      } B;
-   } ADC_STAW1BR_32B_tag;
-
-   typedef union {   /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  AWDE:1;            /* Analog WatchDog Enable - algorithm S */
-         vuint32_t:19;
-         vuint32_t  THRL:12;           /* Low threshold value for channel */
-      } B;
-   } ADC_STAW2R_32B_tag;
-
-   typedef union {   /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  AWDE:1;            /* Analog WatchDog Enable - algorithm RC */
-         vuint32_t  WDTE:1;            /* WatchDog Timer Enable - algorithm RC */
-         vuint32_t:2;
-         vuint32_t  THRH:12;           /* High threshold value for channel 3 */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* Low threshold value for channel 3 */
-      } B;
-   } ADC_STAW3R_32B_tag;
-
-   typedef union {   /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
-      vuint32_t R;
-      struct {
-         vuint32_t  AWDE:1;            /* Analog WatchDog Enable - algorithm C */
-         vuint32_t  WDTE:1;            /* WatchDog Timer Enable - algorithm C */
-         vuint32_t:2;
-         vuint32_t  THRH:12;           /* High threshold value for channel 4 */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* Low threshold value for channel 4 */
-      } B;
-   } ADC_STAW4R_32B_tag;
-
-   typedef union {   /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  THRH:12;           /* High threshold value for algorithm C */
-         vuint32_t:4;
-         vuint32_t  THRL:12;           /* Low threshold value for algorithm C */
-      } B;
-   } ADC_STAW5R_32B_tag;
-
-
-
-   typedef struct ADC_struct_tag { /* start of ADC_tag */
-                                        /* module configuration register */
-      ADC_MCR_32B_tag MCR;                 /* offset: 0x0000 size: 32 bit */
-                                               /* module status register */
-      ADC_MSR_32B_tag MSR;                 /* offset: 0x0004 size: 32 bit */
-      int8_t ADC_reserved_0008[8];
-                                            /* Interrupt status register */
-      ADC_ISR_32B_tag ISR;                 /* offset: 0x0010 size: 32 bit */
-      union {
-         ADC_CEOCFR0_32B_tag CEOCFR[3];    /* offset: 0x0014  (0x0004 x 3) */
-
-         struct {
-                                           /* CHANNEL PENDING REGISTER 0 */
-            ADC_CEOCFR0_32B_tag CEOCFR0;   /* offset: 0x0014 size: 32 bit */
-                                           /* CHANNEL PENDING REGISTER 1 */
-            ADC_CEOCFR1_32B_tag CEOCFR1;   /* offset: 0x0018 size: 32 bit */
-                                           /* CHANNEL PENDING REGISTER 2 */
-            ADC_CEOCFR2_32B_tag CEOCFR2;   /* offset: 0x001C size: 32 bit */
-         };
-
-      };
-                                              /* interrupt mask register */
-      ADC_IMR_32B_tag IMR;                 /* offset: 0x0020 size: 32 bit */
-      union {
-         ADC_CIMR0_32B_tag CIMR[3];        /* offset: 0x0024  (0x0004 x 3) */
-
-         struct {
-                                    /* CHANNEL INTERRUPT MASK REGISTER 0 */
-            ADC_CIMR0_32B_tag CIMR0;       /* offset: 0x0024 size: 32 bit */
-                                    /* CHANNEL INTERRUPT MASK REGISTER 1 */
-            ADC_CIMR1_32B_tag CIMR1;       /* offset: 0x0028 size: 32 bit */
-                                    /* CHANNEL INTERRUPT MASK REGISTER 2 */
-            ADC_CIMR2_32B_tag CIMR2;       /* offset: 0x002C size: 32 bit */
-         };
-
-      };
-                         /* Watchdog Threshold interrupt status register */
-      ADC_WTISR_32B_tag WTISR;             /* offset: 0x0030 size: 32 bit */
-                                     /* Watchdog interrupt MASK register */
-      ADC_WTIMR_32B_tag WTIMR;             /* offset: 0x0034 size: 32 bit */
-      int8_t ADC_reserved_0038[8];
-                                                        /* DMAE register */
-      ADC_DMAE_32B_tag DMAE;               /* offset: 0x0040 size: 32 bit */
-      union {
-         ADC_DMAR0_32B_tag DMAR[3];        /* offset: 0x0044  (0x0004 x 3) */
-
-         struct {
-                                                      /* DMA  REGISTER 0 */
-            ADC_DMAR0_32B_tag DMAR0;       /* offset: 0x0044 size: 32 bit */
-                                                       /* DMA REGISTER 1 */
-            ADC_DMAR1_32B_tag DMAR1;       /* offset: 0x0048 size: 32 bit */
-                                                       /* DMA REGISTER 2 */
-            ADC_DMAR2_32B_tag DMAR2;       /* offset: 0x004C size: 32 bit */
-         };
-
-      };
-      union {
-                                         /* Threshold Control register C */
-         ADC_TRC_32B_tag TRC[4];           /* offset: 0x0050  (0x0004 x 4) */
-
-         struct {
-                                         /* Threshold Control register C */
-            ADC_TRC_32B_tag TRC0;          /* offset: 0x0050 size: 32 bit */
-            ADC_TRC_32B_tag TRC1;          /* offset: 0x0054 size: 32 bit */
-            ADC_TRC_32B_tag TRC2;          /* offset: 0x0058 size: 32 bit */
-            ADC_TRC_32B_tag TRC3;          /* offset: 0x005C size: 32 bit */
-         };
-
-      };
-      union {
-                                             /* Upper Threshold register */
-         ADC_THRHLR_32B_tag THRHLR[4];     /* offset: 0x0060  (0x0004 x 4) */
-
-         struct {
-                                             /* Upper Threshold register */
-            ADC_THRHLR_32B_tag THRHLR0;    /* offset: 0x0060 size: 32 bit */
-            ADC_THRHLR_32B_tag THRHLR1;    /* offset: 0x0064 size: 32 bit */
-            ADC_THRHLR_32B_tag THRHLR2;    /* offset: 0x0068 size: 32 bit */
-            ADC_THRHLR_32B_tag THRHLR3;    /* offset: 0x006C size: 32 bit */
-         };
-
-      };
-      union {
-                                   /* alternate Upper Threshold register */
-         ADC_THRALT_32B_tag THRALT[4];     /* offset: 0x0070  (0x0004 x 4) */
-
-         struct {
-                                   /* alternate Upper Threshold register */
-            ADC_THRALT_32B_tag THRALT0;    /* offset: 0x0070 size: 32 bit */
-            ADC_THRALT_32B_tag THRALT1;    /* offset: 0x0074 size: 32 bit */
-            ADC_THRALT_32B_tag THRALT2;    /* offset: 0x0078 size: 32 bit */
-            ADC_THRALT_32B_tag THRALT3;    /* offset: 0x007C size: 32 bit */
-         };
-
-      };
-                                         /* PRESAMPLING CONTROL REGISTER */
-      ADC_PSCR_32B_tag PSCR;               /* offset: 0x0080 size: 32 bit */
-      union {
-         ADC_PSR0_32B_tag PSR[3];          /* offset: 0x0084  (0x0004 x 3) */
-
-         struct {
-                                              /* Presampling  Register 0 */
-            ADC_PSR0_32B_tag PSR0;         /* offset: 0x0084 size: 32 bit */
-                                               /* Presampling REGISTER 1 */
-            ADC_PSR1_32B_tag PSR1;         /* offset: 0x0088 size: 32 bit */
-                                               /* Presampling REGISTER 2 */
-            ADC_PSR2_32B_tag PSR2;         /* offset: 0x008C size: 32 bit */
-         };
-
-      };
-      int8_t ADC_reserved_0090_C[4];
-      union {
-                                           /* conversion timing register */
-         ADC_CTR_32B_tag CTR[3];           /* offset: 0x0094  (0x0004 x 3) */
-
-         struct {
-                                           /* conversion timing register */
-            ADC_CTR_32B_tag CTR0;          /* offset: 0x0094 size: 32 bit */
-            ADC_CTR_32B_tag CTR1;          /* offset: 0x0098 size: 32 bit */
-            ADC_CTR_32B_tag CTR2;          /* offset: 0x009C size: 32 bit */
-         };
-
-      };
-      int8_t ADC_reserved_00A0_C[4];
-      union {
-         ADC_NCMR0_32B_tag NCMR[3];        /* offset: 0x00A4  (0x0004 x 3) */
-
-         struct {
-                                    /* NORMAL CONVERSION MASK REGISTER 0 */
-            ADC_NCMR0_32B_tag NCMR0;       /* offset: 0x00A4 size: 32 bit */
-                                    /* NORMAL CONVERSION MASK REGISTER 1 */
-            ADC_NCMR1_32B_tag NCMR1;       /* offset: 0x00A8 size: 32 bit */
-                                    /* NORMAL CONVERSION MASK REGISTER 2 */
-            ADC_NCMR2_32B_tag NCMR2;       /* offset: 0x00AC size: 32 bit */
-         };
-
-      };
-      int8_t ADC_reserved_00B0_C[4];
-      union {
-         ADC_JCMR0_32B_tag JCMR[3];        /* offset: 0x00B4  (0x0004 x 3) */
-
-         struct {
-                                  /* Injected Conversion Mask Register 0 */
-            ADC_JCMR0_32B_tag JCMR0;       /* offset: 0x00B4 size: 32 bit */
-                                  /* INJECTED CONVERSION MASK REGISTER 1 */
-            ADC_JCMR1_32B_tag JCMR1;       /* offset: 0x00B8 size: 32 bit */
-                                  /* INJECTED CONVERSION MASK REGISTER 2 */
-            ADC_JCMR2_32B_tag JCMR2;       /* offset: 0x00BC size: 32 bit */
-         };
-
-      };
-                                                 /* Offset Word Regsiter */
-      ADC_OFFWR_32B_tag OFFWR;             /* offset: 0x00C0 size: 32 bit */
-                                         /* Decode Signal Delay Register */
-      ADC_DSDR_32B_tag DSDR;               /* offset: 0x00C4 size: 32 bit */
-                                            /* Power Down Dealy Register */
-      ADC_PDEDR_32B_tag PDEDR;             /* offset: 0x00C8 size: 32 bit */
-      int8_t ADC_reserved_00CC_C[52];
-      union {
-                                                    /* CHANNEL DATA REGS */
-         ADC_CDR_32B_tag CDR[96];          /* offset: 0x0100  (0x0004 x 96) */
-
-         struct {
-                                                    /* CHANNEL DATA REGS */
-            ADC_CDR_32B_tag CDR0;          /* offset: 0x0100 size: 32 bit */
-            ADC_CDR_32B_tag CDR1;          /* offset: 0x0104 size: 32 bit */
-            ADC_CDR_32B_tag CDR2;          /* offset: 0x0108 size: 32 bit */
-            ADC_CDR_32B_tag CDR3;          /* offset: 0x010C size: 32 bit */
-            ADC_CDR_32B_tag CDR4;          /* offset: 0x0110 size: 32 bit */
-            ADC_CDR_32B_tag CDR5;          /* offset: 0x0114 size: 32 bit */
-            ADC_CDR_32B_tag CDR6;          /* offset: 0x0118 size: 32 bit */
-            ADC_CDR_32B_tag CDR7;          /* offset: 0x011C size: 32 bit */
-            ADC_CDR_32B_tag CDR8;          /* offset: 0x0120 size: 32 bit */
-            ADC_CDR_32B_tag CDR9;          /* offset: 0x0124 size: 32 bit */
-            ADC_CDR_32B_tag CDR10;         /* offset: 0x0128 size: 32 bit */
-            ADC_CDR_32B_tag CDR11;         /* offset: 0x012C size: 32 bit */
-            ADC_CDR_32B_tag CDR12;         /* offset: 0x0130 size: 32 bit */
-            ADC_CDR_32B_tag CDR13;         /* offset: 0x0134 size: 32 bit */
-            ADC_CDR_32B_tag CDR14;         /* offset: 0x0138 size: 32 bit */
-            ADC_CDR_32B_tag CDR15;         /* offset: 0x013C size: 32 bit */
-            ADC_CDR_32B_tag CDR16;         /* offset: 0x0140 size: 32 bit */
-            ADC_CDR_32B_tag CDR17;         /* offset: 0x0144 size: 32 bit */
-            ADC_CDR_32B_tag CDR18;         /* offset: 0x0148 size: 32 bit */
-            ADC_CDR_32B_tag CDR19;         /* offset: 0x014C size: 32 bit */
-            ADC_CDR_32B_tag CDR20;         /* offset: 0x0150 size: 32 bit */
-            ADC_CDR_32B_tag CDR21;         /* offset: 0x0154 size: 32 bit */
-            ADC_CDR_32B_tag CDR22;         /* offset: 0x0158 size: 32 bit */
-            ADC_CDR_32B_tag CDR23;         /* offset: 0x015C size: 32 bit */
-            ADC_CDR_32B_tag CDR24;         /* offset: 0x0160 size: 32 bit */
-            ADC_CDR_32B_tag CDR25;         /* offset: 0x0164 size: 32 bit */
-            ADC_CDR_32B_tag CDR26;         /* offset: 0x0168 size: 32 bit */
-            ADC_CDR_32B_tag CDR27;         /* offset: 0x016C size: 32 bit */
-            ADC_CDR_32B_tag CDR28;         /* offset: 0x0170 size: 32 bit */
-            ADC_CDR_32B_tag CDR29;         /* offset: 0x0174 size: 32 bit */
-            ADC_CDR_32B_tag CDR30;         /* offset: 0x0178 size: 32 bit */
-            ADC_CDR_32B_tag CDR31;         /* offset: 0x017C size: 32 bit */
-            ADC_CDR_32B_tag CDR32;         /* offset: 0x0180 size: 32 bit */
-            ADC_CDR_32B_tag CDR33;         /* offset: 0x0184 size: 32 bit */
-            ADC_CDR_32B_tag CDR34;         /* offset: 0x0188 size: 32 bit */
-            ADC_CDR_32B_tag CDR35;         /* offset: 0x018C size: 32 bit */
-            ADC_CDR_32B_tag CDR36;         /* offset: 0x0190 size: 32 bit */
-            ADC_CDR_32B_tag CDR37;         /* offset: 0x0194 size: 32 bit */
-            ADC_CDR_32B_tag CDR38;         /* offset: 0x0198 size: 32 bit */
-            ADC_CDR_32B_tag CDR39;         /* offset: 0x019C size: 32 bit */
-            ADC_CDR_32B_tag CDR40;         /* offset: 0x01A0 size: 32 bit */
-            ADC_CDR_32B_tag CDR41;         /* offset: 0x01A4 size: 32 bit */
-            ADC_CDR_32B_tag CDR42;         /* offset: 0x01A8 size: 32 bit */
-            ADC_CDR_32B_tag CDR43;         /* offset: 0x01AC size: 32 bit */
-            ADC_CDR_32B_tag CDR44;         /* offset: 0x01B0 size: 32 bit */
-            ADC_CDR_32B_tag CDR45;         /* offset: 0x01B4 size: 32 bit */
-            ADC_CDR_32B_tag CDR46;         /* offset: 0x01B8 size: 32 bit */
-            ADC_CDR_32B_tag CDR47;         /* offset: 0x01BC size: 32 bit */
-            ADC_CDR_32B_tag CDR48;         /* offset: 0x01C0 size: 32 bit */
-            ADC_CDR_32B_tag CDR49;         /* offset: 0x01C4 size: 32 bit */
-            ADC_CDR_32B_tag CDR50;         /* offset: 0x01C8 size: 32 bit */
-            ADC_CDR_32B_tag CDR51;         /* offset: 0x01CC size: 32 bit */
-            ADC_CDR_32B_tag CDR52;         /* offset: 0x01D0 size: 32 bit */
-            ADC_CDR_32B_tag CDR53;         /* offset: 0x01D4 size: 32 bit */
-            ADC_CDR_32B_tag CDR54;         /* offset: 0x01D8 size: 32 bit */
-            ADC_CDR_32B_tag CDR55;         /* offset: 0x01DC size: 32 bit */
-            ADC_CDR_32B_tag CDR56;         /* offset: 0x01E0 size: 32 bit */
-            ADC_CDR_32B_tag CDR57;         /* offset: 0x01E4 size: 32 bit */
-            ADC_CDR_32B_tag CDR58;         /* offset: 0x01E8 size: 32 bit */
-            ADC_CDR_32B_tag CDR59;         /* offset: 0x01EC size: 32 bit */
-            ADC_CDR_32B_tag CDR60;         /* offset: 0x01F0 size: 32 bit */
-            ADC_CDR_32B_tag CDR61;         /* offset: 0x01F4 size: 32 bit */
-            ADC_CDR_32B_tag CDR62;         /* offset: 0x01F8 size: 32 bit */
-            ADC_CDR_32B_tag CDR63;         /* offset: 0x01FC size: 32 bit */
-            ADC_CDR_32B_tag CDR64;         /* offset: 0x0200 size: 32 bit */
-            ADC_CDR_32B_tag CDR65;         /* offset: 0x0204 size: 32 bit */
-            ADC_CDR_32B_tag CDR66;         /* offset: 0x0208 size: 32 bit */
-            ADC_CDR_32B_tag CDR67;         /* offset: 0x020C size: 32 bit */
-            ADC_CDR_32B_tag CDR68;         /* offset: 0x0210 size: 32 bit */
-            ADC_CDR_32B_tag CDR69;         /* offset: 0x0214 size: 32 bit */
-            ADC_CDR_32B_tag CDR70;         /* offset: 0x0218 size: 32 bit */
-            ADC_CDR_32B_tag CDR71;         /* offset: 0x021C size: 32 bit */
-            ADC_CDR_32B_tag CDR72;         /* offset: 0x0220 size: 32 bit */
-            ADC_CDR_32B_tag CDR73;         /* offset: 0x0224 size: 32 bit */
-            ADC_CDR_32B_tag CDR74;         /* offset: 0x0228 size: 32 bit */
-            ADC_CDR_32B_tag CDR75;         /* offset: 0x022C size: 32 bit */
-            ADC_CDR_32B_tag CDR76;         /* offset: 0x0230 size: 32 bit */
-            ADC_CDR_32B_tag CDR77;         /* offset: 0x0234 size: 32 bit */
-            ADC_CDR_32B_tag CDR78;         /* offset: 0x0238 size: 32 bit */
-            ADC_CDR_32B_tag CDR79;         /* offset: 0x023C size: 32 bit */
-            ADC_CDR_32B_tag CDR80;         /* offset: 0x0240 size: 32 bit */
-            ADC_CDR_32B_tag CDR81;         /* offset: 0x0244 size: 32 bit */
-            ADC_CDR_32B_tag CDR82;         /* offset: 0x0248 size: 32 bit */
-            ADC_CDR_32B_tag CDR83;         /* offset: 0x024C size: 32 bit */
-            ADC_CDR_32B_tag CDR84;         /* offset: 0x0250 size: 32 bit */
-            ADC_CDR_32B_tag CDR85;         /* offset: 0x0254 size: 32 bit */
-            ADC_CDR_32B_tag CDR86;         /* offset: 0x0258 size: 32 bit */
-            ADC_CDR_32B_tag CDR87;         /* offset: 0x025C size: 32 bit */
-            ADC_CDR_32B_tag CDR88;         /* offset: 0x0260 size: 32 bit */
-            ADC_CDR_32B_tag CDR89;         /* offset: 0x0264 size: 32 bit */
-            ADC_CDR_32B_tag CDR90;         /* offset: 0x0268 size: 32 bit */
-            ADC_CDR_32B_tag CDR91;         /* offset: 0x026C size: 32 bit */
-            ADC_CDR_32B_tag CDR92;         /* offset: 0x0270 size: 32 bit */
-            ADC_CDR_32B_tag CDR93;         /* offset: 0x0274 size: 32 bit */
-            ADC_CDR_32B_tag CDR94;         /* offset: 0x0278 size: 32 bit */
-            ADC_CDR_32B_tag CDR95;         /* offset: 0x027C size: 32 bit */
-         };
-
-      };
-                    /* Upper Threshold register 4 is not contiguous to 3 */
-      ADC_THRHLR4_32B_tag THRHLR4;         /* offset: 0x0280 size: 32 bit */
-                                           /* Upper Threshold register 5 */
-      ADC_THRHLR5_32B_tag THRHLR5;         /* offset: 0x0284 size: 32 bit */
-                                           /* Upper Threshold register 6 */
-      ADC_THRHLR6_32B_tag THRHLR6;         /* offset: 0x0288 size: 32 bit */
-                                           /* Upper Threshold register 7 */
-      ADC_THRHLR7_32B_tag THRHLR7;         /* offset: 0x028C size: 32 bit */
-                                           /* Upper Threshold register 8 */
-      ADC_THRHLR8_32B_tag THRHLR8;         /* offset: 0x0290 size: 32 bit */
-                                           /* Upper Threshold register 9 */
-      ADC_THRHLR9_32B_tag THRHLR9;         /* offset: 0x0294 size: 32 bit */
-                                          /* Upper Threshold register 10 */
-      ADC_THRHLR10_32B_tag THRHLR10;       /* offset: 0x0298 size: 32 bit */
-                                          /* Upper Threshold register 11 */
-      ADC_THRHLR11_32B_tag THRHLR11;       /* offset: 0x029C size: 32 bit */
-                                          /* Upper Threshold register 12 */
-      ADC_THRHLR12_32B_tag THRHLR12;       /* offset: 0x02A0 size: 32 bit */
-                                          /* Upper Threshold register 13 */
-      ADC_THRHLR13_32B_tag THRHLR13;       /* offset: 0x02A4 size: 32 bit */
-                                          /* Upper Threshold register 14 */
-      ADC_THRHLR14_32B_tag THRHLR14;       /* offset: 0x02A8 size: 32 bit */
-                                          /* Upper Threshold register 15 */
-      ADC_THRHLR15_32B_tag THRHLR15;       /* offset: 0x02AC size: 32 bit */
-      union {
-                                     /* Channel Watchdog Select register */
-         ADC_CWSELR_32B_tag CWSELR[12];    /* offset: 0x02B0  (0x0004 x 12) */
-
-         struct {
-                                     /* Channel Watchdog Select register */
-            ADC_CWSELR_32B_tag CWSELR0;    /* offset: 0x02B0 size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR1;    /* offset: 0x02B4 size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR2;    /* offset: 0x02B8 size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR3;    /* offset: 0x02BC size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR4;    /* offset: 0x02C0 size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR5;    /* offset: 0x02C4 size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR6;    /* offset: 0x02C8 size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR7;    /* offset: 0x02CC size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR8;    /* offset: 0x02D0 size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR9;    /* offset: 0x02D4 size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR10;   /* offset: 0x02D8 size: 32 bit */
-            ADC_CWSELR_32B_tag CWSELR11;   /* offset: 0x02DC size: 32 bit */
-         };
-
-      };
-      union {
-                                     /* Channel Watchdog Enable Register */
-         ADC_CWENR_32B_tag CWENR[3];       /* offset: 0x02E0  (0x0004 x 3) */
-
-         struct {
-                                     /* Channel Watchdog Enable Register */
-            ADC_CWENR_32B_tag CWENR0;      /* offset: 0x02E0 size: 32 bit */
-            ADC_CWENR_32B_tag CWENR1;      /* offset: 0x02E4 size: 32 bit */
-            ADC_CWENR_32B_tag CWENR2;      /* offset: 0x02E8 size: 32 bit */
-         };
-
-      };
-      int8_t ADC_reserved_02EC_C[4];
-      union {
-                                /* Analog Watchdog Out of Range Register */
-         ADC_AWORR_32B_tag AWORR[3];       /* offset: 0x02F0  (0x0004 x 3) */
-
-         struct {
-                                /* Analog Watchdog Out of Range Register */
-            ADC_AWORR_32B_tag AWORR0;      /* offset: 0x02F0 size: 32 bit */
-            ADC_AWORR_32B_tag AWORR1;      /* offset: 0x02F4 size: 32 bit */
-            ADC_AWORR_32B_tag AWORR2;      /* offset: 0x02F8 size: 32 bit */
-         };
-
-      };
-      int8_t ADC_reserved_02FC[68];
-                                   /* SELF TEST CONFIGURATION REGISTER 1 */
-      ADC_STCR1_32B_tag STCR1;             /* offset: 0x0340 size: 32 bit */
-                                   /* SELF TEST CONFIGURATION REGISTER 2 */
-      ADC_STCR2_32B_tag STCR2;             /* offset: 0x0344 size: 32 bit */
-                                   /* SELF TEST CONFIGURATION REGISTER 3 */
-      ADC_STCR3_32B_tag STCR3;             /* offset: 0x0348 size: 32 bit */
-                                         /* SELF TEST BAUD RATE REGISTER */
-      ADC_STBRR_32B_tag STBRR;             /* offset: 0x034C size: 32 bit */
-                                          /* SELF TEST STATUS REGISTER 1 */
-      ADC_STSR1_32B_tag STSR1;             /* offset: 0x0350 size: 32 bit */
-                                          /* SELF TEST STATUS REGISTER 2 */
-      ADC_STSR2_32B_tag STSR2;             /* offset: 0x0354 size: 32 bit */
-                                          /* SELF TEST STATUS REGISTER 3 */
-      ADC_STSR3_32B_tag STSR3;             /* offset: 0x0358 size: 32 bit */
-                                          /* SELF TEST STATUS REGISTER 4 */
-      ADC_STSR4_32B_tag STSR4;             /* offset: 0x035C size: 32 bit */
-      int8_t ADC_reserved_0360[16];
-                                            /* SELF TEST DATA REGISTER 1 */
-      ADC_STDR1_32B_tag STDR1;             /* offset: 0x0370 size: 32 bit */
-                                            /* SELF TEST DATA REGISTER 2 */
-      ADC_STDR2_32B_tag STDR2;             /* offset: 0x0374 size: 32 bit */
-      int8_t ADC_reserved_0378[8];
-                                 /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
-      ADC_STAW0R_32B_tag STAW0R;           /* offset: 0x0380 size: 32 bit */
-                                /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
-      ADC_STAW1AR_32B_tag STAW1AR;         /* offset: 0x0384 size: 32 bit */
-                                /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
-      ADC_STAW1BR_32B_tag STAW1BR;         /* offset: 0x0388 size: 32 bit */
-                                 /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
-      ADC_STAW2R_32B_tag STAW2R;           /* offset: 0x038C size: 32 bit */
-                                 /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
-      ADC_STAW3R_32B_tag STAW3R;           /* offset: 0x0390 size: 32 bit */
-                                 /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
-      ADC_STAW4R_32B_tag STAW4R;           /* offset: 0x0394 size: 32 bit */
-                                 /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
-      ADC_STAW5R_32B_tag STAW5R;           /* offset: 0x0398 size: 32 bit */
-   } ADC_tag;
-
-
-#define ADC0  (*(volatile ADC_tag *) 0xFFE00000UL)
-#define ADC1  (*(volatile ADC_tag *) 0xFFE04000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: CTU  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* Trigger Generator Subunit Input Selection register */
-      vuint32_t R;
-      struct {
-         vuint32_t  I15_FE:1;          /* ext_signal Falling Edge */
-         vuint32_t  I15_RE:1;          /* ext_signal Rising  Edge */
-         vuint32_t  I14_FE:1;          /* eTimer2 Falling Edge Enable */
-         vuint32_t  I14_RE:1;          /* eTimer2 Rising  Edge Enable */
-         vuint32_t  I13_FE:1;          /* eTimer1 Falling Edge Enable */
-         vuint32_t  I13_RE:1;          /* eTimer1 Rising  Edge Enable */
-         vuint32_t  I12_FE:1;          /* RPWM ch3 Falling Edge Enable */
-         vuint32_t  I12_RE:1;          /* RPWM ch3 Rising  Edge Enable */
-         vuint32_t  I11_FE:1;          /* RPWM ch2 Falling Edge Enable */
-         vuint32_t  I11_RE:1;          /* RPWM ch2 Rising  Edge Enable */
-         vuint32_t  I10_FE:1;          /* RPWM ch1 Falling Edge Enable */
-         vuint32_t  I10_RE:1;          /* RPWM ch1 Rising  Edge Enable */
-         vuint32_t  I9_FE:1;           /* RPWM ch0 Falling Edge Enable */
-         vuint32_t  I9_RE:1;           /* RPWM ch0 Rising  Edge Enable */
-         vuint32_t  I8_FE:1;           /* PWM ch3 even trig Falling edge Enable */
-         vuint32_t  I8_RE:1;           /* PWM ch3 even trig Rising  edge Enable */
-         vuint32_t  I7_FE:1;           /* PWM ch2 even trig Falling edge Enable */
-         vuint32_t  I7_RE:1;           /* PWM ch2 even trig Rising  edge Enable */
-         vuint32_t  I6_FE:1;           /* PWM ch1 even trig Falling edge Enable */
-         vuint32_t  I6_RE:1;           /* PWM ch1 even trig Rising  edge Enable */
-         vuint32_t  I5_FE:1;           /* PWM ch0 even trig Falling edge Enable */
-         vuint32_t  I5_RE:1;           /* PWM ch0 even trig Rising edge Enable */
-         vuint32_t  I4_FE:1;           /* PWM ch3 odd trig Falling edge Enable */
-         vuint32_t  I4_RE:1;           /* PWM ch3 odd trig Rising  edge Enable */
-         vuint32_t  I3_FE:1;           /* PWM ch2 odd trig Falling edge Enable */
-         vuint32_t  I3_RE:1;           /* PWM ch2 odd trig Rising  edge Enable */
-         vuint32_t  I2_FE:1;           /* PWM ch1 odd trig Falling edge Enable */
-         vuint32_t  I2_RE:1;           /* PWM ch1 odd trig Rising  edge Enable */
-         vuint32_t  I1_FE:1;           /* PWM ch0 odd trig Falling edge Enable */
-         vuint32_t  I1_RE:1;           /* PWM ch0 odd trig Rising  edge Enable */
-         vuint32_t  I0_FE:1;           /* PWM Reload Falling Edge Enable */
-         vuint32_t  I0_RE:1;           /* PWM Reload Rising  Edge Enable */
-      } B;
-   } CTU_TGSISR_32B_tag;
-
-   typedef union {   /* Trigger Generator Subunit Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:7;
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  ET_TM:1;           /* Toggle Mode Enable */
-#else
-         vuint16_t  ETTM:1;              /* deprecated name - please avoid */
-#endif
-         vuint16_t  PRES:2;            /* TGS Prescaler Selection */
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  MRS_SM:5;          /* MRS Selection in Sequential Mode */
-#else
-         vuint16_t  MRSSM:5;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  TGS_M:1;           /* Trigger Generator Subunit Mode */
-#else
-         vuint16_t  TGSM:1;              /* deprecated name - please avoid */
-#endif
-      } B;
-   } CTU_TGSCR_16B_tag;
-
-   typedef union {   /*  */
-      vuint16_t R;
-   } CTU_TCR_16B_tag;
-
-   typedef union {   /* TGS Counter Compare Register */
-      vuint16_t R;
-#ifndef USE_FIELD_ALIASES_CTU
-      struct {
-         vuint16_t  TGSCCV:16;         /* deprecated field -- do not use */
-      } B;
-#endif
-   } CTU_TGSCCR_16B_tag;
-
-   typedef union {   /* TGS Counter Reload Register */
-      vuint16_t R;
-#ifndef USE_FIELD_ALIASES_CTU
-      struct {
-         vuint16_t  TGSCRV:16;         /* deprecated field -- do not use */
-      } B;
-#endif
-   } CTU_TGSCRR_16B_tag;
-
-   typedef union {   /* Commands List Control Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t:3;
-         vuint32_t  T3INDEX:5;         /* Trigger 3 First Command address */
-         vuint32_t:3;
-         vuint32_t  T2INDEX:5;         /* Trigger 2 First Command address */
-         vuint32_t:3;
-         vuint32_t  T1INDEX:5;         /* Trigger 1 First Command address */
-         vuint32_t:3;
-         vuint32_t  T0INDEX:5;         /* Trigger 0 First Command address */
-      } B;
-   } CTU_CLCR1_32B_tag;
-
-   typedef union {   /* Commands List Control Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t:3;
-         vuint32_t  T7INDEX:5;         /* Trigger 7 First Command address */
-         vuint32_t:3;
-         vuint32_t  T6INDEX:5;         /* Trigger 6 First Command address */
-         vuint32_t:3;
-         vuint32_t  T5INDEX:5;         /* Trigger 5 First Command address */
-         vuint32_t:3;
-         vuint32_t  T4INDEX:5;         /* Trigger 4 First Command address */
-      } B;
-   } CTU_CLCR2_32B_tag;
-
-   typedef union {   /* Trigger Handler Control Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t:1;
-         vuint32_t  T3_E:1;            /* Trigger 3 enable */
-         vuint32_t  T3_ETE:1;          /* Trigger 3 Ext Trigger output enable */
-         vuint32_t  T3_T4E:1;          /* Trigger 3 Timer4 output enable */
-         vuint32_t  T3_T3E:1;          /* Trigger 3 Timer3 output enable */
-         vuint32_t  T3_T2E:1;          /* Trigger 3 Timer2 output enable */
-         vuint32_t  T3_T1E:1;          /* Trigger 3 Timer1 output enable */
-         vuint32_t  T3_ADCE:1;         /* Trigger 3 ADC Command output enable */
-         vuint32_t:1;
-         vuint32_t  T2_E:1;            /* Trigger 2 enable */
-         vuint32_t  T2_ETE:1;          /* Trigger 2 Ext Trigger output enable */
-         vuint32_t  T2_T4E:1;          /* Trigger 2 Timer4 output enable */
-         vuint32_t  T2_T3E:1;          /* Trigger 2 Timer3 output enable */
-         vuint32_t  T2_T2E:1;          /* Trigger 2 Timer2 output enable */
-         vuint32_t  T2_T1E:1;          /* Trigger 2 Timer1 output enable */
-         vuint32_t  T2_ADCE:1;         /* Trigger 2 ADC Command output enable */
-         vuint32_t:1;
-         vuint32_t  T1_E:1;            /* Trigger 1 enable */
-         vuint32_t  T1_ETE:1;          /* Trigger 1 Ext Trigger output enable */
-         vuint32_t  T1_T4E:1;          /* Trigger 1 Timer4 output enable */
-         vuint32_t  T1_T3E:1;          /* Trigger 1 Timer3 output enable */
-         vuint32_t  T1_T2E:1;          /* Trigger 1 Timer2 output enable */
-         vuint32_t  T1_T1E:1;          /* Trigger 1 Timer1 output enable */
-         vuint32_t  T1_ADCE:1;         /* Trigger 1 ADC Command output enable */
-         vuint32_t:1;
-         vuint32_t  T0_E:1;            /* Trigger 0 enable */
-         vuint32_t  T0_ETE:1;          /* Trigger 0 Ext Trigger output enable */
-         vuint32_t  T0_T4E:1;          /* Trigger 0 Timer4 output enable */
-         vuint32_t  T0_T3E:1;          /* Trigger 0 Timer3 output enable */
-         vuint32_t  T0_T2E:1;          /* Trigger 0 Timer2 output enable */
-         vuint32_t  T0_T1E:1;          /* Trigger 0 Timer1 output enable */
-         vuint32_t  T0_ADCE:1;         /* Trigger 0 ADC Command output enable */
-      } B;
-   } CTU_THCR1_32B_tag;
-
-   typedef union {   /* Trigger Handler Control Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t:1;
-         vuint32_t  T7_E:1;            /* Trigger 7 enable */
-         vuint32_t  T7_ETE:1;          /* Trigger 7 Ext Trigger output enable */
-         vuint32_t  T7_T4E:1;          /* Trigger 7 Timer4 output enable */
-         vuint32_t  T7_T3E:1;          /* Trigger 7 Timer3 output enable */
-         vuint32_t  T7_T2E:1;          /* Trigger 7 Timer2 output enable */
-         vuint32_t  T7_T1E:1;          /* Trigger 7 Timer1 output enable */
-         vuint32_t  T7_ADCE:1;         /* Trigger 7 ADC Command output enable */
-         vuint32_t:1;
-         vuint32_t  T6_E:1;            /* Trigger 6 enable */
-         vuint32_t  T6_ETE:1;          /* Trigger 6 Ext Trigger output enable */
-         vuint32_t  T6_T4E:1;          /* Trigger 6 Timer4 output enable */
-         vuint32_t  T6_T3E:1;          /* Trigger 6 Timer3 output enable */
-         vuint32_t  T6_T2E:1;          /* Trigger 6 Timer2 output enable */
-         vuint32_t  T6_T1E:1;          /* Trigger 6 Timer1 output enable */
-         vuint32_t  T6_ADCE:1;         /* Trigger 6 ADC Command output enable */
-         vuint32_t:1;
-         vuint32_t  T5_E:1;            /* Trigger 5 enable */
-         vuint32_t  T5_ETE:1;          /* Trigger 5 Ext Trigger output enable */
-         vuint32_t  T5_T4E:1;          /* Trigger 5 Timer4 output enable */
-         vuint32_t  T5_T3E:1;          /* Trigger 5 Timer3 output enable */
-         vuint32_t  T5_T2E:1;          /* Trigger 5 Timer2 output enable */
-         vuint32_t  T5_T1E:1;          /* Trigger 5 Timer1 output enable */
-         vuint32_t  T5_ADCE:1;         /* Trigger 5 ADC Command output enable */
-         vuint32_t:1;
-         vuint32_t  T4_E:1;            /* Trigger 4 enable */
-         vuint32_t  T4_ETE:1;          /* Trigger 4 Ext Trigger output enable */
-         vuint32_t  T4_T4E:1;          /* Trigger 4 Timer4 output enable */
-         vuint32_t  T4_T3E:1;          /* Trigger 4 Timer3 output enable */
-         vuint32_t  T4_T2E:1;          /* Trigger 4 Timer2 output enable */
-         vuint32_t  T4_T1E:1;          /* Trigger 4 Timer1 output enable */
-         vuint32_t  T4_ADCE:1;         /* Trigger 4 ADC Command output enable */
-      } B;
-   } CTU_THCR2_32B_tag;
-
-
-   /* Register layout for all registers CLR_DCM... */
-
-   typedef union {   /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
-      vuint16_t R;
-      struct {
-         vuint16_t  CIR:1;             /* Command Interrupt Request */
-         vuint16_t  LC:1;              /* Last Command */
-         vuint16_t  CMS:1;             /* Conversion Mode Selection */
-         vuint16_t  FIFO:3;            /* FIFO for ADC A/B */
-         vuint16_t:1;
-         vuint16_t  CHB:4;             /* ADC unit B channel number */
-         vuint16_t:1;
-         vuint16_t  CHA:4;             /* ADC unit A channel number */
-      } B;
-   } CTU_CLR_DCM_16B_tag;
-
-
-   /* Register layout for all registers CLR_SCM... */
-
-   typedef union {   /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
-      vuint16_t R;
-      struct {
-         vuint16_t  CIR:1;             /* Command Interrupt Request */
-         vuint16_t  LC:1;              /* Last Command */
-         vuint16_t  CMS:1;             /* Conversion Mode Selection */
-         vuint16_t  FIFO:3;            /* FIFO for ADC A/B */
-         vuint16_t:4;
-         vuint16_t  SU:1;              /* Selection ADC Unit */
-         vuint16_t:1;
-         vuint16_t  CH:4;              /* ADC unit channel number */
-      } B;
-   } CTU_CLR_SCM_16B_tag;
-
-
-   /* Register layout for all registers CLR... */
-
-
-   typedef union {   /* Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  EMPTY_CLR7:1;      /* Empty Clear 7 */
-         vuint16_t  EMPTY_CLR6:1;      /* Empty Clear 6 */
-         vuint16_t  EMPTY_CLR5:1;      /* Empty Clear 5 */
-         vuint16_t  EMPTY_CLR4:1;      /* Empty Clear 4 */
-         vuint16_t  EMPTY_CLR3:1;      /* Empty Clear 3 */
-         vuint16_t  EMPTY_CLR2:1;      /* Empty Clear 2 */
-         vuint16_t  EMPTY_CLR1:1;      /* Empty Clear 1 */
-         vuint16_t  EMPTY_CLR0:1;      /* Empty Clear 0 */
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  DMA_EN7:1;         /* Enable DMA interface for FIFO 7 */
-#else
-         vuint16_t  DMAEN7:1;         /* Enable DMA interface for FIFO 7 */	
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  DMA_EN6:1;         /* Enable DMA interface for FIFO 6 */
-#else
-         vuint16_t  DMAEN6:1;         /* Enable DMA interface for FIFO 6 */	
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  DMA_EN5:1;         /* Enable DMA interface for FIFO 5 */
-#else
-         vuint16_t  DMAEN5:1;         /* Enable DMA interface for FIFO 5 */	
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  DMA_EN4:1;         /* Enable DMA interface for FIFO 4 */
-#else
-         vuint16_t  DMAEN4:1;         /* Enable DMA interface for FIFO 4 */	
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  DMA_EN3:1;         /* Enable DMA interface for FIFO 3 */
-#else
-         vuint16_t  DMAEN3:1;         /* Enable DMA interface for FIFO 3 */	
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  DMA_EN2:1;         /* Enable DMA interface for FIFO 2 */
-#else
-         vuint16_t  DMAEN2:1;         /* Enable DMA interface for FIFO 2 */	
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  DMA_EN1:1;         /* Enable DMA interface for FIFO 1 */
-#else
-         vuint16_t  DMAEN1:1;         /* Enable DMA interface for FIFO 1 */	
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  DMA_EN0:1;         /* Enable DMA interface for FIFO 0 */
-#else
-         vuint16_t  DMAEN0:1;         /* Enable DMA interface for FIFO 0 */	
-#endif
-      } B;
-   } CTU_CR_16B_tag;
-
-   typedef union {   /* Control Register FIFO */
-      vuint32_t R;
-      struct {
-         vuint32_t  FIFO_OVERRUN_EN7:1;   /* FIFO 7 OVERRUN  Enable Interrupt */
-         vuint32_t  FIFO_OVERFLOW_EN7:1;   /* FIFO 7 OVERFLOW Enable Interrupt */
-         vuint32_t  FIFO_EMPTY_EN7:1;   /* FIFO 7 EMPTY Enable Interrupt */
-         vuint32_t  FIFO_FULL_EN7:1;   /* FIFO 7 FULL Enable Interrupt */
-         vuint32_t  FIFO_OVERRUN_EN6:1;   /* FIFO 6 OVERRUN  Enable Interrupt */
-         vuint32_t  FIFO_OVERFLOW_EN6:1;   /* FIFO 6 OVERFLOW Enable Interrupt */
-         vuint32_t  FIFO_EMPTY_EN6:1;   /* FIFO 6 EMPTY Enable Interrupt */
-         vuint32_t  FIFO_FULL_EN6:1;   /* FIFO 6 FULL Enable Interrupt */
-         vuint32_t  FIFO_OVERRUN_EN5:1;   /* FIFO 5 OVERRUN  Enable Interrupt */
-         vuint32_t  FIFO_OVERFLOW_EN5:1;   /* FIFO 5 OVERFLOW Enable Interrupt */
-         vuint32_t  FIFO_EMPTY_EN5:1;   /* FIFO 5 EMPTY Enable Interrupt */
-         vuint32_t  FIFO_FULL_EN5:1;   /* FIFO 5 FULL Enable Interrupt */
-         vuint32_t  FIFO_OVERRUN_EN4:1;   /* FIFO 4 OVERRUN  Enable Interrupt */
-         vuint32_t  FIFO_OVERFLOW_EN4:1;   /* FIFO 4 OVERFLOW Enable Interrupt */
-         vuint32_t  FIFO_EMPTY_EN4:1;   /* FIFO 4 EMPTY Enable Interrupt */
-         vuint32_t  FIFO_FULL_EN4:1;   /* FIFO 4 FULL Enable Interrupt */
-         vuint32_t  FIFO_OVERRUN_EN3:1;   /* FIFO 3 OVERRUN  Enable Interrupt */
-         vuint32_t  FIFO_OVERFLOW_EN3:1;   /* FIFO 3 OVERFLOW Enable Interrupt */
-         vuint32_t  FIFO_EMPTY_EN3:1;   /* FIFO 3 EMPTY Enable Interrupt */
-         vuint32_t  FIFO_FULL_EN3:1;   /* FIFO 3 FULL Enable Interrupt */
-         vuint32_t  FIFO_OVERRUN_EN2:1;   /* FIFO 2 OVERRUN  Enable Interrupt */
-         vuint32_t  FIFO_OVERFLOW_EN2:1;   /* FIFO 2 OVERFLOW Enable Interrupt */
-         vuint32_t  FIFO_EMPTY_EN2:1;   /* FIFO 2 EMPTY Enable Interrupt */
-         vuint32_t  FIFO_FULL_EN2:1;   /* FIFO 2 FULL Enable Interrupt */
-         vuint32_t  FIFO_OVERRUN_EN1:1;   /* FIFO 1 OVERRUN  Enable Interrupt */
-         vuint32_t  FIFO_OVERFLOW_EN1:1;   /* FIFO 1 OVERFLOW Enable Interrupt */
-         vuint32_t  FIFO_EMPTY_EN1:1;   /* FIFO 1 EMPTY Enable Interrupt */
-         vuint32_t  FIFO_FULL_EN1:1;   /* FIFO 1 FULL Enable Interrupt */
-         vuint32_t  FIFO_OVERRUN_EN0:1;   /* FIFO 0 OVERRUN  Enable Interrupt */
-         vuint32_t  FIFO_OVERFLOW_EN0:1;   /* FIFO 0 OVERFLOW Enable Interrupt */
-         vuint32_t  FIFO_EMPTY_EN0:1;   /* FIFO 0 EMPTY Enable Interrupt */
-         vuint32_t  FIFO_FULL_EN0:1;   /* FIFO 0 FULL Enable Interrupt */
-      } B;
-   } CTU_FCR_32B_tag;
-
-   typedef union {   /* Threshold 1 Register */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint32_t  TRESHOLD3:8;       /* Threshlod FIFO 3 */
-#else
-         vuint32_t  THRESHOLD3:8;       /* Threshlod FIFO 3 */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint32_t  TRESHOLD2:8;       /* Threshlod FIFO 2 */
-#else
-         vuint32_t  THRESHOLD2:8;       /* Threshlod FIFO 2 */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint32_t  TRESHOLD1:8;       /* Threshlod FIFO 1 */
-#else
-         vuint32_t  THRESHOLD1:8;       /* Threshlod FIFO 1 */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint32_t  TRESHOLD0:8;       /* Threshlod FIFO 0 */
-#else
-         vuint32_t  THRESHOLD0:8;       /* Threshlod FIFO 0 */
-#endif
-      } B;
-   } CTU_TH1_32B_tag;
-
-   typedef union {   /* Threshold 2 Register */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint32_t  TRESHOLD7:8;       /* Threshlod FIFO 7 */
-#else
-         vuint32_t  THRESHOLD7:8;       /* Threshlod FIFO 7 */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint32_t  TRESHOLD6:8;       /* Threshlod FIFO 6 */
-#else
-         vuint32_t  THRESHOLD6:8;       /* Threshlod FIFO 6 */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint32_t  TRESHOLD5:8;       /* Threshlod FIFO 5 */
-#else
-         vuint32_t  THRESHOLD5:8;       /* Threshlod FIFO 5 */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint32_t  TRESHOLD4:8;       /* Threshlod FIFO 4 */
-#else
-         vuint32_t  THRESHOLD4:8;       /* Threshlod FIFO 4 */
-#endif
-      } B;
-   } CTU_TH2_32B_tag;
-
-   typedef union {   /* Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  FIFO_OVERRUN7:1;   /* FIFO 7 OVERRUN  Flag */
-         vuint32_t  FIFO_OVERFLOW7:1;   /* FIFO 7 OVERFLOW Flag */
-         vuint32_t  FIFO_EMPTY7:1;     /* FIFO 7 EMPTY Flag */
-         vuint32_t  FIFO_FULL7:1;      /* FIFO 7 FULL Flag */
-         vuint32_t  FIFO_OVERRUN6:1;   /* FIFO 6 OVERRUN  Flag */
-         vuint32_t  FIFO_OVERFLOW6:1;   /* FIFO 6 OVERFLOW Flag */
-         vuint32_t  FIFO_EMPTY6:1;     /* FIFO 6 EMPTY Flag */
-         vuint32_t  FIFO_FULL6:1;      /* FIFO 6 FULL Flag */
-         vuint32_t  FIFO_OVERRUN5:1;   /* FIFO 5 OVERRUN  Flag */
-         vuint32_t  FIFO_OVERFLOW5:1;   /* FIFO 5 OVERFLOW Flag */
-         vuint32_t  FIFO_EMPTY5:1;     /* FIFO 5 EMPTY Flag */
-         vuint32_t  FIFO_FULL5:1;      /* FIFO 5 FULL Flag */
-         vuint32_t  FIFO_OVERRUN4:1;   /* FIFO 4 OVERRUN  Flag */
-         vuint32_t  FIFO_OVERFLOW4:1;   /* FIFO 4 OVERFLOW Flag */
-         vuint32_t  FIFO_EMPTY4:1;     /* FIFO 4 EMPTY Flag */
-         vuint32_t  FIFO_FULL4:1;      /* FIFO 4 FULL Flag */
-         vuint32_t  FIFO_OVERRUN3:1;   /* FIFO 3 OVERRUN  Flag */
-         vuint32_t  FIFO_OVERFLOW3:1;   /* FIFO 3 OVERFLOW Flag */
-         vuint32_t  FIFO_EMPTY3:1;     /* FIFO 3 EMPTY Flag */
-         vuint32_t  FIFO_FULL3:1;      /* FIFO 3 FULL Flag */
-         vuint32_t  FIFO_OVERRUN2:1;   /* FIFO 2 OVERRUN  Flag */
-         vuint32_t  FIFO_OVERFLOW2:1;   /* FIFO 2 OVERFLOW Flag */
-         vuint32_t  FIFO_EMPTY2:1;     /* FIFO 2 EMPTY Flag */
-         vuint32_t  FIFO_FULL2:1;      /* FIFO 2 FULL Flag */
-         vuint32_t  FIFO_OVERRUN1:1;   /* FIFO 1 OVERRUN  Flag */
-         vuint32_t  FIFO_OVERFLOW1:1;   /* FIFO 1 OVERFLOW Flag */
-         vuint32_t  FIFO_EMPTY1:1;     /* FIFO 1 EMPTY Flag */
-         vuint32_t  FIFO_FULL1:1;      /* FIFO 1 FULL Flag */
-         vuint32_t  FIFO_OVERRUN0:1;   /* FIFO 0 OVERRUN  Flag */
-         vuint32_t  FIFO_OVERFLOW0:1;   /* FIFO 0 OVERFLOW Flag */
-         vuint32_t  FIFO_EMPTY0:1;     /* FIFO 0 EMPTY Flag */
-         vuint32_t  FIFO_FULL0:1;      /* FIFO 0 FULL Flag */
-      } B;
-   } CTU_STS_32B_tag;
-
-
-   /* Register layout for all registers FR... */
-
-   typedef union {   /* FIFO Right Aligned register */
-      vuint32_t R;
-      struct {
-         vuint32_t:11;
-         vuint32_t  ADC:1;             /* ADC Unit */
-         vuint32_t  N_CH:4;            /* Number Channel */
-         vuint32_t:4;
-         vuint32_t  DATA:12;           /* Data Fifo */
-      } B;
-   } CTU_FR_32B_tag;
-
-
-   /* Register layout for all registers FL... */
-
-   typedef union {   /* FIFO Left Aligned register */
-      vuint32_t R;
-      struct {
-         vuint32_t:11;
-         vuint32_t  ADC:1;             /* ADC Unit */
-         vuint32_t  N_CH:4;            /* Number Channel */
-         vuint32_t:1;
-         vuint32_t  DATA:12;           /* Data Fifo */
-         vuint32_t:3;
-      } B;
-   } CTU_FL_32B_tag;
-
-   typedef union {   /* CTU Error Flag Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:3;
-         vuint16_t  CS:1;              /* Counter Status */
-         vuint16_t  ET_OE:1;           /* ExtTrigger Generation Overrun */
-         vuint16_t  ERR_CMP:1;         /* Set if counter reaches TGSCCR register */
-         vuint16_t  T4_OE:1;           /* Timer4 Generation Overrun */
-         vuint16_t  T3_OE:1;           /* Timer3 Generation Overrun */
-         vuint16_t  T2_OE:1;           /* Timer2 Generation Overrun */
-         vuint16_t  T1_OE:1;           /* Timer1 Generation Overrun */
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  ADC_OE:1;          /* ADC Command Generation Overrun */
-#else
-         vuint16_t  ADCOE:1;          /* ADC Command Generation Overrun */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  TGS_OSM:1;         /* TGS Overrun */
-#else
-         vuint16_t  TGSOSM:1;         /* TGS Overrun */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  MRS_O:1;           /* MRS Overrun */
-#else
-         vuint16_t  MRSO:1;         /* TGS Overrun */
-#endif
-         vuint16_t  ICE:1;             /* Invalid Command Error */
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  SM_TO:1;           /* Trigger Overrun */
-#else
-         vuint16_t  SMTO:1;        /* Trigger Overrun */
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  MRS_RE:1;          /* MRS Reload Error */
-#else
-         vuint16_t  MRSRE:1;        /* MRS Reload Error */
-#endif
-      } B;
-   } CTU_CTUEFR_16B_tag;
-
-   typedef union {   /* CTU Interrupt Flag Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:4;
-         vuint16_t  S_E_B:1;           /* Slice time OK */
-         vuint16_t  S_E_A:1;           /* Slice time OK */
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  ADC_I:1;           /* ADC Command Interrupt Flag */
-#else
-         vuint16_t  ADC:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T7_I:1;            /* Trigger 7  Interrupt Flag */
-#else
-         vuint16_t  T7:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T6_I:1;            /* Trigger 6  Interrupt Flag */
-#else
-         vuint16_t  T6:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T5_I:1;            /* Trigger 5  Interrupt Flag */
-#else
-         vuint16_t  T5:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T4_I:1;            /* Trigger 4  Interrupt Flag */
-#else
-         vuint16_t  T4:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T3_I:1;            /* Trigger 3  Interrupt Flag */
-#else
-         vuint16_t  T3:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T2_I:1;            /* Trigger 2  Interrupt Flag */
-#else
-         vuint16_t  T2:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T1_I:1;            /* Trigger 1  Interrupt Flag */
-#else
-         vuint16_t  T1:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T0_I:1;            /* Trigger 0  Interrupt Flag */
-#else
-         vuint16_t  T0:1;        
-#endif  
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  MRS_I:1;           /* MRS Interrupt Flag */
-#else
-         vuint16_t  MRS:1;        
-#endif
-      } B;
-   } CTU_CTUIFR_16B_tag;
-
-   typedef union {   /* CTU Interrupt/DMA Register */
-      vuint16_t R;
-      struct {       
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T7_I:1;            /* Trigger 7  Interrupt Enable */
-#else
-         vuint16_t  T7IE:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T6_I:1;            /* Trigger 6  Interrupt Enable */
-#else
-         vuint16_t  T6IE:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T5_I:1;            /* Trigger 5  Interrupt Enable */
-#else
-         vuint16_t  T5IE:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T4_I:1;            /* Trigger 4  Interrupt Enable */
-#else
-         vuint16_t  T4IE:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T3_I:1;            /* Trigger 3  Interrupt Enable */
-#else
-         vuint16_t  T3IE:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T2_I:1;            /* Trigger 2  Interrupt Enable */
-#else
-         vuint16_t  T2IE:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T1_I:1;            /* Trigger 1  Interrupt Enable */
-#else
-         vuint16_t  T1IE:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T0_I:1;            /* Trigger 0  Interrupt Enable */
-#else
-         vuint16_t  T0IE:1;        
-#endif
-         vuint16_t:2;
-         vuint16_t  SAF_CNT_B_EN:1;    /* Conversion time counter enabled */
-         vuint16_t  SAF_CNT_A_EN:1;    /* Conversion time counter enabled */
-         vuint16_t  DMA_DE:1;          /* DMA and gre bit */
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  MRS_DMAE:1;        /* DMA Transfer Enable */
-#else
-         vuint16_t  MRSDMAE:1;        
-#endif      
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  MRS_IE:1;          /* MRS Interrupt Enable */
-#else
-         vuint16_t  MRSIE:1;        
-#endif
-         vuint16_t  IEE:1;             /* Interrupt Error Enable */
-      } B;
-   } CTU_CTUIR_16B_tag;
-
-   typedef union {   /* Control On-Time Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:8;
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  COTR_COTR:8;       /* Control On-Time Register and Guard Time */
-#else
-         vuint16_t  COTR:8;        
-#endif
-      } B;
-   } CTU_COTR_16B_tag;
-
-   typedef union {   /* CTU Control Register */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T7_SG:1;           /* Trigger 7 Software Generated */
-#else
-         vuint16_t  T7SG:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T6_SG:1;           /* Trigger 6 Software Generated */
-#else
-         vuint16_t  T6SG:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T5_SG:1;           /* Trigger 5 Software Generated */
-#else
-         vuint16_t  T5SG:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T4_SG:1;           /* Trigger 4 Software Generated */
-#else
-         vuint16_t  T4SG:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T3_SG:1;           /* Trigger 3 Software Generated */
-#else
-         vuint16_t  T3SG:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T2_SG:1;           /* Trigger 2 Software Generated */
-#else
-         vuint16_t  T2SG:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T1_SG:1;           /* Trigger 1 Software Generated */
-#else
-         vuint16_t  T1SG:1;        
-#endif
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  T0_SG:1;           /* Trigger 0 Software Generated */
-#else
-         vuint16_t  T0SG:1;        
-#endif       
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  CTU_ADC_RESET:1;   /* CTU ADC State Machine Reset */
-#else
-         vuint16_t  CTUADCRESET:1;        
-#endif 
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  CTU_ODIS:1;        /* CTU Output Disable */
-#else
-         vuint16_t  CTUODIS:1;        
-#endif         
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  FILTER_EN:1;       /* Synchronize Filter Register value */
-#else
-         vuint16_t  FILTERENABLE:1;        
-#endif
-         vuint16_t  CGRE:1;            /* Clear GRE */
-         vuint16_t  FGRE:1;            /* GRE Flag */
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  MRS_SG:1;          /* MRS Software Generated */
-#else
-         vuint16_t  MRSSG:1;        
-#endif     
-         vuint16_t  GRE:1;             /* General Reload Enable */
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  TGSISR_RE:1;       /* TGSISR Reload Enable */
-#else
-         vuint16_t  TGSISRRE:1;        
-#endif        
-      } B;
-   } CTU_CTUCR_16B_tag;
-
-   typedef union {   /* CTU Digital Filter Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:8;
-#ifndef USE_FIELD_ALIASES_CTU
-         vuint16_t  FILTER_VALUE:8;    /* Filter Value */
-#else
-         vuint16_t  FILTERVALUE:8;       /* deprecated name - please avoid */
-#endif
-      } B;
-   } CTU_FILTER_16B_tag;
-
-   typedef union {   /* CTU Expected A Value Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  EXPECTED_A_VALUE:16;   /* Expected A Value */
-      } B;
-   } CTU_EXPECTED_A_16B_tag;
-
-   typedef union {   /* CTU Expected B Value Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  EXPECTED_B_VALUE:16;   /* Expected B Value */
-      } B;
-   } CTU_EXPECTED_B_16B_tag;
-
-   typedef union {   /* CTU Counter Range Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:8;
-         vuint16_t  CNT_RANGE_VALUE:8;   /* Counter Range Value */
-      } B;
-   } CTU_CNT_RANGE_16B_tag;
-
-
-   /* Register layout for generated register(s) FRA... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } CTU_FRA_32B_tag;
-
-
-   /* Register layout for generated register(s) FLA... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } CTU_FLA_32B_tag;
-
-
-
-   typedef struct CTU_struct_tag { /* start of CTU_tag */
-                   /* Trigger Generator Subunit Input Selection register */
-      CTU_TGSISR_32B_tag TGSISR;           /* offset: 0x0000 size: 32 bit */
-                           /* Trigger Generator Subunit Control Register */
-      CTU_TGSCR_16B_tag TGSCR;             /* offset: 0x0004 size: 16 bit */
-      union {
-         CTU_TCR_16B_tag TCR[8];           /* offset: 0x0006  (0x0002 x 8) */
-
-         struct {
-            CTU_TCR_16B_tag T0CR;          /* offset: 0x0006 size: 16 bit */
-            CTU_TCR_16B_tag T1CR;          /* offset: 0x0008 size: 16 bit */
-            CTU_TCR_16B_tag T2CR;          /* offset: 0x000A size: 16 bit */
-            CTU_TCR_16B_tag T3CR;          /* offset: 0x000C size: 16 bit */
-            CTU_TCR_16B_tag T4CR;          /* offset: 0x000E size: 16 bit */
-            CTU_TCR_16B_tag T5CR;          /* offset: 0x0010 size: 16 bit */
-            CTU_TCR_16B_tag T6CR;          /* offset: 0x0012 size: 16 bit */
-            CTU_TCR_16B_tag T7CR;          /* offset: 0x0014 size: 16 bit */
-         };
-
-      };
-                                         /* TGS Counter Compare Register */
-      CTU_TGSCCR_16B_tag TGSCCR;           /* offset: 0x0016 size: 16 bit */
-                                          /* TGS Counter Reload Register */
-      CTU_TGSCRR_16B_tag TGSCRR;           /* offset: 0x0018 size: 16 bit */
-      int8_t CTU_reserved_001A[2];
-                                     /* Commands List Control Register 1 */
-      CTU_CLCR1_32B_tag CLCR1;             /* offset: 0x001C size: 32 bit */
-                                     /* Commands List Control Register 2 */
-      CTU_CLCR2_32B_tag CLCR2;             /* offset: 0x0020 size: 32 bit */
-                                   /* Trigger Handler Control Register 1 */
-      CTU_THCR1_32B_tag THCR1;             /* offset: 0x0024 size: 32 bit */
-                                   /* Trigger Handler Control Register 2 */
-      CTU_THCR2_32B_tag THCR2;             /* offset: 0x0028 size: 32 bit */
-      union {
-                             /* Command List Register. View: BIT13, BIT9 */
-         CTU_CLR_SCM_16B_tag CLR[24];          /* offset: 0x002C  (0x0002 x 24) */ /* deprecated name - please avoid */
-
-       /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
-         CTU_CLR_SCM_16B_tag CLR_SCM[24];  /* offset: 0x002C  (0x0002 x 24) */
-
-       /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
-         CTU_CLR_DCM_16B_tag CLR_DCM[24];  /* offset: 0x002C  (0x0002 x 24) */
-
-         struct {
-       /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
-            CTU_CLR_SCM_16B_tag CLR_SCM1;  /* offset: 0x002C size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM2;  /* offset: 0x002E size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM3;  /* offset: 0x0030 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM4;  /* offset: 0x0032 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM5;  /* offset: 0x0034 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM6;  /* offset: 0x0036 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM7;  /* offset: 0x0038 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM8;  /* offset: 0x003A size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM9;  /* offset: 0x003C size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM10;  /* offset: 0x003E size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM11;  /* offset: 0x0040 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM12;  /* offset: 0x0042 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM13;  /* offset: 0x0044 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM14;  /* offset: 0x0046 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM15;  /* offset: 0x0048 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM16;  /* offset: 0x004A size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM17;  /* offset: 0x004C size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM18;  /* offset: 0x004E size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM19;  /* offset: 0x0050 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM20;  /* offset: 0x0052 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM21;  /* offset: 0x0054 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM22;  /* offset: 0x0056 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM23;  /* offset: 0x0058 size: 16 bit */
-            CTU_CLR_SCM_16B_tag CLR_SCM24;  /* offset: 0x005A size: 16 bit */
-         };
-
-         struct {
-       /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
-            CTU_CLR_DCM_16B_tag CLR_DCM1;  /* offset: 0x002C size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM2;  /* offset: 0x002E size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM3;  /* offset: 0x0030 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM4;  /* offset: 0x0032 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM5;  /* offset: 0x0034 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM6;  /* offset: 0x0036 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM7;  /* offset: 0x0038 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM8;  /* offset: 0x003A size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM9;  /* offset: 0x003C size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM10;  /* offset: 0x003E size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM11;  /* offset: 0x0040 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM12;  /* offset: 0x0042 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM13;  /* offset: 0x0044 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM14;  /* offset: 0x0046 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM15;  /* offset: 0x0048 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM16;  /* offset: 0x004A size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM17;  /* offset: 0x004C size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM18;  /* offset: 0x004E size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM19;  /* offset: 0x0050 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM20;  /* offset: 0x0052 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM21;  /* offset: 0x0054 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM22;  /* offset: 0x0056 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM23;  /* offset: 0x0058 size: 16 bit */
-            CTU_CLR_DCM_16B_tag CLR_DCM24;  /* offset: 0x005A size: 16 bit */
-         };
-
-      };
-      int8_t CTU_reserved_005C[16];
-                                                     /* Control Register */
-      CTU_CR_16B_tag CR;                   /* offset: 0x006C size: 16 bit */
-      int8_t CTU_reserved_006E[2];
-                                                /* Control Register FIFO */
-      CTU_FCR_32B_tag FCR;                 /* offset: 0x0070 size: 32 bit */
-                                                 /* Threshold 1 Register */
-      CTU_TH1_32B_tag TH1;                 /* offset: 0x0074 size: 32 bit */
-                                                 /* Threshold 2 Register */
-      CTU_TH2_32B_tag TH2;                 /* offset: 0x0078 size: 32 bit */
-      union {
-                                                      /* Status Register */
-         CTU_STS_32B_tag STS;              /* offset: 0x007C size: 32 bit */
-
-         CTU_STS_32B_tag STATUS;           /* deprecated - please avoid */
-
-      };
-      union {
-         CTU_FRA_32B_tag FRA[8];           /* offset: 0x0080  (0x0004 x 8) */
-
-                                          /* FIFO Right Aligned register */
-         CTU_FR_32B_tag FR[8];             /* offset: 0x0080  (0x0004 x 8) */
-
-         struct {
-                                          /* FIFO Right Aligned register */
-            CTU_FR_32B_tag FR0;            /* offset: 0x0080 size: 32 bit */
-            CTU_FR_32B_tag FR1;            /* offset: 0x0084 size: 32 bit */
-            CTU_FR_32B_tag FR2;            /* offset: 0x0088 size: 32 bit */
-            CTU_FR_32B_tag FR3;            /* offset: 0x008C size: 32 bit */
-            CTU_FR_32B_tag FR4;            /* offset: 0x0090 size: 32 bit */
-            CTU_FR_32B_tag FR5;            /* offset: 0x0094 size: 32 bit */
-            CTU_FR_32B_tag FR6;            /* offset: 0x0098 size: 32 bit */
-            CTU_FR_32B_tag FR7;            /* offset: 0x009C size: 32 bit */
-         };
-
-      };
-      union {
-         CTU_FLA_32B_tag FLA[8];           /* offset: 0x00A0  (0x0004 x 8) */
-
-                                           /* FIFO Left Aligned register */
-         CTU_FL_32B_tag FL[8];             /* offset: 0x00A0  (0x0004 x 8) */
-
-         struct {
-                                           /* FIFO Left Aligned register */
-            CTU_FL_32B_tag FL0;            /* offset: 0x00A0 size: 32 bit */
-            CTU_FL_32B_tag FL1;            /* offset: 0x00A4 size: 32 bit */
-            CTU_FL_32B_tag FL2;            /* offset: 0x00A8 size: 32 bit */
-            CTU_FL_32B_tag FL3;            /* offset: 0x00AC size: 32 bit */
-            CTU_FL_32B_tag FL4;            /* offset: 0x00B0 size: 32 bit */
-            CTU_FL_32B_tag FL5;            /* offset: 0x00B4 size: 32 bit */
-            CTU_FL_32B_tag FL6;            /* offset: 0x00B8 size: 32 bit */
-            CTU_FL_32B_tag FL7;            /* offset: 0x00BC size: 32 bit */
-         };
-
-      };
-                                              /* CTU Error Flag Register */
-      CTU_CTUEFR_16B_tag CTUEFR;           /* offset: 0x00C0 size: 16 bit */
-                                          /* CTU Interrupt Flag Register */
-      CTU_CTUIFR_16B_tag CTUIFR;           /* offset: 0x00C2 size: 16 bit */
-                                           /* CTU Interrupt/DMA Register */
-      CTU_CTUIR_16B_tag CTUIR;             /* offset: 0x00C4 size: 16 bit */
-                                             /* Control On-Time Register */
-      CTU_COTR_16B_tag COTR;               /* offset: 0x00C6 size: 16 bit */
-      /* CTU Control Register */
-      CTU_CTUCR_16B_tag CTUCR;             /* offset: 0x00C8 size: 16 bit */
-      union {
-                                          /* CTU Digital Filter Register */
-         CTU_FILTER_16B_tag FILTER;        /* offset: 0x00CA size: 16 bit */
-
-         CTU_FILTER_16B_tag CTUFILTER;     /* deprecated - please avoid */
-
-      };
-                                        /* CTU Expected A Value Register */
-      CTU_EXPECTED_A_16B_tag EXPECTED_A;  /* offset: 0x00CC size: 16 bit */
-
-                                        /* CTU Expected B Value Register */
-      CTU_EXPECTED_B_16B_tag EXPECTED_B;   /* offset: 0x00CE size: 16 bit */
-                                           /* CTU Counter Range Register */
-      CTU_CNT_RANGE_16B_tag CNT_RANGE;     /* offset: 0x00D0 size: 16 bit */
-   } CTU_tag;
-
-
-#define CTU   (*(volatile CTU_tag *) 0xFFE0C000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: mcTIMER  */
-/*                                                              */
-/****************************************************************/
-
-
-   /* Register layout for all registers COMP1... */
-
-   typedef union {   /* Compare Register 1 */
-      vuint16_t R;
-      struct {
-      vuint16_t COMP1:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_COMP1_16B_tag;
-
-
-   /* Register layout for all registers COMP2... */
-
-   typedef union {   /* Compare Register 2 */
-      vuint16_t R;
-      struct {
-      vuint16_t COMP2:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_COMP2_16B_tag;
-
-
-   /* Register layout for all registers CAPT1... */
-
-   typedef union {   /* Capture Register 1 */
-      vuint16_t R;
-      struct {
-      vuint16_t CAPT1:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_CAPT1_16B_tag;
-
-
-   /* Register layout for all registers CAPT2... */
-
-   typedef union {   /* Capture Register 2 */
-      vuint16_t R;
-      struct {
-      vuint16_t CAPT2:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_CAPT2_16B_tag;
-
-
-   /* Register layout for all registers LOAD... */
-
-   typedef union {   /* Load Register */
-      vuint16_t R;
-      struct {
-       vuint16_t LOAD:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_LOAD_16B_tag;
-
-
-   /* Register layout for all registers HOLD... */
-
-   typedef union {   /* Hold Register */
-      vuint16_t R;
-      struct {
-       vuint16_t HOLD:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_HOLD_16B_tag;
-
-
-   /* Register layout for all registers CNTR... */
-
-   typedef union {   /* Counter Register */
-      vuint16_t R;
-      struct {
-       vuint16_t CNTR:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_CNTR_16B_tag;
-
-
-   /* Register layout for all registers CTRL1... */
-
-   typedef union {   /* Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CNTMODE:3;         /* Count Mode */
-         vuint16_t  PRISRC:5;          /* Primary Count Source */
-         vuint16_t  ONCE:1;            /* Count Once */
-         vuint16_t  LENGTH:1;          /* Count Length */
-         vuint16_t  DIR:1;             /* Count Direction */
-         vuint16_t  SECSRC:5;          /* Secondary Count Source */
-      } B;
-   } mcTIMER_CTRL1_16B_tag;
-
-
-   /* Register layout for all registers CTRL2... */
-
-   typedef union {   /* Control Register 2 */
-      vuint16_t R;
-      struct {
-         vuint16_t  OEN:1;             /* Output Enable */
-         vuint16_t  RDNT:1;            /* Redundant Channel Enable */
-         vuint16_t  INPUT:1;           /* External Input Signal */
-         vuint16_t  VAL:1;             /* Forced OFLAG Value */
-         vuint16_t  FORCE:1;           /* Force the OFLAG output */
-         vuint16_t  COFRC:1;           /* Co-channel OFLAG Force */
-         vuint16_t  COINIT:2;          /* Co-channel Initialization */
-         vuint16_t  SIPS:1;            /* Secondary Source Input Polarity Select */
-         vuint16_t  PIPS:1;            /* Primary Source Input Polarity Select */
-         vuint16_t  OPS:1;             /* Output Polarity Select */
-         vuint16_t  MSTR:1;            /* Master Mode */
-         vuint16_t  OUTMODE:4;         /* Output Mode */
-      } B;
-   } mcTIMER_CTRL2_16B_tag;
-
-
-   /* Register layout for all registers CTRL3... */
-
-   typedef union {   /* Control Register 3 */
-      vuint16_t R;
-      struct {
-         vuint16_t  STPEN:1;           /* Stop Action Enable */
-         vuint16_t  ROC:2;             /* Reload On Capture */
-         vuint16_t  FMODE:1;           /* Fault Safing Mode */
-         vuint16_t  FDIS:4;            /* Fault Disable Mask */
-         vuint16_t  C2FCNT:3;          /* CAPT2 FIFO Word Count */
-         vuint16_t  C1FCNT:3;          /* CAPT1 FIFO Word Count */
-         vuint16_t  DBGEN:2;           /* Debug Actions Enable */
-      } B;
-   } mcTIMER_CTRL3_16B_tag;
-
-
-   /* Register layout for all registers STS... */
-
-   typedef union {   /* Status Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:6;
-         vuint16_t  WDF:1;             /* Watchdog Time-out Flag */
-         vuint16_t  RCF:1;             /* Redundant Channel Flag */
-         vuint16_t  ICF2:1;            /* Input Capture 2 Flag */
-         vuint16_t  ICF1:1;            /* Input Capture 1 Flag */
-         vuint16_t  IEHF:1;            /* Input Edge High Flag */
-         vuint16_t  IELF:1;            /* Input Edge Low Flag */
-         vuint16_t  TOF:1;             /* Timer Overflow Flag */
-         vuint16_t  TCF2:1;            /* Timer Compare 2 Flag */
-         vuint16_t  TCF1:1;            /* Timer Compare 1 Flag */
-         vuint16_t  TCF:1;             /* Timer Compare Flag */
-      } B;
-   } mcTIMER_STS_16B_tag;
-
-
-   /* Register layout for all registers INTDMA... */
-
-   typedef union {   /* Interrupt and DMA Enable Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  ICF2DE:1;          /* Input Capture 2 Flag DMA Enable */
-         vuint16_t  ICF1DE:1;          /* Input Capture 1 Flag DMA Enable */
-         vuint16_t  CMPLD2DE:1;        /* Comparator Load Register 2 Flag DMA Enable */
-         vuint16_t  CMPLD1DE:1;        /* Comparator Load Register 1 Flag DMA Enable */
-         vuint16_t:2;
-         vuint16_t  WDFIE:1;           /* Watchdog Flag Interrupt Enable */
-         vuint16_t  RCFIE:1;           /* Redundant Channel Flag Interrupt Enable */
-         vuint16_t  ICF2IE:1;          /* Input Capture 2 Flag Interrupt Enable */
-         vuint16_t  ICF1IE:1;          /* Input Capture 1 Flag Interrupt Enable */
-         vuint16_t  IEHFIE:1;          /* Input Edge High Flag Interrupt Enable */
-         vuint16_t  IELFIE:1;          /* Input Edge Low Flag Interrupt Enable */
-         vuint16_t  TOFIE:1;           /* Timer Overflow Flag Interrupt Enable */
-         vuint16_t  TCF2IE:1;          /* Timer Compare 2 Flag Interrupt Enable */
-         vuint16_t  TCF1IE:1;          /* Timer Compare 1 Flag Interrupt Enable */
-         vuint16_t  TCFIE:1;           /* Timer Compare Flag Interrupt Enable */
-      } B;
-   } mcTIMER_INTDMA_16B_tag;
-
-
-   /* Register layout for all registers CMPLD1... */
-
-   typedef union {   /* Comparator Load Register 1 */
-      vuint16_t R;
-      struct {
-     vuint16_t CMPLD1:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_CMPLD1_16B_tag;
-
-
-   /* Register layout for all registers CMPLD2... */
-
-   typedef union {   /* Comparator Load Register 2 */
-      vuint16_t R;
-      struct {
-     vuint16_t CMPLD2:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_CMPLD2_16B_tag;
-
-
-   /* Register layout for all registers CCCTRL... */
-
-   typedef union {   /* Compare and Capture Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CLC2:3;            /* Compare Load Control 2 */
-         vuint16_t  CLC1:3;            /* Compare Load Control 1 */
-         vuint16_t  CMPMODE:2;         /* Compare Mode */
-         vuint16_t  CPT2MODE:2;        /* Capture 2 Mode Control */
-         vuint16_t  CPT1MODE:2;        /* Capture 1 Mode Control */
-         vuint16_t  CFWM:2;            /* Capture FIFO Water Mark */
-         vuint16_t  ONESHOT:1;         /* One Shot Capture Mode */
-         vuint16_t  ARM:1;             /* Arm Capture */
-      } B;
-   } mcTIMER_CCCTRL_16B_tag;
-
-
-   /* Register layout for all registers FILT... */
-
-   typedef union {   /* Input Filter Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-#ifndef USE_FIELD_ALIASES_mcTIMER
-         vuint16_t  FILT_CNT:3;        /* Input Filter Sample Count */
-#else
-         vuint16_t  FILTCNT:3;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcTIMER
-         vuint16_t  FILT_PER:8;        /* Input Filter Sample Period */
-#else
-         vuint16_t  FILTPER:8;           /* deprecated name - please avoid */
-#endif
-      } B;
-   } mcTIMER_FILT_16B_tag;
-
-   typedef union {   /* Watchdog Time-out Register */
-      vuint16_t R;
-      struct {
-      vuint16_t WDTOL:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_WDTOL_16B_tag;
-
-   typedef union {   /* Watchdog Time-out Register */
-      vuint16_t R;
-      struct {
-      vuint16_t WDTOH:16;  /* deprecated definition -- do not use */
-      } B;
-   } mcTIMER_WDTOH_16B_tag;
-
-   typedef union {   /* Fault Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:3;
-         vuint16_t  FTEST:1;           /* Fault Test */
-         vuint16_t  FIE:4;             /* Fault Interrupt Enable */
-         vuint16_t:4;
-         vuint16_t  FLVL:4;            /* Fault Active Logic Level */
-      } B;
-   } mcTIMER_FCTRL_16B_tag;
-
-   typedef union {   /* Fault Status Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:4;
-         vuint16_t  FFPIN:4;           /* Filtered Fault Pin */
-         vuint16_t:4;
-         vuint16_t  FFLAG:4;           /* Fault Flag */
-      } B;
-   } mcTIMER_FSTS_16B_tag;
-
-   typedef union {   /* Fault Filter Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-#ifndef USE_FIELD_ALIASES_mcTIMER
-         vuint16_t  FFPIN:3;           /* Fault Filter Sample Count */
-#else
-         vuint16_t  FFILTCNT:3;          /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcTIMER
-         vuint16_t  FFILT_PER:8;       /* Fault Filter Sample Period */
-#else
-         vuint16_t  FFILTPER:8;          /* deprecated name - please avoid */
-#endif
-      } B;
-   } mcTIMER_FFILT_16B_tag;
-
-   typedef union {   /* Channel Enable Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:8;
-         vuint16_t  ENBL:8;            /* Timer Channel Enable */
-      } B;
-   } mcTIMER_ENBL_16B_tag;
-
-   typedef union {   /* DMA Request 0 Select Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:11;
-         vuint16_t  DREQ0V:5;          /* DMA Request Select */
-      } B;
-   } mcTIMER_DREQ0_16B_tag;
-
-   typedef union {   /* DMA Request 1 Select Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:11;
-         vuint16_t  DREQ1V:5;          /* DMA Request Select */
-      } B;
-   } mcTIMER_DREQ1_16B_tag;
-
-   typedef union {   /* DMA Request 2 Select Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:11;
-         vuint16_t  DREQ2V:5;          /* DMA Request Select */
-      } B;
-   } mcTIMER_DREQ2_16B_tag;
-
-   typedef union {   /* DMA Request 3 Select Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:11;
-         vuint16_t  DREQ3V:5;          /* DMA Request Select */
-      } B;
-   } mcTIMER_DREQ3_16B_tag;
-
-
-   /* Register layout for generated register(s) DREQ... */
-
-   typedef union {   /*  */
-      vuint16_t R;
-   } mcTIMER_DREQ_16B_tag;
-
-
-   typedef struct mcTIMER_CHANNEL_struct_tag {
-
-                                                   /* Compare Register 1 */
-      mcTIMER_COMP1_16B_tag COMP1;        /* relative offset: 0x0000 */
-                                                   /* Compare Register 2 */
-      mcTIMER_COMP2_16B_tag COMP2;        /* relative offset: 0x0002 */
-                                                   /* Capture Register 1 */
-      mcTIMER_CAPT1_16B_tag CAPT1;        /* relative offset: 0x0004 */
-                                                   /* Capture Register 2 */
-      mcTIMER_CAPT2_16B_tag CAPT2;        /* relative offset: 0x0006 */
-                                                        /* Load Register */
-      mcTIMER_LOAD_16B_tag LOAD;          /* relative offset: 0x0008 */
-                                                        /* Hold Register */
-      mcTIMER_HOLD_16B_tag HOLD;          /* relative offset: 0x000A */
-                                                     /* Counter Register */
-      mcTIMER_CNTR_16B_tag CNTR;          /* relative offset: 0x000C */
-      union {
-                                                     /* Control Register */
-         mcTIMER_CTRL1_16B_tag CTRL1;     /* relative offset: 0x000E */
-         mcTIMER_CTRL1_16B_tag CTRL;      /* deprecated - please avoid */
-      };
-                                                   /* Control Register 2 */
-      mcTIMER_CTRL2_16B_tag CTRL2;        /* relative offset: 0x0010 */
-                                                   /* Control Register 3 */
-      mcTIMER_CTRL3_16B_tag CTRL3;        /* relative offset: 0x0012 */
-                                                      /* Status Register */
-      mcTIMER_STS_16B_tag STS;            /* relative offset: 0x0014 */
-                                    /* Interrupt and DMA Enable Register */
-      mcTIMER_INTDMA_16B_tag INTDMA;      /* relative offset: 0x0016 */
-                                           /* Comparator Load Register 1 */
-      mcTIMER_CMPLD1_16B_tag CMPLD1;      /* relative offset: 0x0018 */
-                                           /* Comparator Load Register 2 */
-      mcTIMER_CMPLD2_16B_tag CMPLD2;      /* relative offset: 0x001A */
-                                 /* Compare and Capture Control Register */
-      mcTIMER_CCCTRL_16B_tag CCCTRL;      /* relative offset: 0x001C */
-                                                /* Input Filter Register */
-      mcTIMER_FILT_16B_tag FILT;          /* relative offset: 0x001E */
-
-   } mcTIMER_CHANNEL_tag;
-
-
-   typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */
-      union {
-                                                /*  Register set CHANNEL */
-         mcTIMER_CHANNEL_tag CHANNEL[6];   /* offset: 0x0000  (0x0020 x 6) */
-
-         struct {
-                                                   /* Compare Register 1 */
-            mcTIMER_COMP1_16B_tag COMP10;  /* offset: 0x0000 size: 16 bit */
-                                                   /* Compare Register 2 */
-            mcTIMER_COMP2_16B_tag COMP20;  /* offset: 0x0002 size: 16 bit */
-                                                   /* Capture Register 1 */
-            mcTIMER_CAPT1_16B_tag CAPT10;  /* offset: 0x0004 size: 16 bit */
-                                                   /* Capture Register 2 */
-            mcTIMER_CAPT2_16B_tag CAPT20;  /* offset: 0x0006 size: 16 bit */
-                                                        /* Load Register */
-            mcTIMER_LOAD_16B_tag LOAD0;    /* offset: 0x0008 size: 16 bit */
-                                                        /* Hold Register */
-            mcTIMER_HOLD_16B_tag HOLD0;    /* offset: 0x000A size: 16 bit */
-                                                     /* Counter Register */
-            mcTIMER_CNTR_16B_tag CNTR0;    /* offset: 0x000C size: 16 bit */
-                                                     /* Control Register */
-            mcTIMER_CTRL1_16B_tag CTRL10;  /* offset: 0x000E size: 16 bit */
-                                                   /* Control Register 2 */
-            mcTIMER_CTRL2_16B_tag CTRL20;  /* offset: 0x0010 size: 16 bit */
-                                                   /* Control Register 3 */
-            mcTIMER_CTRL3_16B_tag CTRL30;  /* offset: 0x0012 size: 16 bit */
-                                                      /* Status Register */
-            mcTIMER_STS_16B_tag STS0;      /* offset: 0x0014 size: 16 bit */
-                                    /* Interrupt and DMA Enable Register */
-            mcTIMER_INTDMA_16B_tag INTDMA0;  /* offset: 0x0016 size: 16 bit */
-                                           /* Comparator Load Register 1 */
-            mcTIMER_CMPLD1_16B_tag CMPLD10;  /* offset: 0x0018 size: 16 bit */
-                                           /* Comparator Load Register 2 */
-            mcTIMER_CMPLD2_16B_tag CMPLD20;  /* offset: 0x001A size: 16 bit */
-                                 /* Compare and Capture Control Register */
-            mcTIMER_CCCTRL_16B_tag CCCTRL0;  /* offset: 0x001C size: 16 bit */
-                                                /* Input Filter Register */
-            mcTIMER_FILT_16B_tag FILT0;    /* offset: 0x001E size: 16 bit */
-                                                   /* Compare Register 1 */
-            mcTIMER_COMP1_16B_tag COMP11;  /* offset: 0x0020 size: 16 bit */
-                                                   /* Compare Register 2 */
-            mcTIMER_COMP2_16B_tag COMP21;  /* offset: 0x0022 size: 16 bit */
-                                                   /* Capture Register 1 */
-            mcTIMER_CAPT1_16B_tag CAPT11;  /* offset: 0x0024 size: 16 bit */
-                                                   /* Capture Register 2 */
-            mcTIMER_CAPT2_16B_tag CAPT21;  /* offset: 0x0026 size: 16 bit */
-                                                        /* Load Register */
-            mcTIMER_LOAD_16B_tag LOAD1;    /* offset: 0x0028 size: 16 bit */
-                                                        /* Hold Register */
-            mcTIMER_HOLD_16B_tag HOLD1;    /* offset: 0x002A size: 16 bit */
-                                                     /* Counter Register */
-            mcTIMER_CNTR_16B_tag CNTR1;    /* offset: 0x002C size: 16 bit */
-                                                     /* Control Register */
-            mcTIMER_CTRL1_16B_tag CTRL11;  /* offset: 0x002E size: 16 bit */
-                                                   /* Control Register 2 */
-            mcTIMER_CTRL2_16B_tag CTRL21;  /* offset: 0x0030 size: 16 bit */
-                                                   /* Control Register 3 */
-            mcTIMER_CTRL3_16B_tag CTRL31;  /* offset: 0x0032 size: 16 bit */
-                                                      /* Status Register */
-            mcTIMER_STS_16B_tag STS1;      /* offset: 0x0034 size: 16 bit */
-                                    /* Interrupt and DMA Enable Register */
-            mcTIMER_INTDMA_16B_tag INTDMA1;  /* offset: 0x0036 size: 16 bit */
-                                           /* Comparator Load Register 1 */
-            mcTIMER_CMPLD1_16B_tag CMPLD11;  /* offset: 0x0038 size: 16 bit */
-                                           /* Comparator Load Register 2 */
-            mcTIMER_CMPLD2_16B_tag CMPLD21;  /* offset: 0x003A size: 16 bit */
-                                 /* Compare and Capture Control Register */
-            mcTIMER_CCCTRL_16B_tag CCCTRL1;  /* offset: 0x003C size: 16 bit */
-                                                /* Input Filter Register */
-            mcTIMER_FILT_16B_tag FILT1;    /* offset: 0x003E size: 16 bit */
-                                                   /* Compare Register 1 */
-            mcTIMER_COMP1_16B_tag COMP12;  /* offset: 0x0040 size: 16 bit */
-                                                   /* Compare Register 2 */
-            mcTIMER_COMP2_16B_tag COMP22;  /* offset: 0x0042 size: 16 bit */
-                                                   /* Capture Register 1 */
-            mcTIMER_CAPT1_16B_tag CAPT12;  /* offset: 0x0044 size: 16 bit */
-                                                   /* Capture Register 2 */
-            mcTIMER_CAPT2_16B_tag CAPT22;  /* offset: 0x0046 size: 16 bit */
-                                                        /* Load Register */
-            mcTIMER_LOAD_16B_tag LOAD2;    /* offset: 0x0048 size: 16 bit */
-                                                        /* Hold Register */
-            mcTIMER_HOLD_16B_tag HOLD2;    /* offset: 0x004A size: 16 bit */
-                                                     /* Counter Register */
-            mcTIMER_CNTR_16B_tag CNTR2;    /* offset: 0x004C size: 16 bit */
-                                                     /* Control Register */
-            mcTIMER_CTRL1_16B_tag CTRL12;  /* offset: 0x004E size: 16 bit */
-                                                   /* Control Register 2 */
-            mcTIMER_CTRL2_16B_tag CTRL22;  /* offset: 0x0050 size: 16 bit */
-                                                   /* Control Register 3 */
-            mcTIMER_CTRL3_16B_tag CTRL32;  /* offset: 0x0052 size: 16 bit */
-                                                      /* Status Register */
-            mcTIMER_STS_16B_tag STS2;      /* offset: 0x0054 size: 16 bit */
-                                    /* Interrupt and DMA Enable Register */
-            mcTIMER_INTDMA_16B_tag INTDMA2;  /* offset: 0x0056 size: 16 bit */
-                                           /* Comparator Load Register 1 */
-            mcTIMER_CMPLD1_16B_tag CMPLD12;  /* offset: 0x0058 size: 16 bit */
-                                           /* Comparator Load Register 2 */
-            mcTIMER_CMPLD2_16B_tag CMPLD22;  /* offset: 0x005A size: 16 bit */
-                                 /* Compare and Capture Control Register */
-            mcTIMER_CCCTRL_16B_tag CCCTRL2;  /* offset: 0x005C size: 16 bit */
-                                                /* Input Filter Register */
-            mcTIMER_FILT_16B_tag FILT2;    /* offset: 0x005E size: 16 bit */
-                                                   /* Compare Register 1 */
-            mcTIMER_COMP1_16B_tag COMP13;  /* offset: 0x0060 size: 16 bit */
-                                                   /* Compare Register 2 */
-            mcTIMER_COMP2_16B_tag COMP23;  /* offset: 0x0062 size: 16 bit */
-                                                   /* Capture Register 1 */
-            mcTIMER_CAPT1_16B_tag CAPT13;  /* offset: 0x0064 size: 16 bit */
-                                                   /* Capture Register 2 */
-            mcTIMER_CAPT2_16B_tag CAPT23;  /* offset: 0x0066 size: 16 bit */
-                                                        /* Load Register */
-            mcTIMER_LOAD_16B_tag LOAD3;    /* offset: 0x0068 size: 16 bit */
-                                                        /* Hold Register */
-            mcTIMER_HOLD_16B_tag HOLD3;    /* offset: 0x006A size: 16 bit */
-                                                     /* Counter Register */
-            mcTIMER_CNTR_16B_tag CNTR3;    /* offset: 0x006C size: 16 bit */
-                                                     /* Control Register */
-            mcTIMER_CTRL1_16B_tag CTRL13;  /* offset: 0x006E size: 16 bit */
-                                                   /* Control Register 2 */
-            mcTIMER_CTRL2_16B_tag CTRL23;  /* offset: 0x0070 size: 16 bit */
-                                                   /* Control Register 3 */
-            mcTIMER_CTRL3_16B_tag CTRL33;  /* offset: 0x0072 size: 16 bit */
-                                                      /* Status Register */
-            mcTIMER_STS_16B_tag STS3;      /* offset: 0x0074 size: 16 bit */
-                                    /* Interrupt and DMA Enable Register */
-            mcTIMER_INTDMA_16B_tag INTDMA3;  /* offset: 0x0076 size: 16 bit */
-                                           /* Comparator Load Register 1 */
-            mcTIMER_CMPLD1_16B_tag CMPLD13;  /* offset: 0x0078 size: 16 bit */
-                                           /* Comparator Load Register 2 */
-            mcTIMER_CMPLD2_16B_tag CMPLD23;  /* offset: 0x007A size: 16 bit */
-                                 /* Compare and Capture Control Register */
-            mcTIMER_CCCTRL_16B_tag CCCTRL3;  /* offset: 0x007C size: 16 bit */
-                                                /* Input Filter Register */
-            mcTIMER_FILT_16B_tag FILT3;    /* offset: 0x007E size: 16 bit */
-                                                   /* Compare Register 1 */
-            mcTIMER_COMP1_16B_tag COMP14;  /* offset: 0x0080 size: 16 bit */
-                                                   /* Compare Register 2 */
-            mcTIMER_COMP2_16B_tag COMP24;  /* offset: 0x0082 size: 16 bit */
-                                                   /* Capture Register 1 */
-            mcTIMER_CAPT1_16B_tag CAPT14;  /* offset: 0x0084 size: 16 bit */
-                                                   /* Capture Register 2 */
-            mcTIMER_CAPT2_16B_tag CAPT24;  /* offset: 0x0086 size: 16 bit */
-                                                        /* Load Register */
-            mcTIMER_LOAD_16B_tag LOAD4;    /* offset: 0x0088 size: 16 bit */
-                                                        /* Hold Register */
-            mcTIMER_HOLD_16B_tag HOLD4;    /* offset: 0x008A size: 16 bit */
-                                                     /* Counter Register */
-            mcTIMER_CNTR_16B_tag CNTR4;    /* offset: 0x008C size: 16 bit */
-                                                     /* Control Register */
-            mcTIMER_CTRL1_16B_tag CTRL14;  /* offset: 0x008E size: 16 bit */
-                                                   /* Control Register 2 */
-            mcTIMER_CTRL2_16B_tag CTRL24;  /* offset: 0x0090 size: 16 bit */
-                                                   /* Control Register 3 */
-            mcTIMER_CTRL3_16B_tag CTRL34;  /* offset: 0x0092 size: 16 bit */
-                                                      /* Status Register */
-            mcTIMER_STS_16B_tag STS4;      /* offset: 0x0094 size: 16 bit */
-                                    /* Interrupt and DMA Enable Register */
-            mcTIMER_INTDMA_16B_tag INTDMA4;  /* offset: 0x0096 size: 16 bit */
-                                           /* Comparator Load Register 1 */
-            mcTIMER_CMPLD1_16B_tag CMPLD14;  /* offset: 0x0098 size: 16 bit */
-                                           /* Comparator Load Register 2 */
-            mcTIMER_CMPLD2_16B_tag CMPLD24;  /* offset: 0x009A size: 16 bit */
-                                 /* Compare and Capture Control Register */
-            mcTIMER_CCCTRL_16B_tag CCCTRL4;  /* offset: 0x009C size: 16 bit */
-                                                /* Input Filter Register */
-            mcTIMER_FILT_16B_tag FILT4;    /* offset: 0x009E size: 16 bit */
-                                                   /* Compare Register 1 */
-            mcTIMER_COMP1_16B_tag COMP15;  /* offset: 0x00A0 size: 16 bit */
-                                                   /* Compare Register 2 */
-            mcTIMER_COMP2_16B_tag COMP25;  /* offset: 0x00A2 size: 16 bit */
-                                                   /* Capture Register 1 */
-            mcTIMER_CAPT1_16B_tag CAPT15;  /* offset: 0x00A4 size: 16 bit */
-                                                   /* Capture Register 2 */
-            mcTIMER_CAPT2_16B_tag CAPT25;  /* offset: 0x00A6 size: 16 bit */
-                                                        /* Load Register */
-            mcTIMER_LOAD_16B_tag LOAD5;    /* offset: 0x00A8 size: 16 bit */
-                                                        /* Hold Register */
-            mcTIMER_HOLD_16B_tag HOLD5;    /* offset: 0x00AA size: 16 bit */
-                                                     /* Counter Register */
-            mcTIMER_CNTR_16B_tag CNTR5;    /* offset: 0x00AC size: 16 bit */
-                                                     /* Control Register */
-            mcTIMER_CTRL1_16B_tag CTRL15;  /* offset: 0x00AE size: 16 bit */
-                                                   /* Control Register 2 */
-            mcTIMER_CTRL2_16B_tag CTRL25;  /* offset: 0x00B0 size: 16 bit */
-                                                   /* Control Register 3 */
-            mcTIMER_CTRL3_16B_tag CTRL35;  /* offset: 0x00B2 size: 16 bit */
-                                                      /* Status Register */
-            mcTIMER_STS_16B_tag STS5;      /* offset: 0x00B4 size: 16 bit */
-                                    /* Interrupt and DMA Enable Register */
-            mcTIMER_INTDMA_16B_tag INTDMA5;  /* offset: 0x00B6 size: 16 bit */
-                                           /* Comparator Load Register 1 */
-            mcTIMER_CMPLD1_16B_tag CMPLD15;  /* offset: 0x00B8 size: 16 bit */
-                                           /* Comparator Load Register 2 */
-            mcTIMER_CMPLD2_16B_tag CMPLD25;  /* offset: 0x00BA size: 16 bit */
-                                 /* Compare and Capture Control Register */
-            mcTIMER_CCCTRL_16B_tag CCCTRL5;  /* offset: 0x00BC size: 16 bit */
-                                                /* Input Filter Register */
-            mcTIMER_FILT_16B_tag FILT5;    /* offset: 0x00BE size: 16 bit */
-         };
-
-      };
-      int8_t mcTIMER_reserved_00C0[64];
-                                           /* Watchdog Time-out Register */
-      mcTIMER_WDTOL_16B_tag WDTOL;         /* offset: 0x0100 size: 16 bit */
-                                           /* Watchdog Time-out Register */
-      mcTIMER_WDTOH_16B_tag WDTOH;         /* offset: 0x0102 size: 16 bit */
-                                               /* Fault Control Register */
-      mcTIMER_FCTRL_16B_tag FCTRL;         /* offset: 0x0104 size: 16 bit */
-                                                /* Fault Status Register */
-      mcTIMER_FSTS_16B_tag FSTS;           /* offset: 0x0106 size: 16 bit */
-                                               /* Fault Filter Registers */
-      mcTIMER_FFILT_16B_tag FFILT;         /* offset: 0x0108 size: 16 bit */
-      int8_t mcTIMER_reserved_010A[2];
-                                             /* Channel Enable Registers */
-      mcTIMER_ENBL_16B_tag ENBL;           /* offset: 0x010C size: 16 bit */
-      int8_t mcTIMER_reserved_010E_C[2];
-      union {
-         mcTIMER_DREQ_16B_tag DREQ[4];     /* offset: 0x0110  (0x0002 x 4) */
-
-         struct {
-                                       /* DMA Request 0 Select Registers */
-            mcTIMER_DREQ0_16B_tag DREQ0;   /* offset: 0x0110 size: 16 bit */
-                                       /* DMA Request 1 Select Registers */
-            mcTIMER_DREQ1_16B_tag DREQ1;   /* offset: 0x0112 size: 16 bit */
-                                       /* DMA Request 2 Select Registers */
-            mcTIMER_DREQ2_16B_tag DREQ2;   /* offset: 0x0114 size: 16 bit */
-                                       /* DMA Request 3 Select Registers */
-            mcTIMER_DREQ3_16B_tag DREQ3;   /* offset: 0x0116 size: 16 bit */
-         };
-
-      };
-   } mcTIMER_tag;
-
-
-#define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL)
-#define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL)
-#define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: mcPWM  */
-/*                                                              */
-/****************************************************************/
-
-
-   /* Register layout for all registers CNT... */
-
-   typedef union {   /* Counter Register */
-      vuint16_t R;
-   } mcPWM_CNT_16B_tag;
-
-
-   /* Register layout for all registers INIT... */
-
-   typedef union {   /* Initial Counter Register */
-      vuint16_t R;
-   } mcPWM_INIT_16B_tag;
-
-
-   /* Register layout for all registers CTRL2... */
-
-   typedef union {   /* Control 2 Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  DBGEN:1;           /* Debug Enable */
-         vuint16_t  WAITEN:1;          /* Wait Enable */
-         vuint16_t  INDEP:1;           /* Independent or Complementary Pair Operation */
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  PWM23_INIT:1;      /* PWM23 Initial Value */
-#else
-         vuint16_t  PWMA_INIT:1;         /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  PWM45_INIT:1;      /* PWM23 Initial Value */
-#else
-         vuint16_t  PWMB_INIT:1;         /* deprecated name - please avoid */
-#endif
-         vuint16_t  PWMX_INIT:1;       /* PWMX Initial Value */
-         vuint16_t  INIT_SEL:2;        /* Initialization Control Select */
-         vuint16_t  FRCEN:1;           /* Force Initialization enable */
-         vuint16_t  FORCE:1;           /* Force Initialization */
-         vuint16_t  FORCE_SEL:3;       /* Force Source Select */
-         vuint16_t  RELOAD_SEL:1;      /* Reload Source Select */
-         vuint16_t  CLK_SEL:2;         /* Clock Source Select */
-      } B;
-   } mcPWM_CTRL2_16B_tag;
-
-
-   /* Register layout for all registers CTRL1... */
-
-   typedef union {   /* Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  LDFQ:4;            /* Load Frequency */
-         vuint16_t  HALF:1;            /* Half Cycle Reload */
-         vuint16_t  FULL:1;            /* Full Cycle Reload */
-         vuint16_t  DT:2;              /* Deadtime */
-         vuint16_t:1;
-         vuint16_t  PRSC:3;            /* Prescaler */
-         vuint16_t:1;
-         vuint16_t  LDMOD:1;           /* Load Mode Select */
-         vuint16_t:1;
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  DBL_EN:1;          /* Double Switching Enable */
-#else
-         vuint16_t  DBLEN:1;             /* deprecated name - please avoid */
-#endif
-      } B;
-   } mcPWM_CTRL1_16B_tag;
-
-
-   /* Register layout for all registers VAL_0... */
-
-   typedef union {   /* Value Register 0 */
-      vuint16_t R;
-   } mcPWM_VAL_0_16B_tag;
-
-
-   /* Register layout for all registers VAL_1... */
-
-   typedef union {   /* Value Register 1 */
-      vuint16_t R;
-   } mcPWM_VAL_1_16B_tag;
-
-
-   /* Register layout for all registers VAL_2... */
-
-   typedef union {   /* Value Register 2 */
-      vuint16_t R;
-   } mcPWM_VAL_2_16B_tag;
-
-
-   /* Register layout for all registers VAL_3... */
-
-   typedef union {   /* Value Register 3 */
-      vuint16_t R;
-   } mcPWM_VAL_3_16B_tag;
-
-
-   /* Register layout for all registers VAL_4... */
-
-   typedef union {   /* Value Register 4 */
-      vuint16_t R;
-   } mcPWM_VAL_4_16B_tag;
-
-
-   /* Register layout for all registers VAL_5... */
-
-   typedef union {   /* Value Register 5 */
-      vuint16_t R;
-   } mcPWM_VAL_5_16B_tag;
-
-
-   /* Register layout for all registers FRACA... */
-
-   typedef union {   /* Fractional Delay Register A */
-      vuint16_t R;
-      struct {
-         vuint16_t  FRACA_EN:1;        /* Fractional Delay Enable */
-         vuint16_t:10;
-         vuint16_t  FRACA_DLY:5;       /* Fractional Delay Value */
-      } B;
-   } mcPWM_FRACA_16B_tag;
-
-
-   /* Register layout for all registers FRACB... */
-
-   typedef union {   /* Fractional Delay Register B */
-      vuint16_t R;
-      struct {
-         vuint16_t  FRACA_EN:1;        /* Fractional Delay Enable */
-         vuint16_t:10;
-         vuint16_t  FRACA_DLY:5;       /* Fractional Delay Value */
-      } B;
-   } mcPWM_FRACB_16B_tag;
-
-
-   /* Register layout for all registers OCTRL... */
-
-   typedef union {   /* Output Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  PWMA_IN:1;         /* PWMA Input */
-         vuint16_t  PWMB_IN:1;         /* PWMB Input */
-         vuint16_t  PWMX_IN:1;         /* PWMX Input */
-         vuint16_t:2;
-         vuint16_t  POLA:1;            /* PWMA Output Polarity */
-         vuint16_t  POLB:1;            /* PWMB Output Polarity */
-         vuint16_t  POLX:1;            /* PWMX Output Polarity */
-         vuint16_t:2;
-         vuint16_t  PWMAFS:2;          /* PWMA Fault State */
-         vuint16_t  PWMBFS:2;          /* PWMB Fault State */
-         vuint16_t  PWMXFS:2;          /* PWMX Fault State */
-      } B;
-   } mcPWM_OCTRL_16B_tag;
-
-
-   /* Register layout for all registers STS... */
-
-   typedef union {   /* Status Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:1;
-         vuint16_t  RUF:1;             /* Registers Updated Flag */
-         vuint16_t  REF:1;             /* Reload Error Flag */
-         vuint16_t  RF:1;              /* Reload Flag */
-         vuint16_t  CFA1:1;            /* Capture Flag A1 */
-         vuint16_t  CFA0:1;            /* Capture Flag A0 */
-         vuint16_t  CFB1:1;            /* Capture Flag B1 */
-         vuint16_t  CFB0:1;            /* Capture Flag B0 */
-         vuint16_t  CFX1:1;            /* Capture Flag X1 */
-         vuint16_t  CFX0:1;            /* Capture Flag X0 */
-         vuint16_t  CMPF:6;            /* Compare Flags */
-      } B;
-   } mcPWM_STS_16B_tag;
-
-
-   /* Register layout for all registers INTEN... */
-
-   typedef union {   /* Interrupt Enable Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  REIE:1;            /* Reload Error Interrupt Enable */
-         vuint16_t  RIE:1;             /* Reload Interrupt Enable */
-         vuint16_t  CA1IE:1;           /* Capture A1 Interrupt Enable */
-         vuint16_t  CA0IE:1;           /* Capture A0 Interrupt Enable */
-         vuint16_t  CB1IE:1;           /* Capture B1 Interrupt Enable */
-         vuint16_t  CB0IE:1;           /* Capture B0 Interrupt Enable */
-         vuint16_t  CX1IE:1;           /* Capture X1 Interrupt Enable */
-         vuint16_t  CX0IE:1;           /* Capture X0 Interrupt Enable */
-         vuint16_t  CMPIE:6;           /* Compare Interrupt Enables */
-      } B;
-   } mcPWM_INTEN_16B_tag;
-
-
-   /* Register layout for all registers DMAEN... */
-
-   typedef union {   /* DMA Enable Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:6;
-         vuint16_t  VALDE:1;           /* Value Register DMA Enable */
-         vuint16_t  FAND:1;            /* FIFO Watermark AND Control */
-         vuint16_t  CAPTDE:2;          /* Capture DMA Enable Source Select */
-         vuint16_t  CA1DE:1;           /* Capture A1 FIFO DMA Enable */
-         vuint16_t  CA0DE:1;           /* Capture A0 FIFO DMA Enable */
-         vuint16_t  CB1DE:1;           /* Capture B1 FIFO DMA Enable */
-         vuint16_t  CB0DE:1;           /* Capture B0 FIFO DMA Enable */
-         vuint16_t  CX1DE:1;           /* Capture X1 FIFO DMA Enable */
-         vuint16_t  CX0DE:1;           /* Capture X0 FIFO DMA Enable */
-      } B;
-   } mcPWM_DMAEN_16B_tag;
-
-
-   /* Register layout for all registers TCTRL... */
-
-   typedef union {   /* Output Trigger Control  Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:10;
-         vuint16_t  OUT_TRIG_EN:6;     /* Output Trigger Enables */
-      } B;
-   } mcPWM_TCTRL_16B_tag;
-
-
-   /* Register layout for all registers DISMAP... */
-
-   typedef union {   /* Fault Disable Mapping   Registers */
-      vuint16_t R;
-      struct {
-         vuint16_t:4;
-         vuint16_t  DISX:4;            /* PWMX Fault Disable Mask */
-         vuint16_t  DISB:4;            /* PWMB Fault Disable Mask */
-         vuint16_t  DISA:4;            /* PWMA Fault Disable Mask */
-      } B;
-   } mcPWM_DISMAP_16B_tag;
-
-
-   /* Register layout for all registers DTCNT0... */
-
-   typedef union {   /* Deadtime Count Register 0 */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  DTCNT0:11;         /* Deadtime Count Register 0 */
-      } B;
-   } mcPWM_DTCNT0_16B_tag;
-
-
-   /* Register layout for all registers DTCNT1... */
-
-   typedef union {   /* Deadtime Count Register 1 */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  DTCNT1:11;         /* Deadtime Count Register 1 */
-      } B;
-   } mcPWM_DTCNT1_16B_tag;
-
-
-   /* Register layout for all registers CAPTCTRLA... */
-
-   typedef union {   /* Capture Control A Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CA1CNT:3;          /* Capture A1 FIFO Word Count */
-         vuint16_t  CA0CNT:3;          /* Capture A0 FIFO Word Count */
-         vuint16_t  CFAWM:2;           /* Capture A FIFOs Water Mark */
-         vuint16_t  EDGCNTAEN:1;       /* Edge Counter A Enable */
-         vuint16_t  INPSELA:1;         /* Input Select A */
-         vuint16_t  EDGA1:2;           /* Edge A 1 */
-         vuint16_t  EDGA0:2;           /* Edge A 0 */
-         vuint16_t  ONESHOTA:1;        /* One Shot Mode A */
-         vuint16_t  ARMA:1;            /* Arm A */
-      } B;
-   } mcPWM_CAPTCTRLA_16B_tag;
-
-
-   /* Register layout for all registers CAPTCMPA... */
-
-   typedef union {   /* Capture Compare A Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  EDGCNTA:8;         /* Edge Counter A */
-         vuint16_t  EDGCMPA:8;         /* Edge Compare A */
-      } B;
-   } mcPWM_CAPTCMPA_16B_tag;
-
-
-   /* Register layout for all registers CAPTCTRLB... */
-
-   typedef union {   /* Capture Control B Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CB1CNT:3;          /* Capture B1 FIFO Word Count */
-         vuint16_t  CB0CNT:3;          /* Capture B0 FIFO Word Count */
-         vuint16_t  CFBWM:2;           /* Capture B FIFOs Water Mark */
-         vuint16_t  EDGCNTBEN:1;       /* Edge Counter B Enable */
-         vuint16_t  INPSELB:1;         /* Input Select B */
-         vuint16_t  EDGB1:2;           /* Edge B 1 */
-         vuint16_t  EDGB0:2;           /* Edge B 0 */
-         vuint16_t  ONESHOTB:1;        /* One Shot Mode B */
-         vuint16_t  ARMB:1;            /* Arm B */
-      } B;
-   } mcPWM_CAPTCTRLB_16B_tag;
-
-
-   /* Register layout for all registers CAPTCMPB... */
-
-   typedef union {   /* Capture Compare B Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  EDGCNTB:8;         /* Edge Counter B */
-         vuint16_t  EDGCMPB:8;         /* Edge Compare B */
-      } B;
-   } mcPWM_CAPTCMPB_16B_tag;
-
-
-   /* Register layout for all registers CAPTCTRLX... */
-
-   typedef union {   /* Capture Control X Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CX1CNT:3;          /* Capture X1 FIFO Word Count */
-         vuint16_t  CX0CNT:3;          /* Capture X0 FIFO Word Count */
-         vuint16_t  CFXWM:2;           /* Capture X FIFOs Water Mark */
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  EDGCNTXEN:1;       /* Edge Counter X Enable */
-#else
-         vuint16_t  EDGCNTX_EN:1;        /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  INPSELX:1;         /* Input Select X */
-#else
-         vuint16_t  INP_SELX:1;          /* deprecated name - please avoid */
-#endif
-         vuint16_t  EDGX1:2;           /* Edge X 1 */
-         vuint16_t  EDGX0:2;           /* Edge X 0 */
-         vuint16_t  ONESHOTX:1;        /* One Shot Mode X */
-         vuint16_t  ARMX:1;            /* Arm X */
-      } B;
-   } mcPWM_CAPTCTRLX_16B_tag;
-
-
-   /* Register layout for all registers CAPTCMPX... */
-
-   typedef union {   /* Capture Compare X Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  EDGCNTX:8;         /* Edge Counter X */
-         vuint16_t  EDGCMPX:8;         /* Edge Compare X */
-      } B;
-   } mcPWM_CAPTCMPX_16B_tag;
-
-
-   /* Register layout for all registers CVAL0... */
-
-   typedef union {   /* Capture Value 0 Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CAPTVAL0:16;       /* Captured value from submodule counter */
-      } B;
-   } mcPWM_CVAL0_16B_tag;
-
-
-   /* Register layout for all registers CVAL0CYC... */
-
-   typedef union {   /* Capture Value 0 Cycle Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:12;
-         vuint16_t  CVAL0CYC:4;        /* Capture Value 0 Cycle */
-      } B;
-   } mcPWM_CVAL0CYC_16B_tag;
-
-
-   /* Register layout for all registers CVAL1... */
-
-   typedef union {   /* Capture Value 1 Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CAPTVAL1:16;       /* Captured value from submodule counter */
-      } B;
-   } mcPWM_CVAL1_16B_tag;
-
-
-   /* Register layout for all registers CVAL1CYC... */
-
-   typedef union {   /* Capture Value 1 Cycle Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:12;
-         vuint16_t  CVAL1CYC:4;        /* Capture Value 1 Cycle */
-      } B;
-   } mcPWM_CVAL1CYC_16B_tag;
-
-
-   /* Register layout for all registers CVAL2... */
-
-   typedef union {   /* Capture Value 2 Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CAPTVAL2:16;       /* Captured value from submodule counter */
-      } B;
-   } mcPWM_CVAL2_16B_tag;
-
-
-   /* Register layout for all registers CVAL2CYC... */
-
-   typedef union {   /* Capture Value 2 Cycle Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:12;
-         vuint16_t  CVAL2CYC:4;        /* Capture Value 2 Cycle */
-      } B;
-   } mcPWM_CVAL2CYC_16B_tag;
-
-
-   /* Register layout for all registers CVAL3... */
-
-   typedef union {   /* Capture Value 3 Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CAPTVAL3:16;       /* Captured value from submodule counter */
-      } B;
-   } mcPWM_CVAL3_16B_tag;
-
-
-   /* Register layout for all registers CVAL3CYC... */
-
-   typedef union {   /* Capture Value 3 Cycle Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:12;
-         vuint16_t  CVAL3CYC:4;        /* Capture Value 3 Cycle */
-      } B;
-   } mcPWM_CVAL3CYC_16B_tag;
-
-
-   /* Register layout for all registers CVAL4... */
-
-   typedef union {   /* Capture Value 4 Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CAPTVAL4:16;       /* Captured value from submodule counter */
-      } B;
-   } mcPWM_CVAL4_16B_tag;
-
-
-   /* Register layout for all registers CVAL4CYC... */
-
-   typedef union {   /* Capture Value 4 Cycle Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:12;
-         vuint16_t  CVAL4CYC:4;        /* Capture Value 4 Cycle */
-      } B;
-   } mcPWM_CVAL4CYC_16B_tag;
-
-
-   /* Register layout for all registers CVAL5... */
-
-   typedef union {   /* Capture Value 5 Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  CAPTVAL5:16;       /* Captured value from submodule counter */
-      } B;
-   } mcPWM_CVAL5_16B_tag;
-
-
-   /* Register layout for all registers CVAL5CYC... */
-
-   typedef union {   /* Capture Value 5 Cycle Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:12;
-         vuint16_t  CVAL5CYC:4;        /* Capture Value 5 Cycle */
-      } B;
-   } mcPWM_CVAL5CYC_16B_tag;
-
-   typedef union {   /* Output Enable Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:4;
-         vuint16_t  PWMA_EN:4;         /* PWMA Output Enables */
-         vuint16_t  PWMB_EN:4;         /* PWMB Output Enables */
-         vuint16_t  PWMX_EN:4;         /* PWMX Output Enables */
-      } B;
-   } mcPWM_OUTEN_16B_tag;
-
-   typedef union {   /* Mask Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:4;
-         vuint16_t  MASKA:4;           /* PWMA Masks */
-         vuint16_t  MASKB:4;           /* PWMB Masks */
-         vuint16_t  MASKX:4;           /* PWMX Masks */
-      } B;
-   } mcPWM_MASK_16B_tag;
-
-   typedef union {   /* Software Controlled Output Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:8;
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  OUT23_3:1;         /* Software Controlled Output 23_3 */
-#else
-         vuint16_t  OUTA_3:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  OUT45_3:1;         /* Software Controlled Output 45_3 */
-#else
-         vuint16_t  OUTB_3:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  OUT23_2:1;         /* Software Controlled Output 23_2 */
-#else
-         vuint16_t  OUTA_2:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  OUT45_2:1;         /* Software Controlled Output 45_2 */
-#else
-         vuint16_t  OUTB_2:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  OUT23_1:1;         /* Software Controlled Output 23_1 */
-#else
-         vuint16_t  OUTA_1:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  OUT45_1:1;         /* Software Controlled Output 45_1 */
-#else
-         vuint16_t  OUTB_1:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  OUT23_0:1;         /* Software Controlled Output 23_0 */
-#else
-         vuint16_t  OUTA_0:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  OUT45_0:1;         /* Software Controlled Output 45_0 */
-#else
-         vuint16_t  OUTB_0:1;            /* deprecated name - please avoid */
-#endif
-      } B;
-   } mcPWM_SWCOUT_16B_tag;
-
-   typedef union {   /* Deadtime Source Select Register */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  SEL23_3:2;         /* PWM23_3 Control Select */
-#else
-         vuint16_t  SELA_3:2;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  SEL45_3:2;         /* PWM45_3 Control Select */
-#else
-         vuint16_t  SELB_3:2;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  SEL23_2:2;         /* PWM23_2 Control Select */
-#else
-         vuint16_t  SELA_2:2;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  SEL45_2:2;         /* PWM45_2 Control Select */
-#else
-         vuint16_t  SELB_2:2;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  SEL23_1:2;         /* PWM23_1 Control Select */
-#else
-         vuint16_t  SELA_1:2;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  SEL45_1:2;         /* PWM45_1 Control Select */
-#else
-         vuint16_t  SELB_1:2;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  SEL23_0:2;         /* PWM23_0 Control Select */
-#else
-         vuint16_t  SELA_0:2;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  SEL45_0:2;         /* PWM45_0 Control Select */
-#else
-         vuint16_t  SELB_0:2;            /* deprecated name - please avoid */
-#endif
-      } B;
-   } mcPWM_DTSRCSEL_16B_tag;
-
-   typedef union {   /* Master Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  IPOL:4;            /* Current Polarity */
-         vuint16_t  RUN:4;             /* Run */
-#ifndef USE_FIELD_ALIASES_mcPWM
-         vuint16_t  CLOK:4;            /* Clear Load Okay */
-#else
-         vuint16_t  CLDOK:4;             /* deprecated name - please avoid */
-#endif
-         vuint16_t  LDOK:4;            /* Load Okay */
-      } B;
-   } mcPWM_MCTRL_16B_tag;
-
-   typedef union {   /* Fault Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  FLVL:4;            /* Fault Level */
-         vuint16_t  FAUTO:4;           /* Automatic Fault Clearing */
-         vuint16_t  FSAFE:4;           /* Fault Safety Mode */
-         vuint16_t  FIE:4;             /* Fault Interrupt Enables */
-      } B;
-   } mcPWM_FCTRL_16B_tag;
-
-   typedef union {   /* Fault Status Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:3;
-         vuint16_t  FTEST:1;           /* Fault Test */
-         vuint16_t  FFPIN:4;           /* Filtered Fault Pins */
-         vuint16_t:4;
-         vuint16_t  FFLAG:4;           /* Fault Flags */
-      } B;
-   } mcPWM_FSTS_16B_tag;
-
-   typedef union {   /* Fault Filter Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  FILT_CNT:3;        /* Fault Filter Count */
-         vuint16_t  FILT_PER:8;        /* Fault Filter Period */
-      } B;
-   } mcPWM_FFILT_16B_tag;
-
-
-   /* Register layout for generated register(s) VAL... */
-
-   typedef union {   /*  */
-      vuint16_t R;
-   } mcPWM_VAL_16B_tag;
-
-
-   typedef struct mcPWM_SUBMOD_struct_tag {
-
-                                                     /* Counter Register */
-      mcPWM_CNT_16B_tag CNT;              /* relative offset: 0x0000 */
-                                             /* Initial Counter Register */
-      mcPWM_INIT_16B_tag INIT;            /* relative offset: 0x0002 */
-                                                   /* Control 2 Register */
-      mcPWM_CTRL2_16B_tag CTRL2;          /* relative offset: 0x0004 */
-      union {
-                                                     /* Control Register */
-         mcPWM_CTRL1_16B_tag CTRL1;       /* relative offset: 0x0006 */
-         mcPWM_CTRL1_16B_tag CTRL;        /* deprecated - please avoid */
-      };
-                                                     /* Value Register 0 */
-      
-      union {
- 
-	     struct {
-			   
-            mcPWM_VAL_0_16B_tag VAL_0;          /* relative offset: 0x0008 */
-                                                     /* Value Register 1 */
-            mcPWM_VAL_1_16B_tag VAL_1;          /* relative offset: 0x000A */
-                                                     /* Value Register 2 */
-            mcPWM_VAL_2_16B_tag VAL_2;          /* relative offset: 0x000C */
-                                                     /* Value Register 3 */
-            mcPWM_VAL_3_16B_tag VAL_3;          /* relative offset: 0x000E */
-                                                     /* Value Register 4 */
-            mcPWM_VAL_4_16B_tag VAL_4;          /* relative offset: 0x0010 */
-                                                     /* Value Register 5 */
-            mcPWM_VAL_5_16B_tag VAL_5;          /* relative offset: 0x0012 */	    
-				
-		 };
-		 
-		 mcPWM_VAL_0_16B_tag VAL[6];    /* offset: 0x0008 size: 16 bit */
-
-	  };
-										  /* Fractional Delay Register A */
-      mcPWM_FRACA_16B_tag FRACA;          /* relative offset: 0x0014 */
-                                          /* Fractional Delay Register B */
-      mcPWM_FRACB_16B_tag FRACB;          /* relative offset: 0x0016 */
-                                              /* Output Control Register */
-      mcPWM_OCTRL_16B_tag OCTRL;          /* relative offset: 0x0018 */
-                                                      /* Status Register */
-      mcPWM_STS_16B_tag STS;              /* relative offset: 0x001A */
-                                           /* Interrupt Enable Registers */
-      mcPWM_INTEN_16B_tag INTEN;          /* relative offset: 0x001C */
-                                                 /* DMA Enable Registers */
-      mcPWM_DMAEN_16B_tag DMAEN;          /* relative offset: 0x001E */
-                                    /* Output Trigger Control  Registers */
-      mcPWM_TCTRL_16B_tag TCTRL;          /* relative offset: 0x0020 */
-                                    /* Fault Disable Mapping   Registers */
-      mcPWM_DISMAP_16B_tag DISMAP;        /* relative offset: 0x0022 */
-                                            /* Deadtime Count Register 0 */
-      mcPWM_DTCNT0_16B_tag DTCNT0;        /* relative offset: 0x0024 */
-                                            /* Deadtime Count Register 1 */
-      mcPWM_DTCNT1_16B_tag DTCNT1;        /* relative offset: 0x0026 */
-                                           /* Capture Control A Register */
-      mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA;  /* relative offset: 0x0028 */
-      union {
-                                           /* Capture Compare A Register */
-         mcPWM_CAPTCMPA_16B_tag CAPTCMPA;  /* relative offset: 0x002A */
-         mcPWM_CAPTCMPA_16B_tag CAPTCOMPA;  /* deprecated - please avoid */
-      };
-                                           /* Capture Control B Register */
-      mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB;  /* relative offset: 0x002C */
-      union {
-                                           /* Capture Compare B Register */
-         mcPWM_CAPTCMPB_16B_tag CAPTCMPB;  /* relative offset: 0x002E */
-         mcPWM_CAPTCMPB_16B_tag CAPTCOMPB;  /* deprecated - please avoid */
-      };
-                                           /* Capture Control X Register */
-      mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX;  /* relative offset: 0x0030 */
-      union {
-                                           /* Capture Compare X Register */
-         mcPWM_CAPTCMPX_16B_tag CAPTCMPX;  /* relative offset: 0x0032 */
-         mcPWM_CAPTCMPX_16B_tag CAPTCOMPX;  /* deprecated - please avoid */
-      };
-                                             /* Capture Value 0 Register */
-      mcPWM_CVAL0_16B_tag CVAL0;          /* relative offset: 0x0034 */
-      union {
-                                       /* Capture Value 0 Cycle Register */
-         mcPWM_CVAL0CYC_16B_tag CVAL0CYC;  /* relative offset: 0x0036 */
-         mcPWM_CVAL0CYC_16B_tag CVAL0C;   /* deprecated - please avoid */
-      };
-                                             /* Capture Value 1 Register */
-      mcPWM_CVAL1_16B_tag CVAL1;          /* relative offset: 0x0038 */
-      union {
-                                       /* Capture Value 1 Cycle Register */
-         mcPWM_CVAL1CYC_16B_tag CVAL1CYC;  /* relative offset: 0x003A */
-         mcPWM_CVAL1CYC_16B_tag CVAL1C;   /* deprecated - please avoid */
-      };
-                                             /* Capture Value 2 Register */
-      mcPWM_CVAL2_16B_tag CVAL2;          /* relative offset: 0x003C */
-      union {
-                                       /* Capture Value 2 Cycle Register */
-         mcPWM_CVAL2CYC_16B_tag CVAL2CYC;  /* relative offset: 0x003E */
-         mcPWM_CVAL2CYC_16B_tag CVAL2C;   /* deprecated - please avoid */
-      };
-                                             /* Capture Value 3 Register */
-      mcPWM_CVAL3_16B_tag CVAL3;          /* relative offset: 0x0040 */
-      union {
-                                       /* Capture Value 3 Cycle Register */
-         mcPWM_CVAL3CYC_16B_tag CVAL3CYC;  /* relative offset: 0x0042 */
-         mcPWM_CVAL3CYC_16B_tag CVAL3C;   /* deprecated - please avoid */
-      };
-                                             /* Capture Value 4 Register */
-      mcPWM_CVAL4_16B_tag CVAL4;          /* relative offset: 0x0044 */
-      union {
-                                       /* Capture Value 4 Cycle Register */
-         mcPWM_CVAL4CYC_16B_tag CVAL4CYC;  /* relative offset: 0x0046 */
-         mcPWM_CVAL4CYC_16B_tag CVAL4C;   /* deprecated - please avoid */
-      };
-                                             /* Capture Value 5 Register */
-      mcPWM_CVAL5_16B_tag CVAL5;          /* relative offset: 0x0048 */
-      union {
-                                       /* Capture Value 5 Cycle Register */
-         mcPWM_CVAL5CYC_16B_tag CVAL5CYC;  /* relative offset: 0x004A */
-         mcPWM_CVAL5CYC_16B_tag CVAL5C;   /* deprecated - please avoid */
-      };
-      int8_t mcPWM_SUBMOD_reserved_004C[4];
-
-   } mcPWM_SUBMOD_tag;
-
-
-   typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */
-      union {
-                                                 /*  Register set SUBMOD */
-         mcPWM_SUBMOD_tag SUBMOD[4];       /* offset: 0x0000  (0x0050 x 4) */
-
-         struct {
-                                                     /* Counter Register */
-            mcPWM_CNT_16B_tag CNT0;        /* offset: 0x0000 size: 16 bit */
-                                             /* Initial Counter Register */
-            mcPWM_INIT_16B_tag INIT0;      /* offset: 0x0002 size: 16 bit */
-                                                   /* Control 2 Register */
-            mcPWM_CTRL2_16B_tag CTRL20;    /* offset: 0x0004 size: 16 bit */
-                                                     /* Control Register */
-            mcPWM_CTRL1_16B_tag CTRL10;    /* offset: 0x0006 size: 16 bit */
-                                                     /* Value Register 0 */
-            mcPWM_VAL_0_16B_tag VAL_00;    /* offset: 0x0008 size: 16 bit */
-                                                     /* Value Register 1 */
-            mcPWM_VAL_1_16B_tag VAL_10;    /* offset: 0x000A size: 16 bit */
-                                                     /* Value Register 2 */
-            mcPWM_VAL_2_16B_tag VAL_20;    /* offset: 0x000C size: 16 bit */
-                                                     /* Value Register 3 */
-            mcPWM_VAL_3_16B_tag VAL_30;    /* offset: 0x000E size: 16 bit */
-                                                     /* Value Register 4 */
-            mcPWM_VAL_4_16B_tag VAL_40;    /* offset: 0x0010 size: 16 bit */
-                                                     /* Value Register 5 */
-            mcPWM_VAL_5_16B_tag VAL_50;    /* offset: 0x0012 size: 16 bit */		
-                                          /* Fractional Delay Register A */
-            mcPWM_FRACA_16B_tag FRACA0;    /* offset: 0x0014 size: 16 bit */
-                                          /* Fractional Delay Register B */
-            mcPWM_FRACB_16B_tag FRACB0;    /* offset: 0x0016 size: 16 bit */
-                                              /* Output Control Register */
-            mcPWM_OCTRL_16B_tag OCTRL0;    /* offset: 0x0018 size: 16 bit */
-                                                      /* Status Register */
-            mcPWM_STS_16B_tag STS0;        /* offset: 0x001A size: 16 bit */
-                                           /* Interrupt Enable Registers */
-            mcPWM_INTEN_16B_tag INTEN0;    /* offset: 0x001C size: 16 bit */
-                                                 /* DMA Enable Registers */
-            mcPWM_DMAEN_16B_tag DMAEN0;    /* offset: 0x001E size: 16 bit */
-                                    /* Output Trigger Control  Registers */
-            mcPWM_TCTRL_16B_tag TCTRL0;    /* offset: 0x0020 size: 16 bit */
-                                    /* Fault Disable Mapping   Registers */
-            mcPWM_DISMAP_16B_tag DISMAP0;  /* offset: 0x0022 size: 16 bit */
-                                            /* Deadtime Count Register 0 */
-            mcPWM_DTCNT0_16B_tag DTCNT00;  /* offset: 0x0024 size: 16 bit */
-                                            /* Deadtime Count Register 1 */
-            mcPWM_DTCNT1_16B_tag DTCNT10;  /* offset: 0x0026 size: 16 bit */
-                                           /* Capture Control A Register */
-            mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA0;  /* offset: 0x0028 size: 16 bit */
-                                           /* Capture Compare A Register */
-            mcPWM_CAPTCMPA_16B_tag CAPTCMPA0;  /* offset: 0x002A size: 16 bit */
-                                           /* Capture Control B Register */
-            mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB0;  /* offset: 0x002C size: 16 bit */
-                                           /* Capture Compare B Register */
-            mcPWM_CAPTCMPB_16B_tag CAPTCMPB0;  /* offset: 0x002E size: 16 bit */
-                                           /* Capture Control X Register */
-            mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0;  /* offset: 0x0030 size: 16 bit */
-                                           /* Capture Compare X Register */
-            mcPWM_CAPTCMPX_16B_tag CAPTCMPX0;  /* offset: 0x0032 size: 16 bit */
-                                             /* Capture Value 0 Register */
-            mcPWM_CVAL0_16B_tag CVAL00;    /* offset: 0x0034 size: 16 bit */
-                                       /* Capture Value 0 Cycle Register */
-            mcPWM_CVAL0CYC_16B_tag CVAL0CYC0;  /* offset: 0x0036 size: 16 bit */
-                                             /* Capture Value 1 Register */
-            mcPWM_CVAL1_16B_tag CVAL10;    /* offset: 0x0038 size: 16 bit */
-                                       /* Capture Value 1 Cycle Register */
-            mcPWM_CVAL1CYC_16B_tag CVAL1CYC0;  /* offset: 0x003A size: 16 bit */
-                                             /* Capture Value 2 Register */
-            mcPWM_CVAL2_16B_tag CVAL20;    /* offset: 0x003C size: 16 bit */
-                                       /* Capture Value 2 Cycle Register */
-            mcPWM_CVAL2CYC_16B_tag CVAL2CYC0;  /* offset: 0x003E size: 16 bit */
-                                             /* Capture Value 3 Register */
-            mcPWM_CVAL3_16B_tag CVAL30;    /* offset: 0x0040 size: 16 bit */
-                                       /* Capture Value 3 Cycle Register */
-            mcPWM_CVAL3CYC_16B_tag CVAL3CYC0;  /* offset: 0x0042 size: 16 bit */
-                                             /* Capture Value 4 Register */
-            mcPWM_CVAL4_16B_tag CVAL40;    /* offset: 0x0044 size: 16 bit */
-                                       /* Capture Value 4 Cycle Register */
-            mcPWM_CVAL4CYC_16B_tag CVAL4CYC0;  /* offset: 0x0046 size: 16 bit */
-                                             /* Capture Value 5 Register */
-            mcPWM_CVAL5_16B_tag CVAL50;    /* offset: 0x0048 size: 16 bit */
-                                       /* Capture Value 5 Cycle Register */
-            mcPWM_CVAL5CYC_16B_tag CVAL5CYC0;  /* offset: 0x004A size: 16 bit */
-            int8_t mcPWM_reserved_004C_I2[4];
-                                                     /* Counter Register */
-            mcPWM_CNT_16B_tag CNT1;        /* offset: 0x0050 size: 16 bit */
-                                             /* Initial Counter Register */
-            mcPWM_INIT_16B_tag INIT1;      /* offset: 0x0052 size: 16 bit */
-                                                   /* Control 2 Register */
-            mcPWM_CTRL2_16B_tag CTRL21;    /* offset: 0x0054 size: 16 bit */
-                                                     /* Control Register */
-            mcPWM_CTRL1_16B_tag CTRL11;    /* offset: 0x0056 size: 16 bit */
-                                                     /* Value Register 0 */
-            mcPWM_VAL_0_16B_tag VAL_01;    /* offset: 0x0058 size: 16 bit */
-                                                     /* Value Register 1 */
-            mcPWM_VAL_1_16B_tag VAL_11;    /* offset: 0x005A size: 16 bit */
-                                                     /* Value Register 2 */
-            mcPWM_VAL_2_16B_tag VAL_21;    /* offset: 0x005C size: 16 bit */
-                                                     /* Value Register 3 */
-            mcPWM_VAL_3_16B_tag VAL_31;    /* offset: 0x005E size: 16 bit */
-                                                     /* Value Register 4 */
-            mcPWM_VAL_4_16B_tag VAL_41;    /* offset: 0x0060 size: 16 bit */
-                                                     /* Value Register 5 */
-            mcPWM_VAL_5_16B_tag VAL_51;    /* offset: 0x0062 size: 16 bit */
-                                          /* Fractional Delay Register A */
-            mcPWM_FRACA_16B_tag FRACA1;    /* offset: 0x0064 size: 16 bit */
-                                          /* Fractional Delay Register B */
-            mcPWM_FRACB_16B_tag FRACB1;    /* offset: 0x0066 size: 16 bit */
-                                              /* Output Control Register */
-            mcPWM_OCTRL_16B_tag OCTRL1;    /* offset: 0x0068 size: 16 bit */
-                                                      /* Status Register */
-            mcPWM_STS_16B_tag STS1;        /* offset: 0x006A size: 16 bit */
-                                           /* Interrupt Enable Registers */
-            mcPWM_INTEN_16B_tag INTEN1;    /* offset: 0x006C size: 16 bit */
-                                                 /* DMA Enable Registers */
-            mcPWM_DMAEN_16B_tag DMAEN1;    /* offset: 0x006E size: 16 bit */
-                                    /* Output Trigger Control  Registers */
-            mcPWM_TCTRL_16B_tag TCTRL1;    /* offset: 0x0070 size: 16 bit */
-                                    /* Fault Disable Mapping   Registers */
-            mcPWM_DISMAP_16B_tag DISMAP1;  /* offset: 0x0072 size: 16 bit */
-                                            /* Deadtime Count Register 0 */
-            mcPWM_DTCNT0_16B_tag DTCNT01;  /* offset: 0x0074 size: 16 bit */
-                                            /* Deadtime Count Register 1 */
-            mcPWM_DTCNT1_16B_tag DTCNT11;  /* offset: 0x0076 size: 16 bit */
-                                           /* Capture Control A Register */
-            mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA1;  /* offset: 0x0078 size: 16 bit */
-                                           /* Capture Compare A Register */
-            mcPWM_CAPTCMPA_16B_tag CAPTCMPA1;  /* offset: 0x007A size: 16 bit */
-                                           /* Capture Control B Register */
-            mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB1;  /* offset: 0x007C size: 16 bit */
-                                           /* Capture Compare B Register */
-            mcPWM_CAPTCMPB_16B_tag CAPTCMPB1;  /* offset: 0x007E size: 16 bit */
-                                           /* Capture Control X Register */
-            mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1;  /* offset: 0x0080 size: 16 bit */
-                                           /* Capture Compare X Register */
-            mcPWM_CAPTCMPX_16B_tag CAPTCMPX1;  /* offset: 0x0082 size: 16 bit */
-                                             /* Capture Value 0 Register */
-            mcPWM_CVAL0_16B_tag CVAL01;    /* offset: 0x0084 size: 16 bit */
-                                       /* Capture Value 0 Cycle Register */
-            mcPWM_CVAL0CYC_16B_tag CVAL0CYC1;  /* offset: 0x0086 size: 16 bit */
-                                             /* Capture Value 1 Register */
-            mcPWM_CVAL1_16B_tag CVAL11;    /* offset: 0x0088 size: 16 bit */
-                                       /* Capture Value 1 Cycle Register */
-            mcPWM_CVAL1CYC_16B_tag CVAL1CYC1;  /* offset: 0x008A size: 16 bit */
-                                             /* Capture Value 2 Register */
-            mcPWM_CVAL2_16B_tag CVAL21;    /* offset: 0x008C size: 16 bit */
-                                       /* Capture Value 2 Cycle Register */
-            mcPWM_CVAL2CYC_16B_tag CVAL2CYC1;  /* offset: 0x008E size: 16 bit */
-                                             /* Capture Value 3 Register */
-            mcPWM_CVAL3_16B_tag CVAL31;    /* offset: 0x0090 size: 16 bit */
-                                       /* Capture Value 3 Cycle Register */
-            mcPWM_CVAL3CYC_16B_tag CVAL3CYC1;  /* offset: 0x0092 size: 16 bit */
-                                             /* Capture Value 4 Register */
-            mcPWM_CVAL4_16B_tag CVAL41;    /* offset: 0x0094 size: 16 bit */
-                                       /* Capture Value 4 Cycle Register */
-            mcPWM_CVAL4CYC_16B_tag CVAL4CYC1;  /* offset: 0x0096 size: 16 bit */
-                                             /* Capture Value 5 Register */
-            mcPWM_CVAL5_16B_tag CVAL51;    /* offset: 0x0098 size: 16 bit */
-                                       /* Capture Value 5 Cycle Register */
-            mcPWM_CVAL5CYC_16B_tag CVAL5CYC1;  /* offset: 0x009A size: 16 bit */
-            int8_t mcPWM_reserved_009C_I2[4];
-                                                     /* Counter Register */
-            mcPWM_CNT_16B_tag CNT2;        /* offset: 0x00A0 size: 16 bit */
-                                             /* Initial Counter Register */
-            mcPWM_INIT_16B_tag INIT2;      /* offset: 0x00A2 size: 16 bit */
-                                                   /* Control 2 Register */
-            mcPWM_CTRL2_16B_tag CTRL22;    /* offset: 0x00A4 size: 16 bit */
-                                                     /* Control Register */
-            mcPWM_CTRL1_16B_tag CTRL12;    /* offset: 0x00A6 size: 16 bit */
-                                                     /* Value Register 0 */
-            mcPWM_VAL_0_16B_tag VAL_02;    /* offset: 0x00A8 size: 16 bit */
-                                                     /* Value Register 1 */
-            mcPWM_VAL_1_16B_tag VAL_12;    /* offset: 0x00AA size: 16 bit */
-                                                     /* Value Register 2 */
-            mcPWM_VAL_2_16B_tag VAL_22;    /* offset: 0x00AC size: 16 bit */
-                                                     /* Value Register 3 */
-            mcPWM_VAL_3_16B_tag VAL_32;    /* offset: 0x00AE size: 16 bit */
-                                                     /* Value Register 4 */
-            mcPWM_VAL_4_16B_tag VAL_42;    /* offset: 0x00B0 size: 16 bit */
-                                                     /* Value Register 5 */
-            mcPWM_VAL_5_16B_tag VAL_52;    /* offset: 0x00B2 size: 16 bit */
-                                          /* Fractional Delay Register A */
-            mcPWM_FRACA_16B_tag FRACA2;    /* offset: 0x00B4 size: 16 bit */
-                                          /* Fractional Delay Register B */
-            mcPWM_FRACB_16B_tag FRACB2;    /* offset: 0x00B6 size: 16 bit */
-                                              /* Output Control Register */
-            mcPWM_OCTRL_16B_tag OCTRL2;    /* offset: 0x00B8 size: 16 bit */
-                                                      /* Status Register */
-            mcPWM_STS_16B_tag STS2;        /* offset: 0x00BA size: 16 bit */
-                                           /* Interrupt Enable Registers */
-            mcPWM_INTEN_16B_tag INTEN2;    /* offset: 0x00BC size: 16 bit */
-                                                 /* DMA Enable Registers */
-            mcPWM_DMAEN_16B_tag DMAEN2;    /* offset: 0x00BE size: 16 bit */
-                                    /* Output Trigger Control  Registers */
-            mcPWM_TCTRL_16B_tag TCTRL2;    /* offset: 0x00C0 size: 16 bit */
-                                    /* Fault Disable Mapping   Registers */
-            mcPWM_DISMAP_16B_tag DISMAP2;  /* offset: 0x00C2 size: 16 bit */
-                                            /* Deadtime Count Register 0 */
-            mcPWM_DTCNT0_16B_tag DTCNT02;  /* offset: 0x00C4 size: 16 bit */
-                                            /* Deadtime Count Register 1 */
-            mcPWM_DTCNT1_16B_tag DTCNT12;  /* offset: 0x00C6 size: 16 bit */
-                                           /* Capture Control A Register */
-            mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA2;  /* offset: 0x00C8 size: 16 bit */
-                                           /* Capture Compare A Register */
-            mcPWM_CAPTCMPA_16B_tag CAPTCMPA2;  /* offset: 0x00CA size: 16 bit */
-                                           /* Capture Control B Register */
-            mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB2;  /* offset: 0x00CC size: 16 bit */
-                                           /* Capture Compare B Register */
-            mcPWM_CAPTCMPB_16B_tag CAPTCMPB2;  /* offset: 0x00CE size: 16 bit */
-                                           /* Capture Control X Register */
-            mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2;  /* offset: 0x00D0 size: 16 bit */
-                                           /* Capture Compare X Register */
-            mcPWM_CAPTCMPX_16B_tag CAPTCMPX2;  /* offset: 0x00D2 size: 16 bit */
-                                             /* Capture Value 0 Register */
-            mcPWM_CVAL0_16B_tag CVAL02;    /* offset: 0x00D4 size: 16 bit */
-                                       /* Capture Value 0 Cycle Register */
-            mcPWM_CVAL0CYC_16B_tag CVAL0CYC2;  /* offset: 0x00D6 size: 16 bit */
-                                             /* Capture Value 1 Register */
-            mcPWM_CVAL1_16B_tag CVAL12;    /* offset: 0x00D8 size: 16 bit */
-                                       /* Capture Value 1 Cycle Register */
-            mcPWM_CVAL1CYC_16B_tag CVAL1CYC2;  /* offset: 0x00DA size: 16 bit */
-                                             /* Capture Value 2 Register */
-            mcPWM_CVAL2_16B_tag CVAL22;    /* offset: 0x00DC size: 16 bit */
-                                       /* Capture Value 2 Cycle Register */
-            mcPWM_CVAL2CYC_16B_tag CVAL2CYC2;  /* offset: 0x00DE size: 16 bit */
-                                             /* Capture Value 3 Register */
-            mcPWM_CVAL3_16B_tag CVAL32;    /* offset: 0x00E0 size: 16 bit */
-                                       /* Capture Value 3 Cycle Register */
-            mcPWM_CVAL3CYC_16B_tag CVAL3CYC2;  /* offset: 0x00E2 size: 16 bit */
-                                             /* Capture Value 4 Register */
-            mcPWM_CVAL4_16B_tag CVAL42;    /* offset: 0x00E4 size: 16 bit */
-                                       /* Capture Value 4 Cycle Register */
-            mcPWM_CVAL4CYC_16B_tag CVAL4CYC2;  /* offset: 0x00E6 size: 16 bit */
-                                             /* Capture Value 5 Register */
-            mcPWM_CVAL5_16B_tag CVAL52;    /* offset: 0x00E8 size: 16 bit */
-                                       /* Capture Value 5 Cycle Register */
-            mcPWM_CVAL5CYC_16B_tag CVAL5CYC2;  /* offset: 0x00EA size: 16 bit */
-            int8_t mcPWM_reserved_00EC_I2[4];
-                                                     /* Counter Register */
-            mcPWM_CNT_16B_tag CNT3;        /* offset: 0x00F0 size: 16 bit */
-                                             /* Initial Counter Register */
-            mcPWM_INIT_16B_tag INIT3;      /* offset: 0x00F2 size: 16 bit */
-                                                   /* Control 2 Register */
-            mcPWM_CTRL2_16B_tag CTRL23;    /* offset: 0x00F4 size: 16 bit */
-                                                     /* Control Register */
-            mcPWM_CTRL1_16B_tag CTRL13;    /* offset: 0x00F6 size: 16 bit */
-                                                     /* Value Register 0 */
-            mcPWM_VAL_0_16B_tag VAL_03;    /* offset: 0x00F8 size: 16 bit */
-                                                     /* Value Register 1 */
-            mcPWM_VAL_1_16B_tag VAL_13;    /* offset: 0x00FA size: 16 bit */
-                                                     /* Value Register 2 */
-            mcPWM_VAL_2_16B_tag VAL_23;    /* offset: 0x00FC size: 16 bit */
-                                                     /* Value Register 3 */
-            mcPWM_VAL_3_16B_tag VAL_33;    /* offset: 0x00FE size: 16 bit */
-                                                     /* Value Register 4 */
-            mcPWM_VAL_4_16B_tag VAL_43;    /* offset: 0x0100 size: 16 bit */
-                                                     /* Value Register 5 */
-            mcPWM_VAL_5_16B_tag VAL_53;    /* offset: 0x0102 size: 16 bit */
-                                          /* Fractional Delay Register A */
-            mcPWM_FRACA_16B_tag FRACA3;    /* offset: 0x0104 size: 16 bit */
-                                          /* Fractional Delay Register B */
-            mcPWM_FRACB_16B_tag FRACB3;    /* offset: 0x0106 size: 16 bit */
-                                              /* Output Control Register */
-            mcPWM_OCTRL_16B_tag OCTRL3;    /* offset: 0x0108 size: 16 bit */
-                                                      /* Status Register */
-            mcPWM_STS_16B_tag STS3;        /* offset: 0x010A size: 16 bit */
-                                           /* Interrupt Enable Registers */
-            mcPWM_INTEN_16B_tag INTEN3;    /* offset: 0x010C size: 16 bit */
-                                                 /* DMA Enable Registers */
-            mcPWM_DMAEN_16B_tag DMAEN3;    /* offset: 0x010E size: 16 bit */
-                                    /* Output Trigger Control  Registers */
-            mcPWM_TCTRL_16B_tag TCTRL3;    /* offset: 0x0110 size: 16 bit */
-                                    /* Fault Disable Mapping   Registers */
-            mcPWM_DISMAP_16B_tag DISMAP3;  /* offset: 0x0112 size: 16 bit */
-                                            /* Deadtime Count Register 0 */
-            mcPWM_DTCNT0_16B_tag DTCNT03;  /* offset: 0x0114 size: 16 bit */
-                                            /* Deadtime Count Register 1 */
-            mcPWM_DTCNT1_16B_tag DTCNT13;  /* offset: 0x0116 size: 16 bit */
-                                           /* Capture Control A Register */
-            mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA3;  /* offset: 0x0118 size: 16 bit */
-                                           /* Capture Compare A Register */
-            mcPWM_CAPTCMPA_16B_tag CAPTCMPA3;  /* offset: 0x011A size: 16 bit */
-                                           /* Capture Control B Register */
-            mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB3;  /* offset: 0x011C size: 16 bit */
-                                           /* Capture Compare B Register */
-            mcPWM_CAPTCMPB_16B_tag CAPTCMPB3;  /* offset: 0x011E size: 16 bit */
-                                           /* Capture Control X Register */
-            mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3;  /* offset: 0x0120 size: 16 bit */
-                                           /* Capture Compare X Register */
-            mcPWM_CAPTCMPX_16B_tag CAPTCMPX3;  /* offset: 0x0122 size: 16 bit */
-                                             /* Capture Value 0 Register */
-            mcPWM_CVAL0_16B_tag CVAL03;    /* offset: 0x0124 size: 16 bit */
-                                       /* Capture Value 0 Cycle Register */
-            mcPWM_CVAL0CYC_16B_tag CVAL0CYC3;  /* offset: 0x0126 size: 16 bit */
-                                             /* Capture Value 1 Register */
-            mcPWM_CVAL1_16B_tag CVAL13;    /* offset: 0x0128 size: 16 bit */
-                                       /* Capture Value 1 Cycle Register */
-            mcPWM_CVAL1CYC_16B_tag CVAL1CYC3;  /* offset: 0x012A size: 16 bit */
-                                             /* Capture Value 2 Register */
-            mcPWM_CVAL2_16B_tag CVAL23;    /* offset: 0x012C size: 16 bit */
-                                       /* Capture Value 2 Cycle Register */
-            mcPWM_CVAL2CYC_16B_tag CVAL2CYC3;  /* offset: 0x012E size: 16 bit */
-                                             /* Capture Value 3 Register */
-            mcPWM_CVAL3_16B_tag CVAL33;    /* offset: 0x0130 size: 16 bit */
-                                       /* Capture Value 3 Cycle Register */
-            mcPWM_CVAL3CYC_16B_tag CVAL3CYC3;  /* offset: 0x0132 size: 16 bit */
-                                             /* Capture Value 4 Register */
-            mcPWM_CVAL4_16B_tag CVAL43;    /* offset: 0x0134 size: 16 bit */
-                                       /* Capture Value 4 Cycle Register */
-            mcPWM_CVAL4CYC_16B_tag CVAL4CYC3;  /* offset: 0x0136 size: 16 bit */
-                                             /* Capture Value 5 Register */
-            mcPWM_CVAL5_16B_tag CVAL53;    /* offset: 0x0138 size: 16 bit */
-                                       /* Capture Value 5 Cycle Register */
-            mcPWM_CVAL5CYC_16B_tag CVAL5CYC3;  /* offset: 0x013A size: 16 bit */
-            int8_t mcPWM_reserved_013C_E2[4];
-         };
-
-      };
-                                               /* Output Enable Register */
-      mcPWM_OUTEN_16B_tag OUTEN;           /* offset: 0x0140 size: 16 bit */
-                                                        /* Mask Register */
-      mcPWM_MASK_16B_tag MASK;             /* offset: 0x0142 size: 16 bit */
-                                  /* Software Controlled Output Register */
-      mcPWM_SWCOUT_16B_tag SWCOUT;         /* offset: 0x0144 size: 16 bit */
-                                      /* Deadtime Source Select Register */
-      mcPWM_DTSRCSEL_16B_tag DTSRCSEL;     /* offset: 0x0146 size: 16 bit */
-                                              /* Master Control Register */
-      mcPWM_MCTRL_16B_tag MCTRL;           /* offset: 0x0148 size: 16 bit */
-      int8_t mcPWM_reserved_014A[2];
-                                               /* Fault Control Register */
-      mcPWM_FCTRL_16B_tag FCTRL;           /* offset: 0x014C size: 16 bit */
-                                                /* Fault Status Register */
-      mcPWM_FSTS_16B_tag FSTS;             /* offset: 0x014E size: 16 bit */
-                                                /* Fault Filter Register */
-      mcPWM_FFILT_16B_tag FFILT;           /* offset: 0x0150 size: 16 bit */
-   } mcPWM_tag;
-
-
-#define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL)
-#define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: LINFLEX  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* LIN Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  CCD:1;             /* Checksum Calculation Disable */
-         vuint32_t  CFD:1;             /* Checksum Field Disable */
-         vuint32_t  LASE:1;            /* LIN Auto Synchronization Enable */
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  AUTOWU:1;          /* Auto Wake Up */
-#else
-         vuint32_t  AWUM:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t  MBL:4;             /* Master Break Length */
-         vuint32_t  BF:1;              /* By-Pass Filter */
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  SLFM:1;            /* Selftest Mode */
-#else
-         vuint32_t  SFTM:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t  LBKM:1;            /* Loopback Mode */
-         vuint32_t  MME:1;             /* Master Mode Enable */
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  SSBL:1;            /* Slave Mode Synch Break Length */
-#else
-         vuint32_t  SSDT:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t  RBLM:1;            /* Receiver Buffer Locked Mode */
-         vuint32_t  SLEEP:1;           /* Sleep Mode Request */
-         vuint32_t  INIT:1;            /* Initialization Mode Request */
-      } B;
-   } LINFLEX_LINCR1_32B_tag;
-
-   typedef union {   /* LIN Interrupt Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  SZIE:1;            /* Stuck at Zero Interrupt Enable */
-         vuint32_t  OCIE:1;            /* Output Compare Interrupt Enable */
-         vuint32_t  BEIE:1;            /* Bit Error Interrupt Enable */
-         vuint32_t  CEIE:1;            /* Checksum Error Interrupt Enable */
-         vuint32_t  HEIE:1;            /* Header Error Interrupt Enable */
-         vuint32_t:2;
-         vuint32_t  FEIE:1;            /* Frame Error Interrupt Enable */
-         vuint32_t  BOIE:1;            /* Buffer Overrun Error Interrupt Enable */
-         vuint32_t  LSIE:1;            /* LIN State Interrupt Enable */
-         vuint32_t  WUIE:1;            /* Wakeup Interrupt Enable */
-         vuint32_t  DBFIE:1;           /* Data Buffer Full Interrupt Enable */
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  DBEIE_TOIE:1;      /* Data Buffer Empty Interrupt Enable */
-#else
-         vuint32_t  DBEIE:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t  DRIE:1;            /* Data Reception complete Interrupt Enable */
-         vuint32_t  DTIE:1;            /* Data Transmitted Interrupt Enable */
-         vuint32_t  HRIE:1;            /* Header Received Interrupt Enable */
-      } B;
-   } LINFLEX_LINIER_32B_tag;
-
-   typedef union {   /* LIN Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  LINS:4;            /* LIN State */
-         vuint32_t:2;
-         vuint32_t  RMB:1;             /* Release Message Buffer */
-         vuint32_t:1;
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  RXBUSY:1;          /* Receiver Busy Flag */
-#else
-         vuint32_t  RBSY:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  RDI:1;             /* LIN Receive Signal */
-#else
-         vuint32_t  RPS:1;               /* deprecated name - please avoid */
-#endif
-         vuint32_t  WUF:1;             /* Wake Up Flag */
-         vuint32_t  DBFF:1;            /* Data Buffer Full Flag */
-         vuint32_t  DBEF:1;            /* Data Buffer Empty Flag */
-         vuint32_t  DRF:1;             /* Data Reception Completed Flag */
-         vuint32_t  DTF:1;             /* Data Transmission Completed Flag */
-         vuint32_t  HRF:1;             /* Header Received Flag */
-      } B;
-   } LINFLEX_LINSR_32B_tag;
-
-   typedef union {   /* LIN Error Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  SZF:1;             /* Stuck at Zero Flag */
-         vuint32_t  OCF:1;             /* Output Compare Flag */
-         vuint32_t  BEF:1;             /* Bit Error Flag */
-         vuint32_t  CEF:1;             /* Checksum Error Flag */
-         vuint32_t  SFEF:1;            /* Sync Field Error Flag */
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  SDEF:1;            /* Sync Delimiter Error Flag */
-#else
-         vuint32_t  BDEF:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t  IDPEF:1;           /* ID Parity Error Flag */
-         vuint32_t  FEF:1;             /* Framing Error Flag */
-         vuint32_t  BOF:1;             /* Buffer Overrun Flag */
-         vuint32_t:6;
-         vuint32_t  NF:1;              /* Noise Flag */
-      } B;
-   } LINFLEX_LINESR_32B_tag;
-
-   typedef union {   /* UART Mode Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  TDFL_TFC:3;        /* Transmitter Data Field Length/TX FIFO Counter */
-         vuint32_t  RDFL_RFC0:3;       /* Reception Data Field Length/RX FIFO Counter */
-         vuint32_t  RFBM:1;            /* RX FIFO/ Buffer Mode */
-         vuint32_t  TFBM:1;            /* TX FIFO/ Buffer Mode */
-         vuint32_t  WL1:1;             /* Word Length in UART mode - bit 1 */
-         vuint32_t  PC1:1;             /* Parity Check - bit 1 */
-         vuint32_t  RXEN:1;            /* Receiver Enable */
-         vuint32_t  TXEN:1;            /* Transmitter Enable */
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  PC0:1;             /* Parity Check - bit 0 */
-#else
-         vuint32_t  OP:1;                /* deprecated name - please avoid */
-#endif
-         vuint32_t  PCE:1;             /* Parity Control Enable */
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  WL0:1;             /* Word Length in UART Mode - bit 0 */
-#else
-         vuint32_t  WL:1;                /* deprecated name - please avoid */
-#endif
-         vuint32_t  UART:1;            /* UART Mode */
-      } B;
-   } LINFLEX_UARTCR_32B_tag;
-
-   typedef union {   /* UART Mode Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  SZF:1;             /* Stuck at Zero Flag */
-         vuint32_t  OCF:1;             /* Output Compare Flag */
-         vuint32_t  PE:4;              /* Parity Error Flag */
-         vuint32_t  RMB:1;             /* Release Message Buffer */
-         vuint32_t  FEF:1;             /* Framing Error Flag */
-         vuint32_t  BOF:1;             /* Buffer Overrun Flag */
-         vuint32_t  RDI:1;             /* Receiver Data Input Signal */
-         vuint32_t  WUF:1;             /* Wakeup Flag */
-         vuint32_t:1;
-         vuint32_t  TO:1;              /* Time Out */
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  DRF_RFE:1;         /* Data Reception Completed Flag/RX FIFO Empty Flag */
-#else
-         vuint32_t  DRF:1;               /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  DTF_TFF:1;         /* Data Transmission Completed Flag/TX FIFO Full Flag */
-#else
-         vuint32_t  DTF:1;               /* deprecated name - please avoid */
-#endif
-         vuint32_t  NF:1;              /* Noise Flag */
-      } B;
-   } LINFLEX_UARTSR_32B_tag;
-
-   typedef union {   /* LIN Time-Out Control Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:21;
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  MODE:1;            /* Time-out Counter Mode */
-#else
-         vuint32_t  LTOM:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t  IOT:1;             /* Idle on Timeout */
-         vuint32_t  TOCE:1;            /* Time-Out Counter Enable */
-         vuint32_t  CNT:8;             /* Counter Value */
-      } B;
-   } LINFLEX_LINTCSR_32B_tag;
-
-   typedef union {   /* LIN Output Compare Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  OC2:8;             /* Output Compare Value 2 */
-         vuint32_t  OC1:8;             /* Output Compare Value 1 */
-      } B;
-   } LINFLEX_LINOCR_32B_tag;
-
-   typedef union {   /* LIN Time-Out Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:20;
-         vuint32_t  RTO:4;             /* Response Time-Out Value */
-         vuint32_t:1;
-         vuint32_t  HTO:7;             /* Header Time-Out Value */
-      } B;
-   } LINFLEX_LINTOCR_32B_tag;
-
-   typedef union {   /* LIN Fractional Baud Rate Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  FBR:4;             /* Fractional Baud Rates */
-#else
-         vuint32_t  DIV_F:4;             /* deprecated name - please avoid */
-#endif
-      } B;
-   } LINFLEX_LINFBRR_32B_tag;
-
-   typedef union {   /* LIN Integer Baud Rate Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:13;
-#ifndef USE_FIELD_ALIASES_LINFLEX
-         vuint32_t  IBR:19;            /* Integer Baud Rates */
-#else
-         vuint32_t  DIV_M:19;            /* deprecated name - please avoid */
-#endif
-      } B;
-   } LINFLEX_LINIBRR_32B_tag;
-
-   typedef union {   /* LIN Checksum Field Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:24;
-         vuint32_t  CF:8;              /* Checksum Bits */
-      } B;
-   } LINFLEX_LINCFR_32B_tag;
-
-   typedef union {   /* LIN Control Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t:17;
-         vuint32_t  IOBE:1;            /* Idle on Bit Error */
-         vuint32_t  IOPE:1;            /* Idle on Identifier Parity Error */
-         vuint32_t  WURQ:1;            /* Wakeup Generate Request */
-         vuint32_t  DDRQ:1;            /* Data Discard Request */
-         vuint32_t  DTRQ:1;            /* Data Transmission Request */
-         vuint32_t  ABRQ:1;            /* Abort Request */
-         vuint32_t  HTRQ:1;            /* Header Transmission Request */
-         vuint32_t:8;
-      } B;
-   } LINFLEX_LINCR2_32B_tag;
-
-   typedef union {   /* Buffer Identifier Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  DFL:6;             /* Data Field Length */
-         vuint32_t  DIR:1;             /* Direction */
-         vuint32_t  CCS:1;             /* Classic Checksum */
-         vuint32_t:2;
-         vuint32_t  ID:6;              /* Identifier */
-      } B;
-   } LINFLEX_BIDR_32B_tag;
-
-   typedef union {   /* Buffer Data Register Least Significant */
-      vuint32_t R;
-      struct {
-         vuint32_t  DATA3:8;           /* Data3 */
-         vuint32_t  DATA2:8;           /* Data2 */
-         vuint32_t  DATA1:8;           /* Data1 */
-         vuint32_t  DATA0:8;           /* Data0 */
-      } B;
-   } LINFLEX_BDRL_32B_tag;
-
-   typedef union {   /* Buffer Data Register Most Significant */
-      vuint32_t R;
-      struct {
-         vuint32_t  DATA7:8;           /* Data7 */
-         vuint32_t  DATA6:8;           /* Data6 */
-         vuint32_t  DATA5:8;           /* Data5 */
-         vuint32_t  DATA4:8;           /* Data4 */
-      } B;
-   } LINFLEX_BDRM_32B_tag;
-
-   typedef union {   /* Identifier Filter Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:24;
-         vuint32_t  FACT:8;            /* Filter Active */
-      } B;
-   } LINFLEX_IFER_32B_tag;
-
-   typedef union {   /* Identifier Filter Match Index */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-         vuint32_t  IFMI_IFMI:4;       /* Filter Match Index */
-      } B;
-   } LINFLEX_IFMI_32B_tag;
-
-   typedef union {   /* Identifier Filter Mode Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-         vuint32_t  IFM:4;             /* Filter Mode */
-      } B;
-   } LINFLEX_IFMR_32B_tag;
-
-
-   /* Register layout for all registers IFCR... */
-
-   typedef union {   /* Identifier Filter Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  DFL:6;             /* Data Field Length */
-         vuint32_t  DIR:1;             /* Direction */
-         vuint32_t  CCS:1;             /* Classic Checksum */
-         vuint32_t:2;
-         vuint32_t  ID:6;              /* Identifier */
-      } B;
-   } LINFLEX_IFCR_32B_tag;
-
-   typedef union {   /* Global Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:26;
-         vuint32_t  TDFBM:1;           /* Transmit Data First Bit MSB */
-         vuint32_t  RDFBM:1;           /* Received Data First Bit MSB */
-         vuint32_t  TDLIS:1;           /* Transmit Data Level Inversion Selection */
-         vuint32_t  RDLIS:1;           /* Received Data Level Inversion Selection */
-         vuint32_t  STOP:1;            /* 1/2 stop bit configuration */
-         vuint32_t  SR:1;              /* Soft Reset */
-      } B;
-   } LINFLEX_GCR_32B_tag;
-
-   typedef union {   /* UART Preset Time Out Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:20;
-         vuint32_t  PTO:12;            /* Preset Time Out */
-      } B;
-   } LINFLEX_UARTPTO_32B_tag;
-
-   typedef union {   /* UART Current Time Out Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:20;
-         vuint32_t  CTO:12;            /* Current Time Out */
-      } B;
-   } LINFLEX_UARTCTO_32B_tag;
-
-   typedef union {   /* DMA TX Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:17;
-         vuint32_t  DTE:15;            /* DMA Tx channel Enable */
-      } B;
-   } LINFLEX_DMATXE_32B_tag;
-
-   typedef union {   /* DMA RX Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:17;
-         vuint32_t  DRE:15;            /* DMA Rx channel Enable */
-      } B;
-   } LINFLEX_DMARXE_32B_tag;
-
-   
-
-   typedef struct LINFLEX_tag{ /* start of LINFLEX_tag */
-                                                 /* LIN Control Register */
-      LINFLEX_LINCR1_32B_tag LINCR1;       /* offset: 0x0000 size: 32 bit */
-                                        /* LIN Interrupt Enable Register */
-      LINFLEX_LINIER_32B_tag LINIER;       /* offset: 0x0004 size: 32 bit */
-                                                  /* LIN Status Register */
-      LINFLEX_LINSR_32B_tag LINSR;         /* offset: 0x0008 size: 32 bit */
-                                            /* LIN Error Status Register */
-      LINFLEX_LINESR_32B_tag LINESR;       /* offset: 0x000C size: 32 bit */
-                                           /* UART Mode Control Register */
-      LINFLEX_UARTCR_32B_tag UARTCR;       /* offset: 0x0010 size: 32 bit */
-                                            /* UART Mode Status Register */
-      LINFLEX_UARTSR_32B_tag UARTSR;       /* offset: 0x0014 size: 32 bit */
-                                 /* LIN Time-Out Control Status Register */
-      LINFLEX_LINTCSR_32B_tag LINTCSR;     /* offset: 0x0018 size: 32 bit */
-                                          /* LIN Output Compare Register */
-      LINFLEX_LINOCR_32B_tag LINOCR;       /* offset: 0x001C size: 32 bit */
-                                        /* LIN Time-Out Control Register */
-      LINFLEX_LINTOCR_32B_tag LINTOCR;     /* offset: 0x0020 size: 32 bit */
-                                    /* LIN Fractional Baud Rate Register */
-      LINFLEX_LINFBRR_32B_tag LINFBRR;     /* offset: 0x0024 size: 32 bit */
-                                       /* LIN Integer Baud Rate Register */
-      LINFLEX_LINIBRR_32B_tag LINIBRR;     /* offset: 0x0028 size: 32 bit */
-                                          /* LIN Checksum Field Register */
-      LINFLEX_LINCFR_32B_tag LINCFR;       /* offset: 0x002C size: 32 bit */
-                                               /* LIN Control Register 2 */
-      LINFLEX_LINCR2_32B_tag LINCR2;       /* offset: 0x0030 size: 32 bit */
-                                           /* Buffer Identifier Register */
-      LINFLEX_BIDR_32B_tag BIDR;           /* offset: 0x0034 size: 32 bit */
-                               /* Buffer Data Register Least Significant */
-      LINFLEX_BDRL_32B_tag BDRL;           /* offset: 0x0038 size: 32 bit */
-                                /* Buffer Data Register Most Significant */
-      LINFLEX_BDRM_32B_tag BDRM;           /* offset: 0x003C size: 32 bit */
-                                    /* Identifier Filter Enable Register */
-      LINFLEX_IFER_32B_tag IFER;           /* offset: 0x0040 size: 32 bit */
-                                        /* Identifier Filter Match Index */
-      LINFLEX_IFMI_32B_tag IFMI;           /* offset: 0x0044 size: 32 bit */
-                                     /* Identifier Filter Mode Register */
-      LINFLEX_IFMR_32B_tag IFMR;           /* offset: 0x0048 size: 32 bit */
-      union {
-                                   /* Identifier Filter Control Register */
-         LINFLEX_IFCR_32B_tag IFCR[8];     /* offset: 0x004C  (0x0004 x 8) */
-
-         struct {
-                                   /* Identifier Filter Control Register */
-            LINFLEX_IFCR_32B_tag IFCR0;    /* offset: 0x004C size: 32 bit */
-            LINFLEX_IFCR_32B_tag IFCR1;    /* offset: 0x0050 size: 32 bit */
-            LINFLEX_IFCR_32B_tag IFCR2;    /* offset: 0x0054 size: 32 bit */
-            LINFLEX_IFCR_32B_tag IFCR3;    /* offset: 0x0058 size: 32 bit */
-            LINFLEX_IFCR_32B_tag IFCR4;    /* offset: 0x005C size: 32 bit */
-            LINFLEX_IFCR_32B_tag IFCR5;    /* offset: 0x0060 size: 32 bit */
-            LINFLEX_IFCR_32B_tag IFCR6;    /* offset: 0x0064 size: 32 bit */
-            LINFLEX_IFCR_32B_tag IFCR7;    /* offset: 0x0068 size: 32 bit */
-         };
-
-      };
-      int8_t LINFLEX_reserved_006C[32];
-                                             /* Global Control Register */
-      LINFLEX_GCR_32B_tag GCR;             /* offset: 0x008C size: 32 bit */
-                                        /* UART Preset Time Out Register */
-      LINFLEX_UARTPTO_32B_tag UARTPTO;     /* offset: 0x0090 size: 32 bit */
-                                       /* UART Current Time Out Register */
-      LINFLEX_UARTCTO_32B_tag UARTCTO;     /* offset: 0x0094 size: 32 bit */
-                                               /* DMA TX Enable Register */
-      LINFLEX_DMATXE_32B_tag DMATXE;       /* offset: 0x0098 size: 32 bit */
-                                               /* DMA RX Enable Register */
-      LINFLEX_DMARXE_32B_tag DMARXE;       /* offset: 0x009C size: 32 bit */
-   } LINFLEX_tag;
-
-
-#define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL)
-#define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: CRC  */
-/*                                                              */
-/****************************************************************/
-
-
-   /* Register layout for all registers CFG... */
-
-   typedef union {   /* CRC_CFG - CRC Configuration register */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint16_t  HALF[2];    /* individual halfwords can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-      struct {
-         vuint32_t:29;
-         vuint32_t  POLYG:1;           /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */
-         vuint32_t  SWAP:1;            /* SWAP selection */
-         vuint32_t  INV:1;             /* INV selection */
-      } B;
-   } CRC_CFG_32B_tag;
-
-
-   /* Register layout for all registers INP... */
-
-   typedef union {   /* CRC_INP - CRC Input register */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint16_t  HALF[2];    /* individual halfwords can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-   } CRC_INP_32B_tag;
-
-
-   /* Register layout for all registers CSTAT... */
-
-   typedef union {   /* CRC_STATUS - CRC Status register */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint16_t  HALF[2];    /* individual halfwords can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-   } CRC_CSTAT_32B_tag;
-
-
-   /* Register layout for all registers OUTP... */
-
-   typedef union {   /* CRC_STATUS - CRC OUTPUT register */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint16_t  HALF[2];    /* individual halfwords can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-   } CRC_OUTP_32B_tag;
-
-
-   typedef struct CRC_CNTX_struct_tag {
-
-                                 /* CRC_CFG - CRC Configuration register */
-      CRC_CFG_32B_tag CFG;                /* relative offset: 0x0000 */
-                                         /* CRC_INP - CRC Input register */
-      CRC_INP_32B_tag INP;                /* relative offset: 0x0004 */
-                                     /* CRC_STATUS - CRC Status register */
-      CRC_CSTAT_32B_tag CSTAT;            /* relative offset: 0x0008 */
-                                     /* CRC_STATUS - CRC OUTPUT register */
-      CRC_OUTP_32B_tag OUTP;              /* relative offset: 0x000C */
-
-   } CRC_CNTX_tag;
-
-
-   typedef struct CRC_struct_tag { /* start of CRC_tag */
-      union {
-                                                   /*  Register set CNTX */
-         CRC_CNTX_tag CNTX[3];             /* offset: 0x0000  (0x0010 x 3) */
-
-         struct {
-                                 /* CRC_CFG - CRC Configuration register */
-            CRC_CFG_32B_tag CFG0;          /* offset: 0x0000 size: 32 bit */
-                                         /* CRC_INP - CRC Input register */
-            CRC_INP_32B_tag INP0;          /* offset: 0x0004 size: 32 bit */
-                                     /* CRC_STATUS - CRC Status register */
-            CRC_CSTAT_32B_tag CSTAT0;      /* offset: 0x0008 size: 32 bit */
-                                     /* CRC_STATUS - CRC OUTPUT register */
-            CRC_OUTP_32B_tag OUTP0;        /* offset: 0x000C size: 32 bit */
-                                 /* CRC_CFG - CRC Configuration register */
-            CRC_CFG_32B_tag CFG1;          /* offset: 0x0010 size: 32 bit */
-                                         /* CRC_INP - CRC Input register */
-            CRC_INP_32B_tag INP1;          /* offset: 0x0014 size: 32 bit */
-                                     /* CRC_STATUS - CRC Status register */
-            CRC_CSTAT_32B_tag CSTAT1;      /* offset: 0x0018 size: 32 bit */
-                                     /* CRC_STATUS - CRC OUTPUT register */
-            CRC_OUTP_32B_tag OUTP1;        /* offset: 0x001C size: 32 bit */
-                                 /* CRC_CFG - CRC Configuration register */
-            CRC_CFG_32B_tag CFG2;          /* offset: 0x0020 size: 32 bit */
-                                         /* CRC_INP - CRC Input register */
-            CRC_INP_32B_tag INP2;          /* offset: 0x0024 size: 32 bit */
-                                     /* CRC_STATUS - CRC Status register */
-            CRC_CSTAT_32B_tag CSTAT2;      /* offset: 0x0028 size: 32 bit */
-                                     /* CRC_STATUS - CRC OUTPUT register */
-            CRC_OUTP_32B_tag OUTP2;        /* offset: 0x002C size: 32 bit */
-         };
-
-      };
-   } CRC_tag;
-
-
-#define CRC   (*(volatile CRC_tag *) 0xFFE68000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: FCCU  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* FCCU Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:23;
-         vuint32_t  NVML:1;            /* NVM configuration loaded */
-         vuint32_t  OPS:2;             /* Operation status */
-         vuint32_t:1;
-         vuint32_t  OPR:5;             /* Operation run */
-      } B;
-   } FCCU_CTRL_32B_tag;
-
-   typedef union {   /* FCCU CTRL Key Register */
-      vuint32_t R;
-   } FCCU_CTRLK_32B_tag;
-
-   typedef union {   /* FCCU Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:10;
-         vuint32_t  RCCE1:1;           /* RCC1 enable */
-         vuint32_t  RCCE0:1;           /* RCC0 enable */
-         vuint32_t  SMRT:4;            /* Safe Mode Request Timer */
-         vuint32_t:4;
-         vuint32_t  CM:1;              /* Config mode */
-         vuint32_t  SM:1;              /* Switching mode */
-         vuint32_t  PS:1;              /* Polarity Selection */
-         vuint32_t  FOM:3;             /* Fault Output Mode Selection */
-         vuint32_t  FOP:6;             /* Fault Output Prescaler */
-      } B;
-   } FCCU_CFG_32B_tag;
-
-   typedef union {   /* FCCU CF Configuration Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFC31:1;           /* CF 31 configuration */
-         vuint32_t  CFC30:1;           /* CF 30 configuration */
-         vuint32_t  CFC29:1;           /* CF 29 configuration */
-         vuint32_t  CFC28:1;           /* CF 28 configuration */
-         vuint32_t  CFC27:1;           /* CF 27 configuration */
-         vuint32_t  CFC26:1;           /* CF 26 configuration */
-         vuint32_t  CFC25:1;           /* CF 25 configuration */
-         vuint32_t  CFC24:1;           /* CF 24 configuration */
-         vuint32_t  CFC23:1;           /* CF 23 configuration */
-         vuint32_t  CFC22:1;           /* CF 22 configuration */
-         vuint32_t  CFC21:1;           /* CF 21 configuration */
-         vuint32_t  CFC20:1;           /* CF 20 configuration */
-         vuint32_t  CFC19:1;           /* CF 19 configuration */
-         vuint32_t  CFC18:1;           /* CF 18 configuration */
-         vuint32_t  CFC17:1;           /* CF 17 configuration */
-         vuint32_t  CFC16:1;           /* CF 16 configuration */
-         vuint32_t  CFC15:1;           /* CF 15 configuration */
-         vuint32_t  CFC14:1;           /* CF 14 configuration */
-         vuint32_t  CFC13:1;           /* CF 13 configuration */
-         vuint32_t  CFC12:1;           /* CF 12 configuration */
-         vuint32_t  CFC11:1;           /* CF 11 configuration */
-         vuint32_t  CFC10:1;           /* CF 10 configuration */
-         vuint32_t  CFC9:1;            /* CF 9 configuration */
-         vuint32_t  CFC8:1;            /* CF 8 configuration */
-         vuint32_t  CFC7:1;            /* CF 7 configuration */
-         vuint32_t  CFC6:1;            /* CF 6 configuration */
-         vuint32_t  CFC5:1;            /* CF 5 configuration */
-         vuint32_t  CFC4:1;            /* CF 4 configuration */
-         vuint32_t  CFC3:1;            /* CF 3 configuration */
-         vuint32_t  CFC2:1;            /* CF 2 configuration */
-         vuint32_t  CFC1:1;            /* CF 1 configuration */
-         vuint32_t  CFC0:1;            /* CF 0 configuration */
-      } B;
-   } FCCU_CF_CFG0_32B_tag;
-
-   typedef union {   /* FCCU CF Configuration Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFC63:1;           /* CF 63 configuration */
-         vuint32_t  CFC62:1;           /* CF 62 configuration */
-         vuint32_t  CFC61:1;           /* CF 61 configuration */
-         vuint32_t  CFC60:1;           /* CF 60 configuration */
-         vuint32_t  CFC59:1;           /* CF 59 configuration */
-         vuint32_t  CFC58:1;           /* CF 58 configuration */
-         vuint32_t  CFC57:1;           /* CF 57 configuration */
-         vuint32_t  CFC56:1;           /* CF 56 configuration */
-         vuint32_t  CFC55:1;           /* CF 55 configuration */
-         vuint32_t  CFC54:1;           /* CF 54 configuration */
-         vuint32_t  CFC53:1;           /* CF 53 configuration */
-         vuint32_t  CFC52:1;           /* CF 52 configuration */
-         vuint32_t  CFC51:1;           /* CF 51 configuration */
-         vuint32_t  CFC50:1;           /* CF 50 configuration */
-         vuint32_t  CFC49:1;           /* CF 49 configuration */
-         vuint32_t  CFC48:1;           /* CF 48 configuration */
-         vuint32_t  CFC47:1;           /* CF 47 configuration */
-         vuint32_t  CFC46:1;           /* CF 46 configuration */
-         vuint32_t  CFC45:1;           /* CF 45 configuration */
-         vuint32_t  CFC44:1;           /* CF 44 configuration */
-         vuint32_t  CFC43:1;           /* CF 43 configuration */
-         vuint32_t  CFC42:1;           /* CF 42 configuration */
-         vuint32_t  CFC41:1;           /* CF 41 configuration */
-         vuint32_t  CFC40:1;           /* CF 40 configuration */
-         vuint32_t  CFC39:1;           /* CF 39 configuration */
-         vuint32_t  CFC38:1;           /* CF 38 configuration */
-         vuint32_t  CFC37:1;           /* CF 37 configuration */
-         vuint32_t  CFC36:1;           /* CF 36 configuration */
-         vuint32_t  CFC35:1;           /* CF 35 configuration */
-         vuint32_t  CFC34:1;           /* CF 34 configuration */
-         vuint32_t  CFC33:1;           /* CF 33 configuration */
-         vuint32_t  CFC32:1;           /* CF 32 configuration */
-      } B;
-   } FCCU_CF_CFG1_32B_tag;
-
-   typedef union {   /* FCCU CF Configuration Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFC95:1;           /* CF 95 configuration */
-         vuint32_t  CFC94:1;           /* CF 94 configuration */
-         vuint32_t  CFC93:1;           /* CF 93 configuration */
-         vuint32_t  CFC92:1;           /* CF 92 configuration */
-         vuint32_t  CFC91:1;           /* CF 91 configuration */
-         vuint32_t  CFC90:1;           /* CF 90 configuration */
-         vuint32_t  CFC89:1;           /* CF 89 configuration */
-         vuint32_t  CFC88:1;           /* CF 88 configuration */
-         vuint32_t  CFC87:1;           /* CF 87 configuration */
-         vuint32_t  CFC86:1;           /* CF 86 configuration */
-         vuint32_t  CFC85:1;           /* CF 85 configuration */
-         vuint32_t  CFC84:1;           /* CF 84 configuration */
-         vuint32_t  CFC83:1;           /* CF 83 configuration */
-         vuint32_t  CFC82:1;           /* CF 82 configuration */
-         vuint32_t  CFC81:1;           /* CF 81 configuration */
-         vuint32_t  CFC80:1;           /* CF 80 configuration */
-         vuint32_t  CFC79:1;           /* CF 79 configuration */
-         vuint32_t  CFC78:1;           /* CF 78 configuration */
-         vuint32_t  CFC77:1;           /* CF 77 configuration */
-         vuint32_t  CFC76:1;           /* CF 76 configuration */
-         vuint32_t  CFC75:1;           /* CF 75 configuration */
-         vuint32_t  CFC74:1;           /* CF 74 configuration */
-         vuint32_t  CFC73:1;           /* CF 73 configuration */
-         vuint32_t  CFC72:1;           /* CF 72 configuration */
-         vuint32_t  CFC71:1;           /* CF 71 configuration */
-         vuint32_t  CFC70:1;           /* CF 70 configuration */
-         vuint32_t  CFC69:1;           /* CF 69 configuration */
-         vuint32_t  CFC68:1;           /* CF 68 configuration */
-         vuint32_t  CFC67:1;           /* CF 67 configuration */
-         vuint32_t  CFC66:1;           /* CF 66 configuration */
-         vuint32_t  CFC65:1;           /* CF 65 configuration */
-         vuint32_t  CFC64:1;           /* CF 64 configuration */
-      } B;
-   } FCCU_CF_CFG2_32B_tag;
-
-   typedef union {   /* FCCU CF Configuration Register 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFC127:1;          /* CF 127 configuration */
-         vuint32_t  CFC126:1;          /* CF 126 configuration */
-         vuint32_t  CFC125:1;          /* CF 125 configuration */
-         vuint32_t  CFC124:1;          /* CF 124 configuration */
-         vuint32_t  CFC123:1;          /* CF 123 configuration */
-         vuint32_t  CFC122:1;          /* CF 122 configuration */
-         vuint32_t  CFC121:1;          /* CF 121 configuration */
-         vuint32_t  CFC120:1;          /* CF 120 configuration */
-         vuint32_t  CFC119:1;          /* CF 119 configuration */
-         vuint32_t  CFC118:1;          /* CF 118 configuration */
-         vuint32_t  CFC117:1;          /* CF 117 configuration */
-         vuint32_t  CFC116:1;          /* CF 116 configuration */
-         vuint32_t  CFC115:1;          /* CF 115 configuration */
-         vuint32_t  CFC114:1;          /* CF 114 configuration */
-         vuint32_t  CFC113:1;          /* CF 113 configuration */
-         vuint32_t  CFC112:1;          /* CF 112 configuration */
-         vuint32_t  CFC111:1;          /* CF 111 configuration */
-         vuint32_t  CFC110:1;          /* CF 110 configuration */
-         vuint32_t  CFC109:1;          /* CF 109 configuration */
-         vuint32_t  CFC108:1;          /* CF 108 configuration */
-         vuint32_t  CFC107:1;          /* CF 107 configuration */
-         vuint32_t  CFC106:1;          /* CF 106 configuration */
-         vuint32_t  CFC105:1;          /* CF 105 configuration */
-         vuint32_t  CFC104:1;          /* CF 104 configuration */
-         vuint32_t  CFC103:1;          /* CF 103 configuration */
-         vuint32_t  CFC102:1;          /* CF 102 configuration */
-         vuint32_t  CFC101:1;          /* CF 101 configuration */
-         vuint32_t  CFC100:1;          /* CF 100 configuration */
-         vuint32_t  CFC99:1;           /* CF 99 configuration */
-         vuint32_t  CFC98:1;           /* CF 98 configuration */
-         vuint32_t  CFC97:1;           /* CF 97 configuration */
-         vuint32_t  CFC96:1;           /* CF 96 configuration */
-      } B;
-   } FCCU_CF_CFG3_32B_tag;
-
-   typedef union {   /* FCCU NCF Configuration Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFC31:1;          /* NCF 31 configuration */
-         vuint32_t  NCFC30:1;          /* NCF 30 configuration */
-         vuint32_t  NCFC29:1;          /* NCF 29 configuration */
-         vuint32_t  NCFC28:1;          /* NCF 28 configuration */
-         vuint32_t  NCFC27:1;          /* NCF 27 configuration */
-         vuint32_t  NCFC26:1;          /* NCF 26 configuration */
-         vuint32_t  NCFC25:1;          /* NCF 25 configuration */
-         vuint32_t  NCFC24:1;          /* NCF 24 configuration */
-         vuint32_t  NCFC23:1;          /* NCF 23 configuration */
-         vuint32_t  NCFC22:1;          /* NCF 22 configuration */
-         vuint32_t  NCFC21:1;          /* NCF 21 configuration */
-         vuint32_t  NCFC20:1;          /* NCF 20 configuration */
-         vuint32_t  NCFC19:1;          /* NCF 19 configuration */
-         vuint32_t  NCFC18:1;          /* NCF 18 configuration */
-         vuint32_t  NCFC17:1;          /* NCF 17 configuration */
-         vuint32_t  NCFC16:1;          /* NCF 16 configuration */
-         vuint32_t  NCFC15:1;          /* NCF 15 configuration */
-         vuint32_t  NCFC14:1;          /* NCF 14 configuration */
-         vuint32_t  NCFC13:1;          /* NCF 13 configuration */
-         vuint32_t  NCFC12:1;          /* NCF 12 configuration */
-         vuint32_t  NCFC11:1;          /* NCF 11 configuration */
-         vuint32_t  NCFC10:1;          /* NCF 10 configuration */
-         vuint32_t  NCFC9:1;           /* NCF 9 configuration */
-         vuint32_t  NCFC8:1;           /* NCF 8 configuration */
-         vuint32_t  NCFC7:1;           /* NCF 7 configuration */
-         vuint32_t  NCFC6:1;           /* NCF 6 configuration */
-         vuint32_t  NCFC5:1;           /* NCF 5 configuration */
-         vuint32_t  NCFC4:1;           /* NCF 4 configuration */
-         vuint32_t  NCFC3:1;           /* NCF 3 configuration */
-         vuint32_t  NCFC2:1;           /* NCF 2 configuration */
-         vuint32_t  NCFC1:1;           /* NCF 1 configuration */
-         vuint32_t  NCFC0:1;           /* NCF 0 configuration */
-      } B;
-   } FCCU_NCF_CFG0_32B_tag;
-
-   typedef union {   /* FCCU NCF Configuration Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFC63:1;          /* NCF 63 configuration */
-         vuint32_t  NCFC62:1;          /* NCF 62 configuration */
-         vuint32_t  NCFC61:1;          /* NCF 61 configuration */
-         vuint32_t  NCFC60:1;          /* NCF 60 configuration */
-         vuint32_t  NCFC59:1;          /* NCF 59 configuration */
-         vuint32_t  NCFC58:1;          /* NCF 58 configuration */
-         vuint32_t  NCFC57:1;          /* NCF 57 configuration */
-         vuint32_t  NCFC56:1;          /* NCF 56 configuration */
-         vuint32_t  NCFC55:1;          /* NCF 55 configuration */
-         vuint32_t  NCFC54:1;          /* NCF 54 configuration */
-         vuint32_t  NCFC53:1;          /* NCF 53 configuration */
-         vuint32_t  NCFC52:1;          /* NCF 52 configuration */
-         vuint32_t  NCFC51:1;          /* NCF 51 configuration */
-         vuint32_t  NCFC50:1;          /* NCF 50 configuration */
-         vuint32_t  NCFC49:1;          /* NCF 49 configuration */
-         vuint32_t  NCFC48:1;          /* NCF 48 configuration */
-         vuint32_t  NCFC47:1;          /* NCF 47 configuration */
-         vuint32_t  NCFC46:1;          /* NCF 46 configuration */
-         vuint32_t  NCFC45:1;          /* NCF 45 configuration */
-         vuint32_t  NCFC44:1;          /* NCF 44 configuration */
-         vuint32_t  NCFC43:1;          /* NCF 43 configuration */
-         vuint32_t  NCFC42:1;          /* NCF 42 configuration */
-         vuint32_t  NCFC41:1;          /* NCF 41 configuration */
-         vuint32_t  NCFC40:1;          /* NCF 40 configuration */
-         vuint32_t  NCFC39:1;          /* NCF 39 configuration */
-         vuint32_t  NCFC38:1;          /* NCF 38 configuration */
-         vuint32_t  NCFC37:1;          /* NCF 37 configuration */
-         vuint32_t  NCFC36:1;          /* NCF 36 configuration */
-         vuint32_t  NCFC35:1;          /* NCF 35 configuration */
-         vuint32_t  NCFC34:1;          /* NCF 34 configuration */
-         vuint32_t  NCFC33:1;          /* NCF 33 configuration */
-         vuint32_t  NCFC32:1;          /* NCF 32 configuration */
-      } B;
-   } FCCU_NCF_CFG1_32B_tag;
-
-   typedef union {   /* FCCU NCF Configuration Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFC95:1;          /* NCF 95 configuration */
-         vuint32_t  NCFC94:1;          /* NCF 94 configuration */
-         vuint32_t  NCFC93:1;          /* NCF 93 configuration */
-         vuint32_t  NCFC92:1;          /* NCF 92 configuration */
-         vuint32_t  NCFC91:1;          /* NCF 91 configuration */
-         vuint32_t  NCFC90:1;          /* NCF 90 configuration */
-         vuint32_t  NCFC89:1;          /* NCF 89 configuration */
-         vuint32_t  NCFC88:1;          /* NCF 88 configuration */
-         vuint32_t  NCFC87:1;          /* NCF 87 configuration */
-         vuint32_t  NCFC86:1;          /* NCF 86 configuration */
-         vuint32_t  NCFC85:1;          /* NCF 85 configuration */
-         vuint32_t  NCFC84:1;          /* NCF 84 configuration */
-         vuint32_t  NCFC83:1;          /* NCF 83 configuration */
-         vuint32_t  NCFC82:1;          /* NCF 82 configuration */
-         vuint32_t  NCFC81:1;          /* NCF 81 configuration */
-         vuint32_t  NCFC80:1;          /* NCF 80 configuration */
-         vuint32_t  NCFC79:1;          /* NCF 79 configuration */
-         vuint32_t  NCFC78:1;          /* NCF 78 configuration */
-         vuint32_t  NCFC77:1;          /* NCF 77 configuration */
-         vuint32_t  NCFC76:1;          /* NCF 76 configuration */
-         vuint32_t  NCFC75:1;          /* NCF 75 configuration */
-         vuint32_t  NCFC74:1;          /* NCF 74 configuration */
-         vuint32_t  NCFC73:1;          /* NCF 73 configuration */
-         vuint32_t  NCFC72:1;          /* NCF 72 configuration */
-         vuint32_t  NCFC71:1;          /* NCF 71 configuration */
-         vuint32_t  NCFC70:1;          /* NCF 70 configuration */
-         vuint32_t  NCFC69:1;          /* NCF 69 configuration */
-         vuint32_t  NCFC68:1;          /* NCF 68 configuration */
-         vuint32_t  NCFC67:1;          /* NCF 67 configuration */
-         vuint32_t  NCFC66:1;          /* NCF 66 configuration */
-         vuint32_t  NCFC65:1;          /* NCF 65 configuration */
-         vuint32_t  NCFC64:1;          /* NCF 64 configuration */
-      } B;
-   } FCCU_NCF_CFG2_32B_tag;
-
-   typedef union {   /* FCCU NCF Configuration Register 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFC127:1;         /* NCF 127 configuration */
-         vuint32_t  NCFC126:1;         /* NCF 126 configuration */
-         vuint32_t  NCFC125:1;         /* NCF 125 configuration */
-         vuint32_t  NCFC124:1;         /* NCF 124 configuration */
-         vuint32_t  NCFC123:1;         /* NCF 123 configuration */
-         vuint32_t  NCFC122:1;         /* NCF 122 configuration */
-         vuint32_t  NCFC121:1;         /* NCF 121 configuration */
-         vuint32_t  NCFC120:1;         /* NCF 120 configuration */
-         vuint32_t  NCFC119:1;         /* NCF 119 configuration */
-         vuint32_t  NCFC118:1;         /* NCF 118 configuration */
-         vuint32_t  NCFC117:1;         /* NCF 117 configuration */
-         vuint32_t  NCFC116:1;         /* NCF 116 configuration */
-         vuint32_t  NCFC115:1;         /* NCF 115 configuration */
-         vuint32_t  NCFC114:1;         /* NCF 114 configuration */
-         vuint32_t  NCFC113:1;         /* NCF 113 configuration */
-         vuint32_t  NCFC112:1;         /* NCF 112 configuration */
-         vuint32_t  NCFC111:1;         /* NCF 111 configuration */
-         vuint32_t  NCFC110:1;         /* NCF 110 configuration */
-         vuint32_t  NCFC109:1;         /* NCF 109 configuration */
-         vuint32_t  NCFC108:1;         /* NCF 108 configuration */
-         vuint32_t  NCFC107:1;         /* NCF 107 configuration */
-         vuint32_t  NCFC106:1;         /* NCF 106 configuration */
-         vuint32_t  NCFC105:1;         /* NCF 105 configuration */
-         vuint32_t  NCFC104:1;         /* NCF 104 configuration */
-         vuint32_t  NCFC103:1;         /* NCF 103 configuration */
-         vuint32_t  NCFC102:1;         /* NCF 102 configuration */
-         vuint32_t  NCFC101:1;         /* NCF 101 configuration */
-         vuint32_t  NCFC100:1;         /* NCF 100 configuration */
-         vuint32_t  NCFC99:1;          /* NCF 99 configuration */
-         vuint32_t  NCFC98:1;          /* NCF 98 configuration */
-         vuint32_t  NCFC97:1;          /* NCF 97 configuration */
-         vuint32_t  NCFC96:1;          /* NCF 96 configuration */
-      } B;
-   } FCCU_NCF_CFG3_32B_tag;
-
-   typedef union {   /* FCCU CFS Configuration Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFSC15:2;          /* CF 15 state configuration */
-         vuint32_t  CFSC14:2;          /* CF 14 state configuration */
-         vuint32_t  CFSC13:2;          /* CF 13 state configuration */
-         vuint32_t  CFSC12:2;          /* CF 12 state configuration */
-         vuint32_t  CFSC11:2;          /* CF 11 state configuration */
-         vuint32_t  CFSC10:2;          /* CF 10 state configuration */
-         vuint32_t  CFSC9:2;           /* CF 9 state configuration */
-         vuint32_t  CFSC8:2;           /* CF 8 state configuration */
-         vuint32_t  CFSC7:2;           /* CF 7 state configuration */
-         vuint32_t  CFSC6:2;           /* CF 6 state configuration */
-         vuint32_t  CFSC5:2;           /* CF 5 state configuration */
-         vuint32_t  CFSC4:2;           /* CF 4 state configuration */
-         vuint32_t  CFSC3:2;           /* CF 3 state configuration */
-         vuint32_t  CFSC2:2;           /* CF 2 state configuration */
-         vuint32_t  CFSC1:2;           /* CF 1 state configuration */
-         vuint32_t  CFSC0:2;           /* CF 0 state configuration */
-      } B;
-   } FCCU_CFS_CFG0_32B_tag;
-
-   typedef union {   /* FCCU CFS Configuration Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFSC31:2;          /* CF 31 state configuration */
-         vuint32_t  CFSC30:2;          /* CF 30 state configuration */
-         vuint32_t  CFSC29:2;          /* CF 29 state configuration */
-         vuint32_t  CFSC28:2;          /* CF 28 state configuration */
-         vuint32_t  CFSC27:2;          /* CF 27 state configuration */
-         vuint32_t  CFSC26:2;          /* CF 26 state configuration */
-         vuint32_t  CFSC25:2;          /* CF 25 state configuration */
-         vuint32_t  CFSC24:2;          /* CF 24 state configuration */
-         vuint32_t  CFSC23:2;          /* CF 23 state configuration */
-         vuint32_t  CFSC22:2;          /* CF 22 state configuration */
-         vuint32_t  CFSC21:2;          /* CF 21 state configuration */
-         vuint32_t  CFSC20:2;          /* CF 20 state configuration */
-         vuint32_t  CFSC19:2;          /* CF 19 state configuration */
-         vuint32_t  CFSC18:2;          /* CF 18 state configuration */
-         vuint32_t  CFSC17:2;          /* CF 17 state configuration */
-         vuint32_t  CFSC16:2;          /* CF 16 state configuration */
-      } B;
-   } FCCU_CFS_CFG1_32B_tag;
-
-   typedef union {   /* FCCU CFS Configuration Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFSC47:2;          /* CF 47 state configuration */
-         vuint32_t  CFSC46:2;          /* CF 46 state configuration */
-         vuint32_t  CFSC45:2;          /* CF 45 state configuration */
-         vuint32_t  CFSC44:2;          /* CF 44 state configuration */
-         vuint32_t  CFSC43:2;          /* CF 43 state configuration */
-         vuint32_t  CFSC42:2;          /* CF 42 state configuration */
-         vuint32_t  CFSC41:2;          /* CF 41 state configuration */
-         vuint32_t  CFSC40:2;          /* CF 40 state configuration */
-         vuint32_t  CFSC39:2;          /* CF 39 state configuration */
-         vuint32_t  CFSC38:2;          /* CF 38 state configuration */
-         vuint32_t  CFSC37:2;          /* CF 37 state configuration */
-         vuint32_t  CFSC36:2;          /* CF 36 state configuration */
-         vuint32_t  CFSC35:2;          /* CF 35 state configuration */
-         vuint32_t  CFSC34:2;          /* CF 34 state configuration */
-         vuint32_t  CFSC33:2;          /* CF 33 state configuration */
-         vuint32_t  CFSC32:2;          /* CF 32 state configuration */
-      } B;
-   } FCCU_CFS_CFG2_32B_tag;
-
-   typedef union {   /* FCCU CFS Configuration Register 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFSC63:2;          /* CF 63 state configuration */
-         vuint32_t  CFSC62:2;          /* CF 62 state configuration */
-         vuint32_t  CFSC61:2;          /* CF 61 state configuration */
-         vuint32_t  CFSC60:2;          /* CF 60 state configuration */
-         vuint32_t  CFSC59:2;          /* CF 59 state configuration */
-         vuint32_t  CFSC58:2;          /* CF 58 state configuration */
-         vuint32_t  CFSC57:2;          /* CF 57 state configuration */
-         vuint32_t  CFSC56:2;          /* CF 56 state configuration */
-         vuint32_t  CFSC55:2;          /* CF 55 state configuration */
-         vuint32_t  CFSC54:2;          /* CF 54 state configuration */
-         vuint32_t  CFSC53:2;          /* CF 53 state configuration */
-         vuint32_t  CFSC52:2;          /* CF 52 state configuration */
-         vuint32_t  CFSC51:2;          /* CF 51 state configuration */
-         vuint32_t  CFSC50:2;          /* CF 50 state configuration */
-         vuint32_t  CFSC49:2;          /* CF 49 state configuration */
-         vuint32_t  CFSC48:2;          /* CF 48 state configuration */
-      } B;
-   } FCCU_CFS_CFG3_32B_tag;
-
-   typedef union {   /* FCCU CFS Configuration Register 4 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFSC79:2;          /* CF 79 state configuration */
-         vuint32_t  CFSC78:2;          /* CF 78 state configuration */
-         vuint32_t  CFSC77:2;          /* CF 77 state configuration */
-         vuint32_t  CFSC76:2;          /* CF 76 state configuration */
-         vuint32_t  CFSC75:2;          /* CF 75 state configuration */
-         vuint32_t  CFSC74:2;          /* CF 74 state configuration */
-         vuint32_t  CFSC73:2;          /* CF 73 state configuration */
-         vuint32_t  CFSC72:2;          /* CF 72 state configuration */
-         vuint32_t  CFSC71:2;          /* CF 71 state configuration */
-         vuint32_t  CFSC70:2;          /* CF 70 state configuration */
-         vuint32_t  CFSC69:2;          /* CF 69 state configuration */
-         vuint32_t  CFSC68:2;          /* CF 68 state configuration */
-         vuint32_t  CFSC67:2;          /* CF 67 state configuration */
-         vuint32_t  CFSC66:2;          /* CF 66 state configuration */
-         vuint32_t  CFSC65:2;          /* CF 65 state configuration */
-         vuint32_t  CFSC64:2;          /* CF 64 state configuration */
-      } B;
-   } FCCU_CFS_CFG4_32B_tag;
-
-   typedef union {   /* FCCU CFS Configuration Register 5 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFSC95:2;          /* CF 95 state configuration */
-         vuint32_t  CFSC94:2;          /* CF 94 state configuration */
-         vuint32_t  CFSC93:2;          /* CF 93 state configuration */
-         vuint32_t  CFSC92:2;          /* CF 92 state configuration */
-         vuint32_t  CFSC91:2;          /* CF 91 state configuration */
-         vuint32_t  CFSC90:2;          /* CF 90 state configuration */
-         vuint32_t  CFSC89:2;          /* CF 89 state configuration */
-         vuint32_t  CFSC88:2;          /* CF 88 state configuration */
-         vuint32_t  CFSC87:2;          /* CF 87 state configuration */
-         vuint32_t  CFSC86:2;          /* CF 86 state configuration */
-         vuint32_t  CFSC85:2;          /* CF 85 state configuration */
-         vuint32_t  CFSC84:2;          /* CF 84 state configuration */
-         vuint32_t  CFSC83:2;          /* CF 83 state configuration */
-         vuint32_t  CFSC82:2;          /* CF 82 state configuration */
-         vuint32_t  CFSC81:2;          /* CF 81 state configuration */
-         vuint32_t  CFSC80:2;          /* CF 80 state configuration */
-      } B;
-   } FCCU_CFS_CFG5_32B_tag;
-
-   typedef union {   /* FCCU CFS Configuration Register 6 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFSC111:2;         /* CF 111 state configuration */
-         vuint32_t  CFSC110:2;         /* CF 110 state configuration */
-         vuint32_t  CFSC109:2;         /* CF 109 state configuration */
-         vuint32_t  CFSC108:2;         /* CF 108 state configuration */
-         vuint32_t  CFSC107:2;         /* CF 107 state configuration */
-         vuint32_t  CFSC106:2;         /* CF 106 state configuration */
-         vuint32_t  CFSC105:2;         /* CF 105 state configuration */
-         vuint32_t  CFSC104:2;         /* CF 104 state configuration */
-         vuint32_t  CFSC103:2;         /* CF 103 state configuration */
-         vuint32_t  CFSC102:2;         /* CF 102 state configuration */
-         vuint32_t  CFSC101:2;         /* CF 101 state configuration */
-         vuint32_t  CFSC100:2;         /* CF 100 state configuration */
-         vuint32_t  CFSC99:2;          /* CF 99 state configuration */
-         vuint32_t  CFSC98:2;          /* CF 98 state configuration */
-         vuint32_t  CFSC97:2;          /* CF 97 state configuration */
-         vuint32_t  CFSC96:2;          /* CF 96 state configuration */
-      } B;
-   } FCCU_CFS_CFG6_32B_tag;
-
-   typedef union {   /* FCCU CFS Configuration Register 7 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFSC127:2;         /* CF 127 state configuration */
-         vuint32_t  CFSC126:2;         /* CF 126 state configuration */
-         vuint32_t  CFSC125:2;         /* CF 125 state configuration */
-         vuint32_t  CFSC124:2;         /* CF 124 state configuration */
-         vuint32_t  CFSC123:2;         /* CF 123 state configuration */
-         vuint32_t  CFSC122:2;         /* CF 122 state configuration */
-         vuint32_t  CFSC121:2;         /* CF 121 state configuration */
-         vuint32_t  CFSC120:2;         /* CF 120 state configuration */
-         vuint32_t  CFSC119:2;         /* CF 119 state configuration */
-         vuint32_t  CFSC118:2;         /* CF 118 state configuration */
-         vuint32_t  CFSC117:2;         /* CF 117 state configuration */
-         vuint32_t  CFSC116:2;         /* CF 116 state configuration */
-         vuint32_t  CFSC115:2;         /* CF 115 state configuration */
-         vuint32_t  CFSC114:2;         /* CF 114 state configuration */
-         vuint32_t  CFSC113:2;         /* CF 113 state configuration */
-         vuint32_t  CFSC112:2;         /* CF 112 state configuration */
-      } B;
-   } FCCU_CFS_CFG7_32B_tag;
-
-   typedef union {   /* FCCU NCFS Configuration Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFSC15:2;         /* NCF 15 state configuration */
-         vuint32_t  NCFSC14:2;         /* NCF 14 state configuration */
-         vuint32_t  NCFSC13:2;         /* NCF 13 state configuration */
-         vuint32_t  NCFSC12:2;         /* NCF 12 state configuration */
-         vuint32_t  NCFSC11:2;         /* NCF 11 state configuration */
-         vuint32_t  NCFSC10:2;         /* NCF 10 state configuration */
-         vuint32_t  NCFSC9:2;          /* NCF 9 state configuration */
-         vuint32_t  NCFSC8:2;          /* NCF 8 state configuration */
-         vuint32_t  NCFSC7:2;          /* NCF 7 state configuration */
-         vuint32_t  NCFSC6:2;          /* NCF 6 state configuration */
-         vuint32_t  NCFSC5:2;          /* NCF 5 state configuration */
-         vuint32_t  NCFSC4:2;          /* NCF 4 state configuration */
-         vuint32_t  NCFSC3:2;          /* NCF 3 state configuration */
-         vuint32_t  NCFSC2:2;          /* NCF 2 state configuration */
-         vuint32_t  NCFSC1:2;          /* NCF 1 state configuration */
-         vuint32_t  NCFSC0:2;          /* NCF 0 state configuration */
-      } B;
-   } FCCU_NCFS_CFG0_32B_tag;
-
-   typedef union {   /* FCCU NCFS Configuration Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFSC31:2;         /* NCF 31 state configuration */
-         vuint32_t  NCFSC30:2;         /* NCF 30 state configuration */
-         vuint32_t  NCFSC29:2;         /* NCF 29 state configuration */
-         vuint32_t  NCFSC28:2;         /* NCF 28 state configuration */
-         vuint32_t  NCFSC27:2;         /* NCF 27 state configuration */
-         vuint32_t  NCFSC26:2;         /* NCF 26 state configuration */
-         vuint32_t  NCFSC25:2;         /* NCF 25 state configuration */
-         vuint32_t  NCFSC24:2;         /* NCF 24 state configuration */
-         vuint32_t  NCFSC23:2;         /* NCF 23 state configuration */
-         vuint32_t  NCFSC22:2;         /* NCF 22 state configuration */
-         vuint32_t  NCFSC21:2;         /* NCF 21 state configuration */
-         vuint32_t  NCFSC20:2;         /* NCF 20 state configuration */
-         vuint32_t  NCFSC19:2;         /* NCF 19 state configuration */
-         vuint32_t  NCFSC18:2;         /* NCF 18 state configuration */
-         vuint32_t  NCFSC17:2;         /* NCF 17 state configuration */
-         vuint32_t  NCFSC16:2;         /* NCF 16 state configuration */
-      } B;
-   } FCCU_NCFS_CFG1_32B_tag;
-
-   typedef union {   /* FCCU NCFS Configuration Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFSC47:2;         /* NCF 47 state configuration */
-         vuint32_t  NCFSC46:2;         /* NCF 46 state configuration */
-         vuint32_t  NCFSC45:2;         /* NCF 45 state configuration */
-         vuint32_t  NCFSC44:2;         /* NCF 44 state configuration */
-         vuint32_t  NCFSC43:2;         /* NCF 43 state configuration */
-         vuint32_t  NCFSC42:2;         /* NCF 42 state configuration */
-         vuint32_t  NCFSC41:2;         /* NCF 41 state configuration */
-         vuint32_t  NCFSC40:2;         /* NCF 40 state configuration */
-         vuint32_t  NCFSC39:2;         /* NCF 39 state configuration */
-         vuint32_t  NCFSC38:2;         /* NCF 38 state configuration */
-         vuint32_t  NCFSC37:2;         /* NCF 37 state configuration */
-         vuint32_t  NCFSC36:2;         /* NCF 36 state configuration */
-         vuint32_t  NCFSC35:2;         /* NCF 35 state configuration */
-         vuint32_t  NCFSC34:2;         /* NCF 34 state configuration */
-         vuint32_t  NCFSC33:2;         /* NCF 33 state configuration */
-         vuint32_t  NCFSC32:2;         /* NCF 32 state configuration */
-      } B;
-   } FCCU_NCFS_CFG2_32B_tag;
-
-   typedef union {   /* FCCU NCFS Configuration Register 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFSC63:2;         /* NCF 63 state configuration */
-         vuint32_t  NCFSC62:2;         /* NCF 62 state configuration */
-         vuint32_t  NCFSC61:2;         /* NCF 61 state configuration */
-         vuint32_t  NCFSC60:2;         /* NCF 60 state configuration */
-         vuint32_t  NCFSC59:2;         /* NCF 59 state configuration */
-         vuint32_t  NCFSC58:2;         /* NCF 58 state configuration */
-         vuint32_t  NCFSC57:2;         /* NCF 57 state configuration */
-         vuint32_t  NCFSC56:2;         /* NCF 56 state configuration */
-         vuint32_t  NCFSC55:2;         /* NCF 55 state configuration */
-         vuint32_t  NCFSC54:2;         /* NCF 54 state configuration */
-         vuint32_t  NCFSC53:2;         /* NCF 53 state configuration */
-         vuint32_t  NCFSC52:2;         /* NCF 52 state configuration */
-         vuint32_t  NCFSC51:2;         /* NCF 51 state configuration */
-         vuint32_t  NCFSC50:2;         /* NCF 50 state configuration */
-         vuint32_t  NCFSC49:2;         /* NCF 49 state configuration */
-         vuint32_t  NCFSC48:2;         /* NCF 48 state configuration */
-      } B;
-   } FCCU_NCFS_CFG3_32B_tag;
-
-   typedef union {   /* FCCU NCFS Configuration Register 4 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFSC79:2;         /* NCF 79 state configuration */
-         vuint32_t  NCFSC78:2;         /* NCF 78 state configuration */
-         vuint32_t  NCFSC77:2;         /* NCF 77 state configuration */
-         vuint32_t  NCFSC76:2;         /* NCF 76 state configuration */
-         vuint32_t  NCFSC75:2;         /* NCF 75 state configuration */
-         vuint32_t  NCFSC74:2;         /* NCF 74 state configuration */
-         vuint32_t  NCFSC73:2;         /* NCF 73 state configuration */
-         vuint32_t  NCFSC72:2;         /* NCF 72 state configuration */
-         vuint32_t  NCFSC71:2;         /* NCF 71 state configuration */
-         vuint32_t  NCFSC70:2;         /* NCF 70 state configuration */
-         vuint32_t  NCFSC69:2;         /* NCF 69 state configuration */
-         vuint32_t  NCFSC68:2;         /* NCF 68 state configuration */
-         vuint32_t  NCFSC67:2;         /* NCF 67 state configuration */
-         vuint32_t  NCFSC66:2;         /* NCF 66 state configuration */
-         vuint32_t  NCFSC65:2;         /* NCF 65 state configuration */
-         vuint32_t  NCFSC64:2;         /* NCF 64 state configuration */
-      } B;
-   } FCCU_NCFS_CFG4_32B_tag;
-
-   typedef union {   /* FCCU NCFS Configuration Register 5 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFSC95:2;         /* NCF 95 state configuration */
-         vuint32_t  NCFSC94:2;         /* NCF 94 state configuration */
-         vuint32_t  NCFSC93:2;         /* NCF 93 state configuration */
-         vuint32_t  NCFSC92:2;         /* NCF 92 state configuration */
-         vuint32_t  NCFSC91:2;         /* NCF 91 state configuration */
-         vuint32_t  NCFSC90:2;         /* NCF 90 state configuration */
-         vuint32_t  NCFSC89:2;         /* NCF 89 state configuration */
-         vuint32_t  NCFSC88:2;         /* NCF 88 state configuration */
-         vuint32_t  NCFSC87:2;         /* NCF 87 state configuration */
-         vuint32_t  NCFSC86:2;         /* NCF 86 state configuration */
-         vuint32_t  NCFSC85:2;         /* NCF 85 state configuration */
-         vuint32_t  NCFSC84:2;         /* NCF 84 state configuration */
-         vuint32_t  NCFSC83:2;         /* NCF 83 state configuration */
-         vuint32_t  NCFSC82:2;         /* NCF 82 state configuration */
-         vuint32_t  NCFSC81:2;         /* NCF 81 state configuration */
-         vuint32_t  NCFSC80:2;         /* NCF 80 state configuration */
-      } B;
-   } FCCU_NCFS_CFG5_32B_tag;
-
-   typedef union {   /* FCCU NCFS Configuration Register 6 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFSC111:2;        /* NCF 111 state configuration */
-         vuint32_t  NCFSC110:2;        /* NCF 110 state configuration */
-         vuint32_t  NCFSC109:2;        /* NCF 109 state configuration */
-         vuint32_t  NCFSC108:2;        /* NCF 108 state configuration */
-         vuint32_t  NCFSC107:2;        /* NCF 107 state configuration */
-         vuint32_t  NCFSC106:2;        /* NCF 106 state configuration */
-         vuint32_t  NCFSC105:2;        /* NCF 105 state configuration */
-         vuint32_t  NCFSC104:2;        /* NCF 104 state configuration */
-         vuint32_t  NCFSC103:2;        /* NCF 103 state configuration */
-         vuint32_t  NCFSC102:2;        /* NCF 102 state configuration */
-         vuint32_t  NCFSC101:2;        /* NCF 101 state configuration */
-         vuint32_t  NCFSC100:2;        /* NCF 100 state configuration */
-         vuint32_t  NCFSC99:2;         /* NCF 99 state configuration */
-         vuint32_t  NCFSC98:2;         /* NCF 98 state configuration */
-         vuint32_t  NCFSC97:2;         /* NCF 97 state configuration */
-         vuint32_t  NCFSC96:2;         /* NCF 96 state configuration */
-      } B;
-   } FCCU_NCFS_CFG6_32B_tag;
-
-   typedef union {   /* FCCU NCFS Configuration Register 7 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFSC127:2;        /* NCF 127 state configuration */
-         vuint32_t  NCFSC126:2;        /* NCF 126 state configuration */
-         vuint32_t  NCFSC125:2;        /* NCF 125 state configuration */
-         vuint32_t  NCFSC124:2;        /* NCF 124 state configuration */
-         vuint32_t  NCFSC123:2;        /* NCF 123 state configuration */
-         vuint32_t  NCFSC122:2;        /* NCF 122 state configuration */
-         vuint32_t  NCFSC121:2;        /* NCF 121 state configuration */
-         vuint32_t  NCFSC120:2;        /* NCF 120 state configuration */
-         vuint32_t  NCFSC119:2;        /* NCF 119 state configuration */
-         vuint32_t  NCFSC118:2;        /* NCF 118 state configuration */
-         vuint32_t  NCFSC117:2;        /* NCF 117 state configuration */
-         vuint32_t  NCFSC116:2;        /* NCF 116 state configuration */
-         vuint32_t  NCFSC115:2;        /* NCF 115 state configuration */
-         vuint32_t  NCFSC114:2;        /* NCF 114 state configuration */
-         vuint32_t  NCFSC113:2;        /* NCF 113 state configuration */
-         vuint32_t  NCFSC112:2;        /* NCF 112 state configuration */
-      } B;
-   } FCCU_NCFS_CFG7_32B_tag;
-
-   typedef union {   /* FCCU CF Status Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFS31:1;           /* CF 31 status */
-         vuint32_t  CFS30:1;           /* CF 30 status */
-         vuint32_t  CFS29:1;           /* CF 29 status */
-         vuint32_t  CFS28:1;           /* CF 28 status */
-         vuint32_t  CFS27:1;           /* CF 27 status */
-         vuint32_t  CFS26:1;           /* CF 26 status */
-         vuint32_t  CFS25:1;           /* CF 25 status */
-         vuint32_t  CFS24:1;           /* CF 24 status */
-         vuint32_t  CFS23:1;           /* CF 23 status */
-         vuint32_t  CFS22:1;           /* CF 22 status */
-         vuint32_t  CFS21:1;           /* CF 21 status */
-         vuint32_t  CFS20:1;           /* CF 20 status */
-         vuint32_t  CFS19:1;           /* CF 19 status */
-         vuint32_t  CFS18:1;           /* CF 18 status */
-         vuint32_t  CFS17:1;           /* CF 17 status */
-         vuint32_t  CFS16:1;           /* CF 16 status */
-         vuint32_t  CFS15:1;           /* CF 15 status */
-         vuint32_t  CFS14:1;           /* CF 14 status */
-         vuint32_t  CFS13:1;           /* CF 13 status */
-         vuint32_t  CFS12:1;           /* CF 12 status */
-         vuint32_t  CFS11:1;           /* CF 11 status */
-         vuint32_t  CFS10:1;           /* CF 10 status */
-         vuint32_t  CFS9:1;            /* CF 9 status */
-         vuint32_t  CFS8:1;            /* CF 8 status */
-         vuint32_t  CFS7:1;            /* CF 7 status */
-         vuint32_t  CFS6:1;            /* CF 6 status */
-         vuint32_t  CFS5:1;            /* CF 5 status */
-         vuint32_t  CFS4:1;            /* CF 4 status */
-         vuint32_t  CFS3:1;            /* CF 3 status */
-         vuint32_t  CFS2:1;            /* CF 2 status */
-         vuint32_t  CFS1:1;            /* CF 1 status */
-         vuint32_t  CFS0:1;            /* CF 0 status */
-      } B;
-   } FCCU_CFS0_32B_tag;
-
-   typedef union {   /* FCCU CF Status Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFS63:1;           /* CF 63 status */
-         vuint32_t  CFS62:1;           /* CF 62 status */
-         vuint32_t  CFS61:1;           /* CF 61 status */
-         vuint32_t  CFS60:1;           /* CF 60 status */
-         vuint32_t  CFS59:1;           /* CF 59 status */
-         vuint32_t  CFS58:1;           /* CF 58 status */
-         vuint32_t  CFS57:1;           /* CF 57 status */
-         vuint32_t  CFS56:1;           /* CF 56 status */
-         vuint32_t  CFS55:1;           /* CF 55 status */
-         vuint32_t  CFS54:1;           /* CF 54 status */
-         vuint32_t  CFS53:1;           /* CF 53 status */
-         vuint32_t  CFS52:1;           /* CF 52 status */
-         vuint32_t  CFS51:1;           /* CF 51 status */
-         vuint32_t  CFS50:1;           /* CF 50 status */
-         vuint32_t  CFS49:1;           /* CF 49 status */
-         vuint32_t  CFS48:1;           /* CF 48 status */
-         vuint32_t  CFS47:1;           /* CF 47 status */
-         vuint32_t  CFS46:1;           /* CF 46 status */
-         vuint32_t  CFS45:1;           /* CF 45 status */
-         vuint32_t  CFS44:1;           /* CF 44 status */
-         vuint32_t  CFS43:1;           /* CF 43 status */
-         vuint32_t  CFS42:1;           /* CF 42 status */
-         vuint32_t  CFS41:1;           /* CF 41 status */
-         vuint32_t  CFS40:1;           /* CF 40 status */
-         vuint32_t  CFS39:1;           /* CF 39 status */
-         vuint32_t  CFS38:1;           /* CF 38 status */
-         vuint32_t  CFS37:1;           /* CF 37 status */
-         vuint32_t  CFS36:1;           /* CF 36 status */
-         vuint32_t  CFS35:1;           /* CF 35 status */
-         vuint32_t  CFS34:1;           /* CF 34 status */
-         vuint32_t  CFS33:1;           /* CF 33 status */
-         vuint32_t  CFS32:1;           /* CF 32 status */
-      } B;
-   } FCCU_CFS1_32B_tag;
-
-   typedef union {   /* FCCU CF Status Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFS95:1;           /* CF 95 status */
-         vuint32_t  CFS94:1;           /* CF 94 status */
-         vuint32_t  CFS93:1;           /* CF 93 status */
-         vuint32_t  CFS92:1;           /* CF 92 status */
-         vuint32_t  CFS91:1;           /* CF 91 status */
-         vuint32_t  CFS90:1;           /* CF 90 status */
-         vuint32_t  CFS89:1;           /* CF 89 status */
-         vuint32_t  CFS88:1;           /* CF 88 status */
-         vuint32_t  CFS87:1;           /* CF 87 status */
-         vuint32_t  CFS86:1;           /* CF 86 status */
-         vuint32_t  CFS85:1;           /* CF 85 status */
-         vuint32_t  CFS84:1;           /* CF 84 status */
-         vuint32_t  CFS83:1;           /* CF 83 status */
-         vuint32_t  CFS82:1;           /* CF 82 status */
-         vuint32_t  CFS81:1;           /* CF 81 status */
-         vuint32_t  CFS80:1;           /* CF 80 status */
-         vuint32_t  CFS79:1;           /* CF 79 status */
-         vuint32_t  CFS78:1;           /* CF 78 status */
-         vuint32_t  CFS77:1;           /* CF 77 status */
-         vuint32_t  CFS76:1;           /* CF 76 status */
-         vuint32_t  CFS75:1;           /* CF 75 status */
-         vuint32_t  CFS74:1;           /* CF 74 status */
-         vuint32_t  CFS73:1;           /* CF 73 status */
-         vuint32_t  CFS72:1;           /* CF 72 status */
-         vuint32_t  CFS71:1;           /* CF 71 status */
-         vuint32_t  CFS70:1;           /* CF 70 status */
-         vuint32_t  CFS69:1;           /* CF 69 status */
-         vuint32_t  CFS68:1;           /* CF 68 status */
-         vuint32_t  CFS67:1;           /* CF 67 status */
-         vuint32_t  CFS66:1;           /* CF 66 status */
-         vuint32_t  CFS65:1;           /* CF 65 status */
-         vuint32_t  CFS64:1;           /* CF 64 status */
-      } B;
-   } FCCU_CFS2_32B_tag;
-
-   typedef union {   /* FCCU CF Status Register 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  CFS127:1;          /* CF 127 status */
-         vuint32_t  CFS126:1;          /* CF 126 status */
-         vuint32_t  CFS125:1;          /* CF 125 status */
-         vuint32_t  CFS124:1;          /* CF 124 status */
-         vuint32_t  CFS123:1;          /* CF 123 status */
-         vuint32_t  CFS122:1;          /* CF 122 status */
-         vuint32_t  CFS121:1;          /* CF 121 status */
-         vuint32_t  CFS120:1;          /* CF 120 status */
-         vuint32_t  CFS119:1;          /* CF 119 status */
-         vuint32_t  CFS118:1;          /* CF 118 status */
-         vuint32_t  CFS117:1;          /* CF 117 status */
-         vuint32_t  CFS116:1;          /* CF 116 status */
-         vuint32_t  CFS115:1;          /* CF 115 status */
-         vuint32_t  CFS114:1;          /* CF 114 status */
-         vuint32_t  CFS113:1;          /* CF 113 status */
-         vuint32_t  CFS112:1;          /* CF 112 status */
-         vuint32_t  CFS111:1;          /* CF 111 status */
-         vuint32_t  CFS110:1;          /* CF 110 status */
-         vuint32_t  CFS109:1;          /* CF 109 status */
-         vuint32_t  CFS108:1;          /* CF 108 status */
-         vuint32_t  CFS107:1;          /* CF 107 status */
-         vuint32_t  CFS106:1;          /* CF 106 status */
-         vuint32_t  CFS105:1;          /* CF 105 status */
-         vuint32_t  CFS104:1;          /* CF 104 status */
-         vuint32_t  CFS103:1;          /* CF 103 status */
-         vuint32_t  CFS102:1;          /* CF 102 status */
-         vuint32_t  CFS101:1;          /* CF 101 status */
-         vuint32_t  CFS100:1;          /* CF 100 status */
-         vuint32_t  CFS99:1;           /* CF 99 status */
-         vuint32_t  CFS98:1;           /* CF 98 status */
-         vuint32_t  CFS97:1;           /* CF 97 status */
-         vuint32_t  CFS96:1;           /* CF 96 status */
-      } B;
-   } FCCU_CFS3_32B_tag;
-
-   typedef union {   /* FCCU_CFK - FCCU CF Key Register */
-      vuint32_t R;
-   } FCCU_CFK_32B_tag;
-
-   typedef union {   /* FCCU NCF Status Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFS31:1;          /* NCF 31 status */
-         vuint32_t  NCFS30:1;          /* NCF 30 status */
-         vuint32_t  NCFS29:1;          /* NCF 29 status */
-         vuint32_t  NCFS28:1;          /* NCF 28 status */
-         vuint32_t  NCFS27:1;          /* NCF 27 status */
-         vuint32_t  NCFS26:1;          /* NCF 26 status */
-         vuint32_t  NCFS25:1;          /* NCF 25 status */
-         vuint32_t  NCFS24:1;          /* NCF 24 status */
-         vuint32_t  NCFS23:1;          /* NCF 23 status */
-         vuint32_t  NCFS22:1;          /* NCF 22 status */
-         vuint32_t  NCFS21:1;          /* NCF 21 status */
-         vuint32_t  NCFS20:1;          /* NCF 20 status */
-         vuint32_t  NCFS19:1;          /* NCF 19 status */
-         vuint32_t  NCFS18:1;          /* NCF 18 status */
-         vuint32_t  NCFS17:1;          /* NCF 17 status */
-         vuint32_t  NCFS16:1;          /* NCF 16 status */
-         vuint32_t  NCFS15:1;          /* NCF 15 status */
-         vuint32_t  NCFS14:1;          /* NCF 14 status */
-         vuint32_t  NCFS13:1;          /* NCF 13 status */
-         vuint32_t  NCFS12:1;          /* NCF 12 status */
-         vuint32_t  NCFS11:1;          /* NCF 11 status */
-         vuint32_t  NCFS10:1;          /* NCF 10 status */
-         vuint32_t  NCFS9:1;           /* NCF 9 status */
-         vuint32_t  NCFS8:1;           /* NCF 8 status */
-         vuint32_t  NCFS7:1;           /* NCF 7 status */
-         vuint32_t  NCFS6:1;           /* NCF 6 status */
-         vuint32_t  NCFS5:1;           /* NCF 5 status */
-         vuint32_t  NCFS4:1;           /* NCF 4 status */
-         vuint32_t  NCFS3:1;           /* NCF 3 status */
-         vuint32_t  NCFS2:1;           /* NCF 2 status */
-         vuint32_t  NCFS1:1;           /* NCF 1 status */
-         vuint32_t  NCFS0:1;           /* NCF 0 status */
-      } B;
-   } FCCU_NCFS0_32B_tag;
-
-   typedef union {   /* FCCU NCF Status Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFS63:1;          /* NCF 63 status */
-         vuint32_t  NCFS62:1;          /* NCF 62 status */
-         vuint32_t  NCFS61:1;          /* NCF 61 status */
-         vuint32_t  NCFS60:1;          /* NCF 60 status */
-         vuint32_t  NCFS59:1;          /* NCF 59 status */
-         vuint32_t  NCFS58:1;          /* NCF 58 status */
-         vuint32_t  NCFS57:1;          /* NCF 57 status */
-         vuint32_t  NCFS56:1;          /* NCF 56 status */
-         vuint32_t  NCFS55:1;          /* NCF 55 status */
-         vuint32_t  NCFS54:1;          /* NCF 54 status */
-         vuint32_t  NCFS53:1;          /* NCF 53 status */
-         vuint32_t  NCFS52:1;          /* NCF 52 status */
-         vuint32_t  NCFS51:1;          /* NCF 51 status */
-         vuint32_t  NCFS50:1;          /* NCF 50 status */
-         vuint32_t  NCFS49:1;          /* NCF 49 status */
-         vuint32_t  NCFS48:1;          /* NCF 48 status */
-         vuint32_t  NCFS47:1;          /* NCF 47 status */
-         vuint32_t  NCFS46:1;          /* NCF 46 status */
-         vuint32_t  NCFS45:1;          /* NCF 45 status */
-         vuint32_t  NCFS44:1;          /* NCF 44 status */
-         vuint32_t  NCFS43:1;          /* NCF 43 status */
-         vuint32_t  NCFS42:1;          /* NCF 42 status */
-         vuint32_t  NCFS41:1;          /* NCF 41 status */
-         vuint32_t  NCFS40:1;          /* NCF 40 status */
-         vuint32_t  NCFS39:1;          /* NCF 39 status */
-         vuint32_t  NCFS38:1;          /* NCF 38 status */
-         vuint32_t  NCFS37:1;          /* NCF 37 status */
-         vuint32_t  NCFS36:1;          /* NCF 36 status */
-         vuint32_t  NCFS35:1;          /* NCF 35 status */
-         vuint32_t  NCFS34:1;          /* NCF 34 status */
-         vuint32_t  NCFS33:1;          /* NCF 33 status */
-         vuint32_t  NCFS32:1;          /* NCF 32 status */
-      } B;
-   } FCCU_NCFS1_32B_tag;
-
-   typedef union {   /* FCCU NCF Status Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFS95:1;          /* NCF 95 status */
-         vuint32_t  NCFS94:1;          /* NCF 94 status */
-         vuint32_t  NCFS93:1;          /* NCF 93 status */
-         vuint32_t  NCFS92:1;          /* NCF 92 status */
-         vuint32_t  NCFS91:1;          /* NCF 91 status */
-         vuint32_t  NCFS90:1;          /* NCF 90 status */
-         vuint32_t  NCFS89:1;          /* NCF 89 status */
-         vuint32_t  NCFS88:1;          /* NCF 88 status */
-         vuint32_t  NCFS87:1;          /* NCF 87 status */
-         vuint32_t  NCFS86:1;          /* NCF 86 status */
-         vuint32_t  NCFS85:1;          /* NCF 85 status */
-         vuint32_t  NCFS84:1;          /* NCF 84 status */
-         vuint32_t  NCFS83:1;          /* NCF 83 status */
-         vuint32_t  NCFS82:1;          /* NCF 82 status */
-         vuint32_t  NCFS81:1;          /* NCF 81 status */
-         vuint32_t  NCFS80:1;          /* NCF 80 status */
-         vuint32_t  NCFS79:1;          /* NCF 79 status */
-         vuint32_t  NCFS78:1;          /* NCF 78 status */
-         vuint32_t  NCFS77:1;          /* NCF 77 status */
-         vuint32_t  NCFS76:1;          /* NCF 76 status */
-         vuint32_t  NCFS75:1;          /* NCF 75 status */
-         vuint32_t  NCFS74:1;          /* NCF 74 status */
-         vuint32_t  NCFS73:1;          /* NCF 73 status */
-         vuint32_t  NCFS72:1;          /* NCF 72 status */
-         vuint32_t  NCFS71:1;          /* NCF 71 status */
-         vuint32_t  NCFS70:1;          /* NCF 70 status */
-         vuint32_t  NCFS69:1;          /* NCF 69 status */
-         vuint32_t  NCFS68:1;          /* NCF 68 status */
-         vuint32_t  NCFS67:1;          /* NCF 67 status */
-         vuint32_t  NCFS66:1;          /* NCF 66 status */
-         vuint32_t  NCFS65:1;          /* NCF 65 status */
-         vuint32_t  NCFS64:1;          /* NCF 64 status */
-      } B;
-   } FCCU_NCFS2_32B_tag;
-
-   typedef union {   /* FCCU NCF Status Register 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFS127:1;         /* NCF 127 status */
-         vuint32_t  NCFS126:1;         /* NCF 126 status */
-         vuint32_t  NCFS125:1;         /* NCF 125 status */
-         vuint32_t  NCFS124:1;         /* NCF 124 status */
-         vuint32_t  NCFS123:1;         /* NCF 123 status */
-         vuint32_t  NCFS122:1;         /* NCF 122 status */
-         vuint32_t  NCFS121:1;         /* NCF 121 status */
-         vuint32_t  NCFS120:1;         /* NCF 120 status */
-         vuint32_t  NCFS119:1;         /* NCF 119 status */
-         vuint32_t  NCFS118:1;         /* NCF 118 status */
-         vuint32_t  NCFS117:1;         /* NCF 117 status */
-         vuint32_t  NCFS116:1;         /* NCF 116 status */
-         vuint32_t  NCFS115:1;         /* NCF 115 status */
-         vuint32_t  NCFS114:1;         /* NCF 114 status */
-         vuint32_t  NCFS113:1;         /* NCF 113 status */
-         vuint32_t  NCFS112:1;         /* NCF 112 status */
-         vuint32_t  NCFS111:1;         /* NCF 111 status */
-         vuint32_t  NCFS110:1;         /* NCF 110 status */
-         vuint32_t  NCFS109:1;         /* NCF 109 status */
-         vuint32_t  NCFS108:1;         /* NCF 108 status */
-         vuint32_t  NCFS107:1;         /* NCF 107 status */
-         vuint32_t  NCFS106:1;         /* NCF 106 status */
-         vuint32_t  NCFS105:1;         /* NCF 105 status */
-         vuint32_t  NCFS104:1;         /* NCF 104 status */
-         vuint32_t  NCFS103:1;         /* NCF 103 status */
-         vuint32_t  NCFS102:1;         /* NCF 102 status */
-         vuint32_t  NCFS101:1;         /* NCF 101 status */
-         vuint32_t  NCFS100:1;         /* NCF 100 status */
-         vuint32_t  NCFS99:1;          /* NCF 99 status */
-         vuint32_t  NCFS98:1;          /* NCF 98 status */
-         vuint32_t  NCFS97:1;          /* NCF 97 status */
-         vuint32_t  NCFS96:1;          /* NCF 96 status */
-      } B;
-   } FCCU_NCFS3_32B_tag;
-
-   typedef union {   /* FCCU_NCFK - FCCU NCF Key Register */
-      vuint32_t R;
-   } FCCU_NCFK_32B_tag;
-
-   typedef union {   /* FCCU NCF Enable Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFE31:1;          /* NCF 31 enable */
-         vuint32_t  NCFE30:1;          /* NCF 30 enable */
-         vuint32_t  NCFE29:1;          /* NCF 29 enable */
-         vuint32_t  NCFE28:1;          /* NCF 28 enable */
-         vuint32_t  NCFE27:1;          /* NCF 27 enable */
-         vuint32_t  NCFE26:1;          /* NCF 26 enable */
-         vuint32_t  NCFE25:1;          /* NCF 25 enable */
-         vuint32_t  NCFE24:1;          /* NCF 24 enable */
-         vuint32_t  NCFE23:1;          /* NCF 23 enable */
-         vuint32_t  NCFE22:1;          /* NCF 22 enable */
-         vuint32_t  NCFE21:1;          /* NCF 21 enable */
-         vuint32_t  NCFE20:1;          /* NCF 20 enable */
-         vuint32_t  NCFE19:1;          /* NCF 19 enable */
-         vuint32_t  NCFE18:1;          /* NCF 18 enable */
-         vuint32_t  NCFE17:1;          /* NCF 17 enable */
-         vuint32_t  NCFE16:1;          /* NCF 16 enable */
-         vuint32_t  NCFE15:1;          /* NCF 15 enable */
-         vuint32_t  NCFE14:1;          /* NCF 14 enable */
-         vuint32_t  NCFE13:1;          /* NCF 13 enable */
-         vuint32_t  NCFE12:1;          /* NCF 12 enable */
-         vuint32_t  NCFE11:1;          /* NCF 11 enable */
-         vuint32_t  NCFE10:1;          /* NCF 10 enable */
-         vuint32_t  NCFE9:1;           /* NCF 9 enable */
-         vuint32_t  NCFE8:1;           /* NCF 8 enable */
-         vuint32_t  NCFE7:1;           /* NCF 7 enable */
-         vuint32_t  NCFE6:1;           /* NCF 6 enable */
-         vuint32_t  NCFE5:1;           /* NCF 5 enable */
-         vuint32_t  NCFE4:1;           /* NCF 4 enable */
-         vuint32_t  NCFE3:1;           /* NCF 3 enable */
-         vuint32_t  NCFE2:1;           /* NCF 2 enable */
-         vuint32_t  NCFE1:1;           /* NCF 1 enable */
-         vuint32_t  NCFE0:1;           /* NCF 0 enable */
-      } B;
-   } FCCU_NCFE0_32B_tag;
-
-   typedef union {   /* FCCU NCF Enable Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFE63:1;          /* NCF 63 enable */
-         vuint32_t  NCFE62:1;          /* NCF 62 enable */
-         vuint32_t  NCFE61:1;          /* NCF 61 enable */
-         vuint32_t  NCFE60:1;          /* NCF 60 enable */
-         vuint32_t  NCFE59:1;          /* NCF 59 enable */
-         vuint32_t  NCFE58:1;          /* NCF 58 enable */
-         vuint32_t  NCFE57:1;          /* NCF 57 enable */
-         vuint32_t  NCFE56:1;          /* NCF 56 enable */
-         vuint32_t  NCFE55:1;          /* NCF 55 enable */
-         vuint32_t  NCFE54:1;          /* NCF 54 enable */
-         vuint32_t  NCFE53:1;          /* NCF 53 enable */
-         vuint32_t  NCFE52:1;          /* NCF 52 enable */
-         vuint32_t  NCFE51:1;          /* NCF 51 enable */
-         vuint32_t  NCFE50:1;          /* NCF 50 enable */
-         vuint32_t  NCFE49:1;          /* NCF 49 enable */
-         vuint32_t  NCFE48:1;          /* NCF 48 enable */
-         vuint32_t  NCFE47:1;          /* NCF 47 enable */
-         vuint32_t  NCFE46:1;          /* NCF 46 enable */
-         vuint32_t  NCFE45:1;          /* NCF 45 enable */
-         vuint32_t  NCFE44:1;          /* NCF 44 enable */
-         vuint32_t  NCFE43:1;          /* NCF 43 enable */
-         vuint32_t  NCFE42:1;          /* NCF 42 enable */
-         vuint32_t  NCFE41:1;          /* NCF 41 enable */
-         vuint32_t  NCFE40:1;          /* NCF 40 enable */
-         vuint32_t  NCFE39:1;          /* NCF 39 enable */
-         vuint32_t  NCFE38:1;          /* NCF 38 enable */
-         vuint32_t  NCFE37:1;          /* NCF 37 enable */
-         vuint32_t  NCFE36:1;          /* NCF 36 enable */
-         vuint32_t  NCFE35:1;          /* NCF 35 enable */
-         vuint32_t  NCFE34:1;          /* NCF 34 enable */
-         vuint32_t  NCFE33:1;          /* NCF 33 enable */
-         vuint32_t  NCFE32:1;          /* NCF 32 enable */
-      } B;
-   } FCCU_NCFE1_32B_tag;
-
-   typedef union {   /* FCCU NCF Enable Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFE95:1;          /* NCF 95 enable */
-         vuint32_t  NCFE94:1;          /* NCF 94 enable */
-         vuint32_t  NCFE93:1;          /* NCF 93 enable */
-         vuint32_t  NCFE92:1;          /* NCF 92 enable */
-         vuint32_t  NCFE91:1;          /* NCF 91 enable */
-         vuint32_t  NCFE90:1;          /* NCF 90 enable */
-         vuint32_t  NCFE89:1;          /* NCF 89 enable */
-         vuint32_t  NCFE88:1;          /* NCF 88 enable */
-         vuint32_t  NCFE87:1;          /* NCF 87 enable */
-         vuint32_t  NCFE86:1;          /* NCF 86 enable */
-         vuint32_t  NCFE85:1;          /* NCF 85 enable */
-         vuint32_t  NCFE84:1;          /* NCF 84 enable */
-         vuint32_t  NCFE83:1;          /* NCF 83 enable */
-         vuint32_t  NCFE82:1;          /* NCF 82 enable */
-         vuint32_t  NCFE81:1;          /* NCF 81 enable */
-         vuint32_t  NCFE80:1;          /* NCF 80 enable */
-         vuint32_t  NCFE79:1;          /* NCF 79 enable */
-         vuint32_t  NCFE78:1;          /* NCF 78 enable */
-         vuint32_t  NCFE77:1;          /* NCF 77 enable */
-         vuint32_t  NCFE76:1;          /* NCF 76 enable */
-         vuint32_t  NCFE75:1;          /* NCF 75 enable */
-         vuint32_t  NCFE74:1;          /* NCF 74 enable */
-         vuint32_t  NCFE73:1;          /* NCF 73 enable */
-         vuint32_t  NCFE72:1;          /* NCF 72 enable */
-         vuint32_t  NCFE71:1;          /* NCF 71 enable */
-         vuint32_t  NCFE70:1;          /* NCF 70 enable */
-         vuint32_t  NCFE69:1;          /* NCF 69 enable */
-         vuint32_t  NCFE68:1;          /* NCF 68 enable */
-         vuint32_t  NCFE67:1;          /* NCF 67 enable */
-         vuint32_t  NCFE66:1;          /* NCF 66 enable */
-         vuint32_t  NCFE65:1;          /* NCF 65 enable */
-         vuint32_t  NCFE64:1;          /* NCF 64 enable */
-      } B;
-   } FCCU_NCFE2_32B_tag;
-
-   typedef union {   /* FCCU NCF Enable Register 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFE127:1;         /* NCF 127 enable */
-         vuint32_t  NCFE126:1;         /* NCF 126 enable */
-         vuint32_t  NCFE125:1;         /* NCF 125 enable */
-         vuint32_t  NCFE124:1;         /* NCF 124 enable */
-         vuint32_t  NCFE123:1;         /* NCF 123 enable */
-         vuint32_t  NCFE122:1;         /* NCF 122 enable */
-         vuint32_t  NCFE121:1;         /* NCF 121 enable */
-         vuint32_t  NCFE120:1;         /* NCF 120 enable */
-         vuint32_t  NCFE119:1;         /* NCF 119 enable */
-         vuint32_t  NCFE118:1;         /* NCF 118 enable */
-         vuint32_t  NCFE117:1;         /* NCF 117 enable */
-         vuint32_t  NCFE116:1;         /* NCF 116 enable */
-         vuint32_t  NCFE115:1;         /* NCF 115 enable */
-         vuint32_t  NCFE114:1;         /* NCF 114 enable */
-         vuint32_t  NCFE113:1;         /* NCF 113 enable */
-         vuint32_t  NCFE112:1;         /* NCF 112 enable */
-         vuint32_t  NCFE111:1;         /* NCF 111 enable */
-         vuint32_t  NCFE110:1;         /* NCF 110 enable */
-         vuint32_t  NCFE109:1;         /* NCF 109 enable */
-         vuint32_t  NCFE108:1;         /* NCF 108 enable */
-         vuint32_t  NCFE107:1;         /* NCF 107 enable */
-         vuint32_t  NCFE106:1;         /* NCF 106 enable */
-         vuint32_t  NCFE105:1;         /* NCF 105 enable */
-         vuint32_t  NCFE104:1;         /* NCF 104 enable */
-         vuint32_t  NCFE103:1;         /* NCF 103 enable */
-         vuint32_t  NCFE102:1;         /* NCF 102 enable */
-         vuint32_t  NCFE101:1;         /* NCF 101 enable */
-         vuint32_t  NCFE100:1;         /* NCF 100 enable */
-         vuint32_t  NCFE99:1;          /* NCF 99 enable */
-         vuint32_t  NCFE98:1;          /* NCF 98 enable */
-         vuint32_t  NCFE97:1;          /* NCF 97 enable */
-         vuint32_t  NCFE96:1;          /* NCF 96 enable */
-      } B;
-   } FCCU_NCFE3_32B_tag;
-
-   typedef union {   /* FCCU NCF Time-out Enable Register 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFTOE31:1;        /* NCF 31 time-out enable */
-         vuint32_t  NCFTOE30:1;        /* NCF 30 time-out enable */
-         vuint32_t  NCFTOE29:1;        /* NCF 29 time-out enable */
-         vuint32_t  NCFTOE28:1;        /* NCF 28 time-out enable */
-         vuint32_t  NCFTOE27:1;        /* NCF 27 time-out enable */
-         vuint32_t  NCFTOE26:1;        /* NCF 26 time-out enable */
-         vuint32_t  NCFTOE25:1;        /* NCF 25 time-out enable */
-         vuint32_t  NCFTOE24:1;        /* NCF 24 time-out enable */
-         vuint32_t  NCFTOE23:1;        /* NCF 23 time-out enable */
-         vuint32_t  NCFTOE22:1;        /* NCF 22 time-out enable */
-         vuint32_t  NCFTOE21:1;        /* NCF 21 time-out enable */
-         vuint32_t  NCFTOE20:1;        /* NCF 20 time-out enable */
-         vuint32_t  NCFTOE19:1;        /* NCF 19 time-out enable */
-         vuint32_t  NCFTOE18:1;        /* NCF 18 time-out enable */
-         vuint32_t  NCFTOE17:1;        /* NCF 17 time-out enable */
-         vuint32_t  NCFTOE16:1;        /* NCF 16 time-out enable */
-         vuint32_t  NCFTOE15:1;        /* NCF 15 time-out enable */
-         vuint32_t  NCFTOE14:1;        /* NCF 14 time-out enable */
-         vuint32_t  NCFTOE13:1;        /* NCF 13 time-out enable */
-         vuint32_t  NCFTOE12:1;        /* NCF 12 time-out enable */
-         vuint32_t  NCFTOE11:1;        /* NCF 11 time-out enable */
-         vuint32_t  NCFTOE10:1;        /* NCF 10 time-out enable */
-         vuint32_t  NCFTOE9:1;         /* NCF 9 time-out enable */
-         vuint32_t  NCFTOE8:1;         /* NCF 8 time-out enable */
-         vuint32_t  NCFTOE7:1;         /* NCF 7 time-out enable */
-         vuint32_t  NCFTOE6:1;         /* NCF 6 time-out enable */
-         vuint32_t  NCFTOE5:1;         /* NCF 5 time-out enable */
-         vuint32_t  NCFTOE4:1;         /* NCF 4 time-out enable */
-         vuint32_t  NCFTOE3:1;         /* NCF 3 time-out enable */
-         vuint32_t  NCFTOE2:1;         /* NCF 2 time-out enable */
-         vuint32_t  NCFTOE1:1;         /* NCF 1 time-out enable */
-         vuint32_t  NCFTOE0:1;         /* NCF 0 time-out enable */
-      } B;
-   } FCCU_NCF_TOE0_32B_tag;
-
-   typedef union {   /* FCCU NCF Time-out Enable Register 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFTOE63:1;        /* NCF 63 time-out enable */
-         vuint32_t  NCFTOE62:1;        /* NCF 62 time-out enable */
-         vuint32_t  NCFTOE61:1;        /* NCF 61 time-out enable */
-         vuint32_t  NCFTOE60:1;        /* NCF 60 time-out enable */
-         vuint32_t  NCFTOE59:1;        /* NCF 59 time-out enable */
-         vuint32_t  NCFTOE58:1;        /* NCF 58 time-out enable */
-         vuint32_t  NCFTOE57:1;        /* NCF 57 time-out enable */
-         vuint32_t  NCFTOE56:1;        /* NCF 56 time-out enable */
-         vuint32_t  NCFTOE55:1;        /* NCF 55 time-out enable */
-         vuint32_t  NCFTOE54:1;        /* NCF 54 time-out enable */
-         vuint32_t  NCFTOE53:1;        /* NCF 53 time-out enable */
-         vuint32_t  NCFTOE52:1;        /* NCF 52 time-out enable */
-         vuint32_t  NCFTOE51:1;        /* NCF 51 time-out enable */
-         vuint32_t  NCFTOE50:1;        /* NCF 50 time-out enable */
-         vuint32_t  NCFTOE49:1;        /* NCF 49 time-out enable */
-         vuint32_t  NCFTOE48:1;        /* NCF 48 time-out enable */
-         vuint32_t  NCFTOE47:1;        /* NCF 47 time-out enable */
-         vuint32_t  NCFTOE46:1;        /* NCF 46 time-out enable */
-         vuint32_t  NCFTOE45:1;        /* NCF 45 time-out enable */
-         vuint32_t  NCFTOE44:1;        /* NCF 44 time-out enable */
-         vuint32_t  NCFTOE43:1;        /* NCF 43 time-out enable */
-         vuint32_t  NCFTOE42:1;        /* NCF 42 time-out enable */
-         vuint32_t  NCFTOE41:1;        /* NCF 41 time-out enable */
-         vuint32_t  NCFTOE40:1;        /* NCF 40 time-out enable */
-         vuint32_t  NCFTOE39:1;        /* NCF 39 time-out enable */
-         vuint32_t  NCFTOE38:1;        /* NCF 38 time-out enable */
-         vuint32_t  NCFTOE37:1;        /* NCF 37 time-out enable */
-         vuint32_t  NCFTOE36:1;        /* NCF 36 time-out enable */
-         vuint32_t  NCFTOE35:1;        /* NCF 35 time-out enable */
-         vuint32_t  NCFTOE34:1;        /* NCF 34 time-out enable */
-         vuint32_t  NCFTOE33:1;        /* NCF 33 time-out enable */
-         vuint32_t  NCFTOE32:1;        /* NCF 32 time-out enable */
-      } B;
-   } FCCU_NCF_TOE1_32B_tag;
-
-   typedef union {   /* FCCU NCF Time-out Enable Register 2 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFTOE95:1;        /* NCF 95 time-out enable */
-         vuint32_t  NCFTOE94:1;        /* NCF 94 time-out enable */
-         vuint32_t  NCFTOE93:1;        /* NCF 93 time-out enable */
-         vuint32_t  NCFTOE92:1;        /* NCF 92 time-out enable */
-         vuint32_t  NCFTOE91:1;        /* NCF 91 time-out enable */
-         vuint32_t  NCFTOE90:1;        /* NCF 90 time-out enable */
-         vuint32_t  NCFTOE89:1;        /* NCF 89 time-out enable */
-         vuint32_t  NCFTOE88:1;        /* NCF 88 time-out enable */
-         vuint32_t  NCFTOE87:1;        /* NCF 87 time-out enable */
-         vuint32_t  NCFTOE86:1;        /* NCF 86 time-out enable */
-         vuint32_t  NCFTOE85:1;        /* NCF 85 time-out enable */
-         vuint32_t  NCFTOE84:1;        /* NCF 84 time-out enable */
-         vuint32_t  NCFTOE83:1;        /* NCF 83 time-out enable */
-         vuint32_t  NCFTOE82:1;        /* NCF 82 time-out enable */
-         vuint32_t  NCFTOE81:1;        /* NCF 81 time-out enable */
-         vuint32_t  NCFTOE80:1;        /* NCF 80 time-out enable */
-         vuint32_t  NCFTOE79:1;        /* NCF 79 time-out enable */
-         vuint32_t  NCFTOE78:1;        /* NCF 78 time-out enable */
-         vuint32_t  NCFTOE77:1;        /* NCF 77 time-out enable */
-         vuint32_t  NCFTOE76:1;        /* NCF 76 time-out enable */
-         vuint32_t  NCFTOE75:1;        /* NCF 75 time-out enable */
-         vuint32_t  NCFTOE74:1;        /* NCF 74 time-out enable */
-         vuint32_t  NCFTOE73:1;        /* NCF 73 time-out enable */
-         vuint32_t  NCFTOE72:1;        /* NCF 72 time-out enable */
-         vuint32_t  NCFTOE71:1;        /* NCF 71 time-out enable */
-         vuint32_t  NCFTOE70:1;        /* NCF 70 time-out enable */
-         vuint32_t  NCFTOE69:1;        /* NCF 69 time-out enable */
-         vuint32_t  NCFTOE68:1;        /* NCF 68 time-out enable */
-         vuint32_t  NCFTOE67:1;        /* NCF 67 time-out enable */
-         vuint32_t  NCFTOE66:1;        /* NCF 66 time-out enable */
-         vuint32_t  NCFTOE65:1;        /* NCF 65 time-out enable */
-         vuint32_t  NCFTOE64:1;        /* NCF 64 time-out enable */
-      } B;
-   } FCCU_NCF_TOE2_32B_tag;
-
-   typedef union {   /* FCCU NCF Time-out Enable Register 3 */
-      vuint32_t R;
-      struct {
-         vuint32_t  NCFTOE127:1;       /* NCF 127 time-out enable */
-         vuint32_t  NCFTOE126:1;       /* NCF 126 time-out enable */
-         vuint32_t  NCFTOE125:1;       /* NCF 125 time-out enable */
-         vuint32_t  NCFTOE124:1;       /* NCF 124 time-out enable */
-         vuint32_t  NCFTOE123:1;       /* NCF 123 time-out enable */
-         vuint32_t  NCFTOE122:1;       /* NCF 122 time-out enable */
-         vuint32_t  NCFTOE121:1;       /* NCF 121 time-out enable */
-         vuint32_t  NCFTOE120:1;       /* NCF 120 time-out enable */
-         vuint32_t  NCFTOE119:1;       /* NCF 119 time-out enable */
-         vuint32_t  NCFTOE118:1;       /* NCF 118 time-out enable */
-         vuint32_t  NCFTOE117:1;       /* NCF 117 time-out enable */
-         vuint32_t  NCFTOE116:1;       /* NCF 116 time-out enable */
-         vuint32_t  NCFTOE115:1;       /* NCF 115 time-out enable */
-         vuint32_t  NCFTOE114:1;       /* NCF 114 time-out enable */
-         vuint32_t  NCFTOE113:1;       /* NCF 113 time-out enable */
-         vuint32_t  NCFTOE112:1;       /* NCF 112 time-out enable */
-         vuint32_t  NCFTOE111:1;       /* NCF 111 time-out enable */
-         vuint32_t  NCFTOE110:1;       /* NCF 110 time-out enable */
-         vuint32_t  NCFTOE109:1;       /* NCF 109 time-out enable */
-         vuint32_t  NCFTOE108:1;       /* NCF 108 time-out enable */
-         vuint32_t  NCFTOE107:1;       /* NCF 107 time-out enable */
-         vuint32_t  NCFTOE106:1;       /* NCF 106 time-out enable */
-         vuint32_t  NCFTOE105:1;       /* NCF 105 time-out enable */
-         vuint32_t  NCFTOE104:1;       /* NCF 104 time-out enable */
-         vuint32_t  NCFTOE103:1;       /* NCF 103 time-out enable */
-         vuint32_t  NCFTOE102:1;       /* NCF 102 time-out enable */
-         vuint32_t  NCFTOE101:1;       /* NCF 101 time-out enable */
-         vuint32_t  NCFTOE100:1;       /* NCF 100 time-out enable */
-         vuint32_t  NCFTOE99:1;        /* NCF 99 time-out enable */
-         vuint32_t  NCFTOE98:1;        /* NCF 98 time-out enable */
-         vuint32_t  NCFTOE97:1;        /* NCF 97 time-out enable */
-         vuint32_t  NCFTOE96:1;        /* NCF 96 time-out enable */
-      } B;
-   } FCCU_NCF_TOE3_32B_tag;
-
-   typedef union {   /* FCCU_NCF_TO - FCCU NCF Time-out Register */
-      vuint32_t R;
-   } FCCU_NCF_TO_32B_tag;
-
-   typedef union {   /* FCCU_CFG_TO - FCCU CFG Timeout Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:29;
-         vuint32_t  TO:3;              /* Configuration time-out */
-      } B;
-   } FCCU_CFG_TO_32B_tag;
-
-   typedef union {   /* FCCU_EINOUT - FCCU IO Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:26;
-         vuint32_t  EIN1:1;            /* Error input 1 */
-         vuint32_t  EIN0:1;            /* Error input 0 */
-         vuint32_t:2;
-         vuint32_t  EOUT1:1;           /* Error out 1 */
-         vuint32_t  EOUT0:1;           /* Error out 0 */
-      } B;
-   } FCCU_EINOUT_32B_tag;
-
-   typedef union {   /* FCCU_STAT - FCCU Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:29;
-         vuint32_t  STATUS:3;          /* FCCU status */
-      } B;
-   } FCCU_STAT_32B_tag;
-
-   typedef union {   /* FCCU_NAFS - FCCU NA Freeze Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:24;
-         vuint32_t  N2AFSTATUS:8;      /* Normal to Alarm Frozen Status */
-      } B;
-   } FCCU_NAFS_32B_tag;
-
-   typedef union {   /* FCCU_AFFS - FCCU AF Freeze Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:22;
-         vuint32_t  AFFS_SRC:2;        /* Fault source */
-         vuint32_t  A2AFSTATUS:8;      /* Alarm to Fault Frozen Status */
-      } B;
-   } FCCU_AFFS_32B_tag;
-
-   typedef union {   /* FCCU_NFFS - FCCU NF Freeze Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:22;
-         vuint32_t  NFFS_SRC:2;        /* Fault source */
-         vuint32_t  NFFS_NFFS:8;       /* Normal to Fault Frozen Status */
-      } B;
-   } FCCU_NFFS_32B_tag;
-
-   typedef union {   /* FCCU_FAFS - FCCU FA Freeze Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:24;
-         vuint32_t  FAFS_FAFS:8;       /* Fault to Normal Frozen Status */
-      } B;
-   } FCCU_FAFS_32B_tag;
-
-   typedef union {   /* FCCU_SCFS - FCCU SC Freeze Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:30;
-         vuint32_t  RCCS1:1;           /* RCC1 Status */
-         vuint32_t  RCCS0:1;           /* RCC0 Status */
-      } B;
-   } FCCU_SCFS_32B_tag;
-
-   typedef union {   /* FCCU_CFF - FCCU CF Fake Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:25;
-         vuint32_t  FCFC:7;            /* Fake critical fault code */
-      } B;
-   } FCCU_CFF_32B_tag;
-
-   typedef union {   /* FCCU_NCFF - FCCU NCF Fake Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:25;
-         vuint32_t  FNCFC:7;           /* Fake non-critical fault code */
-      } B;
-   } FCCU_NCFF_32B_tag;
-
-   typedef union {   /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:29;
-         vuint32_t  NMI_STAT:1;        /* NMI Interrupt Status */
-         vuint32_t  ALRM_STAT:1;       /* Alarm Interrupt Status */
-         vuint32_t  CFG_TO_STAT:1;     /* Configuration Time-out Status */
-      } B;
-   } FCCU_IRQ_STAT_32B_tag;
-
-   typedef union {   /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:31;
-         vuint32_t  CFG_TO_IEN:1;      /* Configuration Time-out Interrupt Enable */
-      } B;
-   } FCCU_IRQ_EN_32B_tag;
-
-   typedef union {   /* FCCU_XTMR - FCCU XTMR Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  XTMR_XTMR:32;      /* Alarm/Watchdog/safe request timer */
-      } B;
-   } FCCU_XTMR_32B_tag;
-
-   typedef union {   /* FCCU_MCS - FCCU MCS Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  VL3:1;             /* Valid */
-         vuint32_t  FS3:1;             /* Fault Status */
-         vuint32_t:2;
-         vuint32_t  MCS3:4;            /* Magic Carpet oldest state */
-         vuint32_t  VL2:1;             /* Valid */
-         vuint32_t  FS2:1;             /* Fault Status */
-         vuint32_t:2;
-         vuint32_t  MCS2:4;            /* Magic Carpet previous-previous state */
-         vuint32_t  VL1:1;             /* Valid */
-         vuint32_t  FS1:1;             /* Fault Status */
-         vuint32_t:2;
-         vuint32_t  MCS1:4;            /* Magic Carpet previous state */
-         vuint32_t  VL0:1;             /* Valid */
-         vuint32_t  FS0:1;             /* Fault Status */
-         vuint32_t:2;
-         vuint32_t  MCS0:4;            /* Magic Carpet latest state */
-      } B;
-   } FCCU_MCS_32B_tag;
-
-
-   /* Register layout for generated register(s) CF_CFG... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } FCCU_CF_CFG_32B_tag;
-
-
-   /* Register layout for generated register(s) NCF_CFG... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } FCCU_NCF_CFG_32B_tag;
-
-
-   /* Register layout for generated register(s) CFS_CFG... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } FCCU_CFS_CFG_32B_tag;
-
-
-   /* Register layout for generated register(s) NCFS_CFG... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } FCCU_NCFS_CFG_32B_tag;
-
-
-   /* Register layout for generated register(s) CFS... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } FCCU_CFS_32B_tag;
-
-
-   /* Register layout for generated register(s) NCFS... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } FCCU_NCFS_32B_tag;
-
-
-   /* Register layout for generated register(s) NCFE... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } FCCU_NCFE_32B_tag;
-
-
-   /* Register layout for generated register(s) NCF_TOE... */
-
-   typedef union {   /*  */
-      vuint32_t R;
-   } FCCU_NCF_TOE_32B_tag;
-
-
-
-   typedef struct FCCU_struct_tag { /* start of FCCU_tag */
-                                                /* FCCU Control Register */
-      FCCU_CTRL_32B_tag CTRL;              /* offset: 0x0000 size: 32 bit */
-                                               /* FCCU CTRL Key Register */
-      FCCU_CTRLK_32B_tag CTRLK;            /* offset: 0x0004 size: 32 bit */
-                                          /* FCCU Configuration Register */
-      FCCU_CFG_32B_tag CFG;                /* offset: 0x0008 size: 32 bit */
-      union {
-         FCCU_CF_CFG_32B_tag CF_CFG[4];    /* offset: 0x000C  (0x0004 x 4) */
-
-         struct {
-                                     /* FCCU CF Configuration Register 0 */
-            FCCU_CF_CFG0_32B_tag CF_CFG0;  /* offset: 0x000C size: 32 bit */
-                                     /* FCCU CF Configuration Register 1 */
-            FCCU_CF_CFG1_32B_tag CF_CFG1;  /* offset: 0x0010 size: 32 bit */
-                                     /* FCCU CF Configuration Register 2 */
-            FCCU_CF_CFG2_32B_tag CF_CFG2;  /* offset: 0x0014 size: 32 bit */
-                                     /* FCCU CF Configuration Register 3 */
-            FCCU_CF_CFG3_32B_tag CF_CFG3;  /* offset: 0x0018 size: 32 bit */
-         };
-
-      };
-      union {
-         FCCU_NCF_CFG_32B_tag NCF_CFG[4];  /* offset: 0x001C  (0x0004 x 4) */
-
-         struct {
-                                    /* FCCU NCF Configuration Register 0 */
-            FCCU_NCF_CFG0_32B_tag NCF_CFG0;  /* offset: 0x001C size: 32 bit */
-                                    /* FCCU NCF Configuration Register 1 */
-            FCCU_NCF_CFG1_32B_tag NCF_CFG1;  /* offset: 0x0020 size: 32 bit */
-                                    /* FCCU NCF Configuration Register 2 */
-            FCCU_NCF_CFG2_32B_tag NCF_CFG2;  /* offset: 0x0024 size: 32 bit */
-                                    /* FCCU NCF Configuration Register 3 */
-            FCCU_NCF_CFG3_32B_tag NCF_CFG3;  /* offset: 0x0028 size: 32 bit */
-         };
-
-      };
-      union {
-         FCCU_CFS_CFG_32B_tag CFS_CFG[8];  /* offset: 0x002C  (0x0004 x 8) */
-
-         struct {
-                                    /* FCCU CFS Configuration Register 0 */
-            FCCU_CFS_CFG0_32B_tag CFS_CFG0;  /* offset: 0x002C size: 32 bit */
-                                    /* FCCU CFS Configuration Register 1 */
-            FCCU_CFS_CFG1_32B_tag CFS_CFG1;  /* offset: 0x0030 size: 32 bit */
-                                    /* FCCU CFS Configuration Register 2 */
-            FCCU_CFS_CFG2_32B_tag CFS_CFG2;  /* offset: 0x0034 size: 32 bit */
-                                    /* FCCU CFS Configuration Register 3 */
-            FCCU_CFS_CFG3_32B_tag CFS_CFG3;  /* offset: 0x0038 size: 32 bit */
-                                    /* FCCU CFS Configuration Register 4 */
-            FCCU_CFS_CFG4_32B_tag CFS_CFG4;  /* offset: 0x003C size: 32 bit */
-                                    /* FCCU CFS Configuration Register 5 */
-            FCCU_CFS_CFG5_32B_tag CFS_CFG5;  /* offset: 0x0040 size: 32 bit */
-                                    /* FCCU CFS Configuration Register 6 */
-            FCCU_CFS_CFG6_32B_tag CFS_CFG6;  /* offset: 0x0044 size: 32 bit */
-                                    /* FCCU CFS Configuration Register 7 */
-            FCCU_CFS_CFG7_32B_tag CFS_CFG7;  /* offset: 0x0048 size: 32 bit */
-         };
-
-      };
-      union {
-         FCCU_NCFS_CFG_32B_tag NCFS_CFG[8];  /* offset: 0x004C  (0x0004 x 8) */
-
-         struct {
-                                   /* FCCU NCFS Configuration Register 0 */
-            FCCU_NCFS_CFG0_32B_tag NCFS_CFG0;  /* offset: 0x004C size: 32 bit */
-                                   /* FCCU NCFS Configuration Register 1 */
-            FCCU_NCFS_CFG1_32B_tag NCFS_CFG1;  /* offset: 0x0050 size: 32 bit */
-                                   /* FCCU NCFS Configuration Register 2 */
-            FCCU_NCFS_CFG2_32B_tag NCFS_CFG2;  /* offset: 0x0054 size: 32 bit */
-                                   /* FCCU NCFS Configuration Register 3 */
-            FCCU_NCFS_CFG3_32B_tag NCFS_CFG3;  /* offset: 0x0058 size: 32 bit */
-                                   /* FCCU NCFS Configuration Register 4 */
-            FCCU_NCFS_CFG4_32B_tag NCFS_CFG4;  /* offset: 0x005C size: 32 bit */
-                                   /* FCCU NCFS Configuration Register 5 */
-            FCCU_NCFS_CFG5_32B_tag NCFS_CFG5;  /* offset: 0x0060 size: 32 bit */
-                                   /* FCCU NCFS Configuration Register 6 */
-            FCCU_NCFS_CFG6_32B_tag NCFS_CFG6;  /* offset: 0x0064 size: 32 bit */
-                                   /* FCCU NCFS Configuration Register 7 */
-            FCCU_NCFS_CFG7_32B_tag NCFS_CFG7;  /* offset: 0x0068 size: 32 bit */
-         };
-
-      };
-      union {
-         FCCU_CFS_32B_tag CFS[4];          /* offset: 0x006C  (0x0004 x 4) */
-
-         struct {
-                                            /* FCCU CF Status Register 0 */
-            FCCU_CFS0_32B_tag CFS0;        /* offset: 0x006C size: 32 bit */
-                                            /* FCCU CF Status Register 1 */
-            FCCU_CFS1_32B_tag CFS1;        /* offset: 0x0070 size: 32 bit */
-                                            /* FCCU CF Status Register 2 */
-            FCCU_CFS2_32B_tag CFS2;        /* offset: 0x0074 size: 32 bit */
-                                            /* FCCU CF Status Register 3 */
-            FCCU_CFS3_32B_tag CFS3;        /* offset: 0x0078 size: 32 bit */
-         };
-
-      };
-                                      /* FCCU_CFK - FCCU CF Key Register */
-      FCCU_CFK_32B_tag CFK;                /* offset: 0x007C size: 32 bit */
-      union {
-         FCCU_NCFS_32B_tag NCFS[4];        /* offset: 0x0080  (0x0004 x 4) */
-
-         struct {
-                                           /* FCCU NCF Status Register 0 */
-            FCCU_NCFS0_32B_tag NCFS0;      /* offset: 0x0080 size: 32 bit */
-                                           /* FCCU NCF Status Register 1 */
-            FCCU_NCFS1_32B_tag NCFS1;      /* offset: 0x0084 size: 32 bit */
-                                           /* FCCU NCF Status Register 2 */
-            FCCU_NCFS2_32B_tag NCFS2;      /* offset: 0x0088 size: 32 bit */
-                                           /* FCCU NCF Status Register 3 */
-            FCCU_NCFS3_32B_tag NCFS3;      /* offset: 0x008C size: 32 bit */
-         };
-
-      };
-                                    /* FCCU_NCFK - FCCU NCF Key Register */
-      FCCU_NCFK_32B_tag NCFK;              /* offset: 0x0090 size: 32 bit */
-      union {
-         FCCU_NCFE_32B_tag NCFE[4];        /* offset: 0x0094  (0x0004 x 4) */
-
-         struct {
-                                           /* FCCU NCF Enable Register 0 */
-            FCCU_NCFE0_32B_tag NCFE0;      /* offset: 0x0094 size: 32 bit */
-                                           /* FCCU NCF Enable Register 1 */
-            FCCU_NCFE1_32B_tag NCFE1;      /* offset: 0x0098 size: 32 bit */
-                                           /* FCCU NCF Enable Register 2 */
-            FCCU_NCFE2_32B_tag NCFE2;      /* offset: 0x009C size: 32 bit */
-                                           /* FCCU NCF Enable Register 3 */
-            FCCU_NCFE3_32B_tag NCFE3;      /* offset: 0x00A0 size: 32 bit */
-         };
-
-      };
-      union {
-         FCCU_NCF_TOE_32B_tag NCF_TOE[4];  /* offset: 0x00A4  (0x0004 x 4) */
-
-         struct {
-                                  /* FCCU NCF Time-out Enable Register 0 */
-            FCCU_NCF_TOE0_32B_tag NCF_TOE0;  /* offset: 0x00A4 size: 32 bit */
-                                  /* FCCU NCF Time-out Enable Register 1 */
-            FCCU_NCF_TOE1_32B_tag NCF_TOE1;  /* offset: 0x00A8 size: 32 bit */
-                                  /* FCCU NCF Time-out Enable Register 2 */
-            FCCU_NCF_TOE2_32B_tag NCF_TOE2;  /* offset: 0x00AC size: 32 bit */
-                                  /* FCCU NCF Time-out Enable Register 3 */
-            FCCU_NCF_TOE3_32B_tag NCF_TOE3;  /* offset: 0x00B0 size: 32 bit */
-         };
-
-      };
-                             /* FCCU_NCF_TO - FCCU NCF Time-out Register */
-      FCCU_NCF_TO_32B_tag NCF_TO;          /* offset: 0x00B4 size: 32 bit */
-                              /* FCCU_CFG_TO - FCCU CFG Timeout Register */
-      FCCU_CFG_TO_32B_tag CFG_TO;          /* offset: 0x00B8 size: 32 bit */
-                               /* FCCU_EINOUT - FCCU IO Control Register */
-      FCCU_EINOUT_32B_tag EINOUT;          /* offset: 0x00BC size: 32 bit */
-                                     /* FCCU_STAT - FCCU Status Register */
-      FCCU_STAT_32B_tag STAT;              /* offset: 0x00C0 size: 32 bit */
-                           /* FCCU_NAFS - FCCU NA Freeze Status Register */
-      FCCU_NAFS_32B_tag NAFS;              /* offset: 0x00C4 size: 32 bit */
-                           /* FCCU_AFFS - FCCU AF Freeze Status Register */
-      FCCU_AFFS_32B_tag AFFS;              /* offset: 0x00C8 size: 32 bit */
-                           /* FCCU_NFFS - FCCU NF Freeze Status Register */
-      FCCU_NFFS_32B_tag NFFS;              /* offset: 0x00CC size: 32 bit */
-                           /* FCCU_FAFS - FCCU FA Freeze Status Register */
-      FCCU_FAFS_32B_tag FAFS;              /* offset: 0x00D0 size: 32 bit */
-                           /* FCCU_SCFS - FCCU SC Freeze Status Register */
-      FCCU_SCFS_32B_tag SCFS;              /* offset: 0x00D4 size: 32 bit */
-                                     /* FCCU_CFF - FCCU CF Fake Register */
-      FCCU_CFF_32B_tag CFF;                /* offset: 0x00D8 size: 32 bit */
-                                   /* FCCU_NCFF - FCCU NCF Fake Register */
-      FCCU_NCFF_32B_tag NCFF;              /* offset: 0x00DC size: 32 bit */
-                             /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
-      FCCU_IRQ_STAT_32B_tag IRQ_STAT;      /* offset: 0x00E0 size: 32 bit */
-                               /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
-      FCCU_IRQ_EN_32B_tag IRQ_EN;          /* offset: 0x00E4 size: 32 bit */
-                                       /* FCCU_XTMR - FCCU XTMR Register */
-      FCCU_XTMR_32B_tag XTMR;              /* offset: 0x00E8 size: 32 bit */
-                                         /* FCCU_MCS - FCCU MCS Register */
-      FCCU_MCS_32B_tag MCS;                /* offset: 0x00EC size: 32 bit */
-   } FCCU_tag;
-
-
-#define FCCU  (*(volatile FCCU_tag *) 0xFFE6C000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: SGENDIG  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* SGENDIG_CTRL - SGENDIG Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  LDOS:1;            /* Operation Status */
-         vuint32_t  IOAMPL:5;          /* Define the AMPLitude value on I/O pad */
-         vuint32_t:2;
-         vuint32_t  SEMASK:1;          /* Sine wave generator Error MASK interrupt register */
-         vuint32_t:5;
-         vuint32_t  S0H1:1;            /* Operation Status */
-         vuint32_t  PDS:1;             /* Operation Status */
-         vuint32_t  IOFREQ:16;         /* Define the FREQuency value on I/O pad */
-      } B;
-   } SGENDIG_CTRL_32B_tag;
-
-   typedef union {   /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable  Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:8;
-         vuint32_t  SERR:1;            /* Sine wave generator Error bit */
-         vuint32_t:3;
-         vuint32_t  FERR:1;            /* Sine wave generator Force Error bit */
-         vuint32_t:19;
-      } B;
-   } SGENDIG_IRQE_32B_tag;
-
-
-
-   typedef struct SGENDIG_struct_tag { /* start of SGENDIG_tag */
-                              /* SGENDIG_CTRL - SGENDIG Control Register */
-      SGENDIG_CTRL_32B_tag CTRL;           /* offset: 0x0000 size: 32 bit */
-            /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable  Register */
-      SGENDIG_IRQE_32B_tag IRQE;           /* offset: 0x0004 size: 32 bit */
-   } SGENDIG_tag;
-
-
-#define SGENDIG (*(volatile SGENDIG_tag *) 0xFFE78000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: AIPS  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* MPROT - Master Privilege Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  MPROT0_MBW:1;      /* Master 0 Buffer Writes */
-         vuint32_t  MPROT0_MTR:1;      /* Master 0 Trusted for Reads */
-         vuint32_t  MPROT0_MTW:1;      /* Master 0 Trusted for Writes */
-         vuint32_t  MPROT0_MPL:1;      /* Master 0 Priviledge Level */
-         vuint32_t  MPROT1_MBW:1;      /* Master 1 Buffer Writes */
-         vuint32_t  MPROT1_MTR:1;      /* Master 1 Trusted for Reads */
-         vuint32_t  MPROT1_MTW:1;      /* Master 1 Trusted for Writes */
-         vuint32_t  MPROT1_MPL:1;      /* Master 1 Priviledge Level */
-         vuint32_t  MPROT2_MBW:1;      /* Master 2 Buffer Writes */
-         vuint32_t  MPROT2_MTR:1;      /* Master 2 Trusted for Reads */
-         vuint32_t  MPROT2_MTW:1;      /* Master 2 Trusted for Writes */
-         vuint32_t  MPROT2_MPL:1;      /* Master 2 Priviledge Level */
-         vuint32_t  MPROT3_MBW:1;      /* Master 3 Buffer Writes */
-         vuint32_t  MPROT3_MTR:1;      /* Master 3 Trusted for Reads */
-         vuint32_t  MPROT3_MTW:1;      /* Master 3 Trusted for Writes */
-         vuint32_t  MPROT3_MPL:1;      /* Master 3 Priviledge Level */
-         vuint32_t  MPROT4_MBW:1;      /* Master 4 Buffer Writes */
-         vuint32_t  MPROT4_MTR:1;      /* Master 4 Trusted for Reads */
-         vuint32_t  MPROT4_MTW:1;      /* Master 4 Trusted for Writes */
-         vuint32_t  MPROT4_MPL:1;      /* Master 4 Priviledge Level */
-         vuint32_t  MPROT5_MBW:1;      /* Master 5 Buffer Writes */
-         vuint32_t  MPROT5_MTR:1;      /* Master 5 Trusted for Reads */
-         vuint32_t  MPROT5_MTW:1;      /* Master 5 Trusted for Writes */
-         vuint32_t  MPROT5_MPL:1;      /* Master 5 Priviledge Level */
-         vuint32_t  MPROT6_MBW:1;      /* Master 6 Buffer Writes */
-         vuint32_t  MPROT6_MTR:1;      /* Master 6 Trusted for Reads */
-         vuint32_t  MPROT6_MTW:1;      /* Master 6 Trusted for Writes */
-         vuint32_t  MPROT6_MPL:1;      /* Master 6 Priviledge Level */
-         vuint32_t  MPROT7_MBW:1;      /* Master 7 Buffer Writes */
-         vuint32_t  MPROT7_MTR:1;      /* Master 7 Trusted for Reads */
-         vuint32_t  MPROT7_MTW:1;      /* Master 7 Trusted for Writes */
-         vuint32_t  MPROT7_MPL:1;      /* Master 7 Priviledge Level */
-      } B;
-   } AIPS_MPROT_32B_tag;
-
-   typedef union {   /* PACR0_7 - Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  PACR0_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR0_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR0_WP:1;        /* Write Protect */
-         vuint32_t  PACR0_TP:1;        /* Trusted Protect */
-         vuint32_t  PACR1_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR1_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR1_WP:1;        /* Write Protect */
-         vuint32_t  PACR1_TP:1;        /* Trusted Protect */
-         vuint32_t  PACR2_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR2_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR2_WP:1;        /* Write Protect */
-         vuint32_t  PACR2_TP:1;        /* Trusted Protect */
-         vuint32_t  PACR3_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR3_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR3_WP:1;        /* Write Protect */
-         vuint32_t  PACR3_TP:1;        /* Trusted Protect */
-         vuint32_t  PACR4_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR4_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR4_WP:1;        /* Write Protect */
-         vuint32_t  PACR4_TP:1;        /* Trusted Protect */
-         vuint32_t  PACR5_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR5_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR5_WP:1;        /* Write Protect */
-         vuint32_t  PACR5_TP:1;        /* Trusted Protect */
-         vuint32_t  PACR6_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR6_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR6_WP:1;        /* Write Protect */
-         vuint32_t  PACR6_TP:1;        /* Trusted Protect */
-         vuint32_t  PACR7_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR7_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR7_WP:1;        /* Write Protect */
-         vuint32_t  PACR7_TP:1;        /* Trusted Protect */
-      } B;
-   } AIPS_PACR0_7_32B_tag;
-
-   typedef union {   /* PACR8_15 - Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  PACR8_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR8_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR8_WP:1;        /* Write Protect */
-         vuint32_t  PACR8_TP:1;        /* Trusted Protect */
-         vuint32_t  PACR9_BW:1;        /* Buffer Writes */
-         vuint32_t  PACR9_SP:1;        /* Supervisor Protect */
-         vuint32_t  PACR9_WP:1;        /* Write Protect */
-         vuint32_t  PACR9_TP:1;        /* Trusted Protect */
-         vuint32_t  PACR10_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR10_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR10_WP:1;       /* Write Protect */
-         vuint32_t  PACR10_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR11_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR11_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR11_WP:1;       /* Write Protect */
-         vuint32_t  PACR11_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR12_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR12_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR12_WP:1;       /* Write Protect */
-         vuint32_t  PACR12_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR13_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR13_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR13_WP:1;       /* Write Protect */
-         vuint32_t  PACR13_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR14_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR14_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR14_WP:1;       /* Write Protect */
-         vuint32_t  PACR14_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR15_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR15_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR15_WP:1;       /* Write Protect */
-         vuint32_t  PACR15_TP:1;       /* Trusted Protect */
-      } B;
-   } AIPS_PACR8_15_32B_tag;
-
-   typedef union {   /* PACR16_23 - Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  PACR16_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR16_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR16_WP:1;       /* Write Protect */
-         vuint32_t  PACR16_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR17_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR17_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR17_WP:1;       /* Write Protect */
-         vuint32_t  PACR17_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR18_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR18_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR18_WP:1;       /* Write Protect */
-         vuint32_t  PACR18_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR19_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR19_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR19_WP:1;       /* Write Protect */
-         vuint32_t  PACR19_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR20_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR20_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR20_WP:1;       /* Write Protect */
-         vuint32_t  PACR20_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR21_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR21_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR21_WP:1;       /* Write Protect */
-         vuint32_t  PACR21_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR22_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR22_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR22_WP:1;       /* Write Protect */
-         vuint32_t  PACR22_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR23_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR23_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR23_WP:1;       /* Write Protect */
-         vuint32_t  PACR23_TP:1;       /* Trusted Protect */
-      } B;
-   } AIPS_PACR16_23_32B_tag;
-
-   typedef union {   /* PACR24_31 - Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  PACR24_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR24_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR24_WP:1;       /* Write Protect */
-         vuint32_t  PACR24_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR25_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR25_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR25_WP:1;       /* Write Protect */
-         vuint32_t  PACR25_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR26_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR26_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR26_WP:1;       /* Write Protect */
-         vuint32_t  PACR26_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR27_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR27_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR27_WP:1;       /* Write Protect */
-         vuint32_t  PACR27_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR28_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR28_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR28_WP:1;       /* Write Protect */
-         vuint32_t  PACR28_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR29_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR29_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR29_WP:1;       /* Write Protect */
-         vuint32_t  PACR29_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR30_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR30_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR30_WP:1;       /* Write Protect */
-         vuint32_t  PACR30_TP:1;       /* Trusted Protect */
-         vuint32_t  PACR31_BW:1;       /* Buffer Writes */
-         vuint32_t  PACR31_SP:1;       /* Supervisor Protect */
-         vuint32_t  PACR31_WP:1;       /* Write Protect */
-         vuint32_t  PACR31_TP:1;       /* Trusted Protect */
-      } B;
-   } AIPS_PACR24_31_32B_tag;
-
-   typedef union {   /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR0_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR0_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR0_WP:1;       /* Write Protect */
-         vuint32_t  OPACR0_TP:1;       /* Trusted Protect */
-         vuint32_t  OPACR1_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR1_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR1_WP:1;       /* Write Protect */
-         vuint32_t  OPACR1_TP:1;       /* Trusted Protect */
-         vuint32_t  OPACR2_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR2_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR2_WP:1;       /* Write Protect */
-         vuint32_t  OPACR2_TP:1;       /* Trusted Protect */
-         vuint32_t  OPACR3_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR3_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR3_WP:1;       /* Write Protect */
-         vuint32_t  OPACR3_TP:1;       /* Trusted Protect */
-         vuint32_t  OPACR4_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR4_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR4_WP:1;       /* Write Protect */
-         vuint32_t  OPACR4_TP:1;       /* Trusted Protect */
-         vuint32_t  OPACR5_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR5_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR5_WP:1;       /* Write Protect */
-         vuint32_t  OPACR5_TP:1;       /* Trusted Protect */
-         vuint32_t  OPACR6_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR6_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR6_WP:1;       /* Write Protect */
-         vuint32_t  OPACR6_TP:1;       /* Trusted Protect */
-         vuint32_t  OPACR7_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR7_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR7_WP:1;       /* Write Protect */
-         vuint32_t  OPACR7_TP:1;       /* Trusted Protect */
-      } B;
-   } AIPS_OPACR0_7_32B_tag;
-
-   typedef union {   /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR8_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR8_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR8_WP:1;       /* Write Protect */
-         vuint32_t  OPACR8_TP:1;       /* Trusted Protect */
-         vuint32_t  OPACR9_BW:1;       /* Buffer Writes */
-         vuint32_t  OPACR9_SP:1;       /* Supervisor Protect */
-         vuint32_t  OPACR9_WP:1;       /* Write Protect */
-         vuint32_t  OPACR9_TP:1;       /* Trusted Protect */
-         vuint32_t  OPACR10_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR10_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR10_WP:1;      /* Write Protect */
-         vuint32_t  OPACR10_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR11_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR11_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR11_WP:1;      /* Write Protect */
-         vuint32_t  OPACR11_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR12_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR12_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR12_WP:1;      /* Write Protect */
-         vuint32_t  OPACR12_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR13_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR13_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR13_WP:1;      /* Write Protect */
-         vuint32_t  OPACR13_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR14_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR14_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR14_WP:1;      /* Write Protect */
-         vuint32_t  OPACR14_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR15_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR15_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR15_WP:1;      /* Write Protect */
-         vuint32_t  OPACR15_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR8_15_32B_tag;
-
-   typedef union {   /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR16_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR16_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR16_WP:1;      /* Write Protect */
-         vuint32_t  OPACR16_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR17_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR17_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR17_WP:1;      /* Write Protect */
-         vuint32_t  OPACR17_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR18_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR18_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR18_WP:1;      /* Write Protect */
-         vuint32_t  OPACR18_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR19_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR19_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR19_WP:1;      /* Write Protect */
-         vuint32_t  OPACR19_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR20_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR20_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR20_WP:1;      /* Write Protect */
-         vuint32_t  OPACR20_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR21_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR21_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR21_WP:1;      /* Write Protect */
-         vuint32_t  OPACR21_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR22_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR22_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR22_WP:1;      /* Write Protect */
-         vuint32_t  OPACR22_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR23_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR23_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR23_WP:1;      /* Write Protect */
-         vuint32_t  OPACR23_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR16_23_32B_tag;
-
-   typedef union {   /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR24_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR24_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR24_WP:1;      /* Write Protect */
-         vuint32_t  OPACR24_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR25_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR25_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR25_WP:1;      /* Write Protect */
-         vuint32_t  OPACR25_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR26_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR26_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR26_WP:1;      /* Write Protect */
-         vuint32_t  OPACR26_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR27_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR27_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR27_WP:1;      /* Write Protect */
-         vuint32_t  OPACR27_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR28_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR28_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR28_WP:1;      /* Write Protect */
-         vuint32_t  OPACR28_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR29_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR29_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR29_WP:1;      /* Write Protect */
-         vuint32_t  OPACR29_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR30_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR30_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR30_WP:1;      /* Write Protect */
-         vuint32_t  OPACR30_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR31_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR31_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR31_WP:1;      /* Write Protect */
-         vuint32_t  OPACR31_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR24_31_32B_tag;
-
-   typedef union {   /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR32_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR32_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR32_WP:1;      /* Write Protect */
-         vuint32_t  OPACR32_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR33_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR33_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR33_WP:1;      /* Write Protect */
-         vuint32_t  OPACR33_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR34_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR34_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR34_WP:1;      /* Write Protect */
-         vuint32_t  OPACR34_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR35_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR35_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR35_WP:1;      /* Write Protect */
-         vuint32_t  OPACR35_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR36_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR36_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR36_WP:1;      /* Write Protect */
-         vuint32_t  OPACR36_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR37_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR37_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR37_WP:1;      /* Write Protect */
-         vuint32_t  OPACR37_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR38_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR38_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR38_WP:1;      /* Write Protect */
-         vuint32_t  OPACR38_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR39_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR39_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR39_WP:1;      /* Write Protect */
-         vuint32_t  OPACR39_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR32_39_32B_tag;
-
-   typedef union {   /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR40_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR40_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR40_WP:1;      /* Write Protect */
-         vuint32_t  OPACR40_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR41_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR41_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR41_WP:1;      /* Write Protect */
-         vuint32_t  OPACR41_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR42_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR42_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR42_WP:1;      /* Write Protect */
-         vuint32_t  OPACR42_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR43_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR43_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR43_WP:1;      /* Write Protect */
-         vuint32_t  OPACR43_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR44_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR44_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR44_WP:1;      /* Write Protect */
-         vuint32_t  OPACR44_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR45_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR45_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR45_WP:1;      /* Write Protect */
-         vuint32_t  OPACR45_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR46_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR46_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR46_WP:1;      /* Write Protect */
-         vuint32_t  OPACR46_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR47_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR47_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR47_WP:1;      /* Write Protect */
-         vuint32_t  OPACR47_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR40_47_32B_tag;
-
-   typedef union {   /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR48_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR48_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR48_WP:1;      /* Write Protect */
-         vuint32_t  OPACR48_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR49_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR49_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR49_WP:1;      /* Write Protect */
-         vuint32_t  OPACR49_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR50_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR50_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR50_WP:1;      /* Write Protect */
-         vuint32_t  OPACR50_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR51_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR51_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR51_WP:1;      /* Write Protect */
-         vuint32_t  OPACR51_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR52_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR52_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR52_WP:1;      /* Write Protect */
-         vuint32_t  OPACR52_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR53_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR53_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR53_WP:1;      /* Write Protect */
-         vuint32_t  OPACR53_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR54_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR54_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR54_WP:1;      /* Write Protect */
-         vuint32_t  OPACR54_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR55_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR55_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR55_WP:1;      /* Write Protect */
-         vuint32_t  OPACR55_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR48_55_32B_tag;
-
-   typedef union {   /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR56_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR56_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR56_WP:1;      /* Write Protect */
-         vuint32_t  OPACR56_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR57_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR57_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR57_WP:1;      /* Write Protect */
-         vuint32_t  OPACR57_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR58_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR58_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR58_WP:1;      /* Write Protect */
-         vuint32_t  OPACR58_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR59_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR59_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR59_WP:1;      /* Write Protect */
-         vuint32_t  OPACR59_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR60_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR60_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR60_WP:1;      /* Write Protect */
-         vuint32_t  OPACR60_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR61_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR61_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR61_WP:1;      /* Write Protect */
-         vuint32_t  OPACR61_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR62_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR62_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR62_WP:1;      /* Write Protect */
-         vuint32_t  OPACR62_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR63_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR63_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR63_WP:1;      /* Write Protect */
-         vuint32_t  OPACR63_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR56_63_32B_tag;
-
-   typedef union {   /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR64_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR64_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR64_WP:1;      /* Write Protect */
-         vuint32_t  OPACR64_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR65_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR65_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR65_WP:1;      /* Write Protect */
-         vuint32_t  OPACR65_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR66_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR66_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR66_WP:1;      /* Write Protect */
-         vuint32_t  OPACR66_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR67_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR67_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR67_WP:1;      /* Write Protect */
-         vuint32_t  OPACR67_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR68_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR68_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR68_WP:1;      /* Write Protect */
-         vuint32_t  OPACR68_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR69_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR69_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR69_WP:1;      /* Write Protect */
-         vuint32_t  OPACR69_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR70_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR70_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR70_WP:1;      /* Write Protect */
-         vuint32_t  OPACR70_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR71_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR71_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR71_WP:1;      /* Write Protect */
-         vuint32_t  OPACR71_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR64_71_32B_tag;
-
-   typedef union {   /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR72_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR72_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR72_WP:1;      /* Write Protect */
-         vuint32_t  OPACR72_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR73_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR73_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR73_WP:1;      /* Write Protect */
-         vuint32_t  OPACR73_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR74_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR74_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR74_WP:1;      /* Write Protect */
-         vuint32_t  OPACR74_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR75_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR75_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR75_WP:1;      /* Write Protect */
-         vuint32_t  OPACR75_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR76_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR76_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR76_WP:1;      /* Write Protect */
-         vuint32_t  OPACR76_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR77_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR77_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR77_WP:1;      /* Write Protect */
-         vuint32_t  OPACR77_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR78_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR78_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR78_WP:1;      /* Write Protect */
-         vuint32_t  OPACR78_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR79_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR79_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR79_WP:1;      /* Write Protect */
-         vuint32_t  OPACR79_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR72_79_32B_tag;
-
-   typedef union {   /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR80_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR80_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR80_WP:1;      /* Write Protect */
-         vuint32_t  OPACR80_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR81_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR81_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR81_WP:1;      /* Write Protect */
-         vuint32_t  OPACR81_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR82_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR82_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR82_WP:1;      /* Write Protect */
-         vuint32_t  OPACR82_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR83_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR83_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR83_WP:1;      /* Write Protect */
-         vuint32_t  OPACR83_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR84_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR84_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR84_WP:1;      /* Write Protect */
-         vuint32_t  OPACR84_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR85_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR85_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR85_WP:1;      /* Write Protect */
-         vuint32_t  OPACR85_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR86_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR86_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR86_WP:1;      /* Write Protect */
-         vuint32_t  OPACR86_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR87_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR87_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR87_WP:1;      /* Write Protect */
-         vuint32_t  OPACR87_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR80_87_32B_tag;
-
-   typedef union {   /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  OPACR88_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR88_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR88_WP:1;      /* Write Protect */
-         vuint32_t  OPACR88_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR89_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR89_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR89_WP:1;      /* Write Protect */
-         vuint32_t  OPACR89_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR90_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR90_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR90_WP:1;      /* Write Protect */
-         vuint32_t  OPACR90_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR91_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR91_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR91_WP:1;      /* Write Protect */
-         vuint32_t  OPACR91_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR92_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR92_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR92_WP:1;      /* Write Protect */
-         vuint32_t  OPACR92_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR93_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR93_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR93_WP:1;      /* Write Protect */
-         vuint32_t  OPACR93_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR94_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR94_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR94_WP:1;      /* Write Protect */
-         vuint32_t  OPACR94_TP:1;      /* Trusted Protect */
-         vuint32_t  OPACR95_BW:1;      /* Buffer Writes */
-         vuint32_t  OPACR95_SP:1;      /* Supervisor Protect */
-         vuint32_t  OPACR95_WP:1;      /* Write Protect */
-         vuint32_t  OPACR95_TP:1;      /* Trusted Protect */
-      } B;
-   } AIPS_OPACR88_95_32B_tag;
-
-
-
-   typedef struct AIPS_struct_tag { /* start of AIPS_tag */
-                                   /* MPROT - Master Privilege Registers */
-      AIPS_MPROT_32B_tag MPROT;            /* offset: 0x0000 size: 32 bit */
-      int8_t AIPS_reserved_0004[28];
-                        /* PACR0_7 - Peripheral Access Control Registers */
-      AIPS_PACR0_7_32B_tag PACR0_7;        /* offset: 0x0020 size: 32 bit */
-                       /* PACR8_15 - Peripheral Access Control Registers */
-      AIPS_PACR8_15_32B_tag PACR8_15;      /* offset: 0x0024 size: 32 bit */
-                      /* PACR16_23 - Peripheral Access Control Registers */
-      AIPS_PACR16_23_32B_tag PACR16_23;    /* offset: 0x0028 size: 32 bit */
-                      /* PACR24_31 - Peripheral Access Control Registers */
-      AIPS_PACR24_31_32B_tag PACR24_31;    /* offset: 0x002C size: 32 bit */
-      int8_t AIPS_reserved_0030[16];
-          /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR0_7_32B_tag OPACR0_7;      /* offset: 0x0040 size: 32 bit */
-         /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR8_15_32B_tag OPACR8_15;    /* offset: 0x0044 size: 32 bit */
-        /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR16_23_32B_tag OPACR16_23;  /* offset: 0x0048 size: 32 bit */
-        /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR24_31_32B_tag OPACR24_31;  /* offset: 0x004C size: 32 bit */
-        /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR32_39_32B_tag OPACR32_39;  /* offset: 0x0050 size: 32 bit */
-        /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR40_47_32B_tag OPACR40_47;  /* offset: 0x0054 size: 32 bit */
-        /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR48_55_32B_tag OPACR48_55;  /* offset: 0x0058 size: 32 bit */
-        /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR56_63_32B_tag OPACR56_63;  /* offset: 0x005C size: 32 bit */
-        /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR64_71_32B_tag OPACR64_71;  /* offset: 0x0060 size: 32 bit */
-        /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR72_79_32B_tag OPACR72_79;  /* offset: 0x0064 size: 32 bit */
-        /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR80_87_32B_tag OPACR80_87;  /* offset: 0x0068 size: 32 bit */
-        /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
-      AIPS_OPACR88_95_32B_tag OPACR88_95;  /* offset: 0x006C size: 32 bit */
-   } AIPS_tag;
-
-
-#define AIPS  (*(volatile AIPS_tag *) 0xFFF00000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: MAX  */
-/*                                                              */
-/****************************************************************/
-
-
-   /* Register layout for all registers MPR... */
-
-   typedef union {   /* Master Priority Register for slave port n */
-      vuint32_t R;
-      struct {
-         vuint32_t:1;
-         vuint32_t  MSTR_7:3;          /* Master 7 Priority */
-         vuint32_t:1;
-         vuint32_t  MSTR_6:3;          /* Master 6 Priority */
-         vuint32_t:1;
-         vuint32_t  MSTR_5:3;          /* Master 5 Priority */
-         vuint32_t:1;
-         vuint32_t  MSTR_4:3;          /* Master 4 Priority */
-         vuint32_t:1;
-         vuint32_t  MSTR_3:3;          /* Master 3 Priority */
-         vuint32_t:1;
-         vuint32_t  MSTR_2:3;          /* Master 2 Priority */
-         vuint32_t:1;
-         vuint32_t  MSTR_1:3;          /* Master 1 Priority */
-         vuint32_t:1;
-         vuint32_t  MSTR_0:3;          /* Master 0 Priority */
-      } B;
-   } MAX_MPR_32B_tag;
-
-
-   /* Register layout for all registers AMPR matches xxx */
-
-
-   /* Register layout for all registers SGPCR... */
-
-   typedef union {   /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-      vuint32_t R;
-      struct {
-         vuint32_t  RO:1;              /* Read Only */
-         vuint32_t  HLP:1;             /* Halt Low Priority */
-         vuint32_t:6;
-         vuint32_t  HPE7:1;            /* High Priority Enable */
-         vuint32_t  HPE6:1;            /* High Priority Enable */
-         vuint32_t  HPE5:1;            /* High Priority Enable */
-         vuint32_t  HPE4:1;            /* High Priority Enable */
-         vuint32_t  HPE3:1;            /* High Priority Enable */
-         vuint32_t  HPE2:1;            /* High Priority Enable */
-         vuint32_t  HPE1:1;            /* High Priority Enable */
-         vuint32_t  HPE0:1;            /* High Priority Enable */
-         vuint32_t:6;
-         vuint32_t  ARB:2;             /* Arbitration Mode */
-         vuint32_t:2;
-         vuint32_t  PCTL:2;            /* Parking Control */
-         vuint32_t:1;
-         vuint32_t  PARK:3;            /* Park */
-      } B;
-   } MAX_SGPCR_32B_tag;
-
-
-   /* Register layout for all registers ASGPCR... */
-
-   typedef union {   /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-      vuint32_t R;
-      struct {
-         vuint32_t:1;
-         vuint32_t  HLP:1;             /* Halt Low Priority */
-         vuint32_t:6;
-         vuint32_t  HPE7:1;            /* High Priority Enable */
-         vuint32_t  HPE6:1;            /* High Priority Enable */
-         vuint32_t  HPE5:1;            /* High Priority Enable */
-         vuint32_t  HPE4:1;            /* High Priority Enable */
-         vuint32_t  HPE3:1;            /* High Priority Enable */
-         vuint32_t  HPE2:1;            /* High Priority Enable */
-         vuint32_t  HPE1:1;            /* High Priority Enable */
-         vuint32_t  HPE0:1;            /* High Priority Enable */
-         vuint32_t:6;
-         vuint32_t  ARB:2;             /* Arbitration Mode */
-         vuint32_t:2;
-         vuint32_t  PCTL:2;            /* Parking Control */
-         vuint32_t:1;
-         vuint32_t  PARK:3;            /* Park */
-      } B;
-   } MAX_ASGPCR_32B_tag;
-
-
-   /* Register layout for all registers MGPCR... */
-
-   typedef union {   /* MAX_MGPCRn - Master General Purpose Control Register n */
-      vuint32_t R;
-      struct {
-         vuint32_t:29;
-         vuint32_t  AULB:3;            /* Arbitrate on Undefined Length Bursts */
-      } B;
-   } MAX_MGPCR_32B_tag;
-
-
-   typedef struct MAX_SLAVE_PORT_struct_tag {
-
-                            /* Master Priority Register for slave port n */
-      MAX_MPR_32B_tag MPR;                /* relative offset: 0x0000 */
-                  /* Alternate Master Priority Register for slave port n */
-      MAX_MPR_32B_tag AMPR;               /* relative offset: 0x0004 */
-      int8_t MAX_SLAVE_PORT_reserved_0008[8];
-    /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-      MAX_SGPCR_32B_tag SGPCR;            /* relative offset: 0x0010 */
-       /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-      MAX_ASGPCR_32B_tag ASGPCR;          /* relative offset: 0x0014 */
-      int8_t MAX_SLAVE_PORT_reserved_0018[232];
-
-   } MAX_SLAVE_PORT_tag;
-
-   typedef struct MAX_MASTER_PORT_struct_tag {
-
-               /* MAX_MGPCRn - Master General Purpose Control Register n */
-      MAX_MGPCR_32B_tag MGPCR;            /* relative offset: 0x0000 */
-      int8_t MAX_MASTER_PORT_reserved_0004[252];
-
-   } MAX_MASTER_PORT_tag;
-
-
-   typedef struct MAX_struct_tag { /* start of MAX_tag */
-      union {
-                                             /*  Register set SLAVE_PORT */
-         MAX_SLAVE_PORT_tag SLAVE_PORT[8];  /* offset: 0x0000  (0x0100 x 8) */
-
-         struct {
-                            /* Master Priority Register for slave port n */
-            MAX_MPR_32B_tag MPR0;          /* offset: 0x0000 size: 32 bit */
-                  /* Alternate Master Priority Register for slave port n */
-            MAX_MPR_32B_tag AMPR0;         /* offset: 0x0004 size: 32 bit */
-            int8_t MAX_reserved_0008_I1[8];
-          /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-            MAX_SGPCR_32B_tag SGPCR0;      /* offset: 0x0010 size: 32 bit */
-          /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-            MAX_ASGPCR_32B_tag ASGPCR0;    /* offset: 0x0014 size: 32 bit */
-            int8_t MAX_reserved_0018_I1[232];
-                            /* Master Priority Register for slave port n */
-            MAX_MPR_32B_tag MPR1;          /* offset: 0x0100 size: 32 bit */
-                  /* Alternate Master Priority Register for slave port n */
-            MAX_MPR_32B_tag AMPR1;         /* offset: 0x0104 size: 32 bit */
-            int8_t MAX_reserved_0108_I1[8];
-          /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-            MAX_SGPCR_32B_tag SGPCR1;      /* offset: 0x0110 size: 32 bit */
-          /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-            MAX_ASGPCR_32B_tag ASGPCR1;    /* offset: 0x0114 size: 32 bit */
-            int8_t MAX_reserved_0118_I1[232];
-                            /* Master Priority Register for slave port n */
-            MAX_MPR_32B_tag MPR2;          /* offset: 0x0200 size: 32 bit */
-                  /* Alternate Master Priority Register for slave port n */
-            MAX_MPR_32B_tag AMPR2;         /* offset: 0x0204 size: 32 bit */
-            int8_t MAX_reserved_0208_I1[8];
-          /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-            MAX_SGPCR_32B_tag SGPCR2;      /* offset: 0x0210 size: 32 bit */
-          /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-            MAX_ASGPCR_32B_tag ASGPCR2;    /* offset: 0x0214 size: 32 bit */
-            int8_t MAX_reserved_0218_I1[232];
-                            /* Master Priority Register for slave port n */
-            MAX_MPR_32B_tag MPR3;          /* offset: 0x0300 size: 32 bit */
-                  /* Alternate Master Priority Register for slave port n */
-            MAX_MPR_32B_tag AMPR3;         /* offset: 0x0304 size: 32 bit */
-            int8_t MAX_reserved_0308_I1[8];
-          /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-            MAX_SGPCR_32B_tag SGPCR3;      /* offset: 0x0310 size: 32 bit */
-          /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-            MAX_ASGPCR_32B_tag ASGPCR3;    /* offset: 0x0314 size: 32 bit */
-            int8_t MAX_reserved_0318_I1[232];
-                            /* Master Priority Register for slave port n */
-            MAX_MPR_32B_tag MPR4;          /* offset: 0x0400 size: 32 bit */
-                  /* Alternate Master Priority Register for slave port n */
-            MAX_MPR_32B_tag AMPR4;         /* offset: 0x0404 size: 32 bit */
-            int8_t MAX_reserved_0408_I1[8];
-          /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-            MAX_SGPCR_32B_tag SGPCR4;      /* offset: 0x0410 size: 32 bit */
-          /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-            MAX_ASGPCR_32B_tag ASGPCR4;    /* offset: 0x0414 size: 32 bit */
-            int8_t MAX_reserved_0418_I1[232];
-                            /* Master Priority Register for slave port n */
-            MAX_MPR_32B_tag MPR5;          /* offset: 0x0500 size: 32 bit */
-                  /* Alternate Master Priority Register for slave port n */
-            MAX_MPR_32B_tag AMPR5;         /* offset: 0x0504 size: 32 bit */
-            int8_t MAX_reserved_0508_I1[8];
-          /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-            MAX_SGPCR_32B_tag SGPCR5;      /* offset: 0x0510 size: 32 bit */
-          /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-            MAX_ASGPCR_32B_tag ASGPCR5;    /* offset: 0x0514 size: 32 bit */
-            int8_t MAX_reserved_0518_I1[232];
-                            /* Master Priority Register for slave port n */
-            MAX_MPR_32B_tag MPR6;          /* offset: 0x0600 size: 32 bit */
-                  /* Alternate Master Priority Register for slave port n */
-            MAX_MPR_32B_tag AMPR6;         /* offset: 0x0604 size: 32 bit */
-            int8_t MAX_reserved_0608_I1[8];
-          /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-            MAX_SGPCR_32B_tag SGPCR6;      /* offset: 0x0610 size: 32 bit */
-          /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-            MAX_ASGPCR_32B_tag ASGPCR6;    /* offset: 0x0614 size: 32 bit */
-            int8_t MAX_reserved_0618_I1[232];
-                            /* Master Priority Register for slave port n */
-            MAX_MPR_32B_tag MPR7;          /* offset: 0x0700 size: 32 bit */
-                  /* Alternate Master Priority Register for slave port n */
-            MAX_MPR_32B_tag AMPR7;         /* offset: 0x0704 size: 32 bit */
-            int8_t MAX_reserved_0708_I1[8];
-          /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
-            MAX_SGPCR_32B_tag SGPCR7;      /* offset: 0x0710 size: 32 bit */
-          /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
-            MAX_ASGPCR_32B_tag ASGPCR7;    /* offset: 0x0714 size: 32 bit */
-            int8_t MAX_reserved_0718_E1[232];
-         };
-
-      };
-      union {
-                                            /*  Register set MASTER_PORT */
-         MAX_MASTER_PORT_tag MASTER_PORT[8];  /* offset: 0x0800  (0x0100 x 8) */
-
-         struct {
-               /* MAX_MGPCRn - Master General Purpose Control Register n */
-            MAX_MGPCR_32B_tag MGPCR0;      /* offset: 0x0800 size: 32 bit */
-            int8_t MAX_reserved_0804_I1[252];
-            MAX_MGPCR_32B_tag MGPCR1;      /* offset: 0x0900 size: 32 bit */
-            int8_t MAX_reserved_0904_I1[252];
-            MAX_MGPCR_32B_tag MGPCR2;      /* offset: 0x0A00 size: 32 bit */
-            int8_t MAX_reserved_0A04_I1[252];
-            MAX_MGPCR_32B_tag MGPCR3;      /* offset: 0x0B00 size: 32 bit */
-            int8_t MAX_reserved_0B04_I1[252];
-            MAX_MGPCR_32B_tag MGPCR4;      /* offset: 0x0C00 size: 32 bit */
-            int8_t MAX_reserved_0C04_I1[252];
-            MAX_MGPCR_32B_tag MGPCR5;      /* offset: 0x0D00 size: 32 bit */
-            int8_t MAX_reserved_0D04_I1[252];
-            MAX_MGPCR_32B_tag MGPCR6;      /* offset: 0x0E00 size: 32 bit */
-            int8_t MAX_reserved_0E04_I1[252];
-            MAX_MGPCR_32B_tag MGPCR7;      /* offset: 0x0F00 size: 32 bit */
-            int8_t MAX_reserved_0F04_E1[252];
-         };
-
-      };
-   } MAX_tag;
-
-
-#define MAX   (*(volatile MAX_tag *) 0xFFF04000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: MPU  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* MPU_CESR - MPU Control/Error Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  SPERR:8;           /* Slave Port n Error */
-         vuint32_t:4;
-         vuint32_t  HRL:4;             /* Hardware Revision Level */
-         vuint32_t  NSP:4;             /* Number of Slave Ports */
-         vuint32_t  NRGD:4;            /* Number of Region Descriptors */
-         vuint32_t:7;
-         vuint32_t  VLD:1;             /* Valid bit */
-      } B;
-   } MPU_CESR_32B_tag;
-
-
-   /* Register layout for all registers EAR... */
-
-   typedef union {   /* MPU_EARn - MPU Error Address Register, Slave Port n */
-      vuint32_t R;
-      struct {
-         vuint32_t  EADDR:32;          /* Error Address */
-      } B;
-   } MPU_EAR_32B_tag;
-
-
-   /* Register layout for all registers EDR... */
-
-   typedef union {   /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
-      vuint32_t R;
-      struct {
-         vuint32_t  EACD:16;           /* Error Access Control Detail */
-         vuint32_t  EPID:8;            /* Error Process Identification */
-         vuint32_t  EMN:4;             /* Error Master Number */
-         vuint32_t  EATTR:3;           /* Error Attributes */
-         vuint32_t  ERW:1;             /* Error Read/Write */
-      } B;
-   } MPU_EDR_32B_tag;
-
-
-   /* Register layout for all registers RGD_WORD0... */
-
-   typedef union {   /* MPU_RGDn_Word0 - MPU Region Descriptor */
-      vuint32_t R;
-      struct {
-         vuint32_t  SRTADDR:27;        /* Start Address */
-         vuint32_t:5;
-      } B;
-   } MPU_RGD_WORD0_32B_tag;
-
-
-   /* Register layout for all registers RGD_WORD1... */
-
-   typedef union {   /* MPU_RGDn_Word1 - MPU Region Descriptor */
-      vuint32_t R;
-      struct {
-         vuint32_t  ENDADDR:27;        /* End Address */
-         vuint32_t:5;
-      } B;
-   } MPU_RGD_WORD1_32B_tag;
-
-
-   /* Register layout for all registers RGD_WORD2... */
-
-   typedef union {   /* MPU_RGDn_Word2 - MPU Region Descriptor */
-      vuint32_t R;
-      struct {
-         vuint32_t  M7RE:1;            /* Bus Master 7 Read Enable */
-         vuint32_t  M7WE:1;            /* Bus Master 7 Write Enable */
-         vuint32_t  M6RE:1;            /* Bus Master 6 Read Enable */
-         vuint32_t  M6WE:1;            /* Bus Master 7 Write Enable */
-         vuint32_t  M5RE:1;            /* Bus Master 5 Read Enable */
-         vuint32_t  M5WE:1;            /* Bus Master 5 Write Enable */
-         vuint32_t  M4RE:1;            /* Bus Master 4 Read Enable */
-         vuint32_t  M4WE:1;            /* Bus Master 4 Write Enable */
-         vuint32_t  M3PE:1;            /* Bus Master 3 Process Identifier Enable */
-         vuint32_t  M3SM:2;            /* Bus Master 3 Supervisor Mode Access Control */
-         vuint32_t  M3UM:3;            /* Bus Master 3 User Mode Access Control */
-         vuint32_t  M2PE:1;            /* Bus Master 2 Process Identifier Enable */
-         vuint32_t  M2SM:2;            /* Bus Master 2 Supervisor Mode Access Control */
-         vuint32_t  M2UM:3;            /* Bus Master 2 User Mode Access Control */
-         vuint32_t  M1PE:1;            /* Bus Master 1 Process Identifier Enable */
-         vuint32_t  M1SM:2;            /* Bus Master 1 Supervisor Mode Access Control */
-         vuint32_t  M1UM:3;            /* Bus Master 1 User Mode Access Control */
-         vuint32_t  M0PE:1;            /* Bus Master 0 Process Identifier Enable */
-         vuint32_t  M0SM:2;            /* Bus Master 0 Supervisor Mode Access Control */
-         vuint32_t  M0UM:3;            /* Bus Master 0 User Mode Access Control */
-      } B;
-   } MPU_RGD_WORD2_32B_tag;
-
-
-   /* Register layout for all registers RGD_WORD3... */
-
-   typedef union {   /* MPU_RGDn_Word3 - MPU Region Descriptor */
-      vuint32_t R;
-      struct {
-         vuint32_t  PID:8;             /* Process Identifier */
-         vuint32_t  PIDMASK:8;         /* Process Identifier Mask */
-         vuint32_t:15;
-         vuint32_t  VLD:1;             /* Valid */
-      } B;
-   } MPU_RGD_WORD3_32B_tag;
-
-
-   /* Register layout for all registers RGDAAC... */
-
-   typedef union {   /* MPU_RGDAACn -  MPU Region Descriptor Alternate Access Control */
-      vuint32_t R;
-      struct {
-         vuint32_t  M7RE:1;            /* Bus Master 7 Read Enable */
-         vuint32_t  M7WE:1;            /* Bus Master 7 Write Enable */
-         vuint32_t  M6RE:1;            /* Bus Master 6 Read Enable */
-         vuint32_t  M6WE:1;            /* Bus Master 7 Write Enable */
-         vuint32_t  M5RE:1;            /* Bus Master 5 Read Enable */
-         vuint32_t  M5WE:1;            /* Bus Master 5 Write Enable */
-         vuint32_t  M4RE:1;            /* Bus Master 4 Read Enable */
-         vuint32_t  M4WE:1;            /* Bus Master 4 Write Enable */
-         vuint32_t  M3PE:1;            /* Bus Master 3 Process Identifier Enable */
-         vuint32_t  M3SM:2;            /* Bus Master 3 Supervisor Mode Access Control */
-         vuint32_t  M3UM:3;            /* Bus Master 3 User Mode Access Control */
-         vuint32_t  M2PE:1;            /* Bus Master 2 Process Identifier Enable */
-         vuint32_t  M2SM:2;            /* Bus Master 2 Supervisor Mode Access Control */
-         vuint32_t  M2UM:3;            /* Bus Master 2 User Mode Access Control */
-         vuint32_t  M1PE:1;            /* Bus Master 1 Process Identifier Enable */
-         vuint32_t  M1SM:2;            /* Bus Master 1 Supervisor Mode Access Control */
-         vuint32_t  M1UM:3;            /* Bus Master 1 User Mode Access Control */
-         vuint32_t  M0PE:1;            /* Bus Master 0 Process Identifier Enable */
-         vuint32_t  M0SM:2;            /* Bus Master 0 Supervisor Mode Access Control */
-         vuint32_t  M0UM:3;            /* Bus Master 0 User Mode Access Control */
-      } B;
-   } MPU_RGDAAC_32B_tag;
-
-
-   typedef struct MPU_SLAVE_PORT_struct_tag {
-
-                  /* MPU_EARn - MPU Error Address Register, Slave Port n */
-      MPU_EAR_32B_tag EAR;                /* relative offset: 0x0000 */
-                   /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
-      MPU_EDR_32B_tag EDR;                /* relative offset: 0x0004 */
-
-   } MPU_SLAVE_PORT_tag;
-
-   typedef struct MPU_REGION_struct_tag {
-
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-      MPU_RGD_WORD0_32B_tag RGD_WORD0;    /* relative offset: 0x0000 */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-      MPU_RGD_WORD1_32B_tag RGD_WORD1;    /* relative offset: 0x0004 */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-      MPU_RGD_WORD2_32B_tag RGD_WORD2;    /* relative offset: 0x0008 */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-      MPU_RGD_WORD3_32B_tag RGD_WORD3;    /* relative offset: 0x000C */
-
-   } MPU_REGION_tag;
-
-
-   typedef struct MPU_struct_tag { /* start of MPU_tag */
-                         /* MPU_CESR - MPU Control/Error Status Register */
-      MPU_CESR_32B_tag CESR;               /* offset: 0x0000 size: 32 bit */
-      int8_t MPU_reserved_0004_C[12];
-      union {
-                                             /*  Register set SLAVE_PORT */
-         MPU_SLAVE_PORT_tag SLAVE_PORT[4];  /* offset: 0x0010  (0x0008 x 4) */
-
-         struct {
-                  /* MPU_EARn - MPU Error Address Register, Slave Port n */
-            MPU_EAR_32B_tag EAR0;          /* offset: 0x0010 size: 32 bit */
-                   /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
-            MPU_EDR_32B_tag EDR0;          /* offset: 0x0014 size: 32 bit */
-                  /* MPU_EARn - MPU Error Address Register, Slave Port n */
-            MPU_EAR_32B_tag EAR1;          /* offset: 0x0018 size: 32 bit */
-                   /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
-            MPU_EDR_32B_tag EDR1;          /* offset: 0x001C size: 32 bit */
-                  /* MPU_EARn - MPU Error Address Register, Slave Port n */
-            MPU_EAR_32B_tag EAR2;          /* offset: 0x0020 size: 32 bit */
-                   /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
-            MPU_EDR_32B_tag EDR2;          /* offset: 0x0024 size: 32 bit */
-                  /* MPU_EARn - MPU Error Address Register, Slave Port n */
-            MPU_EAR_32B_tag EAR3;          /* offset: 0x0028 size: 32 bit */
-                   /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
-            MPU_EDR_32B_tag EDR3;          /* offset: 0x002C size: 32 bit */
-         };
-
-      };
-      int8_t MPU_reserved_0030_C[976];
-      union {
-                                                 /*  Register set REGION */
-         MPU_REGION_tag REGION[16];        /* offset: 0x0400  (0x0010 x 16) */
-
-         struct {
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD0_WORD0;  /* offset: 0x0400 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD0_WORD1;  /* offset: 0x0404 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD0_WORD2;  /* offset: 0x0408 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD0_WORD3;  /* offset: 0x040C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD1_WORD0;  /* offset: 0x0410 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD1_WORD1;  /* offset: 0x0414 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD1_WORD2;  /* offset: 0x0418 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD1_WORD3;  /* offset: 0x041C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD2_WORD0;  /* offset: 0x0420 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD2_WORD1;  /* offset: 0x0424 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD2_WORD2;  /* offset: 0x0428 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD2_WORD3;  /* offset: 0x042C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD3_WORD0;  /* offset: 0x0430 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD3_WORD1;  /* offset: 0x0434 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD3_WORD2;  /* offset: 0x0438 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD3_WORD3;  /* offset: 0x043C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD4_WORD0;  /* offset: 0x0440 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD4_WORD1;  /* offset: 0x0444 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD4_WORD2;  /* offset: 0x0448 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD4_WORD3;  /* offset: 0x044C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD5_WORD0;  /* offset: 0x0450 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD5_WORD1;  /* offset: 0x0454 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD5_WORD2;  /* offset: 0x0458 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD5_WORD3;  /* offset: 0x045C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD6_WORD0;  /* offset: 0x0460 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD6_WORD1;  /* offset: 0x0464 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD6_WORD2;  /* offset: 0x0468 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD6_WORD3;  /* offset: 0x046C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD7_WORD0;  /* offset: 0x0470 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD7_WORD1;  /* offset: 0x0474 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD7_WORD2;  /* offset: 0x0478 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD7_WORD3;  /* offset: 0x047C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD8_WORD0;  /* offset: 0x0480 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD8_WORD1;  /* offset: 0x0484 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD8_WORD2;  /* offset: 0x0488 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD8_WORD3;  /* offset: 0x048C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD9_WORD0;  /* offset: 0x0490 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD9_WORD1;  /* offset: 0x0494 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD9_WORD2;  /* offset: 0x0498 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD9_WORD3;  /* offset: 0x049C size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD10_WORD0;  /* offset: 0x04A0 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD10_WORD1;  /* offset: 0x04A4 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD10_WORD2;  /* offset: 0x04A8 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD10_WORD3;  /* offset: 0x04AC size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD11_WORD0;  /* offset: 0x04B0 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD11_WORD1;  /* offset: 0x04B4 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD11_WORD2;  /* offset: 0x04B8 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD11_WORD3;  /* offset: 0x04BC size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD12_WORD0;  /* offset: 0x04C0 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD12_WORD1;  /* offset: 0x04C4 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD12_WORD2;  /* offset: 0x04C8 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD12_WORD3;  /* offset: 0x04CC size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD13_WORD0;  /* offset: 0x04D0 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD13_WORD1;  /* offset: 0x04D4 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD13_WORD2;  /* offset: 0x04D8 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD13_WORD3;  /* offset: 0x04DC size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD14_WORD0;  /* offset: 0x04E0 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD14_WORD1;  /* offset: 0x04E4 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD14_WORD2;  /* offset: 0x04E8 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD14_WORD3;  /* offset: 0x04EC size: 32 bit */
-                               /* MPU_RGDn_Word0 - MPU Region Descriptor */
-            MPU_RGD_WORD0_32B_tag RGD15_WORD0;  /* offset: 0x04F0 size: 32 bit */
-                               /* MPU_RGDn_Word1 - MPU Region Descriptor */
-            MPU_RGD_WORD1_32B_tag RGD15_WORD1;  /* offset: 0x04F4 size: 32 bit */
-                               /* MPU_RGDn_Word2 - MPU Region Descriptor */
-            MPU_RGD_WORD2_32B_tag RGD15_WORD2;  /* offset: 0x04F8 size: 32 bit */
-                               /* MPU_RGDn_Word3 - MPU Region Descriptor */
-            MPU_RGD_WORD3_32B_tag RGD15_WORD3;  /* offset: 0x04FC size: 32 bit */
-         };
-
-      };
-      int8_t MPU_reserved_0500_C[768];
-      union {
-        /* MPU_RGDAACn -  MPU Region Descriptor Alternate Access Control */
-         MPU_RGDAAC_32B_tag RGDAAC[16];    /* offset: 0x0800  (0x0004 x 16) */
-
-         struct {
-        /* MPU_RGDAACn -  MPU Region Descriptor Alternate Access Control */
-            MPU_RGDAAC_32B_tag RGDAAC0;    /* offset: 0x0800 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC1;    /* offset: 0x0804 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC2;    /* offset: 0x0808 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC3;    /* offset: 0x080C size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC4;    /* offset: 0x0810 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC5;    /* offset: 0x0814 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC6;    /* offset: 0x0818 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC7;    /* offset: 0x081C size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC8;    /* offset: 0x0820 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC9;    /* offset: 0x0824 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC10;   /* offset: 0x0828 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC11;   /* offset: 0x082C size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC12;   /* offset: 0x0830 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC13;   /* offset: 0x0834 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC14;   /* offset: 0x0838 size: 32 bit */
-            MPU_RGDAAC_32B_tag RGDAAC15;   /* offset: 0x083C size: 32 bit */
-         };
-
-      };
-   } MPU_tag;
-
-
-#define MPU   (*(volatile MPU_tag *) 0xFFF10000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: SEMA4  */
-/*                                                              */
-/****************************************************************/
-
-
-   /* Register layout for all registers GATE... */
-
-   typedef union {   /* SEMA4_GATEn - Semephores Gate Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:6;
-         vuint8_t   GTFSM:2;           /* Gate Finite State machine */
-      } B;
-   } SEMA4_GATE_8B_tag;
-
-   typedef union {   /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
-      vuint16_t R;
-      struct {
-         vuint16_t  INE:16;            /* Interrupt Request Notification Enable */
-      } B;
-   } SEMA4_CP0INE_16B_tag;
-
-   typedef union {   /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
-      vuint16_t R;
-      struct {
-         vuint16_t  INE:16;            /* Interrupt Request Notification Enable */
-      } B;
-   } SEMA4_CP1INE_16B_tag;
-
-   typedef union {   /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
-      vuint16_t R;
-      struct {
-         vuint16_t  GN:16;             /* Gate 0 Notification */
-      } B;
-   } SEMA4_CP0NTF_16B_tag;
-
-   typedef union {   /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
-      vuint16_t R;
-      struct {
-         vuint16_t  GN:16;             /* Gate 1 Notification */
-      } B;
-   } SEMA4_CP1NTF_16B_tag;
-
-   typedef union {   /* SEMA4_RSTGT -  Semaphores Reset Gate */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  RSTGSM:2;          /* Reset Gate Finite State Machine */
-         vuint16_t  RSTGDP:7;          /* Reset Gate Data Pattern */
-         vuint16_t  RSTGMS:3;          /* Reset Gate Bus Master */
-         vuint16_t  RSTGTN:8;          /* Reset Gate Number */
-      } B;
-   } SEMA4_RSTGT_16B_tag;
-
-   typedef union {   /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  RSTNSM:2;          /* Reset Gate Finite State Machine */
-         vuint16_t  RSTNDP:7;          /* Reset Gate Data Pattern */
-         vuint16_t  RSTNMS:3;          /* Reset Gate Bus Master */
-         vuint16_t  RSTNTN:8;          /* Reset Gate Number */
-      } B;
-   } SEMA4_RSTNTF_16B_tag;
-
-
-
-   typedef struct SEMA4_struct_tag { /* start of SEMA4_tag */
-      union {
-                               /* SEMA4_GATEn - Semephores Gate Register */
-         SEMA4_GATE_8B_tag GATE[16];       /* offset: 0x0000  (0x0001 x 16) */
-
-         struct {
-                               /* SEMA4_GATEn - Semephores Gate Register */
-            SEMA4_GATE_8B_tag GATE0;       /* offset: 0x0000 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE1;       /* offset: 0x0001 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE2;       /* offset: 0x0002 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE3;       /* offset: 0x0003 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE4;       /* offset: 0x0004 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE5;       /* offset: 0x0005 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE6;       /* offset: 0x0006 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE7;       /* offset: 0x0007 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE8;       /* offset: 0x0008 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE9;       /* offset: 0x0009 size: 8 bit */
-            SEMA4_GATE_8B_tag GATE10;      /* offset: 0x000A size: 8 bit */
-            SEMA4_GATE_8B_tag GATE11;      /* offset: 0x000B size: 8 bit */
-            SEMA4_GATE_8B_tag GATE12;      /* offset: 0x000C size: 8 bit */
-            SEMA4_GATE_8B_tag GATE13;      /* offset: 0x000D size: 8 bit */
-            SEMA4_GATE_8B_tag GATE14;      /* offset: 0x000E size: 8 bit */
-            SEMA4_GATE_8B_tag GATE15;      /* offset: 0x000F size: 8 bit */
-         };
-
-      };
-      int8_t SEMA4_reserved_0010[48];
-          /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
-      SEMA4_CP0INE_16B_tag CP0INE;         /* offset: 0x0040 size: 16 bit */
-      int8_t SEMA4_reserved_0042[6];
-          /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
-      SEMA4_CP1INE_16B_tag CP1INE;         /* offset: 0x0048 size: 16 bit */
-      int8_t SEMA4_reserved_004A[54];
-                 /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
-      SEMA4_CP0NTF_16B_tag CP0NTF;         /* offset: 0x0080 size: 16 bit */
-      int8_t SEMA4_reserved_0082[6];
-                 /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
-      SEMA4_CP1NTF_16B_tag CP1NTF;         /* offset: 0x0088 size: 16 bit */
-      int8_t SEMA4_reserved_008A[118];
-                                 /* SEMA4_RSTGT -  Semaphores Reset Gate */
-      SEMA4_RSTGT_16B_tag RSTGT;           /* offset: 0x0100 size: 16 bit */
-      int8_t SEMA4_reserved_0102[2];
-               /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
-      SEMA4_RSTNTF_16B_tag RSTNTF;         /* offset: 0x0104 size: 16 bit */
-   } SEMA4_tag;
-
-
-#define SEMA4 (*(volatile SEMA4_tag *) 0xFFF24000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: SWT  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* SWT_CR - Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  MAP0:1;            /* Master Acces Protection for Master 0 */
-         vuint32_t  MAP1:1;            /* Master Acces Protection for Master 1 */
-         vuint32_t  MAP2:1;            /* Master Acces Protection for Master 2 */
-         vuint32_t  MAP3:1;            /* Master Acces Protection for Master 3 */
-         vuint32_t  MAP4:1;            /* Master Acces Protection for Master 4 */
-         vuint32_t  MAP5:1;            /* Master Acces Protection for Master 5 */
-         vuint32_t  MAP6:1;            /* Master Acces Protection for Master 6 */
-         vuint32_t  MAP7:1;            /* Master Acces Protection for Master 7 */
-         vuint32_t:14;
-         vuint32_t  KEY:1;             /* Keyed Service Mode */
-         vuint32_t  RIA:1;             /* Reset on Invalid Access */
-         vuint32_t  WND:1;             /* Window Mode */
-         vuint32_t  ITR:1;             /* Interrupt Then Reset */
-         vuint32_t  HLK:1;             /* Hard Lock */
-         vuint32_t  SLK:1;             /* Soft Lock */
-         vuint32_t  CSL:1;             /* Clock Selection */
-         vuint32_t  STP:1;             /* Stop Mode Control */
-         vuint32_t  FRZ:1;             /* Debug Mode Control */
-         vuint32_t  WEN:1;             /* Watchdog Enabled */
-      } B;
-   } SWT_CR_32B_tag;
-
-   typedef union {   /* SWT_IR - SWT Interrupt Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:31;
-         vuint32_t  TIF:1;             /* Time Out Interrupt Flag */
-      } B;
-   } SWT_IR_32B_tag;
-
-   typedef union {   /* SWT_TO - SWT Time-Out Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  WTO:32;            /* Watchdog Time Out Period */
-      } B;
-   } SWT_TO_32B_tag;
-
-   typedef union {   /* SWT_WN - SWT Window Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  WST:32;            /* Watchdog Time Out Period */
-      } B;
-   } SWT_WN_32B_tag;
-
-   typedef union {   /* SWT_SR - SWT Service Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  WSC:16;            /* Watchdog Service Code */
-      } B;
-   } SWT_SR_32B_tag;
-
-   typedef union {   /* SWT_CO - SWT Counter Output Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  CNT:32;            /* Watchdog Count */
-      } B;
-   } SWT_CO_32B_tag;
-
-   typedef union {   /* SWT_SK - SWT Service Key Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  SERVICEKEY:16;     /* Service Key */
-      } B;
-   } SWT_SK_32B_tag;
-
-
-
-   typedef struct SWT_struct_tag { /* start of SWT_tag */
-                                            /* SWT_CR - Control Register */
-      SWT_CR_32B_tag CR;                   /* offset: 0x0000 size: 32 bit */
-                                      /* SWT_IR - SWT Interrupt Register */
-      SWT_IR_32B_tag IR;                   /* offset: 0x0004 size: 32 bit */
-                                       /* SWT_TO - SWT Time-Out Register */
-      SWT_TO_32B_tag TO;                   /* offset: 0x0008 size: 32 bit */
-                                         /* SWT_WN - SWT Window Register */
-      SWT_WN_32B_tag WN;                   /* offset: 0x000C size: 32 bit */
-                                        /* SWT_SR - SWT Service Register */
-      SWT_SR_32B_tag SR;                   /* offset: 0x0010 size: 32 bit */
-                                 /* SWT_CO - SWT Counter Output Register */
-      SWT_CO_32B_tag CO;                   /* offset: 0x0014 size: 32 bit */
-                                    /* SWT_SK - SWT Service Key Register */
-      SWT_SK_32B_tag SK;                   /* offset: 0x0018 size: 32 bit */
-   } SWT_tag;
-
-
-#define SWT   (*(volatile SWT_tag *) 0xFFF38000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: STM  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* STM_CR - Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  CPS:8;             /* Counter Prescaler */
-         vuint32_t:6;
-         vuint32_t  FRZ:1;             /* Freeze Control */
-         vuint32_t  TEN:1;             /* Timer Counter Enabled */
-      } B;
-   } STM_CR_32B_tag;
-
-   typedef union {   /* STM_CNT - STM Count Register */
-      vuint32_t R;
-   } STM_CNT_32B_tag;
-
-
-   /* Register layout for all registers CCR... */
-
-   typedef union {   /* STM_CCRn - STM Channel Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:31;
-         vuint32_t  CEN:1;             /* Channel Enable */
-      } B;
-   } STM_CCR_32B_tag;
-
-
-   /* Register layout for all registers CIR... */
-
-   typedef union {   /* STM_CIRn - STM Channel Interrupt Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:31;
-         vuint32_t  CIF:1;             /* Channel Interrupt Flag */
-      } B;
-   } STM_CIR_32B_tag;
-
-
-   /* Register layout for all registers CMP... */
-
-   typedef union {   /* STM_CMPn - STM Channel Compare Register */
-      vuint32_t R;
-   } STM_CMP_32B_tag;
-
-
-   typedef struct STM_CHANNEL_struct_tag {
-
-                              /* STM_CCRn - STM Channel Control Register */
-      STM_CCR_32B_tag CCR;                /* relative offset: 0x0000 */
-                            /* STM_CIRn - STM Channel Interrupt Register */
-      STM_CIR_32B_tag CIR;                /* relative offset: 0x0004 */
-                              /* STM_CMPn - STM Channel Compare Register */
-      STM_CMP_32B_tag CMP;                /* relative offset: 0x0008 */
-      int8_t STM_CHANNEL_reserved_000C[4];
-
-   } STM_CHANNEL_tag;
-
-
-   typedef struct STM_struct_tag { /* start of STM_tag */
-      union {
-         STM_CR_32B_tag CR0;               /* deprecated - please avoid */
-
-                                            /* STM_CR - Control Register */
-         STM_CR_32B_tag CR;                /* offset: 0x0000 size: 32 bit */
-
-      };
-      union {
-         STM_CNT_32B_tag CNT0;             /* deprecated - please avoid */
-
-                                         /* STM_CNT - STM Count Register */
-         STM_CNT_32B_tag CNT;              /* offset: 0x0004 size: 32 bit */
-
-      };
-      int8_t STM_reserved_0008_C[8];
-      union {
-                                                /*  Register set CHANNEL */
-         STM_CHANNEL_tag CHANNEL[4];       /* offset: 0x0010  (0x0010 x 4) */
-
-         struct {
-                              /* STM_CCRn - STM Channel Control Register */
-            STM_CCR_32B_tag CCR0;          /* offset: 0x0010 size: 32 bit */
-                            /* STM_CIRn - STM Channel Interrupt Register */
-            STM_CIR_32B_tag CIR0;          /* offset: 0x0014 size: 32 bit */
-                              /* STM_CMPn - STM Channel Compare Register */
-            STM_CMP_32B_tag CMP0;          /* offset: 0x0018 size: 32 bit */
-            int8_t STM_reserved_001C_I1[4];
-                              /* STM_CCRn - STM Channel Control Register */
-            STM_CCR_32B_tag CCR1;          /* offset: 0x0020 size: 32 bit */
-                            /* STM_CIRn - STM Channel Interrupt Register */
-            STM_CIR_32B_tag CIR1;          /* offset: 0x0024 size: 32 bit */
-                              /* STM_CMPn - STM Channel Compare Register */
-            STM_CMP_32B_tag CMP1;          /* offset: 0x0028 size: 32 bit */
-            int8_t STM_reserved_002C_I1[4];
-                              /* STM_CCRn - STM Channel Control Register */
-            STM_CCR_32B_tag CCR2;          /* offset: 0x0030 size: 32 bit */
-                            /* STM_CIRn - STM Channel Interrupt Register */
-            STM_CIR_32B_tag CIR2;          /* offset: 0x0034 size: 32 bit */
-                              /* STM_CMPn - STM Channel Compare Register */
-            STM_CMP_32B_tag CMP2;          /* offset: 0x0038 size: 32 bit */
-            int8_t STM_reserved_003C_I1[4];
-                              /* STM_CCRn - STM Channel Control Register */
-            STM_CCR_32B_tag CCR3;          /* offset: 0x0040 size: 32 bit */
-                            /* STM_CIRn - STM Channel Interrupt Register */
-            STM_CIR_32B_tag CIR3;          /* offset: 0x0044 size: 32 bit */
-                              /* STM_CMPn - STM Channel Compare Register */
-            STM_CMP_32B_tag CMP3;          /* offset: 0x0048 size: 32 bit */
-            int8_t STM_reserved_004C_E1[4];
-         };
-
-      };
-   } STM_tag;
-
-
-#define STM   (*(volatile STM_tag *) 0xFFF3C000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: SPP_MCM  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* SPP_MCM_PCT - Processor Core Type */
-      vuint16_t R;
-      struct {
-         vuint16_t  PCTYPE:16;         /* Processor Core Type */
-      } B;
-   } SPP_MCM_PCT_16B_tag;
-
-   typedef union {   /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
-      vuint16_t R;
-      struct {
-         vuint16_t  PLREVISION:16;     /* Platform Revision */
-      } B;
-   } SPP_MCM_PLREV_16B_tag;
-
-   typedef union {   /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
-      vuint32_t R;
-      struct {
-         vuint32_t  PMC:32;            /* IPS Module Configuration */
-      } B;
-   } SPP_MCM_IOPMC_32B_tag;
-
-   typedef union {   /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
-      vuint8_t R;
-      struct {
-         vuint8_t   POR:1;             /* Power on Reset */
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   OFPLR:1;           /* Off-Platform Reset */
-#else
-         vuint8_t   DIR:1;               /* deprecated name - please avoid */
-#endif
-         vuint8_t:6;
-      } B;
-   } SPP_MCM_MRSR_8B_tag;
-
-   typedef union {   /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
-      vuint8_t R;
-      struct {
-         vuint8_t   ENBWCR:1;          /* Enable WCR */
-         vuint8_t:3;
-         vuint8_t   PRILVL:4;          /* Interrupt Priority Level */
-      } B;
-   } SPP_MCM_MWCR_8B_tag;
-
-   typedef union {   /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
-      vuint8_t R;
-      struct {
-         vuint8_t   FB0AI:1;           /* Flash Bank 0 Abort Interrupt */
-         vuint8_t   FB0SI:1;           /* Flash Bank 0 Stall Interrupt */
-         vuint8_t   FB1AI:1;           /* Flash Bank 1 Abort Interrupt */
-         vuint8_t   FB1SI:1;           /* Flash Bank 1 Stall Interrupt */
-         vuint8_t   FB2AI:1;           /* Flash Bank 2 Abort Interrupt */
-         vuint8_t   FB2SI:1;           /* Flash Bank 2 Stall Interrupt */
-         vuint8_t:2;
-      } B;
-   } SPP_MCM_MIR_8B_tag;
-
-   typedef union {   /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  MUSERDCR:32;       /* User Defined Control Register */
-      } B;
-   } SPP_MCM_MUDCR_32B_tag;
-
-   typedef union {   /* SPP_MCM_ECR - ECC Configuration Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:2;
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   EPR1BR:1;          /* Enable Platform RAM 1-bit Reporting */
-#else
-         vuint8_t   ER1BR:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   EPF1BR:1;          /* Enable Platform FLASH 1-bit Reporting */
-#else
-         vuint8_t   EF1BR:1;             /* deprecated name - please avoid */
-#endif
-         vuint8_t:2;
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   EPRNCR:1;          /* Enable Platform RAM Non-Correctable Reporting */
-#else
-         vuint8_t   ERNCR:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   EPFNCR:1;          /* Enable Platform FLASH Non-Correctable Reporting */
-#else
-         vuint8_t   EFNCR:1;             /* deprecated name - please avoid */
-#endif
-      } B;
-   } SPP_MCM_ECR_8B_tag;
-
-   typedef union {   /* SPP_MCM_ESR - ECC Status Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:2;
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   PR1BC:1;           /* Platform RAM 1-bit Correction */
-#else
-         vuint8_t   R1BC:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   PF1BC:1;           /* Platform FLASH 1-bit Correction */
-#else
-         vuint8_t   F1BC:1;              /* deprecated name - please avoid */
-#endif
-         vuint8_t:2;
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   PRNCE:1;           /* Platform RAM Non-Correctable Error */
-#else
-         vuint8_t   RNCE:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   PFNCE:1;           /* Platform FLASH Non-Correctable Error */
-#else
-         vuint8_t   FNCE:1;              /* deprecated name - please avoid */
-#endif
-      } B;
-   } SPP_MCM_ESR_8B_tag;
-
-   typedef union {   /* SPP_MCM_EEGR - ECC Error Generation Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  FRCAP:1;           /* Force Platform RAM Error Injection Access Protection */
-         vuint16_t:1;
-         vuint16_t  FRC1BI:1;          /* Force Platform RAM Continuous 1-Bit Data Inversions */
-         vuint16_t  FR11BI:1;          /* Force Platform RAM One 1-Bit Data Inversion */
-         vuint16_t:2;
-         vuint16_t  FRCNCI:1;          /* Force Platform RAM Continuous Noncorrectable Data Inversions */
-         vuint16_t  FR1NCI:1;          /* Force Platform RAM One Noncorrectable Data Inversions */
-         vuint16_t:1;
-         vuint16_t  ERRBIT:7;          /* Error Bit Position */
-      } B;
-   } SPP_MCM_EEGR_16B_tag;
-
-   typedef union {   /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
-      vuint32_t R;
-   } SPP_MCM_PFEAR_32B_tag;
-
-   typedef union {   /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
-      vuint8_t R;
-   } SPP_MCM_PFEMR_8B_tag;
-
-   typedef union {   /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
-      vuint8_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   F_WRITE:1;         /* AMBA-AHBH Write */
-#else
-         vuint8_t   WRITE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   F_SIZE:3;          /* AMBA-AHBH Size */
-#else
-         vuint8_t   SIZE:3;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   F_PROTECT:4;       /* AMBA-AHBH PROT */
-#else
-         vuint8_t   PROTECTION:4;        /* deprecated name - please avoid */
-#endif
-      } B;
-   } SPP_MCM_PFEAT_8B_tag;
-
-   typedef union {   /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
-      vuint32_t R;
-   } SPP_MCM_PFEDRH_32B_tag;
-
-   typedef union {   /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
-      vuint32_t R;
-   } SPP_MCM_PFEDR_32B_tag;
-
-   typedef union {   /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
-      vuint32_t R;
-   } SPP_MCM_PREAR_32B_tag;
-
-   typedef union {   /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
-      vuint8_t R;
-   } SPP_MCM_PRESR_8B_tag;
-
-   typedef union {   /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:4;
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   PR_EMR:4;          /* Platform RAM ECC Master Number */
-#else
-         vuint8_t   REMR:4;              /* deprecated name - please avoid */
-#endif
-      } B;
-   } SPP_MCM_PREMR_8B_tag;
-
-   typedef union {   /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
-      vuint8_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   R_WRITE:1;         /* AMBA-AHBH Write */
-#else
-         vuint8_t   WRITE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   R_SIZE:3;          /* AMBA-AHBH Size */
-#else
-         vuint8_t   SIZE:3;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_SPP_MCM
-         vuint8_t   R_PROTECT:4;       /* AMBA-AHBH PROT */
-#else
-         vuint8_t   PROTECTION:4;        /* deprecated name - please avoid */
-#endif
-      } B;
-   } SPP_MCM_PREAT_8B_tag;
-
-   typedef union {   /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
-      vuint32_t R;
-   } SPP_MCM_PREDRH_32B_tag;
-
-   typedef union {   /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
-      vuint32_t R;
-   } SPP_MCM_PREDR_32B_tag;
-
-
-
-   typedef struct SPP_MCM_struct_tag { /* start of SPP_MCM_tag */
-                                    /* SPP_MCM_PCT - Processor Core Type */
-      SPP_MCM_PCT_16B_tag PCT;             /* offset: 0x0000 size: 16 bit */
-      union {
-         SPP_MCM_PLREV_16B_tag REV;        /* deprecated - please avoid */
-
-                        /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
-         SPP_MCM_PLREV_16B_tag PLREV;      /* offset: 0x0002 size: 16 bit */
-
-      };
-      int8_t SPP_MCM_reserved_0004_C[4];
-      union {
-         SPP_MCM_IOPMC_32B_tag MC;         /* deprecated - please avoid */
-
-                 /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
-         SPP_MCM_IOPMC_32B_tag IOPMC;      /* offset: 0x0008 size: 32 bit */
-
-      };
-      int8_t SPP_MCM_reserved_000C[3];
-                   /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
-      SPP_MCM_MRSR_8B_tag MRSR;            /* offset: 0x000F size: 8 bit */
-      int8_t SPP_MCM_reserved_0010[3];
-                 /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
-      SPP_MCM_MWCR_8B_tag MWCR;            /* offset: 0x0013 size: 8 bit */
-      int8_t SPP_MCM_reserved_0014[11];
-                       /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
-      SPP_MCM_MIR_8B_tag MIR;              /* offset: 0x001F size: 8 bit */
-      int8_t SPP_MCM_reserved_0020[4];
-          /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
-      SPP_MCM_MUDCR_32B_tag MUDCR;         /* offset: 0x0024 size: 32 bit */
-      int8_t SPP_MCM_reserved_0028[27];
-                             /* SPP_MCM_ECR - ECC Configuration Register */
-      SPP_MCM_ECR_8B_tag ECR;              /* offset: 0x0043 size: 8 bit */
-      int8_t SPP_MCM_reserved_0044[3];
-                                    /* SPP_MCM_ESR - ECC Status Register */
-      SPP_MCM_ESR_8B_tag ESR;              /* offset: 0x0047 size: 8 bit */
-      int8_t SPP_MCM_reserved_0048[2];
-                         /* SPP_MCM_EEGR - ECC Error Generation Register */
-      SPP_MCM_EEGR_16B_tag EEGR;           /* offset: 0x004A size: 16 bit */
-      int8_t SPP_MCM_reserved_004C_C[4];
-      union {
-            /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
-         SPP_MCM_PFEAR_32B_tag PFEAR;      /* offset: 0x0050 size: 32 bit */
-
-         SPP_MCM_PFEAR_32B_tag FEAR;       /* deprecated - please avoid */
-
-      };
-      int8_t SPP_MCM_reserved_0054_C[2];
-      union {
-            /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
-         SPP_MCM_PFEMR_8B_tag PFEMR;       /* offset: 0x0056 size: 8 bit */
-
-         SPP_MCM_PFEMR_8B_tag FEMR;        /* deprecated - please avoid */
-
-      };
-      union {
-               /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
-         SPP_MCM_PFEAT_8B_tag PFEAT;       /* offset: 0x0057 size: 8 bit */
-
-         SPP_MCM_PFEAT_8B_tag FEAT;        /* deprecated - please avoid */
-
-      };
-          /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
-      SPP_MCM_PFEDRH_32B_tag PFEDRH;       /* offset: 0x0058 size: 32 bit */
-      union {
-                     /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
-         SPP_MCM_PFEDR_32B_tag PFEDR;      /* offset: 0x005C size: 32 bit */
-
-         SPP_MCM_PFEDR_32B_tag FEDR;       /* deprecated - please avoid */
-
-      };
-      union {
-         SPP_MCM_PREAR_32B_tag REAR;       /* deprecated - please avoid */
-
-                    /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
-         SPP_MCM_PREAR_32B_tag PREAR;      /* offset: 0x0060 size: 32 bit */
-
-      };
-      int8_t SPP_MCM_reserved_0064_C;
-      union {
-         SPP_MCM_PRESR_8B_tag RESR;        /* deprecated - please avoid */
-
-                   /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
-         SPP_MCM_PRESR_8B_tag PRESR;       /* offset: 0x0065 size: 8 bit */
-
-      };
-      union {
-         SPP_MCM_PREMR_8B_tag REMR;        /* deprecated - please avoid */
-
-              /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
-         SPP_MCM_PREMR_8B_tag PREMR;       /* offset: 0x0066 size: 8 bit */
-
-      };
-      union {
-         SPP_MCM_PREAT_8B_tag REAT;        /* deprecated - please avoid */
-
-                 /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
-         SPP_MCM_PREAT_8B_tag PREAT;       /* offset: 0x0067 size: 8 bit */
-
-      };
-             /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
-      SPP_MCM_PREDRH_32B_tag PREDRH;       /* offset: 0x0068 size: 32 bit */
-      union {
-         SPP_MCM_PREDR_32B_tag REDR;       /* deprecated - please avoid */
-
-                       /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
-         SPP_MCM_PREDR_32B_tag PREDR;      /* offset: 0x006C size: 32 bit */
-
-      };
-   } SPP_MCM_tag;
-
-
-#define SPP_MCM (*(volatile SPP_MCM_tag *) 0xFFF40000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: SPP_DMA2  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* SPP_DMA2_DMACR - DMA Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:14;
-         vuint32_t  CX:1;              /* Cancel Transfer */
-         vuint32_t  ECX:1;             /* Error Cancel Transfer */
-         vuint32_t  GRP3PRI:2;         /* Channel Group 3 Priority */
-         vuint32_t  GRP2PRI:2;         /* Channel Group 2 Priority */
-         vuint32_t  GRP1PRI:2;         /* Channel Group 1 Priority */
-         vuint32_t  GRP0PRI:2;         /* Channel Group 0 Priority */
-         vuint32_t  EMLM:1;            /* Enable Minor Loop Mapping */
-         vuint32_t  CLM:1;             /* Continuous Link Mode */
-         vuint32_t  HALT:1;            /* Halt DMA Operations */
-         vuint32_t  HOE:1;             /* Halt on Error */
-         vuint32_t  ERGA:1;            /* Enable Round Robin Group Arbitration */
-         vuint32_t  ERCA:1;            /* Enable Round Robin Channel Arbitration */
-         vuint32_t  EDBG:1;            /* Enable Debug */
-         vuint32_t  EBW:1;             /* Enable Buffered Writes */
-      } B;
-   } SPP_DMA2_DMACR_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAES - DMA Error Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  VLD:1;             /* Logical OR of DMAERRH and DMAERRL status bits */
-         vuint32_t:14;
-         vuint32_t  ECX:1;             /* Transfer Cancelled */
-         vuint32_t  GPE:1;             /* Group Priority Error */
-         vuint32_t  CPE:1;             /* Channel Priority Error */
-         vuint32_t  ERRCHN:6;          /* Error Channel Number or Cancelled Channel Number */
-         vuint32_t  SAE:1;             /* Source Address Error */
-         vuint32_t  SOE:1;             /* Source Offset Error */
-         vuint32_t  DAE:1;             /* Destination Address Error */
-         vuint32_t  DOE:1;             /* Destination Offset Error */
-         vuint32_t  NCE:1;             /* Nbytes/Citer Configuration Error */
-         vuint32_t  SGE:1;             /* Scatter/Gather Configuration Error */
-         vuint32_t  SBE:1;             /* Source Bus Error */
-         vuint32_t  DBE:1;             /* Destination Bus Error */
-      } B;
-   } SPP_DMA2_DMAES_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  ERQ:32;            /* DMA Enable Request */
-      } B;
-   } SPP_DMA2_DMAERQH_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  ERQ:32;            /* DMA Enable Request */
-      } B;
-   } SPP_DMA2_DMAERQL_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  EEI:32;            /* DMA Enable Error Interrupt */
-      } B;
-   } SPP_DMA2_DMAEEIH_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  EEI:32;            /* DMA Enable Error Interrupt */
-      } B;
-   } SPP_DMA2_DMAEEIL_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:1;
-         vuint8_t   SERQ:7;            /* Set Enable Request */
-      } B;
-   } SPP_DMA2_DMASERQ_8B_tag;
-
-   typedef union {   /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:1;
-         vuint8_t   CERQ:7;            /* Clear Enable Request */
-      } B;
-   } SPP_DMA2_DMACERQ_8B_tag;
-
-   typedef union {   /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:1;
-         vuint8_t   SEEI:7;            /* Set Enable Error Interrupt */
-      } B;
-   } SPP_DMA2_DMASEEI_8B_tag;
-
-   typedef union {   /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
-      vuint8_t R;
-      struct {
-         vuint8_t:1;
-         vuint8_t   CEEI:7;            /* Clear Enable Error Interrupt */
-      } B;
-   } SPP_DMA2_DMACEEI_8B_tag;
-
-   typedef union {   /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
-      vuint8_t R;
-      struct {
-         vuint8_t:1;
-         vuint8_t   CINT:7;            /* Clear Interrupt Request */
-      } B;
-   } SPP_DMA2_DMACINT_8B_tag;
-
-   typedef union {   /* SPP_DMA2_DMACERR - DMA Clear Error */
-      vuint8_t R;
-      struct {
-         vuint8_t:1;
-         vuint8_t   CERR:7;            /* Clear Error Indicator */
-      } B;
-   } SPP_DMA2_DMACERR_8B_tag;
-
-   typedef union {   /* SPP_DMA2_DMASSRT - DMA Set START Bit */
-      vuint8_t R;
-      struct {
-         vuint8_t:1;
-         vuint8_t   SSRT:7;            /* Set START Bit */
-      } B;
-   } SPP_DMA2_DMASSRT_8B_tag;
-
-   typedef union {   /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
-      vuint8_t R;
-      struct {
-         vuint8_t:1;
-         vuint8_t   CDNE:7;            /* Clear DONE Status Bit */
-      } B;
-   } SPP_DMA2_DMACDNE_8B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  INT:32;            /* DMA Interrupt Request */
-      } B;
-   } SPP_DMA2_DMAINTH_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  INT:32;            /* DMA Interrupt Request */
-      } B;
-   } SPP_DMA2_DMAINTL_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAERRH - DMA Error Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  ERR:32;            /* DMA Error n */
-      } B;
-   } SPP_DMA2_DMAERRH_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAERRL - DMA Error Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  ERR:32;            /* DMA Error n */
-      } B;
-   } SPP_DMA2_DMAERRL_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  HRS:32;            /* DMA Hardware Request Status */
-      } B;
-   } SPP_DMA2_DMAHRSH_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  HRS:32;            /* DMA Hardware Request Status */
-      } B;
-   } SPP_DMA2_DMAHRSL_32B_tag;
-
-   typedef union {   /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  GPOR:32;           /* DMA General Purpose Output */
-      } B;
-   } SPP_DMA2_DMAGPOR_32B_tag;
-
-
-   /* Register layout for all registers DCHPRI... */
-
-   typedef union {   /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
-      vuint8_t R;
-      struct {
-         vuint8_t   ECP:1;             /* Enable Channel Preemption */
-         vuint8_t   DPA:1;             /* Disable Preempt Ability */
-         vuint8_t   GRPPRI:2;          /* Channel n Current Group Priority */
-         vuint8_t   CHPRI:4;           /* Channel n Arbitration Priority */
-      } B;
-   } SPP_DMA2_DCHPRI_8B_tag;
-
-
-   /* Register layout for all registers TCDWORD0_... */
-
-   typedef union {   /* SPP_DMA2_TCDn Word0 - Source Address */
-      vuint32_t R;
-      struct {
-         vuint32_t  SADDR:32;          /* Source Address */
-      } B;
-   } SPP_DMA2_TCDWORD0__32B_tag;
-
-
-   /* Register layout for all registers TCDWORD4_... */
-
-   typedef union {   /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-      vuint32_t R;
-      struct {
-         vuint32_t  SMOD:5;            /* Source Address Modulo */
-         vuint32_t  SSIZE:3;           /* Source Data Transfer Size */
-         vuint32_t  DMOD:5;            /* Destination Address Module */
-         vuint32_t  DSIZE:3;           /* Destination Data Transfer Size */
-         vuint32_t  SOFF:16;           /* Source Address Signed Offset */
-      } B;
-   } SPP_DMA2_TCDWORD4__32B_tag;
-
-
-   /* Register layout for all registers TCDWORD8_... */
-
-   typedef union {   /* SPP_DMA2_TCDn Word2 - nbytes */
-      vuint32_t R;
-      struct {
-         vuint32_t  SMLOE:1;           /* Source Minor Loop Offset Enable */
-         vuint32_t  DMLOE:1;           /* Destination Minor Loop Offset Enable */
-         vuint32_t  MLOFF:20;          /* Minor Loop Offset */
-         vuint32_t  NBYTES:10;         /* Inner Minor byte transfer Count */
-      } B;
-   } SPP_DMA2_TCDWORD8__32B_tag;
-
-
-   /* Register layout for all registers TCDWORD12_... */
-
-   typedef union {   /* SPP_DMA2_TCDn Word3 - slast */
-      vuint32_t R;
-      struct {
-         vuint32_t  SLAST:32;          /* Last Source Address Adjustment */
-      } B;
-   } SPP_DMA2_TCDWORD12__32B_tag;
-
-
-   /* Register layout for all registers TCDWORD16_... */
-
-   typedef union {   /* SPP_DMA2_TCDn Word4 - daddr */
-      vuint32_t R;
-      struct {
-         vuint32_t  DADDR:32;          /* Destination Address */
-      } B;
-   } SPP_DMA2_TCDWORD16__32B_tag;
-
-
-   /* Register layout for all registers TCDWORD20_... */
-
-   typedef union {   /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-      vuint32_t R;
-      struct {
-         vuint32_t  CITER_E_LINK:1;    /* Enable Channel to channel linking on minor loop complete */
-         vuint32_t  CITER_LINKCH:6;    /* Link Channel Number */
-         vuint32_t  CITER:9;           /* Current Major Iteration Count */
-         vuint32_t  DOFF:16;           /* Destination Address Signed Offset */
-      } B;
-   } SPP_DMA2_TCDWORD20__32B_tag;
-
-
-   /* Register layout for all registers TCDWORD24_... */
-
-   typedef union {   /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-      vuint32_t R;
-      struct {
-         vuint32_t  DLAST_SGA:32;      /* Last destination address adjustment */
-      } B;
-   } SPP_DMA2_TCDWORD24__32B_tag;
-
-
-   /* Register layout for all registers TCDWORD28_... */
-
-   typedef union {   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-      vuint32_t R;
-      struct {
-         vuint32_t  BITER:16;          /* Enable Channel to Channel linking on minor loop complete */
-         vuint32_t  BWC:2;             /* Bandwidth Control */
-         vuint32_t  MAJOR_LINKCH:6;    /* Link Channel Number */
-         vuint32_t  DONE:1;            /* channel done */
-         vuint32_t  ACTIVE:1;          /* Channel Active */
-         vuint32_t  MAJOR_E_LINK:1;    /* Enable Channel to Channel Linking on major loop complete */
-         vuint32_t  E_SG:1;            /* Enable Scatter/Gather Processing */
-         vuint32_t  D_REQ:1;           /* Disable Request */
-         vuint32_t  INT_HALF:1;        /* Enable an Interrupt when Major Counter is half complete */
-         vuint32_t  INT_MAJ:1;         /* Enable an Interrupt when Major Iteration count completes */
-         vuint32_t  START:1;           /* Channel Start */
-      } B;
-   } SPP_DMA2_TCDWORD28__32B_tag;
-
-
-   typedef struct SPP_DMA2_CHANNEL_struct_tag {
-
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-      SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_;  /* relative offset: 0x0000 */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-      SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_;  /* relative offset: 0x0004 */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-      SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_;  /* relative offset: 0x0008 */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-      SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_;  /* relative offset: 0x000C */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-      SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_;  /* relative offset: 0x0010 */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-      SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_;  /* relative offset: 0x0014 */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-      SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_;  /* relative offset: 0x0018 */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-      SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_;  /* relative offset: 0x001C */
-
-   } SPP_DMA2_CHANNEL_tag;
-
-
-   typedef struct SPP_DMA2_struct_tag { /* start of SPP_DMA2_tag */
-                                /* SPP_DMA2_DMACR - DMA Control Register */
-      SPP_DMA2_DMACR_32B_tag DMACR;        /* offset: 0x0000 size: 32 bit */
-                           /* SPP_DMA2_DMAES - DMA Error Status Register */
-      SPP_DMA2_DMAES_32B_tag DMAES;        /* offset: 0x0004 size: 32 bit */
-                       /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
-      SPP_DMA2_DMAERQH_32B_tag DMAERQH;    /* offset: 0x0008 size: 32 bit */
-                       /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
-      SPP_DMA2_DMAERQL_32B_tag DMAERQL;    /* offset: 0x000C size: 32 bit */
-               /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
-      SPP_DMA2_DMAEEIH_32B_tag DMAEEIH;    /* offset: 0x0010 size: 32 bit */
-               /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
-      SPP_DMA2_DMAEEIL_32B_tag DMAEEIL;    /* offset: 0x0014 size: 32 bit */
-                   /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
-      SPP_DMA2_DMASERQ_8B_tag DMASERQ;     /* offset: 0x0018 size: 8 bit */
-                 /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
-      SPP_DMA2_DMACERQ_8B_tag DMACERQ;     /* offset: 0x0019 size: 8 bit */
-           /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
-      SPP_DMA2_DMASEEI_8B_tag DMASEEI;     /* offset: 0x001A size: 8 bit */
-         /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
-      SPP_DMA2_DMACEEI_8B_tag DMACEEI;     /* offset: 0x001B size: 8 bit */
-                       /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
-      SPP_DMA2_DMACINT_8B_tag DMACINT;     /* offset: 0x001C size: 8 bit */
-                                   /* SPP_DMA2_DMACERR - DMA Clear Error */
-      SPP_DMA2_DMACERR_8B_tag DMACERR;     /* offset: 0x001D size: 8 bit */
-                                 /* SPP_DMA2_DMASSRT - DMA Set START Bit */
-      SPP_DMA2_DMASSRT_8B_tag DMASSRT;     /* offset: 0x001E size: 8 bit */
-                             /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
-      SPP_DMA2_DMACDNE_8B_tag DMACDNE;     /* offset: 0x001F size: 8 bit */
-                    /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
-      SPP_DMA2_DMAINTH_32B_tag DMAINTH;    /* offset: 0x0020 size: 32 bit */
-                    /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
-      SPP_DMA2_DMAINTL_32B_tag DMAINTL;    /* offset: 0x0024 size: 32 bit */
-                                /* SPP_DMA2_DMAERRH - DMA Error Register */
-      SPP_DMA2_DMAERRH_32B_tag DMAERRH;    /* offset: 0x0028 size: 32 bit */
-                                /* SPP_DMA2_DMAERRL - DMA Error Register */
-      SPP_DMA2_DMAERRL_32B_tag DMAERRL;    /* offset: 0x002C size: 32 bit */
-              /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
-      SPP_DMA2_DMAHRSH_32B_tag DMAHRSH;    /* offset: 0x0030 size: 32 bit */
-              /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
-      SPP_DMA2_DMAHRSL_32B_tag DMAHRSL;    /* offset: 0x0034 size: 32 bit */
-               /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
-      SPP_DMA2_DMAGPOR_32B_tag DMAGPOR;    /* offset: 0x0038 size: 32 bit */
-      int8_t SPP_DMA2_reserved_003C_C[196];
-      union {
-                            /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
-         SPP_DMA2_DCHPRI_8B_tag DCHPRI[64];  /* offset: 0x0100  (0x0001 x 64) */
-
-         struct {
-                            /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI0;  /* offset: 0x0100 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI1;  /* offset: 0x0101 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI2;  /* offset: 0x0102 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI3;  /* offset: 0x0103 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI4;  /* offset: 0x0104 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI5;  /* offset: 0x0105 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI6;  /* offset: 0x0106 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI7;  /* offset: 0x0107 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI8;  /* offset: 0x0108 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI9;  /* offset: 0x0109 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI10;  /* offset: 0x010A size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI11;  /* offset: 0x010B size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI12;  /* offset: 0x010C size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI13;  /* offset: 0x010D size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI14;  /* offset: 0x010E size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI15;  /* offset: 0x010F size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI16;  /* offset: 0x0110 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI17;  /* offset: 0x0111 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI18;  /* offset: 0x0112 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI19;  /* offset: 0x0113 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI20;  /* offset: 0x0114 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI21;  /* offset: 0x0115 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI22;  /* offset: 0x0116 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI23;  /* offset: 0x0117 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI24;  /* offset: 0x0118 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI25;  /* offset: 0x0119 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI26;  /* offset: 0x011A size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI27;  /* offset: 0x011B size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI28;  /* offset: 0x011C size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI29;  /* offset: 0x011D size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI30;  /* offset: 0x011E size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI31;  /* offset: 0x011F size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI32;  /* offset: 0x0120 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI33;  /* offset: 0x0121 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI34;  /* offset: 0x0122 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI35;  /* offset: 0x0123 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI36;  /* offset: 0x0124 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI37;  /* offset: 0x0125 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI38;  /* offset: 0x0126 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI39;  /* offset: 0x0127 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI40;  /* offset: 0x0128 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI41;  /* offset: 0x0129 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI42;  /* offset: 0x012A size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI43;  /* offset: 0x012B size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI44;  /* offset: 0x012C size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI45;  /* offset: 0x012D size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI46;  /* offset: 0x012E size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI47;  /* offset: 0x012F size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI48;  /* offset: 0x0130 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI49;  /* offset: 0x0131 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI50;  /* offset: 0x0132 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI51;  /* offset: 0x0133 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI52;  /* offset: 0x0134 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI53;  /* offset: 0x0135 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI54;  /* offset: 0x0136 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI55;  /* offset: 0x0137 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI56;  /* offset: 0x0138 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI57;  /* offset: 0x0139 size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI58;  /* offset: 0x013A size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI59;  /* offset: 0x013B size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI60;  /* offset: 0x013C size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI61;  /* offset: 0x013D size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI62;  /* offset: 0x013E size: 8 bit */
-            SPP_DMA2_DCHPRI_8B_tag DCHPRI63;  /* offset: 0x013F size: 8 bit */
-         };
-
-      };
-      int8_t SPP_DMA2_reserved_0140_C[3776];
-      union {
-                                                /*  Register set CHANNEL */
-         SPP_DMA2_CHANNEL_tag CHANNEL[64];  /* offset: 0x1000  (0x0020 x 64) */
-
-         struct {
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0;  /* offset: 0x1000 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0;  /* offset: 0x1004 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0;  /* offset: 0x1008 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0;  /* offset: 0x100C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0;  /* offset: 0x1010 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0;  /* offset: 0x1014 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0;  /* offset: 0x1018 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0;  /* offset: 0x101C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1;  /* offset: 0x1020 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1;  /* offset: 0x1024 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1;  /* offset: 0x1028 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1;  /* offset: 0x102C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1;  /* offset: 0x1030 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1;  /* offset: 0x1034 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1;  /* offset: 0x1038 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1;  /* offset: 0x103C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2;  /* offset: 0x1040 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2;  /* offset: 0x1044 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2;  /* offset: 0x1048 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2;  /* offset: 0x104C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2;  /* offset: 0x1050 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2;  /* offset: 0x1054 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2;  /* offset: 0x1058 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2;  /* offset: 0x105C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3;  /* offset: 0x1060 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3;  /* offset: 0x1064 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3;  /* offset: 0x1068 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3;  /* offset: 0x106C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3;  /* offset: 0x1070 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3;  /* offset: 0x1074 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3;  /* offset: 0x1078 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3;  /* offset: 0x107C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4;  /* offset: 0x1080 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4;  /* offset: 0x1084 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4;  /* offset: 0x1088 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4;  /* offset: 0x108C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4;  /* offset: 0x1090 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4;  /* offset: 0x1094 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4;  /* offset: 0x1098 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4;  /* offset: 0x109C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5;  /* offset: 0x10A0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5;  /* offset: 0x10A4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5;  /* offset: 0x10A8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5;  /* offset: 0x10AC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5;  /* offset: 0x10B0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5;  /* offset: 0x10B4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5;  /* offset: 0x10B8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5;  /* offset: 0x10BC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6;  /* offset: 0x10C0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6;  /* offset: 0x10C4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6;  /* offset: 0x10C8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6;  /* offset: 0x10CC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6;  /* offset: 0x10D0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6;  /* offset: 0x10D4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6;  /* offset: 0x10D8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6;  /* offset: 0x10DC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7;  /* offset: 0x10E0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7;  /* offset: 0x10E4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7;  /* offset: 0x10E8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7;  /* offset: 0x10EC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7;  /* offset: 0x10F0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7;  /* offset: 0x10F4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7;  /* offset: 0x10F8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7;  /* offset: 0x10FC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8;  /* offset: 0x1100 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8;  /* offset: 0x1104 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8;  /* offset: 0x1108 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8;  /* offset: 0x110C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8;  /* offset: 0x1110 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8;  /* offset: 0x1114 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8;  /* offset: 0x1118 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8;  /* offset: 0x111C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9;  /* offset: 0x1120 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9;  /* offset: 0x1124 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9;  /* offset: 0x1128 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9;  /* offset: 0x112C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9;  /* offset: 0x1130 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9;  /* offset: 0x1134 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9;  /* offset: 0x1138 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9;  /* offset: 0x113C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10;  /* offset: 0x1140 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10;  /* offset: 0x1144 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10;  /* offset: 0x1148 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10;  /* offset: 0x114C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10;  /* offset: 0x1150 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10;  /* offset: 0x1154 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10;  /* offset: 0x1158 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10;  /* offset: 0x115C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11;  /* offset: 0x1160 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11;  /* offset: 0x1164 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11;  /* offset: 0x1168 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11;  /* offset: 0x116C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11;  /* offset: 0x1170 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11;  /* offset: 0x1174 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11;  /* offset: 0x1178 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11;  /* offset: 0x117C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12;  /* offset: 0x1180 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12;  /* offset: 0x1184 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12;  /* offset: 0x1188 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12;  /* offset: 0x118C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12;  /* offset: 0x1190 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12;  /* offset: 0x1194 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12;  /* offset: 0x1198 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12;  /* offset: 0x119C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13;  /* offset: 0x11A0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13;  /* offset: 0x11A4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13;  /* offset: 0x11A8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13;  /* offset: 0x11AC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13;  /* offset: 0x11B0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13;  /* offset: 0x11B4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13;  /* offset: 0x11B8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13;  /* offset: 0x11BC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14;  /* offset: 0x11C0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14;  /* offset: 0x11C4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14;  /* offset: 0x11C8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14;  /* offset: 0x11CC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14;  /* offset: 0x11D0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14;  /* offset: 0x11D4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14;  /* offset: 0x11D8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14;  /* offset: 0x11DC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15;  /* offset: 0x11E0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15;  /* offset: 0x11E4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15;  /* offset: 0x11E8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15;  /* offset: 0x11EC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15;  /* offset: 0x11F0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15;  /* offset: 0x11F4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15;  /* offset: 0x11F8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15;  /* offset: 0x11FC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16;  /* offset: 0x1200 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16;  /* offset: 0x1204 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16;  /* offset: 0x1208 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16;  /* offset: 0x120C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16;  /* offset: 0x1210 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16;  /* offset: 0x1214 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16;  /* offset: 0x1218 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16;  /* offset: 0x121C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17;  /* offset: 0x1220 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17;  /* offset: 0x1224 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17;  /* offset: 0x1228 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17;  /* offset: 0x122C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17;  /* offset: 0x1230 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17;  /* offset: 0x1234 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17;  /* offset: 0x1238 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17;  /* offset: 0x123C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18;  /* offset: 0x1240 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18;  /* offset: 0x1244 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18;  /* offset: 0x1248 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18;  /* offset: 0x124C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18;  /* offset: 0x1250 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18;  /* offset: 0x1254 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18;  /* offset: 0x1258 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18;  /* offset: 0x125C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19;  /* offset: 0x1260 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19;  /* offset: 0x1264 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19;  /* offset: 0x1268 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19;  /* offset: 0x126C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19;  /* offset: 0x1270 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19;  /* offset: 0x1274 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19;  /* offset: 0x1278 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19;  /* offset: 0x127C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20;  /* offset: 0x1280 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20;  /* offset: 0x1284 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20;  /* offset: 0x1288 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20;  /* offset: 0x128C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20;  /* offset: 0x1290 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20;  /* offset: 0x1294 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20;  /* offset: 0x1298 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20;  /* offset: 0x129C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21;  /* offset: 0x12A0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21;  /* offset: 0x12A4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21;  /* offset: 0x12A8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21;  /* offset: 0x12AC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21;  /* offset: 0x12B0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21;  /* offset: 0x12B4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21;  /* offset: 0x12B8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21;  /* offset: 0x12BC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22;  /* offset: 0x12C0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22;  /* offset: 0x12C4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22;  /* offset: 0x12C8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22;  /* offset: 0x12CC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22;  /* offset: 0x12D0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22;  /* offset: 0x12D4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22;  /* offset: 0x12D8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22;  /* offset: 0x12DC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23;  /* offset: 0x12E0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23;  /* offset: 0x12E4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23;  /* offset: 0x12E8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23;  /* offset: 0x12EC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23;  /* offset: 0x12F0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23;  /* offset: 0x12F4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23;  /* offset: 0x12F8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23;  /* offset: 0x12FC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24;  /* offset: 0x1300 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24;  /* offset: 0x1304 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24;  /* offset: 0x1308 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24;  /* offset: 0x130C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24;  /* offset: 0x1310 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24;  /* offset: 0x1314 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24;  /* offset: 0x1318 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24;  /* offset: 0x131C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25;  /* offset: 0x1320 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25;  /* offset: 0x1324 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25;  /* offset: 0x1328 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25;  /* offset: 0x132C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25;  /* offset: 0x1330 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25;  /* offset: 0x1334 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25;  /* offset: 0x1338 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25;  /* offset: 0x133C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26;  /* offset: 0x1340 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26;  /* offset: 0x1344 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26;  /* offset: 0x1348 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26;  /* offset: 0x134C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26;  /* offset: 0x1350 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26;  /* offset: 0x1354 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26;  /* offset: 0x1358 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26;  /* offset: 0x135C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27;  /* offset: 0x1360 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27;  /* offset: 0x1364 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27;  /* offset: 0x1368 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27;  /* offset: 0x136C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27;  /* offset: 0x1370 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27;  /* offset: 0x1374 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27;  /* offset: 0x1378 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27;  /* offset: 0x137C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28;  /* offset: 0x1380 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28;  /* offset: 0x1384 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28;  /* offset: 0x1388 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28;  /* offset: 0x138C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28;  /* offset: 0x1390 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28;  /* offset: 0x1394 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28;  /* offset: 0x1398 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28;  /* offset: 0x139C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29;  /* offset: 0x13A0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29;  /* offset: 0x13A4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29;  /* offset: 0x13A8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29;  /* offset: 0x13AC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29;  /* offset: 0x13B0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29;  /* offset: 0x13B4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29;  /* offset: 0x13B8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29;  /* offset: 0x13BC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30;  /* offset: 0x13C0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30;  /* offset: 0x13C4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30;  /* offset: 0x13C8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30;  /* offset: 0x13CC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30;  /* offset: 0x13D0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30;  /* offset: 0x13D4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30;  /* offset: 0x13D8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30;  /* offset: 0x13DC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31;  /* offset: 0x13E0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31;  /* offset: 0x13E4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31;  /* offset: 0x13E8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31;  /* offset: 0x13EC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31;  /* offset: 0x13F0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31;  /* offset: 0x13F4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31;  /* offset: 0x13F8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31;  /* offset: 0x13FC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32;  /* offset: 0x1400 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32;  /* offset: 0x1404 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32;  /* offset: 0x1408 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32;  /* offset: 0x140C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32;  /* offset: 0x1410 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32;  /* offset: 0x1414 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32;  /* offset: 0x1418 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32;  /* offset: 0x141C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33;  /* offset: 0x1420 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33;  /* offset: 0x1424 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33;  /* offset: 0x1428 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33;  /* offset: 0x142C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33;  /* offset: 0x1430 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33;  /* offset: 0x1434 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33;  /* offset: 0x1438 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33;  /* offset: 0x143C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34;  /* offset: 0x1440 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34;  /* offset: 0x1444 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34;  /* offset: 0x1448 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34;  /* offset: 0x144C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34;  /* offset: 0x1450 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34;  /* offset: 0x1454 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34;  /* offset: 0x1458 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34;  /* offset: 0x145C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35;  /* offset: 0x1460 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35;  /* offset: 0x1464 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35;  /* offset: 0x1468 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35;  /* offset: 0x146C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35;  /* offset: 0x1470 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35;  /* offset: 0x1474 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35;  /* offset: 0x1478 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35;  /* offset: 0x147C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36;  /* offset: 0x1480 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36;  /* offset: 0x1484 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36;  /* offset: 0x1488 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36;  /* offset: 0x148C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36;  /* offset: 0x1490 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36;  /* offset: 0x1494 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36;  /* offset: 0x1498 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36;  /* offset: 0x149C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37;  /* offset: 0x14A0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37;  /* offset: 0x14A4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37;  /* offset: 0x14A8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37;  /* offset: 0x14AC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37;  /* offset: 0x14B0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37;  /* offset: 0x14B4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37;  /* offset: 0x14B8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37;  /* offset: 0x14BC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38;  /* offset: 0x14C0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38;  /* offset: 0x14C4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38;  /* offset: 0x14C8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38;  /* offset: 0x14CC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38;  /* offset: 0x14D0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38;  /* offset: 0x14D4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38;  /* offset: 0x14D8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38;  /* offset: 0x14DC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39;  /* offset: 0x14E0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39;  /* offset: 0x14E4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39;  /* offset: 0x14E8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39;  /* offset: 0x14EC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39;  /* offset: 0x14F0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39;  /* offset: 0x14F4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39;  /* offset: 0x14F8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39;  /* offset: 0x14FC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40;  /* offset: 0x1500 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40;  /* offset: 0x1504 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40;  /* offset: 0x1508 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40;  /* offset: 0x150C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40;  /* offset: 0x1510 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40;  /* offset: 0x1514 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40;  /* offset: 0x1518 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40;  /* offset: 0x151C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41;  /* offset: 0x1520 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41;  /* offset: 0x1524 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41;  /* offset: 0x1528 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41;  /* offset: 0x152C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41;  /* offset: 0x1530 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41;  /* offset: 0x1534 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41;  /* offset: 0x1538 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41;  /* offset: 0x153C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42;  /* offset: 0x1540 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42;  /* offset: 0x1544 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42;  /* offset: 0x1548 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42;  /* offset: 0x154C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42;  /* offset: 0x1550 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42;  /* offset: 0x1554 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42;  /* offset: 0x1558 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42;  /* offset: 0x155C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43;  /* offset: 0x1560 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43;  /* offset: 0x1564 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43;  /* offset: 0x1568 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43;  /* offset: 0x156C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43;  /* offset: 0x1570 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43;  /* offset: 0x1574 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43;  /* offset: 0x1578 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43;  /* offset: 0x157C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44;  /* offset: 0x1580 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44;  /* offset: 0x1584 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44;  /* offset: 0x1588 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44;  /* offset: 0x158C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44;  /* offset: 0x1590 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44;  /* offset: 0x1594 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44;  /* offset: 0x1598 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44;  /* offset: 0x159C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45;  /* offset: 0x15A0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45;  /* offset: 0x15A4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45;  /* offset: 0x15A8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45;  /* offset: 0x15AC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45;  /* offset: 0x15B0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45;  /* offset: 0x15B4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45;  /* offset: 0x15B8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45;  /* offset: 0x15BC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46;  /* offset: 0x15C0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46;  /* offset: 0x15C4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46;  /* offset: 0x15C8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46;  /* offset: 0x15CC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46;  /* offset: 0x15D0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46;  /* offset: 0x15D4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46;  /* offset: 0x15D8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46;  /* offset: 0x15DC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47;  /* offset: 0x15E0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47;  /* offset: 0x15E4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47;  /* offset: 0x15E8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47;  /* offset: 0x15EC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47;  /* offset: 0x15F0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47;  /* offset: 0x15F4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47;  /* offset: 0x15F8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47;  /* offset: 0x15FC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48;  /* offset: 0x1600 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48;  /* offset: 0x1604 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48;  /* offset: 0x1608 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48;  /* offset: 0x160C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48;  /* offset: 0x1610 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48;  /* offset: 0x1614 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48;  /* offset: 0x1618 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48;  /* offset: 0x161C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49;  /* offset: 0x1620 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49;  /* offset: 0x1624 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49;  /* offset: 0x1628 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49;  /* offset: 0x162C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49;  /* offset: 0x1630 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49;  /* offset: 0x1634 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49;  /* offset: 0x1638 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49;  /* offset: 0x163C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50;  /* offset: 0x1640 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50;  /* offset: 0x1644 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50;  /* offset: 0x1648 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50;  /* offset: 0x164C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50;  /* offset: 0x1650 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50;  /* offset: 0x1654 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50;  /* offset: 0x1658 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50;  /* offset: 0x165C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51;  /* offset: 0x1660 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51;  /* offset: 0x1664 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51;  /* offset: 0x1668 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51;  /* offset: 0x166C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51;  /* offset: 0x1670 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51;  /* offset: 0x1674 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51;  /* offset: 0x1678 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51;  /* offset: 0x167C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52;  /* offset: 0x1680 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52;  /* offset: 0x1684 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52;  /* offset: 0x1688 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52;  /* offset: 0x168C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52;  /* offset: 0x1690 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52;  /* offset: 0x1694 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52;  /* offset: 0x1698 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52;  /* offset: 0x169C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53;  /* offset: 0x16A0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53;  /* offset: 0x16A4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53;  /* offset: 0x16A8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53;  /* offset: 0x16AC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53;  /* offset: 0x16B0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53;  /* offset: 0x16B4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53;  /* offset: 0x16B8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53;  /* offset: 0x16BC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54;  /* offset: 0x16C0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54;  /* offset: 0x16C4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54;  /* offset: 0x16C8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54;  /* offset: 0x16CC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54;  /* offset: 0x16D0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54;  /* offset: 0x16D4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54;  /* offset: 0x16D8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54;  /* offset: 0x16DC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55;  /* offset: 0x16E0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55;  /* offset: 0x16E4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55;  /* offset: 0x16E8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55;  /* offset: 0x16EC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55;  /* offset: 0x16F0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55;  /* offset: 0x16F4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55;  /* offset: 0x16F8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55;  /* offset: 0x16FC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56;  /* offset: 0x1700 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56;  /* offset: 0x1704 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56;  /* offset: 0x1708 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56;  /* offset: 0x170C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56;  /* offset: 0x1710 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56;  /* offset: 0x1714 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56;  /* offset: 0x1718 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56;  /* offset: 0x171C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57;  /* offset: 0x1720 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57;  /* offset: 0x1724 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57;  /* offset: 0x1728 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57;  /* offset: 0x172C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57;  /* offset: 0x1730 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57;  /* offset: 0x1734 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57;  /* offset: 0x1738 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57;  /* offset: 0x173C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58;  /* offset: 0x1740 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58;  /* offset: 0x1744 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58;  /* offset: 0x1748 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58;  /* offset: 0x174C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58;  /* offset: 0x1750 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58;  /* offset: 0x1754 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58;  /* offset: 0x1758 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58;  /* offset: 0x175C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59;  /* offset: 0x1760 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59;  /* offset: 0x1764 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59;  /* offset: 0x1768 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59;  /* offset: 0x176C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59;  /* offset: 0x1770 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59;  /* offset: 0x1774 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59;  /* offset: 0x1778 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59;  /* offset: 0x177C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60;  /* offset: 0x1780 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60;  /* offset: 0x1784 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60;  /* offset: 0x1788 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60;  /* offset: 0x178C size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60;  /* offset: 0x1790 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60;  /* offset: 0x1794 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60;  /* offset: 0x1798 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60;  /* offset: 0x179C size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61;  /* offset: 0x17A0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61;  /* offset: 0x17A4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61;  /* offset: 0x17A8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61;  /* offset: 0x17AC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61;  /* offset: 0x17B0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61;  /* offset: 0x17B4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61;  /* offset: 0x17B8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61;  /* offset: 0x17BC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62;  /* offset: 0x17C0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62;  /* offset: 0x17C4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62;  /* offset: 0x17C8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62;  /* offset: 0x17CC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62;  /* offset: 0x17D0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62;  /* offset: 0x17D4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62;  /* offset: 0x17D8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62;  /* offset: 0x17DC size: 32 bit */
-                                 /* SPP_DMA2_TCDn Word0 - Source Address */
-            SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63;  /* offset: 0x17E0 size: 32 bit */
-                 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
-            SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63;  /* offset: 0x17E4 size: 32 bit */
-                                         /* SPP_DMA2_TCDn Word2 - nbytes */
-            SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63;  /* offset: 0x17E8 size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word3 - slast */
-            SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63;  /* offset: 0x17EC size: 32 bit */
-                                          /* SPP_DMA2_TCDn Word4 - daddr */
-            SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63;  /* offset: 0x17F0 size: 32 bit */
-                     /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
-            SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63;  /* offset: 0x17F4 size: 32 bit */
-                                     /* SPP_DMA2_TCDn Word6 -  dlast_sga */
-            SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63;  /* offset: 0x17F8 size: 32 bit */
-                                   /* SPP_DMA2_TCDn Word7 -  biter, etc. */
-            SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63;  /* offset: 0x17FC size: 32 bit */
-         };
-
-      };
-   } SPP_DMA2_tag;
-
-
-#define SPP_DMA2 (*(volatile SPP_DMA2_tag *) 0xFFF44000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: INTC  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* BCR - Block Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:18;
-         vuint32_t  VTES_PRC1:1;       /* Vector Table Entry Size - Processor 1 */
-         vuint32_t:4;
-         vuint32_t  HVEN_PRC1:1;       /* Hardware Vector Enable - Processor 1 */
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_INTC
-         vuint32_t  VTES_PRC0:1;       /* Vector Table Entry Size - Processor 0 */
-#else
-         vuint32_t  VTES:1;              /* deprecated name - please avoid */
-#endif
-         vuint32_t:4;
-#ifndef USE_FIELD_ALIASES_INTC
-         vuint32_t  HVEN_PRC0:1;       /* Hardware Vector Enable - Processor 0 */
-#else
-         vuint32_t  HVEN:1;              /* deprecated name - please avoid */
-#endif
-      } B;
-   } INTC_BCR_32B_tag;
-
-   typedef union {   /* CPR - Current Priority Register - Processor 0 */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-         vuint32_t  PRI:4;             /* Priority Bits */
-      } B;
-   } INTC_CPR_PRC0_32B_tag;
-
-   typedef union {   /* CPR - Current Priority Register - Processor 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t:28;
-         vuint32_t  PRI:4;             /* Priority Bits */
-      } B;
-   } INTC_CPR_PRC1_32B_tag;
-
-   typedef union {   /* IACKR- Interrupt Acknowledge Register - Processor 0 */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_INTC
-         vuint32_t  VTBA_PRC0:21;      /* Vector Table Base Address - Processor 0 */
-#else
-         vuint32_t  VTBA:21;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_INTC
-         vuint32_t  INTEC_PRC0:9;      /* Interrupt Vector - Processor 0 */
-#else
-         vuint32_t  INTVEC:9;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:2;
-      } B;
-   } INTC_IACKR_PRC0_32B_tag;
-
-   typedef union {   /* IACKR- Interrupt Acknowledge Register - Processor 1 */
-      vuint32_t R;
-      struct {
-         vuint32_t  VTBA_PRC1:21;      /* Vector Table Base Address - Processor 1 */
-         vuint32_t  INTEC_PRC1:9;      /* Interrupt Vector - Processor 1 */
-         vuint32_t:2;
-      } B;
-   } INTC_IACKR_PRC1_32B_tag;
-
-   typedef union {   /* EOIR- End of Interrupt Register - Processor 0 */
-      vuint32_t R;
-   } INTC_EOIR_PRC0_32B_tag;
-
-   typedef union {   /* EOIR- End of Interrupt Register - Processor 1 */
-      vuint32_t R;
-   } INTC_EOIR_PRC1_32B_tag;
-
-
-   /* Register layout for all registers SSCIR... */
-
-   typedef union {   /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
-      vuint8_t R;
-      struct {
-         vuint8_t:6;
-         vuint8_t   SET:1;             /* Set Flag bit */
-         vuint8_t   CLR:1;             /* Clear Flag bit */
-      } B;
-   } INTC_SSCIR_8B_tag;
-
-   typedef union {   /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t:6;
-         vuint32_t  SET0:1;            /* Set Flag 0 bit */
-         vuint32_t  CLR0:1;            /* Clear Flag 0 bit */
-         vuint32_t:6;
-         vuint32_t  SET1:1;            /* Set Flag 1 bit */
-         vuint32_t  CLR1:1;            /* Clear Flag 1 bit */
-         vuint32_t:6;
-         vuint32_t  SET2:1;            /* Set Flag 2 bit */
-         vuint32_t  CLR2:1;            /* Clear Flag 2 bit */
-         vuint32_t:6;
-         vuint32_t  SET3:1;            /* Set Flag 3 bit */
-         vuint32_t  CLR3:1;            /* Clear Flag 3 bit */
-      } B;
-   } INTC_SSCIR0_3_32B_tag;
-
-   typedef union {   /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t:6;
-         vuint32_t  SET4:1;            /* Set Flag 4 bit */
-         vuint32_t  CLR4:1;            /* Clear Flag 4 bit */
-         vuint32_t:6;
-         vuint32_t  SET5:1;            /* Set Flag 5 bit */
-         vuint32_t  CLR5:1;            /* Clear Flag 5 bit */
-         vuint32_t:6;
-         vuint32_t  SET6:1;            /* Set Flag 6 bit */
-         vuint32_t  CLR6:1;            /* Clear Flag 6 bit */
-         vuint32_t:6;
-         vuint32_t  SET7:1;            /* Set Flag 7 bit */
-         vuint32_t  CLR7:1;            /* Clear Flag 7 bit */
-      } B;
-   } INTC_SSCIR4_7_32B_tag;
-
-
-   /* Register layout for all registers PSR... */
-
-   typedef union {   /* PSR0-511 - Priority Select Registers */
-      vuint8_t R;
-      struct {
-         vuint8_t   PRC_SEL:2;         /* Processor Select */
-         vuint8_t:2;
-         vuint8_t   PRI:4;             /* Priority Select */
-      } B;
-   } INTC_PSR_8B_tag;
-
-
-   /* Register layout for all registers PSR... */
-
-   typedef union {   /* PSR0_3 - 508_511 - Priority Select Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  PRC_SEL0:2;        /* Processor Select - Entry 0 */
-         vuint32_t:2;
-         vuint32_t  PRI0:4;            /* Priority Select - Entry 0 */
-         vuint32_t  PRC_SEL1:2;        /* Processor Select - Entry 1 */
-         vuint32_t:2;
-         vuint32_t  PRI1:4;            /* Priority Select - Entry 1 */
-         vuint32_t  PRC_SEL2:2;        /* Processor Select - Entry 2 */
-         vuint32_t:2;
-         vuint32_t  PRI2:4;            /* Priority Select - Entry 2 */
-         vuint32_t  PRC_SEL3:2;        /* Processor Select - Entry 3 */
-         vuint32_t:2;
-         vuint32_t  PRI3:4;            /* Priority Select - Entry 3 */
-      } B;
-   } INTC_PSR_32B_tag;
-
-
-
-   typedef struct INTC_struct_tag { /* start of INTC_tag */
-      union {
-         INTC_BCR_32B_tag MCR;             /* deprecated - please avoid */
-
-                                   /* BCR - Block Configuration Register */
-         INTC_BCR_32B_tag BCR;             /* offset: 0x0000 size: 32 bit */
-
-      };
-      int8_t INTC_reserved_0004_C[4];
-      union {
-                        /* CPR - Current Priority Register - Processor 0 */
-         INTC_CPR_PRC0_32B_tag CPR_PRC0;   /* offset: 0x0008 size: 32 bit */
-
-         INTC_CPR_PRC0_32B_tag CPR;        /* deprecated - please avoid */
-
-      };
-                        /* CPR - Current Priority Register - Processor 1 */
-      INTC_CPR_PRC1_32B_tag CPR_PRC1;      /* offset: 0x000C size: 32 bit */
-      union {
-                  /* IACKR- Interrupt Acknowledge Register - Processor 0 */
-         INTC_IACKR_PRC0_32B_tag IACKR_PRC0;  /* offset: 0x0010 size: 32 bit */
-
-         INTC_IACKR_PRC0_32B_tag IACKR;    /* deprecated - please avoid */
-
-      };
-                  /* IACKR- Interrupt Acknowledge Register - Processor 1 */
-      INTC_IACKR_PRC1_32B_tag IACKR_PRC1;  /* offset: 0x0014 size: 32 bit */
-      union {
-                        /* EOIR- End of Interrupt Register - Processor 0 */
-         INTC_EOIR_PRC0_32B_tag EOIR_PRC0;  /* offset: 0x0018 size: 32 bit */
-
-         INTC_EOIR_PRC0_32B_tag EOIR;      /* deprecated - please avoid */
-
-      };
-                        /* EOIR- End of Interrupt Register - Processor 1 */
-      INTC_EOIR_PRC1_32B_tag EOIR_PRC1;    /* offset: 0x001C size: 32 bit */
-      union {
-                 /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
-         INTC_SSCIR_8B_tag SSCIR[8];       /* offset: 0x0020  (0x0001 x 8) */
-
-         struct {
-                 /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
-            INTC_SSCIR_8B_tag SSCIR0;      /* offset: 0x0020 size: 8 bit */
-            INTC_SSCIR_8B_tag SSCIR1;      /* offset: 0x0021 size: 8 bit */
-            INTC_SSCIR_8B_tag SSCIR2;      /* offset: 0x0022 size: 8 bit */
-            INTC_SSCIR_8B_tag SSCIR3;      /* offset: 0x0023 size: 8 bit */
-            INTC_SSCIR_8B_tag SSCIR4;      /* offset: 0x0024 size: 8 bit */
-            INTC_SSCIR_8B_tag SSCIR5;      /* offset: 0x0025 size: 8 bit */
-            INTC_SSCIR_8B_tag SSCIR6;      /* offset: 0x0026 size: 8 bit */
-            INTC_SSCIR_8B_tag SSCIR7;      /* offset: 0x0027 size: 8 bit */
-         };
-
-         struct {
-                    /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
-            INTC_SSCIR0_3_32B_tag SSCIR0_3;  /* offset: 0x0020 size: 32 bit */
-                    /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
-            INTC_SSCIR4_7_32B_tag SSCIR4_7;  /* offset: 0x0024 size: 32 bit */
-         };
-
-      };
-      int8_t INTC_reserved_0028_C[24];
-      union {
-                         /* PSR0_3 - 508_511 - Priority Select Registers */
-         INTC_PSR_32B_tag PSR_32B[128];    /* offset: 0x0040  (0x0004 x 128) */
-
-                                 /* PSR0-511 - Priority Select Registers */
-         INTC_PSR_8B_tag PSR[512];         /* offset: 0x0040  (0x0001 x 512) */
-
-         struct {
-                         /* PSR0_3 - 508_511 - Priority Select Registers */
-            INTC_PSR_32B_tag PSR0_3;       /* offset: 0x0040 size: 32 bit */
-            INTC_PSR_32B_tag PSR4_7;       /* offset: 0x0044 size: 32 bit */
-            INTC_PSR_32B_tag PSR8_11;      /* offset: 0x0048 size: 32 bit */
-            INTC_PSR_32B_tag PSR12_15;     /* offset: 0x004C size: 32 bit */
-            INTC_PSR_32B_tag PSR16_19;     /* offset: 0x0050 size: 32 bit */
-            INTC_PSR_32B_tag PSR20_23;     /* offset: 0x0054 size: 32 bit */
-            INTC_PSR_32B_tag PSR24_27;     /* offset: 0x0058 size: 32 bit */
-            INTC_PSR_32B_tag PSR28_31;     /* offset: 0x005C size: 32 bit */
-            INTC_PSR_32B_tag PSR32_35;     /* offset: 0x0060 size: 32 bit */
-            INTC_PSR_32B_tag PSR36_39;     /* offset: 0x0064 size: 32 bit */
-            INTC_PSR_32B_tag PSR40_43;     /* offset: 0x0068 size: 32 bit */
-            INTC_PSR_32B_tag PSR44_47;     /* offset: 0x006C size: 32 bit */
-            INTC_PSR_32B_tag PSR48_51;     /* offset: 0x0070 size: 32 bit */
-            INTC_PSR_32B_tag PSR52_55;     /* offset: 0x0074 size: 32 bit */
-            INTC_PSR_32B_tag PSR56_59;     /* offset: 0x0078 size: 32 bit */
-            INTC_PSR_32B_tag PSR60_63;     /* offset: 0x007C size: 32 bit */
-            INTC_PSR_32B_tag PSR64_67;     /* offset: 0x0080 size: 32 bit */
-            INTC_PSR_32B_tag PSR68_71;     /* offset: 0x0084 size: 32 bit */
-            INTC_PSR_32B_tag PSR72_75;     /* offset: 0x0088 size: 32 bit */
-            INTC_PSR_32B_tag PSR76_79;     /* offset: 0x008C size: 32 bit */
-            INTC_PSR_32B_tag PSR80_83;     /* offset: 0x0090 size: 32 bit */
-            INTC_PSR_32B_tag PSR84_87;     /* offset: 0x0094 size: 32 bit */
-            INTC_PSR_32B_tag PSR88_91;     /* offset: 0x0098 size: 32 bit */
-            INTC_PSR_32B_tag PSR92_95;     /* offset: 0x009C size: 32 bit */
-            INTC_PSR_32B_tag PSR96_99;     /* offset: 0x00A0 size: 32 bit */
-            INTC_PSR_32B_tag PSR100_103;   /* offset: 0x00A4 size: 32 bit */
-            INTC_PSR_32B_tag PSR104_107;   /* offset: 0x00A8 size: 32 bit */
-            INTC_PSR_32B_tag PSR108_111;   /* offset: 0x00AC size: 32 bit */
-            INTC_PSR_32B_tag PSR112_115;   /* offset: 0x00B0 size: 32 bit */
-            INTC_PSR_32B_tag PSR116_119;   /* offset: 0x00B4 size: 32 bit */
-            INTC_PSR_32B_tag PSR120_123;   /* offset: 0x00B8 size: 32 bit */
-            INTC_PSR_32B_tag PSR124_127;   /* offset: 0x00BC size: 32 bit */
-            INTC_PSR_32B_tag PSR128_131;   /* offset: 0x00C0 size: 32 bit */
-            INTC_PSR_32B_tag PSR132_135;   /* offset: 0x00C4 size: 32 bit */
-            INTC_PSR_32B_tag PSR136_139;   /* offset: 0x00C8 size: 32 bit */
-            INTC_PSR_32B_tag PSR140_143;   /* offset: 0x00CC size: 32 bit */
-            INTC_PSR_32B_tag PSR144_147;   /* offset: 0x00D0 size: 32 bit */
-            INTC_PSR_32B_tag PSR148_151;   /* offset: 0x00D4 size: 32 bit */
-            INTC_PSR_32B_tag PSR152_155;   /* offset: 0x00D8 size: 32 bit */
-            INTC_PSR_32B_tag PSR156_159;   /* offset: 0x00DC size: 32 bit */
-            INTC_PSR_32B_tag PSR160_163;   /* offset: 0x00E0 size: 32 bit */
-            INTC_PSR_32B_tag PSR164_167;   /* offset: 0x00E4 size: 32 bit */
-            INTC_PSR_32B_tag PSR168_171;   /* offset: 0x00E8 size: 32 bit */
-            INTC_PSR_32B_tag PSR172_175;   /* offset: 0x00EC size: 32 bit */
-            INTC_PSR_32B_tag PSR176_179;   /* offset: 0x00F0 size: 32 bit */
-            INTC_PSR_32B_tag PSR180_183;   /* offset: 0x00F4 size: 32 bit */
-            INTC_PSR_32B_tag PSR184_187;   /* offset: 0x00F8 size: 32 bit */
-            INTC_PSR_32B_tag PSR188_191;   /* offset: 0x00FC size: 32 bit */
-            INTC_PSR_32B_tag PSR192_195;   /* offset: 0x0100 size: 32 bit */
-            INTC_PSR_32B_tag PSR196_199;   /* offset: 0x0104 size: 32 bit */
-            INTC_PSR_32B_tag PSR200_203;   /* offset: 0x0108 size: 32 bit */
-            INTC_PSR_32B_tag PSR204_207;   /* offset: 0x010C size: 32 bit */
-            INTC_PSR_32B_tag PSR208_211;   /* offset: 0x0110 size: 32 bit */
-            INTC_PSR_32B_tag PSR212_215;   /* offset: 0x0114 size: 32 bit */
-            INTC_PSR_32B_tag PSR216_219;   /* offset: 0x0118 size: 32 bit */
-            INTC_PSR_32B_tag PSR220_223;   /* offset: 0x011C size: 32 bit */
-            INTC_PSR_32B_tag PSR224_227;   /* offset: 0x0120 size: 32 bit */
-            INTC_PSR_32B_tag PSR228_231;   /* offset: 0x0124 size: 32 bit */
-            INTC_PSR_32B_tag PSR232_235;   /* offset: 0x0128 size: 32 bit */
-            INTC_PSR_32B_tag PSR236_239;   /* offset: 0x012C size: 32 bit */
-            INTC_PSR_32B_tag PSR240_243;   /* offset: 0x0130 size: 32 bit */
-            INTC_PSR_32B_tag PSR244_247;   /* offset: 0x0134 size: 32 bit */
-            INTC_PSR_32B_tag PSR248_251;   /* offset: 0x0138 size: 32 bit */
-            INTC_PSR_32B_tag PSR252_255;   /* offset: 0x013C size: 32 bit */
-            INTC_PSR_32B_tag PSR256_259;   /* offset: 0x0140 size: 32 bit */
-            INTC_PSR_32B_tag PSR260_263;   /* offset: 0x0144 size: 32 bit */
-            INTC_PSR_32B_tag PSR264_267;   /* offset: 0x0148 size: 32 bit */
-            INTC_PSR_32B_tag PSR268_271;   /* offset: 0x014C size: 32 bit */
-            INTC_PSR_32B_tag PSR272_275;   /* offset: 0x0150 size: 32 bit */
-            INTC_PSR_32B_tag PSR276_279;   /* offset: 0x0154 size: 32 bit */
-            INTC_PSR_32B_tag PSR280_283;   /* offset: 0x0158 size: 32 bit */
-            INTC_PSR_32B_tag PSR284_287;   /* offset: 0x015C size: 32 bit */
-            INTC_PSR_32B_tag PSR288_291;   /* offset: 0x0160 size: 32 bit */
-            INTC_PSR_32B_tag PSR292_295;   /* offset: 0x0164 size: 32 bit */
-            INTC_PSR_32B_tag PSR296_299;   /* offset: 0x0168 size: 32 bit */
-            INTC_PSR_32B_tag PSR300_303;   /* offset: 0x016C size: 32 bit */
-            INTC_PSR_32B_tag PSR304_307;   /* offset: 0x0170 size: 32 bit */
-            INTC_PSR_32B_tag PSR308_311;   /* offset: 0x0174 size: 32 bit */
-            INTC_PSR_32B_tag PSR312_315;   /* offset: 0x0178 size: 32 bit */
-            INTC_PSR_32B_tag PSR316_319;   /* offset: 0x017C size: 32 bit */
-            INTC_PSR_32B_tag PSR320_323;   /* offset: 0x0180 size: 32 bit */
-            INTC_PSR_32B_tag PSR324_327;   /* offset: 0x0184 size: 32 bit */
-            INTC_PSR_32B_tag PSR328_331;   /* offset: 0x0188 size: 32 bit */
-            INTC_PSR_32B_tag PSR332_335;   /* offset: 0x018C size: 32 bit */
-            INTC_PSR_32B_tag PSR336_339;   /* offset: 0x0190 size: 32 bit */
-            INTC_PSR_32B_tag PSR340_343;   /* offset: 0x0194 size: 32 bit */
-            INTC_PSR_32B_tag PSR344_347;   /* offset: 0x0198 size: 32 bit */
-            INTC_PSR_32B_tag PSR348_351;   /* offset: 0x019C size: 32 bit */
-            INTC_PSR_32B_tag PSR352_355;   /* offset: 0x01A0 size: 32 bit */
-            INTC_PSR_32B_tag PSR356_359;   /* offset: 0x01A4 size: 32 bit */
-            INTC_PSR_32B_tag PSR360_363;   /* offset: 0x01A8 size: 32 bit */
-            INTC_PSR_32B_tag PSR364_367;   /* offset: 0x01AC size: 32 bit */
-            INTC_PSR_32B_tag PSR368_371;   /* offset: 0x01B0 size: 32 bit */
-            INTC_PSR_32B_tag PSR372_375;   /* offset: 0x01B4 size: 32 bit */
-            INTC_PSR_32B_tag PSR376_379;   /* offset: 0x01B8 size: 32 bit */
-            INTC_PSR_32B_tag PSR380_383;   /* offset: 0x01BC size: 32 bit */
-            INTC_PSR_32B_tag PSR384_387;   /* offset: 0x01C0 size: 32 bit */
-            INTC_PSR_32B_tag PSR388_391;   /* offset: 0x01C4 size: 32 bit */
-            INTC_PSR_32B_tag PSR392_395;   /* offset: 0x01C8 size: 32 bit */
-            INTC_PSR_32B_tag PSR396_399;   /* offset: 0x01CC size: 32 bit */
-            INTC_PSR_32B_tag PSR400_403;   /* offset: 0x01D0 size: 32 bit */
-            INTC_PSR_32B_tag PSR404_407;   /* offset: 0x01D4 size: 32 bit */
-            INTC_PSR_32B_tag PSR408_411;   /* offset: 0x01D8 size: 32 bit */
-            INTC_PSR_32B_tag PSR412_415;   /* offset: 0x01DC size: 32 bit */
-            INTC_PSR_32B_tag PSR416_419;   /* offset: 0x01E0 size: 32 bit */
-            INTC_PSR_32B_tag PSR420_423;   /* offset: 0x01E4 size: 32 bit */
-            INTC_PSR_32B_tag PSR424_427;   /* offset: 0x01E8 size: 32 bit */
-            INTC_PSR_32B_tag PSR428_431;   /* offset: 0x01EC size: 32 bit */
-            INTC_PSR_32B_tag PSR432_435;   /* offset: 0x01F0 size: 32 bit */
-            INTC_PSR_32B_tag PSR436_439;   /* offset: 0x01F4 size: 32 bit */
-            INTC_PSR_32B_tag PSR440_443;   /* offset: 0x01F8 size: 32 bit */
-            INTC_PSR_32B_tag PSR444_447;   /* offset: 0x01FC size: 32 bit */
-            INTC_PSR_32B_tag PSR448_451;   /* offset: 0x0200 size: 32 bit */
-            INTC_PSR_32B_tag PSR452_455;   /* offset: 0x0204 size: 32 bit */
-            INTC_PSR_32B_tag PSR456_459;   /* offset: 0x0208 size: 32 bit */
-            INTC_PSR_32B_tag PSR460_463;   /* offset: 0x020C size: 32 bit */
-            INTC_PSR_32B_tag PSR464_467;   /* offset: 0x0210 size: 32 bit */
-            INTC_PSR_32B_tag PSR468_471;   /* offset: 0x0214 size: 32 bit */
-            INTC_PSR_32B_tag PSR472_475;   /* offset: 0x0218 size: 32 bit */
-            INTC_PSR_32B_tag PSR476_479;   /* offset: 0x021C size: 32 bit */
-            INTC_PSR_32B_tag PSR480_483;   /* offset: 0x0220 size: 32 bit */
-            INTC_PSR_32B_tag PSR484_487;   /* offset: 0x0224 size: 32 bit */
-            INTC_PSR_32B_tag PSR488_491;   /* offset: 0x0228 size: 32 bit */
-            INTC_PSR_32B_tag PSR492_495;   /* offset: 0x022C size: 32 bit */
-            INTC_PSR_32B_tag PSR496_499;   /* offset: 0x0230 size: 32 bit */
-            INTC_PSR_32B_tag PSR500_503;   /* offset: 0x0234 size: 32 bit */
-            INTC_PSR_32B_tag PSR504_507;   /* offset: 0x0238 size: 32 bit */
-            INTC_PSR_32B_tag PSR508_511;   /* offset: 0x023C size: 32 bit */
-         };
-
-         struct {
-                                 /* PSR0-511 - Priority Select Registers */
-            INTC_PSR_8B_tag PSR0;          /* offset: 0x0040 size: 8 bit */
-            INTC_PSR_8B_tag PSR1;          /* offset: 0x0041 size: 8 bit */
-            INTC_PSR_8B_tag PSR2;          /* offset: 0x0042 size: 8 bit */
-            INTC_PSR_8B_tag PSR3;          /* offset: 0x0043 size: 8 bit */
-            INTC_PSR_8B_tag PSR4;          /* offset: 0x0044 size: 8 bit */
-            INTC_PSR_8B_tag PSR5;          /* offset: 0x0045 size: 8 bit */
-            INTC_PSR_8B_tag PSR6;          /* offset: 0x0046 size: 8 bit */
-            INTC_PSR_8B_tag PSR7;          /* offset: 0x0047 size: 8 bit */
-            INTC_PSR_8B_tag PSR8;          /* offset: 0x0048 size: 8 bit */
-            INTC_PSR_8B_tag PSR9;          /* offset: 0x0049 size: 8 bit */
-            INTC_PSR_8B_tag PSR10;         /* offset: 0x004A size: 8 bit */
-            INTC_PSR_8B_tag PSR11;         /* offset: 0x004B size: 8 bit */
-            INTC_PSR_8B_tag PSR12;         /* offset: 0x004C size: 8 bit */
-            INTC_PSR_8B_tag PSR13;         /* offset: 0x004D size: 8 bit */
-            INTC_PSR_8B_tag PSR14;         /* offset: 0x004E size: 8 bit */
-            INTC_PSR_8B_tag PSR15;         /* offset: 0x004F size: 8 bit */
-            INTC_PSR_8B_tag PSR16;         /* offset: 0x0050 size: 8 bit */
-            INTC_PSR_8B_tag PSR17;         /* offset: 0x0051 size: 8 bit */
-            INTC_PSR_8B_tag PSR18;         /* offset: 0x0052 size: 8 bit */
-            INTC_PSR_8B_tag PSR19;         /* offset: 0x0053 size: 8 bit */
-            INTC_PSR_8B_tag PSR20;         /* offset: 0x0054 size: 8 bit */
-            INTC_PSR_8B_tag PSR21;         /* offset: 0x0055 size: 8 bit */
-            INTC_PSR_8B_tag PSR22;         /* offset: 0x0056 size: 8 bit */
-            INTC_PSR_8B_tag PSR23;         /* offset: 0x0057 size: 8 bit */
-            INTC_PSR_8B_tag PSR24;         /* offset: 0x0058 size: 8 bit */
-            INTC_PSR_8B_tag PSR25;         /* offset: 0x0059 size: 8 bit */
-            INTC_PSR_8B_tag PSR26;         /* offset: 0x005A size: 8 bit */
-            INTC_PSR_8B_tag PSR27;         /* offset: 0x005B size: 8 bit */
-            INTC_PSR_8B_tag PSR28;         /* offset: 0x005C size: 8 bit */
-            INTC_PSR_8B_tag PSR29;         /* offset: 0x005D size: 8 bit */
-            INTC_PSR_8B_tag PSR30;         /* offset: 0x005E size: 8 bit */
-            INTC_PSR_8B_tag PSR31;         /* offset: 0x005F size: 8 bit */
-            INTC_PSR_8B_tag PSR32;         /* offset: 0x0060 size: 8 bit */
-            INTC_PSR_8B_tag PSR33;         /* offset: 0x0061 size: 8 bit */
-            INTC_PSR_8B_tag PSR34;         /* offset: 0x0062 size: 8 bit */
-            INTC_PSR_8B_tag PSR35;         /* offset: 0x0063 size: 8 bit */
-            INTC_PSR_8B_tag PSR36;         /* offset: 0x0064 size: 8 bit */
-            INTC_PSR_8B_tag PSR37;         /* offset: 0x0065 size: 8 bit */
-            INTC_PSR_8B_tag PSR38;         /* offset: 0x0066 size: 8 bit */
-            INTC_PSR_8B_tag PSR39;         /* offset: 0x0067 size: 8 bit */
-            INTC_PSR_8B_tag PSR40;         /* offset: 0x0068 size: 8 bit */
-            INTC_PSR_8B_tag PSR41;         /* offset: 0x0069 size: 8 bit */
-            INTC_PSR_8B_tag PSR42;         /* offset: 0x006A size: 8 bit */
-            INTC_PSR_8B_tag PSR43;         /* offset: 0x006B size: 8 bit */
-            INTC_PSR_8B_tag PSR44;         /* offset: 0x006C size: 8 bit */
-            INTC_PSR_8B_tag PSR45;         /* offset: 0x006D size: 8 bit */
-            INTC_PSR_8B_tag PSR46;         /* offset: 0x006E size: 8 bit */
-            INTC_PSR_8B_tag PSR47;         /* offset: 0x006F size: 8 bit */
-            INTC_PSR_8B_tag PSR48;         /* offset: 0x0070 size: 8 bit */
-            INTC_PSR_8B_tag PSR49;         /* offset: 0x0071 size: 8 bit */
-            INTC_PSR_8B_tag PSR50;         /* offset: 0x0072 size: 8 bit */
-            INTC_PSR_8B_tag PSR51;         /* offset: 0x0073 size: 8 bit */
-            INTC_PSR_8B_tag PSR52;         /* offset: 0x0074 size: 8 bit */
-            INTC_PSR_8B_tag PSR53;         /* offset: 0x0075 size: 8 bit */
-            INTC_PSR_8B_tag PSR54;         /* offset: 0x0076 size: 8 bit */
-            INTC_PSR_8B_tag PSR55;         /* offset: 0x0077 size: 8 bit */
-            INTC_PSR_8B_tag PSR56;         /* offset: 0x0078 size: 8 bit */
-            INTC_PSR_8B_tag PSR57;         /* offset: 0x0079 size: 8 bit */
-            INTC_PSR_8B_tag PSR58;         /* offset: 0x007A size: 8 bit */
-            INTC_PSR_8B_tag PSR59;         /* offset: 0x007B size: 8 bit */
-            INTC_PSR_8B_tag PSR60;         /* offset: 0x007C size: 8 bit */
-            INTC_PSR_8B_tag PSR61;         /* offset: 0x007D size: 8 bit */
-            INTC_PSR_8B_tag PSR62;         /* offset: 0x007E size: 8 bit */
-            INTC_PSR_8B_tag PSR63;         /* offset: 0x007F size: 8 bit */
-            INTC_PSR_8B_tag PSR64;         /* offset: 0x0080 size: 8 bit */
-            INTC_PSR_8B_tag PSR65;         /* offset: 0x0081 size: 8 bit */
-            INTC_PSR_8B_tag PSR66;         /* offset: 0x0082 size: 8 bit */
-            INTC_PSR_8B_tag PSR67;         /* offset: 0x0083 size: 8 bit */
-            INTC_PSR_8B_tag PSR68;         /* offset: 0x0084 size: 8 bit */
-            INTC_PSR_8B_tag PSR69;         /* offset: 0x0085 size: 8 bit */
-            INTC_PSR_8B_tag PSR70;         /* offset: 0x0086 size: 8 bit */
-            INTC_PSR_8B_tag PSR71;         /* offset: 0x0087 size: 8 bit */
-            INTC_PSR_8B_tag PSR72;         /* offset: 0x0088 size: 8 bit */
-            INTC_PSR_8B_tag PSR73;         /* offset: 0x0089 size: 8 bit */
-            INTC_PSR_8B_tag PSR74;         /* offset: 0x008A size: 8 bit */
-            INTC_PSR_8B_tag PSR75;         /* offset: 0x008B size: 8 bit */
-            INTC_PSR_8B_tag PSR76;         /* offset: 0x008C size: 8 bit */
-            INTC_PSR_8B_tag PSR77;         /* offset: 0x008D size: 8 bit */
-            INTC_PSR_8B_tag PSR78;         /* offset: 0x008E size: 8 bit */
-            INTC_PSR_8B_tag PSR79;         /* offset: 0x008F size: 8 bit */
-            INTC_PSR_8B_tag PSR80;         /* offset: 0x0090 size: 8 bit */
-            INTC_PSR_8B_tag PSR81;         /* offset: 0x0091 size: 8 bit */
-            INTC_PSR_8B_tag PSR82;         /* offset: 0x0092 size: 8 bit */
-            INTC_PSR_8B_tag PSR83;         /* offset: 0x0093 size: 8 bit */
-            INTC_PSR_8B_tag PSR84;         /* offset: 0x0094 size: 8 bit */
-            INTC_PSR_8B_tag PSR85;         /* offset: 0x0095 size: 8 bit */
-            INTC_PSR_8B_tag PSR86;         /* offset: 0x0096 size: 8 bit */
-            INTC_PSR_8B_tag PSR87;         /* offset: 0x0097 size: 8 bit */
-            INTC_PSR_8B_tag PSR88;         /* offset: 0x0098 size: 8 bit */
-            INTC_PSR_8B_tag PSR89;         /* offset: 0x0099 size: 8 bit */
-            INTC_PSR_8B_tag PSR90;         /* offset: 0x009A size: 8 bit */
-            INTC_PSR_8B_tag PSR91;         /* offset: 0x009B size: 8 bit */
-            INTC_PSR_8B_tag PSR92;         /* offset: 0x009C size: 8 bit */
-            INTC_PSR_8B_tag PSR93;         /* offset: 0x009D size: 8 bit */
-            INTC_PSR_8B_tag PSR94;         /* offset: 0x009E size: 8 bit */
-            INTC_PSR_8B_tag PSR95;         /* offset: 0x009F size: 8 bit */
-            INTC_PSR_8B_tag PSR96;         /* offset: 0x00A0 size: 8 bit */
-            INTC_PSR_8B_tag PSR97;         /* offset: 0x00A1 size: 8 bit */
-            INTC_PSR_8B_tag PSR98;         /* offset: 0x00A2 size: 8 bit */
-            INTC_PSR_8B_tag PSR99;         /* offset: 0x00A3 size: 8 bit */
-            INTC_PSR_8B_tag PSR100;        /* offset: 0x00A4 size: 8 bit */
-            INTC_PSR_8B_tag PSR101;        /* offset: 0x00A5 size: 8 bit */
-            INTC_PSR_8B_tag PSR102;        /* offset: 0x00A6 size: 8 bit */
-            INTC_PSR_8B_tag PSR103;        /* offset: 0x00A7 size: 8 bit */
-            INTC_PSR_8B_tag PSR104;        /* offset: 0x00A8 size: 8 bit */
-            INTC_PSR_8B_tag PSR105;        /* offset: 0x00A9 size: 8 bit */
-            INTC_PSR_8B_tag PSR106;        /* offset: 0x00AA size: 8 bit */
-            INTC_PSR_8B_tag PSR107;        /* offset: 0x00AB size: 8 bit */
-            INTC_PSR_8B_tag PSR108;        /* offset: 0x00AC size: 8 bit */
-            INTC_PSR_8B_tag PSR109;        /* offset: 0x00AD size: 8 bit */
-            INTC_PSR_8B_tag PSR110;        /* offset: 0x00AE size: 8 bit */
-            INTC_PSR_8B_tag PSR111;        /* offset: 0x00AF size: 8 bit */
-            INTC_PSR_8B_tag PSR112;        /* offset: 0x00B0 size: 8 bit */
-            INTC_PSR_8B_tag PSR113;        /* offset: 0x00B1 size: 8 bit */
-            INTC_PSR_8B_tag PSR114;        /* offset: 0x00B2 size: 8 bit */
-            INTC_PSR_8B_tag PSR115;        /* offset: 0x00B3 size: 8 bit */
-            INTC_PSR_8B_tag PSR116;        /* offset: 0x00B4 size: 8 bit */
-            INTC_PSR_8B_tag PSR117;        /* offset: 0x00B5 size: 8 bit */
-            INTC_PSR_8B_tag PSR118;        /* offset: 0x00B6 size: 8 bit */
-            INTC_PSR_8B_tag PSR119;        /* offset: 0x00B7 size: 8 bit */
-            INTC_PSR_8B_tag PSR120;        /* offset: 0x00B8 size: 8 bit */
-            INTC_PSR_8B_tag PSR121;        /* offset: 0x00B9 size: 8 bit */
-            INTC_PSR_8B_tag PSR122;        /* offset: 0x00BA size: 8 bit */
-            INTC_PSR_8B_tag PSR123;        /* offset: 0x00BB size: 8 bit */
-            INTC_PSR_8B_tag PSR124;        /* offset: 0x00BC size: 8 bit */
-            INTC_PSR_8B_tag PSR125;        /* offset: 0x00BD size: 8 bit */
-            INTC_PSR_8B_tag PSR126;        /* offset: 0x00BE size: 8 bit */
-            INTC_PSR_8B_tag PSR127;        /* offset: 0x00BF size: 8 bit */
-            INTC_PSR_8B_tag PSR128;        /* offset: 0x00C0 size: 8 bit */
-            INTC_PSR_8B_tag PSR129;        /* offset: 0x00C1 size: 8 bit */
-            INTC_PSR_8B_tag PSR130;        /* offset: 0x00C2 size: 8 bit */
-            INTC_PSR_8B_tag PSR131;        /* offset: 0x00C3 size: 8 bit */
-            INTC_PSR_8B_tag PSR132;        /* offset: 0x00C4 size: 8 bit */
-            INTC_PSR_8B_tag PSR133;        /* offset: 0x00C5 size: 8 bit */
-            INTC_PSR_8B_tag PSR134;        /* offset: 0x00C6 size: 8 bit */
-            INTC_PSR_8B_tag PSR135;        /* offset: 0x00C7 size: 8 bit */
-            INTC_PSR_8B_tag PSR136;        /* offset: 0x00C8 size: 8 bit */
-            INTC_PSR_8B_tag PSR137;        /* offset: 0x00C9 size: 8 bit */
-            INTC_PSR_8B_tag PSR138;        /* offset: 0x00CA size: 8 bit */
-            INTC_PSR_8B_tag PSR139;        /* offset: 0x00CB size: 8 bit */
-            INTC_PSR_8B_tag PSR140;        /* offset: 0x00CC size: 8 bit */
-            INTC_PSR_8B_tag PSR141;        /* offset: 0x00CD size: 8 bit */
-            INTC_PSR_8B_tag PSR142;        /* offset: 0x00CE size: 8 bit */
-            INTC_PSR_8B_tag PSR143;        /* offset: 0x00CF size: 8 bit */
-            INTC_PSR_8B_tag PSR144;        /* offset: 0x00D0 size: 8 bit */
-            INTC_PSR_8B_tag PSR145;        /* offset: 0x00D1 size: 8 bit */
-            INTC_PSR_8B_tag PSR146;        /* offset: 0x00D2 size: 8 bit */
-            INTC_PSR_8B_tag PSR147;        /* offset: 0x00D3 size: 8 bit */
-            INTC_PSR_8B_tag PSR148;        /* offset: 0x00D4 size: 8 bit */
-            INTC_PSR_8B_tag PSR149;        /* offset: 0x00D5 size: 8 bit */
-            INTC_PSR_8B_tag PSR150;        /* offset: 0x00D6 size: 8 bit */
-            INTC_PSR_8B_tag PSR151;        /* offset: 0x00D7 size: 8 bit */
-            INTC_PSR_8B_tag PSR152;        /* offset: 0x00D8 size: 8 bit */
-            INTC_PSR_8B_tag PSR153;        /* offset: 0x00D9 size: 8 bit */
-            INTC_PSR_8B_tag PSR154;        /* offset: 0x00DA size: 8 bit */
-            INTC_PSR_8B_tag PSR155;        /* offset: 0x00DB size: 8 bit */
-            INTC_PSR_8B_tag PSR156;        /* offset: 0x00DC size: 8 bit */
-            INTC_PSR_8B_tag PSR157;        /* offset: 0x00DD size: 8 bit */
-            INTC_PSR_8B_tag PSR158;        /* offset: 0x00DE size: 8 bit */
-            INTC_PSR_8B_tag PSR159;        /* offset: 0x00DF size: 8 bit */
-            INTC_PSR_8B_tag PSR160;        /* offset: 0x00E0 size: 8 bit */
-            INTC_PSR_8B_tag PSR161;        /* offset: 0x00E1 size: 8 bit */
-            INTC_PSR_8B_tag PSR162;        /* offset: 0x00E2 size: 8 bit */
-            INTC_PSR_8B_tag PSR163;        /* offset: 0x00E3 size: 8 bit */
-            INTC_PSR_8B_tag PSR164;        /* offset: 0x00E4 size: 8 bit */
-            INTC_PSR_8B_tag PSR165;        /* offset: 0x00E5 size: 8 bit */
-            INTC_PSR_8B_tag PSR166;        /* offset: 0x00E6 size: 8 bit */
-            INTC_PSR_8B_tag PSR167;        /* offset: 0x00E7 size: 8 bit */
-            INTC_PSR_8B_tag PSR168;        /* offset: 0x00E8 size: 8 bit */
-            INTC_PSR_8B_tag PSR169;        /* offset: 0x00E9 size: 8 bit */
-            INTC_PSR_8B_tag PSR170;        /* offset: 0x00EA size: 8 bit */
-            INTC_PSR_8B_tag PSR171;        /* offset: 0x00EB size: 8 bit */
-            INTC_PSR_8B_tag PSR172;        /* offset: 0x00EC size: 8 bit */
-            INTC_PSR_8B_tag PSR173;        /* offset: 0x00ED size: 8 bit */
-            INTC_PSR_8B_tag PSR174;        /* offset: 0x00EE size: 8 bit */
-            INTC_PSR_8B_tag PSR175;        /* offset: 0x00EF size: 8 bit */
-            INTC_PSR_8B_tag PSR176;        /* offset: 0x00F0 size: 8 bit */
-            INTC_PSR_8B_tag PSR177;        /* offset: 0x00F1 size: 8 bit */
-            INTC_PSR_8B_tag PSR178;        /* offset: 0x00F2 size: 8 bit */
-            INTC_PSR_8B_tag PSR179;        /* offset: 0x00F3 size: 8 bit */
-            INTC_PSR_8B_tag PSR180;        /* offset: 0x00F4 size: 8 bit */
-            INTC_PSR_8B_tag PSR181;        /* offset: 0x00F5 size: 8 bit */
-            INTC_PSR_8B_tag PSR182;        /* offset: 0x00F6 size: 8 bit */
-            INTC_PSR_8B_tag PSR183;        /* offset: 0x00F7 size: 8 bit */
-            INTC_PSR_8B_tag PSR184;        /* offset: 0x00F8 size: 8 bit */
-            INTC_PSR_8B_tag PSR185;        /* offset: 0x00F9 size: 8 bit */
-            INTC_PSR_8B_tag PSR186;        /* offset: 0x00FA size: 8 bit */
-            INTC_PSR_8B_tag PSR187;        /* offset: 0x00FB size: 8 bit */
-            INTC_PSR_8B_tag PSR188;        /* offset: 0x00FC size: 8 bit */
-            INTC_PSR_8B_tag PSR189;        /* offset: 0x00FD size: 8 bit */
-            INTC_PSR_8B_tag PSR190;        /* offset: 0x00FE size: 8 bit */
-            INTC_PSR_8B_tag PSR191;        /* offset: 0x00FF size: 8 bit */
-            INTC_PSR_8B_tag PSR192;        /* offset: 0x0100 size: 8 bit */
-            INTC_PSR_8B_tag PSR193;        /* offset: 0x0101 size: 8 bit */
-            INTC_PSR_8B_tag PSR194;        /* offset: 0x0102 size: 8 bit */
-            INTC_PSR_8B_tag PSR195;        /* offset: 0x0103 size: 8 bit */
-            INTC_PSR_8B_tag PSR196;        /* offset: 0x0104 size: 8 bit */
-            INTC_PSR_8B_tag PSR197;        /* offset: 0x0105 size: 8 bit */
-            INTC_PSR_8B_tag PSR198;        /* offset: 0x0106 size: 8 bit */
-            INTC_PSR_8B_tag PSR199;        /* offset: 0x0107 size: 8 bit */
-            INTC_PSR_8B_tag PSR200;        /* offset: 0x0108 size: 8 bit */
-            INTC_PSR_8B_tag PSR201;        /* offset: 0x0109 size: 8 bit */
-            INTC_PSR_8B_tag PSR202;        /* offset: 0x010A size: 8 bit */
-            INTC_PSR_8B_tag PSR203;        /* offset: 0x010B size: 8 bit */
-            INTC_PSR_8B_tag PSR204;        /* offset: 0x010C size: 8 bit */
-            INTC_PSR_8B_tag PSR205;        /* offset: 0x010D size: 8 bit */
-            INTC_PSR_8B_tag PSR206;        /* offset: 0x010E size: 8 bit */
-            INTC_PSR_8B_tag PSR207;        /* offset: 0x010F size: 8 bit */
-            INTC_PSR_8B_tag PSR208;        /* offset: 0x0110 size: 8 bit */
-            INTC_PSR_8B_tag PSR209;        /* offset: 0x0111 size: 8 bit */
-            INTC_PSR_8B_tag PSR210;        /* offset: 0x0112 size: 8 bit */
-            INTC_PSR_8B_tag PSR211;        /* offset: 0x0113 size: 8 bit */
-            INTC_PSR_8B_tag PSR212;        /* offset: 0x0114 size: 8 bit */
-            INTC_PSR_8B_tag PSR213;        /* offset: 0x0115 size: 8 bit */
-            INTC_PSR_8B_tag PSR214;        /* offset: 0x0116 size: 8 bit */
-            INTC_PSR_8B_tag PSR215;        /* offset: 0x0117 size: 8 bit */
-            INTC_PSR_8B_tag PSR216;        /* offset: 0x0118 size: 8 bit */
-            INTC_PSR_8B_tag PSR217;        /* offset: 0x0119 size: 8 bit */
-            INTC_PSR_8B_tag PSR218;        /* offset: 0x011A size: 8 bit */
-            INTC_PSR_8B_tag PSR219;        /* offset: 0x011B size: 8 bit */
-            INTC_PSR_8B_tag PSR220;        /* offset: 0x011C size: 8 bit */
-            INTC_PSR_8B_tag PSR221;        /* offset: 0x011D size: 8 bit */
-            INTC_PSR_8B_tag PSR222;        /* offset: 0x011E size: 8 bit */
-            INTC_PSR_8B_tag PSR223;        /* offset: 0x011F size: 8 bit */
-            INTC_PSR_8B_tag PSR224;        /* offset: 0x0120 size: 8 bit */
-            INTC_PSR_8B_tag PSR225;        /* offset: 0x0121 size: 8 bit */
-            INTC_PSR_8B_tag PSR226;        /* offset: 0x0122 size: 8 bit */
-            INTC_PSR_8B_tag PSR227;        /* offset: 0x0123 size: 8 bit */
-            INTC_PSR_8B_tag PSR228;        /* offset: 0x0124 size: 8 bit */
-            INTC_PSR_8B_tag PSR229;        /* offset: 0x0125 size: 8 bit */
-            INTC_PSR_8B_tag PSR230;        /* offset: 0x0126 size: 8 bit */
-            INTC_PSR_8B_tag PSR231;        /* offset: 0x0127 size: 8 bit */
-            INTC_PSR_8B_tag PSR232;        /* offset: 0x0128 size: 8 bit */
-            INTC_PSR_8B_tag PSR233;        /* offset: 0x0129 size: 8 bit */
-            INTC_PSR_8B_tag PSR234;        /* offset: 0x012A size: 8 bit */
-            INTC_PSR_8B_tag PSR235;        /* offset: 0x012B size: 8 bit */
-            INTC_PSR_8B_tag PSR236;        /* offset: 0x012C size: 8 bit */
-            INTC_PSR_8B_tag PSR237;        /* offset: 0x012D size: 8 bit */
-            INTC_PSR_8B_tag PSR238;        /* offset: 0x012E size: 8 bit */
-            INTC_PSR_8B_tag PSR239;        /* offset: 0x012F size: 8 bit */
-            INTC_PSR_8B_tag PSR240;        /* offset: 0x0130 size: 8 bit */
-            INTC_PSR_8B_tag PSR241;        /* offset: 0x0131 size: 8 bit */
-            INTC_PSR_8B_tag PSR242;        /* offset: 0x0132 size: 8 bit */
-            INTC_PSR_8B_tag PSR243;        /* offset: 0x0133 size: 8 bit */
-            INTC_PSR_8B_tag PSR244;        /* offset: 0x0134 size: 8 bit */
-            INTC_PSR_8B_tag PSR245;        /* offset: 0x0135 size: 8 bit */
-            INTC_PSR_8B_tag PSR246;        /* offset: 0x0136 size: 8 bit */
-            INTC_PSR_8B_tag PSR247;        /* offset: 0x0137 size: 8 bit */
-            INTC_PSR_8B_tag PSR248;        /* offset: 0x0138 size: 8 bit */
-            INTC_PSR_8B_tag PSR249;        /* offset: 0x0139 size: 8 bit */
-            INTC_PSR_8B_tag PSR250;        /* offset: 0x013A size: 8 bit */
-            INTC_PSR_8B_tag PSR251;        /* offset: 0x013B size: 8 bit */
-            INTC_PSR_8B_tag PSR252;        /* offset: 0x013C size: 8 bit */
-            INTC_PSR_8B_tag PSR253;        /* offset: 0x013D size: 8 bit */
-            INTC_PSR_8B_tag PSR254;        /* offset: 0x013E size: 8 bit */
-            INTC_PSR_8B_tag PSR255;        /* offset: 0x013F size: 8 bit */
-            INTC_PSR_8B_tag PSR256;        /* offset: 0x0140 size: 8 bit */
-            INTC_PSR_8B_tag PSR257;        /* offset: 0x0141 size: 8 bit */
-            INTC_PSR_8B_tag PSR258;        /* offset: 0x0142 size: 8 bit */
-            INTC_PSR_8B_tag PSR259;        /* offset: 0x0143 size: 8 bit */
-            INTC_PSR_8B_tag PSR260;        /* offset: 0x0144 size: 8 bit */
-            INTC_PSR_8B_tag PSR261;        /* offset: 0x0145 size: 8 bit */
-            INTC_PSR_8B_tag PSR262;        /* offset: 0x0146 size: 8 bit */
-            INTC_PSR_8B_tag PSR263;        /* offset: 0x0147 size: 8 bit */
-            INTC_PSR_8B_tag PSR264;        /* offset: 0x0148 size: 8 bit */
-            INTC_PSR_8B_tag PSR265;        /* offset: 0x0149 size: 8 bit */
-            INTC_PSR_8B_tag PSR266;        /* offset: 0x014A size: 8 bit */
-            INTC_PSR_8B_tag PSR267;        /* offset: 0x014B size: 8 bit */
-            INTC_PSR_8B_tag PSR268;        /* offset: 0x014C size: 8 bit */
-            INTC_PSR_8B_tag PSR269;        /* offset: 0x014D size: 8 bit */
-            INTC_PSR_8B_tag PSR270;        /* offset: 0x014E size: 8 bit */
-            INTC_PSR_8B_tag PSR271;        /* offset: 0x014F size: 8 bit */
-            INTC_PSR_8B_tag PSR272;        /* offset: 0x0150 size: 8 bit */
-            INTC_PSR_8B_tag PSR273;        /* offset: 0x0151 size: 8 bit */
-            INTC_PSR_8B_tag PSR274;        /* offset: 0x0152 size: 8 bit */
-            INTC_PSR_8B_tag PSR275;        /* offset: 0x0153 size: 8 bit */
-            INTC_PSR_8B_tag PSR276;        /* offset: 0x0154 size: 8 bit */
-            INTC_PSR_8B_tag PSR277;        /* offset: 0x0155 size: 8 bit */
-            INTC_PSR_8B_tag PSR278;        /* offset: 0x0156 size: 8 bit */
-            INTC_PSR_8B_tag PSR279;        /* offset: 0x0157 size: 8 bit */
-            INTC_PSR_8B_tag PSR280;        /* offset: 0x0158 size: 8 bit */
-            INTC_PSR_8B_tag PSR281;        /* offset: 0x0159 size: 8 bit */
-            INTC_PSR_8B_tag PSR282;        /* offset: 0x015A size: 8 bit */
-            INTC_PSR_8B_tag PSR283;        /* offset: 0x015B size: 8 bit */
-            INTC_PSR_8B_tag PSR284;        /* offset: 0x015C size: 8 bit */
-            INTC_PSR_8B_tag PSR285;        /* offset: 0x015D size: 8 bit */
-            INTC_PSR_8B_tag PSR286;        /* offset: 0x015E size: 8 bit */
-            INTC_PSR_8B_tag PSR287;        /* offset: 0x015F size: 8 bit */
-            INTC_PSR_8B_tag PSR288;        /* offset: 0x0160 size: 8 bit */
-            INTC_PSR_8B_tag PSR289;        /* offset: 0x0161 size: 8 bit */
-            INTC_PSR_8B_tag PSR290;        /* offset: 0x0162 size: 8 bit */
-            INTC_PSR_8B_tag PSR291;        /* offset: 0x0163 size: 8 bit */
-            INTC_PSR_8B_tag PSR292;        /* offset: 0x0164 size: 8 bit */
-            INTC_PSR_8B_tag PSR293;        /* offset: 0x0165 size: 8 bit */
-            INTC_PSR_8B_tag PSR294;        /* offset: 0x0166 size: 8 bit */
-            INTC_PSR_8B_tag PSR295;        /* offset: 0x0167 size: 8 bit */
-            INTC_PSR_8B_tag PSR296;        /* offset: 0x0168 size: 8 bit */
-            INTC_PSR_8B_tag PSR297;        /* offset: 0x0169 size: 8 bit */
-            INTC_PSR_8B_tag PSR298;        /* offset: 0x016A size: 8 bit */
-            INTC_PSR_8B_tag PSR299;        /* offset: 0x016B size: 8 bit */
-            INTC_PSR_8B_tag PSR300;        /* offset: 0x016C size: 8 bit */
-            INTC_PSR_8B_tag PSR301;        /* offset: 0x016D size: 8 bit */
-            INTC_PSR_8B_tag PSR302;        /* offset: 0x016E size: 8 bit */
-            INTC_PSR_8B_tag PSR303;        /* offset: 0x016F size: 8 bit */
-            INTC_PSR_8B_tag PSR304;        /* offset: 0x0170 size: 8 bit */
-            INTC_PSR_8B_tag PSR305;        /* offset: 0x0171 size: 8 bit */
-            INTC_PSR_8B_tag PSR306;        /* offset: 0x0172 size: 8 bit */
-            INTC_PSR_8B_tag PSR307;        /* offset: 0x0173 size: 8 bit */
-            INTC_PSR_8B_tag PSR308;        /* offset: 0x0174 size: 8 bit */
-            INTC_PSR_8B_tag PSR309;        /* offset: 0x0175 size: 8 bit */
-            INTC_PSR_8B_tag PSR310;        /* offset: 0x0176 size: 8 bit */
-            INTC_PSR_8B_tag PSR311;        /* offset: 0x0177 size: 8 bit */
-            INTC_PSR_8B_tag PSR312;        /* offset: 0x0178 size: 8 bit */
-            INTC_PSR_8B_tag PSR313;        /* offset: 0x0179 size: 8 bit */
-            INTC_PSR_8B_tag PSR314;        /* offset: 0x017A size: 8 bit */
-            INTC_PSR_8B_tag PSR315;        /* offset: 0x017B size: 8 bit */
-            INTC_PSR_8B_tag PSR316;        /* offset: 0x017C size: 8 bit */
-            INTC_PSR_8B_tag PSR317;        /* offset: 0x017D size: 8 bit */
-            INTC_PSR_8B_tag PSR318;        /* offset: 0x017E size: 8 bit */
-            INTC_PSR_8B_tag PSR319;        /* offset: 0x017F size: 8 bit */
-            INTC_PSR_8B_tag PSR320;        /* offset: 0x0180 size: 8 bit */
-            INTC_PSR_8B_tag PSR321;        /* offset: 0x0181 size: 8 bit */
-            INTC_PSR_8B_tag PSR322;        /* offset: 0x0182 size: 8 bit */
-            INTC_PSR_8B_tag PSR323;        /* offset: 0x0183 size: 8 bit */
-            INTC_PSR_8B_tag PSR324;        /* offset: 0x0184 size: 8 bit */
-            INTC_PSR_8B_tag PSR325;        /* offset: 0x0185 size: 8 bit */
-            INTC_PSR_8B_tag PSR326;        /* offset: 0x0186 size: 8 bit */
-            INTC_PSR_8B_tag PSR327;        /* offset: 0x0187 size: 8 bit */
-            INTC_PSR_8B_tag PSR328;        /* offset: 0x0188 size: 8 bit */
-            INTC_PSR_8B_tag PSR329;        /* offset: 0x0189 size: 8 bit */
-            INTC_PSR_8B_tag PSR330;        /* offset: 0x018A size: 8 bit */
-            INTC_PSR_8B_tag PSR331;        /* offset: 0x018B size: 8 bit */
-            INTC_PSR_8B_tag PSR332;        /* offset: 0x018C size: 8 bit */
-            INTC_PSR_8B_tag PSR333;        /* offset: 0x018D size: 8 bit */
-            INTC_PSR_8B_tag PSR334;        /* offset: 0x018E size: 8 bit */
-            INTC_PSR_8B_tag PSR335;        /* offset: 0x018F size: 8 bit */
-            INTC_PSR_8B_tag PSR336;        /* offset: 0x0190 size: 8 bit */
-            INTC_PSR_8B_tag PSR337;        /* offset: 0x0191 size: 8 bit */
-            INTC_PSR_8B_tag PSR338;        /* offset: 0x0192 size: 8 bit */
-            INTC_PSR_8B_tag PSR339;        /* offset: 0x0193 size: 8 bit */
-            INTC_PSR_8B_tag PSR340;        /* offset: 0x0194 size: 8 bit */
-            INTC_PSR_8B_tag PSR341;        /* offset: 0x0195 size: 8 bit */
-            INTC_PSR_8B_tag PSR342;        /* offset: 0x0196 size: 8 bit */
-            INTC_PSR_8B_tag PSR343;        /* offset: 0x0197 size: 8 bit */
-            INTC_PSR_8B_tag PSR344;        /* offset: 0x0198 size: 8 bit */
-            INTC_PSR_8B_tag PSR345;        /* offset: 0x0199 size: 8 bit */
-            INTC_PSR_8B_tag PSR346;        /* offset: 0x019A size: 8 bit */
-            INTC_PSR_8B_tag PSR347;        /* offset: 0x019B size: 8 bit */
-            INTC_PSR_8B_tag PSR348;        /* offset: 0x019C size: 8 bit */
-            INTC_PSR_8B_tag PSR349;        /* offset: 0x019D size: 8 bit */
-            INTC_PSR_8B_tag PSR350;        /* offset: 0x019E size: 8 bit */
-            INTC_PSR_8B_tag PSR351;        /* offset: 0x019F size: 8 bit */
-            INTC_PSR_8B_tag PSR352;        /* offset: 0x01A0 size: 8 bit */
-            INTC_PSR_8B_tag PSR353;        /* offset: 0x01A1 size: 8 bit */
-            INTC_PSR_8B_tag PSR354;        /* offset: 0x01A2 size: 8 bit */
-            INTC_PSR_8B_tag PSR355;        /* offset: 0x01A3 size: 8 bit */
-            INTC_PSR_8B_tag PSR356;        /* offset: 0x01A4 size: 8 bit */
-            INTC_PSR_8B_tag PSR357;        /* offset: 0x01A5 size: 8 bit */
-            INTC_PSR_8B_tag PSR358;        /* offset: 0x01A6 size: 8 bit */
-            INTC_PSR_8B_tag PSR359;        /* offset: 0x01A7 size: 8 bit */
-            INTC_PSR_8B_tag PSR360;        /* offset: 0x01A8 size: 8 bit */
-            INTC_PSR_8B_tag PSR361;        /* offset: 0x01A9 size: 8 bit */
-            INTC_PSR_8B_tag PSR362;        /* offset: 0x01AA size: 8 bit */
-            INTC_PSR_8B_tag PSR363;        /* offset: 0x01AB size: 8 bit */
-            INTC_PSR_8B_tag PSR364;        /* offset: 0x01AC size: 8 bit */
-            INTC_PSR_8B_tag PSR365;        /* offset: 0x01AD size: 8 bit */
-            INTC_PSR_8B_tag PSR366;        /* offset: 0x01AE size: 8 bit */
-            INTC_PSR_8B_tag PSR367;        /* offset: 0x01AF size: 8 bit */
-            INTC_PSR_8B_tag PSR368;        /* offset: 0x01B0 size: 8 bit */
-            INTC_PSR_8B_tag PSR369;        /* offset: 0x01B1 size: 8 bit */
-            INTC_PSR_8B_tag PSR370;        /* offset: 0x01B2 size: 8 bit */
-            INTC_PSR_8B_tag PSR371;        /* offset: 0x01B3 size: 8 bit */
-            INTC_PSR_8B_tag PSR372;        /* offset: 0x01B4 size: 8 bit */
-            INTC_PSR_8B_tag PSR373;        /* offset: 0x01B5 size: 8 bit */
-            INTC_PSR_8B_tag PSR374;        /* offset: 0x01B6 size: 8 bit */
-            INTC_PSR_8B_tag PSR375;        /* offset: 0x01B7 size: 8 bit */
-            INTC_PSR_8B_tag PSR376;        /* offset: 0x01B8 size: 8 bit */
-            INTC_PSR_8B_tag PSR377;        /* offset: 0x01B9 size: 8 bit */
-            INTC_PSR_8B_tag PSR378;        /* offset: 0x01BA size: 8 bit */
-            INTC_PSR_8B_tag PSR379;        /* offset: 0x01BB size: 8 bit */
-            INTC_PSR_8B_tag PSR380;        /* offset: 0x01BC size: 8 bit */
-            INTC_PSR_8B_tag PSR381;        /* offset: 0x01BD size: 8 bit */
-            INTC_PSR_8B_tag PSR382;        /* offset: 0x01BE size: 8 bit */
-            INTC_PSR_8B_tag PSR383;        /* offset: 0x01BF size: 8 bit */
-            INTC_PSR_8B_tag PSR384;        /* offset: 0x01C0 size: 8 bit */
-            INTC_PSR_8B_tag PSR385;        /* offset: 0x01C1 size: 8 bit */
-            INTC_PSR_8B_tag PSR386;        /* offset: 0x01C2 size: 8 bit */
-            INTC_PSR_8B_tag PSR387;        /* offset: 0x01C3 size: 8 bit */
-            INTC_PSR_8B_tag PSR388;        /* offset: 0x01C4 size: 8 bit */
-            INTC_PSR_8B_tag PSR389;        /* offset: 0x01C5 size: 8 bit */
-            INTC_PSR_8B_tag PSR390;        /* offset: 0x01C6 size: 8 bit */
-            INTC_PSR_8B_tag PSR391;        /* offset: 0x01C7 size: 8 bit */
-            INTC_PSR_8B_tag PSR392;        /* offset: 0x01C8 size: 8 bit */
-            INTC_PSR_8B_tag PSR393;        /* offset: 0x01C9 size: 8 bit */
-            INTC_PSR_8B_tag PSR394;        /* offset: 0x01CA size: 8 bit */
-            INTC_PSR_8B_tag PSR395;        /* offset: 0x01CB size: 8 bit */
-            INTC_PSR_8B_tag PSR396;        /* offset: 0x01CC size: 8 bit */
-            INTC_PSR_8B_tag PSR397;        /* offset: 0x01CD size: 8 bit */
-            INTC_PSR_8B_tag PSR398;        /* offset: 0x01CE size: 8 bit */
-            INTC_PSR_8B_tag PSR399;        /* offset: 0x01CF size: 8 bit */
-            INTC_PSR_8B_tag PSR400;        /* offset: 0x01D0 size: 8 bit */
-            INTC_PSR_8B_tag PSR401;        /* offset: 0x01D1 size: 8 bit */
-            INTC_PSR_8B_tag PSR402;        /* offset: 0x01D2 size: 8 bit */
-            INTC_PSR_8B_tag PSR403;        /* offset: 0x01D3 size: 8 bit */
-            INTC_PSR_8B_tag PSR404;        /* offset: 0x01D4 size: 8 bit */
-            INTC_PSR_8B_tag PSR405;        /* offset: 0x01D5 size: 8 bit */
-            INTC_PSR_8B_tag PSR406;        /* offset: 0x01D6 size: 8 bit */
-            INTC_PSR_8B_tag PSR407;        /* offset: 0x01D7 size: 8 bit */
-            INTC_PSR_8B_tag PSR408;        /* offset: 0x01D8 size: 8 bit */
-            INTC_PSR_8B_tag PSR409;        /* offset: 0x01D9 size: 8 bit */
-            INTC_PSR_8B_tag PSR410;        /* offset: 0x01DA size: 8 bit */
-            INTC_PSR_8B_tag PSR411;        /* offset: 0x01DB size: 8 bit */
-            INTC_PSR_8B_tag PSR412;        /* offset: 0x01DC size: 8 bit */
-            INTC_PSR_8B_tag PSR413;        /* offset: 0x01DD size: 8 bit */
-            INTC_PSR_8B_tag PSR414;        /* offset: 0x01DE size: 8 bit */
-            INTC_PSR_8B_tag PSR415;        /* offset: 0x01DF size: 8 bit */
-            INTC_PSR_8B_tag PSR416;        /* offset: 0x01E0 size: 8 bit */
-            INTC_PSR_8B_tag PSR417;        /* offset: 0x01E1 size: 8 bit */
-            INTC_PSR_8B_tag PSR418;        /* offset: 0x01E2 size: 8 bit */
-            INTC_PSR_8B_tag PSR419;        /* offset: 0x01E3 size: 8 bit */
-            INTC_PSR_8B_tag PSR420;        /* offset: 0x01E4 size: 8 bit */
-            INTC_PSR_8B_tag PSR421;        /* offset: 0x01E5 size: 8 bit */
-            INTC_PSR_8B_tag PSR422;        /* offset: 0x01E6 size: 8 bit */
-            INTC_PSR_8B_tag PSR423;        /* offset: 0x01E7 size: 8 bit */
-            INTC_PSR_8B_tag PSR424;        /* offset: 0x01E8 size: 8 bit */
-            INTC_PSR_8B_tag PSR425;        /* offset: 0x01E9 size: 8 bit */
-            INTC_PSR_8B_tag PSR426;        /* offset: 0x01EA size: 8 bit */
-            INTC_PSR_8B_tag PSR427;        /* offset: 0x01EB size: 8 bit */
-            INTC_PSR_8B_tag PSR428;        /* offset: 0x01EC size: 8 bit */
-            INTC_PSR_8B_tag PSR429;        /* offset: 0x01ED size: 8 bit */
-            INTC_PSR_8B_tag PSR430;        /* offset: 0x01EE size: 8 bit */
-            INTC_PSR_8B_tag PSR431;        /* offset: 0x01EF size: 8 bit */
-            INTC_PSR_8B_tag PSR432;        /* offset: 0x01F0 size: 8 bit */
-            INTC_PSR_8B_tag PSR433;        /* offset: 0x01F1 size: 8 bit */
-            INTC_PSR_8B_tag PSR434;        /* offset: 0x01F2 size: 8 bit */
-            INTC_PSR_8B_tag PSR435;        /* offset: 0x01F3 size: 8 bit */
-            INTC_PSR_8B_tag PSR436;        /* offset: 0x01F4 size: 8 bit */
-            INTC_PSR_8B_tag PSR437;        /* offset: 0x01F5 size: 8 bit */
-            INTC_PSR_8B_tag PSR438;        /* offset: 0x01F6 size: 8 bit */
-            INTC_PSR_8B_tag PSR439;        /* offset: 0x01F7 size: 8 bit */
-            INTC_PSR_8B_tag PSR440;        /* offset: 0x01F8 size: 8 bit */
-            INTC_PSR_8B_tag PSR441;        /* offset: 0x01F9 size: 8 bit */
-            INTC_PSR_8B_tag PSR442;        /* offset: 0x01FA size: 8 bit */
-            INTC_PSR_8B_tag PSR443;        /* offset: 0x01FB size: 8 bit */
-            INTC_PSR_8B_tag PSR444;        /* offset: 0x01FC size: 8 bit */
-            INTC_PSR_8B_tag PSR445;        /* offset: 0x01FD size: 8 bit */
-            INTC_PSR_8B_tag PSR446;        /* offset: 0x01FE size: 8 bit */
-            INTC_PSR_8B_tag PSR447;        /* offset: 0x01FF size: 8 bit */
-            INTC_PSR_8B_tag PSR448;        /* offset: 0x0200 size: 8 bit */
-            INTC_PSR_8B_tag PSR449;        /* offset: 0x0201 size: 8 bit */
-            INTC_PSR_8B_tag PSR450;        /* offset: 0x0202 size: 8 bit */
-            INTC_PSR_8B_tag PSR451;        /* offset: 0x0203 size: 8 bit */
-            INTC_PSR_8B_tag PSR452;        /* offset: 0x0204 size: 8 bit */
-            INTC_PSR_8B_tag PSR453;        /* offset: 0x0205 size: 8 bit */
-            INTC_PSR_8B_tag PSR454;        /* offset: 0x0206 size: 8 bit */
-            INTC_PSR_8B_tag PSR455;        /* offset: 0x0207 size: 8 bit */
-            INTC_PSR_8B_tag PSR456;        /* offset: 0x0208 size: 8 bit */
-            INTC_PSR_8B_tag PSR457;        /* offset: 0x0209 size: 8 bit */
-            INTC_PSR_8B_tag PSR458;        /* offset: 0x020A size: 8 bit */
-            INTC_PSR_8B_tag PSR459;        /* offset: 0x020B size: 8 bit */
-            INTC_PSR_8B_tag PSR460;        /* offset: 0x020C size: 8 bit */
-            INTC_PSR_8B_tag PSR461;        /* offset: 0x020D size: 8 bit */
-            INTC_PSR_8B_tag PSR462;        /* offset: 0x020E size: 8 bit */
-            INTC_PSR_8B_tag PSR463;        /* offset: 0x020F size: 8 bit */
-            INTC_PSR_8B_tag PSR464;        /* offset: 0x0210 size: 8 bit */
-            INTC_PSR_8B_tag PSR465;        /* offset: 0x0211 size: 8 bit */
-            INTC_PSR_8B_tag PSR466;        /* offset: 0x0212 size: 8 bit */
-            INTC_PSR_8B_tag PSR467;        /* offset: 0x0213 size: 8 bit */
-            INTC_PSR_8B_tag PSR468;        /* offset: 0x0214 size: 8 bit */
-            INTC_PSR_8B_tag PSR469;        /* offset: 0x0215 size: 8 bit */
-            INTC_PSR_8B_tag PSR470;        /* offset: 0x0216 size: 8 bit */
-            INTC_PSR_8B_tag PSR471;        /* offset: 0x0217 size: 8 bit */
-            INTC_PSR_8B_tag PSR472;        /* offset: 0x0218 size: 8 bit */
-            INTC_PSR_8B_tag PSR473;        /* offset: 0x0219 size: 8 bit */
-            INTC_PSR_8B_tag PSR474;        /* offset: 0x021A size: 8 bit */
-            INTC_PSR_8B_tag PSR475;        /* offset: 0x021B size: 8 bit */
-            INTC_PSR_8B_tag PSR476;        /* offset: 0x021C size: 8 bit */
-            INTC_PSR_8B_tag PSR477;        /* offset: 0x021D size: 8 bit */
-            INTC_PSR_8B_tag PSR478;        /* offset: 0x021E size: 8 bit */
-            INTC_PSR_8B_tag PSR479;        /* offset: 0x021F size: 8 bit */
-            INTC_PSR_8B_tag PSR480;        /* offset: 0x0220 size: 8 bit */
-            INTC_PSR_8B_tag PSR481;        /* offset: 0x0221 size: 8 bit */
-            INTC_PSR_8B_tag PSR482;        /* offset: 0x0222 size: 8 bit */
-            INTC_PSR_8B_tag PSR483;        /* offset: 0x0223 size: 8 bit */
-            INTC_PSR_8B_tag PSR484;        /* offset: 0x0224 size: 8 bit */
-            INTC_PSR_8B_tag PSR485;        /* offset: 0x0225 size: 8 bit */
-            INTC_PSR_8B_tag PSR486;        /* offset: 0x0226 size: 8 bit */
-            INTC_PSR_8B_tag PSR487;        /* offset: 0x0227 size: 8 bit */
-            INTC_PSR_8B_tag PSR488;        /* offset: 0x0228 size: 8 bit */
-            INTC_PSR_8B_tag PSR489;        /* offset: 0x0229 size: 8 bit */
-            INTC_PSR_8B_tag PSR490;        /* offset: 0x022A size: 8 bit */
-            INTC_PSR_8B_tag PSR491;        /* offset: 0x022B size: 8 bit */
-            INTC_PSR_8B_tag PSR492;        /* offset: 0x022C size: 8 bit */
-            INTC_PSR_8B_tag PSR493;        /* offset: 0x022D size: 8 bit */
-            INTC_PSR_8B_tag PSR494;        /* offset: 0x022E size: 8 bit */
-            INTC_PSR_8B_tag PSR495;        /* offset: 0x022F size: 8 bit */
-            INTC_PSR_8B_tag PSR496;        /* offset: 0x0230 size: 8 bit */
-            INTC_PSR_8B_tag PSR497;        /* offset: 0x0231 size: 8 bit */
-            INTC_PSR_8B_tag PSR498;        /* offset: 0x0232 size: 8 bit */
-            INTC_PSR_8B_tag PSR499;        /* offset: 0x0233 size: 8 bit */
-            INTC_PSR_8B_tag PSR500;        /* offset: 0x0234 size: 8 bit */
-            INTC_PSR_8B_tag PSR501;        /* offset: 0x0235 size: 8 bit */
-            INTC_PSR_8B_tag PSR502;        /* offset: 0x0236 size: 8 bit */
-            INTC_PSR_8B_tag PSR503;        /* offset: 0x0237 size: 8 bit */
-            INTC_PSR_8B_tag PSR504;        /* offset: 0x0238 size: 8 bit */
-            INTC_PSR_8B_tag PSR505;        /* offset: 0x0239 size: 8 bit */
-            INTC_PSR_8B_tag PSR506;        /* offset: 0x023A size: 8 bit */
-            INTC_PSR_8B_tag PSR507;        /* offset: 0x023B size: 8 bit */
-            INTC_PSR_8B_tag PSR508;        /* offset: 0x023C size: 8 bit */
-            INTC_PSR_8B_tag PSR509;        /* offset: 0x023D size: 8 bit */
-            INTC_PSR_8B_tag PSR510;        /* offset: 0x023E size: 8 bit */
-            INTC_PSR_8B_tag PSR511;        /* offset: 0x023F size: 8 bit */
-         };
-
-      };
-   } INTC_tag;
-
-
-#define INTC  (*(volatile INTC_tag *) 0xFFF48000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: DSPI  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* MCR - Module Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  MSTR:1;            /* Master/Slave mode select */
-         vuint32_t  CONT_SCKE:1;       /* Continuous SCK Enable */
-         vuint32_t  DCONF:2;           /* DSPI Configuration */
-         vuint32_t  FRZ:1;             /* Freeze */
-         vuint32_t  MTFE:1;            /* Modified Timing Format Enable */
-         vuint32_t  PCSSE:1;           /* Peripheral Chip Select Strobe Enable */
-         vuint32_t  ROOE:1;            /* Receive FIFO Overflow Overwrite Enable */
-         vuint32_t  PCSIS7:1;          /* Peripheral Chip Select 7 Inactive State */
-         vuint32_t  PCSIS6:1;          /* Peripheral Chip Select 6 Inactive State */
-         vuint32_t  PCSIS5:1;          /* Peripheral Chip Select 5 Inactive State */
-         vuint32_t  PCSIS4:1;          /* Peripheral Chip Select 4 Inactive State */
-         vuint32_t  PCSIS3:1;          /* Peripheral Chip Select 3 Inactive State */
-         vuint32_t  PCSIS2:1;          /* Peripheral Chip Select 2 Inactive State */
-         vuint32_t  PCSIS1:1;          /* Peripheral Chip Select 1 Inactive State */
-         vuint32_t  PCSIS0:1;          /* Peripheral Chip Select 0 Inactive State */
-         vuint32_t  DOZE:1;            /* Doze Enable */
-         vuint32_t  MDIS:1;            /* Module Disable */
-         vuint32_t  DIS_TXF:1;         /* Disable Transmit FIFO */
-         vuint32_t  DIS_RXF:1;         /* Disable Receive FIFO */
-         vuint32_t  CLR_TXF:1;         /* Clear TX FIFO */
-         vuint32_t  CLR_RXF:1;         /* Clear RX FIFO */
-         vuint32_t  SMPL_PT:2;         /* Sample Point */
-         vuint32_t:7;
-         vuint32_t  HALT:1;            /* Halt */
-      } B;
-   } DSPI_MCR_32B_tag;
-
-   typedef union {   /* TCR - Transfer Count Register */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  SPI_TCNT:16;       /* SPI Transfer Counter */
-#else
-         vuint32_t  TCNT:16;             /* deprecated name - please avoid */
-#endif
-         vuint32_t:16;
-      } B;
-   } DSPI_TCR_32B_tag;
-
-
-   /* Register layout for all registers CTAR... */
-
-   typedef union {   /* CTAR0-7 - Clock and Transfer Attribute Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t  DBR:1;             /* Double Baud Rate */
-         vuint32_t  FMSZ:4;            /* Frame Size */
-         vuint32_t  CPOL:1;            /* Clock Polarity */
-         vuint32_t  CPHA:1;            /* Clock Phase */
-         vuint32_t  LSBFE:1;           /* LSB First Enable */
-         vuint32_t  PCSSCK:2;          /* PCS to SCK Delay Prescaler */
-         vuint32_t  PASC:2;            /* After SCK Delay Prescaler */
-         vuint32_t  PDT:2;             /* Delay after Transfer Prescaler */
-         vuint32_t  PBR:2;             /* Baud Rate Prescaler */
-         vuint32_t  CSSCK:4;           /* PCS to SCK Delay Scaler */
-         vuint32_t  ASC:4;             /* After SCK Delay Scaler */
-         vuint32_t  DT:4;              /* Delay after Transfer Scaler */
-         vuint32_t  BR:4;              /* Baud Rate Scaler */
-      } B;
-   } DSPI_CTAR_32B_tag;
-
-   typedef union {   /* SR - Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  TCF:1;             /* Transfer Complete Flag */
-         vuint32_t  TXRXS:1;           /* TX & RX Status */
-         vuint32_t:1;
-         vuint32_t  EOQF:1;            /* End of queue Flag */
-         vuint32_t  TFUF:1;            /* Transmit FIFO Underflow Flag */
-         vuint32_t:1;
-         vuint32_t  TFFF:1;            /* Transmit FIFO FIll Flag */
-         vuint32_t:5;
-         vuint32_t  RFOF:1;            /* Receive FIFO Overflow Flag */
-         vuint32_t:1;
-         vuint32_t  RFDF:1;            /* Receive FIFO Drain Flag */
-         vuint32_t:1;
-         vuint32_t  TXCTR:4;           /* TX FIFO Counter */
-         vuint32_t  TXNXTPTR:4;        /* Transmit Next Pointer */
-         vuint32_t  RXCTR:4;           /* RX FIFO Counter */
-         vuint32_t  POPNXTPTR:4;       /* Pop Next Pointer */
-      } B;
-   } DSPI_SR_32B_tag;
-
-   typedef union {   /* RSER - DMA/Interrupt Request Register */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  TCF_RE:1;          /* Transmission Complete Request Enable */
-#else
-         vuint32_t  TCFRE:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t:2;
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  EOQF_RE:1;         /* DSPI Finished Request Enable */
-#else
-         vuint32_t  EOQFRE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  TFUF_RE:1;         /* Transmit FIFO Underflow Request Enable */
-#else
-         vuint32_t  TFUFRE:1;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:1;
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  TFFF_RE:1;         /* Transmit FIFO Fill Request Enable */
-#else
-         vuint32_t  TFFFRE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  TFFF_DIRS:1;       /* Transmit FIFO Fill DMA or Interrupt Request Select */
-#else
-         vuint32_t  TFFFDIRS:1;          /* deprecated name - please avoid */
-#endif
-         vuint32_t:4;
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  RFOF_RE:1;         /* Receive FIFO overflow Request Enable */
-#else
-         vuint32_t  RFOFRE:1;            /* deprecated name - please avoid */
-#endif
-         vuint32_t:1;
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  RFDF_RE:1;         /* Receive FIFO Drain Request Enable */
-#else
-         vuint32_t  RFDFRE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  RFDF_DIRS:1;       /* Receive FIFO Drain DMA or Interrupt Request Select */
-#else
-         vuint32_t  RFDFDIRS:1;          /* deprecated name - please avoid */
-#endif
-         vuint32_t:16;
-      } B;
-   } DSPI_RSER_32B_tag;
-
-   typedef union {   /* PUSHR - PUSH TX FIFO Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  CONT:1;            /* Continuous Peripheral Chip Select Enable */
-         vuint32_t  CTAS:3;            /* Clock and Transfer Attributes Select */
-         vuint32_t  EOQ:1;             /* End of Queue */
-         vuint32_t  CTCNT:1;           /* Clear SPI_TCNT */
-         vuint32_t:2;
-         vuint32_t  PCS7:1;            /* Peripheral Chip Select 7 */
-         vuint32_t  PCS6:1;            /* Peripheral Chip Select 6 */
-         vuint32_t  PCS5:1;            /* Peripheral Chip Select 5 */
-         vuint32_t  PCS4:1;            /* Peripheral Chip Select 4 */
-         vuint32_t  PCS3:1;            /* Peripheral Chip Select 3 */
-         vuint32_t  PCS2:1;            /* Peripheral Chip Select 2 */
-         vuint32_t  PCS1:1;            /* Peripheral Chip Select 1 */
-         vuint32_t  PCS0:1;            /* Peripheral Chip Select 0 */
-         vuint32_t  TXDATA:16;         /* Transmit Data */
-      } B;
-   } DSPI_PUSHR_32B_tag;
-
-   typedef union {   /* POPR - POP RX FIFO Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  RXDATA:16;         /* Receive Data */
-      } B;
-   } DSPI_POPR_32B_tag;
-
-
-   /* Register layout for all registers TXFR... */
-
-   typedef union {   /* Transmit FIFO Registers */
-      vuint32_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  FIFO_TXCMD:16;     /* Transmit Command */
-#else
-         vuint32_t  TXCMD:16;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  FIFO_TXDATA:16;    /* Transmit Data */
-#else
-         vuint32_t  TXDATA:16;           /* deprecated name - please avoid */
-#endif
-      } B;
-   } DSPI_TXFR_32B_tag;
-
-
-   /* Register layout for all registers RXFR... */
-
-   typedef union {   /* Receive FIFO Registers */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-#ifndef USE_FIELD_ALIASES_DSPI
-         vuint32_t  FIFO_RXDATA:16;    /* Transmit Data */
-#else
-         vuint32_t  RXDATA:16;           /* deprecated name - please avoid */
-#endif
-      } B;
-   } DSPI_RXFR_32B_tag;
-
-   typedef union {   /* DSICR - DSI Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  MTOE:1;            /* Multiple Transfer Operation Enable */
-         vuint32_t:1;
-         vuint32_t  MTOCNT:6;          /* Multiple Transfer Operation Count */
-         vuint32_t:4;
-         vuint32_t  TXSS:1;            /* Transmit Data Source Select */
-         vuint32_t  TPOL:1;            /* Trigger Polarity */
-         vuint32_t  TRRE:1;            /* Trigger Reception Enable */
-         vuint32_t  CID:1;             /* Change in Data Transfer Enable */
-         vuint32_t  DCONT:1;           /* DSI Continuous Peripheral Chip Select Enable */
-         vuint32_t  DSICTAS:3;         /* DSI CLock and Transfer Attributes Select */
-         vuint32_t:4;
-         vuint32_t  DPCS7:1;           /* DSI Peripheral Chip Select 7 */
-         vuint32_t  DPCS6:1;           /* DSI Peripheral Chip Select 6 */
-         vuint32_t  DPCS5:1;           /* DSI Peripheral Chip Select 5 */
-         vuint32_t  DPCS4:1;           /* DSI Peripheral Chip Select 4 */
-         vuint32_t  DPCS3:1;           /* DSI Peripheral Chip Select 3 */
-         vuint32_t  DPCS2:1;           /* DSI Peripheral Chip Select 2 */
-         vuint32_t  DPCS1:1;           /* DSI Peripheral Chip Select 1 */
-         vuint32_t  DPCS0:1;           /* DSI Peripheral Chip Select 0 */
-      } B;
-   } DSPI_DSICR_32B_tag;
-
-   typedef union {   /* SDR - DSI Serialization Data Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  SER_DATA:16;       /* Serialized Data */
-      } B;
-   } DSPI_SDR_32B_tag;
-
-   typedef union {   /* ASDR - DSI Alternate Serialization Data Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  ASER_DATA:16;      /* Alternate Serialized Data */
-      } B;
-   } DSPI_ASDR_32B_tag;
-
-   typedef union {   /* COMPR - DSI Transmit Comparison Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  COMP_DATA:16;      /* Compare Data */
-      } B;
-   } DSPI_COMPR_32B_tag;
-
-   typedef union {   /* DDR - DSI Deserialization Data Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-         vuint32_t  DESER_DATA:16;     /* Deserialized Data */
-      } B;
-   } DSPI_DDR_32B_tag;
-
-   typedef union {   /* DSICR1 - DSI Configuration Register 1 */
-      vuint32_t R;
-   } DSPI_DSICR1_32B_tag;
-
-
-
-   typedef struct DSPI_struct_tag { /* start of DSPI_tag */
-                                  /* MCR - Module Configuration Register */
-      DSPI_MCR_32B_tag MCR;                /* offset: 0x0000 size: 32 bit */
-      int8_t DSPI_reserved_0004[4];
-                                        /* TCR - Transfer Count Register */
-      DSPI_TCR_32B_tag TCR;                /* offset: 0x0008 size: 32 bit */
-      union {
-                     /* CTAR0-7 - Clock and Transfer Attribute Registers */
-         DSPI_CTAR_32B_tag CTAR[8];        /* offset: 0x000C  (0x0004 x 8) */
-
-         struct {
-                     /* CTAR0-7 - Clock and Transfer Attribute Registers */
-            DSPI_CTAR_32B_tag CTAR0;       /* offset: 0x000C size: 32 bit */
-            DSPI_CTAR_32B_tag CTAR1;       /* offset: 0x0010 size: 32 bit */
-            DSPI_CTAR_32B_tag CTAR2;       /* offset: 0x0014 size: 32 bit */
-            DSPI_CTAR_32B_tag CTAR3;       /* offset: 0x0018 size: 32 bit */
-            DSPI_CTAR_32B_tag CTAR4;       /* offset: 0x001C size: 32 bit */
-            DSPI_CTAR_32B_tag CTAR5;       /* offset: 0x0020 size: 32 bit */
-            DSPI_CTAR_32B_tag CTAR6;       /* offset: 0x0024 size: 32 bit */
-            DSPI_CTAR_32B_tag CTAR7;       /* offset: 0x0028 size: 32 bit */
-         };
-
-      };
-                                                 /* SR - Status Register */
-      DSPI_SR_32B_tag SR;                  /* offset: 0x002C size: 32 bit */
-                                /* RSER - DMA/Interrupt Request Register */
-      DSPI_RSER_32B_tag RSER;              /* offset: 0x0030 size: 32 bit */
-                                        /* PUSHR - PUSH TX FIFO Register */
-      DSPI_PUSHR_32B_tag PUSHR;            /* offset: 0x0034 size: 32 bit */
-                                          /* POPR - POP RX FIFO Register */
-      DSPI_POPR_32B_tag POPR;              /* offset: 0x0038 size: 32 bit */
-      union {
-                                              /* Transmit FIFO Registers */
-         DSPI_TXFR_32B_tag TXFR[5];        /* offset: 0x003C  (0x0004 x 5) */
-
-         struct {
-                                              /* Transmit FIFO Registers */
-            DSPI_TXFR_32B_tag TXFR0;       /* offset: 0x003C size: 32 bit */
-            DSPI_TXFR_32B_tag TXFR1;       /* offset: 0x0040 size: 32 bit */
-            DSPI_TXFR_32B_tag TXFR2;       /* offset: 0x0044 size: 32 bit */
-            DSPI_TXFR_32B_tag TXFR3;       /* offset: 0x0048 size: 32 bit */
-            DSPI_TXFR_32B_tag TXFR4;       /* offset: 0x004C size: 32 bit */
-         };
-
-      };
-      int8_t DSPI_reserved_0050_C[44];
-      union {
-                                               /* Receive FIFO Registers */
-         DSPI_RXFR_32B_tag RXFR[5];        /* offset: 0x007C  (0x0004 x 5) */
-
-         struct {
-                                               /* Receive FIFO Registers */
-            DSPI_RXFR_32B_tag RXFR0;       /* offset: 0x007C size: 32 bit */
-            DSPI_RXFR_32B_tag RXFR1;       /* offset: 0x0080 size: 32 bit */
-            DSPI_RXFR_32B_tag RXFR2;       /* offset: 0x0084 size: 32 bit */
-            DSPI_RXFR_32B_tag RXFR3;       /* offset: 0x0088 size: 32 bit */
-            DSPI_RXFR_32B_tag RXFR4;       /* offset: 0x008C size: 32 bit */
-         };
-
-      };
-      int8_t DSPI_reserved_0090[44];
-                                   /* DSICR - DSI Configuration Register */
-      DSPI_DSICR_32B_tag DSICR;            /* offset: 0x00BC size: 32 bit */
-                                /* SDR - DSI Serialization Data Register */
-      DSPI_SDR_32B_tag SDR;                /* offset: 0x00C0 size: 32 bit */
-                     /* ASDR - DSI Alternate Serialization Data Register */
-      DSPI_ASDR_32B_tag ASDR;              /* offset: 0x00C4 size: 32 bit */
-                             /* COMPR - DSI Transmit Comparison Register */
-      DSPI_COMPR_32B_tag COMPR;            /* offset: 0x00C8 size: 32 bit */
-                              /* DDR - DSI Deserialization Data Register */
-      DSPI_DDR_32B_tag DDR;                /* offset: 0x00CC size: 32 bit */
-                                /* DSICR1 - DSI Configuration Register 1 */
-      DSPI_DSICR1_32B_tag DSICR1;          /* offset: 0x00D0 size: 32 bit */
-   } DSPI_tag;
-
-
-#define DSPI_A (*(volatile DSPI_tag *) 0xFFF90000UL)
-#define DSPI_B (*(volatile DSPI_tag *) 0xFFF94000UL)
-#define DSPI_C (*(volatile DSPI_tag *) 0xFFF98000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: FLEXCAN  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* MCR - Module Configuration Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  MDIS:1;            /* Module Disable */
-         vuint32_t  FRZ:1;             /* Freeze Enable */
-         vuint32_t  FEN:1;             /* FIFO Enable */
-         vuint32_t  HALT:1;            /* Halt Flexcan */
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  NOT_RDY:1;         /* Flexcan Not Ready */
-#else
-         vuint32_t  NOTRDY:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  WAK_MSK:1;         /* Wake Up Interrupt Mask */
-#else
-         vuint32_t  WAKMSK:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  SOFT_RST:1;        /* Soft Reset */
-#else
-         vuint32_t  SOFTRST:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  FRZ_ACK:1;         /* Freeze Mode Acknowledge */
-#else
-         vuint32_t  FRZACK:1;            /* deprecated name - please avoid */
-#endif
-         vuint32_t  SUPV:1;            /* Supervisor Mode */
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  SLF_WAK:1;         /* Self Wake Up */
-#else
-         vuint32_t  SLFWAK:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  WRN_EN:1;          /* Warning Interrupt Enable */
-#else
-         vuint32_t  WRNEN:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  LPM_ACK:1;         /* Low Power Mode Acknowledge */
-#else
-         vuint32_t  LPMACK:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  WAK_SRC:1;         /* Wake Up Source */
-#else
-         vuint32_t  WAKSRC:1;            /* deprecated name - please avoid */
-#endif
-         vuint32_t  DOZE:1;            /* Doze Mode Enable */
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  SRX_DIS:1;         /* Self Reception Disable */
-#else
-         vuint32_t  SRXDIS:1;            /* deprecated name - please avoid */
-#endif
-         vuint32_t  BCC:1;             /* Backwards Compatibility Configuration */
-         vuint32_t:2;
-         vuint32_t  LPRIO_EN:1;        /* Local Priority Enable */
-         vuint32_t  AEN:1;             /* Abort Enable */
-         vuint32_t:2;
-         vuint32_t  IDAM:2;            /* ID Acceptance Mode */
-         vuint32_t:2;
-         vuint32_t  MAXMB:6;           /* Maximum Number of Message Buffers */
-      } B;
-   } FLEXCAN_MCR_32B_tag;
-
-   typedef union {   /* CTRL -  Control Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  PRESDIV:8;         /* Prescaler Divsion Factor */
-         vuint32_t  RJW:2;             /* Resync Jump Width */
-         vuint32_t  PSEG1:3;           /* Phase Segment 1 */
-         vuint32_t  PSEG2:3;           /* Phase Segment 2 */
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BOFF_MSK:1;        /* Bus Off Mask */
-#else
-         vuint32_t  BOFFMSK:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  ERR_MSK:1;         /* Error Mask */
-#else
-         vuint32_t  ERRMSK:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  CLK_SRC:1;         /* CAN Engine Clock Source */
-#else
-         vuint32_t  CLKSRC:1;            /* deprecated name - please avoid */
-#endif
-         vuint32_t  LPB:1;             /* Loop Back */
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  TWRN_MSK:1;        /* Tx Warning Interrupt Mask */
-#else
-         vuint32_t  TWRNMSK:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  RWRN_MSK:1;        /* Rx Warning Interrupt Mask */
-#else
-         vuint32_t  RWRNMSK:1;           /* deprecated name - please avoid */
-#endif
-         vuint32_t:2;
-         vuint32_t  SMP:1;             /* Sampling Mode */
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BOFF_REC:1;        /* Bus Off Recovery Mode */
-#else
-         vuint32_t  BOFFREC:1;           /* deprecated name - please avoid */
-#endif
-         vuint32_t  TSYN:1;            /* Timer Sync Mode */
-         vuint32_t  LBUF:1;            /* Lowest Buffer Transmitted First */
-         vuint32_t  LOM:1;             /* Listen-Only Mode */
-         vuint32_t  PROPSEG:3;         /* Propagation Segment */
-      } B;
-   } FLEXCAN_CTRL_32B_tag;
-
-   typedef union {   /* TIMER - Free Running Timer */
-      vuint32_t R;
-   } FLEXCAN_TIMER_32B_tag;
-
-   typedef union {   /* RXGMASK - Rx Global Mask Register */
-      vuint32_t R;
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-      struct {
-         vuint32_t  MI:32;             /* deprecated field -- do not use */
-      } B;
-#endif
-   } FLEXCAN_RXGMASK_32B_tag;
-
-   typedef union {   /* RX14MASK - Rx 14 Mask Register */
-      vuint32_t R;
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-      struct {
-         vuint32_t  MI:32;             /* deprecated field -- do not use */
-      } B;
-#endif
-   } FLEXCAN_RX14MASK_32B_tag;
-
-   typedef union {   /* RX15MASK - Rx 15 Mask Register */
-      vuint32_t R;
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-      struct {
-         vuint32_t  MI:32;             /* deprecated field -- do not use */
-      } B;
-#endif
-   } FLEXCAN_RX15MASK_32B_tag;
-
-   typedef union {   /* ECR - Error Counter Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:16;
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  RX_ERR_COUNTER:8;   /* Rx Error Counter */
-#else
-         vuint32_t  RXECNT:8;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  TX_ERR_COUNTER:8;   /* Tx Error Counter */
-#else
-         vuint32_t  TXECNT:8;            /* deprecated name - please avoid */
-#endif
-      } B;
-   } FLEXCAN_ECR_32B_tag;
-
-   typedef union {   /* ESR - Error and Status Register */
-      vuint32_t R;
-      struct {
-         vuint32_t:14;
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  TWRN_INT:1;        /* Tx Warning Interrupt Flag */
-#else
-         vuint32_t  TWRNINT:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  RWRN_INT:1;        /* Rx Warning Interrupt Flag */
-#else
-         vuint32_t  RWRNINT:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BIT1_ERR:1;        /* Bit 1 Error */
-#else
-         vuint32_t  BIT1ERR:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BIT0_ERR:1;        /* Bit 0 Error */
-#else
-         vuint32_t  BIT0ERR:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  ACK_ERR:1;         /* Acknowledge Error */
-#else
-         vuint32_t  ACKERR:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  CRC_ERR:1;         /* Cyclic Redundancy Check Error */
-#else
-         vuint32_t  CRCERR:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  FRM_ERR:1;         /* Form Error */
-#else
-         vuint32_t  FRMERR:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  STF_ERR:1;         /* Stuffing Error */
-#else
-         vuint32_t  STFERR:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  TX_WRN:1;          /* Tx Error Counter */
-#else
-         vuint32_t  TXWRN:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  RX_WRN:1;          /* Rx Error Counter */
-#else
-         vuint32_t  RXWRN:1;             /* deprecated name - please avoid */
-#endif
-         vuint32_t  IDLE:1;            /* CAN bus Idle State */
-         vuint32_t  TXRX:1;            /* Current Flexcan Status */
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  FLT_CONF:2;        /* Fault Confinement State */
-#else
-         vuint32_t  FLTCONF:2;           /* deprecated name - please avoid */
-#endif
-         vuint32_t:1;
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BOFF_INT:1;        /* Bus Off Interrupt */
-#else
-         vuint32_t  BOFFINT:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  ERR_INT:1;         /* Error Interrupt */
-#else
-         vuint32_t  ERRINT:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  WAK_INT:1;         /* Wake-Up Interrupt */
-#else
-         vuint32_t  WAKINT:1;            /* deprecated name - please avoid */
-#endif
-      } B;
-   } FLEXCAN_ESR_32B_tag;
-
-   typedef union {   /* IMASK2 - Interrupt Masks 2 Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  BUF63M:1;          /* Buffer MB Mask 63 Bit */
-         vuint32_t  BUF62M:1;          /* Buffer MB Mask 62 Bit */
-         vuint32_t  BUF61M:1;          /* Buffer MB Mask 61 Bit */
-         vuint32_t  BUF60M:1;          /* Buffer MB Mask 60 Bit */
-         vuint32_t  BUF59M:1;          /* Buffer MB Mask 59 Bit */
-         vuint32_t  BUF58M:1;          /* Buffer MB Mask 58 Bit */
-         vuint32_t  BUF57M:1;          /* Buffer MB Mask 57 Bit */
-         vuint32_t  BUF56M:1;          /* Buffer MB Mask 56 Bit */
-         vuint32_t  BUF55M:1;          /* Buffer MB Mask 55 Bit */
-         vuint32_t  BUF54M:1;          /* Buffer MB Mask 54 Bit */
-         vuint32_t  BUF53M:1;          /* Buffer MB Mask 53 Bit */
-         vuint32_t  BUF52M:1;          /* Buffer MB Mask 52 Bit */
-         vuint32_t  BUF51M:1;          /* Buffer MB Mask 51 Bit */
-         vuint32_t  BUF50M:1;          /* Buffer MB Mask 50 Bit */
-         vuint32_t  BUF49M:1;          /* Buffer MB Mask 49 Bit */
-         vuint32_t  BUF48M:1;          /* Buffer MB Mask 48 Bit */
-         vuint32_t  BUF47M:1;          /* Buffer MB Mask 47 Bit */
-         vuint32_t  BUF46M:1;          /* Buffer MB Mask 46 Bit */
-         vuint32_t  BUF45M:1;          /* Buffer MB Mask 45 Bit */
-         vuint32_t  BUF44M:1;          /* Buffer MB Mask 44 Bit */
-         vuint32_t  BUF43M:1;          /* Buffer MB Mask 43 Bit */
-         vuint32_t  BUF42M:1;          /* Buffer MB Mask 42 Bit */
-         vuint32_t  BUF41M:1;          /* Buffer MB Mask 41 Bit */
-         vuint32_t  BUF40M:1;          /* Buffer MB Mask 40 Bit */
-         vuint32_t  BUF39M:1;          /* Buffer MB Mask 39 Bit */
-         vuint32_t  BUF38M:1;          /* Buffer MB Mask 38 Bit */
-         vuint32_t  BUF37M:1;          /* Buffer MB Mask 37 Bit */
-         vuint32_t  BUF36M:1;          /* Buffer MB Mask 36 Bit */
-         vuint32_t  BUF35M:1;          /* Buffer MB Mask 35 Bit */
-         vuint32_t  BUF34M:1;          /* Buffer MB Mask 34 Bit */
-         vuint32_t  BUF33M:1;          /* Buffer MB Mask 33 Bit */
-         vuint32_t  BUF32M:1;          /* Buffer MB Mask 32 Bit */
-      } B;
-   } FLEXCAN_IMASK2_32B_tag;
-
-   typedef union {   /* IMASK1 - Interrupt Masks 1 Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  BUF31M:1;          /* Buffer MB Mask 31 Bit */
-         vuint32_t  BUF30M:1;          /* Buffer MB Mask 30 Bit */
-         vuint32_t  BUF29M:1;          /* Buffer MB Mask 29 Bit */
-         vuint32_t  BUF28M:1;          /* Buffer MB Mask 28 Bit */
-         vuint32_t  BUF27M:1;          /* Buffer MB Mask 27 Bit */
-         vuint32_t  BUF26M:1;          /* Buffer MB Mask 26 Bit */
-         vuint32_t  BUF25M:1;          /* Buffer MB Mask 25 Bit */
-         vuint32_t  BUF24M:1;          /* Buffer MB Mask 24 Bit */
-         vuint32_t  BUF23M:1;          /* Buffer MB Mask 23 Bit */
-         vuint32_t  BUF22M:1;          /* Buffer MB Mask 22 Bit */
-         vuint32_t  BUF21M:1;          /* Buffer MB Mask 21 Bit */
-         vuint32_t  BUF20M:1;          /* Buffer MB Mask 20 Bit */
-         vuint32_t  BUF19M:1;          /* Buffer MB Mask 19 Bit */
-         vuint32_t  BUF18M:1;          /* Buffer MB Mask 18 Bit */
-         vuint32_t  BUF17M:1;          /* Buffer MB Mask 17 Bit */
-         vuint32_t  BUF16M:1;          /* Buffer MB Mask 16 Bit */
-         vuint32_t  BUF15M:1;          /* Buffer MB Mask 15 Bit */
-         vuint32_t  BUF14M:1;          /* Buffer MB Mask 14 Bit */
-         vuint32_t  BUF13M:1;          /* Buffer MB Mask 13 Bit */
-         vuint32_t  BUF12M:1;          /* Buffer MB Mask 12 Bit */
-         vuint32_t  BUF11M:1;          /* Buffer MB Mask 11 Bit */
-         vuint32_t  BUF10M:1;          /* Buffer MB Mask 10 Bit */
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF9M:1;           /* Buffer MB Mask 9 Bit */
-#else
-         vuint32_t  BUF09M:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF8M:1;           /* Buffer MB Mask 8 Bit */
-#else
-         vuint32_t  BUF08M:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF7M:1;           /* Buffer MB Mask 7 Bit */
-#else
-         vuint32_t  BUF07M:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF6M:1;           /* Buffer MB Mask 6 Bit */
-#else
-         vuint32_t  BUF06M:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF5M:1;           /* Buffer MB Mask 5 Bit */
-#else
-         vuint32_t  BUF05M:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF4M:1;           /* Buffer MB Mask 4 Bit */
-#else
-         vuint32_t  BUF04M:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF3M:1;           /* Buffer MB Mask 3 Bit */
-#else
-         vuint32_t  BUF03M:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF2M:1;           /* Buffer MB Mask 2 Bit */
-#else
-         vuint32_t  BUF02M:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF1M:1;           /* Buffer MB Mask 1 Bit */
-#else
-         vuint32_t  BUF01M:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF0M:1;           /* Buffer MB Mask 0 Bit */
-#else
-         vuint32_t  BUF00M:1;            /* deprecated name - please avoid */
-#endif
-      } B;
-   } FLEXCAN_IMASK1_32B_tag;
-
-   typedef union {   /* IFLAG2 - Interrupt Flags 2 Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  BUF63I:1;          /* Buffer MB Interrupt 63 Bit */
-         vuint32_t  BUF62I:1;          /* Buffer MB Interrupt 62 Bit */
-         vuint32_t  BUF61I:1;          /* Buffer MB Interrupt 61 Bit */
-         vuint32_t  BUF60I:1;          /* Buffer MB Interrupt 60 Bit */
-         vuint32_t  BUF59I:1;          /* Buffer MB Interrupt 59 Bit */
-         vuint32_t  BUF58I:1;          /* Buffer MB Interrupt 58 Bit */
-         vuint32_t  BUF57I:1;          /* Buffer MB Interrupt 57 Bit */
-         vuint32_t  BUF56I:1;          /* Buffer MB Interrupt 56 Bit */
-         vuint32_t  BUF55I:1;          /* Buffer MB Interrupt 55 Bit */
-         vuint32_t  BUF54I:1;          /* Buffer MB Interrupt 54 Bit */
-         vuint32_t  BUF53I:1;          /* Buffer MB Interrupt 53 Bit */
-         vuint32_t  BUF52I:1;          /* Buffer MB Interrupt 52 Bit */
-         vuint32_t  BUF51I:1;          /* Buffer MB Interrupt 51 Bit */
-         vuint32_t  BUF50I:1;          /* Buffer MB Interrupt 50 Bit */
-         vuint32_t  BUF49I:1;          /* Buffer MB Interrupt 49 Bit */
-         vuint32_t  BUF48I:1;          /* Buffer MB Interrupt 48 Bit */
-         vuint32_t  BUF47I:1;          /* Buffer MB Interrupt 47 Bit */
-         vuint32_t  BUF46I:1;          /* Buffer MB Interrupt 46 Bit */
-         vuint32_t  BUF45I:1;          /* Buffer MB Interrupt 45 Bit */
-         vuint32_t  BUF44I:1;          /* Buffer MB Interrupt 44 Bit */
-         vuint32_t  BUF43I:1;          /* Buffer MB Interrupt 43 Bit */
-         vuint32_t  BUF42I:1;          /* Buffer MB Interrupt 42 Bit */
-         vuint32_t  BUF41I:1;          /* Buffer MB Interrupt 41 Bit */
-         vuint32_t  BUF40I:1;          /* Buffer MB Interrupt 40 Bit */
-         vuint32_t  BUF39I:1;          /* Buffer MB Interrupt 39 Bit */
-         vuint32_t  BUF38I:1;          /* Buffer MB Interrupt 38 Bit */
-         vuint32_t  BUF37I:1;          /* Buffer MB Interrupt 37 Bit */
-         vuint32_t  BUF36I:1;          /* Buffer MB Interrupt 36 Bit */
-         vuint32_t  BUF35I:1;          /* Buffer MB Interrupt 35 Bit */
-         vuint32_t  BUF34I:1;          /* Buffer MB Interrupt 34 Bit */
-         vuint32_t  BUF33I:1;          /* Buffer MB Interrupt 33 Bit */
-         vuint32_t  BUF32I:1;          /* Buffer MB Interrupt 32 Bit */
-      } B;
-   } FLEXCAN_IFLAG2_32B_tag;
-
-   typedef union {   /* IFLAG1 - Interrupt Flags 1 Register */
-      vuint32_t R;
-      struct {
-         vuint32_t  BUF31I:1;          /* Buffer MB Interrupt 31 Bit */
-         vuint32_t  BUF30I:1;          /* Buffer MB Interrupt 30 Bit */
-         vuint32_t  BUF29I:1;          /* Buffer MB Interrupt 29 Bit */
-         vuint32_t  BUF28I:1;          /* Buffer MB Interrupt 28 Bit */
-         vuint32_t  BUF27I:1;          /* Buffer MB Interrupt 27 Bit */
-         vuint32_t  BUF26I:1;          /* Buffer MB Interrupt 26 Bit */
-         vuint32_t  BUF25I:1;          /* Buffer MB Interrupt 25 Bit */
-         vuint32_t  BUF24I:1;          /* Buffer MB Interrupt 24 Bit */
-         vuint32_t  BUF23I:1;          /* Buffer MB Interrupt 23 Bit */
-         vuint32_t  BUF22I:1;          /* Buffer MB Interrupt 22 Bit */
-         vuint32_t  BUF21I:1;          /* Buffer MB Interrupt 21 Bit */
-         vuint32_t  BUF20I:1;          /* Buffer MB Interrupt 20 Bit */
-         vuint32_t  BUF19I:1;          /* Buffer MB Interrupt 19 Bit */
-         vuint32_t  BUF18I:1;          /* Buffer MB Interrupt 18 Bit */
-         vuint32_t  BUF17I:1;          /* Buffer MB Interrupt 17 Bit */
-         vuint32_t  BUF16I:1;          /* Buffer MB Interrupt 16 Bit */
-         vuint32_t  BUF15I:1;          /* Buffer MB Interrupt 15 Bit */
-         vuint32_t  BUF14I:1;          /* Buffer MB Interrupt 14 Bit */
-         vuint32_t  BUF13I:1;          /* Buffer MB Interrupt 13 Bit */
-         vuint32_t  BUF12I:1;          /* Buffer MB Interrupt 12 Bit */
-         vuint32_t  BUF11I:1;          /* Buffer MB Interrupt 11 Bit */
-         vuint32_t  BUF10I:1;          /* Buffer MB Interrupt 10 Bit */
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF9I:1;           /* Buffer MB Interrupt 9 Bit */
-#else
-         vuint32_t  BUF09I:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF8I:1;           /* Buffer MB Interrupt 8 Bit */
-#else
-         vuint32_t  BUF08I:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF7I:1;           /* Buffer MB Interrupt 7 Bit */
-#else
-         vuint32_t  BUF07I:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF6I:1;           /* Buffer MB Interrupt 6 Bit */
-#else
-         vuint32_t  BUF06I:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF5I:1;           /* Buffer MB Interrupt 5 Bit */
-#else
-         vuint32_t  BUF05I:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF4I:1;           /* Buffer MB Interrupt 4 Bit */
-#else
-         vuint32_t  BUF04I:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF3I:1;           /* Buffer MB Interrupt 3 Bit */
-#else
-         vuint32_t  BUF03I:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF2I:1;           /* Buffer MB Interrupt 2 Bit */
-#else
-         vuint32_t  BUF02I:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF1I:1;           /* Buffer MB Interrupt 1 Bit */
-#else
-         vuint32_t  BUF01I:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FLEXCAN
-         vuint32_t  BUF0I:1;           /* Buffer MB Interrupt 0 Bit */
-#else
-         vuint32_t  BUF00I:1;            /* deprecated name - please avoid */
-#endif
-      } B;
-   } FLEXCAN_IFLAG1_32B_tag;
-
-
-   /* Register layout for all registers MSG_CS... */
-
-   typedef union {   /* Message Buffer Control and Status */
-      vuint32_t R;
-      struct {
-         vuint32_t:4;
-         vuint32_t  CODE:4;            /* Message Buffer Code */
-         vuint32_t:1;
-         vuint32_t  SRR:1;             /* Substitute Remote Request */
-         vuint32_t  IDE:1;             /* ID Extended Bit */
-         vuint32_t  RTR:1;             /* Remote Transmission Request */
-         vuint32_t  LENGTH:4;          /* Length of Data in Bytes */
-         vuint32_t  TIMESTAMP:16;      /* Free-Running Counter Time Stamp */
-      } B;
-   } FLEXCAN_MSG_CS_32B_tag;
-
-
-   /* Register layout for all registers MSG_ID... */
-
-   typedef union {   /* Message Buffer Identifier Field */
-      vuint32_t R;
-      struct {
-         vuint32_t  PRIO:3;            /* Local Priority */
-         vuint32_t STD_ID:11;
-         vuint32_t EXT_ID:18;
-      } B;
-   } FLEXCAN_MSG_ID_32B_tag;
-
-
-   /* Register layout for all registers MSG_BYTE0_3... */
-
-   typedef union {   /* Message Buffer Data Register */
-      vuint32_t R;
-      vuint8_t   BYTE[4];    /* individual bytes can be accessed */
-      vuint32_t  WORD;       /* individual words can be accessed */
-   } FLEXCAN_MSG_DATA_32B_tag;
-
-    typedef union {
-            vuint8_t  B[8]; /* Data buffer in Bytes (8 bits) */
-            vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
-            vuint32_t W[2]; /* Data buffer in words (32 bits) */
-            vuint32_t R[2]; /* Data buffer in words (32 bits) */
-   } FLEXCAN_MSG_DATA2_32B_tag;
-
-   /* Register layout for all registers MSG_BYTE4_7 matches xxx */
-
-
-   /* Register layout for all registers RXIMR... */
-
-   typedef union {   /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
-      vuint32_t R;
-   } FLEXCAN_RXIMR_32B_tag;
-
-
-   typedef struct FLEXCAN_MB_struct_tag {
-
-      union {
-                                    /* Message Buffer Control and Status */
-         FLEXCAN_MSG_CS_32B_tag MSG_CS;   /* relative offset: 0x0000 */
-         FLEXCAN_MSG_CS_32B_tag CS;       /* deprecated - please avoid */
-      };
-      union {
-                                      /* Message Buffer Identifier Field */
-         FLEXCAN_MSG_ID_32B_tag MSG_ID;   /* relative offset: 0x0004 */
-         FLEXCAN_MSG_ID_32B_tag ID;       /* deprecated - please avoid */
-      };
-      union {	  /* Message Buffer Data Register */
-	     
-		 struct {
-            FLEXCAN_MSG_DATA_32B_tag MSG_BYTE0_3;  /* relative offset: 0x0008 */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG_BYTE4_7;  /* relative offset: 0x000C */
-         };
-		 
-		 FLEXCAN_MSG_DATA2_32B_tag DATA;  /* relative offset: 0x000C */
-		 
-      };
-
-   } FLEXCAN_MB_tag;
-
-
-   typedef struct FLEXCAN_struct_tag { /* start of FLEXCAN_tag */
-                                  /* MCR - Module Configuration Register */
-      FLEXCAN_MCR_32B_tag MCR;             /* offset: 0x0000 size: 32 bit */
-      union {
-                                             /* CTRL -  Control Register */
-         FLEXCAN_CTRL_32B_tag CTRL;        /* offset: 0x0004 size: 32 bit */
-
-         FLEXCAN_CTRL_32B_tag CR;          /* deprecated - please avoid */
-
-      };
-                                           /* TIMER - Free Running Timer */
-      FLEXCAN_TIMER_32B_tag TIMER;         /* offset: 0x0008 size: 32 bit */
-      int8_t FLEXCAN_reserved_000C[4];
-                                    /* RXGMASK - Rx Global Mask Register */
-      FLEXCAN_RXGMASK_32B_tag RXGMASK;     /* offset: 0x0010 size: 32 bit */
-                                       /* RX14MASK - Rx 14 Mask Register */
-      FLEXCAN_RX14MASK_32B_tag RX14MASK;   /* offset: 0x0014 size: 32 bit */
-                                       /* RX15MASK - Rx 15 Mask Register */
-      FLEXCAN_RX15MASK_32B_tag RX15MASK;   /* offset: 0x0018 size: 32 bit */
-                                         /* ECR - Error Counter Register */
-      FLEXCAN_ECR_32B_tag ECR;             /* offset: 0x001C size: 32 bit */
-                                      /* ESR - Error and Status Register */
-      FLEXCAN_ESR_32B_tag ESR;             /* offset: 0x0020 size: 32 bit */
-      union {
-         FLEXCAN_IMASK2_32B_tag IMRH;      /* deprecated - please avoid */
-
-                                  /* IMASK2 - Interrupt Masks 2 Register */
-         FLEXCAN_IMASK2_32B_tag IMASK2;    /* offset: 0x0024 size: 32 bit */
-
-      };
-      union {
-         FLEXCAN_IMASK1_32B_tag IMRL;      /* deprecated - please avoid */
-
-                                  /* IMASK1 - Interrupt Masks 1 Register */
-         FLEXCAN_IMASK1_32B_tag IMASK1;    /* offset: 0x0028 size: 32 bit */
-
-      };
-      union {
-         FLEXCAN_IFLAG2_32B_tag IFRH;      /* deprecated - please avoid */
-
-                                  /* IFLAG2 - Interrupt Flags 2 Register */
-         FLEXCAN_IFLAG2_32B_tag IFLAG2;    /* offset: 0x002C size: 32 bit */
-
-      };
-      union {
-         FLEXCAN_IFLAG1_32B_tag IFRL;      /* deprecated - please avoid */
-
-                                  /* IFLAG1 - Interrupt Flags 1 Register */
-         FLEXCAN_IFLAG1_32B_tag IFLAG1;    /* offset: 0x0030 size: 32 bit */
-
-      };
-      int8_t FLEXCAN_reserved_0034_C[76];
-      union {
-                                                     /*  Register set MB */
-         FLEXCAN_MB_tag MB[64];            /* offset: 0x0080  (0x0010 x 64) */
-
-                                                   /*  Alias name for MB */
-         FLEXCAN_MB_tag BUF[64];           /* deprecated - please avoid */
-
-         struct {
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG0_CS;  /* offset: 0x0080 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG0_ID;  /* offset: 0x0084 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3;  /* offset: 0x0088 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7;  /* offset: 0x008C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG1_CS;  /* offset: 0x0090 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG1_ID;  /* offset: 0x0094 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3;  /* offset: 0x0098 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7;  /* offset: 0x009C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG2_CS;  /* offset: 0x00A0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG2_ID;  /* offset: 0x00A4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3;  /* offset: 0x00A8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7;  /* offset: 0x00AC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG3_CS;  /* offset: 0x00B0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG3_ID;  /* offset: 0x00B4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3;  /* offset: 0x00B8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7;  /* offset: 0x00BC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG4_CS;  /* offset: 0x00C0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG4_ID;  /* offset: 0x00C4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3;  /* offset: 0x00C8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7;  /* offset: 0x00CC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG5_CS;  /* offset: 0x00D0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG5_ID;  /* offset: 0x00D4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3;  /* offset: 0x00D8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7;  /* offset: 0x00DC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG6_CS;  /* offset: 0x00E0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG6_ID;  /* offset: 0x00E4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3;  /* offset: 0x00E8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7;  /* offset: 0x00EC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG7_CS;  /* offset: 0x00F0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG7_ID;  /* offset: 0x00F4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3;  /* offset: 0x00F8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7;  /* offset: 0x00FC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG8_CS;  /* offset: 0x0100 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG8_ID;  /* offset: 0x0104 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3;  /* offset: 0x0108 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7;  /* offset: 0x010C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG9_CS;  /* offset: 0x0110 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG9_ID;  /* offset: 0x0114 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3;  /* offset: 0x0118 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7;  /* offset: 0x011C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG10_CS;  /* offset: 0x0120 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG10_ID;  /* offset: 0x0124 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3;  /* offset: 0x0128 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7;  /* offset: 0x012C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG11_CS;  /* offset: 0x0130 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG11_ID;  /* offset: 0x0134 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3;  /* offset: 0x0138 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7;  /* offset: 0x013C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG12_CS;  /* offset: 0x0140 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG12_ID;  /* offset: 0x0144 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3;  /* offset: 0x0148 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7;  /* offset: 0x014C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG13_CS;  /* offset: 0x0150 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG13_ID;  /* offset: 0x0154 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3;  /* offset: 0x0158 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7;  /* offset: 0x015C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG14_CS;  /* offset: 0x0160 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG14_ID;  /* offset: 0x0164 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3;  /* offset: 0x0168 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7;  /* offset: 0x016C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG15_CS;  /* offset: 0x0170 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG15_ID;  /* offset: 0x0174 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3;  /* offset: 0x0178 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7;  /* offset: 0x017C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG16_CS;  /* offset: 0x0180 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG16_ID;  /* offset: 0x0184 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3;  /* offset: 0x0188 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7;  /* offset: 0x018C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG17_CS;  /* offset: 0x0190 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG17_ID;  /* offset: 0x0194 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3;  /* offset: 0x0198 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7;  /* offset: 0x019C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG18_CS;  /* offset: 0x01A0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG18_ID;  /* offset: 0x01A4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3;  /* offset: 0x01A8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7;  /* offset: 0x01AC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG19_CS;  /* offset: 0x01B0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG19_ID;  /* offset: 0x01B4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3;  /* offset: 0x01B8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7;  /* offset: 0x01BC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG20_CS;  /* offset: 0x01C0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG20_ID;  /* offset: 0x01C4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3;  /* offset: 0x01C8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7;  /* offset: 0x01CC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG21_CS;  /* offset: 0x01D0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG21_ID;  /* offset: 0x01D4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3;  /* offset: 0x01D8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7;  /* offset: 0x01DC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG22_CS;  /* offset: 0x01E0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG22_ID;  /* offset: 0x01E4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3;  /* offset: 0x01E8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7;  /* offset: 0x01EC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG23_CS;  /* offset: 0x01F0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG23_ID;  /* offset: 0x01F4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3;  /* offset: 0x01F8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7;  /* offset: 0x01FC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG24_CS;  /* offset: 0x0200 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG24_ID;  /* offset: 0x0204 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3;  /* offset: 0x0208 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7;  /* offset: 0x020C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG25_CS;  /* offset: 0x0210 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG25_ID;  /* offset: 0x0214 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3;  /* offset: 0x0218 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7;  /* offset: 0x021C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG26_CS;  /* offset: 0x0220 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG26_ID;  /* offset: 0x0224 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3;  /* offset: 0x0228 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7;  /* offset: 0x022C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG27_CS;  /* offset: 0x0230 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG27_ID;  /* offset: 0x0234 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3;  /* offset: 0x0238 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7;  /* offset: 0x023C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG28_CS;  /* offset: 0x0240 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG28_ID;  /* offset: 0x0244 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3;  /* offset: 0x0248 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7;  /* offset: 0x024C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG29_CS;  /* offset: 0x0250 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG29_ID;  /* offset: 0x0254 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3;  /* offset: 0x0258 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7;  /* offset: 0x025C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG30_CS;  /* offset: 0x0260 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG30_ID;  /* offset: 0x0264 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3;  /* offset: 0x0268 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7;  /* offset: 0x026C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG31_CS;  /* offset: 0x0270 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG31_ID;  /* offset: 0x0274 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3;  /* offset: 0x0278 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7;  /* offset: 0x027C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG32_CS;  /* offset: 0x0280 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG32_ID;  /* offset: 0x0284 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3;  /* offset: 0x0288 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7;  /* offset: 0x028C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG33_CS;  /* offset: 0x0290 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG33_ID;  /* offset: 0x0294 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3;  /* offset: 0x0298 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7;  /* offset: 0x029C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG34_CS;  /* offset: 0x02A0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG34_ID;  /* offset: 0x02A4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3;  /* offset: 0x02A8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7;  /* offset: 0x02AC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG35_CS;  /* offset: 0x02B0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG35_ID;  /* offset: 0x02B4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3;  /* offset: 0x02B8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7;  /* offset: 0x02BC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG36_CS;  /* offset: 0x02C0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG36_ID;  /* offset: 0x02C4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3;  /* offset: 0x02C8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7;  /* offset: 0x02CC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG37_CS;  /* offset: 0x02D0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG37_ID;  /* offset: 0x02D4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3;  /* offset: 0x02D8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7;  /* offset: 0x02DC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG38_CS;  /* offset: 0x02E0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG38_ID;  /* offset: 0x02E4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3;  /* offset: 0x02E8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7;  /* offset: 0x02EC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG39_CS;  /* offset: 0x02F0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG39_ID;  /* offset: 0x02F4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3;  /* offset: 0x02F8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7;  /* offset: 0x02FC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG40_CS;  /* offset: 0x0300 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG40_ID;  /* offset: 0x0304 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3;  /* offset: 0x0308 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7;  /* offset: 0x030C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG41_CS;  /* offset: 0x0310 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG41_ID;  /* offset: 0x0314 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3;  /* offset: 0x0318 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7;  /* offset: 0x031C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG42_CS;  /* offset: 0x0320 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG42_ID;  /* offset: 0x0324 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3;  /* offset: 0x0328 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7;  /* offset: 0x032C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG43_CS;  /* offset: 0x0330 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG43_ID;  /* offset: 0x0334 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3;  /* offset: 0x0338 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7;  /* offset: 0x033C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG44_CS;  /* offset: 0x0340 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG44_ID;  /* offset: 0x0344 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3;  /* offset: 0x0348 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7;  /* offset: 0x034C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG45_CS;  /* offset: 0x0350 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG45_ID;  /* offset: 0x0354 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3;  /* offset: 0x0358 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7;  /* offset: 0x035C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG46_CS;  /* offset: 0x0360 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG46_ID;  /* offset: 0x0364 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3;  /* offset: 0x0368 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7;  /* offset: 0x036C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG47_CS;  /* offset: 0x0370 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG47_ID;  /* offset: 0x0374 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3;  /* offset: 0x0378 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7;  /* offset: 0x037C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG48_CS;  /* offset: 0x0380 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG48_ID;  /* offset: 0x0384 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3;  /* offset: 0x0388 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7;  /* offset: 0x038C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG49_CS;  /* offset: 0x0390 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG49_ID;  /* offset: 0x0394 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3;  /* offset: 0x0398 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7;  /* offset: 0x039C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG50_CS;  /* offset: 0x03A0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG50_ID;  /* offset: 0x03A4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3;  /* offset: 0x03A8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7;  /* offset: 0x03AC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG51_CS;  /* offset: 0x03B0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG51_ID;  /* offset: 0x03B4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3;  /* offset: 0x03B8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7;  /* offset: 0x03BC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG52_CS;  /* offset: 0x03C0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG52_ID;  /* offset: 0x03C4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3;  /* offset: 0x03C8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7;  /* offset: 0x03CC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG53_CS;  /* offset: 0x03D0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG53_ID;  /* offset: 0x03D4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3;  /* offset: 0x03D8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7;  /* offset: 0x03DC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG54_CS;  /* offset: 0x03E0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG54_ID;  /* offset: 0x03E4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3;  /* offset: 0x03E8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7;  /* offset: 0x03EC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG55_CS;  /* offset: 0x03F0 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG55_ID;  /* offset: 0x03F4 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3;  /* offset: 0x03F8 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7;  /* offset: 0x03FC size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG56_CS;  /* offset: 0x0400 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG56_ID;  /* offset: 0x0404 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3;  /* offset: 0x0408 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7;  /* offset: 0x040C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG57_CS;  /* offset: 0x0410 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG57_ID;  /* offset: 0x0414 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3;  /* offset: 0x0418 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7;  /* offset: 0x041C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG58_CS;  /* offset: 0x0420 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG58_ID;  /* offset: 0x0424 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3;  /* offset: 0x0428 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7;  /* offset: 0x042C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG59_CS;  /* offset: 0x0430 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG59_ID;  /* offset: 0x0434 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3;  /* offset: 0x0438 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7;  /* offset: 0x043C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG60_CS;  /* offset: 0x0440 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG60_ID;  /* offset: 0x0444 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3;  /* offset: 0x0448 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7;  /* offset: 0x044C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG61_CS;  /* offset: 0x0450 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG61_ID;  /* offset: 0x0454 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3;  /* offset: 0x0458 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7;  /* offset: 0x045C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG62_CS;  /* offset: 0x0460 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG62_ID;  /* offset: 0x0464 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3;  /* offset: 0x0468 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7;  /* offset: 0x046C size: 32 bit */
-                                    /* Message Buffer Control and Status */
-            FLEXCAN_MSG_CS_32B_tag MSG63_CS;  /* offset: 0x0470 size: 32 bit */
-                                      /* Message Buffer Identifier Field */
-            FLEXCAN_MSG_ID_32B_tag MSG63_ID;  /* offset: 0x0474 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3;  /* offset: 0x0478 size: 32 bit */
-                                         /* Message Buffer Data Register */
-            FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7;  /* offset: 0x047C size: 32 bit */
-         };
-
-      };
-      int8_t FLEXCAN_reserved_0480_C[1024];
-      union {
-       /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
-         FLEXCAN_RXIMR_32B_tag RXIMR[64];  /* offset: 0x0880  (0x0004 x 64) */
-
-         struct {
-       /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
-            FLEXCAN_RXIMR_32B_tag RXIMR0;  /* offset: 0x0880 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR1;  /* offset: 0x0884 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR2;  /* offset: 0x0888 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR3;  /* offset: 0x088C size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR4;  /* offset: 0x0890 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR5;  /* offset: 0x0894 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR6;  /* offset: 0x0898 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR7;  /* offset: 0x089C size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR8;  /* offset: 0x08A0 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR9;  /* offset: 0x08A4 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR10;  /* offset: 0x08A8 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR11;  /* offset: 0x08AC size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR12;  /* offset: 0x08B0 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR13;  /* offset: 0x08B4 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR14;  /* offset: 0x08B8 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR15;  /* offset: 0x08BC size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR16;  /* offset: 0x08C0 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR17;  /* offset: 0x08C4 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR18;  /* offset: 0x08C8 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR19;  /* offset: 0x08CC size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR20;  /* offset: 0x08D0 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR21;  /* offset: 0x08D4 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR22;  /* offset: 0x08D8 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR23;  /* offset: 0x08DC size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR24;  /* offset: 0x08E0 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR25;  /* offset: 0x08E4 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR26;  /* offset: 0x08E8 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR27;  /* offset: 0x08EC size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR28;  /* offset: 0x08F0 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR29;  /* offset: 0x08F4 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR30;  /* offset: 0x08F8 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR31;  /* offset: 0x08FC size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR32;  /* offset: 0x0900 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR33;  /* offset: 0x0904 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR34;  /* offset: 0x0908 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR35;  /* offset: 0x090C size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR36;  /* offset: 0x0910 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR37;  /* offset: 0x0914 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR38;  /* offset: 0x0918 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR39;  /* offset: 0x091C size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR40;  /* offset: 0x0920 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR41;  /* offset: 0x0924 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR42;  /* offset: 0x0928 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR43;  /* offset: 0x092C size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR44;  /* offset: 0x0930 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR45;  /* offset: 0x0934 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR46;  /* offset: 0x0938 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR47;  /* offset: 0x093C size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR48;  /* offset: 0x0940 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR49;  /* offset: 0x0944 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR50;  /* offset: 0x0948 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR51;  /* offset: 0x094C size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR52;  /* offset: 0x0950 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR53;  /* offset: 0x0954 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR54;  /* offset: 0x0958 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR55;  /* offset: 0x095C size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR56;  /* offset: 0x0960 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR57;  /* offset: 0x0964 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR58;  /* offset: 0x0968 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR59;  /* offset: 0x096C size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR60;  /* offset: 0x0970 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR61;  /* offset: 0x0974 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR62;  /* offset: 0x0978 size: 32 bit */
-            FLEXCAN_RXIMR_32B_tag RXIMR63;  /* offset: 0x097C size: 32 bit */
-         };
-
-      };
-   } FLEXCAN_tag;
-
-
-#define FLEXCAN_A (*(volatile FLEXCAN_tag *) 0xFFFC0000UL)
-#define FLEXCAN_B (*(volatile FLEXCAN_tag *) 0xFFFC4000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: DMA_CH_MUX  */
-/*                                                              */
-/****************************************************************/
-
-
-   /* Register layout for all registers CHCONFIG... */
-
-   typedef union {   /* CHCONFIG[0-15] - Channel Configuration Registers */
-      vuint8_t R;
-      struct {
-         vuint8_t   ENBL:1;            /* DMA Channel Enable */
-         vuint8_t   TRIG:1;            /* DMA Channel Trigger Enable */
-         vuint8_t   SOURCE:6;          /* DMA Channel Source */
-      } B;
-   } DMA_CH_MUX_CHCONFIG_8B_tag;
-
-
-
-   typedef struct DMA_CH_MUX_struct_tag { /* start of DMA_CH_MUX_tag */
-      union {
-                     /* CHCONFIG[0-15] - Channel Configuration Registers */
-         DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16];  /* offset: 0x0000  (0x0001 x 16) */
-
-         struct {
-                     /* CHCONFIG[0-15] - Channel Configuration Registers */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0;  /* offset: 0x0000 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1;  /* offset: 0x0001 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2;  /* offset: 0x0002 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3;  /* offset: 0x0003 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4;  /* offset: 0x0004 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5;  /* offset: 0x0005 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6;  /* offset: 0x0006 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7;  /* offset: 0x0007 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8;  /* offset: 0x0008 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9;  /* offset: 0x0009 size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10;  /* offset: 0x000A size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11;  /* offset: 0x000B size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12;  /* offset: 0x000C size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13;  /* offset: 0x000D size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14;  /* offset: 0x000E size: 8 bit */
-            DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15;  /* offset: 0x000F size: 8 bit */
-         };
-
-      };
-   } DMA_CH_MUX_tag;
-
-
-#define DMA_CH_MUX (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL)
-
-
-
-/****************************************************************/
-/*                                                              */
-/* Module: FR  */
-/*                                                              */
-/****************************************************************/
-
-   typedef union {   /* Module Version Number */
-      vuint16_t R;
-      struct {
-         vuint16_t  CHIVER:8;          /* VERSION NUMBER OF CHI */
-         vuint16_t  PEVER:8;           /* VERSION NUMBER OF PE */
-      } B;
-   } FR_MVR_16B_tag;
-
-   typedef union {   /* Module Configuration Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  MEN:1;             /* Module Enable */
-         vuint16_t  SBFF:1;            /* System Bus Failure Freeze */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SCM:1;             /* single channel device mode */
-#else
-         vuint16_t  SCMD:1;              /* deprecated name - please avoid */
-#endif
-         vuint16_t  CHB:1;             /* Channel B enable */
-         vuint16_t  CHA:1;             /* channel A enable */
-         vuint16_t  SFFE:1;            /* Sync. frame filter Enable */
-         vuint16_t  ECCE:1;            /* ECC Functionlity Enable */
-         vuint16_t  TMODER:1;          /* Functional Test mode */
-         vuint16_t  FUM:1;             /* FIFO Update Mode */
-         vuint16_t  FAM:1;             /* FIFO Address Mode */
-         vuint16_t:1;
-         vuint16_t  CLKSEL:1;          /* Protocol Engine clock source select */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  BITRATE:3;         /* Bus bit rate */
-#else
-         vuint16_t  PRESCALE:3;          /* deprecated name - please avoid */
-#endif
-         vuint16_t:1;
-      } B;
-   } FR_MCR_16B_tag;
-
-   typedef union {   /* SYSTEM MEMORY BASE ADD HIGH REG */
-      vuint16_t R;
-      struct {
-         vuint16_t  SMBA_31_16:16;     /* SYS_MEM_BASE_ADDR[31:16] */
-      } B;
-   } FR_SYMBADHR_16B_tag;
-
-   typedef union {   /* SYSTEM MEMORY BASE ADD LOW  REG */
-      vuint16_t R;
-      struct {
-         vuint16_t  SMBA_15_4:12;      /* SYS_MEM_BASE_ADDR[15:4] */
-         vuint16_t:4;
-      } B;
-   } FR_SYMBADLR_16B_tag;
-
-   typedef union {   /* STROBE SIGNAL CONTROL REGISTER */
-      vuint16_t R;
-      struct {
-         vuint16_t  WMD:1;             /* DEFINES WRITE MODE OF REG */
-         vuint16_t:3;
-         vuint16_t  SEL:4;             /* STROBE SIGNSL SELECT */
-         vuint16_t:3;
-         vuint16_t  ENB:1;             /* STROBE SIGNAL ENABLE */
-         vuint16_t:2;
-         vuint16_t  STBPSEL:2;         /* STROBE PORT SELECT */
-      } B;
-   } FR_STBSCR_16B_tag;
-
-   typedef union {   /* MESSAGE BUFFER DATA SIZE REGISTER */
-      vuint16_t R;
-      struct {
-         vuint16_t:1;
-         vuint16_t  MBSEG2DS:7;        /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */
-         vuint16_t:1;
-         vuint16_t  MBSEG1DS:7;        /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */
-      } B;
-   } FR_MBDSR_16B_tag;
-
-   typedef union {   /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  LAST_MB_SEG1:6;    /* LAST MESS BUFFER IN SEG 1 */
-         vuint16_t:2;
-         vuint16_t  LAST_MB_UTIL:6;    /* LAST MESSAGE BUFFER UTILISED */
-      } B;
-   } FR_MBSSUTR_16B_tag;
-
-   typedef union {   /* PE DRAM ACCESS REGISTER */
-      vuint16_t R;
-      struct {
-         vuint16_t  INST:4;            /* PE DRAM ACCESS INSTRUCTION */
-         vuint16_t  ADDR:11;           /* PE DRAM ACCESS ADDRESS */
-         vuint16_t  DAD:1;             /* PE DRAM ACCESS DONE */
-      } B;
-   } FR_PEDRAR_16B_tag;
-
-   typedef union {   /* PE DRAM DATA REGISTER */
-      vuint16_t R;
-      struct {
-         vuint16_t  DATA:16;           /* DATA TO BE READ OR WRITTEN */
-      } B;
-   } FR_PEDRDR_16B_tag;
-
-   typedef union {   /* PROTOCOL OPERATION CONTROL REG */
-      vuint16_t R;
-      struct {
-         vuint16_t  WME:1;             /* WRITE MODE EXTERNAL CORRECTION */
-         vuint16_t:3;
-         vuint16_t  EOC_AP:2;          /* EXTERNAL OFFSET CORRECTION APPLICATION */
-         vuint16_t  ERC_AP:2;          /* EXTERNAL RATE CORRECTION APPLICATION */
-         vuint16_t  BSY:1;             /* PROTOCOL CONTROL COMMAND WRITE BUSY */
-         vuint16_t:3;
-         vuint16_t  POCCMD:4;          /* PROTOCOL CONTROL COMMAND */
-      } B;
-   } FR_POCR_16B_tag;
-
-   typedef union {   /* GLOBAL INTERRUPT FLAG & ENABLE REG */
-      vuint16_t R;
-      struct {
-         vuint16_t  MIF:1;             /* MODULE INTERRUPT FLAG */
-         vuint16_t  PRIF:1;            /* PROTOCOL INTERRUPT FLAG */
-         vuint16_t  CHIF:1;            /* CHI INTERRUPT FLAG */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  WUPIF:1;           /* WAKEUP INTERRUPT FLAG */
-#else
-         vuint16_t  WKUPIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FAFBIF:1;          /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */
-#else
-         vuint16_t  FNEBIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FAFAIF:1;          /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */
-#else
-         vuint16_t  FNEAIF:1;            /* deprecated name - please avoid */
-#endif
-         vuint16_t  RBIF:1;            /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */
-         vuint16_t  TBIF:1;            /* TRANSMIT BUFFER INTERRUPT FLAG */
-         vuint16_t  MIE:1;             /* MODULE INTERRUPT ENABLE */
-         vuint16_t  PRIE:1;            /* PROTOCOL INTERRUPT ENABLE */
-         vuint16_t  CHIE:1;            /* CHI INTERRUPT ENABLE */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  WUPIE:1;           /* WAKEUP INTERRUPT ENABLE */
-#else
-         vuint16_t  WKUPIE:1;            /* deprecated name - please avoid */
-#endif
-         vuint16_t  FNEBIE:1;          /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */
-         vuint16_t  FNEAIE:1;          /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */
-         vuint16_t  RBIE:1;            /* RECEIVE BUFFER INTERRUPT ENABLE */
-         vuint16_t  TBIE:1;            /* TRANSMIT BUFFER INTERRUPT ENABLE */
-      } B;
-   } FR_GIFER_16B_tag;
-
-   typedef union {   /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FATL_IF:1;         /* FATAL PROTOCOL ERROR INTERRUPT FLAG */
-#else
-         vuint16_t  FATLIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  INTL_IF:1;         /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */
-#else
-         vuint16_t  INTLIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  ILCF_IF:1;         /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */
-#else
-         vuint16_t  ILCFIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CSA_IF:1;          /* COLDSTART ABORT INTERRUPT FLAG */
-#else
-         vuint16_t  CSAIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MRC_IF:1;          /* MISSING RATE CORRECTION INTERRUPT FLAG */
-#else
-         vuint16_t  MRCIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MOC_IF:1;          /* MISSING OFFSET CORRECTION INTERRUPT FLAG */
-#else
-         vuint16_t  MOCIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CCL_IF:1;          /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */
-#else
-         vuint16_t  CCLIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MXS_IF:1;          /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */
-#else
-         vuint16_t  MXSIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MTX_IF:1;          /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */
-#else
-         vuint16_t  MTXIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  LTXB_IF:1;         /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */
-#else
-         vuint16_t  LTXBIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  LTXA_IF:1;         /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */
-#else
-         vuint16_t  LTXAIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  TBVB_IF:1;         /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */
-#else
-         vuint16_t  TBVBIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  TBVA_IF:1;         /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */
-#else
-         vuint16_t  TBVAIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  TI2_IF:1;          /* TIMER 2 EXPIRED INTERRUPT FLAG */
-#else
-         vuint16_t  TI2IF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  TI1_IF:1;          /* TIMER 1 EXPIRED INTERRUPT FLAG */
-#else
-         vuint16_t  TI1IF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CYS_IF:1;          /* CYCLE START INTERRUPT FLAG */
-#else
-         vuint16_t  CYSIF:1;             /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PIFR0_16B_tag;
-
-   typedef union {   /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  EMC_IF:1;          /* ERROR MODE CHANGED INTERRUPT FLAG */
-#else
-         vuint16_t  EMCIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  IPC_IF:1;          /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */
-#else
-         vuint16_t  IPCIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  PECF_IF:1;         /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */
-#else
-         vuint16_t  PECFIF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  PSC_IF:1;          /* PROTOCOL STATE CHANGED INTERRUPT FLAG */
-#else
-         vuint16_t  PSCIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SSI3_IF:1;         /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */
-#else
-         vuint16_t  SSI3IF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SSI2_IF:1;         /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */
-#else
-         vuint16_t  SSI2IF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SSI1_IF:1;         /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */
-#else
-         vuint16_t  SSI1IF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SSI0_IF:1;         /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */
-#else
-         vuint16_t  SSI0IF:1;            /* deprecated name - please avoid */
-#endif
-         vuint16_t:2;
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  EVT_IF:1;          /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */
-#else
-         vuint16_t  EVTIF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  ODT_IF:1;          /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */
-#else
-         vuint16_t  ODTIF:1;             /* deprecated name - please avoid */
-#endif
-         vuint16_t:4;
-      } B;
-   } FR_PIFR1_16B_tag;
-
-   typedef union {   /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FATL_IE:1;         /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */
-#else
-         vuint16_t  FATLIE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  INTL_IE:1;         /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */
-#else
-         vuint16_t  INTLIE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  ILCF_IE:1;         /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */
-#else
-         vuint16_t  ILCFIE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CSA_IE:1;          /* COLDSTART ABORT INTERRUPT ENABLE */
-#else
-         vuint16_t  CSAIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MRC_IE:1;          /* MISSING RATE CORRECTION INTERRUPT ENABLE */
-#else
-         vuint16_t  MRCIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MOC_IE:1;          /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */
-#else
-         vuint16_t  MOCIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CCL_IE:1;          /* CLOCK CORRECTION LIMIT REACHED */
-#else
-         vuint16_t  CCLIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MXS_IE:1;          /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */
-#else
-         vuint16_t  MXSIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MTX_IE:1;          /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */
-#else
-         vuint16_t  MTXIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  LTXB_IE:1;         /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */
-#else
-         vuint16_t  LTXBIE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  LTXA_IE:1;         /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */
-#else
-         vuint16_t  LTXAIE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  TBVB_IE:1;         /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */
-#else
-         vuint16_t  TBVBIE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  TBVA_IE:1;         /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */
-#else
-         vuint16_t  TBVAIE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  TI2_IE:1;          /* TIMER 2 EXPIRED INTERRUPT ENABLE */
-#else
-         vuint16_t  TI2IE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  TI1_IE:1;          /* TIMER 1 EXPIRED INTERRUPT ENABLE */
-#else
-         vuint16_t  TI1IE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CYS_IE:1;          /* CYCLE START INTERRUPT ENABLE */
-#else
-         vuint16_t  CYSIE:1;             /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PIER0_16B_tag;
-
-   typedef union {   /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  EMC_IE:1;          /* ERROR MODE CHANGED INTERRUPT Enable */
-#else
-         vuint16_t  EMCIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  IPC_IE:1;          /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */
-#else
-         vuint16_t  IPCIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  PECF_IE:1;         /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */
-#else
-         vuint16_t  PECFIE:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  PSC_IE:1;          /* PROTOCOL STATE CHANGED INTERRUPT Enable */
-#else
-         vuint16_t  PSCIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SSI_3_0_IE:4;      /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */
-#else
-         vuint16_t  SSI3IE:1;
-         vuint16_t  SSI2IE:1;
-         vuint16_t  SSI1IE:1;
-         vuint16_t  SSI0IE:1;
-#endif
-         
-         vuint16_t:2;
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  EVT_IE:1;          /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */
-#else
-         vuint16_t  EVTIE:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  ODT_IE:1;          /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */
-#else
-         vuint16_t  ODTIE:1;             /* deprecated name - please avoid */
-#endif
-         vuint16_t:4;
-      } B;
-   } FR_PIER1_16B_tag;
-
-   typedef union {   /* CHI ERROR FLAG REGISTER */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FRLB_EF:1;         /* FRAME LOST CHANNEL B ERROR FLAG */
-#else
-         vuint16_t  FRLBEF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FRLA_EF:1;         /* FRAME LOST CHANNEL A ERROR FLAG */
-#else
-         vuint16_t  FRLAEF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  PCMI_EF:1;         /* PROTOCOL COMMAND IGNORED ERROR FLAG */
-#else
-         vuint16_t  PCMIEF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FOVB_EF:1;         /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */
-#else
-         vuint16_t  FOVBEF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FOVA_EF:1;         /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */
-#else
-         vuint16_t  FOVAEF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MBS_EF:1;          /* MESSAGE BUFFER SEARCH ERROR FLAG */
-#else
-         vuint16_t  MSBEF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MBU_EF:1;          /* MESSAGE BUFFER UTILIZATION ERROR FLAG */
-#else
-         vuint16_t  MBUEF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  LCK_EF:1;          /* LOCK ERROR FLAG */
-#else
-         vuint16_t  LCKEF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  DBL_EF:1;          /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */
-#else
-         vuint16_t  DBLEF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SBCF_EF:1;         /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */
-#else
-         vuint16_t  SBCFEF:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FID_EF:1;          /* FRAME ID ERROR FLAG */
-#else
-         vuint16_t  FIDEF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  DPL_EF:1;          /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */
-#else
-         vuint16_t  DPLEF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SPL_EF:1;          /* STATIC PAYLOAD LENGTH ERROR FLAG */
-#else
-         vuint16_t  SPLEF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  NML_EF:1;          /* NETWORK MANAGEMENT LENGTH ERROR FLAG */
-#else
-         vuint16_t  NMLEF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  NMF_EF:1;          /* NETWORK MANAGEMENT FRAME ERROR FLAG */
-#else
-         vuint16_t  NMFEF:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  ILSA_EF:1;         /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */
-#else
-         vuint16_t  ILSAEF:1;            /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_CHIERFR_16B_tag;
-
-   typedef union {   /* Message Buffer Interrupt Vector Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  TBIVEC:6;          /* Transmit Buffer Interrupt Vector */
-         vuint16_t:2;
-         vuint16_t  RBIVEC:6;          /* Receive Buffer Interrupt Vector */
-      } B;
-   } FR_MBIVEC_16B_tag;
-
-   typedef union {   /* Channel A Status Error Counter Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  STATUS_ERR_CNT:16;   /* Channel Status Error Counter */
-      } B;
-   } FR_CASERCR_16B_tag;
-
-   typedef union {   /* Channel B Status Error Counter Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  STATUS_ERR_CNT:16;   /* Channel Status Error Counter */
-      } B;
-   } FR_CBSERCR_16B_tag;
-
-   typedef union {   /* Protocol Status Register 0 */
-      vuint16_t R;
-      struct {
-         vuint16_t  ERRMODE:2;         /* Error Mode */
-         vuint16_t  SLOTMODE:2;        /* Slot Mode */
-         vuint16_t:1;
-         vuint16_t  PROTSTATE:3;       /* Protocol State */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  STARTUPSTATE:4;    /* Startup State */
-#else
-         vuint16_t  SUBSTATE:4;          /* deprecated name - please avoid */
-#endif
-         vuint16_t  WAKEUPSTATE:4;     /* Wakeup Status */
-      } B;
-   } FR_PSR0_16B_tag;
-
-   typedef union {   /* Protocol Status Register 1 */
-      vuint16_t R;
-      struct {
-         vuint16_t  CSAA:1;            /* Coldstart Attempt Aborted Flag */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CSP:1;             /* Leading Coldstart Path */
-#else
-         vuint16_t  SCP:1;               /* deprecated name - please avoid */
-#endif
-         vuint16_t:1;
-         vuint16_t  REMCSAT:5;         /* Remaining Coldstart Attempts */
-         vuint16_t  CPN:1;             /* Leading Coldstart Path Noise */
-         vuint16_t  HHR:1;             /* Host Halt Request Pending */
-         vuint16_t  FRZ:1;             /* Freeze Occurred */
-         vuint16_t  APTAC:5;           /* Allow Passive to Active Counter */
-      } B;
-   } FR_PSR1_16B_tag;
-
-   typedef union {   /* Protocol Status Register 2 */
-      vuint16_t R;
-      struct {
-         vuint16_t  NBVB:1;            /* NIT Boundary Violation on Channel B */
-         vuint16_t  NSEB:1;            /* NIT Syntax Error on Channel B */
-         vuint16_t  STCB:1;            /* Symbol Window Transmit Conflict on Channel B */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SSVB:1;            /* Symbol Window Boundary Violation on Channel B */
-#else
-         vuint16_t  SBVB:1;              /* deprecated name - please avoid */
-#endif
-         vuint16_t  SSEB:1;            /* Symbol Window Syntax Error on Channel B */
-         vuint16_t  MTB:1;             /* Media Access Test Symbol MTS Received on Channel B */
-         vuint16_t  NBVA:1;            /* NIT Boundary Violation on Channel A */
-         vuint16_t  NSEA:1;            /* NIT Syntax Error on Channel A */
-         vuint16_t  STCA:1;            /* Symbol Window Transmit Conflict on Channel A */
-         vuint16_t  SBVA:1;            /* Symbol Window Boundary Violation on Channel A */
-         vuint16_t  SSEA:1;            /* Symbol Window Syntax Error on Channel A */
-         vuint16_t  MTA:1;             /* Media Access Test Symbol MTS Received on Channel A */
-         vuint16_t  CLKCORRFAILCNT:4;   /* Clock Correction Failed Counter */
-      } B;
-   } FR_PSR2_16B_tag;
-
-   typedef union {   /* Protocol Status Register 3 */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  WUB:1;             /* Wakeup Symbol Received on Channel B */
-         vuint16_t  ABVB:1;            /* Aggregated Boundary Violation on Channel B */
-         vuint16_t  AACB:1;            /* Aggregated Additional Communication on Channel B */
-         vuint16_t  ACEB:1;            /* Aggregated Content Error on Channel B */
-         vuint16_t  ASEB:1;            /* Aggregated Syntax Error on Channel B */
-         vuint16_t  AVFB:1;            /* Aggregated Valid Frame on Channel B */
-         vuint16_t:2;
-         vuint16_t  WUA:1;             /* Wakeup Symbol Received on Channel A */
-         vuint16_t  ABVA:1;            /* Aggregated Boundary Violation on Channel A */
-         vuint16_t  AACA:1;            /* Aggregated Additional Communication on Channel A */
-         vuint16_t  ACEA:1;            /* Aggregated Content Error on Channel A */
-         vuint16_t  ASEA:1;            /* Aggregated Syntax Error on Channel A */
-         vuint16_t  AVFA:1;            /* Aggregated Valid Frame on Channel A */
-      } B;
-   } FR_PSR3_16B_tag;
-
-   typedef union {   /* Macrotick Counter Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  MTCT:14;           /* Macrotick Counter */
-      } B;
-   } FR_MTCTR_16B_tag;
-
-   typedef union {   /* Cycle Counter Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:10;
-         vuint16_t  CYCCNT:6;          /* Cycle Counter */
-      } B;
-   } FR_CYCTR_16B_tag;
-
-   typedef union {   /* Slot Counter Channel A Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  SLOTCNTA:11;       /* Slot Counter Value for Channel A */
-      } B;
-   } FR_SLTCTAR_16B_tag;
-
-   typedef union {   /* Slot Counter Channel B Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  SLOTCNTB:11;       /* Slot Counter Value for Channel B */
-      } B;
-   } FR_SLTCTBR_16B_tag;
-
-   typedef union {   /* Rate Correction Value Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  RATECORR:16;       /* Rate Correction Value */
-      } B;
-   } FR_RTCORVR_16B_tag;
-
-   typedef union {   /* Offset Correction Value Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:6;
-         vuint16_t  OFFSETCORR:10;     /* Offset Correction Value */
-      } B;
-   } FR_OFCORVR_16B_tag;
-
-   typedef union {   /* Combined Interrupt Flag Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:8;
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MIF:1;             /* Module Interrupt Flag */
-#else
-         vuint16_t  MIFR:1;              /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  PRIF:1;            /* Protocol Interrupt Flag */
-#else
-         vuint16_t  PRIFR:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CHIF:1;            /* CHI Interrupt Flag */
-#else
-         vuint16_t  CHIFR:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  WUPIF:1;           /* Wakeup Interrupt Flag */
-#else
-         vuint16_t  WUPIFR:1;            /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FAFBIF:1;          /* Receive FIFO channel B Almost Full Interrupt Flag */
-#else
-         vuint16_t  FNEBIFR:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FAFAIF:1;          /* Receive FIFO channel A Almost Full Interrupt Flag */
-#else
-         vuint16_t  FNEAIFR:1;           /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  RBIF:1;            /* Receive Message Buffer Interrupt Flag */
-#else
-         vuint16_t  RBIFR:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  TBIF:1;            /* Transmit Message Buffer Interrupt Flag */
-#else
-         vuint16_t  TBIFR:1;             /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_CIFR_16B_tag;
-
-   typedef union {   /* System Memory Access Time-Out Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:8;
-         vuint16_t  TIMEOUT:8;         /* Time-Out */
-      } B;
-   } FR_SYMATOR_16B_tag;
-
-   typedef union {   /* Sync Frame Counter Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  SFEVB:4;           /* Sync Frames Channel B, even cycle */
-         vuint16_t  SFEVA:4;           /* Sync Frames Channel A, even cycle */
-         vuint16_t  SFODB:4;           /* Sync Frames Channel B, odd cycle */
-         vuint16_t  SFODA:4;           /* Sync Frames Channel A, odd cycle */
-      } B;
-   } FR_SFCNTR_16B_tag;
-
-   typedef union {   /* Sync Frame Table Offset Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  SFT_OFFSET_15_1:15;   /* Sync Frame Table Offset */
-         vuint16_t:1;
-      } B;
-   } FR_SFTOR_16B_tag;
-
-   typedef union {   /* Sync Frame Table Configuration, Control, Status Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  ELKT:1;            /* Even Cycle Tables Lock/Unlock Trigger */
-         vuint16_t  OLKT:1;            /* Odd Cycle Tables Lock/Unlock Trigger */
-         vuint16_t  CYCNUM:6;          /* Cycle Number */
-         vuint16_t  ELKS:1;            /* Even Cycle Tables Lock Status */
-         vuint16_t  OLKS:1;            /* Odd Cycle Tables Lock Status */
-         vuint16_t  EVAL:1;            /* Even Cycle Tables Valid */
-         vuint16_t  OVAL:1;            /* Odd Cycle Tables Valid */
-         vuint16_t:1;
-         vuint16_t  OPT:1;             /* One Pair Trigger */
-         vuint16_t  SDVEN:1;           /* Sync Frame Deviation Table Enable */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  SIVEN:1;           /* Sync Frame ID Table Enable */
-#else
-         vuint16_t  SIDEN:1;             /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_SFTCCSR_16B_tag;
-
-   typedef union {   /* Sync Frame ID Rejection Filter */
-      vuint16_t R;
-      struct {
-         vuint16_t:6;
-         vuint16_t  SYNFRID:10;        /* Sync Frame Rejection ID */
-      } B;
-   } FR_SFIDRFR_16B_tag;
-
-   typedef union {   /* Sync Frame ID Acceptance Filter Value Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:6;
-         vuint16_t  FVAL:10;           /* Filter Value */
-      } B;
-   } FR_SFIDAFVR_16B_tag;
-
-   typedef union {   /* Sync Frame ID Acceptance Filter Mask Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:6;
-         vuint16_t  FMSK:10;           /* Filter Mask */
-      } B;
-   } FR_SFIDAFMR_16B_tag;
-
-   typedef union {   /* Network Management Vector Register0 */
-      vuint16_t R;
-      struct {
-         vuint16_t  NMVP_15_8:8;       /* Network Management Vector Part */
-         vuint16_t  NMVP_7_0:8;        /* Network Management Vector Part */
-      } B;
-   } FR_NMVR0_16B_tag;
-
-   typedef union {   /* Network Management Vector Register1 */
-      vuint16_t R;
-      struct {
-         vuint16_t  NMVP_15_8:8;       /* Network Management Vector Part */
-         vuint16_t  NMVP_7_0:8;        /* Network Management Vector Part */
-      } B;
-   } FR_NMVR1_16B_tag;
-
-   typedef union {   /* Network Management Vector Register2 */
-      vuint16_t R;
-      struct {
-         vuint16_t  NMVP_15_8:8;       /* Network Management Vector Part */
-         vuint16_t  NMVP_7_0:8;        /* Network Management Vector Part */
-      } B;
-   } FR_NMVR2_16B_tag;
-
-   typedef union {   /* Network Management Vector Register3 */
-      vuint16_t R;
-      struct {
-         vuint16_t  NMVP_15_8:8;       /* Network Management Vector Part */
-         vuint16_t  NMVP_7_0:8;        /* Network Management Vector Part */
-      } B;
-   } FR_NMVR3_16B_tag;
-
-   typedef union {   /* Network Management Vector Register4 */
-      vuint16_t R;
-      struct {
-         vuint16_t  NMVP_15_8:8;       /* Network Management Vector Part */
-         vuint16_t  NMVP_7_0:8;        /* Network Management Vector Part */
-      } B;
-   } FR_NMVR4_16B_tag;
-
-   typedef union {   /* Network Management Vector Register5 */
-      vuint16_t R;
-      struct {
-         vuint16_t  NMVP_15_8:8;       /* Network Management Vector Part */
-         vuint16_t  NMVP_7_0:8;        /* Network Management Vector Part */
-      } B;
-   } FR_NMVR5_16B_tag;
-
-   typedef union {   /* Network Management Vector Length Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:12;
-         vuint16_t  NMVL:4;            /* Network Management Vector Length */
-      } B;
-   } FR_NMVLR_16B_tag;
-
-   typedef union {   /* Timer Configuration and Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-#ifndef USE_FIELD_ALIASES_FR		 
-         vuint16_t  T2_CFG:1;          /* Timer T2 Configuration */
-#else
-         vuint16_t  T2CFG:1;          /* Timer T2 Configuration */
-#endif		
-#ifndef USE_FIELD_ALIASES_FR	 
-         vuint16_t  T2_REP:1;          /* Timer T2 Repetitive Mode */
-#else
-         vuint16_t  T2REP:1;          /* Timer T2 Configuration */
-#endif	
-         vuint16_t:1;
-         vuint16_t  T2SP:1;            /* Timer T2 Stop */
-         vuint16_t  T2TR:1;            /* Timer T2 Trigger */
-         vuint16_t  T2ST:1;            /* Timer T2 State */
-         vuint16_t:3;
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  T1_REP:1;          /* Timer T1 Repetitive Mode */
-#else
-         vuint16_t  T1REP:1;          
-#endif	
-         vuint16_t:1;
-         vuint16_t  T1SP:1;            /* Timer T1 Stop */
-         vuint16_t  T1TR:1;            /* Timer T1 Trigger */
-         vuint16_t  T1ST:1;            /* Timer T1 State */
-      } B;
-   } FR_TICCR_16B_tag;
-
-   typedef union {   /* Timer 1 Cycle Set Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  T1_CYC_VAL:6;      /* Timer T1 Cycle Filter Value */
-#else
-         vuint16_t  TI1CYCVAL:1;        /* Timer T1 Cycle Filter Value */       
-#endif	
-         vuint16_t:2;
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  T1_CYC_MSK:6;      /* Timer T1 Cycle Filter Mask */
-#else
-         vuint16_t  TI1CYCMSK:1;      /* Timer T1 Cycle Filter Mask */
-#endif	
-      } B;
-   } FR_TI1CYSR_16B_tag;
-
-   typedef union {   /* Timer 1 Macrotick Offset Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  T1_MTOFFSET:14;    /* Timer 1 Macrotick Offset */
-      } B;
-   } FR_TI1MTOR_16B_tag;
-
-   typedef union {   /* Timer 2 Configuration Register 0 */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  T2_CYC_VAL:6;      /* Timer T2 Cycle Filter Value */
-         vuint16_t:2;
-         vuint16_t  T2_CYC_MSK:6;      /* Timer T2 Cycle Filter Mask */
-      } B;
-   } FR_TI2CR0_16B_tag;
-
-   typedef union {   /* Timer 2 Configuration Register 1 */
-      vuint16_t R;
-      struct {
-         vuint16_t  T2_MTCNT:16;       /* Timer T2 Macrotick Offset */
-      } B;
-   } FR_TI2CR1_16B_tag;
-
-   typedef union {   /* Slot Status Selection Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  WMD:1;             /* Write Mode */
-         vuint16_t:1;
-         vuint16_t  SEL:2;             /* Selector */
-         vuint16_t:1;
-         vuint16_t  SLOTNUMBER:11;     /* Slot Number */
-      } B;
-   } FR_SSSR_16B_tag;
-
-   typedef union {   /* Slot Status Counter Condition Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  WMD:1;             /* Write Mode */
-         vuint16_t:1;
-         vuint16_t  SEL:2;             /* Selector */
-         vuint16_t:1;
-         vuint16_t  CNTCFG:2;          /* Counter Configuration */
-         vuint16_t  MCY:1;             /* Multi Cycle Selection */
-         vuint16_t  VFR:1;             /* Valid Frame Restriction */
-         vuint16_t  SYF:1;             /* Sync Frame Restriction */
-         vuint16_t  NUF:1;             /* Null Frame Restriction */
-         vuint16_t  SUF:1;             /* Startup Frame Restriction */
-         vuint16_t  STATUSMASK:4;      /* Slot Status Mask */
-      } B;
-   } FR_SSCCR_16B_tag;
-
-   typedef union {   /* Slot Status Register0 */
-      vuint16_t R;
-      struct {
-         vuint16_t  VFB:1;             /* Valid Frame on Channel B */
-         vuint16_t  SYB:1;             /* Sync Frame Indicator Channel B */
-         vuint16_t  NFB:1;             /* Null Frame Indicator Channel B */
-         vuint16_t  SUB:1;             /* Startup Frame Indicator Channel B */
-         vuint16_t  SEB:1;             /* Syntax Error on Channel B */
-         vuint16_t  CEB:1;             /* Content Error on Channel B */
-         vuint16_t  BVB:1;             /* Boundary Violation on Channel B */
-         vuint16_t  TCB:1;             /* Transmission Conflict on Channel B */
-         vuint16_t  VFA:1;             /* Valid Frame on Channel A */
-         vuint16_t  SYA:1;             /* Sync Frame Indicator Channel A */
-         vuint16_t  NFA:1;             /* Null Frame Indicator Channel A */
-         vuint16_t  SUA:1;             /* Startup Frame Indicator Channel A */
-         vuint16_t  SEA:1;             /* Syntax Error on Channel A */
-         vuint16_t  CEA:1;             /* Content Error on Channel A */
-         vuint16_t  BVA:1;             /* Boundary Violation on Channel A */
-         vuint16_t  TCA:1;             /* Transmission Conflict on Channel A */
-      } B;
-   } FR_SSR_16B_tag;
-
-   
-
-   typedef union {   /* Slot Status Counter Register0 */
-      vuint16_t R;
-      struct {
-         vuint16_t  SLOTSTSTUSCNT:16;   /* Slot Status Counter */
-      } B;
-   } FR_SSCR0_16B_tag;
-
-   typedef union {   /* Slot Status Counter Register1 */
-      vuint16_t R;
-      struct {
-         vuint16_t  SLOTSTSTUSCNT:16;   /* Slot Status Counter */
-      } B;
-   } FR_SSCR1_16B_tag;
-
-   typedef union {   /* Slot Status Counter Register2 */
-      vuint16_t R;
-      struct {
-         vuint16_t  SLOTSTSTUSCNT:16;   /* Slot Status Counter */
-      } B;
-   } FR_SSCR2_16B_tag;
-
-   typedef union {   /* Slot Status Counter Register3 */
-      vuint16_t R;
-      struct {
-         vuint16_t  SLOTSTSTUSCNT:16;   /* Slot Status Counter */
-      } B;
-   } FR_SSCR3_16B_tag;
-
-   typedef union {   /* MTS A Configuration Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  MTE:1;             /* Media Access Test Symbol Transmission Enable */
-         vuint16_t:1;
-         vuint16_t  CYCCNTMSK:6;       /* Cycle Counter Mask */
-         vuint16_t:2;
-         vuint16_t  CYCCNTVAL:6;       /* Cycle Counter Value */
-      } B;
-   } FR_MTSACFR_16B_tag;
-
-   typedef union {   /* MTS B Configuration Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  MTE:1;             /* Media Access Test Symbol Transmission Enable */
-         vuint16_t:1;
-         vuint16_t  CYCCNTMSK:6;       /* Cycle Counter Mask */
-         vuint16_t:2;
-         vuint16_t  CYCCNTVAL:6;       /* Cycle Counter Value */
-      } B;
-   } FR_MTSBCFR_16B_tag;
-
-   typedef union {   /* Receive Shadow Buffer Index Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  WMD:1;             /* Write Mode */
-         vuint16_t:1;
-         vuint16_t  SEL:2;             /* Selector */
-         vuint16_t:5;
-         vuint16_t  RSBIDX:7;          /* Receive Shadow Buffer Index */
-      } B;
-   } FR_RSBIR_16B_tag;
-
-   typedef union {   /* Receive FIFO Watermark and Selection Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  WM:8;              /* Watermark Value */
-         vuint16_t:7;
-         vuint16_t  SEL:1;             /* Select */
-      } B;
-   } FR_RFWMSR_16B_tag;
-
-   typedef union {   /* Receive FIFO Start Index Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:6;
-         vuint16_t  SIDX:10;           /* Start Index */
-      } B;
-   } FR_RF_RFSIR_16B_tag;
-
-   typedef union {   /* Receive FIFO Depth and Size Register */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  FIFO_DEPTH:8;      /* FIFO Depth */
-#else
-         vuint16_t  FIFODEPTH:8;         /* deprecated name - please avoid */
-#endif
-         vuint16_t:1;
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  ENTRY_SIZE:7;      /* Entry Size */
-#else
-         vuint16_t  ENTRYSIZE:7;         /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_RFDSR_16B_tag;
-
-   typedef union {   /* Receive FIFO A Read Index Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:6;
-         vuint16_t  RDIDX:10;          /* Read Index */
-      } B;
-   } FR_RFARIR_16B_tag;
-
-   typedef union {   /* Receive FIFO B Read Index Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:6;
-         vuint16_t  RDIDX:10;          /* Read Index */
-      } B;
-   } FR_RFBRIR_16B_tag;
-
-   typedef union {   /* Receive FIFO Message ID Acceptance Filter Value Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  MIDAFVAL:16;       /* Message ID Acceptance Filter Value */
-      } B;
-   } FR_RFMIDAFVR_16B_tag;
-
-   typedef union {   /* Receive FIFO Message ID Acceptance Filter Mask Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  MIDAFMSK:16;       /* Message ID Acceptance Filter Mask */
-      } B;
-   } FR_RFMIDAFMR_16B_tag;
-
-   typedef union {   /* Receive FIFO Frame ID Rejection Filter Value Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  FIDRFVAL:11;       /* Frame ID Rejection Filter Value */
-      } B;
-   } FR_RFFIDRFVR_16B_tag;
-
-   typedef union {   /* Receive FIFO Frame ID Rejection Filter Mask Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  FIDRFMSK:11;       /* Frame ID Rejection Filter Mask */
-      } B;
-   } FR_RFFIDRFMR_16B_tag;
-
-   typedef union {   /* Receive FIFO Range Filter Configuration Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  WMD:1;             /* Write Mode */
-         vuint16_t  IBD:1;             /* Interval Boundary */
-         vuint16_t  SEL:2;             /* Filter Selector */
-         vuint16_t:1;
-         vuint16_t  SID:11;            /* Slot ID */
-      } B;
-   } FR_RFRFCFR_16B_tag;
-
-   typedef union {   /* Receive FIFO Range Filter Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:4;
-         vuint16_t  F3MD:1;            /* Range Filter 3 Mode */
-         vuint16_t  F2MD:1;            /* Range Filter 2 Mode */
-         vuint16_t  F1MD:1;            /* Range Filter 1 Mode */
-         vuint16_t  F0MD:1;            /* Range Filter 0 Mode */
-         vuint16_t:4;
-         vuint16_t  F3EN:1;            /* Range Filter 3 Enable */
-         vuint16_t  F2EN:1;            /* Range Filter 2 Enable */
-         vuint16_t  F1EN:1;            /* Range Filter 1 Enable */
-         vuint16_t  F0EN:1;            /* Range Filter 0 Enable */
-      } B;
-   } FR_RFRFCTR_16B_tag;
-
-   typedef union {   /* Last Dynamic Transmit Slot Channel A Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  LASTDYNTXSLOTA:11;   /* Last Dynamic Transmission Slot Channel A */
-      } B;
-   } FR_LDTXSLAR_16B_tag;
-
-   typedef union {   /* Last Dynamic Transmit Slot Channel B Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  LASTDYNTXSLOTB:11;   /* Last Dynamic Transmission Slot Channel B */
-      } B;
-   } FR_LDTXSLBR_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 0 */
-      vuint16_t R;
-      struct {
-         vuint16_t  ACTION_POINT_OFFSET:6;   /* gdActionPointOffset - 1 */
-         vuint16_t  STATIC_SLOT_LENGTH:10;   /* gdStaticSlot */
-      } B;
-   } FR_PCR0_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 1 */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  MACRO_AFTER_FIRST_STATIC_SLOT:14;   /* gMacroPerCycle - gdStaticSlot */
-      } B;
-   } FR_PCR1_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 2 */
-      vuint16_t R;
-      struct {
-         vuint16_t  MINISLOT_AFTER_ACTION_POINT:6;   /* gdMinislot - gdMinislotActionPointOffset - 1 */
-         vuint16_t  NUMBER_OF_STATIC_SLOTS:10;   /* gNumberOfStaticSlots */
-      } B;
-   } FR_PCR2_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 3 */
-      vuint16_t R;
-      struct {
-         vuint16_t  WAKEUP_SYMBOL_RX_LOW:6;   /* gdWakeupSymbolRxLow */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MINISLOT_ACTION_POINT_OFFSET_4_0:5;   /* gdMinislotActionPointOffset - 1 */
-#else
-         vuint16_t  MINISLOT_ACTION_POINT_OFFSET:5;     /* deprecated name - please avoid */
-#endif
-         vuint16_t  COLDSTART_ATTEMPTS:5;   /* gColdstartAttempts */
-      } B;
-   } FR_PCR3_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 4 */
-      vuint16_t R;
-      struct {
-         vuint16_t  CAS_RX_LOW_MAX:7;   /* gdCASRxLowMax - 1 */
-         vuint16_t  WAKEUP_SYMBOL_RX_WINDOW:9;   /* gdWakeupSymbolRxWindow */
-      } B;
-   } FR_PCR4_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 5 */
-      vuint16_t R;
-      struct {
-         vuint16_t  TSS_TRANSMITTER:4;   /* gdTSSTransmitter */
-         vuint16_t  WAKEUP_SYMBOL_TX_LOW:6;   /* gdWakeupSymbolTxLow */
-         vuint16_t  WAKEUP_SYMBOL_RX_IDLE:6;   /* gdWakeupSymbolRxIdle */
-      } B;
-   } FR_PCR5_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 6 */
-      vuint16_t R;
-      struct {
-         vuint16_t:1;
-         vuint16_t  SYMBOL_WINDOW_AFTER_ACTION_POINT:8;   /* gdSymbolWindow - gdActionPointOffset - 1 */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MACRO_INITIAL_OFFSET_A:7;   /* pMacroInitialOffset[A] */
-#else
-         vuint16_t  MICRO_INITIAL_OFFSET_A:7;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR6_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 7 */
-      vuint16_t R;
-      struct {
-         vuint16_t  DECODING_CORRECTION_B:9;   /* pDecodingCorrection + pDelayCompensation[B] + 2 */
-         vuint16_t  MICRO_PER_MACRO_NOM_HALF:7;   /* round(pMicroPerMacroNom / 2) */
-      } B;
-   } FR_PCR7_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 8 */
-      vuint16_t R;
-      struct {
-         vuint16_t  MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;   /* gMaxWithoutClockCorrectionFatal */
-         vuint16_t  MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;   /* gMaxWithoutClockCorrectionPassive */
-         vuint16_t  WAKEUP_SYMBOL_TX_IDLE:8;   /* gdWakeupSymbolTxIdle */
-      } B;
-   } FR_PCR8_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 9 */
-      vuint16_t R;
-      struct {
-         vuint16_t  MINISLOT_EXISTS:1;   /* gNumberOfMinislots!=0 */
-         vuint16_t  SYMBOL_WINDOW_EXISTS:1;   /* gdSymbolWindow!=0 */
-         vuint16_t  OFFSET_CORRECTION_OUT:14;   /* pOffsetCorrectionOut */
-      } B;
-   } FR_PCR9_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 10 */
-      vuint16_t R;
-      struct {
-         vuint16_t  SINGLE_SLOT_ENABLED:1;   /* pSingleSlotEnabled */
-         vuint16_t  WAKEUP_CHANNEL:1;   /* pWakeupChannel */
-         vuint16_t  MACRO_PER_CYCLE:14;   /* pMicroPerCycle */
-      } B;
-   } FR_PCR10_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 11 */
-      vuint16_t R;
-      struct {
-         vuint16_t  KEY_SLOT_USED_FOR_STARTUP:1;   /* pKeySlotUsedForStartup */
-         vuint16_t  KEY_SLOT_USED_FOR_SYNC:1;   /* pKeySlotUsedForSync */
-         vuint16_t  OFFSET_CORRECTION_START:14;   /* gOffsetCorrectionStart */
-      } B;
-   } FR_PCR11_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 12 */
-      vuint16_t R;
-      struct {
-         vuint16_t  ALLOW_PASSIVE_TO_ACTIVE:5;   /* pAllowPassiveToActive */
-         vuint16_t  KEY_SLOT_HEADER_CRC:11;   /* header CRC for key slot */
-      } B;
-   } FR_PCR12_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 13 */
-      vuint16_t R;
-      struct {
-         vuint16_t  FIRST_MINISLOT_ACTION_POINT_OFFSET:6;   /* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */
-         vuint16_t  STATIC_SLOT_AFTER_ACTION_POINT:10;   /* gdStaticSlot - gdActionPointOffset - 1 */
-      } B;
-   } FR_PCR13_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 14 */
-      vuint16_t R;
-      struct {
-         vuint16_t  RATE_CORRECTION_OUT:11;   /* pRateCorrectionOut */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  LISTEN_TIMEOUT_20_16:5;   /* pdListenTimeout - 1 */
-#else
-         vuint16_t  LISTEN_TIMEOUT_H:5;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR14_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 15 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  LISTEN_TIMEOUT_15_0:16;   /* pdListenTimeout - 1 */
-#else
-         vuint16_t  LISTEN_TIMEOUT_L:16;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR15_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 16 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MACRO_INITIAL_OFFSET_B:7;   /* pMacroInitialOffset[B] */
-#else
-         vuint16_t  MICRO_INITIAL_OFFSET_B:7;     /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  NOISE_LISTEN_TIMEOUT_24_16:9;   /* (gListenNoise * pdListenTimeout) - 1 */
-#else
-         vuint16_t  NOISE_LISTEN_TIMEOUT_H:9;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR16_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 17 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  NOISE_LISTEN_TIMEOUT_15_0:16;   /* (gListenNoise * pdListenTimeout) - 1 */
-#else
-         vuint16_t  NOISE_LISTEN_TIMEOUT_L:16;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR17_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 18 */
-      vuint16_t R;
-      struct {
-         vuint16_t  WAKEUP_PATTERN:6;   /* pWakeupPattern */
-         vuint16_t  KEY_SLOT_ID:10;    /* pKeySlotId */
-      } B;
-   } FR_PCR18_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 19 */
-      vuint16_t R;
-      struct {
-         vuint16_t  DECODING_CORRECTION_A:9;   /* pDecodingCorrection + pDelayCompensation[A] + 2 */
-         vuint16_t  PAYLOAD_LENGTH_STATIC:7;   /* gPayloadLengthStatic */
-      } B;
-   } FR_PCR19_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 20 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MACRO_INITIAL_OFFSET_B:8;   /* pMicroInitialOffset[B] */
-#else
-         vuint16_t  MICRO_INITIAL_OFFSET_B:8;     /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MACRO_INITIAL_OFFSET_A:8;   /* pMicroInitialOffset[A] */
-#else
-         vuint16_t  MICRO_INITIAL_OFFSET_A:8;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR20_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 21 */
-      vuint16_t R;
-      struct {
-         vuint16_t  EXTERN_RATE_CORRECTION:3;   /* pExternRateCorrection */
-         vuint16_t  LATEST_TX:13;      /* gNumberOfMinislots - pLatestTx */
-      } B;
-   } FR_PCR21_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 22 */
-      vuint16_t R;
-      struct {
-         vuint16_t  R:1;               /* Reserved bit */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  COMP_ACCEPTED_STARRUP_RANGE_A:11;   /* pdAcceptedStartupRange - pDelayCompensationChA */
-#else
-         vuint16_t  COMP_ACCEPTED_STARTUP_RANGE_A:11;     /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MICRO_PER_CYCLE_19_16:4;   /* gMicroPerCycle */
-#else
-         vuint16_t  MICRO_PER_CYCLE_H:4;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR22_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 23 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MICRO_PER_CYCLE_15_0:16;   /* pMicroPerCycle */
-#else
-         vuint16_t  micro_per_cycle_l:16;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR23_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 24 */
-      vuint16_t R;
-      struct {
-         vuint16_t  CLUSTER_DRIFT_DAMPING:5;   /* pClusterDriftDamping */
-         vuint16_t  MAX_PAYLOAD_LENGTH_DYNAMIC:7;   /* pPayloadLengthDynMax */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MICRO_PER_CYCLE_MIN_19_16:4;   /* pMicroPerCycle - pdMaxDrift */
-#else
-         vuint16_t  MICRO_PER_CYCLE_MIN_H:4;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR24_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 25 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MICRO_PER_CYCLE_MIN_15_0:16;   /* pMicroPerCycle - pdMaxDrift */
-#else
-         vuint16_t  MICRO_PER_CYCLE_MIN_L:16;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR25_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 26 */
-      vuint16_t R;
-      struct {
-         vuint16_t  ALLOW_HALT_DUE_TO_CLOCK:1;   /* pAllowHaltDueToClock */
-         vuint16_t  COMP_ACCEPTED_STARTUP_RANGE_B:11;   /* pdAcceptedStartupRange - pDelayCompensationChB */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MICRO_PER_CYCLE_MAX_19_16:4;   /* pMicroPerCycle + pdMaxDrift */
-#else
-         vuint16_t  MICRO_PER_CYCLE_MAX_H:4;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR26_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 27 */
-      vuint16_t R;
-      struct {
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  MICRO_PER_CYCLE_MAX_15_0:16;   /* pMicroPerCycle + pdMaxDrift */
-#else
-         vuint16_t  MICRO_PER_CYCLE_MAX_L:16;     /* deprecated name - please avoid */
-#endif
-      } B;
-   } FR_PCR27_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 28 */
-      vuint16_t R;
-      struct {
-         vuint16_t  DYNAMIC_SLOT_IDLE_PHASE:2;   /* gdDynamicSlotIdlePhase */
-         vuint16_t  MACRO_AFTER_OFFSET_CORRECTION:14;   /* gMacroPerCycle - gOffsetCorrectionStart */
-      } B;
-   } FR_PCR28_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 29 */
-      vuint16_t R;
-      struct {
-         vuint16_t  EXTERN_OFFSET_CORRECTION:3;   /* pExternOffsetCorrection */
-         vuint16_t  MINISLOTS_MAX:13;   /* gNumberOfMinislots - 1 */
-      } B;
-   } FR_PCR29_16B_tag;
-
-   typedef union {   /* Protocol Configuration Register 30 */
-      vuint16_t R;
-      struct {
-         vuint16_t:12;
-         vuint16_t  SYNC_NODE_MAX:4;   /* gSyncNodeMax */
-      } B;
-   } FR_PCR30_16B_tag;
-
-   typedef union {   /* Receive FIFO System Memory Base Address High Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  SMBA_31_16:16;     /* System Memory Base Address */
-      } B;
-   } FR_RFSYMBHADR_16B_tag;
-
-   typedef union {   /* Receive FIFO System Memory Base Address Low Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:4;
-         vuint16_t  SMBA_15_4:12;      /* System Memory Base Address */
-      } B;
-   } FR_RFSYMBLADR_16B_tag;
-
-   typedef union {   /* Receive FIFO Periodic Timer Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:2;
-         vuint16_t  PTD:14;            /* Periodic Timer Duration */
-      } B;
-   } FR_RFPTR_16B_tag;
-
-   typedef union {   /* Receive FIFO Fill Level and Pop Count Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  FLPCB:8;           /* Fill Level and Pop Count Channel B */
-         vuint16_t  FLPCA:8;           /* Fill Level and Pop Count Channel A */
-      } B;
-   } FR_RFFLPCR_16B_tag;
-
-   typedef union {   /* ECC Error Interrupt Flag and Enable Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  LRNE_OF:1;         /* LRAM Non-Corrected Error Overflow Flag */
-         vuint16_t  LRCE_OF:1;         /* LRAM Corrected Error Overflow Flag */
-         vuint16_t  DRNE_OF:1;         /* DRAM Non-Corrected Error Overflow Flag */
-         vuint16_t  DRCE_OF:1;         /* DRAM Corrected Error Overflow Flag */
-         vuint16_t  LRNE_IF:1;         /* LRAM Non-Corrected Error Interrupt Flag */
-         vuint16_t  LRCE_IF:1;         /* LRAM Corrected Error Interrupt Flag */
-         vuint16_t  DRNE_IF:1;         /* DRAM Non-Corrected Error Interrupt Flag */
-         vuint16_t  DRCE_IF:1;         /* DRAM Corrected Error Interrupt Flag */
-         vuint16_t:4;
-         vuint16_t  LRNE_IE:1;         /* LRAM Non-Corrected Error Interrupt Enable */
-         vuint16_t  LRCE_IE:1;         /* LRAM Corrected Error Interrupt Enable */
-         vuint16_t  DRNE_IE:1;         /* DRAM Non-Corrected Error Interrupt Enable */
-         vuint16_t  DRCE_IE:1;         /* DRAM Corrected Error Interrupt Enable */
-      } B;
-   } FR_EEIFER_16B_tag;
-
-   typedef union {   /* ECC Error Report and Injection Control Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  BSY:1;             /* Register Update Busy */
-         vuint16_t:5;
-         vuint16_t  ERS:2;             /* Error Report Select */
-         vuint16_t:3;
-         vuint16_t  ERM:1;             /* Error Report Mode */
-         vuint16_t:2;
-         vuint16_t  EIM:1;             /* Error Injection Mode */
-         vuint16_t  EIE:1;             /* Error Injection Enable */
-      } B;
-   } FR_EERICR_16B_tag;
-
-   typedef union {   /* ECC Error Report Adress Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  MID:1;             /* Memory Identifier */
-         vuint16_t  BANK:3;            /* Memory Bank */
-         vuint16_t  ADDR:12;           /* Memory Address */
-      } B;
-   } FR_EERAR_16B_tag;
-
-   typedef union {   /* ECC Error Report Data Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  DATA:16;           /* Data */
-      } B;
-   } FR_EERDR_16B_tag;
-
-   typedef union {   /* ECC Error Report Code Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:11;
-         vuint16_t  CODE:5;            /* Code */
-      } B;
-   } FR_EERCR_16B_tag;
-
-   typedef union {   /* ECC Error Injection Address Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  MID:1;             /* Memory Identifier */
-         vuint16_t  BANK:3;            /* Memory Bank */
-         vuint16_t  ADDR:12;           /* Memory Address */
-      } B;
-   } FR_EEIAR_16B_tag;
-
-   typedef union {   /* ECC Error Injection Data Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  DATA:16;           /* Data */
-      } B;
-   } FR_EEIDR_16B_tag;
-
-   typedef union {   /* ECC Error Injection Code Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:11;
-         vuint16_t  CODE:5;            /* Code */
-      } B;
-   } FR_EEICR_16B_tag;
-
-
-   /* Register layout for all registers MBCCSR... */
-
-   typedef union {   /* Message Buffer Configuration Control Status Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:1;
-         vuint16_t  MCM:1;             /* Message Buffer Commit Mode */
-         vuint16_t  MBT:1;             /* Message Buffer Type */
-         vuint16_t  MTD:1;             /* Message Buffer Transfer Direction */
-         vuint16_t  CMT:1;             /* Commit for Transmission */
-         vuint16_t  EDT:1;             /* Enable/Disable Trigger */
-         vuint16_t  LCKT:1;            /* Lock/Unlock Trigger */
-         vuint16_t  MBIE:1;            /* Message Buffer Interrupt Enable */
-         vuint16_t:3;
-         vuint16_t  DUP:1;             /* Data Updated */
-         vuint16_t  DVAL:1;            /* DataValid */
-         vuint16_t  EDS:1;             /* Enable/Disable Status */
-         vuint16_t  LCKS:1;            /* LockStatus */
-         vuint16_t  MBIF:1;            /* Message Buffer Interrupt Flag */
-      } B;
-   } FR_MBCCSR_16B_tag;
-
-
-   /* Register layout for all registers MBCCFR... */
-
-   typedef union {   /* Message Buffer Cycle Counter Filter Register */
-      vuint16_t R;
-      struct {
-         vuint16_t  MTM:1;             /* Message Buffer Transmission Mode */
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CHA:1;             /* Channel Assignment */
-#else
-         vuint16_t  CHNLA:1;             /* deprecated name - please avoid */
-#endif
-#ifndef USE_FIELD_ALIASES_FR
-         vuint16_t  CHB:1;             /* Channel Assignment */
-#else
-         vuint16_t  CHNLB:1;             /* deprecated name - please avoid */
-#endif
-         vuint16_t  CCFE:1;            /* Cycle Counter Filtering Enable */
-         vuint16_t  CCFMSK:6;          /* Cycle Counter Filtering Mask */
-         vuint16_t  CCFVAL:6;          /* Cycle Counter Filtering Value */
-      } B;
-   } FR_MBCCFR_16B_tag;
-
-
-   /* Register layout for all registers MBFIDR... */
-
-   typedef union {   /* Message Buffer Frame ID Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:5;
-         vuint16_t  FID:11;            /* Frame ID */
-      } B;
-   } FR_MBFIDR_16B_tag;
-
-
-   /* Register layout for all registers MBIDXR... */
-
-   typedef union {   /* Message Buffer Index Register */
-      vuint16_t R;
-      struct {
-         vuint16_t:9;
-         vuint16_t  MBIDX:7;           /* Message Buffer Index */
-      } B;
-   } FR_MBIDXR_16B_tag;
-
-
-   /* Register layout for generated register(s) NMVR... */
-
-   typedef union {   /*  */
-      vuint16_t R;
-   } FR_NMVR_16B_tag;
-
-
-
-
-   /* Register layout for generated register(s) SSCR... */
-
-   typedef union {   /*  */
-      vuint16_t R;
-   } FR_SSCR_16B_tag;
-
-
-   typedef struct FR_MB_struct_tag {
-
-                 /* Message Buffer Configuration Control Status Register */
-      FR_MBCCSR_16B_tag MBCCSR;           /* relative offset: 0x0000 */
-                         /* Message Buffer Cycle Counter Filter Register */
-      FR_MBCCFR_16B_tag MBCCFR;           /* relative offset: 0x0002 */
-                                     /* Message Buffer Frame ID Register */
-      FR_MBFIDR_16B_tag MBFIDR;           /* relative offset: 0x0004 */
-                                        /* Message Buffer Index Register */
-      FR_MBIDXR_16B_tag MBIDXR;           /* relative offset: 0x0006 */
-
-   } FR_MB_tag;
-
-
-   typedef struct FR_struct_tag { /* start of FR_tag */
-                                                /* Module Version Number */
-      FR_MVR_16B_tag MVR;                  /* offset: 0x0000 size: 16 bit */
-                                        /* Module Configuration Register */
-      FR_MCR_16B_tag MCR;                  /* offset: 0x0002 size: 16 bit */
-      union {
-         FR_SYMBADHR_16B_tag SYSBADHR;     /* deprecated - please avoid */
-
-                                      /* SYSTEM MEMORY BASE ADD HIGH REG */
-         FR_SYMBADHR_16B_tag SYMBADHR;     /* offset: 0x0004 size: 16 bit */
-
-      };
-      union {
-         FR_SYMBADLR_16B_tag SYSBADLR;     /* deprecated - please avoid */
-
-                                      /* SYSTEM MEMORY BASE ADD LOW  REG */
-         FR_SYMBADLR_16B_tag SYMBADLR;     /* offset: 0x0006 size: 16 bit */
-
-      };
-                                       /* STROBE SIGNAL CONTROL REGISTER */
-      FR_STBSCR_16B_tag STBSCR;            /* offset: 0x0008 size: 16 bit */
-      int8_t FR_reserved_000A[2];
-                                    /* MESSAGE BUFFER DATA SIZE REGISTER */
-      FR_MBDSR_16B_tag MBDSR;              /* offset: 0x000C size: 16 bit */
-                             /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
-      FR_MBSSUTR_16B_tag MBSSUTR;          /* offset: 0x000E size: 16 bit */
-      union {
-                                              /* PE DRAM ACCESS REGISTER */
-         FR_PEDRAR_16B_tag PEDRAR;         /* offset: 0x0010 size: 16 bit */
-
-         FR_PEDRAR_16B_tag PADR;           /* deprecated - please avoid */
-
-      };
-      union {
-                                                /* PE DRAM DATA REGISTER */
-         FR_PEDRDR_16B_tag PEDRDR;         /* offset: 0x0012 size: 16 bit */
-
-         FR_PEDRDR_16B_tag PDAR;           /* deprecated - please avoid */
-
-      };
-                                       /* PROTOCOL OPERATION CONTROL REG */
-      FR_POCR_16B_tag POCR;                /* offset: 0x0014 size: 16 bit */
-                                   /* GLOBAL INTERRUPT FLAG & ENABLE REG */
-      FR_GIFER_16B_tag GIFER;              /* offset: 0x0016 size: 16 bit */
-                                   /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
-      FR_PIFR0_16B_tag PIFR0;              /* offset: 0x0018 size: 16 bit */
-                                   /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
-      FR_PIFR1_16B_tag PIFR1;              /* offset: 0x001A size: 16 bit */
-                                 /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
-      FR_PIER0_16B_tag PIER0;              /* offset: 0x001C size: 16 bit */
-                                 /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
-      FR_PIER1_16B_tag PIER1;              /* offset: 0x001E size: 16 bit */
-                                              /* CHI ERROR FLAG REGISTER */
-      FR_CHIERFR_16B_tag CHIERFR;          /* offset: 0x0020 size: 16 bit */
-                             /* Message Buffer Interrupt Vector Register */
-      FR_MBIVEC_16B_tag MBIVEC;            /* offset: 0x0022 size: 16 bit */
-                              /* Channel A Status Error Counter Register */
-      FR_CASERCR_16B_tag CASERCR;          /* offset: 0x0024 size: 16 bit */
-                              /* Channel B Status Error Counter Register */
-      FR_CBSERCR_16B_tag CBSERCR;          /* offset: 0x0026 size: 16 bit */
-                                           /* Protocol Status Register 0 */
-      FR_PSR0_16B_tag PSR0;                /* offset: 0x0028 size: 16 bit */
-                                           /* Protocol Status Register 1 */
-      FR_PSR1_16B_tag PSR1;                /* offset: 0x002A size: 16 bit */
-                                           /* Protocol Status Register 2 */
-      FR_PSR2_16B_tag PSR2;                /* offset: 0x002C size: 16 bit */
-                                           /* Protocol Status Register 3 */
-      FR_PSR3_16B_tag PSR3;                /* offset: 0x002E size: 16 bit */
-                                           /* Macrotick Counter Register */
-      FR_MTCTR_16B_tag MTCTR;              /* offset: 0x0030 size: 16 bit */
-                                               /* Cycle Counter Register */
-      FR_CYCTR_16B_tag CYCTR;              /* offset: 0x0032 size: 16 bit */
-                                      /* Slot Counter Channel A Register */
-      FR_SLTCTAR_16B_tag SLTCTAR;          /* offset: 0x0034 size: 16 bit */
-                                      /* Slot Counter Channel B Register */
-      FR_SLTCTBR_16B_tag SLTCTBR;          /* offset: 0x0036 size: 16 bit */
-                                       /* Rate Correction Value Register */
-      FR_RTCORVR_16B_tag RTCORVR;          /* offset: 0x0038 size: 16 bit */
-                                     /* Offset Correction Value Register */
-      FR_OFCORVR_16B_tag OFCORVR;          /* offset: 0x003A size: 16 bit */
-      union {
-         FR_CIFR_16B_tag CIFRR;            /* deprecated - please avoid */
-
-                                     /* Combined Interrupt Flag Register */
-         FR_CIFR_16B_tag CIFR;             /* offset: 0x003C size: 16 bit */
-
-      };
-                               /* System Memory Access Time-Out Register */
-      FR_SYMATOR_16B_tag SYMATOR;          /* offset: 0x003E size: 16 bit */
-                                          /* Sync Frame Counter Register */
-      FR_SFCNTR_16B_tag SFCNTR;            /* offset: 0x0040 size: 16 bit */
-                                     /* Sync Frame Table Offset Register */
-      FR_SFTOR_16B_tag SFTOR;              /* offset: 0x0042 size: 16 bit */
-             /* Sync Frame Table Configuration, Control, Status Register */
-      FR_SFTCCSR_16B_tag SFTCCSR;          /* offset: 0x0044 size: 16 bit */
-                                       /* Sync Frame ID Rejection Filter */
-      FR_SFIDRFR_16B_tag SFIDRFR;          /* offset: 0x0046 size: 16 bit */
-                       /* Sync Frame ID Acceptance Filter Value Register */
-      FR_SFIDAFVR_16B_tag SFIDAFVR;        /* offset: 0x0048 size: 16 bit */
-                        /* Sync Frame ID Acceptance Filter Mask Register */
-      FR_SFIDAFMR_16B_tag SFIDAFMR;        /* offset: 0x004A size: 16 bit */
-      union {
-         FR_NMVR_16B_tag NMVR[6];          /* offset: 0x004C  (0x0002 x 6) */
-
-         struct {
-                                  /* Network Management Vector Register0 */
-            FR_NMVR0_16B_tag NMVR0;        /* offset: 0x004C size: 16 bit */
-                                  /* Network Management Vector Register1 */
-            FR_NMVR1_16B_tag NMVR1;        /* offset: 0x004E size: 16 bit */
-                                  /* Network Management Vector Register2 */
-            FR_NMVR2_16B_tag NMVR2;        /* offset: 0x0050 size: 16 bit */
-                                  /* Network Management Vector Register3 */
-            FR_NMVR3_16B_tag NMVR3;        /* offset: 0x0052 size: 16 bit */
-                                  /* Network Management Vector Register4 */
-            FR_NMVR4_16B_tag NMVR4;        /* offset: 0x0054 size: 16 bit */
-                                  /* Network Management Vector Register5 */
-            FR_NMVR5_16B_tag NMVR5;        /* offset: 0x0056 size: 16 bit */
-         };
-
-      };
-                            /* Network Management Vector Length Register */
-      FR_NMVLR_16B_tag NMVLR;              /* offset: 0x0058 size: 16 bit */
-                             /* Timer Configuration and Control Register */
-      FR_TICCR_16B_tag TICCR;              /* offset: 0x005A size: 16 bit */
-                                           /* Timer 1 Cycle Set Register */
-      FR_TI1CYSR_16B_tag TI1CYSR;          /* offset: 0x005C size: 16 bit */
-      union {
-                                    /* Timer 1 Macrotick Offset Register */
-         FR_TI1MTOR_16B_tag TI1MTOR;       /* offset: 0x005E size: 16 bit */
-
-         FR_TI1MTOR_16B_tag T1MTOR;        /* deprecated - please avoid */
-
-      };
-                                     /* Timer 2 Configuration Register 0 */
-      FR_TI2CR0_16B_tag TI2CR0;            /* offset: 0x0060 size: 16 bit */
-                                     /* Timer 2 Configuration Register 1 */
-      FR_TI2CR1_16B_tag TI2CR1;            /* offset: 0x0062 size: 16 bit */
-                                       /* Slot Status Selection Register */
-      FR_SSSR_16B_tag SSSR;                /* offset: 0x0064 size: 16 bit */
-                               /* Slot Status Counter Condition Register */
-      FR_SSCCR_16B_tag SSCCR;              /* offset: 0x0066 size: 16 bit */
-      union {
-         FR_SSR_16B_tag SSR[8];            /* offset: 0x0068  (0x0002 x 8) */
-
-         struct {
-                                                /* Slot Status Register0 */
-            FR_SSR_16B_tag SSR0;          /* offset: 0x0068 size: 16 bit */
-                                                /* Slot Status Register1 */
-            FR_SSR_16B_tag SSR1;          /* offset: 0x006A size: 16 bit */
-                                                /* Slot Status Register2 */
-            FR_SSR_16B_tag SSR2;          /* offset: 0x006C size: 16 bit */
-                                                /* Slot Status Register3 */
-            FR_SSR_16B_tag SSR3;          /* offset: 0x006E size: 16 bit */
-                                                /* Slot Status Register4 */
-            FR_SSR_16B_tag SSR4;          /* offset: 0x0070 size: 16 bit */
-                                                /* Slot Status Register5 */
-            FR_SSR_16B_tag SSR5;          /* offset: 0x0072 size: 16 bit */
-                                                /* Slot Status Register6 */
-            FR_SSR_16B_tag SSR6;          /* offset: 0x0074 size: 16 bit */
-                                                /* Slot Status Register7 */
-            FR_SSR_16B_tag SSR7;          /* offset: 0x0076 size: 16 bit */
-         };
-
-      };
-      union {
-         FR_SSCR_16B_tag SSCR[4];          /* offset: 0x0078  (0x0002 x 4) */
-
-         struct {
-                                        /* Slot Status Counter Register0 */
-            FR_SSCR0_16B_tag SSCR0;        /* offset: 0x0078 size: 16 bit */
-                                        /* Slot Status Counter Register1 */
-            FR_SSCR1_16B_tag SSCR1;        /* offset: 0x007A size: 16 bit */
-                                        /* Slot Status Counter Register2 */
-            FR_SSCR2_16B_tag SSCR2;        /* offset: 0x007C size: 16 bit */
-                                        /* Slot Status Counter Register3 */
-            FR_SSCR3_16B_tag SSCR3;        /* offset: 0x007E size: 16 bit */
-         };
-
-      };
-                                         /* MTS A Configuration Register */
-      FR_MTSACFR_16B_tag MTSACFR;          /* offset: 0x0080 size: 16 bit */
-                                         /* MTS B Configuration Register */
-      FR_MTSBCFR_16B_tag MTSBCFR;          /* offset: 0x0082 size: 16 bit */
-                                 /* Receive Shadow Buffer Index Register */
-      FR_RSBIR_16B_tag RSBIR;              /* offset: 0x0084 size: 16 bit */
-      union {
-                        /* Receive FIFO Watermark and Selection Register */
-         FR_RFWMSR_16B_tag RFWMSR;         /* offset: 0x0086 size: 16 bit */
-
-         FR_RFWMSR_16B_tag RFSR;           /* deprecated - please avoid */
-
-      };
-      union {
-         FR_RF_RFSIR_16B_tag RFSIR;        /* deprecated - please avoid */
-
-                                    /* Receive FIFO Start Index Register */
-         FR_RF_RFSIR_16B_tag RF_RFSIR;     /* offset: 0x0088 size: 16 bit */
-
-      };
-                                 /* Receive FIFO Depth and Size Register */
-      FR_RFDSR_16B_tag RFDSR;              /* offset: 0x008A size: 16 bit */
-                                   /* Receive FIFO A Read Index Register */
-      FR_RFARIR_16B_tag RFARIR;            /* offset: 0x008C size: 16 bit */
-                                   /* Receive FIFO B Read Index Register */
-      FR_RFBRIR_16B_tag RFBRIR;            /* offset: 0x008E size: 16 bit */
-             /* Receive FIFO Message ID Acceptance Filter Value Register */
-      FR_RFMIDAFVR_16B_tag RFMIDAFVR;      /* offset: 0x0090 size: 16 bit */
-      union {
-              /* Receive FIFO Message ID Acceptance Filter Mask Register */
-         FR_RFMIDAFMR_16B_tag RFMIDAFMR;   /* offset: 0x0092 size: 16 bit */
-
-         FR_RFMIDAFMR_16B_tag RFMIAFMR;    /* deprecated - please avoid */
-
-      };
-                /* Receive FIFO Frame ID Rejection Filter Value Register */
-      FR_RFFIDRFVR_16B_tag RFFIDRFVR;      /* offset: 0x0094 size: 16 bit */
-                 /* Receive FIFO Frame ID Rejection Filter Mask Register */
-      FR_RFFIDRFMR_16B_tag RFFIDRFMR;      /* offset: 0x0096 size: 16 bit */
-                     /* Receive FIFO Range Filter Configuration Register */
-      FR_RFRFCFR_16B_tag RFRFCFR;          /* offset: 0x0098 size: 16 bit */
-                           /* Receive FIFO Range Filter Control Register */
-      FR_RFRFCTR_16B_tag RFRFCTR;          /* offset: 0x009A size: 16 bit */
-                        /* Last Dynamic Transmit Slot Channel A Register */
-      FR_LDTXSLAR_16B_tag LDTXSLAR;        /* offset: 0x009C size: 16 bit */
-                        /* Last Dynamic Transmit Slot Channel B Register */
-      FR_LDTXSLBR_16B_tag LDTXSLBR;        /* offset: 0x009E size: 16 bit */
-                                    /* Protocol Configuration Register 0 */
-      FR_PCR0_16B_tag PCR0;                /* offset: 0x00A0 size: 16 bit */
-                                    /* Protocol Configuration Register 1 */
-      FR_PCR1_16B_tag PCR1;                /* offset: 0x00A2 size: 16 bit */
-                                    /* Protocol Configuration Register 2 */
-      FR_PCR2_16B_tag PCR2;                /* offset: 0x00A4 size: 16 bit */
-                                    /* Protocol Configuration Register 3 */
-      FR_PCR3_16B_tag PCR3;                /* offset: 0x00A6 size: 16 bit */
-                                    /* Protocol Configuration Register 4 */
-      FR_PCR4_16B_tag PCR4;                /* offset: 0x00A8 size: 16 bit */
-                                    /* Protocol Configuration Register 5 */
-      FR_PCR5_16B_tag PCR5;                /* offset: 0x00AA size: 16 bit */
-                                    /* Protocol Configuration Register 6 */
-      FR_PCR6_16B_tag PCR6;                /* offset: 0x00AC size: 16 bit */
-                                    /* Protocol Configuration Register 7 */
-      FR_PCR7_16B_tag PCR7;                /* offset: 0x00AE size: 16 bit */
-                                    /* Protocol Configuration Register 8 */
-      FR_PCR8_16B_tag PCR8;                /* offset: 0x00B0 size: 16 bit */
-                                    /* Protocol Configuration Register 9 */
-      FR_PCR9_16B_tag PCR9;                /* offset: 0x00B2 size: 16 bit */
-                                   /* Protocol Configuration Register 10 */
-      FR_PCR10_16B_tag PCR10;              /* offset: 0x00B4 size: 16 bit */
-                                   /* Protocol Configuration Register 11 */
-      FR_PCR11_16B_tag PCR11;              /* offset: 0x00B6 size: 16 bit */
-                                   /* Protocol Configuration Register 12 */
-      FR_PCR12_16B_tag PCR12;              /* offset: 0x00B8 size: 16 bit */
-                                   /* Protocol Configuration Register 13 */
-      FR_PCR13_16B_tag PCR13;              /* offset: 0x00BA size: 16 bit */
-                                   /* Protocol Configuration Register 14 */
-      FR_PCR14_16B_tag PCR14;              /* offset: 0x00BC size: 16 bit */
-                                   /* Protocol Configuration Register 15 */
-      FR_PCR15_16B_tag PCR15;              /* offset: 0x00BE size: 16 bit */
-                                   /* Protocol Configuration Register 16 */
-      FR_PCR16_16B_tag PCR16;              /* offset: 0x00C0 size: 16 bit */
-                                   /* Protocol Configuration Register 17 */
-      FR_PCR17_16B_tag PCR17;              /* offset: 0x00C2 size: 16 bit */
-                                   /* Protocol Configuration Register 18 */
-      FR_PCR18_16B_tag PCR18;              /* offset: 0x00C4 size: 16 bit */
-                                   /* Protocol Configuration Register 19 */
-      FR_PCR19_16B_tag PCR19;              /* offset: 0x00C6 size: 16 bit */
-                                   /* Protocol Configuration Register 20 */
-      FR_PCR20_16B_tag PCR20;              /* offset: 0x00C8 size: 16 bit */
-                                   /* Protocol Configuration Register 21 */
-      FR_PCR21_16B_tag PCR21;              /* offset: 0x00CA size: 16 bit */
-                                   /* Protocol Configuration Register 22 */
-      FR_PCR22_16B_tag PCR22;              /* offset: 0x00CC size: 16 bit */
-                                   /* Protocol Configuration Register 23 */
-      FR_PCR23_16B_tag PCR23;              /* offset: 0x00CE size: 16 bit */
-                                   /* Protocol Configuration Register 24 */
-      FR_PCR24_16B_tag PCR24;              /* offset: 0x00D0 size: 16 bit */
-                                   /* Protocol Configuration Register 25 */
-      FR_PCR25_16B_tag PCR25;              /* offset: 0x00D2 size: 16 bit */
-                                   /* Protocol Configuration Register 26 */
-      FR_PCR26_16B_tag PCR26;              /* offset: 0x00D4 size: 16 bit */
-                                   /* Protocol Configuration Register 27 */
-      FR_PCR27_16B_tag PCR27;              /* offset: 0x00D6 size: 16 bit */
-                                   /* Protocol Configuration Register 28 */
-      FR_PCR28_16B_tag PCR28;              /* offset: 0x00D8 size: 16 bit */
-                                   /* Protocol Configuration Register 29 */
-      FR_PCR29_16B_tag PCR29;              /* offset: 0x00DA size: 16 bit */
-                                   /* Protocol Configuration Register 30 */
-      FR_PCR30_16B_tag PCR30;              /* offset: 0x00DC size: 16 bit */
-      int8_t FR_reserved_00DE[10];
-                /* Receive FIFO System Memory Base Address High Register */
-      FR_RFSYMBHADR_16B_tag RFSYMBHADR;    /* offset: 0x00E8 size: 16 bit */
-                 /* Receive FIFO System Memory Base Address Low Register */
-      FR_RFSYMBLADR_16B_tag RFSYMBLADR;    /* offset: 0x00EA size: 16 bit */
-                                 /* Receive FIFO Periodic Timer Register */
-      FR_RFPTR_16B_tag RFPTR;              /* offset: 0x00EC size: 16 bit */
-                       /* Receive FIFO Fill Level and Pop Count Register */
-      FR_RFFLPCR_16B_tag RFFLPCR;          /* offset: 0x00EE size: 16 bit */
-                         /* ECC Error Interrupt Flag and Enable Register */
-      FR_EEIFER_16B_tag EEIFER;            /* offset: 0x00F0 size: 16 bit */
-                      /* ECC Error Report and Injection Control Register */
-      FR_EERICR_16B_tag EERICR;            /* offset: 0x00F2 size: 16 bit */
-                                     /* ECC Error Report Adress Register */
-      FR_EERAR_16B_tag EERAR;              /* offset: 0x00F4 size: 16 bit */
-                                       /* ECC Error Report Data Register */
-      FR_EERDR_16B_tag EERDR;              /* offset: 0x00F6 size: 16 bit */
-                                       /* ECC Error Report Code Register */
-      FR_EERCR_16B_tag EERCR;              /* offset: 0x00F8 size: 16 bit */
-                                 /* ECC Error Injection Address Register */
-      FR_EEIAR_16B_tag EEIAR;              /* offset: 0x00FA size: 16 bit */
-                                    /* ECC Error Injection Data Register */
-      FR_EEIDR_16B_tag EEIDR;              /* offset: 0x00FC size: 16 bit */
-                                    /* ECC Error Injection Code Register */
-      FR_EEICR_16B_tag EEICR;              /* offset: 0x00FE size: 16 bit */
-      union {
-                                                     /*  Register set MB */
-         FR_MB_tag MB[64];                 /* offset: 0x0100  (0x0008 x 64) */
-
-         struct {
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR0;     /* offset: 0x0100 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR0;     /* offset: 0x0102 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR0;     /* offset: 0x0104 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR0;     /* offset: 0x0106 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR1;     /* offset: 0x0108 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR1;     /* offset: 0x010A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR1;     /* offset: 0x010C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR1;     /* offset: 0x010E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR2;     /* offset: 0x0110 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR2;     /* offset: 0x0112 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR2;     /* offset: 0x0114 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR2;     /* offset: 0x0116 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR3;     /* offset: 0x0118 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR3;     /* offset: 0x011A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR3;     /* offset: 0x011C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR3;     /* offset: 0x011E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR4;     /* offset: 0x0120 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR4;     /* offset: 0x0122 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR4;     /* offset: 0x0124 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR4;     /* offset: 0x0126 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR5;     /* offset: 0x0128 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR5;     /* offset: 0x012A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR5;     /* offset: 0x012C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR5;     /* offset: 0x012E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR6;     /* offset: 0x0130 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR6;     /* offset: 0x0132 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR6;     /* offset: 0x0134 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR6;     /* offset: 0x0136 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR7;     /* offset: 0x0138 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR7;     /* offset: 0x013A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR7;     /* offset: 0x013C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR7;     /* offset: 0x013E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR8;     /* offset: 0x0140 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR8;     /* offset: 0x0142 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR8;     /* offset: 0x0144 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR8;     /* offset: 0x0146 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR9;     /* offset: 0x0148 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR9;     /* offset: 0x014A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR9;     /* offset: 0x014C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR9;     /* offset: 0x014E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR10;    /* offset: 0x0150 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR10;    /* offset: 0x0152 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR10;    /* offset: 0x0154 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR10;    /* offset: 0x0156 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR11;    /* offset: 0x0158 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR11;    /* offset: 0x015A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR11;    /* offset: 0x015C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR11;    /* offset: 0x015E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR12;    /* offset: 0x0160 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR12;    /* offset: 0x0162 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR12;    /* offset: 0x0164 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR12;    /* offset: 0x0166 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR13;    /* offset: 0x0168 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR13;    /* offset: 0x016A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR13;    /* offset: 0x016C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR13;    /* offset: 0x016E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR14;    /* offset: 0x0170 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR14;    /* offset: 0x0172 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR14;    /* offset: 0x0174 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR14;    /* offset: 0x0176 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR15;    /* offset: 0x0178 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR15;    /* offset: 0x017A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR15;    /* offset: 0x017C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR15;    /* offset: 0x017E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR16;    /* offset: 0x0180 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR16;    /* offset: 0x0182 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR16;    /* offset: 0x0184 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR16;    /* offset: 0x0186 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR17;    /* offset: 0x0188 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR17;    /* offset: 0x018A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR17;    /* offset: 0x018C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR17;    /* offset: 0x018E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR18;    /* offset: 0x0190 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR18;    /* offset: 0x0192 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR18;    /* offset: 0x0194 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR18;    /* offset: 0x0196 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR19;    /* offset: 0x0198 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR19;    /* offset: 0x019A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR19;    /* offset: 0x019C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR19;    /* offset: 0x019E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR20;    /* offset: 0x01A0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR20;    /* offset: 0x01A2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR20;    /* offset: 0x01A4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR20;    /* offset: 0x01A6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR21;    /* offset: 0x01A8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR21;    /* offset: 0x01AA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR21;    /* offset: 0x01AC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR21;    /* offset: 0x01AE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR22;    /* offset: 0x01B0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR22;    /* offset: 0x01B2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR22;    /* offset: 0x01B4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR22;    /* offset: 0x01B6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR23;    /* offset: 0x01B8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR23;    /* offset: 0x01BA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR23;    /* offset: 0x01BC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR23;    /* offset: 0x01BE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR24;    /* offset: 0x01C0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR24;    /* offset: 0x01C2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR24;    /* offset: 0x01C4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR24;    /* offset: 0x01C6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR25;    /* offset: 0x01C8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR25;    /* offset: 0x01CA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR25;    /* offset: 0x01CC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR25;    /* offset: 0x01CE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR26;    /* offset: 0x01D0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR26;    /* offset: 0x01D2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR26;    /* offset: 0x01D4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR26;    /* offset: 0x01D6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR27;    /* offset: 0x01D8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR27;    /* offset: 0x01DA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR27;    /* offset: 0x01DC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR27;    /* offset: 0x01DE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR28;    /* offset: 0x01E0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR28;    /* offset: 0x01E2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR28;    /* offset: 0x01E4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR28;    /* offset: 0x01E6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR29;    /* offset: 0x01E8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR29;    /* offset: 0x01EA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR29;    /* offset: 0x01EC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR29;    /* offset: 0x01EE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR30;    /* offset: 0x01F0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR30;    /* offset: 0x01F2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR30;    /* offset: 0x01F4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR30;    /* offset: 0x01F6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR31;    /* offset: 0x01F8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR31;    /* offset: 0x01FA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR31;    /* offset: 0x01FC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR31;    /* offset: 0x01FE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR32;    /* offset: 0x0200 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR32;    /* offset: 0x0202 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR32;    /* offset: 0x0204 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR32;    /* offset: 0x0206 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR33;    /* offset: 0x0208 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR33;    /* offset: 0x020A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR33;    /* offset: 0x020C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR33;    /* offset: 0x020E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR34;    /* offset: 0x0210 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR34;    /* offset: 0x0212 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR34;    /* offset: 0x0214 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR34;    /* offset: 0x0216 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR35;    /* offset: 0x0218 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR35;    /* offset: 0x021A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR35;    /* offset: 0x021C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR35;    /* offset: 0x021E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR36;    /* offset: 0x0220 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR36;    /* offset: 0x0222 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR36;    /* offset: 0x0224 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR36;    /* offset: 0x0226 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR37;    /* offset: 0x0228 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR37;    /* offset: 0x022A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR37;    /* offset: 0x022C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR37;    /* offset: 0x022E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR38;    /* offset: 0x0230 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR38;    /* offset: 0x0232 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR38;    /* offset: 0x0234 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR38;    /* offset: 0x0236 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR39;    /* offset: 0x0238 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR39;    /* offset: 0x023A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR39;    /* offset: 0x023C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR39;    /* offset: 0x023E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR40;    /* offset: 0x0240 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR40;    /* offset: 0x0242 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR40;    /* offset: 0x0244 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR40;    /* offset: 0x0246 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR41;    /* offset: 0x0248 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR41;    /* offset: 0x024A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR41;    /* offset: 0x024C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR41;    /* offset: 0x024E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR42;    /* offset: 0x0250 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR42;    /* offset: 0x0252 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR42;    /* offset: 0x0254 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR42;    /* offset: 0x0256 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR43;    /* offset: 0x0258 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR43;    /* offset: 0x025A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR43;    /* offset: 0x025C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR43;    /* offset: 0x025E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR44;    /* offset: 0x0260 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR44;    /* offset: 0x0262 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR44;    /* offset: 0x0264 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR44;    /* offset: 0x0266 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR45;    /* offset: 0x0268 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR45;    /* offset: 0x026A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR45;    /* offset: 0x026C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR45;    /* offset: 0x026E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR46;    /* offset: 0x0270 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR46;    /* offset: 0x0272 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR46;    /* offset: 0x0274 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR46;    /* offset: 0x0276 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR47;    /* offset: 0x0278 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR47;    /* offset: 0x027A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR47;    /* offset: 0x027C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR47;    /* offset: 0x027E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR48;    /* offset: 0x0280 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR48;    /* offset: 0x0282 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR48;    /* offset: 0x0284 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR48;    /* offset: 0x0286 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR49;    /* offset: 0x0288 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR49;    /* offset: 0x028A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR49;    /* offset: 0x028C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR49;    /* offset: 0x028E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR50;    /* offset: 0x0290 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR50;    /* offset: 0x0292 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR50;    /* offset: 0x0294 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR50;    /* offset: 0x0296 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR51;    /* offset: 0x0298 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR51;    /* offset: 0x029A size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR51;    /* offset: 0x029C size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR51;    /* offset: 0x029E size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR52;    /* offset: 0x02A0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR52;    /* offset: 0x02A2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR52;    /* offset: 0x02A4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR52;    /* offset: 0x02A6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR53;    /* offset: 0x02A8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR53;    /* offset: 0x02AA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR53;    /* offset: 0x02AC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR53;    /* offset: 0x02AE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR54;    /* offset: 0x02B0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR54;    /* offset: 0x02B2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR54;    /* offset: 0x02B4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR54;    /* offset: 0x02B6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR55;    /* offset: 0x02B8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR55;    /* offset: 0x02BA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR55;    /* offset: 0x02BC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR55;    /* offset: 0x02BE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR56;    /* offset: 0x02C0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR56;    /* offset: 0x02C2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR56;    /* offset: 0x02C4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR56;    /* offset: 0x02C6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR57;    /* offset: 0x02C8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR57;    /* offset: 0x02CA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR57;    /* offset: 0x02CC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR57;    /* offset: 0x02CE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR58;    /* offset: 0x02D0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR58;    /* offset: 0x02D2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR58;    /* offset: 0x02D4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR58;    /* offset: 0x02D6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR59;    /* offset: 0x02D8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR59;    /* offset: 0x02DA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR59;    /* offset: 0x02DC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR59;    /* offset: 0x02DE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR60;    /* offset: 0x02E0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR60;    /* offset: 0x02E2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR60;    /* offset: 0x02E4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR60;    /* offset: 0x02E6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR61;    /* offset: 0x02E8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR61;    /* offset: 0x02EA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR61;    /* offset: 0x02EC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR61;    /* offset: 0x02EE size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR62;    /* offset: 0x02F0 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR62;    /* offset: 0x02F2 size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR62;    /* offset: 0x02F4 size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR62;    /* offset: 0x02F6 size: 16 bit */
-                 /* Message Buffer Configuration Control Status Register */
-            FR_MBCCSR_16B_tag MBCCSR63;    /* offset: 0x02F8 size: 16 bit */
-                         /* Message Buffer Cycle Counter Filter Register */
-            FR_MBCCFR_16B_tag MBCCFR63;    /* offset: 0x02FA size: 16 bit */
-                                     /* Message Buffer Frame ID Register */
-            FR_MBFIDR_16B_tag MBFIDR63;    /* offset: 0x02FC size: 16 bit */
-                                        /* Message Buffer Index Register */
-            FR_MBIDXR_16B_tag MBIDXR63;    /* offset: 0x02FE size: 16 bit */
-         };
-
-      };
-   } FR_tag;
-
-
-#define FR    (*(volatile FR_tag *) 0xFFFE0000UL)
-
-
-
-
-
-#ifdef __MWERKS__
-#pragma pop
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _leopard_H_*/
-/* End of file */
-
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h b/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h
deleted file mode 100644
index 4c6105e15..000000000
--- a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h
+++ /dev/null
@@ -1,448 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    DSPI_v1/spc5_dspi.h
- * @brief   SPC5xx DSPI header file.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPC5_DSPI_H_
-#define _SPC5_DSPI_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    MCR register definitions
- * @{
- */
-#define SPC5_MCR_MSTR                       (1U << 31)
-#define SPC5_MCR_CONT_SCKE                  (1U << 30)
-#define SPC5_MCR_DCONF_MASK                 (3U << 28)
-#define SPC5_MCR_FRZ                        (1U << 27)
-#define SPC5_MCR_MTFE                       (1U << 26)
-#define SPC5_MCR_PCSSE                      (1U << 25)
-#define SPC5_MCR_ROOE                       (1U << 24)
-#define SPC5_MCR_PCSIS7                     (1U << 23)
-#define SPC5_MCR_PCSIS6                     (1U << 22)
-#define SPC5_MCR_PCSIS5                     (1U << 21)
-#define SPC5_MCR_PCSIS4                     (1U << 20)
-#define SPC5_MCR_PCSIS3                     (1U << 19)
-#define SPC5_MCR_PCSIS2                     (1U << 18)
-#define SPC5_MCR_PCSIS1                     (1U << 17)
-#define SPC5_MCR_PCSIS0                     (1U << 16)
-#define SPC5_MCR_DOZE                       (1U << 15)
-#define SPC5_MCR_MDIS                       (1U << 14)
-#define SPC5_MCR_DIS_TXF                    (1U << 13)
-#define SPC5_MCR_DIS_RXF                    (1U << 12)
-#define SPC5_MCR_CLR_TXF                    (1U << 11)
-#define SPC5_MCR_CLR_RXF                    (1U << 10)
-#define SPC5_MCR_SMPL_PT_MASK               (3U << 8)
-#define SPC5_MCR_SMPL_PT(n)                 ((n) << 8)
-#define SPC5_MCR_FCPCS                      (1U << 2)
-#define SPC5_MCR_PES                        (1U << 1)
-#define SPC5_MCR_HALT                       (1U << 0)
-/** @} */
-
-/**
- * @name    RSER register definitions
- * @{
- */
-#define SPC5_RSER_TCF_RE                    (1U << 31)
-#define SPC5_RSER_DSITCF_RE                 (1U << 29)
-#define SPC5_RSER_EOQF_RE                   (1U << 28)
-#define SPC5_RSER_TFUF_RE                   (1U << 27)
-#define SPC5_RSER_SPITCF_RE                 (1U << 26)
-#define SPC5_RSER_TFFF_RE                   (1U << 25)
-#define SPC5_RSER_TFFF_DIRS                 (1U << 24)
-#define SPC5_RSER_DPEF_RE                   (1U << 22)
-#define SPC5_RSER_SPEF_RE                   (1U << 21)
-#define SPC5_RSER_DDIF_RE                   (1U << 20)
-#define SPC5_RSER_RFOF_RE                   (1U << 19)
-#define SPC5_RSER_RFDF_RE                   (1U << 17)
-#define SPC5_RSER_RFDF_DIRS                 (1U << 16)
-/** @} */
-
-/**
- * @name    CTAR registers definitions
- * @{
- */
-#define SPC5_CTAR_DBR                       (1U << 31)
-#define SPC5_CTAR_FMSZ_MASK                 (15U << 27)
-#define SPC5_CTAR_FMSZ(n)                   (((n) - 1) << 27)
-#define SPC5_CTAR_CPOL                      (1U << 26)
-#define SPC5_CTAR_CPHA                      (1U << 25)
-#define SPC5_CTAR_LSBFE                     (1U << 24)
-#define SPC5_CTAR_PCSSCK_MASK               (3U << 22)
-#define SPC5_CTAR_PCSSCK_PRE1               (0U << 22)
-#define SPC5_CTAR_PCSSCK_PRE3               (1U << 22)
-#define SPC5_CTAR_PCSSCK_PRE5               (2U << 22)
-#define SPC5_CTAR_PCSSCK_PRE7               (3U << 22)
-#define SPC5_CTAR_PASC_MASK                 (3U << 20)
-#define SPC5_CTAR_PASC_PRE1                 (0U << 20)
-#define SPC5_CTAR_PASC_PRE3                 (1U << 20)
-#define SPC5_CTAR_PASC_PRE5                 (2U << 20)
-#define SPC5_CTAR_PASC_PRE7                 (3U << 20)
-#define SPC5_CTAR_PDT_MASK                  (3U << 18)
-#define SPC5_CTAR_PDT_PRE1                  (0U << 18)
-#define SPC5_CTAR_PDT_PRE3                  (1U << 18)
-#define SPC5_CTAR_PDT_PRE5                  (2U << 18)
-#define SPC5_CTAR_PDT_PRE7                  (3U << 18)
-#define SPC5_CTAR_PBR_MASK                  (3U << 16)
-#define SPC5_CTAR_PBR_PRE2                  (0U << 16)
-#define SPC5_CTAR_PBR_PRE3                  (1U << 16)
-#define SPC5_CTAR_PBR_PRE5                  (2U << 16)
-#define SPC5_CTAR_PBR_PRE7                  (3U << 16)
-#define SPC5_CTAR_CSSCK_MASK                (15U << 12)
-#define SPC5_CTAR_CSSCK_DIV2                (0U << 12)
-#define SPC5_CTAR_CSSCK_DIV4                (1U << 12)
-#define SPC5_CTAR_CSSCK_DIV6                (2U << 12)
-#define SPC5_CTAR_CSSCK_DIV8                (3U << 12)
-#define SPC5_CTAR_CSSCK_DIV16               (4U << 12)
-#define SPC5_CTAR_CSSCK_DIV32               (5U << 12)
-#define SPC5_CTAR_CSSCK_DIV64               (6U << 12)
-#define SPC5_CTAR_CSSCK_DIV128              (7U << 12)
-#define SPC5_CTAR_CSSCK_DIV256              (8U << 12)
-#define SPC5_CTAR_CSSCK_DIV512              (9U << 12)
-#define SPC5_CTAR_CSSCK_DIV1024             (10U << 12)
-#define SPC5_CTAR_CSSCK_DIV2048             (11U << 12)
-#define SPC5_CTAR_CSSCK_DIV4096             (12U << 12)
-#define SPC5_CTAR_CSSCK_DIV8192             (13U << 12)
-#define SPC5_CTAR_CSSCK_DIV16384            (14U << 12)
-#define SPC5_CTAR_CSSCK_DIV32768            (15U << 12)
-#define SPC5_CTAR_ASC_MASK                  (15U << 8)
-#define SPC5_CTAR_ASC_DIV2                  (0U << 8)
-#define SPC5_CTAR_ASC_DIV4                  (1U << 8)
-#define SPC5_CTAR_ASC_DIV6                  (2U << 8)
-#define SPC5_CTAR_ASC_DIV8                  (3U << 8)
-#define SPC5_CTAR_ASC_DIV16                 (4U << 8)
-#define SPC5_CTAR_ASC_DIV32                 (5U << 8)
-#define SPC5_CTAR_ASC_DIV64                 (6U << 8)
-#define SPC5_CTAR_ASC_DIV128                (7U << 8)
-#define SPC5_CTAR_ASC_DIV256                (8U << 8)
-#define SPC5_CTAR_ASC_DIV512                (9U << 8)
-#define SPC5_CTAR_ASC_DIV1024               (10U << 8)
-#define SPC5_CTAR_ASC_DIV2048               (11U << 8)
-#define SPC5_CTAR_ASC_DIV4096               (12U << 8)
-#define SPC5_CTAR_ASC_DIV8192               (13U << 8)
-#define SPC5_CTAR_ASC_DIV16384              (14U << 8)
-#define SPC5_CTAR_ASC_DIV32768              (15U << 8)
-#define SPC5_CTAR_DT_MASK                   (15U << 4)
-#define SPC5_CTAR_DT_DIV2                   (0U << 4)
-#define SPC5_CTAR_DT_DIV4                   (1U << 4)
-#define SPC5_CTAR_DT_DIV6                   (2U << 4)
-#define SPC5_CTAR_DT_DIV8                   (3U << 4)
-#define SPC5_CTAR_DT_DIV16                  (4U << 4)
-#define SPC5_CTAR_DT_DIV32                  (5U << 4)
-#define SPC5_CTAR_DT_DIV64                  (6U << 4)
-#define SPC5_CTAR_DT_DIV128                 (7U << 4)
-#define SPC5_CTAR_DT_DIV256                 (8U << 4)
-#define SPC5_CTAR_DT_DIV512                 (9U << 4)
-#define SPC5_CTAR_DT_DIV1024                (10U << 4)
-#define SPC5_CTAR_DT_DIV2048                (11U << 4)
-#define SPC5_CTAR_DT_DIV4096                (12U << 4)
-#define SPC5_CTAR_DT_DIV8192                (13U << 4)
-#define SPC5_CTAR_DT_DIV16384               (14U << 4)
-#define SPC5_CTAR_DT_DIV32768               (15U << 4)
-#define SPC5_CTAR_BR_MASK                   (15U << 0)
-#define SPC5_CTAR_BR_DIV2                   (0U << 0)
-#define SPC5_CTAR_BR_DIV4                   (1U << 0)
-#define SPC5_CTAR_BR_DIV6                   (2U << 0)
-#define SPC5_CTAR_BR_DIV8                   (3U << 0)
-#define SPC5_CTAR_BR_DIV16                  (4U << 0)
-#define SPC5_CTAR_BR_DIV32                  (5U << 0)
-#define SPC5_CTAR_BR_DIV64                  (6U << 0)
-#define SPC5_CTAR_BR_DIV128                 (7U << 0)
-#define SPC5_CTAR_BR_DIV256                 (8U << 0)
-#define SPC5_CTAR_BR_DIV512                 (9U << 0)
-#define SPC5_CTAR_BR_DIV1024                (10U << 0)
-#define SPC5_CTAR_BR_DIV2048                (11U << 0)
-#define SPC5_CTAR_BR_DIV4096                (12U << 0)
-#define SPC5_CTAR_BR_DIV8192                (13U << 0)
-#define SPC5_CTAR_BR_DIV16384               (14U << 0)
-#define SPC5_CTAR_BR_DIV32768               (15U << 0)
-/** @} */
-
-/**
- * @name    PUSHR register definitions
- * @{
- */
-#define SPC5_PUSHR_CONT                     (1U << 31)
-#define SPC5_PUSHR_CTAS_MASK                (3U << 28)
-#define SPC5_PUSHR_CTAS(n)                  ((n) << 29)
-#define SPC5_PUSHR_EOQ                      (1U << 27)
-#define SPC5_PUSHR_CTCNT                    (1U << 26)
-#define SPC5_PUSHR_MASC                     (1U << 25)
-#define SPC5_PUSHR_MCSC                     (1U << 24)
-#define SPC5_PUSHR_PCS_MASK                 (255U << 16)
-#define SPC5_PUSHR_PCS(n)                   ((1U << (n)) << 16)
-#define SPC5_PUSHR_TXDATA_MASK              (0xFFFFU << 0)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-struct spc5_dspi {
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t MSTR :1;
-      vuint32_t CONT_SCKE :1;
-      vuint32_t DCONF :2;
-      vuint32_t FRZ :1;
-      vuint32_t MTFE :1;
-      vuint32_t PCSSE :1;
-      vuint32_t ROOE :1;
-      vuint32_t PCSIS7 :1;
-      vuint32_t PCSIS6 :1;
-      vuint32_t PCSIS5 :1;
-      vuint32_t PCSIS4 :1;
-      vuint32_t PCSIS3 :1;
-      vuint32_t PCSIS2 :1;
-      vuint32_t PCSIS1 :1;
-      vuint32_t PCSIS0 :1;
-      vuint32_t :1;
-      vuint32_t MDIS :1;
-      vuint32_t DIS_TXF :1;
-      vuint32_t DIS_RXF :1;
-      vuint32_t CLR_TXF :1;
-      vuint32_t CLR_RXF :1;
-      vuint32_t SMPL_PT :2;
-      vuint32_t :7;
-      vuint32_t HALT :1;
-    } B;
-  } MCR; /* Module Configuration Register */
-
-  uint32_t dspi_reserved1;
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t TCNT :16;
-      vuint32_t :16;
-    } B;
-  } TCR;
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t DBR :1;
-      vuint32_t FMSZ :4;
-      vuint32_t CPOL :1;
-      vuint32_t CPHA :1;
-      vuint32_t LSBFE :1;
-      vuint32_t PCSSCK :2;
-      vuint32_t PASC :2;
-      vuint32_t PDT :2;
-      vuint32_t PBR :2;
-      vuint32_t CSSCK :4;
-      vuint32_t ASC :4;
-      vuint32_t DT :4;
-      vuint32_t BR :4;
-    } B;
-  } CTAR[8]; /* Clock and Transfer Attributes Registers */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t TCF :1;
-      vuint32_t TXRXS :1;
-      vuint32_t :1;
-      vuint32_t EOQF :1;
-      vuint32_t TFUF :1;
-      vuint32_t :1;
-      vuint32_t TFFF :1;
-      vuint32_t :5;
-      vuint32_t RFOF :1;
-      vuint32_t :1;
-      vuint32_t RFDF :1;
-      vuint32_t :1;
-      vuint32_t TXCTR :4;
-      vuint32_t TXNXTPTR :4;
-      vuint32_t RXCTR :4;
-      vuint32_t POPNXTPTR :4;
-    } B;
-  } SR; /* Status Register */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t TCFRE :1;
-      vuint32_t :2;
-      vuint32_t EOQFRE :1;
-      vuint32_t TFUFRE :1;
-      vuint32_t :1;
-      vuint32_t TFFFRE :1;
-      vuint32_t TFFFDIRS :1;
-      vuint32_t :4;
-      vuint32_t RFOFRE :1;
-      vuint32_t :1;
-      vuint32_t RFDFRE :1;
-      vuint32_t RFDFDIRS :1;
-      vuint32_t :16;
-    } B;
-  } RSER; /* DMA/Interrupt Request Select and Enable Register */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t CONT :1;
-      vuint32_t CTAS :3;
-      vuint32_t EOQ :1;
-      vuint32_t CTCNT :1;
-      vuint32_t :2;
-      vuint32_t PCS7 :1;
-      vuint32_t PCS6 :1;
-      vuint32_t PCS5 :1;
-      vuint32_t PCS4 :1;
-      vuint32_t PCS3 :1;
-      vuint32_t PCS2 :1;
-      vuint32_t PCS1 :1;
-      vuint32_t PCS0 :1;
-      vuint32_t TXDATA :16;
-    } B;
-  } PUSHR; /* PUSH TX FIFO Register */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t :16;
-      vuint32_t RXDATA :16;
-    } B;
-  } POPR; /* POP RX FIFO Register */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t TXCMD :16;
-      vuint32_t TXDATA :16;
-    } B;
-  } TXFR[5]; /* Transmit FIFO Registers */
-
-  vuint32_t DSPI_reserved_txf[11];
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t :16;
-      vuint32_t RXDATA :16;
-    } B;
-  } RXFR[5]; /* Receive FIFO Registers */
-
-  vuint32_t DSPI_reserved_rxf[12];
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t MTOE :1;
-      vuint32_t :1;
-      vuint32_t MTOCNT :6;
-      vuint32_t :4;
-      vuint32_t TXSS :1;
-      vuint32_t TPOL :1;
-      vuint32_t TRRE :1;
-      vuint32_t CID :1;
-      vuint32_t DCONT :1;
-      vuint32_t DSICTAS :3;
-      vuint32_t :6;
-      vuint32_t DPCS5 :1;
-      vuint32_t DPCS4 :1;
-      vuint32_t DPCS3 :1;
-      vuint32_t DPCS2 :1;
-      vuint32_t DPCS1 :1;
-      vuint32_t DPCS0 :1;
-    } B;
-  } DSICR; /* DSI Configuration Register */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t :16;
-      vuint32_t SER_DATA :16;
-    } B;
-  } SDR; /* DSI Serialization Data Register */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t :16;
-      vuint32_t ASER_DATA :16;
-    } B;
-  } ASDR; /* DSI Alternate Serialization Data Register */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t :16;
-      vuint32_t COMP_DATA :16;
-    } B;
-  } COMPR; /* DSI Transmit Comparison Register */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t :16;
-      vuint32_t DESER_DATA :16;
-    } B;
-  } DDR; /* DSI deserialization Data Register */
-
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    DSPI units references
- * @{
- */
-#if SPC5_HAS_DSPI0 || defined(__DOXYGEN__)
-#define SPC5_DSPI0      (*(struct spc5_dspi *)0xFFF90000U)
-#endif
-
-#if SPC5_HAS_DSPI1 || defined(__DOXYGEN__)
-#define SPC5_DSPI1      (*(struct spc5_dspi *)0xFFF94000U)
-#endif
-
-#if SPC5_HAS_DSPI2 || defined(__DOXYGEN__)
-#define SPC5_DSPI2      (*(struct spc5_dspi *)0xFFF98000U)
-#endif
-
-#if SPC5_HAS_DSPI3 || defined(__DOXYGEN__)
-#define SPC5_DSPI3      (*(struct spc5_dspi *)0xFFF9C000U)
-#endif
-
-#if SPC5_HAS_DSPI4 || defined(__DOXYGEN__)
-#define SPC5_DSPI4      (*(struct spc5_dspi *)0x8FFA0000U)
-#endif
-/** @} */
-
-#endif /* _SPC5_DSPI_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
deleted file mode 100644
index ff78b3e9e..000000000
--- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
+++ /dev/null
@@ -1,1218 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/DSPI_v1/spi_lld.c
- * @brief   SPC5xx SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/* Some forward declarations.*/
-static void spi_serve_rx_irq(edma_channel_t channel, void *p);
-static void spi_serve_tx_irq(edma_channel_t channel, void *p);
-static void spi_serve_dma_error_irq(edma_channel_t channel,
-                                    void *p,
-                                    uint32_t esr);
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/* Excluded PUSHR bits.*/
-#define DSPI_PUSHR_EXCLUDED_BITS    (SPC5_PUSHR_CTAS_MASK   |               \
-                                     SPC5_PUSHR_EOQ         |               \
-                                     SPC5_PUSHR_TXDATA_MASK)
-
-#define DSPI_POPR8_ADDRESS(spip)    (((uint32_t)&(spip)->dspi->POPR.R) + 3)
-#define DSPI_POPR16_ADDRESS(spip)   (((uint32_t)&(spip)->dspi->POPR.R) + 2)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   SPID1 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/**
- * @brief   SPID2 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
-SPIDriver SPID2;
-#endif
-
-/**
- * @brief   SPID3 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
-SPIDriver SPID3;
-#endif
-
-/**
- * @brief   SPID4 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
-SPIDriver SPID4;
-#endif
-
-/**
- * @brief   SPID5 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
-SPIDriver SPID5;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for DSPI0 TX1.
- */
-static const edma_channel_config_t spi_dspi0_tx1_dma_config = {
-  SPC5_SPI_DSPI0_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI0_TX1_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1
-};
-
-/**
- * @brief   DMA configuration for DSPI0 TX2.
- */
-static const edma_channel_config_t spi_dspi0_tx2_dma_config = {
-  SPC5_SPI_DSPI0_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  0,
-#endif
-  SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1
-};
-
-/**
- * @brief   DMA configuration for DSPI0 RX.
- */
-static const edma_channel_config_t spi_dspi0_rx_dma_config = {
-  SPC5_SPI_DSPI0_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI0_RX_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
-  spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID1
-};
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for DSPI1 TX1.
- */
-static const edma_channel_config_t spi_dspi1_tx1_dma_config = {
-  SPC5_SPI_DSPI1_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI1_TX1_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2
-};
-
-/**
- * @brief   DMA configuration for DSPI1 TX2.
- */
-static const edma_channel_config_t spi_dspi1_tx2_dma_config = {
-  SPC5_SPI_DSPI1_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  0,
-#endif
-  SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2
-};
-
-/**
- * @brief   DMA configuration for DSPI1 RX.
- */
-static const edma_channel_config_t spi_dspi1_rx_dma_config = {
-  SPC5_SPI_DSPI1_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI1_RX_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
-  spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID2
-};
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for DSPI2 TX1.
- */
-static const edma_channel_config_t spi_dspi2_tx1_dma_config = {
-  SPC5_SPI_DSPI2_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI2_TX1_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3
-};
-
-/**
- * @brief   DMA configuration for DSPI2 TX2.
- */
-static const edma_channel_config_t spi_dspi2_tx2_dma_config = {
-  SPC5_SPI_DSPI2_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  0,
-#endif
-  SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3
-};
-
-/**
- * @brief   DMA configuration for DSPI2 RX.
- */
-static const edma_channel_config_t spi_dspi2_rx_dma_config = {
-  SPC5_SPI_DSPI2_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI2_RX_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
-  spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID3
-};
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for DSPI3 TX1.
- */
-static const edma_channel_config_t spi_dspi3_tx1_dma_config = {
-  SPC5_SPI_DSPI3_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI3_TX1_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4
-};
-
-/**
- * @brief   DMA configuration for DSPI3 TX2.
- */
-static const edma_channel_config_t spi_dspi3_tx2_dma_config = {
-  SPC5_SPI_DSPI3_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  0,
-#endif
-  SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4
-};
-
-/**
- * @brief   DMA configuration for DSPI3 RX.
- */
-static const edma_channel_config_t spi_dspi3_rx_dma_config = {
-  SPC5_SPI_DSPI3_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI3_RX_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
-  spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID4
-};
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for DSPI4 TX1.
- */
-static const edma_channel_config_t spi_dspi4_tx1_dma_config = {
-  SPC5_SPI_DSPI4_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI4_TX1_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5
-};
-
-/**
- * @brief   DMA configuration for DSPI4 TX2.
- */
-static const edma_channel_config_t spi_dspi4_tx2_dma_config = {
-  SPC5_SPI_DSPI4_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  0,
-#endif
-  SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
-  spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5
-};
-
-/**
- * @brief   DMA configuration for DSPI4 RX.
- */
-static const edma_channel_config_t spi_dspi4_rx_dma_config = {
-  SPC5_SPI_DSPI4_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
-  SPC5_DSPI4_RX_DMA_DEV_ID,
-#endif
-  SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
-  spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID5
-};
-#endif /* SPC5_SPI_USE_DSPI4 */
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Starts reception using DMA ignoring the received data.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- *
- * @notapi
- */
-static void spi_start_dma_rx_ignore(SPIDriver *spip, size_t n) {
-  static uint32_t datasink;
-
-  edmaChannelSetup(spip->rx_channel,            /* channel.                 */
-                   DSPI_POPR8_ADDRESS(spip),    /* src.                     */
-                   &datasink,                   /* dst.                     */
-                   0,                           /* soff, do not advance.    */
-                   0,                           /* doff, do not advance.    */
-                   0,                           /* ssize, 16 bits transfers.*/
-                   0,                           /* dsize, 16 bits transfers.*/
-                   1,                           /* nbytes, always one.      */
-                   n,                           /* iter.                    */
-                   0,                           /* slast.                   */
-                   0,                           /* dlast.                   */
-                   EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END);     /* mode.*/
-
-  edmaChannelStart(spip->rx_channel);
-}
-
-/**
- * @brief   Starts reception using DMA for frames up to 8 bits.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-static void spi_start_dma_rx8(SPIDriver *spip,
-                              size_t n,
-                              uint8_t *rxbuf) {
-
-  edmaChannelSetup(spip->rx_channel,            /* channel.                 */
-                   DSPI_POPR8_ADDRESS(spip),    /* src.                     */
-                   rxbuf,                       /* dst.                     */
-                   0,                           /* soff, do not advance.    */
-                   1,                           /* doff, advance by one.    */
-                   0,                           /* ssize, 8 bits transfers. */
-                   0,                           /* dsize, 8 bits transfers. */
-                   1,                           /* nbytes, always one.      */
-                   n,                           /* iter.                    */
-                   0,                           /* slast.                   */
-                   0,                           /* dlast.                   */
-                   EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END);     /* mode.*/
-
-  edmaChannelStart(spip->rx_channel);
-}
-
-/**
- * @brief   Starts reception using DMA for frames up to 16 bits.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-static void spi_start_dma_rx16(SPIDriver *spip,
-                               size_t n,
-                               uint16_t *rxbuf) {
-
-  edmaChannelSetup(spip->rx_channel,            /* channel.                 */
-                   DSPI_POPR16_ADDRESS(spip),   /* src.                     */
-                   rxbuf,                       /* dst.                     */
-                   0,                           /* soff, do not advance.    */
-                   2,                           /* doff, advance by two.    */
-                   1,                           /* ssize, 16 bits transfers.*/
-                   1,                           /* dsize, 16 bits transfers.*/
-                   2,                           /* nbytes, always two.      */
-                   n,                           /* iter.                    */
-                   0,                           /* slast, no source adjust. */
-                   0,                           /* dlast.                   */
-                   EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.    */
-
-  edmaChannelStart(spip->rx_channel);
-}
-
-/**
- * @brief   Starts transmission using DMA for frames up to 8 bits.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- *
- * @notapi
- */
-static void spi_start_dma_tx_ignore(SPIDriver *spip, size_t n) {
-
-  /* Preparing the TX intermediate buffer with the fixed part.*/
-  spip->tx_intbuf = spip->config->pushr | (uint32_t)0xFFFF;
-
-  /* The first frame is pushed by the CPU, then the DMA is activated to
-     send the following frames. This should reduce latency on the operation
-     start.*/
-  spip->dspi->PUSHR.R = spip->tx_last = spip->tx_intbuf;
-
-  /* Setting up TX1 DMA TCD parameters for 32 bits transfers.*/
-  edmaChannelSetup(spip->tx1_channel,           /* channel.                 */
-                   &spip->tx_intbuf,            /* src.                     */
-                   &spip->dspi->PUSHR.R,        /* dst.                     */
-                   0,                           /* soff, do not advance.    */
-                   0,                           /* doff, do not advance.    */
-                   2,                           /* ssize, 32 bits transfers.*/
-                   2,                           /* dsize, 32 bits transfers.*/
-                   4,                           /* nbytes, always four.     */
-                   n - 2,                       /* iter.                    */
-                   0,                           /* slast, no source adjust. */
-                   0,                           /* dlast, no dest.adjust.   */
-                   EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.    */
-
-  /* Starting TX1 DMA channel.*/
-  edmaChannelStart(spip->tx1_channel);
-}
-
-/**
- * @brief   Starts transmission using DMA for frames up to 8 bits.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_start_dma_tx8(SPIDriver *spip,
-                              size_t n,
-                              const uint8_t *txbuf) {
-
-  /* Preparing the TX intermediate buffer with the fixed part.*/
-  spip->tx_intbuf = spip->config->pushr;
-
-  /* The first frame is pushed by the CPU, then the DMA is activated to
-     send the following frames. This should reduce latency on the operation
-     start.*/
-  spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf;
-
-  /* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/
-  edmaChannelSetupLinked(
-                   spip->tx1_channel,           /* channel.                 */
-                   spip->tx2_channel,           /* linkch.                  */
-                   txbuf + 1,                   /* src.                     */
-                   ((const uint8_t *)&spip->tx_intbuf) + 3,     /* dst.     */
-                   1,                           /* soff, advance by 1.      */
-                   0,                           /* doff, do not advance.    */
-                   0,                           /* ssize, 8 bits transfers. */
-                   0,                           /* dsize, 8 bits transfers. */
-                   1,                           /* nbytes, always one.      */
-                   n - 2,                       /* iter.                    */
-                   0,                           /* slast, no source adjust. */
-                   0,                           /* dlast, no dest.adjust.   */
-                   EDMA_TCD_MODE_DREQ);         /* mode.                    */
-
-  /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/
-  edmaChannelSetup(spip->tx2_channel,           /* channel.                 */
-                   &spip->tx_intbuf,            /* src.                     */
-                   &spip->dspi->PUSHR.R,        /* dst.                     */
-                   0,                           /* soff, do not advance.    */
-                   0,                           /* doff, do not advance.    */
-                   2,                           /* ssize, 32 bits transfers.*/
-                   2,                           /* dsize, 32 bits transfers.*/
-                   4,                           /* nbytes, always four.     */
-                   n - 2,                       /* iter.                    */
-                   0,                           /* slast, no source adjust. */
-                   0,                           /* dlast, no dest.adjust.   */
-                   EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.    */
-
-  /* The last frame will be pushed by the TX DMA operation completion
-     callback.*/
-  spip->tx_last = txbuf[n - 1];
-
-  /* Starting TX DMA channels.*/
-  edmaChannelStart(spip->tx2_channel);
-  edmaChannelStart(spip->tx1_channel);
-}
-
-/**
- * @brief   Starts transmission using DMA for frames up to 16 bits.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_start_dma_tx16(SPIDriver *spip,
-                               size_t n,
-                               const uint16_t *txbuf) {
-
-  /* Preparing the TX intermediate buffer with the fixed part.*/
-  spip->tx_intbuf = spip->config->pushr;
-
-  /* The first frame is pushed by the CPU, then the DMA is activated to
-     send the following frames. This should reduce latency on the operation
-     start.*/
-  spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf;
-
-  /* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/
-  edmaChannelSetupLinked(
-                   spip->tx1_channel,           /* channel.                 */
-                   spip->tx2_channel,           /* linkch.                  */
-                   txbuf + 1,                   /* src.                     */
-                   ((const uint8_t *)&spip->tx_intbuf) + 2,     /* dst.     */
-                   1,                           /* soff, advance by 1.      */
-                   0,                           /* doff, do not advance.    */
-                   1,                           /* ssize, 16 bits transfers.*/
-                   1,                           /* dsize, 16 bits transfers.*/
-                   1,                           /* nbytes, always one.      */
-                   n - 2,                       /* iter.                    */
-                   0,                           /* slast, no source adjust. */
-                   0,                           /* dlast, no dest.adjust.   */
-                   EDMA_TCD_MODE_DREQ);         /* mode.                    */
-
-  /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/
-  edmaChannelSetup(spip->tx2_channel,           /* channel.                 */
-                   &spip->tx_intbuf,            /* src.                     */
-                   &spip->dspi->PUSHR.R,        /* dst.                     */
-                   0,                           /* soff, do not advance.    */
-                   0,                           /* doff, do not advance.    */
-                   2,                           /* ssize, 32 bits transfers.*/
-                   2,                           /* dsize, 32 bits transfers.*/
-                   4,                           /* nbytes, always four.     */
-                   n - 2,                       /* iter.                    */
-                   0,                           /* slast, no source adjust. */
-                   0,                           /* dlast, no dest.adjust.   */
-                   EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.    */
-
-  /* The last frame will be pushed by the TX DMA operation completion
-     callback.*/
-  spip->tx_last = txbuf[n - 1];
-
-  /* Starting TX DMA channels.*/
-  edmaChannelStart(spip->tx2_channel);
-  edmaChannelStart(spip->tx1_channel);
-}
-
-/**
- * @brief   Starts idle bits using FIFO pre-filling.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- *
- * @notapi
- */
-static void spi_tx_prefill_ignore(SPIDriver *spip, size_t n) {
-  uint32_t cmd = spip->config->pushr;
-
-  do {
-    if (--n == 0) {
-      spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | (uint32_t)0xFFFF) &
-                            ~SPC5_PUSHR_CONT;
-      break;
-    }
-    spip->dspi->PUSHR.R = cmd | (uint32_t)0xFFFF;
-  } while (TRUE);
-}
-
-/**
- * @brief   Starts transmission using FIFO pre-filling for frames up to 8 bits.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_tx_prefill8(SPIDriver *spip,
-                            size_t n,
-                            const uint8_t *txbuf) {
-  uint32_t cmd = spip->config->pushr;
-
-  do {
-    if (--n == 0) {
-      spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf) &
-                            ~SPC5_PUSHR_CONT;
-      break;
-    }
-    spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf;
-    txbuf++;
-  } while (TRUE);
-}
-
-/**
- * @brief   Starts transmission using FIFO pre-filling for frames up to 16 bits.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_tx_prefill16(SPIDriver *spip,
-                             size_t n,
-                             const uint16_t *txbuf) {
-  uint32_t cmd = spip->config->pushr;
-
-  do {
-    if (--n == 0) {
-      spip->dspi->PUSHR.R = SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf;
-      break;
-    }
-    spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf;
-    txbuf++;
-  } while (TRUE);
-}
-
-/**
- * @brief   Shared RX DMA events service routine.
- *
- * @param[in] channel   the channel number
- * @param[in] p         parameter for the registered function
- *
- * @notapi
- */
-static void spi_serve_rx_irq(edma_channel_t channel, void *p) {
-  SPIDriver *spip = (SPIDriver *)p;
-
-  /* Clearing RX channel state.*/
-  edmaChannelStop(channel);
-
-  /* Stops the DSPI and clears the queues.*/
-  spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
-
-  /* Portable SPI ISR code defined in the high level driver, note, it is
-     a macro.*/
-  _spi_isr_code(spip);
-}
-
-/**
- * @brief   Shared TX1/TX2 DMA events service routine.
- *
- * @param[in] channel   the channel number
- * @param[in] p         parameter for the registered function
- *
- * @notapi
- */
-static void spi_serve_tx_irq(edma_channel_t channel, void *p) {
-  SPIDriver *spip = (SPIDriver *)p;
-
-  (void)channel;
-
-  /* Clearing TX channels state.*/
-  edmaChannelStop(spip->tx1_channel);
-  edmaChannelStop(spip->tx2_channel);
-
-  /* If the TX FIFO is full then the push of the last frame is delagated to
-     an interrupt handler else it is performed immediately. Both conditions
-     can be true depending on the SPI speed and ISR latency.*/
-  if (spip->dspi->SR.B.TFFF) {
-    spip->dspi->PUSHR.R = (spip->config->pushr | spip->tx_last | SPC5_PUSHR_EOQ) &
-                          ~SPC5_PUSHR_CONT;
-  }
-  else {
-    spip->dspi->RSER.B.TFFFDIRS = 0;
-  }
-}
-
-/**
- * @brief   Shared ISR for DMA error events.
- *
- * @param[in] channel   the channel number
- * @param[in] p         parameter for the registered function
- * @param[in] esr       content of the ESR register
- *
- * @notapi
- */
-static void spi_serve_dma_error_irq(edma_channel_t channel,
-                                    void *p,
-                                    uint32_t esr) {
-  SPIDriver *spip = (SPIDriver *)p;
-
-  (void)channel;
-  (void)esr;
-
-  /* Stops the DSPI and clears the queues.*/
-  spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
-
-  edmaChannelStop(spip->tx1_channel);
-  edmaChannelStop(spip->tx2_channel);
-  edmaChannelStop(spip->rx_channel);
-
-  SPC5_SPI_DMA_ERROR_HOOK(spip);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI0_TFFF_HANDLER)
-#error "SPC5_DSPI0_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief   DSPI0 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI0_TFFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-
-  /* Interrupt served and back to DMA mode.*/
-  SPC5_DSPI0.RSER.B.TFFFDIRS = 1;
-  SPC5_DSPI0.SR.B.TFFF = 1;
-
-  /* Pushing last frame.*/
-  SPC5_DSPI0.PUSHR.R = (SPID1.config->pushr | SPID1.tx_last | SPC5_PUSHR_EOQ) &
-                        ~SPC5_PUSHR_CONT;
-
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI1_TFFF_HANDLER)
-#error "SPC5_DSPI1_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief   DSPI1 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI1_TFFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-
-  /* Interrupt served and back to DMA mode.*/
-  SPC5_DSPI1.RSER.B.TFFFDIRS = 1;
-  SPC5_DSPI1.SR.B.TFFF = 1;
-
-  /* Pushing last frame.*/
-  SPC5_DSPI1.PUSHR.R = (SPID2.config->pushr | SPID2.tx_last | SPC5_PUSHR_EOQ) &
-                        ~SPC5_PUSHR_CONT;
-
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI2_TFFF_HANDLER)
-#error "SPC5_DSPI2_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief   DSPI2 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI2_TFFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-
-  /* Interrupt served and back to DMA mode.*/
-  SPC5_DSPI2.RSER.B.TFFFDIRS = 1;
-  SPC5_DSPI2.SR.B.TFFF = 1;
-
-  /* Pushing last frame.*/
-  SPC5_DSPI2.PUSHR.R = (SPID3.config->pushr | SPID3.tx_last | SPC5_PUSHR_EOQ) &
-                        ~SPC5_PUSHR_CONT;
-
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI3_TFFF_HANDLER)
-#error "SPC5_DSPI3_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief   DSPI3 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI3_TFFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-
-  /* Interrupt served and back to DMA mode.*/
-  SPC5_DSPI3.RSER.B.TFFFDIRS = 1;
-  SPC5_DSPI3.SR.B.TFFF = 1;
-
-  /* Pushing last frame.*/
-  SPC5_DSPI3.PUSHR.R = (SPID4.config->pushr | SPID4.tx_last | SPC5_PUSHR_EOQ) &
-                        ~SPC5_PUSHR_CONT;
-
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI4_TFFF_HANDLER)
-#error "SPC5_DSPI4_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief   DSPI4 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI4_TFFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-
-  /* Interrupt served and back to DMA mode.*/
-  SPC5_DSPI4.RSER.B.TFFFDIRS = 1;
-  SPC5_DSPI4.SR.B.TFFF = 1;
-
-  /* Pushing last frame.*/
-  SPC5_DSPI4.PUSHR.R = (SPID5.config->pushr | SPID5.tx_last | SPC5_PUSHR_EOQ) &
-                        ~SPC5_PUSHR_CONT;
-
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI4 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if SPC5_SPI_USE_DSPI0
-  /* Driver initialization.*/
-  spiObjectInit(&SPID1);
-  SPC5_DSPI0_ENABLE_CLOCK();
-  SPID1.dspi = &SPC5_DSPI0;
-  SPID1.tx1_channel = EDMA_ERROR;
-  SPID1.tx2_channel = EDMA_ERROR;
-  SPID1.rx_channel  = EDMA_ERROR;
-  SPC5_DSPI0.MCR.R  = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
-                      SPC5_SPI_DSPI0_MCR;
-  INTC.PSR[SPC5_DSPI0_TFFF_NUMBER].R = SPC5_SPI_DSPI0_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1
-  /* Driver initialization.*/
-  SPC5_DSPI1_ENABLE_CLOCK();
-  spiObjectInit(&SPID2);
-  SPID2.dspi = &SPC5_DSPI1;
-  SPID2.tx1_channel = EDMA_ERROR;
-  SPID2.tx2_channel = EDMA_ERROR;
-  SPID2.rx_channel  = EDMA_ERROR;
-  SPC5_DSPI1.MCR.R  = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
-                      SPC5_SPI_DSPI1_MCR;
-  INTC.PSR[SPC5_DSPI1_TFFF_NUMBER].R = SPC5_SPI_DSPI1_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2
-  /* Driver initialization.*/
-  spiObjectInit(&SPID3);
-  SPC5_DSPI2_ENABLE_CLOCK();
-  SPID3.dspi = &SPC5_DSPI2;
-  SPID3.tx1_channel = EDMA_ERROR;
-  SPID3.tx2_channel = EDMA_ERROR;
-  SPID3.rx_channel  = EDMA_ERROR;
-  SPC5_DSPI2.MCR.R  = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
-                      SPC5_SPI_DSPI2_MCR;
-  INTC.PSR[SPC5_DSPI2_TFFF_NUMBER].R = SPC5_SPI_DSPI2_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3
-  /* Driver initialization.*/
-  spiObjectInit(&SPID4);
-  SPC5_DSPI3_ENABLE_CLOCK();
-  SPID4.dspi = &SPC5_DSPI3;
-  SPID4.tx1_channel = EDMA_ERROR;
-  SPID4.tx2_channel = EDMA_ERROR;
-  SPID4.rx_channel  = EDMA_ERROR;
-  SPC5_DSPI3.MCR.R  = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
-                      SPC5_SPI_DSPI3_MCR;
-  INTC.PSR[SPC5_DSPI3_TFFF_NUMBER].R = SPC5_SPI_DSPI3_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4
-  /* Driver initialization.*/
-  spiObjectInit(&SPID5);
-  SPC5_DSPI4_ENABLE_CLOCK();
-  SPID5.dspi = &SPC5_DSPI4;
-  SPID5.tx1_channel = EDMA_ERROR;
-  SPID5.tx2_channel = EDMA_ERROR;
-  SPID5.rx_channel  = EDMA_ERROR;
-  SPC5_DSPI4.MCR.R  = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
-                      SPC5_SPI_DSPI4_MCR;
-  INTC.PSR[SPC5_DSPI4_TFFF_NUMBER].R = SPC5_SPI_DSPI4_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI4 */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  chDbgAssert((spip->config->pushr & DSPI_PUSHR_EXCLUDED_BITS) == 0,
-              "spi_lld_start(), #1", "invalid PUSHR bits specified");
-
-  if (spip->state == SPI_STOP) {
-    /* Enables the peripheral.*/
-
-#if SPC5_SPI_USE_DSPI0
-    if (&SPID1 == spip) {
-      spip->tx1_channel = edmaChannelAllocate(&spi_dspi0_tx1_dma_config);
-      spip->tx2_channel = edmaChannelAllocate(&spi_dspi0_tx2_dma_config);
-      spip->rx_channel = edmaChannelAllocate(&spi_dspi0_rx_dma_config);
-    }
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1
-    if (&SPID2 == spip) {
-      spip->tx1_channel = edmaChannelAllocate(&spi_dspi1_tx1_dma_config);
-      spip->tx2_channel = edmaChannelAllocate(&spi_dspi1_tx2_dma_config);
-      spip->rx_channel = edmaChannelAllocate(&spi_dspi1_rx_dma_config);
-    }
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2
-    if (&SPID3 == spip) {
-      spip->tx1_channel = edmaChannelAllocate(&spi_dspi2_tx1_dma_config);
-      spip->tx2_channel = edmaChannelAllocate(&spi_dspi2_tx2_dma_config);
-      spip->rx_channel = edmaChannelAllocate(&spi_dspi2_rx_dma_config);
-    }
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3
-    if (&SPID4 == spip) {
-      spip->tx1_channel = edmaChannelAllocate(&spi_dspi3_tx1_dma_config);
-      spip->tx2_channel = edmaChannelAllocate(&spi_dspi3_tx2_dma_config);
-      spip->rx_channel = edmaChannelAllocate(&spi_dspi3_rx_dma_config);
-    }
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4
-    if (&SPID5 == spip) {
-      spip->tx1_channel = edmaChannelAllocate(&spi_dspi4_tx1_dma_config);
-      spip->tx2_channel = edmaChannelAllocate(&spi_dspi4_tx2_dma_config);
-      spip->rx_channel = edmaChannelAllocate(&spi_dspi4_rx_dma_config);
-    }
-#endif /* SPC5_SPI_USE_DSPI5 */
-
-    chDbgAssert((spip->tx1_channel != EDMA_ERROR) &&
-                (spip->tx2_channel != EDMA_ERROR) &&
-                (spip->rx_channel != EDMA_ERROR),
-                "spi_lld_start(), #2", "channel cannot be allocated");
-  }
-
-  /* Configures the peripheral.*/
-  spip->dspi->MCR.B.MDIS = 0;
-  spip->dspi->CTAR[0].R  = spip->config->ctar0;
-  spip->dspi->RSER.R     = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
-                           SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
-  spip->dspi->SR.R       = spip->dspi->SR.R;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state == SPI_READY) {
-    /* Releases the allocated EDMA channels.*/
-    edmaChannelRelease(spip->tx1_channel);
-    edmaChannelRelease(spip->tx2_channel);
-    edmaChannelRelease(spip->rx_channel);
-
-    /* Resets the peripheral.*/
-    spip->dspi->CTAR[0].R  = 0;
-    spip->dspi->RSER.R     = 0;
-    spip->dspi->SR.R       = spip->dspi->SR.R;
-    spip->dspi->MCR.R     |= SPC5_MCR_HALT |
-                             SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
-    spip->dspi->MCR.B.MDIS = 1;
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- *          idle words on the SPI bus and ignores the received data.
- * @post    At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  /* Starting transfer.*/
-  spip->dspi->SR.R  = spip->dspi->SR.R;
-  spip->dspi->MCR.B.HALT = 0;
-
-  /* Setting up the RX DMA channel.*/
-  spi_start_dma_rx_ignore(spip, n);
-
-  if (n <= SPC5_DSPI_FIFO_DEPTH) {
-    /* If the total transfer size is smaller than the TX FIFO size then
-       the whole transmitted data is pushed here and the TX DMA is not
-       activated.*/
-    spi_tx_prefill_ignore(spip, n);
-  }
-  else {
-    spi_start_dma_tx_ignore(spip, n);
-  }
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  /* Starting transfer.*/
-  spip->dspi->SR.R  = spip->dspi->SR.R;
-  spip->dspi->MCR.B.HALT = 0;
-
-  /* DMAs require a different setup depending on the frame size.*/
-  if (spip->dspi->CTAR[0].B.FMSZ < 8) {
-    /* Setting up the RX DMA channel.*/
-    spi_start_dma_rx8(spip, n, rxbuf);
-
-    if (n <= SPC5_DSPI_FIFO_DEPTH) {
-      /* If the total transfer size is smaller than the TX FIFO size then
-         the whole transmitted data is pushed here and the TX DMA is not
-         activated.*/
-      spi_tx_prefill8(spip, n, txbuf);
-    }
-    else {
-      spi_start_dma_tx8(spip, n, txbuf);
-    }
-  }
-  else {
-    /* Setting up the RX DMA channel.*/
-    spi_start_dma_rx16(spip, n, rxbuf);
-
-    if (n <= SPC5_DSPI_FIFO_DEPTH) {
-      /* If the total transfer size is smaller than the TX FIFO size then
-         the whole transmitted data is pushed here and the TX DMA is not
-         activated.*/
-      spi_tx_prefill16(spip, n, txbuf);
-    }
-    else {
-      spi_start_dma_tx16(spip, n, txbuf);
-    }
-  }
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  /* Starting transfer.*/
-  spip->dspi->SR.R  = spip->dspi->SR.R;
-  spip->dspi->MCR.B.HALT = 0;
-
-  /* Setting up the RX DMA channel.*/
-  spi_start_dma_rx_ignore(spip, n);
-
-  /* DMAs require a different setup depending on the frame size.*/
-  if (spip->dspi->CTAR[0].B.FMSZ < 8) {
-    if (n <= SPC5_DSPI_FIFO_DEPTH) {
-      /* If the total transfer size is smaller than the TX FIFO size then
-         the whole transmitted data is pushed here and the TX DMA is not
-         activated.*/
-      spi_tx_prefill8(spip, n, txbuf);
-    }
-    else {
-      spi_start_dma_tx8(spip, n, txbuf);
-    }
-  }
-  else {
-    if (n <= SPC5_DSPI_FIFO_DEPTH) {
-      /* If the total transfer size is smaller than the TX FIFO size then
-         the whole transmitted data is pushed here and the TX DMA is not
-         activated.*/
-      spi_tx_prefill16(spip, n, txbuf);
-    }
-    else {
-      spi_start_dma_tx16(spip, n, txbuf);
-    }
-  }
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  /* Starting transfer.*/
-  spip->dspi->SR.R  = spip->dspi->SR.R;
-  spip->dspi->MCR.B.HALT = 0;
-
-  /* DMAs require a different setup depending on the frame size.*/
-  if (spip->dspi->CTAR[0].B.FMSZ < 8) {
-    /* Setting up the RX DMA channel.*/
-    spi_start_dma_rx8(spip, n, rxbuf);
-  }
-  else {
-    /* Setting up the RX DMA channel.*/
-    spi_start_dma_rx16(spip, n, rxbuf);
-  }
-
-  if (n <= SPC5_DSPI_FIFO_DEPTH) {
-    /* If the total transfer size is smaller than the TX FIFO size then
-       the whole transmitted data is pushed here and the TX DMA is not
-       activated.*/
-    spi_tx_prefill_ignore(spip, n);
-  }
-  else {
-    spi_start_dma_tx_ignore(spip, n);
-  }
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-  uint32_t popr;
-
-  spip->dspi->MCR.B.HALT = 0;
-  spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | spip->config->pushr |
-                         (uint32_t)frame) & ~SPC5_PUSHR_CONT;
-  while (!spip->dspi->SR.B.RFDF)
-    ;
-  popr = spip->dspi->POPR.R;
-  spip->dspi->MCR.B.HALT = 1;
-  return (uint16_t)popr;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
deleted file mode 100644
index eafe43c7e..000000000
--- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
+++ /dev/null
@@ -1,562 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/DSPI_v1/spi_lld.h
- * @brief   SPC5xx SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-#include "spc5_dspi.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   SPID1 driver enable switch.
- * @details If set to @p TRUE the support for DSPI0 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI0) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI0                  FALSE
-#endif
-
-/**
- * @brief   SPID2 driver enable switch.
- * @details If set to @p TRUE the support for DSPI1 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI1) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI1                  FALSE
-#endif
-
-/**
- * @brief   SPID3 driver enable switch.
- * @details If set to @p TRUE the support for DSPI2 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI2) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI2                  FALSE
-#endif
-
-/**
- * @brief   SPID4 driver enable switch.
- * @details If set to @p TRUE the support for DSPI3 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI3) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI3                  FALSE
-#endif
-
-/**
- * @brief   SPID5 driver enable switch.
- * @details If set to @p TRUE the support for DSPI4 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI4) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI4                  FALSE
-#endif
-
-/**
- * @brief   DSPI0 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI0_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_MCR                  (SPC5_MCR_PCSIS0 |              \
-                                             SPC5_MCR_PCSIS1 |              \
-                                             SPC5_MCR_PCSIS2 |              \
-                                             SPC5_MCR_PCSIS3 |              \
-                                             SPC5_MCR_PCSIS4 |              \
-                                             SPC5_MCR_PCSIS5 |              \
-                                             SPC5_MCR_PCSIS6 |              \
-                                             SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief   DSPI1 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI1_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_MCR                  (SPC5_MCR_PCSIS0 |              \
-                                             SPC5_MCR_PCSIS1 |              \
-                                             SPC5_MCR_PCSIS2 |              \
-                                             SPC5_MCR_PCSIS3 |              \
-                                             SPC5_MCR_PCSIS4 |              \
-                                             SPC5_MCR_PCSIS5 |              \
-                                             SPC5_MCR_PCSIS6 |              \
-                                             SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief   DSP2 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI2_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_MCR                  (SPC5_MCR_PCSIS0 |              \
-                                             SPC5_MCR_PCSIS1 |              \
-                                             SPC5_MCR_PCSIS2 |              \
-                                             SPC5_MCR_PCSIS3 |              \
-                                             SPC5_MCR_PCSIS4 |              \
-                                             SPC5_MCR_PCSIS5 |              \
-                                             SPC5_MCR_PCSIS6 |              \
-                                             SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief   DSPI3 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI3_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_MCR                  (SPC5_MCR_PCSIS0 |              \
-                                             SPC5_MCR_PCSIS1 |              \
-                                             SPC5_MCR_PCSIS2 |              \
-                                             SPC5_MCR_PCSIS3 |              \
-                                             SPC5_MCR_PCSIS4 |              \
-                                             SPC5_MCR_PCSIS5 |              \
-                                             SPC5_MCR_PCSIS6 |              \
-                                             SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief   DSPI4 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI4_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_MCR                  (SPC5_MCR_PCSIS0 |              \
-                                             SPC5_MCR_PCSIS1 |              \
-                                             SPC5_MCR_PCSIS2 |              \
-                                             SPC5_MCR_PCSIS3 |              \
-                                             SPC5_MCR_PCSIS4 |              \
-                                             SPC5_MCR_PCSIS5 |              \
-                                             SPC5_MCR_PCSIS6 |              \
-                                             SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief   DSPI0 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO         10
-#endif
-
-/**
- * @brief   DSPI1 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI1_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10
-#endif
-
-/**
- * @brief   DSPI2 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI2_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10
-#endif
-
-/**
- * @brief   DSPI3 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI3_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO         10
-#endif
-
-/**
- * @brief   DSPI4 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI4_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO         10
-#endif
-
-/**
- * @brief   SPI DMA error hook.
- */
-#if !defined(SPC5_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define SPC5_SPI_DMA_ERROR_HOOK(spip)       chSysHalt()
-#endif
-
-/**
- * @brief   DSPI0 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI0_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_IRQ_PRIO             10
-#endif
-
-/**
- * @brief   DSPI1 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI1_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_IRQ_PRIO             10
-#endif
-
-/**
- * @brief   DSPI2 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI2_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_IRQ_PRIO             10
-#endif
-
-/**
- * @brief   DSPI3 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI3_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_IRQ_PRIO             10
-#endif
-
-/**
- * @brief   DSPI4 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI4_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_IRQ_PRIO             10
-#endif
-
-/**
- * @brief   DSPI0 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   DSPI0 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   DSPI1 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   DSPI1 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   DSPI2 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI2_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   DSPI2 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI2_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   DSPI3 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI3_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   DSPI3 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI3_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   DSPI4 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI4_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   DSPI4 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI4_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 && !SPC5_HAS_DSPI0
-#error "DSPI0 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI1 && !SPC5_HAS_DSPI1
-#error "DSPI1 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI2 && !SPC5_HAS_DSPI2
-#error "DSPI2 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI3 && !SPC5_HAS_DSPI3
-#error "DSPI3 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI4 && !SPC5_HAS_DSPI4
-#error "DSPI4 not present in the selected device"
-#endif
-
-#if !SPC5_SPI_USE_DSPI0 && !SPC5_SPI_USE_DSPI1 &&                           \
-    !SPC5_SPI_USE_DSPI2 && !SPC5_SPI_USE_DSPI3 &&                           \
-    !SPC5_SPI_USE_DSPI4
-#error "SPI driver activated but no DSPI peripheral assigned"
-#endif
-
-#if SPC5_SPI_USE_DSPI0 && (!defined(SPC5_SPI_DSPI0_TX1_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI0_TX2_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI0_RX_DMA_CH_ID))
-#error "DMA channels not defined for DSPI0, check mcuconf.h"
-#endif
-
-#if SPC5_SPI_USE_DSPI1 && (!defined(SPC5_SPI_DSPI1_TX1_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI1_TX2_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI1_RX_DMA_CH_ID))
-#error "DMA channels not defined for DSPI1, check mcuconf.h"
-#endif
-
-#if SPC5_SPI_USE_DSPI2 && (!defined(SPC5_SPI_DSPI2_TX1_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI2_TX2_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI2_RX_DMA_CH_ID))
-#error "DMA channels not defined for DSPI2, check mcuconf.h"
-#endif
-
-#if SPC5_SPI_USE_DSPI3 && (!defined(SPC5_SPI_DSPI3_TX1_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI3_TX2_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI3_RX_DMA_CH_ID))
-#error "DMA channels not defined for DSPI3, check mcuconf.h"
-#endif
-
-#if SPC5_SPI_USE_DSPI4 && (!defined(SPC5_SPI_DSPI4_TX1_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI4_TX2_DMA_CH_ID) ||        \
-                           !defined(SPC5_SPI_DSPI4_RX_DMA_CH_ID))
-#error "DMA channels not defined for DSPI4, check mcuconf.h"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief   Operation complete callback.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief   The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief   DSPI CTAR0 value for this session.
-   */
-  uint32_t              ctar0;
-  /**
-   * @brief   DSPI PUSHR command for this session.
-   * @note    Only CTAR0 can be referenced, the other CTARs are not
-   *          initialized. The data part must be left to zero.
-   */
-  uint32_t              pushr;
-} SPIConfig;
-
-/**
- * @brief   Structure representing an SPI driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct SPIDriver {
-  /**
-   * @brief   Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief   Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Pointer to the DSPI registers block.
-   */
-  struct spc5_dspi          *dspi;
-  /**
-   * @brief   EDMA channel used for data memory to memory copy.
-   */
-  edma_channel_t            tx1_channel;
-  /**
-   * @brief   EDMA channel used for transmit.
-   */
-  edma_channel_t            tx2_channel;
-  /**
-   * @brief   EDMA channel used for receive.
-   */
-  edma_channel_t            rx_channel;
-  /**
-   * @brief   Last frame of a transmission sequence.
-   */
-  uint32_t                  tx_last;
-  /**
-   * @brief   TX intermediate buffer.
-   * @note    This field is written by the TX1 DMA channel and read by the
-   *          TX2 DMA channel.
-   */
-  uint32_t                  tx_intbuf;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if SPC5_SPI_USE_DSPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#if SPC5_SPI_USE_DSPI2 && !defined(__DOXYGEN__)
-extern SPIDriver SPID3;
-#endif
-
-#if SPC5_SPI_USE_DSPI3 && !defined(__DOXYGEN__)
-extern SPIDriver SPID4;
-#endif
-
-#if SPC5_SPI_USE_DSPI4 && !defined(__DOXYGEN__)
-extern SPIDriver SPID5;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
deleted file mode 100644
index 7aad4027f..000000000
--- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
+++ /dev/null
@@ -1,1402 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/spc5_edma.c
- * @brief   EDMA helper driver code.
- *
- * @addtogroup SPC5xx_EDMA
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if SPC5_HAS_EDMA
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-static const uint8_t g0[16] = {SPC5_EDMA_GROUP0_PRIORITIES};
-#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__)
-static const uint8_t g1[16] = {SPC5_EDMA_GROUP1_PRIORITIES};
-#endif
-#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__)
-static const uint8_t g2[16] = {SPC5_EDMA_GROUP2_PRIORITIES};
-static const uint8_t g3[16] = {SPC5_EDMA_GROUP3_PRIORITIES};
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Configurations for the various EDMA channels.
- */
-static const edma_channel_config_t *channels[SPC5_EDMA_NCHANNELS];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EDMA (channels 0..31) error interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector10) {
-  edma_channel_t channel;
-  uint32_t erl, esr = SPC5_EDMA.ESR.R;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Scanning for errors.*/
-  channel = 0;
-  while (((erl = SPC5_EDMA.ERL.R) != 0) &&
-         (channel < (SPC5_EDMA_NCHANNELS > 32 ? 32 : SPC5_EDMA_NCHANNELS))) {
-    if ((erl & (1U << channel)) != 0) {
-      /* Error flag cleared.*/
-      SPC5_EDMA.CER.R = channel;
-
-      /* If the channel is not associated then the error is simply discarded
-         else the error callback is invoked.*/
-      if ((channels[channel] != NULL) &&
-          (channels[channel]->dma_error_func != NULL))
-        channels[channel]->dma_error_func(channel,
-                                          channels[channel]->dma_param,
-                                          esr);
-      channel++;
-    }
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 0 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector11) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[0] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 0;
-  channels[0]->dma_func(0, channels[0]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 1 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector12) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[1] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 1;
-  channels[1]->dma_func(1, channels[1]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 2 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector13) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[2] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 2;
-  channels[2]->dma_func(2, channels[2]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 3 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector14) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[3] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 3;
-  channels[3]->dma_func(3, channels[3]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 4 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector15) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[4] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 4;
-  channels[4]->dma_func(4, channels[4]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 5 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector16) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[5] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 5;
-  channels[5]->dma_func(5, channels[5]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 6 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector17) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[6] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 6;
-  channels[6]->dma_func(6, channels[6]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 7 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector18) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[7] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 7;
-  channels[7]->dma_func(7, channels[7]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 8 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector19) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[8] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 8;
-  channels[8]->dma_func(8, channels[8]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 9 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector20) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[9] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 9;
-  channels[9]->dma_func(9, channels[9]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 10 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector21) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[10] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 10;
-  channels[10]->dma_func(10, channels[10]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 11 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector22) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[11] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 11;
-  channels[11]->dma_func(11, channels[11]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 12 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector23) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[12] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 12;
-  channels[12]->dma_func(12, channels[12]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 13 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector24) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[13] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 13;
-  channels[13]->dma_func(13, channels[13]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 14 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector25) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[14] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 14;
-  channels[14]->dma_func(14, channels[14]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 15 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector26) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[15] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 15;
-  channels[15]->dma_func(15, channels[15]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__)
-/**
- * @brief   EDMA channel 16 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector27) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[16] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 16;
-  channels[16]->dma_func(16, channels[16]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 17 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector28) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[17] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 17;
-  channels[17]->dma_func(17, channels[17]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 18 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector29) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[18] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 18;
-  channels[18]->dma_func(18, channels[18]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 19 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector30) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[19] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 19;
-  channels[19]->dma_func(19, channels[19]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 20 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector31) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[20] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 20;
-  channels[20]->dma_func(20, channels[20]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 21 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector32) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[21] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 21;
-  channels[21]->dma_func(21, channels[21]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 22 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector33) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[22] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 22;
-  channels[22]->dma_func(22, channels[22]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 23 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector34) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[23] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 23;
-  channels[23]->dma_func(23, channels[23]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 24 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector35) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[24] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 24;
-  channels[24]->dma_func(24, channels[24]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 25 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector36) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[25] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 25;
-  channels[25]->dma_func(25, channels[25]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 26 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector37) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[26] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 26;
-  channels[26]->dma_func(26, channels[26]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 27 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector38) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[27] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 27;
-  channels[27]->dma_func(27, channels[27]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 28 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector39) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[28] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 28;
-  channels[28]->dma_func(28, channels[28]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 29 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector40) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[29] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 29;
-  channels[29]->dma_func(29, channels[29]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 30 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector41) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[30] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 30;
-  channels[30]->dma_func(30, channels[30]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 31 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector42) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[31] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 31;
-  channels[31]->dma_func(31, channels[31]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__)
-/**
- * @brief   EDMA (channels 32..64) error interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector210) {
-  edma_channel_t channel;
-  uint32_t erh, esr = SPC5_EDMA.ESR.R;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Scanning for errors.*/
-  channel = 32;
-  while (((erh = SPC5_EDMA.ERH.R) != 0) && (channel < SPC5_EDMA_NCHANNELS)) {
-
-    if ((erh & (1U << (channel - 32))) != 0) {
-      /* Error flag cleared.*/
-      SPC5_EDMA.CER.R = channel;
-
-      /* If the channel is not associated then the error is simply discarded
-         else the error callback is invoked.*/
-      if ((channels[channel] != NULL) &&
-          (channels[channel]->dma_error_func != NULL))
-        channels[channel]->dma_error_func(channel,
-                                          channels[channel]->dma_param,
-                                          esr);
-      channel++;
-    }
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 32 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector211) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[32] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 32;
-  channels[32]->dma_func(32, channels[32]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 33 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector212) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[33] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 33;
-  channels[33]->dma_func(33, channels[33]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 34 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector213) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[34] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 34;
-  channels[34]->dma_func(34, channels[34]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 35 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector214) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[35] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 35;
-  channels[35]->dma_func(35, channels[35]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 36 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector215) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[36] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 36;
-  channels[36]->dma_func(36, channels[36]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 37 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector216) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[37] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 37;
-  channels[37]->dma_func(37, channels[37]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 38 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector217) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[38] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 38;
-  channels[38]->dma_func(38, channels[38]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 39 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector218) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[39] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 39;
-  channels[39]->dma_func(39, channels[39]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 40 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector219) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[40] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 40;
-  channels[40]->dma_func(40, channels[40]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 41 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector220) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[41] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 41;
-  channels[41]->dma_func(41, channels[41]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 42 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector221) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[42] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 42;
-  channels[42]->dma_func(42, channels[42]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 43 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector222) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[43] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 43;
-  channels[43]->dma_func(43, channels[43]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 44 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector223) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[44] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 44;
-  channels[44]->dma_func(44, channels[44]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 45 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector224) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[45] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 45;
-  channels[45]->dma_func(45, channels[45]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 46 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector225) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[46] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 46;
-  channels[46]->dma_func(46, channels[46]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 47 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector226) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[47] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 47;
-  channels[47]->dma_func(47, channels[47]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 48 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector227) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[48] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 48;
-  channels[48]->dma_func(48, channels[48]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 49 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector228) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[49] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 49;
-  channels[49]->dma_func(49, channels[49]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 50 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector229) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[50] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 50;
-  channels[50]->dma_func(50, channels[50]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 51 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector230) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[51] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 51;
-  channels[51]->dma_func(51, channels[51]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 52 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector231) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[52] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 52;
-  channels[52]->dma_func(52, channels[52]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 53 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector232) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[53] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 53;
-  channels[53]->dma_func(53, channels[53]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 54 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector233) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[54] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 54;
-  channels[54]->dma_func(54, channels[54]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 55 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector234) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[55] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 55;
-  channels[55]->dma_func(55, channels[55]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 56 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector235) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[56] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 56;
-  channels[56]->dma_func(56, channels[56]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 57 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector236) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[57] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 57;
-  channels[57]->dma_func(57, channels[57]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 58 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector237) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[58] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 58;
-  channels[58]->dma_func(58, channels[58]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 59 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector238) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[59] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 59;
-  channels[59]->dma_func(59, channels[59]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 60 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector239) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[60] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 60;
-  channels[60]->dma_func(60, channels[60]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 61 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector240) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[61] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 61;
-  channels[61]->dma_func(61, channels[61]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 62 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector241) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[62] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 62;
-  channels[62]->dma_func(62, channels[62]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EDMA channel 63 interrupt.
- *
- * @isr
- */
-CH_IRQ_HANDLER(vector242) {
-
-  CH_IRQ_PROLOGUE();
-
-  if (channels[63] == NULL) {
-    SPC5_EDMA_ERROR_HANDLER();
-  }
-  SPC5_EDMA.CIRQR.R = 63;
-  channels[63]->dma_func(63, channels[63]->dma_param);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_EDMA_NCHANNELS > 32 */
-#endif /* SPC5_EDMA_NCHANNELS > 16 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EDMA driver initialization.
- *
- * @special
- */
-void edmaInit(void) {
-  unsigned i;
-
-  SPC5_EDMA.CR.R    = SPC5_EDMA_CR_SETTING;
-  SPC5_EDMA.ERQRL.R = 0x00000000;
-  SPC5_EDMA.EEIRL.R = 0x00000000;
-  SPC5_EDMA.IRQRL.R = 0xFFFFFFFF;
-  SPC5_EDMA.ERL.R =   0xFFFFFFFF;
-#if SPC5_EDMA_NCHANNELS > 32
-  SPC5_EDMA.ERQRH.R = 0x00000000;
-  SPC5_EDMA.EEIRH.R = 0x00000000;
-  SPC5_EDMA.IRQRH.R = 0xFFFFFFFF;
-  SPC5_EDMA.ERH.R =   0xFFFFFFFF;
-#endif
-  /* Initializing all the channels with a different priority withing the
-     channels group.*/
-  for (i = 0; i < 16; i++) {
-    SPC5_EDMA.CPR[i].R = g0[i];
-#if SPC5_EDMA_NCHANNELS > 16
-    SPC5_EDMA.CPR[i + 16].R = g1[i];
-#endif
-#if SPC5_EDMA_NCHANNELS > 32
-    SPC5_EDMA.CPR[i + 32].R = g2[i];
-    SPC5_EDMA.CPR[i + 48].R = g3[i];
-#endif
-  }
-
-  /* Error interrupt source.*/
-  INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO;
-
-#if defined(SPC5_EDMA_MUX_PCTL)
-  /* DMA MUX PCTL setup, only if required.*/
-  halSPCSetPeripheralClockMode(SPC5_EDMA_MUX_PCTL, SPC5_EDMA_MUX_START_PCTL);
-#endif
-}
-
-/**
- * @brief   EDMA channel allocation.
- *
- * @param[in] ccfg      channel configuration
- * @return              The channel number.
- * @retval EDMA_ERROR   if the channel cannot be allocated.
- *
- * @special
- */
-edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {
-
-  chDbgCheck((ccfg != NULL) && (ccfg->dma_irq_prio < 16),
-             "edmaChannelAllocate");
-
-  /* If the channel is already taken then an error is returned.*/
-  if (channels[ccfg->dma_channel] != NULL)
-    return EDMA_ERROR;                          /* Already taken.           */
-
-#if SPC5_EDMA_HAS_MUX
-  /* Programming the MUX.*/
-  SPC5_DMAMUX.CHCONFIG[ccfg->dma_channel].R = (uint8_t)(0x80 |
-                                                        ccfg->dma_periph);
-#endif /* !SPC5_EDMA_HAS_MUX */
-
-  /* Associating the configuration to the channel.*/
-  channels[ccfg->dma_channel] = ccfg;
-
-  /* If an error callback is defined then the error interrupt source is
-     enabled for the channel.*/
-  if (ccfg->dma_error_func != NULL)
-    SPC5_EDMA.SEEIR.R = (uint32_t)ccfg->dma_channel;
-
-  /* Setting up IRQ priority for the selected channel.*/
-  INTC.PSR[11 + ccfg->dma_channel].R = ccfg->dma_irq_prio;
-
-  return ccfg->dma_channel;
-}
-
-/**
- * @brief   EDMA channel release.
- *
- * @param[in] channel   the channel number
- *
- * @special
- */
-void edmaChannelRelease(edma_channel_t channel) {
-
-  chDbgCheck((channel >= 0) && (channel < SPC5_EDMA_NCHANNELS),
-             "edmaChannelAllocate");
-  chDbgAssert(channels[channel] != NULL,
-              "edmaChannelRelease(), #1",
-              "not allocated");
-
-  /* Enforcing a stop.*/
-  edmaChannelStop(channel);
-
-#if SPC5_EDMA_HAS_MUX
-  /* Disabling the MUX slot.*/
-  SPC5_DMAMUX.CHCONFIG[channel].R = 0;
-#endif
-
-  /* Clearing ISR sources for the channel.*/
-  SPC5_EDMA.CIRQR.R = channel;
-  SPC5_EDMA.CEEIR.R = channel;
-  SPC5_EDMA.CER.R   = channel;
-
-  /* The channels is flagged as available.*/
-  channels[channel] = NULL;
-}
-
-#endif /* SPC5_HAS_EDMA */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
deleted file mode 100644
index 6bb339537..000000000
--- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
+++ /dev/null
@@ -1,1005 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/spc5_edma.h
- * @brief   EDMA helper driver header.
- *
- * @addtogroup SPC5xx_EDMA
- * @{
- */
-
-#ifndef _SPC5_EDMA_H_
-#define _SPC5_EDMA_H_
-
-#if SPC5_HAS_EDMA
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EDMA channel allocation error.
- */
-#define EDMA_ERROR                  -1
-
-/**
- * @name    EDMA CR register definitions
- * @{
- */
-#define EDMA_CR_CX                  (1U << 17)
-#define EDMA_CR_ECX                 (1U << 16)
-#define EDMA_CR_GRP3PRI_MASK        (3U << 14)
-#define EDMA_CR_GRP3PRI(n)          ((n) << 14)
-#define EDMA_CR_GRP2PRI_MASK        (3U << 12)
-#define EDMA_CR_GRP2PRI(n)          ((n) << 12)
-#define EDMA_CR_GRP1PRI_MASK        (3U << 10)
-#define EDMA_CR_GRP1PRI(n)          ((n) << 10)
-#define EDMA_CR_GRP0PRI_MASK        (3U << 8)
-#define EDMA_CR_GRP0PRI(n)          ((n) << 8)
-#define EDMA_CR_EMLM                (1U << 7)
-#define EDMA_CR_CLM                 (1U << 6)
-#define EDMA_CR_HALT                (1U << 5)
-#define EDMA_CR_HOE                 (1U << 4)
-#define EDMA_CR_ERGA                (1U << 3)
-#define EDMA_CR_ERCA                (1U << 2)
-#define EDMA_CR_EDBG                (1U << 1)
-#define EDMA_CR_EBW                 (1U << 0)
-/** @} */
-
-/**
- * @name    EDMA mode constants
- * @{
- */
-#define EDMA_TCD_MODE_START         (1U << 0)
-#define EDMA_TCD_MODE_INT_END       (1U << 1)
-#define EDMA_TCD_MODE_INT_HALF      (1U << 2)
-#define EDMA_TCD_MODE_DREQ          (1U << 3)
-#define EDMA_TCD_MODE_SG            (1U << 4)
-#define EDMA_TCD_MODE_MELINK        (1U << 5)
-#define EDMA_TCD_MODE_ACTIVE        (1U << 6)
-#define EDMA_TCD_MODE_DONE          (1U << 7)
-#define EDMA_TCD_MODE_MLINKCH_MASK  (63U << 8)
-#define EDMA_TCD_MODE_MLINKCH(n)    ((uint32_t)(n) << 8)
-#define EDMA_TCD_MODE_BWC_MASK      (3U << 14)
-#define EDMA_TCD_MODE_BWC(n)        ((uint32_t)(n) << 14)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Default EDMA CR register initialization.
- */
-#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__)
-#define SPC5_EDMA_CR_SETTING                (EDMA_CR_GRP3PRI(3) |           \
-                                             EDMA_CR_GRP2PRI(2) |           \
-                                             EDMA_CR_GRP1PRI(1) |           \
-                                             EDMA_CR_GRP0PRI(0) |           \
-                                             EDMA_CR_EMLM       |           \
-                                             EDMA_CR_ERGA)
-#endif
-
-/**
- * @brief   Static priorities for channels group 0.
- */
-#if !defined(SPC5_EDMA_GROUP0_PRIORITIES) || defined(__DOXYGEN__)
-#define SPC5_EDMA_GROUP0_PRIORITIES                                         \
-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#endif
-
-/**
- * @brief   Static priorities for channels group 1.
- */
-#if !defined(SPC5_EDMA_GROUP1_PRIORITIES) || defined(__DOXYGEN__)
-#define SPC5_EDMA_GROUP1_PRIORITIES                                         \
-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#endif
-
-/**
- * @brief   Static priorities for channels group 2.
- */
-#if !defined(SPC5_EDMA_GROUP2_PRIORITIES) || defined(__DOXYGEN__)
-#define SPC5_EDMA_GROUP2_PRIORITIES                                         \
-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#endif
-
-/**
- * @brief   Static priorities for channels group 3.
- */
-#if !defined(SPC5_EDMA_GROUP3_PRIORITIES) || defined(__DOXYGEN__)
-#define SPC5_EDMA_GROUP3_PRIORITIES                                         \
-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#endif
-
-/**
- * @brief   EDMA error handler IRQ priority.
- */
-#if !defined(SPC5_EDMA_ERROR_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_EDMA_ERROR_IRQ_PRIO            12
-#endif
-
-/**
- * @brief   EDMA peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EDMA_MUX_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EDMA_MUX_START_PCTL            (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   EDMA critical error handler, must not return.
- */
-#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__)
-#define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of and eDMA channel number.
- */
-typedef int32_t edma_channel_t;
-
-/**
- * @brief   Type of an eDMA TCD.
- */
-typedef struct {
-  union {
-    uint32_t              word[8];
-  };
-} edma_tcd_t;
-
-/**
- * @brief   Type of an eDMA peripheral.
- */
-typedef struct {
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t :14;
-      vuint32_t CX :1;
-      vuint32_t ECX :1;
-      vuint32_t GRP3PRI :2;
-      vuint32_t GRP2PRI :2;
-      vuint32_t GRP1PRI :2;
-      vuint32_t GRP0PRI :2;
-      vuint32_t EMLM :1;
-      vuint32_t CLM :1;
-      vuint32_t HALT :1;
-      vuint32_t HOE :1;
-      vuint32_t ERGA :1;
-      vuint32_t ERCA :1;
-      vuint32_t EDBG :1;
-      vuint32_t :1;
-    } B;
-  } CR; /* DMA Control Register @baseaddress + 0x0 */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t VLD :1;
-      vuint32_t :14;
-      vuint32_t ECX :1;
-      vuint32_t GPE :1;
-      vuint32_t CPE :1;
-      vuint32_t ERRCHN :6;
-      vuint32_t SAE :1;
-      vuint32_t SOE :1;
-      vuint32_t DAE :1;
-      vuint32_t DOE :1;
-      vuint32_t NCE :1;
-      vuint32_t SGE :1;
-      vuint32_t SBE :1;
-      vuint32_t DBE :1;
-    } B;
-  } ESR; /* Error Status Register @baseaddress + 0x4 */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t ERQ63 :1;
-      vuint32_t ERQ62 :1;
-      vuint32_t ERQ61 :1;
-      vuint32_t ERQ60 :1;
-      vuint32_t ERQ59 :1;
-      vuint32_t ERQ58 :1;
-      vuint32_t ERQ57 :1;
-      vuint32_t ERQ56 :1;
-      vuint32_t ERQ55 :1;
-      vuint32_t ERQ54 :1;
-      vuint32_t ERQ53 :1;
-      vuint32_t ERQ52 :1;
-      vuint32_t ERQ51 :1;
-      vuint32_t ERQ50 :1;
-      vuint32_t ERQ49 :1;
-      vuint32_t ERQ48 :1;
-      vuint32_t ERQ47 :1;
-      vuint32_t ERQ46 :1;
-      vuint32_t ERQ45 :1;
-      vuint32_t ERQ44 :1;
-      vuint32_t ERQ43 :1;
-      vuint32_t ERQ42 :1;
-      vuint32_t ERQ41 :1;
-      vuint32_t ERQ40 :1;
-      vuint32_t ERQ39 :1;
-      vuint32_t ERQ38 :1;
-      vuint32_t ERQ37 :1;
-      vuint32_t ERQ36 :1;
-      vuint32_t ERQ35 :1;
-      vuint32_t ERQ34 :1;
-      vuint32_t ERQ33 :1;
-      vuint32_t ERQ32 :1;
-    } B;
-  } ERQRH; /* DMA Enable Request Register High @baseaddress + 0x8*/
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t ERQ31 :1;
-      vuint32_t ERQ30 :1;
-      vuint32_t ERQ29 :1;
-      vuint32_t ERQ28 :1;
-      vuint32_t ERQ27 :1;
-      vuint32_t ERQ26 :1;
-      vuint32_t ERQ25 :1;
-      vuint32_t ERQ24 :1;
-      vuint32_t ERQ23 :1;
-      vuint32_t ERQ22 :1;
-      vuint32_t ERQ21 :1;
-      vuint32_t ERQ20 :1;
-      vuint32_t ERQ19 :1;
-      vuint32_t ERQ18 :1;
-      vuint32_t ERQ17 :1;
-      vuint32_t ERQ16 :1;
-      vuint32_t ERQ15 :1;
-      vuint32_t ERQ14 :1;
-      vuint32_t ERQ13 :1;
-      vuint32_t ERQ12 :1;
-      vuint32_t ERQ11 :1;
-      vuint32_t ERQ10 :1;
-      vuint32_t ERQ09 :1;
-      vuint32_t ERQ08 :1;
-      vuint32_t ERQ07 :1;
-      vuint32_t ERQ06 :1;
-      vuint32_t ERQ05 :1;
-      vuint32_t ERQ04 :1;
-      vuint32_t ERQ03 :1;
-      vuint32_t ERQ02 :1;
-      vuint32_t ERQ01 :1;
-      vuint32_t ERQ00 :1;
-    } B;
-  } ERQRL; /* DMA Enable Request Register Low @baseaddress + 0xC*/
-
-  union {
-    vuint32_t R;
-    struct {
-
-      vuint32_t EEI63 :1;
-      vuint32_t EEI62 :1;
-      vuint32_t EEI61 :1;
-      vuint32_t EEI60 :1;
-      vuint32_t EEI59 :1;
-      vuint32_t EEI58 :1;
-      vuint32_t EEI57 :1;
-      vuint32_t EEI56 :1;
-      vuint32_t EEI55 :1;
-      vuint32_t EEI54 :1;
-      vuint32_t EEI53 :1;
-      vuint32_t EEI52 :1;
-      vuint32_t EEI51 :1;
-      vuint32_t EEI50 :1;
-      vuint32_t EEI49 :1;
-      vuint32_t EEI48 :1;
-      vuint32_t EEI47 :1;
-      vuint32_t EEI46 :1;
-      vuint32_t EEI45 :1;
-      vuint32_t EEI44 :1;
-      vuint32_t EEI43 :1;
-      vuint32_t EEI42 :1;
-      vuint32_t EEI41 :1;
-      vuint32_t EEI40 :1;
-      vuint32_t EEI39 :1;
-      vuint32_t EEI38 :1;
-      vuint32_t EEI37 :1;
-      vuint32_t EEI36 :1;
-      vuint32_t EEI35 :1;
-      vuint32_t EEI34 :1;
-      vuint32_t EEI33 :1;
-      vuint32_t EEI32 :1;
-    } B;
-  } EEIRH; /* DMA Enable Error Interrupt Register High @baseaddress + 0x10*/
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t EEI31 :1;
-      vuint32_t EEI30 :1;
-      vuint32_t EEI29 :1;
-      vuint32_t EEI28 :1;
-      vuint32_t EEI27 :1;
-      vuint32_t EEI26 :1;
-      vuint32_t EEI25 :1;
-      vuint32_t EEI24 :1;
-      vuint32_t EEI23 :1;
-      vuint32_t EEI22 :1;
-      vuint32_t EEI21 :1;
-      vuint32_t EEI20 :1;
-      vuint32_t EEI19 :1;
-      vuint32_t EEI18 :1;
-      vuint32_t EEI17 :1;
-      vuint32_t EEI16 :1;
-      vuint32_t EEI15 :1;
-      vuint32_t EEI14 :1;
-      vuint32_t EEI13 :1;
-      vuint32_t EEI12 :1;
-      vuint32_t EEI11 :1;
-      vuint32_t EEI10 :1;
-      vuint32_t EEI09 :1;
-      vuint32_t EEI08 :1;
-      vuint32_t EEI07 :1;
-      vuint32_t EEI06 :1;
-      vuint32_t EEI05 :1;
-      vuint32_t EEI04 :1;
-      vuint32_t EEI03 :1;
-      vuint32_t EEI02 :1;
-      vuint32_t EEI01 :1;
-      vuint32_t EEI00 :1;
-    } B;
-  } EEIRL; /* DMA Enable Error Interrupt Register Low @baseaddress + 0x14*/
-
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t NOP :1;
-      vuint8_t SERQ :7;
-    } B;
-  } SERQR; /* DMA Set Enable Request Register @baseaddress + 0x18*/
-
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t NOP :1;
-      vuint8_t CERQ :7;
-    } B;
-  } CERQR; /* DMA Clear Enable Request Register @baseaddress + 0x19*/
-
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t NOP :1;
-      vuint8_t SEEI :7;
-    } B;
-  } SEEIR; /* DMA Set Enable Error Interrupt Register @baseaddress + 0x1A*/
-
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t NOP :1;
-      vuint8_t CEEI :7;
-    } B;
-  } CEEIR; /* DMA Clear Enable Error Interrupt Register @baseaddress + 0x1B*/
-
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t NOP :1;
-      vuint8_t CINT :7;
-    } B;
-  } CIRQR; /* DMA Clear Interrupt Request Register @baseaddress + 0x1C */
-
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t NOP :1;
-      vuint8_t CERR :7;
-    } B;
-  } CER; /* DMA Clear error Register @baseaddress + 0x1D */
-
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t NOP :1;
-      vuint8_t SSB :7;
-    } B;
-  } SSBR; /* Set Start Bit Register @baseaddress + 0x1E */
-
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t NOP :1;
-      vuint8_t CDSB :7;
-    } B;
-  } CDSBR; /* Clear Done Status Bit Register @baseaddress + 0x1F */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t INT63 :1;
-      vuint32_t INT62 :1;
-      vuint32_t INT61 :1;
-      vuint32_t INT60 :1;
-      vuint32_t INT59 :1;
-      vuint32_t INT58 :1;
-      vuint32_t INT57 :1;
-      vuint32_t INT56 :1;
-      vuint32_t INT55 :1;
-      vuint32_t INT54 :1;
-      vuint32_t INT53 :1;
-      vuint32_t INT52 :1;
-      vuint32_t INT51 :1;
-      vuint32_t INT50 :1;
-      vuint32_t INT49 :1;
-      vuint32_t INT48 :1;
-      vuint32_t INT47 :1;
-      vuint32_t INT46 :1;
-      vuint32_t INT45 :1;
-      vuint32_t INT44 :1;
-      vuint32_t INT43 :1;
-      vuint32_t INT42 :1;
-      vuint32_t INT41 :1;
-      vuint32_t INT40 :1;
-      vuint32_t INT39 :1;
-      vuint32_t INT38 :1;
-      vuint32_t INT37 :1;
-      vuint32_t INT36 :1;
-      vuint32_t INT35 :1;
-      vuint32_t INT34 :1;
-      vuint32_t INT33 :1;
-      vuint32_t INT32 :1;
-    } B;
-  } IRQRH; /* DMA Interrupt Request High @baseaddress + 0x20 */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t INT31 :1;
-      vuint32_t INT30 :1;
-      vuint32_t INT29 :1;
-      vuint32_t INT28 :1;
-      vuint32_t INT27 :1;
-      vuint32_t INT26 :1;
-      vuint32_t INT25 :1;
-      vuint32_t INT24 :1;
-      vuint32_t INT23 :1;
-      vuint32_t INT22 :1;
-      vuint32_t INT21 :1;
-      vuint32_t INT20 :1;
-      vuint32_t INT19 :1;
-      vuint32_t INT18 :1;
-      vuint32_t INT17 :1;
-      vuint32_t INT16 :1;
-      vuint32_t INT15 :1;
-      vuint32_t INT14 :1;
-      vuint32_t INT13 :1;
-      vuint32_t INT12 :1;
-      vuint32_t INT11 :1;
-      vuint32_t INT10 :1;
-      vuint32_t INT09 :1;
-      vuint32_t INT08 :1;
-      vuint32_t INT07 :1;
-      vuint32_t INT06 :1;
-      vuint32_t INT05 :1;
-      vuint32_t INT04 :1;
-      vuint32_t INT03 :1;
-      vuint32_t INT02 :1;
-      vuint32_t INT01 :1;
-      vuint32_t INT00 :1;
-    } B;
-  } IRQRL; /* DMA Interrupt Request Low @baseaddress + 0x24 */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t ERR63 :1;
-      vuint32_t ERR62 :1;
-      vuint32_t ERR61 :1;
-      vuint32_t ERR60 :1;
-      vuint32_t ERR59 :1;
-      vuint32_t ERR58 :1;
-      vuint32_t ERR57 :1;
-      vuint32_t ERR56 :1;
-      vuint32_t ERR55 :1;
-      vuint32_t ERR54 :1;
-      vuint32_t ERR53 :1;
-      vuint32_t ERR52 :1;
-      vuint32_t ERR51 :1;
-      vuint32_t ERR50 :1;
-      vuint32_t ERR49 :1;
-      vuint32_t ERR48 :1;
-      vuint32_t ERR47 :1;
-      vuint32_t ERR46 :1;
-      vuint32_t ERR45 :1;
-      vuint32_t ERR44 :1;
-      vuint32_t ERR43 :1;
-      vuint32_t ERR42 :1;
-      vuint32_t ERR41 :1;
-      vuint32_t ERR40 :1;
-      vuint32_t ERR39 :1;
-      vuint32_t ERR38 :1;
-      vuint32_t ERR37 :1;
-      vuint32_t ERR36 :1;
-      vuint32_t ERR35 :1;
-      vuint32_t ERR34 :1;
-      vuint32_t ERR33 :1;
-      vuint32_t ERR32 :1;
-    } B;
-  } ERH; /* DMA Error High @baseaddress + 0x28 */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t ERR31 :1;
-      vuint32_t ERR30 :1;
-      vuint32_t ERR29 :1;
-      vuint32_t ERR28 :1;
-      vuint32_t ERR27 :1;
-      vuint32_t ERR26 :1;
-      vuint32_t ERR25 :1;
-      vuint32_t ERR24 :1;
-      vuint32_t ERR23 :1;
-      vuint32_t ERR22 :1;
-      vuint32_t ERR21 :1;
-      vuint32_t ERR20 :1;
-      vuint32_t ERR19 :1;
-      vuint32_t ERR18 :1;
-      vuint32_t ERR17 :1;
-      vuint32_t ERR16 :1;
-      vuint32_t ERR15 :1;
-      vuint32_t ERR14 :1;
-      vuint32_t ERR13 :1;
-      vuint32_t ERR12 :1;
-      vuint32_t ERR11 :1;
-      vuint32_t ERR10 :1;
-      vuint32_t ERR09 :1;
-      vuint32_t ERR08 :1;
-      vuint32_t ERR07 :1;
-      vuint32_t ERR06 :1;
-      vuint32_t ERR05 :1;
-      vuint32_t ERR04 :1;
-      vuint32_t ERR03 :1;
-      vuint32_t ERR02 :1;
-      vuint32_t ERR01 :1;
-      vuint32_t ERR00 :1;
-    } B;
-  } ERL; /* DMA Error Low @baseaddress + 0x2C */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t HRS63 :1;
-      vuint32_t HRS62 :1;
-      vuint32_t HRS61 :1;
-      vuint32_t HRS60 :1;
-      vuint32_t HRS59 :1;
-      vuint32_t HRS58 :1;
-      vuint32_t HRS57 :1;
-      vuint32_t HRS56 :1;
-      vuint32_t HRS55 :1;
-      vuint32_t HRS54 :1;
-      vuint32_t HRS53 :1;
-      vuint32_t HRS52 :1;
-      vuint32_t HRS51 :1;
-      vuint32_t HRS50 :1;
-      vuint32_t HRS49 :1;
-      vuint32_t HRS48 :1;
-      vuint32_t HRS47 :1;
-      vuint32_t HRS46 :1;
-      vuint32_t HRS45 :1;
-      vuint32_t HRS44 :1;
-      vuint32_t HRS43 :1;
-      vuint32_t HRS42 :1;
-      vuint32_t HRS41 :1;
-      vuint32_t HRS40 :1;
-      vuint32_t HRS39 :1;
-      vuint32_t HRS38 :1;
-      vuint32_t HRS37 :1;
-      vuint32_t HRS36 :1;
-      vuint32_t HRS35 :1;
-      vuint32_t HRS34 :1;
-      vuint32_t HRS33 :1;
-      vuint32_t HRS32 :1;
-    } B;
-  } HRSH; /* hardware request status high @baseaddress + 0x30 */
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t HRS31 :1;
-      vuint32_t HRS30 :1;
-      vuint32_t HRS29 :1;
-      vuint32_t HRS28 :1;
-      vuint32_t HRS27 :1;
-      vuint32_t HRS26 :1;
-      vuint32_t HRS25 :1;
-      vuint32_t HRS24 :1;
-      vuint32_t HRS23 :1;
-      vuint32_t HRS22 :1;
-      vuint32_t HRS21 :1;
-      vuint32_t HRS20 :1;
-      vuint32_t HRS19 :1;
-      vuint32_t HRS18 :1;
-      vuint32_t HRS17 :1;
-      vuint32_t HRS16 :1;
-      vuint32_t HRS15 :1;
-      vuint32_t HRS14 :1;
-      vuint32_t HRS13 :1;
-      vuint32_t HRS12 :1;
-      vuint32_t HRS11 :1;
-      vuint32_t HRS10 :1;
-      vuint32_t HRS09 :1;
-      vuint32_t HRS08 :1;
-      vuint32_t HRS07 :1;
-      vuint32_t HRS06 :1;
-      vuint32_t HRS05 :1;
-      vuint32_t HRS04 :1;
-      vuint32_t HRS03 :1;
-      vuint32_t HRS02 :1;
-      vuint32_t HRS01 :1;
-      vuint32_t HRS00 :1;
-    } B;
-  } HRSL; /* hardware request status low @baseaddress + 0x34 */
-
-  uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */
-
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t ECP :1;
-      vuint8_t DPA :1;
-      vuint8_t GRPPRI :2;
-      vuint8_t CHPRI :4;
-    } B;
-  } CPR[64]; /* Channel n Priority @baseaddress + 0x100 */
-
-  uint32_t eDMA_reserved0140[944]; /* 0x0140-0x0FFF */
-
-  edma_tcd_t TCD[64];
-} edma_t;
-
-#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
-/**
- * @brief   Type of a DMA-MUX peripheral.
- */
-typedef struct {
-  union {
-    vuint8_t R;
-    struct {
-      vuint8_t ENBL:1;
-      vuint8_t TRIG:1;
-      vuint8_t SOURCE:6;
-    } B;
-  } CHCONFIG[SPC5_EDMA_NCHANNELS];
-} dma_mux_t;
-#endif /* SPC5_EDMA_HAS_MUX */
-
-/**
- * @brief   DMA callback type.
- *
- * @param[in] channel   the channel number
- * @param[in] p         parameter for the registered function
- */
-typedef void (*edma_callback_t)(edma_channel_t channel, void *p);
-
-/**
- * @brief   DMA error callback type.
- *
- * @param[in] channel   the channel number
- * @param[in] p         parameter for the registered function
- * @param[in] esr       content of the ESR register
- */
-typedef void (*edma_error_callback_t)(edma_channel_t channel,
-                                      void *p,
-                                      uint32_t esr);
-
-/**
- * @brief   Type of an EDMA channel configuration structure.
- */
-typedef struct {
-  edma_channel_t        dma_channel;    /**< @brief Channel to be allocated.*/
-#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
-  uint8_t               dma_periph;     /**< @brief Peripheral to be
-                                             associated to the channel.     */
-#endif
-  uint8_t               dma_irq_prio;   /**< @brief IRQ priority level for
-                                             this channel.                  */
-  edma_callback_t       dma_func;       /**< @brief Channel callback,
-                                             can be NULL if not required.  */
-  edma_error_callback_t dma_error_func; /**< @brief Channel error callback,
-                                             can be NULL if not required.  */
-  void                  *dma_param;     /**< @brief Channel callback param. */
-} edma_channel_config_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Peripherals references
- *
- * @{
- */
-#if SPC5_HAS_EDMA || defined(__DOXYGEN__)
-#define SPC5_EDMA       (*(edma_t *)0xFFF44000U)
-#endif
-
-#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
-#define SPC5_DMAMUX     (*(dma_mux_t *)0xFFFDC000UL)
-#endif
-/** @} */
-
-/**
- * @brief   Returns the TCD address associated to a channel.
- *
- * @param[in] channel   the channel number
- * @return              A pointer to an @p edma_tcd_t structure.
- *
- * @api
- */
-#define edmaGetTCD(channel) ((edma_tcd_t *)&SPC5_EDMA.TCD[channel])
-
-/**
- * @brief   Sets the word 0 fields into a TCD.
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] src       the source address
- *
- * @api
- */
-#define edmaTCDSetWord0(tcdp, src)                                          \
-  ((tcdp)->word[0] = (uint32_t)(src))
-
-/**
- * @brief   Sets the word 1 fields into a TCD.
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] ssize     the source width
- * @param[in] dst       the destination width
- * @param[in] soff      the source increment value
- *
- * @api
- */
-#define edmaTCDSetWord1(tcdp, ssize, dsize, soff)                           \
-  ((tcdp)->word[1] = (((uint32_t)(ssize) << 24) |                           \
-                      ((uint32_t)(dsize) << 16) |                           \
-                      ((uint32_t)(soff) << 0)))
-
-/**
- * @brief   Sets the word 2 fields into a TCD.
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] nbytes    the inner counter value
- *
- * @api
- */
-#define edmaTCDSetWord2(tcdp, nbytes)                                       \
-  ((tcdp)->word[2] = (uint32_t)(nbytes))
-
-/**
- * @brief   Sets the word 3 fields into a TCD.
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] slast      the adjustment value
- *
- * @api
- */
-#define edmaTCDSetWord3(tcdp, slast)                                        \
-  ((tcdp)->word[3] = (uint32_t)(slast))
-
-/**
- * @brief   Sets the word 4 fields into a TCD.
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] dst       the destination address
- *
- * @api
- */
-#define edmaTCDSetWord4(tcdp, dst)                                          \
-  ((tcdp)->word[4] = (uint32_t)(dst))
-
-/**
- * @brief   Sets the word 5 fields into a TCD.
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] citer     the current outer counter value
- * @param[in] doff      the destination increment value
- *
- * @api
- */
-#define edmaTCDSetWord5(tcdp, citer, doff)                                  \
-  ((tcdp)->word[5] = (((uint32_t)(citer) << 16) |                           \
-                      ((uint32_t)(doff) << 0)))
-
-/**
- * @brief   Sets the word 5 fields into a TCD.
- * @note    Transfers are limited to 512 operations using this modality
- *          (citer parameter).
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] linkch    channel linked on minor loop counter
- * @param[in] citer     the current outer counter value
- * @param[in] doff      the destination increment value
- *
- * @api
- */
-#define edmaTCDSetWord5Linked(tcdp, linkch, citer, doff)                    \
-  ((tcdp)->word[5] = (((uint32_t)0x80000000) |                              \
-                      ((uint32_t)(linkch) << 25) |                          \
-                      ((uint32_t)(citer) << 16) |                           \
-                      ((uint32_t)(doff) << 0)))
-
-/**
- * @brief   Sets the word 6 fields into a TCD.
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] dlast     the adjustment value
- *
- * @api
- */
-#define edmaTCDSetWord6(tcdp, dlast)                                        \
-  ((tcdp)->word[6] = (uint32_t)(dlast))
-
-/**
- * @brief   Sets the word 7 fields into a TCD.
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] biter     the base outer counter value
- * @param[in] mode      the mode value
- *
- * @api
- */
-#define edmaTCDSetWord7(tcdp, biter, mode)                                  \
-  ((tcdp)->word[7] = (((uint32_t)(biter) << 16) |                           \
-                      ((uint32_t)(mode) << 0)))
-
-/**
- * @brief   Sets the word 7 fields into a TCD.
- * @note    Transfers are limited to 512 operations using this modality
- *          (biter parameter).
- *
- * @param[in] tcdp      pointer to an @p edma_tcd_t structure
- * @param[in] linkch    channel linked on minor loop counter
- * @param[in] biter     the base outer counter value
- * @param[in] mode      the mode value
- *
- * @api
- */
-#define edmaTCDSetWord7Linked(tcdp, linkch, biter, mode)                    \
-  ((tcdp)->word[7] = (((uint32_t)0x80000000) |                              \
-                      ((uint32_t)(linkch) << 25) |                          \
-                      ((uint32_t)(biter) << 16) |                           \
-                      ((uint32_t)(mode) << 0)))
-
-/**
- * @brief   Starts or restarts an EDMA channel.
- *
- * @param[in] channel   the channel number
- *
- * @api
- */
-#define edmaChannelStart(channel) (SPC5_EDMA.SERQR.R = (channel))
-
-/**
- * @brief   Stops an EDMA channel.
- *
- * @param[in] channel   the channel number
- *
- * @api
- */
-#define edmaChannelStop(channel) {                                          \
-  SPC5_EDMA.CERQR.R = (channel);                                            \
-  SPC5_EDMA.CDSBR.R = (channel);                                            \
-}
-
-/**
- * @brief   EDMA channel setup.
- *
- * @param[in] channel   eDMA channel number
- * @param[in] src       source address
- * @param[in] dst       destination address
- * @param[in] soff      source address offset
- * @param[in] doff      destination address offset
- * @param[in] ssize     source transfer size
- * @param[in] dsize     destination transfer size
- * @param[in] nbytes    minor loop count
- * @param[in] iter      major loop count
- * @param[in] dlast     last destination address adjustment
- * @param[in] slast     last source address adjustment
- * @param[in] mode      LSW of TCD register 7
- *
- * @api
- */
-#define edmaChannelSetup(channel, src, dst, soff, doff, ssize, dsize,       \
-                         nbytes, iter, slast, dlast, mode) {                \
-  edma_tcd_t *tcdp = edmaGetTCD(channel);                                   \
-  edmaTCDSetWord0(tcdp, src);                                               \
-  edmaTCDSetWord1(tcdp, ssize, dsize, soff);                                \
-  edmaTCDSetWord2(tcdp, nbytes);                                            \
-  edmaTCDSetWord3(tcdp, slast);                                             \
-  edmaTCDSetWord4(tcdp, dst);                                               \
-  edmaTCDSetWord5(tcdp, iter, doff);                                        \
-  edmaTCDSetWord6(tcdp, dlast);                                             \
-  edmaTCDSetWord7(tcdp, iter, mode);                                        \
-}
-
-/**
- * @brief   EDMA channel setup with linked channel on both minor and major
- *          loop counters.
- * @note    Transfers are limited to 512 operations using this modality
- *          (iter parameter).
- *
- * @param[in] channel   eDMA channel number
- * @param[in] linkch    channel linked on minor loop counter
- * @param[in] src       source address
- * @param[in] dst       destination address
- * @param[in] soff      source address offset
- * @param[in] doff      destination address offset
- * @param[in] ssize     source transfer size
- * @param[in] dsize     destination transfer size
- * @param[in] nbytes    minor loop count
- * @param[in] iter      major loop count
- * @param[in] dlast     last destination address adjustment
- * @param[in] slast     last source address adjustment
- * @param[in] mode      LSW of TCD register 7
- *
- * @api
- */
-#define edmaChannelSetupLinked(channel, linkch, src, dst, soff,             \
-                               doff, ssize, dsize, nbytes, iter,            \
-                               slast, dlast, mode) {                        \
-  edma_tcd_t *tcdp = edmaGetTCD(channel);                                   \
-  edmaTCDSetWord0(tcdp, src);                                               \
-  edmaTCDSetWord1(tcdp, ssize, dsize, soff);                                \
-  edmaTCDSetWord2(tcdp, nbytes);                                            \
-  edmaTCDSetWord3(tcdp, slast);                                             \
-  edmaTCDSetWord4(tcdp, dst);                                               \
-  edmaTCDSetWord5Linked(tcdp, linkch, iter, doff);                          \
-  edmaTCDSetWord6(tcdp, dlast);                                             \
-  edmaTCDSetWord7Linked(tcdp, linkch, iter, (mode) |                        \
-                                            EDMA_TCD_MODE_MELINK |          \
-                                            EDMA_TCD_MODE_MLINKCH(linkch)); \
-}
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void edmaInit(void);
-  edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg);
-  void edmaChannelRelease(edma_channel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SPC5_HAS_EDMA */
-
-#endif /* _SPC5_EDMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
deleted file mode 100644
index cb479fa1b..000000000
--- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
+++ /dev/null
@@ -1,744 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/EQADC_v1/adc_lld.c
- * @brief   SPC5xx low level ADC driver code.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/* Some forward declarations.*/
-static void adc_serve_rfifo_irq(edma_channel_t channel, void *p);
-static void adc_serve_dma_error_irq(edma_channel_t channel,
-                                    void *p,
-                                    uint32_t esr);
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Calibration constant.
- * @details Ideal conversion result for 75%(VRH - VRL) minus 2.
- */
-#define ADC_IDEAL_RES75_2       12286
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ADCD1 driver identifier.
- */
-#if SPC5_ADC_USE_ADC0_Q0 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/**
- * @brief   ADCD2 driver identifier.
- */
-#if SPC5_ADC_USE_ADC0_Q1 || defined(__DOXYGEN__)
-ADCDriver ADCD2;
-#endif
-
-/**
- * @brief   ADCD3 driver identifier.
- */
-#if SPC5_ADC_USE_ADC0_Q2 || defined(__DOXYGEN__)
-ADCDriver ADCD3;
-#endif
-
-/**
- * @brief   ADCD4 driver identifier.
- */
-#if SPC5_ADC_USE_ADC1_Q3 || defined(__DOXYGEN__)
-ADCDriver ADCD4;
-#endif
-
-/**
- * @brief   ADCD5 driver identifier.
- */
-#if SPC5_ADC_USE_ADC1_Q4 || defined(__DOXYGEN__)
-ADCDriver ADCD5;
-#endif
-
-/**
- * @brief   ADCD6 driver identifier.
- */
-#if SPC5_ADC_USE_ADC1_Q5 || defined(__DOXYGEN__)
-ADCDriver ADCD6;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of active ADC FIFOs.
- */
-static uint32_t adc_active_fifos;
-
-/**
- * @brief   Static setup for input resistors.
- */
-static const uint16_t pudcrs[8] = SPC5_ADC_PUDCR;
-
-#if SPC5_ADC_USE_ADC0_Q0 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for EQADC CFIFO0.
- */
-static const edma_channel_config_t adc_cfifo0_dma_config = {
-  0, SPC5_ADC_FIFO0_DMA_IRQ_PRIO,
-  NULL, adc_serve_dma_error_irq, &ADCD1
-};
-
-/**
- * @brief   DMA configuration for EQADC RFIFO0.
- */
-static const edma_channel_config_t adc_rfifo0_dma_config = {
-  1, SPC5_ADC_FIFO0_DMA_IRQ_PRIO,
-  adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD1
-};
-#endif /* SPC5_ADC_USE_ADC0_Q0 */
-
-#if SPC5_ADC_USE_ADC0_Q1 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for EQADC CFIFO1.
- */
-static const edma_channel_config_t adc_cfifo1_dma_config = {
-  2, SPC5_ADC_FIFO1_DMA_IRQ_PRIO,
-  NULL, adc_serve_dma_error_irq, &ADCD2
-};
-
-/**
- * @brief   DMA configuration for EQADC RFIFO1.
- */
-static const edma_channel_config_t adc_rfifo1_dma_config = {
-  3, SPC5_ADC_FIFO1_DMA_IRQ_PRIO,
-  adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD2
-};
-#endif /* SPC5_ADC_USE_ADC0_Q1 */
-
-#if SPC5_ADC_USE_ADC0_Q2 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for EQADC CFIFO2.
- */
-static const edma_channel_config_t adc_cfifo2_dma_config = {
-  4, SPC5_ADC_FIFO2_DMA_IRQ_PRIO,
-  NULL, adc_serve_dma_error_irq, &ADCD3
-};
-
-/**
- * @brief   DMA configuration for EQADC RFIFO2.
- */
-static const edma_channel_config_t adc_rfifo2_dma_config = {
-  5, SPC5_ADC_FIFO2_DMA_IRQ_PRIO,
-  adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD3
-};
-#endif /* SPC5_ADC_USE_ADC0_Q2 */
-
-#if SPC5_ADC_USE_ADC1_Q3 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for EQADC CFIFO3.
- */
-static const edma_channel_config_t adc_cfifo3_dma_config = {
-  6, SPC5_ADC_FIFO3_DMA_IRQ_PRIO,
-  NULL, adc_serve_dma_error_irq, &ADCD4
-};
-
-/**
- * @brief   DMA configuration for EQADC RFIFO3.
- */
-static const edma_channel_config_t adc_rfifo3_dma_config = {
-  7, SPC5_ADC_FIFO3_DMA_IRQ_PRIO,
-  adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD4
-};
-#endif /* SPC5_ADC_USE_ADC1_Q3 */
-
-#if SPC5_ADC_USE_ADC1_Q4 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for EQADC CFIFO4.
- */
-static const edma_channel_config_t adc_cfifo4_dma_config = {
-  8, SPC5_ADC_FIFO4_DMA_IRQ_PRIO,
-  NULL, adc_serve_dma_error_irq, &ADCD5
-};
-
-/**
- * @brief   DMA configuration for EQADC RFIFO4.
- */
-static const edma_channel_config_t adc_rfifo4_dma_config = {
-  9, SPC5_ADC_FIFO4_DMA_IRQ_PRIO,
-  adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD5
-};
-#endif /* SPC5_ADC_USE_ADC1_Q4 */
-
-#if SPC5_ADC_USE_ADC1_Q5 || defined(__DOXYGEN__)
-/**
- * @brief   DMA configuration for EQADC CFIFO5.
- */
-static const edma_channel_config_t adc_cfifo5_dma_config = {
-  10, SPC5_ADC_FIFO5_DMA_IRQ_PRIO,
-  NULL, adc_serve_dma_error_irq, &ADCD6
-};
-
-/**
- * @brief   DMA configuration for EQADC RFIFO5.
- */
-static const edma_channel_config_t adc_rfifo5_dma_config = {
-  11, SPC5_ADC_FIFO5_DMA_IRQ_PRIO,
-  adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD6
-};
-#endif /* SPC5_ADC_USE_ADC1_Q5 */
-
-/*===========================================================================*/
-/* Driver local functions and macros.                                        */
-/*===========================================================================*/
-
-/**
- * @brief   Unsigned two's complement.
- *
- * @param[in] n         the value to be complemented
- *
- * @notapi
- */
-#define CPL2(n) ((~(uint32_t)(n)) + 1)
-
-/**
- * @brief   Address of a CFIFO push register.
- *
- * @param[in] fifo      the FIFO identifier
- *
- * @notapi
- */
-#define CFIFO_PUSH_ADDR(fifo) ((uint32_t *)(&EQADC.CFPR[fifo].R))
-
-/**
- * @brief   Address of a RFIFO pop register.
- *
- * @param[in] fifo      the FIFO identifier
- *
- * @notapi
- */
-#define RFIFO_POP_ADDR(fifo) (((uint16_t *)&EQADC.RFPR[fifo].R) + 1)
-
-/**
- * @brief   Enables a CFIFO.
- *
- * @param[in] fifo      the FIFO identifier
- * @param[in] cfcr      CFCR register value
- * @param[in] idcr      IDCR register value
- *
- * @notapi
- */
-static void cfifo_enable(adcfifo_t fifo, uint16_t cfcr, uint16_t idcr) {
-
-  EQADC.CFCR[fifo].R = cfcr;
-  EQADC.IDCR[fifo].R = idcr;
-}
-
-/**
- * @brief   Disables a CFIFO and the associated resources.
- *
- * @param[in] fifo      the FIFO identifier
- *
- * @notapi
- */
-static void cfifo_disable(adcfifo_t fifo) {
-
-  /* Disables the CFIFO.*/
-  EQADC.CFCR[fifo].R = EQADC_CFCR_MODE_DISABLED;
-
-  /* Disables Interrupts and DMAs of the CFIFO.*/
-  EQADC.IDCR[fifo].R = 0;
-
-  /* Waits for the CFIFO to become idle.*/
-  while ((EQADC.CFSR.R & (0xC0000000 >> (fifo * 2))) != 0)
-    ;
-
-  /* Invalidates the CFIFO.*/
-  EQADC.CFCR[fifo].R = EQADC_CFCR_CFINV | EQADC_CFCR_MODE_DISABLED;
-
-  /* Clears all Interrupts and eDMA flags for the CFIFO.*/
-  EQADC.FISR[fifo].R = EQADC_FISR_CLEAR_MASK;
-
-  /* Clears the Tx Count Registers for the CFIFO.*/
-  EQADC.CFTCR[fifo].R = 0;
-}
-
-/**
- * @brief   Pushes a command into the CFIFO0.
- *
- * @param[in] cmd       the command
- *
- * @notapi
- */
-static void cfifo0_push_command(adccommand_t cmd) {
-
-  while (EQADC.FISR[0].B.CFCTR >= 4)
-    ;
-  EQADC.CFPR[0].R = cmd;
-}
-
-/**
- * @brief   Waits until the RFIFO0 contains the specified number of entries.
- *
- * @param[in] n     number of entries
- *
- * @notapi
- */
-static void cfifo0_wait_rfifo(uint32_t n) {
-
-  while (EQADC.FISR[0].B.RFCTR < n)
-    ;
-  EQADC.FISR[0].R = EQADC_FISR_CLEAR_MASK;
-}
-
-/**
- * @brief   Reads a sample from the RFIFO0.
- *
- * @notapi
- */
-#define rfifo0_get_value() (EQADC.RFPR[0].R)
-
-/**
- * @brief   Writes an internal ADC register.
- *
- * @param[in] adc       the ADC unit
- * @param[in] reg       the register index
- * @param[in] value     value to be written into the register
- *
- * @notapi
- */
-#define adc_write_register(adc, reg, value)                                 \
-  cfifo0_push_command(EQADC_RW_WRITE | (adc) | EQADC_RW_REG_ADDR(reg) |     \
-                      EQADC_RW_VALUE(value))
-
-
-/**
- * @brief   Enables both ADCs.
- *
- * @notapi
- */
-static void adc_enable(void) {
-
-  /* Both ADCs must be enabled because this sentence in the reference manual:
-    "Both ADC0 and ADC1 of an eQADC module pair must be enabled before
-     calibrating or using either ADC0 or ADC1 of the pair. Failure to
-     enable both ADC0 and ADC1 of the pair can result in inaccurate
-     conversions.".*/
-  adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_CR,
-                     SPC5_ADC_CR_CLK_PS | ADC_CR_EN);
-  adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_CR,
-                     SPC5_ADC_CR_CLK_PS | ADC_CR_EN);
-}
-
-/**
- * @brief   Disables both ADCs.
- *
- * @notapi
- */
-static void adc_disable(void) {
-
-  adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_CR,
-                     SPC5_ADC_CR_CLK_PS);
-  adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_CR,
-                     SPC5_ADC_CR_CLK_PS);
-}
-
-/**
- * @brief   Calibrates an ADC unit.
- *
- * @param[in] adc       the ADC unit
- *
- * @notapi
- */
-static void adc_calibrate(uint32_t adc) {
-  uint16_t res25, res75;
-  uint32_t gcc, occ;
-
-  /* Starts the calibration, write command messages to sample 25% and
-     75% VREF.*/
-  cfifo0_push_command(0x00002C00 | adc);      /* Vref 25%.*/
-  cfifo0_push_command(0x00002B00 | adc);      /* Vref 75%.*/
-  cfifo0_wait_rfifo(2);
-
-  /* Reads the results and compute calibration register values.*/
-  res25 = rfifo0_get_value();
-  res75 = rfifo0_get_value();
-
-  gcc = 0x08000000UL / ((uint32_t)res75 - (uint32_t)res25);
-  occ = (uint32_t)ADC_IDEAL_RES75_2 - ((gcc * (uint32_t)res75) >> 14);
-
-  /* Loads the gain and offset values (default configuration, 12 bits).*/
-  adc_write_register(adc, ADC_REG_GCCR, gcc);
-  adc_write_register(adc, ADC_REG_OCCR, occ & 0xFFFF);
-
-  /* Loads gain and offset values (alternate configuration 1, 10 bits).*/
-  adc_write_register(adc, ADC_REG_AC1GCCR, gcc);
-  adc_write_register(adc, ADC_REG_AC1OCCR, occ & 0xFFFF);
-
-  /* Loads gain and offset values (alternate configuration 1, 8 bits).*/
-  adc_write_register(adc, ADC_REG_AC2GCCR, gcc);
-  adc_write_register(adc, ADC_REG_AC2OCCR, occ & 0xFFFF);
-}
-
-/**
- * @brief   Calibrates an ADC unit.
- *
- * @param[in] adc       the ADC unit
- *
- * @notapi
- */
-static void adc_setup_resistors(uint32_t adc) {
-  unsigned i;
-
-  for (i = 0; i < 8; i++)
-    adc_write_register(adc, ADC_REG_PUDCR(i), pudcrs[i]);
-}
-
-/**
- * @brief   Shared ISR for RFIFO DMA events.
- *
- * @param[in] channel   the channel number
- * @param[in] p         parameter for the registered function
- *
- * @notapi
- */
-static void adc_serve_rfifo_irq(edma_channel_t channel, void *p) {
-  ADCDriver *adcp = (ADCDriver *)p;
-  edma_tcd_t *tcdp = edmaGetTCD(channel);
-
-  if (adcp->grpp != NULL) {
-    if ((tcdp->word[5] >> 16) != (tcdp->word[7] >> 16)) {
-      /* Half transfer processing.*/
-      _adc_isr_half_code(adcp);
-    }
-    else {
-      /* Re-starting DMA channels if in circular mode.*/
-      if (adcp->grpp->circular) {
-        edmaChannelStart(adcp->rfifo_channel);
-        edmaChannelStart(adcp->cfifo_channel);
-      }
-
-      /* Transfer complete processing.*/
-      _adc_isr_full_code(adcp);
-    }
-  }
-}
-
-/**
- * @brief   Shared ISR for CFIFO/RFIFO DMA error events.
- *
- * @param[in] channel   the channel number
- * @param[in] p         parameter for the registered function
- * @param[in] esr       content of the ESR register
- *
- * @notapi
- */
-static void adc_serve_dma_error_irq(edma_channel_t channel,
-                                    void *p,
-                                    uint32_t esr) {
-  ADCDriver *adcp = (ADCDriver *)p;
-
-  (void)channel;
-  (void)esr;
-
-  _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-  /* FIFOs initially all not in use.*/
-  adc_active_fifos = 0;
-
-#if SPC5_ADC_USE_ADC0_Q0
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-  ADCD1.cfifo_channel = EDMA_ERROR;
-  ADCD1.rfifo_channel = EDMA_ERROR;
-  ADCD1.fifo          = ADC_FIFO_0;
-#endif /* SPC5_ADC_USE_EQADC_Q0 */
-
-#if SPC5_ADC_USE_ADC0_Q1
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD2);
-  ADCD2.cfifo_channel = EDMA_ERROR;
-  ADCD2.rfifo_channel = EDMA_ERROR;
-  ADCD2.fifo          = ADC_FIFO_1;
-#endif /* SPC5_ADC_USE_EQADC_Q1 */
-
-#if SPC5_ADC_USE_ADC0_Q2
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD3);
-  ADCD3.cfifo_channel = EDMA_ERROR;
-  ADCD3.rfifo_channel = EDMA_ERROR;
-  ADCD3.fifo          = ADC_FIFO_2;
-#endif /* SPC5_ADC_USE_EQADC_Q2 */
-
-#if SPC5_ADC_USE_ADC1_Q3
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD4);
-  ADCD4.cfifo_channel = EDMA_ERROR;
-  ADCD4.rfifo_channel = EDMA_ERROR;
-  ADCD4.fifo          = ADC_FIFO_3;
-#endif /* SPC5_ADC_USE_ADC1_Q3 */
-
-#if SPC5_ADC_USE_ADC1_Q4
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD5);
-  ADCD5.cfifo_channel = EDMA_ERROR;
-  ADCD5.rfifo_channel = EDMA_ERROR;
-  ADCD5.fifo          = ADC_FIFO_4;
-#endif /* SPC5_ADC_USE_ADC1_Q4 */
-
-#if SPC5_ADC_USE_ADC1_Q5
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD6);
-  ADCD6.cfifo_channel = EDMA_ERROR;
-  ADCD6.rfifo_channel = EDMA_ERROR;
-  ADCD6.fifo          = ADC_FIFO_5;
-#endif /* SPC5_ADC_USE_ADC1_Q5 */
-
-  /* Temporarily enables CFIFO0 for calibration and initialization.*/
-  cfifo_enable(ADC_FIFO_0, EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWCS, 0);
-  adc_enable();
-
-  /* Calibration of both ADC units, programming alternate configs
-     one and two for 10 and 8 bits operations, setting up pull up/down
-     resistors.*/
-#if SPC5_ADC_USE_ADC0
-  adc_calibrate(EQADC_RW_BN_ADC0);
-  adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_AC1CR, ADC_ACR_RESSEL_10BITS);
-  adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_AC2CR, ADC_ACR_RESSEL_8BITS);
-  adc_setup_resistors(EQADC_RW_BN_ADC0);
-#endif
-#if SPC5_ADC_USE_ADC1
-  adc_calibrate(EQADC_RW_BN_ADC1);
-  adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_AC1CR, ADC_ACR_RESSEL_10BITS);
-  adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_AC2CR, ADC_ACR_RESSEL_8BITS);
-  adc_setup_resistors(EQADC_RW_BN_ADC1);
-#endif
-
-  /* ADCs disabled until the driver is started by the application.*/
-  adc_disable();
-  cfifo_disable(ADC_FIFO_0);
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  chDbgAssert(adc_active_fifos < 6, "adc_lld_start(), #1", "too many FIFOs");
-
-  if (adcp->state == ADC_STOP) {
-    /* Enables the peripheral.*/
-#if SPC5_ADC_USE_ADC0_Q0
-    if (&ADCD1 == adcp) {
-      adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo0_dma_config);
-      adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo0_dma_config);
-      adc_active_fifos++;
-    }
-#endif /* SPC5_ADC_USE_ADC0_Q0 */
-
-#if SPC5_ADC_USE_ADC0_Q1
-    if (&ADCD2 == adcp) {
-      adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo1_dma_config);
-      adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo1_dma_config);
-      adc_active_fifos++;
-    }
-#endif /* SPC5_ADC_USE_ADC0_Q1 */
-
-#if SPC5_ADC_USE_ADC0_Q2
-    if (&ADCD3 == adcp) {
-      adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo2_dma_config);
-      adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo2_dma_config);
-      adc_active_fifos++;
-    }
-#endif /* SPC5_ADC_USE_ADC0_Q2 */
-
-#if SPC5_ADC_USE_ADC1_Q3
-    if (&ADCD4 == adcp) {
-      adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo3_dma_config);
-      adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo3_dma_config);
-      adc_active_fifos++;
-    }
-#endif /* SPC5_ADC_USE_ADC1_Q3 */
-
-#if SPC5_ADC_USE_ADC1_Q4
-    if (&ADCD5 == adcp) {
-      adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo4_dma_config);
-      adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo4_dma_config);
-      adc_active_fifos++;
-    }
-#endif /* SPC5_ADC_USE_ADC1_Q4 */
-
-#if SPC5_ADC_USE_ADC1_Q5
-    if (&ADCD6 == adcp) {
-      adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo5_dma_config);
-      adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo5_dma_config);
-      adc_active_fifos++;
-    }
-#endif /* SPC5_ADC_USE_ADC1_Q5 */
-
-    /* If this is the first FIFO activated then the ADC is enabled.*/
-    if (adc_active_fifos == 1)
-      adc_enable();
-  }
-
-  chDbgAssert((adcp->cfifo_channel != EDMA_ERROR) &&
-              (adcp->rfifo_channel != EDMA_ERROR),
-              "adc_lld_start(), #2", "channel cannot be allocated");
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  chDbgAssert(adc_active_fifos < 6, "adc_lld_stop(), #1", "too many FIFOs");
-
-  if (adcp->state == ADC_READY) {
-    /* Resets the peripheral.*/
-
-    /* Releases the allocated EDMA channels.*/
-    edmaChannelRelease(adcp->cfifo_channel);
-    edmaChannelRelease(adcp->rfifo_channel);
-
-    /* If it is the last active FIFO then the ADC is disable too.*/
-    if (--adc_active_fifos == 0)
-      adc_disable();
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- * @note    Because an HW constraint the number of rows in the samples
- *          array must not be greater than the preconfigured value in
- *          the conversion group.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t bitoff;
-
-  chDbgAssert(adcp->grpp->num_iterations >= adcp->depth,
-              "adc_lld_start_conversion(), #1", "too many elements");
-
-  /* Setting up CFIFO TCD parameters.*/
-  edmaChannelSetup(adcp->cfifo_channel,         /* channel.                 */
-                   adcp->grpp->commands,        /* src.                     */
-                   CFIFO_PUSH_ADDR(adcp->fifo), /* dst.                     */
-                   4,                           /* soff, advance by 4.      */
-                   0,                           /* doff, do not advance.    */
-                   2,                           /* ssize, 32 bits transfers.*/
-                   2,                           /* dsize, 32 bits transfers.*/
-                   4,                           /* nbytes, always four.     */
-                   (uint32_t)adcp->grpp->num_channels *
-                   (uint32_t)adcp->depth,       /* iter.                    */
-                   CPL2((uint32_t)adcp->grpp->num_channels *
-                        (uint32_t)adcp->depth *
-                        sizeof(adccommand_t)),  /* slast.                   */
-                   0,                           /* dlast, no dest.adjust.   */
-                   EDMA_TCD_MODE_DREQ);         /* mode.                    */
-
-  /* Setting up RFIFO TCD parameters.*/
-  edmaChannelSetup(adcp->rfifo_channel,         /* channel.                 */
-                   RFIFO_POP_ADDR(adcp->fifo),  /* src.                     */
-                   adcp->samples,               /* dst.                     */
-                   0,                           /* soff, do not advance.    */
-                   2,                           /* doff, advance by two.    */
-                   1,                           /* ssize, 16 bits transfers.*/
-                   1,                           /* dsize, 16 bits transfers.*/
-                   2,                           /* nbytes, always two.      */
-                   (uint32_t)adcp->grpp->num_channels *
-                   (uint32_t)adcp->depth,       /* iter.                    */
-                   0,                           /* slast, no source adjust. */
-                   CPL2((uint32_t)adcp->grpp->num_channels *
-                        (uint32_t)adcp->depth *
-                        sizeof(adcsample_t)),   /* dlast.                   */
-                   EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END |
-                   ((adcp->depth > 1) ? EDMA_TCD_MODE_INT_HALF: 0));/* mode.*/
-
-  /* HW triggers setup.*/
-  bitoff = 20 + ((uint32_t)adcp->fifo * 2);
-  SIU.ETISR.R = (SIU.ETISR.R & ~(3U << bitoff)) |
-                (adcp->grpp->tsel << bitoff);
-  bitoff = (uint32_t)adcp->fifo * 5;
-  SIU.ISEL3.R = (SIU.ISEL3.R & ~(31U << bitoff)) |
-                (adcp->grpp->etsel << bitoff);
-
-  /* Starting DMA channels.*/
-  edmaChannelStart(adcp->rfifo_channel);
-  edmaChannelStart(adcp->cfifo_channel);
-
-  /* Enabling CFIFO, conversion starts.*/
-  cfifo_enable(adcp->fifo, adcp->grpp->cfcr,
-               EQADC_IDCR_CFFE | EQADC_IDCR_CFFS |
-               EQADC_IDCR_RFDE | EQADC_IDCR_RFDS);
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-  /* Stopping DMA channels.*/
-  edmaChannelStop(adcp->cfifo_channel);
-  edmaChannelStop(adcp->rfifo_channel);
-
-  /* Disabling CFIFO.*/
-  cfifo_disable(adcp->fifo);
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
deleted file mode 100644
index 6be4ca5d4..000000000
--- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
+++ /dev/null
@@ -1,663 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/EQADC_v1/adc_lld.c
- * @brief   SPC5xx low level ADC driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Analog channel identifiers
- * @{
- */
-#define ADC_CHN_AN0                 0U
-#define ADC_CHN_AN1                 1U
-#define ADC_CHN_AN2                 2U
-#define ADC_CHN_AN3                 3U
-#define ADC_CHN_AN4                 4U
-#define ADC_CHN_AN5                 5U
-#define ADC_CHN_AN6                 6U
-#define ADC_CHN_AN7                 7U
-#define ADC_CHN_AN8                 8U
-#define ADC_CHN_AN9                 9U
-#define ADC_CHN_AN10                10U
-#define ADC_CHN_AN11                11U
-#define ADC_CHN_AN12                12U
-#define ADC_CHN_AN13                13U
-#define ADC_CHN_AN14                14U
-#define ADC_CHN_AN15                15U
-#define ADC_CHN_AN16                16U
-#define ADC_CHN_AN17                17U
-#define ADC_CHN_AN18                18U
-#define ADC_CHN_AN19                19U
-#define ADC_CHN_AN20                20U
-#define ADC_CHN_AN21                21U
-#define ADC_CHN_AN22                22U
-#define ADC_CHN_AN23                23U
-#define ADC_CHN_AN24                24U
-#define ADC_CHN_AN25                25U
-#define ADC_CHN_AN26                26U
-#define ADC_CHN_AN27                27U
-#define ADC_CHN_AN28                28U
-#define ADC_CHN_AN29                29U
-#define ADC_CHN_AN30                30U
-#define ADC_CHN_AN31                31U
-#define ADC_CHN_AN32                32U
-#define ADC_CHN_AN33                33U
-#define ADC_CHN_AN34                34U
-#define ADC_CHN_AN35                35U
-#define ADC_CHN_AN36                36U
-#define ADC_CHN_AN37                37U
-#define ADC_CHN_AN38                38U
-#define ADC_CHN_AN39                39U
-#define ADC_CHN_VRH                 40U
-#define ADC_CHN_VRL                 41U
-#define ADC_CHN_VREF50              42U
-#define ADC_CHN_VREF75              43U
-#define ADC_CHN_VREF25              44U
-#define ADC_CHN_BANDGAP             45U
-#define ADC_CHN_DAN0                96U
-#define ADC_CHN_DAN1                97U
-#define ADC_CHN_DAN2                98U
-#define ADC_CHN_DAN3                99U
-#define ADC_CHN_TEMP_SENSOR         128U
-#define ADC_CHN_SPARE               129U
-/** @} */
-
-/**
- * @name    Internal registers indexes
- * @{
- */
-#define ADC_REG_CR                  0x1
-#define ADC_REG_TSCR                0x2
-#define ADC_REG_TBCR                0x3
-#define ADC_REG_GCCR                0x4
-#define ADC_REG_OCCR                0x5
-#define ADC_REG_AC1GCCR             0x31
-#define ADC_REG_AC1OCCR             0x32
-#define ADC_REG_AC2GCCR             0x35
-#define ADC_REG_AC2OCCR             0x36
-#define ADC_REG_AC1CR               0x30
-#define ADC_REG_AC2CR               0x34
-#define ADC_REG_AC3CR               0x38
-#define ADC_REG_AC4CR               0x3C
-#define ADC_REG_AC5CR               0x40
-#define ADC_REG_AC6CR               0x44
-#define ADC_REG_AC7CR               0x48
-#define ADC_REG_AC8CR               0x4C
-#define ADC_REG_PUDCR(n)            (0x70 + (n))
-#define ADC_REG_PUDCR0              0x70UL
-#define ADC_REG_PUDCR1              0x71UL
-#define ADC_REG_PUDCR2              0x72UL
-#define ADC_REG_PUDCR3              0x73UL
-#define ADC_REG_PUDCR4              0x74UL
-#define ADC_REG_PUDCR5              0x75UL
-#define ADC_REG_PUDCR6              0x76UL
-#define ADC_REG_PUDCR7              0x77UL
-/** @} */
-
-/**
- * @name    EQADC IDCR registers definitions
- * @{
- */
-#define EQADC_IDCR_NCIE             (1U << 15)
-#define EQADC_IDCR_TORIE            (1U << 14)
-#define EQADC_IDCR_PIE              (1U << 13)
-#define EQADC_IDCR_EOQIE            (1U << 12)
-#define EQADC_IDCR_CFUIE            (1U << 11)
-#define EQADC_IDCR_CFFE             (1U << 9)
-#define EQADC_IDCR_CFFS             (1U << 8)
-#define EQADC_IDCR_RFOIE            (1U << 3)
-#define EQADC_IDCR_RFDE             (1U << 1)
-#define EQADC_IDCR_RFDS             (1U << 0)
-/** @} */
-
-/**
- * @name    EQADC CFCR registers definitions
- * @{
- */
-#define EQADC_CFCR_CFEEE0           (1U << 12)
-#define EQADC_CFCR_STRME0           (1U << 11)
-#define EQADC_CFCR_SSE              (1U << 10)
-#define EQADC_CFCR_CFINV            (1U << 9)
-#define EQADC_CFCR_MODE_MASK        (15U << 4)
-#define EQADC_CFCR_MODE(n)          ((n) << 4)
-#define EQADC_CFCR_MODE_DISABLED    EQADC_CFCR_MODE(0)
-#define EQADC_CFCR_MODE_SWSS        EQADC_CFCR_MODE(1)
-#define EQADC_CFCR_MODE_HWSS_LL     EQADC_CFCR_MODE(2)
-#define EQADC_CFCR_MODE_HWSS_HL     EQADC_CFCR_MODE(3)
-#define EQADC_CFCR_MODE_HWSS_FE     EQADC_CFCR_MODE(4)
-#define EQADC_CFCR_MODE_HWSS_RE     EQADC_CFCR_MODE(5)
-#define EQADC_CFCR_MODE_HWSS_BE     EQADC_CFCR_MODE(6)
-#define EQADC_CFCR_MODE_SWCS        EQADC_CFCR_MODE(9)
-#define EQADC_CFCR_MODE_HWCS_LL     EQADC_CFCR_MODE(10)
-#define EQADC_CFCR_MODE_HWCS_HL     EQADC_CFCR_MODE(11)
-#define EQADC_CFCR_MODE_HWCS_FE     EQADC_CFCR_MODE(12)
-#define EQADC_CFCR_MODE_HWCS_RE     EQADC_CFCR_MODE(13)
-#define EQADC_CFCR_MODE_HWCS_BE     EQADC_CFCR_MODE(14)
-#define EQADC_CFCR_AMODE0_MASK      (15U << 0)
-#define EQADC_CFCR_AMODE0(n)        ((n) << 0)
-/** @} */
-
-/**
- * @name    EQADC FISR registers definitions
- * @{
- */
-#define EQADC_FISR_POPNXTPTR_MASK   (15U << 0)
-#define EQADC_FISR_RFCTR_MASK       (15U << 4)
-#define EQADC_FISR_TNXTPTR_MASK     (15U << 8)
-#define EQADC_FISR_CFCTR_MASK       (15U << 12)
-#define EQADC_FISR_RFDF             (1U << 17)
-#define EQADC_FISR_RFOF             (1U << 19)
-#define EQADC_FISR_CFFF             (1U << 25)
-#define EQADC_FISR_SSS              (1U << 26)
-#define EQADC_FISR_CFUF             (1U << 27)
-#define EQADC_FISR_EOQF             (1U << 28)
-#define EQADC_FISR_PF               (1U << 29)
-#define EQADC_FISR_TORF             (1U << 30)
-#define EQADC_FISR_NCF              (1U << 31)
-#define EQADC_FISR_CLEAR_MASK       (EQADC_FISR_NCF  | EQADC_FISR_TORF |    \
-                                     EQADC_FISR_PF   | EQADC_FISR_EOQF |    \
-                                     EQADC_FISR_CFUF | EQADC_FISR_RFOF |    \
-                                     EQADC_FISR_RFDF)
-/** @} */
-
-/**
- * @name    EQADC conversion/configuration commands
- * @{
- */
-#define EQADC_CONV_CONFIG_STD   (0U << 0)   /**< @brief Alt.config.1.       */
-#define EQADC_CONV_CONFIG_SEL1  (8U << 0)   /**< @brief Alt.config.1.       */
-#define EQADC_CONV_CONFIG_SEL2  (9U << 0)   /**< @brief Alt.config.2.       */
-#define EQADC_CONV_CONFIG_SEL3  (10U << 0)  /**< @brief Alt.config.3.       */
-#define EQADC_CONV_CONFIG_SEL4  (11U << 0)  /**< @brief Alt.config.4.       */
-#define EQADC_CONV_CONFIG_SEL5  (12U << 0)  /**< @brief Alt.config.5.       */
-#define EQADC_CONV_CONFIG_SEL6  (13U << 0)  /**< @brief Alt.config.6.       */
-#define EQADC_CONV_CONFIG_SEL7  (14U << 0)  /**< @brief Alt.config.7.       */
-#define EQADC_CONV_CONFIG_SEL8  (15U << 0)  /**< @brief Alt.config.8.       */
-#define EQADC_CONV_CHANNEL_MASK (255U << 8) /**< @brief Channel number mask.*/
-#define EQADC_CONV_CHANNEL(n)   ((n) << 8)  /**< @brief Channel number.     */
-#define EQADC_CONV_FMT_RJU      (0U << 16)  /**< @brief Unsigned samples.   */
-#define EQADC_CONV_FMT_RJS      (1U << 16)  /**< @brief Signed samples.     */
-#define EQADC_CONV_TSR          (1U << 17)  /**< @brief Time stamp request. */
-#define EQADC_CONV_LST_MASK     (3U << 18)  /**< @brief Sample time.        */
-#define EQADC_CONV_LST_2        (0U << 18)  /**< @brief 2 clock cycles.     */
-#define EQADC_CONV_LST_8        (1U << 18)  /**< @brief 8 clock cycles.     */
-#define EQADC_CONV_LST_64       (2U << 18)  /**< @brief 64 clock cycles.    */
-#define EQADC_CONV_LST_128      (3U << 18)  /**< @brief 128 clock cycles.   */
-#define EQADC_CONV_MSG_MASK     (15U << 20) /**< @brief Message mask.       */
-#define EQADC_CONV_MSG_RFIFO(n) ((n) << 20) /**< @brief Result in RFIFO0..5.*/
-#define EQADC_CONV_MSG_NULL     (6U << 20)  /**< @brief Null message.       */
-#define EQADC_CONV_CAL          (1U << 24)  /**< @brief Calibrated result.  */
-#define EQADC_CONV_BN_MASK      (1U << 25)  /**< @brief Buffer number mask. */
-#define EQADC_CONV_BN_ADC0      (0U << 25)  /**< @brief ADC0 selection.     */
-#define EQADC_CONV_BN_ADC1      (1U << 25)  /**< @brief ADC1 selection.     */
-#define EQADC_CONV_REP          (1U << 29)  /**< @brief Repeat loop flag.   */
-#define EQADC_CONV_PAUSE        (1U << 30)  /**< @brief Pause flag.         */
-#define EQADC_CONV_EOQ          (1U << 31)  /**< @brief End of queue flag.  */
-/** @} */
-
-/**
- * @name    EQADC read/write commands
- * @{
- */
-#define EQADC_RW_REG_ADDR_MASK  (255U << 0)
-#define EQADC_RW_REG_ADDR(n)    ((n) << 0)
-#define EQADC_RW_VALUE_MASK     (0xFFFF << 8)
-#define EQADC_RW_VALUE(n)       ((n) << 8)
-#define EQADC_RW_WRITE          (0U << 24)
-#define EQADC_RW_READ           (1U << 24)
-#define EQADC_RW_BN_ADC0        (0U << 25)
-#define EQADC_RW_BN_ADC1        (1U << 25)
-#define EQADC_RW_REP            (1U << 29)
-#define EQADC_RW_PAUSE          (1U << 30)
-#define EQADC_RW_EOQ            (1U << 31)
-/** @} */
-
-/**
- * @name    ADC CR register definitions
- * @{
- */
-#define ADC_CR_CLK_PS_MASK      (31U << 0)
-#define ADC_CR_CLK_PS(n)        ((((n) >> 1) - 1) | ((n) & 1 ? ADC_CR_ODD_PS\
-                                                             : 0))
-#define ADC_CR_CLK_SEL          (1U << 5)
-#define ADC_CR_CLK_DTY          (1U << 6)
-#define ADC_CR_ODD_PS           (1U << 7)
-#define ADC_CR_TBSEL_MASK       (3U << 8)
-#define ADC_CR_TBSEL(n)         ((n) << 8)
-#define ADC_CR_EMUX             (1U << 11)
-#define ADC_CR_EN               (1U << 15)
-/** @} */
-
-/**
- * @name    ADC AxCR registers definitions
- * @{
- */
-#define ADC_ACR_PRE_GAIN_MASK   (3U << 0)
-#define ADC_ACR_PRE_GAIN_X1     (0U << 0)
-#define ADC_ACR_PRE_GAIN_X2     (1U << 0)
-#define ADC_ACR_PRE_GAIN_X4     (2U << 0)
-#define ADC_ACR_RESSEL_MASK     (3U << 6)
-#define ADC_ACR_RESSEL_12BITS   (0U << 6)
-#define ADC_ACR_RESSEL_10BITS   (1U << 6)
-#define ADC_ACR_RESSEL_8BITS    (2U << 6)
-/** @} */
-
-/**
- * @name    ADC PUDCRx registers definitions
- * @{
- */
-#define ADC_PUDCR_NONE          0x0000
-#define ADC_PUDCR_UP_200K       0x1100
-#define ADC_PUDCR_UP_100K       0x1200
-#define ADC_PUDCR_UP_5K         0x1300
-#define ADC_PUDCR_DOWN_200K     0x2100
-#define ADC_PUDCR_DOWN_100K     0x2200
-#define ADC_PUDCR_DOWN_5K       0x2300
-#define ADC_PUDCR_UP_DOWN_200K  0x3100
-#define ADC_PUDCR_UP_DOWN_100K  0x3200
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADCD1 driver enable switch.
- * @details If set to @p TRUE the support for ADC0 queue 0 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC0_Q0) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC0_Q0                FALSE
-#endif
-
-/**
- * @brief   ADCD2 driver enable switch.
- * @details If set to @p TRUE the support for ADC0 queue 1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC0_Q1) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC0_Q1                FALSE
-#endif
-
-/**
- * @brief   ADCD3 driver enable switch.
- * @details If set to @p TRUE the support for ADC0 queue 2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC0_Q2) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC0_Q2                FALSE
-#endif
-
-/**
- * @brief   ADCD4 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 queue 3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC1_Q3) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC1_Q3                FALSE
-#endif
-
-/**
- * @brief   ADCD5 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 queue 4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC1_Q4) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC1_Q4                FALSE
-#endif
-
-/**
- * @brief   ADCD6 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 queue 5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ADC_USE_ADC1_Q5) || defined(__DOXYGEN__)
-#define SPC5_ADC_USE_ADC1_Q5                FALSE
-#endif
-
-/**
- * @brief   EQADC CFIFO0 and RFIFO0 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO         12
-#endif
-
-/**
- * @brief   EQADC CFIFO1 and RFIFO1 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO1_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO         12
-#endif
-
-/**
- * @brief   EQADC CFIFO2 and RFIFO2 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO2_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO         12
-#endif
-
-/**
- * @brief   EQADC CFIFO3 and RFIFO3 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO3_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO         12
-#endif
-
-/**
- * @brief   EQADC CFIFO4 and RFIFO4 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO4_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO         12
-#endif
-
-/**
- * @brief   EQADC CFIFO5 and RFIFO5 DMA IRQ priority.
- */
-#if !defined(SPC5_ADC0_FIFO5_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO         12
-#endif
-
-/**
- * @brief   EQADC clock prescaler value.
- */
-#if !defined(SPC5_ADC_CR_CLK_PS) || defined(__DOXYGEN__)
-#define SPC5_ADC_CR_CLK_PS                  ADC_CR_CLK_PS(5)
-#endif
-
-/**
- * @brief   Initialization value for PUDCRx registers.
- */
-#if !defined(SPC5_ADC_PUDCR) || defined(__DOXYGEN__)
-#define SPC5_ADC_PUDCR                      {ADC_PUDCR_NONE,                \
-                                             ADC_PUDCR_NONE,                \
-                                             ADC_PUDCR_NONE,                \
-                                             ADC_PUDCR_NONE,                \
-                                             ADC_PUDCR_NONE,                \
-                                             ADC_PUDCR_NONE,                \
-                                             ADC_PUDCR_NONE,                \
-                                             ADC_PUDCR_NONE}
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EQADC
-#error "EQADC not present in the selected device"
-#endif
-
-#define SPC5_ADC_USE_ADC0                   (SPC5_ADC_USE_ADC0_Q0 ||        \
-                                             SPC5_ADC_USE_ADC0_Q1 ||        \
-                                             SPC5_ADC_USE_ADC0_Q2)
-#define SPC5_ADC_USE_ADC1                   (SPC5_ADC_USE_ADC1_Q3 ||        \
-                                             SPC5_ADC_USE_ADC1_Q4 ||        \
-                                             SPC5_ADC_USE_ADC1_Q5)
-
-#if !SPC5_ADC_USE_ADC0 && !SPC5_ADC_USE_ADC1
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*!
- * @brief   FIFO unit numeric IDs.
- */
-typedef enum {
-  ADC_FIFO_0 = 0,
-  ADC_FIFO_1 = 1,
-  ADC_FIFO_2 = 2,
-  ADC_FIFO_3 = 3,
-  ADC_FIFO_4 = 4,
-  ADC_FIFO_5 = 5
-} adcfifo_t;
-
-/**
- * @brief   ADC command data type.
- */
-typedef uint32_t adccommand_t;
-
-/**
- * @brief   ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_DMAFAILURE = 0                    /**< DMA operations failure.    */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Initialization value for CFCR register.
-   */
-  uint16_t                  cfcr;
-  /**
-   * @brief   SIU ETISR.TSEL value for this queue;
-   */
-  uint8_t                   tsel;
-  /**
-   * @brief   SIU ISEL3.ETSEL value for this queue;
-   */
-  uint8_t                   etsel;
-  /**
-   * @brief   Number of command iterations stored in @p commands.
-   * @note    The total number of array elements must be @p num_channels *
-   *          @p num_iterations.
-   * @note    This fields is the upper limit of the parameter @p n that can
-   *          be passed to the functions @p adcConvert() and
-   *          @p adcStartConversion().
-   */
-  uint32_t                  num_iterations;
-  /**
-   * @brief   Pointer to an array of low level EQADC commands to be pushed
-   *          into the CFIFO during a conversion.
-   */
-  const adccommand_t        *commands;
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Empty in this implementation can be ignored.
- */
-typedef struct {
-  uint32_t                  dummy;
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief   Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief   Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief   Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief   Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief   Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   CFIFO/RFIFO used by this instance.
-   */
-  adcfifo_t                 fifo;
-  /**
-   * @brief   EDMA channel used for the CFIFO.
-   */
-  edma_channel_t            cfifo_channel;
-  /**
-   * @brief   EDMA channel used for the RFIFO.
-   */
-  edma_channel_t            rfifo_channel;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_ADC_USE_ADC0_Q0 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#if SPC5_ADC_USE_ADC0_Q1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD2;
-#endif
-
-#if SPC5_ADC_USE_ADC0_Q2 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD3;
-#endif
-
-#if SPC5_ADC_USE_ADC1_Q3 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD4;
-#endif
-
-#if SPC5_ADC_USE_ADC1_Q4 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD5;
-#endif
-
-#if SPC5_ADC_USE_ADC1_Q5 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD6;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c
deleted file mode 100644
index 3257927c6..000000000
--- a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/ESCI_v1/serial_lld.c
- * @brief   SPC5xx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   eSCI-A serial driver identifier.
- */
-#if SPC5_USE_ESCIA || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/**
- * @brief   eSCI-B serial driver identifier.
- */
-#if SPC5_USE_ESCIB || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Driver default configuration.
- */
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  SD_MODE_NORMAL | SD_MODE_PARITY_NONE
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   eSCI initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void esci_init(SerialDriver *sdp, const SerialConfig *config) {
-  volatile struct ESCI_tag *escip = sdp->escip;
-  uint8_t mode = config->sc_mode;
-
-  escip->CR2.R  = 0;                /* MDIS off.                            */
-  escip->CR1.R  = 0;
-  escip->LCR.R  = 0;
-  escip->CR1.B.SBR = SPC5_SYSCLK / (16 * config->sc_speed);
-  if (mode & SD_MODE_LOOPBACK)
-    escip->CR1.B.LOOPS = 1;
-  switch (mode & SD_MODE_PARITY_MASK) {
-  case SD_MODE_PARITY_ODD:
-    escip->CR1.B.PT = 1;
-  case SD_MODE_PARITY_EVEN:
-    escip->CR1.B.PE = 1;
-    escip->CR1.B.M  = 1;            /* Makes it 8 bits data + 1 bit parity. */
-  default:
-    ;
-  }
-  escip->LPR.R  = 0;
-  escip->CR1.R |= 0x0000002C;       /* RIE, TE, RE to 1.                    */
-  escip->CR2.R  = 0x000F;           /* ORIE, NFIE, FEIE, PFIE to 1.         */
-}
-
-/**
- * @brief   eSCI de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] escip     pointer to an eSCI I/O block
- */
-static void esci_deinit(volatile struct ESCI_tag *escip) {
-
-  escip->LPR.R  = 0;
-  escip->SR.R   = 0xFFFFFFFF;
-  escip->CR1.R  = 0;
-  escip->CR2.R  = 0x8000;           /* MDIS on.                             */
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] sr        eSCI SR register value
- */
-static void set_error(SerialDriver *sdp, uint32_t sr) {
-  flagsmask_t sts = 0;
-
-  if (sr & 0x08000000)
-    sts |= SD_OVERRUN_ERROR;
-  if (sr & 0x04000000)
-    sts |= SD_NOISE_ERROR;
-  if (sr & 0x02000000)
-    sts |= SD_FRAMING_ERROR;
-  if (sr & 0x01000000)
-    sts |= SD_PARITY_ERROR;
-/*  if (sr & 0x00000000)
-    sts |= SD_BREAK_DETECTED;*/
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  volatile struct ESCI_tag *escip = sdp->escip;
-
-  uint32_t sr = escip->SR.R;
-  escip->SR.R = 0x3FFFFFFF;                     /* Does not clear TDRE | TC.*/
-  if (sr & 0x0F000000)                          /* OR | NF | FE | PF.       */
-    set_error(sdp, sr);
-  if (sr & 0x20000000) {                        /* RDRF.                    */
-    chSysLockFromIsr();
-    sdIncomingDataI(sdp, escip->DR.B.D);
-    chSysUnlockFromIsr();
-  }
-  if (escip->CR1.B.TIE && (sr & 0x80000000)) {  /* TDRE.                    */
-    msg_t b;
-    chSysLockFromIsr();
-    b = chOQGetI(&sdp->oqueue);
-    if (b < Q_OK) {
-      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-      escip->CR1.B.TIE = 0;
-    }
-    else {
-      ESCI_A.SR.B.TDRE = 1;
-      escip->DR.R = (uint16_t)b;
-    }
-    chSysUnlockFromIsr();
-  }
-}
-
-#if SPC5_USE_ESCIA || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  if (ESCI_A.SR.B.TDRE) {
-    msg_t b = sdRequestDataI(&SD1);
-    if (b != Q_EMPTY) {
-      ESCI_A.SR.B.TDRE = 1;
-      ESCI_A.CR1.B.TIE = 1;
-      ESCI_A.DR.R = (uint16_t)b;
-    }
-  }
-}
-#endif
-
-#if SPC5_USE_ESCIB || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  if (ESCI_B.SR.B.TDRE) {
-    msg_t b = sdRequestDataI(&SD2);
-    if (b != Q_EMPTY) {
-      ESCI_B.SR.B.TDRE = 1;
-      ESCI_B.CR1.B.TIE = 1;
-      ESCI_B.DR.R = (uint16_t)b;
-    }
-  }
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_USE_ESCIA || defined(__DOXYGEN__)
-#if !defined(SPC5_ESCIA_HANDLER)
-#error "SPC5_ESCIA_HANDLER not defined"
-#endif
-/**
- * @brief   eSCI-A interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ESCIA_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_USE_ESCIB || defined(__DOXYGEN__)
-#if !defined(SPC5_ESCIB_HANDLER)
-#error "SPC5_ESCIB_HANDLER not defined"
-#endif
-/**
- * @brief   eSCI-B interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ESCIB_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if SPC5_USE_ESCIA
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.escip       = &ESCI_A;
-  ESCI_A.CR2.R    = 0x8000;                 /* MDIS ON.                     */
-  INTC.PSR[SPC5_ESCIA_NUMBER].R = SPC5_ESCIA_PRIORITY;
-#endif
-
-#if SPC5_USE_ESCIB
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.escip       = &ESCI_B;
-  ESCI_B.CR2.R    = 0x8000;                 /* MDIS ON.                     */
-  INTC.PSR[SPC5_ESCIB_NUMBER].R = SPC5_ESCIB_PRIORITY;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-  esci_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY)
-    esci_deinit(sdp->escip);
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h
deleted file mode 100644
index b8b29fb99..000000000
--- a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/ESCI_v1/serial_lld.c
- * @brief   SPC5xx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Serial port modes
- * @{
- */
-#define SD_MODE_PARITY_MASK     0x03        /**< @brief Parity field mask.  */
-#define SD_MODE_PARITY_NONE     0x00        /**< @brief No parity.          */
-#define SD_MODE_PARITY_EVEN     0x01        /**< @brief Even parity.        */
-#define SD_MODE_PARITY_ODD      0x02        /**< @brief Odd parity.         */
-
-#define SD_MODE_NORMAL          0x00        /**< @brief Normal operations.  */
-#define SD_MODE_LOOPBACK        0x80        /**< @brief Internal loopback.  */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   eSCI-A driver enable switch.
- * @details If set to @p TRUE the support for eSCI-A is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(SPC5_USE_ESCIA) || defined(__DOXYGEN__)
-#define SPC5_USE_ESCIA                      TRUE
-#endif
-
-/**
- * @brief   eSCI-B driver enable switch.
- * @details If set to @p TRUE the support for eSCI-B is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(SPC5_USE_ESCIB) || defined(__DOXYGEN__)
-#define SPC5_USE_ESCIB                      TRUE
-#endif
-
-/**
- * @brief   eSCI-A interrupt priority level setting.
- */
-#if !defined(SPC_ESCIA_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ESCIA_PRIORITY                 8
-#endif
-
-/**
- * @brief   eSCI-B interrupt priority level setting.
- */
-#if !defined(SPC_ESCIB_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ESCIB_PRIORITY                 8
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if SPC5_USE_ESCIA && !SPC5_HAS_ESCIA
-#error "eSCI-A not present in the selected device"
-#endif
-
-#if SPC5_USE_ESCIB && !SPC5_HAS_ESCIB
-#error "eSCI-B not present in the selected device"
-#endif
-
-#if !SPC5_USE_ESCIA && !SPC5_USE_ESCIB
-#error "SERIAL driver activated but no eSCI peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    This structure content is architecture dependent, each driver
- *          implementation defines its own version and the custom static
- *          initializers.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Mode flags.
-   */
-  uint8_t                   sc_mode;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the volatile eSCI registers block.*/                        \
-  volatile struct ESCI_tag  *escip;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_USE_ESCIA && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if SPC5_USE_ESCIB && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c
deleted file mode 100644
index 625f44d19..000000000
--- a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c
+++ /dev/null
@@ -1,3771 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    FlexCAN_v1/can_lld.c
- * @brief   SPC5xx CAN subsystem low level driver source.
- *
- * @addtogroup CAN
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief CAN1 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__)
-CANDriver CAND1;
-#endif
-
-/** @brief CAN2 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__)
-CANDriver CAND2;
-#endif
-
-/** @brief CAN3 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__)
-CANDriver CAND3;
-#endif
-
-/** @brief CAN4 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__)
-CANDriver CAND4;
-#endif
-
-/** @brief CAN5 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__)
-CANDriver CAND5;
-#endif
-
-/** @brief CAN6 driver identifier.*/
-#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__)
-CANDriver CAND6;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Common TX ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_tx_handler(CANDriver *canp) {
-  uint32_t iflag1, iflag2;
-  (void)iflag2;
-
-  /* No more events until a message is transmitted.*/
-  iflag1 = canp->flexcan->IFRL.R;
-  canp->flexcan->IFRL.R = iflag1 & 0xFFFFFF00;
-
-#if SPC5_CAN_USE_FLEXCAN0 && (SPC5_FLEXCAN0_MB == 64)
-  if(&CAND1 == canp) {
-    iflag2 = canp->flexcan->IFRH.R;
-    canp->flexcan->IFRH.R = canp->flexcan->IFRH.R;
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1 && (SPC5_FLEXCAN1_MB == 64)
-  if(&CAND2 == canp) {
-    iflag2 = canp->flexcan->IFRH.R;
-    canp->flexcan->IFRH.R = canp->flexcan->IFRH.R;
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2 && (SPC5_FLEXCAN2_MB == 64)
-  if(&CAND3 == canp) {
-    iflag2 = canp->flexcan->IFRH.R;
-    canp->flexcan->IFRH.R = canp->flexcan->IFRH.R;
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3 && (SPC5_FLEXCAN3_MB == 64)
-  if(&CAND4 == canp) {
-    iflag2 = canp->flexcan->IFRH.R;
-    canp->flexcan->IFRH.R = canp->flexcan->IFRH.R;
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4 && (SPC5_FLEXCAN4_MB == 64)
-  if(&CAND5 == canp) {
-    iflag2 = canp->flexcan->IFRH.R;
-    canp->flexcan->IFRH.R = canp->flexcan->IFRH.R;
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5 && (SPC5_FLEXCAN5_MB == 64)
-  if(&CAND6 == canp) {
-    iflag2 = canp->flexcan->IFRH.R;
-    canp->flexcan->IFRH.R = canp->flexcan->IFRH.R;
-  }
-#endif
-
-  chSysLockFromISR();
-  while (chSemGetCounterI(&canp->txsem) < 0)
-    chSemSignalI(&canp->txsem);
-
-#if SPC5_CAN_USE_FLEXCAN0 && (SPC5_FLEXCAN0_MB == 32)
-  if(&CAND1 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
-  }
-#elif SPC5_CAN_USE_FLEXCAN0 && (SPC5_FLEXCAN0_MB == 64)
-  if(&CAND1 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1 && (SPC5_FLEXCAN1_MB == 32)
-  if(&CAND2 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
-  }
-#elif SPC5_CAN_USE_FLEXCAN1 && (SPC5_FLEXCAN1_MB == 64)
-  if(&CAND2 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2 && (SPC5_FLEXCAN2_MB == 32)
-  if(&CAND3 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
-  }
-#elif SPC5_CAN_USE_FLEXCAN2 && (SPC5_FLEXCAN2_MB == 64)
-  if(&CAND3 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3 && (SPC5_FLEXCAN3_MB == 32)
-  if(&CAND4 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
-  }
-#elif SPC5_CAN_USE_FLEXCAN3 && (SPC5_FLEXCAN3_MB == 64)
-  if(&CAND4 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4 && (SPC5_FLEXCAN4_MB == 32)
-  if(&CAND5 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
-  }
-#elif SPC5_CAN_USE_FLEXCAN4 && (SPC5_FLEXCAN4_MB == 64)
-  if(&CAND5 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5 && (SPC5_FLEXCAN5_MB == 32)
-  if(&CAND6 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
-  }
-#elif SPC5_CAN_USE_FLEXCAN5 && (SPC5_FLEXCAN5_MB == 64)
-  if(&CAND6 == canp) {
-    chEvtBroadcastFlagsI(&canp->txempty_event, iflag2 | (iflag1 & 0xFFFFFF00));
-  }
-#endif
-
-  chSysUnlockFromISR();
-}
-
-/**
- * @brief   Common RX ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_rx_handler(CANDriver *canp) {
-  uint32_t iflag1;
-
-  iflag1 = canp->flexcan->IFRL.R;
-  if ((iflag1 & 0x000000FF) != 0) {
-    chSysLockFromISR();
-	while (chSemGetCounterI(&canp->rxsem) < 0)
-      chSemSignalI(&canp->rxsem);
-
-    chEvtBroadcastFlagsI(&canp->rxfull_event, iflag1 & 0x000000FF);
-    chSysUnlockFromISR();
-
-    /* Release the mailbox.*/
-    canp->flexcan->IFRL.R = iflag1 & 0x000000FF;
-  }
-}
-
-/**
- * @brief   Common error ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_err_handler(CANDriver *canp) {
-
-  uint32_t esr = canp->flexcan->ESR.R;
-  flagsmask_t flags = 0;
-
-  /* Error event.*/
-  if ((esr & CAN_ESR_TWRN_INT) || (esr & CAN_ESR_RWRN_INT)) {
-    canp->flexcan->ESR.B.TXWRN = 1U;
-    canp->flexcan->ESR.B.RXWRN = 1U;
-    flags |= CAN_LIMIT_WARNING;
-  }
-
-  if (esr & CAN_ESR_BOFF_INT) {
-    canp->flexcan->ESR.B.BOFFINT = 1U;
-    flags |= CAN_BUS_OFF_ERROR;
-  }
-
-  if (esr & CAN_ESR_ERR_INT) {
-    canp->flexcan->ESR.B.ERRINT = 1U;
-    flags |= CAN_FRAMING_ERROR;
-  }
-  chSysLockFromISR();
-  chEvtBroadcastFlagsI(&canp->error_event, flags);
-  chSysUnlockFromISR();
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__)
-#if !SPC5_FLEXCAN0_SHARED_IRQ
-/**
- * @brief   CAN1 RX interrupt handler for MB 0.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_00_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 RX interrupt handler for MB 1.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_01_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 RX interrupt handler for MB 2.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_02_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 RX interrupt handler for MB 3.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_03_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 RX interrupt handler for MB 4.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_04_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 RX interrupt handler for MB 5.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_05_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 RX interrupt handler for MB 6.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_06_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 RX interrupt handler for MB 7.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_07_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 8.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_08_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 9.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_09_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 10.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_10_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 12.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_12_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 13.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_13_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 14.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_14_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN0_MB == 64)
-/**
- * @brief   CAN1 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   CAN1 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-#else
-/**
- * @brief   CAN1 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN0_MB == 64)
-/**
- * @brief   CAN1 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief   CAN1 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief   CAN1 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#endif /* SPC5_CAN_USE_FLEXCAN0 */
-
-#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__)
-#if !SPC5_FLEXCAN1_SHARED_IRQ
-/**
- * @brief   CAN2 RX interrupt handler for MB 0.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_00_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 RX interrupt handler for MB 1.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_01_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 RX interrupt handler for MB 2.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_02_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 RX interrupt handler for MB 3.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_03_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 RX interrupt handler for MB 4.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_04_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 RX interrupt handler for MB 5.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_05_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 RX interrupt handler for MB 6.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_06_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 RX interrupt handler for MB 7.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_07_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 8.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_08_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 9.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_09_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 10.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_10_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 12.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_12_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 13.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_13_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 14.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_14_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN1_MB == 64)
-/**
- * @brief   CAN2 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   CAN2 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-#else
-/**
- * @brief   CAN2 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN1_MB == 64)
-/**
- * @brief   CAN2 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief   CAN2 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief   CAN2 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#endif /* SPC5_CAN_USE_FLEXCAN1 */
-
-#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__)
-#if !SPC5_FLEXCAN2_SHARED_IRQ
-/**
- * @brief   CAN3 RX interrupt handler for MB 0.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_00_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 RX interrupt handler for MB 1.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_01_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 RX interrupt handler for MB 2.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_02_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 RX interrupt handler for MB 3.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_03_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 RX interrupt handler for MB 4.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_04_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 RX interrupt handler for MB 5.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_05_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 RX interrupt handler for MB 6.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_06_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 RX interrupt handler for MB 7.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_07_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 8.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_08_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 9.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_09_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 10.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_10_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 12.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_12_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 13.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_13_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 14.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_14_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN2_MB == 64)
-/**
- * @brief   CAN3 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   CAN3 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-#else
-/**
- * @brief   CAN3 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN2_MB == 64)
-/**
- * @brief   CAN3 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief   CAN3 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief   CAN3 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN3 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#endif /* SPC5_CAN_USE_FLEXCAN2 */
-
-#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__)
-#if !SPC5_FLEXCAN3_SHARED_IRQ
-/**
- * @brief   CAN4 RX interrupt handler for MB 0.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_00_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 RX interrupt handler for MB 1.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_01_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 RX interrupt handler for MB 2.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_02_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 RX interrupt handler for MB 3.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_03_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 RX interrupt handler for MB 4.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_04_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 RX interrupt handler for MB 5.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_05_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 RX interrupt handler for MB 6.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_06_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 RX interrupt handler for MB 7.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_07_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 8.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_08_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 9.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_09_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 10.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_10_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 12.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_12_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 13.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_13_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 14.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_14_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN3_MB == 64)
-/**
- * @brief   CAN4 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   CAN4 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-#else
-/**
- * @brief   CAN4 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN3_MB == 64)
-/**
- * @brief   CAN4 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief   CAN4 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief   CAN4 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN4 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#endif /* SPC5_CAN_USE_FLEXCAN3 */
-
-#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__)
-#if !SPC5_FLEXCAN4_SHARED_IRQ
-/**
- * @brief   CAN5 RX interrupt handler for MB 0.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_00_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 RX interrupt handler for MB 1.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_01_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 RX interrupt handler for MB 2.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_02_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 RX interrupt handler for MB 3.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_03_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 RX interrupt handler for MB 4.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_04_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 RX interrupt handler for MB 5.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_05_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 RX interrupt handler for MB 6.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_06_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 RX interrupt handler for MB 7.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_07_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 8.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_08_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 9.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_09_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 10.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_10_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 12.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_12_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 13.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_13_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 14.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_14_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN4_MB == 64)
-/**
- * @brief   CAN5 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   CAN5 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-#else
-/**
- * @brief   CAN5 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN4_MB == 64)
-/**
- * @brief   CAN5 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief   CAN5 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief   CAN5 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN5 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#endif /* SPC5_CAN_USE_FLEXCAN4 */
-
-#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__)
-#if !SPC5_FLEXCAN5_SHARED_IRQ
-/**
- * @brief   CAN6 RX interrupt handler for MB 0.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_00_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 RX interrupt handler for MB 1.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_01_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 RX interrupt handler for MB 2.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_02_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 RX interrupt handler for MB 3.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_03_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 RX interrupt handler for MB 4.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_04_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 RX interrupt handler for MB 5.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_05_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 RX interrupt handler for MB 6.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_06_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 RX interrupt handler for MB 7.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_07_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 8.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_08_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 9.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_09_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 10.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_10_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 12.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_12_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 13.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_13_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 14.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_14_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN5_MB == 64)
-/**
- * @brief   CAN6 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/**
- * @brief   CAN6 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-#else
-/**
- * @brief   CAN6 TX interrupt handler for MB 8-11.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER) {
-
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 12-15.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 TX interrupt handler for MB 16-31.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if (SPC5_FLEXCAN5_MB == 64)
-/**
- * @brief   CAN6 TX interrupt handler for MB 32-63.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*
- * @brief   CAN6 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief   CAN6 RX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 ESR_ERR_INT interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN6 ESR_BOFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_err_handler(&CAND6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-#endif /* SPC5_CAN_USE_FLEXCAN5 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level CAN driver initialization.
- *
- * @notapi
- */
-void can_lld_init(void) {
-
-#if SPC5_CAN_USE_FLEXCAN0
-  /* Driver initialization.*/
-  canObjectInit(&CAND1);
-  CAND1.flexcan = &SPC5_FLEXCAN_0;
-#if !SPC5_FLEXCAN0_SHARED_IRQ
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_00_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_01_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_02_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_04_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_05_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_06_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_08_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_09_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_10_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_12_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_13_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_14_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-#else
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
-#endif
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN1
-  /* Driver initialization.*/
-  canObjectInit(&CAND2);
-  CAND2.flexcan = &SPC5_FLEXCAN_1;
-#if !SPC5_FLEXCAN1_SHARED_IRQ
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_00_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_01_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_02_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_04_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_05_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_06_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_08_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_09_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_10_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_12_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_13_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_14_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-#else
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
-#endif
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN2
-  /* Driver initialization.*/
-  canObjectInit(&CAND3);
-  CAND3.flexcan = &SPC5_FLEXCAN_2;
-#if !SPC5_FLEXCAN2_SHARED_IRQ
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_00_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_01_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_02_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_04_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_05_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_06_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_08_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_09_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_10_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_12_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_13_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_14_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-#else
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
-#endif
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN3
-  /* Driver initialization.*/
-  canObjectInit(&CAND4);
-  CAND4.flexcan = &SPC5_FLEXCAN_3;
-#if !SPC5_FLEXCAN3_SHARED_IRQ
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_00_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_01_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_02_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_04_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_05_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_06_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_08_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_09_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_10_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_12_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_13_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_14_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-#else
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
-#endif
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN4
-  /* Driver initialization.*/
-  canObjectInit(&CAND5);
-  CAND5.flexcan = &SPC5_FLEXCAN_4;
-#if !SPC5_FLEXCAN4_SHARED_IRQ
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_00_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_01_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_02_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_04_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_05_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_06_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_08_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_09_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_10_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_12_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_13_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_14_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-#else
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
-#endif
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN5
-  /* Driver initialization.*/
-  canObjectInit(&CAND6);
-  CAND6.flexcan = &SPC5_FLEXCAN_5;
-#if !SPC5_FLEXCAN5_SHARED_IRQ
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_00_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_01_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_02_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_04_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_05_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_06_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_08_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_09_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_10_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_12_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_13_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_14_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-#else
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-  INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER].R =
-      SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
-#endif
-#endif
-}
-
-/**
- * @brief   Configures and activates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_start(CANDriver *canp) {
-
-  uint8_t mb_index = 0;
-#if SPC5_CAN_USE_FILTERS
-  uint8_t id = 0;
-#endif
-
-  /* Clock activation.*/
-#if SPC5_CAN_USE_FLEXCAN0
-  /* Set peripheral clock mode.*/
-  if(&CAND1 == canp) {
-    SPC5_FLEXCAN0_ENABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
-  /* Set peripheral clock mode.*/
-  if(&CAND2 == canp) {
-    SPC5_FLEXCAN1_ENABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
-  /* Set peripheral clock mode.*/
-  if(&CAND3 == canp) {
-    SPC5_FLEXCAN2_ENABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
-  /* Set peripheral clock mode.*/
-  if(&CAND4 == canp) {
-    SPC5_FLEXCAN3_ENABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
-  /* Set peripheral clock mode.*/
-  if(&CAND5 == canp) {
-    SPC5_FLEXCAN4_ENABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
-  /* Set peripheral clock mode.*/
-  if(&CAND6 == canp) {
-    SPC5_FLEXCAN5_ENABLE_CLOCK();
-  }
-#endif
-
-  /* Entering initialization mode. */
-  canp->state = CAN_STARTING;
-  canp->flexcan->CR.R |= CAN_CTRL_CLK_SRC;
-  canp->flexcan->MCR.R &= ~CAN_MCR_MDIS;
-
-  /*
-   * Individual filtering per MB, disable frame self reception,
-   * disable the FIFO, enable SuperVisor mode.
-   */
-#if SPC5_CAN_USE_FLEXCAN0
-  if(&CAND1 == canp)
-    canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN0_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN1
-  if(&CAND2 == canp)
-    canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN1_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN2
-  if(&CAND3 == canp)
-    canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN2_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN3
-  if(&CAND4 == canp)
-    canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN3_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN4
-  if(&CAND5 == canp)
-    canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN4_MB - 1);
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN5
-  if(&CAND6 == canp)
-    canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN5_MB - 1);
-#endif
-
-  canp->flexcan->CR.R |= CAN_CTRL_TSYN | CAN_CTRL_RJW(3);
-
-  /* TX MB initialization.*/
-#if SPC5_CAN_USE_FLEXCAN0
-  if(&CAND1 == canp) {
-    for(mb_index = 0; mb_index < (SPC5_FLEXCAN0_MB - CAN_RX_MAILBOXES);
-        mb_index++) {
-      canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
-  if(&CAND2 == canp) {
-    for(mb_index = 0; mb_index < (SPC5_FLEXCAN1_MB - CAN_RX_MAILBOXES);
-        mb_index++) {
-      canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
-  if(&CAND3 == canp) {
-    for(mb_index = 0; mb_index < (SPC5_FLEXCAN2_MB - CAN_RX_MAILBOXES);
-        mb_index++) {
-      canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
-  if(&CAND4 == canp) {
-    for(mb_index = 0; mb_index < (SPC5_FLEXCAN3_MB - CAN_RX_MAILBOXES);
-        mb_index++) {
-      canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
-  if(&CAND5 == canp) {
-    for(mb_index = 0; mb_index < (SPC5_FLEXCAN4_MB - CAN_RX_MAILBOXES);
-        mb_index++) {
-      canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
-  if(&CAND6 == canp) {
-    for(mb_index = 0; mb_index < (SPC5_FLEXCAN5_MB - CAN_RX_MAILBOXES);
-        mb_index++) {
-      canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
-    }
-  }
-#endif
-
-  /* Unlock Message buffers.*/
-  (void) canp->flexcan->TIMER.R;
-
-  /* MCR initialization.*/
-  canp->flexcan->MCR.R |= canp->config->mcr;
-
-  /* CTRL initialization.*/
-  canp->flexcan->CR.R |= canp->config->ctrl;
-
-  /* Interrupt sources initialization.*/
-  canp->flexcan->MCR.R |= CAN_MCR_WRN_EN;
-
-  canp->flexcan->CR.R |= CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK  |
-                         CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK;
-
-#if !SPC5_CAN_USE_FILTERS
-  /* RX MB initialization.*/
-  for(mb_index = 0; mb_index < CAN_RX_MAILBOXES; mb_index++) {
-    canp->flexcan->BUF[mb_index].CS.B.CODE = 0U;
-    if(mb_index < 4) {
-      canp->flexcan->BUF[mb_index].CS.B.IDE = 0U;
-    }
-    else {
-      canp->flexcan->BUF[mb_index].CS.B.IDE = 1U;
-    }
-    canp->flexcan->BUF[mb_index].ID.R = 0U;
-    canp->flexcan->BUF[mb_index].CS.B.CODE = 4U;
-  }
-
-  /* Receive all.*/
-  canp->flexcan->RXGMASK.R = 0x00000000;
-#else
-  for (id = 0; id < CAN_RX_MAILBOXES; id++) {
-    canp->flexcan->BUF[id].CS.B.CODE = 0U;
-    if (canp->config->RxFilter[id].scale) {
-      canp->flexcan->BUF[id].CS.B.IDE = 1U;
-      canp->flexcan->BUF[id].ID.R = canp->config->RxFilter[id].register1;
-    }
-    else {
-      canp->flexcan->BUF[id].CS.B.IDE = 0U;
-      canp->flexcan->BUF[id].ID.B.STD_ID = canp->config->RxFilter[id].register1;
-      canp->flexcan->BUF[id].ID.B.EXT_ID = 0U;
-    }
-    /* RX MB initialization.*/
-    canp->flexcan->BUF[id].CS.B.CODE = 4U;
-  }
-  canp->flexcan->RXGMASK.R = 0x0FFFFFFF;
-#endif
-
-  /* Enable MBs interrupts.*/
-#if SPC5_CAN_USE_FLEXCAN0
-  if(&CAND1 == canp) {
-    if(SPC5_FLEXCAN0_MB == 32) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-    }
-    else if(SPC5_FLEXCAN0_MB == 64) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-      canp->flexcan->IMRH.R = 0xFFFFFFFF;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
-  if(&CAND2 == canp) {
-    if(SPC5_FLEXCAN1_MB == 32) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-    }
-    else if(SPC5_FLEXCAN1_MB == 64) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-      canp->flexcan->IMRH.R = 0xFFFFFFFF;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
-  if(&CAND3 == canp) {
-    if(SPC5_FLEXCAN2_MB == 32) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-    }
-    else if(SPC5_FLEXCAN2_MB == 64) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-      canp->flexcan->IMRH.R = 0xFFFFFFFF;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
-  if(&CAND4 == canp) {
-    if(SPC5_FLEXCAN3_MB == 32) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-    }
-    else if(SPC5_FLEXCAN3_MB == 64) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-      canp->flexcan->IMRH.R = 0xFFFFFFFF;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
-  if(&CAND5 == canp) {
-    if(SPC5_FLEXCAN4_MB == 32) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-    }
-    else if(SPC5_FLEXCAN4_MB == 64) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-      canp->flexcan->IMRH.R = 0xFFFFFFFF;
-    }
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
-  if(&CAND6 == canp) {
-    if(SPC5_FLEXCAN5_MB == 32) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-    }
-    else if(SPC5_FLEXCAN5_MB == 64) {
-      canp->flexcan->IMRL.R = 0xFFFFFFFF;
-      canp->flexcan->IMRH.R = 0xFFFFFFFF;
-    }
-  }
-#endif
-
-  /* CAN BUS synchronization.*/
-  canp->flexcan->MCR.B.HALT = 0;
-}
-
-/**
- * @brief   Deactivates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_stop(CANDriver *canp) {
-
-  /* If in ready state then disables the CAN peripheral.*/
-  if (canp->state == CAN_READY) {
-
-    /* Disable Interrupt sources.*/
-    canp->flexcan->MCR.R &= ~CAN_MCR_WRN_EN;
-    canp->flexcan->CR.R &= ~(CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK  |
-                             CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK);
-    canp->flexcan->IMRL.R = 0x00000000;
-
-    canp->flexcan->MCR.R &= ~CAN_MCR_MDIS;
-
-#if SPC5_CAN_USE_FLEXCAN0
-  /* Set peripheral clock mode.*/
-  if(&CAND1 == canp) {
-    SPC5_FLEXCAN0_DISABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
-  /* Set peripheral clock mode.*/
-  if(&CAND2 == canp) {
-    SPC5_FLEXCAN1_DISABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
-  /* Set peripheral clock mode.*/
-  if(&CAND3 == canp) {
-    SPC5_FLEXCAN2_DISABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
-  /* Set peripheral clock mode.*/
-  if(&CAND4 == canp) {
-    SPC5_FLEXCAN3_DISABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
-  /* Set peripheral clock mode.*/
-  if(&CAND5 == canp) {
-    SPC5_FLEXCAN4_DISABLE_CLOCK();
-  }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
-  /* Set peripheral clock mode.*/
-  if(&CAND6 == canp) {
-    SPC5_FLEXCAN5_DISABLE_CLOCK();
-  }
-#endif
-  }
-}
-
-/**
- * @brief   Determines whether a frame can be transmitted.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return              The queue space availability.
- * @retval FALSE        no space in the transmit queue.
- * @retval TRUE         transmit slot available.
- *
- * @notapi
- */
-bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
-
-  uint8_t mbid = 0;
-
-  if(mailbox == CAN_ANY_MAILBOX) {
-#if SPC5_CAN_USE_FLEXCAN0
-    if(&CAND1 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) {
-        if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
-          return TRUE;
-        }
-      }
-      return FALSE;
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
-    if(&CAND2 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) {
-        if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
-          return TRUE;
-        }
-      }
-      return FALSE;
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
-    if(&CAND3 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) {
-        if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
-          return TRUE;
-        }
-      }
-      return FALSE;
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
-    if(&CAND4 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) {
-        if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
-          return TRUE;
-        }
-      }
-      return FALSE;
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
-    if(&CAND5 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) {
-        if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
-          return TRUE;
-        }
-      }
-      return FALSE;
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
-    if(&CAND6 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) {
-        if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
-          return TRUE;
-        }
-      }
-      return FALSE;
-    }
-#endif
-  }
-  else {
-    return canp->flexcan->BUF[mailbox + 7].CS.B.CODE == 0x08;
-  }
-  return FALSE;
-}
-
-/**
- * @brief   Inserts a frame into the transmit queue.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] ctfp      pointer to the CAN frame to be transmitted
- * @param[in] mailbox   mailbox number,  @p CAN_ANY_MAILBOX for any mailbox
- *
- * @notapi
- */
-void can_lld_transmit(CANDriver *canp,
-                      canmbx_t mailbox,
-                      const CANTxFrame *ctfp) {
-
-  CAN_TxMailBox_TypeDef *tmbp = NULL;
-  uint8_t mbid = 0;
-
-  /* Pointer to a free transmission mailbox.*/
-  if (mailbox == CAN_ANY_MAILBOX) {
-#if SPC5_CAN_USE_FLEXCAN0
-    if(&CAND1 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) {
-        if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
-          tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
-          break;
-        }
-      }
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN1
-    if(&CAND2 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) {
-        if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
-          tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
-          break;
-        }
-      }
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN2
-    if(&CAND3 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) {
-        if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
-          tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
-          break;
-        }
-      }
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN3
-    if(&CAND4 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) {
-        if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
-          tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
-          break;
-        }
-      }
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN4
-    if(&CAND5 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) {
-        if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
-          tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
-          break;
-        }
-      }
-    }
-#endif
-#if SPC5_CAN_USE_FLEXCAN5
-    if(&CAND6 == canp) {
-      for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) {
-        if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
-          tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
-          break;
-        }
-      }
-    }
-#endif
-  }
-  else {
-    tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mailbox + 7];
-  }
-
-  /* Preparing the message.*/
-  if (ctfp->IDE) {
-    tmbp->CS.B.IDE = 1U;
-    tmbp->CS.B.RTR = 0U;
-    tmbp->ID.R = ctfp->EID;
-  }
-  else {
-    tmbp->CS.B.IDE = 0U;
-    tmbp->CS.B.RTR = 0U;
-    tmbp->ID.R = ctfp->SID << 18;
-  }
-  tmbp->CS.B.LENGTH = ctfp->LENGTH;
-  tmbp->DATA[0] = ctfp->data32[0];
-  tmbp->DATA[1] = ctfp->data32[1];
-  tmbp->CS.B.CODE = 0x0C;
-}
-
-/**
- *
- * @brief   Determines whether a frame has been received.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return              The queue space availability.
- * @retval FALSE        no space in the transmit queue.
- * @retval TRUE         transmit slot available.
- *
- * @notapi
- */
-
-bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
-
-  uint8_t mbid = 0;
-  bool_t mb_status = FALSE;
-
-  switch (mailbox) {
-  case CAN_ANY_MAILBOX:
-    for (mbid = 0; mbid < CAN_RX_MAILBOXES; mbid++) {
-      if(canp->flexcan->BUF[mbid].CS.B.CODE == 2U) {
-        mb_status = TRUE;
-      }
-    }
-    return mb_status;
-  case 1:
-    return (canp->flexcan->BUF[0].CS.B.CODE == 2U);
-  case 2:
-    return (canp->flexcan->BUF[1].CS.B.CODE == 2U);
-  case 3:
-    return (canp->flexcan->BUF[2].CS.B.CODE == 2U);
-  case 4:
-    return (canp->flexcan->BUF[3].CS.B.CODE == 2U);
-  case 5:
-    return (canp->flexcan->BUF[4].CS.B.CODE == 2U);
-  case 6:
-    return (canp->flexcan->BUF[5].CS.B.CODE == 2U);
-  case 7:
-    return (canp->flexcan->BUF[6].CS.B.CODE == 2U);
-  case 8:
-    return (canp->flexcan->BUF[7].CS.B.CODE == 2U);
-  default:
-    return FALSE;
-  }
-}
-
-/**
- * @brief   Receives a frame from the input queue.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @param[out] crfp     pointer to the buffer where the CAN frame is copied
- *
- * @notapi
- */
-void can_lld_receive(CANDriver *canp,
-                     canmbx_t mailbox,
-                     CANRxFrame *crfp) {
-
-  uint32_t mbid = 0, index = 0;
-
-  if(mailbox != CAN_ANY_MAILBOX) {
-    mbid = mailbox;
-  }
-  else {
-    for (index = 0; index < CAN_RX_MAILBOXES; index++) {
-      if(canp->flexcan->BUF[index].CS.B.CODE == 2U) {
-        mbid = index;
-        break;
-      }
-    }
-  }
-
-  /* Lock the RX MB.*/
-  (void) canp->flexcan->BUF[mbid].CS.B.CODE;
-
-  /* Fetches the message.*/
-  crfp->data32[0] = canp->flexcan->BUF[mbid].DATA.W[0];
-  crfp->data32[1] = canp->flexcan->BUF[mbid].DATA.W[1];
-
-  /* Decodes the various fields in the RX frame.*/
-  crfp->RTR = canp->flexcan->BUF[mbid].CS.B.RTR;
-  crfp->IDE = canp->flexcan->BUF[mbid].CS.B.IDE;
-  if (crfp->IDE)
-    crfp->EID = canp->flexcan->BUF[mbid].ID.B.EXT_ID;
-  else
-    crfp->SID = canp->flexcan->BUF[mbid].ID.B.STD_ID;
-  crfp->LENGTH = canp->flexcan->BUF[mbid].CS.B.LENGTH;
-  crfp->TIME = canp->flexcan->BUF[mbid].CS.B.TIMESTAMP;
-
-  /* Unlock the RX MB.*/
-  (void) canp->flexcan->TIMER.R;
-
-  /* Reconfigure the RX MB in empty status.*/
-  canp->flexcan->BUF[mbid].CS.B.CODE = 4U;
-}
-
-#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
-/**
- * @brief   Enters the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_sleep(CANDriver *canp) {
-
-  /*canp->can->MCR |= CAN_MCR_SLEEP;*/
-}
-
-/**
- * @brief   Enforces leaving the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_wakeup(CANDriver *canp) {
-
-  /*canp->can->MCR &= ~CAN_MCR_SLEEP;*/
-}
-#endif /* CAN_USE_SLEEP_MODE */
-
-#endif /* HAL_USE_CAN */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h
deleted file mode 100644
index ad67c97da..000000000
--- a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h
+++ /dev/null
@@ -1,520 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    FlexCAN_v1/can_lld.h
- * @brief   SPC5xx CAN subsystem low level driver header.
- *
- * @addtogroup CAN
- * @{
- */
-
-#ifndef _CAN_LLD_H_
-#define _CAN_LLD_H_
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-#include "spc5_flexcan.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   This switch defines whether the driver implementation supports
- *          a low power switch mode with an automatic wakeup feature.
- */
-#define CAN_SUPPORTS_SLEEP          FALSE
-
-/**
- * @brief   This implementation supports 24 transmit mailboxes.
- */
-#define CAN_TX_MAILBOXES            24
-
-/**
- * @brief   This implementation supports one FIFO receive mailbox.
- */
-#define CAN_RX_MAILBOXES            8
-
-/**
- * @brief   This implementation supports eight FIFO receive filters.
- */
-#define SPC5_CAN_MAX_FILTERS        8
-
-/**
- * @brief   Enable filters.
- */
-#define SPC5_CAN_FILTER_ON          1
-
-/**
- * @brief   Disable filters.
- */
-#define SPC5_CAN_FILTER_OFF         0
-/**
- * @name    CAN registers helper macros
- * @{
- */
-#define CAN_MCR_MAXMB(n)            (n)
-#define CAN_MCR_AEN                 (1 << 12)
-#define CAN_MCR_LPRIO_EN            (1 << 13)
-#define CAN_MCR_BCC                 (1 << 16)
-#define CAN_MCR_SRX_DIS             (1 << 17)
-#define CAN_MCR_LPM_ACK             (1 << 20)
-#define CAN_MCR_WRN_EN              (1 << 21)
-#define CAN_MCR_SUPV                (1 << 23)
-#define CAN_MCR_FRZ_ACK             (1 << 24)
-#define CAN_MCR_WAK_MSK             (1 << 26)
-#define CAN_MCR_NOT_RDY             (1 << 27)
-#define CAN_MCR_HALT                (1 << 28)
-#define CAN_MCR_FEN                 (1 << 29)
-#define CAN_MCR_FRZ                 (1 << 30)
-#define CAN_MCR_MDIS                (1 << 31)
-
-#define CAN_CTRL_PROPSEG(n)         (n)
-#define CAN_CTRL_LOM                (1 << 3)
-#define CAN_CTRL_TSYN               (1 << 5)
-#define CAN_CTRL_BOFF_REC           (1 << 6)
-#define CAN_CTRL_SMP                (1 << 7)
-#define CAN_CTRL_RWRN_MSK           (1 << 10)
-#define CAN_CTRL_TWRN_MSK           (1 << 11)
-#define CAN_CTRL_LPB                (1 << 12)
-#define CAN_CTRL_CLK_SRC            (1 << 13)
-#define CAN_CTRL_ERR_MSK            (1 << 14)
-#define CAN_CTRL_BOFF_MSK           (1 << 15)
-#define CAN_CTRL_PSEG2(n)           ((n) << 16)
-#define CAN_CTRL_PSEG1(n)           ((n) << 19)
-#define CAN_CTRL_RJW(n)             ((n) << 22)
-#define CAN_CTRL_PRESDIV(n)         ((n) << 24)
-
-#define CAN_IDE_STD                 0           /**< @brief Standard id.    */
-#define CAN_IDE_EXT                 1           /**< @brief Extended id.    */
-
-#define CAN_RTR_DATA                0           /**< @brief Data frame.     */
-#define CAN_RTR_REMOTE              1           /**< @brief Remote frame.   */
-
-#define CAN_ESR_ERR_INT             (1 << 1)
-#define CAN_ESR_BOFF_INT            (1 << 2)
-#define CAN_ESR_TWRN_INT            (1 << 14)
-#define CAN_ESR_RWRN_INT            (1 << 15)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   CAN1 driver enable switch.
- * @details If set to @p TRUE the support for CAN1 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN0) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN0               FALSE
-#endif
-
-/**
- * @brief   CAN2 driver enable switch.
- * @details If set to @p TRUE the support for CAN2 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN1) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN1               FALSE
-#endif
-
-/**
- * @brief   CAN3 driver enable switch.
- * @details If set to @p TRUE the support for CAN3 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN2) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN2               FALSE
-#endif
-
-/**
- * @brief   CAN4 driver enable switch.
- * @details If set to @p TRUE the support for CAN4 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN3) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN3               FALSE
-#endif
-
-/**
- * @brief   CAN5 driver enable switch.
- * @details If set to @p TRUE the support for CAN5 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN4) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN4               FALSE
-#endif
-
-/**
- * @brief   CAN6 driver enable switch.
- * @details If set to @p TRUE the support for CAN6 is included.
- */
-#if !defined(SPC5_CAN_USE_FLEXCAN5) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FLEXCAN5               FALSE
-#endif
-
-/**
- * @brief   CAN1 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN0_IRQ_PRIORITY      11
-#endif
-/** @} */
-
-/**
- * @brief   CAN2 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN1_IRQ_PRIORITY      11
-#endif
-/** @} */
-
-/**
- * @brief   CAN3 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN2_IRQ_PRIORITY      11
-#endif
-/** @} */
-
-/**
- * @brief   CAN4 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN3_IRQ_PRIORITY      11
-#endif
-/** @} */
-
-/**
- * @brief   CAN5 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN4_IRQ_PRIORITY      11
-#endif
-/** @} */
-
-/**
- * @brief   CAN6 interrupt priority level setting.
- */
-#if !defined(SPC5_CAN_FLEXCAN5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_CAN_FLEXCAN5_IRQ_PRIORITY      11
-#endif
-/** @} */
-
-/**
- * @brief   CAN filters enable setting.
- */
-#if !defined(SPC5_CAN_USE_FILTERS) || defined(__DOXYGEN__)
-#define SPC5_CAN_USE_FILTERS                FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if SPC5_CAN_USE_FLEXCAN0 && !SPC5_HAS_FLEXCAN0
-#error "CAN1 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN1 && !SPC5_HAS_FLEXCAN1
-#error "CAN2 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN2 && !SPC5_HAS_FLEXCAN2
-#error "CAN3 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN3 && !SPC5_HAS_FLEXCAN3
-#error "CAN4 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN4 && !SPC5_HAS_FLEXCAN4
-#error "CAN5 not present in the selected device"
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN5 && !SPC5_HAS_FLEXCAN5
-#error "CAN6 not present in the selected device"
-#endif
-
-#if !SPC5_CAN_USE_FLEXCAN0 && !SPC5_CAN_USE_FLEXCAN1                        \
-    && !SPC5_CAN_USE_FLEXCAN2 && !SPC5_CAN_USE_FLEXCAN3                     \
-    && !SPC5_CAN_USE_FLEXCAN4 && !SPC5_CAN_USE_FLEXCAN5
-#error "CAN driver activated but no CAN peripheral assigned"
-#endif
-
-#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
-#error "CAN sleep mode not supported in this architecture"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a transmission mailbox index.
- */
-typedef uint32_t canmbx_t;
-
-/**
- * @brief   CAN TX MB structure.
- */
-typedef struct {
-  union {
-    vuint32_t R;
-    struct {
-      vuint8_t:4;
-      vuint8_t CODE:4;
-      vuint8_t:1;
-      vuint8_t SRR:1;
-      vuint8_t IDE:1;
-      vuint8_t RTR:1;
-      vuint8_t LENGTH:4;
-      vuint16_t TIMESTAMP:16;
-    } B;
-  } CS;
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint8_t PRIO:3;
-      vuint32_t ID:29;
-    } B;
-  } ID;
-  vuint32_t DATA[2];     /* Data buffer in words (32 bits) */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief   CAN transmission frame.
- * @note    Accessing the frame data as word16 or word32 is not portable because
- *          machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
-  struct {
-    uint8_t                 LENGTH:4;       /**< @brief Data length.        */
-    uint8_t                 RTR:1;          /**< @brief Frame type.         */
-    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t              SID:11;         /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t              EID:29;         /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t                 data8[8];       /**< @brief Frame data.         */
-    uint16_t                data16[4];      /**< @brief Frame data.         */
-    uint32_t                data32[2];      /**< @brief Frame data.         */
-  };
-} CANTxFrame;
-
-/**
- * @brief   CAN received frame.
- * @note    Accessing the frame data as word16 or word32 is not portable because
- *          machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
-  struct {
-    uint16_t                TIME;           /**< @brief Time stamp.         */
-  };
-  struct {
-    uint8_t                 LENGTH:4;       /**< @brief Data length.        */
-    uint8_t                 RTR:1;          /**< @brief Frame type.         */
-    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t              SID:11;         /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t              EID:29;         /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t                 data8[8];       /**< @brief Frame data.         */
-    uint16_t                data16[4];      /**< @brief Frame data.         */
-    uint32_t                data32[2];      /**< @brief Frame data.         */
-  };
-} CANRxFrame;
-
-/**
- * @brief   CAN filter.
- * @note    Refer to the SPC5 reference manual for info about filters.
- */
-typedef struct {
-  /**
-   * @brief   Filter scale.
-   * @note    This bit represents the EXT bit associated to this
-   *          filter (0=standard ID mode, 1=extended ID mode).
-   */
-  uint32_t                  scale:1;
-  /**
-   * @brief   Filter register (identifier).
-   */
-  uint32_t                  register1;
-} CANFilter;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   CAN MCR register initialization data.
-   * @note    Some bits in this register are enforced by the driver regardless
-   *          their status in this field.
-   */
-  uint32_t                  mcr;
-  /**
-   * @brief   CAN CTRL register initialization data.
-   * @note    Some bits in this register are enforced by the driver regardless
-   *          their status in this field.
-   */
-  uint32_t                  ctrl;
-#if SPC5_CAN_USE_FILTERS
-  /**
-   * @brief   CAN filters structure.
-   */
-  CANFilter                 RxFilter[CAN_RX_MAILBOXES];
-#endif
-} CANConfig;
-
-/**
- * @brief   Structure representing an CAN driver.
- */
-typedef struct {
-  /**
-   * @brief   Driver state.
-   */
-  canstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const CANConfig           *config;
-  /**
-   * @brief   Transmission queue semaphore.
-   */
-  Semaphore                 txsem;
-  /**
-   * @brief   Receive queue semaphore.
-   */
-  Semaphore                 rxsem;
-  /**
-   * @brief   One or more frames become available.
-   * @note    After broadcasting this event it will not be broadcasted again
-   *          until the received frames queue has been completely emptied. It
-   *          is <b>not</b> broadcasted for each received frame. It is
-   *          responsibility of the application to empty the queue by
-   *          repeatedly invoking @p chReceive() when listening to this event.
-   *          This behavior minimizes the interrupt served by the system
-   *          because CAN traffic.
-   * @note    The flags associated to the listeners will indicate which
-   *          receive mailboxes become non-empty.
-   */
-  EventSource               rxfull_event;
-  /**
-   * @brief   One or more transmission mailbox become available.
-   * @note    The flags associated to the listeners will indicate which
-   *          transmit mailboxes become empty.
-   *
-   */
-  EventSource               txempty_event;
-  /**
-   * @brief   A CAN bus error happened.
-   * @note    The flags associated to the listeners will indicate the
-   *          error(s) that have occurred.
-   */
-  EventSource               error_event;
-#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
-  /**
-   * @brief   Entering sleep state event.
-   */
-  EventSource               sleep_event;
-  /**
-   * @brief   Exiting sleep state event.
-   */
-  EventSource               wakeup_event;
-#endif /* CAN_USE_SLEEP_MODE */
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Pointer to the CAN registers.
-   */
-  volatile struct spc5_flexcan *flexcan;
-} CANDriver;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_CAN_USE_FLEXCAN0 && !defined(__DOXYGEN__)
-extern CANDriver CAND1;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN1 && !defined(__DOXYGEN__)
-extern CANDriver CAND2;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN2 && !defined(__DOXYGEN__)
-extern CANDriver CAND3;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN3 && !defined(__DOXYGEN__)
-extern CANDriver CAND4;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN4 && !defined(__DOXYGEN__)
-extern CANDriver CAND5;
-#endif
-
-#if SPC5_CAN_USE_FLEXCAN5 && !defined(__DOXYGEN__)
-extern CANDriver CAND6;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void can_lld_init(void);
-  void can_lld_start(CANDriver *canp);
-  void can_lld_stop(CANDriver *canp);
-  bool_t can_lld_is_tx_empty(CANDriver *canp,
-                             canmbx_t mailbox);
-  void can_lld_transmit(CANDriver *canp,
-                        canmbx_t mailbox,
-                        const CANTxFrame *crfp);
-  bool_t can_lld_is_rx_nonempty(CANDriver *canp,
-                                canmbx_t mailbox);
-  void can_lld_receive(CANDriver *canp,
-                       canmbx_t mailbox,
-                       CANRxFrame *ctfp);
-#if CAN_USE_SLEEP_MODE
-  void can_lld_sleep(CANDriver *canp);
-  void can_lld_wakeup(CANDriver *canp);
-#endif /* CAN_USE_SLEEP_MODE */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_CAN */
-
-#endif /* _CAN_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h
deleted file mode 100644
index 580f78827..000000000
--- a/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h
+++ /dev/null
@@ -1,442 +0,0 @@
-/*
- * Licensed under ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- *        http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file    FlexCAN_v1/spc5_flexcan.h
- * @brief   SPC5xx FlexCAN header file.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _SPC5_FLEXCAN_H_
-#define _SPC5_FLEXCAN_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPC5 FlexCAN registers block.
- * @note    Redefined from the SPC5 headers because the non uniform
- *          declaration of the SubModules registers among the various
- *          sub-families.
- */
-struct FLEXCAN_BUFFER_t {
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t:4;
-          vuint32_t CODE:4;
-            vuint32_t:1;
-          vuint32_t SRR:1;
-          vuint32_t IDE:1;
-          vuint32_t RTR:1;
-          vuint32_t LENGTH:4;
-          vuint32_t TIMESTAMP:16;
-      } B;
-  } CS;
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t PRIO:3;
-          vuint32_t STD_ID:11;
-          vuint32_t EXT_ID:18;
-      } B;
-  } ID;
-
-  union {
-      /*vuint8_t  B[8]; *//* Data buffer in Bytes (8 bits) */
-      /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
-      vuint32_t W[2];     /* Data buffer in words (32 bits) */
-      /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
-  } DATA;
-
-};                          /* end of FLEXCAN_BUF_t */
-
-struct FLEXCAN_RXFIFO_BUFFER_t {
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t:9;
-          vuint32_t SRR:1;
-          vuint32_t IDE:1;
-          vuint32_t RTR:1;
-          vuint32_t LENGTH:4;
-          vuint32_t TIMESTAMP:16;
-      } B;
-  } CS;
-
-  union {
-      vuint32_t R;
-      struct {
-  vuint32_t:3;
-          vuint32_t STD_ID:11;
-          vuint32_t EXT_ID:18;
-      } B;
-  } ID;
-
-  union {
-      /*vuint8_t  B[8]; *//* Data buffer in Bytes (8 bits) */
-      /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
-      vuint32_t W[2];     /* Data buffer in words (32 bits) */
-      /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
-  } DATA;
-
-  uint32_t FLEXCAN_RXFIFO_reserved[20];   /* {0x00E0-0x0090}/0x4 = 0x14 */
-
-  union {
-      vuint32_t R;
-  } IDTABLE[8];
-
-};                          /* end of FLEXCAN_RXFIFO_t */
-
-struct spc5_flexcan {
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t MDIS:1;
-          vuint32_t FRZ:1;
-          vuint32_t FEN:1;
-          vuint32_t HALT:1;
-          vuint32_t NOTRDY:1;
-          vuint32_t WAKMSK:1;
-          vuint32_t SOFTRST:1;
-          vuint32_t FRZACK:1;
-          vuint32_t SUPV:1;
-          vuint32_t SLFWAK:1;
-          vuint32_t WRNEN:1;
-          vuint32_t LPMACK:1;
-          vuint32_t WAKSRC:1;
-          vuint32_t:1;
-          vuint32_t SRXDIS:1;
-          vuint32_t BCC:1;
-            vuint32_t:2;
-          vuint32_t LPRIO_EN:1;
-          vuint32_t AEN:1;
-            vuint32_t:2;
-          vuint32_t IDAM:2;
-            vuint32_t:2;
-          vuint32_t MAXMB:6;
-      } B;
-  } MCR;                  /* Module Configuration Register */
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t PRESDIV:8;
-          vuint32_t RJW:2;
-          vuint32_t PSEG1:3;
-          vuint32_t PSEG2:3;
-          vuint32_t BOFFMSK:1;
-          vuint32_t ERRMSK:1;
-          vuint32_t CLKSRC:1;
-          vuint32_t LPB:1;
-          vuint32_t TWRNMSK:1;
-          vuint32_t RWRNMSK:1;
-            vuint32_t:2;
-          vuint32_t SMP:1;
-          vuint32_t BOFFREC:1;
-          vuint32_t TSYN:1;
-          vuint32_t LBUF:1;
-          vuint32_t LOM:1;
-          vuint32_t PROPSEG:3;
-      } B;
-  } CR;                   /* Control Register */
-
-  union {
-      vuint32_t R;
-  } TIMER;                /* Free Running Timer */
-
-  uint32_t FLEXCAN_reserved1;
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t MI:32;
-      } B;
-  } RXGMASK;              /* RX Global Mask */
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t MI:32;
-      } B;
-  } RX14MASK;             /* RX 14 Mask */
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t MI:32;
-      } B;
-  } RX15MASK;             /* RX 15 Mask */
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t:16;
-          vuint32_t RXECNT:8;
-          vuint32_t TXECNT:8;
-      } B;
-  } ECR;                  /* Error Counter Register */
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t:14;
-          vuint32_t TWRNINT:1;
-          vuint32_t RWRNINT:1;
-          vuint32_t BIT1ERR:1;
-          vuint32_t BIT0ERR:1;
-          vuint32_t ACKERR:1;
-          vuint32_t CRCERR:1;
-          vuint32_t FRMERR:1;
-          vuint32_t STFERR:1;
-          vuint32_t TXWRN:1;
-          vuint32_t RXWRN:1;
-          vuint32_t IDLE:1;
-          vuint32_t TXRX:1;
-          vuint32_t FLTCONF:2;
-            vuint32_t:1;
-          vuint32_t BOFFINT:1;
-          vuint32_t ERRINT:1;
-          vuint32_t WAKINT:1;
-      } B;
-  } ESR;                  /* Error and Status Register */
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t BUF63M:1;
-          vuint32_t BUF62M:1;
-          vuint32_t BUF61M:1;
-          vuint32_t BUF60M:1;
-          vuint32_t BUF59M:1;
-          vuint32_t BUF58M:1;
-          vuint32_t BUF57M:1;
-          vuint32_t BUF56M:1;
-          vuint32_t BUF55M:1;
-          vuint32_t BUF54M:1;
-          vuint32_t BUF53M:1;
-          vuint32_t BUF52M:1;
-          vuint32_t BUF51M:1;
-          vuint32_t BUF50M:1;
-          vuint32_t BUF49M:1;
-          vuint32_t BUF48M:1;
-          vuint32_t BUF47M:1;
-          vuint32_t BUF46M:1;
-          vuint32_t BUF45M:1;
-          vuint32_t BUF44M:1;
-          vuint32_t BUF43M:1;
-          vuint32_t BUF42M:1;
-          vuint32_t BUF41M:1;
-          vuint32_t BUF40M:1;
-          vuint32_t BUF39M:1;
-          vuint32_t BUF38M:1;
-          vuint32_t BUF37M:1;
-          vuint32_t BUF36M:1;
-          vuint32_t BUF35M:1;
-          vuint32_t BUF34M:1;
-          vuint32_t BUF33M:1;
-          vuint32_t BUF32M:1;
-      } B;
-  } IMRH;                 /* Interruput Masks Register */
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t BUF31M:1;
-          vuint32_t BUF30M:1;
-          vuint32_t BUF29M:1;
-          vuint32_t BUF28M:1;
-          vuint32_t BUF27M:1;
-          vuint32_t BUF26M:1;
-          vuint32_t BUF25M:1;
-          vuint32_t BUF24M:1;
-          vuint32_t BUF23M:1;
-          vuint32_t BUF22M:1;
-          vuint32_t BUF21M:1;
-          vuint32_t BUF20M:1;
-          vuint32_t BUF19M:1;
-          vuint32_t BUF18M:1;
-          vuint32_t BUF17M:1;
-          vuint32_t BUF16M:1;
-          vuint32_t BUF15M:1;
-          vuint32_t BUF14M:1;
-          vuint32_t BUF13M:1;
-          vuint32_t BUF12M:1;
-          vuint32_t BUF11M:1;
-          vuint32_t BUF10M:1;
-          vuint32_t BUF09M:1;
-          vuint32_t BUF08M:1;
-          vuint32_t BUF07M:1;
-          vuint32_t BUF06M:1;
-          vuint32_t BUF05M:1;
-          vuint32_t BUF04M:1;
-          vuint32_t BUF03M:1;
-          vuint32_t BUF02M:1;
-          vuint32_t BUF01M:1;
-          vuint32_t BUF00M:1;
-      } B;
-  } IMRL;                 /* Interruput Masks Register */
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t BUF63I:1;
-          vuint32_t BUF62I:1;
-          vuint32_t BUF61I:1;
-          vuint32_t BUF60I:1;
-          vuint32_t BUF59I:1;
-          vuint32_t BUF58I:1;
-          vuint32_t BUF57I:1;
-          vuint32_t BUF56I:1;
-          vuint32_t BUF55I:1;
-          vuint32_t BUF54I:1;
-          vuint32_t BUF53I:1;
-          vuint32_t BUF52I:1;
-          vuint32_t BUF51I:1;
-          vuint32_t BUF50I:1;
-          vuint32_t BUF49I:1;
-          vuint32_t BUF48I:1;
-          vuint32_t BUF47I:1;
-          vuint32_t BUF46I:1;
-          vuint32_t BUF45I:1;
-          vuint32_t BUF44I:1;
-          vuint32_t BUF43I:1;
-          vuint32_t BUF42I:1;
-          vuint32_t BUF41I:1;
-          vuint32_t BUF40I:1;
-          vuint32_t BUF39I:1;
-          vuint32_t BUF38I:1;
-          vuint32_t BUF37I:1;
-          vuint32_t BUF36I:1;
-          vuint32_t BUF35I:1;
-          vuint32_t BUF34I:1;
-          vuint32_t BUF33I:1;
-          vuint32_t BUF32I:1;
-      } B;
-  } IFRH;                 /* Interruput Flag Register */
-
-  union {
-      vuint32_t R;
-      struct {
-          vuint32_t BUF31I:1;
-          vuint32_t BUF30I:1;
-          vuint32_t BUF29I:1;
-          vuint32_t BUF28I:1;
-          vuint32_t BUF27I:1;
-          vuint32_t BUF26I:1;
-          vuint32_t BUF25I:1;
-          vuint32_t BUF24I:1;
-          vuint32_t BUF23I:1;
-          vuint32_t BUF22I:1;
-          vuint32_t BUF21I:1;
-          vuint32_t BUF20I:1;
-          vuint32_t BUF19I:1;
-          vuint32_t BUF18I:1;
-          vuint32_t BUF17I:1;
-          vuint32_t BUF16I:1;
-          vuint32_t BUF15I:1;
-          vuint32_t BUF14I:1;
-          vuint32_t BUF13I:1;
-          vuint32_t BUF12I:1;
-          vuint32_t BUF11I:1;
-          vuint32_t BUF10I:1;
-          vuint32_t BUF09I:1;
-          vuint32_t BUF08I:1;
-          vuint32_t BUF07I:1;
-          vuint32_t BUF06I:1;
-          vuint32_t BUF05I:1;
-          vuint32_t BUF04I:1;
-          vuint32_t BUF03I:1;
-          vuint32_t BUF02I:1;
-          vuint32_t BUF01I:1;
-          vuint32_t BUF00I:1;
-      } B;
-  } IFRL;                 /* Interruput Flag Register */
-
-  uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */
-
-/****************************************************************************/
-/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure     */
-/****************************************************************************/
-      /* Standard Buffer Structure */
-      struct FLEXCAN_BUFFER_t BUF[64];
-
-      /* RX FIFO and Buffer Structure */
-      /*struct FLEXCAN_RXFIFO_BUFFER_t RXFIFO;
-      struct FLEXCAN_BUFFER_t BUF[56];*/
-/****************************************************************************/
-
-      uint32_t FLEXCAN_reserved3[256];        /* {0x0880-0x0480}/0x4 = 0x100 */
-
-      union {
-          vuint32_t R;
-          struct {
-              vuint32_t MI:32;
-          } B;
-      } RXIMR[64];            /* RX Individual Mask Registers */
-
-  };                          /* end of FLEXCAN_tag */
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    FlexCAN units references
- * @{
- */
-#if SPC5_HAS_FLEXCAN0 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_0      (*(volatile struct spc5_flexcan *)0xFFFC0000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN1 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_1      (*(volatile struct spc5_flexcan *)0xFFFC4000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN2 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_2      (*(volatile struct spc5_flexcan *)0xFFFC8000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN3 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_3      (*(volatile struct spc5_flexcan *)0xFFFCC000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN4 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_4      (*(volatile struct spc5_flexcan *)0xFFFD0000UL)
-#endif
-
-#if SPC5_HAS_FLEXCAN5 || defined(__DOXYGEN__)
-#define SPC5_FLEXCAN_5      (*(volatile struct spc5_flexcan *)0xFFFD4000UL)
-#endif
-/** @} */
-
-#endif /* _SPC5_FLEXCAN_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
deleted file mode 100644
index 7a92b1044..000000000
--- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
+++ /dev/null
@@ -1,1776 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    FlexPWM_v1/pwm_lld.c
- * @brief   SPC5xx low level PWM driver code.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PWMD1 driver identifier.
- * @note    The driver PWMD1 allocates the complex timer TIM1 when enabled.
- */
-#if SPC5_PWM_USE_SMOD0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief   PWMD2 driver identifier.
- * @note    The driver PWMD2 allocates the timer TIM2 when enabled.
- */
-#if SPC5_PWM_USE_SMOD1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief   PWMD3 driver identifier.
- * @note    The driver PWMD3 allocates the timer TIM3 when enabled.
- */
-#if SPC5_PWM_USE_SMOD2 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief   PWMD4 driver identifier.
- * @note    The driver PWMD4 allocates the timer TIM4 when enabled.
- */
-#if SPC5_PWM_USE_SMOD3 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/**
- * @brief   PWMD5 driver identifier.
- * @note    The driver PWMD5 allocates the timer TIM5 when enabled.
- */
-#if SPC5_PWM_USE_SMOD4 || defined(__DOXYGEN__)
-PWMDriver PWMD5;
-#endif
-
-/**
- * @brief   PWMD6 driver identifier.
- * @note    The driver PWMD6 allocates the timer TIM6 when enabled.
- */
-#if SPC5_PWM_USE_SMOD5 || defined(__DOXYGEN__)
-PWMDriver PWMD6;
-#endif
-
-/**
- * @brief   PWMD7 driver identifier.
- * @note    The driver PWMD7 allocates the timer TIM7 when enabled.
- */
-#if SPC5_PWM_USE_SMOD6 || defined(__DOXYGEN__)
-PWMDriver PWMD7;
-#endif
-
-/**
- * @brief   PWMD8 driver identifier.
- * @note    The driver PWMD8 allocates the timer TIM8 when enabled.
- */
-#if SPC5_PWM_USE_SMOD7 || defined(__DOXYGEN__)
-PWMDriver PWMD8;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Number of active FlexPWM0 submodules.
- */
-static uint32_t flexpwm_active_submodules0;
-
-/**
- * @brief   Number of active FlexPWM1 submodules.
- */
-static uint32_t flexpwm_active_submodules1;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Configures and activates the PWM peripheral submodule.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] sid    PWM submodule identifier
- *
- * @notapi
- */
-void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
-  pwmcnt_t pwmperiod;
-  uint32_t psc;
-
-  /* Clears Status Register.*/
-  pwmp->flexpwmp->SUB[sid].STS.R = 0xFFFF;
-
-  /* Clears LDOK and initializes the registers.*/
-  pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U << sid;
-
-  /* Setting PWM clock frequency and submodule prescaler.*/
-  psc = SPC5_FLEXPWM0_CLK / pwmp->config->frequency;
-
-  chDbgAssert((psc <= 0xFFFF) &&
-              (((psc) * pwmp->config->frequency) == SPC5_FLEXPWM0_CLK) &&
-              ((psc == 1) || (psc == 2) || (psc == 4) || (psc == 8) ||
-               (psc == 16) || (psc == 32) ||
-               (psc == 64) || (psc == 128)),
-              "pwm_lld_start_submodule(), #1", "invalid frequency");
-
-  switch (psc) {
-  case 1:
-    pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_1;
-    break;
-  case 2:
-    pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_2;
-    break;
-  case 4:
-    pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_4;
-    break;
-  case 8:
-    pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_8;
-    break;
-  case 16:
-    pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_16;
-    break;
-  case 32:
-    pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_32;
-    break;
-  case 64:
-    pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_64;
-    break;
-  case 128:
-    pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = SPC5_FLEXPWM_PSC_128;
-    break;
-  }
-
-  /* Disables PWM FAULT function. */
-  pwmp->flexpwmp->SUB[sid].DISMAP.R = 0;
-  pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 1U;
-
-  /* Sets PWM period.*/
-  pwmperiod = pwmp->period;
-  pwmp->flexpwmp->SUB[sid].INIT.R = ~(pwmperiod / 2) + 1U;
-  pwmp->flexpwmp->SUB[sid].VAL[0].R = 0;
-  pwmp->flexpwmp->SUB[sid].VAL[1].R = pwmperiod / 2;
-
-  /* Sets the submodule channels.*/
-  switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-  case PWM_ALIGN_EDGE:
-    /* Setting reloads.*/
-    pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 0;
-    pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 1;
-
-    /* Setting active front of PWM channels.*/
-    pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(pwmperiod / 2) + 1U;
-    break;
-  case PWM_ALIGN_CENTER:
-    /* Setting reloads.*/
-    pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 1;
-    pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 0;
-    break;
-  default:
-    ;
-  }
-
-  /* Polarities setup.*/
-  switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) {
-  case PWM_OUTPUT_ACTIVE_LOW:
-    pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;
-
-    /* Enables CHA mask and CHA.*/
-    pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
-    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid;
-
-    break;
-  case PWM_OUTPUT_ACTIVE_HIGH:
-    pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 0;
-
-    /* Enables CHA mask and CHA.*/
-    pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
-    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid;
-
-    break;
-  case PWM_OUTPUT_DISABLED:
-    /* Enables CHA mask.*/
-    pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
-
-    break;
-  default:
-    ;
-  }
-  switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) {
-  case PWM_OUTPUT_ACTIVE_LOW:
-    pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;
-
-    /* Enables CHB mask and CHB.*/
-    pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
-    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid;
-
-    break;
-  case PWM_OUTPUT_ACTIVE_HIGH:
-    pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 0;
-
-    /* Enables CHB mask and CHB.*/
-    pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
-    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid;
-
-    break;
-  case PWM_OUTPUT_DISABLED:
-    /* Enables CHB mask.*/
-    pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
-
-    break;
-  default:
-    ;
-  }
-
-  /* Complementary output setup.*/
-  switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
-  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
-    chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW,
-                "pwm_lld_start_submodule(), #2",
-                "the PWM chB must be set in PWM_OUTPUT_ACTIVE_LOW");
-    pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;
-    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
-    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid;
-    break;
-  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
-    chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_HIGH,
-                "pwm_lld_start_submodule(), #3",
-                "the PWM chB must be set in PWM_OUTPUT_ACTIVE_HIGH");
-    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
-    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= 1U << sid;
-    break;
-  default:
-    ;
-  }
-
-  switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
-  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
-    chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW,
-                "pwm_lld_start_submodule(), #4",
-                "the PWM chA must be set in PWM_OUTPUT_ACTIVE_LOW");
-    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
-    pwmp->flexpwmp->MCTRL.B.IPOL &= ~ (1U << sid);
-    pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;
-    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid;
-    break;
-  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
-    chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH,
-                "pwm_lld_start_submodule(), #5",
-                "the PWM chA must be set in PWM_OUTPUT_ACTIVE_HIGH");
-    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
-    pwmp->flexpwmp->MCTRL.B.IPOL |= 1U << sid;
-    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= 1U << sid;
-    break;
-  default:
-    ;
-  }
-
-  /* Sets the INIT and MASK registers.*/
-  pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U;
-  pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;
-
-  /* Updates SMOD registers and starts SMOD.*/
-  pwmp->flexpwmp->MCTRL.B.LDOK |= 1U << sid;
-  pwmp->flexpwmp->MCTRL.B.RUN |= 1U << sid;
-}
-
-/**
- * @brief   Enables a PWM channel of a submodule.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- * @param[in] sid       PWM submodule id
- *
- * @notapi
- */
-void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
-                                  pwmchannel_t channel,
-                                  pwmcnt_t width, uint8_t sid) {
-  pwmcnt_t pwmperiod;
-  int16_t nwidth;
-  pwmperiod = pwmp->period;
-  nwidth = width - (pwmperiod / 2);
-
-  /* Clears LDOK.*/
-  pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U << sid;
-
-  /* Active the width interrupt.*/
-  if (channel == 0) {
-    if (pwmp->config->channels[0].callback != NULL) {
-      if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x08) == 0) {
-        pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE |= 0x08;
-      }
-    }
-
-    /* Sets the channel width.*/
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-      if (nwidth >= 0)
-        pwmp->flexpwmp->SUB[sid].VAL[3].R = nwidth;
-      else
-        pwmp->flexpwmp->SUB[sid].VAL[3].R = ~((pwmperiod / 2) - width) + 1U;
-      break;
-    case PWM_ALIGN_CENTER:
-      pwmp->flexpwmp->SUB[sid].VAL[3].R = width / 2;
-      pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(width / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-
-    /* Removes the channel mask if it is necessary.*/
-    if ((pwmp->flexpwmp->MASK.B.MASKA & (1U << sid)) == 1)
-      pwmp->flexpwmp->MASK.B.MASKA &= ~ (1U << sid);
-
-    if ((pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) {
-      pwmp->flexpwmp->MASK.B.MASKB &= ~ (1U << sid);
-    }
-  }
-  /* Active the width interrupt.*/
-  else if (channel == 1) {
-    if (pwmp->config->channels[1].callback != NULL) {
-      if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x20) == 0) {
-        pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE |= 0x20;
-      }
-    }
-    /* Sets the channel width.*/
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-      if (nwidth >= 0)
-        pwmp->flexpwmp->SUB[sid].VAL[5].R = nwidth;
-      else
-        pwmp->flexpwmp->SUB[sid].VAL[5].R = ~((pwmperiod / 2) - width) + 1U;
-      break;
-    case PWM_ALIGN_CENTER:
-      pwmp->flexpwmp->SUB[sid].VAL[5].R = width / 2;
-      pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(width / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-
-    /* Removes the channel mask if it is necessary.*/
-    if ((pwmp->flexpwmp->MASK.B.MASKB & (1U << sid)) == 1)
-      pwmp->flexpwmp->MASK.B.MASKB &= ~ (1U << sid);
-
-    if ((pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) {
-      pwmp->flexpwmp->MASK.B.MASKA &= ~ (1U << sid);
-    }
-  }
-
-  /* Active the periodic interrupt.*/
-  if (pwmp->flexpwmp->SUB[sid].INTEN.B.RIE != 1U) {
-    if (pwmp->config->callback != NULL) {
-      pwmp->flexpwmp->SUB[sid].INTEN.B.RIE = 1;
-    }
-  }
-
-  /* Sets the MASK registers.*/
-  pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U;
-  pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;
-
-  /* Forces reload of the VALUE registers.*/
-  pwmp->flexpwmp->MCTRL.B.LDOK |= 1U << sid;
-}
-
-/**
- * @brief   Disables a PWM channel of a submodule.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] sid       PWM submodule id
- *
- * @notapi
- */
-void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,
-                                   pwmchannel_t channel,
-                                   uint8_t sid) {
-
-  pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U << sid;
-
-  /* Disable the width interrupt.*/
-  if (channel == 0) {
-    if (pwmp->config->channels[0].callback != NULL) {
-      if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x08) == 1) {
-        pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE &= 0x37;
-      }
-    }
-
-    /* Active the channel mask.*/
-    if ((pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) {
-      pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
-      pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
-    }
-    else
-      pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
-  }
-  /* Disable the width interrupt.*/
-  else if (channel == 1) {
-    if (pwmp->config->channels[1].callback != NULL) {
-      if ((pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE & 0x20) == 1) {
-        pwmp->flexpwmp->SUB[sid].INTEN.B.CMPIE &= 0x1F;
-      }
-    }
-
-    /* Active the channel mask.*/
-    if ((pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) != 0) {
-      pwmp->flexpwmp->MASK.B.MASKA |= 1U << sid;
-      pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
-    }
-    else
-      pwmp->flexpwmp->MASK.B.MASKB |= 1U << sid;
-  }
-
-  /* Sets the MASK registers.*/
-  pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U;
-  pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;
-
-  /* Disable RIE interrupt to prevent reload interrupt.*/
-  if ((pwmp->flexpwmp->MASK.B.MASKA & (1U << sid)) &&
-      (pwmp->flexpwmp->MASK.B.MASKB & (1U << sid)) == 1) {
-    pwmp->flexpwmp->SUB[sid].INTEN.B.RIE = 0;
-
-    /* Clear the reload flag.*/
-    pwmp->flexpwmp->SUB[sid].STS.B.RF = 1U;
-    }
-
-  pwmp->flexpwmp->MCTRL.B.LDOK |= (1U << sid);
-}
-
-/**
- * @brief   Common SMOD0...SMOD7 IRQ handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
-  uint16_t sr;
-
-#if SPC5_PWM_USE_SMOD0
-  if (&PWMD1 == pwmp) {
-    sr = pwmp->flexpwmp->SUB[0].STS.R & pwmp->flexpwmp->SUB[0].INTEN.R;
-    if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
-      pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x08;
-      pwmp->config->channels[0].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
-      pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x20;
-      pwmp->config->channels[1].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
-      pwmp->flexpwmp->SUB[0].STS.B.RF = 1U;
-      pwmp->config->callback(pwmp);
-    }
-  }
-#endif
-#if SPC5_PWM_USE_SMOD1
-  if (&PWMD2 == pwmp) {
-    sr = pwmp->flexpwmp->SUB[1].STS.R & pwmp->flexpwmp->SUB[1].INTEN.R;
-    if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
-      pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x08;
-      pwmp->config->channels[0].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
-      pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x20;
-      pwmp->config->channels[1].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
-      pwmp->flexpwmp->SUB[1].STS.B.RF = 1U;
-      pwmp->config->callback(pwmp);
-    }
-  }
-#endif
-#if SPC5_PWM_USE_SMOD2
-  if (&PWMD3 == pwmp) {
-    sr = pwmp->flexpwmp->SUB[2].STS.R & pwmp->flexpwmp->SUB[2].INTEN.R;
-    if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
-      pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x08;
-      pwmp->config->channels[0].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
-      pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x20;
-      pwmp->config->channels[1].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
-      pwmp->flexpwmp->SUB[2].STS.B.RF = 1U;
-      pwmp->config->callback(pwmp);
-    }
-  }
-#endif
-#if SPC5_PWM_USE_SMOD3
-  if (&PWMD4 == pwmp) {
-    sr = pwmp->flexpwmp->SUB[3].STS.R & pwmp->flexpwmp->SUB[3].INTEN.R;
-    if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
-      pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x08;
-      pwmp->config->channels[0].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
-      pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x20;
-      pwmp->config->channels[1].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
-      pwmp->flexpwmp->SUB[3].STS.B.RF = 1U;
-      pwmp->config->callback(pwmp);
-    }
-  }
-#endif
-#if SPC5_PWM_USE_SMOD4
-  if (&PWMD5 == pwmp) {
-    sr = pwmp->flexpwmp->SUB[0].STS.R & pwmp->flexpwmp->SUB[0].INTEN.R;
-    if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
-      pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x08;
-      pwmp->config->channels[0].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
-      pwmp->flexpwmp->SUB[0].STS.B.CMPF |= 0x20;
-      pwmp->config->channels[1].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
-      pwmp->flexpwmp->SUB[0].STS.B.RF = 1U;
-      pwmp->config->callback(pwmp);
-    }
-  }
-#endif
-#if SPC5_PWM_USE_SMOD5
-  if (&PWMD6 == pwmp) {
-    sr = pwmp->flexpwmp->SUB[1].STS.R & pwmp->flexpwmp->SUB[1].INTEN.R;
-    if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
-      pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x08;
-      pwmp->config->channels[0].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
-      pwmp->flexpwmp->SUB[1].STS.B.CMPF |= 0x20;
-      pwmp->config->channels[1].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
-      pwmp->flexpwmp->SUB[1].STS.B.RF = 1U;
-      pwmp->config->callback(pwmp);
-    }
-  }
-#endif
-#if SPC5_PWM_USE_SMOD6
-  if (&PWMD7 == pwmp) {
-    sr = pwmp->flexpwmp->SUB[2].STS.R & pwmp->flexpwmp->SUB[2].INTEN.R;
-    if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
-      pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x08;
-      pwmp->config->channels[0].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
-      pwmp->flexpwmp->SUB[2].STS.B.CMPF |= 0x20;
-      pwmp->config->channels[1].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
-      pwmp->flexpwmp->SUB[2].STS.B.RF = 1U;
-      pwmp->config->callback(pwmp);
-    }
-  }
-#endif
-#if SPC5_PWM_USE_SMOD7
-  if (&PWMD8 == pwmp) {
-    sr = pwmp->flexpwmp->SUB[3].STS.R & pwmp->flexpwmp->SUB[3].INTEN.R;
-    if ((sr & SPC5_FLEXPWM_STS_CMPF3) != 0) {
-      pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x08;
-      pwmp->config->channels[0].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_CMPF5) != 0) {
-      pwmp->flexpwmp->SUB[3].STS.B.CMPF |= 0x20;
-      pwmp->config->channels[1].callback(pwmp);
-    }
-    if ((sr & SPC5_FLEXPWM_STS_RF) != 0) {
-      pwmp->flexpwmp->SUB[3].STS.B.RF = 1U;
-      pwmp->config->callback(pwmp);
-    }
-  }
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_SMOD0 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM0_RF0_HANDLER)
-#error "SPC5_FLEXPWM0_RF0_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM0-SMOD0 RF0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF0_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM0_COF0_HANDLER)
-#error "SPC5_FLEXPWM0_COF0_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM0-SMOD0 COF0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF0_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD1 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM0_RF1_HANDLER)
-#error "SPC5_FLEXPWM0_RF1_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM0-SMOD1 RF1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM0_COF1_HANDLER)
-#error "SPC5_FLEXPWM0_COF1_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM0-SMOD1 COF1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD2 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM0_RF2_HANDLER)
-#error "SPC5_FLEXPWM0_RF2_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM0-SMOD2 RF2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM0_COF2_HANDLER)
-#error "SPC5_FLEXPWM0_COF2_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM0-SMOD2 COF2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD3 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM0_RF3_HANDLER)
-#error "SPC5_FLEXPWM0_RF3_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM0-SMOD1 RF3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_RF3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM0_COF3_HANDLER)
-#error "SPC5_FLEXPWM0_COF3_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM0-SMOD1 COF3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM0_COF3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD4 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM1_RF0_HANDLER)
-#error "SPC5_FLEXPWM0_RF1_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM1-SMOD0 RF0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF0_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD5);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM1_COF0_HANDLER)
-#error "SPC5_FLEXPWM1_COF0_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM1-SMOD0 COF0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF0_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD5 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM1_RF1_HANDLER)
-#error "SPC5_FLEXPWM1_RF1_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM1-SMOD1 RF1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD6);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM1_COF1_HANDLER)
-#error "SPC5_FLEXPWM1_COF1_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM1-SMOD1 COF1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD6 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM1_RF2_HANDLER)
-#error "SPC5_FLEXPWM1_RF2_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM1-SMOD2 RF2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD7);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM1_COF2_HANDLER)
-#error "SPC5_FLEXPWM1_COF2_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM1-SMOD2 COF2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD7);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_PWM_USE_SMOD7 || defined(__DOXYGEN__)
-#if !defined(SPC5_FLEXPWM1_RF3_HANDLER)
-#error "SPC5_FLEXPWM1_RF3_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM1-SMOD3 RF3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_RF3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD8);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_FLEXPWM1_COF3_HANDLER)
-#error "SPC5_FLEXPWM1_COF3_HANDLER not defined"
-#endif
-/**
- * @brief   FlexPWM1-SMOD3 COF3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_FLEXPWM1_COF3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD8);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-  /* FlexPWM initially all not in use.*/
-  flexpwm_active_submodules0 = 0;
-  flexpwm_active_submodules1 = 0;
-
-#if (SPC5_PWM_USE_SMOD0)
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD1);
-  PWMD1.flexpwmp = &SPC5_FLEXPWM_0;
-  INTC.PSR[SPC5_FLEXPWM0_RF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_COF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_CAF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD1)
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD2);
-  PWMD2.flexpwmp = &SPC5_FLEXPWM_0;
-  INTC.PSR[SPC5_FLEXPWM0_RF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_COF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_CAF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD2)
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD3);
-  PWMD3.flexpwmp = &SPC5_FLEXPWM_0;
-  INTC.PSR[SPC5_FLEXPWM0_RF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_COF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_CAF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD3)
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD4);
-  PWMD4.flexpwmp = &SPC5_FLEXPWM_0;
-  INTC.PSR[SPC5_FLEXPWM0_RF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_COF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_CAF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_FFLAG_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM0_REF_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD4)
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD5);
-  PWMD5.flexpwmp = &SPC5_FLEXPWM_1;
-  INTC.PSR[SPC5_FLEXPWM1_RF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_COF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_CAF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD5)
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD6);
-  PWMD6.flexpwmp = &SPC5_FLEXPWM_1;
-  INTC.PSR[SPC5_FLEXPWM1_RF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_COF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_CAF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD6)
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD7);
-  PWMD7.flexpwmp = &SPC5_FLEXPWM_1;
-  INTC.PSR[SPC5_FLEXPWM1_RF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_COF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_CAF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
-#endif
-
-#if (SPC5_PWM_USE_SMOD7)
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD8);
-  PWMD8.flexpwmp = &SPC5_FLEXPWM_1;
-  INTC.PSR[SPC5_FLEXPWM1_RF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_COF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_CAF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_FFLAG_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
-  INTC.PSR[SPC5_FLEXPWM1_REF_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
-#endif
-}
-
-/**
- * @brief   Configures and activates the PWM peripheral.
- * @note    Starting a driver that is already in the @p PWM_READY state
- *          disables all the active channels.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-
-  chDbgAssert(flexpwm_active_submodules0 < 5,
-              "pwm_lld_start(), #1", "too many submodules");
-  chDbgAssert(flexpwm_active_submodules1 < 5,
-              "pwm_lld_start(), #2", "too many submodules");
-
-  if (pwmp->state == PWM_STOP) {
-#if SPC5_PWM_USE_SMOD0
-    if (&PWMD1 == pwmp) {
-      flexpwm_active_submodules0++;
-    }
-#endif /* SPC5_PWM_USE_SMOD0 */
-
-#if SPC5_PWM_USE_SMOD1
-    if (&PWMD2 == pwmp) {
-      flexpwm_active_submodules0++;
-    }
-#endif /* SPC5_PWM_USE_SMOD1 */
-
-#if SPC5_PWM_USE_SMOD2
-    if (&PWMD3 == pwmp) {
-      flexpwm_active_submodules0++;
-    }
-#endif /* SPC5_PWM_USE_SMOD2 */
-
-#if SPC5_PWM_USE_SMOD3
-    if (&PWMD4 == pwmp) {
-      flexpwm_active_submodules0++;
-    }
-#endif /* SPC5_PWM_USE_SMOD3 */
-
-#if SPC5_PWM_USE_SMOD4
-    if (&PWMD5 == pwmp) {
-      flexpwm_active_submodules1++;
-    }
-#endif /* SPC5_PWM_USE_SMOD4 */
-
-#if SPC5_PWM_USE_SMOD5
-    if (&PWMD6 == pwmp) {
-      flexpwm_active_submodules1++;
-    }
-#endif /* SPC5_PWM_USE_SMOD5 */
-
-#if SPC5_PWM_USE_SMOD6
-    if (&PWMD7 == pwmp) {
-      flexpwm_active_submodules1++;
-    }
-#endif /* SPC5_PWM_USE_SMOD6 */
-
-#if SPC5_PWM_USE_SMOD7
-    if (&PWMD8 == pwmp) {
-      flexpwm_active_submodules1++;
-    }
-#endif /* SPC5_PWM_USE_SMOD7 */
-
-    /**
-     * If this is the first FlexPWM0 submodule
-     * activated then the FlexPWM0 is enabled.
-     */
-#if SPC5_PWM_USE_FLEXPWM0
-    /* Set Peripheral Clock.*/
-    if (flexpwm_active_submodules0 == 1) {
-      halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL,
-          SPC5_PWM_FLEXPWM0_START_PCTL);
-    }
-#endif
-
-#if SPC5_PWM_USE_FLEXPWM1
-    /* Set Peripheral Clock.*/
-    if (flexpwm_active_submodules1 == 1) {
-      halSPCSetPeripheralClockMode(SPC5_FLEXPWM1_PCTL,
-          SPC5_PWM_FLEXPWM1_START_PCTL);
-    }
-#endif
-
-#if SPC5_PWM_USE_SMOD0
-    if (&PWMD1 == pwmp) {
-      pwm_lld_start_submodule(pwmp, 0);
-    }
-#endif
-#if SPC5_PWM_USE_SMOD1
-    if (&PWMD2 == pwmp) {
-      pwm_lld_start_submodule(pwmp, 1);
-    }
-#endif
-#if SPC5_PWM_USE_SMOD2
-    if (&PWMD3 == pwmp) {
-      pwm_lld_start_submodule(pwmp, 2);
-    }
-#endif
-#if SPC5_PWM_USE_SMOD3
-    if (&PWMD4 == pwmp) {
-      pwm_lld_start_submodule(pwmp, 3);
-    }
-#endif
-#if SPC5_PWM_USE_SMOD4
-    if (&PWMD5 == pwmp) {
-      pwm_lld_start_submodule(pwmp, 0);
-    }
-#endif
-#if SPC5_PWM_USE_SMOD5
-    if (&PWMD6 == pwmp) {
-      pwm_lld_start_submodule(pwmp, 1);
-    }
-#endif
-#if SPC5_PWM_USE_SMOD6
-    if (&PWMD7 == pwmp) {
-      pwm_lld_start_submodule(pwmp, 2);
-    }
-#endif
-#if SPC5_PWM_USE_SMOD7
-    if (&PWMD8 == pwmp) {
-      pwm_lld_start_submodule(pwmp, 3);
-    }
-#endif
-  }
-  else {
-    /* Driver re-configuration scenario, it must be stopped first.*/
-#if SPC5_PWM_USE_SMOD0
-    if (&PWMD1 == pwmp) {
-      /* Disable the interrupts.*/
-      pwmp->flexpwmp->SUB[0].INTEN.R = 0;
-
-      /* Disable the submodule.*/
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE;
-
-      /* Active the submodule masks.*/
-      pwmp->flexpwmp->MASK.B.MASKA &= 0xE;
-      pwmp->flexpwmp->MASK.B.MASKB &= 0xE;
-
-      /* Sets the MASK registers.*/
-      pwmp->flexpwmp->SUB[0].CTRL2.B.FRCEN = 1U;
-      pwmp->flexpwmp->SUB[0].CTRL2.B.FORCE = 1U;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD1
-    if (&PWMD2 == pwmp) {
-      /* Disable the interrupts.*/
-      pwmp->flexpwmp->SUB[1].INTEN.R = 0;
-
-      /* Disable the submodule.*/
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD;
-
-      /* Active the submodule masks.*/
-      pwmp->flexpwmp->MASK.B.MASKA &= 0xD;
-      pwmp->flexpwmp->MASK.B.MASKB &= 0xD;
-
-      /* Sets the MASK registers.*/
-      pwmp->flexpwmp->SUB[1].CTRL2.B.FRCEN = 1U;
-      pwmp->flexpwmp->SUB[1].CTRL2.B.FORCE = 1U;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD2
-    if (&PWMD3 == pwmp) {
-      /* Disable the interrupts.*/
-      pwmp->flexpwmp->SUB[2].INTEN.R = 0;
-
-      /* Disable the submodule.*/
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB;
-
-      /* Active the submodule masks.*/
-      pwmp->flexpwmp->MASK.B.MASKA &= 0xB;
-      pwmp->flexpwmp->MASK.B.MASKB &= 0xB;
-
-      /* Sets the MASK registers.*/
-      pwmp->flexpwmp->SUB[2].CTRL2.B.FRCEN = 1U;
-      pwmp->flexpwmp->SUB[2].CTRL2.B.FORCE = 1U;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD3
-    if (&PWMD4 == pwmp) {
-      /* Disable the interrupts.*/
-      pwmp->flexpwmp->SUB[3].INTEN.R = 0;
-
-      /* Disable the submodule.*/
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7;
-
-      /* Active the submodule masks.*/
-      pwmp->flexpwmp->MASK.B.MASKA &= 0x7;
-      pwmp->flexpwmp->MASK.B.MASKB &= 0x7;
-
-      /* Sets the MASK registers.*/
-      pwmp->flexpwmp->SUB[3].CTRL2.B.FRCEN = 1U;
-      pwmp->flexpwmp->SUB[3].CTRL2.B.FORCE = 1U;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD4
-    if (&PWMD5 == pwmp) {
-      /* Disable the interrupts.*/
-      pwmp->flexpwmp->SUB[0].INTEN.R = 0;
-
-      /* Disable the submodule.*/
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE;
-
-      /* Active the submodule masks.*/
-      pwmp->flexpwmp->MASK.B.MASKA &= 0xE;
-      pwmp->flexpwmp->MASK.B.MASKB &= 0xE;
-
-      /* Sets the MASK registers.*/
-      pwmp->flexpwmp->SUB[0].CTRL2.B.FRCEN = 1U;
-      pwmp->flexpwmp->SUB[0].CTRL2.B.FORCE = 1U;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD5
-    if (&PWMD6 == pwmp) {
-      /* Disable the interrupts.*/
-      pwmp->flexpwmp->SUB[1].INTEN.R = 0;
-
-      /* Disable the submodule.*/
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD;
-
-      /* Active the submodule masks.*/
-      pwmp->flexpwmp->MASK.B.MASKA &= 0xD;
-      pwmp->flexpwmp->MASK.B.MASKB &= 0xD;
-
-      /* Sets the MASK registers.*/
-      pwmp->flexpwmp->SUB[1].CTRL2.B.FRCEN = 1U;
-      pwmp->flexpwmp->SUB[1].CTRL2.B.FORCE = 1U;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD6
-    if (&PWMD7 == pwmp) {
-      /* Disable the interrupts.*/
-      pwmp->flexpwmp->SUB[2].INTEN.R = 0;
-
-      /* Disable the submodule.*/
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB;
-
-      /* Active the submodule masks.*/
-      pwmp->flexpwmp->MASK.B.MASKA &= 0xB;
-      pwmp->flexpwmp->MASK.B.MASKB &= 0xB;
-
-      /* Sets the MASK registers.*/
-      pwmp->flexpwmp->SUB[2].CTRL2.B.FRCEN = 1U;
-      pwmp->flexpwmp->SUB[2].CTRL2.B.FORCE = 1U;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD7
-    if (&PWMD8 == pwmp) {
-      /* Disable the interrupts.*/
-      pwmp->flexpwmp->SUB[3].INTEN.R = 0;
-
-      /* Disable the submodule.*/
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7;
-
-      /* Active the submodule masks.*/
-      pwmp->flexpwmp->MASK.B.MASKA &= 0x7;
-      pwmp->flexpwmp->MASK.B.MASKB &= 0x7;
-
-      /* Sets the MASK registers.*/
-      pwmp->flexpwmp->SUB[3].CTRL2.B.FRCEN = 1U;
-      pwmp->flexpwmp->SUB[3].CTRL2.B.FORCE = 1U;
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Deactivates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
-  chDbgAssert(flexpwm_active_submodules0 < 5,
-              "pwm_lld_stop(), #1", "too many submodules");
-  chDbgAssert(flexpwm_active_submodules1 < 5,
-              "pwm_lld_stop(), #2", "too many submodules");
-
-  /* If in ready state then disables the PWM clock.*/
-  if (pwmp->state == PWM_READY) {
-
-#if SPC5_PWM_USE_SMOD0
-    if (&PWMD1 == pwmp) {
-      flexpwm_active_submodules0--;
-    }
-#endif /* SPC5_PWM_USE_SMOD0 */
-
-#if SPC5_PWM_USE_SMOD1
-    if (&PWMD2 == pwmp) {
-      flexpwm_active_submodules0--;
-    }
-#endif /* SPC5_PWM_USE_SMOD1 */
-
-#if SPC5_PWM_USE_SMOD2
-    if (&PWMD3 == pwmp) {
-      flexpwm_active_submodules0--;
-    }
-#endif /* SPC5_PWM_USE_SMOD2 */
-
-#if SPC5_PWM_USE_SMOD3
-    if (&PWMD4 == pwmp) {
-      flexpwm_active_submodules0--;
-    }
-#endif /* SPC5_PWM_USE_SMOD3 */
-
-#if SPC5_PWM_USE_SMOD4
-    if (&PWMD5 == pwmp) {
-      flexpwm_active_submodules1--;
-    }
-#endif /* SPC5_PWM_USE_SMOD4 */
-
-#if SPC5_PWM_USE_SMOD5
-    if (&PWMD6 == pwmp) {
-      flexpwm_active_submodules1--;
-    }
-#endif /* SPC5_PWM_USE_SMOD5 */
-
-#if SPC5_PWM_USE_SMOD6
-    if (&PWMD7 == pwmp) {
-      flexpwm_active_submodules1--;
-    }
-#endif /* SPC5_PWM_USE_SMOD6 */
-
-#if SPC5_PWM_USE_SMOD7
-    if (&PWMD8 == pwmp) {
-      flexpwm_active_submodules1--;
-    }
-#endif /* SPC5_PWM_USE_SMOD7 */
-
-#if SPC5_PWM_USE_SMOD0
-    if (&PWMD1 == pwmp) {
-      /* SMOD stop.*/
-      pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U;
-      pwmp->flexpwmp->SUB[0].INTEN.R = 0;
-      pwmp->flexpwmp->SUB[0].STS.R = 0xFFFF;
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE;
-
-      pwmp->flexpwmp->MCTRL.B.RUN &= 0xE;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD1
-    if (&PWMD2 == pwmp) {
-      /* SMOD stop.*/
-      pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U;
-      pwmp->flexpwmp->SUB[1].INTEN.R = 0;
-      pwmp->flexpwmp->SUB[1].STS.R = 0xFFFF;
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD;
-
-      pwmp->flexpwmp->MCTRL.B.RUN &= 0xD;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD2
-    if (&PWMD3 == pwmp) {
-      /* SMOD stop.*/
-      pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U;
-      pwmp->flexpwmp->SUB[2].INTEN.R = 0;
-      pwmp->flexpwmp->SUB[2].STS.R = 0xFFFF;
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB;
-
-      pwmp->flexpwmp->MCTRL.B.RUN &= 0xB;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD3
-    if (&PWMD4 == pwmp) {
-      /* SMOD stop.*/
-      pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U;
-      pwmp->flexpwmp->SUB[3].INTEN.R = 0;
-      pwmp->flexpwmp->SUB[3].STS.R = 0xFFFF;
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7;
-
-      pwmp->flexpwmp->MCTRL.B.RUN &= 0x7;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD4
-    if (&PWMD5 == pwmp) {
-      /* SMOD stop.*/
-      pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U;
-      pwmp->flexpwmp->SUB[0].INTEN.R = 0;
-      pwmp->flexpwmp->SUB[0].STS.R = 0xFFFF;
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE;
-
-      pwmp->flexpwmp->MCTRL.B.RUN &= 0xE;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD5
-    if (&PWMD6 == pwmp) {
-      /* SMOD stop.*/
-      pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U;
-      pwmp->flexpwmp->SUB[1].INTEN.R = 0;
-      pwmp->flexpwmp->SUB[1].STS.R = 0xFFFF;
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD;
-
-      pwmp->flexpwmp->MCTRL.B.RUN &= 0xD;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD6
-    if (&PWMD7 == pwmp) {
-      /* SMOD stop.*/
-      pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U;
-      pwmp->flexpwmp->SUB[2].INTEN.R = 0;
-      pwmp->flexpwmp->SUB[2].STS.R = 0xFFFF;
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB;
-
-      pwmp->flexpwmp->MCTRL.B.RUN &= 0xB;
-    }
-#endif
-#if SPC5_PWM_USE_SMOD7
-    if (&PWMD8 == pwmp) {
-      /* SMOD stop.*/
-      pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U;
-      pwmp->flexpwmp->SUB[3].INTEN.R = 0;
-      pwmp->flexpwmp->SUB[3].STS.R = 0xFFFF;
-      pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7;
-      pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7;
-
-      pwmp->flexpwmp->MCTRL.B.RUN &= 0x7;
-    }
-#endif
-
-#if SPC5_PWM_USE_FLEXPWM0
-    /* Disable peripheral clock if there is not an activated module.*/
-    if (flexpwm_active_submodules0 == 0) {
-      halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL,
-                                   SPC5_PWM_FLEXPWM0_STOP_PCTL);
-    }
-#endif
-
-#if SPC5_PWM_USE_FLEXPWM1
-    /* Disable peripheral clock if there is not an activated module.*/
-    if (flexpwm_active_submodules1 == 0) {
-      halSPCSetPeripheralClockMode(SPC5_FLEXPWM1_PCTL,
-                                   SPC5_PWM_FLEXPWM1_STOP_PCTL);
-    }
-#endif
-
-  }
-}
-
-/**
- * @brief   Enables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is active using the specified configuration.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t channel,
-                            pwmcnt_t width) {
-
-#if SPC5_PWM_USE_SMOD0
-  if (&PWMD1 == pwmp) {
-    pwm_lld_enable_submodule_channel(pwmp, channel, width, 0);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD1
-  if (&PWMD2 == pwmp) {
-    pwm_lld_enable_submodule_channel(pwmp, channel, width, 1);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD2
-  if (&PWMD3 == pwmp) {
-    pwm_lld_enable_submodule_channel(pwmp, channel, width, 2);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD3
-  if (&PWMD4 == pwmp) {
-    pwm_lld_enable_submodule_channel(pwmp, channel, width, 3);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD4
-  if (&PWMD5 == pwmp) {
-    pwm_lld_enable_submodule_channel(pwmp, channel, width, 0);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD5
-  if (&PWMD6 == pwmp) {
-    pwm_lld_enable_submodule_channel(pwmp, channel, width, 1);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD6
-  if (&PWMD7 == pwmp) {
-    pwm_lld_enable_submodule_channel(pwmp, channel, width, 2);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD7
-  if (&PWMD8 == pwmp) {
-    pwm_lld_enable_submodule_channel(pwmp, channel, width, 3);
-  }
-#endif
-}
-
-/**
- * @brief   Disables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is disabled and its output line returned to the
- *          idle state.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-#if SPC5_PWM_USE_SMOD0
-  if (&PWMD1 == pwmp) {
-    pwm_lld_disable_submodule_channel(pwmp, channel, 0);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD1
-  if (&PWMD2 == pwmp) {
-    pwm_lld_disable_submodule_channel(pwmp, channel, 1);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD2
-  if (&PWMD3 == pwmp) {
-    pwm_lld_disable_submodule_channel(pwmp, channel, 2);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD3
-  if (&PWMD4 == pwmp) {
-    pwm_lld_disable_submodule_channel(pwmp, channel, 3);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD4
-  if (&PWMD5 == pwmp) {
-    pwm_lld_disable_submodule_channel(pwmp, channel, 0);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD5
-  if (&PWMD6 == pwmp) {
-    pwm_lld_disable_submodule_channel(pwmp, channel, 1);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD6
-  if (&PWMD7 == pwmp) {
-    pwm_lld_disable_submodule_channel(pwmp, channel, 2);
-  }
-#endif
-#if SPC5_PWM_USE_SMOD7
-  if (&PWMD8 == pwmp) {
-    pwm_lld_disable_submodule_channel(pwmp, channel, 3);
-  }
-#endif
-}
-
-/**
- * @brief   Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- *          been activated using @p pwmStart().
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The PWM unit period is changed to the new value.
- * @note    The function has effect at the next cycle start.
- * @note    If a period is specified that is shorter than the pulse width
- *          programmed in one of the channels then the behavior is not
- *          guaranteed.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] period    new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
-
-  pwmcnt_t pwmperiod = period;
-#if SPC5_PWM_USE_SMOD0
-  if (&PWMD1 == pwmp) {
-    pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U;
-
-    /* Setting PWM period.*/
-    pwmp->flexpwmp->SUB[0].INIT.R = ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[0].VAL[0].R = 0;
-    pwmp->flexpwmp->SUB[0].VAL[1].R = pwmperiod / 2;
-
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-      /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[0].VAL[2].R = ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[0].VAL[4].R = ~(pwmperiod / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-    pwmp->flexpwmp->MCTRL.B.LDOK |= 1U;
-  }
-#endif
-#if SPC5_PWM_USE_SMOD1
-  if (&PWMD2 == pwmp) {
-    pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U;
-
-    /* Setting PWM period.*/
-    pwmp->flexpwmp->SUB[1].INIT.R = ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[1].VAL[0].R = 0;
-    pwmp->flexpwmp->SUB[1].VAL[1].R = pwmperiod / 2;
-
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-
-      /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[1].VAL[2].R = ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[1].VAL[4].R = ~(pwmperiod / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-    pwmp->flexpwmp->MCTRL.B.LDOK |= 2U;
-  }
-#endif
-#if SPC5_PWM_USE_SMOD2
-  if (&PWMD3 == pwmp) {
-    pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U;
-
-    /* Setting PWM period.*/
-    pwmp->flexpwmp->SUB[2].INIT.R = ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[2].VAL[0].R = 0;
-    pwmp->flexpwmp->SUB[2].VAL[1].R = pwmperiod / 2;
-
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-      /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[2].VAL[2].R = ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[2].VAL[4].R = ~(pwmperiod / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-    pwmp->flexpwmp->MCTRL.B.LDOK |= 4U;
-  }
-#endif
-#if SPC5_PWM_USE_SMOD3
-  if (&PWMD4 == pwmp) {
-    pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U;
-
-    /* Setting PWM period.*/
-    pwmp->flexpwmp->SUB[3].INIT.R = ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[3].VAL[0].R = 0;
-    pwmp->flexpwmp->SUB[3].VAL[1].R = pwmperiod / 2;
-
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-      /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[3].VAL[2].R = ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[3].VAL[4].R = ~(pwmperiod / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-    pwmp->flexpwmp->MCTRL.B.LDOK |= 8U;
-  }
-#endif
-#if SPC5_PWM_USE_SMOD4
-  if (&PWMD5 == pwmp) {
-    pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U;
-
-    /* Setting PWM period.*/
-    pwmp->flexpwmp->SUB[0].INIT.R = ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[0].VAL[0].R = 0;
-    pwmp->flexpwmp->SUB[0].VAL[1].R = pwmperiod / 2;
-
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-      /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[0].VAL[2].R = ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[0].VAL[4].R = ~(pwmperiod / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-    pwmp->flexpwmp->MCTRL.B.LDOK |= 1U;
-  }
-#endif
-#if SPC5_PWM_USE_SMOD5
-  if (&PWMD6 == pwmp) {
-    pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U;
-
-    /* Setting PWM period.*/
-    pwmp->flexpwmp->SUB[1].INIT.R = ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[1].VAL[0].R = 0;
-    pwmp->flexpwmp->SUB[1].VAL[1].R = pwmperiod / 2;
-
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-      /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[1].VAL[2].R = ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[1].VAL[4].R = ~(pwmperiod / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-    pwmp->flexpwmp->MCTRL.B.LDOK |= 2U;
-  }
-#endif
-#if SPC5_PWM_USE_SMOD6
-  if (&PWMD7 == pwmp) {
-    pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U;
-
-    /* Setting PWM period.*/
-    pwmp->flexpwmp->SUB[2].INIT.R = ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[2].VAL[0].R = 0;
-    pwmp->flexpwmp->SUB[2].VAL[1].R = pwmperiod / 2;
-
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-      /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[2].VAL[2].R = ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[2].VAL[4].R = ~(pwmperiod / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-    pwmp->flexpwmp->MCTRL.B.LDOK |= 4U;
-  }
-#endif
-#if SPC5_PWM_USE_SMOD7
-  if (&PWMD8 == pwmp) {
-    pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U;
-
-    /* Setting PWM period.*/
-    pwmp->flexpwmp->SUB[3].INIT.R = ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[3].VAL[0].R = 0;
-    pwmp->flexpwmp->SUB[3].VAL[1].R = pwmperiod / 2;
-
-    switch (pwmp->config->mode & PWM_ALIGN_MASK) {
-    case PWM_ALIGN_EDGE:
-      /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[3].VAL[2].R = ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[3].VAL[4].R = ~(pwmperiod / 2) + 1U;
-      break;
-    default:
-      ;
-    }
-    pwmp->flexpwmp->MCTRL.B.LDOK |= 8U;
-  }
-#endif
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
deleted file mode 100644
index ea9acb7cd..000000000
--- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
+++ /dev/null
@@ -1,475 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    FlexPWM_v1/pwm_lld.h
- * @brief   SPC5xx low level PWM driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_flexpwm.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    STS register bits definitions
- * @{
- */
-#define SPC5_FLEXPWM_STS_CMPF0              (1U << 0)
-#define SPC5_FLEXPWM_STS_CMPF1              (1U << 1)
-#define SPC5_FLEXPWM_STS_CMPF2              (1U << 2)
-#define SPC5_FLEXPWM_STS_CMPF3              (1U << 3)
-#define SPC5_FLEXPWM_STS_CMPF4              (1U << 4)
-#define SPC5_FLEXPWM_STS_CMPF5              (1U << 5)
-#define SPC5_FLEXPWM_STS_CFX0               (1U << 6)
-#define SPC5_FLEXPWM_STS_CFX1               (1U << 7)
-#define SPC5_FLEXPWM_STS_RF                 (1U << 12)
-#define SPC5_FLEXPWM_STS_REF                (1U << 13)
-#define SPC5_FLEXPWM_STS_RUF                (1U << 14)
-/** @} */
-
-/**
- * @name    PSC values definition
- * @{
- */
-#define SPC5_FLEXPWM_PSC_1                  0U
-#define SPC5_FLEXPWM_PSC_2                  1U
-#define SPC5_FLEXPWM_PSC_4                  2U
-#define SPC5_FLEXPWM_PSC_8                  3U
-#define SPC5_FLEXPWM_PSC_16                 4U
-#define SPC5_FLEXPWM_PSC_32                 5U
-#define SPC5_FLEXPWM_PSC_64                 6U
-#define SPC5_FLEXPWM_PSC_128                7U
-/** @} */
-
-/**
- * @brief   Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS                            2
-
-/**
- * @brief   Complementary output modes mask.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_MASK           0xF0
-
-/**
- * @brief   Complementary output not driven.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_DISABLED       0x00
-
-/**
- * @brief   Complementary output, active is logic level one.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH    0x10
-
-/**
- * @brief   Complementary output, active is logic level zero.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW     0x20
-
-/**
- * @brief   Alignment mode mask.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_MASK                          0x01
-
-/**
- * @brief   Edge-Aligned PWM functional mode.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_EDGE                          0x00
-
-/**
- * @brief   Center-Aligned PWM functional mode.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_CENTER                        0x01
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD0) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD0                  FALSE
-#endif
-
-/**
- * @brief   PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD1) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD1                  FALSE
-#endif
-
-/**
- * @brief   PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD2) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD2                  FALSE
-#endif
-
-/**
- * @brief   PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD3) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD3                  FALSE
-#endif
-
-/**
- * @brief   PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD0_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD0_PRIORITY             7
-#endif
-
-/**
- * @brief   PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD1_PRIORITY             7
-#endif
-
-/**
- * @brief   PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD2_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD2_PRIORITY             7
-#endif
-
-/**
- * @brief   PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD3_PRIORITY             7
-#endif
-
-/**
- * @brief   FlexPWM-0 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_PWM_FLEXPWM0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_PWM_FLEXPWM0_START_PCTL        (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   FlexPWM-0 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_PWM_FLEXPWM0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_PWM_FLEXPWM0_STOP_PCTL         (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   PWMD5 driver enable switch.
- * @details If set to @p TRUE the support for PWMD5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD4) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD4                  FALSE
-#endif
-
-/**
- * @brief   PWMD6 driver enable switch.
- * @details If set to @p TRUE the support for PWMD6 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD5) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD5                  FALSE
-#endif
-
-/**
- * @brief   PWMD7 driver enable switch.
- * @details If set to @p TRUE the support for PWMD7 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD6) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD6                  FALSE
-#endif
-
-/**
- * @brief   PWMD8 driver enable switch.
- * @details If set to @p TRUE the support for PWMD8 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_SMOD7) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_SMOD7                  FALSE
-#endif
-
-/**
- * @brief   PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD4_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD4_PRIORITY             7
-#endif
-
-/**
- * @brief   PWMD6 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD5_PRIORITY             7
-#endif
-
-/**
- * @brief   PWMD7 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD6_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD6_PRIORITY             7
-#endif
-
-/**
- * @brief   PWMD8 interrupt priority level setting.
- */
-#if !defined(SPC5_PWM_SMOD7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PWM_SMOD7_PRIORITY             7
-#endif
-
-/**
- * @brief   FlexPWM-1 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_PWM_FLEXPWM1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_PWM_FLEXPWM1_START_PCTL        (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   FlexPWM-1 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_PWM_FLEXPWM1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_PWM_FLEXPWM1_STOP_PCTL         (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/*===========================================================================*/
-/* Configuration checks.                                                     */
-/*===========================================================================*/
-
-#define SPC5_PWM_USE_FLEXPWM0               (SPC5_PWM_USE_SMOD0 ||          \
-                                             SPC5_PWM_USE_SMOD1 ||          \
-                                             SPC5_PWM_USE_SMOD2 ||          \
-                                             SPC5_PWM_USE_SMOD3)
-
-#define SPC5_PWM_USE_FLEXPWM1               (SPC5_PWM_USE_SMOD4 ||          \
-                                             SPC5_PWM_USE_SMOD5 ||          \
-                                             SPC5_PWM_USE_SMOD6 ||          \
-                                             SPC5_PWM_USE_SMOD7)
-
-#if !SPC5_HAS_FLEXPWM0 && SPC5_PWM_USE_FLEXPWM0
-#error "FlexPWM0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_FLEXPWM1 && SPC5_PWM_USE_FLEXPWM1
-#error "FlexPWM1 not present in the selected device"
-#endif
-
-#if !SPC5_PWM_USE_FLEXPWM0 && !SPC5_PWM_USE_FLEXPWM1
-#error "PWM driver activated but no PWM peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief   PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief   PWM counter type.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief   PWM driver channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel active logic level.
-   */
-  pwmmode_t                 mode;
-  /**
-   * @brief Channel callback pointer.
-   * @note  This callback is invoked on the channel compare event. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief   PWM driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Timer clock in Hz.
-   * @note  The low level can use assertions in order to catch invalid
-   *        frequency specifications.
-   */
-  uint32_t                  frequency;
-  /**
-   * @brief PWM period in ticks.
-   * @note  The low level can use assertions in order to catch invalid
-   *        period specifications.
-   */
-  pwmcnt_t                  period;
-  /**
-   * @brief Periodic callback pointer.
-   * @note  This callback is invoked on PWM counter reset. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /**
-   * @brief Channels configurations.
-   */
-  PWMChannelConfig          channels[PWM_CHANNELS];
-  /* End of the mandatory fields.*/
-  /**
-   * @brief PWM functional mode.
-   */
-  pwmmode_t                 mode;
-} PWMConfig;
-
-/**
- * @brief   Structure representing a PWM driver.
- */
-struct PWMDriver {
-  /**
-   * @brief Driver state.
-   */
-  pwmstate_t                state;
-  /**
-   * @brief Current driver configuration data.
-   */
-  const PWMConfig           *config;
-  /**
-   * @brief Current PWM period in ticks.
-   */
-  pwmcnt_t                  period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
-  PWM_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @Pointer to the volatile FlexPWM registers block.
-   */
-  volatile struct spc5_flexpwm *flexpwmp;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_SMOD0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if SPC5_PWM_USE_SMOD1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if SPC5_PWM_USE_SMOD2 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if SPC5_PWM_USE_SMOD3 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#if SPC5_PWM_USE_SMOD4 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD5;
-#endif
-
-#if SPC5_PWM_USE_SMOD5 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD6;
-#endif
-
-#if SPC5_PWM_USE_SMOD6 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD7;
-#endif
-
-#if SPC5_PWM_USE_SMOD7 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD8;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void pwm_lld_init(void);
-  void pwm_lld_start(PWMDriver *pwmp);
-  void pwm_lld_stop(PWMDriver *pwmp);
-  void pwm_lld_enable_channel(PWMDriver *pwmp,
-                              pwmchannel_t channel,
-                              pwmcnt_t width);
-  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-  void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h
deleted file mode 100644
index 5be53d949..000000000
--- a/os/hal/platforms/SPC5xx/FlexPWM_v1/spc5_flexpwm.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    FlexPWM_v1/spc5_flexpwm.h
- * @brief   SPC5xx FlexPWM header file.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _SPC5_FLEXPWM_H_
-#define _SPC5_FLEXPWM_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPC5 FlexPWM registers block.
- * @note    Redefined from the SPC5 headers because the non uniform
- *          declaration of the SubModules registers among the various
- *          sub-families.
- */
-struct spc5_flexpwm_submodule {
-
-  union {
-    vuint16_t R;
-  } CNT; /* Counter Register */
-
-  union {
-    vuint16_t R;
-  } INIT; /* Initial Count Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t DBGEN :1;
-      vuint16_t WAITEN :1;
-      vuint16_t INDEP :1;
-      vuint16_t PWMA_INIT :1;
-      vuint16_t PWMB_INIT :1;
-      vuint16_t PWMX_INIT :1;
-      vuint16_t INIT_SEL :2;
-      vuint16_t FRCEN :1;
-      vuint16_t FORCE :1;
-      vuint16_t FORCE_SEL :3;
-      vuint16_t RELOAD_SEL :1;
-      vuint16_t CLK_SEL :2;
-    } B;
-  } CTRL2; /* Control 2 Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t LDFQ :4;
-      vuint16_t HALF :1;
-      vuint16_t FULL :1;
-      vuint16_t DT :2;
-      vuint16_t :1;
-      vuint16_t PRSC :3;
-      vuint16_t :3;
-      vuint16_t DBLEN :1;
-    } B;
-  } CTRL; /* Control Register */
-
-  union {
-    vuint16_t R;
-  } VAL[6]; /* Value Register 0->5 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t FRACAEN :1;
-      vuint16_t :10;
-      vuint16_t FRACADLY :5;
-    } B;
-  } FRACA; /* Fractional Delay Register A */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t FRACBEN :1;
-      vuint16_t :10;
-      vuint16_t FRACBDLY :5;
-    } B;
-  } FRACB; /* Fractional Delay Register B */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t PWMA_IN :1;
-      vuint16_t PWMB_IN :1;
-      vuint16_t PWMX_IN :1;
-      vuint16_t :2;
-      vuint16_t POLA :1;
-      vuint16_t POLB :1;
-      vuint16_t POLX :1;
-      vuint16_t :2;
-      vuint16_t PWMAFS :2;
-      vuint16_t PWMBFS :2;
-      vuint16_t PWMXFS :2;
-    } B;
-  } OCTRL; /* Output Control Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :1;
-      vuint16_t RUF :1;
-      vuint16_t REF :1;
-      vuint16_t RF :1;
-      vuint16_t CFA1 :1;
-      vuint16_t CFA0 :1;
-      vuint16_t CFB1 :1;
-      vuint16_t CFB0 :1;
-      vuint16_t CFX1 :1;
-      vuint16_t CFX0 :1;
-      vuint16_t CMPF :6;
-    } B;
-  } STS; /* Status Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :2;
-      vuint16_t REIE :1;
-      vuint16_t RIE :1;
-      vuint16_t :4;
-      vuint16_t CX1IE :1;
-      vuint16_t CX0IE :1;
-      vuint16_t CMPIE :6;
-    } B;
-  } INTEN; /* Interrupt Enable Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :6;
-      vuint16_t VALDE :1;
-      vuint16_t FAND :1;
-      vuint16_t CAPTDE :2;
-      vuint16_t CA1DE :1;
-      vuint16_t CA0DE :1;
-      vuint16_t CB1DE :1;
-      vuint16_t CB0DE :1;
-      vuint16_t CX1DE :1;
-      vuint16_t CX0DE :1;
-    } B;
-  } DMAEN; /* DMA Enable Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :10;
-      vuint16_t OUT_TRIG_EN :6;
-    } B;
-  } TCTRL; /* Output Trigger Control Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :4;
-      vuint16_t DISX :4;
-      vuint16_t DISB :4;
-      vuint16_t DISA :4;
-    } B;
-  } DISMAP; /* Fault Disable Mapping Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :5;
-      vuint16_t DTCNT0 :11;
-    } B;
-  } DTCNT0; /* Deadtime Count Register 0 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :5;
-      vuint16_t DTCNT1 :11;
-    } B;
-  } DTCNT1; /* Deadtime Count Register 1 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CA1CNT :3;
-      vuint16_t CA0CNT :3;
-      vuint16_t CFAWM :2;
-      vuint16_t EDGCNTAEN :1;
-      vuint16_t INPSELA :1;
-      vuint16_t EDGA1 :2;
-      vuint16_t EDGA0 :2;
-      vuint16_t ONESHOTA :1;
-      vuint16_t ARMA :1;
-    } B;
-  } CAPTCTRLA; /* Capture Control Register A */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t EDGCNTA :8;
-      vuint16_t EDGCMPA :8;
-    } B;
-  } CAPTCOMPA; /* Capture Compare Register A */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CB1CNT :3;
-      vuint16_t CB0CNT :3;
-      vuint16_t CFBWM :2;
-      vuint16_t EDGCNTBEN :1;
-      vuint16_t INPSELB :1;
-      vuint16_t EDGB1 :2;
-      vuint16_t EDGB0 :2;
-      vuint16_t ONESHOTB :1;
-      vuint16_t ARMB :1;
-    } B;
-  } CAPTCTRLB; /* Capture Control Register B */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t EDGCNTB :8;
-      vuint16_t EDGCMPB :8;
-    } B;
-  } CAPTCOMPB; /* Capture Compare Register B */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CX1CNT :3;
-      vuint16_t CX0CNT :3;
-      vuint16_t CFXWM :2;
-      vuint16_t EDGCNTX_EN :1;
-      vuint16_t INP_SELX :1;
-      vuint16_t EDGX1 :2;
-      vuint16_t EDGX0 :2;
-      vuint16_t ONESHOTX :1;
-      vuint16_t ARMX :1;
-    } B;
-  } CAPTCTRLX; /* Capture Control Register B */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t EDGCNTX :8;
-      vuint16_t EDGCMPX :8;
-    } B;
-  } CAPTCOMPX; /* Capture Compare Register X */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CAPTVAL0 :16;
-    } B;
-  } CVAL0; /* Capture Value 0 Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :12;
-      vuint16_t CVAL0CYC :4;
-    } B;
-  } CVAL0C; /* Capture Value 0 Cycle Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CAPTVAL1 :16;
-    } B;
-  } CVAL1; /* Capture Value 1 Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :12;
-      vuint16_t CVAL1CYC :4;
-    } B;
-  } CVAL1C; /* Capture Value 1 Cycle Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CAPTVAL2 :16;
-    } B;
-  } CVAL2; /* Capture Value 2 Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :12;
-      vuint16_t CVAL2CYC :4;
-    } B;
-  } CVAL2C; /* Capture Value 2 Cycle Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CAPTVAL3 :16;
-    } B;
-  } CVAL3; /* Capture Value 3 Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :12;
-      vuint16_t CVAL3CYC :4;
-    } B;
-  } CVAL3C; /* Capture Value 3 Cycle Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CAPTVAL4 :16;
-    } B;
-  } CVAL4; /* Capture Value 4 Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :12;
-      vuint16_t CVAL4CYC :4;
-    } B;
-  } CVAL4C; /* Capture Value 4 Cycle Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CAPTVAL5 :16;
-    } B;
-  } CVAL5; /* Capture Value 5 Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :12;
-      vuint16_t CVAL5CYC :4;
-    } B;
-  } CVAL5C; /* Capture Value 5 Cycle Register */
-
-  uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */
-
-};
-/* end of FLEXPWM_SUB_tag */
-
-struct spc5_flexpwm {
-
-  struct spc5_flexpwm_submodule SUB[4];
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :4;
-      vuint16_t PWMA_EN :4;
-      vuint16_t PWMB_EN :4;
-      vuint16_t PWMX_EN :4;
-    } B;
-  } OUTEN; /* Output Enable Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :4;
-      vuint16_t MASKA :4;
-      vuint16_t MASKB :4;
-      vuint16_t MASKX :4;
-    } B;
-  } MASK; /* Output Mask Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :8;
-      vuint16_t OUTA_3 :1;
-      vuint16_t OUTB_3 :1;
-      vuint16_t OUTA_2 :1;
-      vuint16_t OUTB_2 :1;
-      vuint16_t OUTA_1 :1;
-      vuint16_t OUTB_1 :1;
-      vuint16_t OUTA_0 :1;
-      vuint16_t OUTB_0 :1;
-    } B;
-  } SWCOUT; /* Software Controlled Output Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t SELA_3 :2;
-      vuint16_t SELB_3 :2;
-      vuint16_t SELA_2 :2;
-      vuint16_t SELB_2 :2;
-      vuint16_t SELA_1 :2;
-      vuint16_t SELB_1 :2;
-      vuint16_t SELA_0 :2;
-      vuint16_t SELB_0 :2;
-    } B;
-  } DTSRCSEL; /* Deadtime Source Select Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t IPOL :4;
-      vuint16_t RUN :4;
-      vuint16_t CLDOK :4;
-      vuint16_t LDOK :4;
-    } B;
-  } MCTRL; /* Master Control Register */
-
-  int16_t FLEXPWM_reserved1;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t FLVL :4;
-      vuint16_t FAUTO :4;
-      vuint16_t FSAFE :4;
-      vuint16_t FIE :4;
-    } B;
-  } FCTRL; /* Fault Control Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t FTEST :1;
-      vuint16_t FFPIN :4;
-      vuint16_t :4;
-      vuint16_t FFLAG :4;
-    } B;
-  } FSTS; /* Fault Status Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :5;
-      vuint16_t FILT_CNT :3;
-      vuint16_t FILT_PER :8;
-    } B;
-  } FFILT; /* Fault FilterRegister */
-
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    FlexPWM units references
- * @{
- */
-#if SPC5_HAS_FLEXPWM0 || defined(__DOXYGEN__)
-#define SPC5_FLEXPWM_0      (*(volatile struct spc5_flexpwm *)0xFFE24000UL)
-#endif
-
-#if SPC5_HAS_FLEXPWM1 || defined(__DOXYGEN__)
-#define SPC5_FLEXPWM_1      (*(volatile struct spc5_flexpwm *)0xFFE28000UL)
-#endif
-/** @} */
-
-#endif /* _SPC5_FLEXPWM_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
deleted file mode 100644
index 71247b236..000000000
--- a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
+++ /dev/null
@@ -1,602 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/LINFlex_v1/serial_lld.c
- * @brief   SPC5xx low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   LIINFlex-0 serial driver identifier.
- */
-#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/**
- * @brief   LIINFlex-1 serial driver identifier.
- */
-#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/**
- * @brief   LIINFlex-2 serial driver identifier.
- */
-#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/**
- * @brief   LIINFlex-3 serial driver identifier.
- */
-#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
-SerialDriver SD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Driver default configuration.
- */
-static const SerialConfig default_config = {
-  SERIAL_DEFAULT_BITRATE,
-  SD_MODE_8BITS_PARITY_NONE
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   LINFlex initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void spc5_linflex_init(SerialDriver *sdp, const SerialConfig *config) {
-  uint32_t div;
-  volatile struct spc5_linflex *linflexp = sdp->linflexp;
-
-  /* Enters the configuration mode.*/
-  linflexp->LINCR1.R  = 1;                      /* INIT bit.                */
-
-  /* Configures the LINFlex in UART mode with all the required
-     parameters.*/
-  linflexp->UARTCR.R  = SPC5_UARTCR_UART;       /* UART mode FIRST.         */
-  linflexp->UARTCR.R  = SPC5_UARTCR_UART | SPC5_UARTCR_RXEN | config->mode;
-  div = SPC5_LINFLEX0_CLK / config->speed;
-  linflexp->LINFBRR.R = (uint16_t)(div & 15);   /* Fractional divider.      */
-  linflexp->LINIBRR.R = (uint16_t)(div >> 4);   /* Integer divider.         */
-  linflexp->UARTSR.R  = 0xFFFF;                 /* Clearing UARTSR register.*/
-  linflexp->LINIER.R  = SPC5_LINIER_DTIE | SPC5_LINIER_DRIE |
-                        SPC5_LINIER_BOIE | SPC5_LINIER_FEIE |
-                        SPC5_LINIER_SZIE;       /* Interrupts enabled.      */
-
-  /* Leaves the configuration mode.*/
-  linflexp->LINCR1.R  = 0;
-}
-
-/**
- * @brief   LINFlex de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] linflexp  pointer to a LINFlex I/O block
- */
-static void spc5_linflex_deinit(volatile struct spc5_linflex *linflexp) {
-
-  /* Enters the configuration mode.*/
-  linflexp->LINCR1.R  = 1;                      /* INIT bit.                */
-
-  /* Resets the LINFlex registers.*/
-  linflexp->LINFBRR.R = 0;                      /* Fractional divider.      */
-  linflexp->LINIBRR.R = 0;                      /* Integer divider.         */
-  linflexp->UARTSR.R  = 0xFFFF;                 /* Clearing UARTSR register.*/
-  linflexp->UARTCR.R  = SPC5_UARTCR_UART;
-  linflexp->LINIER.R  = 0;                      /* Interrupts disabled.     */
-
-  /* Leaves the configuration mode.*/
-  linflexp->LINCR1.R  = 0;
-}
-
-/**
- * @brief   Common RXI IRQ handler.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- */
-static void spc5xx_serve_rxi_interrupt(SerialDriver *sdp) {
-  flagsmask_t sts = 0;
-  uint16_t sr = sdp->linflexp->UARTSR.R;
-
-  sdp->linflexp->UARTSR.R = SPC5_UARTSR_NF | SPC5_UARTSR_DRF |
-                            SPC5_UARTSR_PE0;
-  if (sr & SPC5_UARTSR_NF)
-    sts |= SD_NOISE_ERROR;
-  if (sr & SPC5_UARTSR_PE0)
-    sts |= SD_PARITY_ERROR;
-  chSysLockFromIsr();
-  if (sts)
-    chnAddFlagsI(sdp, sts);
-  if (sr & SPC5_UARTSR_DRF) {
-    sdIncomingDataI(sdp, sdp->linflexp->BDRM.B.DATA4);
-    sdp->linflexp->UARTSR.R = SPC5_UARTSR_RMB;
-  }
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common TXI IRQ handler.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- */
-static void spc5xx_serve_txi_interrupt(SerialDriver *sdp) {
-  msg_t b;
-
-  sdp->linflexp->UARTSR.R = SPC5_UARTSR_DTF;
-  chSysLockFromIsr();
-  b = chOQGetI(&sdp->oqueue);
-  if (b < Q_OK) {
-    chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-    sdp->linflexp->UARTCR.B.TXEN = 0;
-  }
-  else
-    sdp->linflexp->BDRL.B.DATA0 = b;
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common ERR IRQ handler.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- */
-static void spc5xx_serve_err_interrupt(SerialDriver *sdp) {
-  flagsmask_t sts = 0;
-  uint16_t sr = sdp->linflexp->UARTSR.R;
-
-  sdp->linflexp->UARTSR.R = SPC5_UARTSR_BOF | SPC5_UARTSR_FEF |
-                            SPC5_UARTSR_SZF;
-  if (sr & SPC5_UARTSR_BOF)
-    sts |= SD_OVERRUN_ERROR;
-  if (sr & SPC5_UARTSR_FEF)
-    sts |= SD_FRAMING_ERROR;
-  if (sr & SPC5_UARTSR_SZF)
-    sts |= SD_BREAK_DETECTED;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  if (!SD1.linflexp->UARTCR.B.TXEN) {
-    msg_t b = sdRequestDataI(&SD1);
-    if (b != Q_EMPTY) {
-      SD1.linflexp->UARTCR.B.TXEN = 1;
-      SD1.linflexp->BDRL.B.DATA0 = b;
-    }
-  }
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  if (!SD2.linflexp->UARTCR.B.TXEN) {
-    msg_t b = sdRequestDataI(&SD2);
-    if (b != Q_EMPTY) {
-      SD2.linflexp->UARTCR.B.TXEN = 1;
-      SD2.linflexp->BDRL.B.DATA0 = b;
-    }
-  }
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
-  (void)qp;
-  if (!SD3.linflexp->UARTCR.B.TXEN) {
-    msg_t b = sdRequestDataI(&SD3);
-    if (b != Q_EMPTY) {
-      SD3.linflexp->UARTCR.B.TXEN = 1;
-      SD3.linflexp->BDRL.B.DATA0 = b;
-    }
-  }
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
-static void notify4(GenericQueue *qp) {
-
-  (void)qp;
-  if (!SD4.linflexp->UARTCR.B.TXEN) {
-    msg_t b = sdRequestDataI(&SD4);
-    if (b != Q_EMPTY) {
-      SD4.linflexp->UARTCR.B.TXEN = 1;
-      SD4.linflexp->BDRL.B.DATA0 = b;
-    }
-  }
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__)
-#if !defined(SPC5_LINFLEX0_RXI_HANDLER)
-#error "SPC5_LINFLEX0_RXI_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-0 RXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX0_RXI_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_rxi_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX0_TXI_HANDLER)
-#error "SPC5_LINFLEX0_TXI_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-0 TXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX0_TXI_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_txi_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX0_ERR_HANDLER)
-#error "SPC5_LINFLEX0_ERR_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-0 ERR interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX0_ERR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_err_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__)
-#if !defined(SPC5_LINFLEX1_RXI_HANDLER)
-#error "SPC5_LINFLEX1_RXI_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-1 RXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX1_RXI_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_rxi_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX1_TXI_HANDLER)
-#error "SPC5_LINFLEX1_TXI_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-1 TXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX1_TXI_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_txi_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX1_ERR_HANDLER)
-#error "SPC5_LINFLEX1_ERR_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-1 ERR interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX1_ERR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_err_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
-#if !defined(SPC5_LINFLEX2_RXI_HANDLER)
-#error "SPC5_LINFLEX2_RXI_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-2 RXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX2_RXI_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_rxi_interrupt(&SD3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX2_TXI_HANDLER)
-#error "SPC5_LINFLEX2_TXI_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-2 TXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX2_TXI_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_txi_interrupt(&SD3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX2_ERR_HANDLER)
-#error "SPC5_LINFLEX2_ERR_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-2 ERR interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX2_ERR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_err_interrupt(&SD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
-#if !defined(SPC5_LINFLEX3_RXI_HANDLER)
-#error "SPC5_LINFLEX3_RXI_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-3 RXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX3_RXI_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_rxi_interrupt(&SD4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX3_TXI_HANDLER)
-#error "SPC5_LINFLEX3_TXI_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-3 TXI interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX3_TXI_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_txi_interrupt(&SD4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_LINFLEX3_ERR_HANDLER)
-#error "SPC5_LINFLEX3_ERR_HANDLER not defined"
-#endif
-/**
- * @brief   LINFlex-3 ERR interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_LINFLEX3_ERR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  spc5xx_serve_err_interrupt(&SD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if SPC5_SERIAL_USE_LINFLEX0
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.linflexp = &SPC5_LINFLEX0;
-  INTC.PSR[SPC5_LINFLEX0_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
-  INTC.PSR[SPC5_LINFLEX0_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
-  INTC.PSR[SPC5_LINFLEX0_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX1
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.linflexp = &SPC5_LINFLEX1;
-  INTC.PSR[SPC5_LINFLEX1_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
-  INTC.PSR[SPC5_LINFLEX1_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
-  INTC.PSR[SPC5_LINFLEX1_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX2
-  sdObjectInit(&SD3, NULL, notify3);
-  SD3.linflexp = &SPC5_LINFLEX2;
-  INTC.PSR[SPC5_LINFLEX2_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
-  INTC.PSR[SPC5_LINFLEX2_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
-  INTC.PSR[SPC5_LINFLEX2_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX3
-  sdObjectInit(&SD4, NULL, notify4);
-  SD4.linflexp = &SPC5_LINFLEX3;
-  INTC.PSR[SPC5_LINFLEX3_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
-  INTC.PSR[SPC5_LINFLEX3_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
-  INTC.PSR[SPC5_LINFLEX3_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if SPC5_SERIAL_USE_LINFLEX0
-    if (&SD1 == sdp) {
-      halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL,
-                                   SPC5_SERIAL_LINFLEX0_START_PCTL);
-    }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX1
-    if (&SD2 == sdp) {
-      halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL,
-                                   SPC5_SERIAL_LINFLEX1_START_PCTL);
-    }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX2
-    if (&SD3 == sdp) {
-      halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
-                                   SPC5_SERIAL_LINFLEX2_START_PCTL);
-    }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX3
-    if (&SD4 == sdp) {
-      halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
-                                   SPC5_SERIAL_LINFLEX3_START_PCTL);
-    }
-#endif
-  }
-  spc5_linflex_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    spc5_linflex_deinit(sdp->linflexp);
-
-#if SPC5_SERIAL_USE_LINFLEX0
-    if (&SD1 == sdp) {
-      halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL,
-                                   SPC5_SERIAL_LINFLEX0_STOP_PCTL);
-      return;
-    }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX1
-    if (&SD2 == sdp) {
-      halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL,
-                                   SPC5_SERIAL_LINFLEX1_STOP_PCTL);
-      return;
-    }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX2
-    if (&SD3 == sdp) {
-      halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
-                                   SPC5_SERIAL_LINFLEX2_STOP_PCTL);
-      return;
-    }
-#endif
-#if SPC5_SERIAL_USE_LINFLEX3
-    if (&SD4 == sdp) {
-      halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
-                                   SPC5_SERIAL_LINFLEX3_STOP_PCTL);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h
deleted file mode 100644
index cbd446b86..000000000
--- a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/LINFlex_v1/serial_lld.h
- * @brief   SPC5xx low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-#include "spc5_linflex.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Serial driver allowable modes
- * @{
- */
-#define SD_MODE_8BITS_PARITY_NONE           (SPC5_UARTCR_WL)
-#define SD_MODE_8BITS_PARITY_EVEN           (SPC5_UARTCR_WL |               \
-                                             SPC5_UARTCR_PCE)
-#define SD_MODE_8BITS_PARITY_ODD            (SPC5_UARTCR_WL |               \
-                                             SPC5_UARTCR_PCE |              \
-                                             SPC5_UARTCR_OP)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   LINFlex-0 driver enable switch.
- * @details If set to @p TRUE the support for LINFlex-0 is included.
- */
-#if !defined(SPC5_SERIAL_USE_LINFLEX0) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX0            FALSE
-#endif
-
-/**
- * @brief   LINFlex-1 driver enable switch.
- * @details If set to @p TRUE the support for LINFlex-1 is included.
- */
-#if !defined(SPC5_SERIAL_USE_LINFLEX1) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX1            FALSE
-#endif
-
-/**
- * @brief   LINFlex-2 driver enable switch.
- * @details If set to @p TRUE the support for LINFlex-2 is included.
- */
-#if !defined(SPC5_SERIAL_USE_LINFLEX2) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX2            FALSE
-#endif
-
-/**
- * @brief   LINFlex-3 driver enable switch.
- * @details If set to @p TRUE the support for LINFlex-3 is included.
- */
-#if !defined(SPC5_SERIAL_USE_LINFLEX3) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX3            FALSE
-#endif
-
-/**
- * @brief   LINFlex-0 interrupt priority level setting.
- */
-#if !defined(SPC5_SERIAL_LINFLEX0_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX0_PRIORITY       8
-#endif
-
-/**
- * @brief   LINFlex-1 interrupt priority level setting.
- */
-#if !defined(SPC5_SERIAL_LINFLEX1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX1_PRIORITY       8
-#endif
-
-/**
- * @brief   LINFlex-2 interrupt priority level setting.
- */
-#if !defined(SPC5_SERIAL_LINFLEX2_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX2_PRIORITY       8
-#endif
-
-/**
- * @brief   LINFlex-3 interrupt priority level setting.
- */
-#if !defined(SPC5_SERIAL_LINFLEX3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX3_PRIORITY       8
-#endif
-
-/**
- * @brief   LINFlex-0 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX0_START_PCTL     (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   LINFlex-0 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX0_STOP_PCTL      (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   LINFlex-1 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX1_START_PCTL     (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   LINFlex-1 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX1_STOP_PCTL      (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   LINFlex-2 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX2_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX2_START_PCTL     (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   LINFlex-2 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX2_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX2_STOP_PCTL      (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   LINFlex-3 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX3_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX3_START_PCTL     (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   LINFlex-3 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SERIAL_LINFLEX3_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_LINFLEX3_STOP_PCTL      (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if SPC5_SERIAL_USE_LINFLEX0 && !SPC5_HAS_LINFLEX0
-#error "LINFlex-0 not present in the selected device"
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX1 && !SPC5_HAS_LINFLEX1
-#error "LINFlex-1 not present in the selected device"
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX2 && !SPC5_HAS_LINFLEX2
-#error "LINFlex-2 not present in the selected device"
-#endif
-
-#if SPC5_SERIAL_USE_LINFLEX3 && !SPC5_HAS_LINFLEX3
-#error "LINFlex-3 not present in the selected device"
-#endif
-
-#if !SPC5_SERIAL_USE_LINFLEX0 && !SPC5_SERIAL_USE_LINFLEX1 &&               \
-    !SPC5_SERIAL_USE_LINFLEX2 && !SPC5_SERIAL_USE_LINFLEX3
-#error "SERIAL driver activated but no LINFlex peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    This structure content is architecture dependent, each driver
- *          implementation defines its own version and the custom static
- *          initializers.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  speed;
-  /**
-   * @brief Mode flags.
-   */
-  uint8_t                   mode;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the volatile LINFlex registers block.*/                     \
-  volatile struct spc5_linflex *linflexp;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_SERIAL_USE_LINFLEX0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if SPC5_SERIAL_USE_LINFLEX1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-#if SPC5_SERIAL_USE_LINFLEX2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-#if SPC5_SERIAL_USE_LINFLEX3 && !defined(__DOXYGEN__)
-extern SerialDriver SD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h b/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h
deleted file mode 100644
index 28e7575c4..000000000
--- a/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h
+++ /dev/null
@@ -1,510 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/spc5_linflex.h
- * @brief   LINFlex helper driver header.
- *
- * @addtogroup SPC5xx_LINFLEX
- * @{
- */
-
-#ifndef _SPC5_LINFLEX_H_
-#define _SPC5_LINFLEX_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    LINIER register bits definitions
- * @{
- */
-#define SPC5_LINIER_HRIE                    (1U << 0)
-#define SPC5_LINIER_DTIE                    (1U << 1)
-#define SPC5_LINIER_DRIE                    (1U << 2)
-#define SPC5_LINIER_DBEIE                   (1U << 3)
-#define SPC5_LINIER_DBFIE                   (1U << 4)
-#define SPC5_LINIER_WUIE                    (1U << 5)
-#define SPC5_LINIER_LSIE                    (1U << 6)
-#define SPC5_LINIER_BOIE                    (1U << 7)
-#define SPC5_LINIER_FEIE                    (1U << 8)
-#define SPC5_LINIER_HEIE                    (1U << 11)
-#define SPC5_LINIER_CEIE                    (1U << 12)
-#define SPC5_LINIER_BEIE                    (1U << 13)
-#define SPC5_LINIER_OCIE                    (1U << 14)
-#define SPC5_LINIER_SZIE                    (1U << 15)
-/** @} */
-
-/**
- * @name    UARTSR register bits definitions
- * @{
- */
-#define SPC5_UARTSR_NF                      (1U << 0)
-#define SPC5_UARTSR_DTF                     (1U << 1)
-#define SPC5_UARTSR_DRF                     (1U << 2)
-#define SPC5_UARTSR_WUF                     (1U << 5)
-#define SPC5_UARTSR_RPS                     (1U << 6)
-#define SPC5_UARTSR_BOF                     (1U << 7)
-#define SPC5_UARTSR_FEF                     (1U << 8)
-#define SPC5_UARTSR_RMB                     (1U << 9)
-#define SPC5_UARTSR_PE0                     (1U << 10)
-#define SPC5_UARTSR_PE1                     (1U << 11)
-#define SPC5_UARTSR_PE2                     (1U << 12)
-#define SPC5_UARTSR_PE3                     (1U << 13)
-#define SPC5_UARTSR_OCF                     (1U << 14)
-#define SPC5_UARTSR_SZF                     (1U << 15)
-/** @} */
-
-/**
- * @name    UARTCR register bits definitions
- * @{
- */
-#define SPC5_UARTCR_UART                    (1U << 0)
-#define SPC5_UARTCR_WL                      (1U << 1)
-#define SPC5_UARTCR_PCE                     (1U << 2)
-#define SPC5_UARTCR_OP                      (1U << 3)
-#define SPC5_UARTCR_TXEN                    (1U << 4)
-#define SPC5_UARTCR_RXEN                    (1U << 5)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-
-struct spc5_linflex {
-
-  int16_t LINFLEX_reserved1;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CCD :1;
-      vuint16_t CFD :1;
-      vuint16_t LASE :1;
-      vuint16_t AWUM :1;
-      vuint16_t MBL :4;
-      vuint16_t BF :1;
-      vuint16_t SFTM :1;
-      vuint16_t LBKM :1;
-      vuint16_t MME :1;
-      vuint16_t SBDT :1;
-      vuint16_t RBLM :1;
-      vuint16_t SLEEP :1;
-      vuint16_t INIT :1;
-    } B;
-  } LINCR1;
-
-  int16_t LINFLEX_reserved2;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t SZIE :1;
-      vuint16_t OCIE :1;
-      vuint16_t BEIE :1;
-      vuint16_t CEIE :1;
-      vuint16_t HEIE :1;
-      vuint16_t :2;
-      vuint16_t FEIE :1;
-      vuint16_t BOIE :1;
-      vuint16_t LSIE :1;
-      vuint16_t WUIE :1;
-      vuint16_t DBFIE :1;
-      vuint16_t DBEIE :1;
-      vuint16_t DRIE :1;
-      vuint16_t DTIE :1;
-      vuint16_t HRIE :1;
-    } B;
-  } LINIER;
-
-  int16_t LINFLEX_reserved3;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t LINS :4;
-      vuint16_t :2;
-      vuint16_t RMB :1;
-      vuint16_t :1;
-      vuint16_t RBSY :1;
-      vuint16_t RPS :1;
-      vuint16_t WUF :1;
-      vuint16_t DBFF :1;
-      vuint16_t DBEF :1;
-      vuint16_t DRF :1;
-      vuint16_t DTF :1;
-      vuint16_t HRF :1;
-    } B;
-  } LINSR;
-
-  int16_t LINFLEX_reserved4;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t SZF :1;
-      vuint16_t OCF :1;
-      vuint16_t BEF :1;
-      vuint16_t CEF :1;
-      vuint16_t SFEF :1;
-      vuint16_t BDEF :1;
-      vuint16_t IDPEF :1;
-      vuint16_t FEF :1;
-      vuint16_t BOF :1;
-      vuint16_t :6;
-      vuint16_t NF :1;
-    } B;
-  } LINESR;
-
-  int16_t LINFLEX_reserved5;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :1;
-      vuint16_t TDFL :2;
-      vuint16_t :1;
-      vuint16_t RDFL :2;
-      vuint16_t :4;
-      vuint16_t RXEN :1;
-      vuint16_t TXEN :1;
-      vuint16_t OP :1;
-      vuint16_t PCE :1;
-      vuint16_t WL :1;
-      vuint16_t UART :1;
-    } B;
-  } UARTCR;
-
-  int16_t LINFLEX_reserved6;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t SZF :1;
-      vuint16_t OCF :1;
-      vuint16_t PE :4;
-      vuint16_t RMB :1;
-      vuint16_t FEF :1;
-      vuint16_t BOF :1;
-      vuint16_t RPS :1;
-      vuint16_t WUF :1;
-      vuint16_t :2;
-      vuint16_t DRF :1;
-      vuint16_t DTF :1;
-      vuint16_t NF :1;
-    } B;
-  } UARTSR;
-
-  int16_t LINFLEX_reserved7;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :5;
-      vuint16_t LTOM :1;
-      vuint16_t IOT :1;
-      vuint16_t TOCE :1;
-      vuint16_t CNT :8;
-    } B;
-  } LINTCSR;
-
-  int16_t LINFLEX_reserved8;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t OC2 :8;
-      vuint16_t OC1 :8;
-    } B;
-  } LINOCR;
-
-  int16_t LINFLEX_reserved9;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :4;
-      vuint16_t RTO :4;
-      vuint16_t :1;
-      vuint16_t HTO :7;
-    } B;
-  } LINTOCR;
-
-  int16_t LINFLEX_reserved10;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :12;
-      vuint16_t DIV_F :4;
-    } B;
-  } LINFBRR;
-
-  int16_t LINFLEX_reserved11;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t DIV_M :13;
-    } B;
-  } LINIBRR;
-
-  int16_t LINFLEX_reserved12;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :8;
-      vuint16_t CF :8;
-    } B;
-  } LINCFR;
-
-  int16_t LINFLEX_reserved13;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :1;
-      vuint16_t IOBE :1;
-      vuint16_t IOPE :1;
-      vuint16_t WURQ :1;
-      vuint16_t DDRQ :1;
-      vuint16_t DTRQ :1;
-      vuint16_t ABRQ :1;
-      vuint16_t HTRQ :1;
-      vuint16_t :8;
-    } B;
-  } LINCR2;
-
-  int16_t LINFLEX_reserved14;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t DFL :6;
-      vuint16_t DIR :1;
-      vuint16_t CCS :1;
-      vuint16_t :2;
-      vuint16_t ID :6;
-    } B;
-  } BIDR;
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t DATA3 :8;
-      vuint32_t DATA2 :8;
-      vuint32_t DATA1 :8;
-      vuint32_t DATA0 :8;
-    } B;
-  } BDRL;
-
-  union {
-    vuint32_t R;
-    struct {
-      vuint32_t DATA7 :8;
-      vuint32_t DATA6 :8;
-      vuint32_t DATA5 :8;
-      vuint32_t DATA4 :8;
-    } B;
-  } BDRM;
-
-  int16_t LINFLEX_reserved15;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :8;
-      vuint16_t FACT :8;
-    } B;
-  } IFER;
-
-  int16_t LINFLEX_reserved16;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :12;
-      vuint16_t IFMI :4;
-    } B;
-  } IFMI;
-
-  int16_t LINFLEX_reserved17;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :12;
-      vuint16_t IFM :4;
-    } B;
-  } IFMR;
-
-  int16_t LINFLEX_reserved18;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t DFL :3;
-      vuint16_t DIR :1;
-      vuint16_t CCS :1;
-      vuint16_t :2;
-      vuint16_t ID :6;
-    } B;
-  } IFCR0;
-
-  int16_t LINFLEX_reserved19;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t DFL :3;
-      vuint16_t DIR :1;
-      vuint16_t CCS :1;
-      vuint16_t :2;
-      vuint16_t ID :6;
-    } B;
-  } IFCR1;
-
-  int16_t LINFLEX_reserved20;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t DFL :3;
-      vuint16_t DIR :1;
-      vuint16_t CCS :1;
-      vuint16_t :2;
-      vuint16_t ID :6;
-    } B;
-  } IFCR2;
-
-  int16_t LINFLEX_reserved21;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t DFL :3;
-      vuint16_t DIR :1;
-      vuint16_t CCS :1;
-      vuint16_t :2;
-      vuint16_t ID :6;
-    } B;
-  } IFCR3;
-
-  int16_t LINFLEX_reserved22;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t DFL :3;
-      vuint16_t DIR :1;
-      vuint16_t CCS :1;
-      vuint16_t :2;
-      vuint16_t ID :6;
-    } B;
-  } IFCR4;
-
-  int16_t LINFLEX_reserved23;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t DFL :3;
-      vuint16_t DIR :1;
-      vuint16_t CCS :1;
-      vuint16_t :2;
-      vuint16_t ID :6;
-    } B;
-  } IFCR5;
-
-  int16_t LINFLEX_reserved24;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t DFL :3;
-      vuint16_t DIR :1;
-      vuint16_t CCS :1;
-      vuint16_t :2;
-      vuint16_t ID :6;
-    } B;
-  } IFCR6;
-
-  int16_t LINFLEX_reserved25;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t DFL :3;
-      vuint16_t DIR :1;
-      vuint16_t CCS :1;
-      vuint16_t :2;
-      vuint16_t ID :6;
-    } B;
-  } IFCR7;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    LINFlex units references
- * @{
- */
-#if SPC5_HAS_LINFLEX0 || defined(__DOXYGEN__)
-#define SPC5_LINFLEX0   (*(struct spc5_linflex *)0xFFE40000UL)
-#endif
-
-#if SPC5_HAS_LINFLEX1 || defined(__DOXYGEN__)
-#define SPC5_LINFLEX1   (*(struct spc5_linflex *)0xFFE44000UL)
-#endif
-
-#if SPC5_HAS_LINFLEX2 || defined(__DOXYGEN__)
-#define SPC5_LINFLEX2   (*(struct spc5_linflex *)0xFFE48000UL)
-#endif
-
-#if SPC5_HAS_LINFLEX3 || defined(__DOXYGEN__)
-#define SPC5_LINFLEX3   (*(struct spc5_linflex *)0xFFE4C000UL)
-#endif
-/** @} */
-
-#endif /* _SPC5_LINFLEX_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c
deleted file mode 100644
index d8ae4b2d5..000000000
--- a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/SIUL_v1/pal_lld.c
- * @brief   SPC5xx SIUL low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-#if defined(SPC5_SIUL_SYSTEM_PINS)
-static const unsigned system_pins[] = {SPC5_SIUL_SYSTEM_PINS};
-#endif
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   SPC5xx I/O ports configuration.
- *
- * @param[in] config    the STM32 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-  unsigned i;
-
-#if defined(SPC5_SIUL_PCTL)
-  /* SIUL clock gating if present.*/
-  halSPCSetPeripheralClockMode(SPC5_SIUL_PCTL,
-                               SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
-#endif
-
-  /* Initialize PCR registers for undefined pads.*/
-  for (i = 0; i < SPC5_SIUL_NUM_PCRS; i++) {
-#if defined(SPC5_SIUL_SYSTEM_PINS)
-    /* Handling the case where some SIU pins are not meant to be reprogrammed,
-       for example JTAG pins.*/
-    unsigned j;
-    for (j = 0; j < sizeof system_pins; j++) {
-      if (i == system_pins[j])
-        goto skip;
-    }
-    SIU.PCR[i].R = config->default_mode;
-skip:
-    ;
-#else
-    SIU.PCR[i].R = config->default_mode;
-#endif
-  }
-
-  /* Initialize PADSEL registers.*/
-  for (i = 0; i < SPC5_SIUL_NUM_PADSELS; i++)
-    SIU.PSMI[i].R = config->padsels[i];
-
-  /* Initialize PCR registers for defined pads.*/
-  i = 0;
-  while (config->inits[i].pcr_index != -1) {
-    SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value;
-    SIU.PCR[config->inits[i].pcr_index].R  = config->inits[i].pcr_value;
-    i++;
-  }
-}
-
-/**
- * @brief   Reads a group of bits.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-ioportmask_t _pal_lld_readgroup(ioportid_t port,
-                                ioportmask_t mask,
-                                uint_fast8_t offset) {
-
-  (void)port;
-  (void)mask;
-  (void)offset;
-  return 0;
-}
-
-/**
- * @brief   Writes a group of bits.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-void _pal_lld_writegroup(ioportid_t port,
-                         ioportmask_t mask,
-                         uint_fast8_t offset,
-                         ioportmask_t bits) {
-
-  (void)port;
-  (void)mask;
-  (void)offset;
-  (void)bits;
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-  unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH);
-  ioportmask_t m1 = 0x8000;
-  while (m1) {
-    if (mask & m1)
-      SIU.PCR[pcr_index].R = mode;
-    m1 >>= 1;
-    ++pcr_index;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h
deleted file mode 100644
index 5304ac36d..000000000
--- a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h
+++ /dev/null
@@ -1,427 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/SIUL_v1/pal_lld.h
- * @brief   SPC5xx SIUL low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_RESET
-#undef PAL_MODE_UNCONNECTED
-#undef PAL_MODE_INPUT
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_PUSHPULL
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/**
- * @name    SIUL-specific PAL modes
- * @{
- */
-#define PAL_SPC5_SMC                (1U << 14)
-#define PAL_SPC5_APC                (1U << 13)
-#define PAL_SPC5_PA_MASK            (3U << 10)
-#define PAL_SPC5_PA(n)              ((n) << 10)
-#define PAL_SPC5_OBE                (1U << 9)
-#define PAL_SPC5_IBE                (1U << 8)
-#define PAL_SPC5_ODE                (1U << 5)
-#define PAL_SPC5_SRC                (1U << 2)
-#define PAL_SPC5_WPE                (1U << 1)
-#define PAL_SPC5_WPS                (1U << 0)
-/** @} */
-
-/**
- * @name    Pads mode constants
- * @{
- */
-/**
- * @brief   After reset state.
- */
-#define PAL_MODE_RESET                  0
-
-/**
- * @brief   Safe state for <b>unconnected</b> pads.
- */
-#define PAL_MODE_UNCONNECTED            (PAL_SPC5_WPE | PAL_SPC5_WPS)
-
-/**
- * @brief   Regular input high-Z pad.
- */
-#define PAL_MODE_INPUT                  (PAL_SPC5_IBE)
-
-/**
- * @brief   Input pad with weak pull up resistor.
- */
-#define PAL_MODE_INPUT_PULLUP           (PAL_SPC5_IBE | PAL_SPC5_WPE |      \
-                                         PAL_SPC5_WPS)
-
-/**
- * @brief   Input pad with weak pull down resistor.
- */
-#define PAL_MODE_INPUT_PULLDOWN         (PAL_SPC5_IBE | PAL_SPC5_WPE)
-
-/**
- * @brief   Analog input mode.
- */
-#define PAL_MODE_INPUT_ANALOG           PAL_SPC5_APC
-
-/**
- * @brief   Push-pull output pad.
- */
-#define PAL_MODE_OUTPUT_PUSHPULL        (PAL_SPC5_IBE | PAL_SPC5_OBE)
-
-/**
- * @brief   Open-drain output pad.
- */
-#define PAL_MODE_OUTPUT_OPENDRAIN       (PAL_SPC5_IBE | PAL_SPC5_OBE |      \
-                                         PAL_SPC5_ODE)
-
-/**
- * @brief   Alternate "n" output pad.
- * @note    Both the IBE and OBE bits are specified in this mask, the OBE
- *          bit is not required for some PCRs but in that case it is
- *          ignored.
- */
-#define PAL_MODE_OUTPUT_ALTERNATE(n)    (PAL_SPC5_IBE | PAL_SPC5_OBE |      \
-                                         PAL_SPC5_PA(n))
-/** @} */
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 16
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint16_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint16_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- *          any assumption about it, use the provided macros when populating
- *          variables of this type.
- */
-typedef uint32_t ioportid_t;
-
-/**
- * @brief   SIUL register initializer type.
- */
-typedef struct {
-  int32_t                   pcr_index;
-  uint8_t                   gpdo_value;
-  iomode_t                  pcr_value;
-} spc_siu_init_t;
-
-/**
- * @brief   Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  iomode_t                  default_mode;
-  const spc_siu_init_t      *inits;
-  const uint8_t             *padsels;
-} PALConfig;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   I/O port A identifier.
- */
-#define PORT_A          0
-
-/**
- * @brief   I/O port B identifier.
- */
-#define PORT_B          1
-
-/**
- * @brief   I/O port C identifier.
- */
-#define PORT_C          2
-
-/**
- * @brief   I/O port D identifier.
- */
-#define PORT_D          3
-
-/**
- * @brief   I/O port E identifier.
- */
-#define PORT_E          4
-
-/**
- * @brief   I/O port F identifier.
- */
-#define PORT_F          5
-
-/**
- * @brief   I/O port G identifier.
- */
-#define PORT_G          6
-
-/**
- * @brief   I/O port H identifier.
- */
-#define PORT_H          7
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Port bit helper macro.
- * @note    Overrides the one in @p pal.h.
- *
- * @param[in] n         bit position within the port
- *
- * @return              The bit mask.
- */
-#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n)))
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port])
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port])
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits)                                       \
-  (((volatile uint16_t *)SIU.PGPDO)[port] = (bits))
-
-/**
- * @brief   Reads a group of bits.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset)                               \
-  _pal_lld_readgroup(port, mask, offset)
-
-/**
- * @brief   Writes a group of bits.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                        \
-  _pal_lld_writegroup(port, mask, offset, bits)
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Reads a logical state from an I/O pad.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @return              The logical state.
- * @retval PAL_LOW      low logical state.
- * @retval PAL_HIGH     high logical state.
- *
- * @notapi
- */
-#define pal_lld_readpad(port, pad)                                          \
-  (SIU.GPDI[((port) * 16) + (pad)].R)
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)                                    \
-  (SIU.GPDO[((port) * 16) + (pad)].R = (bit))
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-  (SIU.GPDO[((port) * 16) + (pad)].R = 1)
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-  (SIU.GPDO[((port) * 16) + (pad)].R = 0)
-
-/**
- * @brief   Toggles a pad logical state.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad)                                        \
-  (SIU.GPDO[((port) * 16) + (pad)].R = ~SIU.GPDO[((port) * 16) + (pad)].R)
-
-/**
- * @brief   Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] mode      pad mode
- *
- * @notapi
- */
-#define pal_lld_setpadmode(port, pad, mode)
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  ioportmask_t _pal_lld_readgroup(ioportid_t port,
-                                  ioportmask_t mask,
-                                  uint_fast8_t offset);
-  void _pal_lld_writegroup(ioportid_t port,
-                           ioportmask_t mask,
-                           uint_fast8_t offset,
-                           ioportmask_t bits);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c
deleted file mode 100644
index 1d77a177a..000000000
--- a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/SIU_v1/pal_lld.c
- * @brief   SPC5xx SIU low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-#if defined(SPC5_SIU_SYSTEM_PINS)
-static const unsigned system_pins[] = {SPC5_SIU_SYSTEM_PINS};
-#endif
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   SPC5xx I/O ports configuration.
- *
- * @param[in] config    the STM32 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-  unsigned i;
-
-  /* Initialize PCR registers for defined pads.*/
-  i = 0;
-  while (config->inits[i].pcr_index != -1) {
-    SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value;
-    SIU.PCR[config->inits[i].pcr_index].R  = config->inits[i].pcr_value;
-    i++;
-  }
-}
-
-/**
- * @brief   Reads a group of bits.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-ioportmask_t _pal_lld_readgroup(ioportid_t port,
-                                ioportmask_t mask,
-                                uint_fast8_t offset) {
-
-  (void)port;
-  (void)mask;
-  (void)offset;
-  return 0;
-}
-
-/**
- * @brief   Writes a group of bits.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-void _pal_lld_writegroup(ioportid_t port,
-                         ioportmask_t mask,
-                         uint_fast8_t offset,
-                         ioportmask_t bits) {
-
-  (void)port;
-  (void)mask;
-  (void)offset;
-  (void)bits;
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-  unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH);
-  ioportmask_t m1 = 0x8000;
-  while (m1) {
-    if (mask & m1)
-      SIU.PCR[pcr_index].R = mode;
-    m1 >>= 1;
-    ++pcr_index;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h
deleted file mode 100644
index b9c72bf0c..000000000
--- a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h
+++ /dev/null
@@ -1,423 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/SIU_v1/pal_lld.h
- * @brief   SPC5xx SIU low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_RESET
-#undef PAL_MODE_UNCONNECTED
-#undef PAL_MODE_INPUT
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_PUSHPULL
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/**
- * @name    SIU-specific PAL modes
- * @{
- */
-#define PAL_SPC5_PA_MASK            (15U << 10)
-#define PAL_SPC5_PA(n)              ((n) << 10)
-#define PAL_SPC5_OBE                (1U << 9)
-#define PAL_SPC5_IBE                (1U << 8)
-#define PAL_SPC5_DSC_10PF           (0U << 6)
-#define PAL_SPC5_DSC_20PF           (1U << 6)
-#define PAL_SPC5_DSC_30PF           (2U << 6)
-#define PAL_SPC5_DSC_50PF           (3U << 6)
-#define PAL_SPC5_ODE                (1U << 5)
-#define PAL_SPC5_HYS                (1U << 4)
-#define PAL_SPC5_WPE                (1U << 1)
-#define PAL_SPC5_WPS                (1U << 0)
-/** @} */
-
-/**
- * @name    Pads mode constants
- * @{
- */
-/**
- * @brief   After reset state.
- */
-#define PAL_MODE_RESET                  0
-
-/**
- * @brief   Safe state for <b>unconnected</b> pads.
- */
-#define PAL_MODE_UNCONNECTED            (PAL_SPC5_WPE | PAL_SPC5_WPS)
-
-/**
- * @brief   Regular input high-Z pad.
- */
-#define PAL_MODE_INPUT                  (PAL_SPC5_IBE)
-
-/**
- * @brief   Input pad with weak pull up resistor.
- */
-#define PAL_MODE_INPUT_PULLUP           (PAL_SPC5_IBE | PAL_SPC5_WPE |      \
-                                         PAL_SPC5_WPS)
-
-/**
- * @brief   Input pad with weak pull down resistor.
- */
-#define PAL_MODE_INPUT_PULLDOWN         (PAL_SPC5_IBE | PAL_SPC5_WPE)
-
-/**
- * @brief   Push-pull output pad.
- */
-#define PAL_MODE_OUTPUT_PUSHPULL        (PAL_SPC5_IBE | PAL_SPC5_OBE)
-
-/**
- * @brief   Open-drain output pad.
- */
-#define PAL_MODE_OUTPUT_OPENDRAIN       (PAL_SPC5_IBE | PAL_SPC5_OBE |      \
-                                         PAL_SPC5_ODE)
-
-/**
- * @brief   Alternate "n" output pad.
- * @note    Both the IBE and OBE bits are specified in this mask, the OBE
- *          bit is not required for some PCRs but in that case it is
- *          ignored.
- */
-#define PAL_MODE_OUTPUT_ALTERNATE(n)    (PAL_SPC5_IBE | PAL_SPC5_OBE |      \
-                                         PAL_SPC5_PA(n))
-/** @} */
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 16
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint16_t ioportmask_t;
-
-/**
- * @brief   Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- *          any assumption about it, use the provided macros when populating
- *          variables of this type.
- */
-typedef uint32_t ioportid_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint16_t iomode_t;
-
-/**
- * @brief   SIU/SIUL register initializer type.
- */
-typedef struct {
-  int32_t                   pcr_index;
-  uint8_t                   gpdo_value;
-  iomode_t                  pcr_value;
-} spc_siu_init_t;
-
-/**
- * @brief   Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  const spc_siu_init_t      *inits;
-} PALConfig;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    Port identifiers
- * @{
- */
-#define PORT0           0
-#define PORT1           1
-#define PORT2           2
-#define PORT3           3
-#define PORT4           4
-#define PORT5           5
-#define PORT6           6
-#define PORT7           7
-#define PORT8           8
-#define PORT9           9
-#define PORT10          10
-#define PORT11          11
-#define PORT12          12
-#define PORT13          13
-#define PORT14          14
-#define PORT15          15
-#define PORT16          16
-#define PORT17          17
-#define PORT18          18
-#define PORT19          19
-#define PORT20          20
-#define PORT21          21
-#define PORT22          22
-#define PORT23          23
-#define PORT24          24
-#define PORT25          25
-#define PORT26          26
-#define PORT27          27
-#define PORT28          28
-#define PORT29          29
-#define PORT30          30
-#define PORT31          31
-/** @} */
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Port bit helper macro.
- * @note    Overrides the one in @p pal.h.
- *
- * @param[in] n         bit position within the port
- *
- * @return              The bit mask.
- */
-#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n)))
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-#if SPC5_SIU_SUPPORTS_PORTS || defined(__DOXYGEN__)
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port])
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port])
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits)                                       \
-  (((volatile uint16_t *)SIU.PGPDO)[port] = (bits))
-
-/**
- * @brief   Reads a group of bits.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset)                               \
-  _pal_lld_readgroup(port, mask, offset)
-
-/**
- * @brief   Writes a group of bits.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                        \
-  _pal_lld_writegroup(port, mask, offset, bits)
-
-#endif /* SPC5_SIU_SUPPORTS_PORTS */
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Reads a logical state from an I/O pad.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @return              The logical state.
- * @retval PAL_LOW      low logical state.
- * @retval PAL_HIGH     high logical state.
- *
- * @notapi
- */
-#define pal_lld_readpad(port, pad)                                          \
-  (SIU.GPDI[((port) * 16) + (pad)].R)
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)                                    \
-  (SIU.GPDO[((port) * 16) + (pad)].R = (bit))
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)                                           \
-  (SIU.GPDO[((port) * 16) + (pad)].R = 1)
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)                                         \
-  (SIU.GPDO[((port) * 16) + (pad)].R = 0)
-
-/**
- * @brief   Toggles a pad logical state.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad)                                        \
-  (SIU.GPDO[((port) * 16) + (pad)].R = ~SIU.GPDO[((port) * 16) + (pad)].R)
-
-/**
- * @brief   Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] mode      pad mode
- *
- * @notapi
- */
-#define pal_lld_setpadmode(port, pad, mode)
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  ioportmask_t _pal_lld_readgroup(ioportid_t port,
-                                  ioportmask_t mask,
-                                  uint_fast8_t offset);
-  void _pal_lld_writegroup(ioportid_t port,
-                           ioportmask_t mask,
-                           uint_fast8_t offset,
-                           ioportmask_t bits);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c
deleted file mode 100644
index 6ada01818..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c
+++ /dev/null
@@ -1,919 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/eMIOS200_v1/icu_lld.c
- * @brief   SPC5xx low level icu driver code.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ICUD1 driver identifier.
- * @note    The driver ICUD1 allocates the unified channel eMIOS_CH1
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH1 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-
-/**
- * @brief   ICUD2 driver identifier.
- * @note    The driver ICUD2 allocates the unified channel eMIOS_CH2
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH2 || defined(__DOXYGEN__)
-ICUDriver ICUD2;
-#endif
-
-/**
- * @brief   ICUD3 driver identifier.
- * @note    The driver ICUD3 allocates the unified channel eMIOS_CH3
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH3 || defined(__DOXYGEN__)
-ICUDriver ICUD3;
-#endif
-
-
-/**
- * @brief   ICUD4 driver identifier.
- * @note    The driver ICUD4 allocates the unified channel eMIOS_CH4
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH4 || defined(__DOXYGEN__)
-ICUDriver ICUD4;
-#endif
-
-/**
- * @brief   ICUD5 driver identifier.
- * @note    The driver ICUD5 allocates the unified channel eMIOS_CH5
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH5 || defined(__DOXYGEN__)
-ICUDriver ICUD5;
-#endif
-
-/**
- * @brief   ICUD6 driver identifier.
- * @note    The driver ICUD6 allocates the unified channel eMIOS_CH6
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH6 || defined(__DOXYGEN__)
-ICUDriver ICUD6;
-#endif
-
-/**
- * @brief   ICUD7 driver identifier.
- * @note    The driver ICUD7 allocates the unified channel eMIOS_CH11
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH11 || defined(__DOXYGEN__)
-ICUDriver ICUD7;
-#endif
-
-/**
- * @brief   ICUD8 driver identifier.
- * @note    The driver ICUD8 allocates the unified channel eMIOS_CH13
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH13 || defined(__DOXYGEN__)
-ICUDriver ICUD8;
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-/**
- * @brief   ICUD9 driver identifier.
- * @note    The driver ICUD9 allocates the unified channel eMIOS_CH7
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH7 || defined(__DOXYGEN__)
-ICUDriver ICUD9;
-#endif
-
-/**
- * @brief   ICUD10 driver identifier.
- * @note    The driver ICUD10 allocates the unified channel eMIOS_CH16
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH16 || defined(__DOXYGEN__)
-ICUDriver ICUD10;
-#endif
-
-/**
- * @brief   ICUD11 driver identifier.
- * @note    The driver ICUD11 allocates the unified channel eMIOS_CH17
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH17 || defined(__DOXYGEN__)
-ICUDriver ICUD11;
-#endif
-
-/**
- * @brief   ICUD12 driver identifier.
- * @note    The driver ICUD12 allocates the unified channel eMIOS_CH18
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS_CH18 || defined(__DOXYGEN__)
-ICUDriver ICUD12;
-#endif
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Width and Period registers.
- */
-uint32_t width;
-uint32_t period;
-
-/**
- * @brief   A2 temp registers.
- */
-uint32_t A2_1, A2_2, A2_3;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief               ICU IRQ handler.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
-
-  uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R;
-
-  if (sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL) {
-    icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC;
-    _icu_isr_invoke_overflow_cb(icup);
-  }
-  if (sr && EMIOSS_FLAG) {
-    icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC;
-    if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
-      if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U  &&            \
-          icup->config->period_cb != NULL) {
-        A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
-        period = A2_3 - A2_1;
-        _icu_isr_invoke_period_cb(icup);
-        A2_1 = A2_3;
-      } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 &&       \
-          icup->config->width_cb != NULL) {
-        A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
-        width = A2_2 - A2_1;
-        _icu_isr_invoke_width_cb(icup);
-      }
-    } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) {
-      if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U &&             \
-          icup->config->width_cb != NULL) {
-        A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
-        width = A2_2 - A2_1;
-        _icu_isr_invoke_width_cb(icup);
-      } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 &&       \
-          icup->config->period_cb != NULL) {
-        A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
-        period = A2_3 - A2_1;
-        _icu_isr_invoke_period_cb(icup);
-        A2_1 = A2_3;
-      }
-    }
-  }
-  if (sr && EMIOSS_OVR) {
-    icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC;
-  }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS_CH1
-#if !defined(SPC5_EMIOS_FLAG_F1_HANDLER)
-#error "SPC5_EMIOS_FLAG_F1_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 1 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH1 */
-
-#if SPC5_ICU_USE_EMIOS_CH2
-#if !defined(SPC5_EMIOS_FLAG_F2_HANDLER)
-#error "SPC5_EMIOS_FLAG_F2_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 2 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH2 */
-
-#if SPC5_ICU_USE_EMIOS_CH3
-#if !defined(SPC5_EMIOS_FLAG_F3_HANDLER)
-#error "SPC5_EMIOS_FLAG_F3_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 3 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH3 */
-
-#if SPC5_ICU_USE_EMIOS_CH4
-#if !defined(SPC5_EMIOS_FLAG_F4_HANDLER)
-#error "SPC5_EMIOS_FLAG_F4_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 4 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F4_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH4 */
-
-#if SPC5_ICU_USE_EMIOS_CH5
-#if !defined(SPC5_EMIOS_FLAG_F5_HANDLER)
-#error "SPC5_EMIOS_FLAG_F5_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 5 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F5_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH5 */
-
-#if SPC5_ICU_USE_EMIOS_CH6
-#if !defined(SPC5_EMIOS_FLAG_F6_HANDLER)
-#error "SPC5_EMIOS_FLAG_F6_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 6 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F6_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH6 */
-
-#if SPC5_ICU_USE_EMIOS_CH11
-#if !defined(SPC5_EMIOS_FLAG_F11_HANDLER)
-#error "SPC5_EMIOS_FLAG_F11_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 11 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F11_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD7);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH11 */
-
-#if SPC5_ICU_USE_EMIOS_CH13
-#if !defined(SPC5_EMIOS_FLAG_F13_HANDLER)
-#error "SPC5_EMIOS_FLAG_F13_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 13 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F13_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD8);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH13 */
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-#if SPC5_ICU_USE_EMIOS_CH7
-#if !defined(SPC5_EMIOS_FLAG_F7_HANDLER)
-#error "SPC5_EMIOS_FLAG_F7_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 7 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F7_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD9);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH7 */
-
-#if SPC5_ICU_USE_EMIOS_CH16
-#if !defined(SPC5_EMIOS_FLAG_F16_HANDLER)
-#error "SPC5_EMIOS_FLAG_F16_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 16 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F16_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD10);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH16 */
-
-#if SPC5_ICU_USE_EMIOS_CH17
-#if !defined(SPC5_EMIOS_FLAG_F17_HANDLER)
-#error "SPC5_EMIOS_FLAG_F17_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 17 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F17_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD11);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH17 */
-
-#if SPC5_ICU_USE_EMIOS_CH18
-#if !defined(SPC5_EMIOS_FLAG_F18_HANDLER)
-#error "SPC5_EMIOS_FLAG_F18_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS Channel 18 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F18_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD12);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS_CH18 */
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
-  /* Initialize A2 temp registers.*/
-  A2_1 = 0U;
-  A2_2 = 0U;
-  A2_3 = 0U;
-
-  /* eMIOSx channels initially all not in use.*/
-  reset_emios_active_channels();
-
-#if SPC5_ICU_USE_EMIOS_CH1
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD1);
-  ICUD1.emiosp = &EMIOS;
-  ICUD1.ch_number = 1U;
-  ICUD1.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH1 */
-
-#if SPC5_ICU_USE_EMIOS_CH2
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD2);
-  ICUD2.emiosp = &EMIOS;
-  ICUD2.ch_number = 2U;
-  ICUD2.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH2 */
-
-#if SPC5_ICU_USE_EMIOS_CH3
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD3);
-  ICUD3.emiosp = &EMIOS;
-  ICUD3.ch_number = 3U;
-  ICUD3.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH3 */
-
-#if SPC5_ICU_USE_EMIOS_CH4
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD4);
-  ICUD4.emiosp = &EMIOS;
-  ICUD4.ch_number = 4U;
-  ICUD4.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH4 */
-
-#if SPC5_ICU_USE_EMIOS_CH5
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD5);
-  ICUD5.emiosp = &EMIOS;
-  ICUD5.ch_number = 5U;
-  ICUD5.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH5 */
-
-#if SPC5_ICU_USE_EMIOS_CH6
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD6);
-  ICUD6.emiosp = &EMIOS;
-  ICUD6.ch_number = 6U;
-  ICUD6.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH6 */
-
-#if SPC5_ICU_USE_EMIOS_CH11
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD7);
-  ICUD7.emiosp = &EMIOS;
-  ICUD7.ch_number = 11U;
-  ICUD7.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH11 */
-
-#if SPC5_ICU_USE_EMIOS_CH13
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD8);
-  ICUD8.emiosp = &EMIOS;
-  ICUD8.ch_number = 13U;
-  ICUD8.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH13 */
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-#if SPC5_ICU_USE_EMIOS_CH7
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD9);
-  ICUD9.emiosp = &EMIOS;
-  ICUD9.ch_number = 7U;
-  ICUD9.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH7 */
-
-#if SPC5_ICU_USE_EMIOS_CH16
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD10);
-  ICUD10.emiosp = &EMIOS;
-  ICUD10.ch_number = 16U;
-  ICUD10.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH16 */
-
-#if SPC5_ICU_USE_EMIOS_CH17
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD11);
-  ICUD11.emiosp = &EMIOS;
-  ICUD11.ch_number = 17U;
-  ICUD11.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH17 */
-
-#if SPC5_ICU_USE_EMIOS_CH18
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD12);
-  ICUD12.emiosp = &EMIOS;
-  ICUD12.ch_number = 18U;
-  ICUD12.clock = SPC5_EMIOS_CLK;
-#endif /* SPC5_ICU_USE_EMIOS_CH18 */
-#endif
-
-#if SPC5_ICU_USE_EMIOS
-
-#if SPC5_EMIOS_NUM_CHANNELS == 16
-    INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY;
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-    INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F7_NUMBER].R = SPC5_EMIOS_FLAG_F7_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F16_NUMBER].R = SPC5_EMIOS_FLAG_F16_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F17_NUMBER].R = SPC5_EMIOS_FLAG_F17_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F18_NUMBER].R = SPC5_EMIOS_FLAG_F18_PRIORITY;
-#endif
-
-#endif
-}
-
-/**
- * @brief   Configures and activates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-
-  chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
-		      "icu_lld_start(), #1", "too many channels");
-
-  if (icup->state == ICU_STOP) {
-    /* Enables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS_CH1
-    if (&ICUD1 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH1 */
-#if SPC5_ICU_USE_EMIOS_CH2
-    if (&ICUD2 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH2 */
-#if SPC5_ICU_USE_EMIOS_CH3
-    if (&ICUD3 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH3 */
-#if SPC5_ICU_USE_EMIOS_CH4
-    if (&ICUD4 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH4 */
-#if SPC5_ICU_USE_EMIOS_CH5
-    if (&ICUD5 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH5 */
-#if SPC5_ICU_USE_EMIOS_CH6
-    if (&ICUD6 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH6 */
-#if SPC5_ICU_USE_EMIOS_CH11
-    if (&ICUD7 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH11 */
-#if SPC5_ICU_USE_EMIOS_CH13
-    if (&ICUD8 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH13 */
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-#if SPC5_ICU_USE_EMIOS_CH7
-    if (&ICUD9 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH7 */
-#if SPC5_ICU_USE_EMIOS_CH16
-    if (&ICUD10 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH16 */
-#if SPC5_ICU_USE_EMIOS_CH17
-    if (&ICUD11 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH17 */
-#if SPC5_ICU_USE_EMIOS_CH18
-    if (&ICUD12 == icup)
-      increase_emios_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS_CH18 */
-#endif
-
-    /* Set eMIOS Clock.*/
-#if SPC5_ICU_USE_EMIOS
-    icu_active_emios_clock(icup);
-#endif
-
-  }
-  /* Configures the peripheral.*/
-
-  /* Channel enables.*/
-  icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
-  /* Clear pending IRQs (if any).*/
-  icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
-      EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-  /* Set clock prescaler and control register.*/
-  uint32_t psc = (icup->clock / icup->config->frequency);
-  chDbgAssert((psc <= 4) &&
-              ((psc * icup->config->frequency) == icup->clock) &&
-              ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
-              "icu_lld_start(), #1", "invalid frequency");
-
-  icup->emiosp->CH[icup->ch_number].CCR.B.UCPREN = 0;
-  icup->emiosp->CH[icup->ch_number].CCR.R |=
-      EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) |
-      EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC;
-  icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1;
-  icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN;
-
-  /* Set source polarity.*/
-  if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
-    icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL;
-  } else {
-    icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL;
-  }
-
-  /* Direct pointers to the period and width registers in order to make
-     reading data faster from within callbacks.*/
-  icup->pccrp = &period;
-  icup->wccrp = &width;
-
-  /* Channel disables.*/
-  icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-/**
- * @brief   Deactivates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
-  chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
-		  	  "icu_lld_stop(), #1", "too many channels");
-
-  if (icup->state == ICU_READY) {
-
-    /* Disables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS_CH1
-    if (&ICUD1 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH1 */
-#if SPC5_ICU_USE_EMIOS_CH2
-    if (&ICUD2 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH2 */
-#if SPC5_ICU_USE_EMIOS_CH3
-    if (&ICUD3 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH3 */
-#if SPC5_ICU_USE_EMIOS_CH4
-    if (&ICUD4 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH4 */
-#if SPC5_ICU_USE_EMIOS_CH5
-    if (&ICUD5 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH5 */
-#if SPC5_ICU_USE_EMIOS_CH6
-    if (&ICUD6 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH6 */
-#if SPC5_ICU_USE_EMIOS_CH11
-    if (&ICUD7 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH11 */
-#if SPC5_ICU_USE_EMIOS_CH13
-    if (&ICUD8 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH13 */
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-#if SPC5_ICU_USE_EMIOS_CH7
-    if (&ICUD9 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH7 */
-#if SPC5_ICU_USE_EMIOS_CH16
-    if (&ICUD10 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH16 */
-#if SPC5_ICU_USE_EMIOS_CH17
-    if (&ICUD11 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH17 */
-#if SPC5_ICU_USE_EMIOS_CH18
-    if (&ICUD12 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS_CH18 */
-#endif
-
-    /* eMIOS clock deactivation.*/
-#if SPC5_ICU_USE_EMIOS
-    deactive_emios_clock();
-#endif
-
-  }
-}
-
-/**
- * @brief   Enables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
-  /* Clear pending IRQs (if any).*/
-  icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
-      EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-  /* Active interrupts.*/
-  if (icup->config->period_cb != NULL || icup->config->width_cb != NULL ||  \
-      icup->config->overflow_cb != NULL) {
-    icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U;
-  }
-
-  /* Channel enables.*/
-  icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
-}
-
-/**
- * @brief   Disables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
-  /* Clear pending IRQs (if any).*/
-  icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
-        EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-  /* Disable interrupts.*/
-  icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0;
-
-  /* Channel disables.*/
-  icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h
deleted file mode 100644
index 656476a98..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h
+++ /dev/null
@@ -1,457 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/eMIOS200_v1/icu_lld.h
- * @brief   SPC5xx low level icu driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ICUD1 driver enable switch.
- * @details If set to @p TRUE the support for ICUD1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH1) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH1              FALSE
-#endif
-
-/**
- * @brief   ICUD2 driver enable switch.
- * @details If set to @p TRUE the support for ICUD2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH2) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH2              FALSE
-#endif
-
-/**
- * @brief   ICUD3 driver enable switch.
- * @details If set to @p TRUE the support for ICUD3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH3) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH3              FALSE
-#endif
-
-/**
- * @brief   ICUD4 driver enable switch.
- * @details If set to @p TRUE the support for ICUD4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH4) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH4              FALSE
-#endif
-
-/**
- * @brief   ICUD5 driver enable switch.
- * @details If set to @p TRUE the support for ICUD5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH5) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH5              FALSE
-#endif
-
-/**
- * @brief   ICUD6 driver enable switch.
- * @details If set to @p TRUE the support for ICUD6 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH6) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH6              FALSE
-#endif
-
-/**
- * @brief   ICUD7 driver enable switch.
- * @details If set to @p TRUE the support for ICUD7 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH11) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH11             FALSE
-#endif
-
-/**
- * @brief   ICUD8 driver enable switch.
- * @details If set to @p TRUE the support for ICUD8 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH13) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH13             FALSE
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-/**
- * @brief   ICUD9 driver enable switch.
- * @details If set to @p TRUE the support for ICUD9 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH7) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH7              FALSE
-#endif
-
-/**
- * @brief   ICUD10 driver enable switch.
- * @details If set to @p TRUE the support for ICUD10 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH16) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH16             FALSE
-#endif
-
-/**
- * @brief   ICUD11 driver enable switch.
- * @details If set to @p TRUE the support for ICUD11 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH17) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH17             FALSE
-#endif
-
-/**
- * @brief   ICUD12 driver enable switch.
- * @details If set to @p TRUE the support for ICUD12 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS_CH18) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS_CH18             FALSE
-#endif
-#endif
-
-/**
- * @brief   ICUD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F1_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F2_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F2_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F3_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F4_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F4_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F5_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD6 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F6_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F6_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD7 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F11_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F11_PRIORITY        7
-#endif
-
-/**
- * @brief   ICUD8 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F13_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F13_PRIORITY        7
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-/**
- * @brief   ICUD9 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F7_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD10 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F16_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F16_PRIORITY        7
-#endif
-
-/**
- * @brief   ICUD11 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F17_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F17_PRIORITY        7
-#endif
-
-/**
- * @brief   ICUD12 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F18_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F18_PRIORITY        7
-#endif
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS
-#error "EMIOS not present in the selected device"
-#endif
-#if SPC5_EMIOS_NUM_CHANNELS == 16
-#define SPC5_ICU_USE_EMIOS                  (SPC5_ICU_USE_EMIOS_CH1  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH2  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH3  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH4  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH5  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH6  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH11 ||     \
-                                             SPC5_ICU_USE_EMIOS_CH13)
-#elif SPC5_EMIOS_NUM_CHANNELS == 24
-#define SPC5_ICU_USE_EMIOS                  (SPC5_ICU_USE_EMIOS_CH1  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH2  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH3  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH4  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH5  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH6  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH11 ||     \
-                                             SPC5_ICU_USE_EMIOS_CH13 ||     \
-                                             SPC5_ICU_USE_EMIOS_CH7  ||     \
-                                             SPC5_ICU_USE_EMIOS_CH16 ||     \
-                                             SPC5_ICU_USE_EMIOS_CH17 ||     \
-                                             SPC5_ICU_USE_EMIOS_CH18)
-#endif
-
-#if !SPC5_ICU_USE_EMIOS
-#error "ICU driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief ICU driver mode.
- */
-typedef enum {
-  ICU_INPUT_ACTIVE_HIGH = 0,        /**< Trigger on rising edge.            */
-  ICU_INPUT_ACTIVE_LOW = 1,         /**< Trigger on falling edge.           */
-} icumode_t;
-
-/**
- * @brief   ICU frequency type.
- */
-typedef uint32_t icufreq_t;
-
-/**
- * @brief   ICU counter type.
- */
-typedef uint32_t icucnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Driver mode.
-   */
-  icumode_t     mode;
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  icufreq_t     frequency;
-  /**
-   * @brief   Callback for pulse width measurement.
-   */
-  icucallback_t width_cb;
-  /**
-   * @brief   Callback for cycle period measurement.
-   */
-  icucallback_t period_cb;
-  /**
-   * @brief   Callback for timer overflow.
-   */
-  icucallback_t overflow_cb;
-  /* End of the mandatory fields.*/
-} ICUConfig;
-
-/**
- * @brief   Structure representing an ICU driver.
- */
-struct ICUDriver {
-  /**
-   * @brief Driver state.
-   */
-  icustate_t                state;
-  /**
-   * @brief eMIOSx channel number.
-   */
-  uint32_t                  ch_number;
-  /**
-   * @brief Current configuration data.
-   */
-  const ICUConfig           *config;
-  /**
-   * @brief CH Counter clock.
-   */
-  uint32_t clock;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the eMIOSx registers block.
-   */
-  volatile struct EMIOS_tag *emiosp;
-  /**
-   * @brief CCR register used for width capture.
-   */
-  volatile vuint32_t        *wccrp;
-  /**
-   * @brief CCR register used for period capture.
-   */
-  volatile vuint32_t        *pccrp;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- *          edge and the stop edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
-
-/**
- * @brief   Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- *          edge and the next start edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS_CH1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH2 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD2;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH3 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD3;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH4 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD4;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH5 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD5;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH6 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD6;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH11 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD7;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH13 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD8;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH7 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD9;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH16 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD10;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH17 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD11;
-#endif
-
-#if SPC5_ICU_USE_EMIOS_CH18 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD12;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void icu_lld_init(void);
-  void icu_lld_start(ICUDriver *icup);
-  void icu_lld_stop(ICUDriver *icup);
-  void icu_lld_enable(ICUDriver *icup);
-  void icu_lld_disable(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c
deleted file mode 100644
index 7db39f46e..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c
+++ /dev/null
@@ -1,961 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/eMIOS200_v1/pwm_lld.c
- * @brief   SPC5xx low level pwm driver code.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PWMD1 driver identifier.
- * @note    The driver PWMD1 allocates the unified channel EMIOS_CH0
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief   PWMD2 driver identifier.
- * @note    The driver PWMD2 allocates the unified channel EMIOS_CH8
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH8 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief   PWMD3 driver identifier.
- * @note    The driver PWMD3 allocates the unified channel EMIOS_CH9
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH9 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief   PWMD4 driver identifier.
- * @note    The driver PWMD4 allocates the unified channel EMIOS_CH10
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH10 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/**
- * @brief   PWMD5 driver identifier.
- * @note    The driver PWMD5 allocates the unified channel EMIOS_CH12
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH12 || defined(__DOXYGEN__)
-PWMDriver PWMD5;
-#endif
-
-/**
- * @brief   PWMD6 driver identifier.
- * @note    The driver PWMD6 allocates the unified channel EMIOS_CH14
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH14 || defined(__DOXYGEN__)
-PWMDriver PWMD6;
-#endif
-
-/**
- * @brief   PWMD7 driver identifier.
- * @note    The driver PWMD7 allocates the unified channel EMIOS_CH15
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH15 || defined(__DOXYGEN__)
-PWMDriver PWMD7;
-#endif
-
-/**
- * @brief   PWMD8 driver identifier.
- * @note    The driver PWMD8 allocates the unified channel EMIOS_CH23
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH23 || defined(__DOXYGEN__)
-PWMDriver PWMD8;
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-/**
- * @brief   PWMD9 driver identifier.
- * @note    The driver PWMD9 allocates the unified channel EMIOS_CH19
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH19 || defined(__DOXYGEN__)
-PWMDriver PWMD9;
-#endif
-
-/**
- * @brief   PWMD10 driver identifier.
- * @note    The driver PWMD10 allocates the unified channel EMIOS_CH20
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH20 || defined(__DOXYGEN__)
-PWMDriver PWMD10;
-#endif
-
-/**
- * @brief   PWMD11 driver identifier.
- * @note    The driver PWMD11 allocates the unified channel EMIOS_CH21
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH21 || defined(__DOXYGEN__)
-PWMDriver PWMD11;
-#endif
-
-/**
- * @brief   PWMD12 driver identifier.
- * @note    The driver PWMD12 allocates the unified channel EMIOS_CH22
- *          when enabled.
- */
-#if SPC5_PWM_USE_EMIOS_CH22 || defined(__DOXYGEN__)
-PWMDriver PWMD12;
-#endif
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief               PWM IRQ handler.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
-
-  uint32_t sr = pwmp->emiosp->CH[pwmp->ch_number].CSR.R;
-
-  if (sr && EMIOSS_OVFL) {
-    pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVFLC;
-  }
-  if (sr && EMIOSS_OVR) {
-    pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVRC;
-  }
-  if (sr && EMIOSS_FLAG) {
-    pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_FLAGC;
-
-    if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) {
-      if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U  &&           \
-          pwmp->config->callback != NULL) {
-        pwmp->config->callback(pwmp);
-      } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0 &&      \
-          pwmp->config->channels[0].callback != NULL) {
-        pwmp->config->channels[0].callback(pwmp);
-      }
-    } else if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) {
-      if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0  &&            \
-          pwmp->config->callback != NULL) {
-        pwmp->config->callback(pwmp);
-      } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U &&     \
-          pwmp->config->channels[0].callback != NULL) {
-        pwmp->config->channels[0].callback(pwmp);
-      }
-    }
-  }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS_CH0
-#if !defined(SPC5_EMIOS_FLAG_F0_HANDLER)
-#error "SPC5_EMIOS_FLAG_F0_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 0 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F0_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH0 */
-
-#if SPC5_PWM_USE_EMIOS_CH8
-#if !defined(SPC5_EMIOS_FLAG_F8_HANDLER)
-#error "SPC5_EMIOS_FLAG_F8_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 8 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F8_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH8 */
-
-#if SPC5_PWM_USE_EMIOS_CH9
-#if !defined(SPC5_EMIOS_FLAG_F9_HANDLER)
-#error "SPC5_EMIOS_FLAG_F9_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 9 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F9_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH9 */
-
-#if SPC5_PWM_USE_EMIOS_CH10
-#if !defined(SPC5_EMIOS_FLAG_F10_HANDLER)
-#error "SPC5_EMIOS_FLAG_F10_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 10 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F10_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH10 */
-
-#if SPC5_PWM_USE_EMIOS_CH12
-#if !defined(SPC5_EMIOS_FLAG_F12_HANDLER)
-#error "SPC5_EMIOS_FLAG_F12_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 12 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F12_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH12 */
-
-#if SPC5_PWM_USE_EMIOS_CH14
-#if !defined(SPC5_EMIOS_FLAG_F14_HANDLER)
-#error "SPC5_EMIOS_FLAG_F14_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 14 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F14_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH14 */
-
-#if SPC5_PWM_USE_EMIOS_CH15
-#if !defined(SPC5_EMIOS_FLAG_F15_HANDLER)
-#error "SPC5_EMIOS_FLAG_F15_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 15 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD7);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH15 */
-
-#if SPC5_PWM_USE_EMIOS_CH23
-#if !defined(SPC5_EMIOS_FLAG_F23_HANDLER)
-#error "SPC5_EMIOS_FLAG_F23_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 23 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F23_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD8);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH23 */
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-#if SPC5_PWM_USE_EMIOS_CH19
-#if !defined(SPC5_EMIOS_FLAG_F19_HANDLER)
-#error "SPC5_EMIOS_FLAG_F19_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 19 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F19_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD9);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH19 */
-
-#if SPC5_PWM_USE_EMIOS_CH20
-#if !defined(SPC5_EMIOS_FLAG_F20_HANDLER)
-#error "SPC5_EMIOS_FLAG_F20_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 20 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F20_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD10);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH20 */
-
-#if SPC5_PWM_USE_EMIOS_CH21
-#if !defined(SPC5_EMIOS_FLAG_F21_HANDLER)
-#error "SPC5_EMIOS_FLAG_F21_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 21 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F21_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD11);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH21 */
-
-#if SPC5_PWM_USE_EMIOS_CH22
-#if !defined(SPC5_EMIOS_FLAG_F22_HANDLER)
-#error "SPC5_EMIOS_FLAG_F22_HANDLER not defined"
-#endif
-/**
- * @brief   EMIOS Channel 22 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F22_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD12);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS_CH22 */
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-  /* eMIOSx channels initially all not in use.*/
-  reset_emios_active_channels();
-
-#if SPC5_PWM_USE_EMIOS_CH0
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD1);
-  PWMD1.emiosp = &EMIOS;
-  PWMD1.ch_number = 0U;
-#endif /* SPC5_PWM_USE_EMIOS_CH0 */
-
-#if SPC5_PWM_USE_EMIOS_CH8
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD2);
-  PWMD2.emiosp = &EMIOS;
-  PWMD2.ch_number = 8U;
-#endif /* SPC5_PWM_USE_EMIOS_CH8 */
-
-#if SPC5_PWM_USE_EMIOS_CH9
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD3);
-  PWMD3.emiosp = &EMIOS;
-  PWMD3.ch_number = 9U;
-#endif /* SPC5_PWM_USE_EMIOS_CH9 */
-
-#if SPC5_PWM_USE_EMIOS_CH10
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD4);
-  PWMD4.emiosp = &EMIOS;
-  PWMD4.ch_number = 10U;
-#endif /* SPC5_PWM_USE_EMIOS_CH10 */
-
-#if SPC5_PWM_USE_EMIOS_CH12
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD5);
-  PWMD5.emiosp = &EMIOS;
-  PWMD5.ch_number = 12U;
-#endif /* SPC5_PWM_USE_EMIOS_CH12 */
-
-#if SPC5_PWM_USE_EMIOS_CH14
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD6);
-  PWMD6.emiosp = &EMIOS;
-  PWMD6.ch_number = 14U;
-#endif /* SPC5_PWM_USE_EMIOS_CH14 */
-
-#if SPC5_PWM_USE_EMIOS_CH15
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD7);
-  PWMD7.emiosp = &EMIOS;
-  PWMD7.ch_number = 15U;
-#endif /* SPC5_PWM_USE_EMIOS_CH15 */
-
-#if SPC5_PWM_USE_EMIOS_CH23
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD8);
-  PWMD8.emiosp = &EMIOS;
-  PWMD8.ch_number = 23U;
-#endif /* SPC5_PWM_USE_EMIOS_CH23 */
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-#if SPC5_PWM_USE_EMIOS_CH19
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD9);
-  PWMD9.emiosp = &EMIOS;
-  PWMD9.ch_number = 19U;
-#endif /* SPC5_PWM_USE_EMIOS_CH19 */
-
-#if SPC5_PWM_USE_EMIOS_CH20
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD10);
-  PWMD10.emiosp = &EMIOS;
-  PWMD10.ch_number = 20U;
-#endif /* SPC5_PWM_USE_EMIOS_CH20 */
-
-#if SPC5_PWM_USE_EMIOS_CH21
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD11);
-  PWMD11.emiosp = &EMIOS;
-  PWMD11.ch_number = 21U;
-#endif /* SPC5_PWM_USE_EMIOS_CH21 */
-
-#if SPC5_PWM_USE_EMIOS_CH22
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD12);
-  PWMD12.emiosp = &EMIOS;
-  PWMD12.ch_number = 22U;
-#endif /* SPC5_PWM_USE_EMIOS_CH22 */
-#endif
-
-#if SPC5_PWM_USE_EMIOS
-
-#if SPC5_EMIOS_NUM_CHANNELS == 16
-    INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY;
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-    INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F19_NUMBER].R = SPC5_EMIOS_FLAG_F19_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F20_NUMBER].R = SPC5_EMIOS_FLAG_F20_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F21_NUMBER].R = SPC5_EMIOS_FLAG_F21_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F22_NUMBER].R = SPC5_EMIOS_FLAG_F22_PRIORITY;
-    INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY;
-#endif
-
-#endif
-
-}
-
-/**
- * @brief   Configures and activates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-
-  uint32_t psc = 0;
-
-  chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
-              "pwm_lld_start(), #1", "too many channels");
-
-  if (pwmp->state == PWM_STOP) {
-#if SPC5_PWM_USE_EMIOS_CH0
-    if (&PWMD1 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH0 */
-
-#if SPC5_PWM_USE_EMIOS_CH8
-    if (&PWMD2 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH8 */
-
-#if SPC5_PWM_USE_EMIOS_CH9
-    if (&PWMD3 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH9 */
-
-#if SPC5_PWM_USE_EMIOS_CH10
-    if (&PWMD4 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH10 */
-
-#if SPC5_PWM_USE_EMIOS_CH12
-    if (&PWMD5 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH12 */
-
-#if SPC5_PWM_USE_EMIOS_CH14
-    if (&PWMD6 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH14 */
-
-#if SPC5_PWM_USE_EMIOS_CH15
-    if (&PWMD7 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH15 */
-
-#if SPC5_PWM_USE_EMIOS_CH23
-    if (&PWMD8 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH23 */
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-#if SPC5_PWM_USE_EMIOS_CH19
-    if (&PWMD9 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH19 */
-
-#if SPC5_PWM_USE_EMIOS_CH20
-    if (&PWMD10 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH20 */
-
-#if SPC5_PWM_USE_EMIOS_CH21
-    if (&PWMD11 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH21 */
-
-#if SPC5_PWM_USE_EMIOS_CH22
-    if (&PWMD12 == pwmp) {
-      increase_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH22 */
-#endif
-
-    /* Set eMIOS Clock.*/
-#if SPC5_PWM_USE_EMIOS
-    pwm_active_emios_clock(pwmp);
-#endif
-
-  }
-  /* Configures the peripheral.*/
-
-  /* Channel enables.*/
-  pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number);
-
-  /* Clear pending IRQs (if any).*/
-  pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC |
-      EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-  /* Set clock prescaler and control register.*/
-  psc = (SPC5_EMIOS_CLK / pwmp->config->frequency);
-  chDbgAssert((psc <= 0xFFFF) &&
-              (((psc) * pwmp->config->frequency) == SPC5_EMIOS_CLK) &&
-              ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
-              "pwm_lld_start(), #1", "invalid frequency");
-
-  if (pwmp->config->mode == PWM_ALIGN_EDGE) {
-    pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 0;
-    pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPRE = psc - 1U;
-    pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 1U;
-    pwmp->emiosp->CH[pwmp->ch_number].CCNTR.R = 1U;
-    pwmp->emiosp->CH[pwmp->ch_number].CADR.R = 0U;
-    pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = pwmp->config->period;
-    pwmp->emiosp->CH[pwmp->ch_number].CCR.R |=
-        EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) | EMIOS_CCR_MODE_OPWFMB | 2U;
-    pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_UCPREN;
-
-    /* Set output polarity.*/
-    if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) {
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_EDPOL;
-    } else if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) {
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R &= ~EMIOSC_EDPOL;
-    }
-
-    /* Channel disables.*/
-    pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number);
-
-  } else if (pwmp->config->mode == PWM_ALIGN_CENTER) {
-    /* Not implemented.*/
-  }
-
-}
-
-/**
- * @brief   Deactivates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
-  chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
-		  	  "pwm_lld_stop(), #1", "too many channels");
-
-  if (pwmp->state == PWM_READY) {
-
-    /* Disables the peripheral.*/
-#if SPC5_PWM_USE_EMIOS_CH0
-    if (&PWMD1 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH0 */
-
-#if SPC5_PWM_USE_EMIOS_CH8
-    if (&PWMD2 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH8 */
-
-#if SPC5_PWM_USE_EMIOS_CH9
-    if (&PWMD3 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH9 */
-
-#if SPC5_PWM_USE_EMIOS_CH10
-    if (&PWMD4 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH10 */
-
-#if SPC5_PWM_USE_EMIOS_CH12
-    if (&PWMD5 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH12 */
-
-#if SPC5_PWM_USE_EMIOS_CH14
-    if (&PWMD6 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH14 */
-
-#if SPC5_PWM_USE_EMIOS_CH15
-    if (&PWMD7 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH15 */
-
-#if SPC5_PWM_USE_EMIOS_CH23
-    if (&PWMD8 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH23 */
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-#if SPC5_PWM_USE_EMIOS_CH19
-    if (&PWMD9 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH19 */
-
-#if SPC5_PWM_USE_EMIOS_CH20
-    if (&PWMD10 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH20 */
-
-#if SPC5_PWM_USE_EMIOS_CH21
-    if (&PWMD11 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH21 */
-
-#if SPC5_PWM_USE_EMIOS_CH22
-    if (&PWMD12 == pwmp) {
-      /* Reset UC Control Register.*/
-      pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
-
-      decrease_emios_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS_CH22 */
-#endif
-
-    /* eMIOS clock deactivation.*/
-#if SPC5_PWM_USE_EMIOS
-    deactive_emios_clock();
-#endif
-
-  }
-}
-
-/**
- * @brief   Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- *          been activated using @p pwmStart().
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The PWM unit period is changed to the new value.
- * @note    The function has effect at the next cycle start.
- * @note    If a period is specified that is shorter than the pulse width
- *          programmed in one of the channels then the behavior is not
- *          guaranteed.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] period    new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
-
-  pwmp->period = period;
-  pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = period;
-
-}
-
-/**
- * @brief   Enables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is active using the specified configuration.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t channel,
-                            pwmcnt_t width) {
-
-  (void)channel;
-
-  /* Clear pending IRQs (if any).*/
-  pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC |
-      EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-  /* Set pwm width.*/
-  pwmp->emiosp->CH[pwmp->ch_number].CADR.R = width;
-
-  /* Active interrupts.*/
-  if (pwmp->config->callback != NULL ||                                   \
-      pwmp->config->channels[0].callback != NULL) {
-    pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 1U;
-  }
-
-  /* Channel enables.*/
-  pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number);
-
-}
-
-/**
- * @brief   Disables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is disabled and its output line returned to the
- *          idle state.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-  (void)channel;
-  /* Clear pending IRQs (if any).*/
-  pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC |
-        EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-  /* Disable interrupts.*/
-  pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 0;
-
-  /* Channel disables.*/
-  pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number);
-
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h
deleted file mode 100644
index d859ac30c..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/eMIOS200_v1/pwm_lld.h
- * @brief   SPC5xx low level pwm driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS                            1
-
-/**
- * @brief   Edge-Aligned PWM functional mode.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_EDGE                          0x00
-
-/**
- * @brief   Center-Aligned PWM functional mode.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_CENTER                        0x01
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH0) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH0              FALSE
-#endif
-
-/**
- * @brief   PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH8) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH8              FALSE
-#endif
-
-/**
- * @brief   PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH9) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH9              FALSE
-#endif
-
-/**
- * @brief   PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH10) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH10             FALSE
-#endif
-
-/**
- * @brief   PWMD5 driver enable switch.
- * @details If set to @p TRUE the support for PWMD5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH12) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH12             FALSE
-#endif
-
-/**
- * @brief   PWMD6 driver enable switch.
- * @details If set to @p TRUE the support for PWMD6 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH14) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH14             FALSE
-#endif
-
-/**
- * @brief   PWMD7 driver enable switch.
- * @details If set to @p TRUE the support for PWMD7 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH15) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH15             FALSE
-#endif
-
-/**
- * @brief   PWMD8 driver enable switch.
- * @details If set to @p TRUE the support for PWMD8 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH23) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH23             FALSE
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-/**
- * @brief   PWMD9 driver enable switch.
- * @details If set to @p TRUE the support for PWMD9 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH19) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH19             FALSE
-#endif
-
-/**
- * @brief   PWMD10 driver enable switch.
- * @details If set to @p TRUE the support for PWMD10 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH20) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH20             FALSE
-#endif
-
-/**
- * @brief   PWMD11 driver enable switch.
- * @details If set to @p TRUE the support for PWMD11 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH21) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH21             FALSE
-#endif
-
-/**
- * @brief   PWMD12 driver enable switch.
- * @details If set to @p TRUE the support for PWMD12 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS_CH22) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS_CH22             FALSE
-#endif
-#endif
-
-/**
- * @brief   PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F0_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F0_PRIORITY         7
-#endif
-
-/**
- * @brief   PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F8_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F8_PRIORITY         7
-#endif
-
-/**
- * @brief   PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F9_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F9_PRIORITY         7
-#endif
-
-/**
- * @brief   PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F10_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F10_PRIORITY        7
-#endif
-
-/**
- * @brief   PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F12_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F12_PRIORITY        7
-#endif
-
-/**
- * @brief   PWMD6 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F14_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F14_PRIORITY        7
-#endif
-
-/**
- * @brief   PWMD7 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F15_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F15_PRIORITY        7
-#endif
-
-/**
- * @brief   PWMD8 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F23_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F23_PRIORITY        7
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 24
-/**
- * @brief   PWMD9 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F19_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F19_PRIORITY        7
-#endif
-
-/**
- * @brief   PWMD10 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F20_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F20_PRIORITY        7
-#endif
-
-/**
- * @brief   PWMD11 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F21_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F21_PRIORITY        7
-#endif
-
-/**
- * @brief   PWMD12 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS_FLAG_F22_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS_FLAG_F22_PRIORITY        7
-#endif
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS
-#error "EMIOS not present in the selected device"
-#endif
-
-#if SPC5_EMIOS_NUM_CHANNELS == 16
-#define SPC5_PWM_USE_EMIOS                  (SPC5_PWM_USE_EMIOS_CH0  ||    \
-                                             SPC5_PWM_USE_EMIOS_CH8  ||    \
-                                             SPC5_PWM_USE_EMIOS_CH9  ||    \
-                                             SPC5_PWM_USE_EMIOS_CH10 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH12 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH14 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH15 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH23)
-#elif SPC5_EMIOS_NUM_CHANNELS == 24
-#define SPC5_PWM_USE_EMIOS                  (SPC5_PWM_USE_EMIOS_CH0  ||    \
-                                             SPC5_PWM_USE_EMIOS_CH8  ||    \
-                                             SPC5_PWM_USE_EMIOS_CH9  ||    \
-                                             SPC5_PWM_USE_EMIOS_CH10 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH12 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH14 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH15 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH23 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH19 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH20 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH21 ||    \
-                                             SPC5_PWM_USE_EMIOS_CH22)
-#endif
-
-#if !SPC5_PWM_USE_EMIOS
-#error "PWM driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief   PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief   PWM counter type.
- */
-typedef uint32_t pwmcnt_t;
-
-/**
- * @brief   PWM driver channel configuration structure.
- * @note    Some architectures may not be able to support the channel mode
- *          or the callback, in this case the fields are ignored.
- */
-typedef struct {
-  /**
-   * @brief Channel active logic level.
-   */
-  pwmmode_t                 mode;
-  /**
-   * @brief Channel callback pointer.
-   * @note  This callback is invoked on the channel compare event. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief Timer clock in Hz.
-   * @note  The low level can use assertions in order to catch invalid
-   *        frequency specifications.
-   */
-  uint32_t                  frequency;
-  /**
-   * @brief PWM period in ticks.
-   * @note  The low level can use assertions in order to catch invalid
-   *        period specifications.
-   */
-  pwmcnt_t                  period;
-  /**
-   * @brief Periodic callback pointer.
-   * @note  This callback is invoked on PWM counter reset. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /**
-   * @brief Channels configurations.
-   */
-  PWMChannelConfig          channels[PWM_CHANNELS];
-  /* End of the mandatory fields.*/
-  /**
-   * @brief PWM functional mode.
-   */
-  pwmmode_t                 mode;
-} PWMConfig;
-
-/**
- * @brief   Structure representing an PWM driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct PWMDriver {
-  /**
-   * @brief Driver state.
-   */
-  pwmstate_t                state;
-  /**
-   * @brief eMIOSx channel number.
-   */
-  uint8_t                   ch_number;
-  /**
-   * @brief Current configuration data.
-   */
-  const PWMConfig           *config;
-  /**
-   * @brief Current PWM period in ticks.
-   */
-  pwmcnt_t                  period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
-  PWM_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the eMIOSx registers block.
-   */
-  volatile struct EMIOS_tag *emiosp;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS_CH0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH8 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH9 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH10 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH12 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD5;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH14 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD6;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH15 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD7;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH23 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD8;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH19 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD9;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH20 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD10;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH21 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD11;
-#endif
-
-#if SPC5_PWM_USE_EMIOS_CH22 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD12;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void pwm_lld_init(void);
-  void pwm_lld_start(PWMDriver *pwmp);
-  void pwm_lld_stop(PWMDriver *pwmp);
-  void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
-  void pwm_lld_enable_channel(PWMDriver *pwmp,
-                              pwmchannel_t channel,
-                              pwmcnt_t width);
-  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c
deleted file mode 100644
index c37c22e25..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/eMIOS200_v1/spc5_emios.c
- * @brief   eMIOS200 helper driver code.
- *
- * @addtogroup SPC5xx_eMIOS200
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of active eMIOSx Channels.
- */
-static uint32_t emios_active_channels;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-void reset_emios_active_channels() {
-  emios_active_channels = 0;
-}
-
-uint32_t get_emios_active_channels() {
-  return emios_active_channels;
-}
-
-void increase_emios_active_channels() {
-  emios_active_channels++;
-}
-
-void decrease_emios_active_channels() {
-  emios_active_channels--;
-}
-
-#if HAL_USE_ICU
-void icu_active_emios_clock(ICUDriver *icup) {
-  /* If this is the first Channel activated then the eMIOS0 is enabled.*/
-  if (emios_active_channels == 1) {
-    SPC5_EMIOS_ENABLE_CLOCK();
-
-    /* Disable all unified channels.*/
-    icup->emiosp->MCR.B.GPREN = 0;
-    icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GPRE_VALUE);
-    icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
-    icup->emiosp->MCR.B.GTBE = 1U;
-
-    icup->emiosp->UCDIS.R = 0xFFFFFFFF;
-
-  }
-}
-#endif
-
-#if HAL_USE_PWM
-void pwm_active_emios_clock(PWMDriver *pwmp) {
-  /* If this is the first Channel activated then the eMIOS0 is enabled.*/
-  if (emios_active_channels == 1) {
-    SPC5_EMIOS_ENABLE_CLOCK();
-
-    /* Disable all unified channels.*/
-    pwmp->emiosp->MCR.B.GPREN = 0;
-    pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GPRE_VALUE);
-    pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
-    pwmp->emiosp->MCR.B.GTBE = 1U;
-
-    pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
-
-  }
-}
-#endif
-
-void deactive_emios_clock() {
-  /* If it is the last active channels then the eMIOS0 is disabled.*/
-  if (emios_active_channels == 0) {
-    SPC5_EMIOS_DISABLE_CLOCK();
-
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-
-#endif /* HAL_USE_ICU || HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h
deleted file mode 100644
index f1f08695b..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    SPC5xx/eMIOS200_v1/spc5_emios.h
- * @brief   eMIOS200 helper driver header.
- *
- * @addtogroup SPC5xx_eMIOS200
- * @{
- */
-
-#ifndef _SPC5_EMIOS_H_
-#define _SPC5_EMIOS_H_
-
-#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define EMIOSMCR_MDIS                       (1 << 30)
-#define EMIOSMCR_FRZ                        (1 << 29)
-#define EMIOSMCR_GTBE                       (1 << 28)
-#define EMIOSMCR_GPREN                      (1 << 26)
-#define EMIOSMCR_GPRE(n)                    ((n) << 8)
-
-#define EMIOSC_FREN                         (1 << 31)
-#define EMIOSC_UCPRE(n)                     ((n) << 26)
-#define EMIOSC_UCPREN                       (1 << 25)
-#define EMIOSC_DMA                          (1 << 24)
-#define EMIOSC_IF(n)                        ((n) << 19)
-#define EMIOSC_FCK                          (1 << 18)
-#define EMIOSC_FEN                          (1 << 17)
-#define EMIOSC_FORCMA                       (1 << 13)
-#define EMIOSC_FORCMB                       (1 << 12)
-#define EMIOSC_BSL(n)                       ((n) << 9)
-#define EMIOSC_EDSEL                        (1 << 8)
-#define EMIOSC_EDPOL                        (1 << 7)
-#define EMIOSC_MODE(n)                      ((n) << 0)
-
-#define EMIOS_BSL_COUNTER_BUS_A             0
-#define EMIOS_BSL_COUNTER_BUS_2             1
-#define EMIOS_BSL_INTERNAL_COUNTER          3
-
-#define EMIOS_CCR_MODE_GPIO_IN              0
-#define EMIOS_CCR_MODE_GPIO_OUT             1
-#define EMIOS_CCR_MODE_SAIC                 2
-#define EMIOS_CCR_MODE_SAOC                 3
-#define EMIOS_CCR_MODE_IPWM                 4
-#define EMIOS_CCR_MODE_IPM                  5
-#define EMIOS_CCR_MODE_DAOC_B_MATCH         6
-#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH      7
-#define EMIOS_CCR_MODE_MC_CMS               16
-#define EMIOS_CCR_MODE_MC_CME               17
-#define EMIOS_CCR_MODE_MC_UP_DOWN           18
-#define EMIOS_CCR_MODE_OPWMT                38
-#define EMIOS_CCR_MODE_MCB_UP               80
-#define EMIOS_CCR_MODE_MCB_UP_DOWN          84
-#define EMIOS_CCR_MODE_OPWFMB               88
-#define EMIOS_CCR_MODE_OPWMCB_TE            92
-#define EMIOS_CCR_MODE_OPWMCB_LE            93
-#define EMIOS_CCR_MODE_OPWMB                96
-
-#define EMIOSS_OVR                          (1 << 31)
-#define EMIOSS_OVRC                         (1 << 31)
-#define EMIOSS_OVFL                         (1 << 15)
-#define EMIOSS_OVFLC                        (1 << 15)
-#define EMIOSS_FLAG                         (1 << 0)
-#define EMIOSS_FLAGC                        (1 << 0)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-void reset_emios_active_channels(void);
-uint32_t get_emios_active_channels(void);;
-void increase_emios_active_channels(void);
-void decrease_emios_active_channels(void);
-#if HAL_USE_ICU
-void icu_active_emios_clock(ICUDriver *icup);
-#endif
-#if HAL_USE_PWM
-void pwm_active_emios_clock(PWMDriver *pwmp);
-#endif
-void deactive_emios_clock(void);
-
-#endif /* HAL_USE_ICU || HAL_USE_PWM */
-
-#endif /* _SPC5_EMIOS_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c
deleted file mode 100644
index f465e064b..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c
+++ /dev/null
@@ -1,757 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    eMIOS_v1/icu_lld.c
- * @brief   SPC5xx low level ICU driver code.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ICUD1 driver identifier.
- * @note    The driver ICUD1 allocates the unified channel eMIOS0_CH0
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH0 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-
-/**
- * @brief   ICUD2 driver identifier.
- * @note    The driver ICUD2 allocates the unified channel eMIOS0_CH1
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH1 || defined(__DOXYGEN__)
-ICUDriver ICUD2;
-#endif
-
-/**
- * @brief   ICUD3 driver identifier.
- * @note    The driver ICUD3 allocates the unified channel eMIOS0_CH2
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH2 || defined(__DOXYGEN__)
-ICUDriver ICUD3;
-#endif
-
-/**
- * @brief   ICUD4 driver identifier.
- * @note    The driver ICUD4 allocates the unified channel eMIOS0_CH3
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH3 || defined(__DOXYGEN__)
-ICUDriver ICUD4;
-#endif
-
-/**
- * @brief   ICUD5 driver identifier.
- * @note    The driver ICUD5 allocates the unified channel eMIOS0_CH4
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH4 || defined(__DOXYGEN__)
-ICUDriver ICUD5;
-#endif
-
-/**
- * @brief   ICUD6 driver identifier.
- * @note    The driver ICUD6 allocates the unified channel eMIOS0_CH5
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH5 || defined(__DOXYGEN__)
-ICUDriver ICUD6;
-#endif
-
-/**
- * @brief   ICUD7 driver identifier.
- * @note    The driver ICUD7 allocates the unified channel eMIOS0_CH6
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH6 || defined(__DOXYGEN__)
-ICUDriver ICUD7;
-#endif
-
-/**
- * @brief   ICUD8 driver identifier.
- * @note    The driver ICUD8 allocates the unified channel eMIOS0_CH7
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH7 || defined(__DOXYGEN__)
-ICUDriver ICUD8;
-#endif
-
-/**
- * @brief   ICUD9 driver identifier.
- * @note    The driver ICUD9 allocates the unified channel eMIOS0_CH24
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH24 || defined(__DOXYGEN__)
-ICUDriver ICUD9;
-#endif
-
-/**
- * @brief   ICUD10 driver identifier.
- * @note    The driver ICUD10 allocates the unified channel eMIOS1_CH24
- *          when enabled.
- */
-#if SPC5_ICU_USE_EMIOS1_CH24 || defined(__DOXYGEN__)
-ICUDriver ICUD10;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Width and Period registers.
- */
-int16_t width;
-int16_t period;
-
-/**
- * @brief   A2 temp registers.
- */
-uint16_t A2_1, A2_2, A2_3;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief               ICU IRQ handler.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
-  uint32_t gfr = icup->emiosp->GFR.R;
-
-  if (gfr && (1 << icup->ch_number)) {
-    uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R;
-
-    if(sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL){
-      icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC;
-      _icu_isr_invoke_overflow_cb(icup);
-    }
-    if (sr && EMIOSS_FLAG) {
-      icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC;
-      if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
-        if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U  &&        \
-            icup->config->period_cb != NULL) {
-          A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
-          period = A2_3 - A2_1;
-          _icu_isr_invoke_period_cb(icup);
-          A2_1 = A2_3;
-        } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 &&   \
-            icup->config->width_cb != NULL) {
-          A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
-          width = A2_2 - A2_1;
-          _icu_isr_invoke_width_cb(icup);
-        }
-      } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) {
-        if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U &&         \
-            icup->config->width_cb != NULL) {
-          A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
-          width = A2_2 - A2_1;
-          _icu_isr_invoke_width_cb(icup);
-        } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 &&   \
-            icup->config->period_cb != NULL) {
-          A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
-          period = A2_3 - A2_1;
-          _icu_isr_invoke_period_cb(icup);
-          A2_1 = A2_3;
-        }
-      }
-    }
-    if (sr && EMIOSS_OVR) {
-      icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC;
-    }
-
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1
-#if !defined(SPC5_EMIOS0_GFR_F0F1_HANDLER)
-#error "SPC5_EMIOS0_GFR_F0F1_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 0 and 1 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F0F1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH0
-  icu_lld_serve_interrupt(&ICUD1);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH1
-  icu_lld_serve_interrupt(&ICUD2);
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1 */
-
-#if SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3
-#if !defined(SPC5_EMIOS0_GFR_F2F3_HANDLER)
-#error "SPC5_EMIOS0_GFR_F2F3_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 2 and 3 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F2F3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH2
-  icu_lld_serve_interrupt(&ICUD3);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH3
-  icu_lld_serve_interrupt(&ICUD4);
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3 */
-
-#if SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5
-#if !defined(SPC5_EMIOS0_GFR_F4F5_HANDLER)
-#error "SPC5_EMIOS0_GFR_F4F5_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 4 and 5 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F4F5_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH4
-  icu_lld_serve_interrupt(&ICUD5);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH5
-  icu_lld_serve_interrupt(&ICUD6);
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5 */
-
-#if SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7
-
-#if !defined(SPC5_EMIOS0_GFR_F6F7_HANDLER)
-#error "SPC5_EMIOS0_GFR_F6F7_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 6 and 7 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F6F7_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH6
-  icu_lld_serve_interrupt(&ICUD7);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH7
-  icu_lld_serve_interrupt(&ICUD8);
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7 */
-
-#if SPC5_ICU_USE_EMIOS0_CH24
-#if !defined(SPC5_EMIOS0_GFR_F24F25_HANDLER)
-#error "SPC5_EMIOS0_GFR_F24F25_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 24 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F24F25_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH24
-  icu_lld_serve_interrupt(&ICUD9);
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-
-#if SPC5_ICU_USE_EMIOS1_CH24
-#if !defined(SPC5_EMIOS1_GFR_F24F25_HANDLER)
-#error "SPC5_EMIOS1_GFR_F24F25_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 24 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F24F25_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS1_CH24
-  icu_lld_serve_interrupt(&ICUD10);
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
-  /* Initialize A2 temp registers.*/
-  A2_1 = 0U;
-  A2_2 = 0U;
-  A2_3 = 0U;
-
-  /* eMIOSx channels initially all not in use.*/
-  reset_emios0_active_channels();
-  reset_emios1_active_channels();
-
-#if SPC5_ICU_USE_EMIOS0_CH0
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD1);
-  ICUD1.emiosp = &EMIOS_0;
-  ICUD1.ch_number = 0U;
-  ICUD1.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
-
-#if SPC5_ICU_USE_EMIOS0_CH1
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD2);
-  ICUD2.emiosp = &EMIOS_0;
-  ICUD2.ch_number = 1U;
-  ICUD2.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
-
-#if SPC5_ICU_USE_EMIOS0_CH2
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD3);
-  ICUD3.emiosp = &EMIOS_0;
-  ICUD3.ch_number = 2U;
-  ICUD3.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
-
-#if SPC5_ICU_USE_EMIOS0_CH3
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD4);
-  ICUD4.emiosp = &EMIOS_0;
-  ICUD4.ch_number = 3U;
-  ICUD4.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
-
-#if SPC5_ICU_USE_EMIOS0_CH4
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD5);
-  ICUD5.emiosp = &EMIOS_0;
-  ICUD5.ch_number = 4U;
-  ICUD5.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
-
-#if SPC5_ICU_USE_EMIOS0_CH5
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD6);
-  ICUD6.emiosp = &EMIOS_0;
-  ICUD6.ch_number = 5U;
-  ICUD6.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
-
-#if SPC5_ICU_USE_EMIOS0_CH6
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD7);
-  ICUD7.emiosp = &EMIOS_0;
-  ICUD7.ch_number = 6U;
-  ICUD7.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
-
-#if SPC5_ICU_USE_EMIOS0_CH7
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD8);
-  ICUD8.emiosp = &EMIOS_0;
-  ICUD8.ch_number = 7U;
-  ICUD8.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
-
-#if SPC5_ICU_USE_EMIOS0_CH24
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD9);
-  ICUD9.emiosp = &EMIOS_0;
-  ICUD9.ch_number = 24U;
-  ICUD9.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-
-#if SPC5_ICU_USE_EMIOS1_CH24
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD10);
-  ICUD10.emiosp = &EMIOS_1;
-  ICUD10.ch_number = 24U;
-  ICUD10.clock = SPC5_EMIOS1_CLK;
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
-#if SPC5_ICU_USE_EMIOS0
-
-  INTC.PSR[SPC5_EMIOS0_GFR_F0F1_NUMBER].R = SPC5_EMIOS0_GFR_F0F1_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F2F3_NUMBER].R = SPC5_EMIOS0_GFR_F2F3_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F4F5_NUMBER].R = SPC5_EMIOS0_GFR_F4F5_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F6F7_NUMBER].R = SPC5_EMIOS0_GFR_F6F7_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F24F25_NUMBER].R = SPC5_EMIOS0_GFR_F24F25_PRIORITY;
-
-#endif
-
-#if SPC5_ICU_USE_EMIOS1
-
-  INTC.PSR[SPC5_EMIOS1_GFR_F24F25_NUMBER].R = SPC5_EMIOS1_GFR_F24F25_PRIORITY;
-
-#endif
-}
-
-/**
- * @brief   Configures and activates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-
-  chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_start(), #1",
-                "too many channels");
-
-  chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_start(), #2",
-                "too many channels");
-
-  if (icup->state == ICU_STOP) {
-    /* Enables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS0_CH0
-    if (&ICUD1 == icup)
-      increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
-#if SPC5_ICU_USE_EMIOS0_CH1
-    if (&ICUD2 == icup)
-      increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
-#if SPC5_ICU_USE_EMIOS0_CH2
-    if (&ICUD3 == icup)
-      increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
-#if SPC5_ICU_USE_EMIOS0_CH3
-    if (&ICUD4 == icup)
-      increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
-#if SPC5_ICU_USE_EMIOS0_CH4
-    if (&ICUD5 == icup)
-      increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
-#if SPC5_ICU_USE_EMIOS0_CH5
-    if (&ICUD6 == icup)
-      increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
-#if SPC5_ICU_USE_EMIOS0_CH6
-    if (&ICUD7 == icup)
-      increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
-#if SPC5_ICU_USE_EMIOS0_CH7
-    if (&ICUD8 == icup)
-      increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
-#if SPC5_ICU_USE_EMIOS0_CH24
-    if (&ICUD9 == icup)
-      increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-#if SPC5_ICU_USE_EMIOS1_CH24
-    if (&ICUD10 == icup)
-      increase_emios1_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
-    /* Set eMIOS0 Clock.*/
-#if SPC5_ICU_USE_EMIOS0
-    icu_active_emios0_clock(icup);
-#endif
-
-    /* Set eMIOS1 Clock.*/
-#if SPC5_ICU_USE_EMIOS1
-    icu_active_emios1_clock(icup);
-#endif
-
-  }
-  /* Configures the peripheral.*/
-
-  /* Channel enables.*/
-  icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
-  /* Clear pending IRQs (if any).*/
-  icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
-      EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-  /* Set clock prescaler and control register.*/
-  uint32_t psc = (icup->clock / icup->config->frequency);
-  chDbgAssert((psc <= 0xFFFF) &&
-              (((psc) * icup->config->frequency) == icup->clock) &&
-              ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
-              "icu_lld_start(), #1", "invalid frequency");
-
-  icup->emiosp->CH[icup->ch_number].CCR.B.UCPEN = 0;
-  icup->emiosp->CH[icup->ch_number].CCR.R |=
-      EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) |
-      EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC;
-  icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1;
-  icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN;
-
-  /* Set source polarity.*/
-  if(icup->config->mode == ICU_INPUT_ACTIVE_HIGH){
-    icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL;
-  } else {
-    icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL;
-  }
-
-  /* Direct pointers to the period and width registers in order to make
-     reading data faster from within callbacks.*/
-  icup->pccrp = &period;
-  icup->wccrp = &width;
-
-  /* Channel disables.*/
-  icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-/**
- * @brief   Deactivates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
-  chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_stop(), #1",
-              "too many channels");
-  chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_stop(), #2",
-              "too many channels");
-
-  if (icup->state == ICU_READY) {
-
-    /* Disables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS0_CH0
-    if (&ICUD1 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
-#if SPC5_ICU_USE_EMIOS0_CH1
-    if (&ICUD2 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
-#if SPC5_ICU_USE_EMIOS0_CH2
-    if (&ICUD3 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
-#if SPC5_ICU_USE_EMIOS0_CH3
-    if (&ICUD4 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
-#if SPC5_ICU_USE_EMIOS0_CH4
-    if (&ICUD5 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
-#if SPC5_ICU_USE_EMIOS0_CH5
-    if (&ICUD6 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
-#if SPC5_ICU_USE_EMIOS0_CH6
-    if (&ICUD7 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
-#if SPC5_ICU_USE_EMIOS0_CH7
-    if (&ICUD8 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
-#if SPC5_ICU_USE_EMIOS0_CH24
-    if (&ICUD9 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-#if SPC5_ICU_USE_EMIOS1_CH24
-    if (&ICUD10 == icup) {
-      /* Reset UC Control Register.*/
-      icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
-      decrease_emios1_active_channels();
-    }
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
-    /* eMIOS0 clock deactivation.*/
-#if SPC5_ICU_USE_EMIOS0
-    icu_deactive_emios0_clock(icup);
-#endif
-
-    /* eMIOS1 clock deactivation.*/
-#if SPC5_ICU_USE_EMIOS1
-    icu_deactive_emios1_clock(icup);
-#endif
-  }
-}
-
-/**
- * @brief   Enables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
-  /* Channel enables.*/
-  /*
-  if (!(icup->emiosp->UCDIS.R && (1 << icup->ch_number))) {
-
-    icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-  }
-  */
-
-  /* Channel enables.*/
-  icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
-  /* Clear pending IRQs (if any).*/
-  icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
-      EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-  /* Active interrupts.*/
-  if (icup->config->period_cb != NULL || icup->config->width_cb != NULL ||  \
-      icup->config->overflow_cb != NULL) {
-    icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U;
-  }
-
-}
-
-/**
- * @brief   Disables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
-  /* Clear pending IRQs (if any).*/
-  icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
-        EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-  /* Disable interrupts.*/
-  icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0;
-
-  /* Channel disables.*/
-  icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h
deleted file mode 100644
index 96fb50a82..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    eMIOS_v1/icu_lld.h
- * @brief   SPC5xx low level ICU driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__)
-/**
- * @brief   ICUD1 driver enable switch.
- * @details If set to @p TRUE the support for ICUD1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH0) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH0             FALSE
-#endif
-
-/**
- * @brief   ICUD2 driver enable switch.
- * @details If set to @p TRUE the support for ICUD2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH1) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH1             FALSE
-#endif
-
-/**
- * @brief   ICUD3 driver enable switch.
- * @details If set to @p TRUE the support for ICUD3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH2) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH2             FALSE
-#endif
-
-/**
- * @brief   ICUD4 driver enable switch.
- * @details If set to @p TRUE the support for ICUD4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH3) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH3             FALSE
-#endif
-
-/**
- * @brief   ICUD5 driver enable switch.
- * @details If set to @p TRUE the support for ICUD5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH4) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH4             FALSE
-#endif
-
-/**
- * @brief   ICUD6 driver enable switch.
- * @details If set to @p TRUE the support for ICUD6 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH5) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH5             FALSE
-#endif
-
-/**
- * @brief   ICUD7 driver enable switch.
- * @details If set to @p TRUE the support for ICUD7 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH6) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH6             FALSE
-#endif
-
-/**
- * @brief   ICUD8 driver enable switch.
- * @details If set to @p TRUE the support for ICUD8 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH7) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH7             FALSE
-#endif
-
-/**
- * @brief   ICUD9 driver enable switch.
- * @details If set to @p TRUE the support for ICUD9 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH24) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH24            FALSE
-#endif
-
-/**
- * @brief   ICUD1 and ICUD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F0F1_PRIORITY       7
-#endif
-
-/**
- * @brief   ICUD3 and ICUD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F2F3_PRIORITY       7
-#endif
-
-/**
- * @brief   ICUD5 and ICUD6 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F4F5_PRIORITY       7
-#endif
-
-/**
- * @brief   ICUD7 and ICUD8 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F6F7_PRIORITY       7
-#endif
-
-/**
- * @brief   ICUD9 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F24F25_PRIORITY     7
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__)
-/**
- * @brief   ICUD10 driver enable switch.
- * @details If set to @p TRUE the support for ICUD10 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS1_CH24) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS1_CH24            FALSE
-#endif
-
-/**
- * @brief   ICUD10 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F24F25_PRIORITY     7
-#endif
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS0
-#error "EMIOS0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_EMIOS1
-#error "EMIOS1 not present in the selected device"
-#endif
-
-#define SPC5_ICU_USE_EMIOS0                 (SPC5_ICU_USE_EMIOS0_CH0 ||     \
-                                             SPC5_ICU_USE_EMIOS0_CH1 ||     \
-                                             SPC5_ICU_USE_EMIOS0_CH2 ||     \
-                                             SPC5_ICU_USE_EMIOS0_CH3 ||     \
-                                             SPC5_ICU_USE_EMIOS0_CH4 ||     \
-                                             SPC5_ICU_USE_EMIOS0_CH5 ||     \
-                                             SPC5_ICU_USE_EMIOS0_CH6 ||     \
-                                             SPC5_ICU_USE_EMIOS0_CH7 ||     \
-                                             SPC5_ICU_USE_EMIOS0_CH24)
-
-#define SPC5_ICU_USE_EMIOS1                  SPC5_ICU_USE_EMIOS1_CH24
-
-#if !SPC5_ICU_USE_EMIOS0 && !SPC5_ICU_USE_EMIOS1
-#error "ICU driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief ICU driver mode.
- */
-typedef enum {
-  ICU_INPUT_ACTIVE_HIGH = 0,        /**< Trigger on rising edge.            */
-  ICU_INPUT_ACTIVE_LOW = 1,         /**< Trigger on falling edge.           */
-} icumode_t;
-
-/**
- * @brief   ICU frequency type.
- */
-typedef uint32_t icufreq_t;
-
-/**
- * @brief   ICU counter type.
- */
-typedef uint16_t icucnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Driver mode.
-   */
-  icumode_t     mode;
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  icufreq_t     frequency;
-  /**
-   * @brief   Callback for pulse width measurement.
-   */
-  icucallback_t width_cb;
-  /**
-   * @brief   Callback for cycle period measurement.
-   */
-  icucallback_t period_cb;
-  /**
-   * @brief   Callback for timer overflow.
-   */
-  icucallback_t overflow_cb;
-  /* End of the mandatory fields.*/
-} ICUConfig;
-
-/**
- * @brief   Structure representing an ICU driver.
- */
-struct ICUDriver {
-  /**
-   * @brief Driver state.
-   */
-  icustate_t                state;
-  /**
-   * @brief eMIOSx channel number.
-   */
-  uint32_t                  ch_number;
-  /**
-   * @brief Current configuration data.
-   */
-  const ICUConfig           *config;
-  /**
-   * @brief CH Counter clock.
-   */
-  uint32_t clock;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the eMIOSx registers block.
-   */
-  volatile struct EMIOS_tag *emiosp;
-  /**
-   * @brief CCR register used for width capture.
-   */
-  volatile vint16_t        *wccrp;
-  /**
-   * @brief CCR register used for period capture.
-   */
-  volatile vint16_t        *pccrp;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- *          edge and the stop edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
-
-/**
- * @brief   Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- *          edge and the next start edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS0_CH0 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD2;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH2 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD3;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH3 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD4;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH4 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD5;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH5 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD6;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH6 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD7;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH7 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD8;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH24 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD9;
-#endif
-
-#if SPC5_ICU_USE_EMIOS1_CH24 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD10;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void icu_lld_init(void);
-  void icu_lld_start(ICUDriver *icup);
-  void icu_lld_stop(ICUDriver *icup);
-  void icu_lld_enable(ICUDriver *icup);
-  void icu_lld_disable(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c
deleted file mode 100644
index 88000781f..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c
+++ /dev/null
@@ -1,1759 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    eMIOS_v1/pwm_lld.c
- * @brief   SPC5xx low level PWM driver code.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PWMD1 driver identifier.
- * @note    The driver PWMD1 allocates the unified channels eMIOS0_CH8 -
- *          eMIOS0_CH15 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS0_GROUP0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief   PWMD2 driver identifier.
- * @note    The driver PWMD2 allocates the unified channels eMIOS0_CH16 -
- *          eMIOS0_CH23 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS0_GROUP1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief   PWMD3 driver identifier.
- * @note    The driver PWMD3 allocates the unified channels eMIOS1_CH0 -
- *          eMIOS1_CH7 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS1_GROUP0 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief   PWMD4 driver identifier.
- * @note    The driver PWMD4 allocates the unified channels eMIOS1_CH8 -
- *          eMIOS1_CH15 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS1_GROUP1 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/**
- * @brief   PWMD5 driver identifier.
- * @note    The driver PWMD5 allocates the unified channels eMIOS1_CH16 -
- *          eMIOS1_CH23 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS1_GROUP2 || defined(__DOXYGEN__)
-PWMDriver PWMD5;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief               PWM IRQ handler.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt1(PWMDriver *pwmp, uint32_t index) {
-
-  uint32_t sr = pwmp->emiosp->CH[index].CSR.R;
-  if (sr & EMIOSS_OVFL) {
-    pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC;
-  }
-  if (sr & EMIOSS_OVR) {
-    pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC;
-  }
-  if (sr & EMIOSS_FLAG) {
-    pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC;
-    if (pwmp->config->callback != NULL) {
-      pwmp->config->callback(pwmp);
-    }
-  }
-
-}
-
-static void pwm_lld_serve_interrupt2(PWMDriver *pwmp, uint32_t index) {
-
-  uint32_t sr = pwmp->emiosp->CH[index].CSR.R;
-  if (sr & EMIOSS_OVFL) {
-    pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC;
-  }
-  if (sr & EMIOSS_OVR) {
-    pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC;
-  }
-  if (sr & EMIOSS_FLAG) {
-    pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC;
-    if (pwmp->config->channels[index%8U - 1].callback != NULL) {
-      pwmp->config->channels[index%8U - 1].callback(pwmp);
-    }
-  }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-#if !defined(SPC5_EMIOS0_GFR_F8F9_HANDLER)
-#error "SPC5_EMIOS0_GFR_F8F9_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 8 and 9 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F8F9_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD1.emiosp->GFR.R;
-
-  if (gfr & (1U << 8U)) {
-    pwm_lld_serve_interrupt1(&PWMD1, 8U);
-  }
-  if (gfr & (1U << 9U)) {
-    pwm_lld_serve_interrupt2(&PWMD1, 9U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F10F11_HANDLER)
-#error "SPC5_EMIOS0_GFR_F10F11_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 10 and 11 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F10F11_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD1.emiosp->GFR.R;
-
-  if (gfr & (1U << 10U)) {
-    pwm_lld_serve_interrupt2(&PWMD1, 10U);
-  }
-  if (gfr & (1U << 11U)) {
-    pwm_lld_serve_interrupt2(&PWMD1, 11U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F12F13_HANDLER)
-#error "SPC5_EMIOS0_GFR_F12F13_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 12 and 13 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F12F13_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD1.emiosp->GFR.R;
-
-  if (gfr & (1U << 12U)) {
-    pwm_lld_serve_interrupt2(&PWMD1, 12U);
-  }
-  if (gfr & (1U << 13U)) {
-    pwm_lld_serve_interrupt2(&PWMD1, 13U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F14F15_HANDLER)
-#error "SPC5_EMIOS0_GFR_F14F15_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 14 and 15 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F14F15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD1.emiosp->GFR.R;
-
-  if (gfr && (1U << 14U)) {
-    pwm_lld_serve_interrupt2(&PWMD1, 14U);
-  }
-  if (gfr && (1U << 15U)) {
-    pwm_lld_serve_interrupt2(&PWMD1, 15U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-#if !defined(SPC5_EMIOS0_GFR_F16F17_HANDLER)
-#error "SPC5_EMIOS0_GFR_F16F17_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 16 and 17 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F16F17_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD2.emiosp->GFR.R;
-
-  if (gfr && (1U << 16U)) {
-    pwm_lld_serve_interrupt1(&PWMD2, 16U);
-  }
-  if (gfr && (1U << 17U)) {
-    pwm_lld_serve_interrupt2(&PWMD2, 17U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F18F19_HANDLER)
-#error "SPC5_EMIOS0_GFR_F18F19_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 18 and 19 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F18F19_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD2.emiosp->GFR.R;
-
-  if (gfr && (1U << 18U)) {
-    pwm_lld_serve_interrupt2(&PWMD2, 18U);
-  }
-  if (gfr && (1U << 19U)) {
-    pwm_lld_serve_interrupt2(&PWMD2, 19U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F20F21_HANDLER)
-#error "SPC5_EMIOS0_GFR_F20F21_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 20 and 21 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F20F21_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD2.emiosp->GFR.R;
-
-  if (gfr && (1U << 20U)) {
-    pwm_lld_serve_interrupt2(&PWMD2, 20U);
-  }
-  if (gfr && (1U << 21U)) {
-    pwm_lld_serve_interrupt2(&PWMD2, 21U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F22F23_HANDLER)
-#error "SPC5_EMIOS0_GFR_F22F23_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS0 Channels 22 and 23 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F22F23_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD2.emiosp->GFR.R;
-
-  if (gfr && (1U << 22U)) {
-    pwm_lld_serve_interrupt2(&PWMD2, 22U);
-  }
-  if (gfr && (1U << 23U)) {
-    pwm_lld_serve_interrupt2(&PWMD2, 23U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-#if !defined(SPC5_EMIOS1_GFR_F0F1_HANDLER)
-#error "SPC5_EMIOS1_GFR_F0F1_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 0 and 1 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F0F1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD3.emiosp->GFR.R;
-
-  if (gfr && (1U << 0)) {
-    pwm_lld_serve_interrupt1(&PWMD3, 0);
-  }
-  if (gfr && (1U << 1U)) {
-    pwm_lld_serve_interrupt2(&PWMD3, 1U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F2F3_HANDLER)
-#error "SPC5_EMIOS1_GFR_F2F3_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 2 and 3 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F2F3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD3.emiosp->GFR.R;
-
-  if (gfr && (1U << 2U)) {
-    pwm_lld_serve_interrupt2(&PWMD3, 2U);
-  }
-  if (gfr && (1U << 3U)) {
-    pwm_lld_serve_interrupt2(&PWMD3, 3U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F4F5_HANDLER)
-#error "SPC5_EMIOS1_GFR_F4F5_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 4 and 5 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F4F5_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD3.emiosp->GFR.R;
-
-  if (gfr && (1U << 4U)) {
-    pwm_lld_serve_interrupt2(&PWMD3, 4U);
-  }
-  if (gfr && (1U << 5U)) {
-    pwm_lld_serve_interrupt2(&PWMD3, 5U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F6F7_HANDLER)
-#error "SPC5_EMIOS1_GFR_F6F7_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 6 and 7 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F6F7_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD3.emiosp->GFR.R;
-
-  if (gfr && (1U << 6U)) {
-    pwm_lld_serve_interrupt2(&PWMD3, 6U);
-  }
-  if (gfr && (1U << 7U)) {
-    pwm_lld_serve_interrupt2(&PWMD3, 7U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-#if !defined(SPC5_EMIOS1_GFR_F8F9_HANDLER)
-#error "SPC5_EMIOS1_GFR_F8F9_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 8 and 9 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F8F9_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD4.emiosp->GFR.R;
-
-  if (gfr && (1U << 8U)) {
-    pwm_lld_serve_interrupt1(&PWMD4, 8U);
-  }
-  if (gfr && (1U << 9U)) {
-    pwm_lld_serve_interrupt2(&PWMD4, 9U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F10F11_HANDLER)
-#error "SPC5_EMIOS1_GFR_F10F11_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 10 and 11 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F10F11_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD4.emiosp->GFR.R;
-
-  if (gfr && (1U << 10U)) {
-    pwm_lld_serve_interrupt2(&PWMD4, 10U);
-  }
-  if (gfr && (1U << 11U)) {
-    pwm_lld_serve_interrupt2(&PWMD4, 11U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F12F13_HANDLER)
-#error "SPC5_EMIOS1_GFR_F12F13_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 12 and 13 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F12F13_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD4.emiosp->GFR.R;
-
-  if (gfr && (1U << 12U)) {
-    pwm_lld_serve_interrupt2(&PWMD4, 12U);
-  }
-  if (gfr && (1U << 13U)) {
-    pwm_lld_serve_interrupt2(&PWMD4, 13U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F14F15_HANDLER)
-#error "SPC5_EMIOS1_GFR_F14F15_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 14 and 15 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F14F15_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD4.emiosp->GFR.R;
-
-  if (gfr && (1U << 14U)) {
-    pwm_lld_serve_interrupt2(&PWMD4, 14U);
-  }
-  if (gfr && (1U << 15U)) {
-    pwm_lld_serve_interrupt2(&PWMD4, 15U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-#if !defined(SPC5_EMIOS1_GFR_F16F17_HANDLER)
-#error "SPC5_EMIOS1_GFR_F16F17_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 16 and 17 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F16F17_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD5.emiosp->GFR.R;
-
-  if (gfr && (1U << 16U)) {
-    pwm_lld_serve_interrupt1(&PWMD5, 16U);
-  }
-  if (gfr && (1U << 17U)) {
-    pwm_lld_serve_interrupt2(&PWMD5, 17U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F18F19_HANDLER)
-#error "SPC5_EMIOS1_GFR_F18F19_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 18 and 19 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F18F19_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD5.emiosp->GFR.R;
-
-  if (gfr && (1U << 18U)) {
-    pwm_lld_serve_interrupt2(&PWMD5, 18U);
-  }
-  if (gfr && (1U << 19U)) {
-    pwm_lld_serve_interrupt2(&PWMD5, 19U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F20F21_HANDLER)
-#error "SPC5_EMIOS1_GFR_F20F21_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 20 and 21 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F20F21_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD5.emiosp->GFR.R;
-
-  if (gfr && (1U << 20U)) {
-    pwm_lld_serve_interrupt2(&PWMD5, 20U);
-  }
-  if (gfr && (1U << 21U)) {
-    pwm_lld_serve_interrupt2(&PWMD5, 21U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F22F23_HANDLER)
-#error "SPC5_EMIOS1_GFR_F22F23_HANDLER not defined"
-#endif
-/**
- * @brief   eMIOS1 Channels 22 and 23 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F22F23_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  uint32_t gfr = PWMD5.emiosp->GFR.R;
-
-  if (gfr && (1U << 22U)) {
-    pwm_lld_serve_interrupt2(&PWMD5, 22U);
-  }
-  if (gfr && (1U << 23U)) {
-    pwm_lld_serve_interrupt2(&PWMD5, 23U);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-  /* eMIOSx channels initially all not in use.*/
-  reset_emios0_active_channels();
-  reset_emios1_active_channels();
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD1);
-  PWMD1.emiosp = &EMIOS_0;
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD2);
-  PWMD2.emiosp = &EMIOS_0;
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD3);
-  PWMD3.emiosp = &EMIOS_1;
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD4);
-  PWMD4.emiosp = &EMIOS_1;
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD5);
-  PWMD5.emiosp = &EMIOS_1;
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
-#if SPC5_PWM_USE_EMIOS0
-
-  INTC.PSR[SPC5_EMIOS0_GFR_F8F9_NUMBER].R = SPC5_EMIOS0_GFR_F8F9_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F10F11_NUMBER].R = SPC5_EMIOS0_GFR_F10F11_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F12F13_NUMBER].R = SPC5_EMIOS0_GFR_F12F13_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F14F15_NUMBER].R = SPC5_EMIOS0_GFR_F14F15_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F16F17_NUMBER].R = SPC5_EMIOS0_GFR_F16F17_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F18F19_NUMBER].R = SPC5_EMIOS0_GFR_F18F19_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F20F21_NUMBER].R = SPC5_EMIOS0_GFR_F20F21_PRIORITY;
-  INTC.PSR[SPC5_EMIOS0_GFR_F22F23_NUMBER].R = SPC5_EMIOS0_GFR_F22F23_PRIORITY;
-
-#endif
-
-#if SPC5_PWM_USE_EMIOS1
-
-  INTC.PSR[SPC5_EMIOS1_GFR_F0F1_NUMBER].R = SPC5_EMIOS1_GFR_F0F1_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F2F3_NUMBER].R = SPC5_EMIOS1_GFR_F2F3_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F4F5_NUMBER].R = SPC5_EMIOS1_GFR_F4F5_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F6F7_NUMBER].R = SPC5_EMIOS1_GFR_F6F7_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F8F9_NUMBER].R = SPC5_EMIOS1_GFR_F8F9_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F10F11_NUMBER].R = SPC5_EMIOS1_GFR_F10F11_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F12F13_NUMBER].R = SPC5_EMIOS1_GFR_F12F13_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F14F15_NUMBER].R = SPC5_EMIOS1_GFR_F14F15_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F16F17_NUMBER].R = SPC5_EMIOS1_GFR_F16F17_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F18F19_NUMBER].R = SPC5_EMIOS1_GFR_F18F19_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F20F21_NUMBER].R = SPC5_EMIOS1_GFR_F20F21_PRIORITY;
-  INTC.PSR[SPC5_EMIOS1_GFR_F22F23_NUMBER].R = SPC5_EMIOS1_GFR_F22F23_PRIORITY;
-
-#endif
-
-}
-
-/**
- * @brief   Configures and activates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-
-  uint32_t psc = 0, i = 0;
-
-  chDbgAssert(get_emios0_active_channels() < 28,
-              "pwm_lld_start(), #1", "too many channels");
-  chDbgAssert(get_emios1_active_channels() < 28,
-              "pwm_lld_start(), #2", "too many channels");
-
-  if (pwmp->state == PWM_STOP) {
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-    if (&PWMD1 == pwmp) {
-      increase_emios0_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-    if (&PWMD2 == pwmp) {
-      increase_emios0_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-    if (&PWMD3 == pwmp) {
-      increase_emios1_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-    if (&PWMD4 == pwmp) {
-      increase_emios1_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-    if (&PWMD5 == pwmp) {
-      increase_emios1_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
-    /* Set eMIOS0 Clock.*/
-#if SPC5_PWM_USE_EMIOS0
-    pwm_active_emios0_clock(pwmp);
-#endif
-
-    /* Set eMIOS1 Clock.*/
-#if SPC5_PWM_USE_EMIOS1
-    pwm_active_emios1_clock(pwmp);
-#endif
-
-  }
-  /* Configures the peripheral.*/
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-  if (&PWMD1 == pwmp) {
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-  if (&PWMD2 == pwmp) {
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-  if (&PWMD3 == pwmp) {
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~1U;
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[0].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-  if (&PWMD4 == pwmp) {
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-  if (&PWMD5 == pwmp) {
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-  }
-#endif
-
-  /* Set clock prescaler and control register.*/
-  if (pwmp->emiosp == &EMIOS_0) {
-    psc = (SPC5_EMIOS0_CLK / pwmp->config->frequency);
-    chDbgAssert((psc <= 0xFFFF) &&
-                (((psc) * pwmp->config->frequency) == SPC5_EMIOS0_CLK) &&
-                ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
-                "pwm_lld_start(), #1", "invalid frequency");
-  } else if (pwmp->emiosp == &EMIOS_1) {
-    psc = (SPC5_EMIOS1_CLK / pwmp->config->frequency);
-    chDbgAssert((psc <= 0xFFFF) &&
-                (((psc) * pwmp->config->frequency) == SPC5_EMIOS1_CLK) &&
-                ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
-                "pwm_lld_start(), #2", "invalid frequency");
-  }
-
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-  if (&PWMD1 == pwmp) {
-
-    pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0;
-    pwmp->emiosp->CH[8U].CCNTR.R = 1U;
-    pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period;
-    pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
-    pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
-    pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U;
-    pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN;
-
-    if (pwmp->config->mode == PWM_ALIGN_EDGE) {
-      for (i = 0; i < PWM_CHANNELS; i++) {
-        switch (pwmp->config->channels[i].mode) {
-        case PWM_OUTPUT_DISABLED:
-          break;
-        case PWM_OUTPUT_ACTIVE_HIGH:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 9U].CADR.R = 0;
-          pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
-          break;
-        case PWM_OUTPUT_ACTIVE_LOW:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 9U].CADR.R = 1U;
-          pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
-          break;
-        }
-      }
-
-      /* Channel disables.*/
-      pwmp->emiosp->UCDIS.R |= (1U << 8U);
-
-    }
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-  if (&PWMD2 == pwmp) {
-
-    pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0;
-    pwmp->emiosp->CH[16U].CCNTR.R = 1U;
-    pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period;
-    pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
-    pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
-    pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U;
-    pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN;
-
-    if (pwmp->config->mode == PWM_ALIGN_EDGE) {
-      for (i = 0; i < PWM_CHANNELS; i++) {
-        switch (pwmp->config->channels[i].mode) {
-        case PWM_OUTPUT_DISABLED:
-          break;
-        case PWM_OUTPUT_ACTIVE_HIGH:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 17U].CADR.R = 0;
-          pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
-          break;
-        case PWM_OUTPUT_ACTIVE_LOW:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 17U].CADR.R = 1U;
-          pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
-          break;
-        }
-      }
-
-      /* Channel disables.*/
-      pwmp->emiosp->UCDIS.R |= (1U << 16U);
-
-    }
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-  if (&PWMD3 == pwmp) {
-
-    pwmp->emiosp->CH[0].CCR.B.UCPEN = 0;
-    pwmp->emiosp->CH[0].CCNTR.R = 1U;
-    pwmp->emiosp->CH[0].CADR.R = pwmp->config->period;
-    pwmp->emiosp->CH[0].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
-    pwmp->emiosp->CH[0].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
-    pwmp->emiosp->CH[0].CCR.B.UCPRE = psc - 1U;
-    pwmp->emiosp->CH[0].CCR.R |= EMIOSC_UCPREN;
-
-    if (pwmp->config->mode == PWM_ALIGN_EDGE) {
-      for (i = 0; i < PWM_CHANNELS; i++) {
-        switch (pwmp->config->channels[i].mode) {
-        case PWM_OUTPUT_DISABLED:
-          break;
-        case PWM_OUTPUT_ACTIVE_HIGH:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 1U].CADR.R = 0;
-          pwmp->emiosp->CH[i + 1U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 1U));
-
-          break;
-        case PWM_OUTPUT_ACTIVE_LOW:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 1U].CADR.R = 1U;
-          pwmp->emiosp->CH[i + 1U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 1U].CCR.R &= ~EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 1U));
-
-          break;
-        }
-      }
-
-      /* Channel disables.*/
-      pwmp->emiosp->UCDIS.R |= 1U;
-
-    }
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-  if (&PWMD4 == pwmp) {
-
-    pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0;
-    pwmp->emiosp->CH[8U].CCNTR.R = 1U;
-    pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period;
-    pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
-    pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
-    pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U;
-    pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN;
-
-    if (pwmp->config->mode == PWM_ALIGN_EDGE) {
-      for (i = 0; i < PWM_CHANNELS; i++) {
-        switch (pwmp->config->channels[i].mode) {
-        case PWM_OUTPUT_DISABLED:
-          break;
-        case PWM_OUTPUT_ACTIVE_HIGH:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 9U].CADR.R = 0;
-          pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
-          break;
-        case PWM_OUTPUT_ACTIVE_LOW:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 9U].CADR.R = 1U;
-          pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
-          break;
-        }
-      }
-
-      /* Channel disables.*/
-      pwmp->emiosp->UCDIS.R |= (1U << 8U);
-
-    }
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-  if (&PWMD5 == pwmp) {
-
-    pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0;
-    pwmp->emiosp->CH[16U].CCNTR.R = 1U;
-    pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period;
-    pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
-    pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
-    pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U;
-    pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN;
-
-    if (pwmp->config->mode == PWM_ALIGN_EDGE) {
-      for (i = 0; i < PWM_CHANNELS; i++) {
-        switch (pwmp->config->channels[i].mode) {
-        case PWM_OUTPUT_DISABLED:
-          break;
-        case PWM_OUTPUT_ACTIVE_HIGH:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 17U].CADR.R = 0;
-          pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
-          break;
-        case PWM_OUTPUT_ACTIVE_LOW:
-
-          /* Channel enables.*/
-          pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
-          /* Clear pending IRQs (if any).*/
-          pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-              EMIOSS_FLAGC;
-
-          pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
-          pwmp->emiosp->CH[i + 17U].CADR.R = 1U;
-          pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
-          /* Set output polarity.*/
-          pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL;
-
-          /* Set unified channel mode.*/
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
-          pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
-          pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
-          /* Channel disables.*/
-          pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
-          break;
-        }
-      }
-
-      /* Channel disables.*/
-      pwmp->emiosp->UCDIS.R |= (1U << 16U);
-
-    }
-  }
-#endif
-
-}
-
-/**
- * @brief   Deactivates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
-  uint32_t i = 0;
-
-  chDbgAssert(get_emios0_active_channels() < 28, "pwm_lld_stop(), #1",
-              "too many channels");
-  chDbgAssert(get_emios1_active_channels() < 28, "pwm_lld_stop(), #2",
-              "too many channels");
-
-  if (pwmp->state == PWM_READY) {
-
-    /* Disables the peripheral.*/
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-    if (&PWMD1 == pwmp) {
-      /* Reset UC Control Register of group channels.*/
-      for (i = 0; i < 8; i++) {
-        pwmp->emiosp->CH[i + 8U].CCR.R = 0;
-      }
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-    if (&PWMD2 == pwmp) {
-      /* Reset UC Control Register of group channels.*/
-      for (i = 0; i < 8; i++) {
-        pwmp->emiosp->CH[i + 16U].CCR.R = 0;
-      }
-      decrease_emios0_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-    if (&PWMD3 == pwmp) {
-      /* Reset UC Control Register of group channels.*/
-      for (i = 0; i < 8; i++) {
-        pwmp->emiosp->CH[i].CCR.R = 0;
-      }
-      decrease_emios1_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-    if (&PWMD4 == pwmp) {
-      /* Reset UC Control Register of group channels.*/
-      for (i = 0; i < 8; i++) {
-        pwmp->emiosp->CH[i + 8U].CCR.R = 0;
-      }
-      decrease_emios1_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-    if (&PWMD5 == pwmp) {
-      /* Reset UC Control Register of group channels.*/
-      for (i = 0; i < 8; i++) {
-        pwmp->emiosp->CH[i + 16U].CCR.R = 0;
-      }
-      decrease_emios1_active_channels();
-    }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
-    /* eMIOS0 clock deactivation.*/
-#if SPC5_PWM_USE_EMIOS0
-    pwm_deactive_emios0_clock(pwmp);
-#endif
-
-    /* eMIOS1 clock deactivation.*/
-#if SPC5_PWM_USE_EMIOS1
-    pwm_deactive_emios1_clock(pwmp);
-#endif
-  }
-}
-
-/**
- * @brief   Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- *          been activated using @p pwmStart().
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The PWM unit period is changed to the new value.
- * @note    The function has effect at the next cycle start.
- * @note    If a period is specified that is shorter than the pulse width
- *          programmed in one of the channels then the behavior is not
- *          guaranteed.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] period    new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-  if (&PWMD1 == pwmp) {
-    pwmp->period = period;
-    pwmp->emiosp->CH[8U].CADR.R = period;
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-  if (&PWMD2 == pwmp) {
-    pwmp->period = period;
-    pwmp->emiosp->CH[16U].CADR.R = period;
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-  if (&PWMD3 == pwmp) {
-    pwmp->period = period;
-    pwmp->emiosp->CH[0].CADR.R = period;
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-  if (&PWMD4 == pwmp) {
-    pwmp->period = period;
-    pwmp->emiosp->CH[8U].CADR.R = period;
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-  if (&PWMD5 == pwmp) {
-    pwmp->period = period;
-    pwmp->emiosp->CH[16U].CADR.R = period;
-  }
-#endif
-
-}
-
-/**
- * @brief   Enables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is active using the specified configuration.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t channel,
-                            pwmcnt_t width) {
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-  if (&PWMD1 == pwmp) {
-
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel));
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-    /* Set PWM width.*/
-    pwmp->emiosp->CH[channel + 9U].CBDR.R = width;
-
-    /* Active interrupts.*/
-    if (pwmp->config->channels[channel].callback != NULL) {
-      pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U;
-    }
-
-    /* Enables timer base channel if disable.*/
-    if (pwmp->emiosp->UCDIS.R & (1U << 8U)) {
-      /* Channel enables.*/
-      pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
-      /* Active interrupts.*/
-      if (pwmp->config->callback != NULL ) {
-        pwmp->emiosp->CH[8U].CCR.B.FEN = 1U;
-      }
-    }
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-  if (&PWMD2 == pwmp) {
-
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel));
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-    /* Set PWM width.*/
-    pwmp->emiosp->CH[channel + 17U].CBDR.R = width;
-
-    /* Active interrupts.*/
-    if (pwmp->config->channels[channel].callback != NULL) {
-      pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U;
-    }
-
-    /* Enables timer base channel if disable.*/
-    if (pwmp->emiosp->UCDIS.R & (1U << 16U)) {
-      /* Channel enables.*/
-      pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
-      /* Active interrupts.*/
-      if (pwmp->config->callback != NULL ) {
-        pwmp->emiosp->CH[16U].CCR.B.FEN = 1U;
-      }
-    }
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-  if (&PWMD3 == pwmp) {
-
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~(1U << (1U + channel));
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-    /* Set PWM width.*/
-    pwmp->emiosp->CH[channel + 1U].CBDR.R = width;
-
-
-    /* Active interrupts.*/
-    if (pwmp->config->channels[channel].callback != NULL) {
-      pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 1U;
-    }
-
-    /* Enables timer base channel if disable.*/
-    if (pwmp->emiosp->UCDIS.R & 1U) {
-      /* Channel enables.*/
-      pwmp->emiosp->UCDIS.R &= ~1U;
-
-      /* Active interrupts.*/
-      if (pwmp->config->callback != NULL ) {
-        pwmp->emiosp->CH[0].CCR.B.FEN = 1U;
-      }
-    }
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-  if (&PWMD4 == pwmp) {
-
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel));
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-    /* Set PWM width.*/
-    pwmp->emiosp->CH[channel + 9U].CBDR.R = width;
-
-    /* Active interrupts.*/
-    if (pwmp->config->channels[channel].callback != NULL) {
-      pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U;
-    }
-
-    /* Enables timer base channel if disable.*/
-    if (pwmp->emiosp->UCDIS.R & (1U << 8U)) {
-      /* Channel enables.*/
-      pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
-      /* Active interrupts.*/
-      if (pwmp->config->callback != NULL ) {
-        pwmp->emiosp->CH[8U].CCR.B.FEN = 1U;
-      }
-    }
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-  if (&PWMD5 == pwmp) {
-
-    /* Channel enables.*/
-    pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel));
-
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
-        EMIOSS_FLAGC;
-
-    /* Set PWM width.*/
-    pwmp->emiosp->CH[channel + 17U].CBDR.R = width;
-
-    /* Active interrupts.*/
-    if (pwmp->config->channels[channel].callback != NULL) {
-      pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U;
-    }
-
-    /* Enables timer base channel if disable.*/
-    if (pwmp->emiosp->UCDIS.R & (1U << 16U)) {
-      /* Channel enables.*/
-      pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
-      /* Active interrupts.*/
-      if (pwmp->config->callback != NULL ) {
-        pwmp->emiosp->CH[16U].CCR.B.FEN = 1U;
-      }
-    }
-
-  }
-#endif
-
-}
-
-/**
- * @brief   Disables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is disabled and its output line returned to the
- *          idle state.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-  if (&PWMD1 == pwmp) {
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC |
-          EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-    /* Disable interrupts.*/
-    pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0;
-
-    /* Disable channel.*/
-    pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U));
-
-    /* Disable timer base channel if all PWM channels are disabled.*/
-    if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) {
-      /* Deactive interrupts.*/
-      pwmp->emiosp->CH[8U].CCR.B.FEN = 0;
-
-      /* Disable channel.*/
-      pwmp->emiosp->UCDIS.R |= (1U << 8U);
-    }
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-  if (&PWMD2 == pwmp) {
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC |
-          EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-    /* Disable interrupts.*/
-    pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0;
-
-    /* Disable channel.*/
-    pwmp->emiosp->UCDIS.R |= (1U << (channel + 17));
-
-    /* Disable timer base channel if all PWM channels are disabled.*/
-    if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) {
-      /* Deactive interrupts.*/
-      pwmp->emiosp->CH[16U].CCR.B.FEN = 0;
-
-      /* Disable channel.*/
-      pwmp->emiosp->UCDIS.R |= (1U << 16U);
-    }
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-  if (&PWMD3 == pwmp) {
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC |
-          EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-    /* Disable interrupts.*/
-    pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 0;
-
-    /* Disable channel.*/
-    pwmp->emiosp->UCDIS.R |= (1U << (channel + 1U));
-
-    /* Disable timer base channel if all PWM channels are disabled.*/
-    if ((pwmp->emiosp->UCDIS.R & 0xFE) == 0xFE) {
-      /* Deactive interrupts.*/
-      pwmp->emiosp->CH[0].CCR.B.FEN = 0;
-
-      /* Disable channel.*/
-      pwmp->emiosp->UCDIS.R |= 1U;
-    }
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-  if (&PWMD4 == pwmp) {
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC |
-          EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-    /* Disable interrupts.*/
-    pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0;
-
-    /* Disable channel.*/
-    pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U));
-
-    /* Disable timer base channel if all PWM channels are disabled.*/
-    if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) {
-      /* Deactive interrupts.*/
-      pwmp->emiosp->CH[8U].CCR.B.FEN = 0;
-
-      /* Disable channel.*/
-      pwmp->emiosp->UCDIS.R |= (1U << 8U);
-    }
-
-  }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-  if (&PWMD5 == pwmp) {
-    /* Clear pending IRQs (if any).*/
-    pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC |
-          EMIOSS_OVFLC | EMIOSS_FLAGC;
-
-    /* Disable interrupts.*/
-    pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0;
-
-    /* Disable channel.*/
-    pwmp->emiosp->UCDIS.R |= (1U << (channel + 17U));
-
-    /* Disable timer base channel if all PWM channels are disabled.*/
-    if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) {
-      /* Deactive interrupts.*/
-      pwmp->emiosp->CH[16U].CCR.B.FEN = 0;
-
-      /* Disable channel.*/
-      pwmp->emiosp->UCDIS.R |= (1U << 16U);
-    }
-
-  }
-#endif
-
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h
deleted file mode 100644
index e2dc403a8..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    eMIOS_v1/pwm_lld.h
- * @brief   SPC5xx low level PWM driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS                            7
-
-/**
- * @brief   Edge-Aligned PWM functional mode.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_EDGE                          0x00
-
-/**
- * @brief   Center-Aligned PWM functional mode.
- * @note    This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_CENTER                        0x01
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__)
-/**
- * @brief   PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS0_GROUP0) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS0__GROUP0         FALSE
-#endif
-
-/**
- * @brief   PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS0_GROUP1) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS0_GROUP1          FALSE
-#endif
-
-/**
- * @brief   PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F8F9_PRIORITY       7
-#endif
-
-/**
- * @brief   PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F10F11_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F12F13_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F14F15_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F16F17_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F18F19_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F20F21_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F22F23_PRIORITY     7
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__)
-/**
- * @brief   PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS1_GROUP0) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS1_GROUP0          FALSE
-#endif
-
-/**
- * @brief   PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS1_GROUP1) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS1_GROUP1          FALSE
-#endif
-
-/**
- * @brief   PWMD5 driver enable switch.
- * @details If set to @p TRUE the support for PWMD5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS1_GROUP2) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS1_GROUP2          FALSE
-#endif
-
-/**
- * @brief   PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F0F1_PRIORITY       7
-#endif
-
-/**
- * @brief   PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F2F3_PRIORITY       7
-#endif
-
-/**
- * @brief   PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F4F5_PRIORITY       7
-#endif
-
-/**
- * @brief   PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F6F7_PRIORITY       7
-#endif
-
-/**
- * @brief   PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F8F9_PRIORITY       7
-#endif
-
-/**
- * @brief   PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F10F11_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F12F13_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F14F15_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F16F17_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F18F19_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F20F21_PRIORITY     7
-#endif
-
-/**
- * @brief   PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F22F23_PRIORITY     7
-#endif
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS0
-#error "EMIOS0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_EMIOS1
-#error "EMIOS1 not present in the selected device"
-#endif
-
-#define SPC5_PWM_USE_EMIOS0                 (SPC5_PWM_USE_EMIOS0_GROUP0 ||  \
-                                             SPC5_PWM_USE_EMIOS0_GROUP1)
-
-#define SPC5_PWM_USE_EMIOS1                 (SPC5_PWM_USE_EMIOS1_GROUP0 ||  \
-                                             SPC5_PWM_USE_EMIOS1_GROUP1 ||  \
-                                             SPC5_PWM_USE_EMIOS1_GROUP2)
-
-#if !SPC5_PWM_USE_EMIOS0 && !SPC5_PWM_USE_EMIOS1
-#error "PWM driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief   PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief   PWM counter type.
- */
-typedef uint32_t pwmcnt_t;
-
-/**
- * @brief   PWM driver channel configuration structure.
- * @note    Some architectures may not be able to support the channel mode
- *          or the callback, in this case the fields are ignored.
- */
-typedef struct {
-  /**
-   * @brief Channel active logic level.
-   */
-  pwmmode_t                 mode;
-  /**
-   * @brief Channel callback pointer.
-   * @note  This callback is invoked on the channel compare event. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief Timer clock in Hz.
-   * @note  The low level can use assertions in order to catch invalid
-   *        frequency specifications.
-   */
-  uint32_t                  frequency;
-  /**
-   * @brief PWM period in ticks.
-   * @note  The low level can use assertions in order to catch invalid
-   *        period specifications.
-   */
-  pwmcnt_t                  period;
-  /**
-   * @brief Periodic callback pointer.
-   * @note  This callback is invoked on PWM counter reset. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /**
-   * @brief Channels configurations.
-   */
-  PWMChannelConfig          channels[PWM_CHANNELS];
-  /* End of the mandatory fields.*/
-  /**
-   * @brief PWM functional mode.
-   */
-  pwmmode_t                 mode;
-} PWMConfig;
-
-/**
- * @brief   Structure representing an PWM driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct PWMDriver {
-  /**
-   * @brief Driver state.
-   */
-  pwmstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const PWMConfig           *config;
-  /**
-   * @brief Current PWM period in ticks.
-   */
-  pwmcnt_t                  period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
-  PWM_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the eMIOSx registers block.
-   */
-  volatile struct EMIOS_tag *emiosp;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD5;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void pwm_lld_init(void);
-  void pwm_lld_start(PWMDriver *pwmp);
-  void pwm_lld_stop(PWMDriver *pwmp);
-  void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
-  void pwm_lld_enable_channel(PWMDriver *pwmp,
-                              pwmchannel_t channel,
-                              pwmcnt_t width);
-  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c
deleted file mode 100644
index 9be0ed1c1..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    eMIOS_v1/spc5_emios.c
- * @brief   SPC5xx low level ICU and PWM drivers common code.
- *
- * @addtogroup ICU - PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of active eMIOSx Channels.
- */
-static uint32_t emios0_active_channels;
-static uint32_t emios1_active_channels;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if SPC5_HAS_EMIOS0
-void reset_emios0_active_channels() {
-  emios0_active_channels = 0;
-}
-
-uint32_t get_emios0_active_channels() {
-  return emios0_active_channels;
-}
-
-void increase_emios0_active_channels() {
-  emios0_active_channels++;
-}
-
-void decrease_emios0_active_channels() {
-  emios0_active_channels--;
-}
-
-#if HAL_USE_ICU
-void icu_active_emios0_clock(ICUDriver *icup) {
-  /* If this is the first Channel activated then the eMIOS0 is enabled.*/
-  if (emios0_active_channels == 1) {
-    halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
-                                 SPC5_EMIOS0_START_PCTL);
-
-    /* Disable all unified channels.*/
-    icup->emiosp->MCR.B.GPREN = 0;
-    icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);
-    icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
-    icup->emiosp->MCR.B.GTBE = 1U;
-
-    icup->emiosp->UCDIS.R = 0xFFFFFFFF;
-
-  }
-}
-
-void icu_deactive_emios0_clock(ICUDriver *icup) {
-  /* If it is the last active channels then the eMIOS0 is disabled.*/
-  if (emios0_active_channels == 0) {
-    if (icup->emiosp->UCDIS.R == 0) {
-      halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
-                                   SPC5_EMIOS0_STOP_PCTL);
-    }
-  }
-}
-#endif
-
-#if HAL_USE_PWM
-void pwm_active_emios0_clock(PWMDriver *pwmp) {
-  /* If this is the first Channel activated then the eMIOS0 is enabled.*/
-  if (emios0_active_channels == 1) {
-    halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
-                                 SPC5_EMIOS0_START_PCTL);
-
-    /* Disable all unified channels.*/
-    pwmp->emiosp->MCR.B.GPREN = 0;
-    pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);
-    pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
-    pwmp->emiosp->MCR.B.GTBE = 1U;
-
-    pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
-
-  }
-}
-
-void pwm_deactive_emios0_clock(PWMDriver *pwmp) {
-  /* If it is the last active channels then the eMIOS0 is disabled.*/
-  if (emios0_active_channels == 0) {
-    if (pwmp->emiosp->UCDIS.R == 0) {
-      halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
-                                   SPC5_EMIOS0_STOP_PCTL);
-    }
-  }
-}
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1
-void reset_emios1_active_channels() {
-  emios1_active_channels = 0;
-}
-
-uint32_t get_emios1_active_channels() {
-  return emios1_active_channels;
-}
-
-void increase_emios1_active_channels() {
-  emios1_active_channels++;
-}
-
-void decrease_emios1_active_channels() {
-  emios1_active_channels--;
-}
-
-#if HAL_USE_ICU
-void icu_active_emios1_clock(ICUDriver *icup) {
-  /* If this is the first Channel activated then the eMIOS1 is enabled.*/
-  if (emios1_active_channels == 1) {
-    halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
-                                 SPC5_EMIOS1_START_PCTL);
-
-    /* Disable all unified channels.*/
-    icup->emiosp->MCR.B.GPREN = 0;
-    icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE);
-    icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
-    icup->emiosp->MCR.B.GTBE = 1U;
-
-    icup->emiosp->UCDIS.R = 0xFFFFFFFF;
-
-  }
-}
-
-void icu_deactive_emios1_clock(ICUDriver *icup) {
-  /* If it is the last active channels then the eMIOS1 is disabled.*/
-  if (emios1_active_channels == 0) {
-    if (icup->emiosp->UCDIS.R == 0) {
-      halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
-                                   SPC5_EMIOS1_STOP_PCTL);
-    }
-  }
-}
-#endif
-
-#if HAL_USE_PWM
-void pwm_active_emios1_clock(PWMDriver *pwmp) {
-  /* If this is the first Channel activated then the eMIOS1 is enabled.*/
-  if (emios1_active_channels == 1) {
-    halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
-                                 SPC5_EMIOS1_START_PCTL);
-
-    /* Disable all unified channels.*/
-    pwmp->emiosp->MCR.B.GPREN = 0;
-    pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE);
-    pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
-    pwmp->emiosp->MCR.B.GTBE = 1U;
-
-    pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
-
-  }
-}
-
-void pwm_deactive_emios1_clock(PWMDriver *pwmp) {
-  /* If it is the last active channels then the eMIOS1 is disabled.*/
-  if (emios1_active_channels == 0) {
-    if (pwmp->emiosp->UCDIS.R == 0) {
-      halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
-                                   SPC5_EMIOS1_STOP_PCTL);
-    }
-  }
-}
-#endif
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-
-#endif /* HAL_USE_ICU || HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h
deleted file mode 100644
index 8ac549c65..000000000
--- a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    eMIOS_v1/spc5_emios.h
- * @brief   SPC5xx low level ICU - PWM driver common header.
- *
- * @addtogroup ICU - PWM
- * @{
- */
-
-#ifndef _SPC5_EMIOS_H_
-#define _SPC5_EMIOS_H_
-
-#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define EMIOSMCR_MDIS                       (1U << 30U)
-#define EMIOSMCR_FRZ                        (1U << 29U)
-#define EMIOSMCR_GTBE                       (1U << 28U)
-#define EMIOSMCR_GPREN                      (1U << 26U)
-#define EMIOSMCR_GPRE(n)                    ((n) << 8U)
-
-#define EMIOSC_FREN                         (1U << 31U)
-#define EMIOSC_UCPRE(n)                     ((n) << 26U)
-#define EMIOSC_UCPREN                       (1U << 25U)
-#define EMIOSC_DMA                          (1U << 24U)
-#define EMIOSC_IF(n)                        ((n) << 19U)
-#define EMIOSC_FCK                          (1U << 18U)
-#define EMIOSC_FEN                          (1U << 17U)
-#define EMIOSC_FORCMA                       (1U << 13U)
-#define EMIOSC_FORCMB                       (1U << 12U)
-#define EMIOSC_BSL(n)                       ((n) << 9U)
-#define EMIOSC_EDSEL                        (1U << 8U)
-#define EMIOSC_EDPOL                        (1U << 7U)
-#define EMIOSC_MODE(n)                      ((n) << 0)
-
-#define EMIOS_BSL_COUNTER_BUS_A             0
-#define EMIOS_BSL_COUNTER_BUS_2             1U
-#define EMIOS_BSL_INTERNAL_COUNTER          3U
-
-#define EMIOS_CCR_MODE_GPIO_IN              0
-#define EMIOS_CCR_MODE_GPIO_OUT             1U
-#define EMIOS_CCR_MODE_SAIC                 2U
-#define EMIOS_CCR_MODE_SAOC                 3U
-#define EMIOS_CCR_MODE_IPWM                 4U
-#define EMIOS_CCR_MODE_IPM                  5U
-#define EMIOS_CCR_MODE_DAOC_B_MATCH         6U
-#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH      7U
-#define EMIOS_CCR_MODE_MC_CMS               16U
-#define EMIOS_CCR_MODE_MC_CME               17U
-#define EMIOS_CCR_MODE_MC_UP_DOWN           18U
-#define EMIOS_CCR_MODE_OPWMT                38U
-#define EMIOS_CCR_MODE_MCB_UP               80U
-#define EMIOS_CCR_MODE_MCB_UP_DOWN          84U
-#define EMIOS_CCR_MODE_OPWFMB               88U
-#define EMIOS_CCR_MODE_OPWMCB_TE            92U
-#define EMIOS_CCR_MODE_OPWMCB_LE            93U
-#define EMIOS_CCR_MODE_OPWMB                96U
-
-#define EMIOSS_OVR                          (1U << 31U)
-#define EMIOSS_OVRC                         (1U << 31U)
-#define EMIOSS_OVFL                         (1U << 15U)
-#define EMIOSS_OVFLC                        (1U << 15U)
-#define EMIOSS_FLAG                         (1U << 0)
-#define EMIOSS_FLAGC                        (1U << 0)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-#if SPC5_HAS_EMIOS0
-/**
- * @brief   eMIOS0 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_START_PCTL              (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   eMIOS0 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_STOP_PCTL               (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1
-/**
- * @brief   eMIOS1 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_START_PCTL              (SPC5_ME_PCTL_RUN(1) |  \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   eMIOS1 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_STOP_PCTL               (SPC5_ME_PCTL_RUN(0) |  \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_HAS_EMIOS0
-void reset_emios0_active_channels(void);
-uint32_t get_emios0_active_channels(void);
-void increase_emios0_active_channels(void);
-void decrease_emios0_active_channels(void);
-void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
-void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
-#if HAL_USE_ICU
-void icu_active_emios0_clock(ICUDriver *icup);
-void icu_deactive_emios0_clock(ICUDriver *icup);
-#endif
-#if HAL_USE_PWM
-void pwm_active_emios0_clock(PWMDriver *pwmp);
-void pwm_deactive_emios0_clock(PWMDriver *pwmp);
-#endif
-#endif
-#if SPC5_HAS_EMIOS1
-void reset_emios1_active_channels(void);
-uint32_t get_emios1_active_channels(void);
-void increase_emios1_active_channels(void);
-void decrease_emios1_active_channels(void);
-#if HAL_USE_ICU
-void icu_active_emios1_clock(ICUDriver *icup);
-void icu_deactive_emios1_clock(ICUDriver *icup);
-#endif
-#if HAL_USE_PWM
-void pwm_active_emios1_clock(PWMDriver *pwmp);
-void pwm_deactive_emios1_clock(PWMDriver *pwmp);
-#endif
-#endif
-
-#endif /* HAL_USE_ICU || HAL_USE_PWM */
-
-#endif /* _SPC5_EMIOS_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
deleted file mode 100644
index 4cdfab8f7..000000000
--- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
+++ /dev/null
@@ -1,1389 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    eTimer_v1/icu_lld.c
- * @brief   SPC5xx low level ICU driver code.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ICUD1 driver identifier.
- * @note    The driver ICUD1 allocates the complex timer SMOD0 when enabled.
- */
-#if SPC5_ICU_USE_SMOD0 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-
-/**
- * @brief   ICUD2 driver identifier.
- * @note    The driver ICUD2 allocates the complex timer SMOD1 when enabled.
- */
-#if SPC5_ICU_USE_SMOD1 || defined(__DOXYGEN__)
-ICUDriver ICUD2;
-#endif
-
-/**
- * @brief   ICUD3 driver identifier.
- * @note    The driver ICUD3 allocates the complex timer SMOD2 when enabled.
- */
-#if SPC5_ICU_USE_SMOD2 || defined(__DOXYGEN__)
-ICUDriver ICUD3;
-#endif
-
-/**
- * @brief   ICUD4 driver identifier.
- * @note    The driver ICUD4 allocates the complex timer SMOD3 when enabled.
- */
-#if SPC5_ICU_USE_SMOD3 || defined(__DOXYGEN__)
-ICUDriver ICUD4;
-#endif
-
-/**
- * @brief   ICUD5 driver identifier.
- * @note    The driver ICUD5 allocates the complex timer SMOD4 when enabled.
- */
-#if SPC5_ICU_USE_SMOD4 || defined(__DOXYGEN__)
-ICUDriver ICUD5;
-#endif
-
-/**
- * @brief   ICUD6 driver identifier.
- * @note    The driver ICUD6 allocates the complex timer SMOD5 when enabled.
- */
-#if SPC5_ICU_USE_SMOD5 || defined(__DOXYGEN__)
-ICUDriver ICUD6;
-#endif
-
-/**
- * @brief   ICUD7 driver identifier.
- * @note    The driver ICUD7 allocates the complex timer SMOD6 when enabled.
- */
-#if SPC5_ICU_USE_SMOD6 || defined(__DOXYGEN__)
-ICUDriver ICUD7;
-#endif
-
-/**
- * @brief   ICUD8 driver identifier.
- * @note    The driver ICUD8 allocates the complex timer SMOD7 when enabled.
- */
-#if SPC5_ICU_USE_SMOD7 || defined(__DOXYGEN__)
-ICUDriver ICUD8;
-#endif
-
-/**
- * @brief   ICUD9 driver identifier.
- * @note    The driver ICUD9 allocates the complex timer SMOD8 when enabled.
- */
-#if SPC5_ICU_USE_SMOD8 || defined(__DOXYGEN__)
-ICUDriver ICUD9;
-#endif
-
-/**
- * @brief   ICUD10 driver identifier.
- * @note    The driver ICUD10 allocates the complex timer SMOD9 when enabled.
- */
-#if SPC5_ICU_USE_SMOD9 || defined(__DOXYGEN__)
-ICUDriver ICUD10;
-#endif
-
-/**
- * @brief   ICUD11 driver identifier.
- * @note    The driver ICUD11 allocates the complex timer SMOD10 when enabled.
- */
-#if SPC5_ICU_USE_SMOD10 || defined(__DOXYGEN__)
-ICUDriver ICUD11;
-#endif
-
-/**
- * @brief   ICUD12 driver identifier.
- * @note    The driver ICUD12 allocates the complex timer SMOD11 when enabled.
- */
-#if SPC5_ICU_USE_SMOD11 || defined(__DOXYGEN__)
-ICUDriver ICUD12;
-#endif
-
-/**
- * @brief   ICUD13 driver identifier.
- * @note    The driver ICUD13 allocates the complex timer SMOD12 when enabled.
- */
-#if SPC5_ICU_USE_SMOD12 || defined(__DOXYGEN__)
-ICUDriver ICUD13;
-#endif
-
-/**
- * @brief   ICUD14 driver identifier.
- * @note    The driver ICUD14 allocates the complex timer SMOD13 when enabled.
- */
-#if SPC5_ICU_USE_SMOD13 || defined(__DOXYGEN__)
-ICUDriver ICUD14;
-#endif
-
-/**
- * @brief   ICUD15 driver identifier.
- * @note    The driver ICUD15 allocates the complex timer SMOD14 when enabled.
- */
-#if SPC5_ICU_USE_SMOD14 || defined(__DOXYGEN__)
-ICUDriver ICUD15;
-#endif
-
-/**
- * @brief   ICUD16 driver identifier.
- * @note    The driver ICUD16 allocates the complex timer SMOD15 when enabled.
- */
-#if SPC5_ICU_USE_SMOD15 || defined(__DOXYGEN__)
-ICUDriver ICUD16;
-#endif
-
-/**
- * @brief   ICUD17 driver identifier.
- * @note    The driver ICUD17 allocates the complex timer SMOD16 when enabled.
- */
-#if SPC5_ICU_USE_SMOD16 || defined(__DOXYGEN__)
-ICUDriver ICUD17;
-#endif
-
-/**
- * @brief   ICUD18 driver identifier.
- * @note    The driver ICUD18 allocates the complex timer SMOD17 when enabled.
- */
-#if SPC5_ICU_USE_SMOD17 || defined(__DOXYGEN__)
-ICUDriver ICUD18;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Number of active eTimer Submodules.
- */
-static uint32_t icu_active_submodules0;
-static uint32_t icu_active_submodules1;
-static uint32_t icu_active_submodules2;
-
-/**
- * @brief   Width and Period registers.
- */
-uint16_t width;
-uint16_t period;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
-  uint16_t sr = icup->etimerp->CHANNEL[icup->smod_number].STS.R &
-                icup->etimerp->CHANNEL[icup->smod_number].INTDMA.R;
-
-  if (ICU_SKIP_FIRST_CAPTURE) {
-    if ((sr & 0x0008) != 0) { /* TOF */
-      icup->etimerp->CHANNEL[icup->smod_number].STS.B.TOF = 1U;
-      _icu_isr_invoke_overflow_cb(icup);
-    }
-    if ((sr & 0x0040) != 0) { /* ICF1 */
-      if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE ==
-          SPC5_ETIMER_CNTMODE_RFE_SIHA) {
-        icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
-        icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
-            SPC5_ETIMER_CNTMODE_RE;
-      }
-      else {
-        icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
-        if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C1FCNT == 2) {
-          period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
-          period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
-        } else {
-          period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
-        }
-        _icu_isr_invoke_period_cb(icup);
-      }
-    }
-    else if ((sr & 0x0080) != 0) { /* ICF2 */
-      if (icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE ==
-          SPC5_ETIMER_CNTMODE_RFE_SIHA) {
-        icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U;
-        icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0;
-      }
-      else {
-        icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U;
-        if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C2FCNT == 2) {
-          width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
-          width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
-        } else {
-          width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
-        }
-        _icu_isr_invoke_width_cb(icup);
-      }
-    }
-  } else { /* ICU_SKIP_FIRST_CAPTURE = TRUE*/
-    if ((sr & 0x0008) != 0) { /* TOF */
-      icup->etimerp->CHANNEL[icup->smod_number].STS.B.TOF = 1U;
-      _icu_isr_invoke_overflow_cb(icup);
-    }
-    if ((sr & 0x0040) != 0) { /* ICF1 */
-      icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
-      if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C1FCNT == 2) {
-        period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
-        period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
-      } else {
-        period = icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R;
-      }
-      _icu_isr_invoke_period_cb(icup);
-    }
-    else if ((sr & 0x0080) != 0) { /* ICF2 */
-      icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U;
-      if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C2FCNT == 2) {
-        width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
-        width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
-      } else {
-        width = icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R;
-      }
-      _icu_isr_invoke_width_cb(icup);
-    }
-  } /* ICU_SKIP_FIRST_CAPTURE = FALSE */
-}
-
-/**
- * @brief   eTimer SubModules initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp       pointer to a @p ICUDriver object
- * @param[in] config    the architecture-dependent ICU driver configuration
- */
-static void spc5_icu_smod_init(ICUDriver *icup) {
-  uint32_t psc = (icup->clock / icup->config->frequency);
-
-  chDbgAssert((psc <= 0xFFFF) &&
-              ((psc * icup->config->frequency) == icup->clock) &&
-              ((psc == 1) || (psc == 2) || (psc == 4) ||
-               (psc == 8) || (psc == 16) || (psc == 32) ||
-               (psc == 64) || (psc == 128)),
-              "spc5_icu_smod_init(), #1", "invalid frequency");
-
-  /* Set primary source and clock prescaler.*/
-  switch (psc) {
-  case 1:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
-        SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1;
-    break;
-  case 2:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
-        SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2;
-    break;
-  case 4:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
-        SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4;
-    break;
-  case 8:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
-        SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_8;
-    break;
-  case 16:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
-        SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_16;
-    break;
-  case 32:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
-        SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_32;
-    break;
-  case 64:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
-        SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_64;
-    break;
-  case 128:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.PRISRC =
-        SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_128;
-    break;
-  }
-
-  /* Set control registers.*/
-  icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.ONCE = 0U;
-  icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.LENGTH = 0U;
-  icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.DIR = 0U;
-  icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.PIPS = 0U;
-
-  /* Set secondary source.*/
-  switch (icup->smod_number) {
-  case 0:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
-        SPC5_ETIMER_COUNTER_0_INPUT_PIN;
-    break;
-  case 1:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
-        SPC5_ETIMER_COUNTER_1_INPUT_PIN;
-    break;
-  case 2:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
-        SPC5_ETIMER_COUNTER_2_INPUT_PIN;
-    break;
-  case 3:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
-        SPC5_ETIMER_COUNTER_3_INPUT_PIN;
-    break;
-  case 4:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
-        SPC5_ETIMER_COUNTER_4_INPUT_PIN;
-    break;
-  case 5:
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
-        SPC5_ETIMER_COUNTER_5_INPUT_PIN;
-    break;
-  }
-
-  /* Set secondary source polarity.*/
-  if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.SIPS = 0U;
-  }
-  else {
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.SIPS = 1U;
-  }
-
-  /* Direct pointers to the capture registers in order to make reading
-     data faster from within callbacks.*/
-  icup->pccrp = &period;
-  icup->wccrp = &width;
-
-  /* Enable channel.*/
-  icup->etimerp->ENBL.B.ENBL |= 1U << (icup->smod_number);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_SMOD0
-#if !defined(SPC5_ETIMER0_TC0IR_HANDLER)
-#error "SPC5_ETIMER0_TC0IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer0 Channel 0 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC0IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD0 */
-
-#if SPC5_ICU_USE_SMOD1
-#if !defined(SPC5_ETIMER0_TC1IR_HANDLER)
-#error "SPC5_ETIMER0_TC1IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer0 Channel 1 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC1IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD1 */
-
-#if SPC5_ICU_USE_SMOD2
-#if !defined(SPC5_ETIMER0_TC2IR_HANDLER)
-#error "SPC5_ETIMER0_TC2IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer0 Channel 2 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC2IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD2 */
-
-#if SPC5_ICU_USE_SMOD3
-#if !defined(SPC5_ETIMER0_TC3IR_HANDLER)
-#error "SPC5_ETIMER0_TC3IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer0 Channel 3 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC3IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD3 */
-
-#if SPC5_ICU_USE_SMOD4
-#if !defined(SPC5_ETIMER0_TC4IR_HANDLER)
-#error "SPC5_ETIMER0_TC4IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer0 Channel 4 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC4IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD4 */
-
-#if SPC5_ICU_USE_SMOD5
-#if !defined(SPC5_ETIMER0_TC5IR_HANDLER)
-#error "SPC5_ETIMER0_TC5IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer0 Channel 5 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER0_TC5IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD5 */
-
-#if SPC5_ICU_USE_SMOD6
-#if !defined(SPC5_ETIMER1_TC0IR_HANDLER)
-#error "SPC5_ETIMER1_TC0IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer1 Channel 0 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC0IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD7);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD6 */
-
-#if SPC5_ICU_USE_SMOD7
-#if !defined(SPC5_ETIMER1_TC1IR_HANDLER)
-#error "SPC5_ETIMER1_TC1IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer1 Channel 1 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC1IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD8);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD7 */
-
-#if SPC5_ICU_USE_SMOD8
-#if !defined(SPC5_ETIMER1_TC2IR_HANDLER)
-#error "SPC5_ETIMER1_TC2IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer1 Channel 2 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC2IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD9);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD8 */
-
-#if SPC5_ICU_USE_SMOD9
-#if !defined(SPC5_ETIMER1_TC3IR_HANDLER)
-#error "SPC5_ETIMER1_TC3IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer1 Channel 3 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC3IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD10);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD9 */
-
-#if SPC5_ICU_USE_SMOD10
-#if !defined(SPC5_ETIMER1_TC4IR_HANDLER)
-#error "SPC5_ETIMER1_TC4IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer1 Channel 4 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC4IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD11);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD10 */
-
-#if SPC5_ICU_USE_SMOD11
-#if !defined(SPC5_ETIMER1_TC5IR_HANDLER)
-#error "SPC5_ETIMER1_TC5IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer1 Channel 5 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER1_TC5IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD12);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD11 */
-
-#if SPC5_ICU_USE_SMOD12
-#if !defined(SPC5_ETIMER2_TC0IR_HANDLER)
-#error "SPC5_ETIMER2_TC0IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer2 Channel 0 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC0IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD13);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD12 */
-
-#if SPC5_ICU_USE_SMOD13
-#if !defined(SPC5_ETIMER2_TC1IR_HANDLER)
-#error "SPC5_ETIMER2_TC1IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer2 Channel 1 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC1IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD14);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD13 */
-
-#if SPC5_ICU_USE_SMOD14
-#if !defined(SPC5_ETIMER2_TC2IR_HANDLER)
-#error "SPC5_ETIMER2_TC2IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer2 Channel 2 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC2IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD15);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD14 */
-
-#if SPC5_ICU_USE_SMOD15
-#if !defined(SPC5_ETIMER2_TC3IR_HANDLER)
-#error "SPC5_ETIMER2_TC3IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer2 Channel 3 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC3IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD16);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD15 */
-
-#if SPC5_ICU_USE_SMOD16
-#if !defined(SPC5_ETIMER2_TC4IR_HANDLER)
-#error "SPC5_ETIMER2_TC4IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer2 Channel 4 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC4IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD17);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD16 */
-
-#if SPC5_ICU_USE_SMOD17
-#if !defined(SPC5_ETIMER2_TC5IR_HANDLER)
-#error "SPC5_ETIMER2_TC5IR_HANDLER not defined"
-#endif
-/**
- * @brief   eTimer2 Channel 5 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_ETIMER2_TC5IR_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD18);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_SMOD17 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
-  /* Submodules initially all not in use.*/
-  icu_active_submodules0 = 0;
-  icu_active_submodules1 = 0;
-  icu_active_submodules2 = 0;
-
-  /* Reset width and period registers.*/
-  width = 0;
-  period = 0;
-
-#if SPC5_ICU_USE_SMOD0
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD1);
-  ICUD1.etimerp = &SPC5_ETIMER_0;
-  ICUD1.smod_number = 0U;
-  ICUD1.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD1
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD2);
-  ICUD2.etimerp = &SPC5_ETIMER_0;
-  ICUD2.smod_number = 1U;
-  ICUD2.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD2
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD3);
-  ICUD3.etimerp = &SPC5_ETIMER_0;
-  ICUD3.smod_number = 2U;
-  ICUD3.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD3
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD4);
-  ICUD4.etimerp = &SPC5_ETIMER_0;
-  ICUD4.smod_number = 3U;
-  ICUD4.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD4
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD5);
-  ICUD5.etimerp = &SPC5_ETIMER_0;
-  ICUD5.smod_number = 4U;
-  ICUD5.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD5
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD6);
-  ICUD6.etimerp = &SPC5_ETIMER_0;
-  ICUD6.smod_number = 5U;
-  ICUD6.clock = SPC5_ETIMER0_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD6
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD7);
-  ICUD7.etimerp = &SPC5_ETIMER_1;
-  ICUD7.smod_number = 0U;
-  ICUD7.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD7
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD8);
-  ICUD8.etimerp = &SPC5_ETIMER_1;
-  ICUD8.smod_number = 1U;
-  ICUD8.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD8
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD9);
-  ICUD9.etimerp = &SPC5_ETIMER_1;
-  ICUD9.smod_number = 2U;
-  ICUD9.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD9
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD10);
-  ICUD10.etimerp = &SPC5_ETIMER_1;
-  ICUD10.smod_number = 3U;
-  ICUD10.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD10
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD11);
-  ICUD11.etimerp = &SPC5_ETIMER_1;
-  ICUD11.smod_number = 4U;
-  ICUD11.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD11
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD12);
-  ICUD12.etimerp = &SPC5_ETIMER_1;
-  ICUD12.smod_number = 5U;
-  ICUD12.clock = SPC5_ETIMER1_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD12
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD13);
-  ICUD13.etimerp = &SPC5_ETIMER_2;
-  ICUD13.smod_number = 0U;
-  ICUD13.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD13
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD14);
-  ICUD14.etimerp = &SPC5_ETIMER_2;
-  ICUD14.smod_number = 1U;
-  ICUD14.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD14
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD15);
-  ICUD15.etimerp = &SPC5_ETIMER_2;
-  ICUD15.smod_number = 2U;
-  ICUD15.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD15
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD16);
-  ICUD16.etimerp = &SPC5_ETIMER_2;
-  ICUD16.smod_number = 3U;
-  ICUD16.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD16
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD17);
-  ICUD17.etimerp = &SPC5_ETIMER_2;
-  ICUD17.smod_number = 4U;
-  ICUD17.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_SMOD17
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD18);
-  ICUD18.etimerp = &SPC5_ETIMER_2;
-  ICUD18.smod_number = 5U;
-  ICUD18.clock = SPC5_ETIMER2_CLK;
-#endif
-
-#if SPC5_ICU_USE_ETIMER0
-
-  INTC.PSR[SPC5_ETIMER0_TC0IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
-  INTC.PSR[SPC5_ETIMER0_TC1IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
-  INTC.PSR[SPC5_ETIMER0_TC2IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
-  INTC.PSR[SPC5_ETIMER0_TC3IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
-  INTC.PSR[SPC5_ETIMER0_TC4IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
-  INTC.PSR[SPC5_ETIMER0_TC5IR_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
-  INTC.PSR[SPC5_ETIMER0_WTIF_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
-  INTC.PSR[SPC5_ETIMER0_RCF_NUMBER].R = SPC5_ICU_ETIMER0_PRIORITY;
-
-#endif
-
-#if SPC5_ICU_USE_ETIMER1
-
-  INTC.PSR[SPC5_ETIMER1_TC0IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
-  INTC.PSR[SPC5_ETIMER1_TC1IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
-  INTC.PSR[SPC5_ETIMER1_TC2IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
-  INTC.PSR[SPC5_ETIMER1_TC3IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
-  INTC.PSR[SPC5_ETIMER1_TC4IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
-  INTC.PSR[SPC5_ETIMER1_TC5IR_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
-  INTC.PSR[SPC5_ETIMER1_RCF_NUMBER].R = SPC5_ICU_ETIMER1_PRIORITY;
-
-#endif
-
-#if SPC5_ICU_USE_ETIMER2
-
-  INTC.PSR[SPC5_ETIMER2_TC0IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
-  INTC.PSR[SPC5_ETIMER2_TC1IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
-  INTC.PSR[SPC5_ETIMER2_TC2IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
-  INTC.PSR[SPC5_ETIMER2_TC3IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
-  INTC.PSR[SPC5_ETIMER2_TC4IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
-  INTC.PSR[SPC5_ETIMER2_TC5IR_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
-  INTC.PSR[SPC5_ETIMER2_RCF_NUMBER].R = SPC5_ICU_ETIMER2_PRIORITY;
-
-#endif
-}
-
-/**
- * @brief   Configures and activates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-
-  chDbgAssert(icu_active_submodules0 < 6, "icu_lld_start(), #1",
-              "too many submodules");
-  chDbgAssert(icu_active_submodules1 < 6, "icu_lld_start(), #2",
-              "too many submodules");
-  chDbgAssert(icu_active_submodules2 < 6, "icu_lld_start(), #3",
-              "too many submodules");
-
-  if (icup->state == ICU_STOP) {
-#if SPC5_ICU_USE_SMOD0
-    if (&ICUD1 == icup)
-      icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD1
-    if (&ICUD2 == icup)
-      icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD2
-    if (&ICUD3 == icup)
-      icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD3
-    if (&ICUD4 == icup)
-      icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD4
-    if (&ICUD5 == icup)
-      icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD5
-    if (&ICUD6 == icup)
-      icu_active_submodules0++;
-#endif
-#if SPC5_ICU_USE_SMOD6
-    if (&ICUD7 == icup)
-      icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD7
-    if (&ICUD8 == icup)
-      icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD8
-    if (&ICUD9 == icup)
-      icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD9
-    if (&ICUD10 == icup)
-      icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD10
-    if (&ICUD11 == icup)
-      icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD11
-    if (&ICUD12 == icup)
-      icu_active_submodules1++;
-#endif
-#if SPC5_ICU_USE_SMOD12
-    if (&ICUD13 == icup)
-      icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD13
-    if (&ICUD14 == icup)
-      icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD14
-    if (&ICUD15 == icup)
-      icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD15
-    if (&ICUD16 == icup)
-      icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD16
-    if (&ICUD17 == icup)
-      icu_active_submodules2++;
-#endif
-#if SPC5_ICU_USE_SMOD17
-    if (&ICUD18 == icup)
-      icu_active_submodules2++;
-#endif
-
-    /* Set eTimer0 Clock.*/
-#if SPC5_ICU_USE_ETIMER0
-
-    /* If this is the first Submodule activated then the eTimer0 is enabled.*/
-    if (icu_active_submodules0 == 1) {
-      halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL,
-                                   SPC5_ICU_ETIMER0_START_PCTL);
-    }
-#endif
-
-    /* Set eTimer1 Clock.*/
-#if SPC5_ICU_USE_ETIMER1
-    /* If this is the first Submodule activated then the eTimer1 is enabled.*/
-    if (icu_active_submodules1 == 1) {
-      halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL,
-                                   SPC5_ICU_ETIMER1_START_PCTL);
-    }
-#endif
-
-    /* Set eTimer2 Clock.*/
-#if SPC5_ICU_USE_ETIMER2
-    /* If this is the first Submodule activated then the eTimer2 is enabled.*/
-    if (icu_active_submodules2 == 1) {
-      halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL,
-                                   SPC5_ICU_ETIMER2_START_PCTL);
-    }
-#endif
-
-    /* Timer disabled.*/
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
-        SPC5_ETIMER_CNTMODE_NO_OPERATION;
-
-    /* Clear pending IRQs (if any).*/
-    icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF;
-
-    /* All IRQs and DMA requests disabled.*/
-    icup->etimerp->CHANNEL[icup->smod_number].INTDMA.R = 0U;
-
-    /* Compare Load 1 and Compare Load 2 disabled.*/
-    icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC1 = 0U;
-    icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC2 = 0U;
-
-    /* Capture 1 and Capture 2 disabled.*/
-    icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
-        SPC5_ETIMER_CPT1MODE_DISABLED;
-    icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
-        SPC5_ETIMER_CPT2MODE_DISABLED;
-
-    /* Counter reset to zero.*/
-    icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0U;
-  }
-
-  /* Configuration.*/
-  spc5_icu_smod_init(icup);
-}
-
-/**
- * @brief   Deactivates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
-  chDbgAssert(icu_active_submodules0 < 6, "icu_lld_stop(), #1",
-              "too many submodules");
-  chDbgAssert(icu_active_submodules1 < 6, "icu_lld_stop(), #2",
-              "too many submodules");
-  chDbgAssert(icu_active_submodules2 < 6, "icu_lld_stop(), #3",
-              "too many submodules");
-
-  if (icup->state == ICU_READY) {
-
-#if SPC5_ICU_USE_SMOD0
-    if (&ICUD1 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xFE;
-      icu_active_submodules0--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD1
-    if (&ICUD2 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xFD;
-      icu_active_submodules0--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD2
-    if (&ICUD3 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xFB;
-      icu_active_submodules0--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD3
-    if (&ICUD4 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xF7;
-      icu_active_submodules0--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD4
-    if (&ICUD5 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xEF;
-      icu_active_submodules0--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD5
-    if (&ICUD6 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xDF;
-      icu_active_submodules0--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD6
-    if (&ICUD7 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xFE;
-      icu_active_submodules1--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD7
-    if (&ICUD8 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xFD;
-      icu_active_submodules1--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD8
-    if (&ICUD9 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xFB;
-      icu_active_submodules1--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD9
-    if (&ICUD10 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xF7;
-      icu_active_submodules1--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD10
-    if (&ICUD11 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xEF;
-      icu_active_submodules1--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD11
-    if (&ICUD12 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xDF;
-      icu_active_submodules1--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD12
-    if (&ICUD13 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xFE;
-      icu_active_submodules2--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD13
-    if (&ICUD14 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xFD;
-      icu_active_submodules2--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD14
-    if (&ICUD15 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xFB;
-      icu_active_submodules2--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD15
-    if (&ICUD16 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xF7;
-      icu_active_submodules2--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD16
-    if (&ICUD17 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xEF;
-      icu_active_submodules2--;
-    }
-#endif
-#if SPC5_ICU_USE_SMOD17
-    if (&ICUD18 == icup) {
-      /* Disable channel.*/
-      icup->etimerp->ENBL.B.ENBL &= 0xDF;
-      icu_active_submodules2--;
-    }
-#endif
-    /* eTimer0 clock deactivation.*/
-#if SPC5_ICU_USE_ETIMER0
-    /* If it is the last active submodules then the eTimer0 is disabled.*/
-    if (icu_active_submodules0 == 0) {
-      if (icup->etimerp->ENBL.B.ENBL == 0) {
-        halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL,
-                                     SPC5_ICU_ETIMER0_STOP_PCTL);
-      }
-    }
-#endif
-
-    /* eTimer1 clock deactivation.*/
-#if SPC5_ICU_USE_ETIMER1
-    /* If it is the last active submodules then the eTimer1 is disabled.*/
-    if (icu_active_submodules1 == 0) {
-      if (icup->etimerp->ENBL.B.ENBL == 0) {
-        halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL,
-                                     SPC5_ICU_ETIMER1_STOP_PCTL);
-      }
-    }
-#endif
-
-    /* eTimer2 clock deactivation.*/
-#if SPC5_ICU_USE_ETIMER2
-    /* If it is the last active submodules then the eTimer2 is disabled.*/
-    if (icu_active_submodules2 == 0) {
-      if (icup->etimerp->ENBL.B.ENBL == 0) {
-        halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL,
-                                     SPC5_ICU_ETIMER2_STOP_PCTL);
-      }
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Enables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
-  /* Clear pending IRQs (if any).*/
-  icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF;
-
-  /* Set Capture 1 and Capture 2 Mode.*/
-  icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
-      SPC5_ETIMER_CPT1MODE_RISING_EDGE;
-  icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.ROC =
-      SPC5_ETIMER_ROC_REL_ON_CAP1;
-  icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
-      SPC5_ETIMER_CPT2MODE_FALLING_EDGE;
-
-  /* Active interrupts.*/
-  if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) {
-    icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF1IE = 1U;
-    icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF2IE = 1U;
-  }
-  if (icup->config->overflow_cb != NULL) {
-    icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.TOFIE = 1U;
-  }
-
-  /* Set Capture FIFO Water Mark.*/
-  icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CFWM = 0U;
-
-  /* Enable Counter.*/
-  if (ICU_SKIP_FIRST_CAPTURE) {
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
-        SPC5_ETIMER_CNTMODE_RFE_SIHA;
-  }
-  else {
-    icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE =
-        SPC5_ETIMER_CNTMODE_RE;
-  }
-
-  /* Enable Capture process.*/
-  icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.ARM = 1U;
-}
-
-/**
- * @brief   Disables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
-  /* Disable Capture process.*/
-  icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.ARM = 0U;
-
-  /* Clear pending IRQs (if any).*/
-  icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF;
-
-  /* Set Capture 1 and Capture 2 Mode to Disabled.*/
-  icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
-      SPC5_ETIMER_CPT1MODE_DISABLED;
-  icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
-      SPC5_ETIMER_CPT2MODE_DISABLED;
-
-  /* Disable interrupts.*/
-  if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) {
-    icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF1IE = 0U;
-    icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.ICF2IE = 0U;
-  }
-  if (icup->config->overflow_cb != NULL)
-    icup->etimerp->CHANNEL[icup->smod_number].INTDMA.B.TOFIE = 0U;
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
deleted file mode 100644
index f95f5356f..000000000
--- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
+++ /dev/null
@@ -1,612 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    eTimer_v1/icu_lld.h
- * @brief   SPC5xx low level ICU driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-#include "spc5_etimer.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Mode options
- * @{
- */
-
-/**
- * @brief   Skip first capture cycle.
- * @details If set to @p TRUE the first capture cycle is skipped.
- * @note    The default is @p FALSE.
- */
-#if !defined(ICU_JUMP_FIRST_CAPTURE) || defined(__DOXYGEN__)
-#define ICU_SKIP_FIRST_CAPTURE                      FALSE
-#endif
-
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1        0x18
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2        0x19
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4        0x1A
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_8        0x1B
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_16       0x1C
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_32       0x1D
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_64       0x1E
-#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_128      0x1F
-
-#define SPC5_ETIMER_COUNTER_0_INPUT_PIN             0U
-#define SPC5_ETIMER_COUNTER_1_INPUT_PIN             1U
-#define SPC5_ETIMER_COUNTER_2_INPUT_PIN             2U
-#define SPC5_ETIMER_COUNTER_3_INPUT_PIN             3U
-#define SPC5_ETIMER_COUNTER_4_INPUT_PIN             4U
-#define SPC5_ETIMER_COUNTER_5_INPUT_PIN             5U
-
-#define SPC5_ETIMER_CNTMODE_NO_OPERATION            0U
-#define SPC5_ETIMER_CNTMODE_RE                      1U
-#define SPC5_ETIMER_CNTMODE_RFE                     2U
-#define SPC5_ETIMER_CNTMODE_RFE_SIHA                3U
-#define SPC5_ETIMER_CNTMODE_QUADRATURE              4U
-#define SPC5_ETIMER_CNTMODE_RE_SSSD                 5U
-#define SPC5_ETIMER_CNTMODE_ESS_TRIGGER             6U
-#define SPC5_ETIMER_CNTMODE_CASCADE                 7U
-
-#define SPC5_ETIMER_CPT1MODE_DISABLED               0U
-#define SPC5_ETIMER_CPT1MODE_FALLING_EDGE           1U
-#define SPC5_ETIMER_CPT1MODE_RISING_EDGE            2U
-#define SPC5_ETIMER_CPT1MODE_ANY_EDGE               3U
-
-#define SPC5_ETIMER_CPT2MODE_DISABLED               0U
-#define SPC5_ETIMER_CPT2MODE_FALLING_EDGE           1U
-#define SPC5_ETIMER_CPT2MODE_RISING_EDGE            2U
-#define SPC5_ETIMER_CPT2MODE_ANY_EDGE               3U
-
-#define SPC5_ETIMER_ROC_DO_NOT_RELOAD               0U
-#define SPC5_ETIMER_ROC_REL_ON_CAP1                 1U
-#define SPC5_ETIMER_ROC_REL_ON_CAP2                 2U
-#define SPC5_ETIMER_ROC_REL_ON_CAP1_CAP2            3U
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ICUD1 driver enable switch.
- * @details If set to @p TRUE the support for ICUD1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD0) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD0                  FALSE
-#endif
-
-/**
- * @brief   ICUD2 driver enable switch.
- * @details If set to @p TRUE the support for ICUD2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD1) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD1                  FALSE
-#endif
-
-/**
- * @brief   ICUD3 driver enable switch.
- * @details If set to @p TRUE the support for ICUD3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD2) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD2                  FALSE
-#endif
-
-/**
- * @brief   ICUD4 driver enable switch.
- * @details If set to @p TRUE the support for ICUD4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD3) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD3                  FALSE
-#endif
-
-/**
- * @brief   ICUD5 driver enable switch.
- * @details If set to @p TRUE the support for ICUD5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD4) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD4                  FALSE
-#endif
-
-/**
- * @brief   ICUD6 driver enable switch.
- * @details If set to @p TRUE the support for ICUD6 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD5) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD5                  FALSE
-#endif
-
-/**
- * @brief   eTimer0 interrupt priority level setting.
- */
-#if !defined(SPC5_ICU_ETIMER0_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER0_PRIORITY           7
-#endif
-
-/**
- * @brief   eTIMER0 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER0_START_PCTL         (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   eTIMER0 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER0_STOP_PCTL          (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   ICUD6 driver enable switch.
- * @details If set to @p TRUE the support for ICUD6 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD6) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD6                  FALSE
-#endif
-
-/**
- * @brief   ICUD7 driver enable switch.
- * @details If set to @p TRUE the support for ICUD7 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD7) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD7                  FALSE
-#endif
-
-/**
- * @brief   ICUD8 driver enable switch.
- * @details If set to @p TRUE the support for ICUD8 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD8) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD8                  FALSE
-#endif
-
-/**
- * @brief   ICUD9 driver enable switch.
- * @details If set to @p TRUE the support for ICUD9 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD9) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD9                  FALSE
-#endif
-
-/**
- * @brief   ICUD10 driver enable switch.
- * @details If set to @p TRUE the support for ICUD10 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD10) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD10                 FALSE
-#endif
-
-/**
- * @brief   ICUD11 driver enable switch.
- * @details If set to @p TRUE the support for ICUD11 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD11) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD11                 FALSE
-#endif
-
-/**
- * @brief   eTimer1 interrupt priority level setting.
- */
-#if !defined(SPC5_ICU_ETIMER1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER1_PRIORITY           7
-#endif
-
-/**
- * @brief   eTIMER1 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER1_START_PCTL         (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   eTIMER1 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER1_STOP_PCTL          (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief   ICUD13 driver enable switch.
- * @details If set to @p TRUE the support for ICUD13 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD12) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD12                 FALSE
-#endif
-
-/**
- * @brief   ICUD14 driver enable switch.
- * @details If set to @p TRUE the support for ICUD14 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD13) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD13                 FALSE
-#endif
-
-/**
- * @brief   ICUD15 driver enable switch.
- * @details If set to @p TRUE the support for ICUD15 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD14) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD14                 FALSE
-#endif
-
-/**
- * @brief   ICUD16 driver enable switch.
- * @details If set to @p TRUE the support for ICUD16 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD15) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD15                 FALSE
-#endif
-
-/**
- * @brief   ICUD17 driver enable switch.
- * @details If set to @p TRUE the support for ICUD17 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD16) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD16                 FALSE
-#endif
-
-/**
- * @brief   ICUD18 driver enable switch.
- * @details If set to @p TRUE the support for ICUD18 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_SMOD17) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_SMOD17                 FALSE
-#endif
-
-/**
- * @brief   eTimer2 interrupt priority level setting.
- */
-#if !defined(SPC5_ICU_ETIMER2_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER2_PRIORITY           7
-#endif
-
-/**
- * @brief   eTIMER2 peripheral configuration when started.
- * @note    The default configuration is 1 (always run) in run mode and
- *          2 (only halt) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER2_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER2_START_PCTL         (SPC5_ME_PCTL_RUN(1) |          \
-                                             SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief   eTIMER2 peripheral configuration when stopped.
- * @note    The default configuration is 0 (never run) in run mode and
- *          0 (never run) in low power mode. The defaults of the run modes
- *          are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_ICU_ETIMER2_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_ICU_ETIMER2_STOP_PCTL          (SPC5_ME_PCTL_RUN(0) |          \
-                                             SPC5_ME_PCTL_LP(0))
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#define SPC5_ICU_USE_ETIMER0                (SPC5_ICU_USE_SMOD0 ||          \
-                                             SPC5_ICU_USE_SMOD1 ||          \
-                                             SPC5_ICU_USE_SMOD2 ||          \
-                                             SPC5_ICU_USE_SMOD3 ||          \
-                                             SPC5_ICU_USE_SMOD4 ||          \
-                                             SPC5_ICU_USE_SMOD5)
-
-#define SPC5_ICU_USE_ETIMER1                (SPC5_ICU_USE_SMOD6 ||          \
-                                             SPC5_ICU_USE_SMOD7 ||          \
-                                             SPC5_ICU_USE_SMOD8 ||          \
-                                             SPC5_ICU_USE_SMOD9 ||          \
-                                             SPC5_ICU_USE_SMOD10 ||         \
-                                             SPC5_ICU_USE_SMOD11)
-
-#define SPC5_ICU_USE_ETIMER2                (SPC5_ICU_USE_SMOD12 ||         \
-                                             SPC5_ICU_USE_SMOD13 ||         \
-                                             SPC5_ICU_USE_SMOD14 ||         \
-                                             SPC5_ICU_USE_SMOD15 ||         \
-                                             SPC5_ICU_USE_SMOD16 ||         \
-                                             SPC5_ICU_USE_SMOD17)
-
-#if !SPC5_HAS_ETIMER0 && SPC5_ICU_USE_ETIMER0
-#error "ETIMER0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_ETIMER1 && SPC5_ICU_USE_ETIMER1
-#error "ETIMER1 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_ETIMER2 && SPC5_ICU_USE_ETIMER2
-#error "ETIMER2 not present in the selected device"
-#endif
-
-#if !SPC5_ICU_USE_ETIMER0 && !SPC5_ICU_USE_ETIMER1 && !SPC5_ICU_USE_ETIMER2
-#error "ICU driver activated but no SMOD peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief ICU driver mode.
- */
-typedef enum {
-  ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge.            */
-  ICU_INPUT_ACTIVE_LOW = 1,  /**< Trigger on falling edge.           */
-} icumode_t;
-
-/**
- * @brief   ICU frequency type.
- */
-typedef uint32_t icufreq_t;
-
-/**
- * @brief   ICU channel.
- */
-typedef enum {
-  ICU_CHANNEL_1 = 0, /**< Use SMODxCH1.      */
-  ICU_CHANNEL_2 = 1, /**< Use SMODxCH2.      */
-  ICU_CHANNEL_3 = 2, /**< Use SMODxCH3.      */
-  ICU_CHANNEL_4 = 3, /**< Use SMODxCH4.      */
-  ICU_CHANNEL_5 = 4, /**< Use SMODxCH5.      */
-  ICU_CHANNEL_6 = 5, /**< Use SMODxCH6.      */
-} icuchannel_t;
-
-/**
- * @brief   ICU counter type.
- */
-typedef uint16_t icucnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Driver mode.
-   */
-  icumode_t mode;
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  icufreq_t frequency;
-  /**
-   * @brief   Callback for pulse width measurement.
-   */
-  icucallback_t width_cb;
-  /**
-   * @brief   Callback for cycle period measurement.
-   */
-  icucallback_t period_cb;
-  /**
-   * @brief   Callback for timer overflow.
-   */
-  icucallback_t overflow_cb;
-  /* End of the mandatory fields.*/
-} ICUConfig;
-
-/**
- * @brief   Structure representing an ICU driver.
- */
-struct ICUDriver {
-  /**
-   * @brief Driver state.
-   */
-  icustate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ICUConfig           *config;
-#if defined(ICU_DRIVER_EXT_FIELDS)
-  ICU_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Clock value for this unit.
-   */
-  uint32_t                  clock;
-  /**
-   * @brief eTimer submodule number.
-   */
-  uint32_t                  smod_number;
-  /**
-   * @brief Pointer to the eTimerx registers block.
-   */
-  volatile struct spc5_etimer *etimerp;
-  /**
-   * @brief CCR register used for width capture.
-   */
-  volatile vuint16_t        *wccrp;
-  /**
-   * @brief CCR register used for period capture.
-   */
-  volatile vuint16_t        *pccrp;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- *          edge and the stop edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
-
-/**
- * @brief   Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- *          edge and the next start edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_SMOD0 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-
-#if SPC5_ICU_USE_SMOD1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD2;
-#endif
-
-#if SPC5_ICU_USE_SMOD2 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD3;
-#endif
-
-#if SPC5_ICU_USE_SMOD3 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD4;
-#endif
-
-#if SPC5_ICU_USE_SMOD4 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD5;
-#endif
-
-#if SPC5_ICU_USE_SMOD5 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD6;
-#endif
-
-#if SPC5_ICU_USE_SMOD6 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD7;
-#endif
-
-#if SPC5_ICU_USE_SMOD7 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD8;
-#endif
-
-#if SPC5_ICU_USE_SMOD8 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD9;
-#endif
-
-#if SPC5_ICU_USE_SMOD9 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD10;
-#endif
-
-#if SPC5_ICU_USE_SMOD10 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD11;
-#endif
-
-#if SPC5_ICU_USE_SMOD11 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD12;
-#endif
-
-#if SPC5_ICU_USE_SMOD12 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD13;
-#endif
-
-#if SPC5_ICU_USE_SMOD13 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD14;
-#endif
-
-#if SPC5_ICU_USE_SMOD14 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD15;
-#endif
-
-#if SPC5_ICU_USE_SMOD15 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD16;
-#endif
-
-#if SPC5_ICU_USE_SMOD16 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD17;
-#endif
-
-#if SPC5_ICU_USE_SMOD17 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD18;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void icu_lld_init(void);
-  void icu_lld_start(ICUDriver *icup);
-  void icu_lld_stop(ICUDriver *icup);
-  void icu_lld_enable(ICUDriver *icup);
-  void icu_lld_disable(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h b/os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h
deleted file mode 100644
index 1ab9e8fad..000000000
--- a/os/hal/platforms/SPC5xx/eTimer_v1/spc5_etimer.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
-    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    eTimer_v1/etimer.h
- * @brief   SPC5xx eTimer header file.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ETIMER_H_
-#define _ETIMER_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPC5 FlexPWM registers block.
- * @note    Redefined from the SPC5 headers because the non uniform
- *          declaration of the SubModules registers among the various
- *          sub-families.
- */
-struct spc5_etimer_submodule {
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t COMP1 :16;
-    } B;
-  } COMP1; /* Compare Register 1 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t COMP2 :16;
-    } B;
-  } COMP2; /* Compare Register 2 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CAPT1 :16;
-    } B;
-  } CAPT1; /* Capture Register 1 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CAPT2 :16;
-    } B;
-  } CAPT2; /* Capture Register 2 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t LOAD :16;
-    } B;
-  } LOAD; /* Load Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t HOLD :16;
-    } B;
-  } HOLD; /* Hold Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CNTR :16;
-    } B;
-  } CNTR; /* Counter Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CNTMODE :3;
-      vuint16_t PRISRC :5;
-      vuint16_t ONCE :1;
-      vuint16_t LENGTH :1;
-      vuint16_t DIR :1;
-      vuint16_t SECSRC :5;
-    } B;
-  } CTRL; /* Control Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t OEN :1;
-      vuint16_t RDNT :1;
-      vuint16_t INPUT :1;
-      vuint16_t VAL :1;
-      vuint16_t FORCE :1;
-      vuint16_t COFRC :1;
-      vuint16_t COINIT :2;
-      vuint16_t SIPS :1;
-      vuint16_t PIPS :1;
-      vuint16_t OPS :1;
-      vuint16_t MSTR :1;
-      vuint16_t OUTMODE :4;
-    } B;
-  } CTRL2; /* Control Register 2 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t STPEN :1;
-      vuint16_t ROC :2;
-      vuint16_t FMODE :1;
-      vuint16_t FDIS :4;
-      vuint16_t C2FCNT :3;
-      vuint16_t C1FCNT :3;
-      vuint16_t DBGEN :2;
-    } B;
-  } CTRL3; /* Control Register 3 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :6;
-      vuint16_t WDF :1;
-      vuint16_t RCF :1;
-      vuint16_t ICF2 :1;
-      vuint16_t ICF1 :1;
-      vuint16_t IEHF :1;
-      vuint16_t IELF :1;
-      vuint16_t TOF :1;
-      vuint16_t TCF2 :1;
-      vuint16_t TCF1 :1;
-      vuint16_t TCF :1;
-    } B;
-  } STS; /* Status Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t ICF2DE :1;
-      vuint16_t ICF1DE :1;
-      vuint16_t CMPLD2DE :1;
-      vuint16_t CMPLD1DE :1;
-      vuint16_t :2;
-      vuint16_t WDFIE :1;
-      vuint16_t RCFIE :1;
-      vuint16_t ICF2IE :1;
-      vuint16_t ICF1IE :1;
-      vuint16_t IEHFIE :1;
-      vuint16_t IELFIE :1;
-      vuint16_t TOFIE :1;
-      vuint16_t TCF2IE :1;
-      vuint16_t TCF1IE :1;
-      vuint16_t TCFIE :1;
-    } B;
-  } INTDMA; /* Interrupt and DMA Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CMPLD1 :16;
-    } B;
-  } CMPLD1; /* Compare Load Register 1 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CMPLD2 :16;
-    } B;
-  } CMPLD2; /* Compare Load Register 2 */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t CLC2 :3;
-      vuint16_t CLC1 :3;
-      vuint16_t CMPMODE :2;
-      vuint16_t CPT2MODE :2;
-      vuint16_t CPT1MODE :2;
-      vuint16_t CFWM :2;
-      vuint16_t ONESHOT :1;
-      vuint16_t ARM :1;
-    } B;
-  } CCCTRL; /* Compare and Capture Control Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :5;
-      vuint16_t FILTCNT :3;
-      vuint16_t FILTPER :8;
-    } B;
-  } FILT; /* Input Filter Register */
-
-};
-/* end of ETIMER_CHANNEL_tag */
-
-struct spc5_etimer {
-
-  struct spc5_etimer_submodule CHANNEL[8];
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t WDTOL :16;
-    } B;
-  } WDTOL; /* Watchdog Time-out Low Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t WDTOH :16;
-    } B;
-  } WDTOH; /* Watchdog Time-out High Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :3;
-      vuint16_t FTEST :1;
-      vuint16_t FIE :4;
-      vuint16_t :4;
-      vuint16_t FLVL :4;
-    } B;
-  } FCTRL; /* Fault Control Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :4;
-      vuint16_t FFPIN :4;
-      vuint16_t :4;
-      vuint16_t FFLAG :4;
-    } B;
-  } FSTS; /* Fault Status Register */
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :5;
-      vuint16_t FFILTCNT :3;
-      vuint16_t FFILTPER :8;
-    } B;
-  } FFILT; /* Fault Filter Register */
-
-  int16_t ETIMER_reserved1;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :8;
-      vuint16_t ENBL :8;
-    } B;
-  } ENBL; /* Channel Enable Register */
-
-  int16_t ETIMER_reserved2;
-
-  union {
-    vuint16_t R;
-    struct {
-      vuint16_t :11;
-      vuint16_t DREQ :5;
-    } B;
-  } DREQ[4]; /* DMA Request 0->3 Select Register */
-
-};
-/* end of ETIMER_tag */
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    eTimer units references
- * @{
- */
-#if SPC5_HAS_ETIMER0
-#define SPC5_ETIMER_0      (*(volatile struct spc5_etimer *)0xFFE18000UL)
-#endif
-
-#if SPC5_HAS_ETIMER1
-#define SPC5_ETIMER_1      (*(volatile struct spc5_etimer *)0xFFE1C000UL)
-#endif
-
-#if SPC5_HAS_ETIMER2
-#define SPC5_ETIMER_2      (*(volatile struct spc5_etimer *)0xFFE20000UL)
-#endif
-/** @} */
-
-#endif /* _FLEXPWM_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/DACv1/dac_lld.c b/os/hal/platforms/STM32/DACv1/dac_lld.c
deleted file mode 100644
index d5ff63da2..000000000
--- a/os/hal/platforms/STM32/DACv1/dac_lld.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    STM32F37x/dac_lld.c
- * @brief   STM32F37x DAC subsystem low level driver source.
- *
- * @addtogroup DAC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#if !defined(DAC1)
-#define DAC1 DAC
-#define rccEnableDAC1 rccEnableDAC
-#define rccDisableDAC1 rccDisableDAC
-#endif
-
-#define DAC_CHN1_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_DAC_CHN1_DMA_STREAM,                            \
-                       STM32_DAC_CHN1_DMA_CHN)
-
-#define DAC_CHN2_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_DAC_CHN2_DMA_STREAM,                            \
-                       STM32_DAC_CHN2_DMA_CHN)
-           
-#define DAC_CHN3_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_DAC_CHN3_DMA_STREAM,                            \
-                       STM32_DAC_CHN3_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief CHN1 driver identifier.*/
-#if STM32_DAC_USE_CHN1 || defined(__DOXYGEN__)
-DACDriver DACD1;
-#endif
-
-/** @brief CHN2 driver identifier.*/
-#if STM32_DAC_USE_CHN2 || defined(__DOXYGEN__)
-DACDriver DACD2;
-#endif
-
-/** @brief CHN3 driver identifier.*/
-#if STM32_DAC_USE_CHN3 || defined(__DOXYGEN__)
-DACDriver DACD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-
-/**
- * @brief   Shared end/half-of-tx service routine.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
-#if defined(STM32_DAC_DMA_ERROR_HOOK)
-  (void)dacp;
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    /* DMA errors handling.*/
-    _dac_isr_error_code(dacp);
-  }
-  else {
-    if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-      /* Half transfer processing.*/
-      _dac_isr_half_code(dacp);
-    }
-    if ((flags & STM32_DMA_ISR_TCIF) != 0) {
-      /* Transfer complete processing.*/
-      _dac_isr_full_code(dacp);
-    }
-  }
-#else
-  (void)dacp;
-  (void)flags;
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level DAC driver initialization.
- *
- * @notapi
- */
-void dac_lld_init(void) {
-
-#if STM32_DAC_USE_CHN1
-  dacObjectInit(&DACD1);
-  DACD1.dac     = DAC1;
-  DACD1.tim     = STM32_TIM6;
-  DACD1.irqprio = STM32_DAC_CHN1_IRQ_PRIORITY;
-  DACD1.dma     = STM32_DMA_STREAM(STM32_DAC_CHN1_DMA_STREAM);
-  DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN1_DMA_CHANNEL) |                  \
-                  STM32_DMA_CR_PL(STM32_DAC_CHN1_DMA_PRIORITY) |              \
-                  STM32_DMA_CR_DIR_M2P |                                      \
-                  STM32_DMA_CR_DMEIE |                                        \
-                  STM32_DMA_CR_TEIE |                                         \
-                  STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
-#endif
-
-#if STM32_DAC_USE_CHN2
-  dacObjectInit(&DACD2);
-  DACD2.dac     = DAC1;
-  DACD2.tim     = STM32_TIM7;
-  DACD2.irqprio = STM32_DAC_CHN2_IRQ_PRIORITY;
-  DACD2.dma     = STM32_DMA_STREAM(STM32_DAC_CHN2_DMA_STREAM);
-  DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN2_DMA_CHANNEL) |                  \
-                  STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) |              \
-                  STM32_DMA_CR_DIR_M2P |                                      \
-                  STM32_DMA_CR_DMEIE |                                        \
-                  STM32_DMA_CR_TEIE |                                         \
-                  STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
-#endif
-
-#if STM32_DAC_USE_CHN3
-  dacObjectInit(&DACD3);
-  DACD3.dac     = DAC2;
-  DACD3.tim     = STM32_TIM18;
-  DACD3.irqprio = STM32_DAC_CHN3_IRQ_PRIORITY;
-  DACD3.dma     = STM32_DMA_STREAM(STM32_DAC_CHN3_DMA_STREAM);
-  DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN3_DMA_CHANNEL) |                  \
-                  STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) |              \
-                  STM32_DMA_CR_DIR_M2P |                                      \
-                  STM32_DMA_CR_DMEIE |                                        \
-                  STM32_DMA_CR_TEIE |                                         \
-                  STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
-#endif
-}
-
-/**
- * @brief   Configures and activates the DAC peripheral.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_start(DACDriver *dacp) {
-  uint32_t arr, regshift, trgo, dataoffset;
-  bool_t b;
-  /* If in stopped state then enables the DAC and DMA clocks.*/
-  if (dacp->state == DAC_STOP) {
-#if STM32_DAC_USE_CHN1
-    if (&DACD1 == dacp) {
-      rccEnableDAC1(FALSE);
-      /* DAC1 CR data is at bits 0:15 */
-      regshift = 0;
-      dataoffset = 0;
-      /* Timer setup */
-      rccEnableTIM6(FALSE);
-      rccResetTIM6();
-      trgo = STM32_DAC_CR_TSEL_TIM6;
-    }
-#endif
-#if STM32_DAC_USE_CHN2
-    if (&DACD2 == dacp) {
-      rccEnableDAC1(FALSE);
-      /* DAC2 CR data is at bits 16:31 */
-      regshift = 16;
-      dataoffset = &dacp->dac->DHR12R2 - &dacp->dac->DHR12R1;
-      /* Timer setup */
-      rccEnableTIM7(FALSE);
-      rccResetTIM7();
-      trgo = STM32_DAC_CR_TSEL_TIM7;
-    }
-#endif
-#if STM32_DAC_USE_CHN3
-    if (&DACD3 == dacp) {
-      rccEnableDAC2(FALSE);
-      /* DAC3 CR data is at bits 0:15 */
-      regshift = 0;
-      dataoffset = 0;
-      /* Timer setup */
-      rccEnableTIM18(FALSE);
-      rccResetTIM18();
-      trgo = STM32_DAC_CR_TSEL_TIM18;
-    }
-#endif
-#if STM32_DAC_USE_CHN1 || STM32_DAC_USE_CHN2 || STM32_DAC_USE_CHN3
-    dacp->clock = STM32_TIMCLK1;
-    arr = (dacp->clock / dacp->config->frequency);
-    chDbgAssert((arr <= 0xFFFF),
-        "dac_lld_start(), #1", "invalid frequency");
-
-    /* Timer configuration.*/
-    dacp->tim->CR1  = 0;                        /* Initially stopped.   */
-    dacp->tim->PSC  = 0;                        /* Prescaler value.     */
-    dacp->tim->DIER = 0;
-    dacp->tim->ARR  = arr;
-    dacp->tim->EGR  = TIM_EGR_UG;               /* Update event.        */
-    dacp->tim->CR2  &= (uint16_t)~TIM_CR2_MMS;
-    dacp->tim->CR2  |= (uint16_t)TIM_CR2_MMS_1; /* Enable TRGO updates. */
-    dacp->tim->CNT  = 0;                        /* Reset counter.       */
-    dacp->tim->SR   = 0;                        /* Clear pending IRQs.  */
-    /* Update Event IRQ enabled. */
-    /* Timer start.*/
-    dacp->tim->CR1  = TIM_CR1_CEN;
-
-    /* DAC configuration */
-    dacp->dac->CR |= ( (dacp->dac->CR & ~STM32_DAC_CR_MASK) | \
-      (STM32_DAC_CR_EN | STM32_DAC_CR_DMAEN | dacp->config->cr_flags) ) << regshift;
-      
-    /* DMA setup. */
-    b = dmaStreamAllocate(dacp->dma,
-          dacp->irqprio,
-          (stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
-          (void *)dacp);
-    chDbgAssert(!b, "dac_lld_start(), #2", "stream already allocated");
-    switch (dacp->config->dhrm) {
-      /* Sets the DAC data register */
-      case DAC_DHRM_12BIT_RIGHT:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12R1 + dataoffset);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-        break;
-      case DAC_DHRM_12BIT_LEFT:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12L1 + dataoffset);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-        break;
-      case DAC_DHRM_8BIT_RIGHT:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8R1 + dataoffset);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-        break;
-#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2
-      case DAC_DHRM_12BIT_RIGHT_DUAL:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12RD);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-        break;
-      case DAC_DHRM_12BIT_LEFT_DUAL:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12LD);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-        break;
-      case DAC_DHRM_8BIT_RIGHT_DUAL:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8RD);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-             STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-        break;
-#endif
-  }
-  
-  dacp->dac->CR |= trgo << regshift; /* Enable trigger */
-#endif
-  }
-}
-
-/**
- * @brief   Deactivates the DAC peripheral.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_stop(DACDriver *dacp) {
-
-  /* If in ready state then disables the DAC clock.*/
-  if (dacp->state == DAC_READY) {
-
-    /* DMA disable.*/
-    dmaStreamRelease(dacp->dma);
-
-#if STM32_DAC_USE_CHN1
-    if (&DACD1 == dacp) {
-      dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC1 disable.*/
-    }
-#endif
-#if STM32_DAC_USE_CHN2
-    if (&DACD2 == dacp) {
-      dacp->dac->CR &= ~STM32_DAC_CR_EN << 16; /* DAC1 disable.*/
-    }
-#endif
-#if STM32_DAC_USE_CHN3
-    if (&DACD3 == dacp) {
-      dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC2 disable.*/
-      rccDisableDAC2(FALSE); /* DAC Clock disable.*/
-    }
-#endif
-    dacp->tim->CR1 &= ~TIM_CR1_CEN; /* Disable associated timer */
-    dacp->state = DAC_STOP;
-
-    if (!(DAC1->CR & (STM32_DAC_CR_EN | STM32_DAC_CR_EN << 16))) {
-      /* DAC Clock disable only if all channels are off.*/
-      rccDisableDAC1(FALSE);
-    }
-  }
-}
-
-/**
- * @brief   Sends data over the DAC bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void dac_lld_send(DACDriver *dacp) {
-  chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #1", 
-    "First buffer is NULL pointer");
-  dmaStreamSetMemory0(dacp->dma, dacp->config->buffer1);
-  dmaStreamSetTransactionSize(dacp->dma, dacp->config->buffers_size);
-  dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN);
-}
-
-void dac_lld_send_continuous(DACDriver *dacp){
-  chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #1", 
-    "First buffer is NULL pointer");
-  dmaStreamSetMemory0(dacp->dma, dacp->config->buffer1);
-  dmaStreamSetTransactionSize(dacp->dma, dacp->config->buffers_size);
-  dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN |                \
-                   STM32_DMA_CR_CIRC);
-}
-#if defined(STM32_ADVANCED_DMA) && STM32_ADVANCED_DMA
-void dac_lld_send_doublebuffer(DACDriver *dacp) {
-  chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #1", 
-    "First buffer is NULL pointer");
-  chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #2", 
-    "Second buffer is NULL pointer");
-  dmaStreamSetMemory0(dacp->dma, dacp->config->buffer1);
-  dmaStreamSetMemory1(dacp->dma, dacp->config->buffer2);
-  dmaStreamSetTransactionSize(dacp->dma, dacp->config->buffers_size);
-  dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN |               \
-                   STM32_DMA_CR_DBM);
-}
-#else
-void dac_lld_send_doublebuffer(DACDriver *dacp) { 
-  (void)dacp;
-  chDbgAssert(0, "dac_lld_send_doublebuffer(), #1", 
-    "This DMA mode is not supported by your hardware.");
-};
-#endif
-
-#endif /* HAL_USE_DAC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/DACv1/dac_lld.h b/os/hal/platforms/STM32/DACv1/dac_lld.h
deleted file mode 100644
index ee5a56da8..000000000
--- a/os/hal/platforms/STM32/DACv1/dac_lld.h
+++ /dev/null
@@ -1,375 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    STM32F37x/dac_lld.h
- * @brief   STM32F37x DAC subsystem low level driver header.
- *
- * @addtogroup DAC
- * @{
- */
-
-#ifndef _DAC_LLD_H_
-#define _DAC_LLD_H_
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define STM32_DAC_CR_EN DAC_CR_EN1
-#define STM32_DAC_CR_DMAEN DAC_CR_DMAEN1
-#define STM32_DAC_CR_TEN DAC_CR_TEN1
-
-#define STM32_DAC_CR_MASK (uint32_t)0x00000FFE
-
-#define STM32_DAC_CR_BOFF_ENABLE    (uint32_t)0x00000000
-#define STM32_DAC_CR_BOFF_DISABLE   DAC_CR_BOFF1
-
-#define STM32_DAC_CR_TSEL_NONE     (uint32_t)0x00000000
-#define STM32_DAC_CR_TSEL_TIM2     DAC_CR_TEN1 | DAC_CR_TSEL1_2
-#define STM32_DAC_CR_TSEL_TIM4     DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_2
-#define STM32_DAC_CR_TSEL_TIM5     DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1
-#define STM32_DAC_CR_TSEL_TIM6     DAC_CR_TEN1
-#define STM32_DAC_CR_TSEL_TIM7     DAC_CR_TEN1 | DAC_CR_TSEL1_1
-#define STM32_DAC_CR_TSEL_TIM3     DAC_CR_TEN1 | DAC_CR_TSEL1_0
-#define STM32_DAC_CR_TSEL_TIM18     DAC_CR_TEN1 | DAC_CR_TSEL1_0 | DAC_CR_TSEL1_1
-#define STM32_DAC_CR_TSEL_EXT_IT9  DAC_CR_TEN1 | DAC_CR_TEN1 | DAC_CR_TSEL1_2
-#define STM32_DAC_CR_TSEL_SOFT     DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_2
-
-#define STM32_DAC_CR_WAVE_NONE      (uint32_t)0x00000000
-#define STM32_DAC_CR_WAVE_NOISE     DAC_CR_WAVE1_0
-#define STM32_DAC_CR_WAVE_TRIANGLE  DAC_CR_WAVE1_1
-
-#define STM32_DAC_MAMP_1 (uint32_t)0x00000000
-#define STM32_DAC_MAMP_3    DAC_CR_MAMP1_0
-#define STM32_DAC_MAMP_7    DAC_CR_MAMP1_1
-#define STM32_DAC_MAMP_15   DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1
-#define STM32_DAC_MAMP_31   DAC_CR_MAMP1_2
-#define STM32_DAC_MAMP_63   DAC_CR_MAMP1_0 | DAC_CR_MAMP1_2
-#define STM32_DAC_MAMP_127  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
-#define STM32_DAC_MAMP_255  DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
-#define STM32_DAC_MAMP_511  DAC_CR_MAMP1_3
-#define STM32_DAC_MAMP_1023 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_3
-#define STM32_DAC_MAMP_2047 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_3
-#define STM32_DAC_MAMP_4095 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   DAC1 driver enable switch.
- * @details If set to @p TRUE the support for DAC1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_DAC_USE_DAC1) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC1                  FALSE
-#endif
-
-/**
- * @brief   DAC2 driver enable switch.
- * @details If set to @p TRUE the support for DAC2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_DAC_USE_DAC2) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC2                  FALSE
-#endif
-
-/**
- * @brief   DAC1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC1_DMA_PRIORITY         2
-#endif
-
-/**
- * @brief   DAC2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC2_DMA_PRIORITY         2
-#endif
-
-/**
- * @brief   DAC1 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC1_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   DAC2 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC2_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   DAC1 interrupt priority level setting.uhm
- */
-#if !defined(STM32_DAC_DAC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC1_DMA_IRQ_PRIORITY     10
-#endif
-
-/**
- * @brief   DAC2 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC2_DMA_IRQ_PRIORITY     10
-#endif
-
-
-
-/**
- * @brief   DMA stream used for DAC CHN1 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_DAC_CHN1_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN1_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-#endif
-
-/**
- * @brief   DMA stream used for DAC CHN2 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_DAC_CHN2_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN2_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#endif
-
-/**
- * @brief   DMA stream used for DAC CHN3 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_DAC_CHN3_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_DAC_CHN3_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_DAC_USE_CHN1 && !STM32_HAS_DAC_CHN1
-#error "DAC CHN1 not present in the selected device"
-#endif
-
-#if STM32_DAC_USE_CHN2 && !STM32_HAS_DAC_CHN2
-#error "DAC CHN2 not present in the selected device"
-#endif
-
-#if STM32_DAC_USE_CHN3 && !STM32_HAS_DAC_CHN3
-#error "DAC CHN3 not present in the selected device"
-#endif
-
-#if !STM32_DAC_USE_CHN1  && !STM32_DAC_USE_CHN2 && !STM32_DAC_USE_CHN3
-#error "DAC driver activated but no DAC peripheral assigned"
-#endif
-
-#if STM32_DAC_USE_CHN1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN1_DMA_STREAM, STM32_DAC_CHN1_DMA_MSK)
-#error "invalid DMA stream associated to DAC CHN1"
-#endif
-
-#if STM32_DAC_USE_CHN2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN2_DMA_STREAM, STM32_DAC_CHN2_DMA_MSK)
-#error "invalid DMA stream associated to DAC CHN2"
-#endif
-
-#if STM32_DAC_USE_CHN3 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN3_DMA_STREAM, STM32_DAC_CHN3_DMA_MSK)
-#error "invalid DMA stream associated to DAC CHN3"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an DAC driver.
- */
-typedef struct DACDriver DACDriver;
-
-/**
- * @brief   DAC notification callback type.
- *
- * @param[in] dacp      pointer to the @p DACDriver object triggering the
- *                      callback
- */
-typedef void (*daccallback_t)(DACDriver *dacp);
-
-typedef enum { 
-  DAC_DHRM_12BIT_RIGHT = 0,
-  DAC_DHRM_12BIT_LEFT = 1,
-  DAC_DHRM_8BIT_RIGHT = 2,
-#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2 && !defined(__DOXYGEN__)
-  DAC_DHRM_12BIT_RIGHT_DUAL = 3,
-  DAC_DHRM_12BIT_LEFT_DUAL = 4,
-  DAC_DHRM_8BIT_RIGHT_DUAL = 5
-#endif
-} dacdhrmode_t;
-
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   DAC mode selection.
-   */
-  dacmode_t                 mode;
-  /**
-   * @brief   Timer frequency in Hz.
-   */
-  uint32_t                  frequency;
-  /**
-   * @brief   Transmission buffer 1 pointer.
-   */
-  const void                *buffer1;
-  /**
-   * @brief   Transmission buffer 2 pointer.
-   */
-  const void                *buffer2;
-  /**
-   * @brief   Transmission buffers size in number of samples.
-   */
-  size_t                    buffers_size;
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  daccallback_t             callback;
-  /**
-   * @brief Error handling callback or @p NULL.
-   */
-  daccallback_t             errcallback;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   DAC data holding register mode.
-   */
-  dacdhrmode_t               dhrm;
-  /**
-   * @brief DAC initialization data.
-   */
-  uint32_t                  cr_flags;
-} DACConfig;
-
-/**
- * @brief   Structure representing a DAC driver.
- */
-struct DACDriver {
-  /**
-   * @brief Driver state.
-   */
-  dacstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const DACConfig           *config;
-#if DAC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif /* DAC_USE_WAIT */
-#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* DAC_USE_MUTUAL_EXCLUSION */
-#if defined(DAC_DRIVER_EXT_FIELDS)
-  DAC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the DAC registers block.
-   */
-  DAC_TypeDef               *dac;
-  /**
-   * @brief Pointer to the TIMx registers block.
-   */
-  stm32_tim_t               *tim;
-  /**
-   * @brief The Timer IRQ priority.
-   */
-  uint32_t                  irqprio;
-  /**
-   * @brief Transmit DMA stream.
-   */
-  const stm32_dma_stream_t  *dma;
-  /**
-   * @brief TX DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-  /**
-   * @brief Timer base clock.
-   */
-  uint32_t                  clock;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_DAC_USE_CHN1 && !defined(__DOXYGEN__)
-extern DACDriver DACD1;
-#endif
-
-#if STM32_DAC_USE_CHN2 && !defined(__DOXYGEN__)
-extern DACDriver DACD2;
-#endif
-
-#if STM32_DAC_USE_CHN3 && !defined(__DOXYGEN__)
-extern DACDriver DACD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dac_lld_init(void);
-  void dac_lld_start(DACDriver *dacp);
-  void dac_lld_stop(DACDriver *dacp);
-  void dac_lld_send(DACDriver *dacp);
-  void dac_lld_send_continuous(DACDriver *dacp);
-  void dac_lld_send_doublebuffer(DACDriver *dacp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_DAC */
-
-#endif /* _DAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/GPIOv1/pal_lld.c b/os/hal/platforms/STM32/GPIOv1/pal_lld.c
deleted file mode 100644
index 31eec7883..000000000
--- a/os/hal/platforms/STM32/GPIOv1/pal_lld.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/GPIOv1/pal_lld.c
- * @brief   STM32F1xx GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#if STM32_HAS_GPIOG
-#define APB2_EN_MASK  (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |            \
-                       RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |            \
-                       RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN |            \
-                       RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
-#elif STM32_HAS_GPIOE
-#define APB2_EN_MASK  (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |            \
-                       RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |            \
-                       RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN)
-#else
-#define APB2_EN_MASK  (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |            \
-                       RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |            \
-                       RCC_APB2ENR_AFIOEN)
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 I/O ports configuration.
- * @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled.
- *
- * @param[in] config    the STM32 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  /*
-   * Enables the GPIO related clocks.
-   */
-  rccEnableAPB2(APB2_EN_MASK, FALSE);
-
-  /*
-   * Initial GPIO setup.
-   */
-  GPIOA->ODR = config->PAData.odr;
-  GPIOA->CRH = config->PAData.crh;
-  GPIOA->CRL = config->PAData.crl;
-  GPIOB->ODR = config->PBData.odr;
-  GPIOB->CRH = config->PBData.crh;
-  GPIOB->CRL = config->PBData.crl;
-  GPIOC->ODR = config->PCData.odr;
-  GPIOC->CRH = config->PCData.crh;
-  GPIOC->CRL = config->PCData.crl;
-  GPIOD->ODR = config->PDData.odr;
-  GPIOD->CRH = config->PDData.crh;
-  GPIOD->CRL = config->PDData.crl;
-#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
-  GPIOE->ODR = config->PEData.odr;
-  GPIOE->CRH = config->PEData.crh;
-  GPIOE->CRL = config->PEData.crl;
-#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
-  GPIOF->ODR = config->PFData.odr;
-  GPIOF->CRH = config->PFData.crh;
-  GPIOF->CRL = config->PFData.crl;
-#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
-  GPIOG->ODR = config->PGData.odr;
-  GPIOG->CRH = config->PGData.crh;
-  GPIOG->CRL = config->PGData.crl;
-#endif
-#endif
-#endif
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz.
- * @note    Writing on pads programmed as pull-up or pull-down has the side
- *          effect to modify the resistor setting because the output latched
- *          data is used for the resistor selection.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-  static const uint8_t cfgtab[] = {
-    4,          /* PAL_MODE_RESET, implemented as input.*/
-    2,          /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/
-    4,          /* PAL_MODE_INPUT */
-    8,          /* PAL_MODE_INPUT_PULLUP */
-    8,          /* PAL_MODE_INPUT_PULLDOWN */
-    0,          /* PAL_MODE_INPUT_ANALOG */
-    3,          /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/
-    7,          /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/
-    8,          /* Reserved.*/
-    8,          /* Reserved.*/
-    8,          /* Reserved.*/
-    8,          /* Reserved.*/
-    8,          /* Reserved.*/
-    8,          /* Reserved.*/
-    8,          /* Reserved.*/
-    8,          /* Reserved.*/
-    0xB,        /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/
-    0xF,        /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/
-  };
-  uint32_t mh, ml, crh, crl, cfg;
-  unsigned i;
-
-  if (mode == PAL_MODE_INPUT_PULLUP)
-    port->BSRR = mask;
-  else if (mode == PAL_MODE_INPUT_PULLDOWN)
-    port->BRR = mask;
-  cfg = cfgtab[mode];
-  mh = ml = crh = crl = 0;
-  for (i = 0; i < 8; i++) {
-    ml <<= 4;
-    mh <<= 4;
-    crl <<= 4;
-    crh <<= 4;
-    if ((mask & 0x0080) == 0)
-      ml |= 0xf;
-    else
-      crl |= cfg;
-    if ((mask & 0x8000) == 0)
-      mh |= 0xf;
-    else
-      crh |= cfg;
-    mask <<= 1;
-  }
-  port->CRH = (port->CRH & mh) | crh;
-  port->CRL = (port->CRL & ml) | crl;
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/os/hal/platforms/STM32/GPIOv2/pal_lld.c
deleted file mode 100644
index 32b5a89a9..000000000
--- a/os/hal/platforms/STM32/GPIOv2/pal_lld.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/GPIOv2/pal_lld.c
- * @brief   STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#if defined(STM32L1XX)
-#define AHB_EN_MASK     (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |          \
-                         RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN |          \
-                         RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
-#define AHB_LPEN_MASK   AHB_EN_MASK
-
-#elif defined(STM32F030) || defined(STM32F0XX_MD)
-#define AHB_EN_MASK     (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |          \
-                         RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN |          \
-                         RCC_AHBENR_GPIOFEN)
-
-#elif defined(STM32F0XX_LD)
-#define AHB_EN_MASK     (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |          \
-                         RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN)
-
-#elif defined(STM32F2XX)
-#define AHB1_EN_MASK    (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |        \
-                         RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |        \
-                         RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |        \
-                         RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN |        \
-                         RCC_AHB1ENR_GPIOIEN)
-#define AHB1_LPEN_MASK  AHB1_EN_MASK
-
-#elif defined(STM32F30X) || defined(STM32F37X)
-#define AHB_EN_MASK     (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |          \
-                         RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN |          \
-                         RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN)
-
-#elif defined(STM32F4XX)
-#define AHB1_EN_MASK    (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |        \
-                         RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |        \
-                         RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |        \
-                         RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN |        \
-                         RCC_AHB1ENR_GPIOIEN)
-#define AHB1_LPEN_MASK  AHB1_EN_MASK
-
-#else
-#error "missing or unsupported platform for GPIOv2 PAL driver"
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void initgpio(GPIO_TypeDef *gpiop, const stm32_gpio_setup_t *config) {
-
-  gpiop->OTYPER  = config->otyper;
-  gpiop->OSPEEDR = config->ospeedr;
-  gpiop->PUPDR   = config->pupdr;
-  gpiop->ODR     = config->odr;
-  gpiop->AFRL    = config->afrl;
-  gpiop->AFRH    = config->afrh;
-  gpiop->MODER   = config->moder;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 I/O ports configuration.
- * @details Ports A-D(E, F, G, H) clocks enabled.
- *
- * @param[in] config    the STM32 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  /*
-   * Enables the GPIO related clocks.
-   */
-#if defined(STM32L1XX)
-  rccEnableAHB(AHB_EN_MASK, TRUE);
-  RCC->AHBLPENR |= AHB_LPEN_MASK;
-#elif defined(STM32F0XX)
-  rccEnableAHB(AHB_EN_MASK, TRUE);
-#elif defined(STM32F30X) || defined(STM32F37X)
-  rccEnableAHB(AHB_EN_MASK, TRUE);
-#elif defined(STM32F2XX) || defined(STM32F4XX)
-  RCC->AHB1ENR   |= AHB1_EN_MASK;
-  RCC->AHB1LPENR |= AHB1_LPEN_MASK;
-#endif
-
-  /*
-   * Initial GPIO setup.
-   */
-#if STM32_HAS_GPIOA
-  initgpio(GPIOA, &config->PAData);
-#endif
-#if STM32_HAS_GPIOB
-  initgpio(GPIOB, &config->PBData);
-#endif
-#if STM32_HAS_GPIOC
-  initgpio(GPIOC, &config->PCData);
-#endif
-#if STM32_HAS_GPIOD
-  initgpio(GPIOD, &config->PDData);
-#endif
-#if STM32_HAS_GPIOE
-  initgpio(GPIOE, &config->PEData);
-#endif
-#if STM32_HAS_GPIOF
-  initgpio(GPIOF, &config->PFData);
-#endif
-#if STM32_HAS_GPIOG
-  initgpio(GPIOG, &config->PGData);
-#endif
-#if STM32_HAS_GPIOH
-  initgpio(GPIOH, &config->PHData);
-#endif
-#if STM32_HAS_GPIOI
-  initgpio(GPIOI, &config->PIData);
-#endif
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum
- *          speed.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-#if 1
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  uint32_t moder   = (mode & PAL_STM32_MODE_MASK) >> 0;
-  uint32_t otyper  = (mode & PAL_STM32_OTYPE_MASK) >> 2;
-  uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3;
-  uint32_t pupdr   = (mode & PAL_STM32_PUDR_MASK) >> 5;
-  uint32_t altr    = (mode & PAL_STM32_ALTERNATE_MASK) >> 7;
-  uint32_t bit     = 0;
-  while (TRUE) {
-    if ((mask & 1) != 0) {
-      uint32_t altrmask, m1, m2, m4;
-
-      altrmask = altr << ((bit & 7) * 4);
-      m4 = 15 << ((bit & 7) * 4);
-      if (bit < 8)
-        port->AFRL = (port->AFRL & ~m4) | altrmask;
-      else
-        port->AFRH = (port->AFRH & ~m4) | altrmask;
-      m1 = 1 << bit;
-      port->OTYPER  = (port->OTYPER & ~m1) | otyper;
-      m2 = 3 << (bit * 2);
-      port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
-      port->PUPDR   = (port->PUPDR & ~m2) | pupdr;
-      port->MODER   = (port->MODER & ~m2) | moder;
-    }
-    mask >>= 1;
-    if (!mask)
-      return;
-    otyper <<= 1;
-    ospeedr <<= 2;
-    pupdr <<= 2;
-    moder <<= 2;
-    bit++;
-  }
-}
-#else
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-  uint32_t afrm, moderm, pupdrm, otyperm, ospeedrm;
-  uint32_t m1 = (uint32_t)mask;
-  uint32_t m2 = 0;
-  uint32_t m4l = 0;
-  uint32_t m4h = 0;
-  uint32_t bit = 0;
-  do {
-    if ((mask & 1) != 0) {
-      m2 |= 3 << bit;
-      if (bit < 16)
-        m4l |= 15 << ((bit & 14) * 2);
-      else
-        m4h |= 15 << ((bit & 14) * 2);
-    }
-    bit += 2;
-    mask >>= 1;
-  } while (mask);
-
-  afrm = ((mode & PAL_STM32_ALTERNATE_MASK) >> 7) * 0x1111;
-  port->AFRL = (port->AFRL & ~m4l) | (afrm & m4l);
-  port->AFRH = (port->AFRH & ~m4h) | (afrm & m4h);
-
-  ospeedrm = ((mode & PAL_STM32_OSPEED_MASK) >> 3) * 0x5555;
-  port->OSPEEDR = (port->OSPEEDR & ~m2) | (ospeedrm & m2);
-
-  otyperm = ((mode & PAL_STM32_OTYPE_MASK) >> 2) * 0xffff;
-  port->OTYPER = (port->OTYPER & ~m1) | (otyperm & m1);
-
-  pupdrm = ((mode & PAL_STM32_PUDR_MASK) >> 5) * 0x5555;
-  port->PUPDR = (port->PUPDR & ~m2) | (pupdrm & m2);
-
-  moderm = ((mode & PAL_STM32_MODE_MASK) >> 0) * 0x5555;
-  port->MODER = (port->MODER & ~m2) | (moderm & m2);
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h
deleted file mode 100644
index 846584b86..000000000
--- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/GPIOv2/pal_lld.h
- * @brief   STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_RESET
-#undef PAL_MODE_UNCONNECTED
-#undef PAL_MODE_INPUT
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_INPUT_ANALOG
-#undef PAL_MODE_OUTPUT_PUSHPULL
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/**
- * @name    STM32-specific I/O mode flags
- * @{
- */
-#define PAL_STM32_MODE_MASK             (3 << 0)
-#define PAL_STM32_MODE_INPUT            (0 << 0)
-#define PAL_STM32_MODE_OUTPUT           (1 << 0)
-#define PAL_STM32_MODE_ALTERNATE        (2 << 0)
-#define PAL_STM32_MODE_ANALOG           (3 << 0)
-
-#define PAL_STM32_OTYPE_MASK            (1 << 2)
-#define PAL_STM32_OTYPE_PUSHPULL        (0 << 2)
-#define PAL_STM32_OTYPE_OPENDRAIN       (1 << 2)
-
-#define PAL_STM32_OSPEED_MASK           (3 << 3)
-#define PAL_STM32_OSPEED_LOWEST         (0 << 3)
-#if defined(STM32F0XX) || defined(STM32F30X) || defined(STM32F37X)
-#define PAL_STM32_OSPEED_MID            (1 << 3)
-#else
-#define PAL_STM32_OSPEED_MID1           (1 << 3)
-#define PAL_STM32_OSPEED_MID2           (2 << 3)
-#endif
-#define PAL_STM32_OSPEED_HIGHEST        (3 << 3)
-
-#define PAL_STM32_PUDR_MASK             (3 << 5)
-#define PAL_STM32_PUDR_FLOATING         (0 << 5)
-#define PAL_STM32_PUDR_PULLUP           (1 << 5)
-#define PAL_STM32_PUDR_PULLDOWN         (2 << 5)
-
-#define PAL_STM32_ALTERNATE_MASK        (15 << 7)
-#define PAL_STM32_ALTERNATE(n)          ((n) << 7)
-
-/**
- * @brief   Alternate function.
- *
- * @param[in] n         alternate function selector
- */
-#define PAL_MODE_ALTERNATE(n)           (PAL_STM32_MODE_ALTERNATE |         \
-                                         PAL_STM32_ALTERNATE(n))
-/** @} */
-
-/**
- * @name    Standard I/O mode flags
- * @{
- */
-/**
- * @brief   This mode is implemented as input.
- */
-#define PAL_MODE_RESET                  PAL_STM32_MODE_INPUT
-
-/**
- * @brief   This mode is implemented as input with pull-up.
- */
-#define PAL_MODE_UNCONNECTED            PAL_MODE_INPUT_PULLUP
-
-/**
- * @brief   Regular input high-Z pad.
- */
-#define PAL_MODE_INPUT                  PAL_STM32_MODE_INPUT
-
-/**
- * @brief   Input pad with weak pull up resistor.
- */
-#define PAL_MODE_INPUT_PULLUP           (PAL_STM32_MODE_INPUT |             \
-                                         PAL_STM32_PUDR_PULLUP)
-
-/**
- * @brief   Input pad with weak pull down resistor.
- */
-#define PAL_MODE_INPUT_PULLDOWN         (PAL_STM32_MODE_INPUT |             \
-                                         PAL_STM32_PUDR_PULLDOWN)
-
-/**
- * @brief   Analog input mode.
- */
-#define PAL_MODE_INPUT_ANALOG           PAL_STM32_MODE_ANALOG
-
-/**
- * @brief   Push-pull output pad.
- */
-#define PAL_MODE_OUTPUT_PUSHPULL        (PAL_STM32_MODE_OUTPUT |            \
-                                         PAL_STM32_OTYPE_PUSHPULL)
-
-/**
- * @brief   Open-drain output pad.
- */
-#define PAL_MODE_OUTPUT_OPENDRAIN       (PAL_STM32_MODE_OUTPUT |            \
-                                         PAL_STM32_OTYPE_OPENDRAIN)
-/** @} */
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 GPIO registers block.
- */
-typedef struct {
-
-  volatile uint32_t     MODER;
-  volatile uint32_t     OTYPER;
-  volatile uint32_t     OSPEEDR;
-  volatile uint32_t     PUPDR;
-  volatile uint32_t     IDR;
-  volatile uint32_t     ODR;
-  volatile union {
-    uint32_t            W;
-    struct {
-      uint16_t          set;
-      uint16_t          clear;
-    } H;
-  } BSRR;
-  volatile uint32_t     LCKR;
-  volatile uint32_t     AFRL;
-  volatile uint32_t     AFRH;
-} GPIO_TypeDef;
-
-/**
- * @brief   GPIO port setup info.
- */
-typedef struct {
-  /** Initial value for MODER register.*/
-  uint32_t              moder;
-  /** Initial value for OTYPER register.*/
-  uint32_t              otyper;
-  /** Initial value for OSPEEDR register.*/
-  uint32_t              ospeedr;
-  /** Initial value for PUPDR register.*/
-  uint32_t              pupdr;
-  /** Initial value for ODR register.*/
-  uint32_t              odr;
-  /** Initial value for AFRL register.*/
-  uint32_t              afrl;
-  /** Initial value for AFRH register.*/
-  uint32_t              afrh;
-} stm32_gpio_setup_t;
-
-/**
- * @brief   STM32 GPIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialize the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
-  /** @brief Port A setup data.*/
-  stm32_gpio_setup_t    PAData;
-#endif
-#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
-  /** @brief Port B setup data.*/
-  stm32_gpio_setup_t    PBData;
-#endif
-#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
-  /** @brief Port C setup data.*/
-  stm32_gpio_setup_t    PCData;
-#endif
-#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
-  /** @brief Port D setup data.*/
-  stm32_gpio_setup_t    PDData;
-#endif
-#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
-  /** @brief Port E setup data.*/
-  stm32_gpio_setup_t    PEData;
-#endif
-#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
-  /** @brief Port F setup data.*/
-  stm32_gpio_setup_t    PFData;
-#endif
-#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
-  /** @brief Port G setup data.*/
-  stm32_gpio_setup_t    PGData;
-#endif
-#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
-  /** @brief Port H setup data.*/
-  stm32_gpio_setup_t    PHData;
-#endif
-#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
-  /** @brief Port I setup data.*/
-  stm32_gpio_setup_t    PIData;
-#endif
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 16
-
-/**
- * @brief   Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- *          any assumption about it, use the provided macros when populating
- *          variables of this type.
- */
-typedef GPIO_TypeDef * ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/* The low level driver wraps the definitions already present in the STM32   */
-/* firmware library.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO port A identifier.
- */
-#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
-#define IOPORT1         GPIOA
-#endif
-
-/**
- * @brief   GPIO port B identifier.
- */
-#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
-#define IOPORT2         GPIOB
-#endif
-
-/**
- * @brief   GPIO port C identifier.
- */
-#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
-#define IOPORT3         GPIOC
-#endif
-
-/**
- * @brief   GPIO port D identifier.
- */
-#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
-#define IOPORT4         GPIOD
-#endif
-
-/**
- * @brief   GPIO port E identifier.
- */
-#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
-#define IOPORT5         GPIOE
-#endif
-
-/**
- * @brief   GPIO port F identifier.
- */
-#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
-#define IOPORT6         GPIOF
-#endif
-
-/**
- * @brief   GPIO port G identifier.
- */
-#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
-#define IOPORT7         GPIOG
-#endif
-
-/**
- * @brief   GPIO port H identifier.
- */
-#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
-#define IOPORT8         GPIOH
-#endif
-
-/**
- * @brief   GPIO port I identifier.
- */
-#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
-#define IOPORT9         GPIOI
-#endif
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO ports subsystem initialization.
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads an I/O port.
- * @details This function is implemented by reading the GPIO IDR register, the
- *          implementation has no side effects.
- * @note    This function is not meant to be invoked directly by the application
- *          code.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->IDR)
-
-/**
- * @brief   Reads the output latch.
- * @details This function is implemented by reading the GPIO ODR register, the
- *          implementation has no side effects.
- * @note    This function is not meant to be invoked directly by the application
- *          code.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->ODR)
-
-/**
- * @brief   Writes on a I/O port.
- * @details This function is implemented by writing the GPIO ODR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @details This function is implemented by writing the GPIO BSRR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits))
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @details This function is implemented by writing the GPIO BSRR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits))
-
-/**
- * @brief   Writes a group of bits.
- * @details This function is implemented by writing the GPIO BSRR register, the
- *          implementation has no side effects.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    the group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group
- *                      width are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits)                        \
-  ((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) |               \
-                     (((bits) & (mask)) << (offset)))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Writes a logical state on an output pad.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
deleted file mode 100644
index 2a36776f2..000000000
--- a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
+++ /dev/null
@@ -1,914 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    STM32/I2Cv1/i2c_lld.c
- * @brief   STM32 I2C subsystem low level driver source.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define I2C1_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM,                        \
-                       STM32_I2C1_RX_DMA_CHN)
-
-#define I2C1_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM,                        \
-                       STM32_I2C1_TX_DMA_CHN)
-
-#define I2C2_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM,                        \
-                       STM32_I2C2_RX_DMA_CHN)
-
-#define I2C2_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM,                        \
-                       STM32_I2C2_TX_DMA_CHN)
-
-#define I2C3_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM,                        \
-                       STM32_I2C3_RX_DMA_CHN)
-
-#define I2C3_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM,                        \
-                       STM32_I2C3_TX_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define I2C_EV5_MASTER_MODE_SELECT                                          \
-  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB))
-
-#define I2C_EV6_MASTER_TRA_MODE_SELECTED                                    \
-  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) |          \
-              I2C_SR1_ADDR | I2C_SR1_TXE))
-
-#define I2C_EV6_MASTER_REC_MODE_SELECTED                                    \
-  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR))
-
-#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED                                   \
-  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) |          \
-              I2C_SR1_BTF | I2C_SR1_TXE))
-
-#define I2C_EV9_MASTER_ADD10                                                \
-  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_ADD10))
-
-#define I2C_EV_MASK 0x00FFFFFF
-
-#define I2C_ERROR_MASK                                                      \
-  ((uint16_t)(I2C_SR1_BERR | I2C_SR1_ARLO | I2C_SR1_AF | I2C_SR1_OVR |      \
-              I2C_SR1_PECERR | I2C_SR1_TIMEOUT | I2C_SR1_SMBALERT))
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief I2C1 driver identifier.*/
-#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
-I2CDriver I2CD1;
-#endif
-
-/** @brief I2C2 driver identifier.*/
-#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
-I2CDriver I2CD2;
-#endif
-
-/** @brief I2C3 driver identifier.*/
-#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__)
-I2CDriver I2CD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Wakes up the waiting thread.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] msg       wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((i2cp)->thread != NULL) {                                             \
-    Thread *tp = (i2cp)->thread;                                            \
-    (i2cp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = (msg);                                                 \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
-}
-
-/**
- * @brief   Aborts an I2C transaction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_abort_operation(I2CDriver *i2cp) {
-  I2C_TypeDef *dp = i2cp->i2c;
-
-  /* Stops the I2C peripheral.*/
-  dp->CR1 = I2C_CR1_SWRST;
-  dp->CR1 = 0;
-  dp->CR2 = 0;
-  dp->SR1 = 0;
-
-  /* Stops the associated DMA streams.*/
-  dmaStreamDisable(i2cp->dmatx);
-  dmaStreamDisable(i2cp->dmarx);
-}
-
-/**
- * @brief   Handling of stalled I2C transactions.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_safety_timeout(void *p) {
-  I2CDriver *i2cp = (I2CDriver *)p;
-
-  chSysLockFromIsr();
-  if (i2cp->thread) {
-    Thread *tp = i2cp->thread;
-    i2c_lld_abort_operation(i2cp);
-    i2cp->thread = NULL;
-    tp->p_u.rdymsg = RDY_TIMEOUT;
-    chSchReadyI(tp);
-  }
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Set clock speed.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_set_clock(I2CDriver *i2cp) {
-  I2C_TypeDef *dp = i2cp->i2c;
-  uint16_t regCCR, clock_div;
-  int32_t clock_speed = i2cp->config->clock_speed;
-  i2cdutycycle_t duty = i2cp->config->duty_cycle;
-
-  chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000),
-             "i2c_lld_set_clock");
-
-  /* CR2 Configuration.*/
-  dp->CR2 &= (uint16_t)~I2C_CR2_FREQ;
-  dp->CR2 |= (uint16_t)I2C_CLK_FREQ;
-
-  /* CCR Configuration.*/
-  regCCR = 0;
-  clock_div = I2C_CCR_CCR;
-
-  if (clock_speed <= 100000) {
-    /* Configure clock_div in standard mode.*/
-    chDbgAssert(duty == STD_DUTY_CYCLE,
-                "i2c_lld_set_clock(), #1",
-                "Invalid standard mode duty cycle");
-
-    /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/
-    chDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0,
-                "i2c_lld_set_clock(), #2",
-                "PCLK1 must be divided without remainder");
-    clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2));
-
-    chDbgAssert(clock_div >= 0x04,
-                "i2c_lld_set_clock(), #3",
-                "Clock divider less then 0x04 not allowed");
-    regCCR |= (clock_div & I2C_CCR_CCR);
-
-    /* Sets the Maximum Rise Time for standard mode.*/
-    dp->TRISE = I2C_CLK_FREQ + 1;
-  }
-  else if (clock_speed <= 400000) {
-    /* Configure clock_div in fast mode.*/
-    chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9),
-                "i2c_lld_set_clock(), #4",
-                "Invalid fast mode duty cycle");
-
-    if (duty == FAST_DUTY_CYCLE_2) {
-      /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/
-      chDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0,
-                  "i2c_lld_set_clock(), #5",
-                  "PCLK1 must be divided without remainder");
-      clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3));
-    }
-    else if (duty == FAST_DUTY_CYCLE_16_9) {
-      /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/
-      chDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0,
-                  "i2c_lld_set_clock(), #6",
-                  "PCLK1 must be divided without remainder");
-      clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25));
-      regCCR |= I2C_CCR_DUTY;
-    }
-
-    chDbgAssert(clock_div >= 0x01,
-                    "i2c_lld_set_clock(), #7",
-                    "Clock divider less then 0x04 not allowed");
-    regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR));
-
-    /* Sets the Maximum Rise Time for fast mode.*/
-    dp->TRISE = (I2C_CLK_FREQ * 300 / 1000) + 1;
-  }
-
-  chDbgAssert((clock_div <= I2C_CCR_CCR),
-              "i2c_lld_set_clock(), #8", "the selected clock is too low");
-
-  dp->CCR = regCCR;
-}
-
-/**
- * @brief   Set operation mode of I2C hardware.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_set_opmode(I2CDriver *i2cp) {
-  I2C_TypeDef *dp = i2cp->i2c;
-  i2copmode_t opmode = i2cp->config->op_mode;
-  uint16_t regCR1;
-
-  regCR1 = dp->CR1;
-  switch (opmode) {
-  case OPMODE_I2C:
-    regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE);
-    break;
-  case OPMODE_SMBUS_DEVICE:
-    regCR1 |= I2C_CR1_SMBUS;
-    regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE);
-    break;
-  case OPMODE_SMBUS_HOST:
-    regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE);
-    break;
-  }
-  dp->CR1 = regCR1;
-}
-
-/**
- * @brief   I2C shared ISR code.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
-  I2C_TypeDef *dp = i2cp->i2c;
-  uint32_t regSR2 = dp->SR2;
-  uint32_t event = dp->SR1;
-
-  /* Interrupts are disabled just before dmaStreamEnable() because there
-     is no need of interrupts until next transaction begin. All the work is
-     done by the DMA.*/
-  switch (I2C_EV_MASK & (event | (regSR2 << 16))) {
-  case I2C_EV5_MASTER_MODE_SELECT:
-    if ((i2cp->addr >> 8) > 0) { 
-      /* 10-bit address: 1 1 1 1 0 X X R/W */
-      dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr);
-    } else {
-      dp->DR = i2cp->addr;
-    }
-    break;
-  case I2C_EV9_MASTER_ADD10:
-    /* Set second addr byte (10-bit addressing)*/
-    dp->DR = (0xFF & (i2cp->addr >> 1));
-    break;
-  case I2C_EV6_MASTER_REC_MODE_SELECTED:
-    dp->CR2 &= ~I2C_CR2_ITEVTEN;
-    dmaStreamEnable(i2cp->dmarx);
-    dp->CR2 |= I2C_CR2_LAST;                 /* Needed in receiver mode. */
-    if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2)
-      dp->CR1 &= ~I2C_CR1_ACK;
-    break;
-  case I2C_EV6_MASTER_TRA_MODE_SELECTED:
-    dp->CR2 &= ~I2C_CR2_ITEVTEN;
-    dmaStreamEnable(i2cp->dmatx);
-    break;
-  case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
-    /* Catches BTF event after the end of transmission.*/
-    if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) {
-      /* Starts "read after write" operation, LSB = 1 -> receive.*/
-      i2cp->addr |= 0x01;
-      dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
-      return;
-    }
-    dp->CR2 &= ~I2C_CR2_ITEVTEN;
-    dp->CR1 |= I2C_CR1_STOP;
-    wakeup_isr(i2cp, RDY_OK);
-    break;
-  default:
-    break;
-  }
-  /* Clear ADDR flag. */
-  if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))
-    (void)dp->SR2;
-}
-
-/**
- * @brief   DMA RX end IRQ handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- *
- * @notapi
- */
-static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
-  I2C_TypeDef *dp = i2cp->i2c;
-
-  /* DMA errors handling.*/
-#if defined(STM32_I2C_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_I2C_DMA_ERROR_HOOK(i2cp);
-  }
-#else
-  (void)flags;
-#endif
-
-  dmaStreamDisable(i2cp->dmarx);
-
-  dp->CR2 &= ~I2C_CR2_LAST;
-  dp->CR1 &= ~I2C_CR1_ACK;
-  dp->CR1 |= I2C_CR1_STOP;
-  wakeup_isr(i2cp, RDY_OK);
-}
-
-/**
- * @brief    DMA TX end IRQ handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
-  I2C_TypeDef *dp = i2cp->i2c;
-
-  /* DMA errors handling.*/
-#if defined(STM32_I2C_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_I2C_DMA_ERROR_HOOK(i2cp);
-  }
-#else
-  (void)flags;
-#endif
-
-  dmaStreamDisable(i2cp->dmatx);
-  /* Enables interrupts to catch BTF event meaning transmission part complete.
-     Interrupt handler will decide to generate STOP or to begin receiving part
-     of R/W transaction itself.*/
-  dp->CR2 |= I2C_CR2_ITEVTEN;
-}
-
-/**
- * @brief   I2C error handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in]  sr       content of the SR1 register to be decoded
- *
- * @notapi
- */
-static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) {
-
-  /* Clears interrupt flags just to be safe.*/
-  dmaStreamDisable(i2cp->dmatx);
-  dmaStreamDisable(i2cp->dmarx);
-
-  i2cp->errors = I2CD_NO_ERROR;
-
-  if (sr & I2C_SR1_BERR)                            /* Bus error.           */
-    i2cp->errors |= I2CD_BUS_ERROR;
-
-  if (sr & I2C_SR1_ARLO)                            /* Arbitration lost.    */
-    i2cp->errors |= I2CD_ARBITRATION_LOST;
-
-  if (sr & I2C_SR1_AF) {                            /* Acknowledge fail.    */
-    i2cp->i2c->CR2 &= ~I2C_CR2_ITEVTEN;
-    i2cp->i2c->CR1 |= I2C_CR1_STOP;                 /* Setting stop bit.    */
-    i2cp->errors |= I2CD_ACK_FAILURE;
-  }
-
-  if (sr & I2C_SR1_OVR)                             /* Overrun.             */
-    i2cp->errors |= I2CD_OVERRUN;
-
-  if (sr & I2C_SR1_TIMEOUT)                         /* SMBus Timeout.       */
-    i2cp->errors |= I2CD_TIMEOUT;
-
-  if (sr & I2C_SR1_PECERR)                          /* PEC error.           */
-    i2cp->errors |= I2CD_PEC_ERROR;
-
-  if (sr & I2C_SR1_SMBALERT)                        /* SMBus alert.         */
-    i2cp->errors |= I2CD_SMB_ALERT;
-
-  /* If some error has been identified then sends wakes the waiting thread.*/
-  if (i2cp->errors != I2CD_NO_ERROR)
-    wakeup_isr(i2cp, RDY_RESET);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
-/**
- * @brief   I2C1 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(I2C1_EV_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  i2c_lld_serve_event_interrupt(&I2CD1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   I2C1 error interrupt handler.
- */
-CH_IRQ_HANDLER(I2C1_ER_IRQHandler) {
-  uint16_t sr = I2CD1.i2c->SR1;
-
-  CH_IRQ_PROLOGUE();
-
-  I2CD1.i2c->SR1 = ~(sr & I2C_ERROR_MASK);
-  i2c_lld_serve_error_interrupt(&I2CD1, sr);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_I2C_USE_I2C1 */
-
-#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
-/**
- * @brief   I2C2 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(I2C2_EV_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  i2c_lld_serve_event_interrupt(&I2CD2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   I2C2 error interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(I2C2_ER_IRQHandler) {
-  uint16_t sr = I2CD2.i2c->SR1;
-
-  CH_IRQ_PROLOGUE();
-
-  I2CD2.i2c->SR1 = ~(sr & I2C_ERROR_MASK);
-  i2c_lld_serve_error_interrupt(&I2CD2, sr);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_I2C_USE_I2C2 */
-
-#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__)
-/**
- * @brief   I2C3 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(I2C3_EV_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  i2c_lld_serve_event_interrupt(&I2CD3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   I2C3 error interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(I2C3_ER_IRQHandler) {
-  uint16_t sr = I2CD3.i2c->SR1;
-
-  CH_IRQ_PROLOGUE();
-
-  I2CD3.i2c->SR1 = ~(sr & I2C_ERROR_MASK);
-  i2c_lld_serve_error_interrupt(&I2CD3, sr);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_I2C_USE_I2C3 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-#if STM32_I2C_USE_I2C1
-  i2cObjectInit(&I2CD1);
-  I2CD1.thread = NULL;
-  I2CD1.i2c    = I2C1;
-  I2CD1.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
-  I2CD1.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
-#endif /* STM32_I2C_USE_I2C1 */
-
-#if STM32_I2C_USE_I2C2
-  i2cObjectInit(&I2CD2);
-  I2CD2.thread = NULL;
-  I2CD2.i2c    = I2C2;
-  I2CD2.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
-  I2CD2.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
-#endif /* STM32_I2C_USE_I2C2 */
-
-#if STM32_I2C_USE_I2C3
-  i2cObjectInit(&I2CD3);
-  I2CD3.thread = NULL;
-  I2CD3.i2c    = I2C3;
-  I2CD3.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM);
-  I2CD3.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM);
-#endif /* STM32_I2C_USE_I2C3 */
-}
-
-/**
- * @brief   Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-  I2C_TypeDef *dp = i2cp->i2c;
-
-  i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
-                    STM32_DMA_CR_MINC       | STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE       | STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DIR_M2P;
-  i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
-                    STM32_DMA_CR_MINC       | STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE       | STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DIR_P2M;
-
-  /* If in stopped state then enables the I2C and DMA clocks.*/
-  if (i2cp->state == I2C_STOP) {
-
-#if STM32_I2C_USE_I2C1
-    if (&I2CD1 == i2cp) {
-      bool_t b;
-
-      rccResetI2C1();
-      b = dmaStreamAllocate(i2cp->dmarx,
-                            STM32_I2C_I2C1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated");
-      b = dmaStreamAllocate(i2cp->dmatx,
-                            STM32_I2C_I2C1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated");
-      rccEnableI2C1(FALSE);
-      nvicEnableVector(I2C1_EV_IRQn,
-          CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
-      nvicEnableVector(I2C1_ER_IRQn,
-          CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
-
-      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
-                       STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
-      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
-                       STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
-    }
-#endif /* STM32_I2C_USE_I2C1 */
-
-#if STM32_I2C_USE_I2C2
-    if (&I2CD2 == i2cp) {
-      bool_t b;
-
-      rccResetI2C2();
-      b = dmaStreamAllocate(i2cp->dmarx,
-                            STM32_I2C_I2C2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated");
-      b = dmaStreamAllocate(i2cp->dmatx,
-                            STM32_I2C_I2C2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated");
-      rccEnableI2C2(FALSE);
-      nvicEnableVector(I2C2_EV_IRQn,
-          CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
-      nvicEnableVector(I2C2_ER_IRQn,
-          CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
-
-      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
-                       STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
-      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
-                       STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
-    }
-#endif /* STM32_I2C_USE_I2C2 */
-
-#if STM32_I2C_USE_I2C3
-    if (&I2CD3 == i2cp) {
-      bool_t b;
-
-      rccResetI2C3();
-      b = dmaStreamAllocate(i2cp->dmarx,
-                            STM32_I2C_I2C3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #5", "stream already allocated");
-      b = dmaStreamAllocate(i2cp->dmatx,
-                            STM32_I2C_I2C3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #6", "stream already allocated");
-      rccEnableI2C3(FALSE);
-      nvicEnableVector(I2C3_EV_IRQn,
-          CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY));
-      nvicEnableVector(I2C3_ER_IRQn,
-          CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY));
-
-      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
-                       STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
-      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) |
-                       STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
-    }
-#endif /* STM32_I2C_USE_I2C3 */
-  }
-
-  /* I2C registers pointed by the DMA.*/
-  dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR);
-  dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR);
-
-  /* Reset i2c peripheral.*/
-  dp->CR1 = I2C_CR1_SWRST;
-  dp->CR1 = 0;
-  dp->CR2 = I2C_CR2_ITERREN | I2C_CR2_DMAEN;
-
-  /* Setup I2C parameters.*/
-  i2c_lld_set_clock(i2cp);
-  i2c_lld_set_opmode(i2cp);
-
-  /* Ready to go.*/
-  dp->CR1 |= I2C_CR1_PE;
-}
-
-/**
- * @brief   Deactivates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
-  /* If not in stopped state then disables the I2C clock.*/
-  if (i2cp->state != I2C_STOP) {
-
-    /* I2C disable.*/
-    i2c_lld_abort_operation(i2cp);
-    dmaStreamRelease(i2cp->dmatx);
-    dmaStreamRelease(i2cp->dmarx);
-
-#if STM32_I2C_USE_I2C1
-    if (&I2CD1 == i2cp) {
-      nvicDisableVector(I2C1_EV_IRQn);
-      nvicDisableVector(I2C1_ER_IRQn);
-      rccDisableI2C1(FALSE);
-    }
-#endif
-
-#if STM32_I2C_USE_I2C2
-    if (&I2CD2 == i2cp) {
-      nvicDisableVector(I2C2_EV_IRQn);
-      nvicDisableVector(I2C2_ER_IRQn);
-      rccDisableI2C2(FALSE);
-    }
-#endif
-
-#if STM32_I2C_USE_I2C3
-    if (&I2CD3 == i2cp) {
-      nvicDisableVector(I2C3_EV_IRQn);
-      nvicDisableVector(I2C3_ER_IRQn);
-      rccDisableI2C3(FALSE);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Receives data via the I2C bus as master.
- * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
- *          hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                     uint8_t *rxbuf, size_t rxbytes,
-                                     systime_t timeout) {
-  I2C_TypeDef *dp = i2cp->i2c;
-  VirtualTimer vt;
-
-#if defined(STM32F1XX_I2C)
-  chDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout");
-#endif
-
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Initializes driver fields, LSB = 1 -> receive.*/
-  i2cp->addr = (addr << 1) | 0x01;
-  i2cp->errors = 0;
-
-  /* RX DMA setup.*/
-  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
-  dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
-
-  /* Waits until BUSY flag is reset and the STOP from the previous operation
-     is completed, alternatively for a timeout condition.*/
-  while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) {
-    chSysLock();
-    if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-      return RDY_TIMEOUT;
-    chSysUnlock();
-  }
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Starts the operation.*/
-  dp->CR2 |= I2C_CR2_ITEVTEN;
-  dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief   Transmits data via the I2C bus as master.
- * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
- *          This is hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[in] txbuf     pointer to the transmit buffer
- * @param[in] txbytes   number of bytes to be transmitted
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                      const uint8_t *txbuf, size_t txbytes,
-                                      uint8_t *rxbuf, size_t rxbytes,
-                                      systime_t timeout) {
-  I2C_TypeDef *dp = i2cp->i2c;
-  VirtualTimer vt;
-
-#if defined(STM32F1XX_I2C)
-  chDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))),
-             "i2c_lld_master_transmit_timeout");
-#endif
-
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Initializes driver fields, LSB = 0 -> write.*/
-  i2cp->addr = addr << 1;
-  i2cp->errors = 0;
-
-  /* TX DMA setup.*/
-  dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode);
-  dmaStreamSetMemory0(i2cp->dmatx, txbuf);
-  dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
-
-  /* RX DMA setup.*/
-  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
-  dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
-
-  /* Waits until BUSY flag is reset and the STOP from the previous operation
-     is completed, alternatively for a timeout condition.*/
-  while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) {
-    chSysLock();
-    if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-      return RDY_TIMEOUT;
-    chSysUnlock();
-  }
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Starts the operation.*/
-  dp->CR2 |= I2C_CR2_ITEVTEN;
-  dp->CR1 |= I2C_CR1_START;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.h b/os/hal/platforms/STM32/I2Cv1/i2c_lld.h
deleted file mode 100644
index dcadb3278..000000000
--- a/os/hal/platforms/STM32/I2Cv1/i2c_lld.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    STM32/I2Cv1/i2c_lld.h
- * @brief   STM32 I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Peripheral clock frequency.
- */
-#define I2C_CLK_FREQ  ((STM32_PCLK1) / 1000000)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   I2C1 driver enable switch.
- * @details If set to @p TRUE the support for I2C1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define STM32_I2C_USE_I2C1              FALSE
-#endif
-
-/**
- * @brief   I2C2 driver enable switch.
- * @details If set to @p TRUE the support for I2C2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
-#define STM32_I2C_USE_I2C2              FALSE
-#endif
-
-/**
- * @brief   I2C3 driver enable switch.
- * @details If set to @p TRUE the support for I2C3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__)
-#define STM32_I2C_USE_I2C3              FALSE
-#endif
-
-/**
- * @brief   I2C1 interrupt priority level setting.
- */
-#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_IRQ_PRIORITY     10
-#endif
-
-/**
- * @brief   I2C2 interrupt priority level setting.
- */
-#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_IRQ_PRIORITY     10
-#endif
-
-/**
- * @brief   I2C3 interrupt priority level setting.
- */
-#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C3_IRQ_PRIORITY     10
-#endif
-
-/**
-* @brief   I2C1 DMA priority (0..3|lowest..highest).
-* @note    The priority level is used for both the TX and RX DMA streams but
-*          because of the streams ordering the RX stream has always priority
-*          over the TX stream.
-*/
-#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_DMA_PRIORITY         1
-#endif
-
-/**
-* @brief   I2C2 DMA priority (0..3|lowest..highest).
-* @note    The priority level is used for both the TX and RX DMA streams but
-*          because of the streams ordering the RX stream has always priority
-*          over the TX stream.
-*/
-#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_DMA_PRIORITY         1
-#endif
-
-/**
-* @brief   I2C3 DMA priority (0..3|lowest..highest).
-* @note    The priority level is used for both the TX and RX DMA streams but
-*          because of the streams ordering the RX stream has always priority
-*          over the TX stream.
-*/
-#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C3_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   I2C DMA error hook.
- * @note    The default action for DMA errors is a system halt because DMA
- *          error can only happen because programming errors.
- */
-#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_I2C_DMA_ERROR_HOOK(i2cp)  chSysHalt()
-#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief   DMA stream used for I2C1 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 0)
-#endif
-
-/**
- * @brief   DMA stream used for I2C1 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#endif
-
-/**
- * @brief   DMA stream used for I2C2 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-#endif
-
-/**
- * @brief   DMA stream used for I2C2 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-#endif
-
-/**
- * @brief   DMA stream used for I2C3 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-#endif
-
-/**
- * @brief   DMA stream used for I2C3 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-#endif
-
-#else /* !STM32_ADVANCED_DMA */
-
-/* Fixed streams for platforms using the old DMA peripheral, the values are
-   valid for both STM32F1xx and STM32L1xx.*/
-#define STM32_I2C_I2C1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_I2C_I2C2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#endif /* !STM32_ADVANCED_DMA*/
-
-/* Flag for the whole STM32F1XX family. */
-#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
-    defined(STM32F10X_LD)    || defined(STM32F10X_MD)    || \
-    defined(STM32F10X_HD)    || defined(STM32F10X_XL)    || \
-                                defined(STM32F10X_CL)
-#define STM32F1XX_I2C
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/** @brief  error checks */
-#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
-#error "I2C1 not present in the selected device"
-#endif
-
-#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2
-#error "I2C2 not present in the selected device"
-#endif
-
-#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3
-#error "I2C3 not present in the selected device"
-#endif
-
-#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 &&                           \
-    !STM32_I2C_USE_I2C3
-#error "I2C driver activated but no I2C peripheral assigned"
-#endif
-
-#if STM32_I2C_USE_I2C1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM,                    \
-                           STM32_I2C1_RX_DMA_MSK)
-#error "invalid DMA stream associated to I2C1 RX"
-#endif
-
-#if STM32_I2C_USE_I2C1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM,                    \
-                           STM32_I2C1_TX_DMA_MSK)
-#error "invalid DMA stream associated to I2C1 TX"
-#endif
-
-#if STM32_I2C_USE_I2C2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM,                    \
-                           STM32_I2C2_RX_DMA_MSK)
-#error "invalid DMA stream associated to I2C2 RX"
-#endif
-
-#if STM32_I2C_USE_I2C2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM,                    \
-                           STM32_I2C2_TX_DMA_MSK)
-#error "invalid DMA stream associated to I2C2 TX"
-#endif
-
-#if STM32_I2C_USE_I2C3 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM,                    \
-                           STM32_I2C3_RX_DMA_MSK)
-#error "invalid DMA stream associated to I2C3 RX"
-#endif
-
-#if STM32_I2C_USE_I2C3 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM,                    \
-                           STM32_I2C3_TX_DMA_MSK)
-#error "invalid DMA stream associated to I2C3 TX"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/* Check clock range. */
-#if defined(STM32F4XX)
-#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 42)
-#error "I2C peripheral clock frequency out of range."
-#endif
-
-#elif defined(STM32L1XX_MD)
-#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 32)
-#error "I2C peripheral clock frequency out of range."
-#endif
-
-#elif defined(STM32F2XX)
-#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 30)
-#error "I2C peripheral clock frequency out of range."
-#endif
-
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
-      defined(STM32F10X_HD_VL)
-#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 24)
-#error "I2C peripheral clock frequency out of range."
-#endif
-
-#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) ||                     \
-      defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                     \
-      defined(STM32F10X_CL)
-#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 36)
-#error "I2C peripheral clock frequency out of range."
-#endif
-#else
-#error "unspecified, unsupported or invalid STM32 platform"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing I2C address.
- */
-typedef uint16_t i2caddr_t;
-
-/**
- * @brief   I2C Driver condition flags type.
- */
-typedef uint32_t i2cflags_t;
-
-/**
- * @brief   Supported modes for the I2C bus.
- */
-typedef enum {
-  OPMODE_I2C = 1,
-  OPMODE_SMBUS_DEVICE = 2,
-  OPMODE_SMBUS_HOST = 3,
-} i2copmode_t;
-
-/**
- * @brief   Supported duty cycle modes for the I2C bus.
- */
-typedef enum {
-  STD_DUTY_CYCLE = 1,
-  FAST_DUTY_CYCLE_2 = 2,
-  FAST_DUTY_CYCLE_16_9 = 3,
-} i2cdutycycle_t;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
-  i2copmode_t     op_mode;       /**< @brief Specifies the I2C mode.        */
-  uint32_t        clock_speed;   /**< @brief Specifies the clock frequency.
-                                      @note Must be set to a value lower
-                                      than 400kHz.                          */
-  i2cdutycycle_t  duty_cycle;    /**< @brief Specifies the I2C fast mode
-                                      duty cycle.                           */
-} I2CConfig;
-
-/**
- * @brief   Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver {
-  /**
-   * @brief   Driver state.
-   */
-  i2cstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const I2CConfig           *config;
-  /**
-   * @brief   Error flags.
-   */
-  i2cflags_t                errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
-  I2C_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Thread waiting for I/O completion.
-   */
-  Thread                    *thread;
-  /**
-   * @brief     Current slave address without R/W bit.
-   */
-  i2caddr_t                 addr;
-  /**
-   * @brief RX DMA mode bit mask.
-   */
-  uint32_t                  rxdmamode;
-  /**
-   * @brief TX DMA mode bit mask.
-   */
-  uint32_t                  txdmamode;
-  /**
-   * @brief     Receive DMA channel.
-   */
-  const stm32_dma_stream_t  *dmarx;
-  /**
-   * @brief     Transmit DMA channel.
-   */
-  const stm32_dma_stream_t  *dmatx;
-  /**
-   * @brief     Pointer to the I2Cx registers block.
-   */
-  I2C_TypeDef               *i2c;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Get errors from I2C driver.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-#if STM32_I2C_USE_I2C1
-extern I2CDriver I2CD1;
-#endif
-
-#if STM32_I2C_USE_I2C2
-extern I2CDriver I2CD2;
-#endif
-
-#if STM32_I2C_USE_I2C3
-extern I2CDriver I2CD3;
-#endif
-#endif /* !defined(__DOXYGEN__) */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void i2c_lld_init(void);
-  void i2c_lld_start(I2CDriver *i2cp);
-  void i2c_lld_stop(I2CDriver *i2cp);
-  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                        const uint8_t *txbuf, size_t txbytes,
-                                        uint8_t *rxbuf, size_t rxbytes,
-                                        systime_t timeout);
-  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                       uint8_t *rxbuf, size_t rxbytes,
-                                       systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_I2C  */
-
-#endif /* _I2C_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/I2Cv2/i2c_lld.c b/os/hal/platforms/STM32/I2Cv2/i2c_lld.c
deleted file mode 100644
index 1050dc08f..000000000
--- a/os/hal/platforms/STM32/I2Cv2/i2c_lld.c
+++ /dev/null
@@ -1,789 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    STM32/I2Cv2/i2c_lld.c
- * @brief   STM32 I2C subsystem low level driver source.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define DMAMODE_COMMON                                                      \
-  (STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |                      \
-   STM32_DMA_CR_MINC       | STM32_DMA_CR_DMEIE      |                      \
-   STM32_DMA_CR_TEIE       | STM32_DMA_CR_TCIE)
-
-#define I2C1_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM,                        \
-                       STM32_I2C1_RX_DMA_CHN)
-
-#define I2C1_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM,                        \
-                       STM32_I2C1_TX_DMA_CHN)
-
-#define I2C2_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM,                        \
-                       STM32_I2C2_RX_DMA_CHN)
-
-#define I2C2_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM,                        \
-                       STM32_I2C2_TX_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define I2C_MASTER_TC                                                       \
-  ((uint32_t)(I2C_ISR_BUSY | I2C_ISR_TC))
-
-#define I2C_ERROR_MASK                                                      \
-  ((uint32_t)(I2C_ISR_BERR | I2C_ISR_ARLO | I2C_ISR_OVR | I2C_ISR_PECERR |  \
-              I2C_ISR_TIMEOUT | I2C_ISR_ALERT))
-
-#define I2C_INT_MASK                                                        \
-  ((uint32_t)(I2C_ISR_TCR | I2C_ISR_TC | I2C_ISR_STOPF | I2C_ISR_NACKF |    \
-              I2C_ISR_ADDR | I2C_ISR_RXNE | I2C_ISR_TXIS))
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief I2C1 driver identifier.*/
-#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
-I2CDriver I2CD1;
-#endif
-
-/** @brief I2C2 driver identifier.*/
-#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
-I2CDriver I2CD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Wakes up the waiting thread.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] msg       wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) {                                             \
-  chSysLockFromIsr();                                                       \
-  if ((i2cp)->thread != NULL) {                                             \
-    Thread *tp = (i2cp)->thread;                                            \
-    (i2cp)->thread = NULL;                                                  \
-    tp->p_u.rdymsg = (msg);                                                 \
-    chSchReadyI(tp);                                                        \
-  }                                                                         \
-  chSysUnlockFromIsr();                                                     \
-}
-
-/**
- * @brief   Aborts an I2C transaction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_abort_operation(I2CDriver *i2cp) {
-  I2C_TypeDef *dp = i2cp->i2c;
-
-  if (dp->CR1 & I2C_CR1_PE) {
-    /* Stops the I2C peripheral.*/
-    dp->CR1 &= ~I2C_CR1_PE;
-    while (dp->CR1 & I2C_CR1_PE)
-      dp->CR1 &= ~I2C_CR1_PE;
-    dp->CR1 |= I2C_CR1_PE;
-  }
-
-  /* Stops the associated DMA streams.*/
-  dmaStreamDisable(i2cp->dmatx);
-  dmaStreamDisable(i2cp->dmarx);
-}
-
-/**
- * @brief   Handling of stalled I2C transactions.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_safety_timeout(void *p) {
-  I2CDriver *i2cp = (I2CDriver *)p;
-
-  chSysLockFromIsr();
-  if (i2cp->thread) {
-    Thread *tp = i2cp->thread;
-    i2c_lld_abort_operation(i2cp);
-    i2cp->thread = NULL;
-    tp->p_u.rdymsg = RDY_TIMEOUT;
-    chSchReadyI(tp);
-  }
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   I2C shared ISR code.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] isr       content of the ISR register to be decoded
- *
- * @notapi
- */
-static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t isr) {
-  I2C_TypeDef *dp = i2cp->i2c;
-
-  if ((isr & I2C_ISR_TC) && (i2cp->state == I2C_ACTIVE_TX)) {
-    size_t rxbytes;
-
-    /* Make sure no more 'Transfer complete' interrupts.*/
-    dp->CR1 &= ~I2C_CR1_TCIE;
-
-    rxbytes = dmaStreamGetTransactionSize(i2cp->dmarx);
-    if (rxbytes > 0) {
-      i2cp->state = I2C_ACTIVE_RX;
-
-      /* Enable RX DMA */
-      dmaStreamEnable(i2cp->dmarx);
-
-      dp->CR2 &= ~I2C_CR2_NBYTES;
-      dp->CR2 |= rxbytes << 16;
-
-      /* Starts the read operation.*/
-      dp->CR2 |= I2C_CR2_RD_WRN;
-      dp->CR2 |= I2C_CR2_START;
-    }
-    else {
-      /* Nothing to receive - send STOP immediately.*/
-      dp->CR2 |= I2C_CR2_STOP;
-    }
-  }
-  if (isr & I2C_ISR_NACKF) {
-    /* Starts a STOP sequence immediately on error.*/
-    dp->CR2 |= I2C_CR2_STOP;
-
-    i2cp->errors |= I2CD_ACK_FAILURE;
-  }
-  if (isr & I2C_ISR_STOPF) {
-    /* Stops the associated DMA streams.*/
-    dmaStreamDisable(i2cp->dmatx);
-    dmaStreamDisable(i2cp->dmarx);
-
-    if (i2cp->errors) {
-      wakeup_isr(i2cp, RDY_RESET);
-    }
-    else {
-      wakeup_isr(i2cp, RDY_OK);
-    }
-  }
-}
-
-/**
- * @brief   DMA RX end IRQ handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- *
- * @notapi
- */
-static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
-  I2C_TypeDef *dp = i2cp->i2c;
-
-  /* DMA errors handling.*/
-#if defined(STM32_I2C_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_I2C_DMA_ERROR_HOOK(i2cp);
-  }
-#else
-  (void)flags;
-#endif
-
-  dmaStreamDisable(i2cp->dmarx);
-  dp->CR2 |= I2C_CR2_STOP;
-  wakeup_isr(i2cp, RDY_OK);
-}
-
-/**
- * @brief    DMA TX end IRQ handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-#if defined(STM32_I2C_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_I2C_DMA_ERROR_HOOK(i2cp);
-  }
-#else
-  (void)flags;
-#endif
-
-  dmaStreamDisable(i2cp->dmatx);
-}
-
-/**
- * @brief   I2C error handler.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] isr       content of the ISR register to be decoded
- *
- * @notapi
- */
-static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t isr) {
-
-  /* Clears interrupt flags just to be safe.*/
-  dmaStreamDisable(i2cp->dmatx);
-  dmaStreamDisable(i2cp->dmarx);
-
-  if (isr & I2C_ISR_BERR)
-    i2cp->errors |= I2CD_BUS_ERROR;
-
-  if (isr & I2C_ISR_ARLO)
-    i2cp->errors |= I2CD_ARBITRATION_LOST;
-
-  if (isr & I2C_ISR_OVR)
-    i2cp->errors |= I2CD_OVERRUN;
-
-  if (isr & I2C_ISR_TIMEOUT)
-    i2cp->errors |= I2CD_TIMEOUT;
-
-  /* If some error has been identified then sends wakes the waiting thread.*/
-  if (i2cp->errors != I2CD_NO_ERROR)
-    wakeup_isr(i2cp, RDY_RESET);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
-#if defined(STM32_I2C1_GLOBAL_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief   I2C1 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(STM32_I2C1_GLOBAL_HANDLER) {
-  uint32_t isr = I2CD1.i2c->ISR;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Clearing IRQ bits.*/
-  I2CD1.i2c->ICR = isr;
-
-  if (isr & I2C_ERROR_MASK)
-    i2c_lld_serve_error_interrupt(&I2CD1, isr);
-  else if (isr & I2C_INT_MASK)
-    i2c_lld_serve_interrupt(&I2CD1, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#elif defined(STM32_I2C1_EVENT_HANDLER) && defined(STM32_I2C1_ERROR_HANDLER)
-CH_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) {
-  uint32_t isr = I2CD1.i2c->ISR;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Clearing IRQ bits.*/
-  I2CD1.i2c->ICR = isr & I2C_INT_MASK;
-
-  i2c_lld_serve_interrupt(&I2CD1, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) {
-  uint32_t isr = I2CD1.i2c->ISR;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Clearing IRQ bits.*/
-  I2CD1.i2c->ICR = isr & I2C_ERROR_MASK;
-
-  i2c_lld_serve_error_interrupt(&I2CD1, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#else
-#error "I2C1 interrupt handlers not defined"
-#endif
-#endif /* STM32_I2C_USE_I2C1 */
-
-#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
-#if defined(STM32_I2C2_GLOBAL_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief   I2C2 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(STM32_I2C2_GLOBAL_HANDLER) {
-  uint32_t isr = I2CD2.i2c->ISR;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Clearing IRQ bits.*/
-  I2CD2.i2c->ICR = isr;
-
-  if (isr & I2C_ERROR_MASK)
-    i2c_lld_serve_error_interrupt(&I2CD2, isr);
-  else if (isr & I2C_INT_MASK)
-    i2c_lld_serve_interrupt(&I2CD2, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#elif defined(STM32_I2C2_EVENT_HANDLER) && defined(STM32_I2C2_ERROR_HANDLER)
-CH_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) {
-  uint32_t isr = I2CD2.i2c->ISR;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Clearing IRQ bits.*/
-  I2CD2.i2c->ICR = isr & I2C_INT_MASK;
-
-  i2c_lld_serve_interrupt(&I2CD2, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-
-CH_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) {
-  uint32_t isr = I2CD2.i2c->ISR;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Clearing IRQ bits.*/
-  I2CD2.i2c->ICR = isr & I2C_ERROR_MASK;
-
-  i2c_lld_serve_error_interrupt(&I2CD2, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#else
-#error "I2C2 interrupt handlers not defined"
-#endif
-#endif /* STM32_I2C_USE_I2C2 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-#if STM32_I2C_USE_I2C1
-  i2cObjectInit(&I2CD1);
-  I2CD1.thread = NULL;
-  I2CD1.i2c    = I2C1;
-  I2CD1.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
-  I2CD1.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
-#endif /* STM32_I2C_USE_I2C1 */
-
-#if STM32_I2C_USE_I2C2
-  i2cObjectInit(&I2CD2);
-  I2CD2.thread = NULL;
-  I2CD2.i2c    = I2C2;
-  I2CD2.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
-  I2CD2.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
-#endif /* STM32_I2C_USE_I2C2 */
-}
-
-/**
- * @brief   Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-  I2C_TypeDef *dp = i2cp->i2c;
-
-  i2cp->txdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_M2P;
-  i2cp->rxdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_P2M;
-
-  /* Make sure I2C peripheral is disabled */
-  dp->CR1 &= ~I2C_CR1_PE;
-
-  /* If in stopped state then enables the I2C and DMA clocks.*/
-  if (i2cp->state == I2C_STOP) {
-
-#if STM32_I2C_USE_I2C1
-    if (&I2CD1 == i2cp) {
-      bool_t b;
-
-      rccResetI2C1();
-      b = dmaStreamAllocate(i2cp->dmarx,
-                            STM32_I2C_I2C1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated");
-      b = dmaStreamAllocate(i2cp->dmatx,
-                            STM32_I2C_I2C1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated");
-      rccEnableI2C1(FALSE);
-
-#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__)
-      nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
-#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER)
-      nvicEnableVector(STM32_I2C1_EVENT_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
-      nvicEnableVector(STM32_I2C1_ERROR_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
-#else
-#error "I2C1 interrupt numbers not defined"
-#endif
-
-      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
-                         STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
-      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
-                         STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
-    }
-#endif /* STM32_I2C_USE_I2C1 */
-
-#if STM32_I2C_USE_I2C2
-    if (&I2CD2 == i2cp) {
-      bool_t b;
-
-      rccResetI2C2();
-      b = dmaStreamAllocate(i2cp->dmarx,
-                            STM32_I2C_I2C2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated");
-      b = dmaStreamAllocate(i2cp->dmatx,
-                            STM32_I2C_I2C2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
-                            (void *)i2cp);
-      chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated");
-      rccEnableI2C2(FALSE);
-
-#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__)
-      nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
-#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER)
-      nvicEnableVector(STM32_I2C2_EVENT_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
-      nvicEnableVector(STM32_I2C2_ERROR_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
-#else
-#error "I2C2 interrupt numbers not defined"
-#endif
-
-      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
-                         STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
-      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
-                         STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
-    }
-#endif /* STM32_I2C_USE_I2C2 */
-  }
-
-  /* I2C registers pointed by the DMA.*/
-  dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR);
-  dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR);
-
-  /* Reset i2c peripheral, the TCIE bit will be handled separately.*/
-  dp->CR1 = i2cp->config->cr1 | I2C_CR1_ERRIE | I2C_CR1_STOPIE |
-            I2C_CR1_NACKIE | I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN;
-
-  /* Set slave address field (master mode) */
-  dp->CR2 = (i2cp->config->cr2 & ~I2C_CR2_SADD);
-
-  /* Setup I2C parameters.*/
-  dp->TIMINGR = i2cp->config->timingr;
-
-  /* Ready to go.*/
-  dp->CR1 |= I2C_CR1_PE;
-}
-
-/**
- * @brief   Deactivates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
-  /* If not in stopped state then disables the I2C clock.*/
-  if (i2cp->state != I2C_STOP) {
-
-    /* I2C disable.*/
-    i2c_lld_abort_operation(i2cp);
-    dmaStreamRelease(i2cp->dmatx);
-    dmaStreamRelease(i2cp->dmarx);
-
-#if STM32_I2C_USE_I2C1
-    if (&I2CD1 == i2cp) {
-#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__)
-      nvicDisableVector(STM32_I2C1_GLOBAL_NUMBER);
-#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER)
-      nvicDisableVector(STM32_I2C1_EVENT_NUMBER);
-      nvicDisableVector(STM32_I2C1_ERROR_NUMBER);
-#else
-#error "I2C1 interrupt numbers not defined"
-#endif
-
-      rccDisableI2C1(FALSE);
-    }
-#endif
-
-#if STM32_I2C_USE_I2C2
-    if (&I2CD2 == i2cp) {
-#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__)
-      nvicDisableVector(STM32_I2C2_GLOBAL_NUMBER);
-#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER)
-      nvicDisableVector(STM32_I2C2_EVENT_NUMBER);
-      nvicDisableVector(STM32_I2C2_ERROR_NUMBER);
-#else
-#error "I2C2 interrupt numbers not defined"
-#endif
-
-      rccDisableI2C2(FALSE);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Receives data via the I2C bus as master.
- * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
- *          hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                     uint8_t *rxbuf, size_t rxbytes,
-                                     systime_t timeout) {
-  I2C_TypeDef *dp = i2cp->i2c;
-  VirtualTimer vt;
-  uint32_t addr_cr2 = addr & I2C_CR2_SADD;
-
-  chDbgCheck((rxbytes > 0), "i2c_lld_master_receive_timeout");
-
-  /* Resetting error flags for this transfer.*/
-  i2cp->errors = I2CD_NO_ERROR;
-
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Waits until BUSY flag is reset and the STOP from the previous operation
-     is completed, alternatively for a timeout condition.*/
-  while (dp->ISR & I2C_ISR_BUSY) {
-    chSysLock();
-    if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-      return RDY_TIMEOUT;
-    chSysUnlock();
-  }
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Adjust slave address (master mode) for 7-bit address mode */
-  if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
-    addr_cr2 = (addr_cr2 & 0x7f) << 1;
-
-  /* Set slave address field (master mode) */
-  dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES);
-  dp->CR2 |= (rxbytes << 16) | addr_cr2;
-
-  /* Initializes driver fields */
-  i2cp->errors = 0;
-
-  /* RX DMA setup.*/
-  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
-  dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
-
-  /* Enable RX DMA */
-  dmaStreamEnable(i2cp->dmarx);
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Starts the operation.*/
-  dp->CR2 |= I2C_CR2_RD_WRN;
-  dp->CR2 |= I2C_CR2_START;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief   Transmits data via the I2C bus as master.
- * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
- *          This is hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[in] txbuf     pointer to the transmit buffer
- * @param[in] txbytes   number of bytes to be transmitted
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                      const uint8_t *txbuf, size_t txbytes,
-                                      uint8_t *rxbuf, size_t rxbytes,
-                                      systime_t timeout) {
-  I2C_TypeDef *dp = i2cp->i2c;
-  VirtualTimer vt;
-  uint32_t addr_cr2 = addr & I2C_CR2_SADD;
-
-  chDbgCheck(((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))),
-             "i2c_lld_master_transmit_timeout");
-
-  /* Resetting error flags for this transfer.*/
-  i2cp->errors = I2CD_NO_ERROR;
-
-  /* Global timeout for the whole operation.*/
-  if (timeout != TIME_INFINITE)
-    chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
-
-  /* Releases the lock from high level driver.*/
-  chSysUnlock();
-
-  /* Waits until BUSY flag is reset and the STOP from the previous operation
-     is completed, alternatively for a timeout condition.*/
-  while (dp->ISR & I2C_ISR_BUSY) {
-    chSysLock();
-    if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-      return RDY_TIMEOUT;
-    chSysUnlock();
-  }
-
-  /* This lock will be released in high level driver.*/
-  chSysLock();
-
-  /* Adjust slave address (master mode) for 7-bit address mode */
-  if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
-    addr_cr2 = (addr_cr2 & 0x7f) << 1;
-
-  /* Set slave address field (master mode) */
-  dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES);
-  dp->CR2 |= (txbytes << 16) | addr_cr2;
-
-  /* Initializes driver fields */
-  i2cp->errors = 0;
-
-  /* TX DMA setup.*/
-  dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode);
-  dmaStreamSetMemory0(i2cp->dmatx, txbuf);
-  dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
-
-  /* RX DMA setup.*/
-  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
-  dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
-
-  /* Enable TX DMA */
-  dmaStreamEnable(i2cp->dmatx);
-
-  /* Atomic check on the timer in order to make sure that a timeout didn't
-     happen outside the critical zone.*/
-  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
-    return RDY_TIMEOUT;
-
-  /* Transmission complete interrupt enabled.*/
-  dp->CR1 |= I2C_CR1_TCIE;
-
-  /* Starts the operation as the very last thing.*/
-  dp->CR2 &= ~I2C_CR2_RD_WRN;
-  dp->CR2 |= I2C_CR2_START;
-
-  /* Waits for the operation completion or a timeout.*/
-  i2cp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
-    chVTResetI(&vt);
-
-  return chThdSelf()->p_u.rdymsg;
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/I2Cv2/i2c_lld.h b/os/hal/platforms/STM32/I2Cv2/i2c_lld.h
deleted file mode 100644
index 810c7be84..000000000
--- a/os/hal/platforms/STM32/I2Cv2/i2c_lld.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    STM32/I2Cv2/i2c_lld.h
- * @brief   STM32 I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    TIMINGR register definitions
- * @{
- */
-#define STM32_TIMINGR_PRESC_MASK        (15U << 28)
-#define STM32_TIMINGR_PRESC(n)          ((n) << 28)
-#define STM32_TIMINGR_SCLDEL_MASK       (15U << 20)
-#define STM32_TIMINGR_SCLDEL(n)         ((n) << 20)
-#define STM32_TIMINGR_SDADEL_MASK       (15U << 16)
-#define STM32_TIMINGR_SDADEL(n)         ((n) << 16)
-#define STM32_TIMINGR_SCLH_MASK         (255U << 8)
-#define STM32_TIMINGR_SCLH(n)           ((n) << 8)
-#define STM32_TIMINGR_SCLL_MASK         (255U << 0)
-#define STM32_TIMINGR_SCLL(n)           ((n) << 0)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   I2C1 driver enable switch.
- * @details If set to @p TRUE the support for I2C1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define STM32_I2C_USE_I2C1                  FALSE
-#endif
-
-/**
- * @brief   I2C2 driver enable switch.
- * @details If set to @p TRUE the support for I2C2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
-#define STM32_I2C_USE_I2C2                  FALSE
-#endif
-
-/**
- * @brief   I2C1 interrupt priority level setting.
- */
-#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   I2C2 interrupt priority level setting.
- */
-#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   I2C1 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   I2C2 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   I2C DMA error hook.
- * @note    The default action for DMA errors is a system halt because DMA
- *          error can only happen because programming errors.
- */
-#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      chSysHalt()
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/* Streams for the DMA peripheral.*/
-#if defined(STM32F0XX)
-#define STM32_I2C_I2C1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_I2C_I2C1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-#define STM32_I2C_I2C2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#elif defined(STM32F30X) || defined(STM32F37X)
-#define STM32_I2C_I2C1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_I2C_I2C2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#else
-#error "device unsupported by I2Cv2 driver"
-#endif
-
-/** @brief  error checks */
-#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
-#error "I2C1 not present in the selected device"
-#endif
-
-#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2
-#error "I2C2 not present in the selected device"
-#endif
-
-#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2
-#error "I2C driver activated but no I2C peripheral assigned"
-#endif
-
-#if STM32_I2C_USE_I2C1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM,                    \
-                           STM32_I2C1_RX_DMA_MSK)
-#error "invalid DMA stream associated to I2C1 RX"
-#endif
-
-#if STM32_I2C_USE_I2C1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM,                    \
-                           STM32_I2C1_TX_DMA_MSK)
-#error "invalid DMA stream associated to I2C1 TX"
-#endif
-
-#if STM32_I2C_USE_I2C2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM,                    \
-                           STM32_I2C2_RX_DMA_MSK)
-#error "invalid DMA stream associated to I2C2 RX"
-#endif
-
-#if STM32_I2C_USE_I2C2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM,                    \
-                           STM32_I2C2_TX_DMA_MSK)
-#error "invalid DMA stream associated to I2C2 TX"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/* Check clock range. */
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing I2C address.
- */
-typedef uint16_t i2caddr_t;
-
-/**
- * @brief   I2C Driver condition flags type.
- */
-typedef uint32_t i2cflags_t;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   TIMINGR register initialization.
-   * @note    Refer to the STM32 reference manual, the values are affected
-   *          by the system clock settings in mcuconf.h.
-   */
-  uint32_t        timingr;
-  /**
-   * @brief   CR1 register initialization.
-   * @note    Leave to zero unless you know what you are doing.
-   */
-  uint32_t        cr1;
-  /**
-   * @brief   CR2 register initialization.
-   * @note    Only the ADD10 bit can eventually be specified here.
-   */
-  uint32_t        cr2;
-} I2CConfig;
-
-/**
- * @brief   Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver{
-  /**
-   * @brief   Driver state.
-   */
-  i2cstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const I2CConfig           *config;
-  /**
-   * @brief   Error flags.
-   */
-  i2cflags_t                errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
-  I2C_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Thread waiting for I/O completion.
-   */
-  Thread                    *thread;
-  /**
-   * @brief     Current slave address without R/W bit.
-   */
-  i2caddr_t                 addr;
-  /**
-   * @brief RX DMA mode bit mask.
-   */
-  uint32_t                  rxdmamode;
-  /**
-   * @brief TX DMA mode bit mask.
-   */
-  uint32_t                  txdmamode;
-  /**
-   * @brief     Receive DMA channel.
-   */
-  const stm32_dma_stream_t  *dmarx;
-  /**
-   * @brief     Transmit DMA channel.
-   */
-  const stm32_dma_stream_t  *dmatx;
-  /**
-   * @brief     Pointer to the I2Cx registers block.
-   */
-  I2C_TypeDef               *i2c;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Get errors from I2C driver.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-#if STM32_I2C_USE_I2C1
-extern I2CDriver I2CD1;
-#endif
-
-#if STM32_I2C_USE_I2C2
-extern I2CDriver I2CD2;
-#endif
-
-#endif /* !defined(__DOXYGEN__) */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void i2c_lld_init(void);
-  void i2c_lld_start(I2CDriver *i2cp);
-  void i2c_lld_stop(I2CDriver *i2cp);
-  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                        const uint8_t *txbuf, size_t txbytes,
-                                        uint8_t *rxbuf, size_t rxbytes,
-                                        systime_t timeout);
-  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                       uint8_t *rxbuf, size_t rxbytes,
-                                       systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_I2C  */
-
-#endif /* _I2C_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/OTGv1/usb_lld.c b/os/hal/platforms/STM32/OTGv1/usb_lld.c
deleted file mode 100644
index 9b1d3d489..000000000
--- a/os/hal/platforms/STM32/OTGv1/usb_lld.c
+++ /dev/null
@@ -1,1334 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/OTGv1/usb_lld.c
- * @brief   STM32 USB subsystem low level driver source.
- *
- * @addtogroup USB
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define TRDT_VALUE              5
-
-#define EP0_MAX_INSIZE          64
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief OTG_FS driver identifier.*/
-#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
-USBDriver USBD1;
-#endif
-
-/** @brief OTG_HS driver identifier.*/
-#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
-USBDriver USBD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EP0 state.
- * @note    It is an union because IN and OUT endpoints are never used at the
- *          same time for EP0.
- */
-static union {
-  /**
-   * @brief   IN EP0 state.
-   */
-  USBInEndpointState in;
-  /**
-   * @brief   OUT EP0 state.
-   */
-  USBOutEndpointState out;
-} ep0_state;
-
-/**
- * @brief   Buffer for the EP0 setup packets.
- */
-static uint8_t ep0setup_buffer[8];
-
-/**
- * @brief   EP0 initialization structure.
- */
-static const USBEndpointConfig ep0config = {
-  USB_EP_MODE_TYPE_CTRL,
-  _usb_ep0setup,
-  _usb_ep0in,
-  _usb_ep0out,
-  0x40,
-  0x40,
-  &ep0_state.in,
-  &ep0_state.out,
-  1,
-  ep0setup_buffer
-};
-
-#if STM32_USB_USE_OTG1
-static const stm32_otg_params_t fsparams = {
-  STM32_USB_OTG1_RX_FIFO_SIZE / 4,
-  STM32_OTG1_FIFO_MEM_SIZE,
-  STM32_OTG1_ENDOPOINTS_NUMBER
-};
-#endif
-
-#if STM32_USB_USE_OTG2
-static const stm32_otg_params_t hsparams = {
-  STM32_USB_OTG2_RX_FIFO_SIZE / 4,
-  STM32_OTG2_FIFO_MEM_SIZE,
-  STM32_OTG2_ENDOPOINTS_NUMBER
-};
-#endif
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Wakes up the pump thread.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-static void usb_lld_wakeup_pump(USBDriver *usbp) {
-
-  if (usbp->thd_wait != NULL) {
-    chThdResumeI(usbp->thd_wait);
-    usbp->thd_wait = NULL;
-  }
-}
-
-static void otg_core_reset(USBDriver *usbp) {
-  stm32_otg_t *otgp = usbp->otg;
-
-  halPolledDelay(32);
-
-  /* Core reset and delay of at least 3 PHY cycles.*/
-  otgp->GRSTCTL = GRSTCTL_CSRST;
-  while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
-    ;
-
-  halPolledDelay(12);
-
-  /* Wait AHB idle condition.*/
-  while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)
-    ;
-}
-
-static void otg_disable_ep(USBDriver *usbp) {
-  stm32_otg_t *otgp = usbp->otg;
-  unsigned i;
-
-  for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
-    /* Disable only if enabled because this sentence in the manual:
-       "The application must set this bit only if Endpoint Enable is
-        already set for this endpoint".*/
-    if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0) {
-      otgp->ie[i].DIEPCTL = DIEPCTL_EPDIS;
-      /* Wait for endpoint disable.*/
-      while (!(otgp->ie[i].DIEPINT & DIEPINT_EPDISD))
-        ;
-    }
-    else
-      otgp->ie[i].DIEPCTL = 0;
-    otgp->ie[i].DIEPTSIZ = 0;
-    otgp->ie[i].DIEPINT = 0xFFFFFFFF;
-    /* Disable only if enabled because this sentence in the manual:
-       "The application must set this bit only if Endpoint Enable is
-        already set for this endpoint".
-       Note that the attempt to disable the OUT EP0 is ignored by the
-       hardware but the code is simpler this way.*/
-    if ((otgp->oe[i].DOEPCTL & DOEPCTL_EPENA) != 0) {
-      otgp->oe[i].DOEPCTL = DOEPCTL_EPDIS;
-      /* Wait for endpoint disable.*/
-      while (!(otgp->oe[i].DOEPINT & DOEPINT_OTEPDIS))
-        ;
-    }
-    else
-      otgp->oe[i].DOEPCTL = 0;
-    otgp->oe[i].DOEPTSIZ = 0;
-    otgp->oe[i].DOEPINT = 0xFFFFFFFF;
-  }
-  otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
-}
-
-static void otg_rxfifo_flush(USBDriver *usbp) {
-  stm32_otg_t *otgp = usbp->otg;
-
-  otgp->GRSTCTL = GRSTCTL_RXFFLSH;
-  while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0)
-    ;
-  /* Wait for 3 PHY Clocks.*/
-  halPolledDelay(12);
-}
-
-static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) {
-  stm32_otg_t *otgp = usbp->otg;
-
-  otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH;
-  while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0)
-    ;
-  /* Wait for 3 PHY Clocks.*/
-  halPolledDelay(12);
-}
-
-/**
- * @brief   Resets the FIFO RAM memory allocator.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-static void otg_ram_reset(USBDriver *usbp) {
-
-  usbp->pmnext = usbp->otgparams->rx_fifo_size;
-}
-
-/**
- * @brief   Allocates a block from the FIFO RAM memory.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] size      size of the packet buffer to allocate in words
- *
- * @notapi
- */
-static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) {
-  uint32_t next;
-
-  next = usbp->pmnext;
-  usbp->pmnext += size;
-  chDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size,
-              "otg_fifo_alloc(), #1", "OTG FIFO memory overflow");
-  return next;
-}
-
-/**
- * @brief   Pushes a series of words into a FIFO.
- *
- * @param[in] fifop     pointer to the FIFO register
- * @param[in] buf       pointer to the words buffer, not necessarily word
- *                      aligned
- * @param[in] n         number of words to push
- *
- * @return              A pointer after the last word pushed.
- *
- * @notapi
- */
-static uint8_t *otg_do_push(volatile uint32_t *fifop, uint8_t *buf, size_t n) {
-
-  while (n > 0) {
-    /* Note, this line relies on the Cortex-M3/M4 ability to perform
-       unaligned word accesses and on the LSB-first memory organization.*/
-    *fifop = *((PACKED_VAR uint32_t *)buf);
-    buf += 4;
-    n--;
-  }
-  return buf;
-}
-
-/**
- * @brief   Writes to a TX FIFO.
- *
- * @param[in] fifop     pointer to the FIFO register
- * @param[in] buf       buffer where to copy the endpoint data
- * @param[in] n         maximum number of bytes to copy
- *
- * @notapi
- */
-static void otg_fifo_write_from_buffer(volatile uint32_t *fifop,
-                                       const uint8_t *buf,
-                                       size_t n) {
-
-  otg_do_push(fifop, (uint8_t *)buf, (n + 3) / 4);
-}
-
-/**
- * @brief   Writes to a TX FIFO fetching data from a queue.
- *
- * @param[in] fifop     pointer to the FIFO register
- * @param[in] oqp       pointer to an @p OutputQueue object
- * @param[in] n         maximum number of bytes to copy
- *
- * @notapi
- */
-static void otg_fifo_write_from_queue(volatile uint32_t *fifop,
-                                      OutputQueue *oqp,
-                                      size_t n) {
-  size_t ntogo;
-
-  ntogo = n;
-  while (ntogo > 0) {
-    uint32_t w, i;
-    size_t nw = ntogo / 4;
-
-    if (nw > 0) {
-      size_t streak;
-      uint32_t nw2end = (oqp->q_top - oqp->q_rdptr) / 4;
-
-      ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4;
-      oqp->q_rdptr = otg_do_push(fifop, oqp->q_rdptr, streak);
-      if (oqp->q_rdptr >= oqp->q_top) {
-        oqp->q_rdptr = oqp->q_buffer;
-        continue;
-      }
-    }
-
-    /* If this condition is not satisfied then there is a word lying across
-       queue circular buffer boundary or there are some remaining bytes.*/
-    if (ntogo <= 0)
-      break;
-
-    /* One byte at time.*/
-    w = 0;
-    i = 0;
-    while ((ntogo > 0) && (i < 4)) {
-      w |= (uint32_t)*oqp->q_rdptr++ << (i * 8);
-      if (oqp->q_rdptr >= oqp->q_top)
-        oqp->q_rdptr = oqp->q_buffer;
-      ntogo--;
-      i++;
-    }
-    *fifop = w;
-  }
-
-  /* Updating queue.*/
-  chSysLock();
-  oqp->q_counter += n;
-  while (notempty(&oqp->q_waiting))
-    chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
-  chSchRescheduleS();
-  chSysUnlock();
-}
-
-/**
- * @brief   Pops a series of words from a FIFO.
- *
- * @param[in] fifop     pointer to the FIFO register
- * @param[in] buf       pointer to the words buffer, not necessarily word
- *                      aligned
- * @param[in] n         number of words to push
- *
- * @return              A pointer after the last word pushed.
- *
- * @notapi
- */
-static uint8_t *otg_do_pop(volatile uint32_t *fifop, uint8_t *buf, size_t n) {
-
-  while (n > 0) {
-    uint32_t w = *fifop;
-    /* Note, this line relies on the Cortex-M3/M4 ability to perform
-       unaligned word accesses and on the LSB-first memory organization.*/
-    *((PACKED_VAR uint32_t *)buf) = w;
-    buf += 4;
-    n--;
-  }
-  return buf;
-}
-
-/**
- * @brief   Reads a packet from the RXFIFO.
- *
- * @param[in] fifop     pointer to the FIFO register
- * @param[out] buf      buffer where to copy the endpoint data
- * @param[in] n         number of bytes to pull from the FIFO
- * @param[in] max       number of bytes to copy into the buffer
- *
- * @notapi
- */
-static void otg_fifo_read_to_buffer(volatile uint32_t *fifop,
-                                    uint8_t *buf,
-                                    size_t n,
-                                    size_t max) {
-
-  n = (n + 3) / 4;
-  max = (max + 3) / 4;
-  while (n) {
-    uint32_t w = *fifop;
-    if (max) {
-      /* Note, this line relies on the Cortex-M3/M4 ability to perform
-         unaligned word accesses and on the LSB-first memory organization.*/
-      *((PACKED_VAR uint32_t *)buf) = w;
-      buf += 4;
-      max--;
-    }
-    n--;
-  }
-}
-
-/**
- * @brief   Reads a packet from the RXFIFO.
- *
- * @param[in] fifop     pointer to the FIFO register
- * @param[in] iqp       pointer to an @p InputQueue object
- * @param[in] n         number of bytes to pull from the FIFO
- *
- * @notapi
- */
-static void otg_fifo_read_to_queue(volatile uint32_t *fifop,
-                                   InputQueue *iqp,
-                                   size_t n) {
-  size_t ntogo;
-
-  ntogo = n;
-  while (ntogo > 0) {
-    uint32_t w, i;
-    size_t nw = ntogo / 4;
-
-    if (nw > 0) {
-      size_t streak;
-      uint32_t nw2end = (iqp->q_wrptr - iqp->q_wrptr) / 4;
-
-      ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4;
-      iqp->q_wrptr = otg_do_pop(fifop, iqp->q_wrptr, streak);
-      if (iqp->q_wrptr >= iqp->q_top) {
-        iqp->q_wrptr = iqp->q_buffer;
-        continue;
-      }
-    }
-
-    /* If this condition is not satisfied then there is a word lying across
-       queue circular buffer boundary or there are some remaining bytes.*/
-    if (ntogo <= 0)
-      break;
-
-    /* One byte at time.*/
-    w = *fifop;
-    i = 0;
-    while ((ntogo > 0) && (i < 4)) {
-      *iqp->q_wrptr++ = (uint8_t)(w >> (i * 8));
-      if (iqp->q_wrptr >= iqp->q_top)
-        iqp->q_wrptr = iqp->q_buffer;
-      ntogo--;
-      i++;
-    }
-  }
-
-  /* Updating queue.*/
-  chSysLock();
-  iqp->q_counter += n;
-  while (notempty(&iqp->q_waiting))
-    chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK;
-  chSchRescheduleS();
-  chSysUnlock();
-}
-
-/**
- * @brief   Incoming packets handler.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-static void otg_rxfifo_handler(USBDriver *usbp) {
-  uint32_t sts, cnt, ep;
-
-  sts = usbp->otg->GRXSTSP;
-  switch (sts & GRXSTSP_PKTSTS_MASK) {
-  case GRXSTSP_SETUP_COMP:
-    break;
-  case GRXSTSP_SETUP_DATA:
-    cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
-    ep  = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
-    otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->setup_buf,
-                            cnt, 8);
-    break;
-  case GRXSTSP_OUT_DATA:
-    cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
-    ep  = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
-    if (usbp->epc[ep]->out_state->rxqueued) {
-      /* Queue associated.*/
-      otg_fifo_read_to_queue(usbp->otg->FIFO[0],
-                             usbp->epc[ep]->out_state->mode.queue.rxqueue,
-                             cnt);
-    }
-    else {
-      otg_fifo_read_to_buffer(usbp->otg->FIFO[0],
-                              usbp->epc[ep]->out_state->mode.linear.rxbuf,
-                              cnt,
-                              usbp->epc[ep]->out_state->rxsize -
-                              usbp->epc[ep]->out_state->rxcnt);
-      usbp->epc[ep]->out_state->mode.linear.rxbuf += cnt;
-    }
-    usbp->epc[ep]->out_state->rxcnt += cnt;
-    break;
-  case GRXSTSP_OUT_GLOBAL_NAK:
-  case GRXSTSP_OUT_COMP:
-  default:
-    ;
-  }
-}
-
-/**
- * @brief   Outgoing packets handler.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-static bool_t otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
-
-  /* The TXFIFO is filled until there is space and data to be transmitted.*/
-  while (TRUE) {
-    uint32_t n;
-
-    /* Transaction end condition.*/
-    if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize)
-      return TRUE;
-
-    /* Number of bytes remaining in current transaction.*/
-    n = usbp->epc[ep]->in_state->txsize - usbp->epc[ep]->in_state->txcnt;
-    if (n > usbp->epc[ep]->in_maxsize)
-      n = usbp->epc[ep]->in_maxsize;
-
-    /* Checks if in the TXFIFO there is enough space to accommodate the
-       next packet.*/
-    if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n)
-      return FALSE;
-
-#if STM32_USB_OTGFIFO_FILL_BASEPRI
-    __set_BASEPRI(CORTEX_PRIORITY_MASK(STM32_USB_OTGFIFO_FILL_BASEPRI));
-#endif
-    /* Handles the two cases: linear buffer or queue.*/
-    if (usbp->epc[ep]->in_state->txqueued) {
-      /* Queue associated.*/
-      otg_fifo_write_from_queue(usbp->otg->FIFO[ep],
-                                usbp->epc[ep]->in_state->mode.queue.txqueue,
-                                n);
-    }
-    else {
-      /* Linear buffer associated.*/
-      otg_fifo_write_from_buffer(usbp->otg->FIFO[ep],
-                                 usbp->epc[ep]->in_state->mode.linear.txbuf,
-                                 n);
-      usbp->epc[ep]->in_state->mode.linear.txbuf += n;
-    }
-    usbp->epc[ep]->in_state->txcnt += n;
-  }
-#if STM32_USB_OTGFIFO_FILL_BASEPRI
-  __set_BASEPRI(0);
-#endif
-}
-
-/**
- * @brief   Generic endpoint IN handler.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
-  stm32_otg_t *otgp = usbp->otg;
-  uint32_t epint = otgp->ie[ep].DIEPINT;
-
-  otgp->ie[ep].DIEPINT = epint;
-
-  if (epint & DIEPINT_TOC) {
-    /* Timeouts not handled yet, not sure how to handle.*/
-  }
-  if ((epint & DIEPINT_XFRC) && (otgp->DIEPMSK & DIEPMSK_XFRCM)) {
-    /* Transmit transfer complete.*/
-    USBInEndpointState *isp = usbp->epc[ep]->in_state;
-
-    if (isp->txsize < isp->totsize) {
-      /* In case the transaction covered only part of the total transfer
-         then another transaction is immediately started in order to
-         cover the remaining.*/
-      isp->txsize = isp->totsize - isp->txsize;
-      isp->txcnt  = 0;
-      usb_lld_prepare_transmit(usbp, ep);
-      chSysLockFromIsr();
-      usb_lld_start_in(usbp, ep);
-      chSysUnlockFromIsr();
-    }
-    else {
-      /* End on IN transfer.*/
-      _usb_isr_invoke_in_cb(usbp, ep);
-    }
-  }
-  if ((epint & DIEPINT_TXFE) &&
-      (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) {
-    /* The thread is made ready, it will be scheduled on ISR exit.*/
-    chSysLockFromIsr();
-    usbp->txpending |= (1 << ep);
-    otgp->DIEPEMPMSK &= ~(1 << ep);
-    usb_lld_wakeup_pump(usbp);
-    chSysUnlockFromIsr();
-  }
-}
-
-/**
- * @brief   Generic endpoint OUT handler.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
-  stm32_otg_t *otgp = usbp->otg;
-  uint32_t epint = otgp->oe[ep].DOEPINT;
-
-  /* Resets all EP IRQ sources.*/
-  otgp->oe[ep].DOEPINT = epint;
-
-  if ((epint & DOEPINT_STUP) && (otgp->DOEPMSK & DOEPMSK_STUPM)) {
-    /* Setup packets handling, setup packets are handled using a
-       specific callback.*/
-    _usb_isr_invoke_setup_cb(usbp, ep);
-
-  }
-  if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) {
-    /* Receive transfer complete.*/
-    _usb_isr_invoke_out_cb(usbp, ep);
-  }
-}
-
-/**
- * @brief   OTG shared ISR.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-static void usb_lld_serve_interrupt(USBDriver *usbp) {
-  stm32_otg_t *otgp = usbp->otg;
-  uint32_t sts, src;
-
-  sts = otgp->GINTSTS & otgp->GINTMSK;
-  otgp->GINTSTS = sts;
-
-  /* Reset interrupt handling.*/
-  if (sts & GINTSTS_USBRST) {
-    _usb_reset(usbp);
-    _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
-  }
-
-  /* Enumeration done.*/
-  if (sts & GINTSTS_ENUMDNE) {
-    (void)otgp->DSTS;
-  }
-
-  /* SOF interrupt handling.*/
-  if (sts & GINTSTS_SOF) {
-    _usb_isr_invoke_sof_cb(usbp);
-  }
-
-  /* RX FIFO not empty handling.*/
-  if (sts & GINTSTS_RXFLVL) {
-    /* The interrupt is masked while the thread has control or it would
-       be triggered again.*/
-    chSysLockFromIsr();
-    otgp->GINTMSK &= ~GINTMSK_RXFLVLM;
-    usb_lld_wakeup_pump(usbp);
-    chSysUnlockFromIsr();
-  }
-
-  /* IN/OUT endpoints event handling.*/
-  src = otgp->DAINT;
-  if (sts & GINTSTS_IEPINT) {
-    if (src & (1 << 0))
-      otg_epin_handler(usbp, 0);
-    if (src & (1 << 1))
-      otg_epin_handler(usbp, 1);
-    if (src & (1 << 2))
-      otg_epin_handler(usbp, 2);
-    if (src & (1 << 3))
-      otg_epin_handler(usbp, 3);
-#if STM32_USB_USE_OTG2
-    if (src & (1 << 4))
-      otg_epin_handler(usbp, 4);
-    if (src & (1 << 5))
-      otg_epin_handler(usbp, 5);
-#endif
-  }
-  if (sts & GINTSTS_OEPINT) {
-    if (src & (1 << 16))
-      otg_epout_handler(usbp, 0);
-    if (src & (1 << 17))
-      otg_epout_handler(usbp, 1);
-    if (src & (1 << 18))
-      otg_epout_handler(usbp, 2);
-    if (src & (1 << 19))
-      otg_epout_handler(usbp, 3);
-#if STM32_USB_USE_OTG2
-    if (src & (1 << 20))
-      otg_epout_handler(usbp, 4);
-    if (src & (1 << 21))
-      otg_epout_handler(usbp, 5);
-#endif
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers and threads.                                    */
-/*===========================================================================*/
-
-static msg_t usb_lld_pump(void *p) {
-  USBDriver *usbp = (USBDriver *)p;
-  stm32_otg_t *otgp = usbp->otg;
-
-  chRegSetThreadName("usb_lld_pump");
-  chSysLock();
-  while (TRUE) {
-    usbep_t ep;
-    uint32_t epmask;
-
-    /* Nothing to do, going to sleep.*/
-    if ((usbp->state == USB_STOP) ||
-        ((usbp->txpending == 0) && !(otgp->GINTSTS & GINTSTS_RXFLVL))) {
-      otgp->GINTMSK |= GINTMSK_RXFLVLM;
-      usbp->thd_wait = chThdSelf();
-      chSchGoSleepS(THD_STATE_SUSPENDED);
-    }
-    chSysUnlock();
-
-    /* Checks if there are TXFIFOs to be filled.*/
-    for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
-
-      /* Empties the RX FIFO.*/
-      while (otgp->GINTSTS & GINTSTS_RXFLVL) {
-        otg_rxfifo_handler(usbp);
-      }
-
-      epmask = (1 << ep);
-      if (usbp->txpending & epmask) {
-        bool_t done;
-
-        chSysLock();
-        /* USB interrupts are globally *suspended* because the peripheral
-           does not allow any interference during the TX FIFO filling
-           operation.
-           Synopsys document: DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG)
-             "The application has to finish writing one complete packet before
-              switching to a different channel/endpoint FIFO. Violating this
-              rule results in an error.".*/
-        otgp->GAHBCFG &= ~GAHBCFG_GINTMSK;
-        usbp->txpending &= ~epmask;
-        chSysUnlock();
-
-        done = otg_txfifo_handler(usbp, ep);
-
-        chSysLock();
-        otgp->GAHBCFG |= GAHBCFG_GINTMSK;
-        if (!done)
-          otgp->DIEPEMPMSK |= epmask;
-        chSysUnlock();
-      }
-    }
-    chSysLock();
-  }
-  chSysUnlock();
-  return 0;
-}
-
-#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
-#if !defined(STM32_OTG1_HANDLER)
-#error "STM32_OTG1_HANDLER not defined"
-#endif
-/**
- * @brief   OTG1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_OTG1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  usb_lld_serve_interrupt(&USBD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
-#if !defined(STM32_OTG2_HANDLER)
-#error "STM32_OTG2_HANDLER not defined"
-#endif
-/**
- * @brief   OTG2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_OTG2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  usb_lld_serve_interrupt(&USBD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level USB driver initialization.
- *
- * @notapi
- */
-void usb_lld_init(void) {
-
-  /* Driver initialization.*/
-#if STM32_USB_USE_OTG1
-  usbObjectInit(&USBD1);
-  USBD1.thd_ptr   = NULL;
-  USBD1.thd_wait  = NULL;
-  USBD1.otg       = OTG_FS;
-  USBD1.otgparams = &fsparams;
-
-  /* Filling the thread working area here because the function
-     @p chThdCreateI() does not do it.*/
-#if CH_DBG_FILL_THREADS
-  {
-    void *wsp = USBD1.wa_pump;
-    _thread_memfill((uint8_t *)wsp,
-                    (uint8_t *)wsp + sizeof(Thread),
-                    CH_THREAD_FILL_VALUE);
-    _thread_memfill((uint8_t *)wsp + sizeof(Thread),
-                    (uint8_t *)wsp + sizeof(USBD1.wa_pump) - sizeof(Thread),
-                    CH_STACK_FILL_VALUE);
-  }
-#endif
-#endif
-
-#if STM32_USB_USE_OTG2
-  usbObjectInit(&USBD2);
-  USBD2.thd_ptr   = NULL;
-  USBD2.thd_wait  = NULL;
-  USBD2.otg       = OTG_HS;
-  USBD2.otgparams = &hsparams;
-
-  /* Filling the thread working area here because the function
-     @p chThdCreateI() does not do it.*/
-#if CH_DBG_FILL_THREADS
-  {
-    void *wsp = USBD2.wa_pump;
-    _thread_memfill((uint8_t *)wsp,
-                    (uint8_t *)wsp + sizeof(Thread),
-                    CH_THREAD_FILL_VALUE);
-    _thread_memfill((uint8_t *)wsp + sizeof(Thread),
-                    (uint8_t *)wsp + sizeof(USBD2.wa_pump) - sizeof(Thread),
-                    CH_STACK_FILL_VALUE);
-  }
-#endif
-#endif
-}
-
-/**
- * @brief   Configures and activates the USB peripheral.
- * @note    Starting the OTG cell can be a slow operation carried out with
- *          interrupts disabled, perform it before starting time-critical
- *          operations.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_start(USBDriver *usbp) {
-  stm32_otg_t *otgp = usbp->otg;
-
-  if (usbp->state == USB_STOP) {
-    /* Clock activation.*/
-#if STM32_USB_USE_OTG1
-    if (&USBD1 == usbp) {
-      /* OTG FS clock enable and reset.*/
-      rccEnableOTG_FS(FALSE);
-      rccResetOTG_FS();
-
-      /* Enables IRQ vector.*/
-      nvicEnableVector(STM32_OTG1_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_USB_OTG1_IRQ_PRIORITY));
-    }
-#endif
-#if STM32_USB_USE_OTG2
-    if (&USBD2 == usbp) {
-      /* OTG HS clock enable and reset.*/
-      rccEnableOTG_HS(FALSE);
-      rccResetOTG_HS();
-
-      /* Workaround for the problem described here:
-         http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798 */
-      rccDisableOTG_HSULPI(TRUE);
-
-      /* Enables IRQ vector.*/
-      nvicEnableVector(STM32_OTG2_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_USB_OTG2_IRQ_PRIORITY));
-    }
-#endif
-
-    /* Creates the data pump threads in a suspended state. Note, it is
-       created only once, the first time @p usbStart() is invoked.*/
-    usbp->txpending = 0;
-    if (usbp->thd_ptr == NULL)
-      usbp->thd_ptr = usbp->thd_wait = chThdCreateI(usbp->wa_pump,
-                                                    sizeof usbp->wa_pump,
-                                                    STM32_USB_OTG_THREAD_PRIO,
-                                                    usb_lld_pump,
-                                                    usbp);
-
-    /* - Forced device mode.
-       - USB turn-around time = TRDT_VALUE.
-       - Full Speed 1.1 PHY.*/
-    otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE) | GUSBCFG_PHYSEL;
-
-    /* 48MHz 1.1 PHY.*/
-    otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11;
-
-    /* PHY enabled.*/
-    otgp->PCGCCTL = 0;
-
-    /* Internal FS PHY activation.*/
-#if defined(BOARD_OTG_NOVBUSSENS)
-    otgp->GCCFG = GCCFG_NOVBUSSENS | GCCFG_VBUSASEN | GCCFG_VBUSBSEN |
-                  GCCFG_PWRDWN;
-#else
-    otgp->GCCFG = GCCFG_VBUSASEN | GCCFG_VBUSBSEN | GCCFG_PWRDWN;
-#endif
-
-    /* Soft core reset.*/
-    otg_core_reset(usbp);
-
-    /* Interrupts on TXFIFOs half empty.*/
-    otgp->GAHBCFG = 0;
-
-    /* Endpoints re-initialization.*/
-    otg_disable_ep(usbp);
-
-    /* Clear all pending Device Interrupts, only the USB Reset interrupt
-       is required initially.*/
-    otgp->DIEPMSK  = 0;
-    otgp->DOEPMSK  = 0;
-    otgp->DAINTMSK = 0;
-    if (usbp->config->sof_cb == NULL)
-      otgp->GINTMSK  = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM |
-                       GINTMSK_ESUSPM  |*/;
-    else
-      otgp->GINTMSK  = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM |
-                       GINTMSK_ESUSPM */ | GINTMSK_SOFM;
-    otgp->GINTSTS  = 0xFFFFFFFF;         /* Clears all pending IRQs, if any. */
-
-    /* Global interrupts enable.*/
-    otgp->GAHBCFG |= GAHBCFG_GINTMSK;
-  }
-}
-
-/**
- * @brief   Deactivates the USB peripheral.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_stop(USBDriver *usbp) {
-  stm32_otg_t *otgp = usbp->otg;
-
-  /* If in ready state then disables the USB clock.*/
-  if (usbp->state != USB_STOP) {
-
-    /* Disabling all endpoints in case the driver has been stopped while
-       active.*/
-    otg_disable_ep(usbp);
-
-    usbp->txpending = 0;
-
-    otgp->DAINTMSK   = 0;
-    otgp->GAHBCFG    = 0;
-    otgp->GCCFG      = 0;
-
-#if STM32_USB_USE_USB1
-    if (&USBD1 == usbp) {
-      nvicDisableVector(STM32_OTG1_NUMBER);
-      rccDisableOTG1(FALSE);
-    }
-#endif
-
-#if STM32_USB_USE_USB2
-    if (&USBD2 == usbp) {
-      nvicDisableVector(STM32_OTG2_NUMBER);
-      rccDisableOTG2(FALSE);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   USB low level reset routine.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_reset(USBDriver *usbp) {
-  unsigned i;
-  stm32_otg_t *otgp = usbp->otg;
-
-  /* Flush the Tx FIFO.*/
-  otg_txfifo_flush(usbp, 0);
-
-  /* All endpoints in NAK mode, interrupts cleared.*/
-  for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
-    otgp->ie[i].DIEPCTL = DIEPCTL_SNAK;
-    otgp->oe[i].DOEPCTL = DOEPCTL_SNAK;
-    otgp->ie[i].DIEPINT = 0xFF;
-    otgp->oe[i].DOEPINT = 0xFF;
-  }
-
-  /* Endpoint interrupts all disabled and cleared.*/
-  otgp->DAINT = 0xFFFFFFFF;
-  otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
-
-  /* Resets the FIFO memory allocator.*/
-  otg_ram_reset(usbp);
-
-  /* Receive FIFO size initialization, the address is always zero.*/
-  otgp->GRXFSIZ = usbp->otgparams->rx_fifo_size;
-  otg_rxfifo_flush(usbp);
-
-  /* Resets the device address to zero.*/
-  otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0);
-
-  /* Enables also EP-related interrupt sources.*/
-  otgp->GINTMSK  |= GINTMSK_RXFLVLM | GINTMSK_OEPM  | GINTMSK_IEPM;
-  otgp->DIEPMSK   = DIEPMSK_TOCM    | DIEPMSK_XFRCM;
-  otgp->DOEPMSK   = DOEPMSK_STUPM   | DOEPMSK_XFRCM;
-
-  /* EP0 initialization, it is a special case.*/
-  usbp->epc[0] = &ep0config;
-  otgp->oe[0].DOEPTSIZ = 0;
-  otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL |
-                        DOEPCTL_MPSIZ(ep0config.out_maxsize);
-  otgp->ie[0].DIEPTSIZ = 0;
-  otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL |
-                        DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize);
-  otgp->DIEPTXF0 = DIEPTXF_INEPTXFD(ep0config.in_maxsize / 4) |
-                   DIEPTXF_INEPTXSA(otg_ram_alloc(usbp,
-                                                  ep0config.in_maxsize / 4));
-}
-
-/**
- * @brief   Sets the USB address.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_set_address(USBDriver *usbp) {
-  stm32_otg_t *otgp = usbp->otg;
-
-  otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address);
-}
-
-/**
- * @brief   Enables an endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
-  uint32_t ctl, fsize;
-  stm32_otg_t *otgp = usbp->otg;
-
-  /* IN and OUT common parameters.*/
-  switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) {
-  case USB_EP_MODE_TYPE_CTRL:
-    ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL;
-    break;
-  case USB_EP_MODE_TYPE_ISOC:
-    ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO;
-    break;
-  case USB_EP_MODE_TYPE_BULK:
-    ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK;
-    break;
-  case USB_EP_MODE_TYPE_INTR:
-    ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR;
-    break;
-  default:
-    return;
-  }
-
-  /* OUT endpoint activation or deactivation.*/
-  otgp->oe[ep].DOEPTSIZ = 0;
-  if (usbp->epc[ep]->out_cb != NULL) {
-    otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize);
-    otgp->DAINTMSK |= DAINTMSK_OEPM(ep);
-  }
-  else {
-    otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP;
-    otgp->DAINTMSK &= ~DAINTMSK_OEPM(ep);
-  }
-
-  /* IN endpoint activation or deactivation.*/
-  otgp->ie[ep].DIEPTSIZ = 0;
-  if (usbp->epc[ep]->in_cb != NULL) {
-    /* FIFO allocation for the IN endpoint.*/
-    fsize = usbp->epc[ep]->in_maxsize / 4;
-    if (usbp->epc[ep]->in_multiplier > 1)
-      fsize *= usbp->epc[ep]->in_multiplier;
-    otgp->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFD(fsize) |
-                            DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, fsize));
-    otg_txfifo_flush(usbp, ep);
-
-    otgp->ie[ep].DIEPCTL = ctl |
-                           DIEPCTL_TXFNUM(ep) |
-                           DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize);
-    otgp->DAINTMSK |= DAINTMSK_IEPM(ep);
-  }
-  else {
-    otgp->DIEPTXF[ep - 1] = 0x02000400; /* Reset value.*/
-    otg_txfifo_flush(usbp, ep);
-    otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP;
-    otgp->DAINTMSK &= ~DAINTMSK_IEPM(ep);
-  }
-}
-
-/**
- * @brief   Disables all the active endpoints except the endpoint zero.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_disable_endpoints(USBDriver *usbp) {
-
-  /* Resets the FIFO memory allocator.*/
-  otg_ram_reset(usbp);
-
-  /* Disabling all endpoints.*/
-  otg_disable_ep(usbp);
-}
-
-/**
- * @brief   Returns the status of an OUT endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED  The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE   The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
-  uint32_t ctl;
-
-  (void)usbp;
-
-  ctl = usbp->otg->oe[ep].DOEPCTL;
-  if (!(ctl & DOEPCTL_USBAEP))
-    return EP_STATUS_DISABLED;
-  if (ctl & DOEPCTL_STALL)
-    return EP_STATUS_STALLED;
-  return EP_STATUS_ACTIVE;
-}
-
-/**
- * @brief   Returns the status of an IN endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED  The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE   The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
-  uint32_t ctl;
-
-  (void)usbp;
-
-  ctl = usbp->otg->ie[ep].DIEPCTL;
-  if (!(ctl & DIEPCTL_USBAEP))
-    return EP_STATUS_DISABLED;
-  if (ctl & DIEPCTL_STALL)
-    return EP_STATUS_STALLED;
-  return EP_STATUS_ACTIVE;
-}
-
-/**
- * @brief   Reads a setup packet from the dedicated packet buffer.
- * @details This function must be invoked in the context of the @p setup_cb
- *          callback in order to read the received setup packet.
- * @pre     In order to use this function the endpoint must have been
- *          initialized as a control endpoint.
- * @post    The endpoint is ready to accept another packet.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @param[out] buf      buffer where to copy the packet data
- *
- * @notapi
- */
-void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
-
-  memcpy(buf, usbp->epc[ep]->setup_buf, 8);
-}
-
-/**
- * @brief   Prepares for a receive operation.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
-  uint32_t pcnt;
-  USBOutEndpointState *osp = usbp->epc[ep]->out_state;
-
-  /* Transfer initialization.*/
-  pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
-         usbp->epc[ep]->out_maxsize;
-  usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) |
-                               DOEPTSIZ_XFRSIZ(osp->rxsize);
-
-}
-
-/**
- * @brief   Prepares for a transmit operation.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
-  USBInEndpointState *isp = usbp->epc[ep]->in_state;
-
-  /* Transfer initialization.*/
-  isp->totsize = isp->txsize;
-  if (isp->txsize == 0) {
-    /* Special case, sending zero size packet.*/
-    usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0);
-  }
-  else {
-    if ((ep == 0) && (isp->txsize  > EP0_MAX_INSIZE))
-      isp->txsize = EP0_MAX_INSIZE;
-
-    /* Normal case.*/
-    uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) /
-                    usbp->epc[ep]->in_maxsize;
-    usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(pcnt) |
-                                 DIEPTSIZ_XFRSIZ(isp->txsize);
-  }
-}
-
-/**
- * @brief   Starts a receive operation on an OUT endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
-
-  usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_CNAK;
-}
-
-/**
- * @brief   Starts a transmit operation on an IN endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
-
-  usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
-  usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep);
-}
-
-/**
- * @brief   Brings an OUT endpoint in the stalled state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
-
-  usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_STALL;
-}
-
-/**
- * @brief   Brings an IN endpoint in the stalled state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
-
-  usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_STALL;
-}
-
-/**
- * @brief   Brings an OUT endpoint in the active state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
-
-  usbp->otg->oe[ep].DOEPCTL &= ~DOEPCTL_STALL;
-}
-
-/**
- * @brief   Brings an IN endpoint in the active state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
-
-  usbp->otg->ie[ep].DIEPCTL &= ~DIEPCTL_STALL;
-}
-
-#endif /* HAL_USE_USB */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/OTGv1/usb_lld.h b/os/hal/platforms/STM32/OTGv1/usb_lld.h
deleted file mode 100644
index 2dae8c2ba..000000000
--- a/os/hal/platforms/STM32/OTGv1/usb_lld.h
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/OTGv1/usb_lld.h
- * @brief   STM32 USB subsystem low level driver header.
- *
- * @addtogroup USB
- * @{
- */
-
-#ifndef _USB_LLD_H_
-#define _USB_LLD_H_
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-#include "stm32_otg.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Maximum endpoint address.
- */
-#if !STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
-#define USB_MAX_ENDPOINTS                   3
-#else
-#define USB_MAX_ENDPOINTS                   5
-#endif
-
-/**
- * @brief   Status stage handling method.
- */
-#define USB_EP0_STATUS_STAGE                USB_EP0_STATUS_STAGE_SW
-
-/**
- * @brief   The address can be changed immediately upon packet reception.
- */
-#define USB_SET_ADDRESS_MODE                USB_EARLY_SET_ADDRESS
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   OTG1 driver enable switch.
- * @details If set to @p TRUE the support for OTG_FS is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_USB_USE_OTG1) || defined(__DOXYGEN__)
-#define STM32_USB_USE_OTG1                  FALSE
-#endif
-
-/**
- * @brief   OTG2 driver enable switch.
- * @details If set to @p TRUE the support for OTG_HS is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_USB_USE_OTG2) || defined(__DOXYGEN__)
-#define STM32_USB_USE_OTG2                  FALSE
-#endif
-
-/**
- * @brief   OTG1 interrupt priority level setting.
- */
-#if !defined(STM32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USB_OTG1_IRQ_PRIORITY         14
-#endif
-
-/**
- * @brief   OTG2 interrupt priority level setting.
- */
-#if !defined(STM32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USB_OTG2_IRQ_PRIORITY         14
-#endif
-
-/**
- * @brief   OTG1 RX shared FIFO size.
- * @note    Must be a multiple of 4.
- */
-#if !defined(STM32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__)
-#define STM32_USB_OTG1_RX_FIFO_SIZE         512
-#endif
-
-/**
- * @brief   OTG2 RX shared FIFO size.
- * @note    Must be a multiple of 4.
- */
-#if !defined(STM32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__)
-#define STM32_USB_OTG2_RX_FIFO_SIZE         1024
-#endif
-
-/**
- * @brief   Dedicated data pump threads priority.
- */
-#if !defined(STM32_USB_OTG_THREAD_PRIO) || defined(__DOXYGEN__)
-#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
-#endif
-
-/**
- * @brief   Dedicated data pump threads stack size.
- */
-#if !defined(STM32_USB_OTG_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
-#define STM32_USB_OTG_THREAD_STACK_SIZE     128
-#endif
-
-/**
- * @brief   Exception priority level during TXFIFOs operations.
- * @note    Because an undocumented silicon behavior the operation of
- *          copying a packet into a TXFIFO must not be interrupted by
- *          any other operation on the OTG peripheral.
- *          This parameter represents the priority mask during copy
- *          operations. The default value only allows to call USB
- *          functions from callbacks invoked from USB ISR handlers.
- *          If you need to invoke USB functions from other handlers
- *          then raise this priority mast to the same level of the
- *          handler you need to use.
- * @note    The value zero means disabled, when disabled calling USB
- *          functions is only safe from thread level or from USB
- *          callbacks.
- */
-#if !defined(STM32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__)
-#define STM32_USB_OTGFIFO_FILL_BASEPRI      0
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_USB_USE_OTG1 && !STM32_HAS_OTG1
-#error "OTG1 not present in the selected device"
-#endif
-
-#if STM32_USB_USE_OTG2 && !STM32_HAS_OTG2
-#error "OTG2 not present in the selected device"
-#endif
-
-#if !STM32_USB_USE_OTG1 && !STM32_USB_USE_OTG2
-#error "USB driver activated but no USB peripheral assigned"
-#endif
-
-#if STM32_USB_USE_OTG1 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to OTG1"
-#endif
-
-#if STM32_USB_USE_OTG2 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to OTG2"
-#endif
-
-#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0
-#error "OTG1 RX FIFO size must be a multiple of 4"
-#endif
-
-#if (STM32_USB_OTG2_RX_FIFO_SIZE & 3) != 0
-#error "OTG2 RX FIFO size must be a multiple of 4"
-#endif
-
-#if defined(STM32F4XX) || defined(STM32F2XX)
-#define STM32_USBCLK                        STM32_PLL48CLK
-#elif defined(STM32F10X_CL)
-#define STM32_USBCLK                        STM32_OTGFSCLK
-#else
-#error "unsupported STM32 platform for OTG functionality"
-#endif
-
-#if STM32_USBCLK != 48000000
-#error "the USB OTG driver requires a 48MHz clock"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Peripheral-specific parameters block.
- */
-typedef struct {
-  uint32_t                      rx_fifo_size;
-  uint32_t                      otg_ram_size;
-  uint32_t                      num_endpoints;
-} stm32_otg_params_t;
-
-/**
- * @brief   Type of an IN endpoint state structure.
- */
-typedef struct {
-  /**
-   * @brief   Buffer mode, queue or linear.
-   */
-  bool_t                        txqueued;
-  /**
-   * @brief   Requested transmit transfer size.
-   */
-  size_t                        txsize;
-  /**
-   * @brief   Transmitted bytes so far.
-   */
-  size_t                        txcnt;
-  union {
-    struct {
-      /**
-       * @brief   Pointer to the transmission linear buffer.
-       */
-      const uint8_t             *txbuf;
-    } linear;
-    struct {
-      /**
-       * @brief   Pointer to the output queue.
-       */
-      OutputQueue               *txqueue;
-    } queue;
-  } mode;
-  /**
-   * @brief   Total transmit transfer size.
-   */
-  size_t                        totsize;
-} USBInEndpointState;
-
-/**
- * @brief   Type of an OUT endpoint state structure.
- */
-typedef struct {
-  /**
-   * @brief   Buffer mode, queue or linear.
-   */
-  bool_t                        rxqueued;
-  /**
-   * @brief   Requested receive transfer size.
-   */
-  size_t                        rxsize;
-  /**
-   * @brief   Received bytes so far.
-   */
-  size_t                        rxcnt;
-  union {
-    struct {
-      /**
-       * @brief   Pointer to the receive linear buffer.
-       */
-      uint8_t                   *rxbuf;
-    } linear;
-    struct {
-      /**
-       * @brief   Pointer to the input queue.
-       */
-      InputQueue               *rxqueue;
-    } queue;
-  } mode;
-} USBOutEndpointState;
-
-/**
- * @brief   Type of an USB endpoint configuration structure.
- * @note    Platform specific restrictions may apply to endpoints.
- */
-typedef struct {
-  /**
-   * @brief   Type and mode of the endpoint.
-   */
-  uint32_t                      ep_mode;
-  /**
-   * @brief   Setup packet notification callback.
-   * @details This callback is invoked when a setup packet has been
-   *          received.
-   * @post    The application must immediately call @p usbReadPacket() in
-   *          order to access the received packet.
-   * @note    This field is only valid for @p USB_EP_MODE_TYPE_CTRL
-   *          endpoints, it should be set to @p NULL for other endpoint
-   *          types.
-   */
-  usbepcallback_t               setup_cb;
-  /**
-   * @brief   IN endpoint notification callback.
-   * @details This field must be set to @p NULL if the IN endpoint is not
-   *          used.
-   */
-  usbepcallback_t               in_cb;
-  /**
-   * @brief   OUT endpoint notification callback.
-   * @details This field must be set to @p NULL if the OUT endpoint is not
-   *          used.
-   */
-  usbepcallback_t               out_cb;
-  /**
-   * @brief   IN endpoint maximum packet size.
-   * @details This field must be set to zero if the IN endpoint is not
-   *          used.
-   */
-  uint16_t                      in_maxsize;
-  /**
-   * @brief   OUT endpoint maximum packet size.
-   * @details This field must be set to zero if the OUT endpoint is not
-   *          used.
-   */
-  uint16_t                      out_maxsize;
-  /**
-   * @brief   @p USBEndpointState associated to the IN endpoint.
-   * @details This structure maintains the state of the IN endpoint.
-   */
-  USBInEndpointState            *in_state;
-  /**
-   * @brief   @p USBEndpointState associated to the OUT endpoint.
-   * @details This structure maintains the state of the OUT endpoint.
-   */
-  USBOutEndpointState           *out_state;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Determines the space allocated for the TXFIFO as multiples of
-   *          the packet size (@p in_maxsize). Note that zero is interpreted
-   *          as one for simplicity and robustness.
-   */
-  uint16_t                      in_multiplier;
-  /**
-   * @brief   Pointer to a buffer for setup packets.
-   * @details Setup packets require a dedicated 8-bytes buffer, set this
-   *          field to @p NULL for non-control endpoints.
-   */
-  uint8_t                       *setup_buf;
-} USBEndpointConfig;
-
-/**
- * @brief   Type of an USB driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   USB events callback.
-   * @details This callback is invoked when an USB driver event is registered.
-   */
-  usbeventcb_t                  event_cb;
-  /**
-   * @brief   Device GET_DESCRIPTOR request callback.
-   * @note    This callback is mandatory and cannot be set to @p NULL.
-   */
-  usbgetdescriptor_t            get_descriptor_cb;
-  /**
-   * @brief   Requests hook callback.
-   * @details This hook allows to be notified of standard requests or to
-   *          handle non standard requests.
-   */
-  usbreqhandler_t               requests_hook_cb;
-  /**
-   * @brief   Start Of Frame callback.
-   */
-  usbcallback_t                 sof_cb;
-  /* End of the mandatory fields.*/
-} USBConfig;
-
-/**
- * @brief   Structure representing an USB driver.
- */
-struct USBDriver {
-  /**
-   * @brief   Driver state.
-   */
-  usbstate_t                    state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const USBConfig               *config;
-  /**
-   * @brief   Bit map of the transmitting IN endpoints.
-   */
-  uint16_t                      transmitting;
-  /**
-   * @brief   Bit map of the receiving OUT endpoints.
-   */
-  uint16_t                      receiving;
-  /**
-   * @brief   Active endpoints configurations.
-   */
-  const USBEndpointConfig       *epc[USB_MAX_ENDPOINTS + 1];
-  /**
-   * @brief   Fields available to user, it can be used to associate an
-   *          application-defined handler to an IN endpoint.
-   * @note    The base index is one, the endpoint zero does not have a
-   *          reserved element in this array.
-   */
-  void                          *in_params[USB_MAX_ENDPOINTS];
-  /**
-   * @brief   Fields available to user, it can be used to associate an
-   *          application-defined handler to an OUT endpoint.
-   * @note    The base index is one, the endpoint zero does not have a
-   *          reserved element in this array.
-   */
-  void                          *out_params[USB_MAX_ENDPOINTS];
-  /**
-   * @brief   Endpoint 0 state.
-   */
-  usbep0state_t                 ep0state;
-  /**
-   * @brief   Next position in the buffer to be transferred through endpoint 0.
-   */
-  uint8_t                       *ep0next;
-  /**
-   * @brief   Number of bytes yet to be transferred through endpoint 0.
-   */
-  size_t                        ep0n;
-  /**
-   * @brief   Endpoint 0 end transaction callback.
-   */
-  usbcallback_t                 ep0endcb;
-  /**
-   * @brief   Setup packet buffer.
-   */
-  uint8_t                       setup[8];
-  /**
-   * @brief   Current USB device status.
-   */
-  uint16_t                      status;
-  /**
-   * @brief   Assigned USB address.
-   */
-  uint8_t                       address;
-  /**
-   * @brief   Current USB device configuration.
-   */
-  uint8_t                       configuration;
-#if defined(USB_DRIVER_EXT_FIELDS)
-  USB_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Pointer to the OTG peripheral associated to this driver.
-   */
-  stm32_otg_t                   *otg;
-  /**
-   * @brief   Peripheral-specific parameters.
-   */
-  const stm32_otg_params_t      *otgparams;
-  /**
-   * @brief   Pointer to the next address in the packet memory.
-   */
-  uint32_t                      pmnext;
-  /**
-   * @brief   Mask of TXFIFOs to be filled by the pump thread.
-   */
-  uint32_t                      txpending;
-  /**
-   * @brief   Pointer to the thread.
-   */
-  Thread                        *thd_ptr;
-  /**
-   * @brief   Pointer to the thread when it is sleeping or @p NULL.
-   */
-  Thread                        *thd_wait;
-  /**
-   * @brief   Working area for the dedicated data pump thread;
-   */
-  WORKING_AREA(wa_pump, STM32_USB_OTG_THREAD_STACK_SIZE);
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the exact size of a receive transaction.
- * @details The received size can be different from the size specified in
- *          @p usbStartReceiveI() because the last packet could have a size
- *          different from the expected one.
- * @pre     The OUT endpoint must have been configured in transaction mode
- *          in order to use this function.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              Received data size.
- *
- * @notapi
- */
-#define usb_lld_get_transaction_size(usbp, ep)                              \
-  ((usbp)->epc[ep]->out_state->rxcnt)
-
-/**
- * @brief   Connects the USB device.
- *
- * @api
- */
-#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN)
-
-/**
- * @brief   Disconnect the USB device.
- *
- * @api
- */
-#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_USB_USE_OTG1 && !defined(__DOXYGEN__)
-extern USBDriver USBD1;
-#endif
-
-#if STM32_USB_USE_OTG2 && !defined(__DOXYGEN__)
-extern USBDriver USBD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void usb_lld_init(void);
-  void usb_lld_start(USBDriver *usbp);
-  void usb_lld_stop(USBDriver *usbp);
-  void usb_lld_reset(USBDriver *usbp);
-  void usb_lld_set_address(USBDriver *usbp);
-  void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
-  void usb_lld_disable_endpoints(USBDriver *usbp);
-  usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
-  usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
-  void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
-  void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
-  void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
-  void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
-  void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_USB */
-
-#endif /* _USB_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
deleted file mode 100644
index 108d94fb6..000000000
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    STM32/RTCv1/rtc_lld.c
- * @brief   STM32 RTC subsystem low level driver header.
- *
- * @addtogroup RTC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief RTC driver identifier.
- */
-RTCDriver RTCD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Wait for synchronization of RTC registers with APB1 bus.
- * @details This function must be invoked before trying to read RTC registers
- *          in the backup domain: DIV, CNT, ALR. CR registers can always
- *          be read.
- *
- * @notapi
- */
-#define rtc_lld_apb1_sync() {while ((RTC->CRL & RTC_CRL_RSF) == 0);}
-
-/**
- * @brief   Wait for for previous write operation complete.
- * @details This function must be invoked before writing to any RTC registers
- *
- * @notapi
- */
-#define rtc_lld_wait_write() {while ((RTC->CRL & RTC_CRL_RTOFF) == 0);}
-
-/**
- * @brief   Acquires write access to RTC registers.
- * @details Before writing to the backup domain RTC registers the previous
- *          write operation must be completed. Use this function before
- *          writing to PRL, CNT, ALR registers.
- *
- * @notapi
- */
-#define rtc_lld_acquire() {rtc_lld_wait_write(); RTC->CRL |= RTC_CRL_CNF;}
-
-/**
- * @brief   Releases write access to RTC registers.
- *
- * @notapi
- */
-#define rtc_lld_release() {RTC->CRL &= ~RTC_CRL_CNF;}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   RTC interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(RTC_IRQHandler) {
-  uint16_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  /* This wait works only when AHB1 bus was previously powered off by any
-     reason (standby, reset, etc). In other cases it does nothing.*/
-  rtc_lld_apb1_sync();
-
-  /* Mask of all enabled and pending sources.*/
-  flags = RTC->CRH & RTC->CRL;
-  RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);
-
-  if (flags & RTC_CRL_SECF)
-    RTCD1.callback(&RTCD1, RTC_EVENT_SECOND);
-
-  if (flags & RTC_CRL_ALRF)
-    RTCD1.callback(&RTCD1, RTC_EVENT_ALARM);
-
-  if (flags & RTC_CRL_OWF)
-    RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Load value of RTCCLK to prescaler registers.
- * @note    The pre-scaler must not be set on every reset as RTC clock
- *          counts are lost when it is set.
- * @note    This function designed to be called from
- *          hal_lld_backup_domain_init(). Because there is only place
- *          where possible to detect BKP domain reset event reliably.
- *
- * @notapi
- */
-void rtc_lld_set_prescaler(void){
-  rtc_lld_acquire();
-  RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F;
-  RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1))      & 0xFFFF);
-  rtc_lld_release();
-}
-
-/**
- * @brief   Initialize RTC.
- *
- * @notapi
- */
-void rtc_lld_init(void){
-
-  /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock
-     stop. Otherwise its value will not be actual. */
-  RTC->CRL &= ~RTC_CRL_RSF;
-
-  /* Required because access to PRL.*/
-  rtc_lld_apb1_sync();
-
-  /* All interrupts initially disabled.*/
-  rtc_lld_wait_write();
-  RTC->CRH = 0;
-
-  /* Callback initially disabled.*/
-  RTCD1.callback = NULL;
-
-  /* IRQ vector permanently assigned to this driver.*/
-  nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Set current time.
- * @note    Fractional part will be silently ignored. There is no possibility
- *          to change it on STM32F1xx platform.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] timespec  pointer to a @p RTCTime structure
- *
- * @notapi
- */
-void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
-
-  (void)rtcp;
-
-  rtc_lld_acquire();
-  RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16);
-  RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF);
-  rtc_lld_release();
-}
-
-/**
- * @brief   Get current time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] timespec  pointer to a @p RTCTime structure
- *
- * @notapi
- */
-void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
-  (void)rtcp;
-
-  uint32_t time_frac;
-
-  /* Required because access to CNT and DIV.*/
-  rtc_lld_apb1_sync();
-
-  /* Loops until two consecutive read returning the same value.*/
-  do {
-    timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL;
-    time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL;
-  } while ((timespec->tv_sec) != (((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL));
-
-  timespec->tv_msec = (uint16_t)(((STM32_RTCCLK - 1 - time_frac) * 1000) /
-                                 STM32_RTCCLK);
-}
-
-/**
- * @brief   Set alarm time.
- *
- * @note      Default value after BKP domain reset is 0xFFFFFFFF
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] alarm     alarm identifier
- * @param[in] alarmspec pointer to a @p RTCAlarm structure
- *
- * @notapi
- */
-void rtc_lld_set_alarm(RTCDriver *rtcp,
-                       rtcalarm_t alarm,
-                       const RTCAlarm *alarmspec) {
-
-  (void)rtcp;
-  (void)alarm;
-
-  rtc_lld_acquire();
-  if (alarmspec != NULL) {
-    RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16);
-    RTC->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF);
-  }
-  else {
-    RTC->ALRH = 0;
-    RTC->ALRL = 0;
-  }
-  rtc_lld_release();
-}
-
-/**
- * @brief   Get current alarm.
- * @note    If an alarm has not been set then the returned alarm specification
- *          is not meaningful.
- *
- * @note    Default value after BKP domain reset is 0xFFFFFFFF.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] alarm     alarm identifier
- * @param[out] alarmspec pointer to a @p RTCAlarm structure
- *
- * @notapi
- */
-void rtc_lld_get_alarm(RTCDriver *rtcp,
-                       rtcalarm_t alarm,
-                       RTCAlarm *alarmspec) {
-
-  (void)rtcp;
-  (void)alarm;
-
-  /* Required because access to ALR.*/
-  rtc_lld_apb1_sync();
-
-  alarmspec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL);
-}
-
-/**
- * @brief   Enables or disables RTC callbacks.
- * @details This function enables or disables callbacks, use a @p NULL pointer
- *          in order to disable a callback.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] callback  callback function pointer or @p NULL
- *
- * @notapi
- */
-void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
-
-  if (callback != NULL) {
-
-    /* IRQ sources enabled only after setting up the callback.*/
-    rtcp->callback = callback;
-
-    rtc_lld_wait_write();
-    RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);
-    RTC->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE;
-  }
-  else {
-    rtc_lld_wait_write();
-    RTC->CRH = 0;
-
-    /* Callback set to NULL only after disabling the IRQ sources.*/
-    rtcp->callback = NULL;
-  }
-}
-
-#include "chrtclib.h"
-
-/**
- * @brief   Get current time in format suitable for usage in FatFS.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @return              FAT time value.
- *
- * @api
- */
-uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) {
-  uint32_t fattime;
-  struct tm timp;
-
-  rtcGetTimeTm(rtcp, &timp);
-
-  fattime  = (timp.tm_sec)       >> 1;
-  fattime |= (timp.tm_min)       << 5;
-  fattime |= (timp.tm_hour)      << 11;
-  fattime |= (timp.tm_mday)      << 16;
-  fattime |= (timp.tm_mon + 1)   << 21;
-  fattime |= (timp.tm_year - 80) << 25;
-
-  return fattime;
-}
-#endif /* HAL_USE_RTC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/RTCv2/rtc_lld.c b/os/hal/platforms/STM32/RTCv2/rtc_lld.c
deleted file mode 100644
index 7a6848f57..000000000
--- a/os/hal/platforms/STM32/RTCv2/rtc_lld.c
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    STM32/RTCv2/rtc_lld.c
- * @brief   RTC low level driver.
- *
- * @addtogroup RTC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief RTC driver identifier.
- */
-RTCDriver RTCD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-/**
- * @brief   Wait for synchronization of RTC registers with APB1 bus.
- * @details This function must be invoked before trying to read RTC registers.
- *
- * @notapi
- */
-#define rtc_lld_apb1_sync() {while ((RTCD1.id_rtc->ISR & RTC_ISR_RSF) == 0);}
-
-/**
- * @brief   Beginning of configuration procedure.
- *
- * @notapi
- */
-#define rtc_lld_enter_init() {                                              \
-  RTCD1.id_rtc->ISR |= RTC_ISR_INIT;                                        \
-  while ((RTCD1.id_rtc->ISR & RTC_ISR_INITF) == 0)                          \
-    ;                                                                       \
-}
-
-/**
- * @brief   Finalizing of configuration procedure.
- *
- * @notapi
- */
-#define rtc_lld_exit_init() {RTCD1.id_rtc->ISR &= ~RTC_ISR_INIT;}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enable access to registers.
- *
- * @api
- */
-void rtc_lld_init(void){
-  RTCD1.id_rtc = RTC;
-
-  /* Asynchronous part of preloader. Set it to maximum value. */
-  uint32_t prediv_a = 0x7F;
-
-  /* Disable write protection. */
-  RTCD1.id_rtc->WPR = 0xCA;
-  RTCD1.id_rtc->WPR = 0x53;
-
-  /* If calendar not init yet. */
-  if (!(RTC->ISR & RTC_ISR_INITS)){
-    rtc_lld_enter_init();
-
-    /* Prescaler register must be written in two SEPARATE writes. */
-    prediv_a = (prediv_a << 16) |
-                (((STM32_RTCCLK / (prediv_a + 1)) - 1) & 0x7FFF);
-    RTCD1.id_rtc->PRER = prediv_a;
-    RTCD1.id_rtc->PRER = prediv_a;
-    rtc_lld_exit_init();
-  }
-}
-
-/**
- * @brief   Set current time.
- * @note    Fractional part will be silently ignored. There is no possibility
- *          to set it on STM32 platform.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] timespec  pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
-  (void)rtcp;
-
-  rtc_lld_enter_init();
-  if (timespec->h12)
-    RTCD1.id_rtc->CR |= RTC_CR_FMT;
-  else
-    RTCD1.id_rtc->CR &= ~RTC_CR_FMT;
-  RTCD1.id_rtc->TR = timespec->tv_time;
-  RTCD1.id_rtc->DR = timespec->tv_date;
-  rtc_lld_exit_init();
-}
-
-/**
- * @brief   Get current time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
-  (void)rtcp;
-
-  rtc_lld_apb1_sync();
-
-#if STM32_RTC_HAS_SUBSECONDS
-  timespec->tv_msec =
-      (1000 * ((RTCD1.id_rtc->PRER & 0x7FFF) - RTCD1.id_rtc->SSR)) /
-      ((RTCD1.id_rtc->PRER & 0x7FFF) + 1);
-#endif /* STM32_RTC_HAS_SUBSECONDS */
-  timespec->tv_time = RTCD1.id_rtc->TR;
-  timespec->tv_date = RTCD1.id_rtc->DR;
-}
-
-/**
- * @brief     Set alarm time.
- *
- * @note      Default value after BKP domain reset for both comparators is 0.
- * @note      Function does not performs any checks of alarm time validity.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] alarm     alarm identifier starting from zero
- * @param[in] alarmspec pointer to a @p RTCAlarm structure
- *
- * @api
- */
-void rtc_lld_set_alarm(RTCDriver *rtcp,
-                       rtcalarm_t alarm,
-                       const RTCAlarm *alarmspec) {
-
-  if (alarm == 0) {
-    if (alarmspec != NULL){
-      rtcp->id_rtc->CR &= ~RTC_CR_ALRAE;
-      while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRAWF))
-        ;
-      rtcp->id_rtc->ALRMAR = alarmspec->tv_datetime;
-      rtcp->id_rtc->CR |= RTC_CR_ALRAE;
-      rtcp->id_rtc->CR |= RTC_CR_ALRAIE;
-    }
-    else {
-      rtcp->id_rtc->CR &= ~RTC_CR_ALRAIE;
-      rtcp->id_rtc->CR &= ~RTC_CR_ALRAE;
-    }
-  }
-#if RTC_ALARMS == 2
-  else{
-    if (alarmspec != NULL){
-      rtcp->id_rtc->CR &= ~RTC_CR_ALRBE;
-      while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRBWF))
-        ;
-      rtcp->id_rtc->ALRMBR = alarmspec->tv_datetime;
-      rtcp->id_rtc->CR |= RTC_CR_ALRBE;
-      rtcp->id_rtc->CR |= RTC_CR_ALRBIE;
-    }
-    else {
-      rtcp->id_rtc->CR &= ~RTC_CR_ALRBIE;
-      rtcp->id_rtc->CR &= ~RTC_CR_ALRBE;
-    }
-  }
-#endif /* RTC_ALARMS == 2 */
-}
-
-/**
- * @brief   Get alarm time.
- *
- * @param[in] rtcp       pointer to RTC driver structure
- * @param[in] alarm      alarm identifier starting from zero
- * @param[out] alarmspec pointer to a @p RTCAlarm structure
- *
- * @api
- */
-void rtc_lld_get_alarm(RTCDriver *rtcp,
-                       rtcalarm_t alarm,
-                       RTCAlarm *alarmspec) {
-
-  if (alarm == 0)
-    alarmspec->tv_datetime = rtcp->id_rtc->ALRMAR;
-#if RTC_ALARMS == 2
-  else
-    alarmspec->tv_datetime = rtcp->id_rtc->ALRMBR;
-#endif
-}
-
-/**
- * @brief     Sets time of periodic wakeup.
- *
- * @note      Default value after BKP domain reset is 0x0000FFFF
- *
- * @param[in] rtcp       pointer to RTC driver structure
- * @param[in] wakeupspec pointer to a @p RTCWakeup structure
- *
- * @api
- */
-#if RTC_HAS_PERIODIC_WAKEUPS
-void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, const RTCWakeup *wakeupspec){
-  chDbgCheck((wakeupspec->wakeup != 0x30000),
-              "rtc_lld_set_periodic_wakeup, forbidden combination");
-
-  if (wakeupspec != NULL){
-    rtcp->id_rtc->CR &= ~RTC_CR_WUTE;
-    while(!(rtcp->id_rtc->ISR & RTC_ISR_WUTWF))
-      ;
-    rtcp->id_rtc->WUTR = wakeupspec->wakeup & 0xFFFF;
-    rtcp->id_rtc->CR   = (wakeupspec->wakeup >> 16) & 0x7;
-    rtcp->id_rtc->CR |= RTC_CR_WUTIE;
-    rtcp->id_rtc->CR |= RTC_CR_WUTE;
-  }
-  else {
-    rtcp->id_rtc->CR &= ~RTC_CR_WUTIE;
-    rtcp->id_rtc->CR &= ~RTC_CR_WUTE;
-  }
-}
-#endif /* RTC_HAS_PERIODIC_WAKEUPS */
-
-/**
- * @brief     Gets time of periodic wakeup.
- *
- * @note      Default value after BKP domain reset is 0x0000FFFF
- *
- * @param[in] rtcp        pointer to RTC driver structure
- * @param[out] wakeupspec pointer to a @p RTCWakeup structure
- *
- * @api
- */
-#if RTC_HAS_PERIODIC_WAKEUPS
-void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec){
-  wakeupspec->wakeup  = 0;
-  wakeupspec->wakeup |= rtcp->id_rtc->WUTR;
-  wakeupspec->wakeup |= (((uint32_t)rtcp->id_rtc->CR) & 0x7) << 16;
-}
-#endif /* RTC_HAS_PERIODIC_WAKEUPS */
-
-/**
- * @brief   Get current time in format suitable for usage in FatFS.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @return              FAT time value.
- *
- * @api
- */
-uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) {
-  uint32_t fattime;
-  RTCTime timespec;
-  uint32_t tv_time;
-  uint32_t tv_date;
-  uint32_t v;
-
-  chSysLock();
-  rtcGetTimeI(rtcp, &timespec);
-  chSysUnlock();
-
-  tv_time = timespec.tv_time;
-  tv_date = timespec.tv_date;
-
-  v =  (tv_time & RTC_TR_SU) >> RTC_TR_SU_OFFSET;
-  v += ((tv_time & RTC_TR_ST) >> RTC_TR_ST_OFFSET) * 10;
-  fattime  = v >> 1;
-
-  v =  (tv_time & RTC_TR_MNU) >> RTC_TR_MNU_OFFSET;
-  v += ((tv_time & RTC_TR_MNT) >> RTC_TR_MNT_OFFSET) * 10;
-  fattime |= v << 5;
-
-  v =  (tv_time & RTC_TR_HU) >> RTC_TR_HU_OFFSET;
-  v += ((tv_time & RTC_TR_HT) >> RTC_TR_HT_OFFSET) * 10;
-  v += 12 * ((tv_time & RTC_TR_PM) >> RTC_TR_PM_OFFSET);
-  fattime |= v << 11;
-
-  v =  (tv_date & RTC_DR_DU) >> RTC_DR_DU_OFFSET;
-  v += ((tv_date & RTC_DR_DT) >> RTC_DR_DT_OFFSET) * 10;
-  fattime |= v << 16;
-
-  v =  (tv_date & RTC_DR_MU) >> RTC_DR_MU_OFFSET;
-  v += ((tv_date & RTC_DR_MT) >> RTC_DR_MT_OFFSET) * 10;
-  fattime |= v << 21;
-
-  v =  (tv_date & RTC_DR_YU) >> RTC_DR_YU_OFFSET;
-  v += ((tv_date & RTC_DR_YT) >> RTC_DR_YT_OFFSET) * 10;
-  v += 2000 - 1900 - 80;
-  fattime |= v << 25;
-
-  return fattime;
-}
-
-#endif /* HAL_USE_RTC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/RTCv2/rtc_lld.h b/os/hal/platforms/STM32/RTCv2/rtc_lld.h
deleted file mode 100644
index 1c9b6e627..000000000
--- a/os/hal/platforms/STM32/RTCv2/rtc_lld.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    STM32/RTCv2/rtc_lld.h
- * @brief   RTC low level driver header.
- *
- * @addtogroup RTC
- * @{
- */
-
-#ifndef _RTC_LLD_H_
-#define _RTC_LLD_H_
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Two alarm comparators available on STM32F4x and STM32F2x.
- */
-#if !defined(STM32F0XX)
-#define RTC_ALARMS                2
-#else
-#define RTC_ALARMS                1
-#endif
-
-/**
- * @brief   STM32F0x has no periodic wakeups.
- */
-#if !defined(STM32F0XX)
-#define RTC_HAS_PERIODIC_WAKEUPS  TRUE
-#else
-#define RTC_HAS_PERIODIC_WAKEUPS  FALSE
-#endif
-
-/**
- * @brief   Data offsets in RTC date and time registers.
- */
-#define RTC_TR_PM_OFFSET    22
-#define RTC_TR_HT_OFFSET    20
-#define RTC_TR_HU_OFFSET    16
-#define RTC_TR_MNT_OFFSET   12
-#define RTC_TR_MNU_OFFSET   8
-#define RTC_TR_ST_OFFSET    4
-#define RTC_TR_SU_OFFSET    0
-
-#define RTC_DR_YT_OFFSET    20
-#define RTC_DR_YU_OFFSET    16
-#define RTC_DR_WDU_OFFSET   13
-#define RTC_DR_MT_OFFSET    12
-#define RTC_DR_MU_OFFSET    8
-#define RTC_DR_DT_OFFSET    4
-#define RTC_DR_DU_OFFSET    0
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if HAL_USE_RTC && !STM32_HAS_RTC
-#error "RTC not present in the selected device"
-#endif
-
-#if !(STM32_RTCSEL == STM32_RTCSEL_LSE) &&                                  \
-    !(STM32_RTCSEL == STM32_RTCSEL_LSI) &&                                  \
-    !(STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
-#error "invalid source selected for RTC clock"
-#endif
-
-#if !defined(RTC_USE_INTERRUPTS) || defined(__DOXYGEN__)
-#define RTC_USE_INTERRUPTS                FALSE
-#endif
-
-#if defined(STM32_PCLK1) /* For devices without STM32_PCLK1 (STM32F0xx) */
-#if STM32_PCLK1 < (STM32_RTCCLK * 7)
-#error "STM32_PCLK1 frequency is too low to handle RTC without ugly workaround"
-#endif
-#endif /* defined(STM32_PCLK1) */
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an RTC alarm time stamp.
- */
-typedef struct RTCAlarm RTCAlarm;
-
-/**
- * @brief   Type of a structure representing an RTC wakeup period.
- */
-typedef struct RTCWakeup RTCWakeup;
-
-/**
- * @brief   Type of a structure representing an RTC callbacks config.
- */
-typedef struct RTCCallbackConfig RTCCallbackConfig;
-
-/**
- * @brief   Type of an RTC alarm.
- * @details Meaningful on platforms with more than 1 alarm comparator.
- */
-typedef uint32_t rtcalarm_t;
-
-/**
- * @brief   Structure representing an RTC time stamp.
- */
-struct RTCTime {
-  /**
-   * @brief RTC date register in STM32 BCD format.
-   */
-  uint32_t tv_date;
-  /**
-   * @brief RTC time register in STM32 BCD format.
-   */
-  uint32_t tv_time;
-  /**
-   * @brief Set this to TRUE to use 12 hour notation.
-   */
-  bool_t h12;
-  /**
-   * @brief Fractional part of time.
-   */
-#if STM32_RTC_HAS_SUBSECONDS
-  uint32_t tv_msec;
-#endif
-};
-
-/**
- * @brief   Structure representing an RTC alarm time stamp.
- */
-struct RTCAlarm {
-  /**
-   * @brief Date and time of alarm in STM32 BCD.
-   */
-  uint32_t tv_datetime;
-};
-
-#if RTC_HAS_PERIODIC_WAKEUPS
-/**
- * @brief   Structure representing an RTC periodic wakeup period.
- */
-struct RTCWakeup {
-  /**
-   * @brief   RTC WUTR register.
-   * @details Bits [15:0] contain value of WUTR register
-   *          Bits [18:16] contain value of WUCKSEL bits in CR register
-   *
-   * @note    ((WUTR == 0) || (WUCKSEL == 3)) is forbidden combination.
-   */
-  uint32_t wakeup;
-};
-#endif /* RTC_HAS_PERIODIC_WAKEUPS */
-
-/**
- * @brief   Structure representing an RTC driver.
- */
-struct RTCDriver{
-  /**
-   * @brief Pointer to the RTC registers block.
-   */
-  RTC_TypeDef               *id_rtc;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern RTCDriver RTCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void rtc_lld_init(void);
-  void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec);
-  void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec);
-  void rtc_lld_set_alarm(RTCDriver *rtcp,
-                         rtcalarm_t alarm,
-                         const RTCAlarm *alarmspec);
-  void rtc_lld_get_alarm(RTCDriver *rtcp,
-                         rtcalarm_t alarm,
-                         RTCAlarm *alarmspec);
-#if RTC_HAS_PERIODIC_WAKEUPS
-  void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, const RTCWakeup *wakeupspec);
-  void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec);
-#endif /* RTC_HAS_PERIODIC_WAKEUPS */
-  uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_RTC */
-
-#endif /* _RTC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/SPIv1/spi_lld.c b/os/hal/platforms/STM32/SPIv1/spi_lld.c
deleted file mode 100644
index e3ac56503..000000000
--- a/os/hal/platforms/STM32/SPIv1/spi_lld.c
+++ /dev/null
@@ -1,636 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/SPIv1/spi_lld.c
- * @brief   STM32 SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define SPI1_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM,                        \
-                       STM32_SPI1_RX_DMA_CHN)
-
-#define SPI1_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM,                        \
-                       STM32_SPI1_TX_DMA_CHN)
-
-#define SPI2_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM,                        \
-                       STM32_SPI2_RX_DMA_CHN)
-
-#define SPI2_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM,                        \
-                       STM32_SPI2_TX_DMA_CHN)
-
-#define SPI3_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM,                        \
-                       STM32_SPI3_RX_DMA_CHN)
-
-#define SPI3_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM,                        \
-                       STM32_SPI3_TX_DMA_CHN)
-
-#define SPI4_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM,                        \
-                       STM32_SPI4_RX_DMA_CHN)
-
-#define SPI4_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM,                        \
-                       STM32_SPI4_TX_DMA_CHN)
-
-#define SPI5_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM,                        \
-                       STM32_SPI5_RX_DMA_CHN)
-
-#define SPI5_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM,                        \
-                       STM32_SPI5_TX_DMA_CHN)
-
-#define SPI6_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM,                        \
-                       STM32_SPI6_RX_DMA_CHN)
-
-#define SPI6_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM,                        \
-                       STM32_SPI6_TX_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief SPI1 driver identifier.*/
-#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/** @brief SPI2 driver identifier.*/
-#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)
-SPIDriver SPID2;
-#endif
-
-/** @brief SPI3 driver identifier.*/
-#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)
-SPIDriver SPID3;
-#endif
-
-/** @brief SPI4 driver identifier.*/
-#if STM32_SPI_USE_SPI4 || defined(__DOXYGEN__)
-SPIDriver SPID4;
-#endif
-
-/** @brief SPI5 driver identifier.*/
-#if STM32_SPI_USE_SPI5 || defined(__DOXYGEN__)
-SPIDriver SPID5;
-#endif
-
-/** @brief SPI6 driver identifier.*/
-#if STM32_SPI_USE_SPI6 || defined(__DOXYGEN__)
-SPIDriver SPID6;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static uint16_t dummytx;
-static uint16_t dummyrx;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared end-of-rx service routine.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
-
-  /* DMA errors handling.*/
-#if defined(STM32_SPI_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_SPI_DMA_ERROR_HOOK(spip);
-  }
-#else
-  (void)flags;
-#endif
-
-  /* Stop everything.*/
-  dmaStreamDisable(spip->dmatx);
-  dmaStreamDisable(spip->dmarx);
-
-  /* Portable SPI ISR code defined in the high level driver, note, it is
-     a macro.*/
-  _spi_isr_code(spip);
-}
-
-/**
- * @brief   Shared end-of-tx service routine.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
-
-  /* DMA errors handling.*/
-#if defined(STM32_SPI_DMA_ERROR_HOOK)
-  (void)spip;
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_SPI_DMA_ERROR_HOOK(spip);
-  }
-#else
-  (void)spip;
-  (void)flags;
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-  dummytx = 0xFFFF;
-
-#if STM32_SPI_USE_SPI1
-  spiObjectInit(&SPID1);
-  SPID1.spi       = SPI1;
-  SPID1.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
-  SPID1.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
-  SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_P2M |
-                    STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-  SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_M2P |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_SPI_USE_SPI2
-  spiObjectInit(&SPID2);
-  SPID2.spi       = SPI2;
-  SPID2.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
-  SPID2.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
-  SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_P2M |
-                    STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-  SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_M2P |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_SPI_USE_SPI3
-  spiObjectInit(&SPID3);
-  SPID3.spi       = SPI3;
-  SPID3.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
-  SPID3.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
-  SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_P2M |
-                    STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-  SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_M2P |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_SPI_USE_SPI4
-  spiObjectInit(&SPID4);
-  SPID4.spi       = SPI4;
-  SPID4.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM);
-  SPID4.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM);
-  SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_P2M |
-                    STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-  SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_M2P |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_SPI_USE_SPI5
-  spiObjectInit(&SPID5);
-  SPID5.spi       = SPI5;
-  SPID5.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM);
-  SPID5.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM);
-  SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_P2M |
-                    STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-  SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_M2P |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_SPI_USE_SPI6
-  spiObjectInit(&SPID6);
-  SPID6.spi       = SPI6;
-  SPID6.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM);
-  SPID6.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM);
-  SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_P2M |
-                    STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-  SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_M2P |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-#endif
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  /* If in stopped state then enables the SPI and DMA clocks.*/
-  if (spip->state == SPI_STOP) {
-#if STM32_SPI_USE_SPI1
-    if (&SPID1 == spip) {
-      bool_t b;
-      b = dmaStreamAllocate(spip->dmarx,
-                            STM32_SPI_SPI1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");
-      b = dmaStreamAllocate(spip->dmatx,
-                            STM32_SPI_SPI1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
-      rccEnableSPI1(FALSE);
-    }
-#endif
-#if STM32_SPI_USE_SPI2
-    if (&SPID2 == spip) {
-      bool_t b;
-      b = dmaStreamAllocate(spip->dmarx,
-                            STM32_SPI_SPI2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated");
-      b = dmaStreamAllocate(spip->dmatx,
-                            STM32_SPI_SPI2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated");
-      rccEnableSPI2(FALSE);
-    }
-#endif
-#if STM32_SPI_USE_SPI3
-    if (&SPID3 == spip) {
-      bool_t b;
-      b = dmaStreamAllocate(spip->dmarx,
-                            STM32_SPI_SPI3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated");
-      b = dmaStreamAllocate(spip->dmatx,
-                            STM32_SPI_SPI3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated");
-      rccEnableSPI3(FALSE);
-    }
-#endif
-#if STM32_SPI_USE_SPI4
-    if (&SPID4 == spip) {
-      bool_t b;
-      b = dmaStreamAllocate(spip->dmarx,
-                            STM32_SPI_SPI4_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #7", "stream already allocated");
-      b = dmaStreamAllocate(spip->dmatx,
-                            STM32_SPI_SPI4_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #8", "stream already allocated");
-      rccEnableSPI4(FALSE);
-    }
-#endif
-#if STM32_SPI_USE_SPI5
-    if (&SPID5 == spip) {
-      bool_t b;
-      b = dmaStreamAllocate(spip->dmarx,
-                            STM32_SPI_SPI5_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #9", "stream already allocated");
-      b = dmaStreamAllocate(spip->dmatx,
-                            STM32_SPI_SPI5_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #10", "stream already allocated");
-      rccEnableSPI5(FALSE);
-    }
-#endif
-#if STM32_SPI_USE_SPI6
-    if (&SPID6 == spip) {
-      bool_t b;
-      b = dmaStreamAllocate(spip->dmarx,
-                            STM32_SPI_SPI6_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #11", "stream already allocated");
-      b = dmaStreamAllocate(spip->dmatx,
-                            STM32_SPI_SPI6_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #12", "stream already allocated");
-      rccEnableSPI6(FALSE);
-    }
-#endif
-
-    /* DMA setup.*/
-    dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR);
-    dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR);
-  }
-
-  /* Configuration-specific DMA setup.*/
-  if ((spip->config->cr1 & SPI_CR1_DFF) == 0) {
-    /* Frame width is 8 bits or smaller.*/
-    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
-                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
-                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-  }
-  else {
-    /* Frame width is larger than 8 bits.*/
-    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
-                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
-                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-  }
-  /* SPI setup and enable.*/
-  spip->spi->CR1  = 0;
-  spip->spi->CR1  = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
-                    SPI_CR1_SSI;
-  spip->spi->CR2  = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
-  spip->spi->CR1 |= SPI_CR1_SPE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  /* If in ready state then disables the SPI clock.*/
-  if (spip->state == SPI_READY) {
-
-    /* SPI disable.*/
-    spip->spi->CR1 = 0;
-    spip->spi->CR2 = 0;
-    dmaStreamRelease(spip->dmarx);
-    dmaStreamRelease(spip->dmatx);
-
-#if STM32_SPI_USE_SPI1
-    if (&SPID1 == spip)
-      rccDisableSPI1(FALSE);
-#endif
-#if STM32_SPI_USE_SPI2
-    if (&SPID2 == spip)
-      rccDisableSPI2(FALSE);
-#endif
-#if STM32_SPI_USE_SPI3
-    if (&SPID3 == spip)
-      rccDisableSPI3(FALSE);
-#endif
-#if STM32_SPI_USE_SPI4
-    if (&SPID4 == spip)
-      rccDisableSPI4(FALSE);
-#endif
-#if STM32_SPI_USE_SPI5
-    if (&SPID5 == spip)
-      rccDisableSPI5(FALSE);
-#endif
-#if STM32_SPI_USE_SPI6
-    if (&SPID6 == spip)
-      rccDisableSPI6(FALSE);
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- *          idle words on the SPI bus and ignores the received data.
- * @post    At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  dmaStreamSetMemory0(spip->dmarx, &dummyrx);
-  dmaStreamSetTransactionSize(spip->dmarx, n);
-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
-
-  dmaStreamSetMemory0(spip->dmatx, &dummytx);
-  dmaStreamSetTransactionSize(spip->dmatx, n);
-  dmaStreamSetMode(spip->dmatx, spip->txdmamode);
-
-  dmaStreamEnable(spip->dmarx);
-  dmaStreamEnable(spip->dmatx);
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  dmaStreamSetMemory0(spip->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(spip->dmarx, n);
-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
-
-  dmaStreamSetMemory0(spip->dmatx, txbuf);
-  dmaStreamSetTransactionSize(spip->dmatx, n);
-  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
-
-  dmaStreamEnable(spip->dmarx);
-  dmaStreamEnable(spip->dmatx);
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  dmaStreamSetMemory0(spip->dmarx, &dummyrx);
-  dmaStreamSetTransactionSize(spip->dmarx, n);
-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
-
-  dmaStreamSetMemory0(spip->dmatx, txbuf);
-  dmaStreamSetTransactionSize(spip->dmatx, n);
-  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
-
-  dmaStreamEnable(spip->dmarx);
-  dmaStreamEnable(spip->dmatx);
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  dmaStreamSetMemory0(spip->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(spip->dmarx, n);
-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
-
-  dmaStreamSetMemory0(spip->dmatx, &dummytx);
-  dmaStreamSetTransactionSize(spip->dmatx, n);
-  dmaStreamSetMode(spip->dmatx, spip->txdmamode);
-
-  dmaStreamEnable(spip->dmarx);
-  dmaStreamEnable(spip->dmatx);
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  spip->spi->DR = frame;
-  while ((spip->spi->SR & SPI_SR_RXNE) == 0)
-    ;
-  return spip->spi->DR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/SPIv1/spi_lld.h b/os/hal/platforms/STM32/SPIv1/spi_lld.h
deleted file mode 100644
index 404bb5b0a..000000000
--- a/os/hal/platforms/STM32/SPIv1/spi_lld.h
+++ /dev/null
@@ -1,628 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/SPIv1/spi_lld.h
- * @brief   STM32 SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for SPI1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define STM32_SPI_USE_SPI1                  FALSE
-#endif
-
-/**
- * @brief   SPI2 driver enable switch.
- * @details If set to @p TRUE the support for SPI2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
-#define STM32_SPI_USE_SPI2                  FALSE
-#endif
-
-/**
- * @brief   SPI3 driver enable switch.
- * @details If set to @p TRUE the support for SPI3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
-#define STM32_SPI_USE_SPI3                  FALSE
-#endif
-
-/**
- * @brief   SPI4 driver enable switch.
- * @details If set to @p TRUE the support for SPI4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__)
-#define STM32_SPI_USE_SPI4                  FALSE
-#endif
-
-/**
- * @brief   SPI5 driver enable switch.
- * @details If set to @p TRUE the support for SPI5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__)
-#define STM32_SPI_USE_SPI5                  FALSE
-#endif
-
-/**
- * @brief   SPI6 driver enable switch.
- * @details If set to @p TRUE the support for SPI6 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__)
-#define STM32_SPI_USE_SPI6                  FALSE
-#endif
-
-/**
- * @brief   SPI1 interrupt priority level setting.
- */
-#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   SPI2 interrupt priority level setting.
- */
-#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   SPI3 interrupt priority level setting.
- */
-#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   SPI4 interrupt priority level setting.
- */
-#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI4_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   SPI5 interrupt priority level setting.
- */
-#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI5_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   SPI6 interrupt priority level setting.
- */
-#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI6_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   SPI1 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   SPI2 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   SPI3 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   SPI4 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI4_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   SPI5 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI5_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   SPI6 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI6_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   SPI DMA error hook.
- */
-#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_SPI_DMA_ERROR_HOOK(spip)      chSysHalt()
-#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief   DMA stream used for SPI1 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
-#endif
-
-/**
- * @brief   DMA stream used for SPI1 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
-#endif
-
-/**
- * @brief   DMA stream used for SPI2 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-#endif
-
-/**
- * @brief   DMA stream used for SPI2 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#endif
-
-/**
- * @brief   DMA stream used for SPI3 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
-#endif
-
-/**
- * @brief   DMA stream used for SPI3 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#endif
-
-/**
- * @brief   DMA stream used for SPI4 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI4_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI4_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
-#endif
-
-/**
- * @brief   DMA stream used for SPI4 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI4_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI4_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
-#endif
-
-/**
- * @brief   DMA stream used for SPI5 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI5_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI5_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
-#endif
-
-/**
- * @brief   DMA stream used for SPI5 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI5_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI5_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 4)
-#endif
-
-/**
- * @brief   DMA stream used for SPI6 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI6_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI6_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 6)
-#endif
-
-/**
- * @brief   DMA stream used for SPI6 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI6_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI6_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 5)
-#endif
-
-#else /* !STM32_ADVANCED_DMA */
-
-/* Fixed streams for platforms using the old DMA peripheral, the values are
-   valid for both STM32F1xx and STM32L1xx.*/
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
-#define STM32_SPI_SPI4_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
-#define STM32_SPI_SPI4_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI5_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
-#define STM32_SPI_SPI5_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 4)
-#define STM32_SPI_SPI6_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 5)
-#define STM32_SPI_SPI6_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 6)
-
-#endif /* !STM32_ADVANCED_DMA*/
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
-#error "SPI1 not present in the selected device"
-#endif
-
-#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
-#error "SPI2 not present in the selected device"
-#endif
-
-#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
-#error "SPI3 not present in the selected device"
-#endif
-
-#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4
-#error "SPI4 not present in the selected device"
-#endif
-
-#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5
-#error "SPI5 not present in the selected device"
-#endif
-
-#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6
-#error "SPI6 not present in the selected device"
-#endif
-
-#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \
-    !STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-#if STM32_SPI_USE_SPI1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI1"
-#endif
-
-#if STM32_SPI_USE_SPI2 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI2"
-#endif
-
-#if STM32_SPI_USE_SPI3 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI3"
-#endif
-
-#if STM32_SPI_USE_SPI4 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI4"
-#endif
-
-#if STM32_SPI_USE_SPI5 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI5"
-#endif
-
-#if STM32_SPI_USE_SPI6 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI6"
-#endif
-
-#if STM32_SPI_USE_SPI1 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SPI1"
-#endif
-
-#if STM32_SPI_USE_SPI2 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SPI2"
-#endif
-
-#if STM32_SPI_USE_SPI3 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SPI3"
-#endif
-
-#if STM32_SPI_USE_SPI4 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SPI4"
-#endif
-
-#if STM32_SPI_USE_SPI5 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SPI5"
-#endif
-
-#if STM32_SPI_USE_SPI6 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SPI6"
-#endif
-
-#if STM32_SPI_USE_SPI1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
-#error "invalid DMA stream associated to SPI1 RX"
-#endif
-
-#if STM32_SPI_USE_SPI1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
-#error "invalid DMA stream associated to SPI1 TX"
-#endif
-
-#if STM32_SPI_USE_SPI2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
-#error "invalid DMA stream associated to SPI2 RX"
-#endif
-
-#if STM32_SPI_USE_SPI2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
-#error "invalid DMA stream associated to SPI2 TX"
-#endif
-
-#if STM32_SPI_USE_SPI3 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
-#error "invalid DMA stream associated to SPI3 RX"
-#endif
-
-#if STM32_SPI_USE_SPI3 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
-#error "invalid DMA stream associated to SPI3 TX"
-#endif
-
-#if STM32_SPI_USE_SPI4 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK)
-#error "invalid DMA stream associated to SPI4 RX"
-#endif
-
-#if STM32_SPI_USE_SPI4 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK)
-#error "invalid DMA stream associated to SPI4 TX"
-#endif
-
-#if STM32_SPI_USE_SPI5 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK)
-#error "invalid DMA stream associated to SPI5 RX"
-#endif
-
-#if STM32_SPI_USE_SPI5 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK)
-#error "invalid DMA stream associated to SPI5 TX"
-#endif
-
-#if STM32_SPI_USE_SPI6 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK)
-#error "invalid DMA stream associated to SPI6 RX"
-#endif
-
-#if STM32_SPI_USE_SPI6 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK)
-#error "invalid DMA stream associated to SPI6 TX"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t             end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t                ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t                  sspad;
-  /**
-   * @brief SPI initialization data.
-   */
-  uint16_t                  cr1;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig           *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SPIx registers block.
-   */
-  SPI_TypeDef               *spi;
-  /**
-   * @brief Receive DMA stream.
-   */
-  const stm32_dma_stream_t  *dmarx;
-  /**
-   * @brief Transmit DMA stream.
-   */
-  const stm32_dma_stream_t  *dmatx;
-  /**
-   * @brief RX DMA mode bit mask.
-   */
-  uint32_t                  rxdmamode;
-  /**
-   * @brief TX DMA mode bit mask.
-   */
-  uint32_t                  txdmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
-extern SPIDriver SPID3;
-#endif
-
-#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__)
-extern SPIDriver SPID4;
-#endif
-
-#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__)
-extern SPIDriver SPID5;
-#endif
-
-#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__)
-extern SPIDriver SPID6;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/SPIv2/spi_lld.c b/os/hal/platforms/STM32/SPIv2/spi_lld.c
deleted file mode 100644
index 752c2af66..000000000
--- a/os/hal/platforms/STM32/SPIv2/spi_lld.c
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/SPIv2/spi_lld.c
- * @brief   STM32 SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define SPI1_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM,                        \
-                       STM32_SPI1_RX_DMA_CHN)
-
-#define SPI1_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM,                        \
-                       STM32_SPI1_TX_DMA_CHN)
-
-#define SPI2_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM,                        \
-                       STM32_SPI2_RX_DMA_CHN)
-
-#define SPI2_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM,                        \
-                       STM32_SPI2_TX_DMA_CHN)
-
-#define SPI3_RX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM,                        \
-                       STM32_SPI3_RX_DMA_CHN)
-
-#define SPI3_TX_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM,                        \
-                       STM32_SPI3_TX_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief SPI1 driver identifier.*/
-#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/** @brief SPI2 driver identifier.*/
-#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)
-SPIDriver SPID2;
-#endif
-
-/** @brief SPI3 driver identifier.*/
-#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)
-SPIDriver SPID3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static uint16_t dummytx;
-static uint16_t dummyrx;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared end-of-rx service routine.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
-
-  /* DMA errors handling.*/
-#if defined(STM32_SPI_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_SPI_DMA_ERROR_HOOK(spip);
-  }
-#else
-  (void)flags;
-#endif
-
-  /* Stop everything.*/
-  dmaStreamDisable(spip->dmatx);
-  dmaStreamDisable(spip->dmarx);
-
-  /* Portable SPI ISR code defined in the high level driver, note, it is
-     a macro.*/
-  _spi_isr_code(spip);
-}
-
-/**
- * @brief   Shared end-of-tx service routine.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
-
-  /* DMA errors handling.*/
-#if defined(STM32_SPI_DMA_ERROR_HOOK)
-  (void)spip;
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_SPI_DMA_ERROR_HOOK(spip);
-  }
-#else
-  (void)spip;
-  (void)flags;
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-  dummytx = 0xFFFF;
-
-#if STM32_SPI_USE_SPI1
-  spiObjectInit(&SPID1);
-  SPID1.spi       = SPI1;
-  SPID1.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
-  SPID1.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
-  SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_P2M |
-                    STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-  SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_M2P |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_SPI_USE_SPI2
-  spiObjectInit(&SPID2);
-  SPID2.spi       = SPI2;
-  SPID2.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
-  SPID2.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
-  SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_P2M |
-                    STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-  SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_M2P |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_SPI_USE_SPI3
-  spiObjectInit(&SPID3);
-  SPID3.spi       = SPI3;
-  SPID3.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
-  SPID3.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
-  SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_P2M |
-                    STM32_DMA_CR_TCIE |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-  SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
-                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
-                    STM32_DMA_CR_DIR_M2P |
-                    STM32_DMA_CR_DMEIE |
-                    STM32_DMA_CR_TEIE;
-#endif
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-  uint32_t ds;
-
-  /* If in stopped state then enables the SPI and DMA clocks.*/
-  if (spip->state == SPI_STOP) {
-#if STM32_SPI_USE_SPI1
-    if (&SPID1 == spip) {
-      bool_t b;
-      b = dmaStreamAllocate(spip->dmarx,
-                            STM32_SPI_SPI1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");
-      b = dmaStreamAllocate(spip->dmatx,
-                            STM32_SPI_SPI1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
-      rccEnableSPI1(FALSE);
-    }
-#endif
-#if STM32_SPI_USE_SPI2
-    if (&SPID2 == spip) {
-      bool_t b;
-      b = dmaStreamAllocate(spip->dmarx,
-                            STM32_SPI_SPI2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated");
-      b = dmaStreamAllocate(spip->dmatx,
-                            STM32_SPI_SPI2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated");
-      rccEnableSPI2(FALSE);
-    }
-#endif
-#if STM32_SPI_USE_SPI3
-    if (&SPID3 == spip) {
-      bool_t b;
-      b = dmaStreamAllocate(spip->dmarx,
-                            STM32_SPI_SPI3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated");
-      b = dmaStreamAllocate(spip->dmatx,
-                            STM32_SPI_SPI3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
-                            (void *)spip);
-      chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated");
-      rccEnableSPI3(FALSE);
-    }
-#endif
-
-    /* DMA setup.*/
-    dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR);
-    dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR);
-  }
-
-  /* Configuration-specific DMA setup.*/
-  ds = spip->config->cr2 & SPI_CR2_DS;
-  if (!ds || (ds <= (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0))) {
-    /* Frame width is 8 bits or smaller.*/
-    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
-                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
-                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-  }
-  else {
-    /* Frame width is larger than 8 bits.*/
-    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
-                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
-                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-  }
-  /* SPI setup and enable.*/
-  spip->spi->CR1  = 0;
-  spip->spi->CR1  = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
-                    SPI_CR1_SSI;
-  spip->spi->CR2  = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE |
-                    SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
-  spip->spi->CR1 |= SPI_CR1_SPE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  /* If in ready state then disables the SPI clock.*/
-  if (spip->state == SPI_READY) {
-
-    /* SPI disable.*/
-    spip->spi->CR1 = 0;
-    spip->spi->CR2 = 0;
-    dmaStreamRelease(spip->dmarx);
-    dmaStreamRelease(spip->dmatx);
-
-#if STM32_SPI_USE_SPI1
-    if (&SPID1 == spip)
-      rccDisableSPI1(FALSE);
-#endif
-#if STM32_SPI_USE_SPI2
-    if (&SPID2 == spip)
-      rccDisableSPI2(FALSE);
-#endif
-#if STM32_SPI_USE_SPI3
-    if (&SPID3 == spip)
-      rccDisableSPI3(FALSE);
-#endif
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- *          idle words on the SPI bus and ignores the received data.
- * @post    At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  dmaStreamSetMemory0(spip->dmarx, &dummyrx);
-  dmaStreamSetTransactionSize(spip->dmarx, n);
-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
-
-  dmaStreamSetMemory0(spip->dmatx, &dummytx);
-  dmaStreamSetTransactionSize(spip->dmatx, n);
-  dmaStreamSetMode(spip->dmatx, spip->txdmamode);
-
-  dmaStreamEnable(spip->dmarx);
-  dmaStreamEnable(spip->dmatx);
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  dmaStreamSetMemory0(spip->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(spip->dmarx, n);
-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
-
-  dmaStreamSetMemory0(spip->dmatx, txbuf);
-  dmaStreamSetTransactionSize(spip->dmatx, n);
-  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
-
-  dmaStreamEnable(spip->dmarx);
-  dmaStreamEnable(spip->dmatx);
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  dmaStreamSetMemory0(spip->dmarx, &dummyrx);
-  dmaStreamSetTransactionSize(spip->dmarx, n);
-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
-
-  dmaStreamSetMemory0(spip->dmatx, txbuf);
-  dmaStreamSetTransactionSize(spip->dmatx, n);
-  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
-
-  dmaStreamEnable(spip->dmarx);
-  dmaStreamEnable(spip->dmatx);
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  dmaStreamSetMemory0(spip->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(spip->dmarx, n);
-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
-
-  dmaStreamSetMemory0(spip->dmatx, &dummytx);
-  dmaStreamSetTransactionSize(spip->dmatx, n);
-  dmaStreamSetMode(spip->dmatx, spip->txdmamode);
-
-  dmaStreamEnable(spip->dmarx);
-  dmaStreamEnable(spip->dmatx);
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  /*
-   * Data register must be accessed with the appropriate data size.
-   * Byte size access (uint8_t *) for transactions that are <= 8-bit.
-   * Halfword size access (uint16_t) for transactions that are <= 8-bit.
-   */
-  if ((spip->config->cr2 & SPI_CR2_DS) <= (SPI_CR2_DS_2 |
-                                           SPI_CR2_DS_1 |
-                                           SPI_CR2_DS_0)) {
-    volatile uint8_t *spidr = (volatile uint8_t *)&spip->spi->DR;
-    *spidr = (uint8_t)frame;
-    while ((spip->spi->SR & SPI_SR_RXNE) == 0)
-      ;
-    return (uint16_t)*spidr;
-  }
-  else {
-    spip->spi->DR = frame;
-    while ((spip->spi->SR & SPI_SR_RXNE) == 0)
-      ;
-    return spip->spi->DR;
-  }
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/SPIv2/spi_lld.h b/os/hal/platforms/STM32/SPIv2/spi_lld.h
deleted file mode 100644
index b14ba9e08..000000000
--- a/os/hal/platforms/STM32/SPIv2/spi_lld.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/SPIv2/spi_lld.h
- * @brief   STM32 SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for SPI1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define STM32_SPI_USE_SPI1                  FALSE
-#endif
-
-/**
- * @brief   SPI2 driver enable switch.
- * @details If set to @p TRUE the support for SPI2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
-#define STM32_SPI_USE_SPI2                  FALSE
-#endif
-
-/**
- * @brief   SPI3 driver enable switch.
- * @details If set to @p TRUE the support for SPI3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
-#define STM32_SPI_USE_SPI3                  FALSE
-#endif
-
-/**
- * @brief   SPI1 interrupt priority level setting.
- */
-#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   SPI2 interrupt priority level setting.
- */
-#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   SPI3 interrupt priority level setting.
- */
-#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_IRQ_PRIORITY         10
-#endif
-
-/**
- * @brief   SPI1 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   SPI2 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   SPI3 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA streams but
- *          because of the streams ordering the RX stream has always priority
- *          over the TX stream.
- */
-#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_DMA_PRIORITY         1
-#endif
-
-/**
- * @brief   SPI DMA error hook.
- */
-#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_SPI_DMA_ERROR_HOOK(spip)      chSysHalt()
-#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief   DMA stream used for SPI1 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
-#endif
-
-/**
- * @brief   DMA stream used for SPI1 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
-#endif
-
-/**
- * @brief   DMA stream used for SPI2 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-#endif
-
-/**
- * @brief   DMA stream used for SPI2 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#endif
-
-/**
- * @brief   DMA stream used for SPI3 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
-#endif
-
-/**
- * @brief   DMA stream used for SPI3 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#endif
-
-#else /* !STM32_ADVANCED_DMA */
-
-#if defined(STM32F0XX)
-/* Fixed values for STM32F0xx devices.*/
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#endif /* defined(STM32F0XX) */
-
-#if defined(STM32F30X) || defined(STM32F37X)
-/* Fixed values for STM32F3xx devices.*/
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
-#endif /* defined(STM32F30X) */
-
-#endif /* !STM32_ADVANCED_DMA*/
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
-#error "SPI1 not present in the selected device"
-#endif
-
-#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
-#error "SPI2 not present in the selected device"
-#endif
-
-#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
-#error "SPI3 not present in the selected device"
-#endif
-
-#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-#if STM32_SPI_USE_SPI1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI1"
-#endif
-
-#if STM32_SPI_USE_SPI2 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI2"
-#endif
-
-#if STM32_SPI_USE_SPI3 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI3"
-#endif
-
-#if STM32_SPI_USE_SPI1 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SPI1"
-#endif
-
-#if STM32_SPI_USE_SPI2 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SPI2"
-#endif
-
-#if STM32_SPI_USE_SPI3 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SPI3"
-#endif
-
-#if STM32_SPI_USE_SPI1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
-#error "invalid DMA stream associated to SPI1 RX"
-#endif
-
-#if STM32_SPI_USE_SPI1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
-#error "invalid DMA stream associated to SPI1 TX"
-#endif
-
-#if STM32_SPI_USE_SPI2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
-#error "invalid DMA stream associated to SPI2 RX"
-#endif
-
-#if STM32_SPI_USE_SPI2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
-#error "invalid DMA stream associated to SPI2 TX"
-#endif
-
-#if STM32_SPI_USE_SPI3 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
-#error "invalid DMA stream associated to SPI3 RX"
-#endif
-
-#if STM32_SPI_USE_SPI3 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
-#error "invalid DMA stream associated to SPI3 TX"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t             end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t                ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t                  sspad;
-  /**
-   * @brief SPI CR1 register initialization data.
-   */
-  uint16_t                  cr1;
-  /**
-   * @brief SPI CR2 register initialization data.
-   */
-  uint16_t                  cr2;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig           *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the SPIx registers block.
-   */
-  SPI_TypeDef               *spi;
-  /**
-   * @brief Receive DMA stream.
-   */
-  const stm32_dma_stream_t  *dmarx;
-  /**
-   * @brief Transmit DMA stream.
-   */
-  const stm32_dma_stream_t  *dmatx;
-  /**
-   * @brief RX DMA mode bit mask.
-   */
-  uint32_t                  rxdmamode;
-  /**
-   * @brief TX DMA mode bit mask.
-   */
-  uint32_t                  txdmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
-extern SPIDriver SPID3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/TIMv1/gpt_lld.c b/os/hal/platforms/STM32/TIMv1/gpt_lld.c
deleted file mode 100644
index d847a440e..000000000
--- a/os/hal/platforms/STM32/TIMv1/gpt_lld.c
+++ /dev/null
@@ -1,775 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/gpt_lld.c
- * @brief   STM32 GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPTD1 driver identifier.
- * @note    The driver GPTD1 allocates the complex timer TIM1 when enabled.
- */
-#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief   GPTD2 driver identifier.
- * @note    The driver GPTD2 allocates the timer TIM2 when enabled.
- */
-#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief   GPTD3 driver identifier.
- * @note    The driver GPTD3 allocates the timer TIM3 when enabled.
- */
-#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/**
- * @brief   GPTD4 driver identifier.
- * @note    The driver GPTD4 allocates the timer TIM4 when enabled.
- */
-#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-
-/**
- * @brief   GPTD5 driver identifier.
- * @note    The driver GPTD5 allocates the timer TIM5 when enabled.
- */
-#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__)
-GPTDriver GPTD5;
-#endif
-
-/**
- * @brief   GPTD6 driver identifier.
- * @note    The driver GPTD6 allocates the timer TIM6 when enabled.
- */
-#if STM32_GPT_USE_TIM6 || defined(__DOXYGEN__)
-GPTDriver GPTD6;
-#endif
-
-/**
- * @brief   GPTD7 driver identifier.
- * @note    The driver GPTD7 allocates the timer TIM7 when enabled.
- */
-#if STM32_GPT_USE_TIM7 || defined(__DOXYGEN__)
-GPTDriver GPTD7;
-#endif
-
-/**
- * @brief   GPTD8 driver identifier.
- * @note    The driver GPTD8 allocates the timer TIM8 when enabled.
- */
-#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__)
-GPTDriver GPTD8;
-#endif
-
-/**
- * @brief   GPTD9 driver identifier.
- * @note    The driver GPTD9 allocates the timer TIM9 when enabled.
- */
-#if STM32_GPT_USE_TIM9 || defined(__DOXYGEN__)
-GPTDriver GPTD9;
-#endif
-
-/**
- * @brief   GPTD11 driver identifier.
- * @note    The driver GPTD11 allocates the timer TIM11 when enabled.
- */
-#if STM32_GPT_USE_TIM11 || defined(__DOXYGEN__)
-GPTDriver GPTD11;
-#endif
-
-/**
- * @brief   GPTD12 driver identifier.
- * @note    The driver GPTD12 allocates the timer TIM12 when enabled.
- */
-#if STM32_GPT_USE_TIM12 || defined(__DOXYGEN__)
-GPTDriver GPTD12;
-#endif
-
-/**
- * @brief   GPTD14 driver identifier.
- * @note    The driver GPTD14 allocates the timer TIM14 when enabled.
- */
-#if STM32_GPT_USE_TIM14 || defined(__DOXYGEN__)
-GPTDriver GPTD14;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
-  gptp->tim->SR = 0;
-  if (gptp->state == GPT_ONESHOT) {
-    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
-    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
-  }
-  gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_GPT_USE_TIM1
-#if !defined(STM32_TIM1_UP_HANDLER)
-#error "STM32_TIM1_UP_HANDLER not defined"
-#endif
-/**
- * @brief   TIM2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM1 */
-
-#if STM32_GPT_USE_TIM2
-#if !defined(STM32_TIM2_HANDLER)
-#error "STM32_TIM2_HANDLER not defined"
-#endif
-/**
- * @brief   TIM2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM2 */
-
-#if STM32_GPT_USE_TIM3
-#if !defined(STM32_TIM3_HANDLER)
-#error "STM32_TIM3_HANDLER not defined"
-#endif
-/**
- * @brief   TIM3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM3 */
-
-#if STM32_GPT_USE_TIM4
-#if !defined(STM32_TIM4_HANDLER)
-#error "STM32_TIM4_HANDLER not defined"
-#endif
-/**
- * @brief   TIM4 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM4 */
-
-#if STM32_GPT_USE_TIM5
-#if !defined(STM32_TIM5_HANDLER)
-#error "STM32_TIM5_HANDLER not defined"
-#endif
-/**
- * @brief   TIM5 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM5 */
-
-#if STM32_GPT_USE_TIM6
-#if !defined(STM32_TIM6_HANDLER)
-#error "STM32_TIM6_HANDLER not defined"
-#endif
-/**
- * @brief   TIM6 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM6_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM6 */
-
-#if STM32_GPT_USE_TIM7
-#if !defined(STM32_TIM7_HANDLER)
-#error "STM32_TIM7_HANDLER not defined"
-#endif
-/**
- * @brief   TIM7 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM7_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD7);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM7 */
-
-#if STM32_GPT_USE_TIM8
-#if !defined(STM32_TIM8_UP_HANDLER)
-#error "STM32_TIM8_UP_HANDLER not defined"
-#endif
-/**
- * @brief   TIM8 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD8);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM8 */
-
-#if STM32_GPT_USE_TIM9
-#if !defined(STM32_TIM9_HANDLER)
-#error "STM32_TIM9_HANDLER not defined"
-#endif
-/**
- * @brief   TIM9 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM9_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD9);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM9 */
-
-#if STM32_GPT_USE_TIM11
-#if !defined(STM32_TIM11_HANDLER)
-#error "STM32_TIM11_HANDLER not defined"
-#endif
-/**
- * @brief   TIM11 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM11_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD11);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM11 */
-
-#if STM32_GPT_USE_TIM12
-#if !defined(STM32_TIM12_HANDLER)
-#error "STM32_TIM12_HANDLER not defined"
-#endif
-/**
- * @brief   TIM12 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM12_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD12);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM12 */
-
-#if STM32_GPT_USE_TIM14
-#if !defined(STM32_TIM14_HANDLER)
-#error "STM32_TIM14_HANDLER not defined"
-#endif
-/**
- * @brief   TIM14 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM14_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  gpt_lld_serve_interrupt(&GPTD14);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_GPT_USE_TIM14 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if STM32_GPT_USE_TIM1
-  /* Driver initialization.*/
-  GPTD1.tim = STM32_TIM1;
-  gptObjectInit(&GPTD1);
-#endif
-
-#if STM32_GPT_USE_TIM2
-  /* Driver initialization.*/
-  GPTD2.tim = STM32_TIM2;
-  gptObjectInit(&GPTD2);
-#endif
-
-#if STM32_GPT_USE_TIM3
-  /* Driver initialization.*/
-  GPTD3.tim = STM32_TIM3;
-  gptObjectInit(&GPTD3);
-#endif
-
-#if STM32_GPT_USE_TIM4
-  /* Driver initialization.*/
-  GPTD4.tim = STM32_TIM4;
-  gptObjectInit(&GPTD4);
-#endif
-
-#if STM32_GPT_USE_TIM5
-  /* Driver initialization.*/
-  GPTD5.tim = STM32_TIM5;
-  gptObjectInit(&GPTD5);
-#endif
-
-#if STM32_GPT_USE_TIM6
-  /* Driver initialization.*/
-  GPTD6.tim = STM32_TIM6;
-  gptObjectInit(&GPTD6);
-#endif
-
-#if STM32_GPT_USE_TIM7
-  /* Driver initialization.*/
-  GPTD7.tim = STM32_TIM7;
-  gptObjectInit(&GPTD7);
-#endif
-
-#if STM32_GPT_USE_TIM8
-  /* Driver initialization.*/
-  GPTD8.tim = STM32_TIM8;
-  gptObjectInit(&GPTD8);
-#endif
-
-#if STM32_GPT_USE_TIM9
-  /* Driver initialization.*/
-  GPTD9.tim = STM32_TIM9;
-  gptObjectInit(&GPTD9);
-#endif
-
-#if STM32_GPT_USE_TIM11
-  /* Driver initialization.*/
-  GPTD11.tim = STM32_TIM11;
-  gptObjectInit(&GPTD11);
-#endif
-
-#if STM32_GPT_USE_TIM12
-  /* Driver initialization.*/
-  GPTD12.tim = STM32_TIM12;
-  gptObjectInit(&GPTD12);
-#endif
-
-#if STM32_GPT_USE_TIM14
-  /* Driver initialization.*/
-  GPTD14.tim = STM32_TIM14;
-  gptObjectInit(&GPTD14);
-#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-  uint16_t psc;
-
-  if (gptp->state == GPT_STOP) {
-    /* Clock activation.*/
-#if STM32_GPT_USE_TIM1
-    if (&GPTD1 == gptp) {
-      rccEnableTIM1(FALSE);
-      rccResetTIM1();
-      nvicEnableVector(STM32_TIM1_UP_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
-#if defined(STM32_TIM1CLK)
-      gptp->clock = STM32_TIM1CLK;
-#else
-      gptp->clock = STM32_TIMCLK2;
-#endif
-    }
-#endif
-#if STM32_GPT_USE_TIM2
-    if (&GPTD2 == gptp) {
-      rccEnableTIM2(FALSE);
-      rccResetTIM2();
-      nvicEnableVector(STM32_TIM2_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK1;
-    }
-#endif
-#if STM32_GPT_USE_TIM3
-    if (&GPTD3 == gptp) {
-      rccEnableTIM3(FALSE);
-      rccResetTIM3();
-      nvicEnableVector(STM32_TIM3_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK1;
-    }
-#endif
-#if STM32_GPT_USE_TIM4
-    if (&GPTD4 == gptp) {
-      rccEnableTIM4(FALSE);
-      rccResetTIM4();
-      nvicEnableVector(STM32_TIM4_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK1;
-    }
-#endif
-
-#if STM32_GPT_USE_TIM5
-    if (&GPTD5 == gptp) {
-      rccEnableTIM5(FALSE);
-      rccResetTIM5();
-      nvicEnableVector(STM32_TIM5_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK1;
-    }
-#endif
-
-#if STM32_GPT_USE_TIM6
-    if (&GPTD6 == gptp) {
-      rccEnableTIM6(FALSE);
-      rccResetTIM6();
-      nvicEnableVector(STM32_TIM6_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM6_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK1;
-    }
-#endif
-
-#if STM32_GPT_USE_TIM7
-    if (&GPTD7 == gptp) {
-      rccEnableTIM7(FALSE);
-      rccResetTIM7();
-      nvicEnableVector(STM32_TIM7_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM7_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK1;
-    }
-#endif
-
-#if STM32_GPT_USE_TIM8
-    if (&GPTD8 == gptp) {
-      rccEnableTIM8(FALSE);
-      rccResetTIM8();
-      nvicEnableVector(STM32_TIM8_UP_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY));
-#if defined(STM32_TIM8CLK)
-      gptp->clock = STM32_TIM8CLK;
-#else
-      gptp->clock = STM32_TIMCLK2;
-#endif
-    }
-#endif
-
-#if STM32_GPT_USE_TIM9
-    if (&GPTD9 == gptp) {
-      rccEnableTIM9(FALSE);
-      rccResetTIM9();
-      nvicEnableVector(STM32_TIM9_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM9_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK2;
-    }
-#endif
-
-#if STM32_GPT_USE_TIM11
-    if (&GPTD11 == gptp) {
-      rccEnableTIM11(FALSE);
-      rccResetTIM11();
-      nvicEnableVector(STM32_TIM11_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM11_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK2;
-    }
-#endif
-
-#if STM32_GPT_USE_TIM12
-    if (&GPTD12 == gptp) {
-      rccEnableTIM12(FALSE);
-      rccResetTIM12();
-      nvicEnableVector(STM32_TIM12_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM12_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK1;
-    }
-#endif
-
-#if STM32_GPT_USE_TIM14
-    if (&GPTD14 == gptp) {
-      rccEnableTIM14(FALSE);
-      rccResetTIM14();
-      nvicEnableVector(STM32_TIM14_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM14_IRQ_PRIORITY));
-      gptp->clock = STM32_TIMCLK1;
-    }
-#endif
-  }
-
-  /* Prescaler value calculation.*/
-  psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
-  chDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
-              "gpt_lld_start(), #1", "invalid frequency");
-
-  /* Timer configuration.*/
-  gptp->tim->CR1  = 0;                          /* Initially stopped.       */
-  gptp->tim->CR2  = STM32_TIM_CR2_CCDS;         /* DMA on UE (if any).      */
-  gptp->tim->PSC  = psc;                        /* Prescaler value.         */
-  gptp->tim->DIER = gptp->config->dier &        /* DMA-related DIER bits.   */
-                    STM32_TIM_DIER_IRQ_MASK;
-  gptp->tim->SR   = 0;                          /* Clear pending IRQs.      */
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
-  if (gptp->state == GPT_READY) {
-    gptp->tim->CR1  = 0;                        /* Timer disabled.          */
-    gptp->tim->DIER = 0;                        /* All IRQs disabled.       */
-    gptp->tim->SR   = 0;                        /* Clear pending IRQs.      */
-
-#if STM32_GPT_USE_TIM1
-    if (&GPTD1 == gptp) {
-      nvicDisableVector(STM32_TIM1_UP_NUMBER);
-      rccDisableTIM1(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM2
-    if (&GPTD2 == gptp) {
-      nvicDisableVector(STM32_TIM2_NUMBER);
-      rccDisableTIM2(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM3
-    if (&GPTD3 == gptp) {
-      nvicDisableVector(STM32_TIM3_NUMBER);
-      rccDisableTIM3(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM4
-    if (&GPTD4 == gptp) {
-      nvicDisableVector(STM32_TIM4_NUMBER);
-      rccDisableTIM4(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM5
-    if (&GPTD5 == gptp) {
-      nvicDisableVector(STM32_TIM5_NUMBER);
-      rccDisableTIM5(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM6
-    if (&GPTD6 == gptp) {
-      nvicDisableVector(STM32_TIM6_NUMBER);
-      rccDisableTIM6(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM7
-    if (&GPTD7 == gptp) {
-      nvicDisableVector(STM32_TIM7_NUMBER);
-      rccDisableTIM7(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM8
-    if (&GPTD8 == gptp) {
-      nvicDisableVector(STM32_TIM8_UP_NUMBER);
-      rccDisableTIM8(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM9
-    if (&GPTD9 == gptp) {
-      nvicDisableVector(STM32_TIM9_NUMBER);
-      rccDisableTIM9(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM11
-    if (&GPTD11 == gptp) {
-      nvicDisableVector(STM32_TIM11_NUMBER);
-      rccDisableTIM11(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM12
-    if (&GPTD12 == gptp) {
-      nvicDisableVector(STM32_TIM12_NUMBER);
-      rccDisableTIM12(FALSE);
-    }
-#endif
-#if STM32_GPT_USE_TIM14
-    if (&GPTD14 == gptp) {
-      nvicDisableVector(STM32_TIM14_NUMBER);
-      rccDisableTIM14(FALSE);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tim->ARR   = (uint32_t)(interval - 1);  /* Time constant.           */
-  gptp->tim->EGR   = STM32_TIM_EGR_UG;          /* Update event.            */
-  gptp->tim->CNT   = 0;                         /* Reset counter.           */
-
-  /* NOTE: After generating the UG event it takes several clock cycles before
-     SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
-     before the clearing of SR, to give it some time.*/
-  gptp->tim->SR    = 0;                         /* Clear pending IRQs.      */
-  gptp->tim->DIER |= STM32_TIM_DIER_UIE;        /* Update Event IRQ enabled.*/
-  gptp->tim->CR1   = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
-  gptp->tim->CR1   = 0;                         /* Initially stopped.       */
-  gptp->tim->SR    = 0;                         /* Clear pending IRQs.      */
-
-  /* All interrupts disabled.*/
-  gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-  gptp->tim->ARR  = (uint32_t)(interval - 1);   /* Time constant.           */
-  gptp->tim->EGR  = STM32_TIM_EGR_UG;           /* Update event.            */
-  gptp->tim->SR   = 0;                          /* Clear pending IRQs.      */
-  gptp->tim->CR1  = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
-  while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
-    ;
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/TIMv1/gpt_lld.h b/os/hal/platforms/STM32/TIMv1/gpt_lld.h
deleted file mode 100644
index 56dc04f6b..000000000
--- a/os/hal/platforms/STM32/TIMv1/gpt_lld.h
+++ /dev/null
@@ -1,512 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/gpt_lld.h
- * @brief   STM32 GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#include "stm32_tim.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   GPTD1 driver enable switch.
- * @details If set to @p TRUE the support for GPTD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM1                  FALSE
-#endif
-
-/**
- * @brief   GPTD2 driver enable switch.
- * @details If set to @p TRUE the support for GPTD2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM2                  FALSE
-#endif
-
-/**
- * @brief   GPTD3 driver enable switch.
- * @details If set to @p TRUE the support for GPTD3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM3                  FALSE
-#endif
-
-/**
- * @brief   GPTD4 driver enable switch.
- * @details If set to @p TRUE the support for GPTD4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM4                  FALSE
-#endif
-
-/**
- * @brief   GPTD5 driver enable switch.
- * @details If set to @p TRUE the support for GPTD5 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM5                  FALSE
-#endif
-
-/**
- * @brief   GPTD6 driver enable switch.
- * @details If set to @p TRUE the support for GPTD6 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM6) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM6                  FALSE
-#endif
-
-/**
- * @brief   GPTD7 driver enable switch.
- * @details If set to @p TRUE the support for GPTD7 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM7) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM7                  FALSE
-#endif
-
-/**
- * @brief   GPTD8 driver enable switch.
- * @details If set to @p TRUE the support for GPTD8 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM8                  FALSE
-#endif
-
-/**
- * @brief   GPTD9 driver enable switch.
- * @details If set to @p TRUE the support for GPTD9 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM9) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM9                  FALSE
-#endif
-
-/**
- * @brief   GPTD11 driver enable switch.
- * @details If set to @p TRUE the support for GPTD11 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM11) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM11                 FALSE
-#endif
-
-/**
- * @brief   GPTD12 driver enable switch.
- * @details If set to @p TRUE the support for GPTD12 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM12) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM12                 FALSE
-#endif
-
-/**
- * @brief   GPTD14 driver enable switch.
- * @details If set to @p TRUE the support for GPTD14 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM14) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM14                 FALSE
-#endif
-
-/**
- * @brief   GPTD1 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM1_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   GPTD2 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM2_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   GPTD3 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM3_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   GPTD4 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM4_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   GPTD5 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM5_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   GPTD6 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM6_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   GPTD7 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM7_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM7_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   GPTD8 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM8_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   GPTD9 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM9_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   GPTD11 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM11_IRQ_PRIORITY        7
-#endif
-
-/**
- * @brief   GPTD12 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM12_IRQ_PRIORITY        7
-#endif
-
-/**
- * @brief   GPTD14 interrupt priority level setting.
- */
-#if !defined(STM32_GPT_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_GPT_TIM14_IRQ_PRIORITY        7
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_GPT_USE_TIM1 && !STM32_HAS_TIM1
-#error "TIM1 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM2 && !STM32_HAS_TIM2
-#error "TIM2 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM3 && !STM32_HAS_TIM3
-#error "TIM3 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM4 && !STM32_HAS_TIM4
-#error "TIM4 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM5 && !STM32_HAS_TIM5
-#error "TIM5 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM6 && !STM32_HAS_TIM6
-#error "TIM6 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM7 && !STM32_HAS_TIM7
-#error "TIM7 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM8 && !STM32_HAS_TIM8
-#error "TIM8 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM9 && !STM32_HAS_TIM9
-#error "TIM9 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM11 && !STM32_HAS_TIM11
-#error "TIM11 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM12 && !STM32_HAS_TIM12
-#error "TIM12 not present in the selected device"
-#endif
-
-#if STM32_GPT_USE_TIM14 && !STM32_HAS_TIM14
-#error "TIM14 not present in the selected device"
-#endif
-
-#if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 &&                           \
-    !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 &&  \
-    !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM6 &&  \
-    !STM32_GPT_USE_TIM7 && !STM32_GPT_USE_TIM8 &&  \
-    !STM32_GPT_USE_TIM9 && !STM32_GPT_USE_TIM11 && \
-    !STM32_GPT_USE_TIM12 && !STM32_GPT_USE_TIM14
-#error "GPT driver activated but no TIM peripheral assigned"
-#endif
-
-#if STM32_GPT_USE_TIM1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM1"
-#endif
-
-#if STM32_GPT_USE_TIM2 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM2"
-#endif
-
-#if STM32_GPT_USE_TIM3 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM3"
-#endif
-
-#if STM32_GPT_USE_TIM4 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM4"
-#endif
-
-#if STM32_GPT_USE_TIM5 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM5"
-#endif
-
-#if STM32_GPT_USE_TIM6 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM6_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM6"
-#endif
-
-#if STM32_GPT_USE_TIM7 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM7_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM7"
-#endif
-
-#if STM32_GPT_USE_TIM8 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM8"
-#endif
-
-#if STM32_GPT_USE_TIM9 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM9_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM9"
-#endif
-
-#if STM32_GPT_USE_TIM11 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM11_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM11"
-#endif
-
-#if STM32_GPT_USE_TIM12 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM12_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM12"
-#endif
-
-#if STM32_GPT_USE_TIM14 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM14_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM14"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief TIM DIER register initialization data.
-   * @note  The value of this field should normally be equal to zero.
-   * @note  Only the DMA-related bits can be specified in this field.
-   */
-  uint32_t                  dier;
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-#if defined(GPT_DRIVER_EXT_FIELDS)
-  GPT_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Timer base clock.
-   */
-  uint32_t                  clock;
-  /**
-   * @brief Pointer to the TIMx registers block.
-   */
-  stm32_tim_t               *tim;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Changes the interval of GPT peripheral.
- * @details This function changes the interval of a running GPT unit.
- * @pre     The GPT unit must have been activated using @p gptStart().
- * @pre     The GPT unit must have been running in continuous mode using
- *          @p gptStartContinuous().
- * @post    The GPT unit interval is changed to the new value.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- * @param[in] interval  new cycle time in timer ticks
- * @notapi
- */
-#define gpt_lld_change_interval(gptp, interval)                               \
-  ((gptp)->tim->ARR = (uint32_t)((interval) - 1))
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if STM32_GPT_USE_TIM2 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if STM32_GPT_USE_TIM3 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#if STM32_GPT_USE_TIM4 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-
-#if STM32_GPT_USE_TIM5 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD5;
-#endif
-
-#if STM32_GPT_USE_TIM6 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD6;
-#endif
-
-#if STM32_GPT_USE_TIM7 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD7;
-#endif
-
-#if STM32_GPT_USE_TIM8 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD8;
-#endif
-
-#if STM32_GPT_USE_TIM9 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD9;
-#endif
-
-#if STM32_GPT_USE_TIM11 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD11;
-#endif
-
-#if STM32_GPT_USE_TIM12 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD12;
-#endif
-
-#if STM32_GPT_USE_TIM14 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD14;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/TIMv1/icu_lld.c b/os/hal/platforms/STM32/TIMv1/icu_lld.c
deleted file mode 100644
index ded4f806c..000000000
--- a/os/hal/platforms/STM32/TIMv1/icu_lld.c
+++ /dev/null
@@ -1,653 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Fabio Utzig and
-   Xo Wang.
- */
-
-/**
- * @file    STM32/icu_lld.c
- * @brief   STM32 ICU subsystem low level driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ICUD1 driver identifier.
- * @note    The driver ICUD1 allocates the complex timer TIM1 when enabled.
- */
-#if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-
-/**
- * @brief   ICUD2 driver identifier.
- * @note    The driver ICUD1 allocates the timer TIM2 when enabled.
- */
-#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__)
-ICUDriver ICUD2;
-#endif
-
-/**
- * @brief   ICUD3 driver identifier.
- * @note    The driver ICUD1 allocates the timer TIM3 when enabled.
- */
-#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__)
-ICUDriver ICUD3;
-#endif
-
-/**
- * @brief   ICUD4 driver identifier.
- * @note    The driver ICUD4 allocates the timer TIM4 when enabled.
- */
-#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__)
-ICUDriver ICUD4;
-#endif
-
-/**
- * @brief   ICUD5 driver identifier.
- * @note    The driver ICUD5 allocates the timer TIM5 when enabled.
- */
-#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__)
-ICUDriver ICUD5;
-#endif
-
-/**
- * @brief   ICUD8 driver identifier.
- * @note    The driver ICUD8 allocates the timer TIM8 when enabled.
- */
-#if STM32_ICU_USE_TIM8 || defined(__DOXYGEN__)
-ICUDriver ICUD8;
-#endif
-
-/**
- * @brief   ICUD9 driver identifier.
- * @note    The driver ICUD9 allocates the timer TIM9 when enabled.
- */
-#if STM32_ICU_USE_TIM9 || defined(__DOXYGEN__)
-ICUDriver ICUD9;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
-  uint16_t sr;
-
-  sr  = icup->tim->SR;
-  sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
-  icup->tim->SR = ~sr;
-  if (icup->config->channel == ICU_CHANNEL_1) {
-    if ((sr & STM32_TIM_SR_CC1IF) != 0)
-      _icu_isr_invoke_period_cb(icup);
-    if ((sr & STM32_TIM_SR_CC2IF) != 0)
-      _icu_isr_invoke_width_cb(icup);
-  } else {
-    if ((sr & STM32_TIM_SR_CC1IF) != 0)
-      _icu_isr_invoke_width_cb(icup);
-    if ((sr & STM32_TIM_SR_CC2IF) != 0)
-      _icu_isr_invoke_period_cb(icup);
-  }
-  if ((sr & STM32_TIM_SR_UIF) != 0)
-    _icu_isr_invoke_overflow_cb(icup);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_ICU_USE_TIM1
-#if !defined(STM32_TIM1_UP_HANDLER)
-#error "STM32_TIM1_UP_HANDLER not defined"
-#endif
-/**
- * @brief   TIM1 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(STM32_TIM1_CC_HANDLER)
-#error "STM32_TIM1_CC_HANDLER not defined"
-#endif
-/**
- * @brief   TIM1 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ICU_USE_TIM1 */
-
-#if STM32_ICU_USE_TIM2
-#if !defined(STM32_TIM2_HANDLER)
-#error "STM32_TIM2_HANDLER not defined"
-#endif
-/**
- * @brief   TIM2 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ICU_USE_TIM2 */
-
-#if STM32_ICU_USE_TIM3
-#if !defined(STM32_TIM3_HANDLER)
-#error "STM32_TIM3_HANDLER not defined"
-#endif
-/**
- * @brief   TIM3 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ICU_USE_TIM3 */
-
-#if STM32_ICU_USE_TIM4
-#if !defined(STM32_TIM4_HANDLER)
-#error "STM32_TIM4_HANDLER not defined"
-#endif
-/**
- * @brief   TIM4 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ICU_USE_TIM4 */
-
-#if STM32_ICU_USE_TIM5
-#if !defined(STM32_TIM5_HANDLER)
-#error "STM32_TIM5_HANDLER not defined"
-#endif
-/**
- * @brief   TIM5 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ICU_USE_TIM5 */
-
-#if STM32_ICU_USE_TIM8
-#if !defined(STM32_TIM8_UP_HANDLER)
-#error "STM32_TIM8_UP_HANDLER not defined"
-#endif
-/**
- * @brief   TIM8 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD8);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(STM32_TIM8_CC_HANDLER)
-#error "STM32_TIM8_CC_HANDLER not defined"
-#endif
-/**
- * @brief   TIM8 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD8);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ICU_USE_TIM8 */
-
-#if STM32_ICU_USE_TIM9
-#if !defined(STM32_TIM9_HANDLER)
-#error "STM32_TIM9_HANDLER not defined"
-#endif
-/**
- * @brief   TIM9 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM9_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  icu_lld_serve_interrupt(&ICUD9);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ICU_USE_TIM9 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
-#if STM32_ICU_USE_TIM1
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD1);
-  ICUD1.tim = STM32_TIM1;
-#endif
-
-#if STM32_ICU_USE_TIM2
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD2);
-  ICUD2.tim = STM32_TIM2;
-#endif
-
-#if STM32_ICU_USE_TIM3
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD3);
-  ICUD3.tim = STM32_TIM3;
-#endif
-
-#if STM32_ICU_USE_TIM4
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD4);
-  ICUD4.tim = STM32_TIM4;
-#endif
-
-#if STM32_ICU_USE_TIM5
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD5);
-  ICUD5.tim = STM32_TIM5;
-#endif
-
-#if STM32_ICU_USE_TIM8
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD8);
-  ICUD8.tim = STM32_TIM8;
-#endif
-
-#if STM32_ICU_USE_TIM9
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD9);
-  ICUD9.tim = STM32_TIM9;
-#endif
-}
-
-/**
- * @brief   Configures and activates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-  uint32_t psc;
-
-  chDbgAssert((icup->config->channel == ICU_CHANNEL_1) ||
-              (icup->config->channel == ICU_CHANNEL_2),
-              "icu_lld_start(), #1", "invalid input");
-
-  if (icup->state == ICU_STOP) {
-    /* Clock activation and timer reset.*/
-#if STM32_ICU_USE_TIM1
-    if (&ICUD1 == icup) {
-      rccEnableTIM1(FALSE);
-      rccResetTIM1();
-      nvicEnableVector(STM32_TIM1_UP_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));
-      nvicEnableVector(STM32_TIM1_CC_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));
-#if defined(STM32_TIM1CLK)
-      icup->clock = STM32_TIM1CLK;
-#else
-      icup->clock = STM32_TIMCLK2;
-#endif
-    }
-#endif
-#if STM32_ICU_USE_TIM2
-    if (&ICUD2 == icup) {
-      rccEnableTIM2(FALSE);
-      rccResetTIM2();
-      nvicEnableVector(STM32_TIM2_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY));
-      icup->clock = STM32_TIMCLK1;
-    }
-#endif
-#if STM32_ICU_USE_TIM3
-    if (&ICUD3 == icup) {
-      rccEnableTIM3(FALSE);
-      rccResetTIM3();
-      nvicEnableVector(STM32_TIM3_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY));
-      icup->clock = STM32_TIMCLK1;
-    }
-#endif
-#if STM32_ICU_USE_TIM4
-    if (&ICUD4 == icup) {
-      rccEnableTIM4(FALSE);
-      rccResetTIM4();
-      nvicEnableVector(STM32_TIM4_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY));
-      icup->clock = STM32_TIMCLK1;
-    }
-#endif
-#if STM32_ICU_USE_TIM5
-    if (&ICUD5 == icup) {
-      rccEnableTIM5(FALSE);
-      rccResetTIM5();
-      nvicEnableVector(STM32_TIM5_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY));
-      icup->clock = STM32_TIMCLK1;
-    }
-#endif
-#if STM32_ICU_USE_TIM8
-    if (&ICUD8 == icup) {
-      rccEnableTIM8(FALSE);
-      rccResetTIM8();
-      nvicEnableVector(STM32_TIM8_UP_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
-      nvicEnableVector(STM32_TIM8_CC_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
-#if defined(STM32_TIM8CLK)
-      icup->clock = STM32_TIM8CLK;
-#else
-      icup->clock = STM32_TIMCLK2;
-#endif
-    }
-#endif
-#if STM32_ICU_USE_TIM9
-    if (&ICUD9 == icup) {
-      rccEnableTIM9(FALSE);
-      rccResetTIM9();
-      nvicEnableVector(STM32_TIM9_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM9_IRQ_PRIORITY));
-      icup->clock = STM32_TIMCLK2;
-    }
-#endif
-  }
-  else {
-    /* Driver re-configuration scenario, it must be stopped first.*/
-    icup->tim->CR1    = 0;                  /* Timer disabled.              */
-    icup->tim->DIER   = icup->config->dier &/* DMA-related DIER settings.   */
-                        ~STM32_TIM_DIER_IRQ_MASK;
-    icup->tim->SR     = 0;                  /* Clear eventual pending IRQs. */
-    icup->tim->CCR[0] = 0;                  /* Comparator 1 disabled.       */
-    icup->tim->CCR[1] = 0;                  /* Comparator 2 disabled.       */
-    icup->tim->CNT    = 0;                  /* Counter reset to zero.       */
-  }
-
-  /* Timer configuration.*/
-  psc = (icup->clock / icup->config->frequency) - 1;
-  chDbgAssert((psc <= 0xFFFF) &&
-              ((psc + 1) * icup->config->frequency) == icup->clock,
-              "icu_lld_start(), #1", "invalid frequency");
-  icup->tim->PSC  = (uint16_t)psc;
-  icup->tim->ARR   = 0xFFFF;
-
-  if (icup->config->channel == ICU_CHANNEL_1) {
-    /* Selected input 1.
-       CCMR1_CC1S = 01 = CH1 Input on TI1.
-       CCMR1_CC2S = 10 = CH2 Input on TI1.*/
-    icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(1) | STM32_TIM_CCMR1_CC2S(2);
-
-    /* SMCR_TS  = 101, input is TI1FP1.
-       SMCR_SMS = 100, reset on rising edge.*/
-    icup->tim->SMCR  = STM32_TIM_SMCR_TS(5) | STM32_TIM_SMCR_SMS(4);
-
-    /* The CCER settings depend on the selected trigger mode.
-       ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge.
-       ICU_INPUT_ACTIVE_LOW:  Active on falling edge, idle on rising edge.*/
-    if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH)
-      icup->tim->CCER = STM32_TIM_CCER_CC1E |
-                        STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P;
-    else
-      icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P |
-                        STM32_TIM_CCER_CC2E;
-
-    /* Direct pointers to the capture registers in order to make reading
-       data faster from within callbacks.*/
-    icup->wccrp = &icup->tim->CCR[1];
-    icup->pccrp = &icup->tim->CCR[0];
-  } else {
-    /* Selected input 2.
-       CCMR1_CC1S = 10 = CH1 Input on TI2.
-       CCMR1_CC2S = 01 = CH2 Input on TI2.*/
-    icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(2) | STM32_TIM_CCMR1_CC2S(1);
-
-    /* SMCR_TS  = 110, input is TI2FP2.
-       SMCR_SMS = 100, reset on rising edge.*/
-    icup->tim->SMCR  = STM32_TIM_SMCR_TS(6) | STM32_TIM_SMCR_SMS(4);
-
-    /* The CCER settings depend on the selected trigger mode.
-       ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge.
-       ICU_INPUT_ACTIVE_LOW:  Active on falling edge, idle on rising edge.*/
-    if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH)
-      icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P |
-                        STM32_TIM_CCER_CC2E;
-    else
-      icup->tim->CCER = STM32_TIM_CCER_CC1E |
-                        STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P;
-
-    /* Direct pointers to the capture registers in order to make reading
-       data faster from within callbacks.*/
-    icup->wccrp = &icup->tim->CCR[0];
-    icup->pccrp = &icup->tim->CCR[1];
-  }
-}
-
-/**
- * @brief   Deactivates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
-  if (icup->state == ICU_READY) {
-    /* Clock deactivation.*/
-    icup->tim->CR1  = 0;                    /* Timer disabled.              */
-    icup->tim->DIER = 0;                    /* All IRQs disabled.           */
-    icup->tim->SR   = 0;                    /* Clear eventual pending IRQs. */
-
-#if STM32_ICU_USE_TIM1
-    if (&ICUD1 == icup) {
-      nvicDisableVector(STM32_TIM1_UP_NUMBER);
-      nvicDisableVector(STM32_TIM1_CC_NUMBER);
-      rccDisableTIM1(FALSE);
-    }
-#endif
-#if STM32_ICU_USE_TIM2
-    if (&ICUD2 == icup) {
-      nvicDisableVector(STM32_TIM2_NUMBER);
-      rccDisableTIM2(FALSE);
-    }
-#endif
-#if STM32_ICU_USE_TIM3
-    if (&ICUD3 == icup) {
-      nvicDisableVector(STM32_TIM3_NUMBER);
-      rccDisableTIM3(FALSE);
-    }
-#endif
-#if STM32_ICU_USE_TIM4
-    if (&ICUD4 == icup) {
-      nvicDisableVector(STM32_TIM4_NUMBER);
-      rccDisableTIM4(FALSE);
-    }
-#endif
-#if STM32_ICU_USE_TIM5
-    if (&ICUD5 == icup) {
-      nvicDisableVector(STM32_TIM5_NUMBER);
-      rccDisableTIM5(FALSE);
-    }
-#endif
-#if STM32_ICU_USE_TIM8
-    if (&ICUD8 == icup) {
-      nvicDisableVector(STM32_TIM8_UP_NUMBER);
-      nvicDisableVector(STM32_TIM8_CC_NUMBER);
-      rccDisableTIM8(FALSE);
-    }
-#endif
-#if STM32_ICU_USE_TIM9
-    if (&ICUD9 == icup) {
-      nvicDisableVector(STM32_TIM9_NUMBER);
-      rccDisableTIM9(FALSE);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Enables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
-  icup->tim->EGR |= STM32_TIM_EGR_UG;
-  icup->tim->SR = 0;                        /* Clear pending IRQs (if any). */
-  if (icup->config->channel == ICU_CHANNEL_1) {
-    if (icup->config->period_cb != NULL)
-      icup->tim->DIER |= STM32_TIM_DIER_CC1IE;
-    if (icup->config->width_cb != NULL)
-      icup->tim->DIER |= STM32_TIM_DIER_CC2IE;
-  } else {
-    if (icup->config->width_cb != NULL)
-      icup->tim->DIER |= STM32_TIM_DIER_CC1IE;
-    if (icup->config->period_cb != NULL)
-      icup->tim->DIER |= STM32_TIM_DIER_CC2IE;
-  }
-  if (icup->config->overflow_cb != NULL)
-    icup->tim->DIER |= STM32_TIM_DIER_UIE;
-  icup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
-}
-
-/**
- * @brief   Disables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
-  icup->tim->CR1   = 0;                     /* Initially stopped.           */
-  icup->tim->SR    = 0;                     /* Clear pending IRQs (if any). */
-
-  /* All interrupts disabled.*/
-  icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/TIMv1/icu_lld.h b/os/hal/platforms/STM32/TIMv1/icu_lld.h
deleted file mode 100644
index 6c2c1b93f..000000000
--- a/os/hal/platforms/STM32/TIMv1/icu_lld.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/icu_lld.h
- * @brief   STM32 ICU subsystem low level driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#include "stm32_tim.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ICUD1 driver enable switch.
- * @details If set to @p TRUE the support for ICUD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__)
-#define STM32_ICU_USE_TIM1                  FALSE
-#endif
-
-/**
- * @brief   ICUD2 driver enable switch.
- * @details If set to @p TRUE the support for ICUD2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__)
-#define STM32_ICU_USE_TIM2                  FALSE
-#endif
-
-/**
- * @brief   ICUD3 driver enable switch.
- * @details If set to @p TRUE the support for ICUD3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__)
-#define STM32_ICU_USE_TIM3                  FALSE
-#endif
-
-/**
- * @brief   ICUD4 driver enable switch.
- * @details If set to @p TRUE the support for ICUD4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__)
-#define STM32_ICU_USE_TIM4                  FALSE
-#endif
-
-/**
- * @brief   ICUD5 driver enable switch.
- * @details If set to @p TRUE the support for ICUD5 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__)
-#define STM32_ICU_USE_TIM5                  FALSE
-#endif
-
-/**
- * @brief   ICUD8 driver enable switch.
- * @details If set to @p TRUE the support for ICUD8 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__)
-#define STM32_ICU_USE_TIM8                  FALSE
-#endif
-
-/**
- * @brief   ICUD9 driver enable switch.
- * @details If set to @p TRUE the support for ICUD9 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ICU_USE_TIM9) || defined(__DOXYGEN__)
-#define STM32_ICU_USE_TIM9                  FALSE
-#endif
-
-/**
- * @brief   ICUD1 interrupt priority level setting.
- */
-#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ICU_TIM1_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD2 interrupt priority level setting.
- */
-#if !defined(STM32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ICU_TIM2_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD3 interrupt priority level setting.
- */
-#if !defined(STM32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ICU_TIM3_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD4 interrupt priority level setting.
- */
-#if !defined(STM32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ICU_TIM4_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD5 interrupt priority level setting.
- */
-#if !defined(STM32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ICU_TIM5_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD8 interrupt priority level setting.
- */
-#if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ICU_TIM8_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   ICUD9 interrupt priority level setting.
- */
-#if !defined(STM32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ICU_TIM9_IRQ_PRIORITY         7
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_ICU_USE_TIM1 && !STM32_HAS_TIM1
-#error "TIM1 not present in the selected device"
-#endif
-
-#if STM32_ICU_USE_TIM2 && !STM32_HAS_TIM2
-#error "TIM2 not present in the selected device"
-#endif
-
-#if STM32_ICU_USE_TIM3 && !STM32_HAS_TIM3
-#error "TIM3 not present in the selected device"
-#endif
-
-#if STM32_ICU_USE_TIM4 && !STM32_HAS_TIM4
-#error "TIM4 not present in the selected device"
-#endif
-
-#if STM32_ICU_USE_TIM5 && !STM32_HAS_TIM5
-#error "TIM5 not present in the selected device"
-#endif
-
-#if STM32_ICU_USE_TIM8 && !STM32_HAS_TIM8
-#error "TIM8 not present in the selected device"
-#endif
-
-#if STM32_ICU_USE_TIM9 && !STM32_HAS_TIM9
-#error "TIM9 not present in the selected device"
-#endif
-
-#if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 &&                           \
-    !STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 &&                           \
-    !STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 &&                           \
-    !STM32_ICU_USE_TIM9
-#error "ICU driver activated but no TIM peripheral assigned"
-#endif
-
-#if STM32_ICU_USE_TIM1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM1"
-#endif
-
-#if STM32_ICU_USE_TIM2 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM2"
-#endif
-
-#if STM32_ICU_USE_TIM3 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM3"
-#endif
-
-#if STM32_ICU_USE_TIM4 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM4"
-#endif
-
-#if STM32_ICU_USE_TIM5 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM5"
-#endif
-
-#if STM32_ICU_USE_TIM8 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM8"
-#endif
-
-#if STM32_ICU_USE_TIM9 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM9"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ICU driver mode.
- */
-typedef enum {
-  ICU_INPUT_ACTIVE_HIGH = 0,        /**< Trigger on rising edge.            */
-  ICU_INPUT_ACTIVE_LOW = 1,         /**< Trigger on falling edge.           */
-} icumode_t;
-
-/**
- * @brief   ICU frequency type.
- */
-typedef uint32_t icufreq_t;
-
-/**
- * @brief   ICU channel type.
- */
-typedef enum {
-  ICU_CHANNEL_1 = 0,              /**< Use TIMxCH1.      */
-  ICU_CHANNEL_2 = 1,              /**< Use TIMxCH2.      */
-} icuchannel_t;
-
-/**
- * @brief   ICU counter type.
- */
-typedef uint16_t icucnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Driver mode.
-   */
-  icumode_t                 mode;
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  icufreq_t                 frequency;
-  /**
-   * @brief   Callback for pulse width measurement.
-   */
-  icucallback_t             width_cb;
-  /**
-   * @brief   Callback for cycle period measurement.
-   */
-  icucallback_t             period_cb;
-  /**
-   * @brief   Callback for timer overflow.
-   */
-  icucallback_t             overflow_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Timer input channel to be used.
-   * @note    Only inputs TIMx 1 and 2 are supported.
-   */
-  icuchannel_t              channel;
-  /**
-   * @brief TIM DIER register initialization data.
-   * @note  The value of this field should normally be equal to zero.
-   * @note  Only the DMA-related bits can be specified in this field.
-   */
-  uint32_t                  dier;
-} ICUConfig;
-
-/**
- * @brief   Structure representing an ICU driver.
- */
-struct ICUDriver {
-  /**
-   * @brief Driver state.
-   */
-  icustate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ICUConfig           *config;
-#if defined(ICU_DRIVER_EXT_FIELDS)
-  ICU_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Timer base clock.
-   */
-  uint32_t                  clock;
-  /**
-   * @brief Pointer to the TIMx registers block.
-   */
-  stm32_tim_t               *tim;
-  /**
-   * @brief CCR register used for width capture.
-   */
-  volatile uint32_t         *wccrp;
-  /**
-   * @brief CCR register used for period capture.
-   */
-  volatile uint32_t         *pccrp;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- *          edge and the stop edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
-
-/**
- * @brief   Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- *          edge and the next start edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_ICU_USE_TIM1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-
-#if STM32_ICU_USE_TIM2 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD2;
-#endif
-
-#if STM32_ICU_USE_TIM3 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD3;
-#endif
-
-#if STM32_ICU_USE_TIM4 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD4;
-#endif
-
-#if STM32_ICU_USE_TIM5 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD5;
-#endif
-
-#if STM32_ICU_USE_TIM8 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD8;
-#endif
-
-#if STM32_ICU_USE_TIM9 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD9;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void icu_lld_init(void);
-  void icu_lld_start(ICUDriver *icup);
-  void icu_lld_stop(ICUDriver *icup);
-  void icu_lld_enable(ICUDriver *icup);
-  void icu_lld_disable(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/TIMv1/pwm_lld.c b/os/hal/platforms/STM32/TIMv1/pwm_lld.c
deleted file mode 100644
index 1968ffcfb..000000000
--- a/os/hal/platforms/STM32/TIMv1/pwm_lld.c
+++ /dev/null
@@ -1,713 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/pwm_lld.c
- * @brief   STM32 PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PWMD1 driver identifier.
- * @note    The driver PWMD1 allocates the complex timer TIM1 when enabled.
- */
-#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief   PWMD2 driver identifier.
- * @note    The driver PWMD2 allocates the timer TIM2 when enabled.
- */
-#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief   PWMD3 driver identifier.
- * @note    The driver PWMD3 allocates the timer TIM3 when enabled.
- */
-#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief   PWMD4 driver identifier.
- * @note    The driver PWMD4 allocates the timer TIM4 when enabled.
- */
-#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/**
- * @brief   PWMD5 driver identifier.
- * @note    The driver PWMD5 allocates the timer TIM5 when enabled.
- */
-#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__)
-PWMDriver PWMD5;
-#endif
-
-/**
- * @brief   PWMD8 driver identifier.
- * @note    The driver PWMD8 allocates the timer TIM8 when enabled.
- */
-#if STM32_PWM_USE_TIM8 || defined(__DOXYGEN__)
-PWMDriver PWMD8;
-#endif
-
-/**
- * @brief   PWMD9 driver identifier.
- * @note    The driver PWMD9 allocates the timer TIM9 when enabled.
- */
-#if STM32_PWM_USE_TIM9 || defined(__DOXYGEN__)
-PWMDriver PWMD9;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || STM32_PWM_USE_TIM4 ||       \
-    STM32_PWM_USE_TIM5 || STM32_PWM_USE_TIM9 || defined(__DOXYGEN__)
-/**
- * @brief   Common TIM2...TIM5,TIM9 IRQ handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
-  uint16_t sr;
-
-  sr  = pwmp->tim->SR;
-  sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
-  pwmp->tim->SR = ~sr;
-  if ((sr & STM32_TIM_SR_CC1IF) != 0)
-    pwmp->config->channels[0].callback(pwmp);
-  if ((sr & STM32_TIM_SR_CC2IF) != 0)
-    pwmp->config->channels[1].callback(pwmp);
-  if ((sr & STM32_TIM_SR_CC3IF) != 0)
-    pwmp->config->channels[2].callback(pwmp);
-  if ((sr & STM32_TIM_SR_CC4IF) != 0)
-    pwmp->config->channels[3].callback(pwmp);
-  if ((sr & STM32_TIM_SR_UIF) != 0)
-    pwmp->config->callback(pwmp);
-}
-#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_PWM_USE_TIM1
-#if !defined(STM32_TIM1_UP_HANDLER)
-#error "STM32_TIM1_UP_HANDLER not defined"
-#endif
-/**
- * @brief   TIM1 update interrupt handler.
- * @note    It is assumed that this interrupt is only activated if the callback
- *          pointer is not equal to @p NULL in order to not perform an extra
- *          check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  STM32_TIM1->SR = ~STM32_TIM_SR_UIF;
-  PWMD1.config->callback(&PWMD1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(STM32_TIM1_CC_HANDLER)
-#error "STM32_TIM1_CC_HANDLER not defined"
-#endif
-/**
- * @brief   TIM1 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
-  uint16_t sr;
-
-  CH_IRQ_PROLOGUE();
-
-  sr = STM32_TIM1->SR & STM32_TIM1->DIER & STM32_TIM_DIER_IRQ_MASK;
-  STM32_TIM1->SR = ~sr;
-  if ((sr & STM32_TIM_SR_CC1IF) != 0)
-    PWMD1.config->channels[0].callback(&PWMD1);
-  if ((sr & STM32_TIM_SR_CC2IF) != 0)
-    PWMD1.config->channels[1].callback(&PWMD1);
-  if ((sr & STM32_TIM_SR_CC3IF) != 0)
-    PWMD1.config->channels[2].callback(&PWMD1);
-  if ((sr & STM32_TIM_SR_CC4IF) != 0)
-    PWMD1.config->channels[3].callback(&PWMD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_PWM_USE_TIM1 */
-
-#if STM32_PWM_USE_TIM2
-#if !defined(STM32_TIM2_HANDLER)
-#error "STM32_TIM2_HANDLER not defined"
-#endif
-/**
- * @brief   TIM2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_PWM_USE_TIM2 */
-
-#if STM32_PWM_USE_TIM3
-#if !defined(STM32_TIM3_HANDLER)
-#error "STM32_TIM3_HANDLER not defined"
-#endif
-/**
- * @brief   TIM3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_PWM_USE_TIM3 */
-
-#if STM32_PWM_USE_TIM4
-#if !defined(STM32_TIM4_HANDLER)
-#error "STM32_TIM4_HANDLER not defined"
-#endif
-/**
- * @brief   TIM4 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_PWM_USE_TIM4 */
-
-#if STM32_PWM_USE_TIM5
-#if !defined(STM32_TIM5_HANDLER)
-#error "STM32_TIM5_HANDLER not defined"
-#endif
-/**
- * @brief   TIM5 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_PWM_USE_TIM5 */
-
-#if STM32_PWM_USE_TIM8
-#if !defined(STM32_TIM8_UP_HANDLER)
-#error "STM32_TIM8_UP_HANDLER not defined"
-#endif
-/**
- * @brief   TIM8 update interrupt handler.
- * @note    It is assumed that this interrupt is only activated if the callback
- *          pointer is not equal to @p NULL in order to not perform an extra
- *          check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  STM32_TIM8->SR = ~TIM_SR_UIF;
-  PWMD8.config->callback(&PWMD8);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(STM32_TIM8_CC_HANDLER)
-#error "STM32_TIM8_CC_HANDLER not defined"
-#endif
-/**
- * @brief   TIM8 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
-  uint16_t sr;
-
-  CH_IRQ_PROLOGUE();
-
-  sr = STM32_TIM8->SR & STM32_TIM8->DIER & STM32_TIM_DIER_IRQ_MASK;
-  STM32_TIM8->SR = ~sr;
-  if ((sr & STM32_TIM_SR_CC1IF) != 0)
-    PWMD8.config->channels[0].callback(&PWMD8);
-  if ((sr & STM32_TIM_SR_CC2IF) != 0)
-    PWMD8.config->channels[1].callback(&PWMD8);
-  if ((sr & STM32_TIM_SR_CC3IF) != 0)
-    PWMD8.config->channels[2].callback(&PWMD8);
-  if ((sr & STM32_TIM_SR_CC4IF) != 0)
-    PWMD8.config->channels[3].callback(&PWMD8);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_PWM_USE_TIM8 */
-
-#if STM32_PWM_USE_TIM9
-#if !defined(STM32_TIM9_HANDLER)
-#error "STM32_TIM9_HANDLER not defined"
-#endif
-/**
- * @brief   TIM9 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_TIM9_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  pwm_lld_serve_interrupt(&PWMD9);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_PWM_USE_TIM9 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-#if STM32_PWM_USE_TIM1
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD1);
-  PWMD1.tim = STM32_TIM1;
-#endif
-
-#if STM32_PWM_USE_TIM2
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD2);
-  PWMD2.tim = STM32_TIM2;
-#endif
-
-#if STM32_PWM_USE_TIM3
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD3);
-  PWMD3.tim = STM32_TIM3;
-#endif
-
-#if STM32_PWM_USE_TIM4
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD4);
-  PWMD4.tim = STM32_TIM4;
-#endif
-
-#if STM32_PWM_USE_TIM5
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD5);
-  PWMD5.tim = STM32_TIM5;
-#endif
-
-#if STM32_PWM_USE_TIM8
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD8);
-  PWMD8.tim = STM32_TIM8;
-#endif
-
-#if STM32_PWM_USE_TIM9
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD9);
-  PWMD9.tim = STM32_TIM9;
-#endif
-}
-
-/**
- * @brief   Configures and activates the PWM peripheral.
- * @note    Starting a driver that is already in the @p PWM_READY state
- *          disables all the active channels.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-  uint32_t psc;
-  uint16_t ccer;
-
-  if (pwmp->state == PWM_STOP) {
-    /* Clock activation and timer reset.*/
-#if STM32_PWM_USE_TIM1
-    if (&PWMD1 == pwmp) {
-      rccEnableTIM1(FALSE);
-      rccResetTIM1();
-      nvicEnableVector(STM32_TIM1_UP_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
-      nvicEnableVector(STM32_TIM1_CC_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
-#if defined(STM32_TIM1CLK)
-      pwmp->clock = STM32_TIM1CLK;
-#else
-      pwmp->clock = STM32_TIMCLK2;
-#endif
-    }
-#endif
-#if STM32_PWM_USE_TIM2
-    if (&PWMD2 == pwmp) {
-      rccEnableTIM2(FALSE);
-      rccResetTIM2();
-      nvicEnableVector(STM32_TIM2_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY));
-      pwmp->clock = STM32_TIMCLK1;
-    }
-#endif
-#if STM32_PWM_USE_TIM3
-    if (&PWMD3 == pwmp) {
-      rccEnableTIM3(FALSE);
-      rccResetTIM3();
-      nvicEnableVector(STM32_TIM3_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY));
-      pwmp->clock = STM32_TIMCLK1;
-    }
-#endif
-#if STM32_PWM_USE_TIM4
-    if (&PWMD4 == pwmp) {
-      rccEnableTIM4(FALSE);
-      rccResetTIM4();
-      nvicEnableVector(STM32_TIM4_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY));
-      pwmp->clock = STM32_TIMCLK1;
-    }
-#endif
-
-#if STM32_PWM_USE_TIM5
-    if (&PWMD5 == pwmp) {
-      rccEnableTIM5(FALSE);
-      rccResetTIM5();
-      nvicEnableVector(STM32_TIM5_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY));
-      pwmp->clock = STM32_TIMCLK1;
-    }
-#endif
-#if STM32_PWM_USE_TIM8
-    if (&PWMD8 == pwmp) {
-      rccEnableTIM8(FALSE);
-      rccResetTIM8();
-      nvicEnableVector(STM32_TIM8_UP_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
-      nvicEnableVector(STM32_TIM8_CC_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
-#if defined(STM32_TIM8CLK)
-      pwmp->clock = STM32_TIM8CLK;
-#else
-      pwmp->clock = STM32_TIMCLK2;
-#endif
-    }
-#endif
-#if STM32_PWM_USE_TIM9
-    if (&PWMD9 == pwmp) {
-      rccEnableTIM9(FALSE);
-      rccResetTIM9();
-      nvicEnableVector(STM32_TIM9_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_PWM_TIM9_IRQ_PRIORITY));
-      pwmp->clock = STM32_TIMCLK2;
-    }
-#endif
-
-    /* All channels configured in PWM1 mode with preload enabled and will
-       stay that way until the driver is stopped.*/
-    pwmp->tim->CCMR1 = STM32_TIM_CCMR1_OC1M(6) | STM32_TIM_CCMR1_OC1PE |
-                       STM32_TIM_CCMR1_OC2M(6) | STM32_TIM_CCMR1_OC2PE;
-    pwmp->tim->CCMR2 = STM32_TIM_CCMR2_OC3M(6) | STM32_TIM_CCMR2_OC3PE |
-                       STM32_TIM_CCMR2_OC4M(6) | STM32_TIM_CCMR2_OC4PE;
-  }
-  else {
-    /* Driver re-configuration scenario, it must be stopped first.*/
-    pwmp->tim->CR1    = 0;                  /* Timer disabled.              */
-    pwmp->tim->DIER   = pwmp->config->dier &/* DMA-related DIER settings.   */
-                        ~STM32_TIM_DIER_IRQ_MASK;
-    pwmp->tim->SR     = 0;                  /* Clear eventual pending IRQs. */
-    pwmp->tim->CCR[0] = 0;                  /* Comparator 1 disabled.       */
-    pwmp->tim->CCR[1] = 0;                  /* Comparator 2 disabled.       */
-    pwmp->tim->CCR[2] = 0;                  /* Comparator 3 disabled.       */
-    pwmp->tim->CCR[3] = 0;                  /* Comparator 4 disabled.       */
-    pwmp->tim->CNT  = 0;                    /* Counter reset to zero.       */
-  }
-
-  /* Timer configuration.*/
-  psc = (pwmp->clock / pwmp->config->frequency) - 1;
-  chDbgAssert((psc <= 0xFFFF) &&
-              ((psc + 1) * pwmp->config->frequency) == pwmp->clock,
-              "pwm_lld_start(), #1", "invalid frequency");
-  pwmp->tim->PSC  = (uint16_t)psc;
-  pwmp->tim->ARR  = (uint16_t)(pwmp->period - 1);
-  pwmp->tim->CR2  = pwmp->config->cr2;
-
-  /* Output enables and polarities setup.*/
-  ccer = 0;
-  switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) {
-  case PWM_OUTPUT_ACTIVE_LOW:
-    ccer |= STM32_TIM_CCER_CC1P;
-  case PWM_OUTPUT_ACTIVE_HIGH:
-    ccer |= STM32_TIM_CCER_CC1E;
-  default:
-    ;
-  }
-  switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) {
-  case PWM_OUTPUT_ACTIVE_LOW:
-    ccer |= STM32_TIM_CCER_CC2P;
-  case PWM_OUTPUT_ACTIVE_HIGH:
-    ccer |= STM32_TIM_CCER_CC2E;
-  default:
-    ;
-  }
-  switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) {
-  case PWM_OUTPUT_ACTIVE_LOW:
-    ccer |= STM32_TIM_CCER_CC3P;
-  case PWM_OUTPUT_ACTIVE_HIGH:
-    ccer |= STM32_TIM_CCER_CC3E;
-  default:
-    ;
-  }
-  switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) {
-  case PWM_OUTPUT_ACTIVE_LOW:
-    ccer |= STM32_TIM_CCER_CC4P;
-  case PWM_OUTPUT_ACTIVE_HIGH:
-    ccer |= STM32_TIM_CCER_CC4E;
-  default:
-    ;
-  }
-#if STM32_PWM_USE_ADVANCED
-#if STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8
-  if (&PWMD1 == pwmp) {
-#endif
-#if !STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8
-  if (&PWMD8 == pwmp) {
-#endif
-#if STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8
-  if ((&PWMD1 == pwmp) || (&PWMD8 == pwmp)) {
-#endif
-    switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
-    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
-      ccer |= STM32_TIM_CCER_CC1NP;
-    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
-      ccer |= STM32_TIM_CCER_CC1NE;
-    default:
-      ;
-    }
-    switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
-    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
-      ccer |= STM32_TIM_CCER_CC2NP;
-    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
-      ccer |= STM32_TIM_CCER_CC2NE;
-    default:
-      ;
-    }
-    switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
-    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
-      ccer |= STM32_TIM_CCER_CC3NP;
-    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
-      ccer |= STM32_TIM_CCER_CC3NE;
-    default:
-      ;
-    }
-  }
-#endif /* STM32_PWM_USE_ADVANCED*/
-
-  pwmp->tim->CCER  = ccer;
-  pwmp->tim->EGR   = STM32_TIM_EGR_UG;      /* Update event.                */
-  pwmp->tim->DIER |= pwmp->config->callback == NULL ? 0 : STM32_TIM_DIER_UIE;
-  pwmp->tim->SR    = 0;                     /* Clear pending IRQs.          */
-#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8
-#if STM32_PWM_USE_ADVANCED
-  pwmp->tim->BDTR  = pwmp->config->bdtr | STM32_TIM_BDTR_MOE;
-#else
-  pwmp->tim->BDTR  = STM32_TIM_BDTR_MOE;
-#endif
-#endif
-  /* Timer configured and started.*/
-  pwmp->tim->CR1   = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS |
-                     STM32_TIM_CR1_CEN;
-}
-
-/**
- * @brief   Deactivates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
-  /* If in ready state then disables the PWM clock.*/
-  if (pwmp->state == PWM_READY) {
-    pwmp->tim->CR1  = 0;                    /* Timer disabled.              */
-    pwmp->tim->DIER = 0;                    /* All IRQs disabled.           */
-    pwmp->tim->SR   = 0;                    /* Clear eventual pending IRQs. */
-#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8
-    pwmp->tim->BDTR  = 0;
-#endif
-
-#if STM32_PWM_USE_TIM1
-    if (&PWMD1 == pwmp) {
-      nvicDisableVector(STM32_TIM1_UP_NUMBER);
-      nvicDisableVector(STM32_TIM1_CC_NUMBER);
-      rccDisableTIM1(FALSE);
-    }
-#endif
-#if STM32_PWM_USE_TIM2
-    if (&PWMD2 == pwmp) {
-      nvicDisableVector(STM32_TIM2_NUMBER);
-      rccDisableTIM2(FALSE);
-    }
-#endif
-#if STM32_PWM_USE_TIM3
-    if (&PWMD3 == pwmp) {
-      nvicDisableVector(STM32_TIM3_NUMBER);
-      rccDisableTIM3(FALSE);
-    }
-#endif
-#if STM32_PWM_USE_TIM4
-    if (&PWMD4 == pwmp) {
-      nvicDisableVector(STM32_TIM4_NUMBER);
-      rccDisableTIM4(FALSE);
-    }
-#endif
-#if STM32_PWM_USE_TIM5
-    if (&PWMD5 == pwmp) {
-      nvicDisableVector(STM32_TIM5_NUMBER);
-      rccDisableTIM5(FALSE);
-    }
-#endif
-#if STM32_PWM_USE_TIM8
-    if (&PWMD8 == pwmp) {
-      nvicDisableVector(STM32_TIM8_UP_NUMBER);
-      nvicDisableVector(STM32_TIM8_CC_NUMBER);
-      rccDisableTIM8(FALSE);
-    }
-#endif
-#if STM32_PWM_USE_TIM9
-    if (&PWMD9 == pwmp) {
-      nvicDisableVector(STM32_TIM9_NUMBER);
-      rccDisableTIM9(FALSE);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Enables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is active using the specified configuration.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t channel,
-                            pwmcnt_t width) {
-
-  pwmp->tim->CCR[channel] = width;                  /* New duty cycle.      */
-  /* If there is a callback defined for the channel then the associated
-     interrupt must be enabled.*/
-  if (pwmp->config->channels[channel].callback != NULL) {
-    uint32_t dier = pwmp->tim->DIER;
-    /* If the IRQ is not already enabled care must be taken to clear it,
-       it is probably already pending because the timer is running.*/
-    if ((dier & (2 << channel)) == 0) {
-      pwmp->tim->DIER = dier | (2 << channel);
-      pwmp->tim->SR   = ~(2 << channel);
-    }
-  }
-}
-
-/**
- * @brief   Disables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is disabled and its output line returned to the
- *          idle state.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-  pwmp->tim->CCR[channel] = 0;
-  pwmp->tim->DIER &= ~(2 << channel);
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/TIMv1/pwm_lld.h b/os/hal/platforms/STM32/TIMv1/pwm_lld.h
deleted file mode 100644
index 5b7bfa84e..000000000
--- a/os/hal/platforms/STM32/TIMv1/pwm_lld.h
+++ /dev/null
@@ -1,480 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/pwm_lld.h
- * @brief   STM32 PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#include "stm32_tim.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS                            4
-
-/**
- * @brief   Complementary output modes mask.
- * @note    This is an STM32-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_MASK           0xF0
-
-/**
- * @brief   Complementary output not driven.
- * @note    This is an STM32-specific setting.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_DISABLED       0x00
-
-/**
- * @brief   Complementary output, active is logic level one.
- * @note    This is an STM32-specific setting.
- * @note    This setting is only available if the configuration option
- *          @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced
- *          timers TIM1 and TIM8.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH    0x10
-
-/**
- * @brief   Complementary output, active is logic level zero.
- * @note    This is an STM32-specific setting.
- * @note    This setting is only available if the configuration option
- *          @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced
- *          timers TIM1 and TIM8.
- */
-#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW     0x20
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   If advanced timer features switch.
- * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
- *          enabled.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
-#define STM32_PWM_USE_ADVANCED              FALSE
-#endif
-
-/**
- * @brief   PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__)
-#define STM32_PWM_USE_TIM1                  FALSE
-#endif
-
-/**
- * @brief   PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__)
-#define STM32_PWM_USE_TIM2                  FALSE
-#endif
-
-/**
- * @brief   PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__)
-#define STM32_PWM_USE_TIM3                  FALSE
-#endif
-
-/**
- * @brief   PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__)
-#define STM32_PWM_USE_TIM4                  FALSE
-#endif
-
-/**
- * @brief   PWMD5 driver enable switch.
- * @details If set to @p TRUE the support for PWMD5 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__)
-#define STM32_PWM_USE_TIM5                  FALSE
-#endif
-
-/**
- * @brief   PWMD8 driver enable switch.
- * @details If set to @p TRUE the support for PWMD8 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_PWM_USE_TIM8) || defined(__DOXYGEN__)
-#define STM32_PWM_USE_TIM8                  FALSE
-#endif
-
-/**
- * @brief   PWMD9 driver enable switch.
- * @details If set to @p TRUE the support for PWMD9 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_PWM_USE_TIM9) || defined(__DOXYGEN__)
-#define STM32_PWM_USE_TIM9                  FALSE
-#endif
-
-/**
- * @brief   PWMD1 interrupt priority level setting.
- */
-#if !defined(STM32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_TIM1_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   PWMD2 interrupt priority level setting.
- */
-#if !defined(STM32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_TIM2_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   PWMD3 interrupt priority level setting.
- */
-#if !defined(STM32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_TIM3_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   PWMD4 interrupt priority level setting.
- */
-#if !defined(STM32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_TIM4_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   PWMD5 interrupt priority level setting.
- */
-#if !defined(STM32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_TIM5_IRQ_PRIORITY         7
-#endif
-
-/**
- * @brief   PWMD8 interrupt priority level setting.
- */
-#if !defined(STM32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_TIM8_IRQ_PRIORITY         7
-#endif
-/** @} */
-
-/**
- * @brief   PWMD9 interrupt priority level setting.
- */
-#if !defined(STM32_PWM_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_TIM9_IRQ_PRIORITY         7
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Configuration checks.                                                     */
-/*===========================================================================*/
-
-#if STM32_PWM_USE_TIM1 && !STM32_HAS_TIM1
-#error "TIM1 not present in the selected device"
-#endif
-
-#if STM32_PWM_USE_TIM2 && !STM32_HAS_TIM2
-#error "TIM2 not present in the selected device"
-#endif
-
-#if STM32_PWM_USE_TIM3 && !STM32_HAS_TIM3
-#error "TIM3 not present in the selected device"
-#endif
-
-#if STM32_PWM_USE_TIM4 && !STM32_HAS_TIM4
-#error "TIM4 not present in the selected device"
-#endif
-
-#if STM32_PWM_USE_TIM5 && !STM32_HAS_TIM5
-#error "TIM5 not present in the selected device"
-#endif
-
-#if STM32_PWM_USE_TIM8 && !STM32_HAS_TIM8
-#error "TIM8 not present in the selected device"
-#endif
-
-#if STM32_PWM_USE_TIM9 && !STM32_HAS_TIM9
-#error "TIM9 not present in the selected device"
-#endif
-
-#if !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM2 &&                           \
-    !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4 &&                           \
-    !STM32_PWM_USE_TIM5 && !STM32_PWM_USE_TIM8 &&                           \
-    !STM32_PWM_USE_TIM9
-#error "PWM driver activated but no TIM peripheral assigned"
-#endif
-
-#if STM32_PWM_USE_ADVANCED && !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8
-#error "advanced mode selected but no advanced timer assigned"
-#endif
-
-#if STM32_PWM_USE_TIM1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM1"
-#endif
-
-#if STM32_PWM_USE_TIM2 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM2"
-#endif
-
-#if STM32_PWM_USE_TIM3 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM3"
-#endif
-
-#if STM32_PWM_USE_TIM4 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM4"
-#endif
-
-#if STM32_PWM_USE_TIM5 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM5"
-#endif
-
-#if STM32_PWM_USE_TIM8 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM8_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM8"
-#endif
-
-#if STM32_PWM_USE_TIM9 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM9_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM9"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief   PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief   PWM counter type.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief   PWM driver channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel active logic level.
-   */
-  pwmmode_t                 mode;
-  /**
-   * @brief Channel callback pointer.
-   * @note  This callback is invoked on the channel compare event. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief   PWM driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  uint32_t                  frequency;
-  /**
-   * @brief   PWM period in ticks.
-   * @note    The low level can use assertions in order to catch invalid
-   *          period specifications.
-   */
-  pwmcnt_t                  period;
-  /**
-   * @brief Periodic callback pointer.
-   * @note  This callback is invoked on PWM counter reset. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /**
-   * @brief Channels configurations.
-   */
-  PWMChannelConfig          channels[PWM_CHANNELS];
-  /* End of the mandatory fields.*/
-  /**
-   * @brief TIM CR2 register initialization data.
-   * @note  The value of this field should normally be equal to zero.
-   */
-  uint32_t                  cr2;
-#if STM32_PWM_USE_ADVANCED || defined(__DOXYGEN__)
-  /**
-   * @brief TIM BDTR (break & dead-time) register initialization data.
-   * @note  The value of this field should normally be equal to zero.
-   */                                                                     \
-   uint32_t                 bdtr;
-#endif
-   /**
-    * @brief TIM DIER register initialization data.
-    * @note  The value of this field should normally be equal to zero.
-    * @note  Only the DMA-related bits can be specified in this field.
-    */
-   uint32_t                 dier;
-} PWMConfig;
-
-/**
- * @brief   Structure representing a PWM driver.
- */
-struct PWMDriver {
-  /**
-   * @brief Driver state.
-   */
-  pwmstate_t                state;
-  /**
-   * @brief Current driver configuration data.
-   */
-  const PWMConfig           *config;
-  /**
-   * @brief   Current PWM period in ticks.
-   */
-  pwmcnt_t                  period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
-  PWM_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Timer base clock.
-   */
-  uint32_t                  clock;
-  /**
-   * @brief Pointer to the TIMx registers block.
-   */
-  stm32_tim_t               *tim;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- *          been activated using @p pwmStart().
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The PWM unit period is changed to the new value.
- * @note    The function has effect at the next cycle start.
- * @note    If a period is specified that is shorter than the pulse width
- *          programmed in one of the channels then the behavior is not
- *          guaranteed.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] period    new cycle time in ticks
- *
- * @notapi
- */
-#define pwm_lld_change_period(pwmp, period)                                 \
-  ((pwmp)->tim->ARR = (uint16_t)((period) - 1))
-
-/**
- * @brief   Returns a PWM channel status.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-#define pwm_lld_is_channel_enabled(pwmp, channel)                           \
-  (((pwmp)->tim->CCR[channel] != 0) ||                                      \
-   (((pwmp)->tim->DIER & (2 << channel)) != 0))
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_PWM_USE_TIM1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if STM32_PWM_USE_TIM2 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if STM32_PWM_USE_TIM3 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if STM32_PWM_USE_TIM4 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#if STM32_PWM_USE_TIM5 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD5;
-#endif
-
-#if STM32_PWM_USE_TIM8 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD8;
-#endif
-
-#if STM32_PWM_USE_TIM9 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD9;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void pwm_lld_init(void);
-  void pwm_lld_start(PWMDriver *pwmp);
-  void pwm_lld_stop(PWMDriver *pwmp);
-  void pwm_lld_enable_channel(PWMDriver *pwmp,
-                              pwmchannel_t channel,
-                              pwmcnt_t width);
-  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USARTv1/serial_lld.c b/os/hal/platforms/STM32/USARTv1/serial_lld.c
deleted file mode 100644
index eb344ebc0..000000000
--- a/os/hal/platforms/STM32/USARTv1/serial_lld.c
+++ /dev/null
@@ -1,532 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USARTv1/serial_lld.c
- * @brief   STM32 low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief USART1 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/** @brief USART2 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/** @brief USART3 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/** @brief UART4 serial driver identifier.*/
-#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-SerialDriver SD4;
-#endif
-
-/** @brief UART5 serial driver identifier.*/
-#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-SerialDriver SD5;
-#endif
-
-/** @brief USART6 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-SerialDriver SD6;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config =
-{
-  SERIAL_DEFAULT_BITRATE,
-  0,
-  USART_CR2_STOP1_BITS | USART_CR2_LINEN,
-  0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   USART initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
-  USART_TypeDef *u = sdp->usart;
-
-  /* Baud rate setting.*/
-#if STM32_HAS_USART6
-  if ((sdp->usart == USART1) || (sdp->usart == USART6))
-#else
-  if (sdp->usart == USART1)
-#endif
-    u->BRR = STM32_PCLK2 / config->speed;
-  else
-    u->BRR = STM32_PCLK1 / config->speed;
-
-  /* Note that some bits are enforced.*/
-  u->CR2 = config->cr2 | USART_CR2_LBDIE;
-  u->CR3 = config->cr3 | USART_CR3_EIE;
-  u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE |
-                         USART_CR1_RXNEIE | USART_CR1_TE |
-                         USART_CR1_RE;
-  u->SR = 0;
-  (void)u->SR;  /* SR reset step 1.*/
-  (void)u->DR;  /* SR reset step 2.*/
-}
-
-/**
- * @brief   USART de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] u         pointer to an USART I/O block
- */
-static void usart_deinit(USART_TypeDef *u) {
-
-  u->CR1 = 0;
-  u->CR2 = 0;
-  u->CR3 = 0;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] sr        USART SR register value
- */
-static void set_error(SerialDriver *sdp, uint16_t sr) {
-  flagsmask_t sts = 0;
-
-  if (sr & USART_SR_ORE)
-    sts |= SD_OVERRUN_ERROR;
-  if (sr & USART_SR_PE)
-    sts |= SD_PARITY_ERROR;
-  if (sr & USART_SR_FE)
-    sts |= SD_FRAMING_ERROR;
-  if (sr & USART_SR_NE)
-    sts |= SD_NOISE_ERROR;
-  chnAddFlagsI(sdp, sts);
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] sdp       communication channel associated to the USART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  USART_TypeDef *u = sdp->usart;
-  uint16_t cr1 = u->CR1;
-  uint16_t sr = u->SR;
-
-  /* Special case, LIN break detection.*/
-  if (sr & USART_SR_LBD) {
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, SD_BREAK_DETECTED);
-    chSysUnlockFromIsr();
-    u->SR = ~USART_SR_LBD;
-  }
-
-  /* Data available.*/
-  chSysLockFromIsr();
-  while (sr & USART_SR_RXNE) {
-    /* Error condition detection.*/
-    if (sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE  | USART_SR_PE))
-      set_error(sdp, sr);
-    sdIncomingDataI(sdp, u->DR);
-    sr = u->SR;
-  }
-  chSysUnlockFromIsr();
-
-  /* Transmission buffer empty.*/
-  if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) {
-    msg_t b;
-    chSysLockFromIsr();
-    b = chOQGetI(&sdp->oqueue);
-    if (b < Q_OK) {
-      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-      u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
-    }
-    else
-      u->DR = b;
-    chSysUnlockFromIsr();
-  }
-
-  /* Physical transmission end.*/
-  if (sr & USART_SR_TC) {
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
-    chSysUnlockFromIsr();
-    u->CR1 = cr1 & ~(USART_CR1_TXEIE | USART_CR1_TCIE);
-    u->SR = ~USART_SR_TC;
-  }
-}
-
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  USART1->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  USART2->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
-  (void)qp;
-  USART3->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-static void notify4(GenericQueue *qp) {
-
-  (void)qp;
-  UART4->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-static void notify5(GenericQueue *qp) {
-
-  (void)qp;
-  UART5->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-static void notify6(GenericQueue *qp) {
-
-  (void)qp;
-  USART6->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-#if !defined(STM32_USART1_HANDLER)
-#error "STM32_USART1_HANDLER not defined"
-#endif
-/**
- * @brief   USART1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-#if !defined(STM32_USART2_HANDLER)
-#error "STM32_USART2_HANDLER not defined"
-#endif
-/**
- * @brief   USART2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-#if !defined(STM32_USART3_HANDLER)
-#error "STM32_USART3_HANDLER not defined"
-#endif
-/**
- * @brief   USART3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-#if !defined(STM32_UART4_HANDLER)
-#error "STM32_UART4_HANDLER not defined"
-#endif
-/**
- * @brief   UART4 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-#if !defined(STM32_UART5_HANDLER)
-#error "STM32_UART5_HANDLER not defined"
-#endif
-/**
- * @brief   UART5 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-#if !defined(STM32_USART6_HANDLER)
-#error "STM32_USART6_HANDLER not defined"
-#endif
-/**
- * @brief   USART1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART6_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if STM32_SERIAL_USE_USART1
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.usart = USART1;
-#endif
-
-#if STM32_SERIAL_USE_USART2
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.usart = USART2;
-#endif
-
-#if STM32_SERIAL_USE_USART3
-  sdObjectInit(&SD3, NULL, notify3);
-  SD3.usart = USART3;
-#endif
-
-#if STM32_SERIAL_USE_UART4
-  sdObjectInit(&SD4, NULL, notify4);
-  SD4.usart = UART4;
-#endif
-
-#if STM32_SERIAL_USE_UART5
-  sdObjectInit(&SD5, NULL, notify5);
-  SD5.usart = UART5;
-#endif
-
-#if STM32_SERIAL_USE_USART6
-  sdObjectInit(&SD6, NULL, notify6);
-  SD6.usart = USART6;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if STM32_SERIAL_USE_USART1
-    if (&SD1 == sdp) {
-      rccEnableUSART1(FALSE);
-      nvicEnableVector(STM32_USART1_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_USART2
-    if (&SD2 == sdp) {
-      rccEnableUSART2(FALSE);
-      nvicEnableVector(STM32_USART2_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_USART3
-    if (&SD3 == sdp) {
-      rccEnableUSART3(FALSE);
-      nvicEnableVector(STM32_USART3_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_UART4
-    if (&SD4 == sdp) {
-      rccEnableUART4(FALSE);
-      nvicEnableVector(STM32_UART4_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_UART5
-    if (&SD5 == sdp) {
-      rccEnableUART5(FALSE);
-      nvicEnableVector(STM32_UART5_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_USART6
-    if (&SD6 == sdp) {
-      rccEnableUSART6(FALSE);
-      nvicEnableVector(STM32_USART6_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY));
-    }
-#endif
-  }
-  usart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    usart_deinit(sdp->usart);
-#if STM32_SERIAL_USE_USART1
-    if (&SD1 == sdp) {
-      rccDisableUSART1(FALSE);
-      nvicDisableVector(STM32_USART1_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_USART2
-    if (&SD2 == sdp) {
-      rccDisableUSART2(FALSE);
-      nvicDisableVector(STM32_USART2_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_USART3
-    if (&SD3 == sdp) {
-      rccDisableUSART3(FALSE);
-      nvicDisableVector(STM32_USART3_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_UART4
-    if (&SD4 == sdp) {
-      rccDisableUART4(FALSE);
-      nvicDisableVector(STM32_UART4_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_UART5
-    if (&SD5 == sdp) {
-      rccDisableUART5(FALSE);
-      nvicDisableVector(STM32_UART5_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_USART6
-    if (&SD6 == sdp) {
-      rccDisableUSART6(FALSE);
-      nvicDisableVector(STM32_USART6_NUMBER);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USARTv1/serial_lld.h b/os/hal/platforms/STM32/USARTv1/serial_lld.h
deleted file mode 100644
index 7242537d7..000000000
--- a/os/hal/platforms/STM32/USARTv1/serial_lld.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USARTv1/serial_lld.h
- * @brief   STM32 low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   USART1 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART1             FALSE
-#endif
-
-/**
- * @brief   USART2 driver enable switch.
- * @details If set to @p TRUE the support for USART2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART2             FALSE
-#endif
-
-/**
- * @brief   USART3 driver enable switch.
- * @details If set to @p TRUE the support for USART3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART3             FALSE
-#endif
-
-/**
- * @brief   UART4 driver enable switch.
- * @details If set to @p TRUE the support for UART4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_UART4              FALSE
-#endif
-
-/**
- * @brief   UART5 driver enable switch.
- * @details If set to @p TRUE the support for UART5 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_UART5              FALSE
-#endif
-
-/**
- * @brief   USART6 driver enable switch.
- * @details If set to @p TRUE the support for USART6 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART6             FALSE
-#endif
-
-/**
- * @brief   USART1 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART1_PRIORITY        12
-#endif
-
-/**
- * @brief   USART2 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART2_PRIORITY        12
-#endif
-
-/**
- * @brief   USART3 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART3_PRIORITY        12
-#endif
-
-/**
- * @brief   UART4 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_UART4_PRIORITY         12
-#endif
-
-/**
- * @brief   UART5 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_UART5_PRIORITY         12
-#endif
-
-/**
- * @brief   USART6 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART6_PRIORITY        12
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1
-#error "USART1 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2
-#error "USART2 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3
-#error "USART3 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4
-#error "UART4 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5
-#error "UART5 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6
-#error "USART6 not present in the selected device"
-#endif
-
-#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 &&                 \
-    !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4  &&                 \
-    !STM32_SERIAL_USE_UART5  && !STM32_SERIAL_USE_USART6
-#error "SERIAL driver activated but no USART/UART peripheral assigned"
-#endif
-
-#if STM32_SERIAL_USE_USART1 &&                                              \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
-#error "Invalid IRQ priority assigned to USART1"
-#endif
-
-#if STM32_SERIAL_USE_USART2 &&                                              \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
-#error "Invalid IRQ priority assigned to USART2"
-#endif
-
-#if STM32_SERIAL_USE_USART3 &&                                              \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
-#error "Invalid IRQ priority assigned to USART3"
-#endif
-
-#if STM32_SERIAL_USE_UART4 &&                                               \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
-#error "Invalid IRQ priority assigned to UART4"
-#endif
-
-#if STM32_SERIAL_USE_UART5 &&                                               \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
-#error "Invalid IRQ priority assigned to UART5"
-#endif
-
-#if STM32_SERIAL_USE_USART6 &&                                              \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
-#error "Invalid IRQ priority assigned to USART6"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    This structure content is architecture dependent, each driver
- *          implementation defines its own version and the custom static
- *          initializers.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  speed;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Initialization value for the CR1 register.
-   */
-  uint16_t                  cr1;
-  /**
-   * @brief Initialization value for the CR2 register.
-   */
-  uint16_t                  cr2;
-  /**
-   * @brief Initialization value for the CR3 register.
-   */
-  uint16_t                  cr3;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  USART_TypeDef             *usart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*
- * Extra USARTs definitions here (missing from the ST header file).
- */
-#define USART_CR2_STOP1_BITS    (0 << 12)   /**< @brief CR2 1 stop bit value.*/
-#define USART_CR2_STOP0P5_BITS  (1 << 12)   /**< @brief CR2 0.5 stop bit value.*/
-#define USART_CR2_STOP2_BITS    (2 << 12)   /**< @brief CR2 2 stop bit value.*/
-#define USART_CR2_STOP1P5_BITS  (3 << 12)   /**< @brief CR2 1.5 stop bit value.*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
-extern SerialDriver SD4;
-#endif
-#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
-extern SerialDriver SD5;
-#endif
-#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
-extern SerialDriver SD6;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USARTv1/uart_lld.c b/os/hal/platforms/STM32/USARTv1/uart_lld.c
deleted file mode 100644
index 9cb5bc810..000000000
--- a/os/hal/platforms/STM32/USARTv1/uart_lld.c
+++ /dev/null
@@ -1,824 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USARTv1/uart_lld.c
- * @brief   STM32 low level UART driver code.
- *
- * @addtogroup UART
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define USART1_RX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM,                     \
-                       STM32_USART1_RX_DMA_CHN)
-
-#define USART1_TX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM,                     \
-                       STM32_USART1_TX_DMA_CHN)
-
-#define USART2_RX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM,                     \
-                       STM32_USART2_RX_DMA_CHN)
-
-#define USART2_TX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM,                     \
-                       STM32_USART2_TX_DMA_CHN)
-
-#define USART3_RX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM,                     \
-                       STM32_USART3_RX_DMA_CHN)
-
-#define USART3_TX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM,                     \
-                       STM32_USART3_TX_DMA_CHN)
-
-#define UART4_RX_DMA_CHANNEL                                                \
-  STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM,                      \
-                       STM32_UART4_RX_DMA_CHN)
-
-#define UART4_TX_DMA_CHANNEL                                                \
-  STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM,                      \
-                       STM32_UART4_TX_DMA_CHN)
-
-#define UART5_RX_DMA_CHANNEL                                                \
-  STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM,                      \
-                       STM32_UART5_RX_DMA_CHN)
-
-#define UART5_TX_DMA_CHANNEL                                                \
-  STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM,                      \
-                       STM32_UART5_TX_DMA_CHN)
-
-#define USART6_RX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM,                     \
-                       STM32_USART6_RX_DMA_CHN)
-
-#define USART6_TX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM,                     \
-                       STM32_USART6_TX_DMA_CHN)
-
-#define STM32_UART45_CR2_CHECK_MASK                                         \
-  (USART_CR2_STOP_0 | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA |   \
-   USART_CR2_LBCL)
-
-#define STM32_UART45_CR3_CHECK_MASK                                         \
-  (USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_SCEN |     \
-   USART_CR3_NACK)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief USART1 UART driver identifier.*/
-#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
-UARTDriver UARTD1;
-#endif
-
-/** @brief USART2 UART driver identifier.*/
-#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
-UARTDriver UARTD2;
-#endif
-
-/** @brief USART3 UART driver identifier.*/
-#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
-UARTDriver UARTD3;
-#endif
-
-/** @brief UART4 UART driver identifier.*/
-#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
-UARTDriver UARTD4;
-#endif
-
-/** @brief UART5 UART driver identifier.*/
-#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
-UARTDriver UARTD5;
-#endif
-
-/** @brief USART6 UART driver identifier.*/
-#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
-UARTDriver UARTD6;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Status bits translation.
- *
- * @param[in] sr        USART SR register value
- *
- * @return  The error flags.
- */
-static uartflags_t translate_errors(uint16_t sr) {
-  uartflags_t sts = 0;
-
-  if (sr & USART_SR_ORE)
-    sts |= UART_OVERRUN_ERROR;
-  if (sr & USART_SR_PE)
-    sts |= UART_PARITY_ERROR;
-  if (sr & USART_SR_FE)
-    sts |= UART_FRAMING_ERROR;
-  if (sr & USART_SR_NE)
-    sts |= UART_NOISE_ERROR;
-  if (sr & USART_SR_LBD)
-    sts |= UART_BREAK_DETECTED;
-  return sts;
-}
-
-/**
- * @brief   Puts the receiver in the UART_RX_IDLE state.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-static void set_rx_idle_loop(UARTDriver *uartp) {
-  uint32_t mode;
-  
-  /* RX DMA channel preparation, if the char callback is defined then the
-     TCIE interrupt is enabled too.*/
-  if (uartp->config->rxchar_cb == NULL)
-    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
-  else
-    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
-  dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
-  dmaStreamSetTransactionSize(uartp->dmarx, 1);
-  dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);
-  dmaStreamEnable(uartp->dmarx);
-}
-
-/**
- * @brief   USART de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-static void usart_stop(UARTDriver *uartp) {
-
-  /* Stops RX and TX DMA channels.*/
-  dmaStreamDisable(uartp->dmarx);
-  dmaStreamDisable(uartp->dmatx);
-  
-  /* Stops USART operations.*/
-  uartp->usart->CR1 = 0;
-  uartp->usart->CR2 = 0;
-  uartp->usart->CR3 = 0;
-}
-
-/**
- * @brief   USART initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-static void usart_start(UARTDriver *uartp) {
-  uint16_t cr1;
-  USART_TypeDef *u = uartp->usart;
-
-  /* Defensive programming, starting from a clean state.*/
-  usart_stop(uartp);
-
-  /* Baud rate setting.*/
-#if STM32_HAS_USART6
-  if ((uartp->usart == USART1) || (uartp->usart == USART6))
-#else
-  if (uartp->usart == USART1)
-#endif
-    u->BRR = STM32_PCLK2 / uartp->config->speed;
-  else
-    u->BRR = STM32_PCLK1 / uartp->config->speed;
-
-  /* Resetting eventual pending status flags.*/
-  (void)u->SR;  /* SR reset step 1.*/
-  (void)u->DR;  /* SR reset step 2.*/
-  u->SR = 0;
-
-  /* Note that some bits are enforced because required for correct driver
-     operations.*/
-  u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
-  u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
-                                USART_CR3_EIE;
-  if (uartp->config->txend2_cb == NULL)
-    cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
-  else
-    cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE |
-          USART_CR1_TCIE;
-  u->CR1 = uartp->config->cr1 | cr1;
-
-  /* Starting the receiver idle loop.*/
-  set_rx_idle_loop(uartp);
-}
-
-/**
- * @brief   RX DMA common service routine.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-#if defined(STM32_UART_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_UART_DMA_ERROR_HOOK(uartp);
-  }
-#else
-  (void)flags;
-#endif
-
-  if (uartp->rxstate == UART_RX_IDLE) {
-    /* Receiver in idle state, a callback is generated, if enabled, for each
-       received character and then the driver stays in the same state.*/
-    if (uartp->config->rxchar_cb != NULL)
-      uartp->config->rxchar_cb(uartp, uartp->rxbuf);
-  }
-  else {
-    /* Receiver in active state, a callback is generated, if enabled, after
-       a completed transfer.*/
-    dmaStreamDisable(uartp->dmarx);
-    uartp->rxstate = UART_RX_COMPLETE;
-    if (uartp->config->rxend_cb != NULL)
-      uartp->config->rxend_cb(uartp);
-
-    /* If the callback didn't explicitly change state then the receiver
-       automatically returns to the idle state.*/
-    if (uartp->rxstate == UART_RX_COMPLETE) {
-      uartp->rxstate = UART_RX_IDLE;
-      set_rx_idle_loop(uartp);
-    }
-  }
-}
-
-/**
- * @brief   TX DMA common service routine.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-#if defined(STM32_UART_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_UART_DMA_ERROR_HOOK(uartp);
-  }
-#else
-  (void)flags;
-#endif
-
-  dmaStreamDisable(uartp->dmatx);
-
-  /* A callback is generated, if enabled, after a completed transfer.*/
-  uartp->txstate = UART_TX_COMPLETE;
-  if (uartp->config->txend1_cb != NULL)
-    uartp->config->txend1_cb(uartp);
-
-  /* If the callback didn't explicitly change state then the transmitter
-     automatically returns to the idle state.*/
-  if (uartp->txstate == UART_TX_COMPLETE)
-    uartp->txstate = UART_TX_IDLE;
-}
-
-/**
- * @brief   USART common service routine.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-static void serve_usart_irq(UARTDriver *uartp) {
-  uint16_t sr;
-  USART_TypeDef *u = uartp->usart;
-  
-  sr = u->SR;   /* SR reset step 1.*/
-  (void)u->DR;  /* SR reset step 2.*/
-  if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE |
-            USART_SR_FE  | USART_SR_PE)) {
-    u->SR = ~USART_SR_LBD;
-    if (uartp->config->rxerr_cb != NULL)
-      uartp->config->rxerr_cb(uartp, translate_errors(sr));
-  }
-  if (sr & USART_SR_TC) {
-    u->SR = ~USART_SR_TC;
-
-    /* End of transmission, a callback is generated.*/
-    if (uartp->config->txend2_cb != NULL)
-      uartp->config->txend2_cb(uartp);
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
-#if !defined(STM32_USART1_HANDLER)
-#error "STM32_USART1_HANDLER not defined"
-#endif
-/**
- * @brief   USART1 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_usart_irq(&UARTD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART1 */
-
-#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
-#if !defined(STM32_USART2_HANDLER)
-#error "STM32_USART2_HANDLER not defined"
-#endif
-/**
- * @brief   USART2 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_usart_irq(&UARTD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART2 */
-
-#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
-#if !defined(STM32_USART3_HANDLER)
-#error "STM32_USART3_HANDLER not defined"
-#endif
-/**
- * @brief   USART3 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_usart_irq(&UARTD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART3 */
-
-#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
-#if !defined(STM32_UART4_HANDLER)
-#error "STM32_UART4_HANDLER not defined"
-#endif
-/**
- * @brief   UART4 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_usart_irq(&UARTD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_UART4 */
-
-#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
-#if !defined(STM32_UART5_HANDLER)
-#error "STM32_UART5_HANDLER not defined"
-#endif
-/**
- * @brief   UART5 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_usart_irq(&UARTD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_UART5 */
-
-#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
-#if !defined(STM32_USART6_HANDLER)
-#error "STM32_USART6_HANDLER not defined"
-#endif
-/**
- * @brief   USART6 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART6_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_usart_irq(&UARTD6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART6 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level UART driver initialization.
- *
- * @notapi
- */
-void uart_lld_init(void) {
-
-#if STM32_UART_USE_USART1
-  uartObjectInit(&UARTD1);
-  UARTD1.usart   = USART1;
-  UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-  UARTD1.dmarx   = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
-  UARTD1.dmatx   = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
-#endif
-
-#if STM32_UART_USE_USART2
-  uartObjectInit(&UARTD2);
-  UARTD2.usart   = USART2;
-  UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-  UARTD2.dmarx   = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
-  UARTD2.dmatx   = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
-#endif
-
-#if STM32_UART_USE_USART3
-  uartObjectInit(&UARTD3);
-  UARTD3.usart   = USART3;
-  UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-  UARTD3.dmarx   = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
-  UARTD3.dmatx   = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
-#endif
-
-#if STM32_UART_USE_UART4
-  uartObjectInit(&UARTD4);
-  UARTD4.usart   = UART4;
-  UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-  UARTD4.dmarx   = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM);
-  UARTD4.dmatx   = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM);
-#endif
-
-#if STM32_UART_USE_UART5
-  uartObjectInit(&UARTD5);
-  UARTD5.usart   = UART5;
-  UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-  UARTD5.dmarx   = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM);
-  UARTD5.dmatx   = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM);
-#endif
-
-#if STM32_UART_USE_USART6
-  uartObjectInit(&UARTD6);
-  UARTD6.usart   = USART6;
-  UARTD6.dmarx   = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);
-  UARTD6.dmatx   = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);
-#endif
-}
-
-/**
- * @brief   Configures and activates the UART peripheral.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- *
- * @notapi
- */
-void uart_lld_start(UARTDriver *uartp) {
-
-  if (uartp->state == UART_STOP) {
-#if STM32_UART_USE_USART1
-    if (&UARTD1 == uartp) {
-      bool_t b;
-      b = dmaStreamAllocate(uartp->dmarx,
-                            STM32_UART_USART1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated");
-      b = dmaStreamAllocate(uartp->dmatx,
-                            STM32_UART_USART1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
-      rccEnableUSART1(FALSE);
-      nvicEnableVector(STM32_USART1_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
-      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
-    }
-#endif
-
-#if STM32_UART_USE_USART2
-    if (&UARTD2 == uartp) {
-      bool_t b;
-      b = dmaStreamAllocate(uartp->dmarx,
-                            STM32_UART_USART2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated");
-      b = dmaStreamAllocate(uartp->dmatx,
-                            STM32_UART_USART2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
-      rccEnableUSART2(FALSE);
-      nvicEnableVector(STM32_USART2_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
-      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
-    }
-#endif
-
-#if STM32_UART_USE_USART3
-    if (&UARTD3 == uartp) {
-      bool_t b;
-      b = dmaStreamAllocate(uartp->dmarx,
-                            STM32_UART_USART3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
-      b = dmaStreamAllocate(uartp->dmatx,
-                            STM32_UART_USART3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
-      rccEnableUSART3(FALSE);
-      nvicEnableVector(STM32_USART3_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
-      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
-    }
-#endif
-
-#if STM32_UART_USE_UART4
-    if (&UARTD4 == uartp) {
-      bool_t b;
-
-      chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
-                  "uart_lld_start(), #7",
-                  "specified invalid bits in UART4 CR2 register settings");
-      chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
-                  "uart_lld_start(), #8",
-                  "specified invalid bits in UART4 CR3 register settings");
-
-      b = dmaStreamAllocate(uartp->dmarx,
-                            STM32_UART_UART4_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #9", "stream already allocated");
-      b = dmaStreamAllocate(uartp->dmatx,
-                            STM32_UART_UART4_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #10", "stream already allocated");
-      rccEnableUART4(FALSE);
-      nvicEnableVector(STM32_UART4_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_UART_UART4_IRQ_PRIORITY));
-      uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
-    }
-#endif
-
-#if STM32_UART_USE_UART5
-    if (&UARTD5 == uartp) {
-      bool_t b;
-
-      chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
-                  "uart_lld_start(), #11",
-                  "specified invalid bits in UART5 CR2 register settings");
-      chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
-                  "uart_lld_start(), #12",
-                  "specified invalid bits in UART5 CR3 register settings");
-
-      b = dmaStreamAllocate(uartp->dmarx,
-                            STM32_UART_UART5_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #13", "stream already allocated");
-      b = dmaStreamAllocate(uartp->dmatx,
-                            STM32_UART_UART5_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #14", "stream already allocated");
-      rccEnableUART5(FALSE);
-      nvicEnableVector(STM32_UART5_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_UART_UART5_IRQ_PRIORITY));
-      uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
-    }
-#endif
-
-#if STM32_UART_USE_USART6
-    if (&UARTD6 == uartp) {
-      bool_t b;
-      b = dmaStreamAllocate(uartp->dmarx,
-                            STM32_UART_USART6_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #15", "stream already allocated");
-      b = dmaStreamAllocate(uartp->dmatx,
-                            STM32_UART_USART6_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #16", "stream already allocated");
-      rccEnableUSART6(FALSE);
-      nvicEnableVector(STM32_USART6_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY));
-      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
-    }
-#endif
-
-    /* Static DMA setup, the transfer size depends on the USART settings,
-       it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
-    if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
-      uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-    dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR);
-    dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR);
-    uartp->rxbuf = 0;
-  }
-
-  uartp->rxstate = UART_RX_IDLE;
-  uartp->txstate = UART_TX_IDLE;
-  usart_start(uartp);
-}
-
-/**
- * @brief   Deactivates the UART peripheral.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- *
- * @notapi
- */
-void uart_lld_stop(UARTDriver *uartp) {
-
-  if (uartp->state == UART_READY) {
-    usart_stop(uartp);
-    dmaStreamRelease(uartp->dmarx);
-    dmaStreamRelease(uartp->dmatx);
-
-#if STM32_UART_USE_USART1
-    if (&UARTD1 == uartp) {
-      nvicDisableVector(STM32_USART1_NUMBER);
-      rccDisableUSART1(FALSE);
-      return;
-    }
-#endif
-
-#if STM32_UART_USE_USART2
-    if (&UARTD2 == uartp) {
-      nvicDisableVector(STM32_USART2_NUMBER);
-      rccDisableUSART2(FALSE);
-      return;
-    }
-#endif
-
-#if STM32_UART_USE_USART3
-    if (&UARTD3 == uartp) {
-      nvicDisableVector(STM32_USART3_NUMBER);
-      rccDisableUSART3(FALSE);
-      return;
-    }
-#endif
-
-#if STM32_UART_USE_UART4
-    if (&UARTD4 == uartp) {
-      nvicDisableVector(STM32_UART4_NUMBER);
-      rccDisableUART4(FALSE);
-      return;
-    }
-#endif
-
-#if STM32_UART_USE_UART5
-    if (&UARTD5 == uartp) {
-      nvicDisableVector(STM32_UART5_NUMBER);
-      rccDisableUART5(FALSE);
-      return;
-    }
-#endif
-
-#if STM32_UART_USE_USART6
-    if (&UARTD6 == uartp) {
-      nvicDisableVector(STM32_USART6_NUMBER);
-      rccDisableUSART6(FALSE);
-      return;
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts a transmission on the UART peripheral.
- * @note    The buffers are organized as uint8_t arrays for data sizes below
- *          or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] n         number of data frames to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
-
-  /* TX DMA channel preparation and start.*/
-  dmaStreamSetMemory0(uartp->dmatx, txbuf);
-  dmaStreamSetTransactionSize(uartp->dmatx, n);
-  dmaStreamSetMode(uartp->dmatx, uartp->dmamode    | STM32_DMA_CR_DIR_M2P |
-                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
-  dmaStreamEnable(uartp->dmatx);
-}
-
-/**
- * @brief   Stops any ongoing transmission.
- * @note    Stopping a transmission also suppresses the transmission callbacks.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- *
- * @return              The number of data frames not transmitted by the
- *                      stopped transmit operation.
- *
- * @notapi
- */
-size_t uart_lld_stop_send(UARTDriver *uartp) {
-
-  dmaStreamDisable(uartp->dmatx);
-  return dmaStreamGetTransactionSize(uartp->dmatx);
-}
-
-/**
- * @brief   Starts a receive operation on the UART peripheral.
- * @note    The buffers are organized as uint8_t arrays for data sizes below
- *          or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] n         number of data frames to send
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
-
-  /* Stopping previous activity (idle state).*/
-  dmaStreamDisable(uartp->dmarx);
-
-  /* RX DMA channel preparation and start.*/
-  dmaStreamSetMemory0(uartp->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(uartp->dmarx, n);
-  dmaStreamSetMode(uartp->dmarx, uartp->dmamode    | STM32_DMA_CR_DIR_P2M |
-                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
-  dmaStreamEnable(uartp->dmarx);
-}
-
-/**
- * @brief   Stops any ongoing receive operation.
- * @note    Stopping a receive operation also suppresses the receive callbacks.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- *
- * @return              The number of data frames not received by the
- *                      stopped receive operation.
- *
- * @notapi
- */
-size_t uart_lld_stop_receive(UARTDriver *uartp) {
-  size_t n;
-
-  dmaStreamDisable(uartp->dmarx);
-  n = dmaStreamGetTransactionSize(uartp->dmarx);
-  set_rx_idle_loop(uartp);
-  return n;
-}
-
-#endif /* HAL_USE_UART */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USARTv1/uart_lld.h b/os/hal/platforms/STM32/USARTv1/uart_lld.h
deleted file mode 100644
index d9531ad7a..000000000
--- a/os/hal/platforms/STM32/USARTv1/uart_lld.h
+++ /dev/null
@@ -1,680 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USARTv1/uart_lld.h
- * @brief   STM32 low level UART driver header.
- *
- * @addtogroup UART
- * @{
- */
-
-#ifndef _UART_LLD_H_
-#define _UART_LLD_H_
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   UART driver on USART1 enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART1               FALSE
-#endif
-
-/**
- * @brief   UART driver on USART2 enable switch.
- * @details If set to @p TRUE the support for USART2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART2               FALSE
-#endif
-
-/**
- * @brief   UART driver on USART3 enable switch.
- * @details If set to @p TRUE the support for USART3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART3               FALSE
-#endif
-
-/**
- * @brief   UART driver on UART4 enable switch.
- * @details If set to @p TRUE the support for UART4 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__)
-#define STM32_UART_USE_UART4                FALSE
-#endif
-
-/**
- * @brief   UART driver on UART5 enable switch.
- * @details If set to @p TRUE the support for UART5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_UART5) || defined(__DOXYGEN__)
-#define STM32_UART_USE_UART5                FALSE
-#endif
-
-/**
- * @brief   UART driver on USART6 enable switch.
- * @details If set to @p TRUE the support for USART6 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART6               FALSE
-#endif
-
-/**
- * @brief   USART1 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_IRQ_PRIORITY      12
-#endif
-
-/**
- * @brief   USART2 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_IRQ_PRIORITY      12
-#endif
-
-/**
- * @brief   USART3 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_IRQ_PRIORITY      12
-#endif
-
-/**
- * @brief   UART4 interrupt priority level setting.
- */
-#if !defined(STM32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_UART4_IRQ_PRIORITY       12
-#endif
-
-/**
- * @brief   UART5 interrupt priority level setting.
- */
-#if !defined(STM32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_UART5_IRQ_PRIORITY       12
-#endif
-
-/**
- * @brief   USART6 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART6_IRQ_PRIORITY      12
-#endif
-
-/**
- * @brief   USART1 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_DMA_PRIORITY      0
-#endif
-
-/**
- * @brief   USART2 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_DMA_PRIORITY      0
-#endif
-
-/**
- * @brief   USART3 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_DMA_PRIORITY      0
-#endif
-
-/**
- * @brief   UART4 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(STM32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_UART4_DMA_PRIORITY       0
-#endif
-
-/**
- * @brief   UART5 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(STM32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_UART5_DMA_PRIORITY       0
-#endif
-
-/**
- * @brief   USART6 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART6_DMA_PRIORITY      0
-#endif
-
-/**
- * @brief   USART DMA error hook.
- * @note    The default action for DMA errors is a system halt because DMA
- *          error can only happen because programming errors.
- */
-#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()
-#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief   DMA stream used for USART1 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
-#endif
-
-/**
- * @brief   DMA stream used for USART1 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
-#endif
-
-/**
- * @brief   DMA stream used for USART2 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#endif
-
-/**
- * @brief   DMA stream used for USART2 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#endif
-
-/**
- * @brief   DMA stream used for USART3 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
-#endif
-
-/**
- * @brief   DMA stream used for USART3 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#endif
-
-/**
- * @brief   DMA stream used for UART4 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_UART4_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_UART4_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-#endif
-
-/**
- * @brief   DMA stream used for UART4 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_UART4_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_UART4_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-#endif
-
-/**
- * @brief   DMA stream used for UART5 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_UART5_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_UART5_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 0)
-#endif
-
-/**
- * @brief   DMA stream used for UART5 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_UART5_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_UART5_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-#endif
-
-/**
- * @brief   DMA stream used for USART6 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART6_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
-#endif
-
-/**
- * @brief   DMA stream used for USART6 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART6_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
-#endif
-
-#else /* !STM32_ADVANCED_DMA */
-
-/* Fixed streams for platforms using the old DMA peripheral, the values are
-   valid for both STM32F1xx and STM32L1xx.*/
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
-#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
-
-#endif /* !STM32_ADVANCED_DMA*/
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
-#error "USART1 not present in the selected device"
-#endif
-
-#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
-#error "USART2 not present in the selected device"
-#endif
-
-#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
-#error "USART3 not present in the selected device"
-#endif
-
-#if STM32_UART_USE_UART4 
-#if !STM32_HAS_UART4
-#error "UART4 not present in the selected device"
-#endif
-
-#if !defined(STM32F2XX) && !defined(STM32F4XX)
-#error "UART4 DMA access not supported in this platform"
-#endif
-#endif /* STM32_UART_USE_UART4 */
-
-#if STM32_UART_USE_UART5
-#if !STM32_HAS_UART5
-#error "UART5 not present in the selected device"
-#endif
-
-#if !defined(STM32F2XX) && !defined(STM32F4XX)
-#error "UART5 DMA access not supported in this platform"
-#endif
-#endif /* STM32_UART_USE_UART5 */
-
-#if STM32_UART_USE_USART6 && !STM32_HAS_USART6
-#error "USART6 not present in the selected device"
-#endif
-
-#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 &&                     \
-    !STM32_UART_USE_USART3 && !STM32_UART_USE_UART4 &&                      \
-    !STM32_UART_USE_UART5  && !STM32_UART_USE_USART6
-#error "UART driver activated but no USART/UART peripheral assigned"
-#endif
-
-#if STM32_UART_USE_USART1 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART1"
-#endif
-
-#if STM32_UART_USE_USART2 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART2"
-#endif
-
-#if STM32_UART_USE_USART3 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART3"
-#endif
-
-#if STM32_UART_USE_UART4 &&                                                 \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to UART4"
-#endif
-
-#if STM32_UART_USE_UART5 &&                                                 \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to UART5"
-#endif
-
-#if STM32_UART_USE_USART6 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART6"
-#endif
-
-#if STM32_UART_USE_USART1 &&                                                \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART1"
-#endif
-
-#if STM32_UART_USE_USART2 &&                                                \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART2"
-#endif
-
-#if STM32_UART_USE_USART3 &&                                                \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART3"
-#endif
-
-#if STM32_UART_USE_UART4 &&                                                 \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART4_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to UART4"
-#endif
-
-#if STM32_UART_USE_UART5 &&                                                 \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART5_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to UART5"
-#endif
-
-#if STM32_UART_USE_USART6 &&                                                \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART6"
-#endif
-
-#if STM32_UART_USE_USART1 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM,                 \
-                           STM32_USART1_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART1 RX"
-#endif
-
-#if STM32_UART_USE_USART1 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM,                 \
-                           STM32_USART1_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART1 TX"
-#endif
-
-#if STM32_UART_USE_USART2 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM,                 \
-                           STM32_USART2_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART2 RX"
-#endif
-
-#if STM32_UART_USE_USART2 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM,                 \
-                           STM32_USART2_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART2 TX"
-#endif
-
-#if STM32_UART_USE_USART3 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM,                 \
-                           STM32_USART3_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART3 RX"
-#endif
-
-#if STM32_UART_USE_USART3 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM,                 \
-                           STM32_USART3_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART3 TX"
-#endif
-
-#if STM32_UART_USE_UART4 &&                                                 \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM,                  \
-                           STM32_UART4_RX_DMA_MSK)
-#error "invalid DMA stream associated to UART4 RX"
-#endif
-
-#if STM32_UART_USE_UART4 &&                                                 \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM,                  \
-                           STM32_UART4_TX_DMA_MSK)
-#error "invalid DMA stream associated to UART4 TX"
-#endif
-
-#if STM32_UART_USE_UART5 &&                                                 \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM,                  \
-                           STM32_UART5_RX_DMA_MSK)
-#error "invalid DMA stream associated to UART5 RX"
-#endif
-
-#if STM32_UART_USE_UART5 &&                                                 \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM,                  \
-                           STM32_UART5_TX_DMA_MSK)
-#error "invalid DMA stream associated to UART5 TX"
-#endif
-
-#if STM32_UART_USE_USART6 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM,                 \
-                           STM32_USART6_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART6 RX"
-#endif
-
-#if STM32_UART_USE_USART6 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM,                 \
-                           STM32_USART6_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART6 TX"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART driver condition flags type.
- */
-typedef uint32_t uartflags_t;
-
-/**
- * @brief   Structure representing an UART driver.
- */
-typedef struct UARTDriver UARTDriver;
-
-/**
- * @brief   Generic UART notification callback type.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-typedef void (*uartcb_t)(UARTDriver *uartp);
-
-/**
- * @brief   Character received UART notification callback type.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] c         received character
- */
-typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
-
-/**
- * @brief   Receive error UART notification callback type.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] e         receive error mask
- */
-typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief End of transmission buffer callback.
-   */
-  uartcb_t                  txend1_cb;
-  /**
-   * @brief Physical end of transmission callback.
-   */
-  uartcb_t                  txend2_cb;
-  /**
-   * @brief Receive buffer filled callback.
-   */
-  uartcb_t                  rxend_cb;
-  /**
-   * @brief Character received while out if the @p UART_RECEIVE state.
-   */
-  uartccb_t                 rxchar_cb;
-  /**
-   * @brief Receive error callback.
-   */
-  uartecb_t                 rxerr_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  speed;
-  /**
-   * @brief Initialization value for the CR1 register.
-   */
-  uint16_t                  cr1;
-  /**
-   * @brief Initialization value for the CR2 register.
-   */
-  uint16_t                  cr2;
-  /**
-   * @brief Initialization value for the CR3 register.
-   */
-  uint16_t                  cr3;
-} UARTConfig;
-
-/**
- * @brief   Structure representing an UART driver.
- */
-struct UARTDriver {
-  /**
-   * @brief Driver state.
-   */
-  uartstate_t               state;
-  /**
-   * @brief Transmitter state.
-   */
-  uarttxstate_t             txstate;
-  /**
-   * @brief Receiver state.
-   */
-  uartrxstate_t             rxstate;
-  /**
-   * @brief Current configuration data.
-   */
-  const UARTConfig          *config;
-#if defined(UART_DRIVER_EXT_FIELDS)
-  UART_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the USART registers block.
-   */
-  USART_TypeDef             *usart;
-  /**
-   * @brief DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-  /**
-   * @brief Receive DMA channel.
-   */
-  const stm32_dma_stream_t  *dmarx;
-  /**
-   * @brief Transmit DMA channel.
-   */
-  const stm32_dma_stream_t  *dmatx;
-  /**
-   * @brief Default receive buffer while into @p UART_RX_IDLE state.
-   */
-  volatile uint16_t         rxbuf;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD1;
-#endif
-
-#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD2;
-#endif
-
-#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD3;
-#endif
-
-#if STM32_UART_USE_UART4 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD4;
-#endif
-
-#if STM32_UART_USE_UART5 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD5;
-#endif
-
-#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD6;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void uart_lld_init(void);
-  void uart_lld_start(UARTDriver *uartp);
-  void uart_lld_stop(UARTDriver *uartp);
-  void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
-  size_t uart_lld_stop_send(UARTDriver *uartp);
-  void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
-  size_t uart_lld_stop_receive(UARTDriver *uartp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_UART */
-
-#endif /* _UART_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USARTv2/serial_lld.c b/os/hal/platforms/STM32/USARTv2/serial_lld.c
deleted file mode 100644
index 44f02af1d..000000000
--- a/os/hal/platforms/STM32/USARTv2/serial_lld.c
+++ /dev/null
@@ -1,533 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USARTv2/serial_lld.c
- * @brief   STM32 low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief USART1 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/** @brief USART2 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/** @brief USART3 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/** @brief UART4 serial driver identifier.*/
-#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-SerialDriver SD4;
-#endif
-
-/** @brief UART5 serial driver identifier.*/
-#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-SerialDriver SD5;
-#endif
-
-/** @brief USART6 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-SerialDriver SD6;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config =
-{
-  SERIAL_DEFAULT_BITRATE,
-  0,
-  USART_CR2_STOP1_BITS | USART_CR2_LINEN,
-  0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   USART initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
-  USART_TypeDef *u = sdp->usart;
-
-  /* Baud rate setting.*/
-  u->BRR = (uint16_t)(sdp->clock / config->speed);
-
-  /* Note that some bits are enforced.*/
-  u->CR2 = config->cr2 | USART_CR2_LBDIE;
-  u->CR3 = config->cr3 | USART_CR3_EIE;
-  u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE |
-                         USART_CR1_RXNEIE | USART_CR1_TE |
-                         USART_CR1_RE;
-  u->ICR = 0xFFFFFFFF;
-}
-
-/**
- * @brief   USART de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] u         pointer to an USART I/O block
- */
-static void usart_deinit(USART_TypeDef *u) {
-
-  u->CR1 = 0;
-  u->CR2 = 0;
-  u->CR3 = 0;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] isr       USART ISR register value
- */
-static void set_error(SerialDriver *sdp, uint32_t isr) {
-  flagsmask_t sts = 0;
-
-  if (isr & USART_ISR_ORE)
-    sts |= SD_OVERRUN_ERROR;
-  if (isr & USART_ISR_PE)
-    sts |= SD_PARITY_ERROR;
-  if (isr & USART_ISR_FE)
-    sts |= SD_FRAMING_ERROR;
-  if (isr & USART_ISR_NE)
-    sts |= SD_NOISE_ERROR;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] sdp       communication channel associated to the USART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  USART_TypeDef *u = sdp->usart;
-  uint32_t cr1 = u->CR1;
-  uint32_t isr;
-
-  /* Reading and clearing status.*/
-  isr = u->ISR;
-  u->ICR = isr;
-
-  /* Error condition detection.*/
-  if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE  | USART_ISR_PE))
-    set_error(sdp, isr);
-
-  /* Special case, LIN break detection.*/
-  if (isr & USART_ISR_LBD) {
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, SD_BREAK_DETECTED);
-    chSysUnlockFromIsr();
-  }
-
-  /* Data available.*/
-  if (isr & USART_ISR_RXNE) {
-    chSysLockFromIsr();
-    sdIncomingDataI(sdp, (uint8_t)u->RDR);
-    chSysUnlockFromIsr();
-  }
-
-  /* Transmission buffer empty.*/
-  if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
-    msg_t b;
-    chSysLockFromIsr();
-    b = chOQGetI(&sdp->oqueue);
-    if (b < Q_OK) {
-      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-      u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
-    }
-    else
-      u->TDR = b;
-    chSysUnlockFromIsr();
-  }
-
-  /* Physical transmission end.*/
-  if (isr & USART_ISR_TC) {
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
-    chSysUnlockFromIsr();
-    u->CR1 = cr1 & ~USART_CR1_TCIE;
-  }
-}
-
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  USART1->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  USART2->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
-  (void)qp;
-  USART3->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-static void notify4(GenericQueue *qp) {
-
-  (void)qp;
-  UART4->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-static void notify5(GenericQueue *qp) {
-
-  (void)qp;
-  UART5->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-static void notify6(GenericQueue *qp) {
-
-  (void)qp;
-  USART6->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-#if !defined(STM32_USART1_HANDLER)
-#error "STM32_USART1_HANDLER not defined"
-#endif
-/**
- * @brief   USART1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-#if !defined(STM32_USART2_HANDLER)
-#error "STM32_USART2_HANDLER not defined"
-#endif
-/**
- * @brief   USART2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-#if !defined(STM32_USART3_HANDLER)
-#error "STM32_USART3_HANDLER not defined"
-#endif
-/**
- * @brief   USART3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
-#if !defined(STM32_UART4_HANDLER)
-#error "STM32_UART4_HANDLER not defined"
-#endif
-/**
- * @brief   UART4 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-#if !defined(STM32_UART5_HANDLER)
-#error "STM32_UART5_HANDLER not defined"
-#endif
-/**
- * @brief   UART5 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD5);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
-#if !defined(STM32_USART6_HANDLER)
-#error "STM32_USART6_HANDLER not defined"
-#endif
-/**
- * @brief   USART1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART6_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD6);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if STM32_SERIAL_USE_USART1
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.usart = USART1;
-  SD1.clock = STM32_USART1CLK;
-#endif
-
-#if STM32_SERIAL_USE_USART2
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.usart = USART2;
-  SD2.clock = STM32_USART2CLK;
-#endif
-
-#if STM32_SERIAL_USE_USART3
-  sdObjectInit(&SD3, NULL, notify3);
-  SD3.usart = USART3;
-  SD3.clock = STM32_USART3CLK;
-#endif
-
-#if STM32_SERIAL_USE_UART4
-  sdObjectInit(&SD4, NULL, notify4);
-  SD4.usart = UART4;
-  SD4.clock = STM32_UART4CLK;
-#endif
-
-#if STM32_SERIAL_USE_UART5
-  sdObjectInit(&SD5, NULL, notify5);
-  SD5.usart = UART5;
-  SD5.clock = STM32_UART5CLK;
-#endif
-
-#if STM32_SERIAL_USE_USART6
-  sdObjectInit(&SD6, NULL, notify6);
-  SD6.usart = USART6;
-  SD6.clock = STM32_USART6CLK;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if STM32_SERIAL_USE_USART1
-    if (&SD1 == sdp) {
-      rccEnableUSART1(FALSE);
-      nvicEnableVector(STM32_USART1_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_USART2
-    if (&SD2 == sdp) {
-      rccEnableUSART2(FALSE);
-      nvicEnableVector(STM32_USART2_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_USART3
-    if (&SD3 == sdp) {
-      rccEnableUSART3(FALSE);
-      nvicEnableVector(STM32_USART3_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_UART4
-    if (&SD4 == sdp) {
-      rccEnableUART4(FALSE);
-      nvicEnableVector(STM32_UART4_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_UART5
-    if (&SD5 == sdp) {
-      rccEnableUART5(FALSE);
-      nvicEnableVector(STM32_UART5_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_USART6
-    if (&SD6 == sdp) {
-      rccEnableUSART6(FALSE);
-      nvicEnableVector(STM32_USART6_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY));
-    }
-#endif
-  }
-  usart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    usart_deinit(sdp->usart);
-#if STM32_SERIAL_USE_USART1
-    if (&SD1 == sdp) {
-      rccDisableUSART1(FALSE);
-      nvicDisableVector(STM32_USART1_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_USART2
-    if (&SD2 == sdp) {
-      rccDisableUSART2(FALSE);
-      nvicDisableVector(STM32_USART2_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_USART3
-    if (&SD3 == sdp) {
-      rccDisableUSART3(FALSE);
-      nvicDisableVector(STM32_USART3_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_UART4
-    if (&SD4 == sdp) {
-      rccDisableUART4(FALSE);
-      nvicDisableVector(STM32_UART4_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_UART5
-    if (&SD5 == sdp) {
-      rccDisableUART5(FALSE);
-      nvicDisableVector(STM32_UART5_NUMBER);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_USART6
-    if (&SD6 == sdp) {
-      rccDisableUSART6(FALSE);
-      nvicDisableVector(STM32_USART6_NUMBER);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USARTv2/serial_lld.h b/os/hal/platforms/STM32/USARTv2/serial_lld.h
deleted file mode 100644
index 743cb0b50..000000000
--- a/os/hal/platforms/STM32/USARTv2/serial_lld.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USARTv2/serial_lld.h
- * @brief   STM32 low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   USART1 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART1             FALSE
-#endif
-
-/**
- * @brief   USART2 driver enable switch.
- * @details If set to @p TRUE the support for USART2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART2             FALSE
-#endif
-
-/**
- * @brief   USART3 driver enable switch.
- * @details If set to @p TRUE the support for USART3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART3             FALSE
-#endif
-
-/**
- * @brief   UART4 driver enable switch.
- * @details If set to @p TRUE the support for UART4 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_UART4              FALSE
-#endif
-
-/**
- * @brief   UART5 driver enable switch.
- * @details If set to @p TRUE the support for UART5 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_UART5              FALSE
-#endif
-
-/**
- * @brief   USART6 driver enable switch.
- * @details If set to @p TRUE the support for USART6 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART6             FALSE
-#endif
-
-/**
- * @brief   USART1 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART1_PRIORITY        12
-#endif
-
-/**
- * @brief   USART2 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART2_PRIORITY        12
-#endif
-
-/**
- * @brief   USART3 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART3_PRIORITY        12
-#endif
-
-/**
- * @brief   UART4 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_UART4_PRIORITY         12
-#endif
-
-/**
- * @brief   UART5 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_UART5_PRIORITY         12
-#endif
-
-/**
- * @brief   USART6 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART6_PRIORITY        12
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1
-#error "USART1 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2
-#error "USART2 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3
-#error "USART3 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4
-#error "UART4 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5
-#error "UART5 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6
-#error "USART6 not present in the selected device"
-#endif
-
-#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 &&                 \
-    !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4  &&                 \
-    !STM32_SERIAL_USE_UART5  && !STM32_SERIAL_USE_USART6
-#error "SERIAL driver activated but no USART/UART peripheral assigned"
-#endif
-
-#if STM32_SERIAL_USE_USART1 &&                                              \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
-#error "Invalid IRQ priority assigned to USART1"
-#endif
-
-#if STM32_SERIAL_USE_USART2 &&                                              \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
-#error "Invalid IRQ priority assigned to USART2"
-#endif
-
-#if STM32_SERIAL_USE_USART3 &&                                              \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
-#error "Invalid IRQ priority assigned to USART3"
-#endif
-
-#if STM32_SERIAL_USE_UART4 &&                                               \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
-#error "Invalid IRQ priority assigned to UART4"
-#endif
-
-#if STM32_SERIAL_USE_UART5 &&                                               \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
-#error "Invalid IRQ priority assigned to UART5"
-#endif
-
-#if STM32_SERIAL_USE_USART6 &&                                              \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
-#error "Invalid IRQ priority assigned to USART6"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    This structure content is architecture dependent, each driver
- *          implementation defines its own version and the custom static
- *          initializers.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  speed;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Initialization value for the CR1 register.
-   */
-  uint32_t                  cr1;
-  /**
-   * @brief Initialization value for the CR2 register.
-   */
-  uint32_t                  cr2;
-  /**
-   * @brief Initialization value for the CR3 register.
-   */
-  uint32_t                  cr3;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  USART_TypeDef             *usart;                                         \
-  /* Clock frequency for the associated USART/UART.*/                       \
-  uint32_t                  clock;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*
- * Extra USARTs definitions here (missing from the ST header file).
- */
-#define USART_CR2_STOP1_BITS    (0 << 12)   /**< @brief CR2 1 stop bit value.*/
-#define USART_CR2_STOP0P5_BITS  (1 << 12)   /**< @brief CR2 0.5 stop bit value.*/
-#define USART_CR2_STOP2_BITS    (2 << 12)   /**< @brief CR2 2 stop bit value.*/
-#define USART_CR2_STOP1P5_BITS  (3 << 12)   /**< @brief CR2 1.5 stop bit value.*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
-extern SerialDriver SD4;
-#endif
-#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
-extern SerialDriver SD5;
-#endif
-#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
-extern SerialDriver SD6;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USARTv2/uart_lld.c b/os/hal/platforms/STM32/USARTv2/uart_lld.c
deleted file mode 100644
index 740c2fd98..000000000
--- a/os/hal/platforms/STM32/USARTv2/uart_lld.c
+++ /dev/null
@@ -1,594 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USARTv2/uart_lld.c
- * @brief   STM32 low level UART driver code.
- *
- * @addtogroup UART
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define USART1_RX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM,                     \
-                       STM32_USART1_RX_DMA_CHN)
-
-#define USART1_TX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM,                     \
-                       STM32_USART1_TX_DMA_CHN)
-
-#define USART2_RX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM,                     \
-                       STM32_USART2_RX_DMA_CHN)
-
-#define USART2_TX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM,                     \
-                       STM32_USART2_TX_DMA_CHN)
-
-#define USART3_RX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM,                     \
-                       STM32_USART3_RX_DMA_CHN)
-
-#define USART3_TX_DMA_CHANNEL                                               \
-  STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM,                     \
-                       STM32_USART3_TX_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief USART1 UART driver identifier.*/
-#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
-UARTDriver UARTD1;
-#endif
-
-/** @brief USART2 UART driver identifier.*/
-#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
-UARTDriver UARTD2;
-#endif
-
-/** @brief USART3 UART driver identifier.*/
-#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
-UARTDriver UARTD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Status bits translation.
- *
- * @param[in] sr        USART SR register value
- *
- * @return  The error flags.
- */
-static uartflags_t translate_errors(uint32_t isr) {
-  uartflags_t sts = 0;
-
-  if (isr & USART_ISR_ORE)
-    sts |= UART_OVERRUN_ERROR;
-  if (isr & USART_ISR_PE)
-    sts |= UART_PARITY_ERROR;
-  if (isr & USART_ISR_FE)
-    sts |= UART_FRAMING_ERROR;
-  if (isr & USART_ISR_NE)
-    sts |= UART_NOISE_ERROR;
-  if (isr & USART_ISR_LBD)
-    sts |= UART_BREAK_DETECTED;
-  return sts;
-}
-
-/**
- * @brief   Puts the receiver in the UART_RX_IDLE state.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-static void set_rx_idle_loop(UARTDriver *uartp) {
-  uint32_t mode;
-  
-  /* RX DMA channel preparation, if the char callback is defined then the
-     TCIE interrupt is enabled too.*/
-  if (uartp->config->rxchar_cb == NULL)
-    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
-  else
-    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
-  dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
-  dmaStreamSetTransactionSize(uartp->dmarx, 1);
-  dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);
-  dmaStreamEnable(uartp->dmarx);
-}
-
-/**
- * @brief   USART de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-static void usart_stop(UARTDriver *uartp) {
-
-  /* Stops RX and TX DMA channels.*/
-  dmaStreamDisable(uartp->dmarx);
-  dmaStreamDisable(uartp->dmatx);
-  
-  /* Stops USART operations.*/
-  uartp->usart->CR1 = 0;
-  uartp->usart->CR2 = 0;
-  uartp->usart->CR3 = 0;
-}
-
-/**
- * @brief   USART initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-static void usart_start(UARTDriver *uartp) {
-  uint32_t cr1;
-  USART_TypeDef *u = uartp->usart;
-
-  /* Defensive programming, starting from a clean state.*/
-  usart_stop(uartp);
-
-  /* Baud rate setting.*/
-#if defined(STM32F0XX)
-  if (uartp->usart == USART1)
-    u->BRR = STM32_USART1CLK / uartp->config->speed;
-  else
-    u->BRR = STM32_PCLK / uartp->config->speed;
-#else /* !defined(STM32F0XX) */
-  if (uartp->usart == USART1)
-    u->BRR = STM32_PCLK2 / uartp->config->speed;
-  else
-    u->BRR = STM32_PCLK1 / uartp->config->speed;
-#endif /* !defined(STM32F0XX) */
-
-  /* Resetting eventual pending status flags.*/
-  u->ICR = 0xFFFFFFFF;
-
-  /* Note that some bits are enforced because required for correct driver
-     operations.*/
-  u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
-  u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
-                                USART_CR3_EIE;
-  if (uartp->config->txend2_cb == NULL)
-    cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
-  else
-    cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE |
-          USART_CR1_TCIE;
-  u->CR1 = uartp->config->cr1 | cr1;
-
-  /* Starting the receiver idle loop.*/
-  set_rx_idle_loop(uartp);
-}
-
-/**
- * @brief   RX DMA common service routine.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-#if defined(STM32_UART_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_UART_DMA_ERROR_HOOK(uartp);
-  }
-#else
-  (void)flags;
-#endif
-
-  if (uartp->rxstate == UART_RX_IDLE) {
-    /* Receiver in idle state, a callback is generated, if enabled, for each
-       received character and then the driver stays in the same state.*/
-    if (uartp->config->rxchar_cb != NULL)
-      uartp->config->rxchar_cb(uartp, uartp->rxbuf);
-  }
-  else {
-    /* Receiver in active state, a callback is generated, if enabled, after
-       a completed transfer.*/
-    dmaStreamDisable(uartp->dmarx);
-    uartp->rxstate = UART_RX_COMPLETE;
-    if (uartp->config->rxend_cb != NULL)
-      uartp->config->rxend_cb(uartp);
-
-    /* If the callback didn't explicitly change state then the receiver
-       automatically returns to the idle state.*/
-    if (uartp->rxstate == UART_RX_COMPLETE) {
-      uartp->rxstate = UART_RX_IDLE;
-      set_rx_idle_loop(uartp);
-    }
-  }
-}
-
-/**
- * @brief   TX DMA common service routine.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-#if defined(STM32_UART_DMA_ERROR_HOOK)
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    STM32_UART_DMA_ERROR_HOOK(uartp);
-  }
-#else
-  (void)flags;
-#endif
-
-  dmaStreamDisable(uartp->dmatx);
-
-  /* A callback is generated, if enabled, after a completed transfer.*/
-  uartp->txstate = UART_TX_COMPLETE;
-  if (uartp->config->txend1_cb != NULL)
-    uartp->config->txend1_cb(uartp);
-
-  /* If the callback didn't explicitly change state then the transmitter
-     automatically returns to the idle state.*/
-  if (uartp->txstate == UART_TX_COMPLETE)
-    uartp->txstate = UART_TX_IDLE;
-}
-
-/**
- * @brief   USART common service routine.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-static void serve_usart_irq(UARTDriver *uartp) {
-  uint32_t isr;
-  USART_TypeDef *u = uartp->usart;
-  
-  /* Reading and clearing status.*/
-  isr = u->ISR;
-  u->ICR = isr;
-
-  if (isr & (USART_ISR_LBD | USART_ISR_ORE | USART_ISR_NE |
-             USART_ISR_FE  | USART_ISR_PE)) {
-    if (uartp->config->rxerr_cb != NULL)
-      uartp->config->rxerr_cb(uartp, translate_errors(isr));
-  }
-  if (isr & USART_ISR_TC) {
-    /* End of transmission, a callback is generated.*/
-    if (uartp->config->txend2_cb != NULL)
-      uartp->config->txend2_cb(uartp);
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
-#if !defined(STM32_USART1_HANDLER)
-#error "STM32_USART1_HANDLER not defined"
-#endif
-/**
- * @brief   USART1 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_usart_irq(&UARTD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART1 */
-
-#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
-#if !defined(STM32_USART2_HANDLER)
-#error "STM32_USART2_HANDLER not defined"
-#endif
-/**
- * @brief   USART2 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_usart_irq(&UARTD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART2 */
-
-#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
-#if !defined(STM32_USART3_HANDLER)
-#error "STM32_USART3_HANDLER not defined"
-#endif
-/**
- * @brief   USART3 IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_usart_irq(&UARTD3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_UART_USE_USART3 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level UART driver initialization.
- *
- * @notapi
- */
-void uart_lld_init(void) {
-
-#if STM32_UART_USE_USART1
-  uartObjectInit(&UARTD1);
-  UARTD1.usart   = USART1;
-  UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-  UARTD1.dmarx   = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
-  UARTD1.dmatx   = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
-#endif
-
-#if STM32_UART_USE_USART2
-  uartObjectInit(&UARTD2);
-  UARTD2.usart   = USART2;
-  UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-  UARTD2.dmarx   = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
-  UARTD2.dmatx   = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
-#endif
-
-#if STM32_UART_USE_USART3
-  uartObjectInit(&UARTD3);
-  UARTD3.usart   = USART3;
-  UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-  UARTD3.dmarx   = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
-  UARTD3.dmatx   = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
-#endif
-}
-
-/**
- * @brief   Configures and activates the UART peripheral.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- *
- * @notapi
- */
-void uart_lld_start(UARTDriver *uartp) {
-
-  if (uartp->state == UART_STOP) {
-#if STM32_UART_USE_USART1
-    if (&UARTD1 == uartp) {
-      bool_t b;
-      b = dmaStreamAllocate(uartp->dmarx,
-                            STM32_UART_USART1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated");
-      b = dmaStreamAllocate(uartp->dmatx,
-                            STM32_UART_USART1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
-      rccEnableUSART1(FALSE);
-      nvicEnableVector(STM32_USART1_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
-      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
-    }
-#endif
-
-#if STM32_UART_USE_USART2
-    if (&UARTD2 == uartp) {
-      bool_t b;
-      b = dmaStreamAllocate(uartp->dmarx,
-                            STM32_UART_USART2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated");
-      b = dmaStreamAllocate(uartp->dmatx,
-                            STM32_UART_USART2_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
-      rccEnableUSART2(FALSE);
-      nvicEnableVector(STM32_USART2_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
-      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
-    }
-#endif
-
-#if STM32_UART_USE_USART3
-    if (&UARTD3 == uartp) {
-      bool_t b;
-      b = dmaStreamAllocate(uartp->dmarx,
-                            STM32_UART_USART3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
-      b = dmaStreamAllocate(uartp->dmatx,
-                            STM32_UART_USART3_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                            (void *)uartp);
-      chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
-      rccEnableUSART3(FALSE);
-      nvicEnableVector(STM32_USART3_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
-      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
-                        STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
-    }
-#endif
-
-    /* Static DMA setup, the transfer size depends on the USART settings,
-       it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
-    if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
-      uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-    dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR);
-    dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR);
-    uartp->rxbuf = 0;
-  }
-
-  uartp->rxstate = UART_RX_IDLE;
-  uartp->txstate = UART_TX_IDLE;
-  usart_start(uartp);
-}
-
-/**
- * @brief   Deactivates the UART peripheral.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- *
- * @notapi
- */
-void uart_lld_stop(UARTDriver *uartp) {
-
-  if (uartp->state == UART_READY) {
-    usart_stop(uartp);
-    dmaStreamRelease(uartp->dmarx);
-    dmaStreamRelease(uartp->dmatx);
-
-#if STM32_UART_USE_USART1
-    if (&UARTD1 == uartp) {
-      nvicDisableVector(STM32_USART1_NUMBER);
-      rccDisableUSART1(FALSE);
-      return;
-    }
-#endif
-
-#if STM32_UART_USE_USART2
-    if (&UARTD2 == uartp) {
-      nvicDisableVector(STM32_USART2_NUMBER);
-      rccDisableUSART2(FALSE);
-      return;
-    }
-#endif
-
-#if STM32_UART_USE_USART3
-    if (&UARTD3 == uartp) {
-      nvicDisableVector(STM32_USART3_NUMBER);
-      rccDisableUSART3(FALSE);
-      return;
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts a transmission on the UART peripheral.
- * @note    The buffers are organized as uint8_t arrays for data sizes below
- *          or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] n         number of data frames to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
-
-  /* TX DMA channel preparation and start.*/
-  dmaStreamSetMemory0(uartp->dmatx, txbuf);
-  dmaStreamSetTransactionSize(uartp->dmatx, n);
-  dmaStreamSetMode(uartp->dmatx, uartp->dmamode    | STM32_DMA_CR_DIR_M2P |
-                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
-  dmaStreamEnable(uartp->dmatx);
-}
-
-/**
- * @brief   Stops any ongoing transmission.
- * @note    Stopping a transmission also suppresses the transmission callbacks.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- *
- * @return              The number of data frames not transmitted by the
- *                      stopped transmit operation.
- *
- * @notapi
- */
-size_t uart_lld_stop_send(UARTDriver *uartp) {
-
-  dmaStreamDisable(uartp->dmatx);
-  return dmaStreamGetTransactionSize(uartp->dmatx);
-}
-
-/**
- * @brief   Starts a receive operation on the UART peripheral.
- * @note    The buffers are organized as uint8_t arrays for data sizes below
- *          or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] n         number of data frames to send
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
-
-  /* Stopping previous activity (idle state).*/
-  dmaStreamDisable(uartp->dmarx);
-
-  /* RX DMA channel preparation and start.*/
-  dmaStreamSetMemory0(uartp->dmarx, rxbuf);
-  dmaStreamSetTransactionSize(uartp->dmarx, n);
-  dmaStreamSetMode(uartp->dmarx, uartp->dmamode    | STM32_DMA_CR_DIR_P2M |
-                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
-  dmaStreamEnable(uartp->dmarx);
-}
-
-/**
- * @brief   Stops any ongoing receive operation.
- * @note    Stopping a receive operation also suppresses the receive callbacks.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- *
- * @return              The number of data frames not received by the
- *                      stopped receive operation.
- *
- * @notapi
- */
-size_t uart_lld_stop_receive(UARTDriver *uartp) {
-  size_t n;
-
-  dmaStreamDisable(uartp->dmarx);
-  n = dmaStreamGetTransactionSize(uartp->dmarx);
-  set_rx_idle_loop(uartp);
-  return n;
-}
-
-#endif /* HAL_USE_UART */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USARTv2/uart_lld.h b/os/hal/platforms/STM32/USARTv2/uart_lld.h
deleted file mode 100644
index 6d44af0ba..000000000
--- a/os/hal/platforms/STM32/USARTv2/uart_lld.h
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USARTv2/uart_lld.h
- * @brief   STM32 low level UART driver header.
- *
- * @addtogroup UART
- * @{
- */
-
-#ifndef _UART_LLD_H_
-#define _UART_LLD_H_
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   UART driver on USART1 enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART1               FALSE
-#endif
-
-/**
- * @brief   UART driver on USART2 enable switch.
- * @details If set to @p TRUE the support for USART2 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART2               FALSE
-#endif
-
-/**
- * @brief   UART driver on USART3 enable switch.
- * @details If set to @p TRUE the support for USART3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
-#define STM32_UART_USE_USART3               FALSE
-#endif
-
-/**
- * @brief   USART1 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_IRQ_PRIORITY      12
-#endif
-
-/**
- * @brief   USART2 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_IRQ_PRIORITY      12
-#endif
-
-/**
- * @brief   USART3 interrupt priority level setting.
- */
-#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_IRQ_PRIORITY      12
-#endif
-
-/**
- * @brief   USART1 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_DMA_PRIORITY      0
-#endif
-
-/**
- * @brief   USART2 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_DMA_PRIORITY      0
-#endif
-
-/**
- * @brief   USART3 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_DMA_PRIORITY      0
-#endif
-
-/**
- * @brief   USART1 DMA error hook.
- * @note    The default action for DMA errors is a system halt because DMA
- *          error can only happen because programming errors.
- */
-#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()
-#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief   DMA stream used for USART1 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
-#endif
-
-/**
- * @brief   DMA stream used for USART1 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
-#endif
-
-/**
- * @brief   DMA stream used for USART2 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#endif
-
-/**
- * @brief   DMA stream used for USART2 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#endif
-
-/**
- * @brief   DMA stream used for USART3 RX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
-#endif
-
-/**
- * @brief   DMA stream used for USART3 TX operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#endif
-
-#else /* !STM32_ADVANCED_DMA*/
-
-#if defined(STM32F0XX)
-/* Fixed values for STM32F0xx devices.*/
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-#endif /* defined(STM32F0XX) */
-
-#if defined(STM32F30X)|| defined(STM32F37X)
-/* Fixed values for STM32F3xx devices.*/
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-#endif /* defined(STM32F30X) */
-
-#endif /* !STM32_ADVANCED_DMA*/
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
-#error "USART1 not present in the selected device"
-#endif
-
-#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
-#error "USART2 not present in the selected device"
-#endif
-
-#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
-#error "USART3 not present in the selected device"
-#endif
-
-#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 &&                     \
-    !STM32_UART_USE_USART3
-#error "UART driver activated but no USART/UART peripheral assigned"
-#endif
-
-#if STM32_UART_USE_USART1 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART1"
-#endif
-
-#if STM32_UART_USE_USART2 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART2"
-#endif
-
-#if STM32_UART_USE_USART3 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USART3"
-#endif
-
-#if STM32_UART_USE_USART1 &&                                                \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART1"
-#endif
-
-#if STM32_UART_USE_USART2 &&                                                \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART2"
-#endif
-
-#if STM32_UART_USE_USART3 &&                                                \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to USART3"
-#endif
-
-#if STM32_UART_USE_USART1 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM,                 \
-                           STM32_USART1_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART1 RX"
-#endif
-
-#if STM32_UART_USE_USART1 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM,                 \
-                           STM32_USART1_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART1 TX"
-#endif
-
-#if STM32_UART_USE_USART2 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM,                 \
-                           STM32_USART2_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART2 RX"
-#endif
-
-#if STM32_UART_USE_USART2 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM,                 \
-                           STM32_USART2_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART2 TX"
-#endif
-
-#if STM32_UART_USE_USART3 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM,                 \
-                           STM32_USART3_RX_DMA_MSK)
-#error "invalid DMA stream associated to USART3 RX"
-#endif
-
-#if STM32_UART_USE_USART3 &&                                                \
-    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM,                 \
-                           STM32_USART3_TX_DMA_MSK)
-#error "invalid DMA stream associated to USART3 TX"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART driver condition flags type.
- */
-typedef uint32_t uartflags_t;
-
-/**
- * @brief   Structure representing an UART driver.
- */
-typedef struct UARTDriver UARTDriver;
-
-/**
- * @brief   Generic UART notification callback type.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-typedef void (*uartcb_t)(UARTDriver *uartp);
-
-/**
- * @brief   Character received UART notification callback type.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] c         received character
- */
-typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
-
-/**
- * @brief   Receive error UART notification callback type.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] e         receive error mask
- */
-typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief End of transmission buffer callback.
-   */
-  uartcb_t                  txend1_cb;
-  /**
-   * @brief Physical end of transmission callback.
-   */
-  uartcb_t                  txend2_cb;
-  /**
-   * @brief Receive buffer filled callback.
-   */
-  uartcb_t                  rxend_cb;
-  /**
-   * @brief Character received while out if the @p UART_RECEIVE state.
-   */
-  uartccb_t                 rxchar_cb;
-  /**
-   * @brief Receive error callback.
-   */
-  uartecb_t                 rxerr_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  speed;
-  /**
-   * @brief Initialization value for the CR1 register.
-   */
-  uint32_t                  cr1;
-  /**
-   * @brief Initialization value for the CR2 register.
-   */
-  uint32_t                  cr2;
-  /**
-   * @brief Initialization value for the CR3 register.
-   */
-  uint32_t                  cr3;
-} UARTConfig;
-
-/**
- * @brief   Structure representing an UART driver.
- */
-struct UARTDriver {
-  /**
-   * @brief Driver state.
-   */
-  uartstate_t               state;
-  /**
-   * @brief Transmitter state.
-   */
-  uarttxstate_t             txstate;
-  /**
-   * @brief Receiver state.
-   */
-  uartrxstate_t             rxstate;
-  /**
-   * @brief Current configuration data.
-   */
-  const UARTConfig          *config;
-#if defined(UART_DRIVER_EXT_FIELDS)
-  UART_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the USART registers block.
-   */
-  USART_TypeDef             *usart;
-  /**
-   * @brief DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-  /**
-   * @brief Receive DMA channel.
-   */
-  const stm32_dma_stream_t  *dmarx;
-  /**
-   * @brief Transmit DMA channel.
-   */
-  const stm32_dma_stream_t  *dmatx;
-  /**
-   * @brief Default receive buffer while into @p UART_RX_IDLE state.
-   */
-  volatile uint16_t         rxbuf;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD1;
-#endif
-
-#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD2;
-#endif
-
-#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void uart_lld_init(void);
-  void uart_lld_start(UARTDriver *uartp);
-  void uart_lld_stop(UARTDriver *uartp);
-  void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
-  size_t uart_lld_stop_send(UARTDriver *uartp);
-  void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
-  size_t uart_lld_stop_receive(UARTDriver *uartp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_UART */
-
-#endif /* _UART_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.c b/os/hal/platforms/STM32/USBv1/usb_lld.c
deleted file mode 100644
index 22af59866..000000000
--- a/os/hal/platforms/STM32/USBv1/usb_lld.c
+++ /dev/null
@@ -1,830 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USBv1/usb_lld.c
- * @brief   STM32 USB subsystem low level driver source.
- *
- * @addtogroup USB
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define BTABLE_ADDR     0x0000
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief USB1 driver identifier.*/
-#if STM32_USB_USE_USB1 || defined(__DOXYGEN__)
-USBDriver USBD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EP0 state.
- * @note    It is an union because IN and OUT endpoints are never used at the
- *          same time for EP0.
- */
-static union {
-  /**
-   * @brief   IN EP0 state.
-   */
-  USBInEndpointState in;
-  /**
-   * @brief   OUT EP0 state.
-   */
-  USBOutEndpointState out;
-} ep0_state;
-
-/**
- * @brief   Buffer for the EP0 setup packets.
- */
-static uint8_t ep0setup_buffer[8];
-
-/**
- * @brief   EP0 initialization structure.
- */
-static const USBEndpointConfig ep0config = {
-  USB_EP_MODE_TYPE_CTRL,
-  _usb_ep0setup,
-  _usb_ep0in,
-  _usb_ep0out,
-  0x40,
-  0x40,
-  &ep0_state.in,
-  &ep0_state.out,
-  1,
-  ep0setup_buffer
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Resets the packet memory allocator.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- */
-static void usb_pm_reset(USBDriver *usbp) {
-
-  /* The first 64 bytes are reserved for the descriptors table. The effective
-     available RAM for endpoint buffers is just 448 bytes.*/
-  usbp->pmnext = 64;
-}
-
-/**
- * @brief   Resets the packet memory allocator.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] size      size of the packet buffer to allocate
- */
-static uint32_t usb_pm_alloc(USBDriver *usbp, size_t size) {
-  uint32_t next;
-
-  next = usbp->pmnext;
-  usbp->pmnext += size;
-  chDbgAssert(usbp->pmnext <= USB_PMA_SIZE, "usb_pm_alloc(), #1", "PMA overflow");
-  return next;
-}
-
-/**
- * @brief   Reads from a dedicated packet buffer.
- *
- * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
- * @param[out] buf      buffer where to copy the packet data
- * @param[in] n         maximum number of bytes to copy. This value must
- *                      not exceed the maximum packet size for this endpoint.
- *
- * @notapi
- */
-static void usb_packet_read_to_buffer(stm32_usb_descriptor_t *udp,
-                                      uint8_t *buf, size_t n) {
-  uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0);
-
-  n = (n + 1) / 2;
-  while (n > 0) {
-    /* Note, this line relies on the Cortex-M3/M4 ability to perform
-       unaligned word accesses.*/
-    *(uint16_t *)buf = (uint16_t)*pmap++;
-    buf += 2;
-    n--;
-  }
-}
-
-/**
- * @brief   Reads from a dedicated packet buffer.
- *
- * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
- * @param[in] iqp       pointer to an @p InputQueue object
- * @param[in] n         maximum number of bytes to copy. This value must
- *                      not exceed the maximum packet size for this endpoint.
- *
- * @notapi
- */
-static void usb_packet_read_to_queue(stm32_usb_descriptor_t *udp,
-                                     InputQueue *iqp, size_t n) {
-  size_t nhw;
-  uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0);
-
-  nhw = n / 2;
-  while (nhw > 0) {
-    uint32_t w;
-
-    w = *pmap++;
-    *iqp->q_wrptr++ = (uint8_t)w;
-    if (iqp->q_wrptr >= iqp->q_top)
-      iqp->q_wrptr = iqp->q_buffer;
-    *iqp->q_wrptr++ = (uint8_t)(w >> 8);
-    if (iqp->q_wrptr >= iqp->q_top)
-      iqp->q_wrptr = iqp->q_buffer;
-    nhw--;
-  }
-  /* Last byte for odd numbers.*/
-  if ((n & 1) != 0) {
-    *iqp->q_wrptr++ = (uint8_t)*pmap;
-    if (iqp->q_wrptr >= iqp->q_top)
-      iqp->q_wrptr = iqp->q_buffer;
-  }
-
-  /* Updating queue.*/
-  chSysLockFromIsr();
-  iqp->q_counter += n;
-  while (notempty(&iqp->q_waiting))
-    chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK;
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Writes to a dedicated packet buffer.
- *
- * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
- * @param[in] buf       buffer where to fetch the packet data
- * @param[in] n         maximum number of bytes to copy. This value must
- *                      not exceed the maximum packet size for this endpoint.
- *
- * @notapi
- */
-static void usb_packet_write_from_buffer(stm32_usb_descriptor_t *udp,
-                                         const uint8_t *buf,
-                                         size_t n) {
-  uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0);
-
-  udp->TXCOUNT0 = (uint16_t)n;
-  n = (n + 1) / 2;
-  while (n > 0) {
-    /* Note, this line relies on the Cortex-M3/M4 ability to perform
-       unaligned word accesses.*/
-    *pmap++ = *(uint16_t *)buf;
-    buf += 2;
-    n--;
-  }
-}
-
-/**
- * @brief   Writes to a dedicated packet buffer.
- *
- * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
- * @param[in] buf       buffer where to fetch the packet data
- * @param[in] n         maximum number of bytes to copy. This value must
- *                      not exceed the maximum packet size for this endpoint.
- *
- * @notapi
- */
-static void usb_packet_write_from_queue(stm32_usb_descriptor_t *udp,
-                                        OutputQueue *oqp, size_t n) {
-  size_t nhw;
-  uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0);
-
-  udp->TXCOUNT0 = (uint16_t)n;
-  nhw = n / 2;
-  while (nhw > 0) {
-    uint32_t w;
-
-    w  = (uint32_t)*oqp->q_rdptr++;
-    if (oqp->q_rdptr >= oqp->q_top)
-      oqp->q_rdptr = oqp->q_buffer;
-    w |= (uint32_t)*oqp->q_rdptr++ << 8;
-    if (oqp->q_rdptr >= oqp->q_top)
-      oqp->q_rdptr = oqp->q_buffer;
-    *pmap++ = w;
-    nhw--;
-  }
-
-  /* Last byte for odd numbers.*/
-  if ((n & 1) != 0) {
-    *pmap = (uint32_t)*oqp->q_rdptr++;
-    if (oqp->q_rdptr >= oqp->q_top)
-      oqp->q_rdptr = oqp->q_buffer;
-  }
-
-  /* Updating queue. Note, the lock is done in this unusual way because this
-     function can be called from both ISR and thread context so the kind
-     of lock function to be invoked cannot be decided beforehand.*/
-  port_lock();
-  dbg_enter_lock();
-
-  oqp->q_counter += n;
-  while (notempty(&oqp->q_waiting))
-    chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
-
-  dbg_leave_lock();
-  port_unlock();
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_USB_USE_USB1 || defined(__DOXYGEN__)
-#if !defined(STM32_USB1_HP_HANDLER)
-#error "STM32_USB1_HP_HANDLER not defined"
-#endif
-/**
- * @brief   USB high priority interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USB1_HP_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(STM32_USB1_LP_HANDLER)
-#error "STM32_USB1_LP_HANDLER not defined"
-#endif
-/**
- * @brief   USB low priority interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_USB1_LP_HANDLER) {
-  uint32_t istr;
-  USBDriver *usbp = &USBD1;
-
-  CH_IRQ_PROLOGUE();
-
-  istr = STM32_USB->ISTR;
-
-  /* USB bus reset condition handling.*/
-  if (istr & ISTR_RESET) {
-    _usb_reset(usbp);
-    _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
-    STM32_USB->ISTR = ~ISTR_RESET;
-  }
-
-  /* USB bus SUSPEND condition handling.*/
-  if (istr & ISTR_SUSP) {
-    STM32_USB->CNTR |= CNTR_FSUSP;
-    _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND);
-#if STM32_USB_LOW_POWER_ON_SUSPEND
-    STM32_USB->CNTR |= CNTR_LP_MODE;
-#endif
-    STM32_USB->ISTR = ~ISTR_SUSP;
-  }
-
-  /* USB bus WAKEUP condition handling.*/
-  if (istr & ISTR_WKUP) {
-    uint32_t fnr = STM32_USB->FNR;
-    if (!(fnr & FNR_RXDP)) {
-      STM32_USB->CNTR &= ~CNTR_FSUSP;
-      _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP);
-    }
-#if STM32_USB_LOW_POWER_ON_SUSPEND
-    else {
-      /* Just noise, going back in SUSPEND mode, reference manual 22.4.5,
-         table 169.*/
-      STM32_USB->CNTR |= CNTR_LP_MODE;
-    }
-#endif
-    STM32_USB->ISTR = ~ISTR_WKUP;
-  }
-
-  /* SOF handling.*/
-  if (istr & ISTR_SOF) {
-    _usb_isr_invoke_sof_cb(usbp);
-    STM32_USB->ISTR = ~ISTR_SOF;
-  }
-
-  /* Endpoint events handling.*/
-  while (istr & ISTR_CTR) {
-    size_t n;
-    uint32_t ep;
-    uint32_t epr = STM32_USB->EPR[ep = istr & ISTR_EP_ID_MASK];
-    const USBEndpointConfig *epcp = usbp->epc[ep];
-
-    if (epr & EPR_CTR_TX) {
-      size_t transmitted;
-      /* IN endpoint, transmission.*/
-      EPR_CLEAR_CTR_TX(ep);
-
-      transmitted = (size_t)USB_GET_DESCRIPTOR(ep)->TXCOUNT0;
-      epcp->in_state->txcnt  += transmitted;
-      n = epcp->in_state->txsize - epcp->in_state->txcnt;
-      if (n > 0) {
-        /* Transfer not completed, there are more packets to send.*/
-        if (n > epcp->in_maxsize)
-          n = epcp->in_maxsize;
-
-        if (epcp->in_state->txqueued)
-          usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep),
-                                      epcp->in_state->mode.queue.txqueue,
-                                      n);
-        else {
-          epcp->in_state->mode.linear.txbuf += transmitted;
-          usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep),
-                                       epcp->in_state->mode.linear.txbuf,
-                                       n);
-        }
-        chSysLockFromIsr();
-        usb_lld_start_in(usbp, ep);
-        chSysUnlockFromIsr();
-      }
-      else {
-        /* Transfer completed, invokes the callback.*/
-        _usb_isr_invoke_in_cb(usbp, ep);
-      }
-    }
-    if (epr & EPR_CTR_RX) {
-      EPR_CLEAR_CTR_RX(ep);
-      /* OUT endpoint, receive.*/
-      if (epr & EPR_SETUP) {
-        /* Setup packets handling, setup packets are handled using a
-           specific callback.*/
-        _usb_isr_invoke_setup_cb(usbp, ep);
-      }
-      else {
-        stm32_usb_descriptor_t *udp = USB_GET_DESCRIPTOR(ep);
-        n = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK;
-
-        /* Reads the packet into the defined buffer.*/
-        if (epcp->out_state->rxqueued)
-          usb_packet_read_to_queue(udp,
-                                   epcp->out_state->mode.queue.rxqueue,
-                                   n);
-        else {
-          usb_packet_read_to_buffer(udp,
-                                    epcp->out_state->mode.linear.rxbuf,
-                                    n);
-          epcp->out_state->mode.linear.rxbuf += n;
-        }
-        /* Transaction data updated.*/
-        epcp->out_state->rxcnt              += n;
-        epcp->out_state->rxsize             -= n;
-        epcp->out_state->rxpkts             -= 1;
-
-        /* The transaction is completed if the specified number of packets
-           has been received or the current packet is a short packet.*/
-        if ((n < epcp->out_maxsize) || (epcp->out_state->rxpkts == 0)) {
-          /* Transfer complete, invokes the callback.*/
-          _usb_isr_invoke_out_cb(usbp, ep);
-        }
-        else {
-          /* Transfer not complete, there are more packets to receive.*/
-          EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID);
-        }
-      }
-    }
-    istr = STM32_USB->ISTR;
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level USB driver initialization.
- *
- * @notapi
- */
-void usb_lld_init(void) {
-
-  /* Driver initialization.*/
-  usbObjectInit(&USBD1);
-}
-
-/**
- * @brief   Configures and activates the USB peripheral.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_start(USBDriver *usbp) {
-
-  if (usbp->state == USB_STOP) {
-    /* Clock activation.*/
-#if STM32_USB_USE_USB1
-    if (&USBD1 == usbp) {
-      /* USB clock enabled.*/
-      rccEnableUSB(FALSE);
-      /* Powers up the transceiver while holding the USB in reset state.*/
-      STM32_USB->CNTR = CNTR_FRES;
-      /* Enabling the USB IRQ vectors, this also gives enough time to allow
-         the transceiver power up (1uS).*/
-      nvicEnableVector(STM32_USB1_HP_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_USB_USB1_HP_IRQ_PRIORITY));
-      nvicEnableVector(STM32_USB1_LP_NUMBER,
-                       CORTEX_PRIORITY_MASK(STM32_USB_USB1_LP_IRQ_PRIORITY));
-      /* Releases the USB reset.*/
-      STM32_USB->CNTR = 0;
-    }
-#endif
-    /* Reset procedure enforced on driver start.*/
-    _usb_reset(usbp);
-  }
-  /* Configuration.*/
-}
-
-/**
- * @brief   Deactivates the USB peripheral.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_stop(USBDriver *usbp) {
-
-  /* If in ready state then disables the USB clock.*/
-  if (usbp->state == USB_STOP) {
-#if STM32_USB_USE_USB1
-    if (&USBD1 == usbp) {
-      nvicDisableVector(STM32_USB1_HP_NUMBER);
-      nvicDisableVector(STM32_USB1_LP_NUMBER);
-      STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES;
-      rccDisableUSB(FALSE);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   USB low level reset routine.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_reset(USBDriver *usbp) {
-  uint32_t cntr;
-
-  /* Post reset initialization.*/
-  STM32_USB->BTABLE = 0;
-  STM32_USB->ISTR   = 0;
-  STM32_USB->DADDR  = DADDR_EF;
-  cntr              = /*CNTR_ESOFM | */ CNTR_RESETM  | CNTR_SUSPM |
-                      CNTR_WKUPM | /*CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM;
-  /* The SOF interrupt is only enabled if a callback is defined for
-     this service because it is an high rate source.*/
-  if (usbp->config->sof_cb != NULL)
-    cntr |= CNTR_SOFM;
-  STM32_USB->CNTR = cntr;
-
-  /* Resets the packet memory allocator.*/
-  usb_pm_reset(usbp);
-
-  /* EP0 initialization.*/
-  usbp->epc[0] = &ep0config;
-  usb_lld_init_endpoint(usbp, 0);
-}
-
-/**
- * @brief   Sets the USB address.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_set_address(USBDriver *usbp) {
-
-  STM32_USB->DADDR = (uint32_t)(usbp->address) | DADDR_EF;
-}
-
-/**
- * @brief   Enables an endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
-  uint16_t nblocks, epr;
-  stm32_usb_descriptor_t *dp;
-  const USBEndpointConfig *epcp = usbp->epc[ep];
-
-  /* Setting the endpoint type.*/
-  switch (epcp->ep_mode & USB_EP_MODE_TYPE) {
-  case USB_EP_MODE_TYPE_ISOC:
-    epr = EPR_EP_TYPE_ISO;
-    break;
-  case USB_EP_MODE_TYPE_BULK:
-    epr = EPR_EP_TYPE_BULK;
-    break;
-  case USB_EP_MODE_TYPE_INTR:
-    epr = EPR_EP_TYPE_INTERRUPT;
-    break;
-  default:
-    epr = EPR_EP_TYPE_CONTROL;
-  }
-
-  /* IN endpoint initially in NAK mode.*/
-  if (epcp->in_cb != NULL)
-    epr |= EPR_STAT_TX_NAK;
-
-  /* OUT endpoint initially in NAK mode.*/
-  if (epcp->out_cb != NULL)
-    epr |= EPR_STAT_RX_NAK;
-
-  /* EPxR register setup.*/
-  EPR_SET(ep, epr | ep);
-  EPR_TOGGLE(ep, epr);
-
-  /* Endpoint size and address initialization.*/
-  if (epcp->out_maxsize > 62)
-    nblocks = (((((epcp->out_maxsize - 1) | 0x1f) + 1) / 32) << 10) |
-              0x8000;
-  else
-    nblocks = ((((epcp->out_maxsize - 1) | 1) + 1) / 2) << 10;
-  dp = USB_GET_DESCRIPTOR(ep);
-  dp->TXCOUNT0 = 0;
-  dp->RXCOUNT0 = nblocks;
-  dp->TXADDR0  = usb_pm_alloc(usbp, epcp->in_maxsize);
-  dp->RXADDR0  = usb_pm_alloc(usbp, epcp->out_maxsize);
-}
-
-/**
- * @brief   Disables all the active endpoints except the endpoint zero.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_disable_endpoints(USBDriver *usbp) {
-  unsigned i;
-
-  /* Resets the packet memory allocator.*/
-  usb_pm_reset(usbp);
-
-  /* Disabling all endpoints.*/
-  for (i = 1; i <= USB_ENDOPOINTS_NUMBER; i++) {
-    EPR_TOGGLE(i, 0);
-    EPR_SET(i, 0);
-  }
-}
-
-/**
- * @brief   Returns the status of an OUT endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED  The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE   The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  switch (STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) {
-  case EPR_STAT_RX_DIS:
-    return EP_STATUS_DISABLED;
-  case EPR_STAT_RX_STALL:
-    return EP_STATUS_STALLED;
-  default:
-    return EP_STATUS_ACTIVE;
-  }
-}
-
-/**
- * @brief   Returns the status of an IN endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED  The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE   The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  switch (STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) {
-  case EPR_STAT_TX_DIS:
-    return EP_STATUS_DISABLED;
-  case EPR_STAT_TX_STALL:
-    return EP_STATUS_STALLED;
-  default:
-    return EP_STATUS_ACTIVE;
-  }
-}
-
-/**
- * @brief   Reads a setup packet from the dedicated packet buffer.
- * @details This function must be invoked in the context of the @p setup_cb
- *          callback in order to read the received setup packet.
- * @pre     In order to use this function the endpoint must have been
- *          initialized as a control endpoint.
- * @post    The endpoint is ready to accept another packet.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @param[out] buf      buffer where to copy the packet data
- *
- * @notapi
- */
-void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
-  uint32_t *pmap;
-  stm32_usb_descriptor_t *udp;
-  uint32_t n;
-
-  (void)usbp;
-  udp = USB_GET_DESCRIPTOR(ep);
-  pmap = USB_ADDR2PTR(udp->RXADDR0);
-  for (n = 0; n < 4; n++) {
-    *(uint16_t *)buf = (uint16_t)*pmap++;
-    buf += 2;
-  }
-}
-
-/**
- * @brief   Prepares for a receive operation.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
-  USBOutEndpointState *osp = usbp->epc[ep]->out_state;
-
-  /* Transfer initialization.*/
-  if (osp->rxsize == 0)         /* Special case for zero sized packets.*/
-    osp->rxpkts = 1;
-  else
-    osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
-                             usbp->epc[ep]->out_maxsize);
-}
-
-/**
- * @brief   Prepares for a transmit operation.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
-  size_t n;
-  USBInEndpointState *isp = usbp->epc[ep]->in_state;
-
-  /* Transfer initialization.*/
-  n = isp->txsize;
-  if (n > (size_t)usbp->epc[ep]->in_maxsize)
-    n = (size_t)usbp->epc[ep]->in_maxsize;
-
-  if (isp->txqueued)
-    usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep),
-                                isp->mode.queue.txqueue, n);
-  else
-    usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep),
-                                 isp->mode.linear.txbuf, n);
-}
-
-/**
- * @brief   Starts a receive operation on an OUT endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-
-  EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID);
-}
-
-/**
- * @brief   Starts a transmit operation on an IN endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-
-  EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID);
-}
-
-/**
- * @brief   Brings an OUT endpoint in the stalled state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-
-  EPR_SET_STAT_RX(ep, EPR_STAT_RX_STALL);
-}
-
-/**
- * @brief   Brings an IN endpoint in the stalled state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-
-  EPR_SET_STAT_TX(ep, EPR_STAT_TX_STALL);
-}
-
-/**
- * @brief   Brings an OUT endpoint in the active state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-
-  /* Makes sure to not put to NAK an endpoint that is already
-     transferring.*/
-  if ((STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) != EPR_STAT_RX_VALID)
-    EPR_SET_STAT_TX(ep, EPR_STAT_RX_NAK);
-}
-
-/**
- * @brief   Brings an IN endpoint in the active state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-
-  /* Makes sure to not put to NAK an endpoint that is already
-     transferring.*/
-  if ((STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) != EPR_STAT_TX_VALID)
-    EPR_SET_STAT_TX(ep, EPR_STAT_TX_NAK);
-}
-
-#endif /* HAL_USE_USB */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.h b/os/hal/platforms/STM32/USBv1/usb_lld.h
deleted file mode 100644
index 74618900f..000000000
--- a/os/hal/platforms/STM32/USBv1/usb_lld.h
+++ /dev/null
@@ -1,442 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/USBv1/usb_lld.h
- * @brief   STM32 USB subsystem low level driver header.
- *
- * @addtogroup USB
- * @{
- */
-
-#ifndef _USB_LLD_H_
-#define _USB_LLD_H_
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-#include "stm32_usb.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Maximum endpoint address.
- */
-#define USB_MAX_ENDPOINTS                   USB_ENDOPOINTS_NUMBER
-
-/**
- * @brief   Status stage handling method.
- */
-#define USB_EP0_STATUS_STAGE                USB_EP0_STATUS_STAGE_SW
-
-/**
- * @brief   This device requires the address change after the status packet.
- */
-#define USB_SET_ADDRESS_MODE                USB_LATE_SET_ADDRESS
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   USB1 driver enable switch.
- * @details If set to @p TRUE the support for USB1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_USB_USE_USB1) || defined(__DOXYGEN__)
-#define STM32_USB_USE_USB1                  FALSE
-#endif
-
-/**
- * @brief   Enables the USB device low power mode on suspend.
- */
-#if !defined(STM32_USB_LOW_POWER_ON_SUSPEND) || defined(__DOXYGEN__)
-#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE
-#endif
-
-/**
- * @brief   USB1 interrupt priority level setting.
- */
-#if !defined(STM32_USB_USB1_HP_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USB_USB1_HP_IRQ_PRIORITY      13
-#endif
-
-/**
- * @brief   USB1 interrupt priority level setting.
- */
-#if !defined(STM32_USB_USB1_LP_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USB_USB1_LP_IRQ_PRIORITY      14
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_USB_USE_USB1 && !STM32_HAS_USB
-#error "USB not present in the selected device"
-#endif
-
-#if !STM32_USB_USE_USB1
-#error "USB driver activated but no USB peripheral assigned"
-#endif
-
-#if STM32_USB_USE_USB1 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_HP_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USB HP"
-#endif
-
-#if STM32_USB_USE_USB1 &&                                                \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_LP_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to USB LP"
-#endif
-
-#if STM32_USBCLK != 48000000
-#error "the USB driver requires a 48MHz clock"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of an IN endpoint state structure.
- */
-typedef struct {
-  /**
-   * @brief   Buffer mode, queue or linear.
-   */
-  bool_t                        txqueued;
-  /**
-   * @brief   Requested transmit transfer size.
-   */
-  size_t                        txsize;
-  /**
-   * @brief   Transmitted bytes so far.
-   */
-  size_t                        txcnt;
-  union {
-    struct {
-      /**
-       * @brief   Pointer to the transmission linear buffer.
-       */
-      const uint8_t             *txbuf;
-    } linear;
-    struct {
-      /**
-       * @brief   Pointer to the output queue.
-       */
-      OutputQueue               *txqueue;
-    } queue;
-    /* End of the mandatory fields.*/
-  } mode;
-} USBInEndpointState;
-
-/**
- * @brief   Type of an OUT endpoint state structure.
- */
-typedef struct {
-  /**
-   * @brief   Buffer mode, queue or linear.
-   */
-  bool_t                        rxqueued;
-  /**
-   * @brief   Requested receive transfer size.
-   */
-  size_t                        rxsize;
-  /**
-   * @brief   Received bytes so far.
-   */
-  size_t                        rxcnt;
-  union {
-    struct {
-      /**
-       * @brief   Pointer to the receive linear buffer.
-       */
-      uint8_t                   *rxbuf;
-    } linear;
-    struct {
-      /**
-       * @brief   Pointer to the input queue.
-       */
-      InputQueue               *rxqueue;
-    } queue;
-  } mode;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Number of packets to receive.
-   */
-  uint16_t                      rxpkts;
-} USBOutEndpointState;
-
-/**
- * @brief   Type of an USB endpoint configuration structure.
- * @note    Platform specific restrictions may apply to endpoints.
- */
-typedef struct {
-  /**
-   * @brief   Type and mode of the endpoint.
-   */
-  uint32_t                      ep_mode;
-  /**
-   * @brief   Setup packet notification callback.
-   * @details This callback is invoked when a setup packet has been
-   *          received.
-   * @post    The application must immediately call @p usbReadPacket() in
-   *          order to access the received packet.
-   * @note    This field is only valid for @p USB_EP_MODE_TYPE_CTRL
-   *          endpoints, it should be set to @p NULL for other endpoint
-   *          types.
-   */
-  usbepcallback_t               setup_cb;
-  /**
-   * @brief   IN endpoint notification callback.
-   * @details This field must be set to @p NULL if the IN endpoint is not
-   *          used.
-   */
-  usbepcallback_t               in_cb;
-  /**
-   * @brief   OUT endpoint notification callback.
-   * @details This field must be set to @p NULL if the OUT endpoint is not
-   *          used.
-   */
-  usbepcallback_t               out_cb;
-  /**
-   * @brief   IN endpoint maximum packet size.
-   * @details This field must be set to zero if the IN endpoint is not
-   *          used.
-   */
-  uint16_t                      in_maxsize;
-  /**
-   * @brief   OUT endpoint maximum packet size.
-   * @details This field must be set to zero if the OUT endpoint is not
-   *          used.
-   */
-  uint16_t                      out_maxsize;
-  /**
-   * @brief   @p USBEndpointState associated to the IN endpoint.
-   * @details This structure maintains the state of the IN endpoint.
-   */
-  USBInEndpointState            *in_state;
-  /**
-   * @brief   @p USBEndpointState associated to the OUT endpoint.
-   * @details This structure maintains the state of the OUT endpoint.
-   */
-  USBOutEndpointState           *out_state;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Reserved field, not currently used.
-   * @note    Initialize this field to 1 in order to be forward compatible.
-   */
-  uint16_t                      ep_buffers;
-  /**
-   * @brief   Pointer to a buffer for setup packets.
-   * @details Setup packets require a dedicated 8-bytes buffer, set this
-   *          field to @p NULL for non-control endpoints.
-   */
-  uint8_t                       *setup_buf;
-} USBEndpointConfig;
-
-/**
- * @brief   Type of an USB driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   USB events callback.
-   * @details This callback is invoked when an USB driver event is registered.
-   */
-  usbeventcb_t                  event_cb;
-  /**
-   * @brief   Device GET_DESCRIPTOR request callback.
-   * @note    This callback is mandatory and cannot be set to @p NULL.
-   */
-  usbgetdescriptor_t            get_descriptor_cb;
-  /**
-   * @brief   Requests hook callback.
-   * @details This hook allows to be notified of standard requests or to
-   *          handle non standard requests.
-   */
-  usbreqhandler_t               requests_hook_cb;
-  /**
-   * @brief   Start Of Frame callback.
-   */
-  usbcallback_t                 sof_cb;
-  /* End of the mandatory fields.*/
-} USBConfig;
-
-/**
- * @brief   Structure representing an USB driver.
- */
-struct USBDriver {
-  /**
-   * @brief   Driver state.
-   */
-  usbstate_t                    state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const USBConfig               *config;
-  /**
-   * @brief   Bit map of the transmitting IN endpoints.
-   */
-  uint16_t                      transmitting;
-  /**
-   * @brief   Bit map of the receiving OUT endpoints.
-   */
-  uint16_t                      receiving;
-  /**
-   * @brief   Active endpoints configurations.
-   */
-  const USBEndpointConfig       *epc[USB_MAX_ENDPOINTS + 1];
-  /**
-   * @brief   Fields available to user, it can be used to associate an
-   *          application-defined handler to an IN endpoint.
-   * @note    The base index is one, the endpoint zero does not have a
-   *          reserved element in this array.
-   */
-  void                          *in_params[USB_MAX_ENDPOINTS];
-  /**
-   * @brief   Fields available to user, it can be used to associate an
-   *          application-defined handler to an OUT endpoint.
-   * @note    The base index is one, the endpoint zero does not have a
-   *          reserved element in this array.
-   */
-  void                          *out_params[USB_MAX_ENDPOINTS];
-  /**
-   * @brief   Endpoint 0 state.
-   */
-  usbep0state_t                 ep0state;
-  /**
-   * @brief   Next position in the buffer to be transferred through endpoint 0.
-   */
-  uint8_t                       *ep0next;
-  /**
-   * @brief   Number of bytes yet to be transferred through endpoint 0.
-   */
-  size_t                        ep0n;
-  /**
-   * @brief   Endpoint 0 end transaction callback.
-   */
-  usbcallback_t                 ep0endcb;
-  /**
-   * @brief   Setup packet buffer.
-   */
-  uint8_t                       setup[8];
-  /**
-   * @brief   Current USB device status.
-   */
-  uint16_t                      status;
-  /**
-   * @brief   Assigned USB address.
-   */
-  uint8_t                       address;
-  /**
-   * @brief   Current USB device configuration.
-   */
-  uint8_t                       configuration;
-#if defined(USB_DRIVER_EXT_FIELDS)
-  USB_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Pointer to the next address in the packet memory.
-   */
-  uint32_t                      pmnext;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current frame number.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @return              The current frame number.
- *
- * @notapi
- */
-#define usb_lld_get_frame_number(usbp) (STM32_USB->FNR & FNR_FN_MASK)
-
-/**
- * @brief   Returns the exact size of a receive transaction.
- * @details The received size can be different from the size specified in
- *          @p usbStartReceiveI() because the last packet could have a size
- *          different from the expected one.
- * @pre     The OUT endpoint must have been configured in transaction mode
- *          in order to use this function.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              Received data size.
- *
- * @notapi
- */
-#define usb_lld_get_transaction_size(usbp, ep)                              \
-  ((usbp)->epc[ep]->out_state->rxcnt)
-
-/**
- * @brief   Returns the exact size of a received packet.
- * @pre     The OUT endpoint must have been configured in packet mode
- *          in order to use this function.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              Received data size.
- *
- * @notapi
- */
-#define  usb_lld_get_packet_size(usbp, ep)                                  \
-  ((size_t)USB_GET_DESCRIPTOR(ep)->RXCOUNT & RXCOUNT_COUNT_MASK)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_USB_USE_USB1 && !defined(__DOXYGEN__)
-extern USBDriver USBD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void usb_lld_init(void);
-  void usb_lld_start(USBDriver *usbp);
-  void usb_lld_stop(USBDriver *usbp);
-  void usb_lld_reset(USBDriver *usbp);
-  void usb_lld_set_address(USBDriver *usbp);
-  void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
-  void usb_lld_disable_endpoints(USBDriver *usbp);
-  usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
-  usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
-  void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
-  void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
-  void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
-  void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
-  void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_USB */
-
-#endif /* _USB_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/can_lld.c b/os/hal/platforms/STM32/can_lld.c
deleted file mode 100644
index 716b16e84..000000000
--- a/os/hal/platforms/STM32/can_lld.c
+++ /dev/null
@@ -1,718 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/can_lld.c
- * @brief   STM32 CAN subsystem low level driver source.
- *
- * @addtogroup CAN
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief CAN1 driver identifier.*/
-#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)
-CANDriver CAND1;
-#endif
-
-/** @brief CAN2 driver identifier.*/
-#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)
-CANDriver CAND2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Programs the filters.
- *
- * @param[in] can2sb    number of the first filter assigned to CAN2
- * @param[in] num       number of entries in the filters array, if zero then
- *                      a default filter is programmed
- * @param[in] cfp       pointer to the filters array, can be @p NULL if
- *                      (num == 0)
- *
- * @notapi
- */
-static void can_lld_set_filters(uint32_t can2sb,
-                                uint32_t num,
-                                const CANFilter *cfp) {
-
-  /* Temporarily enabling CAN1 clock.*/
-  rccEnableCAN1(FALSE);
-
-  /* Filters initialization.*/
-  CAN1->FMR = (CAN1->FMR & 0xFFFF0000) | (can2sb << 8) | CAN_FMR_FINIT;
-  if (num > 0) {
-    uint32_t i, fmask;
-
-    /* All filters cleared.*/
-    CAN1->FA1R = 0;
-    CAN1->FM1R = 0;
-    CAN1->FS1R = 0;
-    CAN1->FFA1R = 0;
-    for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) {
-      CAN1->sFilterRegister[i].FR1 = 0;
-      CAN1->sFilterRegister[i].FR2 = 0;
-    }
-
-    /* Scanning the filters array.*/
-    for (i = 0; i < num; i++) {
-      fmask = 1 << cfp->filter;
-      if (cfp->mode)
-        CAN1->FM1R |= fmask;
-      if (cfp->scale)
-        CAN1->FS1R |= fmask;
-      if (cfp->assignment)
-        CAN1->FFA1R |= fmask;
-      CAN1->sFilterRegister[cfp->filter].FR1 = cfp->register1;
-      CAN1->sFilterRegister[cfp->filter].FR2 = cfp->register2;
-      CAN1->FA1R |= fmask;
-      cfp++;
-    }
-  }
-  else {
-    /* Setting up a single default filter that enables everything for both
-       CANs.*/
-    CAN1->sFilterRegister[0].FR1 = 0;
-    CAN1->sFilterRegister[0].FR2 = 0;
-    CAN1->sFilterRegister[can2sb].FR1 = 0;
-    CAN1->sFilterRegister[can2sb].FR2 = 0;
-    CAN1->FM1R = 0;
-    CAN1->FFA1R = 0;
-    CAN1->FS1R = 1 | (1 << can2sb);
-    CAN1->FA1R = 1 | (1 << can2sb);
-  }
-  CAN1->FMR &= ~CAN_FMR_FINIT;
-
-  /* Clock disabled, it will be enabled again in can_lld_start().*/
-  rccDisableCAN1(FALSE);
-}
-
-/**
- * @brief   Common TX ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_tx_handler(CANDriver *canp) {
-
-  /* No more events until a message is transmitted.*/
-  canp->can->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2;
-  chSysLockFromIsr();
-  while (chSemGetCounterI(&canp->txsem) < 0)
-    chSemSignalI(&canp->txsem);
-  chEvtBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1));
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common RX0 ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_rx0_handler(CANDriver *canp) {
-  uint32_t rf0r;
-
-  rf0r = canp->can->RF0R;
-  if ((rf0r & CAN_RF0R_FMP0) > 0) {
-    /* No more receive events until the queue 0 has been emptied.*/
-    canp->can->IER &= ~CAN_IER_FMPIE0;
-    chSysLockFromIsr();
-    while (chSemGetCounterI(&canp->rxsem) < 0)
-      chSemSignalI(&canp->rxsem);
-    chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1));
-    chSysUnlockFromIsr();
-  }
-  if ((rf0r & CAN_RF0R_FOVR0) > 0) {
-    /* Overflow events handling.*/
-    canp->can->RF0R = CAN_RF0R_FOVR0;
-    chSysLockFromIsr();
-    chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
-    chSysUnlockFromIsr();
-  }
-}
-
-/**
- * @brief   Common RX1 ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_rx1_handler(CANDriver *canp) {
-  uint32_t rf1r;
-
-  rf1r = canp->can->RF1R;
-  if ((rf1r & CAN_RF1R_FMP1) > 0) {
-    /* No more receive events until the queue 0 has been emptied.*/
-    canp->can->IER &= ~CAN_IER_FMPIE1;
-    chSysLockFromIsr();
-    while (chSemGetCounterI(&canp->rxsem) < 0)
-      chSemSignalI(&canp->rxsem);
-    chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2));
-    chSysUnlockFromIsr();
-  }
-  if ((rf1r & CAN_RF1R_FOVR1) > 0) {
-    /* Overflow events handling.*/
-    canp->can->RF1R = CAN_RF1R_FOVR1;
-    chSysLockFromIsr();
-    chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
-    chSysUnlockFromIsr();
-  }
-}
-
-/**
- * @brief   Common SCE ISR handler.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-static void can_lld_sce_handler(CANDriver *canp) {
-  uint32_t msr;
-
-  msr = canp->can->MSR;
-  canp->can->MSR = CAN_MSR_ERRI | CAN_MSR_WKUI | CAN_MSR_SLAKI;
-  /* Wakeup event.*/
-#if CAN_USE_SLEEP_MODE
-  if (msr & CAN_MSR_WKUI) {
-    canp->state = CAN_READY;
-    canp->can->MCR &= ~CAN_MCR_SLEEP;
-    chSysLockFromIsr();
-    chEvtBroadcastI(&canp->wakeup_event);
-    chSysUnlockFromIsr();
-  }
-#endif /* CAN_USE_SLEEP_MODE */
-  /* Error event.*/
-  if (msr & CAN_MSR_ERRI) {
-    flagsmask_t flags;
-    uint32_t esr = canp->can->ESR;
-
-    canp->can->ESR &= ~CAN_ESR_LEC;
-    flags = (flagsmask_t)(esr & 7);
-    if ((esr & CAN_ESR_LEC) > 0)
-      flags |= CAN_FRAMING_ERROR;
-
-    chSysLockFromIsr();
-    /* The content of the ESR register is copied unchanged in the upper
-       half word of the listener flags mask.*/
-    chEvtBroadcastFlagsI(&canp->error_event, flags | (flagsmask_t)(esr << 16));
-    chSysUnlockFromIsr();
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)
-/**
- * @brief   CAN1 TX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief   CAN1 RX0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx0_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 RX1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx1_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN1 SCE interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_sce_handler(&CAND1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_CAN_USE_CAN1 */
-
-#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)
-/**
- * @brief   CAN2 TX interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_tx_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*
- * @brief   CAN2 RX0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx0_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 RX1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_rx1_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   CAN2 SCE interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  can_lld_sce_handler(&CAND2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_CAN_USE_CAN2 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level CAN driver initialization.
- *
- * @notapi
- */
-void can_lld_init(void) {
-
-#if STM32_CAN_USE_CAN1
-  /* Driver initialization.*/
-  canObjectInit(&CAND1);
-  CAND1.can = CAN1;
-#endif
-#if STM32_CAN_USE_CAN2
-  /* Driver initialization.*/
-  canObjectInit(&CAND2);
-  CAND2.can = CAN2;
-#endif
-
-  /* Filters initialization.*/
-#if STM32_HAS_CAN2
-  can_lld_set_filters(STM32_CAN_MAX_FILTERS / 2, 0, NULL);
-#else
-  can_lld_set_filters(STM32_CAN_MAX_FILTERS, 0, NULL);
-#endif
-}
-
-/**
- * @brief   Configures and activates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_start(CANDriver *canp) {
-
-  /* Clock activation.*/
-#if STM32_CAN_USE_CAN1
-  if (&CAND1 == canp) {
-    nvicEnableVector(STM32_CAN1_TX_NUMBER,
-                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
-    nvicEnableVector(STM32_CAN1_RX0_NUMBER,
-                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
-    nvicEnableVector(STM32_CAN1_RX1_NUMBER,
-                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
-    nvicEnableVector(STM32_CAN1_SCE_NUMBER,
-                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
-    rccEnableCAN1(FALSE);
-  }
-#endif
-#if STM32_CAN_USE_CAN2
-  if (&CAND2 == canp) {
-
-    chDbgAssert(CAND1.state != CAN_STOP,
-                "can_lld_start(), #1", "CAN1 must be started");
-
-    nvicEnableVector(STM32_CAN2_TX_NUMBER,
-                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
-    nvicEnableVector(STM32_CAN2_RX0_NUMBER,
-                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
-    nvicEnableVector(STM32_CAN2_RX1_NUMBER,
-                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
-    nvicEnableVector(STM32_CAN2_SCE_NUMBER,
-                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));
-    rccEnableCAN2(FALSE);
-  }
-#endif
-
-  /* Entering initialization mode. */
-  canp->state = CAN_STARTING;
-  canp->can->MCR = CAN_MCR_INRQ;
-  while ((canp->can->MSR & CAN_MSR_INAK) == 0)
-    chThdSleepS(1);
-  /* BTR initialization.*/
-  canp->can->BTR = canp->config->btr;
-  /* MCR initialization.*/
-  canp->can->MCR = canp->config->mcr;
-
-  /* Interrupt sources initialization.*/
-  canp->can->IER = CAN_IER_TMEIE  | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 |
-                   CAN_IER_WKUIE  | CAN_IER_ERRIE  | CAN_IER_LECIE  |
-                   CAN_IER_BOFIE  | CAN_IER_EPVIE  | CAN_IER_EWGIE  |
-                   CAN_IER_FOVIE0 | CAN_IER_FOVIE1;
-}
-
-/**
- * @brief   Deactivates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_stop(CANDriver *canp) {
-
-  /* If in ready state then disables the CAN peripheral.*/
-  if (canp->state == CAN_READY) {
-#if STM32_CAN_USE_CAN1
-    if (&CAND1 == canp) {
-
-#if STM32_CAN_USE_CAN2
-      chDbgAssert(CAND2.state == CAN_STOP,
-                  "can_lld_stop(), #1", "CAN2 must be stopped");
-#endif
-
-      CAN1->MCR = 0x00010002;                   /* Register reset value.    */
-      CAN1->IER = 0x00000000;                   /* All sources disabled.    */
-      nvicDisableVector(STM32_CAN1_TX_NUMBER);
-      nvicDisableVector(STM32_CAN1_RX0_NUMBER);
-      nvicDisableVector(STM32_CAN1_RX1_NUMBER);
-      nvicDisableVector(STM32_CAN1_SCE_NUMBER);
-      rccDisableCAN1(FALSE);
-    }
-#endif
-#if STM32_CAN_USE_CAN2
-    if (&CAND2 == canp) {
-      CAN2->MCR = 0x00010002;                   /* Register reset value.    */
-      CAN2->IER = 0x00000000;                   /* All sources disabled.    */
-      nvicDisableVector(STM32_CAN2_TX_NUMBER);
-      nvicDisableVector(STM32_CAN2_RX0_NUMBER);
-      nvicDisableVector(STM32_CAN2_RX1_NUMBER);
-      nvicDisableVector(STM32_CAN2_SCE_NUMBER);
-      rccDisableCAN2(FALSE);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Determines whether a frame can be transmitted.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return              The queue space availability.
- * @retval FALSE        no space in the transmit queue.
- * @retval TRUE         transmit slot available.
- *
- * @notapi
- */
-bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
-
-  switch (mailbox) {
-  case CAN_ANY_MAILBOX:
-    return (canp->can->TSR & CAN_TSR_TME) != 0;
-  case 1:
-    return (canp->can->TSR & CAN_TSR_TME0) != 0;
-  case 2:
-    return (canp->can->TSR & CAN_TSR_TME1) != 0;
-  case 3:
-    return (canp->can->TSR & CAN_TSR_TME2) != 0;
-  default:
-    return FALSE;
-  }
-}
-
-/**
- * @brief   Inserts a frame into the transmit queue.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] ctfp      pointer to the CAN frame to be transmitted
- * @param[in] mailbox   mailbox number,  @p CAN_ANY_MAILBOX for any mailbox
- *
- * @notapi
- */
-void can_lld_transmit(CANDriver *canp,
-                      canmbx_t mailbox,
-                      const CANTxFrame *ctfp) {
-  uint32_t tir;
-  CAN_TxMailBox_TypeDef *tmbp;
-
-  /* Pointer to a free transmission mailbox.*/
-  switch (mailbox) {
-  case CAN_ANY_MAILBOX:
-    tmbp = &canp->can->sTxMailBox[(canp->can->TSR & CAN_TSR_CODE) >> 24];
-    break;
-  case 1:
-    tmbp = &canp->can->sTxMailBox[0];
-    break;
-  case 2:
-    tmbp = &canp->can->sTxMailBox[1];
-    break;
-  case 3:
-    tmbp = &canp->can->sTxMailBox[2];
-    break;
-  default:
-    return;
-  }
-
-  /* Preparing the message.*/
-  if (ctfp->IDE)
-    tir = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) |
-          CAN_TI0R_IDE;
-  else
-    tir = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1);
-  tmbp->TDTR = ctfp->DLC;
-  tmbp->TDLR = ctfp->data32[0];
-  tmbp->TDHR = ctfp->data32[1];
-  tmbp->TIR  = tir | CAN_TI0R_TXRQ;
-}
-
-/**
- * @brief   Determines whether a frame has been received.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return              The queue space availability.
- * @retval FALSE        no space in the transmit queue.
- * @retval TRUE         transmit slot available.
- *
- * @notapi
- */
-bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
-
-  switch (mailbox) {
-  case CAN_ANY_MAILBOX:
-    return ((canp->can->RF0R & CAN_RF0R_FMP0) != 0 ||
-            (canp->can->RF1R & CAN_RF1R_FMP1) != 0);
-  case 1:
-    return (canp->can->RF0R & CAN_RF0R_FMP0) != 0;
-  case 2:
-    return (canp->can->RF1R & CAN_RF1R_FMP1) != 0;
-  default:
-    return FALSE;
-  }
-}
-
-/**
- * @brief   Receives a frame from the input queue.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @param[out] crfp     pointer to the buffer where the CAN frame is copied
- *
- * @notapi
- */
-void can_lld_receive(CANDriver *canp,
-                     canmbx_t mailbox,
-                     CANRxFrame *crfp) {
-  uint32_t rir, rdtr;
-
-  if (mailbox == CAN_ANY_MAILBOX) {
-    if ((canp->can->RF0R & CAN_RF0R_FMP0) != 0)
-      mailbox = 1;
-    else if ((canp->can->RF1R & CAN_RF1R_FMP1) != 0)
-      mailbox = 2;
-    else {
-      /* Should not happen, do nothing.*/
-      return;
-    }
-  }
-  switch (mailbox) {
-  case 1:
-    /* Fetches the message.*/
-    rir  = canp->can->sFIFOMailBox[0].RIR;
-    rdtr = canp->can->sFIFOMailBox[0].RDTR;
-    crfp->data32[0] = canp->can->sFIFOMailBox[0].RDLR;
-    crfp->data32[1] = canp->can->sFIFOMailBox[0].RDHR;
-
-    /* Releases the mailbox.*/
-    canp->can->RF0R = CAN_RF0R_RFOM0;
-
-    /* If the queue is empty re-enables the interrupt in order to generate
-       events again.*/
-    if ((canp->can->RF0R & CAN_RF0R_FMP0) == 0)
-      canp->can->IER |= CAN_IER_FMPIE0;
-    break;
-  case 2:
-    /* Fetches the message.*/
-    rir  = canp->can->sFIFOMailBox[1].RIR;
-    rdtr = canp->can->sFIFOMailBox[1].RDTR;
-    crfp->data32[0] = canp->can->sFIFOMailBox[1].RDLR;
-    crfp->data32[1] = canp->can->sFIFOMailBox[1].RDHR;
-
-    /* Releases the mailbox.*/
-    canp->can->RF1R = CAN_RF1R_RFOM1;
-
-    /* If the queue is empty re-enables the interrupt in order to generate
-       events again.*/
-    if ((canp->can->RF1R & CAN_RF1R_FMP1) == 0)
-      canp->can->IER |= CAN_IER_FMPIE1;
-    break;
-  default:
-    /* Should not happen, do nothing.*/
-    return;
-  }
-
-  /* Decodes the various fields in the RX frame.*/
-  crfp->RTR = (rir & CAN_RI0R_RTR) >> 1;
-  crfp->IDE = (rir & CAN_RI0R_IDE) >> 2;
-  if (crfp->IDE)
-    crfp->EID = rir >> 3;
-  else
-    crfp->SID = rir >> 21;
-  crfp->DLC = rdtr & CAN_RDT0R_DLC;
-  crfp->FMI = (uint8_t)(rdtr >> 8);
-  crfp->TIME = (uint16_t)(rdtr >> 16);
-}
-
-#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
-/**
- * @brief   Enters the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_sleep(CANDriver *canp) {
-
-  canp->can->MCR |= CAN_MCR_SLEEP;
-}
-
-/**
- * @brief   Enforces leaving the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_wakeup(CANDriver *canp) {
-
-  canp->can->MCR &= ~CAN_MCR_SLEEP;
-}
-#endif /* CAN_USE_SLEEP_MODE */
-
-/**
- * @brief   Programs the filters.
- * @note    This is an STM32-specific API.
- *
- * @param[in] can2sb    number of the first filter assigned to CAN2
- * @param[in] num       number of entries in the filters array, if zero then
- *                      a default filter is programmed
- * @param[in] cfp       pointer to the filters array, can be @p NULL if
- *                      (num == 0)
- *
- * @api
- */
-void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp) {
-
-  chDbgCheck((can2sb > 1) && (can2sb < STM32_CAN_MAX_FILTERS) &&
-             (num < STM32_CAN_MAX_FILTERS),
-             "canSTM32SetFilters");
-
-#if STM32_CAN_USE_CAN1
-  chDbgAssert(CAND1.state == CAN_STOP,
-              "canSTM32SetFilters(), #1", "invalid state");
-#endif
-#if STM32_CAN_USE_CAN2
-  chDbgAssert(CAND2.state == CAN_STOP,
-              "canSTM32SetFilters(), #2", "invalid state");
-#endif
-
-  can_lld_set_filters(can2sb, num, cfp);
-}
-
-#endif /* HAL_USE_CAN */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h
deleted file mode 100644
index d4e8188bb..000000000
--- a/os/hal/platforms/STM32/can_lld.h
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/can_lld.h
- * @brief   STM32 CAN subsystem low level driver header.
- *
- * @addtogroup CAN
- * @{
- */
-
-#ifndef _CAN_LLD_H_
-#define _CAN_LLD_H_
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*
- * The following macros from the ST header file are replaced with better
- * equivalents.
- */
-#undef CAN_BTR_BRP
-#undef CAN_BTR_TS1
-#undef CAN_BTR_TS2
-#undef CAN_BTR_SJW
-
-/**
- * @brief   This switch defines whether the driver implementation supports
- *          a low power switch mode with automatic an wakeup feature.
- */
-#define CAN_SUPPORTS_SLEEP          TRUE
-
-/**
- * @brief   This implementation supports three transmit mailboxes.
- */
-#define CAN_TX_MAILBOXES            3
-
-/**
- * @brief   This implementation supports two receive mailboxes.
- */
-#define CAN_RX_MAILBOXES            2
-
-/**
- * @name    CAN registers helper macros
- * @{
- */
-#define CAN_BTR_BRP(n)              (n)         /**< @brief BRP field macro.*/
-#define CAN_BTR_TS1(n)              ((n) << 16) /**< @brief TS1 field macro.*/
-#define CAN_BTR_TS2(n)              ((n) << 20) /**< @brief TS2 field macro.*/
-#define CAN_BTR_SJW(n)              ((n) << 24) /**< @brief SJW field macro.*/
-
-#define CAN_IDE_STD                 0           /**< @brief Standard id.    */
-#define CAN_IDE_EXT                 1           /**< @brief Extended id.    */
-
-#define CAN_RTR_DATA                0           /**< @brief Data frame.     */
-#define CAN_RTR_REMOTE              1           /**< @brief Remote frame.   */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   CAN1 driver enable switch.
- * @details If set to @p TRUE the support for CAN1 is included.
- */
-#if !defined(STM32_CAN_USE_CAN1) || defined(__DOXYGEN__)
-#define STM32_CAN_USE_CAN1                  FALSE
-#endif
-
-/**
- * @brief   CAN2 driver enable switch.
- * @details If set to @p TRUE the support for CAN2 is included.
- */
-#if !defined(STM32_CAN_USE_CAN2) || defined(__DOXYGEN__)
-#define STM32_CAN_USE_CAN2                  FALSE
-#endif
-
-/**
- * @brief   CAN1 interrupt priority level setting.
- */
-#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_CAN_CAN1_IRQ_PRIORITY         11
-#endif
-/** @} */
-
-/**
- * @brief   CAN2 interrupt priority level setting.
- */
-#if !defined(STM32_CAN_CAN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_CAN_CAN2_IRQ_PRIORITY         11
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_CAN_USE_CAN1 && !STM32_HAS_CAN1
-#error "CAN1 not present in the selected device"
-#endif
-
-#if STM32_CAN_USE_CAN2 && !STM32_HAS_CAN2
-#error "CAN2 not present in the selected device"
-#endif
-
-#if !STM32_CAN_USE_CAN1 && !STM32_CAN_USE_CAN2
-#error "CAN driver activated but no CAN peripheral assigned"
-#endif
-
-#if !STM32_CAN_USE_CAN1 && STM32_CAN_USE_CAN2
-#error "CAN2 requires CAN1, it cannot operate independently"
-#endif
-
-#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
-#error "CAN sleep mode not supported in this architecture"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a transmission mailbox index.
- */
-typedef uint32_t canmbx_t;
-
-/**
- * @brief   CAN transmission frame.
- * @note    Accessing the frame data as word16 or word32 is not portable because
- *          machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
-  struct {
-    uint8_t                 DLC:4;          /**< @brief Data length.        */
-    uint8_t                 RTR:1;          /**< @brief Frame type.         */
-    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t              SID:11;         /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t              EID:29;         /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t                 data8[8];       /**< @brief Frame data.         */
-    uint16_t                data16[4];      /**< @brief Frame data.         */
-    uint32_t                data32[2];      /**< @brief Frame data.         */
-  };
-} CANTxFrame;
-
-/**
- * @brief   CAN received frame.
- * @note    Accessing the frame data as word16 or word32 is not portable because
- *          machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
-  struct {
-    uint8_t                 FMI;            /**< @brief Filter id.          */
-    uint16_t                TIME;           /**< @brief Time stamp.         */
-  };
-  struct {
-    uint8_t                 DLC:4;          /**< @brief Data length.        */
-    uint8_t                 RTR:1;          /**< @brief Frame type.         */
-    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t              SID:11;         /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t              EID:29;         /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t                 data8[8];       /**< @brief Frame data.         */
-    uint16_t                data16[4];      /**< @brief Frame data.         */
-    uint32_t                data32[2];      /**< @brief Frame data.         */
-  };
-} CANRxFrame;
-
-/**
- * @brief   CAN filter.
- * @note    Refer to the STM32 reference manual for info about filters.
- */
-typedef struct {
-  /**
-   * @brief   Number of the filter to be programmed.
-   */
-  uint32_t                  filter;
-  /**
-   * @brief   Filter mode.
-   * @note    This bit represent the CAN_FM1R register bit associated to this
-   *          filter (0=mask mode, 1=list mode).
-   */
-  uint32_t                  mode:1;
-  /**
-   * @brief   Filter scale.
-   * @note    This bit represent the CAN_FS1R register bit associated to this
-   *          filter (0=16 bits mode, 1=32 bits mode).
-   */
-  uint32_t                  scale:1;
-  /**
-   * @brief   Filter mode.
-   * @note    This bit represent the CAN_FFA1R register bit associated to this
-   *          filter, must be set to zero in this version of the driver.
-   */
-  uint32_t                  assignment:1;
-  /**
-   * @brief   Filter register 1 (identifier).
-   */
-  uint32_t                  register1;
-  /**
-   * @brief   Filter register 2 (mask/identifier depending on mode=0/1).
-   */
-  uint32_t                  register2;
-} CANFilter;
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   CAN MCR register initialization data.
-   * @note    Some bits in this register are enforced by the driver regardless
-   *          their status in this field.
-   */
-  uint32_t                  mcr;
-  /**
-   * @brief   CAN BTR register initialization data.
-   * @note    Some bits in this register are enforced by the driver regardless
-   *          their status in this field.
-   */
-  uint32_t                  btr;
-} CANConfig;
-
-/**
- * @brief   Structure representing an CAN driver.
- */
-typedef struct {
-  /**
-   * @brief   Driver state.
-   */
-  canstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const CANConfig           *config;
-  /**
-   * @brief   Transmission queue semaphore.
-   */
-  Semaphore                 txsem;
-  /**
-   * @brief   Receive queue semaphore.
-   */
-  Semaphore                 rxsem;
-  /**
-   * @brief   One or more frames become available.
-   * @note    After broadcasting this event it will not be broadcasted again
-   *          until the received frames queue has been completely emptied. It
-   *          is <b>not</b> broadcasted for each received frame. It is
-   *          responsibility of the application to empty the queue by
-   *          repeatedly invoking @p chReceive() when listening to this event.
-   *          This behavior minimizes the interrupt served by the system
-   *          because CAN traffic.
-   * @note    The flags associated to the listeners will indicate which
-   *          receive mailboxes become non-empty.
-   */
-  EventSource               rxfull_event;
-  /**
-   * @brief   One or more transmission mailbox become available.
-   * @note    The flags associated to the listeners will indicate which
-   *          transmit mailboxes become empty.
-   *
-   */
-  EventSource               txempty_event;
-  /**
-   * @brief   A CAN bus error happened.
-   * @note    The flags associated to the listeners will indicate the
-   *          error(s) that have occurred.
-   */
-  EventSource               error_event;
-#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
-  /**
-   * @brief   Entering sleep state event.
-   */
-  EventSource               sleep_event;
-  /**
-   * @brief   Exiting sleep state event.
-   */
-  EventSource               wakeup_event;
-#endif /* CAN_USE_SLEEP_MODE */
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Pointer to the CAN registers.
-   */
-  CAN_TypeDef               *can;
-} CANDriver;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_CAN_USE_CAN1 && !defined(__DOXYGEN__)
-extern CANDriver CAND1;
-#endif
-
-#if STM32_CAN_USE_CAN2 && !defined(__DOXYGEN__)
-extern CANDriver CAND2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void can_lld_init(void);
-  void can_lld_start(CANDriver *canp);
-  void can_lld_stop(CANDriver *canp);
-  bool_t can_lld_is_tx_empty(CANDriver *canp,
-                             canmbx_t mailbox);
-  void can_lld_transmit(CANDriver *canp,
-                        canmbx_t mailbox,
-                        const CANTxFrame *crfp);
-  bool_t can_lld_is_rx_nonempty(CANDriver *canp,
-                                canmbx_t mailbox);
-  void can_lld_receive(CANDriver *canp,
-                       canmbx_t mailbox,
-                       CANRxFrame *ctfp);
-#if CAN_USE_SLEEP_MODE
-  void can_lld_sleep(CANDriver *canp);
-  void can_lld_wakeup(CANDriver *canp);
-#endif /* CAN_USE_SLEEP_MODE */
-  void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_CAN */
-
-#endif /* _CAN_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/ext_lld.c b/os/hal/platforms/STM32/ext_lld.c
deleted file mode 100644
index 9cab60133..000000000
--- a/os/hal/platforms/STM32/ext_lld.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/ext_lld.c
- * @brief   STM32 EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTD1 driver identifier.
- */
-EXTDriver EXTD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
-  /* Driver initialization.*/
-  extObjectInit(&EXTD1);
-}
-
-/**
- * @brief   Configures and activates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
-  unsigned i;
-
-  if (extp->state == EXT_STOP)
-    ext_lld_exti_irq_enable();
-
-  /* Configuration of automatic channels.*/
-  for (i = 0; i < EXT_MAX_CHANNELS; i++)
-    if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
-      ext_lld_channel_enable(extp, i);
-    else
-      ext_lld_channel_disable(extp, i);
-}
-
-/**
- * @brief   Deactivates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-
-  if (extp->state == EXT_ACTIVE)
-    ext_lld_exti_irq_disable();
-
-  EXTI->EMR = 0;
-  EXTI->IMR = 0;
-  EXTI->PR  = 0xFFFFFFFF;
-#if STM32_EXTI_NUM_CHANNELS > 32
-  EXTI->PR2 = 0xFFFFFFFF;
-#endif
-}
-
-/**
- * @brief   Enables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
-  /* Setting the associated GPIO for external channels.*/
-  if (channel < 16) {
-    uint32_t n = channel >> 2;
-    uint32_t mask = ~(0xF << ((channel & 3) * 4));
-    uint32_t port = ((extp->config->channels[channel].mode &
-                      EXT_MODE_GPIO_MASK) >>
-                     EXT_MODE_GPIO_OFF) << ((channel & 3) * 4);
-
-#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||                 \
-    defined(STM32F10X_HD_VL) || defined(STM32F10X_LD)    ||                 \
-    defined(STM32F10X_MD)    || defined(STM32F10X_HD)    ||                 \
-    defined(STM32F10X_XL)    || defined(STM32F10X_CL)
-    AFIO->EXTICR[n] = (AFIO->EXTICR[n] & mask) | port;
-#else /* !defined(STM32F1XX) */
-    SYSCFG->EXTICR[n] = (SYSCFG->EXTICR[n] & mask) | port;
-#endif /* !defined(STM32F1XX) */
-  }
-
-#if STM32_EXTI_NUM_CHANNELS > 32
-  if (channel < 32) {
-#endif
-    /* Programming edge registers.*/
-    if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
-      EXTI->RTSR |= (1 << channel);
-    else
-      EXTI->RTSR &= ~(1 << channel);
-    if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
-      EXTI->FTSR |= (1 << channel);
-    else
-      EXTI->FTSR &= ~(1 << channel);
-
-    /* Programming interrupt and event registers.*/
-    if (extp->config->channels[channel].cb != NULL) {
-      EXTI->IMR |= (1 << channel);
-      EXTI->EMR &= ~(1 << channel);
-    }
-    else {
-      EXTI->EMR |= (1 << channel);
-      EXTI->IMR &= ~(1 << channel);
-    }
-#if STM32_EXTI_NUM_CHANNELS > 32
-  }
-  else {
-    /* Programming edge registers.*/
-    if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
-      EXTI->RTSR2 |= (1 << (32 - channel));
-    else
-      EXTI->RTSR2 &= ~(1 << (32 - channel));
-    if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
-      EXTI->FTSR2 |= (1 << (32 - channel));
-    else
-      EXTI->FTSR2 &= ~(1 << (32 - channel));
-
-    /* Programming interrupt and event registers.*/
-    if (extp->config->channels[channel].cb != NULL) {
-      EXTI->IMR2 |= (1 << (32 - channel));
-      EXTI->EMR2 &= ~(1 << (32 - channel));
-    }
-    else {
-      EXTI->EMR2 |= (1 << (32 - channel));
-      EXTI->IMR2 &= ~(1 << (32 - channel));
-    }
-  }
-#endif
-}
-
-/**
- * @brief   Disables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-
-  (void)extp;
-
-#if STM32_EXTI_NUM_CHANNELS > 32
-  if (channel < 32) {
-#endif
-    EXTI->IMR   &= ~(1 << channel);
-    EXTI->EMR   &= ~(1 << channel);
-    EXTI->RTSR  &= ~(1 << channel);
-    EXTI->FTSR  &= ~(1 << channel);
-    EXTI->PR     =  (1 << channel);
-#if STM32_EXTI_NUM_CHANNELS > 32
-  }
-  else {
-    EXTI->IMR2  &= ~(1 << (32 - channel));
-    EXTI->EMR2  &= ~(1 << (32 - channel));
-    EXTI->RTSR2 &= ~(1 << (32 - channel));
-    EXTI->FTSR2 &= ~(1 << (32 - channel));
-    EXTI->PR2    =  (1 << (32 - channel));
-  }
-#endif
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c
deleted file mode 100644
index 46ff53d5f..000000000
--- a/os/hal/platforms/STM32/mac_lld.c
+++ /dev/null
@@ -1,741 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/mac_lld.c
- * @brief   STM32 low level MAC driver code.
- *
- * @addtogroup MAC
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-#include "mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define BUFFER_SIZE ((((STM32_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
-
-/* MII divider optimal value.*/
-#if (STM32_HCLK >= 150000000)
-#define MACMIIDR_CR ETH_MACMIIAR_CR_Div102
-#elif (STM32_HCLK >= 100000000)
-#define MACMIIDR_CR ETH_MACMIIAR_CR_Div62
-#elif (STM32_HCLK >= 60000000)
-#define MACMIIDR_CR     ETH_MACMIIAR_CR_Div42
-#elif (STM32_HCLK >= 35000000)
-#define MACMIIDR_CR     ETH_MACMIIAR_CR_Div26
-#elif (STM32_HCLK >= 20000000)
-#define MACMIIDR_CR     ETH_MACMIIAR_CR_Div16
-#else
-#error "STM32_HCLK below minimum frequency for ETH operations (20MHz)"
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Ethernet driver 1.
- */
-MACDriver ETHD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
-                                              0x37, 0x01, 0x10};
-
-static stm32_eth_rx_descriptor_t rd[STM32_MAC_RECEIVE_BUFFERS];
-static stm32_eth_tx_descriptor_t td[STM32_MAC_TRANSMIT_BUFFERS];
-
-static uint32_t rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];
-static uint32_t tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Writes a PHY register.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] reg       register number
- * @param[in] value     new register value
- */
-static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) {
-
-  ETH->MACMIIDR = value;
-  ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR |
-                  ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
-  while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
-    ;
-}
-
-/**
- * @brief   Reads a PHY register.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] reg       register number
- *
- * @return              The PHY register content.
- */
-static uint32_t mii_read(MACDriver *macp, uint32_t reg) {
-
-  ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | ETH_MACMIIAR_MB;
-  while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
-    ;
-  return ETH->MACMIIDR;
-}
-
-#if !defined(BOARD_PHY_ADDRESS)
-/**
- * @brief   PHY address detection.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- */
-static void mii_find_phy(MACDriver *macp) {
-  uint32_t i;
-
-#if STM32_MAC_PHY_TIMEOUT > 0
-  halrtcnt_t start = halGetCounterValue();
-  halrtcnt_t timeout  = start + MS2RTT(STM32_MAC_PHY_TIMEOUT);
-  while (halIsCounterWithin(start, timeout)) {
-#endif
-    for (i = 0; i < 31; i++) {
-      macp->phyaddr = i << 11;
-      ETH->MACMIIDR = (i << 6) | MACMIIDR_CR;
-      if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
-          ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
-        return;
-      }
-    }
-#if STM32_MAC_PHY_TIMEOUT > 0
-  }
-#endif
-  /* Wrong or defective board.*/
-  chSysHalt();
-}
-#endif
-
-/**
- * @brief   MAC address setup.
- *
- * @param[in] p         pointer to a six bytes buffer containing the MAC
- *                      address
- */
-static void mac_lld_set_address(const uint8_t *p) {
-
-  /* MAC address configuration, only a single address comparator is used,
-     hash table not used.*/
-  ETH->MACA0HR   = ((uint32_t)p[5] << 8) |
-                   ((uint32_t)p[4] << 0);
-  ETH->MACA0LR   = ((uint32_t)p[3] << 24) |
-                   ((uint32_t)p[2] << 16) |
-                   ((uint32_t)p[1] << 8) |
-                   ((uint32_t)p[0] << 0);
-  ETH->MACA1HR   = 0x0000FFFF;
-  ETH->MACA1LR   = 0xFFFFFFFF;
-  ETH->MACA2HR   = 0x0000FFFF;
-  ETH->MACA2LR   = 0xFFFFFFFF;
-  ETH->MACA3HR   = 0x0000FFFF;
-  ETH->MACA3LR   = 0xFFFFFFFF;
-  ETH->MACHTHR   = 0;
-  ETH->MACHTLR   = 0;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-CH_IRQ_HANDLER(ETH_IRQHandler) {
-  uint32_t dmasr;
-
-  CH_IRQ_PROLOGUE();
-
-  dmasr = ETH->DMASR;
-  ETH->DMASR = dmasr; /* Clear status bits.*/
-
-  if (dmasr & ETH_DMASR_RS) {
-    /* Data Received.*/
-    chSysLockFromIsr();
-    chSemResetI(&ETHD1.rdsem, 0);
-#if MAC_USE_EVENTS
-    chEvtBroadcastI(&ETHD1.rdevent);
-#endif
-    chSysUnlockFromIsr();
-  }
-
-  if (dmasr & ETH_DMASR_TS) {
-    /* Data Transmitted.*/
-    chSysLockFromIsr();
-    chSemResetI(&ETHD1.tdsem, 0);
-    chSysUnlockFromIsr();
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level MAC initialization.
- *
- * @notapi
- */
-void mac_lld_init(void) {
-  unsigned i;
-
-  macObjectInit(&ETHD1);
-  ETHD1.link_up = FALSE;
-
-  /* Descriptor tables are initialized in chained mode, note that the first
-     word is not initialized here but in mac_lld_start().*/
-  for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) {
-    rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE;
-    rd[i].rdes2 = (uint32_t)rb[i];
-    rd[i].rdes3 = (uint32_t)&rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS];
-  }
-  for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) {
-    td[i].tdes1 = 0;
-    td[i].tdes2 = (uint32_t)tb[i];
-    td[i].tdes3 = (uint32_t)&td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS];
-  }
-
-  /* Selection of the RMII or MII mode based on info exported by board.h.*/
-#if defined(STM32F10X_CL)
-#if defined(BOARD_PHY_RMII)
-  AFIO->MAPR |= AFIO_MAPR_MII_RMII_SEL;
-#else
-  AFIO->MAPR &= ~AFIO_MAPR_MII_RMII_SEL;
-#endif
-#elif defined(STM32F2XX) || defined(STM32F4XX)
-#if defined(BOARD_PHY_RMII)
-  SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
-#else
-  SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL;
-#endif
-#else
-#error "unsupported STM32 platform for MAC driver"
-#endif
-
-  /* Reset of the MAC core.*/
-  rccResetETH();
-
-  /* MAC clocks temporary activation.*/
-  rccEnableETH(FALSE);
-
-  /* PHY address setup.*/
-#if defined(BOARD_PHY_ADDRESS)
-  ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
-#else
-  mii_find_phy(&ETHD1);
-#endif
-
-#if defined(BOARD_PHY_RESET)
-  /* PHY board-specific reset procedure.*/
-  BOARD_PHY_RESET();
-#else
-  /* PHY soft reset procedure.*/
-  mii_write(&ETHD1, MII_BMCR, BMCR_RESET);
-#if defined(BOARD_PHY_RESET_DELAY)
-  halPolledDelay(BOARD_PHY_RESET_DELAY);
-#endif
-  while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)
-    ;
-#endif
-
-#if STM32_MAC_ETH1_CHANGE_PHY_STATE
-  /* PHY in power down mode until the driver will be started.*/
-  mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN);
-#endif
-
-  /* MAC clocks stopped again.*/
-  rccDisableETH(FALSE);
-}
-
-/**
- * @brief   Configures and activates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_start(MACDriver *macp) {
-  unsigned i;
-
-  /* Resets the state of all descriptors.*/
-  for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++)
-    rd[i].rdes0 = STM32_RDES0_OWN;
-  macp->rxptr = (stm32_eth_rx_descriptor_t *)rd;
-  for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++)
-    td[i].tdes0 = STM32_TDES0_TCH;
-  macp->txptr = (stm32_eth_tx_descriptor_t *)td;
-
-  /* MAC clocks activation and commanded reset procedure.*/
-  rccEnableETH(FALSE);
-#if defined(STM32_MAC_DMABMR_SR)
-  ETH->DMABMR |= ETH_DMABMR_SR;
-  while(ETH->DMABMR & ETH_DMABMR_SR)
-    ;
-#endif
-
-  /* ISR vector enabled.*/
-  nvicEnableVector(ETH_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_MAC_ETH1_IRQ_PRIORITY));
-
-#if STM32_MAC_ETH1_CHANGE_PHY_STATE
-  /* PHY in power up mode.*/
-  mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
-#endif
-
-  /* MAC configuration.*/
-  ETH->MACFFR    = 0;
-  ETH->MACFCR    = 0;
-  ETH->MACVLANTR = 0;
-
-  /* MAC address setup.*/
-  if (macp->config->mac_address == NULL)
-    mac_lld_set_address(default_mac_address);
-  else
-    mac_lld_set_address(macp->config->mac_address);
-
-  /* Transmitter and receiver enabled.
-     Note that the complete setup of the MAC is performed when the link
-     status is detected.*/
-#if STM32_MAC_IP_CHECKSUM_OFFLOAD
-  ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE;
-#else
-  ETH->MACCR =                  ETH_MACCR_RE | ETH_MACCR_TE;
-#endif
-
-  /* DMA configuration:
-     Descriptor chains pointers.*/
-  ETH->DMARDLAR = (uint32_t)rd;
-  ETH->DMATDLAR = (uint32_t)td;
-
-  /* Enabling required interrupt sources.*/
-  ETH->DMASR    = ETH->DMASR;
-  ETH->DMAIER   = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
-
-  /* DMA general settings.*/
-  ETH->DMABMR   = ETH_DMABMR_AAB | ETH_DMABMR_RDP_1Beat | ETH_DMABMR_PBL_1Beat;
-
-  /* Transmit FIFO flush.*/
-  ETH->DMAOMR   = ETH_DMAOMR_FTF;
-  while (ETH->DMAOMR & ETH_DMAOMR_FTF)
-    ;
-
-  /* DMA final configuration and start.*/
-  ETH->DMAOMR   = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_TSF |
-                  ETH_DMAOMR_ST | ETH_DMAOMR_SR;
-}
-
-/**
- * @brief   Deactivates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_stop(MACDriver *macp) {
-
-  if (macp->state != MAC_STOP) {
-#if STM32_MAC_ETH1_CHANGE_PHY_STATE
-    /* PHY in power down mode until the driver will be restarted.*/
-    mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
-#endif
-
-    /* MAC and DMA stopped.*/
-    ETH->MACCR    = 0;
-    ETH->DMAOMR   = 0;
-    ETH->DMAIER   = 0;
-    ETH->DMASR    = ETH->DMASR;
-
-    /* MAC clocks stopped.*/
-    rccDisableETH(FALSE);
-
-    /* ISR vector disabled.*/
-    nvicDisableVector(ETH_IRQn);
-  }
-}
-
-/**
- * @brief   Returns a transmission descriptor.
- * @details One of the available transmission descriptors is locked and
- *          returned.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] tdp      pointer to a @p MACTransmitDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                      MACTransmitDescriptor *tdp) {
-  stm32_eth_tx_descriptor_t *tdes;
-
-  if (!macp->link_up)
-    return RDY_TIMEOUT;
-
-  chSysLock();
-
-  /* Get Current TX descriptor.*/
-  tdes = macp->txptr;
-
-  /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
-     another thread.*/
-  if (tdes->tdes0 & (STM32_TDES0_OWN | STM32_TDES0_LOCKED)) {
-    chSysUnlock();
-    return RDY_TIMEOUT;
-  }
-
-  /* Marks the current descriptor as locked using a reserved bit.*/
-  tdes->tdes0 |= STM32_TDES0_LOCKED;
-
-  /* Next TX descriptor to use.*/
-  macp->txptr = (stm32_eth_tx_descriptor_t *)tdes->tdes3;
-
-  chSysUnlock();
-
-  /* Set the buffer size and configuration.*/
-  tdp->offset   = 0;
-  tdp->size     = STM32_MAC_BUFFERS_SIZE;
-  tdp->physdesc = tdes;
-
-  return RDY_OK;
-}
-
-/**
- * @brief   Releases a transmit descriptor and starts the transmission of the
- *          enqueued data as a single frame.
- *
- * @param[in] tdp       the pointer to the @p MACTransmitDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
-
-  chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
-              "mac_lld_release_transmit_descriptor(), #1",
-              "attempt to release descriptor already owned by DMA");
-
-  chSysLock();
-
-  /* Unlocks the descriptor and returns it to the DMA engine.*/
-  tdp->physdesc->tdes1 = tdp->offset;
-  tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_MAC_IP_CHECKSUM_OFFLOAD) |
-                         STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS |
-                         STM32_TDES0_TCH | STM32_TDES0_OWN;
-
-  /* If the DMA engine is stalled then a restart request is issued.*/
-  if ((ETH->DMASR & ETH_DMASR_TPS) == ETH_DMASR_TPS_Suspended) {
-    ETH->DMASR   = ETH_DMASR_TBUS;
-    ETH->DMATPDR = ETH_DMASR_TBUS; /* Any value is OK.*/
-  }
-
-  chSysUnlock();
-}
-
-/**
- * @brief   Returns a receive descriptor.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] rdp      pointer to a @p MACReceiveDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                     MACReceiveDescriptor *rdp) {
-  stm32_eth_rx_descriptor_t *rdes;
-
-  chSysLock();
-
-  /* Get Current RX descriptor.*/
-  rdes = macp->rxptr;
-
-  /* Iterates through received frames until a valid one is found, invalid
-     frames are discarded.*/
-  while (!(rdes->rdes0 & STM32_RDES0_OWN)) {
-    if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES))
-#if STM32_MAC_IP_CHECKSUM_OFFLOAD
-        && (rdes->rdes0 & STM32_RDES0_FT)
-        && !(rdes->rdes0 & (STM32_RDES0_IPHCE | STM32_RDES0_PCE))
-#endif
-        && (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) {
-      /* Found a valid one.*/
-      rdp->offset   = 0;
-      rdp->size     = ((rdes->rdes0 & STM32_RDES0_FL_MASK) >> 16) - 4;
-      rdp->physdesc = rdes;
-      macp->rxptr   = (stm32_eth_rx_descriptor_t *)rdes->rdes3;
-
-      chSysUnlock();
-      return RDY_OK;
-    }
-    /* Invalid frame found, purging.*/
-    rdes->rdes0 = STM32_RDES0_OWN;
-    rdes = (stm32_eth_rx_descriptor_t *)rdes->rdes3;
-  }
-
-  /* Next descriptor to check.*/
-  macp->rxptr = rdes;
-
-  chSysUnlock();
-  return RDY_TIMEOUT;
-}
-
-/**
- * @brief   Releases a receive descriptor.
- * @details The descriptor and its buffer are made available for more incoming
- *          frames.
- *
- * @param[in] rdp       the pointer to the @p MACReceiveDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
-
-  chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
-              "mac_lld_release_receive_descriptor(), #1",
-              "attempt to release descriptor already owned by DMA");
-
-  chSysLock();
-
-  /* Give buffer back to the Ethernet DMA.*/
-  rdp->physdesc->rdes0 = STM32_RDES0_OWN;
-
-  /* If the DMA engine is stalled then a restart request is issued.*/
-  if ((ETH->DMASR & ETH_DMASR_RPS) == ETH_DMASR_RPS_Suspended) {
-    ETH->DMASR   = ETH_DMASR_RBUS;
-    ETH->DMARPDR = ETH_DMASR_RBUS; /* Any value is OK.*/
-  }
-
-  chSysUnlock();
-}
-
-/**
- * @brief   Updates and returns the link status.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @return              The link status.
- * @retval TRUE         if the link is active.
- * @retval FALSE        if the link is down.
- *
- * @notapi
- */
-bool_t mac_lld_poll_link_status(MACDriver *macp) {
-  uint32_t maccr, bmsr, bmcr;
-
-  maccr = ETH->MACCR;
-
-  /* PHY CR and SR registers read.*/
-  (void)mii_read(macp, MII_BMSR);
-  bmsr = mii_read(macp, MII_BMSR);
-  bmcr = mii_read(macp, MII_BMCR);
-
-  /* Check on auto-negotiation mode.*/
-  if (bmcr & BMCR_ANENABLE) {
-    uint32_t lpa;
-
-    /* Auto-negotiation must be finished without faults and link established.*/
-    if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
-        (BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
-      return macp->link_up = FALSE;
-
-    /* Auto-negotiation enabled, checks the LPA register.*/
-    lpa = mii_read(macp, MII_LPA);
-
-    /* Check on link speed.*/
-    if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
-      maccr |= ETH_MACCR_FES;
-    else
-      maccr &= ~ETH_MACCR_FES;
-
-    /* Check on link mode.*/
-    if (lpa & (LPA_10FULL | LPA_100FULL))
-      maccr |= ETH_MACCR_DM;
-    else
-      maccr &= ~ETH_MACCR_DM;
-  }
-  else {
-    /* Link must be established.*/
-    if (!(bmsr & BMSR_LSTATUS))
-      return macp->link_up = FALSE;
-
-    /* Check on link speed.*/
-    if (bmcr & BMCR_SPEED100)
-      maccr |= ETH_MACCR_FES;
-    else
-      maccr &= ~ETH_MACCR_FES;
-
-    /* Check on link mode.*/
-    if (bmcr & BMCR_FULLDPLX)
-      maccr |= ETH_MACCR_DM;
-    else
-      maccr &= ~ETH_MACCR_DM;
-  }
-
-  /* Changes the mode in the MAC.*/
-  ETH->MACCR = maccr;
-
-  /* Returns the link status.*/
-  return macp->link_up = TRUE;
-}
-
-/**
- * @brief   Writes to a transmit descriptor's stream.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf       pointer to the buffer containing the data to be
- *                      written
- * @param[in] size      number of bytes to be written
- * @return              The number of bytes written into the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if the maximum
- *                      frame size is reached.
- *
- * @notapi
- */
-size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                         uint8_t *buf,
-                                         size_t size) {
-
-  chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
-              "mac_lld_write_transmit_descriptor(), #1",
-              "attempt to write descriptor already owned by DMA");
-
-  if (size > tdp->size - tdp->offset)
-    size = tdp->size - tdp->offset;
-
-  if (size > 0) {
-    memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size);
-    tdp->offset += size;
-  }
-  return size;
-}
-
-/**
- * @brief   Reads from a receive descriptor's stream.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[in] buf       pointer to the buffer that will receive the read data
- * @param[in] size      number of bytes to be read
- * @return              The number of bytes read from the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if there are
- *                      no more bytes to read.
- *
- * @notapi
- */
-size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                       uint8_t *buf,
-                                       size_t size) {
-
-  chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
-              "mac_lld_read_receive_descriptor(), #1",
-              "attempt to read descriptor already owned by DMA");
-
-  if (size > rdp->size - rdp->offset)
-    size = rdp->size - rdp->offset;
-
-  if (size > 0) {
-    memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size);
-    rdp->offset += size;
-  }
-  return size;
-}
-
-#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
-/**
- * @brief   Returns a pointer to the next transmit buffer in the descriptor
- *          chain.
- * @note    The API guarantees that enough buffers can be requested to fill
- *          a whole frame.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] size      size of the requested buffer. Specify the frame size
- *                      on the first call then scale the value down subtracting
- *                      the amount of data already copied into the previous
- *                      buffers.
- * @param[out] sizep    pointer to variable receiving the buffer size, it is
- *                      zero when the last buffer has already been returned.
- *                      Note that a returned size lower than the amount
- *                      requested means that more buffers must be requested
- *                      in order to fill the frame data entirely.
- * @return              Pointer to the returned buffer.
- * @retval NULL         if the buffer chain has been entirely scanned.
- *
- * @notapi
- */
-uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
-                                          size_t size,
-                                          size_t *sizep) {
-
-  if (tdp->offset == 0) {
-    *sizep      = tdp->size;
-    tdp->offset = size;
-    return (uint8_t *)tdp->physdesc->tdes2;
-  }
-  *sizep = 0;
-  return NULL;
-}
-
-/**
- * @brief   Returns a pointer to the next receive buffer in the descriptor
- *          chain.
- * @note    The API guarantees that the descriptor chain contains a whole
- *          frame.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[out] sizep    pointer to variable receiving the buffer size, it is
- *                      zero when the last buffer has already been returned.
- * @return              Pointer to the returned buffer.
- * @retval NULL         if the buffer chain has been entirely scanned.
- *
- * @notapi
- */
-const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
-                                               size_t *sizep) {
-
-  if (rdp->size > 0) {
-    *sizep      = rdp->size;
-    rdp->offset = rdp->size;
-    rdp->size   = 0;
-    return (uint8_t *)rdp->physdesc->rdes2;
-  }
-  *sizep = 0;
-  return NULL;
-}
-#endif /* MAC_USE_ZERO_COPY */
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c
deleted file mode 100644
index cc048a03b..000000000
--- a/os/hal/platforms/STM32/sdc_lld.c
+++ /dev/null
@@ -1,791 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/sdc_lld.c
- * @brief   STM32 SDC subsystem low level driver source.
- *
- * @addtogroup SDC
- * @{
- */
-
-/*
- TODO: Try preerase blocks before writing (ACMD23).
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SDC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define DMA_CHANNEL                                                         \
-  STM32_DMA_GETCHANNEL(STM32_SDC_SDIO_DMA_STREAM,                           \
-                       STM32_SDC_SDIO_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief SDCD1 driver identifier.*/
-SDCDriver SDCD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
-/**
- * @brief   Buffer for temporary storage during unaligned transfers.
- */
-static union {
-  uint32_t  alignment;
-  uint8_t   buf[MMCSD_BLOCK_SIZE];
-} u;
-#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Prepares card to handle read transaction.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to read
- * @param[in] n         number of blocks to read
- * @param[in] resp      pointer to the response buffer
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-static bool_t sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
-                                   uint32_t n, uint32_t *resp) {
-
-  /* Driver handles data in 512 bytes blocks (just like HC cards). But if we
-     have not HC card than we must convert address from blocks to bytes.*/
-  if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY))
-    startblk *= MMCSD_BLOCK_SIZE;
-
-  if (n > 1) {
-    /* Send read multiple blocks command to card.*/
-    if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_MULTIPLE_BLOCK,
-                                   startblk, resp) || MMCSD_R1_ERROR(resp[0]))
-      return CH_FAILED;
-  }
-  else{
-    /* Send read single block command.*/
-    if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_SINGLE_BLOCK,
-                                   startblk, resp) || MMCSD_R1_ERROR(resp[0]))
-      return CH_FAILED;
-  }
-
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Prepares card to handle write transaction.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to read
- * @param[in] n         number of blocks to write
- * @param[in] resp      pointer to the response buffer
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-static bool_t sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
-                                    uint32_t n, uint32_t *resp) {
-
-  /* Driver handles data in 512 bytes blocks (just like HC cards). But if we
-     have not HC card than we must convert address from blocks to bytes.*/
-  if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY))
-    startblk *= MMCSD_BLOCK_SIZE;
-
-  if (n > 1) {
-    /* Write multiple blocks command.*/
-    if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK,
-                                   startblk, resp) || MMCSD_R1_ERROR(resp[0]))
-      return CH_FAILED;
-  }
-  else{
-    /* Write single block command.*/
-    if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_BLOCK,
-                                   startblk, resp) || MMCSD_R1_ERROR(resp[0]))
-      return CH_FAILED;
-  }
-
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Wait end of data transaction and performs finalizations.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] n         number of blocks in transaction
- * @param[in] resp      pointer to the response buffer
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- */
-static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
-                                           uint32_t *resp) {
-
-  /* Note the mask is checked before going to sleep because the interrupt
-     may have occurred before reaching the critical zone.*/
-  chSysLock();
-  if (SDIO->MASK != 0) {
-    chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_start_data_transaction(), #1", "not NULL");
-    sdcp->thread = chThdSelf();
-    chSchGoSleepS(THD_STATE_SUSPENDED);
-    chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_start_data_transaction(), #2", "not NULL");
-  }
-  if ((SDIO->STA & SDIO_STA_DATAEND) == 0) {
-    chSysUnlock();
-    return CH_FAILED;
-  }
-
-#if (defined(STM32F4XX) || defined(STM32F2XX))
-  /* Wait until DMA channel enabled to be sure that all data transferred.*/
-  while (sdcp->dma->stream->CR & STM32_DMA_CR_EN)
-    ;
-
-  /* DMA event flags must be manually cleared.*/
-  dmaStreamClearInterrupt(sdcp->dma);
-
-  SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
-  SDIO->DCTRL = 0;
-  chSysUnlock();
-
-  /* Wait until interrupt flags to be cleared.*/
-  /*while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF)
-    dmaStreamClearInterrupt(sdcp->dma);*/
-#else
-  /* Waits for transfer completion at DMA level, the the stream is
-     disabled and cleared.*/
-  dmaWaitCompletion(sdcp->dma);
-
-  SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
-  SDIO->DCTRL = 0;
-  chSysUnlock();
-#endif
-
-  /* Finalize transaction.*/
-  if (n > 1)
-    return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp);
-
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Gets SDC errors.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] sta       value of the STA register
- *
- * @notapi
- */
-static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sta) {
-  uint32_t errors = SDC_NO_ERROR;
-
-  if (sta & SDIO_STA_CCRCFAIL)
-    errors |= SDC_CMD_CRC_ERROR;
-  if (sta & SDIO_STA_DCRCFAIL)
-    errors |= SDC_DATA_CRC_ERROR;
-  if (sta & SDIO_STA_CTIMEOUT)
-    errors |= SDC_COMMAND_TIMEOUT;
-  if (sta & SDIO_STA_DTIMEOUT)
-    errors |= SDC_DATA_TIMEOUT;
-  if (sta & SDIO_STA_TXUNDERR)
-    errors |= SDC_TX_UNDERRUN;
-  if (sta & SDIO_STA_RXOVERR)
-    errors |= SDC_RX_OVERRUN;
-  if (sta & SDIO_STA_STBITERR)
-    errors |= SDC_STARTBIT_ERROR;
-
-  sdcp->errors |= errors;
-}
-
-/**
- * @brief   Performs clean transaction stopping in case of errors.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] n         number of blocks in transaction
- * @param[in] resp      pointer to the response buffer
- *
- * @notapi
- */
-static void sdc_lld_error_cleanup(SDCDriver *sdcp,
-                                  uint32_t n,
-                                  uint32_t *resp) {
-  uint32_t sta = SDIO->STA;
-
-  dmaStreamClearInterrupt(sdcp->dma);
-  dmaStreamDisable(sdcp->dma);
-  SDIO->ICR   = STM32_SDIO_ICR_ALL_FLAGS;
-  SDIO->MASK  = 0;
-  SDIO->DCTRL = 0;
-  sdc_lld_collect_errors(sdcp, sta);
-  if (n > 1)
-    sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if !defined(STM32_SDIO_HANDLER)
-#error "STM32_SDIO_HANDLER not defined"
-#endif
-/**
- * @brief   SDIO IRQ handler.
- * @details It just wakes transaction thread. All error  handling performs in
- *          that thread.
- *
- * @isr
- */
-CH_IRQ_HANDLER(STM32_SDIO_HANDLER) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr()
-
-  /* Disables the source but the status flags are not reset because the
-     read/write functions needs to check them.*/
-  SDIO->MASK = 0;
-
-  if (SDCD1.thread != NULL) {
-    chSchReadyI(SDCD1.thread);
-    SDCD1.thread = NULL;
-  }
-
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SDC driver initialization.
- *
- * @notapi
- */
-void sdc_lld_init(void) {
-
-  sdcObjectInit(&SDCD1);
-  SDCD1.thread = NULL;
-  SDCD1.dma    = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM);
-#if CH_DBG_ENABLE_ASSERTS
-  SDCD1.sdio   = SDIO;
-#endif
-}
-
-/**
- * @brief   Configures and activates the SDC peripheral.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_start(SDCDriver *sdcp) {
-
-  sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) |
-                  STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) |
-                  STM32_DMA_CR_PSIZE_WORD |
-                  STM32_DMA_CR_MSIZE_WORD |
-                  STM32_DMA_CR_MINC;
-
-#if (defined(STM32F4XX) || defined(STM32F2XX))
-  sdcp->dmamode |= STM32_DMA_CR_PFCTRL |
-                   STM32_DMA_CR_PBURST_INCR4 |
-                   STM32_DMA_CR_MBURST_INCR4;
-#endif
-
-  if (sdcp->state == BLK_STOP) {
-    /* Note, the DMA must be enabled before the IRQs.*/
-    bool_t b;
-    b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDIO_IRQ_PRIORITY, NULL, NULL);
-    chDbgAssert(!b, "sdc_lld_start(), #1", "stream already allocated");
-    dmaStreamSetPeripheral(sdcp->dma, &SDIO->FIFO);
-#if (defined(STM32F4XX) || defined(STM32F2XX))
-    dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL);
-#endif
-    nvicEnableVector(STM32_SDIO_NUMBER,
-                     CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY));
-    rccEnableSDIO(FALSE);
-  }
-
-  /* Configuration, card clock is initially stopped.*/
-  SDIO->POWER  = 0;
-  SDIO->CLKCR  = 0;
-  SDIO->DCTRL  = 0;
-  SDIO->DTIMER = 0;
-}
-
-/**
- * @brief   Deactivates the SDC peripheral.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_stop(SDCDriver *sdcp) {
-
-  if (sdcp->state != BLK_STOP) {
-
-    /* SDIO deactivation.*/
-    SDIO->POWER  = 0;
-    SDIO->CLKCR  = 0;
-    SDIO->DCTRL  = 0;
-    SDIO->DTIMER = 0;
-
-    /* Clock deactivation.*/
-    nvicDisableVector(STM32_SDIO_NUMBER);
-    dmaStreamRelease(sdcp->dma);
-    rccDisableSDIO(FALSE);
-  }
-}
-
-/**
- * @brief   Starts the SDIO clock and sets it to init mode (400kHz or less).
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_start_clk(SDCDriver *sdcp) {
-
-  (void)sdcp;
-
-  /* Initial clock setting: 400kHz, 1bit mode.*/
-  SDIO->CLKCR  = STM32_SDIO_DIV_LS;
-  SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1;
-  SDIO->CLKCR |= SDIO_CLKCR_CLKEN;
-
-  /* Clock activation delay.*/
-  chThdSleepMilliseconds(STM32_SDC_CLOCK_ACTIVATION_DELAY);
-}
-
-/**
- * @brief   Sets the SDIO clock to data mode (25MHz or less).
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_set_data_clk(SDCDriver *sdcp) {
-
-  (void)sdcp;
-
-  SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS;
-}
-
-/**
- * @brief   Stops the SDIO clock.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_stop_clk(SDCDriver *sdcp) {
-
-  (void)sdcp;
-
-  SDIO->CLKCR = 0;
-  SDIO->POWER = 0;
-}
-
-/**
- * @brief   Switches the bus to 4 bits mode.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] mode      bus mode
- *
- * @notapi
- */
-void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
-  uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS;
-
-  (void)sdcp;
-
-  switch (mode) {
-  case SDC_MODE_1BIT:
-    SDIO->CLKCR = clk;
-    break;
-  case SDC_MODE_4BIT:
-    SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0;
-    break;
-  case SDC_MODE_8BIT:
-    SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1;
-    break;
-  }
-}
-
-/**
- * @brief   Sends an SDIO command with no response expected.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] cmd       card command
- * @param[in] arg       command argument
- *
- * @notapi
- */
-void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
-
-  (void)sdcp;
-
-  SDIO->ARG = arg;
-  SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN;
-  while ((SDIO->STA & SDIO_STA_CMDSENT) == 0)
-    ;
-  SDIO->ICR = SDIO_ICR_CMDSENTC;
-}
-
-/**
- * @brief   Sends an SDIO command with a short response expected.
- * @note    The CRC is not verified.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] cmd       card command
- * @param[in] arg       command argument
- * @param[out] resp     pointer to the response buffer (one word)
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                              uint32_t *resp) {
-  uint32_t sta;
-
-  (void)sdcp;
-
-  SDIO->ARG = arg;
-  SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN;
-  while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
-                               SDIO_STA_CCRCFAIL)) == 0)
-    ;
-  SDIO->ICR = sta;
-  if ((sta & (SDIO_STA_CTIMEOUT)) != 0) {
-    sdc_lld_collect_errors(sdcp, sta);
-    return CH_FAILED;
-  }
-  *resp = SDIO->RESP1;
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Sends an SDIO command with a short response expected and CRC.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] cmd       card command
- * @param[in] arg       command argument
- * @param[out] resp     pointer to the response buffer (one word)
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                  uint32_t *resp) {
-  uint32_t sta;
-
-  (void)sdcp;
-
-  SDIO->ARG = arg;
-  SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN;
-  while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
-                               SDIO_STA_CCRCFAIL)) == 0)
-    ;
-  SDIO->ICR = sta;
-  if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) {
-    sdc_lld_collect_errors(sdcp, sta);
-    return CH_FAILED;
-  }
-  *resp = SDIO->RESP1;
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Sends an SDIO command with a long response expected and CRC.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] cmd       card command
- * @param[in] arg       command argument
- * @param[out] resp     pointer to the response buffer (four words)
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                 uint32_t *resp) {
-  uint32_t sta;
-
-  (void)sdcp;
-
-  SDIO->ARG = arg;
-  SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 |
-                              SDIO_CMD_CPSMEN;
-  while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
-                               SDIO_STA_CCRCFAIL)) == 0)
-    ;
-  SDIO->ICR = sta;
-  if ((sta & (STM32_SDIO_STA_ERROR_MASK)) != 0) {
-    sdc_lld_collect_errors(sdcp, sta);
-    return CH_FAILED;
-  }
-  /* Save bytes in reverse order because MSB in response comes first.*/
-  *resp++ = SDIO->RESP4;
-  *resp++ = SDIO->RESP3;
-  *resp++ = SDIO->RESP2;
-  *resp   = SDIO->RESP1;
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Reads one or more blocks.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to read
- * @param[out] buf      pointer to the read buffer
- * @param[in] n         number of blocks to read
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
-                            uint8_t *buf, uint32_t n) {
-  uint32_t resp[1];
-
-  chDbgCheck((n < (0x1000000 / MMCSD_BLOCK_SIZE)), "max transaction size");
-
-  SDIO->DTIMER = STM32_SDC_READ_TIMEOUT;
-
-  /* Checks for errors and waits for the card to be ready for reading.*/
-  if (_sdc_wait_for_transfer_state(sdcp))
-    return CH_FAILED;
-
-  /* Prepares the DMA channel for writing.*/
-  dmaStreamSetMemory0(sdcp->dma, buf);
-  dmaStreamSetTransactionSize(sdcp->dma,
-                              (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
-  dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M);
-  dmaStreamEnable(sdcp->dma);
-
-  /* Setting up data transfer.*/
-  SDIO->ICR   = STM32_SDIO_ICR_ALL_FLAGS;
-  SDIO->MASK  = SDIO_MASK_DCRCFAILIE |
-                SDIO_MASK_DTIMEOUTIE |
-                SDIO_MASK_STBITERRIE |
-                SDIO_MASK_RXOVERRIE |
-                SDIO_MASK_DATAENDIE;
-  SDIO->DLEN  = n * MMCSD_BLOCK_SIZE;
-
-  /* Transaction starts just after DTEN bit setting.*/
-  SDIO->DCTRL = SDIO_DCTRL_DTDIR |
-                SDIO_DCTRL_DBLOCKSIZE_3 |
-                SDIO_DCTRL_DBLOCKSIZE_0 |
-                SDIO_DCTRL_DMAEN |
-                SDIO_DCTRL_DTEN;
-
-  /* Talk to card what we want from it.*/
-  if (sdc_lld_prepare_read(sdcp, startblk, n, resp) == TRUE)
-    goto error;
-  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE)
-    goto error;
-
-  return CH_SUCCESS;
-
-error:
-  sdc_lld_error_cleanup(sdcp, n, resp);
-  return CH_FAILED;
-}
-
-/**
- * @brief   Writes one or more blocks.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to write
- * @param[out] buf      pointer to the write buffer
- * @param[in] n         number of blocks to write
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
-                             const uint8_t *buf, uint32_t n) {
-  uint32_t resp[1];
-
-  chDbgCheck((n < (0x1000000 / MMCSD_BLOCK_SIZE)), "max transaction size");
-
-  SDIO->DTIMER = STM32_SDC_WRITE_TIMEOUT;
-
-  /* Checks for errors and waits for the card to be ready for writing.*/
-  if (_sdc_wait_for_transfer_state(sdcp))
-    return CH_FAILED;
-
-  /* Prepares the DMA channel for writing.*/
-  dmaStreamSetMemory0(sdcp->dma, buf);
-  dmaStreamSetTransactionSize(sdcp->dma,
-                              (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
-  dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_M2P);
-  dmaStreamEnable(sdcp->dma);
-
-  /* Setting up data transfer.*/
-  SDIO->ICR   = STM32_SDIO_ICR_ALL_FLAGS;
-  SDIO->MASK  = SDIO_MASK_DCRCFAILIE |
-                SDIO_MASK_DTIMEOUTIE |
-                SDIO_MASK_STBITERRIE |
-                SDIO_MASK_TXUNDERRIE |
-                SDIO_MASK_DATAENDIE;
-  SDIO->DLEN  = n * MMCSD_BLOCK_SIZE;
-
-  /* Talk to card what we want from it.*/
-  if (sdc_lld_prepare_write(sdcp, startblk, n, resp) == TRUE)
-    goto error;
-
-  /* Transaction starts just after DTEN bit setting.*/
-  SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 |
-                SDIO_DCTRL_DBLOCKSIZE_0 |
-                SDIO_DCTRL_DMAEN |
-                SDIO_DCTRL_DTEN;
-  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE)
-    goto error;
-
-  return CH_SUCCESS;
-
-error:
-  sdc_lld_error_cleanup(sdcp, n, resp);
-  return CH_FAILED;
-}
-
-/**
- * @brief   Reads one or more blocks.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to read
- * @param[out] buf      pointer to the read buffer
- * @param[in] n         number of blocks to read
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
-                    uint8_t *buf, uint32_t n) {
-
-#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
-  if (((unsigned)buf & 3) != 0) {
-    uint32_t i;
-    for (i = 0; i < n; i++) {
-      if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1))
-        return CH_FAILED;
-      memcpy(buf, u.buf, MMCSD_BLOCK_SIZE);
-      buf += MMCSD_BLOCK_SIZE;
-      startblk++;
-    }
-    return CH_SUCCESS;
-  }
-#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
-  return sdc_lld_read_aligned(sdcp, startblk, buf, n);
-}
-
-/**
- * @brief   Writes one or more blocks.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to write
- * @param[out] buf      pointer to the write buffer
- * @param[in] n         number of blocks to write
- *
- * @return              The operation status.
- * @retval CH_SUCCESS  operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
-                     const uint8_t *buf, uint32_t n) {
-
-#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
-  if (((unsigned)buf & 3) != 0) {
-    uint32_t i;
-    for (i = 0; i < n; i++) {
-      memcpy(u.buf, buf, MMCSD_BLOCK_SIZE);
-      buf += MMCSD_BLOCK_SIZE;
-      if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1))
-        return CH_FAILED;
-      startblk++;
-    }
-    return CH_SUCCESS;
-  }
-#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
-  return sdc_lld_write_aligned(sdcp, startblk, buf, n);
-}
-
-/**
- * @brief   Waits for card idle condition.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   the operation succeeded.
- * @retval CH_FAILED    the operation failed.
- *
- * @api
- */
-bool_t sdc_lld_sync(SDCDriver *sdcp) {
-
-  /* TODO: Implement.*/
-  (void)sdcp;
-  return CH_SUCCESS;
-}
-
-#endif /* HAL_USE_SDC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h
deleted file mode 100644
index 89ce3f49f..000000000
--- a/os/hal/platforms/STM32/sdc_lld.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/sdc_lld.h
- * @brief   STM32 SDC subsystem low level driver header.
- *
- * @addtogroup SDC
- * @{
- */
-
-#ifndef _SDC_LLD_H_
-#define _SDC_LLD_H_
-
-#if HAL_USE_SDC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief Value to clear all interrupts flag at once.
- */
-#define STM32_SDIO_ICR_ALL_FLAGS (SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | \
-                                  SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC | \
-                                  SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC |  \
-                                  SDIO_ICR_CMDRENDC  | SDIO_ICR_CMDSENTC |  \
-                                  SDIO_ICR_DATAENDC  | SDIO_ICR_STBITERRC | \
-                                  SDIO_ICR_DBCKENDC  | SDIO_ICR_SDIOITC |   \
-                                  SDIO_ICR_CEATAENDC)
-
-/**
- * @brief Mask of error flags in STA register.
- */
-#define STM32_SDIO_STA_ERROR_MASK (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL |  \
-                                   SDIO_STA_CTIMEOUT | SDIO_STA_DTIMEOUT |  \
-                                   SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   SDIO DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SDC_SDIO_DMA_PRIORITY         3
-#endif
-
-/**
- * @brief   SDIO interrupt priority level setting.
- */
-#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SDC_SDIO_IRQ_PRIORITY         9
-#endif
-
-/**
- * @brief   Write timeout in milliseconds.
- */
-#if !defined(SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__)
-#define SDC_WRITE_TIMEOUT_MS                250
-#endif
-
-/**
- * @brief   Read timeout in milliseconds.
- */
-#if !defined(SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__)
-#define SDC_READ_TIMEOUT_MS                 25
-#endif
-
-/**
- * @brief   Card clock activation delay in milliseconds.
- */
-#if !defined(STM32_SDC_CLOCK_ACTIVATION_DELAY) || defined(__DOXYGEN__)
-#define STM32_SDC_CLOCK_ACTIVATION_DELAY    10
-#endif
-
-/**
- * @brief   Support for unaligned transfers.
- * @note    Unaligned transfers are much slower.
- */
-#if !defined(STM32_SDC_SDIO_UNALIGNED_SUPPORT) || defined(__DOXYGEN__)
-#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    TRUE
-#endif
-
-#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
-
-/**
- * @brief   DMA stream used for SDC operations.
- * @note    This option is only available on platforms with enhanced DMA.
- */
-#if !defined(STM32_SDC_SDIO_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 3)
-#endif
-
-#else /* !STM32_ADVANCED_DMA*/
-#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
-
-#endif /* !STM32_ADVANCED_DMA*/
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !STM32_HAS_SDIO
-#error "SDIO not present in the selected device"
-#endif
-
-#if !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SDC_SDIO_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SDIO"
-#endif
-
-#if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDIO_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SDIO"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*
- * SDIO clock divider.
- */
-#if (defined(STM32F4XX) || defined(STM32F2XX))
-#define STM32_SDIO_DIV_HS                   0
-#define STM32_SDIO_DIV_LS                   120
-
-#elif STM32_HCLK > 48000000
-#define STM32_SDIO_DIV_HS                   1
-#define STM32_SDIO_DIV_LS                   178
-#else
-
-#define STM32_SDIO_DIV_HS                   0
-#define STM32_SDIO_DIV_LS                   118
-#endif
-
-/**
- * @brief   SDIO data timeouts in SDIO clock cycles.
- */
-#if (defined(STM32F4XX) || defined(STM32F2XX))
-#if !STM32_CLOCK48_REQUIRED
-#error "SDIO requires STM32_CLOCK48_REQUIRED to be enabled"
-#endif
-
-#define STM32_SDC_WRITE_TIMEOUT                                             \
-  (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS)
-#define STM32_SDC_READ_TIMEOUT                                              \
-  (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS)
-
-#else
-#define STM32_SDC_WRITE_TIMEOUT                                             \
-  (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS)
-#define STM32_SDC_READ_TIMEOUT                                              \
-  (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS)
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of SDIO bus mode.
- */
-typedef enum {
-  SDC_MODE_1BIT = 0,
-  SDC_MODE_4BIT,
-  SDC_MODE_8BIT
-} sdcbusmode_t;
-
-/**
- * @brief   Type of card flags.
- */
-typedef uint32_t sdcmode_t;
-
-/**
- * @brief   SDC Driver condition flags type.
- */
-typedef uint32_t sdcflags_t;
-
-/**
- * @brief   Type of a structure representing an SDC driver.
- */
-typedef struct SDCDriver SDCDriver;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t dummy;
-} SDCConfig;
-
-/**
- * @brief   @p SDCDriver specific methods.
- */
-#define _sdc_driver_methods                                                 \
-  _mmcsd_block_device_methods
-
-/**
- * @extends MMCSDBlockDeviceVMT
- *
- * @brief   @p SDCDriver virtual methods table.
- */
-struct SDCDriverVMT {
-  _sdc_driver_methods
-};
-
-/**
- * @brief   Structure representing an SDC driver.
- */
-struct SDCDriver {
-  /**
-   * @brief Virtual Methods Table.
-   */
-  const struct SDCDriverVMT *vmt;
-  _mmcsd_block_device_data
-  /**
-   * @brief Current configuration data.
-   */
-  const SDCConfig           *config;
-  /**
-   * @brief Various flags regarding the mounted card.
-   */
-  sdcmode_t                 cardmode;
-  /**
-   * @brief Errors flags.
-   */
-  sdcflags_t                errors;
-  /**
-   * @brief Card RCA.
-   */
-  uint32_t                  rca;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Thread waiting for I/O completion IRQ.
-   */
-  Thread                    *thread;
-  /**
-   * @brief     DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-  /**
-   * @brief     Transmit DMA channel.
-   */
-  const stm32_dma_stream_t  *dma;
-  /**
-   * @brief     Pointer to the SDIO registers block.
-   * @note      Used only for dubugging purpose.
-   */
-#if CH_DBG_ENABLE_ASSERTS
-  SDIO_TypeDef              *sdio;
-#endif
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern SDCDriver SDCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sdc_lld_init(void);
-  void sdc_lld_start(SDCDriver *sdcp);
-  void sdc_lld_stop(SDCDriver *sdcp);
-  void sdc_lld_start_clk(SDCDriver *sdcp);
-  void sdc_lld_set_data_clk(SDCDriver *sdcp);
-  void sdc_lld_stop_clk(SDCDriver *sdcp);
-  void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
-  void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
-  bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                uint32_t *resp);
-  bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                    uint32_t *resp);
-  bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                   uint32_t *resp);
-  bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
-                      uint8_t *buf, uint32_t n);
-  bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
-                       const uint8_t *buf, uint32_t n);
-  bool_t sdc_lld_sync(SDCDriver *sdcp);
-  bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp);
-  bool_t sdc_lld_is_write_protected(SDCDriver *sdcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SDC */
-
-#endif /* _SDC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32/stm32.h b/os/hal/platforms/STM32/stm32.h
deleted file mode 100644
index 1ad0691bc..000000000
--- a/os/hal/platforms/STM32/stm32.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32/stm32.h
- * @brief   STM32 common header.
- * @pre     One of the following macros must be defined before including
- *          this header, the macro selects the inclusion of the appropriate
- *          vendor header:
- *          - STM32F0XX for Entry Level devices.
- *          - STM32F10X_LD_VL for Value Line Low Density devices.
- *          - STM32F10X_MD_VL for Value Line Medium Density devices.
- *          - STM32F10X_LD for Performance Low Density devices.
- *          - STM32F10X_MD for Performance Medium Density devices.
- *          - STM32F10X_HD for Performance High Density devices.
- *          - STM32F10X_XL for Performance eXtra Density devices.
- *          - STM32F10X_CL for Connectivity Line devices.
- *          - STM32F2XX for High-performance STM32 F-2 devices.
- *          - STM32F30X for Analog & DSP devices.
- *          - STM32F37X for Analog & DSP devices.
- *          - STM32F4XX for High-performance STM32 F-4 devices.
- *          - STM32L1XX_MD for Ultra Low Power Medium-density devices.
- *          - STM32L1XX_MDP for Ultra Low Power Medium-density Plus devices.
- *          - STM32L1XX_HD for Ultra Low Power High-density devices.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _STM32_H_
-#define _STM32_H_
-
-#if defined(STM32F030)         || defined(STM32F0XX_LD)    ||               \
-    defined(STM32F0XX_MD)
-#include "stm32f0xx.h"
-
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
-      defined(STM32F10X_HD_VL) || defined(STM32F10X_LD)    ||               \
-      defined(STM32F10X_MD)    || defined(STM32F10X_HD)    ||               \
-      defined(STM32F10X_XL)    || defined(STM32F10X_CL)    ||               \
-      defined(__DOXYGEN__)
-#include "stm32f10x.h"
-
-#elif defined(STM32F2XX)
-#include "stm32f2xx.h"
-
-#elif defined(STM32F30X)
-#include "stm32f30x.h"
-
-#elif defined(STM32F37X)
-#include "stm32f37x.h"
-
-#elif defined(STM32F401xx)     || defined(STM32F40_41xxx)  ||               \
-      defined(STM32F427_437xx) || defined(STM32F429_439xx)
-#include "stm32f4xx.h"
-
-#elif defined(STM32L1XX_MD)    || defined(STM32L1XX_MDP)   ||               \
-      defined(STM32L1XX_HD)
-#include "stm32l1xx.h"
-
-#else
-#error "STM32 device not specified"
-#endif
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#endif /* _STM32_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
deleted file mode 100644
index ba4834b40..000000000
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F0xx/adc_lld.c
- * @brief   STM32F0xx ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Stops an ongoing conversion, if any.
- *
- * @param[in] adc       pointer to the ADC registers block
- */
-static void adc_lld_stop_adc(ADC_TypeDef *adc) {
-
-  if (adc->CR & ADC_CR_ADSTART) {
-    adc->CR |= ADC_CR_ADSTP;
-    while (adc->CR & ADC_CR_ADSTP)
-      ;
-  }
-}
-
-/**
- * @brief   ADC DMA ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    /* DMA, this could help only if the DMA tries to access an unmapped
-       address space or violates alignment rules.*/
-    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
-  }
-  else {
-    /* It is possible that the conversion group has already be reset by the
-       ADC error handler, in this case this interrupt is spurious.*/
-    if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
-        /* Transfer complete processing.*/
-        _adc_isr_full_code(adcp);
-      }
-      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
-    }
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-/**
- * @brief   ADC interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector70) {
-  uint32_t isr;
-
-  CH_IRQ_PROLOGUE();
-
-  isr = ADC1->ISR;
-  ADC1->ISR = isr;
-
-  /* It could be a spurious interrupt caused by overflows after DMA disabling,
-     just ignore it in this case.*/
-  if (ADCD1.grpp != NULL) {
-    /* Note, an overflow may occur after the conversion ended before the driver
-       is able to stop the ADC, this is why the DMA channel is checked too.*/
-    if ((isr & ADC_ISR_OVR) &&
-        (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
-      /* ADC overflow condition, this could happen only if the DMA is unable
-         to read data fast enough.*/
-      _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
-    }
-    if (isr & ADC_ISR_AWD) {
-      /* Analog watchdog error.*/
-      _adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
-    }
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if STM32_ADC_USE_ADC1
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-  ADCD1.adc = ADC1;
-  ADCD1.dmastp  = STM32_DMA1_STREAM1;
-  ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-#endif
-
-  /* The shared vector is initialized on driver initialization and never
-     disabled.*/
-  nvicEnableVector(12, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
-
-  /* Calibration procedure.*/
-  rccEnableADC1(FALSE);
-  chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state");
-  ADC1->CR |= ADC_CR_ADCAL;
-  while (ADC1->CR & ADC_CR_ADCAL)
-    ;
-  rccDisableADC1(FALSE);
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  /* If in stopped state then enables the ADC and DMA clocks.*/
-  if (adcp->state == ADC_STOP) {
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-      bool_t b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
-                            (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
-      rccEnableADC1(FALSE);
-#if STM32_ADCSW == STM32_ADCSW_HSI14
-      /* Clock from HSI14, no need for jitter removal.*/
-      ADC1->CFGR2 = 0x00001000;
-#else
-#if STM32_ADCPRE == STM32_ADCPRE_DIV2
-      ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV2;
-#else
-      ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV4;
-#endif
-#endif
-    }
-#endif /* STM32_ADC_USE_ADC1 */
-
-    /* ADC initial setup, starting the analog part here in order to reduce
-       the latency when starting a conversion.*/
-    adcp->adc->CR = ADC_CR_ADEN;
-    while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
-      ;
-  }
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  /* If in ready state then disables the ADC clock and analog part.*/
-  if (adcp->state == ADC_READY) {
-
-    dmaStreamRelease(adcp->dmastp);
-
-    /* Disabling ADC.*/
-    if (adcp->adc->CR & ADC_CR_ADEN) {
-      adc_lld_stop_adc(adcp->adc);
-      adcp->adc->CR |= ADC_CR_ADDIS;
-      while (adcp->adc->CR & ADC_CR_ADDIS)
-        ;
-    }
-
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp)
-      rccDisableADC1(FALSE);
-#endif
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t mode;
-  const ADCConversionGroup *grpp = adcp->grpp;
-
-  /* DMA setup.*/
-  mode = adcp->dmamode;
-  if (grpp->circular) {
-    mode |= STM32_DMA_CR_CIRC;
-    if (adcp->depth > 1) {
-      /* If circular buffer depth > 1, then the half transfer interrupt
-         is enabled in order to allow streaming processing.*/
-      mode |= STM32_DMA_CR_HTIE;
-    }
-  }
-  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
-  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
-                                            (uint32_t)adcp->depth);
-  dmaStreamSetMode(adcp->dmastp, mode);
-  dmaStreamEnable(adcp->dmastp);
-
-  /* ADC setup, if it is defined a callback for the analog watch dog then it
-     is enabled.*/
-  adcp->adc->ISR    = adcp->adc->ISR;
-  adcp->adc->IER    = ADC_IER_OVRIE | ADC_IER_AWDIE;
-  adcp->adc->TR     = grpp->tr;
-  adcp->adc->SMPR   = grpp->smpr;
-  adcp->adc->CHSELR = grpp->chselr;
-
-  /* ADC configuration and start.*/
-  adcp->adc->CFGR1  = grpp->cfgr1 | ADC_CFGR1_CONT  | ADC_CFGR1_DMACFG |
-                                    ADC_CFGR1_DMAEN;
-  adcp->adc->CR    |= ADC_CR_ADSTART;
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-  dmaStreamDisable(adcp->dmastp);
-  adc_lld_stop_adc(adcp->adc);
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
deleted file mode 100644
index 411e31581..000000000
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F0xx/adc_lld.h
- * @brief   STM32F0xx ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Sampling rates
- * @{
- */
-#define ADC_SMPR_SMP_1P5        0   /**< @brief 14 cycles conversion time   */
-#define ADC_SMPR_SMP_7P5        1   /**< @brief 21 cycles conversion time.  */
-#define ADC_SMPR_SMP_13P5       2   /**< @brief 28 cycles conversion time.  */
-#define ADC_SMPR_SMP_28P5       3   /**< @brief 41 cycles conversion time.  */
-#define ADC_SMPR_SMP_41P5       4   /**< @brief 54 cycles conversion time.  */
-#define ADC_SMPR_SMP_55P5       5   /**< @brief 68 cycles conversion time.  */
-#define ADC_SMPR_SMP_71P5       6   /**< @brief 84 cycles conversion time.  */
-#define ADC_SMPR_SMP_239P5      7   /**< @brief 252 cycles conversion time. */
-/** @} */
-
-/**
- * @name    Resolution
- * @{
- */
-#define ADC_CFGR1_RES_12BIT     (0 << 3)
-#define ADC_CFGR1_RES_10BIT     (1 << 3)
-#define ADC_CFGR1_RES_8BIT      (2 << 3)
-#define ADC_CFGR1_RES_6BIT      (3 << 3)
-/** @} */
-
-/**
- * @name    Threashold register initializer
- * @{
- */
-#define ADC_TR(low, high)       (((uint32_t)(high) << 16) | (uint32_t)(low))
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1                  FALSE
-#endif
-
-/**
- * @brief   ADC1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_PRIORITY         2
-#endif
-
-/**
- * @brief   ADC interrupt priority level setting.
- */
-#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_IRQ_PRIORITY              2
-#endif
-
-/**
- * @brief   ADC1 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
-#error "ADC1 not present in the selected device"
-#endif
-
-#if !STM32_ADC_USE_ADC1
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1 DMA"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC1"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
-  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
-  ADC_ERR_AWD = 2                           /**< Analog watchdog triggered. */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    The use of this configuration structure requires knowledge of
- *          STM32 ADC cell registers interface, please refer to the STM32
- *          reference manual for details.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   ADC CFGR1 register initialization data.
-   */
-  uint32_t                  cfgr1;
-  /**
-   * @brief   ADC TR register initialization data.
-   */
-  uint32_t                  tr;
-  /**
-   * @brief   ADC SMPR register initialization data.
-   */
-  uint32_t                  smpr;
-  /**
-   * @brief   ADC CHSELR register initialization data.
-   * @details The number of bits at logic level one in this register must
-   *          be equal to the number in the @p num_channels field.
-   */
-  uint32_t                  chselr;
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the ADCx registers block.
-   */
-  ADC_TypeDef               *adc;
-  /**
-   * @brief Pointer to associated DMA channel.
-   */
-  const stm32_dma_stream_t  *dmastp;
-  /**
-   * @brief DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Changes the value of the ADC CCR register.
- * @details Use this function in order to enable or disable the internal
- *          analog sources. See the documentation in the STM32F0xx Reference
- *          Manual.
- */
-#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.c b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
deleted file mode 100644
index afccfdd8c..000000000
--- a/os/hal/platforms/STM32F0xx/ext_lld_isr.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F0xx/ext_lld_isr.c
- * @brief   STM32F0xx EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTI[0]...EXTI[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector54) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 0) | (1 << 1));
-  EXTI->PR = pr;
-  if (pr & (1 << 0))
-    EXTD1.config->channels[0].cb(&EXTD1, 0);
-  if (pr & (1 << 1))
-    EXTD1.config->channels[1].cb(&EXTD1, 1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[2]...EXTI[3] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector58) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 2) | (1 << 3));
-  EXTI->PR = pr;
-  if (pr & (1 << 2))
-    EXTD1.config->channels[2].cb(&EXTD1, 2);
-  if (pr & (1 << 3))
-    EXTD1.config->channels[3].cb(&EXTD1, 3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[4]...EXTI[15] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector5C) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 4)  | (1 << 5)  | (1 << 6)  | (1 << 7)  | (1 << 8)  |
-                   (1 << 9)  | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) |
-                   (1 << 14) | (1 << 15));
-  EXTI->PR = pr;
-  if (pr & (1 << 4))
-    EXTD1.config->channels[4].cb(&EXTD1, 4);
-  if (pr & (1 << 5))
-    EXTD1.config->channels[5].cb(&EXTD1, 5);
-  if (pr & (1 << 6))
-    EXTD1.config->channels[6].cb(&EXTD1, 6);
-  if (pr & (1 << 7))
-    EXTD1.config->channels[7].cb(&EXTD1, 7);
-  if (pr & (1 << 8))
-    EXTD1.config->channels[8].cb(&EXTD1, 8);
-  if (pr & (1 << 9))
-    EXTD1.config->channels[9].cb(&EXTD1, 9);
-  if (pr & (1 << 10))
-    EXTD1.config->channels[10].cb(&EXTD1, 10);
-  if (pr & (1 << 11))
-    EXTD1.config->channels[11].cb(&EXTD1, 11);
-  if (pr & (1 << 12))
-    EXTD1.config->channels[12].cb(&EXTD1, 12);
-  if (pr & (1 << 13))
-    EXTD1.config->channels[13].cb(&EXTD1, 13);
-  if (pr & (1 << 14))
-    EXTD1.config->channels[14].cb(&EXTD1, 14);
-  if (pr & (1 << 15))
-    EXTD1.config->channels[15].cb(&EXTD1, 15);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[16] interrupt handler (PVD).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector44) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 16);
-  EXTD1.config->channels[16].cb(&EXTD1, 16);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[17] interrupt handler (RTC).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector48) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 17);
-  EXTD1.config->channels[17].cb(&EXTD1, 17);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(void) {
-
-  nvicEnableVector(EXTI0_1_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_1_IRQ_PRIORITY));
-  nvicEnableVector(EXTI2_3_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_3_IRQ_PRIORITY));
-  nvicEnableVector(EXTI4_15_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_15_IRQ_PRIORITY));
-  nvicEnableVector(PVD_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
-  nvicEnableVector(RTC_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(void) {
-
-  nvicDisableVector(EXTI0_1_IRQn);
-  nvicDisableVector(EXTI2_3_IRQn);
-  nvicDisableVector(EXTI4_15_IRQn);
-  nvicDisableVector(PVD_IRQn);
-  nvicDisableVector(RTC_IRQn);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
deleted file mode 100644
index be9ccf1eb..000000000
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F0xx/hal_lld.c
- * @brief   STM32F0xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes the backup domain.
- * @note    WARNING! Changing clock source impossible without resetting
- *          of the whole BKP domain.
- */
-static void hal_lld_backup_domain_init(void) {
-
-  /* Backup domain access enabled and left open.*/
-  PWR->CR |= PWR_CR_DBP;
-
-  /* Reset BKP domain if different clock source selected.*/
-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
-    /* Backup domain reset.*/
-    RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0;
-  }
-
-  /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-#if defined(STM32_LSE_BYPASS)
-  /* LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
-#else
-  /* No LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
-#endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
-#endif
-
-#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
-  /* If the backup domain hasn't been initialized yet then proceed with
-     initialization.*/
-  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
-    /* Selects clock source.*/
-    RCC->BDCR |= STM32_RTCSEL;
-
-    /* RTC clock enabled.*/
-    RCC->BDCR |= RCC_BDCR_RTCEN;
-  }
-#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* Reset of all peripherals.*/
-  rccResetAPB1(0xFFFFFFFF);
-  rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
-
-  /* SysTick initialization using the system clock.*/
-  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(FALSE);
-
-  /* Initializes the backup domain.*/
-  hal_lld_backup_domain_init();
-
-#if defined(STM32_DMA_REQUIRED)
-  dmaInit();
-#endif
-
-  /* Programmable voltage detector enable.*/
-#if STM32_PVD_ENABLE
-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-#endif /* STM32_PVD_ENABLE */
-}
-
-/**
- * @brief   STM32 clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function should be invoked just after the system reset.
- *
- * @special
- */
-void stm32_clock_init(void) {
-
-#if !STM32_NO_INIT
-  /* HSI setup, it enforces the reset situation in order to handle possible
-     problems with JTAG probes and re-initializations.*/
-  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;                                       /* Wait until HSI is stable.    */
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
-  RCC->CFGR = 0;                            /* CFGR reset value.            */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;                                       /* Waits until HSI is selected. */
-
-#if STM32_HSE_ENABLED
-  /* HSE activation.*/
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
-#else
-  /* No HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON;
-#endif
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;                                       /* Waits until HSE is stable.   */
-#endif
-
-#if STM32_HSE14_ENABLED
-  /* HSI14 activation.*/
-  RCC->CR2 |= RCC_CR2_HSI14ON;
-  while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
-    ;                                       /* Waits until HSI14 is stable. */
-#endif
-
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                                       /* Waits until LSI is stable.   */
-#endif
-
-  /* Clock settings.*/
-  RCC->CFGR  = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
-               STM32_ADCPRE | STM32_PPRE   | STM32_HPRE;
-  RCC->CFGR2 = STM32_PREDIV;
-  RCC->CFGR3 = STM32_ADCSW  | STM32_CECSW  | STM32_I2C1SW |
-               STM32_USART1SW;
-
-#if STM32_ACTIVATE_PLL
-  /* PLL activation.*/
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;                                       /* Waits until PLL is stable.   */
-#endif
-
-  /* Flash setup and final clock selection.   */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* Switching to the configured clock source if it is different from HSI.*/
-#if (STM32_SW != STM32_SW_HSI)
-  /* Switches clock source.*/
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;                                       /* Waits selection complete.    */
-#endif
-
-  /* SYSCFG clock enabled here because it is a multi-functional unit shared
-     among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
-#endif /* !STM32_NO_INIT */
-}
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
deleted file mode 100644
index fd166d7c3..000000000
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ /dev/null
@@ -1,796 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F0xx/hal_lld.h
- * @brief   STM32F0xx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - STM32_LSECLK.
- *          - STM32_LSEDRV.
- *          - STM32_LSE_BYPASS (optionally).
- *          - STM32_HSECLK.
- *          - STM32_HSE_BYPASS (optionally).
- *          .
- *          One of the following macros must also be defined:
- *          - STM32F030 for Value Line devices.
- *          - STM32F0XX_LD for Low Density devices.
- *          - STM32F0XX_MD for Medium Density devices.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "stm32.h"
-#include "stm32_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @name    Platform identification macros
- * @{
- */
-#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
-#define PLATFORM_NAME           "STM32F051xx/F061xx Entry Level Medium Density devices"
-#define STM32F0XX
-
-#elif defined(STM32F0XX_LD)
-#define PLATFORM_NAME           "STM32F050xx/F060xx Entry Level Low Density devices"
-#define STM32F0XX
-
-#elif defined(STM32F030)
-#define PLATFORM_NAME           "STM32F050xx/F060xx Entry Level Value Line devices"
-#define STM32F0XX
-
-#else
-#error "STM32F0xx device not specified"
-#endif
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum system clock frequency.
- */
-#define STM32_SYSCLK_MAX        48000000
-
-/**
- * @brief   Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX        32000000
-
-/**
- * @brief   Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN        1000000
-
-/**
- * @brief   Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX        1000000
-
-/**
- * @brief   Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN        32768
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MAX         25000000
-
-/**
- * @brief   Minimum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MIN         1000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MAX        48000000
-
-/**
- * @brief   Minimum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MIN        16000000
-
-/**
- * @brief   Maximum APB clock frequency.
- */
-#define STM32_PCLK_MAX          48000000
-
-/**
- * @brief   Maximum ADC clock frequency.
- */
-#define STM32_ADCCLK_MAX        14000000
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define STM32_HSICLK            8000000     /**< High speed internal clock. */
-#define STM32_HSI14CLK          14000000    /**< 14MHz speed internal clock.*/
-#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
-/** @} */
-
-/**
- * @name    PWR_CR register bits definitions
- * @{
- */
-#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
-#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
-#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
-#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
-#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
-#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
-#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
-#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
-#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
-/** @} */
-
-/**
- * @name    RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
-#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
-#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
-
-#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
-#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
-#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
-#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
-#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
-#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
-#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
-#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
-#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
-
-#define STM32_PPRE_DIV1         (0 << 8)    /**< HCLK divided by 1.         */
-#define STM32_PPRE_DIV2         (4 << 8)    /**< HCLK divided by 2.         */
-#define STM32_PPRE_DIV4         (5 << 8)    /**< HCLK divided by 4.         */
-#define STM32_PPRE_DIV8         (6 << 8)    /**< HCLK divided by 8.         */
-#define STM32_PPRE_DIV16        (7 << 8)    /**< HCLK divided by 16.        */
-
-#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PCLK divided by 2.         */
-#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PCLK divided by 4.         */
-
-#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
-#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
-
-#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
-#define STM32_MCOSEL_HSI14      (3 << 24)   /**< HSI14 clock on MCO pin.    */
-#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
-#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
-#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
-#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
-/** @} */
-
-/**
- * @name    RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
-#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
-#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
-#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
-#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 32 used as
-                                                 RTC clock.                 */
-/** @} */
-
-/**
- * @name    RCC_CFGR3 register bits definitions
- * @{
- */
-#define STM32_USART1SW_MASK     (3 << 0)    /**< USART1 clock source mask.  */
-#define STM32_USART1SW_PCLK     (0 << 0)    /**< USART1 clock is PCLK.      */
-#define STM32_USART1SW_SYSCLK   (1 << 0)    /**< USART1 clock is SYSCLK.    */
-#define STM32_USART1SW_LSE      (2 << 0)    /**< USART1 clock is LSE.       */
-#define STM32_USART1SW_HSI      (3 << 0)    /**< USART1 clock is HSI.       */
-#define STM32_I2C1SW_MASK       (1 << 4)    /**< I2C clock source mask.     */
-#define STM32_I2C1SW_HSI        (0 << 4)    /**< I2C clock is HSI.          */
-#define STM32_I2C1SW_SYSCLK     (1 << 4)    /**< I2C clock is SYSCLK.       */
-#define STM32_CECSW_MASK        (1 << 6)    /**< CEC clock source mask.     */
-#define STM32_CECSW_HSI         (0 << 6)    /**< CEC clock is HSI/244.      */
-#define STM32_CECSW_LSE         (1 << 6)    /**< CEC clock is LSE.          */
-#define STM32_ADCSW_MASK        (1 << 8)    /**< ADC clock source mask.     */
-#define STM32_ADCSW_HSI14       (0 << 8)    /**< ADC clock is HSI14.        */
-#define STM32_ADCSW_PCLK        (1 << 8)    /**< ADC clock is PCLK/2|4.     */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Disables the PWR/RCC initialization in the HAL.
- */
-#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT               FALSE
-#endif
-
-/**
- * @brief   Enables or disables the programmable voltage detector.
- */
-#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE            FALSE
-#endif
-
-/**
- * @brief   Sets voltage level for programmable voltage detector.
- */
-#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS                   STM32_PLS_LEV0
-#endif
-
-/**
- * @brief   Enables or disables the HSI clock source.
- */
-#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the HSI14 clock source.
- */
-#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI14_ENABLED         TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSI clock source.
- */
-#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED           FALSE
-#endif
-
-/**
- * @brief   Enables or disables the HSE clock source.
- */
-#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSE clock source.
- */
-#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED           FALSE
-#endif
-
-/**
- * @brief   Main clock source selection.
- * @note    If the selected clock source is not the PLL then the PLL is not
- *          initialized and started.
- * @note    The default value is calculated for a 48MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW                    STM32_SW_PLL
-#endif
-
-/**
- * @brief   Clock source for the PLL.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 48MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief   Crystal PLL pre-divider.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
-#define STM32_PREDIV_VALUE                  1
-#endif
-
-/**
- * @brief   PLL multiplier value.
- * @note    The allowed range is 2...16.
- * @note    The default value is calculated for a 48MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE          6
-#endif
-
-/**
- * @brief   AHB prescaler value.
- * @note    The default value is calculated for a 48MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE                  STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief   APB1 prescaler value.
- */
-#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
-#define STM32_PPRE                  STM32_PPRE_DIV1
-#endif
-
-/**
- * @brief   MCO pin setting.
- */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
-#endif
-
-/**
- * @brief   ADC prescaler value.
- */
-#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADCPRE                STM32_ADCPRE_DIV4
-#endif
-
-/**
- * @brief   ADC clock source.
- */
-#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
-#define STM32_ADCSW                 STM32_ADCSW_HSI14
-#endif
-
-/**
- * @brief   CEC clock source.
- */
-#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
-#define STM32_CECSW                 STM32_CECSW_HSI
-#endif
-
-/**
- * @brief   I2C1 clock source.
- */
-#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
-#define STM32_I2C1SW                STM32_I2C1SW_HSI
-#endif
-
-/**
- * @brief   USART1 clock source.
- */
-#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
-#define STM32_USART1SW              STM32_USART1SW_PCLK
-#endif
-
-/**
- * @brief   RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL                STM32_RTCSEL_LSI
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F0xx_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined"
-#endif
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if STM32_CECSW == STM32_CECSW_HSI
-#error "HSI not enabled, required by STM32_CECSW"
-#endif
-
-#if STM32_I2C1SW == STM32_I2C1SW_HSI
-#error "HSI not enabled, required by STM32_I2C1SW"
-#endif
-
-#if STM32_USART1SW == STM32_USART1SW_HSI
-#error "HSI not enabled, required by STM32_USART1SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCOSEL"
-#endif
-
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSI14 related checks.
- */
-#if STM32_HSI14_ENABLED
-#else /* !STM32_HSI14_ENABLED */
-
-#if STM32_MCOSEL == STM32_MCOSEL_HSI14
-#error "HSI14 not enabled, required by STM32_MCOSEL"
-#endif
-
-#if STM32_ADCSW == STM32_ADCSW_HSI14
-#error "HSI14 not enabled, required by STM32_ADCSW"
-#endif
-
-#endif /* !STM32_HSI14_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCOSEL"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSI
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if (STM32_LSECLK == 0)
-#error "LSE frequency not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#if !defined(STM32_LSEDRV)
-#error "STM32_LSEDRV not defined"
-#endif
-
-#if (STM32_LSEDRV >> 3) > 3
-#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
-#endif
-
-#if STM32_CECSW == STM32_CECSW_LSE
-#error "LSE not enabled, required by STM32_CECSW"
-#endif
-
-#if STM32_USART1SW == STM32_USART1SW_LSE
-#error "LSE not enabled, required by STM32_USART1SW"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/* PLL activation conditions.*/
-#if (STM32_SW == STM32_SW_PLL) ||                                           \
-    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL          TRUE
-#else
-#define STM32_ACTIVATE_PLL          FALSE
-#endif
-
-/* HSE prescaler setting check.*/
-#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
-#define STM32_PREDIV                ((STM32_PREDIV_VALUE - 1) << 0)
-#else
-#error "invalid STM32_PREDIV value specified"
-#endif
-
-/**
- * @brief   PLLMUL field.
- */
-#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
-    defined(__DOXYGEN__)
-#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
-#else
-#error "invalid STM32_PLLMUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PREDIV_VALUE)
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/* PLL input frequency range check.*/
-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
-#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
-#endif
-
-/**
- * @brief   System clock source.
- */
-#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
-#define STM32_SYSCLK                STM32_PLLCLKOUT
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/* AHB frequency check.*/
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB frequency.
- */
-#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK                  (STM32_HCLK / 1)
-#elif STM32_PPRE == STM32_PPRE_DIV2
-#define STM32_PCLK                  (STM32_HCLK / 2)
-#elif STM32_PPRE == STM32_PPRE_DIV4
-#define STM32_PCLK                  (STM32_HCLK / 4)
-#elif STM32_PPRE == STM32_PPRE_DIV8
-#define STM32_PCLK                  (STM32_HCLK / 8)
-#elif STM32_PPRE == STM32_PPRE_DIV16
-#define STM32_PCLK                  (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE value specified"
-#endif
-
-/* APB frequency check.*/
-#if STM32_PCLK > STM32_PCLK_MAX
-#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
-#endif
-
-/**
- * @brief   RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                (STM32_HSECLK / 32)
-#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
-#define STM32_RTCCLK                0
-#else
-#error "invalid source selected for RTC clock"
-#endif
-
-/**
- * @brief   ADC frequency.
- */
-#if STM32_ADCSW == STM32_ADCSW_HSI14
-#define STM32_ADCCLK                STM32_HSI14CLK
-#elif STM32_ADCSW == STM32_ADCSW_PCLK
-#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_ADCCLK                (STM32_PCLK / 2)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
-#define STM32_ADCCLK                (STM32_PCLK / 4)
-#else
-#error "invalid STM32_ADCPRE value specified"
-#endif
-#else
-#error "invalid source selected for ADC clock"
-#endif
-
-/* ADC frequency check.*/
-#if STM32_ADCCLK > STM32_ADCCLK_MAX
-#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/**
- * @brief   CEC frequency.
- */
-#if STM32_CECSW == STM32_CECSW_HSI
-#define STM32_CECCLK                STM32_HSICLK
-#elif STM32_CECSW == STM32_CECSW_LSE
-#define STM32_CECCLK                STM32_LSECLK
-#else
-#error "invalid source selected for CEC clock"
-#endif
-
-/**
- * @brief   I2C1 frequency.
- */
-#if STM32_I2CSW == STM32_I2C1SW_HSI
-#define STM32_I2C1CLK               STM32_HSICLK
-#elif STM32_I2CSW == STM32_I2C1SW_SYSCLK
-#define STM32_I2C1CLK               STM32_SYSCLK
-#else
-#error "invalid source selected for I2C1 clock"
-#endif
-
-/**
- * @brief   USART1 frequency.
- */
-#if STM32_USART1SW == STM32_USART1SW_PCLK
-#define STM32_USART1CLK             STM32_PCLK
-#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
-#define STM32_USART1CLK             STM32_SYSCLK
-#elif STM32_USART1SW == STM32_USART1SW_LSECLK
-#define STM32_USART1CLK             STM32_LSECLK
-#elif STM32_USART1SW == STM32_USART1SW_HSICLK
-#define STM32_USART1CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART1 clock"
-#endif
-
-/**
- * @brief   USART2 frequency.
- */
-#define STM32_USART2CLK             STM32_PCLK
-
-/**
- * @brief   Timers clock.
- */
-#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK * 1)
-#define STM32_TIMCLK2               (STM32_PCLK * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK * 2)
-#define STM32_TIMCLK2               (STM32_PCLK * 2)
-#endif
-
-/**
- * @brief   Flash settings.
- */
-#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS             0x00000010
-#else
-#define STM32_FLASHBITS             0x00000011
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-/* STM32 ISR, DMA and RCC helpers.*/
-#include "stm32_isr.h"
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void stm32_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/platform.dox b/os/hal/platforms/STM32F0xx/platform.dox
deleted file mode 100644
index c8caa2b89..000000000
--- a/os/hal/platforms/STM32F0xx/platform.dox
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM32F0xx_DRIVERS STM32F0xx Drivers
- * @details This section describes all the supported drivers on the STM32F0xx
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup STM32F0xx_HAL STM32F0xx Initialization Support
- * @details The STM32F0xx HAL support is responsible for system initialization.
- *
- * @section stm32f0xx_hal_1 Supported HW resources
- * - PLL1.
- * - RCC.
- * - Flash.
- * .
- * @section stm32f0xx_hal_2 STM32F0xx HAL driver implementation features
- * - PLL startup and stabilization.
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash wait states initialization based on the selected clock options.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * - DMA support initialization.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_ADC STM32F0xx ADC Support
- * @details The STM32F0xx ADC driver supports the ADC peripherals using DMA
- *          channels for maximum performance.
- *
- * @section stm32f0xx_adc_1 Supported HW resources
- * - ADC1.
- * - DMA1.
- * .
- * @section stm32f0xx_adc_2 STM32F0xx ADC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Streaming conversion using DMA for maximum performance.
- * - Programmable ADC interrupt priority level.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - DMA errors detection.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_EXT STM32F0xx EXT Support
- * @details The STM32F0xx EXT driver uses the EXTI peripheral.
- *
- * @section stm32f0xx_ext_1 Supported HW resources
- * - EXTI.
- * .
- * @section stm32f0xx_ext_2 STM32F0xx EXT driver implementation features
- * - Each EXTI channel can be independently enabled and programmed.
- * - Programmable EXTI interrupts priority level.
- * - Capability to work as event sources (WFE) rather than interrupt sources.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_GPT STM32F0xx GPT Support
- * @details The STM32F0xx GPT driver uses the TIMx peripherals.
- *
- * @section stm32f0xx_gpt_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * .
- * @section stm32f0xx_gpt_2 STM32F0xx GPT driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_ICU STM32F0xx ICU Support
- * @details The STM32F0xx ICU driver uses the TIMx peripherals.
- *
- * @section stm32f0xx_icu_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * .
- * @section stm32f0xx_icu_2 STM32F0xx ICU driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_PAL STM32F0xx PAL Support
- * @details The STM32F0xx PAL driver uses the GPIO peripherals.
- *
- * @section stm32f0xx_pal_1 Supported HW resources
- * - GPIOA.
- * - GPIOB.
- * - GPIOC.
- * - GPIOD.
- * - GPIOF.
- * .
- * @section stm32f0xx_pal_2 STM32F0xx PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 16 bits wide ports.
- * - Atomic set/reset functions.
- * - Atomic set+reset function (atomic bus operations).
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section stm32f0xx_pal_3 Supported PAL setup modes
- * The STM32F0xx PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_INPUT_PULLDOWN.
- * - @p PAL_MODE_INPUT_ANALOG.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * - @p PAL_MODE_ALTERNATE (non standard).
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section stm32f0xx_pal_4 Suboptimal behavior
- * The STM32F0xx GPIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_PWM STM32F0xx PWM Support
- * @details The STM32F0xx PWM driver uses the TIMx peripherals.
- *
- * @section stm32f0xx_pwm_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * .
- * @section stm32f0xx_pwm_2 STM32F0xx PWM driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Four independent PWM channels per timer.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_SERIAL STM32F0xx Serial Support
- * @details The STM32F0xx Serial driver uses the USART/UART peripherals in a
- *          buffered, interrupt driven, implementation.
- *
- * @section stm32f0xx_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * .
- * @section stm32f0xx_serial_2 STM32F0xx Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable priority levels for each UART/USART.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_SPI STM32F0xx SPI Support
- * @details The SPI driver supports the STM32F0xx SPI peripherals using DMA
- *          channels for maximum performance.
- *
- * @section stm32f0xx_spi_1 Supported HW resources
- * - SPI1.
- * - SPI2.
- * - DMA1.
- * .
- * @section stm32f0xx_spi_2 STM32F0xx SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SPI can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each SPI.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_UART STM32F0xx UART Support
- * @details The UART driver supports the STM32F0xx USART peripherals using DMA
- *          channels for maximum performance.
- *
- * @section stm32f0xx_uart_1 Supported HW resources
- * The UART driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - DMA1.
- * .
- * @section stm32f0xx_uart_2 STM32F0xx UART driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each UART/USART.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_PLATFORM_DRIVERS STM32F0xx Platform Drivers
- * @details Platform support drivers. Platform drivers do not implement HAL
- *          standard driver templates, their role is to support platform
- *          specific functionalities.
- *
- * @ingroup STM32F0xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_DMA STM32F0xx DMA Support
- * @details This DMA helper driver is used by the other drivers in order to
- *          access the shared DMA resources in a consistent way.
- *
- * @section stm32f0xx_dma_1 Supported HW resources
- * The DMA driver can support any of the following hardware resources:
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32f0xx_dma_2 STM32F0xx DMA driver implementation features
- * - Exports helper functions/macros to the other drivers that share the
- *   DMA resource.
- * - Automatic DMA clock stop when not in use by any driver.
- * - DMA streams and interrupt vectors sharing among multiple drivers.
- * .
- * @ingroup STM32F0xx_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_ISR STM32F0xx ISR Support
- * @details This ISR helper driver is used by the other drivers in order to
- *          map ISR names to physical vector names.
- *
- * @ingroup STM32F0xx_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup STM32F0xx_RCC STM32F0xx RCC Support
- * @details This RCC helper driver is used by the other drivers in order to
- *          access the shared RCC resources in a consistent way.
- *
- * @section stm32f0xx_rcc_1 Supported HW resources
- * - RCC.
- * .
- * @section stm32f0xx_rcc_2 STM32F0xx RCC driver implementation features
- * - Peripherals reset.
- * - Peripherals clock enable.
- * - Peripherals clock disable.
- * .
- * @ingroup STM32F0xx_PLATFORM_DRIVERS
- */
diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
deleted file mode 100644
index 00107c4d6..000000000
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-# List of all the STM32F0xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
-              ${CHIBIOS}/os/hal/platforms/STM32 \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2
diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c
deleted file mode 100644
index 167321730..000000000
--- a/os/hal/platforms/STM32F0xx/stm32_dma.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F0xx/stm32_dma.c
- * @brief   DMA helper driver code.
- *
- * @addtogroup STM32F0xx_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- *          shared resource, this driver allows to allocate and free DMA
- *          streams at runtime in order to allow all the other device
- *          drivers to coordinate the access to the resource.
- * @note    The DMA ISR handlers are all declared into this module because
- *          sharing, the various device drivers can associate a callback to
- *          ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
-   has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK     0x0000007F
-
-/**
- * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK     0x00000F80
-
-/**
- * @brief   Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE   0x00000000
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- *          identifier and the involved physical registers.
- * @note    Don't use this array directly, use the appropriate wrapper macros
- *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
-  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
-  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_3_IRQn},
-  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel2_3_IRQn},
-  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_5_IRQn},
-  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel4_5_IRQn}
-};
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DMA ISR redirector type.
- */
-typedef struct {
-  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
-  void                  *dma_param;     /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief   Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief   DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector64) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 0;
-  if (dma_isr_redir[0].dma_func)
-    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 streams 2 and 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector68) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Check on channel 2.*/
-  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = flags << 4;
-    if (dma_isr_redir[1].dma_func)
-      dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-  }
-
-  /* Check on channel 3.*/
-  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = flags << 8;
-    if (dma_isr_redir[2].dma_func)
-      dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 streams 4 and 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector6C) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Check on channel 4.*/
-  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = flags << 12;
-    if (dma_isr_redir[3].dma_func)
-      dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-  }
-
-  /* Check on channel 5.*/
-  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = flags << 16;
-    if (dma_isr_redir[4].dma_func)
-      dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
-  int i;
-
-  dma_streams_mask = 0;
-  for (i = 0; i < STM32_DMA_STREAMS; i++) {
-    _stm32_dma_streams[i].channel->CCR = 0;
-    dma_isr_redir[i].dma_func = NULL;
-  }
-  DMA1->IFCR = 0xFFFFFFFF;
-}
-
-/**
- * @brief   Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- *          The function also enables the IRQ vector associated to the stream
- *          and initializes its priority.
- * @pre     The stream must not be already in use or an error is returned.
- * @post    The stream is allocated and the default ISR handler redirected
- *          to the specified function.
- * @post    The stream ISR vector is enabled and its priority configured.
- * @post    The stream must be freed using @p dmaStreamRelease() before it can
- *          be reused with another peripheral.
- * @post    The stream is in its post-reset state.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] priority  IRQ priority mask for the DMA stream
- * @param[in] func      handling function pointer, can be @p NULL
- * @param[in] param     a parameter to be passed to the handling function
- * @return              The operation status.
- * @retval FALSE        no error, stream taken.
- * @retval TRUE         error, stream already taken.
- *
- * @special
- */
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                         uint32_t priority,
-                         stm32_dmaisr_t func,
-                         void *param) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
-
-  /* Checks if the stream is already taken.*/
-  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
-    return TRUE;
-
-  /* Marks the stream as allocated.*/
-  dma_isr_redir[dmastp->selfindex].dma_func  = func;
-  dma_isr_redir[dmastp->selfindex].dma_param = param;
-  dma_streams_mask |= (1 << dmastp->selfindex);
-
-  /* Enabling DMA clocks required by the current streams set.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
-    rccEnableDMA1(FALSE);
-
-  /* Putting the stream in a safe state.*/
-  dmaStreamDisable(dmastp);
-  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
-
-  /* Enables the associated IRQ vector if a callback is defined.*/
-  if (func != NULL)
-    nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
-
-  return FALSE;
-}
-
-/**
- * @brief   Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- *          Trying to release a unallocated stream is an illegal operation
- *          and is trapped if assertions are enabled.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    The stream is again available.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamRelease");
-
-  /* Check if the streams is not taken.*/
-  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
-              "dmaStreamRelease(), #1", "not allocated");
-
-  /* Disables the associated IRQ vector.*/
-  nvicDisableVector(dmastp->vector);
-
-  /* Marks the stream as not allocated.*/
-  dma_streams_mask &= ~(1 << dmastp->selfindex);
-
-  /* Shutting down clocks that are no more required, if any.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
-    rccDisableDMA1(FALSE);
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.h b/os/hal/platforms/STM32F0xx/stm32_dma.h
deleted file mode 100644
index 277ebf4d4..000000000
--- a/os/hal/platforms/STM32F0xx/stm32_dma.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F0xx/stm32_dma.h
- * @brief   DMA helper driver header.
- * @note    This file requires definitions from the ST header file stm32f0xx.h.
- * @note    This driver uses the new naming convention used for the STM32F2xx
- *          so the "DMA channels" are referred as "DMA streams".
- *
- * @addtogroup STM32F0xx_DMA
- * @{
- */
-
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Total number of DMA streams.
- * @note    This is the total number of streams among all the DMA units.
- */
-#define STM32_DMA_STREAMS           5
-
-/**
- * @brief   Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK          0x0F
-
-/**
- * @brief   Returns the channel associated to the specified stream.
- *
- * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
- * @param[in] c         a stream/channel association word, one channel per
- *                      nibble, not associated channels must be set to 0xF
- * @return              Always zero, in this platform there is no dynamic
- *                      association between streams and channels.
- */
-#define STM32_DMA_GETCHANNEL(n, c)  0
-
-/**
- * @brief   Checks if a DMA priority is within the valid range.
- * @param[in] prio      DMA priority
- *
- * @retval              The check result.
- * @retval FALSE        invalid DMA priority.
- * @retval TRUE         correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
-
-/**
- * @brief   Returns an unique numeric identifier for a DMA stream.
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              An unique numeric stream identifier.
- */
-#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1)
-
-/**
- * @brief   Returns a DMA stream identifier mask.
- *
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              A DMA stream identifier mask.
- */
-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
-  (1 << STM32_DMA_STREAM_ID(dma, stream))
-
-/**
- * @brief   Checks if a DMA stream unique identifier belongs to a mask.
- * @param[in] id        the stream numeric identifier
- * @param[in] mask      the stream numeric identifiers mask
- *
- * @retval              The check result.
- * @retval FALSE        id does not belong to the mask.
- * @retval TRUE         id belongs to the mask.
- */
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
-
-/**
- * @name    DMA streams identifiers
- * @{
- */
-/**
- * @brief   Returns a pointer to a stm32_dma_stream_t structure.
- *
- * @param[in] id        the stream numeric identifier
- * @return              A pointer to the stm32_dma_stream_t constant structure
- *                      associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
-/** @} */
-
-/**
- * @name    CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN             DMA_CCR_EN
-#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE
-#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE
-#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE
-#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
-#define STM32_DMA_CR_DIR_P2M        0
-#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR
-#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM
-#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC
-#define STM32_DMA_CR_PINC           DMA_CCR_PINC
-#define STM32_DMA_CR_MINC           DMA_CCR_MINC
-#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE     0
-#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE     0
-#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
-                                     STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
-#define STM32_DMA_CR_PL(n)          ((n) << 12)
-/** @} */
-
-/**
- * @name    CR register constants only found in enhanced DMA
- * @{
- */
-#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
-/** @} */
-
-/**
- * @name    Status flags passed to the ISR callbacks
- * @{
- */
-#define STM32_DMA_ISR_FEIF          0
-#define STM32_DMA_ISR_DMEIF         0
-#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
-#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
-#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA stream descriptor structure.
- */
-typedef struct {
-  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
-  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
-  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
-                                             register.                      */
-  uint8_t               selfindex;      /**< @brief Index to self in array. */
-  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
-} stm32_dma_stream_t;
-
-/**
- * @brief   STM32 DMA ISR function type.
- *
- * @param[in] p         parameter for the registered function
- * @param[in] flags     pre-shifted content of the ISR register, the bits
- *                      are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Associates a peripheral data register to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CPAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) {                              \
-  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Associates a memory destination to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CMAR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) {                                 \
-  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Sets the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] size      value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) {                         \
-  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
-}
-
-/**
- * @brief   Returns the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @return              The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
-
-/**
- * @brief   Programs the stream mode settings.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) {                                    \
-  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
-}
-
-/**
- * @brief   DMA stream enable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) {                                           \
-  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
-}
-
-/**
- * @brief   DMA stream disable.
- * @details The function disables the specified stream and then clears any
- *          pending interrupt.
- * @note    This function can be invoked in both ISR or thread context.
- * @note    Interrupts enabling flags are set to zero after this call, see
- *          bug 3607518.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) {                                          \
-  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
-                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
-  dmaStreamClearInterrupt(dmastp);                                          \
-}
-
-/**
- * @brief   DMA stream interrupt sources clear.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) {                                   \
-  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
-}
-
-/**
- * @brief   Starts a memory to memory operation using the specified stream.
- * @note    The default transfer data mode is "byte to byte" but it can be
- *          changed by specifying extra options in the @p mode parameter.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register, this value
- *                      is implicitly ORed with:
- *                      - @p STM32_DMA_CR_MINC
- *                      - @p STM32_DMA_CR_PINC
- *                      - @p STM32_DMA_CR_DIR_M2M
- *                      - @p STM32_DMA_CR_EN
- *                      .
- * @param[in] src       source address
- * @param[in] dst       destination address
- * @param[in] n         number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
-  dmaStreamSetPeripheral(dmastp, src);                                      \
-  dmaStreamSetMemory0(dmastp, dst);                                         \
-  dmaStreamSetTransactionSize(dmastp, n);                                   \
-  dmaStreamSetMode(dmastp, (mode) |                                         \
-                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
-                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
-}
-
-/**
- * @brief   Polled wait for DMA transfer end.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) {                                         \
-  while ((dmastp)->channel->CNDTR > 0)                                      \
-    ;                                                                       \
-  dmaStreamDisable(dmastp);                                                 \
-}
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dmaInit(void);
-  bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                           uint32_t priority,
-                           stm32_dmaisr_t func,
-                           void *param);
-  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/stm32_registry.h b/os/hal/platforms/STM32F0xx/stm32_registry.h
deleted file mode 100644
index e56f7df50..000000000
--- a/os/hal/platforms/STM32F0xx/stm32_registry.h
+++ /dev/null
@@ -1,414 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F0xx/stm32_registry.h
- * @brief   STM32F0xx capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _STM32_REGISTRY_H_
-#define _STM32_REGISTRY_H_
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    STM32F0xx capabilities
- * @{
- */
-#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
-
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_ADC1_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC2          FALSE
-#define STM32_HAS_ADC3          FALSE
-#define STM32_HAS_ADC4          FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          FALSE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         FALSE
-#define STM32_HAS_GPIOF         TRUE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#define STM32_RTC_IS_CALENDAR   TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          FALSE
-#define STM32_HAS_SPI4          FALSE
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          FALSE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          FALSE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         TRUE
-#define STM32_HAS_TIM15         TRUE
-#define STM32_HAS_TIM16         TRUE
-#define STM32_HAS_TIM17         TRUE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        FALSE
-#define STM32_HAS_UART4         FALSE
-#define STM32_HAS_UART5         FALSE
-#define STM32_HAS_USART6        FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB           TRUE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-
-#elif defined(STM32F0XX_LD)
-
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_ADC1_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC2          FALSE
-#define STM32_HAS_ADC3          FALSE
-#define STM32_HAS_ADC4          FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          FALSE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         FALSE
-#define STM32_HAS_GPIOE         FALSE
-#define STM32_HAS_GPIOF         TRUE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          FALSE
-#define STM32_HAS_I2C3          FALSE
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#define STM32_RTC_IS_CALENDAR   TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          FALSE
-#define STM32_HAS_SPI3          FALSE
-#define STM32_HAS_SPI4          FALSE
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          FALSE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          FALSE
-#define STM32_HAS_TIM7          FALSE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         TRUE
-#define STM32_HAS_TIM15         FALSE
-#define STM32_HAS_TIM16         TRUE
-#define STM32_HAS_TIM17         TRUE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        FALSE
-#define STM32_HAS_USART3        FALSE
-#define STM32_HAS_UART4         FALSE
-#define STM32_HAS_UART5         FALSE
-#define STM32_HAS_USART6        FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB           FALSE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-
-#else /* STM32F030 */
-
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_ADC1_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC2          FALSE
-#define STM32_HAS_ADC3          FALSE
-#define STM32_HAS_ADC4          FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          FALSE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         FALSE
-#define STM32_HAS_GPIOF         TRUE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#define STM32_RTC_IS_CALENDAR   TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          FALSE
-#define STM32_HAS_SPI4          FALSE
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          FALSE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          FALSE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          FALSE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         TRUE
-#define STM32_HAS_TIM15         TRUE
-#define STM32_HAS_TIM16         TRUE
-#define STM32_HAS_TIM17         TRUE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        FALSE
-#define STM32_HAS_UART4         FALSE
-#define STM32_HAS_UART5         FALSE
-#define STM32_HAS_USART6        FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB           TRUE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-
-#endif /* STM32F030 */
-
-/** @} */
-
-#endif /* _STM32_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/stm32f0xx.h b/os/hal/platforms/STM32F0xx/stm32f0xx.h
deleted file mode 100644
index 8c03ef180..000000000
--- a/os/hal/platforms/STM32F0xx/stm32f0xx.h
+++ /dev/null
@@ -1,3295 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx.h
-  * @author  MCD Application Team
-  * @version V1.2.1
-  * @date    22-November-2013
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32F0xx devices.  
-  *          
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_STDPERIPH_DRIVER"
-  *              - To change few application-specific parameters such as the HSE 
-  *                crystal frequency
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx
-  * @{
-  */
-    
-#ifndef __STM32F0XX_H
-#define __STM32F0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/* Uncomment the line below according to the target STM32F0 device used in your 
-   application 
-  */
-
-#if !defined (STM32F0XX_LD)  && !defined (STM32F0XX_MD) && !defined (STM32F030)
-  /* #define STM32F0XX_LD */ /*!< STM32F0xx Low-density devices are STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes */
-  /* #define STM32F0XX_MD */     /*!< STM32F0xx Medium-density devices are STM32F051xx and STM32F061xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes */  
-    #define STM32F030  /*!< STM32F030 devices are STM32F030xx value line microcontrollers */
-#endif
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-
-/* Old STM32F0XX definition, maintained for legacy purpose */
-#if defined(STM32F0XX)
-  #define STM32F0XX_MD
-#endif /* STM32F0XX */
-
-/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
-#if defined (STM32F030X8) || defined (STM32F030X6)
-  #define    STM32F030
-#endif /* STM32F030X8 or  STM32F030X6 */
-
-#if !defined (STM32F0XX_LD)  && !defined (STM32F0XX_MD) && !defined (STM32F030)
- #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
-#endif
-
-#if !defined  USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_STDPERIPH_DRIVER*/
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application 
-   
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */
-#if !defined  (HSE_VALUE)     
-#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
-#endif /* HSE_VALUE */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-   Timeout value 
-   */
-#if !defined  (HSE_STARTUP_TIMEOUT)
-#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-   Timeout value 
-   */
-#if !defined  (HSI_STARTUP_TIMEOUT)
-#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
-
-#if !defined  (HSI_VALUE) 
-#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI_VALUE */
-
-#if !defined  (HSI14_VALUE) 
-#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI14_VALUE */
-
-#if !defined  (LSI_VALUE) 
-#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* LSI_VALUE */
-
-#if !defined  (LSE_VALUE) 
-#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
- * @brief STM32F0xx Standard Peripheral Library version number V1.2.1
-   */
-#define __STM32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
-#define __STM32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F0XX_STDPERIPH_VERSION        ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
-                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
-                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
-                                             |(__STM32F0XX_STDPERIPH_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief STM32F0xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
-#define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
-
-/*!< Interrupt Number Definition */
-typedef enum IRQn
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
-#if defined (STM32F0XX_MD)
-/******  STM32F0XX_MD  specific Interrupt Numbers ****************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TS_IRQn                     = 8,      /*!< Touch sense controller Interrupt                        */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
-  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
-  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
-  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
-  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  CEC_IRQn                    = 30      /*!< CEC Interrupt                                           */
-#elif defined (STM32F0XX_LD)
-/******  STM32F0XX_LD specific Interrupt Numbers *****************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
-  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
-  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
-  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
-  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
-  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  USART1_IRQn                 = 27      /*!< USART1 Interrupt                                        */
-#elif defined (STM32F030)
-/******  STM32F030 specific Interrupt Numbers ********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
-  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
-  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
-  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
-  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
-  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
-  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28      /*!< USART2 Interrupt                                        */
-#endif /* STM32F0XX_MD */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0.h"
-/* CHIBIOS FIX */
-/*#include "system_stm32f0xx.h"*/
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief HDMI-CEC 
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
-  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
-  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
-  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
-  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
-  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x1C */
-} COMP_TypeDef;
-
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;       /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;      /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t   RESERVED0;    /*!< Reserved,                                                    0x05 */
-  uint16_t  RESERVED1;    /*!< Reserved,                                                    0x06 */
-  __IO uint32_t CR;       /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t  RESERVED2;    /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;     /*!< Initial CRC value register,                  Address offset: 0x10 */
-} CRC_TypeDef;
-
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-       uint32_t RESERVED[6];  /*!< Reserved,                                                                 0x14 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-       uint32_t RESERVED1;    /*!< Reserved,                                                                 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
-  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
-  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
-  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
-  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
-  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
-  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
-  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
-  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
-  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
-  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
-  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
-  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-/* CHIBIOS FIX */
-#if 0
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
-  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
-  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
-  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
-  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
-  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
-  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
-  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
-  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
-}GPIO_TypeDef;
-#endif
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */
-       uint32_t RESERVED;    /*!< Reserved,                                                                  0x04 */
-  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration register,     Address offset: 0x14-0x08 */
-  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                           Address offset: 0x18 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
-  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
-  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
-  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
-  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
-  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
-  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
-  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
-  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
-  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
-  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{                           
-  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
-       uint32_t RESERVED0;  /*!< Reserved,                                                 Address offset: 0x14 */
-       uint32_t RESERVED1;  /*!< Reserved,                                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
-       uint32_t RESERVED2;  /*!< Reserved,                                                 Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CAL;        /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-       uint32_t RESERVED3;  /*!< Reserved,                                                 Address offset: 0x48 */
-       uint32_t RESERVED4;  /*!< Reserved,                                                 Address offset: 0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-  
-typedef struct
-{
-  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
-  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
-  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
-  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
-  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
-  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
-  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
-  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
-  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
-} SPI_TypeDef;
-
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
-  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
-  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
-  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
-  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
-  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
-  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
-  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
-  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
-  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
-  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
-  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
-  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
-  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
-  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
-  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
-  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
-  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
-  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
-  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
-  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
-  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
-  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
-  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
-  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
-  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
-  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
-  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
-  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
-  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
-  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
-  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
-  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
-  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
-  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
-  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< TSC control register,                                     Address offset: 0x00 */
-  __IO uint32_t IER;       /*!< TSC interrupt enable register,                            Address offset: 0x04 */
-  __IO uint32_t ICR;       /*!< TSC interrupt clear register,                             Address offset: 0x08 */ 
-  __IO uint32_t ISR;       /*!< TSC interrupt status register,                            Address offset: 0x0C */
-  __IO uint32_t IOHCR;     /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
-  __IO uint32_t RESERVED1; /*!< Reserved,                                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;    /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
-  __IO uint32_t RESERVED2; /*!< Reserved,                                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;     /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
-  __IO uint32_t RESERVED3; /*!< Reserved,                                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;     /*!< TSC I/O channel control register,                         Address offset: 0x28 */
-  __IO uint32_t RESERVED4; /*!< Reserved,                                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;    /*!< TSC I/O group control status register,                    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register,                         Address offset: 0x34-48 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-  
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
-  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
-  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
-  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
-} USART_TypeDef;
-
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
-#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
-#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400)
-#define CEC_BASE              (APBPERIPH_BASE + 0x00007800)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
-#define COMP_BASE             (APBPERIPH_BASE + 0x0001001C)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708)
-#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
-#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
-#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
-#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
-
-#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
-#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
-#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
-#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
-#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP                ((COMP_TypeDef *) COMP_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
-#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
-#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
-#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
-#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
-#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
-#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
-#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
-#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
-#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
-#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
-#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
-#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
-#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
-#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
-#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
-#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
-#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
-#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
-#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
-#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
-#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
-#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
-#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
-#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
-#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
-#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
-#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
-#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
-#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
-#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
-#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define  ADC_CFGR2_JITOFFDIV4                 ((uint32_t)0x80000000)       /*!< Jitter Off when ADC clocked by PCLK div4 */
-#define  ADC_CFGR2_JITOFFDIV2                 ((uint32_t)0x40000000)       /*!< Jitter Off when ADC clocked by PCLK div2 */
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define  ADC_SMPR1_SMPR                      ((uint32_t)0x00000007)        /*!< SMPR[2:0] bits (Sampling time selection) */
-#define  ADC_SMPR1_SMPR_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMPR_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMPR_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
-#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
-#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
-#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
-#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
-#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
-#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
-#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
-#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
-#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
-#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
-#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
-#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
-#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
-#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
-#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
-#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
-#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
-#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
-#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
-#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 HDMI-CEC (CEC)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                         */
-#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message            */
-#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message              */
-
-/*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time               */
-#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                      */
-#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                        */
-#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation    */
-#define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation   */
-#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast no Error generation  */
-#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional      */
-#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                    */
-#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                    */
-
-/*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                        */
-
-/*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                        */
-
-/*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                   */
-#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                   */
-#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                         */
-#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                */
-#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error          */
-#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error           */
-#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge             */
-#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                   */
-#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                    */
-#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                */
-#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                 */
-#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                           */
-#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge             */
-
-/*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable         */
-#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable         */
-#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable               */
-#define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable      */
-#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable*/
-#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable */
-#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable   */
-#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable         */
-#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable         */
-#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable      */
-#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable       */
-#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                 */
-#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/***********************  Bit definition for COMP_CSR register  ***************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< SW1 switch control */
-#define COMP_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
-#define COMP_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
-#define COMP_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
-#define COMP_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
-#define COMP_CSR_COMP1OUTSEL           ((uint32_t)0x00000700) /*!< COMP1 output select */
-#define COMP_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
-#define COMP_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
-#define COMP_CSR_COMP1OUTSEL_2         ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
-#define COMP_CSR_COMP1POL              ((uint32_t)0x00000800) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1HYST             ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
-#define COMP_CSR_COMP1HYST_0           ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
-#define COMP_CSR_COMP1HYST_1           ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
-#define COMP_CSR_COMP1OUT              ((uint32_t)0x00004000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK             ((uint32_t)0x00008000) /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN               ((uint32_t)0x00010000) /*!< COMP2 enable */
-#define COMP_CSR_COMP2MODE             ((uint32_t)0x000C0000) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2MODE_0           ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
-#define COMP_CSR_COMP2MODE_1           ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
-#define COMP_CSR_COMP2INSEL            ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INSEL_0          ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INSEL_1          ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INSEL_2          ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_WNDWEN                ((uint32_t)0x00800000) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP2OUTSEL           ((uint32_t)0x07000000) /*!< COMP2 output select */
-#define COMP_CSR_COMP2OUTSEL_0         ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
-#define COMP_CSR_COMP2OUTSEL_1         ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
-#define COMP_CSR_COMP2OUTSEL_2         ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
-#define COMP_CSR_COMP2POL              ((uint32_t)0x08000000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2HYST             ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
-#define COMP_CSR_COMP2HYST_0           ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
-#define COMP_CSR_COMP2HYST_1           ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
-#define COMP_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
-#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
-#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA Underrun Interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!<DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)         /*!<DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!<DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
-#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
-#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
-#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
-#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
-#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
-#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
-#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
-
-#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
-#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
-#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
-#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
-
-#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
-#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
-#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
-#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
-#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
-
-#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
-
-/******************  Bit definition for FLASH_KEYR register  ******************/
-#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
-
-/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
-
-/******************  FLASH Keys  **********************************************/
-#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
-#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
-                                                                                to unlock the write access to the FPEC. */
-                                                               
-#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
-#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
-                                                                                unlock the write access to the option byte block */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
-#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000010)        /*!< Write Protection Error */
-#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
-
-/*******************  Bit definition for FLASH_CR register  *******************/
-#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
-#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
-#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
-#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
-#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
-#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
-#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
-#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
-#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
-#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
-#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
-
-/*******************  Bit definition for FLASH_AR register  *******************/
-#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
-#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
-#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */
-
-#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
-#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
-#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
-#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
-
-/* Old BOOT1 bit definition, maintained for legacy purpose */
-#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
-
-/* Old OBR_VDDA bit definition, maintained for legacy purpose */
-#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR_WRP                      ((uint32_t)0x0000FFFF)        /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for OB_RDP register  **********************/
-#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
-#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
-
-/******************  Bit definition for OB_USER register  *********************/
-#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
-#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
-
-/******************  Bit definition for OB_WRP0 register  *********************/
-#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for OB_WRP1 register  *********************/
-#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
-#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
-#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
-#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
-#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
-#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
-#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
-#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
-#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
-#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
-#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
-#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
-#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
-#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
-#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
-#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_0                 ((uint32_t)0x00000001)
-#define GPIO_IDR_1                 ((uint32_t)0x00000002)
-#define GPIO_IDR_2                 ((uint32_t)0x00000004)
-#define GPIO_IDR_3                 ((uint32_t)0x00000008)
-#define GPIO_IDR_4                 ((uint32_t)0x00000010)
-#define GPIO_IDR_5                 ((uint32_t)0x00000020)
-#define GPIO_IDR_6                 ((uint32_t)0x00000040)
-#define GPIO_IDR_7                 ((uint32_t)0x00000080)
-#define GPIO_IDR_8                 ((uint32_t)0x00000100)
-#define GPIO_IDR_9                 ((uint32_t)0x00000200)
-#define GPIO_IDR_10                ((uint32_t)0x00000400)
-#define GPIO_IDR_11                ((uint32_t)0x00000800)
-#define GPIO_IDR_12                ((uint32_t)0x00001000)
-#define GPIO_IDR_13                ((uint32_t)0x00002000)
-#define GPIO_IDR_14                ((uint32_t)0x00004000)
-#define GPIO_IDR_15                ((uint32_t)0x00008000)
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_0                 ((uint32_t)0x00000001)
-#define GPIO_ODR_1                 ((uint32_t)0x00000002)
-#define GPIO_ODR_2                 ((uint32_t)0x00000004)
-#define GPIO_ODR_3                 ((uint32_t)0x00000008)
-#define GPIO_ODR_4                 ((uint32_t)0x00000010)
-#define GPIO_ODR_5                 ((uint32_t)0x00000020)
-#define GPIO_ODR_6                 ((uint32_t)0x00000040)
-#define GPIO_ODR_7                 ((uint32_t)0x00000080)
-#define GPIO_ODR_8                 ((uint32_t)0x00000100)
-#define GPIO_ODR_9                 ((uint32_t)0x00000200)
-#define GPIO_ODR_10                ((uint32_t)0x00000400)
-#define GPIO_ODR_11                ((uint32_t)0x00000800)
-#define GPIO_ODR_12                ((uint32_t)0x00001000)
-#define GPIO_ODR_13                ((uint32_t)0x00002000)
-#define GPIO_ODR_14                ((uint32_t)0x00004000)
-#define GPIO_ODR_15                ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
-#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
-#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
-#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
-#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
-#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
-#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
-#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
-#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
-#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
-#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
-#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
-#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
-#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
-#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
-#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
-#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
-#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
-#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
-#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
-#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
-#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
-#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
-#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
-#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
-#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
-#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
-#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
-#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
-#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
-#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
-#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
-#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
-#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
-#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
-#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
-#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
-#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
-#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
-#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
-#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
-#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
-#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
-#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
-#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
-#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
-#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
-#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
-#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
-#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
-#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
-#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
-#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
-#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
-#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
-#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
-#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
-#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
-#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
-#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
-
-#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
-#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE configuration */
-#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
-#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-/*!< ADCPPRE configuration */
-#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADCPRE bit (ADC prescaler) */
-
-#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK divided by 2 */
-#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK divided by 4 */
-
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-#define  RCC_CFGR_PLLSRC_HSI_Div2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
-#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
-
-#define  RCC_CFGR_PLLMULL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
-#define  RCC_CFGR_PLLMULL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
-#define  RCC_CFGR_PLLMULL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
-#define  RCC_CFGR_PLLMULL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
-#define  RCC_CFGR_PLLMULL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
-#define  RCC_CFGR_PLLMULL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
-#define  RCC_CFGR_PLLMULL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
-#define  RCC_CFGR_PLLMULL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
-#define  RCC_CFGR_PLLMULL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
-#define  RCC_CFGR_PLLMULL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
-#define  RCC_CFGR_PLLMULL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
-#define  RCC_CFGR_PLLMULL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
-#define  RCC_CFGR_PLLMULL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
-#define  RCC_CFGR_PLLMULL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
-#define  RCC_CFGR_PLLMULL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
-
-/*!< MCO configuration */
-#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
-#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
-#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
-#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
-#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
-#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
-#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
-
-#define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-#define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-#define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-#define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-#define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-#define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-#define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-#define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-#define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-
-#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO (only for STM32F0XX_LD and STM32FO30X6 devices) */
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
-#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 clock reset */
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
-#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
-#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
-#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
-#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
-#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
-#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
-#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
-#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
-#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
-#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
-#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
-#define  RCC_AHBENR_TSEN                     ((uint32_t)0x01000000)        /*!< TS clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
-#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
-#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
-#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
-#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
-#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
-
-/*******************  Bit definition for RCC_BDCR register  *******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
-
-#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-
-#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
-
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
-
-/*******************  Bit definition for RCC_CSR register  ********************/  
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-#define  RCC_CSR_V18PWRRSTF                 ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_OBL                         ((uint32_t)0x02000000)        /*!< OBL reset flag */
-#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-/*******************  Bit definition for RCC_AHBRSTR register  ****************/
-#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
-#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
-#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
-#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
-#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
-#define  RCC_AHBRSTR_TSRST                   ((uint32_t)0x00100000)         /*!< TS clock reset */
-
-/*******************  Bit definition for RCC_CFGR2 register  ******************/
-/*!< PREDIV1 configuration */
-#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
-#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
-#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
-#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
-#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
-#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
-#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
-#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
-#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
-#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
-#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
-#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
-#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
-#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
-#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
-#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
-#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
-
-/*******************  Bit definition for RCC_CFGR3 register  ******************/
-/*!< USART1 Clock source selection */
-#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
-#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-/*!< I2C1 Clock source selection */
-#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 
-#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */ 
-#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */ 
-
-/*******************  Bit definition for RCC_CR2 register  ********************/
-#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
-#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
-#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
-#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
-#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_CALSEL                        ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CAL_CALP                         ((uint32_t)0x00008000)
-#define RTC_CAL_CALW8                        ((uint32_t)0x00004000)
-#define RTC_CAL_CALW16                       ((uint32_t)0x00002000)
-#define RTC_CAL_CALM                         ((uint32_t)0x000001FF)
-#define RTC_CAL_CALM_0                       ((uint32_t)0x00000001)
-#define RTC_CAL_CALM_1                       ((uint32_t)0x00000002)
-#define RTC_CAL_CALM_2                       ((uint32_t)0x00000004)
-#define RTC_CAL_CALM_3                       ((uint32_t)0x00000008)
-#define RTC_CAL_CALM_4                       ((uint32_t)0x00000010)
-#define RTC_CAL_CALM_5                       ((uint32_t)0x00000020)
-#define RTC_CAL_CALM_6                       ((uint32_t)0x00000040)
-#define RTC_CAL_CALM_7                       ((uint32_t)0x00000080)
-#define RTC_CAL_CALM_8                       ((uint32_t)0x00000100)
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
-#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
-#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
-#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
-#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
-#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
-#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
-#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
-#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
-#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
-#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
-#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
-#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
-#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
-#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
-#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
-#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
-#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
-#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
-#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
-#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
-#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
-#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
-#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
-#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0XX_LD and STM32FO30X6 devices) */
-#define SYSCFG_CFGR1_I2C_FMP_PA9            ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F0XX_LD and STM32FO30X6 devices) */
-#define SYSCFG_CFGR1_I2C_FMP_PA10           ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F0XX_LD and STM32FO30X6 devices) */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0003) /*!< PF[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0030) /*!< PF[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0003) /*!< PF[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0030) /*!< PF[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0300) /*!< PF[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x3000) /*!< PF[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_SRAM_PE                   ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
-#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
-#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
-#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
-
-#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
-#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
-#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
-#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
-#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-
-#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
-#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
-#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
-#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
-#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
-#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
-#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
-#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
-#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
-#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
-#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
-#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
-#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
-#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
-#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
-#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
-#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
-#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
-#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
-#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
-#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
-#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
-#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
-#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
-#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
-#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
-#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
-#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
-#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
-#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
-#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
-#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
-#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
-#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
-#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
-#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
-#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
-#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
-#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
-#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
-#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
-#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
-#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
-#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
-#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
-#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
-#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
-#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
-#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
-#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
-#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
-#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
-#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
-#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
-#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
-#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
-#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
-#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
-#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
-#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
-#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
-#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
-#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
-#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
-#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
-#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
-#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
-#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
-#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
-#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
-#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
-#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
-#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
-#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
-#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
-#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
-#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
-#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
-#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
-#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
-#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-
-#ifdef USE_STDPERIPH_DRIVER
-  #include "stm32f0xx_conf.h"
-#endif
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM32F1xx/adc_lld.c b/os/hal/platforms/STM32F1xx/adc_lld.c
deleted file mode 100644
index 926fb9c5a..000000000
--- a/os/hal/platforms/STM32F1xx/adc_lld.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F1xx/adc_lld.c
- * @brief   STM32F1xx ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Shared ADC DMA ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-  if ((flags & STM32_DMA_ISR_TEIF) != 0) {
-    /* DMA, this could help only if the DMA tries to access an unmapped
-       address space or violates alignment rules.*/
-    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
-  }
-  else {
-    if ((flags & STM32_DMA_ISR_TCIF) != 0) {
-      /* Transfer complete processing.*/
-      _adc_isr_full_code(adcp);
-    }
-    else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-      /* Half transfer processing.*/
-      _adc_isr_half_code(adcp);
-    }
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if STM32_ADC_USE_ADC1
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-  ADCD1.adc = ADC1;
-  ADCD1.dmastp  = STM32_DMA1_STREAM1;
-  ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_TEIE;
-
-  /* Temporary activation.*/
-  rccEnableADC1(FALSE);
-  ADC1->CR1 = 0;
-  ADC1->CR2 = ADC_CR2_ADON;
-
-  /* Reset calibration just to be safe.*/
-  ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
-  while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
-    ;
-
-  /* Calibration.*/
-  ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
-  while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
-    ;
-
-  /* Return the ADC in low power mode.*/
-  ADC1->CR2 = 0;
-  rccDisableADC1(FALSE);
-#endif
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  /* If in stopped state then enables the ADC and DMA clocks.*/
-  if (adcp->state == ADC_STOP) {
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-      bool_t b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC1_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
-                            (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
-      rccEnableADC1(FALSE);
-    }
-#endif
-
-    /* ADC setup, the calibration procedure has already been performed
-       during initialization.*/
-    adcp->adc->CR1 = 0;
-    adcp->adc->CR2 = 0;
-  }
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  /* If in ready state then disables the ADC clock.*/
-  if (adcp->state == ADC_READY) {
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-      ADC1->CR1 = 0;
-      ADC1->CR2 = 0;
-      dmaStreamRelease(adcp->dmastp);
-      rccDisableADC1(FALSE);
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t mode, cr2;
-  const ADCConversionGroup *grpp = adcp->grpp;
-
-  /* DMA setup.*/
-  mode = adcp->dmamode;
-  if (grpp->circular) {
-    mode |= STM32_DMA_CR_CIRC;
-    if (adcp->depth > 1) {
-      /* If circular buffer depth > 1, then the half transfer interrupt
-         is enabled in order to allow streaming processing.*/
-      mode |= STM32_DMA_CR_HTIE;
-    }
-  }
-  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
-  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
-                                            (uint32_t)adcp->depth);
-  dmaStreamSetMode(adcp->dmastp, mode);
-  dmaStreamEnable(adcp->dmastp);
-
-  /* ADC setup.*/
-  adcp->adc->CR1   = grpp->cr1 | ADC_CR1_SCAN;
-  cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
-  if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0)
-    cr2 |= ADC_CR2_CONT;
-  adcp->adc->CR2   = grpp->cr2 | cr2;
-  adcp->adc->SMPR1 = grpp->smpr1;
-  adcp->adc->SMPR2 = grpp->smpr2;
-  adcp->adc->SQR1  = grpp->sqr1;
-  adcp->adc->SQR2  = grpp->sqr2;
-  adcp->adc->SQR3  = grpp->sqr3;
-
-  /* ADC start by writing ADC_CR2_ADON a second time.*/
-  adcp->adc->CR2   = cr2;
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-  dmaStreamDisable(adcp->dmastp);
-  adcp->adc->CR2 = 0;
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/adc_lld.h b/os/hal/platforms/STM32F1xx/adc_lld.h
deleted file mode 100644
index a4966d99d..000000000
--- a/os/hal/platforms/STM32F1xx/adc_lld.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F1xx/adc_lld.h
- * @brief   STM32F1xx ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Triggers selection
- * @{
- */
-#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 17) /**< @brief Trigger source.     */
-#define ADC_CR2_EXTSEL_SWSTART  (7 << 17)   /**< @brief Software trigger.   */
-/** @} */
-
-/**
- * @name    Available analog channels
- * @{
- */
-#define ADC_CHANNEL_IN0         0   /**< @brief External analog input 0.    */
-#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
-#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
-#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
-#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
-#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
-#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
-#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
-#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
-#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
-#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
-#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
-#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
-#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
-#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
-#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
-#define ADC_CHANNEL_SENSOR      16  /**< @brief Internal temperature sensor.*/
-#define ADC_CHANNEL_VREFINT     17  /**< @brief Internal reference.         */
-/** @} */
-
-/**
- * @name    Sampling rates
- * @{
- */
-#define ADC_SAMPLE_1P5          0   /**< @brief 1.5 cycles sampling time.   */
-#define ADC_SAMPLE_7P5          1   /**< @brief 7.5 cycles sampling time.   */
-#define ADC_SAMPLE_13P5         2   /**< @brief 13.5 cycles sampling time.  */
-#define ADC_SAMPLE_28P5         3   /**< @brief 28.5 cycles sampling time.  */
-#define ADC_SAMPLE_41P5         4   /**< @brief 41.5 cycles sampling time.  */
-#define ADC_SAMPLE_55P5         5   /**< @brief 55.5 cycles sampling time.  */
-#define ADC_SAMPLE_71P5         6   /**< @brief 71.5 cycles sampling time.  */
-#define ADC_SAMPLE_239P5        7   /**< @brief 239.5 cycles sampling time. */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1                  FALSE
-#endif
-
-/**
- * @brief   ADC1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_PRIORITY         2
-#endif
-
-/**
- * @brief   ADC1 interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_IRQ_PRIORITY         5
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
-#error "ADC1 not present in the selected device"
-#endif
-
-#if !STM32_ADC_USE_ADC1
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_DMAFAILURE = 0                    /**< DMA operations failure.    */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    The use of this configuration structure requires knowledge of
- *          STM32 ADC cell registers interface, please refer to the STM32
- *          reference manual for details.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   ADC CR1 register initialization data.
-   * @note    All the required bits must be defined into this field except
-   *          @p ADC_CR1_SCAN that is enforced inside the driver.
-   */
-  uint32_t                  cr1;
-  /**
-   * @brief   ADC CR2 register initialization data.
-   * @note    All the required bits must be defined into this field except
-   *          @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
-   *          enforced inside the driver.
-   */
-  uint32_t                  cr2;
-  /**
-   * @brief   ADC SMPR1 register initialization data.
-   * @details In this field must be specified the sample times for channels
-   *          10...17.
-   */
-  uint32_t                  smpr1;
-  /**
-   * @brief   ADC SMPR2 register initialization data.
-   * @details In this field must be specified the sample times for channels
-   *          0...9.
-   */
-  uint32_t                  smpr2;
-  /**
-   * @brief   ADC SQR1 register initialization data.
-   * @details Conversion group sequence 13...16 + sequence length.
-   */
-  uint32_t                  sqr1;
-  /**
-   * @brief   ADC SQR2 register initialization data.
-   * @details Conversion group sequence 7...12.
-   */
-  uint32_t                  sqr2;
-  /**
-   * @brief   ADC SQR3 register initialization data.
-   * @details Conversion group sequence 1...6.
-   */
-  uint32_t                  sqr3;
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the ADCx registers block.
-   */
-  ADC_TypeDef               *adc;
-  /**
-   * @brief Pointer to associated DMA channel.
-   */
-  const stm32_dma_stream_t  *dmastp;
-  /**
-   * @brief DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Sequences building helper macros
- * @{
- */
-/**
- * @brief   Number of channels in a conversion sequence.
- */
-#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
-
-#define ADC_SQR3_SQ1_N(n)       ((n) << 0)  /**< @brief 1st channel in seq. */
-#define ADC_SQR3_SQ2_N(n)       ((n) << 5)  /**< @brief 2nd channel in seq. */
-#define ADC_SQR3_SQ3_N(n)       ((n) << 10) /**< @brief 3rd channel in seq. */
-#define ADC_SQR3_SQ4_N(n)       ((n) << 15) /**< @brief 4th channel in seq. */
-#define ADC_SQR3_SQ5_N(n)       ((n) << 20) /**< @brief 5th channel in seq. */
-#define ADC_SQR3_SQ6_N(n)       ((n) << 25) /**< @brief 6th channel in seq. */
-
-#define ADC_SQR2_SQ7_N(n)       ((n) << 0)  /**< @brief 7th channel in seq. */
-#define ADC_SQR2_SQ8_N(n)       ((n) << 5)  /**< @brief 8th channel in seq. */
-#define ADC_SQR2_SQ9_N(n)       ((n) << 10) /**< @brief 9th channel in seq. */
-#define ADC_SQR2_SQ10_N(n)      ((n) << 15) /**< @brief 10th channel in seq.*/
-#define ADC_SQR2_SQ11_N(n)      ((n) << 20) /**< @brief 11th channel in seq.*/
-#define ADC_SQR2_SQ12_N(n)      ((n) << 25) /**< @brief 12th channel in seq.*/
-
-#define ADC_SQR1_SQ13_N(n)      ((n) << 0)  /**< @brief 13th channel in seq.*/
-#define ADC_SQR1_SQ14_N(n)      ((n) << 5)  /**< @brief 14th channel in seq.*/
-#define ADC_SQR1_SQ15_N(n)      ((n) << 10) /**< @brief 15th channel in seq.*/
-#define ADC_SQR1_SQ16_N(n)      ((n) << 15) /**< @brief 16th channel in seq.*/
-/** @} */
-
-/**
- * @name    Sampling rate settings helper macros
- * @{
- */
-#define ADC_SMPR2_SMP_AN0(n)    ((n) << 0)  /**< @brief AN0 sampling time.  */
-#define ADC_SMPR2_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
-#define ADC_SMPR2_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
-#define ADC_SMPR2_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
-#define ADC_SMPR2_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
-#define ADC_SMPR2_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
-#define ADC_SMPR2_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
-#define ADC_SMPR2_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
-#define ADC_SMPR2_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
-#define ADC_SMPR2_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
-
-#define ADC_SMPR1_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
-#define ADC_SMPR1_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
-#define ADC_SMPR1_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
-#define ADC_SMPR1_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
-#define ADC_SMPR1_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
-#define ADC_SMPR1_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
-#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
-                                                 sampling time.             */
-#define ADC_SMPR1_SMP_VREF(n)   ((n) << 21) /**< @brief Voltage Reference
-                                                 sampling time.             */
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/ext_lld_isr.c b/os/hal/platforms/STM32F1xx/ext_lld_isr.c
deleted file mode 100644
index ee4236c9b..000000000
--- a/os/hal/platforms/STM32F1xx/ext_lld_isr.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F1xx/ext_lld_isr.c
- * @brief   STM32F1xx EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTI[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI0_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 0);
-  EXTD1.config->channels[0].cb(&EXTD1, 0);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI1_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 1);
-  EXTD1.config->channels[1].cb(&EXTD1, 1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[2] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI2_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 2);
-  EXTD1.config->channels[2].cb(&EXTD1, 2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[3] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI3_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 3);
-  EXTD1.config->channels[3].cb(&EXTD1, 3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[4] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI4_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 4);
-  EXTD1.config->channels[4].cb(&EXTD1, 4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[5]...EXTI[9] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
-  EXTI->PR = pr;
-  if (pr & (1 << 5))
-    EXTD1.config->channels[5].cb(&EXTD1, 5);
-  if (pr & (1 << 6))
-    EXTD1.config->channels[6].cb(&EXTD1, 6);
-  if (pr & (1 << 7))
-    EXTD1.config->channels[7].cb(&EXTD1, 7);
-  if (pr & (1 << 8))
-    EXTD1.config->channels[8].cb(&EXTD1, 8);
-  if (pr & (1 << 9))
-    EXTD1.config->channels[9].cb(&EXTD1, 9);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[10]...EXTI[15] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
-                   (1 << 15));
-  EXTI->PR = pr;
-  if (pr & (1 << 10))
-    EXTD1.config->channels[10].cb(&EXTD1, 10);
-  if (pr & (1 << 11))
-    EXTD1.config->channels[11].cb(&EXTD1, 11);
-  if (pr & (1 << 12))
-    EXTD1.config->channels[12].cb(&EXTD1, 12);
-  if (pr & (1 << 13))
-    EXTD1.config->channels[13].cb(&EXTD1, 13);
-  if (pr & (1 << 14))
-    EXTD1.config->channels[14].cb(&EXTD1, 14);
-  if (pr & (1 << 15))
-    EXTD1.config->channels[15].cb(&EXTD1, 15);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[16] interrupt handler (PVD).
- *
- * @isr
- */
-CH_IRQ_HANDLER(PVD_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 16);
-  EXTD1.config->channels[16].cb(&EXTD1, 16);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[17] interrupt handler (RTC).
- *
- * @isr
- */
-CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 17);
-  EXTD1.config->channels[17].cb(&EXTD1, 17);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if defined(STM32F10X_CL)
-/**
- * @brief   EXTI[18] interrupt handler (OTG_FS_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 18);
-  EXTD1.config->channels[18].cb(&EXTD1, 18);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[19] interrupt handler (ETH_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 19);
-  EXTD1.config->channels[19].cb(&EXTD1, 19);
-
-  CH_IRQ_EPILOGUE();
-}
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
-      defined(STM32F10X_HD_VL)
-
-#else /* Other STM32F1xx devices.*/
-/**
- * @brief   EXTI[18] interrupt handler (USB_FS_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 18);
-  EXTD1.config->channels[18].cb(&EXTD1, 18);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(void) {
-
-  nvicEnableVector(EXTI0_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
-  nvicEnableVector(EXTI1_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
-  nvicEnableVector(EXTI2_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
-  nvicEnableVector(EXTI3_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
-  nvicEnableVector(EXTI4_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
-  nvicEnableVector(EXTI9_5_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
-  nvicEnableVector(EXTI15_10_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
-  nvicEnableVector(PVD_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
-  nvicEnableVector(RTC_Alarm_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
-#if defined(STM32F10X_CL)
-  /* EXTI vectors specific to STM32F1xx Connectivity Line.*/
-  nvicEnableVector(OTG_FS_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
-  nvicEnableVector(ETH_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
-      defined(STM32F10X_HD_VL)
-  /* EXTI vectors specific to STM32F1xx Value Line.*/
-#else
-  /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
-  nvicEnableVector(USB_FS_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
-#endif
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(void) {
-
-  nvicDisableVector(EXTI0_IRQn);
-  nvicDisableVector(EXTI1_IRQn);
-  nvicDisableVector(EXTI2_IRQn);
-  nvicDisableVector(EXTI3_IRQn);
-  nvicDisableVector(EXTI4_IRQn);
-  nvicDisableVector(EXTI9_5_IRQn);
-  nvicDisableVector(EXTI15_10_IRQn);
-  nvicDisableVector(PVD_IRQn);
-  nvicDisableVector(RTC_Alarm_IRQn);
-#if defined(STM32F10X_CL)
-  /* EXTI vectors specific to STM32F1xx Connectivity Line.*/
-  nvicDisableVector(OTG_FS_WKUP_IRQn);
-  nvicDisableVector(ETH_WKUP_IRQn);
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
-    defined(STM32F10X_HD_VL)
-  /* EXTI vectors specific to STM32F1xx Value Line.*/
-#else
-  /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
-  nvicDisableVector(USB_FS_WKUP_IRQn);
-#endif
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c
deleted file mode 100644
index eb87a1a84..000000000
--- a/os/hal/platforms/STM32F1xx/hal_lld.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F1xx/hal_lld.c
- * @brief   STM32F1xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes the backup domain.
- * @note    WARNING! Changing clock source impossible without resetting
- *          of the whole BKP domain.
- */
-static void hal_lld_backup_domain_init(void) {
-
-  /* Backup domain access enabled and left open.*/
-  PWR->CR |= PWR_CR_DBP;
-
-#if HAL_USE_RTC
-  /* Reset BKP domain if different clock source selected.*/
-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
-    /* Backup domain reset.*/
-    RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0;
-  }
-
-  /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-  RCC->BDCR |= RCC_BDCR_LSEON;
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
-#endif /* STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
-  /* If the backup domain hasn't been initialized yet then proceed with
-     initialization.*/
-  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
-    /* Selects clock source.*/
-    RCC->BDCR |= STM32_RTCSEL;
-
-    /* Prescaler value loaded in registers.*/
-    rtc_lld_set_prescaler();
-
-    /* RTC clock enabled.*/
-    RCC->BDCR |= RCC_BDCR_RTCEN;
-  }
-#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
-#endif /* HAL_USE_RTC */
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* Reset of all peripherals.*/
-  rccResetAPB1(0xFFFFFFFF);
-  rccResetAPB2(0xFFFFFFFF);
-
-  /* SysTick initialization using the system clock.*/
-  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-
-  /* DWT cycle counter enable.*/
-  SCS_DEMCR |= SCS_DEMCR_TRCENA;
-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
-
-  /* PWR and BD clocks enabled.*/
-  rccEnablePWRInterface(FALSE);
-  rccEnableBKPInterface(FALSE);
-
-  /* Initializes the backup domain.*/
-  hal_lld_backup_domain_init();
-
-#if defined(STM32_DMA_REQUIRED)
-  dmaInit();
-#endif
-
-  /* Programmable voltage detector enable.*/
-#if STM32_PVD_ENABLE
-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-#endif /* STM32_PVD_ENABLE */
-}
-
-/**
- * @brief   STM32 clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function should be invoked just after the system reset.
- *
- * @special
- */
-#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) ||                    \
-    defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) ||                    \
-    defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                       \
-    defined(__DOXYGEN__)
-/*
- * Clocks initialization for all sub-families except CL.
- */
-void stm32_clock_init(void) {
-
-#if !STM32_NO_INIT
-  /* HSI setup, it enforces the reset situation in order to handle possible
-     problems with JTAG probes and re-initializations.*/
-  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;                                       /* Wait until HSI is stable.    */
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
-  RCC->CFGR = 0;                            /* CFGR reset value.            */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;                                       /* Waits until HSI is selected. */
-
-#if STM32_HSE_ENABLED
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEBYP;
-#endif
-  /* HSE activation.*/
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;                                       /* Waits until HSE is stable.   */
-#endif
-
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                                       /* Waits until LSI is stable.   */
-#endif
-
-#if STM32_ACTIVATE_PLL
-  /* PLL activation.*/
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;                                       /* Waits until PLL is stable.   */
-#endif
-
-  /* Clock settings.*/
-#if STM32_HAS_USB
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE |
-              STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2  | STM32_PPRE1    |
-              STM32_HPRE;
-#else
-  RCC->CFGR = STM32_MCOSEL |                STM32_PLLMUL | STM32_PLLXTPRE |
-              STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2  | STM32_PPRE1    |
-              STM32_HPRE;
-#endif
-
-  /* Flash setup and final clock selection.   */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* Switching to the configured clock source if it is different from HSI.*/
-#if (STM32_SW != STM32_SW_HSI)
-  /* Switches clock source.*/
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;                                       /* Waits selection complete.    */
-#endif
-
-#if !STM32_HSI_ENABLED
-  RCC->CR &= ~RCC_CR_HSION;
-#endif
-#endif /* !STM32_NO_INIT */
-}
-
-#elif defined(STM32F10X_CL)
-/*
- * Clocks initialization for the CL sub-family.
- */
-void stm32_clock_init(void) {
-
-#if !STM32_NO_INIT
-  /* HSI setup.*/
-  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;                                       /* Wait until HSI is stable.    */
-  RCC->CFGR = 0;
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;                                       /* Wait until HSI is the source.*/
-
-#if STM32_HSE_ENABLED
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEBYP;
-#endif
-  /* HSE activation.*/
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;                                       /* Waits until HSE is stable.   */
-#endif
-
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                                       /* Waits until LSI is stable.   */
-#endif
-
-  /* Settings of various dividers and multipliers in CFGR2.*/
-  RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
-               STM32_PREDIV1 | STM32_PREDIV1SRC;
-
-  /* PLL2 setup, if activated.*/
-#if STM32_ACTIVATE_PLL2
-  RCC->CR |= RCC_CR_PLL2ON;
-  while (!(RCC->CR & RCC_CR_PLL2RDY))
-    ;                                        /* Waits until PLL2 is stable. */
-#endif
-
-  /* PLL3 setup, if activated.*/
-#if STM32_ACTIVATE_PLL3
-  RCC->CR |= RCC_CR_PLL3ON;
-  while (!(RCC->CR & RCC_CR_PLL3RDY))
-    ;                                        /* Waits until PLL3 is stable. */
-#endif
-
-  /* PLL1 setup, if activated.*/
-#if STM32_ACTIVATE_PLL1
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;                           /* Waits until PLL1 is stable.              */
-#endif
-
-  /* Clock settings.*/
-#if STM32_HAS_OTG1
-  RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC |
-              STM32_ADCPRE | STM32_PPRE2    | STM32_PPRE1  | STM32_HPRE;
-#else
-  RCC->CFGR = STM32_MCO    |                  STM32_PLLMUL | STM32_PLLSRC |
-              STM32_ADCPRE | STM32_PPRE2    | STM32_PPRE1  | STM32_HPRE;
-#endif
-
-  /* Flash setup and final clock selection.   */
-  FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock.    */
-
-  /* Switching to the configured clock source if it is different from HSI.*/
-#if (STM32_SW != STM32_SW_HSI)
-  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-#endif
-
-#if !STM32_HSI_ENABLED
-  RCC->CR &= ~RCC_CR_HSION;
-#endif
-#endif /* !STM32_NO_INIT */
-}
-#else
-void stm32_clock_init(void) {}
-#endif
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h
deleted file mode 100644
index 969f96474..000000000
--- a/os/hal/platforms/STM32F1xx/hal_lld.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F1xx/hal_lld.h
- * @brief   STM32F1xx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - STM32_LSECLK.
- *          - STM32_HSECLK.
- *          - STM32_HSE_BYPASS (optionally).
- *          .
- *          One of the following macros must also be defined:
- *          - STM32F10X_LD_VL for Value Line Low Density devices.
- *          - STM32F10X_MD_VL for Value Line Medium Density devices.
- *          - STM32F10X_LD for Performance Low Density devices.
- *          - STM32F10X_MD for Performance Medium Density devices.
- *          - STM32F10X_HD for Performance High Density devices.
- *          - STM32F10X_XL for Performance eXtra Density devices.
- *          - STM32F10X_CL for Connectivity Line devices.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "stm32.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define STM32_HSICLK            8000000     /**< High speed internal clock. */
-#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
-/** @} */
-
-/**
- * @name    PWR_CR register bits definitions
- * @{
- */
-#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
-#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
-#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
-#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
-#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
-#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
-#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
-#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
-#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
-/** @} */
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    STM32F1xx capabilities
- * @{
- */
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_IS_CALENDAR   FALSE
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Disables the PWR/RCC initialization in the HAL.
- */
-#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT               FALSE
-#endif
-
-/**
- * @brief   Enables or disables the programmable voltage detector.
- */
-#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE            FALSE
-#endif
-
-/**
- * @brief   Sets voltage level for programmable voltage detector.
- */
-#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS                   STM32_PLS_LEV0
-#endif
-
-/**
- * @brief   Enables or disables the HSI clock source.
- */
-#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSI clock source.
- */
-#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED           FALSE
-#endif
-
-/**
- * @brief   Enables or disables the HSE clock source.
- */
-#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSE clock source.
- */
-#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED           FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if defined(__DOXYGEN__)
-/**
- * @name    Platform identification
- * @{
- */
-#define PLATFORM_NAME           "STM32"
-/** @} */
-
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
-      defined(STM32F10X_HD_VL) || defined(__DOXYGEN__)
-#include "hal_lld_f100.h"
-
-#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) ||                     \
-      defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                     \
-      defined(__DOXYGEN__)
-#include "hal_lld_f103.h"
-
-#elif defined(STM32F10X_CL) || defined(__DOXYGEN__)
-#include "hal_lld_f105_f107.h"
-
-#else
-#error "unspecified, unsupported or invalid STM32 platform"
-#endif
-
-/* There are differences in vector names in the various sub-families,
-   normalizing.*/
-#if defined(STM32F10X_XL)
-#define TIM1_BRK_IRQn       TIM1_BRK_TIM9_IRQn
-#define TIM1_UP_IRQn        TIM1_UP_TIM10_IRQn
-#define TIM1_TRG_COM_IRQn   TIM1_TRG_COM_TIM11_IRQn
-#define TIM8_BRK_IRQn       TIM8_BRK_TIM12_IRQn
-#define TIM8_UP_IRQn        TIM8_UP_TIM13_IRQn
-#define TIM8_TRG_COM_IRQn   TIM8_TRG_COM_TIM14_IRQn
-
-#elif defined(STM32F10X_LD_VL)|| defined(STM32F10X_MD_VL) ||                \
-      defined(STM32F10X_HD_VL)
-#define TIM1_BRK_IRQn       TIM1_BRK_TIM15_IRQn
-#define TIM1_UP_IRQn        TIM1_UP_TIM16_IRQn
-#define TIM1_TRG_COM_IRQn   TIM1_TRG_COM_TIM17_IRQn
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief   Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This service is implemented by returning the content of the
- *          DWT_CYCCNT register.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value()         DWT_CYCCNT
-
-/**
- * @brief   Realtime counter frequency.
- * @note    The DWT_CYCCNT register is incremented directly by the system
- *          clock so this function returns STM32_HCLK.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency()     STM32_HCLK
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-/* STM32 ISR, DMA and RCC helpers.*/
-#include "stm32_isr.h"
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void stm32_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
deleted file mode 100644
index 548bb03d0..000000000
--- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h
+++ /dev/null
@@ -1,950 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM32F100_HAL STM32F100 HAL Support
- * @details HAL support for STM32 Value Line LD, MD and HD sub-families.
- *
- * @ingroup HAL
- */
-
-/**
- * @file    STM32F1xx/hal_lld_f100.h
- * @brief   STM32F100 Value Line HAL subsystem low level driver header.
- *
- * @addtogroup STM32F100_HAL
- * @{
- */
-
-#ifndef _HAL_LLD_F100_H_
-#define _HAL_LLD_F100_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Platform identification
- * @{
- */
-#if defined(__DOXYGEN__)
-#define PLATFORM_NAME           "STM32F100 Value Line"
-
-#elif defined(STM32F10X_LD_VL)
-#define PLATFORM_NAME           "STM32F100 Value Line Low Density"
-
-#elif defined(STM32F10X_MD_VL)
-#define PLATFORM_NAME           "STM32F100 Value Line Medium Density"
-#else
-#error "unsupported STM32 Value Line member"
-#endif
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum system clock frequency.
- */
-#define STM32_SYSCLK_MAX        24000000
-
-/**
- * @brief   Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX        24000000
-
-/**
- * @brief   Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN        1000000
-
-/**
- * @brief   Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX        1000000
-
-/**
- * @brief   Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN        32768
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MAX         24000000
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MIN         1000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MAX        24000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MIN        16000000
-
-/**
- * @brief   Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX         24000000
-
-/**
- * @brief   Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX         24000000
-
-/**
- * @brief   Maximum ADC clock frequency.
- */
-#define STM32_ADCCLK_MAX        12000000
-/** @} */
-
-/**
- * @name    RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
-#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
-#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
-
-#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
-#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
-#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
-#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
-#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
-#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
-#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
-#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
-#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
-
-#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
-#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
-#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
-#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
-#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
-
-#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
-#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
-#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
-#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
-#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
-
-#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PPRE2 divided by 2.        */
-#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PPRE2 divided by 4.        */
-#define STM32_ADCPRE_DIV6       (2 << 14)   /**< PPRE2 divided by 6.        */
-#define STM32_ADCPRE_DIV8       (3 << 14)   /**< PPRE2 divided by 8.        */
-
-#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
-#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
-
-#define STM32_PLLXTPRE_DIV1     (0 << 17)   /**< HSE divided by 1.          */
-#define STM32_PLLXTPRE_DIV2     (1 << 17)   /**< HSE divided by 2.          */
-
-#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
-#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
-#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
-#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
-#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
-/** @} */
-
-/**
- * @name    RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
-#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
-#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
-#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
-#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 128 used as
-                                                 RTC clock.                 */
-/** @} */
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-/**
- * @name    STM32F100 LD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_HAS_ADC2          FALSE
-#define STM32_HAS_ADC3          FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          FALSE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 18
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         FALSE
-#define STM32_HAS_GPIOF         FALSE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          FALSE
-#define STM32_I2C2_RX_DMA_MSK   0
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   0
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_SPI3_RX_DMA_MSK   0
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   0
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          FALSE
-#define STM32_SPI2_RX_DMA_MSK   0
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   0
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          FALSE
-#define STM32_SPI3_RX_DMA_MSK   0
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   0
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          FALSE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          TRUE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         FALSE
-#define STM32_HAS_TIM15         TRUE
-#define STM32_HAS_TIM16         TRUE
-#define STM32_HAS_TIM17         TRUE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        FALSE
-#define STM32_USART3_RX_DMA_MSK 0
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK 0
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         FALSE
-#define STM32_UART4_RX_DMA_MSK  0
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  0
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         FALSE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           FALSE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-#endif /* defined(STM32F10X_LD_VL) */
-
-#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
-/**
- * @name    STM32F100 MD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_HAS_ADC2          FALSE
-#define STM32_HAS_ADC3          FALSE
-#define STM32_HAS_ADC4          FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          FALSE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         TRUE
-#define STM32_HAS_GPIOF         FALSE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_I2C3_RX_DMA_MSK   0
-#define STM32_I2C3_RX_DMA_CHN   0x00000000
-#define STM32_I2C3_TX_DMA_MSK   0
-#define STM32_I2C3_TX_DMA_CHN   0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          FALSE
-#define STM32_HAS_SPI4          FALSE
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          TRUE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          TRUE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         FALSE
-#define STM32_HAS_TIM15         TRUE
-#define STM32_HAS_TIM16         TRUE
-#define STM32_HAS_TIM17         TRUE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         FALSE
-#define STM32_UART4_RX_DMA_MSK  0
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  0
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         FALSE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           FALSE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-#endif /* defined(STM32F10X_MD_VL) */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names.                                     */
-/*===========================================================================*/
-
-/**
- * @name  IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler         Vector40    /**< Window Watchdog.           */
-#define PVD_IRQHandler          Vector44    /**< PVD through EXTI Line
-                                                 detect.                    */
-#define TAMPER_IRQHandler       Vector48    /**< Tamper.                    */
-#define RTC_IRQHandler          Vector4C    /**< RTC.                       */
-#define FLASH_IRQHandler        Vector50    /**< Flash.                     */
-#define RCC_IRQHandler          Vector54    /**< RCC.                       */
-#define EXTI0_IRQHandler        Vector58    /**< EXTI Line 0.               */
-#define EXTI1_IRQHandler        Vector5C    /**< EXTI Line 1.               */
-#define EXTI2_IRQHandler        Vector60    /**< EXTI Line 2.               */
-#define EXTI3_IRQHandler        Vector64    /**< EXTI Line 3.               */
-#define EXTI4_IRQHandler        Vector68    /**< EXTI Line 4.               */
-#define DMA1_Ch1_IRQHandler     Vector6C    /**< DMA1 Channel 1.            */
-#define DMA1_Ch2_IRQHandler     Vector70    /**< DMA1 Channel 2.            */
-#define DMA1_Ch3_IRQHandler     Vector74    /**< DMA1 Channel 3.            */
-#define DMA1_Ch4_IRQHandler     Vector78    /**< DMA1 Channel 4.            */
-#define DMA1_Ch5_IRQHandler     Vector7C    /**< DMA1 Channel 5.            */
-#define DMA1_Ch6_IRQHandler     Vector80    /**< DMA1 Channel 6.            */
-#define DMA1_Ch7_IRQHandler     Vector84    /**< DMA1 Channel 7.            */
-#define ADC1_2_IRQHandler       Vector88    /**< ADC1_2.                    */
-#define EXTI9_5_IRQHandler      Vector9C    /**< EXTI Line 9..5.            */
-#define TIM1_BRK_IRQHandler     VectorA0    /**< TIM1 Break.                */
-#define TIM1_UP_IRQHandler      VectorA4    /**< TIM1 Update.               */
-#define TIM1_TRG_COM_IRQHandler VectorA8    /**< TIM1 Trigger and
-                                                 Commutation.               */
-#define TIM1_CC_IRQHandler      VectorAC    /**< TIM1 Capture Compare.      */
-#define TIM2_IRQHandler         VectorB0    /**< TIM2.                      */
-#define TIM3_IRQHandler         VectorB4    /**< TIM3.                      */
-#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-#define TIM4_IRQHandler         VectorB8    /**< TIM4.                      */
-#endif
-#define I2C1_EV_IRQHandler      VectorBC    /**< I2C1 Event.                */
-#define I2C1_ER_IRQHandler      VectorC0    /**< I2C1 Error.                */
-#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-#define I2C2_EV_IRQHandler      VectorC4    /**< I2C2 Event.                */
-#define I2C2_ER_IRQHandler      VectorC8    /**< I2C2 Error.                */
-#endif
-#define SPI1_IRQHandler         VectorCC    /**< SPI1.                      */
-#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-#define SPI2_IRQHandler         VectorD0    /**< SPI2.                      */
-#endif
-#define USART1_IRQHandler       VectorD4    /**< USART1.                    */
-#define USART2_IRQHandler       VectorD8    /**< USART2.                    */
-#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
-#define USART3_IRQHandler       VectorDC    /**< USART3.                    */
-#endif
-#define EXTI15_10_IRQHandler    VectorE0    /**< EXTI Line 15..10.          */
-#define RTC_Alarm_IRQHandler    VectorE4    /**< RTC Alarm through EXTI.    */
-#define CEC_IRQHandler          VectorE8    /**< CEC.                       */
-#define TIM12_IRQHandler        VectorEC    /**< TIM12.                     */
-#define TIM13_IRQHandler        VectorF0    /**< TIM13.                     */
-#define TIM14_IRQHandler        VectorF4    /**< TIM14.                     */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Main clock source selection.
- * @note    If the selected clock source is not the PLL then the PLL is not
- *          initialized and started.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW                    STM32_SW_PLL
-#endif
-
-/**
- * @brief   Clock source for the PLL.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief   Crystal PLL pre-divider.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
-#define STM32_PLLXTPRE              STM32_PLLXTPRE_DIV1
-#endif
-
-/**
- * @brief   PLL multiplier value.
- * @note    The allowed range is 2...16.
- * @note    The default value is calculated for a 24MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE          3
-#endif
-
-/**
- * @brief   AHB prescaler value.
- * @note    The default value is calculated for a 24MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE                  STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief   APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1                 STM32_PPRE1_DIV1
-#endif
-
-/**
- * @brief   APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2                 STM32_PPRE2_DIV1
-#endif
-
-/**
- * @brief   ADC prescaler value.
- */
-#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADCPRE                STM32_ADCPRE_DIV2
-#endif
-
-/**
- * @brief   MCO pin setting.
- */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL                   STM32_MCOSEL_NOCLOCK
-#endif
-
-/**
- * @brief   RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL                   STM32_RTCSEL_LSI
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F100_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F100_MCUCONF not defined"
-#endif
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCOSEL"
-#endif
-
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                         \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCOSEL"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSELSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSI
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if (STM32_LSECLK == 0)
-#error "LSE frequency not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/* PLL activation conditions.*/
-#if (STM32_SW == STM32_SW_PLL) ||                                           \
-    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL          TRUE
-#else
-#define STM32_ACTIVATE_PLL          FALSE
-#endif
-
-/* HSE prescaler setting check.*/
-#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) &&                              \
-    (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
-#error "invalid STM32_PLLXTPRE value specified"
-#endif
-
-/**
- * @brief   PLLMUL field.
- */
-#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
-    defined(__DOXYGEN__)
-#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
-#else
-#error "invalid STM32_PLLMUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
-#define STM32_PLLCLKIN              (STM32_HSECLK / 1)
-#else
-#define STM32_PLLCLKIN              (STM32_HSECLK / 2)
-#endif
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/* PLL input frequency range check.*/
-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
-#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
-#endif
-
-/**
- * @brief   System clock source.
- */
-#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
-#define STM32_SYSCLK                STM32_PLLCLKOUT
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/* AHB frequency check.*/
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                 (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                 (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                 (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                 (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/* APB1 frequency check.*/
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief   APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                 (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                 (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                 (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                 (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/**
- * @brief   RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                (STM32_HSECLK / 128)
-#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
-#define STM32_RTCCLK                0
-#else
-#error "invalid source selected for RTC clock"
-#endif
-
-/**
- * @brief   ADC frequency.
- */
-#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_ADCCLK                (STM32_PCLK2 / 2)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
-#define STM32_ADCCLK                (STM32_PCLK2 / 4)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
-#define STM32_ADCCLK                (STM32_PCLK2 / 6)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
-#define STM32_ADCCLK                (STM32_PCLK2 / 8)
-#else
-#error "invalid STM32_ADCPRE value specified"
-#endif
-
-/* ADC frequency check.*/
-#if STM32_ADCCLK > STM32_ADCCLK_MAX
-#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/**
- * @brief   Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief   Timers 1, 8, 9, 10, 11 clock.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
-#endif
-
-/**
- * @brief   Flash settings.
- */
-#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS             0x00000010
-#elif STM32_HCLK <= 48000000
-#define STM32_FLASHBITS             0x00000011
-#else
-#define STM32_FLASHBITS             0x00000012
-#endif
-
-#endif /* _HAL_LLD_F100_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
deleted file mode 100644
index 012578d69..000000000
--- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h
+++ /dev/null
@@ -1,1308 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM32F103_HAL STM32F103 HAL Support
- * @details HAL support for STM32 Performance Line LD, MD and HD sub-families.
- *
- * @ingroup HAL
- */
-
-/**
- * @file    STM32F1xx/hal_lld_f103.h
- * @brief   STM32F103 Performance Line HAL subsystem low level driver header.
- *
- * @addtogroup STM32F103_HAL
- * @{
- */
-
-#ifndef _HAL_LLD_F103_H_
-#define _HAL_LLD_F103_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Platform identification
- * @{
- */
-#if defined(__DOXYGEN__)
-#define PLATFORM_NAME           "STM32F10x Performance Line"
-
-#elif defined(STM32F10X_LD)
-#define PLATFORM_NAME           "STM32F10x Performance Line Low Density"
-
-#elif defined(STM32F10X_MD)
-#define PLATFORM_NAME           "STM32F10x Performance Line Medium Density"
-
-#elif defined(STM32F10X_HD)
-#define PLATFORM_NAME           "STM32F10x Performance Line High Density"
-
-#elif defined(STM32F10X_XL)
-#define PLATFORM_NAME           "STM32F10x Performance Line eXtra Density"
-
-#else
-#error "unsupported STM32 Performance Line member"
-#endif
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum system clock frequency.
- */
-#define STM32_SYSCLK_MAX        72000000
-
-/**
- * @brief   Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX        25000000
-
-/**
- * @brief   Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN        1000000
-
-/**
- * @brief   Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX        1000000
-
-/**
- * @brief   Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN        32768
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MAX         25000000
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MIN         1000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MAX        72000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MIN        16000000
-
-/**
- * @brief   Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX         36000000
-
-/**
- * @brief   Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX         72000000
-
-/**
- * @brief   Maximum ADC clock frequency.
- */
-#define STM32_ADCCLK_MAX        14000000
-/** @} */
-
-/**
- * @name    RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
-#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
-#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
-
-#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
-#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
-#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
-#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
-#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
-#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
-#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
-#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
-#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
-
-#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
-#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
-#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
-#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
-#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
-
-#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
-#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
-#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
-#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
-#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
-
-#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PPRE2 divided by 2.        */
-#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PPRE2 divided by 4.        */
-#define STM32_ADCPRE_DIV6       (2 << 14)   /**< PPRE2 divided by 6.        */
-#define STM32_ADCPRE_DIV8       (3 << 14)   /**< PPRE2 divided by 8.        */
-
-#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
-#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
-
-#define STM32_PLLXTPRE_DIV1     (0 << 17)   /**< HSE divided by 1.          */
-#define STM32_PLLXTPRE_DIV2     (1 << 17)   /**< HSE divided by 2.          */
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)   /**< PLLOUT divided by 1.5.     */
-#define STM32_USBPRE_DIV1       (1 << 22)   /**< PLLOUT divided by 1.       */
-
-#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
-#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
-#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
-#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
-#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
-/** @} */
-
-/**
- * @name    RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
-#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
-#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
-#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
-#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 128 used as
-                                                 RTC clock.                 */
-/** @} */
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-#if defined(STM32F10X_LD) || defined(__DOXYGEN__)
-/**
- * @name    STM32F103 LD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_HAS_ADC2          TRUE
-#define STM32_HAS_ADC3          FALSE
-#define STM32_HAS_ADC4          FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          TRUE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         FALSE
-#define STM32_HAS_GPIOF         FALSE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          FALSE
-#define STM32_I2C2_RX_DMA_MSK   0
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   0
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_SPI3_RX_DMA_MSK   0
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   0
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          FALSE
-#define STM32_SPI2_RX_DMA_MSK   0
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   0
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          FALSE
-#define STM32_SPI3_RX_DMA_MSK   0
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   0
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          FALSE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          FALSE
-#define STM32_HAS_TIM7          FALSE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         FALSE
-#define STM32_HAS_TIM15         FALSE
-#define STM32_HAS_TIM16         FALSE
-#define STM32_HAS_TIM17         FALSE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        FALSE
-#define STM32_USART3_RX_DMA_MSK 0
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK 0
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         FALSE
-#define STM32_UART4_RX_DMA_MSK  0
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  0
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         FALSE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           FALSE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-#endif /* defined(STM32F10X_LD) */
-
-#if defined(STM32F10X_MD) || defined(__DOXYGEN__)
-/**
- * @name    STM32F103 MD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_HAS_ADC2          TRUE
-#define STM32_HAS_ADC3          FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          TRUE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         TRUE
-#define STM32_HAS_GPIOF         FALSE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_I2C3_RX_DMA_MSK   0
-#define STM32_I2C3_RX_DMA_CHN   0x00000000
-#define STM32_I2C3_TX_DMA_MSK   0
-#define STM32_I2C3_TX_DMA_CHN   0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          FALSE
-#define STM32_SPI3_RX_DMA_MSK   0
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   0
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          TRUE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          FALSE
-#define STM32_HAS_TIM7          FALSE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         FALSE
-#define STM32_HAS_TIM15         FALSE
-#define STM32_HAS_TIM16         FALSE
-#define STM32_HAS_TIM17         FALSE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         FALSE
-#define STM32_UART4_RX_DMA_MSK  0
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  0
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         FALSE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           TRUE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-#endif /* defined(STM32F10X_MD) */
-
-#if defined(STM32F10X_HD) || defined(__DOXYGEN__)
-/**
- * @name    STM32F103 HD capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_HAS_ADC2          TRUE
-#define STM32_HAS_ADC3          TRUE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          TRUE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         TRUE
-#define STM32_HAS_GPIOF         TRUE
-#define STM32_HAS_GPIOG         TRUE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_I2C3_RX_DMA_MSK   0
-#define STM32_I2C3_RX_DMA_CHN   0x00000000
-#define STM32_I2C3_TX_DMA_MSK   0
-#define STM32_I2C3_TX_DMA_CHN   0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          TRUE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          TRUE
-#define STM32_SPI3_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 1)
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 2)
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          TRUE
-#define STM32_HAS_TIM5          TRUE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          TRUE
-#define STM32_HAS_TIM8          TRUE
-#define STM32_HAS_TIM9          TRUE
-#define STM32_HAS_TIM10         TRUE
-#define STM32_HAS_TIM11         TRUE
-#define STM32_HAS_TIM12         TRUE
-#define STM32_HAS_TIM13         TRUE
-#define STM32_HAS_TIM14         TRUE
-#define STM32_HAS_TIM15         FALSE
-#define STM32_HAS_TIM16         FALSE
-#define STM32_HAS_TIM17         FALSE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         TRUE
-#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         TRUE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           TRUE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-#endif /* defined(STM32F10X_HD) */
-
-#if defined(STM32F10X_XL) || defined(__DOXYGEN__)
-/**
- * @name    STM32F103 XL capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_HAS_ADC2          TRUE
-#define STM32_HAS_ADC3          TRUE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          TRUE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 19
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         TRUE
-#define STM32_HAS_GPIOF         TRUE
-#define STM32_HAS_GPIOG         TRUE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_I2C3_RX_DMA_MSK   0
-#define STM32_I2C3_RX_DMA_CHN   0x00000000
-#define STM32_I2C3_TX_DMA_MSK   0
-#define STM32_I2C3_TX_DMA_CHN   0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          TRUE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          TRUE
-#define STM32_SPI3_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 1)
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 2)
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI4          FALSE
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          TRUE
-#define STM32_HAS_TIM5          TRUE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          TRUE
-#define STM32_HAS_TIM8          TRUE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         FALSE
-#define STM32_HAS_TIM15         FALSE
-#define STM32_HAS_TIM16         FALSE
-#define STM32_HAS_TIM17         FALSE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         TRUE
-#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         TRUE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           TRUE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-#endif /* defined(STM32F10X_XL) */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names.                                     */
-/*===========================================================================*/
-
-/**
- * @name  IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler         Vector40    /**< Window Watchdog.           */
-#define PVD_IRQHandler          Vector44    /**< PVD through EXTI Line
-                                                 detect.                    */
-#define TAMPER_IRQHandler       Vector48    /**< Tamper.                    */
-#define RTC_IRQHandler          Vector4C    /**< RTC.                       */
-#define FLASH_IRQHandler        Vector50    /**< Flash.                     */
-#define RCC_IRQHandler          Vector54    /**< RCC.                       */
-#define EXTI0_IRQHandler        Vector58    /**< EXTI Line 0.               */
-#define EXTI1_IRQHandler        Vector5C    /**< EXTI Line 1.               */
-#define EXTI2_IRQHandler        Vector60    /**< EXTI Line 2.               */
-#define EXTI3_IRQHandler        Vector64    /**< EXTI Line 3.               */
-#define EXTI4_IRQHandler        Vector68    /**< EXTI Line 4.               */
-#define DMA1_Ch1_IRQHandler     Vector6C    /**< DMA1 Channel 1.            */
-#define DMA1_Ch2_IRQHandler     Vector70    /**< DMA1 Channel 2.            */
-#define DMA1_Ch3_IRQHandler     Vector74    /**< DMA1 Channel 3.            */
-#define DMA1_Ch4_IRQHandler     Vector78    /**< DMA1 Channel 4.            */
-#define DMA1_Ch5_IRQHandler     Vector7C    /**< DMA1 Channel 5.            */
-#define DMA1_Ch6_IRQHandler     Vector80    /**< DMA1 Channel 6.            */
-#define DMA1_Ch7_IRQHandler     Vector84    /**< DMA1 Channel 7.            */
-#define ADC1_2_IRQHandler       Vector88    /**< ADC1_2.                    */
-#define CAN1_TX_IRQHandler      Vector8C    /**< CAN1 TX.                   */
-#define USB_HP_IRQHandler       Vector8C    /**< USB High Priority, CAN1 TX.*/
-#define CAN1_RX0_IRQHandler     Vector90    /**< CAN1 RX0.                  */
-#define USB_LP_IRQHandler       Vector90    /**< USB Low Priority, CAN1 RX0.*/
-#define CAN1_RX1_IRQHandler     Vector94    /**< CAN1 RX1.                  */
-#define CAN1_SCE_IRQHandler     Vector98    /**< CAN1 SCE.                  */
-#define EXTI9_5_IRQHandler      Vector9C    /**< EXTI Line 9..5.            */
-#define TIM1_BRK_IRQHandler     VectorA0    /**< TIM1 Break.                */
-#define TIM1_UP_IRQHandler      VectorA4    /**< TIM1 Update.               */
-#define TIM1_TRG_COM_IRQHandler VectorA8    /**< TIM1 Trigger and
-                                                 Commutation.               */
-#define TIM1_CC_IRQHandler      VectorAC    /**< TIM1 Capture Compare.      */
-#define TIM2_IRQHandler         VectorB0    /**< TIM2.                      */
-#define TIM3_IRQHandler         VectorB4    /**< TIM3.                      */
-#define TIM4_IRQHandler         VectorB8    /**< TIM4.                      */
-#define I2C1_EV_IRQHandler      VectorBC    /**< I2C1 Event.                */
-#define I2C1_ER_IRQHandler      VectorC0    /**< I2C1 Error.                */
-#define I2C2_EV_IRQHandler      VectorC4    /**< I2C2 Event.                */
-#define I2C2_ER_IRQHandler      VectorC8    /**< I2C2 Error.                */
-#define SPI1_IRQHandler         VectorCC    /**< SPI1.                      */
-#define SPI2_IRQHandler         VectorD0    /**< SPI2.                      */
-#define USART1_IRQHandler       VectorD4    /**< USART1.                    */
-#define USART2_IRQHandler       VectorD8    /**< USART2.                    */
-#define USART3_IRQHandler       VectorDC    /**< USART3.                    */
-#define EXTI15_10_IRQHandler    VectorE0    /**< EXTI Line 15..10.          */
-#define RTC_Alarm_IRQHandler    VectorE4    /**< RTC Alarm through EXTI.    */
-#define USB_FS_WKUP_IRQHandler  VectorE8    /**< USB Wakeup from suspend.   */
-#define TIM8_BRK_IRQHandler     VectorEC    /**< TIM8 Break.                */
-#define TIM8_UP_IRQHandler      VectorF0    /**< TIM8 Update.               */
-#define TIM8_TRG_COM_IRQHandler VectorF4    /**< TIM8 Trigger and
-                                                 Commutation.               */
-#define TIM8_CC_IRQHandler      VectorF8    /**< TIM8 Capture Compare.      */
-#define ADC3_IRQHandler         VectorFC    /**< ADC3.                      */
-#define FSMC_IRQHandler         Vector100   /**< FSMC.                      */
-#define SDIO_IRQHandler         Vector104   /**< SDIO.                      */
-#define TIM5_IRQHandler         Vector108   /**< TIM5.                      */
-#define SPI3_IRQHandler         Vector10C   /**< SPI3.                      */
-#define UART4_IRQHandler        Vector110   /**< UART4.                     */
-#define UART5_IRQHandler        Vector114   /**< UART5.                     */
-#define TIM6_IRQHandler         Vector118   /**< TIM6.                      */
-#define TIM7_IRQHandler         Vector11C   /**< TIM7.                      */
-#define DMA2_Ch1_IRQHandler     Vector120   /**< DMA2 Channel1.             */
-#define DMA2_Ch2_IRQHandler     Vector124   /**< DMA2 Channel2.             */
-#define DMA2_Ch3_IRQHandler     Vector128   /**< DMA2 Channel3.             */
-#define DMA2_Ch4_5_IRQHandler   Vector12C   /**< DMA2 Channel4 & Channel5.  */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Main clock source selection.
- * @note    If the selected clock source is not the PLL then the PLL is not
- *          initialized and started.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW                    STM32_SW_PLL
-#endif
-
-/**
- * @brief   Clock source for the PLL.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief   Crystal PLL pre-divider.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
-#define STM32_PLLXTPRE              STM32_PLLXTPRE_DIV1
-#endif
-
-/**
- * @brief   PLL multiplier value.
- * @note    The allowed range is 2...16.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE          9
-#endif
-
-/**
- * @brief   AHB prescaler value.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE                  STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief   APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1                 STM32_PPRE1_DIV2
-#endif
-
-/**
- * @brief   APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2                 STM32_PPRE2_DIV2
-#endif
-
-/**
- * @brief   ADC prescaler value.
- */
-#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADCPRE                STM32_ADCPRE_DIV4
-#endif
-
-/**
- * @brief   USB clock setting.
- */
-#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
-#define STM32_USB_CLOCK_REQUIRED    TRUE
-#endif
-
-/**
- * @brief   USB prescaler initialization.
- */
-#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
-#define STM32_USBPRE                STM32_USBPRE_DIV1P5
-#endif
-
-/**
- * @brief   MCO pin setting.
- */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
-#endif
-
-/**
- * @brief   RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL                STM32_RTCSEL_LSI
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F103_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F103_MCUCONF not defined"
-#endif
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCOSEL"
-#endif
-
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCOSEL"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSI
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if (STM32_LSECLK == 0)
-#error "LSE frequency not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/* PLL activation conditions.*/
-#if STM32_USB_CLOCK_REQUIRED ||                                             \
-    (STM32_SW == STM32_SW_PLL) ||                                           \
-    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL          TRUE
-#else
-#define STM32_ACTIVATE_PLL          FALSE
-#endif
-
-/* HSE prescaler setting check.*/
-#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) &&                              \
-    (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
-#error "invalid STM32_PLLXTPRE value specified"
-#endif
-
-/**
- * @brief   PLLMUL field.
- */
-#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
-    defined(__DOXYGEN__)
-#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
-#else
-#error "invalid STM32_PLLMUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
-#define STM32_PLLCLKIN              (STM32_HSECLK / 1)
-#else
-#define STM32_PLLCLKIN              (STM32_HSECLK / 2)
-#endif
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/* PLL input frequency range check.*/
-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
-#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
-#endif
-
-/**
- * @brief   System clock source.
- */
-#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
-#define STM32_SYSCLK                STM32_PLLCLKOUT
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/* AHB frequency check.*/
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                 (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                 (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                 (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                 (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/* APB1 frequency check.*/
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief   APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                 (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                 (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                 (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                 (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/**
- * @brief   RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                (STM32_HSECLK / 128)
-#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
-#define STM32_RTCCLK                0
-#else
-#error "invalid source selected for RTC clock"
-#endif
-
-/**
- * @brief   ADC frequency.
- */
-#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_ADCCLK                (STM32_PCLK2 / 2)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
-#define STM32_ADCCLK                (STM32_PCLK2 / 4)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
-#define STM32_ADCCLK                (STM32_PCLK2 / 6)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
-#define STM32_ADCCLK                (STM32_PCLK2 / 8)
-#else
-#error "invalid STM32_ADCPRE value specified"
-#endif
-
-/* ADC frequency check.*/
-#if STM32_ADCCLK > STM32_ADCCLK_MAX
-#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/**
- * @brief   USB frequency.
- */
-#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
-#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
-#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
-#define STM32_USBCLK                STM32_PLLCLKOUT
-#else
-#error "invalid STM32_USBPRE value specified"
-#endif
-
-/**
- * @brief   Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief   Timers 1, 8, 9, 10, 11 clock.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
-#endif
-
-/**
- * @brief   Flash settings.
- */
-#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS             0x00000010
-#elif STM32_HCLK <= 48000000
-#define STM32_FLASHBITS             0x00000011
-#else
-#define STM32_FLASHBITS             0x00000012
-#endif
-
-#endif /* _HAL_LLD_F103_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
deleted file mode 100644
index 5805bc532..000000000
--- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
+++ /dev/null
@@ -1,1050 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM32F10X_CL_HAL STM32F105/F107 HAL Support
- * @details HAL support for STM32 Connectivity Line sub-family.
- *
- * @ingroup HAL
- */
-
-/**
- * @file    STM32F1xx/hal_lld_f105_f107.h
- * @brief   STM32F10x Connectivity Line HAL subsystem low level driver header.
- *
- * @addtogroup STM32F10X_CL_HAL
- * @{
- */
-
-#ifndef _HAL_LLD_F105_F107_H_
-#define _HAL_LLD_F105_F107_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Platform identification
- * @{
- */
-#define PLATFORM_NAME           "STM32F10x Connectivity Line"
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum system clock frequency.
- */
-#define STM32_SYSCLK_MAX        72000000
-
-/**
- * @brief   Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX        50000000
-
-/**
- * @brief   Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN        1000000
-
-/**
- * @brief   Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX        1000000
-
-/**
- * @brief   Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN        32768
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLL1IN_MAX        12000000
-
-/**
- * @brief   Maximum PLL1 input clock frequency.
- */
-#define STM32_PLL1IN_MIN        3000000
-
-/**
- * @brief   Maximum PLL1 input clock frequency.
- */
-#define STM32_PLL23IN_MAX       5000000
-
-/**
- * @brief   Maximum PLL2 and PLL3 input clock frequency.
- */
-#define STM32_PLL23IN_MIN       3000000
-
-/**
- * @brief   Maximum PLL1 VCO clock frequency.
- */
-#define STM32_PLL1VCO_MAX       144000000
-
-/**
- * @brief   Maximum PLL1 VCO clock frequency.
- */
-#define STM32_PLL1VCO_MIN       36000000
-
-/**
- * @brief   Maximum PLL2 and PLL3 VCO clock frequency.
- */
-#define STM32_PLL23VCO_MAX      148000000
-
-/**
- * @brief   Maximum PLL2 and PLL3 VCO clock frequency.
- */
-#define STM32_PLL23VCO_MIN      80000000
-
-/**
- * @brief   Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX         36000000
-
-/**
- * @brief   Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX         72000000
-
-/**
- * @brief   Maximum ADC clock frequency.
- */
-#define STM32_ADCCLK_MAX        14000000
-
-/**
- * @brief   Maximum SPI/I2S clock frequency.
- */
-#define STM32_SPII2S_MAX        18000000
-/** @} */
-
-/**
- * @name    RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
-#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
-#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
-
-#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
-#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
-#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
-#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
-#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
-#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
-#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
-#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
-#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
-
-#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
-#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
-#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
-#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
-#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
-
-#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
-#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
-#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
-#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
-#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
-
-#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PPRE2 divided by 2.        */
-#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PPRE2 divided by 4.        */
-#define STM32_ADCPRE_DIV6       (2 << 14)   /**< PPRE2 divided by 6.        */
-#define STM32_ADCPRE_DIV8       (3 << 14)   /**< PPRE2 divided by 8.        */
-
-#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
-#define STM32_PLLSRC_PREDIV1    (1 << 16)   /**< PLL clock source is
-                                                 PREDIV1.                   */
-
-#define STM32_OTGFSPRE_DIV2     (1 << 22)   /**< HCLK*2 divided by 2.       */
-#define STM32_OTGFSPRE_DIV3     (0 << 22)   /**< HCLK*2 divided by 3.       */
-
-#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
-#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
-#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
-#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
-#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
-#define STM32_MCOSEL_PLL2       (8 << 24)   /**< PLL2 clock on MCO pin.     */
-#define STM32_MCOSEL_PLL3DIV2   (9 << 24)   /**< PLL3/2 clock on MCO pin.   */
-#define STM32_MCOSEL_XT1        (10 << 24)  /**< XT1 clock on MCO pin.      */
-#define STM32_MCOSEL_PLL3       (11 << 24)  /**< PLL3 clock on MCO pin.     */
-/** @} */
-
-/**
- * @name    RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
-#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
-#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
-#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
-#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 128 used as
-                                                 RTC clock.                 */
-/** @} */
-
-/**
- * @name    RCC_CFGR2 register bits definitions
- * @{
- */
-#define STM32_PREDIV1SRC_HSE    (0 << 16)   /**< PREDIV1 source is HSE.     */
-#define STM32_PREDIV1SRC_PLL2   (1 << 16)   /**< PREDIV1 source is PLL2.    */
-/** @} */
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    STM32F105/F107 CL capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_HAS_ADC2          TRUE
-#define STM32_HAS_ADC3          FALSE
-#define STM32_HAS_ADC4          FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          TRUE
-#define STM32_HAS_CAN2          TRUE
-#define STM32_CAN_MAX_FILTERS   28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           TRUE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 20
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         TRUE
-#define STM32_HAS_GPIOF         FALSE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_I2C3_RX_DMA_MSK   0
-#define STM32_I2C3_RX_DMA_CHN   0x00000000
-#define STM32_I2C3_TX_DMA_MSK   0
-#define STM32_I2C3_TX_DMA_CHN   0x00000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          TRUE
-#define STM32_SPI3_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 1)
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 2)
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI4          FALSE
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          TRUE
-#define STM32_HAS_TIM5          TRUE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          TRUE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         FALSE
-#define STM32_HAS_TIM15         FALSE
-#define STM32_HAS_TIM16         FALSE
-#define STM32_HAS_TIM17         FALSE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         TRUE
-#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         TRUE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           FALSE
-#define STM32_HAS_OTG1          TRUE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names.                                     */
-/*===========================================================================*/
-
-/**
- * @name  IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler         Vector40    /**< Window Watchdog.           */
-#define PVD_IRQHandler          Vector44    /**< PVD through EXTI Line
-                                                 detect.                    */
-#define TAMPER_IRQHandler       Vector48    /**< Tamper.                    */
-#define RTC_IRQHandler          Vector4C    /**< RTC.                       */
-#define FLASH_IRQHandler        Vector50    /**< Flash.                     */
-#define RCC_IRQHandler          Vector54    /**< RCC.                       */
-#define EXTI0_IRQHandler        Vector58    /**< EXTI Line 0.               */
-#define EXTI1_IRQHandler        Vector5C    /**< EXTI Line 1.               */
-#define EXTI2_IRQHandler        Vector60    /**< EXTI Line 2.               */
-#define EXTI3_IRQHandler        Vector64    /**< EXTI Line 3.               */
-#define EXTI4_IRQHandler        Vector68    /**< EXTI Line 4.               */
-#define DMA1_Ch1_IRQHandler     Vector6C    /**< DMA1 Channel 1.            */
-#define DMA1_Ch2_IRQHandler     Vector70    /**< DMA1 Channel 2.            */
-#define DMA1_Ch3_IRQHandler     Vector74    /**< DMA1 Channel 3.            */
-#define DMA1_Ch4_IRQHandler     Vector78    /**< DMA1 Channel 4.            */
-#define DMA1_Ch5_IRQHandler     Vector7C    /**< DMA1 Channel 5.            */
-#define DMA1_Ch6_IRQHandler     Vector80    /**< DMA1 Channel 6.            */
-#define DMA1_Ch7_IRQHandler     Vector84    /**< DMA1 Channel 7.            */
-#define ADC1_2_IRQHandler       Vector88    /**< ADC1 and ADC2.             */
-#define CAN1_TX_IRQHandler      Vector8C    /**< CAN1 TX.                   */
-#define CAN1_RX0_IRQHandler     Vector90    /**< CAN1 RX0.                  */
-#define CAN1_RX1_IRQHandler     Vector94    /**< CAN1 RX1.                  */
-#define CAN1_SCE_IRQHandler     Vector98    /**< CAN1 SCE.                  */
-#define EXTI9_5_IRQHandler      Vector9C    /**< EXTI Line 9..5.            */
-#define TIM1_BRK_IRQHandler     VectorA0    /**< TIM1 Break.                */
-#define TIM1_UP_IRQHandler      VectorA4    /**< TIM1 Update.               */
-#define TIM1_TRG_COM_IRQHandler VectorA8    /**< TIM1 Trigger and
-                                                 Commutation.               */
-#define TIM1_CC_IRQHandler      VectorAC    /**< TIM1 Capture Compare.      */
-#define TIM2_IRQHandler         VectorB0    /**< TIM2.                      */
-#define TIM3_IRQHandler         VectorB4    /**< TIM3.                      */
-#define TIM4_IRQHandler         VectorB8    /**< TIM4.                      */
-#define I2C1_EV_IRQHandler      VectorBC    /**< I2C1 Event.                */
-#define I2C1_ER_IRQHandler      VectorC0    /**< I2C1 Error.                */
-#define I2C2_EV_IRQHandler      VectorC4    /**< I2C2 Event.                */
-#define I2C2_ER_IRQHandler      VectorC8    /**< I2C1 Error.                */
-#define SPI1_IRQHandler         VectorCC    /**< SPI1.                      */
-#define SPI2_IRQHandler         VectorD0    /**< SPI2.                      */
-#define USART1_IRQHandler       VectorD4    /**< USART1.                    */
-#define USART2_IRQHandler       VectorD8    /**< USART2.                    */
-#define USART3_IRQHandler       VectorDC    /**< USART3.                    */
-#define EXTI15_10_IRQHandler    VectorE0    /**< EXTI Line 15..10.          */
-#define RTC_Alarm_IRQHandler    VectorE4    /**< RTC alarm through EXTI
-                                                 line.                      */
-#define OTG_FS_WKUP_IRQHandler  VectorE8    /**< USB OTG FS Wakeup through
-                                                 EXTI line.                 */
-#define TIM5_IRQHandler         Vector108   /**< TIM5.                      */
-#define SPI3_IRQHandler         Vector10C   /**< SPI3.                      */
-#define UART4_IRQHandler        Vector110   /**< UART4.                     */
-#define UART5_IRQHandler        Vector114   /**< UART5.                     */
-#define TIM6_IRQHandler         Vector118   /**< TIM6.                      */
-#define TIM7_IRQHandler         Vector11C   /**< TIM7.                      */
-#define DMA2_Ch1_IRQHandler     Vector120   /**< DMA2 Channel1.             */
-#define DMA2_Ch2_IRQHandler     Vector124   /**< DMA2 Channel2.             */
-#define DMA2_Ch3_IRQHandler     Vector128   /**< DMA2 Channel3.             */
-#define DMA2_Ch4_IRQHandler     Vector12C   /**< DMA2 Channel4.             */
-#define DMA2_Ch5_IRQHandler     Vector130   /**< DMA2 Channel5.             */
-#define ETH_IRQHandler          Vector134   /**< Ethernet.                  */
-#define ETH_WKUP_IRQHandler     Vector138   /**< Ethernet Wakeup through
-                                                 EXTI line.                 */
-#define CAN2_TX_IRQHandler      Vector13C   /**< CAN2 TX.                   */
-#define CAN2_RX0_IRQHandler     Vector140   /**< CAN2 RX0.                  */
-#define CAN2_RX1_IRQHandler     Vector144   /**< CAN2 RX1.                  */
-#define CAN2_SCE_IRQHandler     Vector148   /**< CAN2 SCE.                  */
-#define OTG_FS_IRQHandler       Vector14C   /**< USB OTG FS.                */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Main clock source selection.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 25MHz crystal using both PLL and PLL2.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW                    STM32_SW_PLL
-#endif
-
-/**
- * @brief   Clock source for the PLL.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 25MHz crystal using both PLL and PLL2.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                STM32_PLLSRC_PREDIV1
-#endif
-
-/**
- * @brief   PREDIV1 clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 25MHz crystal using both PLL and PLL2.
- */
-#if !defined(STM32_PREDIV1SRC) || defined(__DOXYGEN__)
-#define STM32_PREDIV1SRC            STM32_PREDIV1SRC_HSE
-#endif
-
-/**
- * @brief   PREDIV1 division factor.
- * @note    The allowed range is 1...16.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 25MHz crystal using both PLL and PLL2.
- */
-#if !defined(STM32_PREDIV1_VALUE) || defined(__DOXYGEN__)
-#define STM32_PREDIV1_VALUE         5
-#endif
-
-/**
- * @brief   PLL multiplier value.
- * @note    The allowed range is 4...9.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 25MHz crystal using both PLL and PLL2.
- */
-#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE          9
-#endif
-
-/**
- * @brief   PREDIV2 division factor.
- * @note    The allowed range is 1...16.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 25MHz crystal using both PLL and PLL2.
- */
-#if !defined(STM32_PREDIV2_VALUE) || defined(__DOXYGEN__)
-#define STM32_PREDIV2_VALUE         5
-#endif
-
-/**
- * @brief   PLL2 multiplier value.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 25MHz crystal using both PLL and PLL2.
- */
-#if !defined(STM32_PLL2MUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLL2MUL_VALUE         8
-#endif
-
-/**
- * @brief   PLL3 multiplier value.
- * @note    The default value is calculated for a 50MHz clock from
- *          a 25MHz crystal.
- */
-#if !defined(STM32_PLL3MUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLL3MUL_VALUE         10
-#endif
-
-/**
- * @brief   AHB prescaler value.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 25MHz crystal using both PLL and PLL2.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE                  STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief   APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1                 STM32_PPRE1_DIV2
-#endif
-
-/**
- * @brief   APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2                 STM32_PPRE2_DIV2
-#endif
-
-/**
- * @brief   ADC prescaler value.
- */
-#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADCPRE                STM32_ADCPRE_DIV4
-#endif
-
-/**
- * @brief   USB clock setting.
- */
-#if !defined(STM32_OTG_CLOCK_REQUIRED) || defined(__DOXYGEN__)
-#define STM32_OTG_CLOCK_REQUIRED    TRUE
-#endif
-
-/**
- * @brief   OTG prescaler initialization.
- */
-#if !defined(STM32_OTGFSPRE) || defined(__DOXYGEN__)
-#define STM32_OTGFSPRE              STM32_OTGFSPRE_DIV3
-#endif
-
-/**
- * @brief   Dedicated I2S clock setting.
- */
-#if !defined(STM32_I2S_CLOCK_REQUIRED) || defined(__DOXYGEN__)
-#define STM32_I2S_CLOCK_REQUIRED    FALSE
-#endif
-
-/**
- * @brief   MCO pin setting.
- */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL                   STM32_MCOSEL_NOCLOCK
-#endif
-
-/**
- * @brief   RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL                   STM32_RTCSEL_HSEDIV
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F107_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F107_MCUCONF not defined"
-#endif
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCOSEL"
-#endif
-
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE)) ||                                 \
-    (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) ||                              \
-    (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) ||                              \
-    (STM32_MCOSEL == STM32_MCOSEL_XT1)
-#error "HSE not enabled, required by STM32_MCOSEL"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSI
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if (STM32_LSECLK == 0)
-#error "LSE frequency not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/* PLL1 activation conditions.*/
-#if STM32_OTG_CLOCK_REQUIRED ||                                             \
-    (STM32_SW == STM32_SW_PLL) ||                                           \
-    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL1 activation flag.
- */
-#define STM32_ACTIVATE_PLL1         TRUE
-#else
-#define STM32_ACTIVATE_PLL1         FALSE
-#endif
-
-/* PLL2 activation conditions.*/
-#if ((STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) && STM32_ACTIVATE_PLL1) || \
-    (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) ||                              \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL2 activation flag.
- */
-#define STM32_ACTIVATE_PLL2         TRUE
-#else
-#define STM32_ACTIVATE_PLL2         FALSE
-#endif
-
-/* PLL3 activation conditions.*/
-#if STM32_I2S_CLOCK_REQUIRED ||                                             \
-    (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) ||                              \
-    (STM32_MCOSEL == STM32_MCOSEL_PLL3) ||                                  \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL3 activation flag.
- */
-#define STM32_ACTIVATE_PLL3         TRUE
-#else
-#define STM32_ACTIVATE_PLL3         FALSE
-#endif
-
-/**
- * @brief   PREDIV1 field.
- */
-#if (STM32_PREDIV1_VALUE >= 1) && (STM32_PREDIV1_VALUE <= 16) ||            \
-    defined(__DOXYGEN__)
-#define STM32_PREDIV1               ((STM32_PREDIV1_VALUE - 1) << 0)
-#else
-#error "invalid STM32_PREDIV1_VALUE value specified"
-#endif
-
-/**
- * @brief   PREDIV2 field.
- */
-#if (STM32_PREDIV2_VALUE >= 1) && (STM32_PREDIV2_VALUE <= 16) ||            \
-    defined(__DOXYGEN__)
-#define STM32_PREDIV2               ((STM32_PREDIV2_VALUE - 1) << 4)
-#else
-#error "invalid STM32_PREDIV2_VALUE value specified"
-#endif
-
-/**
- * @brief   PLLMUL field.
- */
-#if ((STM32_PLLMUL_VALUE >= 4) && (STM32_PLLMUL_VALUE <= 9)) ||             \
-    defined(__DOXYGEN__)
-#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
-#else
-#error "invalid STM32_PLLMUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL2MUL field.
- */
-#if ((STM32_PLL2MUL_VALUE >= 8) && (STM32_PLL2MUL_VALUE <= 14)) ||          \
-    defined(__DOXYGEN__)
-#define STM32_PLL2MUL               ((STM32_PLL2MUL_VALUE - 2) << 8)
-#elif (STM32_PLL2MUL_VALUE == 16)
-#define STM32_PLL2MUL               (14 << 8)
-#elif (STM32_PLL2MUL_VALUE == 20)
-#define STM32_PLL2MUL               (15 << 8)
-#else
-#error "invalid STM32_PLL2MUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL3MUL field.
- */
-#if ((STM32_PLL3MUL_VALUE >= 8) && (STM32_PLL3MUL_VALUE <= 14)) ||          \
-    defined(__DOXYGEN__)
-#define STM32_PLL3MUL               ((STM32_PLL3MUL_VALUE - 2) << 12)
-#elif (STM32_PLL3MUL_VALUE == 16)
-#define STM32_PLL3MUL               (14 << 12)
-#elif (STM32_PLL3MUL_VALUE == 20)
-#define STM32_PLL3MUL               (15 << 12)
-#else
-#error "invalid STM32_PLL3MUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL2 input frequency.
- */
-#define STM32_PLL2CLKIN             (STM32_HSECLK / STM32_PREDIV2_VALUE)
-
-/* PLL2 input frequency range check.*/
-#if (STM32_PLL2CLKIN < STM32_PLL23IN_MIN) ||                                \
-    (STM32_PLL2CLKIN > STM32_PLL23IN_MAX)
-#error "STM32_PLL2CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)"
-#endif
-
-/**
- * @brief   PLL2 output clock frequency.
- */
-#define STM32_PLL2CLKOUT            (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE)
-
-/**
- * @brief   PLL2 VCO clock frequency.
- */
-#define STM32_PLL2VCO               (STM32_PLL2CLKOUT * 2)
-
-/* PLL2 output frequency range check.*/
-#if (STM32_PLL2VCO < STM32_PLL23VCO_MIN) ||                                 \
-    (STM32_PLL2VCO > STM32_PLL23VCO_MAX)
-#error "STM32_PLL2VCO outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)"
-#endif
-
-/**
- * @brief   PLL3 input frequency.
- */
-#define STM32_PLL3CLKIN             (STM32_HSECLK / STM32_PREDIV2_VALUE)
-
-/* PLL3 input frequency range check.*/
-#if (STM32_PLL3CLKIN < STM32_PLL23IN_MIN) ||                                \
-    (STM32_PLL3CLKIN > STM32_PLL23IN_MAX)
-#error "STM32_PLL3CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)"
-#endif
-
-/**
- * @brief   PLL3 output clock frequency.
- */
-#define STM32_PLL3CLKOUT            (STM32_PLL3CLKIN * STM32_PLL3MUL_VALUE)
-
-/**
- * @brief   PLL3 VCO clock frequency.
- */
-#define STM32_PLL3VCO               (STM32_PLL3CLKOUT * 2)
-
-/* PLL3 output frequency range check.*/
-#if (STM32_PLL3VCO < STM32_PLL23VCO_MIN) ||                                 \
-    (STM32_PLL3VCO > STM32_PLL23VCO_MAX)
-#error "STM32_PLL3CLKOUT outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)"
-#endif
-
-/**
- * @brief   PREDIV1 input frequency.
- */
-#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PREDIV1CLK            STM32_HSECLK
-#elif STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2
-#define STM32_PREDIV1CLK            STM32_PLL2CLKOUT
-#else
-#error "invalid STM32_PREDIV1SRC value specified"
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) || defined(__DOXYGEN__)
-#define STM32_PLLCLKIN              (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/* PLL input frequency range check.*/
-#if (STM32_PLLCLKIN < STM32_PLL1IN_MIN) || (STM32_PLLCLKIN > STM32_PLL1IN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLL1IN_MIN...STM32_PLL1IN_MAX)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-
-/**
- * @brief   PLL VCO clock frequency.
- */
-#define STM32_PLLVCO                (STM32_PLLCLKOUT * 2)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLVCO < STM32_PLL1VCO_MIN) || (STM32_PLLVCO > STM32_PLL1VCO_MAX)
-#error "STM32_PLLVCO outside acceptable range (STM32_PLL1VCO_MIN...STM32_PLL1VCO_MAX)"
-#endif
-
-/**
- * @brief   System clock source.
- */
-#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
-#define STM32_SYSCLK                STM32_PLLCLKOUT
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/* AHB frequency check.*/
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                 (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                 (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                 (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                 (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/* APB1 frequency check.*/
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief   APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                 (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                 (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                 (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                 (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/**
- * @brief   RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                (STM32_HSECLK / 128)
-#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
-#define STM32_RTCCLK                0
-#else
-#error "invalid source selected for RTC clock"
-#endif
-
-/**
- * @brief   ADC frequency.
- */
-#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_ADCCLK                (STM32_PCLK2 / 2)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
-#define STM32_ADCCLK                (STM32_PCLK2 / 4)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
-#define STM32_ADCCLK                (STM32_PCLK2 / 6)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
-#define STM32_ADCCLK                (STM32_PCLK2 / 8)
-#else
-#error "invalid STM32_ADCPRE value specified"
-#endif
-
-/* ADC frequency check.*/
-#if STM32_ADCCLK > STM32_ADCCLK_MAX
-#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/**
- * @brief   OTG frequency.
- */
-#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__)
-#define STM32_OTGFSCLK              (STM32_PLLVCO / 3)
-#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2)
-#define STM32_OTGFSCLK              (STM32_PLLVCO / 2)
-#else
-#error "invalid STM32_OTGFSPRE value specified"
-#endif
-
-/**
- * @brief   Timers 2, 3, 4, 5, 6, 7 clock.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief   Timers 1, 8 clock.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
-#endif
-
-/**
- * @brief   Flash settings.
- */
-#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS             0x00000010
-#elif STM32_HCLK <= 48000000
-#define STM32_FLASHBITS             0x00000011
-#else
-#define STM32_FLASHBITS             0x00000012
-#endif
-
-#endif /* _HAL_LLD_F105_F107_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/platform.dox b/os/hal/platforms/STM32F1xx/platform.dox
deleted file mode 100644
index ecbe2d4e0..000000000
--- a/os/hal/platforms/STM32F1xx/platform.dox
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers
- * @details This section describes all the supported drivers on the STM32F1xx
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup STM32F1xx_HAL STM32F1xx Initialization Support
- * @details The STM32F1xx HAL support is responsible for system initialization.
- *
- * @section stm32f1xx_hal_1 Supported HW resources
- * - PLL1.
- * - PLL2 (where present).
- * - RCC.
- * - Flash.
- * .
- * @section stm32f1xx_hal_2 STM32F1xx HAL driver implementation features
- * - PLLs startup and stabilization.
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash wait states initialization based on the selected clock options.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * - DMA support initialization.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_ADC STM32F1xx ADC Support
- * @details The STM32F1xx ADC driver supports the ADC peripherals using DMA
- *          channels for maximum performance.
- *
- * @section stm32f1xx_adc_1 Supported HW resources
- * - ADC1.
- * - DMA1.
- * .
- * @section stm32f1xx_adc_2 STM32F1xx ADC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Streaming conversion using DMA for maximum performance.
- * - Programmable ADC interrupt priority level.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - DMA errors detection.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_CAN STM32F1xx CAN Support
- * @details The STM32F1xx CAN driver uses the CAN peripherals.
- *
- * @section stm32f1xx_can_1 Supported HW resources
- * - bxCAN1.
- * .
- * @section stm32f1xx_can_2 STM32F1xx CAN driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Support for bxCAN sleep mode.
- * - Programmable bxCAN interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_EXT STM32F1xx EXT Support
- * @details The STM32F1xx EXT driver uses the EXTI peripheral.
- *
- * @section stm32f1xx_ext_1 Supported HW resources
- * - EXTI.
- * .
- * @section stm32f1xx_ext_2 STM32F1xx EXT driver implementation features
- * - Each EXTI channel can be independently enabled and programmed.
- * - Programmable EXTI interrupts priority level.
- * - Capability to work as event sources (WFE) rather than interrupt sources.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_GPT STM32F1xx GPT Support
- * @details The STM32F1xx GPT driver uses the TIMx peripherals.
- *
- * @section stm32f1xx_gpt_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * .
- * @section stm32f1xx_gpt_2 STM32F1xx GPT driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_I2C STM32F1xx I2C Support
- * @details The STM32F1xx I2C driver uses the I2Cx peripherals.
- *
- * @section stm32f1xx_i2c_1 Supported HW resources
- * - I2C1.
- * - I2C2.
- * .
- * @section stm32f1xx_i2c_2 STM32F1xx I2C driver implementation features
- * - Each I2C port can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable I2Cx interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_ICU STM32F1xx ICU Support
- * @details The STM32F1xx ICU driver uses the TIMx peripherals.
- *
- * @section stm32f1xx_icu_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * .
- * @section stm32f1xx_icu_2 STM32F1xx ICU driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_MAC STM32F1xx MAC Support
- * @details The STM32 MAC driver supports the ETH peripheral.
- *
- * @section at91sam7_mac_1 Supported HW resources
- * - ETH.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_PAL STM32F1xx PAL Support
- * @details The STM32F1xx PAL driver uses the GPIO peripherals.
- *
- * @section stm32f1xx_pal_1 Supported HW resources
- * - AFIO.
- * - GPIOA.
- * - GPIOB.
- * - GPIOC.
- * - GPIOD.
- * - GPIOE (where present).
- * - GPIOF (where present).
- * - GPIOG (where present).
- * .
- * @section stm32f1xx_pal_2 STM32F1xx PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 16 bits wide ports.
- * - Atomic set/reset functions.
- * - Atomic set+reset function (atomic bus operations).
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section stm32f1xx_pal_3 Supported PAL setup modes
- * The STM32F1xx PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_INPUT_PULLDOWN.
- * - @p PAL_MODE_INPUT_ANALOG.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard).
- * - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard).
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section stm32f1xx_pal_4 Suboptimal behavior
- * The STM32F1xx GPIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * - Writing on pads/groups/ports programmed as input with pull-up/down
- *   resistor can change the resistor setting because the output latch is
- *   used for resistor selection.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_PWM STM32F1xx PWM Support
- * @details The STM32F1xx PWM driver uses the TIMx peripherals.
- *
- * @section stm32f1xx_pwm_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * .
- * @section stm32f1xx_pwm_2 STM32F1xx PWM driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Four independent PWM channels per timer.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_RTC STM32F1xx RTC Support
- * @details The STM32F1xx RTC driver uses the RTC peripheral.
- *
- * @section stm32f1xx_rtc_1 Supported HW resources
- * - RTC.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_SDC STM32F1xx SDC Support
- * @details The STM32F1xx SDC driver uses the SDIO peripheral.
- *
- * @section stm32f1xx_sdc_1 Supported HW resources
- * - SDIO.
- * - DMA2.
- * .
- * @section stm32f1xx_sdc_2 STM32F1xx SDC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support
- * @details The STM32F1xx Serial driver uses the USART/UART peripherals in a
- *          buffered, interrupt driven, implementation.
- *
- * @section stm32f1xx_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3 (where present).
- * - UART4 (where present).
- * - UART5 (where present).
- * .
- * @section stm32f1xx_serial_2 STM32F1xx Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable priority levels for each UART/USART.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_SPI STM32F1xx SPI Support
- * @details The SPI driver supports the STM32F1xx SPI peripherals using DMA
- *          channels for maximum performance.
- *
- * @section stm32f1xx_spi_1 Supported HW resources
- * - SPI1.
- * - SPI2.
- * - SPI3 (where present).
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32f1xx_spi_2 STM32F1xx SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SPI can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each SPI.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_UART STM32F1xx UART Support
- * @details The UART driver supports the STM32F1xx USART peripherals using DMA
- *          channels for maximum performance.
- *
- * @section stm32f1xx_uart_1 Supported HW resources
- * The UART driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3 (where present).
- * - UART4 (where present).
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32f1xx_uart_2 STM32F1xx UART driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each UART/USART.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_USB STM32F1xx USB Support
- * @details The USB driver supports the STM32F1xx USB peripheral.
- *
- * @section stm32f1xx_usb_1 Supported HW resources
- * The USB driver can support any of the following hardware resources:
- * - USB.
- * .
- * @section stm32f1xx_usb_2 STM32F1xx USB driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority levels.
- * - Each endpoint programmable in Control, Bulk and Interrupt modes.
- * .
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_PLATFORM_DRIVERS STM32F1xx Platform Drivers
- * @details Platform support drivers. Platform drivers do not implement HAL
- *          standard driver templates, their role is to support platform
- *          specific functionalities.
- *
- * @ingroup STM32F1xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_DMA STM32F1xx DMA Support
- * @details This DMA helper driver is used by the other drivers in order to
- *          access the shared DMA resources in a consistent way.
- *
- * @section stm32f1xx_dma_1 Supported HW resources
- * The DMA driver can support any of the following hardware resources:
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features
- * - Exports helper functions/macros to the other drivers that share the
- *   DMA resource.
- * - Automatic DMA clock stop when not in use by any driver.
- * - DMA streams and interrupt vectors sharing among multiple drivers.
- * .
- * @ingroup STM32F1xx_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_ISR STM32F1xx ISR Support
- * @details This ISR helper driver is used by the other drivers in order to
- *          map ISR names to physical vector names.
- *
- * @ingroup STM32F1xx_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup STM32F1xx_RCC STM32F1xx RCC Support
- * @details This RCC helper driver is used by the other drivers in order to
- *          access the shared RCC resources in a consistent way.
- *
- * @section stm32f1xx_rcc_1 Supported HW resources
- * - RCC.
- * .
- * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features
- * - Peripherals reset.
- * - Peripherals clock enable.
- * - Peripherals clock disable.
- * .
- * @ingroup STM32F1xx_PLATFORM_DRIVERS
- */
diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk
deleted file mode 100644
index 8a4a3c778..000000000
--- a/os/hal/platforms/STM32F1xx/platform.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-# List of all the STM32F1xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \
-              ${CHIBIOS}/os/hal/platforms/STM32 \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USBv1
-
diff --git a/os/hal/platforms/STM32F1xx/platform_f105_f107.mk b/os/hal/platforms/STM32F1xx/platform_f105_f107.mk
deleted file mode 100644
index 88595f8ad..000000000
--- a/os/hal/platforms/STM32F1xx/platform_f105_f107.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-# List of all the STM32F1xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
-			  ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
-			  ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \
-              ${CHIBIOS}/os/hal/platforms/STM32 \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/OTGv1
diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.c b/os/hal/platforms/STM32F1xx/stm32_dma.c
deleted file mode 100644
index d4141d114..000000000
--- a/os/hal/platforms/STM32F1xx/stm32_dma.c
+++ /dev/null
@@ -1,492 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F1xx/stm32_dma.c
- * @brief   DMA helper driver code.
- *
- * @addtogroup STM32F1xx_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- *          shared resource, this driver allows to allocate and free DMA
- *          streams at runtime in order to allow all the other device
- *          drivers to coordinate the access to the resource.
- * @note    The DMA ISR handlers are all declared into this module because
- *          sharing, the various device drivers can associate a callback to
- *          ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
-   has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK     0x0000007F
-
-/**
- * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK     0x00000F80
-
-/**
- * @brief   Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE   0x00000000
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- *          identifier and the involved physical registers.
- * @note    Don't use this array directly, use the appropriate wrapper macros
- *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
-  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
-  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
-  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
-  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
-  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
-  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
-  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
-  {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
-  {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
-  {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
-#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
-  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
-  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
-#else /* !STM32F10X_CL */
-  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn},
-  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn},
-#endif /* !STM32F10X_CL */
-#endif /* STM32_HAS_DMA2 */
-};
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DMA ISR redirector type.
- */
-typedef struct {
-  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
-  void                  *dma_param;     /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief   Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief   DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 0;
-  if (dma_isr_redir[0].dma_func)
-    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 4;
-  if (dma_isr_redir[1].dma_func)
-    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 8;
-  if (dma_isr_redir[2].dma_func)
-    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 12;
-  if (dma_isr_redir[3].dma_func)
-    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 16;
-  if (dma_isr_redir[4].dma_func)
-    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 20;
-  if (dma_isr_redir[5].dma_func)
-    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 24;
-  if (dma_isr_redir[6].dma_func)
-    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
-/**
- * @brief   DMA2 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 0;
-  if (dma_isr_redir[7].dma_func)
-    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 4;
-  if (dma_isr_redir[8].dma_func)
-    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 8;
-  if (dma_isr_redir[9].dma_func)
-    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
-/**
- * @brief   DMA2 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 12;
-  if (dma_isr_redir[10].dma_func)
-    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 16;
-  if (dma_isr_redir[11].dma_func)
-    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-#else /* !STM32F10X_CL */
-/**
- * @brief   DMA2 streams 4 and 5 shared interrupt handler.
- * @note    This IRQ is shared between DMA2 channels 4 and 5 so it is a
- *          bit less efficient because an extra check.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  /* Check on channel 4.*/
-  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  if (flags & STM32_DMA_ISR_MASK) {
-    DMA2->IFCR = flags << 12;
-    if (dma_isr_redir[10].dma_func)
-      dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
-  }
-
-  /* Check on channel 5.*/
-  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  if (flags & STM32_DMA_ISR_MASK) {
-    DMA2->IFCR = flags << 16;
-    if (dma_isr_redir[11].dma_func)
-      dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
-  }
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* !STM32F10X_CL */
-#endif /* STM32_HAS_DMA2 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
-  int i;
-
-  dma_streams_mask = 0;
-  for (i = 0; i < STM32_DMA_STREAMS; i++) {
-    _stm32_dma_streams[i].channel->CCR = 0;
-    dma_isr_redir[i].dma_func = NULL;
-  }
-  DMA1->IFCR = 0xFFFFFFFF;
-#if STM32_HAS_DMA2
-  DMA2->IFCR = 0xFFFFFFFF;
-#endif
-}
-
-/**
- * @brief   Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- *          The function also enables the IRQ vector associated to the stream
- *          and initializes its priority.
- * @pre     The stream must not be already in use or an error is returned.
- * @post    The stream is allocated and the default ISR handler redirected
- *          to the specified function.
- * @post    The stream ISR vector is enabled and its priority configured.
- * @post    The stream must be freed using @p dmaStreamRelease() before it can
- *          be reused with another peripheral.
- * @post    The stream is in its post-reset state.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] priority  IRQ priority mask for the DMA stream
- * @param[in] func      handling function pointer, can be @p NULL
- * @param[in] param     a parameter to be passed to the handling function
- * @return              The operation status.
- * @retval FALSE        no error, stream taken.
- * @retval TRUE         error, stream already taken.
- *
- * @special
- */
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                         uint32_t priority,
-                         stm32_dmaisr_t func,
-                         void *param) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
-
-  /* Checks if the stream is already taken.*/
-  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
-    return TRUE;
-
-  /* Marks the stream as allocated.*/
-  dma_isr_redir[dmastp->selfindex].dma_func  = func;
-  dma_isr_redir[dmastp->selfindex].dma_param = param;
-  dma_streams_mask |= (1 << dmastp->selfindex);
-
-  /* Enabling DMA clocks required by the current streams set.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
-    rccEnableDMA1(FALSE);
-#if STM32_HAS_DMA2
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
-    rccEnableDMA2(FALSE);
-#endif
-
-  /* Putting the stream in a safe state.*/
-  dmaStreamDisable(dmastp);
-  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
-
-  /* Enables the associated IRQ vector if a callback is defined.*/
-  if (func != NULL)
-    nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
-
-  return FALSE;
-}
-
-/**
- * @brief   Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- *          Trying to release a unallocated stream is an illegal operation
- *          and is trapped if assertions are enabled.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    The stream is again available.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamRelease");
-
-  /* Check if the streams is not taken.*/
-  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
-              "dmaStreamRelease(), #1", "not allocated");
-
-  /* Disables the associated IRQ vector.*/
-  nvicDisableVector(dmastp->vector);
-
-  /* Marks the stream as not allocated.*/
-  dma_streams_mask &= ~(1 << dmastp->selfindex);
-
-  /* Shutting down clocks that are no more required, if any.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
-    rccDisableDMA1(FALSE);
-#if STM32_HAS_DMA2
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
-    rccDisableDMA2(FALSE);
-#endif
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h
deleted file mode 100644
index 70737fe7c..000000000
--- a/os/hal/platforms/STM32F1xx/stm32_dma.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F1xx/stm32_dma.h
- * @brief   DMA helper driver header.
- * @note    This file requires definitions from the ST header file stm32f10x.h.
- * @note    This driver uses the new naming convention used for the STM32F2xx
- *          so the "DMA channels" are referred as "DMA streams".
- *
- * @addtogroup STM32F1xx_DMA
- * @{
- */
-
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Total number of DMA streams.
- * @note    This is the total number of streams among all the DMA units.
- */
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
-#define STM32_DMA_STREAMS           12
-#else
-#define STM32_DMA_STREAMS           7
-#endif
-
-/**
- * @brief   Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK          0x0F
-
-/**
- * @brief   Returns the channel associated to the specified stream.
- *
- * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
- * @param[in] c         a stream/channel association word, one channel per
- *                      nibble, not associated channels must be set to 0xF
- * @return              Always zero, in this platform there is no dynamic
- *                      association between streams and channels.
- */
-#define STM32_DMA_GETCHANNEL(n, c)  0
-
-/**
- * @brief   Checks if a DMA priority is within the valid range.
- * @param[in] prio      DMA priority
- *
- * @retval              The check result.
- * @retval FALSE        invalid DMA priority.
- * @retval TRUE         correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
-
-/**
- * @brief   Returns an unique numeric identifier for a DMA stream.
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              An unique numeric stream identifier.
- */
-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
-
-/**
- * @brief   Returns a DMA stream identifier mask.
- *
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              A DMA stream identifier mask.
- */
-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
-  (1 << STM32_DMA_STREAM_ID(dma, stream))
-
-/**
- * @brief   Checks if a DMA stream unique identifier belongs to a mask.
- * @param[in] id        the stream numeric identifier
- * @param[in] mask      the stream numeric identifiers mask
- *
- * @retval              The check result.
- * @retval FALSE        id does not belong to the mask.
- * @retval TRUE         id belongs to the mask.
- */
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
-
-/**
- * @name    DMA streams identifiers
- * @{
- */
-/**
- * @brief   Returns a pointer to a stm32_dma_stream_t structure.
- *
- * @param[in] id        the stream numeric identifier
- * @return              A pointer to the stm32_dma_stream_t constant structure
- *                      associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
-#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
-#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
-#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(7)
-#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(8)
-#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(9)
-#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(10)
-#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(11)
-/** @} */
-
-/**
- * @name    CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN             DMA_CCR1_EN
-#define STM32_DMA_CR_TEIE           DMA_CCR1_TEIE
-#define STM32_DMA_CR_HTIE           DMA_CCR1_HTIE
-#define STM32_DMA_CR_TCIE           DMA_CCR1_TCIE
-#define STM32_DMA_CR_DIR_MASK       (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM)
-#define STM32_DMA_CR_DIR_P2M        0
-#define STM32_DMA_CR_DIR_M2P        DMA_CCR1_DIR
-#define STM32_DMA_CR_DIR_M2M        DMA_CCR1_MEM2MEM
-#define STM32_DMA_CR_CIRC           DMA_CCR1_CIRC
-#define STM32_DMA_CR_PINC           DMA_CCR1_PINC
-#define STM32_DMA_CR_MINC           DMA_CCR1_MINC
-#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR1_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE     0
-#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR1_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR1_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR1_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE     0
-#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR1_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR1_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
-                                     STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK        DMA_CCR1_PL
-#define STM32_DMA_CR_PL(n)          ((n) << 12)
-/** @} */
-
-/**
- * @name    CR register constants only found in enhanced DMA
- * @{
- */
-#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
-/** @} */
-
-/**
- * @name    Status flags passed to the ISR callbacks
- * @{
- */
-#define STM32_DMA_ISR_FEIF          0
-#define STM32_DMA_ISR_DMEIF         0
-#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
-#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
-#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA stream descriptor structure.
- */
-typedef struct {
-  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
-  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
-  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
-                                             register.                      */
-  uint8_t               selfindex;      /**< @brief Index to self in array. */
-  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
-} stm32_dma_stream_t;
-
-/**
- * @brief   STM32 DMA ISR function type.
- *
- * @param[in] p         parameter for the registered function
- * @param[in] flags     pre-shifted content of the ISR register, the bits
- *                      are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Associates a peripheral data register to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CPAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) {                              \
-  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Associates a memory destination to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CMAR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) {                                 \
-  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Sets the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] size      value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) {                         \
-  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
-}
-
-/**
- * @brief   Returns the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @return              The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
-
-/**
- * @brief   Programs the stream mode settings.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) {                                    \
-  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
-}
-
-/**
- * @brief   DMA stream enable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) {                                           \
-  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
-}
-
-/**
- * @brief   DMA stream disable.
- * @details The function disables the specified stream and then clears any
- *          pending interrupt.
- * @note    This function can be invoked in both ISR or thread context.
- * @note    Interrupts enabling flags are set to zero after this call, see
- *          bug 3607518.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) {                                          \
-  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
-                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
-  dmaStreamClearInterrupt(dmastp);                                          \
-}
-
-/**
- * @brief   DMA stream interrupt sources clear.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) {                                   \
-  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
-}
-
-/**
- * @brief   Starts a memory to memory operation using the specified stream.
- * @note    The default transfer data mode is "byte to byte" but it can be
- *          changed by specifying extra options in the @p mode parameter.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register, this value
- *                      is implicitly ORed with:
- *                      - @p STM32_DMA_CR_MINC
- *                      - @p STM32_DMA_CR_PINC
- *                      - @p STM32_DMA_CR_DIR_M2M
- *                      - @p STM32_DMA_CR_EN
- *                      .
- * @param[in] src       source address
- * @param[in] dst       destination address
- * @param[in] n         number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
-  dmaStreamSetPeripheral(dmastp, src);                                      \
-  dmaStreamSetMemory0(dmastp, dst);                                         \
-  dmaStreamSetTransactionSize(dmastp, n);                                   \
-  dmaStreamSetMode(dmastp, (mode) |                                         \
-                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
-                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
-}
-
-/**
- * @brief   Polled wait for DMA transfer end.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) {                                         \
-  while ((dmastp)->channel->CNDTR > 0)                                      \
-    ;                                                                       \
-  dmaStreamDisable(dmastp);                                                 \
-}
-
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dmaInit(void);
-  bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                           uint32_t priority,
-                           stm32_dmaisr_t func,
-                           void *param);
-  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F1xx/stm32f10x.h b/os/hal/platforms/STM32F1xx/stm32f10x.h
deleted file mode 100644
index 6697b9648..000000000
--- a/os/hal/platforms/STM32F1xx/stm32f10x.h
+++ /dev/null
@@ -1,8357 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f10x.h
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32F10x Connectivity line, 
-  *          High density, High density value line, Medium density, 
-  *          Medium density Value line, Low density, Low density Value line 
-  *          and XL-density devices.
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral�s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral�s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_STDPERIPH_DRIVER"
-  *              - To change few application-specific parameters such as the HSE 
-  *                crystal frequency
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x
-  * @{
-  */
-    
-#ifndef __STM32F10x_H
-#define __STM32F10x_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) 
-  /* CHIBIOS FIX */
-#include "board.h"
-  /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices */
-  /* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */  
-  /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices */
-  /* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */  
-  /* #define STM32F10X_HD */     /*!< STM32F10X_HD: STM32 High density devices */
-  /* #define STM32F10X_HD_VL */  /*!< STM32F10X_HD_VL: STM32 High density value line devices */  
-  /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices */
-  /* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */
-#endif
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
-   where the Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density value line devices are STM32F100xx microcontrollers where the Flash
-   memory density ranges between 16 and 32 Kbytes.
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
-   where the Flash memory density ranges between 64 and 128 Kbytes.
- - Medium-density value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 64 and 128 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.   
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-  */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
- #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
-#endif
-
-#if !defined  USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_STDPERIPH_DRIVER*/
-#endif
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application 
-   
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */           
-#if !defined  HSE_VALUE
- #ifdef STM32F10X_CL   
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
- #else 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
- #endif /* STM32F10X_CL */
-#endif /* HSE_VALUE */
-
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-   Timeout value 
-   */
-#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
-
-#define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
-
-/**
- * @brief STM32F10x Standard Peripheral Library version number
-   */
-#define __STM32F10X_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:24] main version */                                  
-#define __STM32F10X_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
-#define __STM32F10X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F10X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F10X_STDPERIPH_VERSION       ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
-                                             |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
-                                             |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
-                                             |(__STM32F10X_STDPERIPH_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#ifdef STM32F10X_XL
- #define __MPU_PRESENT             1 /*!< STM32 XL-density devices provide an MPU */
-#else
- #define __MPU_PRESENT             0 /*!< Other STM32 devices does not provide an MPU */
-#endif /* STM32F10X_XL */
-#define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * @brief STM32F10x Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
-
-/******  STM32 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
-  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
-  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
-
-#ifdef STM32F10X_LD
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
-  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  USB_FS_WKUP_IRQn            = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-#endif /* STM32F10X_LD */  
-
-#ifdef STM32F10X_LD_VL
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
-  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
-  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
-  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
-#endif /* STM32F10X_LD_VL */
-
-#ifdef STM32F10X_MD
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
-  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  USB_FS_WKUP_IRQn            = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-#endif /* STM32F10X_MD */  
-
-#ifdef STM32F10X_MD_VL
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
-  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
-  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
-  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
-#endif /* STM32F10X_MD_VL */
-
-#ifdef STM32F10X_HD
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
-  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */
-  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */
-  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
-  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
-  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
-#endif /* STM32F10X_HD */  
-
-#ifdef STM32F10X_HD_VL
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
-  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
-  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
-  TIM12_IRQn                  = 43,     /*!< TIM12 global Interrupt                               */
-  TIM13_IRQn                  = 44,     /*!< TIM13 global Interrupt                               */
-  TIM14_IRQn                  = 45,     /*!< TIM14 global Interrupt                               */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */  
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
-  TIM7_IRQn                   = 55,     /*!< TIM7 Interrupt                                       */  
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
-  DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
-  DMA2_Channel5_IRQn          = 60      /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is 
-                                             mapped at position 60 only if the MISC_REMAP bit in 
-                                             the AFIO_MAPR2 register is set)                      */       
-#endif /* STM32F10X_HD_VL */
-
-#ifdef STM32F10X_XL
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
-  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
-  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
-#endif /* STM32F10X_XL */  
-
-#ifdef STM32F10X_CL
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
-  CAN1_TX_IRQn                = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
-  CAN1_RX0_IRQn               = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
-  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
-  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
-  /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
-  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
-  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                      */
-  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                      */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                            */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt          */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                    */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                   */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                   */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                   */
-  OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */
-#endif /* STM32F10X_CL */     
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-/* CHIBIOS FIX */
-/*#include "system_stm32f10x.h"*/
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t  s32;
-typedef int16_t s16;
-typedef int8_t  s8;
-
-typedef const int32_t sc32;  /*!< Read Only */
-typedef const int16_t sc16;  /*!< Read Only */
-typedef const int8_t sc8;   /*!< Read Only */
-
-typedef __IO int32_t  vs32;
-typedef __IO int16_t  vs16;
-typedef __IO int8_t   vs8;
-
-typedef __I int32_t vsc32;  /*!< Read Only */
-typedef __I int16_t vsc16;  /*!< Read Only */
-typedef __I int8_t vsc8;   /*!< Read Only */
-
-typedef uint32_t  u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-typedef const uint32_t uc32;  /*!< Read Only */
-typedef const uint16_t uc16;  /*!< Read Only */
-typedef const uint8_t uc8;   /*!< Read Only */
-
-typedef __IO uint32_t  vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t  vu8;
-
-typedef __I uint32_t vuc32;  /*!< Read Only */
-typedef __I uint16_t vuc16;  /*!< Read Only */
-typedef __I uint8_t vuc8;   /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
-#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
-#define HSE_Value            HSE_VALUE
-#define HSI_Value            HSI_VALUE
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;
-  __IO uint32_t CR1;
-  __IO uint32_t CR2;
-  __IO uint32_t SMPR1;
-  __IO uint32_t SMPR2;
-  __IO uint32_t JOFR1;
-  __IO uint32_t JOFR2;
-  __IO uint32_t JOFR3;
-  __IO uint32_t JOFR4;
-  __IO uint32_t HTR;
-  __IO uint32_t LTR;
-  __IO uint32_t SQR1;
-  __IO uint32_t SQR2;
-  __IO uint32_t SQR3;
-  __IO uint32_t JSQR;
-  __IO uint32_t JDR1;
-  __IO uint32_t JDR2;
-  __IO uint32_t JDR3;
-  __IO uint32_t JDR4;
-  __IO uint32_t DR;
-} ADC_TypeDef;
-
-/** 
-  * @brief Backup Registers  
-  */
-
-typedef struct
-{
-  uint32_t  RESERVED0;
-  __IO uint16_t DR1;
-  uint16_t  RESERVED1;
-  __IO uint16_t DR2;
-  uint16_t  RESERVED2;
-  __IO uint16_t DR3;
-  uint16_t  RESERVED3;
-  __IO uint16_t DR4;
-  uint16_t  RESERVED4;
-  __IO uint16_t DR5;
-  uint16_t  RESERVED5;
-  __IO uint16_t DR6;
-  uint16_t  RESERVED6;
-  __IO uint16_t DR7;
-  uint16_t  RESERVED7;
-  __IO uint16_t DR8;
-  uint16_t  RESERVED8;
-  __IO uint16_t DR9;
-  uint16_t  RESERVED9;
-  __IO uint16_t DR10;
-  uint16_t  RESERVED10; 
-  __IO uint16_t RTCCR;
-  uint16_t  RESERVED11;
-  __IO uint16_t CR;
-  uint16_t  RESERVED12;
-  __IO uint16_t CSR;
-  uint16_t  RESERVED13[5];
-  __IO uint16_t DR11;
-  uint16_t  RESERVED14;
-  __IO uint16_t DR12;
-  uint16_t  RESERVED15;
-  __IO uint16_t DR13;
-  uint16_t  RESERVED16;
-  __IO uint16_t DR14;
-  uint16_t  RESERVED17;
-  __IO uint16_t DR15;
-  uint16_t  RESERVED18;
-  __IO uint16_t DR16;
-  uint16_t  RESERVED19;
-  __IO uint16_t DR17;
-  uint16_t  RESERVED20;
-  __IO uint16_t DR18;
-  uint16_t  RESERVED21;
-  __IO uint16_t DR19;
-  uint16_t  RESERVED22;
-  __IO uint16_t DR20;
-  uint16_t  RESERVED23;
-  __IO uint16_t DR21;
-  uint16_t  RESERVED24;
-  __IO uint16_t DR22;
-  uint16_t  RESERVED25;
-  __IO uint16_t DR23;
-  uint16_t  RESERVED26;
-  __IO uint16_t DR24;
-  uint16_t  RESERVED27;
-  __IO uint16_t DR25;
-  uint16_t  RESERVED28;
-  __IO uint16_t DR26;
-  uint16_t  RESERVED29;
-  __IO uint16_t DR27;
-  uint16_t  RESERVED30;
-  __IO uint16_t DR28;
-  uint16_t  RESERVED31;
-  __IO uint16_t DR29;
-  uint16_t  RESERVED32;
-  __IO uint16_t DR30;
-  uint16_t  RESERVED33; 
-  __IO uint16_t DR31;
-  uint16_t  RESERVED34;
-  __IO uint16_t DR32;
-  uint16_t  RESERVED35;
-  __IO uint16_t DR33;
-  uint16_t  RESERVED36;
-  __IO uint16_t DR34;
-  uint16_t  RESERVED37;
-  __IO uint16_t DR35;
-  uint16_t  RESERVED38;
-  __IO uint16_t DR36;
-  uint16_t  RESERVED39;
-  __IO uint16_t DR37;
-  uint16_t  RESERVED40;
-  __IO uint16_t DR38;
-  uint16_t  RESERVED41;
-  __IO uint16_t DR39;
-  uint16_t  RESERVED42;
-  __IO uint16_t DR40;
-  uint16_t  RESERVED43;
-  __IO uint16_t DR41;
-  uint16_t  RESERVED44;
-  __IO uint16_t DR42;
-  uint16_t  RESERVED45;    
-} BKP_TypeDef;
-  
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;
-  __IO uint32_t TDTR;
-  __IO uint32_t TDLR;
-  __IO uint32_t TDHR;
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;
-  __IO uint32_t RDTR;
-  __IO uint32_t RDLR;
-  __IO uint32_t RDHR;
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1;
-  __IO uint32_t FR2;
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t MCR;
-  __IO uint32_t MSR;
-  __IO uint32_t TSR;
-  __IO uint32_t RF0R;
-  __IO uint32_t RF1R;
-  __IO uint32_t IER;
-  __IO uint32_t ESR;
-  __IO uint32_t BTR;
-  uint32_t  RESERVED0[88];
-  CAN_TxMailBox_TypeDef sTxMailBox[3];
-  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
-  uint32_t  RESERVED1[12];
-  __IO uint32_t FMR;
-  __IO uint32_t FM1R;
-  uint32_t  RESERVED2;
-  __IO uint32_t FS1R;
-  uint32_t  RESERVED3;
-  __IO uint32_t FFA1R;
-  uint32_t  RESERVED4;
-  __IO uint32_t FA1R;
-  uint32_t  RESERVED5[8];
-#ifndef STM32F10X_CL
-  CAN_FilterRegister_TypeDef sFilterRegister[14];
-#else
-  CAN_FilterRegister_TypeDef sFilterRegister[28];
-#endif /* STM32F10X_CL */  
-} CAN_TypeDef;
-
-/** 
-  * @brief Consumer Electronics Control (CEC)
-  */
-typedef struct
-{
-  __IO uint32_t CFGR;
-  __IO uint32_t OAR;
-  __IO uint32_t PRES;
-  __IO uint32_t ESR;
-  __IO uint32_t CSR;
-  __IO uint32_t TXD;
-  __IO uint32_t RXD;  
-} CEC_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;
-  __IO uint8_t  IDR;
-  uint8_t   RESERVED0;
-  uint16_t  RESERVED1;
-  __IO uint32_t CR;
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t SWTRIGR;
-  __IO uint32_t DHR12R1;
-  __IO uint32_t DHR12L1;
-  __IO uint32_t DHR8R1;
-  __IO uint32_t DHR12R2;
-  __IO uint32_t DHR12L2;
-  __IO uint32_t DHR8R2;
-  __IO uint32_t DHR12RD;
-  __IO uint32_t DHR12LD;
-  __IO uint32_t DHR8RD;
-  __IO uint32_t DOR1;
-  __IO uint32_t DOR2;
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-  __IO uint32_t SR;
-#endif
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;
-  __IO uint32_t CR;	
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;
-  __IO uint32_t CNDTR;
-  __IO uint32_t CPAR;
-  __IO uint32_t CMAR;
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;
-  __IO uint32_t IFCR;
-} DMA_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-       uint32_t RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-       uint32_t RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-       uint32_t RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-       uint32_t RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-       uint32_t RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-       uint32_t RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-       uint32_t RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-       uint32_t RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-       uint32_t RESERVED8[567];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-       uint32_t RESERVED9[9];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;
-  __IO uint32_t EMR;
-  __IO uint32_t RTSR;
-  __IO uint32_t FTSR;
-  __IO uint32_t SWIER;
-  __IO uint32_t PR;
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;
-  __IO uint32_t KEYR;
-  __IO uint32_t OPTKEYR;
-  __IO uint32_t SR;
-  __IO uint32_t CR;
-  __IO uint32_t AR;
-  __IO uint32_t RESERVED;
-  __IO uint32_t OBR;
-  __IO uint32_t WRPR;
-#ifdef STM32F10X_XL
-  uint32_t RESERVED1[8]; 
-  __IO uint32_t KEYR2;
-  uint32_t RESERVED2;   
-  __IO uint32_t SR2;
-  __IO uint32_t CR2;
-  __IO uint32_t AR2; 
-#endif /* STM32F10X_XL */  
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-  
-typedef struct
-{
-  __IO uint16_t RDP;
-  __IO uint16_t USER;
-  __IO uint16_t Data0;
-  __IO uint16_t Data1;
-  __IO uint16_t WRP0;
-  __IO uint16_t WRP1;
-  __IO uint16_t WRP2;
-  __IO uint16_t WRP3;
-} OB_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;
-  __IO uint32_t SR2;
-  __IO uint32_t PMEM2;
-  __IO uint32_t PATT2;
-  uint32_t  RESERVED0;   
-  __IO uint32_t ECCR2; 
-} FSMC_Bank2_TypeDef;  
-
-/** 
-  * @brief Flexible Static Memory Controller Bank3
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR3;
-  __IO uint32_t SR3;
-  __IO uint32_t PMEM3;
-  __IO uint32_t PATT3;
-  uint32_t  RESERVED0;   
-  __IO uint32_t ECCR3; 
-} FSMC_Bank3_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;
-  __IO uint32_t SR4;
-  __IO uint32_t PMEM4;
-  __IO uint32_t PATT4;
-  __IO uint32_t PIO4; 
-} FSMC_Bank4_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t CRL;
-  __IO uint32_t CRH;
-  __IO uint32_t IDR;
-  __IO uint32_t ODR;
-  __IO uint32_t BSRR;
-  __IO uint32_t BRR;
-  __IO uint32_t LCKR;
-} GPIO_TypeDef;
-
-/** 
-  * @brief Alternate Function I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t EVCR;
-  __IO uint32_t MAPR;
-  __IO uint32_t EXTICR[4];
-  uint32_t RESERVED0;
-  __IO uint32_t MAPR2;  
-} AFIO_TypeDef;
-/** 
-  * @brief Inter Integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;
-  uint16_t  RESERVED0;
-  __IO uint16_t CR2;
-  uint16_t  RESERVED1;
-  __IO uint16_t OAR1;
-  uint16_t  RESERVED2;
-  __IO uint16_t OAR2;
-  uint16_t  RESERVED3;
-  __IO uint16_t DR;
-  uint16_t  RESERVED4;
-  __IO uint16_t SR1;
-  uint16_t  RESERVED5;
-  __IO uint16_t SR2;
-  uint16_t  RESERVED6;
-  __IO uint16_t CCR;
-  uint16_t  RESERVED7;
-  __IO uint16_t TRISE;
-  uint16_t  RESERVED8;
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;
-  __IO uint32_t PR;
-  __IO uint32_t RLR;
-  __IO uint32_t SR;
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CSR;
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CFGR;
-  __IO uint32_t CIR;
-  __IO uint32_t APB2RSTR;
-  __IO uint32_t APB1RSTR;
-  __IO uint32_t AHBENR;
-  __IO uint32_t APB2ENR;
-  __IO uint32_t APB1ENR;
-  __IO uint32_t BDCR;
-  __IO uint32_t CSR;
-
-#ifdef STM32F10X_CL  
-  __IO uint32_t AHBRSTR;
-  __IO uint32_t CFGR2;
-#endif /* STM32F10X_CL */ 
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)   
-  uint32_t RESERVED0;
-  __IO uint32_t CFGR2;
-#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ 
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint16_t CRH;
-  uint16_t  RESERVED0;
-  __IO uint16_t CRL;
-  uint16_t  RESERVED1;
-  __IO uint16_t PRLH;
-  uint16_t  RESERVED2;
-  __IO uint16_t PRLL;
-  uint16_t  RESERVED3;
-  __IO uint16_t DIVH;
-  uint16_t  RESERVED4;
-  __IO uint16_t DIVL;
-  uint16_t  RESERVED5;
-  __IO uint16_t CNTH;
-  uint16_t  RESERVED6;
-  __IO uint16_t CNTL;
-  uint16_t  RESERVED7;
-  __IO uint16_t ALRH;
-  uint16_t  RESERVED8;
-  __IO uint16_t ALRL;
-  uint16_t  RESERVED9;
-} RTC_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;
-  __IO uint32_t CLKCR;
-  __IO uint32_t ARG;
-  __IO uint32_t CMD;
-  __I uint32_t RESPCMD;
-  __I uint32_t RESP1;
-  __I uint32_t RESP2;
-  __I uint32_t RESP3;
-  __I uint32_t RESP4;
-  __IO uint32_t DTIMER;
-  __IO uint32_t DLEN;
-  __IO uint32_t DCTRL;
-  __I uint32_t DCOUNT;
-  __I uint32_t STA;
-  __IO uint32_t ICR;
-  __IO uint32_t MASK;
-  uint32_t  RESERVED0[2];
-  __I uint32_t FIFOCNT;
-  uint32_t  RESERVED1[13];
-  __IO uint32_t FIFO;
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;
-  uint16_t  RESERVED0;
-  __IO uint16_t CR2;
-  uint16_t  RESERVED1;
-  __IO uint16_t SR;
-  uint16_t  RESERVED2;
-  __IO uint16_t DR;
-  uint16_t  RESERVED3;
-  __IO uint16_t CRCPR;
-  uint16_t  RESERVED4;
-  __IO uint16_t RXCRCR;
-  uint16_t  RESERVED5;
-  __IO uint16_t TXCRCR;
-  uint16_t  RESERVED6;
-  __IO uint16_t I2SCFGR;
-  uint16_t  RESERVED7;
-  __IO uint16_t I2SPR;
-  uint16_t  RESERVED8;  
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;
-  uint16_t  RESERVED0;
-  __IO uint16_t CR2;
-  uint16_t  RESERVED1;
-  __IO uint16_t SMCR;
-  uint16_t  RESERVED2;
-  __IO uint16_t DIER;
-  uint16_t  RESERVED3;
-  __IO uint16_t SR;
-  uint16_t  RESERVED4;
-  __IO uint16_t EGR;
-  uint16_t  RESERVED5;
-  __IO uint16_t CCMR1;
-  uint16_t  RESERVED6;
-  __IO uint16_t CCMR2;
-  uint16_t  RESERVED7;
-  __IO uint16_t CCER;
-  uint16_t  RESERVED8;
-  __IO uint16_t CNT;
-  uint16_t  RESERVED9;
-  __IO uint16_t PSC;
-  uint16_t  RESERVED10;
-  __IO uint16_t ARR;
-  uint16_t  RESERVED11;
-  __IO uint16_t RCR;
-  uint16_t  RESERVED12;
-  __IO uint16_t CCR1;
-  uint16_t  RESERVED13;
-  __IO uint16_t CCR2;
-  uint16_t  RESERVED14;
-  __IO uint16_t CCR3;
-  uint16_t  RESERVED15;
-  __IO uint16_t CCR4;
-  uint16_t  RESERVED16;
-  __IO uint16_t BDTR;
-  uint16_t  RESERVED17;
-  __IO uint16_t DCR;
-  uint16_t  RESERVED18;
-  __IO uint16_t DMAR;
-  uint16_t  RESERVED19;
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint16_t SR;
-  uint16_t  RESERVED0;
-  __IO uint16_t DR;
-  uint16_t  RESERVED1;
-  __IO uint16_t BRR;
-  uint16_t  RESERVED2;
-  __IO uint16_t CR1;
-  uint16_t  RESERVED3;
-  __IO uint16_t CR2;
-  uint16_t  RESERVED4;
-  __IO uint16_t CR3;
-  uint16_t  RESERVED5;
-  __IO uint16_t GTPR;
-  uint16_t  RESERVED6;
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CFR;
-  __IO uint32_t SR;
-} WWDG_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
-
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
-#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
-
-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
-#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)
-
-#define SDIO_BASE             (PERIPH_BASE + 0x18000)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
-
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
-
-#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
-
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
-#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
-#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
-
-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define BKP                 ((BKP_TypeDef *) BKP_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */
-#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_2V2                      ((uint16_t)0x0000)     /*!< PVD level 2.2V */
-#define  PWR_CR_PLS_2V3                      ((uint16_t)0x0020)     /*!< PVD level 2.3V */
-#define  PWR_CR_PLS_2V4                      ((uint16_t)0x0040)     /*!< PVD level 2.4V */
-#define  PWR_CR_PLS_2V5                      ((uint16_t)0x0060)     /*!< PVD level 2.5V */
-#define  PWR_CR_PLS_2V6                      ((uint16_t)0x0080)     /*!< PVD level 2.6V */
-#define  PWR_CR_PLS_2V7                      ((uint16_t)0x00A0)     /*!< PVD level 2.7V */
-#define  PWR_CR_PLS_2V8                      ((uint16_t)0x00C0)     /*!< PVD level 2.8V */
-#define  PWR_CR_PLS_2V9                      ((uint16_t)0x00E0)     /*!< PVD level 2.9V */
-
-#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
-
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
-#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Backup registers                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for BKP_DR1 register  ********************/
-#define  BKP_DR1_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR2 register  ********************/
-#define  BKP_DR2_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR3 register  ********************/
-#define  BKP_DR3_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR4 register  ********************/
-#define  BKP_DR4_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR5 register  ********************/
-#define  BKP_DR5_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR6 register  ********************/
-#define  BKP_DR6_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR7 register  ********************/
-#define  BKP_DR7_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR8 register  ********************/
-#define  BKP_DR8_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR9 register  ********************/
-#define  BKP_DR9_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR10 register  *******************/
-#define  BKP_DR10_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR11 register  *******************/
-#define  BKP_DR11_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR12 register  *******************/
-#define  BKP_DR12_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR13 register  *******************/
-#define  BKP_DR13_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR14 register  *******************/
-#define  BKP_DR14_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR15 register  *******************/
-#define  BKP_DR15_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR16 register  *******************/
-#define  BKP_DR16_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR17 register  *******************/
-#define  BKP_DR17_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/******************  Bit definition for BKP_DR18 register  ********************/
-#define  BKP_DR18_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR19 register  *******************/
-#define  BKP_DR19_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR20 register  *******************/
-#define  BKP_DR20_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR21 register  *******************/
-#define  BKP_DR21_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR22 register  *******************/
-#define  BKP_DR22_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR23 register  *******************/
-#define  BKP_DR23_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR24 register  *******************/
-#define  BKP_DR24_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR25 register  *******************/
-#define  BKP_DR25_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR26 register  *******************/
-#define  BKP_DR26_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR27 register  *******************/
-#define  BKP_DR27_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR28 register  *******************/
-#define  BKP_DR28_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR29 register  *******************/
-#define  BKP_DR29_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR30 register  *******************/
-#define  BKP_DR30_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR31 register  *******************/
-#define  BKP_DR31_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR32 register  *******************/
-#define  BKP_DR32_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR33 register  *******************/
-#define  BKP_DR33_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR34 register  *******************/
-#define  BKP_DR34_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR35 register  *******************/
-#define  BKP_DR35_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR36 register  *******************/
-#define  BKP_DR36_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR37 register  *******************/
-#define  BKP_DR37_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR38 register  *******************/
-#define  BKP_DR38_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR39 register  *******************/
-#define  BKP_DR39_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR40 register  *******************/
-#define  BKP_DR40_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR41 register  *******************/
-#define  BKP_DR41_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/*******************  Bit definition for BKP_DR42 register  *******************/
-#define  BKP_DR42_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
-
-/******************  Bit definition for BKP_RTCCR register  *******************/
-#define  BKP_RTCCR_CAL                       ((uint16_t)0x007F)     /*!< Calibration value */
-#define  BKP_RTCCR_CCO                       ((uint16_t)0x0080)     /*!< Calibration Clock Output */
-#define  BKP_RTCCR_ASOE                      ((uint16_t)0x0100)     /*!< Alarm or Second Output Enable */
-#define  BKP_RTCCR_ASOS                      ((uint16_t)0x0200)     /*!< Alarm or Second Output Selection */
-
-/********************  Bit definition for BKP_CR register  ********************/
-#define  BKP_CR_TPE                          ((uint8_t)0x01)        /*!< TAMPER pin enable */
-#define  BKP_CR_TPAL                         ((uint8_t)0x02)        /*!< TAMPER pin active level */
-
-/*******************  Bit definition for BKP_CSR register  ********************/
-#define  BKP_CSR_CTE                         ((uint16_t)0x0001)     /*!< Clear Tamper event */
-#define  BKP_CSR_CTI                         ((uint16_t)0x0002)     /*!< Clear Tamper Interrupt */
-#define  BKP_CSR_TPIE                        ((uint16_t)0x0004)     /*!< TAMPER Pin interrupt enable */
-#define  BKP_CSR_TEF                         ((uint16_t)0x0100)     /*!< Tamper Event Flag */
-#define  BKP_CSR_TIF                         ((uint16_t)0x0200)     /*!< Tamper Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-
-#ifdef STM32F10X_CL
- #define  RCC_CR_PLL2ON                       ((uint32_t)0x04000000)        /*!< PLL2 enable */
- #define  RCC_CR_PLL2RDY                      ((uint32_t)0x08000000)        /*!< PLL2 clock ready flag */
- #define  RCC_CR_PLL3ON                       ((uint32_t)0x10000000)        /*!< PLL3 enable */
- #define  RCC_CR_PLL3RDY                      ((uint32_t)0x20000000)        /*!< PLL3 clock ready flag */
-#endif /* STM32F10X_CL */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-/*!< ADCPPRE configuration */
-#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)        /*!< ADCPRE[1:0] bits (ADC prescaler) */
-#define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)        /*!< Bit 0 */
-#define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)        /*!< Bit 1 */
-
-#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */
-#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */
-#define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */
-#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */
-
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-#ifdef STM32F10X_CL
- #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
- #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
-
- #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
- #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
-
- #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock * 4 */
- #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock * 5 */
- #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock * 6 */
- #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock * 7 */
- #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock * 8 */
- #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock * 9 */
- #define  RCC_CFGR_PLLMULL6_5                ((uint32_t)0x00340000)        /*!< PLL input clock * 6.5 */
- 
- #define  RCC_CFGR_OTGFSPRE                  ((uint32_t)0x00400000)        /*!< USB OTG FS prescaler */
- 
-/*!< MCO configuration */
- #define  RCC_CFGR_MCO                       ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
- #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
- #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
- #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
- #define  RCC_CFGR_MCO_3                     ((uint32_t)0x08000000)        /*!< Bit 3 */
-
- #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
- #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source */
- #define  RCC_CFGR_MCO_PLLCLK_Div2           ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
- #define  RCC_CFGR_MCO_PLL2CLK               ((uint32_t)0x08000000)        /*!< PLL2 clock selected as MCO source*/
- #define  RCC_CFGR_MCO_PLL3CLK_Div2          ((uint32_t)0x09000000)        /*!< PLL3 clock divided by 2 selected as MCO source*/
- #define  RCC_CFGR_MCO_Ext_HSE               ((uint32_t)0x0A000000)        /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
- #define  RCC_CFGR_MCO_PLL3CLK               ((uint32_t)0x0B000000)        /*!< PLL3 clock selected as MCO source */
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
- #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
- #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
-
- #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
- #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
-
- #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
- #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
- #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
- #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
- #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
- #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
- #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
- #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
- #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
- #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
- #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
- #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
- #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
- #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
- #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
-
-/*!< MCO configuration */
- #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
- #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
- #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
- #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
-
- #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
- #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
- #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
-#else
- #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
- #define  RCC_CFGR_PLLSRC_HSE                ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */
-
- #define  RCC_CFGR_PLLXTPRE_HSE              ((uint32_t)0x00000000)        /*!< HSE clock not divided for PLL entry */
- #define  RCC_CFGR_PLLXTPRE_HSE_Div2         ((uint32_t)0x00020000)        /*!< HSE clock divided by 2 for PLL entry */
-
- #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
- #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
- #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
- #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
- #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
- #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
- #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
- #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
- #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
- #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
- #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
- #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
- #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
- #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
- #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
- #define  RCC_CFGR_USBPRE                    ((uint32_t)0x00400000)        /*!< USB Device prescaler */
-
-/*!< MCO configuration */
- #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
- #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
- #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
- #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
-
- #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
- #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
- #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
- #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
-#endif /* STM32F10X_CL */
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-#ifdef STM32F10X_CL
- #define  RCC_CIR_PLL2RDYF                    ((uint32_t)0x00000020)        /*!< PLL2 Ready Interrupt flag */
- #define  RCC_CIR_PLL3RDYF                    ((uint32_t)0x00000040)        /*!< PLL3 Ready Interrupt flag */
- #define  RCC_CIR_PLL2RDYIE                   ((uint32_t)0x00002000)        /*!< PLL2 Ready Interrupt Enable */
- #define  RCC_CIR_PLL3RDYIE                   ((uint32_t)0x00004000)        /*!< PLL3 Ready Interrupt Enable */
- #define  RCC_CIR_PLL2RDYC                    ((uint32_t)0x00200000)        /*!< PLL2 Ready Interrupt Clear */
- #define  RCC_CIR_PLL3RDYC                    ((uint32_t)0x00400000)        /*!< PLL3 Ready Interrupt Clear */
-#endif /* STM32F10X_CL */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */
-#define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)        /*!< I/O port A reset */
-#define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)        /*!< I/O port B reset */
-#define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)        /*!< I/O port C reset */
-#define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)        /*!< I/O port D reset */
-#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define  RCC_APB2RSTR_ADC2RST                ((uint32_t)0x00000400)        /*!< ADC 2 interface reset */
-#endif
-
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 Timer reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI 1 reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 Timer reset */
-#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 Timer reset */
-#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 Timer reset */
-#endif
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define  RCC_APB2RSTR_IOPERST               ((uint32_t)0x00000040)        /*!< I/O port E reset */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
- #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
- #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
- #define  RCC_APB2RSTR_TIM8RST               ((uint32_t)0x00002000)        /*!< TIM8 Timer reset */
- #define  RCC_APB2RSTR_ADC3RST               ((uint32_t)0x00008000)        /*!< ADC3 interface reset */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
- #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
-#endif
-
-#ifdef STM32F10X_XL
- #define  RCC_APB2RSTR_TIM9RST               ((uint32_t)0x00080000)         /*!< TIM9 Timer reset */
- #define  RCC_APB2RSTR_TIM10RST              ((uint32_t)0x00100000)         /*!< TIM10 Timer reset */
- #define  RCC_APB2RSTR_TIM11RST              ((uint32_t)0x00200000)         /*!< TIM11 Timer reset */
-#endif /* STM32F10X_XL */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN1 reset */
-#endif
-
-#define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define  RCC_APB1RSTR_TIM4RST               ((uint32_t)0x00000004)        /*!< Timer 4 reset */
- #define  RCC_APB1RSTR_SPI2RST               ((uint32_t)0x00004000)        /*!< SPI 2 reset */
- #define  RCC_APB1RSTR_USART3RST             ((uint32_t)0x00040000)        /*!< USART 3 reset */
- #define  RCC_APB1RSTR_I2C2RST               ((uint32_t)0x00400000)        /*!< I2C 2 reset */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined  (STM32F10X_XL)
- #define  RCC_APB1RSTR_USBRST                ((uint32_t)0x00800000)        /*!< USB Device reset */
-#endif
-
-#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_XL)
- #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
- #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
- #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
- #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
- #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
- #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
- #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
-#endif
-
-#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
- #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
- #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
- #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
- #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC interface reset */ 
-#endif
-
-#if defined  (STM32F10X_HD_VL)
- #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
- #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< TIM12 Timer reset */
- #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< TIM13 Timer reset */
- #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< TIM14 Timer reset */
- #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */ 
- #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
- #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */ 
-#endif
-
-#ifdef STM32F10X_CL
- #define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)        /*!< CAN2 reset */
-#endif /* STM32F10X_CL */
-
-#ifdef STM32F10X_XL
- #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)         /*!< TIM12 Timer reset */
- #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)         /*!< TIM13 Timer reset */
- #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)         /*!< TIM14 Timer reset */
-#endif /* STM32F10X_XL */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_DMA1EN                   ((uint16_t)0x0001)            /*!< DMA1 clock enable */
-#define  RCC_AHBENR_SRAMEN                   ((uint16_t)0x0004)            /*!< SRAM interface clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint16_t)0x0010)            /*!< FLITF clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint16_t)0x0040)            /*!< CRC clock enable */
-
-/* CHIBIOS FIX */
-//#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL)
-#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL) || defined  (STM32F10X_XL)
- #define  RCC_AHBENR_DMA2EN                  ((uint16_t)0x0002)            /*!< DMA2 clock enable */
-#endif
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
- #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
- #define  RCC_AHBENR_SDIOEN                  ((uint16_t)0x0400)            /*!< SDIO clock enable */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
-#endif
-
-#ifdef STM32F10X_CL
- #define  RCC_AHBENR_OTGFSEN                 ((uint32_t)0x00001000)         /*!< USB OTG FS clock enable */
- #define  RCC_AHBENR_ETHMACEN                ((uint32_t)0x00004000)         /*!< ETHERNET MAC clock enable */
- #define  RCC_AHBENR_ETHMACTXEN              ((uint32_t)0x00008000)         /*!< ETHERNET MAC Tx clock enable */
- #define  RCC_AHBENR_ETHMACRXEN              ((uint32_t)0x00010000)         /*!< ETHERNET MAC Rx clock enable */
-#endif /* STM32F10X_CL */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)         /*!< Alternate Function I/O clock enable */
-#define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)         /*!< I/O port A clock enable */
-#define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)         /*!< I/O port B clock enable */
-#define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)         /*!< I/O port C clock enable */
-#define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)         /*!< I/O port D clock enable */
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC 1 interface clock enable */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000400)         /*!< ADC 2 interface clock enable */
-#endif
-
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)         /*!< TIM1 Timer clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI 1 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)         /*!< TIM15 Timer clock enable */
-#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)         /*!< TIM16 Timer clock enable */
-#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)         /*!< TIM17 Timer clock enable */
-#endif
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define  RCC_APB2ENR_IOPEEN                 ((uint32_t)0x00000040)         /*!< I/O port E clock enable */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
- #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
- #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
- #define  RCC_APB2ENR_TIM8EN                 ((uint32_t)0x00002000)         /*!< TIM8 Timer clock enable */
- #define  RCC_APB2ENR_ADC3EN                 ((uint32_t)0x00008000)         /*!< DMA1 clock enable */
-#endif
-
-#if defined (STM32F10X_HD_VL)
- #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
- #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
-#endif
-
-#ifdef STM32F10X_XL
- #define  RCC_APB2ENR_TIM9EN                 ((uint32_t)0x00080000)         /*!< TIM9 Timer clock enable  */
- #define  RCC_APB2ENR_TIM10EN                ((uint32_t)0x00100000)         /*!< TIM10 Timer clock enable  */
- #define  RCC_APB2ENR_TIM11EN                ((uint32_t)0x00200000)         /*!< TIM11 Timer clock enable */
-#endif
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
-
-#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN1 clock enable */
-#endif
-
-#define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
-
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
- #define  RCC_APB1ENR_TIM4EN                 ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
- #define  RCC_APB1ENR_SPI2EN                 ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
- #define  RCC_APB1ENR_USART3EN               ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
- #define  RCC_APB1ENR_I2C2EN                 ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
-#endif /* STM32F10X_LD && STM32F10X_LD_VL */
-
-/* CHIBIOS FIX */
-//#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)
-#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)
- #define  RCC_APB1ENR_USBEN                  ((uint32_t)0x00800000)        /*!< USB Device clock enable */
-#endif
-
-/* CHIBIOS FIX */
-//#if defined (STM32F10X_HD) || defined  (STM32F10X_CL)
-#if defined (STM32F10X_XL) || defined (STM32F10X_HD) || defined  (STM32F10X_CL)
- #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
- #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
- #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
- #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
- #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
- #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
- #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
-#endif
-
-#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
- #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
- #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
- #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
- #define  RCC_APB1ENR_CECEN                  ((uint32_t)0x40000000)        /*!< CEC interface clock enable */ 
-#endif
-
-#ifdef STM32F10X_HD_VL
- #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
- #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
- #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
- #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
- #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
- #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
- #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */ 
-#endif /* STM32F10X_HD_VL */
-
-#ifdef STM32F10X_CL
- #define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)        /*!< CAN2 clock enable */
-#endif /* STM32F10X_CL */
-
-#ifdef STM32F10X_XL
- #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
- #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
- #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
-#endif /* STM32F10X_XL */
-
-/*******************  Bit definition for RCC_BDCR register  *******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
-
-#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
-
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
-
-/*******************  Bit definition for RCC_CSR register  ********************/  
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-#ifdef STM32F10X_CL
-/*******************  Bit definition for RCC_AHBRSTR register  ****************/
- #define  RCC_AHBRSTR_OTGFSRST               ((uint32_t)0x00001000)         /*!< USB OTG FS reset */
- #define  RCC_AHBRSTR_ETHMACRST              ((uint32_t)0x00004000)         /*!< ETHERNET MAC reset */
-
-/*******************  Bit definition for RCC_CFGR2 register  ******************/
-/*!< PREDIV1 configuration */
- #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
- #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
- #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
- #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
- #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
- #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
- #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
- #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
- #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
- #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
- #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
- #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
- #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
- #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
- #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
- #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
- #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
- #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
- #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
- #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
-
-/*!< PREDIV2 configuration */
- #define  RCC_CFGR2_PREDIV2                  ((uint32_t)0x000000F0)        /*!< PREDIV2[3:0] bits */
- #define  RCC_CFGR2_PREDIV2_0                ((uint32_t)0x00000010)        /*!< Bit 0 */
- #define  RCC_CFGR2_PREDIV2_1                ((uint32_t)0x00000020)        /*!< Bit 1 */
- #define  RCC_CFGR2_PREDIV2_2                ((uint32_t)0x00000040)        /*!< Bit 2 */
- #define  RCC_CFGR2_PREDIV2_3                ((uint32_t)0x00000080)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PREDIV2_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV2 input clock not divided */
- #define  RCC_CFGR2_PREDIV2_DIV2             ((uint32_t)0x00000010)        /*!< PREDIV2 input clock divided by 2 */
- #define  RCC_CFGR2_PREDIV2_DIV3             ((uint32_t)0x00000020)        /*!< PREDIV2 input clock divided by 3 */
- #define  RCC_CFGR2_PREDIV2_DIV4             ((uint32_t)0x00000030)        /*!< PREDIV2 input clock divided by 4 */
- #define  RCC_CFGR2_PREDIV2_DIV5             ((uint32_t)0x00000040)        /*!< PREDIV2 input clock divided by 5 */
- #define  RCC_CFGR2_PREDIV2_DIV6             ((uint32_t)0x00000050)        /*!< PREDIV2 input clock divided by 6 */
- #define  RCC_CFGR2_PREDIV2_DIV7             ((uint32_t)0x00000060)        /*!< PREDIV2 input clock divided by 7 */
- #define  RCC_CFGR2_PREDIV2_DIV8             ((uint32_t)0x00000070)        /*!< PREDIV2 input clock divided by 8 */
- #define  RCC_CFGR2_PREDIV2_DIV9             ((uint32_t)0x00000080)        /*!< PREDIV2 input clock divided by 9 */
- #define  RCC_CFGR2_PREDIV2_DIV10            ((uint32_t)0x00000090)        /*!< PREDIV2 input clock divided by 10 */
- #define  RCC_CFGR2_PREDIV2_DIV11            ((uint32_t)0x000000A0)        /*!< PREDIV2 input clock divided by 11 */
- #define  RCC_CFGR2_PREDIV2_DIV12            ((uint32_t)0x000000B0)        /*!< PREDIV2 input clock divided by 12 */
- #define  RCC_CFGR2_PREDIV2_DIV13            ((uint32_t)0x000000C0)        /*!< PREDIV2 input clock divided by 13 */
- #define  RCC_CFGR2_PREDIV2_DIV14            ((uint32_t)0x000000D0)        /*!< PREDIV2 input clock divided by 14 */
- #define  RCC_CFGR2_PREDIV2_DIV15            ((uint32_t)0x000000E0)        /*!< PREDIV2 input clock divided by 15 */
- #define  RCC_CFGR2_PREDIV2_DIV16            ((uint32_t)0x000000F0)        /*!< PREDIV2 input clock divided by 16 */
-
-/*!< PLL2MUL configuration */
- #define  RCC_CFGR2_PLL2MUL                  ((uint32_t)0x00000F00)        /*!< PLL2MUL[3:0] bits */
- #define  RCC_CFGR2_PLL2MUL_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
- #define  RCC_CFGR2_PLL2MUL_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
- #define  RCC_CFGR2_PLL2MUL_2                ((uint32_t)0x00000400)        /*!< Bit 2 */
- #define  RCC_CFGR2_PLL2MUL_3                ((uint32_t)0x00000800)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PLL2MUL8                 ((uint32_t)0x00000600)        /*!< PLL2 input clock * 8 */
- #define  RCC_CFGR2_PLL2MUL9                 ((uint32_t)0x00000700)        /*!< PLL2 input clock * 9 */
- #define  RCC_CFGR2_PLL2MUL10                ((uint32_t)0x00000800)        /*!< PLL2 input clock * 10 */
- #define  RCC_CFGR2_PLL2MUL11                ((uint32_t)0x00000900)        /*!< PLL2 input clock * 11 */
- #define  RCC_CFGR2_PLL2MUL12                ((uint32_t)0x00000A00)        /*!< PLL2 input clock * 12 */
- #define  RCC_CFGR2_PLL2MUL13                ((uint32_t)0x00000B00)        /*!< PLL2 input clock * 13 */
- #define  RCC_CFGR2_PLL2MUL14                ((uint32_t)0x00000C00)        /*!< PLL2 input clock * 14 */
- #define  RCC_CFGR2_PLL2MUL16                ((uint32_t)0x00000E00)        /*!< PLL2 input clock * 16 */
- #define  RCC_CFGR2_PLL2MUL20                ((uint32_t)0x00000F00)        /*!< PLL2 input clock * 20 */
-
-/*!< PLL3MUL configuration */
- #define  RCC_CFGR2_PLL3MUL                  ((uint32_t)0x0000F000)        /*!< PLL3MUL[3:0] bits */
- #define  RCC_CFGR2_PLL3MUL_0                ((uint32_t)0x00001000)        /*!< Bit 0 */
- #define  RCC_CFGR2_PLL3MUL_1                ((uint32_t)0x00002000)        /*!< Bit 1 */
- #define  RCC_CFGR2_PLL3MUL_2                ((uint32_t)0x00004000)        /*!< Bit 2 */
- #define  RCC_CFGR2_PLL3MUL_3                ((uint32_t)0x00008000)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PLL3MUL8                 ((uint32_t)0x00006000)        /*!< PLL3 input clock * 8 */
- #define  RCC_CFGR2_PLL3MUL9                 ((uint32_t)0x00007000)        /*!< PLL3 input clock * 9 */
- #define  RCC_CFGR2_PLL3MUL10                ((uint32_t)0x00008000)        /*!< PLL3 input clock * 10 */
- #define  RCC_CFGR2_PLL3MUL11                ((uint32_t)0x00009000)        /*!< PLL3 input clock * 11 */
- #define  RCC_CFGR2_PLL3MUL12                ((uint32_t)0x0000A000)        /*!< PLL3 input clock * 12 */
- #define  RCC_CFGR2_PLL3MUL13                ((uint32_t)0x0000B000)        /*!< PLL3 input clock * 13 */
- #define  RCC_CFGR2_PLL3MUL14                ((uint32_t)0x0000C000)        /*!< PLL3 input clock * 14 */
- #define  RCC_CFGR2_PLL3MUL16                ((uint32_t)0x0000E000)        /*!< PLL3 input clock * 16 */
- #define  RCC_CFGR2_PLL3MUL20                ((uint32_t)0x0000F000)        /*!< PLL3 input clock * 20 */
-
- #define  RCC_CFGR2_PREDIV1SRC               ((uint32_t)0x00010000)        /*!< PREDIV1 entry clock source */
- #define  RCC_CFGR2_PREDIV1SRC_PLL2          ((uint32_t)0x00010000)        /*!< PLL2 selected as PREDIV1 entry clock source */
- #define  RCC_CFGR2_PREDIV1SRC_HSE           ((uint32_t)0x00000000)        /*!< HSE selected as PREDIV1 entry clock source */
- #define  RCC_CFGR2_I2S2SRC                  ((uint32_t)0x00020000)        /*!< I2S2 entry clock source */
- #define  RCC_CFGR2_I2S3SRC                  ((uint32_t)0x00040000)        /*!< I2S3 clock source */
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/*******************  Bit definition for RCC_CFGR2 register  ******************/
-/*!< PREDIV1 configuration */
- #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
- #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
- #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
- #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
- #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-
- #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
- #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
- #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
- #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
- #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
- #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
- #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
- #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
- #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
- #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
- #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
- #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
- #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
- #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
- #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
- #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
-#endif
- 
-/******************************************************************************/
-/*                                                                            */
-/*                General Purpose and Alternate Function I/O                  */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for GPIO_CRL register  *******************/
-#define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
-
-#define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
-#define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
-#define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
-#define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
-#define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
-#define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
-#define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
-#define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
-#define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
-
-#define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
-#define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
-#define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
-#define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
-#define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
-#define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
-#define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
-#define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
-
-#define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
-#define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
-#define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
-
-/*******************  Bit definition for GPIO_CRH register  *******************/
-#define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
-
-#define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
-#define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
-#define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
-#define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
-#define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
-#define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
-#define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
-#define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
-#define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
-
-#define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
-#define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
-#define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
-#define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
-#define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
-#define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
-#define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
-#define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
-
-#define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
-#define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
-#define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
-
-/*!<******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR0                        ((uint16_t)0x0001)            /*!< Port input data, bit 0 */
-#define GPIO_IDR_IDR1                        ((uint16_t)0x0002)            /*!< Port input data, bit 1 */
-#define GPIO_IDR_IDR2                        ((uint16_t)0x0004)            /*!< Port input data, bit 2 */
-#define GPIO_IDR_IDR3                        ((uint16_t)0x0008)            /*!< Port input data, bit 3 */
-#define GPIO_IDR_IDR4                        ((uint16_t)0x0010)            /*!< Port input data, bit 4 */
-#define GPIO_IDR_IDR5                        ((uint16_t)0x0020)            /*!< Port input data, bit 5 */
-#define GPIO_IDR_IDR6                        ((uint16_t)0x0040)            /*!< Port input data, bit 6 */
-#define GPIO_IDR_IDR7                        ((uint16_t)0x0080)            /*!< Port input data, bit 7 */
-#define GPIO_IDR_IDR8                        ((uint16_t)0x0100)            /*!< Port input data, bit 8 */
-#define GPIO_IDR_IDR9                        ((uint16_t)0x0200)            /*!< Port input data, bit 9 */
-#define GPIO_IDR_IDR10                       ((uint16_t)0x0400)            /*!< Port input data, bit 10 */
-#define GPIO_IDR_IDR11                       ((uint16_t)0x0800)            /*!< Port input data, bit 11 */
-#define GPIO_IDR_IDR12                       ((uint16_t)0x1000)            /*!< Port input data, bit 12 */
-#define GPIO_IDR_IDR13                       ((uint16_t)0x2000)            /*!< Port input data, bit 13 */
-#define GPIO_IDR_IDR14                       ((uint16_t)0x4000)            /*!< Port input data, bit 14 */
-#define GPIO_IDR_IDR15                       ((uint16_t)0x8000)            /*!< Port input data, bit 15 */
-
-/*******************  Bit definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR0                        ((uint16_t)0x0001)            /*!< Port output data, bit 0 */
-#define GPIO_ODR_ODR1                        ((uint16_t)0x0002)            /*!< Port output data, bit 1 */
-#define GPIO_ODR_ODR2                        ((uint16_t)0x0004)            /*!< Port output data, bit 2 */
-#define GPIO_ODR_ODR3                        ((uint16_t)0x0008)            /*!< Port output data, bit 3 */
-#define GPIO_ODR_ODR4                        ((uint16_t)0x0010)            /*!< Port output data, bit 4 */
-#define GPIO_ODR_ODR5                        ((uint16_t)0x0020)            /*!< Port output data, bit 5 */
-#define GPIO_ODR_ODR6                        ((uint16_t)0x0040)            /*!< Port output data, bit 6 */
-#define GPIO_ODR_ODR7                        ((uint16_t)0x0080)            /*!< Port output data, bit 7 */
-#define GPIO_ODR_ODR8                        ((uint16_t)0x0100)            /*!< Port output data, bit 8 */
-#define GPIO_ODR_ODR9                        ((uint16_t)0x0200)            /*!< Port output data, bit 9 */
-#define GPIO_ODR_ODR10                       ((uint16_t)0x0400)            /*!< Port output data, bit 10 */
-#define GPIO_ODR_ODR11                       ((uint16_t)0x0800)            /*!< Port output data, bit 11 */
-#define GPIO_ODR_ODR12                       ((uint16_t)0x1000)            /*!< Port output data, bit 12 */
-#define GPIO_ODR_ODR13                       ((uint16_t)0x2000)            /*!< Port output data, bit 13 */
-#define GPIO_ODR_ODR14                       ((uint16_t)0x4000)            /*!< Port output data, bit 14 */
-#define GPIO_ODR_ODR15                       ((uint16_t)0x8000)            /*!< Port output data, bit 15 */
-
-/******************  Bit definition for GPIO_BSRR register  *******************/
-#define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
-#define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
-#define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
-#define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
-#define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
-#define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
-#define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
-#define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
-#define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
-#define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
-#define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
-#define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
-#define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
-#define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
-#define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
-#define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
-
-#define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
-#define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
-#define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
-#define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
-#define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
-#define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
-#define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
-#define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
-#define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
-#define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
-#define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
-#define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
-#define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
-#define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
-#define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
-#define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
-
-/*******************  Bit definition for GPIO_BRR register  *******************/
-#define GPIO_BRR_BR0                         ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */
-#define GPIO_BRR_BR1                         ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */
-#define GPIO_BRR_BR2                         ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */
-#define GPIO_BRR_BR3                         ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */
-#define GPIO_BRR_BR4                         ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */
-#define GPIO_BRR_BR5                         ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */
-#define GPIO_BRR_BR6                         ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */
-#define GPIO_BRR_BR7                         ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */
-#define GPIO_BRR_BR8                         ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */
-#define GPIO_BRR_BR9                         ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */
-#define GPIO_BRR_BR10                        ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */
-#define GPIO_BRR_BR11                        ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */
-#define GPIO_BRR_BR12                        ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */
-#define GPIO_BRR_BR13                        ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */
-#define GPIO_BRR_BR14                        ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */
-#define GPIO_BRR_BR15                        ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */
-
-/******************  Bit definition for GPIO_LCKR register  *******************/
-#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
-#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
-#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
-#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
-#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
-#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
-#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
-#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
-#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
-#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
-#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
-#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
-#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
-#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
-#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
-#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
-#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for AFIO_EVCR register  *******************/
-#define AFIO_EVCR_PIN                        ((uint8_t)0x0F)               /*!< PIN[3:0] bits (Pin selection) */
-#define AFIO_EVCR_PIN_0                      ((uint8_t)0x01)               /*!< Bit 0 */
-#define AFIO_EVCR_PIN_1                      ((uint8_t)0x02)               /*!< Bit 1 */
-#define AFIO_EVCR_PIN_2                      ((uint8_t)0x04)               /*!< Bit 2 */
-#define AFIO_EVCR_PIN_3                      ((uint8_t)0x08)               /*!< Bit 3 */
-
-/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0                    ((uint8_t)0x00)               /*!< Pin 0 selected */
-#define AFIO_EVCR_PIN_PX1                    ((uint8_t)0x01)               /*!< Pin 1 selected */
-#define AFIO_EVCR_PIN_PX2                    ((uint8_t)0x02)               /*!< Pin 2 selected */
-#define AFIO_EVCR_PIN_PX3                    ((uint8_t)0x03)               /*!< Pin 3 selected */
-#define AFIO_EVCR_PIN_PX4                    ((uint8_t)0x04)               /*!< Pin 4 selected */
-#define AFIO_EVCR_PIN_PX5                    ((uint8_t)0x05)               /*!< Pin 5 selected */
-#define AFIO_EVCR_PIN_PX6                    ((uint8_t)0x06)               /*!< Pin 6 selected */
-#define AFIO_EVCR_PIN_PX7                    ((uint8_t)0x07)               /*!< Pin 7 selected */
-#define AFIO_EVCR_PIN_PX8                    ((uint8_t)0x08)               /*!< Pin 8 selected */
-#define AFIO_EVCR_PIN_PX9                    ((uint8_t)0x09)               /*!< Pin 9 selected */
-#define AFIO_EVCR_PIN_PX10                   ((uint8_t)0x0A)               /*!< Pin 10 selected */
-#define AFIO_EVCR_PIN_PX11                   ((uint8_t)0x0B)               /*!< Pin 11 selected */
-#define AFIO_EVCR_PIN_PX12                   ((uint8_t)0x0C)               /*!< Pin 12 selected */
-#define AFIO_EVCR_PIN_PX13                   ((uint8_t)0x0D)               /*!< Pin 13 selected */
-#define AFIO_EVCR_PIN_PX14                   ((uint8_t)0x0E)               /*!< Pin 14 selected */
-#define AFIO_EVCR_PIN_PX15                   ((uint8_t)0x0F)               /*!< Pin 15 selected */
-
-#define AFIO_EVCR_PORT                       ((uint8_t)0x70)               /*!< PORT[2:0] bits (Port selection) */
-#define AFIO_EVCR_PORT_0                     ((uint8_t)0x10)               /*!< Bit 0 */
-#define AFIO_EVCR_PORT_1                     ((uint8_t)0x20)               /*!< Bit 1 */
-#define AFIO_EVCR_PORT_2                     ((uint8_t)0x40)               /*!< Bit 2 */
-
-/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA                    ((uint8_t)0x00)               /*!< Port A selected */
-#define AFIO_EVCR_PORT_PB                    ((uint8_t)0x10)               /*!< Port B selected */
-#define AFIO_EVCR_PORT_PC                    ((uint8_t)0x20)               /*!< Port C selected */
-#define AFIO_EVCR_PORT_PD                    ((uint8_t)0x30)               /*!< Port D selected */
-#define AFIO_EVCR_PORT_PE                    ((uint8_t)0x40)               /*!< Port E selected */
-
-#define AFIO_EVCR_EVOE                       ((uint8_t)0x80)               /*!< Event Output Enable */
-
-/******************  Bit definition for AFIO_MAPR register  *******************/
-#define AFIO_MAPR_SPI1_REMAP                 ((uint32_t)0x00000001)        /*!< SPI1 remapping */
-#define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */
-#define AFIO_MAPR_USART1_REMAP               ((uint32_t)0x00000004)        /*!< USART1 remapping */
-#define AFIO_MAPR_USART2_REMAP               ((uint32_t)0x00000008)        /*!< USART2 remapping */
-
-#define AFIO_MAPR_USART3_REMAP               ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
-#define AFIO_MAPR_USART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define AFIO_MAPR_USART3_REMAP_1             ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
-
-#define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
-#define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
-
-#define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
-#define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
-
-#define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
-#define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */
-
-/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
-
-#define AFIO_MAPR_TIM4_REMAP                 ((uint32_t)0x00001000)        /*!< TIM4_REMAP bit (TIM4 remapping) */
-
-#define AFIO_MAPR_CAN_REMAP                  ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
-#define AFIO_MAPR_CAN_REMAP_0                ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define AFIO_MAPR_CAN_REMAP_1                ((uint32_t)0x00004000)        /*!< Bit 1 */
-
-/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2           ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3           ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
-
-#define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-#define AFIO_MAPR_TIM5CH4_IREMAP             ((uint32_t)0x00010000)        /*!< TIM5 Channel4 Internal Remap */
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((uint32_t)0x00020000)        /*!< ADC 1 External Trigger Injected Conversion remapping */
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((uint32_t)0x00040000)        /*!< ADC 1 External Trigger Regular Conversion remapping */
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((uint32_t)0x00080000)        /*!< ADC 2 External Trigger Injected Conversion remapping */
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((uint32_t)0x00100000)        /*!< ADC 2 External Trigger Regular Conversion remapping */
-
-/*!< SWJ_CFG configuration */
-#define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
-#define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
-#define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
-
-#ifdef STM32F10X_CL
-/*!< ETH_REMAP configuration */
- #define AFIO_MAPR_ETH_REMAP                  ((uint32_t)0x00200000)        /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
-
-/*!< CAN2_REMAP configuration */
- #define AFIO_MAPR_CAN2_REMAP                 ((uint32_t)0x00400000)        /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
-
-/*!< MII_RMII_SEL configuration */
- #define AFIO_MAPR_MII_RMII_SEL               ((uint32_t)0x00800000)        /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
-
-/*!< SPI3_REMAP configuration */
- #define AFIO_MAPR_SPI3_REMAP                 ((uint32_t)0x10000000)        /*!< SPI3_REMAP bit (SPI3 remapping) */
-
-/*!< TIM2ITR1_IREMAP configuration */
- #define AFIO_MAPR_TIM2ITR1_IREMAP            ((uint32_t)0x20000000)        /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
-
-/*!< PTP_PPS_REMAP configuration */
- #define AFIO_MAPR_PTP_PPS_REMAP              ((uint32_t)0x40000000)        /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
-#endif
-
-/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
-#define AFIO_EXTICR1_EXTI0                   ((uint16_t)0x000F)            /*!< EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI1                   ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI2                   ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI3                   ((uint16_t)0xF000)            /*!< EXTI 3 configuration */
-
-/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA                ((uint16_t)0x0000)            /*!< PA[0] pin */
-#define AFIO_EXTICR1_EXTI0_PB                ((uint16_t)0x0001)            /*!< PB[0] pin */
-#define AFIO_EXTICR1_EXTI0_PC                ((uint16_t)0x0002)            /*!< PC[0] pin */
-#define AFIO_EXTICR1_EXTI0_PD                ((uint16_t)0x0003)            /*!< PD[0] pin */
-#define AFIO_EXTICR1_EXTI0_PE                ((uint16_t)0x0004)            /*!< PE[0] pin */
-#define AFIO_EXTICR1_EXTI0_PF                ((uint16_t)0x0005)            /*!< PF[0] pin */
-#define AFIO_EXTICR1_EXTI0_PG                ((uint16_t)0x0006)            /*!< PG[0] pin */
-
-/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA                ((uint16_t)0x0000)            /*!< PA[1] pin */
-#define AFIO_EXTICR1_EXTI1_PB                ((uint16_t)0x0010)            /*!< PB[1] pin */
-#define AFIO_EXTICR1_EXTI1_PC                ((uint16_t)0x0020)            /*!< PC[1] pin */
-#define AFIO_EXTICR1_EXTI1_PD                ((uint16_t)0x0030)            /*!< PD[1] pin */
-#define AFIO_EXTICR1_EXTI1_PE                ((uint16_t)0x0040)            /*!< PE[1] pin */
-#define AFIO_EXTICR1_EXTI1_PF                ((uint16_t)0x0050)            /*!< PF[1] pin */
-#define AFIO_EXTICR1_EXTI1_PG                ((uint16_t)0x0060)            /*!< PG[1] pin */
-
-/*!< EXTI2 configuration */  
-#define AFIO_EXTICR1_EXTI2_PA                ((uint16_t)0x0000)            /*!< PA[2] pin */
-#define AFIO_EXTICR1_EXTI2_PB                ((uint16_t)0x0100)            /*!< PB[2] pin */
-#define AFIO_EXTICR1_EXTI2_PC                ((uint16_t)0x0200)            /*!< PC[2] pin */
-#define AFIO_EXTICR1_EXTI2_PD                ((uint16_t)0x0300)            /*!< PD[2] pin */
-#define AFIO_EXTICR1_EXTI2_PE                ((uint16_t)0x0400)            /*!< PE[2] pin */
-#define AFIO_EXTICR1_EXTI2_PF                ((uint16_t)0x0500)            /*!< PF[2] pin */
-#define AFIO_EXTICR1_EXTI2_PG                ((uint16_t)0x0600)            /*!< PG[2] pin */
-
-/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA                ((uint16_t)0x0000)            /*!< PA[3] pin */
-#define AFIO_EXTICR1_EXTI3_PB                ((uint16_t)0x1000)            /*!< PB[3] pin */
-#define AFIO_EXTICR1_EXTI3_PC                ((uint16_t)0x2000)            /*!< PC[3] pin */
-#define AFIO_EXTICR1_EXTI3_PD                ((uint16_t)0x3000)            /*!< PD[3] pin */
-#define AFIO_EXTICR1_EXTI3_PE                ((uint16_t)0x4000)            /*!< PE[3] pin */
-#define AFIO_EXTICR1_EXTI3_PF                ((uint16_t)0x5000)            /*!< PF[3] pin */
-#define AFIO_EXTICR1_EXTI3_PG                ((uint16_t)0x6000)            /*!< PG[3] pin */
-
-/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
-#define AFIO_EXTICR2_EXTI4                   ((uint16_t)0x000F)            /*!< EXTI 4 configuration */
-#define AFIO_EXTICR2_EXTI5                   ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */
-#define AFIO_EXTICR2_EXTI6                   ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */
-#define AFIO_EXTICR2_EXTI7                   ((uint16_t)0xF000)            /*!< EXTI 7 configuration */
-
-/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA                ((uint16_t)0x0000)            /*!< PA[4] pin */
-#define AFIO_EXTICR2_EXTI4_PB                ((uint16_t)0x0001)            /*!< PB[4] pin */
-#define AFIO_EXTICR2_EXTI4_PC                ((uint16_t)0x0002)            /*!< PC[4] pin */
-#define AFIO_EXTICR2_EXTI4_PD                ((uint16_t)0x0003)            /*!< PD[4] pin */
-#define AFIO_EXTICR2_EXTI4_PE                ((uint16_t)0x0004)            /*!< PE[4] pin */
-#define AFIO_EXTICR2_EXTI4_PF                ((uint16_t)0x0005)            /*!< PF[4] pin */
-#define AFIO_EXTICR2_EXTI4_PG                ((uint16_t)0x0006)            /*!< PG[4] pin */
-
-/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA                ((uint16_t)0x0000)            /*!< PA[5] pin */
-#define AFIO_EXTICR2_EXTI5_PB                ((uint16_t)0x0010)            /*!< PB[5] pin */
-#define AFIO_EXTICR2_EXTI5_PC                ((uint16_t)0x0020)            /*!< PC[5] pin */
-#define AFIO_EXTICR2_EXTI5_PD                ((uint16_t)0x0030)            /*!< PD[5] pin */
-#define AFIO_EXTICR2_EXTI5_PE                ((uint16_t)0x0040)            /*!< PE[5] pin */
-#define AFIO_EXTICR2_EXTI5_PF                ((uint16_t)0x0050)            /*!< PF[5] pin */
-#define AFIO_EXTICR2_EXTI5_PG                ((uint16_t)0x0060)            /*!< PG[5] pin */
-
-/*!< EXTI6 configuration */  
-#define AFIO_EXTICR2_EXTI6_PA                ((uint16_t)0x0000)            /*!< PA[6] pin */
-#define AFIO_EXTICR2_EXTI6_PB                ((uint16_t)0x0100)            /*!< PB[6] pin */
-#define AFIO_EXTICR2_EXTI6_PC                ((uint16_t)0x0200)            /*!< PC[6] pin */
-#define AFIO_EXTICR2_EXTI6_PD                ((uint16_t)0x0300)            /*!< PD[6] pin */
-#define AFIO_EXTICR2_EXTI6_PE                ((uint16_t)0x0400)            /*!< PE[6] pin */
-#define AFIO_EXTICR2_EXTI6_PF                ((uint16_t)0x0500)            /*!< PF[6] pin */
-#define AFIO_EXTICR2_EXTI6_PG                ((uint16_t)0x0600)            /*!< PG[6] pin */
-
-/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA                ((uint16_t)0x0000)            /*!< PA[7] pin */
-#define AFIO_EXTICR2_EXTI7_PB                ((uint16_t)0x1000)            /*!< PB[7] pin */
-#define AFIO_EXTICR2_EXTI7_PC                ((uint16_t)0x2000)            /*!< PC[7] pin */
-#define AFIO_EXTICR2_EXTI7_PD                ((uint16_t)0x3000)            /*!< PD[7] pin */
-#define AFIO_EXTICR2_EXTI7_PE                ((uint16_t)0x4000)            /*!< PE[7] pin */
-#define AFIO_EXTICR2_EXTI7_PF                ((uint16_t)0x5000)            /*!< PF[7] pin */
-#define AFIO_EXTICR2_EXTI7_PG                ((uint16_t)0x6000)            /*!< PG[7] pin */
-
-/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
-#define AFIO_EXTICR3_EXTI8                   ((uint16_t)0x000F)            /*!< EXTI 8 configuration */
-#define AFIO_EXTICR3_EXTI9                   ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */
-#define AFIO_EXTICR3_EXTI10                  ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */
-#define AFIO_EXTICR3_EXTI11                  ((uint16_t)0xF000)            /*!< EXTI 11 configuration */
-
-/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA                ((uint16_t)0x0000)            /*!< PA[8] pin */
-#define AFIO_EXTICR3_EXTI8_PB                ((uint16_t)0x0001)            /*!< PB[8] pin */
-#define AFIO_EXTICR3_EXTI8_PC                ((uint16_t)0x0002)            /*!< PC[8] pin */
-#define AFIO_EXTICR3_EXTI8_PD                ((uint16_t)0x0003)            /*!< PD[8] pin */
-#define AFIO_EXTICR3_EXTI8_PE                ((uint16_t)0x0004)            /*!< PE[8] pin */
-#define AFIO_EXTICR3_EXTI8_PF                ((uint16_t)0x0005)            /*!< PF[8] pin */
-#define AFIO_EXTICR3_EXTI8_PG                ((uint16_t)0x0006)            /*!< PG[8] pin */
-
-/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA                ((uint16_t)0x0000)            /*!< PA[9] pin */
-#define AFIO_EXTICR3_EXTI9_PB                ((uint16_t)0x0010)            /*!< PB[9] pin */
-#define AFIO_EXTICR3_EXTI9_PC                ((uint16_t)0x0020)            /*!< PC[9] pin */
-#define AFIO_EXTICR3_EXTI9_PD                ((uint16_t)0x0030)            /*!< PD[9] pin */
-#define AFIO_EXTICR3_EXTI9_PE                ((uint16_t)0x0040)            /*!< PE[9] pin */
-#define AFIO_EXTICR3_EXTI9_PF                ((uint16_t)0x0050)            /*!< PF[9] pin */
-#define AFIO_EXTICR3_EXTI9_PG                ((uint16_t)0x0060)            /*!< PG[9] pin */
-
-/*!< EXTI10 configuration */  
-#define AFIO_EXTICR3_EXTI10_PA               ((uint16_t)0x0000)            /*!< PA[10] pin */
-#define AFIO_EXTICR3_EXTI10_PB               ((uint16_t)0x0100)            /*!< PB[10] pin */
-#define AFIO_EXTICR3_EXTI10_PC               ((uint16_t)0x0200)            /*!< PC[10] pin */
-#define AFIO_EXTICR3_EXTI10_PD               ((uint16_t)0x0300)            /*!< PD[10] pin */
-#define AFIO_EXTICR3_EXTI10_PE               ((uint16_t)0x0400)            /*!< PE[10] pin */
-#define AFIO_EXTICR3_EXTI10_PF               ((uint16_t)0x0500)            /*!< PF[10] pin */
-#define AFIO_EXTICR3_EXTI10_PG               ((uint16_t)0x0600)            /*!< PG[10] pin */
-
-/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA               ((uint16_t)0x0000)            /*!< PA[11] pin */
-#define AFIO_EXTICR3_EXTI11_PB               ((uint16_t)0x1000)            /*!< PB[11] pin */
-#define AFIO_EXTICR3_EXTI11_PC               ((uint16_t)0x2000)            /*!< PC[11] pin */
-#define AFIO_EXTICR3_EXTI11_PD               ((uint16_t)0x3000)            /*!< PD[11] pin */
-#define AFIO_EXTICR3_EXTI11_PE               ((uint16_t)0x4000)            /*!< PE[11] pin */
-#define AFIO_EXTICR3_EXTI11_PF               ((uint16_t)0x5000)            /*!< PF[11] pin */
-#define AFIO_EXTICR3_EXTI11_PG               ((uint16_t)0x6000)            /*!< PG[11] pin */
-
-/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
-#define AFIO_EXTICR4_EXTI12                  ((uint16_t)0x000F)            /*!< EXTI 12 configuration */
-#define AFIO_EXTICR4_EXTI13                  ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */
-#define AFIO_EXTICR4_EXTI14                  ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */
-#define AFIO_EXTICR4_EXTI15                  ((uint16_t)0xF000)            /*!< EXTI 15 configuration */
-
-/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA               ((uint16_t)0x0000)            /*!< PA[12] pin */
-#define AFIO_EXTICR4_EXTI12_PB               ((uint16_t)0x0001)            /*!< PB[12] pin */
-#define AFIO_EXTICR4_EXTI12_PC               ((uint16_t)0x0002)            /*!< PC[12] pin */
-#define AFIO_EXTICR4_EXTI12_PD               ((uint16_t)0x0003)            /*!< PD[12] pin */
-#define AFIO_EXTICR4_EXTI12_PE               ((uint16_t)0x0004)            /*!< PE[12] pin */
-#define AFIO_EXTICR4_EXTI12_PF               ((uint16_t)0x0005)            /*!< PF[12] pin */
-#define AFIO_EXTICR4_EXTI12_PG               ((uint16_t)0x0006)            /*!< PG[12] pin */
-
-/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA               ((uint16_t)0x0000)            /*!< PA[13] pin */
-#define AFIO_EXTICR4_EXTI13_PB               ((uint16_t)0x0010)            /*!< PB[13] pin */
-#define AFIO_EXTICR4_EXTI13_PC               ((uint16_t)0x0020)            /*!< PC[13] pin */
-#define AFIO_EXTICR4_EXTI13_PD               ((uint16_t)0x0030)            /*!< PD[13] pin */
-#define AFIO_EXTICR4_EXTI13_PE               ((uint16_t)0x0040)            /*!< PE[13] pin */
-#define AFIO_EXTICR4_EXTI13_PF               ((uint16_t)0x0050)            /*!< PF[13] pin */
-#define AFIO_EXTICR4_EXTI13_PG               ((uint16_t)0x0060)            /*!< PG[13] pin */
-
-/*!< EXTI14 configuration */  
-#define AFIO_EXTICR4_EXTI14_PA               ((uint16_t)0x0000)            /*!< PA[14] pin */
-#define AFIO_EXTICR4_EXTI14_PB               ((uint16_t)0x0100)            /*!< PB[14] pin */
-#define AFIO_EXTICR4_EXTI14_PC               ((uint16_t)0x0200)            /*!< PC[14] pin */
-#define AFIO_EXTICR4_EXTI14_PD               ((uint16_t)0x0300)            /*!< PD[14] pin */
-#define AFIO_EXTICR4_EXTI14_PE               ((uint16_t)0x0400)            /*!< PE[14] pin */
-#define AFIO_EXTICR4_EXTI14_PF               ((uint16_t)0x0500)            /*!< PF[14] pin */
-#define AFIO_EXTICR4_EXTI14_PG               ((uint16_t)0x0600)            /*!< PG[14] pin */
-
-/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA               ((uint16_t)0x0000)            /*!< PA[15] pin */
-#define AFIO_EXTICR4_EXTI15_PB               ((uint16_t)0x1000)            /*!< PB[15] pin */
-#define AFIO_EXTICR4_EXTI15_PC               ((uint16_t)0x2000)            /*!< PC[15] pin */
-#define AFIO_EXTICR4_EXTI15_PD               ((uint16_t)0x3000)            /*!< PD[15] pin */
-#define AFIO_EXTICR4_EXTI15_PE               ((uint16_t)0x4000)            /*!< PE[15] pin */
-#define AFIO_EXTICR4_EXTI15_PF               ((uint16_t)0x5000)            /*!< PF[15] pin */
-#define AFIO_EXTICR4_EXTI15_PG               ((uint16_t)0x6000)            /*!< PG[15] pin */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-/******************  Bit definition for AFIO_MAPR2 register  ******************/
-#define AFIO_MAPR2_TIM15_REMAP               ((uint32_t)0x00000001)        /*!< TIM15 remapping */
-#define AFIO_MAPR2_TIM16_REMAP               ((uint32_t)0x00000002)        /*!< TIM16 remapping */
-#define AFIO_MAPR2_TIM17_REMAP               ((uint32_t)0x00000004)        /*!< TIM17 remapping */
-#define AFIO_MAPR2_CEC_REMAP                 ((uint32_t)0x00000008)        /*!< CEC remapping */
-#define AFIO_MAPR2_TIM1_DMA_REMAP            ((uint32_t)0x00000010)        /*!< TIM1_DMA remapping */
-#endif
-
-#ifdef STM32F10X_HD_VL
-#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
-#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
-#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
-#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP       ((uint32_t)0x00000800)        /*!< TIM6/TIM7 and DAC DMA remapping */
-#define AFIO_MAPR2_TIM12_REMAP               ((uint32_t)0x00001000)        /*!< TIM12 remapping */
-#define AFIO_MAPR2_MISC_REMAP                ((uint32_t)0x00002000)        /*!< Miscellaneous remapping */
-#endif
-
-#ifdef STM32F10X_XL 
-/******************  Bit definition for AFIO_MAPR2 register  ******************/
-#define AFIO_MAPR2_TIM9_REMAP                ((uint32_t)0x00000020)        /*!< TIM9 remapping */
-#define AFIO_MAPR2_TIM10_REMAP               ((uint32_t)0x00000040)        /*!< TIM10 remapping */
-#define AFIO_MAPR2_TIM11_REMAP               ((uint32_t)0x00000080)        /*!< TIM11 remapping */
-#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
-#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
-#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
-#endif
-
-/******************************************************************************/
-/*                                                                            */
-/*                               SystemTick                                   */
-/*                                                                            */
-/******************************************************************************/
-
-/*****************  Bit definition for SysTick_CTRL register  *****************/
-#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
-#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
-#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
-#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
-
-/*****************  Bit definition for SysTick_LOAD register  *****************/
-#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/*****************  Bit definition for SysTick_VAL register  ******************/
-#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
-
-/*****************  Bit definition for SysTick_CALIB register  ****************/
-#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
-#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
-#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  Nested Vectored Interrupt Controller                      */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for NVIC_ISER register  *******************/
-#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
-#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICER register  *******************/
-#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
-#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ISPR register  *******************/
-#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
-#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICPR register  *******************/
-#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
-#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_IABR register  *******************/
-#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
-#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_PRI0 register  *******************/
-#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
-#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
-#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
-#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
-
-/******************  Bit definition for NVIC_PRI1 register  *******************/
-#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
-#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
-#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
-#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
-
-/******************  Bit definition for NVIC_PRI2 register  *******************/
-#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
-#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
-#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
-#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
-
-/******************  Bit definition for NVIC_PRI3 register  *******************/
-#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
-#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
-#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
-#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
-
-/******************  Bit definition for NVIC_PRI4 register  *******************/
-#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
-#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
-#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
-#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
-
-/******************  Bit definition for NVIC_PRI5 register  *******************/
-#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
-#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
-#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
-#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
-
-/******************  Bit definition for NVIC_PRI6 register  *******************/
-#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
-#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
-#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
-#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
-
-/******************  Bit definition for NVIC_PRI7 register  *******************/
-#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
-#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
-#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
-#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
-
-/******************  Bit definition for SCB_CPUID register  *******************/
-#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
-#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
-#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
-#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
-#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
-
-/*******************  Bit definition for SCB_ICSR register  *******************/
-#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
-#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
-#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
-#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
-#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
-#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
-#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
-#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
-
-/*******************  Bit definition for SCB_VTOR register  *******************/
-#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
-#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
-
-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
-#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
-#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
-#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
-
-#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
-#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
-
-/* prority group configuration */
-#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
-#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/*******************  Bit definition for SCB_SCR register  ********************/
-#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
-#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
-#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
-
-/********************  Bit definition for SCB_CCR register  *******************/
-#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
-#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
-#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
-#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/*******************  Bit definition for SCB_SHPR register ********************/
-#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/******************  Bit definition for SCB_SHCSR register  *******************/
-#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
-#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
-#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
-#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
-#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
-#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
-#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
-#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
-#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
-#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
-#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
-#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
-#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
-#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
-
-/*******************  Bit definition for SCB_CFSR register  *******************/
-/*!< MFSR */
-#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
-#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
-#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
-#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
-#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
-#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
-#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
-#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
-#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
-#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to execute an undefined instruction */
-#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
-#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
-#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
-#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/*******************  Bit definition for SCB_HFSR register  *******************/
-#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occurs because of vector table read on exception processing */
-#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
-
-/*******************  Bit definition for SCB_DFSR register  *******************/
-#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
-#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
-#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
-#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
-#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
-
-/*******************  Bit definition for SCB_MMFAR register  ******************/
-#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
-
-/*******************  Bit definition for SCB_BFAR register  *******************/
-#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
-
-/*******************  Bit definition for SCB_afsr register  *******************/
-#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
-#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
-#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR1 register  *******************/
-#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
-#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
-#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*******************  Bit definition for DMA_CCR2 register  *******************/
-#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*******************  Bit definition for DMA_CCR3 register  *******************/
-#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*!<******************  Bit definition for DMA_CCR4 register  *******************/
-#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/******************  Bit definition for DMA_CCR5 register  *******************/
-#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
-
-/*******************  Bit definition for DMA_CCR6 register  *******************/
-#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*******************  Bit definition for DMA_CCR7 register  *******************/
-#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!< Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!< End of conversion */
-#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!< Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!< Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!< Regular channel Start flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
-
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
-
-#define  ADC_CR1_DUALMOD                     ((uint32_t)0x000F0000)        /*!< DUALMOD[3:0] bits (Dual mode selection) */
-#define  ADC_CR1_DUALMOD_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CR1_DUALMOD_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  ADC_CR1_DUALMOD_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  ADC_CR1_DUALMOD_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
-
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
-#define  ADC_CR2_CAL                         ((uint32_t)0x00000004)        /*!< A/D Calibration */
-#define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)        /*!< Reset Calibration */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
-
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)        /*!< JEXTSEL[2:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)        /*!< External Trigger Conversion mode for injected channels */
-
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)        /*!< Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)        /*!< Bit 2 */
-
-#define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)        /*!< External Trigger Conversion mode for regular channels */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)        /*!< Start Conversion of injected channels */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)        /*!< Start Conversion of regular channels */
-#define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!< ADC2 data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    CEC                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for CEC_CFGR register  ******************/
-#define  CEC_CFGR_PE              ((uint16_t)0x0001)     /*!<  Peripheral Enable */
-#define  CEC_CFGR_IE              ((uint16_t)0x0002)     /*!<  Interrupt Enable */
-#define  CEC_CFGR_BTEM            ((uint16_t)0x0004)     /*!<  Bit Timing Error Mode */
-#define  CEC_CFGR_BPEM            ((uint16_t)0x0008)     /*!<  Bit Period Error Mode */
-
-/********************  Bit definition for CEC_OAR register  ******************/
-#define  CEC_OAR_OA               ((uint16_t)0x000F)     /*!<  OA[3:0]: Own Address */
-#define  CEC_OAR_OA_0             ((uint16_t)0x0001)     /*!<  Bit 0 */
-#define  CEC_OAR_OA_1             ((uint16_t)0x0002)     /*!<  Bit 1 */
-#define  CEC_OAR_OA_2             ((uint16_t)0x0004)     /*!<  Bit 2 */
-#define  CEC_OAR_OA_3             ((uint16_t)0x0008)     /*!<  Bit 3 */
-
-/********************  Bit definition for CEC_PRES register  ******************/
-#define  CEC_PRES_PRES            ((uint16_t)0x3FFF)   /*!<  Prescaler Counter Value */
-
-/********************  Bit definition for CEC_ESR register  ******************/
-#define  CEC_ESR_BTE              ((uint16_t)0x0001)     /*!<  Bit Timing Error */
-#define  CEC_ESR_BPE              ((uint16_t)0x0002)     /*!<  Bit Period Error */
-#define  CEC_ESR_RBTFE            ((uint16_t)0x0004)     /*!<  Rx Block Transfer Finished Error */
-#define  CEC_ESR_SBE              ((uint16_t)0x0008)     /*!<  Start Bit Error */
-#define  CEC_ESR_ACKE             ((uint16_t)0x0010)     /*!<  Block Acknowledge Error */
-#define  CEC_ESR_LINE             ((uint16_t)0x0020)     /*!<  Line Error */
-#define  CEC_ESR_TBTFE            ((uint16_t)0x0040)     /*!<  Tx Block Transfer Finished Error */
-
-/********************  Bit definition for CEC_CSR register  ******************/
-#define  CEC_CSR_TSOM             ((uint16_t)0x0001)     /*!<  Tx Start Of Message */
-#define  CEC_CSR_TEOM             ((uint16_t)0x0002)     /*!<  Tx End Of Message */
-#define  CEC_CSR_TERR             ((uint16_t)0x0004)     /*!<  Tx Error */
-#define  CEC_CSR_TBTRF            ((uint16_t)0x0008)     /*!<  Tx Byte Transfer Request or Block Transfer Finished */
-#define  CEC_CSR_RSOM             ((uint16_t)0x0010)     /*!<  Rx Start Of Message */
-#define  CEC_CSR_REOM             ((uint16_t)0x0020)     /*!<  Rx End Of Message */
-#define  CEC_CSR_RERR             ((uint16_t)0x0040)     /*!<  Rx Error */
-#define  CEC_CSR_RBTF             ((uint16_t)0x0080)     /*!<  Rx Block Transfer Finished */
-
-/********************  Bit definition for CEC_TXD register  ******************/
-#define  CEC_TXD_TXD              ((uint16_t)0x00FF)     /*!<  Tx Data register */
-
-/********************  Bit definition for CEC_RXD register  ******************/
-#define  CEC_RXD_RXD              ((uint16_t)0x00FF)     /*!<  Rx Data register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!< Counter enable */
-#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!< Update disable */
-#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!< Update request source */
-#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!< One pulse mode */
-#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!< Direction */
-
-#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!< CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!< Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!< Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!< Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!< CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!< Capture/Compare Preloaded Control */
-#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!< Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!< Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!< MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!< TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!< Output Idle state 1 (OC1 output) */
-#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!< Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!< Output Idle state 2 (OC2 output) */
-#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!< Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!< Output Idle state 3 (OC3 output) */
-#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!< Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!< Output Idle state 4 (OC4 output) */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!< SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
-
-#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!< TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!< Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!< ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!< Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!< Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!< Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!< ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!< External clock enable */
-#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!< External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!< Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!< COM interrupt enable */
-#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!< Trigger interrupt enable */
-#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!< Break interrupt enable */
-#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!< Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!< Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!< Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!< Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!< COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!< Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!< Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!< COM interrupt Flag */
-#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!< Trigger interrupt Flag */
-#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!< Break interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!< Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!< Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!< Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!< Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!< Update Generation */
-#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!< Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!< Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!< Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!< Capture/Compare 4 Generation */
-#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!< Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!< Trigger Generation */
-#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!< Break Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!< Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!< Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!< Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!< Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!< Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!< Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!< Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!< Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!< Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!< Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!< Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!< Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!< Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!< Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!< Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!< Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!< Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!< Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!< Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!< Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!< Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!< Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!< Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!< Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!< Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!< Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!< Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!< Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!< actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!< Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!< Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!< Bit 7 */
-
-#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!< LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!< Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!< Off-State Selection for Run mode */
-#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!< Break enable */
-#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!< Break Polarity */
-#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!< Automatic Output enable */
-#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!< Main Output enable */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!< DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!< Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!< DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!< Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!< Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!< Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!< DMA register for burst accesses */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Real-Time Clock                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for RTC_CRH register  ********************/
-#define  RTC_CRH_SECIE                       ((uint8_t)0x01)               /*!< Second Interrupt Enable */
-#define  RTC_CRH_ALRIE                       ((uint8_t)0x02)               /*!< Alarm Interrupt Enable */
-#define  RTC_CRH_OWIE                        ((uint8_t)0x04)               /*!< OverfloW Interrupt Enable */
-
-/*******************  Bit definition for RTC_CRL register  ********************/
-#define  RTC_CRL_SECF                        ((uint8_t)0x01)               /*!< Second Flag */
-#define  RTC_CRL_ALRF                        ((uint8_t)0x02)               /*!< Alarm Flag */
-#define  RTC_CRL_OWF                         ((uint8_t)0x04)               /*!< OverfloW Flag */
-#define  RTC_CRL_RSF                         ((uint8_t)0x08)               /*!< Registers Synchronized Flag */
-#define  RTC_CRL_CNF                         ((uint8_t)0x10)               /*!< Configuration Flag */
-#define  RTC_CRL_RTOFF                       ((uint8_t)0x20)               /*!< RTC operation OFF */
-
-/*******************  Bit definition for RTC_PRLH register  *******************/
-#define  RTC_PRLH_PRL                        ((uint16_t)0x000F)            /*!< RTC Prescaler Reload Value High */
-
-/*******************  Bit definition for RTC_PRLL register  *******************/
-#define  RTC_PRLL_PRL                        ((uint16_t)0xFFFF)            /*!< RTC Prescaler Reload Value Low */
-
-/*******************  Bit definition for RTC_DIVH register  *******************/
-#define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /*!< RTC Clock Divider High */
-
-/*******************  Bit definition for RTC_DIVL register  *******************/
-#define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /*!< RTC Clock Divider Low */
-
-/*******************  Bit definition for RTC_CNTH register  *******************/
-#define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter High */
-
-/*******************  Bit definition for RTC_CNTL register  *******************/
-#define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter Low */
-
-/*******************  Bit definition for RTC_ALRH register  *******************/
-#define  RTC_ALRH_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm High */
-
-/*******************  Bit definition for RTC_ALRL register  *******************/
-#define  RTC_ALRL_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm Low */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
-#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
-#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
-#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
-#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
-#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
-#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
-#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
-#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
-#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
-#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
-#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
-
-#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
-
-#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
-
-#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
-#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
-
-#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
-
-/******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
-
-#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
-
-#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
-
-#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
-#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
-
-#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
-
-/******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
-
-#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
-
-#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
-
-#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
-#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
-
-#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
-
-/*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
-#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
-#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
-#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
-#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
-#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
-
-/*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
-#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
-#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
-#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
-#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
-#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
-
-/*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
-#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
-#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
-#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
-#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
-#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
-
-/******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!< IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!< Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!< Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!< Bit 7 */
-
-#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
-
-#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!< Bit 7 */
-
-#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
-
-/******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
-
-/******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
-#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
-#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
-#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
-
-#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
-#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
-#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
-#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
-#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
-#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
-#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
-#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                   USB Device FS                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*!< Endpoint-specific registers */
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
-
-#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
-#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
-#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
-
-#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
-
-#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
-
-#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
-#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
-
-/*!< Common registers */
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!< Force USB Reset */
-#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!< Power down */
-#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!< Low-power mode */
-#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!< Force suspend */
-#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!< Resume request */
-#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!< Expected Start Of Frame Interrupt Mask */
-#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!< Start Of Frame Interrupt Mask */
-#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!< RESET Interrupt Mask */
-#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!< Suspend mode Interrupt Mask */
-#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!< Wakeup Interrupt Mask */
-#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!< Error Interrupt Mask */
-#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun Interrupt Mask */
-#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!< Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!< Endpoint Identifier */
-#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!< Direction of transaction */
-#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!< Expected Start Of Frame */
-#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!< Start Of Frame */
-#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!< USB RESET request */
-#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!< Suspend mode request */
-#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!< Wake up */
-#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!< Error */
-#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun */
-#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!< Correct Transfer */
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!< Frame Number */
-#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!< Lost SOF */
-#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!< Locked */
-#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!< Receive Data - Line Status */
-#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!< Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!< ADD[6:0] bits (Device Address) */
-#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!< Bit 0 */
-#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!< Bit 1 */
-#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!< Bit 2 */
-#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!< Bit 3 */
-#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!< Bit 4 */
-#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!< Bit 5 */
-#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!< Bit 6 */
-
-#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!< Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!< Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*!< CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!< Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!< Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!< Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!< Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!< No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!< Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!< Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!< Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!< CAN software master reset */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!< Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!< Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!< Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!< Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!< Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!< Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!< Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!< Last Sample Point */
-#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!< CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!< Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!< Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!< Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!< Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!< Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!< Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!< Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!< Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!< Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!< Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!< Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!< Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!< Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!< Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!< Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!< Mailbox Code */
-
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!< TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!< Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!< Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!< Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!< LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!< Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!< Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!< Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!< FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!< FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!< FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!< Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!< FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!< FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!< FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!< Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!< FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!< FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!< FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!< FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!< FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!< FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!< Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!< Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!< Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!< Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!< Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!< Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!< Sleep Interrupt Enable */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!< Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!< Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!< Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!< LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!< Bit 2 */
-
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!< Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!< Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!< Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!< Time Segment 1 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!< Time Segment 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!< Resynchronization Jump Width */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!< Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!< Silent Mode */
-
-/*!< Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
-
-/*!< CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!< Filter Init Mode */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!< Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!< Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!< Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!< Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!< Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!< Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!< Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!< Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!< Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!< Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!< Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!< Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!< Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!< Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!< Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!< Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!< Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!< Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!< Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!< Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!< Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!< Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!< Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!< Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!< Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!< Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!< Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!< Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!< Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!< Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!< Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!< Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!< Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!< Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!< Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!< Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!< Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!< Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!< Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!< Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!< Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!< Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!< Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!< Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!< Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!< Filter Active */
-#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!< Filter 0 Active */
-#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!< Filter 1 Active */
-#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!< Filter 2 Active */
-#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!< Filter 3 Active */
-#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!< Filter 4 Active */
-#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!< Filter 5 Active */
-#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!< Filter 6 Active */
-#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!< Filter 7 Active */
-#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!< Filter 8 Active */
-#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!< Filter 9 Active */
-#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!< Filter 10 Active */
-#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!< Filter 11 Active */
-#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!< Filter 12 Active */
-#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!< Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
-
-#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
-#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
-#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
-#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!< Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!< DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!< Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!< Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!< steady state clock polarity */
-
-#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!< I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!< Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!< PCM frame synchronization */
-
-#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!< I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!< I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!< I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!< I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!< Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!< Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
-#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
-#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
-#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
-#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
-#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
-#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
-#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
-#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
-#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
-#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
-#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
-#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
-
-#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
-#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
-#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
-#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
-
-#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
-#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
-#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
-#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
-#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
-#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
-#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
-#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
-#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
-#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
-#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
-#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
-#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
-#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
-#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
-#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
-#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
-#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
-#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
-#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
-#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
-#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
-#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
-#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
-#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
-#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
-#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
-#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
-#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
-#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
-#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
-#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< USART Oversmapling 8-bits */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
-#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
-
-#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
-#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
-#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One Bit method */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
-
-#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  DBGMCU_CR_DBG_IWDG_STOP             ((uint32_t)0x00000100)        /*!< Debug Independent Watchdog stopped when Core is halted */
-#define  DBGMCU_CR_DBG_WWDG_STOP             ((uint32_t)0x00000200)        /*!< Debug Window Watchdog stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM1_STOP             ((uint32_t)0x00000400)        /*!< TIM1 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM2_STOP             ((uint32_t)0x00000800)        /*!< TIM2 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM3_STOP             ((uint32_t)0x00001000)        /*!< TIM3 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM4_STOP             ((uint32_t)0x00002000)        /*!< TIM4 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_CAN1_STOP             ((uint32_t)0x00004000)        /*!< Debug CAN1 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)        /*!< SMBUS timeout mode stopped when Core is halted */
-#define  DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)        /*!< SMBUS timeout mode stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM8_STOP             ((uint32_t)0x00020000)        /*!< TIM8 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM5_STOP             ((uint32_t)0x00040000)        /*!< TIM5 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM6_STOP             ((uint32_t)0x00080000)        /*!< TIM6 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_TIM7_STOP             ((uint32_t)0x00100000)        /*!< TIM7 counter stopped when core is halted */
-#define  DBGMCU_CR_DBG_CAN2_STOP             ((uint32_t)0x00200000)        /*!< Debug CAN2 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM15_STOP            ((uint32_t)0x00400000)        /*!< Debug TIM15 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM16_STOP            ((uint32_t)0x00800000)        /*!< Debug TIM16 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM17_STOP            ((uint32_t)0x01000000)        /*!< Debug TIM17 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM12_STOP            ((uint32_t)0x02000000)        /*!< Debug TIM12 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM13_STOP            ((uint32_t)0x04000000)        /*!< Debug TIM13 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM14_STOP            ((uint32_t)0x08000000)        /*!< Debug TIM14 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM9_STOP             ((uint32_t)0x10000000)        /*!< Debug TIM9 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM10_STOP            ((uint32_t)0x20000000)        /*!< Debug TIM10 stopped when Core is halted */
-#define  DBGMCU_CR_DBG_TIM11_STOP            ((uint32_t)0x40000000)        /*!< Debug TIM11 stopped when Core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
-#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x00)               /*!< Bit 0 */
-#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x01)               /*!< Bit 0 */
-#define  FLASH_ACR_LATENCY_2                 ((uint8_t)0x02)               /*!< Bit 1 */
-
-#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
-#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)               /*!< Prefetch Buffer Status */
-
-/******************  Bit definition for FLASH_KEYR register  ******************/
-#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
-
-/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint8_t)0x01)               /*!< Busy */
-#define  FLASH_SR_PGERR                      ((uint8_t)0x04)               /*!< Programming Error */
-#define  FLASH_SR_WRPRTERR                   ((uint8_t)0x10)               /*!< Write Protection Error */
-#define  FLASH_SR_EOP                        ((uint8_t)0x20)               /*!< End of operation */
-
-/*******************  Bit definition for FLASH_CR register  *******************/
-#define  FLASH_CR_PG                         ((uint16_t)0x0001)            /*!< Programming */
-#define  FLASH_CR_PER                        ((uint16_t)0x0002)            /*!< Page Erase */
-#define  FLASH_CR_MER                        ((uint16_t)0x0004)            /*!< Mass Erase */
-#define  FLASH_CR_OPTPG                      ((uint16_t)0x0010)            /*!< Option Byte Programming */
-#define  FLASH_CR_OPTER                      ((uint16_t)0x0020)            /*!< Option Byte Erase */
-#define  FLASH_CR_STRT                       ((uint16_t)0x0040)            /*!< Start */
-#define  FLASH_CR_LOCK                       ((uint16_t)0x0080)            /*!< Lock */
-#define  FLASH_CR_OPTWRE                     ((uint16_t)0x0200)            /*!< Option Bytes Write Enable */
-#define  FLASH_CR_ERRIE                      ((uint16_t)0x0400)            /*!< Error Interrupt Enable */
-#define  FLASH_CR_EOPIE                      ((uint16_t)0x1000)            /*!< End of operation interrupt enable */
-
-/*******************  Bit definition for FLASH_AR register  *******************/
-#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_OPTERR                    ((uint16_t)0x0001)            /*!< Option Byte Error */
-#define  FLASH_OBR_RDPRT                     ((uint16_t)0x0002)            /*!< Read protection */
-
-#define  FLASH_OBR_USER                      ((uint16_t)0x03FC)            /*!< User Option Bytes */
-#define  FLASH_OBR_WDG_SW                    ((uint16_t)0x0004)            /*!< WDG_SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint16_t)0x0008)            /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint16_t)0x0010)            /*!< nRST_STDBY */
-#define  FLASH_OBR_BFB2                      ((uint16_t)0x0020)            /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for FLASH_RDP register  *******************/
-#define  FLASH_RDP_RDP                       ((uint32_t)0x000000FF)        /*!< Read protection option byte */
-#define  FLASH_RDP_nRDP                      ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
-
-/******************  Bit definition for FLASH_USER register  ******************/
-#define  FLASH_USER_USER                     ((uint32_t)0x00FF0000)        /*!< User option byte */
-#define  FLASH_USER_nUSER                    ((uint32_t)0xFF000000)        /*!< User complemented option byte */
-
-/******************  Bit definition for FLASH_Data0 register  *****************/
-#define  FLASH_Data0_Data0                   ((uint32_t)0x000000FF)        /*!< User data storage option byte */
-#define  FLASH_Data0_nData0                  ((uint32_t)0x0000FF00)        /*!< User data storage complemented option byte */
-
-/******************  Bit definition for FLASH_Data1 register  *****************/
-#define  FLASH_Data1_Data1                   ((uint32_t)0x00FF0000)        /*!< User data storage option byte */
-#define  FLASH_Data1_nData1                  ((uint32_t)0xFF000000)        /*!< User data storage complemented option byte */
-
-/******************  Bit definition for FLASH_WRP0 register  ******************/
-#define  FLASH_WRP0_WRP0                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  FLASH_WRP0_nWRP0                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP1 register  ******************/
-#define  FLASH_WRP1_WRP1                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  FLASH_WRP1_nWRP1                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP2 register  ******************/
-#define  FLASH_WRP2_WRP2                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  FLASH_WRP2_nWRP2                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP3 register  ******************/
-#define  FLASH_WRP3_WRP3                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  FLASH_WRP3_nWRP3                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-
-#ifdef STM32F10X_CL
-/******************************************************************************/
-/*                Ethernet MAC Registers bits definitions                     */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
-#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
-#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
-  #define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
-#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
-#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
-#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
-#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
-#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
-#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
-#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
-#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM 	  ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
-#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
-#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
-#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
-#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
-#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
-#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
-#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
-#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
-#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
-#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
-#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
-#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
-#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
-#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
-#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
-#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
-#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
-#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
-#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
-#endif /* STM32F10X_CL */
-
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-
-#ifdef USE_STDPERIPH_DRIVER
-  #include "stm32f10x_conf.h"
-#endif
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F10x_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM32F30x/adc_lld.c b/os/hal/platforms/STM32F30x/adc_lld.c
deleted file mode 100644
index 7a331d7a6..000000000
--- a/os/hal/platforms/STM32F30x/adc_lld.c
+++ /dev/null
@@ -1,555 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/adc_lld.c
- * @brief   STM32F30x ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#if STM32_ADC_DUAL_MODE
-#if STM32_ADC_COMPACT_SAMPLES
-/* Compact type dual mode.*/
-#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
-#define ADC_DMA_MDMA    ADC_CCR_MDMA_HWORD
-
-#else /* !STM32_ADC_COMPACT_SAMPLES */
-/* Large type dual mode.*/
-#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)
-#define ADC_DMA_MDMA    ADC_CCR_MDMA_WORD
-#endif /* !STM32_ADC_COMPACT_SAMPLES */
-
-#else /* !STM32_ADC_DUAL_MODE */
-#if STM32_ADC_COMPACT_SAMPLES
-/* Compact type single mode.*/
-#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
-#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED
-
-#else /* !STM32_ADC_COMPACT_SAMPLES */
-/* Large type single mode.*/
-#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
-#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED
-#endif /* !STM32_ADC_COMPACT_SAMPLES */
-#endif /* !STM32_ADC_DUAL_MODE */
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
-ADCDriver ADCD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Enables the ADC voltage regulator.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_vreg_on(ADCDriver *adcp) {
-
-  adcp->adcm->CR = 0;   /* RM 12.4.3.*/
-  adcp->adcm->CR = ADC_CR_ADVREGEN_0;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcs->CR = ADC_CR_ADVREGEN_0;
-#endif
-  halPolledDelay(US2RTT(10));
-}
-
-/**
- * @brief   Disables the ADC voltage regulator.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_vreg_off(ADCDriver *adcp) {
-
-  adcp->adcm->CR = 0;   /* RM 12.4.3.*/
-  adcp->adcm->CR = ADC_CR_ADVREGEN_1;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcs->CR = ADC_CR_ADVREGEN_1;
-#endif
-}
-
-/**
- * @brief   Enables the ADC analog circuit.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_analog_on(ADCDriver *adcp) {
-
-  adcp->adcm->CR |= ADC_CR_ADEN;
-  while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0)
-    ;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcs->CR |= ADC_CR_ADEN;
-  while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0)
-    ;
-#endif
-}
-
-/**
- * @brief   Disables the ADC  analog circuit.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_analog_off(ADCDriver *adcp) {
-
-  adcp->adcm->CR |= ADC_CR_ADDIS;
-  while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)
-    ;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcs->CR |= ADC_CR_ADDIS;
-  while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)
-    ;
-#endif
-}
-
-/**
- * @brief   Calibrates and ADC unit.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_calibrate(ADCDriver *adcp) {
-
-  chDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #1",
-                                                   "invalid register state");
-  adcp->adcm->CR |= ADC_CR_ADCAL;
-  while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
-    ;
-#if STM32_ADC_DUAL_MODE
-  chDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #2",
-                                                   "invalid register state");
-  adcp->adcs->CR |= ADC_CR_ADCAL;
-  while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
-    ;
-#endif
-}
-
-/**
- * @brief   Stops an ongoing conversion, if any.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_stop_adc(ADCDriver *adcp) {
-
-  if (adcp->adcm->CR & ADC_CR_ADSTART) {
-    adcp->adcm->CR |= ADC_CR_ADSTP;
-    while (adcp->adcm->CR & ADC_CR_ADSTP)
-      ;
-  }
-}
-
-/**
- * @brief   ADC DMA ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    /* DMA, this could help only if the DMA tries to access an unmapped
-       address space or violates alignment rules.*/
-    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
-  }
-  else {
-    /* It is possible that the conversion group has already be reset by the
-       ADC error handler, in this case this interrupt is spurious.*/
-    if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
-        /* Transfer complete processing.*/
-        _adc_isr_full_code(adcp);
-      }
-      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
-    }
-  }
-}
-
-/**
- * @brief   ADC ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] isr       content of the ISR register
- */
-static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
-
-  /* It could be a spurious interrupt caused by overflows after DMA disabling,
-     just ignore it in this case.*/
-  if (adcp->grpp != NULL) {
-    /* Note, an overflow may occur after the conversion ended before the driver
-       is able to stop the ADC, this is why the DMA channel is checked too.*/
-    if ((isr & ADC_ISR_OVR) &&
-        (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
-      /* ADC overflow condition, this could happen only if the DMA is unable
-         to read data fast enough.*/
-      _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
-    }
-    if (isr & ADC_ISR_AWD1) {
-      /* Analog watchdog error.*/
-      _adc_isr_error_code(adcp, ADC_ERR_AWD1);
-    }
-    if (isr & ADC_ISR_AWD2) {
-      /* Analog watchdog error.*/
-      _adc_isr_error_code(adcp, ADC_ERR_AWD2);
-    }
-    if (isr & ADC_ISR_AWD3) {
-      /* Analog watchdog error.*/
-      _adc_isr_error_code(adcp, ADC_ERR_AWD3);
-    }
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-/**
- * @brief   ADC1/ADC2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector88) {
-  uint32_t isr;
-
-  CH_IRQ_PROLOGUE();
-
-#if STM32_ADC_DUAL_MODE
-  isr  = ADC1->ISR;
-  isr |= ADC2->ISR;
-  ADC1->ISR = isr;
-  ADC2->ISR = isr;
-#else /* !STM32_ADC_DUAL_MODE */
-  isr  = ADC1->ISR;
-  ADC1->ISR = isr;
-#endif /* !STM32_ADC_DUAL_MODE */
-
-  adc_lld_serve_interrupt(&ADCD1, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
-/**
- * @brief   ADC3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorFC) {
-  uint32_t isr;
-
-  CH_IRQ_PROLOGUE();
-
-  isr  = ADC3->ISR;
-  ADC3->ISR = isr;
-
-  adc_lld_serve_interrupt(&ADCD3, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if STM32_ADC_DUAL_MODE
-/**
- * @brief   ADC4 interrupt handler (as ADC3 slave).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector134) {
-  uint32_t isr;
-
-  CH_IRQ_PROLOGUE();
-
-  isr  = ADC4->ISR;
-  ADC4->ISR = isr;
-
-  adc_lld_serve_interrupt(&ADCD3, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_DUAL_MODE */
-#endif /* STM32_ADC_USE_ADC3 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if STM32_ADC_USE_ADC1
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-  ADCD1.adcc = ADC1_2;
-  ADCD1.adcm = ADC1;
-#if STM32_ADC_DUAL_MODE
-  ADCD1.adcs = ADC2;
-#endif
-  ADCD1.dmastp  = STM32_DMA1_STREAM1;
-  ADCD1.dmamode = ADC_DMA_SIZE |
-                  STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-  nvicEnableVector(ADC1_2_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_ADC_ADC12_IRQ_PRIORITY));
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC3
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD3);
-  ADCD3.adcc = ADC3_4;
-  ADCD3.adcm = ADC3;
-#if STM32_ADC_DUAL_MODE
-  ADCD3.adcs = ADC4;
-#endif
-  ADCD3.dmastp  = STM32_DMA2_STREAM5;
-  ADCD3.dmamode = ADC_DMA_SIZE |
-                  STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-  nvicEnableVector(ADC3_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
-#if STM32_ADC_DUAL_MODE
-  nvicEnableVector(ADC4_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_ADC_ADC34_IRQ_PRIORITY));
-#endif
-#endif /* STM32_ADC_USE_ADC3 */
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  /* If in stopped state then enables the ADC and DMA clocks.*/
-  if (adcp->state == ADC_STOP) {
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-      bool_t b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC12_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
-                            (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
-      rccEnableADC12(FALSE);
-    }
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC3
-    if (&ADCD3 == adcp) {
-      bool_t b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC34_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
-                            (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");
-      rccEnableADC34(FALSE);
-    }
-#endif /* STM32_ADC_USE_ADC2 */
-
-    /* Setting DMA peripheral-side pointer.*/
-#if STM32_ADC_DUAL_MODE
-      dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);
-#else
-      dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);
-#endif
-
-    /* Clock source setting.*/
-    adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
-
-    /* Master ADC calibration.*/
-    adc_lld_vreg_on(adcp);
-    adc_lld_calibrate(adcp);
-
-    /* Master ADC enabled here in order to reduce conversions latencies.*/
-    adc_lld_analog_on(adcp);
-  }
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  /* If in ready state then disables the ADC clock and analog part.*/
-  if (adcp->state == ADC_READY) {
-
-    /* Releasing the associated DMA channel.*/
-    dmaStreamRelease(adcp->dmastp);
-
-    /* Stopping the ongoing conversion, if any.*/
-    adc_lld_stop_adc(adcp);
-
-    /* Disabling ADC analog circuit and regulator.*/
-    adc_lld_analog_off(adcp);
-    adc_lld_vreg_off(adcp);
-
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp)
-      rccDisableADC12(FALSE);
-#endif
-
-#if STM32_ADC_USE_ADC3
-    if (&ADCD1 == adcp)
-      rccDisableADC34(FALSE);
-#endif
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t dmamode, ccr, cfgr;
-  const ADCConversionGroup *grpp = adcp->grpp;
-
-  chDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
-              "adc_lld_start_conversion(), #1",
-              "odd number of channels in dual mode");
-
-  /* Calculating control registers values.*/
-  dmamode = adcp->dmamode;
-  ccr     = grpp->ccr | (adcp->adcc->CCR & (ADC_CCR_CKMODE_MASK |
-                                            ADC_CCR_MDMA_MASK));
-  cfgr    = grpp->cfgr | ADC_CFGR_CONT | ADC_CFGR_DMAEN;
-  if (grpp->circular) {
-    dmamode |= STM32_DMA_CR_CIRC;
-#if STM32_ADC_DUAL_MODE
-    ccr  |= ADC_CCR_DMACFG_CIRCULAR;
-#else
-    cfgr |= ADC_CFGR_DMACFG_CIRCULAR;
-#endif
-    if (adcp->depth > 1) {
-      /* If circular buffer depth > 1, then the half transfer interrupt
-         is enabled in order to allow streaming processing.*/
-      dmamode |= STM32_DMA_CR_HTIE;
-    }
-  }
-
-  /* DMA setup.*/
-  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
-#if STM32_ADC_DUAL_MODE
-  dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *
-                                            (uint32_t)adcp->depth);
-#else
-    dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
-                                              (uint32_t)adcp->depth);
-#endif
-  dmaStreamSetMode(adcp->dmastp, dmamode);
-  dmaStreamEnable(adcp->dmastp);
-
-  /* Configuring the CCR register with the static settings ORed with
-     the user-specified settings in the conversion group configuration
-     structure.*/
-  adcp->adcc->CCR   = ccr;
-
-  /* ADC setup, if it is defined a callback for the analog watch dog then it
-     is enabled.*/
-  adcp->adcm->ISR   = adcp->adcm->ISR;
-  adcp->adcm->IER   = ADC_IER_OVR | ADC_IER_AWD1;
-  adcp->adcm->TR1   = grpp->tr1;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcm->SMPR1 = grpp->smpr[0];
-  adcp->adcm->SMPR2 = grpp->smpr[1];
-  adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
-  adcp->adcm->SQR2  = grpp->sqr[1];
-  adcp->adcm->SQR3  = grpp->sqr[2];
-  adcp->adcm->SQR4  = grpp->sqr[3];
-  adcp->adcs->SMPR1 = grpp->ssmpr[0];
-  adcp->adcs->SMPR2 = grpp->ssmpr[1];
-  adcp->adcs->SQR1  = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
-  adcp->adcs->SQR2  = grpp->ssqr[1];
-  adcp->adcs->SQR3  = grpp->ssqr[2];
-  adcp->adcs->SQR4  = grpp->ssqr[3];
-
-#else /* !STM32_ADC_DUAL_MODE */
-  adcp->adcm->SMPR1 = grpp->smpr[0];
-  adcp->adcm->SMPR2 = grpp->smpr[1];
-  adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
-  adcp->adcm->SQR2  = grpp->sqr[1];
-  adcp->adcm->SQR3  = grpp->sqr[2];
-  adcp->adcm->SQR4  = grpp->sqr[3];
-#endif /* !STM32_ADC_DUAL_MODE */
-
-  /* ADC configuration.*/
-  adcp->adcm->CFGR  = cfgr;
-
-  /* Starting conversion.*/
-  adcp->adcm->CR   |= ADC_CR_ADSTART;
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-  dmaStreamDisable(adcp->dmastp);
-  adc_lld_stop_adc(adcp);
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F30x/adc_lld.h b/os/hal/platforms/STM32F30x/adc_lld.h
deleted file mode 100644
index 85dd429f1..000000000
--- a/os/hal/platforms/STM32F30x/adc_lld.h
+++ /dev/null
@@ -1,612 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/adc_lld.h
- * @brief   STM32F30x ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Available analog channels
- * @{
- */
-#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
-#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
-#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
-#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
-#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
-#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
-#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
-#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
-#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
-#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
-#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
-#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
-#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
-#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
-#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
-#define ADC_CHANNEL_IN16        16  /**< @brief External analog input 16.   */
-#define ADC_CHANNEL_IN17        17  /**< @brief External analog input 17.   */
-#define ADC_CHANNEL_IN18        18  /**< @brief External analog input 18.   */
-/** @} */
-
-/**
- * @name    Sampling rates
- * @{
- */
-#define ADC_SMPR_SMP_1P5        0   /**< @brief 14 cycles conversion time   */
-#define ADC_SMPR_SMP_2P5        1   /**< @brief 15 cycles conversion time.  */
-#define ADC_SMPR_SMP_4P5        2   /**< @brief 17 cycles conversion time.  */
-#define ADC_SMPR_SMP_7P5        3   /**< @brief 20 cycles conversion time.  */
-#define ADC_SMPR_SMP_19P5       4   /**< @brief 32 cycles conversion time.  */
-#define ADC_SMPR_SMP_61P5       5   /**< @brief 74 cycles conversion time.  */
-#define ADC_SMPR_SMP_181P5      6   /**< @brief 194 cycles conversion time. */
-#define ADC_SMPR_SMP_601P5      7   /**< @brief 614 cycles conversion time. */
-/** @} */
-
-/**
- * @name    Resolution
- * @{
- */
-#define ADC_CFGR1_RES_12BIT     (0 << 3)
-#define ADC_CFGR1_RES_10BIT     (1 << 3)
-#define ADC_CFGR1_RES_8BIT      (2 << 3)
-#define ADC_CFGR1_RES_6BIT      (3 << 3)
-/** @} */
-
-/**
- * @name    CFGR register configuration helpers
- * @{
- */
-#define ADC_CFGR_DMACFG_MASK            (1 << 1)
-#define ADC_CFGR_DMACFG_ONESHOT         (0 << 1)
-#define ADC_CFGR_DMACFG_CIRCULAR        (1 << 1)
-
-#define ADC_CFGR_RES_MASK               (3 << 3)
-#define ADC_CFGR_RES_12BITS             (0 << 3)
-#define ADC_CFGR_RES_10BITS             (1 << 3)
-#define ADC_CFGR_RES_8BITS              (2 << 3)
-#define ADC_CFGR_RES_6BITS              (3 << 3)
-
-#define ADC_CFGR_ALIGN_MASK             (1 << 5)
-#define ADC_CFGR_ALIGN_RIGHT            (0 << 5)
-#define ADC_CFGR_ALIGN_LEFT             (1 << 5)
-
-#define ADC_CFGR_EXTSEL_MASK            (15 << 6)
-#define ADC_CFGR_EXTSEL_SRC(n)          ((n) << 6)
-
-#define ADC_CFGR_EXTEN_MASK             (3 << 10)
-#define ADC_CFGR_EXTEN_DISABLED         (0 << 10)
-#define ADC_CFGR_EXTEN_RISING           (1 << 10)
-#define ADC_CFGR_EXTEN_FALLING          (2 << 10)
-#define ADC_CFGR_EXTEN_BOTH             (3 << 10)
-
-#define ADC_CFGR_DISCEN_MASK            (1 << 16)
-#define ADC_CFGR_DISCEN_DISABLED        (0 << 16)
-#define ADC_CFGR_DISCEN_ENABLED         (1 << 16)
-
-#define ADC_CFGR_DISCNUM_MASK           (7 << 17)
-#define ADC_CFGR_DISCNUM_VAL(n)         ((n) << 17)
-
-#define ADC_CFGR_AWD1_DISABLED          0
-#define ADC_CFGR_AWD1_ALL               (1 << 23)
-#define ADC_CFGR_AWD1_SINGLE(n)         (((n) << 26) | (1 << 23) | (1 << 22))
-/** @} */
-
-/**
- * @name    CCR register configuration helpers
- * @{
- */
-#define ADC_CCR_DUAL_MASK               (31 << 0)
-#define ADC_CCR_DUAL(n)                 ((n) << 0)
-#define ADC_CCR_DELAY_MASK              (15 << 8)
-#define ADC_CCR_DELAY(n)                ((n) << 8)
-#define ADC_CCR_DMACFG_MASK             (1 << 13)
-#define ADC_CCR_DMACFG_ONESHOT          (0 << 13)
-#define ADC_CCR_DMACFG_CIRCULAR         (1 << 13)
-#define ADC_CCR_MDMA_MASK               (3 << 14)
-#define ADC_CCR_MDMA_DISABLED           (0 << 14)
-#define ADC_CCR_MDMA_WORD               (2 << 14)
-#define ADC_CCR_MDMA_HWORD              (3 << 14)
-#define ADC_CCR_CKMODE_MASK             (3 << 16)
-#define ADC_CCR_CKMODE_ADCCK            (0 << 16)
-#define ADC_CCR_CKMODE_AHB_DIV1         (1 << 16)
-#define ADC_CCR_CKMODE_AHB_DIV2         (2 << 16)
-#define ADC_CCR_CKMODE_AHB_DIV4         (3 << 16)
-#define ADC_CCR_VREFEN                  (1 << 22)
-#define ADC_CCR_TSEN                    (1 << 23)
-#define ADC_CCR_VBATEN                  (1 << 24)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1                  FALSE
-#endif
-
-/**
- * @brief   ADC3 driver enable switch.
- * @details If set to @p TRUE the support for ADC3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC3                  FALSE
-#endif
-
-/**
- * @brief   ADC1/ADC2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_DMA_PRIORITY        2
-#endif
-
-/**
- * @brief   ADC3/ADC4 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_DMA_PRIORITY        2
-#endif
-
-/**
- * @brief   ADC1/ADC2 interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_IRQ_PRIORITY        5
-#endif
-
-/**
- * @brief   ADC3/ADC4 interrupt priority level setting.
- */
-#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_IRQ_PRIORITY        5
-#endif
-
-/**
- * @brief   ADC1/ADC2 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5
-#endif
-
-/**
- * @brief   ADC3/ADC4 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5
-#endif
-
-/**
- * @brief   ADC1/ADC2 clock source and mode.
- */
-#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
-#endif
-
-/**
- * @brief   ADC3/ADC4 clock source and mode.
- */
-#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
-#endif
-
-/**
- * @brief   Enables the ADC master/slave mode.
- */
-#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_DUAL_MODE                 FALSE
-#endif
-
-/**
- * @brief   Makes the ADC samples type an 8bits one.
- */
-#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
-#define STM32_ADC_COMPACT_SAMPLES           FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
-#error "ADC1 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
-#error "ADC3 not present in the selected device"
-#endif
-
-#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC3
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1 DMA"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC3 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC3"
-#endif
-
-#if STM32_ADC_USE_ADC3 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC3 DMA"
-#endif
-
-#if STM32_ADC_USE_ADC3 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC3"
-#endif
-
-#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
-#define STM32_ADC12_CLOCK               STM32_ADC12CLK
-#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC12_CLOCK               (STM32_HCLK / 1)
-#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
-#define STM32_ADC12_CLOCK               (STM32_HCLK / 2)
-#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
-#define STM32_ADC12_CLOCK               (STM32_HCLK / 4)
-#else
-#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
-#endif
-
-#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
-#define STM32_ADC34_CLOCK               STM32_ADC34CLK
-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC34_CLOCK               (STM32_HCLK / 1)
-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
-#define STM32_ADC34_CLOCK               (STM32_HCLK / 2)
-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
-#define STM32_ADC34_CLOCK               (STM32_HCLK / 4)
-#else
-#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
-#endif
-
-#if STM32_ADC12_CLOCK > 72000000
-#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
-#endif
-
-#if STM32_ADC34_CLOCK > 72000000
-#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-#if !STM32_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)
-typedef uint16_t adcsample_t;
-#else
-typedef uint8_t adcsample_t;
-#endif
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
-  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
-  ADC_ERR_AWD1 = 2,                         /**< Watchdog 1 triggered.      */
-  ADC_ERR_AWD2 = 3,                         /**< Watchdog 2 triggered.      */
-  ADC_ERR_AWD3 = 4                          /**< Watchdog 3 triggered.      */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    The use of this configuration structure requires knowledge of
- *          STM32 ADC cell registers interface, please refer to the STM32
- *          reference manual for details.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   ADC CFGR register initialization data.
-   * @note    The bits DMAEN, DMACFG, OVRMOD, CONT are enforced internally
-   *          to the driver, keep them to zero.
-   */
-  uint32_t                  cfgr;
-  /**
-   * @brief   ADC TR1 register initialization data.
-   */
-  uint32_t                  tr1;
-  /**
-   * @brief   ADC CCR register initialization data.
-   * @note    The bits CKMODE, MDMA, DMACFG are enforced internally to the
-   *          driver, keep them to zero.
-   */
-  uint32_t                  ccr;
-  /**
-   * @brief   ADC SMPRx registers initialization data.
-   */
-  uint32_t                  smpr[2];
-  /**
-   * @brief   ADC SQRx register initialization data.
-   */
-  uint32_t                  sqr[4];
-#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
-  /**
-   * @brief   Slave ADC SMPRx registers initialization data.
-   */
-  uint32_t                  ssmpr[2];
-  /**
-   * @brief   Slave ADC SQRx register initialization data.
-   */
-  uint32_t                  ssqr[4];
-#endif /* STM32_ADC_DUAL_MODE */
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief   Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief   Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief   Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief   Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief   Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Pointer to the common ADCx_y registers block.
-   */
-  ADC_Common_TypeDef        *adcc;
-  /**
-   * @brief   Pointer to the master ADCx registers block.
-   */
-  ADC_TypeDef               *adcm;
-#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
-  /**
-   * @brief   Pointer to the slave ADCx registers block.
-   */
-  ADC_TypeDef               *adcs;
-#endif /* STM32_ADC_DUAL_MODE */
-  /**
-   * @brief   Pointer to associated DMA channel.
-   */
-  const stm32_dma_stream_t  *dmastp;
-  /**
-   * @brief   DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Threashold register initializer
- * @{
- */
-#define ADC_TR(low, high)       (((uint32_t)(high) << 16) | (uint32_t)(low))
-/** @} */
-
-/**
- * @name    Sequences building helper macros
- * @{
- */
-/**
- * @brief   Number of channels in a conversion sequence.
- */
-#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 0)
-
-#define ADC_SQR1_SQ1_N(n)       ((n) << 6)  /**< @brief 1st channel in seq. */
-#define ADC_SQR1_SQ2_N(n)       ((n) << 12) /**< @brief 2nd channel in seq. */
-#define ADC_SQR1_SQ3_N(n)       ((n) << 18) /**< @brief 3rd channel in seq. */
-#define ADC_SQR1_SQ4_N(n)       ((n) << 24) /**< @brief 4th channel in seq. */
-
-#define ADC_SQR2_SQ5_N(n)       ((n) << 0)  /**< @brief 5th channel in seq. */
-#define ADC_SQR2_SQ6_N(n)       ((n) << 6)  /**< @brief 6th channel in seq. */
-#define ADC_SQR2_SQ7_N(n)       ((n) << 12) /**< @brief 7th channel in seq. */
-#define ADC_SQR2_SQ8_N(n)       ((n) << 18) /**< @brief 8th channel in seq. */
-#define ADC_SQR2_SQ9_N(n)       ((n) << 24) /**< @brief 9th channel in seq. */
-
-#define ADC_SQR3_SQ10_N(n)      ((n) << 0)  /**< @brief 10th channel in seq.*/
-#define ADC_SQR3_SQ11_N(n)      ((n) << 6)  /**< @brief 11th channel in seq.*/
-#define ADC_SQR3_SQ12_N(n)      ((n) << 12) /**< @brief 12th channel in seq.*/
-#define ADC_SQR3_SQ13_N(n)      ((n) << 18) /**< @brief 13th channel in seq.*/
-#define ADC_SQR3_SQ14_N(n)      ((n) << 24) /**< @brief 14th channel in seq.*/
-
-#define ADC_SQR4_SQ15_N(n)      ((n) << 0)  /**< @brief 15th channel in seq.*/
-#define ADC_SQR4_SQ16_N(n)      ((n) << 6)  /**< @brief 16th channel in seq.*/
-/** @} */
-
-/**
- * @name    Sampling rate settings helper macros
- * @{
- */
-#define ADC_SMPR1_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
-#define ADC_SMPR1_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
-#define ADC_SMPR1_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
-#define ADC_SMPR1_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
-#define ADC_SMPR1_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
-#define ADC_SMPR1_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
-#define ADC_SMPR1_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
-#define ADC_SMPR1_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
-#define ADC_SMPR1_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
-
-#define ADC_SMPR2_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
-#define ADC_SMPR2_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
-#define ADC_SMPR2_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
-#define ADC_SMPR2_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
-#define ADC_SMPR2_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
-#define ADC_SMPR2_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
-#define ADC_SMPR2_SMP_AN16(n)   ((n) << 18) /**< @brief AN16 sampling time. */
-#define ADC_SMPR2_SMP_AN17(n)   ((n) << 21) /**< @brief AN17 sampling time. */
-#define ADC_SMPR2_SMP_AN18(n)   ((n) << 24) /**< @brief AN18 sampling time. */
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F30x/ext_lld_isr.c b/os/hal/platforms/STM32F30x/ext_lld_isr.c
deleted file mode 100644
index c9802713e..000000000
--- a/os/hal/platforms/STM32F30x/ext_lld_isr.c
+++ /dev/null
@@ -1,418 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/ext_lld_isr.c
- * @brief   STM32F30x EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if !defined(STM32_DISABLE_EXTI0_HANDLER)
-/**
- * @brief   EXTI[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector58) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 0);
-  EXTD1.config->channels[0].cb(&EXTD1, 0);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI1_HANDLER)
-/**
- * @brief   EXTI[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector5C) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 1);
-  EXTD1.config->channels[1].cb(&EXTD1, 1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI2_HANDLER)
-/**
- * @brief   EXTI[2] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector60) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 2);
-  EXTD1.config->channels[2].cb(&EXTD1, 2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI3_HANDLER)
-/**
- * @brief   EXTI[3] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector64) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 3);
-  EXTD1.config->channels[3].cb(&EXTD1, 3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI4_HANDLER)
-/**
- * @brief   EXTI[4] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector68) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 4);
-  EXTD1.config->channels[4].cb(&EXTD1, 4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
-/**
- * @brief   EXTI[5]...EXTI[9] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector9C) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
-  EXTI->PR = pr;
-  if (pr & (1 << 5))
-    EXTD1.config->channels[5].cb(&EXTD1, 5);
-  if (pr & (1 << 6))
-    EXTD1.config->channels[6].cb(&EXTD1, 6);
-  if (pr & (1 << 7))
-    EXTD1.config->channels[7].cb(&EXTD1, 7);
-  if (pr & (1 << 8))
-    EXTD1.config->channels[8].cb(&EXTD1, 8);
-  if (pr & (1 << 9))
-    EXTD1.config->channels[9].cb(&EXTD1, 9);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
-/**
- * @brief   EXTI[10]...EXTI[15] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorE0) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
-                   (1 << 15));
-  EXTI->PR = pr;
-  if (pr & (1 << 10))
-    EXTD1.config->channels[10].cb(&EXTD1, 10);
-  if (pr & (1 << 11))
-    EXTD1.config->channels[11].cb(&EXTD1, 11);
-  if (pr & (1 << 12))
-    EXTD1.config->channels[12].cb(&EXTD1, 12);
-  if (pr & (1 << 13))
-    EXTD1.config->channels[13].cb(&EXTD1, 13);
-  if (pr & (1 << 14))
-    EXTD1.config->channels[14].cb(&EXTD1, 14);
-  if (pr & (1 << 15))
-    EXTD1.config->channels[15].cb(&EXTD1, 15);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI16_HANDLER)
-/**
- * @brief   EXTI[16] interrupt handler (PVD).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector44) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 16);
-  EXTD1.config->channels[16].cb(&EXTD1, 16);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI17_HANDLER)
-/**
- * @brief   EXTI[17] interrupt handler (RTC Alarm).
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorE4) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 17);
-  EXTD1.config->channels[17].cb(&EXTD1, 17);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI18_HANDLER)
-/**
- * @brief   EXTI[18] interrupt handler (USB Wakeup).
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorE8) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 18);
-  EXTD1.config->channels[18].cb(&EXTD1, 18);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI19_HANDLER)
-/**
- * @brief   EXTI[19] interrupt handler (Tamper TimeStamp).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector48) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 19);
-  EXTD1.config->channels[19].cb(&EXTD1, 19);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI20_HANDLER)
-/**
- * @brief   EXTI[20] interrupt handler (RTC Wakeup).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector4C) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 20);
-  EXTD1.config->channels[20].cb(&EXTD1, 20);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER)
-/**
- * @brief   EXTI[21],EXTI[22],EXTI[29] interrupt handler (COMP1, COMP2, COMP3).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector140) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 21) | (1 << 22) | (1 << 29));
-  EXTI->PR = pr;
-  if (pr & (1 << 21))
-    EXTD1.config->channels[21].cb(&EXTD1, 21);
-  if (pr & (1 << 22))
-    EXTD1.config->channels[22].cb(&EXTD1, 22);
-  if (pr & (1 << 29))
-    EXTD1.config->channels[29].cb(&EXTD1, 29);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI30_32_HANDLER)
-/**
- * @brief   EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector144) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 30) | (1 << 31));
-  EXTI->PR = pr;
-  if (pr & (1 << 30))
-    EXTD1.config->channels[30].cb(&EXTD1, 30);
-  if (pr & (1 << 31))
-    EXTD1.config->channels[31].cb(&EXTD1, 31);
-
-  pr = EXTI->PR2 & (1 << 0);
-  EXTI->PR2 = pr;
-  if (pr & (1 << 0))
-    EXTD1.config->channels[32].cb(&EXTD1, 32);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI33_HANDLER)
-/**
- * @brief   EXTI[33] interrupt handler (COMP7).
- *
- * @isr
- */
-CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR2 = (1 << 1);
-  EXTD1.config->channels[33].cb(&EXTD1, 33);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(void) {
-
-  nvicEnableVector(EXTI0_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
-  nvicEnableVector(EXTI1_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
-  nvicEnableVector(EXTI2_TS_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
-  nvicEnableVector(EXTI3_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
-  nvicEnableVector(EXTI4_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
-  nvicEnableVector(EXTI9_5_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
-  nvicEnableVector(EXTI15_10_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
-  nvicEnableVector(PVD_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
-  nvicEnableVector(RTC_Alarm_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
-  nvicEnableVector(USBWakeUp_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
-  nvicEnableVector(TAMPER_STAMP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
-  nvicEnableVector(RTC_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
-  nvicEnableVector(COMP1_2_3_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY));
-  nvicEnableVector(COMP4_5_6_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI30_32_IRQ_PRIORITY));
-  nvicEnableVector(COMP7_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI33_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(void) {
-
-  nvicDisableVector(EXTI0_IRQn);
-  nvicDisableVector(EXTI1_IRQn);
-  nvicDisableVector(EXTI2_TS_IRQn);
-  nvicDisableVector(EXTI3_IRQn);
-  nvicDisableVector(EXTI4_IRQn);
-  nvicDisableVector(EXTI9_5_IRQn);
-  nvicDisableVector(EXTI15_10_IRQn);
-  nvicDisableVector(PVD_IRQn);
-  nvicDisableVector(RTC_Alarm_IRQn);
-  nvicDisableVector(USBWakeUp_IRQn);
-  nvicDisableVector(TAMPER_STAMP_IRQn);
-  nvicDisableVector(RTC_WKUP_IRQn);
-  nvicDisableVector(COMP1_2_3_IRQn);
-  nvicDisableVector(COMP4_5_6_IRQn);
-  nvicDisableVector(COMP7_IRQn);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F30x/hal_lld.c b/os/hal/platforms/STM32F30x/hal_lld.c
deleted file mode 100644
index 1df31f277..000000000
--- a/os/hal/platforms/STM32F30x/hal_lld.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/hal_lld.c
- * @brief   STM32F30x HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes the backup domain.
- * @note    WARNING! Changing clock source impossible without resetting
- *          of the whole BKP domain.
- */
-static void hal_lld_backup_domain_init(void) {
-
-  /* Backup domain access enabled and left open.*/
-  PWR->CR |= PWR_CR_DBP;
-
-  /* Reset BKP domain if different clock source selected.*/
-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
-    /* Backup domain reset.*/
-    RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0;
-  }
-
-  /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-#if defined(STM32_LSE_BYPASS)
-  /* LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
-#else
-  /* No LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
-#endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
-#endif
-
-#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
-  /* If the backup domain hasn't been initialized yet then proceed with
-     initialization.*/
-  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
-    /* Selects clock source.*/
-    RCC->BDCR |= STM32_RTCSEL;
-
-    /* RTC clock enabled.*/
-    RCC->BDCR |= RCC_BDCR_RTCEN;
-  }
-#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* Reset of all peripherals.*/
-  rccResetAPB1(0xFFFFFFFF);
-  rccResetAPB2(0xFFFFFFFF);
-
-  /* SysTick initialization using the system clock.*/
-  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-
-  /* DWT cycle counter enable.*/
-  SCS_DEMCR |= SCS_DEMCR_TRCENA;
-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
-
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(FALSE);
-
-  /* Initializes the backup domain.*/
-  hal_lld_backup_domain_init();
-
-#if defined(STM32_DMA_REQUIRED)
-  dmaInit();
-#endif
-
-  /* Programmable voltage detector enable.*/
-#if STM32_PVD_ENABLE
-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-#endif /* STM32_PVD_ENABLE */
-
-  /* SYSCFG clock enabled here because it is a multi-functional unit shared
-     among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
-
-  /* USB IRQ relocated to not conflict with CAN.*/
-  SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
-}
-
-/**
- * @brief   STM32 clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function should be invoked just after the system reset.
- *
- * @special
- */
-void stm32_clock_init(void) {
-
-#if !STM32_NO_INIT
-  /* HSI setup, it enforces the reset situation in order to handle possible
-     problems with JTAG probes and re-initializations.*/
-  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;                                       /* Wait until HSI is stable.    */
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
-  RCC->CFGR = 0;                            /* CFGR reset value.            */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;                                       /* Waits until HSI is selected. */
-
-#if STM32_HSE_ENABLED
-  /* HSE activation.*/
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
-#else
-  /* No HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON;
-#endif
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;                                       /* Waits until HSE is stable.   */
-#endif
-
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                                       /* Waits until LSI is stable.   */
-#endif
-
-  /* Clock settings.*/
-  RCC->CFGR  = STM32_MCOSEL    | STM32_USBPRE    | STM32_PLLMUL   |
-               STM32_PLLSRC    | STM32_PPRE1     | STM32_PPRE2    |
-               STM32_HPRE;
-  RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;
-  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |
-               STM32_USART2SW  | STM32_TIM8SW    | STM32_TIM1SW   |
-               STM32_I2C2SW    | STM32_I2C1SW    | STM32_USART1SW;
-
-#if STM32_ACTIVATE_PLL
-  /* PLL activation.*/
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;                                       /* Waits until PLL is stable.   */
-#endif
-
-  /* Flash setup and final clock selection.   */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* Switching to the configured clock source if it is different from HSI.*/
-#if (STM32_SW != STM32_SW_HSI)
-  /* Switches clock source.*/
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;                                       /* Waits selection complete.    */
-#endif
-#endif /* !STM32_NO_INIT */
-}
-
-/** @} */
diff --git a/os/hal/platforms/STM32F30x/hal_lld.h b/os/hal/platforms/STM32F30x/hal_lld.h
deleted file mode 100644
index 7085abb94..000000000
--- a/os/hal/platforms/STM32F30x/hal_lld.h
+++ /dev/null
@@ -1,1137 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/hal_lld.h
- * @brief   STM32F30x HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - STM32_LSECLK.
- *          - STM32_LSEDRV.
- *          - STM32_LSE_BYPASS (optionally).
- *          - STM32_HSECLK.
- *          - STM32_HSE_BYPASS (optionally).
- *          .
- *          One of the following macros must also be defined:
- *          - STM32F30X for Analog & DSP devices.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "stm32.h"
-#include "stm32_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @name    Platform identification
- * @{
- */
-#define PLATFORM_NAME           "STM32F30x Analog & DSP"
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum system clock frequency.
- */
-#define STM32_SYSCLK_MAX        72000000
-
-/**
- * @brief   Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX        32000000
-
-/**
- * @brief   Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN        1000000
-
-/**
- * @brief   Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX        1000000
-
-/**
- * @brief   Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN        32768
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MAX         24000000
-
-/**
- * @brief   Minimum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MIN         1000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MAX        72000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MIN        16000000
-
-/**
- * @brief   Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX         36000000
-
-/**
- * @brief   Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX         72000000
-
-/**
- * @brief   Maximum ADC clock frequency.
- */
-#define STM32_ADCCLK_MAX        72000000
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define STM32_HSICLK            8000000     /**< High speed internal clock. */
-#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
-/** @} */
-
-/**
- * @name    PWR_CR register bits definitions
- * @{
- */
-#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
-#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
-#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
-#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
-#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
-#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
-#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
-#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
-#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
-/** @} */
-
-/**
- * @name    RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
-#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
-#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
-
-#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
-#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
-#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
-#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
-#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
-#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
-#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
-#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
-#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
-
-#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
-#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
-#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
-#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
-#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
-
-#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
-#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
-#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
-#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
-#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
-
-#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI/2. */
-#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is
-                                                 HSE/PREDIV.                */
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)   /**< USB clock is PLLCLK/1.5.   */
-#define STM32_USBPRE_DIV1       (1 << 22)   /**< USB clock is PLLCLK/1.     */
-
-#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
-#define STM32_MCOSEL_LSI        (2 << 24)   /**< LSI clock on MCO pin.      */
-#define STM32_MCOSEL_LSE        (3 << 24)   /**< LSE clock on MCO pin.      */
-#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
-#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
-#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
-#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
-/** @} */
-
-/**
- * @name    RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
-#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
-#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
-#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
-#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 32 used as
-                                                 RTC clock.                 */
-/** @} */
-
-/**
- * @name    RCC_CFGR2 register bits definitions
- * @{
- */
-#define STM32_PREDIV_MASK       (15 << 0)   /**< PREDIV divisor mask.       */
-#define STM32_ADC12PRES_MASK    (31 << 4)   /**< ADC12 clock source mask.   */
-#define STM32_ADC12PRES_NOCLOCK (0 << 4)    /**< ADC12 clock is disabled.   */
-#define STM32_ADC12PRES_DIV1    (16 << 4)   /**< ADC12 clock is PLL/1.      */
-#define STM32_ADC12PRES_DIV2    (17 << 4)   /**< ADC12 clock is PLL/2.      */
-#define STM32_ADC12PRES_DIV4    (18 << 4)   /**< ADC12 clock is PLL/4.      */
-#define STM32_ADC12PRES_DIV6    (19 << 4)   /**< ADC12 clock is PLL/6.      */
-#define STM32_ADC12PRES_DIV8    (20 << 4)   /**< ADC12 clock is PLL/8.      */
-#define STM32_ADC12PRES_DIV10   (21 << 4)   /**< ADC12 clock is PLL/10.     */
-#define STM32_ADC12PRES_DIV12   (22 << 4)   /**< ADC12 clock is PLL/12.     */
-#define STM32_ADC12PRES_DIV16   (23 << 4)   /**< ADC12 clock is PLL/16.     */
-#define STM32_ADC12PRES_DIV32   (24 << 4)   /**< ADC12 clock is PLL/32.     */
-#define STM32_ADC12PRES_DIV64   (25 << 4)   /**< ADC12 clock is PLL/64.     */
-#define STM32_ADC12PRES_DIV128  (26 << 4)   /**< ADC12 clock is PLL/128.    */
-#define STM32_ADC12PRES_DIV256  (27 << 4)   /**< ADC12 clock is PLL/256.    */
-#define STM32_ADC34PRES_MASK    (31 << 9)   /**< ADC34 clock source mask.   */
-#define STM32_ADC34PRES_NOCLOCK (0 << 9)    /**< ADC34 clock is disabled.   */
-#define STM32_ADC34PRES_DIV1    (16 << 9)   /**< ADC34 clock is PLL/1.      */
-#define STM32_ADC34PRES_DIV2    (17 << 9)   /**< ADC34 clock is PLL/2.      */
-#define STM32_ADC34PRES_DIV4    (18 << 9)   /**< ADC34 clock is PLL/4.      */
-#define STM32_ADC34PRES_DIV6    (19 << 9)   /**< ADC34 clock is PLL/6.      */
-#define STM32_ADC34PRES_DIV8    (20 << 9)   /**< ADC34 clock is PLL/8.      */
-#define STM32_ADC34PRES_DIV10   (21 << 9)   /**< ADC34 clock is PLL/10.     */
-#define STM32_ADC34PRES_DIV12   (22 << 9)   /**< ADC34 clock is PLL/12.     */
-#define STM32_ADC34PRES_DIV16   (23 << 9)   /**< ADC34 clock is PLL/16.     */
-#define STM32_ADC34PRES_DIV32   (24 << 9)   /**< ADC34 clock is PLL/32.     */
-#define STM32_ADC34PRES_DIV64   (25 << 9)   /**< ADC34 clock is PLL/64.     */
-#define STM32_ADC34PRES_DIV128  (26 << 9)   /**< ADC34 clock is PLL/128.    */
-#define STM32_ADC34PRES_DIV256  (27 << 9)   /**< ADC34 clock is PLL/256.    */
-/** @} */
-
-/**
- * @name    RCC_CFGR3 register bits definitions
- * @{
- */
-#define STM32_USART1SW_MASK     (3 << 0)    /**< USART1 clock source mask. */
-#define STM32_USART1SW_PCLK     (0 << 0)    /**< USART1 clock is PCLK.     */
-#define STM32_USART1SW_SYSCLK   (1 << 0)    /**< USART1 clock is SYSCLK.   */
-#define STM32_USART1SW_LSE      (2 << 0)    /**< USART1 clock is LSE.      */
-#define STM32_USART1SW_HSI      (3 << 0)    /**< USART1 clock is HSI.      */
-#define STM32_I2C1SW_MASK       (1 << 4)    /**< I2C1 clock source mask.   */
-#define STM32_I2C1SW_HSI        (0 << 4)    /**< I2C1 clock is HSI.        */
-#define STM32_I2C1SW_SYSCLK     (1 << 4)    /**< I2C1 clock is SYSCLK.     */
-#define STM32_I2C2SW_MASK       (1 << 5)    /**< I2C2 clock source mask.   */
-#define STM32_I2C2SW_HSI        (0 << 5)    /**< I2C2 clock is HSI.        */
-#define STM32_I2C2SW_SYSCLK     (1 << 5)    /**< I2C2 clock is SYSCLK.     */
-#define STM32_TIM1SW_MASK       (1 << 8)    /**< TIM1 clock source mask.   */
-#define STM32_TIM1SW_PCLK2      (0 << 8)    /**< TIM1 clock is PCLK2.      */
-#define STM32_TIM1SW_PLLX2      (1 << 8)    /**< TIM1 clock is PLL*2.      */
-#define STM32_TIM8SW_MASK       (1 << 9)    /**< TIM8 clock source mask.   */
-#define STM32_TIM8SW_PCLK2      (0 << 9)    /**< TIM8 clock is PCLK2.      */
-#define STM32_TIM8SW_PLLX2      (1 << 9)    /**< TIM8 clock is PLL*2.      */
-#define STM32_USART2SW_MASK     (3 << 16)   /**< USART2 clock source mask. */
-#define STM32_USART2SW_PCLK     (0 << 16)   /**< USART2 clock is PCLK.     */
-#define STM32_USART2SW_SYSCLK   (1 << 16)   /**< USART2 clock is SYSCLK.   */
-#define STM32_USART2SW_LSE      (2 << 16)   /**< USART2 clock is LSE.      */
-#define STM32_USART2SW_HSI      (3 << 16)   /**< USART2 clock is HSI.      */
-#define STM32_USART3SW_MASK     (3 << 18)   /**< USART3 clock source mask. */
-#define STM32_USART3SW_PCLK     (0 << 18)   /**< USART3 clock is PCLK.     */
-#define STM32_USART3SW_SYSCLK   (1 << 18)   /**< USART3 clock is SYSCLK.   */
-#define STM32_USART3SW_LSE      (2 << 18)   /**< USART3 clock is LSE.      */
-#define STM32_USART3SW_HSI      (3 << 18)   /**< USART3 clock is HSI.      */
-#define STM32_UART4SW_MASK      (3 << 20)   /**< USART4 clock source mask. */
-#define STM32_UART4SW_PCLK      (0 << 20)   /**< USART4 clock is PCLK.     */
-#define STM32_UART4SW_SYSCLK    (1 << 20)   /**< USART4 clock is SYSCLK.   */
-#define STM32_UART4SW_LSE       (2 << 20)   /**< USART4 clock is LSE.      */
-#define STM32_UART4SW_HSI       (3 << 20)   /**< USART4 clock is HSI.      */
-#define STM32_UART5SW_MASK      (3 << 22)   /**< USART5 clock source mask. */
-#define STM32_UART5SW_PCLK      (0 << 22)   /**< USART5 clock is PCLK.     */
-#define STM32_UART5SW_SYSCLK    (1 << 22)   /**< USART5 clock is SYSCLK.   */
-#define STM32_UART5SW_LSE       (2 << 22)   /**< USART5 clock is LSE.      */
-#define STM32_UART5SW_HSI       (3 << 22)   /**< USART5 clock is HSI.      */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Disables the PWR/RCC initialization in the HAL.
- */
-#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT                       FALSE
-#endif
-
-/**
- * @brief   Enables or disables the programmable voltage detector.
- */
-#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE                    FALSE
-#endif
-
-/**
- * @brief   Sets voltage level for programmable voltage detector.
- */
-#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS                           STM32_PLS_LEV0
-#endif
-
-/**
- * @brief   Enables or disables the HSI clock source.
- */
-#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI_ENABLED                   TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSI clock source.
- */
-#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED                   TRUE
-#endif
-
-/**
- * @brief   Enables or disables the HSE clock source.
- */
-#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED                   TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSE clock source.
- */
-#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED                   FALSE
-#endif
-
-/**
- * @brief   Main clock source selection.
- * @note    If the selected clock source is not the PLL then the PLL is not
- *          initialized and started.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW                            STM32_SW_PLL
-#endif
-
-/**
- * @brief   Clock source for the PLL.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                        STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief   Crystal PLL pre-divider.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
-#define STM32_PREDIV_VALUE                  1
-#endif
-
-/**
- * @brief   PLL multiplier value.
- * @note    The allowed range is 2...16.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE                  9
-#endif
-
-/**
- * @brief   AHB prescaler value.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE                          STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief   APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1                         STM32_PPRE1_DIV2
-#endif
-
-/**
- * @brief   APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2                         STM32_PPRE2_DIV2
-#endif
-
-/**
- * @brief   MCO pin setting.
- */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
-#endif
-
-/**
- * @brief   ADC12 prescaler value.
- */
-#if !defined(STM32_ADC12PRES) || defined(__DOXYGEN__)
-#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV1
-#endif
-
-/**
- * @brief   ADC34 prescaler value.
- */
-#if !defined(STM32_ADC34PRES) || defined(__DOXYGEN__)
-#define STM32_ADC34PRES                     STM32_ADC34PRES_DIV1
-#endif
-
-/**
- * @brief   USART1 clock source.
- */
-#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
-#define STM32_USART1SW                      STM32_USART1SW_PCLK
-#endif
-
-/**
- * @brief   USART2 clock source.
- */
-#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
-#define STM32_USART2SW                      STM32_USART2SW_PCLK
-#endif
-
-/**
- * @brief   USART3 clock source.
- */
-#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
-#define STM32_USART3SW                      STM32_USART3SW_PCLK
-#endif
-
-/**
- * @brief   UART4 clock source.
- */
-#if !defined(STM32_UART4SW) || defined(__DOXYGEN__)
-#define STM32_UART4SW                       STM32_UART4SW_PCLK
-#endif
-
-/**
- * @brief   UART5 clock source.
- */
-#if !defined(STM32_UART5SW) || defined(__DOXYGEN__)
-#define STM32_UART5SW                       STM32_UART5SW_PCLK
-#endif
-
-/**
- * @brief   I2C1 clock source.
- */
-#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
-#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK
-#endif
-
-/**
- * @brief   I2C2 clock source.
- */
-#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
-#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK
-#endif
-
-/**
- * @brief   TIM1 clock source.
- */
-#if !defined(STM32_TIM1SW) || defined(__DOXYGEN__)
-#define STM32_TIM1SW                        STM32_TIM1SW_PCLK2
-#endif
-
-/**
- * @brief   TIM8 clock source.
- */
-#if !defined(STM32_TIM8SW) || defined(__DOXYGEN__)
-#define STM32_TIM8SW                        STM32_TIM8SW_PCLK2
-#endif
-
-/**
- * @brief   RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL                        STM32_RTCSEL_LSI
-#endif
-
-/**
- * @brief   USB clock setting.
- */
-#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
-#define STM32_USB_CLOCK_REQUIRED            TRUE
-#endif
-
-/**
- * @brief   USB prescaler initialization.
- */
-#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
-#define STM32_USBPRE                        STM32_USBPRE_DIV1P5
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F30x_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F30x_MCUCONF not defined"
-#endif
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if STM32_USART1SW == STM32_USART1SW_HSI
-#error "HSI not enabled, required by STM32_USART1SW"
-#endif
-
-#if STM32_USART2SW == STM32_USART2SW_HSI
-#error "HSI not enabled, required by STM32_USART2SW"
-#endif
-
-#if STM32_USART3SW == STM32_USART3SW_HSI
-#error "HSI not enabled, required by STM32_USART3SW"
-#endif
-
-#if STM32_UART4SW == STM32_UART4SW_HSI
-#error "HSI not enabled, required by STM32_UART4SW"
-#endif
-
-#if STM32_UART5SW == STM32_UART5SW_HSI
-#error "HSI not enabled, required by STM32_UART5SW"
-#endif
-
-#if STM32_I2C1SW == STM32_I2C1SW_HSI
-#error "HSI not enabled, required by STM32_I2C1SW"
-#endif
-
-#if STM32_I2C2SW == STM32_I2C2SW_HSI
-#error "HSI not enabled, required by STM32_I2C2SW"
-#endif
-
-#if STM32_TIM1SW == STM32_TIM1SW_HSI
-#error "HSI not enabled, required by STM32_TIM1SW"
-#endif
-
-#if STM32_TIM8SW == STM32_TIM8SW_HSI
-#error "HSI not enabled, required by STM32_TIM8SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCOSEL"
-#endif
-
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCOSEL"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSI
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0)
-#error "STM32_LSECLK not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#if !defined(STM32_LSEDRV)
-#error "STM32_LSEDRV not defined"
-#endif
-
-#if (STM32_LSEDRV >> 3) > 3
-#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
-#endif
-
-#if STM32_USART1SW == STM32_USART1SW_LSE
-#error "LSE not enabled, required by STM32_USART1SW"
-#endif
-
-#if STM32_USART2SW == STM32_USART2SW_LSE
-#error "LSE not enabled, required by STM32_USART2SW"
-#endif
-
-#if STM32_USART3SW == STM32_USART3SW_LSE
-#error "LSE not enabled, required by STM32_USART3SW"
-#endif
-
-#if STM32_UART4SW == STM32_UART4SW_LSE
-#error "LSE not enabled, required by STM32_UART4SW"
-#endif
-
-#if STM32_UART5SW == STM32_UART5SW_LSE
-#error "LSE not enabled, required by STM32_UART5SW"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/* PLL activation conditions.*/
-#if (STM32_SW == STM32_SW_PLL) ||                                           \
-    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
-    (STM32_TIM1SW == STM32_TIM1SW_PLLX2) ||                                 \
-    (STM32_TIM8SW == STM32_TIM8SW_PLLX2) ||                                 \
-    (STM32_ADC12PRES != STM32_ADC12PRES_NOCLOCK) ||                         \
-    (STM32_ADC34PRES != STM32_ADC34PRES_NOCLOCK) ||                         \
-    STM32_USB_CLOCK_REQUIRED ||                                             \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL          TRUE
-#else
-#define STM32_ACTIVATE_PLL          FALSE
-#endif
-
-/* HSE prescaler setting check.*/
-#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
-#define STM32_PREDIV                ((STM32_PREDIV_VALUE - 1) << 0)
-#else
-#error "invalid STM32_PREDIV value specified"
-#endif
-
-/**
- * @brief   PLLMUL field.
- */
-#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
-    defined(__DOXYGEN__)
-#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
-#else
-#error "invalid STM32_PLLMUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PREDIV_VALUE)
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/* PLL input frequency range check.*/
-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
-#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
-#endif
-
-/**
- * @brief   System clock source.
- */
-#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
-#define STM32_SYSCLK                STM32_PLLCLKOUT
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/* AHB frequency check.*/
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                  (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                  (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                  (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                  (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                  (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/* APB1 frequency check.*/
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief   APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                  (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                  (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                  (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                  (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                  (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/**
- * @brief   RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                (STM32_HSECLK / 32)
-#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
-#define STM32_RTCCLK                0
-#else
-#error "invalid source selected for RTC clock"
-#endif
-
-/**
- * @brief   ADC12 frequency.
- */
-#if (STM32_ADC12PRES == STM32_ADC12PRES_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_ADC12CLK              0
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV1
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 1)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV2
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 2)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV4
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 4)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV6
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 6)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV8
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 8)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV10
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 10)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV12
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 12)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV16
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 16)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV32
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 32)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV64
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 64)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV128
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 128)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV256
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 256)
-#else
-#error "invalid STM32_ADC12PRES value specified"
-#endif
-
-/**
- * @brief   ADC34 frequency.
- */
-#if (STM32_ADC43PRES == STM32_ADC34PRES_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_ADC34CLK              0
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV1
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 1)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV2
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 2)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV4
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 4)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV6
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 6)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV8
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 8)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV10
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 10)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV12
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 12)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV16
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 16)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV32
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 32)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV64
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 64)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV128
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 128)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV256
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 256)
-#else
-#error "invalid STM32_ADC34PRES value specified"
-#endif
-
-/* ADC12 frequency check.*/
-#if STM32_ADC12CLK > STM32_ADCCLK_MAX
-#error "STM32_ADC12CLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/* ADC34 frequency check.*/
-#if STM32_ADC34CLK > STM32_ADCCLK_MAX
-#error "STM32_ADC34CLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/**
- * @brief   I2C1 frequency.
- */
-#if STM32_I2C1SW == STM32_I2C1SW_HSI
-#define STM32_I2C1CLK               STM32_HSICLK
-#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
-#define STM32_I2C1CLK               STM32_SYSCLK
-#else
-#error "invalid source selected for I2C1 clock"
-#endif
-
-/**
- * @brief   I2C2 frequency.
- */
-#if STM32_I2C2SW == STM32_I2C2SW_HSI
-#define STM32_I2C2CLK               STM32_HSICLK
-#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK
-#define STM32_I2C2CLK               STM32_SYSCLK
-#else
-#error "invalid source selected for I2C2 clock"
-#endif
-
-/**
- * @brief   USART1 frequency.
- */
-#if STM32_USART1SW == STM32_USART1SW_PCLK
-#define STM32_USART1CLK             STM32_PCLK2
-#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
-#define STM32_USART1CLK             STM32_SYSCLK
-#elif STM32_USART1SW == STM32_USART1SW_LSECLK
-#define STM32_USART1CLK             STM32_LSECLK
-#elif STM32_USART1SW == STM32_USART1SW_HSICLK
-#define STM32_USART1CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART1 clock"
-#endif
-
-/**
- * @brief   USART2 frequency.
- */
-#if STM32_USART2SW == STM32_USART2SW_PCLK
-#define STM32_USART2CLK             STM32_PCLK1
-#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
-#define STM32_USART2CLK             STM32_SYSCLK
-#elif STM32_USART2SW == STM32_USART2SW_LSECLK
-#define STM32_USART2CLK             STM32_LSECLK
-#elif STM32_USART2SW == STM32_USART2SW_HSICLK
-#define STM32_USART2CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART2 clock"
-#endif
-
-/**
- * @brief   USART3 frequency.
- */
-#if STM32_USART3SW == STM32_USART3SW_PCLK
-#define STM32_USART3CLK             STM32_PCLK1
-#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
-#define STM32_USART3CLK             STM32_SYSCLK
-#elif STM32_USART3SW == STM32_USART3SW_LSECLK
-#define STM32_USART3CLK             STM32_LSECLK
-#elif STM32_USART3SW == STM32_USART3SW_HSICLK
-#define STM32_USART3CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART3 clock"
-#endif
-
-/**
- * @brief   UART4 frequency.
- */
-#if STM32_UART4SW == STM32_UART4SW_PCLK
-#define STM32_UART4CLK             STM32_PCLK1
-#elif STM32_UART4SW == STM32_UART4SW_SYSCLK
-#define STM32_UART4CLK             STM32_SYSCLK
-#elif STM32_UART4SW == STM32_UART4SW_LSECLK
-#define STM32_UART4CLK             STM32_LSECLK
-#elif STM32_UART4SW == STM32_UART4SW_HSICLK
-#define STM32_UART4CLK             STM32_HSICLK
-#else
-#error "invalid source selected for UART4 clock"
-#endif
-
-/**
- * @brief   UART5 frequency.
- */
-#if STM32_UART5SW == STM32_UART5SW_PCLK
-#define STM32_UART5CLK             STM32_PCLK1
-#elif STM32_UART5SW == STM32_UART5SW_SYSCLK
-#define STM32_UART5CLK             STM32_SYSCLK
-#elif STM32_UART5SW == STM32_UART5SW_LSECLK
-#define STM32_UART5CLK             STM32_LSECLK
-#elif STM32_UART5SW == STM32_UART5SW_HSICLK
-#define STM32_UART5CLK             STM32_HSICLK
-#else
-#error "invalid source selected for UART5 clock"
-#endif
-
-/**
- * @brief   TIM1 frequency.
- */
-#if STM32_TIM1SW == STM32_TIM1SW_PCLK2
-#define STM32_TIM1CLK               STM32_PCLK2
-#elif STM32_TIM1SW == STM32_TIM1SW_PLLX2
-#define STM32_TIM1CLK               (STM32_PLLCLKOUT * 2)
-#else
-#error "invalid source selected for TIM1 clock"
-#endif
-
-/**
- * @brief   TIM8 frequency.
- */
-#if STM32_TIM8SW == STM32_TIM8SW_PCLK2
-#define STM32_TIM8CLK               STM32_PCLK2
-#elif STM32_TIM8SW == STM32_TIM8SW_PLLX2
-#define STM32_TIM8CLK               (STM32_PLLCLKOUT * 2)
-#else
-#error "invalid source selected for TIM8 clock"
-#endif
-
-/**
- * @brief   Timers 2, 3, 4, 6, 7 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief   Timers 1, 8, 15, 16, 17 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
-#endif
-
-/**
- * @brief   USB frequency.
- */
-#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
-#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
-#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
-#define STM32_USBCLK                STM32_PLLCLKOUT
-#else
-#error "invalid STM32_USBPRE value specified"
-#endif
-
-/**
- * @brief   Flash settings.
- */
-#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS             0x00000010
-#elif STM32_HCLK <= 48000000
-#define STM32_FLASHBITS             0x00000011
-#else
-#define STM32_FLASHBITS             0x00000012
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief   Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This service is implemented by returning the content of the
- *          DWT_CYCCNT register.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value()         DWT_CYCCNT
-
-/**
- * @brief   Realtime counter frequency.
- * @note    The DWT_CYCCNT register is incremented directly by the system
- *          clock so this function returns STM32_HCLK.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency()     STM32_HCLK
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-/* STM32 ISR, DMA and RCC helpers.*/
-#include "stm32_isr.h"
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void stm32_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F30x/platform.mk b/os/hal/platforms/STM32F30x/platform.mk
deleted file mode 100644
index ef55085b8..000000000
--- a/os/hal/platforms/STM32F30x/platform.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-# List of all the STM32F30x platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F30x/stm32_dma.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F30x/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F30x/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F30x/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F30x \
-              ${CHIBIOS}/os/hal/platforms/STM32 \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USBv1
diff --git a/os/hal/platforms/STM32F30x/stm32_dma.c b/os/hal/platforms/STM32F30x/stm32_dma.c
deleted file mode 100644
index 95181c90f..000000000
--- a/os/hal/platforms/STM32F30x/stm32_dma.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/stm32_dma.c
- * @brief   DMA helper driver code.
- *
- * @addtogroup STM32F30x_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- *          shared resource, this driver allows to allocate and free DMA
- *          streams at runtime in order to allow all the other device
- *          drivers to coordinate the access to the resource.
- * @note    The DMA ISR handlers are all declared into this module because
- *          sharing, the various device drivers can associate a callback to
- *          ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
-   has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK     0x0000007F
-
-/**
- * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK     0x00000F80
-
-/**
- * @brief   Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE   0x00000000
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- *          identifier and the involved physical registers.
- * @note    Don't use this array directly, use the appropriate wrapper macros
- *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
-  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
-  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
-  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
-  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
-  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
-  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
-  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
-  {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
-  {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
-  {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
-  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
-  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
-};
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DMA ISR redirector type.
- */
-typedef struct {
-  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
-  void                  *dma_param;     /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief   Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief   DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector6C) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 0;
-  if (dma_isr_redir[0].dma_func)
-    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector70) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 4;
-  if (dma_isr_redir[1].dma_func)
-    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector74) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 8;
-  if (dma_isr_redir[2].dma_func)
-    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector78) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 12;
-  if (dma_isr_redir[3].dma_func)
-    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector7C) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 16;
-  if (dma_isr_redir[4].dma_func)
-    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector80) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 20;
-  if (dma_isr_redir[5].dma_func)
-    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector84) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 24;
-  if (dma_isr_redir[6].dma_func)
-    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector120) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 0;
-  if (dma_isr_redir[7].dma_func)
-    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector124) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 4;
-  if (dma_isr_redir[8].dma_func)
-    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector128) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 8;
-  if (dma_isr_redir[9].dma_func)
-    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector12C) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 12;
-  if (dma_isr_redir[10].dma_func)
-    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector130) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 16;
-  if (dma_isr_redir[11].dma_func)
-    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
-  int i;
-
-  dma_streams_mask = 0;
-  for (i = 0; i < STM32_DMA_STREAMS; i++) {
-    _stm32_dma_streams[i].channel->CCR = 0;
-    dma_isr_redir[i].dma_func = NULL;
-  }
-  DMA1->IFCR = 0xFFFFFFFF;
-#if STM32_HAS_DMA2
-  DMA2->IFCR = 0xFFFFFFFF;
-#endif
-}
-
-/**
- * @brief   Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- *          The function also enables the IRQ vector associated to the stream
- *          and initializes its priority.
- * @pre     The stream must not be already in use or an error is returned.
- * @post    The stream is allocated and the default ISR handler redirected
- *          to the specified function.
- * @post    The stream ISR vector is enabled and its priority configured.
- * @post    The stream must be freed using @p dmaStreamRelease() before it can
- *          be reused with another peripheral.
- * @post    The stream is in its post-reset state.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] priority  IRQ priority mask for the DMA stream
- * @param[in] func      handling function pointer, can be @p NULL
- * @param[in] param     a parameter to be passed to the handling function
- * @return              The operation status.
- * @retval FALSE        no error, stream taken.
- * @retval TRUE         error, stream already taken.
- *
- * @special
- */
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                         uint32_t priority,
-                         stm32_dmaisr_t func,
-                         void *param) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
-
-  /* Checks if the stream is already taken.*/
-  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
-    return TRUE;
-
-  /* Marks the stream as allocated.*/
-  dma_isr_redir[dmastp->selfindex].dma_func  = func;
-  dma_isr_redir[dmastp->selfindex].dma_param = param;
-  dma_streams_mask |= (1 << dmastp->selfindex);
-
-  /* Enabling DMA clocks required by the current streams set.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
-    rccEnableDMA1(FALSE);
-#if STM32_HAS_DMA2
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
-    rccEnableDMA2(FALSE);
-#endif
-
-  /* Putting the stream in a safe state.*/
-  dmaStreamDisable(dmastp);
-  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
-
-  /* Enables the associated IRQ vector if a callback is defined.*/
-  if (func != NULL)
-    nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
-
-  return FALSE;
-}
-
-/**
- * @brief   Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- *          Trying to release a unallocated stream is an illegal operation
- *          and is trapped if assertions are enabled.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    The stream is again available.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamRelease");
-
-  /* Check if the streams is not taken.*/
-  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
-              "dmaStreamRelease(), #1", "not allocated");
-
-  /* Disables the associated IRQ vector.*/
-  nvicDisableVector(dmastp->vector);
-
-  /* Marks the stream as not allocated.*/
-  dma_streams_mask &= ~(1 << dmastp->selfindex);
-
-  /* Shutting down clocks that are no more required, if any.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
-    rccDisableDMA1(FALSE);
-#if STM32_HAS_DMA2
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
-    rccDisableDMA2(FALSE);
-#endif
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F30x/stm32_dma.h b/os/hal/platforms/STM32F30x/stm32_dma.h
deleted file mode 100644
index 2415f00f2..000000000
--- a/os/hal/platforms/STM32F30x/stm32_dma.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/stm32_dma.h
- * @brief   DMA helper driver header.
- * @note    This file requires definitions from the ST header file stm32f30x.h.
- * @note    This driver uses the new naming convention used for the STM32F2xx
- *          so the "DMA channels" are referred as "DMA streams".
- *
- * @addtogroup STM32F30x_DMA
- * @{
- */
-
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Total number of DMA streams.
- * @note    This is the total number of streams among all the DMA units.
- */
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
-#define STM32_DMA_STREAMS           12
-#else
-#define STM32_DMA_STREAMS           7
-#endif
-
-/**
- * @brief   Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK          0x0F
-
-/**
- * @brief   Returns the channel associated to the specified stream.
- *
- * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
- * @param[in] c         a stream/channel association word, one channel per
- *                      nibble, not associated channels must be set to 0xF
- * @return              Always zero, in this platform there is no dynamic
- *                      association between streams and channels.
- */
-#define STM32_DMA_GETCHANNEL(n, c)  0
-
-/**
- * @brief   Checks if a DMA priority is within the valid range.
- * @param[in] prio      DMA priority
- *
- * @retval              The check result.
- * @retval FALSE        invalid DMA priority.
- * @retval TRUE         correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
-
-/**
- * @brief   Returns an unique numeric identifier for a DMA stream.
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              An unique numeric stream identifier.
- */
-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
-
-/**
- * @brief   Returns a DMA stream identifier mask.
- *
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              A DMA stream identifier mask.
- */
-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
-  (1 << STM32_DMA_STREAM_ID(dma, stream))
-
-/**
- * @brief   Checks if a DMA stream unique identifier belongs to a mask.
- * @param[in] id        the stream numeric identifier
- * @param[in] mask      the stream numeric identifiers mask
- *
- * @retval              The check result.
- * @retval FALSE        id does not belong to the mask.
- * @retval TRUE         id belongs to the mask.
- */
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
-
-/**
- * @name    DMA streams identifiers
- * @{
- */
-/**
- * @brief   Returns a pointer to a stm32_dma_stream_t structure.
- *
- * @param[in] id        the stream numeric identifier
- * @return              A pointer to the stm32_dma_stream_t constant structure
- *                      associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
-#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
-#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
-#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(7)
-#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(8)
-#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(9)
-#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(10)
-#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(11)
-/** @} */
-
-/**
- * @name    CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN             DMA_CCR_EN
-#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE
-#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE
-#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE
-#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
-#define STM32_DMA_CR_DIR_P2M        0
-#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR
-#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM
-#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC
-#define STM32_DMA_CR_PINC           DMA_CCR_PINC
-#define STM32_DMA_CR_MINC           DMA_CCR_MINC
-#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE     0
-#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE     0
-#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
-                                     STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
-#define STM32_DMA_CR_PL(n)          ((n) << 12)
-/** @} */
-
-/**
- * @name    CR register constants only found in enhanced DMA
- * @{
- */
-#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
-/** @} */
-
-/**
- * @name    Status flags passed to the ISR callbacks
- * @{
- */
-#define STM32_DMA_ISR_FEIF          0
-#define STM32_DMA_ISR_DMEIF         0
-#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
-#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
-#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA stream descriptor structure.
- */
-typedef struct {
-  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
-  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
-  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
-                                             register.                      */
-  uint8_t               selfindex;      /**< @brief Index to self in array. */
-  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
-} stm32_dma_stream_t;
-
-/**
- * @brief   STM32 DMA ISR function type.
- *
- * @param[in] p         parameter for the registered function
- * @param[in] flags     pre-shifted content of the ISR register, the bits
- *                      are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Associates a peripheral data register to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CPAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) {                              \
-  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Associates a memory destination to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CMAR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) {                                 \
-  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Sets the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] size      value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) {                         \
-  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
-}
-
-/**
- * @brief   Returns the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @return              The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
-
-/**
- * @brief   Programs the stream mode settings.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) {                                    \
-  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
-}
-
-/**
- * @brief   DMA stream enable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) {                                           \
-  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
-}
-
-/**
- * @brief   DMA stream disable.
- * @details The function disables the specified stream and then clears any
- *          pending interrupt.
- * @note    This function can be invoked in both ISR or thread context.
- * @note    Interrupts enabling flags are set to zero after this call, see
- *          bug 3607518.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) {                                          \
-  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
-                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
-  dmaStreamClearInterrupt(dmastp);                                          \
-}
-
-/**
- * @brief   DMA stream interrupt sources clear.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) {                                   \
-  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
-}
-
-/**
- * @brief   Starts a memory to memory operation using the specified stream.
- * @note    The default transfer data mode is "byte to byte" but it can be
- *          changed by specifying extra options in the @p mode parameter.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register, this value
- *                      is implicitly ORed with:
- *                      - @p STM32_DMA_CR_MINC
- *                      - @p STM32_DMA_CR_PINC
- *                      - @p STM32_DMA_CR_DIR_M2M
- *                      - @p STM32_DMA_CR_EN
- *                      .
- * @param[in] src       source address
- * @param[in] dst       destination address
- * @param[in] n         number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
-  dmaStreamSetPeripheral(dmastp, src);                                      \
-  dmaStreamSetMemory0(dmastp, dst);                                         \
-  dmaStreamSetTransactionSize(dmastp, n);                                   \
-  dmaStreamSetMode(dmastp, (mode) |                                         \
-                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
-                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
-}
-
-/**
- * @brief   Polled wait for DMA transfer end.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) {                                         \
-  while ((dmastp)->channel->CNDTR > 0)                                      \
-    ;                                                                       \
-  dmaStreamDisable(dmastp);                                                 \
-}
-
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dmaInit(void);
-  bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                           uint32_t priority,
-                           stm32_dmaisr_t func,
-                           void *param);
-  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F30x/stm32_registry.h b/os/hal/platforms/STM32F30x/stm32_registry.h
deleted file mode 100644
index c655f0167..000000000
--- a/os/hal/platforms/STM32F30x/stm32_registry.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/stm32_registry.h
- * @brief   STM32F30x capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _STM32_REGISTRY_H_
-#define _STM32_REGISTRY_H_
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    STM32F30x capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_ADC1_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC2          TRUE
-#define STM32_ADC2_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 1) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC3          TRUE
-#define STM32_ADC3_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_ADC3_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC4          TRUE
-#define STM32_ADC4_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 2) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC4_DMA_CHN      0x00000000
-
-#define STM32_HAS_SDADC1        FALSE
-#define STM32_SDADC1_DMA_MSK    0
-#define STM32_SDADC1_DMA_CHN    0x00000000
-
-#define STM32_HAS_SDADC2        FALSE
-#define STM32_SDADC2_DMA_MSK    0
-#define STM32_SDADC2_DMA_CHN    0x00000000
-
-#define STM32_HAS_SDADC3        FALSE
-#define STM32_SDADC3_DMA_MSK    0
-#define STM32_SDADC3_DMA_CHN    0x00000000
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          TRUE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 34
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         TRUE
-#define STM32_HAS_GPIOF         TRUE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_I2C3_RX_DMA_MSK   0
-#define STM32_I2C3_RX_DMA_CHN   0x00000000
-#define STM32_I2C3_TX_DMA_MSK   0
-#define STM32_I2C3_TX_DMA_CHN   0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_IS_CALENDAR   TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          TRUE
-#define STM32_SPI3_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 1)
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 2)
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI4          FALSE
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          TRUE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          TRUE
-#define STM32_HAS_TIM8          TRUE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         FALSE
-#define STM32_HAS_TIM15         TRUE
-#define STM32_HAS_TIM16         TRUE
-#define STM32_HAS_TIM17         TRUE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         TRUE
-#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         TRUE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           TRUE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-
-#endif /* _STM32_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F30x/stm32f30x.h b/os/hal/platforms/STM32F30x/stm32f30x.h
deleted file mode 100644
index 99c6178ee..000000000
--- a/os/hal/platforms/STM32F30x/stm32f30x.h
+++ /dev/null
@@ -1,6213 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f30x.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    04-September-2012
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral registers definitions, bits 
-  *          definitions and memory mapping for STM32F30x devices.
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral�s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral�s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_STDPERIPH_DRIVER"
-  *              - To change few application-specific parameters such as the HSE 
-  *                crystal frequency
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral registers declarations and bits definition
-  *           - Macros to access peripheral registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f30x
-  * @{
-  */
-    
-#ifndef __STM32F30x_H
-#define __STM32F30x_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32F30X) 
-  #define STM32F30X
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-
-#if !defined (STM32F30X)
- #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)"
-#endif
-
-#if !defined  (USE_STDPERIPH_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_STDPERIPH_DRIVER*/
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application 
-   
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */           
-#if !defined  (HSE_VALUE) 
- #define HSE_VALUE            ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-   Timeout value 
-   */
-#if !defined  (HSE_STARTUP_TIMEOUT) 
- #define HSE_STARTUP_TIMEOUT  ((uint16_t)0x0500)   /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-   Timeout value 
-   */
-#if !defined  (HSI_STARTUP_TIMEOUT) 
- #define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */  
-
-#if !defined  (HSI_VALUE) 
- #define HSI_VALUE  ((uint32_t)8000000)
-#endif /* HSI_VALUE */                      /*!< Value of the Internal High Speed oscillator in Hz.
-                                            The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */     
-
-
-/**
- * @brief STM32F30x Standard Peripherals Library version number V1.0.0
-   */
-#define __STM32F30X_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
-#define __STM32F30X_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32F30X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F30X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F30X_STDPERIPH_VERSION       ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\
-                                             |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\
-                                             |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\
-                                             |(__STM32F30X_STDPERIPH_VERSION_RC))
-                                             
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
- */
-#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1         /*!< STM32F30X provide an MPU */
-#define __NVIC_PRIO_BITS          4         /*!< STM32F30X uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT             1         /*!< STM32F30X provide an FPU */
-
-
-/**
- * @brief STM32F30X Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum IRQn
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts                                   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the  lines 17, 19 & 20           */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_TS_IRQn               = 8,      /*!< EXTI Line2 Interrupt and Touch Sense Interrupt                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
-  ADC1_2_IRQn                 = 18,     /*!< ADC1 & ADC2 Interrupts                                            */
-  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts                    */
-  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts                    */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                                   */
-  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                                  */
-  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt                  */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  USBWakeUp_IRQn              = 42,     /*!< USB Wakeup Interrupt                                              */    
-  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
-  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
-  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                             */
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
-  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
-  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
-  ADC4_IRQn                   = 61,     /*!< ADC4  global Interrupt                                            */
-  COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 global Interrupt                           */
-  COMP4_5_6_IRQn              = 65,     /*!< COMP5, COMP6 and COMP4 global Interrupt                           */
-  COMP7_IRQn                  = 66,     /*!< COMP7 global Interrupt                                            */
-  USB_HP_IRQn                 = 74,     /*!< USB High Priority global Interrupt remap                          */
-  USB_LP_IRQn                 = 75,     /*!< USB Low Priority global Interrupt  remap                          */
-  USBWakeUp_RMP_IRQn          = 76,     /*!< USB Wakeup Interrupt remap                                        */
-  FPU_IRQn                    = 81      /*!< Floating point Interrupt                                          */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"            /* Cortex-M4 processor and core peripherals */
-/* CHIBIOS FIX */
-/*#include "system_stm32f30x.h"*/    /* STM32F30x System Header */
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t  s32;
-typedef int16_t s16;
-typedef int8_t  s8;
-
-typedef const int32_t sc32;  /*!< Read Only */
-typedef const int16_t sc16;  /*!< Read Only */
-typedef const int8_t sc8;   /*!< Read Only */
-
-typedef __IO int32_t  vs32;
-typedef __IO int16_t  vs16;
-typedef __IO int8_t   vs8;
-
-typedef __I int32_t vsc32;  /*!< Read Only */
-typedef __I int16_t vsc16;  /*!< Read Only */
-typedef __I int8_t vsc8;   /*!< Read Only */
-
-typedef uint32_t  u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-typedef const uint32_t uc32;  /*!< Read Only */
-typedef const uint16_t uc16;  /*!< Read Only */
-typedef const uint8_t uc8;   /*!< Read Only */
-
-typedef __IO uint32_t  vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t  vu8;
-
-typedef __I uint32_t vuc32;  /*!< Read Only */
-typedef __I uint16_t vuc16;  /*!< Read Only */
-typedef __I uint8_t vuc8;   /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                 Address offset: 0x00 */
-  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                     Address offset: 0x04 */      
-  __IO uint32_t CR;               /*!< ADC control register,                              Address offset: 0x08 */
-  __IO uint32_t CFGR;             /*!< ADC Configuration register,                        Address offset: 0x0C */
-  uint32_t      RESERVED0;        /*!< Reserved, 0x010                                                         */
-  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                        Address offset: 0x14 */
-  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                        Address offset: 0x18 */
-  uint32_t      RESERVED1;        /*!< Reserved, 0x01C                                                         */
-  __IO uint32_t TR1;              /*!< ADC watchdog threshold register 1,                 Address offset: 0x20 */
-  __IO uint32_t TR2;              /*!< ADC watchdog threshold register 2,                 Address offset: 0x24 */
-  __IO uint32_t TR3;              /*!< ADC watchdog threshold register 3,                 Address offset: 0x28 */
-  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                         */
-  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                   Address offset: 0x30 */
-  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                   Address offset: 0x34 */
-  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                   Address offset: 0x38 */
-  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                   Address offset: 0x3C */
-  __IO uint32_t DR;               /*!< ADC regular data register,                         Address offset: 0x40 */
-  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                         */
-  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                         */
-  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                    Address offset: 0x4C */
-  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                 */
-  __IO uint32_t OFR1;             /*!< ADC offset register 1,                             Address offset: 0x60 */
-  __IO uint32_t OFR2;             /*!< ADC offset register 2,                             Address offset: 0x64 */
-  __IO uint32_t OFR3;             /*!< ADC offset register 3,                             Address offset: 0x68 */
-  __IO uint32_t OFR4;             /*!< ADC offset register 4,                             Address offset: 0x6C */
-  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                 */
-  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                      Address offset: 0x80 */
-  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                      Address offset: 0x84 */
-  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                      Address offset: 0x88 */
-  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                      Address offset: 0x8C */
-  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                 */  
-  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,     Address offset: 0xA0 */
-  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,     Address offset: 0xA4 */
-  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                         */
-  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                         */  
-  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,         Address offset: 0xB0 */
-  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                          Address offset: 0xB4 */
-  
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;            /*!< ADC Common status register,                  Address offset: ADC1/3 base address + 0x300 */
-  uint32_t      RESERVED;       /*!< Reserved, ADC1/3 base address + 0x304                                                    */
-  __IO uint32_t CCR;            /*!< ADC common control register,                 Address offset: ADC1/3 base address + 0x308 */
-  __IO uint32_t CDR;            /*!< ADC common regular data register for dual
-                                     AND triple modes,                            Address offset: ADC1/3 base address + 0x30C */
-} ADC_Common_TypeDef;
-  
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-  
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-
-/** 
-  * @brief Analog Comparators 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< Comparator control Status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
-  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;    /*!< DMA interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t IFCR;   /*!< DMA interrupt clear flag register,  Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;        /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
-  __IO uint32_t EMR;        /*!< EXTI Event mask register,                    Address offset: 0x04 */
-  __IO uint32_t RTSR;       /*!< EXTI Rising trigger selection register,      Address offset: 0x08 */
-  __IO uint32_t FTSR;       /*!< EXTI Falling trigger selection register,     Address offset: 0x0C */
-  __IO uint32_t SWIER;      /*!< EXTI Software interrupt event register,      Address offset: 0x10 */
-  __IO uint32_t PR;         /*!< EXTI Pending register,                       Address offset: 0x14 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x18                                                    */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x1C                                                    */
-  __IO uint32_t IMR2;       /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
-  __IO uint32_t EMR2;       /*!< EXTI Event mask register,                    Address offset: 0x24 */
-  __IO uint32_t RTSR2;      /*!< EXTI Rising trigger selection register,      Address offset: 0x28 */
-  __IO uint32_t FTSR2;      /*!< EXTI Falling trigger selection register,     Address offset: 0x2C */
-  __IO uint32_t SWIER2;     /*!< EXTI Software interrupt event register,      Address offset: 0x30 */
-  __IO uint32_t PR2;        /*!< EXTI Pending register,                       Address offset: 0x34 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< FLASH access control register,              Address offset: 0x00 */
-  __IO uint32_t KEYR;         /*!< FLASH key register,                         Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;      /*!< FLASH option key register,                  Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< FLASH status register,                      Address offset: 0x0C */
-  __IO uint32_t CR;           /*!< FLASH control register,                     Address offset: 0x10 */
-  __IO uint32_t AR;           /*!< FLASH address register,                     Address offset: 0x14 */
-  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                   */
-  __IO uint32_t OBR;          /*!< FLASH Option byte register,                 Address offset: 0x1C */
-  __IO uint32_t WRPR;         /*!< FLASH Write register,                       Address offset: 0x20 */
-  
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
-  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
-  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
-  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
-  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
-  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
-  __IO uint16_t WRP2;         /*!<FLASH option byte write protection 2,          Address offset: 0x10 */
-  __IO uint16_t WRP3;         /*!<FLASH option byte write protection 3,          Address offset: 0x12 */
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-/* CHIBIOS FIX */
-#if 0
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
-  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
-  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
-  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
-  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
-  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
-  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
-  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
-  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
-}GPIO_TypeDef;
-#endif
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-  
-typedef struct
-{
-  __IO uint32_t CSR;        /*!< OPAMP control and status register,            Address offset: 0x00 */
-} OPAMP_TypeDef;
-
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t CFGR1;      /*!< SYSCFG configuration register 1,                   Address offset: 0x00 */
-  __IO uint32_t RCR;        /*!< SYSCFG CCM SRAM protection register,               Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];  /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
-  __IO uint32_t CFGR2;     /*!< SYSCFG configuration register 2,                    Address offset: 0x18 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  
-}I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */ 
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
-  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
-  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
-  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
-  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
-  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
-  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
-  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
-  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
-  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */ 
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-  
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  uint32_t RESERVED0;       /*!< Reserved, 0x18                                                                 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                   Address offset: 0x8C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-  
-typedef struct
-{
-  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
-  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
-  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
-  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
-  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
-  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
-  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
-  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
-  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
- __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
-  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
-  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,      Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare register 4,      Address offset: 0x5C */
-} TIM_TypeDef;
-
-
-/** 
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-  
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
-  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
-  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
-  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
-} USART_TypeDef; 
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
-#define AHB3PERIPH_BASE       (PERIPH_BASE + 0x10000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x00003400)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x00004000)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000)
-#define COMP_BASE             (APB2PERIPH_BASE + 0x0000001C)
-#define COMP1_BASE            (APB2PERIPH_BASE + 0x0000001C)
-#define COMP2_BASE            (APB2PERIPH_BASE + 0x00000020)
-#define COMP3_BASE            (APB2PERIPH_BASE + 0x00000024)
-#define COMP4_BASE            (APB2PERIPH_BASE + 0x00000028)
-#define COMP5_BASE            (APB2PERIPH_BASE + 0x0000002C)
-#define COMP6_BASE            (APB2PERIPH_BASE + 0x00000030)
-#define COMP7_BASE            (APB2PERIPH_BASE + 0x00000034)
-#define OPAMP_BASE            (APB2PERIPH_BASE + 0x00000038)
-#define OPAMP1_BASE           (APB2PERIPH_BASE + 0x00000038)
-#define OPAMP2_BASE           (APB2PERIPH_BASE + 0x0000003C)
-#define OPAMP3_BASE           (APB2PERIPH_BASE + 0x00000040)
-#define OPAMP4_BASE           (APB2PERIPH_BASE + 0x00000044)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400)
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x00003400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800)
-#define TIM15_BASE            (APB2PERIPH_BASE + 0x00004000)
-#define TIM16_BASE            (APB2PERIPH_BASE + 0x00004400)
-#define TIM17_BASE            (APB2PERIPH_BASE + 0x00004800)
-
-/*!< AHB1 peripherals */
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x00000000)
-#define DMA1_Channel1_BASE    (AHB1PERIPH_BASE + 0x00000008)
-#define DMA1_Channel2_BASE    (AHB1PERIPH_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE    (AHB1PERIPH_BASE + 0x00000030)
-#define DMA1_Channel4_BASE    (AHB1PERIPH_BASE + 0x00000044)
-#define DMA1_Channel5_BASE    (AHB1PERIPH_BASE + 0x00000058)
-#define DMA1_Channel6_BASE    (AHB1PERIPH_BASE + 0x0000006C)
-#define DMA1_Channel7_BASE    (AHB1PERIPH_BASE + 0x00000080)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x00000400)
-#define DMA2_Channel1_BASE    (AHB1PERIPH_BASE + 0x00000408)
-#define DMA2_Channel2_BASE    (AHB1PERIPH_BASE + 0x0000041C)
-#define DMA2_Channel3_BASE    (AHB1PERIPH_BASE + 0x00000430)
-#define DMA2_Channel4_BASE    (AHB1PERIPH_BASE + 0x00000444)
-#define DMA2_Channel5_BASE    (AHB1PERIPH_BASE + 0x00000458)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x00001000)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
-#define OB_BASE               ((uint32_t)0x1FFFF800)     /*!< Flash Option Bytes base address */
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x00003000)
-#define TSC_BASE              (AHB1PERIPH_BASE + 0x00004000)
-
-/*!< AHB2 peripherals */
-#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400)
-
-/*!< AHB3 peripherals */
-#define ADC1_BASE             (AHB3PERIPH_BASE + 0x0000)
-#define ADC2_BASE             (AHB3PERIPH_BASE + 0x0100)
-#define ADC1_2_BASE           (AHB3PERIPH_BASE + 0x0300)
-#define ADC3_BASE             (AHB3PERIPH_BASE + 0x0400)
-#define ADC4_BASE             (AHB3PERIPH_BASE + 0x0500)
-#define ADC3_4_BASE           (AHB3PERIPH_BASE + 0x0700)
-
-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP                ((COMP_TypeDef *) COMP_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define COMP3               ((COMP_TypeDef *) COMP3_BASE)
-#define COMP4               ((COMP_TypeDef *) COMP4_BASE)
-#define COMP5               ((COMP_TypeDef *) COMP5_BASE)
-#define COMP6               ((COMP_TypeDef *) COMP6_BASE)
-#define COMP7               ((COMP_TypeDef *) COMP7_BASE)
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
-#define OPAMP3              ((OPAMP_TypeDef *) OPAMP3_BASE)
-#define OPAMP4              ((OPAMP_TypeDef *) OPAMP4_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define ADC4                ((ADC_TypeDef *) ADC4_BASE)
-#define ADC1_2              ((ADC_Common_TypeDef *) ADC1_2_BASE)
-#define ADC3_4              ((ADC_Common_TypeDef *) ADC3_4_BASE)
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter SAR (ADC)               */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_ISR register  ********************/
-/* CHIBIOS FIX */
-//#define ADC_ISR_ADRD         ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag  */
-#define ADC_ISR_ADRDY         ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag  */
-#define ADC_ISR_EOSMP         ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
-#define ADC_ISR_EOC           ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
-#define ADC_ISR_EOS           ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_ISR_OVR           ((uint32_t)0x00000010) /*!< ADC overrun flag */
-#define ADC_ISR_JEOC          ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
-#define ADC_ISR_JEOS          ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_ISR_AWD1          ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
-#define ADC_ISR_AWD2          ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
-#define ADC_ISR_AWD3          ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
-#define ADC_ISR_JQOVF         ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
-
-/********************  Bit definition for ADC_IER register  ********************/
-#define ADC_IER_RDY           ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IER_EOSMP         ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
-#define ADC_IER_EOC           ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IER_EOS           ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
-#define ADC_IER_OVR           ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
-#define ADC_IER_JEOC          ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IER_JEOS          ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
-#define ADC_IER_AWD1          ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
-#define ADC_IER_AWD2          ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
-#define ADC_IER_AWD3          ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
-#define ADC_IER_JQOVF         ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
-
-/********************  Bit definition for ADC_CR register  ********************/
-#define ADC_CR_ADEN          ((uint32_t)0x00000001) /*!< ADC Enable control */
-#define ADC_CR_ADDIS         ((uint32_t)0x00000002) /*!< ADC Disable command */
-#define ADC_CR_ADSTART       ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
-#define ADC_CR_JADSTART      ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
-#define ADC_CR_ADSTP         ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
-#define ADC_CR_JADSTP        ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
-#define ADC_CR_ADVREGEN      ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
-#define ADC_CR_ADVREGEN_0    ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
-#define ADC_CR_ADVREGEN_1    ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
-#define ADC_CR_ADCALDIF      ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
-#define ADC_CR_ADCAL         ((uint32_t)0x80000000) /*!< ADC Calibration */
-
-/********************  Bit definition for ADC_CFGR register  ********************/
-#define ADC_CFGR_DMAEN     ((uint32_t)0x00000001) /*!< ADC DMA Enable */
-#define ADC_CFGR_DMACFG    ((uint32_t)0x00000002) /*!< ADC DMA configuration */
-
-#define ADC_CFGR_RES       ((uint32_t)0x00000018) /*!< ADC Data resolution */
-#define ADC_CFGR_RES_0     ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
-#define ADC_CFGR_RES_1     ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
-
-#define ADC_CFGR_ALIGN     ((uint32_t)0x00000020) /*!< ADC Data Alignement */
-
-#define ADC_CFGR_EXTSEL   ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
-#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
-#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
-#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
-#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
-
-#define ADC_CFGR_EXTEN     ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
-#define ADC_CFGR_EXTEN_0   ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
-#define ADC_CFGR_EXTEN_1   ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
-
-#define ADC_CFGR_OVRMOD    ((uint32_t)0x00001000) /*!< ADC overrun mode */
-#define ADC_CFGR_CONT      ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
-#define ADC_CFGR_AUTDLY   ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
-#define ADC_CFGR_AUTOFF    ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
-#define ADC_CFGR_DISCEN    ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
-
-#define ADC_CFGR_DISCNUM   ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
-#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
-#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
-#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
-
-#define ADC_CFGR_JDISCEN   ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
-#define ADC_CFGR_JQM       ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
-#define ADC_CFGR_AWD1SGL   ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
-#define ADC_CFGR_AWD1EN    ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
-#define ADC_CFGR_JAWD1EN   ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
-#define ADC_CFGR_JAUTO     ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
-
-#define ADC_CFGR_AWD1CH    ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
-#define ADC_CFGR_AWD1CH_0  ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
-#define ADC_CFGR_AWD1CH_1  ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1  */
-#define ADC_CFGR_AWD1CH_2  ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2  */
-#define ADC_CFGR_AWD1CH_3  ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3  */
-#define ADC_CFGR_AWD1CH_4  ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4  */
-
-/********************  Bit definition for ADC_SMPR1 register  ********************/
-#define ADC_SMPR1_SMP0     ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection  */
-#define ADC_SMPR1_SMP0_0   ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
-#define ADC_SMPR1_SMP0_1   ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
-#define ADC_SMPR1_SMP0_2   ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
-
-#define ADC_SMPR1_SMP1     ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection  */
-#define ADC_SMPR1_SMP1_0   ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
-#define ADC_SMPR1_SMP1_1   ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
-#define ADC_SMPR1_SMP1_2   ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
-
-#define ADC_SMPR1_SMP2     ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection  */
-#define ADC_SMPR1_SMP2_0   ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
-#define ADC_SMPR1_SMP2_1   ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
-#define ADC_SMPR1_SMP2_2   ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
-
-#define ADC_SMPR1_SMP3     ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection  */
-#define ADC_SMPR1_SMP3_0   ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
-#define ADC_SMPR1_SMP3_1   ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
-#define ADC_SMPR1_SMP3_2   ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
-
-#define ADC_SMPR1_SMP4     ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection  */
-#define ADC_SMPR1_SMP4_0   ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
-#define ADC_SMPR1_SMP4_1   ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
-#define ADC_SMPR1_SMP4_2   ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
-
-#define ADC_SMPR1_SMP5     ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection  */
-#define ADC_SMPR1_SMP5_0   ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
-#define ADC_SMPR1_SMP5_1   ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
-#define ADC_SMPR1_SMP5_2   ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
-
-#define ADC_SMPR1_SMP6     ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection  */
-#define ADC_SMPR1_SMP6_0   ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
-#define ADC_SMPR1_SMP6_1   ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
-#define ADC_SMPR1_SMP6_2   ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
-
-#define ADC_SMPR1_SMP7     ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection  */
-#define ADC_SMPR1_SMP7_0   ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
-#define ADC_SMPR1_SMP7_1   ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
-#define ADC_SMPR1_SMP7_2   ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
-
-#define ADC_SMPR1_SMP8     ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection  */
-#define ADC_SMPR1_SMP8_0   ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
-#define ADC_SMPR1_SMP8_1   ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
-#define ADC_SMPR1_SMP8_2   ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
-
-#define ADC_SMPR1_SMP9     ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection  */
-#define ADC_SMPR1_SMP9_0   ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
-#define ADC_SMPR1_SMP9_1   ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
-#define ADC_SMPR1_SMP9_2   ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
-
-/********************  Bit definition for ADC_SMPR2 register  ********************/
-#define ADC_SMPR2_SMP10     ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection  */
-#define ADC_SMPR2_SMP10_0   ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
-#define ADC_SMPR2_SMP10_1   ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
-#define ADC_SMPR2_SMP10_2   ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
-
-#define ADC_SMPR2_SMP11     ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection  */
-#define ADC_SMPR2_SMP11_0   ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
-#define ADC_SMPR2_SMP11_1   ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
-#define ADC_SMPR2_SMP11_2   ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
-
-#define ADC_SMPR2_SMP12     ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection  */
-#define ADC_SMPR2_SMP12_0   ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
-#define ADC_SMPR2_SMP12_1   ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
-#define ADC_SMPR2_SMP12_2   ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
-
-#define ADC_SMPR2_SMP13     ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection  */
-#define ADC_SMPR2_SMP13_0   ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
-#define ADC_SMPR2_SMP13_1   ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
-#define ADC_SMPR2_SMP13_2   ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
-
-#define ADC_SMPR2_SMP14     ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection  */
-#define ADC_SMPR2_SMP14_0   ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
-#define ADC_SMPR2_SMP14_1   ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
-#define ADC_SMPR2_SMP14_2   ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
-
-#define ADC_SMPR2_SMP15     ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection  */
-#define ADC_SMPR2_SMP15_0   ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
-#define ADC_SMPR2_SMP15_1   ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
-#define ADC_SMPR2_SMP15_2   ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
-
-#define ADC_SMPR2_SMP16     ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection  */
-#define ADC_SMPR2_SMP16_0   ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
-#define ADC_SMPR2_SMP16_1   ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
-#define ADC_SMPR2_SMP16_2   ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
-
-#define ADC_SMPR2_SMP17     ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection  */
-#define ADC_SMPR2_SMP17_0   ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
-#define ADC_SMPR2_SMP17_1   ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
-#define ADC_SMPR2_SMP17_2   ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
-
-#define ADC_SMPR2_SMP18     ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection  */
-#define ADC_SMPR2_SMP18_0   ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
-#define ADC_SMPR2_SMP18_1   ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
-#define ADC_SMPR2_SMP18_2   ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
-
-/********************  Bit definition for ADC_TR1 register  ********************/
-#define ADC_TR1_LT1         ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
-#define ADC_TR1_LT1_0       ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
-#define ADC_TR1_LT1_1       ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
-#define ADC_TR1_LT1_2       ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
-#define ADC_TR1_LT1_3       ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
-#define ADC_TR1_LT1_4       ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
-#define ADC_TR1_LT1_5       ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
-#define ADC_TR1_LT1_6       ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
-#define ADC_TR1_LT1_7       ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
-#define ADC_TR1_LT1_8       ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
-#define ADC_TR1_LT1_9       ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
-#define ADC_TR1_LT1_10      ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
-#define ADC_TR1_LT1_11      ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
-
-#define ADC_TR1_HT1         ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
-#define ADC_TR1_HT1_0       ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
-#define ADC_TR1_HT1_1       ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
-#define ADC_TR1_HT1_2       ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
-#define ADC_TR1_HT1_3       ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
-#define ADC_TR1_HT1_4       ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
-#define ADC_TR1_HT1_5       ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
-#define ADC_TR1_HT1_6       ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
-#define ADC_TR1_HT1_7       ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
-#define ADC_TR1_HT1_8       ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
-#define ADC_TR1_HT1_9       ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
-#define ADC_TR1_HT1_10      ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
-#define ADC_TR1_HT1_11      ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
-
-/********************  Bit definition for ADC_TR2 register  ********************/
-#define ADC_TR2_LT2         ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
-#define ADC_TR2_LT2_0       ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
-#define ADC_TR2_LT2_1       ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
-#define ADC_TR2_LT2_2       ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
-#define ADC_TR2_LT2_3       ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
-#define ADC_TR2_LT2_4       ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
-#define ADC_TR2_LT2_5       ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
-#define ADC_TR2_LT2_6       ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
-#define ADC_TR2_LT2_7       ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
-
-#define ADC_TR2_HT2         ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
-#define ADC_TR2_HT2_0       ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
-#define ADC_TR2_HT2_1       ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
-#define ADC_TR2_HT2_2       ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
-#define ADC_TR2_HT2_3       ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
-#define ADC_TR2_HT2_4       ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
-#define ADC_TR2_HT2_5       ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
-#define ADC_TR2_HT2_6       ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
-#define ADC_TR2_HT2_7       ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
-
-/********************  Bit definition for ADC_TR3 register  ********************/
-#define ADC_TR3_LT3         ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
-#define ADC_TR3_LT3_0       ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
-#define ADC_TR3_LT3_1       ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
-#define ADC_TR3_LT3_2       ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
-#define ADC_TR3_LT3_3       ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
-#define ADC_TR3_LT3_4       ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
-#define ADC_TR3_LT3_5       ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
-#define ADC_TR3_LT3_6       ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
-#define ADC_TR3_LT3_7       ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
-
-#define ADC_TR3_HT3         ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
-#define ADC_TR3_HT3_0       ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
-#define ADC_TR3_HT3_1       ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
-#define ADC_TR3_HT3_2       ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
-#define ADC_TR3_HT3_3       ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
-#define ADC_TR3_HT3_4       ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
-#define ADC_TR3_HT3_5       ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
-#define ADC_TR3_HT3_6       ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
-#define ADC_TR3_HT3_7       ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
-
-/********************  Bit definition for ADC_SQR1 register  ********************/
-#define ADC_SQR1_L          ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
-#define ADC_SQR1_L_0        ((uint32_t)0x00000001) /*!< ADC L bit 0 */
-#define ADC_SQR1_L_1        ((uint32_t)0x00000002) /*!< ADC L bit 1 */
-#define ADC_SQR1_L_2        ((uint32_t)0x00000004) /*!< ADC L bit 2 */
-#define ADC_SQR1_L_3        ((uint32_t)0x00000008) /*!< ADC L bit 3 */
-
-#define ADC_SQR1_SQ1        ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
-#define ADC_SQR1_SQ1_0      ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
-#define ADC_SQR1_SQ1_1      ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
-#define ADC_SQR1_SQ1_2      ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
-#define ADC_SQR1_SQ1_3      ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
-#define ADC_SQR1_SQ1_4      ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
-
-#define ADC_SQR1_SQ2        ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
-#define ADC_SQR1_SQ2_0      ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
-#define ADC_SQR1_SQ2_1      ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
-#define ADC_SQR1_SQ2_2      ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
-#define ADC_SQR1_SQ2_3      ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
-#define ADC_SQR1_SQ2_4      ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
-
-#define ADC_SQR1_SQ3        ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
-#define ADC_SQR1_SQ3_0      ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
-#define ADC_SQR1_SQ3_1      ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
-#define ADC_SQR1_SQ3_2      ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
-#define ADC_SQR1_SQ3_3      ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
-#define ADC_SQR1_SQ3_4      ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
-
-#define ADC_SQR1_SQ4        ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
-#define ADC_SQR1_SQ4_0      ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
-#define ADC_SQR1_SQ4_1      ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
-#define ADC_SQR1_SQ4_2      ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
-#define ADC_SQR1_SQ4_3      ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
-#define ADC_SQR1_SQ4_4      ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
-
-/********************  Bit definition for ADC_SQR2 register  ********************/
-#define ADC_SQR2_SQ5        ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
-#define ADC_SQR2_SQ5_0      ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
-#define ADC_SQR2_SQ5_1      ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
-#define ADC_SQR2_SQ5_2      ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
-#define ADC_SQR2_SQ5_3      ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
-#define ADC_SQR2_SQ5_4      ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
-
-#define ADC_SQR2_SQ6        ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
-#define ADC_SQR2_SQ6_0      ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
-#define ADC_SQR2_SQ6_1      ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
-#define ADC_SQR2_SQ6_2      ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
-#define ADC_SQR2_SQ6_3      ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
-#define ADC_SQR2_SQ6_4      ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
-
-#define ADC_SQR2_SQ7        ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
-#define ADC_SQR2_SQ7_0      ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
-#define ADC_SQR2_SQ7_1      ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
-#define ADC_SQR2_SQ7_2      ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
-#define ADC_SQR2_SQ7_3      ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
-#define ADC_SQR2_SQ7_4      ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
-
-#define ADC_SQR2_SQ8        ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
-#define ADC_SQR2_SQ8_0      ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
-#define ADC_SQR2_SQ8_1      ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
-#define ADC_SQR2_SQ8_2      ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
-#define ADC_SQR2_SQ8_3      ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
-#define ADC_SQR2_SQ8_4      ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
-
-#define ADC_SQR2_SQ9        ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
-#define ADC_SQR2_SQ9_0      ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
-#define ADC_SQR2_SQ9_1      ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
-#define ADC_SQR2_SQ9_2      ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
-#define ADC_SQR2_SQ9_3      ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
-#define ADC_SQR2_SQ9_4      ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
-
-/********************  Bit definition for ADC_SQR3 register  ********************/
-#define ADC_SQR3_SQ10       ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
-#define ADC_SQR3_SQ10_0     ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
-#define ADC_SQR3_SQ10_1     ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
-#define ADC_SQR3_SQ10_2     ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
-#define ADC_SQR3_SQ10_3     ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
-#define ADC_SQR3_SQ10_4     ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
-
-#define ADC_SQR3_SQ11       ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
-#define ADC_SQR3_SQ11_0     ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
-#define ADC_SQR3_SQ11_1     ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
-#define ADC_SQR3_SQ11_2     ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
-#define ADC_SQR3_SQ11_3     ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
-#define ADC_SQR3_SQ11_4     ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
-
-#define ADC_SQR3_SQ12       ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
-#define ADC_SQR3_SQ12_0     ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
-#define ADC_SQR3_SQ12_1     ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
-#define ADC_SQR3_SQ12_2     ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
-#define ADC_SQR3_SQ12_3     ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
-#define ADC_SQR3_SQ12_4     ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
-
-#define ADC_SQR3_SQ13       ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
-#define ADC_SQR3_SQ13_0     ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
-#define ADC_SQR3_SQ13_1     ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
-#define ADC_SQR3_SQ13_2     ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
-#define ADC_SQR3_SQ13_3     ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
-#define ADC_SQR3_SQ13_4     ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
-
-#define ADC_SQR3_SQ14       ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
-#define ADC_SQR3_SQ14_0     ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
-#define ADC_SQR3_SQ14_1     ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
-#define ADC_SQR3_SQ14_2     ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
-#define ADC_SQR3_SQ14_3     ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
-#define ADC_SQR3_SQ14_4     ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
-
-/********************  Bit definition for ADC_SQR4 register  ********************/
-#define ADC_SQR3_SQ15       ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
-#define ADC_SQR3_SQ15_0     ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
-#define ADC_SQR3_SQ15_1     ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
-#define ADC_SQR3_SQ15_2     ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
-#define ADC_SQR3_SQ15_3     ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
-#define ADC_SQR3_SQ15_4     ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
-
-#define ADC_SQR3_SQ16       ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
-#define ADC_SQR3_SQ16_0     ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
-#define ADC_SQR3_SQ16_1     ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
-#define ADC_SQR3_SQ16_2     ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
-#define ADC_SQR3_SQ16_3     ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
-#define ADC_SQR3_SQ16_4     ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_RDATA        ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
-#define ADC_DR_RDATA_0      ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
-#define ADC_DR_RDATA_1      ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
-#define ADC_DR_RDATA_2      ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
-#define ADC_DR_RDATA_3      ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
-#define ADC_DR_RDATA_4      ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
-#define ADC_DR_RDATA_5      ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
-#define ADC_DR_RDATA_6      ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
-#define ADC_DR_RDATA_7      ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
-#define ADC_DR_RDATA_8      ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
-#define ADC_DR_RDATA_9      ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
-#define ADC_DR_RDATA_10     ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
-#define ADC_DR_RDATA_11     ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
-#define ADC_DR_RDATA_12     ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
-#define ADC_DR_RDATA_13     ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
-#define ADC_DR_RDATA_14     ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
-#define ADC_DR_RDATA_15     ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
-
-/********************  Bit definition for ADC_JSQR register  ********************/
-#define ADC_JSQR_JL         ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
-#define ADC_JSQR_JL_0       ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
-#define ADC_JSQR_JL_1       ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
-
-#define ADC_JSQR_JEXTSEL    ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
-#define ADC_JSQR_JEXTSEL_0  ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
-#define ADC_JSQR_JEXTSEL_1  ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
-#define ADC_JSQR_JEXTSEL_2  ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
-#define ADC_JSQR_JEXTSEL_3  ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
-
-#define ADC_JSQR_JEXTEN     ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
-#define ADC_JSQR_JEXTEN_0   ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
-#define ADC_JSQR_JEXTEN_1   ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
-
-#define ADC_JSQR_JSQ1       ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
-#define ADC_JSQR_JSQ1_0     ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
-#define ADC_JSQR_JSQ1_1     ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
-#define ADC_JSQR_JSQ1_2     ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
-#define ADC_JSQR_JSQ1_3     ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
-#define ADC_JSQR_JSQ1_4     ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
-
-#define ADC_JSQR_JSQ2       ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
-#define ADC_JSQR_JSQ2_0     ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
-#define ADC_JSQR_JSQ2_1     ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
-#define ADC_JSQR_JSQ2_2     ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
-#define ADC_JSQR_JSQ2_3     ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
-#define ADC_JSQR_JSQ2_4     ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
-
-#define ADC_JSQR_JSQ3       ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
-#define ADC_JSQR_JSQ3_0     ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
-#define ADC_JSQR_JSQ3_1     ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
-#define ADC_JSQR_JSQ3_2     ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
-#define ADC_JSQR_JSQ3_3     ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
-#define ADC_JSQR_JSQ3_4     ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
-
-#define ADC_JSQR_JSQ4       ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
-#define ADC_JSQR_JSQ4_0     ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
-#define ADC_JSQR_JSQ4_1     ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
-#define ADC_JSQR_JSQ4_2     ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
-#define ADC_JSQR_JSQ4_3     ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
-#define ADC_JSQR_JSQ4_4     ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
-
-/********************  Bit definition for ADC_OFR1 register  ********************/
-#define ADC_OFR1_OFFSET1    ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
-#define ADC_OFR1_OFFSET1_0  ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
-#define ADC_OFR1_OFFSET1_1  ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
-#define ADC_OFR1_OFFSET1_2  ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
-#define ADC_OFR1_OFFSET1_3  ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
-#define ADC_OFR1_OFFSET1_4  ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
-#define ADC_OFR1_OFFSET1_5  ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
-#define ADC_OFR1_OFFSET1_6  ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
-#define ADC_OFR1_OFFSET1_7  ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
-#define ADC_OFR1_OFFSET1_8  ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
-#define ADC_OFR1_OFFSET1_9  ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
-#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
-#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
-
-#define ADC_OFR1_OFFSET1_CH     ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
-#define ADC_OFR1_OFFSET1_CH_0  ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
-#define ADC_OFR1_OFFSET1_CH_1  ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
-#define ADC_OFR1_OFFSET1_CH_2  ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
-#define ADC_OFR1_OFFSET1_CH_3  ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
-#define ADC_OFR1_OFFSET1_CH_4  ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
-
-#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
-
-/********************  Bit definition for ADC_OFR2 register  ********************/
-#define ADC_OFR2_OFFSET2    ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
-#define ADC_OFR2_OFFSET2_0  ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
-#define ADC_OFR2_OFFSET2_1  ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
-#define ADC_OFR2_OFFSET2_2  ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
-#define ADC_OFR2_OFFSET2_3  ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
-#define ADC_OFR2_OFFSET2_4  ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
-#define ADC_OFR2_OFFSET2_5  ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
-#define ADC_OFR2_OFFSET2_6  ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
-#define ADC_OFR2_OFFSET2_7  ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
-#define ADC_OFR2_OFFSET2_8  ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
-#define ADC_OFR2_OFFSET2_9  ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
-#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
-#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
-
-#define ADC_OFR2_OFFSET2_CH     ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
-#define ADC_OFR2_OFFSET2_CH_0  ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
-#define ADC_OFR2_OFFSET2_CH_1  ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
-#define ADC_OFR2_OFFSET2_CH_2  ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
-#define ADC_OFR2_OFFSET2_CH_3  ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
-#define ADC_OFR2_OFFSET2_CH_4  ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
-
-#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
-
-/********************  Bit definition for ADC_OFR3 register  ********************/
-#define ADC_OFR3_OFFSET3    ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
-#define ADC_OFR3_OFFSET3_0  ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
-#define ADC_OFR3_OFFSET3_1  ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
-#define ADC_OFR3_OFFSET3_2  ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
-#define ADC_OFR3_OFFSET3_3  ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
-#define ADC_OFR3_OFFSET3_4  ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
-#define ADC_OFR3_OFFSET3_5  ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
-#define ADC_OFR3_OFFSET3_6  ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
-#define ADC_OFR3_OFFSET3_7  ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
-#define ADC_OFR3_OFFSET3_8  ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
-#define ADC_OFR3_OFFSET3_9  ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
-#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
-#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
-
-#define ADC_OFR3_OFFSET3_CH     ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
-#define ADC_OFR3_OFFSET3_CH_0  ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
-#define ADC_OFR3_OFFSET3_CH_1  ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
-#define ADC_OFR3_OFFSET3_CH_2  ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
-#define ADC_OFR3_OFFSET3_CH_3  ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
-#define ADC_OFR3_OFFSET3_CH_4  ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
-
-#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
-
-/********************  Bit definition for ADC_OFR4 register  ********************/
-#define ADC_OFR4_OFFSET4    ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
-#define ADC_OFR4_OFFSET4_0  ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
-#define ADC_OFR4_OFFSET4_1  ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
-#define ADC_OFR4_OFFSET4_2  ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
-#define ADC_OFR4_OFFSET4_3  ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
-#define ADC_OFR4_OFFSET4_4  ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
-#define ADC_OFR4_OFFSET4_5  ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
-#define ADC_OFR4_OFFSET4_6  ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
-#define ADC_OFR4_OFFSET4_7  ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
-#define ADC_OFR4_OFFSET4_8  ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
-#define ADC_OFR4_OFFSET4_9  ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
-#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
-#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
-
-#define ADC_OFR4_OFFSET4_CH     ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
-#define ADC_OFR4_OFFSET4_CH_0  ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
-#define ADC_OFR4_OFFSET4_CH_1  ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
-#define ADC_OFR4_OFFSET4_CH_2  ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
-#define ADC_OFR4_OFFSET4_CH_3  ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
-#define ADC_OFR4_OFFSET4_CH_4  ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
-
-#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
-
-/********************  Bit definition for ADC_JDR1 register  ********************/
-#define ADC_JDR1_JDATA      ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
-#define ADC_JDR1_JDATA_0    ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
-#define ADC_JDR1_JDATA_1    ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
-#define ADC_JDR1_JDATA_2    ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
-#define ADC_JDR1_JDATA_3    ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
-#define ADC_JDR1_JDATA_4    ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
-#define ADC_JDR1_JDATA_5    ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
-#define ADC_JDR1_JDATA_6    ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
-#define ADC_JDR1_JDATA_7    ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
-#define ADC_JDR1_JDATA_8    ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
-#define ADC_JDR1_JDATA_9    ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
-#define ADC_JDR1_JDATA_10   ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
-#define ADC_JDR1_JDATA_11   ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
-#define ADC_JDR1_JDATA_12   ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
-#define ADC_JDR1_JDATA_13   ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
-#define ADC_JDR1_JDATA_14   ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
-#define ADC_JDR1_JDATA_15   ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
-
-/********************  Bit definition for ADC_JDR2 register  ********************/
-#define ADC_JDR2_JDATA      ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
-#define ADC_JDR2_JDATA_0    ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
-#define ADC_JDR2_JDATA_1    ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
-#define ADC_JDR2_JDATA_2    ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
-#define ADC_JDR2_JDATA_3    ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
-#define ADC_JDR2_JDATA_4    ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
-#define ADC_JDR2_JDATA_5    ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
-#define ADC_JDR2_JDATA_6    ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
-#define ADC_JDR2_JDATA_7    ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
-#define ADC_JDR2_JDATA_8    ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
-#define ADC_JDR2_JDATA_9    ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
-#define ADC_JDR2_JDATA_10   ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
-#define ADC_JDR2_JDATA_11   ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
-#define ADC_JDR2_JDATA_12   ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
-#define ADC_JDR2_JDATA_13   ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
-#define ADC_JDR2_JDATA_14   ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
-#define ADC_JDR2_JDATA_15   ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
-
-/********************  Bit definition for ADC_JDR3 register  ********************/
-#define ADC_JDR3_JDATA      ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
-#define ADC_JDR3_JDATA_0    ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
-#define ADC_JDR3_JDATA_1    ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
-#define ADC_JDR3_JDATA_2    ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
-#define ADC_JDR3_JDATA_3    ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
-#define ADC_JDR3_JDATA_4    ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
-#define ADC_JDR3_JDATA_5    ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
-#define ADC_JDR3_JDATA_6    ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
-#define ADC_JDR3_JDATA_7    ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
-#define ADC_JDR3_JDATA_8    ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
-#define ADC_JDR3_JDATA_9    ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
-#define ADC_JDR3_JDATA_10   ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
-#define ADC_JDR3_JDATA_11   ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
-#define ADC_JDR3_JDATA_12   ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
-#define ADC_JDR3_JDATA_13   ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
-#define ADC_JDR3_JDATA_14   ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
-#define ADC_JDR3_JDATA_15   ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
-
-/********************  Bit definition for ADC_JDR4 register  ********************/
-#define ADC_JDR4_JDATA      ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
-#define ADC_JDR4_JDATA_0    ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
-#define ADC_JDR4_JDATA_1    ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
-#define ADC_JDR4_JDATA_2    ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
-#define ADC_JDR4_JDATA_3    ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
-#define ADC_JDR4_JDATA_4    ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
-#define ADC_JDR4_JDATA_5    ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
-#define ADC_JDR4_JDATA_6    ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
-#define ADC_JDR4_JDATA_7    ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
-#define ADC_JDR4_JDATA_8    ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
-#define ADC_JDR4_JDATA_9    ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
-#define ADC_JDR4_JDATA_10   ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
-#define ADC_JDR4_JDATA_11   ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
-#define ADC_JDR4_JDATA_12   ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
-#define ADC_JDR4_JDATA_13   ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
-#define ADC_JDR4_JDATA_14   ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
-#define ADC_JDR4_JDATA_15   ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
-
-/********************  Bit definition for ADC_AWD2CR register  ********************/
-#define ADC_AWD2CR_AWD2CH    ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD2CR_AWD2CH_0  ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
-#define ADC_AWD2CR_AWD2CH_1  ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
-#define ADC_AWD2CR_AWD2CH_2  ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
-#define ADC_AWD2CR_AWD2CH_3  ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
-#define ADC_AWD2CR_AWD2CH_4  ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
-#define ADC_AWD2CR_AWD2CH_5  ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
-#define ADC_AWD2CR_AWD2CH_6  ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
-#define ADC_AWD2CR_AWD2CH_7  ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
-#define ADC_AWD2CR_AWD2CH_8  ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
-#define ADC_AWD2CR_AWD2CH_9  ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
-#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
-#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
-#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
-#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
-#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
-#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
-#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
-#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
-
-/********************  Bit definition for ADC_AWD3CR register  ********************/
-#define ADC_AWD3CR_AWD3CH    ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD3CR_AWD3CH_0  ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
-#define ADC_AWD3CR_AWD3CH_1  ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
-#define ADC_AWD3CR_AWD3CH_2  ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
-#define ADC_AWD3CR_AWD3CH_3  ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
-#define ADC_AWD3CR_AWD3CH_4  ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
-#define ADC_AWD3CR_AWD3CH_5  ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
-#define ADC_AWD3CR_AWD3CH_6  ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
-#define ADC_AWD3CR_AWD3CH_7  ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
-#define ADC_AWD3CR_AWD3CH_8  ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
-#define ADC_AWD3CR_AWD3CH_9  ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
-#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
-#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
-#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
-#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
-#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
-#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
-#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
-#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
-
-/********************  Bit definition for ADC_DIFSEL register  ********************/
-#define ADC_DIFSEL_DIFSEL    ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
-#define ADC_DIFSEL_DIFSEL_0  ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
-#define ADC_DIFSEL_DIFSEL_1  ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
-#define ADC_DIFSEL_DIFSEL_2  ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
-#define ADC_DIFSEL_DIFSEL_3  ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
-#define ADC_DIFSEL_DIFSEL_4  ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
-#define ADC_DIFSEL_DIFSEL_5  ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
-#define ADC_DIFSEL_DIFSEL_6  ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
-#define ADC_DIFSEL_DIFSEL_7  ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
-#define ADC_DIFSEL_DIFSEL_8  ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
-#define ADC_DIFSEL_DIFSEL_9  ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
-#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
-#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
-#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
-#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
-#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
-#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
-#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
-#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT_S   ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
-#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
-#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
-#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
-#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
-#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
-#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
-#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
-#define ADC_CALFACT_CALFACT_D   ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
-#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
-#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
-#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
-#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
-#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
-#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
-#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
-
-/*************************  ADC Common registers  *****************************/
-/********************  Bit definition for ADC12_CSR register  ********************/
-#define ADC12_CSR_ADRDY_MST         ((uint32_t)0x00000001) /*!< Master ADC ready */
-#define ADC12_CSR_ADRDY_EOSMP_MST   ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
-#define ADC12_CSR_ADRDY_EOC_MST     ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
-#define ADC12_CSR_ADRDY_EOS_MST     ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
-#define ADC12_CSR_ADRDY_OVR_MST     ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
-#define ADC12_CSR_ADRDY_JEOC_MST    ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
-#define ADC12_CSR_ADRDY_JEOS_MST    ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
-#define ADC12_CSR_AWD1_MST          ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
-#define ADC12_CSR_AWD2_MST          ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
-#define ADC12_CSR_AWD3_MST          ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
-#define ADC12_CSR_JQOVF_MST         ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
-#define ADC12_CSR_ADRDY_SLV         ((uint32_t)0x00010000) /*!< Slave ADC ready */
-#define ADC12_CSR_ADRDY_EOSMP_SLV   ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
-#define ADC12_CSR_ADRDY_EOC_SLV     ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
-#define ADC12_CSR_ADRDY_EOS_SLV     ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
-#define ADC12_CSR_ADRDY_OVR_SLV     ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
-#define ADC12_CSR_ADRDY_JEOC_SLV    ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
-#define ADC12_CSR_ADRDY_JEOS_SLV    ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
-#define ADC12_CSR_AWD1_SLV          ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
-#define ADC12_CSR_AWD2_SLV          ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
-#define ADC12_CSR_AWD3_SLV          ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
-#define ADC12_CSR_JQOVF_SLV         ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
-
-/********************  Bit definition for ADC34_CSR register  ********************/
-#define ADC34_CSR_ADRDY_MST         ((uint32_t)0x00000001) /*!< Master ADC ready */
-#define ADC34_CSR_ADRDY_EOSMP_MST   ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
-#define ADC34_CSR_ADRDY_EOC_MST     ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
-#define ADC34_CSR_ADRDY_EOS_MST     ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
-#define ADC34_CSR_ADRDY_OVR_MST     ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
-#define ADC34_CSR_ADRDY_JEOC_MST    ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
-#define ADC34_CSR_ADRDY_JEOS_MST    ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
-#define ADC34_CSR_AWD1_MST          ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
-#define ADC34_CSR_AWD2_MST          ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
-#define ADC34_CSR_AWD3_MST          ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
-#define ADC34_CSR_JQOVF_MST         ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
-#define ADC34_CSR_ADRDY_SLV         ((uint32_t)0x00010000) /*!< Slave ADC ready */
-#define ADC34_CSR_ADRDY_EOSMP_SLV   ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
-#define ADC34_CSR_ADRDY_EOC_SLV     ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
-#define ADC34_CSR_ADRDY_EOS_SLV     ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
-#define ADC12_CSR_ADRDY_OVR_SLV     ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
-#define ADC34_CSR_ADRDY_JEOC_SLV    ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
-#define ADC34_CSR_ADRDY_JEOS_SLV    ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
-#define ADC34_CSR_AWD1_SLV          ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
-#define ADC34_CSR_AWD2_SLV          ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
-#define ADC34_CSR_AWD3_SLV          ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
-#define ADC34_CSR_JQOVF_SLV         ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
-
-/********************  Bit definition for ADC_CCR register  ********************/
-#define ADC12_CCR_MULTI             ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
-#define ADC12_CCR_MULTI_0           ((uint32_t)0x00000001) /*!< MULTI bit 0 */
-#define ADC12_CCR_MULTI_1           ((uint32_t)0x00000002) /*!< MULTI bit 1 */
-#define ADC12_CCR_MULTI_2           ((uint32_t)0x00000004) /*!< MULTI bit 2 */
-#define ADC12_CCR_MULTI_3           ((uint32_t)0x00000008) /*!< MULTI bit 3 */
-#define ADC12_CCR_MULTI_4           ((uint32_t)0x00000010) /*!< MULTI bit 4 */
-#define ADC12_CCR_DELAY             ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
-#define ADC12_CCR_DELAY_0           ((uint32_t)0x00000100) /*!< DELAY bit 0 */
-#define ADC12_CCR_DELAY_1           ((uint32_t)0x00000200) /*!< DELAY bit 1 */
-#define ADC12_CCR_DELAY_2           ((uint32_t)0x00000400) /*!< DELAY bit 2 */
-#define ADC12_CCR_DELAY_3           ((uint32_t)0x00000800) /*!< DELAY bit 3 */
-#define ADC12_CCR_DMACFG            ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
-#define ADC12_CCR_MDMA              ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
-#define ADC12_CCR_MDMA_0            ((uint32_t)0x00004000) /*!< MDMA bit 0 */
-#define ADC12_CCR_MDMA_1            ((uint32_t)0x00008000) /*!< MDMA bit 1 */
-#define ADC12_CCR_CKMODE            ((uint32_t)0x00030000) /*!< ADC clock mode */
-#define ADC12_CCR_CKMODE_0          ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
-#define ADC12_CCR_CKMODE_1          ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
-#define ADC12_CCR_VREFEN            ((uint32_t)0x00400000) /*!< VREFINT enable */
-#define ADC12_CCR_TSEN              ((uint32_t)0x00800000) /*!< Temperature sensor enable */
-#define ADC12_CCR_VBATEN            ((uint32_t)0x01000000) /*!< VBAT enable */
-
-/********************  Bit definition for ADC_CCR register  ********************/
-#define ADC34_CCR_MULTI             ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
-#define ADC34_CCR_MULTI_0           ((uint32_t)0x00000001) /*!< MULTI bit 0 */
-#define ADC34_CCR_MULTI_1           ((uint32_t)0x00000002) /*!< MULTI bit 1 */
-#define ADC34_CCR_MULTI_2           ((uint32_t)0x00000004) /*!< MULTI bit 2 */
-#define ADC34_CCR_MULTI_3           ((uint32_t)0x00000008) /*!< MULTI bit 3 */
-#define ADC34_CCR_MULTI_4           ((uint32_t)0x00000010) /*!< MULTI bit 4 */
-
-#define ADC34_CCR_DELAY             ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
-#define ADC34_CCR_DELAY_0           ((uint32_t)0x00000100) /*!< DELAY bit 0 */
-#define ADC34_CCR_DELAY_1           ((uint32_t)0x00000200) /*!< DELAY bit 1 */
-#define ADC34_CCR_DELAY_2           ((uint32_t)0x00000400) /*!< DELAY bit 2 */
-#define ADC34_CCR_DELAY_3           ((uint32_t)0x00000800) /*!< DELAY bit 3 */
-
-#define ADC34_CCR_DMACFG            ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
-#define ADC34_CCR_MDMA              ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
-#define ADC34_CCR_MDMA_0            ((uint32_t)0x00004000) /*!< MDMA bit 0 */
-#define ADC34_CCR_MDMA_1            ((uint32_t)0x00008000) /*!< MDMA bit 1 */
-
-#define ADC34_CCR_CKMODE            ((uint32_t)0x00030000) /*!< ADC clock mode */
-#define ADC34_CCR_CKMODE_0          ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
-#define ADC34_CCR_CKMODE_1          ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
-
-#define ADC34_CCR_VREFEN            ((uint32_t)0x00400000) /*!< VREFINT enable */
-#define ADC34_CCR_TSEN              ((uint32_t)0x00800000) /*!< Temperature sensor enable */
-#define ADC34_CCR_VBATEN            ((uint32_t)0x01000000) /*!< VBAT enable */
-
-/********************  Bit definition for ADC_CDR register  ********************/
-#define ADC12_CDR_RDATA_MST         ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
-#define ADC12_CDR_RDATA_MST_0       ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
-#define ADC12_CDR_RDATA_MST_1       ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
-#define ADC12_CDR_RDATA_MST_2       ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
-#define ADC12_CDR_RDATA_MST_3       ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
-#define ADC12_CDR_RDATA_MST_4       ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
-#define ADC12_CDR_RDATA_MST_5       ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
-#define ADC12_CDR_RDATA_MST_6       ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
-#define ADC12_CDR_RDATA_MST_7       ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
-#define ADC12_CDR_RDATA_MST_8       ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
-#define ADC12_CDR_RDATA_MST_9       ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
-#define ADC12_CDR_RDATA_MST_10      ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
-#define ADC12_CDR_RDATA_MST_11      ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
-#define ADC12_CDR_RDATA_MST_12      ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
-#define ADC12_CDR_RDATA_MST_13      ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
-#define ADC12_CDR_RDATA_MST_14      ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
-#define ADC12_CDR_RDATA_MST_15      ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
-
-#define ADC12_CDR_RDATA_SLV         ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
-#define ADC12_CDR_RDATA_SLV_0       ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
-#define ADC12_CDR_RDATA_SLV_1       ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
-#define ADC12_CDR_RDATA_SLV_2       ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
-#define ADC12_CDR_RDATA_SLV_3       ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
-#define ADC12_CDR_RDATA_SLV_4       ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
-#define ADC12_CDR_RDATA_SLV_5       ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
-#define ADC12_CDR_RDATA_SLV_6       ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
-#define ADC12_CDR_RDATA_SLV_7       ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
-#define ADC12_CDR_RDATA_SLV_8       ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
-#define ADC12_CDR_RDATA_SLV_9       ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
-#define ADC12_CDR_RDATA_SLV_10      ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
-#define ADC12_CDR_RDATA_SLV_11      ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
-#define ADC12_CDR_RDATA_SLV_12      ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
-#define ADC12_CDR_RDATA_SLV_13      ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
-#define ADC12_CDR_RDATA_SLV_14      ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
-#define ADC12_CDR_RDATA_SLV_15      ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
-
-/********************  Bit definition for ADC_CDR register  ********************/
-#define ADC34_CDR_RDATA_MST         ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
-#define ADC34_CDR_RDATA_MST_0       ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
-#define ADC34_CDR_RDATA_MST_1       ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
-#define ADC34_CDR_RDATA_MST_2       ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
-#define ADC34_CDR_RDATA_MST_3       ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
-#define ADC34_CDR_RDATA_MST_4       ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
-#define ADC34_CDR_RDATA_MST_5       ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
-#define ADC34_CDR_RDATA_MST_6       ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
-#define ADC34_CDR_RDATA_MST_7       ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
-#define ADC34_CDR_RDATA_MST_8       ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
-#define ADC34_CDR_RDATA_MST_9       ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
-#define ADC34_CDR_RDATA_MST_10      ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
-#define ADC34_CDR_RDATA_MST_11      ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
-#define ADC34_CDR_RDATA_MST_12      ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
-#define ADC34_CDR_RDATA_MST_13      ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
-#define ADC34_CDR_RDATA_MST_14      ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
-#define ADC34_CDR_RDATA_MST_15      ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
-
-#define ADC34_CDR_RDATA_SLV         ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
-#define ADC34_CDR_RDATA_SLV_0       ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
-#define ADC34_CDR_RDATA_SLV_1       ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
-#define ADC34_CDR_RDATA_SLV_2       ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
-#define ADC34_CDR_RDATA_SLV_3       ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
-#define ADC34_CDR_RDATA_SLV_4       ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
-#define ADC34_CDR_RDATA_SLV_5       ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
-#define ADC34_CDR_RDATA_SLV_6       ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
-#define ADC34_CDR_RDATA_SLV_7       ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
-#define ADC34_CDR_RDATA_SLV_8       ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
-#define ADC34_CDR_RDATA_SLV_9       ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
-#define ADC34_CDR_RDATA_SLV_10      ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
-#define ADC34_CDR_RDATA_SLV_11      ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
-#define ADC34_CDR_RDATA_SLV_12      ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
-#define ADC34_CDR_RDATA_SLV_13      ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
-#define ADC34_CDR_RDATA_SLV_14      ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
-#define ADC34_CDR_RDATA_SLV_15      ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/**********************  Bit definition for COMP1_CSR register  ***************/
-#define COMP1_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP1_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
-#define COMP1_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
-#define COMP1_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
-#define COMP1_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
-#define COMP1_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
-#define COMP1_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP1_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP1_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
-#define COMP1_CSR_COMP1NONINSEL         ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */
-#define COMP1_CSR_COMP1OUTSEL           ((uint32_t)0x00003C00) /*!< COMP1 output select */
-#define COMP1_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
-#define COMP1_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
-#define COMP1_CSR_COMP1OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
-#define COMP1_CSR_COMP1OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
-#define COMP1_CSR_COMP1POL              ((uint32_t)0x00008000) /*!< COMP1 output polarity */
-#define COMP1_CSR_COMP1HYST             ((uint32_t)0x00030000) /*!< COMP1 hysteresis */
-#define COMP1_CSR_COMP1HYST_0           ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */
-#define COMP1_CSR_COMP1HYST_1           ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */
-#define COMP1_CSR_COMP1BLANKING         ((uint32_t)0x000C0000) /*!< COMP1 blanking */
-#define COMP1_CSR_COMP1BLANKING_0       ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
-#define COMP1_CSR_COMP1BLANKING_1       ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
-#define COMP1_CSR_COMP1BLANKING_2       ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
-#define COMP1_CSR_COMP1OUT              ((uint32_t)0x40000000) /*!< COMP1 output level */
-#define COMP1_CSR_COMP1LOCK             ((uint32_t)0x80000000) /*!< COMP1 lock */
-
-/**********************  Bit definition for COMP2_CSR register  ***************/
-#define COMP2_CSR_COMP2EN               ((uint32_t)0x00000001) /*!< COMP2 enable */
-#define COMP2_CSR_COMP2MODE             ((uint32_t)0x0000000C) /*!< COMP2 power mode */
-#define COMP2_CSR_COMP2MODE_0           ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */
-#define COMP2_CSR_COMP2MODE_1           ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */
-#define COMP2_CSR_COMP2INSEL            ((uint32_t)0x00000070) /*!< COMP2 inverting input select */
-#define COMP2_CSR_COMP2INSEL_0          ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
-#define COMP2_CSR_COMP2INSEL_1          ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
-#define COMP2_CSR_COMP2INSEL_2          ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
-#define COMP2_CSR_COMP2NONINSEL         ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */
-#define COMP2_CSR_COMP2WNDWEN           ((uint32_t)0x00000200) /*!< COMP2 window mode enable */
-#define COMP2_CSR_COMP2OUTSEL           ((uint32_t)0x00003C00) /*!< COMP2 output select */
-#define COMP2_CSR_COMP2OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
-#define COMP2_CSR_COMP2OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
-#define COMP2_CSR_COMP2OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
-#define COMP2_CSR_COMP2OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
-#define COMP2_CSR_COMP2POL              ((uint32_t)0x00008000) /*!< COMP2 output polarity */
-#define COMP2_CSR_COMP2HYST             ((uint32_t)0x00030000) /*!< COMP2 hysteresis */
-#define COMP2_CSR_COMP2HYST_0           ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */
-#define COMP2_CSR_COMP2HYST_1           ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */
-#define COMP2_CSR_COMP2BLANKING         ((uint32_t)0x000C0000) /*!< COMP2 blanking */
-#define COMP2_CSR_COMP2BLANKING_0       ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
-#define COMP2_CSR_COMP2BLANKING_1       ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
-#define COMP2_CSR_COMP2BLANKING_2       ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
-#define COMP2_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP2_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP3_CSR register  ***************/
-#define COMP3_CSR_COMP3EN               ((uint32_t)0x00000001) /*!< COMP3 enable */
-#define COMP3_CSR_COMP3MODE             ((uint32_t)0x0000000C) /*!< COMP3 power mode */
-#define COMP3_CSR_COMP3MODE_0           ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */
-#define COMP3_CSR_COMP3MODE_1           ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */
-#define COMP3_CSR_COMP3INSEL            ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
-#define COMP3_CSR_COMP3INSEL_0          ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
-#define COMP3_CSR_COMP3INSEL_1          ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
-#define COMP3_CSR_COMP3INSEL_2          ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
-#define COMP3_CSR_COMP3NONINSEL         ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */
-#define COMP3_CSR_COMP3OUTSEL           ((uint32_t)0x00003C00) /*!< COMP3 output select */
-#define COMP3_CSR_COMP3OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
-#define COMP3_CSR_COMP3OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
-#define COMP3_CSR_COMP3OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
-#define COMP3_CSR_COMP3OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
-#define COMP3_CSR_COMP3POL              ((uint32_t)0x00008000) /*!< COMP3 output polarity */
-#define COMP3_CSR_COMP3HYST             ((uint32_t)0x00030000) /*!< COMP3 hysteresis */
-#define COMP3_CSR_COMP3HYST_0           ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */
-#define COMP3_CSR_COMP3HYST_1           ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */
-#define COMP3_CSR_COMP3BLANKING         ((uint32_t)0x000C0000) /*!< COMP3 blanking */
-#define COMP3_CSR_COMP3BLANKING_0       ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
-#define COMP3_CSR_COMP3BLANKING_1       ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
-#define COMP3_CSR_COMP3BLANKING_2       ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
-#define COMP3_CSR_COMP3OUT              ((uint32_t)0x40000000) /*!< COMP3 output level */
-#define COMP3_CSR_COMP3LOCK             ((uint32_t)0x80000000) /*!< COMP3 lock */
-
-/**********************  Bit definition for COMP4_CSR register  ***************/
-#define COMP4_CSR_COMP4EN               ((uint32_t)0x00000001) /*!< COMP4 enable */
-#define COMP4_CSR_COMP4MODE             ((uint32_t)0x0000000C) /*!< COMP4 power mode */
-#define COMP4_CSR_COMP4MODE_0           ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */
-#define COMP4_CSR_COMP4MODE_1           ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */
-#define COMP4_CSR_COMP4INSEL            ((uint32_t)0x00000070) /*!< COMP4 inverting input select */
-#define COMP4_CSR_COMP4INSEL_0          ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
-#define COMP4_CSR_COMP4INSEL_1          ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
-#define COMP4_CSR_COMP4INSEL_2          ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
-#define COMP4_CSR_COMP4NONINSEL         ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */
-#define COMP4_CSR_COMP4WNDWEN           ((uint32_t)0x00000200) /*!< COMP4 window mode enable */
-#define COMP4_CSR_COMP4OUTSEL           ((uint32_t)0x00003C00) /*!< COMP4 output select */
-#define COMP4_CSR_COMP4OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
-#define COMP4_CSR_COMP4OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
-#define COMP4_CSR_COMP4OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
-#define COMP4_CSR_COMP4OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
-#define COMP4_CSR_COMP4POL              ((uint32_t)0x00008000) /*!< COMP4 output polarity */
-#define COMP4_CSR_COMP4HYST             ((uint32_t)0x00030000) /*!< COMP4 hysteresis */
-#define COMP4_CSR_COMP4HYST_0           ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */
-#define COMP4_CSR_COMP4HYST_1           ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */
-#define COMP4_CSR_COMP4BLANKING         ((uint32_t)0x000C0000) /*!< COMP4 blanking */
-#define COMP4_CSR_COMP4BLANKING_0       ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
-#define COMP4_CSR_COMP4BLANKING_1       ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
-#define COMP4_CSR_COMP4BLANKING_2       ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
-#define COMP4_CSR_COMP4OUT              ((uint32_t)0x40000000) /*!< COMP4 output level */
-#define COMP4_CSR_COMP4LOCK             ((uint32_t)0x80000000) /*!< COMP4 lock */
-
-/**********************  Bit definition for COMP5_CSR register  ***************/
-#define COMP5_CSR_COMP5EN               ((uint32_t)0x00000001) /*!< COMP5 enable */
-#define COMP5_CSR_COMP5MODE             ((uint32_t)0x0000000C) /*!< COMP5 power mode */
-#define COMP5_CSR_COMP5MODE_0           ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */
-#define COMP5_CSR_COMP5MODE_1           ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */
-#define COMP5_CSR_COMP5INSEL            ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
-#define COMP5_CSR_COMP5INSEL_0          ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
-#define COMP5_CSR_COMP5INSEL_1          ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
-#define COMP5_CSR_COMP5INSEL_2          ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
-#define COMP5_CSR_COMP5NONINSEL         ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */
-#define COMP5_CSR_COMP5OUTSEL           ((uint32_t)0x00003C00) /*!< COMP5 output select */
-#define COMP5_CSR_COMP5OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
-#define COMP5_CSR_COMP5OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
-#define COMP5_CSR_COMP5OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
-#define COMP5_CSR_COMP5OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
-#define COMP5_CSR_COMP5POL              ((uint32_t)0x00008000) /*!< COMP5 output polarity */
-#define COMP5_CSR_COMP5HYST             ((uint32_t)0x00030000) /*!< COMP5 hysteresis */
-#define COMP5_CSR_COMP5HYST_0           ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */
-#define COMP5_CSR_COMP5HYST_1           ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */
-#define COMP5_CSR_COMP5BLANKING         ((uint32_t)0x000C0000) /*!< COMP5 blanking */
-#define COMP5_CSR_COMP5BLANKING_0       ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
-#define COMP5_CSR_COMP5BLANKING_1       ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
-#define COMP5_CSR_COMP5BLANKING_2       ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
-#define COMP5_CSR_COMP5OUT              ((uint32_t)0x40000000) /*!< COMP5 output level */
-#define COMP5_CSR_COMP5LOCK             ((uint32_t)0x80000000) /*!< COMP5 lock */
-
-/**********************  Bit definition for COMP6_CSR register  ***************/
-#define COMP6_CSR_COMP6EN               ((uint32_t)0x00000001) /*!< COMP6 enable */
-#define COMP6_CSR_COMP6MODE             ((uint32_t)0x0000000C) /*!< COMP6 power mode */
-#define COMP6_CSR_COMP6MODE_0           ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */
-#define COMP6_CSR_COMP6MODE_1           ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */
-#define COMP6_CSR_COMP6INSEL            ((uint32_t)0x00000070) /*!< COMP6 inverting input select */
-#define COMP6_CSR_COMP6INSEL_0          ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
-#define COMP6_CSR_COMP6INSEL_1          ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
-#define COMP6_CSR_COMP6INSEL_2          ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
-#define COMP6_CSR_COMP6NONINSEL         ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */
-#define COMP6_CSR_COMP6WNDWEN           ((uint32_t)0x00000200) /*!< COMP6 window mode enable */
-#define COMP6_CSR_COMP6OUTSEL           ((uint32_t)0x00003C00) /*!< COMP6 output select */
-#define COMP6_CSR_COMP6OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
-#define COMP6_CSR_COMP6OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
-#define COMP6_CSR_COMP6OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
-#define COMP6_CSR_COMP6OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
-#define COMP6_CSR_COMP6POL              ((uint32_t)0x00008000) /*!< COMP6 output polarity */
-#define COMP6_CSR_COMP6HYST             ((uint32_t)0x00030000) /*!< COMP6 hysteresis */
-#define COMP6_CSR_COMP6HYST_0           ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */
-#define COMP6_CSR_COMP6HYST_1           ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */
-#define COMP6_CSR_COMP6BLANKING         ((uint32_t)0x000C0000) /*!< COMP6 blanking */
-#define COMP6_CSR_COMP6BLANKING_0       ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
-#define COMP6_CSR_COMP6BLANKING_1       ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
-#define COMP6_CSR_COMP6BLANKING_2       ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
-#define COMP6_CSR_COMP6OUT              ((uint32_t)0x40000000) /*!< COMP6 output level */
-#define COMP6_CSR_COMP6LOCK             ((uint32_t)0x80000000) /*!< COMP6 lock */
-
-/**********************  Bit definition for COMP7_CSR register  ***************/
-#define COMP7_CSR_COMP7EN               ((uint32_t)0x00000001) /*!< COMP7 enable */
-#define COMP7_CSR_COMP7MODE             ((uint32_t)0x0000000C) /*!< COMP7 power mode */
-#define COMP7_CSR_COMP7MODE_0           ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */
-#define COMP7_CSR_COMP7MODE_1           ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */
-#define COMP7_CSR_COMP7INSEL            ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
-#define COMP7_CSR_COMP7INSEL_0          ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
-#define COMP7_CSR_COMP7INSEL_1          ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
-#define COMP7_CSR_COMP7INSEL_2          ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
-#define COMP7_CSR_COMP7NONINSEL         ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */
-#define COMP7_CSR_COMP7OUTSEL           ((uint32_t)0x00003C00) /*!< COMP7 output select */
-#define COMP7_CSR_COMP7OUTSEL_0         ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
-#define COMP7_CSR_COMP7OUTSEL_1         ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
-#define COMP7_CSR_COMP7OUTSEL_2         ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
-#define COMP7_CSR_COMP7OUTSEL_3         ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
-#define COMP7_CSR_COMP7POL              ((uint32_t)0x00008000) /*!< COMP7 output polarity */
-#define COMP7_CSR_COMP7HYST             ((uint32_t)0x00030000) /*!< COMP7 hysteresis */
-#define COMP7_CSR_COMP7HYST_0           ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */
-#define COMP7_CSR_COMP7HYST_1           ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */
-#define COMP7_CSR_COMP7BLANKING         ((uint32_t)0x000C0000) /*!< COMP7 blanking */
-#define COMP7_CSR_COMP7BLANKING_0       ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
-#define COMP7_CSR_COMP7BLANKING_1       ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
-#define COMP7_CSR_COMP7BLANKING_2       ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
-#define COMP7_CSR_COMP7OUT              ((uint32_t)0x40000000) /*!< COMP7 output level */
-#define COMP7_CSR_COMP7LOCK             ((uint32_t)0x80000000) /*!< COMP7 lock */
-
-/**********************  Bit definition for COMP_CSR register  ****************/
-#define COMP_CSR_COMPxEN               ((uint32_t)0x00000001) /*!< COMPx enable */
-#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
-#define COMP_CSR_COMPxMODE             ((uint32_t)0x0000000C) /*!< COMPx power mode */
-#define COMP_CSR_COMPxMODE_0           ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
-#define COMP_CSR_COMPxMODE_1           ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
-#define COMP_CSR_COMPxINSEL            ((uint32_t)0x00000070) /*!< COMPx inverting input select */
-#define COMP_CSR_COMPxINSEL_0          ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
-#define COMP_CSR_COMPxINSEL_1          ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
-#define COMP_CSR_COMPxINSEL_2          ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxNONINSEL         ((uint32_t)0x00000080) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMPxWNDWEN           ((uint32_t)0x00000200) /*!< COMPx window mode enable */
-#define COMP_CSR_COMPxOUTSEL           ((uint32_t)0x00003C00) /*!< COMPx output select */
-#define COMP_CSR_COMPxOUTSEL_0         ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
-#define COMP_CSR_COMPxOUTSEL_1         ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
-#define COMP_CSR_COMPxOUTSEL_2         ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
-#define COMP_CSR_COMPxOUTSEL_3         ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
-#define COMP_CSR_COMPxPOL              ((uint32_t)0x00008000) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxHYST             ((uint32_t)0x00030000) /*!< COMPx hysteresis */
-#define COMP_CSR_COMPxHYST_0           ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */
-#define COMP_CSR_COMPxHYST_1           ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */
-#define COMP_CSR_COMPxBLANKING         ((uint32_t)0x000C0000) /*!< COMPx blanking */
-#define COMP_CSR_COMPxBLANKING_0       ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
-#define COMP_CSR_COMPxBLANKING_1       ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
-#define COMP_CSR_COMPxBLANKING_2       ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
-#define COMP_CSR_COMPxOUT              ((uint32_t)0x40000000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK             ((uint32_t)0x80000000) /*!< COMPx lock */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Operational Amplifier (OPAMP)                          */
-/*                                                                            */
-/******************************************************************************/
-/*********************  Bit definition for OPAMP1_CSR register  ***************/
-#define OPAMP1_CSR_OPAMP1EN               ((uint32_t)0x00000001) /*!< OPAMP1 enable */
-#define OPAMP1_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
-#define OPAMP1_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
-#define OPAMP1_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
-#define OPAMP1_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
-#define OPAMP1_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
-#define OPAMP1_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
-#define OPAMP1_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
-#define OPAMP1_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
-#define OPAMP1_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
-#define OPAMP1_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
-#define OPAMP1_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
-#define OPAMP1_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
-#define OPAMP1_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
-#define OPAMP1_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
-#define OPAMP1_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
-#define OPAMP1_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
-#define OPAMP1_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
-#define OPAMP1_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
-#define OPAMP1_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
-#define OPAMP1_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
-#define OPAMP1_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
-#define OPAMP1_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
-#define OPAMP1_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
-#define OPAMP1_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
-#define OPAMP1_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
-#define OPAMP1_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
-#define OPAMP1_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
-
-/*********************  Bit definition for OPAMP2_CSR register  ***************/
-#define OPAMP2_CSR_OPAMP2EN               ((uint32_t)0x00000001) /*!< OPAMP2 enable */
-#define OPAMP2_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
-#define OPAMP2_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
-#define OPAMP2_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
-#define OPAMP2_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
-#define OPAMP2_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
-#define OPAMP2_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
-#define OPAMP2_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
-#define OPAMP2_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
-#define OPAMP2_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
-#define OPAMP2_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
-#define OPAMP2_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
-#define OPAMP2_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
-#define OPAMP2_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
-#define OPAMP2_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
-#define OPAMP2_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
-#define OPAMP2_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
-#define OPAMP2_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
-#define OPAMP2_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
-#define OPAMP2_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
-#define OPAMP2_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
-#define OPAMP2_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
-#define OPAMP2_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
-#define OPAMP2_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
-#define OPAMP2_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
-#define OPAMP2_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
-#define OPAMP2_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
-#define OPAMP2_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
-
-/*********************  Bit definition for OPAMP3_CSR register  ***************/
-#define OPAMP3_CSR_OPAMP3EN               ((uint32_t)0x00000001) /*!< OPAMP3 enable */
-#define OPAMP3_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
-#define OPAMP3_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
-#define OPAMP3_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
-#define OPAMP3_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
-#define OPAMP3_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
-#define OPAMP3_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
-#define OPAMP3_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
-#define OPAMP3_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
-#define OPAMP3_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
-#define OPAMP3_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
-#define OPAMP3_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
-#define OPAMP3_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
-#define OPAMP3_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
-#define OPAMP3_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
-#define OPAMP3_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
-#define OPAMP3_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
-#define OPAMP3_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
-#define OPAMP3_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
-#define OPAMP3_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
-#define OPAMP3_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
-#define OPAMP3_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
-#define OPAMP3_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
-#define OPAMP3_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
-#define OPAMP3_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
-#define OPAMP3_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
-#define OPAMP3_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
-#define OPAMP3_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
-
-/*********************  Bit definition for OPAMP4_CSR register  ***************/
-#define OPAMP4_CSR_OPAMP4EN               ((uint32_t)0x00000001) /*!< OPAMP4 enable */
-#define OPAMP4_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
-#define OPAMP4_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
-#define OPAMP4_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
-#define OPAMP4_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
-#define OPAMP4_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
-#define OPAMP4_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
-#define OPAMP4_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
-#define OPAMP4_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
-#define OPAMP4_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
-#define OPAMP4_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
-#define OPAMP4_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
-#define OPAMP4_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
-#define OPAMP4_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
-#define OPAMP4_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
-#define OPAMP4_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
-#define OPAMP4_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
-#define OPAMP4_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
-#define OPAMP4_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
-#define OPAMP4_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
-#define OPAMP4_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
-#define OPAMP4_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
-#define OPAMP4_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
-#define OPAMP4_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
-#define OPAMP4_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
-#define OPAMP4_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
-#define OPAMP4_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
-#define OPAMP4_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
-
-/*********************  Bit definition for OPAMPx_CSR register  ***************/
-#define OPAMP_CSR_OPAMPxEN               ((uint32_t)0x00000001) /*!< OPAMP enable */
-#define OPAMP_CSR_FORCEVP                ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
-#define OPAMP_CSR_VPSEL                  ((uint32_t)0x0000000C) /*!< Non inverting input selection */
-#define OPAMP_CSR_VPSEL_0                ((uint32_t)0x00000004) /*!< Bit 0 */
-#define OPAMP_CSR_VPSEL_1                ((uint32_t)0x00000008) /*!< Bit 1 */
-#define OPAMP_CSR_VMSEL                  ((uint32_t)0x00000060) /*!< Inverting input selection */
-#define OPAMP_CSR_VMSEL_0                ((uint32_t)0x00000020) /*!< Bit 0 */
-#define OPAMP_CSR_VMSEL_1                ((uint32_t)0x00000040) /*!< Bit 1 */
-#define OPAMP_CSR_TCMEN                  ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
-#define OPAMP_CSR_VMSSEL                 ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
-#define OPAMP_CSR_VPSSEL                 ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
-#define OPAMP_CSR_VPSSEL_0               ((uint32_t)0x00000200) /*!< Bit 0 */
-#define OPAMP_CSR_VPSSEL_1               ((uint32_t)0x00000400) /*!< Bit 1 */
-#define OPAMP_CSR_CALON                  ((uint32_t)0x00000800) /*!< Calibration mode enable */
-#define OPAMP_CSR_CALSEL                 ((uint32_t)0x00003000) /*!< Calibration selection */
-#define OPAMP_CSR_CALSEL_0               ((uint32_t)0x00001000) /*!< Bit 0 */
-#define OPAMP_CSR_CALSEL_1               ((uint32_t)0x00002000) /*!< Bit 1 */
-#define OPAMP_CSR_PGGAIN                 ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
-#define OPAMP_CSR_PGGAIN_0               ((uint32_t)0x00004000) /*!< Bit 0 */
-#define OPAMP_CSR_PGGAIN_1               ((uint32_t)0x00008000) /*!< Bit 1 */
-#define OPAMP_CSR_PGGAIN_2               ((uint32_t)0x00010000) /*!< Bit 2 */
-#define OPAMP_CSR_PGGAIN_3               ((uint32_t)0x00020000) /*!< Bit 3 */
-#define OPAMP_CSR_USERTRIM               ((uint32_t)0x00040000) /*!< User trimming enable */
-#define OPAMP_CSR_TRIMOFFSETP            ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
-#define OPAMP_CSR_TRIMOFFSETN            ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
-#define OPAMP_CSR_TSTREF                 ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
-#define OPAMP_CSR_OUTCAL                 ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
-#define OPAMP_CSR_LOCK                   ((uint32_t)0x80000000) /*!< OPAMP lock */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Controller Area Network (CAN )                           */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
-#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
-#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
-#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
-#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
-#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
-#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
-#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
-#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
-#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
-#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
-#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     CRC calculation unit (CRC)                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits */
-#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
-#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
-#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< Bit 0 */
-#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< Bit 1 */
-#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU (DBGMCU)                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP        ((uint32_t)0x00000004)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
-#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00000004)
-#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00000008)
-#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00000010)
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller (DMA)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
-#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
-#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
-#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
-#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
-#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
-#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
-#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
-#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
-#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
-
-#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
-#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
-#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
-#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
-
-#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
-#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
-#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller (EXTI)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
-#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
-#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
-#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
-#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
-#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
-#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
-#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
-#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
-#define  EXTI_RTSR_TR24                      ((uint32_t)0x01000000)        /*!< Rising trigger event configuration bit of line 24 */
-#define  EXTI_RTSR_TR25                      ((uint32_t)0x02000000)        /*!< Rising trigger event configuration bit of line 25 */
-#define  EXTI_RTSR_TR26                      ((uint32_t)0x04000000)        /*!< Rising trigger event configuration bit of line 26 */
-#define  EXTI_RTSR_TR27                      ((uint32_t)0x08000000)        /*!< Rising trigger event configuration bit of line 27 */
-#define  EXTI_RTSR_TR28                      ((uint32_t)0x10000000)        /*!< Rising trigger event configuration bit of line 28 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
-#define  EXTI_FTSR_TR24                      ((uint32_t)0x01000000)        /*!< Falling trigger event configuration bit of line 24 */
-#define  EXTI_FTSR_TR25                      ((uint32_t)0x02000000)        /*!< Falling trigger event configuration bit of line 25 */
-#define  EXTI_FTSR_TR26                      ((uint32_t)0x04000000)        /*!< Falling trigger event configuration bit of line 26 */
-#define  EXTI_FTSR_TR27                      ((uint32_t)0x08000000)        /*!< Falling trigger event configuration bit of line 27 */
-#define  EXTI_FTSR_TR28                      ((uint32_t)0x10000000)        /*!< Falling trigger event configuration bit of line 28 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
-#define  EXTI_SWIER_SWIER24                  ((uint32_t)0x01000000)        /*!< Software Interrupt on line 24 */
-#define  EXTI_SWIER_SWIER25                  ((uint32_t)0x02000000)        /*!< Software Interrupt on line 25 */
-#define  EXTI_SWIER_SWIER26                  ((uint32_t)0x04000000)        /*!< Software Interrupt on line 26 */
-#define  EXTI_SWIER_SWIER27                  ((uint32_t)0x08000000)        /*!< Software Interrupt on line 27 */
-#define  EXTI_SWIER_SWIER28                  ((uint32_t)0x10000000)        /*!< Software Interrupt on line 28 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit for line 23 */
-#define  EXTI_PR_PR24                        ((uint32_t)0x01000000)        /*!< Pending bit for line 24 */
-#define  EXTI_PR_PR25                        ((uint32_t)0x02000000)        /*!< Pending bit for line 25 */
-#define  EXTI_PR_PR26                        ((uint32_t)0x04000000)        /*!< Pending bit for line 26 */
-#define  EXTI_PR_PR27                        ((uint32_t)0x08000000)        /*!< Pending bit for line 27 */
-#define  EXTI_PR_PR28                        ((uint32_t)0x10000000)        /*!< Pending bit for line 28 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
-#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x01)               /*!< Bit 0 */
-#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x02)               /*!< Bit 1 */
-
-#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
-#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)  
-
-/******************  Bit definition for FLASH_KEYR register  ******************/
-#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
-
-#define  RDP_KEY                             ((uint16_t)0x00A5)            /*!< RDP Key */
-#define  FLASH_KEY1                          ((uint32_t)0x45670123)        /*!< FPEC Key1 */
-#define  FLASH_KEY2                          ((uint32_t)0xCDEF89AB)        /*!< FPEC Key2 */
-
-/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
-
-#define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
-#define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
-#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000010)        /*!< Write Protection Error */
-#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
-
-/*******************  Bit definition for FLASH_CR register  *******************/
-#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
-#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
-#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
-#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
-#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
-#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
-#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
-#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
-#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
-#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
-#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< OptionBytes Loader Launch */
-
-/*******************  Bit definition for FLASH_AR register  *******************/
-#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
-#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
-#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */
-
-#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
-#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)      /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for OB_RDP register  **********************/
-#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
-#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
-
-/******************  Bit definition for OB_USER register  *********************/
-#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
-#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
-
-/******************  Bit definition for FLASH_WRP0 register  ******************/
-#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP1 register  ******************/
-#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP2 register  ******************/
-#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP3 register  ******************/
-#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O (GPIO)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
-#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
-#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
-#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
-#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
-#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
-#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
-#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
-#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
-#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
-#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
-#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
-#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
-#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
-#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
-#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
-
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
-
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)                       
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_0                 ((uint32_t)0x00000001)
-#define GPIO_IDR_1                 ((uint32_t)0x00000002)
-#define GPIO_IDR_2                 ((uint32_t)0x00000004)
-#define GPIO_IDR_3                 ((uint32_t)0x00000008)
-#define GPIO_IDR_4                 ((uint32_t)0x00000010)
-#define GPIO_IDR_5                 ((uint32_t)0x00000020)
-#define GPIO_IDR_6                 ((uint32_t)0x00000040)
-#define GPIO_IDR_7                 ((uint32_t)0x00000080)
-#define GPIO_IDR_8                 ((uint32_t)0x00000100)
-#define GPIO_IDR_9                 ((uint32_t)0x00000200)
-#define GPIO_IDR_10                ((uint32_t)0x00000400)
-#define GPIO_IDR_11                ((uint32_t)0x00000800)
-#define GPIO_IDR_12                ((uint32_t)0x00001000)
-#define GPIO_IDR_13                ((uint32_t)0x00002000)
-#define GPIO_IDR_14                ((uint32_t)0x00004000)
-#define GPIO_IDR_15                ((uint32_t)0x00008000)
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_0                 ((uint32_t)0x00000001)
-#define GPIO_ODR_1                 ((uint32_t)0x00000002)
-#define GPIO_ODR_2                 ((uint32_t)0x00000004)
-#define GPIO_ODR_3                 ((uint32_t)0x00000008)
-#define GPIO_ODR_4                 ((uint32_t)0x00000010)
-#define GPIO_ODR_5                 ((uint32_t)0x00000020)
-#define GPIO_ODR_6                 ((uint32_t)0x00000040)
-#define GPIO_ODR_7                 ((uint32_t)0x00000080)
-#define GPIO_ODR_8                 ((uint32_t)0x00000100)
-#define GPIO_ODR_9                 ((uint32_t)0x00000200)
-#define GPIO_ODR_10                ((uint32_t)0x00000400)
-#define GPIO_ODR_11                ((uint32_t)0x00000800)
-#define GPIO_ODR_12                ((uint32_t)0x00001000)
-#define GPIO_ODR_13                ((uint32_t)0x00002000)
-#define GPIO_ODR_14                ((uint32_t)0x00004000)
-#define GPIO_ODR_15                ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
-#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
-#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
-#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
-#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
-#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
-#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
-#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
-#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
-#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
-#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
-#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
-#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
-#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
-#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
-#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
-#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
-#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
-#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
-#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
-#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
-#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
-#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
-#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
-#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
-#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
-#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
-#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
-#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
-#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *****************/
-#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
-#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
-#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
-#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *****************/
-#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
-#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
-#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
-#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
-#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
-#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
-#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
-#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
-#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
-#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
-#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
-#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
-#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
-#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
-#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
-#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
-#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
-#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
-#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
-#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
-#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
-#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
-#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
-#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
-#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
-#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  ********************/
-#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG (IWDG)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                       ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
-#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
-#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
-
-#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
-#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
-#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
-
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
-
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-#define  RCC_CFGR_PLLSRC_HSI_Div2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
-#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
-
-#define  RCC_CFGR_PLLMULL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
-#define  RCC_CFGR_PLLMULL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
-#define  RCC_CFGR_PLLMULL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
-#define  RCC_CFGR_PLLMULL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
-#define  RCC_CFGR_PLLMULL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
-#define  RCC_CFGR_PLLMULL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
-#define  RCC_CFGR_PLLMULL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
-#define  RCC_CFGR_PLLMULL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
-#define  RCC_CFGR_PLLMULL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
-#define  RCC_CFGR_PLLMULL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
-#define  RCC_CFGR_PLLMULL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
-#define  RCC_CFGR_PLLMULL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
-#define  RCC_CFGR_PLLMULL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
-#define  RCC_CFGR_PLLMULL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
-#define  RCC_CFGR_PLLMULL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
-
-/*!< USB configuration */
-#define  RCC_CFGR_USBPRE                     ((uint32_t)0x00400000)        /*!< USB prescaler */
-
-/*!< I2S configuration */
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)        /*!< I2S external clock source selection */
-
-/*!< MCO configuration */
-#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
-#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
-#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
-#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
-#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
-#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
-
-#define  RCC_CFGR_MCOF                       ((uint32_t)0x10000000)        /*!< Microcontroller Clock Output Flag */
-
-/*********************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-/******************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG reset */
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000200)        /*!< TIM1 reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000200)        /*!< TIM8 reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
-#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 reset */
-#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 reset */
-#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 reset */
-
-/******************  Bit definition for RCC_APB1RSTR register  ******************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 reset */
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI3 reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
-#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR reset */
-#define  RCC_APB1RSTR_DACRST                ((uint32_t)0x20000000)         /*!< DAC reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
-#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
-#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
-#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
-#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
-#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
-#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
-#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
-#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
-#define  RCC_AHBENR_TSEN                     ((uint32_t)0x01000000)        /*!< TS clock enable */
-#define  RCC_AHBENR_ADC12EN                  ((uint32_t)0x10000000)        /*!< ADC1/ ADC2 clock enable */
-#define  RCC_AHBENR_ADC34EN                  ((uint32_t)0x20000000)        /*!< ADC1/ ADC2 clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00002000)        /*!< TIM8 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
-#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
-#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
-#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
-
-/******************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI3 clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
-/* CHIBIOS FIX */
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)        /*!< UART 3 clock enable */
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)        /*!< UART 4 clock enable */
-//#define  RCC_APB1ENR_UART3EN                 ((uint32_t)0x00080000)        /*!< UART 3 clock enable */
-//#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00100000)        /*!< UART 4 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
-#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
-
-#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-
-
-#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-/*!< RTC configuration */
-#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
-
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
-#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-/*******************  Bit definition for RCC_AHBRSTR register  ****************/
-#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA reset */
-#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB reset */
-#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC reset */
-#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD reset */
-#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF reset */
-#define  RCC_AHBRSTR_TSRST                   ((uint32_t)0x00100000)         /*!< TS reset */
-#define  RCC_AHBRSTR_ADC12RST                ((uint32_t)0x01000000)         /*!< ADC1 & ADC2 reset */
-#define  RCC_AHBRSTR_ADC34RST                ((uint32_t)0x02000000)         /*!< ADC3 & ADC4 reset */
-
-/*******************  Bit definition for RCC_CFGR2 register  ******************/
-/*!< PREDIV1 configuration */
-#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
-#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
-#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
-#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
-#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
-#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
-#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
-#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
-#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
-#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
-#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
-#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
-#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
-#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
-#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
-#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
-#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
-
-/*!< ADCPRE12 configuration */
-#define  RCC_CFGR2_ADCPRE12                  ((uint32_t)0x000001F0)        /*!< ADCPRE12[8:4] bits */
-#define  RCC_CFGR2_ADCPRE12_0                ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR2_ADCPRE12_1                ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR2_ADCPRE12_2                ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR2_ADCPRE12_3                ((uint32_t)0x00000080)        /*!< Bit 3 */
-#define  RCC_CFGR2_ADCPRE12_4                ((uint32_t)0x00000100)        /*!< Bit 4 */
-
-#define  RCC_CFGR2_ADCPRE12_NO               ((uint32_t)0x00000000)        /*!< ADC12 clock disabled, ADC12 can use AHB clock */
-#define  RCC_CFGR2_ADCPRE12_DIV1             ((uint32_t)0x00000100)        /*!< ADC12 PLL clock divided by 1 */
-#define  RCC_CFGR2_ADCPRE12_DIV2             ((uint32_t)0x00000110)        /*!< ADC12 PLL clock divided by 2 */
-#define  RCC_CFGR2_ADCPRE12_DIV4             ((uint32_t)0x00000120)        /*!< ADC12 PLL clock divided by 4 */
-#define  RCC_CFGR2_ADCPRE12_DIV6             ((uint32_t)0x00000130)        /*!< ADC12 PLL clock divided by 6 */
-#define  RCC_CFGR2_ADCPRE12_DIV8             ((uint32_t)0x00000140)        /*!< ADC12 PLL clock divided by 8 */
-#define  RCC_CFGR2_ADCPRE12_DIV10            ((uint32_t)0x00000150)        /*!< ADC12 PLL clock divided by 10 */
-#define  RCC_CFGR2_ADCPRE12_DIV12            ((uint32_t)0x00000160)        /*!< ADC12 PLL clock divided by 12 */
-#define  RCC_CFGR2_ADCPRE12_DIV16            ((uint32_t)0x00000170)        /*!< ADC12 PLL clock divided by 16 */
-#define  RCC_CFGR2_ADCPRE12_DIV32            ((uint32_t)0x00000180)        /*!< ADC12 PLL clock divided by 32 */
-#define  RCC_CFGR2_ADCPRE12_DIV64            ((uint32_t)0x00000190)        /*!< ADC12 PLL clock divided by 64 */
-#define  RCC_CFGR2_ADCPRE12_DIV128           ((uint32_t)0x000001A0)        /*!< ADC12 PLL clock divided by 128 */
-#define  RCC_CFGR2_ADCPRE12_DIV256           ((uint32_t)0x000001B0)        /*!< ADC12 PLL clock divided by 256 */
-
-/*!< ADCPRE34 configuration */
-#define  RCC_CFGR2_ADCPRE34                  ((uint32_t)0x00003E00)        /*!< ADCPRE34[13:5] bits */
-#define  RCC_CFGR2_ADCPRE34_0                ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  RCC_CFGR2_ADCPRE34_1                ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  RCC_CFGR2_ADCPRE34_2                ((uint32_t)0x00000800)        /*!< Bit 2 */
-#define  RCC_CFGR2_ADCPRE34_3                ((uint32_t)0x00001000)        /*!< Bit 3 */
-#define  RCC_CFGR2_ADCPRE34_4                ((uint32_t)0x00002000)        /*!< Bit 4 */
-
-#define  RCC_CFGR2_ADCPRE34_NO               ((uint32_t)0x00000000)        /*!< ADC34 clock disabled, ADC34 can use AHB clock */
-#define  RCC_CFGR2_ADCPRE34_DIV1             ((uint32_t)0x00002000)        /*!< ADC34 PLL clock divided by 1 */
-#define  RCC_CFGR2_ADCPRE34_DIV2             ((uint32_t)0x00002200)        /*!< ADC34 PLL clock divided by 2 */
-#define  RCC_CFGR2_ADCPRE34_DIV4             ((uint32_t)0x00002400)        /*!< ADC34 PLL clock divided by 4 */
-#define  RCC_CFGR2_ADCPRE34_DIV6             ((uint32_t)0x00002600)        /*!< ADC34 PLL clock divided by 6 */
-#define  RCC_CFGR2_ADCPRE34_DIV8             ((uint32_t)0x00002800)        /*!< ADC34 PLL clock divided by 8 */
-#define  RCC_CFGR2_ADCPRE34_DIV10            ((uint32_t)0x00002A00)        /*!< ADC34 PLL clock divided by 10 */
-#define  RCC_CFGR2_ADCPRE34_DIV12            ((uint32_t)0x00002C00)        /*!< ADC34 PLL clock divided by 12 */
-#define  RCC_CFGR2_ADCPRE34_DIV16            ((uint32_t)0x00002E00)        /*!< ADC34 PLL clock divided by 16 */
-#define  RCC_CFGR2_ADCPRE34_DIV32            ((uint32_t)0x00003000)        /*!< ADC34 PLL clock divided by 32 */
-#define  RCC_CFGR2_ADCPRE34_DIV64            ((uint32_t)0x00003200)        /*!< ADC34 PLL clock divided by 64 */
-#define  RCC_CFGR2_ADCPRE34_DIV128           ((uint32_t)0x00003400)        /*!< ADC34 PLL clock divided by 128 */
-#define  RCC_CFGR2_ADCPRE34_DIV256           ((uint32_t)0x00003600)        /*!< ADC34 PLL clock divided by 256 */
-
-/*******************  Bit definition for RCC_CFGR3 register  ******************/
-#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
-#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR3_I2CSW                     ((uint32_t)0x00000030)        /*!< I2CSW bits */
-#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 
-#define  RCC_CFGR3_I2C2SW                    ((uint32_t)0x00000020)        /*!< I2C2SW bits */
-
-#define  RCC_CFGR3_TIMSW                     ((uint32_t)0x00000300)        /*!< TIMSW bits */
-#define  RCC_CFGR3_TIM1SW                    ((uint32_t)0x00000100)        /*!< TIM1SW bits */ 
-#define  RCC_CFGR3_TIM8SW                    ((uint32_t)0x00000200)        /*!< TIM8SW bits */
-
-#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
-#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
-#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
-
-#define  RCC_CFGR3_UART4SW                   ((uint32_t)0x00300000)        /*!< UART4SW[1:0] bits */
-#define  RCC_CFGR3_UART4SW_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  RCC_CFGR3_UART4SW_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-#define  RCC_CFGR3_UART5SW                   ((uint32_t)0x00C00000)        /*!< UART5SW[1:0] bits */
-#define  RCC_CFGR3_UART5SW_0                 ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define  RCC_CFGR3_UART5SW_1                 ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
-#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
-
-#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
-#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
-#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
-#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
-#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
-#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
-
-#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
-#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
-
-#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
-#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
-#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
-#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
-#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
-#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
-#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
-#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
-
-#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
-
-#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        System Configuration(SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  *****************/
-#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< Bit 1 */
-#define SYSCFG_CFGR1_USB_IT_RMP             ((uint32_t)0x00000020) /*!< USB interrupt remap */
-#define SYSCFG_CFGR1_TIM1_ITR3_RMP          ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
-#define SYSCFG_CFGR1_DAC_TRIG_RMP           ((uint32_t)0x00000080) /*!< DAC Trigger remap */
-#define SYSCFG_CFGR1_ADC24_DMA_RMP          ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
-#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
-#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1_DMA_RMP       ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 DMA remap */
-#define SYSCFG_CFGR1_TIM7DAC2_DMA_RMP       ((uint32_t)0x00004000) /*!< Timer 7 / DAC2 DMA remap */
-#define SYSCFG_CFGR1_I2C_PB6_FMP            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_PB7_FMP            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_PB8_FMP            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_PB9_FMP            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR1_I2C1_FMP               ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR1_I2C2_FMP               ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR1_ENCODER_MODE           ((uint32_t)0x00C00000) /*!< Encoder Mode */
-#define SYSCFG_CFGR1_ENCODER_MODE_0         ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
-#define SYSCFG_CFGR1_ENCODER_MODE_1         ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
-#define SYSCFG_CFGR1_FPU_IE                 ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
-#define SYSCFG_CFGR1_FPU_IE_0               ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
-#define SYSCFG_CFGR1_FPU_IE_1               ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
-#define SYSCFG_CFGR1_FPU_IE_2               ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
-#define SYSCFG_CFGR1_FPU_IE_3               ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
-#define SYSCFG_CFGR1_FPU_IE_4               ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
-#define SYSCFG_CFGR1_FPU_IE_5               ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
-
-/*****************  Bit definition for SYSCFG_RCR register  *******************/
-#define SYSCFG_RCR_PAGE0          ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
-#define SYSCFG_RCR_PAGE1          ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
-#define SYSCFG_RCR_PAGE2          ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
-#define SYSCFG_RCR_PAGE3          ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
-#define SYSCFG_RCR_PAGE4          ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
-#define SYSCFG_RCR_PAGE5          ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
-#define SYSCFG_RCR_PAGE6          ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
-#define SYSCFG_RCR_PAGE7          ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTIRCR_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTIRCR_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTIRCR_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTIRCR_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTIRCR_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTIRCR_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTIRCR_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTIRCR_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTIRCR_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
-#define SYSCFG_EXTIRCR_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTIRCR_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTIRCR_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTIRCR_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTIRCR_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTIRCR_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
-#define SYSCFG_EXTIRCR_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTIRCR_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTIRCR_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTIRCR_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTIRCR_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTIRCR_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
-#define SYSCFG_EXTIRCR_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTIRCR_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTIRCR_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTIRCR_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTIRCR_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTIRCR_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 */
-#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 */
-#define SYSCFG_CFGR2_BYP_ADDR_PAR              ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
-#define SYSCFG_CFGR2_SRAM_PE                   ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
-#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
-#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
-#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
-
-#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CR1_UIFREMAP                    ((uint16_t)0x0800)            /*!<Update interrupt flag remap */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint32_t)0x00000001)            /*!<Capture/Compare Preloaded Control */
-#define  TIM_CR2_CCUS                        ((uint32_t)0x00000004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint32_t)0x00000100)            /*!<Output Idle state 1 (OC1 output) */
-#define  TIM_CR2_OIS1N                       ((uint32_t)0x00000200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint32_t)0x00000400)            /*!<Output Idle state 2 (OC2 output) */
-#define  TIM_CR2_OIS2N                       ((uint32_t)0x00000800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint32_t)0x00001000)            /*!<Output Idle state 3 (OC3 output) */
-#define  TIM_CR2_OIS3N                       ((uint32_t)0x00002000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint32_t)0x00004000)            /*!<Output Idle state 4 (OC4 output) */
-#define  TIM_CR2_OIS5                        ((uint32_t)0x00010000)            /*!<Output Idle state 4 (OC4 output) */
-#define  TIM_CR2_OIS6                        ((uint32_t)0x00020000)            /*!<Output Idle state 4 (OC4 output) */
-
-#define  TIM_CR2_MMS2                        ((uint32_t)0x00F00000)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS2_0                      ((uint32_t)0x00100000)            /*!<Bit 0 */
-#define  TIM_CR2_MMS2_1                      ((uint32_t)0x00200000)            /*!<Bit 1 */
-#define  TIM_CR2_MMS2_2                      ((uint32_t)0x00400000)            /*!<Bit 2 */
-#define  TIM_CR2_MMS2_3                      ((uint32_t)0x00800000)            /*!<Bit 2 */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x00010007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define  TIM_SMCR_SMS_3                      ((uint32_t)0x00010000)            /*!<Bit 3 */
-
-#define  TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
-#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
-#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_COMIF                        ((uint32_t)0x00000020)            /*!<COM interrupt Flag */
-#define  TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_BIF                          ((uint32_t)0x00000080)            /*!<Break interrupt Flag */
-#define  TIM_SR_B2IF                         ((uint32_t)0x00000100)            /*!<Break2 interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */
-#define  TIM_SR_CC5IF                        ((uint32_t)0x00010000)            /*!<Capture/Compare 5 interrupt Flag */
-#define  TIM_SR_CC6IF                        ((uint32_t)0x00020000)            /*!<Capture/Compare 6 interrupt Flag */
-
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint16_t)0x0001)               /*!<Update Generation */
-#define  TIM_EGR_CC1G                        ((uint16_t)0x0002)               /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint16_t)0x0004)               /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint16_t)0x0008)               /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint16_t)0x0010)               /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_COMG                        ((uint16_t)0x0020)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint16_t)0x0040)               /*!<Trigger Generation */
-#define  TIM_EGR_BG                          ((uint16_t)0x0080)               /*!<Break Generation */
-#define  TIM_EGR_B2G                         ((uint16_t)0x0100)               /*!<Break Generation */
-
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x00010070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR1_OC1M_3                    ((uint32_t)0x00010000)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x01007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR1_OC2M_3                    ((uint32_t)0x01000000)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR2_OC3M_3                    ((uint32_t)0x00010000)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR2_OC4M_3                    ((uint32_t)0x00100000)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x00000004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x00000008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint16_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x00000080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x00000400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x00000800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint16_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x00008000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      ((uint32_t)0x00000040)            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */
-#define  TIM_CCER_CC5E                       ((uint32_t)0x00010000)            /*!<Capture/Compare 5 output enable */
-#define  TIM_CCER_CC5P                       ((uint32_t)0x00020000)            /*!<Capture/Compare 5 output Polarity */
-#define  TIM_CCER_CC6E                       ((uint32_t)0x00100000)            /*!<Capture/Compare 6 output enable */
-#define  TIM_CCER_CC6P                       ((uint32_t)0x00200000)            /*!<Capture/Compare 6 output Polarity */
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFFFFF)            /*!<Counter Value */
-#define  TIM_CNT_UIFCPY                      ((uint32_t)0x80000000)                                        /*!<Update interrupt flag copy */
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFFFFF)            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define  TIM_CCR5_CCR5                       ((uint32_t)0xFFFFFFFF)        /*!<Capture/Compare 5 Value */
-#define  TIM_CCR5_GC5C1                      ((uint32_t)0x20000000)        /*!<Group Channel 5 and Channel 1 */
-#define  TIM_CCR5_GC5C2                      ((uint32_t)0x40000000)        /*!<Group Channel 5 and Channel 2 */
-#define  TIM_CCR5_GC5C3                      ((uint32_t)0x80000000)        /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 6 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint32_t)0x000000FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint32_t)0x00000010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint32_t)0x00000020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint32_t)0x00000040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint32_t)0x00000080)            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       ((uint32_t)0x00000300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       ((uint32_t)0x00000400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint32_t)0x00000800)            /*!<Off-State Selection for Run mode */
-#define  TIM_BDTR_BKE                        ((uint32_t)0x00001000)            /*!<Break enable for Break1 */
-#define  TIM_BDTR_BKP                        ((uint32_t)0x00002000)            /*!<Break Polarity for Break1 */
-#define  TIM_BDTR_AOE                        ((uint32_t)0x00004000)            /*!<Automatic Output enable */
-#define  TIM_BDTR_MOE                        ((uint32_t)0x00008000)            /*!<Main Output enable */
-
-#define  TIM_BDTR_BKF                        ((uint32_t)0x000F0000)            /*!<Break Filter for Break1 */
-#define  TIM_BDTR_BK2F                       ((uint32_t)0x00F00000)            /*!<Break Filter for Break2 */
-
-#define  TIM_BDTR_BK2E                       ((uint32_t)0x01000000)            /*!<Break enable for Break2 */
-#define  TIM_BDTR_BK2P                       ((uint32_t)0x02000000)            /*!<Break Polarity for Break2 */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM16_OR register  *********************/
-#define TIM16_OR_TI1_RMP                     ((uint16_t)0x00C0)            /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
-#define TIM16_OR_TI1_RMP_0                   ((uint16_t)0x0040)            /*!<Bit 0 */
-#define TIM16_OR_TI1_RMP_1                   ((uint16_t)0x0080)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM1_OR register  *********************/
-#define TIM1_OR_ETR_RMP                      ((uint16_t)0x000F)            /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
-#define TIM1_OR_ETR_RMP_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define TIM1_OR_ETR_RMP_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-#define TIM1_OR_ETR_RMP_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
-#define TIM1_OR_ETR_RMP_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM8_OR register  *********************/
-#define TIM8_OR_ETR_RMP                      ((uint16_t)0x000F)            /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
-#define TIM8_OR_ETR_RMP_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define TIM8_OR_ETR_RMP_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-#define TIM8_OR_ETR_RMP_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
-#define TIM8_OR_ETR_RMP_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define  TIM_CCMR3_OC5FE                     ((uint32_t)0x00000004)            /*!<Output Compare 5 Fast enable */
-#define  TIM_CCMR3_OC5PE                     ((uint32_t)0x00000008)            /*!<Output Compare 5 Preload enable */
-
-#define  TIM_CCMR3_OC5M                      ((uint32_t)0x00000070)            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
-#define  TIM_CCMR3_OC5M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR3_OC5M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR3_OC5M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR3_OC5M_3                    ((uint32_t)0x00010000)            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC5CE                     ((uint32_t)0x00000080)            /*!<Output Compare 5 Clear Enable */
-
-#define  TIM_CCMR3_OC6FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR3_OC6PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR3_OC6M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR3_OC6M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR3_OC6M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR3_OC6M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR3_OC6M_3                    ((uint32_t)0x00100000)            /*!<Bit 3 */
-
-#define  TIM_CCMR3_OC6CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
-#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
-#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
-#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
-#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
-#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
-#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
-#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
-#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
-#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
-#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
-#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
-#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
-#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
-#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
-#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
-#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
-#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
-#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
-#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
-#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
-#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
-#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
-#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
-#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
-#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
-#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
-#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                     ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
-#define  USART_RQR_SBKRQ                     ((uint16_t)0x0002)                /*!< Send Break Request */
-#define  USART_RQR_MMRQ                      ((uint16_t)0x0004)                /*!< Mute Mode Request */
-#define  USART_RQR_RXFRQ                     ((uint16_t)0x0008)                /*!< Receive Data flush Request */
-#define  USART_RQR_TXFRQ                     ((uint16_t)0x0010)                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
-#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
-#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
-#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
-#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
-#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
-#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
-#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
-#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
-#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
-#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
-#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
-#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
-#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
-#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
-#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
-#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
-#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
-#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
-#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
-#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
-#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
-#define  USART_ICR_NCF                       ((uint32_t)0x00000004)            /*!< Noise detected Clear Flag */
-#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
-#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
-#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
-#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
-#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
-#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
-#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
-#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
-#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-
-#ifdef USE_STDPERIPH_DRIVER
-  #include "stm32f30x_conf.h"
-#endif /* USE_STDPERIPH_DRIVER */
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F30x_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM32F37x/adc_lld.c b/os/hal/platforms/STM32F37x/adc_lld.c
deleted file mode 100644
index 411c3a086..000000000
--- a/os/hal/platforms/STM32F37x/adc_lld.c
+++ /dev/null
@@ -1,741 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F37x/adc_lld.c
- * @brief   STM32F37x ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define SDADC_FORBIDDEN_CR1_FLAGS   (SDADC_CR1_INIT   | SDADC_CR1_RDMAEN |  \
-                                     SDADC_CR1_RSYNC  | SDADC_CR1_JSYNC  |  \
-                                     SDADC_CR1_ROVRIE | SDADC_CR1_REOCIE |  \
-                                     SDADC_CR1_JEOCIE | SDADC_CR1_EOCALIE)
-
-#define SDADC_ENFORCED_CR1_FLAGS    (SDADC_CR1_JDMAEN  | SDADC_CR1_JOVRIE)
-
-#define SDADC_FORBIDDEN_CR2_FLAGS   (SDADC_CR2_RSWSTART   |                 \
-                                     SDADC_CR2_RCONT      |                 \
-                                     SDADC_CR2_RCH        |                 \
-                                     SDADC_CR2_JCONT      |                 \
-                                     SDADC_CR2_STARTCALIB |                 \
-                                     SDADC_CR2_CALIBCNT)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/** @brief SDADC1 driver identifier.*/
-#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__)
-ADCDriver SDADCD1;
-#endif
-
-/** @brief SDADC2 driver identifier.*/
-#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__)
-ADCDriver SDADCD2;
-#endif
-
-/** @brief SDADC3 driver identifier.*/
-#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__)
-ADCDriver SDADCD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static const ADCConfig adc_lld_default_config = {
-#if STM32_ADC_USE_SDADC
-  0,
-  {
-     0,
-     0,
-     0
-  }
-#else /* !STM32_ADC_USE_SDADC */
-  0
-#endif /* !STM32_ADC_USE_SDADC */
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Stops, reconfigures and restarts an ADC/SDADC.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_reconfig(ADCDriver *adcp) {
-
-#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
-  if (adcp->adc != NULL)
-#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
-#if STM32_ADC_USE_ADC
-  {
-    /* ADC initial setup, starting the analog part here in order to reduce
-       the latency when starting a conversion.*/
-    uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE;
-    adcp->adc->CR2 = cr2;
-    adcp->adc->CR1 = 0;
-    adcp->adc->CR2 = cr2 | ADC_CR2_ADON;
-
-  }
-#endif /* STM32_ADC_USE_ADC */
-#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
-  else if (adcp->sdadc != NULL)
-#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
-#if STM32_ADC_USE_SDADC
-  {
-    /* SDADC initial setup, starting the analog part here in order to reduce
-       the latency when starting a conversion.*/
-    adcp->sdadc->CR2    = 0;
-    adcp->sdadc->CR1    = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
-                          ~SDADC_FORBIDDEN_CR1_FLAGS;
-    adcp->sdadc->CONF0R = (adcp->sdadc->CONF0R & SDADC_CONFR_OFFSET_MASK) |
-                          adcp->config->confxr[0];
-    adcp->sdadc->CONF1R = (adcp->sdadc->CONF1R & SDADC_CONFR_OFFSET_MASK) |
-                          adcp->config->confxr[1];
-    adcp->sdadc->CONF2R = (adcp->sdadc->CONF2R & SDADC_CONFR_OFFSET_MASK) |
-                          adcp->config->confxr[2];
-    adcp->sdadc->CR2    = SDADC_CR2_ADON;
-  }
-#endif /* STM32_ADC_USE_SDADC */
-#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
-else {
-    chDbgAssert(FALSE, "adc_lld_start(), #5", "invalid state");
-  }
-#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
-}
-
-/**
- * @brief   ADC DMA ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- *
- * @notapi
- */
-static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    /* DMA, this could help only if the DMA tries to access an unmapped
-       address space or violates alignment rules.*/
-    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
-  }
-  else {
-    /* It is possible that the conversion group has already be reset by the
-       ADC error handler, in this case this interrupt is spurious.*/
-    if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
-        /* Transfer complete processing.*/
-        _adc_isr_full_code(adcp);
-      }
-      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
-    }
-  }
-}
-
-#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
-/**
- * @brief   ADC ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] sr        content of the ISR register
- *
- * @notapi
- */
-static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sr) {
-
-  /* It could be a spurious interrupt caused by overflows after DMA disabling,
-     just ignore it in this case.*/
-  if (adcp->grpp != NULL) {
-    if (sr & ADC_SR_AWD) {
-      /* Analog watchdog error.*/
-      _adc_isr_error_code(adcp, ADC_ERR_AWD1);
-    }
-  }
-}
-#endif /* STM32_ADC_USE_ADC */
-
-#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
-/**
- * @brief   ADC ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] isr       content of the ISR register
- *
- * @notapi
- */
-static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
-
-  /* It could be a spurious interrupt caused by overflows after DMA disabling,
-     just ignore it in this case.*/
-  if (adcp->grpp != NULL) {
-    /* Note, an overflow may occur after the conversion ended before the driver
-       is able to stop the ADC, this is why the DMA channel is checked too.*/
-    if ((isr & SDADC_ISR_JOVRF) &&
-        (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
-      /* ADC overflow condition, this could happen only if the DMA is unable
-         to read data fast enough.*/
-      _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
-    }
-  }
-}
-#endif /* STM32_ADC_USE_SDADC */
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-/**
- * @brief   ADC1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector88) {
-  uint32_t sr;
-
-  CH_IRQ_PROLOGUE();
-
-  sr  = ADC1->SR;
-  ADC1->SR = 0;
-  adc_lld_serve_interrupt(&ADCD1, sr);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__)
-/**
- * @brief   SDADC1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector134) {
-  uint32_t isr;
-
-  CH_IRQ_PROLOGUE();
-
-  isr  = SDADC1->ISR;
-  SDADC1->CLRISR = isr;
-  sdadc_lld_serve_interrupt(&SDADCD1, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_USE_SDADC1 */
-
-#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__)
-/**
- * @brief   SDADC2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector138) {
-  uint32_t isr;
-
-  CH_IRQ_PROLOGUE();
-
-  isr  = SDADC2->ISR;
-  SDADC2->CLRISR = isr;
-  sdadc_lld_serve_interrupt(&SDADCD2, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_USE_SDADC2 */
-
-#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__)
-/**
- * @brief   SDADC3 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector13C) {
-  uint32_t isr;
-
-  CH_IRQ_PROLOGUE();
-
-  isr  = SDADC3->ISR;
-  SDADC3->CLRISR = isr;
-  sdadc_lld_serve_interrupt(&SDADCD3, isr);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_USE_SDADC3 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if STM32_ADC_USE_ADC1
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-  ADCD1.adc     = ADC1;
-#if STM32_ADC_USE_SDADC
-  ADCD1.sdadc   = NULL;
-#endif
-  ADCD1.dmastp  = STM32_DMA1_STREAM1;
-  ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
-                  STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-  nvicEnableVector(ADC1_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_ADC_ADC1_IRQ_PRIORITY));
-#endif
-
-#if STM32_ADC_USE_SDADC1
-  /* Driver initialization.*/
-  adcObjectInit(&SDADCD1);
-#if STM32_ADC_USE_ADC
-  SDADCD1.adc     = NULL;
-#endif
-  SDADCD1.sdadc   = SDADC1;
-  SDADCD1.dmastp  = STM32_DMA2_STREAM3;
-  SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) |
-                  STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-  nvicEnableVector(SDADC1_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY));
-#endif
-
-#if STM32_ADC_USE_SDADC2
-  /* Driver initialization.*/
-  adcObjectInit(&SDADCD2);
-#if STM32_ADC_USE_ADC
-  SDADCD2.adc     = NULL;
-#endif
-  SDADCD2.sdadc   = SDADC2;
-  SDADCD2.dmastp  = STM32_DMA2_STREAM4;
-  SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) |
-                  STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-  nvicEnableVector(SDADC2_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY));
-#endif
-
-#if STM32_ADC_USE_SDADC3
-  /* Driver initialization.*/
-  adcObjectInit(&SDADCD3);
-#if STM32_ADC_USE_ADC
-  SDADCD3.adc     = NULL;
-#endif
-  SDADCD3.sdadc   = SDADC3;
-  SDADCD3.dmastp  = STM32_DMA2_STREAM5;
-  SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) |
-                  STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-  nvicEnableVector(SDADC3_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY));
-#endif
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  if (adcp->config == NULL)
-    adcp->config = &adc_lld_default_config;
-
-  /* If in stopped state then enables the ADC and DMA clocks.*/
-  if (adcp->state == ADC_STOP) {
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-      bool_t b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
-                            (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
-      rccEnableADC1(FALSE);
-    }
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_SDADC1
-    if (&SDADCD1 == adcp) {
-      bool_t b = dmaStreamAllocate(adcp->dmastp,
-                                   STM32_ADC_SDADC1_DMA_IRQ_PRIORITY,
-                                   (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
-                                   (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR);
-      rccEnableSDADC1(FALSE);
-      PWR->CR |= PWR_CR_SDADC1EN;
-      adcp->sdadc->CR2 = 0;
-      adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
-                         ~SDADC_FORBIDDEN_CR1_FLAGS;
-      adcp->sdadc->CR2 = SDADC_CR2_ADON;
-    }
-#endif /* STM32_ADC_USE_SDADC1 */
-
-#if STM32_ADC_USE_SDADC2
-    if (&SDADCD2 == adcp) {
-      bool_t b = dmaStreamAllocate(adcp->dmastp,
-                                   STM32_ADC_SDADC2_DMA_IRQ_PRIORITY,
-                                   (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
-                                   (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR);
-      rccEnableSDADC2(FALSE);
-      PWR->CR |= PWR_CR_SDADC2EN;
-      adcp->sdadc->CR2 = 0;
-      adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
-                         ~SDADC_FORBIDDEN_CR1_FLAGS;
-      adcp->sdadc->CR2 = SDADC_CR2_ADON;
-    }
-#endif /* STM32_ADC_USE_SDADC2 */
-
-#if STM32_ADC_USE_SDADC3
-    if (&SDADCD3 == adcp) {
-      bool_t b = dmaStreamAllocate(adcp->dmastp,
-                                   STM32_ADC_SDADC3_DMA_IRQ_PRIORITY,
-                                   (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
-                                   (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #4", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR);
-      rccEnableSDADC3(FALSE);
-      PWR->CR |= PWR_CR_SDADC3EN;
-      adcp->sdadc->CR2 = 0;
-      adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
-                         ~SDADC_FORBIDDEN_CR1_FLAGS;
-      adcp->sdadc->CR2 = SDADC_CR2_ADON;
-    }
-#endif /* STM32_ADC_USE_SDADC3 */
-  }
-
-  adc_lld_reconfig(adcp);
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  /* If in ready state then disables the ADC clock.*/
-  if (adcp->state == ADC_READY) {
-    dmaStreamRelease(adcp->dmastp);
-
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-      adcp->adc->CR1 = 0;
-      adcp->adc->CR2 = 0;
-      rccDisableADC1(FALSE);
-    }
-#endif
-
-#if STM32_ADC_USE_SDADC1
-    if (&SDADCD1 == adcp) {
-      adcp->sdadc->CR1 = 0;
-      adcp->sdadc->CR2 = 0;
-      rccDisableSDADC1(FALSE);
-      PWR->CR &= ~PWR_CR_SDADC1EN;
-    }
-#endif
-
-#if STM32_ADC_USE_SDADC2
-    if (&SDADCD2 == adcp) {
-      adcp->sdadc->CR1 = 0;
-      adcp->sdadc->CR2 = 0;
-      rccDisableSDADC2(FALSE);
-      PWR->CR &= ~PWR_CR_SDADC2EN;
-    }
-#endif
-
-#if STM32_ADC_USE_SDADC3
-    if (&SDADCD3 == adcp) {
-      adcp->sdadc->CR1 = 0;
-      adcp->sdadc->CR2 = 0;
-      rccDisableSDADC3(FALSE);
-      PWR->CR &= ~PWR_CR_SDADC3EN;
-    }
-#endif
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t mode;
-  const ADCConversionGroup* grpp = adcp->grpp;
-
-  /* DMA setup.*/
-  mode = adcp->dmamode;
-  if (grpp->circular) {
-    mode |= STM32_DMA_CR_CIRC;
-    if (adcp->depth > 1) {
-      /* If circular buffer depth > 1, then the half transfer interrupt
-         is enabled in order to allow streaming processing.*/
-      mode |= STM32_DMA_CR_HTIE;
-    }
-  }
-  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
-  dmaStreamSetTransactionSize(adcp->dmastp,
-			      (uint32_t)grpp->num_channels * 
-			      (uint32_t)adcp->depth);
-  dmaStreamSetMode(adcp->dmastp, mode);
-  dmaStreamEnable(adcp->dmastp);
-
-#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
-  if (adcp->adc != NULL)
-#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
-#if STM32_ADC_USE_ADC
-  {
-    uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE;
-    cr2 |= grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
-    if ((cr2 & ADC_CR2_SWSTART) != 0)
-      cr2 |= ADC_CR2_CONT;
-    adcp->adc->CR2   = cr2;
-
-    /* ADC setup.*/
-    adcp->adc->SR    = 0;
-    adcp->adc->LTR   = grpp->u.adc.ltr;
-    adcp->adc->HTR   = grpp->u.adc.htr;
-    adcp->adc->SMPR1 = grpp->u.adc.smpr[0];
-    adcp->adc->SMPR2 = grpp->u.adc.smpr[1];
-    adcp->adc->SQR1  = grpp->u.adc.sqr[0] |
-                       ADC_SQR1_NUM_CH(grpp->num_channels);
-    adcp->adc->SQR2  = grpp->u.adc.sqr[1];
-    adcp->adc->SQR3  = grpp->u.adc.sqr[2];
-
-    /* ADC conversion start, the start is performed using the method
-       specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
-    adcp->adc->CR1   = grpp->u.adc.cr1 | ADC_CR1_AWDIE | ADC_CR1_SCAN;
-    adcp->adc->CR2   = adcp->adc->CR2;  /* Triggers the conversion start.*/
-  }
-#endif /* STM32_ADC_USE_ADC */
-#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
-  else if (adcp->sdadc != NULL)
-#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
-#if STM32_ADC_USE_SDADC
-  {
-    uint32_t cr2 = (grpp->u.sdadc.cr2 & ~SDADC_FORBIDDEN_CR2_FLAGS) |
-                   SDADC_CR2_ADON;
-    if ((grpp->u.sdadc.cr2 & SDADC_CR2_JSWSTART) != 0)
-      cr2 |= SDADC_CR2_JCONT;
-
-    /* Entering initialization mode.*/
-    adcp->sdadc->CR1 |= SDADC_CR1_INIT;
-    while ((adcp->sdadc->ISR & SDADC_ISR_INITRDY) == 0)
-      ;
-
-    /* SDADC setup.*/
-    adcp->sdadc->JCHGR    = grpp->u.sdadc.jchgr;
-    adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0];
-    adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1];
-
-    /* SDADC trigger modes, this write must be performed when
-       SDADC_CR1_INIT=1.*/
-    adcp->sdadc->CR2 = cr2;
-
-    /* Leaving initialization mode.*/
-    adcp->sdadc->CR1 &= ~SDADC_CR1_INIT;
-
-    /* Special case, if SDADC_CR2_JSWSTART is specified it has to be
-       written after SDADC_CR1_INIT has been set to zero. Just a write is
-       performed, any other bit is ingore if not in initialization mode.*/
-    adcp->sdadc->CR2 = cr2;
-  }
-#endif /* STM32_ADC_USE_SDADC */
-#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
-  else {
-    chDbgAssert(FALSE, "adc_lld_start_conversion(), #1", "invalid state");
-  }
-#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-  /* Disabling the associated DMA stream.*/
-  dmaStreamDisable(adcp->dmastp);
-
-  /* Stopping and restarting the whole ADC, apparently the only way to stop
-     a conversion.*/
-  adc_lld_reconfig(adcp);
-}
-
-/**
- * @brief   Calibrates an ADC unit.
- * @note    The calibration must be performed after calling @p adcStart().
- * @note    For SDADC units it is assumed that the field SDADC_CR2_CALIBCNT
- *          has been
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @api
- */
-void adcSTM32Calibrate(ADCDriver *adcp) {
-
-  chDbgAssert((adcp->state == ADC_READY) ||
-              (adcp->state == ADC_COMPLETE) ||
-              (adcp->state == ADC_ERROR),
-              "adcSTM32Calibrate(), #1", "not ready");
-
-#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
-  if (adcp->adc != NULL)
-#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
-#if STM32_ADC_USE_ADC
-  {
-    /* Resetting calibration just to be safe.*/
-    ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
-    while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
-      ;
-
-    /* Calibration.*/
-    ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
-    while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
-      ;
-  }
-#endif /* STM32_ADC_USE_ADC */
-#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
-  else if (adcp->sdadc != NULL)
-#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
-#if STM32_ADC_USE_SDADC
-  {
-    /* Selecting a full calibration in three steps.*/
-    adcp->sdadc->CR2  = (adcp->sdadc->CR2 & ~SDADC_CR2_CALIBCNT) |
-                        SDADC_CR2_CALIBCNT_1;
-
-    /* Calibration.*/
-    adcp->sdadc->CR2 |= SDADC_CR2_STARTCALIB;
-    while ((adcp->sdadc->ISR & SDADC_ISR_EOCALF) == 0)
-      ;
-
-    /* Clearing the EOCALF flag.*/
-    adcp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF;
-  }
-#endif /* STM32_ADC_USE_SDADC */
-#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
-  else {
-    chDbgAssert(FALSE, "adcSTM32Calibrate(), #2", "invalid state");
-  }
-#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
-}
-
-#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
-/**
- * @brief   Enables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- *          temperature sensor and internal reference voltage.
- * @note    This is an STM32-only functionality.
- *
- * @api
- */
-void adcSTM32EnableTSVREFE(void) {
-
-  ADC1->CR2 |= ADC_CR2_TSVREFE;
-}
-
-/**
- * @brief   Disables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- *          temperature sensor and internal reference voltage.
- * @note    This is an STM32-only functionality.
- *
- * @api
- */
-void adcSTM32DisableTSVREFE(void) {
-
-  ADC1->CR2 &= ~ADC_CR2_TSVREFE;
-}
-
-/**
- * @brief   Enables the VBATE bit.
- * @details The VBATE bit is required in order to sample the VBAT channel.
- * @note    This is an STM32-only functionality.
- *
- * @api
- */
-void adcSTM32EnableVBATE(void) {
-
-  SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT;
-}
-
-/**
- * @brief   Disables the VBATE bit.
- * @details The VBATE bit is required in order to sample the VBAT channel.
- * @note    This is an STM32-only functionality.
- *
- * @api
- */
-void adcSTM32DisableVBATE(void) {
-
-  SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_VBAT;
-}
-#endif /* STM32_ADC_USE_ADC */
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F37x/adc_lld.h b/os/hal/platforms/STM32F37x/adc_lld.h
deleted file mode 100644
index 41b203ac6..000000000
--- a/os/hal/platforms/STM32F37x/adc_lld.h
+++ /dev/null
@@ -1,710 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F37x/adc_lld.h
- * @brief   STM32F37x ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Triggers selection
- * @{
- */
-#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 24) /**< @brief Trigger source.     */
-/** @} */
-
-/**
- * @name    ADC clock divider settings
- * @{
- */
-#define ADC_CCR_ADCPRE_DIV2     0
-#define ADC_CCR_ADCPRE_DIV4     1
-#define ADC_CCR_ADCPRE_DIV6     2
-#define ADC_CCR_ADCPRE_DIV8     3
-/** @} */
-
-/**
- * @name    Available analog channels
- * @{
- */
-#define ADC_CHANNEL_IN0         0   /**< @brief External analog input 0.    */
-#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
-#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
-#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
-#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
-#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
-#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
-#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
-#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
-#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
-#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
-#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
-#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
-#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
-#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
-#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
-#define ADC_CHANNEL_SENSOR      16  /**< @brief Internal temperature sensor.*/
-#define ADC_CHANNEL_VREFINT     17  /**< @brief Internal reference.         */
-#define ADC_CHANNEL_VBAT        18  /**< @brief VBAT.                       */
-/** @} */
-
-/**
- * @name    Sampling rates
- * @{
- */
-#define ADC_SAMPLE_1P5          0   /**< @brief 1.5 cycles sampling time.   */
-#define ADC_SAMPLE_7P5          1   /**< @brief 7.5 cycles sampling time.   */
-#define ADC_SAMPLE_13P5         2   /**< @brief 13.5 cycles sampling time.  */
-#define ADC_SAMPLE_28P5         3   /**< @brief 28.5 cycles sampling time.  */
-#define ADC_SAMPLE_41P5         4   /**< @brief 41.5 cycles sampling time.  */
-#define ADC_SAMPLE_55P5         5   /**< @brief 55.5 cycles sampling time.  */
-#define ADC_SAMPLE_71P5         6   /**< @brief 71.5 cycles sampling time.  */
-#define ADC_SAMPLE_239P5        7   /**< @brief 239.5 cycles sampling time. */
-/** @} */
-
-/**
- * @name    SDADC JCHGR bit definitions
- * @{
- */
-#define SDADC_JCHG_MASK         (511U << 0)
-#define SDADC_JCHG(n)           (1U << (n))
-/** @} */
-
-/**
- * @name    SDADC channels definitions
- * @{
- */
-#define SDADC_CHANNEL_0         SDADC_JCHG(0)
-#define SDADC_CHANNEL_1         SDADC_JCHG(1)
-#define SDADC_CHANNEL_2         SDADC_JCHG(2)
-#define SDADC_CHANNEL_3         SDADC_JCHG(3)
-#define SDADC_CHANNEL_4         SDADC_JCHG(4)
-#define SDADC_CHANNEL_5         SDADC_JCHG(5)
-#define SDADC_CHANNEL_6         SDADC_JCHG(6)
-#define SDADC_CHANNEL_7         SDADC_JCHG(7)
-#define SDADC_CHANNEL_8         SDADC_JCHG(8)
-#define SDADC_CHANNEL_9         SDADC_JCHG(9)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- */
-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1                  FALSE
-#endif
-
-/**
- * @brief   SDADC1 driver enable switch.
- * @details If set to @p TRUE the support for SDADC1 is included.
- */
-#if !defined(STM32_ADC_USE_SDADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_SDADC1                FALSE
-#endif
-
-/**
- * @brief   SDADC2 driver enable switch.
- * @details If set to @p TRUE the support for SDADC2 is included.
- */
-#if !defined(STM32_ADC_USE_SDADC2) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_SDADC2                FALSE
-#endif
-
-/**
- * @brief   SDADC3 driver enable switch.
- * @details If set to @p TRUE the support for SDADC3 is included.
- */
-#if !defined(STM32_ADC_USE_SDADC3) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_SDADC3                FALSE
-#endif
-
-/**
- * @brief   ADC1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_PRIORITY         2
-#endif
-
-/**
- * @brief   SDADC1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_SDADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_SDADC1_DMA_PRIORITY       2
-#endif
-
-/**
- * @brief   SDADC2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_SDADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_SDADC2_DMA_PRIORITY       2
-#endif
-
-/**
- * @brief   SDADC3 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_SDADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_SDADC3_DMA_PRIORITY       2
-#endif
-
-/**
- * @brief   ADC interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_IRQ_PRIORITY         5
-#endif
-
-/**
- * @brief   ADC DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
-#endif
-
-/**
- * @brief   SDADC1 interrupt priority level setting.
- */
-#if !defined(STM32_ADC_SDADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_SDADC1_IRQ_PRIORITY       5
-#endif
-
-/**
- * @brief   SDADC2 interrupt priority level setting.
- */
-#if !defined(STM32_ADC_SDADC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_SDADC2_IRQ_PRIORITY       5
-#endif
-
-/**
- * @brief   SDADC3 interrupt priority level setting.
- */
-#if !defined(STM32_ADC_SDADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_SDADC3_IRQ_PRIORITY       5
-#endif
-
-/**
- * @brief   SDADC1 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY   5
-#endif
-
-/**
- * @brief   SDADC2 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY   5
-#endif
-
-/**
- * @brief   SDADC3 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY   5
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/**
- * @brief   At least an ADC unit is in use.
- */
-#define STM32_ADC_USE_ADC   STM32_ADC_USE_ADC1
-
-/**
- * @brief   At least an SDADC unit is in use.
- */
-#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 ||                        \
-                             STM32_ADC_USE_SDADC2 ||                        \
-                             STM32_ADC_USE_SDADC3)
-
-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
-#error "ADC1 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_SDADC1 && !STM32_HAS_SDADC1
-#error "SDADC1 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_SDADC2 && !STM32_HAS_SDADC2
-#error "SDADC2 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_SDADC3 && !STM32_HAS_SDADC3
-#error "SDADC3 not present in the selected device"
-#endif
-
-#if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC
-#error "ADC driver activated but no ADC/SDADC peripheral assigned"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1 DMA"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_SDADC1 &&                                                 \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SDADC1"
-#endif
-
-#if STM32_ADC_USE_SDADC1 &&                                                 \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SDADC1 DMA"
-#endif
-
-#if STM32_ADC_USE_SDADC1 &&                                                 \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SDADC1"
-#endif
-
-#if STM32_ADC_USE_SDADC2 &&                                                 \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SDADC2"
-#endif
-
-#if STM32_ADC_USE_SDADC2 &&                                                 \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SDADC2 DMA"
-#endif
-
-#if STM32_ADC_USE_SDADC2 &&                                                 \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SDADC2"
-#endif
-
-#if STM32_ADC_USE_SDADC3 &&                                                 \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SDADC3"
-#endif
-
-#if STM32_ADC_USE_SDADC3 &&                                                 \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SDADC3 DMA"
-#endif
-
-#if STM32_ADC_USE_SDADC3 &&                                                 \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to SDADC3"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
-  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
-  ADC_ERR_AWD1 = 2                          /**< Watchdog 1 triggered.      */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    The use of this configuration structure requires knowledge of
- *          STM32 ADC cell registers interface, please refer to the STM32
- *          reference manual for details.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-
-  /**
-   * @brief  Union of ADC and SDADC config parms.  The decision of which struct 
-   *         union to use is determined by the ADCDriver.  If the ADCDriver adc parm
-   *         is not NULL, then use the adc struct, otherwise if the ADCDriver sdadc parm
-   *         is not NULL, then use the sdadc struct.
-   */
-  union { 
-#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
-    struct {
-      /**
-       * @brief   ADC CR1 register initialization data.
-       * @note    All the required bits must be defined into this field except
-       *          @p ADC_CR1_SCAN that is enforced inside the driver.
-       */
-      uint32_t                  cr1;
-      /**
-       * @brief   ADC CR2 register initialization data.
-       * @note    All the required bits must be defined into this field except
-       *          @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
-       *          enforced inside the driver.
-       */
-      uint32_t                  cr2;
-      /**
-       * @brief   ADC LTR register initialization data.
-       */
-      uint32_t                  ltr;
-      /**
-       * @brief   ADC HTR register initialization data.
-       */
-      uint32_t                  htr;
-      /**
-       * @brief   ADC SMPRx registers initialization data.
-       */
-      uint32_t                  smpr[2];
-      /**
-       * @brief   ADC SQRx register initialization data.
-       */
-      uint32_t                  sqr[3];
-    } adc;
-#endif /* STM32_ADC_USE_ADC */
-#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
-    struct {
-      /**
-       * @brief   SDADC CR2 register initialization data.
-       * @note    Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL
-       *          and @p SDADC_CR2_JEXTEN can be specified in this field.
-       */
-      uint32_t                  cr2;
-      /**
-       * @brief   SDADC JCHGR register initialization data.
-       */
-      uint32_t                  jchgr;
-      /**
-       * @brief   SDADC CONFCHxR registers initialization data.
-       */
-      uint32_t                  confchr[2];
-    } sdadc;
-#endif /* STM32_ADC_USE_SDADC */
-  } u;
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-#if STM32_ADC_USE_SDADC
-  /**
-   * @brief   SDADC CR1 register initialization data.
-   */
-  uint32_t                  cr1;
-  /**
-   * @brief   SDADC CONFxR registers initialization data.
-   */
-  uint32_t                  confxr[3];
-#else /* !STM32_ADC_USE_SDADC */
-  uint32_t                  dummy;
-#endif /* !STM32_ADC_USE_SDADC */
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
-  /**
-   * @brief   Pointer to the ADCx registers block.
-   */
-  ADC_TypeDef               *adc;
-#endif
-#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
-  /**
-   * @brief   Pointer to the SDADCx registers block.
-   */
-  SDADC_TypeDef             *sdadc;
-#endif
-  /**
-   * @brief   Pointer to associated DMA channel.
-   */
-  const stm32_dma_stream_t  *dmastp;
-  /**
-   * @brief   DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Sequences building helper macros for ADC
- * @{
- */
-/**
- * @brief   Number of channels in a conversion sequence.
- */
-#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
-#define ADC_SQR1_SQ13_N(n)      ((n) << 0)  /**< @brief 13th channel in seq.*/
-#define ADC_SQR1_SQ14_N(n)      ((n) << 5)  /**< @brief 14th channel in seq.*/
-#define ADC_SQR1_SQ15_N(n)      ((n) << 10) /**< @brief 15th channel in seq.*/
-#define ADC_SQR1_SQ16_N(n)      ((n) << 15) /**< @brief 16th channel in seq.*/
-
-#define ADC_SQR2_SQ7_N(n)       ((n) << 0)  /**< @brief 7th channel in seq. */
-#define ADC_SQR2_SQ8_N(n)       ((n) << 5)  /**< @brief 8th channel in seq. */
-#define ADC_SQR2_SQ9_N(n)       ((n) << 10) /**< @brief 9th channel in seq. */
-#define ADC_SQR2_SQ10_N(n)      ((n) << 15) /**< @brief 10th channel in seq.*/
-#define ADC_SQR2_SQ11_N(n)      ((n) << 20) /**< @brief 11th channel in seq.*/
-#define ADC_SQR2_SQ12_N(n)      ((n) << 25) /**< @brief 12th channel in seq.*/
-
-#define ADC_SQR3_SQ1_N(n)       ((n) << 0)  /**< @brief 1st channel in seq. */
-#define ADC_SQR3_SQ2_N(n)       ((n) << 5)  /**< @brief 2nd channel in seq. */
-#define ADC_SQR3_SQ3_N(n)       ((n) << 10) /**< @brief 3rd channel in seq. */
-#define ADC_SQR3_SQ4_N(n)       ((n) << 15) /**< @brief 4th channel in seq. */
-#define ADC_SQR3_SQ5_N(n)       ((n) << 20) /**< @brief 5th channel in seq. */
-#define ADC_SQR3_SQ6_N(n)       ((n) << 25) /**< @brief 6th channel in seq. */
-/** @} */
-
-/**
- * @name    Sampling rate settings helper macros
- * @{
- */
-#define ADC_SMPR2_SMP_AN0(n)    ((n) << 0)  /**< @brief AN0 sampling time.  */
-#define ADC_SMPR2_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
-#define ADC_SMPR2_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
-#define ADC_SMPR2_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
-#define ADC_SMPR2_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
-#define ADC_SMPR2_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
-#define ADC_SMPR2_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
-#define ADC_SMPR2_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
-#define ADC_SMPR2_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
-#define ADC_SMPR2_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
-
-#define ADC_SMPR1_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
-#define ADC_SMPR1_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
-#define ADC_SMPR1_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
-#define ADC_SMPR1_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
-#define ADC_SMPR1_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
-#define ADC_SMPR1_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
-#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
-                                                 sampling time.             */
-#define ADC_SMPR1_SMP_VREF(n)   ((n) << 21) /**< @brief Voltage Reference
-                                                 sampling time.             */
-#define ADC_SMPR1_SMP_VBAT(n)   ((n) << 24) /**< @brief VBAT sampling time. */
-/** @} */
-
-/**
- * @name    Sequences building helper macros for SDADC
- * @{
- */
-#define SDADC_JCHGR_CH(n)           (1U << (n))
-/** @} */
-
-/**
- * @name    Channel configuration number helper macros for SDADC
- * @{
- */
-#define SDADC_CONFCHR1_CH0(n)       ((n) << 0)
-#define SDADC_CONFCHR1_CH1(n)       ((n) << 4)
-#define SDADC_CONFCHR1_CH2(n)       ((n) << 8)
-#define SDADC_CONFCHR1_CH3(n)       ((n) << 12)
-#define SDADC_CONFCHR1_CH4(n)       ((n) << 16)
-#define SDADC_CONFCHR1_CH5(n)       ((n) << 20)
-#define SDADC_CONFCHR1_CH6(n)       ((n) << 24)
-#define SDADC_CONFCHR1_CH7(n)       ((n) << 28)
-#define SDADC_CONFCHR2_CH8(n)       ((n) << 0)
-/** @} */
-
-/**
- * @name    Configuration registers helper macros for SDADC
- * @{
- */
-#define SDADC_CONFR_OFFSET_MASK     (0xFFFU << 0)
-#define SDADC_CONFR_OFFSET(n)       ((n) << 0)
-#define SDADC_CONFR_GAIN_MASK       (7U << 20)
-#define SDADC_CONFR_GAIN_1X         (0U << 20)
-#define SDADC_CONFR_GAIN_2X         (1U << 20)
-#define SDADC_CONFR_GAIN_4X         (2U << 20)
-#define SDADC_CONFR_GAIN_8X         (3U << 20)
-#define SDADC_CONFR_GAIN_16X        (4U << 20)
-#define SDADC_CONFR_GAIN_32X        (5U << 20)
-#define SDADC_CONFR_GAIN_0P5X       (7U << 20)
-#define SDADC_CONFR_SE_MASK         (3U << 26)
-#define SDADC_CONFR_SE_DIFF         (0U << 26)
-#define SDADC_CONFR_SE_OFFSET       (1U << 26)
-#define SDADC_CONFR_SE_ZERO_VOLT    (3U << 26)
-#define SDADC_CONFR_COMMON_MASK     (3U << 30)
-#define SDADC_CONFR_COMMON_VSSSD    (0U << 30)
-#define SDADC_CONFR_COMMON_VDDSD2   (1U << 30)
-#define SDADC_CONFR_COMMON_VDDSD    (2U << 30)
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#if STM32_ADC_USE_SDADC1 && !defined(__DOXYGEN__)
-extern ADCDriver SDADCD1;
-#endif
-
-#if STM32_ADC_USE_SDADC2 && !defined(__DOXYGEN__)
-extern ADCDriver SDADCD2;
-#endif
-
-#if STM32_ADC_USE_SDADC3 && !defined(__DOXYGEN__)
-extern ADCDriver SDADCD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-  void adcSTM32Calibrate(ADCDriver *adcdp);
-#if STM32_ADC_USE_ADC
-  void adcSTM32EnableTSVREFE(void);
-  void adcSTM32DisableTSVREFE(void);
-  void adcSTM32EnableVBATE(void);
-  void adcSTM32DisableVBATE(void);
-#endif /* STM32_ADC_USE_ADC */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F37x/ext_lld_isr.c b/os/hal/platforms/STM32F37x/ext_lld_isr.c
deleted file mode 100644
index f43f3aecb..000000000
--- a/os/hal/platforms/STM32F37x/ext_lld_isr.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F37x/ext_lld_isr.c
- * @brief   STM32F37x EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if !defined(STM32_DISABLE_EXTI0_HANDLER)
-/**
- * @brief   EXTI[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector58) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 0);
-  EXTD1.config->channels[0].cb(&EXTD1, 0);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI1_HANDLER)
-/**
- * @brief   EXTI[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector5C) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 1);
-  EXTD1.config->channels[1].cb(&EXTD1, 1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI2_HANDLER)
-/**
- * @brief   EXTI[2] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector60) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 2);
-  EXTD1.config->channels[2].cb(&EXTD1, 2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI3_HANDLER)
-/**
- * @brief   EXTI[3] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector64) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 3);
-  EXTD1.config->channels[3].cb(&EXTD1, 3);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI4_HANDLER)
-/**
- * @brief   EXTI[4] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector68) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 4);
-  EXTD1.config->channels[4].cb(&EXTD1, 4);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
-/**
- * @brief   EXTI[5]...EXTI[9] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector9C) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
-  EXTI->PR = pr;
-  if (pr & (1 << 5))
-    EXTD1.config->channels[5].cb(&EXTD1, 5);
-  if (pr & (1 << 6))
-    EXTD1.config->channels[6].cb(&EXTD1, 6);
-  if (pr & (1 << 7))
-    EXTD1.config->channels[7].cb(&EXTD1, 7);
-  if (pr & (1 << 8))
-    EXTD1.config->channels[8].cb(&EXTD1, 8);
-  if (pr & (1 << 9))
-    EXTD1.config->channels[9].cb(&EXTD1, 9);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
-/**
- * @brief   EXTI[10]...EXTI[15] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorE0) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
-                   (1 << 15));
-  EXTI->PR = pr;
-  if (pr & (1 << 10))
-    EXTD1.config->channels[10].cb(&EXTD1, 10);
-  if (pr & (1 << 11))
-    EXTD1.config->channels[11].cb(&EXTD1, 11);
-  if (pr & (1 << 12))
-    EXTD1.config->channels[12].cb(&EXTD1, 12);
-  if (pr & (1 << 13))
-    EXTD1.config->channels[13].cb(&EXTD1, 13);
-  if (pr & (1 << 14))
-    EXTD1.config->channels[14].cb(&EXTD1, 14);
-  if (pr & (1 << 15))
-    EXTD1.config->channels[15].cb(&EXTD1, 15);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI16_HANDLER)
-/**
- * @brief   EXTI[16] interrupt handler (PVD).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector44) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 16);
-  EXTD1.config->channels[16].cb(&EXTD1, 16);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI17_HANDLER)
-/**
- * @brief   EXTI[17] interrupt handler (RTC Alarm).
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorE4) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 17);
-  EXTD1.config->channels[17].cb(&EXTD1, 17);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI18_HANDLER)
-/**
- * @brief   EXTI[18] interrupt handler (USB Wakeup).
- *
- * @isr
- */
-CH_IRQ_HANDLER(VectorE8) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 18);
-  EXTD1.config->channels[18].cb(&EXTD1, 18);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI19_HANDLER)
-/**
- * @brief   EXTI[19] interrupt handler (Tamper TimeStamp).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector48) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 19);
-  EXTD1.config->channels[19].cb(&EXTD1, 19);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI20_HANDLER)
-/**
- * @brief   EXTI[20] interrupt handler (RTC Wakeup).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector4C) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 20);
-  EXTD1.config->channels[20].cb(&EXTD1, 20);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI21_22_HANDLER)
-/**
- * @brief   EXTI[21]..EXTI[22] interrupt handler (COMP1, COMP2).
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector140) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 21) | (1 << 22));
-  EXTI->PR = pr;
-  if (pr & (1 << 21))
-    EXTD1.config->channels[21].cb(&EXTD1, 21);
-  if (pr & (1 << 22))
-    EXTD1.config->channels[22].cb(&EXTD1, 22);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(void) {
-
-  nvicEnableVector(EXTI0_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
-  nvicEnableVector(EXTI1_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
-  nvicEnableVector(EXTI2_TS_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
-  nvicEnableVector(EXTI3_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
-  nvicEnableVector(EXTI4_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
-  nvicEnableVector(EXTI9_5_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
-  nvicEnableVector(EXTI15_10_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
-  nvicEnableVector(PVD_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
-  nvicEnableVector(RTC_Alarm_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
-  nvicEnableVector(USBWakeUp_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
-  nvicEnableVector(TAMPER_STAMP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
-  nvicEnableVector(RTC_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
-  nvicEnableVector(COMP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(void) {
-
-  nvicDisableVector(EXTI0_IRQn);
-  nvicDisableVector(EXTI1_IRQn);
-  nvicDisableVector(EXTI2_TS_IRQn);
-  nvicDisableVector(EXTI3_IRQn);
-  nvicDisableVector(EXTI4_IRQn);
-  nvicDisableVector(EXTI9_5_IRQn);
-  nvicDisableVector(EXTI15_10_IRQn);
-  nvicDisableVector(PVD_IRQn);
-  nvicDisableVector(RTC_Alarm_IRQn);
-  nvicDisableVector(USBWakeUp_IRQn);
-  nvicDisableVector(TAMPER_STAMP_IRQn);
-  nvicDisableVector(RTC_WKUP_IRQn);
-  nvicDisableVector(COMP_IRQn);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F37x/hal_lld.c b/os/hal/platforms/STM32F37x/hal_lld.c
deleted file mode 100644
index ba6100056..000000000
--- a/os/hal/platforms/STM32F37x/hal_lld.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F37x/hal_lld.c
- * @brief   STM32F37x HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes the backup domain.
- * @note    WARNING! Changing clock source impossible without resetting
- *          of the whole BKP domain.
- */
-static void hal_lld_backup_domain_init(void) {
-
-  /* Backup domain access enabled and left open.*/
-  PWR->CR |= PWR_CR_DBP;
-
-  /* Reset BKP domain if different clock source selected.*/
-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
-    /* Backup domain reset.*/
-    RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0;
-  }
-
-  /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-#if defined(STM32_LSE_BYPASS)
-  /* LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
-#else
-  /* No LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
-#endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
-#endif
-
-#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
-  /* If the backup domain hasn't been initialized yet then proceed with
-     initialization.*/
-  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
-    /* Selects clock source.*/
-    RCC->BDCR |= STM32_RTCSEL;
-
-    /* RTC clock enabled.*/
-    RCC->BDCR |= RCC_BDCR_RTCEN;
-  }
-#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* Reset of all peripherals.*/
-  rccResetAPB1(0xFFFFFFFF);
-  rccResetAPB2(0xFFFFFFFF);
-
-  /* SysTick initialization using the system clock.*/
-  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-
-  /* DWT cycle counter enable.*/
-  SCS_DEMCR |= SCS_DEMCR_TRCENA;
-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
-
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(FALSE);
-
-  /* Initializes the backup domain.*/
-  hal_lld_backup_domain_init();
-
-#if defined(STM32_DMA_REQUIRED)
-  dmaInit();
-#endif
-
-  /* Programmable voltage detector enable.*/
-#if STM32_PVD_ENABLE
-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-#endif /* STM32_PVD_ENABLE */
-
-  /* SYSCFG clock enabled here because it is a multi-functional unit shared
-     among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
-}
-
-/**
- * @brief   STM32 clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function should be invoked just after the system reset.
- *
- * @special
- */
-void stm32_clock_init(void) {
-
-#if !STM32_NO_INIT
-  /* HSI setup, it enforces the reset situation in order to handle possible
-     problems with JTAG probes and re-initializations.*/
-  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;                                       /* Wait until HSI is stable.    */
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
-  RCC->CFGR = 0;                            /* CFGR reset value.            */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;                                       /* Waits until HSI is selected. */
-
-#if STM32_HSE_ENABLED
-  /* HSE activation.*/
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
-#else
-  /* No HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON;
-#endif
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;                                       /* Waits until HSE is stable.   */
-#endif
-
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                                       /* Waits until LSI is stable.   */
-#endif
-
-  /* Clock settings.*/
-  RCC->CFGR  = STM32_SDPRE     | STM32_MCOSEL    | STM32_USBPRE    |
-               STM32_PLLMUL    | STM32_PLLSRC    | STM32_ADCPRE    |
-               STM32_PPRE1     | STM32_PPRE2     | STM32_HPRE;
-  RCC->CFGR2 = STM32_PREDIV;
-  RCC->CFGR3 = STM32_USART3SW  | STM32_USART2SW  | STM32_I2C2SW    |
-               STM32_I2C1SW    | STM32_USART1SW;
-
-#if STM32_ACTIVATE_PLL
-  /* PLL activation.*/
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;                                       /* Waits until PLL is stable.   */
-#endif
-
-  /* Flash setup and final clock selection.   */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* Switching to the configured clock source if it is different from HSI.*/
-#if (STM32_SW != STM32_SW_HSI)
-  /* Switches clock source.*/
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;                                       /* Waits selection complete.    */
-#endif
-#endif /* !STM32_NO_INIT */
-}
-
-/** @} */
diff --git a/os/hal/platforms/STM32F37x/hal_lld.h b/os/hal/platforms/STM32F37x/hal_lld.h
deleted file mode 100644
index 12118dca2..000000000
--- a/os/hal/platforms/STM32F37x/hal_lld.h
+++ /dev/null
@@ -1,1025 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F37x/hal_lld.h
- * @brief   STM32F37x HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - STM32_LSECLK.
- *          - STM32_LSEDRV.
- *          - STM32_LSE_BYPASS (optionally).
- *          - STM32_HSECLK.
- *          - STM32_HSE_BYPASS (optionally).
- *          .
- *          One of the following macros must also be defined:
- *          - STM32F37X for Analog & DSP devices.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "stm32.h"
-#include "stm32_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @name    Platform identification
- * @{
- */
-#define PLATFORM_NAME           "STM32F37x Analog & DSP"
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum system clock frequency.
- */
-#define STM32_SYSCLK_MAX        72000000
-
-/**
- * @brief   Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX        32000000
-
-/**
- * @brief   Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN        1000000
-
-/**
- * @brief   Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX        1000000
-
-/**
- * @brief   Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN        32768
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MAX         24000000
-
-/**
- * @brief   Minimum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MIN         1000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MAX        72000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MIN        16000000
-
-/**
- * @brief   Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX         36000000
-
-/**
- * @brief   Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX         72000000
-
-/**
- * @brief   Maximum ADC clock frequency.
- */
-#define STM32_ADCCLK_MAX        14000000
-
-/**
- * @brief   Minimum ADC clock frequency.
- */
-#define STM32_ADCCLK_MIN        6000000
-
-/**
- * @brief   Maximum SDADC clock frequency in fast mode.
- */
-#define STM32_SDADCCLK_FAST_MAX 6000000
-
-/**
- * @brief   Maximum SDADC clock frequency in slow mode.
- */
-#define STM32_SDADCCLK_SLOW_MAX 1500000
-
-/**
- * @brief   Minimum SDADC clock frequency.
- */
-#define STM32_SDADCCLK_MIN      500000
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define STM32_HSICLK            8000000     /**< High speed internal clock. */
-#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
-/** @} */
-
-/**
- * @name    PWR_CR register bits definitions
- * @{
- */
-#define STM32_PLS_MASK          (7U << 5)   /**< PLS bits mask.             */
-#define STM32_PLS_LEV0          (0U << 5)   /**< PVD level 0.               */
-#define STM32_PLS_LEV1          (1U << 5)   /**< PVD level 1.               */
-#define STM32_PLS_LEV2          (2U << 5)   /**< PVD level 2.               */
-#define STM32_PLS_LEV3          (3U << 5)   /**< PVD level 3.               */
-#define STM32_PLS_LEV4          (4U << 5)   /**< PVD level 4.               */
-#define STM32_PLS_LEV5          (5U << 5)   /**< PVD level 5.               */
-#define STM32_PLS_LEV6          (6U << 5)   /**< PVD level 6.               */
-#define STM32_PLS_LEV7          (7U << 5)   /**< PVD level 7.               */
-/** @} */
-
-/**
- * @name    RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_HSI            (0U << 0)   /**< SYSCLK source is HSI.      */
-#define STM32_SW_HSE            (1U << 0)   /**< SYSCLK source is HSE.      */
-#define STM32_SW_PLL            (2U << 0)   /**< SYSCLK source is PLL.      */
-
-#define STM32_HPRE_DIV1         (0U << 4)   /**< SYSCLK divided by 1.       */
-#define STM32_HPRE_DIV2         (8u << 4)   /**< SYSCLK divided by 2.       */
-#define STM32_HPRE_DIV4         (9U << 4)   /**< SYSCLK divided by 4.       */
-#define STM32_HPRE_DIV8         (10U << 4)  /**< SYSCLK divided by 8.       */
-#define STM32_HPRE_DIV16        (11U << 4)  /**< SYSCLK divided by 16.      */
-#define STM32_HPRE_DIV64        (12U << 4)  /**< SYSCLK divided by 64.      */
-#define STM32_HPRE_DIV128       (13U << 4)  /**< SYSCLK divided by 128.     */
-#define STM32_HPRE_DIV256       (14U << 4)  /**< SYSCLK divided by 256.     */
-#define STM32_HPRE_DIV512       (15U << 4)  /**< SYSCLK divided by 512.     */
-
-#define STM32_PPRE1_DIV1        (0U << 8)   /**< HCLK divided by 1.         */
-#define STM32_PPRE1_DIV2        (4U << 8)   /**< HCLK divided by 2.         */
-#define STM32_PPRE1_DIV4        (5U << 8)   /**< HCLK divided by 4.         */
-#define STM32_PPRE1_DIV8        (6U << 8)   /**< HCLK divided by 8.         */
-#define STM32_PPRE1_DIV16       (7U << 8)   /**< HCLK divided by 16.        */
-
-#define STM32_PPRE2_DIV1        (0U << 11)  /**< HCLK divided by 1.         */
-#define STM32_PPRE2_DIV2        (4U << 11)  /**< HCLK divided by 2.         */
-#define STM32_PPRE2_DIV4        (5U << 11)  /**< HCLK divided by 4.         */
-#define STM32_PPRE2_DIV8        (6U << 11)  /**< HCLK divided by 8.         */
-#define STM32_PPRE2_DIV16       (7U << 11)  /**< HCLK divided by 16.        */
-
-#define STM32_ADCPRE_DIV2       (0U << 14)  /**< PPRE2 divided by 2.        */
-#define STM32_ADCPRE_DIV4       (1U << 14)  /**< PPRE2 divided by 4.        */
-#define STM32_ADCPRE_DIV6       (2U << 14)  /**< PPRE2 divided by 6.        */
-#define STM32_ADCPRE_DIV8       (3U << 14)  /**< PPRE2 divided by 8.        */
-
-#define STM32_PLLSRC_HSI        (0U << 16)  /**< PLL clock source is HSI/2. */
-#define STM32_PLLSRC_HSE        (1U << 16)  /**< PLL clock source is
-                                                 HSE/PREDIV.                */
-
-#define STM32_USBPRE_DIV1P5     (0U << 22)  /**< USB clock is PLLCLK/1.5.   */
-#define STM32_USBPRE_DIV1       (1U << 22)  /**< USB clock is PLLCLK/1.     */
-
-#define STM32_MCOSEL_NOCLOCK    (0U << 24)  /**< No clock on MCO pin.       */
-#define STM32_MCOSEL_LSI        (2U << 24)  /**< LSI clock on MCO pin.      */
-#define STM32_MCOSEL_LSE        (3U << 24)  /**< LSE clock on MCO pin.      */
-#define STM32_MCOSEL_SYSCLK     (4U << 24)  /**< SYSCLK on MCO pin.         */
-#define STM32_MCOSEL_HSI        (5U << 24)  /**< HSI clock on MCO pin.      */
-#define STM32_MCOSEL_HSE        (6U << 24)  /**< HSE clock on MCO pin.      */
-#define STM32_MCOSEL_PLLDIV2    (7U << 24)  /**< PLL/2 clock on MCO pin.    */
-
-#define STM32_SDPRE_DIV2        (16U << 27) /**< SYSCLK divided by 2.       */
-#define STM32_SDPRE_DIV4        (17U << 27) /**< SYSCLK divided by 4.       */
-#define STM32_SDPRE_DIV6        (18U << 27) /**< SYSCLK divided by 6.       */
-#define STM32_SDPRE_DIV8        (19U << 27) /**< SYSCLK divided by 8.       */
-#define STM32_SDPRE_DIV10       (20U << 27) /**< SYSCLK divided by 10.      */
-#define STM32_SDPRE_DIV12       (21U << 27) /**< SYSCLK divided by 12.      */
-#define STM32_SDPRE_DIV14       (22U << 27) /**< SYSCLK divided by 14.      */
-#define STM32_SDPRE_DIV16       (23U << 27) /**< SYSCLK divided by 16.      */
-#define STM32_SDPRE_DIV20       (24U << 27) /**< SYSCLK divided by 20.      */
-#define STM32_SDPRE_DIV24       (25U << 27) /**< SYSCLK divided by 24.      */
-#define STM32_SDPRE_DIV28       (26U << 27) /**< SYSCLK divided by 28.      */
-#define STM32_SDPRE_DIV32       (27U << 27) /**< SYSCLK divided by 32.      */
-#define STM32_SDPRE_DIV36       (28U << 27) /**< SYSCLK divided by 36.      */
-#define STM32_SDPRE_DIV40       (29U << 27) /**< SYSCLK divided by 40.      */
-#define STM32_SDPRE_DIV44       (30U << 27) /**< SYSCLK divided by 44.      */
-#define STM32_SDPRE_DIV48       (31U << 27) /**< SYSCLK divided by 48.      */
-/** @} */
-
-/**
- * @name    RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK       (3U << 8)   /**< RTC clock source mask.     */
-#define STM32_RTCSEL_NOCLOCK    (0U << 8)   /**< No clock.                  */
-#define STM32_RTCSEL_LSE        (1U << 8)   /**< LSE used as RTC clock.     */
-#define STM32_RTCSEL_LSI        (2U << 8)   /**< LSI used as RTC clock.     */
-#define STM32_RTCSEL_HSEDIV     (3U << 8)   /**< HSE divided by 32 used as
-                                                 RTC clock.                 */
-/** @} */
-
-/**
- * @name    RCC_CFGR2 register bits definitions
- * @{
- */
-#define STM32_PREDIV_MASK       (15U << 0)  /**< PREDIV divisor mask.       */
-/** @} */
-
-/**
- * @name    RCC_CFGR3 register bits definitions
- * @{
- */
-#define STM32_USART1SW_MASK     (3U << 0)   /**< USART1 clock source mask. */
-#define STM32_USART1SW_PCLK     (0U << 0)   /**< USART1 clock is PCLK.     */
-#define STM32_USART1SW_SYSCLK   (1U << 0)   /**< USART1 clock is SYSCLK.   */
-#define STM32_USART1SW_LSE      (2U << 0)   /**< USART1 clock is LSE.      */
-#define STM32_USART1SW_HSI      (3U << 0)   /**< USART1 clock is HSI.      */
-#define STM32_I2C1SW_MASK       (1U << 4)   /**< I2C1 clock source mask.   */
-#define STM32_I2C1SW_HSI        (0U << 4)   /**< I2C1 clock is HSI.        */
-#define STM32_I2C1SW_SYSCLK     (1U << 4)   /**< I2C1 clock is SYSCLK.     */
-#define STM32_I2C2SW_MASK       (1U << 5)   /**< I2C2 clock source mask.   */
-#define STM32_I2C2SW_HSI        (0U << 5)   /**< I2C2 clock is HSI.        */
-#define STM32_I2C2SW_SYSCLK     (1U << 5)   /**< I2C2 clock is SYSCLK.     */
-#define STM32_USART2SW_MASK     (3U << 16)  /**< USART2 clock source mask. */
-#define STM32_USART2SW_PCLK     (0U << 16)  /**< USART2 clock is PCLK.     */
-#define STM32_USART2SW_SYSCLK   (1U << 16)  /**< USART2 clock is SYSCLK.   */
-#define STM32_USART2SW_LSE      (2U << 16)  /**< USART2 clock is LSE.      */
-#define STM32_USART2SW_HSI      (3U << 16)  /**< USART2 clock is HSI.      */
-#define STM32_USART3SW_MASK     (3U << 18)  /**< USART3 clock source mask. */
-#define STM32_USART3SW_PCLK     (0U << 18)  /**< USART3 clock is PCLK.     */
-#define STM32_USART3SW_SYSCLK   (1U << 18)  /**< USART3 clock is SYSCLK.   */
-#define STM32_USART3SW_LSE      (2U << 18)  /**< USART3 clock is LSE.      */
-#define STM32_USART3SW_HSI      (3U << 18)  /**< USART3 clock is HSI.      */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Disables the PWR/RCC initialization in the HAL.
- */
-#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT                       FALSE
-#endif
-
-/**
- * @brief   Enables or disables the programmable voltage detector.
- */
-#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE                    FALSE
-#endif
-
-/**
- * @brief   Sets voltage level for programmable voltage detector.
- */
-#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS                           STM32_PLS_LEV0
-#endif
-
-/**
- * @brief   Enables or disables the HSI clock source.
- */
-#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI_ENABLED                   TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSI clock source.
- */
-#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED                   TRUE
-#endif
-
-/**
- * @brief   Enables or disables the HSE clock source.
- */
-#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED                   TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSE clock source.
- */
-#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED                   FALSE
-#endif
-
-/**
- * @brief   Main clock source selection.
- * @note    If the selected clock source is not the PLL then the PLL is not
- *          initialized and started.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW                            STM32_SW_PLL
-#endif
-
-/**
- * @brief   Clock source for the PLL.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                        STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief   Crystal PLL pre-divider.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
-#define STM32_PREDIV_VALUE                  1
-#endif
-
-/**
- * @brief   PLL multiplier value.
- * @note    The allowed range is 2...16.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE                  9
-#endif
-
-/**
- * @brief   AHB prescaler value.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE                          STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief   APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1                         STM32_PPRE1_DIV2
-#endif
-
-/**
- * @brief   APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2                         STM32_PPRE2_DIV2
-#endif
-
-/**
- * @brief   MCO pin setting.
- */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
-#endif
-
-/**
- * @brief   ADC prescaler value.
- */
-#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADCPRE                        STM32_ADCPRE_DIV4
-#endif
-
-/**
- * @brief   SDADC prescaler value.
- */
-#if !defined(STM32_SDPRE) || defined(__DOXYGEN__)
-#define STM32_SDPRE                         STM32_SDPRE_DIV12
-#endif
-
-/**
- * @brief   USART1 clock source.
- */
-#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
-#define STM32_USART1SW                      STM32_USART1SW_PCLK
-#endif
-
-/**
- * @brief   USART2 clock source.
- */
-#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
-#define STM32_USART2SW                      STM32_USART2SW_PCLK
-#endif
-
-/**
- * @brief   USART3 clock source.
- */
-#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
-#define STM32_USART3SW                      STM32_USART3SW_PCLK
-#endif
-
-/**
- * @brief   I2C1 clock source.
- */
-#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
-#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK
-#endif
-
-/**
- * @brief   I2C2 clock source.
- */
-#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
-#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK
-#endif
-
-/**
- * @brief   RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL                        STM32_RTCSEL_LSI
-#endif
-
-/**
- * @brief   USB clock setting.
- */
-#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
-#define STM32_USB_CLOCK_REQUIRED            TRUE
-#endif
-
-/**
- * @brief   USB prescaler initialization.
- */
-#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
-#define STM32_USBPRE                        STM32_USBPRE_DIV1P5
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F37x_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F37x_MCUCONF not defined"
-#endif
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if STM32_USART1SW == STM32_USART1SW_HSI
-#error "HSI not enabled, required by STM32_USART1SW"
-#endif
-
-#if STM32_USART2SW == STM32_USART2SW_HSI
-#error "HSI not enabled, required by STM32_USART2SW"
-#endif
-
-#if STM32_USART3SW == STM32_USART3SW_HSI
-#error "HSI not enabled, required by STM32_USART3SW"
-#endif
-
-#if STM32_I2C1SW == STM32_I2C1SW_HSI
-#error "HSI not enabled, required by STM32_I2C1SW"
-#endif
-
-#if STM32_I2C2SW == STM32_I2C2SW_HSI
-#error "HSI not enabled, required by STM32_I2C2SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCOSEL"
-#endif
-
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCOSEL"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSI
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0)
-#error "STM32_LSECLK not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#if !defined(STM32_LSEDRV)
-#error "STM32_LSEDRV not defined"
-#endif
-
-#if (STM32_LSEDRV >> 3) > 3
-#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
-#endif
-
-#if STM32_USART1SW == STM32_USART1SW_LSE
-#error "LSE not enabled, required by STM32_USART1SW"
-#endif
-
-#if STM32_USART2SW == STM32_USART2SW_LSE
-#error "LSE not enabled, required by STM32_USART2SW"
-#endif
-
-#if STM32_USART3SW == STM32_USART3SW_LSE
-#error "LSE not enabled, required by STM32_USART3SW"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/* PLL activation conditions.*/
-#if (STM32_SW == STM32_SW_PLL) ||                                           \
-    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
-    STM32_USB_CLOCK_REQUIRED ||                                             \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL          TRUE
-#else
-#define STM32_ACTIVATE_PLL          FALSE
-#endif
-
-/* HSE prescaler setting check.*/
-#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
-#define STM32_PREDIV                ((STM32_PREDIV_VALUE - 1) << 0)
-#else
-#error "invalid STM32_PREDIV value specified"
-#endif
-
-/**
- * @brief   PLLMUL field.
- */
-#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
-    defined(__DOXYGEN__)
-#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
-#else
-#error "invalid STM32_PLLMUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PREDIV_VALUE)
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/* PLL input frequency range check.*/
-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
-#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
-#endif
-
-/**
- * @brief   System clock source.
- */
-#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
-#define STM32_SYSCLK                STM32_PLLCLKOUT
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/* AHB frequency check.*/
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                  (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                  (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                  (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                  (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                  (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/* APB1 frequency check.*/
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief   APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                  (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                  (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                  (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                  (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                  (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/**
- * @brief   RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                (STM32_HSECLK / 32)
-#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
-#define STM32_RTCCLK                0
-#else
-#error "invalid source selected for RTC clock"
-#endif
-
-/**
- * @brief   ADC frequency.
- */
-#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_ADCCLK                (STM32_PCLK2 / 2)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
-#define STM32_ADCCLK                (STM32_PCLK2 / 4)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
-#define STM32_ADCCLK                (STM32_PCLK2 / 6)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
-#define STM32_ADCCLK                (STM32_PCLK2 / 8)
-#else
-#error "invalid STM32_ADCPRE value specified"
-#endif
-
-/* ADC maximum frequency check.*/
-#if STM32_ADCCLK > STM32_ADCCLK_MAX
-#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/* ADC minimum frequency check.*/
-#if STM32_ADCCLK < STM32_ADCCLK_MIN
-#error "STM32_ADCCLK exceeding minimum frequency (STM32_ADCCLK_MIN)"
-#endif
-
-/**
- * @brief   SDADC frequency.
- */
-#if (STM32_SDPRE == STM32_SDPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 2)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV4) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 4)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV6) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 6)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV8) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 8)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV10) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 10)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV12) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 12)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV14) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 14)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV16) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 16)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV20) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 20)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV24) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 24)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV28) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 28)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV32) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 32)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV36) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 36)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV40) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 40)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV44) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 44)
-#elif (STM32_SDPRE == STM32_SDPRE_DIV48) || defined(__DOXYGEN__)
-#define STM32_SDADCCLK              (STM32_SYSCLK / 48)
-#else
-#error "invalid STM32_SDPRE value specified"
-#endif
-
-/* SDADC maximum frequency check.*/
-#if STM32_SDADCCLK > STM32_SDADCCLK_FAST_MAX
-#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_FAST_MAX)"
-#endif
-
-/* SDADC minimum frequency check.*/
-#if STM32_SDADCCLK < STM32_SDADCCLK_MIN
-#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_MIN)"
-#endif
-
-/**
- * @brief   I2C1 frequency.
- */
-#if STM32_I2C1SW == STM32_I2C1SW_HSI
-#define STM32_I2C1CLK               STM32_HSICLK
-#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
-#define STM32_I2C1CLK               STM32_SYSCLK
-#else
-#error "invalid source selected for I2C1 clock"
-#endif
-
-/**
- * @brief   I2C2 frequency.
- */
-#if STM32_I2C2SW == STM32_I2C2SW_HSI
-#define STM32_I2C2CLK               STM32_HSICLK
-#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK
-#define STM32_I2C2CLK               STM32_SYSCLK
-#else
-#error "invalid source selected for I2C2 clock"
-#endif
-
-/**
- * @brief   USART1 frequency.
- */
-#if STM32_USART1SW == STM32_USART1SW_PCLK
-#define STM32_USART1CLK             STM32_PCLK2
-#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
-#define STM32_USART1CLK             STM32_SYSCLK
-#elif STM32_USART1SW == STM32_USART1SW_LSECLK
-#define STM32_USART1CLK             STM32_LSECLK
-#elif STM32_USART1SW == STM32_USART1SW_HSICLK
-#define STM32_USART1CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART1 clock"
-#endif
-
-/**
- * @brief   USART2 frequency.
- */
-#if STM32_USART2SW == STM32_USART2SW_PCLK
-#define STM32_USART2CLK             STM32_PCLK1
-#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
-#define STM32_USART2CLK             STM32_SYSCLK
-#elif STM32_USART2SW == STM32_USART2SW_LSECLK
-#define STM32_USART2CLK             STM32_LSECLK
-#elif STM32_USART2SW == STM32_USART2SW_HSICLK
-#define STM32_USART2CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART2 clock"
-#endif
-
-/**
- * @brief   USART3 frequency.
- */
-#if STM32_USART3SW == STM32_USART3SW_PCLK
-#define STM32_USART3CLK             STM32_PCLK1
-#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
-#define STM32_USART3CLK             STM32_SYSCLK
-#elif STM32_USART3SW == STM32_USART3SW_LSECLK
-#define STM32_USART3CLK             STM32_LSECLK
-#elif STM32_USART3SW == STM32_USART3SW_HSICLK
-#define STM32_USART3CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART3 clock"
-#endif
-
-/**
- * @brief   Timers 2, 3, 4, 5, 6, 7, 12, 13, 14, 18 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief   Timers 15, 16, 17, 19 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
-#endif
-
-/**
- * @brief   USB frequency.
- */
-#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
-#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
-#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
-#define STM32_USBCLK                STM32_PLLCLKOUT
-#else
-#error "invalid STM32_USBPRE value specified"
-#endif
-
-/**
- * @brief   Flash settings.
- */
-#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS             0x00000010
-#elif STM32_HCLK <= 48000000
-#define STM32_FLASHBITS             0x00000011
-#else
-#define STM32_FLASHBITS             0x00000012
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief   Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This service is implemented by returning the content of the
- *          DWT_CYCCNT register.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value()         DWT_CYCCNT
-
-/**
- * @brief   Realtime counter frequency.
- * @note    The DWT_CYCCNT register is incremented directly by the system
- *          clock so this function returns STM32_HCLK.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency()     STM32_HCLK
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-/* STM32 ISR, DMA and RCC helpers.*/
-#include "stm32_isr.h"
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void stm32_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F37x/platform.mk b/os/hal/platforms/STM32F37x/platform.mk
deleted file mode 100644
index 8fd96632c..000000000
--- a/os/hal/platforms/STM32F37x/platform.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-# List of all the STM32F37x platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F37x/stm32_dma.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F37x/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F37x/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F37x/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F37x \
-              ${CHIBIOS}/os/hal/platforms/STM32 \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USBv1
diff --git a/os/hal/platforms/STM32F37x/stm32_dma.c b/os/hal/platforms/STM32F37x/stm32_dma.c
deleted file mode 100644
index 7cfabfe72..000000000
--- a/os/hal/platforms/STM32F37x/stm32_dma.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F37x/stm32_dma.c
- * @brief   DMA helper driver code.
- *
- * @addtogroup STM32F37x_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- *          shared resource, this driver allows to allocate and free DMA
- *          streams at runtime in order to allow all the other device
- *          drivers to coordinate the access to the resource.
- * @note    The DMA ISR handlers are all declared into this module because
- *          sharing, the various device drivers can associate a callback to
- *          ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
-   has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK     0x0000007F
-
-/**
- * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK     0x00000F80
-
-/**
- * @brief   Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE   0x00000000
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- *          identifier and the involved physical registers.
- * @note    Don't use this array directly, use the appropriate wrapper macros
- *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
-  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
-  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
-  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
-  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
-  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
-  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
-  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
-  {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
-  {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
-  {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
-  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
-  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
-};
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DMA ISR redirector type.
- */
-typedef struct {
-  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
-  void                  *dma_param;     /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief   Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief   DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector6C) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 0;
-  if (dma_isr_redir[0].dma_func)
-    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector70) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 4;
-  if (dma_isr_redir[1].dma_func)
-    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector74) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 8;
-  if (dma_isr_redir[2].dma_func)
-    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector78) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 12;
-  if (dma_isr_redir[3].dma_func)
-    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector7C) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 16;
-  if (dma_isr_redir[4].dma_func)
-    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector80) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 20;
-  if (dma_isr_redir[5].dma_func)
-    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector84) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 24;
-  if (dma_isr_redir[6].dma_func)
-    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector120) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 0;
-  if (dma_isr_redir[7].dma_func)
-    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector124) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 4;
-  if (dma_isr_redir[8].dma_func)
-    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector128) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 8;
-  if (dma_isr_redir[9].dma_func)
-    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector12C) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 12;
-  if (dma_isr_redir[10].dma_func)
-    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector130) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 16;
-  if (dma_isr_redir[11].dma_func)
-    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
-  int i;
-
-  dma_streams_mask = 0;
-  for (i = 0; i < STM32_DMA_STREAMS; i++) {
-    _stm32_dma_streams[i].channel->CCR = 0;
-    dma_isr_redir[i].dma_func = NULL;
-  }
-  DMA1->IFCR = 0xFFFFFFFF;
-#if STM32_HAS_DMA2
-  DMA2->IFCR = 0xFFFFFFFF;
-#endif
-}
-
-/**
- * @brief   Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- *          The function also enables the IRQ vector associated to the stream
- *          and initializes its priority.
- * @pre     The stream must not be already in use or an error is returned.
- * @post    The stream is allocated and the default ISR handler redirected
- *          to the specified function.
- * @post    The stream ISR vector is enabled and its priority configured.
- * @post    The stream must be freed using @p dmaStreamRelease() before it can
- *          be reused with another peripheral.
- * @post    The stream is in its post-reset state.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] priority  IRQ priority mask for the DMA stream
- * @param[in] func      handling function pointer, can be @p NULL
- * @param[in] param     a parameter to be passed to the handling function
- * @return              The operation status.
- * @retval FALSE        no error, stream taken.
- * @retval TRUE         error, stream already taken.
- *
- * @special
- */
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                         uint32_t priority,
-                         stm32_dmaisr_t func,
-                         void *param) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
-
-  /* Checks if the stream is already taken.*/
-  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
-    return TRUE;
-
-  /* Marks the stream as allocated.*/
-  dma_isr_redir[dmastp->selfindex].dma_func  = func;
-  dma_isr_redir[dmastp->selfindex].dma_param = param;
-  dma_streams_mask |= (1 << dmastp->selfindex);
-
-  /* Enabling DMA clocks required by the current streams set.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
-    rccEnableDMA1(FALSE);
-#if STM32_HAS_DMA2
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
-    rccEnableDMA2(FALSE);
-#endif
-
-  /* Putting the stream in a safe state.*/
-  dmaStreamDisable(dmastp);
-  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
-
-  /* Enables the associated IRQ vector if a callback is defined.*/
-  if (func != NULL)
-    nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
-
-  return FALSE;
-}
-
-/**
- * @brief   Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- *          Trying to release a unallocated stream is an illegal operation
- *          and is trapped if assertions are enabled.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    The stream is again available.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamRelease");
-
-  /* Check if the streams is not taken.*/
-  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
-              "dmaStreamRelease(), #1", "not allocated");
-
-  /* Disables the associated IRQ vector.*/
-  nvicDisableVector(dmastp->vector);
-
-  /* Marks the stream as not allocated.*/
-  dma_streams_mask &= ~(1 << dmastp->selfindex);
-
-  /* Shutting down clocks that are no more required, if any.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
-    rccDisableDMA1(FALSE);
-#if STM32_HAS_DMA2
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
-    rccDisableDMA2(FALSE);
-#endif
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F37x/stm32_dma.h b/os/hal/platforms/STM32F37x/stm32_dma.h
deleted file mode 100644
index 79d295598..000000000
--- a/os/hal/platforms/STM32F37x/stm32_dma.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F37x/stm32_dma.h
- * @brief   DMA helper driver header.
- * @note    This file requires definitions from the ST header file stm32f30x.h.
- * @note    This driver uses the new naming convention used for the STM32F2xx
- *          so the "DMA channels" are referred as "DMA streams".
- *
- * @addtogroup STM32F37x_DMA
- * @{
- */
-
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Total number of DMA streams.
- * @note    This is the total number of streams among all the DMA units.
- */
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
-#define STM32_DMA_STREAMS           12
-#else
-#define STM32_DMA_STREAMS           7
-#endif
-
-/**
- * @brief   Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK          0x0F
-
-/**
- * @brief   Returns the channel associated to the specified stream.
- *
- * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
- * @param[in] c         a stream/channel association word, one channel per
- *                      nibble, not associated channels must be set to 0xF
- * @return              Always zero, in this platform there is no dynamic
- *                      association between streams and channels.
- */
-#define STM32_DMA_GETCHANNEL(n, c)  0
-
-/**
- * @brief   Checks if a DMA priority is within the valid range.
- * @param[in] prio      DMA priority
- *
- * @retval              The check result.
- * @retval FALSE        invalid DMA priority.
- * @retval TRUE         correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
-
-/**
- * @brief   Returns an unique numeric identifier for a DMA stream.
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              An unique numeric stream identifier.
- */
-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
-
-/**
- * @brief   Returns a DMA stream identifier mask.
- *
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              A DMA stream identifier mask.
- */
-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
-  (1 << STM32_DMA_STREAM_ID(dma, stream))
-
-/**
- * @brief   Checks if a DMA stream unique identifier belongs to a mask.
- * @param[in] id        the stream numeric identifier
- * @param[in] mask      the stream numeric identifiers mask
- *
- * @retval              The check result.
- * @retval FALSE        id does not belong to the mask.
- * @retval TRUE         id belongs to the mask.
- */
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
-
-/**
- * @name    DMA streams identifiers
- * @{
- */
-/**
- * @brief   Returns a pointer to a stm32_dma_stream_t structure.
- *
- * @param[in] id        the stream numeric identifier
- * @return              A pointer to the stm32_dma_stream_t constant structure
- *                      associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
-#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
-#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
-#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(7)
-#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(8)
-#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(9)
-#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(10)
-#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(11)
-/** @} */
-
-/**
- * @name    CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN             DMA_CCR_EN
-#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE
-#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE
-#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE
-#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
-#define STM32_DMA_CR_DIR_P2M        0
-#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR
-#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM
-#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC
-#define STM32_DMA_CR_PINC           DMA_CCR_PINC
-#define STM32_DMA_CR_MINC           DMA_CCR_MINC
-#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE     0
-#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE     0
-#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
-                                     STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
-#define STM32_DMA_CR_PL(n)          ((n) << 12)
-/** @} */
-
-/**
- * @name    CR register constants only found in enhanced DMA
- * @{
- */
-#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
-/** @} */
-
-/**
- * @name    Status flags passed to the ISR callbacks
- * @{
- */
-#define STM32_DMA_ISR_FEIF          0
-#define STM32_DMA_ISR_DMEIF         0
-#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
-#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
-#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA stream descriptor structure.
- */
-typedef struct {
-  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
-  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
-  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
-                                             register.                      */
-  uint8_t               selfindex;      /**< @brief Index to self in array. */
-  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
-} stm32_dma_stream_t;
-
-/**
- * @brief   STM32 DMA ISR function type.
- *
- * @param[in] p         parameter for the registered function
- * @param[in] flags     pre-shifted content of the ISR register, the bits
- *                      are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Associates a peripheral data register to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CPAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) {                              \
-  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Associates a memory destination to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CMAR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) {                                 \
-  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Sets the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] size      value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) {                         \
-  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
-}
-
-/**
- * @brief   Returns the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @return              The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
-
-/**
- * @brief   Programs the stream mode settings.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) {                                    \
-  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
-}
-
-/**
- * @brief   DMA stream enable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) {                                           \
-  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
-}
-
-/**
- * @brief   DMA stream disable.
- * @details The function disables the specified stream and then clears any
- *          pending interrupt.
- * @note    This function can be invoked in both ISR or thread context.
- * @note    Interrupts enabling flags are set to zero after this call, see
- *          bug 3607518.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) {                                          \
-  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
-                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
-  dmaStreamClearInterrupt(dmastp);                                          \
-}
-
-/**
- * @brief   DMA stream interrupt sources clear.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) {                                   \
-  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
-}
-
-/**
- * @brief   Starts a memory to memory operation using the specified stream.
- * @note    The default transfer data mode is "byte to byte" but it can be
- *          changed by specifying extra options in the @p mode parameter.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register, this value
- *                      is implicitly ORed with:
- *                      - @p STM32_DMA_CR_MINC
- *                      - @p STM32_DMA_CR_PINC
- *                      - @p STM32_DMA_CR_DIR_M2M
- *                      - @p STM32_DMA_CR_EN
- *                      .
- * @param[in] src       source address
- * @param[in] dst       destination address
- * @param[in] n         number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
-  dmaStreamSetPeripheral(dmastp, src);                                      \
-  dmaStreamSetMemory0(dmastp, dst);                                         \
-  dmaStreamSetTransactionSize(dmastp, n);                                   \
-  dmaStreamSetMode(dmastp, (mode) |                                         \
-                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
-                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
-}
-
-/**
- * @brief   Polled wait for DMA transfer end.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) {                                         \
-  while ((dmastp)->channel->CNDTR > 0)                                      \
-    ;                                                                       \
-  dmaStreamDisable(dmastp);                                                 \
-}
-
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dmaInit(void);
-  bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                           uint32_t priority,
-                           stm32_dmaisr_t func,
-                           void *param);
-  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F37x/stm32_registry.h b/os/hal/platforms/STM32F37x/stm32_registry.h
deleted file mode 100644
index 0adb93d9f..000000000
--- a/os/hal/platforms/STM32F37x/stm32_registry.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F37x/stm32_registry.h
- * @brief   STM32F37x capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _STM32_REGISTRY_H_
-#define _STM32_REGISTRY_H_
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    STM32F37x capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_ADC1_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC2          FALSE
-#define STM32_ADC2_DMA_MSK      0
-#define STM32_ADC2_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC3          FALSE
-#define STM32_ADC3_DMA_MSK      0
-#define STM32_ADC3_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC4          FALSE
-#define STM32_ADC4_DMA_MSK      0
-#define STM32_ADC4_DMA_CHN      0x00000000
-
-#define STM32_HAS_SDADC1        TRUE
-#define STM32_SDADC1_DMA_MSK    (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SDADC1_DMA_CHN    0x00000000
-
-#define STM32_HAS_SDADC2        TRUE
-#define STM32_SDADC2_DMA_MSK    (STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SDADC2_DMA_CHN    0x00000000
-
-#define STM32_HAS_SDADC3        TRUE
-#define STM32_SDADC3_DMA_MSK    (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SDADC3_DMA_CHN    0x00000000
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          TRUE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 29
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         TRUE
-#define STM32_HAS_GPIOF         TRUE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_I2C3_RX_DMA_MSK   0
-#define STM32_I2C3_RX_DMA_CHN   0x00000000
-#define STM32_I2C3_TX_DMA_MSK   0
-#define STM32_I2C3_TX_DMA_CHN   0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_IS_CALENDAR   TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          TRUE
-#define STM32_SPI3_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 1)
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 2)
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI4          FALSE
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          FALSE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          TRUE
-#define STM32_HAS_TIM5          TRUE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          TRUE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         TRUE
-#define STM32_HAS_TIM13         TRUE
-#define STM32_HAS_TIM14         TRUE
-#define STM32_HAS_TIM15         TRUE
-#define STM32_HAS_TIM16         TRUE
-#define STM32_HAS_TIM17         TRUE
-#define STM32_HAS_TIM18         TRUE
-#define STM32_HAS_TIM19         TRUE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         FALSE
-#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         FALSE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           TRUE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-
-#endif /* _STM32_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F37x/stm32f37x.h b/os/hal/platforms/STM32F37x/stm32f37x.h
deleted file mode 100644
index d9b8d66ec..000000000
--- a/os/hal/platforms/STM32F37x/stm32f37x.h
+++ /dev/null
@@ -1,5442 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f37x.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    20-September-2012
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral registers definitions, bits 
-  *          definitions and memory mapping for STM32F37x devices.
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral�s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral�s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_STDPERIPH_DRIVER"
-  *              - To change few application-specific parameters such as the HSE 
-  *                crystal frequency
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral registers declarations and bits definition
-  *           - Macros to access peripheral registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
-  * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f37x
-  * @{
-  */
-    
-#ifndef __STM32F37x_H
-#define __STM32F37x_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32F37X) 
-  #define STM32F37X
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-
-#if !defined (STM32F37X)
- #error "Please select first the target STM32F37X device used in your application (in stm32f37x.h file)"
-#endif
-
-#if !defined  (USE_STDPERIPH_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_STDPERIPH_DRIVER*/
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application 
-   
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */           
-#if !defined  (HSE_VALUE) 
- #define HSE_VALUE            ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-   Timeout value 
-   */
-#if !defined  (HSE_STARTUP_TIMEOUT) 
- #define HSE_STARTUP_TIMEOUT  ((uint16_t)0x0500)   /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-   Timeout value 
-   */
-#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
-
-#if !defined  (HSI_VALUE) 
- #define HSI_VALUE  ((uint32_t)8000000)
-#endif /* HSI_VALUE */                      /*!< Value of the Internal High Speed oscillator in Hz.
-                                            The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)40000)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */     
-
-/**
- * @brief STM32F37x Standard Peripherals Library version number V1.0.0
-   */
-#define __STM32F37X_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
-#define __STM32F37X_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32F37X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F37X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F37X_STDPERIPH_VERSION       ( (__STM32F37X_STDPERIPH_VERSION_MAIN << 24)\
-                                             |(__STM32F37X_STDPERIPH_VERSION_SUB1 << 16)\
-                                             |(__STM32F37X_STDPERIPH_VERSION_SUB2 << 8)\
-                                             |(__STM32F37X_STDPERIPH_VERSION_RC))
-                                             
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
- */
-#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1         /*!< STM32F37X provide an MPU */
-#define __NVIC_PRIO_BITS          4         /*!< STM32F37X uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT             1         /*!< STM32F37X provide an FPU */
-
-
-/**
- * @brief STM32F37X Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum IRQn
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line 19          */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line 20                     */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_TS_IRQn               = 8,      /*!< EXTI Line2 Interrupt and Touch Sense Interrupt                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
-  ADC1_IRQn                   = 18,     /*!< ADC1 Interrupts                                                   */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                  */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                 */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                 */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                 */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM15_IRQn                  = 24,     /*!< TIM15 global Interrupt                                            */
-  TIM16_IRQn                  = 25,     /*!< TIM16 global Interrupt                                            */
-  TIM17_IRQn                  = 26,     /*!< TIM17 global Interrupt                                            */
-  TIM18_DAC2_IRQn             = 27,     /*!< TIM18 global Interrupt and DAC2 underrun Interrupt                */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  CEC_IRQn                    = 42,     /*!< CEC Interrupt                                                     */    
-  TIM12_IRQn                  = 43,     /*!< TIM12 global interrupt                                            */
-  TIM13_IRQn                  = 44,     /*!< TIM13 global interrupt                                            */
-  TIM14_IRQn                  = 45,     /*!< TIM14 global interrupt                                            */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  TIM6_DAC1_IRQn              = 54,     /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/
-  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                             */
-  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
-  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
-  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
-  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
-  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
-  SDADC1_IRQn                 = 61,     /*!< ADC Sigma Delta 1 global Interrupt                                */
-  SDADC2_IRQn                 = 62,     /*!< ADC Sigma Delta 2 global Interrupt                                */
-  SDADC3_IRQn                 = 63,     /*!< ADC Sigma Delta 1 global Interrupt                                */
-  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 global Interrupt                                  */
-  USB_HP_IRQn                 = 74,     /*!< USB High Priority global Interrupt                                */
-  USB_LP_IRQn                 = 75,     /*!< USB Low Priority global Interrupt                                 */
-  USBWakeUp_IRQn              = 76,     /*!< USB Wakeup Interrupt                                              */
-  TIM19_IRQn                  = 78,     /*!< TIM19 global Interrupt                                            */
-  FPU_IRQn                    = 81      /*!< Floating point Interrupt                                          */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"            /* Cortex-M4 processor and core peripherals */
-/* CHIBIOS FIX */
-/*#include "system_stm32f37x.h"*/    /* STM32F37x System Header */
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t  s32;
-typedef int16_t s16;
-typedef int8_t  s8;
-
-typedef const int32_t sc32;  /*!< Read Only */
-typedef const int16_t sc16;  /*!< Read Only */
-typedef const int8_t sc8;   /*!< Read Only */
-
-typedef __IO int32_t  vs32;
-typedef __IO int16_t  vs16;
-typedef __IO int8_t   vs8;
-
-typedef __I int32_t vsc32;  /*!< Read Only */
-typedef __I int16_t vsc16;  /*!< Read Only */
-typedef __I int8_t vsc8;   /*!< Read Only */
-
-typedef uint32_t  u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-typedef const uint32_t uc32;  /*!< Read Only */
-typedef const uint16_t uc16;  /*!< Read Only */
-typedef const uint8_t uc8;   /*!< Read Only */
-
-typedef __IO uint32_t  vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t  vu8;
-
-typedef __I uint32_t vuc32;  /*!< Read Only */
-typedef __I uint16_t vuc16;  /*!< Read Only */
-typedef __I uint8_t vuc8;   /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;    /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;   /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;   /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1; /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2; /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;   /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;   /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;  /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;  /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;  /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;  /*!< ADC injected sequence register,              Address offset: 0x38 */
-  __IO uint32_t JDR1;  /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;  /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;  /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;  /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;    /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-  
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-  
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief Consumer Electronics Control     
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
-  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
-  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
-  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
-  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
-  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
-}CEC_TypeDef;
-
-/** 
-  * @brief Analog Comparators 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< Comparator control Status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
-  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< FLASH access control register,              Address offset: 0x00 */
-  __IO uint32_t KEYR;         /*!< FLASH key register,                         Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;      /*!< FLASH option key register,                  Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< FLASH status register,                      Address offset: 0x0C */
-  __IO uint32_t CR;           /*!< FLASH control register,                     Address offset: 0x10 */
-  __IO uint32_t AR;           /*!< FLASH address register,                     Address offset: 0x14 */
-  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                   */
-  __IO uint32_t OBR;          /*!< FLASH Option byte register,                 Address offset: 0x1C */
-  __IO uint32_t WRPR;         /*!< FLASH Write register,                       Address offset: 0x20 */
-  
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
-  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
-  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
-  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
-  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
-  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
-  __IO uint16_t WRP2;         /*!<FLASH option byte write protection 2,          Address offset: 0x10 */
-  __IO uint16_t WRP3;         /*!<FLASH option byte write protection 3,          Address offset: 0x12 */
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-/* CHIBIOS FIX */
-#if 0
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
-  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
-  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
-  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
-  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
-  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
-  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
-  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
-  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
-}GPIO_TypeDef;
-#endif
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                      Address offset: 0x00 */
-       uint32_t RESERVED;    /*!< Reserved,                                                             0x04 */
-  __IO uint32_t EXTICR[4];   /*!< SYSCFG control register,                              Adress offset: 0x14-0x08 */
-  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                      Address offset: 0x18 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  
-}I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */ 
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
-  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
-  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
-  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
-  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
-  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
-  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
-  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
-  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
-  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */ 
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-  
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  uint32_t RESERVED0;       /*!< Reserved, 0x18                                                                 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                   Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                   Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                   Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                   Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                   Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                   Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                   Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                   Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                   Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                   Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                   Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                   Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                   Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Sigma-Delta Analog to Digital Converter (SDADC)  
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< SDADC control register 1,                        Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< SDADC control register 2,                        Address offset: 0x04 */
-  __IO uint32_t ISR;          /*!< SDADC interrupt and status register,             Address offset: 0x08 */
-  __IO uint32_t CLRISR;       /*!< SDADC clear interrupt and status register,       Address offset: 0x0C */
-  __IO uint32_t RESERVED0;    /*!< Reserved, 0x10                                                        */
-  __IO uint32_t JCHGR;        /*!< SDADC injected channel group selection register, Address offset: 0x14 */
-  __IO uint32_t RESERVED1;    /*!< Reserved, 0x18                                                        */
-  __IO uint32_t RESERVED2;    /*!< Reserved, 0x1C                                                        */
-  __IO uint32_t CONF0R;       /*!< SDADC configuration 0 register,                  Address offset: 0x20 */
-  __IO uint32_t CONF1R;       /*!< SDADC configuration 1 register,                  Address offset: 0x24 */
-  __IO uint32_t CONF2R;       /*!< SDADC configuration 2 register,                  Address offset: 0x28 */
-  __IO uint32_t RESERVED3[5]; /*!< Reserved, 0x2C - 0x3C                                                 */
-  __IO uint32_t CONFCHR1;     /*!< SDADC channel configuration register 1,          Address offset: 0x40 */
-  __IO uint32_t CONFCHR2;     /*!< SDADC channel configuration register 2,          Address offset: 0x44 */
-  __IO uint32_t RESERVED4[6]; /*!< Reserved, 0x48 - 0x5C                                                 */
-  __IO uint32_t JDATAR;       /*!< SDADC data register for injected group,          Address offset: 0x60 */
-  __IO uint32_t RDATAR;       /*!< SDADC data register for the regular channel,     Address offset: 0x64 */
-  __IO uint32_t RESERVED5[2]; /*!< Reserved, 0x68 - 0x6C                                                 */
-  __IO uint32_t JDATA12R;     /*!< SDADC1 and SDADC2 injected data register,        Address offset: 0x70 */
-  __IO uint32_t RDATA12R;     /*!< SDADC1 and SDADC2 regular data register,         Address offset: 0x74 */
-  __IO uint32_t JDATA13R;     /*!< SDADC1 and SDADC3 injected data register,        Address offset: 0x78 */
-  __IO uint32_t RDATA13R;     /*!< SDADC1 and SDADC3 regular data register,         Address offset: 0x7C */
-} SDADC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-  
-typedef struct
-{
-  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
-  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
-  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
-  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
-  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
-  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
-  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
-  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
-  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
-} SPI_TypeDef;
-
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
-  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
-  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
-  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
-  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
-  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
-  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
-  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
-  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
-  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
-  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
-  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
-} TIM_TypeDef;
-
-/** 
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
-} TSC_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-  
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
-  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
-  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
-  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
-} USART_TypeDef; 
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400)
-#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
-#define DAC2_BASE             (APB1PERIPH_BASE + 0x9800)
-#define TIM18_BASE            (APB1PERIPH_BASE + 0x9C00)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000)
-#define COMP_BASE             (APB2PERIPH_BASE + 0x001C)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
-#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
-#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
-#define TIM19_BASE            (APB2PERIPH_BASE + 0x5C00)
-#define SDADC1_BASE           (APB2PERIPH_BASE + 0x6000)
-#define SDADC2_BASE           (APB2PERIPH_BASE + 0x6400)
-#define SDADC3_BASE           (APB2PERIPH_BASE + 0x6800)
-
-/*!< AHB1 peripherals */
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE    (AHB1PERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE    (AHB1PERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE    (AHB1PERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE    (AHB1PERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE    (AHB1PERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE    (AHB1PERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE    (AHB1PERIPH_BASE + 0x0080)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE    (AHB1PERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE    (AHB1PERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE    (AHB1PERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE    (AHB1PERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE    (AHB1PERIPH_BASE + 0x0458)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define OB_BASE               ((uint32_t)0x1FFFF800)     /*!< Flash Option Bytes base address */
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define TSC_BASE              (AHB1PERIPH_BASE + 0x00004000)
-
-/*!< AHB2 peripherals */
-#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400)
-
-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
-#define DAC2                ((DAC_TypeDef *) DAC2_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-#define COMP                ((COMP_TypeDef *) COMP_BASE)
-#define TIM18               ((TIM_TypeDef *) TIM18_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#define TIM19               ((TIM_TypeDef *) TIM19_BASE)
-#define SDADC1              ((SDADC_TypeDef *) SDADC1_BASE)
-#define SDADC2              ((SDADC_TypeDef *) SDADC2_BASE)
-#define SDADC3              ((SDADC_TypeDef *) SDADC3_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter SAR (ADC)               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)  /*!< Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002)  /*!< End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)  /*!< Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)  /*!< Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010)  /*!< Regular channel Start flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)  /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)  /*!< Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)  /*!< Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)  /*!< Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)  /*!< Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)  /*!< Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)  /*!< Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)  /*!< Analog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)  /*!< Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)  /*!< Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)  /*!< Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)  /*!< Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)  /*!< Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)  /*!< Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)  /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)  /*!< Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)  /*!< Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)  /*!< Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)  /*!< Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)  /*!< Analog watchdog enable on regular channels */
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)  /*!< A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)  /*!< Continuous Conversion */
-#define  ADC_CR2_CAL                         ((uint32_t)0x00000004)  /*!< A/D Calibration */
-#define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)  /*!< Reset Calibration */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)  /*!< Direct Memory access mode */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)  /*!< Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)  /*!< JEXTSEL[2:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)  /*!< Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)  /*!< Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)  /*!< Bit 2 */
-#define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)  /*!< External Trigger Conversion mode for injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)  /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)  /*!< Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)  /*!< Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)  /*!< Bit 2 */
-#define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)  /*!< External Trigger Conversion mode for regular channels */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)  /*!< Start Conversion of injected channels */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)  /*!< Start Conversion of regular channels */
-#define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)  /*!< Temperature Sensor and VREFINT Enable */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)  /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)  /*!< Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)  /*!< Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)  /*!< Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)  /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)  /*!< Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)  /*!< Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)  /*!< Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)  /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)  /*!< Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)  /*!< Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)  /*!< Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)  /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)  /*!< Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)  /*!< Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)  /*!< Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)  /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)  /*!< Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)  /*!< Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)  /*!< Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)  /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/***********************  Bit definition for COMP_CSR register  ***************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< SW1 switch control */
-#define COMP_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
-#define COMP_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
-#define COMP_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
-#define COMP_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
-#define COMP_CSR_COMP1OUTSEL           ((uint32_t)0x00000700) /*!< COMP1 output select */
-#define COMP_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
-#define COMP_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
-#define COMP_CSR_COMP1OUTSEL_2         ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
-#define COMP_CSR_COMP1POL              ((uint32_t)0x00000800) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1HYST             ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
-#define COMP_CSR_COMP1HYST_0           ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
-#define COMP_CSR_COMP1HYST_1           ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
-#define COMP_CSR_COMP1OUT              ((uint32_t)0x00004000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK             ((uint32_t)0x00008000) /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN               ((uint32_t)0x00010000) /*!< COMP2 enable */
-#define COMP_CSR_COMP2MODE             ((uint32_t)0x000C0000) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2MODE_0           ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
-#define COMP_CSR_COMP2MODE_1           ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
-#define COMP_CSR_COMP2INSEL            ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INSEL_0          ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INSEL_1          ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INSEL_2          ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_WNDWEN                ((uint32_t)0x00800000) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP2OUTSEL           ((uint32_t)0x07000000) /*!< COMP2 output select */
-#define COMP_CSR_COMP2OUTSEL_0         ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
-#define COMP_CSR_COMP2OUTSEL_1         ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
-#define COMP_CSR_COMP2OUTSEL_2         ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
-#define COMP_CSR_COMP2POL              ((uint32_t)0x08000000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2HYST             ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
-#define COMP_CSR_COMP2HYST_0           ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
-#define COMP_CSR_COMP2HYST_1           ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
-#define COMP_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Controller Area Network (CAN )                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
-#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
-#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
-#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
-#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
-#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
-#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
-#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
-#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
-#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
-#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
-#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     CRC calculation unit (CRC)                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits */
-#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
-#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
-#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< Bit 0 */
-#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< Bit 1 */
-#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU (DBGMCU)                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP        ((uint32_t)0x00000004)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP        ((uint32_t)0x00000008)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP       ((uint32_t)0x00000040)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP       ((uint32_t)0x00000080)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)
-#define  DBGMCU_APB1_FZ_DBG_TIM18_STOP       ((uint32_t)0x00000200)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00000004)
-#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00000008)
-#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00000010)
-#define  DBGMCU_APB2_FZ_DBG_TIM19_STOP       ((uint32_t)0x00000020)
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller (DMA)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
-#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
-#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
-#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
-#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
-#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
-#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
-#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
-#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
-#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
-
-#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
-#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
-#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
-#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
-
-#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
-#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
-#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller (EXTI)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
-#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
-#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
-#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
-#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
-#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
-#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
-#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
-#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
-#define  EXTI_RTSR_TR24                      ((uint32_t)0x01000000)        /*!< Rising trigger event configuration bit of line 24 */
-#define  EXTI_RTSR_TR25                      ((uint32_t)0x02000000)        /*!< Rising trigger event configuration bit of line 25 */
-#define  EXTI_RTSR_TR26                      ((uint32_t)0x04000000)        /*!< Rising trigger event configuration bit of line 26 */
-#define  EXTI_RTSR_TR27                      ((uint32_t)0x08000000)        /*!< Rising trigger event configuration bit of line 27 */
-#define  EXTI_RTSR_TR28                      ((uint32_t)0x10000000)        /*!< Rising trigger event configuration bit of line 28 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
-#define  EXTI_FTSR_TR24                      ((uint32_t)0x01000000)        /*!< Falling trigger event configuration bit of line 24 */
-#define  EXTI_FTSR_TR25                      ((uint32_t)0x02000000)        /*!< Falling trigger event configuration bit of line 25 */
-#define  EXTI_FTSR_TR26                      ((uint32_t)0x04000000)        /*!< Falling trigger event configuration bit of line 26 */
-#define  EXTI_FTSR_TR27                      ((uint32_t)0x08000000)        /*!< Falling trigger event configuration bit of line 27 */
-#define  EXTI_FTSR_TR28                      ((uint32_t)0x10000000)        /*!< Falling trigger event configuration bit of line 28 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
-#define  EXTI_SWIER_SWIER24                  ((uint32_t)0x01000000)        /*!< Software Interrupt on line 24 */
-#define  EXTI_SWIER_SWIER25                  ((uint32_t)0x02000000)        /*!< Software Interrupt on line 25 */
-#define  EXTI_SWIER_SWIER26                  ((uint32_t)0x04000000)        /*!< Software Interrupt on line 26 */
-#define  EXTI_SWIER_SWIER27                  ((uint32_t)0x08000000)        /*!< Software Interrupt on line 27 */
-#define  EXTI_SWIER_SWIER28                  ((uint32_t)0x10000000)        /*!< Software Interrupt on line 28 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
-#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit for line 23 */
-#define  EXTI_PR_PR24                        ((uint32_t)0x01000000)        /*!< Pending bit for line 24 */
-#define  EXTI_PR_PR25                        ((uint32_t)0x02000000)        /*!< Pending bit for line 25 */
-#define  EXTI_PR_PR26                        ((uint32_t)0x04000000)        /*!< Pending bit for line 26 */
-#define  EXTI_PR_PR27                        ((uint32_t)0x08000000)        /*!< Pending bit for line 27 */
-#define  EXTI_PR_PR28                        ((uint32_t)0x10000000)        /*!< Pending bit for line 28 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
-#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x01)               /*!< Bit 0 */
-#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x02)               /*!< Bit 1 */
-
-#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
-#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)
-
-/******************  Bit definition for FLASH_KEYR register  ******************/
-#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
-
-/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
-#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000010)        /*!< Write Protection Error */
-#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
-
-/*******************  Bit definition for FLASH_CR register  *******************/
-#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
-#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
-#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
-#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
-#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
-#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
-#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
-#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
-#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
-#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
-#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< OptionBytes Loader Launch */
-
-/*******************  Bit definition for FLASH_AR register  *******************/
-#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
-#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
-#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */
-
-#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
-#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)      /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for OB_RDP register  **********************/
-#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
-#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
-
-/******************  Bit definition for OB_USER register  *********************/
-#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
-#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
-
-/******************  Bit definition for FLASH_WRP0 register  ******************/
-#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP1 register  ******************/
-#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP2 register  ******************/
-#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP3 register  ******************/
-#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O (GPIO)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
-#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
-#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
-#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
-#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
-#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
-#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
-#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
-#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
-#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
-#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
-#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
-#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
-#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
-#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
-#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_0                 ((uint32_t)0x00000001)
-#define GPIO_IDR_1                 ((uint32_t)0x00000002)
-#define GPIO_IDR_2                 ((uint32_t)0x00000004)
-#define GPIO_IDR_3                 ((uint32_t)0x00000008)
-#define GPIO_IDR_4                 ((uint32_t)0x00000010)
-#define GPIO_IDR_5                 ((uint32_t)0x00000020)
-#define GPIO_IDR_6                 ((uint32_t)0x00000040)
-#define GPIO_IDR_7                 ((uint32_t)0x00000080)
-#define GPIO_IDR_8                 ((uint32_t)0x00000100)
-#define GPIO_IDR_9                 ((uint32_t)0x00000200)
-#define GPIO_IDR_10                ((uint32_t)0x00000400)
-#define GPIO_IDR_11                ((uint32_t)0x00000800)
-#define GPIO_IDR_12                ((uint32_t)0x00001000)
-#define GPIO_IDR_13                ((uint32_t)0x00002000)
-#define GPIO_IDR_14                ((uint32_t)0x00004000)
-#define GPIO_IDR_15                ((uint32_t)0x00008000)
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_0                 ((uint32_t)0x00000001)
-#define GPIO_ODR_1                 ((uint32_t)0x00000002)
-#define GPIO_ODR_2                 ((uint32_t)0x00000004)
-#define GPIO_ODR_3                 ((uint32_t)0x00000008)
-#define GPIO_ODR_4                 ((uint32_t)0x00000010)
-#define GPIO_ODR_5                 ((uint32_t)0x00000020)
-#define GPIO_ODR_6                 ((uint32_t)0x00000040)
-#define GPIO_ODR_7                 ((uint32_t)0x00000080)
-#define GPIO_ODR_8                 ((uint32_t)0x00000100)
-#define GPIO_ODR_9                 ((uint32_t)0x00000200)
-#define GPIO_ODR_10                ((uint32_t)0x00000400)
-#define GPIO_ODR_11                ((uint32_t)0x00000800)
-#define GPIO_ODR_12                ((uint32_t)0x00001000)
-#define GPIO_ODR_13                ((uint32_t)0x00002000)
-#define GPIO_ODR_14                ((uint32_t)0x00004000)
-#define GPIO_ODR_15                ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
-#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
-#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
-#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
-#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
-#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
-#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
-#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
-#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
-#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
-#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
-#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
-#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
-#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
-#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
-#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
-#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
-#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
-#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
-#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
-#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
-#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
-#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
-#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
-#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
-#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
-#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
-#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
-#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
-#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
-#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
-#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
-#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
-#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
-#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
-#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
-#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
-#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
-#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
-#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
-#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
-#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
-#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
-#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
-#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
-#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
-#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
-#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
-#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
-#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
-#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
-#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
-#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
-#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
-#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
-#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
-#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
-#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)        /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG (IWDG)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                       ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          HDMI-CEC (CEC)                                    */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                              */
-#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message                 */
-#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message                   */
-
-/*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time                    */
-#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                           */
-#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                             */
-#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation         */
-#define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation        */
-#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional           */
-#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast No error generation       */
-#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                         */
-#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                         */
-
-/*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                              */
-
-/*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                              */
-
-/*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                      */
-#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                      */
-#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                            */
-#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                   */
-#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error             */
-#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error              */
-#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge                */
-#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                      */
-#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                       */
-#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                   */
-#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                    */
-#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                              */
-#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge                */
-
-/*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable            */
-#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable            */
-#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable                  */
-#define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable         */
-#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable   */
-#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable    */
-#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable      */
-#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable            */
-#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable            */
-#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable         */
-#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable          */
-#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                    */
-#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
-#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
-#define  PWR_CR_SDADC1EN                     ((uint16_t)0x0200)     /*!< Enable Analog part of the SDADC1 */
-#define  PWR_CR_SDADC2EN                     ((uint16_t)0x0400)     /*!< Enable Analog part of the SDADC2 */
-#define  PWR_CR_SDADC3EN                     ((uint16_t)0x0800)     /*!< Enable Analog part of the SDADC3 */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
-#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
-
-#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
-#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
-#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
-
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-/*!< ADCPRE configuration */
-#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)
-#define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)
-#define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)
-
-#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< ADC CLK divided by 2 */
-#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< ADC CLK divided by 4 */
-#define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< ADC CLK divided by 6 */
-#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< ADC CLK divided by 8 */
-
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-#define  RCC_CFGR_PLLSRC_HSI_Div2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
-#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
-
-#define  RCC_CFGR_PLLMULL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
-#define  RCC_CFGR_PLLMULL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
-#define  RCC_CFGR_PLLMULL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
-#define  RCC_CFGR_PLLMULL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
-#define  RCC_CFGR_PLLMULL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
-#define  RCC_CFGR_PLLMULL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
-#define  RCC_CFGR_PLLMULL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
-#define  RCC_CFGR_PLLMULL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
-#define  RCC_CFGR_PLLMULL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
-#define  RCC_CFGR_PLLMULL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
-#define  RCC_CFGR_PLLMULL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
-#define  RCC_CFGR_PLLMULL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
-#define  RCC_CFGR_PLLMULL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
-#define  RCC_CFGR_PLLMULL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
-#define  RCC_CFGR_PLLMULL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
-
-/*!< USB configuration */
-#define  RCC_CFGR_USBPRE                     ((uint32_t)0x00400000)        /*!< USB prescaler */
-
-/*!< MCO configuration */
-#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
-#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
-#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
-#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
-#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
-#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
-
-/*!< SDADCPRE configuration */
-#define  RCC_CFGR_SDADCPRE                   ((uint32_t)0xF8000000)        /*!< SDADCPRE[4:0] bits (Sigma Delta ADC prescaler) */
-#define  RCC_CFGR_SDADCPRE_0                 ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  RCC_CFGR_SDADCPRE_1                 ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  RCC_CFGR_SDADCPRE_2                 ((uint32_t)0x20000000)        /*!< Bit 2 */
-#define  RCC_CFGR_SDADCPRE_3                 ((uint32_t)0x40000000)        /*!< Bit 3 */
-#define  RCC_CFGR_SDADCPRE_4                 ((uint32_t)0x80000000)        /*!< Bit 4 */
-
-#define  RCC_CFGR_SDADCPRE_DIV1              ((uint32_t)0x00000000)        /*!< SDADC CLK not divided */
-#define  RCC_CFGR_SDADCPRE_DIV2              ((uint32_t)0x80000000)        /*!< SDADC CLK divided by 2 */
-#define  RCC_CFGR_SDADCPRE_DIV4              ((uint32_t)0x88000000)        /*!< SDADC CLK divided by 4 */
-#define  RCC_CFGR_SDADCPRE_DIV6              ((uint32_t)0x90000000)        /*!< SDADC CLK divided by 6 */
-#define  RCC_CFGR_SDADCPRE_DIV8              ((uint32_t)0x98000000)        /*!< SDADC CLK divided by 8 */
-#define  RCC_CFGR_SDADCPRE_DIV10             ((uint32_t)0xA0000000)        /*!< SDADC CLK divided by 10 */
-#define  RCC_CFGR_SDADCPRE_DIV12             ((uint32_t)0xA8000000)        /*!< SDADC CLK divided by 12 */
-#define  RCC_CFGR_SDADCPRE_DIV14             ((uint32_t)0xB0000000)        /*!< SDADC CLK divided by 14 */
-#define  RCC_CFGR_SDADCPRE_DIV16             ((uint32_t)0xB8000000)        /*!< SDADC CLK divided by 16 */
-#define  RCC_CFGR_SDADCPRE_DIV20             ((uint32_t)0xC0000000)        /*!< SDADC CLK divided by 20 */
-#define  RCC_CFGR_SDADCPRE_DIV24             ((uint32_t)0xC8000000)        /*!< SDADC CLK divided by 24 */
-#define  RCC_CFGR_SDADCPRE_DIV28             ((uint32_t)0xD0000000)        /*!< SDADC CLK divided by 28 */
-#define  RCC_CFGR_SDADCPRE_DIV32             ((uint32_t)0xD8000000)        /*!< SDADC CLK divided by 32 */
-#define  RCC_CFGR_SDADCPRE_DIV36             ((uint32_t)0xE0000000)        /*!< SDADC CLK divided by 36 */
-#define  RCC_CFGR_SDADCPRE_DIV40             ((uint32_t)0xE8000000)        /*!< SDADC CLK divided by 40 */
-#define  RCC_CFGR_SDADCPRE_DIV44             ((uint32_t)0xF0000000)        /*!< SDADC CLK divided by 44 */
-#define  RCC_CFGR_SDADCPRE_DIV48             ((uint32_t)0xF8000000)        /*!< SDADC CLK divided by 48 */
-
-/*********************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-/******************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG reset */
-#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
-#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 reset */
-#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 reset */
-#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 reset */
-#define  RCC_APB2RSTR_TIM19RST               ((uint32_t)0x00080000)        /*!< TIM19 reset */
-#define  RCC_APB2RSTR_SDADC1RST              ((uint32_t)0x01000000)        /*!< SDADC1 reset */
-#define  RCC_APB2RSTR_SDADC2RST              ((uint32_t)0x02000000)        /*!< SDADC2 reset */
-#define  RCC_APB2RSTR_SDADC3RST              ((uint32_t)0x04000000)        /*!< SDADC3 reset */
-
-/******************  Bit definition for RCC_APB1RSTR register  ******************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< Timer 12 reset */
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< Timer 13 reset */
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 reset */
-#define  RCC_APB1RSTR_TIM18RST               ((uint32_t)0x00000200)        /*!< Timer 18 reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 reset */
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI3 reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
-#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN reset */
-#define  RCC_APB1RSTR_DAC2RST                ((uint32_t)0x04000000)        /*!< DAC 2 reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR reset */
-#define  RCC_APB1RSTR_DAC1RST                ((uint32_t)0x20000000)        /*!< DAC 1 reset */
-#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
-#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
-#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
-#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
-#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
-#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
-#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
-#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
-#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
-
-#define  RCC_AHBENR_TSEN                     ((uint32_t)0x01000000)        /*!< TS clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
-#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
-#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
-#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
-#define  RCC_APB2ENR_TIM19EN                 ((uint32_t)0x00080000)        /*!< TIM19 clock enable */
-#define  RCC_APB2ENR_SDADC1EN                ((uint32_t)0x01000000)        /*!< SDADC1 clock enable */
-#define  RCC_APB2ENR_SDADC2EN                ((uint32_t)0x02000000)        /*!< SDADC2 clock enable */
-#define  RCC_APB2ENR_SDADC3EN                ((uint32_t)0x04000000)        /*!< SDADC3 clock enable */
-
-/******************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)        /*!< Timer 12 clock enable */
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)        /*!< Timer 13 clock enable */
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
-#define  RCC_APB1ENR_TIM18EN                 ((uint32_t)0x00000200)        /*!< Timer 18 clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI3 clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
-#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN clock enable */
-#define  RCC_APB1ENR_DAC2EN                  ((uint32_t)0x04000000)        /*!< DAC 2 clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
-#define  RCC_APB1ENR_DAC1EN                  ((uint32_t)0x20000000)        /*!< DAC 1 clock enable */
-#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
-
-#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-
-
-#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-/*!< RTC configuration */
-#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
-
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_OBL                         ((uint32_t)0x02000000)        /*!< OBL reset flag */
-#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-/*******************  Bit definition for RCC_AHBRSTR register  ****************/
-#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA reset */
-#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB reset */
-#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC reset */
-#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD reset */
-#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF reset */
-#define  RCC_AHBRSTR_TSRST                   ((uint32_t)0x00100000)         /*!< TS reset */
-
-/*******************  Bit definition for RCC_CFGR2 register  ******************/
-/*!< PREDIV1 configuration */
-#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
-#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
-#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
-#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
-#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
-#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
-#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
-#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
-#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
-#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
-#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
-#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
-#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
-#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
-#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
-#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
-#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
-
-/*******************  Bit definition for RCC_CFGR3 register  ******************/
-#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
-#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR3_I2CSW                     ((uint32_t)0x00000030)        /*!< I2CSW bits */
-#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 
-#define  RCC_CFGR3_I2C2SW                    ((uint32_t)0x00000020)        /*!< I2C2SW bits */
-#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */ 
-
-#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
-#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
-#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
-#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/*                                                                            */
-/*             Sigma-Delta Analog to Digital Converter (SDADC)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*****************  Bit definition for SDADC_CR1 register  ********************/
-#define  SDADC_CR1_EOCALIE                       ((uint32_t)0x00000001)        /*!< End of calibration interrupt enable */
-#define  SDADC_CR1_JEOCIE                        ((uint32_t)0x00000002)        /*!< Injected end of conversion interrupt enable */
-#define  SDADC_CR1_JOVRIE                        ((uint32_t)0x00000004)        /*!< Injected data overrun interrupt enable */
-#define  SDADC_CR1_REOCIE                        ((uint32_t)0x00000008)        /*!< Regular end of conversion interrupt enable */
-#define  SDADC_CR1_ROVRIE                        ((uint32_t)0x00000010)        /*!< Regular data overrun interrupt enable */
-#define  SDADC_CR1_REFV                          ((uint32_t)0x00000300)        /*!< Reference voltage selection */
-#define  SDADC_CR1_REFV_0                        ((uint32_t)0x00000100)        /*!< Reference voltage selection bit 0 */
-#define  SDADC_CR1_REFV_1                        ((uint32_t)0x00000200)        /*!< Reference voltage selection bit 1 */
-#define  SDADC_CR1_SLOWCK                        ((uint32_t)0x00000400)        /*!< Slow clock mode enable */
-#define  SDADC_CR1_SBI                           ((uint32_t)0x00000800)        /*!< Enter standby mode when idle */
-#define  SDADC_CR1_PDI                           ((uint32_t)0x00001000)        /*!< Enter power down mode when idle */
-#define  SDADC_CR1_JSYNC                         ((uint32_t)0x00004000)        /*!< Launch a injected conversion synchronously with SDADC1 */
-#define  SDADC_CR1_RSYNC                         ((uint32_t)0x00008000)        /*!< Launch regular conversion synchronously with SDADC1 */
-#define  SDADC_CR1_JDMAEN                        ((uint32_t)0x00010000)        /*!< DMA channel enabled to read data for the injected channel group */
-#define  SDADC_CR1_RDMAEN                        ((uint32_t)0x00020000)        /*!< DMA channel enabled to read data for the regular channel */
-#define  SDADC_CR1_INIT                          ((uint32_t)0x80000000)        /*!< Initialization mode request */
-
-/*****************  Bit definition for SDADC_CR2 register  ********************/
-#define  SDADC_CR2_ADON                          ((uint32_t)0x00000001)        /*!< SDADC enable */
-#define  SDADC_CR2_CALIBCNT                      ((uint32_t)0x00000006)        /*!< Number of calibration sequences to be performed */
-#define  SDADC_CR2_CALIBCNT_0                    ((uint32_t)0x00000002)        /*!< Number of calibration sequences to be performed bit 0 */
-#define  SDADC_CR2_CALIBCNT_1                    ((uint32_t)0x00000004)        /*!< Number of calibration sequences to be performed bit 1 */
-#define  SDADC_CR2_STARTCALIB                    ((uint32_t)0x00000010)        /*!< Start calibration */
-#define  SDADC_CR2_JCONT                         ((uint32_t)0x00000020)        /*!< Continuous mode selection for injected conversions */
-#define  SDADC_CR2_JDS                           ((uint32_t)0x00000040)        /*!< Delay start of injected conversions */
-#define  SDADC_CR2_JEXTSEL                       ((uint32_t)0x00000F00)        /*!< Trigger signal selection for launching injected conversions */
-#define  SDADC_CR2_JEXTSEL_0                     ((uint32_t)0x00000100)        /*!< Trigger signal selection for launching injected conversions bit 0 */
-#define  SDADC_CR2_JEXTSEL_1                     ((uint32_t)0x00000200)        /*!< Trigger signal selection for launching injected conversions bit 1 */
-#define  SDADC_CR2_JEXTSEL_2                     ((uint32_t)0x00000400)        /*!< Trigger signal selection for launching injected conversions bit 2 */
-#define  SDADC_CR2_JEXTSEL_3                     ((uint32_t)0x00000800)        /*!< Trigger signal selection for launching injected conversions bit 3 */
-#define  SDADC_CR2_JEXTEN                        ((uint32_t)0x00006000)        /*!< Trigger enable and trigger edge selection for injected conversions */
-#define  SDADC_CR2_JEXTEN_0                      ((uint32_t)0x00002000)        /*!< Trigger enable and trigger edge selection for injected conversions bit 0 */
-#define  SDADC_CR2_JEXTEN_1                      ((uint32_t)0x00004000)        /*!< Trigger enable and trigger edge selection for injected conversions bit 1 */
-#define  SDADC_CR2_JSWSTART                      ((uint32_t)0x00008000)        /*!< Start a conversion of the injected group of channels */
-#define  SDADC_CR2_RCH                           ((uint32_t)0x000F0000)        /*!< Regular channel selection */
-#define  SDADC_CR2_RCH_0                         ((uint32_t)0x00010000)        /*!< Regular channel selection bit 0 */
-#define  SDADC_CR2_RCH_1                         ((uint32_t)0x00020000)        /*!< Regular channel selection bit 1 */
-#define  SDADC_CR2_RCH_2                         ((uint32_t)0x00040000)        /*!< Regular channel selection bit 2 */
-#define  SDADC_CR2_RCH_3                         ((uint32_t)0x00080000)        /*!< Regular channel selection bit 3 */
-#define  SDADC_CR2_RCONT                         ((uint32_t)0x00400000)        /*!< Continuous mode selection for regular conversions */
-#define  SDADC_CR2_RSWSTART                      ((uint32_t)0x00800000)        /*!< Software start of a conversion on the regular channel */
-#define  SDADC_CR2_FAST                          ((uint32_t)0x01000000)        /*!< Fast conversion mode selection */
-
-/********************  Bit definition for SDADC_ISR register  *****************/
-#define  SDADC_ISR_EOCALF                        ((uint32_t)0x00000001)        /*!< End of calibration flag */
-#define  SDADC_ISR_JEOCF                         ((uint32_t)0x00000002)        /*!< End of injected conversion flag */
-#define  SDADC_ISR_JOVRF                         ((uint32_t)0x00000004)        /*!< Injected conversion overrun flag */
-#define  SDADC_ISR_REOCF                         ((uint32_t)0x00000010)        /*!< End of regular conversion flag */
-#define  SDADC_ISR_ROVRF                         ((uint32_t)0x00000020)        /*!< Regular conversion overrun flag */
-#define  SDADC_ISR_CALIBIP                       ((uint32_t)0x00001000)        /*!< Calibration in progress status */
-#define  SDADC_ISR_JCIP                          ((uint32_t)0x00002000)        /*!< Injected conversion in progress status */
-#define  SDADC_ISR_RCIP                          ((uint32_t)0x00004000)        /*!< Regular conversion in progress status */
-#define  SDADC_ISR_STABIP                        ((uint32_t)0x00008000)        /*!< Stabilization in progress status */
-#define  SDADC_ISR_INITRDY                       ((uint32_t)0x80000000)        /*!< Initialization mode is ready */
-
-/******************  Bit definition for SDADC_CLRISR register  ****************/
-#define  SDADC_ISR_CLREOCALF                     ((uint32_t)0x00000001)       /*!< Clear the end of calibration flag */
-#define  SDADC_ISR_CLRJOVRF                      ((uint32_t)0x00000004)       /*!< Clear the injected conversion overrun flag */
-#define  SDADC_ISR_CLRROVRF                      ((uint32_t)0x00000010)       /*!< Clear the regular conversion overrun flag */
-
-/******************  Bit definition for SDADC_JCHGR register  *****************/
-#define  SDADC_JCHGR_JCHG                        ((uint32_t)0x000001FF)       /*!< Injected channel group selection */
-#define  SDADC_JCHGR_JCHG_0                      ((uint32_t)0x00000001)       /*!< Injected channel 0 selection */
-#define  SDADC_JCHGR_JCHG_1                      ((uint32_t)0x00000002)       /*!< Injected channel 1 selection */
-#define  SDADC_JCHGR_JCHG_2                      ((uint32_t)0x00000004)       /*!< Injected channel 2 selection */
-#define  SDADC_JCHGR_JCHG_3                      ((uint32_t)0x00000008)       /*!< Injected channel 3 selection */
-#define  SDADC_JCHGR_JCHG_4                      ((uint32_t)0x00000010)       /*!< Injected channel 4 selection */
-#define  SDADC_JCHGR_JCHG_5                      ((uint32_t)0x00000020)       /*!< Injected channel 5 selection */
-#define  SDADC_JCHGR_JCHG_6                      ((uint32_t)0x00000040)       /*!< Injected channel 6 selection */
-#define  SDADC_JCHGR_JCHG_7                      ((uint32_t)0x00000080)       /*!< Injected channel 7 selection */
-#define  SDADC_JCHGR_JCHG_8                      ((uint32_t)0x00000100)       /*!< Injected channel 8 selection */
-
-/******************  Bit definition for SDADC_CONF0R register  ****************/
-#define  SDADC_CONF0R_OFFSET0                    ((uint32_t)0x00000FFF)       /*!< 12-bit calibration offset for configuration 0 */
-#define  SDADC_CONF0R_GAIN0                      ((uint32_t)0x00700000)       /*!< Gain setting for configuration 0 */
-#define  SDADC_CONF0R_GAIN0_0                    ((uint32_t)0x00100000)       /*!< Gain setting for configuration 0 Bit 0*/
-#define  SDADC_CONF0R_GAIN0_1                    ((uint32_t)0x00200000)       /*!< Gain setting for configuration 0 Bit 1 */
-#define  SDADC_CONF0R_GAIN0_2                    ((uint32_t)0x00400000)       /*!< Gain setting for configuration 0 Bit 2 */
-#define  SDADC_CONF0R_SE0                        ((uint32_t)0x0C000000)       /*!< Single ended mode for configuration 0 */
-#define  SDADC_CONF0R_SE0_0                      ((uint32_t)0x04000000)       /*!< Single ended mode for configuration 0 Bit 0 */
-#define  SDADC_CONF0R_SE0_1                      ((uint32_t)0x08000000)       /*!< Single ended mode for configuration 0 Bit 1 */
-#define  SDADC_CONF0R_COMMON0                    ((uint32_t)0xC0000000)       /*!< Common mode for configuration 0 */
-#define  SDADC_CONF0R_COMMON0_0                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 0 Bit 0 */
-#define  SDADC_CONF0R_COMMON0_1                  ((uint32_t)0x80000000)       /*!< Common mode for configuration 0 Bit 1 */
-
-/******************  Bit definition for SDADC_CONF1R register  ****************/
-#define  SDADC_CONF1R_OFFSET1                    ((uint32_t)0x00000FFF)       /*!< 12-bit calibration offset for configuration 1 */
-#define  SDADC_CONF1R_GAIN1                      ((uint32_t)0x00700000)       /*!< Gain setting for configuration 1 */
-#define  SDADC_CONF1R_GAIN1_0                    ((uint32_t)0x00100000)       /*!< Gain setting for configuration 1 Bit 0 */
-#define  SDADC_CONF1R_GAIN1_1                    ((uint32_t)0x00200000)       /*!< Gain setting for configuration 1 Bit 1 */
-#define  SDADC_CONF1R_GAIN1_2                    ((uint32_t)0x00400000)       /*!< Gain setting for configuration 1 Bit 2 */
-#define  SDADC_CONF1R_SE1                        ((uint32_t)0x0C000000)       /*!< Single ended mode for configuration 1 */
-#define  SDADC_CONF1R_SE1_0                      ((uint32_t)0x04000000)       /*!< Single ended mode for configuration 1 Bit 0 */
-#define  SDADC_CONF1R_SE1_1                      ((uint32_t)0x08000000)       /*!< Single ended mode for configuration 1 Bit 1 */
-#define  SDADC_CONF1R_COMMON1                    ((uint32_t)0xC0000000)       /*!< Common mode for configuration 1 */
-#define  SDADC_CONF1R_COMMON1_0                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 1 Bit 0 */
-#define  SDADC_CONF1R_COMMON1_1                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 1 Bit 1 */
-
-/******************  Bit definition for SDADC_CONF2R register  ****************/
-#define  SDADC_CONF2R_OFFSET2                    ((uint32_t)0x00000FFF)       /*!< 12-bit calibration offset for configuration 2 */
-#define  SDADC_CONF2R_GAIN2                      ((uint32_t)0x00700000)       /*!< Gain setting for configuration 2 */
-#define  SDADC_CONF2R_GAIN2_0                    ((uint32_t)0x00100000)       /*!< Gain setting for configuration 2 Bit 0 */
-#define  SDADC_CONF2R_GAIN2_1                    ((uint32_t)0x00200000)       /*!< Gain setting for configuration 2 Bit 1 */
-#define  SDADC_CONF2R_GAIN2_2                    ((uint32_t)0x00400000)       /*!< Gain setting for configuration 2 Bit 2 */
-#define  SDADC_CONF2R_SE2                        ((uint32_t)0x0C000000)       /*!< Single ended mode for configuration 2 */
-#define  SDADC_CONF2R_SE2_0                      ((uint32_t)0x04000000)       /*!< Single ended mode for configuration 2 Bit 0 */
-#define  SDADC_CONF2R_SE2_1                      ((uint32_t)0x08000000)       /*!< Single ended mode for configuration 2 Bit 1 */
-#define  SDADC_CONF2R_COMMON2                    ((uint32_t)0xC0000000)       /*!< Common mode for configuration 2 */
-#define  SDADC_CONF2R_COMMON2_0                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 2 Bit 0 */
-#define  SDADC_CONF2R_COMMON2_1                  ((uint32_t)0x80000000)       /*!< Common mode for configuration 2 Bit 1 */
-
-/*****************  Bit definition for SDADC_CONFCHR1 register  ***************/
-#define  SDADC_CONFCHR1_CONFCH0                  ((uint32_t)0x00000003)      /*!< Channel 0 configuration */
-#define  SDADC_CONFCHR1_CONFCH1                  ((uint32_t)0x00000030)      /*!< Channel 1 configuration */
-#define  SDADC_CONFCHR1_CONFCH2                  ((uint32_t)0x00000300)      /*!< Channel 2 configuration */
-#define  SDADC_CONFCHR1_CONFCH3                  ((uint32_t)0x00003000)      /*!< Channel 3 configuration */
-#define  SDADC_CONFCHR1_CONFCH4                  ((uint32_t)0x00030000)      /*!< Channel 4 configuration */
-#define  SDADC_CONFCHR1_CONFCH5                  ((uint32_t)0x00300000)      /*!< Channel 5 configuration */
-#define  SDADC_CONFCHR1_CONFCH6                  ((uint32_t)0x03000000)      /*!< Channel 6 configuration */
-#define  SDADC_CONFCHR1_CONFCH7                  ((uint32_t)0x30000000)      /*!< Channel 7 configuration */
-
-/*****************  Bit definition for SDADC_CONFCHR2 register  ***************/
-#define  SDADC_CONFCHR2_CONFCH8                  ((uint32_t)0x00000003)      /*!< Channel 8 configuration */
-
-/*****************  Bit definition for SDADC_JDATAR register  ***************/
-#define  SDADC_JDATAR_JDATA                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data */
-#define  SDADC_JDATAR_JDATACH                    ((uint32_t)0x0F000000)      /*!< Injected channel most recently converted */
-#define  SDADC_JDATAR_JDATACH_0                  ((uint32_t)0x01000000)      /*!< Injected channel most recently converted bit 0 */
-#define  SDADC_JDATAR_JDATACH_1                  ((uint32_t)0x02000000)      /*!< Injected channel most recently converted bit 1 */
-#define  SDADC_JDATAR_JDATACH_2                  ((uint32_t)0x04000000)      /*!< Injected channel most recently converted bit 2 */
-#define  SDADC_JDATAR_JDATACH_3                  ((uint32_t)0x08000000)      /*!< Injected channel most recently converted bit 3 */
-
-/*****************  Bit definition for SDADC_RDATAR register  ***************/
-#define  SDADC_RDATAR_RDATA                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data */
-
-/*****************  Bit definition for SDADC_JDATA12R register  ***************/
-#define  SDADC_JDATA12R_JDATA2                      ((uint32_t)0xFFFF0000)      /*!< Injected group conversion data for SDADC2 */
-#define  SDADC_JDATA12R_JDATA1                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data for SDADC1 */
-
-/*****************  Bit definition for SDADC_RDATA12R register  ***************/
-#define  SDADC_RDATA12R_RDATA2                      ((uint32_t)0xFFFF0000)      /*!< Regular conversion data for SDADC2 */
-#define  SDADC_RDATA12R_RDATA1                      ((uint32_t)0x0000FFFF)      /*!< Regular conversion data for SDADC1 */
-
-/*****************  Bit definition for SDADC_JDATA13R register  ***************/
-#define  SDADC_JDATA13R_JDATA3                      ((uint32_t)0xFFFF0000)      /*!< Injected group conversion data for SDADC3 */
-#define  SDADC_JDATA13R_JDATA1                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data for SDADC1 */
-
-/*****************  Bit definition for SDADC_RDATA13R register  ***************/
-#define  SDADC_RDATA13R_RDATA3                      ((uint32_t)0xFFFF0000)      /*!< Regular conversion data for SDADC3 */
-#define  SDADC_RDATA13R_RDATA1                      ((uint32_t)0x0000FFFF)      /*!< Regular conversion data for SDADC1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
-#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
-#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
-#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
-#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
-#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
-#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
-#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
-#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
-#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
-#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
-#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
-#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
-#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
-#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
-#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
-#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
-#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
-#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
-#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
-#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        System Configuration(SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< Bit 1 */
-#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
-#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP    ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
-#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP    ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
-#define SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP   ((uint32_t)0x00008000) /*!< Timer 18 / DAC2 Ch1 DMA remap */
-#define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_I2C2           ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR1_VBAT                   ((uint32_t)0x01000000) /*!< VBAT monitoring */
-#define SYSCFG_CFGR1_FPU_IE                 ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
-#define SYSCFG_CFGR1_FPU_IE_0               ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
-#define SYSCFG_CFGR1_FPU_IE_1               ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
-#define SYSCFG_CFGR1_FPU_IE_2               ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
-#define SYSCFG_CFGR1_FPU_IE_3               ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
-#define SYSCFG_CFGR1_FPU_IE_4               ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
-#define SYSCFG_CFGR1_FPU_IE_5               ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_SRAM_PE                   ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
-#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
-#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
-#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
-
-#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
-#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
-#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
-#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
-#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-
-#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
-#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
-#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
-#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
-#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
-#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
-#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
-#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
-#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
-#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
-#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM14_OR_TI1_RMP                       ((uint16_t)0x00C0)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
-#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
-#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
-#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
-#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
-#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
-#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
-#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
-#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
-#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
-#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
-#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
-#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
-#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
-#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
-#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
-#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
-#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
-#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
-#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
-#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
-#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
-#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
-#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
-#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
-#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
-#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
-#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
-#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
-#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                     ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
-#define  USART_RQR_SBKRQ                     ((uint16_t)0x0002)                /*!< Send Break Request */
-#define  USART_RQR_MMRQ                      ((uint16_t)0x0004)                /*!< Mute Mode Request */
-#define  USART_RQR_RXFRQ                     ((uint16_t)0x0008)                /*!< Receive Data flush Request */
-#define  USART_RQR_TXFRQ                     ((uint16_t)0x0010)                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
-#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
-#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
-#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
-#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
-#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
-#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
-#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
-#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
-#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
-#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
-#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
-#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
-#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
-#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
-#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
-#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
-#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
-#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
-#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
-#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
-#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
-#define  USART_ICR_NCF                       ((uint32_t)0x00000004)            /*!< Noise detected Clear Flag */
-#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
-#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
-#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
-#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
-#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
-#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
-#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
-#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
-#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */
-
-#ifdef USE_STDPERIPH_DRIVER
-  #include "stm32f37x_conf.h"
-#endif /* USE_STDPERIPH_DRIVER */
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F37x_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c
deleted file mode 100644
index e5de44aa8..000000000
--- a/os/hal/platforms/STM32F4xx/adc_lld.c
+++ /dev/null
@@ -1,419 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F4xx/adc_lld.c
- * @brief   STM32F4xx/STM32F2xx ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#define ADC1_DMA_CHANNEL                                                    \
-  STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
-
-#define ADC2_DMA_CHANNEL                                                    \
-  STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
-
-#define ADC3_DMA_CHANNEL                                                    \
-  STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/** @brief ADC2 driver identifier.*/
-#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
-ADCDriver ADCD2;
-#endif
-
-/** @brief ADC3 driver identifier.*/
-#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
-ADCDriver ADCD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   ADC DMA ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    /* DMA, this could help only if the DMA tries to access an unmapped
-       address space or violates alignment rules.*/
-    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
-  }
-  else {
-    /* It is possible that the conversion group has already be reset by the
-       ADC error handler, in this case this interrupt is spurious.*/
-    if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
-        /* Transfer complete processing.*/
-        _adc_isr_full_code(adcp);
-      }
-      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
-    }
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 ||       \
-    defined(__DOXYGEN__)
-/**
- * @brief   ADC interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
-  uint32_t sr;
-
-  CH_IRQ_PROLOGUE();
-
-#if STM32_ADC_USE_ADC1
-  sr = ADC1->SR;
-  ADC1->SR = 0;
-  /* Note, an overflow may occur after the conversion ended before the driver
-     is able to stop the ADC, this is why the DMA channel is checked too.*/
-  if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
-    /* ADC overflow condition, this could happen only if the DMA is unable
-       to read data fast enough.*/
-    if (ADCD1.grpp != NULL)
-      _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
-  }
-  /* TODO: Add here analog watchdog handling.*/
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC2
-  sr = ADC2->SR;
-  ADC2->SR = 0;
-  /* Note, an overflow may occur after the conversion ended before the driver
-     is able to stop the ADC, this is why the DMA channel is checked too.*/
-  if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) {
-    /* ADC overflow condition, this could happen only if the DMA is unable
-       to read data fast enough.*/
-    if (ADCD2.grpp != NULL)
-      _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW);
-  }
-  /* TODO: Add here analog watchdog handling.*/
-#endif /* STM32_ADC_USE_ADC2 */
-
-#if STM32_ADC_USE_ADC3
-  sr = ADC3->SR;
-  ADC3->SR = 0;
-  /* Note, an overflow may occur after the conversion ended before the driver
-     is able to stop the ADC, this is why the DMA channel is checked too.*/
-  if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) {
-    /* ADC overflow condition, this could happen only if the DMA is unable
-       to read data fast enough.*/
-    if (ADCD3.grpp != NULL)
-      _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW);
-  }
-  /* TODO: Add here analog watchdog handling.*/
-#endif /* STM32_ADC_USE_ADC3 */
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if STM32_ADC_USE_ADC1
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-  ADCD1.adc = ADC1;
-  ADCD1.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
-  ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
-                  STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_ADC_USE_ADC2
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD2);
-  ADCD2.adc = ADC2;
-  ADCD2.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
-  ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
-                  STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_ADC_USE_ADC3
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD3);
-  ADCD3.adc = ADC3;
-  ADCD3.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
-  ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
-                  STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-#endif
-
-  /* The shared vector is initialized on driver initialization and never
-     disabled.*/
-  nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  /* If in stopped state then enables the ADC and DMA clocks.*/
-  if (adcp->state == ADC_STOP) {
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-      bool_t b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
-                            (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
-      rccEnableADC1(FALSE);
-    }
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC2
-    if (&ADCD2 == adcp) {
-      bool_t b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
-                            (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
-      rccEnableADC2(FALSE);
-    }
-#endif /* STM32_ADC_USE_ADC2 */
-
-#if STM32_ADC_USE_ADC3
-    if (&ADCD3 == adcp) {
-      bool_t b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
-                            (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
-      rccEnableADC3(FALSE);
-    }
-#endif /* STM32_ADC_USE_ADC3 */
-
-    /* This is a common register but apparently it requires that at least one
-       of the ADCs is clocked in order to allow writing, see bug 3575297.*/
-    ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) |
-               (STM32_ADC_ADCPRE << 16);
-
-    /* ADC initial setup, starting the analog part here in order to reduce
-       the latency when starting a conversion.*/
-    adcp->adc->CR1 = 0;
-    adcp->adc->CR2 = 0;
-    adcp->adc->CR2 = ADC_CR2_ADON;
-  }
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  /* If in ready state then disables the ADC clock.*/
-  if (adcp->state == ADC_READY) {
-    dmaStreamRelease(adcp->dmastp);
-    adcp->adc->CR1 = 0;
-    adcp->adc->CR2 = 0;
-
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp)
-      rccDisableADC1(FALSE);
-#endif
-
-#if STM32_ADC_USE_ADC2
-    if (&ADCD2 == adcp)
-      rccDisableADC2(FALSE);
-#endif
-
-#if STM32_ADC_USE_ADC3
-    if (&ADCD3 == adcp)
-      rccDisableADC3(FALSE);
-#endif
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t mode;
-  const ADCConversionGroup *grpp = adcp->grpp;
-
-  /* DMA setup.*/
-  mode = adcp->dmamode;
-  if (grpp->circular) {
-    mode |= STM32_DMA_CR_CIRC;
-    if (adcp->depth > 1) {
-      /* If circular buffer depth > 1, then the half transfer interrupt
-         is enabled in order to allow streaming processing.*/
-      mode |= STM32_DMA_CR_HTIE;
-    }
-  }
-  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
-  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
-                                            (uint32_t)adcp->depth);
-  dmaStreamSetMode(adcp->dmastp, mode);
-  dmaStreamEnable(adcp->dmastp);
-
-  /* ADC setup.*/
-  adcp->adc->SR    = 0;
-  adcp->adc->SMPR1 = grpp->smpr1;
-  adcp->adc->SMPR2 = grpp->smpr2;
-  adcp->adc->SQR1  = grpp->sqr1;
-  adcp->adc->SQR2  = grpp->sqr2;
-  adcp->adc->SQR3  = grpp->sqr3;
-
-  /* ADC configuration and start, the start is performed using the method
-     specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
-  adcp->adc->CR1   = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
-  if ((grpp->cr2 & ADC_CR2_SWSTART) != 0)
-    adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
-                                 ADC_CR2_DDS   | ADC_CR2_ADON;
-  else
-    adcp->adc->CR2 = grpp->cr2 |                 ADC_CR2_DMA |
-                                 ADC_CR2_DDS   | ADC_CR2_ADON;
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-  dmaStreamDisable(adcp->dmastp);
-  adcp->adc->CR1 = 0;
-  adcp->adc->CR2 = 0;
-  adcp->adc->CR2 = ADC_CR2_ADON;
-}
-
-/**
- * @brief   Enables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- *          temperature sensor and internal reference voltage.
- * @note    This is an STM32-only functionality.
- */
-void adcSTM32EnableTSVREFE(void) {
-
-  ADC->CCR |= ADC_CCR_TSVREFE;
-}
-
-/**
- * @brief   Disables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- *          temperature sensor and internal reference voltage.
- * @note    This is an STM32-only functionality.
- */
-void adcSTM32DisableTSVREFE(void) {
-
-  ADC->CCR &= ~ADC_CCR_TSVREFE;
-}
-
-/**
- * @brief   Enables the VBATE bit.
- * @details The VBATE bit is required in order to sample the VBAT channel.
- * @note    This is an STM32-only functionality.
- * @note    This function is meant to be called after @p adcStart().
- */
-void adcSTM32EnableVBATE(void) {
-
-  ADC->CCR |= ADC_CCR_VBATE;
-}
-
-/**
- * @brief   Disables the VBATE bit.
- * @details The VBATE bit is required in order to sample the VBAT channel.
- * @note    This is an STM32-only functionality.
- * @note    This function is meant to be called after @p adcStart().
- */
-void adcSTM32DisableVBATE(void) {
-
-  ADC->CCR &= ~ADC_CCR_VBATE;
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h
deleted file mode 100644
index 7cda791ac..000000000
--- a/os/hal/platforms/STM32F4xx/adc_lld.h
+++ /dev/null
@@ -1,567 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F4xx/adc_lld.h
- * @brief   STM32F4xx/STM32F2xx ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Minimum ADC clock frequency.
- */
-#define STM32_ADCCLK_MIN        600000
-
-/**
- * @brief   Maximum ADC clock frequency.
- */
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
-#define STM32_ADCCLK_MAX        36000000
-#else
-#define STM32_ADCCLK_MAX        30000000
-#endif
-/** @} */
-
-/**
- * @name    Triggers selection
- * @{
- */
-#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 24) /**< @brief Trigger source.     */
-/** @} */
-
-/**
- * @name    ADC clock divider settings
- * @{
- */
-#define ADC_CCR_ADCPRE_DIV2     0
-#define ADC_CCR_ADCPRE_DIV4     1
-#define ADC_CCR_ADCPRE_DIV6     2
-#define ADC_CCR_ADCPRE_DIV8     3
-/** @} */
-
-/**
- * @name    Available analog channels
- * @{
- */
-#define ADC_CHANNEL_IN0         0   /**< @brief External analog input 0.    */
-#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
-#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
-#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
-#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
-#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
-#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
-#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
-#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
-#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
-#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
-#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
-#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
-#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
-#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
-#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
-#define ADC_CHANNEL_SENSOR      16  /**< @brief Internal temperature sensor.
-                                         @note Available onADC1 only.       */
-#define ADC_CHANNEL_VREFINT     17  /**< @brief Internal reference.
-                                         @note Available onADC1 only.       */
-#define ADC_CHANNEL_VBAT        18  /**< @brief VBAT.
-                                         @note Available onADC1 only.       */
-/** @} */
-
-/**
- * @name    Sampling rates
- * @{
- */
-#define ADC_SAMPLE_3            0   /**< @brief 3 cycles sampling time.     */
-#define ADC_SAMPLE_15           1   /**< @brief 15 cycles sampling time.    */
-#define ADC_SAMPLE_28           2   /**< @brief 28 cycles sampling time.    */
-#define ADC_SAMPLE_56           3   /**< @brief 56 cycles sampling time.    */
-#define ADC_SAMPLE_84           4   /**< @brief 84 cycles sampling time.    */
-#define ADC_SAMPLE_112          5   /**< @brief 112 cycles sampling time.   */
-#define ADC_SAMPLE_144          6   /**< @brief 144 cycles sampling time.   */
-#define ADC_SAMPLE_480          7   /**< @brief 480 cycles sampling time.   */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC common clock divider.
- * @note    This setting is influenced by the VDDA voltage and other
- *          external conditions, please refer to the datasheet for more
- *          info.<br>
- *          See section 5.3.20 "12-bit ADC characteristics".
- */
-#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV2
-#endif
-
-/**
- * @brief   ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1                  FALSE
-#endif
-
-/**
- * @brief   ADC2 driver enable switch.
- * @details If set to @p TRUE the support for ADC2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC2                  FALSE
-#endif
-
-/**
- * @brief   ADC3 driver enable switch.
- * @details If set to @p TRUE the support for ADC3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC3                  FALSE
-#endif
-
-/**
- * @brief   DMA stream used for ADC1 operations.
- */
-#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
-#endif
-
-/**
- * @brief   DMA stream used for ADC2 operations.
- */
-#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
-#endif
-
-/**
- * @brief   DMA stream used for ADC3 operations.
- */
-#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
-#endif
-
-/**
- * @brief   ADC1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_PRIORITY         2
-#endif
-
-/**
- * @brief   ADC2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC2_DMA_PRIORITY         2
-#endif
-
-/**
- * @brief   ADC3 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC3_DMA_PRIORITY         2
-#endif
-
-/**
- * @brief   ADC interrupt priority level setting.
- * @note    This setting is shared among ADC1, ADC2 and ADC3 because
- *          all ADCs share the same vector.
- */
-#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_IRQ_PRIORITY              5
-#endif
-
-/**
- * @brief   ADC1 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
-#endif
-
-/**
- * @brief   ADC2 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5
-#endif
-
-/**
- * @brief   ADC3 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
-#error "ADC1 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2
-#error "ADC2 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
-#error "ADC3 not present in the selected device"
-#endif
-
-#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
-#error "invalid DMA stream associated to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC2 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK)
-#error "invalid DMA stream associated to ADC2"
-#endif
-
-#if STM32_ADC_USE_ADC3 &&                                                   \
-    !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK)
-#error "invalid DMA stream associated to ADC3"
-#endif
-
-/* ADC clock related settings and checks.*/
-#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2
-#define STM32_ADCCLK                        (STM32_PCLK2 / 2)
-#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4
-#define STM32_ADCCLK                        (STM32_PCLK2 / 4)
-#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6
-#define STM32_ADCCLK                        (STM32_PCLK2 / 6)
-#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8
-#define STM32_ADCCLK                        (STM32_PCLK2 / 8)
-#else
-#error "invalid STM32_ADC_ADCPRE value specified"
-#endif
-
-#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX)
-#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
-  ADC_ERR_OVERFLOW = 1                      /**< ADC overflow condition.    */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    The use of this configuration structure requires knowledge of
- *          STM32 ADC cell registers interface, please refer to the STM32
- *          reference manual for details.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   ADC CR1 register initialization data.
-   * @note    All the required bits must be defined into this field except
-   *          @p ADC_CR1_SCAN that is enforced inside the driver.
-   */
-  uint32_t                  cr1;
-  /**
-   * @brief   ADC CR2 register initialization data.
-   * @note    All the required bits must be defined into this field except
-   *          @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
-   *          enforced inside the driver.
-   */
-  uint32_t                  cr2;
-  /**
-   * @brief   ADC SMPR1 register initialization data.
-   * @details In this field must be specified the sample times for channels
-   *          10...18.
-   */
-  uint32_t                  smpr1;
-  /**
-   * @brief   ADC SMPR2 register initialization data.
-   * @details In this field must be specified the sample times for channels
-   *          0...9.
-   */
-  uint32_t                  smpr2;
-  /**
-   * @brief   ADC SQR1 register initialization data.
-   * @details Conversion group sequence 13...16 + sequence length.
-   */
-  uint32_t                  sqr1;
-  /**
-   * @brief   ADC SQR2 register initialization data.
-   * @details Conversion group sequence 7...12.
-   */
-  uint32_t                  sqr2;
-  /**
-   * @brief   ADC SQR3 register initialization data.
-   * @details Conversion group sequence 1...6.
-   */
-  uint32_t                  sqr3;
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the ADCx registers block.
-   */
-  ADC_TypeDef               *adc;
-  /**
-   * @brief Pointer to associated DMA channel.
-   */
-  const stm32_dma_stream_t  *dmastp;
-  /**
-   * @brief DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Sequences building helper macros
- * @{
- */
-/**
- * @brief   Number of channels in a conversion sequence.
- */
-#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
-
-#define ADC_SQR3_SQ1_N(n)       ((n) << 0)  /**< @brief 1st channel in seq. */
-#define ADC_SQR3_SQ2_N(n)       ((n) << 5)  /**< @brief 2nd channel in seq. */
-#define ADC_SQR3_SQ3_N(n)       ((n) << 10) /**< @brief 3rd channel in seq. */
-#define ADC_SQR3_SQ4_N(n)       ((n) << 15) /**< @brief 4th channel in seq. */
-#define ADC_SQR3_SQ5_N(n)       ((n) << 20) /**< @brief 5th channel in seq. */
-#define ADC_SQR3_SQ6_N(n)       ((n) << 25) /**< @brief 6th channel in seq. */
-
-#define ADC_SQR2_SQ7_N(n)       ((n) << 0)  /**< @brief 7th channel in seq. */
-#define ADC_SQR2_SQ8_N(n)       ((n) << 5)  /**< @brief 8th channel in seq. */
-#define ADC_SQR2_SQ9_N(n)       ((n) << 10) /**< @brief 9th channel in seq. */
-#define ADC_SQR2_SQ10_N(n)      ((n) << 15) /**< @brief 10th channel in seq.*/
-#define ADC_SQR2_SQ11_N(n)      ((n) << 20) /**< @brief 11th channel in seq.*/
-#define ADC_SQR2_SQ12_N(n)      ((n) << 25) /**< @brief 12th channel in seq.*/
-
-#define ADC_SQR1_SQ13_N(n)      ((n) << 0)  /**< @brief 13th channel in seq.*/
-#define ADC_SQR1_SQ14_N(n)      ((n) << 5)  /**< @brief 14th channel in seq.*/
-#define ADC_SQR1_SQ15_N(n)      ((n) << 10) /**< @brief 15th channel in seq.*/
-#define ADC_SQR1_SQ16_N(n)      ((n) << 15) /**< @brief 16th channel in seq.*/
-/** @} */
-
-/**
- * @name    Sampling rate settings helper macros
- * @{
- */
-#define ADC_SMPR2_SMP_AN0(n)    ((n) << 0)  /**< @brief AN0 sampling time.  */
-#define ADC_SMPR2_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
-#define ADC_SMPR2_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
-#define ADC_SMPR2_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
-#define ADC_SMPR2_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
-#define ADC_SMPR2_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
-#define ADC_SMPR2_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
-#define ADC_SMPR2_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
-#define ADC_SMPR2_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
-#define ADC_SMPR2_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
-
-#define ADC_SMPR1_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
-#define ADC_SMPR1_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
-#define ADC_SMPR1_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
-#define ADC_SMPR1_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
-#define ADC_SMPR1_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
-#define ADC_SMPR1_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
-#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
-                                                 sampling time.             */
-#define ADC_SMPR1_SMP_VREF(n)   ((n) << 21) /**< @brief Voltage Reference
-                                                 sampling time.             */
-#define ADC_SMPR1_SMP_VBAT(n)   ((n) << 24) /**< @brief VBAT sampling time. */
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD2;
-#endif
-
-#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-  void adcSTM32EnableTSVREFE(void);
-  void adcSTM32DisableTSVREFE(void);
-  void adcSTM32EnableVBATE(void);
-  void adcSTM32DisableVBATE(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F4xx/ext_lld_isr.c b/os/hal/platforms/STM32F4xx/ext_lld_isr.c
deleted file mode 100644
index 64731b4c4..000000000
--- a/os/hal/platforms/STM32F4xx/ext_lld_isr.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F4xx/ext_lld_isr.c
- * @brief   STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTI[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI0_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 0);
-  EXTD1.config->channels[0].cb(&EXTD1, 0);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI1_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 1);
-  EXTD1.config->channels[1].cb(&EXTD1, 1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[2] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI2_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 2);
-  EXTD1.config->channels[2].cb(&EXTD1, 2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[3] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI3_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 3);
-  EXTD1.config->channels[3].cb(&EXTD1, 3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[4] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI4_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 4);
-  EXTD1.config->channels[4].cb(&EXTD1, 4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[5]...EXTI[9] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
-  EXTI->PR = pr;
-  if (pr & (1 << 5))
-    EXTD1.config->channels[5].cb(&EXTD1, 5);
-  if (pr & (1 << 6))
-    EXTD1.config->channels[6].cb(&EXTD1, 6);
-  if (pr & (1 << 7))
-    EXTD1.config->channels[7].cb(&EXTD1, 7);
-  if (pr & (1 << 8))
-    EXTD1.config->channels[8].cb(&EXTD1, 8);
-  if (pr & (1 << 9))
-    EXTD1.config->channels[9].cb(&EXTD1, 9);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[10]...EXTI[15] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
-                   (1 << 15));
-  EXTI->PR = pr;
-  if (pr & (1 << 10))
-    EXTD1.config->channels[10].cb(&EXTD1, 10);
-  if (pr & (1 << 11))
-    EXTD1.config->channels[11].cb(&EXTD1, 11);
-  if (pr & (1 << 12))
-    EXTD1.config->channels[12].cb(&EXTD1, 12);
-  if (pr & (1 << 13))
-    EXTD1.config->channels[13].cb(&EXTD1, 13);
-  if (pr & (1 << 14))
-    EXTD1.config->channels[14].cb(&EXTD1, 14);
-  if (pr & (1 << 15))
-    EXTD1.config->channels[15].cb(&EXTD1, 15);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[16] interrupt handler (PVD).
- *
- * @isr
- */
-CH_IRQ_HANDLER(PVD_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 16);
-  EXTD1.config->channels[16].cb(&EXTD1, 16);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[17] interrupt handler (RTC).
- *
- * @isr
- */
-CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 17);
-  EXTD1.config->channels[17].cb(&EXTD1, 17);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[18] interrupt handler (OTG_FS_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 18);
-  EXTD1.config->channels[18].cb(&EXTD1, 18);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[19] interrupt handler (ETH_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 19);
-  EXTD1.config->channels[19].cb(&EXTD1, 19);
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !defined(STM32F401xx)
-/**
- * @brief   EXTI[20] interrupt handler (OTG_HS_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 20);
-  EXTD1.config->channels[20].cb(&EXTD1, 20);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[21] interrupt handler (TAMPER_STAMP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 21);
-  EXTD1.config->channels[21].cb(&EXTD1, 21);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* !defined(STM32F401xx) */
-
-/**
- * @brief   EXTI[22] interrupt handler (RTC_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 22);
-  EXTD1.config->channels[22].cb(&EXTD1, 22);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(void) {
-
-  nvicEnableVector(EXTI0_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
-  nvicEnableVector(EXTI1_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
-  nvicEnableVector(EXTI2_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
-  nvicEnableVector(EXTI3_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
-  nvicEnableVector(EXTI4_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
-  nvicEnableVector(EXTI9_5_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
-  nvicEnableVector(EXTI15_10_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
-  nvicEnableVector(PVD_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
-  nvicEnableVector(RTC_Alarm_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
-  nvicEnableVector(OTG_FS_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
-  nvicEnableVector(ETH_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
-#if !defined(STM32F401xx)
-  nvicEnableVector(OTG_HS_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
-  nvicEnableVector(TAMP_STAMP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY));
-#endif /* !defined(STM32F401xx) */
-  nvicEnableVector(RTC_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(void) {
-
-  nvicDisableVector(EXTI0_IRQn);
-  nvicDisableVector(EXTI1_IRQn);
-  nvicDisableVector(EXTI2_IRQn);
-  nvicDisableVector(EXTI3_IRQn);
-  nvicDisableVector(EXTI4_IRQn);
-  nvicDisableVector(EXTI9_5_IRQn);
-  nvicDisableVector(EXTI15_10_IRQn);
-  nvicDisableVector(PVD_IRQn);
-  nvicDisableVector(RTC_Alarm_IRQn);
-  nvicDisableVector(OTG_FS_WKUP_IRQn);
-  nvicDisableVector(ETH_WKUP_IRQn);
-#if !defined(STM32F401xx)
-  nvicDisableVector(OTG_HS_WKUP_IRQn);
-  nvicDisableVector(TAMP_STAMP_IRQn);
-#endif /* !defined(STM32F401xx) */
-  nvicDisableVector(RTC_WKUP_IRQn);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
deleted file mode 100644
index fc8043675..000000000
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F4xx/hal_lld.c
- * @brief   STM32F4xx/STM32F2xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-/* TODO: LSEBYP like in F3.*/
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes the backup domain.
- * @note    WARNING! Changing clock source impossible without resetting
- *          of the whole BKP domain.
- */
-static void hal_lld_backup_domain_init(void) {
-
-  /* Backup domain access enabled and left open.*/
-  PWR->CR |= PWR_CR_DBP;
-
-  /* Reset BKP domain if different clock source selected.*/
-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
-    /* Backup domain reset.*/
-    RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0;
-  }
-
-#if STM32_LSE_ENABLED
-#if defined(STM32_LSE_BYPASS)
-  /* LSE Bypass.*/
-  RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
-#else
-  /* No LSE Bypass.*/
-  RCC->BDCR |= RCC_BDCR_LSEON;
-#endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                       /* Waits until LSE is stable.   */
-#endif
-
-#if HAL_USE_RTC
-  /* If the backup domain hasn't been initialized yet then proceed with
-     initialization.*/
-  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
-    /* Selects clock source.*/
-    RCC->BDCR |= STM32_RTCSEL;
-
-    /* RTC clock enabled.*/
-    RCC->BDCR |= RCC_BDCR_RTCEN;
-  }
-#endif /* HAL_USE_RTC */
-
-#if STM32_BKPRAM_ENABLE
-  rccEnableBKPSRAM(false);
-
-  PWR->CSR |= PWR_CSR_BRE;
-  while ((PWR->CSR & PWR_CSR_BRR) == 0)
-    ;                                /* Waits until the regulator is stable */
-#else
-  PWR->CSR &= ~PWR_CSR_BRE;
-#endif /* STM32_BKPRAM_ENABLE */
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* Reset of all peripherals. AHB3 is not reseted because it could have
-     been initialized in the board initialization file (board.c).*/
-  rccResetAHB1(~0);
-  rccResetAHB2(~0);
-  rccResetAPB1(~RCC_APB1RSTR_PWRRST);
-  rccResetAPB2(~0);
-
-  /* SysTick initialization using the system clock.*/
-  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-
-  /* DWT cycle counter enable.*/
-  SCS_DEMCR |= SCS_DEMCR_TRCENA;
-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
-
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(FALSE);
-
-  /* Initializes the backup domain.*/
-  hal_lld_backup_domain_init();
-
-#if defined(STM32_DMA_REQUIRED)
-  dmaInit();
-#endif
-
-  /* Programmable voltage detector enable.*/
-#if STM32_PVD_ENABLE
-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-#endif /* STM32_PVD_ENABLE */
-}
-
-/**
- * @brief   STM32F2xx clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function should be invoked just after the system reset.
- *
- * @special
- */
-void stm32_clock_init(void) {
-
-#if !STM32_NO_INIT
-  /* PWR clock enable.*/
-  RCC->APB1ENR = RCC_APB1ENR_PWREN;
-
-  /* PWR initialization.*/
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
-  PWR->CR = STM32_VOS;
-#else
-  PWR->CR = 0;
-#endif
-
-  /* HSI setup, it enforces the reset situation in order to handle possible
-     problems with JTAG probes and re-initializations.*/
-  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;                                       /* Wait until HSI is stable.    */
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
-  RCC->CFGR = 0;                            /* CFGR reset value.            */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;                                       /* Waits until HSI is selected. */
-
-#if STM32_HSE_ENABLED
-  /* HSE activation.*/
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
-#else
-  /* No HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON;
-#endif
-  while ((RCC->CR & RCC_CR_HSERDY) == 0)
-    ;                           /* Waits until HSE is stable.               */
-#endif
-
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                           /* Waits until LSI is stable.               */
-#endif
-
-#if STM32_ACTIVATE_PLL
-  /* PLL activation.*/
-  RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
-                 STM32_PLLM;
-  RCC->CR |= RCC_CR_PLLON;
-
-  /* Synchronization with voltage regulator stabilization.*/
-#if defined(STM32F4XX)
-  while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
-    ;                           /* Waits until power regulator is stable.   */
-
-#if STM32_OVERDRIVE_REQUIRED
-  /* Overdrive activation performed after activating the PLL in order to save
-     time as recommended in RM in "Entering Over-drive mode" paragraph.*/
-  PWR->CR |= PWR_CR_ODEN;
-  while (!(PWR->CSR & PWR_CSR_ODRDY))
-      ;
-  PWR->CR |= PWR_CR_ODSWEN;
-  while (!(PWR->CSR & PWR_CSR_ODSWRDY))
-      ;
-#endif /* STM32_OVERDRIVE_REQUIRED */
-#endif /* defined(STM32F4XX) */
-
-  /* Waiting for PLL lock.*/
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;
-#endif /* STM32_OVERDRIVE_REQUIRED */
-
-#if STM32_ACTIVATE_PLLI2S
-  /* PLLI2S activation.*/
-  RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
-  RCC->CR |= RCC_CR_PLLI2SON;
-
-  /* Waiting for PLL lock.*/
-  while (!(RCC->CR & RCC_CR_PLLI2SRDY))
-    ;
-#endif
-
-  /* Other clock-related settings (dividers, MCO etc).*/
-  RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
-              STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-
-  /* Flash setup.*/
-#if defined(STM32_USE_REVISION_A_FIX)
-  /* Some old revisions of F4x MCUs randomly crashes with compiler
-     optimizations enabled AND flash caches enabled. */
-  if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
-    FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
-  else
-    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
-                 FLASH_ACR_DCEN | STM32_FLASHBITS;
-#else
-  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
-               FLASH_ACR_DCEN | STM32_FLASHBITS;
-#endif
-
-  /* Switching to the configured clock source if it is different from MSI.*/
-#if (STM32_SW != STM32_SW_HSI)
-  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-#endif
-#endif /* STM32_NO_INIT */
-
-  /* SYSCFG clock enabled here because it is a multi-functional unit shared
-     among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
-}
-
-/** @} */
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
deleted file mode 100644
index c1b0dc9be..000000000
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ /dev/null
@@ -1,1777 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F4xx/hal_lld.h
- * @brief   STM32F4xx/STM32F2xx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - STM32_LSECLK.
- *          - STM32_LSE_BYPASS (optionally).
- *          - STM32_HSECLK.
- *          - STM32_HSE_BYPASS (optionally).
- *          - STM32_VDD (as hundredths of Volt).
- *          .
- *          One of the following macros must also be defined:
- *          - STM32F2XX for High-performance STM32 F-2 devices.
- *          - STM32F401xx for High-performance STM32 F-4 devices.
- *          - STM32F40_41xxx for High-performance STM32 F-4 devices.
- *          - STM32F427_437xx for High-performance STM32 F-4 devices.
- *          - STM32F429_439xx for High-performance STM32 F-4 devices.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "stm32.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @name    Platform identification macros
- * @{
- */
-#if defined(STM32F429_439xx) || defined(__DOXYGEN__)
-#define PLATFORM_NAME           "STM32F429/F439 High Performance with DSP and FPU"
-#define STM32F4XX
-
-#elif defined(STM32F427_437xx)
-#define PLATFORM_NAME           "STM32F427/F437 High Performance with DSP and FPU"
-#define STM32F4XX
-
-#elif defined(STM32F40_41xxx)
-#define PLATFORM_NAME           "STM32F407/F417 High Performance with DSP and FPU"
-#define STM32F4XX
-
-#elif defined(STM32F401xx)
-#define PLATFORM_NAME           "STM32F401 High Performance with DSP and FPU"
-#define STM32F4XX
-
-#elif defined(STM32F2XX)
-#define PLATFORM_NAME           "STM32F2xx High Performance"
-
-#else
-#error "STM32F2xx/F4xx device not specified"
-#endif
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) ||                 \
-    defined(__DOXYGEN__)
-/**
- * @brief   Absolute maximum system clock.
- */
-#define STM32_SYSCLK_MAX        180000000
-
-/**
- * @brief   Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX        26000000
-
-/**
- * @brief   Maximum HSE clock frequency using an external source.
- */
-#define STM32_HSECLK_BYP_MAX    50000000
-
-/**
- * @brief   Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN        4000000
-
-/**
- * @brief   Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_BYP_MIN    1000000
-
-/**
- * @brief   Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX        32768
-
-/**
- * @brief   Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_BYP_MAX    1000000
-
-/**
- * @brief   Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN        32768
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MAX         2100000
-
-/**
- * @brief   Minimum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MIN         950000
-
-/**
- * @brief   Maximum PLLs VCO clock frequency.
- */
-#define STM32_PLLVCO_MAX        432000000
-
-/**
- * @brief   Maximum PLLs VCO clock frequency.
- */
-#define STM32_PLLVCO_MIN        192000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MAX        180000000
-
-/**
- * @brief   Minimum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MIN        24000000
-
-/**
- * @brief   Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX         (STM32_PLLOUT_MAX /4)
-
-/**
- * @brief   Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX         (STM32_PLLOUT_MAX / 2)
-
-/**
- * @brief   Maximum SPI/I2S clock frequency.
- */
-#define STM32_SPII2S_MAX        45000000
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F40_41xxx) || defined(__DOXYGEN__)
-#define STM32_SYSCLK_MAX        168000000
-#define STM32_HSECLK_MAX        26000000
-#define STM32_HSECLK_BYP_MAX    50000000
-#define STM32_HSECLK_MIN        4000000
-#define STM32_HSECLK_BYP_MIN    1000000
-#define STM32_LSECLK_MAX        32768
-#define STM32_LSECLK_BYP_MAX    1000000
-#define STM32_LSECLK_MIN        32768
-#define STM32_PLLIN_MAX         2100000
-#define STM32_PLLIN_MIN         950000
-#define STM32_PLLVCO_MAX        432000000
-#define STM32_PLLVCO_MIN        192000000
-#define STM32_PLLOUT_MAX        168000000
-#define STM32_PLLOUT_MIN        24000000
-#define STM32_PCLK1_MAX         42000000
-#define STM32_PCLK2_MAX         84000000
-#define STM32_SPII2S_MAX        42000000
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F401xx) || defined(__DOXYGEN__)
-#define STM32_SYSCLK_MAX        84000000
-#define STM32_HSECLK_MAX        26000000
-#define STM32_HSECLK_BYP_MAX    50000000
-#define STM32_HSECLK_MIN        4000000
-#define STM32_HSECLK_BYP_MIN    1000000
-#define STM32_LSECLK_MAX        32768
-#define STM32_LSECLK_BYP_MAX    1000000
-#define STM32_LSECLK_MIN        32768
-#define STM32_PLLIN_MAX         2100000
-#define STM32_PLLIN_MIN         950000
-#define STM32_PLLVCO_MAX        432000000
-#define STM32_PLLVCO_MIN        192000000
-#define STM32_PLLOUT_MAX        84000000
-#define STM32_PLLOUT_MIN        24000000
-#define STM32_PCLK1_MAX         42000000
-#define STM32_PCLK2_MAX         84000000
-#define STM32_SPII2S_MAX        42000000
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F2XX)
-#define STM32_SYSCLK_MAX        120000000
-#define STM32_HSECLK_MAX        26000000
-#define STM32_HSECLK_BYP_MAX    26000000
-#define STM32_HSECLK_MIN        1000000
-#define STM32_HSECLK_BYP_MIN    1000000
-#define STM32_LSECLK_MAX        32768
-#define STM32_LSECLK_BYP_MAX    1000000
-#define STM32_LSECLK_MIN        32768
-#define STM32_PLLIN_MAX         2000000
-#define STM32_PLLIN_MIN         950000
-#define STM32_PLLVCO_MAX        432000000
-#define STM32_PLLVCO_MIN        192000000
-#define STM32_PLLOUT_MAX        120000000
-#define STM32_PLLOUT_MIN        24000000
-#define STM32_PCLK1_MAX         30000000
-#define STM32_PCLK2_MAX         60000000
-#define STM32_SPII2S_MAX        30000000
-#endif /* defined(STM32F2XX) */
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define STM32_HSICLK            16000000    /**< High speed internal clock. */
-#define STM32_LSICLK            32000       /**< Low speed internal clock.  */
-/** @} */
-
-/**
- * @name    PWR_CR register bits definitions
- * @{
- */
-#define STM32_VOS_SCALE3        (PWR_CR_VOS_0)
-#define STM32_VOS_SCALE2        (PWR_CR_VOS_1)
-#define STM32_VOS_SCALE1        (PWR_CR_VOS_1 | PWR_CR_VOS_0)
-#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
-#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
-#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
-#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
-#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
-#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
-#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
-#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
-#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
-/** @} */
-
-/**
- * @name    RCC_PLLCFGR register bits definitions
- * @{
- */
-#define STM32_PLLP_MASK			(3 << 16)	/**< PLLP mask.                 */
-#define STM32_PLLP_DIV2			(0 << 16)	/**< PLL clock divided by 2.    */
-#define STM32_PLLP_DIV4			(1 << 16)	/**< PLL clock divided by 4.    */
-#define STM32_PLLP_DIV6			(2 << 16)   /**< PLL clock divided by 6.    */
-#define STM32_PLLP_DIV8			(3 << 16)   /**< PLL clock divided by 8.    */
-
-#define STM32_PLLSRC_HSI        (0 << 22)   /**< PLL clock source is HSI.   */
-#define STM32_PLLSRC_HSE        (1 << 22)   /**< PLL clock source is HSE.   */
-/** @} */
-
-/**
- * @name    RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_MASK           (3 << 0)    /**< SW mask.                   */
-#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
-#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
-#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
-
-#define STM32_HPRE_MASK         (15 << 4)   /**< HPRE mask.                 */
-#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
-#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
-#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
-#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
-#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
-#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
-#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
-#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
-#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
-
-#define STM32_PPRE1_MASK        (7 << 10)	/**< PPRE1 mask.                */
-#define STM32_PPRE1_DIV1        (0 << 10)   /**< HCLK divided by 1.         */
-#define STM32_PPRE1_DIV2        (4 << 10)   /**< HCLK divided by 2.         */
-#define STM32_PPRE1_DIV4        (5 << 10)   /**< HCLK divided by 4.         */
-#define STM32_PPRE1_DIV8        (6 << 10)   /**< HCLK divided by 8.         */
-#define STM32_PPRE1_DIV16       (7 << 10)   /**< HCLK divided by 16.        */
-
-#define STM32_PPRE2_MASK        (7 << 13)	/**< PPRE2 mask.                */
-#define STM32_PPRE2_DIV1        (0 << 13)   /**< HCLK divided by 1.         */
-#define STM32_PPRE2_DIV2        (4 << 13)   /**< HCLK divided by 2.         */
-#define STM32_PPRE2_DIV4        (5 << 13)   /**< HCLK divided by 4.         */
-#define STM32_PPRE2_DIV8        (6 << 13)   /**< HCLK divided by 8.         */
-#define STM32_PPRE2_DIV16       (7 << 13)   /**< HCLK divided by 16.        */
-
-#define STM32_RTCPRE_MASK       (31 << 16)  /**< RTCPRE mask.               */
-
-#define STM32_MCO1SEL_MASK      (3 << 21)   /**< MCO1 mask.                 */
-#define STM32_MCO1SEL_HSI       (0 << 21)   /**< HSI clock on MCO1 pin.     */
-#define STM32_MCO1SEL_LSE       (1 << 21)   /**< LSE clock on MCO1 pin.     */
-#define STM32_MCO1SEL_HSE       (2 << 21)   /**< HSE clock on MCO1 pin.     */
-#define STM32_MCO1SEL_PLL       (3 << 21)   /**< PLL clock on MCO1 pin.     */
-
-#define STM32_I2SSRC_MASK       (1 << 23)   /**< I2CSRC mask.               */
-#define STM32_I2SSRC_PLLI2S     (0 << 23)   /**< I2SSRC is PLLI2S.          */
-#define STM32_I2SSRC_CKIN       (1 << 23)   /**< I2S_CKIN is PLLI2S.        */
-
-#define STM32_MCO1PRE_MASK      (7 << 24)   /**< MCO1PRE mask.              */
-#define STM32_MCO1PRE_DIV1      (0 << 24)   /**< MCO1 divided by 1.         */
-#define STM32_MCO1PRE_DIV2      (4 << 24)   /**< MCO1 divided by 2.         */
-#define STM32_MCO1PRE_DIV3      (5 << 24)   /**< MCO1 divided by 3.         */
-#define STM32_MCO1PRE_DIV4      (6 << 24)   /**< MCO1 divided by 4.         */
-#define STM32_MCO1PRE_DIV5      (7 << 24)   /**< MCO1 divided by 5.         */
-
-#define STM32_MCO2PRE_MASK      (7 << 27)   /**< MCO2PRE mask.              */
-#define STM32_MCO2PRE_DIV1      (0 << 27)   /**< MCO2 divided by 1.         */
-#define STM32_MCO2PRE_DIV2      (4 << 27)   /**< MCO2 divided by 2.         */
-#define STM32_MCO2PRE_DIV3      (5 << 27)   /**< MCO2 divided by 3.         */
-#define STM32_MCO2PRE_DIV4      (6 << 27)   /**< MCO2 divided by 4.         */
-#define STM32_MCO2PRE_DIV5      (7 << 27)   /**< MCO2 divided by 5.         */
-
-#define STM32_MCO2SEL_MASK      (3U << 30)  /**< MCO2 mask.                 */
-#define STM32_MCO2SEL_SYSCLK    (0U << 30)  /**< SYSCLK clock on MCO2 pin.  */
-#define STM32_MCO2SEL_PLLI2S    (1U << 30)  /**< PLLI2S clock on MCO2 pin.  */
-#define STM32_MCO2SEL_HSE       (2U << 30)  /**< HSE clock on MCO2 pin.     */
-#define STM32_MCO2SEL_PLL       (3U << 30)  /**< PLL clock on MCO2 pin.     */
-
-#define STM32_RTC_NOCLOCK       (0 << 8)    /**< No clock.                  */
-#define STM32_RTC_LSE           (1 << 8)    /**< LSE used as RTC clock.     */
-#define STM32_RTC_LSI           (2 << 8)    /**< LSI used as RTC clock.     */
-#define STM32_RTC_HSE           (3 << 8)    /**< HSE divided by programmable
-                                                 prescaler used as RTC clock*/
-
-/**
- * @name    RCC_PLLI2SCFGR register bits definitions
- * @{
- */
-#define STM32_PLLI2SN_MASK      (511 << 6)  /**< PLLI2SN mask.              */
-#define STM32_PLLI2SR_MASK      (7 << 28)   /**< PLLI2SR mask.              */
-/** @} */
-
-/**
- * @name    RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC source mask.           */
-#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No RTC source.             */
-#define STM32_RTCSEL_LSE        (1 << 8)    /**< RTC source is LSE.         */
-#define STM32_RTCSEL_LSI        (2 << 8)    /**< RTC source is LSI.         */
-#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< RTC source is HSE divided. */
-/** @} */
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    STM32F4xx capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 0) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC2          TRUE
-#define STM32_ADC2_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 2) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN      0x00001100
-
-#define STM32_HAS_ADC3          TRUE
-#define STM32_ADC3_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 0) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 1))
-#define STM32_ADC3_DMA_CHN      0x00000022
-
-#define STM32_HAS_ADC4          FALSE
-#define STM32_ADC4_DMA_MSK      0x00000000
-#define STM32_ADC4_DMA_CHN      0x00000000
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          TRUE
-#define STM32_HAS_CAN2          TRUE
-#define STM32_CAN_MAX_FILTERS   28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      TRUE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          TRUE
-
-/* ETH attributes.*/
-#if !defined(STM32F401xx)
-#define STM32_HAS_ETH           TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_ETH           FALSE
-#endif /* defined(STM32F401xx) */
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 23
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         TRUE
-#define STM32_HAS_GPIOH         TRUE
-#if !defined(STM32F401xx)
-#define STM32_HAS_GPIOF         TRUE
-#define STM32_HAS_GPIOG         TRUE
-#define STM32_HAS_GPIOI         TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_GPIOF         FALSE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOI         FALSE
-#endif /* defined(STM32F401xx) */
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 0) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN   0x00100001
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x11000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN   0x00007700
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C2_TX_DMA_CHN   0x70000000
-
-#define STM32_HAS_I2C3          TRUE
-#define STM32_I2C3_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_I2C3_RX_DMA_CHN   0x00000300
-#define STM32_I2C3_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C3_TX_DMA_CHN   0x00030000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#else
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#endif
-#define STM32_RTC_IS_CALENDAR   TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          TRUE
-#define STM32_SDC_SDIO_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN  0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 0) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN   0x00000303
-#define STM32_SPI1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 3) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN   0x00303000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          TRUE
-#define STM32_SPI3_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 0) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) ||                 \
-    defined(STM32F401xx)
-#define STM32_HAS_SPI4          TRUE
-#define STM32_SPI4_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 0) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SPI4_RX_DMA_CHN   0x00005004
-#define STM32_SPI4_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 1) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN   0x00050040
-#else
-#define STM32_HAS_SPI4          FALSE
-#endif
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
-#define STM32_HAS_SPI5          TRUE
-#define STM32_SPI5_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 3) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI5_RX_DMA_CHN   0x00702000
-#define STM32_SPI5_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 4) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI5_TX_DMA_CHN   0x07020000
-
-#define STM32_HAS_SPI6          TRUE
-#define STM32_SPI6_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI6_RX_DMA_CHN   0x01000000
-#define STM32_SPI6_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI6_TX_DMA_CHN   0x00100000
-
-#else /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-#endif /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          TRUE
-#define STM32_HAS_TIM5          TRUE
-#if !defined(STM32F401xx)
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          TRUE
-#define STM32_HAS_TIM8          TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_TIM6          FALSE
-#define STM32_HAS_TIM7          FALSE
-#define STM32_HAS_TIM8          FALSE
-#endif /* defined(STM32F401xx) */
-#define STM32_HAS_TIM9          TRUE
-#define STM32_HAS_TIM10         TRUE
-#define STM32_HAS_TIM11         TRUE
-#if !defined(STM32F401xx)
-#define STM32_HAS_TIM12         TRUE
-#define STM32_HAS_TIM13         TRUE
-#define STM32_HAS_TIM14         TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         FALSE
-#endif /* defined(STM32F401xx) */
-#define STM32_HAS_TIM15         FALSE
-#define STM32_HAS_TIM16         FALSE
-#define STM32_HAS_TIM17         FALSE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#if !defined(STM32F401xx)
-#define STM32_HAS_USART3        TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_USART3_RX_DMA_CHN 0x00000040
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074000
-
-#define STM32_HAS_UART4         TRUE
-#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_UART4_RX_DMA_CHN  0x00000400
-#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_UART4_TX_DMA_CHN  0x00040000
-
-#define STM32_HAS_UART5         TRUE
-#define STM32_UART5_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 0))
-#define STM32_UART5_RX_DMA_CHN  0x00000004
-#define STM32_UART5_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_UART5_TX_DMA_CHN  0x40000000
-
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_USART3        FALSE
-#define STM32_HAS_UART4         FALSE
-#define STM32_HAS_UART5         FALSE
-#endif /* defined(STM32F401xx) */
-
-#define STM32_HAS_USART6        TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |            \
-                                 STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           FALSE
-#define STM32_HAS_OTG1          TRUE
-#if !defined(STM32F401xx)
-#define STM32_HAS_OTG2          TRUE
-#else /* defined(STM32F401xx) */
-#define STM32_HAS_OTG2          FALSE
-#endif /* defined(STM32F401xx) */
-/** @} */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names.                                     */
-/*===========================================================================*/
-
-/**
- * @name    IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler         Vector40    /**< Window Watchdog.           */
-#define PVD_IRQHandler          Vector44    /**< PVD through EXTI Line
-                                                 detect.                    */
-#define TAMP_STAMP_IRQHandler   Vector48    /**< Tamper and TimeStamp
-                                                 through EXTI Line.         */
-#define RTC_WKUP_IRQHandler     Vector4C    /**< RTC wakeup EXTI Line.      */
-#define FLASH_IRQHandler        Vector50    /**< Flash.                     */
-#define RCC_IRQHandler          Vector54    /**< RCC.                       */
-#define EXTI0_IRQHandler        Vector58    /**< EXTI Line 0.               */
-#define EXTI1_IRQHandler        Vector5C    /**< EXTI Line 1.               */
-#define EXTI2_IRQHandler        Vector60    /**< EXTI Line 2.               */
-#define EXTI3_IRQHandler        Vector64    /**< EXTI Line 3.               */
-#define EXTI4_IRQHandler        Vector68    /**< EXTI Line 4.               */
-#define DMA1_Stream0_IRQHandler Vector6C    /**< DMA1 Stream 0.             */
-#define DMA1_Stream1_IRQHandler Vector70    /**< DMA1 Stream 1.             */
-#define DMA1_Stream2_IRQHandler Vector74    /**< DMA1 Stream 2.             */
-#define DMA1_Stream3_IRQHandler Vector78    /**< DMA1 Stream 3.             */
-#define DMA1_Stream4_IRQHandler Vector7C    /**< DMA1 Stream 4.             */
-#define DMA1_Stream5_IRQHandler Vector80    /**< DMA1 Stream 5.             */
-#define DMA1_Stream6_IRQHandler Vector84    /**< DMA1 Stream 6.             */
-#define ADC1_2_3_IRQHandler     Vector88    /**< ADC1, ADC2 and ADC3.       */
-#define CAN1_TX_IRQHandler      Vector8C    /**< CAN1 TX.                   */
-#define CAN1_RX0_IRQHandler     Vector90    /**< CAN1 RX0.                  */
-#define CAN1_RX1_IRQHandler     Vector94    /**< CAN1 RX1.                  */
-#define CAN1_SCE_IRQHandler     Vector98    /**< CAN1 SCE.                  */
-#define EXTI9_5_IRQHandler      Vector9C    /**< EXTI Line 9..5.            */
-#define TIM1_BRK_IRQHandler     VectorA0    /**< TIM1 Break.                */
-#define TIM1_UP_IRQHandler      VectorA4    /**< TIM1 Update.               */
-#define TIM1_TRG_COM_IRQHandler VectorA8    /**< TIM1 Trigger and
-                                                 Commutation.               */
-#define TIM1_CC_IRQHandler      VectorAC    /**< TIM1 Capture Compare.      */
-#define TIM2_IRQHandler         VectorB0    /**< TIM2.                      */
-#define TIM3_IRQHandler         VectorB4    /**< TIM3.                      */
-#define TIM4_IRQHandler         VectorB8    /**< TIM4.                      */
-#define I2C1_EV_IRQHandler      VectorBC    /**< I2C1 Event.                */
-#define I2C1_ER_IRQHandler      VectorC0    /**< I2C1 Error.                */
-#define I2C2_EV_IRQHandler      VectorC4    /**< I2C2 Event.                */
-#define I2C2_ER_IRQHandler      VectorC8    /**< I2C1 Error.                */
-#define SPI1_IRQHandler         VectorCC    /**< SPI1.                      */
-#define SPI2_IRQHandler         VectorD0    /**< SPI2.                      */
-#define USART1_IRQHandler       VectorD4    /**< USART1.                    */
-#define USART2_IRQHandler       VectorD8    /**< USART2.                    */
-#define USART3_IRQHandler       VectorDC    /**< USART3.                    */
-#define EXTI15_10_IRQHandler    VectorE0    /**< EXTI Line 15..10.          */
-#define RTC_Alarm_IRQHandler    VectorE4    /**< RTC alarms (A and B)
-                                                 through EXTI line.         */
-#define OTG_FS_WKUP_IRQHandler  VectorE8    /**< USB OTG FS Wakeup through
-                                                 EXTI line.                 */
-#define TIM8_BRK_IRQHandler     VectorEC    /**< TIM8 Break.                */
-#define TIM8_UP_IRQHandler      VectorF0    /**< TIM8 Update.               */
-#define TIM8_TRG_COM_IRQHandler VectorF4    /**< TIM8 Trigger and
-                                                 Commutation.               */
-#define TIM8_CC_IRQHandler      VectorF8    /**< TIM8 Capture Compare.      */
-#define DMA1_Stream7_IRQHandler VectorFC    /**< DMA1 Stream 7.             */
-#define FSMC_IRQHandler         Vector100   /**< FSMC.                      */
-#define SDIO_IRQHandler         Vector104   /**< SDIO.                      */
-#define TIM5_IRQHandler         Vector108   /**< TIM5.                      */
-#define SPI3_IRQHandler         Vector10C   /**< SPI3.                      */
-#define UART4_IRQHandler        Vector110   /**< UART4.                     */
-#define UART5_IRQHandler        Vector114   /**< UART5.                     */
-#define TIM6_IRQHandler         Vector118   /**< TIM6.                      */
-#define TIM7_IRQHandler         Vector11C   /**< TIM7.                      */
-#define DMA2_Stream0_IRQHandler Vector120   /**< DMA2 Stream0.              */
-#define DMA2_Stream1_IRQHandler Vector124   /**< DMA2 Stream1.              */
-#define DMA2_Stream2_IRQHandler Vector128   /**< DMA2 Stream2.              */
-#define DMA2_Stream3_IRQHandler Vector12C   /**< DMA2 Stream3.              */
-#define DMA2_Stream4_IRQHandler Vector130   /**< DMA2 Stream4.              */
-#define ETH_IRQHandler          Vector134   /**< Ethernet.                  */
-#define ETH_WKUP_IRQHandler     Vector138   /**< Ethernet Wakeup through
-                                                 EXTI line.                 */
-#define CAN2_TX_IRQHandler      Vector13C   /**< CAN2 TX.                   */
-#define CAN2_RX0_IRQHandler     Vector140   /**< CAN2 RX0.                  */
-#define CAN2_RX1_IRQHandler     Vector144   /**< CAN2 RX1.                  */
-#define CAN2_SCE_IRQHandler     Vector148   /**< CAN2 SCE.                  */
-#define OTG_FS_IRQHandler       Vector14C   /**< USB OTG FS.                */
-#define DMA2_Stream5_IRQHandler Vector150   /**< DMA2 Stream5.              */
-#define DMA2_Stream6_IRQHandler Vector154   /**< DMA2 Stream6.              */
-#define DMA2_Stream7_IRQHandler Vector158   /**< DMA2 Stream7.              */
-#define USART6_IRQHandler       Vector15C   /**< USART6.                    */
-#define I2C3_EV_IRQHandler      Vector160   /**< I2C3 Event.                */
-#define I2C3_ER_IRQHandler      Vector164   /**< I2C3 Error.                */
-#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/
-#define OTG_HS_EP1_IN_IRQHandler Vector16C  /**< USB OTG HS End Point 1 In. */
-#define OTG_HS_WKUP_IRQHandler  Vector170   /**< USB OTG HS Wakeup through
-                                                 EXTI line.                 */
-#define OTG_HS_IRQHandler       Vector174   /**< USB OTG HS.                */
-#define DCMI_IRQHandler         Vector178   /**< DCMI.                      */
-#define CRYP_IRQHandler         Vector17C   /**< CRYP.                      */
-#define HASH_RNG_IRQHandler     Vector180   /**< Hash and Rng.              */
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
-#define FPU_IRQHandler          Vector184   /**< Floating Point Unit.       */
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Disables the PWR/RCC initialization in the HAL.
- */
-#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT               FALSE
-#endif
-
-/**
- * @brief   Enables or disables the programmable voltage detector.
- */
-#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE            FALSE
-#endif
-
-/**
- * @brief   Sets voltage level for programmable voltage detector.
- */
-#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS                   STM32_PLS_LEV0
-#endif
-
-/**
- * @brief   Enables the backup RAM regulator.
- */
-#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__)
-#define STM32_BKPRAM_ENABLE         FALSE
-#endif
-
-/**
- * @brief   Enables or disables the HSI clock source.
- */
-#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSI clock source.
- */
-#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED           FALSE
-#endif
-
-/**
- * @brief   Enables or disables the HSE clock source.
- */
-#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSE clock source.
- */
-#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED           FALSE
-#endif
-
-/**
- * @brief   USB/SDIO clock setting.
- */
-#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__)
-#define STM32_CLOCK48_REQUIRED      TRUE
-#endif
-
-/**
- * @brief   Main clock source selection.
- * @note    If the selected clock source is not the PLL then the PLL is not
- *          initialized and started.
- * @note    The default value is calculated for a 168MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW                    STM32_SW_PLL
-#endif
-
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
-/**
- * @brief   Clock source for the PLLs.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 168MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief   PLLM divider value.
- * @note    The allowed values are 2..63.
- * @note    The default value is calculated for a 168MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLM_VALUE            8
-#endif
-
-/**
- * @brief   PLLN multiplier value.
- * @note    The allowed values are 192..432.
- * @note    The default value is calculated for a 168MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLN_VALUE            336
-#endif
-
-/**
- * @brief   PLLP divider value.
- * @note    The allowed values are 2, 4, 6, 8.
- * @note    The default value is calculated for a 168MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLP_VALUE            2
-#endif
-
-/**
- * @brief   PLLQ multiplier value.
- * @note    The allowed values are 2..15.
- * @note    The default value is calculated for a 168MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLQ_VALUE            7
-#endif
-
-#else /* !defined(STM32F4XX) */
-/**
- * @brief   Clock source for the PLLs.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 120MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief   PLLM divider value.
- * @note    The allowed values are 2..63.
- * @note    The default value is calculated for a 120MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLM_VALUE            8
-#endif
-
-/**
- * @brief   PLLN multiplier value.
- * @note    The allowed values are 192..432.
- * @note    The default value is calculated for a 120MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLN_VALUE            240
-#endif
-
-/**
- * @brief   PLLP divider value.
- * @note    The allowed values are 2, 4, 6, 8.
- * @note    The default value is calculated for a 120MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLP_VALUE            2
-#endif
-
-/**
- * @brief   PLLQ multiplier value.
- * @note    The allowed values are 2..15.
- * @note    The default value is calculated for a 120MHz system clock from
- *          an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLQ_VALUE            5
-#endif
-#endif /* !defined(STM32F4XX) */
-
-/**
- * @brief   AHB prescaler value.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE                  STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief   APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1                 STM32_PPRE1_DIV4
-#endif
-
-/**
- * @brief   APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2                 STM32_PPRE2_DIV2
-#endif
-
-/**
- * @brief   RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL                STM32_RTCSEL_LSE
-#endif
-
-/**
- * @brief   RTC HSE prescaler value.
- */
-#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
-#define STM32_RTCPRE_VALUE          8
-#endif
-
-/**
- * @brief   MC01 clock source value.
- * @note    The default value outputs HSI clock on MC01 pin.
- */
-#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
-#define STM32_MCO1SEL               STM32_MCO1SEL_HSI
-#endif
-
-/**
- * @brief   MC01 prescaler value.
- * @note    The default value outputs HSI clock on MC01 pin.
- */
-#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
-#define STM32_MCO1PRE               STM32_MCO1PRE_DIV1
-#endif
-
-/**
- * @brief   MC02 clock source value.
- * @note    The default value outputs SYSCLK / 5 on MC02 pin.
- */
-#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
-#define STM32_MCO2SEL               STM32_MCO2SEL_SYSCLK
-#endif
-
-/**
- * @brief   MC02 prescaler value.
- * @note    The default value outputs SYSCLK / 5 on MC02 pin.
- */
-#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
-#define STM32_MCO2PRE               STM32_MCO2PRE_DIV5
-#endif
-
-/**
- * @brief   I2S clock source.
- */
-#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
-#define STM32_I2SSRC                STM32_I2SSRC_CKIN
-#endif
-
-/**
- * @brief   PLLI2SN multiplier value.
- * @note    The allowed values are 192..432.
- */
-#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SN_VALUE         192
-#endif
-
-/**
- * @brief   PLLI2SR multiplier value.
- * @note    The allowed values are 2..7.
- */
-#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SR_VALUE         5
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F4xx_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"
-#endif
-
-#else /* !defined(STM32F4XX) */
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F2xx_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined"
-#endif
-#endif /* !defined(STM32F4XX) */
-
-/**
- * @brief   Maximum frequency thresholds and wait states for flash access.
- * @note    The values are valid for 2.7V to 3.6V supply range.
- */
-#if defined(STM32F429_439xx) || defined(STM32F427_437xx) ||                 \
-    defined(STM32F40_41xxx) || defined(__DOXYGEN__)
-#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
-#define STM32_0WS_THRESHOLD         30000000
-#define STM32_1WS_THRESHOLD         60000000
-#define STM32_2WS_THRESHOLD         90000000
-#define STM32_3WS_THRESHOLD         120000000
-#define STM32_4WS_THRESHOLD         150000000
-#define STM32_5WS_THRESHOLD         180000000
-#define STM32_6WS_THRESHOLD         0
-#define STM32_7WS_THRESHOLD         0
-#define STM32_8WS_THRESHOLD         0
-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
-#define STM32_0WS_THRESHOLD         24000000
-#define STM32_1WS_THRESHOLD         48000000
-#define STM32_2WS_THRESHOLD         72000000
-#define STM32_3WS_THRESHOLD         96000000
-#define STM32_4WS_THRESHOLD         120000000
-#define STM32_5WS_THRESHOLD         144000000
-#define STM32_6WS_THRESHOLD         168000000
-#define STM32_7WS_THRESHOLD         180000000
-#define STM32_8WS_THRESHOLD         0
-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
-#define STM32_0WS_THRESHOLD         22000000
-#define STM32_1WS_THRESHOLD         44000000
-#define STM32_2WS_THRESHOLD         66000000
-#define STM32_3WS_THRESHOLD         88000000
-#define STM32_4WS_THRESHOLD         110000000
-#define STM32_5WS_THRESHOLD         132000000
-#define STM32_6WS_THRESHOLD         154000000
-#define STM32_7WS_THRESHOLD         176000000
-#define STM32_8WS_THRESHOLD         180000000
-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
-#define STM32_0WS_THRESHOLD         20000000
-#define STM32_1WS_THRESHOLD         40000000
-#define STM32_2WS_THRESHOLD         60000000
-#define STM32_3WS_THRESHOLD         80000000
-#define STM32_4WS_THRESHOLD         100000000
-#define STM32_5WS_THRESHOLD         120000000
-#define STM32_6WS_THRESHOLD         140000000
-#define STM32_7WS_THRESHOLD         168000000
-#define STM32_8WS_THRESHOLD         0
-#else
-#error "invalid VDD voltage specified"
-#endif
-
-#elif defined(STM32F401xx)
-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
-#define STM32_0WS_THRESHOLD         30000000
-#define STM32_1WS_THRESHOLD         60000000
-#define STM32_2WS_THRESHOLD         84000000
-#define STM32_3WS_THRESHOLD         0
-#define STM32_4WS_THRESHOLD         0
-#define STM32_5WS_THRESHOLD         0
-#define STM32_6WS_THRESHOLD         0
-#define STM32_7WS_THRESHOLD         0
-#define STM32_8WS_THRESHOLD         0
-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
-#define STM32_0WS_THRESHOLD         24000000
-#define STM32_1WS_THRESHOLD         48000000
-#define STM32_2WS_THRESHOLD         72000000
-#define STM32_3WS_THRESHOLD         84000000
-#define STM32_4WS_THRESHOLD         0
-#define STM32_5WS_THRESHOLD         0
-#define STM32_6WS_THRESHOLD         0
-#define STM32_7WS_THRESHOLD         0
-#define STM32_8WS_THRESHOLD         0
-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
-#define STM32_0WS_THRESHOLD         18000000
-#define STM32_1WS_THRESHOLD         36000000
-#define STM32_2WS_THRESHOLD         54000000
-#define STM32_3WS_THRESHOLD         72000000
-#define STM32_4WS_THRESHOLD         840000000
-#define STM32_5WS_THRESHOLD         0
-#define STM32_6WS_THRESHOLD         0
-#define STM32_7WS_THRESHOLD         0
-#define STM32_8WS_THRESHOLD         0
-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
-#define STM32_0WS_THRESHOLD         16000000
-#define STM32_1WS_THRESHOLD         32000000
-#define STM32_2WS_THRESHOLD         48000000
-#define STM32_3WS_THRESHOLD         64000000
-#define STM32_4WS_THRESHOLD         800000000
-#define STM32_5WS_THRESHOLD         840000000
-#define STM32_6WS_THRESHOLD         0
-#define STM32_7WS_THRESHOLD         0
-#define STM32_8WS_THRESHOLD         0
-#else
-#error "invalid VDD voltage specified"
-#endif
-
-#else /* STM32F2XX */
-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
-#define STM32_0WS_THRESHOLD         30000000
-#define STM32_1WS_THRESHOLD         60000000
-#define STM32_2WS_THRESHOLD         90000000
-#define STM32_3WS_THRESHOLD         120000000
-#define STM32_4WS_THRESHOLD         0
-#define STM32_5WS_THRESHOLD         0
-#define STM32_6WS_THRESHOLD         0
-#define STM32_7WS_THRESHOLD         0
-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
-#define STM32_0WS_THRESHOLD         24000000
-#define STM32_1WS_THRESHOLD         48000000
-#define STM32_2WS_THRESHOLD         72000000
-#define STM32_3WS_THRESHOLD         96000000
-#define STM32_4WS_THRESHOLD         120000000
-#define STM32_5WS_THRESHOLD         0
-#define STM32_6WS_THRESHOLD         0
-#define STM32_7WS_THRESHOLD         0
-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
-#define STM32_0WS_THRESHOLD         18000000
-#define STM32_1WS_THRESHOLD         36000000
-#define STM32_2WS_THRESHOLD         54000000
-#define STM32_3WS_THRESHOLD         72000000
-#define STM32_4WS_THRESHOLD         90000000
-#define STM32_5WS_THRESHOLD         108000000
-#define STM32_6WS_THRESHOLD         120000000
-#define STM32_7WS_THRESHOLD         0
-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
-#define STM32_0WS_THRESHOLD         16000000
-#define STM32_1WS_THRESHOLD         32000000
-#define STM32_2WS_THRESHOLD         48000000
-#define STM32_3WS_THRESHOLD         64000000
-#define STM32_4WS_THRESHOLD         80000000
-#define STM32_5WS_THRESHOLD         96000000
-#define STM32_6WS_THRESHOLD         112000000
-#define STM32_7WS_THRESHOLD         120000000
-#else
-#error "invalid VDD voltage specified"
-#endif
-#endif /* STM32F2XX */
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) ||                                 \
-    ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) &&                                \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCO1SEL"
-#endif
-
-#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_MCO2SEL"
-#endif
-
-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) &&                                \
-    (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_I2SSRC"
-#endif
-
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) ||                                 \
-    ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) &&                                \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCO1SEL"
-#endif
-
-#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) ||                                 \
-    ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) &&                                \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCO2SEL"
-#endif
-
-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) &&                                \
-    (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_I2SSRC"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSI
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if (STM32_LSECLK == 0)
-#error "LSE frequency not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/**
- * @brief   STM32_PLLM field.
- */
-#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) ||                \
-    defined(__DOXYGEN__)
-#define STM32_PLLM                  (STM32_PLLM_VALUE << 0)
-#else
-#error "invalid STM32_PLLM_VALUE value specified"
-#endif
-
-/**
- * @brief   PLLs input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN              (STM32_HSICLK / STM32_PLLM_VALUE)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/*
- * PLLs input frequency range check.
- */
-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
-/*
- * PLL enable check.
- */
-#if STM32_CLOCK48_REQUIRED ||                                               \
-    (STM32_SW == STM32_SW_PLL) ||                                           \
-    (STM32_MCO1SEL == STM32_MCO1SEL_PLL) ||                                 \
-    (STM32_MCO2SEL == STM32_MCO2SEL_PLL) ||                                 \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL          TRUE
-#else
-#define STM32_ACTIVATE_PLL          FALSE
-#endif
-
-/**
- * @brief   STM32_PLLN field.
- */
-#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) ||              \
-    defined(__DOXYGEN__)
-#define STM32_PLLN                  (STM32_PLLN_VALUE << 6)
-#else
-#error "invalid STM32_PLLN_VALUE value specified"
-#endif
-
-/**
- * @brief   STM32_PLLP field.
- */
-#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLP                  (0 << 16)
-#elif STM32_PLLP_VALUE == 4
-#define STM32_PLLP                  (1 << 16)
-#elif STM32_PLLP_VALUE == 6
-#define STM32_PLLP                  (2 << 16)
-#elif STM32_PLLP_VALUE == 8
-#define STM32_PLLP                  (3 << 16)
-#else
-#error "invalid STM32_PLLP_VALUE value specified"
-#endif
-
-/**
- * @brief   STM32_PLLQ field.
- */
-#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) ||                \
-    defined(__DOXYGEN__)
-#define STM32_PLLQ                  (STM32_PLLQ_VALUE << 24)
-#else
-#error "invalid STM32_PLLQ_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL VCO frequency.
- */
-#define STM32_PLLVCO                (STM32_PLLCLKIN * STM32_PLLN_VALUE)
-
-/*
- * PLL VCO frequency range check.
- */
-#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
-#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT             (STM32_PLLVCO / STM32_PLLP_VALUE)
-
-/*
- * PLL output frequency range check.
- */
-#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
-#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
-#endif
-
-/**
- * @brief   System clock source.
- */
-#if STM32_NO_INIT || defined(__DOXYGEN__)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
-#elif (STM32_SW == STM32_SW_PLL)
-#define STM32_SYSCLK                STM32_PLLCLKOUT
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/* Calculating VOS settings, it is different for each sub-platform.*/
-#if defined(STM32F429_439xx) || defined(STM32F427_437xx) ||                 \
-    defined(__DOXYGEN__)
-#if STM32_SYSCLK <= 120000000
-#define STM32_VOS                   STM32_VOS_SCALE3
-#define STM32_OVERDRIVE_REQUIRED    FALSE
-#elif STM32_SYSCLK <= 144000000
-#define STM32_VOS                   STM32_VOS_SCALE2
-#define STM32_OVERDRIVE_REQUIRED    FALSE
-#elif STM32_SYSCLK <= 168000000
-#define STM32_VOS                   STM32_VOS_SCALE1
-#define STM32_OVERDRIVE_REQUIRED    FALSE
-#else
-#define STM32_VOS                   STM32_VOS_SCALE1
-#define STM32_OVERDRIVE_REQUIRED    TRUE
-#endif
-
-#elif defined(STM32F40_41xxx)
-#if STM32_SYSCLK <= 144000000
-#define STM32_VOS                   STM32_VOS_SCALE2
-#else
-#define STM32_VOS                   STM32_VOS_SCALE1
-#endif
-#define STM32_OVERDRIVE_REQUIRED    FALSE
-
-#elif defined(STM32F401xx)
-#if STM32_SYSCLK <= 60000000
-#define STM32_VOS                   STM32_VOS_SCALE3
-#else
-#define STM32_VOS                   STM32_VOS_SCALE2
-#endif
-#define STM32_OVERDRIVE_REQUIRED    FALSE
-
-#else /* STM32F2XX */
-#define STM32_OVERDRIVE_REQUIRED    FALSE
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/*
- * AHB frequency check.
- */
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                 (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                 (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                 (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                 (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/*
- * APB1 frequency check.
- */
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief   APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                 (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                 (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                 (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                 (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/*
- * APB2 frequency check.
- */
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/*
- * PLLI2S enable check.
- */
-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__)
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLLI2S       TRUE
-#else
-#define STM32_ACTIVATE_PLLI2S       FALSE
-#endif
-
-/**
- * @brief   STM32_PLLI2SN field.
- */
-#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) ||       \
-    defined(__DOXYGEN__)
-#define STM32_PLLI2SN               (STM32_PLLI2SN_VALUE << 6)
-#else
-#error "invalid STM32_PLLI2SN_VALUE value specified"
-#endif
-
-/**
- * @brief   STM32_PLLI2SR field.
- */
-#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) ||           \
-    defined(__DOXYGEN__)
-#define STM32_PLLI2SR               (STM32_PLLI2SR_VALUE << 28)
-#else
-#error "invalid STM32_PLLI2SR_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL VCO frequency.
- */
-#define STM32_PLLI2SVCO             (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE)
-
-/*
- * PLLI2S VCO frequency range check.
- */
-#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) ||                                 \
-    (STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
-#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
-#endif
-
-/**
- * @brief   PLLI2S output clock frequency.
- */
-#define STM32_PLLI2SCLKOUT          (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
-
-/**
- * @brief   MCO1 divider clock.
- */
-#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
-#define STM32_MCO1DIVCLK             STM32_HSICLK
-#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
-#define STM32_MCO1DIVCLK             STM32_LSECLK
-#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
-#define STM32_MCO1DIVCLK             STM32_HSECLK
-#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
-#define STM32_MCO1DIVCLK             STM32_PLLCLKOUT
-#else
-#error "invalid STM32_MCO1SEL value specified"
-#endif
-
-/**
- * @brief   MCO1 output pin clock.
- */
-#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_MCO1CLK                STM32_MCO1DIVCLK
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
-#define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 2)
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
-#define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 3)
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
-#define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 4)
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
-#define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 5)
-#else
-#error "invalid STM32_MCO1PRE value specified"
-#endif
-
-/**
- * @brief   MCO2 divider clock.
- */
-#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
-#define STM32_MCO2DIVCLK             STM32_HSECLK
-#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
-#define STM32_MCO2DIVCLK             STM32_PLLCLKOUT
-#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
-#define STM32_MCO2DIVCLK             STM32_SYSCLK
-#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
-#define STM32_MCO2DIVCLK             STM32_PLLI2S
-#else
-#error "invalid STM32_MCO2SEL value specified"
-#endif
-
-/**
- * @brief   MCO2 output pin clock.
- */
-#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_MCO2CLK                STM32_MCO2DIVCLK
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
-#define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 2)
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
-#define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 3)
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
-#define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 4)
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
-#define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 5)
-#else
-#error "invalid STM32_MCO2PRE value specified"
-#endif
-
-/**
- * @brief   RTC HSE divider setting.
- */
-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) ||            \
-    defined(__DOXYGEN__)
-#define STM32_RTCPRE                (STM32_RTCPRE_VALUE << 16)
-#else
-#error "invalid STM32_RTCPRE value specified"
-#endif
-
-/**
- * @brief   HSE divider toward RTC clock.
- */
-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31))  ||           \
-    defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK             (STM32_HSECLK / STM32_RTCPRE_VALUE)
-#else
-#error "invalid STM32_RTCPRE value specified"
-#endif
-
-/**
- * @brief   RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                0
-#elif STM32_RTCSEL == STM32_RTCSEL_LSE
-#define STM32_RTCCLK                STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                STM32_HSEDIVCLK
-#else
-#error "invalid STM32_RTCSEL value specified"
-#endif
-
-/**
- * @brief   48MHz frequency.
- */
-#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
-#define STM32_PLL48CLK              (STM32_PLLVCO / STM32_PLLQ_VALUE)
-#else
-#define STM32_PLL48CLK              0
-#endif
-
-/**
- * @brief   Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief   Timers 1, 8 clock.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
-#endif
-
-/**
- * @brief   Flash settings.
- */
-#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS             0x00000000
-#elif STM32_HCLK <= STM32_1WS_THRESHOLD
-#define STM32_FLASHBITS             0x00000001
-#elif STM32_HCLK <= STM32_2WS_THRESHOLD
-#define STM32_FLASHBITS             0x00000002
-#elif STM32_HCLK <= STM32_3WS_THRESHOLD
-#define STM32_FLASHBITS             0x00000003
-#elif STM32_HCLK <= STM32_4WS_THRESHOLD
-#define STM32_FLASHBITS             0x00000004
-#elif STM32_HCLK <= STM32_5WS_THRESHOLD
-#define STM32_FLASHBITS             0x00000005
-#elif STM32_HCLK <= STM32_6WS_THRESHOLD
-#define STM32_FLASHBITS             0x00000006
-#elif STM32_HCLK <= STM32_7WS_THRESHOLD
-#define STM32_FLASHBITS             0x00000007
-#else
-#define STM32_FLASHBITS             0x00000008
-#endif
-
-/* There are differences in vector names in the various sub-families,
-   normalizing.*/
-#define TIM1_BRK_IRQn       TIM1_BRK_TIM9_IRQn
-#define TIM1_UP_IRQn        TIM1_UP_TIM10_IRQn
-#define TIM1_TRG_COM_IRQn   TIM1_TRG_COM_TIM11_IRQn
-#define TIM8_BRK_IRQn       TIM8_BRK_TIM12_IRQn
-#define TIM8_UP_IRQn        TIM8_UP_TIM13_IRQn
-#define TIM8_TRG_COM_IRQn   TIM8_TRG_COM_TIM14_IRQn
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief   Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This service is implemented by returning the content of the
- *          DWT_CYCCNT register.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value()         DWT_CYCCNT
-
-/**
- * @brief   Realtime counter frequency.
- * @note    The DWT_CYCCNT register is incremented directly by the system
- *          clock so this function returns STM32_HCLK.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency()     STM32_HCLK
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-/* STM32 helpers and custom drivers.*/
-#include "stm32_isr.h"
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void stm32_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F4xx/platform.dox b/os/hal/platforms/STM32F4xx/platform.dox
deleted file mode 100644
index 38e98bd59..000000000
--- a/os/hal/platforms/STM32F4xx/platform.dox
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM32F4xx_DRIVERS STM32F4xx/STM32F2xx Drivers
- * @details This section describes all the supported drivers on the STM32F4xx
- *          and STM32F2xx platform and the implementation details of the single
- *          drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup STM32F4xx_HAL STM32F4xx Initialization Support
- * @details The STM32F4xx HAL support is responsible for system initialization.
- *
- * @section stm32f4xx_hal_1 Supported HW resources
- * - PLL1.
- * - PLL2.
- * - RCC.
- * - Flash.
- * .
- * @section stm32f4xx_hal_2 STM32F4xx HAL driver implementation features
- * - PLL startup and stabilization.
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash wait states initialization based on the selected clock options.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * - DMA support initialization.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_ADC STM32F4xx ADC Support
- * @details The STM32F4xx ADC driver supports the ADC peripherals using DMA
- *          channels for maximum performance.
- *
- * @section stm32f4xx_adc_1 Supported HW resources
- * - ADC1.
- * - ADC2.
- * - ADC3.
- * - DMA2.
- * .
- * @section stm32f4xx_adc_2 STM32F4xx ADC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Streaming conversion using DMA for maximum performance.
- * - Programmable ADC interrupt priority level.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - DMA and ADC errors detection.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_CAN STM32F4xx CAN Support
- * @details The STM32F4xx CAN driver uses the CAN peripherals.
- *
- * @section stm32f4xx_can_1 Supported HW resources
- * - bxCAN1.
- * .
- * @section stm32f4xx_can_2 STM32F4xx CAN driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Support for bxCAN sleep mode.
- * - Programmable bxCAN interrupts priority level.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_EXT STM32F4xx EXT Support
- * @details The STM32F4xx EXT driver uses the EXTI peripheral.
- *
- * @section stm32f4xx_ext_1 Supported HW resources
- * - EXTI.
- * .
- * @section stm32f4xx_ext_2 STM32F4xx EXT driver implementation features
- * - Each EXTI channel can be independently enabled and programmed.
- * - Programmable EXTI interrupts priority level.
- * - Capability to work as event sources (WFE) rather than interrupt sources.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_GPT STM32F4xx GPT Support
- * @details The STM32F4xx GPT driver uses the TIMx peripherals.
- *
- * @section stm32f4xx_gpt_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * - TIM8.
- * .
- * @section stm32f4xx_gpt_2 STM32F4xx GPT driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_ICU STM32F4xx ICU Support
- * @details The STM32F4xx ICU driver uses the TIMx peripherals.
- *
- * @section stm32f4xx_icu_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * - TIM8.
- * .
- * @section stm32f4xx_icu_2 STM32F4xx ICU driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_MAC STM32F4xx MAC Support
- * @details The STM32F4xx MAC driver supports the ETH peripheral.
- *
- * @section stm32f4xx_mac_1 Supported HW resources
- * - ETH.
- * - PHY (external).
- * .
- * @section stm32f4xx_mac_2 STM32F4xx MAC driver implementation features
- * - Dedicated DMA operations.
- * - Support for checksum off-loading.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_PAL STM32F4xx PAL Support
- * @details The STM32F4xx PAL driver uses the GPIO peripherals.
- *
- * @section stm32f4xx_pal_1 Supported HW resources
- * - GPIOA.
- * - GPIOB.
- * - GPIOC.
- * - GPIOD.
- * - GPIOE.
- * - GPIOF.
- * - GPIOG.
- * - GPIOH.
- * - GPIOI.
- * .
- * @section stm32f4xx_pal_2 STM32F4xx PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 16 bits wide ports.
- * - Atomic set/reset functions.
- * - Atomic set+reset function (atomic bus operations).
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section stm32f4xx_pal_3 Supported PAL setup modes
- * The STM32F4xx PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_INPUT_PULLDOWN.
- * - @p PAL_MODE_INPUT_ANALOG.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * - @p PAL_MODE_ALTERNATE (non standard).
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section stm32f4xx_pal_4 Suboptimal behavior
- * The STM32F4xx GPIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_PWM STM32F4xx PWM Support
- * @details The STM32F4xx PWM driver uses the TIMx peripherals.
- *
- * @section stm32f4xx_pwm_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * - TIM8.
- * .
- * @section stm32f4xx_pwm_2 STM32F4xx PWM driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Four independent PWM channels per timer.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_SDC STM32F4xx SDC Support
- * @details The STM32F4xx SDC driver uses the SDIO peripheral.
- *
- * @section stm32f4xx_sdc_1 Supported HW resources
- * - SDIO.
- * - DMA2.
- * .
- * @section stm32f4xx_sdc_2 STM32F4xx SDC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_SERIAL STM32F4xx Serial Support
- * @details The STM32F4xx Serial driver uses the USART/UART peripherals in a
- *          buffered, interrupt driven, implementation.
- *
- * @section stm32f4xx_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3.
- * - UART4.
- * - UART5.
- * - USART6.
- * .
- * @section stm32f4xx_serial_2 STM32F4xx Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable priority levels for each UART/USART.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_SPI STM32F4xx SPI Support
- * @details The SPI driver supports the STM32F4xx SPI peripherals using DMA
- *          channels for maximum performance.
- *
- * @section stm32f4xx_spi_1 Supported HW resources
- * - SPI1.
- * - SPI2.
- * - SPI3.
- * - DMA1.
- * - DMA2.
- * .
- * @section stm32f4xx_spi_2 STM32F4xx SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SPI can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each SPI.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_UART STM32F4xx UART Support
- * @details The UART driver supports the STM32F4xx USART peripherals using DMA
- *          channels for maximum performance.
- *
- * @section stm32f4xx_uart_1 Supported HW resources
- * The UART driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3.
- * - DMA1.
- * - DMA2.
- * .
- * @section stm32f4xx_uart_2 STM32F4xx UART driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each UART/USART.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_PLATFORM_DRIVERS STM32F4xx Platform Drivers
- * @details Platform support drivers. Platform drivers do not implement HAL
- *          standard driver templates, their role is to support platform
- *          specific functionalities.
- *
- * @ingroup STM32F4xx_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_DMA STM32F4xx DMA Support
- * @details This DMA helper driver is used by the other drivers in order to
- *          access the shared DMA resources in a consistent way.
- *
- * @section stm32f4xx_dma_1 Supported HW resources
- * The DMA driver can support any of the following hardware resources:
- * - DMA1.
- * - DMA2.
- * .
- * @section stm32f4xx_dma_2 STM32F4xx DMA driver implementation features
- * - Exports helper functions/macros to the other drivers that share the
- *   DMA resource.
- * - Automatic DMA clock stop when not in use by any driver.
- * - DMA streams and interrupt vectors sharing among multiple drivers.
- * .
- * @ingroup STM32F4xx_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_ISR STM32F4xx ISR Support
- * @details This ISR helper driver is used by the other drivers in order to
- *          map ISR names to physical vector names.
- *
- * @ingroup STM32F4xx_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup STM32F4xx_RCC STM32F4xx RCC Support
- * @details This RCC helper driver is used by the other drivers in order to
- *          access the shared RCC resources in a consistent way.
- *
- * @section stm32f4xx_rcc_1 Supported HW resources
- * - RCC.
- * .
- * @section stm32f4xx_rcc_2 STM32F4xx RCC driver implementation features
- * - Peripherals reset.
- * - Peripherals clock enable.
- * - Peripherals clock disable.
- * .
- * @ingroup STM32F4xx_PLATFORM_DRIVERS
- */
diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk
deleted file mode 100644
index 4cebeb169..000000000
--- a/os/hal/platforms/STM32F4xx/platform.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-# List of all the STM32F2xx/STM32F4xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F4xx/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \
-              ${CHIBIOS}/os/hal/platforms/STM32 \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1
diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.c b/os/hal/platforms/STM32F4xx/stm32_dma.c
deleted file mode 100644
index 1d6ce01bd..000000000
--- a/os/hal/platforms/STM32F4xx/stm32_dma.c
+++ /dev/null
@@ -1,528 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F4xx/stm32_dma.c
- * @brief   Enhanced DMA helper driver code.
- *
- * @addtogroup STM32F4xx_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- *          shared resource, this driver allows to allocate and free DMA
- *          streams at runtime in order to allow all the other device
- *          drivers to coordinate the access to the resource.
- * @note    The DMA ISR handlers are all declared into this module because
- *          sharing, the various device drivers can associate a callback to
- *          ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
-   has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK     0x000000FF
-
-/**
- * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK     0x0000FF00
-
-/**
- * @brief   Post-reset value of the stream CR register.
- */
-#define STM32_DMA_CR_RESET_VALUE    0x00000000
-
-/**
- * @brief   Post-reset value of the stream FCR register.
- */
-#define STM32_DMA_FCR_RESET_VALUE   0x00000021
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- *          identifier and the involved physical registers.
- * @note    Don't use this array directly, use the appropriate wrapper macros
- *          instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
-  {DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn},
-  {DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn},
-  {DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn},
-  {DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn},
-  {DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn},
-  {DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn},
-  {DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn},
-  {DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn},
-  {DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn},
-  {DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn},
-  {DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn},
-  {DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn},
-  {DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn},
-  {DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn},
-  {DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn},
-  {DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn},
-};
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DMA ISR redirector type.
- */
-typedef struct {
-  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
-  void                  *dma_param;     /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief   Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief   DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA1 stream 0 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = flags << 0;
-  if (dma_isr_redir[0].dma_func)
-    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = flags << 6;
-  if (dma_isr_redir[1].dma_func)
-    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = flags << 16;
-  if (dma_isr_redir[2].dma_func)
-    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = flags << 22;
-  if (dma_isr_redir[3].dma_func)
-    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = flags << 0;
-  if (dma_isr_redir[4].dma_func)
-    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = flags << 6;
-  if (dma_isr_redir[5].dma_func)
-    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = flags << 16;
-  if (dma_isr_redir[6].dma_func)
-    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = flags << 22;
-  if (dma_isr_redir[7].dma_func)
-    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 0 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = flags << 0;
-  if (dma_isr_redir[8].dma_func)
-    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = flags << 6;
-  if (dma_isr_redir[9].dma_func)
-    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = flags << 16;
-  if (dma_isr_redir[10].dma_func)
-    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = flags << 22;
-  if (dma_isr_redir[11].dma_func)
-    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = flags << 0;
-  if (dma_isr_redir[12].dma_func)
-    dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = flags << 6;
-  if (dma_isr_redir[13].dma_func)
-    dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 6 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = flags << 16;
-  if (dma_isr_redir[14].dma_func)
-    dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 7 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = flags << 22;
-  if (dma_isr_redir[15].dma_func)
-    dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
-  int i;
-
-  dma_streams_mask = 0;
-  for (i = 0; i < STM32_DMA_STREAMS; i++) {
-    _stm32_dma_streams[i].stream->CR = 0;
-    dma_isr_redir[i].dma_func = NULL;
-  }
-  DMA1->LIFCR = 0xFFFFFFFF;
-  DMA1->HIFCR = 0xFFFFFFFF;
-  DMA2->LIFCR = 0xFFFFFFFF;
-  DMA2->HIFCR = 0xFFFFFFFF;
-}
-
-/**
- * @brief   Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- *          The function also enables the IRQ vector associated to the stream
- *          and initializes its priority.
- * @pre     The stream must not be already in use or an error is returned.
- * @post    The stream is allocated and the default ISR handler redirected
- *          to the specified function.
- * @post    The stream ISR vector is enabled and its priority configured.
- * @post    The stream must be freed using @p dmaStreamRelease() before it can
- *          be reused with another peripheral.
- * @post    The stream is in its post-reset state.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] priority  IRQ priority mask for the DMA stream
- * @param[in] func      handling function pointer, can be @p NULL
- * @param[in] param     a parameter to be passed to the handling function
- * @return              The operation status.
- * @retval FALSE        no error, stream taken.
- * @retval TRUE         error, stream already taken.
- *
- * @special
- */
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                         uint32_t priority,
-                         stm32_dmaisr_t func,
-                         void *param) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
-
-  /* Checks if the stream is already taken.*/
-  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
-    return TRUE;
-
-  /* Marks the stream as allocated.*/
-  dma_isr_redir[dmastp->selfindex].dma_func  = func;
-  dma_isr_redir[dmastp->selfindex].dma_param = param;
-  dma_streams_mask |= (1 << dmastp->selfindex);
-
-  /* Enabling DMA clocks required by the current streams set.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
-    rccEnableDMA1(FALSE);
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
-    rccEnableDMA2(FALSE);
-
-  /* Putting the stream in a safe state.*/
-  dmaStreamDisable(dmastp);
-  dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
-  dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
-
-  /* Enables the associated IRQ vector if a callback is defined.*/
-  if (func != NULL)
-    nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
-
-  return FALSE;
-}
-
-/**
- * @brief   Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- *          Trying to release a unallocated stream is an illegal operation
- *          and is trapped if assertions are enabled.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    The stream is again available.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamRelease");
-
-  /* Check if the streams is not taken.*/
-  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
-              "dmaStreamRelease(), #1", "not allocated");
-
-  /* Disables the associated IRQ vector.*/
-  nvicDisableVector(dmastp->vector);
-
-  /* Marks the stream as not allocated.*/
-  dma_streams_mask &= ~(1 << dmastp->selfindex);
-
-  /* Shutting down clocks that are no more required, if any.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
-    rccDisableDMA1(FALSE);
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
-    rccDisableDMA2(FALSE);
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h
deleted file mode 100644
index 62b0fbd43..000000000
--- a/os/hal/platforms/STM32F4xx/stm32_dma.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F4xx/stm32_dma.h
- * @brief   Enhanced-DMA helper driver header.
- * @note    This file requires definitions from the ST STM32F4xx header file
- *          stm32f4xx.h.
- *
- * @addtogroup STM32F4xx_DMA
- * @{
- */
-
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Total number of DMA streams.
- * @note    This is the total number of streams among all the DMA units.
- */
-#define STM32_DMA_STREAMS           16
-
-/**
- * @brief   Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK          0x3D
-
-/**
- * @brief   Returns the channel associated to the specified stream.
- *
- * @param[in] id        the unique numeric stream identifier
- * @param[in] c         a stream/channel association word, one channel per
- *                      nibble
- * @return              Returns the channel associated to the stream.
- */
-#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7)
-
-/**
- * @brief   Checks if a DMA priority is within the valid range.
- * @param[in] prio      DMA priority
- *
- * @retval              The check result.
- * @retval FALSE        invalid DMA priority.
- * @retval TRUE         correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
-
-/**
- * @brief   Returns an unique numeric identifier for a DMA stream.
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              An unique numeric stream identifier.
- */
-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream))
-
-/**
- * @brief   Returns a DMA stream identifier mask.
- *
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              A DMA stream identifier mask.
- */
-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
-  (1 << STM32_DMA_STREAM_ID(dma, stream))
-
-/**
- * @brief   Checks if a DMA stream unique identifier belongs to a mask.
- * @param[in] id        the stream numeric identifier
- * @param[in] mask      the stream numeric identifiers mask
- *
- * @retval              The check result.
- * @retval FALSE        id does not belong to the mask.
- * @retval TRUE         id belongs to the mask.
- */
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
-
-/**
- * @name    DMA streams identifiers
- * @{
- */
-/**
- * @brief   Returns a pointer to a stm32_dma_stream_t structure.
- *
- * @param[in] id        the stream numeric identifier
- * @return              A pointer to the stm32_dma_stream_t constant structure
- *                      associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM0          STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(4)
-#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(5)
-#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(6)
-#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(7)
-#define STM32_DMA2_STREAM0          STM32_DMA_STREAM(8)
-#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(9)
-#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(10)
-#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(11)
-#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(12)
-#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(13)
-#define STM32_DMA2_STREAM6          STM32_DMA_STREAM(14)
-#define STM32_DMA2_STREAM7          STM32_DMA_STREAM(15)
-/** @} */
-
-/**
- * @name    CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN             DMA_SxCR_EN
-#define STM32_DMA_CR_TEIE           DMA_SxCR_TEIE
-#define STM32_DMA_CR_HTIE           DMA_SxCR_HTIE
-#define STM32_DMA_CR_TCIE           DMA_SxCR_TCIE
-#define STM32_DMA_CR_DIR_MASK       DMA_SxCR_DIR
-#define STM32_DMA_CR_DIR_P2M        0
-#define STM32_DMA_CR_DIR_M2P        DMA_SxCR_DIR_0
-#define STM32_DMA_CR_DIR_M2M        DMA_SxCR_DIR_1
-#define STM32_DMA_CR_CIRC           DMA_SxCR_CIRC
-#define STM32_DMA_CR_PINC           DMA_SxCR_PINC
-#define STM32_DMA_CR_MINC           DMA_SxCR_MINC
-#define STM32_DMA_CR_PSIZE_MASK     DMA_SxCR_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE     0
-#define STM32_DMA_CR_PSIZE_HWORD    DMA_SxCR_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD     DMA_SxCR_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK     DMA_SxCR_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE     0
-#define STM32_DMA_CR_MSIZE_HWORD    DMA_SxCR_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD     DMA_SxCR_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
-                                     STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK        DMA_SxCR_PL
-#define STM32_DMA_CR_PL(n)          ((n) << 16)
-/** @} */
-
-/**
- * @name    CR register constants only found in STM32F2xx/STM32F4xx
- * @{
- */
-#define STM32_DMA_CR_DMEIE          DMA_SxCR_DMEIE
-#define STM32_DMA_CR_PFCTRL         DMA_SxCR_PFCTRL
-#define STM32_DMA_CR_PINCOS         DMA_SxCR_PINCOS
-#define STM32_DMA_CR_DBM            DMA_SxCR_DBM
-#define STM32_DMA_CR_CT             DMA_SxCR_CT
-#define STM32_DMA_CR_PBURST_MASK    DMA_SxCR_PBURST
-#define STM32_DMA_CR_PBURST_SINGLE  0
-#define STM32_DMA_CR_PBURST_INCR4   DMA_SxCR_PBURST_0
-#define STM32_DMA_CR_PBURST_INCR8   DMA_SxCR_PBURST_1
-#define STM32_DMA_CR_PBURST_INCR16  (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
-#define STM32_DMA_CR_MBURST_MASK    DMA_SxCR_MBURST
-#define STM32_DMA_CR_MBURST_SINGLE  0
-#define STM32_DMA_CR_MBURST_INCR4   DMA_SxCR_MBURST_0
-#define STM32_DMA_CR_MBURST_INCR8   DMA_SxCR_MBURST_1
-#define STM32_DMA_CR_MBURST_INCR16  (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
-#define STM32_DMA_CR_CHSEL_MASK     DMA_SxCR_CHSEL
-#define STM32_DMA_CR_CHSEL(n)       ((n) << 25)
-/** @} */
-
-/**
- * @name    FCR register constants only found in STM32F2xx/STM32F4xx
- * @{
- */
-#define STM32_DMA_FCR_FEIE          DMA_SxFCR_FEIE
-#define STM32_DMA_FCR_FS_MASK       DMA_SxFCR_FS
-#define STM32_DMA_FCR_DMDIS         DMA_SxFCR_DMDIS
-#define STM32_DMA_FCR_FTH_MASK      DMA_SxFCR_FTH
-#define STM32_DMA_FCR_FTH_1Q        0
-#define STM32_DMA_FCR_FTH_HALF      DMA_SxFCR_FTH_0
-#define STM32_DMA_FCR_FTH_3Q        DMA_SxFCR_FTH_1
-#define STM32_DMA_FCR_FTH_FULL      (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)
-/** @} */
-
-/**
- * @name    Status flags passed to the ISR callbacks
- */
-#define STM32_DMA_ISR_FEIF          DMA_LISR_FEIF0
-#define STM32_DMA_ISR_DMEIF         DMA_LISR_DMEIF0
-#define STM32_DMA_ISR_TEIF          DMA_LISR_TEIF0
-#define STM32_DMA_ISR_HTIF          DMA_LISR_HTIF0
-#define STM32_DMA_ISR_TCIF          DMA_LISR_TCIF0
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA stream descriptor structure.
- */
-typedef struct {
-  DMA_Stream_TypeDef    *stream;        /**< @brief Associated DMA stream.  */
-  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
-  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
-                                             register.                      */
-  uint8_t               selfindex;      /**< @brief Index to self in array. */
-  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
-} stm32_dma_stream_t;
-
-/**
- * @brief   STM32 DMA ISR function type.
- *
- * @param[in] p         parameter for the registered function
- * @param[in] flags     pre-shifted content of the xISR register, the bits
- *                      are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Associates a peripheral data register to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the PAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) {                              \
-  (dmastp)->stream->PAR  = (uint32_t)(addr);                                \
-}
-
-/**
- * @brief   Associates a memory destination to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the M0AR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) {                                 \
-  (dmastp)->stream->M0AR  = (uint32_t)(addr);                               \
-}
-
-/**
- * @brief   Associates an alternate memory destination to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the M1AR register
- *
- * @special
- */
-#define dmaStreamSetMemory1(dmastp, addr) {                                 \
-  (dmastp)->stream->M1AR  = (uint32_t)(addr);                               \
-}
-
-/**
- * @brief   Sets the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] size      value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) {                         \
-  (dmastp)->stream->NDTR  = (uint32_t)(size);                               \
-}
-
-/**
- * @brief   Returns the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @return              The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR))
-
-/**
- * @brief   Programs the stream mode settings.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) {                                    \
-  (dmastp)->stream->CR  = (uint32_t)(mode);                                 \
-}
-
-/**
- * @brief   Programs the stream FIFO settings.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the FCR register
- *
- * @special
- */
-#define dmaStreamSetFIFO(dmastp, mode) {                                    \
-  (dmastp)->stream->FCR = (uint32_t)(mode);                                 \
-}
-
-/**
- * @brief   DMA stream enable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) {                                           \
-  (dmastp)->stream->CR |= STM32_DMA_CR_EN;                                  \
-}
-
-/**
- * @brief   DMA stream disable.
- * @details The function disables the specified stream, waits for the disable
- *          operation to complete and then clears any pending interrupt.
- * @note    This function can be invoked in both ISR or thread context.
- * @note    Interrupts enabling flags are set to zero after this call, see
- *          bug 3607518.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) {                                          \
-  (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE  |        \
-                            STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE |        \
-                            STM32_DMA_CR_EN);                               \
-  while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0)                     \
-    ;                                                                       \
-  dmaStreamClearInterrupt(dmastp);                                          \
-}
-
-/**
- * @brief   DMA stream interrupt sources clear.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) {                                   \
-  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
-}
-
-/**
- * @brief   Starts a memory to memory operation using the specified stream.
- * @note    The default transfer data mode is "byte to byte" but it can be
- *          changed by specifying extra options in the @p mode parameter.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register, this value
- *                      is implicitly ORed with:
- *                      - @p STM32_DMA_CR_MINC
- *                      - @p STM32_DMA_CR_PINC
- *                      - @p STM32_DMA_CR_DIR_M2M
- *                      - @p STM32_DMA_CR_EN
- *                      .
- * @param[in] src       source address
- * @param[in] dst       destination address
- * @param[in] n         number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
-  dmaStreamSetPeripheral(dmastp, src);                                      \
-  dmaStreamSetMemory0(dmastp, dst);                                         \
-  dmaStreamSetTransactionSize(dmastp, n);                                   \
-  dmaStreamSetMode(dmastp, (mode) |                                         \
-                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
-                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
-}
-
-/**
- * @brief   Polled wait for DMA transfer end.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) {                                         \
-  while ((dmastp)->stream->NDTR > 0)                                        \
-    ;                                                                       \
-  dmaStreamDisable(dmastp);                                                 \
-}
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dmaInit(void);
-  bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                           uint32_t priority,
-                           stm32_dmaisr_t func,
-                           void *param);
-  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F4xx/stm32_isr.h b/os/hal/platforms/STM32F4xx/stm32_isr.h
deleted file mode 100644
index a763e28e7..000000000
--- a/os/hal/platforms/STM32F4xx/stm32_isr.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F4xx/stm32_isr.h
- * @brief   ISR remapper driver header.
- *
- * @addtogroup STM32F4xx_ISR
- * @{
- */
-
-#ifndef _STM32_ISR_H_
-#define _STM32_ISR_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    ISR names and numbers remapping
- * @{
- */
-/*
- * CAN units.
- */
-#define STM32_CAN1_TX_HANDLER       CAN1_TX_IRQHandler
-#define STM32_CAN1_RX0_HANDLER      CAN1_RX0_IRQHandler
-#define STM32_CAN1_RX1_HANDLER      CAN1_RX1_IRQHandler
-#define STM32_CAN1_SCE_HANDLER      CAN1_SCE_IRQHandler
-#define STM32_CAN2_TX_HANDLER       CAN2_TX_IRQHandler
-#define STM32_CAN2_RX0_HANDLER      CAN2_RX0_IRQHandler
-#define STM32_CAN2_RX1_HANDLER      CAN2_RX1_IRQHandler
-#define STM32_CAN2_SCE_HANDLER      CAN2_SCE_IRQHandler
-
-#define STM32_CAN1_TX_NUMBER        CAN1_TX_IRQn
-#define STM32_CAN1_RX0_NUMBER       CAN1_RX0_IRQn
-#define STM32_CAN1_RX1_NUMBER       CAN1_RX1_IRQn
-#define STM32_CAN1_SCE_NUMBER       CAN1_SCE_IRQn
-#define STM32_CAN2_TX_NUMBER        CAN2_TX_IRQn
-#define STM32_CAN2_RX0_NUMBER       CAN2_RX0_IRQn
-#define STM32_CAN2_RX1_NUMBER       CAN2_RX1_IRQn
-#define STM32_CAN2_SCE_NUMBER       CAN2_SCE_IRQn
-
-/*
- * OTG units.
- */
-#define STM32_OTG1_HANDLER          Vector14C
-#define STM32_OTG2_HANDLER          Vector174
-#define STM32_OTG2_EP1OUT_HANDLER   Vector168
-#define STM32_OTG2_EP1IN_HANDLER    Vector16C
-
-#define STM32_OTG1_NUMBER           OTG_FS_IRQn
-#define STM32_OTG2_NUMBER           OTG_HS_IRQn
-#define STM32_OTG2_EP1OUT_NUMBER    OTG_HS_EP1_OUT_IRQn
-#define STM32_OTG2_EP1IN_NUMBER     OTG_HS_EP1_IN_IRQn
-
-/*
- * SDIO unit.
- */
-#define STM32_SDIO_HANDLER          SDIO_IRQHandler
-
-#define STM32_SDIO_NUMBER           SDIO_IRQn
-
-/*
- * TIM units.
- */
-#define STM32_TIM1_UP_HANDLER       TIM1_UP_IRQHandler
-#define STM32_TIM1_CC_HANDLER       TIM1_CC_IRQHandler
-#define STM32_TIM2_HANDLER          TIM2_IRQHandler
-#define STM32_TIM3_HANDLER          TIM3_IRQHandler
-#define STM32_TIM4_HANDLER          TIM4_IRQHandler
-#define STM32_TIM5_HANDLER          TIM5_IRQHandler
-#define STM32_TIM6_HANDLER          TIM6_IRQHandler
-#define STM32_TIM7_HANDLER          TIM7_IRQHandler
-#define STM32_TIM8_UP_HANDLER       TIM8_UP_IRQHandler
-#define STM32_TIM8_CC_HANDLER       TIM8_CC_IRQHandler
-#define STM32_TIM9_HANDLER          TIM1_BRK_IRQHandler
-#define STM32_TIM11_HANDLER         TIM1_TRG_COM_IRQHandler
-#define STM32_TIM12_HANDLER         TIM8_BRK_IRQHandler
-#define STM32_TIM14_HANDLER         TIM8_TRG_COM_IRQHandler
-
-#define STM32_TIM1_UP_NUMBER        TIM1_UP_TIM10_IRQn
-#define STM32_TIM1_CC_NUMBER        TIM1_CC_IRQn
-#define STM32_TIM2_NUMBER           TIM2_IRQn
-#define STM32_TIM3_NUMBER           TIM3_IRQn
-#define STM32_TIM4_NUMBER           TIM4_IRQn
-#define STM32_TIM5_NUMBER           TIM5_IRQn
-#define STM32_TIM6_NUMBER           TIM6_DAC_IRQn
-#define STM32_TIM7_NUMBER           TIM7_IRQn
-#define STM32_TIM8_UP_NUMBER        TIM8_UP_TIM13_IRQn
-#define STM32_TIM8_CC_NUMBER        TIM8_CC_IRQn
-#define STM32_TIM9_NUMBER           TIM1_BRK_TIM9_IRQn
-#define STM32_TIM11_NUMBER          TIM1_TRG_COM_TIM11_IRQn
-#define STM32_TIM12_NUMBER          TIM8_BRK_TIM12_IRQn
-#define STM32_TIM14_NUMBER          TIM8_TRG_COM_TIM14_IRQn
-
-/*
- * USART units.
- */
-#define STM32_USART1_HANDLER        USART1_IRQHandler
-#define STM32_USART2_HANDLER        USART2_IRQHandler
-#define STM32_USART3_HANDLER        USART3_IRQHandler
-#define STM32_UART4_HANDLER         UART4_IRQHandler
-#define STM32_UART5_HANDLER         UART5_IRQHandler
-#define STM32_USART6_HANDLER        USART6_IRQHandler
-
-#define STM32_USART1_NUMBER         USART1_IRQn
-#define STM32_USART2_NUMBER         USART2_IRQn
-#define STM32_USART3_NUMBER         USART3_IRQn
-#define STM32_UART4_NUMBER          UART4_IRQn
-#define STM32_UART5_NUMBER          UART5_IRQn
-#define STM32_USART6_NUMBER         USART6_IRQn
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#endif /* _STM32_ISR_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F4xx/stm32f2xx.h b/os/hal/platforms/STM32F4xx/stm32f2xx.h
deleted file mode 100644
index f4506b2fe..000000000
--- a/os/hal/platforms/STM32F4xx/stm32f2xx.h
+++ /dev/null
@@ -1,6881 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f2xx.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    18-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32F2xx devices.
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral�s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral�s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_STDPERIPH_DRIVER"
-  *              - To change few application-specific parameters such as the HSE 
-  *                crystal frequency
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f2xx
-  * @{
-  */
-    
-#ifndef __STM32F2xx_H
-#define __STM32F2xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32F2XX) 
-  #define STM32F2XX
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-
-#if !defined (STM32F2XX)
- #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)"
-#endif
-
-#if !defined  (USE_STDPERIPH_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_STDPERIPH_DRIVER*/
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application 
-   
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */           
-#define HSE_VALUE            ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-   Timeout value 
-   */
-#define HSE_STARTUP_TIMEOUT  ((uint16_t)0x0500)   /*!< Time out for HSE start up */
-#define HSI_VALUE            ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-
-/**
- * @brief STM32F2Xxx Standard Peripherals Library version number V1.0.0
-   */
-#define __STM32F2XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
-#define __STM32F2XX_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32F2XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F2XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F2XX_STDPERIPH_VERSION        ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\
-                                             |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\
-                                             |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\
-                                             |(__STM32F2XX_STDPERIPH_VERSION_RC))
-                                             
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __MPU_PRESENT             1 /*!< STM32F2XX provide an MPU */
-#define __NVIC_PRIO_BITS          4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * @brief STM32F2XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */ 
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80      /*!< Hash and Rng global interrupt                                     */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-/* CHIBIOS FIX */
-/* #include "system_stm32f2xx.h" */
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t  s32;
-typedef int16_t s16;
-typedef int8_t  s8;
-
-typedef const int32_t sc32;  /*!< Read Only */
-typedef const int16_t sc16;  /*!< Read Only */
-typedef const int8_t sc8;   /*!< Read Only */
-
-typedef __IO int32_t  vs32;
-typedef __IO int16_t  vs16;
-typedef __IO int8_t   vs8;
-
-typedef __I int32_t vsc32;  /*!< Read Only */
-typedef __I int16_t vsc16;  /*!< Read Only */
-typedef __I int8_t vsc8;   /*!< Read Only */
-
-typedef uint32_t  u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-typedef const uint32_t uc32;  /*!< Read Only */
-typedef const uint16_t uc16;  /*!< Read Only */
-typedef const uint8_t uc8;   /*!< Read Only */
-
-typedef __IO uint32_t  vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t  vu8;
-
-typedef __I uint32_t vuc32;  /*!< Read Only */
-typedef __I uint16_t vuc16;  /*!< Read Only */
-typedef __I uint8_t vuc8;   /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;  /* added for STM32F2xx */
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;  /* added for STM32F2xx */
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register, Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,            Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,     Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,         Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,        Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register, Address offset: 0x14 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-} FSMC_Bank2_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank3
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FSMC_Bank3_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-/* CHIBIOS FIX */
-#if 0
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
-  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x24-0x28 */
-} GPIO_TypeDef;
-#endif
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                   */
-  __IO uint16_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                   */
-  __IO uint16_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                   */
-  __IO uint16_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                   */
-  __IO uint16_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                   */
-  __IO uint16_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                   */
-  __IO uint16_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                   */
-  __IO uint16_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                   */
-  __IO uint16_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                   */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  uint32_t RESERVED1;    /*!< Reserved, 0x28                                                                 */
-  uint32_t RESERVED2;    /*!< Reserved, 0x2C                                                                 */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  uint32_t RESERVED3;    /*!< Reserved, 0x38                                                                 */
-  uint32_t RESERVED4;    /*!< Reserved, 0x3C                                                                 */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  uint32_t RESERVED5;    /*!< Reserved, 0x44                                                                 */
-  uint32_t RESERVED6;    /*!< Reserved, 0x48                                                                 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
-  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
-  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
-  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
-  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
-  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
-  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
-  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
-  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
-  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
-  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
-  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
-  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
-  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
-  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
-  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
-  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
-  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
-  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
-  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
-  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
-  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
-  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
-  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
-  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
-  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Crypto Processor
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< CRYP control register,                            Address offset: 0x00 */
-  __IO uint32_t SR;     /*!< CRYP status register,                             Address offset: 0x04 */
-  __IO uint32_t DR;     /*!< CRYP data input register,                         Address offset: 0x08 */
-  __IO uint32_t DOUT;   /*!< CRYP data output register,                        Address offset: 0x0C */
-  __IO uint32_t DMACR;  /*!< CRYP DMA control register,                        Address offset: 0x10 */
-  __IO uint32_t IMSCR;  /*!< CRYP interrupt mask set/clear register,           Address offset: 0x14 */
-  __IO uint32_t RISR;   /*!< CRYP raw interrupt status register,               Address offset: 0x18 */
-  __IO uint32_t MISR;   /*!< CRYP masked interrupt status register,            Address offset: 0x1C */
-  __IO uint32_t K0LR;   /*!< CRYP key left  register 0,                        Address offset: 0x20 */
-  __IO uint32_t K0RR;   /*!< CRYP key right register 0,                        Address offset: 0x24 */
-  __IO uint32_t K1LR;   /*!< CRYP key left  register 1,                        Address offset: 0x28 */
-  __IO uint32_t K1RR;   /*!< CRYP key right register 1,                        Address offset: 0x2C */
-  __IO uint32_t K2LR;   /*!< CRYP key left  register 2,                        Address offset: 0x30 */
-  __IO uint32_t K2RR;   /*!< CRYP key right register 2,                        Address offset: 0x34 */
-  __IO uint32_t K3LR;   /*!< CRYP key left  register 3,                        Address offset: 0x38 */
-  __IO uint32_t K3RR;   /*!< CRYP key right register 3,                        Address offset: 0x3C */
-  __IO uint32_t IV0LR;  /*!< CRYP initialization vector left-word  register 0, Address offset: 0x40 */
-  __IO uint32_t IV0RR;  /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
-  __IO uint32_t IV1LR;  /*!< CRYP initialization vector left-word  register 1, Address offset: 0x48 */
-  __IO uint32_t IV1RR;  /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
-} CRYP_TypeDef;
-
-/** 
-  * @brief HASH
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;        /*!< HASH control register,          Address offset: 0x00        */
-  __IO uint32_t DIN;       /*!< HASH data input register,       Address offset: 0x04        */
-  __IO uint32_t STR;       /*!< HASH start register,            Address offset: 0x08        */
-  __IO uint32_t HR[5];     /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
-  __IO uint32_t IMR;       /*!< HASH interrupt enable register, Address offset: 0x20        */
-  __IO uint32_t SR;        /*!< HASH status register,           Address offset: 0x24        */
-  uint32_t  RESERVED[52];  /*!< Reserved, 0x28-0xF4                                         */
-  __IO uint32_t CSR[51];   /*!< HASH context swap registers,    Address offset: 0x0F8-0x1C0 */  
-} HASH_TypeDef;
-
-/** 
-  * @brief HASH
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00) 
-#define BKPSRAM_BASE          (AHB1PERIPH_BASE + 0x4000)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!<Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!<End of conversion */
-#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!<Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!<Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint8_t)0x20)               /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
-#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
-#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
-#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
-#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
-#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
-#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
-#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
-#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
-#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
-#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
-#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Crypto Processor                                */
-/*                                                                            */
-/******************************************************************************/
-/******************* Bits definition for CRYP_CR register  ********************/
-#define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004)
-
-#define CRYP_CR_ALGOMODE                     ((uint32_t)0x00000038)
-#define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008)
-#define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010)
-#define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020)
-#define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000)
-#define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008)
-#define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010)
-#define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018)
-#define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020)
-#define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028)
-#define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030)
-#define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038)
-
-#define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0)
-#define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040)
-#define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080)
-#define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300)
-#define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100)
-#define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200)
-#define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000)
-#define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000)
-/****************** Bits definition for CRYP_SR register  *********************/
-#define CRYP_SR_IFEM                         ((uint32_t)0x00000001)
-#define CRYP_SR_IFNF                         ((uint32_t)0x00000002)
-#define CRYP_SR_OFNE                         ((uint32_t)0x00000004)
-#define CRYP_SR_OFFU                         ((uint32_t)0x00000008)
-#define CRYP_SR_BUSY                         ((uint32_t)0x00000010)
-/****************** Bits definition for CRYP_DMACR register  ******************/
-#define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001)
-#define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002)
-/*****************  Bits definition for CRYP_IMSCR register  ******************/
-#define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001)
-#define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002)
-/****************** Bits definition for CRYP_RISR register  *******************/
-#define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001)
-#define CRYP_RISR_INRIS                      ((uint32_t)0x00000002)
-/****************** Bits definition for CRYP_MISR register  *******************/
-#define CRYP_MISR_INMIS                      ((uint32_t)0x00000001)
-#define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002)
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
-#define DCMI_CR_CM                           ((uint32_t)0x00000002)
-#define DCMI_CR_CROP                         ((uint32_t)0x00000004)
-#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
-#define DCMI_CR_ESS                          ((uint32_t)0x00000010)
-#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
-#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
-#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
-#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
-#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
-#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
-#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
-#define DCMI_CR_CRE                          ((uint32_t)0x00001000)
-#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
-#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
-#define DCMI_SR_FNE                          ((uint32_t)0x00000004)
-
-/********************  Bits definition for DCMI_RISR register  ****************/
-#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
-#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
-#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
-#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
-#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
-#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
-#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
-#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
-#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
-
-/********************  Bits definition for DCMI_MISR register  ****************/
-#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
-#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
-#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
-#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
-#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
-#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
-#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
-#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
-#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/ 
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x00000007)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
-
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                  ((uint32_t)0x00000001)
-#define FLASH_OPTCR_OPTSTRT                  ((uint32_t)0x00000002)
-#define FLASH_OPTCR_BOR_LEV_0                ((uint32_t)0x00000004)
-#define FLASH_OPTCR_BOR_LEV_1                ((uint32_t)0x00000008)
-#define FLASH_OPTCR_BOR_LEV                  ((uint32_t)0x0000000C)
-#define FLASH_OPTCR_WDG_SW                   ((uint32_t)0x00000020)
-#define FLASH_OPTCR_nRST_STOP                ((uint32_t)0x00000040)
-#define FLASH_OPTCR_nRST_STDBY               ((uint32_t)0x00000080)
-#define FLASH_OPTCR_RDP_0                    ((uint32_t)0x00000100)
-#define FLASH_OPTCR_RDP_1                    ((uint32_t)0x00000200)
-#define FLASH_OPTCR_RDP_2                    ((uint32_t)0x00000400)
-#define FLASH_OPTCR_RDP_3                    ((uint32_t)0x00000800)
-#define FLASH_OPTCR_RDP_4                    ((uint32_t)0x00001000)
-#define FLASH_OPTCR_RDP_5                    ((uint32_t)0x00002000)
-#define FLASH_OPTCR_RDP_6                    ((uint32_t)0x00004000)
-#define FLASH_OPTCR_RDP_7                    ((uint32_t)0x00008000)
-#define FLASH_OPTCR_nWRP_0                   ((uint32_t)0x00010000)
-#define FLASH_OPTCR_nWRP_1                   ((uint32_t)0x00020000)
-#define FLASH_OPTCR_nWRP_2                   ((uint32_t)0x00040000)
-#define FLASH_OPTCR_nWRP_3                   ((uint32_t)0x00080000)
-#define FLASH_OPTCR_nWRP_4                   ((uint32_t)0x00100000)
-#define FLASH_OPTCR_nWRP_5                   ((uint32_t)0x00200000)
-#define FLASH_OPTCR_nWRP_6                   ((uint32_t)0x00400000)
-#define FLASH_OPTCR_nWRP_7                   ((uint32_t)0x00800000)
-#define FLASH_OPTCR_nWRP_8                   ((uint32_t)0x01000000)
-#define FLASH_OPTCR_nWRP_9                   ((uint32_t)0x02000000)
-#define FLASH_OPTCR_nWRP_10                  ((uint32_t)0x04000000)
-#define FLASH_OPTCR_nWRP_11                  ((uint32_t)0x08000000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
-#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
-
-#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
-#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
-#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit */
-#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
-#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
-#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
-#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
-#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait */
-#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
-#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
-
-#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
-#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
-#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit */
-#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
-#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
-#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
-#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
-#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait */
-#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
-#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
-
-#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
-#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
-#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit. */
-#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
-#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
-#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
-#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
-#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait */
-#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
-
-#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
-#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
-#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit */
-#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
-#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
-#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
-#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
-#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait */
-#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
-#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
-
-#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
-
-#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
-
-#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
-
-#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
-
-#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
-
-#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
-
-#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
-
-#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
-
-#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
-
-/*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status */
-#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status */
-#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status */
-#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit */
-#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit */
-#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status */
-#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status */
-#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status */
-#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit */
-#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit */
-#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status */
-#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status */
-#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status */
-#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit */
-#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit */
-#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
-
-/******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
-
-/******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
-
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
-
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
-
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
-
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
-
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
-
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
-
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
-
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
-
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
-
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
-
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
-
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
-
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
-
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
-
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
-
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
-
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
-
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
-
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
-
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
-
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
-
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
-
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
-
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
-
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
-
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
-
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
-
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
-
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
-
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
-
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
-
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
-
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
-
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
-
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
-
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
-
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
-
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
-
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
-
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
-
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
-
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
-
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
-
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
-
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_OTYPER_IDR_0                    ((uint32_t)0x00000001)
-#define GPIO_OTYPER_IDR_1                    ((uint32_t)0x00000002)
-#define GPIO_OTYPER_IDR_2                    ((uint32_t)0x00000004)
-#define GPIO_OTYPER_IDR_3                    ((uint32_t)0x00000008)
-#define GPIO_OTYPER_IDR_4                    ((uint32_t)0x00000010)
-#define GPIO_OTYPER_IDR_5                    ((uint32_t)0x00000020)
-#define GPIO_OTYPER_IDR_6                    ((uint32_t)0x00000040)
-#define GPIO_OTYPER_IDR_7                    ((uint32_t)0x00000080)
-#define GPIO_OTYPER_IDR_8                    ((uint32_t)0x00000100)
-#define GPIO_OTYPER_IDR_9                    ((uint32_t)0x00000200)
-#define GPIO_OTYPER_IDR_10                   ((uint32_t)0x00000400)
-#define GPIO_OTYPER_IDR_11                   ((uint32_t)0x00000800)
-#define GPIO_OTYPER_IDR_12                   ((uint32_t)0x00001000)
-#define GPIO_OTYPER_IDR_13                   ((uint32_t)0x00002000)
-#define GPIO_OTYPER_IDR_14                   ((uint32_t)0x00004000)
-#define GPIO_OTYPER_IDR_15                   ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_OTYPER_ODR_0                    ((uint32_t)0x00000001)
-#define GPIO_OTYPER_ODR_1                    ((uint32_t)0x00000002)
-#define GPIO_OTYPER_ODR_2                    ((uint32_t)0x00000004)
-#define GPIO_OTYPER_ODR_3                    ((uint32_t)0x00000008)
-#define GPIO_OTYPER_ODR_4                    ((uint32_t)0x00000010)
-#define GPIO_OTYPER_ODR_5                    ((uint32_t)0x00000020)
-#define GPIO_OTYPER_ODR_6                    ((uint32_t)0x00000040)
-#define GPIO_OTYPER_ODR_7                    ((uint32_t)0x00000080)
-#define GPIO_OTYPER_ODR_8                    ((uint32_t)0x00000100)
-#define GPIO_OTYPER_ODR_9                    ((uint32_t)0x00000200)
-#define GPIO_OTYPER_ODR_10                   ((uint32_t)0x00000400)
-#define GPIO_OTYPER_ODR_11                   ((uint32_t)0x00000800)
-#define GPIO_OTYPER_ODR_12                   ((uint32_t)0x00001000)
-#define GPIO_OTYPER_ODR_13                   ((uint32_t)0x00002000)
-#define GPIO_OTYPER_ODR_14                   ((uint32_t)0x00004000)
-#define GPIO_OTYPER_ODR_15                   ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    HASH                                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for HASH_CR register  ********************/
-#define HASH_CR_INIT                         ((uint32_t)0x00000004)
-#define HASH_CR_DMAE                         ((uint32_t)0x00000008)
-#define HASH_CR_DATATYPE                     ((uint32_t)0x00000030)
-#define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010)
-#define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020)
-#define HASH_CR_MODE                         ((uint32_t)0x00000040)
-#define HASH_CR_ALGO                         ((uint32_t)0x00000080)
-#define HASH_CR_NBW                          ((uint32_t)0x00000F00)
-#define HASH_CR_NBW_0                        ((uint32_t)0x00000100)
-#define HASH_CR_NBW_1                        ((uint32_t)0x00000200)
-#define HASH_CR_NBW_2                        ((uint32_t)0x00000400)
-#define HASH_CR_NBW_3                        ((uint32_t)0x00000800)
-#define HASH_CR_DINNE                        ((uint32_t)0x00001000)
-#define HASH_CR_LKEY                         ((uint32_t)0x00010000)
-
-/******************  Bits definition for HASH_STR register  *******************/
-#define HASH_STR_NBW                         ((uint32_t)0x0000001F)
-#define HASH_STR_NBW_0                       ((uint32_t)0x00000001)
-#define HASH_STR_NBW_1                       ((uint32_t)0x00000002)
-#define HASH_STR_NBW_2                       ((uint32_t)0x00000004)
-#define HASH_STR_NBW_3                       ((uint32_t)0x00000008)
-#define HASH_STR_NBW_4                       ((uint32_t)0x00000010)
-#define HASH_STR_DCAL                        ((uint32_t)0x00000100)
-
-/******************  Bits definition for HASH_IMR register  *******************/
-#define HASH_IMR_DINIM                       ((uint32_t)0x00000001)
-#define HASH_IMR_DCIM                        ((uint32_t)0x00000002)
-
-/******************  Bits definition for HASH_SR register  ********************/
-#define HASH_SR_DINIS                        ((uint32_t)0x00000001)
-#define HASH_SR_DCIS                         ((uint32_t)0x00000002)
-#define HASH_SR_DMAS                         ((uint32_t)0x00000004)
-#define HASH_SR_BUSY                         ((uint32_t)0x00000008)
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!<Peripheral Enable */
-#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!<SMBus Mode */
-#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!<SMBus Type */
-#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!<ARP Enable */
-#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!<PEC Enable */
-#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!<General Call Enable */
-#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!<Clock Stretching Disable (Slave mode) */
-#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!<Start Generation */
-#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!<Stop Generation */
-#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!<Acknowledge Enable */
-#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!<Packet Error Checking */
-#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!<SMBus Alert */
-#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!<Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!<Error Interrupt Enable */
-#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!<Event Interrupt Enable */
-#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!<DMA Requests Enable */
-#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!<DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!<Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!<8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!<Start Bit (Master mode) */
-#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!<Byte Transfer Finished */
-#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!<10-bit header sent (Master mode) */
-#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!<Stop detection (Slave mode) */
-#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!<Data Register not Empty (receivers) */
-#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!<Data Register Empty (transmitters) */
-#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!<Bus Error */
-#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!<Arbitration Lost (master mode) */
-#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!<Acknowledge Failure */
-#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!<Overrun/Underrun */
-#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!<PEC Error in reception */
-#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!<Timeout or Tlow Error */
-#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!<SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!<Master/Slave */
-#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!<Bus Busy */
-#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!<Transmitter/Receiver */
-#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!<General Call Address (Slave mode) */
-#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!<SMBus Host Header (Slave mode) */
-#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!<Dual Flag (Slave mode) */
-#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!<Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!<Fast Mode Duty Cycle */
-#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!<I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */
-#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
-#define  PWR_CR_FPDS                         ((uint16_t)0x0200)     /*!< Flash power down in Stop mode */
-
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
-#define  PWR_CSR_BRR                         ((uint16_t)0x0008)     /*!< Backup regulator ready */
-#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
-#define  PWR_CSR_BRE                         ((uint16_t)0x0200)     /*!< Backup regulator enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
-
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
-
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
-
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
-
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
-
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E00)         /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
-
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
-
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
-
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
-
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
-#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
-#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
-#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
-#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
-/* CHIBIOS FIX */
-/*#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x10000000)*/
-#define  RCC_AHB1RSTR_OTGHSRST                ((uint32_t)0x10000000)
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
-#define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010)
-#define  RCC_AHB2RSTR_HSAHRST                ((uint32_t)0x00000020)
-#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
-/* CHIBIOS FIX */
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
-#define  RCC_APB1RSTR_WWDGEN                 ((uint32_t)0x00000800)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00008000)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00010000)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
-#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
-#define  RCC_APB2RSTR_SPI1                   ((uint32_t)0x00001000)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
-#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
-#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
-#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
-#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
-#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
-#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
-#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
-#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
-#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
-#define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010)
-#define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020)
-#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
-#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
-#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
-#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
-#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
-#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
-#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
-#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
-#define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010)
-#define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020)
-#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
-#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
-#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
-#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
-#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
-#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
-#define  RCC_APB2LPENR_ADC2PEN               ((uint32_t)0x00000200)
-#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
-
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
-
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
-#define RNG_CR_IE                            ((uint32_t)0x00000008)
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!<Clock divide factor */
-#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!<Clock enable bit */
-#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!<Power saving configuration bit */
-#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!<HW Flow Control enable */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!<Command Index */
-
-#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!<CPSM Waits for Interrupt Request */
-#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!<SD I/O suspend command */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!<Enable CMD completion */
-#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!<CE-ATA command */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!<Data transfer enabled bit */
-#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!<Data transfer mode selection */
-#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!<DMA enabled bit */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!<Read wait start */
-#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!<Read wait stop */
-#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!<Read wait mode */
-#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed) */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed) */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed) */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required) */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero) */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed) */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!<Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!<Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!<SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!<Frame Format */
-#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!<Internal slave select */
-#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!<Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!<Receive only */
-#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!<Data Frame Format */
-#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!<Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!<Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!<Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!<Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!<Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!<SS Output Enable */
-#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!<Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!<Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!<Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!<Channel side */
-#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!<Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!<CRC Error flag */
-#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!<Mode fault */
-#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!<Overrun flag */
-#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!<Busy flag */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!<Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!<Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!<Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
-
-#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
-
-#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!<SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001)
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002)
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-/* CHIBIOS FIX */
-#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
-/*#define SYSCFG_PMC_MII_RMII            ((uint16_t)0x0080)*/ /*!<Ethernet PHY interface selection */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0006) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0007) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint16_t)0x0008) /*!<PI[0] pin */
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0060) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0070) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint16_t)0x0080) /*!<PI[1] pin */
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0600) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0700) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint16_t)0x0800) /*!<PI[2] pin */
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x6000) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint16_t)0x7000) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint16_t)0x8000) /*!<PI[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0006) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint16_t)0x0007) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint16_t)0x0008) /*!<PI[4] pin */
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0060) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint16_t)0x0070) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint16_t)0x0080) /*!<PI[5] pin */
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0600) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint16_t)0x0700) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint16_t)0x0800) /*!<PI[6] pin */
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x6000) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint16_t)0x7000) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint16_t)0x8000) /*!<PI[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0006) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint16_t)0x0007) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint16_t)0x0008) /*!<PI[8] pin */
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0060) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint16_t)0x0070) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint16_t)0x0080) /*!<PI[9] pin */
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0600) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint16_t)0x0700) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint16_t)0x0800) /*!<PI[10] pin */
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x6000) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint16_t)0x7000) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint16_t)0x8000) /*!<PI[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0006) /*!<PG[12] pin */
-#define SYSCFG_EXTICR3_EXTI12_PH        ((uint16_t)0x0007) /*!<PH[12] pin */
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0060) /*!<PG[13] pin */
-#define SYSCFG_EXTICR3_EXTI13_PH        ((uint16_t)0x0070) /*!<PH[13] pin */
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0600) /*!<PG[14] pin */
-#define SYSCFG_EXTICR3_EXTI14_PH        ((uint16_t)0x0700) /*!<PH[14] pin */
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x6000) /*!<PG[15] pin */
-#define SYSCFG_EXTICR3_EXTI15_PH        ((uint16_t)0x7000) /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
-#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
-#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
-#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
-
-#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
-#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
-#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
-#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
-#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
-#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
-#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
-#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
-#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
-#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
-#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
-#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
-#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
-#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
-#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint16_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
-#define TIM_OR_TI4_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint16_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!<Parity Error */
-#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!<Framing Error */
-#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!<Noise Error Flag */
-#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!<OverRun Error */
-#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!<IDLE line detected */
-#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!<Transmission Complete */
-#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!<LIN Break Detection Flag */
-#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!<CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!<Send Break */
-#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!<Receiver wakeup */
-#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!<Receiver Enable */
-#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!<Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!<IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!<RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!<PE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!<PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!<Parity Selection */
-#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!<Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!<Wakeup method */
-#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!<Word length */
-#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!<USART Enable */
-#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!<USART Oversampling by 8 enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!<Address of the USART node */
-#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!<LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!<Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!<Clock Phase */
-#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!<Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!<Clock Enable */
-
-#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!<Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!<IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!<IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!<Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!<Smartcard NACK enable */
-#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!<Smartcard mode enable */
-#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!<DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!<DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!<RTS Enable */
-#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!<CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!<CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP        ((uint32_t)0x00000004)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP        ((uint32_t)0x00000008)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP       ((uint32_t)0x00000040)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP       ((uint32_t)0x00000080)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP       ((uint32_t)0x00001000)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
-#define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
-#define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
-#define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
-#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
-#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
-#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
-#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
-#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
-#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
-#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
-#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
-#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
-#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
-#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
-#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-120 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/42 */  
-#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
-#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
-#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
-#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
-#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset (Only in STM32F2xx) */
-#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset (Only in STM32F2xx) */
-#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
-#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
-#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
-#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
-#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
-#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
-#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
-#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
-#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
-#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
-#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
-#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
-#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
-#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
-
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-
-#ifdef USE_STDPERIPH_DRIVER
-  #include "stm32f2xx_conf.h"
-#endif /* USE_STDPERIPH_DRIVER */
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F2xx_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM32F4xx/stm32f4xx.h b/os/hal/platforms/STM32F4xx/stm32f4xx.h
deleted file mode 100644
index 1ddbeb36c..000000000
--- a/os/hal/platforms/STM32F4xx/stm32f4xx.h
+++ /dev/null
@@ -1,9158 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx.h
-  * @author  MCD Application Team
-  * @version V1.2.1
-  * @date    19-September-2013
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32F4xx devices.            
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral�s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral�s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_STDPERIPH_DRIVER"
-  *              - To change few application-specific parameters such as the HSE 
-  *                crystal frequency
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx
-  * @{
-  */
-    
-#ifndef __STM32F4xx_H
-#define __STM32F4xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx)
-  /* #define STM32F40_41xxx */   /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,  
-                                     STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, 
-                                     STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
-
-  /* #define STM32F427_437xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,  
-                                       STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
-                                    
-  /* #define STM32F429_439xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,  
-                                       STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, 
-                                       STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
-                                       STM32F439IG and STM32F439II Devices */
-                                    
-  /* #define STM32F401xx */     /*!< STM32F401CB, STM32F401CC,  STM32F401RB,  STM32F401RC, STM32F401VB and STM32F401VC Devices */  
-  
-#endif
-
-/* Old STM32F40XX definition, maintained for legacy purpose */
-#ifdef STM32F40XX
-  #define STM32F40_41xxx
-#endif /* STM32F40XX */
-
-/* Old STM32F427X definition, maintained for legacy purpose */
-#ifdef STM32F427X
-  #define STM32F427_437xx
-#endif /* STM32F427X */
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-
-#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx)
- #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
-#endif
-
-#if !defined  (USE_STDPERIPH_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_STDPERIPH_DRIVER */
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application 
-   
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */           
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-  
-#endif /* HSE_VALUE */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-   Timeout value 
-   */
-#if !defined  (HSE_STARTUP_TIMEOUT) 
-  #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x05000)   /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */   
-
-#if !defined  (HSI_VALUE)   
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */   
-
-/**
- * @brief STM32F4XX Standard Peripherals Library version number V1.2.0
-   */
-#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
-#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F4XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
-                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
-                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
-                                             |(__STM32F4XX_STDPERIPH_VERSION_RC))
-                                             
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
- */
-#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum IRQn
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-
-#if defined (STM32F40_41xxx)
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
-#endif /* STM32F40_41xxx */
-
-#if defined (STM32F427_437xx)
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */   
-#endif /* STM32F427_437xx */
-    
-#if defined (STM32F429_439xx)
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
-  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
-  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
-  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
-  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
-  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
-  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
-  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
-  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
-  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
-  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
-  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */   
-#endif /* STM32F429_439xx */
-   
-#if defined (STM32F401xx)
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */  
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  FPU_IRQn                    = 81,      /*!< FPU global interrupt                                             */
-  SPI4_IRQn                   = 84       /*!< SPI4 global Interrupt                                            */
-#endif /* STM32F401xx */
-
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-/* CHIBIOS FIX */
-//#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef int32_t  s32;
-typedef int16_t s16;
-typedef int8_t  s8;
-
-typedef const int32_t sc32;  /*!< Read Only */
-typedef const int16_t sc16;  /*!< Read Only */
-typedef const int8_t sc8;   /*!< Read Only */
-
-typedef __IO int32_t  vs32;
-typedef __IO int16_t  vs16;
-typedef __IO int8_t   vs8;
-
-typedef __I int32_t vsc32;  /*!< Read Only */
-typedef __I int16_t vsc16;  /*!< Read Only */
-typedef __I int8_t vsc8;   /*!< Read Only */
-
-typedef uint32_t  u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-typedef const uint32_t uc32;  /*!< Read Only */
-typedef const uint16_t uc16;  /*!< Read Only */
-typedef const uint8_t uc8;   /*!< Read Only */
-
-typedef __IO uint32_t  vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t  vu8;
-
-typedef __I uint32_t vuc32;  /*!< Read Only */
-typedef __I uint16_t vuc16;  /*!< Read Only */
-typedef __I uint8_t vuc8;   /*!< Read Only */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
- 
-/** 
-  * @brief DMA2D Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
-  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
-  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
-  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
-  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
-  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
-  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
-  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
-  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
-  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
-  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
-  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
-  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
-  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
-  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
-  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
-  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
-  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
-  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
-  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
-  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
-  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
-  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-#if defined (STM32F40_41xxx)
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-} FSMC_Bank2_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank3
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FSMC_Bank3_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef; 
-#endif /* STM32F40_41xxx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-/** 
-  * @brief Flexible Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-} FMC_Bank2_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank3
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/** 
-  * @brief Flexible Memory Controller Bank4
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FMC_Bank4_TypeDef; 
-
-/** 
-  * @brief Flexible Memory Controller Bank5_6
-  */
-  
-typedef struct
-{
-  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
-  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
-  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
-  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
-  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
-} FMC_Bank5_6_TypeDef; 
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-/* CHIBIOS FIX */
-#if 0
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
-  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-#endif
-
-/** 
-  * @brief System configuration controller
-  */
-  
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                   */
-  __IO uint16_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                   */
-  __IO uint16_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                   */
-  __IO uint16_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                   */
-  __IO uint16_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                   */
-  __IO uint16_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                   */
-  __IO uint16_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                   */
-  __IO uint16_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                   */
-  __IO uint16_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                   */
-  __IO uint16_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
-  uint16_t      RESERVED9;  /*!< Reserved, 0x26                                   */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD-TFT Display Controller
-  */
-  
-typedef struct
-{
-  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
-  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
-  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
-  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
-  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
-  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
-  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
-  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
-  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
-  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
-  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
-  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
-  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
-  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
-  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
-  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
-} LTDC_TypeDef;  
-
-/** 
-  * @brief LCD-TFT Display layer x Controller
-  */
-  
-typedef struct
-{  
-  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
-  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
-  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
-  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
-  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
-  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
-  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
-  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
-  uint32_t      RESERVED0[2];  /*!< Reserved */
-  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
-  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
-  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
-  uint32_t      RESERVED1[3];  /*!< Reserved */
-  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
-  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
-
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Audio Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
-} SAI_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
-  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
-  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
-  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
-  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
-  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
-  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
-  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
-  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
-  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
-  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
-  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
-  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
-  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
-  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
-  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
-  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
-  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
-  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
-  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
-  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
-  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
-  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
-  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
-  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
-  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
-  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
-  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
-  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
-  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
-  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
-  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
-  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Crypto Processor
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
-  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
-  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
-  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
-  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
-  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
-  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
-  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
-  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
-  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
-  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
-  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
-  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
-  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
-  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
-  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
-  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
-  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
-  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
-  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
-  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
-  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
-  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
-  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
-  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
-  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
-  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
-  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
-  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
-  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
-  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
-  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
-  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
-  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
-  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
-  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/** 
-  * @brief HASH
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
-  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
-  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
-  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
-  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
-  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
-       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
-  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/** 
-  * @brief HASH_DIGEST
-  */
-  
-typedef struct 
-{
-  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
-} HASH_DIGEST_TypeDef;
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-
-#if defined (STM32F40_41xxx)
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
-#endif /* STM32F40_41xxx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-#define FMC_R_BASE            ((uint32_t)0xA0000000) /*!< FMC registers base address                                                 */
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-#define CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region  */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */
-#define SRAM2_BB_BASE         ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region                              */
-#define SRAM3_BB_BASE         ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region                              */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
-#define UART7_BASE            (APB1PERIPH_BASE + 0x7800)
-#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)
-#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400)
-#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800)
-#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
-#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
-#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104) 
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
-#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400)
-#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
-#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
-#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
-
-#if defined (STM32F40_41xxx)
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
-#endif /* STM32F40_41xxx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000)
-#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104)
-#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060)
-#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080)
-#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0)
-#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140)
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define UART7               ((USART_TypeDef *) UART7_BASE)
-#define UART8               ((USART_TypeDef *) UART8_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
-#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
-#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#if defined (STM32F40_41xxx)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
-#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#endif /* STM32F40_41xxx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
-#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
-#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!<Analog watchdog flag               */
-#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!<End of conversion                  */
-#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!<Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!<Injected channel Start flag        */
-#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!<Regular channel Start flag         */
-#define  ADC_SR_OVR                          ((uint8_t)0x20)               /*!<Overrun flag                       */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC                              */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable                     */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels                */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode                                             */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode  */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion                   */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels                */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels               */
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count)  */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels           */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels            */
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution)                            */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable                              */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF             */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion              */
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode          */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection        */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment                     */
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
-#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
-#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
-#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
-#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
-#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
-#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
-#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
-#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
-#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
-#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
-#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
-#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
-#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
-#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
-#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
-#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
-#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
-#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
-#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
-#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
-#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
-#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
-#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
-#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
-#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
-#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
-#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
-#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
-#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
-#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
-
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
-#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
-#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
-#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
-#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
-#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
-#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
-#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
-#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
-#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
-#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
-#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
-#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
-#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
-#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
-#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
-#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
-#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
-#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
-#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
-#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
-#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
-#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
-#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
-
-#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
-#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
-#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
-#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
-
-#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
-#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
-#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
-#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
-#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
-#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
-#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
-#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
-#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
-#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
-#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
-#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
-#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
-#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
-#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
-#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
-#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
-#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
-#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
-#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
-#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
-#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
-
-#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
-#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
-
-#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
-#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
-#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
-#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
-#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
-#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
-#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
-#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
-#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
-#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
-#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
-#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
-#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
-#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
-#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
-#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
-#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
-#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
-#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
-#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
-#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
-#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
-#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
-#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
-#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
-#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
-#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
-#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
-#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
-#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
-#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
-#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
-#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
-#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
-#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
-#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
-#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
-#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
-#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
-#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
-#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
-#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
-#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
-#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
-#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
-#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
-#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
-#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
-#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
-#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
-#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
-#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
-#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
-#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
-#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
-#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
-#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
-#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
-#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
-#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
-#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
-#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
-#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
-#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
-#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
-#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
-#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
-#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
-#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
-#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
-#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
-#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
-#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
-#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
-#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
-#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
-#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
-#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
-#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
-#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
-#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
-#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
-#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
-#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
-#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
-#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
-#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
-#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
-#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
-#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
-#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
-#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
-#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
-#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
-#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
-#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
-#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
-#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
-#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
-#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
-#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
-#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
-#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
-#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
-#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
-#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
-#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Crypto Processor                                */
-/*                                                                            */
-/******************************************************************************/
-/******************* Bits definition for CRYP_CR register  ********************/
-#define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004)
-
-#define CRYP_CR_ALGOMODE                     ((uint32_t)0x00080038)
-#define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008)
-#define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010)
-#define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020)
-#define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000)
-#define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008)
-#define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010)
-#define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018)
-#define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020)
-#define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028)
-#define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030)
-#define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038)
-
-#define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0)
-#define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040)
-#define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080)
-#define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300)
-#define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100)
-#define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200)
-#define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000)
-#define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000)
-
-#define CRYP_CR_GCM_CCMPH                    ((uint32_t)0x00030000)
-#define CRYP_CR_GCM_CCMPH_0                  ((uint32_t)0x00010000)
-#define CRYP_CR_GCM_CCMPH_1                  ((uint32_t)0x00020000)
-#define CRYP_CR_ALGOMODE_3                   ((uint32_t)0x00080000) 
-
-/****************** Bits definition for CRYP_SR register  *********************/
-#define CRYP_SR_IFEM                         ((uint32_t)0x00000001)
-#define CRYP_SR_IFNF                         ((uint32_t)0x00000002)
-#define CRYP_SR_OFNE                         ((uint32_t)0x00000004)
-#define CRYP_SR_OFFU                         ((uint32_t)0x00000008)
-#define CRYP_SR_BUSY                         ((uint32_t)0x00000010)
-/****************** Bits definition for CRYP_DMACR register  ******************/
-#define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001)
-#define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002)
-/*****************  Bits definition for CRYP_IMSCR register  ******************/
-#define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001)
-#define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002)
-/****************** Bits definition for CRYP_RISR register  *******************/
-#define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001)
-#define CRYP_RISR_INRIS                      ((uint32_t)0x00000002)
-/****************** Bits definition for CRYP_MISR register  *******************/
-#define CRYP_MISR_INMIS                      ((uint32_t)0x00000001)
-#define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002)
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 Debug MCU                                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
-#define DCMI_CR_CM                           ((uint32_t)0x00000002)
-#define DCMI_CR_CROP                         ((uint32_t)0x00000004)
-#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
-#define DCMI_CR_ESS                          ((uint32_t)0x00000010)
-#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
-#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
-#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
-#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
-#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
-#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
-#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
-#define DCMI_CR_CRE                          ((uint32_t)0x00001000)
-#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
-#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
-#define DCMI_SR_FNE                          ((uint32_t)0x00000004)
-
-/********************  Bits definition for DCMI_RISR register  ****************/
-#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
-#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
-#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
-#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
-#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
-#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
-#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
-#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
-#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
-
-/********************  Bits definition for DCMI_MISR register  ****************/
-#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
-#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
-#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
-#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
-#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
-#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
-#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
-#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
-#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/ 
-#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
-#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
-#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
-#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
-#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
-#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
-#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
-#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
-#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
-#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
-#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
-#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
-#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
-#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
-#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
-#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
-#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
-#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
-#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
-#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
-#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
-#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
-#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
-#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
-#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
-#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
-#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
-#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
-#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
-#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
-#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
-#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
-#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
-#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
-#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
-#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
-#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
-#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
-#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
-#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
-#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
-#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
-#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
-#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
-#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
-#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
-#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
-#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
-#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
-#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
-#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
-#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
-#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
-#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
-#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
-#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
-#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
-#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
-#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
-#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
-#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
-#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
-#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
-#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
-#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
-#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
-#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
-#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
-#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
-#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
-#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
-#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
-#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
-#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
-#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
-#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
-#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
-#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
-#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
-#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
-#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
-#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
-#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
-#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
-#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
-#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
-#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
-#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
-#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
-#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
-#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
-#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
-#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
-#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
-#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
-#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
-#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
-#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
-#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
-#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
-#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
-#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
-#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
-#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
-#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
-#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
-#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
-#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
-#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
-#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
-#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
-#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
-#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
-#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
-#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
-#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
-#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
-#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
-#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
-#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
-#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
-#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
-#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
-#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
-#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
-#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
-#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
-#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
-#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
-#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
-#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
-#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
-#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
-#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
-#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         AHB Master DMA2D Controller (DMA2D)                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DMA2D_CR register  ******************/
-
-#define DMA2D_CR_START                     ((uint32_t)0x00000001)               /*!< Start transfer */
-#define DMA2D_CR_SUSP                      ((uint32_t)0x00000002)               /*!< Suspend transfer */
-#define DMA2D_CR_ABORT                     ((uint32_t)0x00000004)               /*!< Abort transfer */
-#define DMA2D_CR_TEIE                      ((uint32_t)0x00000100)               /*!< Transfer Error Interrupt Enable */
-#define DMA2D_CR_TCIE                      ((uint32_t)0x00000200)               /*!< Transfer Complete Interrupt Enable */
-#define DMA2D_CR_TWIE                      ((uint32_t)0x00000400)               /*!< Transfer Watermark Interrupt Enable */
-#define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800)               /*!< CLUT Access Error Interrupt Enable */
-#define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000)               /*!< CLUT Transfer Complete Interrupt Enable */
-#define DMA2D_CR_CEIE                      ((uint32_t)0x00002000)               /*!< Configuration Error Interrupt Enable */
-#define DMA2D_CR_MODE                      ((uint32_t)0x00030000)               /*!< DMA2D Mode */
-
-/********************  Bit definition for DMA2D_ISR register  *****************/
-
-#define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001)               /*!< Transfer Error Interrupt Flag */
-#define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002)               /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004)               /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008)               /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010)               /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020)               /*!< Configuration Error Interrupt Flag */
-
-/********************  Bit definition for DMA2D_IFSR register  ****************/
-
-#define DMA2D_IFSR_CTEIF                   ((uint32_t)0x00000001)               /*!< Clears Transfer Error Interrupt Flag */
-#define DMA2D_IFSR_CTCIF                   ((uint32_t)0x00000002)               /*!< Clears Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CTWIF                   ((uint32_t)0x00000004)               /*!< Clears Transfer Watermark Interrupt Flag */
-#define DMA2D_IFSR_CCAEIF                  ((uint32_t)0x00000008)               /*!< Clears CLUT Access Error Interrupt Flag */
-#define DMA2D_IFSR_CCTCIF                  ((uint32_t)0x00000010)               /*!< Clears CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_IFSR_CCEIF                   ((uint32_t)0x00000020)               /*!< Clears Configuration Error Interrupt Flag */
-
-/********************  Bit definition for DMA2D_FGMAR register  ***************/
-
-#define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_FGOR register  ****************/
-
-#define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_BGMAR register  ***************/
-
-#define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGOR register  ****************/
-
-#define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_FGPFCCR register  *************/
-
-#define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
-#define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
-#define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
-#define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
-#define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha mode */
-#define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_FGCOLR register  **************/
-
-#define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
-#define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
-#define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */   
-
-/********************  Bit definition for DMA2D_BGPFCCR register  *************/
-
-#define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
-#define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
-#define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
-#define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
-#define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha Mode */
-#define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
-
-/********************  Bit definition for DMA2D_BGCOLR register  **************/
-
-#define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
-#define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
-#define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */
-
-/********************  Bit definition for DMA2D_FGCMAR register  **************/
-
-#define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_BGCMAR register  **************/
-
-#define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OPFCCR register  **************/
-
-#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007)               /*!< Color mode */
-
-/********************  Bit definition for DMA2D_OCOLR register  ***************/
-
-/*!<Mode_ARGB8888/RGB888 */
-
-#define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FF)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000)               /*!< Alpha Channel Value */
-
-/*!<Mode_RGB565 */
-#define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800)               /*!< Red Value */
-
-/*!<Mode_ARGB1555 */
-#define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000)               /*!< Alpha Channel Value */
-
-/*!<Mode_ARGB4444 */
-#define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000F)               /*!< BLUE Value */
-#define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0)               /*!< GREEN Value  */
-#define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00)               /*!< Red Value */
-#define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000)               /*!< Alpha Channel Value */
-
-/********************  Bit definition for DMA2D_OMAR register  ****************/
-
-#define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
-
-/********************  Bit definition for DMA2D_OOR register  *****************/
-
-#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFF)               /*!< Line Offset */
-
-/********************  Bit definition for DMA2D_NLR register  *****************/
-
-#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFF)               /*!< Number of Lines */
-#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000)               /*!< Pixel per Lines */
-
-/********************  Bit definition for DMA2D_LWR register  *****************/
-
-#define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFF)               /*!< Line Watermark */
-
-/********************  Bit definition for DMA2D_AMTCR register  ***************/
-
-#define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001)               /*!< Enable */
-#define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00)               /*!< Dead Time */
-
-
-
-/********************  Bit definition for DMA2D_FGCLUT register  **************/
-                                                                     
-/********************  Bit definition for DMA2D_BGCLUT register  **************/
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
-#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
-#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
-#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
-#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
-#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
-#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
-#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
-#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
-#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008)
-#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009)
-#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000A)
-#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000B)
-#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000C)
-#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000D)
-#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000E)
-#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000F)
-
-#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
-#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
-#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
-#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
-#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
-#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
-#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
-#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
-#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
-#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
-#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG                          ((uint32_t)0x00000001)
-#define FLASH_CR_SER                         ((uint32_t)0x00000002)
-#define FLASH_CR_MER                         ((uint32_t)0x00000004)
-#define FLASH_CR_MER1                        FLASH_CR_MER
-#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
-#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
-#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
-#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
-#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
-#define FLASH_CR_SNB_4                       ((uint32_t)0x00000040)
-#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
-#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
-#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
-#define FLASH_CR_MER2                        ((uint32_t)0x00008000)
-#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
-#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
-#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
-#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
-#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
-#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
-#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
-#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010)
-
-#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
-#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
-#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
-#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
-#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
-#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
-#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
-#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
-#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
-#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
-#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
-#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
-#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
-
-#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000) 
-#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000) 
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
-#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
-#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
-#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
-#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
-#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
-#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
-#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
-#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
-#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
-#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
-#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
-#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
-
-#if defined (STM32F40_41xxx)
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
-#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
-#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
-#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
-#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
-#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
-#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                */
-#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
-#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
-#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
-#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
-#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
-#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
-#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
-#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
-#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
-#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
-#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
-#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
-#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
-
-#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
-#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
-#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
-#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
-#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
-#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
-#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
-#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
-#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
-#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
-#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FSMC_PCR2 register  *******************/
-#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
-#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
-
-#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
-
-#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
-
-#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */
-#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR3 register  *******************/
-#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
-#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
-
-#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
-
-#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
-
-#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
-
-/******************  Bit definition for FSMC_PCR4 register  *******************/
-#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
-#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
-
-#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
-
-#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
-
-#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
-#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
-
-#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
-#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
-
-/*******************  Bit definition for FSMC_SR2 register  *******************/
-#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
-#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR3 register  *******************/
-#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
-#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR4 register  *******************/
-#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                 */
-#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                       */
-#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status                */
-#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit   */
-#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit         */
-#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit  */
-#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
-
-/******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT2 register  ******************/
-#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT3 register  ******************/
-#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PATT4 register  ******************/
-#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_PIO4 register  *******************/
-#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
-
-/******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
-#endif /* STM32F40_41xxx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-/******************************************************************************/
-/*                                                                            */
-/*                          Flexible Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FMC_BCR1 register  *******************/
-#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
-#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
-#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
-#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
-#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
-#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
-#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
-#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
-#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000)        /*!<Continous clock enable     */
-
-/******************  Bit definition for FMC_BCR2 register  *******************/
-#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
-#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
-#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
-#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
-#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
-#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
-#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
-#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR3 register  *******************/
-#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
-#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
-#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
-#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
-#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
-#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
-#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
-#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BCR4 register  *******************/
-#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
-#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
-
-#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
-#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
-#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
-#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
-#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
-#define  FMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
-#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
-#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
-#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
-#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
-#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
-#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
-
-/******************  Bit definition for FMC_BTR1 register  ******************/
-#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
-#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR2 register  *******************/
-#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/*******************  Bit definition for FMC_BTR3 register  *******************/
-#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BTR4 register  *******************/
-#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-
-#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR1 register  ******************/
-#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR2 register  ******************/
-#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
-#define  FMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR3 register  ******************/
-#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_BWTR4 register  ******************/
-#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
-#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
-#define  FMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
-
-#define  FMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
-#define  FMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
-#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
-#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_PCR2 register  *******************/
-#define  FMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
-
-#define  FMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
-
-#define  FMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
-
-#define  FMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size)           */
-#define  FMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR3 register  *******************/
-#define  FMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
-
-#define  FMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
-
-#define  FMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
-
-#define  FMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_PCR4 register  *******************/
-#define  FMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
-#define  FMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
-#define  FMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
-
-#define  FMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define  FMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
-
-#define  FMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
-#define  FMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
-#define  FMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
-#define  FMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
-#define  FMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
-
-#define  FMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
-#define  FMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
-#define  FMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
-#define  FMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
-
-#define  FMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
-#define  FMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
-#define  FMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
-#define  FMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
-
-/*******************  Bit definition for FMC_SR2 register  *******************/
-#define  FMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
-#define  FMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR3 register  *******************/
-#define  FMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
-#define  FMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
-
-/*******************  Bit definition for FMC_SR4 register  *******************/
-#define  FMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
-#define  FMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
-#define  FMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
-#define  FMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
-#define  FMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
-#define  FMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
-#define  FMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
-
-/******************  Bit definition for FMC_PMEM2 register  ******************/
-#define  FMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define  FMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define  FMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define  FMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define  FMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM3 register  ******************/
-#define  FMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define  FMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define  FMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define  FMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define  FMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PMEM4 register  ******************/
-#define  FMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define  FMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define  FMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define  FMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define  FMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT2 register  ******************/
-#define  FMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define  FMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define  FMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define  FMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define  FMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT3 register  ******************/
-#define  FMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define  FMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define  FMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define  FMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define  FMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PATT4 register  ******************/
-#define  FMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define  FMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define  FMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define  FMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define  FMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_PIO4 register  *******************/
-#define  FMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define  FMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  FMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  FMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  FMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  FMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define  FMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  FMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  FMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  FMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
-#define  FMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define  FMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
-#define  FMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
-#define  FMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
-#define  FMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
-#define  FMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
-#define  FMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
-
-#define  FMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define  FMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  FMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
-#define  FMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
-#define  FMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
-#define  FMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
-#define  FMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
-
-/******************  Bit definition for FMC_ECCR2 register  ******************/
-#define  FMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
-
-/******************  Bit definition for FMC_ECCR3 register  ******************/
-#define  FMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
-
-/******************  Bit definition for FMC_SDCR1 register  ******************/
-#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
-
-#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
-#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
-
-#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
-
-#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDRAM clock configuration */
-#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
-
-#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
-
-#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000)        /*!<Write protection */
-#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDCR2 register  ******************/
-#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
-#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
-#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
-
-#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
-#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
-#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
-
-#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
-
-#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
-#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
-
-#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
-
-#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000)        /*!<RPIPE[1:0](Read pipe) */
-#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
-#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
-
-/******************  Bit definition for FMC_SDTR1 register  ******************/
-#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
-
-#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDTR2 register  ******************/
-#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
-#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
-                                            
-#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
-#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
-#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
-#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
-#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
-#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
-#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
-#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
-#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
-#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
-
-#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
-#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
-
-/******************  Bit definition for FMC_SDCMR register  ******************/
-#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007)        /*!<MODE[2:0] bits (Command mode) */
-#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000003)        /*!<Bit 2 */
-                                            
-#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008)        /*!<Command target 2 */
-
-#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010)        /*!<Command target 1 */
-
-#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
-#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080)        /*!<Bit 2 */
-#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100)        /*!<Bit 3 */
-
-#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00)        /*!<MRD[12:0] bits (Mode register definition) */
-
-/******************  Bit definition for FMC_SDRTR register  ******************/
-#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001)        /*!<Clear refresh error flag */
-
-#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFE)        /*!<COUNT[12:0] bits (Refresh timer count) */
-
-#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000)        /*!<RES interupt enable */
-
-/******************  Bit definition for FMC_SDSR register  ******************/
-#define  FMC_SDSR_RE                        ((uint32_t)0x00000001)        /*!<Refresh error flag */
-
-#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
-#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004)        /*!<Bit 1 */
-
-#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
-#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010)        /*!<Bit 1 */
-
-#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020)        /*!<Busy status */
-
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
-
-#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
-
-#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
-
-#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
-
-#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
-
-#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
-
-#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
-
-#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
-
-#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
-
-#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
-
-#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
-
-#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
-
-#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
-
-#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
-
-#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
-
-#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
-
-#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
-
-#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
-
-#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
-
-#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
-
-#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
-
-#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
-
-#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
-
-#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
-
-#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
-
-#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
-
-#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
-
-#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
-
-#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
-
-#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
-
-#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
-
-#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
-
-#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
-
-#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
-
-#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
-
-#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
-
-#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
-
-#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
-
-#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
-
-#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
-
-#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
-
-#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
-
-#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
-
-#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
-
-#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
-
-#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    HASH                                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for HASH_CR register  ********************/
-#define HASH_CR_INIT                         ((uint32_t)0x00000004)
-#define HASH_CR_DMAE                         ((uint32_t)0x00000008)
-#define HASH_CR_DATATYPE                     ((uint32_t)0x00000030)
-#define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010)
-#define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020)
-#define HASH_CR_MODE                         ((uint32_t)0x00000040)
-#define HASH_CR_ALGO                         ((uint32_t)0x00040080)
-#define HASH_CR_ALGO_0                       ((uint32_t)0x00000080)
-#define HASH_CR_ALGO_1                       ((uint32_t)0x00040000)
-#define HASH_CR_NBW                          ((uint32_t)0x00000F00)
-#define HASH_CR_NBW_0                        ((uint32_t)0x00000100)
-#define HASH_CR_NBW_1                        ((uint32_t)0x00000200)
-#define HASH_CR_NBW_2                        ((uint32_t)0x00000400)
-#define HASH_CR_NBW_3                        ((uint32_t)0x00000800)
-#define HASH_CR_DINNE                        ((uint32_t)0x00001000)
-#define HASH_CR_MDMAT                        ((uint32_t)0x00002000)
-#define HASH_CR_LKEY                         ((uint32_t)0x00010000)
-
-/******************  Bits definition for HASH_STR register  *******************/
-#define HASH_STR_NBW                         ((uint32_t)0x0000001F)
-#define HASH_STR_NBW_0                       ((uint32_t)0x00000001)
-#define HASH_STR_NBW_1                       ((uint32_t)0x00000002)
-#define HASH_STR_NBW_2                       ((uint32_t)0x00000004)
-#define HASH_STR_NBW_3                       ((uint32_t)0x00000008)
-#define HASH_STR_NBW_4                       ((uint32_t)0x00000010)
-#define HASH_STR_DCAL                        ((uint32_t)0x00000100)
-
-/******************  Bits definition for HASH_IMR register  *******************/
-#define HASH_IMR_DINIM                       ((uint32_t)0x00000001)
-#define HASH_IMR_DCIM                        ((uint32_t)0x00000002)
-
-/******************  Bits definition for HASH_SR register  ********************/
-#define HASH_SR_DINIS                        ((uint32_t)0x00000001)
-#define HASH_SR_DCIS                         ((uint32_t)0x00000002)
-#define HASH_SR_DMAS                         ((uint32_t)0x00000004)
-#define HASH_SR_BUSY                         ((uint32_t)0x00000008)
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!<Peripheral Enable                             */
-#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!<SMBus Mode                                    */
-#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!<SMBus Type                                    */
-#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!<ARP Enable                                    */
-#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!<PEC Enable                                    */
-#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!<General Call Enable                           */
-#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!<Clock Stretching Disable (Slave mode)         */
-#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!<Start Generation                              */
-#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!<Stop Generation                               */
-#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!<Acknowledge Enable                            */
-#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!<Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!<Packet Error Checking                         */
-#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!<SMBus Alert                                   */
-#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
-
-#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!<Error Interrupt Enable  */
-#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!<Event Interrupt Enable  */
-#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!<Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!<DMA Requests Enable     */
-#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!<Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!<Interface Address */
-
-#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!<Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!<Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!<Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!<Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!<Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!<Start Bit (Master mode)                         */
-#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!<Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!<Byte Transfer Finished                          */
-#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!<10-bit header sent (Master mode)                */
-#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!<Stop detection (Slave mode)                     */
-#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!<Data Register not Empty (receivers)             */
-#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!<Data Register Empty (transmitters)              */
-#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!<Bus Error                                       */
-#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!<Arbitration Lost (master mode)                  */
-#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!<Acknowledge Failure                             */
-#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!<Overrun/Underrun                                */
-#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!<PEC Error in reception                          */
-#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!<Timeout or Tlow Error                           */
-#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!<Master/Slave                              */
-#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!<Bus Busy                                  */
-#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!<Transmitter/Receiver                      */
-#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!<General Call Address (Slave mode)         */
-#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!<SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!<SMBus Host Header (Slave mode)            */
-#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!<Dual Flag (Slave mode)                    */
-#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!<Packet Error Checking Register            */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!<Fast Mode Duty Cycle                                       */
-#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************  Bit definition for I2C_FLTR register  *******************/
-#define  I2C_FLTR_DNF                     ((uint8_t)0x0F)                  /*!<Digital Noise Filter */
-#define  I2C_FLTR_ANOFF                   ((uint8_t)0x10)                  /*!<Analog Noise Filter OFF */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
-#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update      */
-#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      LCD-TFT Display Controller (LTDC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for LTDC_SSCR register  *****************/
-
-#define LTDC_SSCR_VSH                       ((uint32_t)0x000007FF)              /*!< Vertical Synchronization Height */
-#define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000)              /*!< Horizontal Synchronization Width */
-
-/********************  Bit definition for LTDC_BPCR register  *****************/
-
-#define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FF)              /*!< Accumulated Vertical Back Porch */
-#define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000)              /*!< Accumulated Horizontal Back Porch */
-
-/********************  Bit definition for LTDC_AWCR register  *****************/
-
-#define LTDC_AWCR_AAH                       ((uint32_t)0x000007FF)              /*!< Accumulated Active heigh */
-#define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000)              /*!< Accumulated Active Width */
-
-/********************  Bit definition for LTDC_TWCR register  *****************/
-
-#define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FF)              /*!< Total Heigh */
-#define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000)              /*!< Total Width */
-
-/********************  Bit definition for LTDC_GCR register  ******************/
-
-#define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001)              /*!< LCD-TFT controller enable bit */
-#define LTDC_GCR_DBW                        ((uint32_t)0x00000070)              /*!< Dither Blue Width */
-#define LTDC_GCR_DGW                        ((uint32_t)0x00000700)              /*!< Dither Green Width */
-#define LTDC_GCR_DRW                        ((uint32_t)0x00007000)              /*!< Dither Red Width */
-#define LTDC_GCR_DTEN                       ((uint32_t)0x00010000)              /*!< Dither Enable */
-#define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000)              /*!< Pixel Clock Polarity */
-#define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000)              /*!< Data Enable Polarity */
-#define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000)              /*!< Vertical Synchronization Polarity */
-#define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000)              /*!< Horizontal Synchronization Polarity */
-
-/********************  Bit definition for LTDC_SRCR register  *****************/
-
-#define LTDC_SRCR_IMR                      ((uint32_t)0x00000001)               /*!< Immediate Reload */
-#define LTDC_SRCR_VBR                      ((uint32_t)0x00000002)               /*!< Vertical Blanking Reload */
-
-/********************  Bit definition for LTDC_BCCR register  *****************/
-
-#define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FF)              /*!< Background Blue value */
-#define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00)              /*!< Background Green value */
-#define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000)              /*!< Background Red value */
-
-/********************  Bit definition for LTDC_IER register  ******************/
-
-#define LTDC_IER_LIE                        ((uint32_t)0x00000001)              /*!< Line Interrupt Enable */
-#define LTDC_IER_FUIE                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Enable */
-#define LTDC_IER_TERRIE                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Enable */
-#define LTDC_IER_RRIE                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt enable */
-
-/********************  Bit definition for LTDC_ISR register  ******************/
-
-#define LTDC_ISR_LIF                        ((uint32_t)0x00000001)              /*!< Line Interrupt Flag */
-#define LTDC_ISR_FUIF                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_ICR register  ******************/
-
-#define LTDC_ICR_CLIF                       ((uint32_t)0x00000001)              /*!< Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002)              /*!< Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004)              /*!< Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008)              /*!< Clears Register Reload interrupt Flag */
-
-/********************  Bit definition for LTDC_LIPCR register  ****************/
-
-#define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FF)              /*!< Line Interrupt Position */
-
-/********************  Bit definition for LTDC_CPSR register  *****************/
-
-#define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFF)              /*!< Current Y Position */
-#define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000)              /*!< Current X Position */
-
-/********************  Bit definition for LTDC_CDSR register  *****************/
-
-#define LTDC_CDSR_VDES                      ((uint32_t)0x00000001)              /*!< Vertical Data Enable Status */
-#define LTDC_CDSR_HDES                      ((uint32_t)0x00000002)              /*!< Horizontal Data Enable Status */
-#define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004)              /*!< Vertical Synchronization Status */
-#define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008)              /*!< Horizontal Synchronization Status */
-
-/********************  Bit definition for LTDC_LxCR register  *****************/
-
-#define LTDC_LxCR_LEN                       ((uint32_t)0x00000001)              /*!< Layer Enable */
-#define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002)              /*!< Color Keying Enable */
-#define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010)              /*!< Color Lockup Table Enable */
-
-/********************  Bit definition for LTDC_LxWHPCR register  **************/
-
-#define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Horizontal Stop Position */
-
-/********************  Bit definition for LTDC_LxWVPCR register  **************/
-
-#define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Vertical Stop Position */
-
-/********************  Bit definition for LTDC_LxCKCR register  ***************/
-
-#define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FF)              /*!< Color Key Blue value */
-#define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00)              /*!< Color Key Green value */
-#define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000)              /*!< Color Key Red value */
-
-/********************  Bit definition for LTDC_LxPFCR register  ***************/
-
-#define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007)              /*!< Pixel Format */
-
-/********************  Bit definition for LTDC_LxCACR register  ***************/
-
-#define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FF)              /*!< Constant Alpha */
-
-/********************  Bit definition for LTDC_LxDCCR register  ***************/
-
-#define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FF)              /*!< Default Color Blue */
-#define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00)              /*!< Default Color Green */
-#define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000)              /*!< Default Color Red */
-#define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000)              /*!< Default Color Alpha */
-                                
-/********************  Bit definition for LTDC_LxBFCR register  ***************/
-
-#define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007)              /*!< Blending Factor 2 */
-#define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700)              /*!< Blending Factor 1 */
-
-/********************  Bit definition for LTDC_LxCFBAR register  **************/
-
-#define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFF)              /*!< Color Frame Buffer Start Address */
-
-/********************  Bit definition for LTDC_LxCFBLR register  **************/
-
-#define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFF)              /*!< Color Frame Buffer Line Length */
-#define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000)              /*!< Color Frame Buffer Pitch in bytes */
-
-/********************  Bit definition for LTDC_LxCFBLNR register  *************/
-
-#define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FF)              /*!< Frame Buffer Line Number */
-
-/********************  Bit definition for LTDC_LxCLUTWR register  *************/
-
-#define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FF)              /*!< Blue value */
-#define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00)              /*!< Green value */
-#define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value */
-#define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
-
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
-#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
-#define  PWR_CR_LPUDS                        ((uint32_t)0x00000400)     /*!< Low-Power Regulator in Stop under-drive mode               */
-#define  PWR_CR_MRUDS                        ((uint32_t)0x00000800)     /*!< Main regulator in Stop under-drive mode                    */
-
-#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit */ 
-
-#define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
-
-#define  PWR_CR_ODEN                         ((uint32_t)0x00010000)     /*!< Over Drive enable                   */
-#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000)     /*!< Over Drive switch enabled           */
-#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000)     /*!< Under Drive enable in stop mode     */
-#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000)     /*!< Bit 0                               */
-#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000)     /*!< Bit 1                               */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
-#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
-#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
-#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
-#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
-#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000)     /*!< Over Drive generator ready                       */
-#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000)     /*!< Over Drive Switch ready                          */
-#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000)     /*!< Under Drive ready                                */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
-
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
-#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
-#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
-#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
-#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
-#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
-
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
-#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
-#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
-#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
-#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
-#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
-#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
-#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
-#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
-
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
-#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
-#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
-#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000)
-#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000)
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
-#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
-#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
-#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
-#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
-#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
-#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
-
-#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
-#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
-#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
-#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
-#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
-#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
-#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
-#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
-#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
-#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
-
-#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
-#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
-#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
-
-#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
-#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
-
-#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
-#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
-#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
-#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
-#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
-#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
-#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
-#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
-#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
-#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
-
-/*!< MCO1 configuration */
-#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
-#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
-#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
-
-#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
-
-#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
-#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
-#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
-#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
-
-#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
-#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
-#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
-#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
-
-#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
-#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
-#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
-#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
-#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040)
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
-#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
-#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000)
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
-#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
-#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000)
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
-#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
-#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
-#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
-#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
-#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
-#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
-#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
-#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
-#define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200)
-#define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400)
-#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
-#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
-#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
-#define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000)
-#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
-/* CHIBIOS FIX */
-//#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x10000000)
-#define  RCC_AHB1RSTR_OTGHSRST                ((uint32_t)0x10000000)
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
-#define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010)
-#define  RCC_AHB2RSTR_HASHRST                ((uint32_t)0x00000020)
- /* maintained for legacy purpose */
- #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
-#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
-#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
-
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#if defined(STM32F40_41xxx)
-#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)
-#endif /* STM32F40_41xxx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001)
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
-#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
-#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
-#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
-#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
-#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
-#define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000)
-#define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000)
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
-#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
-#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
-#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
-#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
-#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)
-#define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000)
-#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000)
-#define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000)
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
-#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
-#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
-#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
-#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
-#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
-#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
-#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
-#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
-#define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200)
-#define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400)
-#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
-#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
-#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)
-#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
-#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
-#define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000)
-#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
-#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
-#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
-#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
-#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
-#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
-#define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010)
-#define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020)
-#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
-#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-
-#if defined(STM32F40_41xxx)
-#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)
-#endif /* STM32F40_41xxx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001)
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
-#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
-#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
-#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
-#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
-#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
-#define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000)
-#define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000)
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
-#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
-#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
-#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
-#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
-#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
-#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
-#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000)
-#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000)
-#define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000)
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
-#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
-#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
-#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
-#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
-#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
-#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
-#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
-#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
-#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200)
-#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400)
-#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
-#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
-#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
-#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
-#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
-#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000)
-#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
-#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
-#define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000)
-#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
-#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
-#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
-#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
-#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
-#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
-#define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010)
-#define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020)
-#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
-#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#if defined(STM32F40_41xxx)
-#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)
-#endif /* STM32F40_41xxx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001)
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
-#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
-#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
-#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
-#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
-#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
-#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
-#define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000)
-#define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000)
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
-#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
-#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
-#define  RCC_APB2LPENR_ADC2PEN               ((uint32_t)0x00000200)
-#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
-#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
-#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)
-#define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000)
-#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000)
-#define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000)
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
-
-#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
-#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
-#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
-
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
-#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
-#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
-#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
-#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
-#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
-#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
-#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000)
-#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
-
-/********************  Bit definition for RCC_PLLSAICFGR register  ************/
-#define  RCC_PLLSAICFGR_PLLI2SN              ((uint32_t)0x00007FC0)
-#define  RCC_PLLSAICFGR_PLLI2SQ              ((uint32_t)0x0F000000)
-#define  RCC_PLLSAICFGR_PLLI2SR              ((uint32_t)0x70000000)
-
-/********************  Bit definition for RCC_DCKCFGR register  ***************/
-#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001F)
-#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00)
-#define  RCC_DCKCFGR_PLLSAIDIVR              ((uint32_t)0x00030000)
-#define  RCC_DCKCFGR_SAI1ASRC                ((uint32_t)0x00300000)
-#define  RCC_DCKCFGR_SAI1BSRC                ((uint32_t)0x00C00000)
-#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000)
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
-#define RNG_CR_IE                            ((uint32_t)0x00000008)
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
-#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Serial Audio Interface                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for SAI_GCR register  *******************/
-#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
-#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
-
-#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
-#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010)        /*!<Bit 0 */
-#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020)        /*!<Bit 1 */
-
-/*******************  Bit definition for SAI_xCR1 register  *******************/
-#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003)        /*!<MODE[1:0] bits (Audio Block Mode)           */
-#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-
-#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000C)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
-#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004)        /*!<Bit 0 */
-#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008)        /*!<Bit 1 */
-
-#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0)        /*!<DS[1:0] bits (Data Size) */
-#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020)        /*!<Bit 0 */
-#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040)        /*!<Bit 1 */
-#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080)        /*!<Bit 2 */
-
-#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100)        /*!<LSB First Configuration  */
-#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200)        /*!<ClocK STRobing edge      */
-
-#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00)        /*!<SYNCEN[1:0](SYNChronization ENable) */
-#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400)        /*!<Bit 0 */
-#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800)        /*!<Bit 1 */
-
-#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000)        /*!<Mono mode                  */
-#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000)        /*!<Output Drive               */
-#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000)        /*!<Audio Block enable         */
-#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000)        /*!<DMA enable                 */
-#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000)        /*!<No Divider Configuration   */
-
-#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00780000)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
-#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00080000)        /*!<Bit 0  */
-#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00100000)        /*!<Bit 1  */
-#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00200000)        /*!<Bit 2  */
-#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00400000)        /*!<Bit 3  */
-
-/*******************  Bit definition for SAI_xCR2 register  *******************/
-#define  SAI_xCR2_FTH                     ((uint32_t)0x00000003)        /*!<FTH[1:0](Fifo THreshold)  */
-#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
-
-#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008)        /*!<Fifo FLUSH                       */
-#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010)        /*!<TRIState Management on data line */
-#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020)        /*!<Mute mode                        */
-#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040)        /*!<Muate value                      */
-
-#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80)       /*!<MUTECNT[5:0] (MUTE counter) */
-#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080)        /*!<Bit 0 */
-#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100)        /*!<Bit 1 */
-#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200)        /*!<Bit 2 */
-#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400)        /*!<Bit 3 */
-#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */
-#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */
-
-#define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */
-
-#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */
-#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */
-#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000)        /*!<Bit 1 */
-
-/******************  Bit definition for SAI_xFRCR register  *******************/
-#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FF)        /*!<FRL[1:0](Frame length)  */
-#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
-#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
-#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
-#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
-
-#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00)        /*!<FRL[1:0] (Frame synchronization active level length)  */
-#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800)        /*!<Bit 3 */
-#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000)        /*!<Bit 4 */
-#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000)        /*!<Bit 5 */
-#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000)        /*!<Bit 6 */
-
-#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000)        /*!< Frame Synchronization Definition */
-#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000)        /*!<Frame Synchronization POLarity    */
-#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000)        /*!<Frame Synchronization OFFset      */
-
-/******************  Bit definition for SAI_xSLOTR register  *******************/
-#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001F)        /*!<FRL[4:0](First Bit Offset)  */
-#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001)        /*!<Bit 0 */
-#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002)        /*!<Bit 1 */
-#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004)        /*!<Bit 2 */
-#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008)        /*!<Bit 3 */
-#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010)        /*!<Bit 4 */
-                                     
-#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0)        /*!<SLOTSZ[1:0] (Slot size)  */
-#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080)        /*!<Bit 1 */
-
-#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
-#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000)        /*!<SLOTEN[15:0] (Slot Enable)  */
-
-/*******************  Bit definition for SAI_xIMR register  *******************/
-#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001)        /*!<Overrun underrun interrupt enable                              */
-#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002)        /*!<Mute detection interrupt enable                                */
-#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004)        /*!<Wrong Clock Configuration interrupt enable                     */
-#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008)        /*!<FIFO request interrupt enable                                  */
-#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010)        /*!<Codec not ready interrupt enable                               */
-#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020)        /*!<Anticipated frame synchronization detection interrupt enable   */
-#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040)        /*!<Late frame synchronization detection interrupt enable          */
-
-/********************  Bit definition for SAI_xSR register  *******************/
-#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001)         /*!<Overrun underrun                               */
-#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002)         /*!<Mute detection                                 */
-#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004)         /*!<Wrong Clock Configuration                      */
-#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008)         /*!<FIFO request                                   */
-#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010)         /*!<Codec not ready                                */
-#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020)         /*!<Anticipated frame synchronization detection    */
-#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040)         /*!<Late frame synchronization detection           */
-
-#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
-#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000)         /*!<Bit 0 */
-#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000)         /*!<Bit 1 */
-#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00030000)         /*!<Bit 2 */
-
-/******************  Bit definition for SAI_xCLRFR register  ******************/
-#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001)        /*!<Clear Overrun underrun                               */
-#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002)        /*!<Clear Mute detection                                 */
-#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004)        /*!<Clear Wrong Clock Configuration                      */
-#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008)        /*!<Clear FIFO request                                   */
-#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010)        /*!<Clear Codec not ready                                */
-#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020)        /*!<Clear Anticipated frame synchronization detection    */
-#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040)        /*!<Clear Late frame synchronization detection           */
-
-/******************  Bit definition for SAI_xDR register  ******************/
-#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFF)        
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!<Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!<Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!<Clock divide factor             */
-#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!<Clock enable bit                */
-#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!<Power saving configuration bit  */
-#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!<Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!<Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!<Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!<Command Index                               */
-
-#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!< Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!< Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
-#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!<SD I/O suspend command                                         */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!<Enable CMD completion                                          */
-#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!<Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!<CE-ATA command       */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!<Data transfer enabled bit         */
-#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!<Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!<Data transfer mode selection      */
-#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!<DMA enabled bit                   */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!<Read wait start         */
-#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!<Read wait stop          */
-#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!<Read wait mode          */
-#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!<Clock Phase      */
-#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!<Clock Polarity   */
-#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!<Master Selection */
-
-#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!<BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!<Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!<Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!<Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!<SPI Enable                          */
-#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!<Frame Format                        */
-#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!<Internal slave select               */
-#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!<Software slave management           */
-#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!<Receive only                        */
-#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!<Data Frame Format                   */
-#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!<Transmit CRC next                   */
-#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!<Hardware CRC calculation enable     */
-#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!<Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!<Rx Buffer DMA Enable                 */
-#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!<Tx Buffer DMA Enable                 */
-#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!<SS Output Enable                     */
-#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!<Error Interrupt Enable               */
-#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!<RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!<Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!<Transmit buffer Empty    */
-#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!<Channel side             */
-#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!<Underrun flag            */
-#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!<CRC Error flag           */
-#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!<Mode fault               */
-#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!<Overrun flag             */
-#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!<Busy flag                */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity               */
-
-#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization                 */
-
-#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable         */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler         */
-#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!<Bit 0 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!<Bit 1 */
-#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004) /*!<Bit 2 */
-
-#define SYSCFG_MEMRMP_FB_MODE           ((uint32_t)0x00000100) /*!< User Flash Bank mode */
-
-#define SYSCFG_MEMRMP_SWP_FMC           ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
-#define SYSCFG_MEMRMP_SWP_FMC_0         ((uint32_t)0x00000400) /*!<Bit 0 */
-#define SYSCFG_MEMRMP_SWP_FMC_1         ((uint32_t)0x00000800) /*!<Bit 1 */
-
-
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */
-#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit  */
-
-#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!<EXTI 3 configuration */
-/** 
-  * @brief   EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0006) /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0007) /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint16_t)0x0008) /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint16_t)0x0009) /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint16_t)0x000A) /*!<PK[0] pin */
-
-/** 
-  * @brief   EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0060) /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0070) /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint16_t)0x0080) /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint16_t)0x0090) /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint16_t)0x00A0) /*!<PK[1] pin */
-
-/** 
-  * @brief   EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0600) /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0700) /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint16_t)0x0800) /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint16_t)0x0900) /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint16_t)0x0A00) /*!<PK[2] pin */
-
-/** 
-  * @brief   EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x6000) /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint16_t)0x7000) /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint16_t)0x8000) /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint16_t)0x9000) /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint16_t)0xA000) /*!<PK[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!<EXTI 7 configuration */
-/** 
-  * @brief   EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0006) /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint16_t)0x0007) /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint16_t)0x0008) /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint16_t)0x0009) /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint16_t)0x000A) /*!<PK[4] pin */
-
-/** 
-  * @brief   EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0060) /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint16_t)0x0070) /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint16_t)0x0080) /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint16_t)0x0090) /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint16_t)0x00A0) /*!<PK[5] pin */
-
-/** 
-  * @brief   EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0600) /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint16_t)0x0700) /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint16_t)0x0800) /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint16_t)0x0900) /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint16_t)0x0A00) /*!<PK[6] pin */
-
-/** 
-  * @brief   EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x6000) /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint16_t)0x7000) /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint16_t)0x8000) /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint16_t)0x9000) /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint16_t)0xA000) /*!<PK[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!<EXTI 11 configuration */
-           
-/** 
-  * @brief   EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0006) /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint16_t)0x0007) /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint16_t)0x0008) /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint16_t)0x0009) /*!<PJ[8] pin */
-
-/** 
-  * @brief   EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0060) /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint16_t)0x0070) /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint16_t)0x0080) /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint16_t)0x0090) /*!<PJ[9] pin */
-
-/** 
-  * @brief   EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0600) /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint16_t)0x0700) /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint16_t)0x0800) /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint16_t)0x0900) /*!<PJ[10] pin */
-
-/** 
-  * @brief   EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x6000) /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint16_t)0x7000) /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint16_t)0x8000) /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint16_t)0x9000) /*!<PJ[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!<EXTI 15 configuration */
-/** 
-  * @brief   EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0006) /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint16_t)0x0007) /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint16_t)0x0008) /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint16_t)0x0009) /*!<PJ[12] pin */
-
-/** 
-  * @brief   EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0060) /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint16_t)0x0070) /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint16_t)0x0008) /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint16_t)0x0009) /*!<PJ[13] pin */
-
-/** 
-  * @brief   EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0600) /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint16_t)0x0700) /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint16_t)0x0800) /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint16_t)0x0900) /*!<PJ[14] pin */
-
-/** 
-  * @brief   EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x6000) /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint16_t)0x7000) /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint16_t)0x8000) /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint16_t)0x9000) /*!<PJ[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
-#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable        */
-#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable        */
-#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode        */
-#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction             */
-
-#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable     */
-
-#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
-#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection            */
-
-#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
-#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
-#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
-#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
-#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-
-#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
-#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode                       */
-
-#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable     */
-#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
-#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
-#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
-#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
-#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable                 */
-#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable             */
-#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable               */
-#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable            */
-#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable               */
-#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag              */
-#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
-#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
-#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
-#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
-#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag                 */
-#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag             */
-#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag               */
-#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation                         */
-#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation              */
-#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation              */
-#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation              */
-#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation              */
-#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation                        */
-#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
-#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable              */
-
-#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
-
-#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
-#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable              */
-
-#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable           */
-#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable        */
-
-#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable    */
-#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
-#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
-#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
-#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
-#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
-#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
-#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
-#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
-#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
-#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
-#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
-#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode  */
-#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable                      */
-#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity                    */
-#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable           */
-#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI4_RMP                       ((uint16_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
-#define TIM_OR_TI4_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
-#define TIM_OR_ITR1_RMP                      ((uint16_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
-#define TIM_OR_ITR1_RMP_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!<Parity Error                 */
-#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!<Framing Error                */
-#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!<Noise Error Flag             */
-#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!<OverRun Error                */
-#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!<IDLE line detected           */
-#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!<Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!<Transmission Complete        */
-#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!<Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!<LIN Break Detection Flag     */
-#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!<Fraction of USARTDIV */
-#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!<Send Break                             */
-#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!<Receiver wakeup                        */
-#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!<Receiver Enable                        */
-#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!<Transmitter Enable                     */
-#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!<IDLE Interrupt Enable                  */
-#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!<RXNE Interrupt Enable                  */
-#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!<PE Interrupt Enable                    */
-#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!<Parity Selection                       */
-#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!<Parity Control Enable                  */
-#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!<Wakeup method                          */
-#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!<Word length                            */
-#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!<USART Enable                           */
-#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!<Address of the USART node            */
-#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!<LIN Break Detection Length           */
-#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!<Last Bit Clock pulse                 */
-#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!<Clock Phase                          */
-#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!<Clock Polarity                       */
-#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!<Clock Enable                         */
-
-#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!<Error Interrupt Enable      */
-#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!<IrDA mode Enable            */
-#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!<IrDA Low-Power              */
-#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!<Half-Duplex Selection       */
-#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!<Smartcard NACK enable       */
-#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!<Smartcard mode enable       */
-#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!<DMA Enable Receiver         */
-#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!<DMA Enable Transmitter      */
-#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!<RTS Enable                  */
-#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!<CTS Enable                  */
-#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!<CTS Interrupt Enable        */
-#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!<Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!<Bit 7 */
-
-#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
-#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
-#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
-#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
-#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
-#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
-#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
-#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
-#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
-#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
-#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
-#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
-#define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
-#define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
-#define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
-#define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
-#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
-#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
-  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
-  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
-  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
-  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
-  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
-  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
-  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
-#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
-#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
-#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
-#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
-#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
-#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
-#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
-  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
-  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
-  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
-#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
-#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
-#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
-#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
-#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
-#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
-  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
-  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
-  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
-#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
-#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
-#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
-#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
-#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
-#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
-  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
-  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
-  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
-  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
-  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
-#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
-#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
-  
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
-#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
-  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
-  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
-  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
-  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
-#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
-#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
-#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
-#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
-#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
-#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
-#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
-#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
-#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
-#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
-#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
-#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
-#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
-  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
-  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
-  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
-  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
-  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
-#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Contol Register */
-#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset */
-#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
-#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
-#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
-#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */
-#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
-#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
-#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
-#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
-#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
-#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
-  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
-#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
-  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
-  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
-#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
-#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
-#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
-#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
-  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
-  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
-  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
-  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
-  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
-  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
-  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
-  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
-  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
-  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
-  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
-  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
-  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
-  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
-#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
-#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
-#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
-#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
-#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
-#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
-#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
-#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
-#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
-#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
-#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
-#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
-#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
-  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
-#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
-  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
-  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
-  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
-  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
-#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
-
-/**
-  *
-  */
-
- /**
-  * @}
-  */ 
-
-#ifdef USE_STDPERIPH_DRIVER
-  #include "stm32f4xx_conf.h"
-#endif /* USE_STDPERIPH_DRIVER */
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F4xx_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c
deleted file mode 100644
index 4147095db..000000000
--- a/os/hal/platforms/STM32L1xx/adc_lld.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32L1xx/adc_lld.c
- * @brief   STM32L1xx ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   ADC DMA ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    /* DMA, this could help only if the DMA tries to access an unmapped
-       address space or violates alignment rules.*/
-    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
-  }
-  else {
-    /* It is possible that the conversion group has already be reset by the
-       ADC error handler, in this case this interrupt is spurious.*/
-    if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
-        /* Transfer complete processing.*/
-        _adc_isr_full_code(adcp);
-      }
-      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
-    }
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-/**
- * @brief   ADC interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(ADC1_IRQHandler) {
-  uint32_t sr;
-
-  CH_IRQ_PROLOGUE();
-
-  sr = ADC1->SR;
-  ADC1->SR = 0;
-  /* Note, an overflow may occur after the conversion ended before the driver
-     is able to stop the ADC, this is why the DMA channel is checked too.*/
-  if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
-    /* ADC overflow condition, this could happen only if the DMA is unable
-       to read data fast enough.*/
-    if (ADCD1.grpp != NULL)
-      _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
-  }
-  /* TODO: Add here analog watchdog handling.*/
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if STM32_ADC_USE_ADC1
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-  ADCD1.adc = ADC1;
-  ADCD1.dmastp  = STM32_DMA1_STREAM1;
-  ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-#endif
-
-  /* The shared vector is initialized on driver initialization and never
-     disabled.*/
-  nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  /* If in stopped state then enables the ADC and DMA clocks.*/
-  if (adcp->state == ADC_STOP) {
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-      bool_t b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
-                            (void *)adcp);
-      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
-      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
-      rccEnableADC1(FALSE);
-    }
-#endif /* STM32_ADC_USE_ADC1 */
-
-    /* ADC initial setup, starting the analog part here in order to reduce
-       the latency when starting a conversion.*/
-    adcp->adc->CR1 = 0;
-    adcp->adc->CR2 = 0;
-    adcp->adc->CR2 = ADC_CR2_ADON;
-  }
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  /* If in ready state then disables the ADC clock and analog part.*/
-  if (adcp->state == ADC_READY) {
-    dmaStreamRelease(adcp->dmastp);
-    adcp->adc->CR1 = 0;
-    adcp->adc->CR2 = 0;
-
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp)
-      rccDisableADC1(FALSE);
-#endif
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t mode;
-  const ADCConversionGroup *grpp = adcp->grpp;
-
-  /* DMA setup.*/
-  mode = adcp->dmamode;
-  if (grpp->circular) {
-    mode |= STM32_DMA_CR_CIRC;
-    if (adcp->depth > 1) {
-      /* If circular buffer depth > 1, then the half transfer interrupt
-         is enabled in order to allow streaming processing.*/
-      mode |= STM32_DMA_CR_HTIE;
-    }
-  }
-  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
-  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
-                                            (uint32_t)adcp->depth);
-  dmaStreamSetMode(adcp->dmastp, mode);
-  dmaStreamEnable(adcp->dmastp);
-
-  /* ADC setup.*/
-  adcp->adc->SR    = 0;
-  adcp->adc->SMPR1 = grpp->smpr1;
-  adcp->adc->SMPR2 = grpp->smpr2;
-  adcp->adc->SMPR3 = grpp->smpr3;
-  adcp->adc->SQR1  = grpp->sqr1;
-  adcp->adc->SQR2  = grpp->sqr2;
-  adcp->adc->SQR3  = grpp->sqr3;
-  adcp->adc->SQR4  = grpp->sqr4;
-  adcp->adc->SQR5  = grpp->sqr5;
-
-  /* ADC configuration and start, the start is performed using the method
-     specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
-  adcp->adc->CR1   = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
-  if ((grpp->cr2 & ADC_CR2_SWSTART) != 0)
-    adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
-                                 ADC_CR2_DDS   | ADC_CR2_ADON;
-  else
-    adcp->adc->CR2 = grpp->cr2 |                 ADC_CR2_DMA |
-                                 ADC_CR2_DDS   | ADC_CR2_ADON;
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-  dmaStreamDisable(adcp->dmastp);
-  adcp->adc->CR1 = 0;
-  adcp->adc->CR2 = 0;
-  adcp->adc->CR2 = ADC_CR2_ADON;
-}
-
-/**
- * @brief   Enables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- *          temperature sensor and internal reference voltage.
- * @note    This is an STM32-only functionality.
- */
-void adcSTM32EnableTSVREFE(void) {
-
-  ADC->CCR |= ADC_CCR_TSVREFE;
-}
-
-/**
- * @brief   Disables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- *          temperature sensor and internal reference voltage.
- * @note    This is an STM32-only functionality.
- */
-void adcSTM32DisableTSVREFE(void) {
-
-  ADC->CCR &= ~ADC_CCR_TSVREFE;
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/STM32L1xx/adc_lld.h b/os/hal/platforms/STM32L1xx/adc_lld.h
deleted file mode 100644
index 2ac857c16..000000000
--- a/os/hal/platforms/STM32L1xx/adc_lld.h
+++ /dev/null
@@ -1,484 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32L1xx/adc_lld.h
- * @brief   STM32L1xx ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Triggers selection
- * @{
- */
-#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 24) /**< @brief Trigger source.     */
-/** @} */
-
-/**
- * @name    ADC clock divider settings
- * @{
- */
-#define ADC_CCR_ADCPRE_DIV1     0
-#define ADC_CCR_ADCPRE_DIV2     1
-#define ADC_CCR_ADCPRE_DIV4     2
-/** @} */
-
-/**
- * @name    Available analog channels
- * @{
- */
-#define ADC_CHANNEL_IN0         0   /**< @brief External analog input 0.    */
-#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
-#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
-#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
-#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
-#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
-#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
-#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
-#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
-#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
-#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
-#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
-#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
-#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
-#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
-#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
-#define ADC_CHANNEL_SENSOR      16  /**< @brief Internal temperature sensor.*/
-#define ADC_CHANNEL_VREFINT     17  /**< @brief Internal reference.         */
-#define ADC_CHANNEL_IN18        18  /**< @brief External analog input 18.   */
-#define ADC_CHANNEL_IN19        19  /**< @brief External analog input 19.   */
-#define ADC_CHANNEL_IN20        20  /**< @brief External analog input 20.   */
-#define ADC_CHANNEL_IN21        21  /**< @brief External analog input 21.   */
-#define ADC_CHANNEL_IN22        22  /**< @brief External analog input 22.   */
-#define ADC_CHANNEL_IN23        23  /**< @brief External analog input 23.   */
-#define ADC_CHANNEL_IN24        24  /**< @brief External analog input 24.   */
-#define ADC_CHANNEL_IN25        25  /**< @brief External analog input 25.   */
-/** @} */
-
-/**
- * @name    Sampling rates
- * @{
- */
-#define ADC_SAMPLE_4            0   /**< @brief 4 cycles sampling time.     */
-#define ADC_SAMPLE_9            1   /**< @brief 9 cycles sampling time.     */
-#define ADC_SAMPLE_16           2   /**< @brief 16 cycles sampling time.    */
-#define ADC_SAMPLE_24           3   /**< @brief 24 cycles sampling time.    */
-#define ADC_SAMPLE_48           4   /**< @brief 48 cycles sampling time.    */
-#define ADC_SAMPLE_96           5   /**< @brief 96 cycles sampling time.    */
-#define ADC_SAMPLE_192          6   /**< @brief 192 cycles sampling time.   */
-#define ADC_SAMPLE_384          7   /**< @brief 384 cycles sampling time.   */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1                  FALSE
-#endif
-
-/**
- * @brief   ADC common clock divider.
- * @note    This setting is influenced by the VDDA voltage and other
- *          external conditions, please refer to the STM32L15x datasheet
- *          for more info.<br>
- *          See section 6.3.15 "12-bit ADC characteristics".
- */
-#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV1
-#endif
-
-/**
- * @brief   ADC1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_PRIORITY         2
-#endif
-
-/**
- * @brief   ADC interrupt priority level setting.
- */
-#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_IRQ_PRIORITY              5
-#endif
-
-/**
- * @brief   ADC1 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
-#error "ADC1 not present in the selected device"
-#endif
-
-#if !STM32_ADC_USE_ADC1
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1 DMA"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC1"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
-  ADC_ERR_OVERFLOW = 1                      /**< ADC overflow condition.    */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    The use of this configuration structure requires knowledge of
- *          STM32 ADC cell registers interface, please refer to the STM32
- *          reference manual for details.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   ADC CR1 register initialization data.
-   * @note    All the required bits must be defined into this field except
-   *          @p ADC_CR1_SCAN that is enforced inside the driver.
-   */
-  uint32_t                  cr1;
-  /**
-   * @brief   ADC CR2 register initialization data.
-   * @note    All the required bits must be defined into this field except
-   *          @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
-   *          enforced inside the driver.
-   */
-  uint32_t                  cr2;
-  /**
-   * @brief   ADC SMPR1 register initialization data.
-   * @details In this field must be specified the sample times for channels
-   *          20...25.
-   */
-  uint32_t                  smpr1;
-  /**
-   * @brief   ADC SMPR2 register initialization data.
-   * @details In this field must be specified the sample times for channels
-   *          10...19.
-   */
-  uint32_t                  smpr2;
-  /**
-   * @brief   ADC SMPR3 register initialization data.
-   * @details In this field must be specified the sample times for channels
-   *          0...9.
-   */
-  uint32_t                  smpr3;
-  /**
-   * @brief   ADC SQR1 register initialization data.
-   * @details Conversion group sequence 25...27 + sequence length.
-   */
-  uint32_t                  sqr1;
-  /**
-   * @brief   ADC SQR2 register initialization data.
-   * @details Conversion group sequence 19...24.
-   */
-  uint32_t                  sqr2;
-  /**
-   * @brief   ADC SQR3 register initialization data.
-   * @details Conversion group sequence 13...18.
-   */
-  uint32_t                  sqr3;
-  /**
-   * @brief   ADC SQR3 register initialization data.
-   * @details Conversion group sequence 7...12.
-   */
-  uint32_t                  sqr4;
-  /**
-   * @brief   ADC SQR3 register initialization data.
-   * @details Conversion group sequence 1...6.
-   */
-  uint32_t                  sqr5;
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Pointer to the ADCx registers block.
-   */
-  ADC_TypeDef               *adc;
-  /**
-   * @brief Pointer to associated DMA channel.
-   */
-  const stm32_dma_stream_t  *dmastp;
-  /**
-   * @brief DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Sequences building helper macros
- * @{
- */
-/**
- * @brief   Number of channels in a conversion sequence.
- */
-#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
-
-#define ADC_SQR5_SQ1_N(n)       ((n) << 0)  /**< @brief 1st channel in seq. */
-#define ADC_SQR5_SQ2_N(n)       ((n) << 5)  /**< @brief 2nd channel in seq. */
-#define ADC_SQR5_SQ3_N(n)       ((n) << 10) /**< @brief 3rd channel in seq. */
-#define ADC_SQR5_SQ4_N(n)       ((n) << 15) /**< @brief 4th channel in seq. */
-#define ADC_SQR5_SQ5_N(n)       ((n) << 20) /**< @brief 5th channel in seq. */
-#define ADC_SQR5_SQ6_N(n)       ((n) << 25) /**< @brief 6th channel in seq. */
-
-#define ADC_SQR4_SQ7_N(n)       ((n) << 0)  /**< @brief 7th channel in seq. */
-#define ADC_SQR4_SQ8_N(n)       ((n) << 5)  /**< @brief 8th channel in seq. */
-#define ADC_SQR4_SQ9_N(n)       ((n) << 10) /**< @brief 9th channel in seq. */
-#define ADC_SQR4_SQ10_N(n)      ((n) << 15) /**< @brief 10th channel in seq.*/
-#define ADC_SQR4_SQ11_N(n)      ((n) << 20) /**< @brief 11th channel in seq.*/
-#define ADC_SQR4_SQ12_N(n)      ((n) << 25) /**< @brief 12th channel in seq.*/
-
-#define ADC_SQR3_SQ13_N(n)      ((n) << 0)  /**< @brief 13th channel in seq.*/
-#define ADC_SQR3_SQ14_N(n)      ((n) << 5)  /**< @brief 14th channel in seq.*/
-#define ADC_SQR3_SQ15_N(n)      ((n) << 10) /**< @brief 15th channel in seq.*/
-#define ADC_SQR3_SQ16_N(n)      ((n) << 15) /**< @brief 16th channel in seq.*/
-#define ADC_SQR3_SQ17_N(n)      ((n) << 20) /**< @brief 17th channel in seq.*/
-#define ADC_SQR3_SQ18_N(n)      ((n) << 25) /**< @brief 18th channel in seq.*/
-
-#define ADC_SQR2_SQ19_N(n)      ((n) << 0)  /**< @brief 19th channel in seq.*/
-#define ADC_SQR2_SQ20_N(n)      ((n) << 5)  /**< @brief 20th channel in seq.*/
-#define ADC_SQR2_SQ21_N(n)      ((n) << 10) /**< @brief 21th channel in seq.*/
-#define ADC_SQR2_SQ22_N(n)      ((n) << 15) /**< @brief 22th channel in seq.*/
-#define ADC_SQR2_SQ23_N(n)      ((n) << 20) /**< @brief 23th channel in seq.*/
-#define ADC_SQR2_SQ24_N(n)      ((n) << 25) /**< @brief 24th channel in seq.*/
-
-#define ADC_SQR1_SQ25_N(n)      ((n) << 0)  /**< @brief 25th channel in seq.*/
-#define ADC_SQR1_SQ26_N(n)      ((n) << 5)  /**< @brief 26th channel in seq.*/
-#define ADC_SQR1_SQ27_N(n)      ((n) << 10) /**< @brief 27th channel in seq.*/
-/** @} */
-
-/**
- * @name    Sampling rate settings helper macros
- * @{
- */
-#define ADC_SMPR3_SMP_AN0(n)    ((n) << 0)  /**< @brief AN0 sampling time.  */
-#define ADC_SMPR3_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
-#define ADC_SMPR3_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
-#define ADC_SMPR3_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
-#define ADC_SMPR3_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
-#define ADC_SMPR3_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
-#define ADC_SMPR3_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
-#define ADC_SMPR3_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
-#define ADC_SMPR3_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
-#define ADC_SMPR3_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
-
-#define ADC_SMPR2_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
-#define ADC_SMPR2_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
-#define ADC_SMPR2_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
-#define ADC_SMPR2_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
-#define ADC_SMPR2_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
-#define ADC_SMPR2_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
-#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
-                                                 sampling time.             */
-#define ADC_SMPR2_SMP_VREF(n)   ((n) << 21) /**< @brief Voltage Reference
-                                                 sampling time.             */
-#define ADC_SMPR2_SMP_AN18(n)   ((n) << 24) /**< @brief AN18 sampling time. */
-#define ADC_SMPR2_SMP_AN19(n)   ((n) << 27) /**< @brief AN19 sampling time. */
-
-#define ADC_SMPR1_SMP_AN20(n)   ((n) << 0)  /**< @brief AN20 sampling time. */
-#define ADC_SMPR1_SMP_AN21(n)   ((n) << 3)  /**< @brief AN21 sampling time. */
-#define ADC_SMPR1_SMP_AN22(n)   ((n) << 6)  /**< @brief AN22 sampling time. */
-#define ADC_SMPR1_SMP_AN23(n)   ((n) << 9)  /**< @brief AN23 sampling time. */
-#define ADC_SMPR1_SMP_AN24(n)   ((n) << 12) /**< @brief AN24 sampling time. */
-#define ADC_SMPR1_SMP_AN25(n)   ((n) << 15) /**< @brief AN25 sampling time. */
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-  void adcSTM32EnableTSVREFE(void);
-  void adcSTM32DisableTSVREFE(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32L1xx/ext_lld_isr.c b/os/hal/platforms/STM32L1xx/ext_lld_isr.c
deleted file mode 100644
index ea9259a69..000000000
--- a/os/hal/platforms/STM32L1xx/ext_lld_isr.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32L1xx/ext_lld_isr.c
- * @brief   STM32L1xx EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTI[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI0_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 0);
-  EXTD1.config->channels[0].cb(&EXTD1, 0);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI1_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 1);
-  EXTD1.config->channels[1].cb(&EXTD1, 1);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[2] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI2_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 2);
-  EXTD1.config->channels[2].cb(&EXTD1, 2);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[3] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI3_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 3);
-  EXTD1.config->channels[3].cb(&EXTD1, 3);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[4] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI4_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 4);
-  EXTD1.config->channels[4].cb(&EXTD1, 4);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[5]...EXTI[9] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
-  EXTI->PR = pr;
-  if (pr & (1 << 5))
-    EXTD1.config->channels[5].cb(&EXTD1, 5);
-  if (pr & (1 << 6))
-    EXTD1.config->channels[6].cb(&EXTD1, 6);
-  if (pr & (1 << 7))
-    EXTD1.config->channels[7].cb(&EXTD1, 7);
-  if (pr & (1 << 8))
-    EXTD1.config->channels[8].cb(&EXTD1, 8);
-  if (pr & (1 << 9))
-    EXTD1.config->channels[9].cb(&EXTD1, 9);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[10]...EXTI[15] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
-                   (1 << 15));
-  EXTI->PR = pr;
-  if (pr & (1 << 10))
-    EXTD1.config->channels[10].cb(&EXTD1, 10);
-  if (pr & (1 << 11))
-    EXTD1.config->channels[11].cb(&EXTD1, 11);
-  if (pr & (1 << 12))
-    EXTD1.config->channels[12].cb(&EXTD1, 12);
-  if (pr & (1 << 13))
-    EXTD1.config->channels[13].cb(&EXTD1, 13);
-  if (pr & (1 << 14))
-    EXTD1.config->channels[14].cb(&EXTD1, 14);
-  if (pr & (1 << 15))
-    EXTD1.config->channels[15].cb(&EXTD1, 15);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[16] interrupt handler (PVD).
- *
- * @isr
- */
-CH_IRQ_HANDLER(PVD_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 16);
-  EXTD1.config->channels[16].cb(&EXTD1, 16);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[17] interrupt handler (RTC).
- *
- * @isr
- */
-CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 17);
-  EXTD1.config->channels[17].cb(&EXTD1, 17);
-
-  CH_IRQ_EPILOGUE();
-}
-/**
- * @brief   EXTI[18] interrupt handler (USB_FS_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 18);
-  EXTD1.config->channels[18].cb(&EXTD1, 18);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[19] interrupt handler (TAMPER_STAMP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 19);
-  EXTD1.config->channels[19].cb(&EXTD1, 19);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[20] interrupt handler (RTC_WKUP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 20);
-  EXTD1.config->channels[20].cb(&EXTD1, 20);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   EXTI[21]...EXTI[22] interrupt handler (COMP).
- *
- * @isr
- */
-CH_IRQ_HANDLER(COMP_IRQHandler) {
-  uint32_t pr;
-
-  CH_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 21) | (1 << 22));
-  EXTI->PR = pr;
-  if (pr & (1 << 21))
-    EXTD1.config->channels[21].cb(&EXTD1, 21);
-  if (pr & (1 << 22))
-    EXTD1.config->channels[22].cb(&EXTD1, 22);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(void) {
-
-  nvicEnableVector(EXTI0_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
-  nvicEnableVector(EXTI1_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
-  nvicEnableVector(EXTI2_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
-  nvicEnableVector(EXTI3_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
-  nvicEnableVector(EXTI4_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
-  nvicEnableVector(EXTI9_5_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
-  nvicEnableVector(EXTI15_10_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
-  nvicEnableVector(PVD_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
-  nvicEnableVector(RTC_Alarm_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
-  nvicEnableVector(USB_FS_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
-  nvicEnableVector(TAMPER_STAMP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
-  nvicEnableVector(RTC_WKUP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
-  nvicEnableVector(COMP_IRQn,
-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_IRQ_PRIORITY));
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(void) {
-
-  nvicDisableVector(EXTI0_IRQn);
-  nvicDisableVector(EXTI1_IRQn);
-  nvicDisableVector(EXTI2_IRQn);
-  nvicDisableVector(EXTI3_IRQn);
-  nvicDisableVector(EXTI4_IRQn);
-  nvicDisableVector(EXTI9_5_IRQn);
-  nvicDisableVector(EXTI15_10_IRQn);
-  nvicDisableVector(PVD_IRQn);
-  nvicDisableVector(RTC_Alarm_IRQn);
-  nvicDisableVector(USB_FS_WKUP_IRQn);
-  nvicDisableVector(TAMPER_STAMP_IRQn);
-  nvicDisableVector(RTC_WKUP_IRQn);
-  nvicDisableVector(COMP_IRQn);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c
deleted file mode 100644
index 5ed7d5476..000000000
--- a/os/hal/platforms/STM32L1xx/hal_lld.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32L1xx/hal_lld.c
- * @brief   STM32L1xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-/* TODO: LSEBYP like in F3.*/
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes the backup domain.
- */
-static void hal_lld_backup_domain_init(void) {
-
-  /* Backup domain access enabled and left open.*/
-  PWR->CR |= PWR_CR_DBP;
-
-  /* Reset BKP domain if different clock source selected.*/
-  if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
-    /* Backup domain reset.*/
-    RCC->CSR |= RCC_CSR_RTCRST;
-    RCC->CSR &= ~RCC_CSR_RTCRST;
-  }
-
-  /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-  RCC->CSR |= RCC_CSR_LSEON;
-  while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
-#endif
-
-#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
-  /* If the backup domain hasn't been initialized yet then proceed with
-     initialization.*/
-  if ((RCC->CSR & RCC_CSR_RTCEN) == 0) {
-    /* Selects clock source.*/
-    RCC->CSR |= STM32_RTCSEL;
-
-    /* RTC clock enabled.*/
-    RCC->CSR |= RCC_CSR_RTCEN;
-  }
-#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* Reset of all peripherals.*/
-  rccResetAHB(~RCC_AHBRSTR_FLITFRST);
-  rccResetAPB1(~RCC_APB1RSTR_PWRRST);
-  rccResetAPB2(~0);
-
-  /* SysTick initialization using the system clock.*/
-  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
-  SysTick->VAL = 0;
-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                  SysTick_CTRL_ENABLE_Msk |
-                  SysTick_CTRL_TICKINT_Msk;
-
-  /* DWT cycle counter enable.*/
-  SCS_DEMCR |= SCS_DEMCR_TRCENA;
-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
-
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(FALSE);
-
-  /* Initializes the backup domain.*/
-  hal_lld_backup_domain_init();
-
-#if defined(STM32_DMA_REQUIRED)
-  dmaInit();
-#endif
-
-  /* Programmable voltage detector enable.*/
-#if STM32_PVD_ENABLE
-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-#endif /* STM32_PVD_ENABLE */
-}
-
-/**
- * @brief   STM32L1xx voltage, clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function should be invoked just after the system reset.
- *
- * @special
- */
-#if defined(STM32L1XX_MD) || defined(__DOXYGEN__)
-/**
- * @brief   Clocks and internal voltage initialization.
- */
-void stm32_clock_init(void) {
-
-#if !STM32_NO_INIT
-  /* PWR clock enable.*/
-  RCC->APB1ENR = RCC_APB1ENR_PWREN;
-
-  /* Core voltage setup.*/
-  while ((PWR->CSR & PWR_CSR_VOSF) != 0)
-    ;                           /* Waits until regulator is stable.         */
-  PWR->CR = STM32_VOS;
-  while ((PWR->CSR & PWR_CSR_VOSF) != 0)
-    ;                           /* Waits until regulator is stable.         */
-
-  /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
-     always enabled because it is the fallback clock when PLL the fails.
-     Trim fields are not altered from reset values.*/
-  RCC->CFGR  = 0;
-  RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
-  RCC->CR    = RCC_CR_MSION;
-  while ((RCC->CR & RCC_CR_MSIRDY) == 0)
-    ;                           /* Waits until MSI is stable.               */
-
-#if STM32_HSI_ENABLED
-  /* HSI activation.*/
-  RCC->CR |= RCC_CR_HSION;
-  while ((RCC->CR & RCC_CR_HSIRDY) == 0)
-    ;                           /* Waits until HSI is stable.               */
-#endif
-
-#if STM32_HSE_ENABLED
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEBYP;
-#endif
-  /* HSE activation.*/
-  RCC->CR |= RCC_CR_HSEON;
-  while ((RCC->CR & RCC_CR_HSERDY) == 0)
-    ;                           /* Waits until HSE is stable.               */
-#endif
-
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                           /* Waits until LSI is stable.               */
-#endif
-
-#if STM32_LSE_ENABLED
-  /* LSE activation, have to unlock the register.*/
-  if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
-    PWR->CR |= PWR_CR_DBP;
-    RCC->CSR |= RCC_CSR_LSEON;
-    PWR->CR &= ~PWR_CR_DBP;
-  }
-  while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
-    ;                           /* Waits until LSE is stable.               */
-#endif
-
-#if STM32_ACTIVATE_PLL
-  /* PLL activation.*/
-  RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;                           /* Waits until PLL is stable.               */
-#endif
-
-  /* Other clock-related settings (dividers, MCO etc).*/
-  RCC->CR   |= STM32_RTCPRE;
-  RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
-               STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
-  RCC->CSR  |= STM32_RTCSEL;
-
-  /* Flash setup and final clock selection.*/
-#if defined(STM32_FLASHBITS1)
-  FLASH->ACR = STM32_FLASHBITS1;
-#endif
-#if defined(STM32_FLASHBITS2)
-  FLASH->ACR = STM32_FLASHBITS2;
-#endif
-
-  /* Switching to the configured clock source if it is different from MSI.*/
-#if (STM32_SW != STM32_SW_MSI)
-  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-#endif
-#endif /* STM32_NO_INIT */
-
-  /* SYSCFG clock enabled here because it is a multi-functional unit shared
-     among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
-}
-#else
-void stm32_clock_init(void) {}
-#endif
-
-/** @} */
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h
deleted file mode 100644
index 86aa2b778..000000000
--- a/os/hal/platforms/STM32L1xx/hal_lld.h
+++ /dev/null
@@ -1,1084 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32L1xx/hal_lld.h
- * @brief   STM32L1xx HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - STM32_LSECLK.
- *          - STM32_HSECLK.
- *          - STM32_HSE_BYPASS (optionally).
- *          .
- *          One of the following macros must also be defined:
- *          - STM32L1XX_MD for Ultra Low Power Medium-density devices.
- *          - STM32L1XX_MDP for Ultra Low Power Medium-density Plus devices.
- *          - STM32L1XX_HD for Ultra Low Power High-density devices.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "stm32.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @name    Platform identification
- * @{
- */
-#if defined(STM32L1XX_MD) || defined(__DOXYGEN__)
-#define PLATFORM_NAME           "STM32L1xx Ultra Low Power Medium Density"
-#define STM32L1XX
-
-#elif defined(STM32L1XX_MDP)
-#define PLATFORM_NAME           "STM32L1xx Ultra Low Power Medium Density Plus"
-#define STM32L1XX
-
-#elif defined(STM32L1XX_HD)
-#define PLATFORM_NAME           "STM32L1xx Ultra Low Power High Density"
-#define STM32L1XX
-
-#else
-#error "STM32L1xx device not specified"
-#endif
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define STM32_HSICLK            16000000    /**< High speed internal clock. */
-#define STM32_LSICLK            38000       /**< Low speed internal clock.  */
-/** @} */
-
-/**
- * @name    PWR_CR register bits definitions
- * @{
- */
-#define STM32_VOS_MASK          (3 << 11)   /**< Core voltage mask.         */
-#define STM32_VOS_1P8           (1 << 11)   /**< Core voltage 1.8 Volts.    */
-#define STM32_VOS_1P5           (2 << 11)   /**< Core voltage 1.5 Volts.    */
-#define STM32_VOS_1P2           (3 << 11)   /**< Core voltage 1.2 Volts.    */
-
-#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
-#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
-#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
-#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
-#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
-#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
-#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
-#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
-#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
-/** @} */
-
-/**
- * @name    RCC_CR register bits definitions
- * @{
- */
-#define STM32_RTCPRE_MASK       (3 << 29)   /**< RTCPRE mask.               */
-#define STM32_RTCPRE_DIV2       (0 << 29)   /**< HSE divided by 2.          */
-#define STM32_RTCPRE_DIV4       (1 << 29)   /**< HSE divided by 4.          */
-#define STM32_RTCPRE_DIV8       (2 << 29)   /**< HSE divided by 2.          */
-#define STM32_RTCPRE_DIV16      (3 << 29)   /**< HSE divided by 16.         */
-/** @} */
-
-/**
- * @name    RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_MSI            (0 << 0)    /**< SYSCLK source is MSI.      */
-#define STM32_SW_HSI            (1 << 0)    /**< SYSCLK source is HSI.      */
-#define STM32_SW_HSE            (2 << 0)    /**< SYSCLK source is HSE.      */
-#define STM32_SW_PLL            (3 << 0)    /**< SYSCLK source is PLL.      */
-
-#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
-#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
-#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
-#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
-#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
-#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
-#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
-#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
-#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
-
-#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
-#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
-#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
-#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
-#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
-
-#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
-#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
-#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
-#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
-#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
-
-#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
-#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
-
-#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
-#define STM32_MCOSEL_SYSCLK     (1 << 24)   /**< SYSCLK on MCO pin.         */
-#define STM32_MCOSEL_HSI        (2 << 24)   /**< HSI clock on MCO pin.      */
-#define STM32_MCOSEL_MSI        (3 << 24)   /**< MSI clock on MCO pin.      */
-#define STM32_MCOSEL_HSE        (4 << 24)   /**< HSE clock on MCO pin.      */
-#define STM32_MCOSEL_PLL        (5 << 24)   /**< PLL clock on MCO pin.      */
-#define STM32_MCOSEL_LSI        (6 << 24)   /**< LSI clock on MCO pin.      */
-#define STM32_MCOSEL_LSE        (7 << 24)   /**< LSE clock on MCO pin.      */
-
-#define STM32_MCOPRE_DIV1       (0 << 28)   /**< MCO divided by 1.          */
-#define STM32_MCOPRE_DIV2       (1 << 28)   /**< MCO divided by 1.          */
-#define STM32_MCOPRE_DIV4       (2 << 28)   /**< MCO divided by 1.          */
-#define STM32_MCOPRE_DIV8       (3 << 28)   /**< MCO divided by 1.          */
-#define STM32_MCOPRE_DIV16      (4 << 28)   /**< MCO divided by 1.          */
-/** @} */
-
-/**
- * @name    RCC_ICSCR register bits definitions
- * @{
- */
-#define STM32_MSIRANGE_MASK     (7 << 13)   /**< MSIRANGE field mask.       */
-#define STM32_MSIRANGE_64K      (0 << 13)   /**< 64kHz nominal.             */
-#define STM32_MSIRANGE_128K     (1 << 13)   /**< 128kHz nominal.            */
-#define STM32_MSIRANGE_256K     (2 << 13)   /**< 256kHz nominal.            */
-#define STM32_MSIRANGE_512K     (3 << 13)   /**< 512kHz nominal.            */
-#define STM32_MSIRANGE_1M       (4 << 13)   /**< 1MHz nominal.              */
-#define STM32_MSIRANGE_2M       (5 << 13)   /**< 2MHz nominal.              */
-#define STM32_MSIRANGE_4M       (6 << 13)   /**< 4MHz nominal               */
-/** @} */
-
-/**
- * @name    RCC_CSR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK       (3 << 16)   /**< RTC source mask.           */
-#define STM32_RTCSEL_NOCLOCK    (0 << 16)   /**< No RTC source.             */
-#define STM32_RTCSEL_LSE        (1 << 16)   /**< RTC source is LSE.         */
-#define STM32_RTCSEL_LSI        (2 << 16)   /**< RTC source is LSI.         */
-#define STM32_RTCSEL_HSEDIV     (3 << 16)   /**< RTC source is HSE divided. */
-/** @} */
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    STM32L1xx capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_HAS_ADC2          FALSE
-#define STM32_HAS_ADC3          FALSE
-#define STM32_HAS_ADC4          FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          FALSE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 23
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         TRUE
-#define STM32_HAS_GPIOF         FALSE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         TRUE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_I2C3_RX_DMA_MSK   0
-#define STM32_I2C3_RX_DMA_CHN   0x00000000
-#define STM32_I2C3_TX_DMA_MSK   0
-#define STM32_I2C3_TX_DMA_CHN   0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#define STM32_RTC_IS_CALENDAR   TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          TRUE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          FALSE
-#define STM32_HAS_SPI4          FALSE
-#define STM32_HAS_SPI5          FALSE
-#define STM32_HAS_SPI6          FALSE
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          FALSE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          TRUE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          TRUE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          TRUE
-#define STM32_HAS_TIM10         TRUE
-#define STM32_HAS_TIM11         TRUE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         FALSE
-#define STM32_HAS_TIM15         FALSE
-#define STM32_HAS_TIM16         FALSE
-#define STM32_HAS_TIM17         FALSE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        TRUE
-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         FALSE
-#define STM32_UART4_RX_DMA_MSK  0
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  0
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         FALSE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           TRUE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names.                                     */
-/*===========================================================================*/
-
-/**
- * @name  IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler         Vector40    /**< Window Watchdog.           */
-#define PVD_IRQHandler          Vector44    /**< PVD through EXTI Line
-                                                 detect.                    */
-#define TAMPER_STAMP_IRQHandler Vector48    /**< Tamper and Time Stamp
-                                                 through EXTI.              */
-#define RTC_WKUP_IRQHandler     Vector4C    /**< RTC Wakeup Timer through
-                                                 EXTI.                      */
-#define FLASH_IRQHandler        Vector50    /**< Flash.                     */
-#define RCC_IRQHandler          Vector54    /**< RCC.                       */
-#define EXTI0_IRQHandler        Vector58    /**< EXTI Line 0.               */
-#define EXTI1_IRQHandler        Vector5C    /**< EXTI Line 1.               */
-#define EXTI2_IRQHandler        Vector60    /**< EXTI Line 2.               */
-#define EXTI3_IRQHandler        Vector64    /**< EXTI Line 3.               */
-#define EXTI4_IRQHandler        Vector68    /**< EXTI Line 4.               */
-#define DMA1_Ch1_IRQHandler     Vector6C    /**< DMA1 Channel 1.            */
-#define DMA1_Ch2_IRQHandler     Vector70    /**< DMA1 Channel 2.            */
-#define DMA1_Ch3_IRQHandler     Vector74    /**< DMA1 Channel 3.            */
-#define DMA1_Ch4_IRQHandler     Vector78    /**< DMA1 Channel 4.            */
-#define DMA1_Ch5_IRQHandler     Vector7C    /**< DMA1 Channel 5.            */
-#define DMA1_Ch6_IRQHandler     Vector80    /**< DMA1 Channel 6.            */
-#define DMA1_Ch7_IRQHandler     Vector84    /**< DMA1 Channel 7.            */
-#define ADC1_IRQHandler         Vector88    /**< ADC1.                      */
-#define USB_HP_IRQHandler       Vector8C    /**< USB High Priority.         */
-#define USB_LP_IRQHandler       Vector90    /**< USB Low Priority.          */
-#define DAC_IRQHandler          Vector94    /**< DAC.                       */
-#define COMP_IRQHandler         Vector98    /**< Comparator through EXTI.   */
-#define EXTI9_5_IRQHandler      Vector9C    /**< EXTI Line 9..5.            */
-#define LCD_IRQHandler          VectorA0    /**< LCD.                       */
-#define TIM9_IRQHandler         VectorA4    /**< TIM9.                      */
-#define TIM10_IRQHandler        VectorA8    /**< TIM10.                     */
-#define TIM11_IRQHandler        VectorAC    /**< TIM11.                     */
-#define TIM2_IRQHandler         VectorB0    /**< TIM2.                      */
-#define TIM3_IRQHandler         VectorB4    /**< TIM3.                      */
-#define TIM4_IRQHandler         VectorB8    /**< TIM4.                      */
-#define I2C1_EV_IRQHandler      VectorBC    /**< I2C1 Event.                */
-#define I2C1_ER_IRQHandler      VectorC0    /**< I2C1 Error.                */
-#define I2C2_EV_IRQHandler      VectorC4    /**< I2C2 Event.                */
-#define I2C2_ER_IRQHandler      VectorC8    /**< I2C2 Error.                */
-#define SPI1_IRQHandler         VectorCC    /**< SPI1.                      */
-#define SPI2_IRQHandler         VectorD0    /**< SPI2.                      */
-#define USART1_IRQHandler       VectorD4    /**< USART1.                    */
-#define USART2_IRQHandler       VectorD8    /**< USART2.                    */
-#define USART3_IRQHandler       VectorDC    /**< USART3.                    */
-#define EXTI15_10_IRQHandler    VectorE0    /**< EXTI Line 15..10.          */
-#define RTC_Alarm_IRQHandler    VectorE4    /**< RTC Alarm through EXTI.    */
-#define USB_FS_WKUP_IRQHandler  VectorE8    /**< USB Wakeup from suspend.   */
-#define TIM6_IRQHandler         VectorEC    /**< TIM6.                      */
-#define TIM7_IRQHandler         VectorF0    /**< TIM7.                      */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Disables the PWR/RCC initialization in the HAL.
- */
-#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT               FALSE
-#endif
-
-/**
- * @brief   Core voltage selection.
- * @note    This setting affects all the performance and clock related
- *          settings, the maximum performance is only obtainable selecting
- *          the maximum voltage.
- */
-#if !defined(STM32_VOS) || defined(__DOXYGEN__)
-#define STM32_VOS                   STM32_VOS_1P8
-#endif
-
-/**
- * @brief   Enables or disables the programmable voltage detector.
- */
-#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE            FALSE
-#endif
-
-/**
- * @brief   Sets voltage level for programmable voltage detector.
- */
-#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS                   STM32_PLS_LEV0
-#endif
-
-/**
- * @brief   Enables or disables the HSI clock source.
- */
-#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSI clock source.
- */
-#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the HSE clock source.
- */
-#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED           FALSE
-#endif
-
-/**
- * @brief   Enables or disables the LSE clock source.
- */
-#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED           FALSE
-#endif
-
-/**
- * @brief   ADC clock setting.
- */
-#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
-#define STM32_ADC_CLOCK_ENABLED     TRUE
-#endif
-
-/**
- * @brief   USB clock setting.
- */
-#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
-#define STM32_USB_CLOCK_ENABLED     TRUE
-#endif
-
-/**
- * @brief   MSI frequency setting.
- */
-#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
-#define STM32_MSIRANGE              STM32_MSIRANGE_2M
-#endif
-
-/**
- * @brief   Main clock source selection.
- * @note    If the selected clock source is not the PLL then the PLL is not
- *          initialized and started.
- * @note    The default value is calculated for a 32MHz system clock from
- *          the internal 16MHz HSI clock.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW                    STM32_SW_PLL
-#endif
-
-/**
- * @brief   Clock source for the PLL.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 32MHz system clock from
- *          the internal 16MHz HSI clock.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                STM32_PLLSRC_HSI
-#endif
-
-/**
- * @brief   PLL multiplier value.
- * @note    The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.
- * @note    The default value is calculated for a 32MHz system clock from
- *          the internal 16MHz HSI clock.
- */
-#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE          6
-#endif
-
-/**
- * @brief   PLL divider value.
- * @note    The allowed values are 2, 3, 4.
- * @note    The default value is calculated for a 32MHz system clock from
- *          the internal 16MHz HSI clock.
- */
-#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLDIV_VALUE          3
-#endif
-
-/**
- * @brief   AHB prescaler value.
- * @note    The default value is calculated for a 32MHz system clock from
- *          the internal 16MHz HSI clock.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE                  STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief   APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1                 STM32_PPRE1_DIV1
-#endif
-
-/**
- * @brief   APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2                 STM32_PPRE2_DIV1
-#endif
-
-/**
- * @brief   MCO clock source.
- */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
-#endif
-
-/**
- * @brief   MCO divider setting.
- */
-#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
-#define STM32_MCOPRE                STM32_MCOPRE_DIV1
-#endif
-
-/**
- * @brief   RTC/LCD clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL                STM32_RTCSEL_LSE
-#endif
-
-/**
- * @brief   HSE divider toward RTC setting.
- */
-#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
-#define STM32_RTCPRE                STM32_RTCPRE_DIV2
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32L1xx_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32L1xx_MCUCONF not defined"
-#endif
-
-/* Voltage related limits.*/
-#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
-/**
- * @brief   Maximum HSE clock frequency at current voltage setting.
- */
-#define STM32_HSECLK_MAX            32000000
-
-/**
- * @brief   Maximum SYSCLK clock frequency at current voltage setting.
- */
-#define STM32_SYSCLK_MAX            32000000
-
-/**
- * @brief   Maximum VCO clock frequency at current voltage setting.
- */
-#define STM32_PLLVCO_MAX            96000000
-
-/**
- * @brief   Minimum VCO clock frequency at current voltage setting.
- */
-#define STM32_PLLVCO_MIN            6000000
-
-/**
- * @brief   Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX             32000000
-
-/**
- * @brief   Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX             32000000
-
-/**
- * @brief   Maximum frequency not requiring a wait state for flash accesses.
- */
-#define STM32_0WS_THRESHOLD         16000000
-
-/**
- * @brief   HSI availability at current voltage settings.
- */
-#define STM32_HSI_AVAILABLE         TRUE
-
-#elif STM32_VOS == STM32_VOS_1P5
-#define STM32_HSECLK_MAX            16000000
-#define STM32_SYSCLK_MAX            16000000
-#define STM32_PLLVCO_MAX            48000000
-#define STM32_PLLVCO_MIN            6000000
-#define STM32_PCLK1_MAX             16000000
-#define STM32_PCLK2_MAX             16000000
-#define STM32_0WS_THRESHOLD         8000000
-#define STM32_HSI_AVAILABLE         TRUE
-#elif STM32_VOS == STM32_VOS_1P2
-#define STM32_HSECLK_MAX            4000000
-#define STM32_SYSCLK_MAX            4000000
-#define STM32_PLLVCO_MAX            24000000
-#define STM32_PLLVCO_MIN            6000000
-#define STM32_PCLK1_MAX             4000000
-#define STM32_PCLK2_MAX             4000000
-#define STM32_0WS_THRESHOLD         2000000
-#define STM32_HSI_AVAILABLE         FALSE
-#else
-#error "invalid STM32_VOS value specified"
-#endif
-
-/* HSI related checks.*/
-#if STM32_HSI_ENABLED
-#if !STM32_HSI_AVAILABLE
-  #error "impossible to activate HSI under the current voltage settings"
-#endif
-#else /* !STM32_HSI_ENABLED */
-#if STM32_ADC_CLOCK_ENABLED ||                                              \
-    (STM32_SW == STM32_SW_HSI) ||                                           \
-    ((STM32_SW == STM32_SW_PLL) &&                                          \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI)) ||                                 \
-    (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLL) &&                                  \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "required HSI clock is not enabled"
-#endif
-#endif /* !STM32_HSI_ENABLED */
-
-/* HSE related checks.*/
-#if STM32_HSE_ENABLED
-#if STM32_HSECLK == 0
-#error "impossible to activate HSE"
-#endif
-#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"
-#endif
-#else /* !STM32_HSE_ENABLED */
-#if (STM32_SW == STM32_SW_HSE) ||                                           \
-    ((STM32_SW == STM32_SW_PLL) &&                                          \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE)) ||                                 \
-    (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLL) &&                                  \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE)) ||                                 \
-    (STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
-#error "required HSE clock is not enabled"
-#endif
-#endif /* !STM32_HSE_ENABLED */
-
-/* LSI related checks.*/
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-#if STM32_RTCCLK == STM32_LSICLK
-#error "required LSI clock is not enabled"
-#endif
-#endif /* !STM32_LSI_ENABLED */
-
-/* LSE related checks.*/
-#if STM32_LSE_ENABLED
-#if (STM32_LSECLK == 0)
-#error "impossible to activate LSE"
-#endif
-#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
-#error "STM32_LSECLK outside acceptable range (1...1000kHz)"
-#endif
-#else /* !STM32_LSE_ENABLED */
-#if STM32_RTCCLK == STM32_LSECLK
-#error "required LSE clock is not enabled"
-#endif
-#endif /* !STM32_LSE_ENABLED */
-
-/* PLL related checks.*/
-#if STM32_USB_CLOCK_ENABLED ||                                              \
-    (STM32_SW == STM32_SW_PLL) ||                                           \
-    (STM32_MCOSEL == STM32_MCOSEL_PLL) ||                                   \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL          TRUE
-#else
-#define STM32_ACTIVATE_PLL          FALSE
-#endif
-
-/**
- * @brief   PLLMUL field.
- */
-#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__)
-#define STM32_PLLMUL                (0 << 18)
-#elif STM32_PLLMUL_VALUE == 4
-#define STM32_PLLMUL                (1 << 18)
-#elif STM32_PLLMUL_VALUE == 6
-#define STM32_PLLMUL                (2 << 18)
-#elif STM32_PLLMUL_VALUE == 8
-#define STM32_PLLMUL                (3 << 18)
-#elif STM32_PLLMUL_VALUE == 12
-#define STM32_PLLMUL                (4 << 18)
-#elif STM32_PLLMUL_VALUE == 16
-#define STM32_PLLMUL                (5 << 18)
-#elif STM32_PLLMUL_VALUE == 24
-#define STM32_PLLMUL                (6 << 18)
-#elif STM32_PLLMUL_VALUE == 32
-#define STM32_PLLMUL                (7 << 18)
-#elif STM32_PLLMUL_VALUE == 48
-#define STM32_PLLMUL                (8 << 18)
-#else
-#error "invalid STM32_PLLMUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLLDIV field.
- */
-#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLDIV                (1 << 22)
-#elif STM32_PLLDIV_VALUE == 3
-#define STM32_PLLDIV                (2 << 22)
-#elif STM32_PLLDIV_VALUE == 4
-#define STM32_PLLDIV                (3 << 22)
-#else
-#error "invalid STM32_PLLDIV_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLCLKIN              STM32_HSECLK
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN              STM32_HSICLK
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/* PLL input frequency range check.*/
-#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000)
-#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)"
-#endif
-
-/**
- * @brief   PLL VCO frequency.
- */
-#define STM32_PLLVCO                (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
-#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT             (STM32_PLLVCO / STM32_PLLDIV_VALUE)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000)
-#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)"
-#endif
-
-/**
- * @brief   MSI frequency.
- * @note    Values are taken from the STM8Lxx datasheet.
- */
-#if STM32_MSIRANGE == STM32_MSIRANGE_64K
-#define STM32_MSICLK                65500
-#elif STM32_MSIRANGE == STM32_MSIRANGE_128K
-#define STM32_MSICLK                131000
-#elif STM32_MSIRANGE == STM32_MSIRANGE_256K
-#define STM32_MSICLK                262000
-#elif STM32_MSIRANGE == STM32_MSIRANGE_512K
-#define STM32_MSICLK                524000
-#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
-#define STM32_MSICLK                1050000
-#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
-#define STM32_MSICLK                2100000
-#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
-#define STM32_MSICLK                4200000
-#else
-#error "invalid STM32_MSIRANGE value specified"
-#endif
-
-/**
- * @brief   System clock source.
- */
-#if STM32_NO_INIT || defined(__DOXYGEN__)
-#define STM32_SYSCLK                2100000
-#elif (STM32_SW == STM32_SW_MSI)
-#define STM32_SYSCLK                STM32_MSICLK
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
-#elif (STM32_SW == STM32_SW_PLL)
-#define STM32_SYSCLK                STM32_PLLCLKOUT
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/* AHB frequency check.*/
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                 (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                 (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                 (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                 (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/* APB1 frequency check.*/
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief   APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                 (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                 (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                 (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                 (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/**
- * @brief   MCO divider clock.
- */
-#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_MCODIVCLK             0
-#elif STM32_MCOSEL == STM32_MCOSEL_HSI
-#define STM32_MCODIVCLK             STM32_HSICLK
-#elif STM32_MCOSEL == STM32_MCOSEL_MSI
-#define STM32_MCODIVCLK             STM32_MSICLK
-#elif STM32_MCOSEL == STM32_MCOSEL_HSE
-#define STM32_MCODIVCLK             STM32_HSECLK
-#elif STM32_MCOSEL == STM32_MCOSEL_PLL
-#define STM32_MCODIVCLK             STM32_PLLCLKOUT
-#elif STM32_MCOSEL == STM32_MCOSEL_LSI
-#define STM32_MCODIVCLK             STM32_LSICLK
-#elif STM32_MCOSEL == STM32_MCOSEL_LSE
-#define STM32_MCODIVCLK             STM32_LSECLK
-#else
-#error "invalid STM32_MCOSEL value specified"
-#endif
-
-/**
- * @brief   MCO output pin clock.
- */
-#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_MCOCLK                STM32_MCODIVCLK
-#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 2)
-#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 4)
-#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 8)
-#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
-#define STM32_MCOCLK                (STM32_MCODIVCLK / 16)
-#else
-#error "invalid STM32_MCOPRE value specified"
-#endif
-
-/**
- * @brief   HSE divider toward RTC clock.
- */
-#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK             (STM32_HSECLK / 2)
-#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK             (STM32_HSECLK / 4)
-#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK             (STM32_HSECLK / 8)
-#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK             (STM32_HSECLK / 16)
-#else
-#error "invalid STM32_RTCPRE value specified"
-#endif
-
-/**
- * @brief   RTC/LCD clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                  0
-#elif STM32_RTCSEL == STM32_RTCSEL_LSE
-#define STM32_RTCCLK                  STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                  STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                  STM32_HSEDIVCLK
-#else
-#error "invalid STM32_RTCSEL value specified"
-#endif
-
-/**
- * @brief   ADC frequency.
- */
-#define STM32_ADCCLK                STM32_HSICLK
-
-/**
- * @brief   USB frequency.
- */
-#define STM32_USBCLK                (STM32_PLLVCO / 2)
-
-/**
- * @brief   Timers 2, 3, 4, 6, 7 clock.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief   Timers 9, 10, 11 clock.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
-#endif
-
-/**
- * @brief   Flash settings.
- */
-#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS1            0x00000000
-#else
-#define STM32_FLASHBITS1            0x00000004
-#define STM32_FLASHBITS2            0x00000007
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief   Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This service is implemented by returning the content of the
- *          DWT_CYCCNT register.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value()         DWT_CYCCNT
-
-/**
- * @brief   Realtime counter frequency.
- * @note    The DWT_CYCCNT register is incremented directly by the system
- *          clock so this function returns STM32_HCLK.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency()     STM32_HCLK
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-/* STM32 ISR, DMA and RCC helpers.*/
-#include "stm32_isr.h"
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void stm32_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32L1xx/platform.mk b/os/hal/platforms/STM32L1xx/platform.mk
deleted file mode 100644
index 05a50a362..000000000
--- a/os/hal/platforms/STM32L1xx/platform.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-# List of all the STM32L1xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \
-              ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32L1xx/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32L1xx \
-              ${CHIBIOS}/os/hal/platforms/STM32 \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
-              ${CHIBIOS}/os/hal/platforms/STM32/USBv1
diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.c b/os/hal/platforms/STM32L1xx/stm32_dma.c
deleted file mode 100644
index 5c74e9227..000000000
--- a/os/hal/platforms/STM32L1xx/stm32_dma.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32L1xx/stm32_dma.c
- * @brief   DMA helper driver code.
- *
- * @addtogroup STM32L1xx_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- *          shared resource, this driver allows to allocate and free DMA
- *          streams at runtime in order to allow all the other device
- *          drivers to coordinate the access to the resource.
- * @note    The DMA ISR handlers are all declared into this module because
- *          sharing, the various device drivers can associate a callback to
- *          ISRs when allocating streams.
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
-   has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK     0x0000007F
-
-/**
- * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK     0x00000F80
-
-/**
- * @brief   Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE   0x00000000
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- *          identifier and the involved physical registers.
- * @note    Don't use this array directly, use the appropriate wrapper macros
- *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
-  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
-  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
-  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
-  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
-  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
-  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
-  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}
-};
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DMA ISR redirector type.
- */
-typedef struct {
-  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
-  void                  *dma_param;     /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief   Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief   DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 0;
-  if (dma_isr_redir[0].dma_func)
-    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 4;
-  if (dma_isr_redir[1].dma_func)
-    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 8;
-  if (dma_isr_redir[2].dma_func)
-    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 12;
-  if (dma_isr_redir[3].dma_func)
-    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 16;
-  if (dma_isr_redir[4].dma_func)
-    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 20;
-  if (dma_isr_redir[5].dma_func)
-    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
-  uint32_t flags;
-
-  CH_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 24;
-  if (dma_isr_redir[6].dma_func)
-    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
-
-  CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
-  int i;
-
-  dma_streams_mask = 0;
-  for (i = 0; i < STM32_DMA_STREAMS; i++) {
-    _stm32_dma_streams[i].channel->CCR = 0;
-    dma_isr_redir[i].dma_func = NULL;
-  }
-  DMA1->IFCR = 0xFFFFFFFF;
-}
-
-/**
- * @brief   Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- *          The function also enables the IRQ vector associated to the stream
- *          and initializes its priority.
- * @pre     The stream must not be already in use or an error is returned.
- * @post    The stream is allocated and the default ISR handler redirected
- *          to the specified function.
- * @post    The stream ISR vector is enabled and its priority configured.
- * @post    The stream must be freed using @p dmaStreamRelease() before it can
- *          be reused with another peripheral.
- * @post    The stream is in its post-reset state.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] priority  IRQ priority mask for the DMA stream
- * @param[in] func      handling function pointer, can be @p NULL
- * @param[in] param     a parameter to be passed to the handling function
- * @return              The operation status.
- * @retval FALSE        no error, stream taken.
- * @retval TRUE         error, stream already taken.
- *
- * @special
- */
-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                         uint32_t priority,
-                         stm32_dmaisr_t func,
-                         void *param) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
-
-  /* Checks if the stream is already taken.*/
-  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
-    return TRUE;
-
-  /* Marks the stream as allocated.*/
-  dma_isr_redir[dmastp->selfindex].dma_func  = func;
-  dma_isr_redir[dmastp->selfindex].dma_param = param;
-  dma_streams_mask |= (1 << dmastp->selfindex);
-
-  /* Enabling DMA clocks required by the current streams set.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
-    rccEnableDMA1(FALSE);
-
-  /* Putting the stream in a safe state.*/
-  dmaStreamDisable(dmastp);
-  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
-
-  /* Enables the associated IRQ vector if a callback is defined.*/
-  if (func != NULL)
-    nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
-
-  return FALSE;
-}
-
-/**
- * @brief   Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- *          Trying to release a unallocated stream is an illegal operation
- *          and is trapped if assertions are enabled.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    The stream is again available.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
-  chDbgCheck(dmastp != NULL, "dmaStreamRelease");
-
-  /* Check if the streams is not taken.*/
-  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
-              "dmaStreamRelease(), #1", "not allocated");
-
-  /* Disables the associated IRQ vector.*/
-  nvicDisableVector(dmastp->vector);
-
-  /* Marks the stream as not allocated.*/
-  dma_streams_mask &= ~(1 << dmastp->selfindex);
-
-  /* Shutting down clocks that are no more required, if any.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
-    rccDisableDMA1(FALSE);
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h
deleted file mode 100644
index 2e3225ce9..000000000
--- a/os/hal/platforms/STM32L1xx/stm32_dma.h
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32L1xx/stm32_dma.h
- * @brief   DMA helper driver header.
- * @note    This file requires definitions from the ST header file stm32l1xx.h.
- * @note    This driver uses the new naming convention used for the STM32F2xx
- *          so the "DMA channels" are referred as "DMA streams".
- *
- * @addtogroup STM32L1xx_DMA
- * @{
- */
-
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Total number of DMA streams.
- * @note    This is the total number of streams among all the DMA units.
- */
-#define STM32_DMA_STREAMS           7
-
-/**
- * @brief   Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK          0x0F
-
-/**
- * @brief   Returns the channel associated to the specified stream.
- *
- * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
- * @param[in] c         a stream/channel association word, one channel per
- *                      nibble, not associated channels must be set to 0xF
- * @return              Always zero, in this platform there is no dynamic
- *                      association between streams and channels.
- */
-#define STM32_DMA_GETCHANNEL(n, c)  0
-
-/**
- * @brief   Checks if a DMA priority is within the valid range.
- * @param[in] prio      DMA priority
- *
- * @retval              The check result.
- * @retval FALSE        invalid DMA priority.
- * @retval TRUE         correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
-
-/**
- * @brief   Returns an unique numeric identifier for a DMA stream.
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              An unique numeric stream identifier.
- */
-#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1)
-
-/**
- * @brief   Returns a DMA stream identifier mask.
- *
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              A DMA stream identifier mask.
- */
-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
-  (1 << STM32_DMA_STREAM_ID(dma, stream))
-
-/**
- * @brief   Checks if a DMA stream unique identifier belongs to a mask.
- * @param[in] id        the stream numeric identifier
- * @param[in] mask      the stream numeric identifiers mask
- *
- * @retval              The check result.
- * @retval FALSE        id does not belong to the mask.
- * @retval TRUE         id belongs to the mask.
- */
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
-
-/**
- * @name    DMA streams identifiers
- * @{
- */
-/**
- * @brief   Returns a pointer to a stm32_dma_stream_t structure.
- *
- * @param[in] id        the stream numeric identifier
- * @return              A pointer to the stm32_dma_stream_t constant structure
- *                      associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
-#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
-#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
-/** @} */
-
-/**
- * @name    CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN             DMA_CCR1_EN
-#define STM32_DMA_CR_TEIE           DMA_CCR1_TEIE
-#define STM32_DMA_CR_HTIE           DMA_CCR1_HTIE
-#define STM32_DMA_CR_TCIE           DMA_CCR1_TCIE
-#define STM32_DMA_CR_DIR_MASK       (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM)
-#define STM32_DMA_CR_DIR_P2M        0
-#define STM32_DMA_CR_DIR_M2P        DMA_CCR1_DIR
-#define STM32_DMA_CR_DIR_M2M        DMA_CCR1_MEM2MEM
-#define STM32_DMA_CR_CIRC           DMA_CCR1_CIRC
-#define STM32_DMA_CR_PINC           DMA_CCR1_PINC
-#define STM32_DMA_CR_MINC           DMA_CCR1_MINC
-#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR1_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE     0
-#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR1_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR1_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR1_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE     0
-#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR1_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR1_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
-                                     STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK        DMA_CCR1_PL
-#define STM32_DMA_CR_PL(n)          ((n) << 12)
-/** @} */
-
-/**
- * @name    CR register constants only found in enhanced DMA
- * @{
- */
-#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
-/** @} */
-
-/**
- * @name    Status flags passed to the ISR callbacks
- * @{
- */
-#define STM32_DMA_ISR_FEIF          0
-#define STM32_DMA_ISR_DMEIF         0
-#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
-#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
-#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA stream descriptor structure.
- */
-typedef struct {
-  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
-  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
-  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
-                                             register.                      */
-  uint8_t               selfindex;      /**< @brief Index to self in array. */
-  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
-} stm32_dma_stream_t;
-
-/**
- * @brief   STM32 DMA ISR function type.
- *
- * @param[in] p         parameter for the registered function
- * @param[in] flags     pre-shifted content of the ISR register, the bits
- *                      are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Associates a peripheral data register to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CPAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) {                              \
-  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Associates a memory destination to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CMAR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) {                                 \
-  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Sets the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] size      value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) {                         \
-  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
-}
-
-/**
- * @brief   Returns the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @return              The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
-
-/**
- * @brief   Programs the stream mode settings.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) {                                    \
-  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
-}
-
-/**
- * @brief   DMA stream enable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) {                                           \
-  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
-}
-
-/**
- * @brief   DMA stream disable.
- * @details The function disables the specified stream and then clears any
- *          pending interrupt.
- * @note    This function can be invoked in both ISR or thread context.
- * @note    Interrupts enabling flags are set to zero after this call, see
- *          bug 3607518.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) {                                          \
-  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
-                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
-  dmaStreamClearInterrupt(dmastp);                                          \
-}
-
-/**
- * @brief   DMA stream interrupt sources clear.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) {                                   \
-  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
-}
-
-/**
- * @brief   Starts a memory to memory operation using the specified stream.
- * @note    The default transfer data mode is "byte to byte" but it can be
- *          changed by specifying extra options in the @p mode parameter.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register, this value
- *                      is implicitly ORed with:
- *                      - @p STM32_DMA_CR_MINC
- *                      - @p STM32_DMA_CR_PINC
- *                      - @p STM32_DMA_CR_DIR_M2M
- *                      - @p STM32_DMA_CR_EN
- *                      .
- * @param[in] src       source address
- * @param[in] dst       destination address
- * @param[in] n         number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
-  dmaStreamSetPeripheral(dmastp, src);                                      \
-  dmaStreamSetMemory0(dmastp, dst);                                         \
-  dmaStreamSetTransactionSize(dmastp, n);                                   \
-  dmaStreamSetMode(dmastp, (mode) |                                         \
-                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
-                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
-}
-
-/**
- * @brief   Polled wait for DMA transfer end.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) {                                         \
-  while ((dmastp)->channel->CNDTR > 0)                                      \
-    ;                                                                       \
-  dmaStreamDisable(dmastp);                                                 \
-}
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dmaInit(void);
-  bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                           uint32_t priority,
-                           stm32_dmaisr_t func,
-                           void *param);
-  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32L1xx/stm32_isr.h b/os/hal/platforms/STM32L1xx/stm32_isr.h
deleted file mode 100644
index d90d28c0b..000000000
--- a/os/hal/platforms/STM32L1xx/stm32_isr.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32L1xx/stm32_isr.h
- * @brief   ISR remapper driver header.
- *
- * @addtogroup STM32L1xx_ISR
- * @{
- */
-
-#ifndef _STM32_ISR_H_
-#define _STM32_ISR_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    ISR names and numbers remapping
- * @{
- */
-/*
- * TIM units.
- */
-#define STM32_TIM2_HANDLER          TIM2_IRQHandler
-#define STM32_TIM3_HANDLER          TIM3_IRQHandler
-#define STM32_TIM4_HANDLER          TIM4_IRQHandler
-#define STM32_TIM9_HANDLER          TIM9_IRQHandler
-
-#define STM32_TIM2_NUMBER           TIM2_IRQn
-#define STM32_TIM3_NUMBER           TIM3_IRQn
-#define STM32_TIM4_NUMBER           TIM4_IRQn
-#define STM32_TIM9_NUMBER           TIM9_IRQn
-
-/*
- * USART units.
- */
-#define STM32_USART1_HANDLER        USART1_IRQHandler
-#define STM32_USART2_HANDLER        USART2_IRQHandler
-#define STM32_USART3_HANDLER        USART3_IRQHandler
-
-#define STM32_USART1_NUMBER         USART1_IRQn
-#define STM32_USART2_NUMBER         USART2_IRQn
-#define STM32_USART3_NUMBER         USART3_IRQn
-
-/*
- * USB units.
- */
-#define STM32_USB1_HP_HANDLER       Vector8C
-#define STM32_USB1_LP_HANDLER       Vector90
-
-#define STM32_USB1_HP_NUMBER        USB_HP_IRQn
-#define STM32_USB1_LP_NUMBER        USB_LP_IRQn
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#endif /* _STM32_ISR_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h
deleted file mode 100644
index f938db6b1..000000000
--- a/os/hal/platforms/STM32L1xx/stm32l1xx.h
+++ /dev/null
@@ -1,6355 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx.h
-  * @author  MCD Application Team
-  * @version V1.1.1
-  * @date    09-March-2012
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx High-, Medium-density
-  *          and Medium-density Plus devices.
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral�s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral�s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_STDPERIPH_DRIVER"
-  *              - To change few application-specific parameters such as the HSE 
-  *                crystal frequency
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx
-  * @{
-  */
-    
-#ifndef __STM32L1XX_H
-#define __STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/* Uncomment the line below according to the target STM32L device used in your 
-   application 
-  */
-
-#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
-  /* #define STM32L1XX_MD  */   /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */
-  /* #define STM32L1XX_MDP */   /*!< STM32L1XX_MDP: STM32L Ultra Low Power Medium-density Plus devices */
-  #define STM32L1XX_HD    /*!< STM32L1XX_HD: STM32L Ultra Low Power High-density devices */
-#endif
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-
- - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and 
-   STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
- - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx 
-   microcontrollers where the Flash memory density is 384 Kbytes.
-  */
-
-#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
- #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
-#endif
-
-#if !defined  USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_STDPERIPH_DRIVER*/
-#endif
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application 
-   
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */
-#if !defined  (HSE_VALUE)
-#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-   Timeout value 
-   */
-#if !defined  (HSE_STARTUP_TIMEOUT)
-#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
-#endif
-
-/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-   Timeout value 
-   */
-#if !defined  (HSI_STARTUP_TIMEOUT)
-#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
-#endif
-
-#if !defined  (HSI_VALUE)
-#define HSI_VALUE  ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif
-
-#if !defined  (LSI_VALUE)
-#define LSI_VALUE  ((uint32_t)37000)    /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif
-
-#if !defined  (LSE_VALUE)
-#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif
-
-/**
- * @brief STM32L1xx Standard Peripheral Library version number V1.1.1
-   */
-#define __STM32L1XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L1XX_STDPERIPH_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
-#define __STM32L1XX_STDPERIPH_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
-#define __STM32L1XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32L1XX_STDPERIPH_VERSION       ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
-                                             |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
-                                             |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
-                                             |(__STM32L1XX_STDPERIPH_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-#define __CM3_REV                 0x200 /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1 /*!< STM32L provides MPU                          */
-#define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
- 
-/*!< Interrupt Number Definition */
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and Time Stamp through EXTI Line Interrupts      */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-#ifdef STM32L1XX_MD
-  TIM7_IRQn                   = 44      /*!< TIM7 global Interrupt                                   */
-#endif
-
-#ifdef STM32L1XX_MDP
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  /* CHIBIOS FIX */
-  TIM5_IRQn                   = 45,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 46,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 47,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 48,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 49,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 50,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 51,     /*!< DMA2 Channel 5 global Interrupt                         */
-  AES_IRQn                    = 52,     /*!< AES global Interrupt                                    */
-  COMP_ACQ_IRQn               = 53      /*!< Comparator Channel Acquisition global Interrupt         */
-#endif
-
-#ifdef STM32L1XX_HD
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  SDIO_IRQn                   = 45,     /*!< SDIO global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-#endif
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-/* CHIBIOS FIX */
-/*#include "system_stm32l1xx.h"*/
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/** 
-  * @brief  __RAM_FUNC definition
-  */ 
-#if defined ( __CC_ARM   )
-/* ARM Compiler
-   ------------
-   RAM functions are defined using the toolchain options. 
-   Functions that are executed in RAM should reside in a separate source 
-   module. Using the 'Options for File' dialog you can simply change the 
-   'Code / Const' area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 
-   'Options for Target' dialog. 
-*/
- #define __RAM_FUNC FLASH_Status 
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
-*/
- #define __RAM_FUNC __ramfunc FLASH_Status
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-   RAM functions are defined using a specific toolchain attribute 
-   "__attribute__((section(".data")))". 
-*/
- #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
-
-#elif defined   (  __TASKING__  )
-/* TASKING Compiler
-   ----------------
-   RAM functions are defined using a specific toolchain pragma. This pragma is 
-   defined in the stm32l1xx_flash_ramfunc.c 
-*/
- #define __RAM_FUNC  FLASH_Status
-
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< COMP comparator control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t   RESERVED0;        /*!< Reserved,                                    0x05                 */
-  uint16_t  RESERVED1;        /*!< Reserved,                                    0x06                 */
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!< EXTI interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!< EXTI event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!< EXTI rising edge trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!< EXTI software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!< EXTI pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;         /*!< Write protection register,                   Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    0x24                 */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x28 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x2C */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-  
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;             /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;             /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;             /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;             /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;           /*!< write protection register 10 11,        Address offset: 0x1C */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control/status register,                     Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];      /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];      /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;        
-
-/** 
-  * @brief General Purpose IO
-  */
-/* CHIBIOS FIX */
-#if 0
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint16_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  uint16_t RESERVED0;         /*!< Reserved,                                    0x06                      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint16_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  uint16_t RESERVED1;         /*!< Reserved,                                    0x12                      */
-  __IO uint16_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  uint16_t RESERVED2;         /*!< Reserved,                                    0x16                      */
-  __IO uint16_t BSRRL;        /*!< GPIO port bit set/reset low registerBSRR,    Address offset: 0x18      */
-  __IO uint16_t BSRRH;        /*!< GPIO port bit set/reset high registerBSRR,   Address offset: 0x1A      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,        Address offset: 0x20-0x24 */
-  __IO uint16_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-  uint16_t RESERVED3;         /*!< Reserved,                                    0x2A                      */
-} GPIO_TypeDef;
-#endif
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  uint16_t  RESERVED0;        /*!< Reserved,                                    0x02                 */
-  __IO uint16_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  uint16_t  RESERVED1;        /*!< Reserved,                                    0x06                 */
-  __IO uint16_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  uint16_t  RESERVED2;        /*!< Reserved,                                    0x0A                 */
-  __IO uint16_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  uint16_t  RESERVED3;        /*!< Reserved,                                    0x0E                 */
-  __IO uint16_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  uint16_t  RESERVED4;        /*!< Reserved,                                    0x12                 */
-  __IO uint16_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  uint16_t  RESERVED5;        /*!< Reserved,                                    0x16                 */
-  __IO uint16_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  uint16_t  RESERVED6;        /*!< Reserved,                                    0x1A                 */
-  __IO uint16_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  uint16_t  RESERVED7;        /*!< Reserved,                                    0x1E                 */
-  __IO uint16_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-  uint16_t  RESERVED8;        /*!< Reserved,                                    0x22                 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,           Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;       /*!< RI input capture register,             Address offset: 0x00 */
-  __IO uint32_t ASCR1;     /*!< RI analog switches control register,   Address offset: 0x04 */
-  __IO uint32_t ASCR2;     /*!< RI analog switch control register 2,   Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,       Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,       Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,       Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,       Address offset: 0x18 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
-  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
-  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
-  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
-  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
-  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
-  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
-  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
-  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint16_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  uint16_t      RESERVED0;    /*!< Reserved, 0x02                                            */
-  __IO uint16_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  uint16_t      RESERVED1;    /*!< Reserved, 0x06                                            */
-  __IO uint16_t SMCR;         /*!< TIM slave mode control register,     Address offset: 0x08 */
-  uint16_t      RESERVED2;    /*!< Reserved, 0x0A                                            */
-  __IO uint16_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  uint16_t      RESERVED3;    /*!< Reserved, 0x0E                                            */
-  __IO uint16_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  uint16_t      RESERVED4;    /*!< Reserved, 0x12                                            */
-  __IO uint16_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  uint16_t      RESERVED5;    /*!< Reserved, 0x16                                            */
-  __IO uint16_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  uint16_t      RESERVED6;    /*!< Reserved, 0x1A                                            */
-  __IO uint16_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  uint16_t      RESERVED7;    /*!< Reserved, 0x1E                                            */
-  __IO uint16_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  uint16_t      RESERVED8;    /*!< Reserved, 0x22                                            */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint16_t PSC;          /*!< TIM prescaler,                       Address offset: 0x28 */
-  uint16_t      RESERVED10;   /*!< Reserved, 0x2A                                            */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint16_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  uint16_t      RESERVED18;   /*!< Reserved, 0x4A                                            */ 
-  __IO uint16_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  uint16_t      RESERVED19;   /*!< Reserved, 0x4E                                            */ 
-  __IO uint16_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-  uint16_t      RESERVED20;   /*!< Reserved, 0x52                                            */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
-  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
-  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
-  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
-  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
-  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
-  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
-
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x2400)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x7C00)
-#define RI_BASE               (APB1PERIPH_BASE + 0x7C04)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7C5C)
-
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x0800)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x0C00)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x1000)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2700)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
-
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x1000)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x1400)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x1800)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x1C00)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x3800)
-
-
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FF80000)    /*!< FLASH Option Bytes base address */
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x6000)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001C)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006C)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080)
-
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x6400)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001C)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058)
-
-#define AES_BASE              ((uint32_t)0x50060000)
-
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
-
-#define DBGMCU_BASE           ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define COMP                ((COMP_TypeDef *) COMP_BASE)
-#define RI                  ((RI_TypeDef *) RI_BASE)
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-
-#define AES                 ((AES_TypeDef *) AES_BASE)
-
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!< Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!< End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!< Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!< Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!< Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!< Overrun flag */
-#define  ADC_SR_ADONS                        ((uint32_t)0x00000040)        /*!< ADC ON status */
-#define  ADC_SR_RCNR                         ((uint32_t)0x00000100)        /*!< Regular channel not ready flag */
-#define  ADC_SR_JCNR                         ((uint32_t)0x00000200)        /*!< Injected channel not ready flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
-
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
-
-#define  ADC_CR1_PDD                         ((uint32_t)0x00010000)        /*!< Power Down during Delay phase */
-#define  ADC_CR1_PDI                         ((uint32_t)0x00020000)        /*!< Power Down during Idle phase */
-
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
-
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!< RES[1:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
-
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)        /*!< Overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
-#define  ADC_CR2_CFG                         ((uint32_t)0x00000004)        /*!< ADC Configuration */
-
-#define  ADC_CR2_DELS                        ((uint32_t)0x00000070)        /*!< DELS[2:0] bits (Delay selection) */
-#define  ADC_CR2_DELS_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  ADC_CR2_DELS_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  ADC_CR2_DELS_2                      ((uint32_t)0x00000040)        /*!< Bit 2 */
-
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!< DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!< End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
-
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!< JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!< Start Conversion of injected channels */
-
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!< Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP20                     ((uint32_t)0x00000007)        /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
-#define  ADC_SMPR1_SMP20_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP20_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP20_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP21                     ((uint32_t)0x00000038)        /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
-#define  ADC_SMPR1_SMP21_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP21_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP21_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP22                     ((uint32_t)0x000001C0)        /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
-#define  ADC_SMPR1_SMP22_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP22_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP22_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP23                     ((uint32_t)0x00000E00)        /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
-#define  ADC_SMPR1_SMP23_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP23_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP23_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP24                     ((uint32_t)0x00007000)        /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
-#define  ADC_SMPR1_SMP24_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP24_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP24_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP25                     ((uint32_t)0x00038000)        /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
-#define  ADC_SMPR1_SMP25_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP25_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP25_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP26                     ((uint32_t)0x001C0000)        /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
-#define  ADC_SMPR1_SMP26_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP26_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP26_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP27                     ((uint32_t)0x00E00000)        /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
-#define  ADC_SMPR1_SMP27_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP27_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP27_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP28                     ((uint32_t)0x07000000)        /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
-#define  ADC_SMPR1_SMP28_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP28_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP28_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP29                     ((uint32_t)0x38000000)        /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
-#define  ADC_SMPR1_SMP29_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP29_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP29_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR2_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR2_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR2_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR2_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR2_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR2_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR2_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP18                     ((uint32_t)0x07000000)        /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR2_SMP18_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP18_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP18_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP19                     ((uint32_t)0x38000000)        /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
-#define  ADC_SMPR2_SMP19_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP19_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP19_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define  ADC_SMPR3_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR3_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
- 
-#define  ADC_SMPR3_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR3_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR3_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR3_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR3_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR3_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR3_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR3_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR3_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR3_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)         /*!< Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  ADC_SQR1_SQ28                       ((uint32_t)0x000F8000)        /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
-#define  ADC_SQR1_SQ28_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ28_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ28_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ28_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ28_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ27                       ((uint32_t)0x00007C00)        /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
-#define  ADC_SQR1_SQ27_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ27_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ27_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ27_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ27_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ26                       ((uint32_t)0x000003E0)        /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
-#define  ADC_SQR1_SQ26_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ26_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ26_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ26_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ26_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ25                       ((uint32_t)0x0000001F)        /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
-#define  ADC_SQR1_SQ25_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ25_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ25_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ25_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ25_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ19                       ((uint32_t)0x0000001F)        /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
-#define  ADC_SQR2_SQ19_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ19_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ19_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ19_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ19_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ20                       ((uint32_t)0x000003E0)        /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
-#define  ADC_SQR2_SQ20_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ20_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ20_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ20_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ20_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ21                       ((uint32_t)0x00007C00)        /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
-#define  ADC_SQR2_SQ21_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ21_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ21_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ21_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ21_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ22                       ((uint32_t)0x000F8000)        /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
-#define  ADC_SQR2_SQ22_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ22_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ22_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ22_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ22_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ23                       ((uint32_t)0x01F00000)        /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
-#define  ADC_SQR2_SQ23_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ23_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ23_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ23_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ23_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ24                       ((uint32_t)0x3E000000)        /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
-#define  ADC_SQR2_SQ24_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ24_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ24_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ24_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ24_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR3_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR3_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR3_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR3_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ17                       ((uint32_t)0x01F00000)        /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
-#define  ADC_SQR3_SQ17_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ17_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ17_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ17_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ17_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ18                       ((uint32_t)0x3E000000)        /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
-#define  ADC_SQR3_SQ18_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ18_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ18_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ18_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ18_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define  ADC_SQR4_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR4_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR4_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR4_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ10                        ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR4_SQ10_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ10_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ10_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ10_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ10_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ11                        ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR4_SQ11_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ11_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ11_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ11_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ11_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ12                        ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR4_SQ12_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ12_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ12_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ12_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ12_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define  ADC_SQR5_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR5_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR5_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR5_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR5_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR5_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR5_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define  ADC_SMPR3_SMP30                     ((uint32_t)0x00000007)        /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
-#define  ADC_SMPR3_SMP30_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP30_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP30_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
- 
-#define  ADC_SMPR3_SMP31                     ((uint32_t)0x00000038)        /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
-#define  ADC_SMPR3_SMP31_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP31_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP31_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!< ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!< ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!< ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!< ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!< ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020)        /*!< ADC1 overrun  flag */
-#define  ADC_CSR_ADONS1                      ((uint32_t)0x00000040)        /*!< ADON status of ADC1 */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!< ADC prescaler*/
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */ 
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define  AES_CR_EN                           ((uint32_t)0x00000001)        /*!< AES Enable */
-#define  AES_CR_DATATYPE                     ((uint32_t)0x00000006)        /*!< Data type selection */
-#define  AES_CR_DATATYPE_0                   ((uint32_t)0x00000002)        /*!< Bit 0 */
-#define  AES_CR_DATATYPE_1                   ((uint32_t)0x00000004)        /*!< Bit 1 */
-
-#define  AES_CR_MODE                         ((uint32_t)0x00000018)        /*!< AES Mode Of Operation */
-#define  AES_CR_MODE_0                       ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  AES_CR_MODE_1                       ((uint32_t)0x00000010)        /*!< Bit 1 */
-
-#define  AES_CR_CHMOD                        ((uint32_t)0x00000060)        /*!< AES Chaining Mode */
-#define  AES_CR_CHMOD_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  AES_CR_CHMOD_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-
-#define  AES_CR_CCFC                         ((uint32_t)0x00000080)        /*!< Computation Complete Flag Clear */
-#define  AES_CR_ERRC                         ((uint32_t)0x00000100)        /*!< Error Clear */
-#define  AES_CR_CCIE                         ((uint32_t)0x00000200)        /*!< Computation Complete Interrupt Enable */
-#define  AES_CR_ERRIE                        ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
-#define  AES_CR_DMAINEN                      ((uint32_t)0x00000800)        /*!< DMA ENable managing the data input phase */
-#define  AES_CR_DMAOUTEN                     ((uint32_t)0x00001000)        /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define  AES_SR_CCF                          ((uint32_t)0x00000001)        /*!< Computation Complete Flag */
-#define  AES_SR_RDERR                        ((uint32_t)0x00000002)        /*!< Read Error Flag */
-#define  AES_SR_WRERR                        ((uint32_t)0x00000004)        /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define  AES_DINR                            ((uint32_t)0x0000FFFF)        /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define  AES_DOUTR                           ((uint32_t)0x0000FFFF)        /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define  AES_KEYR0                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define  AES_KEYR1                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define  AES_KEYR2                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define  AES_KEYR3                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define  AES_IVR0                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define  AES_IVR1                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define  AES_IVR2                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define  AES_IVR3                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define  COMP_CSR_10KPU                      ((uint32_t)0x00000001)        /*!< 10K pull-up resistor */
-#define  COMP_CSR_400KPU                     ((uint32_t)0x00000002)        /*!< 400K pull-up resistor */
-#define  COMP_CSR_10KPD                      ((uint32_t)0x00000004)        /*!< 10K pull-down resistor */
-#define  COMP_CSR_400KPD                     ((uint32_t)0x00000008)        /*!< 400K pull-down resistor */
-
-#define  COMP_CSR_CMP1EN                     ((uint32_t)0x00000010)        /*!< Comparator 1 enable */
-#define  COMP_CSR_SW1                        ((uint32_t)0x00000020)        /*!< SW1 analog switch enable */
-#define  COMP_CSR_CMP1OUT                    ((uint32_t)0x00000080)        /*!< Comparator 1 output */
-
-#define  COMP_CSR_SPEED                      ((uint32_t)0x00001000)        /*!< Comparator 2 speed */
-#define  COMP_CSR_CMP2OUT                    ((uint32_t)0x00002000)        /*!< Comparator 2 ouput */
-
-#define  COMP_CSR_VREFOUTEN                  ((uint32_t)0x00010000)        /*!< Comparator Vref Enable */
-#define  COMP_CSR_WNDWE                      ((uint32_t)0x00020000)        /*!< Window mode enable */
-
-#define  COMP_CSR_INSEL                      ((uint32_t)0x001C0000)        /*!< INSEL[2:0] Inversion input Selection */
-#define  COMP_CSR_INSEL_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  COMP_CSR_INSEL_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  COMP_CSR_INSEL_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  COMP_CSR_OUTSEL                     ((uint32_t)0x00E00000)        /*!< OUTSEL[2:0] comparator 2 output redirection */
-#define  COMP_CSR_OUTSEL_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  COMP_CSR_OUTSEL_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  COMP_CSR_OUTSEL_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  COMP_CSR_FCH3                       ((uint32_t)0x04000000)        /*!< Bit 26 */
-#define  COMP_CSR_FCH8                       ((uint32_t)0x08000000)        /*!< Bit 27 */
-#define  COMP_CSR_RCH13                      ((uint32_t)0x10000000)        /*!< Bit 28 */
-
-#define  COMP_CSR_CAIE                       ((uint32_t)0x20000000)        /*!< Bit 29 */
-#define  COMP_CSR_CAIF                       ((uint32_t)0x40000000)        /*!< Bit 30 */
-#define  COMP_CSR_TSUSP                      ((uint32_t)0x80000000)        /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD                     ((uint32_t)0x00000001)        /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1                     ((uint32_t)0x00000002)        /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1                     ((uint32_t)0x00000004)        /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1                     ((uint32_t)0x00000008)        /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1                     ((uint32_t)0x00000010)        /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L                  ((uint32_t)0x00000020)        /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H                  ((uint32_t)0x00000040)        /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM                    ((uint32_t)0x00000080)        /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD                     ((uint32_t)0x00000100)        /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2                     ((uint32_t)0x00000200)        /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2                     ((uint32_t)0x00000400)        /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2                     ((uint32_t)0x00000800)        /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2                     ((uint32_t)0x00001000)        /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L                  ((uint32_t)0x00002000)        /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H                  ((uint32_t)0x00004000)        /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM                    ((uint32_t)0x00008000)        /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_OPA3PD                     ((uint32_t)0x00010000)        /*!< OPAMP3 disable */
-#define OPAMP_CSR_S3SEL3                     ((uint32_t)0x00020000)        /*!< Switch 3 for OPAMP3 Enable */
-#define OPAMP_CSR_S4SEL3                     ((uint32_t)0x00040000)        /*!< Switch 4 for OPAMP3 Enable */
-#define OPAMP_CSR_S5SEL3                     ((uint32_t)0x00080000)        /*!< Switch 5 for OPAMP3 Enable */
-#define OPAMP_CSR_S6SEL3                     ((uint32_t)0x00100000)        /*!< Switch 6 for OPAMP3 Enable */
-#define OPAMP_CSR_OPA3CAL_L                  ((uint32_t)0x00200000)        /*!< OPAMP3 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA3CAL_H                  ((uint32_t)0x00400000)        /*!< OPAMP3 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA3LPM                    ((uint32_t)0x00800000)        /*!< OPAMP3 Low power enable */
-#define OPAMP_CSR_ANAWSEL1                   ((uint32_t)0x01000000)        /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2                   ((uint32_t)0x02000000)        /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_ANAWSEL3                   ((uint32_t)0x04000000)        /*!< Switch ANA Enable for OPAMP3 */
-#define OPAMP_CSR_S7SEL2                     ((uint32_t)0x08000000)        /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE                  ((uint32_t)0x10000000)        /*!< Power range selection */
-#define OPAMP_CSR_OPA1CALOUT                 ((uint32_t)0x20000000)        /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT                 ((uint32_t)0x40000000)        /*!< OPAMP2 calibration output */
-#define OPAMP_CSR_OPA3CALOUT                 ((uint32_t)0x80000000)        /*!< OPAMP3 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM        ((uint32_t)0x000003FF)        /*!< Offset trim for OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM        ((uint32_t)0x000FFC00)        /*!< Offset trim for OPAMP2 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM        ((uint32_t)0x3FF00000)        /*!< Offset trim for OPAMP2 */
-#define OPAMP_OTR_OT_USER                    ((uint32_t)0x80000000)        /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP  ((uint32_t)0x000003FF)        /*!< Offset trim in low power for OPAMP1 */
-#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP  ((uint32_t)0x000FFC00)        /*!< Offset trim in low power for OPAMP2 */
-#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP  ((uint32_t)0x3FF00000)        /*!< Offset trim in low power for OPAMP3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF)        /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFF)               /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x00000001)        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun interrupt enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP             ((uint32_t)0x00000001)   /*!< TIM2 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP             ((uint32_t)0x00000002)   /*!< TIM3 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP             ((uint32_t)0x00000004)   /*!< TIM4 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP             ((uint32_t)0x00000008)   /*!< TIM5 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP             ((uint32_t)0x00000010)   /*!< TIM6 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP             ((uint32_t)0x00000020)   /*!< TIM7 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP              ((uint32_t)0x00000400)   /*!< RTC Counter stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP             ((uint32_t)0x00000800)   /*!< Debug Window Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP             ((uint32_t)0x00001000)   /*!< Debug Independent Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< SMBUS timeout mode stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)   /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP             ((uint32_t)0x00000004)   /*!< TIM9 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP            ((uint32_t)0x00000008)   /*!< TIM10 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP            ((uint32_t)0x00000010)   /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
-#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clearr */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
-#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR1 register  *******************/
-#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
-#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
-#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*******************  Bit definition for DMA_CCR2 register  *******************/
-#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< ransfer complete interrupt enable */
-#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*******************  Bit definition for DMA_CCR3 register  *******************/
-#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*!<******************  Bit definition for DMA_CCR4 register  *******************/
-#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/******************  Bit definition for DMA_CCR5 register  *******************/
-#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
-
-/*******************  Bit definition for DMA_CCR6 register  *******************/
-#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
-
-/*******************  Bit definition for DMA_CCR7 register  *******************/
-#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
-#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
-#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
-#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
-#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
-
-#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
-
-#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
-
-#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
-#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
-#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< Latency */
-#define  FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_ACC64                     ((uint32_t)0x00000004)        /*!< Access 64 bits */
-#define  FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */
-#define  FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */
-#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */
-#define FLASH_PECR_FTDW                      ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */
-#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK                ((uint32_t)0x00008000)        /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define  FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define  FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define  FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define  FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/
-#define  FLASH_SR_ENHV                       ((uint32_t)0x00000004)        /*!< End of high voltage */
-#define  FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */
-
-#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protected error */
-#define  FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */
-#define  FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */
-#define  FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option validity error */
-#define  FLASH_SR_OPTVERRUSR                 ((uint32_t)0x00001000)        /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_RDPRT                     ((uint16_t)0x000000AA)        /*!< Read Protection */
-#define  FLASH_OBR_BOR_LEV                   ((uint16_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define  FLASH_OBR_USER                      ((uint32_t)0x00700000)        /*!< User Option Bytes */
-#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00100000)        /*!< IWDG_SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00200000)        /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00400000)        /*!< nRST_STDBY */
-#define  FLASH_OBR_nRST_BFB2                 ((uint32_t)0x00800000)        /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
-
-/******************  Bit definition for FLASH_WRPR1 register  *****************/
-#define  FLASH_WRPR1_WRP                     ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
-
-/******************  Bit definition for FLASH_WRPR2 register  *****************/
-#define  FLASH_WRPR2_WRP                     ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
-#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
-#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
-#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
-#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
-
-#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
-#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
-#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
-
-#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
-#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
-#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
-#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
-#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
-#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
-#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
-#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
-#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
-#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
-#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
-#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
-#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
-#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      General Purpose IOs (GPIO)                            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/  
-#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
-#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
-#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
-#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
-#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
-#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
-#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
-#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
-#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
-#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
-#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
-#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
-#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
-#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
-#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
-#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_OTYPER register  ****************/   
-#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
-
-/*******************  Bit definition for GPIO_OSPEEDR register  ***************/  
-#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_PUPDR register  *****************/  
-#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
-#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
-#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
-#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
-#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
-#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
-#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
-#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
-#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
-#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
-#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
-#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
-#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
-#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
-#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
-#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
-#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
-#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
-#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
-#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
-#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
-#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
-#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
-#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
-#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
-#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
-#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
-#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
-#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
-#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
-#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
-#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
-
-/*******************  Bit definition for GPIO_BSRR register  ******************/  
-#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_LCKR register  ******************/
-#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
-
-/*******************  Bit definition for GPIO_AFRL register  ******************/
-#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
-
-/*******************  Bit definition for GPIO_AFRH register  ******************/
-#define GPIO_AFRH_AFRH8            ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFRH9            ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFRH10           ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFRH11           ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFRH12           ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFRH13           ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFRH14           ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFRH15           ((uint32_t)0xF0000000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
-#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
-#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
-#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
-#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
-#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
-#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
-#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
-#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
-#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
-#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
-#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
-#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
-
-#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
-#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
-#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
-#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
-
-#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
-#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
-#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
-#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
-#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
-#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
-#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
-#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
-#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
-#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
-#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
-#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
-#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
-#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
-#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
-#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
-#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
-#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
-#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
-#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */
-#define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */
-
-#define LCD_CR_MUX_SEG             ((uint32_t)0x00000080)     /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */
-#define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */
-#define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */
-
-#define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */
-#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */
-#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */
-
-#define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */
-#define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */
-#define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */
-#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */
-
-#define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */
-#define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */
-#define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
-#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
-#define  PWR_CR_ULP                          ((uint16_t)0x0200)     /*!< Ultra Low Power mode */
-#define  PWR_CR_FWU                          ((uint16_t)0x0400)     /*!< Fast wakeup */
-
-#define  PWR_CR_VOS                          ((uint16_t)0x1800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define  PWR_CR_VOS_0                        ((uint16_t)0x0800)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint16_t)0x1000)     /*!< Bit 1 */
-#define  PWR_CR_LPRUN                        ((uint16_t)0x4000)     /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
-#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
-#define  PWR_CSR_VOSF                        ((uint16_t)0x0010)     /*!< Voltage Scaling select flag */
-#define  PWR_CSR_REGLPF                      ((uint16_t)0x0020)     /*!< Regulator LP flag */
-
-#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
-#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
-#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
-
-#define  RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */
-#define  RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */
-
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-#define  RCC_CR_CSSON                        ((uint32_t)0x10000000)        /*!< Clock Security System enable */
-
-#define  RCC_CR_RTCPRE                       ((uint32_t)0x60000000)        /*!< RTC/LCD Prescaler */
-#define  RCC_CR_RTCPRE_0                     ((uint32_t)0x20000000)        /*!< Bit0 */
-#define  RCC_CR_RTCPRE_1                     ((uint32_t)0x40000000)        /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */
-#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */
-
-#define  RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */
-#define  RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define  RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define  RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define  RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */
-#define  RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */
-#define  RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */
-#define  RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */
-#define  RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */
-#define  RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-/*!< SW configuration */
-#define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */
-
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */
-
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */
-#define  RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */
-
-
-#define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */
-#define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */
-#define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */
-#define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */
-#define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */
-#define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */
-#define  RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */
-#define  RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */
-#define  RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define  RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define  RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */
-#define  RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */
-
-
-/*!< PLLDIV configuration */
-#define  RCC_CFGR_PLLDIV1                    ((uint32_t)0x00000000)        /*!< PLL clock output = CKVCO / 1 */
-#define  RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */
-#define  RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */
-#define  RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */
-
-
-#define  RCC_CFGR_MCOSEL                     ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define  RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-/*!< MCO configuration */
-#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected */
-#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */
-#define  RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */
-#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */
-#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */
-#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */
-#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */
-
-#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000)        /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define  RCC_CFGR_MCOPRE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCOPRE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCOPRE_2                   ((uint32_t)0x40000000)        /*!< Bit 2 */
-
-/*!< MCO Prescaler configuration */
-#define  RCC_CFGR_MCO_DIV1                   ((uint32_t)0x00000000)        /*!< MCO Clock divided by 1 */
-#define  RCC_CFGR_MCO_DIV2                   ((uint32_t)0x10000000)        /*!< MCO Clock divided by 2 */
-#define  RCC_CFGR_MCO_DIV4                   ((uint32_t)0x20000000)        /*!< MCO Clock divided by 4 */
-#define  RCC_CFGR_MCO_DIV8                   ((uint32_t)0x30000000)        /*!< MCO Clock divided by 8 */
-#define  RCC_CFGR_MCO_DIV16                  ((uint32_t)0x40000000)        /*!< MCO Clock divided by 16 */
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_MSIRDYF                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */
-#define  RCC_CIR_LSECSS                      ((uint32_t)0x00000040)        /*!< LSE CSS Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_MSIRDYIE                    ((uint32_t)0x00002000)        /*!< MSI Ready Interrupt Enable */
-#define  RCC_CIR_LSECSSIE                    ((uint32_t)0x00004000)        /*!< LSE CSS Interrupt Enable */
-
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_MSIRDYC                     ((uint32_t)0x00200000)        /*!< MSI Ready Interrupt Clear */
-#define  RCC_CIR_LSECSSC                     ((uint32_t)0x00400000)        /*!< LSE CSS Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */
-#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */
-#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */
-#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */
-#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00000010)        /*!< GPIO port E reset */
-#define  RCC_AHBRSTR_GPIOHRST                ((uint32_t)0x00000020)        /*!< GPIO port H reset */
-#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00000040)        /*!< GPIO port F reset */
-#define  RCC_AHBRSTR_GPIOGRST                ((uint32_t)0x00000080)        /*!< GPIO port G reset */
-#define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */
-#define  RCC_AHBRSTR_FLITFRST                ((uint32_t)0x00008000)        /*!< FLITF reset */
-#define  RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x01000000)        /*!< DMA1 reset */
-#define  RCC_AHBRSTR_DMA2RST                 ((uint32_t)0x02000000)        /*!< DMA2 reset */
-#define  RCC_AHBRSTR_AESRST                  ((uint32_t)0x08000000)        /*!< AES reset */
-#define  RCC_AHBRSTR_FSMCRST                 ((uint32_t)0x40000000)        /*!< FSMC reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< System Configuration SYSCFG reset */
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00000004)        /*!< TIM9 reset */
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00000008)        /*!< TIM10 reset */
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00000010)        /*!< TIM11 reset */
-#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
-#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)        /*!< SDIO reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
-#define  RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI 2 reset */
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
-#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
-#define  RCC_APB1RSTR_COMPRST                ((uint32_t)0x80000000)        /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */
-#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */
-#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */
-#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */
-#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00000010)        /*!< GPIO port E clock enable */
-#define  RCC_AHBENR_GPIOHEN                  ((uint32_t)0x00000020)        /*!< GPIO port H clock enable */
-#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00000040)        /*!< GPIO port F clock enable */
-#define  RCC_AHBENR_GPIOGEN                  ((uint32_t)0x00000080)        /*!< GPIO port G clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00008000)        /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x01000000)        /*!< DMA1 clock enable */
-#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x02000000)        /*!< DMA2 clock enable */
-#define  RCC_AHBENR_AESEN                    ((uint32_t)0x08000000)        /*!< AES clock enable */
-#define  RCC_AHBENR_FSMCEN                   ((uint32_t)0x40000000)        /*!< FSMC clock enable */
-
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enable */
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00000004)         /*!< TIM9 interface clock enable */
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00000008)         /*!< TIM10 interface clock enable */
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enable */
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC1 clock enable */
-#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)         /*!< SDIO clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI1 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
-
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
-#define  RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
-#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
-#define  RCC_APB1ENR_COMPEN                  ((uint32_t)0x80000000)        /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define  RCC_AHBLPENR_GPIOALPEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOBLPEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOCLPEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIODLPEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOELPEN              ((uint32_t)0x00000010)        /*!< GPIO port E clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOHLPEN              ((uint32_t)0x00000020)        /*!< GPIO port H clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOFLPEN              ((uint32_t)0x00000040)        /*!< GPIO port F clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOGLPEN              ((uint32_t)0x00000080)        /*!< GPIO port G clock enabled in sleep mode */
-#define  RCC_AHBLPENR_CRCLPEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */
-#define  RCC_AHBLPENR_FLITFLPEN              ((uint32_t)0x00008000)        /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define  RCC_AHBLPENR_SRAMLPEN               ((uint32_t)0x00010000)        /*!< SRAM clock enabled in sleep mode */
-#define  RCC_AHBLPENR_DMA1LPEN               ((uint32_t)0x01000000)        /*!< DMA1 clock enabled in sleep mode */
-#define  RCC_AHBLPENR_DMA2LPEN               ((uint32_t)0x02000000)        /*!< DMA2 clock enabled in sleep mode */
-#define  RCC_AHBLPENR_AESLPEN                ((uint32_t)0x08000000)        /*!< AES clock enabled in sleep mode */
-#define  RCC_AHBLPENR_FSMCLPEN               ((uint32_t)0x40000000)        /*!< FSMC clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00000004)         /*!< TIM9 interface clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00000008)         /*!< TIM10 interface clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enabled in sleep mode */
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000200)         /*!< ADC1 clock enabled in sleep mode */
-#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)         /*!< SDIO clock enabled in sleep mode */
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)         /*!< SPI1 clock enabled in sleep mode */
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00004000)         /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)        /*!< Timer 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)        /*!< Timer 4 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)        /*!< Timer 5 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)        /*!< Timer 7 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_LCDLPEN               ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)        /*!< SPI 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)        /*!< SPI 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)        /*!< USART 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)        /*!< USART 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)        /*!< UART 4 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)        /*!< UART 5 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)        /*!< I2C 1 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)        /*!< I2C 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USBLPEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)        /*!< Power interface clock enabled in sleep mode */
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)        /*!< DAC interface clock enabled in sleep mode */
-#define  RCC_APB1LPENR_COMPLPEN              ((uint32_t)0x80000000)        /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define  RCC_CSR_LSION                      ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                     ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-
-#define  RCC_CSR_LSEON                      ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */
-#define  RCC_CSR_LSERDY                     ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */
-#define  RCC_CSR_LSEBYP                     ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */
-#define  RCC_CSR_LSECSSON                   ((uint32_t)0x00000800)        /*!< External Low Speed oscillator CSS Enable */
-#define  RCC_CSR_LSECSSD                    ((uint32_t)0x00001000)        /*!< External Low Speed oscillator CSS Detected */
-
-#define  RCC_CSR_RTCSEL                     ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_CSR_RTCSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  RCC_CSR_RTCSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define  RCC_CSR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CSR_RTCSEL_LSE                 ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_CSR_RTCSEL_LSI                 ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_CSR_RTCSEL_HSE                 ((uint32_t)0x00030000)        /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define  RCC_CSR_RTCEN                      ((uint32_t)0x00400000)        /*!< RTC clock enable */
-#define  RCC_CSR_RTCRST                     ((uint32_t)0x00800000)        /*!< RTC reset  */
- 
-#define  RCC_CSR_RMVF                       ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_OBLRSTF                    ((uint32_t)0x02000000)        /*!< Option Bytes Loader reset flag */
-#define  RCC_CSR_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                    ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                    ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                   ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
-#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
-#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
-#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
-#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
-#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
-
-#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
-#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
-
-#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
-#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
-
-#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
-#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
-
-#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
-#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
-#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
-#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
-#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
-#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
-#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
-#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
-#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
-
-#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
-#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
-#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
-#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
-
-#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
-#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
-#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
-#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
-#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
-#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
-#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
-#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
-#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
-#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
-#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
-#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
-#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
-#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
-#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
-#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
-#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
-#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
-#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
-#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
-#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
-#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
-#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
-#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
-#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
-#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
-#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
-#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
-#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
-#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
-#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
-#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
-#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
-#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
-#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
-#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
-#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
-#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
-#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
-#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
-#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
-#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
-#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
-#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
-#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
-#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
-#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
-#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
-#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
-#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
-#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
-#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
-#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
-#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
-#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
-#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
-
-#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
-#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
-#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
-#define  SPI_CR2_FRF                         ((uint8_t)0x08)               /*!< Frame format */
-#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
-
-#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
-
-#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!< Bit 0 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!< Bit 1 */
-#define SYSCFG_MEMRMP_BOOT_MODE         ((uint32_t)0x00000300) /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       ((uint32_t)0x00000200) /*!< Bit 1 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU               ((uint32_t)0x00000001) /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0005) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0006) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0007) /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0050) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0060) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0070) /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0500) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0600) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0700) /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x3000) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x4000) /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0006) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0007) /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0060) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0070) /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0600) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0700) /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x6000) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x7000) /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0006) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0007) /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0060) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0070) /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0600) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0700) /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x6000) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x7000) /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0006) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0007) /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0060) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0070) /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0600) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0700) /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x6000) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x7000) /*!< PG[15] pin */
- 
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define  RI_ICR_IC1Z                    ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */
-#define  RI_ICR_IC1Z_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ICR_IC1Z_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ICR_IC1Z_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ICR_IC1Z_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define  RI_ICR_IC2Z                    ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
-#define  RI_ICR_IC2Z_0                  ((uint32_t)0x00000010) /*!< Bit 0 */
-#define  RI_ICR_IC2Z_1                  ((uint32_t)0x00000020) /*!< Bit 1 */
-#define  RI_ICR_IC2Z_2                  ((uint32_t)0x00000040) /*!< Bit 2 */
-#define  RI_ICR_IC2Z_3                  ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define  RI_ICR_IC3Z                    ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */
-#define  RI_ICR_IC3Z_0                  ((uint32_t)0x00000100) /*!< Bit 0 */
-#define  RI_ICR_IC3Z_1                  ((uint32_t)0x00000200) /*!< Bit 1 */
-#define  RI_ICR_IC3Z_2                  ((uint32_t)0x00000400) /*!< Bit 2 */
-#define  RI_ICR_IC3Z_3                  ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define  RI_ICR_IC4Z                    ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */
-#define  RI_ICR_IC4Z_0                  ((uint32_t)0x00001000) /*!< Bit 0 */
-#define  RI_ICR_IC4Z_1                  ((uint32_t)0x00002000) /*!< Bit 1 */
-#define  RI_ICR_IC4Z_2                  ((uint32_t)0x00004000) /*!< Bit 2 */
-#define  RI_ICR_IC4Z_3                  ((uint32_t)0x00008000) /*!< Bit 3 */
-
-#define  RI_ICR_TIM                     ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
-#define  RI_ICR_TIM_0                   ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_ICR_TIM_1                   ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define  RI_ICR_IC1                     ((uint32_t)0x00040000) /*!< Input capture 1 */
-#define  RI_ICR_IC2                     ((uint32_t)0x00080000) /*!< Input capture 2 */
-#define  RI_ICR_IC3                     ((uint32_t)0x00100000) /*!< Input capture 3 */
-#define  RI_ICR_IC4                     ((uint32_t)0x00200000) /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define  RI_ASCR1_CH                    ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define  RI_ASCR1_CH_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASCR1_CH_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASCR1_CH_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASCR1_CH_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASCR1_CH_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASCR1_CH_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASCR1_CH_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASCR1_CH_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASCR1_CH_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASCR1_CH_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASCR1_CH_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASCR1_CH_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASCR1_CH_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASCR1_CH_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASCR1_CH_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASCR1_CH_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-#define  RI_ASCR1_CH_31                 ((uint32_t)0x00010000) /*!< Bit 16 */
-#define  RI_ASCR1_CH_18                 ((uint32_t)0x00040000) /*!< Bit 18 */
-#define  RI_ASCR1_CH_19                 ((uint32_t)0x00080000) /*!< Bit 19 */
-#define  RI_ASCR1_CH_20                 ((uint32_t)0x00100000) /*!< Bit 20 */
-#define  RI_ASCR1_CH_21                 ((uint32_t)0x00200000) /*!< Bit 21 */
-#define  RI_ASCR1_CH_22                 ((uint32_t)0x00400000) /*!< Bit 22 */
-#define  RI_ASCR1_CH_23                 ((uint32_t)0x00800000) /*!< Bit 23 */
-#define  RI_ASCR1_CH_24                 ((uint32_t)0x01000000) /*!< Bit 24 */
-#define  RI_ASCR1_CH_25                 ((uint32_t)0x02000000) /*!< Bit 25 */
-#define  RI_ASCR1_VCOMP                 ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
-#define  RI_ASCR1_CH_27                 ((uint32_t)0x00400000) /*!< Bit 27 */
-#define  RI_ASCR1_CH_28                 ((uint32_t)0x00800000) /*!< Bit 28 */
-#define  RI_ASCR1_CH_29                 ((uint32_t)0x01000000) /*!< Bit 29 */
-#define  RI_ASCR1_CH_30                 ((uint32_t)0x02000000) /*!< Bit 30 */
-#define  RI_ASCR1_SCM                   ((uint32_t)0x80000000) /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define  RI_ASCR2_GR10_1                ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
-#define  RI_ASCR2_GR10_2                ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
-#define  RI_ASCR2_GR10_3                ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
-#define  RI_ASCR2_GR10_4                ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
-#define  RI_ASCR2_GR6_1                 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
-#define  RI_ASCR2_GR6_2                 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
-#define  RI_ASCR2_GR5_1                 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
-#define  RI_ASCR2_GR5_2                 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
-#define  RI_ASCR2_GR5_3                 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
-#define  RI_ASCR2_GR4_1                 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
-#define  RI_ASCR2_GR4_2                 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
-#define  RI_ASCR2_GR4_3                 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
-#define  RI_ASCR2_GR4_4                 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
-#define  RI_ASCR2_CH0b                  ((uint32_t)0x00010000) /*!< CH0b selection bit */
-#define  RI_ASCR2_CH1b                  ((uint32_t)0x00020000) /*!< CH1b selection bit */
-#define  RI_ASCR2_CH2b                  ((uint32_t)0x00040000) /*!< CH2b selection bit */
-#define  RI_ASCR2_CH3b                  ((uint32_t)0x00080000) /*!< CH3b selection bit */
-#define  RI_ASCR2_CH6b                  ((uint32_t)0x00100000) /*!< CH6b selection bit */
-#define  RI_ASCR2_CH7b                  ((uint32_t)0x00200000) /*!< CH7b selection bit */
-#define  RI_ASCR2_CH8b                  ((uint32_t)0x00400000) /*!< CH8b selection bit */
-#define  RI_ASCR2_CH9b                  ((uint32_t)0x00800000) /*!< CH9b selection bit */
-#define  RI_ASCR2_CH10b                 ((uint32_t)0x01000000) /*!< CH10b selection bit */
-#define  RI_ASCR2_CH11b                 ((uint32_t)0x02000000) /*!< CH11b selection bit */
-#define  RI_ASCR2_CH12b                 ((uint32_t)0x04000000) /*!< CH12b selection bit */
-#define  RI_ASCR2_GR6_3                 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
-#define  RI_ASCR2_GR6_4                 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
-#define  RI_ASCR2_GR5_4                 ((uint32_t)0x20000000) /*!< GR5-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define  RI_HYSCR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
-#define  RI_HYSCR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define  RI_HYSCR1_PB                   ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
-#define  RI_HYSCR1_PB_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR1_PB_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR1_PB_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR1_PB_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR1_PB_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR1_PB_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR1_PB_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR1_PB_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR1_PB_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR1_PB_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR1_PB_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR1_PB_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR1_PB_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR1_PB_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR1_PB_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR1_PB_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define  RI_HYSCR2_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
-#define  RI_HYSCR2_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR2_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR2_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR2_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR2_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR2_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR2_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR2_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR2_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR2_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR2_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR2_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR2_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR2_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR2_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR2_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define  RI_HYSCR2_PD                   ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
-#define  RI_HYSCR2_PD_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR2_PD_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR2_PD_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR2_PD_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR2_PD_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR2_PD_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR2_PD_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR2_PD_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR2_PD_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR2_PD_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR2_PD_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR2_PD_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR2_PD_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR2_PD_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR2_PD_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR2_PD_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define  RI_HYSCR2_PE                   ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
-#define  RI_HYSCR2_PE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR2_PE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR2_PE_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR2_PE_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR2_PE_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR2_PE_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR2_PE_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR2_PE_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR2_PE_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR2_PE_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR2_PE_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR2_PE_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR2_PE_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR2_PE_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR2_PE_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR2_PE_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define  RI_HYSCR3_PF                   ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
-#define  RI_HYSCR3_PF_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR3_PF_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR3_PF_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR3_PF_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR3_PF_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR3_PF_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR3_PF_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR3_PF_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR3_PF_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR3_PF_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR3_PF_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR3_PF_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR3_PF_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR3_PF_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR3_PF_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR3_PF_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define  RI_HYSCR4_PG                   ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
-#define  RI_HYSCR4_PG_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR4_PG_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR4_PG_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR4_PG_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR4_PG_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR4_PG_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR4_PG_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR4_PG_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR4_PG_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR4_PG_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR4_PG_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR4_PG_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR4_PG_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR4_PG_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR4_PG_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR4_PG_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
-#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
-#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
-#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
-
-#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-
-#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!<OCCS bits (OCref Clear Selection) */
-
-#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
-#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
-#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define  TIM_OR_TI1RMP                       ((uint16_t)0x0003)            /*!<Option register for TI1 Remapping */
-#define  TIM_OR_TI1RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_OR_TI1RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
-#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
-#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
-#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
-#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
-#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
-#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
-#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
-#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
-#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
-#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
-#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
-#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
-#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
-
-#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
-
-#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
-#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
-#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
-
-#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
-
-#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
-#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
-
-#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
-#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
-
-#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
-
-#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
-
-#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
-#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
-
-#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
-#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
-
-#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
-
-#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
-
-#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
-#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
-
-#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
-#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
-
-#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
-
-#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
-
-#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
-#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
-
-#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
-#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
-
-#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
-
-#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
-
-#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
-#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
-
-#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
-#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
-
-#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
-
-#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
-
-#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
-#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
-
-#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
-#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
-
-#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
-
-#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
-
-#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
-#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
-
-#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
-#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
-
-#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
-
-#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
-
-#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
-
-#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
-#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
-
-#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
-#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
-
-#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
-
-#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!<Force USB Reset */
-#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!<Power down */
-#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!<Low-power mode */
-#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!<Force suspend */
-#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!<Resume request */
-#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!<Expected Start Of Frame Interrupt Mask */
-#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!<Start Of Frame Interrupt Mask */
-#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!<RESET Interrupt Mask */
-#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!<Suspend mode Interrupt Mask */
-#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!<Wakeup Interrupt Mask */
-#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!<Error Interrupt Mask */
-#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!<Endpoint Identifier */
-#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!<Direction of transaction */
-#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!<Expected Start Of Frame */
-#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!<Start Of Frame */
-#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!<USB RESET request */
-#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!<Suspend mode request */
-#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!<Wake up */
-#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!<Error */
-#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun */
-#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!<Correct Transfer */
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!<Frame Number */
-#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!<Lost SOF */
-#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!<Locked */
-#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!<Receive Data - Line Status */
-#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!<ADD[6:0] bits (Device Address) */
-#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!<Bit 0 */
-#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!<Bit 1 */
-#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!<Bit 2 */
-#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!<Bit 3 */
-#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!<Bit 4 */
-#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!<Bit 5 */
-#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!<Bit 6 */
-
-#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
-#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
-#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
-#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
-#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
-#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
-#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
-#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
-#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
-#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
-#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        SystemTick (SysTick)                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*****************  Bit definition for SysTick_CTRL register  *****************/
-#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
-#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
-#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
-#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
-
-/*****************  Bit definition for SysTick_LOAD register  *****************/
-#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/*****************  Bit definition for SysTick_VAL register  ******************/
-#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
-
-/*****************  Bit definition for SysTick_CALIB register  ****************/
-#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
-#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
-#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/*                                                                            */
-/*               Nested Vectored Interrupt Controller (NVIC)                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for NVIC_ISER register  *******************/
-#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
-#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICER register  *******************/
-#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
-#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ISPR register  *******************/
-#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
-#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICPR register  *******************/
-#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
-#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_IABR register  *******************/
-#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
-#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_PRI0 register  *******************/
-#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
-#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
-#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
-#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
-
-/******************  Bit definition for NVIC_PRI1 register  *******************/
-#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
-#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
-#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
-#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
-
-/******************  Bit definition for NVIC_PRI2 register  *******************/
-#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
-#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
-#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
-#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
-
-/******************  Bit definition for NVIC_PRI3 register  *******************/
-#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
-#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
-#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
-#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
-
-/******************  Bit definition for NVIC_PRI4 register  *******************/
-#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
-#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
-#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
-#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
-
-/******************  Bit definition for NVIC_PRI5 register  *******************/
-#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
-#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
-#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
-#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
-
-/******************  Bit definition for NVIC_PRI6 register  *******************/
-#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
-#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
-#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
-#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
-
-/******************  Bit definition for NVIC_PRI7 register  *******************/
-#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
-#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
-#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
-#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
-
-/******************  Bit definition for SCB_CPUID register  *******************/
-#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
-#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
-#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
-#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
-#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
-
-/*******************  Bit definition for SCB_ICSR register  *******************/
-#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
-#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
-#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
-#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
-#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
-#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
-#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
-#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
-
-/*******************  Bit definition for SCB_VTOR register  *******************/
-#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
-#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
-
-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
-#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
-#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
-#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
-
-#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
-#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
-
-/* prority group configuration */
-#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
-#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/*******************  Bit definition for SCB_SCR register  ********************/
-#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
-#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
-#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
-
-/********************  Bit definition for SCB_CCR register  *******************/
-#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
-#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
-#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
-#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/*******************  Bit definition for SCB_SHPR register ********************/
-#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/******************  Bit definition for SCB_SHCSR register  *******************/
-#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
-#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
-#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
-#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
-#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
-#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
-#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
-#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
-#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
-#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
-#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
-#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
-#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
-#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
-
-/*******************  Bit definition for SCB_CFSR register  *******************/
-/*!< MFSR */
-#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
-#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
-#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
-#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
-#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
-#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
-#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
-#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
-#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
-#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */
-#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
-#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
-#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
-#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/*******************  Bit definition for SCB_HFSR register  *******************/
-#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */
-#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
-
-/*******************  Bit definition for SCB_DFSR register  *******************/
-#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
-#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
-#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
-#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
-#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
-
-/*******************  Bit definition for SCB_MMFAR register  ******************/
-#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
-
-/*******************  Bit definition for SCB_BFAR register  *******************/
-#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
-
-/*******************  Bit definition for SCB_afsr register  *******************/
-#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-
-#ifdef USE_STDPERIPH_DRIVER
-  #include "stm32l1xx_conf.h"
-#endif
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1XX_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM8L/hal_lld.c b/os/hal/platforms/STM8L/hal_lld.c
deleted file mode 100644
index 06e6ad981..000000000
--- a/os/hal/platforms/STM8L/hal_lld.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8L/hal_lld.c
- * @brief   STM8L HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- * @details Clock sources initialization, HSI is assumed to be already
- *          started after reset.
- * @note    If the @p STM8L_CLOCK_INIT option is set to @p FALSE then the
- *          initialization is not performed and is left to the application.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-#if !STM8L_NO_CLOCK_INIT
-  /* Makes sure that HSI is stable before proceeding.*/
-  CLK->ICKCR |= CLK_ICKCR_HSION;
-  while ((CLK->ICKCR & CLK_ICKCR_HSIRDY) == 0)
-    ;
-
-  /* LSI startup and stabilization if required.*/
-#if STM8L_LSI_ENABLED
-  CLK->ICKCR |= CLK_ICKCR_LSION;
-  while ((CLK->ICKCR & CLK_ICKCR_LSIRDY) == 0)
-    ;
-#endif
-
-  /* HSE startup and stabilization if required.*/
-#if STM8L_HSE_ENABLED
-#if HSEBYPASS
-  CLK->ECKCR |= CLK_ECKCR_HSEON | CLK_ECKCR_HSEBYP;
-#else
-  CLK->ECKCR |= CLK_ECKCR_HSEON;
-#endif
-  while ((CLK->ECKCR & CLK_ECKCR_HSERDY) == 0)
-    ;
-#endif
-
-  /* LSE startup and stabilization if required.*/
-#if STM8L_LSE_ENABLED
-#if LSEBYPASS
-  CLK->ECKCR |= CLK_ECKCR_LSEON | CLK_ECKCR_LSEBYP;
-#else
-  CLK->ECKCR |= CLK_ECKCR_LSEON;
-#endif
-  while ((CLK->ECKCR & CLK_ECKCR_LSERDY) == 0)
-    ;
-#endif
-
-  /* Setting up clock dividers.*/
-  CLK->CKDIVR = STM8L_SYSCLK_DIVIDER << 0;
-
-  /* SYSCLK switch to the selected source, not necessary if it is HSI.*/
-#if STM8L_SYSCLK_SOURCE != CLK_SYSSEL_HSI
-  /* Switching clock (manual switch mode).*/
-  CLK->SWR  = STM8L_SYSCLK_SOURCE;
-  while ((CLK->SWCR & CLK_SWCR_SWIF) == 0)
-    ;
-  CLK->SWCR = CLK_SWCR_SWEN;
-#endif
-
-  /* Clocks initially all disabled, note the boot ROM clock is disabled
-     because the boot loader is no more required and it draws precious uAs.*/
-  CLK->PCKENR1 = 0;
-  CLK->PCKENR2 = 0;
-  CLK->PCKENR3 = 0;
-
-  /* Other clock related initializations.*/
-  CLK->CSSR = 0;
-  CLK->CCOR = 0;
-
-  /* HSI disabled if it is no more required.*/
-#if !STM8L_HSI_ENABLED
-  CLK->ICKCR &= ~CLK_ICKCR_HSION;
-#endif
-#endif /* !STM8L_NO_CLOCK_INIT */
-}
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/hal_lld.h b/os/hal/platforms/STM8L/hal_lld.h
deleted file mode 100644
index 0f8ca6776..000000000
--- a/os/hal/platforms/STM8L/hal_lld.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8L/hal_lld.h
- * @brief   STM8L HAL subsystem low level driver source.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - HSECLK (@p 0 if disabled or frequency in Hertz).
- *          - HSEBYPASS (@p TRUE if external oscillator rather than a crystal).
- *          - LSECLK (@p 0 if disabled or frequency in Hertz).
- *          - LSEBYPASS (@p TRUE if external oscillator rather than a crystal).
- *          .
- *          One of the following macros must also be defined:
- *          - STM8L15X_MD for Medium Density devices.
- *          - STM8L15X_MDP for Medium Density Plus devices.
- *          - STM8L15X_HD for High Density devices.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#undef FALSE
-#undef TRUE
-#include "stm8l15x.h"
-#define FALSE 0
-#define TRUE (!FALSE)
-
-#if defined (STM8L15X_MD)
-#include "hal_lld_stm8l_md.h"
-#elif defined (STM8L15X_MDP)
-#include "hal_lld_stm8l_mdp.h"
-#elif defined (STM8L15X_HD)
-#include "hal_lld_stm8l_hd.h"
-#else
-#error "unspecified, unsupported or invalid STM8L platform"
-#endif
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME       "STM8L"
-
-#define LSICLK              38000       /**< Low speed internal clock.      */
-#define HSICLK              16000000    /**< High speed internal clock.     */
-
-#define CLK_SYSSEL_HSI      1           /**< HSI system clock selector.     */
-#define CLK_SYSSEL_LSI      2           /**< LSI system clock selector.     */
-#define CLK_SYSSEL_HSE      4           /**< HSE system clock selector.     */
-#define CLK_SYSSEL_LSE      8           /**< LSE system clock selector.     */
-
-#define CLK_SYSCLK_DIV1     0           /**< Source clock divided by 1.     */
-#define CLK_SYSCLK_DIV2     1           /**< Source clock divided by 2.     */
-#define CLK_SYSCLK_DIV4     2           /**< Source clock divided by 4.     */
-#define CLK_SYSCLK_DIV8     3           /**< Source clock divided by 8.     */
-#define CLK_SYSCLK_DIV16    4           /**< Source clock divided by 16.    */
-#define CLK_SYSCLK_DIV32    5           /**< Source clock divided by 32.    */
-#define CLK_SYSCLK_DIV64    6           /**< Source clock divided by 64.    */
-#define CLK_SYSCLK_DIV128   7           /**< Source clock divided by 128.   */
-
-#define CLK_RTCSEL_HSI      1           /**< HSI RTC clock selector.        */
-#define CLK_RTCSEL_LSI      2           /**< LSI RTC clock selector.        */
-#define CLK_RTCSEL_HSE      4           /**< HSE RTC clock selector.        */
-#define CLK_RTCSEL_LSE      8           /**< LSE RTC clock selector.        */
-
-#define CLK_RTCCLK_DIV1     0           /**< Source clock divided by 1.     */
-#define CLK_RTCCLK_DIV2     1           /**< Source clock divided by 2.     */
-#define CLK_RTCCLK_DIV4     2           /**< Source clock divided by 4.     */
-#define CLK_RTCCLK_DIV8     3           /**< Source clock divided by 8.     */
-#define CLK_RTCCLK_DIV16    4           /**< Source clock divided by 16.    */
-#define CLK_RTCCLK_DIV32    5           /**< Source clock divided by 32.    */
-#define CLK_RTCCLK_DIV64    6           /**< Source clock divided by 64.    */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Disables the clock initialization in the HAL.
- */
-#if !defined(STM8L_NO_CLOCK_INIT) || defined(__DOXYGEN__)
-#define STM8L_NO_CLOCK_INIT         FALSE
-#endif
-
-/**
- * @brief   Enables or disables the HSI clock source.
- */
-#if !defined(STM8L_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM8L_HSI_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSI clock source.
- */
-#if !defined(STM8L_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM8L_LSI_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the HSE clock source.
- */
-#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM8L_HSE_ENABLED           FALSE
-#endif
-
-/**
- * @brief   Enables or disables the LSE clock source.
- */
-#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM8L_LSE_ENABLED           FALSE
-#endif
-
-/**
- * @brief   System clock source selection.
- */
-#if !defined(STM8L_SYSCLK_SOURCE) || defined(__DOXYGEN__)
-#define STM8L_SYSCLK_SOURCE         CLK_SYSSEL_HSI
-#endif
-
-/**
- * @brief   System clock divider.
- */
-#if !defined(STM8L_SYSCLK_DIVIDER) || defined(__DOXYGEN__)
-#define STM8L_SYSCLK_DIVIDER        CLK_SYSCLK_DIV1
-#endif
-
-/**
- * @brief   RTC clock source selection.
- */
-#if !defined(STM8L_RTCCLK_SOURCE) || defined(__DOXYGEN__)
-#define STM8L_RTCCLK_SOURCE         CLK_RTCSEL_HSI
-#endif
-
-/**
- * @brief   RTC clock divider.
- */
-#if !defined(STM8L_RTCCLK_DIVIDER) || defined(__DOXYGEN__)
-#define STM8L_RTCCLK_DIVIDER        CLK_RTCCLK_DIV1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV1)  &&                           \
-    (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV2)  &&                           \
-    (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV4)  &&                           \
-    (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV8)  &&                           \
-    (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV16) &&                           \
-    (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV32) &&                           \
-    (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV64) &&                           \
-    (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV128)
-#error "specified invalid SYSCLK divider"
-#endif
-
-#if (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV1)  &&                           \
-    (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV2)  &&                           \
-    (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV4)  &&                           \
-    (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV8)  &&                           \
-    (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV16) &&                           \
-    (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV32) &&                           \
-    (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV64)
-#error "specified invalid RTCCLK divider"
-#endif
-
-#if STM8L_HSE_ENABLED && (HSECLK == 0)
-#error "impossible to activate HSE"
-#endif
-
-#if STM8L_LSE_ENABLED && (LSECLK == 0)
-#error "impossible to activate LSE"
-#endif
-
-#if !STM8L_HSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI) ||       \
-                           (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI))
-#error "requested HSI clock is not enabled"
-#endif
-
-#if !STM8L_LSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI) ||       \
-                           (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI))
-#error "requested LSI clock is not enabled"
-#endif
-
-#if !STM8L_HSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE) ||       \
-                           (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE))
-#error "requested HSE clock is not enabled"
-#endif
-
-#if !STM8L_LSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE) ||       \
-                           (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE))
-#error "requested LSE clock is not enabled"
-#endif
-
-/**
- * @brief   System clock.
- */
-#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__)
-#define SYSCLK                      (HSICLK / 8)
-#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI
-#define SYSCLK                      (HSICLK / (1 << STM8L_SYSCLK_DIVIDER))
-#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI
-#define SYSCLK                      (LSICLK / (1 << STM8L_SYSCLK_DIVIDER))
-#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE
-#define SYSCLK                      (HSECLK / (1 << STM8L_SYSCLK_DIVIDER))
-#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE
-#define SYSCLK                      (LSECLK / (1 << STM8L_SYSCLK_DIVIDER))
-#else
-#error "specified invalid SYSCLK source"
-#endif
-
-/**
- * @brief   RTC clock.
- */
-#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__)
-#define RTCCLK                      0
-#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI
-#define RTCCLK                      (HSICLK / (1 << STM8L_RTCCLK_DIVIDER))
-#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI
-#define RTCCLK                      (LSICLK / (1 << STM8L_RTCCLK_DIVIDER))
-#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE
-#define RTCCLK                      (HSECLK / (1 << STM8L_RTCCLK_DIVIDER))
-#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE
-#define RTCCLK                      (LSECLK / (1 << STM8L_RTCCLK_DIVIDER))
-#else
-#error "specified invalid RTCCLK source"
-#endif
-
-/**
- * @brief   CPU clock.
- * @details On the STM8L the CPU clock is always equal to the system clock.
- */
-#define CPUCLK                      SYSCLK
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h b/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h
deleted file mode 100644
index 68a3211d8..000000000
--- a/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM8L_HD_HAL STM8L High Density sub-family
- *
- * @ingroup HAL
- */
-
-/**
- * @file    STM8L/hal_lld_stm8l_hd.h
- * @brief   STM8L High Density sub-family capabilities descriptor.
- *
- * @addtogroup STM8L_HD_HAL
- * @{
- */
-
-#ifndef _HAL_LLD_STM8L_HD_H_
-#define _HAL_LLD_STM8L_HD_H_
-
-/*===========================================================================*/
-/* Sub-family capabilities.                                                  */
-/*===========================================================================*/
-
-#define STM8L_HAS_ADC1              TRUE
-
-#define STM8L_HAS_BEEP              TRUE
-
-#define STM8L_HAS_COMP1             TRUE
-#define STM8L_HAS_COMP2             TRUE
-
-#define STM8L_HAS_DAC1              TRUE
-
-#define STM8L_HAS_DMA1              TRUE
-
-#define STM8L_HAS_GPIOA             TRUE
-#define STM8L_HAS_GPIOB             TRUE
-#define STM8L_HAS_GPIOC             TRUE
-#define STM8L_HAS_GPIOD             TRUE
-#define STM8L_HAS_GPIOE             TRUE
-#define STM8L_HAS_GPIOF             TRUE
-#define STM8L_HAS_GPIOG             TRUE
-#define STM8L_HAS_GPIOH             TRUE
-#define STM8L_HAS_GPIOI             TRUE
-
-#define STM8L_HAS_I2C1              TRUE
-
-#define STM8L_HAS_LCD               TRUE
-
-#define STM8L_HAS_SPI1              TRUE
-#define STM8L_HAS_SPI2              TRUE
-
-#define STM8L_HAS_TIM1              TRUE
-#define STM8L_HAS_TIM2              TRUE
-#define STM8L_HAS_TIM3              TRUE
-#define STM8L_HAS_TIM4              TRUE
-#define STM8L_HAS_TIM5              TRUE
-
-#define STM8L_HAS_USART1            TRUE
-#define STM8L_HAS_USART2            TRUE
-#define STM8L_HAS_USART3            TRUE
-
-#endif /* _HAL_LLD_STM8L_HD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/hal_lld_stm8l_md.h b/os/hal/platforms/STM8L/hal_lld_stm8l_md.h
deleted file mode 100644
index 072a77dca..000000000
--- a/os/hal/platforms/STM8L/hal_lld_stm8l_md.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM8L_MD_HAL STM8L Medium Density sub-family
- *
- * @ingroup HAL
- */
-
-/**
- * @file    STM8L/hal_lld_stm8l_md.h
- * @brief   STM8L Medium Density sub-family capabilities descriptor.
- *
- * @addtogroup STM8L_MD_HAL
- * @{
- */
-
-#ifndef _HAL_LLD_STM8L_MD_H_
-#define _HAL_LLD_STM8L_MD_H_
-
-/*===========================================================================*/
-/* Sub-family capabilities.                                                  */
-/*===========================================================================*/
-
-#define STM8L_HAS_ADC1              TRUE
-
-#define STM8L_HAS_BEEP              TRUE
-
-#define STM8L_HAS_COMP1             TRUE
-#define STM8L_HAS_COMP2             TRUE
-
-#define STM8L_HAS_DAC1              TRUE
-
-#define STM8L_HAS_DMA1              TRUE
-
-#define STM8L_HAS_GPIOA             TRUE
-#define STM8L_HAS_GPIOB             TRUE
-#define STM8L_HAS_GPIOC             TRUE
-#define STM8L_HAS_GPIOD             TRUE
-#define STM8L_HAS_GPIOE             TRUE
-#define STM8L_HAS_GPIOF             TRUE
-#define STM8L_HAS_GPIOG             FALSE
-#define STM8L_HAS_GPIOH             FALSE
-#define STM8L_HAS_GPIOI             FALSE
-
-#define STM8L_HAS_I2C1              TRUE
-
-#define STM8L_HAS_LCD               TRUE
-
-#define STM8L_HAS_SPI1              TRUE
-#define STM8L_HAS_SPI2              FALSE
-
-#define STM8L_HAS_TIM1              TRUE
-#define STM8L_HAS_TIM2              TRUE
-#define STM8L_HAS_TIM3              TRUE
-#define STM8L_HAS_TIM4              TRUE
-#define STM8L_HAS_TIM5              FALSE
-
-#define STM8L_HAS_USART1            TRUE
-#define STM8L_HAS_USART2            FALSE
-#define STM8L_HAS_USART3            FALSE
-
-#endif /* _HAL_LLD_STM8L_MD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h b/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h
deleted file mode 100644
index 83e0672c9..000000000
--- a/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM8L_MDP_HAL STM8L Medium Density Plus sub-family
- *
- * @ingroup HAL
- */
-
-/**
- * @file    STM8L/hal_lld_stm8l_mdp.h
- * @brief   STM8L Medium Density Plus sub-family capabilities descriptor.
- *
- * @addtogroup STM8L_MDP_HAL
- * @{
- */
-
-#ifndef _HAL_LLD_STM8L_MDP_H_
-#define _HAL_LLD_STM8L_MDP_H_
-
-/*===========================================================================*/
-/* Sub-family capabilities.                                                  */
-/*===========================================================================*/
-
-#define STM8L_HAS_ADC1              TRUE
-
-#define STM8L_HAS_BEEP              TRUE
-
-#define STM8L_HAS_COMP1             TRUE
-#define STM8L_HAS_COMP2             TRUE
-
-#define STM8L_HAS_DAC1              TRUE
-
-#define STM8L_HAS_DMA1              TRUE
-
-#define STM8L_HAS_GPIOA             TRUE
-#define STM8L_HAS_GPIOB             TRUE
-#define STM8L_HAS_GPIOC             TRUE
-#define STM8L_HAS_GPIOD             TRUE
-#define STM8L_HAS_GPIOE             TRUE
-#define STM8L_HAS_GPIOF             TRUE
-#define STM8L_HAS_GPIOG             TRUE
-#define STM8L_HAS_GPIOH             TRUE
-#define STM8L_HAS_GPIOI             TRUE
-
-#define STM8L_HAS_I2C1              TRUE
-
-#define STM8L_HAS_LCD               TRUE
-
-#define STM8L_HAS_SPI1              TRUE
-#define STM8L_HAS_SPI2              TRUE
-
-#define STM8L_HAS_TIM1              TRUE
-#define STM8L_HAS_TIM2              TRUE
-#define STM8L_HAS_TIM3              TRUE
-#define STM8L_HAS_TIM4              TRUE
-#define STM8L_HAS_TIM5              TRUE
-
-#define STM8L_HAS_USART1            TRUE
-#define STM8L_HAS_USART2            TRUE
-#define STM8L_HAS_USART3            TRUE
-
-#endif /* _HAL_LLD_STM8L_MDP_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/pal_lld.c b/os/hal/platforms/STM8L/pal_lld.c
deleted file mode 100644
index 1b83d8a8d..000000000
--- a/os/hal/platforms/STM8L/pal_lld.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8L/pal_lld.c
- * @brief   STM8L GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT_PULLUP:
-    port->DDR &= ~mask;
-    port->CR1 |=  mask;
-    port->CR2 &= ~mask;
-    break;
-  case PAL_MODE_INPUT:
-  case PAL_MODE_INPUT_ANALOG:
-    port->DDR &= ~mask;
-    port->CR1 &= ~mask;
-    port->CR2 &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-  case PAL_MODE_OUTPUT_PUSHPULL_SLOW:
-    port->DDR |=  mask;
-    port->CR1 |=  mask;
-    port->CR2 &= ~mask;
-    break;
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->DDR |=  mask;
-    port->CR1 |=  mask;
-    port->CR2 |=  mask;
-    break;
-  case PAL_MODE_OUTPUT_OPENDRAIN_SLOW:
-    port->DDR |=  mask;
-    port->CR1 &= ~mask;
-    port->CR2 &= ~mask;
-    break;
-  case PAL_MODE_OUTPUT_OPENDRAIN:
-    port->DDR |=  mask;
-    port->CR1 &= ~mask;
-    port->CR2 |=  mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/pal_lld.h b/os/hal/platforms/STM8L/pal_lld.h
deleted file mode 100644
index b7dffed26..000000000
--- a/os/hal/platforms/STM8L/pal_lld.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8L/pal_lld.h
- * @brief   STM8L GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLDOWN
-
-/**
- * @brief   STM8L specific alternate push-pull slow output mode.
- */
-#define PAL_MODE_OUTPUT_PUSHPULL_SLOW   16
-
-/**
- * @brief   STM8L specific alternate open-drain slow output mode.
- */
-#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW  17
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-#if STM8L_HAS_GPIOI || defined(__DOXYGEN__)
-  GPIO_TypeDef          P[9];
-#elif STM8L_HAS_GPIOH || defined(__DOXYGEN__)
-  GPIO_TypeDef          P[8];
-#elif STM8L_HAS_GPIOG || defined(__DOXYGEN__)
-  GPIO_TypeDef          P[7];
-#else
-  GPIO_TypeDef          P[6];
-#endif
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 8
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint8_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint8_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef GPIO_TypeDef *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO ports as a whole.
- */
-#define IOPORTS         ((PALConfig *)0x5000)
-
-#if STM8L_HAS_GPIOA || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port A identifier.
- */
-#define IOPORT1         GPIOA
-#endif
-
-#if STM8L_HAS_GPIOB || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port B identifier.
- */
-#define IOPORT2         GPIOB
-#endif
-
-#if STM8L_HAS_GPIOC || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port C identifier.
- */
-#define IOPORT3         GPIOC
-#endif
-
-#if STM8L_HAS_GPIOD || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port D identifier.
- */
-#define IOPORT4         GPIOD
-#endif
-
-#if STM8L_HAS_GPIOE || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port E identifier.
- */
-#define IOPORT5         GPIOE
-#endif
-
-#if STM8L_HAS_GPIOF || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port F identifier.
- */
-#define IOPORT6         GPIOF
-#endif
-
-#if STM8L_HAS_GPIOG || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port G identifier.
- */
-#define IOPORT7         GPIOG
-#endif
-
-#if STM8L_HAS_GPIOH || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port H identifier.
- */
-#define IOPORT8         GPIOH
-#endif
-
-#if STM8L_HAS_GPIOI || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port I identifier.
- */
-#define IOPORT9         GPIOI
-#endif
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) (*IOPORTS = *(config))
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->IDR)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->ODR)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-extern ROMCONST PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/platform.dox b/os/hal/platforms/STM8L/platform.dox
deleted file mode 100644
index 9c28a931b..000000000
--- a/os/hal/platforms/STM8L/platform.dox
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM8L_DRIVERS STM8L Drivers
- * @details This section describes all the supported drivers on the STM8L
- * and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup STM8L_HAL STM8L Initialization Support
- * @details The STM8L HAL support is responsible for system initialization.
- *
- * @section stm8l_hal_1 Supported HW resources
- * - CLK.
- * .
- * @section stm8l_hal_2 STM8L HAL driver implementation features
- * - Board related initializations.
- * - Clock tree initialization.
- * - Clock source selection.
- * .
- * @ingroup STM8L_DRIVERS
- */
-
-/**
- * @defgroup STM8L_PAL STM8L PAL Support
- * @details The STM8L PAL driver uses the GPIO peripherals.
- *
- * @section stm8l_pal_1 Supported HW resources
- * - GPIOA.
- * - GPIOB.
- * - GPIOC.
- * - GPIOD.
- * - GPIOE.
- * - GPIOF.
- * - GPIOG.
- * - GPIOH (where present).
- * - GPIOI (where present).
- * .
- * @section stm8l_pal_2 STM8L PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 8 bits wide ports.
- * - Atomic set/reset/toggle functions because special STM8L instruction set.
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section stm8l_pal_3 Supported PAL setup modes
- * The STM8L PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section stm8l_pal_4 Suboptimal behavior
- * The STM8L GPIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Bus/group writing is not atomic.
- * - Pad/group mode setup is not atomic.
- * .
- * @ingroup STM8L_DRIVERS
- */
-
-/**
- * @defgroup STM8L_SERIAL STM8L Serial Support
- * @details The STM8L Serial driver uses the USART1 peripheral in a
- *          buffered, interrupt driven, implementation.
- *
- * @section stm8l_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART1.
- * - USART2 (where present).
- * - USART3 (where present).
- * .
- * @section stm8l_serial_2 STM8L Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Fully interrupt driven.
- * .
- * @ingroup STM8L_DRIVERS
- */
diff --git a/os/hal/platforms/STM8L/serial_lld.c b/os/hal/platforms/STM8L/serial_lld.c
deleted file mode 100644
index 2ef60bce8..000000000
--- a/os/hal/platforms/STM8L/serial_lld.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8L/serial_lld.c
- * @brief   STM8L low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   USART1 serial driver identifier.
- */
-#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/**
- * @brief   USART2 serial driver identifier.
- */
-#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/**
- * @brief   USART3 serial driver identifier.
- */
-#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Driver default configuration.
- */
-static ROMCONST SerialConfig default_config = {
-  BRR(SERIAL_DEFAULT_BITRATE),
-  SD_MODE_PARITY_NONE | SD_MODE_STOP_1
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  USART1->CR2 |= USART_CR2_TIEN;
-}
-#endif /* STM8L_SERIAL_USE_USART1 */
-
-#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  USART2->CR2 |= USART_CR2_TIEN;
-}
-#endif /* STM8L_SERIAL_USE_USART1 */
-
-#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
-  (void)qp;
-  USART3->CR2 |= USART_CR2_TIEN;
-}
-#endif /* STM8L_SERIAL_USE_USART3 */
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/* See in serial_lld.h.*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] sr        USART SR register value
- *
- * @notapi
- */
-void sd_lld_set_error(SerialDriver *sdp, uint8_t sr) {
-  flagsmask_t sts = 0;
-
-  if (sr & USART_SR_OR)
-    sts |= SD_OVERRUN_ERROR;
-  if (sr & USART_SR_NF)
-    sts |= SD_NOISE_ERROR;
-  if (sr & USART_SR_FE)
-    sts |= SD_FRAMING_ERROR;
-  if (sr & USART_SR_PE)
-    sts |= SD_PARITY_ERROR;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if STM8L_SERIAL_USE_USART1
-  sdObjectInit(&SD1, NULL, notify1);
-  CLK->PCKENR1 |= CLK_PCKENR1_USART1;       /* PCKEN12, clock source.       */
-  USART1->CR1 = USART_CR1_USARTD;           /* USARTD (low power).          */
-  SD1.usart = USART1;
-#endif
-
-#if STM8L_SERIAL_USE_USART2
-  sdObjectInit(&SD2, NULL, notify2);
-  CLK->PCKENR3 |= CLK_PCKENR3_USART2;       /* PCKEN13, clock source.       */
-  USART2->CR1 = USART_CR1_USARTD;           /* USARTD (low power).          */
-  SD2.usart = USART2;
-#endif
-
-#if STM8L_SERIAL_USE_USART3
-  sdObjectInit(&SD3, NULL, notify3);
-  CLK->PCKENR3 |= CLK_PCKENR3_USART3;       /* PCKEN13, clock source.       */
-  USART3->CR1 = USART_CR1_USARTD;           /* USARTD (low power).          */
-  SD3.usart = USART3;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-  USART_TypeDef *u = sdp->usart;
-
-  if (config == NULL)
-    config = &default_config;
-
-  u->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
-                      ((uint8_t)config->sc_brr & (uint8_t)0x0F));
-  u->BRR1 = (uint8_t)(config->sc_brr >> 4);
-  u->CR1  = (uint8_t)(config->sc_mode & SD_MODE_PARITY);
-  u->CR2  = USART_CR2_RIEN | USART_CR2_TEN | USART_CR2_REN;
-  u->CR3  = (uint8_t)(config->sc_mode & SD_MODE_STOP);
-  u->CR4  = 0;
-  u->CR5  = 0;
-  u->PSCR = 1;
-  (void)u->SR;
-  (void)u->DR;
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-  USART_TypeDef *u = sdp->usart;
-
-  u->CR1  = USART_CR1_USARTD;
-  u->CR2  = 0;
-  u->CR3  = 0;
-  u->CR4  = 0;
-  u->CR5  = 0;
-  u->PSCR = 0;
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/serial_lld.h b/os/hal/platforms/STM8L/serial_lld.h
deleted file mode 100644
index 1164cc8fc..000000000
--- a/os/hal/platforms/STM8L/serial_lld.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8L/serial_lld.h
- * @brief   STM8L low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define SD_MODE_PARITY          0x07        /**< @brief Parity field mask.  */
-#define SD_MODE_PARITY_NONE     0x00        /**< @brief No parity.          */
-#define SD_MODE_PARITY_EVEN     0x05        /**< @brief Even parity.        */
-#define SD_MODE_PARITY_ODD      0x07        /**< @brief Odd parity.         */
-
-#define SD_MODE_STOP            0x30        /**< @brief Stop bits mask.     */
-#define SD_MODE_STOP_1          0x00        /**< @brief One stop bit.       */
-#define SD_MODE_STOP_2          0x20        /**< @brief Two stop bits.      */
-#define SD_MODE_STOP_1P5        0x30        /**< @brief 1.5 stop bits.      */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   USART1 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM8L_SERIAL_USE_USART1) || defined(__DOXYGEN__)
-#define STM8L_SERIAL_USE_USART1     TRUE
-#endif
-
-/**
- * @brief   USART2 driver enable switch.
- * @details If set to @p TRUE the support for USART3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM8L_SERIAL_USE_USART2) || defined(__DOXYGEN__)
-#define STM8L_SERIAL_USE_USART2     TRUE
-#endif
-
-/**
- * @brief   USART3 driver enable switch.
- * @details If set to @p TRUE the support for USART3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM8L_SERIAL_USE_USART3) || defined(__DOXYGEN__)
-#define STM8L_SERIAL_USE_USART3     TRUE
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM8L_SERIAL_USE_USART1 && !STM8L_HAS_USART1
-#error "USART1 not present in the selected device"
-#endif
-
-#if STM8L_SERIAL_USE_USART2 && !STM8L_HAS_USART2
-#error "USART2 not present in the selected device"
-#endif
-
-#if STM8L_SERIAL_USE_USART3 && !STM8L_HAS_USART3
-#error "USART3 not present in the selected device"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    This structure content is architecture dependent, each driver
- *          implementation defines its own version and the custom static
- *          initializers.
- */
-typedef struct {
-  /**
-   * @brief Bit rate register.
-   */
-  uint16_t                  sc_brr;
-  /**
-   * @brief Mode flags.
-   */
-  uint8_t                   sc_mode;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  USART_TypeDef             *usart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Macro for baud rate computation.
- * @note    Make sure the final baud rate is within tolerance.
- */
-#define BRR(b) (SYSCLK / (b))
-
-#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-/**
- * @brief USART1 RX interrupt handler segment.
- */
-#define _USART1_RECEIVE_ISR() {                                             \
-  uint8_t sr = USART1->SR;                                                  \
-  if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF |                     \
-            USART_SR_FE | USART_SR_PE)) {                                   \
-    if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE))       \
-      sd_lld_set_error(&SD1, sr);                                           \
-    chSysLockFromIsr();                                                     \
-    sdIncomingDataI(&SD1, USART1->DR);                                      \
-    chSysUnlockFromIsr();                                                   \
-  }                                                                         \
-}
-
-/**
- * @brief USART1 TX interrupt handler segment.
- */
-#define _USART1_TRANSMIT_ISR() {                                            \
-  if (USART1->SR & USART_SR_TXE) {                                          \
-    msg_t b;                                                                \
-    chSysLockFromIsr();                                                     \
-    b = sdRequestDataI(&SD1);                                               \
-    chSysUnlockFromIsr();                                                   \
-    if (b < Q_OK)                                                           \
-      USART1->CR2 &= (uint8_t)~USART_CR2_TIEN;                              \
-    else                                                                    \
-      USART1->DR = (uint8_t)b;                                              \
-  }                                                                         \
-}
-#endif /* STM8L_SERIAL_USE_USART1 */
-
-#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-/**
- * @brief USART2 RX interrupt handler segment.
- */
-#define _USART2_RECEIVE_ISR() {                                             \
-  uint8_t sr = USART2->SR;                                                  \
-  if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF |                     \
-            USART_SR_FE | USART_SR_PE)) {                                   \
-    if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE))       \
-      sd_lld_set_error(&SD2, sr);                                           \
-    chSysLockFromIsr();                                                     \
-    sdIncomingDataI(&SD2, USART2->DR);                                      \
-    chSysUnlockFromIsr();                                                   \
-  }                                                                         \
-}
-
-/**
- * @brief USART2 TX interrupt handler segment.
- */
-#define _USART2_TRANSMIT_ISR() {                                            \
-  if (USART2->SR & USART_SR_TXE) {                                          \
-    msg_t b;                                                                \
-    chSysLockFromIsr();                                                     \
-    b = sdRequestDataI(&SD2);                                               \
-    chSysUnlockFromIsr();                                                   \
-    if (b < Q_OK)                                                           \
-      USART2->CR2 &= (uint8_t)~USART_CR2_TIEN;                              \
-    else                                                                    \
-      USART2->DR = (uint8_t)b;                                              \
-  }                                                                         \
-}
-#endif /* STM8L_SERIAL_USE_USART2 */
-
-#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-/**
- * @brief USART3 RX interrupt handler segment.
- */
-#define _USART3_RECEIVE_ISR() {                                             \
-  uint8_t sr = USART3->SR;                                                  \
-  if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF |                     \
-            USART_SR_FE | USART_SR_PE)) {                                   \
-    if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE))       \
-      sd_lld_set_error(&SD3, sr);                                           \
-    chSysLockFromIsr();                                                     \
-    sdIncomingDataI(&SD3, USART3->DR);                                      \
-    chSysUnlockFromIsr();                                                   \
-  }                                                                         \
-}
-
-/**
- * @brief USART3 TX interrupt handler segment.
- */
-#define _USART3_TRANSMIT_ISR() {                                            \
-  if (USART3->SR & USART_SR_TXE) {                                          \
-    msg_t b;                                                                \
-    chSysLockFromIsr();                                                     \
-    b = sdRequestDataI(&SD3);                                               \
-    chSysUnlockFromIsr();                                                   \
-    if (b < Q_OK)                                                           \
-      USART3->CR2 &= (uint8_t)~USART_CR2_TIEN;                              \
-    else                                                                    \
-      USART3->DR = (uint8_t)b;                                              \
-  }                                                                         \
-}
-#endif /* STM8L_SERIAL_USE_USART3 */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM8L_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if STM8L_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-#if STM8L_SERIAL_USE_USART3 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-  void sd_lld_set_error(SerialDriver *sdp, uint8_t sr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/shared_isr.c b/os/hal/platforms/STM8L/shared_isr.c
deleted file mode 100644
index ed94a112b..000000000
--- a/os/hal/platforms/STM8L/shared_isr.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8L/shared_isr.c
- * @brief   STM8L shared interrupt code source.
- * @details The STM8L shares some interrupt handlers among several sources.
- *          This module includes all the interrupt handlers that are
- *          used by more than one peripheral.
- * @note    Only the interrupt handlers that are used by the HAL are defined
- *          in this module.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/* This inclusion allows user ISR to be added to the HAL.*/
-#if defined(_USER_ISR_)
-#include "user_isr.h"
-#endif
-
-#if defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) ||         \
-    defined(__DOXYGEN__)
-/**
- * @brief   IRQ 19 service routine.
- * @details This handler is shared between the following sources:
- *          - TIM2 update/overflow/trigger/break.
- *          - USART2 transmit.
- *          .
- *
- * @isr
- */
-CH_IRQ_HANDLER(19) {
-  CH_IRQ_PROLOGUE();
-
-#if defined(_TIM2_UPDATE_ISR)
-  _TIM2_UPDATE_ISR();
-#endif
-#if defined(_USART2_TRANSMIT_ISR)
-  _USART2_TRANSMIT_ISR();
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) */
-
-#if defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) ||           \
-    defined(__DOXYGEN__)
-/**
- * @brief   IRQ 20 service routine.
- * @details This handler is shared between the following sources:
- *          - TIM2 compare/capture
- *          - USART2 receive.
- *          .
- *
- * @isr
- */
-CH_IRQ_HANDLER(20) {
-  CH_IRQ_PROLOGUE();
-
-#if defined(_TIM2_COMPARE_ISR)
-  _TIM2_COMPARE_ISR();
-#endif
-#if defined(_USART2_RECEIVE_ISR)
-  _USART2_RECEIVE_ISR();
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) */
-
-#if defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) ||         \
-    defined(__DOXYGEN__)
-/**
- * @brief   IRQ 21 service routine.
- * @details This handler is shared between the following sources:
- *          - TIM3 update/overflow/trigger/break.
- *          - USART3 transmit.
- *          .
- *
- * @isr
- */
-CH_IRQ_HANDLER(21) {
-  CH_IRQ_PROLOGUE();
-
-#if defined(_TIM3_UPDATE_ISR)
-  _TIM3_UPDATE_ISR();
-#endif
-#if defined(_USART3_TRANSMIT_ISR)
-  _USART3_TRANSMIT_ISR();
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) */
-
-#if defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) ||           \
-    defined(__DOXYGEN__)
-/**
- * @brief   IRQ 22 service routine.
- * @details This handler is shared between the following sources:
- *          - TIM3 compare/capture
- *          - USART3 receive.
- *          .
- *
- * @isr
- */
-CH_IRQ_HANDLER(22) {
-  CH_IRQ_PROLOGUE();
-
-#if defined(_TIM3_COMPARE_ISR)
-  _TIM3_COMPARE_ISR();
-#endif
-#if defined(_USART3_RECEIVE_ISR)
-  _USART3_RECEIVE_ISR();
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) */
-
-#if defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) ||         \
-    defined(__DOXYGEN__)
-/**
- * @brief   IRQ 27 service routine.
- * @details This handler is shared between the following sources:
- *          - TIM5 update/overflow/trigger/break.
- *          - USART1 transmit.
- *          .
- *
- * @isr
- */
-CH_IRQ_HANDLER(27) {
-  CH_IRQ_PROLOGUE();
-
-#if defined(_TIM5_UPDATE_ISR)
-  _TIM5_UPDATE_ISR();
-#endif
-#if defined(_USART1_TRANSMIT_ISR)
-  _USART1_TRANSMIT_ISR();
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) */
-
-#if defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) ||           \
-    defined(__DOXYGEN__)
-/**
- * @brief   IRQ 28 service routine.
- * @details This handler is shared between the following sources:
- *          - TIM5 compare/capture
- *          - USART1 receive.
- *          .
- *
- * @isr
- */
-CH_IRQ_HANDLER(28) {
-  CH_IRQ_PROLOGUE();
-
-#if defined(_TIM5_COMPARE_ISR)
-  _TIM5_COMPARE_ISR();
-#endif
-#if defined(_USART1_RECEIVE_ISR)
-  _USART1_RECEIVE_ISR();
-#endif
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) */
-
-/** @} */
diff --git a/os/hal/platforms/STM8L/stm8l15x.h b/os/hal/platforms/STM8L/stm8l15x.h
deleted file mode 100644
index 6971a9da5..000000000
--- a/os/hal/platforms/STM8L/stm8l15x.h
+++ /dev/null
@@ -1,3000 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm8l15x.h
-  * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    13-May-2011
-  * @brief   This file contains all the peripheral register's definitions, bits
-  *          definitions and memory mapping for STM8L15x devices.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM8L15x_H
- #define __STM8L15x_H
-
-/** @addtogroup STM8L15x_StdPeriph_Driver
-  * @{
-  */
-/* Uncomment the line below according to the target STM8L15x device used in your
-   application
-  */
-/* #define STM8L15X_LD */     /*!< STM8L15X_LD: STM8L15x Low density devices */
-/* #define STM8L15X_MD */     /*!< STM8L15X_MD: STM8L15x Medium density devices */
-/* #define STM8L15X_MDP */    /*!< STM8L15X_MDP: STM8L15x Medium density plus devices */
-/* #define STM8L15X_HD */    /*!< STM8L15X_HD: STM8L15x/16x High density devices */
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-
- - Low density STM8L15x devices are STM8L151C3, STM8L151K3, STM8L151G3, STM8L151F3,
-   STM8L151C2, STM8L151K2, STM8L151G2 and STM8L151F2 microcontrollers where the 
-   Flash memory density ranges between 4 and 8 Kbytes.
- - Medium density STM8L15x devices are STM8L151C4, STM8L151C6, STM8L152C4,
-   STM8L152C6, STM8L151K4, STM8L151K6, STM8L152K4, STM8L152K6, STM8L151G4,
-   STM8L151G6, STM8L152G4 and STM8L152G6 microcontrollers where the Flash memory
-   density ranges between 16 and 32 Kbytes.
- - Medium density Plus devices are STM8L151R6, STM8L152R6 microcontrollers where
-  the Flash memory density is fixed and equal to 32 Kbytes and a wider range of
-  peripheral than the medium density devices.
- - High density STM8L15x devices are STM8L151x8, STM8L152x8, STM8L162R8 and STM8L162M8
-   microcontrollers where the Flash memory density is fixed and equal to 64 Kbytes with 
-   the same peripheral set than Medium Density Plus devices.
-
- */
-
-#if !defined (STM8L15X_MD) && !defined (STM8L15X_MDP) && !defined (STM8L15X_HD) && !defined (STM8L15X_LD)
- #error "Please select first the target STM8L device used in your application (in stm8l15x.h file)"
-#endif
-
-/******************************************************************************/
-/*                   Library configuration section                            */
-/******************************************************************************/
-/* Check the used compiler */
-#if defined(__CSMC__)
- #define _COSMIC_
-#elif defined(__RCST7__)
- #define _RAISONANCE_
-#elif defined(__ICCSTM8__)
- #define _IAR_
-#else
- #error "Unsupported Compiler!"          /* Compiler defines not found */
-#endif
-
-#if !defined  USE_STDPERIPH_DRIVER
-/* Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will be
-   based on direct access to peripherals registers */
-/* CHIBIOS FIX */
-/* #define USE_STDPERIPH_DRIVER*/
-#endif
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application
-
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */
-#if !defined  HSE_Value
- #define HSE_VALUE   ((uint32_t)16000000) /*!< Typical Value of the HSE in Hz */
-#endif /* HSE_Value */
-
-/**
-  * @brief Definition of External Low Speed oscillator (LSE) frequency
-  */
-#define LSE_VALUE   ((uint32_t)32768)   /*!< Typical Value of the LSE in Hz */
-
-/**
-  * @brief Definition of Device on-chip RC oscillator frequencies
-  */
-#define HSI_VALUE   ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */
-#define LSI_VALUE   ((uint32_t)38000)    /*!< Typical Value of the LSI in Hz */
-
-#ifdef _COSMIC_
- #define FAR  @far
- #define NEAR @near
- #define TINY @tiny
- #define EEPROM @eeprom
- #define CONST  const
-#elif defined (_RAISONANCE_) /* __RCST7__ */
- #define FAR  far
- #define NEAR data
- #define TINY page0
- #define EEPROM eeprom
- #define CONST  code
- #if defined (STM8L15X_MD) || defined (STM8L15X_MDP)
-  /*!< Used with memory Models for code less than 64K */
-  #define MEMCPY memcpy
- #else /* STM8L15X_HD */
-   /*!< Used with memory Models for code higher than 64K */
-  #define MEMCPY fmemcpy
- #endif /* STM8L15X_MD or STM8L15X_MDP */ 
-#else /*_IAR_*/
- #define FAR  __far
- #define NEAR __near
- #define TINY __tiny
- #define EEPROM __eeprom
- #define CONST  const
-#endif /* __CSMC__ */
-
-/**
-  * @brief Legacy definition
-  */
-#define __CONST  CONST
-
-#if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L15X_LD) 
-/*!< Used with memory Models for code smaller than 64K */
- #define PointerAttr NEAR
-#else /* STM8L15X_HD */
-/*!< Used with memory Models for code higher than 64K */
- #define PointerAttr FAR
-#endif /* STM8L15X_MD or STM8L15X_MDP or STM8L15X_LD*/
-
-/* Uncomment the line below to enable the FLASH functions execution from RAM */
-#if !defined (RAM_EXECUTION)
-/* #define RAM_EXECUTION  (1) */
-#endif /* RAM_EXECUTION */
-
-#ifdef RAM_EXECUTION
- #ifdef _COSMIC_
-   #define IN_RAM(a) a
- #elif defined (_RAISONANCE_) /* __RCST7__ */
-   #define IN_RAM(a) a inram
- #else /*_IAR_*/
-  #define IN_RAM(a) __ramfunc a
- #endif /* _COSMIC_ */
-#else 
-  #define IN_RAM(a) a
-#endif /* RAM_EXECUTION */
-
-/*!< [31:16] STM8L15X Standard Peripheral Library main version */
-#define __STM8L15X_STDPERIPH_VERSION_MAIN   ((uint8_t)0x01) /*!< [31:24] main version */                                  
-#define __STM8L15X_STDPERIPH_VERSION_SUB1   ((uint8_t)0x05) /*!< [23:16] sub1 version */
-#define __STM8L15X_STDPERIPH_VERSION_SUB2   ((uint8_t)0x00) /*!< [15:8]  sub2 version */
-#define __STM8L15X_STDPERIPH_VERSION_RC     ((uint8_t)0x00) /*!< [7:0]  release candidate */ 
-#define __STM8L15X_STDPERIPH_VERSION       ( (__STM8L15X_STDPERIPH_VERSION_MAIN << 24)\
-                                          |(__STM8L15X_STDPERIPH_VERSION_SUB1 << 16)\
-                                          |(__STM8L15X_STDPERIPH_VERSION_SUB2 << 8)\
-                                          |(__STM8L15X_STDPERIPH_VERSION_RC))
-
-/******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types and constants ----------------------------------------------*/
-
-/** @addtogroup Exported_types
-  * @{
-  */
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-#define     __I     volatile const   /*!< defines 'read only' permissions     */
-#define     __O     volatile         /*!< defines 'write only' permissions    */
-#define     __IO    volatile         /*!< defines 'read / write' permissions  */
-
-/* CHIBIOS FIX */
-#if 0
-/*!< Signed integer types  */
-typedef   signed char     int8_t;
-typedef   signed short    int16_t;
-typedef   signed long     int32_t;
-
-/*!< Unsigned integer types  */
-typedef unsigned char     uint8_t;
-typedef unsigned short    uint16_t;
-typedef unsigned long     uint32_t;
-#endif
-
-/*!< STM8Lx Standard Peripheral Library old types (maintained for legacy purpose) */
-
-typedef int32_t  s32;
-typedef int16_t s16;
-typedef int8_t  s8;
-
-typedef uint32_t  u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-
-typedef enum {FALSE = 0, TRUE = !FALSE} bool;
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-#define U8_MAX     (255)
-#define S8_MAX     (127)
-#define S8_MIN     (-128)
-#define U16_MAX    (65535u)
-#define S16_MAX    (32767)
-#define S16_MIN    (-32768)
-#define U32_MAX    (4294967295uL)
-#define S32_MAX    (2147483647)
-#define S32_MIN    (-2147483648uL)
-
-/**
-  * @}
-  */
-
-/** @addtogroup MAP_FILE_Exported_Types_and_Constants
-  * @{
-  */
-
-/******************************************************************************/
-/*                          IP registers structures                           */
-/******************************************************************************/
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief General Purpose I/Os (GPIO)
-  */
-typedef struct GPIO_struct
-{
-  __IO uint8_t ODR; /*!< Output Data Register */
-  __IO uint8_t IDR; /*!< Input Data Register */
-  __IO uint8_t DDR; /*!< Data Direction Register */
-  __IO uint8_t CR1; /*!< Configuration Register 1 */
-  __IO uint8_t CR2; /*!< Configuration Register 2 */
-}
-GPIO_TypeDef;
-
-/** @addtogroup GPIO_Registers_Reset_Value
-  * @{
-  */
-#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
-#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
-#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
-#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief Real-Time Clock (RTC) peripheral registers.
-  */
-typedef struct RTC_struct
-{
-  __IO uint8_t TR1; /*!<  Time  Register  1*/
-  __IO uint8_t TR2; /*!<  Time  Register  2*/
-  __IO uint8_t TR3; /*!<  Time  Register  3*/
-
-  uint8_t RESERVED0;
-
-  __IO uint8_t DR1; /*!<  Date  Register  1*/
-  __IO uint8_t DR2; /*!<  Date  Register  2*/
-  __IO uint8_t DR3; /*!<  Date  Register  3*/
-
-  uint8_t RESERVED1;
-
-  __IO uint8_t CR1; /*!<  Control  Register  1*/
-  __IO uint8_t CR2; /*!<  Control  Register  2*/
-  __IO uint8_t CR3; /*!<  Control  Register  3*/
-
-  uint8_t RESERVED2;
-
-  __IO uint8_t ISR1; /*!<  Initialisation and Status  Register 1 */
-  __IO uint8_t ISR2; /*!<  Initialisation and Status  Register 2 */
-
-  uint8_t RESERVED3;
-  uint8_t RESERVED4;
-
-  __IO uint8_t SPRERH; /*!<  Synchronous Prediv high  Register  */
-  __IO uint8_t SPRERL; /*!<  Synchronous Prediv Low Register  */
-  __IO uint8_t APRER;  /*!<  Asynchronous Prediv  Register  */
-
-  uint8_t RESERVED5;
-
-  __IO uint8_t WUTRH; /*!<  Wake-Up Timer High Register  */
-  __IO uint8_t WUTRL; /*!<  Wake-Up Timer  Low Register  */
-
-  uint8_t RESERVED6;
-
-  __IO uint8_t SSRH; /*!< Sub Second High Register  */
-  __IO uint8_t SSRL; /*!< Sub Second Low Register  */
-
-  __IO uint8_t WPR;  /*!< Write Protection Register  */
-
-  __IO uint8_t SHIFTRH; /*!< Shift control High Register  */
-  __IO uint8_t SHIFTRL; /*!<  Shift control Low Register  */
-
-  __IO uint8_t ALRMAR1; /*!<  ALARM A  Register 1  */
-  __IO uint8_t ALRMAR2; /*!<  ALARM A  Register 2 */
-  __IO uint8_t ALRMAR3; /*!<  ALARM A  Register 3 */
-  __IO uint8_t ALRMAR4; /*!<  ALARM A  Register 4 */
-
-  uint8_t RESERVED7[4];
-
-  __IO uint8_t ALRMASSRH; /*!<  ALARM A Subsecond Register High */
-  __IO uint8_t ALRMASSRL; /*!<  ALARM A Subsecond Register Low  */
-  __IO uint8_t ALRMASSMSKR; /*!<  ALARM A Subsecond Mask Register  */
-
-  uint8_t RESERVED8[3];
-
-  __IO uint8_t CALRH; /*!<  Calibration register high  */
-  __IO uint8_t CALRL; /*!<  Calibration register low  */
-
-  __IO uint8_t TCR1; /*!<  Tamper control register 1   */
-  __IO uint8_t TCR2; /*!<  Tamper control register 2  */
-}
-RTC_TypeDef;
-
-/** @addtogroup RTC_Registers_Reset_Value
-  * @{
-  */
-#define RTC_TR1_RESET_VALUE       ((uint8_t)0x00)
-#define RTC_TR2_RESET_VALUE       ((uint8_t)0x00)
-#define RTC_TR3_RESET_VALUE       ((uint8_t)0x00)
-
-#define RTC_DR1_RESET_VALUE       ((uint8_t)0x01)
-#define RTC_DR2_RESET_VALUE       ((uint8_t)0x21)
-#define RTC_DR3_RESET_VALUE       ((uint8_t)0x00)
-
-#define RTC_CR1_RESET_VALUE       ((uint8_t)0x00)
-#define RTC_CR2_RESET_VALUE       ((uint8_t)0x00)
-#define RTC_CR3_RESET_VALUE       ((uint8_t)0x00)
-
-#define RTC_ISR1_RESET_VALUE      ((uint8_t)0x07)
-#define RTC_ISR2_RESET_VALUE      ((uint8_t)0x00)
-
-#define RTC_SPRERH_RESET_VALUE    ((uint8_t)0x00)
-#define RTC_SPRERL_RESET_VALUE    ((uint8_t)0xFF)
-#define RTC_APRER_RESET_VALUE     ((uint8_t)0x7F)
-
-#define RTC_WUTRH_RESET_VALUE     ((uint8_t)0xFF)
-#define RTC_WUTRL_RESET_VALUE     ((uint8_t)0xFF)
-
-#define RTC_WPR_RESET_VALUE       ((uint8_t)0x00)
-
-#define RTC_ALRMAR1_RESET_VALUE   ((uint8_t)0x00)
-#define RTC_ALRMAR2_RESET_VALUE   ((uint8_t)0x00)
-#define RTC_ALRMAR3_RESET_VALUE   ((uint8_t)0x00)
-#define RTC_ALRMAR4_RESET_VALUE   ((uint8_t)0x00)
-
-#define RTC_SHIFTRH_RESET_VALUE   ((uint8_t)0x00)
-#define RTC_SHIFTRL_RESET_VALUE   ((uint8_t)0x00)
-
-#define RTC_ALRMASSRH_RESET_VALUE   ((uint8_t)0x00)
-#define RTC_ALRMASSRL_RESET_VALUE   ((uint8_t)0x00)
-#define RTC_ALRMASSMSKR_RESET_VALUE   ((uint8_t)0x00)
-
-#define RTC_CALRH_RESET_VALUE   ((uint8_t)0x00)
-#define RTC_CALRL_RESET_VALUE   ((uint8_t)0x00)
-
-#define RTC_TCR1_RESET_VALUE   ((uint8_t)0x00)
-#define RTC_TCR2_RESET_VALUE   ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Registers_Bits_Definition
-  * @{
-  */
-
-/* Bits definition for RTC_TR1 register*/
-#define RTC_TR1_ST               ((uint8_t)0x70)
-#define RTC_TR1_SU               ((uint8_t)0x0F)
-
-/* Bits definition for RTC_TR2 register*/
-#define RTC_TR2_MNT              ((uint8_t)0x70)
-#define RTC_TR2_MNU              ((uint8_t)0x0F)
-
-/* Bits definition for RTC_TR3 register*/
-#define RTC_TR3_PM               ((uint8_t)0x40)
-#define RTC_TR3_HT               ((uint8_t)0x30)
-#define RTC_TR3_HU               ((uint8_t)0x0F)
-
-/* Bits definition for RTC_DR1 register*/
-#define RTC_DR1_DT               ((uint8_t)0x30)
-#define RTC_DR1_DU               ((uint8_t)0x0F)
-
-/* Bits definition for RTC_DR2 register*/
-#define RTC_DR2_WDU              ((uint8_t)0xE0)
-#define RTC_DR2_MT               ((uint8_t)0x10)
-#define RTC_DR2_MU               ((uint8_t)0x0F)
-
-/* Bits definition for RTC_DR3 register*/
-#define RTC_DR3_YT               ((uint8_t)0xF0)
-#define RTC_DR3_YU               ((uint8_t)0x0F)
-
-/* Bits definition for RTC_CR1 register*/
-#define RTC_CR1_FMT              ((uint8_t)0x40)
-#define RTC_CR1_RATIO            ((uint8_t)0x20)
-#define RTC_CR1_WUCKSEL          ((uint8_t)0x07)
-#define RTC_CR1_BYPSHAD           ((uint8_t)0x10)
-
-
-/* Bits definition for RTC_CR2 register*/
-#define RTC_CR2_WUTIE            ((uint8_t)0x40)
-#define RTC_CR2_ALRAIE           ((uint8_t)0x10)
-#define RTC_CR2_WUTE             ((uint8_t)0x04)
-#define RTC_CR2_ALRAE            ((uint8_t)0x01)
-#define RTC_CR2_ALRIE            ((uint8_t)0x20)
-
-
-
-/* Bits definition for RTC_CR3 register*/
-#define RTC_CR3_COE              ((uint8_t)0x80)
-#define RTC_CR3_OSEL             ((uint8_t)0x60)
-#define RTC_CR3_POL              ((uint8_t)0x10)
-#define RTC_CR3_COSEL            ((uint8_t)0x08)
-#define RTC_CR3_BCK              ((uint8_t)0x04)
-#define RTC_CR3_SUB1H            ((uint8_t)0x02)
-#define RTC_CR3_ADD1H            ((uint8_t)0x01)
-
-
-/* Bits definition for RTC_ISR1 register*/
-#define RTC_ISR1_INIT            ((uint8_t)0x80)
-#define RTC_ISR1_INITF           ((uint8_t)0x40)
-#define RTC_ISR1_RSF             ((uint8_t)0x20)
-#define RTC_ISR1_INITS           ((uint8_t)0x10)
-#define RTC_ISR1_SHPF            ((uint8_t)0x08)
-#define RTC_ISR1_WUTWF           ((uint8_t)0x04)
-#define RTC_ISR1_RECALPF         ((uint8_t)0x02)
-#define RTC_ISR1_ALRAWF          ((uint8_t)0x01)
-
-
-/* Bits definition for RTC_ISR2 register*/
-#define RTC_ISR2_WUTF            ((uint8_t)0x04)
-#define RTC_ISR2_ALRAF           ((uint8_t)0x01)
-#define RTC_ISR2_TAMP3F          ((uint8_t)0x80)
-#define RTC_ISR2_TAMP2F          ((uint8_t)0x40)
-#define RTC_ISR2_TAMP1F          ((uint8_t)0x20)
-
-/* Bits definition for RTC_SHIFTRH register*/
-#define RTC_SHIFTRH_ADD1S        ((uint8_t)0x80)
-#define RTC_SHIFTRH_SUBFS        ((uint8_t)0x7F)
-
-/* Bits definition for RTC_SHIFTRL register*/
-#define RTC_SHIFTRL_SUBFS        ((uint8_t)0xFF)
-
-
-/* Bits definition for RTC_ALRMAR1 register*/
-#define RTC_ALRMAR1_MSK1         ((uint8_t)0x80)
-#define RTC_ALRMAR1_ST           ((uint8_t)0x70)
-#define RTC_ALRMAR1_SU           ((uint8_t)0x0F)
-
-/* Bits definition for RTC_ALRMAR2 register*/
-#define RTC_ALRMAR2_MSK2         ((uint8_t)0x80)
-#define RTC_ALRMAR2_MNT          ((uint8_t)0x70)
-#define RTC_ALRMAR2_MNU          ((uint8_t)0x0F)
-
-/* Bits definition for RTC_ALRMAR3 register*/
-#define RTC_ALRMAR3_MSK3         ((uint8_t)0x80)
-#define RTC_ALRMAR3_PM           ((uint8_t)0x40)
-#define RTC_ALRMAR3_HT           ((uint8_t)0x30)
-#define RTC_ALRMAR3_HU           ((uint8_t)0x0F)
-
-/* Bits definition for RTC_ALRMAR4 register*/
-#define RTC_ALRMAR4_MSK4         ((uint8_t)0x80)
-#define RTC_ALRMAR4_WDSEL        ((uint8_t)0x40)
-#define RTC_ALRMAR4_DT           ((uint8_t)0x30)
-#define RTC_ALRMAR4_DU           ((uint8_t)0x0F)
-
-/* Bits definition for RTC_ALRMASSRH register*/
-#define RTC_ALRMASSRH_ALSS         ((uint8_t)0x7F)
-
-/* Bits definition for RTC_ALRMASSRL register*/
-#define RTC_ALRMASSRL_ALSS         ((uint8_t)0xFF)
-
-/* Bits definition for RTC_ALRMASSMSKR register*/
-#define RTC_ALRMASSMSKR_MASKSS   ((uint8_t)0x1F)
-
-
-/* Bits definition for RTC_CALRH register*/
-#define RTC_CALRH_CALP          ((uint8_t)0x80)
-#define RTC_CALRH_CALW8         ((uint8_t)0x40)
-#define RTC_CALRH_CALW16        ((uint8_t)0x20)
-#define RTC_CALRH_CALWx         ((uint8_t)0x60)
-#define RTC_CALRH_CALM          ((uint8_t)0x01)
-
-/* Bits definition for RTC_CALRL register*/
-#define RTC_CALRL_CALM          ((uint8_t)0xFF)
-
-/* Bits definition for RTC_TCR1 register*/
-#define RTC_TCR1_TAMP3LEVEL     ((uint8_t)0x40)
-#define RTC_TCR1_TAMP3E         ((uint8_t)0x20)
-#define RTC_TCR1_TAMP2LEVEL     ((uint8_t)0x10)
-#define RTC_TCR1_TAMP2E         ((uint8_t)0x08)
-#define RTC_TCR1_TAMP1LEVEL     ((uint8_t)0x04)
-#define RTC_TCR1_TAMP1E         ((uint8_t)0x02)
-#define RTC_TCR1_TAMPIE         ((uint8_t)0x01)
-
-/* Bits definition for RTC_TCR2 register*/
-#define RTC_TCR2_TAMPPUDIS         ((uint8_t)0x80)
-#define RTC_TCR2_TAMPPRCH          ((uint8_t)0x60)
-#define RTC_TCR2_TAMPFLT           ((uint8_t)0x18)
-#define RTC_TCR2_TAMPFREQ          ((uint8_t)0x07)
-
-
-/*RTC special defines */
-#define RTC_WPR_EnableKey        ((uint8_t)0xFF)
-#define RTC_WPR_DisableKey1      ((uint8_t)0xCA)
-#define RTC_WPR_DisableKey2      ((uint8_t)0x53)
-
-/**
-  * @}
-  */
-
-/**
-  * @brief CSS on LSE registers.
-  */
-typedef struct CSSLSE_struct
-{
-  __IO uint8_t CSR; /*!<  Control and Status Register*/
-}
-CSSLSE_TypeDef;
-
-/** @addtogroup CSSLSE_Registers_Reset_Value
-  * @{
-  */
-#define CSSLSE_CSR_RESET_VALUE       ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup CSSLSE_Registers_Bits_Definition
-  * @{
-  */
-
-/* Bits definition for CSSLSE_CSR register*/
-#define CSSLSE_CSR_SWITCHF            ((uint8_t)0x10)
-#define CSSLSE_CSR_CSSF               ((uint8_t)0x08)
-#define CSSLSE_CSR_CSSIE              ((uint8_t)0x04)
-#define CSSLSE_CSR_SWITCHEN           ((uint8_t)0x02)
-#define CSSLSE_CSR_CSSEN              ((uint8_t)0x01)
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief Beeper (BEEP) peripheral registers.
-  */
-
-typedef struct BEEP_struct
-{
-  __IO uint8_t CSR1; /*!< BEEP Control status register1 */
-  uint8_t RSERVED1;
-  uint8_t RESERVED2;
-  __IO uint8_t CSR2; /*!< BEEP Control status register2 */
-}
-BEEP_TypeDef;
-
-/** @addtogroup BEEP_Registers_Reset_Value
-  * @{
-  */
-#define BEEP_CSR1_RESET_VALUE ((uint8_t)0x00)
-#define BEEP_CSR2_RESET_VALUE ((uint8_t)0x1F)
-
-/**
-  * @}
-  */
-
-/** @addtogroup BEEP_Registers_Bits_Definition
-  * @{
-  */
-
-#define BEEP_CSR1_MSR     ((uint8_t)0x01) /*!< Measurement enable mask */
-
-#define BEEP_CSR2_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */
-#define BEEP_CSR2_BEEPEN  ((uint8_t)0x20) /*!< Beeper enable mask */
-#define BEEP_CSR2_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------ok*/
-
-/**
-  * @brief Configuration Registers (CFG)
-  */
-
-typedef struct CFG_struct
-{
-  __IO uint8_t GCR; /*!< Global Configuration register */
-}
-CFG_TypeDef;
-
-/** @addtogroup CFG_Registers_Reset_Value
-  * @{
-  */
-
-#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup CFG_Registers_Bits_Definition
-  * @{
-  */
-
-#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */
-#define CFG_GCR_AL  ((uint8_t)0x02) /*!< Activation Level bit mask */
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------ok*/
-
-/**
-  * @brief SYSCFG
-  */
-
-typedef struct SYSCFG_struct
-{
-  __IO uint8_t RMPCR3; /*!< Remap control register 3 */
-  __IO uint8_t RMPCR1; /*!< Remap control register 1 */
-  __IO uint8_t RMPCR2; /*!< Remap control register 2 */
-}
-SYSCFG_TypeDef;
-
-/** @addtogroup SYSCFG_Registers_Reset_Value
-  * @{
-  */
-#define SYSCFG_RMPCR1_RESET_VALUE ((uint8_t)0x0C)
-#define SYSCFG_RMPCR2_RESET_VALUE ((uint8_t)0x00)
-#define SYSCFG_RMPCR3_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup SYSCFG_Registers_Bits_Definition
-  * @{
-  */
-
-/* For DMA Channel Mapping*/
-#define SYSCFG_RMPCR1_ADC1DMA_REMAP     ((uint8_t)0x03) /*!< ADC1 DMA channel remapping */
-#define SYSCFG_RMPCR1_TIM4DMA_REMAP     ((uint8_t)0x0C) /*!< TIM4 DMA channel remapping */
-
-
-/* For GPIO Reapping*/
-#define SYSCFG_RMPCR1_USART1TR_REMAP    ((uint8_t)0x30) /*!< USART1_TX and USART1_RX remapping */
-#define SYSCFG_RMPCR1_USART1CK_REMAP    ((uint8_t)0x40) /*!< USART1_CK remapping */
-#define SYSCFG_RMPCR1_SPI1_REMAP        ((uint8_t)0x80) /*!< SPI1 remapping */
-
-#define SYSCFG_RMPCR2_ADC1TRIG_REMAP    ((uint8_t)0x01) /*!< ADC1 External Trigger remap */
-#define SYSCFG_RMPCR2_TIM2TRIG_REMAP    ((uint8_t)0x02) /*!< TIM2 Trigger remap */
-#define SYSCFG_RMPCR2_TIM3TRIG_REMAP1   ((uint8_t)0x04) /*!< TIM3 Trigger remap 1 */
-#define SYSCFG_RMPCR2_TIM2TRIG_LSE      ((uint8_t)0x08) /*!< TIM2 Trigger remap to LSE */
-#define SYSCFG_RMPCR2_TIM3TRIG_LSE      ((uint8_t)0x10) /*!< TIM3 Trigger remap to LSE */
-#define SYSCFG_RMPCR2_SPI2_REMAP        ((uint8_t)0x20) /*!< SPI2 remapping */
-#define SYSCFG_RMPCR2_TIM3TRIG_REMAP2   ((uint8_t)0x40) /*!< TIM3 Trigger remap 2 */
-#define SYSCFG_RMPCR2_TIM23BKIN_REMAP   ((uint8_t)0x80) /*!< TIM2 & TIM3 Break input remap */
-
-#define SYSCFG_RMPCR3_SPI1_REMAP        ((uint8_t)0x01) /*!< SPI1 remapping */
-#define SYSCFG_RMPCR3_USART3TR_REMAP    ((uint8_t)0x02) /*!< USART3_TX and USART3_RX remapping */
-#define SYSCFG_RMPCR3_USART3CK_REMAP    ((uint8_t)0x04) /*!< USART3_CK remapping */
-#define SYSCFG_RMPCR3_TIM3CH1_REMAP     ((uint8_t)0x08) /*!< TIM3 channel 1 remapping */
-#define SYSCFG_RMPCR3_TIM3CH2_REMAP     ((uint8_t)0x10) /*!< TIM3 channel 2 remapping */
-#define SYSCFG_RMPCR3_CCO_REMAP         ((uint8_t)0x20) /*!< CCO remapping */
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------ok*/
-
-/**
-  * @brief Clock Controller (CLK)
-  */
-typedef struct CLK_struct
-{
-  __IO uint8_t CKDIVR;      /*!< Clock Master Divider Register */
-  __IO uint8_t CRTCR;  /*!< RTC Clock selection Register */
-  __IO uint8_t ICKCR;     /*!< Internal Clocks Control Register */
-  __IO uint8_t PCKENR1;  /*!< Peripheral Clock Gating Register 1 */
-  __IO uint8_t PCKENR2;  /*!< Peripheral Clock Gating Register 2 */
-  __IO uint8_t CCOR;       /*!< Configurable Clock Output Register */
-  __IO uint8_t ECKCR;     /*!< External Clocks Control Register */
-  __IO uint8_t SCSR;     /*!< System clock status Register */
-  __IO uint8_t SWR;      /*!< System clock Switch Register */
-  __IO uint8_t SWCR;     /*!< Switch Control Register */
-  __IO uint8_t CSSR;     /*!< Clock Security Sytem Register */
-  __IO uint8_t CBEEPR;     /*!< Clock BEEP Register */
-  __IO uint8_t HSICALR;     /*!< HSI Calibration Register */
-  __IO uint8_t HSITRIMR; /*!< HSI clock Calibration Trimmer Register */
-  __IO uint8_t HSIUNLCKR; /*!< HSI Unlock  Register */
-  __IO uint8_t REGCSR;  /*!< Main regulator control status register */
-  __IO uint8_t PCKENR3;  /*!< Peripheral Clock Gating Register 3 */
-}
-CLK_TypeDef;
-
-/** @addtogroup CLK_Registers_Reset_Value
-  * @{
-  */
-#define CLK_CKDIVR_RESET_VALUE    ((uint8_t)0x03)
-#define CLK_CRTCR_RESET_VALUE     ((uint8_t)0x00)
-#define CLK_ICKCR_RESET_VALUE     ((uint8_t)0x11)
-#define CLK_PCKENR1_RESET_VALUE   ((uint8_t)0x00)
-#define CLK_PCKENR2_RESET_VALUE   ((uint8_t)0x80)
-#define CLK_PCKENR3_RESET_VALUE   ((uint8_t)0x00)
-#define CLK_CCOR_RESET_VALUE      ((uint8_t)0x00)
-#define CLK_ECKCR_RESET_VALUE     ((uint8_t)0x00)
-#define CLK_SCSR_RESET_VALUE      ((uint8_t)0x01)
-#define CLK_SWR_RESET_VALUE       ((uint8_t)0x01)
-#define CLK_SWCR_RESET_VALUE      ((uint8_t)0x00)
-#define CLK_CSSR_RESET_VALUE      ((uint8_t)0x00)
-#define CLK_CBEEPR_RESET_VALUE    ((uint8_t)0x00)
-#define CLK_HSICALR_RESET_VALUE   ((uint8_t)0x00)
-#define CLK_HSITRIMR_RESET_VALUE  ((uint8_t)0x00)
-#define CLK_HSIUNLCKR_RESET_VALUE ((uint8_t)0x00)
-#define CLK_REGCSR_RESET_VALUE    ((uint8_t)0xB9)
-/**
-  * @}
-  */
-
-/** @addtogroup CLK_Registers_Bits_Definition
-  * @{
-  */
-
-#define CLK_CKDIVR_CKM            ((uint8_t)0x07) /*!< System clock prescaler mask */
-
-#define CLK_CRTCR_RTCDIV          ((uint8_t)0xE0) /*!< RTC clock prescaler  mask*/
-#define CLK_CRTCR_RTCSEL          ((uint8_t)0x1E) /*!< RTC clock output selection  mask */
-#define CLK_CRTCR_RTCSWBSY        ((uint8_t)0x01) /*!< RTC clock switch busy */
-
-#define CLK_ICKCR_BEEPAHALT       ((uint8_t)0x40) /*!< BEEP clock Active Halt/Halt mode */
-#define CLK_ICKCR_FHWU            ((uint8_t)0x20) /*!< Fast Wake-up from Active Halt/Halt mode */
-#define CLK_ICKCR_SAHALT          ((uint8_t)0x10) /*!< Slow Active-halt mode */
-#define CLK_ICKCR_LSIRDY          ((uint8_t)0x08) /*!< Low speed internal RC oscillator ready */
-#define CLK_ICKCR_LSION           ((uint8_t)0x04) /*!< Low speed internal RC oscillator enable */
-#define CLK_ICKCR_HSIRDY          ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */
-#define CLK_ICKCR_HSION           ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */
-
-#define CLK_PCKENR1_TIM2          ((uint8_t)0x01) /*!< Timer 2 clock enable */
-#define CLK_PCKENR1_TIM3          ((uint8_t)0x02) /*!< Timer 3 clock enable */
-#define CLK_PCKENR1_TIM4          ((uint8_t)0x04) /*!< Timer 4 clock enable */
-#define CLK_PCKENR1_I2C1          ((uint8_t)0x08) /*!< I2C1 clock enable */
-#define CLK_PCKENR1_SPI1          ((uint8_t)0x10) /*!< SPI1 clock enable */
-#define CLK_PCKENR1_USART1        ((uint8_t)0x20) /*!< USART1 clock enable */
-#define CLK_PCKENR1_BEEP          ((uint8_t)0x40) /*!< BEEP clock enable */
-#define CLK_PCKENR1_DAC           ((uint8_t)0x80) /*!< DAC clock enable */
-
-#define CLK_PCKENR2_ADC1          ((uint8_t)0x01) /*!< ADC1 clock enable */
-#define CLK_PCKENR2_TIM1          ((uint8_t)0x02) /*!< TIM1 clock enable */
-#define CLK_PCKENR2_RTC           ((uint8_t)0x04) /*!< RTC clock enable */
-#define CLK_PCKENR2_LCD           ((uint8_t)0x08) /*!< LCD clock enable */
-#define CLK_PCKENR2_DMA1          ((uint8_t)0x10) /*!< DMA1 clock enable */
-#define CLK_PCKENR2_COMP          ((uint8_t)0x20) /*!< Comparator clock enable */
-#define CLK_PCKENR2_BOOTROM       ((uint8_t)0x80) /*!< Boot ROM clock enable */
-
-#define CLK_PCKENR3_AES           ((uint8_t)0x01) /*!< AES clock enable */
-#define CLK_PCKENR3_TIM5          ((uint8_t)0x02) /*!< Timer 5 clock enable */
-#define CLK_PCKENR3_SPI2          ((uint8_t)0x04) /*!< SPI2 clock enable */
-#define CLK_PCKENR3_UASRT2        ((uint8_t)0x08) /*!< USART2 clock enable */
-#define CLK_PCKENR3_USART3        ((uint8_t)0x10) /*!< USART3 clock enable */
-
-#define CLK_CCOR_CCODIV           ((uint8_t)0xE0) /*!< Configurable Clock output prescaler */
-#define CLK_CCOR_CCOSEL           ((uint8_t)0x1E) /*!< Configurable clock output selection */
-#define CLK_CCOR_CCOSWBSY         ((uint8_t)0x01) /*!< Configurable clock output switch busy  flag */
-
-#define CLK_ECKCR_LSEBYP          ((uint8_t)0x20) /*!< Low speed external clock bypass */
-#define CLK_ECKCR_HSEBYP          ((uint8_t)0x10) /*!< High speed external clock bypass */
-#define CLK_ECKCR_LSERDY          ((uint8_t)0x08) /*!< Low speed external crystal oscillator ready */
-#define CLK_ECKCR_LSEON           ((uint8_t)0x04) /*!< Low speed external crystal oscillator enable */
-#define CLK_ECKCR_HSERDY          ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */
-#define CLK_ECKCR_HSEON           ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */
-
-#define CLK_SCSR_CKM              ((uint8_t)0x0F) /*!< System clock status bits */
-
-#define CLK_SWR_SWI               ((uint8_t)0x0F) /*!< System clock selection bits */
-
-#define CLK_SWCR_SWIF             ((uint8_t)0x08) /*!< Clock switch interrupt flag */
-#define CLK_SWCR_SWIEN            ((uint8_t)0x04) /*!< Clock switch interrupt enable */
-#define CLK_SWCR_SWEN             ((uint8_t)0x02) /*!< Switch start/stop */
-#define CLK_SWCR_SWBSY            ((uint8_t)0x01) /*!< Switch busy */
-
-#define CLK_CSSR_CSSDGON          ((uint8_t)0x10) /*!< Clock security sytem deglitcher system */
-#define CLK_CSSR_CSSD             ((uint8_t)0x08) /*!< Clock security sytem detection */
-#define CLK_CSSR_CSSDIE           ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */
-#define CLK_CSSR_AUX              ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */
-#define CLK_CSSR_CSSEN            ((uint8_t)0x01) /*!< Clock security system enable */
-
-#define CLK_CBEEPR_CLKBEEPSEL     ((uint8_t)0x06) /*!< Configurable BEEP clock source selection */
-#define CLK_CBEEPR_BEEPSWBSY      ((uint8_t)0x01) /*!< BEEP clock busy in switch  */
-
-#define CLK_HSICALR_HSICAL        ((uint8_t)0xFF) /*!<  Copy of otpion byte trimming HSI oscillator */
-
-#define CLK_HSITRIMR_HSITRIM      ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer */
-
-#define CLK_HSIUNLCKR_HSIUNLCK    ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer unlock  */
-
-#define CLK_REGCSR_EEREADY        ((uint8_t)0x80) /*!< Flash program memory and Data EEPROM ready */
-#define CLK_REGCSR_EEBUSY         ((uint8_t)0x40) /*!< Flash program memory and Data EEPROM busy */
-#define CLK_REGCSR_LSEPD          ((uint8_t)0x20) /*!< LSE power-down */
-#define CLK_REGCSR_HSEPD          ((uint8_t)0x10) /*!< HSE power-down */
-#define CLK_REGCSR_LSIPD          ((uint8_t)0x08) /*!< LSI power-down */
-#define CLK_REGCSR_HSIPD          ((uint8_t)0x04) /*!< HSI power-down */
-#define CLK_REGCSR_REGOFF         ((uint8_t)0x02) /*!< Main regulator OFF */
-#define CLK_REGCSR_REGREADY       ((uint8_t)0x01) /*!< Main regulator ready */
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------ok*/
-
-/**
-  * @brief Comparator interface (COMP)
-  */
-
-typedef struct COMP_struct
-{
-  __IO uint8_t CSR1;   /*!< Control status register 1  */
-  __IO uint8_t CSR2;   /*!< Control status register 2  */
-  __IO uint8_t CSR3;   /*!< Control status register 3  */
-  __IO uint8_t CSR4;   /*!< Control status register 4  */
-  __IO uint8_t CSR5;   /*!< Control status register 5  */
-}
-COMP_TypeDef;
-
-
-/** @addtogroup COMP_Registers_Reset_Value
-  * @{
-  */
-#define COMP_CSR1_RESET_VALUE  ((uint8_t)0x00)
-#define COMP_CSR2_RESET_VALUE  ((uint8_t)0x00)
-#define COMP_CSR3_RESET_VALUE  ((uint8_t)0xC0)
-#define COMP_CSR4_RESET_VALUE  ((uint8_t)0x00)
-#define COMP_CSR5_RESET_VALUE  ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup COMP_Registers_Bits_Definition
-  * @{
-  */
-
-/* CSR1 */
-#define COMP_CSR1_IE1        ((uint8_t)0x20) /*!<  Comparator 1 Interrupt Enable Mask. */
-#define COMP_CSR1_EF1        ((uint8_t)0x10) /*!<  Comparator 1 Event Flag Mask. */
-#define COMP_CSR1_CMP1OUT    ((uint8_t)0x08) /*!<  Comparator 1 Ouptput Mask. */
-#define COMP_CSR1_STE        ((uint8_t)0x04) /*!<  Schmitt trigger enable Mask. */
-#define COMP_CSR1_CMP1       ((uint8_t)0x03) /*!<  Comparator 1 Configuration Mask. */
-
-/* CSR2 */
-#define COMP_CSR2_IE2        ((uint8_t)0x20) /*!<  Comparator 2 Interrupt Enable Mask. */
-#define COMP_CSR2_EF2        ((uint8_t)0x10) /*!<  Comparator 2 Event Flag Mask. */
-#define COMP_CSR2_CMP2OUT    ((uint8_t)0x08) /*!<  Comparator 2 Ouptput Mask. */
-#define COMP_CSR2_SPEED      ((uint8_t)0x04) /*!<  Comparator 2 speed modeMask. */
-#define COMP_CSR2_CMP2       ((uint8_t)0x03) /*!<  Comparator 2 Configuration Mask. */
-
-/* CSR3 */
-#define COMP_CSR3_OUTSEL     ((uint8_t)0xC0) /*!<  Comparator 2 output selection Mask. */
-#define COMP_CSR3_INSEL      ((uint8_t)0x38) /*!<  Inversion input selection Mask. */
-#define COMP_CSR3_VREFEN     ((uint8_t)0x04) /*!<  Internal reference voltage Enable Mask. */
-#define COMP_CSR3_WNDWE      ((uint8_t)0x02) /*!<  Window Mode Enable Mask. */
-#define COMP_CSR3_VREFOUTEN  ((uint8_t)0x01) /*!<  VREF Output Enable Mask. */
-
-/* CSR4 */
-#define COMP_CSR4_NINVTRIG   ((uint8_t)0x38) /*!<  COMP2 non-inverting input Mask. */
-#define COMP_CSR4_INVTRIG    ((uint8_t)0x07) /*!<  COMP2 inverting input Mask. */
-
-/* CSR5 */
-#define COMP_CSR5_DACTRIG    ((uint8_t)0x38) /*!<  DAC outputs Mask. */
-#define COMP_CSR5_VREFTRIG   ((uint8_t)0x07) /*!<  VREF outputs Mask. */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------ok*/
-
-/**
-  * @brief External Interrupt Controller (EXTI)
-  */
-typedef struct EXTI_struct
-{
-  __IO uint8_t CR1;           /*!<  The four LSB EXTI  pin sensitivity */
-  __IO uint8_t CR2;           /*!<  The four MSB EXTI  pin sensitivity */
-  __IO uint8_t CR3;           /*!<  EXTI port B & port D sensitivity */
-  __IO uint8_t SR1;           /*!<  Pins Status flag register 1 */
-  __IO uint8_t SR2;           /*!<  Ports Status flage register 2 */
-  __IO uint8_t CONF1;         /*!<  Port interrupt selector */
-  uint8_t RESERVED[4];  /*!<  reserved area */
-  __IO uint8_t CR4;           /*!<  EXTI port G & port H sensitivity */
-  __IO uint8_t CONF2;         /*!<  Port interrupt selector */
-}
-EXTI_TypeDef;
-
-/** @addtogroup EXTI_Registers_Reset_Value
-  * @{
-  */
-
-#define EXTI_CR1_RESET_VALUE   ((uint8_t)0x00)
-#define EXTI_CR2_RESET_VALUE   ((uint8_t)0x00)
-#define EXTI_CR3_RESET_VALUE   ((uint8_t)0x00)
-#define EXTI_CONF1_RESET_VALUE ((uint8_t)0x00)
-#define EXTI_SR1_RESET_VALUE   ((uint8_t)0x00)
-#define EXTI_SR2_RESET_VALUE   ((uint8_t)0x00)
-#define EXTI_CR4_RESET_VALUE   ((uint8_t)0x00)
-#define EXTI_CONF2_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup EXTI_Registers_Bits_Definition
-  * @{
-  */
-/* CR1 */
-#define EXTI_CR1_P3IS      ((uint8_t)0xC0) /*!< EXTI Pin 3 external interrupt sensitivity bit Mask */
-#define EXTI_CR1_P2IS      ((uint8_t)0x30) /*!< EXTI Pin 2 external interrupt sensitivity bit Mask */
-#define EXTI_CR1_P1IS      ((uint8_t)0x0C) /*!< EXTI Pin 1  external interrupt sensitivity bit Mask */
-#define EXTI_CR1_P0IS      ((uint8_t)0x03) /*!< EXTI Pin 0 external interrupt sensitivity bit Mask */
-
-/* CR2 */
-#define EXTI_CR2_P7IS      ((uint8_t)0xC0) /*!< EXTI Pin 7 external interrupt sensitivity bit Mask */
-#define EXTI_CR2_P6IS      ((uint8_t)0x30) /*!< EXTI Pin 6 external interrupt sensitivity bit Mask */
-#define EXTI_CR2_P5IS      ((uint8_t)0x0C) /*!< EXTI Pin 5  external interrupt sensitivity bit Mask */
-#define EXTI_CR2_P4IS      ((uint8_t)0x03) /*!< EXTI Pin 4 external interrupt sensitivity bit Mask */
-
-/* CR3 */
-#define EXTI_CR3_PBIS      ((uint8_t)0x03) /*!< EXTI PORTB external interrupt sensitivity bits Mask */
-#define EXTI_CR3_PDIS      ((uint8_t)0x0C) /*!< EXTI PORTD external interrupt sensitivity bits Mask */
-#define EXTI_CR3_PEIS      ((uint8_t)0x30) /*!< EXTI PORTE external interrupt sensitivity bits Mask */
-#define EXTI_CR3_PFIS      ((uint8_t)0xC0) /*!< EXTI PORTF external interrupt sensitivity bits Mask */
-
-/* CONF1 */
-#define EXTI_CONF1_PBLIS   ((uint8_t)0x01) /*!< EXTI PORTB low interrupt selector bit Mask */
-#define EXTI_CONF1_PBHIS   ((uint8_t)0x02) /*!< EXTI PORTB high interrupt selector bit Mask */
-#define EXTI_CONF1_PDLIS   ((uint8_t)0x04) /*!< EXTI PORTD low interrupt selector bit Mask */
-#define EXTI_CONF1_PDHIS   ((uint8_t)0x08) /*!< EXTI PORTD high interrupt selector bit Mask */
-#define EXTI_CONF1_PELIS   ((uint8_t)0x10) /*!< EXTI PORTE low interrupt selector bit Mask */
-#define EXTI_CONF1_PEHIS   ((uint8_t)0x20) /*!< EXTI PORTE high interrupt selector bit Mask */
-#define EXTI_CONF1_PFLIS   ((uint8_t)0x40) /*!< EXTI PORTF low interrupt selector bit Mask */
-#define EXTI_CONF1_PFES    ((uint8_t)0x80) /*!< EXTI PORTF or PORTE interrupt selector bit Mask */
-
-/* CR4 */
-#define EXTI_CR4_PGIS      ((uint8_t)0x03) /*!< EXTI PORTG external interrupt sensitivity bits Mask */
-#define EXTI_CR4_PHIS      ((uint8_t)0x0C) /*!< EXTI PORTH external interrupt sensitivity bits Mask */
-
-/* CONF2 */
-#define EXTI_CONF2_PFHIS   ((uint8_t)0x01) /*!< EXTI PORTF high interrupt selector bit Mask */
-#define EXTI_CONF2_PGLIS   ((uint8_t)0x02) /*!< EXTI PORTG low interrupt selector bit Mask */
-#define EXTI_CONF2_PGHIS   ((uint8_t)0x04) /*!< EXTI PORTG high interrupt selector bit Mask */
-#define EXTI_CONF2_PHLIS   ((uint8_t)0x08) /*!< EXTI PORTH low interrupt selector bit Mask */
-#define EXTI_CONF2_PHHIS   ((uint8_t)0x10) /*!< EXTI PORTH high interrupt selector bit Mask */
-#define EXTI_CONF2_PGBS    ((uint8_t)0x20) /*!< EXTI PORTB or PORTG interrupt selector bit Mask */
-#define EXTI_CONF2_PHDS    ((uint8_t)0x40) /*!< EXTI PORTD or PORTH interrupt selector bit Mask */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------ok*/
-
-/**
-  * @brief FLASH and Data EEPROM
-  */
-typedef struct FLASH_struct
-{
-  __IO uint8_t CR1;        /*!< Flash control register 1 */
-  __IO uint8_t CR2;        /*!< Flash control register 2 */
-  __IO uint8_t PUKR;       /*!< Flash program memory unprotection register */
-  __IO uint8_t DUKR;       /*!< Data EEPROM unprotection register */
-  __IO uint8_t IAPSR;      /*!< Flash in-application programming status register */
-}
-FLASH_TypeDef;
-
-/** @addtogroup FLASH_Registers_Reset_Value
-  * @{
-  */
-#define FLASH_CR1_RESET_VALUE    ((uint8_t)0x00)
-#define FLASH_CR2_RESET_VALUE    ((uint8_t)0x00)
-#define FLASH_PUKR_RESET_VALUE   ((uint8_t)0xAE)
-#define FLASH_DUKR_RESET_VALUE   ((uint8_t)0x56)
-#define FLASH_IAPSR_RESET_VALUE  ((uint8_t)0x40)
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Registers_Bits_Definition
-  * @{
-  */
-#define FLASH_CR1_EEPM           ((uint8_t)0x08) /*!< Flash low power selection during Run and Low power run mode Mask */
-#define FLASH_CR1_WAITM          ((uint8_t)0x04) /*!< Flash low power selection during Wait and Low power wait mode Mask */
-#define FLASH_CR1_IE             ((uint8_t)0x02) /*!< Flash Interrupt enable Mask */
-#define FLASH_CR1_FIX            ((uint8_t)0x01) /*!< Fix programming time Mask */
-
-#define FLASH_CR2_OPT            ((uint8_t)0x80) /*!< Enable write access to option bytes*/
-#define FLASH_CR2_WPRG           ((uint8_t)0x40) /*!< Word write once Mask */
-#define FLASH_CR2_ERASE          ((uint8_t)0x20) /*!< Erase block Mask */
-#define FLASH_CR2_FPRG           ((uint8_t)0x10) /*!< Fast programming mode Mask */
-#define FLASH_CR2_PRG            ((uint8_t)0x01) /*!< Program block Mask */
-
-#define FLASH_IAPSR_HVOFF        ((uint8_t)0x40) /*!< End of high voltage flag Mask */
-#define FLASH_IAPSR_DUL          ((uint8_t)0x08) /*!< Data EEPROM unlocked flag Mask */
-#define FLASH_IAPSR_EOP          ((uint8_t)0x04) /*!< End of operation flag Mask */
-#define FLASH_IAPSR_PUL          ((uint8_t)0x02) /*!< Program memory unlocked flag Mask */
-#define FLASH_IAPSR_WR_PG_DIS    ((uint8_t)0x01) /*!< Write attempted to protected page Mask */
-
-#define FLASH_PUKR_PUK           ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */
-
-#define FLASH_DUKR_DUK           ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */
-
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief Inter-Integrated Circuit (I2C)
-  */
-typedef struct I2C_struct
-{
-  __IO uint8_t CR1;    /*!< I2C control register 1 */
-  __IO uint8_t CR2;    /*!< I2C control register 2 */
-  __IO uint8_t FREQR;  /*!< I2C frequency register */
-  __IO uint8_t OARL;   /*!< I2C own address register 1 LSB */
-  __IO uint8_t OARH;   /*!< I2C own address register 1 MSB */
-  __IO uint8_t OAR2;   /*!< I2C own address register 2 */
-  __IO uint8_t DR;     /*!< I2C data register */
-  __IO uint8_t SR1;    /*!< I2C status register 1 */
-  __IO uint8_t SR2;    /*!< I2C status register 2 */
-  __IO uint8_t SR3;    /*!< I2C status register 3 */
-  __IO uint8_t ITR;    /*!< I2C interrupt & DMA register */
-  __IO uint8_t CCRL;   /*!< I2C clock control register low */
-  __IO uint8_t CCRH;   /*!< I2C clock control register high */
-  __IO uint8_t TRISER; /*!< I2C maximum rise time register */
-  __IO uint8_t PECR;   /*!< I2CPacket Error Checking register */
-}
-I2C_TypeDef;
-
-/** @addtogroup I2C_Registers_Reset_Value
-  * @{
-  */
-#define I2C_CR1_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_CR2_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_FREQR_RESET_VALUE  ((uint8_t)0x00)
-#define I2C_OARL_RESET_VALUE   ((uint8_t)0x00)
-#define I2C_OARH_RESET_VALUE   ((uint8_t)0x00)
-#define I2C_OAR2_RESET_VALUE   ((uint8_t)0x00)
-#define I2C_DR_RESET_VALUE     ((uint8_t)0x00)
-#define I2C_SR1_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_SR2_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_SR3_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_ITR_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_CCRL_RESET_VALUE   ((uint8_t)0x00)
-#define I2C_CCRH_RESET_VALUE   ((uint8_t)0x00)
-#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
-#define I2C_PECR_RESET_VALUE   ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Registers_Bits_Definition
-  * @{
-  */
-
-#define I2C_CR1_NOSTRETCH   ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_ENGC        ((uint8_t)0x40) /*!< General Call Enable */
-#define I2C_CR1_ENPEC       ((uint8_t)0x20) /*!< PEC Enable */
-#define I2C_CR1_ARP         ((uint8_t)0x10) /*!< ARP Enable */
-#define I2C_CR1_SMBTYPE     ((uint8_t)0x08) /*!< SMBus type */
-#define I2C_CR1_SMBUS       ((uint8_t)0x02) /*!< SMBus mode */
-#define I2C_CR1_PE          ((uint8_t)0x01) /*!< Peripheral Enable */
-
-#define I2C_CR2_SWRST       ((uint8_t)0x80) /*!< Software Reset */
-#define I2C_CR2_ALERT       ((uint8_t)0x20) /*!< SMBus Alert*/
-#define I2C_CR2_PEC         ((uint8_t)0x10) /*!< Packet Error Checking */
-#define I2C_CR2_POS         ((uint8_t)0x08) /*!< Acknowledge */
-#define I2C_CR2_ACK         ((uint8_t)0x04) /*!< Acknowledge Enable */
-#define I2C_CR2_STOP        ((uint8_t)0x02) /*!< Stop Generation */
-#define I2C_CR2_START       ((uint8_t)0x01) /*!< Start Generation */
-
-#define I2C_FREQR_FREQ      ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */
-
-#define I2C_OARL_ADD        ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */
-#define I2C_OARL_ADD0       ((uint8_t)0x01) /*!< Interface Address bit0 */
-
-#define I2C_OARH_ADDMODE    ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */
-#define I2C_OARH_ADDCONF    ((uint8_t)0x40) /*!< Address mode configuration */
-#define I2C_OARH_ADD        ((uint8_t)0x06) /*!< Interface Address bits [9..8] */
-
-#define I2C_OAR2_ADD2       ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */
-#define I2C_OAR2_ENDUAL     ((uint8_t)0x01) /*!< Dual addressing mode enable */
-
-#define I2C_DR_DR           ((uint8_t)0xFF) /*!< Data Register */
-
-#define I2C_SR1_TXE         ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_RXNE        ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_STOPF       ((uint8_t)0x10) /*!< Stop detection (Slave mode) */
-#define I2C_SR1_ADD10       ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_BTF         ((uint8_t)0x04) /*!< Byte Transfer Finished */
-#define I2C_SR1_ADDR        ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_SB          ((uint8_t)0x01) /*!< Start Bit (Master mode) */
-
-#define I2C_SR2_SMBALERT    ((uint8_t)0x80) /*!< SMBus Alert */
-#define I2C_SR2_TIMEOUT     ((uint8_t)0x40) /*!< Time out or TLow error */
-#define I2C_SR2_WUFH        ((uint8_t)0x20) /*!< Wake-up from Halt */
-#define I2C_SR2_PECERR      ((uint8_t)0x10) /*!< PEC error in reception */
-#define I2C_SR2_OVR         ((uint8_t)0x08) /*!< Overrun/Underrun */
-#define I2C_SR2_AF          ((uint8_t)0x04) /*!< Acknowledge Failure */
-#define I2C_SR2_ARLO        ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */
-#define I2C_SR2_BERR        ((uint8_t)0x01) /*!< Bus Error */
-
-#define I2C_SR3_DUALF       ((uint8_t)0x80) /*!< Dual flag (Slave mode) */
-#define I2C_SR3_SMBHOST     ((uint8_t)0x40) /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR3_SMBDEFAULT  ((uint8_t)0x20) /*!< SMBus Default Header (Slave mode) */
-#define I2C_SR3_GENCALL     ((uint8_t)0x10) /*!< General Call Header (Slave mode) */
-#define I2C_SR3_TRA         ((uint8_t)0x04) /*!< Transmitter/Receiver */
-#define I2C_SR3_BUSY        ((uint8_t)0x02) /*!< Bus Busy */
-#define I2C_SR3_MSL         ((uint8_t)0x01) /*!< Master/Slave */
-
-#define I2C_ITR_LAST        ((uint8_t)0x10) /*!< DMA Last transfer */
-#define I2C_ITR_DMAEN       ((uint8_t)0x08) /*!< DMA request Enable */
-#define I2C_ITR_ITBUFEN     ((uint8_t)0x04) /*!< Buffer Interrupt Enable */
-#define I2C_ITR_ITEVTEN     ((uint8_t)0x02) /*!< Event Interrupt Enable */
-#define I2C_ITR_ITERREN     ((uint8_t)0x01) /*!< Error Interrupt Enable */
-
-#define I2C_CCRL_CCR        ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */
-
-#define I2C_CCRH_FS         ((uint8_t)0x80) /*!< Master Mode Selection */
-#define I2C_CCRH_DUTY       ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */
-#define I2C_CCRH_CCR        ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */
-
-#define I2C_TRISER_TRISE    ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-#define I2C_PECR_PEC        ((uint8_t)0xFF) /*!< Packet error checking */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief IR digital interface (IRTIM)
-  */
-typedef struct IRTIM_struct
-{
-  __IO uint8_t CR; /*!< control register */
-}
-IRTIM_TypeDef;
-/** @addtogroup IRTIM_Registers_Reset_Value
-  * @{
-  */
-#define IRTIM_CR_RESET_VALUE    ((uint8_t)0x00)
-
-
-/**
-* @}
-*/
-
-/** @addtogroup IRTIM_Registers_Bits_Definition
-  * @{
-  */
-/* CR*/
-#define IRTIM_CR_EN     ((uint8_t)0x01) /*!< IRTIM_OUT enable Mask. */
-#define IRTIM_CR_HSEN   ((uint8_t)0x02) /*!< High sink open drain buffer enable Mask */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief Interrupt Controller (ITC)
-  */
-typedef struct ITC_struct
-{
-  __IO uint8_t ISPR1; /*!<  Interrupt Software Priority register 1 */
-  __IO uint8_t ISPR2; /*!<  Interrupt Software Priority register 2 */
-  __IO uint8_t ISPR3; /*!<  Interrupt Software Priority register 3 */
-  __IO uint8_t ISPR4; /*!<  Interrupt Software Priority register 4 */
-  __IO uint8_t ISPR5; /*!<  Interrupt Software Priority register 5 */
-  __IO uint8_t ISPR6; /*!<  Interrupt Software Priority register 6 */
-  __IO uint8_t ISPR7; /*!<  Interrupt Software Priority register 7 */
-  __IO uint8_t ISPR8; /*!<  Interrupt Software Priority register 8 */
-}
-ITC_TypeDef;
-
-/** @addtogroup ITC_Registers_Reset_Value
-  * @{
-  */
-#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers 0 to 7 */
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief Internal Low Speed Watchdog (IWDG)
-  */
-typedef struct IWDG_struct
-{
-  __IO uint8_t KR;  /*!<  Low Speed Watchdog Key Register */
-  __IO uint8_t PR;  /*!<  Low Speed Watchdog Prescaler Register */
-  __IO uint8_t RLR; /*!<  Low Speed Watchdog Reload Register */
-}
-IWDG_TypeDef;
-
-/** @addtogroup IWDG_Registers_Reset_Value
-  * @{
-  */
-#define IWDG_RLR_RESET_VALUE    ((uint8_t)0xFF)  /*! <Reload Register Default Value */
-#define IWDG_PR_RESET_VALUE     ((uint8_t)0x00)  /*! <Prescaler Register Default Value */
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-
-
-/**
-  * @brief Wait For Event (WFE) peripheral registers.
-  */
-/** @addtogroup WFE_Registers
-  * @{
-  */
-typedef struct WFE_struct
-{
-  __IO uint8_t CR1;  /*!<  Wait for event control register 1 */
-  __IO uint8_t CR2;  /*!<  Wait for event control register 2 */
-  __IO uint8_t CR3;  /*!<  Wait for event control register 3 */
-  __IO uint8_t CR4;  /*!<  Wait for event control register 4 */
-}
-WFE_TypeDef;
-/**
-  * @}
-  */
-/** @addtogroup WFE_Registers_Reset_Value
-  * @{
-  */
-
-#define WFE_CRX_RESET_VALUE ((uint8_t)0x00) /*!< Reset value wait for event control register */
-/**
-  * @}
-  */
-
-/** @addtogroup WFE_Registers_Bits_Definition
-  * @{
-  */
-
-#define WFE_CR1_EXTI_EV3      ((uint8_t)0x80)  /*!< External interrupt event 3 Mask */
-#define WFE_CR1_EXTI_EV2      ((uint8_t)0x40)  /*!< External interrupt event 2 Mask */
-#define WFE_CR1_EXTI_EV1      ((uint8_t)0x20)  /*!< External interrupt event 1 Mask */
-#define WFE_CR1_EXTI_EV0      ((uint8_t)0x10)  /*!< External interrupt event 0 Mask */
-#define WFE_CR1_TIM1_EV1      ((uint8_t)0x08)  /*!< TIM1 event 1 Mask */
-#define WFE_CR1_TIM1_EV0      ((uint8_t)0x04)  /*!< TIM1 event 0 Mask */
-#define WFE_CR1_TIM2_EV1      ((uint8_t)0x02)  /*!< TIM2 event 1 Mask */
-#define WFE_CR1_TIM2_EV0      ((uint8_t)0x01)  /*!< TIM2 event 0 Mask */
-
-#define WFE_CR2_ADC1_COMP_EV  ((uint8_t)0x80)  /*!< ADC / COMP event Mask*/
-#define WFE_CR2_EXTI_EVEF     ((uint8_t)0x40)  /*!< External interrupt event on Port E or Port F Mask */
-#define WFE_CR2_EXTI_EVDH     ((uint8_t)0x20)  /*!< External interrupt event on Port D or Port H Mask */
-#define WFE_CR2_EXTI_EVBG     ((uint8_t)0x10)  /*!< External interrupt event on Port B or Port G Mask */
-#define WFE_CR2_EXTI_EV7      ((uint8_t)0x08)  /*!< External interrupt event 7 Mask */
-#define WFE_CR2_EXTI_EV6      ((uint8_t)0x04)  /*!< External interrupt event 6 Mask */
-#define WFE_CR2_EXTI_EV5      ((uint8_t)0x02)  /*!< External interrupt event 5 Mask */
-#define WFE_CR2_EXTI_EV4      ((uint8_t)0x01)  /*!< External interrupt event 4 Mask */
-
-#define WFE_CR3_DMA1CH23_EV   ((uint8_t)0x80)  /*!< DMA1 channel 2 and 3 interrupt event Mask */
-#define WFE_CR3_DMA1CH01_EV   ((uint8_t)0x40)  /*!< DMA1 channel 0 and 1 interrupt event Mask */
-#define WFE_CR3_USART1_EV     ((uint8_t)0x20)  /*!< USART1 Rx and Tx interrupt event Mask */
-#define WFE_CR3_I2C1_EV       ((uint8_t)0x10)  /*!< I2C1 Rx and Tx interrupt event Mask */
-#define WFE_CR3_SPI1_EV       ((uint8_t)0x08)  /*!< SPI1 Rx and Tx interrupt event Mask */
-#define WFE_CR3_TIM4_EV       ((uint8_t)0x04)  /*!< TIM4 event Mask */
-#define WFE_CR3_TIM3_EV1      ((uint8_t)0x02)  /*!< TIM3 event 1 Mask */
-#define WFE_CR3_TIM3_EV0      ((uint8_t)0x01)  /*!< TIM3 event 0 Mask */
-
-#define WFE_CR4_AES_EV        ((uint8_t)0x40)  /*!< AES event Mask */
-#define WFE_CR4_TIM5_EV1      ((uint8_t)0x20)  /*!< TIM5 event 1 Mask */
-#define WFE_CR4_TIM5_EV0      ((uint8_t)0x10)  /*!< TIM5 event 0 Mask */
-#define WFE_CR4_USART3_EV     ((uint8_t)0x08)  /*!< USART3 Rx and Tx interrupt event Mask */
-#define WFE_CR4_USART2_EV     ((uint8_t)0x04)  /*!< USART2 Rx and Tx interrupt event Mask */
-#define WFE_CR4_SPI2_EV       ((uint8_t)0x02)  /*!< SPI2 Rx and Tx interrupt event Mask */
-#define WFE_CR4_RTC_CSS_EV    ((uint8_t)0x01)  /*!< RTC or CSS on LSE interrupt event Mask */
-
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief Option Bytes (OPT)
-  */
-typedef struct OPT_struct
-{
-  __IO uint8_t ROP;        /*!< Read-out protection*/
-  uint8_t  RESERVED1;
-  __IO uint8_t UBC;        /*!< User Boot code size*/
-  uint8_t  RESERVED2;
-  uint8_t  RESERVED3;
-  uint8_t  RESERVED4;
-  uint8_t  RESERVED5;
-  __IO uint8_t PCODESIZE;
-  __IO uint8_t WDG;        /*!< Independent and Window watchdog option */
-  __IO uint8_t XTSTARTUP;  /*!< HSE and LSE option */
-  __IO uint8_t BOR;        /*!< Brownout option */
-}
-OPT_TypeDef;
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief Reset Controller (RST)
-  */
-typedef struct RST_struct
-{
-  __IO uint8_t CR;  /*!< Multiplex Reset Pad */
-  __IO uint8_t SR;  /*!< Reset status register */
-
-}
-RST_TypeDef;
-/**
-  * @}
-  */
-
-/** @addtogroup RST_Registers_Reset_Value
-  * @{
-  */
-
-#define RST_CR_RESET_VALUE    ((uint8_t)0x00) /*!< Reset pin configuration register  1 reset value */
-#define RST_SR_RESET_VALUE    ((uint8_t)0x01) /*!< Reset status register 2 reset value */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RST_Registers_Bits_Definition
-  * @{
-  */
-#define RST_SR_BORF           ((uint8_t)0x20) /*!< Brownout reset flag mask           */
-#define RST_SR_WWDGF          ((uint8_t)0x10) /*!< Window Watchdog reset flag mask */
-#define RST_SR_SWIMF          ((uint8_t)0x08) /*!< SWIM reset flag mask            */
-#define RST_SR_ILLOPF         ((uint8_t)0x04) /*!< Illegal opcode reset flag mask    */
-#define RST_SR_IWDGF          ((uint8_t)0x02) /*!< Independent Watchdog reset flag mask    */
-#define RST_SR_PORF           ((uint8_t)0x01) /*!< Power On Reset (POR) flag mask    */
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief Power Control (PWR)
-  */
-typedef struct PWR_struct
-{
-  __IO uint8_t CSR1;          /*!< PWR control status register 1 */
-  __IO uint8_t CSR2;          /*!< PWR control status register 2 */
-
-}
-PWR_TypeDef;
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Registers_Reset_Value
-  * @{
-  */
-
-#define PWR_CSR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Status Register 1 reset value */
-#define PWR_CSR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Status Register 2 reset value */
-
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Registers_Bits_Definition
-  * @{
-  */
-#define PWR_CSR1_PVDOF          ((uint8_t)0x40) /*!< PVD output flag mask         */
-#define PWR_CSR1_PVDIF          ((uint8_t)0x20) /*!< PVD interrupt flag mask */
-#define PWR_CSR1_PVDIEN         ((uint8_t)0x10) /*!< PVD interrupt enable mask            */
-#define PWR_CSR1_PLS            ((uint8_t)0x0E) /*!< PVD Level thresholds selector mask    */
-#define PWR_CSR1_PVDE           ((uint8_t)0x01) /*!< Power Voltage Detector (PVD) enable mask */
-
-
-#define PWR_CSR2_FWU            ((uint8_t)0x04) /*!< Fast wake up configuration mask */
-#define PWR_CSR2_ULP            ((uint8_t)0x02) /*!< Ultra Low power configuration mask  */
-#define PWR_CR2_VREFINTF        ((uint8_t)0x01) /*!< Internal reference voltage status flag mask  */
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief Routing Interface (RI)
-  */
-typedef struct RI_struct
-{
-  uint8_t RESERVED;
-  __IO uint8_t ICR1;   /*!< Timer input capture routing register 1 */
-  __IO uint8_t ICR2;   /*!< Timer input capture routing register 2 */
-  __IO uint8_t IOIR1;  /*!< I/O input register 1 */
-  __IO uint8_t IOIR2;  /*!< I/O input register 2 */
-  __IO uint8_t IOIR3;  /*!< I/O input register 3 */
-  __IO uint8_t IOCMR1; /*!< I/O control mode register 1 */
-  __IO uint8_t IOCMR2; /*!< I/O control mode register 2 */
-  __IO uint8_t IOCMR3; /*!< I/O control mode register 3 */
-  __IO uint8_t IOSR1;  /*!< I/O switch register 1*/
-  __IO uint8_t IOSR2;  /*!< I/O switch register 2*/
-  __IO uint8_t IOSR3;  /*!< I/O switch register 3*/
-  __IO uint8_t IOGCR;  /*!< I/O group control register */
-  __IO uint8_t ASCR1;  /*!< Analog Switch Control register 1 */
-  __IO uint8_t ASCR2;  /*!< Analog Switch Control register 2 */
-  __IO uint8_t RCR;    /*!< Resistor control register  */
-  uint8_t RESERVED1[16];
-  __IO uint8_t CR;     /*!< Control Register  */
-  __IO uint8_t IOMR1;   /*!< IO Mask Register 1 */
-  __IO uint8_t IOMR2;   /*!< IO Mask Register 2 */
-  __IO uint8_t IOMR3;   /*!< IO Mask Register 3 */
-  __IO uint8_t IOMR4;   /*!< IO Mask Register 4*/
-  __IO uint8_t IOIR4;  /*!< I/O input register 4 */
-  __IO uint8_t IOCMR4; /*!< I/O control mode register 4 */
-  __IO uint8_t IOSR4;  /*!< I/O switch register 4 */
-}RI_TypeDef;
-/**
-  * @}
-  */
-
-/** @addtogroup RI_Registers_Reset_Value
-  * @{
-  */
-
-#define RI_ICR1_RESET_VALUE     ((uint8_t)0x00) /*!< Timer input capture routing register 1 reset value */
-#define RI_ICR2_RESET_VALUE     ((uint8_t)0x00) /*!< Timer input capture routing register 2 reset value */
-
-#define RI_IOCMR1_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 1 reset value */
-#define RI_IOCMR2_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 2 reset value */
-#define RI_IOCMR3_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 3 reset value */
-
-#define RI_IOSR1_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 1 reset value */
-#define RI_IOSR2_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 2 reset value */
-#define RI_IOSR3_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 3 reset value */
-
-#define RI_IOGCR_RESET_VALUE    ((uint8_t)0xFF) /*!< IO group control register reset value */
-
-#define RI_ASCR1_RESET_VALUE    ((uint8_t)0x00) /*!< Analog switch register 1 reset value */
-#define RI_ASCR2_RESET_VALUE    ((uint8_t)0x00) /*!< Analog switch register 2 reset value */
-#define RI_RCR_RESET_VALUE      ((uint8_t)0x00) /*!< Resistor control register reset value */
-
-#define RI_IOCMR4_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 4 reset value */
-#define RI_IOSR4_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 4 reset value */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RI_Registers_Bits_Definition
-  * @{
-  */
-#define RI_ICR1_IC2CS          ((uint8_t)0x1F) /*!< TIM1 Input Capture 2 I/O selection mask */
-
-#define RI_ICR2_IC3CS          ((uint8_t)0x1F) /*!< TIM1 Input Capture 3 I/O selection mask */
-
-#define RI_IOIR1_CH1I          ((uint8_t)0x01) /*!< Channel 1 I/O pin input value */
-#define RI_IOIR1_CH4I          ((uint8_t)0x02) /*!< Channel 4 I/O pin input value */
-#define RI_IOIR1_CH7I          ((uint8_t)0x04) /*!< Channel 7 I/O pin input value */
-#define RI_IOIR1_CH10I         ((uint8_t)0x08) /*!< Channel 10 I/O pin input value */
-#define RI_IOIR1_CH13I         ((uint8_t)0x10) /*!< Channel 13 I/O pin input value */
-#define RI_IOIR1_CH16I         ((uint8_t)0x20) /*!< Channel 16 I/O pin input value */
-#define RI_IOIR1_CH19I         ((uint8_t)0x40) /*!< Channel 19 I/O pin input value */
-#define RI_IOIR1_CH22I         ((uint8_t)0x80) /*!< Channel 22 I/O pin input value */
-
-#define RI_IOIR2_CH2I          ((uint8_t)0x01) /*!< Channel 2 I/O pin input value */
-#define RI_IOIR2_CH5I          ((uint8_t)0x02) /*!< Channel 5 I/O pin input value */
-#define RI_IOIR2_CH8I          ((uint8_t)0x04) /*!< Channel 8 I/O pin input value */
-#define RI_IOIR2_CH11I         ((uint8_t)0x08) /*!< Channel 11 I/O pin input value */
-#define RI_IOIR2_CH14I         ((uint8_t)0x10) /*!< Channel 14 I/O pin input value */
-#define RI_IOIR2_CH17I         ((uint8_t)0x20) /*!< Channel 17 I/O pin input value */
-#define RI_IOIR2_CH20I         ((uint8_t)0x40) /*!< Channel 20 I/O pin input value */
-#define RI_IOIR2_CH23I         ((uint8_t)0x80) /*!< Channel 23 I/O pin input value */
-
-#define RI_IOIR3_CH3I          ((uint8_t)0x01) /*!< Channel 3 I/O pin input value */
-#define RI_IOIR3_CH6I          ((uint8_t)0x02) /*!< Channel 6 I/O pin input value */
-#define RI_IOIR3_CH9I          ((uint8_t)0x04) /*!< Channel 9 I/O pin input value */
-#define RI_IOIR3_CH12I         ((uint8_t)0x08) /*!< Channel 12 I/O pin input value */
-#define RI_IOIR3_CH15I         ((uint8_t)0x10) /*!< Channel 15 I/O pin input value */
-#define RI_IOIR3_CH18I         ((uint8_t)0x20) /*!< Channel 18 I/O pin input value */
-#define RI_IOIR3_CH21I         ((uint8_t)0x40) /*!< Channel 21 I/O pin input value */
-#define RI_IOIR3_CH24I         ((uint8_t)0x80) /*!< Channel 24 I/O pin input value */
-
-#define RI_IOCMR1_CH1M          ((uint8_t)0x01) /*!< Channel 1 I/O control mode */
-#define RI_IOCMR1_CH4M          ((uint8_t)0x02) /*!< Channel 4 I/O control mode */
-#define RI_IOCMR1_CH7M          ((uint8_t)0x04) /*!< Channel 7 I/O control mode */
-#define RI_IOCMR1_CH10M         ((uint8_t)0x08) /*!< Channel 10 I/O control mode */
-#define RI_IOCMR1_CH13M         ((uint8_t)0x10) /*!< Channel 13 I/O control mode */
-#define RI_IOCMR1_CH16M         ((uint8_t)0x20) /*!< Channel 16 I/O control mode */
-#define RI_IOCMR1_CH19M         ((uint8_t)0x40) /*!< Channel 19 I/O control mode */
-#define RI_IOCMR1_CH22M         ((uint8_t)0x80) /*!< Channel 22 I/O control mode */
-
-#define RI_IOCMR2_CH2M          ((uint8_t)0x01) /*!< Channel 2 I/O control mode */
-#define RI_IOCMR2_CH5M          ((uint8_t)0x02) /*!< Channel 5 I/O control mode */
-#define RI_IOCMR2_CH8M          ((uint8_t)0x04) /*!< Channel 8 I/O control mode */
-#define RI_IOCMR2_CH11M         ((uint8_t)0x08) /*!< Channel 11 I/O control mode */
-#define RI_IOCMR2_CH14M         ((uint8_t)0x10) /*!< Channel 14 I/O control mode */
-#define RI_IOCMR2_CH17M         ((uint8_t)0x20) /*!< Channel 17 I/O control mode */
-#define RI_IOCMR2_CH20M         ((uint8_t)0x40) /*!< Channel 20 I/O control mode */
-#define RI_IOCMR2_CH23M         ((uint8_t)0x80) /*!< Channel 23 I/O control mode */
-
-#define RI_IOCMR3_CH3M          ((uint8_t)0x01) /*!< Channel 3 I/O control mode */
-#define RI_IOCMR3_CH6M          ((uint8_t)0x02) /*!< Channel 6 I/O control mode */
-#define RI_IOCMR3_CH9M          ((uint8_t)0x04) /*!< Channel 9 I/O control mode */
-#define RI_IOCMR3_CH12M         ((uint8_t)0x08) /*!< Channel 12 I/O control mode */
-#define RI_IOCMR3_CH15M         ((uint8_t)0x10) /*!< Channel 15 I/O control mode */
-#define RI_IOCMR3_CH18M         ((uint8_t)0x20) /*!< Channel 18 I/O control mode */
-#define RI_IOCMR3_CH21M         ((uint8_t)0x40) /*!< Channel 21 I/O control mode */
-#define RI_IOCMR3_CH24M         ((uint8_t)0x80) /*!< Channel 24 I/O control mode */
-
-#define RI_IOSR1_CH1E          ((uint8_t)0x01) /*!< Channel 1 I/O switch control */
-#define RI_IOSR1_CH4E          ((uint8_t)0x02) /*!< Channel 4 I/O switch control */
-#define RI_IOSR1_CH7E          ((uint8_t)0x04) /*!< Channel 7 I/O switch control */
-#define RI_IOSR1_CH10E         ((uint8_t)0x08) /*!< Channel 10 I/O switch control */
-#define RI_IOSR1_CH13E         ((uint8_t)0x10) /*!< Channel 13 I/O switch control */
-#define RI_IOSR1_CH16E         ((uint8_t)0x20) /*!< Channel 16 I/O switch control */
-#define RI_IOSR1_CH19E         ((uint8_t)0x40) /*!< Channel 19 I/O switch control */
-#define RI_IOSR1_CH22E         ((uint8_t)0x80) /*!< Channel 22 I/O switch control */
-
-#define RI_IOSR2_CH2E          ((uint8_t)0x01) /*!< Channel 2 I/O switch control */
-#define RI_IOSR2_CH5E          ((uint8_t)0x02) /*!< Channel 5 I/O switch control */
-#define RI_IOSR2_CH8E          ((uint8_t)0x04) /*!< Channel 8 I/O switch control */
-#define RI_IOSR2_CH11E         ((uint8_t)0x08) /*!< Channel 11 I/O switch control */
-#define RI_IOSR2_CH14E         ((uint8_t)0x10) /*!< Channel 14 I/O switch control */
-#define RI_IOSR2_CH17E         ((uint8_t)0x20) /*!< Channel 17 I/O switch control */
-#define RI_IOSR2_CH20E         ((uint8_t)0x40) /*!< Channel 20 I/O switch control */
-#define RI_IOSR2_CH23E         ((uint8_t)0x80) /*!< Channel 23 I/O switch control */
-
-#define RI_IOSR3_CH3E          ((uint8_t)0x01) /*!< Channel 3 I/O switch control */
-#define RI_IOSR3_CH6E          ((uint8_t)0x02) /*!< Channel 6 I/O switch control */
-#define RI_IOSR3_CH9E          ((uint8_t)0x04) /*!< Channel 9 I/O switch control */
-#define RI_IOSR3_CH12E         ((uint8_t)0x08) /*!< Channel 12 I/O switch control */
-#define RI_IOSR3_CH15E         ((uint8_t)0x10) /*!< Channel 15 I/O switch control */
-#define RI_IOSR3_CH18E         ((uint8_t)0x20) /*!< Channel 18 I/O switch control */
-#define RI_IOSR3_CH21E         ((uint8_t)0x40) /*!< Channel 21 I/O switch control */
-#define RI_IOSR3_CH24E         ((uint8_t)0x80) /*!< Channel 24 I/O switch control */
-
-#define RI_IOGCR_IOM1          ((uint8_t)0x03) /*!< I/O mode 1 */
-#define RI_IOGCR_IOM2          ((uint8_t)0x0C) /*!< I/O mode 2 */
-#define RI_IOGCR_IOM3          ((uint8_t)0x30) /*!< I/O mode 3 */
-#define RI_IOGCR_IOM4          ((uint8_t)0xC0) /*!< I/O mode 4 */
-
-#define RI_ASCR1_AS0           ((uint8_t)0x01) /*!< Analog switch AS0 control */
-#define RI_ASCR1_AS1           ((uint8_t)0x02) /*!< Analog switch AS1 control */
-#define RI_ASCR1_AS2           ((uint8_t)0x04) /*!< Analog switch AS2 control */
-#define RI_ASCR1_AS3           ((uint8_t)0x08) /*!< Analog switch AS3 control */
-#define RI_ASCR1_AS4           ((uint8_t)0x10) /*!< Analog switch AS4 control */
-#define RI_ASCR1_AS5           ((uint8_t)0x20) /*!< Analog switch AS5 control */
-#define RI_ASCR1_AS6           ((uint8_t)0x40) /*!< Analog switch AS6 control */
-#define RI_ASCR1_AS7           ((uint8_t)0x80) /*!< Analog switch AS7 control */
-
-#define RI_ASCR2_AS8           ((uint8_t)0x01) /*!< Analog switch AS8 control */
-#define RI_ASCR2_AS9           ((uint8_t)0x02) /*!< Analog switch AS9 control */
-#define RI_ASCR2_AS10          ((uint8_t)0x04) /*!< Analog switch AS10 control */
-#define RI_ASCR2_AS11          ((uint8_t)0x08) /*!< Analog switch AS11 control */
-#define RI_ASCR2_AS14          ((uint8_t)0x40) /*!< Analog switch AS14 control */
-
-#define RI_RCR_400KPD          ((uint8_t)0x08) /*!< 400K pull-down resistor Mask. */
-#define RI_RCR_10KPD           ((uint8_t)0x04) /*!< 10K pull-down resistor Mask. */
-#define RI_RCR_400KPU          ((uint8_t)0x02) /*!< 400K pull-up resistor Mask. */
-#define RI_RCR_10KPU           ((uint8_t)0x01) /*!< 10K pull-up resistor Mask. */
-
-#define RI_IOSR4_CH29E         ((uint8_t)0x01) /*!< Channel 29 I/O switch control */
-#define RI_IOSR4_CH26E         ((uint8_t)0x02) /*!< Channel 26 I/O switch control */
-#define RI_IOSR4_CH27E         ((uint8_t)0x40) /*!< Channel 27 I/O switch control */
-#define RI_IOSR4_CH28E         ((uint8_t)0x80) /*!< Channel 28 I/O switch control */
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------ok*/
-
-/**
-  * @brief Serial Peripheral Interface (SPI)
-  */
-typedef struct SPI_struct
-{
-  __IO uint8_t CR1;    /*!< SPI control register 1 */
-  __IO uint8_t CR2;    /*!< SPI control register 2 */
-  __IO uint8_t CR3;    /*!< SPI DMA and interrupt control register */
-  __IO uint8_t SR;     /*!< SPI status register */
-  __IO uint8_t DR;     /*!< SPI data I/O register */
-  __IO uint8_t CRCPR;  /*!< SPI CRC polynomial register */
-  __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
-  __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
-}
-SPI_TypeDef;
-
-/** @addtogroup SPI_Registers_Reset_Value
-  * @{
-  */
-
-#define SPI_CR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 1 reset value */
-#define SPI_CR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 2 reset value */
-#define SPI_CR3_RESET_VALUE    ((uint8_t)0x00) /*!< DMA and Interrupt Control Register reset value */
-#define SPI_SR_RESET_VALUE     ((uint8_t)0x02) /*!< Status Register reset value */
-#define SPI_DR_RESET_VALUE     ((uint8_t)0x00) /*!< Data Register reset value */
-#define SPI_CRCPR_RESET_VALUE  ((uint8_t)0x07) /*!< Polynomial Register reset value */
-#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */
-#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */
-
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Registers_Bits_Definition
-  * @{
-  */
-
-#define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */
-#define SPI_CR1_SPE      ((uint8_t)0x40) /*!< Enable bits mask */
-#define SPI_CR1_BR       ((uint8_t)0x38) /*!< Baud rate control mask */
-#define SPI_CR1_MSTR     ((uint8_t)0x04) /*!< Master Selection mask */
-#define SPI_CR1_CPOL     ((uint8_t)0x02) /*!< Clock Polarity mask */
-#define SPI_CR1_CPHA     ((uint8_t)0x01) /*!< Clock Phase mask */
-
-#define SPI_CR2_BDM      ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */
-#define SPI_CR2_BDOE     ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */
-#define SPI_CR2_CRCEN    ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */
-#define SPI_CR2_CRCNEXT  ((uint8_t)0x10) /*!< Transmit CRC next mask */
-#define SPI_CR2_RXONLY   ((uint8_t)0x04) /*!< Receive only mask */
-#define SPI_CR2_SSM      ((uint8_t)0x02) /*!< Software slave management mask */
-#define SPI_CR2_SSI      ((uint8_t)0x01) /*!< Internal slave select mask */
-
-#define SPI_CR3_TXIE     ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */
-#define SPI_CR3_RXIE     ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */
-#define SPI_CR3_ERRIE    ((uint8_t)0x20) /*!< Error interrupt enable mask */
-#define SPI_CR3_WKIE     ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */
-#define SPI_CR3_TXDMAEN  ((uint8_t)0x02) /*!< Tx Buffer DMA enable mask */
-#define SPI_CR3_RXDMAEN  ((uint8_t)0x01) /*!< Rx Buffer DMA enable mask */
-
-#define SPI_SR_BSY       ((uint8_t)0x80) /*!< Busy flag */
-#define SPI_SR_OVR       ((uint8_t)0x40) /*!< Overrun flag */
-#define SPI_SR_MODF      ((uint8_t)0x20) /*!< Mode fault */
-#define SPI_SR_CRCERR    ((uint8_t)0x10) /*!< CRC error flag */
-#define SPI_SR_WKUP      ((uint8_t)0x08) /*!< Wake-Up flag */
-#define SPI_SR_TXE       ((uint8_t)0x02) /*!< Transmit buffer empty */
-#define SPI_SR_RXNE      ((uint8_t)0x01) /*!< Receive buffer not empty */
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------ok*/
-
-/**
-  * @brief Advanced 16 bit timer with complementary PWM outputs (TIM1)
-  */
-typedef struct TIM1_struct
-{
-  __IO uint8_t CR1;   /*!< control register 1 */
-  __IO uint8_t CR2;   /*!< control register 2 */
-  __IO uint8_t SMCR;  /*!< Synchro mode control register */
-  __IO uint8_t ETR;   /*!< external trigger register */
-  __IO uint8_t DER;   /*!< DMA requests enable register */
-  __IO uint8_t IER;   /*!< interrupt enable register*/
-  __IO uint8_t SR1;   /*!< status register 1 */
-  __IO uint8_t SR2;   /*!< status register 2 */
-  __IO uint8_t EGR;   /*!< event generation register */
-  __IO uint8_t CCMR1; /*!< CC mode register 1 */
-  __IO uint8_t CCMR2; /*!< CC mode register 2 */
-  __IO uint8_t CCMR3; /*!< CC mode register 3 */
-  __IO uint8_t CCMR4; /*!< CC mode register 4 */
-  __IO uint8_t CCER1; /*!< CC enable register 1 */
-  __IO uint8_t CCER2; /*!< CC enable register 2 */
-  __IO uint8_t CNTRH; /*!< counter high */
-  __IO uint8_t CNTRL; /*!< counter low */
-  __IO uint8_t PSCRH; /*!< prescaler high */
-  __IO uint8_t PSCRL; /*!< prescaler low */
-  __IO uint8_t ARRH;  /*!< auto-reload register high */
-  __IO uint8_t ARRL;  /*!< auto-reload register low */
-  __IO uint8_t RCR;   /*!< Repetition Counter register */
-  __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
-  __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
-  __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
-  __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
-  __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
-  __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
-  __IO uint8_t CCR4H; /*!< capture/compare register 3 high */
-  __IO uint8_t CCR4L; /*!< capture/compare register 3 low */
-  __IO uint8_t BKR;   /*!< Break Register */
-  __IO uint8_t DTR;   /*!< dead-time register */
-  __IO uint8_t OISR;  /*!< Output idle register */
-  __IO uint8_t DCR1;  /*!< DMA control register 1 */
-  __IO uint8_t DCR2;  /*!< DMA control register 2 */
-  __IO uint8_t DMAR;  /*!< DMA Address for brust mode */
-}
-TIM1_TypeDef;
-
-/** @addtogroup TIM1_Registers_Reset_Value
-  * @{
-  */
-#define TIM1_CR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_CR2_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_SMCR_RESET_VALUE  ((uint8_t)0x00)
-#define TIM1_ETR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_DER_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_IER_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_SR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_SR2_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_EGR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_ARRH_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM1_ARRL_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM1_RCR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_BKR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_DTR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_OISR_RESET_VALUE  ((uint8_t)0x00)
-#define TIM1_DCR1_RESET_VALUE  ((uint8_t)0x00)
-#define TIM1_DCR2_RESET_VALUE  ((uint8_t)0x00)
-#define TIM1_DMAR_RESET_VALUE  ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM1_Registers_Bits_Definition
-  * @{
-  */
-/* CR1*/
-#define TIM1_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
-#define TIM1_CR1_CMS     ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */
-#define TIM1_CR1_DIR     ((uint8_t)0x10) /*!< Direction mask. */
-#define TIM1_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
-#define TIM1_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
-#define TIM1_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
-#define TIM1_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
-/* CR2*/
-#define TIM1_CR2_TI1S    ((uint8_t)0x80) /*!< TI1 selection  */
-#define TIM1_CR2_MMS     ((uint8_t)0x70) /*!< MMS Selection mask. */
-#define TIM1_CR2_CCDS    ((uint8_t)0x08) /*!< Capture/Compare DMA Selection */
-#define TIM1_CR2_CCUS    ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */
-#define TIM1_CR2_CCPC    ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */
-/* SMCR*/
-#define TIM1_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode mask. */
-#define TIM1_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection mask. */
-#define TIM1_SMCR_OCCS   ((uint8_t)0x08) /*!< OCREFCLR Selection mask. */
-#define TIM1_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection mask. */
-/* ETR*/
-#define TIM1_ETR_ETP     ((uint8_t)0x80) /*!< External Trigger Polarity mask. */
-#define TIM1_ETR_ECE     ((uint8_t)0x40) /*!< External Clock mask. */
-#define TIM1_ETR_ETPS    ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */
-#define TIM1_ETR_ETF     ((uint8_t)0x0F) /*!< External Trigger Filter mask. */
-/* DER*/
-#define TIM1_DER_COMDE   ((uint8_t)0x20) /*!< Commutation DMA request Enable  mask.*/
-#define TIM1_DER_CC4DE   ((uint8_t)0x10) /*!< Capture/Compare 4 DMA request Enable  mask.*/
-#define TIM1_DER_CC3DE   ((uint8_t)0x08) /*!< Capture/Compare 3 DMA request Enable  mask.*/
-#define TIM1_DER_CC2DE   ((uint8_t)0x04) /*!< Capture/Compare 2 DMA request Enable  mask.*/
-#define TIM1_DER_CC1DE   ((uint8_t)0x02) /*!< Capture/Compare 1 DMA request Enable  mask.*/
-#define TIM1_DER_UDE     ((uint8_t)0x01) /*!< Update DMA request Enable  mask. */
-/* IER*/
-#define TIM1_IER_BIE     ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */
-#define TIM1_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
-#define TIM1_IER_COMIE   ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/
-#define TIM1_IER_CC4IE   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */
-#define TIM1_IER_CC3IE   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
-#define TIM1_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
-#define TIM1_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
-#define TIM1_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
-/* SR1*/
-#define TIM1_SR1_BIF     ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */
-#define TIM1_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
-#define TIM1_SR1_COMIF   ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */
-#define TIM1_SR1_CC4IF   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */
-#define TIM1_SR1_CC3IF   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
-#define TIM1_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
-#define TIM1_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
-#define TIM1_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
-/* SR2*/
-#define TIM1_SR2_CC4OF   ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */
-#define TIM1_SR2_CC3OF   ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
-#define TIM1_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
-#define TIM1_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
-/*EGR*/
-#define TIM1_EGR_BG      ((uint8_t)0x80) /*!< Break Generation mask. */
-#define TIM1_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation mask. */
-#define TIM1_EGR_COMG    ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */
-#define TIM1_EGR_CC4G    ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */
-#define TIM1_EGR_CC3G    ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
-#define TIM1_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
-#define TIM1_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
-#define TIM1_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
-/*CCMR*/
-#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
-#define TIM1_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
-#define TIM1_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
-#define TIM1_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
-#define TIM1_CCMR_OCxFE  ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */
-#define TIM1_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
-#define TIM1_CCMR_OCxCE  ((uint8_t)0x80) /*!< Output Compare x Clear Enable mask. */
-
-#define CCMR_TIxDirect_Set ((uint8_t)0x01)
-/*CCER1*/
-#define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */
-#define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */
-#define TIM1_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
-#define TIM1_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
-#define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */
-#define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */
-#define TIM1_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
-#define TIM1_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
-/*CCER2*/
-#define TIM1_CCER2_CC4P  ((uint8_t)0x20) /*!< Capture/Compare 4 Polarity mask. */
-#define TIM1_CCER2_CC4E  ((uint8_t)0x10) /*!< Capture/Compare 4 Enable mask. */
-#define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */
-#define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */
-#define TIM1_CCER2_CC3P  ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
-#define TIM1_CCER2_CC3E  ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
-/*CNTR*/
-#define TIM1_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
-#define TIM1_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
-/*PSCR*/
-#define TIM1_PSCH_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
-#define TIM1_PSCL_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */
-/*ARR*/
-#define TIM1_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
-#define TIM1_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
-/*RCR*/
-#define TIM1_RCR_REP     ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */
-/*CCR1*/
-#define TIM1_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
-#define TIM1_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
-/*CCR2*/
-#define TIM1_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
-#define TIM1_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
-/*CCR3*/
-#define TIM1_CCR3H_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
-#define TIM1_CCR3L_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
-/*CCR4*/
-#define TIM1_CCR4H_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */
-#define TIM1_CCR4L_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */
-/*BKR*/
-#define TIM1_BKR_MOE     ((uint8_t)0x80) /*!< Main Output Enable mask. */
-#define TIM1_BKR_AOE     ((uint8_t)0x40) /*!< Automatic Output Enable mask. */
-#define TIM1_BKR_BKP     ((uint8_t)0x20) /*!< Break Polarity mask. */
-#define TIM1_BKR_BKE     ((uint8_t)0x10) /*!< Break Enable mask. */
-#define TIM1_BKR_OSSR    ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */
-#define TIM1_BKR_OSSI    ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */
-#define TIM1_BKR_LOCK    ((uint8_t)0x03) /*!< Lock Configuration mask. */
-/*DTR*/
-#define TIM1_DTR_DTG     ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */
-/*OISR*/
-#define TIM1_OISR_OIS3N  ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */
-#define TIM1_OISR_OIS3   ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */
-#define TIM1_OISR_OIS2N  ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */
-#define TIM1_OISR_OIS2   ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */
-#define TIM1_OISR_OIS1N  ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */
-#define TIM1_OISR_OIS1   ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */
-
-/*DCR1*/
-#define TIM1_DCR1_DBA    ((uint8_t)0x1F)    /*!< DMA Base Address mask. */
-
-/*DCR2*/
-#define TIM1_DCR2_DBL    ((uint8_t)0x1F)    /*!< DMA Burst Length mask. */
-
-/*DMAR*/
-#define TIM1_DMAR_VR     ((uint8_t)0xFF)    /*!< Virtual register mask. */
-
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief 16 bit timer :TIM2, TIM3 & TIM5
-  */
-typedef struct TIM_struct
-{
-  __IO uint8_t CR1;    /*!< control register 1   */
-  __IO uint8_t CR2;    /*!< control register 2   */
-  __IO uint8_t SMCR;   /*!< Synchro mode control register */
-  __IO uint8_t ETR;    /*!< external trigger register */
-  __IO uint8_t DER;    /*!< DMA requests enable register */
-  __IO uint8_t IER;    /*!< interrupt enable register*/
-  __IO uint8_t SR1;    /*!< status register 1   */
-  __IO uint8_t SR2;    /*!< status register 2   */
-  __IO uint8_t EGR;    /*!< event generation register */
-  __IO uint8_t CCMR1;  /*!< CC mode register 1      */
-  __IO uint8_t CCMR2;  /*!< CC mode register 2      */
-  __IO uint8_t CCER1;  /*!< CC enable register 1     */
-  __IO uint8_t CNTRH;  /*!< counterregister  high  */
-  __IO uint8_t CNTRL;  /*!< counterregister  low   */
-  __IO uint8_t PSCR;   /*!< prescaler  register   */
-  __IO uint8_t ARRH;   /*!< auto-reload register high  */
-  __IO uint8_t ARRL;   /*!< auto-reload register low    */
-  __IO uint8_t CCR1H;  /*!< capture/compare register 1 high   */
-  __IO uint8_t CCR1L;  /*!< capture/compare register 1 low     */
-  __IO uint8_t CCR2H;  /*!< capture/compare register 2 high   */
-  __IO uint8_t CCR2L;  /*!< capture/compare register 2 low     */
-  __IO uint8_t BKR;    /*!< Break Register */
-  __IO uint8_t OISR;   /*!< Output idle register */
-}
-TIM_TypeDef;
-
-/** @addtogroup TIM2_TIM3_Registers_Reset_Value
-  * @{
-  */
-#define TIM_CR1_RESET_VALUE    ((uint8_t)0x00)
-#define TIM_CR2_RESET_VALUE    ((uint8_t)0x00)
-#define TIM_SMCR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM_ETR_RESET_VALUE    ((uint8_t)0x00)
-#define TIM_DER_RESET_VALUE    ((uint8_t)0x00)
-#define TIM_IER_RESET_VALUE    ((uint8_t)0x00)
-#define TIM_SR1_RESET_VALUE    ((uint8_t)0x00)
-#define TIM_SR2_RESET_VALUE    ((uint8_t)0x00)
-#define TIM_EGR_RESET_VALUE    ((uint8_t)0x00)
-#define TIM_CCMR1_RESET_VALUE  ((uint8_t)0x00)
-#define TIM_CCMR2_RESET_VALUE  ((uint8_t)0x00)
-
-#define TIM_CCER1_RESET_VALUE  ((uint8_t)0x00)
-
-#define TIM_CNTRH_RESET_VALUE  ((uint8_t)0x00)
-#define TIM_CNTRL_RESET_VALUE  ((uint8_t)0x00)
-
-#define TIM_PSCR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM_ARRH_RESET_VALUE   ((uint8_t)0xFF)
-#define TIM_ARRL_RESET_VALUE   ((uint8_t)0xFF)
-
-#define TIM_CCR1H_RESET_VALUE  ((uint8_t)0x00)
-#define TIM_CCR1L_RESET_VALUE  ((uint8_t)0x00)
-#define TIM_CCR2H_RESET_VALUE  ((uint8_t)0x00)
-#define TIM_CCR2L_RESET_VALUE  ((uint8_t)0x00)
-
-#define TIM_BKR_RESET_VALUE    ((uint8_t)0x00)
-#define TIM_OISR_RESET_VALUE   ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM2_TIM3_TIM5_Registers_Bits_Definition
-  * @{
-  */
-/* CR1*/
-#define TIM_CR1_ARPE     ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */
-#define TIM_CR1_CMS      ((uint8_t)0x60) /*!< Center-aligned Mode Selection Mask. */
-#define TIM_CR1_DIR      ((uint8_t)0x10) /*!< Direction Mask. */
-#define TIM_CR1_OPM      ((uint8_t)0x08) /*!< One Pulse Mode Mask. */
-#define TIM_CR1_URS      ((uint8_t)0x04) /*!< Update Request Source Mask. */
-#define TIM_CR1_UDIS     ((uint8_t)0x02) /*!< Update DIsable Mask. */
-#define TIM_CR1_CEN      ((uint8_t)0x01) /*!< Counter Enable Mask. */
-
-/* CR2*/
-#define TIM_CR2_TI1S     ((uint8_t)0x80) /*!< TI1 selection  */
-#define TIM_CR2_MMS      ((uint8_t)0x70) /*!< MMS Selection Mask. */
-#define TIM_CR2_CCDS     ((uint8_t)0x08) /*!< Capture/Compare DMA Selection */
-
-
-/* SMCR*/
-#define TIM_SMCR_MSM     ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
-#define TIM_SMCR_TS      ((uint8_t)0x70) /*!< Trigger Selection Mask. */
-#define TIM_SMCR_SMS     ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
-
-
-/* ETR*/
-#define TIM_ETR_ETP      ((uint8_t)0x80) /*!< External Trigger Polarity Mask. */
-#define TIM_ETR_ECE      ((uint8_t)0x40)/*!< External Clock Mask. */
-#define TIM_ETR_ETPS     ((uint8_t)0x30) /*!< External Trigger Prescaler Mask. */
-#define TIM_ETR_ETF      ((uint8_t)0x0F) /*!< External Trigger Filter Mask. */
-
-/* DER*/
-#define TIM_DER_CC2DE    ((uint8_t)0x04) /*!< Capture/Compare 2 DMA request Enable mask.*/
-#define TIM_DER_CC1DE    ((uint8_t)0x02) /*!< Capture/Compare 1 DMA request Enable mask.*/
-#define TIM_DER_UDE      ((uint8_t)0x01) /*!< Update DMA request Enable  mask. */
-
-/* IER*/
-#define TIM_IER_BIE      ((uint8_t)0x80) /*!< Break Interrupt Enable Mask. */
-#define TIM_IER_TIE      ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */
-#define TIM_IER_CC2IE    ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable Mask. */
-#define TIM_IER_CC1IE    ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable Mask. */
-#define TIM_IER_UIE      ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */
-
-/* SR1*/
-#define TIM_SR1_BIF      ((uint8_t)0x80) /*!< Break Interrupt Flag Mask. */
-#define TIM_SR1_TIF      ((uint8_t)0x40) /*!< Trigger Interrupt Flag Mask. */
-#define TIM_SR1_CC2IF    ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag Mask. */
-#define TIM_SR1_CC1IF    ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag Mask. */
-#define TIM_SR1_UIF      ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */
-
-/* SR2*/
-#define TIM_SR2_CC2OF    ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag Mask. */
-#define TIM_SR2_CC1OF    ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag Mask. */
-
-/*EGR*/
-#define TIM_EGR_BG       ((uint8_t)0x80) /*!< Break Generation Mask. */
-#define TIM_EGR_TG       ((uint8_t)0x40) /*!< Trigger Generation Mask. */
-#define TIM_EGR_CC2G     ((uint8_t)0x04) /*!< Capture/Compare 2 Generation Mask. */
-#define TIM_EGR_CC1G     ((uint8_t)0x02) /*!< Capture/Compare 1 Generation Mask. */
-#define TIM_EGR_UG       ((uint8_t)0x01) /*!< Update Generation Mask. */
-
-/*CCMR*/
-#define TIM_CCMR_ICxF    ((uint8_t)0xF0) /*!< Input Capture x Filter Mask. */
-#define TIM_CCMR_ICxPSC  ((uint8_t)0x0C) /*!< Input Capture x Prescaler Mask. */
-#define TIM_CCMR_CCxS    ((uint8_t)0x03) /*!< Capture/Compare x Selection Mask. */
-#define TIM_CCMR_OCM     ((uint8_t)0x70) /*!< Output Compare x Mode Mask. */
-#define TIM_CCMR_OCxPE   ((uint8_t)0x08) /*!< Output Compare x Preload Enable Mask. */
-#define TIM_CCMR_OCxFE   ((uint8_t)0x04) /*!< Output Compare x Fast Enable Mask. */
-
-#define TIM_CCMR_TIxDirect_Set   ((uint8_t)0x01)
-
-/*CCER1*/
-#define TIM_CCER1_CC2P   ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity Mask. */
-#define TIM_CCER1_CC2E   ((uint8_t)0x10) /*!< Capture/Compare 2 output enable Mask. */
-#define TIM_CCER1_CC1P   ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity Mask. */
-#define TIM_CCER1_CC1E   ((uint8_t)0x01) /*!< Capture/Compare 1 output enable Mask. */
-
-/*CNTR*/
-#define TIM_CNTRH_CNT    ((uint8_t)0xFF) /*!< Counter Value (MSB) Mask. */
-#define TIM_CNTRL_CNT    ((uint8_t)0xFF) /*!< Counter Value (LSB) Mask. */
-
-/*PSCR*/
-#define TIM_PSCR_PSC     ((uint8_t)0x07) /*!< Prescaler Value  Mask. */
-
-/*ARR*/
-#define TIM_ARRH_ARR     ((uint8_t)0xFF) /*!< Autoreload Value (MSB) Mask. */
-#define TIM_ARRL_ARR     ((uint8_t)0xFF) /*!< Autoreload Value (LSB) Mask. */
-
-
-/*CCR1*/
-#define TIM_CCR1H_CCR1   ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) Mask. */
-#define TIM_CCR1L_CCR1   ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) Mask. */
-
-/*CCR2*/
-#define TIM_CCR2H_CCR2   ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) Mask. */
-#define TIM_CCR2L_CCR2   ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) Mask. */
-
-
-/*BKR*/
-#define TIM_BKR_MOE      ((uint8_t)0x80) /*!< Main Output Enable Mask. */
-#define TIM_BKR_AOE      ((uint8_t)0x40) /*!< Automatic Output Enable Mask. */
-#define TIM_BKR_BKP      ((uint8_t)0x20) /*!< Break Polarity Mask. */
-#define TIM_BKR_BKE      ((uint8_t)0x10) /*!< Break Enable Mask. */
-#define TIM_BKR_OSSI     ((uint8_t)0x04) /*!< Off-State Selection for Idle mode Mask. */
-#define TIM_BKR_LOCK     ((uint8_t)0x03) /*!<Lock Configuration Mask. */
-
-/*OISR*/
-#define TIM_OISR_OIS2    ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) Mask. */
-#define TIM_OISR_OIS1    ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) Mask. */
-/**
-  * @}
-  */
-
-
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief 8-bit system or Low End Small Timer (TIM4)
-  */
-typedef struct TIM4_struct
-{
-  __IO uint8_t CR1;   /*!< control register 1 */
-  __IO uint8_t CR2;   /*!< control register 2 */
-  __IO uint8_t SMCR;  /*!< Synchro mode control register */
-  __IO uint8_t DER;   /*!< DMA requests enable register */
-  __IO uint8_t IER;   /*!< interrupt enable register  */
-  __IO uint8_t SR1;   /*!< status register 1    */
-  __IO uint8_t EGR;   /*!< event generation register */
-  __IO uint8_t CNTR;  /*!< counter register  */
-  __IO uint8_t PSCR;  /*!< prescaler register */
-  __IO uint8_t ARR;   /*!< auto-reload register */
-}
-TIM4_TypeDef;
-/** @addtogroup TIM4_Registers_Reset_Value
-  * @{
-  */
-#define TIM4_CR1_RESET_VALUE    ((uint8_t)0x00)
-#define TIM4_CR2_RESET_VALUE    ((uint8_t)0x00)
-#define TIM4_SMCR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM4_DER_RESET_VALUE    ((uint8_t)0x00)
-#define TIM4_IER_RESET_VALUE    ((uint8_t)0x00)
-#define TIM4_SR1_RESET_VALUE    ((uint8_t)0x00)
-#define TIM4_EGR_RESET_VALUE    ((uint8_t)0x00)
-#define TIM4_CNTR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM4_PSCR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM4_ARR_RESET_VALUE    ((uint8_t)0xFF)
-
-/**
-* @}
-*/
-
-/** @addtogroup TIM4_Registers_Bits_Definition
-  * @{
-  */
-/* CR1*/
-#define TIM4_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */
-#define TIM4_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode Mask. */
-#define TIM4_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source Mask. */
-#define TIM4_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable Mask. */
-#define TIM4_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable Mask. */
-
-/* CR2*/
-#define TIM4_CR2_MMS     ((uint8_t)0x70) /*!< MMS Selection Mask. */
-
-/* SMCR*/
-#define TIM4_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
-#define TIM4_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection Mask. */
-#define TIM4_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
-
-/* DER*/
-#define TIM4_DER_UDE     ((uint8_t)0x01) /*!< Update DMA request Enable  mask. */
-
-/* IER*/
-#define TIM4_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */
-#define TIM4_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */
-
-/* SR1*/
-#define TIM4_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */
-#define TIM4_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag Mask. */
-
-/* EGR*/
-#define TIM4_EGR_UG      ((uint8_t)0x01) /*!< Update Generation Mask. */
-#define TIM4_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation Mask. */
-
-/* CNTR*/
-#define TIM4_CNTR_CNT    ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */
-
-/* PSCR*/
-#define TIM4_PSCR_PSC    ((uint8_t)0x0F) /*!<Prescaler Value  Mask. */
-
-/* ARR*/
-#define TIM4_ARR_ARR     ((uint8_t)0xFF) /*!<Autoreload Value Mask. */
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief USART
-  */
-typedef struct USART_struct
-{
-  __IO uint8_t SR;   /*!<  USART status register  */
-  __IO uint8_t DR;   /*!<  USART data register     */
-  __IO uint8_t BRR1; /*!<  USART baud rate register   */
-  __IO uint8_t BRR2; /*!<  USART DIV mantissa[11:8] SCIDIV fraction */
-  __IO uint8_t CR1;  /*!<  USART control register 1     */
-  __IO uint8_t CR2;  /*!<  USART control register 2     */
-  __IO uint8_t CR3;  /*!<  USART control register 3      */
-  __IO uint8_t CR4;  /*!< USART control register 4      */
-  __IO uint8_t CR5;  /*!<  USART control register 5       */
-  __IO uint8_t GTR;  /*!<  USART guard time register     */
-  __IO uint8_t PSCR; /*!<  USART prescaler register     */
-}
-USART_TypeDef;
-
-
-/** @addtogroup USART_Registers_Reset_Value
-  * @{
-  */
-#define USART_SR_RESET_VALUE ((uint8_t)0xC0)
-#define USART_BRR1_RESET_VALUE ((uint8_t)0x00)
-#define USART_BRR2_RESET_VALUE ((uint8_t)0x00)
-#define USART_CR1_RESET_VALUE ((uint8_t)0x00)
-#define USART_CR2_RESET_VALUE ((uint8_t)0x00)
-#define USART_CR3_RESET_VALUE ((uint8_t)0x00)
-#define USART_CR4_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Registers_Bits_Definition
-  * @{
-  */
-#define USART_SR_TXE       ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
-#define USART_SR_TC        ((uint8_t)0x40) /*!< Transmission Complete mask */
-#define USART_SR_RXNE      ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
-#define USART_SR_IDLE      ((uint8_t)0x10) /*!< IDLE line detected mask */
-#define USART_SR_OR        ((uint8_t)0x08) /*!< OverRun error mask */
-#define USART_SR_NF        ((uint8_t)0x04) /*!< Noise Flag mask */
-#define USART_SR_FE        ((uint8_t)0x02) /*!< Framing Error mask */
-#define USART_SR_PE        ((uint8_t)0x01) /*!< Parity Error mask */
-
-#define USART_BRR1_DIVM    ((uint8_t)0xFF) /*!< LSB mantissa of USARTDIV [7:0] mask */
-
-#define USART_BRR2_DIVM    ((uint8_t)0xF0) /*!< MSB mantissa of USARTDIV [11:8] mask */
-#define USART_BRR2_DIVF    ((uint8_t)0x0F) /*!< Fraction bits of USARTDIV [3:0] mask */
-
-#define USART_CR1_R8       ((uint8_t)0x80) /*!< Receive Data bit 8 */
-#define USART_CR1_T8       ((uint8_t)0x40) /*!< Transmit data bit 8 */
-#define USART_CR1_USARTD   ((uint8_t)0x20) /*!< USART Disable (for low power consumption) */
-#define USART_CR1_M        ((uint8_t)0x10) /*!< Word length mask */
-#define USART_CR1_WAKE     ((uint8_t)0x08) /*!< Wake-up method mask */
-#define USART_CR1_PCEN     ((uint8_t)0x04) /*!< Parity Control Enable mask */
-#define USART_CR1_PS       ((uint8_t)0x02) /*!< USART Parity Selection */
-#define USART_CR1_PIEN     ((uint8_t)0x01) /*!< USART Parity Interrupt Enable mask */
-
-#define USART_CR2_TIEN     ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
-#define USART_CR2_TCIEN    ((uint8_t)0x40) /*!< TransmissionComplete Interrupt Enable mask */
-#define USART_CR2_RIEN     ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
-#define USART_CR2_ILIEN    ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
-#define USART_CR2_TEN      ((uint8_t)0x08) /*!< Transmitter Enable mask */
-#define USART_CR2_REN      ((uint8_t)0x04) /*!< Receiver Enable mask */
-#define USART_CR2_RWU      ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
-#define USART_CR2_SBK      ((uint8_t)0x01) /*!< Send Break mask */
-
-#define USART_CR3_STOP     ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
-#define USART_CR3_CLKEN    ((uint8_t)0x08) /*!< Clock Enable mask */
-#define USART_CR3_CPOL     ((uint8_t)0x04) /*!< Clock Polarity mask */
-#define USART_CR3_CPHA     ((uint8_t)0x02) /*!< Clock Phase mask */
-#define USART_CR3_LBCL     ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
-
-#define USART_CR4_ADD      ((uint8_t)0x0F) /*!< Address of the USART node mask */
-
-#define USART_CR5_DMAT     ((uint8_t)0x80) /*!< DMA Enable transmitter mask */
-#define USART_CR5_DMAR     ((uint8_t)0x40) /*!< DMA Enable receiver mask */
-#define USART_CR5_SCEN     ((uint8_t)0x20) /*!< Smart Card Enable mask */
-#define USART_CR5_NACK     ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
-#define USART_CR5_HDSEL    ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
-#define USART_CR5_IRLP     ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
-#define USART_CR5_IREN     ((uint8_t)0x02) /*!< Irda Enable mask */
-#define USART_CR5_EIE      ((uint8_t)0x01) /*!< Error Interrupt mask */
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief Analog to Digital Converter (ADC) peripheral
-  */
-typedef struct ADC_struct
-{
-  __IO uint8_t   CR1;      /*!< Control register 1    */
-  __IO uint8_t   CR2;      /*!< Control register 2    */
-  __IO uint8_t   CR3;      /*!<  Control register 3    */
-  __IO uint8_t   SR;       /*!< Status register    */
-  __IO uint8_t   DRH;      /*!< Data register MSB    */
-  __IO uint8_t   DRL;      /*!< Data register LSB    */
-  __IO uint8_t   HTRH;     /*!< High voltage reference register MSB    */
-  __IO uint8_t   HTRL;     /*!< High voltage reference register LSB    */
-  __IO uint8_t   LTRH;     /*!< Low voltage reference register MSB    */
-  __IO uint8_t   LTRL;     /*!< Low voltage reference register LSB    */
-  __IO uint8_t   SQR[4];   /*!< Channel select scan registers    */
-  __IO uint8_t   TRIGR[4]; /*!< Trigger disable  registers  */
-}
-ADC_TypeDef;
-
-/** @addtogroup ADC_Registers_Reset_Value
-  * @{
-  */
-#define  ADC_CR1_RESET_VALUE      ((uint8_t) 0x00)
-#define  ADC_CR2_RESET_VALUE      ((uint8_t) 0x00)
-#define  ADC_CR3_RESET_VALUE      ((uint8_t) 0x1F)
-#define  ADC_SR_RESET_VALUE       ((uint8_t) 0x00)
-#define  ADC_DRH_RESET_VALUE      ((uint8_t) 0x00)
-#define  ADC_DRL_RESET_VALUE      ((uint8_t) 0x00)
-#define  ADC_HTRH_RESET_VALUE     ((uint8_t) 0x0F)
-#define  ADC_HTRL_RESET_VALUE     ((uint8_t) 0xFF)
-#define  ADC_LTRH_RESET_VALUE     ((uint8_t) 0x00)
-#define  ADC_LTRL_RESET_VALUE     ((uint8_t) 0x00)
-#define  ADC_SQR1_RESET_VALUE     ((uint8_t) 0x00)
-#define  ADC_SQR2_RESET_VALUE     ((uint8_t) 0x00)
-#define  ADC_SQR3_RESET_VALUE     ((uint8_t) 0x00)
-#define  ADC_SQR4_RESET_VALUE     ((uint8_t) 0x00)
-#define  ADC_TRIGR1_RESET_VALUE   ((uint8_t) 0x00)
-#define  ADC_TRIGR2_RESET_VALUE   ((uint8_t) 0x00)
-#define  ADC_TRIGR3_RESET_VALUE   ((uint8_t) 0x00)
-#define  ADC_TRIGR4_RESET_VALUE   ((uint8_t) 0x00)
-
-
-/**
-* @}
-*/
-
-/** @addtogroup ADC_Registers_Bits_Definition
-  * @{
-  */
-#define  ADC_CR1_ADON           ((uint8_t)0x01)
-#define  ADC_CR1_START          ((uint8_t)0x02)
-#define  ADC_CR1_CONT           ((uint8_t)0x04)
-#define  ADC_CR1_EOCIE          ((uint8_t)0x08)
-#define  ADC_CR1_AWDIE          ((uint8_t)0x10)
-#define  ADC_CR1_RES            ((uint8_t)0x60)
-#define  ADC_CR1_OVERIE         ((uint8_t)0x80)
-
-
-#define  ADC_CR2_SMPT1          ((uint8_t)0x07)
-#define  ADC_CR2_EXTSEL         ((uint8_t)0x18)
-#define  ADC_CR2_TRIGEDGE       ((uint8_t)0x60)
-#define  ADC_CR2_PRESC          ((uint8_t)0x80)
-
-#define  ADC_CR3_CHSEL          ((uint8_t)0x1F)
-#define  ADC_CR3_SMPT2          ((uint8_t)0xE0)
-
-#define  ADC_SR_EOC             ((uint8_t)0x01)
-#define  ADC_SR_AWD             ((uint8_t)0x02)
-#define  ADC_SR_OVER            ((uint8_t)0x04)
-
-#define  ADC_DRH_CONVDATA       ((uint8_t)0x0F)
-#define  ADC_DRL_CONVDATA       ((uint8_t)0xFF)
-
-#define  ADC_HTRH_HT            ((uint8_t)0x0F)
-#define  ADC_HTRL_HT            ((uint8_t)0xFF)
-
-#define  ADC_LTRH_LT            ((uint8_t)0x0F)
-#define  ADC_LTRL_LT            ((uint8_t)0xFF)
-
-#define  ADC_SQR1_CHSELS        ((uint8_t)0x3F)
-#define  ADC_SQR1_DMAOFF        ((uint8_t)0x80)
-#define  ADC_SQR2_CHSELS        ((uint8_t)0xFF)
-#define  ADC_SQR3_CHSELS        ((uint8_t)0xFF)
-#define  ADC_SQR4_CHSELS        ((uint8_t)0xFF)
-
-#define  ADC_TRIGR1_TRIG        ((uint8_t)0x0F)
-#define  ADC_TRIGR1_VREFINTON   ((uint8_t)0x10)
-#define  ADC_TRIGR1_TSON        ((uint8_t)0x20)
-
-#define  ADC_TRIGR2_TRIG        ((uint8_t)0xFF)
-#define  ADC_TRIGR3_TRIG        ((uint8_t)0xFF)
-#define  ADC_TRIGR4_TRIG        ((uint8_t)0xFF)
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-
-/**
- * @brief Digital to Analog Converter (DAC) peripheral
-  */
-typedef struct DAC_struct
-{
-  __IO uint8_t  CH1CR1;   /*!< DAC control register 1  */
-  __IO uint8_t  CH1CR2;   /*!< DAC control register 2  */
-  __IO uint8_t  CH2CR1;   /*!< DAC channel 2 control register 1  */
-  __IO uint8_t  CH2CR2;   /*!< DAC channel 2 control register 2  */
-  __IO uint8_t  SWTRIGR; /*!< DAC software trigger register */
-  __IO uint8_t  SR;      /*!< DAC status register */
-
-  /*Channel 1 registers*/
-  __IO uint8_t  RESERVED0[2];
-  __IO uint8_t  CH1RDHRH; /*!< DAC Channel 1 right aligned data holding register MSB */
-  __IO uint8_t  CH1RDHRL; /*!< DAC Channel 1 right aligned data holding register LSB */
-  __IO uint8_t  RESERVED1[2];
-  __IO uint8_t  CH1LDHRH; /*!< DAC Channel 1 left aligned data holding register MSB */
-  __IO uint8_t  CH1LDHRL; /*!< DAC Channel 1 left aligned data holding register LSB */
-  __IO uint8_t  RESERVED2[2];
-  __IO uint8_t  CH1DHR8; /*!< DAC Channel 1 8-bit data holding register */
-
-  /*Channel 2 registers*/
-  __IO uint8_t  RESERVED3[3];
-  __IO uint8_t  CH2RDHRH; /*!< DAC Channel 2 right aligned data holding register MSB */
-  __IO uint8_t  CH2RDHRL; /*!< DAC Channel 2 right aligned data holding register LSB */
-  __IO uint8_t  RESERVED4[2];
-  __IO uint8_t  CH2LDHRH; /*!< DAC Channel 2 left aligned data holding register MSB */
-  __IO uint8_t  CH2LDHRL; /*!< DAC Channel 2 left aligned data holding register LSB */
-  __IO uint8_t  RESERVED5[2];
-  __IO uint8_t  CH2DHR8; /*!< DAC Channel 2 8-bit data holding register */
-
-
-  /* Dual mode registers */
-  __IO uint8_t  RESERVED6[3];
-  __IO uint8_t  DCH1RDHRH; /*!< DAC Dual mode Channel 1 right aligned data holding register MSB */
-  __IO uint8_t  DCH1RDHRL; /*!< DAC Dual mode Channel 1 right aligned data holding register LSB */
-  __IO uint8_t  DCH2RDHRH; /*!< DAC Dual mode Channel 2 right aligned data holding register MSB */
-  __IO uint8_t  DCH2RDHRL; /*!< DAC Dual mode Channel 2 right aligned data holding register LSB */
-  __IO uint8_t  DCH1LDHRH; /*!< DAC Dual mode Channel 1 left aligned data holding register MSB */
-  __IO uint8_t  DCH1LDHRL; /*!< DAC Dual mode Channel 1 left aligned data holding register LSB */
-  __IO uint8_t  DCH2LDHRH; /*!< DAC Dual mode Channel 2 left aligned data holding register MSB */
-  __IO uint8_t  DCH2LDHRL; /*!< DAC Dual mode Channel 2 left aligned data holding register LSB */
-  __IO uint8_t  DCH1DHR8; /*!< DAC Dual mode Channel 1 8-bit data holding register */
-  __IO uint8_t  DCH2DHR8; /*!< DAC Dual mode Channel 2 8-bit data holding register */
-
-  /* DOR registers*/
-  __IO uint8_t  RESERVED7[2];
-  __IO uint8_t  CH1DORH; /*!< DAC Channel 1 data output register MSB */
-  __IO uint8_t  CH1DORL; /*!< DAC Channel 1 data output register LSB */
-  __IO uint8_t  RESERVED8[2];
-  __IO uint8_t  CH2DORH; /*!< DAC Channel 2 data output register MSB */
-  __IO uint8_t  CH2DORL; /*!< DAC Channel 2 data output register LSB */
-}
-DAC_TypeDef;
-
-/** @addtogroup DAC_Registers_Reset_Value
-  * @{
-  */
-#define DAC_CR1_RESET_VALUE       ((uint8_t)0x00)
-#define DAC_CR2_RESET_VALUE       ((uint8_t)0x00)
-#define DAC_SWTRIGR_RESET_VALUE   ((uint8_t)0x00)
-#define DAC_SR_RESET_VALUE        ((uint8_t)0x00)
-#define DAC_RDHRH_RESET_VALUE     ((uint8_t)0x00)
-#define DAC_RDHRL_RESET_VALUE     ((uint8_t)0x00)
-#define DAC_LDHRH_RESET_VALUE     ((uint8_t)0x00)
-#define DAC_LDHRL_RESET_VALUE     ((uint8_t)0x00)
-#define DAC_DHR8_RESET_VALUE      ((uint8_t)0x00)
-#define DAC_DORH_RESET_VALUE      ((uint8_t)0x00)
-#define DAC_DORL_RESET_VALUE      ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Registers_Bits_Definition
-  * @{
-  */
-
-/* CR1*/
-#define DAC_CR1_TSEL          ((uint8_t)0x38) /*!<  DAC channel trigger selection. */
-#define DAC_CR1_TEN           ((uint8_t)0x04) /*!<  DAC channel trigger enable. */
-#define DAC_CR1_BOFF          ((uint8_t)0x02) /*!<  DAC channel output buffer disable. */
-#define DAC_CR1_EN            ((uint8_t)0x01) /*!<  DAC channel enable. */
-#define DAC_CR1_WAVEN         ((uint8_t)0xC0) /*!<  DAC channel wave generation enable. */
-
-/* CR2*/
-#define DAC_CR2_DMAUDRIE      ((uint8_t)0x20) /*!<  DAC channel DMA underrun interrupt enable. */
-#define DAC_CR2_DMAEN         ((uint8_t)0x10) /*!<  DAC DMA enable. */
-#define DAC_CR2_MAMPx         ((uint8_t)0x0F) /*!<  DAC Dchannel wave generation config. */
-
-/* SWTRIGR*/
-#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01) /*!<  DAC channel 1 software trigger. */
-#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02) /*!<  DAC channel 2 software trigger. */
-
-/* SR*/
-#define DAC_SR_DMAUDR1        ((uint8_t)0x01) /*!<  DAC channel 1 DMA underrun flag. */
-#define DAC_SR_DMAUDR2        ((uint8_t)0x02) /*!<  DAC channel 2 DMA underrun flag. */
-
-/* RDHRH*/
-#define DAC_RDHRH_RDHRH       ((uint8_t)0x0F) /*!<  DAC right aligned data holding register most significant bits. */
-
-/* RDHRL*/
-#define DAC_RDHRL_RDHRL       ((uint8_t)0xFF) /*!<  DAC right aligned data holding register least significant bits. */
-
-/* LDHRL*/
-#define DAC_LDHRH_LDHRH       ((uint8_t)0xFF) /*!<  DAC left aligned data holding register most significant bits. */
-
-/* LDHRL*/
-#define DAC_LDHRL_LDHRL       ((uint8_t)0xF0) /*!<  DAC left aligned data holding register least significant bits. */
-
-/* DHR8*/
-#define DAC_DHR8_8DHR         ((uint8_t)0xFF) /*!< DAC 8bit data holding bits */
-
-/* DORH*/
-#define DAC_DORH_DORH         ((uint8_t)0x0F) /*!< DAC data output register most significant bit */
-
-/* DORL*/
-#define DAC_DORL_DORL         ((uint8_t)0xFF) /*!< DAC data output register least significant bit */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief  Direct-Memory Access (DMA)
-  */
-typedef struct DMA_struct
-{
-  __IO uint8_t  GCSR;     /*!<  Global configuration and status register  */
-  __IO uint8_t  GIR1;     /*!<  Global interrupt register 1  */
-}
-DMA_TypeDef;
-/**
-  * @}
-  */
-typedef struct DMA_Channel_struct
-{
-  __IO uint8_t  CCR;       /*!<  CHx Control register  */
-  __IO uint8_t  CSPR;      /*!<  CHx Status & Priority register  */
-  __IO uint8_t  CNBTR;     /*!<  CHx Number of Bytes to Tranfer register  */
-  __IO uint8_t  CPARH;     /*!<  Peripheral Address High register  */
-  __IO uint8_t  CPARL;     /*!<  Peripheral Address Low register  */
-  __IO uint8_t  CM0EAR;    /*!<  Memory 0 Extended Address register  (for channel3)*/
-  __IO uint8_t  CM0ARH;    /*!<  Memory 0 Address High register  */
-  __IO uint8_t  CM0ARL;    /*!<  Memory 0 Address Low register  */
-}
-DMA_Channel_TypeDef;
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Registers_Reset_Value
-  * @{
-  */
-#define DMA_GCSR_RESET_VALUE       ((uint8_t)0xFC)
-#define DMA_GIR1_RESET_VALUE       ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Channels_Registers_Reset_Value
-  * @{
-  */
-#define DMA_CCR_RESET_VALUE          ((uint8_t)0x00)
-#define DMA_CSPR_RESET_VALUE         ((uint8_t)0x00)
-#define DMA_CNBTR_RESET_VALUE        ((uint8_t)0x00)
-#define DMA_CPARH_RESET_VALUE        ((uint8_t)0x52)
-#define DMA_C3PARH_RESET_VALUE       ((uint8_t)0x40)
-#define DMA_CPARL_RESET_VALUE        ((uint8_t)0x00)
-#define DMA_C3M0EAR_RESET_VALUE      ((uint8_t)0x00)
-#define DMA_CM0ARH_RESET_VALUE       ((uint8_t)0x00)
-#define DMA_CM0ARL_RESET_VALUE       ((uint8_t)0x00)
-/** @addtogroup DMA_Registers_Bits_Definition
-  * @{
-  */
-
-/*  Bit definition for DMA_GCSR register  */
-
-#define  DMA_GCSR_GE        ((uint8_t)0x01)            /*!<Global Enable */
-#define  DMA_GCSR_GB        ((uint8_t)0x02)            /*!<Global Busy */
-#define  DMA_GCSR_TO        ((uint8_t)0xFC)            /*!<Time Out */
-
-/*  Bit definition for DMA_GIR1 register  */
-#define  DMA_GIR1_IFC0      ((uint8_t)0x01)            /*!< Interrupt Flag Channel 0 */
-#define  DMA_GIR1_IFC1      ((uint8_t)0x02)            /*!< Interrupt Flag Channel 1 */
-#define  DMA_GIR1_IFC2      ((uint8_t)0x04)            /*!< Interrupt Flag Channel 2 */
-#define  DMA_GIR1_IFC3      ((uint8_t)0x08)            /*!< Interrupt Flag Channel 3 */
-
-
-/*  Bit definition for DMA_CCR registers  */
-#define  DMA_CCR_CE         ((uint8_t)0x01)            /*!<Channel enable*/
-#define  DMA_CCR_TCIE       ((uint8_t)0x02)            /*!<Transfer complete interrupt enable */
-#define  DMA_CCR_HTIE       ((uint8_t)0x04)            /*!<Half Transfer interrupt enable */
-#define  DMA_CCR_DTD        ((uint8_t)0x08)            /*!<Data transfer direction */
-#define  DMA_CCR_ARM        ((uint8_t)0x10)            /*!<Autorelaod mode Circular buffer mode */
-#define  DMA_CCR_IDM        ((uint8_t)0x20)            /*!<Inc/Dec mode */
-#define  DMA_CCR_MEM        ((uint8_t)0x40)            /*!<Memory Transfer Enable */
-
-
-/*  Bit definition for DMA_CSPR registers  */
-#define  DMA_CSPR_TCIF      ((uint8_t)0x02)            /*!<Transaction Complete Interrupt Flag*/
-#define  DMA_CSPR_HTIF      ((uint8_t)0x04)            /*!<Half Transaction Interrupt Flag*/
-#define  DMA_CSPR_16BM      ((uint8_t)0x08)            /*!<16 bit mode*/
-#define  DMA_CSPR_PL        ((uint8_t)0x30)            /*!<Channel priority level*/
-#define  DMA_CSPR_PEND      ((uint8_t)0x40)            /*!<Channel pending*/
-#define  DMA_CSPR_BUSY      ((uint8_t)0x80)            /*!<Channel Busy */
-
-
-/*  Bit definition for DMA_CNBTR register */
-#define  DMA_CNBTR_NDT      ((uint8_t)0xFF)            /*!<Number of data to Transfer */
-
-
-/*  Bit definition for DMA_CPARH register  */
-#define  DMA_CPARH_PA       ((uint8_t)0xFF)        /*!<Peripheral MSB Address Pointer */
-/*  Bit definition for DMA_CPARL register  */
-#define  DMA_CPARL_PA       ((uint8_t)0xFF)        /*!<Peripheral LSB Address Pointer */
-
-
-/*  Bit definition for DMA_CMAR registers  */
-#define  DMA_CM0EAR_MA      ((uint8_t)0x01)        /* Memory Extended Address Pointer only for channel 3 in Memory to memory transfer*/
-#define  DMA_CM0ARH_MA      ((uint8_t)0xFF)        /*!<Memory MSB Address Pointer*/
-#define  DMA_CM0ARL_MA      ((uint8_t)0xFF)        /*!<Memory LSB Address Pointer */
-
-
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief Window Watchdog (WWDG)
-  */
-typedef struct WWDG_struct
-{
-  __IO uint8_t CR; /*!< Control Register */
-  __IO uint8_t WR; /*!< Window Register */
-}
-WWDG_TypeDef;
-
-/** @addtogroup WWDG_Registers_Reset_Value
-  * @{
-  */
-
-#define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
-#define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
-
-/**
-* @}
-*/
-
-/** @addtogroup WWDG_Registers_Bits_Definition
-  * @{
-  */
-
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */
-#define WWDG_CR_T6   ((uint8_t)0x40) /*!< T6 bit mask */
-#define WWDG_CR_T    ((uint8_t)0x7F) /*!< T bits mask */
-
-#define WWDG_WR_MSB  ((uint8_t)0x80) /*!< MSB bit mask */
-#define WWDG_WR_W    ((uint8_t)0x7F) /*!< W bits mask */
-
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief LCD Controller (LCD)
-  */
-typedef struct LCD_struct
-{
-  __IO uint8_t CR1;      /*!< LCD control register 1 */
-  __IO uint8_t CR2;      /*!< LCD control register 2 */
-  __IO uint8_t CR3;      /*!< LCD control register 3 */
-  __IO uint8_t FRQ;      /*!< LCD frequency register */
-  __IO uint8_t PM[6];    /*!< LCD portmask registers*/
-  uint8_t RESERVED1[2];  /*!< Reserved */
-  __IO uint8_t RAM[22];  /*!< LCD RAM registers*/
-  uint8_t RESERVED2[13]; /*!< Reserved */
-  __IO uint8_t CR4;      /*!< LCD control register 4 */
-}
-LCD_TypeDef;
-/** @addtogroup LCD_Registers_Reset_Value
-  * @{
-  */
-#define LCD_CR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 1 reset value */
-#define LCD_CR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 2 reset value */
-#define LCD_CR3_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 3 reset value */
-#define LCD_FRQ_RESET_VALUE    ((uint8_t)0x00) /*!< Register Frequency reset value */
-#define LCD_PM_RESET_VALUE     ((uint8_t)0x00) /*!< Port mask Register reset value */
-#define LCD_RAM_RESET_VALUE    ((uint8_t)0x00) /*!< RAM Register reset value       */
-#define LCD_CR4_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 4 reset value */
-
-
-/**
-* @}
-*/
-
-/** @addtogroup LCD_Registers_Bits_Definition
-  * @{
-  */
-#define LCD_CR1_BLINK    ((uint8_t)0xC0) /*!< Blink bits mask           */
-#define LCD_CR1_BLINKF   ((uint8_t)0x38) /*!< Blink frequency bits mask */
-#define LCD_CR1_DUTY     ((uint8_t)0x06) /*!< Duty bits mask            */
-#define LCD_CR1_B2       ((uint8_t)0x01) /*!< Bias selector bit mask    */
-
-
-#define LCD_CR2_PON      ((uint8_t)0xE0) /*!< Pulse on duration bits mask */
-#define LCD_CR2_HD       ((uint8_t)0x10) /*!< High drive enable bit mask  */
-#define LCD_CR2_CC       ((uint8_t)0x0E) /*!< Contrast control bits mask  */
-#define LCD_CR2_VSEL     ((uint8_t)0x01) /*!< Voltage source bit mask     */
-
-#define LCD_CR3_LCDEN    ((uint8_t)0x40) /*!< Enable bit mask           */
-#define LCD_CR3_SOFIE    ((uint8_t)0x20) /*!< Start of frame interrupt enable mask */
-#define LCD_CR3_SOF      ((uint8_t)0x10) /*!< Start of frame bit mask              */
-#define LCD_CR3_SOFC     ((uint8_t)0x08) /*!< Clear start of frame bit mask        */
-#define LCD_CR3_DEAD     ((uint8_t)0x07) /*!< DEAD time bits mask                  */
-
-#define LCD_FRQ_DIV      ((uint8_t)0x0F) /*!< Divider bits mask */
-#define LCD_FRQ_PS       ((uint8_t)0xF0) /*!< 16 bits prescaler bits mask */
-
-#define LCD_CR4_MAPCOM   ((uint8_t)0x08) /*!< Select the mapping scheme for the COM[7:4] */
-#define LCD_CR4_PAGECOM  ((uint8_t)0x04) /*!< Select the LCD RAM page sector */
-#define LCD_CR4_DUTY8    ((uint8_t)0x02) /*!< Enable the 1/8 duty */
-#define LCD_CR4_B4       ((uint8_t)0x01) /*!< Enable the 1/4 bias */
-
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/* This peripheral is avilable in STM8L16x devices only*/
-/**
-  * @brief AES tiny (AES)
-  */
-typedef struct AES_struct
-{
-  __IO uint8_t CR;      /*!< AES control register     */
-  __IO uint8_t SR;      /*!< AES status register      */
-  __IO uint8_t DINR;    /*!< AES Data input register  */
-  __IO uint8_t DOUTR;   /*!< AES Data output register */
-}
-AES_TypeDef;
-
-/** @addtogroup AES_Registers_Reset_Value
-  * @{
-  */
-#define AES_CR_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register reset value     */
-#define AES_SR_RESET_VALUE    ((uint8_t)0x00) /*!< Status Register reset value      */
-#define AES_DINR_RESET_VALUE  ((uint8_t)0x00) /*!< Data input register reset value  */
-#define AES_DOUTR_RESET_VALUE ((uint8_t)0x00) /*!< Data output register reset value */
-/**
-* @}
-*/
-
-/** @addtogroup AES_Registers_Bits_Definition
-  * @{
-  */
-#define AES_CR_DMAEN  ((uint8_t)0x80) /*!< DMA Enable bit mask */
-#define AES_CR_ERRIE  ((uint8_t)0x40) /*!< Error Interrupt Enable bit mask */
-#define AES_CR_CCIE   ((uint8_t)0x20) /*!< Computation Complete Interrupt Enable bit mask */
-#define AES_CR_ERRC   ((uint8_t)0x10) /*!< Error Clear bit mask  */
-#define AES_CR_CCFC   ((uint8_t)0x08) /*!< Computation Complete Flag Clear bit mask */
-#define AES_CR_MODE   ((uint8_t)0x06) /*!< AES Modes of Operation bits mask */
-#define AES_CR_EN     ((uint8_t)0x01) /*!< AES Enable bit mask */
-
-#define AES_SR_WRERR  ((uint8_t)0x04) /*!< Write Error Flag bit mask */
-#define AES_SR_RDERR  ((uint8_t)0x02) /*!< Read Error Flag bit mask */
-#define AES_SR_CCF    ((uint8_t)0x01) /*!< Computation Complete Flag bit mask */
-
-#define AES_DINR      ((uint8_t)0xFF) /*!< Data Input bits mask */
-#define AES_DOUTR     ((uint8_t)0xFF) /*!< Data Output bits mask */
-
-/**
-  * @}
-  */
-/******************************************************************************/
-/*                          Peripherals Base Address                          */
-/******************************************************************************/
-#define OPT_BASE                    (uint16_t)0x4800
-#define GPIOA_BASE                  (uint16_t)0x5000
-#define GPIOB_BASE                  (uint16_t)0x5005
-#define GPIOC_BASE                  (uint16_t)0x500A
-#define GPIOD_BASE                  (uint16_t)0x500F
-#define GPIOE_BASE                  (uint16_t)0x5014
-#define GPIOF_BASE                  (uint16_t)0x5019
-#define GPIOG_BASE                  (uint16_t)0x501E
-#define GPIOH_BASE                  (uint16_t)0x5023
-#define GPIOI_BASE                  (uint16_t)0x5028
-#define FLASH_BASE                  (uint16_t)0x5050
-#define DMA1_BASE                   (uint16_t)0x5070
-#define DMA1_Channel0_BASE          (uint16_t)0x5075
-#define DMA1_Channel1_BASE          (uint16_t)0x507F
-#define DMA1_Channel2_BASE          (uint16_t)0x5089
-#define DMA1_Channel3_BASE          (uint16_t)0x5093
-#define SYSCFG_BASE                 (uint16_t)0x509D
-#define EXTI_BASE                   (uint16_t)0x50A0
-#define WFE_BASE                    (uint16_t)0x50A6
-#define RST_BASE                    (uint16_t)0x50B0
-#define PWR_BASE                    (uint16_t)0x50B2
-#define CLK_BASE                    (uint16_t)0x50C0
-#define WWDG_BASE                   (uint16_t)0x50D3
-#define IWDG_BASE                   (uint16_t)0x50E0
-#define BEEP_BASE                   (uint16_t)0x50F0
-#define RTC_BASE                    (uint16_t)0x5140
-#define CSSLSE_BASE                 (uint16_t)0x5190
-#define SPI1_BASE                   (uint16_t)0x5200
-#define SPI2_BASE                   (uint16_t)0x53C0
-#define I2C1_BASE                   (uint16_t)0x5210
-#define USART1_BASE                 (uint16_t)0x5230
-#define USART2_BASE                 (uint16_t)0x53E0
-#define USART3_BASE                 (uint16_t)0x53F0
-#define TIM2_BASE                   (uint16_t)0x5250
-#define TIM3_BASE                   (uint16_t)0x5280
-#define TIM1_BASE                   (uint16_t)0x52B0
-#define TIM4_BASE                   (uint16_t)0x52E0
-#define IRTIM_BASE                  (uint16_t)0x52FF
-#define TIM5_BASE                   (uint16_t)0x5300
-#define ADC1_BASE                   (uint16_t)0x5340
-#define DAC_BASE                    (uint16_t)0x5380
-#define AES_BASE                    (uint16_t)0x53D0
-#define LCD_BASE                    (uint16_t)0x5400
-#define RI_BASE                     (uint16_t)0x5430
-#define COMP_BASE                   (uint16_t)0x5440
-#define CFG_BASE                    (uint16_t)0x7F60
-#define ITC_BASE                    (uint16_t)0x7F70
-#define DM_BASE                     (uint16_t)0x7F90
-
-/******************************************************************************/
-/*                          Peripherals declarations                          */
-/******************************************************************************/
-
-
-#define SYSCFG                      ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define GPIOA                       ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB                       ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC                       ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD                       ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE                       ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF                       ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG                       ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH                       ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI                       ((GPIO_TypeDef *) GPIOI_BASE)
-#define RTC                         ((RTC_TypeDef *) RTC_BASE)
-#define FLASH                       ((FLASH_TypeDef *) FLASH_BASE)
-#define EXTI                        ((EXTI_TypeDef *) EXTI_BASE)
-#define RST                         ((RST_TypeDef *) RST_BASE)
-#define PWR                         ((PWR_TypeDef *) PWR_BASE)
-#define CLK                         ((CLK_TypeDef *) CLK_BASE)
-#define CSSLSE                      ((CSSLSE_TypeDef *) CSSLSE_BASE)
-#define WWDG                        ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                        ((IWDG_TypeDef *) IWDG_BASE)
-#define WFE                         ((WFE_TypeDef *) WFE_BASE)
-#define BEEP                        ((BEEP_TypeDef *) BEEP_BASE)
-#define SPI1                        ((SPI_TypeDef *) SPI1_BASE)
-#define SPI2                        ((SPI_TypeDef *) SPI2_BASE)
-#define I2C1                        ((I2C_TypeDef *) I2C1_BASE)
-#define USART1                      ((USART_TypeDef *) USART1_BASE)
-#define USART2                      ((USART_TypeDef *) USART2_BASE)
-#define USART3                      ((USART_TypeDef *) USART3_BASE)
-#define LCD                         ((LCD_TypeDef *) LCD_BASE)
-#define TIM1                        ((TIM1_TypeDef *) TIM1_BASE)
-#define TIM2                        ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                        ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                        ((TIM4_TypeDef *) TIM4_BASE)
-#define TIM5                        ((TIM_TypeDef *) TIM5_BASE)
-#define IRTIM                       ((IRTIM_TypeDef *) IRTIM_BASE)
-#define ITC                         ((ITC_TypeDef *) ITC_BASE)
-#define DAC                         ((DAC_TypeDef *) DAC_BASE)
-#define DMA1                        ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel0               ((DMA_Channel_TypeDef *) DMA1_Channel0_BASE)
-#define DMA1_Channel1               ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2               ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3               ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DM                          ((DM_TypeDef *) DM_BASE)
-#define RI                          ((RI_TypeDef *) RI_BASE)
-#define COMP                        ((COMP_TypeDef *) COMP_BASE)
-#define AES                         ((AES_TypeDef *) AES_BASE)
-#define ADC1                        ((ADC_TypeDef *) ADC1_BASE)
-#define CFG                         ((CFG_TypeDef *) CFG_BASE)
-#define OPT                         ((OPT_TypeDef *) OPT_BASE)
-
-#ifdef USE_STDPERIPH_DRIVER 
- #include "stm8l15x_conf.h"
-#endif
-
-/* Exported macro --------------------------------------------------------------*/
-
-/*============================== Interrupts ====================================*/
-#ifdef _RAISONANCE_
- #include <intrist7.h>
- #define enableInterrupts()  _rim_()  /*!<enable interrupts */
- #define disableInterrupts() _sim_()  /*!<disable interrupts */
- #define rim()               _rim_()  /*!<enable interrupts */
- #define sim()               _sim_()  /*!<disable interrupts */
- #define nop()               _nop_()  /*!<No Operation */
- #define trap()              _trap_() /*!<Trap (soft IT) */
- #define wfi()               _wfi_()  /*!<Wait For Interrupt */
- #define wfe()               _wfe_()  /*!<Wait For Interrupt */
- #define halt()              _halt_() /*!<Halt */
-#elif defined(_COSMIC_)
- #define enableInterrupts() {_asm("rim\n");} /*!<enable interrupts */
- #define disableInterrupts() {_asm("sim\n");} /*!<disable interrupts */
- #define rim() {_asm("rim\n");} /*!<enable interrupts */
- #define sim() {_asm("sim\n");} /*!<disable interrupts */
- #define nop() {_asm("nop\n");} /*!<No Operation */
- #define trap() {_asm("trap\n");} /*!<Trap (soft IT) */
- #define wfi() {_asm("wfi\n");} /*!<Wait For Interrupt */
- #define wfe() {_asm("wfe\n");} /*!<Wait for event */
- #define halt() {_asm("halt\n");} /*!<Halt */
-#else /*_IAR*/
- #include <intrinsics.h>
- #define enableInterrupts()    __enable_interrupt()   /* enable interrupts */
- #define disableInterrupts()   __disable_interrupt()  /* disable interrupts */
- #define rim()                 __enable_interrupt()   /* enable interrupts */
- #define sim()                 __disable_interrupt()  /* disable interrupts */
- #define nop()                 __no_operation()       /* No Operation */
- #define trap()                __trap()               /* Trap (soft IT) */
- #define wfi()                 __wait_for_interrupt() /* Wait For Interrupt */
- #define wfe()                 __wait_for_event();    /* Wait for event */
- #define halt()                __halt()               /* Halt */
-#endif /* _RAISONANCE_ */
-
-/*============================== Interrupt vector Handling ========================*/
-
-#ifdef _COSMIC_
- #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)
- #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)
-#endif /* _COSMIC_ */
-
-#ifdef _RAISONANCE_
- #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b
- #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap
-#endif /* _RAISONANCE_ */
-
-#ifdef _IAR_
- #define STRINGVECTOR(x) #x
- #define VECTOR_ID(x) STRINGVECTOR( vector = (x) )
- #define INTERRUPT_HANDLER( a, b )  \
- _Pragma( VECTOR_ID( (b)+2 ) )        \
- __interrupt void (a)( void )
- #define INTERRUPT_HANDLER_TRAP(a) \
- _Pragma( VECTOR_ID( 1 ) ) \
- __interrupt void (a) (void)  
-#endif /* _IAR_ */
-
-/*============================== Interrupt Handler declaration ========================*/
-#ifdef _COSMIC_
- #define INTERRUPT @far @interrupt
-#elif defined(_IAR_)
- #define INTERRUPT __interrupt
-#endif /* _COSMIC_ */
- 
-/*============================== Handling bits ====================================*/
-/*-----------------------------------------------------------------------------
-Method : I
-Description : Handle the bit from the character variables.
-Comments :    The different parameters of commands are
-              - VAR : Name of the character variable where the bit is located.
-              - Place : Bit position in the variable (7 6 5 4 3 2 1 0)
-              - Value : Can be 0 (reset bit) or not 0 (set bit)
-              The "MskBit" command allows to select some bits in a source
-              variables and copy it in a destination var (return the value).
-              The "ValBit" command returns the value of a bit in a char
-              variable: the bit is reseted if it returns 0 else the bit is set.
-              This method generates not an optimised code yet.
------------------------------------------------------------------------------*/
-#define SetBit(VAR,Place)         ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
-#define ClrBit(VAR,Place)         ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
-
-#define ChgBit(VAR,Place)         ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
-#define AffBit(VAR,Place,Value)   ((Value) ? \
-                                   ((VAR) |= ((uint8_t)1<<(Place))) : \
-                                   ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))
-#define MskBit(Dest,Msk,Src)      ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
-
-#define ValBit(VAR,Place)         ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
-
-#define BYTE_0(n)                 ((uint8_t)((n) & (uint8_t)0xFF))        /*!< Returns the low byte of the 32-bit value */
-#define BYTE_1(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))  /*!< Returns the second byte of the 32-bit value */
-#define BYTE_2(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */
-#define BYTE_3(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */
-
-/*============================== Assert Macros ====================================*/
-#define IS_STATE_VALUE(STATE) \
-  (((STATE) == SET) || \
-   ((STATE) == RESET))
-
-/*-----------------------------------------------------------------------------
-Method : II
-Description : Handle directly the bit.
-Comments :    The idea is to handle directly with the bit name. For that, it is
-              necessary to have RAM area descriptions (example: HW register...)
-              and the following command line for each area.
-              This method generates the most optimized code.
------------------------------------------------------------------------------*/
-
-#define AREA 0x00     /* The area of bits begins at address 0x10. */
-
-#define BitClr(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
-#define BitSet(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
-#define BitVal(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
-
-
-#endif /* __STM8L15x_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM8S/hal_lld.c b/os/hal/platforms/STM8S/hal_lld.c
deleted file mode 100644
index ddc7c79b6..000000000
--- a/os/hal/platforms/STM8S/hal_lld.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8S/hal_lld.c
- * @brief   STM8S HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- * @details Clock sources initialization, HSI is assumed to be already
- *          started after reset.
- * @note    If the @p STM8S_CLOCK_INIT option is set to @p FALSE then the
- *          initialization is not performed and is left to the application.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-#if !STM8S_NO_CLOCK_INIT
-  /* Makes sure that HSI is stable before proceeding.*/
-  CLK->ICKR |= CLK_ICKR_HSIEN;
-  while ((CLK->ICKR & CLK_ICKR_HSIRDY) == 0)
-    ;
-
-  /* LSI startup and stabilization if required.*/
-#if STM8S_LSI_ENABLED
-  CLK->ICKR |= CLK_ICKR_LSIEN;
-  while ((CLK->ICKR & CLK_ICKR_LSIRDY) == 0)
-    ;
-#endif
-
-  /* HSE startup and stabilization if required.*/
-#if STM8S_HSE_ENABLED
-  CLK->ECKR |= CLK_ECKR_HSEEN;
-  while ((CLK->ECKR & CLK_ECKR_HSERDY) == 0)
-    ;
-#endif
-
-  /* Setting up clock dividers.*/
-  CLK->CKDIVR  = (STM8S_HSI_DIVIDER << 3) | (STM8S_CPU_DIVIDER << 0);
-
-  /* SYSCLK switch to the selected source, not necessary if it is HSI.*/
-#if STM8S_SYSCLK_SOURCE != CLK_SYSSEL_HSI
-  /* Switching clock (manual switch mode).*/
-  CLK->SWR  = STM8S_SYSCLK_SOURCE;
-  while ((CLK->SWCR & CLK_SWCR_SWIF) == 0)
-    ;
-  CLK->SWCR = CLK_SWCR_SWEN;
-#endif
-
-  /* Clocks initially all disabled.*/
-  CLK->PCKENR1 = 0;
-  CLK->PCKENR2 = 0;
-
-  /* Other clock related initializations.*/
-  CLK->CSSR    = 0;
-  CLK->CCOR    = 0;
-
-  /* HSI disabled if it is no more required.*/
-#if !STM8S_HSI_ENABLED
-  CLK->ICKR &= ~CLK_ICKR_HSIEN;
-#endif
-#endif /* !STM8S_NO_CLOCK_INIT */
-}
-
-/** @} */
diff --git a/os/hal/platforms/STM8S/hal_lld.h b/os/hal/platforms/STM8S/hal_lld.h
deleted file mode 100644
index 0bf87ac01..000000000
--- a/os/hal/platforms/STM8S/hal_lld.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8S/hal_lld.h
- * @brief   STM8S HAL subsystem low level driver source.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - HSECLK (@p 0 if disabled or frequency in Hertz).
- *          .
- *          One of the following macros must also be defined:
- *          - STM8S103.
- *          - STM8S105.
- *          - STM8S207.
- *          - STM8S208.
- *          - STM8S903.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#undef FALSE
-#undef TRUE
-
-#if defined(STM8S208) || defined(STM8S207) || defined(STM8S105) ||          \
-    defined(STM8S103) || defined(STM8S903)
-#include "stm8s.h"
-#else
-#error "unsupported or invalid STM8 platform"
-#endif
-
-#define FALSE 0
-#define TRUE (!FALSE)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME       "STM8S"
-
-#define LSICLK              128000      /**< Low speed internal clock.      */
-#define HSICLK              16000000    /**< High speed internal clock.     */
-
-#define CLK_SYSSEL_HSI      0xE1        /**< HSI clock selector.            */
-#define CLK_SYSSEL_LSI      0xD2        /**< LSI clock selector.            */
-#define CLK_SYSSEL_HSE      0xB4        /**< HSE clock selector.            */
-
-#define CLK_HSI_DIV1        0           /**< HSI clock divided by 1.        */
-#define CLK_HSI_DIV2        1           /**< HSI clock divided by 2.        */
-#define CLK_HSI_DIV4        2           /**< HSI clock divided by 4.        */
-#define CLK_HSI_DIV8        3           /**< HSI clock divided by 8.        */
-
-#define CLK_CPU_DIV1        0           /**< CPU clock divided by 1.        */
-#define CLK_CPU_DIV2        1           /**< CPU clock divided by 2.        */
-#define CLK_CPU_DIV4        2           /**< CPU clock divided by 4.        */
-#define CLK_CPU_DIV8        3           /**< CPU clock divided by 8.        */
-#define CLK_CPU_DIV16       4           /**< CPU clock divided by 16.       */
-#define CLK_CPU_DIV32       5           /**< CPU clock divided by 32.       */
-#define CLK_CPU_DIV64       6           /**< CPU clock divided by 64.       */
-#define CLK_CPU_DIV128      7           /**< CPU clock divided by 128.      */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Disables the clock initialization in the HAL.
- */
-#if !defined(STM8S_NO_CLOCK_INIT) || defined(__DOXYGEN__)
-#define STM8S_NO_CLOCK_INIT         FALSE
-#endif
-
-/**
- * @brief   Enables or disables the HSI clock source.
- */
-#if !defined(STM8S_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM8S_HSI_ENABLED           FALSE
-#endif
-
-/**
- * @brief   Enables or disables the LSI clock source.
- */
-#if !defined(STM8S_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM8S_LSI_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Enables or disables the HSE clock source.
- */
-#if !defined(STM8S_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM8S_HSE_ENABLED           TRUE
-#endif
-
-/**
- * @brief   Clock source setting.
- */
-#if !defined(STM8S_SYSCLK_SOURCE) || defined(__DOXYGEN__)
-#define STM8S_SYSCLK_SOURCE         CLK_SYSSEL_HSE
-#endif
-
-/**
- * @brief   HSI clock divider.
- */
-#if !defined(STM8S_HSI_DIVIDER) || defined(__DOXYGEN__)
-#define STM8S_HSI_DIVIDER           CLK_HSI_DIV8
-#endif
-
-/**
- * @brief   CPU clock divider.
- */
-#if !defined(STM8S_CPU_DIVIDER) || defined(__DOXYGEN__)
-#define STM8S_CPU_DIVIDER           CLK_CPU_DIV1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if (STM8S_HSI_DIVIDER != CLK_HSI_DIV1)  &&                                 \
-    (STM8S_HSI_DIVIDER != CLK_HSI_DIV2)  &&                                 \
-    (STM8S_HSI_DIVIDER != CLK_HSI_DIV4)  &&                                 \
-    (STM8S_HSI_DIVIDER != CLK_HSI_DIV8)
-#error "specified invalid HSI divider"
-#endif
-
-#if (STM8S_CPU_DIVIDER != CLK_CPU_DIV1)  &&                                 \
-    (STM8S_CPU_DIVIDER != CLK_CPU_DIV2)  &&                                 \
-    (STM8S_CPU_DIVIDER != CLK_CPU_DIV4)  &&                                 \
-    (STM8S_CPU_DIVIDER != CLK_CPU_DIV8)  &&                                 \
-    (STM8S_CPU_DIVIDER != CLK_CPU_DIV16) &&                                 \
-    (STM8S_CPU_DIVIDER != CLK_CPU_DIV32) &&                                 \
-    (STM8S_CPU_DIVIDER != CLK_CPU_DIV64) &&                                 \
-    (STM8S_CPU_DIVIDER != CLK_CPU_DIV128)
-#error "specified invalid CPU divider"
-#endif
-
-#if STM8S_HSE_ENABLED && (HSECLK == 0)
-#error "impossible to activate HSE"
-#endif
-
-#if !STM8S_HSI_ENABLED && (STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSI)
-#error "requested HSI clock is not enabled"
-#endif
-
-#if !STM8S_LSI_ENABLED && (STM8S_SYSCLK_SOURCE == CLK_SYSSEL_LSI)
-#error "requested LSI clock is not enabled"
-#endif
-
-#if !STM8S_HSE_ENABLED && (STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSE)
-#error "requested HSE clock is not enabled"
-#endif
-
-/**
- * @brief   System clock.
- */
-#if STM8SL_NO_CLOCK_INIT || defined(__DOXYGEN__)
-#define SYSCLK                      (HSICLK / 8)
-#elif STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSI
-#define SYSCLK                      (HSICLK / (1 << STM8S_HSI_DIVIDER))
-#elif STM8S_SYSCLK_SOURCE == CLK_SYSSEL_LSI
-#define SYSCLK                      LSICLK
-#elif STM8S_SYSCLK_SOURCE == CLK_SYSSEL_HSE
-#define SYSCLK                      HSECLK
-#else
-#error "specified invalid clock source"
-#endif
-
-/**
- * @brief   CPU clock.
- * @details On the STM8SS the CPU clock can be programmed to be a fraction of
- *          the system clock.
- */
-#define CPUCLK                      (SYSCLK / (1 << STM8S_CPU_DIVIDER))
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8S/pal_lld.c b/os/hal/platforms/STM8S/pal_lld.c
deleted file mode 100644
index b377abc63..000000000
--- a/os/hal/platforms/STM8S/pal_lld.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8S/pal_lld.c
- * @brief   STM8S GPIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT_PULLUP:
-    port->DDR &= ~mask;
-    port->CR1 |=  mask;
-    port->CR2 &= ~mask;
-    break;
-  case PAL_MODE_INPUT:
-  case PAL_MODE_INPUT_ANALOG:
-    port->DDR &= ~mask;
-    port->CR1 &= ~mask;
-    port->CR2 &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-  case PAL_MODE_OUTPUT_PUSHPULL_SLOW:
-    port->DDR |=  mask;
-    port->CR1 |=  mask;
-    port->CR2 &= ~mask;
-    break;
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->DDR |=  mask;
-    port->CR1 |=  mask;
-    port->CR2 |=  mask;
-    break;
-  case PAL_MODE_OUTPUT_OPENDRAIN_SLOW:
-    port->DDR |=  mask;
-    port->CR1 &= ~mask;
-    port->CR2 &= ~mask;
-    break;
-  case PAL_MODE_OUTPUT_OPENDRAIN:
-    port->DDR |=  mask;
-    port->CR1 &= ~mask;
-    port->CR2 |=  mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/STM8S/pal_lld.h b/os/hal/platforms/STM8S/pal_lld.h
deleted file mode 100644
index 86246a05b..000000000
--- a/os/hal/platforms/STM8S/pal_lld.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8S/pal_lld.h
- * @brief   STM8S GPIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLDOWN
-
-/**
- * @brief   STM8S specific alternate push-pull slow output mode.
- */
-#define PAL_MODE_OUTPUT_PUSHPULL_SLOW   16
-
-/**
- * @brief   STM8S specific alternate open-drain slow output mode.
- */
-#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW  17
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-#if defined(STM8S105) || defined(__DOXYGEN__)
-  GPIO_TypeDef          P[7];
-#elif defined(STM8S207) || defined(STM8S208)
-  GPIO_TypeDef          P[9];
-#else
-  GPIO_TypeDef          P[6];
-#endif
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 8
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint8_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint8_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef GPIO_TypeDef *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   GPIO ports as a whole.
- */
-#define IOPORTS         ((PALConfig *)0x5000)
-
-/**
- * @brief   GPIO port A identifier.
- */
-#define IOPORT1         GPIOA
-
-/**
- * @brief   GPIO port B identifier.
- */
-#define IOPORT2         GPIOB
-
-/**
- * @brief   GPIO port C identifier.
- */
-#define IOPORT3         GPIOC
-
-/**
- * @brief   GPIO port D identifier.
- */
-#define IOPORT4         GPIOD
-
-/**
- * @brief   GPIO port E identifier.
- */
-#define IOPORT5         GPIOE
-
-/**
- * @brief   GPIO port F identifier.
- */
-#define IOPORT6         GPIOF
-
-#if defined(STM8S207) || defined(STM8S208) || defined(STM8S105) ||          \
-    defined(__DOXYGEN__)
-/**
- * @brief   GPIO port G identifier.
- */
-#define IOPORT7         GPIOG
-#endif
-
-#if defined(STM8S207) || defined(STM8S208) || defined(__DOXYGEN__)
-/**
- * @brief   GPIO port H identifier.
- */
-#define IOPORT8         GPIOH
-
-/**
- * @brief   GPIO port I identifier.
- */
-#define IOPORT9         GPIOI
-#endif
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) (*IOPORTS = *(config))
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->IDR)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->ODR)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-extern ROMCONST PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8S/platform.dox b/os/hal/platforms/STM8S/platform.dox
deleted file mode 100644
index 9d259cadc..000000000
--- a/os/hal/platforms/STM8S/platform.dox
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup STM8S STM8S Drivers
- * @details This section describes all the supported drivers on the STM8S
- *          platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup STM8S_HAL STM8S Initialization Support
- * @details The STM8S HAL support is responsible for system initialization.
- *
- * @section stm8s_hal_1 Supported HW resources
- * - CLK.
- * .
- * @section stm8s_hal_2 STM8S HAL driver implementation features
- * - Clock tree initialization.
- * - Clock source selection.
- * .
- * @ingroup STM8S
- */
-
-/**
- * @defgroup STM8S_PAL STM8S PAL Support
- * @details The STM8S PAL driver uses the GPIO peripherals.
- *
- * @section stm8s_pal_1 Supported HW resources
- * - GPIOA.
- * - GPIOB.
- * - GPIOC.
- * - GPIOD.
- * - GPIOE.
- * - GPIOF.
- * - GPIOG (where present).
- * - GPIOH (where present).
- * - GPIOI (where present).
- * .
- * @section stm8s_pal_2 STM8S PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 8 bits wide ports.
- * - Atomic set/reset/toggle functions because special STM8S instruction set.
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section stm8s_pal_3 Supported PAL setup modes
- * The STM8S PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section stm8s_pal_4 Suboptimal behavior
- * The STM8S GPIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Bus/group writing is not atomic.
- * - Pad/group mode setup is not atomic.
- * .
- * @ingroup STM8S
- */
-
-/**
- * @defgroup STM8S_SERIAL STM8S Serial Support
- * @details The STM8S Serial driver uses the UART peripherals in a
- *          buffered, interrupt driven, implementation.
- *
- * @section stm8s_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - UART1.
- * - UART2 (where present).
- * - UART3 (where present).
- * .
- * @section stm8s_serial_2 STM8S Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART can be independently enabled and programmed. Unused
- *   peripherals are left in low power mode.
- * - Fully interrupt driven.
- * .
- * @ingroup STM8S
- */
-
-/**
- * @defgroup STM8S_SPI STM8S SPI Support
- * @details The SPI driver supports the STM8S SPI peripheral in an interrupt
- *          driven implementation.
- * @note    Being the SPI a fast peripheral, much care must be taken to
- *          not saturate the CPU bandwidth with an excessive IRQ rate. The
- *          maximum transfer bit rate is likely limited by the IRQ
- *          handling.
- *
- * @section stm8s_spi_1 Supported HW resources
- * - SPI.
- * .
- * @section stm8s_spi_2 STM8S SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Fully interrupt driven.
- * .
- * @ingroup STM8S
- */
diff --git a/os/hal/platforms/STM8S/serial_lld.c b/os/hal/platforms/STM8S/serial_lld.c
deleted file mode 100644
index fc49540a6..000000000
--- a/os/hal/platforms/STM8S/serial_lld.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8S/serial_lld.c
- * @brief   STM8S low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART1 serial driver identifier.
- */
-#if STM8S_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/**
- * @brief   UART2 serial driver identifier.
- */
-#if STM8S_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/**
- * @brief   UART3 serial driver identifier.
- */
-#if STM8S_SERIAL_USE_UART3 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Driver default configuration.
- */
-static ROMCONST SerialConfig default_config = {
-  BRR(SERIAL_DEFAULT_BITRATE),
-  SD_MODE_PARITY_NONE | SD_MODE_STOP_1
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void set_error(SerialDriver *sdp, uint8_t sr) {
-  flagsmask_t sts = 0;
-
-  /* Note, SR register bit definitions are equal for all UARTs so using
-     the UART1 definitions is fine.*/
-  if (sr & UART1_SR_OR)
-    sts |= SD_OVERRUN_ERROR;
-  if (sr & UART1_SR_NF)
-    sts |= SD_NOISE_ERROR;
-  if (sr & UART1_SR_FE)
-    sts |= SD_FRAMING_ERROR;
-  if (sr & UART1_SR_PE)
-    sts |= SD_PARITY_ERROR;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-#if STM8S_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  UART1->CR2 |= UART1_CR2_TIEN;
-}
-
-/**
- * @brief   UART1 initialization.
- *
- * @param[in] config    architecture-dependent serial driver configuration
- */
-static void uart1_init(const SerialConfig *config) {
-
-  UART1->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
-                          ((uint8_t)config->sc_brr & (uint8_t)0x0F));
-  UART1->BRR1 = (uint8_t)(config->sc_brr >> 4);
-  UART1->CR1  = (uint8_t)(config->sc_mode &
-                          SD_MODE_PARITY);  /* PIEN included.               */
-  UART1->CR2  = UART1_CR2_RIEN | UART1_CR2_TEN | UART1_CR2_REN;
-  UART1->CR3  = (uint8_t)(config->sc_mode & SD_MODE_STOP);
-  UART1->CR4  = 0;
-  UART1->CR5  = 0;
-  UART1->PSCR = 1;
-  (void)UART1->SR;
-  (void)UART1->DR;
-}
-
-/**
- * @brief   UART1 de-initialization.
- */
-static void uart1_deinit(void) {
-
-  UART1->CR1  = UART1_CR1_UARTD;
-  UART1->CR2  = 0;
-  UART1->CR3  = 0;
-  UART1->CR4  = 0;
-  UART1->CR5  = 0;
-  UART1->PSCR = 0;
-}
-#endif /* STM8S_SERIAL_USE_UART1 */
-
-#if STM8S_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  UART2->CR2 |= UART2_CR2_TIEN;
-}
-
-/**
- * @brief   UART2 initialization.
- *
- * @param[in] config    architecture-dependent serial driver configuration
- */
-static void uart2_init(const SerialConfig *config) {
-
-  UART2->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
-                          ((uint8_t)config->sc_brr & (uint8_t)0x0F));
-  UART2->BRR1 = (uint8_t)(config->sc_brr >> 4);
-  UART2->CR1  = (uint8_t)(config->sc_mode &
-                          SD_MODE_PARITY);  /* PIEN included.               */
-  UART2->CR2  = UART2_CR2_RIEN | UART2_CR2_TEN | UART2_CR2_REN;
-  UART2->CR3  = (uint8_t)(config->sc_mode & SD_MODE_STOP);
-  UART2->CR4  = 0;
-  UART2->CR5  = 0;
-  UART2->CR6  = 0;
-  UART2->PSCR = 1;
-  (void)UART2->SR;
-  (void)UART2->DR;
-}
-
-/**
- * @brief   UART1 de-initialization.
- */
-static void uart2_deinit(void) {
-
-  UART2->CR1  = UART2_CR1_UARTD;
-  UART2->CR2  = 0;
-  UART2->CR3  = 0;
-  UART2->CR4  = 0;
-  UART2->CR5  = 0;
-  UART2->CR6  = 0;
-  UART2->PSCR = 0;
-}
-#endif /* STM8S_SERIAL_USE_UART1 */
-
-#if STM8S_SERIAL_USE_UART3 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
-  (void)qp;
-  UART3->CR2 |= UART3_CR2_TIEN;
-}
-
-/**
- * @brief   UART3 initialization.
- *
- * @param[in] config    architecture-dependent serial driver configuration
- */
-static void uart3_init(const SerialConfig *config) {
-
-  UART3->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
-                          ((uint8_t)config->sc_brr & (uint8_t)0x0F));
-  UART3->BRR1 = (uint8_t)(config->sc_brr >> 4);
-  UART3->CR1  = (uint8_t)(config->sc_mode &
-                          SD_MODE_PARITY);  /* PIEN included.               */
-  UART3->CR2  = UART3_CR2_RIEN | UART3_CR2_TEN | UART3_CR2_REN;
-  UART3->CR3  = (uint8_t)(config->sc_mode & SD_MODE_STOP);
-  UART3->CR4  = 0;
-  UART3->CR6  = 0;
-  (void)UART3->SR;
-  (void)UART3->DR;
-}
-
-/**
- * @brief   UART3 de-initialization.
- */
-static void uart3_deinit(void) {
-
-  UART3->CR1  = UART3_CR1_UARTD;
-  UART3->CR2  = 0;
-  UART3->CR3  = 0;
-  UART3->CR4  = 0;
-  UART3->CR6  = 0;
-}
-#endif /* STM8S_SERIAL_USE_UART3 */
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM8S_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-/**
- * @brief   IRQ 17 service routine.
- *
- * @isr
- */
-CH_IRQ_HANDLER(17) {
-  msg_t b;
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  b = sdRequestDataI(&SD1);
-  chSysUnlockFromIsr();
-  if (b < Q_OK)
-    UART1->CR2 &= (uint8_t)~UART1_CR2_TIEN;
-  else
-    UART1->DR = (uint8_t)b;
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   IRQ 18 service routine.
- *
- * @isr
- */
-CH_IRQ_HANDLER(18) {
-  uint8_t sr = UART1->SR;
-
-  CH_IRQ_PROLOGUE();
-
-  if ((sr = UART1->SR) & (UART1_SR_OR | UART1_SR_NF |
-                          UART1_SR_FE | UART1_SR_PE))
-    set_error(&SD1, sr);
-  chSysLockFromIsr();
-  sdIncomingDataI(&SD1, UART1->DR);
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM8S_SERIAL_USE_UART1 */
-
-#if STM8S_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-/**
- * @brief   IRQ 20 service routine.
- *
- * @isr
- */
-CH_IRQ_HANDLER(20) {
-  msg_t b;
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  b = sdRequestDataI(&SD2);
-  chSysUnlockFromIsr();
-  if (b < Q_OK)
-    UART2->CR2 &= (uint8_t)~UART2_CR2_TIEN;
-  else
-    UART2->DR = (uint8_t)b;
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   IRQ 21 service routine.
- *
- * @isr
- */
-CH_IRQ_HANDLER(21) {
-  uint8_t sr = UART2->SR;
-
-  CH_IRQ_PROLOGUE();
-
-  if ((sr = UART2->SR) & (UART2_SR_OR | UART2_SR_NF |
-                          UART2_SR_FE | UART2_SR_PE))
-    set_error(&SD2, sr);
-  chSysLockFromIsr();
-  sdIncomingDataI(&SD2, UART2->DR);
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM8S_SERIAL_USE_UART2 */
-
-#if STM8S_SERIAL_USE_UART3 || defined(__DOXYGEN__)
-/**
- * @brief   IRQ 20 service routine.
- *
- * @isr
- */
-CH_IRQ_HANDLER(20) {
-  msg_t b;
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  b = sdRequestDataI(&SD3);
-  chSysUnlockFromIsr();
-  if (b < Q_OK)
-    UART3->CR2 &= (uint8_t)~UART3_CR2_TIEN;
-  else
-    UART3->DR = (uint8_t)b;
-
-  CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   IRQ 21 service routine.
- *
- * @isr
- */
-CH_IRQ_HANDLER(21) {
-  uint8_t sr = UART3->SR;
-
-  CH_IRQ_PROLOGUE();
-
-  if ((sr = UART3->SR) & (UART3_SR_OR | UART3_SR_NF |
-                          UART3_SR_FE | UART3_SR_PE))
-    set_error(&SD3, sr);
-  chSysLockFromIsr();
-  sdIncomingDataI(&SD3, UART3->DR);
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-#endif /* STM8S_SERIAL_USE_UART3 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if STM8S_SERIAL_USE_UART1
-  sdObjectInit(&SD1, NULL, notify1);
-  CLK->PCKENR1 |= CLK_PCKENR1_UART1;        /* PCKEN12, clock source.       */
-  UART1->CR1 = UART1_CR1_UARTD;             /* UARTD (low power).           */
-#endif
-
-#if STM8S_SERIAL_USE_UART2
-  sdObjectInit(&SD2, NULL, notify2);
-  CLK->PCKENR1 |= CLK_PCKENR1_UART2;        /* PCKEN13, clock source.       */
-  UART2->CR1 = UART2_CR1_UARTD;             /* UARTD (low power).           */
-#endif
-
-#if STM8S_SERIAL_USE_UART3
-  sdObjectInit(&SD3, NULL, notify3);
-  CLK->PCKENR1 |= CLK_PCKENR1_UART3;        /* PCKEN13, clock source.       */
-  UART3->CR1 = UART3_CR1_UARTD;             /* UARTD (low power).           */
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-#if STM8S_SERIAL_USE_UART1
-  if (&SD1 == sdp) {
-    uart1_init(config);
-    return;
-  }
-#endif
-#if STM8S_SERIAL_USE_UART2
-  if (&SD2 == sdp) {
-    uart2_init(config);
-    return;
-  }
-#endif
-#if STM8S_SERIAL_USE_UART3
-  if (&SD3 == sdp) {
-    uart3_init(config);
-    return;
-  }
-#endif
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-#if STM8S_SERIAL_USE_UART1
-  if (&SD1 == sdp) {
-    uart1_deinit();
-    return;
-  }
-#endif
-#if STM8S_SERIAL_USE_UART2
-  if (&SD2 == sdp) {
-    uart2_deinit();
-    return;
-  }
-#endif
-#if STM8S_SERIAL_USE_UART3
-  if (&SD3 == sdp) {
-    uart3_deinit();
-    return;
-  }
-#endif
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/STM8S/serial_lld.h b/os/hal/platforms/STM8S/serial_lld.h
deleted file mode 100644
index 9dfca2262..000000000
--- a/os/hal/platforms/STM8S/serial_lld.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8S/serial_lld.h
- * @brief   STM8S low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define SD_MODE_PARITY          0x07        /**< @brief Parity field mask.  */
-#define SD_MODE_PARITY_NONE     0x00        /**< @brief No parity.          */
-#define SD_MODE_PARITY_EVEN     0x05        /**< @brief Even parity.        */
-#define SD_MODE_PARITY_ODD      0x07        /**< @brief Odd parity.         */
-
-#define SD_MODE_STOP            0x30        /**< @brief Stop bits mask.     */
-#define SD_MODE_STOP_1          0x00        /**< @brief One stop bit.       */
-#define SD_MODE_STOP_2          0x20        /**< @brief Two stop bits.      */
-#define SD_MODE_STOP_1P5        0x30        /**< @brief 1.5 stop bits.      */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART1 driver enable switch.
- * @details If set to @p TRUE the support for UART1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM8S_SERIAL_USE_UART1) || defined(__DOXYGEN__)
-#define STM8S_SERIAL_USE_UART1          TRUE
-#endif
-
-/**
- * @brief   UART2 driver enable switch.
- * @details If set to @p TRUE the support for UART3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM8S_SERIAL_USE_UART2) || defined(__DOXYGEN__)
-#define STM8S_SERIAL_USE_UART2          TRUE
-#endif
-
-/**
- * @brief   UART3 driver enable switch.
- * @details If set to @p TRUE the support for UART3 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM8S_SERIAL_USE_UART3) || defined(__DOXYGEN__)
-#define STM8S_SERIAL_USE_UART3          TRUE
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM8S_SERIAL_USE_UART2 && STM8S_SERIAL_USE_UART3
-#error "STM8S UART2 and UART3 cannot be used together"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    This structure content is architecture dependent, each driver
- *          implementation defines its own version and the custom static
- *          initializers.
- */
-typedef struct {
-  /**
-   * @brief Bit rate register.
-   */
-  uint16_t                  sc_brr;
-  /**
-   * @brief Mode flags.
-   */
-  uint8_t                   sc_mode;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Macro for baud rate computation.
- * @note    Make sure the final baud rate is within tolerance.
- */
-#define BRR(b) (SYSCLK / (b))
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM8S_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if STM8S_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-#if STM8S_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8S/spi_lld.c b/os/hal/platforms/STM8S/spi_lld.c
deleted file mode 100644
index 9a9256c61..000000000
--- a/os/hal/platforms/STM8S/spi_lld.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8S/spi_lld.c
- * @brief   STM8S low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-#if STM8S_SPI_USE_SPI || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM8S_SPI_USE_SPI || defined(__DOXYGEN__)
-/**
- * @brief   IRQ 10 service routine.
- *
- * @isr
- */
-CH_IRQ_HANDLER(10) {
-
-  CH_IRQ_PROLOGUE();
-
-  if ((SPI->SR & SPI_SR_OVR) != 0) {
-    /* The overflow condition should never happen because priority is given
-       to receive but a hook macro is provided anyway...*/
-    STM8S_SPI_ERROR_HOOK(&SPID1);
-  }
-  /* Handling the DR register like it is a FIFO with depth>1 in order to
-     handle the case where a frame arrives immediately after reading the
-     DR register.*/
-  while ((SPI->SR & SPI_SR_RXNE) != 0) {
-    if (SPID1.rxptr != NULL)
-       *SPID1.rxptr++ = SPI->DR;
-    else
-      (void)SPI->DR;
-    if (--SPID1.rxcnt == 0) {
-      chDbgAssert(SPID1.txcnt == 0,
-                  "IRQ10, #1", "counter out of synch");
-      /* Stops all the IRQ sources.*/
-      SPI->ICR = 0;
-      /* Portable SPI ISR code defined in the high level driver, note, it
-         is a macro.*/
-      _spi_isr_code(&SPID1);
-      /* Goto because it is mandatory to go through the epilogue, cannot
-         just return.*/
-      goto exit_isr;
-    }
-  }
-  /* Loading the DR register.*/
-  if ((SPI->SR & SPI_SR_TXE) != 0) {
-    if (SPID1.txptr != NULL)
-      SPI->DR = *SPID1.txptr++;
-    else
-      SPI->DR = 0xFF;
-  }
-
-exit_isr:
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if STM8S_SPI_USE_SPI
-  spiObjectInit(&SPID1);
-#endif /* STM8S_SPI_USE_SPI */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  /* Clock activation.*/
-  CLK->PCKENR1 |= CLK_PCKENR1_SPI;              /* PCKEN11, clock source.   */
-
-  /* Configuration.*/
-  SPI->CR1  = 0;
-  SPI->CR1  = spip->config->cr1 | SPI_CR1_MSTR;
-  SPI->CR2  = SPI_CR2_SSI | SPI_CR2_SSM;
-  SPI->CR1 |= SPI_CR1_SPE;
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  (void)spip;
-
-  /* Reset state.*/
-  SPI->CR1 = 0;
-  SPI->CR2 = 0;
-  SPI->ICR = 0;
-
-  /* Clock de-activation.*/
-  CLK->PCKENR1 &= (uint8_t)~CLK_PCKENR1_SPI;    /* PCKEN11, clock source.   */
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- *          ignores the received data. This function can be invoked even
- *          when a slave select signal has not been yet asserted.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  spip->rxptr = NULL;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE;
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE;
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  spip->rxptr = NULL;
-  spip->txptr = txbuf;
-  spip->rxcnt = spip->txcnt = n;
-  SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE;
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  spip->rxptr = rxbuf;
-  spip->txptr = NULL;
-  spip->rxcnt = spip->txcnt = n;
-  SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE;
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) {
-
-  (void)spip;
-
-  SPI->DR = (uint32_t)frame;
-  while ((SPI->SR & SPI_SR_RXNE) == 0)
-    ;
-  return (uint16_t)SPI->DR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/STM8S/spi_lld.h b/os/hal/platforms/STM8S/spi_lld.h
deleted file mode 100644
index 8b87b81fc..000000000
--- a/os/hal/platforms/STM8S/spi_lld.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM8S/spi_lld.h
- * @brief   STM8S low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver enable switch.
- * @details If set to @p TRUE the support for device SSP0 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM8S_SPI_USE_SPI) || defined(__DOXYGEN__)
-#define STM8S_SPI_USE_SPI               TRUE
-#endif
-
-/**
- * @brief   Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(STM8S_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM8S_SPI_ERROR_HOOK(spip)      chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if !STM8S_SPI_USE_SPI
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback or @p NULL.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief The chip select line port.
-   */
-  ioportid_t            ssport;
-  /**
-   * @brief The chip select line pad number.
-   */
-  uint16_t              sspad;
-  /**
-   * @brief SPI initialization data.
-   */
-  uint8_t               cr1;
-} SPIConfig;
-
-/**
- * @brief   Structure representing a SPI driver.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief Number of bytes yet to be received.
-   */
-  uint16_t              rxcnt;
-  /**
-   * @brief Receive pointer or @p NULL.
-   */
-  uint8_t               *rxptr;
-  /**
-   * @brief Number of bytes yet to be transmitted.
-   */
-  uint16_t              txcnt;
-  /**
-   * @brief Transmit pointer or @p NULL.
-   */
-  const uint8_t         *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM8S_SPI_USE_SPI && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM8S/stm8s.h b/os/hal/platforms/STM8S/stm8s.h
deleted file mode 100644
index 07a8362d3..000000000
--- a/os/hal/platforms/STM8S/stm8s.h
+++ /dev/null
@@ -1,2725 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm8s.h
-  * @author  MCD Application Team
-  * @version V2.1.0
-  * @date    18-November-2011
-  * @brief   This file contains all HW registers definitions and memory mapping.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM8S_H
-#define __STM8S_H
-
-/** @addtogroup STM8S_StdPeriph_Driver
-  * @{
-  */
-
-/* Uncomment the line below according to the target STM8S or STM8A device used in your
-   application. */
-
- /* #define STM8S208 */      /*!< STM8S High density devices with CAN */
- /* #define STM8S207 */      /*!< STM8S High density devices without CAN */
- /* #define STM8S007 */      /*!< STM8S Value Line High density devices */
- /* #define STM8AF52Ax */    /*!< STM8A High density devices with CAN */
- /* #define STM8AF62Ax */    /*!< STM8A High density devices without CAN */
- /* #define STM8S105 */      /*!< STM8S Medium density devices */
- /* #define STM8S005 */      /*!< STM8S Value Line Medium density devices */
- /* #define STM8AF626x */    /*!< STM8A Medium density devices */
- /* #define STM8S103 */      /*!< STM8S Low density devices */
- /* #define STM8S003 */      /*!< STM8S Value Line Low density devices */
- /* #define STM8S903 */      /*!< STM8S Low density devices */
-
-/*   Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-
-  - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,
-    STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory
-    density ranges between 32 to 128 Kbytes
-  - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,
-    STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory
-    density ranges between 8 to 32 Kbytes
-  - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers
-    where the Flash memory density ranges between 32 to 128 Kbytes.
-  - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers
-    where the Flash memory density ranges between 16 to 32-Kbytes.
-  - Low-Density STM8S devices are the STM8S103xx, STM8S003 and STM8S903xx microcontrollers
-    where the Flash density is 8 Kbytes. */
-
-#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \
-    !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \
-    !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \
-    !defined (STM8S003)&& !defined (STM8S005)
- #error "Please select first the target STM8S/A device used in your application (in stm8s.h file)"
-#endif
-
-/******************************************************************************/
-/*                   Library configuration section                            */
-/******************************************************************************/
-/* Check the used compiler */
-#if defined(__CSMC__)
- #define _COSMIC_
-#elif defined(__RCST7__)
- #define _RAISONANCE_
-#elif defined(__ICCSTM8__)
- #define _IAR_
-#else
- #error "Unsupported Compiler!"          /* Compiler defines not found */
-#endif
-
-#if !defined  USE_STDPERIPH_DRIVER
-/* Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will be
-   based on direct access to peripherals registers */
-/* CHIBIOS FIX */
-/* #define USE_STDPERIPH_DRIVER*/
-#endif
-
-/**
-  * @brief  In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application
-
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */
-#if !defined  HSE_Value
- #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
-     defined (STM8AF62Ax)
-  #define HSE_VALUE ((u32)24000000) /* Value of the External oscillator in Hz*/
- #else
-  #define HSE_VALUE ((u32)16000000) /* Value of the External oscillator in Hz*/
- #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax */
-#endif /* HSE_Value */
-
-/**
-  * @brief  Definition of Device on-chip RC oscillator frequencies
-  */
-#define HSI_VALUE   ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */
-#define LSI_VALUE   ((uint32_t)128000)   /*!< Typical Value of the LSI in Hz */
-
-#ifdef _COSMIC_
- #define FAR  @far
- #define NEAR @near
- #define TINY @tiny
- #define EEPROM @eeprom
- #define CONST  const
-#elif defined (_RAISONANCE_) /* __RCST7__ */
- #define FAR  far
- #define NEAR data
- #define TINY page0
- #define EEPROM eeprom
- #define CONST  code
- #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
-     defined (STM8AF62Ax)
-   /*!< Used with memory Models for code higher than 64K */
-  #define MEMCPY fmemcpy
- #else /* STM8S903, STM8S103, STM8S003, STM8S105, STM8AF626x */
-  /*!< Used with memory Models for code less than 64K */
-  #define MEMCPY memcpy
- #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */
-#else /*_IAR_*/
- #define FAR  __far
- #define NEAR __near
- #define TINY __tiny
- #define EEPROM __eeprom
- #define CONST  const
-#endif /* __CSMC__ */
-
-/* For FLASH routines, select whether pointer will be declared as near (2 bytes,
-   to handle code smaller than 64KB) or far (3 bytes, to handle code larger
-   than 64K) */
-
-#if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \
-    defined (STM8S903) || defined (STM8AF626x)
-/*!< Used with memory Models for code smaller than 64K */
- #define PointerAttr NEAR
-#else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */
-/*!< Used with memory Models for code higher than 64K */
- #define PointerAttr FAR
-#endif /* STM8S105 or STM8S103 or STM8S003 or STM8S903 or STM8AF626x */
-
-/* Uncomment the line below to enable the FLASH functions execution from RAM */
-#if !defined (RAM_EXECUTION)
-/* #define RAM_EXECUTION  (1) */
-#endif /* RAM_EXECUTION */
-
-#ifdef RAM_EXECUTION
- #ifdef _COSMIC_
-   #define IN_RAM(a) a
- #elif defined (_RAISONANCE_) /* __RCST7__ */
-   #define IN_RAM(a) a inram
- #else /*_IAR_*/
-  #define IN_RAM(a) __ramfunc a
- #endif /* _COSMIC_ */
-#else
-  #define IN_RAM(a) a
-#endif /* RAM_EXECUTION */
-
-/*!< [31:16] STM8S Standard Peripheral Library main version V2.1.0*/
-#define __STM8S_STDPERIPH_VERSION_MAIN   ((uint8_t)0x02) /*!< [31:24] main version */
-#define __STM8S_STDPERIPH_VERSION_SUB1   ((uint8_t)0x01) /*!< [23:16] sub1 version */
-#define __STM8S_STDPERIPH_VERSION_SUB2   ((uint8_t)0x00) /*!< [15:8]  sub2 version */
-#define __STM8S_STDPERIPH_VERSION_RC     ((uint8_t)0x00) /*!< [7:0]  release candidate */
-#define __STM8S_STDPERIPH_VERSION       ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\
-                                          |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\
-                                          |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\
-                                          |(__STM8S_STDPERIPH_VERSION_RC))
-
-/******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types and constants ----------------------------------------------*/
-
-/** @addtogroup Exported_types
-  * @{
-  */
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-#define     __I     volatile const   /*!< defines 'read only' permissions     */
-#define     __O     volatile         /*!< defines 'write only' permissions    */
-#define     __IO    volatile         /*!< defines 'read / write' permissions  */
-
-/*!< Signed integer types  */
-/* CHIBIOS FIX */
-#if 0
-typedef   signed char     int8_t;
-typedef   signed short    int16_t;
-typedef   signed long     int32_t;
-
-/*!< Unsigned integer types  */
-typedef unsigned char     uint8_t;
-typedef unsigned short    uint16_t;
-typedef unsigned long     uint32_t;
-#endif
-
-/*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */
-
-typedef int32_t  s32;
-typedef int16_t s16;
-typedef int8_t  s8;
-
-typedef uint32_t  u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-
-typedef enum {FALSE = 0, TRUE = !FALSE} bool;
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-#define U8_MAX     (255)
-#define S8_MAX     (127)
-#define S8_MIN     (-128)
-#define U16_MAX    (65535u)
-#define S16_MAX    (32767)
-#define S16_MIN    (-32768)
-#define U32_MAX    (4294967295uL)
-#define S32_MAX    (2147483647)
-#define S32_MIN    (-2147483648uL)
-
-/**
-  * @}
-  */
-
-/** @addtogroup MAP_FILE_Exported_Types_and_Constants
-  * @{
-  */
-
-/******************************************************************************/
-/*                          IP registers structures                           */
-/******************************************************************************/
-
-/**
-  * @brief  General Purpose I/Os (GPIO)
-  */
-typedef struct GPIO_struct
-{
-  __IO uint8_t ODR; /*!< Output Data Register */
-  __IO uint8_t IDR; /*!< Input Data Register */
-  __IO uint8_t DDR; /*!< Data Direction Register */
-  __IO uint8_t CR1; /*!< Configuration Register 1 */
-  __IO uint8_t CR2; /*!< Configuration Register 2 */
-}
-GPIO_TypeDef;
-
-/** @addtogroup GPIO_Registers_Reset_Value
-  * @{
-  */
-
-#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
-#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
-#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
-#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
-    defined(STM8S903) || defined(STM8AF626x)
-/**
-  * @brief  Analog to Digital Converter (ADC1)
-  */
- typedef struct ADC1_struct
- {
-  __IO uint8_t DB0RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB0RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  __IO uint8_t DB1RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB1RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  __IO uint8_t DB2RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB2RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  __IO uint8_t DB3RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB3RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  __IO uint8_t DB4RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB4RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  __IO uint8_t DB5RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB5RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  __IO uint8_t DB6RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB6RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  __IO uint8_t DB7RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB7RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  __IO uint8_t DB8RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB8RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  __IO uint8_t DB9RH;         /*!< ADC1 Data Buffer Register (MSB)  */
-  __IO uint8_t DB9RL;         /*!< ADC1 Data Buffer Register (LSB)  */
-  uint8_t RESERVED[12];       /*!< Reserved byte */
-  __IO uint8_t CSR;           /*!< ADC1 control status register */
-  __IO uint8_t CR1;           /*!< ADC1 configuration register 1 */
-  __IO uint8_t CR2;           /*!< ADC1 configuration register 2 */
-  __IO uint8_t CR3;           /*!< ADC1 configuration register 3  */
-  __IO uint8_t DRH;           /*!< ADC1 Data high */
-  __IO uint8_t DRL;           /*!< ADC1 Data low */
-  __IO uint8_t TDRH;          /*!< ADC1 Schmitt trigger disable register high */
-  __IO uint8_t TDRL;          /*!< ADC1 Schmitt trigger disable register low */
-  __IO uint8_t HTRH;          /*!< ADC1 high threshold register High*/
-  __IO uint8_t HTRL;          /*!< ADC1 high threshold register Low*/
-  __IO uint8_t LTRH;          /*!< ADC1 low threshold register high */
-  __IO uint8_t LTRL;          /*!< ADC1 low threshold register low */
-  __IO uint8_t AWSRH;         /*!< ADC1 watchdog status register high */
-  __IO uint8_t AWSRL;         /*!< ADC1 watchdog status register low */
-  __IO uint8_t AWCRH;         /*!< ADC1 watchdog control register high */
-  __IO uint8_t AWCRL;         /*!< ADC1 watchdog control register low */
- }
- ADC1_TypeDef;
-
-/** @addtogroup ADC1_Registers_Reset_Value
-  * @{
-  */
- #define  ADC1_CSR_RESET_VALUE    ((uint8_t)0x00)
- #define  ADC1_CR1_RESET_VALUE    ((uint8_t)0x00)
- #define  ADC1_CR2_RESET_VALUE    ((uint8_t)0x00)
- #define  ADC1_CR3_RESET_VALUE    ((uint8_t)0x00)
- #define  ADC1_TDRL_RESET_VALUE   ((uint8_t)0x00)
- #define  ADC1_TDRH_RESET_VALUE   ((uint8_t)0x00)
- #define  ADC1_HTRL_RESET_VALUE   ((uint8_t)0x03)
- #define  ADC1_HTRH_RESET_VALUE   ((uint8_t)0xFF)
- #define  ADC1_LTRH_RESET_VALUE   ((uint8_t)0x00)
- #define  ADC1_LTRL_RESET_VALUE   ((uint8_t)0x00)
- #define  ADC1_AWCRH_RESET_VALUE  ((uint8_t)0x00)
- #define  ADC1_AWCRL_RESET_VALUE  ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @addtogroup ADC1_Registers_Bits_Definition
-  * @{
-  */
- #define ADC1_CSR_EOC     ((uint8_t)0x80) /*!< End of Conversion mask */
- #define ADC1_CSR_AWD     ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */
- #define ADC1_CSR_EOCIE   ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
- #define ADC1_CSR_AWDIE   ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */
- #define ADC1_CSR_CH      ((uint8_t)0x0F) /*!< Channel selection bits mask */
-
- #define ADC1_CR1_SPSEL   ((uint8_t)0x70) /*!< Prescaler selection mask */
- #define ADC1_CR1_CONT    ((uint8_t)0x02) /*!< Continuous conversion mask */
- #define ADC1_CR1_ADON    ((uint8_t)0x01) /*!< A/D Converter on/off mask */
-
- #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
- #define ADC1_CR2_EXTSEL  ((uint8_t)0x30) /*!< External event selection mask */
- #define ADC1_CR2_ALIGN   ((uint8_t)0x08) /*!< Data Alignment mask */
- #define ADC1_CR2_SCAN    ((uint8_t)0x02) /*!< Scan mode mask */
-
- #define ADC1_CR3_DBUF    ((uint8_t)0x80) /*!< Data Buffer Enable mask */
- #define ADC1_CR3_OVR     ((uint8_t)0x40) /*!< Overrun Status Flag mask */
-
-#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Analog to Digital Converter (ADC2)
-  */
-#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
- typedef struct ADC2_struct
- {
-  __IO uint8_t CSR;        /*!< ADC2 control status register */
-  __IO uint8_t CR1;        /*!< ADC2 configuration register 1 */
-  __IO uint8_t CR2;        /*!< ADC2 configuration register 2 */
-  uint8_t RESERVED;        /*!< Reserved byte */
-  __IO uint8_t DRH;        /*!< ADC2 Data high */
-  __IO uint8_t DRL;        /*!< ADC2 Data low */
-  __IO uint8_t TDRH;       /*!< ADC2 Schmitt trigger disable register high  */
-  __IO uint8_t TDRL;       /*!< ADC2 Schmitt trigger disable register low */
- }
- ADC2_TypeDef;
-
-/** @addtogroup ADC2_Registers_Reset_Value
-  * @{
-  */
- #define  ADC2_CSR_RESET_VALUE  ((uint8_t)0x00)
- #define  ADC2_CR1_RESET_VALUE  ((uint8_t)0x00)
- #define  ADC2_CR2_RESET_VALUE  ((uint8_t)0x00)
- #define  ADC2_TDRL_RESET_VALUE ((uint8_t)0x00)
- #define  ADC2_TDRH_RESET_VALUE ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @addtogroup ADC2_Registers_Bits_Definition
-  * @{
-  */
- #define ADC2_CSR_EOC     ((uint8_t)0x80) /*!< End of Conversion mask */
- #define ADC2_CSR_EOCIE   ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
- #define ADC2_CSR_CH      ((uint8_t)0x0F) /*!< Channel selection bits mask */
-
- #define ADC2_CR1_SPSEL   ((uint8_t)0x70) /*!< Prescaler selection mask */
- #define ADC2_CR1_CONT    ((uint8_t)0x02) /*!< Continuous conversion mask */
- #define ADC2_CR1_ADON    ((uint8_t)0x01) /*!< A/D Converter on/off mask */
-
- #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
- #define ADC2_CR2_EXTSEL  ((uint8_t)0x30) /*!< External event selection mask */
- #define ADC2_CR2_ALIGN   ((uint8_t)0x08) /*!< Data Alignment mask */
-
-#endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @brief  Auto Wake Up (AWU) peripheral registers.
-  */
-typedef struct AWU_struct
-{
-  __IO uint8_t CSR; /*!< AWU Control status register */
-  __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */
-  __IO uint8_t TBR; /*!< AWU Time base selection register */
-}
-AWU_TypeDef;
-
-/** @addtogroup AWU_Registers_Reset_Value
-  * @{
-  */
-#define AWU_CSR_RESET_VALUE ((uint8_t)0x00)
-#define AWU_APR_RESET_VALUE ((uint8_t)0x3F)
-#define AWU_TBR_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup AWU_Registers_Bits_Definition
-  * @{
-  */
-
-#define AWU_CSR_AWUF    ((uint8_t)0x20) /*!< Interrupt flag mask */
-#define AWU_CSR_AWUEN   ((uint8_t)0x10) /*!< Auto Wake-up enable mask */
-#define AWU_CSR_MSR     ((uint8_t)0x01) /*!< LSI Measurement enable mask */
-
-#define AWU_APR_APR     ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */
-
-#define AWU_TBR_AWUTB   ((uint8_t)0x0F) /*!< Timebase selection mask */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Beeper (BEEP) peripheral registers.
-  */
-
-typedef struct BEEP_struct
-{
-  __IO uint8_t CSR; /*!< BEEP Control status register */
-}
-BEEP_TypeDef;
-
-/** @addtogroup BEEP_Registers_Reset_Value
-  * @{
-  */
-#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)
-/**
-  * @}
-  */
-
-/** @addtogroup BEEP_Registers_Bits_Definition
-  * @{
-  */
-#define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */
-#define BEEP_CSR_BEEPEN  ((uint8_t)0x20) /*!< Beeper enable mask */
-#define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Clock Controller (CLK)
-  */
-typedef struct CLK_struct
-{
-  __IO uint8_t ICKR;     /*!< Internal Clocks Control Register */
-  __IO uint8_t ECKR;     /*!< External Clocks Control Register */
-  uint8_t RESERVED;      /*!< Reserved byte */
-  __IO uint8_t CMSR;     /*!< Clock Master Status Register */
-  __IO uint8_t SWR;      /*!< Clock Master Switch Register */
-  __IO uint8_t SWCR;     /*!< Switch Control Register */
-  __IO uint8_t CKDIVR;   /*!< Clock Divider Register */
-  __IO uint8_t PCKENR1;  /*!< Peripheral Clock Gating Register 1 */
-  __IO uint8_t CSSR;     /*!< Clock Security System Register */
-  __IO uint8_t CCOR;     /*!< Configurable Clock Output Register */
-  __IO uint8_t PCKENR2;  /*!< Peripheral Clock Gating Register 2 */
-  uint8_t RESERVED1;     /*!< Reserved byte */
-  __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */
-  __IO uint8_t SWIMCCR;  /*!< SWIM clock control register */
-}
-CLK_TypeDef;
-
-/** @addtogroup CLK_Registers_Reset_Value
-  * @{
-  */
-
-#define CLK_ICKR_RESET_VALUE     ((uint8_t)0x01)
-#define CLK_ECKR_RESET_VALUE     ((uint8_t)0x00)
-#define CLK_CMSR_RESET_VALUE     ((uint8_t)0xE1)
-#define CLK_SWR_RESET_VALUE      ((uint8_t)0xE1)
-#define CLK_SWCR_RESET_VALUE     ((uint8_t)0x00)
-#define CLK_CKDIVR_RESET_VALUE   ((uint8_t)0x18)
-#define CLK_PCKENR1_RESET_VALUE  ((uint8_t)0xFF)
-#define CLK_PCKENR2_RESET_VALUE  ((uint8_t)0xFF)
-#define CLK_CSSR_RESET_VALUE     ((uint8_t)0x00)
-#define CLK_CCOR_RESET_VALUE     ((uint8_t)0x00)
-#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
-#define CLK_SWIMCCR_RESET_VALUE  ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup CLK_Registers_Bits_Definition
-  * @{
-  */
-#define CLK_ICKR_SWUAH       ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */
-#define CLK_ICKR_LSIRDY      ((uint8_t)0x10) /*!< Low speed internal oscillator ready */
-#define CLK_ICKR_LSIEN       ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */
-#define CLK_ICKR_FHWU        ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */
-#define CLK_ICKR_HSIRDY      ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */
-#define CLK_ICKR_HSIEN       ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */
-
-#define CLK_ECKR_HSERDY      ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */
-#define CLK_ECKR_HSEEN       ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */
-
-#define CLK_CMSR_CKM         ((uint8_t)0xFF) /*!< Clock master status bits */
-
-#define CLK_SWR_SWI          ((uint8_t)0xFF) /*!< Clock master selection bits */
-
-#define CLK_SWCR_SWIF        ((uint8_t)0x08) /*!< Clock switch interrupt flag */
-#define CLK_SWCR_SWIEN       ((uint8_t)0x04) /*!< Clock switch interrupt enable */
-#define CLK_SWCR_SWEN        ((uint8_t)0x02) /*!< Switch start/stop */
-#define CLK_SWCR_SWBSY       ((uint8_t)0x01) /*!< Switch busy flag*/
-
-#define CLK_CKDIVR_HSIDIV    ((uint8_t)0x18) /*!< High speed internal clock prescaler */
-#define CLK_CKDIVR_CPUDIV    ((uint8_t)0x07) /*!< CPU clock prescaler */
-
-#define CLK_PCKENR1_TIM1     ((uint8_t)0x80) /*!< Timer 1 clock enable */
-#define CLK_PCKENR1_TIM3     ((uint8_t)0x40) /*!< Timer 3 clock enable */
-#define CLK_PCKENR1_TIM2     ((uint8_t)0x20) /*!< Timer 2 clock enable */
-#define CLK_PCKENR1_TIM5     ((uint8_t)0x20) /*!< Timer 5 clock enable */
-#define CLK_PCKENR1_TIM4     ((uint8_t)0x10) /*!< Timer 4 clock enable */
-#define CLK_PCKENR1_TIM6     ((uint8_t)0x10) /*!< Timer 6 clock enable */
-#define CLK_PCKENR1_UART3    ((uint8_t)0x08) /*!< UART3 clock enable */
-#define CLK_PCKENR1_UART2    ((uint8_t)0x08) /*!< UART2 clock enable */
-#define CLK_PCKENR1_UART1    ((uint8_t)0x04) /*!< UART1 clock enable */
-#define CLK_PCKENR1_SPI      ((uint8_t)0x02) /*!< SPI clock enable */
-#define CLK_PCKENR1_I2C      ((uint8_t)0x01) /*!< I2C clock enable */
-
-#define CLK_PCKENR2_CAN      ((uint8_t)0x80) /*!< CAN clock enable */
-#define CLK_PCKENR2_ADC      ((uint8_t)0x08) /*!< ADC clock enable */
-#define CLK_PCKENR2_AWU      ((uint8_t)0x04) /*!< AWU clock enable */
-
-#define CLK_CSSR_CSSD        ((uint8_t)0x08) /*!< Clock security system detection */
-#define CLK_CSSR_CSSDIE      ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */
-#define CLK_CSSR_AUX         ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */
-#define CLK_CSSR_CSSEN       ((uint8_t)0x01) /*!< Clock security system enable */
-
-#define CLK_CCOR_CCOBSY      ((uint8_t)0x40) /*!< Configurable clock output busy */
-#define CLK_CCOR_CCORDY      ((uint8_t)0x20) /*!< Configurable clock output ready */
-#define CLK_CCOR_CCOSEL      ((uint8_t)0x1E) /*!< Configurable clock output selection */
-#define CLK_CCOR_CCOEN       ((uint8_t)0x01) /*!< Configurable clock output enable */
-
-#define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */
-
-#define CLK_SWIMCCR_SWIMDIV  ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  16-bit timer with complementary PWM outputs (TIM1)
-  */
-
-typedef struct TIM1_struct
-{
-  __IO uint8_t CR1;   /*!< control register 1 */
-  __IO uint8_t CR2;   /*!< control register 2 */
-  __IO uint8_t SMCR;  /*!< Synchro mode control register */
-  __IO uint8_t ETR;   /*!< external trigger register */
-  __IO uint8_t IER;   /*!< interrupt enable register*/
-  __IO uint8_t SR1;   /*!< status register 1 */
-  __IO uint8_t SR2;   /*!< status register 2 */
-  __IO uint8_t EGR;   /*!< event generation register */
-  __IO uint8_t CCMR1; /*!< CC mode register 1 */
-  __IO uint8_t CCMR2; /*!< CC mode register 2 */
-  __IO uint8_t CCMR3; /*!< CC mode register 3 */
-  __IO uint8_t CCMR4; /*!< CC mode register 4 */
-  __IO uint8_t CCER1; /*!< CC enable register 1 */
-  __IO uint8_t CCER2; /*!< CC enable register 2 */
-  __IO uint8_t CNTRH; /*!< counter high */
-  __IO uint8_t CNTRL; /*!< counter low */
-  __IO uint8_t PSCRH; /*!< prescaler high */
-  __IO uint8_t PSCRL; /*!< prescaler low */
-  __IO uint8_t ARRH;  /*!< auto-reload register high */
-  __IO uint8_t ARRL;  /*!< auto-reload register low */
-  __IO uint8_t RCR;   /*!< Repetition Counter register */
-  __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
-  __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
-  __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
-  __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
-  __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
-  __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
-  __IO uint8_t CCR4H; /*!< capture/compare register 3 high */
-  __IO uint8_t CCR4L; /*!< capture/compare register 3 low */
-  __IO uint8_t BKR;   /*!< Break Register */
-  __IO uint8_t DTR;   /*!< dead-time register */
-  __IO uint8_t OISR;  /*!< Output idle register */
-}
-TIM1_TypeDef;
-
-/** @addtogroup TIM1_Registers_Reset_Value
-  * @{
-  */
-
-#define TIM1_CR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_CR2_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_SMCR_RESET_VALUE  ((uint8_t)0x00)
-#define TIM1_ETR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_IER_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_SR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_SR2_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_EGR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_ARRH_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM1_ARRL_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM1_RCR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
-#define TIM1_BKR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_DTR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM1_OISR_RESET_VALUE  ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM1_Registers_Bits_Definition
-  * @{
-  */
-/* CR1*/
-#define TIM1_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
-#define TIM1_CR1_CMS     ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */
-#define TIM1_CR1_DIR     ((uint8_t)0x10) /*!< Direction mask. */
-#define TIM1_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
-#define TIM1_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
-#define TIM1_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
-#define TIM1_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
-/* CR2*/
-#define TIM1_CR2_TI1S    ((uint8_t)0x80) /*!< TI1S Selection mask. */
-#define TIM1_CR2_MMS     ((uint8_t)0x70) /*!< MMS Selection mask. */
-#define TIM1_CR2_COMS    ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */
-#define TIM1_CR2_CCPC    ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */
-/* SMCR*/
-#define TIM1_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode mask. */
-#define TIM1_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection mask. */
-#define TIM1_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection mask. */
-/*ETR*/
-#define TIM1_ETR_ETP     ((uint8_t)0x80) /*!< External Trigger Polarity mask. */
-#define TIM1_ETR_ECE     ((uint8_t)0x40)/*!< External Clock mask. */
-#define TIM1_ETR_ETPS    ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */
-#define TIM1_ETR_ETF     ((uint8_t)0x0F) /*!< External Trigger Filter mask. */
-/*IER*/
-#define TIM1_IER_BIE     ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */
-#define TIM1_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
-#define TIM1_IER_COMIE   ((uint8_t)0x20) /*!<  Commutation Interrupt Enable mask.*/
-#define TIM1_IER_CC4IE   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */
-#define TIM1_IER_CC3IE   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
-#define TIM1_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
-#define TIM1_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
-#define TIM1_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
-/*SR1*/
-#define TIM1_SR1_BIF     ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */
-#define TIM1_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
-#define TIM1_SR1_COMIF   ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */
-#define TIM1_SR1_CC4IF   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */
-#define TIM1_SR1_CC3IF   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
-#define TIM1_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
-#define TIM1_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
-#define TIM1_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
-/*SR2*/
-#define TIM1_SR2_CC4OF   ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */
-#define TIM1_SR2_CC3OF   ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
-#define TIM1_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
-#define TIM1_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
-/*EGR*/
-#define TIM1_EGR_BG      ((uint8_t)0x80) /*!< Break Generation mask. */
-#define TIM1_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation mask. */
-#define TIM1_EGR_COMG    ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */
-#define TIM1_EGR_CC4G    ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */
-#define TIM1_EGR_CC3G    ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
-#define TIM1_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
-#define TIM1_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
-#define TIM1_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
-/*CCMR*/
-#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
-#define TIM1_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
-#define TIM1_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
-#define TIM1_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
-#define TIM1_CCMR_OCxFE  ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */
-#define TIM1_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
-
-#define CCMR_TIxDirect_Set ((uint8_t)0x01)
-/*CCER1*/
-#define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */
-#define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */
-#define TIM1_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
-#define TIM1_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
-#define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */
-#define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */
-#define TIM1_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
-#define TIM1_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
-/*CCER2*/
-#define TIM1_CCER2_CC4P  ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */
-#define TIM1_CCER2_CC4E  ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */
-#define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */
-#define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */
-#define TIM1_CCER2_CC3P  ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
-#define TIM1_CCER2_CC3E  ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
-/*CNTRH*/
-#define TIM1_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
-/*CNTRL*/
-#define TIM1_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
-/*PSCH*/
-#define TIM1_PSCH_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
-/*PSCL*/
-#define TIM1_PSCL_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */
-/*ARR*/
-#define TIM1_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
-#define TIM1_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
-/*RCR*/
-#define TIM1_RCR_REP     ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */
-/*CCR1*/
-#define TIM1_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
-#define TIM1_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
-/*CCR2*/
-#define TIM1_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
-#define TIM1_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
-/*CCR3*/
-#define TIM1_CCR3H_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
-#define TIM1_CCR3L_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
-/*CCR4*/
-#define TIM1_CCR4H_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */
-#define TIM1_CCR4L_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */
-/*BKR*/
-#define TIM1_BKR_MOE     ((uint8_t)0x80) /*!< Main Output Enable mask. */
-#define TIM1_BKR_AOE     ((uint8_t)0x40) /*!< Automatic Output Enable mask. */
-#define TIM1_BKR_BKP     ((uint8_t)0x20) /*!< Break Polarity mask. */
-#define TIM1_BKR_BKE     ((uint8_t)0x10) /*!< Break Enable mask. */
-#define TIM1_BKR_OSSR    ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */
-#define TIM1_BKR_OSSI    ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */
-#define TIM1_BKR_LOCK    ((uint8_t)0x03) /*!< Lock Configuration mask. */
-/*DTR*/
-#define TIM1_DTR_DTG     ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */
-/*OISR*/
-#define TIM1_OISR_OIS4   ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */
-#define TIM1_OISR_OIS3N  ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */
-#define TIM1_OISR_OIS3   ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */
-#define TIM1_OISR_OIS2N  ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */
-#define TIM1_OISR_OIS2   ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */
-#define TIM1_OISR_OIS1N  ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */
-#define TIM1_OISR_OIS1   ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  16-bit timer (TIM2)
-  */
-
-typedef struct TIM2_struct
-{
-  __IO uint8_t CR1;   /*!< control register 1 */
-#if defined(STM8S103) || defined(STM8S003)
-	uint8_t RESERVED1; /*!< Reserved register */
-	uint8_t RESERVED2; /*!< Reserved register */
-#endif
-  __IO uint8_t IER;   /*!< interrupt enable register */
-  __IO uint8_t SR1;   /*!< status register 1 */
-  __IO uint8_t SR2;   /*!< status register 2 */
-  __IO uint8_t EGR;   /*!< event generation register */
-  __IO uint8_t CCMR1; /*!< CC mode register 1 */
-  __IO uint8_t CCMR2; /*!< CC mode register 2 */
-  __IO uint8_t CCMR3; /*!< CC mode register 3 */
-  __IO uint8_t CCER1; /*!< CC enable register 1 */
-  __IO uint8_t CCER2; /*!< CC enable register 2 */
-  __IO uint8_t CNTRH; /*!< counter high */
-  __IO uint8_t CNTRL; /*!< counter low */
-  __IO uint8_t PSCR;  /*!< prescaler register */
-  __IO uint8_t ARRH;  /*!< auto-reload register high */
-  __IO uint8_t ARRL;  /*!< auto-reload register low */
-  __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
-  __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
-  __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
-  __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
-  __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
-  __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
-}
-TIM2_TypeDef;
-
-/** @addtogroup TIM2_Registers_Reset_Value
-  * @{
-  */
-
-#define TIM2_CR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM2_IER_RESET_VALUE   ((uint8_t)0x00)
-#define TIM2_SR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM2_SR2_RESET_VALUE   ((uint8_t)0x00)
-#define TIM2_EGR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_PSCR_RESET_VALUE  ((uint8_t)0x00)
-#define TIM2_ARRH_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM2_ARRL_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
-#define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM2_Registers_Bits_Definition
-  * @{
-  */
-/*CR1*/
-#define TIM2_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
-#define TIM2_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
-#define TIM2_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
-#define TIM2_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
-#define TIM2_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
-/*IER*/
-#define TIM2_IER_CC3IE   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
-#define TIM2_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
-#define TIM2_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
-#define TIM2_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
-/*SR1*/
-#define TIM2_SR1_CC3IF   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
-#define TIM2_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
-#define TIM2_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
-#define TIM2_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
-/*SR2*/
-#define TIM2_SR2_CC3OF   ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
-#define TIM2_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
-#define TIM2_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
-/*EGR*/
-#define TIM2_EGR_CC3G    ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
-#define TIM2_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
-#define TIM2_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
-#define TIM2_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
-/*CCMR*/
-#define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
-#define TIM2_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
-#define TIM2_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
-#define TIM2_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
-#define TIM2_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
-/*CCER1*/
-#define TIM2_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
-#define TIM2_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
-#define TIM2_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
-#define TIM2_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
-/*CCER2*/
-#define TIM2_CCER2_CC3P  ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
-#define TIM2_CCER2_CC3E  ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
-/*CNTR*/
-#define TIM2_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
-#define TIM2_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
-/*PSCR*/
-#define TIM2_PSCR_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
-/*ARR*/
-#define TIM2_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
-#define TIM2_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
-/*CCR1*/
-#define TIM2_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
-#define TIM2_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
-/*CCR2*/
-#define TIM2_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
-#define TIM2_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
-/*CCR3*/
-#define TIM2_CCR3H_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
-#define TIM2_CCR3L_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  16-bit timer (TIM3)
-  */
-typedef struct TIM3_struct
-{
-  __IO uint8_t CR1;   /*!< control register 1 */
-  __IO uint8_t IER;   /*!< interrupt enable register */
-  __IO uint8_t SR1;   /*!< status register 1 */
-  __IO uint8_t SR2;   /*!< status register 2 */
-  __IO uint8_t EGR;   /*!< event generation register */
-  __IO uint8_t CCMR1; /*!< CC mode register 1 */
-  __IO uint8_t CCMR2; /*!< CC mode register 2 */
-  __IO uint8_t CCER1; /*!< CC enable register 1 */
-  __IO uint8_t CNTRH; /*!< counter high */
-  __IO uint8_t CNTRL; /*!< counter low */
-  __IO uint8_t PSCR;  /*!< prescaler register */
-  __IO uint8_t ARRH;  /*!< auto-reload register high */
-  __IO uint8_t ARRL;  /*!< auto-reload register low */
-  __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
-  __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
-  __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
-  __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
-}
-TIM3_TypeDef;
-
-/** @addtogroup TIM3_Registers_Reset_Value
-  * @{
-  */
-
-#define TIM3_CR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM3_IER_RESET_VALUE   ((uint8_t)0x00)
-#define TIM3_SR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM3_SR2_RESET_VALUE   ((uint8_t)0x00)
-#define TIM3_EGR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
-#define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
-#define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
-#define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
-#define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
-#define TIM3_PSCR_RESET_VALUE  ((uint8_t)0x00)
-#define TIM3_ARRH_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM3_ARRL_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
-#define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
-#define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
-#define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM3_Registers_Bits_Definition
-  * @{
-  */
-/*CR1*/
-#define TIM3_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
-#define TIM3_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
-#define TIM3_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
-#define TIM3_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
-#define TIM3_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
-/*IER*/
-#define TIM3_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
-#define TIM3_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
-#define TIM3_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
-/*SR1*/
-#define TIM3_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
-#define TIM3_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
-#define TIM3_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
-/*SR2*/
-#define TIM3_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
-#define TIM3_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
-/*EGR*/
-#define TIM3_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
-#define TIM3_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
-#define TIM3_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
-/*CCMR*/
-#define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
-#define TIM3_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
-#define TIM3_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
-#define TIM3_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
-#define TIM3_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
-/*CCER1*/
-#define TIM3_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
-#define TIM3_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
-#define TIM3_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
-#define TIM3_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
-/*CNTR*/
-#define TIM3_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
-#define TIM3_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
-/*PSCR*/
-#define TIM3_PSCR_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
-/*ARR*/
-#define TIM3_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
-#define TIM3_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
-/*CCR1*/
-#define TIM3_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
-#define TIM3_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
-/*CCR2*/
-#define TIM3_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
-#define TIM3_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  8-bit system timer (TIM4)
-  */
-
-typedef struct TIM4_struct
-{
-  __IO uint8_t CR1;  /*!< control register 1 */
-#if defined(STM8S103) || defined(STM8S003)
-	uint8_t RESERVED1; /*!< Reserved register */
-	uint8_t RESERVED2; /*!< Reserved register */
-#endif
-  __IO uint8_t IER;  /*!< interrupt enable register */
-  __IO uint8_t SR1;  /*!< status register 1 */
-  __IO uint8_t EGR;  /*!< event generation register */
-  __IO uint8_t CNTR; /*!< counter register */
-  __IO uint8_t PSCR; /*!< prescaler register */
-  __IO uint8_t ARR;  /*!< auto-reload register */
-}
-TIM4_TypeDef;
-
-/** @addtogroup TIM4_Registers_Reset_Value
-  * @{
-  */
-
-#define TIM4_CR1_RESET_VALUE  ((uint8_t)0x00)
-#define TIM4_IER_RESET_VALUE  ((uint8_t)0x00)
-#define TIM4_SR1_RESET_VALUE  ((uint8_t)0x00)
-#define TIM4_EGR_RESET_VALUE  ((uint8_t)0x00)
-#define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
-#define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
-#define TIM4_ARR_RESET_VALUE  ((uint8_t)0xFF)
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM4_Registers_Bits_Definition
-  * @{
-  */
-/*CR1*/
-#define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
-#define TIM4_CR1_OPM  ((uint8_t)0x08) /*!< One Pulse Mode mask. */
-#define TIM4_CR1_URS  ((uint8_t)0x04) /*!< Update Request Source mask. */
-#define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
-#define TIM4_CR1_CEN  ((uint8_t)0x01) /*!< Counter Enable mask. */
-/*IER*/
-#define TIM4_IER_UIE  ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
-/*SR1*/
-#define TIM4_SR1_UIF  ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
-/*EGR*/
-#define TIM4_EGR_UG   ((uint8_t)0x01) /*!< Update Generation mask. */
-/*CNTR*/
-#define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
-/*PSCR*/
-#define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value  mask. */
-/*ARR*/
-#define TIM4_ARR_ARR  ((uint8_t)0xFF) /*!< Autoreload Value mask. */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  16-bit timer with synchro module (TIM5)
-  */
-
-typedef struct TIM5_struct
-{
-  __IO uint8_t CR1;       /*!<TIM5 Control Register 1                */
-  __IO uint8_t CR2;       /*!<TIM5 Control Register 2                */
-  __IO uint8_t SMCR;      /*!<TIM5 Slave Mode Control Register       */
-  __IO uint8_t IER;       /*!<TIM5 Interrupt Enable Register         */
-  __IO uint8_t SR1;       /*!<TIM5 Status Register 1                 */
-  __IO uint8_t SR2;       /*!<TIM5 Status Register 2                 */
-  __IO uint8_t EGR;       /*!<TIM5 Event Generation Register         */
-  __IO uint8_t CCMR1;     /*!<TIM5 Capture/Compare Mode Register 1   */
-  __IO uint8_t CCMR2;     /*!<TIM5 Capture/Compare Mode Register 2   */
-  __IO uint8_t CCMR3;     /*!<TIM5 Capture/Compare Mode Register 3   */
-  __IO uint8_t CCER1;     /*!<TIM5 Capture/Compare Enable Register 1 */
-  __IO uint8_t CCER2;     /*!<TIM5 Capture/Compare Enable Register 2 */
-  __IO uint8_t CNTRH;     /*!<TIM5 Counter High                      */
-  __IO uint8_t CNTRL;     /*!<TIM5 Counter Low                       */
-  __IO uint8_t PSCR;      /*!<TIM5 Prescaler Register                */
-  __IO uint8_t ARRH;      /*!<TIM5 Auto-Reload Register High         */
-  __IO uint8_t ARRL;      /*!<TIM5 Auto-Reload Register Low          */
-  __IO uint8_t CCR1H;     /*!<TIM5 Capture/Compare Register 1 High   */
-  __IO uint8_t CCR1L;     /*!<TIM5 Capture/Compare Register 1 Low    */
-  __IO uint8_t CCR2H;     /*!<TIM5 Capture/Compare Register 2 High   */
-  __IO uint8_t CCR2L;     /*!<TIM5 Capture/Compare Register 2 Low    */
-  __IO uint8_t CCR3H;     /*!<TIM5 Capture/Compare Register 3 High   */
-  __IO uint8_t CCR3L;     /*!<TIM5 Capture/Compare Register 3 Low    */
-}TIM5_TypeDef;
-
-/** @addtogroup TIM5_Registers_Reset_Value
-  * @{
-  */
-
-#define TIM5_CR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM5_CR2_RESET_VALUE 	 ((uint8_t)0x00)
-#define TIM5_SMCR_RESET_VALUE	 ((uint8_t)0x00)
-#define TIM5_IER_RESET_VALUE   ((uint8_t)0x00)
-#define TIM5_SR1_RESET_VALUE   ((uint8_t)0x00)
-#define TIM5_SR2_RESET_VALUE   ((uint8_t)0x00)
-#define TIM5_EGR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_PSCR_RESET_VALUE  ((uint8_t)0x00)
-#define TIM5_ARRH_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM5_ARRL_RESET_VALUE  ((uint8_t)0xFF)
-#define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)
-#define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM5_Registers_Bits_Definition
-  * @{
-  */
-/* CR1*/
-#define TIM5_CR1_ARPE           ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
-#define TIM5_CR1_OPM            ((uint8_t)0x08) /*!< One Pulse Mode mask. */
-#define TIM5_CR1_URS            ((uint8_t)0x04) /*!< Update Request Source mask. */
-#define TIM5_CR1_UDIS           ((uint8_t)0x02) /*!< Update DIsable mask. */
-#define TIM5_CR1_CEN            ((uint8_t)0x01) /*!< Counter Enable mask. */
-/* CR2*/
-#define TIM5_CR2_TI1S 	        ((uint8_t)0x80) /*!< TI1S Selection Mask. */
-#define	TIM5_CR2_MMS	          ((uint8_t)0x70) /*!< MMS Selection Mask. */
-/* SMCR*/
-#define TIM5_SMCR_MSM           ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
-#define TIM5_SMCR_TS            ((uint8_t)0x70) /*!< Trigger Selection Mask. */
-#define TIM5_SMCR_SMS           ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
-/*IER*/
-#define TIM5_IER_TIE            ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
-#define TIM5_IER_CC3IE          ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
-#define TIM5_IER_CC2IE          ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
-#define TIM5_IER_CC1IE          ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
-#define TIM5_IER_UIE            ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
-/*SR1*/
-#define TIM5_SR1_TIF            ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
-#define TIM5_SR1_CC3IF          ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
-#define TIM5_SR1_CC2IF          ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
-#define TIM5_SR1_CC1IF          ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
-#define TIM5_SR1_UIF            ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
-/*SR2*/
-#define TIM5_SR2_CC3OF          ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
-#define TIM5_SR2_CC2OF          ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
-#define TIM5_SR2_CC1OF          ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
-/*EGR*/
-#define TIM5_EGR_TG             ((uint8_t)0x40) /*!< Trigger Generation mask. */
-#define TIM5_EGR_CC3G           ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
-#define TIM5_EGR_CC2G           ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
-#define TIM5_EGR_CC1G           ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
-#define TIM5_EGR_UG             ((uint8_t)0x01) /*!< Update Generation mask. */
-/*CCMR*/
-#define TIM5_CCMR_ICxPSC        ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
-#define TIM5_CCMR_ICxF          ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
-#define TIM5_CCMR_OCM           ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
-#define	TIM5_CCMR_OCxPE         ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
-#define TIM5_CCMR_CCxS          ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
-/*CCER1*/
-#define TIM5_CCER1_CC2P         ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
-#define TIM5_CCER1_CC2E         ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
-#define TIM5_CCER1_CC1P         ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
-#define TIM5_CCER1_CC1E         ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
-/*CCER2*/
-#define TIM5_CCER2_CC3P         ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
-#define TIM5_CCER2_CC3E         ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
-/*CNTR*/
-#define TIM5_CNTRH_CNT          ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
-#define TIM5_CNTRL_CNT          ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
-/*PSCR*/
-#define TIM5_PSCR_PSC           ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
-/*ARR*/
-#define TIM5_ARRH_ARR           ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
-#define TIM5_ARRL_ARR           ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
-/*CCR1*/
-#define TIM5_CCR1H_CCR1         ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
-#define TIM5_CCR1L_CCR1         ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
-/*CCR2*/
-#define TIM5_CCR2H_CCR2         ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
-#define TIM5_CCR2L_CCR2         ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
-/*CCR3*/
-#define TIM5_CCR3H_CCR3         ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
-#define TIM5_CCR3L_CCR3         ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
-/*CCMR*/
-#define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)
-/**
-  * @}
-  */
-	
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  8-bit system timer  with synchro module(TIM6)
-  */
-
-typedef struct TIM6_struct
-{
-    __IO uint8_t CR1; 	/*!< control register 1 */
-    __IO uint8_t CR2; 	/*!< control register 2 */
-    __IO uint8_t SMCR; 	/*!< Synchro mode control register */
-    __IO uint8_t IER; 	/*!< interrupt enable register  */
-    __IO uint8_t SR1; 	/*!< status register 1    */
-    __IO uint8_t EGR; 	/*!< event generation register */
-    __IO uint8_t CNTR; 	/*!< counter register  */
-    __IO uint8_t PSCR; 	/*!< prescaler register */
-    __IO uint8_t ARR; 	/*!< auto-reload register */
-}
-TIM6_TypeDef;
-/** @addtogroup TIM6_Registers_Reset_Value
-  * @{
-  */
-#define TIM6_CR1_RESET_VALUE    ((uint8_t)0x00)
-#define TIM6_CR2_RESET_VALUE    ((uint8_t)0x00)
-#define TIM6_SMCR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM6_IER_RESET_VALUE    ((uint8_t)0x00)
-#define TIM6_SR1_RESET_VALUE    ((uint8_t)0x00)
-#define TIM6_EGR_RESET_VALUE    ((uint8_t)0x00)
-#define TIM6_CNTR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM6_PSCR_RESET_VALUE   ((uint8_t)0x00)
-#define TIM6_ARR_RESET_VALUE    ((uint8_t)0xFF)
-
-/**
-* @}
-*/
-
-/** @addtogroup TIM6_Registers_Bits_Definition
-  * @{
-  */
-/* CR1*/
-#define TIM6_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */
-#define TIM6_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode Mask. */
-#define TIM6_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source Mask. */
-#define TIM6_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable Mask. */
-#define TIM6_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable Mask. */
-/* CR2*/
-#define	TIM6_CR2_MMS	   ((uint8_t)0x70) /*!< MMS Selection Mask. */
-/* SMCR*/
-#define TIM6_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
-#define TIM6_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection Mask. */
-#define TIM6_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
-/* IER*/
-#define TIM6_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */
-#define TIM6_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */
-/* SR1*/
-#define TIM6_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
-#define TIM6_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */
-/* EGR*/
-#define TIM6_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation mask. */
-#define TIM6_EGR_UG      ((uint8_t)0x01) /*!< Update Generation Mask. */
-/* CNTR*/
-#define TIM6_CNTR_CNT    ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */
-/* PSCR*/
-#define TIM6_PSCR_PSC    ((uint8_t)0x07) /*!<Prescaler Value  Mask. */
-
-#define TIM6_ARR_ARR 	   ((uint8_t)0xFF) /*!<Autoreload Value Mask. */
-/**
-  * @}
-  */
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Inter-Integrated Circuit (I2C)
-  */
-
-typedef struct I2C_struct
-{
-  __IO uint8_t CR1;       /*!< I2C control register 1 */
-  __IO uint8_t CR2;       /*!< I2C control register 2 */
-  __IO uint8_t FREQR;     /*!< I2C frequency register */
-  __IO uint8_t OARL;      /*!< I2C own address register LSB */
-  __IO uint8_t OARH;      /*!< I2C own address register MSB */
-  uint8_t RESERVED1;      /*!< Reserved byte */
-  __IO uint8_t DR;        /*!< I2C data register */
-  __IO uint8_t SR1;       /*!< I2C status register 1 */
-  __IO uint8_t SR2;       /*!< I2C status register 2 */
-  __IO uint8_t SR3;       /*!< I2C status register 3 */
-  __IO uint8_t ITR;       /*!< I2C interrupt register */
-  __IO uint8_t CCRL;      /*!< I2C clock control register low */
-  __IO uint8_t CCRH;      /*!< I2C clock control register high */
-  __IO uint8_t TRISER;    /*!< I2C maximum rise time register */
-  uint8_t RESERVED2;      /*!< Reserved byte */
-}
-I2C_TypeDef;
-
-/** @addtogroup I2C_Registers_Reset_Value
-  * @{
-  */
-
-#define I2C_CR1_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_CR2_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_FREQR_RESET_VALUE  ((uint8_t)0x00)
-#define I2C_OARL_RESET_VALUE   ((uint8_t)0x00)
-#define I2C_OARH_RESET_VALUE   ((uint8_t)0x00)
-#define I2C_DR_RESET_VALUE     ((uint8_t)0x00)
-#define I2C_SR1_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_SR2_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_SR3_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_ITR_RESET_VALUE    ((uint8_t)0x00)
-#define I2C_CCRL_RESET_VALUE   ((uint8_t)0x00)
-#define I2C_CCRH_RESET_VALUE   ((uint8_t)0x00)
-#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Registers_Bits_Definition
-  * @{
-  */
-
-#define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_ENGC      ((uint8_t)0x40) /*!< General Call Enable */
-#define I2C_CR1_PE        ((uint8_t)0x01) /*!< Peripheral Enable */
-
-#define I2C_CR2_SWRST ((uint8_t)0x80)     /*!< Software Reset */
-#define I2C_CR2_POS   ((uint8_t)0x08)     /*!< Acknowledge */
-#define I2C_CR2_ACK   ((uint8_t)0x04)     /*!< Acknowledge Enable */
-#define I2C_CR2_STOP  ((uint8_t)0x02)     /*!< Stop Generation */
-#define I2C_CR2_START ((uint8_t)0x01)     /*!< Start Generation */
-
-#define I2C_FREQR_FREQ ((uint8_t)0x3F)    /*!< Peripheral Clock Frequency */
-
-#define I2C_OARL_ADD  ((uint8_t)0xFE)     /*!< Interface Address bits [7..1] */
-#define I2C_OARL_ADD0 ((uint8_t)0x01)     /*!< Interface Address bit0 */
-
-#define I2C_OARH_ADDMODE ((uint8_t)0x80)  /*!< Addressing Mode (Slave mode) */
-#define I2C_OARH_ADDCONF ((uint8_t)0x40)  /*!< Address Mode Configuration */
-#define I2C_OARH_ADD     ((uint8_t)0x06)  /*!< Interface Address bits [9..8] */
-
-#define I2C_DR_DR        ((uint8_t)0xFF)  /*!< Data Register */
-
-#define I2C_SR1_TXE      ((uint8_t)0x80)  /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_RXNE     ((uint8_t)0x40)  /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_STOPF    ((uint8_t)0x10)  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_ADD10    ((uint8_t)0x08)  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_BTF      ((uint8_t)0x04)  /*!< Byte Transfer Finished */
-#define I2C_SR1_ADDR     ((uint8_t)0x02)  /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_SB       ((uint8_t)0x01)  /*!< Start Bit (Master mode) */
-
-#define I2C_SR2_WUFH     ((uint8_t)0x20)  /*!< Wake-up from Halt */
-#define I2C_SR2_OVR      ((uint8_t)0x08)  /*!< Overrun/Underrun */
-#define I2C_SR2_AF       ((uint8_t)0x04)  /*!< Acknowledge Failure */
-#define I2C_SR2_ARLO     ((uint8_t)0x02)  /*!< Arbitration Lost (master mode) */
-#define I2C_SR2_BERR     ((uint8_t)0x01)  /*!< Bus Error */
-
-#define I2C_SR3_GENCALL  ((uint8_t)0x10)  /*!< General Call Header (Slave mode) */
-#define I2C_SR3_TRA      ((uint8_t)0x04)  /*!< Transmitter/Receiver */
-#define I2C_SR3_BUSY     ((uint8_t)0x02)  /*!< Bus Busy */
-#define I2C_SR3_MSL      ((uint8_t)0x01)  /*!< Master/Slave */
-
-#define I2C_ITR_ITBUFEN  ((uint8_t)0x04)  /*!< Buffer Interrupt Enable */
-#define I2C_ITR_ITEVTEN  ((uint8_t)0x02)  /*!< Event Interrupt Enable */
-#define I2C_ITR_ITERREN  ((uint8_t)0x01)  /*!< Error Interrupt Enable */
-
-#define I2C_CCRL_CCR     ((uint8_t)0xFF)  /*!< Clock Control Register (Master mode) */
-
-#define I2C_CCRH_FS      ((uint8_t)0x80)  /*!< Master Mode Selection */
-#define I2C_CCRH_DUTY    ((uint8_t)0x40)  /*!< Fast Mode Duty Cycle */
-#define I2C_CCRH_CCR     ((uint8_t)0x0F)  /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */
-
-#define I2C_TRISER_TRISE ((uint8_t)0x3F)  /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Interrupt Controller (ITC)
-  */
-
-typedef struct ITC_struct
-{
-  __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */
-  __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */
-  __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */
-  __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */
-  __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */
-  __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */
-  __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */
-  __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */
-}
-ITC_TypeDef;
-
-/** @addtogroup ITC_Registers_Reset_Value
-  * @{
-  */
-
-#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers */
-
-/**
-  * @}
-  */
-
-/** @addtogroup CPU_Registers_Bits_Definition
-  * @{
-  */
-
-#define CPU_CC_I1I0 ((uint8_t)0x28) /*!< Condition Code register, I1 and I0 bits mask */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  External Interrupt Controller (EXTI)
-  */
-
-typedef struct EXTI_struct
-{
-  __IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */
-  __IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */
-}
-EXTI_TypeDef;
-
-/** @addtogroup EXTI_Registers_Reset_Value
-  * @{
-  */
-
-#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
-#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup EXTI_Registers_Bits_Definition
-  * @{
-  */
-
-#define EXTI_CR1_PDIS ((uint8_t)0xC0) /*!< PORTD external interrupt sensitivity bits mask */
-#define EXTI_CR1_PCIS ((uint8_t)0x30) /*!< PORTC external interrupt sensitivity bits mask */
-#define EXTI_CR1_PBIS ((uint8_t)0x0C) /*!< PORTB external interrupt sensitivity bits mask */
-#define EXTI_CR1_PAIS ((uint8_t)0x03) /*!< PORTA external interrupt sensitivity bits mask */
-
-#define EXTI_CR2_TLIS ((uint8_t)0x04) /*!< Top level interrupt sensitivity bit mask */
-#define EXTI_CR2_PEIS ((uint8_t)0x03) /*!< PORTE external interrupt sensitivity bits mask */
-
-/**
-  * @}
-  */
-
-
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  FLASH program and Data memory (FLASH)
-  */
-
-typedef struct FLASH_struct
-{
-  __IO uint8_t CR1;       /*!< Flash control register 1 */
-  __IO uint8_t CR2;       /*!< Flash control register 2 */
-  __IO uint8_t NCR2;      /*!< Flash complementary control register 2 */
-  __IO uint8_t FPR;       /*!< Flash protection register */
-  __IO uint8_t NFPR;      /*!< Flash complementary protection register */
-  __IO uint8_t IAPSR;     /*!< Flash in-application programming status register */
-  uint8_t RESERVED1;      /*!< Reserved byte */
-  uint8_t RESERVED2;      /*!< Reserved byte */
-  __IO uint8_t PUKR;      /*!< Flash program memory unprotection register */
-  uint8_t RESERVED3;      /*!< Reserved byte */
-  __IO uint8_t DUKR;      /*!< Data EEPROM unprotection register */
-}
-FLASH_TypeDef;
-
-/** @addtogroup FLASH_Registers_Reset_Value
-  * @{
-  */
-
-#define FLASH_CR1_RESET_VALUE   ((uint8_t)0x00)
-#define FLASH_CR2_RESET_VALUE   ((uint8_t)0x00)
-#define FLASH_NCR2_RESET_VALUE  ((uint8_t)0xFF)
-#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
-#define FLASH_PUKR_RESET_VALUE  ((uint8_t)0x00)
-#define FLASH_DUKR_RESET_VALUE  ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Registers_Bits_Definition
-  * @{
-  */
-
-#define FLASH_CR1_HALT        ((uint8_t)0x08) /*!< Standby in Halt mode mask */
-#define FLASH_CR1_AHALT       ((uint8_t)0x04) /*!< Standby in Active Halt mode mask */
-#define FLASH_CR1_IE          ((uint8_t)0x02) /*!< Flash Interrupt enable mask */
-#define FLASH_CR1_FIX         ((uint8_t)0x01) /*!< Fix programming time mask */
-
-#define FLASH_CR2_OPT         ((uint8_t)0x80) /*!< Select option byte mask */
-#define FLASH_CR2_WPRG        ((uint8_t)0x40) /*!< Word Programming mask */
-#define FLASH_CR2_ERASE       ((uint8_t)0x20) /*!< Erase block mask */
-#define FLASH_CR2_FPRG        ((uint8_t)0x10) /*!< Fast programming mode mask */
-#define FLASH_CR2_PRG         ((uint8_t)0x01) /*!< Program block mask */
-
-#define FLASH_NCR2_NOPT       ((uint8_t)0x80) /*!< Select option byte mask */
-#define FLASH_NCR2_NWPRG      ((uint8_t)0x40) /*!< Word Programming mask */
-#define FLASH_NCR2_NERASE     ((uint8_t)0x20) /*!< Erase block mask */
-#define FLASH_NCR2_NFPRG      ((uint8_t)0x10) /*!< Fast programming mode mask */
-#define FLASH_NCR2_NPRG       ((uint8_t)0x01) /*!< Program block mask */
-
-#define FLASH_IAPSR_HVOFF     ((uint8_t)0x40) /*!< End of high voltage flag mask */
-#define FLASH_IAPSR_DUL       ((uint8_t)0x08) /*!< Data EEPROM unlocked flag mask */
-#define FLASH_IAPSR_EOP       ((uint8_t)0x04) /*!< End of operation flag mask */
-#define FLASH_IAPSR_PUL       ((uint8_t)0x02) /*!< Flash Program memory unlocked flag mask */
-#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page mask */
-
-#define FLASH_PUKR_PUK        ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */
-
-#define FLASH_DUKR_DUK        ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Option Bytes (OPT)
-  */
-typedef struct OPT_struct
-{
-  __IO uint8_t OPT0;  /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */
-  __IO uint8_t OPT1;  /*!< Option byte 1: User boot code */
-  __IO uint8_t NOPT1; /*!< Complementary Option byte 1 */
-  __IO uint8_t OPT2;  /*!< Option byte 2: Alternate function remapping */
-  __IO uint8_t NOPT2; /*!< Complementary Option byte 2 */
-  __IO uint8_t OPT3;  /*!< Option byte 3: Watchdog option */
-  __IO uint8_t NOPT3; /*!< Complementary Option byte 3 */
-  __IO uint8_t OPT4;  /*!< Option byte 4: Clock option */
-  __IO uint8_t NOPT4; /*!< Complementary Option byte 4 */
-  __IO uint8_t OPT5;  /*!< Option byte 5: HSE clock startup */
-  __IO uint8_t NOPT5; /*!< Complementary Option byte 5 */
-  uint8_t RESERVED1;  /*!< Reserved Option byte*/
-  uint8_t RESERVED2; /*!< Reserved Option byte*/
-  __IO uint8_t OPT7;  /*!< Option byte 7: flash wait states */
-  __IO uint8_t NOPT7; /*!< Complementary Option byte 7 */
-}
-OPT_TypeDef;
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Independent Watchdog (IWDG)
-  */
-
-typedef struct IWDG_struct
-{
-  __IO uint8_t KR;  /*!< Key Register */
-  __IO uint8_t PR;  /*!< Prescaler Register */
-  __IO uint8_t RLR; /*!< Reload Register */
-}
-IWDG_TypeDef;
-
-/** @addtogroup IWDG_Registers_Reset_Value
-  * @{
-  */
-
-#define IWDG_PR_RESET_VALUE  ((uint8_t)0x00)
-#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Window Watchdog (WWDG)
-  */
-
-typedef struct WWDG_struct
-{
-  __IO uint8_t CR; /*!< Control Register */
-  __IO uint8_t WR; /*!< Window Register */
-}
-WWDG_TypeDef;
-
-/** @addtogroup WWDG_Registers_Reset_Value
-  * @{
-  */
-
-#define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
-#define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
-
-/**
-  * @}
-  */
-
-/** @addtogroup WWDG_Registers_Bits_Definition
-  * @{
-  */
-
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */
-#define WWDG_CR_T6   ((uint8_t)0x40) /*!< T6 bit mask */
-#define WWDG_CR_T    ((uint8_t)0x7F) /*!< T bits mask */
-
-#define WWDG_WR_MSB  ((uint8_t)0x80) /*!< MSB bit mask */
-#define WWDG_WR_W    ((uint8_t)0x7F) /*!< W bits mask */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Reset Controller (RST)
-  */
-
-typedef struct RST_struct
-{
-  __IO uint8_t SR; /*!< Reset status register */
-}
-RST_TypeDef;
-
-/** @addtogroup RST_Registers_Bits_Definition
-  * @{
-  */
-
-#define RST_SR_EMCF   ((uint8_t)0x10) /*!< EMC reset flag bit mask */
-#define RST_SR_SWIMF  ((uint8_t)0x08) /*!< SWIM reset flag bit mask */
-#define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag bit mask */
-#define RST_SR_IWDGF  ((uint8_t)0x02) /*!< IWDG reset flag bit mask */
-#define RST_SR_WWDGF  ((uint8_t)0x01) /*!< WWDG reset flag bit mask */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Serial Peripheral Interface (SPI)
-  */
-
-typedef struct SPI_struct
-{
-  __IO uint8_t CR1;    /*!< SPI control register 1 */
-  __IO uint8_t CR2;    /*!< SPI control register 2 */
-  __IO uint8_t ICR;    /*!< SPI interrupt control register */
-  __IO uint8_t SR;     /*!< SPI status register */
-  __IO uint8_t DR;     /*!< SPI data I/O register */
-  __IO uint8_t CRCPR;  /*!< SPI CRC polynomial register */
-  __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
-  __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
-}
-SPI_TypeDef;
-
-/** @addtogroup SPI_Registers_Reset_Value
-  * @{
-  */
-
-#define SPI_CR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 1 reset value */
-#define SPI_CR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 2 reset value */
-#define SPI_ICR_RESET_VALUE    ((uint8_t)0x00) /*!< Interrupt Control Register reset value */
-#define SPI_SR_RESET_VALUE     ((uint8_t)0x02) /*!< Status Register reset value */
-#define SPI_DR_RESET_VALUE     ((uint8_t)0x00) /*!< Data Register reset value */
-#define SPI_CRCPR_RESET_VALUE  ((uint8_t)0x07) /*!< Polynomial Register reset value */
-#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */
-#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */
-
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Registers_Bits_Definition
-  * @{
-  */
-
-#define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */
-#define SPI_CR1_SPE      ((uint8_t)0x40) /*!< Enable bits mask */
-#define SPI_CR1_BR       ((uint8_t)0x38) /*!< Baud rate control mask */
-#define SPI_CR1_MSTR     ((uint8_t)0x04) /*!< Master Selection mask */
-#define SPI_CR1_CPOL     ((uint8_t)0x02) /*!< Clock Polarity mask */
-#define SPI_CR1_CPHA     ((uint8_t)0x01) /*!< Clock Phase mask */
-
-#define SPI_CR2_BDM      ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */
-#define SPI_CR2_BDOE     ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */
-#define SPI_CR2_CRCEN    ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */
-#define SPI_CR2_CRCNEXT  ((uint8_t)0x10) /*!< Transmit CRC next mask */
-#define SPI_CR2_RXONLY   ((uint8_t)0x04) /*!< Receive only mask */
-#define SPI_CR2_SSM      ((uint8_t)0x02) /*!< Software slave management mask */
-#define SPI_CR2_SSI      ((uint8_t)0x01) /*!< Internal slave select mask */
-
-#define SPI_ICR_TXEI     ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */
-#define SPI_ICR_RXEI     ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */
-#define SPI_ICR_ERRIE    ((uint8_t)0x20) /*!< Error interrupt enable mask */
-#define SPI_ICR_WKIE     ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */
-
-#define SPI_SR_BSY       ((uint8_t)0x80) /*!< Busy flag */
-#define SPI_SR_OVR       ((uint8_t)0x40) /*!< Overrun flag */
-#define SPI_SR_MODF      ((uint8_t)0x20) /*!< Mode fault */
-#define SPI_SR_CRCERR    ((uint8_t)0x10) /*!< CRC error flag */
-#define SPI_SR_WKUP      ((uint8_t)0x08) /*!< Wake-Up flag */
-#define SPI_SR_TXE       ((uint8_t)0x02) /*!< Transmit buffer empty */
-#define SPI_SR_RXNE      ((uint8_t)0x01) /*!< Receive buffer not empty */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Universal Synchronous Asynchronous Receiver Transmitter (UART1)
-  */
-
-typedef struct UART1_struct
-{
-  __IO uint8_t SR;   /*!< UART1 status register */
-  __IO uint8_t DR;   /*!< UART1 data register */
-  __IO uint8_t BRR1; /*!< UART1 baud rate register */
-  __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
-  __IO uint8_t CR1;  /*!< UART1 control register 1 */
-  __IO uint8_t CR2;  /*!< UART1 control register 2 */
-  __IO uint8_t CR3;  /*!< UART1 control register 3 */
-  __IO uint8_t CR4;  /*!< UART1 control register 4 */
-  __IO uint8_t CR5;  /*!< UART1 control register 5 */
-  __IO uint8_t GTR;  /*!< UART1 guard time register */
-  __IO uint8_t PSCR; /*!< UART1 prescaler register */
-}
-UART1_TypeDef;
-
-/** @addtogroup UART1_Registers_Reset_Value
-  * @{
-  */
-
-#define UART1_SR_RESET_VALUE   ((uint8_t)0xC0)
-#define UART1_BRR1_RESET_VALUE ((uint8_t)0x00)
-#define UART1_BRR2_RESET_VALUE ((uint8_t)0x00)
-#define UART1_CR1_RESET_VALUE  ((uint8_t)0x00)
-#define UART1_CR2_RESET_VALUE  ((uint8_t)0x00)
-#define UART1_CR3_RESET_VALUE  ((uint8_t)0x00)
-#define UART1_CR4_RESET_VALUE  ((uint8_t)0x00)
-#define UART1_CR5_RESET_VALUE  ((uint8_t)0x00)
-#define UART1_GTR_RESET_VALUE  ((uint8_t)0x00)
-#define UART1_PSCR_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART1_Registers_Bits_Definition
-  * @{
-  */
-
-#define UART1_SR_TXE   ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
-#define UART1_SR_TC    ((uint8_t)0x40) /*!< Transmission Complete mask */
-#define UART1_SR_RXNE  ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
-#define UART1_SR_IDLE  ((uint8_t)0x10) /*!< IDLE line detected mask */
-#define UART1_SR_OR   ((uint8_t)0x08) /*!< OverRun error mask */
-#define UART1_SR_NF    ((uint8_t)0x04) /*!< Noise Flag mask */
-#define UART1_SR_FE    ((uint8_t)0x02) /*!< Framing Error mask */
-#define UART1_SR_PE    ((uint8_t)0x01) /*!< Parity Error mask */
-
-#define UART1_BRR1_DIVM  ((uint8_t)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */
-
-#define UART1_BRR2_DIVM  ((uint8_t)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */
-#define UART1_BRR2_DIVF  ((uint8_t)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */
-
-#define UART1_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
-#define UART1_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
-#define UART1_CR1_UARTD   ((uint8_t)0x20) /*!< UART1 Disable (for low power consumption) */
-#define UART1_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
-#define UART1_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
-#define UART1_CR1_PCEN    ((uint8_t)0x04) /*!< Parity Control Enable mask */
-#define UART1_CR1_PS      ((uint8_t)0x02) /*!< UART1 Parity Selection */
-#define UART1_CR1_PIEN    ((uint8_t)0x01) /*!< UART1 Parity Interrupt Enable mask */
-
-#define UART1_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
-#define UART1_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
-#define UART1_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
-#define UART1_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
-#define UART1_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
-#define UART1_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
-#define UART1_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
-#define UART1_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
-
-#define UART1_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
-#define UART1_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
-#define UART1_CR3_CKEN    ((uint8_t)0x08) /*!< Clock Enable mask */
-#define UART1_CR3_CPOL    ((uint8_t)0x04) /*!< Clock Polarity mask */
-#define UART1_CR3_CPHA    ((uint8_t)0x02) /*!< Clock Phase mask */
-#define UART1_CR3_LBCL    ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
-
-#define UART1_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
-#define UART1_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
-#define UART1_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
-#define UART1_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART1 node mask */
-
-#define UART1_CR5_SCEN    ((uint8_t)0x20) /*!< Smart Card Enable mask */
-#define UART1_CR5_NACK    ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
-#define UART1_CR5_HDSEL   ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
-#define UART1_CR5_IRLP    ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
-#define UART1_CR5_IREN    ((uint8_t)0x02) /*!< Irda Enable mask */
-
-/**
-  * @}
-  */
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Universal Synchronous Asynchronous Receiver Transmitter (UART2)
-  */
-
-typedef struct UART2_struct
-{
-  __IO uint8_t SR;   /*!< UART1 status register */
-  __IO uint8_t DR;   /*!< UART1 data register */
-  __IO uint8_t BRR1; /*!< UART1 baud rate register */
-  __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
-  __IO uint8_t CR1;  /*!< UART1 control register 1 */
-  __IO uint8_t CR2;  /*!< UART1 control register 2 */
-  __IO uint8_t CR3;  /*!< UART1 control register 3 */
-  __IO uint8_t CR4;  /*!< UART1 control register 4 */
-  __IO uint8_t CR5;  /*!< UART1 control register 5 */
-	__IO uint8_t CR6;  /*!< UART1 control register 6 */
-  __IO uint8_t GTR;  /*!< UART1 guard time register */
-  __IO uint8_t PSCR; /*!< UART1 prescaler register */
-}
-UART2_TypeDef;
-
-/** @addtogroup UART2_Registers_Reset_Value
-  * @{
-  */
-
-#define UART2_SR_RESET_VALUE   ((uint8_t)0xC0)
-#define UART2_BRR1_RESET_VALUE ((uint8_t)0x00)
-#define UART2_BRR2_RESET_VALUE ((uint8_t)0x00)
-#define UART2_CR1_RESET_VALUE  ((uint8_t)0x00)
-#define UART2_CR2_RESET_VALUE  ((uint8_t)0x00)
-#define UART2_CR3_RESET_VALUE  ((uint8_t)0x00)
-#define UART2_CR4_RESET_VALUE  ((uint8_t)0x00)
-#define UART2_CR5_RESET_VALUE  ((uint8_t)0x00)
-#define UART2_CR6_RESET_VALUE  ((uint8_t)0x00)
-#define UART2_GTR_RESET_VALUE  ((uint8_t)0x00)
-#define UART2_PSCR_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART2_Registers_Bits_Definition
-  * @{
-  */
-
-#define UART2_SR_TXE   ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
-#define UART2_SR_TC    ((uint8_t)0x40) /*!< Transmission Complete mask */
-#define UART2_SR_RXNE  ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
-#define UART2_SR_IDLE  ((uint8_t)0x10) /*!< IDLE line detected mask */
-#define UART2_SR_OR   ((uint8_t)0x08) /*!< OverRun error mask */
-#define UART2_SR_NF    ((uint8_t)0x04) /*!< Noise Flag mask */
-#define UART2_SR_FE    ((uint8_t)0x02) /*!< Framing Error mask */
-#define UART2_SR_PE    ((uint8_t)0x01) /*!< Parity Error mask */
-
-#define UART2_BRR1_DIVM  ((uint8_t)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */
-
-#define UART2_BRR2_DIVM  ((uint8_t)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */
-#define UART2_BRR2_DIVF  ((uint8_t)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */
-
-#define UART2_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
-#define UART2_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
-#define UART2_CR1_UARTD   ((uint8_t)0x20) /*!< UART2 Disable (for low power consumption) */
-#define UART2_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
-#define UART2_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
-#define UART2_CR1_PCEN    ((uint8_t)0x04) /*!< Parity Control Enable mask */
-#define UART2_CR1_PS      ((uint8_t)0x02) /*!< UART2 Parity Selection */
-#define UART2_CR1_PIEN    ((uint8_t)0x01) /*!< UART2 Parity Interrupt Enable mask */
-
-#define UART2_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
-#define UART2_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
-#define UART2_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
-#define UART2_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
-#define UART2_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
-#define UART2_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
-#define UART2_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
-#define UART2_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
-
-#define UART2_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
-#define UART2_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
-#define UART2_CR3_CKEN    ((uint8_t)0x08) /*!< Clock Enable mask */
-#define UART2_CR3_CPOL    ((uint8_t)0x04) /*!< Clock Polarity mask */
-#define UART2_CR3_CPHA    ((uint8_t)0x02) /*!< Clock Phase mask */
-#define UART2_CR3_LBCL    ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
-
-#define UART2_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
-#define UART2_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
-#define UART2_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
-#define UART2_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART2 node mask */
-
-#define UART2_CR5_SCEN    ((uint8_t)0x20) /*!< Smart Card Enable mask */
-#define UART2_CR5_NACK    ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
-#define UART2_CR5_HDSEL   ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
-#define UART2_CR5_IRLP    ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
-#define UART2_CR5_IREN    ((uint8_t)0x02) /*!< Irda Enable mask */
-
-#define UART2_CR6_LDUM    ((uint8_t)0x80) /*!< LIN Divider Update Method */
-#define UART2_CR6_LSLV    ((uint8_t)0x20) /*!< LIN Slave Enable */
-#define UART2_CR6_LASE    ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
-#define UART2_CR6_LHDIEN  ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */
-#define UART2_CR6_LHDF    ((uint8_t)0x02) /*!< LIN Header Detection Flag */
-#define UART2_CR6_LSF     ((uint8_t)0x01) /*!< LIN Synch Field */
-
-/**
-  * @}
-  */
-
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  LIN Universal Asynchronous Receiver Transmitter (UART3)
-  */
-
-typedef struct UART3_struct
-{
-  __IO uint8_t SR;       /*!< status register */
-  __IO uint8_t DR;       /*!< data register */
-  __IO uint8_t BRR1;     /*!< baud rate register */
-  __IO uint8_t BRR2;     /*!< DIV mantissa[11:8] SCIDIV fraction */
-  __IO uint8_t CR1;      /*!< control register 1 */
-  __IO uint8_t CR2;      /*!< control register 2 */
-  __IO uint8_t CR3;      /*!< control register 3 */
-  __IO uint8_t CR4;      /*!< control register 4 */
-  uint8_t RESERVED; /*!< Reserved byte */
-  __IO uint8_t CR6;      /*!< control register 5 */
-}
-UART3_TypeDef;
-
-/** @addtogroup UART3_Registers_Reset_Value
-  * @{
-  */
-
-#define UART3_SR_RESET_VALUE   ((uint8_t)0xC0)
-#define UART3_BRR1_RESET_VALUE ((uint8_t)0x00)
-#define UART3_BRR2_RESET_VALUE ((uint8_t)0x00)
-#define UART3_CR1_RESET_VALUE  ((uint8_t)0x00)
-#define UART3_CR2_RESET_VALUE  ((uint8_t)0x00)
-#define UART3_CR3_RESET_VALUE  ((uint8_t)0x00)
-#define UART3_CR4_RESET_VALUE  ((uint8_t)0x00)
-#define UART3_CR6_RESET_VALUE  ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART3_Registers_Bits_Definition
-  * @{
-  */
-
-#define UART3_SR_TXE      ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
-#define UART3_SR_TC       ((uint8_t)0x40) /*!< Transmission Complete mask */
-#define UART3_SR_RXNE     ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
-#define UART3_SR_IDLE     ((uint8_t)0x10) /*!< IDLE line detected mask */
-#define UART3_SR_OR       ((uint8_t)0x08) /*!< OverRun error mask */
-#define UART3_SR_NF       ((uint8_t)0x04) /*!< Noise Flag mask */
-#define UART3_SR_FE       ((uint8_t)0x02) /*!< Framing Error mask */
-#define UART3_SR_PE       ((uint8_t)0x01) /*!< Parity Error mask */
-
-#define UART3_BRR1_DIVM   ((uint8_t)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */
-
-#define UART3_BRR2_DIVM   ((uint8_t)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */
-#define UART3_BRR2_DIVF   ((uint8_t)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */
-
-#define UART3_CR1_R8      ((uint8_t)0x80) /*!< Receive Data bit 8 */
-#define UART3_CR1_T8      ((uint8_t)0x40) /*!< Transmit data bit 8 */
-#define UART3_CR1_UARTD   ((uint8_t)0x20) /*!< UART Disable (for low power consumption) */
-#define UART3_CR1_M       ((uint8_t)0x10) /*!< Word length mask */
-#define UART3_CR1_WAKE    ((uint8_t)0x08) /*!< Wake-up method mask */
-#define UART3_CR1_PCEN    ((uint8_t)0x04) /*!< Parity control enable mask */
-#define UART3_CR1_PS      ((uint8_t)0x02) /*!< Parity selection bit mask */
-#define UART3_CR1_PIEN    ((uint8_t)0x01) /*!< Parity interrupt enable bit mask */
-
-#define UART3_CR2_TIEN    ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
-#define UART3_CR2_TCIEN   ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
-#define UART3_CR2_RIEN    ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
-#define UART3_CR2_ILIEN   ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
-#define UART3_CR2_TEN     ((uint8_t)0x08) /*!< Transmitter Enable mask */
-#define UART3_CR2_REN     ((uint8_t)0x04) /*!< Receiver Enable mask */
-#define UART3_CR2_RWU     ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
-#define UART3_CR2_SBK     ((uint8_t)0x01) /*!< Send Break mask */
-
-#define UART3_CR3_LINEN   ((uint8_t)0x40) /*!< Alternate Function output mask */
-#define UART3_CR3_STOP    ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
-
-#define UART3_CR4_LBDIEN  ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
-#define UART3_CR4_LBDL    ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
-#define UART3_CR4_LBDF    ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
-#define UART3_CR4_ADD     ((uint8_t)0x0F) /*!< Address of the UART3 node mask */
-
-#define UART3_CR6_LDUM    ((uint8_t)0x80) /*!< LIN Divider Update Method */
-#define UART3_CR6_LSLV    ((uint8_t)0x20) /*!< LIN Slave Enable */
-#define UART3_CR6_LASE    ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
-#define UART3_CR6_LHDIEN  ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */
-#define UART3_CR6_LHDF    ((uint8_t)0x02) /*!< LIN Header Detection Flag */
-#define UART3_CR6_LSF     ((uint8_t)0x01) /*!< LIN Synch Field */
-
-/**
-  * @}
-  */
-
-
-/*----------------------------------------------------------------------------*/
-/**
-  * @brief  Controller Area Network  (CAN)
-  */
-
-typedef struct
-{
-  __IO uint8_t MCR;    /*!< CAN master control register */
-  __IO uint8_t MSR;    /*!< CAN master status register */
-  __IO uint8_t TSR;    /*!< CAN transmit status register */
-  __IO uint8_t TPR;    /*!< CAN transmit priority register */
-  __IO uint8_t RFR;    /*!< CAN receive FIFO register */
-  __IO uint8_t IER;    /*!< CAN interrupt enable register */
-  __IO uint8_t DGR;    /*!< CAN diagnosis register */
-  __IO uint8_t PSR;    /*!< CAN page selection register */
-
-  union
-  {
-    struct
-    {
-      __IO uint8_t MCSR;
-      __IO uint8_t MDLCR;
-      __IO uint8_t MIDR1;
-      __IO uint8_t MIDR2;
-      __IO uint8_t MIDR3;
-      __IO uint8_t MIDR4;
-      __IO uint8_t MDAR1;
-      __IO uint8_t MDAR2;
-      __IO uint8_t MDAR3;
-      __IO uint8_t MDAR4;
-      __IO uint8_t MDAR5;
-      __IO uint8_t MDAR6;
-      __IO uint8_t MDAR7;
-      __IO uint8_t MDAR8;
-      __IO uint8_t MTSRL;
-      __IO uint8_t MTSRH;
-    }
-	  TxMailbox;
-
-	struct
-    {
-      __IO uint8_t FR01;
-      __IO uint8_t FR02;
-      __IO uint8_t FR03;
-      __IO uint8_t FR04;
-      __IO uint8_t FR05;
-      __IO uint8_t FR06;
-      __IO uint8_t FR07;
-      __IO uint8_t FR08;
-
-      __IO uint8_t FR09;
-      __IO uint8_t FR10;
-      __IO uint8_t FR11;
-      __IO uint8_t FR12;
-      __IO uint8_t FR13;
-      __IO uint8_t FR14;
-      __IO uint8_t FR15;
-      __IO uint8_t FR16;
-    }
-	Filter;
-	
-
-    struct
-    {
-      __IO uint8_t F0R1;
-      __IO uint8_t F0R2;
-      __IO uint8_t F0R3;
-      __IO uint8_t F0R4;
-      __IO uint8_t F0R5;
-      __IO uint8_t F0R6;
-      __IO uint8_t F0R7;
-      __IO uint8_t F0R8;
-
-      __IO uint8_t F1R1;
-      __IO uint8_t F1R2;
-      __IO uint8_t F1R3;
-      __IO uint8_t F1R4;
-      __IO uint8_t F1R5;
-      __IO uint8_t F1R6;
-      __IO uint8_t F1R7;
-	  __IO uint8_t F1R8;
-    }
-	  Filter01;
-
-    struct
-    {
-      __IO uint8_t F2R1;
-      __IO uint8_t F2R2;
-      __IO uint8_t F2R3;
-      __IO uint8_t F2R4;
-      __IO uint8_t F2R5;
-      __IO uint8_t F2R6;
-      __IO uint8_t F2R7;
-      __IO uint8_t F2R8;
-	
-      __IO uint8_t F3R1;
-      __IO uint8_t F3R2;
-      __IO uint8_t F3R3;
-      __IO uint8_t F3R4;
-      __IO uint8_t F3R5;
-      __IO uint8_t F3R6;
-      __IO uint8_t F3R7;
-      __IO uint8_t F3R8;
-    }
-	  Filter23;
-
-    struct
-    {
-      __IO uint8_t F4R1;
-      __IO uint8_t F4R2;
-      __IO uint8_t F4R3;
-      __IO uint8_t F4R4;
-      __IO uint8_t F4R5;
-      __IO uint8_t F4R6;
-      __IO uint8_t F4R7;
-      __IO uint8_t F4R8;
-			
-      __IO uint8_t F5R1;
-      __IO uint8_t F5R2;
-      __IO uint8_t F5R3;
-      __IO uint8_t F5R4;
-      __IO uint8_t F5R5;
-      __IO uint8_t F5R6;
-      __IO uint8_t F5R7;
-      __IO uint8_t F5R8;
-    }
-	  Filter45;
-
-    struct
-    {
-      __IO uint8_t ESR;
-      __IO uint8_t EIER;
-      __IO uint8_t TECR;
-      __IO uint8_t RECR;
-      __IO uint8_t BTR1;
-      __IO uint8_t BTR2;
-      u8 Reserved1[2];
-      __IO uint8_t FMR1;
-      __IO uint8_t FMR2;
-      __IO uint8_t FCR1;
-      __IO uint8_t FCR2;
-      __IO uint8_t FCR3;
-      u8 Reserved2[3];
-    }
-		Config;
-
-    struct
-    {
-      __IO uint8_t MFMI;
-      __IO uint8_t MDLCR;
-      __IO uint8_t MIDR1;
-      __IO uint8_t MIDR2;
-      __IO uint8_t MIDR3;
-      __IO uint8_t MIDR4;
-      __IO uint8_t MDAR1;
-      __IO uint8_t MDAR2;
-      __IO uint8_t MDAR3;
-      __IO uint8_t MDAR4;
-      __IO uint8_t MDAR5;
-      __IO uint8_t MDAR6;
-      __IO uint8_t MDAR7;
-      __IO uint8_t MDAR8;
-      __IO uint8_t MTSRL;
-      __IO uint8_t MTSRH;
-    }
-	  RxFIFO;
-  }Page;
-} CAN_TypeDef;
-/** @addtogroup CAN_Registers_Bits_Definition
-  * @{
-  */
-/*******************************Common****************************************/
-/* CAN Master Control Register bits */
-#define CAN_MCR_INRQ     ((uint8_t)0x01)
-#define CAN_MCR_SLEEP    ((uint8_t)0x02)
-#define CAN_MCR_TXFP     ((uint8_t)0x04)
-#define CAN_MCR_RFLM     ((uint8_t)0x08)
-#define CAN_MCR_NART     ((uint8_t)0x10)
-#define CAN_MCR_AWUM     ((uint8_t)0x20)
-#define CAN_MCR_ABOM     ((uint8_t)0x40)
-#define CAN_MCR_TTCM     ((uint8_t)0x80)
-
-/* CAN Master Status Register bits */
-#define CAN_MSR_INAK     ((uint8_t)0x01)
-#define CAN_MSR_SLAK     ((uint8_t)0x02)
-#define CAN_MSR_ERRI     ((uint8_t)0x04)
-#define CAN_MSR_WKUI     ((uint8_t)0x08)
-#define CAN_MSR_TX       ((uint8_t)0x10)
-#define CAN_MSR_RX       ((uint8_t)0x20)
-
-/* CAN Transmit Status Register bits */
-#define CAN_TSR_RQCP0    ((uint8_t)0x01)
-#define CAN_TSR_RQCP1    ((uint8_t)0x02)
-#define CAN_TSR_RQCP2    ((uint8_t)0x04)
-#define CAN_TSR_RQCP012  ((uint8_t)0x07)
-#define CAN_TSR_TXOK0    ((uint8_t)0x10)
-#define CAN_TSR_TXOK1    ((uint8_t)0x20)
-#define CAN_TSR_TXOK2    ((uint8_t)0x40)
-
-#define CAN_TPR_CODE0    ((uint8_t)0x01)
-#define CAN_TPR_TME0     ((uint8_t)0x04)
-#define CAN_TPR_TME1     ((uint8_t)0x08)
-#define CAN_TPR_TME2     ((uint8_t)0x10)
-#define CAN_TPR_LOW0     ((uint8_t)0x20)
-#define CAN_TPR_LOW1     ((uint8_t)0x40)
-#define CAN_TPR_LOW2     ((uint8_t)0x80)
-/* CAN Receive FIFO Register bits */
-#define CAN_RFR_FMP01  ((uint8_t)0x03)
-#define CAN_RFR_FULL   ((uint8_t)0x08)
-#define CAN_RFR_FOVR   ((uint8_t)0x10)
-#define CAN_RFR_RFOM   ((uint8_t)0x20)
-
-/* CAN Interrupt Register bits */
-#define CAN_IER_TMEIE  ((uint8_t)0x01)
-#define CAN_IER_FMPIE  ((uint8_t)0x02)
-#define CAN_IER_FFIE   ((uint8_t)0x04)
-#define CAN_IER_FOVIE  ((uint8_t)0x08)
-#define CAN_IER_WKUIE  ((uint8_t)0x80)
-
-
-/* CAN diagnostic Register bits */
-#define CAN_DGR_LBKM  ((uint8_t)0x01)
-#define CAN_DGR_SLIM  ((uint8_t)0x02)
-#define CAN_DGR_SAMP  ((uint8_t)0x04)
-#define CAN_DGR_RX    ((uint8_t)0x08)
-#define CAN_DGR_TXM2E ((uint8_t)0x10)
-
-
-/* CAN page select Register bits */
-#define CAN_PSR_PS0  ((uint8_t)0x01)
-#define CAN_PSR_PS1  ((uint8_t)0x02)
-#define CAN_PSR_PS2  ((uint8_t)0x04)
-
-/*********************Tx MailBox & Fifo Page common bits***********************/
-#define CAN_MCSR_TXRQ    ((uint8_t)0x01)
-#define CAN_MCSR_ABRQ    ((uint8_t)0x02)
-#define CAN_MCSR_RQCP    ((uint8_t)0x04)
-#define CAN_MCSR_TXOK    ((uint8_t)0x08)
-#define CAN_MCSR_ALST    ((uint8_t)0x10)
-#define CAN_MCSR_TERR    ((uint8_t)0x20)
-
-#define CAN_MDLCR_DLC    ((uint8_t)0x0F)
-#define CAN_MDLCR_TGT    ((uint8_t)0x80)
-
-#define CAN_MIDR1_RTR    ((uint8_t)0x20)
-#define CAN_MIDR1_IDE    ((uint8_t)0x40)
-
-
-/*************************Filter Page******************************************/
-
-/* CAN Error Status Register bits */
-#define CAN_ESR_EWGF     ((uint8_t)0x01)
-#define CAN_ESR_EPVF     ((uint8_t)0x02)
-#define CAN_ESR_BOFF     ((uint8_t)0x04)
-#define CAN_ESR_LEC0     ((uint8_t)0x10)
-#define CAN_ESR_LEC1     ((uint8_t)0x20)
-#define CAN_ESR_LEC2     ((uint8_t)0x40)
-#define CAN_ESR_LEC      ((uint8_t)0x70)
-
-/* CAN Error Status Register bits */
-#define CAN_EIER_EWGIE    ((uint8_t)0x01)
-#define CAN_EIER_EPVIE    ((uint8_t)0x02)
-#define CAN_EIER_BOFIE    ((uint8_t)0x04)
-#define CAN_EIER_LECIE    ((uint8_t)0x10)
-#define CAN_EIER_ERRIE    ((uint8_t)0x80)
-
-/* CAN transmit error counter Register bits(CAN_TECR) */
-#define CAN_TECR_TEC0     ((uint8_t)0x01)
-#define CAN_TECR_TEC1     ((uint8_t)0x02)
-#define CAN_TECR_TEC2     ((uint8_t)0x04)
-#define CAN_TECR_TEC3     ((uint8_t)0x08)
-#define CAN_TECR_TEC4     ((uint8_t)0x10)
-#define CAN_TECR_TEC5     ((uint8_t)0x20)
-#define CAN_TECR_TEC6     ((uint8_t)0x40)
-#define CAN_TECR_TEC7     ((uint8_t)0x80)
-
-/* CAN RECEIVE error counter Register bits(CAN_TECR) */
-#define CAN_RECR_REC0     ((uint8_t)0x01)
-#define CAN_RECR_REC1     ((uint8_t)0x02)
-#define CAN_RECR_REC2     ((uint8_t)0x04)
-#define CAN_RECR_REC3     ((uint8_t)0x08)
-#define CAN_RECR_REC4     ((uint8_t)0x10)
-#define CAN_RECR_REC5     ((uint8_t)0x20)
-#define CAN_RECR_REC6     ((uint8_t)0x40)
-#define CAN_RECR_REC7     ((uint8_t)0x80)
-
-/* CAN filter mode register bits (CAN_FMR) */
-#define CAN_FMR1_FML0     ((uint8_t)0x01)
-#define CAN_FMR1_FMH0     ((uint8_t)0x02)
-#define CAN_FMR1_FML1     ((uint8_t)0x04)
-#define CAN_FMR1_FMH1     ((uint8_t)0x08)
-#define CAN_FMR1_FML2     ((uint8_t)0x10)
-#define CAN_FMR1_FMH2     ((uint8_t)0x20)
-#define CAN_FMR1_FML3     ((uint8_t)0x40)
-#define CAN_FMR1_FMH3     ((uint8_t)0x80)
-
-#define CAN_FMR2_FML4     ((uint8_t)0x01)
-#define CAN_FMR2_FMH4     ((uint8_t)0x02)
-#define CAN_FMR2_FML5     ((uint8_t)0x04)
-#define CAN_FMR2_FMH5     ((uint8_t)0x08)
-
-/* CAN filter Config register bits (CAN_FCR) */
-#define CAN_FCR1_FACT0     ((uint8_t)0x01)
-#define CAN_FCR1_FACT1     ((uint8_t)0x10)
-#define CAN_FCR2_FACT2     ((uint8_t)0x01)
-#define CAN_FCR2_FACT3     ((uint8_t)0x10)
-#define CAN_FCR3_FACT4     ((uint8_t)0x01)
-#define CAN_FCR3_FACT5     ((uint8_t)0x10)
-
-#define CAN_FCR1_FSC00    ((uint8_t)0x02)
-#define CAN_FCR1_FSC01    ((uint8_t)0x04)
-#define CAN_FCR1_FSC10    ((uint8_t)0x20)
-#define CAN_FCR1_FSC11    ((uint8_t)0x40)
-#define CAN_FCR2_FSC20    ((uint8_t)0x02)
-#define CAN_FCR2_FSC21    ((uint8_t)0x04)
-#define CAN_FCR2_FSC30    ((uint8_t)0x20)
-#define CAN_FCR2_FSC31    ((uint8_t)0x40)
-#define CAN_FCR3_FSC40    ((uint8_t)0x02)
-#define CAN_FCR3_FSC41    ((uint8_t)0x04)
-#define CAN_FCR3_FSC50    ((uint8_t)0x20)
-#define CAN_FCR3_FSC51    ((uint8_t)0x40)
-
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup CAN_Registers_Reset_Value
-  * @{
-  */
-
-#define  	CAN_MCR_RESET_VALUE			((uint8_t)0x02)
-#define  	CAN_MSR_RESET_VALUE			((uint8_t)0x02)
-#define  	CAN_TSR_RESET_VALUE			((uint8_t)0x00)
-#define  	CAN_TPR_RESET_VALUE			((uint8_t)0x0C)
-#define  	CAN_RFR_RESET_VALUE			((uint8_t)0x00)
-#define  	CAN_IER_RESET_VALUE			((uint8_t)0x00)
-#define  	CAN_DGR_RESET_VALUE			((uint8_t)0x0C)
-#define  	CAN_PSR_RESET_VALUE			((uint8_t)0x00)
-
-#define  	CAN_ESR_RESET_VALUE			((uint8_t)0x00)
-#define  	CAN_EIER_RESET_VALUE		((uint8_t)0x00)
-#define  	CAN_TECR_RESET_VALUE		((uint8_t)0x00)
-#define  	CAN_RECR_RESET_VALUE		((uint8_t)0x00)
-#define  	CAN_BTR1_RESET_VALUE		((uint8_t)0x40)
-#define  	CAN_BTR2_RESET_VALUE		((uint8_t)0x23)
-#define  	CAN_FMR1_RESET_VALUE		((uint8_t)0x00)
-#define  	CAN_FMR2_RESET_VALUE		((uint8_t)0x00)
-#define  	CAN_FCR_RESET_VALUE			((uint8_t)0x00)
-
-#define  	CAN_MFMI_RESET_VALUE			((uint8_t)0x00)
-#define  	CAN_MDLC_RESET_VALUE			((uint8_t)0x00)
-#define  	CAN_MCSR_RESET_VALUE			((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Configuration Registers (CFG)
-  */
-
-typedef struct CFG_struct
-{
-  __IO uint8_t GCR; /*!< Global Configuration register */
-}
-CFG_TypeDef;
-
-/** @addtogroup CFG_Registers_Reset_Value
-  * @{
-  */
-
-#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @addtogroup CFG_Registers_Bits_Definition
-  * @{
-  */
-
-#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */
-#define CFG_GCR_AL  ((uint8_t)0x02) /*!< Activation Level bit mask */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*                          Peripherals Base Address                          */
-/******************************************************************************/
-
-/** @addtogroup MAP_FILE_Base_Addresses
-  * @{
-  */
-#define OPT_BaseAddress         0x4800
-#define GPIOA_BaseAddress       0x5000
-#define GPIOB_BaseAddress       0x5005
-#define GPIOC_BaseAddress       0x500A
-#define GPIOD_BaseAddress       0x500F
-#define GPIOE_BaseAddress       0x5014
-#define GPIOF_BaseAddress       0x5019
-#define GPIOG_BaseAddress       0x501E
-#define GPIOH_BaseAddress       0x5023
-#define GPIOI_BaseAddress       0x5028
-#define FLASH_BaseAddress       0x505A
-#define EXTI_BaseAddress        0x50A0
-#define RST_BaseAddress         0x50B3
-#define CLK_BaseAddress         0x50C0
-#define WWDG_BaseAddress        0x50D1
-#define IWDG_BaseAddress        0x50E0
-#define AWU_BaseAddress         0x50F0
-#define BEEP_BaseAddress        0x50F3
-#define SPI_BaseAddress         0x5200
-#define I2C_BaseAddress         0x5210
-#define UART1_BaseAddress       0x5230
-#define UART2_BaseAddress       0x5240
-#define UART3_BaseAddress       0x5240
-#define TIM1_BaseAddress        0x5250
-#define TIM2_BaseAddress        0x5300
-#define TIM3_BaseAddress        0x5320
-#define TIM4_BaseAddress        0x5340
-#define TIM5_BaseAddress        0x5300
-#define TIM6_BaseAddress        0x5340
-#define ADC1_BaseAddress        0x53E0
-#define ADC2_BaseAddress        0x5400
-#define CAN_BaseAddress         0x5420
-#define CFG_BaseAddress         0x7F60
-#define ITC_BaseAddress         0x7F70
-#define DM_BaseAddress          0x7F90
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*                          Peripherals declarations                          */
-/******************************************************************************/
-
-#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
-    defined(STM8S903) || defined(STM8AF626x)
- #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)
-#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */
-
-#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
-    defined (STM8AF62Ax)
-#define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress)
-#endif /* (STM8S208) ||(STM8S207) || (STM8S007) || (STM8AF52Ax) || (STM8AF62Ax) */
-
-#define AWU ((AWU_TypeDef *) AWU_BaseAddress)
-
-#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
-
-#if defined (STM8S208) || defined (STM8AF52Ax)
- #define CAN ((CAN_TypeDef *) CAN_BaseAddress)
-#endif /* (STM8S208) || (STM8AF52Ax) */
-
-#define CLK ((CLK_TypeDef *) CLK_BaseAddress)
-
-#define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)
-
-#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
-
-#define OPT ((OPT_TypeDef *) OPT_BaseAddress)
-
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
-
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
-
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
-
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
-
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
-
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
-
-#if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined(STM8S105) || \
-    defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)
- #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)
-#endif /* (STM8S208) ||(STM8S207)  || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x) */
-
-#if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || \
-    defined (STM8AF62Ax)
- #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress)
- #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress)
-#endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
-
-#define RST ((RST_TypeDef *) RST_BaseAddress)
-
-#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
-#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
-
-#define SPI ((SPI_TypeDef *) SPI_BaseAddress)
-#define I2C ((I2C_TypeDef *) I2C_BaseAddress)
-
-#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
-    defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
- #define UART1 ((UART1_TypeDef *) UART1_BaseAddress)
-#endif /* (STM8S208) ||(STM8S207)  || (STM8S103) || (STM8S903) || (STM8AF52Ax) || (STM8AF62Ax) */
-
-#if defined (STM8S105) || defined (STM8S005) || defined (STM8AF626x)
- #define UART2 ((UART2_TypeDef *) UART2_BaseAddress)
-#endif /* STM8S105 || STM8S005 || STM8AF626x */
-
-#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
-    defined (STM8AF62Ax)
- #define UART3 ((UART3_TypeDef *) UART3_BaseAddress)
-#endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
-
-#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
-
-#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
-    defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \
-    defined (STM8AF62Ax) || defined (STM8AF626x)
- #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)
-#endif /* (STM8S208) ||(STM8S207)  || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
-
-#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S105) || \
-    defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)
- #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress)
-#endif /* (STM8S208) ||(STM8S207)  || (STM8S105) || (STM8AF62Ax) || (STM8AF52Ax) || (STM8AF626x)*/
-
-#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
-    defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \
-    defined (STM8AF62Ax) || defined (STM8AF626x)
- #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)
-#endif /* (STM8S208) ||(STM8S207)  || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
-
-#ifdef STM8S903
- #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress)
- #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress)
-#endif /* STM8S903 */
-
-#define ITC ((ITC_TypeDef *) ITC_BaseAddress)
-
-#define CFG ((CFG_TypeDef *) CFG_BaseAddress)
-
-#define DM ((DM_TypeDef *) DM_BaseAddress)
-
-
-#ifdef USE_STDPERIPH_DRIVER
- #include "stm8s_conf.h"
-#endif
-
-/* Exported macro --------------------------------------------------------------*/
-
-/*============================== Interrupts ====================================*/
-#ifdef _RAISONANCE_
- #include <intrins.h>
- #define enableInterrupts()    _rim_()  /* enable interrupts */
- #define disableInterrupts()   _sim_()  /* disable interrupts */
- #define rim()                 _rim_()  /* enable interrupts */
- #define sim()                 _sim_()  /* disable interrupts */
- #define nop()                 _nop_()  /* No Operation */
- #define trap()                _trap_() /* Trap (soft IT) */
- #define wfi()                 _wfi_()  /* Wait For Interrupt */
- #define halt()                _halt_() /* Halt */
-#elif defined(_COSMIC_)
- #define enableInterrupts()    {_asm("rim\n");}  /* enable interrupts */
- #define disableInterrupts()   {_asm("sim\n");}  /* disable interrupts */
- #define rim()                 {_asm("rim\n");}  /* enable interrupts */
- #define sim()                 {_asm("sim\n");}  /* disable interrupts */
- #define nop()                 {_asm("nop\n");}  /* No Operation */
- #define trap()                {_asm("trap\n");} /* Trap (soft IT) */
- #define wfi()                 {_asm("wfi\n");}  /* Wait For Interrupt */
- #define halt()                {_asm("halt\n");} /* Halt */
-#else /*_IAR_*/
- #include <intrinsics.h>
- #define enableInterrupts()    __enable_interrupt()   /* enable interrupts */
- #define disableInterrupts()   __disable_interrupt()  /* disable interrupts */
- #define rim()                 __enable_interrupt()   /* enable interrupts */
- #define sim()                 __disable_interrupt()  /* disable interrupts */
- #define nop()                 __no_operation()       /* No Operation */
- #define trap()                __trap()               /* Trap (soft IT) */
- #define wfi()                 __wait_for_interrupt() /* Wait For Interrupt */
- #define halt()                __halt()               /* Halt */
-#endif /*_RAISONANCE_*/
-
-/*============================== Interrupt vector Handling ========================*/
-
-#ifdef _COSMIC_
- #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)
- #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)
-#endif /* _COSMIC_ */
-
-#ifdef _RAISONANCE_
- #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b
- #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap
-#endif /* _RAISONANCE_ */
-
-#ifdef _IAR_
- #define STRINGVECTOR(x) #x
- #define VECTOR_ID(x) STRINGVECTOR( vector = (x) )
- #define INTERRUPT_HANDLER( a, b )  \
- _Pragma( VECTOR_ID( (b)+2 ) )        \
- __interrupt void (a)( void )
- #define INTERRUPT_HANDLER_TRAP(a) \
- _Pragma( VECTOR_ID( 1 ) ) \
- __interrupt void (a) (void)
-#endif /* _IAR_ */
-
-/*============================== Interrupt Handler declaration ========================*/
-#ifdef _COSMIC_
- #define INTERRUPT @far @interrupt
-#elif defined(_IAR_)
- #define INTERRUPT __interrupt
-#endif /* _COSMIC_ */
-
-/*============================== Handling bits ====================================*/
-/*-----------------------------------------------------------------------------
-Method : I
-Description : Handle the bit from the character variables.
-Comments :    The different parameters of commands are
-              - VAR : Name of the character variable where the bit is located.
-              - Place : Bit position in the variable (7 6 5 4 3 2 1 0)
-              - Value : Can be 0 (reset bit) or not 0 (set bit)
-              The "MskBit" command allows to select some bits in a source
-              variables and copy it in a destination var (return the value).
-              The "ValBit" command returns the value of a bit in a char
-              variable: the bit is reset if it returns 0 else the bit is set.
-              This method generates not an optimised code yet.
------------------------------------------------------------------------------*/
-#define SetBit(VAR,Place)         ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
-#define ClrBit(VAR,Place)         ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
-
-#define ChgBit(VAR,Place)         ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
-#define AffBit(VAR,Place,Value)   ((Value) ? \
-                                   ((VAR) |= ((uint8_t)1<<(Place))) : \
-                                   ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))
-#define MskBit(Dest,Msk,Src)      ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
-
-#define ValBit(VAR,Place)         ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
-
-#define BYTE_0(n)                 ((uint8_t)((n) & (uint8_t)0xFF))        /*!< Returns the low byte of the 32-bit value */
-#define BYTE_1(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))  /*!< Returns the second byte of the 32-bit value */
-#define BYTE_2(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */
-#define BYTE_3(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */
-
-/*============================== Assert Macros ====================================*/
-#define IS_STATE_VALUE_OK(SensitivityValue) \
-  (((SensitivityValue) == ENABLE) || \
-   ((SensitivityValue) == DISABLE))
-
-/*-----------------------------------------------------------------------------
-Method : II
-Description : Handle directly the bit.
-Comments :    The idea is to handle directly with the bit name. For that, it is
-              necessary to have RAM area descriptions (example: HW register...)
-              and the following command line for each area.
-              This method generates the most optimized code.
------------------------------------------------------------------------------*/
-
-#define AREA 0x00     /* The area of bits begins at address 0x10. */
-
-#define BitClr(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
-#define BitSet(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
-#define BitVal(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __STM8S_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM8S/stm8s_type.h b/os/hal/platforms/STM8S/stm8s_type.h
deleted file mode 100644
index 5c80f6687..000000000
--- a/os/hal/platforms/STM8S/stm8s_type.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
-  ******************************************************************************
-  * @file stm8s_type.h
-  * @brief This file contains all common data types.
-  * @author STMicroelectronics - MCD Application Team
-  * @version V1.1.1
-  * @date 06/05/2009
-  ******************************************************************************
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
-  * @image html logo.bmp
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM8S_TYPE_H
-#define __STM8S_TYPE_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-typedef signed long  s32;
-typedef signed short s16;
-typedef signed char  s8;
-
-typedef signed long  const sc32;  /* Read Only */
-typedef signed short const sc16;  /* Read Only */
-typedef signed char  const sc8;   /* Read Only */
-
-typedef volatile signed long  vs32;
-typedef volatile signed short vs16;
-typedef volatile signed char  vs8;
-
-typedef volatile signed long  const vsc32;  /* Read Only */
-typedef volatile signed short const vsc16;  /* Read Only */
-typedef volatile signed char  const vsc8;   /* Read Only */
-
-typedef unsigned long  u32;
-typedef unsigned short u16;
-typedef unsigned char  u8;
-
-typedef unsigned long  const uc32;  /* Read Only */
-typedef unsigned short const uc16;  /* Read Only */
-typedef unsigned char  const uc8;   /* Read Only */
-
-typedef volatile unsigned long  vu32;
-typedef volatile unsigned short vu16;
-typedef volatile unsigned char  vu8;
-
-typedef volatile unsigned long  const vuc32;  /* Read Only */
-typedef volatile unsigned short const vuc16;  /* Read Only */
-typedef volatile unsigned char  const vuc8;   /* Read Only */
-
-typedef enum
-{
-  FALSE = 0,
-  TRUE = !FALSE
-}
-bool;
-
-typedef enum {
-  RESET = 0,
-  SET = !RESET
-}
-FlagStatus, ITStatus, BitStatus;
-
-typedef enum {
-  DISABLE = 0,
-  ENABLE = !DISABLE
-}
-FunctionalState;
-
-#define IS_FUNCTIONALSTATE_OK(VALUE) ( (VALUE == ENABLE) || (VALUE == DISABLE) )
-
-typedef enum {
-  ERROR = 0,
-  SUCCESS = !ERROR
-}
-ErrorStatus;
-
-#define U8_MAX     ((u8)255)
-#define S8_MAX     ((s8)127)
-#define S8_MIN     ((s8)-128)
-#define U16_MAX    ((u16)65535u)
-#define S16_MAX    ((s16)32767)
-#define S16_MIN    ((s16)-32768)
-#define U32_MAX    ((u32)4294967295uL)
-#define S32_MAX    ((s32)2147483647)
-#define S32_MIN    ((s32)-2147483648)
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __STM8S_TYPE_H */
-
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/Win32/console.c b/os/hal/platforms/Win32/console.c
deleted file mode 100644
index dbbfbf661..000000000
--- a/os/hal/platforms/Win32/console.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file console.c
- * @brief Simulator console driver code.
- * @{
- */
-
-#include <stdio.h>
-
-#include "ch.h"
-#include "hal.h"
-#include "console.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief Console driver 1.
- */
-BaseChannel CD1;
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static size_t write(void *ip, const uint8_t *bp, size_t n) {
-  size_t ret;
-
-  (void)ip;
-  ret = fwrite(bp, 1, n, stdout);
-  fflush(stdout);
-  return ret;
-}
-
-static size_t read(void *ip, uint8_t *bp, size_t n) {
-
-  (void)ip;
-  return fread(bp, 1, n, stdin);
-}
-
-static msg_t put(void *ip, uint8_t b) {
-
-  (void)ip;
-
-  fputc(b, stdout);
-  fflush(stdout);
-  return RDY_OK;
-}
-
-static msg_t get(void *ip) {
-
-  (void)ip;
-
-  return fgetc(stdin);
-}
-
-static msg_t putt(void *ip, uint8_t b, systime_t time) {
-
-  (void)ip;
-  (void)time;
-  fputc(b, stdout);
-  fflush(stdout);
-  return RDY_OK;
-}
-
-static msg_t gett(void *ip, systime_t time) {
-
-  (void)ip;
-  (void)time;
-  return fgetc(stdin);
-}
-
-static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) {
-  size_t ret;
-
-  (void)ip;
-  (void)time;
-  ret = fwrite(bp, 1, n, stdout);
-  fflush(stdout);
-  return ret;
-}
-
-static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) {
-
-  (void)ip;
-  (void)time;
-  return fread(bp, 1, n, stdin);
-}
-
-static const struct BaseChannelVMT vmt = {
-  write, read, put, get,
-  putt, gett, writet, readt
-};
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-void conInit(void) {
-
-  CD1.vmt = &vmt;
-}
-
-/** @} */
diff --git a/os/hal/platforms/Win32/console.h b/os/hal/platforms/Win32/console.h
deleted file mode 100644
index 491b6f36b..000000000
--- a/os/hal/platforms/Win32/console.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file console.h
- * @brief Simulator console driver header.
- * @{
- */
-
-#ifndef _CONSOLE_H_
-#define _CONSOLE_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-extern BaseChannel CD1;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void conInit(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CONSOLE_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Win32/hal_lld.c b/os/hal/platforms/Win32/hal_lld.c
deleted file mode 100644
index c86e84de7..000000000
--- a/os/hal/platforms/Win32/hal_lld.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file Win32/hal_lld.c
- * @brief Win32 HAL subsystem low level driver code.
- * @addtogroup WIN32_HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-static LARGE_INTEGER nextcnt;
-static LARGE_INTEGER slice;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief Low level HAL driver initialization.
- */
-void hal_lld_init(void) {
-  WSADATA wsaData;
-
-  /* Initialization.*/
-  if (WSAStartup(2, &wsaData) != 0) {
-    printf("Unable to locate a winsock DLL\n");
-    exit(1);
-  }
-
-  printf("ChibiOS/RT simulator (Win32)\n");
-  if (!QueryPerformanceFrequency(&slice)) {
-    printf("QueryPerformanceFrequency() error");
-    exit(1);
-  }
-  slice.QuadPart /= CH_FREQUENCY;
-  QueryPerformanceCounter(&nextcnt);
-  nextcnt.QuadPart += slice.QuadPart;
-
-  fflush(stdout);
-}
-
-/**
- * @brief Interrupt simulation.
- */
-void ChkIntSources(void) {
-  LARGE_INTEGER n;
-
-#if HAL_USE_SERIAL
-  if (sd_lld_interrupt_pending()) {
-    dbg_check_lock();
-    if (chSchIsPreemptionRequired())
-      chSchDoReschedule();
-    dbg_check_unlock();
-    return;
-  }
-#endif
-
-  /* Interrupt Timer simulation (10ms interval).*/
-  QueryPerformanceCounter(&n);
-  if (n.QuadPart > nextcnt.QuadPart) {
-    nextcnt.QuadPart += slice.QuadPart;
-
-    CH_IRQ_PROLOGUE();
-
-    chSysLockFromIsr();
-    chSysTimerHandlerI();
-    chSysUnlockFromIsr();
-
-    CH_IRQ_EPILOGUE();
-
-    dbg_check_lock();
-    if (chSchIsPreemptionRequired())
-      chSchDoReschedule();
-    dbg_check_unlock();
-  }
-}
-
-/** @} */
diff --git a/os/hal/platforms/Win32/hal_lld.h b/os/hal/platforms/Win32/hal_lld.h
deleted file mode 100644
index 2f07c682d..000000000
--- a/os/hal/platforms/Win32/hal_lld.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Win32/hal_lld.h
- * @brief   WIN32 simulator HAL subsystem low level driver header.
- *
- * @addtogroup WIN32_HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include <windows.h>
-#include <stdio.h>
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief   Platform name.
- */
-#define PLATFORM_NAME   "Win32"
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void ChkIntSources(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Win32/pal_lld.c b/os/hal/platforms/Win32/pal_lld.c
deleted file mode 100644
index 94f5380b3..000000000
--- a/os/hal/platforms/Win32/pal_lld.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Win32/pal_lld.c
- * @brief   Win32 low level simulated PAL driver code.
- *
- * @addtogroup WIN32_PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   VIO1 simulated port.
- */
-sim_vio_port_t vio_port_1;
-
-/**
- * @brief   VIO2 simulated port.
- */
-sim_vio_port_t vio_port_2;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @note This function is not meant to be invoked directly by the application
- *       code.
- * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high
- *       state.
- * @note This function does not alter the @p PINSELx registers. Alternate
- *       functions setup must be handled by device-specific code.
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  switch (mode) {
-  case PAL_MODE_RESET:
-  case PAL_MODE_INPUT:
-    port->dir &= ~mask;
-    break;
-  case PAL_MODE_UNCONNECTED:
-    port->latch |= mask;
-  case PAL_MODE_OUTPUT_PUSHPULL:
-    port->dir |= mask;
-    break;
-  }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/Win32/pal_lld.h b/os/hal/platforms/Win32/pal_lld.h
deleted file mode 100644
index 59273a109..000000000
--- a/os/hal/platforms/Win32/pal_lld.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Win32/pal_lld.h
- * @brief   Win32 low level simulated PAL driver header.
- *
- * @addtogroup WIN32_PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLUP
-#undef PAL_MODE_INPUT_PULLDOWN
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-#undef PAL_MODE_INPUT_ANALOG
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   VIO port structure.
- */
-typedef struct {
-  /**
-   * @brief   VIO_LATCH register.
-   * @details This register represents the output latch of the VIO port.
-   */
-  uint32_t          latch;
-  /**
-   * @brief   VIO_PIN register.
-   * @details This register represents the logical level at the VIO port
-   *          pin level.
-   */
-  uint32_t          pin;
-  /**
-   * @brief   VIO_DIR register.
-   * @details Direction of the VIO port bits, 0=input, 1=output.
-   */
-  uint32_t          dir;
-} sim_vio_port_t;
-
-/**
- * @brief   Virtual I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-  /**
-   * @brief Virtual port 1 setup data.
-   */
-  sim_vio_port_t    VP1Data;
-  /**
-   * @brief Virtual port 2 setup data.
-   */
-  sim_vio_port_t    VP2Data;
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- */
-typedef sim_vio_port_t *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   VIO port 1 identifier.
- */
-#define IOPORT1         (&vio_port_1)
-
-/**
- * @brief   VIO port 2 identifier.
- */
-#define IOPORT2         (&vio_port_2)
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config)                                                \
-  (vio_port_1 = (config)->VP1Data,                                          \
-   vio_port_2 = (config)->VP2Data)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->pin)
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->latch)
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->latch = (bits))
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-#if !defined(__DOXYGEN__)
-extern sim_vio_port_t vio_port_1;
-extern sim_vio_port_t vio_port_2;
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/Win32/platform.mk b/os/hal/platforms/Win32/platform.mk
deleted file mode 100644
index 0887c1ae3..000000000
--- a/os/hal/platforms/Win32/platform.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-# List of all the Win32 platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/Win32/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/Win32/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/Win32/serial_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/Win32
diff --git a/os/hal/platforms/Win32/serial_lld.c b/os/hal/platforms/Win32/serial_lld.c
deleted file mode 100644
index bfa5b80f8..000000000
--- a/os/hal/platforms/Win32/serial_lld.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file Win32/serial_lld.c
- * @brief Win32 low level simulated serial driver code.
- * @addtogroup WIN32_SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief Serial driver 1 identifier.*/
-#if USE_WIN32_SERIAL1 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-/** @brief Serial driver 2 identifier.*/
-#if USE_WIN32_SERIAL2 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
-};
-
-static u_long nb = 1;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-static void init(SerialDriver *sdp, uint16_t port) {
-  struct sockaddr_in sad;
-  struct protoent *prtp;
-
-  if ((prtp = getprotobyname("tcp")) == NULL) {
-    printf("%s: Error mapping protocol name to protocol number\n", sdp->com_name);
-    goto abort;
-  }
-
-  sdp->com_listen = socket(PF_INET, SOCK_STREAM, prtp->p_proto);
-  if (sdp->com_listen == INVALID_SOCKET) {
-    printf("%s: Error creating simulator socket\n", sdp->com_name);
-    goto abort;
-  }
-
-  if (ioctlsocket(sdp->com_listen, FIONBIO, &nb) != 0) {
-    printf("%s: Unable to setup non blocking mode on socket\n", sdp->com_name);
-    goto abort;
-  }
-
-  memset(&sad, 0, sizeof(sad));
-  sad.sin_family = AF_INET;
-  sad.sin_addr.s_addr = INADDR_ANY;
-  sad.sin_port = htons(port);
-  if (bind(sdp->com_listen, (struct sockaddr *)&sad, sizeof(sad))) {
-    printf("%s: Error binding socket\n", sdp->com_name);
-    goto abort;
-  }
-
-  if (listen(sdp->com_listen, 1) != 0) {
-    printf("%s: Error listening socket\n", sdp->com_name);
-    goto abort;
-  }
-  printf("Full Duplex Channel %s listening on port %d\n", sdp->com_name, port);
-  return;
-
-abort:
-  if (sdp->com_listen != INVALID_SOCKET)
-    closesocket(sdp->com_listen);
-  WSACleanup();
-  exit(1);
-}
-
-static bool_t connint(SerialDriver *sdp) {
-
-  if (sdp->com_data == INVALID_SOCKET) {
-    struct sockaddr addr;
-    int addrlen = sizeof(addr);
-
-    if ((sdp->com_data = accept(sdp->com_listen, &addr, &addrlen)) == INVALID_SOCKET)
-      return FALSE;
-
-    if (ioctlsocket(sdp->com_data, FIONBIO, &nb) != 0) {
-      printf("%s: Unable to setup non blocking mode on data socket\n", sdp->com_name);
-      goto abort;
-    }
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, CHN_CONNECTED);
-    chSysUnlockFromIsr();
-    return TRUE;
-  }
-  return FALSE;
-abort:
-  if (sdp->com_listen != INVALID_SOCKET)
-    closesocket(sdp->com_listen);
-  if (sdp->com_data != INVALID_SOCKET)
-    closesocket(sdp->com_data);
-  WSACleanup();
-  exit(1);
-}
-
-static bool_t inint(SerialDriver *sdp) {
-
-  if (sdp->com_data != INVALID_SOCKET) {
-    int i;
-    uint8_t data[32];
-
-    /*
-     * Input.
-     */
-    int n = recv(sdp->com_data, data, sizeof(data), 0);
-    switch (n) {
-    case 0:
-      closesocket(sdp->com_data);
-      sdp->com_data = INVALID_SOCKET;
-      chSysLockFromIsr();
-      chnAddFlagsI(sdp, CHN_DISCONNECTED);
-      chSysUnlockFromIsr();
-      return FALSE;
-    case SOCKET_ERROR:
-      if (WSAGetLastError() == WSAEWOULDBLOCK)
-        return FALSE;
-      closesocket(sdp->com_data);
-      sdp->com_data = INVALID_SOCKET;
-      return FALSE;
-    }
-    for (i = 0; i < n; i++) {
-      chSysLockFromIsr();
-      sdIncomingDataI(sdp, data[i]);
-      chSysUnlockFromIsr();
-    }
-    return TRUE;
-  }
-  return FALSE;
-}
-
-static bool_t outint(SerialDriver *sdp) {
-
-  if (sdp->com_data != INVALID_SOCKET) {
-    int n;
-    uint8_t data[1];
-
-    /*
-     * Input.
-     */
-    chSysLockFromIsr();
-    n = sdRequestDataI(sdp);
-    chSysUnlockFromIsr();
-    if (n < 0)
-      return FALSE;
-    data[0] = (uint8_t)n;
-    n = send(sdp->com_data, data, sizeof(data), 0);
-    switch (n) {
-    case 0:
-      closesocket(sdp->com_data);
-      sdp->com_data = INVALID_SOCKET;
-      chSysLockFromIsr();
-      chnAddFlagsI(sdp, CHN_DISCONNECTED);
-      chSysUnlockFromIsr();
-      return FALSE;
-    case SOCKET_ERROR:
-      if (WSAGetLastError() == WSAEWOULDBLOCK)
-        return FALSE;
-      closesocket(sdp->com_data);
-      sdp->com_data = INVALID_SOCKET;
-      return FALSE;
-    }
-    return TRUE;
-  }
-  return FALSE;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * Low level serial driver initialization.
- */
-void sd_lld_init(void) {
-
-#if USE_WIN32_SERIAL1
-  sdObjectInit(&SD1, NULL, NULL);
-  SD1.com_listen = INVALID_SOCKET;
-  SD1.com_data = INVALID_SOCKET;
-  SD1.com_name = "SD1";
-#endif
-
-#if USE_WIN32_SERIAL1
-  sdObjectInit(&SD2, NULL, NULL);
-  SD2.com_listen = INVALID_SOCKET;
-  SD2.com_data = INVALID_SOCKET;
-  SD2.com_name = "SD2";
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-#if USE_WIN32_SERIAL1
-  if (sdp == &SD1)
-    init(&SD1, SD1_PORT);
-#endif
-
-#if USE_WIN32_SERIAL1
-  if (sdp == &SD2)
-    init(&SD2, SD2_PORT);
-#endif
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  (void)sdp;
-}
-
-bool_t sd_lld_interrupt_pending(void) {
-  bool_t b;
-
-  CH_IRQ_PROLOGUE();
-
-  b =  connint(&SD1) || connint(&SD2) ||
-       inint(&SD1)   || inint(&SD2)   ||
-       outint(&SD1)  || outint(&SD2);
-
-  CH_IRQ_EPILOGUE();
-
-  return b;
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/Win32/serial_lld.h b/os/hal/platforms/Win32/serial_lld.h
deleted file mode 100644
index 9618ae5b9..000000000
--- a/os/hal/platforms/Win32/serial_lld.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    Win32/serial_lld.h
- * @brief   Win32 low level simulated serial driver header.
- *
- * @addtogroup WIN32_SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Serial buffers size.
- * @details Configuration parameter, you can change the depth of the queue
- *          buffers depending on the requirements of your application.
- */
-#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define SERIAL_BUFFERS_SIZE 1024
-#endif
-
-/**
- * @brief   SD1 driver enable switch.
- * @details If set to @p TRUE the support for SD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_WIN32_SERIAL1) || defined(__DOXYGEN__)
-#define USE_WIN32_SERIAL1 TRUE
-#endif
-
-/**
- * @brief   SD2 driver enable switch.
- * @details If set to @p TRUE the support for SD2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(USE_WIN32_SERIAL2) || defined(__DOXYGEN__)
-#define USE_WIN32_SERIAL2 TRUE
-#endif
-
-/**
- * @brief   Listen port for SD1.
- */
-#if !defined(SD1_PORT) || defined(__DOXYGEN__)
-#define SD1_PORT  29001
-#endif
-
-/**
- * @brief   Listen port for SD2.
- */
-#if !defined(SD2_PORT) || defined(__DOXYGEN__)
-#define SD2_PORT  29002
-#endif
-
-/*===========================================================================*/
-/* Unsupported event flags and custom events.                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    This structure content is architecture dependent, each driver
- *          implementation defines its own version and the custom static
- *          initializers.
- */
-typedef struct {
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Listen socket for simulated serial port.*/                             \
-  SOCKET                    com_listen;                                     \
-  /* Data socket for simulated serial port.*/                               \
-  SOCKET                    com_data;                                       \
-  /* Port readable name.*/                                                  \
-  const char                *com_name;
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if USE_WIN32_SERIAL1 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if USE_WIN32_SERIAL2 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-  bool_t sd_lld_interrupt_pending(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/platforms.dox b/os/hal/platforms/platforms.dox
deleted file mode 100644
index 3ff14f700..000000000
--- a/os/hal/platforms/platforms.dox
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @defgroup platforms Platforms
- * @brief Supported platforms.
- * @details The implementation of the device drivers can be slightly different
- * on the various platforms because architectural constrains. This section
- * describes the implementation of the various device drivers on the various
- * supported platforms.
- */
diff --git a/os/hal/ports/STM32/LLD/DACv1/dac_lld.c b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c
new file mode 100644
index 000000000..943f388fa
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c
@@ -0,0 +1,351 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32/DACv1/dac_lld.c
+ * @brief   STM32 DAC subsystem low level driver source.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_DAC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if !defined(DAC1)
+#define DAC1 DAC
+#define rccEnableDAC1 rccEnableDAC
+#define rccDisableDAC1 rccDisableDAC
+#endif
+
+#define DAC_CHN1_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_DAC_CHN1_DMA_STREAM,                            \
+                       STM32_DAC_CHN1_DMA_CHN)
+
+#define DAC_CHN2_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_DAC_CHN2_DMA_STREAM,                            \
+                       STM32_DAC_CHN2_DMA_CHN)
+           
+#define DAC_CHN3_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_DAC_CHN3_DMA_STREAM,                            \
+                       STM32_DAC_CHN3_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief CHN1 driver identifier.*/
+#if STM32_DAC_USE_CHN1 || defined(__DOXYGEN__)
+DACDriver DACD1;
+#endif
+
+/** @brief CHN2 driver identifier.*/
+#if STM32_DAC_USE_CHN2 || defined(__DOXYGEN__)
+DACDriver DACD2;
+#endif
+
+/** @brief CHN3 driver identifier.*/
+#if STM32_DAC_USE_CHN3 || defined(__DOXYGEN__)
+DACDriver DACD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared end/half-of-tx service routine.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
+
+#if defined(STM32_DAC_DMA_ERROR_HOOK)
+  (void)dacp;
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    /* DMA errors handling.*/
+    //~ _dac_isr_error_code(dacp, flags);
+  }
+  else {
+    if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+      /* Half transfer processing.*/
+      //~ _dac_isr_half_code(dacp);
+    }
+    if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+      /* Transfer complete processing.*/
+      //~ _dac_isr_full_code(dacp);
+    }
+  }
+#else
+  (void)dacp;
+  (void)flags;
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level DAC driver initialization.
+ *
+ * @notapi
+ */
+void dac_lld_init(void) {
+
+#if STM32_DAC_USE_CHN1
+  dacObjectInit(&DACD1);
+  DACD1.dac     = DAC1;
+  DACD1.tim     = STM32_TIM6;
+  DACD1.irqprio = STM32_DAC_CHN1_IRQ_PRIORITY;
+  DACD1.dma     = STM32_DMA_STREAM(STM32_DAC_CHN1_DMA_STREAM);
+  DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN1_DMA_CHANNEL) |                  \
+                  STM32_DMA_CR_PL(STM32_DAC_CHN1_DMA_PRIORITY) |              \
+                  STM32_DMA_CR_DIR_M2P |                                      \
+                  STM32_DMA_CR_DMEIE |                                        \
+                  STM32_DMA_CR_TEIE |                                         \
+                  STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
+#endif
+
+#if STM32_DAC_USE_CHN2
+  dacObjectInit(&DACD2);
+  DACD2.dac     = DAC1;
+  DACD2.tim     = STM32_TIM7;
+  DACD2.irqprio = STM32_DAC_CHN2_IRQ_PRIORITY;
+  DACD2.dma     = STM32_DMA_STREAM(STM32_DAC_CHN2_DMA_STREAM);
+  DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN2_DMA_CHANNEL) |                  \
+                  STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) |              \
+                  STM32_DMA_CR_DIR_M2P |                                      \
+                  STM32_DMA_CR_DMEIE |                                        \
+                  STM32_DMA_CR_TEIE |                                         \
+                  STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
+#endif
+
+#if STM32_DAC_USE_CHN3
+  dacObjectInit(&DACD3);
+  DACD3.dac     = DAC2;
+  DACD3.tim     = STM32_TIM18;
+  DACD3.irqprio = STM32_DAC_CHN3_IRQ_PRIORITY;
+  DACD3.dma     = STM32_DMA_STREAM(STM32_DAC_CHN3_DMA_STREAM);
+  DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN3_DMA_CHANNEL) |                  \
+                  STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) |              \
+                  STM32_DMA_CR_DIR_M2P |                                      \
+                  STM32_DMA_CR_DMEIE |                                        \
+                  STM32_DMA_CR_TEIE |                                         \
+                  STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the DAC peripheral.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_start(DACDriver *dacp) {
+  uint32_t arr, regshift, trgo, dataoffset;
+  bool b;
+  /* If in stopped state then enables the DAC and DMA clocks.*/
+  if (dacp->state == DAC_STOP) {
+#if STM32_DAC_USE_CHN1
+    if (&DACD1 == dacp) {
+      rccEnableDAC1(FALSE);
+      /* DAC1 CR data is at bits 0:15 */
+      regshift = 0;
+      dataoffset = 0;
+      /* Timer setup */
+      rccEnableTIM6(FALSE);
+      rccResetTIM6();
+      trgo = STM32_DAC_CR_TSEL_TIM6;
+    }
+#endif
+#if STM32_DAC_USE_CHN2
+    if (&DACD2 == dacp) {
+      rccEnableDAC1(FALSE);
+      /* DAC2 CR data is at bits 16:31 */
+      regshift = 16;
+      dataoffset = &dacp->dac->DHR12R2 - &dacp->dac->DHR12R1;
+      /* Timer setup */
+      rccEnableTIM7(FALSE);
+      rccResetTIM7();
+      trgo = STM32_DAC_CR_TSEL_TIM7;
+    }
+#endif
+#if STM32_DAC_USE_CHN3
+    if (&DACD3 == dacp) {
+      rccEnableDAC2(FALSE);
+      /* DAC3 CR data is at bits 0:15 */
+      regshift = 0;
+      dataoffset = 0;
+      /* Timer setup */
+      rccEnableTIM18(FALSE);
+      rccResetTIM18();
+      trgo = STM32_DAC_CR_TSEL_TIM18;
+    }
+#endif
+#if STM32_DAC_USE_CHN1 || STM32_DAC_USE_CHN2 || STM32_DAC_USE_CHN3
+    dacp->clock = STM32_TIMCLK1;
+    arr = (dacp->clock / dacp->config->frequency);
+    osalDbgAssert((arr <= 0xFFFF),
+        "invalid frequency");
+
+    /* Timer configuration.*/
+    dacp->tim->CR1  = 0;                        /* Initially stopped.   */
+    dacp->tim->PSC  = 0;                        /* Prescaler value.     */
+    dacp->tim->DIER = 0;
+    dacp->tim->ARR  = arr;
+    dacp->tim->EGR  = TIM_EGR_UG;               /* Update event.        */
+    dacp->tim->CR2  &= (uint16_t)~TIM_CR2_MMS;
+    dacp->tim->CR2  |= (uint16_t)TIM_CR2_MMS_1; /* Enable TRGO updates. */
+    dacp->tim->CNT  = 0;                        /* Reset counter.       */
+    dacp->tim->SR   = 0;                        /* Clear pending IRQs.  */
+    /* Update Event IRQ enabled. */
+    /* Timer start.*/
+    dacp->tim->CR1  = TIM_CR1_CEN;
+
+    /* DAC configuration */
+    dacp->dac->CR |= ( (dacp->dac->CR & ~STM32_DAC_CR_MASK) | \
+      (STM32_DAC_CR_EN | STM32_DAC_CR_DMAEN | dacp->config->cr_flags) ) << regshift;
+      
+    /* DMA setup. */
+    b = dmaStreamAllocate(dacp->dma,
+          dacp->irqprio,
+          (stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
+          (void *)dacp);
+    osalDbgAssert(!b, "stream already allocated");
+    switch (dacp->config->dhrm) {
+      /* Sets the DAC data register */
+      case DAC_DHRM_12BIT_RIGHT:
+        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12R1 + dataoffset);
+        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
+              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+        break;
+      case DAC_DHRM_12BIT_LEFT:
+        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12L1 + dataoffset);
+        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
+              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+        break;
+      case DAC_DHRM_8BIT_RIGHT:
+        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8R1 + dataoffset);
+        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
+              STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
+        break;
+#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2
+      case DAC_DHRM_12BIT_RIGHT_DUAL:
+        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12RD);
+        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
+              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+        break;
+      case DAC_DHRM_12BIT_LEFT_DUAL:
+        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12LD);
+        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
+              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+        break;
+      case DAC_DHRM_8BIT_RIGHT_DUAL:
+        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8RD);
+        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
+             STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
+        break;
+#endif
+  }
+  
+  dacp->dac->CR |= trgo << regshift; /* Enable timer trigger */
+#endif
+  }
+}
+
+/**
+ * @brief   Deactivates the DAC peripheral.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_stop(DACDriver *dacp) {
+
+  /* If in ready state then disables the DAC clock.*/
+  if (dacp->state == DAC_READY) {
+
+    /* DMA disable.*/
+    dmaStreamRelease(dacp->dma);
+
+#if STM32_DAC_USE_CHN1
+    if (&DACD1 == dacp) {
+      dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC1 disable.*/
+    }
+#endif
+#if STM32_DAC_USE_CHN2
+    if (&DACD2 == dacp) {
+      dacp->dac->CR &= ~STM32_DAC_CR_EN << 16; /* DAC1 disable.*/
+    }
+#endif
+#if STM32_DAC_USE_CHN3
+    if (&DACD3 == dacp) {
+      dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC2 disable.*/
+      rccDisableDAC2(FALSE); /* DAC Clock disable.*/
+    }
+#endif
+    dacp->tim->CR1 &= ~TIM_CR1_CEN; /* Disable associated timer */
+    dacp->state = DAC_STOP;
+
+    if (!(DAC1->CR & (STM32_DAC_CR_EN | STM32_DAC_CR_EN << 16))) {
+      /* DAC Clock disable only if all channels are off.*/
+      rccDisableDAC1(FALSE);
+    }
+  }
+}
+
+/**
+ * @brief   Sends data over the DAC bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ * @param[in] n         number of words to send
+ * @param[in] txbuf     the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void dac_lld_start_conversion(DACDriver *dacp) {
+  osalDbgAssert(dacp->samples, 
+    "dacp->samples is NULL pointer");
+  dmaStreamSetMemory0(dacp->dma, dacp->samples);
+  dmaStreamSetTransactionSize(dacp->dma, dacp->depth);
+  dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN |
+  STM32_DMA_CR_CIRC);
+}
+#endif /* HAL_USE_DAC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/DACv1/dac_lld.h b/os/hal/ports/STM32/LLD/DACv1/dac_lld.h
new file mode 100644
index 000000000..8e219f0fa
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/DACv1/dac_lld.h
@@ -0,0 +1,415 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32/DACv1/dac_lld.h
+ * @brief   STM32 DAC subsystem low level driver header.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#ifndef _DAC_LLD_H_
+#define _DAC_LLD_H_
+
+#include "stm32_tim.h"
+
+#if HAL_USE_DAC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+#define STM32_DAC_CR_EN DAC_CR_EN1
+#define STM32_DAC_CR_DMAEN DAC_CR_DMAEN1
+#define STM32_DAC_CR_TEN DAC_CR_TEN1
+
+#define STM32_DAC_CR_MASK (uint32_t)0x00000FFE
+
+#define STM32_DAC_CR_BOFF_ENABLE    (uint32_t)0x00000000
+#define STM32_DAC_CR_BOFF_DISABLE   DAC_CR_BOFF1
+
+#define STM32_DAC_CR_TSEL_NONE     (uint32_t)0x00000000
+#define STM32_DAC_CR_TSEL_TIM2     DAC_CR_TEN1 | DAC_CR_TSEL1_2
+#define STM32_DAC_CR_TSEL_TIM4     DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_2
+#define STM32_DAC_CR_TSEL_TIM5     DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1
+#define STM32_DAC_CR_TSEL_TIM6     DAC_CR_TEN1
+#define STM32_DAC_CR_TSEL_TIM7     DAC_CR_TEN1 | DAC_CR_TSEL1_1
+#define STM32_DAC_CR_TSEL_TIM3     DAC_CR_TEN1 | DAC_CR_TSEL1_0
+#define STM32_DAC_CR_TSEL_TIM18     DAC_CR_TEN1 | DAC_CR_TSEL1_0 | DAC_CR_TSEL1_1
+#define STM32_DAC_CR_TSEL_EXT_IT9  DAC_CR_TEN1 | DAC_CR_TEN1 | DAC_CR_TSEL1_2
+#define STM32_DAC_CR_TSEL_SOFT     DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_2
+
+#define STM32_DAC_CR_WAVE_NONE      (uint32_t)0x00000000
+#define STM32_DAC_CR_WAVE_NOISE     DAC_CR_WAVE1_0
+#define STM32_DAC_CR_WAVE_TRIANGLE  DAC_CR_WAVE1_1
+
+#define STM32_DAC_MAMP_1 (uint32_t)0x00000000
+#define STM32_DAC_MAMP_3    DAC_CR_MAMP1_0
+#define STM32_DAC_MAMP_7    DAC_CR_MAMP1_1
+#define STM32_DAC_MAMP_15   DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1
+#define STM32_DAC_MAMP_31   DAC_CR_MAMP1_2
+#define STM32_DAC_MAMP_63   DAC_CR_MAMP1_0 | DAC_CR_MAMP1_2
+#define STM32_DAC_MAMP_127  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
+#define STM32_DAC_MAMP_255  DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
+#define STM32_DAC_MAMP_511  DAC_CR_MAMP1_3
+#define STM32_DAC_MAMP_1023 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_3
+#define STM32_DAC_MAMP_2047 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_3
+#define STM32_DAC_MAMP_4095 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   DAC CHN1 driver enable switch.
+ * @details If set to @p TRUE the support for DAC CHN1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_DAC_USE_CHN1) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_CHN1                  FALSE
+#endif
+
+/**
+ * @brief   DAC CHN2 driver enable switch.
+ * @details If set to @p TRUE the support for DAC CHN2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_DAC_USE_CHN2) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_CHN2                  FALSE
+#endif
+
+/**
+ * @brief   DAC CHN3 driver enable switch.
+ * @details If set to @p TRUE the support for DAC CHN3 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_DAC_USE_CHN3) || defined(__DOXYGEN__)
+#define STM32_DAC_USE_CHN3                  FALSE
+#endif
+
+/**
+ * @brief   DAC CHN1 interrupt priority level setting.
+ */
+#if !defined(STM32_DAC_CHN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_CHN1_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   DAC CHN2 interrupt priority level setting.
+ */
+#if !defined(STM32_DAC_CHN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_CHN2_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   DAC CHN3 interrupt priority level setting.
+ */
+#if !defined(STM32_DAC_CHN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_CHN3_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   DAC CHN1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_DAC_CHN1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_CHN1_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   DAC CHN2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_DAC_CHN2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_CHN2_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   DAC CHN3 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_DAC_CHN3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_DAC_CHN2_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   DAC DMA error hook.
+ */
+#if !defined(STM32_DAC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_DAC_DMA_ERROR_HOOK(dacp)      osalSysHalt()
+#endif
+
+/**
+ * @brief   DMA stream used for DAC CHN1 TX operations.
+ * @note    This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_DAC_CHN1_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_DAC_CHN1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 3)
+#endif
+
+/**
+ * @brief   DMA stream used for DAC CHN2 TX operations.
+ * @note    This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_DAC_CHN2_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_DAC_CHN2_DMA_STREAM           STM32_DMA_STREAM_ID(1, 4)
+#endif
+
+/**
+ * @brief   DMA stream used for DAC CHN3 TX operations.
+ * @note    This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_DAC_CHN3_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_DAC_CHN3_DMA_STREAM           STM32_DMA_STREAM_ID(1, 5)
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_DAC_USE_CHN1 && !STM32_HAS_DAC_CHN1
+#error "DAC CHN1 not present in the selected device"
+#endif
+
+#if STM32_DAC_USE_CHN2 && !STM32_HAS_DAC_CHN2
+#error "DAC CHN2 not present in the selected device"
+#endif
+
+#if STM32_DAC_USE_CHN3 && !STM32_HAS_DAC_CHN3
+#error "DAC CHN3 not present in the selected device"
+#endif
+
+#if !STM32_DAC_USE_CHN1  && !STM32_DAC_USE_CHN2 && !STM32_DAC_USE_CHN3
+#error "DAC driver activated but no DAC peripheral assigned"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+   reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_DAC_USE_CHN1 && !defined(STM32_DAC_CHN1_DMA_STREAM)
+#error "DAC1 CHN1 DMA stream not defined"
+#endif
+
+#if STM32_DAC_USE_CHN2 && !defined(STM32_DAC_CHN2_DMA_STREAM)
+#error "DAC1 CHN2 DMA stream not defined"
+#endif
+
+#if STM32_DAC_USE_CHN3 && !defined(STM32_DAC_CHN3_DMA_STREAM)
+#error "DAC1 CHN3 DMA stream not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_DAC_USE_CHN1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN1_DMA_STREAM, STM32_DAC_CHN1_DMA_MSK)
+#error "invalid DMA stream associated to DAC CHN1"
+#endif
+
+#if STM32_DAC_USE_CHN2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN2_DMA_STREAM, STM32_DAC_CHN2_DMA_MSK)
+#error "invalid DMA stream associated to DAC CHN2"
+#endif
+
+#if STM32_DAC_USE_CHN3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN3_DMA_STREAM, STM32_DAC_CHN3_DMA_MSK)
+#error "invalid DMA stream associated to DAC CHN3"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an DAC driver.
+ */
+typedef struct DACDriver DACDriver;
+
+/**
+ * @brief   Type representing a DAC sample.
+ */
+typedef uint16_t dacsample_t;
+
+/**
+ * @brief   DAC notification callback type.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object triggering the
+ *                      callback
+ */
+typedef void (*daccallback_t)(DACDriver *dacp);
+
+typedef enum { 
+  DAC_DHRM_12BIT_RIGHT = 0,
+  DAC_DHRM_12BIT_LEFT = 1,
+  DAC_DHRM_8BIT_RIGHT = 2,
+#if STM32_HAS_DAC_CHN2 && !defined(__DOXYGEN__)
+  DAC_DHRM_12BIT_RIGHT_DUAL = 3,
+  DAC_DHRM_12BIT_LEFT_DUAL = 4,
+  DAC_DHRM_8BIT_RIGHT_DUAL = 5
+#endif
+} dacdhrmode_t;
+
+/**
+ * @brief   DAC Conversion group structure.
+ */
+typedef struct {
+  /**
+   * @brief Number of DAC channels.
+   */
+  uint32_t                  num_channels;
+  /**
+   * @brief Operation complete callback or @p NULL.
+   */
+  daccallback_t             end_cb;
+  /**
+   * @brief Error handling callback or @p NULL.
+   */
+  daccallback_t             error_cb;
+  
+} DACConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief   Timer frequency in Hz.
+   */
+  uint32_t                  frequency;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   DAC data holding register mode.
+   */
+  dacdhrmode_t              dhrm;
+  /**
+   * @brief DAC initialization data.
+   */
+  uint32_t                  cr_flags;
+} DACConfig;
+
+/**
+ * @brief   Structure representing a DAC driver.
+ */
+struct DACDriver {
+  /**
+   * @brief Driver state.
+   */
+  dacstate_t                state;
+  /**
+   * @brief Conversion group.
+   */
+  const DACConversionGroup  *grpp;
+  /**
+   * @brief Samples buffer pointer.
+   */
+  const dacsample_t         *samples;
+  /**
+   * @brief Samples buffer size.
+   */
+  uint16_t                  depth;
+  /**
+   * @brief Current configuration data.
+   */
+  const DACConfig           *config;
+#if DAC_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif /* DAC_USE_WAIT */
+#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the bus.
+   */
+  mutex_t                   mutex;
+#endif /* DAC_USE_MUTUAL_EXCLUSION */
+#if defined(DAC_DRIVER_EXT_FIELDS)
+  DAC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the DAC registers block.
+   */
+  DAC_TypeDef               *dac;
+  /**
+   * @brief Pointer to the TIMx registers block.
+   */
+  stm32_tim_t               *tim;
+  /**
+   * @brief The Timer IRQ priority.
+   */
+  uint32_t                  irqprio;
+  /**
+   * @brief Transmit DMA stream.
+   */
+  const stm32_dma_stream_t  *dma;
+  /**
+   * @brief TX DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+  /**
+   * @brief Timer base clock.
+   */
+  uint32_t                  clock;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_DAC_USE_CHN1 && !defined(__DOXYGEN__)
+extern DACDriver DACD1;
+#endif
+
+#if STM32_DAC_USE_CHN2 && !defined(__DOXYGEN__)
+extern DACDriver DACD2;
+#endif
+
+#if STM32_DAC_USE_CHN3 && !defined(__DOXYGEN__)
+extern DACDriver DACD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dac_lld_init(void);
+  void dac_lld_start(DACDriver *dacp);
+  void dac_lld_stop(DACDriver *dacp);
+  void dac_lld_start_conversion(DACDriver *dacp);
+  void dac_lld_stop_conversion(DACDriver *dacp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_DAC */
+
+#endif /* _DAC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c
new file mode 100644
index 000000000..decfa9b28
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c
@@ -0,0 +1,183 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/GPIOv1/pal_lld.c
+ * @brief   STM32F1xx GPIO low level driver code.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if STM32_HAS_GPIOG
+#define APB2_EN_MASK  (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |            \
+                       RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |            \
+                       RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN |            \
+                       RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
+#elif STM32_HAS_GPIOE
+#define APB2_EN_MASK  (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |            \
+                       RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |            \
+                       RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN)
+#else
+#define APB2_EN_MASK  (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |            \
+                       RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |            \
+                       RCC_APB2ENR_AFIOEN)
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 I/O ports configuration.
+ * @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled.
+ *
+ * @param[in] config    the STM32 ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config) {
+
+  /*
+   * Enables the GPIO related clocks.
+   */
+  rccEnableAPB2(APB2_EN_MASK, FALSE);
+
+  /*
+   * Initial GPIO setup.
+   */
+  GPIOA->ODR = config->PAData.odr;
+  GPIOA->CRH = config->PAData.crh;
+  GPIOA->CRL = config->PAData.crl;
+  GPIOB->ODR = config->PBData.odr;
+  GPIOB->CRH = config->PBData.crh;
+  GPIOB->CRL = config->PBData.crl;
+  GPIOC->ODR = config->PCData.odr;
+  GPIOC->CRH = config->PCData.crh;
+  GPIOC->CRL = config->PCData.crl;
+  GPIOD->ODR = config->PDData.odr;
+  GPIOD->CRH = config->PDData.crh;
+  GPIOD->CRL = config->PDData.crl;
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+  GPIOE->ODR = config->PEData.odr;
+  GPIOE->CRH = config->PEData.crh;
+  GPIOE->CRL = config->PEData.crl;
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+  GPIOF->ODR = config->PFData.odr;
+  GPIOF->CRH = config->PFData.crh;
+  GPIOF->CRL = config->PFData.crl;
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+  GPIOG->ODR = config->PGData.odr;
+  GPIOG->CRH = config->PGData.crh;
+  GPIOG->CRL = config->PGData.crl;
+#endif
+#endif
+#endif
+}
+
+/**
+ * @brief   Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ *          with the specified mode.
+ * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz.
+ * @note    Writing on pads programmed as pull-up or pull-down has the side
+ *          effect to modify the resistor setting because the output latched
+ *          data is used for the resistor selection.
+ *
+ * @param[in] port      the port identifier
+ * @param[in] mask      the group mask
+ * @param[in] mode      the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+                           ioportmask_t mask,
+                           iomode_t mode) {
+  static const uint8_t cfgtab[] = {
+    4,          /* PAL_MODE_RESET, implemented as input.*/
+    2,          /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/
+    4,          /* PAL_MODE_INPUT */
+    8,          /* PAL_MODE_INPUT_PULLUP */
+    8,          /* PAL_MODE_INPUT_PULLDOWN */
+    0,          /* PAL_MODE_INPUT_ANALOG */
+    3,          /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/
+    7,          /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/
+    8,          /* Reserved.*/
+    8,          /* Reserved.*/
+    8,          /* Reserved.*/
+    8,          /* Reserved.*/
+    8,          /* Reserved.*/
+    8,          /* Reserved.*/
+    8,          /* Reserved.*/
+    8,          /* Reserved.*/
+    0xB,        /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/
+    0xF,        /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/
+  };
+  uint32_t mh, ml, crh, crl, cfg;
+  unsigned i;
+
+  if (mode == PAL_MODE_INPUT_PULLUP)
+    port->BSRR = mask;
+  else if (mode == PAL_MODE_INPUT_PULLDOWN)
+    port->BRR = mask;
+  cfg = cfgtab[mode];
+  mh = ml = crh = crl = 0;
+  for (i = 0; i < 8; i++) {
+    ml <<= 4;
+    mh <<= 4;
+    crl <<= 4;
+    crh <<= 4;
+    if ((mask & 0x0080) == 0)
+      ml |= 0xf;
+    else
+      crl |= cfg;
+    if ((mask & 0x8000) == 0)
+      mh |= 0xf;
+    else
+      crh |= cfg;
+    mask <<= 1;
+  }
+  port->CRH = (port->CRH & mh) | crh;
+  port->CRL = (port->CRL & ml) | crl;
+}
+
+#endif /* HAL_USE_PAL */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/GPIOv1/pal_lld.h b/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.h
index 56255ed1a..56255ed1a 100644
--- a/os/hal/platforms/STM32/GPIOv1/pal_lld.h
+++ b/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.h
diff --git a/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c
new file mode 100644
index 000000000..2ded0a6ef
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c
@@ -0,0 +1,254 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/GPIOv2/pal_lld.c
+ * @brief   STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver code.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if defined(STM32L1XX)
+#define AHB_EN_MASK     (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |          \
+                         RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN |          \
+                         RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
+#define AHB_LPEN_MASK   AHB_EN_MASK
+
+#elif defined(STM32F030) || defined(STM32F0XX_MD)
+#define AHB_EN_MASK     (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |          \
+                         RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN |          \
+                         RCC_AHBENR_GPIOFEN)
+
+#elif defined(STM32F0XX_LD)
+#define AHB_EN_MASK     (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |          \
+                         RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN)
+
+#elif defined(STM32F2XX)
+#define AHB1_EN_MASK    (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |        \
+                         RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |        \
+                         RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |        \
+                         RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN |        \
+                         RCC_AHB1ENR_GPIOIEN)
+#define AHB1_LPEN_MASK  AHB1_EN_MASK
+
+#elif defined(STM32F30X) || defined(STM32F37X)
+#define AHB_EN_MASK     (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN |          \
+                         RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN |          \
+                         RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN)
+
+#elif defined(STM32F4XX)
+#define AHB1_EN_MASK    (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |        \
+                         RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |        \
+                         RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |        \
+                         RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN |        \
+                         RCC_AHB1ENR_GPIOIEN)
+#define AHB1_LPEN_MASK  AHB1_EN_MASK
+
+#else
+#error "missing or unsupported platform for GPIOv2 PAL driver"
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+static void initgpio(stm32_gpio_t *gpiop, const stm32_gpio_setup_t *config) {
+
+  gpiop->OTYPER  = config->otyper;
+  gpiop->OSPEEDR = config->ospeedr;
+  gpiop->PUPDR   = config->pupdr;
+  gpiop->ODR     = config->odr;
+  gpiop->AFRL    = config->afrl;
+  gpiop->AFRH    = config->afrh;
+  gpiop->MODER   = config->moder;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 I/O ports configuration.
+ * @details Ports A-D(E, F, G, H) clocks enabled.
+ *
+ * @param[in] config    the STM32 ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config) {
+
+  /*
+   * Enables the GPIO related clocks.
+   */
+#if defined(STM32L1XX)
+  rccEnableAHB(AHB_EN_MASK, TRUE);
+  RCC->AHBLPENR |= AHB_LPEN_MASK;
+#elif defined(STM32F0XX)
+  rccEnableAHB(AHB_EN_MASK, TRUE);
+#elif defined(STM32F30X) || defined(STM32F37X)
+  rccEnableAHB(AHB_EN_MASK, TRUE);
+#elif defined(STM32F2XX) || defined(STM32F4XX)
+  RCC->AHB1ENR   |= AHB1_EN_MASK;
+  RCC->AHB1LPENR |= AHB1_LPEN_MASK;
+#endif
+
+  /*
+   * Initial GPIO setup.
+   */
+#if STM32_HAS_GPIOA
+  initgpio(GPIOA, &config->PAData);
+#endif
+#if STM32_HAS_GPIOB
+  initgpio(GPIOB, &config->PBData);
+#endif
+#if STM32_HAS_GPIOC
+  initgpio(GPIOC, &config->PCData);
+#endif
+#if STM32_HAS_GPIOD
+  initgpio(GPIOD, &config->PDData);
+#endif
+#if STM32_HAS_GPIOE
+  initgpio(GPIOE, &config->PEData);
+#endif
+#if STM32_HAS_GPIOF
+  initgpio(GPIOF, &config->PFData);
+#endif
+#if STM32_HAS_GPIOG
+  initgpio(GPIOG, &config->PGData);
+#endif
+#if STM32_HAS_GPIOH
+  initgpio(GPIOH, &config->PHData);
+#endif
+#if STM32_HAS_GPIOI
+  initgpio(GPIOI, &config->PIData);
+#endif
+}
+
+/**
+ * @brief   Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ *          with the specified mode.
+ * @note    @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum
+ *          speed.
+ *
+ * @param[in] port      the port identifier
+ * @param[in] mask      the group mask
+ * @param[in] mode      the mode
+ *
+ * @notapi
+ */
+#if 1
+void _pal_lld_setgroupmode(ioportid_t port,
+                           ioportmask_t mask,
+                           iomode_t mode) {
+
+  uint32_t moder   = (mode & PAL_STM32_MODE_MASK) >> 0;
+  uint32_t otyper  = (mode & PAL_STM32_OTYPE_MASK) >> 2;
+  uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3;
+  uint32_t pupdr   = (mode & PAL_STM32_PUDR_MASK) >> 5;
+  uint32_t altr    = (mode & PAL_STM32_ALTERNATE_MASK) >> 7;
+  uint32_t bit     = 0;
+  while (TRUE) {
+    if ((mask & 1) != 0) {
+      uint32_t altrmask, m1, m2, m4;
+
+      altrmask = altr << ((bit & 7) * 4);
+      m4 = 15 << ((bit & 7) * 4);
+      if (bit < 8)
+        port->AFRL = (port->AFRL & ~m4) | altrmask;
+      else
+        port->AFRH = (port->AFRH & ~m4) | altrmask;
+      m1 = 1 << bit;
+      port->OTYPER  = (port->OTYPER & ~m1) | otyper;
+      m2 = 3 << (bit * 2);
+      port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
+      port->PUPDR   = (port->PUPDR & ~m2) | pupdr;
+      port->MODER   = (port->MODER & ~m2) | moder;
+    }
+    mask >>= 1;
+    if (!mask)
+      return;
+    otyper <<= 1;
+    ospeedr <<= 2;
+    pupdr <<= 2;
+    moder <<= 2;
+    bit++;
+  }
+}
+#else
+void _pal_lld_setgroupmode(ioportid_t port,
+                           ioportmask_t mask,
+                           iomode_t mode) {
+  uint32_t afrm, moderm, pupdrm, otyperm, ospeedrm;
+  uint32_t m1 = (uint32_t)mask;
+  uint32_t m2 = 0;
+  uint32_t m4l = 0;
+  uint32_t m4h = 0;
+  uint32_t bit = 0;
+  do {
+    if ((mask & 1) != 0) {
+      m2 |= 3 << bit;
+      if (bit < 16)
+        m4l |= 15 << ((bit & 14) * 2);
+      else
+        m4h |= 15 << ((bit & 14) * 2);
+    }
+    bit += 2;
+    mask >>= 1;
+  } while (mask);
+
+  afrm = ((mode & PAL_STM32_ALTERNATE_MASK) >> 7) * 0x1111;
+  port->AFRL = (port->AFRL & ~m4l) | (afrm & m4l);
+  port->AFRH = (port->AFRH & ~m4h) | (afrm & m4h);
+
+  ospeedrm = ((mode & PAL_STM32_OSPEED_MASK) >> 3) * 0x5555;
+  port->OSPEEDR = (port->OSPEEDR & ~m2) | (ospeedrm & m2);
+
+  otyperm = ((mode & PAL_STM32_OTYPE_MASK) >> 2) * 0xffff;
+  port->OTYPER = (port->OTYPER & ~m1) | (otyperm & m1);
+
+  pupdrm = ((mode & PAL_STM32_PUDR_MASK) >> 5) * 0x5555;
+  port->PUPDR = (port->PUPDR & ~m2) | (pupdrm & m2);
+
+  moderm = ((mode & PAL_STM32_MODE_MASK) >> 0) * 0x5555;
+  port->MODER = (port->MODER & ~m2) | (moderm & m2);
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.h b/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.h
new file mode 100644
index 000000000..42b9ba02d
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.h
@@ -0,0 +1,491 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/GPIOv2/pal_lld.h
+ * @brief   STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef _PAL_LLD_H_
+#define _PAL_LLD_H_
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes                                      */
+/*===========================================================================*/
+
+#undef PAL_MODE_RESET
+#undef PAL_MODE_UNCONNECTED
+#undef PAL_MODE_INPUT
+#undef PAL_MODE_INPUT_PULLUP
+#undef PAL_MODE_INPUT_PULLDOWN
+#undef PAL_MODE_INPUT_ANALOG
+#undef PAL_MODE_OUTPUT_PUSHPULL
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+
+/**
+ * @name    STM32-specific I/O mode flags
+ * @{
+ */
+#define PAL_STM32_MODE_MASK             (3 << 0)
+#define PAL_STM32_MODE_INPUT            (0 << 0)
+#define PAL_STM32_MODE_OUTPUT           (1 << 0)
+#define PAL_STM32_MODE_ALTERNATE        (2 << 0)
+#define PAL_STM32_MODE_ANALOG           (3 << 0)
+
+#define PAL_STM32_OTYPE_MASK            (1 << 2)
+#define PAL_STM32_OTYPE_PUSHPULL        (0 << 2)
+#define PAL_STM32_OTYPE_OPENDRAIN       (1 << 2)
+
+#define PAL_STM32_OSPEED_MASK           (3 << 3)
+#define PAL_STM32_OSPEED_LOWEST         (0 << 3)
+#if defined(STM32F0XX) || defined(STM32F30X) || defined(STM32F37X)
+#define PAL_STM32_OSPEED_MID            (1 << 3)
+#else
+#define PAL_STM32_OSPEED_MID1           (1 << 3)
+#define PAL_STM32_OSPEED_MID2           (2 << 3)
+#endif
+#define PAL_STM32_OSPEED_HIGHEST        (3 << 3)
+
+#define PAL_STM32_PUDR_MASK             (3 << 5)
+#define PAL_STM32_PUDR_FLOATING         (0 << 5)
+#define PAL_STM32_PUDR_PULLUP           (1 << 5)
+#define PAL_STM32_PUDR_PULLDOWN         (2 << 5)
+
+#define PAL_STM32_ALTERNATE_MASK        (15 << 7)
+#define PAL_STM32_ALTERNATE(n)          ((n) << 7)
+
+/**
+ * @brief   Alternate function.
+ *
+ * @param[in] n         alternate function selector
+ */
+#define PAL_MODE_ALTERNATE(n)           (PAL_STM32_MODE_ALTERNATE |         \
+                                         PAL_STM32_ALTERNATE(n))
+/** @} */
+
+/**
+ * @name    Standard I/O mode flags
+ * @{
+ */
+/**
+ * @brief   This mode is implemented as input.
+ */
+#define PAL_MODE_RESET                  PAL_STM32_MODE_INPUT
+
+/**
+ * @brief   This mode is implemented as input with pull-up.
+ */
+#define PAL_MODE_UNCONNECTED            PAL_MODE_INPUT_PULLUP
+
+/**
+ * @brief   Regular input high-Z pad.
+ */
+#define PAL_MODE_INPUT                  PAL_STM32_MODE_INPUT
+
+/**
+ * @brief   Input pad with weak pull up resistor.
+ */
+#define PAL_MODE_INPUT_PULLUP           (PAL_STM32_MODE_INPUT |             \
+                                         PAL_STM32_PUDR_PULLUP)
+
+/**
+ * @brief   Input pad with weak pull down resistor.
+ */
+#define PAL_MODE_INPUT_PULLDOWN         (PAL_STM32_MODE_INPUT |             \
+                                         PAL_STM32_PUDR_PULLDOWN)
+
+/**
+ * @brief   Analog input mode.
+ */
+#define PAL_MODE_INPUT_ANALOG           PAL_STM32_MODE_ANALOG
+
+/**
+ * @brief   Push-pull output pad.
+ */
+#define PAL_MODE_OUTPUT_PUSHPULL        (PAL_STM32_MODE_OUTPUT |            \
+                                         PAL_STM32_OTYPE_PUSHPULL)
+
+/**
+ * @brief   Open-drain output pad.
+ */
+#define PAL_MODE_OUTPUT_OPENDRAIN       (PAL_STM32_MODE_OUTPUT |            \
+                                         PAL_STM32_OTYPE_OPENDRAIN)
+/** @} */
+
+/* Discarded definitions from the ST headers, the PAL driver uses its own
+   definitions in order to have an unified handling for all devices.
+   Unfortunately the ST headers have no uniform definitions for the same
+   objects across the various sub-families.*/
+#undef GPIOA
+#undef GPIOB
+#undef GPIOC
+#undef GPIOD
+#undef GPIOE
+#undef GPIOF
+#undef GPIOG
+#undef GPIOH
+#undef GPIOI
+
+/**
+ * @name    GPIO ports definitions
+ * @{
+ */
+#define GPIOA                           ((stm32_gpio_t *)GPIOA_BASE)
+#define GPIOB                           ((stm32_gpio_t *)GPIOB_BASE)
+#define GPIOC                           ((stm32_gpio_t *)GPIOC_BASE)
+#define GPIOD                           ((stm32_gpio_t *)GPIOD_BASE)
+#define GPIOE                           ((stm32_gpio_t *)GPIOE_BASE)
+#define GPIOF                           ((stm32_gpio_t *)GPIOF_BASE)
+#define GPIOG                           ((stm32_gpio_t *)GPIOG_BASE)
+#define GPIOH                           ((stm32_gpio_t *)GPIOH_BASE)
+#define GPIOI                           ((stm32_gpio_t *)GPIOI_BASE)
+/** @} */
+
+/*===========================================================================*/
+/* I/O Ports Types and constants.                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 GPIO registers block.
+ */
+typedef struct {
+
+  volatile uint32_t     MODER;
+  volatile uint32_t     OTYPER;
+  volatile uint32_t     OSPEEDR;
+  volatile uint32_t     PUPDR;
+  volatile uint32_t     IDR;
+  volatile uint32_t     ODR;
+  volatile union {
+    uint32_t            W;
+    struct {
+      uint16_t          set;
+      uint16_t          clear;
+    } H;
+  } BSRR;
+  volatile uint32_t     LCKR;
+  volatile uint32_t     AFRL;
+  volatile uint32_t     AFRH;
+  volatile uint32_t     BRR;
+} stm32_gpio_t;
+
+/**
+ * @brief   GPIO port setup info.
+ */
+typedef struct {
+  /** Initial value for MODER register.*/
+  uint32_t              moder;
+  /** Initial value for OTYPER register.*/
+  uint32_t              otyper;
+  /** Initial value for OSPEEDR register.*/
+  uint32_t              ospeedr;
+  /** Initial value for PUPDR register.*/
+  uint32_t              pupdr;
+  /** Initial value for ODR register.*/
+  uint32_t              odr;
+  /** Initial value for AFRL register.*/
+  uint32_t              afrl;
+  /** Initial value for AFRH register.*/
+  uint32_t              afrh;
+} stm32_gpio_setup_t;
+
+/**
+ * @brief   STM32 GPIO static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ *          system startup time in order to initialize the digital I/O
+ *          subsystem. This represents only the initial setup, specific pads
+ *          or whole ports can be reprogrammed at later time.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+  /** @brief Port A setup data.*/
+  stm32_gpio_setup_t    PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+  /** @brief Port B setup data.*/
+  stm32_gpio_setup_t    PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+  /** @brief Port C setup data.*/
+  stm32_gpio_setup_t    PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+  /** @brief Port D setup data.*/
+  stm32_gpio_setup_t    PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+  /** @brief Port E setup data.*/
+  stm32_gpio_setup_t    PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+  /** @brief Port F setup data.*/
+  stm32_gpio_setup_t    PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+  /** @brief Port G setup data.*/
+  stm32_gpio_setup_t    PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+  /** @brief Port H setup data.*/
+  stm32_gpio_setup_t    PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+  /** @brief Port I setup data.*/
+  stm32_gpio_setup_t    PIData;
+#endif
+} PALConfig;
+
+/**
+ * @brief   Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 16
+
+/**
+ * @brief   Whole port mask.
+ * @details This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
+
+/**
+ * @brief   Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief   Digital I/O modes.
+ */
+typedef uint32_t iomode_t;
+
+/**
+ * @brief   Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ *          any assumption about it, use the provided macros when populating
+ *          variables of this type.
+ */
+typedef stm32_gpio_t * ioportid_t;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers.                                                    */
+/* The low level driver wraps the definitions already present in the STM32   */
+/* firmware library.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   GPIO port A identifier.
+ */
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+#define IOPORT1         GPIOA
+#endif
+
+/**
+ * @brief   GPIO port B identifier.
+ */
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+#define IOPORT2         GPIOB
+#endif
+
+/**
+ * @brief   GPIO port C identifier.
+ */
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+#define IOPORT3         GPIOC
+#endif
+
+/**
+ * @brief   GPIO port D identifier.
+ */
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+#define IOPORT4         GPIOD
+#endif
+
+/**
+ * @brief   GPIO port E identifier.
+ */
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+#define IOPORT5         GPIOE
+#endif
+
+/**
+ * @brief   GPIO port F identifier.
+ */
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+#define IOPORT6         GPIOF
+#endif
+
+/**
+ * @brief   GPIO port G identifier.
+ */
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+#define IOPORT7         GPIOG
+#endif
+
+/**
+ * @brief   GPIO port H identifier.
+ */
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+#define IOPORT8         GPIOH
+#endif
+
+/**
+ * @brief   GPIO port I identifier.
+ */
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+#define IOPORT9         GPIOI
+#endif
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as      */
+/* functions, if so please put them in pal_lld.c.                            */
+/*===========================================================================*/
+
+/**
+ * @brief   GPIO ports subsystem initialization.
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief   Reads an I/O port.
+ * @details This function is implemented by reading the GPIO IDR register, the
+ *          implementation has no side effects.
+ * @note    This function is not meant to be invoked directly by the application
+ *          code.
+ *
+ * @param[in] port      port identifier
+ * @return              The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) ((port)->IDR)
+
+/**
+ * @brief   Reads the output latch.
+ * @details This function is implemented by reading the GPIO ODR register, the
+ *          implementation has no side effects.
+ * @note    This function is not meant to be invoked directly by the application
+ *          code.
+ *
+ * @param[in] port      port identifier
+ * @return              The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) ((port)->ODR)
+
+/**
+ * @brief   Writes on a I/O port.
+ * @details This function is implemented by writing the GPIO ODR register, the
+ *          implementation has no side effects.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
+
+/**
+ * @brief   Sets a bits mask on a I/O port.
+ * @details This function is implemented by writing the GPIO BSRR register, the
+ *          implementation has no side effects.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits))
+
+/**
+ * @brief   Clears a bits mask on a I/O port.
+ * @details This function is implemented by writing the GPIO BSRR register, the
+ *          implementation has no side effects.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits))
+
+/**
+ * @brief   Writes a group of bits.
+ * @details This function is implemented by writing the GPIO BSRR register, the
+ *          implementation has no side effects.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    the group bit offset within the port
+ * @param[in] bits      bits to be written. Values exceeding the group
+ *                      width are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits)                        \
+  ((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) |               \
+                     (((bits) & (mask)) << (offset)))
+
+/**
+ * @brief   Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ *          with the specified mode.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @param[in] mode      group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
+  _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief   Writes a logical state on an output pad.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @param[in] bit       logical value, the value must be @p PAL_LOW or
+ *                      @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
+
+extern const PALConfig pal_default_config;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _pal_lld_init(const PALConfig *config);
+  void _pal_lld_setgroupmode(ioportid_t port,
+                             ioportmask_t mask,
+                             iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* _PAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c
new file mode 100644
index 000000000..9a88bedf5
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c
@@ -0,0 +1,855 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+   aka barthess.
+ */
+
+/**
+ * @file    STM32/I2Cv1/i2c_lld.c
+ * @brief   STM32 I2C subsystem low level driver source.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define I2C1_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM,                        \
+                       STM32_I2C1_RX_DMA_CHN)
+
+#define I2C1_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM,                        \
+                       STM32_I2C1_TX_DMA_CHN)
+
+#define I2C2_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM,                        \
+                       STM32_I2C2_RX_DMA_CHN)
+
+#define I2C2_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM,                        \
+                       STM32_I2C2_TX_DMA_CHN)
+
+#define I2C3_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM,                        \
+                       STM32_I2C3_RX_DMA_CHN)
+
+#define I2C3_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM,                        \
+                       STM32_I2C3_TX_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+#define I2C_EV5_MASTER_MODE_SELECT                                          \
+  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB))
+
+#define I2C_EV6_MASTER_TRA_MODE_SELECTED                                    \
+  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) |          \
+              I2C_SR1_ADDR | I2C_SR1_TXE))
+
+#define I2C_EV6_MASTER_REC_MODE_SELECTED                                    \
+  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR))
+
+#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED                                   \
+  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) |          \
+              I2C_SR1_BTF | I2C_SR1_TXE))
+
+#define I2C_EV9_MASTER_ADD10                                                \
+  ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_ADD10))
+
+#define I2C_EV_MASK 0x00FFFFFF
+
+#define I2C_ERROR_MASK                                                      \
+  ((uint16_t)(I2C_SR1_BERR | I2C_SR1_ARLO | I2C_SR1_AF | I2C_SR1_OVR |      \
+              I2C_SR1_PECERR | I2C_SR1_TIMEOUT | I2C_SR1_SMBALERT))
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief I2C1 driver identifier.*/
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/** @brief I2C2 driver identifier.*/
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+/** @brief I2C3 driver identifier.*/
+#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__)
+I2CDriver I2CD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Aborts an I2C transaction.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_abort_operation(I2CDriver *i2cp) {
+  I2C_TypeDef *dp = i2cp->i2c;
+
+  /* Stops the I2C peripheral.*/
+  dp->CR1 = I2C_CR1_SWRST;
+  dp->CR1 = 0;
+  dp->CR2 = 0;
+  dp->SR1 = 0;
+
+  /* Stops the associated DMA streams.*/
+  dmaStreamDisable(i2cp->dmatx);
+  dmaStreamDisable(i2cp->dmarx);
+}
+
+/**
+ * @brief   Set clock speed.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_set_clock(I2CDriver *i2cp) {
+  I2C_TypeDef *dp = i2cp->i2c;
+  uint16_t regCCR, clock_div;
+  int32_t clock_speed = i2cp->config->clock_speed;
+  i2cdutycycle_t duty = i2cp->config->duty_cycle;
+
+  osalDbgCheck((i2cp != NULL) &&
+               (clock_speed > 0) &&
+               (clock_speed <= 4000000));
+
+  /* CR2 Configuration.*/
+  dp->CR2 &= (uint16_t)~I2C_CR2_FREQ;
+  dp->CR2 |= (uint16_t)I2C_CLK_FREQ;
+
+  /* CCR Configuration.*/
+  regCCR = 0;
+  clock_div = I2C_CCR_CCR;
+
+  if (clock_speed <= 100000) {
+    /* Configure clock_div in standard mode.*/
+    osalDbgAssert(duty == STD_DUTY_CYCLE, "invalid standard mode duty cycle");
+
+    /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/
+    osalDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0,
+                  "PCLK1 must be divisible without remainder");
+    clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2));
+
+    osalDbgAssert(clock_div >= 0x04,
+                  "clock divider less then 0x04 not allowed");
+    regCCR |= (clock_div & I2C_CCR_CCR);
+
+    /* Sets the Maximum Rise Time for standard mode.*/
+    dp->TRISE = I2C_CLK_FREQ + 1;
+  }
+  else if (clock_speed <= 400000) {
+    /* Configure clock_div in fast mode.*/
+    osalDbgAssert((duty == FAST_DUTY_CYCLE_2) ||
+                  (duty == FAST_DUTY_CYCLE_16_9),
+                  "invalid fast mode duty cycle");
+
+    if (duty == FAST_DUTY_CYCLE_2) {
+      /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/
+      osalDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0,
+                    "PCLK1 must be divided without remainder");
+      clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3));
+    }
+    else if (duty == FAST_DUTY_CYCLE_16_9) {
+      /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/
+      osalDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0,
+                    "PCLK1 must be divided without remainder");
+      clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25));
+      regCCR |= I2C_CCR_DUTY;
+    }
+
+    osalDbgAssert(clock_div >= 0x01,
+                  "clock divider less then 0x04 not allowed");
+    regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR));
+
+    /* Sets the Maximum Rise Time for fast mode.*/
+    dp->TRISE = (I2C_CLK_FREQ * 300 / 1000) + 1;
+  }
+
+  osalDbgAssert((clock_div <= I2C_CCR_CCR), "the selected clock is too low");
+
+  dp->CCR = regCCR;
+}
+
+/**
+ * @brief   Set operation mode of I2C hardware.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_set_opmode(I2CDriver *i2cp) {
+  I2C_TypeDef *dp = i2cp->i2c;
+  i2copmode_t opmode = i2cp->config->op_mode;
+  uint16_t regCR1;
+
+  regCR1 = dp->CR1;
+  switch (opmode) {
+  case OPMODE_I2C:
+    regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE);
+    break;
+  case OPMODE_SMBUS_DEVICE:
+    regCR1 |= I2C_CR1_SMBUS;
+    regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE);
+    break;
+  case OPMODE_SMBUS_HOST:
+    regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE);
+    break;
+  }
+  dp->CR1 = regCR1;
+}
+
+/**
+ * @brief   I2C shared ISR code.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
+  I2C_TypeDef *dp = i2cp->i2c;
+  uint32_t regSR2 = dp->SR2;
+  uint32_t event = dp->SR1;
+
+  /* Interrupts are disabled just before dmaStreamEnable() because there
+     is no need of interrupts until next transaction begin. All the work is
+     done by the DMA.*/
+  switch (I2C_EV_MASK & (event | (regSR2 << 16))) {
+  case I2C_EV5_MASTER_MODE_SELECT:
+    if ((i2cp->addr >> 8) > 0) { 
+      /* 10-bit address: 1 1 1 1 0 X X R/W */
+      dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr);
+    } else {
+      dp->DR = i2cp->addr;
+    }
+    break;
+  case I2C_EV9_MASTER_ADD10:
+    /* Set second addr byte (10-bit addressing)*/
+    dp->DR = (0xFF & (i2cp->addr >> 1));
+    break;
+  case I2C_EV6_MASTER_REC_MODE_SELECTED:
+    dp->CR2 &= ~I2C_CR2_ITEVTEN;
+    dmaStreamEnable(i2cp->dmarx);
+    dp->CR2 |= I2C_CR2_LAST;                 /* Needed in receiver mode. */
+    if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2)
+      dp->CR1 &= ~I2C_CR1_ACK;
+    break;
+  case I2C_EV6_MASTER_TRA_MODE_SELECTED:
+    dp->CR2 &= ~I2C_CR2_ITEVTEN;
+    dmaStreamEnable(i2cp->dmatx);
+    break;
+  case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
+    /* Catches BTF event after the end of transmission.*/
+    if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) {
+      /* Starts "read after write" operation, LSB = 1 -> receive.*/
+      i2cp->addr |= 0x01;
+      dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
+      return;
+    }
+    dp->CR2 &= ~I2C_CR2_ITEVTEN;
+    dp->CR1 |= I2C_CR1_STOP;
+    _i2c_wakeup_isr(i2cp);
+    break;
+  default:
+    break;
+  }
+  /* Clear ADDR flag. */
+  if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))
+    (void)dp->SR2;
+}
+
+/**
+ * @brief   DMA RX end IRQ handler.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
+  I2C_TypeDef *dp = i2cp->i2c;
+
+  /* DMA errors handling.*/
+#if defined(STM32_I2C_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_I2C_DMA_ERROR_HOOK(i2cp);
+  }
+#else
+  (void)flags;
+#endif
+
+  dmaStreamDisable(i2cp->dmarx);
+
+  dp->CR2 &= ~I2C_CR2_LAST;
+  dp->CR1 &= ~I2C_CR1_ACK;
+  dp->CR1 |= I2C_CR1_STOP;
+  _i2c_wakeup_isr(i2cp);
+}
+
+/**
+ * @brief    DMA TX end IRQ handler.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
+  I2C_TypeDef *dp = i2cp->i2c;
+
+  /* DMA errors handling.*/
+#if defined(STM32_I2C_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_I2C_DMA_ERROR_HOOK(i2cp);
+  }
+#else
+  (void)flags;
+#endif
+
+  dmaStreamDisable(i2cp->dmatx);
+  /* Enables interrupts to catch BTF event meaning transmission part complete.
+     Interrupt handler will decide to generate STOP or to begin receiving part
+     of R/W transaction itself.*/
+  dp->CR2 |= I2C_CR2_ITEVTEN;
+}
+
+/**
+ * @brief   I2C error handler.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in]  sr       content of the SR1 register to be decoded
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) {
+
+  /* Clears interrupt flags just to be safe.*/
+  dmaStreamDisable(i2cp->dmatx);
+  dmaStreamDisable(i2cp->dmarx);
+
+  i2cp->errors = I2C_NO_ERROR;
+
+  if (sr & I2C_SR1_BERR)                            /* Bus error.           */
+    i2cp->errors |= I2C_BUS_ERROR;
+
+  if (sr & I2C_SR1_ARLO)                            /* Arbitration lost.    */
+    i2cp->errors |= I2C_ARBITRATION_LOST;
+
+  if (sr & I2C_SR1_AF) {                            /* Acknowledge fail.    */
+    i2cp->i2c->CR2 &= ~I2C_CR2_ITEVTEN;
+    i2cp->i2c->CR1 |= I2C_CR1_STOP;                 /* Setting stop bit.    */
+    i2cp->errors |= I2C_ACK_FAILURE;
+  }
+
+  if (sr & I2C_SR1_OVR)                             /* Overrun.             */
+    i2cp->errors |= I2C_OVERRUN;
+
+  if (sr & I2C_SR1_TIMEOUT)                         /* SMBus Timeout.       */
+    i2cp->errors |= I2C_TIMEOUT;
+
+  if (sr & I2C_SR1_PECERR)                          /* PEC error.           */
+    i2cp->errors |= I2C_PEC_ERROR;
+
+  if (sr & I2C_SR1_SMBALERT)                        /* SMBus alert.         */
+    i2cp->errors |= I2C_SMB_ALERT;
+
+  /* If some error has been identified then sends wakes the waiting thread.*/
+  if (i2cp->errors != I2C_NO_ERROR)
+    _i2c_wakeup_error_isr(i2cp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C1 event interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_event_interrupt(&I2CD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   I2C1 error interrupt handler.
+ */
+OSAL_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) {
+  uint16_t sr = I2CD1.i2c->SR1;
+
+  OSAL_IRQ_PROLOGUE();
+
+  I2CD1.i2c->SR1 = ~(sr & I2C_ERROR_MASK);
+  i2c_lld_serve_error_interrupt(&I2CD1, sr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_I2C_USE_I2C1 */
+
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C2 event interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_event_interrupt(&I2CD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   I2C2 error interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) {
+  uint16_t sr = I2CD2.i2c->SR1;
+
+  OSAL_IRQ_PROLOGUE();
+
+  I2CD2.i2c->SR1 = ~(sr & I2C_ERROR_MASK);
+  i2c_lld_serve_error_interrupt(&I2CD2, sr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_I2C_USE_I2C2 */
+
+#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C3 event interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(I2C3_EV_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_event_interrupt(&I2CD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   I2C3 error interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(I2C3_ER_IRQHandler) {
+  uint16_t sr = I2CD3.i2c->SR1;
+
+  OSAL_IRQ_PROLOGUE();
+
+  I2CD3.i2c->SR1 = ~(sr & I2C_ERROR_MASK);
+  i2c_lld_serve_error_interrupt(&I2CD3, sr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_I2C_USE_I2C3 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level I2C driver initialization.
+ *
+ * @notapi
+ */
+void i2c_lld_init(void) {
+
+#if STM32_I2C_USE_I2C1
+  i2cObjectInit(&I2CD1);
+  I2CD1.thread = NULL;
+  I2CD1.i2c    = I2C1;
+  I2CD1.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
+  I2CD1.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
+#endif /* STM32_I2C_USE_I2C1 */
+
+#if STM32_I2C_USE_I2C2
+  i2cObjectInit(&I2CD2);
+  I2CD2.thread = NULL;
+  I2CD2.i2c    = I2C2;
+  I2CD2.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
+  I2CD2.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
+#endif /* STM32_I2C_USE_I2C2 */
+
+#if STM32_I2C_USE_I2C3
+  i2cObjectInit(&I2CD3);
+  I2CD3.thread = NULL;
+  I2CD3.i2c    = I2C3;
+  I2CD3.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM);
+  I2CD3.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM);
+#endif /* STM32_I2C_USE_I2C3 */
+}
+
+/**
+ * @brief   Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_start(I2CDriver *i2cp) {
+  I2C_TypeDef *dp = i2cp->i2c;
+
+  i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
+                    STM32_DMA_CR_MINC       | STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE       | STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DIR_M2P;
+  i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
+                    STM32_DMA_CR_MINC       | STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE       | STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DIR_P2M;
+
+  /* If in stopped state then enables the I2C and DMA clocks.*/
+  if (i2cp->state == I2C_STOP) {
+
+#if STM32_I2C_USE_I2C1
+    if (&I2CD1 == i2cp) {
+      bool b;
+
+      rccResetI2C1();
+      b = dmaStreamAllocate(i2cp->dmarx,
+                            STM32_I2C_I2C1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(i2cp->dmatx,
+                            STM32_I2C_I2C1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableI2C1(FALSE);
+      nvicEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
+      nvicEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
+
+      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
+                       STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
+      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
+                       STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
+    }
+#endif /* STM32_I2C_USE_I2C1 */
+
+#if STM32_I2C_USE_I2C2
+    if (&I2CD2 == i2cp) {
+      bool b;
+
+      rccResetI2C2();
+      b = dmaStreamAllocate(i2cp->dmarx,
+                            STM32_I2C_I2C2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(i2cp->dmatx,
+                            STM32_I2C_I2C2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableI2C2(FALSE);
+      nvicEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
+      nvicEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
+
+      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
+                       STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
+      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
+                       STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
+    }
+#endif /* STM32_I2C_USE_I2C2 */
+
+#if STM32_I2C_USE_I2C3
+    if (&I2CD3 == i2cp) {
+      bool b;
+
+      rccResetI2C3();
+      b = dmaStreamAllocate(i2cp->dmarx,
+                            STM32_I2C_I2C3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(i2cp->dmatx,
+                            STM32_I2C_I2C3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableI2C3(FALSE);
+      nvicEnableVector(I2C3_EV_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY);
+      nvicEnableVector(I2C3_ER_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY);
+
+      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) |
+                       STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
+      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C3_TX_DMA_CHANNEL) |
+                       STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY);
+    }
+#endif /* STM32_I2C_USE_I2C3 */
+  }
+
+  /* I2C registers pointed by the DMA.*/
+  dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR);
+  dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR);
+
+  /* Reset i2c peripheral.*/
+  dp->CR1 = I2C_CR1_SWRST;
+  dp->CR1 = 0;
+  dp->CR2 = I2C_CR2_ITERREN | I2C_CR2_DMAEN;
+
+  /* Setup I2C parameters.*/
+  i2c_lld_set_clock(i2cp);
+  i2c_lld_set_opmode(i2cp);
+
+  /* Ready to go.*/
+  dp->CR1 |= I2C_CR1_PE;
+}
+
+/**
+ * @brief   Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_stop(I2CDriver *i2cp) {
+
+  /* If not in stopped state then disables the I2C clock.*/
+  if (i2cp->state != I2C_STOP) {
+
+    /* I2C disable.*/
+    i2c_lld_abort_operation(i2cp);
+    dmaStreamRelease(i2cp->dmatx);
+    dmaStreamRelease(i2cp->dmarx);
+
+#if STM32_I2C_USE_I2C1
+    if (&I2CD1 == i2cp) {
+      nvicDisableVector(I2C1_EV_IRQn);
+      nvicDisableVector(I2C1_ER_IRQn);
+      rccDisableI2C1(FALSE);
+    }
+#endif
+
+#if STM32_I2C_USE_I2C2
+    if (&I2CD2 == i2cp) {
+      nvicDisableVector(I2C2_EV_IRQn);
+      nvicDisableVector(I2C2_ER_IRQn);
+      rccDisableI2C2(FALSE);
+    }
+#endif
+
+#if STM32_I2C_USE_I2C3
+    if (&I2CD3 == i2cp) {
+      nvicDisableVector(I2C3_EV_IRQn);
+      nvicDisableVector(I2C3_ER_IRQn);
+      rccDisableI2C3(FALSE);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Receives data via the I2C bus as master.
+ * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
+ *          hardware restriction.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] addr      slave device address
+ * @param[out] rxbuf    pointer to the receive buffer
+ * @param[in] rxbytes   number of bytes to be received
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if the function succeeded.
+ * @retval MSG_RESET    if one or more I2C errors occurred, the errors can
+ *                      be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT  if a timeout occurred before operation end. <b>After a
+ *                      timeout the driver must be stopped and restarted
+ *                      because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                     uint8_t *rxbuf, size_t rxbytes,
+                                     systime_t timeout) {
+  I2C_TypeDef *dp = i2cp->i2c;
+  systime_t start, end;
+
+#if defined(STM32F1XX_I2C)
+  osalDbgCheck(rxbytes > 1);
+#endif
+
+  /* Resetting error flags for this transfer.*/
+  i2cp->errors = I2C_NO_ERROR;
+
+  /* Initializes driver fields, LSB = 1 -> receive.*/
+  i2cp->addr = (addr << 1) | 0x01;
+
+  /* Releases the lock from high level driver.*/
+  osalSysUnlock();
+
+  /* RX DMA setup.*/
+  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
+  dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
+
+  /* Calculating the time window for the timeout on the busy bus condition.*/
+  start = osalOsGetSystemTimeX();
+  end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT);
+
+  /* Waits until BUSY flag is reset or, alternatively, for a timeout
+     condition.*/
+  while (true) {
+    osalSysLock();
+
+    /* If the bus is not busy then the operation can continue, note, the
+       loop is exited in the locked state.*/
+    if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP))
+      break;
+
+    /* If the system time went outside the allowed window then a timeout
+       condition is returned.*/
+    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+      return MSG_TIMEOUT;
+
+    osalSysUnlock();
+  }
+
+  /* Starts the operation.*/
+  dp->CR2 |= I2C_CR2_ITEVTEN;
+  dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
+
+  /* Waits for the operation completion or a timeout.*/
+  return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+}
+
+/**
+ * @brief   Transmits data via the I2C bus as master.
+ * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
+ *          This is hardware restriction.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] addr      slave device address
+ * @param[in] txbuf     pointer to the transmit buffer
+ * @param[in] txbytes   number of bytes to be transmitted
+ * @param[out] rxbuf    pointer to the receive buffer
+ * @param[in] rxbytes   number of bytes to be received
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if the function succeeded.
+ * @retval MSG_RESET    if one or more I2C errors occurred, the errors can
+ *                      be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT  if a timeout occurred before operation end. <b>After a
+ *                      timeout the driver must be stopped and restarted
+ *                      because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                      const uint8_t *txbuf, size_t txbytes,
+                                      uint8_t *rxbuf, size_t rxbytes,
+                                      systime_t timeout) {
+  I2C_TypeDef *dp = i2cp->i2c;
+  systime_t start, end;
+
+#if defined(STM32F1XX_I2C)
+  osalDbgCheck((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL)));
+#endif
+
+  /* Resetting error flags for this transfer.*/
+  i2cp->errors = I2C_NO_ERROR;
+
+  /* Initializes driver fields, LSB = 0 -> transmit.*/
+  i2cp->addr = (addr << 1);
+
+  /* Releases the lock from high level driver.*/
+  osalSysUnlock();
+
+  /* TX DMA setup.*/
+  dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode);
+  dmaStreamSetMemory0(i2cp->dmatx, txbuf);
+  dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
+
+  /* RX DMA setup.*/
+  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
+  dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
+
+  /* Calculating the time window for the timeout on the busy bus condition.*/
+  start = osalOsGetSystemTimeX();
+  end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT);
+
+  /* Waits until BUSY flag is reset or, alternatively, for a timeout
+     condition.*/
+  while (true) {
+    osalSysLock();
+
+    /* If the bus is not busy then the operation can continue, note, the
+       loop is exited in the locked state.*/
+    if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP))
+      break;
+
+    /* If the system time went outside the allowed window then a timeout
+       condition is returned.*/
+    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+      return MSG_TIMEOUT;
+
+    osalSysUnlock();
+  }
+
+  /* Starts the operation.*/
+  dp->CR2 |= I2C_CR2_ITEVTEN;
+  dp->CR1 |= I2C_CR1_START;
+
+  /* Waits for the operation completion or a timeout.*/
+  return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+}
+
+#endif /* HAL_USE_I2C */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.h b/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.h
new file mode 100644
index 000000000..c36b4bcfe
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.h
@@ -0,0 +1,512 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+   aka barthess.
+ */
+
+/**
+ * @file    STM32/I2Cv1/i2c_lld.h
+ * @brief   STM32 I2C subsystem low level driver header.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#ifndef _I2C_LLD_H_
+#define _I2C_LLD_H_
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Peripheral clock frequency.
+ */
+#define I2C_CLK_FREQ  ((STM32_PCLK1) / 1000000)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   I2C1 driver enable switch.
+ * @details If set to @p TRUE the support for I2C1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C1                  FALSE
+#endif
+
+/**
+ * @brief   I2C2 driver enable switch.
+ * @details If set to @p TRUE the support for I2C2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C2                  FALSE
+#endif
+
+/**
+ * @brief   I2C3 driver enable switch.
+ * @details If set to @p TRUE the support for I2C3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C3                  FALSE
+#endif
+
+/**
+ * @brief   I2C timeout on busy condition in milliseconds.
+ */
+#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
+#define STM32_I2C_BUSY_TIMEOUT              50
+#endif
+
+/**
+ * @brief   I2C1 interrupt priority level setting.
+ */
+#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C1_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   I2C2 interrupt priority level setting.
+ */
+#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C2_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   I2C3 interrupt priority level setting.
+ */
+#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C3_IRQ_PRIORITY         10
+#endif
+
+/**
+* @brief   I2C1 DMA priority (0..3|lowest..highest).
+* @note    The priority level is used for both the TX and RX DMA streams but
+*          because of the streams ordering the RX stream has always priority
+*          over the TX stream.
+*/
+#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C1_DMA_PRIORITY         1
+#endif
+
+/**
+* @brief   I2C2 DMA priority (0..3|lowest..highest).
+* @note    The priority level is used for both the TX and RX DMA streams but
+*          because of the streams ordering the RX stream has always priority
+*          over the TX stream.
+*/
+#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C2_DMA_PRIORITY         1
+#endif
+
+/**
+* @brief   I2C3 DMA priority (0..3|lowest..highest).
+* @note    The priority level is used for both the TX and RX DMA streams but
+*          because of the streams ordering the RX stream has always priority
+*          over the TX stream.
+*/
+#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C3_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   I2C DMA error hook.
+ * @note    The default action for DMA errors is a system halt because DMA
+ *          error can only happen because programming errors.
+ */
+#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      chSysHalt("DMA failure")
+#endif
+
+#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
+
+/**
+ * @brief   DMA stream used for I2C1 RX operations.
+ * @note    This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#endif
+
+/**
+ * @brief   DMA stream used for I2C1 TX operations.
+ * @note    This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+#endif
+
+/**
+ * @brief   DMA stream used for I2C2 RX operations.
+ * @note    This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#endif
+
+/**
+ * @brief   DMA stream used for I2C2 TX operations.
+ * @note    This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#endif
+
+/**
+ * @brief   DMA stream used for I2C3 RX operations.
+ * @note    This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#endif
+
+/**
+ * @brief   DMA stream used for I2C3 TX operations.
+ * @note    This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#endif
+
+#else /* !STM32_ADVANCED_DMA */
+
+/* Fixed streams for platforms using the old DMA peripheral, the values are
+   valid for both STM32F1xx and STM32L1xx.*/
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#endif /* !STM32_ADVANCED_DMA*/
+
+/* Flag for the whole STM32F1XX family. */
+#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
+    defined(STM32F10X_HD_VL) || defined(STM32F10X_LD)    || \
+    defined(STM32F10X_MD)    || defined(STM32F10X_HD)    || \
+    defined(STM32F10X_XL)    || defined(STM32F10X_CL)
+#define STM32F1XX_I2C
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/** @brief  error checks */
+#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
+#error "I2C1 not present in the selected device"
+#endif
+
+#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2
+#error "I2C2 not present in the selected device"
+#endif
+
+#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3
+#error "I2C3 not present in the selected device"
+#endif
+
+#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 &&                           \
+    !STM32_I2C_USE_I2C3
+#error "I2C driver activated but no I2C peripheral assigned"
+#endif
+
+#if STM32_I2C_USE_I2C1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C1"
+#endif
+
+#if STM32_I2C_USE_I2C2 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C2"
+#endif
+
+#if STM32_I2C_USE_I2C3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C3"
+#endif
+
+#if STM32_I2C_USE_I2C1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C1"
+#endif
+
+#if STM32_I2C_USE_I2C2 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C2"
+#endif
+
+#if STM32_I2C_USE_I2C3 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C3"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+   reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) ||        \
+                           !defined(STM32_I2C_I2C1_TX_DMA_STREAM))
+#error "I2C1 DMA streams not defined"
+#endif
+
+#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) ||        \
+                           !defined(STM32_I2C_I2C2_TX_DMA_STREAM))
+#error "I2C2 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_I2C_USE_I2C1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM,                    \
+                           STM32_I2C1_RX_DMA_MSK)
+#error "invalid DMA stream associated to I2C1 RX"
+#endif
+
+#if STM32_I2C_USE_I2C1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM,                    \
+                           STM32_I2C1_TX_DMA_MSK)
+#error "invalid DMA stream associated to I2C1 TX"
+#endif
+
+#if STM32_I2C_USE_I2C2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM,                    \
+                           STM32_I2C2_RX_DMA_MSK)
+#error "invalid DMA stream associated to I2C2 RX"
+#endif
+
+#if STM32_I2C_USE_I2C2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM,                    \
+                           STM32_I2C2_TX_DMA_MSK)
+#error "invalid DMA stream associated to I2C2 TX"
+#endif
+
+#if STM32_I2C_USE_I2C3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM,                    \
+                           STM32_I2C3_RX_DMA_MSK)
+#error "invalid DMA stream associated to I2C3 RX"
+#endif
+
+#if STM32_I2C_USE_I2C3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM,                    \
+                           STM32_I2C3_TX_DMA_MSK)
+#error "invalid DMA stream associated to I2C3 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/* Check clock range. */
+#if defined(STM32F4XX)
+#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 42)
+#error "I2C peripheral clock frequency out of range."
+#endif
+
+#elif defined(STM32L1XX_MD)
+#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 32)
+#error "I2C peripheral clock frequency out of range."
+#endif
+
+#elif defined(STM32F2XX)
+#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 30)
+#error "I2C peripheral clock frequency out of range."
+#endif
+
+#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
+      defined(STM32F10X_HD_VL)
+#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 24)
+#error "I2C peripheral clock frequency out of range."
+#endif
+
+#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) ||                     \
+      defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                     \
+      defined(STM32F10X_CL)
+#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 36)
+#error "I2C peripheral clock frequency out of range."
+#endif
+#else
+#error "unspecified, unsupported or invalid STM32 platform"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type representing I2C address.
+ */
+typedef uint16_t i2caddr_t;
+
+/**
+ * @brief   I2C Driver condition flags type.
+ */
+typedef uint32_t i2cflags_t;
+
+/**
+ * @brief   Supported modes for the I2C bus.
+ */
+typedef enum {
+  OPMODE_I2C = 1,
+  OPMODE_SMBUS_DEVICE = 2,
+  OPMODE_SMBUS_HOST = 3,
+} i2copmode_t;
+
+/**
+ * @brief   Supported duty cycle modes for the I2C bus.
+ */
+typedef enum {
+  STD_DUTY_CYCLE = 1,
+  FAST_DUTY_CYCLE_2 = 2,
+  FAST_DUTY_CYCLE_16_9 = 3,
+} i2cdutycycle_t;
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+  i2copmode_t     op_mode;       /**< @brief Specifies the I2C mode.        */
+  uint32_t        clock_speed;   /**< @brief Specifies the clock frequency.
+                                      @note Must be set to a value lower
+                                      than 400kHz.                          */
+  i2cdutycycle_t  duty_cycle;    /**< @brief Specifies the I2C fast mode
+                                      duty cycle.                           */
+} I2CConfig;
+
+/**
+ * @brief   Type of a structure representing an I2C driver.
+ */
+typedef struct I2CDriver I2CDriver;
+
+/**
+ * @brief Structure representing an I2C driver.
+ */
+struct I2CDriver {
+  /**
+   * @brief   Driver state.
+   */
+  i2cstate_t                state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const I2CConfig           *config;
+  /**
+   * @brief   Error flags.
+   */
+  i2cflags_t                errors;
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief   Mutex protecting the bus.
+   */
+  mutex_t                   mutex;
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#if defined(I2C_DRIVER_EXT_FIELDS)
+  I2C_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Thread waiting for I/O completion.
+   */
+  thread_reference_t        thread;
+  /**
+   * @brief     Current slave address without R/W bit.
+   */
+  i2caddr_t                 addr;
+  /**
+   * @brief RX DMA mode bit mask.
+   */
+  uint32_t                  rxdmamode;
+  /**
+   * @brief TX DMA mode bit mask.
+   */
+  uint32_t                  txdmamode;
+  /**
+   * @brief     Receive DMA channel.
+   */
+  const stm32_dma_stream_t  *dmarx;
+  /**
+   * @brief     Transmit DMA channel.
+   */
+  const stm32_dma_stream_t  *dmatx;
+  /**
+   * @brief     Pointer to the I2Cx registers block.
+   */
+  I2C_TypeDef               *i2c;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Get errors from I2C driver.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+#if STM32_I2C_USE_I2C1
+extern I2CDriver I2CD1;
+#endif
+
+#if STM32_I2C_USE_I2C2
+extern I2CDriver I2CD2;
+#endif
+
+#if STM32_I2C_USE_I2C3
+extern I2CDriver I2CD3;
+#endif
+#endif /* !defined(__DOXYGEN__) */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void i2c_lld_init(void);
+  void i2c_lld_start(I2CDriver *i2cp);
+  void i2c_lld_stop(I2CDriver *i2cp);
+  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                        const uint8_t *txbuf, size_t txbytes,
+                                        uint8_t *rxbuf, size_t rxbytes,
+                                        systime_t timeout);
+  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                       uint8_t *rxbuf, size_t rxbytes,
+                                       systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2C  */
+
+#endif /* _I2C_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c
new file mode 100644
index 000000000..249a6f54b
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c
@@ -0,0 +1,720 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/I2Cv2/i2c_lld.c
+ * @brief   STM32 I2C subsystem low level driver source.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define DMAMODE_COMMON                                                      \
+  (STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |                      \
+   STM32_DMA_CR_MINC       | STM32_DMA_CR_DMEIE      |                      \
+   STM32_DMA_CR_TEIE       | STM32_DMA_CR_TCIE)
+
+#define I2C1_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM,                        \
+                       STM32_I2C1_RX_DMA_CHN)
+
+#define I2C1_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM,                        \
+                       STM32_I2C1_TX_DMA_CHN)
+
+#define I2C2_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM,                        \
+                       STM32_I2C2_RX_DMA_CHN)
+
+#define I2C2_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM,                        \
+                       STM32_I2C2_TX_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+#define I2C_MASTER_TC                                                       \
+  ((uint32_t)(I2C_ISR_BUSY | I2C_ISR_TC))
+
+#define I2C_ERROR_MASK                                                      \
+  ((uint32_t)(I2C_ISR_BERR | I2C_ISR_ARLO | I2C_ISR_OVR | I2C_ISR_PECERR |  \
+              I2C_ISR_TIMEOUT | I2C_ISR_ALERT))
+
+#define I2C_INT_MASK                                                        \
+  ((uint32_t)(I2C_ISR_TCR | I2C_ISR_TC | I2C_ISR_STOPF | I2C_ISR_NACKF |    \
+              I2C_ISR_ADDR | I2C_ISR_RXNE | I2C_ISR_TXIS))
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief I2C1 driver identifier.*/
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/** @brief I2C2 driver identifier.*/
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Aborts an I2C transaction.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_abort_operation(I2CDriver *i2cp) {
+  I2C_TypeDef *dp = i2cp->i2c;
+
+  if (dp->CR1 & I2C_CR1_PE) {
+    /* Stops the I2C peripheral.*/
+    dp->CR1 &= ~I2C_CR1_PE;
+    while (dp->CR1 & I2C_CR1_PE)
+      dp->CR1 &= ~I2C_CR1_PE;
+    dp->CR1 |= I2C_CR1_PE;
+  }
+
+  /* Stops the associated DMA streams.*/
+  dmaStreamDisable(i2cp->dmatx);
+  dmaStreamDisable(i2cp->dmarx);
+}
+
+/**
+ * @brief   I2C shared ISR code.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] isr       content of the ISR register to be decoded
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t isr) {
+  I2C_TypeDef *dp = i2cp->i2c;
+
+  if ((isr & I2C_ISR_TC) && (i2cp->state == I2C_ACTIVE_TX)) {
+    size_t rxbytes;
+
+    /* Make sure no more 'Transfer complete' interrupts.*/
+    dp->CR1 &= ~I2C_CR1_TCIE;
+
+    rxbytes = dmaStreamGetTransactionSize(i2cp->dmarx);
+    if (rxbytes > 0) {
+      i2cp->state = I2C_ACTIVE_RX;
+
+      /* Enable RX DMA */
+      dmaStreamEnable(i2cp->dmarx);
+
+      dp->CR2 &= ~I2C_CR2_NBYTES;
+      dp->CR2 |= rxbytes << 16;
+
+      /* Starts the read operation.*/
+      dp->CR2 |= I2C_CR2_RD_WRN;
+      dp->CR2 |= I2C_CR2_START;
+    }
+    else {
+      /* Nothing to receive - send STOP immediately.*/
+      dp->CR2 |= I2C_CR2_STOP;
+    }
+  }
+  if (isr & I2C_ISR_NACKF) {
+    /* Starts a STOP sequence immediately on error.*/
+    dp->CR2 |= I2C_CR2_STOP;
+
+    i2cp->errors |= I2C_ACK_FAILURE;
+  }
+  if (isr & I2C_ISR_STOPF) {
+    /* Stops the associated DMA streams.*/
+    dmaStreamDisable(i2cp->dmatx);
+    dmaStreamDisable(i2cp->dmarx);
+
+    /* The wake up message depends on the presence of errors.*/
+    if (i2cp->errors)
+      _i2c_wakeup_error_isr(i2cp);
+    else
+      _i2c_wakeup_isr(i2cp);
+  }
+}
+
+/**
+ * @brief   DMA RX end IRQ handler.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
+  I2C_TypeDef *dp = i2cp->i2c;
+
+  /* DMA errors handling.*/
+#if defined(STM32_I2C_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_I2C_DMA_ERROR_HOOK(i2cp);
+  }
+#else
+  (void)flags;
+#endif
+
+  dmaStreamDisable(i2cp->dmarx);
+  dp->CR2 |= I2C_CR2_STOP;
+  _i2c_wakeup_isr(i2cp);
+}
+
+/**
+ * @brief    DMA TX end IRQ handler.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(STM32_I2C_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_I2C_DMA_ERROR_HOOK(i2cp);
+  }
+#else
+  (void)flags;
+#endif
+
+  dmaStreamDisable(i2cp->dmatx);
+}
+
+/**
+ * @brief   I2C error handler.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] isr       content of the ISR register to be decoded
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t isr) {
+
+  /* Clears interrupt flags just to be safe.*/
+  dmaStreamDisable(i2cp->dmatx);
+  dmaStreamDisable(i2cp->dmarx);
+
+  if (isr & I2C_ISR_BERR)
+    i2cp->errors |= I2C_BUS_ERROR;
+
+  if (isr & I2C_ISR_ARLO)
+    i2cp->errors |= I2C_ARBITRATION_LOST;
+
+  if (isr & I2C_ISR_OVR)
+    i2cp->errors |= I2C_OVERRUN;
+
+  if (isr & I2C_ISR_TIMEOUT)
+    i2cp->errors |= I2C_TIMEOUT;
+
+  /* If some error has been identified then sends wakes the waiting thread.*/
+  if (i2cp->errors != I2C_NO_ERROR)
+    _i2c_wakeup_error_isr(i2cp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+#if defined(STM32_I2C1_GLOBAL_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   I2C1 event interrupt handler.
+ *
+ * @notapi
+ */
+CH_IRQ_HANDLER(STM32_I2C1_GLOBAL_HANDLER) {
+  uint32_t isr = I2CD1.i2c->ISR;
+
+  CH_IRQ_PROLOGUE();
+
+  /* Clearing IRQ bits.*/
+  I2CD1.i2c->ICR = isr;
+
+  if (isr & I2C_ERROR_MASK)
+    i2c_lld_serve_error_interrupt(&I2CD1, isr);
+  else if (isr & I2C_INT_MASK)
+    i2c_lld_serve_interrupt(&I2CD1, isr);
+
+  CH_IRQ_EPILOGUE();
+}
+
+#elif defined(STM32_I2C1_EVENT_HANDLER) && defined(STM32_I2C1_ERROR_HANDLER)
+CH_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) {
+  uint32_t isr = I2CD1.i2c->ISR;
+
+  CH_IRQ_PROLOGUE();
+
+  /* Clearing IRQ bits.*/
+  I2CD1.i2c->ICR = isr & I2C_INT_MASK;
+
+  i2c_lld_serve_interrupt(&I2CD1, isr);
+
+  CH_IRQ_EPILOGUE();
+}
+
+CH_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) {
+  uint32_t isr = I2CD1.i2c->ISR;
+
+  CH_IRQ_PROLOGUE();
+
+  /* Clearing IRQ bits.*/
+  I2CD1.i2c->ICR = isr & I2C_ERROR_MASK;
+
+  i2c_lld_serve_error_interrupt(&I2CD1, isr);
+
+  CH_IRQ_EPILOGUE();
+}
+
+#else
+#error "I2C1 interrupt handlers not defined"
+#endif
+#endif /* STM32_I2C_USE_I2C1 */
+
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+#if defined(STM32_I2C2_GLOBAL_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   I2C2 event interrupt handler.
+ *
+ * @notapi
+ */
+CH_IRQ_HANDLER(STM32_I2C2_GLOBAL_HANDLER) {
+  uint32_t isr = I2CD2.i2c->ISR;
+
+  CH_IRQ_PROLOGUE();
+
+  /* Clearing IRQ bits.*/
+  I2CD2.i2c->ICR = isr;
+
+  if (isr & I2C_ERROR_MASK)
+    i2c_lld_serve_error_interrupt(&I2CD2, isr);
+  else if (isr & I2C_INT_MASK)
+    i2c_lld_serve_interrupt(&I2CD2, isr);
+
+  CH_IRQ_EPILOGUE();
+}
+
+#elif defined(STM32_I2C2_EVENT_HANDLER) && defined(STM32_I2C2_ERROR_HANDLER)
+CH_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) {
+  uint32_t isr = I2CD2.i2c->ISR;
+
+  CH_IRQ_PROLOGUE();
+
+  /* Clearing IRQ bits.*/
+  I2CD2.i2c->ICR = isr & I2C_INT_MASK;
+
+  i2c_lld_serve_interrupt(&I2CD2, isr);
+
+  CH_IRQ_EPILOGUE();
+}
+
+CH_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) {
+  uint32_t isr = I2CD2.i2c->ISR;
+
+  CH_IRQ_PROLOGUE();
+
+  /* Clearing IRQ bits.*/
+  I2CD2.i2c->ICR = isr & I2C_ERROR_MASK;
+
+  i2c_lld_serve_error_interrupt(&I2CD2, isr);
+
+  CH_IRQ_EPILOGUE();
+}
+
+#else
+#error "I2C2 interrupt handlers not defined"
+#endif
+#endif /* STM32_I2C_USE_I2C2 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level I2C driver initialization.
+ *
+ * @notapi
+ */
+void i2c_lld_init(void) {
+
+#if STM32_I2C_USE_I2C1
+  i2cObjectInit(&I2CD1);
+  I2CD1.thread = NULL;
+  I2CD1.i2c    = I2C1;
+  I2CD1.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
+  I2CD1.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
+#endif /* STM32_I2C_USE_I2C1 */
+
+#if STM32_I2C_USE_I2C2
+  i2cObjectInit(&I2CD2);
+  I2CD2.thread = NULL;
+  I2CD2.i2c    = I2C2;
+  I2CD2.dmarx  = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
+  I2CD2.dmatx  = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
+#endif /* STM32_I2C_USE_I2C2 */
+}
+
+/**
+ * @brief   Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_start(I2CDriver *i2cp) {
+  I2C_TypeDef *dp = i2cp->i2c;
+
+  i2cp->txdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_M2P;
+  i2cp->rxdmamode = DMAMODE_COMMON | STM32_DMA_CR_DIR_P2M;
+
+  /* Make sure I2C peripheral is disabled */
+  dp->CR1 &= ~I2C_CR1_PE;
+
+  /* If in stopped state then enables the I2C and DMA clocks.*/
+  if (i2cp->state == I2C_STOP) {
+
+#if STM32_I2C_USE_I2C1
+    if (&I2CD1 == i2cp) {
+      bool b;
+
+      rccResetI2C1();
+      b = dmaStreamAllocate(i2cp->dmarx,
+                            STM32_I2C_I2C1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(i2cp->dmatx,
+                            STM32_I2C_I2C1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableI2C1(FALSE);
+
+#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+      nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER,
+                       CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
+#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER)
+      nvicEnableVector(STM32_I2C1_EVENT_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY);
+      nvicEnableVector(STM32_I2C1_ERROR_NUMBER, STM32_I2C_I2C1_IRQ_PRIORITY);
+#else
+#error "I2C1 interrupt numbers not defined"
+#endif
+
+      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
+                         STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
+      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
+                         STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
+    }
+#endif /* STM32_I2C_USE_I2C1 */
+
+#if STM32_I2C_USE_I2C2
+    if (&I2CD2 == i2cp) {
+      bool b;
+
+      rccResetI2C2();
+      b = dmaStreamAllocate(i2cp->dmarx,
+                            STM32_I2C_I2C2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(i2cp->dmatx,
+                            STM32_I2C_I2C2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
+                            (void *)i2cp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableI2C2(FALSE);
+
+#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+      nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER,
+                       CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
+#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER)
+      nvicEnableVector(STM32_I2C2_EVENT_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY);
+      nvicEnableVector(STM32_I2C2_ERROR_NUMBER, STM32_I2C_I2C2_IRQ_PRIORITY);
+#else
+#error "I2C2 interrupt numbers not defined"
+#endif
+
+      i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
+                         STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
+      i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
+                         STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
+    }
+#endif /* STM32_I2C_USE_I2C2 */
+  }
+
+  /* I2C registers pointed by the DMA.*/
+  dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR);
+  dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR);
+
+  /* Reset i2c peripheral, the TCIE bit will be handled separately.*/
+  dp->CR1 = i2cp->config->cr1 | I2C_CR1_ERRIE | I2C_CR1_STOPIE |
+            I2C_CR1_NACKIE | I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN;
+
+  /* Set slave address field (master mode) */
+  dp->CR2 = (i2cp->config->cr2 & ~I2C_CR2_SADD);
+
+  /* Setup I2C parameters.*/
+  dp->TIMINGR = i2cp->config->timingr;
+
+  /* Ready to go.*/
+  dp->CR1 |= I2C_CR1_PE;
+}
+
+/**
+ * @brief   Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_stop(I2CDriver *i2cp) {
+
+  /* If not in stopped state then disables the I2C clock.*/
+  if (i2cp->state != I2C_STOP) {
+
+    /* I2C disable.*/
+    i2c_lld_abort_operation(i2cp);
+    dmaStreamRelease(i2cp->dmatx);
+    dmaStreamRelease(i2cp->dmarx);
+
+#if STM32_I2C_USE_I2C1
+    if (&I2CD1 == i2cp) {
+#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+      nvicDisableVector(STM32_I2C1_GLOBAL_NUMBER);
+#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER)
+      nvicDisableVector(STM32_I2C1_EVENT_NUMBER);
+      nvicDisableVector(STM32_I2C1_ERROR_NUMBER);
+#else
+#error "I2C1 interrupt numbers not defined"
+#endif
+
+      rccDisableI2C1(FALSE);
+    }
+#endif
+
+#if STM32_I2C_USE_I2C2
+    if (&I2CD2 == i2cp) {
+#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__)
+      nvicDisableVector(STM32_I2C2_GLOBAL_NUMBER);
+#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER)
+      nvicDisableVector(STM32_I2C2_EVENT_NUMBER);
+      nvicDisableVector(STM32_I2C2_ERROR_NUMBER);
+#else
+#error "I2C2 interrupt numbers not defined"
+#endif
+
+      rccDisableI2C2(FALSE);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Receives data via the I2C bus as master.
+ * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
+ *          hardware restriction.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] addr      slave device address
+ * @param[out] rxbuf    pointer to the receive buffer
+ * @param[in] rxbytes   number of bytes to be received
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if the function succeeded.
+ * @retval MSG_RESET    if one or more I2C errors occurred, the errors can
+ *                      be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT  if a timeout occurred before operation end. <b>After a
+ *                      timeout the driver must be stopped and restarted
+ *                      because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                     uint8_t *rxbuf, size_t rxbytes,
+                                     systime_t timeout) {
+  I2C_TypeDef *dp = i2cp->i2c;
+  uint32_t addr_cr2 = addr & I2C_CR2_SADD;
+  systime_t start, end;
+
+  /* Resetting error flags for this transfer.*/
+  i2cp->errors = I2C_NO_ERROR;
+
+  /* Releases the lock from high level driver.*/
+  osalSysUnlock();
+
+  /* RX DMA setup.*/
+  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
+  dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
+
+  /* Calculating the time window for the timeout on the busy bus condition.*/
+  start = osalOsGetSystemTimeX();
+  end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT);
+
+  /* Waits until BUSY flag is reset or, alternatively, for a timeout
+     condition.*/
+  while (true) {
+    osalSysLock();
+
+    /* If the bus is not busy then the operation can continue, note, the
+       loop is exited in the locked state.*/
+    if ((dp->ISR & I2C_ISR_BUSY) == 0)
+      break;
+
+    /* If the system time went outside the allowed window then a timeout
+       condition is returned.*/
+    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+      return MSG_TIMEOUT;
+
+    osalSysUnlock();
+  }
+
+  /* Adjust slave address (master mode) for 7-bit address mode */
+  if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
+    addr_cr2 = (addr_cr2 & 0x7f) << 1;
+
+  /* Set slave address field (master mode) */
+  dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES);
+  dp->CR2 |= (rxbytes << 16) | addr_cr2;
+
+  /* Enable RX DMA */
+  dmaStreamEnable(i2cp->dmarx);
+
+  /* Starts the operation.*/
+  dp->CR2 |= I2C_CR2_RD_WRN;
+  dp->CR2 |= I2C_CR2_START;
+
+  /* Waits for the operation completion or a timeout.*/
+  return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+}
+
+/**
+ * @brief   Transmits data via the I2C bus as master.
+ * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
+ *          This is hardware restriction.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] addr      slave device address
+ * @param[in] txbuf     pointer to the transmit buffer
+ * @param[in] txbytes   number of bytes to be transmitted
+ * @param[out] rxbuf    pointer to the receive buffer
+ * @param[in] rxbytes   number of bytes to be received
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if the function succeeded.
+ * @retval MSG_RESET    if one or more I2C errors occurred, the errors can
+ *                      be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT  if a timeout occurred before operation end. <b>After a
+ *                      timeout the driver must be stopped and restarted
+ *                      because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                      const uint8_t *txbuf, size_t txbytes,
+                                      uint8_t *rxbuf, size_t rxbytes,
+                                      systime_t timeout) {
+  I2C_TypeDef *dp = i2cp->i2c;
+  uint32_t addr_cr2 = addr & I2C_CR2_SADD;
+  systime_t start, end;
+
+  /* Resetting error flags for this transfer.*/
+  i2cp->errors = I2C_NO_ERROR;
+
+  /* Releases the lock from high level driver.*/
+  osalSysUnlock();
+
+  /* TX DMA setup.*/
+  dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode);
+  dmaStreamSetMemory0(i2cp->dmatx, txbuf);
+  dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
+
+  /* RX DMA setup.*/
+  dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode);
+  dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
+
+  /* Calculating the time window for the timeout on the busy bus condition.*/
+  start = osalOsGetSystemTimeX();
+  end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT);
+
+  /* Waits until BUSY flag is reset or, alternatively, for a timeout
+     condition.*/
+  while (true) {
+    osalSysLock();
+
+    /* If the bus is not busy then the operation can continue, note, the
+       loop is exited in the locked state.*/
+    if ((dp->ISR & I2C_ISR_BUSY) == 0)
+      break;
+
+    /* If the system time went outside the allowed window then a timeout
+       condition is returned.*/
+    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+      return MSG_TIMEOUT;
+
+    osalSysUnlock();
+  }
+
+  /* Adjust slave address (master mode) for 7-bit address mode */
+  if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
+    addr_cr2 = (addr_cr2 & 0x7f) << 1;
+
+  /* Set slave address field (master mode) */
+  dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES);
+  dp->CR2 |= (txbytes << 16) | addr_cr2;
+
+  /* Enable TX DMA */
+  dmaStreamEnable(i2cp->dmatx);
+
+  /* Transmission complete interrupt enabled.*/
+  dp->CR1 |= I2C_CR1_TCIE;
+
+  /* Starts the operation as the very last thing.*/
+  dp->CR2 &= ~I2C_CR2_RD_WRN;
+  dp->CR2 |= I2C_CR2_START;
+
+  /* Waits for the operation completion or a timeout.*/
+  return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+}
+
+#endif /* HAL_USE_I2C */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.h b/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.h
new file mode 100644
index 000000000..070b2edad
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.h
@@ -0,0 +1,357 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+   aka barthess.
+ */
+
+/**
+ * @file    STM32/I2Cv2/i2c_lld.h
+ * @brief   STM32 I2C subsystem low level driver header.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#ifndef _I2C_LLD_H_
+#define _I2C_LLD_H_
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    TIMINGR register definitions
+ * @{
+ */
+#define STM32_TIMINGR_PRESC_MASK        (15U << 28)
+#define STM32_TIMINGR_PRESC(n)          ((n) << 28)
+#define STM32_TIMINGR_SCLDEL_MASK       (15U << 20)
+#define STM32_TIMINGR_SCLDEL(n)         ((n) << 20)
+#define STM32_TIMINGR_SDADEL_MASK       (15U << 16)
+#define STM32_TIMINGR_SDADEL(n)         ((n) << 16)
+#define STM32_TIMINGR_SCLH_MASK         (255U << 8)
+#define STM32_TIMINGR_SCLH(n)           ((n) << 8)
+#define STM32_TIMINGR_SCLL_MASK         (255U << 0)
+#define STM32_TIMINGR_SCLL(n)           ((n) << 0)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   I2C1 driver enable switch.
+ * @details If set to @p TRUE the support for I2C1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C1                  FALSE
+#endif
+
+/**
+ * @brief   I2C2 driver enable switch.
+ * @details If set to @p TRUE the support for I2C2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C2                  FALSE
+#endif
+
+/**
+ * @brief   I2C timeout on busy condition in milliseconds.
+ */
+#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
+#define STM32_I2C_BUSY_TIMEOUT              50
+#endif
+
+/**
+ * @brief   I2C1 interrupt priority level setting.
+ */
+#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C1_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   I2C2 interrupt priority level setting.
+ */
+#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C2_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   I2C1 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C1_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   I2C2 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C2_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   I2C DMA error hook.
+ * @note    The default action for DMA errors is a system halt because DMA
+ *          error can only happen because programming errors.
+ */
+#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/** @brief  error checks */
+#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
+#error "I2C1 not present in the selected device"
+#endif
+
+#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2
+#error "I2C2 not present in the selected device"
+#endif
+
+#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2
+#error "I2C driver activated but no I2C peripheral assigned"
+#endif
+
+#if STM32_I2C_USE_I2C1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C1"
+#endif
+
+#if STM32_I2C_USE_I2C2 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C2"
+#endif
+
+#if STM32_I2C_USE_I2C1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C1"
+#endif
+
+#if STM32_I2C_USE_I2C2 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to I2C2"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+   reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) ||        \
+                           !defined(STM32_I2C_I2C1_TX_DMA_STREAM))
+#error "I2C1 DMA streams not defined"
+#endif
+
+#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) ||        \
+                           !defined(STM32_I2C_I2C2_TX_DMA_STREAM))
+#error "I2C2 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_I2C_USE_I2C1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM,                    \
+                           STM32_I2C1_RX_DMA_MSK)
+#error "invalid DMA stream associated to I2C1 RX"
+#endif
+
+#if STM32_I2C_USE_I2C1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM,                    \
+                           STM32_I2C1_TX_DMA_MSK)
+#error "invalid DMA stream associated to I2C1 TX"
+#endif
+
+#if STM32_I2C_USE_I2C2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM,                    \
+                           STM32_I2C2_RX_DMA_MSK)
+#error "invalid DMA stream associated to I2C2 RX"
+#endif
+
+#if STM32_I2C_USE_I2C2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM,                    \
+                           STM32_I2C2_TX_DMA_MSK)
+#error "invalid DMA stream associated to I2C2 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/* Check clock range. */
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type representing I2C address.
+ */
+typedef uint16_t i2caddr_t;
+
+/**
+ * @brief   I2C Driver condition flags type.
+ */
+typedef uint32_t i2cflags_t;
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief   TIMINGR register initialization.
+   * @note    Refer to the STM32 reference manual, the values are affected
+   *          by the system clock settings in mcuconf.h.
+   */
+  uint32_t        timingr;
+  /**
+   * @brief   CR1 register initialization.
+   * @note    Leave to zero unless you know what you are doing.
+   */
+  uint32_t        cr1;
+  /**
+   * @brief   CR2 register initialization.
+   * @note    Only the ADD10 bit can eventually be specified here.
+   */
+  uint32_t        cr2;
+} I2CConfig;
+
+/**
+ * @brief   Type of a structure representing an I2C driver.
+ */
+typedef struct I2CDriver I2CDriver;
+
+/**
+ * @brief Structure representing an I2C driver.
+ */
+struct I2CDriver{
+  /**
+   * @brief   Driver state.
+   */
+  i2cstate_t                state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const I2CConfig           *config;
+  /**
+   * @brief   Error flags.
+   */
+  i2cflags_t                errors;
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  mutex_t                   mutex;
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#if defined(I2C_DRIVER_EXT_FIELDS)
+  I2C_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Thread waiting for I/O completion.
+   */
+  thread_reference_t        thread;
+  /**
+   * @brief     Current slave address without R/W bit.
+   */
+  i2caddr_t                 addr;
+  /**
+   * @brief RX DMA mode bit mask.
+   */
+  uint32_t                  rxdmamode;
+  /**
+   * @brief TX DMA mode bit mask.
+   */
+  uint32_t                  txdmamode;
+  /**
+   * @brief     Receive DMA channel.
+   */
+  const stm32_dma_stream_t  *dmarx;
+  /**
+   * @brief     Transmit DMA channel.
+   */
+  const stm32_dma_stream_t  *dmatx;
+  /**
+   * @brief     Pointer to the I2Cx registers block.
+   */
+  I2C_TypeDef               *i2c;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Get errors from I2C driver.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+#if STM32_I2C_USE_I2C1
+extern I2CDriver I2CD1;
+#endif
+
+#if STM32_I2C_USE_I2C2
+extern I2CDriver I2CD2;
+#endif
+
+#endif /* !defined(__DOXYGEN__) */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void i2c_lld_init(void);
+  void i2c_lld_start(I2CDriver *i2cp);
+  void i2c_lld_stop(I2CDriver *i2cp);
+  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                        const uint8_t *txbuf, size_t txbytes,
+                                        uint8_t *rxbuf, size_t rxbytes,
+                                        systime_t timeout);
+  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                       uint8_t *rxbuf, size_t rxbytes,
+                                       systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2C  */
+
+#endif /* _I2C_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/OTGv1/stm32_otg.h b/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h
index f81ce5412..f81ce5412 100644
--- a/os/hal/platforms/STM32/OTGv1/stm32_otg.h
+++ b/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h
diff --git a/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c b/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c
new file mode 100644
index 000000000..83997cc18
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c
@@ -0,0 +1,1334 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/OTGv1/usb_lld.c
+ * @brief   STM32 USB subsystem low level driver source.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define TRDT_VALUE              5
+
+#define EP0_MAX_INSIZE          64
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief OTG_FS driver identifier.*/
+#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
+USBDriver USBD1;
+#endif
+
+/** @brief OTG_HS driver identifier.*/
+#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
+USBDriver USBD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   EP0 state.
+ * @note    It is an union because IN and OUT endpoints are never used at the
+ *          same time for EP0.
+ */
+static union {
+  /**
+   * @brief   IN EP0 state.
+   */
+  USBInEndpointState in;
+  /**
+   * @brief   OUT EP0 state.
+   */
+  USBOutEndpointState out;
+} ep0_state;
+
+/**
+ * @brief   Buffer for the EP0 setup packets.
+ */
+static uint8_t ep0setup_buffer[8];
+
+/**
+ * @brief   EP0 initialization structure.
+ */
+static const USBEndpointConfig ep0config = {
+  USB_EP_MODE_TYPE_CTRL,
+  _usb_ep0setup,
+  _usb_ep0in,
+  _usb_ep0out,
+  0x40,
+  0x40,
+  &ep0_state.in,
+  &ep0_state.out,
+  1,
+  ep0setup_buffer
+};
+
+#if STM32_USB_USE_OTG1
+static const stm32_otg_params_t fsparams = {
+  STM32_USB_OTG1_RX_FIFO_SIZE / 4,
+  STM32_OTG1_FIFO_MEM_SIZE,
+  STM32_OTG1_ENDOPOINTS_NUMBER
+};
+#endif
+
+#if STM32_USB_USE_OTG2
+static const stm32_otg_params_t hsparams = {
+  STM32_USB_OTG2_RX_FIFO_SIZE / 4,
+  STM32_OTG2_FIFO_MEM_SIZE,
+  STM32_OTG2_ENDOPOINTS_NUMBER
+};
+#endif
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+static void otg_core_reset(USBDriver *usbp) {
+  stm32_otg_t *otgp = usbp->otg;
+
+  osalSysPolledDelayX(32);
+
+  /* Core reset and delay of at least 3 PHY cycles.*/
+  otgp->GRSTCTL = GRSTCTL_CSRST;
+  while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
+    ;
+
+  osalSysPolledDelayX(12);
+
+  /* Wait AHB idle condition.*/
+  while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)
+    ;
+}
+
+static void otg_disable_ep(USBDriver *usbp) {
+  stm32_otg_t *otgp = usbp->otg;
+  unsigned i;
+
+  for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
+    /* Disable only if enabled because this sentence in the manual:
+       "The application must set this bit only if Endpoint Enable is
+        already set for this endpoint".*/
+    if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0) {
+      otgp->ie[i].DIEPCTL = DIEPCTL_EPDIS;
+      /* Wait for endpoint disable.*/
+      while (!(otgp->ie[i].DIEPINT & DIEPINT_EPDISD))
+        ;
+    }
+    else
+      otgp->ie[i].DIEPCTL = 0;
+    otgp->ie[i].DIEPTSIZ = 0;
+    otgp->ie[i].DIEPINT = 0xFFFFFFFF;
+    /* Disable only if enabled because this sentence in the manual:
+       "The application must set this bit only if Endpoint Enable is
+        already set for this endpoint".
+       Note that the attempt to disable the OUT EP0 is ignored by the
+       hardware but the code is simpler this way.*/
+    if ((otgp->oe[i].DOEPCTL & DOEPCTL_EPENA) != 0) {
+      otgp->oe[i].DOEPCTL = DOEPCTL_EPDIS;
+      /* Wait for endpoint disable.*/
+      while (!(otgp->oe[i].DOEPINT & DOEPINT_OTEPDIS))
+        ;
+    }
+    else
+      otgp->oe[i].DOEPCTL = 0;
+    otgp->oe[i].DOEPTSIZ = 0;
+    otgp->oe[i].DOEPINT = 0xFFFFFFFF;
+  }
+  otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
+}
+
+static void otg_rxfifo_flush(USBDriver *usbp) {
+  stm32_otg_t *otgp = usbp->otg;
+
+  otgp->GRSTCTL = GRSTCTL_RXFFLSH;
+  while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0)
+    ;
+  /* Wait for 3 PHY Clocks.*/
+  osalSysPolledDelayX(12);
+}
+
+static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) {
+  stm32_otg_t *otgp = usbp->otg;
+
+  otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH;
+  while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0)
+    ;
+  /* Wait for 3 PHY Clocks.*/
+  osalSysPolledDelayX(12);
+}
+
+/**
+ * @brief   Resets the FIFO RAM memory allocator.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+static void otg_ram_reset(USBDriver *usbp) {
+
+  usbp->pmnext = usbp->otgparams->rx_fifo_size;
+}
+
+/**
+ * @brief   Allocates a block from the FIFO RAM memory.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] size      size of the packet buffer to allocate in words
+ *
+ * @notapi
+ */
+static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) {
+  uint32_t next;
+
+  next = usbp->pmnext;
+  usbp->pmnext += size;
+  osalDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size,
+                "OTG FIFO memory overflow");
+  return next;
+}
+
+/**
+ * @brief   Pushes a series of words into a FIFO.
+ *
+ * @param[in] fifop     pointer to the FIFO register
+ * @param[in] buf       pointer to the words buffer, not necessarily word
+ *                      aligned
+ * @param[in] n         number of words to push
+ *
+ * @return              A pointer after the last word pushed.
+ *
+ * @notapi
+ */
+static uint8_t *otg_do_push(volatile uint32_t *fifop, uint8_t *buf, size_t n) {
+
+  while (n > 0) {
+    /* Note, this line relies on the Cortex-M3/M4 ability to perform
+       unaligned word accesses and on the LSB-first memory organization.*/
+    *fifop = *((PACKED_VAR uint32_t *)buf);
+    buf += 4;
+    n--;
+  }
+  return buf;
+}
+
+/**
+ * @brief   Writes to a TX FIFO.
+ *
+ * @param[in] fifop     pointer to the FIFO register
+ * @param[in] buf       buffer where to copy the endpoint data
+ * @param[in] n         maximum number of bytes to copy
+ *
+ * @notapi
+ */
+static void otg_fifo_write_from_buffer(volatile uint32_t *fifop,
+                                       const uint8_t *buf,
+                                       size_t n) {
+
+  otg_do_push(fifop, (uint8_t *)buf, (n + 3) / 4);
+}
+
+/**
+ * @brief   Writes to a TX FIFO fetching data from a queue.
+ *
+ * @param[in] fifop     pointer to the FIFO register
+ * @param[in] oqp       pointer to an @p output_queue_t object
+ * @param[in] n         maximum number of bytes to copy
+ *
+ * @notapi
+ */
+static void otg_fifo_write_from_queue(volatile uint32_t *fifop,
+                                      output_queue_t *oqp,
+                                      size_t n) {
+  size_t ntogo;
+
+  ntogo = n;
+  while (ntogo > 0) {
+    uint32_t w, i;
+    size_t nw = ntogo / 4;
+
+    if (nw > 0) {
+      size_t streak;
+      uint32_t nw2end = (oqp->q_top - oqp->q_rdptr) / 4;
+
+      ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4;
+      oqp->q_rdptr = otg_do_push(fifop, oqp->q_rdptr, streak);
+      if (oqp->q_rdptr >= oqp->q_top) {
+        oqp->q_rdptr = oqp->q_buffer;
+        continue;
+      }
+    }
+
+    /* If this condition is not satisfied then there is a word lying across
+       queue circular buffer boundary or there are some remaining bytes.*/
+    if (ntogo <= 0)
+      break;
+
+    /* One byte at time.*/
+    w = 0;
+    i = 0;
+    while ((ntogo > 0) && (i < 4)) {
+      w |= (uint32_t)*oqp->q_rdptr++ << (i * 8);
+      if (oqp->q_rdptr >= oqp->q_top)
+        oqp->q_rdptr = oqp->q_buffer;
+      ntogo--;
+      i++;
+    }
+    *fifop = w;
+  }
+
+  /* Updating queue.*/
+  osalSysLock();
+  oqp->q_counter += n;
+  osalThreadDequeueAllI(&oqp->q_waiting, Q_OK);
+  osalOsRescheduleS();
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Pops a series of words from a FIFO.
+ *
+ * @param[in] fifop     pointer to the FIFO register
+ * @param[in] buf       pointer to the words buffer, not necessarily word
+ *                      aligned
+ * @param[in] n         number of words to push
+ *
+ * @return              A pointer after the last word pushed.
+ *
+ * @notapi
+ */
+static uint8_t *otg_do_pop(volatile uint32_t *fifop, uint8_t *buf, size_t n) {
+
+  while (n > 0) {
+    uint32_t w = *fifop;
+    /* Note, this line relies on the Cortex-M3/M4 ability to perform
+       unaligned word accesses and on the LSB-first memory organization.*/
+    *((PACKED_VAR uint32_t *)buf) = w;
+    buf += 4;
+    n--;
+  }
+  return buf;
+}
+
+/**
+ * @brief   Reads a packet from the RXFIFO.
+ *
+ * @param[in] fifop     pointer to the FIFO register
+ * @param[out] buf      buffer where to copy the endpoint data
+ * @param[in] n         number of bytes to pull from the FIFO
+ * @param[in] max       number of bytes to copy into the buffer
+ *
+ * @notapi
+ */
+static void otg_fifo_read_to_buffer(volatile uint32_t *fifop,
+                                    uint8_t *buf,
+                                    size_t n,
+                                    size_t max) {
+
+  n = (n + 3) / 4;
+  max = (max + 3) / 4;
+  while (n) {
+    uint32_t w = *fifop;
+    if (max) {
+      /* Note, this line relies on the Cortex-M3/M4 ability to perform
+         unaligned word accesses and on the LSB-first memory organization.*/
+      *((PACKED_VAR uint32_t *)buf) = w;
+      buf += 4;
+      max--;
+    }
+    n--;
+  }
+}
+
+/**
+ * @brief   Reads a packet from the RXFIFO.
+ *
+ * @param[in] fifop     pointer to the FIFO register
+ * @param[in] iqp       pointer to an @p input_queue_t object
+ * @param[in] n         number of bytes to pull from the FIFO
+ *
+ * @notapi
+ */
+static void otg_fifo_read_to_queue(volatile uint32_t *fifop,
+                                   input_queue_t *iqp,
+                                   size_t n) {
+  size_t ntogo;
+
+  ntogo = n;
+  while (ntogo > 0) {
+    uint32_t w, i;
+    size_t nw = ntogo / 4;
+
+    if (nw > 0) {
+      size_t streak;
+      uint32_t nw2end = (iqp->q_wrptr - iqp->q_wrptr) / 4;
+
+      ntogo -= (streak = nw <= nw2end ? nw : nw2end) * 4;
+      iqp->q_wrptr = otg_do_pop(fifop, iqp->q_wrptr, streak);
+      if (iqp->q_wrptr >= iqp->q_top) {
+        iqp->q_wrptr = iqp->q_buffer;
+        continue;
+      }
+    }
+
+    /* If this condition is not satisfied then there is a word lying across
+       queue circular buffer boundary or there are some remaining bytes.*/
+    if (ntogo <= 0)
+      break;
+
+    /* One byte at time.*/
+    w = *fifop;
+    i = 0;
+    while ((ntogo > 0) && (i < 4)) {
+      *iqp->q_wrptr++ = (uint8_t)(w >> (i * 8));
+      if (iqp->q_wrptr >= iqp->q_top)
+        iqp->q_wrptr = iqp->q_buffer;
+      ntogo--;
+      i++;
+    }
+  }
+
+  /* Updating queue.*/
+  osalSysLock();
+  iqp->q_counter += n;
+  osalThreadDequeueAllI(&iqp->q_waiting, Q_OK);
+  osalOsRescheduleS();
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Incoming packets handler.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+static void otg_rxfifo_handler(USBDriver *usbp) {
+  uint32_t sts, cnt, ep;
+
+  sts = usbp->otg->GRXSTSP;
+  switch (sts & GRXSTSP_PKTSTS_MASK) {
+  case GRXSTSP_SETUP_COMP:
+    break;
+  case GRXSTSP_SETUP_DATA:
+    cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
+    ep  = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
+    otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->setup_buf,
+                            cnt, 8);
+    break;
+  case GRXSTSP_OUT_DATA:
+    cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
+    ep  = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
+    if (usbp->epc[ep]->out_state->rxqueued) {
+      /* Queue associated.*/
+      otg_fifo_read_to_queue(usbp->otg->FIFO[0],
+                             usbp->epc[ep]->out_state->mode.queue.rxqueue,
+                             cnt);
+    }
+    else {
+      otg_fifo_read_to_buffer(usbp->otg->FIFO[0],
+                              usbp->epc[ep]->out_state->mode.linear.rxbuf,
+                              cnt,
+                              usbp->epc[ep]->out_state->rxsize -
+                              usbp->epc[ep]->out_state->rxcnt);
+      usbp->epc[ep]->out_state->mode.linear.rxbuf += cnt;
+    }
+    usbp->epc[ep]->out_state->rxcnt += cnt;
+    break;
+  case GRXSTSP_OUT_GLOBAL_NAK:
+  case GRXSTSP_OUT_COMP:
+  default:
+    ;
+  }
+}
+
+/**
+ * @brief   Outgoing packets handler.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
+
+  /* The TXFIFO is filled until there is space and data to be transmitted.*/
+  while (TRUE) {
+    uint32_t n;
+
+    /* Transaction end condition.*/
+    if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize)
+      return TRUE;
+
+    /* Number of bytes remaining in current transaction.*/
+    n = usbp->epc[ep]->in_state->txsize - usbp->epc[ep]->in_state->txcnt;
+    if (n > usbp->epc[ep]->in_maxsize)
+      n = usbp->epc[ep]->in_maxsize;
+
+    /* Checks if in the TXFIFO there is enough space to accommodate the
+       next packet.*/
+    if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n)
+      return FALSE;
+
+#if STM32_USB_OTGFIFO_FILL_BASEPRI
+    __set_BASEPRI(CORTEX_PRIORITY_MASK(STM32_USB_OTGFIFO_FILL_BASEPRI));
+#endif
+    /* Handles the two cases: linear buffer or queue.*/
+    if (usbp->epc[ep]->in_state->txqueued) {
+      /* Queue associated.*/
+      otg_fifo_write_from_queue(usbp->otg->FIFO[ep],
+                                usbp->epc[ep]->in_state->mode.queue.txqueue,
+                                n);
+    }
+    else {
+      /* Linear buffer associated.*/
+      otg_fifo_write_from_buffer(usbp->otg->FIFO[ep],
+                                 usbp->epc[ep]->in_state->mode.linear.txbuf,
+                                 n);
+      usbp->epc[ep]->in_state->mode.linear.txbuf += n;
+    }
+    usbp->epc[ep]->in_state->txcnt += n;
+  }
+#if STM32_USB_OTGFIFO_FILL_BASEPRI
+  __set_BASEPRI(0);
+#endif
+}
+
+/**
+ * @brief   Generic endpoint IN handler.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
+  stm32_otg_t *otgp = usbp->otg;
+  uint32_t epint = otgp->ie[ep].DIEPINT;
+
+  otgp->ie[ep].DIEPINT = epint;
+
+  if (epint & DIEPINT_TOC) {
+    /* Timeouts not handled yet, not sure how to handle.*/
+  }
+  if ((epint & DIEPINT_XFRC) && (otgp->DIEPMSK & DIEPMSK_XFRCM)) {
+    /* Transmit transfer complete.*/
+    USBInEndpointState *isp = usbp->epc[ep]->in_state;
+
+    if (isp->txsize < isp->totsize) {
+      /* In case the transaction covered only part of the total transfer
+         then another transaction is immediately started in order to
+         cover the remaining.*/
+      isp->txsize = isp->totsize - isp->txsize;
+      isp->txcnt  = 0;
+      usb_lld_prepare_transmit(usbp, ep);
+      osalSysLockFromISR();
+      usb_lld_start_in(usbp, ep);
+      osalSysUnlockFromISR();
+    }
+    else {
+      /* End on IN transfer.*/
+      _usb_isr_invoke_in_cb(usbp, ep);
+    }
+  }
+  if ((epint & DIEPINT_TXFE) &&
+      (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) {
+    /* The thread is made ready, it will be scheduled on ISR exit.*/
+    osalSysLockFromISR();
+    usbp->txpending |= (1 << ep);
+    otgp->DIEPEMPMSK &= ~(1 << ep);
+    osalThreadResumeI(&usbp->wait, MSG_OK);
+    osalSysUnlockFromISR();
+  }
+}
+
+/**
+ * @brief   Generic endpoint OUT handler.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
+  stm32_otg_t *otgp = usbp->otg;
+  uint32_t epint = otgp->oe[ep].DOEPINT;
+
+  /* Resets all EP IRQ sources.*/
+  otgp->oe[ep].DOEPINT = epint;
+
+  if ((epint & DOEPINT_STUP) && (otgp->DOEPMSK & DOEPMSK_STUPM)) {
+    /* Setup packets handling, setup packets are handled using a
+       specific callback.*/
+    _usb_isr_invoke_setup_cb(usbp, ep);
+
+  }
+  if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) {
+    /* Receive transfer complete.*/
+    _usb_isr_invoke_out_cb(usbp, ep);
+  }
+}
+
+/**
+ * @brief   OTG shared ISR.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+static void usb_lld_serve_interrupt(USBDriver *usbp) {
+  stm32_otg_t *otgp = usbp->otg;
+  uint32_t sts, src;
+
+  sts = otgp->GINTSTS & otgp->GINTMSK;
+  otgp->GINTSTS = sts;
+
+  /* Reset interrupt handling.*/
+  if (sts & GINTSTS_USBRST) {
+    _usb_reset(usbp);
+    _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
+  }
+
+  /* Enumeration done.*/
+  if (sts & GINTSTS_ENUMDNE) {
+    (void)otgp->DSTS;
+  }
+
+  /* SOF interrupt handling.*/
+  if (sts & GINTSTS_SOF) {
+    _usb_isr_invoke_sof_cb(usbp);
+  }
+
+  /* RX FIFO not empty handling.*/
+  if (sts & GINTSTS_RXFLVL) {
+    /* The interrupt is masked while the thread has control or it would
+       be triggered again.*/
+    osalSysLockFromISR();
+    otgp->GINTMSK &= ~GINTMSK_RXFLVLM;
+    osalThreadResumeI(&usbp->wait, MSG_OK);
+    osalSysUnlockFromISR();
+  }
+
+  /* IN/OUT endpoints event handling.*/
+  src = otgp->DAINT;
+  if (sts & GINTSTS_IEPINT) {
+    if (src & (1 << 0))
+      otg_epin_handler(usbp, 0);
+    if (src & (1 << 1))
+      otg_epin_handler(usbp, 1);
+    if (src & (1 << 2))
+      otg_epin_handler(usbp, 2);
+    if (src & (1 << 3))
+      otg_epin_handler(usbp, 3);
+#if STM32_USB_USE_OTG2
+    if (src & (1 << 4))
+      otg_epin_handler(usbp, 4);
+    if (src & (1 << 5))
+      otg_epin_handler(usbp, 5);
+#endif
+  }
+  if (sts & GINTSTS_OEPINT) {
+    if (src & (1 << 16))
+      otg_epout_handler(usbp, 0);
+    if (src & (1 << 17))
+      otg_epout_handler(usbp, 1);
+    if (src & (1 << 18))
+      otg_epout_handler(usbp, 2);
+    if (src & (1 << 19))
+      otg_epout_handler(usbp, 3);
+#if STM32_USB_USE_OTG2
+    if (src & (1 << 20))
+      otg_epout_handler(usbp, 4);
+    if (src & (1 << 21))
+      otg_epout_handler(usbp, 5);
+#endif
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
+#if !defined(STM32_OTG1_HANDLER)
+#error "STM32_OTG1_HANDLER not defined"
+#endif
+/**
+ * @brief   OTG1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_OTG1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  usb_lld_serve_interrupt(&USBD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
+#if !defined(STM32_OTG2_HANDLER)
+#error "STM32_OTG2_HANDLER not defined"
+#endif
+/**
+ * @brief   OTG2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_OTG2_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  usb_lld_serve_interrupt(&USBD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level USB driver initialization.
+ *
+ * @notapi
+ */
+void usb_lld_init(void) {
+
+  /* Driver initialization.*/
+#if STM32_USB_USE_OTG1
+  usbObjectInit(&USBD1);
+  USBD1.wait      = NULL;
+  USBD1.otg       = OTG_FS;
+  USBD1.otgparams = &fsparams;
+
+#if defined(_CHIBIOS_RT_)
+  USBD1.tr = NULL;
+  /* Filling the thread working area here because the function
+     @p chThdCreateI() does not do it.*/
+#if CH_DBG_FILL_THREADS
+  {
+    void *wsp = USBD1.wa_pump;
+    _thread_memfill((uint8_t *)wsp,
+                    (uint8_t *)wsp + sizeof(thread_t),
+                    CH_DBG_THREAD_FILL_VALUE);
+    _thread_memfill((uint8_t *)wsp + sizeof(thread_t),
+                    (uint8_t *)wsp + sizeof(USBD1.wa_pump) - sizeof(thread_t),
+                    CH_DBG_STACK_FILL_VALUE);
+  }
+#endif /* CH_DBG_FILL_THREADS */
+#endif /* defined(_CHIBIOS_RT_) */
+#endif
+
+#if STM32_USB_USE_OTG2
+  usbObjectInit(&USBD2);
+  USBD2.wait      = NULL;
+  USBD2.otg       = OTG_HS;
+  USBD2.otgparams = &hsparams;
+
+#if defined(_CHIBIOS_RT_)
+  USBD2.tr = NULL;
+  /* Filling the thread working area here because the function
+     @p chThdCreateI() does not do it.*/
+#if CH_DBG_FILL_THREADS
+  {
+    void *wsp = USBD2.wa_pump;
+    _thread_memfill((uint8_t *)wsp,
+                    (uint8_t *)wsp + sizeof(thread_t),
+                    CH_DBG_THREAD_FILL_VALUE);
+    _thread_memfill((uint8_t *)wsp + sizeof(thread_t),
+                    (uint8_t *)wsp + sizeof(USBD2.wa_pump) - sizeof(thread_t),
+                    CH_DBG_STACK_FILL_VALUE);
+  }
+#endif /* CH_DBG_FILL_THREADS */
+#endif /* defined(_CHIBIOS_RT_) */
+#endif
+}
+
+/**
+ * @brief   Configures and activates the USB peripheral.
+ * @note    Starting the OTG cell can be a slow operation carried out with
+ *          interrupts disabled, perform it before starting time-critical
+ *          operations.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_start(USBDriver *usbp) {
+  stm32_otg_t *otgp = usbp->otg;
+
+  if (usbp->state == USB_STOP) {
+    /* Clock activation.*/
+#if STM32_USB_USE_OTG1
+    if (&USBD1 == usbp) {
+      /* OTG FS clock enable and reset.*/
+      rccEnableOTG_FS(FALSE);
+      rccResetOTG_FS();
+
+      /* Enables IRQ vector.*/
+      nvicEnableVector(STM32_OTG1_NUMBER, STM32_USB_OTG1_IRQ_PRIORITY);
+    }
+#endif
+#if STM32_USB_USE_OTG2
+    if (&USBD2 == usbp) {
+      /* OTG HS clock enable and reset.*/
+      rccEnableOTG_HS(FALSE);
+      rccResetOTG_HS();
+
+      /* Workaround for the problem described here:
+         http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798 */
+      rccDisableOTG_HSULPI(TRUE);
+
+      /* Enables IRQ vector.*/
+      nvicEnableVector(STM32_OTG2_NUMBER, STM32_USB_OTG2_IRQ_PRIORITY);
+    }
+#endif
+
+    usbp->txpending = 0;
+
+#if defined(_CHIBIOS_RT_)
+    /* Creates the data pump threads in a suspended state. Note, it is
+       created only once, the first time @p usbStart() is invoked.*/
+    if (usbp->tr == NULL)
+      usbp->tr = usbp->wait = chThdCreateI(usbp->wa_pump,
+                                           sizeof usbp->wa_pump,
+                                           STM32_USB_OTG_THREAD_PRIO,
+                                           usb_lld_pump,
+                                           usbp);
+#endif
+
+    /* - Forced device mode.
+       - USB turn-around time = TRDT_VALUE.
+       - Full Speed 1.1 PHY.*/
+    otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE) | GUSBCFG_PHYSEL;
+
+    /* 48MHz 1.1 PHY.*/
+    otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11;
+
+    /* PHY enabled.*/
+    otgp->PCGCCTL = 0;
+
+    /* Internal FS PHY activation.*/
+#if defined(BOARD_OTG_NOVBUSSENS)
+    otgp->GCCFG = GCCFG_NOVBUSSENS | GCCFG_VBUSASEN | GCCFG_VBUSBSEN |
+                  GCCFG_PWRDWN;
+#else
+    otgp->GCCFG = GCCFG_VBUSASEN | GCCFG_VBUSBSEN | GCCFG_PWRDWN;
+#endif
+
+    /* Soft core reset.*/
+    otg_core_reset(usbp);
+
+    /* Interrupts on TXFIFOs half empty.*/
+    otgp->GAHBCFG = 0;
+
+    /* Endpoints re-initialization.*/
+    otg_disable_ep(usbp);
+
+    /* Clear all pending Device Interrupts, only the USB Reset interrupt
+       is required initially.*/
+    otgp->DIEPMSK  = 0;
+    otgp->DOEPMSK  = 0;
+    otgp->DAINTMSK = 0;
+    if (usbp->config->sof_cb == NULL)
+      otgp->GINTMSK  = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM |
+                       GINTMSK_ESUSPM  |*/;
+    else
+      otgp->GINTMSK  = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM /*| GINTMSK_USBSUSPM |
+                       GINTMSK_ESUSPM */ | GINTMSK_SOFM;
+    otgp->GINTSTS  = 0xFFFFFFFF;         /* Clears all pending IRQs, if any. */
+
+    /* Global interrupts enable.*/
+    otgp->GAHBCFG |= GAHBCFG_GINTMSK;
+  }
+}
+
+/**
+ * @brief   Deactivates the USB peripheral.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_stop(USBDriver *usbp) {
+  stm32_otg_t *otgp = usbp->otg;
+
+  /* If in ready state then disables the USB clock.*/
+  if (usbp->state != USB_STOP) {
+
+    /* Disabling all endpoints in case the driver has been stopped while
+       active.*/
+    otg_disable_ep(usbp);
+
+    usbp->txpending = 0;
+
+    otgp->DAINTMSK   = 0;
+    otgp->GAHBCFG    = 0;
+    otgp->GCCFG      = 0;
+
+#if STM32_USB_USE_USB1
+    if (&USBD1 == usbp) {
+      nvicDisableVector(STM32_OTG1_NUMBER);
+      rccDisableOTG1(FALSE);
+    }
+#endif
+
+#if STM32_USB_USE_USB2
+    if (&USBD2 == usbp) {
+      nvicDisableVector(STM32_OTG2_NUMBER);
+      rccDisableOTG2(FALSE);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   USB low level reset routine.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_reset(USBDriver *usbp) {
+  unsigned i;
+  stm32_otg_t *otgp = usbp->otg;
+
+  /* Flush the Tx FIFO.*/
+  otg_txfifo_flush(usbp, 0);
+
+  /* All endpoints in NAK mode, interrupts cleared.*/
+  for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
+    otgp->ie[i].DIEPCTL = DIEPCTL_SNAK;
+    otgp->oe[i].DOEPCTL = DOEPCTL_SNAK;
+    otgp->ie[i].DIEPINT = 0xFF;
+    otgp->oe[i].DOEPINT = 0xFF;
+  }
+
+  /* Endpoint interrupts all disabled and cleared.*/
+  otgp->DAINT = 0xFFFFFFFF;
+  otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
+
+  /* Resets the FIFO memory allocator.*/
+  otg_ram_reset(usbp);
+
+  /* Receive FIFO size initialization, the address is always zero.*/
+  otgp->GRXFSIZ = usbp->otgparams->rx_fifo_size;
+  otg_rxfifo_flush(usbp);
+
+  /* Resets the device address to zero.*/
+  otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0);
+
+  /* Enables also EP-related interrupt sources.*/
+  otgp->GINTMSK  |= GINTMSK_RXFLVLM | GINTMSK_OEPM  | GINTMSK_IEPM;
+  otgp->DIEPMSK   = DIEPMSK_TOCM    | DIEPMSK_XFRCM;
+  otgp->DOEPMSK   = DOEPMSK_STUPM   | DOEPMSK_XFRCM;
+
+  /* EP0 initialization, it is a special case.*/
+  usbp->epc[0] = &ep0config;
+  otgp->oe[0].DOEPTSIZ = 0;
+  otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL |
+                        DOEPCTL_MPSIZ(ep0config.out_maxsize);
+  otgp->ie[0].DIEPTSIZ = 0;
+  otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL |
+                        DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize);
+  otgp->DIEPTXF0 = DIEPTXF_INEPTXFD(ep0config.in_maxsize / 4) |
+                   DIEPTXF_INEPTXSA(otg_ram_alloc(usbp,
+                                                  ep0config.in_maxsize / 4));
+}
+
+/**
+ * @brief   Sets the USB address.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_set_address(USBDriver *usbp) {
+  stm32_otg_t *otgp = usbp->otg;
+
+  otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address);
+}
+
+/**
+ * @brief   Enables an endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
+  uint32_t ctl, fsize;
+  stm32_otg_t *otgp = usbp->otg;
+
+  /* IN and OUT common parameters.*/
+  switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) {
+  case USB_EP_MODE_TYPE_CTRL:
+    ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL;
+    break;
+  case USB_EP_MODE_TYPE_ISOC:
+    ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO;
+    break;
+  case USB_EP_MODE_TYPE_BULK:
+    ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK;
+    break;
+  case USB_EP_MODE_TYPE_INTR:
+    ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR;
+    break;
+  default:
+    return;
+  }
+
+  /* OUT endpoint activation or deactivation.*/
+  otgp->oe[ep].DOEPTSIZ = 0;
+  if (usbp->epc[ep]->out_cb != NULL) {
+    otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize);
+    otgp->DAINTMSK |= DAINTMSK_OEPM(ep);
+  }
+  else {
+    otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP;
+    otgp->DAINTMSK &= ~DAINTMSK_OEPM(ep);
+  }
+
+  /* IN endpoint activation or deactivation.*/
+  otgp->ie[ep].DIEPTSIZ = 0;
+  if (usbp->epc[ep]->in_cb != NULL) {
+    /* FIFO allocation for the IN endpoint.*/
+    fsize = usbp->epc[ep]->in_maxsize / 4;
+    if (usbp->epc[ep]->in_multiplier > 1)
+      fsize *= usbp->epc[ep]->in_multiplier;
+    otgp->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFD(fsize) |
+                            DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, fsize));
+    otg_txfifo_flush(usbp, ep);
+
+    otgp->ie[ep].DIEPCTL = ctl |
+                           DIEPCTL_TXFNUM(ep) |
+                           DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize);
+    otgp->DAINTMSK |= DAINTMSK_IEPM(ep);
+  }
+  else {
+    otgp->DIEPTXF[ep - 1] = 0x02000400; /* Reset value.*/
+    otg_txfifo_flush(usbp, ep);
+    otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP;
+    otgp->DAINTMSK &= ~DAINTMSK_IEPM(ep);
+  }
+}
+
+/**
+ * @brief   Disables all the active endpoints except the endpoint zero.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_disable_endpoints(USBDriver *usbp) {
+
+  /* Resets the FIFO memory allocator.*/
+  otg_ram_reset(usbp);
+
+  /* Disabling all endpoints.*/
+  otg_disable_ep(usbp);
+}
+
+/**
+ * @brief   Returns the status of an OUT endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ * @return              The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED  The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE   The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
+  uint32_t ctl;
+
+  (void)usbp;
+
+  ctl = usbp->otg->oe[ep].DOEPCTL;
+  if (!(ctl & DOEPCTL_USBAEP))
+    return EP_STATUS_DISABLED;
+  if (ctl & DOEPCTL_STALL)
+    return EP_STATUS_STALLED;
+  return EP_STATUS_ACTIVE;
+}
+
+/**
+ * @brief   Returns the status of an IN endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ * @return              The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED  The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE   The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
+  uint32_t ctl;
+
+  (void)usbp;
+
+  ctl = usbp->otg->ie[ep].DIEPCTL;
+  if (!(ctl & DIEPCTL_USBAEP))
+    return EP_STATUS_DISABLED;
+  if (ctl & DIEPCTL_STALL)
+    return EP_STATUS_STALLED;
+  return EP_STATUS_ACTIVE;
+}
+
+/**
+ * @brief   Reads a setup packet from the dedicated packet buffer.
+ * @details This function must be invoked in the context of the @p setup_cb
+ *          callback in order to read the received setup packet.
+ * @pre     In order to use this function the endpoint must have been
+ *          initialized as a control endpoint.
+ * @post    The endpoint is ready to accept another packet.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ * @param[out] buf      buffer where to copy the packet data
+ *
+ * @notapi
+ */
+void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
+
+  memcpy(buf, usbp->epc[ep]->setup_buf, 8);
+}
+
+/**
+ * @brief   Prepares for a receive operation.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
+  uint32_t pcnt;
+  USBOutEndpointState *osp = usbp->epc[ep]->out_state;
+
+  /* Transfer initialization.*/
+  pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
+         usbp->epc[ep]->out_maxsize;
+  usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) |
+                               DOEPTSIZ_XFRSIZ(osp->rxsize);
+
+}
+
+/**
+ * @brief   Prepares for a transmit operation.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
+  USBInEndpointState *isp = usbp->epc[ep]->in_state;
+
+  /* Transfer initialization.*/
+  isp->totsize = isp->txsize;
+  if (isp->txsize == 0) {
+    /* Special case, sending zero size packet.*/
+    usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0);
+  }
+  else {
+    if ((ep == 0) && (isp->txsize  > EP0_MAX_INSIZE))
+      isp->txsize = EP0_MAX_INSIZE;
+
+    /* Normal case.*/
+    uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) /
+                    usbp->epc[ep]->in_maxsize;
+    usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(pcnt) |
+                                 DIEPTSIZ_XFRSIZ(isp->txsize);
+  }
+}
+
+/**
+ * @brief   Starts a receive operation on an OUT endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
+
+  usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_CNAK;
+}
+
+/**
+ * @brief   Starts a transmit operation on an IN endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
+
+  usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+  usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep);
+}
+
+/**
+ * @brief   Brings an OUT endpoint in the stalled state.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
+
+  usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_STALL;
+}
+
+/**
+ * @brief   Brings an IN endpoint in the stalled state.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
+
+  usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_STALL;
+}
+
+/**
+ * @brief   Brings an OUT endpoint in the active state.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
+
+  usbp->otg->oe[ep].DOEPCTL &= ~DOEPCTL_STALL;
+}
+
+/**
+ * @brief   Brings an IN endpoint in the active state.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
+
+  usbp->otg->ie[ep].DIEPCTL &= ~DIEPCTL_STALL;
+}
+
+/**
+ * @brief   USB data transfer loop.
+ * @details This function must be executed by a system thread in order to
+ *          make the USB driver work.
+ * @note    The data copy part of the driver is implemented in this thread
+ *          in order to not perform heavy tasks withing interrupt handlers.
+ *
+ * @param[in] p         pointer to the @p USBDriver object
+ * @return              The function never returns.
+ *
+ * @special
+ */
+msg_t usb_lld_pump(void *p) {
+  USBDriver *usbp = (USBDriver *)p;
+  stm32_otg_t *otgp = usbp->otg;
+
+#if defined(_CHIBIOS_RT_)
+  chRegSetThreadName("usb_lld_pump");
+#endif
+  osalSysLock();
+  while (true) {
+    usbep_t ep;
+    uint32_t epmask;
+
+    /* Nothing to do, going to sleep.*/
+    if ((usbp->state == USB_STOP) ||
+        ((usbp->txpending == 0) && !(otgp->GINTSTS & GINTSTS_RXFLVL))) {
+      otgp->GINTMSK |= GINTMSK_RXFLVLM;
+      osalThreadSuspendS(&usbp->wait);
+    }
+    osalSysUnlock();
+
+    /* Checks if there are TXFIFOs to be filled.*/
+    for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
+
+      /* Empties the RX FIFO.*/
+      while (otgp->GINTSTS & GINTSTS_RXFLVL) {
+        otg_rxfifo_handler(usbp);
+      }
+
+      epmask = (1 << ep);
+      if (usbp->txpending & epmask) {
+        bool done;
+
+        osalSysLock();
+        /* USB interrupts are globally *suspended* because the peripheral
+           does not allow any interference during the TX FIFO filling
+           operation.
+           Synopsys document: DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG)
+             "The application has to finish writing one complete packet before
+              switching to a different channel/endpoint FIFO. Violating this
+              rule results in an error.".*/
+        otgp->GAHBCFG &= ~GAHBCFG_GINTMSK;
+        usbp->txpending &= ~epmask;
+        osalSysUnlock();
+
+        done = otg_txfifo_handler(usbp, ep);
+
+        osalSysLock();
+        otgp->GAHBCFG |= GAHBCFG_GINTMSK;
+        if (!done)
+          otgp->DIEPEMPMSK |= epmask;
+        osalSysUnlock();
+      }
+    }
+    osalSysLock();
+  }
+  osalSysUnlock();
+  return 0;
+}
+
+#endif /* HAL_USE_USB */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/OTGv1/usb_lld.h b/os/hal/ports/STM32/LLD/OTGv1/usb_lld.h
new file mode 100644
index 000000000..689d607a5
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/OTGv1/usb_lld.h
@@ -0,0 +1,546 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/OTGv1/usb_lld.h
+ * @brief   STM32 USB subsystem low level driver header.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#ifndef _USB_LLD_H_
+#define _USB_LLD_H_
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+#include "stm32_otg.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Maximum endpoint address.
+ */
+#if !STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
+#define USB_MAX_ENDPOINTS                   3
+#else
+#define USB_MAX_ENDPOINTS                   5
+#endif
+
+/**
+ * @brief   Status stage handling method.
+ */
+#define USB_EP0_STATUS_STAGE                USB_EP0_STATUS_STAGE_SW
+
+/**
+ * @brief   The address can be changed immediately upon packet reception.
+ */
+#define USB_SET_ADDRESS_MODE                USB_EARLY_SET_ADDRESS
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   OTG1 driver enable switch.
+ * @details If set to @p TRUE the support for OTG_FS is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_USB_USE_OTG1) || defined(__DOXYGEN__)
+#define STM32_USB_USE_OTG1                  FALSE
+#endif
+
+/**
+ * @brief   OTG2 driver enable switch.
+ * @details If set to @p TRUE the support for OTG_HS is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_USB_USE_OTG2) || defined(__DOXYGEN__)
+#define STM32_USB_USE_OTG2                  FALSE
+#endif
+
+/**
+ * @brief   OTG1 interrupt priority level setting.
+ */
+#if !defined(STM32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_USB_OTG1_IRQ_PRIORITY         14
+#endif
+
+/**
+ * @brief   OTG2 interrupt priority level setting.
+ */
+#if !defined(STM32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_USB_OTG2_IRQ_PRIORITY         14
+#endif
+
+/**
+ * @brief   OTG1 RX shared FIFO size.
+ * @note    Must be a multiple of 4.
+ */
+#if !defined(STM32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__)
+#define STM32_USB_OTG1_RX_FIFO_SIZE         512
+#endif
+
+/**
+ * @brief   OTG2 RX shared FIFO size.
+ * @note    Must be a multiple of 4.
+ */
+#if !defined(STM32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__)
+#define STM32_USB_OTG2_RX_FIFO_SIZE         1024
+#endif
+
+/**
+ * @brief   Dedicated data pump threads priority.
+ */
+#if !defined(STM32_USB_OTG_THREAD_PRIO) || defined(__DOXYGEN__)
+#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
+#endif
+
+/**
+ * @brief   Dedicated data pump threads stack size.
+ */
+#if !defined(STM32_USB_OTG_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define STM32_USB_OTG_THREAD_STACK_SIZE     128
+#endif
+
+/**
+ * @brief   Exception priority level during TXFIFOs operations.
+ * @note    Because an undocumented silicon behavior the operation of
+ *          copying a packet into a TXFIFO must not be interrupted by
+ *          any other operation on the OTG peripheral.
+ *          This parameter represents the priority mask during copy
+ *          operations. The default value only allows to call USB
+ *          functions from callbacks invoked from USB ISR handlers.
+ *          If you need to invoke USB functions from other handlers
+ *          then raise this priority mast to the same level of the
+ *          handler you need to use.
+ * @note    The value zero means disabled, when disabled calling USB
+ *          functions is only safe from thread level or from USB
+ *          callbacks.
+ */
+#if !defined(STM32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__)
+#define STM32_USB_OTGFIFO_FILL_BASEPRI      0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_USB_USE_OTG1 && !STM32_HAS_OTG1
+#error "OTG1 not present in the selected device"
+#endif
+
+#if STM32_USB_USE_OTG2 && !STM32_HAS_OTG2
+#error "OTG2 not present in the selected device"
+#endif
+
+#if !STM32_USB_USE_OTG1 && !STM32_USB_USE_OTG2
+#error "USB driver activated but no USB peripheral assigned"
+#endif
+
+#if STM32_USB_USE_OTG1 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to OTG1"
+#endif
+
+#if STM32_USB_USE_OTG2 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_OTG2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to OTG2"
+#endif
+
+#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0
+#error "OTG1 RX FIFO size must be a multiple of 4"
+#endif
+
+#if (STM32_USB_OTG2_RX_FIFO_SIZE & 3) != 0
+#error "OTG2 RX FIFO size must be a multiple of 4"
+#endif
+
+#if defined(STM32F4XX) || defined(STM32F2XX)
+#define STM32_USBCLK                        STM32_PLL48CLK
+#elif defined(STM32F10X_CL)
+#define STM32_USBCLK                        STM32_OTGFSCLK
+#else
+#error "unsupported STM32 platform for OTG functionality"
+#endif
+
+#if STM32_USBCLK != 48000000
+#error "the USB OTG driver requires a 48MHz clock"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Peripheral-specific parameters block.
+ */
+typedef struct {
+  uint32_t                      rx_fifo_size;
+  uint32_t                      otg_ram_size;
+  uint32_t                      num_endpoints;
+} stm32_otg_params_t;
+
+/**
+ * @brief   Type of an IN endpoint state structure.
+ */
+typedef struct {
+  /**
+   * @brief   Buffer mode, queue or linear.
+   */
+  bool                          txqueued;
+  /**
+   * @brief   Requested transmit transfer size.
+   */
+  size_t                        txsize;
+  /**
+   * @brief   Transmitted bytes so far.
+   */
+  size_t                        txcnt;
+  union {
+    struct {
+      /**
+       * @brief   Pointer to the transmission linear buffer.
+       */
+      const uint8_t             *txbuf;
+    } linear;
+    struct {
+      /**
+       * @brief   Pointer to the output queue.
+       */
+      output_queue_t            *txqueue;
+    } queue;
+  } mode;
+  /**
+   * @brief   Total transmit transfer size.
+   */
+  size_t                        totsize;
+} USBInEndpointState;
+
+/**
+ * @brief   Type of an OUT endpoint state structure.
+ */
+typedef struct {
+  /**
+   * @brief   Buffer mode, queue or linear.
+   */
+  bool                          rxqueued;
+  /**
+   * @brief   Requested receive transfer size.
+   */
+  size_t                        rxsize;
+  /**
+   * @brief   Received bytes so far.
+   */
+  size_t                        rxcnt;
+  union {
+    struct {
+      /**
+       * @brief   Pointer to the receive linear buffer.
+       */
+      uint8_t                   *rxbuf;
+    } linear;
+    struct {
+      /**
+       * @brief   Pointer to the input queue.
+       */
+      input_queue_t            *rxqueue;
+    } queue;
+  } mode;
+} USBOutEndpointState;
+
+/**
+ * @brief   Type of an USB endpoint configuration structure.
+ * @note    Platform specific restrictions may apply to endpoints.
+ */
+typedef struct {
+  /**
+   * @brief   Type and mode of the endpoint.
+   */
+  uint32_t                      ep_mode;
+  /**
+   * @brief   Setup packet notification callback.
+   * @details This callback is invoked when a setup packet has been
+   *          received.
+   * @post    The application must immediately call @p usbReadPacket() in
+   *          order to access the received packet.
+   * @note    This field is only valid for @p USB_EP_MODE_TYPE_CTRL
+   *          endpoints, it should be set to @p NULL for other endpoint
+   *          types.
+   */
+  usbepcallback_t               setup_cb;
+  /**
+   * @brief   IN endpoint notification callback.
+   * @details This field must be set to @p NULL if the IN endpoint is not
+   *          used.
+   */
+  usbepcallback_t               in_cb;
+  /**
+   * @brief   OUT endpoint notification callback.
+   * @details This field must be set to @p NULL if the OUT endpoint is not
+   *          used.
+   */
+  usbepcallback_t               out_cb;
+  /**
+   * @brief   IN endpoint maximum packet size.
+   * @details This field must be set to zero if the IN endpoint is not
+   *          used.
+   */
+  uint16_t                      in_maxsize;
+  /**
+   * @brief   OUT endpoint maximum packet size.
+   * @details This field must be set to zero if the OUT endpoint is not
+   *          used.
+   */
+  uint16_t                      out_maxsize;
+  /**
+   * @brief   @p USBEndpointState associated to the IN endpoint.
+   * @details This structure maintains the state of the IN endpoint.
+   */
+  USBInEndpointState            *in_state;
+  /**
+   * @brief   @p USBEndpointState associated to the OUT endpoint.
+   * @details This structure maintains the state of the OUT endpoint.
+   */
+  USBOutEndpointState           *out_state;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Determines the space allocated for the TXFIFO as multiples of
+   *          the packet size (@p in_maxsize). Note that zero is interpreted
+   *          as one for simplicity and robustness.
+   */
+  uint16_t                      in_multiplier;
+  /**
+   * @brief   Pointer to a buffer for setup packets.
+   * @details Setup packets require a dedicated 8-bytes buffer, set this
+   *          field to @p NULL for non-control endpoints.
+   */
+  uint8_t                       *setup_buf;
+} USBEndpointConfig;
+
+/**
+ * @brief   Type of an USB driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief   USB events callback.
+   * @details This callback is invoked when an USB driver event is registered.
+   */
+  usbeventcb_t                  event_cb;
+  /**
+   * @brief   Device GET_DESCRIPTOR request callback.
+   * @note    This callback is mandatory and cannot be set to @p NULL.
+   */
+  usbgetdescriptor_t            get_descriptor_cb;
+  /**
+   * @brief   Requests hook callback.
+   * @details This hook allows to be notified of standard requests or to
+   *          handle non standard requests.
+   */
+  usbreqhandler_t               requests_hook_cb;
+  /**
+   * @brief   Start Of Frame callback.
+   */
+  usbcallback_t                 sof_cb;
+  /* End of the mandatory fields.*/
+} USBConfig;
+
+/**
+ * @brief   Structure representing an USB driver.
+ */
+struct USBDriver {
+  /**
+   * @brief   Driver state.
+   */
+  usbstate_t                    state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const USBConfig               *config;
+  /**
+   * @brief   Bit map of the transmitting IN endpoints.
+   */
+  uint16_t                      transmitting;
+  /**
+   * @brief   Bit map of the receiving OUT endpoints.
+   */
+  uint16_t                      receiving;
+  /**
+   * @brief   Active endpoints configurations.
+   */
+  const USBEndpointConfig       *epc[USB_MAX_ENDPOINTS + 1];
+  /**
+   * @brief   Fields available to user, it can be used to associate an
+   *          application-defined handler to an IN endpoint.
+   * @note    The base index is one, the endpoint zero does not have a
+   *          reserved element in this array.
+   */
+  void                          *in_params[USB_MAX_ENDPOINTS];
+  /**
+   * @brief   Fields available to user, it can be used to associate an
+   *          application-defined handler to an OUT endpoint.
+   * @note    The base index is one, the endpoint zero does not have a
+   *          reserved element in this array.
+   */
+  void                          *out_params[USB_MAX_ENDPOINTS];
+  /**
+   * @brief   Endpoint 0 state.
+   */
+  usbep0state_t                 ep0state;
+  /**
+   * @brief   Next position in the buffer to be transferred through endpoint 0.
+   */
+  uint8_t                       *ep0next;
+  /**
+   * @brief   Number of bytes yet to be transferred through endpoint 0.
+   */
+  size_t                        ep0n;
+  /**
+   * @brief   Endpoint 0 end transaction callback.
+   */
+  usbcallback_t                 ep0endcb;
+  /**
+   * @brief   Setup packet buffer.
+   */
+  uint8_t                       setup[8];
+  /**
+   * @brief   Current USB device status.
+   */
+  uint16_t                      status;
+  /**
+   * @brief   Assigned USB address.
+   */
+  uint8_t                       address;
+  /**
+   * @brief   Current USB device configuration.
+   */
+  uint8_t                       configuration;
+#if defined(USB_DRIVER_EXT_FIELDS)
+  USB_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Pointer to the OTG peripheral associated to this driver.
+   */
+  stm32_otg_t                   *otg;
+  /**
+   * @brief   Peripheral-specific parameters.
+   */
+  const stm32_otg_params_t      *otgparams;
+  /**
+   * @brief   Pointer to the next address in the packet memory.
+   */
+  uint32_t                      pmnext;
+  /**
+   * @brief   Mask of TXFIFOs to be filled by the pump thread.
+   */
+  uint32_t                      txpending;
+  /**
+   * @brief   Pointer to the thread when it is sleeping or @p NULL.
+   */
+  thread_reference_t            wait;
+#if defined(_CHIBIOS_RT_)
+  /**
+   * @brief   Pointer to the thread.
+   */
+  thread_reference_t            tr;
+  /**
+   * @brief   Working area for the dedicated data pump thread;
+   */
+  THD_WORKING_AREA(wa_pump, STM32_USB_OTG_THREAD_STACK_SIZE);
+#endif
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the exact size of a receive transaction.
+ * @details The received size can be different from the size specified in
+ *          @p usbStartReceiveI() because the last packet could have a size
+ *          different from the expected one.
+ * @pre     The OUT endpoint must have been configured in transaction mode
+ *          in order to use this function.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ * @return              Received data size.
+ *
+ * @notapi
+ */
+#define usb_lld_get_transaction_size(usbp, ep)                              \
+  ((usbp)->epc[ep]->out_state->rxcnt)
+
+/**
+ * @brief   Connects the USB device.
+ *
+ * @api
+ */
+#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN)
+
+/**
+ * @brief   Disconnect the USB device.
+ *
+ * @api
+ */
+#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_USB_USE_OTG1 && !defined(__DOXYGEN__)
+extern USBDriver USBD1;
+#endif
+
+#if STM32_USB_USE_OTG2 && !defined(__DOXYGEN__)
+extern USBDriver USBD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void usb_lld_init(void);
+  void usb_lld_start(USBDriver *usbp);
+  void usb_lld_stop(USBDriver *usbp);
+  void usb_lld_reset(USBDriver *usbp);
+  void usb_lld_set_address(USBDriver *usbp);
+  void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
+  void usb_lld_disable_endpoints(USBDriver *usbp);
+  usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
+  usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
+  void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
+  void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
+  void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
+  void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
+  void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
+  void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
+  void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
+  void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
+  void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
+  msg_t usb_lld_pump(void *p);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_USB */
+
+#endif /* _USB_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c b/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c
new file mode 100644
index 000000000..094b569d8
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c
@@ -0,0 +1,328 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+   aka barthess.
+ */
+
+/**
+ * @file    STM32/RTCv1/rtc_lld.c
+ * @brief   STM32 RTC subsystem low level driver header.
+ *
+ * @addtogroup RTC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_RTC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief RTC driver identifier.
+ */
+RTCDriver RTCD1;
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Wait for synchronization of RTC registers with APB1 bus.
+ * @details This function must be invoked before trying to read RTC registers
+ *          in the backup domain: DIV, CNT, ALR. CR registers can always
+ *          be read.
+ *
+ * @notapi
+ */
+#define rtc_lld_apb1_sync() {while ((RTC->CRL & RTC_CRL_RSF) == 0);}
+
+/**
+ * @brief   Wait for for previous write operation complete.
+ * @details This function must be invoked before writing to any RTC registers
+ *
+ * @notapi
+ */
+#define rtc_lld_wait_write() {while ((RTC->CRL & RTC_CRL_RTOFF) == 0);}
+
+/**
+ * @brief   Acquires write access to RTC registers.
+ * @details Before writing to the backup domain RTC registers the previous
+ *          write operation must be completed. Use this function before
+ *          writing to PRL, CNT, ALR registers.
+ *
+ * @notapi
+ */
+#define rtc_lld_acquire() {rtc_lld_wait_write(); RTC->CRL |= RTC_CRL_CNF;}
+
+/**
+ * @brief   Releases write access to RTC registers.
+ *
+ * @notapi
+ */
+#define rtc_lld_release() {RTC->CRL &= ~RTC_CRL_CNF;}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   RTC interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(RTC_IRQHandler) {
+  uint16_t flags;
+
+  CH_IRQ_PROLOGUE();
+
+  /* This wait works only when AHB1 bus was previously powered off by any
+     reason (standby, reset, etc). In other cases it does nothing.*/
+  rtc_lld_apb1_sync();
+
+  /* Mask of all enabled and pending sources.*/
+  flags = RTC->CRH & RTC->CRL;
+  RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);
+
+  if (flags & RTC_CRL_SECF)
+    RTCD1.callback(&RTCD1, RTC_EVENT_SECOND);
+
+  if (flags & RTC_CRL_ALRF)
+    RTCD1.callback(&RTCD1, RTC_EVENT_ALARM);
+
+  if (flags & RTC_CRL_OWF)
+    RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW);
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Load value of RTCCLK to prescaler registers.
+ * @note    The pre-scaler must not be set on every reset as RTC clock
+ *          counts are lost when it is set.
+ * @note    This function designed to be called from
+ *          hal_lld_backup_domain_init(). Because there is only place
+ *          where possible to detect BKP domain reset event reliably.
+ *
+ * @notapi
+ */
+void rtc_lld_set_prescaler(void){
+  rtc_lld_acquire();
+  RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F;
+  RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1))      & 0xFFFF);
+  rtc_lld_release();
+}
+
+/**
+ * @brief   Initialize RTC.
+ *
+ * @notapi
+ */
+void rtc_lld_init(void){
+
+  /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock
+     stop. Otherwise its value will not be actual. */
+  RTC->CRL &= ~RTC_CRL_RSF;
+
+  /* Required because access to PRL.*/
+  rtc_lld_apb1_sync();
+
+  /* All interrupts initially disabled.*/
+  rtc_lld_wait_write();
+  RTC->CRH = 0;
+
+  /* Callback initially disabled.*/
+  RTCD1.callback = NULL;
+
+  /* IRQ vector permanently assigned to this driver.*/
+  nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY));
+}
+
+/**
+ * @brief   Set current time.
+ * @note    Fractional part will be silently ignored. There is no possibility
+ *          to change it on STM32F1xx platform.
+ *
+ * @param[in] rtcp      pointer to RTC driver structure
+ * @param[in] timespec  pointer to a @p RTCTime structure
+ *
+ * @notapi
+ */
+void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
+
+  (void)rtcp;
+
+  rtc_lld_acquire();
+  RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16);
+  RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF);
+  rtc_lld_release();
+}
+
+/**
+ * @brief   Get current time.
+ *
+ * @param[in] rtcp      pointer to RTC driver structure
+ * @param[in] timespec  pointer to a @p RTCTime structure
+ *
+ * @notapi
+ */
+void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
+  (void)rtcp;
+
+  uint32_t time_frac;
+
+  /* Required because access to CNT and DIV.*/
+  rtc_lld_apb1_sync();
+
+  /* Loops until two consecutive read returning the same value.*/
+  do {
+    timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL;
+    time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL;
+  } while ((timespec->tv_sec) != (((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL));
+
+  timespec->tv_msec = (uint16_t)(((STM32_RTCCLK - 1 - time_frac) * 1000) /
+                                 STM32_RTCCLK);
+}
+
+/**
+ * @brief   Set alarm time.
+ *
+ * @note      Default value after BKP domain reset is 0xFFFFFFFF
+ *
+ * @param[in] rtcp      pointer to RTC driver structure
+ * @param[in] alarm     alarm identifier
+ * @param[in] alarmspec pointer to a @p RTCAlarm structure
+ *
+ * @notapi
+ */
+void rtc_lld_set_alarm(RTCDriver *rtcp,
+                       rtcalarm_t alarm,
+                       const RTCAlarm *alarmspec) {
+
+  (void)rtcp;
+  (void)alarm;
+
+  rtc_lld_acquire();
+  if (alarmspec != NULL) {
+    RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16);
+    RTC->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF);
+  }
+  else {
+    RTC->ALRH = 0;
+    RTC->ALRL = 0;
+  }
+  rtc_lld_release();
+}
+
+/**
+ * @brief   Get current alarm.
+ * @note    If an alarm has not been set then the returned alarm specification
+ *          is not meaningful.
+ *
+ * @note    Default value after BKP domain reset is 0xFFFFFFFF.
+ *
+ * @param[in] rtcp      pointer to RTC driver structure
+ * @param[in] alarm     alarm identifier
+ * @param[out] alarmspec pointer to a @p RTCAlarm structure
+ *
+ * @notapi
+ */
+void rtc_lld_get_alarm(RTCDriver *rtcp,
+                       rtcalarm_t alarm,
+                       RTCAlarm *alarmspec) {
+
+  (void)rtcp;
+  (void)alarm;
+
+  /* Required because access to ALR.*/
+  rtc_lld_apb1_sync();
+
+  alarmspec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL);
+}
+
+/**
+ * @brief   Enables or disables RTC callbacks.
+ * @details This function enables or disables callbacks, use a @p NULL pointer
+ *          in order to disable a callback.
+ *
+ * @param[in] rtcp      pointer to RTC driver structure
+ * @param[in] callback  callback function pointer or @p NULL
+ *
+ * @notapi
+ */
+void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
+
+  if (callback != NULL) {
+
+    /* IRQ sources enabled only after setting up the callback.*/
+    rtcp->callback = callback;
+
+    rtc_lld_wait_write();
+    RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);
+    RTC->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE;
+  }
+  else {
+    rtc_lld_wait_write();
+    RTC->CRH = 0;
+
+    /* Callback set to NULL only after disabling the IRQ sources.*/
+    rtcp->callback = NULL;
+  }
+}
+
+#include "chrtclib.h"
+
+/**
+ * @brief   Get current time in format suitable for usage in FatFS.
+ *
+ * @param[in] rtcp      pointer to RTC driver structure
+ * @return              FAT time value.
+ *
+ * @api
+ */
+uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) {
+  uint32_t fattime;
+  struct tm timp;
+
+  rtcGetTimeTm(rtcp, &timp);
+
+  fattime  = (timp.tm_sec)       >> 1;
+  fattime |= (timp.tm_min)       << 5;
+  fattime |= (timp.tm_hour)      << 11;
+  fattime |= (timp.tm_mday)      << 16;
+  fattime |= (timp.tm_mon + 1)   << 21;
+  fattime |= (timp.tm_year - 80) << 25;
+
+  return fattime;
+}
+#endif /* HAL_USE_RTC */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.h
index 62b74cc46..62b74cc46 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.h
+++ b/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.h
diff --git a/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c b/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c
new file mode 100644
index 000000000..d30401422
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c
@@ -0,0 +1,321 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+   aka barthess.
+ */
+
+/**
+ * @file    STM32/RTCv2/rtc_lld.c
+ * @brief   STM32L1xx/STM32F2xx/STM32F4xx RTC low level driver.
+ *
+ * @addtogroup RTC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_RTC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief RTC driver identifier.
+ */
+RTCDriver RTCD1;
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+/**
+ * @brief   Wait for synchronization of RTC registers with APB1 bus.
+ * @details This function must be invoked before trying to read RTC registers.
+ *
+ * @notapi
+ */
+#define rtc_lld_apb1_sync() {while ((RTCD1.id_rtc->ISR & RTC_ISR_RSF) == 0);}
+
+/**
+ * @brief   Beginning of configuration procedure.
+ *
+ * @notapi
+ */
+#define rtc_lld_enter_init() {                                                \
+  RTCD1.id_rtc->ISR |= RTC_ISR_INIT;                                          \
+  while ((RTCD1.id_rtc->ISR & RTC_ISR_INITF) == 0)                            \
+    ;                                                                         \
+}
+
+/**
+ * @brief   Finalizing of configuration procedure.
+ *
+ * @notapi
+ */
+#define rtc_lld_exit_init() {RTCD1.id_rtc->ISR &= ~RTC_ISR_INIT;}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Enable access to registers.
+ *
+ * @api
+ */
+void rtc_lld_init(void){
+  RTCD1.id_rtc = RTC;
+
+  /* Asynchronous part of preloader. Set it to maximum value. */
+  uint32_t prediv_a = 0x7F;
+
+  /* Disable write protection. */
+  RTCD1.id_rtc->WPR = 0xCA;
+  RTCD1.id_rtc->WPR = 0x53;
+
+  /* If calendar not init yet. */
+  if (!(RTC->ISR & RTC_ISR_INITS)){
+    rtc_lld_enter_init();
+
+    /* Prescaler register must be written in two SEPARATE writes. */
+    prediv_a = (prediv_a << 16) |
+                (((STM32_RTCCLK / (prediv_a + 1)) - 1) & 0x7FFF);
+    RTCD1.id_rtc->PRER = prediv_a;
+    RTCD1.id_rtc->PRER = prediv_a;
+    rtc_lld_exit_init();
+  }
+}
+
+/**
+ * @brief   Set current time.
+ * @note    Fractional part will be silently ignored. There is no possibility
+ *          to set it on STM32 platform.
+ *
+ * @param[in] rtcp      pointer to RTC driver structure
+ * @param[in] timespec  pointer to a @p RTCTime structure
+ *
+ * @api
+ */
+void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
+  (void)rtcp;
+
+  rtc_lld_enter_init();
+  if (timespec->h12)
+    RTCD1.id_rtc->CR |= RTC_CR_FMT;
+  else
+    RTCD1.id_rtc->CR &= ~RTC_CR_FMT;
+  RTCD1.id_rtc->TR = timespec->tv_time;
+  RTCD1.id_rtc->DR = timespec->tv_date;
+  rtc_lld_exit_init();
+}
+
+/**
+ * @brief   Get current time.
+ *
+ * @param[in] rtcp      pointer to RTC driver structure
+ * @param[out] timespec pointer to a @p RTCTime structure
+ *
+ * @api
+ */
+void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
+  (void)rtcp;
+
+  rtc_lld_apb1_sync();
+
+#if STM32_RTC_HAS_SUBSECONDS
+  timespec->tv_msec =
+      (1000 * ((RTCD1.id_rtc->PRER & 0x7FFF) - RTCD1.id_rtc->SSR)) /
+      ((RTCD1.id_rtc->PRER & 0x7FFF) + 1);
+#endif /* STM32_RTC_HAS_SUBSECONDS */
+  timespec->tv_time = RTCD1.id_rtc->TR;
+  timespec->tv_date = RTCD1.id_rtc->DR;
+}
+
+/**
+ * @brief     Set alarm time.
+ *
+ * @note      Default value after BKP domain reset for both comparators is 0.
+ * @note      Function does not performs any checks of alarm time validity.
+ *
+ * @param[in] rtcp      Pointer to RTC driver structure.
+ * @param[in] alarm     Alarm identifier. Can be 1 or 2.
+ * @param[in] alarmspec Pointer to a @p RTCAlarm structure.
+ *
+ * @api
+ */
+void rtc_lld_set_alarm(RTCDriver *rtcp,
+                       rtcalarm_t alarm,
+                       const RTCAlarm *alarmspec) {
+  if (alarm == 1){
+    if (alarmspec != NULL){
+      rtcp->id_rtc->CR &= ~RTC_CR_ALRAE;
+      while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRAWF))
+        ;
+      rtcp->id_rtc->ALRMAR = alarmspec->tv_datetime;
+      rtcp->id_rtc->CR |= RTC_CR_ALRAE;
+      rtcp->id_rtc->CR |= RTC_CR_ALRAIE;
+    }
+    else {
+      rtcp->id_rtc->CR &= ~RTC_CR_ALRAIE;
+      rtcp->id_rtc->CR &= ~RTC_CR_ALRAE;
+    }
+  }
+  else{
+    if (alarmspec != NULL){
+      rtcp->id_rtc->CR &= ~RTC_CR_ALRBE;
+      while(!(rtcp->id_rtc->ISR & RTC_ISR_ALRBWF))
+        ;
+      rtcp->id_rtc->ALRMBR = alarmspec->tv_datetime;
+      rtcp->id_rtc->CR |= RTC_CR_ALRBE;
+      rtcp->id_rtc->CR |= RTC_CR_ALRBIE;
+    }
+    else {
+      rtcp->id_rtc->CR &= ~RTC_CR_ALRBIE;
+      rtcp->id_rtc->CR &= ~RTC_CR_ALRBE;
+    }
+  }
+}
+
+/**
+ * @brief   Get alarm time.
+ *
+ * @param[in] rtcp       pointer to RTC driver structure
+ * @param[in] alarm      alarm identifier
+ * @param[out] alarmspec pointer to a @p RTCAlarm structure
+ *
+ * @api
+ */
+void rtc_lld_get_alarm(RTCDriver *rtcp,
+                       rtcalarm_t alarm,
+                       RTCAlarm *alarmspec) {
+  if (alarm == 1)
+    alarmspec->tv_datetime = rtcp->id_rtc->ALRMAR;
+  else
+    alarmspec->tv_datetime = rtcp->id_rtc->ALRMBR;
+}
+
+/**
+ * @brief     Sets time of periodic wakeup.
+ *
+ * @note      Default value after BKP domain reset is 0x0000FFFF
+ *
+ * @param[in] rtcp       pointer to RTC driver structure
+ * @param[in] wakeupspec pointer to a @p RTCWakeup structure
+ *
+ * @api
+ */
+void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec){
+  chDbgCheck((wakeupspec->wakeup != 0x30000),
+              "rtc_lld_set_periodic_wakeup, forbidden combination");
+
+  if (wakeupspec != NULL){
+    rtcp->id_rtc->CR &= ~RTC_CR_WUTE;
+    while(!(rtcp->id_rtc->ISR & RTC_ISR_WUTWF))
+      ;
+    rtcp->id_rtc->WUTR = wakeupspec->wakeup & 0xFFFF;
+    rtcp->id_rtc->CR   = (wakeupspec->wakeup >> 16) & 0x7;
+    rtcp->id_rtc->CR |= RTC_CR_WUTIE;
+    rtcp->id_rtc->CR |= RTC_CR_WUTE;
+  }
+  else {
+    rtcp->id_rtc->CR &= ~RTC_CR_WUTIE;
+    rtcp->id_rtc->CR &= ~RTC_CR_WUTE;
+  }
+}
+
+/**
+ * @brief     Gets time of periodic wakeup.
+ *
+ * @note      Default value after BKP domain reset is 0x0000FFFF
+ *
+ * @param[in] rtcp        pointer to RTC driver structure
+ * @param[out] wakeupspec pointer to a @p RTCWakeup structure
+ *
+ * @api
+ */
+void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec){
+  wakeupspec->wakeup  = 0;
+  wakeupspec->wakeup |= rtcp->id_rtc->WUTR;
+  wakeupspec->wakeup |= (((uint32_t)rtcp->id_rtc->CR) & 0x7) << 16;
+}
+
+/**
+ * @brief   Get current time in format suitable for usage in FatFS.
+ *
+ * @param[in] rtcp      pointer to RTC driver structure
+ * @return              FAT time value.
+ *
+ * @api
+ */
+uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp) {
+  uint32_t fattime;
+  RTCTime timespec;
+  uint32_t tv_time;
+  uint32_t tv_date;
+  uint32_t v;
+
+  chSysLock();
+  rtcGetTimeI(rtcp, &timespec);
+  chSysUnlock();
+
+  tv_time = timespec.tv_time;
+  tv_date = timespec.tv_date;
+
+  v =  (tv_time & RTC_TR_SU) >> RTC_TR_SU_OFFSET;
+  v += ((tv_time & RTC_TR_ST) >> RTC_TR_ST_OFFSET) * 10;
+  fattime  = v >> 1;
+
+  v =  (tv_time & RTC_TR_MNU) >> RTC_TR_MNU_OFFSET;
+  v += ((tv_time & RTC_TR_MNT) >> RTC_TR_MNT_OFFSET) * 10;
+  fattime |= v << 5;
+
+  v =  (tv_time & RTC_TR_HU) >> RTC_TR_HU_OFFSET;
+  v += ((tv_time & RTC_TR_HT) >> RTC_TR_HT_OFFSET) * 10;
+  v += 12 * ((tv_time & RTC_TR_PM) >> RTC_TR_PM_OFFSET);
+  fattime |= v << 11;
+
+  v =  (tv_date & RTC_DR_DU) >> RTC_DR_DU_OFFSET;
+  v += ((tv_date & RTC_DR_DT) >> RTC_DR_DT_OFFSET) * 10;
+  fattime |= v << 16;
+
+  v =  (tv_date & RTC_DR_MU) >> RTC_DR_MU_OFFSET;
+  v += ((tv_date & RTC_DR_MT) >> RTC_DR_MT_OFFSET) * 10;
+  fattime |= v << 21;
+
+  v =  (tv_date & RTC_DR_YU) >> RTC_DR_YU_OFFSET;
+  v += ((tv_date & RTC_DR_YT) >> RTC_DR_YT_OFFSET) * 10;
+  v += 2000 - 1900 - 80;
+  fattime |= v << 25;
+
+  return fattime;
+}
+
+#endif /* HAL_USE_RTC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.h b/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.h
new file mode 100644
index 000000000..8e0ce8dd0
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.h
@@ -0,0 +1,206 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+   aka barthess.
+ */
+
+/**
+ * @file    STM32/RTCv2/rtc_lld.h
+ * @brief   STM32L1xx/STM32F2xx/STM32F4xx RTC low level driver header.
+ *
+ * @addtogroup RTC
+ * @{
+ */
+
+#ifndef _RTC_LLD_H_
+#define _RTC_LLD_H_
+
+#if HAL_USE_RTC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Two alarm comparators available on STM32F4x.
+ */
+#define RTC_ALARMS                  2
+
+/**
+ * @brief   Data offsets in RTC date and time registers.
+ */
+#define RTC_TR_PM_OFFSET    22
+#define RTC_TR_HT_OFFSET    20
+#define RTC_TR_HU_OFFSET    16
+#define RTC_TR_MNT_OFFSET   12
+#define RTC_TR_MNU_OFFSET   8
+#define RTC_TR_ST_OFFSET    4
+#define RTC_TR_SU_OFFSET    0
+
+#define RTC_DR_YT_OFFSET    20
+#define RTC_DR_YU_OFFSET    16
+#define RTC_DR_WDU_OFFSET   13
+#define RTC_DR_MT_OFFSET    12
+#define RTC_DR_MU_OFFSET    8
+#define RTC_DR_DT_OFFSET    4
+#define RTC_DR_DU_OFFSET    0
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if HAL_USE_RTC && !STM32_HAS_RTC
+#error "RTC not present in the selected device"
+#endif
+
+#if !(STM32_RTCSEL == STM32_RTCSEL_LSE) &&                                  \
+    !(STM32_RTCSEL == STM32_RTCSEL_LSI) &&                                  \
+    !(STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
+#error "invalid source selected for RTC clock"
+#endif
+
+#if !defined(RTC_USE_INTERRUPTS) || defined(__DOXYGEN__)
+#define RTC_USE_INTERRUPTS                FALSE
+#endif
+
+#if STM32_PCLK1 < (STM32_RTCCLK * 7)
+#error "STM32_PCLK1 frequency is too low to handle RTC without ugly workaround"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an RTC alarm time stamp.
+ */
+typedef struct RTCAlarm RTCAlarm;
+
+/**
+ * @brief   Type of a structure representing an RTC wakeup period.
+ */
+typedef struct RTCWakeup RTCWakeup;
+
+/**
+ * @brief   Type of a structure representing an RTC callbacks config.
+ */
+typedef struct RTCCallbackConfig RTCCallbackConfig;
+
+/**
+ * @brief   Type of an RTC alarm.
+ * @details Meaningful on platforms with more than 1 alarm comparator.
+ */
+typedef uint32_t rtcalarm_t;
+
+/**
+ * @brief   Structure representing an RTC time stamp.
+ */
+struct RTCTime {
+  /**
+   * @brief RTC date register in STM32 BCD format.
+   */
+  uint32_t tv_date;
+  /**
+   * @brief RTC time register in STM32 BCD format.
+   */
+  uint32_t tv_time;
+  /**
+   * @brief Set this to TRUE to use 12 hour notation.
+   */
+  bool_t h12;
+  /**
+   * @brief Fractional part of time.
+   */
+#if STM32_RTC_HAS_SUBSECONDS
+  uint32_t tv_msec;
+#endif
+};
+
+/**
+ * @brief   Structure representing an RTC alarm time stamp.
+ */
+struct RTCAlarm {
+  /**
+   * @brief Date and time of alarm in STM32 BCD.
+   */
+  uint32_t tv_datetime;
+};
+
+/**
+ * @brief   Structure representing an RTC periodic wakeup period.
+ */
+struct RTCWakeup {
+  /**
+   * @brief   RTC WUTR register.
+   * @details Bits [15:0] contain value of WUTR register
+   *          Bits [18:16] contain value of WUCKSEL bits in CR register
+   *
+   * @note    ((WUTR == 0) || (WUCKSEL == 3)) is forbidden combination.
+   */
+  uint32_t wakeup;
+};
+
+/**
+ * @brief   Structure representing an RTC driver.
+ */
+struct RTCDriver{
+  /**
+   * @brief Pointer to the RTC registers block.
+   */
+  RTC_TypeDef               *id_rtc;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern RTCDriver RTCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void rtc_lld_init(void);
+  void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec);
+  void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec);
+  void rtc_lld_set_alarm(RTCDriver *rtcp,
+                         rtcalarm_t alarm,
+                         const RTCAlarm *alarmspec);
+  void rtc_lld_get_alarm(RTCDriver *rtcp,
+                         rtcalarm_t alarm,
+                         RTCAlarm *alarmspec);
+  void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec);
+  void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec);
+  uint32_t rtc_lld_get_time_fat(RTCDriver *rtcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_RTC */
+
+#endif /* _RTC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c b/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c
new file mode 100644
index 000000000..162f138ed
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c
@@ -0,0 +1,455 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    i2s_lld.c
+ * @brief   STM32 I2S subsystem low level driver source.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define I2S2_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM,                        \
+                       STM32_SPI2_RX_DMA_CHN)
+
+#define I2S2_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM,                        \
+                       STM32_SPI2_TX_DMA_CHN)
+
+#define I2S3_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_RX_DMA_STREAM,                        \
+                       STM32_SPI3_RX_DMA_CHN)
+
+#define I2S3_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM,                        \
+                       STM32_SPI3_TX_DMA_CHN)
+
+/*
+ * Static I2S settings for I2S2.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG                 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG                 SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG                 SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG                 (SPI_I2SCFGR_I2SCFG_1 |         \
+                                             SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
+
+/*
+ * Static I2S settings for I2S3.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG                 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG                 SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG                 SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+#define STM32_I2S3_CFGR_CFG                 (SPI_I2SCFGR_I2SCFG_1 |         \
+                                             SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SP3_MODE) */
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief I2S2 driver identifier.*/
+#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__)
+I2SDriver I2SD2;
+#endif
+
+/** @brief I2S3 driver identifier.*/
+#if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__)
+I2SDriver I2SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) ||                            \
+    STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
+/**
+ * @brief   Shared end-of-rx service routine.
+ *
+ * @param[in] i2sp      pointer to the @p I2SDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
+
+  (void)i2sp;
+
+  /* DMA errors handling.*/
+#if defined(STM32_I2S_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_I2S_DMA_ERROR_HOOK(i2sp);
+  }
+#endif
+
+  /* Callbacks handling, note it is portable code defined in the high
+     level driver.*/
+  if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+    /* Transfer complete processing.*/
+    _i2s_isr_full_code(i2sp);
+  }
+  else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+    /* Half transfer processing.*/
+    _i2s_isr_half_code(i2sp);
+  }
+}
+#endif
+
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) ||                            \
+    STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
+/**
+ * @brief   Shared end-of-tx service routine.
+ *
+ * @param[in] i2sp      pointer to the @p I2SDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
+
+  (void)i2sp;
+
+  /* DMA errors handling.*/
+#if defined(STM32_I2S_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_I2S_DMA_ERROR_HOOK(i2sp);
+  }
+#endif
+
+  /* Callbacks handling, note it is portable code defined in the high
+     level driver.*/
+  if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+    /* Transfer complete processing.*/
+    _i2s_isr_full_code(i2sp);
+  }
+  else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+    /* Half transfer processing.*/
+    _i2s_isr_half_code(i2sp);
+  }
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level I2S driver initialization.
+ *
+ * @notapi
+ */
+void i2s_lld_init(void) {
+
+#if STM32_I2S_USE_SPI2
+  i2sObjectInit(&I2SD2);
+  I2SD2.spi       = SPI2;
+  I2SD2.cfg       = STM32_I2S2_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+  I2SD2.dmarx     = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM);
+  I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
+                    STM32_DMA_CR_PSIZE_HWORD |
+                    STM32_DMA_CR_MSIZE_HWORD |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_MINC |
+                    STM32_DMA_CR_CIRC |
+                    STM32_DMA_CR_HTIE |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#else
+  I2SD2.dmarx     = NULL;
+  I2SD2.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+  I2SD2.dmatx     = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM);
+  I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
+                    STM32_DMA_CR_PSIZE_HWORD |
+                    STM32_DMA_CR_MSIZE_HWORD |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_MINC |
+                    STM32_DMA_CR_CIRC |
+                    STM32_DMA_CR_HTIE |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#else
+  I2SD2.dmatx     = NULL;
+  I2SD2.txdmamode = 0;
+#endif
+#endif
+
+#if STM32_I2S_USE_SPI3
+  i2sObjectInit(&I2SD3);
+  I2SD3.spi       = SPI3;
+  I2SD3.cfg       = STM32_I2S3_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+  I2SD3.dmarx     = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM);
+  I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
+                    STM32_DMA_CR_PSIZE_HWORD |
+                    STM32_DMA_CR_MSIZE_HWORD |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_MINC |
+                    STM32_DMA_CR_CIRC |
+                    STM32_DMA_CR_HTIE |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#else
+  I2SD3.dmarx     = NULL;
+  I2SD3.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+  I2SD3.dmatx     = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM);
+  I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
+                    STM32_DMA_CR_PSIZE_HWORD |
+                    STM32_DMA_CR_MSIZE_HWORD |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_MINC |
+                    STM32_DMA_CR_CIRC |
+                    STM32_DMA_CR_HTIE |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#else
+  I2SD3.dmatx     = NULL;
+  I2SD3.txdmamode = 0;
+#endif
+#endif
+}
+
+/**
+ * @brief   Configures and activates the I2S peripheral.
+ *
+ * @param[in] i2sp      pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start(I2SDriver *i2sp) {
+
+  /* If in stopped state then enables the SPI and DMA clocks.*/
+  if (i2sp->state == I2S_STOP) {
+
+#if STM32_I2S_USE_SPI2
+    if (&I2SD2 == i2sp) {
+      bool b;
+
+      /* Enabling I2S unit clock.*/
+      rccEnableSPI2(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+      b = dmaStreamAllocate(i2sp->dmarx,
+                            STM32_I2S_SPI2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+                            (void *)i2sp);
+      osalDbgAssert(!b, "stream already allocated");
+
+      /* CRs settings are done here because those never changes until
+          the driver is stopped.*/
+      i2sp->spi->CR1 = 0;
+      i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+      b = dmaStreamAllocate(i2sp->dmatx,
+                            STM32_I2S_SPI2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+                            (void *)i2sp);
+      osalDbgAssert(!b, "stream already allocated");
+
+      /* CRs settings are done here because those never changes until
+          the driver is stopped.*/
+      i2sp->spi->CR1 = 0;
+      i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+    }
+#endif
+#if STM32_I2S_USE_SPI3
+    if (&I2SD3 == i2sp) {
+      bool b;
+
+      /* Enabling I2S unit clock.*/
+      rccEnableSPI3(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
+      b = dmaStreamAllocate(i2sp->dmarx,
+                            STM32_I2S_SPI3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+                            (void *)i2sp);
+      osalDbgAssert(!b, "stream already allocated");
+
+      i2sp->spi->CR1 = 0;
+      i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+      b = dmaStreamAllocate(i2sp->dmatx,
+                            STM32_I2S_SPI3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+                            (void *)i2sp);
+      osalDbgAssert(!b, "stream already allocated");
+
+      i2sp->spi->CR1 = 0;
+      i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+    }
+#endif
+
+    if (NULL != i2sp->dmarx) {
+      dmaStreamSetMode(i2sp->dmarx, i2sp->rxdmamode);
+      dmaStreamSetPeripheral(i2sp->dmarx, &i2sp->spi->DR);
+    }
+    if (NULL != i2sp->dmatx) {
+      dmaStreamSetMode(i2sp->dmatx, i2sp->txdmamode);
+      dmaStreamSetPeripheral(i2sp->dmatx, &i2sp->spi->DR);
+    }
+  }
+
+  /* I2S (re)configuration.*/
+  i2sp->spi->I2SPR   = i2sp->config->i2spr;
+  i2sp->spi->I2SCFGR = i2sp->config->i2scfgr | i2sp->cfg | SPI_I2SCFGR_I2SMOD;
+}
+
+/**
+ * @brief   Deactivates the I2S peripheral.
+ *
+ * @param[in] i2sp      pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop(I2SDriver *i2sp) {
+
+  /* If in ready state then disables the SPI clock.*/
+  if (i2sp->state == I2S_READY) {
+
+    /* SPI disable.*/
+    i2sp->spi->CR2 = 0;
+    if (NULL != i2sp->dmarx)
+      dmaStreamRelease(i2sp->dmarx);
+    if (NULL != i2sp->dmatx)
+      dmaStreamRelease(i2sp->dmatx);
+
+#if STM32_I2S_USE_SPI2
+    if (&I2SD2 == i2sp)
+      rccDisableSPI2(FALSE);
+#endif
+#if STM32_I2S_USE_SPI3
+    if (&I2SD3 == i2sp)
+      rccDisableSPI3(FALSE);
+#endif
+  }
+}
+
+/**
+ * @brief   Starts a I2S data exchange.
+ *
+ * @param[in] i2sp      pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start_exchange(I2SDriver *i2sp) {
+  size_t size = i2sp->config->size;
+
+  /* In 32 bit modes the DMA has to perform double operations because fetches
+     are always performed using 16 bit accesses.*/
+  if ((i2sp->config->i2scfgr & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) != 0)
+    size *= 2;
+
+  /* RX DMA setup.*/
+  if (NULL != i2sp->dmarx) {
+    dmaStreamSetMemory0(i2sp->dmarx, i2sp->config->rx_buffer);
+    dmaStreamSetTransactionSize(i2sp->dmarx, size);
+    dmaStreamEnable(i2sp->dmarx);
+  }
+
+  /* TX DMA setup.*/
+  if (NULL != i2sp->dmatx) {
+    dmaStreamSetMemory0(i2sp->dmatx, i2sp->config->tx_buffer);
+    dmaStreamSetTransactionSize(i2sp->dmatx, size);
+    dmaStreamEnable(i2sp->dmatx);
+  }
+
+  /* Starting transfer.*/
+  i2sp->spi->I2SCFGR |= SPI_I2SCFGR_I2SE;
+}
+
+/**
+ * @brief   Stops the ongoing data exchange.
+ * @details The ongoing data exchange, if any, is stopped, if the driver
+ *          was not active the function does nothing.
+ *
+ * @param[in] i2sp      pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop_exchange(I2SDriver *i2sp) {
+
+  /* Stop TX DMA, if enabled.*/
+  if (NULL != i2sp->dmatx) {
+    dmaStreamDisable(i2sp->dmatx);
+
+    /* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory
+       to wait for TXE = 1 and BSY = 0.*/
+    while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE)
+      ;
+  }
+
+  /* Stop SPI/I2S peripheral.*/
+  i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
+
+  /* Stop RX DMA, if enabled.*/
+  if (NULL != i2sp->dmarx)
+    dmaStreamDisable(i2sp->dmarx);
+}
+
+#endif /* HAL_USE_I2S */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h b/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h
new file mode 100644
index 000000000..595843d33
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h
@@ -0,0 +1,351 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    i2s_lld.h
+ * @brief   STM32 I2S subsystem low level driver header.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#ifndef _I2S_LLD_H_
+#define _I2S_LLD_H_
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Static I2S modes
+ * @{
+ */
+#define STM32_I2S_MODE_SLAVE                0
+#define STM32_I2S_MODE_MASTER               1
+#define STM32_I2S_MODE_RX                   2
+#define STM32_I2S_MODE_TX                   4
+#define STM32_I2S_MODE_RXTX                 (STM32_I2S_MODE_RX |            \
+                                             STM32_I2S_MODE_TX)
+/** @} */
+
+/**
+ * @name    Mode checks
+ * @{
+ */
+#define STM32_I2S_IS_MASTER(mode)           ((mode) & STM32_I2S_MODE_MASTER)
+#define STM32_I2S_RX_ENABLED(mode)          ((mode) & STM32_I2S_MODE_RX)
+#define STM32_I2S_TX_ENABLED(mode)          ((mode) & STM32_I2S_MODE_TX)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   I2S2 driver enable switch.
+ * @details If set to @p TRUE the support for I2S2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI2) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI2                  FALSE
+#endif
+
+/**
+ * @brief   I2S3 driver enable switch.
+ * @details If set to @p TRUE the support for I2S3 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI3) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI3                  FALSE
+#endif
+
+/**
+ * @brief   I2S2 mode.
+ */
+#if !defined(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_MODE                 (STM32_I2S_MODE_MASTER |        \
+                                             STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief   I2S3 mode.
+ */
+#if !defined(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI3_MODE                 (STM32_I2S_MODE_MASTER |        \
+                                             STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief   I2S2 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   I2S3 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI3_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   I2S2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   I2S3 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI3_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   I2S DMA error hook.
+ */
+#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) &&                            \
+    STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#error "I2S2 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) &&                            \
+    STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
+#error "I2S3 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2
+#error "SPI2 not present in the selected device"
+#endif
+
+#if STM32_I2S_USE_SPI3 && !STM32_HAS_SPI3
+#error "SPI3 not present in the selected device"
+#endif
+
+#if !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3
+#error "I2S driver activated but no SPI peripheral assigned"
+#endif
+
+#if STM32_I2S_USE_SPI2 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2S_SPI2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI2"
+#endif
+
+#if STM32_I2S_USE_SPI3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2S_SPI3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI3"
+#endif
+
+#if STM32_I2S_USE_SPI2 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI2"
+#endif
+
+#if STM32_I2S_USE_SPI3 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI3"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+   reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_I2S_USE_SPI2 && (!defined(STM32_I2S_SPI2_RX_DMA_STREAM) ||        \
+                           !defined(STM32_I2S_SPI2_TX_DMA_STREAM))
+#error "SPI2 DMA streams not defined"
+#endif
+
+#if STM32_I2S_USE_SPI3 && (!defined(STM32_I2S_SPI3_RX_DMA_STREAM) ||        \
+                           !defined(STM32_I2S_SPI3_TX_DMA_STREAM))
+#error "SPI3 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_I2S_USE_SPI2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 RX"
+#endif
+
+#if STM32_I2S_USE_SPI2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 TX"
+#endif
+
+#if STM32_I2S_USE_SPI3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 RX"
+#endif
+
+#if STM32_I2S_USE_SPI3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an I2S driver.
+ */
+typedef struct I2SDriver I2SDriver;
+
+/**
+ * @brief   I2S notification callback type.
+ *
+ * @param[in] i2sp      pointer to the @p I2SDriver object
+ * @param[in] offset    offset in buffers of the data to read/write
+ * @param[in] n         number of samples to read/write
+ */
+typedef void (*i2scallback_t)(I2SDriver *i2sp, size_t offset, size_t n);
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief   Transmission buffer pointer.
+   * @note    Can be @p NULL if TX is not required.
+   */
+  const void                *tx_buffer;
+  /**
+   * @brief   Receive buffer pointer.
+   * @note    Can be @p NULL if RX is not required.
+   */
+  void                      *rx_buffer;
+  /**
+   * @brief   TX and RX buffers size as number of samples.
+   */
+  size_t                    size;
+  /**
+   * @brief   Callback function called during streaming.
+   */
+  i2scallback_t             end_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Configuration of the I2SCFGR register.
+   * @details See the STM32 reference manual, this register is used for
+   *          the I2S configuration, the following bits must not be
+   *          specified because handled directly by the driver:
+   *          - I2SMOD
+   *          - I2SE
+   *          - I2SCFG
+   *          .
+   */
+  int16_t                   i2scfgr;
+  /**
+   * @brief   Configuration of the I2SPR register.
+   * @details See the STM32 reference manual, this register is used for
+   *          the I2S clock setup.
+   */
+  int16_t                   i2spr;
+} I2SConfig;
+
+/**
+ * @brief   Structure representing an I2S driver.
+ */
+struct I2SDriver {
+  /**
+   * @brief   Driver state.
+   */
+  i2sstate_t                state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const I2SConfig           *config;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Pointer to the SPIx registers block.
+   */
+  SPI_TypeDef               *spi;
+  /**
+   * @brief   Calculated part of the I2SCFGR register.
+   */
+  uint16_t                  cfg;
+  /**
+   * @brief   Receive DMA stream or @p NULL.
+   */
+  const stm32_dma_stream_t  *dmarx;
+  /**
+   * @brief   Transmit DMA stream or @p NULL.
+   */
+  const stm32_dma_stream_t  *dmatx;
+  /**
+   * @brief   RX DMA mode bit mask.
+   */
+  uint32_t                  rxdmamode;
+  /**
+   * @brief   TX DMA mode bit mask.
+   */
+  uint32_t                  txdmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_I2S_USE_SPI2 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD2;
+#endif
+
+#if STM32_I2S_USE_SPI3 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void i2s_lld_init(void);
+  void i2s_lld_start(I2SDriver *i2sp);
+  void i2s_lld_stop(I2SDriver *i2sp);
+  void i2s_lld_start_exchange(I2SDriver *i2sp);
+  void i2s_lld_stop_exchange(I2SDriver *i2sp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2S */
+
+#endif /* _I2S_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c b/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c
new file mode 100644
index 000000000..048ad5743
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c
@@ -0,0 +1,635 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/SPIv1/spi_lld.c
+ * @brief   STM32 SPI subsystem low level driver source.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define SPI1_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM,                        \
+                       STM32_SPI1_RX_DMA_CHN)
+
+#define SPI1_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM,                        \
+                       STM32_SPI1_TX_DMA_CHN)
+
+#define SPI2_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM,                        \
+                       STM32_SPI2_RX_DMA_CHN)
+
+#define SPI2_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM,                        \
+                       STM32_SPI2_TX_DMA_CHN)
+
+#define SPI3_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM,                        \
+                       STM32_SPI3_RX_DMA_CHN)
+
+#define SPI3_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM,                        \
+                       STM32_SPI3_TX_DMA_CHN)
+
+#define SPI4_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM,                        \
+                       STM32_SPI4_RX_DMA_CHN)
+
+#define SPI4_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM,                        \
+                       STM32_SPI4_TX_DMA_CHN)
+
+#define SPI5_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM,                        \
+                       STM32_SPI5_RX_DMA_CHN)
+
+#define SPI5_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM,                        \
+                       STM32_SPI5_TX_DMA_CHN)
+
+#define SPI6_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM,                        \
+                       STM32_SPI6_RX_DMA_CHN)
+
+#define SPI6_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM,                        \
+                       STM32_SPI6_TX_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief SPI1 driver identifier.*/
+#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
+SPIDriver SPID1;
+#endif
+
+/** @brief SPI2 driver identifier.*/
+#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)
+SPIDriver SPID2;
+#endif
+
+/** @brief SPI3 driver identifier.*/
+#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)
+SPIDriver SPID3;
+#endif
+
+/** @brief SPI4 driver identifier.*/
+#if STM32_SPI_USE_SPI4 || defined(__DOXYGEN__)
+SPIDriver SPID4;
+#endif
+
+/** @brief SPI5 driver identifier.*/
+#if STM32_SPI_USE_SPI5 || defined(__DOXYGEN__)
+SPIDriver SPID5;
+#endif
+
+/** @brief SPI6 driver identifier.*/
+#if STM32_SPI_USE_SPI6 || defined(__DOXYGEN__)
+SPIDriver SPID6;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+static uint16_t dummytx;
+static uint16_t dummyrx;
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared end-of-rx service routine.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(STM32_SPI_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_SPI_DMA_ERROR_HOOK(spip);
+  }
+#else
+  (void)flags;
+#endif
+
+  /* Stop everything.*/
+  dmaStreamDisable(spip->dmatx);
+  dmaStreamDisable(spip->dmarx);
+
+  /* Portable SPI ISR code defined in the high level driver, note, it is
+     a macro.*/
+  _spi_isr_code(spip);
+}
+
+/**
+ * @brief   Shared end-of-tx service routine.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(STM32_SPI_DMA_ERROR_HOOK)
+  (void)spip;
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_SPI_DMA_ERROR_HOOK(spip);
+  }
+#else
+  (void)spip;
+  (void)flags;
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level SPI driver initialization.
+ *
+ * @notapi
+ */
+void spi_lld_init(void) {
+
+  dummytx = 0xFFFF;
+
+#if STM32_SPI_USE_SPI1
+  spiObjectInit(&SPID1);
+  SPID1.spi       = SPI1;
+  SPID1.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
+  SPID1.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
+  SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+  SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_SPI_USE_SPI2
+  spiObjectInit(&SPID2);
+  SPID2.spi       = SPI2;
+  SPID2.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
+  SPID2.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
+  SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+  SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_SPI_USE_SPI3
+  spiObjectInit(&SPID3);
+  SPID3.spi       = SPI3;
+  SPID3.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
+  SPID3.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
+  SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+  SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_SPI_USE_SPI4
+  spiObjectInit(&SPID4);
+  SPID4.spi       = SPI4;
+  SPID4.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM);
+  SPID4.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM);
+  SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+  SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_SPI_USE_SPI5
+  spiObjectInit(&SPID5);
+  SPID5.spi       = SPI5;
+  SPID5.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM);
+  SPID5.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM);
+  SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+  SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_SPI_USE_SPI6
+  spiObjectInit(&SPID6);
+  SPID6.spi       = SPI6;
+  SPID6.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM);
+  SPID6.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM);
+  SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+  SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the SPI peripheral.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_start(SPIDriver *spip) {
+
+  /* If in stopped state then enables the SPI and DMA clocks.*/
+  if (spip->state == SPI_STOP) {
+#if STM32_SPI_USE_SPI1
+    if (&SPID1 == spip) {
+      bool b;
+      b = dmaStreamAllocate(spip->dmarx,
+                            STM32_SPI_SPI1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(spip->dmatx,
+                            STM32_SPI_SPI1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableSPI1(FALSE);
+    }
+#endif
+#if STM32_SPI_USE_SPI2
+    if (&SPID2 == spip) {
+      bool b;
+      b = dmaStreamAllocate(spip->dmarx,
+                            STM32_SPI_SPI2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(spip->dmatx,
+                            STM32_SPI_SPI2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableSPI2(FALSE);
+    }
+#endif
+#if STM32_SPI_USE_SPI3
+    if (&SPID3 == spip) {
+      bool b;
+      b = dmaStreamAllocate(spip->dmarx,
+                            STM32_SPI_SPI3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(spip->dmatx,
+                            STM32_SPI_SPI3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableSPI3(FALSE);
+    }
+#endif
+#if STM32_SPI_USE_SPI4
+    if (&SPID4 == spip) {
+      bool b;
+      b = dmaStreamAllocate(spip->dmarx,
+                            STM32_SPI_SPI4_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+                            (void *)spip);
+      chDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(spip->dmatx,
+                            STM32_SPI_SPI4_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+                            (void *)spip);
+      chDbgAssert(!b, "stream already allocated");
+      rccEnableSPI4(FALSE);
+    }
+#endif
+#if STM32_SPI_USE_SPI5
+    if (&SPID5 == spip) {
+      bool b;
+      b = dmaStreamAllocate(spip->dmarx,
+                            STM32_SPI_SPI5_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+                            (void *)spip);
+      chDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(spip->dmatx,
+                            STM32_SPI_SPI5_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+                            (void *)spip);
+      chDbgAssert(!b, "stream already allocated");
+      rccEnableSPI5(FALSE);
+    }
+#endif
+#if STM32_SPI_USE_SPI6
+    if (&SPID6 == spip) {
+      bool b;
+      b = dmaStreamAllocate(spip->dmarx,
+                            STM32_SPI_SPI6_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+                            (void *)spip);
+      chDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(spip->dmatx,
+                            STM32_SPI_SPI6_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+                            (void *)spip);
+      chDbgAssert(!b, "stream already allocated");
+      rccEnableSPI6(FALSE);
+    }
+#endif
+
+    /* DMA setup.*/
+    dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR);
+    dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR);
+  }
+
+  /* Configuration-specific DMA setup.*/
+  if ((spip->config->cr1 & SPI_CR1_DFF) == 0) {
+    /* Frame width is 8 bits or smaller.*/
+    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
+                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
+    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
+                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
+  }
+  else {
+    /* Frame width is larger than 8 bits.*/
+    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
+                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
+                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+  }
+  /* SPI setup and enable.*/
+  spip->spi->CR1  = 0;
+  spip->spi->CR1  = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
+                    SPI_CR1_SSI;
+  spip->spi->CR2  = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
+  spip->spi->CR1 |= SPI_CR1_SPE;
+}
+
+/**
+ * @brief   Deactivates the SPI peripheral.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_stop(SPIDriver *spip) {
+
+  /* If in ready state then disables the SPI clock.*/
+  if (spip->state == SPI_READY) {
+
+    /* SPI disable.*/
+    spip->spi->CR1 = 0;
+    spip->spi->CR2 = 0;
+    dmaStreamRelease(spip->dmarx);
+    dmaStreamRelease(spip->dmatx);
+
+#if STM32_SPI_USE_SPI1
+    if (&SPID1 == spip)
+      rccDisableSPI1(FALSE);
+#endif
+#if STM32_SPI_USE_SPI2
+    if (&SPID2 == spip)
+      rccDisableSPI2(FALSE);
+#endif
+#if STM32_SPI_USE_SPI3
+    if (&SPID3 == spip)
+      rccDisableSPI3(FALSE);
+#endif
+#if STM32_SPI_USE_SPI4
+    if (&SPID4 == spip)
+      rccDisableSPI4(FALSE);
+#endif
+#if STM32_SPI_USE_SPI5
+    if (&SPID5 == spip)
+      rccDisableSPI5(FALSE);
+#endif
+#if STM32_SPI_USE_SPI6
+    if (&SPID6 == spip)
+      rccDisableSPI6(FALSE);
+#endif
+  }
+}
+
+/**
+ * @brief   Asserts the slave select signal and prepares for transfers.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_select(SPIDriver *spip) {
+
+  palClearPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief   Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_unselect(SPIDriver *spip) {
+
+  palSetPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief   Ignores data on the SPI bus.
+ * @details This asynchronous function starts the transmission of a series of
+ *          idle words on the SPI bus and ignores the received data.
+ * @post    At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to be ignored
+ *
+ * @notapi
+ */
+void spi_lld_ignore(SPIDriver *spip, size_t n) {
+
+  dmaStreamSetMemory0(spip->dmarx, &dummyrx);
+  dmaStreamSetTransactionSize(spip->dmarx, n);
+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
+
+  dmaStreamSetMemory0(spip->dmatx, &dummytx);
+  dmaStreamSetTransactionSize(spip->dmatx, n);
+  dmaStreamSetMode(spip->dmatx, spip->txdmamode);
+
+  dmaStreamEnable(spip->dmarx);
+  dmaStreamEnable(spip->dmatx);
+}
+
+/**
+ * @brief   Exchanges data on the SPI bus.
+ * @details This asynchronous function starts a simultaneous transmit/receive
+ *          operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to be exchanged
+ * @param[in] txbuf     the pointer to the transmit buffer
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_exchange(SPIDriver *spip, size_t n,
+                      const void *txbuf, void *rxbuf) {
+
+  dmaStreamSetMemory0(spip->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(spip->dmarx, n);
+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
+
+  dmaStreamSetMemory0(spip->dmatx, txbuf);
+  dmaStreamSetTransactionSize(spip->dmatx, n);
+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
+
+  dmaStreamEnable(spip->dmarx);
+  dmaStreamEnable(spip->dmatx);
+}
+
+/**
+ * @brief   Sends data over the SPI bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to send
+ * @param[in] txbuf     the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
+
+  dmaStreamSetMemory0(spip->dmarx, &dummyrx);
+  dmaStreamSetTransactionSize(spip->dmarx, n);
+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
+
+  dmaStreamSetMemory0(spip->dmatx, txbuf);
+  dmaStreamSetTransactionSize(spip->dmatx, n);
+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
+
+  dmaStreamEnable(spip->dmarx);
+  dmaStreamEnable(spip->dmatx);
+}
+
+/**
+ * @brief   Receives data from the SPI bus.
+ * @details This asynchronous function starts a receive operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to receive
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
+
+  dmaStreamSetMemory0(spip->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(spip->dmarx, n);
+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
+
+  dmaStreamSetMemory0(spip->dmatx, &dummytx);
+  dmaStreamSetTransactionSize(spip->dmatx, n);
+  dmaStreamSetMode(spip->dmatx, spip->txdmamode);
+
+  dmaStreamEnable(spip->dmarx);
+  dmaStreamEnable(spip->dmatx);
+}
+
+/**
+ * @brief   Exchanges one frame using a polled wait.
+ * @details This synchronous function exchanges one frame using a polled
+ *          synchronization method. This function is useful when exchanging
+ *          small amount of data on high speed channels, usually in this
+ *          situation is much more efficient just wait for completion using
+ *          polling than suspending the thread waiting for an interrupt.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] frame     the data frame to send over the SPI bus
+ * @return              The received data frame from the SPI bus.
+ */
+uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
+
+  spip->spi->DR = frame;
+  while ((spip->spi->SR & SPI_SR_RXNE) == 0)
+    ;
+  return spip->spi->DR;
+}
+
+#endif /* HAL_USE_SPI */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/SPIv1/spi_lld.h b/os/hal/ports/STM32/LLD/SPIv1/spi_lld.h
new file mode 100644
index 000000000..011f83685
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/SPIv1/spi_lld.h
@@ -0,0 +1,543 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/SPIv1/spi_lld.h
+ * @brief   STM32 SPI subsystem low level driver header.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef _SPI_LLD_H_
+#define _SPI_LLD_H_
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   SPI1 driver enable switch.
+ * @details If set to @p TRUE the support for SPI1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI1                  FALSE
+#endif
+
+/**
+ * @brief   SPI2 driver enable switch.
+ * @details If set to @p TRUE the support for SPI2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI2                  FALSE
+#endif
+
+/**
+ * @brief   SPI3 driver enable switch.
+ * @details If set to @p TRUE the support for SPI3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI3                  FALSE
+#endif
+
+/**
+ * @brief   SPI4 driver enable switch.
+ * @details If set to @p TRUE the support for SPI4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI4                  FALSE
+#endif
+
+/**
+ * @brief   SPI5 driver enable switch.
+ * @details If set to @p TRUE the support for SPI5 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI5                  FALSE
+#endif
+
+/**
+ * @brief   SPI6 driver enable switch.
+ * @details If set to @p TRUE the support for SPI6 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI6                  FALSE
+#endif
+
+/**
+ * @brief   SPI1 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI1_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI2 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI2_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI3 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI3_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI4 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI4_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI5 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI5_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI6 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI6_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI1 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI1_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   SPI2 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI2_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   SPI3 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI3_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   SPI4 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI4_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   SPI5 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI5_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   SPI6 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI6_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   SPI DMA error hook.
+ */
+#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
+#error "SPI2 not present in the selected device"
+#endif
+
+#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
+#error "SPI3 not present in the selected device"
+#endif
+
+#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4
+#error "SPI4 not present in the selected device"
+#endif
+
+#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5
+#error "SPI5 not present in the selected device"
+#endif
+
+#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6
+#error "SPI6 not present in the selected device"
+#endif
+
+#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \
+    !STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6
+#error "SPI driver activated but no SPI peripheral assigned"
+#endif
+
+#if STM32_SPI_USE_SPI1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
+#if STM32_SPI_USE_SPI2 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI2"
+#endif
+
+#if STM32_SPI_USE_SPI3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI3"
+#endif
+
+#if STM32_SPI_USE_SPI4 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI4"
+#endif
+
+#if STM32_SPI_USE_SPI5 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI5"
+#endif
+
+#if STM32_SPI_USE_SPI6 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI6"
+#endif
+
+#if STM32_SPI_USE_SPI1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI1"
+#endif
+
+#if STM32_SPI_USE_SPI2 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI2"
+#endif
+
+#if STM32_SPI_USE_SPI3 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI3"
+#endif
+
+#if STM32_SPI_USE_SPI4 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI4"
+#endif
+
+#if STM32_SPI_USE_SPI5 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI5"
+#endif
+
+#if STM32_SPI_USE_SPI6 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI6"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+   reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) ||        \
+                           !defined(STM32_SPI_SPI1_TX_DMA_STREAM))
+#error "SPI1 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) ||        \
+                           !defined(STM32_SPI_SPI2_TX_DMA_STREAM))
+#error "SPI2 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) ||        \
+                           !defined(STM32_SPI_SPI3_TX_DMA_STREAM))
+#error "SPI3 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) ||        \
+                           !defined(STM32_SPI_SPI4_TX_DMA_STREAM))
+#error "SPI4 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) ||        \
+                           !defined(STM32_SPI_SPI5_TX_DMA_STREAM))
+#error "SPI5 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) ||        \
+                           !defined(STM32_SPI_SPI6_TX_DMA_STREAM))
+#error "SPI6 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_SPI_USE_SPI1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 RX"
+#endif
+
+#if STM32_SPI_USE_SPI1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 TX"
+#endif
+
+#if STM32_SPI_USE_SPI2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 RX"
+#endif
+
+#if STM32_SPI_USE_SPI2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 TX"
+#endif
+
+#if STM32_SPI_USE_SPI3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 RX"
+#endif
+
+#if STM32_SPI_USE_SPI3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 TX"
+#endif
+
+#if STM32_SPI_USE_SPI4 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI4 RX"
+#endif
+
+#if STM32_SPI_USE_SPI4 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI4 TX"
+#endif
+
+#if STM32_SPI_USE_SPI5 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI5 RX"
+#endif
+
+#if STM32_SPI_USE_SPI5 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI5 TX"
+#endif
+
+#if STM32_SPI_USE_SPI6 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI6 RX"
+#endif
+
+#if STM32_SPI_USE_SPI6 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI6 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an SPI driver.
+ */
+typedef struct SPIDriver SPIDriver;
+
+/**
+ * @brief   SPI notification callback type.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object triggering the
+ *                      callback
+ */
+typedef void (*spicallback_t)(SPIDriver *spip);
+
+/**
+ * @brief   Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief Operation complete callback or @p NULL.
+   */
+  spicallback_t             end_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief The chip select line port.
+   */
+  ioportid_t                ssport;
+  /**
+   * @brief The chip select line pad number.
+   */
+  uint16_t                  sspad;
+  /**
+   * @brief SPI initialization data.
+   */
+  uint16_t                  cr1;
+} SPIConfig;
+
+/**
+ * @brief   Structure representing a SPI driver.
+ */
+struct SPIDriver {
+  /**
+   * @brief Driver state.
+   */
+  spistate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const SPIConfig           *config;
+#if SPI_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif /* SPI_USE_WAIT */
+#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the bus.
+   */
+  mutex_t                   mutex;
+#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#if defined(SPI_DRIVER_EXT_FIELDS)
+  SPI_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the SPIx registers block.
+   */
+  SPI_TypeDef               *spi;
+  /**
+   * @brief Receive DMA stream.
+   */
+  const stm32_dma_stream_t  *dmarx;
+  /**
+   * @brief Transmit DMA stream.
+   */
+  const stm32_dma_stream_t  *dmatx;
+  /**
+   * @brief RX DMA mode bit mask.
+   */
+  uint32_t                  rxdmamode;
+  /**
+   * @brief TX DMA mode bit mask.
+   */
+  uint32_t                  txdmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
+extern SPIDriver SPID1;
+#endif
+
+#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
+extern SPIDriver SPID2;
+#endif
+
+#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
+extern SPIDriver SPID3;
+#endif
+
+#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__)
+extern SPIDriver SPID4;
+#endif
+
+#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__)
+extern SPIDriver SPID5;
+#endif
+
+#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__)
+extern SPIDriver SPID6;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void spi_lld_init(void);
+  void spi_lld_start(SPIDriver *spip);
+  void spi_lld_stop(SPIDriver *spip);
+  void spi_lld_select(SPIDriver *spip);
+  void spi_lld_unselect(SPIDriver *spip);
+  void spi_lld_ignore(SPIDriver *spip, size_t n);
+  void spi_lld_exchange(SPIDriver *spip, size_t n,
+                        const void *txbuf, void *rxbuf);
+  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
+  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
+  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SPI */
+
+#endif /* _SPI_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c b/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c
new file mode 100644
index 000000000..e21f80074
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c
@@ -0,0 +1,501 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/SPIv2/spi_lld.c
+ * @brief   STM32 SPI subsystem low level driver source.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define SPI1_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM,                        \
+                       STM32_SPI1_RX_DMA_CHN)
+
+#define SPI1_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM,                        \
+                       STM32_SPI1_TX_DMA_CHN)
+
+#define SPI2_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM,                        \
+                       STM32_SPI2_RX_DMA_CHN)
+
+#define SPI2_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM,                        \
+                       STM32_SPI2_TX_DMA_CHN)
+
+#define SPI3_RX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM,                        \
+                       STM32_SPI3_RX_DMA_CHN)
+
+#define SPI3_TX_DMA_CHANNEL                                                 \
+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM,                        \
+                       STM32_SPI3_TX_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief SPI1 driver identifier.*/
+#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
+SPIDriver SPID1;
+#endif
+
+/** @brief SPI2 driver identifier.*/
+#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)
+SPIDriver SPID2;
+#endif
+
+/** @brief SPI3 driver identifier.*/
+#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)
+SPIDriver SPID3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+static uint16_t dummytx;
+static uint16_t dummyrx;
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared end-of-rx service routine.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(STM32_SPI_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_SPI_DMA_ERROR_HOOK(spip);
+  }
+#else
+  (void)flags;
+#endif
+
+  /* Stop everything.*/
+  dmaStreamDisable(spip->dmatx);
+  dmaStreamDisable(spip->dmarx);
+
+  /* Portable SPI ISR code defined in the high level driver, note, it is
+     a macro.*/
+  _spi_isr_code(spip);
+}
+
+/**
+ * @brief   Shared end-of-tx service routine.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(STM32_SPI_DMA_ERROR_HOOK)
+  (void)spip;
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_SPI_DMA_ERROR_HOOK(spip);
+  }
+#else
+  (void)spip;
+  (void)flags;
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level SPI driver initialization.
+ *
+ * @notapi
+ */
+void spi_lld_init(void) {
+
+  dummytx = 0xFFFF;
+
+#if STM32_SPI_USE_SPI1
+  spiObjectInit(&SPID1);
+  SPID1.spi       = SPI1;
+  SPID1.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
+  SPID1.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
+  SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+  SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_SPI_USE_SPI2
+  spiObjectInit(&SPID2);
+  SPID2.spi       = SPI2;
+  SPID2.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
+  SPID2.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
+  SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+  SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_SPI_USE_SPI3
+  spiObjectInit(&SPID3);
+  SPID3.spi       = SPI3;
+  SPID3.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
+  SPID3.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
+  SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_P2M |
+                    STM32_DMA_CR_TCIE |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+  SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
+                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
+                    STM32_DMA_CR_DIR_M2P |
+                    STM32_DMA_CR_DMEIE |
+                    STM32_DMA_CR_TEIE;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the SPI peripheral.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_start(SPIDriver *spip) {
+  uint32_t ds;
+
+  /* If in stopped state then enables the SPI and DMA clocks.*/
+  if (spip->state == SPI_STOP) {
+#if STM32_SPI_USE_SPI1
+    if (&SPID1 == spip) {
+      bool b;
+      b = dmaStreamAllocate(spip->dmarx,
+                            STM32_SPI_SPI1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(spip->dmatx,
+                            STM32_SPI_SPI1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableSPI1(FALSE);
+    }
+#endif
+#if STM32_SPI_USE_SPI2
+    if (&SPID2 == spip) {
+      bool b;
+      b = dmaStreamAllocate(spip->dmarx,
+                            STM32_SPI_SPI2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(spip->dmatx,
+                            STM32_SPI_SPI2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableSPI2(FALSE);
+    }
+#endif
+#if STM32_SPI_USE_SPI3
+    if (&SPID3 == spip) {
+      bool b;
+      b = dmaStreamAllocate(spip->dmarx,
+                            STM32_SPI_SPI3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(spip->dmatx,
+                            STM32_SPI_SPI3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
+                            (void *)spip);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableSPI3(FALSE);
+    }
+#endif
+
+    /* DMA setup.*/
+    dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR);
+    dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR);
+  }
+
+  /* Configuration-specific DMA setup.*/
+  ds = spip->config->cr2 & SPI_CR2_DS;
+  if (!ds || (ds <= (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0))) {
+    /* Frame width is 8 bits or smaller.*/
+    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
+                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
+    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
+                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
+  }
+  else {
+    /* Frame width is larger than 8 bits.*/
+    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
+                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
+                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+  }
+  /* SPI setup and enable.*/
+  spip->spi->CR1  = 0;
+  spip->spi->CR1  = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
+                    SPI_CR1_SSI;
+  spip->spi->CR2  = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE |
+                    SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
+  spip->spi->CR1 |= SPI_CR1_SPE;
+}
+
+/**
+ * @brief   Deactivates the SPI peripheral.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_stop(SPIDriver *spip) {
+
+  /* If in ready state then disables the SPI clock.*/
+  if (spip->state == SPI_READY) {
+
+    /* SPI disable.*/
+    spip->spi->CR1 = 0;
+    spip->spi->CR2 = 0;
+    dmaStreamRelease(spip->dmarx);
+    dmaStreamRelease(spip->dmatx);
+
+#if STM32_SPI_USE_SPI1
+    if (&SPID1 == spip)
+      rccDisableSPI1(FALSE);
+#endif
+#if STM32_SPI_USE_SPI2
+    if (&SPID2 == spip)
+      rccDisableSPI2(FALSE);
+#endif
+#if STM32_SPI_USE_SPI3
+    if (&SPID3 == spip)
+      rccDisableSPI3(FALSE);
+#endif
+  }
+}
+
+/**
+ * @brief   Asserts the slave select signal and prepares for transfers.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_select(SPIDriver *spip) {
+
+  palClearPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief   Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_unselect(SPIDriver *spip) {
+
+  palSetPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief   Ignores data on the SPI bus.
+ * @details This asynchronous function starts the transmission of a series of
+ *          idle words on the SPI bus and ignores the received data.
+ * @post    At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to be ignored
+ *
+ * @notapi
+ */
+void spi_lld_ignore(SPIDriver *spip, size_t n) {
+
+  dmaStreamSetMemory0(spip->dmarx, &dummyrx);
+  dmaStreamSetTransactionSize(spip->dmarx, n);
+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
+
+  dmaStreamSetMemory0(spip->dmatx, &dummytx);
+  dmaStreamSetTransactionSize(spip->dmatx, n);
+  dmaStreamSetMode(spip->dmatx, spip->txdmamode);
+
+  dmaStreamEnable(spip->dmarx);
+  dmaStreamEnable(spip->dmatx);
+}
+
+/**
+ * @brief   Exchanges data on the SPI bus.
+ * @details This asynchronous function starts a simultaneous transmit/receive
+ *          operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to be exchanged
+ * @param[in] txbuf     the pointer to the transmit buffer
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_exchange(SPIDriver *spip, size_t n,
+                      const void *txbuf, void *rxbuf) {
+
+  dmaStreamSetMemory0(spip->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(spip->dmarx, n);
+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
+
+  dmaStreamSetMemory0(spip->dmatx, txbuf);
+  dmaStreamSetTransactionSize(spip->dmatx, n);
+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
+
+  dmaStreamEnable(spip->dmarx);
+  dmaStreamEnable(spip->dmatx);
+}
+
+/**
+ * @brief   Sends data over the SPI bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to send
+ * @param[in] txbuf     the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
+
+  dmaStreamSetMemory0(spip->dmarx, &dummyrx);
+  dmaStreamSetTransactionSize(spip->dmarx, n);
+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
+
+  dmaStreamSetMemory0(spip->dmatx, txbuf);
+  dmaStreamSetTransactionSize(spip->dmatx, n);
+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
+
+  dmaStreamEnable(spip->dmarx);
+  dmaStreamEnable(spip->dmatx);
+}
+
+/**
+ * @brief   Receives data from the SPI bus.
+ * @details This asynchronous function starts a receive operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to receive
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
+
+  dmaStreamSetMemory0(spip->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(spip->dmarx, n);
+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
+
+  dmaStreamSetMemory0(spip->dmatx, &dummytx);
+  dmaStreamSetTransactionSize(spip->dmatx, n);
+  dmaStreamSetMode(spip->dmatx, spip->txdmamode);
+
+  dmaStreamEnable(spip->dmarx);
+  dmaStreamEnable(spip->dmatx);
+}
+
+/**
+ * @brief   Exchanges one frame using a polled wait.
+ * @details This synchronous function exchanges one frame using a polled
+ *          synchronization method. This function is useful when exchanging
+ *          small amount of data on high speed channels, usually in this
+ *          situation is much more efficient just wait for completion using
+ *          polling than suspending the thread waiting for an interrupt.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] frame     the data frame to send over the SPI bus
+ * @return              The received data frame from the SPI bus.
+ */
+uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
+
+  /*
+   * Data register must be accessed with the appropriate data size.
+   * Byte size access (uint8_t *) for transactions that are <= 8-bit.
+   * Halfword size access (uint16_t) for transactions that are <= 8-bit.
+   */
+  if ((spip->config->cr2 & SPI_CR2_DS) <= (SPI_CR2_DS_2 |
+                                           SPI_CR2_DS_1 |
+                                           SPI_CR2_DS_0)) {
+    volatile uint8_t *spidr = (volatile uint8_t *)&spip->spi->DR;
+    *spidr = (uint8_t)frame;
+    while ((spip->spi->SR & SPI_SR_RXNE) == 0)
+      ;
+    return (uint16_t)*spidr;
+  }
+  else {
+    spip->spi->DR = frame;
+    while ((spip->spi->SR & SPI_SR_RXNE) == 0)
+      ;
+    return spip->spi->DR;
+  }
+}
+
+#endif /* HAL_USE_SPI */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/SPIv2/spi_lld.h b/os/hal/ports/STM32/LLD/SPIv2/spi_lld.h
new file mode 100644
index 000000000..271774bfc
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/SPIv2/spi_lld.h
@@ -0,0 +1,369 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/SPIv2/spi_lld.h
+ * @brief   STM32 SPI subsystem low level driver header.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef _SPI_LLD_H_
+#define _SPI_LLD_H_
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   SPI1 driver enable switch.
+ * @details If set to @p TRUE the support for SPI1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI1                  FALSE
+#endif
+
+/**
+ * @brief   SPI2 driver enable switch.
+ * @details If set to @p TRUE the support for SPI2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI2                  FALSE
+#endif
+
+/**
+ * @brief   SPI3 driver enable switch.
+ * @details If set to @p TRUE the support for SPI3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
+#define STM32_SPI_USE_SPI3                  FALSE
+#endif
+
+/**
+ * @brief   SPI1 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI1_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI2 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI2_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI3 interrupt priority level setting.
+ */
+#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI3_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI1 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI1_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   SPI2 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI2_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   SPI3 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA streams but
+ *          because of the streams ordering the RX stream has always priority
+ *          over the TX stream.
+ */
+#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI3_DMA_PRIORITY         1
+#endif
+
+/**
+ * @brief   SPI DMA error hook.
+ */
+#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
+#error "SPI2 not present in the selected device"
+#endif
+
+#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
+#error "SPI3 not present in the selected device"
+#endif
+
+#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3
+#error "SPI driver activated but no SPI peripheral assigned"
+#endif
+
+#if STM32_SPI_USE_SPI1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
+#if STM32_SPI_USE_SPI2 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI2"
+#endif
+
+#if STM32_SPI_USE_SPI3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI3"
+#endif
+
+#if STM32_SPI_USE_SPI1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI1"
+#endif
+
+#if STM32_SPI_USE_SPI2 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI2"
+#endif
+
+#if STM32_SPI_USE_SPI3 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI3"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+   reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) ||        \
+                           !defined(STM32_SPI_SPI1_TX_DMA_STREAM))
+#error "SPI1 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) ||        \
+                           !defined(STM32_SPI_SPI2_TX_DMA_STREAM))
+#error "SPI2 DMA streams not defined"
+#endif
+
+#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) ||        \
+                           !defined(STM32_SPI_SPI3_TX_DMA_STREAM))
+#error "SPI3 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_SPI_USE_SPI1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 RX"
+#endif
+
+#if STM32_SPI_USE_SPI1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 TX"
+#endif
+
+#if STM32_SPI_USE_SPI2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 RX"
+#endif
+
+#if STM32_SPI_USE_SPI2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 TX"
+#endif
+
+#if STM32_SPI_USE_SPI3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 RX"
+#endif
+
+#if STM32_SPI_USE_SPI3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI3 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an SPI driver.
+ */
+typedef struct SPIDriver SPIDriver;
+
+/**
+ * @brief   SPI notification callback type.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object triggering the
+ *                      callback
+ */
+typedef void (*spicallback_t)(SPIDriver *spip);
+
+/**
+ * @brief   Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief Operation complete callback or @p NULL.
+   */
+  spicallback_t             end_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief The chip select line port.
+   */
+  ioportid_t                ssport;
+  /**
+   * @brief The chip select line pad number.
+   */
+  uint16_t                  sspad;
+  /**
+   * @brief SPI CR1 register initialization data.
+   */
+  uint16_t                  cr1;
+  /**
+   * @brief SPI CR2 register initialization data.
+   */
+  uint16_t                  cr2;
+} SPIConfig;
+
+/**
+ * @brief   Structure representing a SPI driver.
+ */
+struct SPIDriver {
+  /**
+   * @brief Driver state.
+   */
+  spistate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const SPIConfig           *config;
+#if SPI_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief   Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif /* SPI_USE_WAIT */
+#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief   Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#if defined(SPI_DRIVER_EXT_FIELDS)
+  SPI_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the SPIx registers block.
+   */
+  SPI_TypeDef               *spi;
+  /**
+   * @brief Receive DMA stream.
+   */
+  const stm32_dma_stream_t  *dmarx;
+  /**
+   * @brief Transmit DMA stream.
+   */
+  const stm32_dma_stream_t  *dmatx;
+  /**
+   * @brief RX DMA mode bit mask.
+   */
+  uint32_t                  rxdmamode;
+  /**
+   * @brief TX DMA mode bit mask.
+   */
+  uint32_t                  txdmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
+extern SPIDriver SPID1;
+#endif
+
+#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
+extern SPIDriver SPID2;
+#endif
+
+#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
+extern SPIDriver SPID3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void spi_lld_init(void);
+  void spi_lld_start(SPIDriver *spip);
+  void spi_lld_stop(SPIDriver *spip);
+  void spi_lld_select(SPIDriver *spip);
+  void spi_lld_unselect(SPIDriver *spip);
+  void spi_lld_ignore(SPIDriver *spip, size_t n);
+  void spi_lld_exchange(SPIDriver *spip, size_t n,
+                        const void *txbuf, void *rxbuf);
+  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
+  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
+  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SPI */
+
+#endif /* _SPI_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c b/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c
new file mode 100644
index 000000000..29173a8b5
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c
@@ -0,0 +1,763 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/gpt_lld.c
+ * @brief   STM32 GPT subsystem low level driver source.
+ *
+ * @addtogroup GPT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_GPT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   GPTD1 driver identifier.
+ * @note    The driver GPTD1 allocates the complex timer TIM1 when enabled.
+ */
+#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__)
+GPTDriver GPTD1;
+#endif
+
+/**
+ * @brief   GPTD2 driver identifier.
+ * @note    The driver GPTD2 allocates the timer TIM2 when enabled.
+ */
+#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__)
+GPTDriver GPTD2;
+#endif
+
+/**
+ * @brief   GPTD3 driver identifier.
+ * @note    The driver GPTD3 allocates the timer TIM3 when enabled.
+ */
+#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__)
+GPTDriver GPTD3;
+#endif
+
+/**
+ * @brief   GPTD4 driver identifier.
+ * @note    The driver GPTD4 allocates the timer TIM4 when enabled.
+ */
+#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__)
+GPTDriver GPTD4;
+#endif
+
+/**
+ * @brief   GPTD5 driver identifier.
+ * @note    The driver GPTD5 allocates the timer TIM5 when enabled.
+ */
+#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__)
+GPTDriver GPTD5;
+#endif
+
+/**
+ * @brief   GPTD6 driver identifier.
+ * @note    The driver GPTD6 allocates the timer TIM6 when enabled.
+ */
+#if STM32_GPT_USE_TIM6 || defined(__DOXYGEN__)
+GPTDriver GPTD6;
+#endif
+
+/**
+ * @brief   GPTD7 driver identifier.
+ * @note    The driver GPTD7 allocates the timer TIM7 when enabled.
+ */
+#if STM32_GPT_USE_TIM7 || defined(__DOXYGEN__)
+GPTDriver GPTD7;
+#endif
+
+/**
+ * @brief   GPTD8 driver identifier.
+ * @note    The driver GPTD8 allocates the timer TIM8 when enabled.
+ */
+#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__)
+GPTDriver GPTD8;
+#endif
+
+/**
+ * @brief   GPTD9 driver identifier.
+ * @note    The driver GPTD9 allocates the timer TIM9 when enabled.
+ */
+#if STM32_GPT_USE_TIM9 || defined(__DOXYGEN__)
+GPTDriver GPTD9;
+#endif
+
+/**
+ * @brief   GPTD11 driver identifier.
+ * @note    The driver GPTD11 allocates the timer TIM11 when enabled.
+ */
+#if STM32_GPT_USE_TIM11 || defined(__DOXYGEN__)
+GPTDriver GPTD11;
+#endif
+
+/**
+ * @brief   GPTD12 driver identifier.
+ * @note    The driver GPTD12 allocates the timer TIM12 when enabled.
+ */
+#if STM32_GPT_USE_TIM12 || defined(__DOXYGEN__)
+GPTDriver GPTD12;
+#endif
+
+/**
+ * @brief   GPTD14 driver identifier.
+ * @note    The driver GPTD14 allocates the timer TIM14 when enabled.
+ */
+#if STM32_GPT_USE_TIM14 || defined(__DOXYGEN__)
+GPTDriver GPTD14;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared IRQ handler.
+ *
+ * @param[in] gptp      pointer to a @p GPTDriver object
+ */
+static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
+
+  gptp->tim->SR = 0;
+  if (gptp->state == GPT_ONESHOT) {
+    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
+    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
+  }
+  gptp->config->callback(gptp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_GPT_USE_TIM1
+#if !defined(STM32_TIM1_UP_HANDLER)
+#error "STM32_TIM1_UP_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM1 */
+
+#if STM32_GPT_USE_TIM2
+#if !defined(STM32_TIM2_HANDLER)
+#error "STM32_TIM2_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM2 */
+
+#if STM32_GPT_USE_TIM3
+#if !defined(STM32_TIM3_HANDLER)
+#error "STM32_TIM3_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM3 */
+
+#if STM32_GPT_USE_TIM4
+#if !defined(STM32_TIM4_HANDLER)
+#error "STM32_TIM4_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM4 */
+
+#if STM32_GPT_USE_TIM5
+#if !defined(STM32_TIM5_HANDLER)
+#error "STM32_TIM5_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM5 */
+
+#if STM32_GPT_USE_TIM6
+#if !defined(STM32_TIM6_HANDLER)
+#error "STM32_TIM6_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM6_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM6 */
+
+#if STM32_GPT_USE_TIM7
+#if !defined(STM32_TIM7_HANDLER)
+#error "STM32_TIM7_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM7_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM7 */
+
+#if STM32_GPT_USE_TIM8
+#if !defined(STM32_TIM8_UP_HANDLER)
+#error "STM32_TIM8_UP_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM8 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM8 */
+
+#if STM32_GPT_USE_TIM9
+#if !defined(STM32_TIM9_HANDLER)
+#error "STM32_TIM9_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM9 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM9 */
+
+#if STM32_GPT_USE_TIM11
+#if !defined(STM32_TIM11_HANDLER)
+#error "STM32_TIM11_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM11 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM11_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD11);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM11 */
+
+#if STM32_GPT_USE_TIM12
+#if !defined(STM32_TIM12_HANDLER)
+#error "STM32_TIM12_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM12 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD12);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM12 */
+
+#if STM32_GPT_USE_TIM14
+#if !defined(STM32_TIM14_HANDLER)
+#error "STM32_TIM14_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM14 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM14_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD14);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_GPT_USE_TIM14 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level GPT driver initialization.
+ *
+ * @notapi
+ */
+void gpt_lld_init(void) {
+
+#if STM32_GPT_USE_TIM1
+  /* Driver initialization.*/
+  GPTD1.tim = STM32_TIM1;
+  gptObjectInit(&GPTD1);
+#endif
+
+#if STM32_GPT_USE_TIM2
+  /* Driver initialization.*/
+  GPTD2.tim = STM32_TIM2;
+  gptObjectInit(&GPTD2);
+#endif
+
+#if STM32_GPT_USE_TIM3
+  /* Driver initialization.*/
+  GPTD3.tim = STM32_TIM3;
+  gptObjectInit(&GPTD3);
+#endif
+
+#if STM32_GPT_USE_TIM4
+  /* Driver initialization.*/
+  GPTD4.tim = STM32_TIM4;
+  gptObjectInit(&GPTD4);
+#endif
+
+#if STM32_GPT_USE_TIM5
+  /* Driver initialization.*/
+  GPTD5.tim = STM32_TIM5;
+  gptObjectInit(&GPTD5);
+#endif
+
+#if STM32_GPT_USE_TIM6
+  /* Driver initialization.*/
+  GPTD6.tim = STM32_TIM6;
+  gptObjectInit(&GPTD6);
+#endif
+
+#if STM32_GPT_USE_TIM7
+  /* Driver initialization.*/
+  GPTD7.tim = STM32_TIM7;
+  gptObjectInit(&GPTD7);
+#endif
+
+#if STM32_GPT_USE_TIM8
+  /* Driver initialization.*/
+  GPTD8.tim = STM32_TIM8;
+  gptObjectInit(&GPTD8);
+#endif
+
+#if STM32_GPT_USE_TIM9
+  /* Driver initialization.*/
+  GPTD9.tim = STM32_TIM9;
+  gptObjectInit(&GPTD9);
+#endif
+
+#if STM32_GPT_USE_TIM11
+  /* Driver initialization.*/
+  GPTD11.tim = STM32_TIM11;
+  gptObjectInit(&GPTD11);
+#endif
+
+#if STM32_GPT_USE_TIM12
+  /* Driver initialization.*/
+  GPTD12.tim = STM32_TIM12;
+  gptObjectInit(&GPTD12);
+#endif
+
+#if STM32_GPT_USE_TIM14
+  /* Driver initialization.*/
+  GPTD14.tim = STM32_TIM14;
+  gptObjectInit(&GPTD14);
+#endif
+}
+
+/**
+ * @brief   Configures and activates the GPT peripheral.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_start(GPTDriver *gptp) {
+  uint16_t psc;
+
+  if (gptp->state == GPT_STOP) {
+    /* Clock activation.*/
+#if STM32_GPT_USE_TIM1
+    if (&GPTD1 == gptp) {
+      rccEnableTIM1(FALSE);
+      rccResetTIM1();
+      nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY);
+#if defined(STM32_TIM1CLK)
+      gptp->clock = STM32_TIM1CLK;
+#else
+      gptp->clock = STM32_TIMCLK2;
+#endif
+    }
+#endif
+#if STM32_GPT_USE_TIM2
+    if (&GPTD2 == gptp) {
+      rccEnableTIM2(FALSE);
+      rccResetTIM2();
+      nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK1;
+    }
+#endif
+#if STM32_GPT_USE_TIM3
+    if (&GPTD3 == gptp) {
+      rccEnableTIM3(FALSE);
+      rccResetTIM3();
+      nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK1;
+    }
+#endif
+#if STM32_GPT_USE_TIM4
+    if (&GPTD4 == gptp) {
+      rccEnableTIM4(FALSE);
+      rccResetTIM4();
+      nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK1;
+    }
+#endif
+
+#if STM32_GPT_USE_TIM5
+    if (&GPTD5 == gptp) {
+      rccEnableTIM5(FALSE);
+      rccResetTIM5();
+      nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK1;
+    }
+#endif
+
+#if STM32_GPT_USE_TIM6
+    if (&GPTD6 == gptp) {
+      rccEnableTIM6(FALSE);
+      rccResetTIM6();
+      nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK1;
+    }
+#endif
+
+#if STM32_GPT_USE_TIM7
+    if (&GPTD7 == gptp) {
+      rccEnableTIM7(FALSE);
+      rccResetTIM7();
+      nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK1;
+    }
+#endif
+
+#if STM32_GPT_USE_TIM8
+    if (&GPTD8 == gptp) {
+      rccEnableTIM8(FALSE);
+      rccResetTIM8();
+      nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY);
+#if defined(STM32_TIM8CLK)
+      gptp->clock = STM32_TIM8CLK;
+#else
+      gptp->clock = STM32_TIMCLK2;
+#endif
+    }
+#endif
+
+#if STM32_GPT_USE_TIM9
+    if (&GPTD9 == gptp) {
+      rccEnableTIM9(FALSE);
+      rccResetTIM9();
+      nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK2;
+    }
+#endif
+
+#if STM32_GPT_USE_TIM11
+    if (&GPTD11 == gptp) {
+      rccEnableTIM11(FALSE);
+      rccResetTIM11();
+      nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK2;
+    }
+#endif
+
+#if STM32_GPT_USE_TIM12
+    if (&GPTD12 == gptp) {
+      rccEnableTIM12(FALSE);
+      rccResetTIM12();
+      nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK1;
+    }
+#endif
+
+#if STM32_GPT_USE_TIM14
+    if (&GPTD14 == gptp) {
+      rccEnableTIM14(FALSE);
+      rccResetTIM14();
+      nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY);
+      gptp->clock = STM32_TIMCLK1;
+    }
+#endif
+  }
+
+  /* Prescaler value calculation.*/
+  psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
+  osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
+                "invalid frequency");
+
+  /* Timer configuration.*/
+  gptp->tim->CR1  = 0;                          /* Initially stopped.       */
+  gptp->tim->CR2  = gptp->config->cr2;
+  gptp->tim->PSC  = psc;                        /* Prescaler value.         */
+  gptp->tim->DIER = gptp->config->dier &        /* DMA-related DIER bits.   */
+                    ~STM32_TIM_DIER_IRQ_MASK;
+  gptp->tim->SR   = 0;                          /* Clear pending IRQs.      */
+}
+
+/**
+ * @brief   Deactivates the GPT peripheral.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_stop(GPTDriver *gptp) {
+
+  if (gptp->state == GPT_READY) {
+    gptp->tim->CR1  = 0;                        /* Timer disabled.          */
+    gptp->tim->DIER = 0;                        /* All IRQs disabled.       */
+    gptp->tim->SR   = 0;                        /* Clear pending IRQs.      */
+
+#if STM32_GPT_USE_TIM1
+    if (&GPTD1 == gptp) {
+      nvicDisableVector(STM32_TIM1_UP_NUMBER);
+      rccDisableTIM1(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM2
+    if (&GPTD2 == gptp) {
+      nvicDisableVector(STM32_TIM2_NUMBER);
+      rccDisableTIM2(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM3
+    if (&GPTD3 == gptp) {
+      nvicDisableVector(STM32_TIM3_NUMBER);
+      rccDisableTIM3(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM4
+    if (&GPTD4 == gptp) {
+      nvicDisableVector(STM32_TIM4_NUMBER);
+      rccDisableTIM4(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM5
+    if (&GPTD5 == gptp) {
+      nvicDisableVector(STM32_TIM5_NUMBER);
+      rccDisableTIM5(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM6
+    if (&GPTD6 == gptp) {
+      nvicDisableVector(STM32_TIM6_NUMBER);
+      rccDisableTIM6(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM7
+    if (&GPTD7 == gptp) {
+      nvicDisableVector(STM32_TIM7_NUMBER);
+      rccDisableTIM7(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM8
+    if (&GPTD8 == gptp) {
+      nvicDisableVector(STM32_TIM8_UP_NUMBER);
+      rccDisableTIM8(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM9
+    if (&GPTD9 == gptp) {
+      nvicDisableVector(STM32_TIM9_NUMBER);
+      rccDisableTIM9(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM11
+    if (&GPTD11 == gptp) {
+      nvicDisableVector(STM32_TIM11_NUMBER);
+      rccDisableTIM11(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM12
+    if (&GPTD12 == gptp) {
+      nvicDisableVector(STM32_TIM12_NUMBER);
+      rccDisableTIM12(FALSE);
+    }
+#endif
+#if STM32_GPT_USE_TIM14
+    if (&GPTD14 == gptp) {
+      nvicDisableVector(STM32_TIM14_NUMBER);
+      rccDisableTIM14(FALSE);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts the timer in continuous mode.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ * @param[in] interval  period in ticks
+ *
+ * @notapi
+ */
+void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
+
+  gptp->tim->ARR   = (uint32_t)(interval - 1);  /* Time constant.           */
+  gptp->tim->EGR   = STM32_TIM_EGR_UG;          /* Update event.            */
+  gptp->tim->CNT   = 0;                         /* Reset counter.           */
+
+  /* NOTE: After generating the UG event it takes several clock cycles before
+     SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
+     before the clearing of SR, to give it some time.*/
+  gptp->tim->SR    = 0;                         /* Clear pending IRQs.      */
+  if (NULL != gptp->config->callback)
+    gptp->tim->DIER |= STM32_TIM_DIER_UIE;      /* Update Event IRQ enabled.*/
+  gptp->tim->CR1   = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
+}
+
+/**
+ * @brief   Stops the timer.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_stop_timer(GPTDriver *gptp) {
+
+  gptp->tim->CR1   = 0;                         /* Initially stopped.       */
+  gptp->tim->SR    = 0;                         /* Clear pending IRQs.      */
+
+  /* All interrupts disabled.*/
+  gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
+}
+
+/**
+ * @brief   Starts the timer in one shot mode and waits for completion.
+ * @details This function specifically polls the timer waiting for completion
+ *          in order to not have extra delays caused by interrupt servicing,
+ *          this function is only recommended for short delays.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ * @param[in] interval  time interval in ticks
+ *
+ * @notapi
+ */
+void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
+
+  gptp->tim->ARR  = (uint32_t)(interval - 1);   /* Time constant.           */
+  gptp->tim->EGR  = STM32_TIM_EGR_UG;           /* Update event.            */
+  gptp->tim->CR1  = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
+  while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
+    ;
+  gptp->tim->SR   = 0;                          /* Clear pending IRQs.      */
+}
+
+#endif /* HAL_USE_GPT */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h b/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h
new file mode 100644
index 000000000..7146a9c3c
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h
@@ -0,0 +1,542 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/gpt_lld.h
+ * @brief   STM32 GPT subsystem low level driver header.
+ *
+ * @addtogroup GPT
+ * @{
+ */
+
+#ifndef _GPT_LLD_H_
+#define _GPT_LLD_H_
+
+#include "stm32_tim.h"
+
+#if HAL_USE_GPT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   GPTD1 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM1                  FALSE
+#endif
+
+/**
+ * @brief   GPTD2 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM2                  FALSE
+#endif
+
+/**
+ * @brief   GPTD3 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD3 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM3                  FALSE
+#endif
+
+/**
+ * @brief   GPTD4 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD4 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM4                  FALSE
+#endif
+
+/**
+ * @brief   GPTD5 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD5 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM5                  FALSE
+#endif
+
+/**
+ * @brief   GPTD6 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD6 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM6) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM6                  FALSE
+#endif
+
+/**
+ * @brief   GPTD7 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD7 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM7) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM7                  FALSE
+#endif
+
+/**
+ * @brief   GPTD8 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD8 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM8                  FALSE
+#endif
+
+/**
+ * @brief   GPTD9 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD9 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM9) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM9                  FALSE
+#endif
+
+/**
+ * @brief   GPTD11 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD11 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM11) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM11                 FALSE
+#endif
+
+/**
+ * @brief   GPTD12 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD12 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM12) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM12                 FALSE
+#endif
+
+/**
+ * @brief   GPTD14 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD14 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_GPT_USE_TIM14) || defined(__DOXYGEN__)
+#define STM32_GPT_USE_TIM14                 FALSE
+#endif
+
+/**
+ * @brief   GPTD1 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM1_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD2 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM2_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD3 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM3_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD4 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM4_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD5 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM5_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD6 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM6_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD7 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM7_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD8 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM8_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD9 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM9_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD11 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM11_IRQ_PRIORITY        7
+#endif
+
+/**
+ * @brief   GPTD12 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM12_IRQ_PRIORITY        7
+#endif
+
+/**
+ * @brief   GPTD14 interrupt priority level setting.
+ */
+#if !defined(STM32_GPT_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_GPT_TIM14_IRQ_PRIORITY        7
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_GPT_USE_TIM1 && !STM32_HAS_TIM1
+#error "TIM1 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM2 && !STM32_HAS_TIM2
+#error "TIM2 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM3 && !STM32_HAS_TIM3
+#error "TIM3 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM4 && !STM32_HAS_TIM4
+#error "TIM4 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM5 && !STM32_HAS_TIM5
+#error "TIM5 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM6 && !STM32_HAS_TIM6
+#error "TIM6 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM7 && !STM32_HAS_TIM7
+#error "TIM7 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM8 && !STM32_HAS_TIM8
+#error "TIM8 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM9 && !STM32_HAS_TIM9
+#error "TIM9 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM11 && !STM32_HAS_TIM11
+#error "TIM11 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM12 && !STM32_HAS_TIM12
+#error "TIM12 not present in the selected device"
+#endif
+
+#if STM32_GPT_USE_TIM14 && !STM32_HAS_TIM14
+#error "TIM14 not present in the selected device"
+#endif
+
+#if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 &&                           \
+    !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 &&  \
+    !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM6 &&  \
+    !STM32_GPT_USE_TIM7 && !STM32_GPT_USE_TIM8 &&  \
+    !STM32_GPT_USE_TIM9 && !STM32_GPT_USE_TIM11 && \
+    !STM32_GPT_USE_TIM12 && !STM32_GPT_USE_TIM14
+#error "GPT driver activated but no TIM peripheral assigned"
+#endif
+
+#if STM32_GPT_USE_TIM1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM1"
+#endif
+
+#if STM32_GPT_USE_TIM2 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM2"
+#endif
+
+#if STM32_GPT_USE_TIM3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM3"
+#endif
+
+#if STM32_GPT_USE_TIM4 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM4"
+#endif
+
+#if STM32_GPT_USE_TIM5 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM5"
+#endif
+
+#if STM32_GPT_USE_TIM6 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM6"
+#endif
+
+#if STM32_GPT_USE_TIM7 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM7"
+#endif
+
+#if STM32_GPT_USE_TIM8 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM8"
+#endif
+
+#if STM32_GPT_USE_TIM9 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM9_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM9"
+#endif
+
+#if STM32_GPT_USE_TIM11 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM11_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM11"
+#endif
+
+#if STM32_GPT_USE_TIM12 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM12_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM12"
+#endif
+
+#if STM32_GPT_USE_TIM14 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM14_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM14"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   GPT frequency type.
+ */
+typedef uint32_t gptfreq_t;
+
+/**
+ * @brief   GPT counter type.
+ */
+typedef uint32_t gptcnt_t;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief   Timer clock in Hz.
+   * @note    The low level can use assertions in order to catch invalid
+   *          frequency specifications.
+   */
+  gptfreq_t                 frequency;
+  /**
+   * @brief   Timer callback pointer.
+   * @note    This callback is invoked on GPT counter events.
+   * @note    This callback can be set to @p NULL but in that case the
+   *          one-shot mode cannot be used.
+   */
+  gptcallback_t             callback;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief TIM CR2 register initialization data.
+   * @note  The value of this field should normally be equal to zero.
+   */
+  uint32_t                  cr2;
+  /**
+   * @brief TIM DIER register initialization data.
+   * @note  The value of this field should normally be equal to zero.
+   * @note  Only the DMA-related bits can be specified in this field.
+   */
+  uint32_t                  dier;
+} GPTConfig;
+
+/**
+ * @brief   Structure representing a GPT driver.
+ */
+struct GPTDriver {
+  /**
+   * @brief Driver state.
+   */
+  gptstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const GPTConfig           *config;
+#if defined(GPT_DRIVER_EXT_FIELDS)
+  GPT_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Timer base clock.
+   */
+  uint32_t                  clock;
+  /**
+   * @brief Pointer to the TIMx registers block.
+   */
+  stm32_tim_t               *tim;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Changes the interval of GPT peripheral.
+ * @details This function changes the interval of a running GPT unit.
+ * @pre     The GPT unit must be running in continuous mode.
+ * @post    The GPT unit interval is changed to the new value.
+ * @note    The function has effect at the next cycle start.
+ *
+ * @param[in] gptp      pointer to a @p GPTDriver object
+ * @param[in] interval  new cycle time in timer ticks
+ *
+ * @notapi
+ */
+#define gpt_lld_change_interval(gptp, interval)                               \
+  ((gptp)->tim->ARR = (uint32_t)((interval) - 1))
+
+/**
+ * @brief   Returns the interval of GPT peripheral.
+ * @pre     The GPT unit must be running in continuous mode.
+ *
+ * @param[in] gptp      pointer to a @p GPTDriver object
+ * @return              The current interval.
+ *
+ * @notapi
+ */
+#define gpt_lld_get_interval(gptp) ((gptcnt_t)(gptp)->tim->ARR + 1)
+
+/**
+ * @brief   Returns the counter value of GPT peripheral.
+ * @pre     The GPT unit must be running in continuous mode.
+ * @note    The nature of the counter is not defined, it may count upward
+ *          or downward, it could be continuously running or not.
+ *
+ * @param[in] gptp      pointer to a @p GPTDriver object
+ * @return              The current counter value.
+ *
+ * @notapi
+ */
+#define gpt_lld_get_counter(gptp) ((gptcnt_t)(gptp)->tim->CNT)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD1;
+#endif
+
+#if STM32_GPT_USE_TIM2 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD2;
+#endif
+
+#if STM32_GPT_USE_TIM3 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD3;
+#endif
+
+#if STM32_GPT_USE_TIM4 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD4;
+#endif
+
+#if STM32_GPT_USE_TIM5 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD5;
+#endif
+
+#if STM32_GPT_USE_TIM6 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD6;
+#endif
+
+#if STM32_GPT_USE_TIM7 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD7;
+#endif
+
+#if STM32_GPT_USE_TIM8 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD8;
+#endif
+
+#if STM32_GPT_USE_TIM9 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD9;
+#endif
+
+#if STM32_GPT_USE_TIM11 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD11;
+#endif
+
+#if STM32_GPT_USE_TIM12 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD12;
+#endif
+
+#if STM32_GPT_USE_TIM14 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD14;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void gpt_lld_init(void);
+  void gpt_lld_start(GPTDriver *gptp);
+  void gpt_lld_stop(GPTDriver *gptp);
+  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
+  void gpt_lld_stop_timer(GPTDriver *gptp);
+  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_GPT */
+
+#endif /* _GPT_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c
new file mode 100644
index 000000000..5ad019052
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c
@@ -0,0 +1,643 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+   Concepts and parts of this file have been contributed by Fabio Utzig and
+   Xo Wang.
+ */
+
+/**
+ * @file    STM32/icu_lld.c
+ * @brief   STM32 ICU subsystem low level driver header.
+ *
+ * @addtogroup ICU
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ICU || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   ICUD1 driver identifier.
+ * @note    The driver ICUD1 allocates the complex timer TIM1 when enabled.
+ */
+#if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__)
+ICUDriver ICUD1;
+#endif
+
+/**
+ * @brief   ICUD2 driver identifier.
+ * @note    The driver ICUD1 allocates the timer TIM2 when enabled.
+ */
+#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__)
+ICUDriver ICUD2;
+#endif
+
+/**
+ * @brief   ICUD3 driver identifier.
+ * @note    The driver ICUD1 allocates the timer TIM3 when enabled.
+ */
+#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__)
+ICUDriver ICUD3;
+#endif
+
+/**
+ * @brief   ICUD4 driver identifier.
+ * @note    The driver ICUD4 allocates the timer TIM4 when enabled.
+ */
+#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__)
+ICUDriver ICUD4;
+#endif
+
+/**
+ * @brief   ICUD5 driver identifier.
+ * @note    The driver ICUD5 allocates the timer TIM5 when enabled.
+ */
+#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__)
+ICUDriver ICUD5;
+#endif
+
+/**
+ * @brief   ICUD8 driver identifier.
+ * @note    The driver ICUD8 allocates the timer TIM8 when enabled.
+ */
+#if STM32_ICU_USE_TIM8 || defined(__DOXYGEN__)
+ICUDriver ICUD8;
+#endif
+
+/**
+ * @brief   ICUD9 driver identifier.
+ * @note    The driver ICUD9 allocates the timer TIM9 when enabled.
+ */
+#if STM32_ICU_USE_TIM9 || defined(__DOXYGEN__)
+ICUDriver ICUD9;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared IRQ handler.
+ *
+ * @param[in] icup      pointer to the @p ICUDriver object
+ */
+static void icu_lld_serve_interrupt(ICUDriver *icup) {
+  uint16_t sr;
+
+  sr  = icup->tim->SR;
+  sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
+  icup->tim->SR = ~sr;
+  if (icup->config->channel == ICU_CHANNEL_1) {
+    if ((sr & STM32_TIM_SR_CC1IF) != 0)
+      _icu_isr_invoke_period_cb(icup);
+    if ((sr & STM32_TIM_SR_CC2IF) != 0)
+      _icu_isr_invoke_width_cb(icup);
+  } else {
+    if ((sr & STM32_TIM_SR_CC1IF) != 0)
+      _icu_isr_invoke_width_cb(icup);
+    if ((sr & STM32_TIM_SR_CC2IF) != 0)
+      _icu_isr_invoke_period_cb(icup);
+  }
+  if ((sr & STM32_TIM_SR_UIF) != 0)
+    _icu_isr_invoke_overflow_cb(icup);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_ICU_USE_TIM1
+#if !defined(STM32_TIM1_UP_HANDLER)
+#error "STM32_TIM1_UP_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM1 compare interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(STM32_TIM1_CC_HANDLER)
+#error "STM32_TIM1_CC_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM1 compare interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM1 */
+
+#if STM32_ICU_USE_TIM2
+#if !defined(STM32_TIM2_HANDLER)
+#error "STM32_TIM2_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM2 interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM2 */
+
+#if STM32_ICU_USE_TIM3
+#if !defined(STM32_TIM3_HANDLER)
+#error "STM32_TIM3_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM3 interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM3 */
+
+#if STM32_ICU_USE_TIM4
+#if !defined(STM32_TIM4_HANDLER)
+#error "STM32_TIM4_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM4 interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM4 */
+
+#if STM32_ICU_USE_TIM5
+#if !defined(STM32_TIM5_HANDLER)
+#error "STM32_TIM5_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM5 interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM5 */
+
+#if STM32_ICU_USE_TIM8
+#if !defined(STM32_TIM8_UP_HANDLER)
+#error "STM32_TIM8_UP_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM8 compare interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(STM32_TIM8_CC_HANDLER)
+#error "STM32_TIM8_CC_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM8 compare interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM8 */
+
+#if STM32_ICU_USE_TIM9
+#if !defined(STM32_TIM9_HANDLER)
+#error "STM32_TIM9_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM9 interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  icu_lld_serve_interrupt(&ICUD9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ICU_USE_TIM9 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ICU driver initialization.
+ *
+ * @notapi
+ */
+void icu_lld_init(void) {
+
+#if STM32_ICU_USE_TIM1
+  /* Driver initialization.*/
+  icuObjectInit(&ICUD1);
+  ICUD1.tim = STM32_TIM1;
+#endif
+
+#if STM32_ICU_USE_TIM2
+  /* Driver initialization.*/
+  icuObjectInit(&ICUD2);
+  ICUD2.tim = STM32_TIM2;
+#endif
+
+#if STM32_ICU_USE_TIM3
+  /* Driver initialization.*/
+  icuObjectInit(&ICUD3);
+  ICUD3.tim = STM32_TIM3;
+#endif
+
+#if STM32_ICU_USE_TIM4
+  /* Driver initialization.*/
+  icuObjectInit(&ICUD4);
+  ICUD4.tim = STM32_TIM4;
+#endif
+
+#if STM32_ICU_USE_TIM5
+  /* Driver initialization.*/
+  icuObjectInit(&ICUD5);
+  ICUD5.tim = STM32_TIM5;
+#endif
+
+#if STM32_ICU_USE_TIM8
+  /* Driver initialization.*/
+  icuObjectInit(&ICUD8);
+  ICUD8.tim = STM32_TIM8;
+#endif
+
+#if STM32_ICU_USE_TIM9
+  /* Driver initialization.*/
+  icuObjectInit(&ICUD9);
+  ICUD9.tim = STM32_TIM9;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the ICU peripheral.
+ *
+ * @param[in] icup      pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_start(ICUDriver *icup) {
+  uint32_t psc;
+
+  osalDbgAssert((icup->config->channel == ICU_CHANNEL_1) ||
+                (icup->config->channel == ICU_CHANNEL_2),
+                "invalid input");
+
+  if (icup->state == ICU_STOP) {
+    /* Clock activation and timer reset.*/
+#if STM32_ICU_USE_TIM1
+    if (&ICUD1 == icup) {
+      rccEnableTIM1(FALSE);
+      rccResetTIM1();
+      nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY);
+      nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY);
+#if defined(STM32_TIM1CLK)
+      icup->clock = STM32_TIM1CLK;
+#else
+      icup->clock = STM32_TIMCLK2;
+#endif
+    }
+#endif
+#if STM32_ICU_USE_TIM2
+    if (&ICUD2 == icup) {
+      rccEnableTIM2(FALSE);
+      rccResetTIM2();
+      nvicEnableVector(STM32_TIM2_NUMBER, STM32_ICU_TIM2_IRQ_PRIORITY);
+      icup->clock = STM32_TIMCLK1;
+    }
+#endif
+#if STM32_ICU_USE_TIM3
+    if (&ICUD3 == icup) {
+      rccEnableTIM3(FALSE);
+      rccResetTIM3();
+      nvicEnableVector(STM32_TIM3_NUMBER, STM32_ICU_TIM3_IRQ_PRIORITY);
+      icup->clock = STM32_TIMCLK1;
+    }
+#endif
+#if STM32_ICU_USE_TIM4
+    if (&ICUD4 == icup) {
+      rccEnableTIM4(FALSE);
+      rccResetTIM4();
+      nvicEnableVector(STM32_TIM4_NUMBER, STM32_ICU_TIM4_IRQ_PRIORITY);
+      icup->clock = STM32_TIMCLK1;
+    }
+#endif
+#if STM32_ICU_USE_TIM5
+    if (&ICUD5 == icup) {
+      rccEnableTIM5(FALSE);
+      rccResetTIM5();
+      nvicEnableVector(STM32_TIM5_NUMBER, STM32_ICU_TIM5_IRQ_PRIORITY);
+      icup->clock = STM32_TIMCLK1;
+    }
+#endif
+#if STM32_ICU_USE_TIM8
+    if (&ICUD8 == icup) {
+      rccEnableTIM8(FALSE);
+      rccResetTIM8();
+      nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY);
+      nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY);
+#if defined(STM32_TIM8CLK)
+      icup->clock = STM32_TIM8CLK;
+#else
+      icup->clock = STM32_TIMCLK2;
+#endif
+    }
+#endif
+#if STM32_ICU_USE_TIM9
+    if (&ICUD9 == icup) {
+      rccEnableTIM9(FALSE);
+      rccResetTIM9();
+      nvicEnableVector(STM32_TIM9_NUMBER, STM32_ICU_TIM9_IRQ_PRIORITY);
+      icup->clock = STM32_TIMCLK2;
+    }
+#endif
+  }
+  else {
+    /* Driver re-configuration scenario, it must be stopped first.*/
+    icup->tim->CR1    = 0;                  /* Timer disabled.              */
+    icup->tim->DIER   = icup->config->dier &/* DMA-related DIER settings.   */
+                        ~STM32_TIM_DIER_IRQ_MASK;
+    icup->tim->SR     = 0;                  /* Clear eventual pending IRQs. */
+    icup->tim->CCR[0] = 0;                  /* Comparator 1 disabled.       */
+    icup->tim->CCR[1] = 0;                  /* Comparator 2 disabled.       */
+    icup->tim->CNT    = 0;                  /* Counter reset to zero.       */
+  }
+
+  /* Timer configuration.*/
+  psc = (icup->clock / icup->config->frequency) - 1;
+  osalDbgAssert((psc <= 0xFFFF) &&
+                ((psc + 1) * icup->config->frequency) == icup->clock,
+                "invalid frequency");
+  icup->tim->PSC  = (uint16_t)psc;
+  icup->tim->ARR   = 0xFFFF;
+
+  if (icup->config->channel == ICU_CHANNEL_1) {
+    /* Selected input 1.
+       CCMR1_CC1S = 01 = CH1 Input on TI1.
+       CCMR1_CC2S = 10 = CH2 Input on TI1.*/
+    icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(1) | STM32_TIM_CCMR1_CC2S(2);
+
+    /* SMCR_TS  = 101, input is TI1FP1.
+       SMCR_SMS = 100, reset on rising edge.*/
+    icup->tim->SMCR  = STM32_TIM_SMCR_TS(5) | STM32_TIM_SMCR_SMS(4);
+
+    /* The CCER settings depend on the selected trigger mode.
+       ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge.
+       ICU_INPUT_ACTIVE_LOW:  Active on falling edge, idle on rising edge.*/
+    if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH)
+      icup->tim->CCER = STM32_TIM_CCER_CC1E |
+                        STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P;
+    else
+      icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P |
+                        STM32_TIM_CCER_CC2E;
+
+    /* Direct pointers to the capture registers in order to make reading
+       data faster from within callbacks.*/
+    icup->wccrp = &icup->tim->CCR[1];
+    icup->pccrp = &icup->tim->CCR[0];
+  } else {
+    /* Selected input 2.
+       CCMR1_CC1S = 10 = CH1 Input on TI2.
+       CCMR1_CC2S = 01 = CH2 Input on TI2.*/
+    icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(2) | STM32_TIM_CCMR1_CC2S(1);
+
+    /* SMCR_TS  = 110, input is TI2FP2.
+       SMCR_SMS = 100, reset on rising edge.*/
+    icup->tim->SMCR  = STM32_TIM_SMCR_TS(6) | STM32_TIM_SMCR_SMS(4);
+
+    /* The CCER settings depend on the selected trigger mode.
+       ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge.
+       ICU_INPUT_ACTIVE_LOW:  Active on falling edge, idle on rising edge.*/
+    if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH)
+      icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P |
+                        STM32_TIM_CCER_CC2E;
+    else
+      icup->tim->CCER = STM32_TIM_CCER_CC1E |
+                        STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P;
+
+    /* Direct pointers to the capture registers in order to make reading
+       data faster from within callbacks.*/
+    icup->wccrp = &icup->tim->CCR[0];
+    icup->pccrp = &icup->tim->CCR[1];
+  }
+}
+
+/**
+ * @brief   Deactivates the ICU peripheral.
+ *
+ * @param[in] icup      pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_stop(ICUDriver *icup) {
+
+  if (icup->state == ICU_READY) {
+    /* Clock deactivation.*/
+    icup->tim->CR1  = 0;                    /* Timer disabled.              */
+    icup->tim->DIER = 0;                    /* All IRQs disabled.           */
+    icup->tim->SR   = 0;                    /* Clear eventual pending IRQs. */
+
+#if STM32_ICU_USE_TIM1
+    if (&ICUD1 == icup) {
+      nvicDisableVector(STM32_TIM1_UP_NUMBER);
+      nvicDisableVector(STM32_TIM1_CC_NUMBER);
+      rccDisableTIM1(FALSE);
+    }
+#endif
+#if STM32_ICU_USE_TIM2
+    if (&ICUD2 == icup) {
+      nvicDisableVector(STM32_TIM2_NUMBER);
+      rccDisableTIM2(FALSE);
+    }
+#endif
+#if STM32_ICU_USE_TIM3
+    if (&ICUD3 == icup) {
+      nvicDisableVector(STM32_TIM3_NUMBER);
+      rccDisableTIM3(FALSE);
+    }
+#endif
+#if STM32_ICU_USE_TIM4
+    if (&ICUD4 == icup) {
+      nvicDisableVector(STM32_TIM4_NUMBER);
+      rccDisableTIM4(FALSE);
+    }
+#endif
+#if STM32_ICU_USE_TIM5
+    if (&ICUD5 == icup) {
+      nvicDisableVector(STM32_TIM5_NUMBER);
+      rccDisableTIM5(FALSE);
+    }
+#endif
+#if STM32_ICU_USE_TIM8
+    if (&ICUD8 == icup) {
+      nvicDisableVector(STM32_TIM8_UP_NUMBER);
+      nvicDisableVector(STM32_TIM8_CC_NUMBER);
+      rccDisableTIM8(FALSE);
+    }
+#endif
+#if STM32_ICU_USE_TIM9
+    if (&ICUD9 == icup) {
+      nvicDisableVector(STM32_TIM9_NUMBER);
+      rccDisableTIM9(FALSE);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Enables the input capture.
+ *
+ * @param[in] icup      pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_enable(ICUDriver *icup) {
+
+  icup->tim->EGR |= STM32_TIM_EGR_UG;
+  icup->tim->SR = 0;                        /* Clear pending IRQs (if any). */
+  if (icup->config->channel == ICU_CHANNEL_1) {
+    if (icup->config->period_cb != NULL)
+      icup->tim->DIER |= STM32_TIM_DIER_CC1IE;
+    if (icup->config->width_cb != NULL)
+      icup->tim->DIER |= STM32_TIM_DIER_CC2IE;
+  } else {
+    if (icup->config->width_cb != NULL)
+      icup->tim->DIER |= STM32_TIM_DIER_CC1IE;
+    if (icup->config->period_cb != NULL)
+      icup->tim->DIER |= STM32_TIM_DIER_CC2IE;
+  }
+  if (icup->config->overflow_cb != NULL)
+    icup->tim->DIER |= STM32_TIM_DIER_UIE;
+  icup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
+}
+
+/**
+ * @brief   Disables the input capture.
+ *
+ * @param[in] icup      pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_disable(ICUDriver *icup) {
+
+  icup->tim->CR1   = 0;                     /* Initially stopped.           */
+  icup->tim->SR    = 0;                     /* Clear pending IRQs (if any). */
+
+  /* All interrupts disabled.*/
+  icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
+}
+
+#endif /* HAL_USE_ICU */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h b/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h
new file mode 100644
index 000000000..f436096c3
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h
@@ -0,0 +1,412 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/icu_lld.h
+ * @brief   STM32 ICU subsystem low level driver header.
+ *
+ * @addtogroup ICU
+ * @{
+ */
+
+#ifndef _ICU_LLD_H_
+#define _ICU_LLD_H_
+
+#if HAL_USE_ICU || defined(__DOXYGEN__)
+
+#include "stm32_tim.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   ICUD1 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM1                  FALSE
+#endif
+
+/**
+ * @brief   ICUD2 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM2                  FALSE
+#endif
+
+/**
+ * @brief   ICUD3 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD3 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM3                  FALSE
+#endif
+
+/**
+ * @brief   ICUD4 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD4 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM4                  FALSE
+#endif
+
+/**
+ * @brief   ICUD5 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD5 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM5                  FALSE
+#endif
+
+/**
+ * @brief   ICUD8 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD8 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM8                  FALSE
+#endif
+
+/**
+ * @brief   ICUD9 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD9 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ICU_USE_TIM9) || defined(__DOXYGEN__)
+#define STM32_ICU_USE_TIM9                  FALSE
+#endif
+
+/**
+ * @brief   ICUD1 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM1_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   ICUD2 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM2_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   ICUD3 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM3_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   ICUD4 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM4_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   ICUD5 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM5_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   ICUD8 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM8_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   ICUD9 interrupt priority level setting.
+ */
+#if !defined(STM32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ICU_TIM9_IRQ_PRIORITY         7
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_ICU_USE_TIM1 && !STM32_HAS_TIM1
+#error "TIM1 not present in the selected device"
+#endif
+
+#if STM32_ICU_USE_TIM2 && !STM32_HAS_TIM2
+#error "TIM2 not present in the selected device"
+#endif
+
+#if STM32_ICU_USE_TIM3 && !STM32_HAS_TIM3
+#error "TIM3 not present in the selected device"
+#endif
+
+#if STM32_ICU_USE_TIM4 && !STM32_HAS_TIM4
+#error "TIM4 not present in the selected device"
+#endif
+
+#if STM32_ICU_USE_TIM5 && !STM32_HAS_TIM5
+#error "TIM5 not present in the selected device"
+#endif
+
+#if STM32_ICU_USE_TIM8 && !STM32_HAS_TIM8
+#error "TIM8 not present in the selected device"
+#endif
+
+#if STM32_ICU_USE_TIM9 && !STM32_HAS_TIM9
+#error "TIM9 not present in the selected device"
+#endif
+
+#if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 &&                           \
+    !STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 &&                           \
+    !STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 &&                           \
+    !STM32_ICU_USE_TIM9
+#error "ICU driver activated but no TIM peripheral assigned"
+#endif
+
+#if STM32_ICU_USE_TIM1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM1"
+#endif
+
+#if STM32_ICU_USE_TIM2 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM2"
+#endif
+
+#if STM32_ICU_USE_TIM3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM3"
+#endif
+
+#if STM32_ICU_USE_TIM4 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM4"
+#endif
+
+#if STM32_ICU_USE_TIM5 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM5"
+#endif
+
+#if STM32_ICU_USE_TIM8 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM8"
+#endif
+
+#if STM32_ICU_USE_TIM9 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM9"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ICU driver mode.
+ */
+typedef enum {
+  ICU_INPUT_ACTIVE_HIGH = 0,        /**< Trigger on rising edge.            */
+  ICU_INPUT_ACTIVE_LOW = 1,         /**< Trigger on falling edge.           */
+} icumode_t;
+
+/**
+ * @brief   ICU frequency type.
+ */
+typedef uint32_t icufreq_t;
+
+/**
+ * @brief   ICU channel type.
+ */
+typedef enum {
+  ICU_CHANNEL_1 = 0,              /**< Use TIMxCH1.      */
+  ICU_CHANNEL_2 = 1,              /**< Use TIMxCH2.      */
+} icuchannel_t;
+
+/**
+ * @brief   ICU counter type.
+ */
+typedef uint16_t icucnt_t;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief   Driver mode.
+   */
+  icumode_t                 mode;
+  /**
+   * @brief   Timer clock in Hz.
+   * @note    The low level can use assertions in order to catch invalid
+   *          frequency specifications.
+   */
+  icufreq_t                 frequency;
+  /**
+   * @brief   Callback for pulse width measurement.
+   */
+  icucallback_t             width_cb;
+  /**
+   * @brief   Callback for cycle period measurement.
+   */
+  icucallback_t             period_cb;
+  /**
+   * @brief   Callback for timer overflow.
+   */
+  icucallback_t             overflow_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Timer input channel to be used.
+   * @note    Only inputs TIMx 1 and 2 are supported.
+   */
+  icuchannel_t              channel;
+  /**
+   * @brief TIM DIER register initialization data.
+   * @note  The value of this field should normally be equal to zero.
+   * @note  Only the DMA-related bits can be specified in this field.
+   */
+  uint32_t                  dier;
+} ICUConfig;
+
+/**
+ * @brief   Structure representing an ICU driver.
+ */
+struct ICUDriver {
+  /**
+   * @brief Driver state.
+   */
+  icustate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const ICUConfig           *config;
+#if defined(ICU_DRIVER_EXT_FIELDS)
+  ICU_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Timer base clock.
+   */
+  uint32_t                  clock;
+  /**
+   * @brief Pointer to the TIMx registers block.
+   */
+  stm32_tim_t               *tim;
+  /**
+   * @brief CCR register used for width capture.
+   */
+  volatile uint32_t         *wccrp;
+  /**
+   * @brief CCR register used for period capture.
+   */
+  volatile uint32_t         *pccrp;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the width of the latest pulse.
+ * @details The pulse width is defined as number of ticks between the start
+ *          edge and the stop edge.
+ *
+ * @param[in] icup      pointer to the @p ICUDriver object
+ * @return              The number of ticks.
+ *
+ * @notapi
+ */
+#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
+
+/**
+ * @brief   Returns the width of the latest cycle.
+ * @details The cycle width is defined as number of ticks between a start
+ *          edge and the next start edge.
+ *
+ * @param[in] icup      pointer to the @p ICUDriver object
+ * @return              The number of ticks.
+ *
+ * @notapi
+ */
+#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_ICU_USE_TIM1 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD1;
+#endif
+
+#if STM32_ICU_USE_TIM2 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD2;
+#endif
+
+#if STM32_ICU_USE_TIM3 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD3;
+#endif
+
+#if STM32_ICU_USE_TIM4 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD4;
+#endif
+
+#if STM32_ICU_USE_TIM5 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD5;
+#endif
+
+#if STM32_ICU_USE_TIM8 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD8;
+#endif
+
+#if STM32_ICU_USE_TIM9 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD9;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void icu_lld_init(void);
+  void icu_lld_start(ICUDriver *icup);
+  void icu_lld_stop(ICUDriver *icup);
+  void icu_lld_enable(ICUDriver *icup);
+  void icu_lld_disable(ICUDriver *icup);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ICU */
+
+#endif /* _ICU_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c b/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c
new file mode 100644
index 000000000..81caf52e0
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c
@@ -0,0 +1,703 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/pwm_lld.c
+ * @brief   STM32 PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   PWMD1 driver identifier.
+ * @note    The driver PWMD1 allocates the complex timer TIM1 when enabled.
+ */
+#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief   PWMD2 driver identifier.
+ * @note    The driver PWMD2 allocates the timer TIM2 when enabled.
+ */
+#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief   PWMD3 driver identifier.
+ * @note    The driver PWMD3 allocates the timer TIM3 when enabled.
+ */
+#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/**
+ * @brief   PWMD4 driver identifier.
+ * @note    The driver PWMD4 allocates the timer TIM4 when enabled.
+ */
+#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__)
+PWMDriver PWMD4;
+#endif
+
+/**
+ * @brief   PWMD5 driver identifier.
+ * @note    The driver PWMD5 allocates the timer TIM5 when enabled.
+ */
+#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__)
+PWMDriver PWMD5;
+#endif
+
+/**
+ * @brief   PWMD8 driver identifier.
+ * @note    The driver PWMD8 allocates the timer TIM8 when enabled.
+ */
+#if STM32_PWM_USE_TIM8 || defined(__DOXYGEN__)
+PWMDriver PWMD8;
+#endif
+
+/**
+ * @brief   PWMD9 driver identifier.
+ * @note    The driver PWMD9 allocates the timer TIM9 when enabled.
+ */
+#if STM32_PWM_USE_TIM9 || defined(__DOXYGEN__)
+PWMDriver PWMD9;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+#if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || STM32_PWM_USE_TIM4 ||       \
+    STM32_PWM_USE_TIM5 || STM32_PWM_USE_TIM9 || defined(__DOXYGEN__)
+/**
+ * @brief   Common TIM2...TIM5,TIM9 IRQ handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ */
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+  uint16_t sr;
+
+  sr  = pwmp->tim->SR;
+  sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
+  pwmp->tim->SR = ~sr;
+  if ((sr & STM32_TIM_SR_CC1IF) != 0)
+    pwmp->config->channels[0].callback(pwmp);
+  if ((sr & STM32_TIM_SR_CC2IF) != 0)
+    pwmp->config->channels[1].callback(pwmp);
+  if ((sr & STM32_TIM_SR_CC3IF) != 0)
+    pwmp->config->channels[2].callback(pwmp);
+  if ((sr & STM32_TIM_SR_CC4IF) != 0)
+    pwmp->config->channels[3].callback(pwmp);
+  if ((sr & STM32_TIM_SR_UIF) != 0)
+    pwmp->config->callback(pwmp);
+}
+#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_PWM_USE_TIM1
+#if !defined(STM32_TIM1_UP_HANDLER)
+#error "STM32_TIM1_UP_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM1 update interrupt handler.
+ * @note    It is assumed that this interrupt is only activated if the callback
+ *          pointer is not equal to @p NULL in order to not perform an extra
+ *          check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  STM32_TIM1->SR = ~STM32_TIM_SR_UIF;
+  PWMD1.config->callback(&PWMD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(STM32_TIM1_CC_HANDLER)
+#error "STM32_TIM1_CC_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM1 compare interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
+  uint16_t sr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  sr = STM32_TIM1->SR & STM32_TIM1->DIER & STM32_TIM_DIER_IRQ_MASK;
+  STM32_TIM1->SR = ~sr;
+  if ((sr & STM32_TIM_SR_CC1IF) != 0)
+    PWMD1.config->channels[0].callback(&PWMD1);
+  if ((sr & STM32_TIM_SR_CC2IF) != 0)
+    PWMD1.config->channels[1].callback(&PWMD1);
+  if ((sr & STM32_TIM_SR_CC3IF) != 0)
+    PWMD1.config->channels[2].callback(&PWMD1);
+  if ((sr & STM32_TIM_SR_CC4IF) != 0)
+    PWMD1.config->channels[3].callback(&PWMD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_PWM_USE_TIM1 */
+
+#if STM32_PWM_USE_TIM2
+#if !defined(STM32_TIM2_HANDLER)
+#error "STM32_TIM2_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_interrupt(&PWMD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_PWM_USE_TIM2 */
+
+#if STM32_PWM_USE_TIM3
+#if !defined(STM32_TIM3_HANDLER)
+#error "STM32_TIM3_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_interrupt(&PWMD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_PWM_USE_TIM3 */
+
+#if STM32_PWM_USE_TIM4
+#if !defined(STM32_TIM4_HANDLER)
+#error "STM32_TIM4_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_interrupt(&PWMD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_PWM_USE_TIM4 */
+
+#if STM32_PWM_USE_TIM5
+#if !defined(STM32_TIM5_HANDLER)
+#error "STM32_TIM5_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_interrupt(&PWMD5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_PWM_USE_TIM5 */
+
+#if STM32_PWM_USE_TIM8
+#if !defined(STM32_TIM8_UP_HANDLER)
+#error "STM32_TIM8_UP_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM8 update interrupt handler.
+ * @note    It is assumed that this interrupt is only activated if the callback
+ *          pointer is not equal to @p NULL in order to not perform an extra
+ *          check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  STM32_TIM8->SR = ~TIM_SR_UIF;
+  PWMD8.config->callback(&PWMD8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(STM32_TIM8_CC_HANDLER)
+#error "STM32_TIM8_CC_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM8 compare interrupt handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
+  uint16_t sr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  sr = STM32_TIM8->SR & STM32_TIM8->DIER & STM32_TIM_DIER_IRQ_MASK;
+  STM32_TIM8->SR = ~sr;
+  if ((sr & STM32_TIM_SR_CC1IF) != 0)
+    PWMD8.config->channels[0].callback(&PWMD8);
+  if ((sr & STM32_TIM_SR_CC2IF) != 0)
+    PWMD8.config->channels[1].callback(&PWMD8);
+  if ((sr & STM32_TIM_SR_CC3IF) != 0)
+    PWMD8.config->channels[2].callback(&PWMD8);
+  if ((sr & STM32_TIM_SR_CC4IF) != 0)
+    PWMD8.config->channels[3].callback(&PWMD8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_PWM_USE_TIM8 */
+
+#if STM32_PWM_USE_TIM9
+#if !defined(STM32_TIM9_HANDLER)
+#error "STM32_TIM9_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM9 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_interrupt(&PWMD9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_PWM_USE_TIM9 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+
+#if STM32_PWM_USE_TIM1
+  /* Driver initialization.*/
+  pwmObjectInit(&PWMD1);
+  PWMD1.tim = STM32_TIM1;
+#endif
+
+#if STM32_PWM_USE_TIM2
+  /* Driver initialization.*/
+  pwmObjectInit(&PWMD2);
+  PWMD2.tim = STM32_TIM2;
+#endif
+
+#if STM32_PWM_USE_TIM3
+  /* Driver initialization.*/
+  pwmObjectInit(&PWMD3);
+  PWMD3.tim = STM32_TIM3;
+#endif
+
+#if STM32_PWM_USE_TIM4
+  /* Driver initialization.*/
+  pwmObjectInit(&PWMD4);
+  PWMD4.tim = STM32_TIM4;
+#endif
+
+#if STM32_PWM_USE_TIM5
+  /* Driver initialization.*/
+  pwmObjectInit(&PWMD5);
+  PWMD5.tim = STM32_TIM5;
+#endif
+
+#if STM32_PWM_USE_TIM8
+  /* Driver initialization.*/
+  pwmObjectInit(&PWMD8);
+  PWMD8.tim = STM32_TIM8;
+#endif
+
+#if STM32_PWM_USE_TIM9
+  /* Driver initialization.*/
+  pwmObjectInit(&PWMD9);
+  PWMD9.tim = STM32_TIM9;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the PWM peripheral.
+ * @note    Starting a driver that is already in the @p PWM_READY state
+ *          disables all the active channels.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+  uint32_t psc;
+  uint16_t ccer;
+
+  if (pwmp->state == PWM_STOP) {
+    /* Clock activation and timer reset.*/
+#if STM32_PWM_USE_TIM1
+    if (&PWMD1 == pwmp) {
+      rccEnableTIM1(FALSE);
+      rccResetTIM1();
+      nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY);
+      nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY);
+#if defined(STM32_TIM1CLK)
+      pwmp->clock = STM32_TIM1CLK;
+#else
+      pwmp->clock = STM32_TIMCLK2;
+#endif
+    }
+#endif
+#if STM32_PWM_USE_TIM2
+    if (&PWMD2 == pwmp) {
+      rccEnableTIM2(FALSE);
+      rccResetTIM2();
+      nvicEnableVector(STM32_TIM2_NUMBER, STM32_PWM_TIM2_IRQ_PRIORITY);
+      pwmp->clock = STM32_TIMCLK1;
+    }
+#endif
+#if STM32_PWM_USE_TIM3
+    if (&PWMD3 == pwmp) {
+      rccEnableTIM3(FALSE);
+      rccResetTIM3();
+      nvicEnableVector(STM32_TIM3_NUMBER, STM32_PWM_TIM3_IRQ_PRIORITY);
+      pwmp->clock = STM32_TIMCLK1;
+    }
+#endif
+#if STM32_PWM_USE_TIM4
+    if (&PWMD4 == pwmp) {
+      rccEnableTIM4(FALSE);
+      rccResetTIM4();
+      nvicEnableVector(STM32_TIM4_NUMBER, STM32_PWM_TIM4_IRQ_PRIORITY);
+      pwmp->clock = STM32_TIMCLK1;
+    }
+#endif
+
+#if STM32_PWM_USE_TIM5
+    if (&PWMD5 == pwmp) {
+      rccEnableTIM5(FALSE);
+      rccResetTIM5();
+      nvicEnableVector(STM32_TIM5_NUMBER, STM32_PWM_TIM5_IRQ_PRIORITY);
+      pwmp->clock = STM32_TIMCLK1;
+    }
+#endif
+#if STM32_PWM_USE_TIM8
+    if (&PWMD8 == pwmp) {
+      rccEnableTIM8(FALSE);
+      rccResetTIM8();
+      nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY);
+      nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY);
+#if defined(STM32_TIM8CLK)
+      pwmp->clock = STM32_TIM8CLK;
+#else
+      pwmp->clock = STM32_TIMCLK2;
+#endif
+    }
+#endif
+#if STM32_PWM_USE_TIM9
+    if (&PWMD9 == pwmp) {
+      rccEnableTIM9(FALSE);
+      rccResetTIM9();
+      nvicEnableVector(STM32_TIM9_NUMBER, STM32_PWM_TIM9_IRQ_PRIORITY);
+      pwmp->clock = STM32_TIMCLK2;
+    }
+#endif
+
+    /* All channels configured in PWM1 mode with preload enabled and will
+       stay that way until the driver is stopped.*/
+    pwmp->tim->CCMR1 = STM32_TIM_CCMR1_OC1M(6) | STM32_TIM_CCMR1_OC1PE |
+                       STM32_TIM_CCMR1_OC2M(6) | STM32_TIM_CCMR1_OC2PE;
+    pwmp->tim->CCMR2 = STM32_TIM_CCMR2_OC3M(6) | STM32_TIM_CCMR2_OC3PE |
+                       STM32_TIM_CCMR2_OC4M(6) | STM32_TIM_CCMR2_OC4PE;
+  }
+  else {
+    /* Driver re-configuration scenario, it must be stopped first.*/
+    pwmp->tim->CR1    = 0;                  /* Timer disabled.              */
+    pwmp->tim->DIER   = pwmp->config->dier &/* DMA-related DIER settings.   */
+                        ~STM32_TIM_DIER_IRQ_MASK;
+    pwmp->tim->SR     = 0;                  /* Clear eventual pending IRQs. */
+    pwmp->tim->CCR[0] = 0;                  /* Comparator 1 disabled.       */
+    pwmp->tim->CCR[1] = 0;                  /* Comparator 2 disabled.       */
+    pwmp->tim->CCR[2] = 0;                  /* Comparator 3 disabled.       */
+    pwmp->tim->CCR[3] = 0;                  /* Comparator 4 disabled.       */
+    pwmp->tim->CNT  = 0;                    /* Counter reset to zero.       */
+  }
+
+  /* Timer configuration.*/
+  psc = (pwmp->clock / pwmp->config->frequency) - 1;
+  osalDbgAssert((psc <= 0xFFFF) &&
+                ((psc + 1) * pwmp->config->frequency) == pwmp->clock,
+                "invalid frequency");
+  pwmp->tim->PSC  = (uint16_t)psc;
+  pwmp->tim->ARR  = (uint16_t)(pwmp->period - 1);
+  pwmp->tim->CR2  = pwmp->config->cr2;
+
+  /* Output enables and polarities setup.*/
+  ccer = 0;
+  switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) {
+  case PWM_OUTPUT_ACTIVE_LOW:
+    ccer |= STM32_TIM_CCER_CC1P;
+  case PWM_OUTPUT_ACTIVE_HIGH:
+    ccer |= STM32_TIM_CCER_CC1E;
+  default:
+    ;
+  }
+  switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) {
+  case PWM_OUTPUT_ACTIVE_LOW:
+    ccer |= STM32_TIM_CCER_CC2P;
+  case PWM_OUTPUT_ACTIVE_HIGH:
+    ccer |= STM32_TIM_CCER_CC2E;
+  default:
+    ;
+  }
+  switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) {
+  case PWM_OUTPUT_ACTIVE_LOW:
+    ccer |= STM32_TIM_CCER_CC3P;
+  case PWM_OUTPUT_ACTIVE_HIGH:
+    ccer |= STM32_TIM_CCER_CC3E;
+  default:
+    ;
+  }
+  switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) {
+  case PWM_OUTPUT_ACTIVE_LOW:
+    ccer |= STM32_TIM_CCER_CC4P;
+  case PWM_OUTPUT_ACTIVE_HIGH:
+    ccer |= STM32_TIM_CCER_CC4E;
+  default:
+    ;
+  }
+#if STM32_PWM_USE_ADVANCED
+#if STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8
+  if (&PWMD1 == pwmp) {
+#endif
+#if !STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8
+  if (&PWMD8 == pwmp) {
+#endif
+#if STM32_PWM_USE_TIM1 && STM32_PWM_USE_TIM8
+  if ((&PWMD1 == pwmp) || (&PWMD8 == pwmp)) {
+#endif
+    switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
+    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
+      ccer |= STM32_TIM_CCER_CC1NP;
+    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
+      ccer |= STM32_TIM_CCER_CC1NE;
+    default:
+      ;
+    }
+    switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
+    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
+      ccer |= STM32_TIM_CCER_CC2NP;
+    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
+      ccer |= STM32_TIM_CCER_CC2NE;
+    default:
+      ;
+    }
+    switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
+    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
+      ccer |= STM32_TIM_CCER_CC3NP;
+    case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
+      ccer |= STM32_TIM_CCER_CC3NE;
+    default:
+      ;
+    }
+  }
+#endif /* STM32_PWM_USE_ADVANCED*/
+
+  pwmp->tim->CCER  = ccer;
+  pwmp->tim->EGR   = STM32_TIM_EGR_UG;      /* Update event.                */
+  pwmp->tim->DIER |= pwmp->config->callback == NULL ? 0 : STM32_TIM_DIER_UIE;
+  pwmp->tim->SR    = 0;                     /* Clear pending IRQs.          */
+#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8
+#if STM32_PWM_USE_ADVANCED
+  pwmp->tim->BDTR  = pwmp->config->bdtr | STM32_TIM_BDTR_MOE;
+#else
+  pwmp->tim->BDTR  = STM32_TIM_BDTR_MOE;
+#endif
+#endif
+  /* Timer configured and started.*/
+  pwmp->tim->CR1   = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS |
+                     STM32_TIM_CR1_CEN;
+}
+
+/**
+ * @brief   Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+  /* If in ready state then disables the PWM clock.*/
+  if (pwmp->state == PWM_READY) {
+    pwmp->tim->CR1  = 0;                    /* Timer disabled.              */
+    pwmp->tim->DIER = 0;                    /* All IRQs disabled.           */
+    pwmp->tim->SR   = 0;                    /* Clear eventual pending IRQs. */
+#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8
+    pwmp->tim->BDTR  = 0;
+#endif
+
+#if STM32_PWM_USE_TIM1
+    if (&PWMD1 == pwmp) {
+      nvicDisableVector(STM32_TIM1_UP_NUMBER);
+      nvicDisableVector(STM32_TIM1_CC_NUMBER);
+      rccDisableTIM1(FALSE);
+    }
+#endif
+#if STM32_PWM_USE_TIM2
+    if (&PWMD2 == pwmp) {
+      nvicDisableVector(STM32_TIM2_NUMBER);
+      rccDisableTIM2(FALSE);
+    }
+#endif
+#if STM32_PWM_USE_TIM3
+    if (&PWMD3 == pwmp) {
+      nvicDisableVector(STM32_TIM3_NUMBER);
+      rccDisableTIM3(FALSE);
+    }
+#endif
+#if STM32_PWM_USE_TIM4
+    if (&PWMD4 == pwmp) {
+      nvicDisableVector(STM32_TIM4_NUMBER);
+      rccDisableTIM4(FALSE);
+    }
+#endif
+#if STM32_PWM_USE_TIM5
+    if (&PWMD5 == pwmp) {
+      nvicDisableVector(STM32_TIM5_NUMBER);
+      rccDisableTIM5(FALSE);
+    }
+#endif
+#if STM32_PWM_USE_TIM8
+    if (&PWMD8 == pwmp) {
+      nvicDisableVector(STM32_TIM8_UP_NUMBER);
+      nvicDisableVector(STM32_TIM8_CC_NUMBER);
+      rccDisableTIM8(FALSE);
+    }
+#endif
+#if STM32_PWM_USE_TIM9
+    if (&PWMD9 == pwmp) {
+      nvicDisableVector(STM32_TIM9_NUMBER);
+      rccDisableTIM9(FALSE);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Enables a PWM channel.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @post    The channel is active using the specified configuration.
+ * @note    The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
+ * @param[in] width     PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+                            pwmchannel_t channel,
+                            pwmcnt_t width) {
+
+  pwmp->tim->CCR[channel] = width;                  /* New duty cycle.      */
+  /* If there is a callback defined for the channel then the associated
+     interrupt must be enabled.*/
+  if (pwmp->config->channels[channel].callback != NULL) {
+    uint32_t dier = pwmp->tim->DIER;
+    /* If the IRQ is not already enabled care must be taken to clear it,
+       it is probably already pending because the timer is running.*/
+    if ((dier & (2 << channel)) == 0) {
+      pwmp->tim->DIER = dier | (2 << channel);
+      pwmp->tim->SR   = ~(2 << channel);
+    }
+  }
+}
+
+/**
+ * @brief   Disables a PWM channel.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @post    The channel is disabled and its output line returned to the
+ *          idle state.
+ * @note    The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+  pwmp->tim->CCR[channel] = 0;
+  pwmp->tim->DIER &= ~(2 << channel);
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h b/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h
new file mode 100644
index 000000000..c77acf883
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h
@@ -0,0 +1,480 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/pwm_lld.h
+ * @brief   STM32 PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _PWM_LLD_H_
+#define _PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+#include "stm32_tim.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS                            4
+
+/**
+ * @brief   Complementary output modes mask.
+ * @note    This is an STM32-specific setting.
+ */
+#define PWM_COMPLEMENTARY_OUTPUT_MASK           0xF0
+
+/**
+ * @brief   Complementary output not driven.
+ * @note    This is an STM32-specific setting.
+ */
+#define PWM_COMPLEMENTARY_OUTPUT_DISABLED       0x00
+
+/**
+ * @brief   Complementary output, active is logic level one.
+ * @note    This is an STM32-specific setting.
+ * @note    This setting is only available if the configuration option
+ *          @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced
+ *          timers TIM1 and TIM8.
+ */
+#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH    0x10
+
+/**
+ * @brief   Complementary output, active is logic level zero.
+ * @note    This is an STM32-specific setting.
+ * @note    This setting is only available if the configuration option
+ *          @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced
+ *          timers TIM1 and TIM8.
+ */
+#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW     0x20
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   If advanced timer features switch.
+ * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
+ *          enabled.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_ADVANCED              FALSE
+#endif
+
+/**
+ * @brief   PWMD1 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_TIM1                  FALSE
+#endif
+
+/**
+ * @brief   PWMD2 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_TIM2                  FALSE
+#endif
+
+/**
+ * @brief   PWMD3 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD3 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_TIM3                  FALSE
+#endif
+
+/**
+ * @brief   PWMD4 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD4 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_TIM4                  FALSE
+#endif
+
+/**
+ * @brief   PWMD5 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD5 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_TIM5                  FALSE
+#endif
+
+/**
+ * @brief   PWMD8 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD8 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_TIM8) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_TIM8                  FALSE
+#endif
+
+/**
+ * @brief   PWMD9 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD9 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_TIM9) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_TIM9                  FALSE
+#endif
+
+/**
+ * @brief   PWMD1 interrupt priority level setting.
+ */
+#if !defined(STM32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM1_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   PWMD2 interrupt priority level setting.
+ */
+#if !defined(STM32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM2_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   PWMD3 interrupt priority level setting.
+ */
+#if !defined(STM32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM3_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   PWMD4 interrupt priority level setting.
+ */
+#if !defined(STM32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM4_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   PWMD5 interrupt priority level setting.
+ */
+#if !defined(STM32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM5_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   PWMD8 interrupt priority level setting.
+ */
+#if !defined(STM32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM8_IRQ_PRIORITY         7
+#endif
+/** @} */
+
+/**
+ * @brief   PWMD9 interrupt priority level setting.
+ */
+#if !defined(STM32_PWM_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM9_IRQ_PRIORITY         7
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Configuration checks.                                                     */
+/*===========================================================================*/
+
+#if STM32_PWM_USE_TIM1 && !STM32_HAS_TIM1
+#error "TIM1 not present in the selected device"
+#endif
+
+#if STM32_PWM_USE_TIM2 && !STM32_HAS_TIM2
+#error "TIM2 not present in the selected device"
+#endif
+
+#if STM32_PWM_USE_TIM3 && !STM32_HAS_TIM3
+#error "TIM3 not present in the selected device"
+#endif
+
+#if STM32_PWM_USE_TIM4 && !STM32_HAS_TIM4
+#error "TIM4 not present in the selected device"
+#endif
+
+#if STM32_PWM_USE_TIM5 && !STM32_HAS_TIM5
+#error "TIM5 not present in the selected device"
+#endif
+
+#if STM32_PWM_USE_TIM8 && !STM32_HAS_TIM8
+#error "TIM8 not present in the selected device"
+#endif
+
+#if STM32_PWM_USE_TIM9 && !STM32_HAS_TIM9
+#error "TIM9 not present in the selected device"
+#endif
+
+#if !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM2 &&                           \
+    !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4 &&                           \
+    !STM32_PWM_USE_TIM5 && !STM32_PWM_USE_TIM8 &&                           \
+    !STM32_PWM_USE_TIM9
+#error "PWM driver activated but no TIM peripheral assigned"
+#endif
+
+#if STM32_PWM_USE_ADVANCED && !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM8
+#error "advanced mode selected but no advanced timer assigned"
+#endif
+
+#if STM32_PWM_USE_TIM1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM1"
+#endif
+
+#if STM32_PWM_USE_TIM2 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM2"
+#endif
+
+#if STM32_PWM_USE_TIM3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM3"
+#endif
+
+#if STM32_PWM_USE_TIM4 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM4"
+#endif
+
+#if STM32_PWM_USE_TIM5 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM5"
+#endif
+
+#if STM32_PWM_USE_TIM8 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM8_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM8"
+#endif
+
+#if STM32_PWM_USE_TIM9 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_PWM_TIM9_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM9"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief PWM mode type.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief   PWM channel type.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief   PWM counter type.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief   PWM driver channel configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief Channel active logic level.
+   */
+  pwmmode_t                 mode;
+  /**
+   * @brief Channel callback pointer.
+   * @note  This callback is invoked on the channel compare event. If set to
+   *        @p NULL then the callback is disabled.
+   */
+  pwmcallback_t             callback;
+  /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief   PWM driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief   Timer clock in Hz.
+   * @note    The low level can use assertions in order to catch invalid
+   *          frequency specifications.
+   */
+  uint32_t                  frequency;
+  /**
+   * @brief   PWM period in ticks.
+   * @note    The low level can use assertions in order to catch invalid
+   *          period specifications.
+   */
+  pwmcnt_t                  period;
+  /**
+   * @brief Periodic callback pointer.
+   * @note  This callback is invoked on PWM counter reset. If set to
+   *        @p NULL then the callback is disabled.
+   */
+  pwmcallback_t             callback;
+  /**
+   * @brief Channels configurations.
+   */
+  PWMChannelConfig          channels[PWM_CHANNELS];
+  /* End of the mandatory fields.*/
+  /**
+   * @brief TIM CR2 register initialization data.
+   * @note  The value of this field should normally be equal to zero.
+   */
+  uint32_t                  cr2;
+#if STM32_PWM_USE_ADVANCED || defined(__DOXYGEN__)
+  /**
+   * @brief TIM BDTR (break & dead-time) register initialization data.
+   * @note  The value of this field should normally be equal to zero.
+   */                                                                     \
+   uint32_t                 bdtr;
+#endif
+   /**
+    * @brief TIM DIER register initialization data.
+    * @note  The value of this field should normally be equal to zero.
+    * @note  Only the DMA-related bits can be specified in this field.
+    */
+   uint32_t                 dier;
+} PWMConfig;
+
+/**
+ * @brief   Structure representing a PWM driver.
+ */
+struct PWMDriver {
+  /**
+   * @brief Driver state.
+   */
+  pwmstate_t                state;
+  /**
+   * @brief Current driver configuration data.
+   */
+  const PWMConfig           *config;
+  /**
+   * @brief   Current PWM period in ticks.
+   */
+  pwmcnt_t                  period;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+  PWM_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Timer base clock.
+   */
+  uint32_t                  clock;
+  /**
+   * @brief Pointer to the TIMx registers block.
+   */
+  stm32_tim_t               *tim;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ *          been activated using @p pwmStart().
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @post    The PWM unit period is changed to the new value.
+ * @note    The function has effect at the next cycle start.
+ * @note    If a period is specified that is shorter than the pulse width
+ *          programmed in one of the channels then the behavior is not
+ *          guaranteed.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] period    new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period)                                 \
+  ((pwmp)->tim->ARR = (uint16_t)((period) - 1))
+
+/**
+ * @brief   Returns a PWM channel status.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
+ *
+ * @notapi
+ */
+#define pwm_lld_is_channel_enabled(pwmp, channel)                           \
+  (((pwmp)->tim->CCR[channel] != 0) ||                                      \
+   (((pwmp)->tim->DIER & (2 << channel)) != 0))
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_PWM_USE_TIM1 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+
+#if STM32_PWM_USE_TIM2 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+
+#if STM32_PWM_USE_TIM3 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#if STM32_PWM_USE_TIM4 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD4;
+#endif
+
+#if STM32_PWM_USE_TIM5 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD5;
+#endif
+
+#if STM32_PWM_USE_TIM8 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD8;
+#endif
+
+#if STM32_PWM_USE_TIM9 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD9;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void pwm_lld_init(void);
+  void pwm_lld_start(PWMDriver *pwmp);
+  void pwm_lld_stop(PWMDriver *pwmp);
+  void pwm_lld_enable_channel(PWMDriver *pwmp,
+                              pwmchannel_t channel,
+                              pwmcnt_t width);
+  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* _PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/st_lld.c b/os/hal/ports/STM32/LLD/TIMv1/st_lld.c
new file mode 100644
index 000000000..01aeabf1b
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/TIMv1/st_lld.c
@@ -0,0 +1,214 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/st_lld.c
+ * @brief   ST Driver subsystem low level driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+
+#if (OSAL_ST_RESOLUTION == 32)
+#define ST_ARR_INIT                         0xFFFFFFFF
+#else
+#define ST_ARR_INIT                         0x0000FFFF
+#endif
+
+#if STM32_ST_USE_TIMER == 2
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM2_IS_32BITS
+#error "TIM2 is not a 32bits timer"
+#endif
+
+#define ST_HANDLER                          STM32_TIM2_HANDLER
+#define ST_NUMBER                           STM32_TIM2_NUMBER
+#define ST_CLOCK_SRC                        STM32_TIMCLK1
+#define ST_ENABLE_CLOCK()                   rccEnableTIM2(FALSE)
+
+#elif STM32_ST_USE_TIMER == 3
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM3_IS_32BITS
+#error "TIM3 is not a 32bits timer"
+#endif
+
+#define ST_HANDLER                          STM32_TIM3_HANDLER
+#define ST_NUMBER                           STM32_TIM3_NUMBER
+#define ST_CLOCK_SRC                        STM32_TIMCLK1
+#define ST_ENABLE_CLOCK()                   rccEnableTIM3(FALSE)
+
+#elif STM32_ST_USE_TIMER == 4
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM4_IS_32BITS
+#error "TIM4 is not a 32bits timer"
+#endif
+
+#define ST_HANDLER                          STM32_TIM4_HANDLER
+#define ST_NUMBER                           STM32_TIM4_NUMBER
+#define ST_CLOCK_SRC                        STM32_TIMCLK1
+#define ST_ENABLE_CLOCK()                   rccEnableTIM4(FALSE)
+
+#elif STM32_ST_USE_TIMER == 5
+#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM5_IS_32BITS
+#error "TIM5 is not a 32bits timer"
+#endif
+
+#define ST_HANDLER                          STM32_TIM5_HANDLER
+#define ST_NUMBER                           STM32_TIM5_NUMBER
+#define ST_CLOCK_SRC                        STM32_TIMCLK1
+#define ST_ENABLE_CLOCK()                   rccEnableTIM5(FALSE)
+
+#else
+#error "STM32_ST_USE_TIMER specifies an unsupported timer"
+#endif
+
+#if ST_CLOCK_SRC % OSAL_ST_FREQUENCY != 0
+#error "the selected ST frequency is not obtainable because integer rounding"
+#endif
+
+#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF
+#error "the selected ST frequency is not obtainable because TIM timer prescaler limits"
+#endif
+
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+
+#if STM32_HCLK % OSAL_ST_FREQUENCY != 0
+#error "the selected ST frequency is not obtainable because integer rounding"
+#endif
+
+#if (STM32_HCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFFFF
+#error "the selected ST frequency is not obtainable because SysTick timer counter limits"
+#endif
+
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
+/**
+ * @brief   System Timer vector.
+ * @details This interrupt is used for system tick in periodic mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SysTick_Handler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  osalSysLockFromISR();
+  osalOsTimerHandlerI();
+  osalSysUnlockFromISR();
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
+/**
+ * @brief   TIM2 interrupt handler.
+ * @details This interrupt is used for system tick in free running mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(ST_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  STM32_ST_TIM->SR = 0;
+
+  osalSysLockFromISR();
+  osalOsTimerHandlerI();
+  osalSysUnlockFromISR();
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void) {
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+  /* Free running counter mode.*/
+
+  /* Enabling timer clock.*/
+  ST_ENABLE_CLOCK();
+
+  /* Initializing the counter in free running mode.*/
+  STM32_ST_TIM->PSC    = (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1;
+  STM32_ST_TIM->ARR    = ST_ARR_INIT;
+  STM32_ST_TIM->CCMR1  = 0;
+  STM32_ST_TIM->CCR[0] = 0;
+  STM32_ST_TIM->DIER   = 0;
+  STM32_ST_TIM->CR2    = 0;
+  STM32_ST_TIM->EGR    = TIM_EGR_UG;
+  STM32_ST_TIM->CR1    = TIM_CR1_CEN;
+
+  /* IRQ enabled.*/
+  nvicEnableVector(ST_NUMBER, STM32_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+  /* Periodic systick mode, the Cortex-Mx internal systick timer is used
+     in this mode.*/
+  SysTick->LOAD = (STM32_HCLK / OSAL_ST_FREQUENCY) - 1;
+  SysTick->VAL = 0;
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+                  SysTick_CTRL_ENABLE_Msk |
+                  SysTick_CTRL_TICKINT_Msk;
+
+  /* IRQ enabled.*/
+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, STM32_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/st_lld.h b/os/hal/ports/STM32/LLD/TIMv1/st_lld.h
new file mode 100644
index 000000000..394e59e62
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/TIMv1/st_lld.h
@@ -0,0 +1,197 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/st_lld.h
+ * @brief   ST Driver subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ *          include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef _ST_LLD_H_
+#define _ST_LLD_H_
+
+#include "mcuconf.h"
+#include "stm32_registry.h"
+#include "stm32_tim.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   SysTick timer IRQ priority.
+ */
+#if !defined(STM32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ST_IRQ_PRIORITY               8
+#endif
+
+/**
+ * @brief   TIMx unit (by number) to be used for free running operations.
+ * @note    You must select a 32 bits timer if a 32 bits @p systick_t type
+ *          is required.
+ */
+#if !defined(STM32_ST_USE_TIMER) || defined(__DOXYGEN__)
+#define STM32_ST_USE_TIMER                  2
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_ST_USE_TIMER == 2
+#if !STM32_HAS_TIM2
+#error "TIM2 not present"
+#endif
+#define STM32_ST_TIM                              STM32_TIM2
+
+#elif STM32_ST_USE_TIMER == 3
+#if !STM32_HAS_TIM3
+#error "TIM3 not present"
+#endif
+#define STM32_ST_TIM                              STM32_TIM3
+
+#elif STM32_ST_USE_TIMER == 4
+#if !STM32_HAS_TIM4
+#error "TIM4 not present"
+#endif
+#define STM32_ST_TIM                              STM32_TIM4
+
+#elif STM32_ST_USE_TIMER == 5
+#if !STM32_HAS_TIM5
+#error "TIM5 not present"
+#endif
+#define STM32_ST_TIM                              STM32_TIM5
+
+#else
+#error "STM32_ST_USE_TIMER specifies an unsupported timer"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the time counter value.
+ *
+ * @return              The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+  return (systime_t)STM32_ST_TIM->CNT;
+}
+
+/**
+ * @brief   Starts the alarm.
+ * @note    Makes sure that no spurious alarms are triggered after
+ *          this call.
+ *
+ * @param[in] time      the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t time) {
+
+  STM32_ST_TIM->CCR[0] = (uint32_t)time;
+  STM32_ST_TIM->SR     = 0;
+  STM32_ST_TIM->DIER   = STM32_TIM_DIER_CC1IE;
+}
+
+/**
+ * @brief   Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+  STM32_ST_TIM->DIER = 0;
+}
+
+/**
+ * @brief   Sets the alarm time.
+ *
+ * @param[in] time      the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t time) {
+
+  STM32_ST_TIM->CCR[0] = (uint32_t)time;
+}
+
+/**
+ * @brief   Returns the current alarm time.
+ *
+ * @return              The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+  return (systime_t)STM32_ST_TIM->CCR[0];
+}
+
+/**
+ * @brief   Determines if the alarm is active.
+ *
+ * @return              The alarm status.
+ * @retval false        if the alarm is not active.
+ * @retval true         is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+  return (bool)((STM32_ST_TIM->DIER & STM32_TIM_DIER_CC1IE) != 0);
+}
+
+#endif /* _ST_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/TIMv1/stm32_tim.h b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
index b5b7e7809..b5b7e7809 100644
--- a/os/hal/platforms/STM32/TIMv1/stm32_tim.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
diff --git a/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c b/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c
new file mode 100644
index 000000000..87be9bbb6
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c
@@ -0,0 +1,525 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USARTv1/serial_lld.c
+ * @brief   STM32 low level serial driver code.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief USART1 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+/** @brief USART2 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+/** @brief USART3 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/** @brief UART4 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+/** @brief UART5 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+/** @brief USART6 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/** @brief Driver default configuration.*/
+static const SerialConfig default_config =
+{
+  SERIAL_DEFAULT_BITRATE,
+  0,
+  USART_CR2_STOP1_BITS | USART_CR2_LINEN,
+  0
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   USART initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] config    the architecture-dependent serial driver configuration
+ */
+static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
+  USART_TypeDef *u = sdp->usart;
+
+  /* Baud rate setting.*/
+#if STM32_HAS_USART6
+  if ((sdp->usart == USART1) || (sdp->usart == USART6))
+#else
+  if (sdp->usart == USART1)
+#endif
+    u->BRR = STM32_PCLK2 / config->speed;
+  else
+    u->BRR = STM32_PCLK1 / config->speed;
+
+  /* Note that some bits are enforced.*/
+  u->CR2 = config->cr2 | USART_CR2_LBDIE;
+  u->CR3 = config->cr3 | USART_CR3_EIE;
+  u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE |
+                         USART_CR1_RXNEIE | USART_CR1_TE |
+                         USART_CR1_RE;
+  u->SR = 0;
+  (void)u->SR;  /* SR reset step 1.*/
+  (void)u->DR;  /* SR reset step 2.*/
+}
+
+/**
+ * @brief   USART de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] u         pointer to an USART I/O block
+ */
+static void usart_deinit(USART_TypeDef *u) {
+
+  u->CR1 = 0;
+  u->CR2 = 0;
+  u->CR3 = 0;
+}
+
+/**
+ * @brief   Error handling routine.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] sr        USART SR register value
+ */
+static void set_error(SerialDriver *sdp, uint16_t sr) {
+  eventflags_t sts = 0;
+
+  if (sr & USART_SR_ORE)
+    sts |= SD_OVERRUN_ERROR;
+  if (sr & USART_SR_PE)
+    sts |= SD_PARITY_ERROR;
+  if (sr & USART_SR_FE)
+    sts |= SD_FRAMING_ERROR;
+  if (sr & USART_SR_NE)
+    sts |= SD_NOISE_ERROR;
+  chnAddFlagsI(sdp, sts);
+}
+
+/**
+ * @brief   Common IRQ handler.
+ *
+ * @param[in] sdp       communication channel associated to the USART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+  USART_TypeDef *u = sdp->usart;
+  uint16_t cr1 = u->CR1;
+  uint16_t sr = u->SR;
+
+  /* Special case, LIN break detection.*/
+  if (sr & USART_SR_LBD) {
+    osalSysLockFromISR();
+    chnAddFlagsI(sdp, SD_BREAK_DETECTED);
+    osalSysUnlockFromISR();
+    u->SR = ~USART_SR_LBD;
+  }
+
+  /* Data available.*/
+  osalSysLockFromISR();
+  while (sr & USART_SR_RXNE) {
+    /* Error condition detection.*/
+    if (sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE  | USART_SR_PE))
+      set_error(sdp, sr);
+    sdIncomingDataI(sdp, u->DR);
+    sr = u->SR;
+  }
+  osalSysUnlockFromISR();
+
+  /* Transmission buffer empty.*/
+  if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) {
+    msg_t b;
+    osalSysLockFromISR();
+    b = oqGetI(&sdp->oqueue);
+    if (b < Q_OK) {
+      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+      u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
+    }
+    else
+      u->DR = b;
+    osalSysUnlockFromISR();
+  }
+
+  /* Physical transmission end.*/
+  if (sr & USART_SR_TC) {
+    osalSysLockFromISR();
+    chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
+    osalSysUnlockFromISR();
+    u->CR1 = cr1 & ~(USART_CR1_TXEIE | USART_CR1_TCIE);
+    u->SR = ~USART_SR_TC;
+  }
+}
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp) {
+
+  (void)qp;
+  USART1->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp) {
+
+  (void)qp;
+  USART2->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp) {
+
+  (void)qp;
+  USART3->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+static void notify4(io_queue_t *qp) {
+
+  (void)qp;
+  UART4->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+static void notify5(io_queue_t *qp) {
+
+  (void)qp;
+  UART5->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+static void notify6(io_queue_t *qp) {
+
+  (void)qp;
+  USART6->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+#if !defined(STM32_USART1_HANDLER)
+#error "STM32_USART1_HANDLER not defined"
+#endif
+/**
+ * @brief   USART1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+#if !defined(STM32_USART2_HANDLER)
+#error "STM32_USART2_HANDLER not defined"
+#endif
+/**
+ * @brief   USART2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+#if !defined(STM32_USART3_HANDLER)
+#error "STM32_USART3_HANDLER not defined"
+#endif
+/**
+ * @brief   USART3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+#if !defined(STM32_UART4_HANDLER)
+#error "STM32_UART4_HANDLER not defined"
+#endif
+/**
+ * @brief   UART4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+#if !defined(STM32_UART5_HANDLER)
+#error "STM32_UART5_HANDLER not defined"
+#endif
+/**
+ * @brief   UART5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+#if !defined(STM32_USART6_HANDLER)
+#error "STM32_USART6_HANDLER not defined"
+#endif
+/**
+ * @brief   USART1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if STM32_SERIAL_USE_USART1
+  sdObjectInit(&SD1, NULL, notify1);
+  SD1.usart = USART1;
+#endif
+
+#if STM32_SERIAL_USE_USART2
+  sdObjectInit(&SD2, NULL, notify2);
+  SD2.usart = USART2;
+#endif
+
+#if STM32_SERIAL_USE_USART3
+  sdObjectInit(&SD3, NULL, notify3);
+  SD3.usart = USART3;
+#endif
+
+#if STM32_SERIAL_USE_UART4
+  sdObjectInit(&SD4, NULL, notify4);
+  SD4.usart = UART4;
+#endif
+
+#if STM32_SERIAL_USE_UART5
+  sdObjectInit(&SD5, NULL, notify5);
+  SD5.usart = UART5;
+#endif
+
+#if STM32_SERIAL_USE_USART6
+  sdObjectInit(&SD6, NULL, notify6);
+  SD6.usart = USART6;
+#endif
+}
+
+/**
+ * @brief   Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] config    the architecture-dependent serial driver configuration.
+ *                      If this parameter is set to @p NULL then a default
+ *                      configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+  if (config == NULL)
+    config = &default_config;
+
+  if (sdp->state == SD_STOP) {
+#if STM32_SERIAL_USE_USART1
+    if (&SD1 == sdp) {
+      rccEnableUSART1(FALSE);
+      nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_USART2
+    if (&SD2 == sdp) {
+      rccEnableUSART2(FALSE);
+      nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_USART3
+    if (&SD3 == sdp) {
+      rccEnableUSART3(FALSE);
+      nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_UART4
+    if (&SD4 == sdp) {
+      rccEnableUART4(FALSE);
+      nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_UART5
+    if (&SD5 == sdp) {
+      rccEnableUART5(FALSE);
+      nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_USART6
+    if (&SD6 == sdp) {
+      rccEnableUSART6(FALSE);
+      nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);
+    }
+#endif
+  }
+  usart_init(sdp, config);
+}
+
+/**
+ * @brief   Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ *          interrupt vector.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+  if (sdp->state == SD_READY) {
+    usart_deinit(sdp->usart);
+#if STM32_SERIAL_USE_USART1
+    if (&SD1 == sdp) {
+      rccDisableUSART1(FALSE);
+      nvicDisableVector(STM32_USART1_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART2
+    if (&SD2 == sdp) {
+      rccDisableUSART2(FALSE);
+      nvicDisableVector(STM32_USART2_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART3
+    if (&SD3 == sdp) {
+      rccDisableUSART3(FALSE);
+      nvicDisableVector(STM32_USART3_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_UART4
+    if (&SD4 == sdp) {
+      rccDisableUART4(FALSE);
+      nvicDisableVector(STM32_UART4_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_UART5
+    if (&SD5 == sdp) {
+      rccDisableUART5(FALSE);
+      nvicDisableVector(STM32_UART5_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART6
+    if (&SD6 == sdp) {
+      rccDisableUSART6(FALSE);
+      nvicDisableVector(STM32_USART6_NUMBER);
+      return;
+    }
+#endif
+  }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/USARTv1/serial_lld.h b/os/hal/ports/STM32/LLD/USARTv1/serial_lld.h
new file mode 100644
index 000000000..bdf8e9bdb
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USARTv1/serial_lld.h
@@ -0,0 +1,303 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USARTv1/serial_lld.h
+ * @brief   STM32 low level serial driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   USART1 driver enable switch.
+ * @details If set to @p TRUE the support for USART1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART1             FALSE
+#endif
+
+/**
+ * @brief   USART2 driver enable switch.
+ * @details If set to @p TRUE the support for USART2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART2             FALSE
+#endif
+
+/**
+ * @brief   USART3 driver enable switch.
+ * @details If set to @p TRUE the support for USART3 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART3             FALSE
+#endif
+
+/**
+ * @brief   UART4 driver enable switch.
+ * @details If set to @p TRUE the support for UART4 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART4              FALSE
+#endif
+
+/**
+ * @brief   UART5 driver enable switch.
+ * @details If set to @p TRUE the support for UART5 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART5              FALSE
+#endif
+
+/**
+ * @brief   USART6 driver enable switch.
+ * @details If set to @p TRUE the support for USART6 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART6             FALSE
+#endif
+
+/**
+ * @brief   USART1 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART1_PRIORITY        12
+#endif
+
+/**
+ * @brief   USART2 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART2_PRIORITY        12
+#endif
+
+/**
+ * @brief   USART3 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART3_PRIORITY        12
+#endif
+
+/**
+ * @brief   UART4 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART4_PRIORITY         12
+#endif
+
+/**
+ * @brief   UART5 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART5_PRIORITY         12
+#endif
+
+/**
+ * @brief   USART6 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART6_PRIORITY        12
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1
+#error "USART1 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2
+#error "USART2 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3
+#error "USART3 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4
+#error "UART4 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5
+#error "UART5 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6
+#error "USART6 not present in the selected device"
+#endif
+
+#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 &&                 \
+    !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4  &&                 \
+    !STM32_SERIAL_USE_UART5  && !STM32_SERIAL_USE_USART6
+#error "SERIAL driver activated but no USART/UART peripheral assigned"
+#endif
+
+#if STM32_SERIAL_USE_USART1 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
+#error "Invalid IRQ priority assigned to USART1"
+#endif
+
+#if STM32_SERIAL_USE_USART2 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
+#error "Invalid IRQ priority assigned to USART2"
+#endif
+
+#if STM32_SERIAL_USE_USART3 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
+#error "Invalid IRQ priority assigned to USART3"
+#endif
+
+#if STM32_SERIAL_USE_UART4 &&                                               \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
+#error "Invalid IRQ priority assigned to UART4"
+#endif
+
+#if STM32_SERIAL_USE_UART5 &&                                               \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
+#error "Invalid IRQ priority assigned to UART5"
+#endif
+
+#if STM32_SERIAL_USE_USART6 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
+#error "Invalid IRQ priority assigned to USART6"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ *          in order to configure and start a serial driver operations.
+ * @note    This structure content is architecture dependent, each driver
+ *          implementation defines its own version and the custom static
+ *          initializers.
+ */
+typedef struct {
+  /**
+   * @brief Bit rate.
+   */
+  uint32_t                  speed;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Initialization value for the CR1 register.
+   */
+  uint16_t                  cr1;
+  /**
+   * @brief Initialization value for the CR2 register.
+   */
+  uint16_t                  cr2;
+  /**
+   * @brief Initialization value for the CR3 register.
+   */
+  uint16_t                  cr3;
+} SerialConfig;
+
+/**
+ * @brief   @p SerialDriver specific data.
+ */
+#define _serial_driver_data                                                 \
+  _base_asynchronous_channel_data                                           \
+  /* Driver state.*/                                                        \
+  sdstate_t                 state;                                          \
+  /* Input queue.*/                                                         \
+  input_queue_t             iqueue;                                         \
+  /* Output queue.*/                                                        \
+  output_queue_t            oqueue;                                         \
+  /* Input circular buffer.*/                                               \
+  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
+  /* Output circular buffer.*/                                              \
+  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
+  /* End of the mandatory fields.*/                                         \
+  /* Pointer to the USART registers block.*/                                \
+  USART_TypeDef             *usart;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*
+ * Extra USARTs definitions here (missing from the ST header file).
+ */
+#define USART_CR2_STOP1_BITS    (0 << 12)   /**< @brief CR2 1 stop bit value.*/
+#define USART_CR2_STOP0P5_BITS  (1 << 12)   /**< @brief CR2 0.5 stop bit value.*/
+#define USART_CR2_STOP2_BITS    (2 << 12)   /**< @brief CR2 2 stop bit value.*/
+#define USART_CR2_STOP1P5_BITS  (3 << 12)   /**< @brief CR2 1.5 stop bit value.*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void sd_lld_init(void);
+  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+  void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c b/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c
new file mode 100644
index 000000000..b1856366c
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c
@@ -0,0 +1,813 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USARTv1/uart_lld.c
+ * @brief   STM32 low level UART driver code.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define USART1_RX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM,                     \
+                       STM32_USART1_RX_DMA_CHN)
+
+#define USART1_TX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM,                     \
+                       STM32_USART1_TX_DMA_CHN)
+
+#define USART2_RX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM,                     \
+                       STM32_USART2_RX_DMA_CHN)
+
+#define USART2_TX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM,                     \
+                       STM32_USART2_TX_DMA_CHN)
+
+#define USART3_RX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM,                     \
+                       STM32_USART3_RX_DMA_CHN)
+
+#define USART3_TX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM,                     \
+                       STM32_USART3_TX_DMA_CHN)
+
+#define UART4_RX_DMA_CHANNEL                                                \
+  STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM,                      \
+                       STM32_UART4_RX_DMA_CHN)
+
+#define UART4_TX_DMA_CHANNEL                                                \
+  STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM,                      \
+                       STM32_UART4_TX_DMA_CHN)
+
+#define UART5_RX_DMA_CHANNEL                                                \
+  STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM,                      \
+                       STM32_UART5_RX_DMA_CHN)
+
+#define UART5_TX_DMA_CHANNEL                                                \
+  STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM,                      \
+                       STM32_UART5_TX_DMA_CHN)
+
+#define USART6_RX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM,                     \
+                       STM32_USART6_RX_DMA_CHN)
+
+#define USART6_TX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM,                     \
+                       STM32_USART6_TX_DMA_CHN)
+
+#define STM32_UART45_CR2_CHECK_MASK                                         \
+  (USART_CR2_STOP_0 | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA |   \
+   USART_CR2_LBCL)
+
+#define STM32_UART45_CR3_CHECK_MASK                                         \
+  (USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_SCEN |     \
+   USART_CR3_NACK)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief USART1 UART driver identifier.*/
+#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
+UARTDriver UARTD1;
+#endif
+
+/** @brief USART2 UART driver identifier.*/
+#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
+UARTDriver UARTD2;
+#endif
+
+/** @brief USART3 UART driver identifier.*/
+#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
+UARTDriver UARTD3;
+#endif
+
+/** @brief UART4 UART driver identifier.*/
+#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
+UARTDriver UARTD4;
+#endif
+
+/** @brief UART5 UART driver identifier.*/
+#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
+UARTDriver UARTD5;
+#endif
+
+/** @brief USART6 UART driver identifier.*/
+#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
+UARTDriver UARTD6;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Status bits translation.
+ *
+ * @param[in] sr        USART SR register value
+ *
+ * @return  The error flags.
+ */
+static uartflags_t translate_errors(uint16_t sr) {
+  uartflags_t sts = 0;
+
+  if (sr & USART_SR_ORE)
+    sts |= UART_OVERRUN_ERROR;
+  if (sr & USART_SR_PE)
+    sts |= UART_PARITY_ERROR;
+  if (sr & USART_SR_FE)
+    sts |= UART_FRAMING_ERROR;
+  if (sr & USART_SR_NE)
+    sts |= UART_NOISE_ERROR;
+  if (sr & USART_SR_LBD)
+    sts |= UART_BREAK_DETECTED;
+  return sts;
+}
+
+/**
+ * @brief   Puts the receiver in the UART_RX_IDLE state.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void set_rx_idle_loop(UARTDriver *uartp) {
+  uint32_t mode;
+  
+  /* RX DMA channel preparation, if the char callback is defined then the
+     TCIE interrupt is enabled too.*/
+  if (uartp->config->rxchar_cb == NULL)
+    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
+  else
+    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
+  dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
+  dmaStreamSetTransactionSize(uartp->dmarx, 1);
+  dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);
+  dmaStreamEnable(uartp->dmarx);
+}
+
+/**
+ * @brief   USART de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void usart_stop(UARTDriver *uartp) {
+
+  /* Stops RX and TX DMA channels.*/
+  dmaStreamDisable(uartp->dmarx);
+  dmaStreamDisable(uartp->dmatx);
+  
+  /* Stops USART operations.*/
+  uartp->usart->CR1 = 0;
+  uartp->usart->CR2 = 0;
+  uartp->usart->CR3 = 0;
+}
+
+/**
+ * @brief   USART initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void usart_start(UARTDriver *uartp) {
+  uint16_t cr1;
+  USART_TypeDef *u = uartp->usart;
+
+  /* Defensive programming, starting from a clean state.*/
+  usart_stop(uartp);
+
+  /* Baud rate setting.*/
+#if STM32_HAS_USART6
+  if ((uartp->usart == USART1) || (uartp->usart == USART6))
+#else
+  if (uartp->usart == USART1)
+#endif
+    u->BRR = STM32_PCLK2 / uartp->config->speed;
+  else
+    u->BRR = STM32_PCLK1 / uartp->config->speed;
+
+  /* Resetting eventual pending status flags.*/
+  (void)u->SR;  /* SR reset step 1.*/
+  (void)u->DR;  /* SR reset step 2.*/
+  u->SR = 0;
+
+  /* Note that some bits are enforced because required for correct driver
+     operations.*/
+  u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
+  u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
+                                USART_CR3_EIE;
+  if (uartp->config->txend2_cb == NULL)
+    cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
+  else
+    cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE |
+          USART_CR1_TCIE;
+  u->CR1 = uartp->config->cr1 | cr1;
+
+  /* Starting the receiver idle loop.*/
+  set_rx_idle_loop(uartp);
+}
+
+/**
+ * @brief   RX DMA common service routine.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(STM32_UART_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_UART_DMA_ERROR_HOOK(uartp);
+  }
+#else
+  (void)flags;
+#endif
+
+  if (uartp->rxstate == UART_RX_IDLE) {
+    /* Receiver in idle state, a callback is generated, if enabled, for each
+       received character and then the driver stays in the same state.*/
+    if (uartp->config->rxchar_cb != NULL)
+      uartp->config->rxchar_cb(uartp, uartp->rxbuf);
+  }
+  else {
+    /* Receiver in active state, a callback is generated, if enabled, after
+       a completed transfer.*/
+    dmaStreamDisable(uartp->dmarx);
+    uartp->rxstate = UART_RX_COMPLETE;
+    if (uartp->config->rxend_cb != NULL)
+      uartp->config->rxend_cb(uartp);
+
+    /* If the callback didn't explicitly change state then the receiver
+       automatically returns to the idle state.*/
+    if (uartp->rxstate == UART_RX_COMPLETE) {
+      uartp->rxstate = UART_RX_IDLE;
+      set_rx_idle_loop(uartp);
+    }
+  }
+}
+
+/**
+ * @brief   TX DMA common service routine.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(STM32_UART_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_UART_DMA_ERROR_HOOK(uartp);
+  }
+#else
+  (void)flags;
+#endif
+
+  dmaStreamDisable(uartp->dmatx);
+
+  /* A callback is generated, if enabled, after a completed transfer.*/
+  uartp->txstate = UART_TX_COMPLETE;
+  if (uartp->config->txend1_cb != NULL)
+    uartp->config->txend1_cb(uartp);
+
+  /* If the callback didn't explicitly change state then the transmitter
+     automatically returns to the idle state.*/
+  if (uartp->txstate == UART_TX_COMPLETE)
+    uartp->txstate = UART_TX_IDLE;
+}
+
+/**
+ * @brief   USART common service routine.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void serve_usart_irq(UARTDriver *uartp) {
+  uint16_t sr;
+  USART_TypeDef *u = uartp->usart;
+  
+  sr = u->SR;   /* SR reset step 1.*/
+  (void)u->DR;  /* SR reset step 2.*/
+  if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE |
+            USART_SR_FE  | USART_SR_PE)) {
+    u->SR = ~USART_SR_LBD;
+    if (uartp->config->rxerr_cb != NULL)
+      uartp->config->rxerr_cb(uartp, translate_errors(sr));
+  }
+  if (sr & USART_SR_TC) {
+    u->SR = ~USART_SR_TC;
+
+    /* End of transmission, a callback is generated.*/
+    if (uartp->config->txend2_cb != NULL)
+      uartp->config->txend2_cb(uartp);
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
+#if !defined(STM32_USART1_HANDLER)
+#error "STM32_USART1_HANDLER not defined"
+#endif
+/**
+ * @brief   USART1 IRQ handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD1);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART1 */
+
+#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
+#if !defined(STM32_USART2_HANDLER)
+#error "STM32_USART2_HANDLER not defined"
+#endif
+/**
+ * @brief   USART2 IRQ handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD2);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART2 */
+
+#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
+#if !defined(STM32_USART3_HANDLER)
+#error "STM32_USART3_HANDLER not defined"
+#endif
+/**
+ * @brief   USART3 IRQ handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD3);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART3 */
+
+#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
+#if !defined(STM32_UART4_HANDLER)
+#error "STM32_UART4_HANDLER not defined"
+#endif
+/**
+ * @brief   UART4 IRQ handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD4);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_UART4 */
+
+#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
+#if !defined(STM32_UART5_HANDLER)
+#error "STM32_UART5_HANDLER not defined"
+#endif
+/**
+ * @brief   UART5 IRQ handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD5);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_UART5 */
+
+#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
+#if !defined(STM32_USART6_HANDLER)
+#error "STM32_USART6_HANDLER not defined"
+#endif
+/**
+ * @brief   USART6 IRQ handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USART6_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD6);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART6 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level UART driver initialization.
+ *
+ * @notapi
+ */
+void uart_lld_init(void) {
+
+#if STM32_UART_USE_USART1
+  uartObjectInit(&UARTD1);
+  UARTD1.usart   = USART1;
+  UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+  UARTD1.dmarx   = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
+  UARTD1.dmatx   = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
+#endif
+
+#if STM32_UART_USE_USART2
+  uartObjectInit(&UARTD2);
+  UARTD2.usart   = USART2;
+  UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+  UARTD2.dmarx   = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
+  UARTD2.dmatx   = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
+#endif
+
+#if STM32_UART_USE_USART3
+  uartObjectInit(&UARTD3);
+  UARTD3.usart   = USART3;
+  UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+  UARTD3.dmarx   = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
+  UARTD3.dmatx   = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
+#endif
+
+#if STM32_UART_USE_UART4
+  uartObjectInit(&UARTD4);
+  UARTD4.usart   = UART4;
+  UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+  UARTD4.dmarx   = STM32_DMA_STREAM(STM32_UART_UART4_RX_DMA_STREAM);
+  UARTD4.dmatx   = STM32_DMA_STREAM(STM32_UART_UART4_TX_DMA_STREAM);
+#endif
+
+#if STM32_UART_USE_UART5
+  uartObjectInit(&UARTD5);
+  UARTD5.usart   = UART5;
+  UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+  UARTD5.dmarx   = STM32_DMA_STREAM(STM32_UART_UART5_RX_DMA_STREAM);
+  UARTD5.dmatx   = STM32_DMA_STREAM(STM32_UART_UART5_TX_DMA_STREAM);
+#endif
+
+#if STM32_UART_USE_USART6
+  uartObjectInit(&UARTD6);
+  UARTD6.usart   = USART6;
+  UARTD6.dmarx   = STM32_DMA_STREAM(STM32_UART_USART6_RX_DMA_STREAM);
+  UARTD6.dmatx   = STM32_DMA_STREAM(STM32_UART_USART6_TX_DMA_STREAM);
+#endif
+}
+
+/**
+ * @brief   Configures and activates the UART peripheral.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_start(UARTDriver *uartp) {
+
+  if (uartp->state == UART_STOP) {
+#if STM32_UART_USE_USART1
+    if (&UARTD1 == uartp) {
+      bool b;
+      b = dmaStreamAllocate(uartp->dmarx,
+                            STM32_UART_USART1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(uartp->dmatx,
+                            STM32_UART_USART1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableUSART1(FALSE);
+      nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);
+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
+                        STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
+    }
+#endif
+
+#if STM32_UART_USE_USART2
+    if (&UARTD2 == uartp) {
+      bool b;
+      b = dmaStreamAllocate(uartp->dmarx,
+                            STM32_UART_USART2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(uartp->dmatx,
+                            STM32_UART_USART2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableUSART2(FALSE);
+      nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);
+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
+                        STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
+    }
+#endif
+
+#if STM32_UART_USE_USART3
+    if (&UARTD3 == uartp) {
+      bool b;
+      b = dmaStreamAllocate(uartp->dmarx,
+                            STM32_UART_USART3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(uartp->dmatx,
+                            STM32_UART_USART3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableUSART3(FALSE);
+      nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);
+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
+                        STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
+    }
+#endif
+
+#if STM32_UART_USE_UART4
+    if (&UARTD4 == uartp) {
+      bool b;
+
+      chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
+                  "specified invalid bits in UART4 CR2 register settings");
+      chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
+                  "specified invalid bits in UART4 CR3 register settings");
+
+      b = dmaStreamAllocate(uartp->dmarx,
+                            STM32_UART_UART4_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(uartp->dmatx,
+                            STM32_UART_UART4_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableUART4(FALSE);
+      nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY);
+      uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
+                        STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
+    }
+#endif
+
+#if STM32_UART_USE_UART5
+    if (&UARTD5 == uartp) {
+      bool b;
+
+      chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
+                  "specified invalid bits in UART5 CR2 register settings");
+      chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
+                  "specified invalid bits in UART5 CR3 register settings");
+
+      b = dmaStreamAllocate(uartp->dmarx,
+                            STM32_UART_UART5_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(uartp->dmatx,
+                            STM32_UART_UART5_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableUART5(FALSE);
+      nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY);
+      uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
+                        STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
+    }
+#endif
+
+#if STM32_UART_USE_USART6
+    if (&UARTD6 == uartp) {
+      bool b;
+      b = dmaStreamAllocate(uartp->dmarx,
+                            STM32_UART_USART6_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(uartp->dmatx,
+                            STM32_UART_USART6_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableUSART6(FALSE);
+      nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY);
+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
+                        STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
+    }
+#endif
+
+    /* Static DMA setup, the transfer size depends on the USART settings,
+       it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
+    if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
+      uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+    dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR);
+    dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR);
+    uartp->rxbuf = 0;
+  }
+
+  uartp->rxstate = UART_RX_IDLE;
+  uartp->txstate = UART_TX_IDLE;
+  usart_start(uartp);
+}
+
+/**
+ * @brief   Deactivates the UART peripheral.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_stop(UARTDriver *uartp) {
+
+  if (uartp->state == UART_READY) {
+    usart_stop(uartp);
+    dmaStreamRelease(uartp->dmarx);
+    dmaStreamRelease(uartp->dmatx);
+
+#if STM32_UART_USE_USART1
+    if (&UARTD1 == uartp) {
+      nvicDisableVector(STM32_USART1_NUMBER);
+      rccDisableUSART1(FALSE);
+      return;
+    }
+#endif
+
+#if STM32_UART_USE_USART2
+    if (&UARTD2 == uartp) {
+      nvicDisableVector(STM32_USART2_NUMBER);
+      rccDisableUSART2(FALSE);
+      return;
+    }
+#endif
+
+#if STM32_UART_USE_USART3
+    if (&UARTD3 == uartp) {
+      nvicDisableVector(STM32_USART3_NUMBER);
+      rccDisableUSART3(FALSE);
+      return;
+    }
+#endif
+
+#if STM32_UART_USE_UART4
+    if (&UARTD4 == uartp) {
+      nvicDisableVector(STM32_UART4_NUMBER);
+      rccDisableUART4(FALSE);
+      return;
+    }
+#endif
+
+#if STM32_UART_USE_UART5
+    if (&UARTD5 == uartp) {
+      nvicDisableVector(STM32_UART5_NUMBER);
+      rccDisableUART5(FALSE);
+      return;
+    }
+#endif
+
+#if STM32_UART_USE_USART6
+    if (&UARTD6 == uartp) {
+      nvicDisableVector(STM32_USART6_NUMBER);
+      rccDisableUSART6(FALSE);
+      return;
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts a transmission on the UART peripheral.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below
+ *          or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] n         number of data frames to send
+ * @param[in] txbuf     the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
+
+  /* TX DMA channel preparation and start.*/
+  dmaStreamSetMemory0(uartp->dmatx, txbuf);
+  dmaStreamSetTransactionSize(uartp->dmatx, n);
+  dmaStreamSetMode(uartp->dmatx, uartp->dmamode    | STM32_DMA_CR_DIR_M2P |
+                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
+  dmaStreamEnable(uartp->dmatx);
+}
+
+/**
+ * @brief   Stops any ongoing transmission.
+ * @note    Stopping a transmission also suppresses the transmission callbacks.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @return              The number of data frames not transmitted by the
+ *                      stopped transmit operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_send(UARTDriver *uartp) {
+
+  dmaStreamDisable(uartp->dmatx);
+  return dmaStreamGetTransactionSize(uartp->dmatx);
+}
+
+/**
+ * @brief   Starts a receive operation on the UART peripheral.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below
+ *          or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] n         number of data frames to send
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
+
+  /* Stopping previous activity (idle state).*/
+  dmaStreamDisable(uartp->dmarx);
+
+  /* RX DMA channel preparation and start.*/
+  dmaStreamSetMemory0(uartp->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(uartp->dmarx, n);
+  dmaStreamSetMode(uartp->dmarx, uartp->dmamode    | STM32_DMA_CR_DIR_P2M |
+                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
+  dmaStreamEnable(uartp->dmarx);
+}
+
+/**
+ * @brief   Stops any ongoing receive operation.
+ * @note    Stopping a receive operation also suppresses the receive callbacks.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @return              The number of data frames not received by the
+ *                      stopped receive operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_receive(UARTDriver *uartp) {
+  size_t n;
+
+  dmaStreamDisable(uartp->dmarx);
+  n = dmaStreamGetTransactionSize(uartp->dmarx);
+  set_rx_idle_loop(uartp);
+  return n;
+}
+
+#endif /* HAL_USE_UART */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/USARTv1/uart_lld.h b/os/hal/ports/STM32/LLD/USARTv1/uart_lld.h
new file mode 100644
index 000000000..b5992b340
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USARTv1/uart_lld.h
@@ -0,0 +1,603 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USARTv1/uart_lld.h
+ * @brief   STM32 low level UART driver header.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#ifndef _UART_LLD_H_
+#define _UART_LLD_H_
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   UART driver on USART1 enable switch.
+ * @details If set to @p TRUE the support for USART1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART1               FALSE
+#endif
+
+/**
+ * @brief   UART driver on USART2 enable switch.
+ * @details If set to @p TRUE the support for USART2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART2               FALSE
+#endif
+
+/**
+ * @brief   UART driver on USART3 enable switch.
+ * @details If set to @p TRUE the support for USART3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART3               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART4 enable switch.
+ * @details If set to @p TRUE the support for UART4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__)
+#define STM32_UART_USE_UART4                FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART5 enable switch.
+ * @details If set to @p TRUE the support for UART5 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_UART5) || defined(__DOXYGEN__)
+#define STM32_UART_USE_UART5                FALSE
+#endif
+
+/**
+ * @brief   UART driver on USART6 enable switch.
+ * @details If set to @p TRUE the support for USART6 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART6               FALSE
+#endif
+
+/**
+ * @brief   USART1 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART1_IRQ_PRIORITY      12
+#endif
+
+/**
+ * @brief   USART2 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART2_IRQ_PRIORITY      12
+#endif
+
+/**
+ * @brief   USART3 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART3_IRQ_PRIORITY      12
+#endif
+
+/**
+ * @brief   UART4 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART4_IRQ_PRIORITY       12
+#endif
+
+/**
+ * @brief   UART5 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART5_IRQ_PRIORITY       12
+#endif
+
+/**
+ * @brief   USART6 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART6_IRQ_PRIORITY      12
+#endif
+
+/**
+ * @brief   USART1 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART1_DMA_PRIORITY      0
+#endif
+
+/**
+ * @brief   USART2 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART2_DMA_PRIORITY      0
+#endif
+
+/**
+ * @brief   USART3 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART3_DMA_PRIORITY      0
+#endif
+
+/**
+ * @brief   UART4 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(STM32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART4_DMA_PRIORITY       0
+#endif
+
+/**
+ * @brief   UART5 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(STM32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_UART5_DMA_PRIORITY       0
+#endif
+
+/**
+ * @brief   USART6 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART6_DMA_PRIORITY      0
+#endif
+
+/**
+ * @brief   USART DMA error hook.
+ * @note    The default action for DMA errors is a system halt because DMA
+ *          error can only happen because programming errors.
+ */
+#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
+#error "USART1 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
+#error "USART2 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
+#error "USART3 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_UART4 
+#if !STM32_HAS_UART4
+#error "UART4 not present in the selected device"
+#endif
+
+#if !defined(STM32F2XX) && !defined(STM32F4XX)
+#error "UART4 DMA access not supported in this platform"
+#endif
+#endif /* STM32_UART_USE_UART4 */
+
+#if STM32_UART_USE_UART5
+#if !STM32_HAS_UART5
+#error "UART5 not present in the selected device"
+#endif
+
+#if !defined(STM32F2XX) && !defined(STM32F4XX)
+#error "UART5 DMA access not supported in this platform"
+#endif
+#endif /* STM32_UART_USE_UART5 */
+
+#if STM32_UART_USE_USART6 && !STM32_HAS_USART6
+#error "USART6 not present in the selected device"
+#endif
+
+#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 &&                     \
+    !STM32_UART_USE_USART3 && !STM32_UART_USE_UART4 &&                      \
+    !STM32_UART_USE_UART5  && !STM32_UART_USE_USART6
+#error "UART driver activated but no USART/UART peripheral assigned"
+#endif
+
+#if STM32_UART_USE_USART1 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART1"
+#endif
+
+#if STM32_UART_USE_USART2 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART2"
+#endif
+
+#if STM32_UART_USE_USART3 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART3"
+#endif
+
+#if STM32_UART_USE_UART4 &&                                                 \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART4"
+#endif
+
+#if STM32_UART_USE_UART5 &&                                                 \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART5"
+#endif
+
+#if STM32_UART_USE_USART6 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART6"
+#endif
+
+#if STM32_UART_USE_USART1 &&                                                \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART1"
+#endif
+
+#if STM32_UART_USE_USART2 &&                                                \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART2"
+#endif
+
+#if STM32_UART_USE_USART3 &&                                                \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART3"
+#endif
+
+#if STM32_UART_USE_UART4 &&                                                 \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART4_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to UART4"
+#endif
+
+#if STM32_UART_USE_UART5 &&                                                 \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART5_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to UART5"
+#endif
+
+#if STM32_UART_USE_USART6 &&                                                \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART6"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+   reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) ||  \
+                              !defined(STM32_UART_USART1_TX_DMA_STREAM))
+#error "USART1 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_STREAM) ||  \
+                              !defined(STM32_UART_USART2_TX_DMA_STREAM))
+#error "USART2 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_STREAM) ||  \
+                              !defined(STM32_UART_USART3_TX_DMA_STREAM))
+#error "USART3 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_UART4 && (!defined(STM32_UART_UART4_RX_DMA_STREAM) ||    \
+                             !defined(STM32_UART_UART4_TX_DMA_STREAM))
+#error "UART4 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_UART5 && (!defined(STM32_UART_UART5_RX_DMA_STREAM) ||    \
+                             !defined(STM32_UART_UART5_TX_DMA_STREAM))
+#error "UART5 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART6 && (!defined(STM32_UART_USART6_RX_DMA_STREAM) ||  \
+                              !defined(STM32_UART_USART6_TX_DMA_STREAM))
+#error "USART6 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_UART_USE_USART1 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM,                 \
+                           STM32_USART1_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART1 RX"
+#endif
+
+#if STM32_UART_USE_USART1 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM,                 \
+                           STM32_USART1_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART1 TX"
+#endif
+
+#if STM32_UART_USE_USART2 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM,                 \
+                           STM32_USART2_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART2 RX"
+#endif
+
+#if STM32_UART_USE_USART2 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM,                 \
+                           STM32_USART2_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART2 TX"
+#endif
+
+#if STM32_UART_USE_USART3 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM,                 \
+                           STM32_USART3_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART3 RX"
+#endif
+
+#if STM32_UART_USE_USART3 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM,                 \
+                           STM32_USART3_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART3 TX"
+#endif
+
+#if STM32_UART_USE_UART4 &&                                                 \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM,                  \
+                           STM32_UART4_RX_DMA_MSK)
+#error "invalid DMA stream associated to UART4 RX"
+#endif
+
+#if STM32_UART_USE_UART4 &&                                                 \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM,                  \
+                           STM32_UART4_TX_DMA_MSK)
+#error "invalid DMA stream associated to UART4 TX"
+#endif
+
+#if STM32_UART_USE_UART5 &&                                                 \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM,                  \
+                           STM32_UART5_RX_DMA_MSK)
+#error "invalid DMA stream associated to UART5 RX"
+#endif
+
+#if STM32_UART_USE_UART5 &&                                                 \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM,                  \
+                           STM32_UART5_TX_DMA_MSK)
+#error "invalid DMA stream associated to UART5 TX"
+#endif
+
+#if STM32_UART_USE_USART6 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM,                 \
+                           STM32_USART6_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART6 RX"
+#endif
+
+#if STM32_UART_USE_USART6 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM,                 \
+                           STM32_USART6_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART6 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   UART driver condition flags type.
+ */
+typedef uint32_t uartflags_t;
+
+/**
+ * @brief   Structure representing an UART driver.
+ */
+typedef struct UARTDriver UARTDriver;
+
+/**
+ * @brief   Generic UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+typedef void (*uartcb_t)(UARTDriver *uartp);
+
+/**
+ * @brief   Character received UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] c         received character
+ */
+typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
+
+/**
+ * @brief   Receive error UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] e         receive error mask
+ */
+typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief End of transmission buffer callback.
+   */
+  uartcb_t                  txend1_cb;
+  /**
+   * @brief Physical end of transmission callback.
+   */
+  uartcb_t                  txend2_cb;
+  /**
+   * @brief Receive buffer filled callback.
+   */
+  uartcb_t                  rxend_cb;
+  /**
+   * @brief Character received while out if the @p UART_RECEIVE state.
+   */
+  uartccb_t                 rxchar_cb;
+  /**
+   * @brief Receive error callback.
+   */
+  uartecb_t                 rxerr_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Bit rate.
+   */
+  uint32_t                  speed;
+  /**
+   * @brief Initialization value for the CR1 register.
+   */
+  uint16_t                  cr1;
+  /**
+   * @brief Initialization value for the CR2 register.
+   */
+  uint16_t                  cr2;
+  /**
+   * @brief Initialization value for the CR3 register.
+   */
+  uint16_t                  cr3;
+} UARTConfig;
+
+/**
+ * @brief   Structure representing an UART driver.
+ */
+struct UARTDriver {
+  /**
+   * @brief Driver state.
+   */
+  uartstate_t               state;
+  /**
+   * @brief Transmitter state.
+   */
+  uarttxstate_t             txstate;
+  /**
+   * @brief Receiver state.
+   */
+  uartrxstate_t             rxstate;
+  /**
+   * @brief Current configuration data.
+   */
+  const UARTConfig          *config;
+#if defined(UART_DRIVER_EXT_FIELDS)
+  UART_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the USART registers block.
+   */
+  USART_TypeDef             *usart;
+  /**
+   * @brief DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+  /**
+   * @brief Receive DMA channel.
+   */
+  const stm32_dma_stream_t  *dmarx;
+  /**
+   * @brief Transmit DMA channel.
+   */
+  const stm32_dma_stream_t  *dmatx;
+  /**
+   * @brief Default receive buffer while into @p UART_RX_IDLE state.
+   */
+  volatile uint16_t         rxbuf;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD1;
+#endif
+
+#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD2;
+#endif
+
+#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD3;
+#endif
+
+#if STM32_UART_USE_UART4 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD4;
+#endif
+
+#if STM32_UART_USE_UART5 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD5;
+#endif
+
+#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD6;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void uart_lld_init(void);
+  void uart_lld_start(UARTDriver *uartp);
+  void uart_lld_stop(UARTDriver *uartp);
+  void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
+  size_t uart_lld_stop_send(UARTDriver *uartp);
+  void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
+  size_t uart_lld_stop_receive(UARTDriver *uartp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_UART */
+
+#endif /* _UART_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c b/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c
new file mode 100644
index 000000000..38042003e
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c
@@ -0,0 +1,522 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USARTv2/serial_lld.c
+ * @brief   STM32 low level serial driver code.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief USART1 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+/** @brief USART2 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+/** @brief USART3 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/** @brief UART4 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+/** @brief UART5 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+/** @brief USART6 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/** @brief Driver default configuration.*/
+static const SerialConfig default_config =
+{
+  SERIAL_DEFAULT_BITRATE,
+  0,
+  USART_CR2_STOP1_BITS | USART_CR2_LINEN,
+  0
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   USART initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] config    the architecture-dependent serial driver configuration
+ */
+static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
+  USART_TypeDef *u = sdp->usart;
+
+  /* Baud rate setting.*/
+  u->BRR = (uint16_t)(sdp->clock / config->speed);
+
+  /* Note that some bits are enforced.*/
+  u->CR2 = config->cr2 | USART_CR2_LBDIE;
+  u->CR3 = config->cr3 | USART_CR3_EIE;
+  u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE |
+                         USART_CR1_RXNEIE | USART_CR1_TE |
+                         USART_CR1_RE;
+  u->ICR = 0xFFFFFFFF;
+}
+
+/**
+ * @brief   USART de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] u         pointer to an USART I/O block
+ */
+static void usart_deinit(USART_TypeDef *u) {
+
+  u->CR1 = 0;
+  u->CR2 = 0;
+  u->CR3 = 0;
+}
+
+/**
+ * @brief   Error handling routine.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] isr       USART ISR register value
+ */
+static void set_error(SerialDriver *sdp, uint32_t isr) {
+  eventflags_t sts = 0;
+
+  if (isr & USART_ISR_ORE)
+    sts |= SD_OVERRUN_ERROR;
+  if (isr & USART_ISR_PE)
+    sts |= SD_PARITY_ERROR;
+  if (isr & USART_ISR_FE)
+    sts |= SD_FRAMING_ERROR;
+  if (isr & USART_ISR_NE)
+    sts |= SD_NOISE_ERROR;
+  osalSysLockFromISR();
+  chnAddFlagsI(sdp, sts);
+  osalSysUnlockFromISR();
+}
+
+/**
+ * @brief   Common IRQ handler.
+ *
+ * @param[in] sdp       communication channel associated to the USART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+  USART_TypeDef *u = sdp->usart;
+  uint32_t cr1 = u->CR1;
+  uint32_t isr;
+
+  /* Reading and clearing status.*/
+  isr = u->ISR;
+  u->ICR = isr;
+
+  /* Error condition detection.*/
+  if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE  | USART_ISR_PE))
+    set_error(sdp, isr);
+  /* Special case, LIN break detection.*/
+  if (isr & USART_ISR_LBD) {
+    osalSysLockFromISR();
+    chnAddFlagsI(sdp, SD_BREAK_DETECTED);
+    osalSysUnlockFromISR();
+  }
+  /* Data available.*/
+  if (isr & USART_ISR_RXNE) {
+    osalSysLockFromISR();
+    sdIncomingDataI(sdp, (uint8_t)u->RDR);
+    osalSysUnlockFromISR();
+  }
+  /* Transmission buffer empty.*/
+  if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
+    msg_t b;
+    osalSysLockFromISR();
+    b = oqGetI(&sdp->oqueue);
+    if (b < Q_OK) {
+      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+      u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
+    }
+    else
+      u->TDR = b;
+    osalSysUnlockFromISR();
+  }
+  /* Physical transmission end.*/
+  if (isr & USART_ISR_TC) {
+    osalSysLockFromISR();
+    chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
+    osalSysUnlockFromISR();
+    u->CR1 = cr1 & ~USART_CR1_TCIE;
+  }
+}
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp) {
+
+  (void)qp;
+  USART1->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp) {
+
+  (void)qp;
+  USART2->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp) {
+
+  (void)qp;
+  USART3->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+static void notify4(io_queue_t *qp) {
+
+  (void)qp;
+  UART4->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+static void notify5(io_queue_t *qp) {
+
+  (void)qp;
+  UART5->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+static void notify6(io_queue_t *qp) {
+
+  (void)qp;
+  USART6->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+#if !defined(STM32_USART1_HANDLER)
+#error "STM32_USART1_HANDLER not defined"
+#endif
+/**
+ * @brief   USART1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+#if !defined(STM32_USART2_HANDLER)
+#error "STM32_USART2_HANDLER not defined"
+#endif
+/**
+ * @brief   USART2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+#if !defined(STM32_USART3_HANDLER)
+#error "STM32_USART3_HANDLER not defined"
+#endif
+/**
+ * @brief   USART3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+#if !defined(STM32_UART4_HANDLER)
+#error "STM32_UART4_HANDLER not defined"
+#endif
+/**
+ * @brief   UART4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+#if !defined(STM32_UART5_HANDLER)
+#error "STM32_UART5_HANDLER not defined"
+#endif
+/**
+ * @brief   UART5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+#if !defined(STM32_USART6_HANDLER)
+#error "STM32_USART6_HANDLER not defined"
+#endif
+/**
+ * @brief   USART1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if STM32_SERIAL_USE_USART1
+  sdObjectInit(&SD1, NULL, notify1);
+  SD1.usart = USART1;
+  SD1.clock = STM32_USART1CLK;
+#endif
+
+#if STM32_SERIAL_USE_USART2
+  sdObjectInit(&SD2, NULL, notify2);
+  SD2.usart = USART2;
+  SD2.clock = STM32_USART2CLK;
+#endif
+
+#if STM32_SERIAL_USE_USART3
+  sdObjectInit(&SD3, NULL, notify3);
+  SD3.usart = USART3;
+  SD3.clock = STM32_USART3CLK;
+#endif
+
+#if STM32_SERIAL_USE_UART4
+  sdObjectInit(&SD4, NULL, notify4);
+  SD4.usart = UART4;
+  SD4.clock = STM32_UART4CLK;
+#endif
+
+#if STM32_SERIAL_USE_UART5
+  sdObjectInit(&SD5, NULL, notify5);
+  SD5.usart = UART5;
+  SD5.clock = STM32_UART5CLK;
+#endif
+
+#if STM32_SERIAL_USE_USART6
+  sdObjectInit(&SD6, NULL, notify6);
+  SD6.usart = USART6;
+  SD6.clock = STM32_USART6CLK;
+#endif
+}
+
+/**
+ * @brief   Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] config    the architecture-dependent serial driver configuration.
+ *                      If this parameter is set to @p NULL then a default
+ *                      configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+  if (config == NULL)
+    config = &default_config;
+
+  if (sdp->state == SD_STOP) {
+#if STM32_SERIAL_USE_USART1
+    if (&SD1 == sdp) {
+      rccEnableUSART1(FALSE);
+      nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_USART2
+    if (&SD2 == sdp) {
+      rccEnableUSART2(FALSE);
+      nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_USART3
+    if (&SD3 == sdp) {
+      rccEnableUSART3(FALSE);
+      nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_UART4
+    if (&SD4 == sdp) {
+      rccEnableUART4(FALSE);
+      nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_UART5
+    if (&SD5 == sdp) {
+      rccEnableUART5(FALSE);
+      nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);
+    }
+#endif
+#if STM32_SERIAL_USE_USART6
+    if (&SD6 == sdp) {
+      rccEnableUSART6(FALSE);
+      nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);
+    }
+#endif
+  }
+  usart_init(sdp, config);
+}
+
+/**
+ * @brief   Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ *          interrupt vector.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+  if (sdp->state == SD_READY) {
+    usart_deinit(sdp->usart);
+#if STM32_SERIAL_USE_USART1
+    if (&SD1 == sdp) {
+      rccDisableUSART1(FALSE);
+      nvicDisableVector(STM32_USART1_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART2
+    if (&SD2 == sdp) {
+      rccDisableUSART2(FALSE);
+      nvicDisableVector(STM32_USART2_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART3
+    if (&SD3 == sdp) {
+      rccDisableUSART3(FALSE);
+      nvicDisableVector(STM32_USART3_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_UART4
+    if (&SD4 == sdp) {
+      rccDisableUART4(FALSE);
+      nvicDisableVector(STM32_UART4_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_UART5
+    if (&SD5 == sdp) {
+      rccDisableUART5(FALSE);
+      nvicDisableVector(STM32_UART5_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART6
+    if (&SD6 == sdp) {
+      rccDisableUSART6(FALSE);
+      nvicDisableVector(STM32_USART6_NUMBER);
+      return;
+    }
+#endif
+  }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h b/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h
new file mode 100644
index 000000000..ac7415895
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USARTv2/serial_lld.h
@@ -0,0 +1,305 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USARTv2/serial_lld.h
+ * @brief   STM32 low level serial driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   USART1 driver enable switch.
+ * @details If set to @p TRUE the support for USART1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART1             FALSE
+#endif
+
+/**
+ * @brief   USART2 driver enable switch.
+ * @details If set to @p TRUE the support for USART2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART2             FALSE
+#endif
+
+/**
+ * @brief   USART3 driver enable switch.
+ * @details If set to @p TRUE the support for USART3 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART3             FALSE
+#endif
+
+/**
+ * @brief   UART4 driver enable switch.
+ * @details If set to @p TRUE the support for UART4 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART4              FALSE
+#endif
+
+/**
+ * @brief   UART5 driver enable switch.
+ * @details If set to @p TRUE the support for UART5 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART5              FALSE
+#endif
+
+/**
+ * @brief   USART6 driver enable switch.
+ * @details If set to @p TRUE the support for USART6 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART6             FALSE
+#endif
+
+/**
+ * @brief   USART1 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART1_PRIORITY        12
+#endif
+
+/**
+ * @brief   USART2 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART2_PRIORITY        12
+#endif
+
+/**
+ * @brief   USART3 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART3_PRIORITY        12
+#endif
+
+/**
+ * @brief   UART4 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART4_PRIORITY         12
+#endif
+
+/**
+ * @brief   UART5 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART5_PRIORITY         12
+#endif
+
+/**
+ * @brief   USART6 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART6_PRIORITY        12
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1
+#error "USART1 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2
+#error "USART2 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3
+#error "USART3 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4
+#error "UART4 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5
+#error "UART5 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6
+#error "USART6 not present in the selected device"
+#endif
+
+#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 &&                 \
+    !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4  &&                 \
+    !STM32_SERIAL_USE_UART5  && !STM32_SERIAL_USE_USART6
+#error "SERIAL driver activated but no USART/UART peripheral assigned"
+#endif
+
+#if STM32_SERIAL_USE_USART1 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
+#error "Invalid IRQ priority assigned to USART1"
+#endif
+
+#if STM32_SERIAL_USE_USART2 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
+#error "Invalid IRQ priority assigned to USART2"
+#endif
+
+#if STM32_SERIAL_USE_USART3 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
+#error "Invalid IRQ priority assigned to USART3"
+#endif
+
+#if STM32_SERIAL_USE_UART4 &&                                               \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
+#error "Invalid IRQ priority assigned to UART4"
+#endif
+
+#if STM32_SERIAL_USE_UART5 &&                                               \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
+#error "Invalid IRQ priority assigned to UART5"
+#endif
+
+#if STM32_SERIAL_USE_USART6 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
+#error "Invalid IRQ priority assigned to USART6"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ *          in order to configure and start a serial driver operations.
+ * @note    This structure content is architecture dependent, each driver
+ *          implementation defines its own version and the custom static
+ *          initializers.
+ */
+typedef struct {
+  /**
+   * @brief Bit rate.
+   */
+  uint32_t                  speed;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Initialization value for the CR1 register.
+   */
+  uint32_t                  cr1;
+  /**
+   * @brief Initialization value for the CR2 register.
+   */
+  uint32_t                  cr2;
+  /**
+   * @brief Initialization value for the CR3 register.
+   */
+  uint32_t                  cr3;
+} SerialConfig;
+
+/**
+ * @brief   @p SerialDriver specific data.
+ */
+#define _serial_driver_data                                                 \
+  _base_asynchronous_channel_data                                           \
+  /* Driver state.*/                                                        \
+  sdstate_t                 state;                                          \
+  /* Input queue.*/                                                         \
+  input_queue_t             iqueue;                                         \
+  /* Output queue.*/                                                        \
+  output_queue_t               oqueue;                                      \
+  /* Input circular buffer.*/                                               \
+  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
+  /* Output circular buffer.*/                                              \
+  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
+  /* End of the mandatory fields.*/                                         \
+  /* Pointer to the USART registers block.*/                                \
+  USART_TypeDef             *usart;                                         \
+  /* Clock frequency for the associated USART/UART.*/                       \
+  uint32_t                  clock;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*
+ * Extra USARTs definitions here (missing from the ST header file).
+ */
+#define USART_CR2_STOP1_BITS    (0 << 12)   /**< @brief CR2 1 stop bit value.*/
+#define USART_CR2_STOP0P5_BITS  (1 << 12)   /**< @brief CR2 0.5 stop bit value.*/
+#define USART_CR2_STOP2_BITS    (2 << 12)   /**< @brief CR2 2 stop bit value.*/
+#define USART_CR2_STOP1P5_BITS  (3 << 12)   /**< @brief CR2 1.5 stop bit value.*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void sd_lld_init(void);
+  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+  void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c b/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c
new file mode 100644
index 000000000..54a187a39
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c
@@ -0,0 +1,590 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USARTv2/uart_lld.c
+ * @brief   STM32 low level UART driver code.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define USART1_RX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM,                     \
+                       STM32_USART1_RX_DMA_CHN)
+
+#define USART1_TX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM,                     \
+                       STM32_USART1_TX_DMA_CHN)
+
+#define USART2_RX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM,                     \
+                       STM32_USART2_RX_DMA_CHN)
+
+#define USART2_TX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM,                     \
+                       STM32_USART2_TX_DMA_CHN)
+
+#define USART3_RX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM,                     \
+                       STM32_USART3_RX_DMA_CHN)
+
+#define USART3_TX_DMA_CHANNEL                                               \
+  STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM,                     \
+                       STM32_USART3_TX_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief USART1 UART driver identifier.*/
+#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
+UARTDriver UARTD1;
+#endif
+
+/** @brief USART2 UART driver identifier.*/
+#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
+UARTDriver UARTD2;
+#endif
+
+/** @brief USART3 UART driver identifier.*/
+#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
+UARTDriver UARTD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Status bits translation.
+ *
+ * @param[in] sr        USART SR register value
+ *
+ * @return  The error flags.
+ */
+static uartflags_t translate_errors(uint32_t isr) {
+  uartflags_t sts = 0;
+
+  if (isr & USART_ISR_ORE)
+    sts |= UART_OVERRUN_ERROR;
+  if (isr & USART_ISR_PE)
+    sts |= UART_PARITY_ERROR;
+  if (isr & USART_ISR_FE)
+    sts |= UART_FRAMING_ERROR;
+  if (isr & USART_ISR_NE)
+    sts |= UART_NOISE_ERROR;
+  if (isr & USART_ISR_LBD)
+    sts |= UART_BREAK_DETECTED;
+  return sts;
+}
+
+/**
+ * @brief   Puts the receiver in the UART_RX_IDLE state.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void set_rx_idle_loop(UARTDriver *uartp) {
+  uint32_t mode;
+  
+  /* RX DMA channel preparation, if the char callback is defined then the
+     TCIE interrupt is enabled too.*/
+  if (uartp->config->rxchar_cb == NULL)
+    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
+  else
+    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
+  dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
+  dmaStreamSetTransactionSize(uartp->dmarx, 1);
+  dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);
+  dmaStreamEnable(uartp->dmarx);
+}
+
+/**
+ * @brief   USART de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void usart_stop(UARTDriver *uartp) {
+
+  /* Stops RX and TX DMA channels.*/
+  dmaStreamDisable(uartp->dmarx);
+  dmaStreamDisable(uartp->dmatx);
+  
+  /* Stops USART operations.*/
+  uartp->usart->CR1 = 0;
+  uartp->usart->CR2 = 0;
+  uartp->usart->CR3 = 0;
+}
+
+/**
+ * @brief   USART initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void usart_start(UARTDriver *uartp) {
+  uint32_t cr1;
+  USART_TypeDef *u = uartp->usart;
+
+  /* Defensive programming, starting from a clean state.*/
+  usart_stop(uartp);
+
+  /* Baud rate setting.*/
+#if defined(STM32F0XX)
+  if (uartp->usart == USART1)
+    u->BRR = STM32_USART1CLK / uartp->config->speed;
+  else
+    u->BRR = STM32_PCLK / uartp->config->speed;
+#else /* !defined(STM32F0XX) */
+  if (uartp->usart == USART1)
+    u->BRR = STM32_PCLK2 / uartp->config->speed;
+  else
+    u->BRR = STM32_PCLK1 / uartp->config->speed;
+#endif /* !defined(STM32F0XX) */
+
+  /* Resetting eventual pending status flags.*/
+  u->ICR = 0xFFFFFFFF;
+
+  /* Note that some bits are enforced because required for correct driver
+     operations.*/
+  u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
+  u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
+                                USART_CR3_EIE;
+  if (uartp->config->txend2_cb == NULL)
+    cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
+  else
+    cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE |
+          USART_CR1_TCIE;
+  u->CR1 = uartp->config->cr1 | cr1;
+
+  /* Starting the receiver idle loop.*/
+  set_rx_idle_loop(uartp);
+}
+
+/**
+ * @brief   RX DMA common service routine.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(STM32_UART_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_UART_DMA_ERROR_HOOK(uartp);
+  }
+#else
+  (void)flags;
+#endif
+
+  if (uartp->rxstate == UART_RX_IDLE) {
+    /* Receiver in idle state, a callback is generated, if enabled, for each
+       received character and then the driver stays in the same state.*/
+    if (uartp->config->rxchar_cb != NULL)
+      uartp->config->rxchar_cb(uartp, uartp->rxbuf);
+  }
+  else {
+    /* Receiver in active state, a callback is generated, if enabled, after
+       a completed transfer.*/
+    dmaStreamDisable(uartp->dmarx);
+    uartp->rxstate = UART_RX_COMPLETE;
+    if (uartp->config->rxend_cb != NULL)
+      uartp->config->rxend_cb(uartp);
+
+    /* If the callback didn't explicitly change state then the receiver
+       automatically returns to the idle state.*/
+    if (uartp->rxstate == UART_RX_COMPLETE) {
+      uartp->rxstate = UART_RX_IDLE;
+      set_rx_idle_loop(uartp);
+    }
+  }
+}
+
+/**
+ * @brief   TX DMA common service routine.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(STM32_UART_DMA_ERROR_HOOK)
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    STM32_UART_DMA_ERROR_HOOK(uartp);
+  }
+#else
+  (void)flags;
+#endif
+
+  dmaStreamDisable(uartp->dmatx);
+
+  /* A callback is generated, if enabled, after a completed transfer.*/
+  uartp->txstate = UART_TX_COMPLETE;
+  if (uartp->config->txend1_cb != NULL)
+    uartp->config->txend1_cb(uartp);
+
+  /* If the callback didn't explicitly change state then the transmitter
+     automatically returns to the idle state.*/
+  if (uartp->txstate == UART_TX_COMPLETE)
+    uartp->txstate = UART_TX_IDLE;
+}
+
+/**
+ * @brief   USART common service routine.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void serve_usart_irq(UARTDriver *uartp) {
+  uint32_t isr;
+  USART_TypeDef *u = uartp->usart;
+  
+  /* Reading and clearing status.*/
+  isr = u->ISR;
+  u->ICR = isr;
+
+  if (isr & (USART_ISR_LBD | USART_ISR_ORE | USART_ISR_NE |
+             USART_ISR_FE  | USART_ISR_PE)) {
+    if (uartp->config->rxerr_cb != NULL)
+      uartp->config->rxerr_cb(uartp, translate_errors(isr));
+  }
+  if (isr & USART_ISR_TC) {
+    /* End of transmission, a callback is generated.*/
+    if (uartp->config->txend2_cb != NULL)
+      uartp->config->txend2_cb(uartp);
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
+#if !defined(STM32_USART1_HANDLER)
+#error "STM32_USART1_HANDLER not defined"
+#endif
+/**
+ * @brief   USART1 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART1 */
+
+#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
+#if !defined(STM32_USART2_HANDLER)
+#error "STM32_USART2_HANDLER not defined"
+#endif
+/**
+ * @brief   USART2 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART2 */
+
+#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
+#if !defined(STM32_USART3_HANDLER)
+#error "STM32_USART3_HANDLER not defined"
+#endif
+/**
+ * @brief   USART3 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_UART_USE_USART3 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level UART driver initialization.
+ *
+ * @notapi
+ */
+void uart_lld_init(void) {
+
+#if STM32_UART_USE_USART1
+  uartObjectInit(&UARTD1);
+  UARTD1.usart   = USART1;
+  UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+  UARTD1.dmarx   = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
+  UARTD1.dmatx   = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
+#endif
+
+#if STM32_UART_USE_USART2
+  uartObjectInit(&UARTD2);
+  UARTD2.usart   = USART2;
+  UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+  UARTD2.dmarx   = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
+  UARTD2.dmatx   = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
+#endif
+
+#if STM32_UART_USE_USART3
+  uartObjectInit(&UARTD3);
+  UARTD3.usart   = USART3;
+  UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+  UARTD3.dmarx   = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
+  UARTD3.dmatx   = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
+#endif
+}
+
+/**
+ * @brief   Configures and activates the UART peripheral.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_start(UARTDriver *uartp) {
+
+  if (uartp->state == UART_STOP) {
+#if STM32_UART_USE_USART1
+    if (&UARTD1 == uartp) {
+      bool b;
+      b = dmaStreamAllocate(uartp->dmarx,
+                            STM32_UART_USART1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(uartp->dmatx,
+                            STM32_UART_USART1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableUSART1(FALSE);
+      nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);
+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
+                        STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
+    }
+#endif
+
+#if STM32_UART_USE_USART2
+    if (&UARTD2 == uartp) {
+      bool b;
+      b = dmaStreamAllocate(uartp->dmarx,
+                            STM32_UART_USART2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(uartp->dmatx,
+                            STM32_UART_USART2_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableUSART2(FALSE);
+      nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);
+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
+                        STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
+    }
+#endif
+
+#if STM32_UART_USE_USART3
+    if (&UARTD3 == uartp) {
+      bool b;
+      b = dmaStreamAllocate(uartp->dmarx,
+                            STM32_UART_USART3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      b = dmaStreamAllocate(uartp->dmatx,
+                            STM32_UART_USART3_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                            (void *)uartp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableUSART3(FALSE);
+      nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);
+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
+                        STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
+    }
+#endif
+
+    /* Static DMA setup, the transfer size depends on the USART settings,
+       it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
+    if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
+      uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+    dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR);
+    dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR);
+    uartp->rxbuf = 0;
+  }
+
+  uartp->rxstate = UART_RX_IDLE;
+  uartp->txstate = UART_TX_IDLE;
+  usart_start(uartp);
+}
+
+/**
+ * @brief   Deactivates the UART peripheral.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_stop(UARTDriver *uartp) {
+
+  if (uartp->state == UART_READY) {
+    usart_stop(uartp);
+    dmaStreamRelease(uartp->dmarx);
+    dmaStreamRelease(uartp->dmatx);
+
+#if STM32_UART_USE_USART1
+    if (&UARTD1 == uartp) {
+      nvicDisableVector(STM32_USART1_NUMBER);
+      rccDisableUSART1(FALSE);
+      return;
+    }
+#endif
+
+#if STM32_UART_USE_USART2
+    if (&UARTD2 == uartp) {
+      nvicDisableVector(STM32_USART2_NUMBER);
+      rccDisableUSART2(FALSE);
+      return;
+    }
+#endif
+
+#if STM32_UART_USE_USART3
+    if (&UARTD3 == uartp) {
+      nvicDisableVector(STM32_USART3_NUMBER);
+      rccDisableUSART3(FALSE);
+      return;
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts a transmission on the UART peripheral.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below
+ *          or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] n         number of data frames to send
+ * @param[in] txbuf     the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
+
+  /* TX DMA channel preparation and start.*/
+  dmaStreamSetMemory0(uartp->dmatx, txbuf);
+  dmaStreamSetTransactionSize(uartp->dmatx, n);
+  dmaStreamSetMode(uartp->dmatx, uartp->dmamode    | STM32_DMA_CR_DIR_M2P |
+                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
+  dmaStreamEnable(uartp->dmatx);
+}
+
+/**
+ * @brief   Stops any ongoing transmission.
+ * @note    Stopping a transmission also suppresses the transmission callbacks.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @return              The number of data frames not transmitted by the
+ *                      stopped transmit operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_send(UARTDriver *uartp) {
+
+  dmaStreamDisable(uartp->dmatx);
+  return dmaStreamGetTransactionSize(uartp->dmatx);
+}
+
+/**
+ * @brief   Starts a receive operation on the UART peripheral.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below
+ *          or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] n         number of data frames to send
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
+
+  /* Stopping previous activity (idle state).*/
+  dmaStreamDisable(uartp->dmarx);
+
+  /* RX DMA channel preparation and start.*/
+  dmaStreamSetMemory0(uartp->dmarx, rxbuf);
+  dmaStreamSetTransactionSize(uartp->dmarx, n);
+  dmaStreamSetMode(uartp->dmarx, uartp->dmamode    | STM32_DMA_CR_DIR_P2M |
+                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
+  dmaStreamEnable(uartp->dmarx);
+}
+
+/**
+ * @brief   Stops any ongoing receive operation.
+ * @note    Stopping a receive operation also suppresses the receive callbacks.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @return              The number of data frames not received by the
+ *                      stopped receive operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_receive(UARTDriver *uartp) {
+  size_t n;
+
+  dmaStreamDisable(uartp->dmarx);
+  n = dmaStreamGetTransactionSize(uartp->dmarx);
+  set_rx_idle_loop(uartp);
+  return n;
+}
+
+#endif /* HAL_USE_UART */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/USARTv2/uart_lld.h b/os/hal/ports/STM32/LLD/USARTv2/uart_lld.h
new file mode 100644
index 000000000..b9ee5aeb7
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USARTv2/uart_lld.h
@@ -0,0 +1,407 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USARTv2/uart_lld.h
+ * @brief   STM32 low level UART driver header.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#ifndef _UART_LLD_H_
+#define _UART_LLD_H_
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   UART driver on USART1 enable switch.
+ * @details If set to @p TRUE the support for USART1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART1               FALSE
+#endif
+
+/**
+ * @brief   UART driver on USART2 enable switch.
+ * @details If set to @p TRUE the support for USART2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART2               FALSE
+#endif
+
+/**
+ * @brief   UART driver on USART3 enable switch.
+ * @details If set to @p TRUE the support for USART3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
+#define STM32_UART_USE_USART3               FALSE
+#endif
+
+/**
+ * @brief   USART1 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART1_IRQ_PRIORITY      12
+#endif
+
+/**
+ * @brief   USART2 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART2_IRQ_PRIORITY      12
+#endif
+
+/**
+ * @brief   USART3 interrupt priority level setting.
+ */
+#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART3_IRQ_PRIORITY      12
+#endif
+
+/**
+ * @brief   USART1 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART1_DMA_PRIORITY      0
+#endif
+
+/**
+ * @brief   USART2 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART2_DMA_PRIORITY      0
+#endif
+
+/**
+ * @brief   USART3 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_UART_USART3_DMA_PRIORITY      0
+#endif
+
+/**
+ * @brief   USART1 DMA error hook.
+ * @note    The default action for DMA errors is a system halt because DMA
+ *          error can only happen because programming errors.
+ */
+#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
+#error "USART1 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
+#error "USART2 not present in the selected device"
+#endif
+
+#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
+#error "USART3 not present in the selected device"
+#endif
+
+#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 &&                     \
+    !STM32_UART_USE_USART3
+#error "UART driver activated but no USART/UART peripheral assigned"
+#endif
+
+#if STM32_UART_USE_USART1 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART1"
+#endif
+
+#if STM32_UART_USE_USART2 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART2"
+#endif
+
+#if STM32_UART_USE_USART3 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USART3"
+#endif
+
+#if STM32_UART_USE_USART1 &&                                                \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART1"
+#endif
+
+#if STM32_UART_USE_USART2 &&                                                \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART2"
+#endif
+
+#if STM32_UART_USE_USART3 &&                                                \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to USART3"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+   reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) ||  \
+                              !defined(STM32_UART_USART1_TX_DMA_STREAM))
+#error "USART1 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_STREAM) ||  \
+                              !defined(STM32_UART_USART2_TX_DMA_STREAM))
+#error "USART2 DMA streams not defined"
+#endif
+
+#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_STREAM) ||  \
+                              !defined(STM32_UART_USART3_TX_DMA_STREAM))
+#error "USART3 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_UART_USE_USART1 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM,                 \
+                           STM32_USART1_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART1 RX"
+#endif
+
+#if STM32_UART_USE_USART1 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM,                 \
+                           STM32_USART1_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART1 TX"
+#endif
+
+#if STM32_UART_USE_USART2 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM,                 \
+                           STM32_USART2_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART2 RX"
+#endif
+
+#if STM32_UART_USE_USART2 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM,                 \
+                           STM32_USART2_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART2 TX"
+#endif
+
+#if STM32_UART_USE_USART3 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM,                 \
+                           STM32_USART3_RX_DMA_MSK)
+#error "invalid DMA stream associated to USART3 RX"
+#endif
+
+#if STM32_UART_USE_USART3 &&                                                \
+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM,                 \
+                           STM32_USART3_TX_DMA_MSK)
+#error "invalid DMA stream associated to USART3 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   UART driver condition flags type.
+ */
+typedef uint32_t uartflags_t;
+
+/**
+ * @brief   Structure representing an UART driver.
+ */
+typedef struct UARTDriver UARTDriver;
+
+/**
+ * @brief   Generic UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+typedef void (*uartcb_t)(UARTDriver *uartp);
+
+/**
+ * @brief   Character received UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] c         received character
+ */
+typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
+
+/**
+ * @brief   Receive error UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] e         receive error mask
+ */
+typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief End of transmission buffer callback.
+   */
+  uartcb_t                  txend1_cb;
+  /**
+   * @brief Physical end of transmission callback.
+   */
+  uartcb_t                  txend2_cb;
+  /**
+   * @brief Receive buffer filled callback.
+   */
+  uartcb_t                  rxend_cb;
+  /**
+   * @brief Character received while out if the @p UART_RECEIVE state.
+   */
+  uartccb_t                 rxchar_cb;
+  /**
+   * @brief Receive error callback.
+   */
+  uartecb_t                 rxerr_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Bit rate.
+   */
+  uint32_t                  speed;
+  /**
+   * @brief Initialization value for the CR1 register.
+   */
+  uint32_t                  cr1;
+  /**
+   * @brief Initialization value for the CR2 register.
+   */
+  uint32_t                  cr2;
+  /**
+   * @brief Initialization value for the CR3 register.
+   */
+  uint32_t                  cr3;
+} UARTConfig;
+
+/**
+ * @brief   Structure representing an UART driver.
+ */
+struct UARTDriver {
+  /**
+   * @brief Driver state.
+   */
+  uartstate_t               state;
+  /**
+   * @brief Transmitter state.
+   */
+  uarttxstate_t             txstate;
+  /**
+   * @brief Receiver state.
+   */
+  uartrxstate_t             rxstate;
+  /**
+   * @brief Current configuration data.
+   */
+  const UARTConfig          *config;
+#if defined(UART_DRIVER_EXT_FIELDS)
+  UART_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the USART registers block.
+   */
+  USART_TypeDef             *usart;
+  /**
+   * @brief DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+  /**
+   * @brief Receive DMA channel.
+   */
+  const stm32_dma_stream_t  *dmarx;
+  /**
+   * @brief Transmit DMA channel.
+   */
+  const stm32_dma_stream_t  *dmatx;
+  /**
+   * @brief Default receive buffer while into @p UART_RX_IDLE state.
+   */
+  volatile uint16_t         rxbuf;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD1;
+#endif
+
+#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD2;
+#endif
+
+#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void uart_lld_init(void);
+  void uart_lld_start(UARTDriver *uartp);
+  void uart_lld_stop(UARTDriver *uartp);
+  void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
+  size_t uart_lld_stop_send(UARTDriver *uartp);
+  void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
+  size_t uart_lld_stop_receive(UARTDriver *uartp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_UART */
+
+#endif /* _UART_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/USBv1/stm32_usb.h b/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
index 83f349e42..83f349e42 100644
--- a/os/hal/platforms/STM32/USBv1/stm32_usb.h
+++ b/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
diff --git a/os/hal/ports/STM32/LLD/USBv1/usb_lld.c b/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
new file mode 100644
index 000000000..a8159a898
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
@@ -0,0 +1,824 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USBv1/usb_lld.c
+ * @brief   STM32 USB subsystem low level driver source.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define BTABLE_ADDR     0x0000
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief USB1 driver identifier.*/
+#if STM32_USB_USE_USB1 || defined(__DOXYGEN__)
+USBDriver USBD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   EP0 state.
+ * @note    It is an union because IN and OUT endpoints are never used at the
+ *          same time for EP0.
+ */
+static union {
+  /**
+   * @brief   IN EP0 state.
+   */
+  USBInEndpointState in;
+  /**
+   * @brief   OUT EP0 state.
+   */
+  USBOutEndpointState out;
+} ep0_state;
+
+/**
+ * @brief   Buffer for the EP0 setup packets.
+ */
+static uint8_t ep0setup_buffer[8];
+
+/**
+ * @brief   EP0 initialization structure.
+ */
+static const USBEndpointConfig ep0config = {
+  USB_EP_MODE_TYPE_CTRL,
+  _usb_ep0setup,
+  _usb_ep0in,
+  _usb_ep0out,
+  0x40,
+  0x40,
+  &ep0_state.in,
+  &ep0_state.out,
+  1,
+  ep0setup_buffer
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Resets the packet memory allocator.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ */
+static void usb_pm_reset(USBDriver *usbp) {
+
+  /* The first 64 bytes are reserved for the descriptors table. The effective
+     available RAM for endpoint buffers is just 448 bytes.*/
+  usbp->pmnext = 64;
+}
+
+/**
+ * @brief   Resets the packet memory allocator.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] size      size of the packet buffer to allocate
+ */
+static uint32_t usb_pm_alloc(USBDriver *usbp, size_t size) {
+  uint32_t next;
+
+  next = usbp->pmnext;
+  usbp->pmnext += size;
+  osalDbgAssert(usbp->pmnext <= USB_PMA_SIZE, "PMA overflow");
+  return next;
+}
+
+/**
+ * @brief   Reads from a dedicated packet buffer.
+ *
+ * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
+ * @param[out] buf      buffer where to copy the packet data
+ * @param[in] n         maximum number of bytes to copy. This value must
+ *                      not exceed the maximum packet size for this endpoint.
+ *
+ * @notapi
+ */
+static void usb_packet_read_to_buffer(stm32_usb_descriptor_t *udp,
+                                      uint8_t *buf, size_t n) {
+  uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0);
+
+  n = (n + 1) / 2;
+  while (n > 0) {
+    /* Note, this line relies on the Cortex-M3/M4 ability to perform
+       unaligned word accesses.*/
+    *(uint16_t *)buf = (uint16_t)*pmap++;
+    buf += 2;
+    n--;
+  }
+}
+
+/**
+ * @brief   Reads from a dedicated packet buffer.
+ *
+ * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
+ * @param[in] iqp       pointer to an @p input_queue_t object
+ * @param[in] n         maximum number of bytes to copy. This value must
+ *                      not exceed the maximum packet size for this endpoint.
+ *
+ * @notapi
+ */
+static void usb_packet_read_to_queue(stm32_usb_descriptor_t *udp,
+                                     input_queue_t *iqp, size_t n) {
+  size_t nhw;
+  uint32_t *pmap= USB_ADDR2PTR(udp->RXADDR0);
+
+  nhw = n / 2;
+  while (nhw > 0) {
+    uint32_t w;
+
+    w = *pmap++;
+    *iqp->q_wrptr++ = (uint8_t)w;
+    if (iqp->q_wrptr >= iqp->q_top)
+      iqp->q_wrptr = iqp->q_buffer;
+    *iqp->q_wrptr++ = (uint8_t)(w >> 8);
+    if (iqp->q_wrptr >= iqp->q_top)
+      iqp->q_wrptr = iqp->q_buffer;
+    nhw--;
+  }
+  /* Last byte for odd numbers.*/
+  if ((n & 1) != 0) {
+    *iqp->q_wrptr++ = (uint8_t)*pmap;
+    if (iqp->q_wrptr >= iqp->q_top)
+      iqp->q_wrptr = iqp->q_buffer;
+  }
+
+  /* Updating queue.*/
+  osalSysLockFromISR();
+
+  iqp->q_counter += n;
+  osalThreadDequeueAllI(&iqp->q_waiting, Q_OK);
+
+  osalSysUnlockFromISR();
+}
+
+/**
+ * @brief   Writes to a dedicated packet buffer.
+ *
+ * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
+ * @param[in] buf       buffer where to fetch the packet data
+ * @param[in] n         maximum number of bytes to copy. This value must
+ *                      not exceed the maximum packet size for this endpoint.
+ *
+ * @notapi
+ */
+static void usb_packet_write_from_buffer(stm32_usb_descriptor_t *udp,
+                                         const uint8_t *buf,
+                                         size_t n) {
+  uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0);
+
+  udp->TXCOUNT0 = (uint16_t)n;
+  n = (n + 1) / 2;
+  while (n > 0) {
+    /* Note, this line relies on the Cortex-M3/M4 ability to perform
+       unaligned word accesses.*/
+    *pmap++ = *(uint16_t *)buf;
+    buf += 2;
+    n--;
+  }
+}
+
+/**
+ * @brief   Writes to a dedicated packet buffer.
+ *
+ * @param[in] udp       pointer to a @p stm32_usb_descriptor_t
+ * @param[in] buf       buffer where to fetch the packet data
+ * @param[in] n         maximum number of bytes to copy. This value must
+ *                      not exceed the maximum packet size for this endpoint.
+ *
+ * @notapi
+ */
+static void usb_packet_write_from_queue(stm32_usb_descriptor_t *udp,
+                                        output_queue_t *oqp, size_t n) {
+  size_t nhw;
+  syssts_t sts;
+  uint32_t *pmap = USB_ADDR2PTR(udp->TXADDR0);
+
+  udp->TXCOUNT0 = (uint16_t)n;
+  nhw = n / 2;
+  while (nhw > 0) {
+    uint32_t w;
+
+    w  = (uint32_t)*oqp->q_rdptr++;
+    if (oqp->q_rdptr >= oqp->q_top)
+      oqp->q_rdptr = oqp->q_buffer;
+    w |= (uint32_t)*oqp->q_rdptr++ << 8;
+    if (oqp->q_rdptr >= oqp->q_top)
+      oqp->q_rdptr = oqp->q_buffer;
+    *pmap++ = w;
+    nhw--;
+  }
+
+  /* Last byte for odd numbers.*/
+  if ((n & 1) != 0) {
+    *pmap = (uint32_t)*oqp->q_rdptr++;
+    if (oqp->q_rdptr >= oqp->q_top)
+      oqp->q_rdptr = oqp->q_buffer;
+  }
+
+  /* Updating queue.*/
+  sts = osalSysGetStatusAndLockX();
+
+  oqp->q_counter += n;
+  osalThreadDequeueAllI(&oqp->q_waiting, Q_OK);
+
+  osalSysRestoreStatusX(sts);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_USB_USE_USB1 || defined(__DOXYGEN__)
+#if !defined(STM32_USB1_HP_HANDLER)
+#error "STM32_USB1_HP_HANDLER not defined"
+#endif
+/**
+ * @brief   USB high priority interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USB1_HP_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  CH_IRQ_EPILOGUE();
+}
+
+#if !defined(STM32_USB1_LP_HANDLER)
+#error "STM32_USB1_LP_HANDLER not defined"
+#endif
+/**
+ * @brief   USB low priority interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USB1_LP_HANDLER) {
+  uint32_t istr;
+  USBDriver *usbp = &USBD1;
+
+  CH_IRQ_PROLOGUE();
+
+  istr = STM32_USB->ISTR;
+
+  /* USB bus reset condition handling.*/
+  if (istr & ISTR_RESET) {
+    _usb_reset(usbp);
+    _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
+    STM32_USB->ISTR = ~ISTR_RESET;
+  }
+
+  /* USB bus SUSPEND condition handling.*/
+  if (istr & ISTR_SUSP) {
+    STM32_USB->CNTR |= CNTR_FSUSP;
+    _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND);
+#if STM32_USB_LOW_POWER_ON_SUSPEND
+    STM32_USB->CNTR |= CNTR_LP_MODE;
+#endif
+    STM32_USB->ISTR = ~ISTR_SUSP;
+  }
+
+  /* USB bus WAKEUP condition handling.*/
+  if (istr & ISTR_WKUP) {
+    uint32_t fnr = STM32_USB->FNR;
+    if (!(fnr & FNR_RXDP)) {
+      STM32_USB->CNTR &= ~CNTR_FSUSP;
+      _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP);
+    }
+#if STM32_USB_LOW_POWER_ON_SUSPEND
+    else {
+      /* Just noise, going back in SUSPEND mode, reference manual 22.4.5,
+         table 169.*/
+      STM32_USB->CNTR |= CNTR_LP_MODE;
+    }
+#endif
+    STM32_USB->ISTR = ~ISTR_WKUP;
+  }
+
+  /* SOF handling.*/
+  if (istr & ISTR_SOF) {
+    _usb_isr_invoke_sof_cb(usbp);
+    STM32_USB->ISTR = ~ISTR_SOF;
+  }
+
+  /* Endpoint events handling.*/
+  while (istr & ISTR_CTR) {
+    size_t n;
+    uint32_t ep;
+    uint32_t epr = STM32_USB->EPR[ep = istr & ISTR_EP_ID_MASK];
+    const USBEndpointConfig *epcp = usbp->epc[ep];
+
+    if (epr & EPR_CTR_TX) {
+      size_t transmitted;
+      /* IN endpoint, transmission.*/
+      EPR_CLEAR_CTR_TX(ep);
+
+      transmitted = (size_t)USB_GET_DESCRIPTOR(ep)->TXCOUNT0;
+      epcp->in_state->txcnt  += transmitted;
+      n = epcp->in_state->txsize - epcp->in_state->txcnt;
+      if (n > 0) {
+        /* Transfer not completed, there are more packets to send.*/
+        if (n > epcp->in_maxsize)
+          n = epcp->in_maxsize;
+
+        if (epcp->in_state->txqueued)
+          usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep),
+                                      epcp->in_state->mode.queue.txqueue,
+                                      n);
+        else {
+          epcp->in_state->mode.linear.txbuf += transmitted;
+          usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep),
+                                       epcp->in_state->mode.linear.txbuf,
+                                       n);
+        }
+        osalSysLockFromISR();
+        usb_lld_start_in(usbp, ep);
+        osalSysUnlockFromISR();
+      }
+      else {
+        /* Transfer completed, invokes the callback.*/
+        _usb_isr_invoke_in_cb(usbp, ep);
+      }
+    }
+    if (epr & EPR_CTR_RX) {
+      EPR_CLEAR_CTR_RX(ep);
+      /* OUT endpoint, receive.*/
+      if (epr & EPR_SETUP) {
+        /* Setup packets handling, setup packets are handled using a
+           specific callback.*/
+        _usb_isr_invoke_setup_cb(usbp, ep);
+      }
+      else {
+        stm32_usb_descriptor_t *udp = USB_GET_DESCRIPTOR(ep);
+        n = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK;
+
+        /* Reads the packet into the defined buffer.*/
+        if (epcp->out_state->rxqueued)
+          usb_packet_read_to_queue(udp,
+                                   epcp->out_state->mode.queue.rxqueue,
+                                   n);
+        else {
+          usb_packet_read_to_buffer(udp,
+                                    epcp->out_state->mode.linear.rxbuf,
+                                    n);
+          epcp->out_state->mode.linear.rxbuf += n;
+        }
+        /* Transaction data updated.*/
+        epcp->out_state->rxcnt              += n;
+        epcp->out_state->rxsize             -= n;
+        epcp->out_state->rxpkts             -= 1;
+
+        /* The transaction is completed if the specified number of packets
+           has been received or the current packet is a short packet.*/
+        if ((n < epcp->out_maxsize) || (epcp->out_state->rxpkts == 0)) {
+          /* Transfer complete, invokes the callback.*/
+          _usb_isr_invoke_out_cb(usbp, ep);
+        }
+        else {
+          /* Transfer not complete, there are more packets to receive.*/
+          EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID);
+        }
+      }
+    }
+    istr = STM32_USB->ISTR;
+  }
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level USB driver initialization.
+ *
+ * @notapi
+ */
+void usb_lld_init(void) {
+
+  /* Driver initialization.*/
+  usbObjectInit(&USBD1);
+}
+
+/**
+ * @brief   Configures and activates the USB peripheral.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_start(USBDriver *usbp) {
+
+  if (usbp->state == USB_STOP) {
+    /* Clock activation.*/
+#if STM32_USB_USE_USB1
+    if (&USBD1 == usbp) {
+      /* USB clock enabled.*/
+      rccEnableUSB(FALSE);
+      /* Powers up the transceiver while holding the USB in reset state.*/
+      STM32_USB->CNTR = CNTR_FRES;
+      /* Enabling the USB IRQ vectors, this also gives enough time to allow
+         the transceiver power up (1uS).*/
+      nvicEnableVector(STM32_USB1_HP_NUMBER, STM32_USB_USB1_HP_IRQ_PRIORITY);
+      nvicEnableVector(STM32_USB1_LP_NUMBER, STM32_USB_USB1_LP_IRQ_PRIORITY);
+      /* Releases the USB reset.*/
+      STM32_USB->CNTR = 0;
+    }
+#endif
+    /* Reset procedure enforced on driver start.*/
+    _usb_reset(usbp);
+  }
+  /* Configuration.*/
+}
+
+/**
+ * @brief   Deactivates the USB peripheral.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_stop(USBDriver *usbp) {
+
+  /* If in ready state then disables the USB clock.*/
+  if (usbp->state == USB_STOP) {
+#if STM32_USB_USE_USB1
+    if (&USBD1 == usbp) {
+      nvicDisableVector(STM32_USB1_HP_NUMBER);
+      nvicDisableVector(STM32_USB1_LP_NUMBER);
+      STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES;
+      rccDisableUSB(FALSE);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   USB low level reset routine.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_reset(USBDriver *usbp) {
+  uint32_t cntr;
+
+  /* Post reset initialization.*/
+  STM32_USB->BTABLE = 0;
+  STM32_USB->ISTR   = 0;
+  STM32_USB->DADDR  = DADDR_EF;
+  cntr              = /*CNTR_ESOFM | */ CNTR_RESETM  | CNTR_SUSPM |
+                      CNTR_WKUPM | /*CNTR_ERRM | CNTR_PMAOVRM |*/ CNTR_CTRM;
+  /* The SOF interrupt is only enabled if a callback is defined for
+     this service because it is an high rate source.*/
+  if (usbp->config->sof_cb != NULL)
+    cntr |= CNTR_SOFM;
+  STM32_USB->CNTR = cntr;
+
+  /* Resets the packet memory allocator.*/
+  usb_pm_reset(usbp);
+
+  /* EP0 initialization.*/
+  usbp->epc[0] = &ep0config;
+  usb_lld_init_endpoint(usbp, 0);
+}
+
+/**
+ * @brief   Sets the USB address.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_set_address(USBDriver *usbp) {
+
+  STM32_USB->DADDR = (uint32_t)(usbp->address) | DADDR_EF;
+}
+
+/**
+ * @brief   Enables an endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
+  uint16_t nblocks, epr;
+  stm32_usb_descriptor_t *dp;
+  const USBEndpointConfig *epcp = usbp->epc[ep];
+
+  /* Setting the endpoint type.*/
+  switch (epcp->ep_mode & USB_EP_MODE_TYPE) {
+  case USB_EP_MODE_TYPE_ISOC:
+    epr = EPR_EP_TYPE_ISO;
+    break;
+  case USB_EP_MODE_TYPE_BULK:
+    epr = EPR_EP_TYPE_BULK;
+    break;
+  case USB_EP_MODE_TYPE_INTR:
+    epr = EPR_EP_TYPE_INTERRUPT;
+    break;
+  default:
+    epr = EPR_EP_TYPE_CONTROL;
+  }
+
+  /* IN endpoint initially in NAK mode.*/
+  if (epcp->in_cb != NULL)
+    epr |= EPR_STAT_TX_NAK;
+
+  /* OUT endpoint initially in NAK mode.*/
+  if (epcp->out_cb != NULL)
+    epr |= EPR_STAT_RX_NAK;
+
+  /* EPxR register setup.*/
+  EPR_SET(ep, epr | ep);
+  EPR_TOGGLE(ep, epr);
+
+  /* Endpoint size and address initialization.*/
+  if (epcp->out_maxsize > 62)
+    nblocks = (((((epcp->out_maxsize - 1) | 0x1f) + 1) / 32) << 10) |
+              0x8000;
+  else
+    nblocks = ((((epcp->out_maxsize - 1) | 1) + 1) / 2) << 10;
+  dp = USB_GET_DESCRIPTOR(ep);
+  dp->TXCOUNT0 = 0;
+  dp->RXCOUNT0 = nblocks;
+  dp->TXADDR0  = usb_pm_alloc(usbp, epcp->in_maxsize);
+  dp->RXADDR0  = usb_pm_alloc(usbp, epcp->out_maxsize);
+}
+
+/**
+ * @brief   Disables all the active endpoints except the endpoint zero.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_disable_endpoints(USBDriver *usbp) {
+  unsigned i;
+
+  /* Resets the packet memory allocator.*/
+  usb_pm_reset(usbp);
+
+  /* Disabling all endpoints.*/
+  for (i = 1; i <= USB_ENDOPOINTS_NUMBER; i++) {
+    EPR_TOGGLE(i, 0);
+    EPR_SET(i, 0);
+  }
+}
+
+/**
+ * @brief   Returns the status of an OUT endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ * @return              The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED  The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE   The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
+
+  (void)usbp;
+  switch (STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) {
+  case EPR_STAT_RX_DIS:
+    return EP_STATUS_DISABLED;
+  case EPR_STAT_RX_STALL:
+    return EP_STATUS_STALLED;
+  default:
+    return EP_STATUS_ACTIVE;
+  }
+}
+
+/**
+ * @brief   Returns the status of an IN endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ * @return              The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED  The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE   The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
+
+  (void)usbp;
+  switch (STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) {
+  case EPR_STAT_TX_DIS:
+    return EP_STATUS_DISABLED;
+  case EPR_STAT_TX_STALL:
+    return EP_STATUS_STALLED;
+  default:
+    return EP_STATUS_ACTIVE;
+  }
+}
+
+/**
+ * @brief   Reads a setup packet from the dedicated packet buffer.
+ * @details This function must be invoked in the context of the @p setup_cb
+ *          callback in order to read the received setup packet.
+ * @pre     In order to use this function the endpoint must have been
+ *          initialized as a control endpoint.
+ * @post    The endpoint is ready to accept another packet.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ * @param[out] buf      buffer where to copy the packet data
+ *
+ * @notapi
+ */
+void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
+  uint32_t *pmap;
+  stm32_usb_descriptor_t *udp;
+  uint32_t n;
+
+  (void)usbp;
+  udp = USB_GET_DESCRIPTOR(ep);
+  pmap = USB_ADDR2PTR(udp->RXADDR0);
+  for (n = 0; n < 4; n++) {
+    *(uint16_t *)buf = (uint16_t)*pmap++;
+    buf += 2;
+  }
+}
+
+/**
+ * @brief   Prepares for a receive operation.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
+  USBOutEndpointState *osp = usbp->epc[ep]->out_state;
+
+  /* Transfer initialization.*/
+  if (osp->rxsize == 0)         /* Special case for zero sized packets.*/
+    osp->rxpkts = 1;
+  else
+    osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
+                             usbp->epc[ep]->out_maxsize);
+}
+
+/**
+ * @brief   Prepares for a transmit operation.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
+  size_t n;
+  USBInEndpointState *isp = usbp->epc[ep]->in_state;
+
+  /* Transfer initialization.*/
+  n = isp->txsize;
+  if (n > (size_t)usbp->epc[ep]->in_maxsize)
+    n = (size_t)usbp->epc[ep]->in_maxsize;
+
+  if (isp->txqueued)
+    usb_packet_write_from_queue(USB_GET_DESCRIPTOR(ep),
+                                isp->mode.queue.txqueue, n);
+  else
+    usb_packet_write_from_buffer(USB_GET_DESCRIPTOR(ep),
+                                 isp->mode.linear.txbuf, n);
+}
+
+/**
+ * @brief   Starts a receive operation on an OUT endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
+
+  (void)usbp;
+
+  EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID);
+}
+
+/**
+ * @brief   Starts a transmit operation on an IN endpoint.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
+
+  (void)usbp;
+
+  EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID);
+}
+
+/**
+ * @brief   Brings an OUT endpoint in the stalled state.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
+
+  (void)usbp;
+
+  EPR_SET_STAT_RX(ep, EPR_STAT_RX_STALL);
+}
+
+/**
+ * @brief   Brings an IN endpoint in the stalled state.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
+
+  (void)usbp;
+
+  EPR_SET_STAT_TX(ep, EPR_STAT_TX_STALL);
+}
+
+/**
+ * @brief   Brings an OUT endpoint in the active state.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
+
+  (void)usbp;
+
+  /* Makes sure to not put to NAK an endpoint that is already
+     transferring.*/
+  if ((STM32_USB->EPR[ep] & EPR_STAT_RX_MASK) != EPR_STAT_RX_VALID)
+    EPR_SET_STAT_TX(ep, EPR_STAT_RX_NAK);
+}
+
+/**
+ * @brief   Brings an IN endpoint in the active state.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
+
+  (void)usbp;
+
+  /* Makes sure to not put to NAK an endpoint that is already
+     transferring.*/
+  if ((STM32_USB->EPR[ep] & EPR_STAT_TX_MASK) != EPR_STAT_TX_VALID)
+    EPR_SET_STAT_TX(ep, EPR_STAT_TX_NAK);
+}
+
+#endif /* HAL_USE_USB */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/USBv1/usb_lld.h b/os/hal/ports/STM32/LLD/USBv1/usb_lld.h
new file mode 100644
index 000000000..828129032
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/USBv1/usb_lld.h
@@ -0,0 +1,442 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/USBv1/usb_lld.h
+ * @brief   STM32 USB subsystem low level driver header.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#ifndef _USB_LLD_H_
+#define _USB_LLD_H_
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+#include "stm32_usb.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Maximum endpoint address.
+ */
+#define USB_MAX_ENDPOINTS                   USB_ENDOPOINTS_NUMBER
+
+/**
+ * @brief   Status stage handling method.
+ */
+#define USB_EP0_STATUS_STAGE                USB_EP0_STATUS_STAGE_SW
+
+/**
+ * @brief   This device requires the address change after the status packet.
+ */
+#define USB_SET_ADDRESS_MODE                USB_LATE_SET_ADDRESS
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   USB1 driver enable switch.
+ * @details If set to @p TRUE the support for USB1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_USB_USE_USB1) || defined(__DOXYGEN__)
+#define STM32_USB_USE_USB1                  FALSE
+#endif
+
+/**
+ * @brief   Enables the USB device low power mode on suspend.
+ */
+#if !defined(STM32_USB_LOW_POWER_ON_SUSPEND) || defined(__DOXYGEN__)
+#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE
+#endif
+
+/**
+ * @brief   USB1 interrupt priority level setting.
+ */
+#if !defined(STM32_USB_USB1_HP_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_USB_USB1_HP_IRQ_PRIORITY      13
+#endif
+
+/**
+ * @brief   USB1 interrupt priority level setting.
+ */
+#if !defined(STM32_USB_USB1_LP_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_USB_USB1_LP_IRQ_PRIORITY      14
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_USB_USE_USB1 && !STM32_HAS_USB
+#error "USB not present in the selected device"
+#endif
+
+#if !STM32_USB_USE_USB1
+#error "USB driver activated but no USB peripheral assigned"
+#endif
+
+#if STM32_USB_USE_USB1 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_HP_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USB HP"
+#endif
+
+#if STM32_USB_USE_USB1 &&                                                \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_USB_USB1_LP_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USB LP"
+#endif
+
+#if STM32_USBCLK != 48000000
+#error "the USB driver requires a 48MHz clock"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of an IN endpoint state structure.
+ */
+typedef struct {
+  /**
+   * @brief   Buffer mode, queue or linear.
+   */
+  bool                          txqueued;
+  /**
+   * @brief   Requested transmit transfer size.
+   */
+  size_t                        txsize;
+  /**
+   * @brief   Transmitted bytes so far.
+   */
+  size_t                        txcnt;
+  union {
+    struct {
+      /**
+       * @brief   Pointer to the transmission linear buffer.
+       */
+      const uint8_t             *txbuf;
+    } linear;
+    struct {
+      /**
+       * @brief   Pointer to the output queue.
+       */
+      output_queue_t            *txqueue;
+    } queue;
+    /* End of the mandatory fields.*/
+  } mode;
+} USBInEndpointState;
+
+/**
+ * @brief   Type of an OUT endpoint state structure.
+ */
+typedef struct {
+  /**
+   * @brief   Buffer mode, queue or linear.
+   */
+  bool                          rxqueued;
+  /**
+   * @brief   Requested receive transfer size.
+   */
+  size_t                        rxsize;
+  /**
+   * @brief   Received bytes so far.
+   */
+  size_t                        rxcnt;
+  union {
+    struct {
+      /**
+       * @brief   Pointer to the receive linear buffer.
+       */
+      uint8_t                   *rxbuf;
+    } linear;
+    struct {
+      /**
+       * @brief   Pointer to the input queue.
+       */
+      input_queue_t            *rxqueue;
+    } queue;
+  } mode;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Number of packets to receive.
+   */
+  uint16_t                      rxpkts;
+} USBOutEndpointState;
+
+/**
+ * @brief   Type of an USB endpoint configuration structure.
+ * @note    Platform specific restrictions may apply to endpoints.
+ */
+typedef struct {
+  /**
+   * @brief   Type and mode of the endpoint.
+   */
+  uint32_t                      ep_mode;
+  /**
+   * @brief   Setup packet notification callback.
+   * @details This callback is invoked when a setup packet has been
+   *          received.
+   * @post    The application must immediately call @p usbReadPacket() in
+   *          order to access the received packet.
+   * @note    This field is only valid for @p USB_EP_MODE_TYPE_CTRL
+   *          endpoints, it should be set to @p NULL for other endpoint
+   *          types.
+   */
+  usbepcallback_t               setup_cb;
+  /**
+   * @brief   IN endpoint notification callback.
+   * @details This field must be set to @p NULL if the IN endpoint is not
+   *          used.
+   */
+  usbepcallback_t               in_cb;
+  /**
+   * @brief   OUT endpoint notification callback.
+   * @details This field must be set to @p NULL if the OUT endpoint is not
+   *          used.
+   */
+  usbepcallback_t               out_cb;
+  /**
+   * @brief   IN endpoint maximum packet size.
+   * @details This field must be set to zero if the IN endpoint is not
+   *          used.
+   */
+  uint16_t                      in_maxsize;
+  /**
+   * @brief   OUT endpoint maximum packet size.
+   * @details This field must be set to zero if the OUT endpoint is not
+   *          used.
+   */
+  uint16_t                      out_maxsize;
+  /**
+   * @brief   @p USBEndpointState associated to the IN endpoint.
+   * @details This structure maintains the state of the IN endpoint.
+   */
+  USBInEndpointState            *in_state;
+  /**
+   * @brief   @p USBEndpointState associated to the OUT endpoint.
+   * @details This structure maintains the state of the OUT endpoint.
+   */
+  USBOutEndpointState           *out_state;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Reserved field, not currently used.
+   * @note    Initialize this field to 1 in order to be forward compatible.
+   */
+  uint16_t                      ep_buffers;
+  /**
+   * @brief   Pointer to a buffer for setup packets.
+   * @details Setup packets require a dedicated 8-bytes buffer, set this
+   *          field to @p NULL for non-control endpoints.
+   */
+  uint8_t                       *setup_buf;
+} USBEndpointConfig;
+
+/**
+ * @brief   Type of an USB driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief   USB events callback.
+   * @details This callback is invoked when an USB driver event is registered.
+   */
+  usbeventcb_t                  event_cb;
+  /**
+   * @brief   Device GET_DESCRIPTOR request callback.
+   * @note    This callback is mandatory and cannot be set to @p NULL.
+   */
+  usbgetdescriptor_t            get_descriptor_cb;
+  /**
+   * @brief   Requests hook callback.
+   * @details This hook allows to be notified of standard requests or to
+   *          handle non standard requests.
+   */
+  usbreqhandler_t               requests_hook_cb;
+  /**
+   * @brief   Start Of Frame callback.
+   */
+  usbcallback_t                 sof_cb;
+  /* End of the mandatory fields.*/
+} USBConfig;
+
+/**
+ * @brief   Structure representing an USB driver.
+ */
+struct USBDriver {
+  /**
+   * @brief   Driver state.
+   */
+  usbstate_t                    state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const USBConfig               *config;
+  /**
+   * @brief   Bit map of the transmitting IN endpoints.
+   */
+  uint16_t                      transmitting;
+  /**
+   * @brief   Bit map of the receiving OUT endpoints.
+   */
+  uint16_t                      receiving;
+  /**
+   * @brief   Active endpoints configurations.
+   */
+  const USBEndpointConfig       *epc[USB_MAX_ENDPOINTS + 1];
+  /**
+   * @brief   Fields available to user, it can be used to associate an
+   *          application-defined handler to an IN endpoint.
+   * @note    The base index is one, the endpoint zero does not have a
+   *          reserved element in this array.
+   */
+  void                          *in_params[USB_MAX_ENDPOINTS];
+  /**
+   * @brief   Fields available to user, it can be used to associate an
+   *          application-defined handler to an OUT endpoint.
+   * @note    The base index is one, the endpoint zero does not have a
+   *          reserved element in this array.
+   */
+  void                          *out_params[USB_MAX_ENDPOINTS];
+  /**
+   * @brief   Endpoint 0 state.
+   */
+  usbep0state_t                 ep0state;
+  /**
+   * @brief   Next position in the buffer to be transferred through endpoint 0.
+   */
+  uint8_t                       *ep0next;
+  /**
+   * @brief   Number of bytes yet to be transferred through endpoint 0.
+   */
+  size_t                        ep0n;
+  /**
+   * @brief   Endpoint 0 end transaction callback.
+   */
+  usbcallback_t                 ep0endcb;
+  /**
+   * @brief   Setup packet buffer.
+   */
+  uint8_t                       setup[8];
+  /**
+   * @brief   Current USB device status.
+   */
+  uint16_t                      status;
+  /**
+   * @brief   Assigned USB address.
+   */
+  uint8_t                       address;
+  /**
+   * @brief   Current USB device configuration.
+   */
+  uint8_t                       configuration;
+#if defined(USB_DRIVER_EXT_FIELDS)
+  USB_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Pointer to the next address in the packet memory.
+   */
+  uint32_t                      pmnext;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the current frame number.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @return              The current frame number.
+ *
+ * @notapi
+ */
+#define usb_lld_get_frame_number(usbp) (STM32_USB->FNR & FNR_FN_MASK)
+
+/**
+ * @brief   Returns the exact size of a receive transaction.
+ * @details The received size can be different from the size specified in
+ *          @p usbStartReceiveI() because the last packet could have a size
+ *          different from the expected one.
+ * @pre     The OUT endpoint must have been configured in transaction mode
+ *          in order to use this function.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ * @return              Received data size.
+ *
+ * @notapi
+ */
+#define usb_lld_get_transaction_size(usbp, ep)                              \
+  ((usbp)->epc[ep]->out_state->rxcnt)
+
+/**
+ * @brief   Returns the exact size of a received packet.
+ * @pre     The OUT endpoint must have been configured in packet mode
+ *          in order to use this function.
+ *
+ * @param[in] usbp      pointer to the @p USBDriver object
+ * @param[in] ep        endpoint number
+ * @return              Received data size.
+ *
+ * @notapi
+ */
+#define  usb_lld_get_packet_size(usbp, ep)                                  \
+  ((size_t)USB_GET_DESCRIPTOR(ep)->RXCOUNT & RXCOUNT_COUNT_MASK)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_USB_USE_USB1 && !defined(__DOXYGEN__)
+extern USBDriver USBD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void usb_lld_init(void);
+  void usb_lld_start(USBDriver *usbp);
+  void usb_lld_stop(USBDriver *usbp);
+  void usb_lld_reset(USBDriver *usbp);
+  void usb_lld_set_address(USBDriver *usbp);
+  void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
+  void usb_lld_disable_endpoints(USBDriver *usbp);
+  usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
+  usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
+  void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
+  void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
+  void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
+  void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
+  void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
+  void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
+  void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
+  void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
+  void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_USB */
+
+#endif /* _USB_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/can_lld.c b/os/hal/ports/STM32/LLD/can_lld.c
new file mode 100644
index 000000000..48820f171
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/can_lld.c
@@ -0,0 +1,701 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/can_lld.c
+ * @brief   STM32 CAN subsystem low level driver source.
+ *
+ * @addtogroup CAN
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_CAN || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief CAN1 driver identifier.*/
+#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)
+CANDriver CAND1;
+#endif
+
+/** @brief CAN2 driver identifier.*/
+#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)
+CANDriver CAND2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Programs the filters.
+ *
+ * @param[in] can2sb    number of the first filter assigned to CAN2
+ * @param[in] num       number of entries in the filters array, if zero then
+ *                      a default filter is programmed
+ * @param[in] cfp       pointer to the filters array, can be @p NULL if
+ *                      (num == 0)
+ *
+ * @notapi
+ */
+static void can_lld_set_filters(uint32_t can2sb,
+                                uint32_t num,
+                                const CANFilter *cfp) {
+
+  /* Temporarily enabling CAN1 clock.*/
+  rccEnableCAN1(FALSE);
+
+  /* Filters initialization.*/
+  CAN1->FMR = (CAN1->FMR & 0xFFFF0000) | (can2sb << 8) | CAN_FMR_FINIT;
+  if (num > 0) {
+    uint32_t i, fmask;
+
+    /* All filters cleared.*/
+    CAN1->FA1R = 0;
+    CAN1->FM1R = 0;
+    CAN1->FS1R = 0;
+    CAN1->FFA1R = 0;
+    for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) {
+      CAN1->sFilterRegister[i].FR1 = 0;
+      CAN1->sFilterRegister[i].FR2 = 0;
+    }
+
+    /* Scanning the filters array.*/
+    for (i = 0; i < num; i++) {
+      fmask = 1 << cfp->filter;
+      if (cfp->mode)
+        CAN1->FM1R |= fmask;
+      if (cfp->scale)
+        CAN1->FS1R |= fmask;
+      if (cfp->assignment)
+        CAN1->FFA1R |= fmask;
+      CAN1->sFilterRegister[cfp->filter].FR1 = cfp->register1;
+      CAN1->sFilterRegister[cfp->filter].FR2 = cfp->register2;
+      CAN1->FA1R |= fmask;
+      cfp++;
+    }
+  }
+  else {
+    /* Setting up a single default filter that enables everything for both
+       CANs.*/
+    CAN1->sFilterRegister[0].FR1 = 0;
+    CAN1->sFilterRegister[0].FR2 = 0;
+    CAN1->sFilterRegister[can2sb].FR1 = 0;
+    CAN1->sFilterRegister[can2sb].FR2 = 0;
+    CAN1->FM1R = 0;
+    CAN1->FFA1R = 0;
+    CAN1->FS1R = 1 | (1 << can2sb);
+    CAN1->FA1R = 1 | (1 << can2sb);
+  }
+  CAN1->FMR &= ~CAN_FMR_FINIT;
+
+  /* Clock disabled, it will be enabled again in can_lld_start().*/
+  rccDisableCAN1(FALSE);
+}
+
+/**
+ * @brief   Common TX ISR handler.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_tx_handler(CANDriver *canp) {
+
+  /* No more events until a message is transmitted.*/
+  canp->can->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2;
+  osalSysLockFromISR();
+  osalThreadDequeueAllI(&canp->txqueue, MSG_OK);
+  osalEventBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1));
+  osalSysUnlockFromISR();
+}
+
+/**
+ * @brief   Common RX0 ISR handler.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_rx0_handler(CANDriver *canp) {
+  uint32_t rf0r;
+
+  rf0r = canp->can->RF0R;
+  if ((rf0r & CAN_RF0R_FMP0) > 0) {
+    /* No more receive events until the queue 0 has been emptied.*/
+    canp->can->IER &= ~CAN_IER_FMPIE0;
+    osalSysLockFromISR();
+    osalThreadDequeueAllI(&canp->rxqueue, MSG_OK);
+    osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1));
+    osalSysUnlockFromISR();
+  }
+  if ((rf0r & CAN_RF0R_FOVR0) > 0) {
+    /* Overflow events handling.*/
+    canp->can->RF0R = CAN_RF0R_FOVR0;
+    osalSysLockFromISR();
+    osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
+    osalSysUnlockFromISR();
+  }
+}
+
+/**
+ * @brief   Common RX1 ISR handler.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_rx1_handler(CANDriver *canp) {
+  uint32_t rf1r;
+
+  rf1r = canp->can->RF1R;
+  if ((rf1r & CAN_RF1R_FMP1) > 0) {
+    /* No more receive events until the queue 0 has been emptied.*/
+    canp->can->IER &= ~CAN_IER_FMPIE1;
+    osalSysLockFromISR();
+    osalThreadDequeueAllI(&canp->rxqueue, MSG_OK);
+    osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2));
+    osalSysUnlockFromISR();
+  }
+  if ((rf1r & CAN_RF1R_FOVR1) > 0) {
+    /* Overflow events handling.*/
+    canp->can->RF1R = CAN_RF1R_FOVR1;
+    osalSysLockFromISR();
+    osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);
+    osalSysUnlockFromISR();
+  }
+}
+
+/**
+ * @brief   Common SCE ISR handler.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_sce_handler(CANDriver *canp) {
+  uint32_t msr;
+
+  msr = canp->can->MSR;
+  canp->can->MSR = CAN_MSR_ERRI | CAN_MSR_WKUI | CAN_MSR_SLAKI;
+  /* Wakeup event.*/
+#if CAN_USE_SLEEP_MODE
+  if (msr & CAN_MSR_WKUI) {
+    canp->state = CAN_READY;
+    canp->can->MCR &= ~CAN_MCR_SLEEP;
+    osalSysLockFromISR();
+    osalEventBroadcastFlagsI(&canp->wakeup_event, 0);
+    osalSysUnlockFromISR();
+  }
+#endif /* CAN_USE_SLEEP_MODE */
+  /* Error event.*/
+  if (msr & CAN_MSR_ERRI) {
+    eventflags_t flags;
+    uint32_t esr = canp->can->ESR;
+
+    canp->can->ESR &= ~CAN_ESR_LEC;
+    flags = (eventflags_t)(esr & 7);
+    if ((esr & CAN_ESR_LEC) > 0)
+      flags |= CAN_FRAMING_ERROR;
+
+    osalSysLockFromISR();
+    /* The content of the ESR register is copied unchanged in the upper
+       half word of the listener flags mask.*/
+    osalEventBroadcastFlagsI(&canp->error_event, flags | (eventflags_t)(esr << 16));
+    osalSysUnlockFromISR();
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)
+/**
+ * @brief   CAN1 TX interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_tx_handler(&CAND1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*
+ * @brief   CAN1 RX0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_rx0_handler(&CAND1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN1 RX1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_rx1_handler(&CAND1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN1 SCE interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_sce_handler(&CAND1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_CAN_USE_CAN1 */
+
+#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)
+/**
+ * @brief   CAN2 TX interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_tx_handler(&CAND2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*
+ * @brief   CAN2 RX0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_rx0_handler(&CAND2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN2 RX1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_rx1_handler(&CAND2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN2 SCE interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_sce_handler(&CAND2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_CAN_USE_CAN2 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level CAN driver initialization.
+ *
+ * @notapi
+ */
+void can_lld_init(void) {
+
+#if STM32_CAN_USE_CAN1
+  /* Driver initialization.*/
+  canObjectInit(&CAND1);
+  CAND1.can = CAN1;
+#endif
+#if STM32_CAN_USE_CAN2
+  /* Driver initialization.*/
+  canObjectInit(&CAND2);
+  CAND2.can = CAN2;
+#endif
+
+  /* Filters initialization.*/
+#if STM32_HAS_CAN2
+  can_lld_set_filters(STM32_CAN_MAX_FILTERS / 2, 0, NULL);
+#else
+  can_lld_set_filters(STM32_CAN_MAX_FILTERS, 0, NULL);
+#endif
+}
+
+/**
+ * @brief   Configures and activates the CAN peripheral.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_start(CANDriver *canp) {
+
+  /* Clock activation.*/
+#if STM32_CAN_USE_CAN1
+  if (&CAND1 == canp) {
+    nvicEnableVector(STM32_CAN1_TX_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
+    nvicEnableVector(STM32_CAN1_RX0_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
+    nvicEnableVector(STM32_CAN1_RX1_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
+    nvicEnableVector(STM32_CAN1_SCE_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
+    rccEnableCAN1(FALSE);
+  }
+#endif
+#if STM32_CAN_USE_CAN2
+  if (&CAND2 == canp) {
+
+    osalDbgAssert(CAND1.state != CAN_STOP, "CAN1 must be started");
+
+    nvicEnableVector(STM32_CAN2_TX_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
+    nvicEnableVector(STM32_CAN2_RX0_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
+    nvicEnableVector(STM32_CAN2_RX1_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
+    nvicEnableVector(STM32_CAN2_SCE_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
+    rccEnableCAN2(FALSE);
+  }
+#endif
+
+  /* Entering initialization mode. */
+  canp->state = CAN_STARTING;
+  canp->can->MCR = CAN_MCR_INRQ;
+  while ((canp->can->MSR & CAN_MSR_INAK) == 0)
+    osalThreadSleepS(1);
+  /* BTR initialization.*/
+  canp->can->BTR = canp->config->btr;
+  /* MCR initialization.*/
+  canp->can->MCR = canp->config->mcr;
+
+  /* Interrupt sources initialization.*/
+  canp->can->IER = CAN_IER_TMEIE  | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 |
+                   CAN_IER_WKUIE  | CAN_IER_ERRIE  | CAN_IER_LECIE  |
+                   CAN_IER_BOFIE  | CAN_IER_EPVIE  | CAN_IER_EWGIE  |
+                   CAN_IER_FOVIE0 | CAN_IER_FOVIE1;
+}
+
+/**
+ * @brief   Deactivates the CAN peripheral.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_stop(CANDriver *canp) {
+
+  /* If in ready state then disables the CAN peripheral.*/
+  if (canp->state == CAN_READY) {
+#if STM32_CAN_USE_CAN1
+    if (&CAND1 == canp) {
+
+#if STM32_CAN_USE_CAN2
+      osalDbgAssert(CAND2.state == CAN_STOP, "CAN2 must be stopped");
+#endif
+
+      CAN1->MCR = 0x00010002;                   /* Register reset value.    */
+      CAN1->IER = 0x00000000;                   /* All sources disabled.    */
+      nvicDisableVector(STM32_CAN1_TX_NUMBER);
+      nvicDisableVector(STM32_CAN1_RX0_NUMBER);
+      nvicDisableVector(STM32_CAN1_RX1_NUMBER);
+      nvicDisableVector(STM32_CAN1_SCE_NUMBER);
+      rccDisableCAN1(FALSE);
+    }
+#endif
+#if STM32_CAN_USE_CAN2
+    if (&CAND2 == canp) {
+      CAN2->MCR = 0x00010002;                   /* Register reset value.    */
+      CAN2->IER = 0x00000000;                   /* All sources disabled.    */
+      nvicDisableVector(STM32_CAN2_TX_NUMBER);
+      nvicDisableVector(STM32_CAN2_RX0_NUMBER);
+      nvicDisableVector(STM32_CAN2_RX1_NUMBER);
+      nvicDisableVector(STM32_CAN2_SCE_NUMBER);
+      rccDisableCAN2(FALSE);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Determines whether a frame can be transmitted.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ *
+ * @return              The queue space availability.
+ * @retval FALSE        no space in the transmit queue.
+ * @retval TRUE         transmit slot available.
+ *
+ * @notapi
+ */
+bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
+
+  switch (mailbox) {
+  case CAN_ANY_MAILBOX:
+    return (canp->can->TSR & CAN_TSR_TME) != 0;
+  case 1:
+    return (canp->can->TSR & CAN_TSR_TME0) != 0;
+  case 2:
+    return (canp->can->TSR & CAN_TSR_TME1) != 0;
+  case 3:
+    return (canp->can->TSR & CAN_TSR_TME2) != 0;
+  default:
+    return FALSE;
+  }
+}
+
+/**
+ * @brief   Inserts a frame into the transmit queue.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] ctfp      pointer to the CAN frame to be transmitted
+ * @param[in] mailbox   mailbox number,  @p CAN_ANY_MAILBOX for any mailbox
+ *
+ * @notapi
+ */
+void can_lld_transmit(CANDriver *canp,
+                      canmbx_t mailbox,
+                      const CANTxFrame *ctfp) {
+  uint32_t tir;
+  CAN_TxMailBox_TypeDef *tmbp;
+
+  /* Pointer to a free transmission mailbox.*/
+  switch (mailbox) {
+  case CAN_ANY_MAILBOX:
+    tmbp = &canp->can->sTxMailBox[(canp->can->TSR & CAN_TSR_CODE) >> 24];
+    break;
+  case 1:
+    tmbp = &canp->can->sTxMailBox[0];
+    break;
+  case 2:
+    tmbp = &canp->can->sTxMailBox[1];
+    break;
+  case 3:
+    tmbp = &canp->can->sTxMailBox[2];
+    break;
+  default:
+    return;
+  }
+
+  /* Preparing the message.*/
+  if (ctfp->IDE)
+    tir = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) |
+          CAN_TI0R_IDE;
+  else
+    tir = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1);
+  tmbp->TDTR = ctfp->DLC;
+  tmbp->TDLR = ctfp->data32[0];
+  tmbp->TDHR = ctfp->data32[1];
+  tmbp->TIR  = tir | CAN_TI0R_TXRQ;
+}
+
+/**
+ * @brief   Determines whether a frame has been received.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ *
+ * @return              The queue space availability.
+ * @retval FALSE        no space in the transmit queue.
+ * @retval TRUE         transmit slot available.
+ *
+ * @notapi
+ */
+bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
+
+  switch (mailbox) {
+  case CAN_ANY_MAILBOX:
+    return ((canp->can->RF0R & CAN_RF0R_FMP0) != 0 ||
+            (canp->can->RF1R & CAN_RF1R_FMP1) != 0);
+  case 1:
+    return (canp->can->RF0R & CAN_RF0R_FMP0) != 0;
+  case 2:
+    return (canp->can->RF1R & CAN_RF1R_FMP1) != 0;
+  default:
+    return FALSE;
+  }
+}
+
+/**
+ * @brief   Receives a frame from the input queue.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ * @param[out] crfp     pointer to the buffer where the CAN frame is copied
+ *
+ * @notapi
+ */
+void can_lld_receive(CANDriver *canp,
+                     canmbx_t mailbox,
+                     CANRxFrame *crfp) {
+  uint32_t rir, rdtr;
+
+  if (mailbox == CAN_ANY_MAILBOX) {
+    if ((canp->can->RF0R & CAN_RF0R_FMP0) != 0)
+      mailbox = 1;
+    else if ((canp->can->RF1R & CAN_RF1R_FMP1) != 0)
+      mailbox = 2;
+    else {
+      /* Should not happen, do nothing.*/
+      return;
+    }
+  }
+  switch (mailbox) {
+  case 1:
+    /* Fetches the message.*/
+    rir  = canp->can->sFIFOMailBox[0].RIR;
+    rdtr = canp->can->sFIFOMailBox[0].RDTR;
+    crfp->data32[0] = canp->can->sFIFOMailBox[0].RDLR;
+    crfp->data32[1] = canp->can->sFIFOMailBox[0].RDHR;
+
+    /* Releases the mailbox.*/
+    canp->can->RF0R = CAN_RF0R_RFOM0;
+
+    /* If the queue is empty re-enables the interrupt in order to generate
+       events again.*/
+    if ((canp->can->RF0R & CAN_RF0R_FMP0) == 0)
+      canp->can->IER |= CAN_IER_FMPIE0;
+    break;
+  case 2:
+    /* Fetches the message.*/
+    rir  = canp->can->sFIFOMailBox[1].RIR;
+    rdtr = canp->can->sFIFOMailBox[1].RDTR;
+    crfp->data32[0] = canp->can->sFIFOMailBox[1].RDLR;
+    crfp->data32[1] = canp->can->sFIFOMailBox[1].RDHR;
+
+    /* Releases the mailbox.*/
+    canp->can->RF1R = CAN_RF1R_RFOM1;
+
+    /* If the queue is empty re-enables the interrupt in order to generate
+       events again.*/
+    if ((canp->can->RF1R & CAN_RF1R_FMP1) == 0)
+      canp->can->IER |= CAN_IER_FMPIE1;
+    break;
+  default:
+    /* Should not happen, do nothing.*/
+    return;
+  }
+
+  /* Decodes the various fields in the RX frame.*/
+  crfp->RTR = (rir & CAN_RI0R_RTR) >> 1;
+  crfp->IDE = (rir & CAN_RI0R_IDE) >> 2;
+  if (crfp->IDE)
+    crfp->EID = rir >> 3;
+  else
+    crfp->SID = rir >> 21;
+  crfp->DLC = rdtr & CAN_RDT0R_DLC;
+  crfp->FMI = (uint8_t)(rdtr >> 8);
+  crfp->TIME = (uint16_t)(rdtr >> 16);
+}
+
+#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
+/**
+ * @brief   Enters the sleep mode.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_sleep(CANDriver *canp) {
+
+  canp->can->MCR |= CAN_MCR_SLEEP;
+}
+
+/**
+ * @brief   Enforces leaving the sleep mode.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_wakeup(CANDriver *canp) {
+
+  canp->can->MCR &= ~CAN_MCR_SLEEP;
+}
+#endif /* CAN_USE_SLEEP_MODE */
+
+/**
+ * @brief   Programs the filters.
+ * @note    This is an STM32-specific API.
+ *
+ * @param[in] can2sb    number of the first filter assigned to CAN2
+ * @param[in] num       number of entries in the filters array, if zero then
+ *                      a default filter is programmed
+ * @param[in] cfp       pointer to the filters array, can be @p NULL if
+ *                      (num == 0)
+ *
+ * @api
+ */
+void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp) {
+
+  osalDbgCheck((can2sb > 1) && (can2sb < STM32_CAN_MAX_FILTERS) &&
+               (num < STM32_CAN_MAX_FILTERS));
+
+#if STM32_CAN_USE_CAN1
+  osalDbgAssert(CAND1.state == CAN_STOP, "invalid state");
+#endif
+#if STM32_CAN_USE_CAN2
+  osalDbgAssert(CAND2.state == CAN_STOP, "invalid state");
+#endif
+
+  can_lld_set_filters(can2sb, num, cfp);
+}
+
+#endif /* HAL_USE_CAN */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/can_lld.h b/os/hal/ports/STM32/LLD/can_lld.h
new file mode 100644
index 000000000..d15119a40
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/can_lld.h
@@ -0,0 +1,365 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/can_lld.h
+ * @brief   STM32 CAN subsystem low level driver header.
+ *
+ * @addtogroup CAN
+ * @{
+ */
+
+#ifndef _CAN_LLD_H_
+#define _CAN_LLD_H_
+
+#if HAL_USE_CAN || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*
+ * The following macros from the ST header file are replaced with better
+ * equivalents.
+ */
+#undef CAN_BTR_BRP
+#undef CAN_BTR_TS1
+#undef CAN_BTR_TS2
+#undef CAN_BTR_SJW
+
+/**
+ * @brief   This switch defines whether the driver implementation supports
+ *          a low power switch mode with automatic an wakeup feature.
+ */
+#define CAN_SUPPORTS_SLEEP          TRUE
+
+/**
+ * @brief   This implementation supports three transmit mailboxes.
+ */
+#define CAN_TX_MAILBOXES            3
+
+/**
+ * @brief   This implementation supports two receive mailboxes.
+ */
+#define CAN_RX_MAILBOXES            2
+
+/**
+ * @name    CAN registers helper macros
+ * @{
+ */
+#define CAN_BTR_BRP(n)              (n)         /**< @brief BRP field macro.*/
+#define CAN_BTR_TS1(n)              ((n) << 16) /**< @brief TS1 field macro.*/
+#define CAN_BTR_TS2(n)              ((n) << 20) /**< @brief TS2 field macro.*/
+#define CAN_BTR_SJW(n)              ((n) << 24) /**< @brief SJW field macro.*/
+
+#define CAN_IDE_STD                 0           /**< @brief Standard id.    */
+#define CAN_IDE_EXT                 1           /**< @brief Extended id.    */
+
+#define CAN_RTR_DATA                0           /**< @brief Data frame.     */
+#define CAN_RTR_REMOTE              1           /**< @brief Remote frame.   */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   CAN1 driver enable switch.
+ * @details If set to @p TRUE the support for CAN1 is included.
+ */
+#if !defined(STM32_CAN_USE_CAN1) || defined(__DOXYGEN__)
+#define STM32_CAN_USE_CAN1                  FALSE
+#endif
+
+/**
+ * @brief   CAN2 driver enable switch.
+ * @details If set to @p TRUE the support for CAN2 is included.
+ */
+#if !defined(STM32_CAN_USE_CAN2) || defined(__DOXYGEN__)
+#define STM32_CAN_USE_CAN2                  FALSE
+#endif
+
+/**
+ * @brief   CAN1 interrupt priority level setting.
+ */
+#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_CAN_CAN1_IRQ_PRIORITY         11
+#endif
+/** @} */
+
+/**
+ * @brief   CAN2 interrupt priority level setting.
+ */
+#if !defined(STM32_CAN_CAN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_CAN_CAN2_IRQ_PRIORITY         11
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_CAN_USE_CAN1 && !STM32_HAS_CAN1
+#error "CAN1 not present in the selected device"
+#endif
+
+#if STM32_CAN_USE_CAN2 && !STM32_HAS_CAN2
+#error "CAN2 not present in the selected device"
+#endif
+
+#if !STM32_CAN_USE_CAN1 && !STM32_CAN_USE_CAN2
+#error "CAN driver activated but no CAN peripheral assigned"
+#endif
+
+#if !STM32_CAN_USE_CAN1 && STM32_CAN_USE_CAN2
+#error "CAN2 requires CAN1, it cannot operate independently"
+#endif
+
+#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
+#error "CAN sleep mode not supported in this architecture"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a transmission mailbox index.
+ */
+typedef uint32_t canmbx_t;
+
+/**
+ * @brief   CAN transmission frame.
+ * @note    Accessing the frame data as word16 or word32 is not portable because
+ *          machine data endianness, it can be still useful for a quick filling.
+ */
+typedef struct {
+  struct {
+    uint8_t                 DLC:4;          /**< @brief Data length.        */
+    uint8_t                 RTR:1;          /**< @brief Frame type.         */
+    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
+  };
+  union {
+    struct {
+      uint32_t              SID:11;         /**< @brief Standard identifier.*/
+    };
+    struct {
+      uint32_t              EID:29;         /**< @brief Extended identifier.*/
+    };
+  };
+  union {
+    uint8_t                 data8[8];       /**< @brief Frame data.         */
+    uint16_t                data16[4];      /**< @brief Frame data.         */
+    uint32_t                data32[2];      /**< @brief Frame data.         */
+  };
+} CANTxFrame;
+
+/**
+ * @brief   CAN received frame.
+ * @note    Accessing the frame data as word16 or word32 is not portable because
+ *          machine data endianness, it can be still useful for a quick filling.
+ */
+typedef struct {
+  struct {
+    uint8_t                 FMI;            /**< @brief Filter id.          */
+    uint16_t                TIME;           /**< @brief Time stamp.         */
+  };
+  struct {
+    uint8_t                 DLC:4;          /**< @brief Data length.        */
+    uint8_t                 RTR:1;          /**< @brief Frame type.         */
+    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
+  };
+  union {
+    struct {
+      uint32_t              SID:11;         /**< @brief Standard identifier.*/
+    };
+    struct {
+      uint32_t              EID:29;         /**< @brief Extended identifier.*/
+    };
+  };
+  union {
+    uint8_t                 data8[8];       /**< @brief Frame data.         */
+    uint16_t                data16[4];      /**< @brief Frame data.         */
+    uint32_t                data32[2];      /**< @brief Frame data.         */
+  };
+} CANRxFrame;
+
+/**
+ * @brief   CAN filter.
+ * @note    Refer to the STM32 reference manual for info about filters.
+ */
+typedef struct {
+  /**
+   * @brief   Number of the filter to be programmed.
+   */
+  uint32_t                  filter;
+  /**
+   * @brief   Filter mode.
+   * @note    This bit represent the CAN_FM1R register bit associated to this
+   *          filter (0=mask mode, 1=list mode).
+   */
+  uint32_t                  mode:1;
+  /**
+   * @brief   Filter scale.
+   * @note    This bit represent the CAN_FS1R register bit associated to this
+   *          filter (0=16 bits mode, 1=32 bits mode).
+   */
+  uint32_t                  scale:1;
+  /**
+   * @brief   Filter mode.
+   * @note    This bit represent the CAN_FFA1R register bit associated to this
+   *          filter, must be set to zero in this version of the driver.
+   */
+  uint32_t                  assignment:1;
+  /**
+   * @brief   Filter register 1 (identifier).
+   */
+  uint32_t                  register1;
+  /**
+   * @brief   Filter register 2 (mask/identifier depending on mode=0/1).
+   */
+  uint32_t                  register2;
+} CANFilter;
+
+/**
+ * @brief   Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief   CAN MCR register initialization data.
+   * @note    Some bits in this register are enforced by the driver regardless
+   *          their status in this field.
+   */
+  uint32_t                  mcr;
+  /**
+   * @brief   CAN BTR register initialization data.
+   * @note    Some bits in this register are enforced by the driver regardless
+   *          their status in this field.
+   */
+  uint32_t                  btr;
+} CANConfig;
+
+/**
+ * @brief   Structure representing an CAN driver.
+ */
+typedef struct {
+  /**
+   * @brief   Driver state.
+   */
+  canstate_t                state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const CANConfig           *config;
+  /**
+   * @brief   Transmission threads queue.
+   */
+  threads_queue_t           txqueue;
+  /**
+   * @brief   Receive threads queue.
+   */
+  threads_queue_t           rxqueue;
+  /**
+   * @brief   One or more frames become available.
+   * @note    After broadcasting this event it will not be broadcasted again
+   *          until the received frames queue has been completely emptied. It
+   *          is <b>not</b> broadcasted for each received frame. It is
+   *          responsibility of the application to empty the queue by
+   *          repeatedly invoking @p chReceive() when listening to this event.
+   *          This behavior minimizes the interrupt served by the system
+   *          because CAN traffic.
+   * @note    The flags associated to the listeners will indicate which
+   *          receive mailboxes become non-empty.
+   */
+  event_source_t            rxfull_event;
+  /**
+   * @brief   One or more transmission mailbox become available.
+   * @note    The flags associated to the listeners will indicate which
+   *          transmit mailboxes become empty.
+   *
+   */
+  event_source_t            txempty_event;
+  /**
+   * @brief   A CAN bus error happened.
+   * @note    The flags associated to the listeners will indicate the
+   *          error(s) that have occurred.
+   */
+  event_source_t            error_event;
+#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
+  /**
+   * @brief   Entering sleep state event.
+   */
+  event_source_t            sleep_event;
+  /**
+   * @brief   Exiting sleep state event.
+   */
+  event_source_t            wakeup_event;
+#endif /* CAN_USE_SLEEP_MODE */
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Pointer to the CAN registers.
+   */
+  CAN_TypeDef               *can;
+} CANDriver;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_CAN_USE_CAN1 && !defined(__DOXYGEN__)
+extern CANDriver CAND1;
+#endif
+
+#if STM32_CAN_USE_CAN2 && !defined(__DOXYGEN__)
+extern CANDriver CAND2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void can_lld_init(void);
+  void can_lld_start(CANDriver *canp);
+  void can_lld_stop(CANDriver *canp);
+  bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox);
+  void can_lld_transmit(CANDriver *canp,
+                        canmbx_t mailbox,
+                        const CANTxFrame *crfp);
+  bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox);
+  void can_lld_receive(CANDriver *canp,
+                       canmbx_t mailbox,
+                       CANRxFrame *ctfp);
+#if CAN_USE_SLEEP_MODE
+  void can_lld_sleep(CANDriver *canp);
+  void can_lld_wakeup(CANDriver *canp);
+#endif /* CAN_USE_SLEEP_MODE */
+  void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_CAN */
+
+#endif /* _CAN_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/ext_lld.c b/os/hal/ports/STM32/LLD/ext_lld.c
new file mode 100644
index 000000000..8457db1cb
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/ext_lld.c
@@ -0,0 +1,219 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/ext_lld.c
+ * @brief   STM32 EXT subsystem low level driver source.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   EXTD1 driver identifier.
+ */
+EXTDriver EXTD1;
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level EXT driver initialization.
+ *
+ * @notapi
+ */
+void ext_lld_init(void) {
+
+  /* Driver initialization.*/
+  extObjectInit(&EXTD1);
+}
+
+/**
+ * @brief   Configures and activates the EXT peripheral.
+ *
+ * @param[in] extp      pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_start(EXTDriver *extp) {
+  unsigned i;
+
+  if (extp->state == EXT_STOP)
+    ext_lld_exti_irq_enable();
+
+  /* Configuration of automatic channels.*/
+  for (i = 0; i < EXT_MAX_CHANNELS; i++)
+    if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
+      ext_lld_channel_enable(extp, i);
+    else
+      ext_lld_channel_disable(extp, i);
+}
+
+/**
+ * @brief   Deactivates the EXT peripheral.
+ *
+ * @param[in] extp      pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_stop(EXTDriver *extp) {
+
+  if (extp->state == EXT_ACTIVE)
+    ext_lld_exti_irq_disable();
+
+  EXTI->EMR = 0;
+  EXTI->IMR = 0;
+  EXTI->PR  = 0xFFFFFFFF;
+#if STM32_EXTI_NUM_CHANNELS > 32
+  EXTI->PR2 = 0xFFFFFFFF;
+#endif
+}
+
+/**
+ * @brief   Enables an EXT channel.
+ *
+ * @param[in] extp      pointer to the @p EXTDriver object
+ * @param[in] channel   channel to be enabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
+
+  /* Setting the associated GPIO for external channels.*/
+  if (channel < 16) {
+    uint32_t n = channel >> 2;
+    uint32_t mask = ~(0xF << ((channel & 3) * 4));
+    uint32_t port = ((extp->config->channels[channel].mode &
+                      EXT_MODE_GPIO_MASK) >>
+                     EXT_MODE_GPIO_OFF) << ((channel & 3) * 4);
+
+#if defined(STM32F1XX)
+    AFIO->EXTICR[n] = (AFIO->EXTICR[n] & mask) | port;
+#else /* !defined(STM32F1XX) */
+    SYSCFG->EXTICR[n] = (SYSCFG->EXTICR[n] & mask) | port;
+#endif /* !defined(STM32F1XX) */
+  }
+
+#if STM32_EXTI_NUM_CHANNELS > 32
+  if (channel < 32) {
+#endif
+    /* Programming edge registers.*/
+    if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
+      EXTI->RTSR |= (1 << channel);
+    else
+      EXTI->RTSR &= ~(1 << channel);
+    if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
+      EXTI->FTSR |= (1 << channel);
+    else
+      EXTI->FTSR &= ~(1 << channel);
+
+    /* Programming interrupt and event registers.*/
+    if (extp->config->channels[channel].cb != NULL) {
+      EXTI->IMR |= (1 << channel);
+      EXTI->EMR &= ~(1 << channel);
+    }
+    else {
+      EXTI->EMR |= (1 << channel);
+      EXTI->IMR &= ~(1 << channel);
+    }
+#if STM32_EXTI_NUM_CHANNELS > 32
+  }
+  else {
+    /* Programming edge registers.*/
+    if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE)
+      EXTI->RTSR2 |= (1 << (32 - channel));
+    else
+      EXTI->RTSR2 &= ~(1 << (32 - channel));
+    if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
+      EXTI->FTSR2 |= (1 << (32 - channel));
+    else
+      EXTI->FTSR2 &= ~(1 << (32 - channel));
+
+    /* Programming interrupt and event registers.*/
+    if (extp->config->channels[channel].cb != NULL) {
+      EXTI->IMR2 |= (1 << (32 - channel));
+      EXTI->EMR2 &= ~(1 << (32 - channel));
+    }
+    else {
+      EXTI->EMR2 |= (1 << (32 - channel));
+      EXTI->IMR2 &= ~(1 << (32 - channel));
+    }
+  }
+#endif
+}
+
+/**
+ * @brief   Disables an EXT channel.
+ *
+ * @param[in] extp      pointer to the @p EXTDriver object
+ * @param[in] channel   channel to be disabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
+
+  (void)extp;
+
+#if STM32_EXTI_NUM_CHANNELS > 32
+  if (channel < 32) {
+#endif
+    EXTI->IMR   &= ~(1 << channel);
+    EXTI->EMR   &= ~(1 << channel);
+    EXTI->RTSR  &= ~(1 << channel);
+    EXTI->FTSR  &= ~(1 << channel);
+    EXTI->PR     =  (1 << channel);
+#if STM32_EXTI_NUM_CHANNELS > 32
+  }
+  else {
+    EXTI->IMR2  &= ~(1 << (32 - channel));
+    EXTI->EMR2  &= ~(1 << (32 - channel));
+    EXTI->RTSR2 &= ~(1 << (32 - channel));
+    EXTI->FTSR2 &= ~(1 << (32 - channel));
+    EXTI->PR2    =  (1 << (32 - channel));
+  }
+#endif
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/ext_lld.h b/os/hal/ports/STM32/LLD/ext_lld.h
index 7a59fa728..7a59fa728 100644
--- a/os/hal/platforms/STM32/ext_lld.h
+++ b/os/hal/ports/STM32/LLD/ext_lld.h
diff --git a/os/hal/ports/STM32/LLD/mac_lld.c b/os/hal/ports/STM32/LLD/mac_lld.c
new file mode 100644
index 000000000..9f1b5e3db
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/mac_lld.c
@@ -0,0 +1,741 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/mac_lld.c
+ * @brief   STM32 low level MAC driver code.
+ *
+ * @addtogroup MAC
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#if HAL_USE_MAC || defined(__DOXYGEN__)
+
+#include "mii.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define BUFFER_SIZE ((((STM32_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
+
+/* MII divider optimal value.*/
+#if (STM32_HCLK >= 150000000)
+#define MACMIIDR_CR ETH_MACMIIAR_CR_Div102
+#elif (STM32_HCLK >= 100000000)
+#define MACMIIDR_CR ETH_MACMIIAR_CR_Div62
+#elif (STM32_HCLK >= 60000000)
+#define MACMIIDR_CR     ETH_MACMIIAR_CR_Div42
+#elif (STM32_HCLK >= 35000000)
+#define MACMIIDR_CR     ETH_MACMIIAR_CR_Div26
+#elif (STM32_HCLK >= 20000000)
+#define MACMIIDR_CR     ETH_MACMIIAR_CR_Div16
+#else
+#error "STM32_HCLK below minimum frequency for ETH operations (20MHz)"
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Ethernet driver 1.
+ */
+MACDriver ETHD1;
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
+                                              0x37, 0x01, 0x10};
+
+static stm32_eth_rx_descriptor_t rd[STM32_MAC_RECEIVE_BUFFERS];
+static stm32_eth_tx_descriptor_t td[STM32_MAC_TRANSMIT_BUFFERS];
+
+static uint32_t rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];
+static uint32_t tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Writes a PHY register.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[in] reg       register number
+ * @param[in] value     new register value
+ */
+static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) {
+
+  ETH->MACMIIDR = value;
+  ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR |
+                  ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
+  while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
+    ;
+}
+
+/**
+ * @brief   Reads a PHY register.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[in] reg       register number
+ *
+ * @return              The PHY register content.
+ */
+static uint32_t mii_read(MACDriver *macp, uint32_t reg) {
+
+  ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | ETH_MACMIIAR_MB;
+  while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
+    ;
+  return ETH->MACMIIDR;
+}
+
+#if !defined(BOARD_PHY_ADDRESS)
+/**
+ * @brief   PHY address detection.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ */
+static void mii_find_phy(MACDriver *macp) {
+  uint32_t i;
+
+#if STM32_MAC_PHY_TIMEOUT > 0
+  halrtcnt_t start = halGetCounterValue();
+  halrtcnt_t timeout  = start + MS2RTT(STM32_MAC_PHY_TIMEOUT);
+  while (halIsCounterWithin(start, timeout)) {
+#endif
+    for (i = 0; i < 31; i++) {
+      macp->phyaddr = i << 11;
+      ETH->MACMIIDR = (i << 6) | MACMIIDR_CR;
+      if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
+          ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
+        return;
+      }
+    }
+#if STM32_MAC_PHY_TIMEOUT > 0
+  }
+#endif
+  /* Wrong or defective board.*/
+  chSysHalt();
+}
+#endif
+
+/**
+ * @brief   MAC address setup.
+ *
+ * @param[in] p         pointer to a six bytes buffer containing the MAC
+ *                      address
+ */
+static void mac_lld_set_address(const uint8_t *p) {
+
+  /* MAC address configuration, only a single address comparator is used,
+     hash table not used.*/
+  ETH->MACA0HR   = ((uint32_t)p[5] << 8) |
+                   ((uint32_t)p[4] << 0);
+  ETH->MACA0LR   = ((uint32_t)p[3] << 24) |
+                   ((uint32_t)p[2] << 16) |
+                   ((uint32_t)p[1] << 8) |
+                   ((uint32_t)p[0] << 0);
+  ETH->MACA1HR   = 0x0000FFFF;
+  ETH->MACA1LR   = 0xFFFFFFFF;
+  ETH->MACA2HR   = 0x0000FFFF;
+  ETH->MACA2LR   = 0xFFFFFFFF;
+  ETH->MACA3HR   = 0x0000FFFF;
+  ETH->MACA3LR   = 0xFFFFFFFF;
+  ETH->MACHTHR   = 0;
+  ETH->MACHTLR   = 0;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+CH_IRQ_HANDLER(ETH_IRQHandler) {
+  uint32_t dmasr;
+
+  CH_IRQ_PROLOGUE();
+
+  dmasr = ETH->DMASR;
+  ETH->DMASR = dmasr; /* Clear status bits.*/
+
+  if (dmasr & ETH_DMASR_RS) {
+    /* Data Received.*/
+    chSysLockFromIsr();
+    chSemResetI(&ETHD1.rdsem, 0);
+#if MAC_USE_EVENTS
+    chEvtBroadcastI(&ETHD1.rdevent);
+#endif
+    chSysUnlockFromIsr();
+  }
+
+  if (dmasr & ETH_DMASR_TS) {
+    /* Data Transmitted.*/
+    chSysLockFromIsr();
+    chSemResetI(&ETHD1.tdsem, 0);
+    chSysUnlockFromIsr();
+  }
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level MAC initialization.
+ *
+ * @notapi
+ */
+void mac_lld_init(void) {
+  unsigned i;
+
+  macObjectInit(&ETHD1);
+  ETHD1.link_up = FALSE;
+
+  /* Descriptor tables are initialized in chained mode, note that the first
+     word is not initialized here but in mac_lld_start().*/
+  for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) {
+    rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE;
+    rd[i].rdes2 = (uint32_t)rb[i];
+    rd[i].rdes3 = (uint32_t)&rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS];
+  }
+  for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) {
+    td[i].tdes1 = 0;
+    td[i].tdes2 = (uint32_t)tb[i];
+    td[i].tdes3 = (uint32_t)&td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS];
+  }
+
+  /* Selection of the RMII or MII mode based on info exported by board.h.*/
+#if defined(STM32F10X_CL)
+#if defined(BOARD_PHY_RMII)
+  AFIO->MAPR |= AFIO_MAPR_MII_RMII_SEL;
+#else
+  AFIO->MAPR &= ~AFIO_MAPR_MII_RMII_SEL;
+#endif
+#elif defined(STM32F2XX) || defined(STM32F4XX)
+#if defined(BOARD_PHY_RMII)
+  SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
+#else
+  SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL;
+#endif
+#else
+#error "unsupported STM32 platform for MAC driver"
+#endif
+
+  /* Reset of the MAC core.*/
+  rccResetETH();
+
+  /* MAC clocks temporary activation.*/
+  rccEnableETH(FALSE);
+
+  /* PHY address setup.*/
+#if defined(BOARD_PHY_ADDRESS)
+  ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
+#else
+  mii_find_phy(&ETHD1);
+#endif
+
+#if defined(BOARD_PHY_RESET)
+  /* PHY board-specific reset procedure.*/
+  BOARD_PHY_RESET();
+#else
+  /* PHY soft reset procedure.*/
+  mii_write(&ETHD1, MII_BMCR, BMCR_RESET);
+#if defined(BOARD_PHY_RESET_DELAY)
+  halPolledDelay(BOARD_PHY_RESET_DELAY);
+#endif
+  while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)
+    ;
+#endif
+
+#if STM32_MAC_ETH1_CHANGE_PHY_STATE
+  /* PHY in power down mode until the driver will be started.*/
+  mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN);
+#endif
+
+  /* MAC clocks stopped again.*/
+  rccDisableETH(FALSE);
+}
+
+/**
+ * @brief   Configures and activates the MAC peripheral.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ *
+ * @notapi
+ */
+void mac_lld_start(MACDriver *macp) {
+  unsigned i;
+
+  /* Resets the state of all descriptors.*/
+  for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++)
+    rd[i].rdes0 = STM32_RDES0_OWN;
+  macp->rxptr = (stm32_eth_rx_descriptor_t *)rd;
+  for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++)
+    td[i].tdes0 = STM32_TDES0_TCH;
+  macp->txptr = (stm32_eth_tx_descriptor_t *)td;
+
+  /* MAC clocks activation and commanded reset procedure.*/
+  rccEnableETH(FALSE);
+#if defined(STM32_MAC_DMABMR_SR)
+  ETH->DMABMR |= ETH_DMABMR_SR;
+  while(ETH->DMABMR & ETH_DMABMR_SR)
+    ;
+#endif
+
+  /* ISR vector enabled.*/
+  nvicEnableVector(ETH_IRQn,
+                   CORTEX_PRIORITY_MASK(STM32_MAC_ETH1_IRQ_PRIORITY));
+
+#if STM32_MAC_ETH1_CHANGE_PHY_STATE
+  /* PHY in power up mode.*/
+  mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
+#endif
+
+  /* MAC configuration.*/
+  ETH->MACFFR    = 0;
+  ETH->MACFCR    = 0;
+  ETH->MACVLANTR = 0;
+
+  /* MAC address setup.*/
+  if (macp->config->mac_address == NULL)
+    mac_lld_set_address(default_mac_address);
+  else
+    mac_lld_set_address(macp->config->mac_address);
+
+  /* Transmitter and receiver enabled.
+     Note that the complete setup of the MAC is performed when the link
+     status is detected.*/
+#if STM32_MAC_IP_CHECKSUM_OFFLOAD
+  ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE;
+#else
+  ETH->MACCR =                  ETH_MACCR_RE | ETH_MACCR_TE;
+#endif
+
+  /* DMA configuration:
+     Descriptor chains pointers.*/
+  ETH->DMARDLAR = (uint32_t)rd;
+  ETH->DMATDLAR = (uint32_t)td;
+
+  /* Enabling required interrupt sources.*/
+  ETH->DMASR    = ETH->DMASR;
+  ETH->DMAIER   = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
+
+  /* DMA general settings.*/
+  ETH->DMABMR   = ETH_DMABMR_AAB | ETH_DMABMR_RDP_1Beat | ETH_DMABMR_PBL_1Beat;
+
+  /* Transmit FIFO flush.*/
+  ETH->DMAOMR   = ETH_DMAOMR_FTF;
+  while (ETH->DMAOMR & ETH_DMAOMR_FTF)
+    ;
+
+  /* DMA final configuration and start.*/
+  ETH->DMAOMR   = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_TSF |
+                  ETH_DMAOMR_ST | ETH_DMAOMR_SR;
+}
+
+/**
+ * @brief   Deactivates the MAC peripheral.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ *
+ * @notapi
+ */
+void mac_lld_stop(MACDriver *macp) {
+
+  if (macp->state != MAC_STOP) {
+#if STM32_MAC_ETH1_CHANGE_PHY_STATE
+    /* PHY in power down mode until the driver will be restarted.*/
+    mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
+#endif
+
+    /* MAC and DMA stopped.*/
+    ETH->MACCR    = 0;
+    ETH->DMAOMR   = 0;
+    ETH->DMAIER   = 0;
+    ETH->DMASR    = ETH->DMASR;
+
+    /* MAC clocks stopped.*/
+    rccDisableETH(FALSE);
+
+    /* ISR vector disabled.*/
+    nvicDisableVector(ETH_IRQn);
+  }
+}
+
+/**
+ * @brief   Returns a transmission descriptor.
+ * @details One of the available transmission descriptors is locked and
+ *          returned.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[out] tdp      pointer to a @p MACTransmitDescriptor structure
+ * @return              The operation status.
+ * @retval RDY_OK       the descriptor has been obtained.
+ * @retval RDY_TIMEOUT  descriptor not available.
+ *
+ * @notapi
+ */
+msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
+                                      MACTransmitDescriptor *tdp) {
+  stm32_eth_tx_descriptor_t *tdes;
+
+  if (!macp->link_up)
+    return RDY_TIMEOUT;
+
+  chSysLock();
+
+  /* Get Current TX descriptor.*/
+  tdes = macp->txptr;
+
+  /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
+     another thread.*/
+  if (tdes->tdes0 & (STM32_TDES0_OWN | STM32_TDES0_LOCKED)) {
+    chSysUnlock();
+    return RDY_TIMEOUT;
+  }
+
+  /* Marks the current descriptor as locked using a reserved bit.*/
+  tdes->tdes0 |= STM32_TDES0_LOCKED;
+
+  /* Next TX descriptor to use.*/
+  macp->txptr = (stm32_eth_tx_descriptor_t *)tdes->tdes3;
+
+  chSysUnlock();
+
+  /* Set the buffer size and configuration.*/
+  tdp->offset   = 0;
+  tdp->size     = STM32_MAC_BUFFERS_SIZE;
+  tdp->physdesc = tdes;
+
+  return RDY_OK;
+}
+
+/**
+ * @brief   Releases a transmit descriptor and starts the transmission of the
+ *          enqueued data as a single frame.
+ *
+ * @param[in] tdp       the pointer to the @p MACTransmitDescriptor structure
+ *
+ * @notapi
+ */
+void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
+
+  chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
+              "mac_lld_release_transmit_descriptor(), #1",
+              "attempt to release descriptor already owned by DMA");
+
+  chSysLock();
+
+  /* Unlocks the descriptor and returns it to the DMA engine.*/
+  tdp->physdesc->tdes1 = tdp->offset;
+  tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_MAC_IP_CHECKSUM_OFFLOAD) |
+                         STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS |
+                         STM32_TDES0_TCH | STM32_TDES0_OWN;
+
+  /* If the DMA engine is stalled then a restart request is issued.*/
+  if ((ETH->DMASR & ETH_DMASR_TPS) == ETH_DMASR_TPS_Suspended) {
+    ETH->DMASR   = ETH_DMASR_TBUS;
+    ETH->DMATPDR = ETH_DMASR_TBUS; /* Any value is OK.*/
+  }
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Returns a receive descriptor.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[out] rdp      pointer to a @p MACReceiveDescriptor structure
+ * @return              The operation status.
+ * @retval RDY_OK       the descriptor has been obtained.
+ * @retval RDY_TIMEOUT  descriptor not available.
+ *
+ * @notapi
+ */
+msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
+                                     MACReceiveDescriptor *rdp) {
+  stm32_eth_rx_descriptor_t *rdes;
+
+  chSysLock();
+
+  /* Get Current RX descriptor.*/
+  rdes = macp->rxptr;
+
+  /* Iterates through received frames until a valid one is found, invalid
+     frames are discarded.*/
+  while (!(rdes->rdes0 & STM32_RDES0_OWN)) {
+    if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES))
+#if STM32_MAC_IP_CHECKSUM_OFFLOAD
+        && (rdes->rdes0 & STM32_RDES0_FT)
+        && !(rdes->rdes0 & (STM32_RDES0_IPHCE | STM32_RDES0_PCE))
+#endif
+        && (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) {
+      /* Found a valid one.*/
+      rdp->offset   = 0;
+      rdp->size     = ((rdes->rdes0 & STM32_RDES0_FL_MASK) >> 16) - 4;
+      rdp->physdesc = rdes;
+      macp->rxptr   = (stm32_eth_rx_descriptor_t *)rdes->rdes3;
+
+      chSysUnlock();
+      return RDY_OK;
+    }
+    /* Invalid frame found, purging.*/
+    rdes->rdes0 = STM32_RDES0_OWN;
+    rdes = (stm32_eth_rx_descriptor_t *)rdes->rdes3;
+  }
+
+  /* Next descriptor to check.*/
+  macp->rxptr = rdes;
+
+  chSysUnlock();
+  return RDY_TIMEOUT;
+}
+
+/**
+ * @brief   Releases a receive descriptor.
+ * @details The descriptor and its buffer are made available for more incoming
+ *          frames.
+ *
+ * @param[in] rdp       the pointer to the @p MACReceiveDescriptor structure
+ *
+ * @notapi
+ */
+void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
+
+  chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
+              "mac_lld_release_receive_descriptor(), #1",
+              "attempt to release descriptor already owned by DMA");
+
+  chSysLock();
+
+  /* Give buffer back to the Ethernet DMA.*/
+  rdp->physdesc->rdes0 = STM32_RDES0_OWN;
+
+  /* If the DMA engine is stalled then a restart request is issued.*/
+  if ((ETH->DMASR & ETH_DMASR_RPS) == ETH_DMASR_RPS_Suspended) {
+    ETH->DMASR   = ETH_DMASR_RBUS;
+    ETH->DMARPDR = ETH_DMASR_RBUS; /* Any value is OK.*/
+  }
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Updates and returns the link status.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @return              The link status.
+ * @retval TRUE         if the link is active.
+ * @retval FALSE        if the link is down.
+ *
+ * @notapi
+ */
+bool_t mac_lld_poll_link_status(MACDriver *macp) {
+  uint32_t maccr, bmsr, bmcr;
+
+  maccr = ETH->MACCR;
+
+  /* PHY CR and SR registers read.*/
+  (void)mii_read(macp, MII_BMSR);
+  bmsr = mii_read(macp, MII_BMSR);
+  bmcr = mii_read(macp, MII_BMCR);
+
+  /* Check on auto-negotiation mode.*/
+  if (bmcr & BMCR_ANENABLE) {
+    uint32_t lpa;
+
+    /* Auto-negotiation must be finished without faults and link established.*/
+    if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
+        (BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
+      return macp->link_up = FALSE;
+
+    /* Auto-negotiation enabled, checks the LPA register.*/
+    lpa = mii_read(macp, MII_LPA);
+
+    /* Check on link speed.*/
+    if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
+      maccr |= ETH_MACCR_FES;
+    else
+      maccr &= ~ETH_MACCR_FES;
+
+    /* Check on link mode.*/
+    if (lpa & (LPA_10FULL | LPA_100FULL))
+      maccr |= ETH_MACCR_DM;
+    else
+      maccr &= ~ETH_MACCR_DM;
+  }
+  else {
+    /* Link must be established.*/
+    if (!(bmsr & BMSR_LSTATUS))
+      return macp->link_up = FALSE;
+
+    /* Check on link speed.*/
+    if (bmcr & BMCR_SPEED100)
+      maccr |= ETH_MACCR_FES;
+    else
+      maccr &= ~ETH_MACCR_FES;
+
+    /* Check on link mode.*/
+    if (bmcr & BMCR_FULLDPLX)
+      maccr |= ETH_MACCR_DM;
+    else
+      maccr &= ~ETH_MACCR_DM;
+  }
+
+  /* Changes the mode in the MAC.*/
+  ETH->MACCR = maccr;
+
+  /* Returns the link status.*/
+  return macp->link_up = TRUE;
+}
+
+/**
+ * @brief   Writes to a transmit descriptor's stream.
+ *
+ * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
+ * @param[in] buf       pointer to the buffer containing the data to be
+ *                      written
+ * @param[in] size      number of bytes to be written
+ * @return              The number of bytes written into the descriptor's
+ *                      stream, this value can be less than the amount
+ *                      specified in the parameter @p size if the maximum
+ *                      frame size is reached.
+ *
+ * @notapi
+ */
+size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
+                                         uint8_t *buf,
+                                         size_t size) {
+
+  chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN),
+              "mac_lld_write_transmit_descriptor(), #1",
+              "attempt to write descriptor already owned by DMA");
+
+  if (size > tdp->size - tdp->offset)
+    size = tdp->size - tdp->offset;
+
+  if (size > 0) {
+    memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size);
+    tdp->offset += size;
+  }
+  return size;
+}
+
+/**
+ * @brief   Reads from a receive descriptor's stream.
+ *
+ * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
+ * @param[in] buf       pointer to the buffer that will receive the read data
+ * @param[in] size      number of bytes to be read
+ * @return              The number of bytes read from the descriptor's
+ *                      stream, this value can be less than the amount
+ *                      specified in the parameter @p size if there are
+ *                      no more bytes to read.
+ *
+ * @notapi
+ */
+size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
+                                       uint8_t *buf,
+                                       size_t size) {
+
+  chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN),
+              "mac_lld_read_receive_descriptor(), #1",
+              "attempt to read descriptor already owned by DMA");
+
+  if (size > rdp->size - rdp->offset)
+    size = rdp->size - rdp->offset;
+
+  if (size > 0) {
+    memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size);
+    rdp->offset += size;
+  }
+  return size;
+}
+
+#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
+/**
+ * @brief   Returns a pointer to the next transmit buffer in the descriptor
+ *          chain.
+ * @note    The API guarantees that enough buffers can be requested to fill
+ *          a whole frame.
+ *
+ * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
+ * @param[in] size      size of the requested buffer. Specify the frame size
+ *                      on the first call then scale the value down subtracting
+ *                      the amount of data already copied into the previous
+ *                      buffers.
+ * @param[out] sizep    pointer to variable receiving the buffer size, it is
+ *                      zero when the last buffer has already been returned.
+ *                      Note that a returned size lower than the amount
+ *                      requested means that more buffers must be requested
+ *                      in order to fill the frame data entirely.
+ * @return              Pointer to the returned buffer.
+ * @retval NULL         if the buffer chain has been entirely scanned.
+ *
+ * @notapi
+ */
+uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
+                                          size_t size,
+                                          size_t *sizep) {
+
+  if (tdp->offset == 0) {
+    *sizep      = tdp->size;
+    tdp->offset = size;
+    return (uint8_t *)tdp->physdesc->tdes2;
+  }
+  *sizep = 0;
+  return NULL;
+}
+
+/**
+ * @brief   Returns a pointer to the next receive buffer in the descriptor
+ *          chain.
+ * @note    The API guarantees that the descriptor chain contains a whole
+ *          frame.
+ *
+ * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
+ * @param[out] sizep    pointer to variable receiving the buffer size, it is
+ *                      zero when the last buffer has already been returned.
+ * @return              Pointer to the returned buffer.
+ * @retval NULL         if the buffer chain has been entirely scanned.
+ *
+ * @notapi
+ */
+const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
+                                               size_t *sizep) {
+
+  if (rdp->size > 0) {
+    *sizep      = rdp->size;
+    rdp->offset = rdp->size;
+    rdp->size   = 0;
+    return (uint8_t *)rdp->physdesc->rdes2;
+  }
+  *sizep = 0;
+  return NULL;
+}
+#endif /* MAC_USE_ZERO_COPY */
+
+#endif /* HAL_USE_MAC */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/ports/STM32/LLD/mac_lld.h
index bde7e0345..bde7e0345 100644
--- a/os/hal/platforms/STM32/mac_lld.h
+++ b/os/hal/ports/STM32/LLD/mac_lld.h
diff --git a/os/hal/ports/STM32/LLD/sdc_lld.c b/os/hal/ports/STM32/LLD/sdc_lld.c
new file mode 100644
index 000000000..1aca84fb0
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/sdc_lld.c
@@ -0,0 +1,780 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/sdc_lld.c
+ * @brief   STM32 SDC subsystem low level driver source.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+/*
+ TODO: Try preerase blocks before writing (ACMD23).
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define DMA_CHANNEL                                                         \
+  STM32_DMA_GETCHANNEL(STM32_SDC_SDIO_DMA_STREAM,                           \
+                       STM32_SDC_SDIO_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief SDCD1 driver identifier.*/
+SDCDriver SDCD1;
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
+/**
+ * @brief   Buffer for temporary storage during unaligned transfers.
+ */
+static union {
+  uint32_t  alignment;
+  uint8_t   buf[MMCSD_BLOCK_SIZE];
+} u;
+#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Prepares card to handle read transaction.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to read
+ * @param[in] n         number of blocks to read
+ * @param[in] resp      pointer to the response buffer
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
+                                 uint32_t n, uint32_t *resp) {
+
+  /* Driver handles data in 512 bytes blocks (just like HC cards). But if we
+     have not HC card than we must convert address from blocks to bytes.*/
+  if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY))
+    startblk *= MMCSD_BLOCK_SIZE;
+
+  if (n > 1) {
+    /* Send read multiple blocks command to card.*/
+    if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_MULTIPLE_BLOCK,
+                                   startblk, resp) || MMCSD_R1_ERROR(resp[0]))
+      return HAL_FAILED;
+  }
+  else{
+    /* Send read single block command.*/
+    if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_SINGLE_BLOCK,
+                                   startblk, resp) || MMCSD_R1_ERROR(resp[0]))
+      return HAL_FAILED;
+  }
+
+  return HAL_SUCCESS;
+}
+
+/**
+ * @brief   Prepares card to handle write transaction.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to read
+ * @param[in] n         number of blocks to write
+ * @param[in] resp      pointer to the response buffer
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+static bool sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
+                                  uint32_t n, uint32_t *resp) {
+
+  /* Driver handles data in 512 bytes blocks (just like HC cards). But if we
+     have not HC card than we must convert address from blocks to bytes.*/
+  if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY))
+    startblk *= MMCSD_BLOCK_SIZE;
+
+  if (n > 1) {
+    /* Write multiple blocks command.*/
+    if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK,
+                                   startblk, resp) || MMCSD_R1_ERROR(resp[0]))
+      return HAL_FAILED;
+  }
+  else{
+    /* Write single block command.*/
+    if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_BLOCK,
+                                   startblk, resp) || MMCSD_R1_ERROR(resp[0]))
+      return HAL_FAILED;
+  }
+
+  return HAL_SUCCESS;
+}
+
+/**
+ * @brief   Wait end of data transaction and performs finalizations.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] n         number of blocks in transaction
+ * @param[in] resp      pointer to the response buffer
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ */
+static bool sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
+                                         uint32_t *resp) {
+
+  /* Note the mask is checked before going to sleep because the interrupt
+     may have occurred before reaching the critical zone.*/
+  osalSysLock();
+  if (SDIO->MASK != 0)
+    osalThreadSuspendS(&sdcp->thread);
+  if ((SDIO->STA & SDIO_STA_DATAEND) == 0) {
+    osalSysUnlock();
+    return HAL_FAILED;
+  }
+
+#if (defined(STM32F4XX) || defined(STM32F2XX))
+  /* Wait until DMA channel enabled to be sure that all data transferred.*/
+  while (sdcp->dma->stream->CR & STM32_DMA_CR_EN)
+    ;
+
+  /* DMA event flags must be manually cleared.*/
+  dmaStreamClearInterrupt(sdcp->dma);
+
+  SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
+  SDIO->DCTRL = 0;
+  osalSysUnlock();
+
+  /* Wait until interrupt flags to be cleared.*/
+  /*while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF)
+    dmaStreamClearInterrupt(sdcp->dma);*/
+#else
+  /* Waits for transfer completion at DMA level, the the stream is
+     disabled and cleared.*/
+  dmaWaitCompletion(sdcp->dma);
+
+  SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
+  SDIO->DCTRL = 0;
+  osalSysUnlock();
+#endif
+
+  /* Finalize transaction.*/
+  if (n > 1)
+    return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp);
+
+  return HAL_SUCCESS;
+}
+
+/**
+ * @brief   Gets SDC errors.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] sta       value of the STA register
+ *
+ * @notapi
+ */
+static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sta) {
+  uint32_t errors = SDC_NO_ERROR;
+
+  if (sta & SDIO_STA_CCRCFAIL)
+    errors |= SDC_CMD_CRC_ERROR;
+  if (sta & SDIO_STA_DCRCFAIL)
+    errors |= SDC_DATA_CRC_ERROR;
+  if (sta & SDIO_STA_CTIMEOUT)
+    errors |= SDC_COMMAND_TIMEOUT;
+  if (sta & SDIO_STA_DTIMEOUT)
+    errors |= SDC_DATA_TIMEOUT;
+  if (sta & SDIO_STA_TXUNDERR)
+    errors |= SDC_TX_UNDERRUN;
+  if (sta & SDIO_STA_RXOVERR)
+    errors |= SDC_RX_OVERRUN;
+  if (sta & SDIO_STA_STBITERR)
+    errors |= SDC_STARTBIT_ERROR;
+
+  sdcp->errors |= errors;
+}
+
+/**
+ * @brief   Performs clean transaction stopping in case of errors.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] n         number of blocks in transaction
+ * @param[in] resp      pointer to the response buffer
+ *
+ * @notapi
+ */
+static void sdc_lld_error_cleanup(SDCDriver *sdcp,
+                                  uint32_t n,
+                                  uint32_t *resp) {
+  uint32_t sta = SDIO->STA;
+
+  dmaStreamClearInterrupt(sdcp->dma);
+  dmaStreamDisable(sdcp->dma);
+  SDIO->ICR   = STM32_SDIO_ICR_ALL_FLAGS;
+  SDIO->MASK  = 0;
+  SDIO->DCTRL = 0;
+  sdc_lld_collect_errors(sdcp, sta);
+  if (n > 1)
+    sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if !defined(STM32_SDIO_HANDLER)
+#error "STM32_SDIO_HANDLER not defined"
+#endif
+/**
+ * @brief   SDIO IRQ handler.
+ * @details It just wakes transaction thread. All error  handling performs in
+ *          that thread.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_SDIO_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  osalSysLockFromISR();
+
+  /* Disables the source but the status flags are not reset because the
+     read/write functions needs to check them.*/
+  SDIO->MASK = 0;
+
+  osalThreadResumeI(&SDCD1.thread, MSG_OK);
+
+  osalSysUnlockFromISR();
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level SDC driver initialization.
+ *
+ * @notapi
+ */
+void sdc_lld_init(void) {
+
+  sdcObjectInit(&SDCD1);
+  SDCD1.thread = NULL;
+  SDCD1.dma    = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM);
+#if CH_DBG_ENABLE_ASSERTS
+  SDCD1.sdio   = SDIO;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the SDC peripheral.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start(SDCDriver *sdcp) {
+
+  sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) |
+                  STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) |
+                  STM32_DMA_CR_PSIZE_WORD |
+                  STM32_DMA_CR_MSIZE_WORD |
+                  STM32_DMA_CR_MINC;
+
+#if (defined(STM32F4XX) || defined(STM32F2XX))
+  sdcp->dmamode |= STM32_DMA_CR_PFCTRL |
+                   STM32_DMA_CR_PBURST_INCR4 |
+                   STM32_DMA_CR_MBURST_INCR4;
+#endif
+
+  if (sdcp->state == BLK_STOP) {
+    /* Note, the DMA must be enabled before the IRQs.*/
+    bool b;
+    b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDIO_IRQ_PRIORITY, NULL, NULL);
+    osalDbgAssert(!b, "stream already allocated");
+    dmaStreamSetPeripheral(sdcp->dma, &SDIO->FIFO);
+#if (defined(STM32F4XX) || defined(STM32F2XX))
+    dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL);
+#endif
+    nvicEnableVector(STM32_SDIO_NUMBER, STM32_SDC_SDIO_IRQ_PRIORITY);
+    rccEnableSDIO(FALSE);
+  }
+
+  /* Configuration, card clock is initially stopped.*/
+  SDIO->POWER  = 0;
+  SDIO->CLKCR  = 0;
+  SDIO->DCTRL  = 0;
+  SDIO->DTIMER = 0;
+}
+
+/**
+ * @brief   Deactivates the SDC peripheral.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop(SDCDriver *sdcp) {
+
+  if (sdcp->state != BLK_STOP) {
+
+    /* SDIO deactivation.*/
+    SDIO->POWER  = 0;
+    SDIO->CLKCR  = 0;
+    SDIO->DCTRL  = 0;
+    SDIO->DTIMER = 0;
+
+    /* Clock deactivation.*/
+    nvicDisableVector(STM32_SDIO_NUMBER);
+    dmaStreamRelease(sdcp->dma);
+    rccDisableSDIO(FALSE);
+  }
+}
+
+/**
+ * @brief   Starts the SDIO clock and sets it to init mode (400kHz or less).
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start_clk(SDCDriver *sdcp) {
+
+  (void)sdcp;
+
+  /* Initial clock setting: 400kHz, 1bit mode.*/
+  SDIO->CLKCR  = STM32_SDIO_DIV_LS;
+  SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1;
+  SDIO->CLKCR |= SDIO_CLKCR_CLKEN;
+
+  /* Clock activation delay.*/
+  osalThreadSleep(MS2ST(STM32_SDC_CLOCK_ACTIVATION_DELAY));
+}
+
+/**
+ * @brief   Sets the SDIO clock to data mode (25MHz or less).
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_set_data_clk(SDCDriver *sdcp) {
+
+  (void)sdcp;
+
+  SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS;
+}
+
+/**
+ * @brief   Stops the SDIO clock.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop_clk(SDCDriver *sdcp) {
+
+  (void)sdcp;
+
+  SDIO->CLKCR = 0;
+  SDIO->POWER = 0;
+}
+
+/**
+ * @brief   Switches the bus to 4 bits mode.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] mode      bus mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
+  uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS;
+
+  (void)sdcp;
+
+  switch (mode) {
+  case SDC_MODE_1BIT:
+    SDIO->CLKCR = clk;
+    break;
+  case SDC_MODE_4BIT:
+    SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0;
+    break;
+  case SDC_MODE_8BIT:
+    SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1;
+    break;
+  }
+}
+
+/**
+ * @brief   Sends an SDIO command with no response expected.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] cmd       card command
+ * @param[in] arg       command argument
+ *
+ * @notapi
+ */
+void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
+
+  (void)sdcp;
+
+  SDIO->ARG = arg;
+  SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN;
+  while ((SDIO->STA & SDIO_STA_CMDSENT) == 0)
+    ;
+  SDIO->ICR = SDIO_ICR_CMDSENTC;
+}
+
+/**
+ * @brief   Sends an SDIO command with a short response expected.
+ * @note    The CRC is not verified.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] cmd       card command
+ * @param[in] arg       command argument
+ * @param[out] resp     pointer to the response buffer (one word)
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                            uint32_t *resp) {
+  uint32_t sta;
+
+  (void)sdcp;
+
+  SDIO->ARG = arg;
+  SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN;
+  while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
+                               SDIO_STA_CCRCFAIL)) == 0)
+    ;
+  SDIO->ICR = sta;
+  if ((sta & (SDIO_STA_CTIMEOUT)) != 0) {
+    sdc_lld_collect_errors(sdcp, sta);
+    return HAL_FAILED;
+  }
+  *resp = SDIO->RESP1;
+  return HAL_SUCCESS;
+}
+
+/**
+ * @brief   Sends an SDIO command with a short response expected and CRC.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] cmd       card command
+ * @param[in] arg       command argument
+ * @param[out] resp     pointer to the response buffer (one word)
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                                uint32_t *resp) {
+  uint32_t sta;
+
+  (void)sdcp;
+
+  SDIO->ARG = arg;
+  SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN;
+  while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
+                               SDIO_STA_CCRCFAIL)) == 0)
+    ;
+  SDIO->ICR = sta;
+  if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) {
+    sdc_lld_collect_errors(sdcp, sta);
+    return HAL_FAILED;
+  }
+  *resp = SDIO->RESP1;
+  return HAL_SUCCESS;
+}
+
+/**
+ * @brief   Sends an SDIO command with a long response expected and CRC.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] cmd       card command
+ * @param[in] arg       command argument
+ * @param[out] resp     pointer to the response buffer (four words)
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                               uint32_t *resp) {
+  uint32_t sta;
+
+  (void)sdcp;
+
+  SDIO->ARG = arg;
+  SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 |
+                              SDIO_CMD_CPSMEN;
+  while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT |
+                               SDIO_STA_CCRCFAIL)) == 0)
+    ;
+  SDIO->ICR = sta;
+  if ((sta & (STM32_SDIO_STA_ERROR_MASK)) != 0) {
+    sdc_lld_collect_errors(sdcp, sta);
+    return HAL_FAILED;
+  }
+  /* Save bytes in reverse order because MSB in response comes first.*/
+  *resp++ = SDIO->RESP4;
+  *resp++ = SDIO->RESP3;
+  *resp++ = SDIO->RESP2;
+  *resp   = SDIO->RESP1;
+  return HAL_SUCCESS;
+}
+
+/**
+ * @brief   Reads one or more blocks.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to read
+ * @param[out] buf      pointer to the read buffer
+ * @param[in] n         number of blocks to read
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
+                          uint8_t *buf, uint32_t n) {
+  uint32_t resp[1];
+
+  osalDbgCheck(n < 0x1000000 / MMCSD_BLOCK_SIZE);
+
+  SDIO->DTIMER = STM32_SDC_READ_TIMEOUT;
+
+  /* Checks for errors and waits for the card to be ready for reading.*/
+  if (_sdc_wait_for_transfer_state(sdcp))
+    return HAL_FAILED;
+
+  /* Prepares the DMA channel for writing.*/
+  dmaStreamSetMemory0(sdcp->dma, buf);
+  dmaStreamSetTransactionSize(sdcp->dma,
+                              (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
+  dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M);
+  dmaStreamEnable(sdcp->dma);
+
+  /* Setting up data transfer.*/
+  SDIO->ICR   = STM32_SDIO_ICR_ALL_FLAGS;
+  SDIO->MASK  = SDIO_MASK_DCRCFAILIE |
+                SDIO_MASK_DTIMEOUTIE |
+                SDIO_MASK_STBITERRIE |
+                SDIO_MASK_RXOVERRIE |
+                SDIO_MASK_DATAENDIE;
+  SDIO->DLEN  = n * MMCSD_BLOCK_SIZE;
+
+  /* Transaction starts just after DTEN bit setting.*/
+  SDIO->DCTRL = SDIO_DCTRL_DTDIR |
+                SDIO_DCTRL_DBLOCKSIZE_3 |
+                SDIO_DCTRL_DBLOCKSIZE_0 |
+                SDIO_DCTRL_DMAEN |
+                SDIO_DCTRL_DTEN;
+
+  /* Talk to card what we want from it.*/
+  if (sdc_lld_prepare_read(sdcp, startblk, n, resp) == TRUE)
+    goto error;
+  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE)
+    goto error;
+
+  return HAL_SUCCESS;
+
+error:
+  sdc_lld_error_cleanup(sdcp, n, resp);
+  return HAL_FAILED;
+}
+
+/**
+ * @brief   Writes one or more blocks.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to write
+ * @param[out] buf      pointer to the write buffer
+ * @param[in] n         number of blocks to write
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
+                           const uint8_t *buf, uint32_t n) {
+  uint32_t resp[1];
+
+  osalDbgCheck(n < 0x1000000 / MMCSD_BLOCK_SIZE);
+
+  SDIO->DTIMER = STM32_SDC_WRITE_TIMEOUT;
+
+  /* Checks for errors and waits for the card to be ready for writing.*/
+  if (_sdc_wait_for_transfer_state(sdcp))
+    return HAL_FAILED;
+
+  /* Prepares the DMA channel for writing.*/
+  dmaStreamSetMemory0(sdcp->dma, buf);
+  dmaStreamSetTransactionSize(sdcp->dma,
+                              (n * MMCSD_BLOCK_SIZE) / sizeof (uint32_t));
+  dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_M2P);
+  dmaStreamEnable(sdcp->dma);
+
+  /* Setting up data transfer.*/
+  SDIO->ICR   = STM32_SDIO_ICR_ALL_FLAGS;
+  SDIO->MASK  = SDIO_MASK_DCRCFAILIE |
+                SDIO_MASK_DTIMEOUTIE |
+                SDIO_MASK_STBITERRIE |
+                SDIO_MASK_TXUNDERRIE |
+                SDIO_MASK_DATAENDIE;
+  SDIO->DLEN  = n * MMCSD_BLOCK_SIZE;
+
+  /* Talk to card what we want from it.*/
+  if (sdc_lld_prepare_write(sdcp, startblk, n, resp) == TRUE)
+    goto error;
+
+  /* Transaction starts just after DTEN bit setting.*/
+  SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 |
+                SDIO_DCTRL_DBLOCKSIZE_0 |
+                SDIO_DCTRL_DMAEN |
+                SDIO_DCTRL_DTEN;
+  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE)
+    goto error;
+
+  return HAL_SUCCESS;
+
+error:
+  sdc_lld_error_cleanup(sdcp, n, resp);
+  return HAL_FAILED;
+}
+
+/**
+ * @brief   Reads one or more blocks.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to read
+ * @param[out] buf      pointer to the read buffer
+ * @param[in] n         number of blocks to read
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+                  uint8_t *buf, uint32_t n) {
+
+#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
+  if (((unsigned)buf & 3) != 0) {
+    uint32_t i;
+    for (i = 0; i < n; i++) {
+      if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1))
+        return HAL_FAILED;
+      memcpy(buf, u.buf, MMCSD_BLOCK_SIZE);
+      buf += MMCSD_BLOCK_SIZE;
+      startblk++;
+    }
+    return HAL_SUCCESS;
+  }
+#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+  return sdc_lld_read_aligned(sdcp, startblk, buf, n);
+}
+
+/**
+ * @brief   Writes one or more blocks.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to write
+ * @param[out] buf      pointer to the write buffer
+ * @param[in] n         number of blocks to write
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+                   const uint8_t *buf, uint32_t n) {
+
+#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
+  if (((unsigned)buf & 3) != 0) {
+    uint32_t i;
+    for (i = 0; i < n; i++) {
+      memcpy(u.buf, buf, MMCSD_BLOCK_SIZE);
+      buf += MMCSD_BLOCK_SIZE;
+      if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1))
+        return HAL_FAILED;
+      startblk++;
+    }
+    return HAL_SUCCESS;
+  }
+#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
+  return sdc_lld_write_aligned(sdcp, startblk, buf, n);
+}
+
+/**
+ * @brief   Waits for card idle condition.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  the operation succeeded.
+ * @retval HAL_FAILED   the operation failed.
+ *
+ * @api
+ */
+bool sdc_lld_sync(SDCDriver *sdcp) {
+
+  /* TODO: Implement.*/
+  (void)sdcp;
+  return HAL_SUCCESS;
+}
+
+#endif /* HAL_USE_SDC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/sdc_lld.h b/os/hal/ports/STM32/LLD/sdc_lld.h
new file mode 100644
index 000000000..6f0e389d6
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/sdc_lld.h
@@ -0,0 +1,322 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32/sdc_lld.h
+ * @brief   STM32 SDC subsystem low level driver header.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#ifndef _SDC_LLD_H_
+#define _SDC_LLD_H_
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief Value to clear all interrupts flag at once.
+ */
+#define STM32_SDIO_ICR_ALL_FLAGS (SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC | \
+                                  SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC | \
+                                  SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC |  \
+                                  SDIO_ICR_CMDRENDC  | SDIO_ICR_CMDSENTC |  \
+                                  SDIO_ICR_DATAENDC  | SDIO_ICR_STBITERRC | \
+                                  SDIO_ICR_DBCKENDC  | SDIO_ICR_SDIOITC |   \
+                                  SDIO_ICR_CEATAENDC)
+
+/**
+ * @brief Mask of error flags in STA register.
+ */
+#define STM32_SDIO_STA_ERROR_MASK (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL |  \
+                                   SDIO_STA_CTIMEOUT | SDIO_STA_DTIMEOUT |  \
+                                   SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   SDIO DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SDC_SDIO_DMA_PRIORITY         3
+#endif
+
+/**
+ * @brief   SDIO interrupt priority level setting.
+ */
+#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SDC_SDIO_IRQ_PRIORITY         9
+#endif
+
+/**
+ * @brief   Write timeout in milliseconds.
+ */
+#if !defined(STM32_SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__)
+#define STM32_SDC_WRITE_TIMEOUT_MS          250
+#endif
+
+/**
+ * @brief   Read timeout in milliseconds.
+ */
+#if !defined(STM32_SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__)
+#define STM32_SDC_READ_TIMEOUT_MS           25
+#endif
+
+/**
+ * @brief   Card clock activation delay in milliseconds.
+ */
+#if !defined(STM32_SDC_CLOCK_ACTIVATION_DELAY) || defined(__DOXYGEN__)
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY    10
+#endif
+
+/**
+ * @brief   Support for unaligned transfers.
+ * @note    Unaligned transfers are much slower.
+ */
+#if !defined(STM32_SDC_SDIO_UNALIGNED_SUPPORT) || defined(__DOXYGEN__)
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !STM32_HAS_SDIO
+#error "SDIO not present in the selected device"
+#endif
+
+#if !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SDC_SDIO_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDIO"
+#endif
+
+#if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDIO_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SDIO"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+   reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if !defined(STM32_SDC_SDIO_DMA_STREAM)
+#error "SDIO DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if !STM32_DMA_IS_VALID_ID(STM32_SDC_SDIO_DMA_STREAM, STM32_SDC_SDIO_DMA_MSK)
+#error "invalid DMA stream associated to SDIO"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*
+ * SDIO clock divider.
+ */
+#if (defined(STM32F4XX) || defined(STM32F2XX))
+#define STM32_SDIO_DIV_HS                   0
+#define STM32_SDIO_DIV_LS                   120
+
+#elif STM32_HCLK > 48000000
+#define STM32_SDIO_DIV_HS                   1
+#define STM32_SDIO_DIV_LS                   178
+#else
+
+#define STM32_SDIO_DIV_HS                   0
+#define STM32_SDIO_DIV_LS                   118
+#endif
+
+/**
+ * @brief   SDIO data timeouts in SDIO clock cycles.
+ */
+#if (defined(STM32F4XX) || defined(STM32F2XX))
+#if !STM32_CLOCK48_REQUIRED
+#error "SDIO requires STM32_CLOCK48_REQUIRED to be enabled"
+#endif
+
+#define STM32_SDC_WRITE_TIMEOUT                                             \
+  (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) *                    \
+   STM32_SDC_WRITE_TIMEOUT_MS)
+#define STM32_SDC_READ_TIMEOUT                                              \
+  (((STM32_PLL48CLK / (STM32_SDIO_DIV_HS + 2)) / 1000) *                    \
+   STM32_SDC_READ_TIMEOUT_MS)
+
+#else /* !(defined(STM32F4XX) || defined(STM32F2XX)) */
+
+#define STM32_SDC_WRITE_TIMEOUT                                             \
+  (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) *                        \
+   STM32_SDC_WRITE_TIMEOUT_MS)
+#define STM32_SDC_READ_TIMEOUT                                              \
+  (((STM32_HCLK / (STM32_SDIO_DIV_HS + 2)) / 1000) *                        \
+   STM32_SDC_READ_TIMEOUT_MS)
+
+#endif /* !(defined(STM32F4XX) || defined(STM32F2XX)) */
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of SDIO bus mode.
+ */
+typedef enum {
+  SDC_MODE_1BIT = 0,
+  SDC_MODE_4BIT,
+  SDC_MODE_8BIT
+} sdcbusmode_t;
+
+/**
+ * @brief   Type of card flags.
+ */
+typedef uint32_t sdcmode_t;
+
+/**
+ * @brief   SDC Driver condition flags type.
+ */
+typedef uint32_t sdcflags_t;
+
+/**
+ * @brief   Type of a structure representing an SDC driver.
+ */
+typedef struct SDCDriver SDCDriver;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  uint32_t dummy;
+} SDCConfig;
+
+/**
+ * @brief   @p SDCDriver specific methods.
+ */
+#define _sdc_driver_methods                                                 \
+  _mmcsd_block_device_methods
+
+/**
+ * @extends MMCSDBlockDeviceVMT
+ *
+ * @brief   @p SDCDriver virtual methods table.
+ */
+struct SDCDriverVMT {
+  _sdc_driver_methods
+};
+
+/**
+ * @brief   Structure representing an SDC driver.
+ */
+struct SDCDriver {
+  /**
+   * @brief Virtual Methods Table.
+   */
+  const struct SDCDriverVMT *vmt;
+  _mmcsd_block_device_data
+  /**
+   * @brief Current configuration data.
+   */
+  const SDCConfig           *config;
+  /**
+   * @brief Various flags regarding the mounted card.
+   */
+  sdcmode_t                 cardmode;
+  /**
+   * @brief Errors flags.
+   */
+  sdcflags_t                errors;
+  /**
+   * @brief Card RCA.
+   */
+  uint32_t                  rca;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Thread waiting for I/O completion IRQ.
+   */
+  thread_reference_t        thread;
+  /**
+   * @brief     DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+  /**
+   * @brief     Transmit DMA channel.
+   */
+  const stm32_dma_stream_t  *dma;
+#if CH_DBG_ENABLE_ASSERTS || defined(__DOXYGEN__)
+  /**
+   * @brief     Pointer to the SDIO registers block.
+   * @note      Used only for dubugging purpose.
+   */
+  SDIO_TypeDef              *sdio;
+#endif
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern SDCDriver SDCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void sdc_lld_init(void);
+  void sdc_lld_start(SDCDriver *sdcp);
+  void sdc_lld_stop(SDCDriver *sdcp);
+  void sdc_lld_start_clk(SDCDriver *sdcp);
+  void sdc_lld_set_data_clk(SDCDriver *sdcp);
+  void sdc_lld_stop_clk(SDCDriver *sdcp);
+  void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
+  void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
+  bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                              uint32_t *resp);
+  bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                                  uint32_t *resp);
+  bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                                 uint32_t *resp);
+  bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+                    uint8_t *buf, uint32_t n);
+  bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+                     const uint8_t *buf, uint32_t n);
+  bool sdc_lld_sync(SDCDriver *sdcp);
+  bool sdc_lld_is_card_inserted(SDCDriver *sdcp);
+  bool sdc_lld_is_write_protected(SDCDriver *sdcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SDC */
+
+#endif /* _SDC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/adc_lld.c b/os/hal/ports/STM32/STM32F0xx/adc_lld.c
new file mode 100644
index 000000000..9e95c0007
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/adc_lld.c
@@ -0,0 +1,296 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F0xx/adc_lld.c
+ * @brief   STM32F0xx ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Stops an ongoing conversion, if any.
+ *
+ * @param[in] adc       pointer to the ADC registers block
+ */
+static void adc_lld_stop_adc(ADC_TypeDef *adc) {
+
+  if (adc->CR & ADC_CR_ADSTART) {
+    adc->CR |= ADC_CR_ADSTP;
+    while (adc->CR & ADC_CR_ADSTP)
+      ;
+  }
+}
+
+/**
+ * @brief   ADC DMA ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    /* DMA, this could help only if the DMA tries to access an unmapped
+       address space or violates alignment rules.*/
+    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+  }
+  else {
+    /* It is possible that the conversion group has already be reset by the
+       ADC error handler, in this case this interrupt is spurious.*/
+    if (adcp->grpp != NULL) {
+      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+        /* Transfer complete processing.*/
+        _adc_isr_full_code(adcp);
+      }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief   ADC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  isr = ADC1->ISR;
+  ADC1->ISR = isr;
+
+  /* It could be a spurious interrupt caused by overflows after DMA disabling,
+     just ignore it in this case.*/
+  if (ADCD1.grpp != NULL) {
+    /* Note, an overflow may occur after the conversion ended before the driver
+       is able to stop the ADC, this is why the DMA channel is checked too.*/
+    if ((isr & ADC_ISR_OVR) &&
+        (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
+      /* ADC overflow condition, this could happen only if the DMA is unable
+         to read data fast enough.*/
+      _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+    }
+    if (isr & ADC_ISR_AWD) {
+      /* Analog watchdog error.*/
+      _adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
+    }
+  }
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adc = ADC1;
+  ADCD1.dmastp  = STM32_DMA1_STREAM1;
+  ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+#endif
+
+  /* The shared vector is initialized on driver initialization and never
+     disabled.*/
+  nvicEnableVector(12, STM32_ADC_IRQ_PRIORITY);
+
+  /* Calibration procedure.*/
+  rccEnableADC1(FALSE);
+  osalDbgAssert(ADC1->CR == 0, "invalid register state");
+  ADC1->CR |= ADC_CR_ADCAL;
+  while (ADC1->CR & ADC_CR_ADCAL)
+    ;
+  rccDisableADC1(FALSE);
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+  /* If in stopped state then enables the ADC and DMA clocks.*/
+  if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      bool b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+                            (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+      rccEnableADC1(FALSE);
+#if STM32_ADCSW == STM32_ADCSW_HSI14
+      /* Clock from HSI14, no need for jitter removal.*/
+      ADC1->CFGR2 = 0x00001000;
+#else
+#if STM32_ADCPRE == STM32_ADCPRE_DIV2
+      ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV2;
+#else
+      ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV4;
+#endif
+#endif
+    }
+#endif /* STM32_ADC_USE_ADC1 */
+
+    /* ADC initial setup, starting the analog part here in order to reduce
+       the latency when starting a conversion.*/
+    adcp->adc->CR = ADC_CR_ADEN;
+    while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
+      ;
+  }
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+  /* If in ready state then disables the ADC clock and analog part.*/
+  if (adcp->state == ADC_READY) {
+
+    dmaStreamRelease(adcp->dmastp);
+
+    /* Disabling ADC.*/
+    if (adcp->adc->CR & ADC_CR_ADEN) {
+      adc_lld_stop_adc(adcp->adc);
+      adcp->adc->CR |= ADC_CR_ADDIS;
+      while (adcp->adc->CR & ADC_CR_ADDIS)
+        ;
+    }
+
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp)
+      rccDisableADC1(FALSE);
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+  uint32_t mode;
+  const ADCConversionGroup *grpp = adcp->grpp;
+
+  /* DMA setup.*/
+  mode = adcp->dmamode;
+  if (grpp->circular) {
+    mode |= STM32_DMA_CR_CIRC;
+    if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
+    }
+  }
+  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+                                            (uint32_t)adcp->depth);
+  dmaStreamSetMode(adcp->dmastp, mode);
+  dmaStreamEnable(adcp->dmastp);
+
+  /* ADC setup, if it is defined a callback for the analog watch dog then it
+     is enabled.*/
+  adcp->adc->ISR    = adcp->adc->ISR;
+  adcp->adc->IER    = ADC_IER_OVRIE | ADC_IER_AWDIE;
+  adcp->adc->TR     = grpp->tr;
+  adcp->adc->SMPR   = grpp->smpr;
+  adcp->adc->CHSELR = grpp->chselr;
+
+  /* ADC configuration and start.*/
+  adcp->adc->CFGR1  = grpp->cfgr1 | ADC_CFGR1_CONT  | ADC_CFGR1_DMACFG |
+                                    ADC_CFGR1_DMAEN;
+  adcp->adc->CR    |= ADC_CR_ADSTART;
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+  dmaStreamDisable(adcp->dmastp);
+  adc_lld_stop_adc(adcp->adc);
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/adc_lld.h b/os/hal/ports/STM32/STM32F0xx/adc_lld.h
new file mode 100644
index 000000000..bddb6453a
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/adc_lld.h
@@ -0,0 +1,329 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F0xx/adc_lld.h
+ * @brief   STM32F0xx ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Sampling rates
+ * @{
+ */
+#define ADC_SMPR_SMP_1P5        0   /**< @brief 14 cycles conversion time   */
+#define ADC_SMPR_SMP_7P5        1   /**< @brief 21 cycles conversion time.  */
+#define ADC_SMPR_SMP_13P5       2   /**< @brief 28 cycles conversion time.  */
+#define ADC_SMPR_SMP_28P5       3   /**< @brief 41 cycles conversion time.  */
+#define ADC_SMPR_SMP_41P5       4   /**< @brief 54 cycles conversion time.  */
+#define ADC_SMPR_SMP_55P5       5   /**< @brief 68 cycles conversion time.  */
+#define ADC_SMPR_SMP_71P5       6   /**< @brief 84 cycles conversion time.  */
+#define ADC_SMPR_SMP_239P5      7   /**< @brief 252 cycles conversion time. */
+/** @} */
+
+/**
+ * @name    Resolution
+ * @{
+ */
+#define ADC_CFGR1_RES_12BIT     (0 << 3)
+#define ADC_CFGR1_RES_10BIT     (1 << 3)
+#define ADC_CFGR1_RES_8BIT      (2 << 3)
+#define ADC_CFGR1_RES_6BIT      (3 << 3)
+/** @} */
+
+/**
+ * @name    Threashold register initializer
+ * @{
+ */
+#define ADC_TR(low, high)       (((uint32_t)(high) << 16) | (uint32_t)(low))
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1                  FALSE
+#endif
+
+/**
+ * @brief   ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   ADC interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_IRQ_PRIORITY              2
+#endif
+
+/**
+ * @brief   ADC1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief   Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief   Possible ADC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
+  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
+  ADC_ERR_AWD = 2                           /**< Analog watchdog triggered. */
+} adcerror_t;
+
+/**
+ * @brief   Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief   ADC notification callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] buffer    pointer to the most recent samples data
+ * @param[in] n         number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief   ADC error callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] err       ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief   Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ *          operation.
+ * @note    The use of this configuration structure requires knowledge of
+ *          STM32 ADC cell registers interface, please refer to the STM32
+ *          reference manual for details.
+ */
+typedef struct {
+  /**
+   * @brief   Enables the circular buffer mode for the group.
+   */
+  bool                      circular;
+  /**
+   * @brief   Number of the analog channels belonging to the conversion group.
+   */
+  adc_channels_num_t        num_channels;
+  /**
+   * @brief   Callback function associated to the group or @p NULL.
+   */
+  adccallback_t             end_cb;
+  /**
+   * @brief   Error callback or @p NULL.
+   */
+  adcerrorcallback_t        error_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   ADC CFGR1 register initialization data.
+   */
+  uint32_t                  cfgr1;
+  /**
+   * @brief   ADC TR register initialization data.
+   */
+  uint32_t                  tr;
+  /**
+   * @brief   ADC SMPR register initialization data.
+   */
+  uint32_t                  smpr;
+  /**
+   * @brief   ADC CHSELR register initialization data.
+   * @details The number of bits at logic level one in this register must
+   *          be equal to the number in the @p num_channels field.
+   */
+  uint32_t                  chselr;
+} ADCConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  uint32_t                  dummy;
+} ADCConfig;
+
+/**
+ * @brief   Structure representing an ADC driver.
+ */
+struct ADCDriver {
+  /**
+   * @brief Driver state.
+   */
+  adcstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const ADCConfig           *config;
+  /**
+   * @brief Current samples buffer pointer or @p NULL.
+   */
+  adcsample_t               *samples;
+  /**
+   * @brief Current samples buffer depth or @p 0.
+   */
+  size_t                    depth;
+  /**
+   * @brief Current conversion group pointer or @p NULL.
+   */
+  const ADCConversionGroup  *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+  ADC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the ADCx registers block.
+   */
+  ADC_TypeDef               *adc;
+  /**
+   * @brief Pointer to associated DMA channel.
+   */
+  const stm32_dma_stream_t  *dmastp;
+  /**
+   * @brief DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Changes the value of the ADC CCR register.
+ * @details Use this function in order to enable or disable the internal
+ *          analog sources. See the documentation in the STM32F0xx Reference
+ *          Manual.
+ */
+#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adc_lld_init(void);
+  void adc_lld_start(ADCDriver *adcp);
+  void adc_lld_stop(ADCDriver *adcp);
+  void adc_lld_start_conversion(ADCDriver *adcp);
+  void adc_lld_stop_conversion(ADCDriver *adcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c
new file mode 100644
index 000000000..fb5100e8c
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c
@@ -0,0 +1,197 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F0xx/ext_lld_isr.c
+ * @brief   STM32F0xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   EXTI[0]...EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector54) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 0) | (1 << 1));
+  EXTI->PR = pr;
+  if (pr & (1 << 0))
+    EXTD1.config->channels[0].cb(&EXTD1, 0);
+  if (pr & (1 << 1))
+    EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[2]...EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 2) | (1 << 3));
+  EXTI->PR = pr;
+  if (pr & (1 << 2))
+    EXTD1.config->channels[2].cb(&EXTD1, 2);
+  if (pr & (1 << 3))
+    EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[4]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 4)  | (1 << 5)  | (1 << 6)  | (1 << 7)  | (1 << 8)  |
+                   (1 << 9)  | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) |
+                   (1 << 14) | (1 << 15));
+  EXTI->PR = pr;
+  if (pr & (1 << 4))
+    EXTD1.config->channels[4].cb(&EXTD1, 4);
+  if (pr & (1 << 5))
+    EXTD1.config->channels[5].cb(&EXTD1, 5);
+  if (pr & (1 << 6))
+    EXTD1.config->channels[6].cb(&EXTD1, 6);
+  if (pr & (1 << 7))
+    EXTD1.config->channels[7].cb(&EXTD1, 7);
+  if (pr & (1 << 8))
+    EXTD1.config->channels[8].cb(&EXTD1, 8);
+  if (pr & (1 << 9))
+    EXTD1.config->channels[9].cb(&EXTD1, 9);
+  if (pr & (1 << 10))
+    EXTD1.config->channels[10].cb(&EXTD1, 10);
+  if (pr & (1 << 11))
+    EXTD1.config->channels[11].cb(&EXTD1, 11);
+  if (pr & (1 << 12))
+    EXTD1.config->channels[12].cb(&EXTD1, 12);
+  if (pr & (1 << 13))
+    EXTD1.config->channels[13].cb(&EXTD1, 13);
+  if (pr & (1 << 14))
+    EXTD1.config->channels[14].cb(&EXTD1, 14);
+  if (pr & (1 << 15))
+    EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 16);
+  EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[17] interrupt handler (RTC).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 17);
+  EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+  nvicEnableVector(EXTI0_1_IRQn, STM32_EXT_EXTI0_1_IRQ_PRIORITY);
+  nvicEnableVector(EXTI2_3_IRQn, STM32_EXT_EXTI2_3_IRQ_PRIORITY);
+  nvicEnableVector(EXTI4_15_IRQn, STM32_EXT_EXTI4_15_IRQ_PRIORITY);
+  nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+  nvicEnableVector(RTC_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+}
+
+/**
+ * @brief   Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+  nvicDisableVector(EXTI0_1_IRQn);
+  nvicDisableVector(EXTI2_3_IRQn);
+  nvicDisableVector(EXTI4_15_IRQn);
+  nvicDisableVector(PVD_IRQn);
+  nvicDisableVector(RTC_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h
index 9885fbc65..9885fbc65 100644
--- a/os/hal/platforms/STM32F0xx/ext_lld_isr.h
+++ b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
new file mode 100644
index 000000000..9b6a85b91
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
@@ -0,0 +1,199 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F0xx/hal_lld.c
+ * @brief   STM32F0xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the backup domain.
+ * @note    WARNING! Changing clock source impossible without resetting
+ *          of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+  /* Backup domain access enabled and left open.*/
+  PWR->CR |= PWR_CR_DBP;
+
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0;
+  }
+
+  /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+#if defined(STM32_LSE_BYPASS)
+  /* LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+  /* No LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                     /* Waits until LSE is stable.   */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+    /* Selects clock source.*/
+    RCC->BDCR |= STM32_RTCSEL;
+
+    /* RTC clock enabled.*/
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+  /* Reset of all peripherals.*/
+  rccResetAPB1(0xFFFFFFFF);
+  rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
+
+  /* PWR clock enabled.*/
+  rccEnablePWRInterface(FALSE);
+
+  /* Initializes the backup domain.*/
+  hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+  dmaInit();
+#endif
+
+  /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief   STM32 clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* HSI setup, it enforces the reset situation in order to handle possible
+     problems with JTAG probes and re-initializations.*/
+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;                                       /* Wait until HSI is stable.    */
+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
+  RCC->CFGR = 0;                            /* CFGR reset value.            */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;                                       /* Waits until HSI is selected. */
+
+#if STM32_HSE_ENABLED
+  /* HSE activation.*/
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+  /* No HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON;
+#endif
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;                                       /* Waits until HSE is stable.   */
+#endif
+
+#if STM32_HSE14_ENABLED
+  /* HSI14 activation.*/
+  RCC->CR2 |= RCC_CR2_HSI14ON;
+  while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
+    ;                                       /* Waits until HSI14 is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                                       /* Waits until LSI is stable.   */
+#endif
+
+  /* Clock settings.*/
+  RCC->CFGR  = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
+               STM32_ADCPRE | STM32_PPRE   | STM32_HPRE;
+  RCC->CFGR2 = STM32_PREDIV;
+  RCC->CFGR3 = STM32_ADCSW  | STM32_CECSW  | STM32_I2C1SW |
+               STM32_USART1SW;
+
+#if STM32_ACTIVATE_PLL
+  /* PLL activation.*/
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                                       /* Waits until PLL is stable.   */
+#endif
+
+  /* Flash setup and final clock selection.   */
+  FLASH->ACR = STM32_FLASHBITS;
+
+  /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+  /* Switches clock source.*/
+  RCC->CFGR |= STM32_SW;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;                                       /* Waits selection complete.    */
+#endif
+
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+#endif /* !STM32_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h
new file mode 100644
index 000000000..044b13a37
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h
@@ -0,0 +1,791 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F0xx/hal_lld.h
+ * @brief   STM32F0xx HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - STM32_LSECLK.
+ *          - STM32_LSEDRV.
+ *          - STM32_LSE_BYPASS (optionally).
+ *          - STM32_HSECLK.
+ *          - STM32_HSE_BYPASS (optionally).
+ *          .
+ *          One of the following macros must also be defined:
+ *          - STM32F030 for Value Line devices.
+ *          - STM32F0XX_LD for Low Density devices.
+ *          - STM32F0XX_MD for Medium Density devices.
+ *          .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification macros
+ * @{
+ */
+#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
+#define PLATFORM_NAME           "STM32F051xx/F061xx Entry Level Medium Density devices"
+#define STM32F0XX
+
+#elif defined(STM32F0XX_LD)
+#define PLATFORM_NAME           "STM32F050xx/F060xx Entry Level Low Density devices"
+#define STM32F0XX
+
+#elif defined(STM32F030)
+#define PLATFORM_NAME           "STM32F050xx/F060xx Entry Level Value Line devices"
+#define STM32F0XX
+
+#else
+#error "STM32F0xx device not specified"
+#endif
+/** @} */
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX        48000000
+
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        32000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        1000000
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        1000000
+
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX         25000000
+
+/**
+ * @brief   Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN         1000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX        48000000
+
+/**
+ * @brief   Minimum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN        16000000
+
+/**
+ * @brief   Maximum APB clock frequency.
+ */
+#define STM32_PCLK_MAX          48000000
+
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX        14000000
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK            8000000     /**< High speed internal clock. */
+#define STM32_HSI14CLK          14000000    /**< 14MHz speed internal clock.*/
+#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
+/** @} */
+
+/**
+ * @name    PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE_DIV1         (0 << 8)    /**< HCLK divided by 1.         */
+#define STM32_PPRE_DIV2         (4 << 8)    /**< HCLK divided by 2.         */
+#define STM32_PPRE_DIV4         (5 << 8)    /**< HCLK divided by 4.         */
+#define STM32_PPRE_DIV8         (6 << 8)    /**< HCLK divided by 8.         */
+#define STM32_PPRE_DIV16        (7 << 8)    /**< HCLK divided by 16.        */
+
+#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PCLK divided by 2.         */
+#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PCLK divided by 4.         */
+
+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
+#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
+
+#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_HSI14      (3 << 24)   /**< HSI14 clock on MCO pin.    */
+#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
+/** @} */
+
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
+#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
+#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
+#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
+#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 32 used as
+                                                 RTC clock.                 */
+/** @} */
+
+/**
+ * @name    RCC_CFGR3 register bits definitions
+ * @{
+ */
+#define STM32_USART1SW_MASK     (3 << 0)    /**< USART1 clock source mask.  */
+#define STM32_USART1SW_PCLK     (0 << 0)    /**< USART1 clock is PCLK.      */
+#define STM32_USART1SW_SYSCLK   (1 << 0)    /**< USART1 clock is SYSCLK.    */
+#define STM32_USART1SW_LSE      (2 << 0)    /**< USART1 clock is LSE.       */
+#define STM32_USART1SW_HSI      (3 << 0)    /**< USART1 clock is HSI.       */
+#define STM32_I2C1SW_MASK       (1 << 4)    /**< I2C clock source mask.     */
+#define STM32_I2C1SW_HSI        (0 << 4)    /**< I2C clock is HSI.          */
+#define STM32_I2C1SW_SYSCLK     (1 << 4)    /**< I2C clock is SYSCLK.       */
+#define STM32_CECSW_MASK        (1 << 6)    /**< CEC clock source mask.     */
+#define STM32_CECSW_HSI         (0 << 6)    /**< CEC clock is HSI/244.      */
+#define STM32_CECSW_LSE         (1 << 6)    /**< CEC clock is LSE.          */
+#define STM32_ADCSW_MASK        (1 << 8)    /**< ADC clock source mask.     */
+#define STM32_ADCSW_HSI14       (0 << 8)    /**< ADC clock is HSI14.        */
+#define STM32_ADCSW_PCLK        (1 << 8)    /**< ADC clock is PCLK/2|4.     */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT               FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE            FALSE
+#endif
+
+/**
+ * @brief   Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                   STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief   Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the HSI14 clock source.
+ */
+#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI14_ENABLED         TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED           FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED           FALSE
+#endif
+
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 48MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                    STM32_SW_PLL
+#endif
+
+/**
+ * @brief   Clock source for the PLL.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 48MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief   Crystal PLL pre-divider.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PREDIV_VALUE                  1
+#endif
+
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed range is 2...16.
+ * @note    The default value is calculated for a 48MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE          6
+#endif
+
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 48MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                  STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
+#define STM32_PPRE                  STM32_PPRE_DIV1
+#endif
+
+/**
+ * @brief   MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief   ADC prescaler value.
+ */
+#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADCPRE                STM32_ADCPRE_DIV4
+#endif
+
+/**
+ * @brief   ADC clock source.
+ */
+#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
+#define STM32_ADCSW                 STM32_ADCSW_HSI14
+#endif
+
+/**
+ * @brief   CEC clock source.
+ */
+#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
+#define STM32_CECSW                 STM32_CECSW_HSI
+#endif
+
+/**
+ * @brief   I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
+#define STM32_I2C1SW                STM32_I2C1SW_HSI
+#endif
+
+/**
+ * @brief   USART1 clock source.
+ */
+#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
+#define STM32_USART1SW              STM32_USART1SW_PCLK
+#endif
+
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                STM32_RTCSEL_LSI
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F0xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if STM32_CECSW == STM32_CECSW_HSI
+#error "HSI not enabled, required by STM32_CECSW"
+#endif
+
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#error "HSI not enabled, required by STM32_I2C1SW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_HSI
+#error "HSI not enabled, required by STM32_USART1SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSI14 related checks.
+ */
+#if STM32_HSI14_ENABLED
+#else /* !STM32_HSI14_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_HSI14
+#error "HSI14 not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_ADCSW == STM32_ADCSW_HSI14
+#error "HSI14 not enabled, required by STM32_ADCSW"
+#endif
+
+#endif /* !STM32_HSI14_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined"
+#endif
+
+#if (STM32_LSEDRV >> 3) > 3
+#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
+#endif
+
+#if STM32_CECSW == STM32_CECSW_LSE
+#error "LSE not enabled, required by STM32_CECSW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_LSE
+#error "LSE not enabled, required by STM32_USART1SW"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+
+/* HSE prescaler setting check.*/
+#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
+#define STM32_PREDIV                ((STM32_PREDIV_VALUE - 1) << 0)
+#else
+#error "invalid STM32_PREDIV value specified"
+#endif
+
+/**
+ * @brief   PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PREDIV_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB frequency.
+ */
+#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK                  (STM32_HCLK / 1)
+#elif STM32_PPRE == STM32_PPRE_DIV2
+#define STM32_PCLK                  (STM32_HCLK / 2)
+#elif STM32_PPRE == STM32_PPRE_DIV4
+#define STM32_PCLK                  (STM32_HCLK / 4)
+#elif STM32_PPRE == STM32_PPRE_DIV8
+#define STM32_PCLK                  (STM32_HCLK / 8)
+#elif STM32_PPRE == STM32_PPRE_DIV16
+#define STM32_PCLK                  (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE value specified"
+#endif
+
+/* APB frequency check.*/
+#if STM32_PCLK > STM32_PCLK_MAX
+#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
+#endif
+
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                (STM32_HSECLK / 32)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK                0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief   ADC frequency.
+ */
+#if STM32_ADCSW == STM32_ADCSW_HSI14
+#define STM32_ADCCLK                STM32_HSI14CLK
+#elif STM32_ADCSW == STM32_ADCSW_PCLK
+#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_ADCCLK                (STM32_PCLK / 2)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
+#define STM32_ADCCLK                (STM32_PCLK / 4)
+#else
+#error "invalid STM32_ADCPRE value specified"
+#endif
+#else
+#error "invalid source selected for ADC clock"
+#endif
+
+/* ADC frequency check.*/
+#if STM32_ADCCLK > STM32_ADCCLK_MAX
+#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/**
+ * @brief   CEC frequency.
+ */
+#if STM32_CECSW == STM32_CECSW_HSI
+#define STM32_CECCLK                STM32_HSICLK
+#elif STM32_CECSW == STM32_CECSW_LSE
+#define STM32_CECCLK                STM32_LSECLK
+#else
+#error "invalid source selected for CEC clock"
+#endif
+
+/**
+ * @brief   I2C1 frequency.
+ */
+#if STM32_I2CSW == STM32_I2C1SW_HSI
+#define STM32_I2C1CLK               STM32_HSICLK
+#elif STM32_I2CSW == STM32_I2C1SW_SYSCLK
+#define STM32_I2C1CLK               STM32_SYSCLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief   USART1 frequency.
+ */
+#if STM32_USART1SW == STM32_USART1SW_PCLK
+#define STM32_USART1CLK             STM32_PCLK
+#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
+#define STM32_USART1CLK             STM32_SYSCLK
+#elif STM32_USART1SW == STM32_USART1SW_LSECLK
+#define STM32_USART1CLK             STM32_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_HSICLK
+#define STM32_USART1CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief   USART2 frequency.
+ */
+#define STM32_USART2CLK             STM32_PCLK
+
+/**
+ * @brief   Timers clock.
+ */
+#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK * 1)
+#define STM32_TIMCLK2               (STM32_PCLK * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK * 2)
+#define STM32_TIMCLK2               (STM32_PCLK * 2)
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000010
+#else
+#define STM32_FLASHBITS             0x00000011
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk
new file mode 100644
index 000000000..3c4d9baf5
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/platform.mk
@@ -0,0 +1,28 @@
+# List of all the STM32F0xx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/stm32_dma.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/adc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/ext_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_dma.c b/os/hal/ports/STM32/STM32F0xx/stm32_dma.c
new file mode 100644
index 000000000..65419feba
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_dma.c
@@ -0,0 +1,291 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F0xx/stm32_dma.c
+ * @brief   DMA helper driver code.
+ *
+ * @addtogroup STM32F0xx_DMA
+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a
+ *          shared resource, this driver allows to allocate and free DMA
+ *          streams at runtime in order to allow all the other device
+ *          drivers to coordinate the access to the resource.
+ * @note    The DMA ISR handlers are all declared into this module because
+ *          sharing, the various device drivers can associate a callback to
+ *          ISRs when allocating streams.
+ * @{
+ */
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA1_STREAMS_MASK     0x0000007F
+
+/**
+ * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA2_STREAMS_MASK     0x00000F80
+
+/**
+ * @brief   Post-reset value of the stream CCR register.
+ */
+#define STM32_DMA_CCR_RESET_VALUE   0x00000000
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ *          identifier and the involved physical registers.
+ * @note    Don't use this array directly, use the appropriate wrapper macros
+ *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
+ */
+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
+  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
+  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_3_IRQn},
+  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel2_3_IRQn},
+  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_5_IRQn},
+  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel4_5_IRQn}
+};
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA ISR redirector type.
+ */
+typedef struct {
+  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
+  void                  *dma_param;     /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
+/**
+ * @brief   Mask of the allocated streams.
+ */
+static uint32_t dma_streams_mask;
+
+/**
+ * @brief   DMA IRQ redirectors.
+ */
+static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA1 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 0;
+  if (dma_isr_redir[0].dma_func)
+    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 streams 2 and 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  /* Check on channel 2.*/
+  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA1->IFCR = flags << 4;
+    if (dma_isr_redir[1].dma_func)
+      dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+  }
+
+  /* Check on channel 3.*/
+  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA1->IFCR = flags << 8;
+    if (dma_isr_redir[2].dma_func)
+      dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+  }
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 streams 4 and 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector6C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  /* Check on channel 4.*/
+  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA1->IFCR = flags << 12;
+    if (dma_isr_redir[3].dma_func)
+      dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+  }
+
+  /* Check on channel 5.*/
+  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA1->IFCR = flags << 16;
+    if (dma_isr_redir[4].dma_func)
+      dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+  }
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+  int i;
+
+  dma_streams_mask = 0;
+  for (i = 0; i < STM32_DMA_STREAMS; i++) {
+    _stm32_dma_streams[i].channel->CCR = 0;
+    dma_isr_redir[i].dma_func = NULL;
+  }
+  DMA1->IFCR = 0xFFFFFFFF;
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ * @pre     The stream must not be already in use or an error is returned.
+ * @post    The stream is allocated and the default ISR handler redirected
+ *          to the specified function.
+ * @post    The stream ISR vector is enabled and its priority configured.
+ * @post    The stream must be freed using @p dmaStreamRelease() before it can
+ *          be reused with another peripheral.
+ * @post    The stream is in its post-reset state.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] priority  IRQ priority mask for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              The operation status.
+ * @retval FALSE        no error, stream taken.
+ * @retval TRUE         error, stream already taken.
+ *
+ * @special
+ */
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                       uint32_t priority,
+                       stm32_dmaisr_t func,
+                       void *param) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Checks if the stream is already taken.*/
+  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
+    return TRUE;
+
+  /* Marks the stream as allocated.*/
+  dma_isr_redir[dmastp->selfindex].dma_func  = func;
+  dma_isr_redir[dmastp->selfindex].dma_param = param;
+  dma_streams_mask |= (1 << dmastp->selfindex);
+
+  /* Enabling DMA clocks required by the current streams set.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
+    rccEnableDMA1(FALSE);
+
+  /* Putting the stream in a safe state.*/
+  dmaStreamDisable(dmastp);
+  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
+
+  /* Enables the associated IRQ vector if a callback is defined.*/
+  if (func != NULL)
+    nvicEnableVector(dmastp->vector, priority);
+
+  return FALSE;
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    The stream is again available.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Check if the streams is not taken.*/
+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+                "not allocated");
+
+  /* Disables the associated IRQ vector.*/
+  nvicDisableVector(dmastp->vector);
+
+  /* Marks the stream as not allocated.*/
+  dma_streams_mask &= ~(1 << dmastp->selfindex);
+
+  /* Shutting down clocks that are no more required, if any.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
+    rccDisableDMA1(FALSE);
+}
+
+#endif /* STM32_DMA_REQUIRED */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_dma.h b/os/hal/ports/STM32/STM32F0xx/stm32_dma.h
new file mode 100644
index 000000000..3acff9647
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_dma.h
@@ -0,0 +1,394 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F0xx/stm32_dma.h
+ * @brief   DMA helper driver header.
+ * @note    This file requires definitions from the ST header file stm32f0xx.h.
+ * @note    This driver uses the new naming convention used for the STM32F2xx
+ *          so the "DMA channels" are referred as "DMA streams".
+ *
+ * @addtogroup STM32F0xx_DMA
+ * @{
+ */
+
+#ifndef _STM32_DMA_H_
+#define _STM32_DMA_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Total number of DMA streams.
+ * @note    This is the total number of streams among all the DMA units.
+ */
+#define STM32_DMA_STREAMS           5
+
+/**
+ * @brief   Mask of the ISR bits passed to the DMA callback functions.
+ */
+#define STM32_DMA_ISR_MASK          0x0F
+
+/**
+ * @brief   Returns the channel associated to the specified stream.
+ *
+ * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
+ * @param[in] c         a stream/channel association word, one channel per
+ *                      nibble, not associated channels must be set to 0xF
+ * @return              Always zero, in this platform there is no dynamic
+ *                      association between streams and channels.
+ */
+#define STM32_DMA_GETCHANNEL(n, c)  0
+
+/**
+ * @brief   Checks if a DMA priority is within the valid range.
+ * @param[in] prio      DMA priority
+ *
+ * @retval              The check result.
+ * @retval FALSE        invalid DMA priority.
+ * @retval TRUE         correct DMA priority.
+ */
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+
+/**
+ * @brief   Returns an unique numeric identifier for a DMA stream.
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              An unique numeric stream identifier.
+ */
+#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1)
+
+/**
+ * @brief   Returns a DMA stream identifier mask.
+ *
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              A DMA stream identifier mask.
+ */
+#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
+  (1 << STM32_DMA_STREAM_ID(dma, stream))
+
+/**
+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.
+ * @param[in] id        the stream numeric identifier
+ * @param[in] mask      the stream numeric identifiers mask
+ *
+ * @retval              The check result.
+ * @retval FALSE        id does not belong to the mask.
+ * @retval TRUE         id belongs to the mask.
+ */
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+
+/**
+ * @name    DMA streams identifiers
+ * @{
+ */
+/**
+ * @brief   Returns a pointer to a stm32_dma_stream_t structure.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @return              A pointer to the stm32_dma_stream_t constant structure
+ *                      associated to the DMA stream.
+ */
+#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
+
+#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
+#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
+#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
+#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
+#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
+/** @} */
+
+/**
+ * @name    CR register constants common to all DMA types
+ * @{
+ */
+#define STM32_DMA_CR_EN             DMA_CCR_EN
+#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE
+#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE
+#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE
+#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
+#define STM32_DMA_CR_DIR_P2M        0
+#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR
+#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM
+#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC
+#define STM32_DMA_CR_PINC           DMA_CCR_PINC
+#define STM32_DMA_CR_MINC           DMA_CCR_MINC
+#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE
+#define STM32_DMA_CR_PSIZE_BYTE     0
+#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0
+#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1
+#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE
+#define STM32_DMA_CR_MSIZE_BYTE     0
+#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
+#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
+                                     STM32_DMA_CR_MSIZE_MASK)
+#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
+#define STM32_DMA_CR_PL(n)          ((n) << 12)
+/** @} */
+
+/**
+ * @name    CR register constants only found in enhanced DMA
+ * @{
+ */
+#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
+/** @} */
+
+/**
+ * @name    Status flags passed to the ISR callbacks
+ * @{
+ */
+#define STM32_DMA_ISR_FEIF          0
+#define STM32_DMA_ISR_DMEIF         0
+#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
+#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
+#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA stream descriptor structure.
+ */
+typedef struct {
+  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
+  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
+  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
+                                             register.                      */
+  uint8_t               selfindex;      /**< @brief Index to self in array. */
+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
+} stm32_dma_stream_t;
+
+/**
+ * @brief   STM32 DMA ISR function type.
+ *
+ * @param[in] p         parameter for the registered function
+ * @param[in] flags     pre-shifted content of the ISR register, the bits
+ *                      are aligned to bit zero
+ */
+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Associates a peripheral data register to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CPAR register
+ *
+ * @special
+ */
+#define dmaStreamSetPeripheral(dmastp, addr) {                              \
+  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Associates a memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CMAR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory0(dmastp, addr) {                                 \
+  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Sets the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] size      value to be written in the CNDTR register
+ *
+ * @special
+ */
+#define dmaStreamSetTransactionSize(dmastp, size) {                         \
+  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
+}
+
+/**
+ * @brief   Returns the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @return              The number of transfers to be performed.
+ *
+ * @special
+ */
+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
+
+/**
+ * @brief   Programs the stream mode settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register
+ *
+ * @special
+ */
+#define dmaStreamSetMode(dmastp, mode) {                                    \
+  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
+}
+
+/**
+ * @brief   DMA stream enable.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamEnable(dmastp) {                                           \
+  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
+}
+
+/**
+ * @brief   DMA stream disable.
+ * @details The function disables the specified stream and then clears any
+ *          pending interrupt.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @note    Interrupts enabling flags are set to zero after this call, see
+ *          bug 3607518.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamDisable(dmastp) {                                          \
+  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
+                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
+  dmaStreamClearInterrupt(dmastp);                                          \
+}
+
+/**
+ * @brief   DMA stream interrupt sources clear.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamClearInterrupt(dmastp) {                                   \
+  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
+}
+
+/**
+ * @brief   Starts a memory to memory operation using the specified stream.
+ * @note    The default transfer data mode is "byte to byte" but it can be
+ *          changed by specifying extra options in the @p mode parameter.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register, this value
+ *                      is implicitly ORed with:
+ *                      - @p STM32_DMA_CR_MINC
+ *                      - @p STM32_DMA_CR_PINC
+ *                      - @p STM32_DMA_CR_DIR_M2M
+ *                      - @p STM32_DMA_CR_EN
+ *                      .
+ * @param[in] src       source address
+ * @param[in] dst       destination address
+ * @param[in] n         number of data units to copy
+ */
+#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
+  dmaStreamSetPeripheral(dmastp, src);                                      \
+  dmaStreamSetMemory0(dmastp, dst);                                         \
+  dmaStreamSetTransactionSize(dmastp, n);                                   \
+  dmaStreamSetMode(dmastp, (mode) |                                         \
+                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
+                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
+}
+
+/**
+ * @brief   Polled wait for DMA transfer end.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ */
+#define dmaWaitCompletion(dmastp) {                                         \
+  while ((dmastp)->channel->CNDTR > 0)                                      \
+    ;                                                                       \
+  dmaStreamDisable(dmastp);                                                 \
+}
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dmaInit(void);
+  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                         uint32_t priority,
+                         stm32_dmaisr_t func,
+                         void *param);
+  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_DMA_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h
index 52421a4d5..52421a4d5 100644
--- a/os/hal/platforms/STM32F0xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h
diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
index 88e47f2c0..88e47f2c0 100644
--- a/os/hal/platforms/STM32F0xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
new file mode 100644
index 000000000..4f738859b
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
@@ -0,0 +1,426 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F0xx/stm32_registry.h
+ * @brief   STM32F0xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    STM32F0xx capabilities
+ * @{
+ */
+#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      FALSE
+#define STM32_HAS_CAN2                      FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC                       TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             28
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            FALSE
+#define STM32_RTC_IS_CALENDAR               TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM14                     TRUE
+#define STM32_TIM14_IS_32BITS               FALSE
+#define STM32_TIM14_CHANNELS                1
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART3                    FALSE
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+
+#elif defined(STM32F0XX_LD)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      FALSE
+#define STM32_HAS_CAN2                      FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC                       FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             28
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     FALSE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_I2C2                      FALSE
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            FALSE
+#define STM32_RTC_IS_CALENDAR               TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      FALSE
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM14                     TRUE
+#define STM32_TIM14_IS_32BITS               FALSE
+#define STM32_TIM14_CHANNELS                1
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM6                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM15                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_USART2                    FALSE
+#define STM32_HAS_USART3                    FALSE
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+
+#else /* STM32F030 */
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      FALSE
+#define STM32_HAS_CAN2                      FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC                       FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             28
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            FALSE
+#define STM32_RTC_IS_CALENDAR               TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM14                     TRUE
+#define STM32_TIM14_IS_32BITS               FALSE
+#define STM32_TIM14_CHANNELS                1
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM2                      FALSE
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART3                    FALSE
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+
+#endif /* STM32F030 */
+
+/** @} */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F1xx/adc_lld.c b/os/hal/ports/STM32/STM32F1xx/adc_lld.c
new file mode 100644
index 000000000..956cdf2de
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/adc_lld.c
@@ -0,0 +1,233 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/adc_lld.c
+ * @brief   STM32F1xx ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared ADC DMA ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+  if ((flags & STM32_DMA_ISR_TEIF) != 0) {
+    /* DMA, this could help only if the DMA tries to access an unmapped
+       address space or violates alignment rules.*/
+    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+  }
+  else {
+    if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+      /* Transfer complete processing.*/
+      _adc_isr_full_code(adcp);
+    }
+    else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+      /* Half transfer processing.*/
+      _adc_isr_half_code(adcp);
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adc = ADC1;
+  ADCD1.dmastp  = STM32_DMA1_STREAM1;
+  ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_TEIE;
+
+  /* Temporary activation.*/
+  rccEnableADC1(FALSE);
+  ADC1->CR1 = 0;
+  ADC1->CR2 = ADC_CR2_ADON;
+
+  /* Reset calibration just to be safe.*/
+  ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+  while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
+    ;
+
+  /* Calibration.*/
+  ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+  while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
+    ;
+
+  /* Return the ADC in low power mode.*/
+  ADC1->CR2 = 0;
+  rccDisableADC1(FALSE);
+#endif
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+  /* If in stopped state then enables the ADC and DMA clocks.*/
+  if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      bool b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC1_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+                            (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+      rccEnableADC1(FALSE);
+    }
+#endif
+
+    /* ADC setup, the calibration procedure has already been performed
+       during initialization.*/
+    adcp->adc->CR1 = 0;
+    adcp->adc->CR2 = 0;
+  }
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+  /* If in ready state then disables the ADC clock.*/
+  if (adcp->state == ADC_READY) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      ADC1->CR1 = 0;
+      ADC1->CR2 = 0;
+      dmaStreamRelease(adcp->dmastp);
+      rccDisableADC1(FALSE);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+  uint32_t mode, cr2;
+  const ADCConversionGroup *grpp = adcp->grpp;
+
+  /* DMA setup.*/
+  mode = adcp->dmamode;
+  if (grpp->circular) {
+    mode |= STM32_DMA_CR_CIRC;
+    if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
+    }
+  }
+  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+                                            (uint32_t)adcp->depth);
+  dmaStreamSetMode(adcp->dmastp, mode);
+  dmaStreamEnable(adcp->dmastp);
+
+  /* ADC setup.*/
+  adcp->adc->CR1   = grpp->cr1 | ADC_CR1_SCAN;
+  cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
+  if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0)
+    cr2 |= ADC_CR2_CONT;
+  adcp->adc->CR2   = grpp->cr2 | cr2;
+  adcp->adc->SMPR1 = grpp->smpr1;
+  adcp->adc->SMPR2 = grpp->smpr2;
+  adcp->adc->SQR1  = grpp->sqr1;
+  adcp->adc->SQR2  = grpp->sqr2;
+  adcp->adc->SQR3  = grpp->sqr3;
+
+  /* ADC start by writing ADC_CR2_ADON a second time.*/
+  adcp->adc->CR2   = cr2;
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+  dmaStreamDisable(adcp->dmastp);
+  adcp->adc->CR2 = 0;
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F1xx/adc_lld.h b/os/hal/ports/STM32/STM32F1xx/adc_lld.h
new file mode 100644
index 000000000..cb94b9571
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/adc_lld.h
@@ -0,0 +1,389 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/adc_lld.h
+ * @brief   STM32F1xx ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Triggers selection
+ * @{
+ */
+#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 17) /**< @brief Trigger source.     */
+#define ADC_CR2_EXTSEL_SWSTART  (7 << 17)   /**< @brief Software trigger.   */
+/** @} */
+
+/**
+ * @name    Available analog channels
+ * @{
+ */
+#define ADC_CHANNEL_IN0         0   /**< @brief External analog input 0.    */
+#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
+#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
+#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
+#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
+#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
+#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
+#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
+#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
+#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
+#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
+#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
+#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
+#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
+#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
+#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
+#define ADC_CHANNEL_SENSOR      16  /**< @brief Internal temperature sensor.*/
+#define ADC_CHANNEL_VREFINT     17  /**< @brief Internal reference.         */
+/** @} */
+
+/**
+ * @name    Sampling rates
+ * @{
+ */
+#define ADC_SAMPLE_1P5          0   /**< @brief 1.5 cycles sampling time.   */
+#define ADC_SAMPLE_7P5          1   /**< @brief 7.5 cycles sampling time.   */
+#define ADC_SAMPLE_13P5         2   /**< @brief 13.5 cycles sampling time.  */
+#define ADC_SAMPLE_28P5         3   /**< @brief 28.5 cycles sampling time.  */
+#define ADC_SAMPLE_41P5         4   /**< @brief 41.5 cycles sampling time.  */
+#define ADC_SAMPLE_55P5         5   /**< @brief 55.5 cycles sampling time.  */
+#define ADC_SAMPLE_71P5         6   /**< @brief 71.5 cycles sampling time.  */
+#define ADC_SAMPLE_239P5        7   /**< @brief 239.5 cycles sampling time. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1                  FALSE
+#endif
+
+/**
+ * @brief   ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   ADC1 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_IRQ_PRIORITY         5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief   Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief   Possible ADC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  ADC_ERR_DMAFAILURE = 0                    /**< DMA operations failure.    */
+} adcerror_t;
+
+/**
+ * @brief   Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief   ADC notification callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] buffer    pointer to the most recent samples data
+ * @param[in] n         number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief   ADC error callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] err       ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief   Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ *          operation.
+ * @note    The use of this configuration structure requires knowledge of
+ *          STM32 ADC cell registers interface, please refer to the STM32
+ *          reference manual for details.
+ */
+typedef struct {
+  /**
+   * @brief   Enables the circular buffer mode for the group.
+   */
+  bool                      circular;
+  /**
+   * @brief   Number of the analog channels belonging to the conversion group.
+   */
+  adc_channels_num_t        num_channels;
+  /**
+   * @brief   Callback function associated to the group or @p NULL.
+   */
+  adccallback_t             end_cb;
+  /**
+   * @brief   Error callback or @p NULL.
+   */
+  adcerrorcallback_t        error_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   ADC CR1 register initialization data.
+   * @note    All the required bits must be defined into this field except
+   *          @p ADC_CR1_SCAN that is enforced inside the driver.
+   */
+  uint32_t                  cr1;
+  /**
+   * @brief   ADC CR2 register initialization data.
+   * @note    All the required bits must be defined into this field except
+   *          @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
+   *          enforced inside the driver.
+   */
+  uint32_t                  cr2;
+  /**
+   * @brief   ADC SMPR1 register initialization data.
+   * @details In this field must be specified the sample times for channels
+   *          10...17.
+   */
+  uint32_t                  smpr1;
+  /**
+   * @brief   ADC SMPR2 register initialization data.
+   * @details In this field must be specified the sample times for channels
+   *          0...9.
+   */
+  uint32_t                  smpr2;
+  /**
+   * @brief   ADC SQR1 register initialization data.
+   * @details Conversion group sequence 13...16 + sequence length.
+   */
+  uint32_t                  sqr1;
+  /**
+   * @brief   ADC SQR2 register initialization data.
+   * @details Conversion group sequence 7...12.
+   */
+  uint32_t                  sqr2;
+  /**
+   * @brief   ADC SQR3 register initialization data.
+   * @details Conversion group sequence 1...6.
+   */
+  uint32_t                  sqr3;
+} ADCConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  uint32_t                  dummy;
+} ADCConfig;
+
+/**
+ * @brief   Structure representing an ADC driver.
+ */
+struct ADCDriver {
+  /**
+   * @brief Driver state.
+   */
+  adcstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const ADCConfig           *config;
+  /**
+   * @brief Current samples buffer pointer or @p NULL.
+   */
+  adcsample_t               *samples;
+  /**
+   * @brief Current samples buffer depth or @p 0.
+   */
+  size_t                    depth;
+  /**
+   * @brief Current conversion group pointer or @p NULL.
+   */
+  const ADCConversionGroup  *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+  ADC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the ADCx registers block.
+   */
+  ADC_TypeDef               *adc;
+  /**
+   * @brief Pointer to associated DMA channel.
+   */
+  const stm32_dma_stream_t  *dmastp;
+  /**
+   * @brief DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Sequences building helper macros
+ * @{
+ */
+/**
+ * @brief   Number of channels in a conversion sequence.
+ */
+#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
+
+#define ADC_SQR3_SQ1_N(n)       ((n) << 0)  /**< @brief 1st channel in seq. */
+#define ADC_SQR3_SQ2_N(n)       ((n) << 5)  /**< @brief 2nd channel in seq. */
+#define ADC_SQR3_SQ3_N(n)       ((n) << 10) /**< @brief 3rd channel in seq. */
+#define ADC_SQR3_SQ4_N(n)       ((n) << 15) /**< @brief 4th channel in seq. */
+#define ADC_SQR3_SQ5_N(n)       ((n) << 20) /**< @brief 5th channel in seq. */
+#define ADC_SQR3_SQ6_N(n)       ((n) << 25) /**< @brief 6th channel in seq. */
+
+#define ADC_SQR2_SQ7_N(n)       ((n) << 0)  /**< @brief 7th channel in seq. */
+#define ADC_SQR2_SQ8_N(n)       ((n) << 5)  /**< @brief 8th channel in seq. */
+#define ADC_SQR2_SQ9_N(n)       ((n) << 10) /**< @brief 9th channel in seq. */
+#define ADC_SQR2_SQ10_N(n)      ((n) << 15) /**< @brief 10th channel in seq.*/
+#define ADC_SQR2_SQ11_N(n)      ((n) << 20) /**< @brief 11th channel in seq.*/
+#define ADC_SQR2_SQ12_N(n)      ((n) << 25) /**< @brief 12th channel in seq.*/
+
+#define ADC_SQR1_SQ13_N(n)      ((n) << 0)  /**< @brief 13th channel in seq.*/
+#define ADC_SQR1_SQ14_N(n)      ((n) << 5)  /**< @brief 14th channel in seq.*/
+#define ADC_SQR1_SQ15_N(n)      ((n) << 10) /**< @brief 15th channel in seq.*/
+#define ADC_SQR1_SQ16_N(n)      ((n) << 15) /**< @brief 16th channel in seq.*/
+/** @} */
+
+/**
+ * @name    Sampling rate settings helper macros
+ * @{
+ */
+#define ADC_SMPR2_SMP_AN0(n)    ((n) << 0)  /**< @brief AN0 sampling time.  */
+#define ADC_SMPR2_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
+#define ADC_SMPR2_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
+#define ADC_SMPR2_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
+#define ADC_SMPR2_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
+#define ADC_SMPR2_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
+#define ADC_SMPR2_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
+#define ADC_SMPR2_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
+#define ADC_SMPR2_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
+#define ADC_SMPR2_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
+
+#define ADC_SMPR1_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
+#define ADC_SMPR1_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
+#define ADC_SMPR1_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
+#define ADC_SMPR1_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
+#define ADC_SMPR1_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
+#define ADC_SMPR1_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
+#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
+                                                 sampling time.             */
+#define ADC_SMPR1_SMP_VREF(n)   ((n) << 21) /**< @brief Voltage Reference
+                                                 sampling time.             */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adc_lld_init(void);
+  void adc_lld_start(ADCDriver *adcp);
+  void adc_lld_stop(ADCDriver *adcp);
+  void adc_lld_start_conversion(ADCDriver *adcp);
+  void adc_lld_stop_conversion(ADCDriver *adcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c
new file mode 100644
index 000000000..92d770b76
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c
@@ -0,0 +1,325 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/ext_lld_isr.c
+ * @brief   STM32F1xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(EXTI0_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 0);
+  EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(EXTI1_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 1);
+  EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(EXTI2_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 2);
+  EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(EXTI3_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 3);
+  EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(EXTI4_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 4);
+  EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(EXTI9_5_IRQHandler) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
+  EXTI->PR = pr;
+  if (pr & (1 << 5))
+    EXTD1.config->channels[5].cb(&EXTD1, 5);
+  if (pr & (1 << 6))
+    EXTD1.config->channels[6].cb(&EXTD1, 6);
+  if (pr & (1 << 7))
+    EXTD1.config->channels[7].cb(&EXTD1, 7);
+  if (pr & (1 << 8))
+    EXTD1.config->channels[8].cb(&EXTD1, 8);
+  if (pr & (1 << 9))
+    EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(EXTI15_10_IRQHandler) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
+                   (1 << 15));
+  EXTI->PR = pr;
+  if (pr & (1 << 10))
+    EXTD1.config->channels[10].cb(&EXTD1, 10);
+  if (pr & (1 << 11))
+    EXTD1.config->channels[11].cb(&EXTD1, 11);
+  if (pr & (1 << 12))
+    EXTD1.config->channels[12].cb(&EXTD1, 12);
+  if (pr & (1 << 13))
+    EXTD1.config->channels[13].cb(&EXTD1, 13);
+  if (pr & (1 << 14))
+    EXTD1.config->channels[14].cb(&EXTD1, 14);
+  if (pr & (1 << 15))
+    EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(PVD_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 16);
+  EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[17] interrupt handler (RTC).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 17);
+  EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if defined(STM32F10X_CL)
+/**
+ * @brief   EXTI[18] interrupt handler (OTG_FS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 18);
+  EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[19] interrupt handler (ETH_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 19);
+  EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
+      defined(STM32F10X_HD_VL)
+
+#else /* Other STM32F1xx devices.*/
+/**
+ * @brief   EXTI[18] interrupt handler (USB_FS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 18);
+  EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+  nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+  nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+  nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+  nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+  nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+  nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+  nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+  nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+  nvicEnableVector(RTCAlarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+#if defined(STM32F10X_CL)
+  /* EXTI vectors specific to STM32F1xx Connectivity Line.*/
+  nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+  nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
+      defined(STM32F10X_HD_VL)
+  /* EXTI vectors specific to STM32F1xx Value Line.*/
+#else
+  /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
+  nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief   Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+  nvicDisableVector(EXTI0_IRQn);
+  nvicDisableVector(EXTI1_IRQn);
+  nvicDisableVector(EXTI2_IRQn);
+  nvicDisableVector(EXTI3_IRQn);
+  nvicDisableVector(EXTI4_IRQn);
+  nvicDisableVector(EXTI9_5_IRQn);
+  nvicDisableVector(EXTI15_10_IRQn);
+  nvicDisableVector(PVD_IRQn);
+  nvicDisableVector(RTCAlarm_IRQn);
+#if defined(STM32F10X_CL)
+  /* EXTI vectors specific to STM32F1xx Connectivity Line.*/
+  nvicDisableVector(OTG_FS_WKUP_IRQn);
+  nvicDisableVector(ETH_WKUP_IRQn);
+#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||               \
+    defined(STM32F10X_HD_VL)
+  /* EXTI vectors specific to STM32F1xx Value Line.*/
+#else
+  /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
+  nvicDisableVector(USBWakeUp_IRQn);
+#endif
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F1xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.h
index 1114acf49..1114acf49 100644
--- a/os/hal/platforms/STM32F1xx/ext_lld_isr.h
+++ b/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.h
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_lld.c
new file mode 100644
index 000000000..301f26fb9
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.c
@@ -0,0 +1,290 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/hal_lld.c
+ * @brief   STM32F1xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the backup domain.
+ * @note    WARNING! Changing clock source impossible without resetting
+ *          of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+  /* Backup domain access enabled and left open.*/
+  PWR->CR |= PWR_CR_DBP;
+
+#if HAL_USE_RTC
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0;
+  }
+
+  /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+  RCC->BDCR |= RCC_BDCR_LSEON;
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                     /* Waits until LSE is stable.   */
+#endif /* STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+    /* Selects clock source.*/
+    RCC->BDCR |= STM32_RTCSEL;
+
+    /* Prescaler value loaded in registers.*/
+    rtc_lld_set_prescaler();
+
+    /* RTC clock enabled.*/
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+#endif /* HAL_USE_RTC */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+  /* Reset of all peripherals.*/
+  rccResetAPB1(0xFFFFFFFF);
+  rccResetAPB2(0xFFFFFFFF);
+
+  /* PWR and BD clocks enabled.*/
+  rccEnablePWRInterface(FALSE);
+  rccEnableBKPInterface(FALSE);
+
+  /* Initializes the backup domain.*/
+  hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+  dmaInit();
+#endif
+
+  /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief   STM32 clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) ||                    \
+    defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) ||                    \
+    defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                       \
+    defined(__DOXYGEN__)
+/*
+ * Clocks initialization for all sub-families except CL.
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* HSI setup, it enforces the reset situation in order to handle possible
+     problems with JTAG probes and re-initializations.*/
+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;                                       /* Wait until HSI is stable.    */
+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
+  RCC->CFGR = 0;                            /* CFGR reset value.            */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;                                       /* Waits until HSI is selected. */
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEBYP;
+#endif
+  /* HSE activation.*/
+  RCC->CR |= RCC_CR_HSEON;
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;                                       /* Waits until HSE is stable.   */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                                       /* Waits until LSI is stable.   */
+#endif
+
+#if STM32_ACTIVATE_PLL
+  /* PLL activation.*/
+  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                                       /* Waits until PLL is stable.   */
+#endif
+
+  /* Clock settings.*/
+#if STM32_HAS_USB
+  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE |
+              STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2  | STM32_PPRE1    |
+              STM32_HPRE;
+#else
+  RCC->CFGR = STM32_MCOSEL |                STM32_PLLMUL | STM32_PLLXTPRE |
+              STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2  | STM32_PPRE1    |
+              STM32_HPRE;
+#endif
+
+  /* Flash setup and final clock selection.   */
+  FLASH->ACR = STM32_FLASHBITS;
+
+  /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+  /* Switches clock source.*/
+  RCC->CFGR |= STM32_SW;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;                                       /* Waits selection complete.    */
+#endif
+
+#if !STM32_HSI_ENABLED
+  RCC->CR &= ~RCC_CR_HSION;
+#endif
+#endif /* !STM32_NO_INIT */
+}
+
+#elif defined(STM32F10X_CL)
+/*
+ * Clocks initialization for the CL sub-family.
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* HSI setup.*/
+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;                                       /* Wait until HSI is stable.    */
+  RCC->CFGR = 0;
+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;                                       /* Wait until HSI is the source.*/
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEBYP;
+#endif
+  /* HSE activation.*/
+  RCC->CR |= RCC_CR_HSEON;
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;                                       /* Waits until HSE is stable.   */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                                       /* Waits until LSI is stable.   */
+#endif
+
+  /* Settings of various dividers and multipliers in CFGR2.*/
+  RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
+               STM32_PREDIV1 | STM32_PREDIV1SRC;
+
+  /* PLL2 setup, if activated.*/
+#if STM32_ACTIVATE_PLL2
+  RCC->CR |= RCC_CR_PLL2ON;
+  while (!(RCC->CR & RCC_CR_PLL2RDY))
+    ;                                        /* Waits until PLL2 is stable. */
+#endif
+
+  /* PLL3 setup, if activated.*/
+#if STM32_ACTIVATE_PLL3
+  RCC->CR |= RCC_CR_PLL3ON;
+  while (!(RCC->CR & RCC_CR_PLL3RDY))
+    ;                                        /* Waits until PLL3 is stable. */
+#endif
+
+  /* PLL1 setup, if activated.*/
+#if STM32_ACTIVATE_PLL1
+  RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                           /* Waits until PLL1 is stable.              */
+#endif
+
+  /* Clock settings.*/
+#if STM32_HAS_OTG1
+  RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC |
+              STM32_ADCPRE | STM32_PPRE2    | STM32_PPRE1  | STM32_HPRE;
+#else
+  RCC->CFGR = STM32_MCO    |                  STM32_PLLMUL | STM32_PLLSRC |
+              STM32_ADCPRE | STM32_PPRE2    | STM32_PPRE1  | STM32_HPRE;
+#endif
+
+  /* Flash setup and final clock selection.   */
+  FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock.    */
+
+  /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;
+#endif
+
+#if !STM32_HSI_ENABLED
+  RCC->CR &= ~RCC_CR_HSION;
+#endif
+#endif /* !STM32_NO_INIT */
+}
+#else
+void stm32_clock_init(void) {}
+#endif
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.h b/os/hal/ports/STM32/STM32F1xx/hal_lld.h
new file mode 100644
index 000000000..7498ea48c
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.h
@@ -0,0 +1,217 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/hal_lld.h
+ * @brief   STM32F1xx HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - STM32_LSECLK.
+ *          - STM32_HSECLK.
+ *          - STM32_HSE_BYPASS (optionally).
+ *          .
+ *          One of the following macros must also be defined:
+ *          - STM32F10X_LD_VL for Value Line Low Density devices.
+ *          - STM32F10X_MD_VL for Value Line Medium Density devices.
+ *          - STM32F10X_HD_VL for Value Line High Density devices.
+ *          - STM32F10X_LD for Performance Low Density devices.
+ *          - STM32F10X_MD for Performance Medium Density devices.
+ *          - STM32F10X_HD for Performance High Density devices.
+ *          - STM32F10X_XL for Performance eXtra Density devices.
+ *          - STM32F10X_CL for Connectivity Line devices.
+ *          .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+#if defined(__DOXYGEN__)
+#define PLATFORM_NAME           "STM32F1xx"
+
+#elif defined(STM32F10X_LD_VL)
+#define PLATFORM_NAME           "STM32F100 Value Line Low Density"
+
+#elif defined(STM32F10X_MD_VL)
+#define PLATFORM_NAME           "STM32F100 Value Line Medium Density"
+
+#elif defined(STM32F10X_HD_VL)
+#define PLATFORM_NAME           "STM32F100 Value Line High Density"
+
+#elif defined(STM32F10X_LD)
+#define PLATFORM_NAME           "STM32F10x Performance Line Low Density"
+
+#elif defined(STM32F10X_MD)
+#define PLATFORM_NAME           "STM32F10x Performance Line Medium Density"
+
+#elif defined(STM32F10X_HD)
+#define PLATFORM_NAME           "STM32F10x Performance Line High Density"
+
+#elif defined(STM32F10X_XL)
+#define PLATFORM_NAME           "STM32F10x Performance Line eXtra Density"
+
+#elif defined(STM32F10X_CL)
+#define PLATFORM_NAME           "STM32F10x Connectivity Line"
+
+#else
+#error "unsupported or unrecognized STM32F1xx member"
+#endif
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK            8000000     /**< High speed internal clock. */
+#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
+/** @} */
+
+/**
+ * @name    PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
+/** @} */
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT               FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE            FALSE
+#endif
+
+/**
+ * @brief   Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                   STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief   Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED           FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED           FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) ||                 \
+    defined(STM32F10X_HD_VL) || defined(__DOXYGEN__)
+#include "hal_lld_f100.h"
+
+#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) ||                     \
+      defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                     \
+      defined(__DOXYGEN__)
+#include "hal_lld_f103.h"
+
+#elif defined(STM32F10X_CL) || defined(__DOXYGEN__)
+#include "hal_lld_f105_f107.h"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h b/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h
new file mode 100644
index 000000000..232d479c5
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h
@@ -0,0 +1,574 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @defgroup STM32F100_HAL STM32F100 HAL Support
+ * @details HAL support for STM32 Value Line LD, MD and HD sub-families.
+ *
+ * @ingroup HAL
+ */
+
+/**
+ * @file    STM32F1xx/hal_lld_f100.h
+ * @brief   STM32F100 Value Line HAL subsystem low level driver header.
+ *
+ * @addtogroup STM32F100_HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_F100_H_
+#define _HAL_LLD_F100_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX        24000000
+
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        24000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        1000000
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        1000000
+
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX         24000000
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN         1000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX        24000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN        16000000
+
+/**
+ * @brief   Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX         24000000
+
+/**
+ * @brief   Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX         24000000
+
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX        12000000
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
+#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
+#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
+#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
+#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
+
+#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
+
+#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PPRE2 divided by 2.        */
+#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PPRE2 divided by 4.        */
+#define STM32_ADCPRE_DIV6       (2 << 14)   /**< PPRE2 divided by 6.        */
+#define STM32_ADCPRE_DIV8       (3 << 14)   /**< PPRE2 divided by 8.        */
+
+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
+#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
+
+#define STM32_PLLXTPRE_DIV1     (0 << 17)   /**< HSE divided by 1.          */
+#define STM32_PLLXTPRE_DIV2     (1 << 17)   /**< HSE divided by 2.          */
+
+#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
+/** @} */
+
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
+#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
+#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
+#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
+#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 128 used as
+                                                 RTC clock.                 */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                    STM32_SW_PLL
+#endif
+
+/**
+ * @brief   Clock source for the PLL.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief   Crystal PLL pre-divider.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
+#define STM32_PLLXTPRE              STM32_PLLXTPRE_DIV1
+#endif
+
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed range is 2...16.
+ * @note    The default value is calculated for a 24MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE          3
+#endif
+
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 24MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                  STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1                 STM32_PPRE1_DIV1
+#endif
+
+/**
+ * @brief   APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2                 STM32_PPRE2_DIV1
+#endif
+
+/**
+ * @brief   ADC prescaler value.
+ */
+#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADCPRE                STM32_ADCPRE_DIV2
+#endif
+
+/**
+ * @brief   MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                   STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                   STM32_RTCSEL_LSI
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F100_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F100_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                         \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSELSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+
+/* HSE prescaler setting check.*/
+#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) &&                              \
+    (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
+#error "invalid STM32_PLLXTPRE value specified"
+#endif
+
+/**
+ * @brief   PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
+#define STM32_PLLCLKIN              (STM32_HSECLK / 1)
+#else
+#define STM32_PLLCLKIN              (STM32_HSECLK / 2)
+#endif
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                (STM32_HSECLK / 128)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK                0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief   ADC frequency.
+ */
+#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_ADCCLK                (STM32_PCLK2 / 2)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
+#define STM32_ADCCLK                (STM32_PCLK2 / 4)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
+#define STM32_ADCCLK                (STM32_PCLK2 / 6)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
+#define STM32_ADCCLK                (STM32_PCLK2 / 8)
+#else
+#error "invalid STM32_ADCPRE value specified"
+#endif
+
+/* ADC frequency check.*/
+#if STM32_ADCCLK > STM32_ADCCLK_MAX
+#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/**
+ * @brief   Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief   Timers 1, 8, 9, 10, 11 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS             0x00000011
+#else
+#define STM32_FLASHBITS             0x00000012
+#endif
+
+#endif /* _HAL_LLD_F100_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h b/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h
new file mode 100644
index 000000000..280d9e5fb
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h
@@ -0,0 +1,604 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @defgroup STM32F103_HAL STM32F103 HAL Support
+ * @details HAL support for STM32 Performance Line LD, MD and HD sub-families.
+ *
+ * @ingroup HAL
+ */
+
+/**
+ * @file    STM32F1xx/hal_lld_f103.h
+ * @brief   STM32F103 Performance Line HAL subsystem low level driver header.
+ *
+ * @addtogroup STM32F103_HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_F103_H_
+#define _HAL_LLD_F103_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX        72000000
+
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        25000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        1000000
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        1000000
+
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX         25000000
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN         1000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX        72000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN        16000000
+
+/**
+ * @brief   Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX         36000000
+
+/**
+ * @brief   Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX         72000000
+
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX        14000000
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
+#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
+#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
+#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
+#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
+
+#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
+
+#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PPRE2 divided by 2.        */
+#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PPRE2 divided by 4.        */
+#define STM32_ADCPRE_DIV6       (2 << 14)   /**< PPRE2 divided by 6.        */
+#define STM32_ADCPRE_DIV8       (3 << 14)   /**< PPRE2 divided by 8.        */
+
+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
+#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
+
+#define STM32_PLLXTPRE_DIV1     (0 << 17)   /**< HSE divided by 1.          */
+#define STM32_PLLXTPRE_DIV2     (1 << 17)   /**< HSE divided by 2.          */
+
+#define STM32_USBPRE_DIV1P5     (0 << 22)   /**< PLLOUT divided by 1.5.     */
+#define STM32_USBPRE_DIV1       (1 << 22)   /**< PLLOUT divided by 1.       */
+
+#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
+/** @} */
+
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
+#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
+#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
+#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
+#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 128 used as
+                                                 RTC clock.                 */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                    STM32_SW_PLL
+#endif
+
+/**
+ * @brief   Clock source for the PLL.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief   Crystal PLL pre-divider.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
+#define STM32_PLLXTPRE              STM32_PLLXTPRE_DIV1
+#endif
+
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed range is 2...16.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE          9
+#endif
+
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                  STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1                 STM32_PPRE1_DIV2
+#endif
+
+/**
+ * @brief   APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2                 STM32_PPRE2_DIV2
+#endif
+
+/**
+ * @brief   ADC prescaler value.
+ */
+#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADCPRE                STM32_ADCPRE_DIV4
+#endif
+
+/**
+ * @brief   USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_REQUIRED    TRUE
+#endif
+
+/**
+ * @brief   USB prescaler initialization.
+ */
+#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
+#define STM32_USBPRE                STM32_USBPRE_DIV1P5
+#endif
+
+/**
+ * @brief   MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                STM32_RTCSEL_LSI
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F103_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F103_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if STM32_USB_CLOCK_REQUIRED ||                                             \
+    (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+
+/* HSE prescaler setting check.*/
+#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) &&                              \
+    (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
+#error "invalid STM32_PLLXTPRE value specified"
+#endif
+
+/**
+ * @brief   PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
+#define STM32_PLLCLKIN              (STM32_HSECLK / 1)
+#else
+#define STM32_PLLCLKIN              (STM32_HSECLK / 2)
+#endif
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                (STM32_HSECLK / 128)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK                0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief   ADC frequency.
+ */
+#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_ADCCLK                (STM32_PCLK2 / 2)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
+#define STM32_ADCCLK                (STM32_PCLK2 / 4)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
+#define STM32_ADCCLK                (STM32_PCLK2 / 6)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
+#define STM32_ADCCLK                (STM32_PCLK2 / 8)
+#else
+#error "invalid STM32_ADCPRE value specified"
+#endif
+
+/* ADC frequency check.*/
+#if STM32_ADCCLK > STM32_ADCCLK_MAX
+#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/**
+ * @brief   USB frequency.
+ */
+#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
+#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
+#define STM32_USBCLK                STM32_PLLCLKOUT
+#else
+#error "invalid STM32_USBPRE value specified"
+#endif
+
+/**
+ * @brief   Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief   Timers 1, 8, 9, 10, 11 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS             0x00000011
+#else
+#define STM32_FLASHBITS             0x00000012
+#endif
+
+#endif /* _HAL_LLD_F103_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h b/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h
new file mode 100644
index 000000000..0bed30a05
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h
@@ -0,0 +1,814 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @defgroup STM32F10X_CL_HAL STM32F105/F107 HAL Support
+ * @details HAL support for STM32 Connectivity Line sub-family.
+ *
+ * @ingroup HAL
+ */
+
+/**
+ * @file    STM32F1xx/hal_lld_f105_f107.h
+ * @brief   STM32F10x Connectivity Line HAL subsystem low level driver header.
+ *
+ * @addtogroup STM32F10X_CL_HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_F105_F107_H_
+#define _HAL_LLD_F105_F107_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX        72000000
+
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        50000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        1000000
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        1000000
+
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLL1IN_MAX        12000000
+
+/**
+ * @brief   Maximum PLL1 input clock frequency.
+ */
+#define STM32_PLL1IN_MIN        3000000
+
+/**
+ * @brief   Maximum PLL1 input clock frequency.
+ */
+#define STM32_PLL23IN_MAX       5000000
+
+/**
+ * @brief   Maximum PLL2 and PLL3 input clock frequency.
+ */
+#define STM32_PLL23IN_MIN       3000000
+
+/**
+ * @brief   Maximum PLL1 VCO clock frequency.
+ */
+#define STM32_PLL1VCO_MAX       144000000
+
+/**
+ * @brief   Maximum PLL1 VCO clock frequency.
+ */
+#define STM32_PLL1VCO_MIN       36000000
+
+/**
+ * @brief   Maximum PLL2 and PLL3 VCO clock frequency.
+ */
+#define STM32_PLL23VCO_MAX      148000000
+
+/**
+ * @brief   Maximum PLL2 and PLL3 VCO clock frequency.
+ */
+#define STM32_PLL23VCO_MIN      80000000
+
+/**
+ * @brief   Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX         36000000
+
+/**
+ * @brief   Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX         72000000
+
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX        14000000
+
+/**
+ * @brief   Maximum SPI/I2S clock frequency.
+ */
+#define STM32_SPII2S_MAX        18000000
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
+#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
+#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
+#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
+#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
+
+#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
+
+#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PPRE2 divided by 2.        */
+#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PPRE2 divided by 4.        */
+#define STM32_ADCPRE_DIV6       (2 << 14)   /**< PPRE2 divided by 6.        */
+#define STM32_ADCPRE_DIV8       (3 << 14)   /**< PPRE2 divided by 8.        */
+
+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
+#define STM32_PLLSRC_PREDIV1    (1 << 16)   /**< PLL clock source is
+                                                 PREDIV1.                   */
+
+#define STM32_OTGFSPRE_DIV2     (1 << 22)   /**< HCLK*2 divided by 2.       */
+#define STM32_OTGFSPRE_DIV3     (0 << 22)   /**< HCLK*2 divided by 3.       */
+
+#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
+#define STM32_MCOSEL_PLL2       (8 << 24)   /**< PLL2 clock on MCO pin.     */
+#define STM32_MCOSEL_PLL3DIV2   (9 << 24)   /**< PLL3/2 clock on MCO pin.   */
+#define STM32_MCOSEL_XT1        (10 << 24)  /**< XT1 clock on MCO pin.      */
+#define STM32_MCOSEL_PLL3       (11 << 24)  /**< PLL3 clock on MCO pin.     */
+/** @} */
+
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
+#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
+#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
+#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
+#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 128 used as
+                                                 RTC clock.                 */
+/** @} */
+
+/**
+ * @name    RCC_CFGR2 register bits definitions
+ * @{
+ */
+#define STM32_PREDIV1SRC_HSE    (0 << 16)   /**< PREDIV1 source is HSE.     */
+#define STM32_PREDIV1SRC_PLL2   (1 << 16)   /**< PREDIV1 source is PLL2.    */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Main clock source selection.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 25MHz crystal using both PLL and PLL2.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                    STM32_SW_PLL
+#endif
+
+/**
+ * @brief   Clock source for the PLL.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 25MHz crystal using both PLL and PLL2.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                STM32_PLLSRC_PREDIV1
+#endif
+
+/**
+ * @brief   PREDIV1 clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 25MHz crystal using both PLL and PLL2.
+ */
+#if !defined(STM32_PREDIV1SRC) || defined(__DOXYGEN__)
+#define STM32_PREDIV1SRC            STM32_PREDIV1SRC_HSE
+#endif
+
+/**
+ * @brief   PREDIV1 division factor.
+ * @note    The allowed range is 1...16.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 25MHz crystal using both PLL and PLL2.
+ */
+#if !defined(STM32_PREDIV1_VALUE) || defined(__DOXYGEN__)
+#define STM32_PREDIV1_VALUE         5
+#endif
+
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed range is 4...9.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 25MHz crystal using both PLL and PLL2.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE          9
+#endif
+
+/**
+ * @brief   PREDIV2 division factor.
+ * @note    The allowed range is 1...16.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 25MHz crystal using both PLL and PLL2.
+ */
+#if !defined(STM32_PREDIV2_VALUE) || defined(__DOXYGEN__)
+#define STM32_PREDIV2_VALUE         5
+#endif
+
+/**
+ * @brief   PLL2 multiplier value.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 25MHz crystal using both PLL and PLL2.
+ */
+#if !defined(STM32_PLL2MUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLL2MUL_VALUE         8
+#endif
+
+/**
+ * @brief   PLL3 multiplier value.
+ * @note    The default value is calculated for a 50MHz clock from
+ *          a 25MHz crystal.
+ */
+#if !defined(STM32_PLL3MUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLL3MUL_VALUE         10
+#endif
+
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 25MHz crystal using both PLL and PLL2.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                  STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1                 STM32_PPRE1_DIV2
+#endif
+
+/**
+ * @brief   APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2                 STM32_PPRE2_DIV2
+#endif
+
+/**
+ * @brief   ADC prescaler value.
+ */
+#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADCPRE                STM32_ADCPRE_DIV4
+#endif
+
+/**
+ * @brief   USB clock setting.
+ */
+#if !defined(STM32_OTG_CLOCK_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_OTG_CLOCK_REQUIRED    TRUE
+#endif
+
+/**
+ * @brief   OTG prescaler initialization.
+ */
+#if !defined(STM32_OTGFSPRE) || defined(__DOXYGEN__)
+#define STM32_OTGFSPRE              STM32_OTGFSPRE_DIV3
+#endif
+
+/**
+ * @brief   Dedicated I2S clock setting.
+ */
+#if !defined(STM32_I2S_CLOCK_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_I2S_CLOCK_REQUIRED    FALSE
+#endif
+
+/**
+ * @brief   MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                   STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                   STM32_RTCSEL_HSEDIV
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F107_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F107_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE)) ||                                 \
+    (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) ||                              \
+    (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) ||                              \
+    (STM32_MCOSEL == STM32_MCOSEL_XT1)
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL1 activation conditions.*/
+#if STM32_OTG_CLOCK_REQUIRED ||                                             \
+    (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL1 activation flag.
+ */
+#define STM32_ACTIVATE_PLL1         TRUE
+#else
+#define STM32_ACTIVATE_PLL1         FALSE
+#endif
+
+/* PLL2 activation conditions.*/
+#if ((STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) && STM32_ACTIVATE_PLL1) || \
+    (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) ||                              \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL2 activation flag.
+ */
+#define STM32_ACTIVATE_PLL2         TRUE
+#else
+#define STM32_ACTIVATE_PLL2         FALSE
+#endif
+
+/* PLL3 activation conditions.*/
+#if STM32_I2S_CLOCK_REQUIRED ||                                             \
+    (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) ||                              \
+    (STM32_MCOSEL == STM32_MCOSEL_PLL3) ||                                  \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL3 activation flag.
+ */
+#define STM32_ACTIVATE_PLL3         TRUE
+#else
+#define STM32_ACTIVATE_PLL3         FALSE
+#endif
+
+/**
+ * @brief   PREDIV1 field.
+ */
+#if (STM32_PREDIV1_VALUE >= 1) && (STM32_PREDIV1_VALUE <= 16) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PREDIV1               ((STM32_PREDIV1_VALUE - 1) << 0)
+#else
+#error "invalid STM32_PREDIV1_VALUE value specified"
+#endif
+
+/**
+ * @brief   PREDIV2 field.
+ */
+#if (STM32_PREDIV2_VALUE >= 1) && (STM32_PREDIV2_VALUE <= 16) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PREDIV2               ((STM32_PREDIV2_VALUE - 1) << 4)
+#else
+#error "invalid STM32_PREDIV2_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 4) && (STM32_PLLMUL_VALUE <= 9)) ||             \
+    defined(__DOXYGEN__)
+#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL2MUL field.
+ */
+#if ((STM32_PLL2MUL_VALUE >= 8) && (STM32_PLL2MUL_VALUE <= 14)) ||          \
+    defined(__DOXYGEN__)
+#define STM32_PLL2MUL               ((STM32_PLL2MUL_VALUE - 2) << 8)
+#elif (STM32_PLL2MUL_VALUE == 16)
+#define STM32_PLL2MUL               (14 << 8)
+#elif (STM32_PLL2MUL_VALUE == 20)
+#define STM32_PLL2MUL               (15 << 8)
+#else
+#error "invalid STM32_PLL2MUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL3MUL field.
+ */
+#if ((STM32_PLL3MUL_VALUE >= 8) && (STM32_PLL3MUL_VALUE <= 14)) ||          \
+    defined(__DOXYGEN__)
+#define STM32_PLL3MUL               ((STM32_PLL3MUL_VALUE - 2) << 12)
+#elif (STM32_PLL3MUL_VALUE == 16)
+#define STM32_PLL3MUL               (14 << 12)
+#elif (STM32_PLL3MUL_VALUE == 20)
+#define STM32_PLL3MUL               (15 << 12)
+#else
+#error "invalid STM32_PLL3MUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL2 input frequency.
+ */
+#define STM32_PLL2CLKIN             (STM32_HSECLK / STM32_PREDIV2_VALUE)
+
+/* PLL2 input frequency range check.*/
+#if (STM32_PLL2CLKIN < STM32_PLL23IN_MIN) ||                                \
+    (STM32_PLL2CLKIN > STM32_PLL23IN_MAX)
+#error "STM32_PLL2CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)"
+#endif
+
+/**
+ * @brief   PLL2 output clock frequency.
+ */
+#define STM32_PLL2CLKOUT            (STM32_PLL2CLKIN * STM32_PLL2MUL_VALUE)
+
+/**
+ * @brief   PLL2 VCO clock frequency.
+ */
+#define STM32_PLL2VCO               (STM32_PLL2CLKOUT * 2)
+
+/* PLL2 output frequency range check.*/
+#if (STM32_PLL2VCO < STM32_PLL23VCO_MIN) ||                                 \
+    (STM32_PLL2VCO > STM32_PLL23VCO_MAX)
+#error "STM32_PLL2VCO outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)"
+#endif
+
+/**
+ * @brief   PLL3 input frequency.
+ */
+#define STM32_PLL3CLKIN             (STM32_HSECLK / STM32_PREDIV2_VALUE)
+
+/* PLL3 input frequency range check.*/
+#if (STM32_PLL3CLKIN < STM32_PLL23IN_MIN) ||                                \
+    (STM32_PLL3CLKIN > STM32_PLL23IN_MAX)
+#error "STM32_PLL3CLKIN outside acceptable range (STM32_PLL23IN_MIN...STM32_PLL23IN_MAX)"
+#endif
+
+/**
+ * @brief   PLL3 output clock frequency.
+ */
+#define STM32_PLL3CLKOUT            (STM32_PLL3CLKIN * STM32_PLL3MUL_VALUE)
+
+/**
+ * @brief   PLL3 VCO clock frequency.
+ */
+#define STM32_PLL3VCO               (STM32_PLL3CLKOUT * 2)
+
+/* PLL3 output frequency range check.*/
+#if (STM32_PLL3VCO < STM32_PLL23VCO_MIN) ||                                 \
+    (STM32_PLL3VCO > STM32_PLL23VCO_MAX)
+#error "STM32_PLL3CLKOUT outside acceptable range (STM32_PLL23VCO_MIN...STM32_PLL23VCO_MAX)"
+#endif
+
+/**
+ * @brief   PREDIV1 input frequency.
+ */
+#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PREDIV1CLK            STM32_HSECLK
+#elif STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2
+#define STM32_PREDIV1CLK            STM32_PLL2CLKOUT
+#else
+#error "invalid STM32_PREDIV1SRC value specified"
+#endif
+
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_PREDIV1) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN              (STM32_PREDIV1CLK / STM32_PREDIV1_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLL1IN_MIN) || (STM32_PLLCLKIN > STM32_PLL1IN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLL1IN_MIN...STM32_PLL1IN_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/**
+ * @brief   PLL VCO clock frequency.
+ */
+#define STM32_PLLVCO                (STM32_PLLCLKOUT * 2)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLVCO < STM32_PLL1VCO_MIN) || (STM32_PLLVCO > STM32_PLL1VCO_MAX)
+#error "STM32_PLLVCO outside acceptable range (STM32_PLL1VCO_MIN...STM32_PLL1VCO_MAX)"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                (STM32_HSECLK / 128)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK                0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief   ADC frequency.
+ */
+#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_ADCCLK                (STM32_PCLK2 / 2)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
+#define STM32_ADCCLK                (STM32_PCLK2 / 4)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
+#define STM32_ADCCLK                (STM32_PCLK2 / 6)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
+#define STM32_ADCCLK                (STM32_PCLK2 / 8)
+#else
+#error "invalid STM32_ADCPRE value specified"
+#endif
+
+/* ADC frequency check.*/
+#if STM32_ADCCLK > STM32_ADCCLK_MAX
+#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/**
+ * @brief   OTG frequency.
+ */
+#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__)
+#define STM32_OTGFSCLK              (STM32_PLLVCO / 3)
+#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2)
+#define STM32_OTGFSCLK              (STM32_PLLVCO / 2)
+#else
+#error "invalid STM32_OTGFSPRE value specified"
+#endif
+
+/**
+ * @brief   Timers 2, 3, 4, 5, 6, 7 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief   Timers 1, 8 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS             0x00000011
+#else
+#define STM32_FLASHBITS             0x00000012
+#endif
+
+#endif /* _HAL_LLD_F105_F107_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F1xx/platform.mk b/os/hal/ports/STM32/STM32F1xx/platform.mk
new file mode 100644
index 000000000..daff671f2
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/platform.mk
@@ -0,0 +1,34 @@
+# List of all the STM32F1xx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/stm32_dma.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/adc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/can_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/ext_lld.c \
+			  ${CHIBIOS}/os/hal/ports/STM32/LLD/mac_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/sdc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c \
+			  ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1
+
diff --git a/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk b/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk
new file mode 100644
index 000000000..267f78599
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk
@@ -0,0 +1,32 @@
+# List of all the STM32F1xx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/stm32_dma.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/adc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/can_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/ext_lld.c \
+			  ${CHIBIOS}/os/hal/ports/STM32/LLD/mac_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/sdc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c \
+			  ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/OTGv1
diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_dma.c b/os/hal/ports/STM32/STM32F1xx/stm32_dma.c
new file mode 100644
index 000000000..c3b39d37c
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/stm32_dma.c
@@ -0,0 +1,491 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/stm32_dma.c
+ * @brief   DMA helper driver code.
+ *
+ * @addtogroup STM32F1xx_DMA
+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a
+ *          shared resource, this driver allows to allocate and free DMA
+ *          streams at runtime in order to allow all the other device
+ *          drivers to coordinate the access to the resource.
+ * @note    The DMA ISR handlers are all declared into this module because
+ *          sharing, the various device drivers can associate a callback to
+ *          ISRs when allocating streams.
+ * @{
+ */
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA1_STREAMS_MASK     0x0000007F
+
+/**
+ * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA2_STREAMS_MASK     0x00000F80
+
+/**
+ * @brief   Post-reset value of the stream CCR register.
+ */
+#define STM32_DMA_CCR_RESET_VALUE   0x00000000
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ *          identifier and the involved physical registers.
+ * @note    Don't use this array directly, use the appropriate wrapper macros
+ *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
+ */
+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
+  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
+  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
+  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
+  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
+  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
+  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
+  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
+#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
+  {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
+  {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
+  {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
+#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
+  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
+  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
+#else /* !STM32F10X_CL */
+  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn},
+  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn},
+#endif /* !STM32F10X_CL */
+#endif /* STM32_HAS_DMA2 */
+};
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA ISR redirector type.
+ */
+typedef struct {
+  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
+  void                  *dma_param;     /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
+/**
+ * @brief   Mask of the allocated streams.
+ */
+static uint32_t dma_streams_mask;
+
+/**
+ * @brief   DMA IRQ redirectors.
+ */
+static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA1 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector6C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 0;
+  if (dma_isr_redir[0].dma_func)
+    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 4;
+  if (dma_isr_redir[1].dma_func)
+    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector74) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 8;
+  if (dma_isr_redir[2].dma_func)
+    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector78) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 12;
+  if (dma_isr_redir[3].dma_func)
+    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector7C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 16;
+  if (dma_isr_redir[4].dma_func)
+    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 6 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector80) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 20;
+  if (dma_isr_redir[5].dma_func)
+    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 7 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector84) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 24;
+  if (dma_isr_redir[6].dma_func)
+    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
+/**
+ * @brief   DMA2 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector120) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 0;
+  if (dma_isr_redir[7].dma_func)
+    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector124) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 4;
+  if (dma_isr_redir[8].dma_func)
+    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector128) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 8;
+  if (dma_isr_redir[9].dma_func)
+    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA2 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector12C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 12;
+  if (dma_isr_redir[10].dma_func)
+    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector130) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 16;
+  if (dma_isr_redir[11].dma_func)
+    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#else /* !STM32F10X_CL */
+/**
+ * @brief   DMA2 streams 4 and 5 shared interrupt handler.
+ * @note    This IRQ is shared between DMA2 channels 4 and 5 so it is a
+ *          bit less efficient because an extra check.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  /* Check on channel 4.*/
+  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA2->IFCR = flags << 12;
+    if (dma_isr_redir[10].dma_func)
+      dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+  }
+
+  /* Check on channel 5.*/
+  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA2->IFCR = flags << 16;
+    if (dma_isr_redir[11].dma_func)
+      dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+  }
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* !STM32F10X_CL */
+#endif /* STM32_HAS_DMA2 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+  int i;
+
+  dma_streams_mask = 0;
+  for (i = 0; i < STM32_DMA_STREAMS; i++) {
+    _stm32_dma_streams[i].channel->CCR = 0;
+    dma_isr_redir[i].dma_func = NULL;
+  }
+  DMA1->IFCR = 0xFFFFFFFF;
+#if STM32_HAS_DMA2
+  DMA2->IFCR = 0xFFFFFFFF;
+#endif
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ * @pre     The stream must not be already in use or an error is returned.
+ * @post    The stream is allocated and the default ISR handler redirected
+ *          to the specified function.
+ * @post    The stream ISR vector is enabled and its priority configured.
+ * @post    The stream must be freed using @p dmaStreamRelease() before it can
+ *          be reused with another peripheral.
+ * @post    The stream is in its post-reset state.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] priority  IRQ priority mask for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              The operation status.
+ * @retval FALSE        no error, stream taken.
+ * @retval TRUE         error, stream already taken.
+ *
+ * @special
+ */
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                       uint32_t priority,
+                       stm32_dmaisr_t func,
+                       void *param) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Checks if the stream is already taken.*/
+  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
+    return TRUE;
+
+  /* Marks the stream as allocated.*/
+  dma_isr_redir[dmastp->selfindex].dma_func  = func;
+  dma_isr_redir[dmastp->selfindex].dma_param = param;
+  dma_streams_mask |= (1 << dmastp->selfindex);
+
+  /* Enabling DMA clocks required by the current streams set.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
+    rccEnableDMA1(FALSE);
+#if STM32_HAS_DMA2
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
+    rccEnableDMA2(FALSE);
+#endif
+
+  /* Putting the stream in a safe state.*/
+  dmaStreamDisable(dmastp);
+  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
+
+  /* Enables the associated IRQ vector if a callback is defined.*/
+  if (func != NULL)
+    nvicEnableVector(dmastp->vector, priority);
+
+  return FALSE;
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    The stream is again available.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Check if the streams is not taken.*/
+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+                "not allocated");
+
+  /* Disables the associated IRQ vector.*/
+  nvicDisableVector(dmastp->vector);
+
+  /* Marks the stream as not allocated.*/
+  dma_streams_mask &= ~(1 << dmastp->selfindex);
+
+  /* Shutting down clocks that are no more required, if any.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
+    rccDisableDMA1(FALSE);
+#if STM32_HAS_DMA2
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
+    rccDisableDMA2(FALSE);
+#endif
+}
+
+#endif /* STM32_DMA_REQUIRED */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_dma.h b/os/hal/ports/STM32/STM32F1xx/stm32_dma.h
new file mode 100644
index 000000000..00f6e344a
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/stm32_dma.h
@@ -0,0 +1,406 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/stm32_dma.h
+ * @brief   DMA helper driver header.
+ * @note    This file requires definitions from the ST header file stm32f10x.h.
+ * @note    This driver uses the new naming convention used for the STM32F2xx
+ *          so the "DMA channels" are referred as "DMA streams".
+ *
+ * @addtogroup STM32F1xx_DMA
+ * @{
+ */
+
+#ifndef _STM32_DMA_H_
+#define _STM32_DMA_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Total number of DMA streams.
+ * @note    This is the total number of streams among all the DMA units.
+ */
+#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
+#define STM32_DMA_STREAMS           12
+#else
+#define STM32_DMA_STREAMS           7
+#endif
+
+/**
+ * @brief   Mask of the ISR bits passed to the DMA callback functions.
+ */
+#define STM32_DMA_ISR_MASK          0x0F
+
+/**
+ * @brief   Returns the channel associated to the specified stream.
+ *
+ * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
+ * @param[in] c         a stream/channel association word, one channel per
+ *                      nibble, not associated channels must be set to 0xF
+ * @return              Always zero, in this platform there is no dynamic
+ *                      association between streams and channels.
+ */
+#define STM32_DMA_GETCHANNEL(n, c)  0
+
+/**
+ * @brief   Checks if a DMA priority is within the valid range.
+ * @param[in] prio      DMA priority
+ *
+ * @retval              The check result.
+ * @retval FALSE        invalid DMA priority.
+ * @retval TRUE         correct DMA priority.
+ */
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+
+/**
+ * @brief   Returns an unique numeric identifier for a DMA stream.
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              An unique numeric stream identifier.
+ */
+#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
+
+/**
+ * @brief   Returns a DMA stream identifier mask.
+ *
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              A DMA stream identifier mask.
+ */
+#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
+  (1 << STM32_DMA_STREAM_ID(dma, stream))
+
+/**
+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.
+ * @param[in] id        the stream numeric identifier
+ * @param[in] mask      the stream numeric identifiers mask
+ *
+ * @retval              The check result.
+ * @retval FALSE        id does not belong to the mask.
+ * @retval TRUE         id belongs to the mask.
+ */
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+
+/**
+ * @name    DMA streams identifiers
+ * @{
+ */
+/**
+ * @brief   Returns a pointer to a stm32_dma_stream_t structure.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @return              A pointer to the stm32_dma_stream_t constant structure
+ *                      associated to the DMA stream.
+ */
+#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
+
+#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
+#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
+#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
+#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
+#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
+#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
+#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
+#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(7)
+#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(8)
+#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(9)
+#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(10)
+#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(11)
+/** @} */
+
+/**
+ * @name    CR register constants common to all DMA types
+ * @{
+ */
+#define STM32_DMA_CR_EN             DMA_CCR1_EN
+#define STM32_DMA_CR_TEIE           DMA_CCR1_TEIE
+#define STM32_DMA_CR_HTIE           DMA_CCR1_HTIE
+#define STM32_DMA_CR_TCIE           DMA_CCR1_TCIE
+#define STM32_DMA_CR_DIR_MASK       (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM)
+#define STM32_DMA_CR_DIR_P2M        0
+#define STM32_DMA_CR_DIR_M2P        DMA_CCR1_DIR
+#define STM32_DMA_CR_DIR_M2M        DMA_CCR1_MEM2MEM
+#define STM32_DMA_CR_CIRC           DMA_CCR1_CIRC
+#define STM32_DMA_CR_PINC           DMA_CCR1_PINC
+#define STM32_DMA_CR_MINC           DMA_CCR1_MINC
+#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR1_PSIZE
+#define STM32_DMA_CR_PSIZE_BYTE     0
+#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR1_PSIZE_0
+#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR1_PSIZE_1
+#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR1_MSIZE
+#define STM32_DMA_CR_MSIZE_BYTE     0
+#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR1_MSIZE_0
+#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR1_MSIZE_1
+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
+                                     STM32_DMA_CR_MSIZE_MASK)
+#define STM32_DMA_CR_PL_MASK        DMA_CCR1_PL
+#define STM32_DMA_CR_PL(n)          ((n) << 12)
+/** @} */
+
+/**
+ * @name    CR register constants only found in enhanced DMA
+ * @{
+ */
+#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
+/** @} */
+
+/**
+ * @name    Status flags passed to the ISR callbacks
+ * @{
+ */
+#define STM32_DMA_ISR_FEIF          0
+#define STM32_DMA_ISR_DMEIF         0
+#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
+#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
+#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA stream descriptor structure.
+ */
+typedef struct {
+  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
+  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
+  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
+                                             register.                      */
+  uint8_t               selfindex;      /**< @brief Index to self in array. */
+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
+} stm32_dma_stream_t;
+
+/**
+ * @brief   STM32 DMA ISR function type.
+ *
+ * @param[in] p         parameter for the registered function
+ * @param[in] flags     pre-shifted content of the ISR register, the bits
+ *                      are aligned to bit zero
+ */
+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Associates a peripheral data register to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CPAR register
+ *
+ * @special
+ */
+#define dmaStreamSetPeripheral(dmastp, addr) {                              \
+  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Associates a memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CMAR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory0(dmastp, addr) {                                 \
+  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Sets the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] size      value to be written in the CNDTR register
+ *
+ * @special
+ */
+#define dmaStreamSetTransactionSize(dmastp, size) {                         \
+  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
+}
+
+/**
+ * @brief   Returns the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @return              The number of transfers to be performed.
+ *
+ * @special
+ */
+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
+
+/**
+ * @brief   Programs the stream mode settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register
+ *
+ * @special
+ */
+#define dmaStreamSetMode(dmastp, mode) {                                    \
+  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
+}
+
+/**
+ * @brief   DMA stream enable.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamEnable(dmastp) {                                           \
+  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
+}
+
+/**
+ * @brief   DMA stream disable.
+ * @details The function disables the specified stream and then clears any
+ *          pending interrupt.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @note    Interrupts enabling flags are set to zero after this call, see
+ *          bug 3607518.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamDisable(dmastp) {                                          \
+  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
+                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
+  dmaStreamClearInterrupt(dmastp);                                          \
+}
+
+/**
+ * @brief   DMA stream interrupt sources clear.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamClearInterrupt(dmastp) {                                   \
+  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
+}
+
+/**
+ * @brief   Starts a memory to memory operation using the specified stream.
+ * @note    The default transfer data mode is "byte to byte" but it can be
+ *          changed by specifying extra options in the @p mode parameter.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register, this value
+ *                      is implicitly ORed with:
+ *                      - @p STM32_DMA_CR_MINC
+ *                      - @p STM32_DMA_CR_PINC
+ *                      - @p STM32_DMA_CR_DIR_M2M
+ *                      - @p STM32_DMA_CR_EN
+ *                      .
+ * @param[in] src       source address
+ * @param[in] dst       destination address
+ * @param[in] n         number of data units to copy
+ */
+#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
+  dmaStreamSetPeripheral(dmastp, src);                                      \
+  dmaStreamSetMemory0(dmastp, dst);                                         \
+  dmaStreamSetTransactionSize(dmastp, n);                                   \
+  dmaStreamSetMode(dmastp, (mode) |                                         \
+                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
+                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
+}
+
+/**
+ * @brief   Polled wait for DMA transfer end.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ */
+#define dmaWaitCompletion(dmastp) {                                         \
+  while ((dmastp)->channel->CNDTR > 0)                                      \
+    ;                                                                       \
+  dmaStreamDisable(dmastp);                                                 \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dmaInit(void);
+  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                         uint32_t priority,
+                         stm32_dmaisr_t func,
+                         void *param);
+  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_DMA_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F1xx/stm32_isr.h b/os/hal/ports/STM32/STM32F1xx/stm32_isr.h
index 892fa0f9d..892fa0f9d 100644
--- a/os/hal/platforms/STM32F1xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F1xx/stm32_isr.h
diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h
index 8de6ec43c..8de6ec43c 100644
--- a/os/hal/platforms/STM32F1xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h
diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
new file mode 100644
index 000000000..46ce6e297
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h
@@ -0,0 +1,1094 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F1xx/stm32_registry.h
+ * @brief   STM32F1xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
+/**
+ * @name    STM32F100 LD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      FALSE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               0
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             18
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     FALSE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      FALSE
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_IS_CALENDAR               FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      FALSE
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              4
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    FALSE
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+#endif /* defined(STM32F10X_LD_VL) */
+
+#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
+/**
+ * @name    STM32F100 MD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      FALSE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               0
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     FALSE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_IS_CALENDAR               FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              4
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+#endif /* defined(STM32F10X_MD_VL) */
+
+#if defined(STM32F10X_LD) || defined(__DOXYGEN__)
+/**
+ * @name    STM32F103 LD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      FALSE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     FALSE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      FALSE
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_IS_CALENDAR               FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      FALSE
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              4
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM6                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM15                     FALSE
+#define STM32_HAS_TIM16                     FALSE
+#define STM32_HAS_TIM17                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    FALSE
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+#endif /* defined(STM32F10X_LD) */
+
+#if defined(STM32F10X_MD) || defined(__DOXYGEN__)
+/**
+ * @name    STM32F103 MD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      FALSE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     FALSE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_IS_CALENDAR               FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              4
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM6                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM15                     FALSE
+#define STM32_HAS_TIM16                     FALSE
+#define STM32_HAS_TIM17                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+#endif /* defined(STM32F10X_MD) */
+
+#if defined(STM32F10X_HD) || defined(__DOXYGEN__)
+/**
+ * @name    STM32F103 HD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      TRUE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     TRUE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_IS_CALENDAR               FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      TRUE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              4
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM5                      TRUE
+#define STM32_TIM5_IS_32BITS                FALSE
+#define STM32_TIM5_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM8                      TRUE
+#define STM32_TIM8_IS_32BITS                FALSE
+#define STM32_TIM8_CHANNELS                 4
+
+#define STM32_HAS_TIM9                      TRUE
+#define STM32_TIM9_IS_32BITS                FALSE
+#define STM32_TIM9_CHANNELS                 2
+
+#define STM32_HAS_TIM10                     TRUE
+#define STM32_TIM10_IS_32BITS               FALSE
+#define STM32_TIM10_CHANNELS                2
+
+#define STM32_HAS_TIM11                     TRUE
+#define STM32_TIM11_IS_32BITS               FALSE
+#define STM32_TIM11_CHANNELS                2
+
+#define STM32_HAS_TIM12                     TRUE
+#define STM32_TIM12_IS_32BITS               FALSE
+#define STM32_TIM12_CHANNELS                2
+
+#define STM32_HAS_TIM13                     TRUE
+#define STM32_TIM13_IS_32BITS               FALSE
+#define STM32_TIM13_CHANNELS                2
+
+#define STM32_HAS_TIM14                     TRUE
+#define STM32_TIM14_IS_32BITS               FALSE
+#define STM32_TIM14_CHANNELS                2
+
+#define STM32_HAS_TIM15                     FALSE
+#define STM32_HAS_TIM16                     FALSE
+#define STM32_HAS_TIM17                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+#endif /* defined(STM32F10X_HD) */
+
+#if defined(STM32F10X_XL) || defined(__DOXYGEN__)
+/**
+ * @name    STM32F103 XL capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      TRUE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     TRUE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_IS_CALENDAR               FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      TRUE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              4
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM5                      TRUE
+#define STM32_TIM5_IS_32BITS                FALSE
+#define STM32_TIM5_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM8                      TRUE
+#define STM32_TIM8_IS_32BITS                FALSE
+#define STM32_TIM8_CHANNELS                 4
+
+#define STM32_HAS_TIM9                      TRUE
+#define STM32_TIM9_IS_32BITS                FALSE
+#define STM32_TIM9_CHANNELS                 2
+
+#define STM32_HAS_TIM10                     TRUE
+#define STM32_TIM10_IS_32BITS               FALSE
+#define STM32_TIM10_CHANNELS                2
+
+#define STM32_HAS_TIM11                     TRUE
+#define STM32_TIM11_IS_32BITS               FALSE
+#define STM32_TIM11_CHANNELS                2
+
+#define STM32_HAS_TIM12                     TRUE
+#define STM32_TIM12_IS_32BITS               FALSE
+#define STM32_TIM12_CHANNELS                2
+
+#define STM32_HAS_TIM13                     TRUE
+#define STM32_TIM13_IS_32BITS               FALSE
+#define STM32_TIM13_CHANNELS                2
+
+#define STM32_HAS_TIM14                     TRUE
+#define STM32_TIM14_IS_32BITS               FALSE
+#define STM32_TIM14_CHANNELS                2
+
+#define STM32_HAS_TIM15                     FALSE
+#define STM32_HAS_TIM16                     FALSE
+#define STM32_HAS_TIM17                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+#endif /* defined(STM32F10X_XL) */
+
+#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
+/**
+ * @name    STM32F105/F107 CL capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      TRUE
+#define STM32_CAN_MAX_FILTERS               28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       TRUE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             20
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     FALSE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_IS_CALENDAR               FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              4
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM5                      TRUE
+#define STM32_TIM5_IS_32BITS                FALSE
+#define STM32_TIM5_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM15                     FALSE
+#define STM32_HAS_TIM16                     FALSE
+#define STM32_HAS_TIM17                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5                     TRUE
+
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      TRUE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+#endif /* defined(STM32F10X_CL) */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/adc_lld.c b/os/hal/ports/STM32/STM32F30x/adc_lld.c
new file mode 100644
index 000000000..4be6b56a7
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F30x/adc_lld.c
@@ -0,0 +1,548 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F30x/adc_lld.c
+ * @brief   STM32F30x ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if STM32_ADC_DUAL_MODE
+#if STM32_ADC_COMPACT_SAMPLES
+/* Compact type dual mode.*/
+#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
+#define ADC_DMA_MDMA    ADC_CCR_MDMA_HWORD
+
+#else /* !STM32_ADC_COMPACT_SAMPLES */
+/* Large type dual mode.*/
+#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)
+#define ADC_DMA_MDMA    ADC_CCR_MDMA_WORD
+#endif /* !STM32_ADC_COMPACT_SAMPLES */
+
+#else /* !STM32_ADC_DUAL_MODE */
+#if STM32_ADC_COMPACT_SAMPLES
+/* Compact type single mode.*/
+#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
+#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED
+
+#else /* !STM32_ADC_COMPACT_SAMPLES */
+/* Large type single mode.*/
+#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
+#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED
+#endif /* !STM32_ADC_COMPACT_SAMPLES */
+#endif /* !STM32_ADC_DUAL_MODE */
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
+ADCDriver ADCD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the ADC voltage regulator.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_vreg_on(ADCDriver *adcp) {
+
+  adcp->adcm->CR = 0;   /* RM 12.4.3.*/
+  adcp->adcm->CR = ADC_CR_ADVREGEN_0;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcs->CR = ADC_CR_ADVREGEN_0;
+#endif
+  osalSysPolledDelayX(US2RTC(STM32_HCLK, 10));
+}
+
+/**
+ * @brief   Disables the ADC voltage regulator.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_vreg_off(ADCDriver *adcp) {
+
+  adcp->adcm->CR = 0;   /* RM 12.4.3.*/
+  adcp->adcm->CR = ADC_CR_ADVREGEN_1;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcs->CR = ADC_CR_ADVREGEN_1;
+#endif
+}
+
+/**
+ * @brief   Enables the ADC analog circuit.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_analog_on(ADCDriver *adcp) {
+
+  adcp->adcm->CR |= ADC_CR_ADEN;
+  while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0)
+    ;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcs->CR |= ADC_CR_ADEN;
+  while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0)
+    ;
+#endif
+}
+
+/**
+ * @brief   Disables the ADC  analog circuit.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_analog_off(ADCDriver *adcp) {
+
+  adcp->adcm->CR |= ADC_CR_ADDIS;
+  while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)
+    ;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcs->CR |= ADC_CR_ADDIS;
+  while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)
+    ;
+#endif
+}
+
+/**
+ * @brief   Calibrates and ADC unit.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_calibrate(ADCDriver *adcp) {
+
+  osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state");
+  adcp->adcm->CR |= ADC_CR_ADCAL;
+  while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
+    ;
+#if STM32_ADC_DUAL_MODE
+  osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state");
+  adcp->adcs->CR |= ADC_CR_ADCAL;
+  while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
+    ;
+#endif
+}
+
+/**
+ * @brief   Stops an ongoing conversion, if any.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_stop_adc(ADCDriver *adcp) {
+
+  if (adcp->adcm->CR & ADC_CR_ADSTART) {
+    adcp->adcm->CR |= ADC_CR_ADSTP;
+    while (adcp->adcm->CR & ADC_CR_ADSTP)
+      ;
+  }
+}
+
+/**
+ * @brief   ADC DMA ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    /* DMA, this could help only if the DMA tries to access an unmapped
+       address space or violates alignment rules.*/
+    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+  }
+  else {
+    /* It is possible that the conversion group has already be reset by the
+       ADC error handler, in this case this interrupt is spurious.*/
+    if (adcp->grpp != NULL) {
+      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+        /* Transfer complete processing.*/
+        _adc_isr_full_code(adcp);
+      }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
+    }
+  }
+}
+
+/**
+ * @brief   ADC ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] isr       content of the ISR register
+ */
+static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
+
+  /* It could be a spurious interrupt caused by overflows after DMA disabling,
+     just ignore it in this case.*/
+  if (adcp->grpp != NULL) {
+    /* Note, an overflow may occur after the conversion ended before the driver
+       is able to stop the ADC, this is why the DMA channel is checked too.*/
+    if ((isr & ADC_ISR_OVR) &&
+        (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
+      /* ADC overflow condition, this could happen only if the DMA is unable
+         to read data fast enough.*/
+      _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
+    }
+    if (isr & ADC_ISR_AWD1) {
+      /* Analog watchdog error.*/
+      _adc_isr_error_code(adcp, ADC_ERR_AWD1);
+    }
+    if (isr & ADC_ISR_AWD2) {
+      /* Analog watchdog error.*/
+      _adc_isr_error_code(adcp, ADC_ERR_AWD2);
+    }
+    if (isr & ADC_ISR_AWD3) {
+      /* Analog watchdog error.*/
+      _adc_isr_error_code(adcp, ADC_ERR_AWD3);
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief   ADC1/ADC2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector88) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+#if STM32_ADC_DUAL_MODE
+  isr  = ADC1->ISR;
+  isr |= ADC2->ISR;
+  ADC1->ISR = isr;
+  ADC2->ISR = isr;
+#else /* !STM32_ADC_DUAL_MODE */
+  isr  = ADC1->ISR;
+  ADC1->ISR = isr;
+#endif /* !STM32_ADC_DUAL_MODE */
+
+  adc_lld_serve_interrupt(&ADCD1, isr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
+/**
+ * @brief   ADC3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorFC) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  isr  = ADC3->ISR;
+  ADC3->ISR = isr;
+
+  adc_lld_serve_interrupt(&ADCD3, isr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if STM32_ADC_DUAL_MODE
+/**
+ * @brief   ADC4 interrupt handler (as ADC3 slave).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector134) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  isr  = ADC4->ISR;
+  ADC4->ISR = isr;
+
+  adc_lld_serve_interrupt(&ADCD3, isr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_DUAL_MODE */
+#endif /* STM32_ADC_USE_ADC3 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adcc = ADC1_2;
+  ADCD1.adcm = ADC1;
+#if STM32_ADC_DUAL_MODE
+  ADCD1.adcs = ADC2;
+#endif
+  ADCD1.dmastp  = STM32_DMA1_STREAM1;
+  ADCD1.dmamode = ADC_DMA_SIZE |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+  nvicEnableVector(ADC1_2_IRQn, STM32_ADC_ADC12_IRQ_PRIORITY);
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_ADC3
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD3);
+  ADCD3.adcc = ADC3_4;
+  ADCD3.adcm = ADC3;
+#if STM32_ADC_DUAL_MODE
+  ADCD3.adcs = ADC4;
+#endif
+  ADCD3.dmastp  = STM32_DMA2_STREAM5;
+  ADCD3.dmamode = ADC_DMA_SIZE |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+  nvicEnableVector(ADC3_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
+#if STM32_ADC_DUAL_MODE
+  nvicEnableVector(ADC4_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
+#endif
+#endif /* STM32_ADC_USE_ADC3 */
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+  /* If in stopped state then enables the ADC and DMA clocks.*/
+  if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      bool b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC12_DMA_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+                            (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableADC12(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_ADC3
+    if (&ADCD3 == adcp) {
+      bool b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC34_DMA_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+                            (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableADC34(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC2 */
+
+    /* Setting DMA peripheral-side pointer.*/
+#if STM32_ADC_DUAL_MODE
+      dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);
+#else
+      dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);
+#endif
+
+    /* Clock source setting.*/
+    adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+
+    /* Master ADC calibration.*/
+    adc_lld_vreg_on(adcp);
+    adc_lld_calibrate(adcp);
+
+    /* Master ADC enabled here in order to reduce conversions latencies.*/
+    adc_lld_analog_on(adcp);
+  }
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+  /* If in ready state then disables the ADC clock and analog part.*/
+  if (adcp->state == ADC_READY) {
+
+    /* Releasing the associated DMA channel.*/
+    dmaStreamRelease(adcp->dmastp);
+
+    /* Stopping the ongoing conversion, if any.*/
+    adc_lld_stop_adc(adcp);
+
+    /* Disabling ADC analog circuit and regulator.*/
+    adc_lld_analog_off(adcp);
+    adc_lld_vreg_off(adcp);
+
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp)
+      rccDisableADC12(FALSE);
+#endif
+
+#if STM32_ADC_USE_ADC3
+    if (&ADCD1 == adcp)
+      rccDisableADC34(FALSE);
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+  uint32_t dmamode, ccr, cfgr;
+  const ADCConversionGroup *grpp = adcp->grpp;
+
+  osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
+                "odd number of channels in dual mode");
+
+  /* Calculating control registers values.*/
+  dmamode = adcp->dmamode;
+  ccr     = grpp->ccr | (adcp->adcc->CCR & (ADC_CCR_CKMODE_MASK |
+                                            ADC_CCR_MDMA_MASK));
+  cfgr    = grpp->cfgr | ADC_CFGR_CONT | ADC_CFGR_DMAEN;
+  if (grpp->circular) {
+    dmamode |= STM32_DMA_CR_CIRC;
+#if STM32_ADC_DUAL_MODE
+    ccr  |= ADC_CCR_DMACFG_CIRCULAR;
+#else
+    cfgr |= ADC_CFGR_DMACFG_CIRCULAR;
+#endif
+    if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
+      dmamode |= STM32_DMA_CR_HTIE;
+    }
+  }
+
+  /* DMA setup.*/
+  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+#if STM32_ADC_DUAL_MODE
+  dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *
+                                            (uint32_t)adcp->depth);
+#else
+    dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+                                              (uint32_t)adcp->depth);
+#endif
+  dmaStreamSetMode(adcp->dmastp, dmamode);
+  dmaStreamEnable(adcp->dmastp);
+
+  /* Configuring the CCR register with the static settings ORed with
+     the user-specified settings in the conversion group configuration
+     structure.*/
+  adcp->adcc->CCR   = ccr;
+
+  /* ADC setup, if it is defined a callback for the analog watch dog then it
+     is enabled.*/
+  adcp->adcm->ISR   = adcp->adcm->ISR;
+  adcp->adcm->IER   = ADC_IER_OVR | ADC_IER_AWD1;
+  adcp->adcm->TR1   = grpp->tr1;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcm->SMPR1 = grpp->smpr[0];
+  adcp->adcm->SMPR2 = grpp->smpr[1];
+  adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
+  adcp->adcm->SQR2  = grpp->sqr[1];
+  adcp->adcm->SQR3  = grpp->sqr[2];
+  adcp->adcm->SQR4  = grpp->sqr[3];
+  adcp->adcs->SMPR1 = grpp->ssmpr[0];
+  adcp->adcs->SMPR2 = grpp->ssmpr[1];
+  adcp->adcs->SQR1  = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
+  adcp->adcs->SQR2  = grpp->ssqr[1];
+  adcp->adcs->SQR3  = grpp->ssqr[2];
+  adcp->adcs->SQR4  = grpp->ssqr[3];
+
+#else /* !STM32_ADC_DUAL_MODE */
+  adcp->adcm->SMPR1 = grpp->smpr[0];
+  adcp->adcm->SMPR2 = grpp->smpr[1];
+  adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
+  adcp->adcm->SQR2  = grpp->sqr[1];
+  adcp->adcm->SQR3  = grpp->sqr[2];
+  adcp->adcm->SQR4  = grpp->sqr[3];
+#endif /* !STM32_ADC_DUAL_MODE */
+
+  /* ADC configuration.*/
+  adcp->adcm->CFGR  = cfgr;
+
+  /* Starting conversion.*/
+  adcp->adcm->CR   |= ADC_CR_ADSTART;
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+  dmaStreamDisable(adcp->dmastp);
+  adc_lld_stop_adc(adcp);
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/adc_lld.h b/os/hal/ports/STM32/STM32F30x/adc_lld.h
new file mode 100644
index 000000000..1c9ac03e4
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F30x/adc_lld.h
@@ -0,0 +1,608 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F30x/adc_lld.h
+ * @brief   STM32F30x ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Available analog channels
+ * @{
+ */
+#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
+#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
+#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
+#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
+#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
+#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
+#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
+#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
+#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
+#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
+#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
+#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
+#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
+#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
+#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
+#define ADC_CHANNEL_IN16        16  /**< @brief External analog input 16.   */
+#define ADC_CHANNEL_IN17        17  /**< @brief External analog input 17.   */
+#define ADC_CHANNEL_IN18        18  /**< @brief External analog input 18.   */
+/** @} */
+
+/**
+ * @name    Sampling rates
+ * @{
+ */
+#define ADC_SMPR_SMP_1P5        0   /**< @brief 14 cycles conversion time   */
+#define ADC_SMPR_SMP_2P5        1   /**< @brief 15 cycles conversion time.  */
+#define ADC_SMPR_SMP_4P5        2   /**< @brief 17 cycles conversion time.  */
+#define ADC_SMPR_SMP_7P5        3   /**< @brief 20 cycles conversion time.  */
+#define ADC_SMPR_SMP_19P5       4   /**< @brief 32 cycles conversion time.  */
+#define ADC_SMPR_SMP_61P5       5   /**< @brief 74 cycles conversion time.  */
+#define ADC_SMPR_SMP_181P5      6   /**< @brief 194 cycles conversion time. */
+#define ADC_SMPR_SMP_601P5      7   /**< @brief 614 cycles conversion time. */
+/** @} */
+
+/**
+ * @name    Resolution
+ * @{
+ */
+#define ADC_CFGR1_RES_12BIT     (0 << 3)
+#define ADC_CFGR1_RES_10BIT     (1 << 3)
+#define ADC_CFGR1_RES_8BIT      (2 << 3)
+#define ADC_CFGR1_RES_6BIT      (3 << 3)
+/** @} */
+
+/**
+ * @name    CFGR register configuration helpers
+ * @{
+ */
+#define ADC_CFGR_DMACFG_MASK            (1 << 1)
+#define ADC_CFGR_DMACFG_ONESHOT         (0 << 1)
+#define ADC_CFGR_DMACFG_CIRCULAR        (1 << 1)
+
+#define ADC_CFGR_RES_MASK               (3 << 3)
+#define ADC_CFGR_RES_12BITS             (0 << 3)
+#define ADC_CFGR_RES_10BITS             (1 << 3)
+#define ADC_CFGR_RES_8BITS              (2 << 3)
+#define ADC_CFGR_RES_6BITS              (3 << 3)
+
+#define ADC_CFGR_ALIGN_MASK             (1 << 5)
+#define ADC_CFGR_ALIGN_RIGHT            (0 << 5)
+#define ADC_CFGR_ALIGN_LEFT             (1 << 5)
+
+#define ADC_CFGR_EXTSEL_MASK            (15 << 6)
+#define ADC_CFGR_EXTSEL_SRC(n)          ((n) << 6)
+
+#define ADC_CFGR_EXTEN_MASK             (3 << 10)
+#define ADC_CFGR_EXTEN_DISABLED         (0 << 10)
+#define ADC_CFGR_EXTEN_RISING           (1 << 10)
+#define ADC_CFGR_EXTEN_FALLING          (2 << 10)
+#define ADC_CFGR_EXTEN_BOTH             (3 << 10)
+
+#define ADC_CFGR_DISCEN_MASK            (1 << 16)
+#define ADC_CFGR_DISCEN_DISABLED        (0 << 16)
+#define ADC_CFGR_DISCEN_ENABLED         (1 << 16)
+
+#define ADC_CFGR_DISCNUM_MASK           (7 << 17)
+#define ADC_CFGR_DISCNUM_VAL(n)         ((n) << 17)
+
+#define ADC_CFGR_AWD1_DISABLED          0
+#define ADC_CFGR_AWD1_ALL               (1 << 23)
+#define ADC_CFGR_AWD1_SINGLE(n)         (((n) << 26) | (1 << 23) | (1 << 22))
+/** @} */
+
+/**
+ * @name    CCR register configuration helpers
+ * @{
+ */
+#define ADC_CCR_DUAL_MASK               (31 << 0)
+#define ADC_CCR_DUAL(n)                 ((n) << 0)
+#define ADC_CCR_DELAY_MASK              (15 << 8)
+#define ADC_CCR_DELAY(n)                ((n) << 8)
+#define ADC_CCR_DMACFG_MASK             (1 << 13)
+#define ADC_CCR_DMACFG_ONESHOT          (0 << 13)
+#define ADC_CCR_DMACFG_CIRCULAR         (1 << 13)
+#define ADC_CCR_MDMA_MASK               (3 << 14)
+#define ADC_CCR_MDMA_DISABLED           (0 << 14)
+#define ADC_CCR_MDMA_WORD               (2 << 14)
+#define ADC_CCR_MDMA_HWORD              (3 << 14)
+#define ADC_CCR_CKMODE_MASK             (3 << 16)
+#define ADC_CCR_CKMODE_ADCCK            (0 << 16)
+#define ADC_CCR_CKMODE_AHB_DIV1         (1 << 16)
+#define ADC_CCR_CKMODE_AHB_DIV2         (2 << 16)
+#define ADC_CCR_CKMODE_AHB_DIV4         (3 << 16)
+#define ADC_CCR_VREFEN                  (1 << 22)
+#define ADC_CCR_TSEN                    (1 << 23)
+#define ADC_CCR_VBATEN                  (1 << 24)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1                  FALSE
+#endif
+
+/**
+ * @brief   ADC3 driver enable switch.
+ * @details If set to @p TRUE the support for ADC3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC3                  FALSE
+#endif
+
+/**
+ * @brief   ADC1/ADC2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC12_DMA_PRIORITY        2
+#endif
+
+/**
+ * @brief   ADC3/ADC4 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC34_DMA_PRIORITY        2
+#endif
+
+/**
+ * @brief   ADC1/ADC2 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC12_IRQ_PRIORITY        5
+#endif
+
+/**
+ * @brief   ADC3/ADC4 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC34_IRQ_PRIORITY        5
+#endif
+
+/**
+ * @brief   ADC1/ADC2 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5
+#endif
+
+/**
+ * @brief   ADC3/ADC4 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5
+#endif
+
+/**
+ * @brief   ADC1/ADC2 clock source and mode.
+ */
+#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
+#endif
+
+/**
+ * @brief   ADC3/ADC4 clock source and mode.
+ */
+#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
+#endif
+
+/**
+ * @brief   Enables the ADC master/slave mode.
+ */
+#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)
+#define STM32_ADC_DUAL_MODE                 FALSE
+#endif
+
+/**
+ * @brief   Makes the ADC samples type an 8bits one.
+ */
+#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
+#define STM32_ADC_COMPACT_SAMPLES           FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
+#error "ADC3 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC3
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC3"
+#endif
+
+#if STM32_ADC_USE_ADC3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC3 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC3 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC3"
+#endif
+
+#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
+#define STM32_ADC12_CLOCK               STM32_ADC12CLK
+#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC12_CLOCK               (STM32_HCLK / 1)
+#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
+#define STM32_ADC12_CLOCK               (STM32_HCLK / 2)
+#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
+#define STM32_ADC12_CLOCK               (STM32_HCLK / 4)
+#else
+#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
+#endif
+
+#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
+#define STM32_ADC34_CLOCK               STM32_ADC34CLK
+#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC34_CLOCK               (STM32_HCLK / 1)
+#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
+#define STM32_ADC34_CLOCK               (STM32_HCLK / 2)
+#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
+#define STM32_ADC34_CLOCK               (STM32_HCLK / 4)
+#else
+#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
+#endif
+
+#if STM32_ADC12_CLOCK > 72000000
+#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
+#endif
+
+#if STM32_ADC34_CLOCK > 72000000
+#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC sample data type.
+ */
+#if !STM32_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)
+typedef uint16_t adcsample_t;
+#else
+typedef uint8_t adcsample_t;
+#endif
+
+/**
+ * @brief   Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief   Possible ADC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
+  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
+  ADC_ERR_AWD1 = 2,                         /**< Watchdog 1 triggered.      */
+  ADC_ERR_AWD2 = 3,                         /**< Watchdog 2 triggered.      */
+  ADC_ERR_AWD3 = 4                          /**< Watchdog 3 triggered.      */
+} adcerror_t;
+
+/**
+ * @brief   Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief   ADC notification callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] buffer    pointer to the most recent samples data
+ * @param[in] n         number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief   ADC error callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] err       ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief   Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ *          operation.
+ * @note    The use of this configuration structure requires knowledge of
+ *          STM32 ADC cell registers interface, please refer to the STM32
+ *          reference manual for details.
+ */
+typedef struct {
+  /**
+   * @brief   Enables the circular buffer mode for the group.
+   */
+  bool                      circular;
+  /**
+   * @brief   Number of the analog channels belonging to the conversion group.
+   */
+  adc_channels_num_t        num_channels;
+  /**
+   * @brief   Callback function associated to the group or @p NULL.
+   */
+  adccallback_t             end_cb;
+  /**
+   * @brief   Error callback or @p NULL.
+   */
+  adcerrorcallback_t        error_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   ADC CFGR register initialization data.
+   * @note    The bits DMAEN, DMACFG, OVRMOD, CONT are enforced internally
+   *          to the driver, keep them to zero.
+   */
+  uint32_t                  cfgr;
+  /**
+   * @brief   ADC TR1 register initialization data.
+   */
+  uint32_t                  tr1;
+  /**
+   * @brief   ADC CCR register initialization data.
+   * @note    The bits CKMODE, MDMA, DMACFG are enforced internally to the
+   *          driver, keep them to zero.
+   */
+  uint32_t                  ccr;
+  /**
+   * @brief   ADC SMPRx registers initialization data.
+   */
+  uint32_t                  smpr[2];
+  /**
+   * @brief   ADC SQRx register initialization data.
+   */
+  uint32_t                  sqr[4];
+#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
+  /**
+   * @brief   Slave ADC SMPRx registers initialization data.
+   */
+  uint32_t                  ssmpr[2];
+  /**
+   * @brief   Slave ADC SQRx register initialization data.
+   */
+  uint32_t                  ssqr[4];
+#endif /* STM32_ADC_DUAL_MODE */
+} ADCConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  uint32_t                  dummy;
+} ADCConfig;
+
+/**
+ * @brief   Structure representing an ADC driver.
+ */
+struct ADCDriver {
+  /**
+   * @brief   Driver state.
+   */
+  adcstate_t                state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const ADCConfig           *config;
+  /**
+   * @brief   Current samples buffer pointer or @p NULL.
+   */
+  adcsample_t               *samples;
+  /**
+   * @brief   Current samples buffer depth or @p 0.
+   */
+  size_t                    depth;
+  /**
+   * @brief   Current conversion group pointer or @p NULL.
+   */
+  const ADCConversionGroup  *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief   Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief   Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+  ADC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Pointer to the common ADCx_y registers block.
+   */
+  ADC_Common_TypeDef        *adcc;
+  /**
+   * @brief   Pointer to the master ADCx registers block.
+   */
+  ADC_TypeDef               *adcm;
+#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
+  /**
+   * @brief   Pointer to the slave ADCx registers block.
+   */
+  ADC_TypeDef               *adcs;
+#endif /* STM32_ADC_DUAL_MODE */
+  /**
+   * @brief   Pointer to associated DMA channel.
+   */
+  const stm32_dma_stream_t  *dmastp;
+  /**
+   * @brief   DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Threashold register initializer
+ * @{
+ */
+#define ADC_TR(low, high)       (((uint32_t)(high) << 16) | (uint32_t)(low))
+/** @} */
+
+/**
+ * @name    Sequences building helper macros
+ * @{
+ */
+/**
+ * @brief   Number of channels in a conversion sequence.
+ */
+#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 0)
+
+#define ADC_SQR1_SQ1_N(n)       ((n) << 6)  /**< @brief 1st channel in seq. */
+#define ADC_SQR1_SQ2_N(n)       ((n) << 12) /**< @brief 2nd channel in seq. */
+#define ADC_SQR1_SQ3_N(n)       ((n) << 18) /**< @brief 3rd channel in seq. */
+#define ADC_SQR1_SQ4_N(n)       ((n) << 24) /**< @brief 4th channel in seq. */
+
+#define ADC_SQR2_SQ5_N(n)       ((n) << 0)  /**< @brief 5th channel in seq. */
+#define ADC_SQR2_SQ6_N(n)       ((n) << 6)  /**< @brief 6th channel in seq. */
+#define ADC_SQR2_SQ7_N(n)       ((n) << 12) /**< @brief 7th channel in seq. */
+#define ADC_SQR2_SQ8_N(n)       ((n) << 18) /**< @brief 8th channel in seq. */
+#define ADC_SQR2_SQ9_N(n)       ((n) << 24) /**< @brief 9th channel in seq. */
+
+#define ADC_SQR3_SQ10_N(n)      ((n) << 0)  /**< @brief 10th channel in seq.*/
+#define ADC_SQR3_SQ11_N(n)      ((n) << 6)  /**< @brief 11th channel in seq.*/
+#define ADC_SQR3_SQ12_N(n)      ((n) << 12) /**< @brief 12th channel in seq.*/
+#define ADC_SQR3_SQ13_N(n)      ((n) << 18) /**< @brief 13th channel in seq.*/
+#define ADC_SQR3_SQ14_N(n)      ((n) << 24) /**< @brief 14th channel in seq.*/
+
+#define ADC_SQR4_SQ15_N(n)      ((n) << 0)  /**< @brief 15th channel in seq.*/
+#define ADC_SQR4_SQ16_N(n)      ((n) << 6)  /**< @brief 16th channel in seq.*/
+/** @} */
+
+/**
+ * @name    Sampling rate settings helper macros
+ * @{
+ */
+#define ADC_SMPR1_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
+#define ADC_SMPR1_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
+#define ADC_SMPR1_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
+#define ADC_SMPR1_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
+#define ADC_SMPR1_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
+#define ADC_SMPR1_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
+#define ADC_SMPR1_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
+#define ADC_SMPR1_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
+#define ADC_SMPR1_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
+
+#define ADC_SMPR2_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
+#define ADC_SMPR2_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
+#define ADC_SMPR2_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
+#define ADC_SMPR2_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
+#define ADC_SMPR2_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
+#define ADC_SMPR2_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
+#define ADC_SMPR2_SMP_AN16(n)   ((n) << 18) /**< @brief AN16 sampling time. */
+#define ADC_SMPR2_SMP_AN17(n)   ((n) << 21) /**< @brief AN17 sampling time. */
+#define ADC_SMPR2_SMP_AN18(n)   ((n) << 24) /**< @brief AN18 sampling time. */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adc_lld_init(void);
+  void adc_lld_start(ADCDriver *adcp);
+  void adc_lld_stop(ADCDriver *adcp);
+  void adc_lld_start_conversion(ADCDriver *adcp);
+  void adc_lld_stop_conversion(ADCDriver *adcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/ext_lld_isr.c b/os/hal/ports/STM32/STM32F30x/ext_lld_isr.c
new file mode 100644
index 000000000..08af37b19
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F30x/ext_lld_isr.c
@@ -0,0 +1,402 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F30x/ext_lld_isr.c
+ * @brief   STM32F30x EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if !defined(STM32_DISABLE_EXTI0_HANDLER)
+/**
+ * @brief   EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 0);
+  EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI1_HANDLER)
+/**
+ * @brief   EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 1);
+  EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI2_HANDLER)
+/**
+ * @brief   EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 2);
+  EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI3_HANDLER)
+/**
+ * @brief   EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 3);
+  EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI4_HANDLER)
+/**
+ * @brief   EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 4);
+  EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
+/**
+ * @brief   EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
+  EXTI->PR = pr;
+  if (pr & (1 << 5))
+    EXTD1.config->channels[5].cb(&EXTD1, 5);
+  if (pr & (1 << 6))
+    EXTD1.config->channels[6].cb(&EXTD1, 6);
+  if (pr & (1 << 7))
+    EXTD1.config->channels[7].cb(&EXTD1, 7);
+  if (pr & (1 << 8))
+    EXTD1.config->channels[8].cb(&EXTD1, 8);
+  if (pr & (1 << 9))
+    EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
+/**
+ * @brief   EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
+                   (1 << 15));
+  EXTI->PR = pr;
+  if (pr & (1 << 10))
+    EXTD1.config->channels[10].cb(&EXTD1, 10);
+  if (pr & (1 << 11))
+    EXTD1.config->channels[11].cb(&EXTD1, 11);
+  if (pr & (1 << 12))
+    EXTD1.config->channels[12].cb(&EXTD1, 12);
+  if (pr & (1 << 13))
+    EXTD1.config->channels[13].cb(&EXTD1, 13);
+  if (pr & (1 << 14))
+    EXTD1.config->channels[14].cb(&EXTD1, 14);
+  if (pr & (1 << 15))
+    EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI16_HANDLER)
+/**
+ * @brief   EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 16);
+  EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI17_HANDLER)
+/**
+ * @brief   EXTI[17] interrupt handler (RTC Alarm).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 17);
+  EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI18_HANDLER)
+/**
+ * @brief   EXTI[18] interrupt handler (USB Wakeup).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE8) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 18);
+  EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI19_HANDLER)
+/**
+ * @brief   EXTI[19] interrupt handler (Tamper TimeStamp).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 19);
+  EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI20_HANDLER)
+/**
+ * @brief   EXTI[20] interrupt handler (RTC Wakeup).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 20);
+  EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER)
+/**
+ * @brief   EXTI[21],EXTI[22],EXTI[29] interrupt handler (COMP1, COMP2, COMP3).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector140) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 21) | (1 << 22) | (1 << 29));
+  EXTI->PR = pr;
+  if (pr & (1 << 21))
+    EXTD1.config->channels[21].cb(&EXTD1, 21);
+  if (pr & (1 << 22))
+    EXTD1.config->channels[22].cb(&EXTD1, 22);
+  if (pr & (1 << 29))
+    EXTD1.config->channels[29].cb(&EXTD1, 29);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI30_32_HANDLER)
+/**
+ * @brief   EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector144) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 30) | (1 << 31));
+  EXTI->PR = pr;
+  if (pr & (1 << 30))
+    EXTD1.config->channels[30].cb(&EXTD1, 30);
+  if (pr & (1 << 31))
+    EXTD1.config->channels[31].cb(&EXTD1, 31);
+
+  pr = EXTI->PR2 & (1 << 0);
+  EXTI->PR2 = pr;
+  if (pr & (1 << 0))
+    EXTD1.config->channels[32].cb(&EXTD1, 32);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI33_HANDLER)
+/**
+ * @brief   EXTI[33] interrupt handler (COMP7).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR2 = (1 << 1);
+  EXTD1.config->channels[33].cb(&EXTD1, 33);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+  nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+  nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+  nvicEnableVector(EXTI2_TS_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+  nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+  nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+  nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+  nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+  nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+  nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+  nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+  nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+  nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+  nvicEnableVector(COMP1_2_3_IRQn, STM32_EXT_EXTI21_22_29_IRQ_PRIORITY);
+  nvicEnableVector(COMP4_5_6_IRQn, STM32_EXT_EXTI30_32_IRQ_PRIORITY);
+  nvicEnableVector(COMP7_IRQn, STM32_EXT_EXTI33_IRQ_PRIORITY);
+}
+
+/**
+ * @brief   Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+  nvicDisableVector(EXTI0_IRQn);
+  nvicDisableVector(EXTI1_IRQn);
+  nvicDisableVector(EXTI2_TS_IRQn);
+  nvicDisableVector(EXTI3_IRQn);
+  nvicDisableVector(EXTI4_IRQn);
+  nvicDisableVector(EXTI9_5_IRQn);
+  nvicDisableVector(EXTI15_10_IRQn);
+  nvicDisableVector(PVD_IRQn);
+  nvicDisableVector(RTC_Alarm_IRQn);
+  nvicDisableVector(USBWakeUp_IRQn);
+  nvicDisableVector(TAMPER_STAMP_IRQn);
+  nvicDisableVector(RTC_WKUP_IRQn);
+  nvicDisableVector(COMP1_2_3_IRQn);
+  nvicDisableVector(COMP4_5_6_IRQn);
+  nvicDisableVector(COMP7_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F30x/ext_lld_isr.h b/os/hal/ports/STM32/STM32F30x/ext_lld_isr.h
index 42f1e30fe..42f1e30fe 100644
--- a/os/hal/platforms/STM32F30x/ext_lld_isr.h
+++ b/os/hal/ports/STM32/STM32F30x/ext_lld_isr.h
diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.c b/os/hal/ports/STM32/STM32F30x/hal_lld.c
new file mode 100644
index 000000000..46561dc76
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F30x/hal_lld.c
@@ -0,0 +1,197 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F30x/hal_lld.c
+ * @brief   STM32F30x HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the backup domain.
+ * @note    WARNING! Changing clock source impossible without resetting
+ *          of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+  /* Backup domain access enabled and left open.*/
+  PWR->CR |= PWR_CR_DBP;
+
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0;
+  }
+
+  /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+#if defined(STM32_LSE_BYPASS)
+  /* LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+  /* No LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                     /* Waits until LSE is stable.   */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+    /* Selects clock source.*/
+    RCC->BDCR |= STM32_RTCSEL;
+
+    /* RTC clock enabled.*/
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+  /* Reset of all peripherals.*/
+  rccResetAPB1(0xFFFFFFFF);
+  rccResetAPB2(0xFFFFFFFF);
+
+  /* PWR clock enabled.*/
+  rccEnablePWRInterface(FALSE);
+
+  /* Initializes the backup domain.*/
+  hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+  dmaInit();
+#endif
+
+  /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+
+  /* USB IRQ relocated to not conflict with CAN.*/
+  SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
+}
+
+/**
+ * @brief   STM32 clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* HSI setup, it enforces the reset situation in order to handle possible
+     problems with JTAG probes and re-initializations.*/
+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;                                       /* Wait until HSI is stable.    */
+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
+  RCC->CFGR = 0;                            /* CFGR reset value.            */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;                                       /* Waits until HSI is selected. */
+
+#if STM32_HSE_ENABLED
+  /* HSE activation.*/
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+  /* No HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON;
+#endif
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;                                       /* Waits until HSE is stable.   */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                                       /* Waits until LSI is stable.   */
+#endif
+
+  /* Clock settings.*/
+  RCC->CFGR  = STM32_MCOSEL    | STM32_USBPRE    | STM32_PLLMUL   |
+               STM32_PLLSRC    | STM32_PPRE1     | STM32_PPRE2    |
+               STM32_HPRE;
+  RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;
+  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |
+               STM32_USART2SW  | STM32_TIM8SW    | STM32_TIM1SW   |
+               STM32_I2C2SW    | STM32_I2C1SW    | STM32_USART1SW;
+
+#if STM32_ACTIVATE_PLL
+  /* PLL activation.*/
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                                       /* Waits until PLL is stable.   */
+#endif
+
+  /* Flash setup and final clock selection.   */
+  FLASH->ACR = STM32_FLASHBITS;
+
+  /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+  /* Switches clock source.*/
+  RCC->CFGR |= STM32_SW;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;                                       /* Waits selection complete.    */
+#endif
+#endif /* !STM32_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.h b/os/hal/ports/STM32/STM32F30x/hal_lld.h
new file mode 100644
index 000000000..eb046a7b7
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F30x/hal_lld.h
@@ -0,0 +1,1099 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F30x/hal_lld.h
+ * @brief   STM32F30x HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - STM32_LSECLK.
+ *          - STM32_LSEDRV.
+ *          - STM32_LSE_BYPASS (optionally).
+ *          - STM32_HSECLK.
+ *          - STM32_HSE_BYPASS (optionally).
+ *          .
+ *          One of the following macros must also be defined:
+ *          - STM32F30X for Analog & DSP devices.
+ *          .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+#define PLATFORM_NAME           "STM32F30x Analog & DSP"
+/** @} */
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX        72000000
+
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        32000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        1000000
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        1000000
+
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX         24000000
+
+/**
+ * @brief   Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN         1000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX        72000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN        16000000
+
+/**
+ * @brief   Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX         36000000
+
+/**
+ * @brief   Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX         72000000
+
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX        72000000
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK            8000000     /**< High speed internal clock. */
+#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
+/** @} */
+
+/**
+ * @name    PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
+#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
+#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
+#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
+#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
+
+#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
+
+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI/2. */
+#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is
+                                                 HSE/PREDIV.                */
+
+#define STM32_USBPRE_DIV1P5     (0 << 22)   /**< USB clock is PLLCLK/1.5.   */
+#define STM32_USBPRE_DIV1       (1 << 22)   /**< USB clock is PLLCLK/1.     */
+
+#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_LSI        (2 << 24)   /**< LSI clock on MCO pin.      */
+#define STM32_MCOSEL_LSE        (3 << 24)   /**< LSE clock on MCO pin.      */
+#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
+/** @} */
+
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
+#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
+#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
+#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
+#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 32 used as
+                                                 RTC clock.                 */
+/** @} */
+
+/**
+ * @name    RCC_CFGR2 register bits definitions
+ * @{
+ */
+#define STM32_PREDIV_MASK       (15 << 0)   /**< PREDIV divisor mask.       */
+#define STM32_ADC12PRES_MASK    (31 << 4)   /**< ADC12 clock source mask.   */
+#define STM32_ADC12PRES_NOCLOCK (0 << 4)    /**< ADC12 clock is disabled.   */
+#define STM32_ADC12PRES_DIV1    (16 << 4)   /**< ADC12 clock is PLL/1.      */
+#define STM32_ADC12PRES_DIV2    (17 << 4)   /**< ADC12 clock is PLL/2.      */
+#define STM32_ADC12PRES_DIV4    (18 << 4)   /**< ADC12 clock is PLL/4.      */
+#define STM32_ADC12PRES_DIV6    (19 << 4)   /**< ADC12 clock is PLL/6.      */
+#define STM32_ADC12PRES_DIV8    (20 << 4)   /**< ADC12 clock is PLL/8.      */
+#define STM32_ADC12PRES_DIV10   (21 << 4)   /**< ADC12 clock is PLL/10.     */
+#define STM32_ADC12PRES_DIV12   (22 << 4)   /**< ADC12 clock is PLL/12.     */
+#define STM32_ADC12PRES_DIV16   (23 << 4)   /**< ADC12 clock is PLL/16.     */
+#define STM32_ADC12PRES_DIV32   (24 << 4)   /**< ADC12 clock is PLL/32.     */
+#define STM32_ADC12PRES_DIV64   (25 << 4)   /**< ADC12 clock is PLL/64.     */
+#define STM32_ADC12PRES_DIV128  (26 << 4)   /**< ADC12 clock is PLL/128.    */
+#define STM32_ADC12PRES_DIV256  (27 << 4)   /**< ADC12 clock is PLL/256.    */
+#define STM32_ADC34PRES_MASK    (31 << 9)   /**< ADC34 clock source mask.   */
+#define STM32_ADC34PRES_NOCLOCK (0 << 9)    /**< ADC34 clock is disabled.   */
+#define STM32_ADC34PRES_DIV1    (16 << 9)   /**< ADC34 clock is PLL/1.      */
+#define STM32_ADC34PRES_DIV2    (17 << 9)   /**< ADC34 clock is PLL/2.      */
+#define STM32_ADC34PRES_DIV4    (18 << 9)   /**< ADC34 clock is PLL/4.      */
+#define STM32_ADC34PRES_DIV6    (19 << 9)   /**< ADC34 clock is PLL/6.      */
+#define STM32_ADC34PRES_DIV8    (20 << 9)   /**< ADC34 clock is PLL/8.      */
+#define STM32_ADC34PRES_DIV10   (21 << 9)   /**< ADC34 clock is PLL/10.     */
+#define STM32_ADC34PRES_DIV12   (22 << 9)   /**< ADC34 clock is PLL/12.     */
+#define STM32_ADC34PRES_DIV16   (23 << 9)   /**< ADC34 clock is PLL/16.     */
+#define STM32_ADC34PRES_DIV32   (24 << 9)   /**< ADC34 clock is PLL/32.     */
+#define STM32_ADC34PRES_DIV64   (25 << 9)   /**< ADC34 clock is PLL/64.     */
+#define STM32_ADC34PRES_DIV128  (26 << 9)   /**< ADC34 clock is PLL/128.    */
+#define STM32_ADC34PRES_DIV256  (27 << 9)   /**< ADC34 clock is PLL/256.    */
+/** @} */
+
+/**
+ * @name    RCC_CFGR3 register bits definitions
+ * @{
+ */
+#define STM32_USART1SW_MASK     (3 << 0)    /**< USART1 clock source mask. */
+#define STM32_USART1SW_PCLK     (0 << 0)    /**< USART1 clock is PCLK.     */
+#define STM32_USART1SW_SYSCLK   (1 << 0)    /**< USART1 clock is SYSCLK.   */
+#define STM32_USART1SW_LSE      (2 << 0)    /**< USART1 clock is LSE.      */
+#define STM32_USART1SW_HSI      (3 << 0)    /**< USART1 clock is HSI.      */
+#define STM32_I2C1SW_MASK       (1 << 4)    /**< I2C1 clock source mask.   */
+#define STM32_I2C1SW_HSI        (0 << 4)    /**< I2C1 clock is HSI.        */
+#define STM32_I2C1SW_SYSCLK     (1 << 4)    /**< I2C1 clock is SYSCLK.     */
+#define STM32_I2C2SW_MASK       (1 << 5)    /**< I2C2 clock source mask.   */
+#define STM32_I2C2SW_HSI        (0 << 5)    /**< I2C2 clock is HSI.        */
+#define STM32_I2C2SW_SYSCLK     (1 << 5)    /**< I2C2 clock is SYSCLK.     */
+#define STM32_TIM1SW_MASK       (1 << 8)    /**< TIM1 clock source mask.   */
+#define STM32_TIM1SW_PCLK2      (0 << 8)    /**< TIM1 clock is PCLK2.      */
+#define STM32_TIM1SW_PLLX2      (1 << 8)    /**< TIM1 clock is PLL*2.      */
+#define STM32_TIM8SW_MASK       (1 << 9)    /**< TIM8 clock source mask.   */
+#define STM32_TIM8SW_PCLK2      (0 << 9)    /**< TIM8 clock is PCLK2.      */
+#define STM32_TIM8SW_PLLX2      (1 << 9)    /**< TIM8 clock is PLL*2.      */
+#define STM32_USART2SW_MASK     (3 << 16)   /**< USART2 clock source mask. */
+#define STM32_USART2SW_PCLK     (0 << 16)   /**< USART2 clock is PCLK.     */
+#define STM32_USART2SW_SYSCLK   (1 << 16)   /**< USART2 clock is SYSCLK.   */
+#define STM32_USART2SW_LSE      (2 << 16)   /**< USART2 clock is LSE.      */
+#define STM32_USART2SW_HSI      (3 << 16)   /**< USART2 clock is HSI.      */
+#define STM32_USART3SW_MASK     (3 << 18)   /**< USART3 clock source mask. */
+#define STM32_USART3SW_PCLK     (0 << 18)   /**< USART3 clock is PCLK.     */
+#define STM32_USART3SW_SYSCLK   (1 << 18)   /**< USART3 clock is SYSCLK.   */
+#define STM32_USART3SW_LSE      (2 << 18)   /**< USART3 clock is LSE.      */
+#define STM32_USART3SW_HSI      (3 << 18)   /**< USART3 clock is HSI.      */
+#define STM32_UART4SW_MASK      (3 << 20)   /**< USART4 clock source mask. */
+#define STM32_UART4SW_PCLK      (0 << 20)   /**< USART4 clock is PCLK.     */
+#define STM32_UART4SW_SYSCLK    (1 << 20)   /**< USART4 clock is SYSCLK.   */
+#define STM32_UART4SW_LSE       (2 << 20)   /**< USART4 clock is LSE.      */
+#define STM32_UART4SW_HSI       (3 << 20)   /**< USART4 clock is HSI.      */
+#define STM32_UART5SW_MASK      (3 << 22)   /**< USART5 clock source mask. */
+#define STM32_UART5SW_PCLK      (0 << 22)   /**< USART5 clock is PCLK.     */
+#define STM32_UART5SW_SYSCLK    (1 << 22)   /**< USART5 clock is SYSCLK.   */
+#define STM32_UART5SW_LSE       (2 << 22)   /**< USART5 clock is LSE.      */
+#define STM32_UART5SW_HSI       (3 << 22)   /**< USART5 clock is HSI.      */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT                       FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE                    FALSE
+#endif
+
+/**
+ * @brief   Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                           STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief   Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED                   TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED                   TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED                   TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED                   FALSE
+#endif
+
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                            STM32_SW_PLL
+#endif
+
+/**
+ * @brief   Clock source for the PLL.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                        STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief   Crystal PLL pre-divider.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PREDIV_VALUE                  1
+#endif
+
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed range is 2...16.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE                  9
+#endif
+
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                          STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1                         STM32_PPRE1_DIV2
+#endif
+
+/**
+ * @brief   APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2                         STM32_PPRE2_DIV2
+#endif
+
+/**
+ * @brief   MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief   ADC12 prescaler value.
+ */
+#if !defined(STM32_ADC12PRES) || defined(__DOXYGEN__)
+#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV1
+#endif
+
+/**
+ * @brief   ADC34 prescaler value.
+ */
+#if !defined(STM32_ADC34PRES) || defined(__DOXYGEN__)
+#define STM32_ADC34PRES                     STM32_ADC34PRES_DIV1
+#endif
+
+/**
+ * @brief   USART1 clock source.
+ */
+#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
+#define STM32_USART1SW                      STM32_USART1SW_PCLK
+#endif
+
+/**
+ * @brief   USART2 clock source.
+ */
+#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
+#define STM32_USART2SW                      STM32_USART2SW_PCLK
+#endif
+
+/**
+ * @brief   USART3 clock source.
+ */
+#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
+#define STM32_USART3SW                      STM32_USART3SW_PCLK
+#endif
+
+/**
+ * @brief   UART4 clock source.
+ */
+#if !defined(STM32_UART4SW) || defined(__DOXYGEN__)
+#define STM32_UART4SW                       STM32_UART4SW_PCLK
+#endif
+
+/**
+ * @brief   UART5 clock source.
+ */
+#if !defined(STM32_UART5SW) || defined(__DOXYGEN__)
+#define STM32_UART5SW                       STM32_UART5SW_PCLK
+#endif
+
+/**
+ * @brief   I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
+#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK
+#endif
+
+/**
+ * @brief   I2C2 clock source.
+ */
+#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
+#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK
+#endif
+
+/**
+ * @brief   TIM1 clock source.
+ */
+#if !defined(STM32_TIM1SW) || defined(__DOXYGEN__)
+#define STM32_TIM1SW                        STM32_TIM1SW_PCLK2
+#endif
+
+/**
+ * @brief   TIM8 clock source.
+ */
+#if !defined(STM32_TIM8SW) || defined(__DOXYGEN__)
+#define STM32_TIM8SW                        STM32_TIM8SW_PCLK2
+#endif
+
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                        STM32_RTCSEL_LSI
+#endif
+
+/**
+ * @brief   USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_REQUIRED            TRUE
+#endif
+
+/**
+ * @brief   USB prescaler initialization.
+ */
+#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
+#define STM32_USBPRE                        STM32_USBPRE_DIV1P5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F30x_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F30x_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_HSI
+#error "HSI not enabled, required by STM32_USART1SW"
+#endif
+
+#if STM32_USART2SW == STM32_USART2SW_HSI
+#error "HSI not enabled, required by STM32_USART2SW"
+#endif
+
+#if STM32_USART3SW == STM32_USART3SW_HSI
+#error "HSI not enabled, required by STM32_USART3SW"
+#endif
+
+#if STM32_UART4SW == STM32_UART4SW_HSI
+#error "HSI not enabled, required by STM32_UART4SW"
+#endif
+
+#if STM32_UART5SW == STM32_UART5SW_HSI
+#error "HSI not enabled, required by STM32_UART5SW"
+#endif
+
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#error "HSI not enabled, required by STM32_I2C1SW"
+#endif
+
+#if STM32_I2C2SW == STM32_I2C2SW_HSI
+#error "HSI not enabled, required by STM32_I2C2SW"
+#endif
+
+#if STM32_TIM1SW == STM32_TIM1SW_HSI
+#error "HSI not enabled, required by STM32_TIM1SW"
+#endif
+
+#if STM32_TIM8SW == STM32_TIM8SW_HSI
+#error "HSI not enabled, required by STM32_TIM8SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0)
+#error "STM32_LSECLK not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined"
+#endif
+
+#if (STM32_LSEDRV >> 3) > 3
+#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_LSE
+#error "LSE not enabled, required by STM32_USART1SW"
+#endif
+
+#if STM32_USART2SW == STM32_USART2SW_LSE
+#error "LSE not enabled, required by STM32_USART2SW"
+#endif
+
+#if STM32_USART3SW == STM32_USART3SW_LSE
+#error "LSE not enabled, required by STM32_USART3SW"
+#endif
+
+#if STM32_UART4SW == STM32_UART4SW_LSE
+#error "LSE not enabled, required by STM32_UART4SW"
+#endif
+
+#if STM32_UART5SW == STM32_UART5SW_LSE
+#error "LSE not enabled, required by STM32_UART5SW"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
+    (STM32_TIM1SW == STM32_TIM1SW_PLLX2) ||                                 \
+    (STM32_TIM8SW == STM32_TIM8SW_PLLX2) ||                                 \
+    (STM32_ADC12PRES != STM32_ADC12PRES_NOCLOCK) ||                         \
+    (STM32_ADC34PRES != STM32_ADC34PRES_NOCLOCK) ||                         \
+    STM32_USB_CLOCK_REQUIRED ||                                             \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+
+/* HSE prescaler setting check.*/
+#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
+#define STM32_PREDIV                ((STM32_PREDIV_VALUE - 1) << 0)
+#else
+#error "invalid STM32_PREDIV value specified"
+#endif
+
+/**
+ * @brief   PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PREDIV_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                  (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                  (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                  (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                  (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                  (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                  (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                  (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                  (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                  (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                  (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                (STM32_HSECLK / 32)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK                0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief   ADC12 frequency.
+ */
+#if (STM32_ADC12PRES == STM32_ADC12PRES_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_ADC12CLK              0
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV1
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 1)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV2
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 2)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV4
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 4)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV6
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 6)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV8
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 8)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV10
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 10)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV12
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 12)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV16
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 16)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV32
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 32)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV64
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 64)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV128
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 128)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV256
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 256)
+#else
+#error "invalid STM32_ADC12PRES value specified"
+#endif
+
+/**
+ * @brief   ADC34 frequency.
+ */
+#if (STM32_ADC43PRES == STM32_ADC34PRES_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_ADC34CLK              0
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV1
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 1)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV2
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 2)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV4
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 4)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV6
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 6)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV8
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 8)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV10
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 10)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV12
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 12)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV16
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 16)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV32
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 32)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV64
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 64)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV128
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 128)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV256
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 256)
+#else
+#error "invalid STM32_ADC34PRES value specified"
+#endif
+
+/* ADC12 frequency check.*/
+#if STM32_ADC12CLK > STM32_ADCCLK_MAX
+#error "STM32_ADC12CLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/* ADC34 frequency check.*/
+#if STM32_ADC34CLK > STM32_ADCCLK_MAX
+#error "STM32_ADC34CLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/**
+ * @brief   I2C1 frequency.
+ */
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#define STM32_I2C1CLK               STM32_HSICLK
+#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
+#define STM32_I2C1CLK               STM32_SYSCLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief   I2C2 frequency.
+ */
+#if STM32_I2C2SW == STM32_I2C2SW_HSI
+#define STM32_I2C2CLK               STM32_HSICLK
+#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK
+#define STM32_I2C2CLK               STM32_SYSCLK
+#else
+#error "invalid source selected for I2C2 clock"
+#endif
+
+/**
+ * @brief   USART1 frequency.
+ */
+#if STM32_USART1SW == STM32_USART1SW_PCLK
+#define STM32_USART1CLK             STM32_PCLK2
+#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
+#define STM32_USART1CLK             STM32_SYSCLK
+#elif STM32_USART1SW == STM32_USART1SW_LSECLK
+#define STM32_USART1CLK             STM32_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_HSICLK
+#define STM32_USART1CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief   USART2 frequency.
+ */
+#if STM32_USART2SW == STM32_USART2SW_PCLK
+#define STM32_USART2CLK             STM32_PCLK1
+#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
+#define STM32_USART2CLK             STM32_SYSCLK
+#elif STM32_USART2SW == STM32_USART2SW_LSECLK
+#define STM32_USART2CLK             STM32_LSECLK
+#elif STM32_USART2SW == STM32_USART2SW_HSICLK
+#define STM32_USART2CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART2 clock"
+#endif
+
+/**
+ * @brief   USART3 frequency.
+ */
+#if STM32_USART3SW == STM32_USART3SW_PCLK
+#define STM32_USART3CLK             STM32_PCLK1
+#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
+#define STM32_USART3CLK             STM32_SYSCLK
+#elif STM32_USART3SW == STM32_USART3SW_LSECLK
+#define STM32_USART3CLK             STM32_LSECLK
+#elif STM32_USART3SW == STM32_USART3SW_HSICLK
+#define STM32_USART3CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART3 clock"
+#endif
+
+/**
+ * @brief   UART4 frequency.
+ */
+#if STM32_UART4SW == STM32_UART4SW_PCLK
+#define STM32_UART4CLK             STM32_PCLK1
+#elif STM32_UART4SW == STM32_UART4SW_SYSCLK
+#define STM32_UART4CLK             STM32_SYSCLK
+#elif STM32_UART4SW == STM32_UART4SW_LSECLK
+#define STM32_UART4CLK             STM32_LSECLK
+#elif STM32_UART4SW == STM32_UART4SW_HSICLK
+#define STM32_UART4CLK             STM32_HSICLK
+#else
+#error "invalid source selected for UART4 clock"
+#endif
+
+/**
+ * @brief   UART5 frequency.
+ */
+#if STM32_UART5SW == STM32_UART5SW_PCLK
+#define STM32_UART5CLK             STM32_PCLK1
+#elif STM32_UART5SW == STM32_UART5SW_SYSCLK
+#define STM32_UART5CLK             STM32_SYSCLK
+#elif STM32_UART5SW == STM32_UART5SW_LSECLK
+#define STM32_UART5CLK             STM32_LSECLK
+#elif STM32_UART5SW == STM32_UART5SW_HSICLK
+#define STM32_UART5CLK             STM32_HSICLK
+#else
+#error "invalid source selected for UART5 clock"
+#endif
+
+/**
+ * @brief   TIM1 frequency.
+ */
+#if STM32_TIM1SW == STM32_TIM1SW_PCLK2
+#define STM32_TIM1CLK               STM32_PCLK2
+#elif STM32_TIM1SW == STM32_TIM1SW_PLLX2
+#define STM32_TIM1CLK               (STM32_PLLCLKOUT * 2)
+#else
+#error "invalid source selected for TIM1 clock"
+#endif
+
+/**
+ * @brief   TIM8 frequency.
+ */
+#if STM32_TIM8SW == STM32_TIM8SW_PCLK2
+#define STM32_TIM8CLK               STM32_PCLK2
+#elif STM32_TIM8SW == STM32_TIM8SW_PLLX2
+#define STM32_TIM8CLK               (STM32_PLLCLKOUT * 2)
+#else
+#error "invalid source selected for TIM8 clock"
+#endif
+
+/**
+ * @brief   Timers 2, 3, 4, 6, 7 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief   Timers 1, 8, 15, 16, 17 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief   USB frequency.
+ */
+#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
+#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
+#define STM32_USBCLK                STM32_PLLCLKOUT
+#else
+#error "invalid STM32_USBPRE value specified"
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS             0x00000011
+#else
+#define STM32_FLASHBITS             0x00000012
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/platform.mk b/os/hal/ports/STM32/STM32F30x/platform.mk
new file mode 100644
index 000000000..f24aee535
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F30x/platform.mk
@@ -0,0 +1,31 @@
+# List of all the STM32F30x platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x/stm32_dma.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x/hal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x/adc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/can_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/ext_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1
diff --git a/os/hal/ports/STM32/STM32F30x/stm32_dma.c b/os/hal/ports/STM32/STM32F30x/stm32_dma.c
new file mode 100644
index 000000000..e18f2f4e1
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F30x/stm32_dma.c
@@ -0,0 +1,449 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F30x/stm32_dma.c
+ * @brief   DMA helper driver code.
+ *
+ * @addtogroup STM32F30x_DMA
+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a
+ *          shared resource, this driver allows to allocate and free DMA
+ *          streams at runtime in order to allow all the other device
+ *          drivers to coordinate the access to the resource.
+ * @note    The DMA ISR handlers are all declared into this module because
+ *          sharing, the various device drivers can associate a callback to
+ *          ISRs when allocating streams.
+ * @{
+ */
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA1_STREAMS_MASK     0x0000007F
+
+/**
+ * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA2_STREAMS_MASK     0x00000F80
+
+/**
+ * @brief   Post-reset value of the stream CCR register.
+ */
+#define STM32_DMA_CCR_RESET_VALUE   0x00000000
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ *          identifier and the involved physical registers.
+ * @note    Don't use this array directly, use the appropriate wrapper macros
+ *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
+ */
+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
+  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
+  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
+  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
+  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
+  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
+  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
+  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
+  {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
+  {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
+  {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
+  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
+  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
+};
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA ISR redirector type.
+ */
+typedef struct {
+  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
+  void                  *dma_param;     /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
+/**
+ * @brief   Mask of the allocated streams.
+ */
+static uint32_t dma_streams_mask;
+
+/**
+ * @brief   DMA IRQ redirectors.
+ */
+static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA1 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector6C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 0;
+  if (dma_isr_redir[0].dma_func)
+    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 4;
+  if (dma_isr_redir[1].dma_func)
+    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector74) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 8;
+  if (dma_isr_redir[2].dma_func)
+    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector78) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 12;
+  if (dma_isr_redir[3].dma_func)
+    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector7C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 16;
+  if (dma_isr_redir[4].dma_func)
+    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 6 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector80) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 20;
+  if (dma_isr_redir[5].dma_func)
+    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 7 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector84) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 24;
+  if (dma_isr_redir[6].dma_func)
+    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector120) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 0;
+  if (dma_isr_redir[7].dma_func)
+    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector124) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 4;
+  if (dma_isr_redir[8].dma_func)
+    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector128) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 8;
+  if (dma_isr_redir[9].dma_func)
+    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector12C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 12;
+  if (dma_isr_redir[10].dma_func)
+    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector130) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 16;
+  if (dma_isr_redir[11].dma_func)
+    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+  int i;
+
+  dma_streams_mask = 0;
+  for (i = 0; i < STM32_DMA_STREAMS; i++) {
+    _stm32_dma_streams[i].channel->CCR = 0;
+    dma_isr_redir[i].dma_func = NULL;
+  }
+  DMA1->IFCR = 0xFFFFFFFF;
+#if STM32_HAS_DMA2
+  DMA2->IFCR = 0xFFFFFFFF;
+#endif
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ * @pre     The stream must not be already in use or an error is returned.
+ * @post    The stream is allocated and the default ISR handler redirected
+ *          to the specified function.
+ * @post    The stream ISR vector is enabled and its priority configured.
+ * @post    The stream must be freed using @p dmaStreamRelease() before it can
+ *          be reused with another peripheral.
+ * @post    The stream is in its post-reset state.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] priority  IRQ priority mask for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              The operation status.
+ * @retval FALSE        no error, stream taken.
+ * @retval TRUE         error, stream already taken.
+ *
+ * @special
+ */
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                       uint32_t priority,
+                       stm32_dmaisr_t func,
+                       void *param) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Checks if the stream is already taken.*/
+  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
+    return TRUE;
+
+  /* Marks the stream as allocated.*/
+  dma_isr_redir[dmastp->selfindex].dma_func  = func;
+  dma_isr_redir[dmastp->selfindex].dma_param = param;
+  dma_streams_mask |= (1 << dmastp->selfindex);
+
+  /* Enabling DMA clocks required by the current streams set.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
+    rccEnableDMA1(FALSE);
+#if STM32_HAS_DMA2
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
+    rccEnableDMA2(FALSE);
+#endif
+
+  /* Putting the stream in a safe state.*/
+  dmaStreamDisable(dmastp);
+  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
+
+  /* Enables the associated IRQ vector if a callback is defined.*/
+  if (func != NULL)
+    nvicEnableVector(dmastp->vector, priority);
+
+  return FALSE;
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    The stream is again available.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Check if the streams is not taken.*/
+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+                "not allocated");
+
+  /* Disables the associated IRQ vector.*/
+  nvicDisableVector(dmastp->vector);
+
+  /* Marks the stream as not allocated.*/
+  dma_streams_mask &= ~(1 << dmastp->selfindex);
+
+  /* Shutting down clocks that are no more required, if any.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
+    rccDisableDMA1(FALSE);
+#if STM32_HAS_DMA2
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
+    rccDisableDMA2(FALSE);
+#endif
+}
+
+#endif /* STM32_DMA_REQUIRED */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/stm32_dma.h b/os/hal/ports/STM32/STM32F30x/stm32_dma.h
new file mode 100644
index 000000000..21c97a38b
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F30x/stm32_dma.h
@@ -0,0 +1,406 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F30x/stm32_dma.h
+ * @brief   DMA helper driver header.
+ * @note    This file requires definitions from the ST header file stm32f30x.h.
+ * @note    This driver uses the new naming convention used for the STM32F2xx
+ *          so the "DMA channels" are referred as "DMA streams".
+ *
+ * @addtogroup STM32F30x_DMA
+ * @{
+ */
+
+#ifndef _STM32_DMA_H_
+#define _STM32_DMA_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Total number of DMA streams.
+ * @note    This is the total number of streams among all the DMA units.
+ */
+#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
+#define STM32_DMA_STREAMS           12
+#else
+#define STM32_DMA_STREAMS           7
+#endif
+
+/**
+ * @brief   Mask of the ISR bits passed to the DMA callback functions.
+ */
+#define STM32_DMA_ISR_MASK          0x0F
+
+/**
+ * @brief   Returns the channel associated to the specified stream.
+ *
+ * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
+ * @param[in] c         a stream/channel association word, one channel per
+ *                      nibble, not associated channels must be set to 0xF
+ * @return              Always zero, in this platform there is no dynamic
+ *                      association between streams and channels.
+ */
+#define STM32_DMA_GETCHANNEL(n, c)  0
+
+/**
+ * @brief   Checks if a DMA priority is within the valid range.
+ * @param[in] prio      DMA priority
+ *
+ * @retval              The check result.
+ * @retval FALSE        invalid DMA priority.
+ * @retval TRUE         correct DMA priority.
+ */
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+
+/**
+ * @brief   Returns an unique numeric identifier for a DMA stream.
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              An unique numeric stream identifier.
+ */
+#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
+
+/**
+ * @brief   Returns a DMA stream identifier mask.
+ *
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              A DMA stream identifier mask.
+ */
+#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
+  (1 << STM32_DMA_STREAM_ID(dma, stream))
+
+/**
+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.
+ * @param[in] id        the stream numeric identifier
+ * @param[in] mask      the stream numeric identifiers mask
+ *
+ * @retval              The check result.
+ * @retval FALSE        id does not belong to the mask.
+ * @retval TRUE         id belongs to the mask.
+ */
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+
+/**
+ * @name    DMA streams identifiers
+ * @{
+ */
+/**
+ * @brief   Returns a pointer to a stm32_dma_stream_t structure.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @return              A pointer to the stm32_dma_stream_t constant structure
+ *                      associated to the DMA stream.
+ */
+#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
+
+#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
+#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
+#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
+#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
+#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
+#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
+#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
+#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(7)
+#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(8)
+#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(9)
+#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(10)
+#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(11)
+/** @} */
+
+/**
+ * @name    CR register constants common to all DMA types
+ * @{
+ */
+#define STM32_DMA_CR_EN             DMA_CCR_EN
+#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE
+#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE
+#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE
+#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
+#define STM32_DMA_CR_DIR_P2M        0
+#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR
+#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM
+#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC
+#define STM32_DMA_CR_PINC           DMA_CCR_PINC
+#define STM32_DMA_CR_MINC           DMA_CCR_MINC
+#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE
+#define STM32_DMA_CR_PSIZE_BYTE     0
+#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0
+#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1
+#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE
+#define STM32_DMA_CR_MSIZE_BYTE     0
+#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
+#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
+                                     STM32_DMA_CR_MSIZE_MASK)
+#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
+#define STM32_DMA_CR_PL(n)          ((n) << 12)
+/** @} */
+
+/**
+ * @name    CR register constants only found in enhanced DMA
+ * @{
+ */
+#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
+/** @} */
+
+/**
+ * @name    Status flags passed to the ISR callbacks
+ * @{
+ */
+#define STM32_DMA_ISR_FEIF          0
+#define STM32_DMA_ISR_DMEIF         0
+#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
+#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
+#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA stream descriptor structure.
+ */
+typedef struct {
+  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
+  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
+  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
+                                             register.                      */
+  uint8_t               selfindex;      /**< @brief Index to self in array. */
+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
+} stm32_dma_stream_t;
+
+/**
+ * @brief   STM32 DMA ISR function type.
+ *
+ * @param[in] p         parameter for the registered function
+ * @param[in] flags     pre-shifted content of the ISR register, the bits
+ *                      are aligned to bit zero
+ */
+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Associates a peripheral data register to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CPAR register
+ *
+ * @special
+ */
+#define dmaStreamSetPeripheral(dmastp, addr) {                              \
+  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Associates a memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CMAR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory0(dmastp, addr) {                                 \
+  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Sets the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] size      value to be written in the CNDTR register
+ *
+ * @special
+ */
+#define dmaStreamSetTransactionSize(dmastp, size) {                         \
+  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
+}
+
+/**
+ * @brief   Returns the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @return              The number of transfers to be performed.
+ *
+ * @special
+ */
+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
+
+/**
+ * @brief   Programs the stream mode settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register
+ *
+ * @special
+ */
+#define dmaStreamSetMode(dmastp, mode) {                                    \
+  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
+}
+
+/**
+ * @brief   DMA stream enable.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamEnable(dmastp) {                                           \
+  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
+}
+
+/**
+ * @brief   DMA stream disable.
+ * @details The function disables the specified stream and then clears any
+ *          pending interrupt.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @note    Interrupts enabling flags are set to zero after this call, see
+ *          bug 3607518.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamDisable(dmastp) {                                          \
+  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
+                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
+  dmaStreamClearInterrupt(dmastp);                                          \
+}
+
+/**
+ * @brief   DMA stream interrupt sources clear.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamClearInterrupt(dmastp) {                                   \
+  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
+}
+
+/**
+ * @brief   Starts a memory to memory operation using the specified stream.
+ * @note    The default transfer data mode is "byte to byte" but it can be
+ *          changed by specifying extra options in the @p mode parameter.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register, this value
+ *                      is implicitly ORed with:
+ *                      - @p STM32_DMA_CR_MINC
+ *                      - @p STM32_DMA_CR_PINC
+ *                      - @p STM32_DMA_CR_DIR_M2M
+ *                      - @p STM32_DMA_CR_EN
+ *                      .
+ * @param[in] src       source address
+ * @param[in] dst       destination address
+ * @param[in] n         number of data units to copy
+ */
+#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
+  dmaStreamSetPeripheral(dmastp, src);                                      \
+  dmaStreamSetMemory0(dmastp, dst);                                         \
+  dmaStreamSetTransactionSize(dmastp, n);                                   \
+  dmaStreamSetMode(dmastp, (mode) |                                         \
+                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
+                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
+}
+
+/**
+ * @brief   Polled wait for DMA transfer end.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ */
+#define dmaWaitCompletion(dmastp) {                                         \
+  while ((dmastp)->channel->CNDTR > 0)                                      \
+    ;                                                                       \
+  dmaStreamDisable(dmastp);                                                 \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dmaInit(void);
+  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                         uint32_t priority,
+                         stm32_dmaisr_t func,
+                         void *param);
+  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_DMA_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F30x/stm32_isr.h b/os/hal/ports/STM32/STM32F30x/stm32_isr.h
index 94b04b63e..94b04b63e 100644
--- a/os/hal/platforms/STM32F30x/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F30x/stm32_isr.h
diff --git a/os/hal/platforms/STM32F30x/stm32_rcc.h b/os/hal/ports/STM32/STM32F30x/stm32_rcc.h
index 9cc2edf52..9cc2edf52 100644
--- a/os/hal/platforms/STM32F30x/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F30x/stm32_rcc.h
diff --git a/os/hal/ports/STM32/STM32F30x/stm32_registry.h b/os/hal/ports/STM32/STM32F30x/stm32_registry.h
new file mode 100644
index 000000000..5ab6aa3f2
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F30x/stm32_registry.h
@@ -0,0 +1,195 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F30x/stm32_registry.h
+ * @brief   STM32F30x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    STM32F30x capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      TRUE
+#define STM32_HAS_ADC4                      TRUE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             34
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_IS_CALENDAR               TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM8                      TRUE
+#define STM32_TIM8_IS_32BITS                FALSE
+#define STM32_TIM8_CHANNELS                 6
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5                     TRUE
+
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F37x/adc_lld.c b/os/hal/ports/STM32/STM32F37x/adc_lld.c
new file mode 100644
index 000000000..3d4ede887
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F37x/adc_lld.c
@@ -0,0 +1,735 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F37x/adc_lld.c
+ * @brief   STM32F37x ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define SDADC_FORBIDDEN_CR1_FLAGS   (SDADC_CR1_INIT   | SDADC_CR1_RDMAEN |  \
+                                     SDADC_CR1_RSYNC  | SDADC_CR1_JSYNC  |  \
+                                     SDADC_CR1_ROVRIE | SDADC_CR1_REOCIE |  \
+                                     SDADC_CR1_JEOCIE | SDADC_CR1_EOCALIE)
+
+#define SDADC_ENFORCED_CR1_FLAGS    (SDADC_CR1_JDMAEN  | SDADC_CR1_JOVRIE)
+
+#define SDADC_FORBIDDEN_CR2_FLAGS   (SDADC_CR2_RSWSTART   |                 \
+                                     SDADC_CR2_RCONT      |                 \
+                                     SDADC_CR2_RCH        |                 \
+                                     SDADC_CR2_JCONT      |                 \
+                                     SDADC_CR2_STARTCALIB |                 \
+                                     SDADC_CR2_CALIBCNT)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/** @brief SDADC1 driver identifier.*/
+#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__)
+ADCDriver SDADCD1;
+#endif
+
+/** @brief SDADC2 driver identifier.*/
+#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__)
+ADCDriver SDADCD2;
+#endif
+
+/** @brief SDADC3 driver identifier.*/
+#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__)
+ADCDriver SDADCD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+static const ADCConfig adc_lld_default_config = {
+#if STM32_ADC_USE_SDADC
+  0,
+  {
+     0,
+     0,
+     0
+  }
+#else /* !STM32_ADC_USE_SDADC */
+  0
+#endif /* !STM32_ADC_USE_SDADC */
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Stops, reconfigures and restarts an ADC/SDADC.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_reconfig(ADCDriver *adcp) {
+
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+  if (adcp->adc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC
+  {
+    /* ADC initial setup, starting the analog part here in order to reduce
+       the latency when starting a conversion.*/
+    uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE;
+    adcp->adc->CR2 = cr2;
+    adcp->adc->CR1 = 0;
+    adcp->adc->CR2 = cr2 | ADC_CR2_ADON;
+
+  }
+#endif /* STM32_ADC_USE_ADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+  else if (adcp->sdadc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_SDADC
+  {
+    /* SDADC initial setup, starting the analog part here in order to reduce
+       the latency when starting a conversion.*/
+    adcp->sdadc->CR2    = 0;
+    adcp->sdadc->CR1    = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
+                          ~SDADC_FORBIDDEN_CR1_FLAGS;
+    adcp->sdadc->CONF0R = (adcp->sdadc->CONF0R & SDADC_CONFR_OFFSET_MASK) |
+                          adcp->config->confxr[0];
+    adcp->sdadc->CONF1R = (adcp->sdadc->CONF1R & SDADC_CONFR_OFFSET_MASK) |
+                          adcp->config->confxr[1];
+    adcp->sdadc->CONF2R = (adcp->sdadc->CONF2R & SDADC_CONFR_OFFSET_MASK) |
+                          adcp->config->confxr[2];
+    adcp->sdadc->CR2    = SDADC_CR2_ADON;
+  }
+#endif /* STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+else {
+    osalDbgAssert(FALSE, "invalid state");
+  }
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+}
+
+/**
+ * @brief   ADC DMA ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ *
+ * @notapi
+ */
+static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    /* DMA, this could help only if the DMA tries to access an unmapped
+       address space or violates alignment rules.*/
+    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+  }
+  else {
+    /* It is possible that the conversion group has already be reset by the
+       ADC error handler, in this case this interrupt is spurious.*/
+    if (adcp->grpp != NULL) {
+      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+        /* Transfer complete processing.*/
+        _adc_isr_full_code(adcp);
+      }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
+    }
+  }
+}
+
+#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
+/**
+ * @brief   ADC ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] sr        content of the ISR register
+ *
+ * @notapi
+ */
+static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sr) {
+
+  /* It could be a spurious interrupt caused by overflows after DMA disabling,
+     just ignore it in this case.*/
+  if (adcp->grpp != NULL) {
+    if (sr & ADC_SR_AWD) {
+      /* Analog watchdog error.*/
+      _adc_isr_error_code(adcp, ADC_ERR_AWD1);
+    }
+  }
+}
+#endif /* STM32_ADC_USE_ADC */
+
+#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
+/**
+ * @brief   ADC ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] isr       content of the ISR register
+ *
+ * @notapi
+ */
+static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
+
+  /* It could be a spurious interrupt caused by overflows after DMA disabling,
+     just ignore it in this case.*/
+  if (adcp->grpp != NULL) {
+    /* Note, an overflow may occur after the conversion ended before the driver
+       is able to stop the ADC, this is why the DMA channel is checked too.*/
+    if ((isr & SDADC_ISR_JOVRF) &&
+        (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
+      /* ADC overflow condition, this could happen only if the DMA is unable
+         to read data fast enough.*/
+      _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
+    }
+  }
+}
+#endif /* STM32_ADC_USE_SDADC */
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief   ADC1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector88) {
+  uint32_t sr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  sr  = ADC1->SR;
+  ADC1->SR = 0;
+  adc_lld_serve_interrupt(&ADCD1, sr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__)
+/**
+ * @brief   SDADC1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector134) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  isr  = SDADC1->ISR;
+  SDADC1->CLRISR = isr;
+  sdadc_lld_serve_interrupt(&SDADCD1, isr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_SDADC1 */
+
+#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__)
+/**
+ * @brief   SDADC2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector138) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  isr  = SDADC2->ISR;
+  SDADC2->CLRISR = isr;
+  sdadc_lld_serve_interrupt(&SDADCD2, isr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_SDADC2 */
+
+#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__)
+/**
+ * @brief   SDADC3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector13C) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  isr  = SDADC3->ISR;
+  SDADC3->CLRISR = isr;
+  sdadc_lld_serve_interrupt(&SDADCD3, isr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_SDADC3 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adc     = ADC1;
+#if STM32_ADC_USE_SDADC
+  ADCD1.sdadc   = NULL;
+#endif
+  ADCD1.dmastp  = STM32_DMA1_STREAM1;
+  ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+  nvicEnableVector(ADC1_IRQn, STM32_ADC_ADC1_IRQ_PRIORITY);
+#endif
+
+#if STM32_ADC_USE_SDADC1
+  /* Driver initialization.*/
+  adcObjectInit(&SDADCD1);
+#if STM32_ADC_USE_ADC
+  SDADCD1.adc     = NULL;
+#endif
+  SDADCD1.sdadc   = SDADC1;
+  SDADCD1.dmastp  = STM32_DMA2_STREAM3;
+  SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) |
+                  STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+  nvicEnableVector(SDADC1_IRQn, STM32_ADC_SDADC1_IRQ_PRIORITY);
+#endif
+
+#if STM32_ADC_USE_SDADC2
+  /* Driver initialization.*/
+  adcObjectInit(&SDADCD2);
+#if STM32_ADC_USE_ADC
+  SDADCD2.adc     = NULL;
+#endif
+  SDADCD2.sdadc   = SDADC2;
+  SDADCD2.dmastp  = STM32_DMA2_STREAM4;
+  SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) |
+                  STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+  nvicEnableVector(SDADC2_IRQn, STM32_ADC_SDADC2_IRQ_PRIORITY);
+#endif
+
+#if STM32_ADC_USE_SDADC3
+  /* Driver initialization.*/
+  adcObjectInit(&SDADCD3);
+#if STM32_ADC_USE_ADC
+  SDADCD3.adc     = NULL;
+#endif
+  SDADCD3.sdadc   = SDADC3;
+  SDADCD3.dmastp  = STM32_DMA2_STREAM5;
+  SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) |
+                  STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+  nvicEnableVector(SDADC3_IRQn, STM32_ADC_SDADC3_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+  if (adcp->config == NULL)
+    adcp->config = &adc_lld_default_config;
+
+  /* If in stopped state then enables the ADC and DMA clocks.*/
+  if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      bool b = dmaStreamAllocate(adcp->dmastp,
+                                 STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+                                 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+                                 (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+      rccEnableADC1(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_SDADC1
+    if (&SDADCD1 == adcp) {
+      bool b = dmaStreamAllocate(adcp->dmastp,
+                                 STM32_ADC_SDADC1_DMA_IRQ_PRIORITY,
+                                 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+                                 (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR);
+      rccEnableSDADC1(FALSE);
+      PWR->CR |= PWR_CR_SDADC1EN;
+      adcp->sdadc->CR2 = 0;
+      adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
+                         ~SDADC_FORBIDDEN_CR1_FLAGS;
+      adcp->sdadc->CR2 = SDADC_CR2_ADON;
+    }
+#endif /* STM32_ADC_USE_SDADC1 */
+
+#if STM32_ADC_USE_SDADC2
+    if (&SDADCD2 == adcp) {
+      bool b = dmaStreamAllocate(adcp->dmastp,
+                                 STM32_ADC_SDADC2_DMA_IRQ_PRIORITY,
+                                 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+                                 (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR);
+      rccEnableSDADC2(FALSE);
+      PWR->CR |= PWR_CR_SDADC2EN;
+      adcp->sdadc->CR2 = 0;
+      adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
+                         ~SDADC_FORBIDDEN_CR1_FLAGS;
+      adcp->sdadc->CR2 = SDADC_CR2_ADON;
+    }
+#endif /* STM32_ADC_USE_SDADC2 */
+
+#if STM32_ADC_USE_SDADC3
+    if (&SDADCD3 == adcp) {
+      bool b = dmaStreamAllocate(adcp->dmastp,
+                                 STM32_ADC_SDADC3_DMA_IRQ_PRIORITY,
+                                 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+                                 (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR);
+      rccEnableSDADC2(FALSE);
+      PWR->CR |= PWR_CR_SDADC3EN;
+      adcp->sdadc->CR2 = 0;
+      adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
+                         ~SDADC_FORBIDDEN_CR1_FLAGS;
+      adcp->sdadc->CR2 = SDADC_CR2_ADON;
+    }
+#endif /* STM32_ADC_USE_SDADC3 */
+  }
+
+  adc_lld_reconfig(adcp);
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+  /* If in ready state then disables the ADC clock.*/
+  if (adcp->state == ADC_READY) {
+    dmaStreamRelease(adcp->dmastp);
+
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      adcp->adc->CR1 = 0;
+      adcp->adc->CR2 = 0;
+      rccDisableADC1(FALSE);
+    }
+#endif
+
+#if STM32_ADC_USE_SDADC1
+    if (&SDADCD1 == adcp) {
+      adcp->sdadc->CR1 = 0;
+      adcp->sdadc->CR2 = 0;
+      rccDisableSDADC1(FALSE);
+      PWR->CR &= ~PWR_CR_SDADC1EN;
+    }
+#endif
+
+#if STM32_ADC_USE_SDADC2
+    if (&SDADCD2 == adcp) {
+      adcp->sdadc->CR1 = 0;
+      adcp->sdadc->CR2 = 0;
+      rccDisableSDADC2(FALSE);
+      PWR->CR &= ~PWR_CR_SDADC2EN;
+    }
+#endif
+
+#if STM32_ADC_USE_SDADC3
+    if (&SDADCD3 == adcp) {
+      adcp->sdadc->CR1 = 0;
+      adcp->sdadc->CR2 = 0;
+      rccDisableSDADC3(FALSE);
+      PWR->CR &= ~PWR_CR_SDADC3EN;
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+  uint32_t mode;
+  const ADCConversionGroup* grpp = adcp->grpp;
+
+  /* DMA setup.*/
+  mode = adcp->dmamode;
+  if (grpp->circular) {
+    mode |= STM32_DMA_CR_CIRC;
+    if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
+    }
+  }
+  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+  dmaStreamSetTransactionSize(adcp->dmastp,
+                              (uint32_t)grpp->num_channels * 
+                              (uint32_t)adcp->depth);
+  dmaStreamSetMode(adcp->dmastp, mode);
+  dmaStreamEnable(adcp->dmastp);
+
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+  if (adcp->adc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC
+  {
+    uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE;
+    cr2 |= grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
+    if ((cr2 & ADC_CR2_SWSTART) != 0)
+      cr2 |= ADC_CR2_CONT;
+    adcp->adc->CR2   = cr2;
+
+    /* ADC setup.*/
+    adcp->adc->SR    = 0;
+    adcp->adc->LTR   = grpp->u.adc.ltr;
+    adcp->adc->HTR   = grpp->u.adc.htr;
+    adcp->adc->SMPR1 = grpp->u.adc.smpr[0];
+    adcp->adc->SMPR2 = grpp->u.adc.smpr[1];
+    adcp->adc->SQR1  = grpp->u.adc.sqr[0] |
+                       ADC_SQR1_NUM_CH(grpp->num_channels);
+    adcp->adc->SQR2  = grpp->u.adc.sqr[1];
+    adcp->adc->SQR3  = grpp->u.adc.sqr[2];
+
+    /* ADC conversion start, the start is performed using the method
+       specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
+    adcp->adc->CR1   = grpp->u.adc.cr1 | ADC_CR1_AWDIE | ADC_CR1_SCAN;
+    adcp->adc->CR2   = adcp->adc->CR2;  /* Triggers the conversion start.*/
+  }
+#endif /* STM32_ADC_USE_ADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+  else if (adcp->sdadc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_SDADC
+  {
+    uint32_t cr2 = (grpp->u.sdadc.cr2 & ~SDADC_FORBIDDEN_CR2_FLAGS) |
+                   SDADC_CR2_ADON;
+    if ((grpp->u.sdadc.cr2 & SDADC_CR2_JSWSTART) != 0)
+      cr2 |= SDADC_CR2_JCONT;
+
+    /* Entering initialization mode.*/
+    adcp->sdadc->CR1 |= SDADC_CR1_INIT;
+    while ((adcp->sdadc->ISR & SDADC_ISR_INITRDY) == 0)
+      ;
+
+    /* SDADC setup.*/
+    adcp->sdadc->JCHGR    = grpp->u.sdadc.jchgr;
+    adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0];
+    adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1];
+
+    /* SDADC trigger modes, this write must be performed when
+       SDADC_CR1_INIT=1.*/
+    adcp->sdadc->CR2 = cr2;
+
+    /* Leaving initialization mode.*/
+    adcp->sdadc->CR1 &= ~SDADC_CR1_INIT;
+
+    /* Special case, if SDADC_CR2_JSWSTART is specified it has to be
+       written after SDADC_CR1_INIT has been set to zero. Just a write is
+       performed, any other bit is ingore if not in initialization mode.*/
+    adcp->sdadc->CR2 = cr2;
+  }
+#endif /* STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+  else {
+    osalDbgAssert(FALSE, "invalid state");
+  }
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+  /* Disabling the associated DMA stream.*/
+  dmaStreamDisable(adcp->dmastp);
+
+  /* Stopping and restarting the whole ADC, apparently the only way to stop
+     a conversion.*/
+  adc_lld_reconfig(adcp);
+}
+
+/**
+ * @brief   Calibrates an ADC unit.
+ * @note    The calibration must be performed after calling @p adcStart().
+ * @note    For SDADC units it is assumed that the field SDADC_CR2_CALIBCNT
+ *          has been
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @api
+ */
+void adcSTM32Calibrate(ADCDriver *adcp) {
+
+  osalDbgAssert((adcp->state == ADC_READY) ||
+              (adcp->state == ADC_COMPLETE) ||
+              (adcp->state == ADC_ERROR),
+              "not ready");
+
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+  if (adcp->adc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC
+  {
+    /* Resetting calibration just to be safe.*/
+    ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+    while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
+      ;
+
+    /* Calibration.*/
+    ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+    while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
+      ;
+  }
+#endif /* STM32_ADC_USE_ADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+  else if (adcp->sdadc != NULL)
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_SDADC
+  {
+    /* Selecting a full calibration in three steps.*/
+    adcp->sdadc->CR2  = (adcp->sdadc->CR2 & ~SDADC_CR2_CALIBCNT) |
+                        SDADC_CR2_CALIBCNT_1;
+
+    /* Calibration.*/
+    adcp->sdadc->CR2 |= SDADC_CR2_STARTCALIB;
+    while ((adcp->sdadc->ISR & SDADC_ISR_EOCALF) == 0)
+      ;
+
+    /* Clearing the EOCALF flag.*/
+    adcp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF;
+  }
+#endif /* STM32_ADC_USE_SDADC */
+#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
+  else {
+    osalDbgAssert(FALSE, "invalid state");
+  }
+#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
+}
+
+#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
+/**
+ * @brief   Enables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ *          temperature sensor and internal reference voltage.
+ * @note    This is an STM32-only functionality.
+ *
+ * @api
+ */
+void adcSTM32EnableTSVREFE(void) {
+
+  ADC1->CR2 |= ADC_CR2_TSVREFE;
+}
+
+/**
+ * @brief   Disables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ *          temperature sensor and internal reference voltage.
+ * @note    This is an STM32-only functionality.
+ *
+ * @api
+ */
+void adcSTM32DisableTSVREFE(void) {
+
+  ADC1->CR2 &= ~ADC_CR2_TSVREFE;
+}
+
+/**
+ * @brief   Enables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note    This is an STM32-only functionality.
+ *
+ * @api
+ */
+void adcSTM32EnableVBATE(void) {
+
+  SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT;
+}
+
+/**
+ * @brief   Disables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note    This is an STM32-only functionality.
+ *
+ * @api
+ */
+void adcSTM32DisableVBATE(void) {
+
+  SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_VBAT;
+}
+#endif /* STM32_ADC_USE_ADC */
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F37x/adc_lld.h b/os/hal/ports/STM32/STM32F37x/adc_lld.h
new file mode 100644
index 000000000..42cff6d61
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F37x/adc_lld.h
@@ -0,0 +1,706 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F37x/adc_lld.h
+ * @brief   STM32F37x ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Triggers selection
+ * @{
+ */
+#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 24) /**< @brief Trigger source.     */
+/** @} */
+
+/**
+ * @name    ADC clock divider settings
+ * @{
+ */
+#define ADC_CCR_ADCPRE_DIV2     0
+#define ADC_CCR_ADCPRE_DIV4     1
+#define ADC_CCR_ADCPRE_DIV6     2
+#define ADC_CCR_ADCPRE_DIV8     3
+/** @} */
+
+/**
+ * @name    Available analog channels
+ * @{
+ */
+#define ADC_CHANNEL_IN0         0   /**< @brief External analog input 0.    */
+#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
+#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
+#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
+#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
+#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
+#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
+#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
+#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
+#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
+#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
+#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
+#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
+#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
+#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
+#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
+#define ADC_CHANNEL_SENSOR      16  /**< @brief Internal temperature sensor.*/
+#define ADC_CHANNEL_VREFINT     17  /**< @brief Internal reference.         */
+#define ADC_CHANNEL_VBAT        18  /**< @brief VBAT.                       */
+/** @} */
+
+/**
+ * @name    Sampling rates
+ * @{
+ */
+#define ADC_SAMPLE_1P5          0   /**< @brief 1.5 cycles sampling time.   */
+#define ADC_SAMPLE_7P5          1   /**< @brief 7.5 cycles sampling time.   */
+#define ADC_SAMPLE_13P5         2   /**< @brief 13.5 cycles sampling time.  */
+#define ADC_SAMPLE_28P5         3   /**< @brief 28.5 cycles sampling time.  */
+#define ADC_SAMPLE_41P5         4   /**< @brief 41.5 cycles sampling time.  */
+#define ADC_SAMPLE_55P5         5   /**< @brief 55.5 cycles sampling time.  */
+#define ADC_SAMPLE_71P5         6   /**< @brief 71.5 cycles sampling time.  */
+#define ADC_SAMPLE_239P5        7   /**< @brief 239.5 cycles sampling time. */
+/** @} */
+
+/**
+ * @name    SDADC JCHGR bit definitions
+ * @{
+ */
+#define SDADC_JCHG_MASK         (511U << 0)
+#define SDADC_JCHG(n)           (1U << (n))
+/** @} */
+
+/**
+ * @name    SDADC channels definitions
+ * @{
+ */
+#define SDADC_CHANNEL_0         SDADC_JCHG(0)
+#define SDADC_CHANNEL_1         SDADC_JCHG(1)
+#define SDADC_CHANNEL_2         SDADC_JCHG(2)
+#define SDADC_CHANNEL_3         SDADC_JCHG(3)
+#define SDADC_CHANNEL_4         SDADC_JCHG(4)
+#define SDADC_CHANNEL_5         SDADC_JCHG(5)
+#define SDADC_CHANNEL_6         SDADC_JCHG(6)
+#define SDADC_CHANNEL_7         SDADC_JCHG(7)
+#define SDADC_CHANNEL_8         SDADC_JCHG(8)
+#define SDADC_CHANNEL_9         SDADC_JCHG(9)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1                  FALSE
+#endif
+
+/**
+ * @brief   SDADC1 driver enable switch.
+ * @details If set to @p TRUE the support for SDADC1 is included.
+ */
+#if !defined(STM32_ADC_USE_SDADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_SDADC1                FALSE
+#endif
+
+/**
+ * @brief   SDADC2 driver enable switch.
+ * @details If set to @p TRUE the support for SDADC2 is included.
+ */
+#if !defined(STM32_ADC_USE_SDADC2) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_SDADC2                FALSE
+#endif
+
+/**
+ * @brief   SDADC3 driver enable switch.
+ * @details If set to @p TRUE the support for SDADC3 is included.
+ */
+#if !defined(STM32_ADC_USE_SDADC3) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_SDADC3                FALSE
+#endif
+
+/**
+ * @brief   ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   SDADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_SDADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC1_DMA_PRIORITY       2
+#endif
+
+/**
+ * @brief   SDADC2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_SDADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC2_DMA_PRIORITY       2
+#endif
+
+/**
+ * @brief   SDADC3 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_SDADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC3_DMA_PRIORITY       2
+#endif
+
+/**
+ * @brief   ADC interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_IRQ_PRIORITY         5
+#endif
+
+/**
+ * @brief   ADC DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
+#endif
+
+/**
+ * @brief   SDADC1 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC1_IRQ_PRIORITY       5
+#endif
+
+/**
+ * @brief   SDADC2 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC2_IRQ_PRIORITY       5
+#endif
+
+/**
+ * @brief   SDADC3 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC3_IRQ_PRIORITY       5
+#endif
+
+/**
+ * @brief   SDADC1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY   5
+#endif
+
+/**
+ * @brief   SDADC2 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY   5
+#endif
+
+/**
+ * @brief   SDADC3 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY   5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/**
+ * @brief   At least an ADC unit is in use.
+ */
+#define STM32_ADC_USE_ADC   STM32_ADC_USE_ADC1
+
+/**
+ * @brief   At least an SDADC unit is in use.
+ */
+#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 ||                        \
+                             STM32_ADC_USE_SDADC2 ||                        \
+                             STM32_ADC_USE_SDADC3)
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_SDADC1 && !STM32_HAS_SDADC1
+#error "SDADC1 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_SDADC2 && !STM32_HAS_SDADC2
+#error "SDADC2 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_SDADC3 && !STM32_HAS_SDADC3
+#error "SDADC3 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC
+#error "ADC driver activated but no ADC/SDADC peripheral assigned"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_SDADC1 &&                                                 \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC1"
+#endif
+
+#if STM32_ADC_USE_SDADC1 &&                                                 \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_SDADC1 &&                                                 \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SDADC1"
+#endif
+
+#if STM32_ADC_USE_SDADC2 &&                                                 \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC2"
+#endif
+
+#if STM32_ADC_USE_SDADC2 &&                                                 \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC2 DMA"
+#endif
+
+#if STM32_ADC_USE_SDADC2 &&                                                 \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SDADC2"
+#endif
+
+#if STM32_ADC_USE_SDADC3 &&                                                 \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC3"
+#endif
+
+#if STM32_ADC_USE_SDADC3 &&                                                 \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SDADC3 DMA"
+#endif
+
+#if STM32_ADC_USE_SDADC3 &&                                                 \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SDADC3"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief   Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief   Possible ADC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
+  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
+  ADC_ERR_AWD1 = 2                          /**< Watchdog 1 triggered.      */
+} adcerror_t;
+
+/**
+ * @brief   Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief   ADC notification callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] buffer    pointer to the most recent samples data
+ * @param[in] n         number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief   ADC error callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] err       ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief   Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ *          operation.
+ * @note    The use of this configuration structure requires knowledge of
+ *          STM32 ADC cell registers interface, please refer to the STM32
+ *          reference manual for details.
+ */
+typedef struct {
+  /**
+   * @brief   Enables the circular buffer mode for the group.
+   */
+  bool                      circular;
+  /**
+   * @brief   Number of the analog channels belonging to the conversion group.
+   */
+  adc_channels_num_t        num_channels;
+  /**
+   * @brief   Callback function associated to the group or @p NULL.
+   */
+  adccallback_t             end_cb;
+  /**
+   * @brief   Error callback or @p NULL.
+   */
+  adcerrorcallback_t        error_cb;
+  /* End of the mandatory fields.*/
+
+  /**
+   * @brief  Union of ADC and SDADC config parms.  The decision of which struct 
+   *         union to use is determined by the ADCDriver.  If the ADCDriver adc parm
+   *         is not NULL, then use the adc struct, otherwise if the ADCDriver sdadc parm
+   *         is not NULL, then use the sdadc struct.
+   */
+  union { 
+#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
+    struct {
+      /**
+       * @brief   ADC CR1 register initialization data.
+       * @note    All the required bits must be defined into this field except
+       *          @p ADC_CR1_SCAN that is enforced inside the driver.
+       */
+      uint32_t                  cr1;
+      /**
+       * @brief   ADC CR2 register initialization data.
+       * @note    All the required bits must be defined into this field except
+       *          @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
+       *          enforced inside the driver.
+       */
+      uint32_t                  cr2;
+      /**
+       * @brief   ADC LTR register initialization data.
+       */
+      uint32_t                  ltr;
+      /**
+       * @brief   ADC HTR register initialization data.
+       */
+      uint32_t                  htr;
+      /**
+       * @brief   ADC SMPRx registers initialization data.
+       */
+      uint32_t                  smpr[2];
+      /**
+       * @brief   ADC SQRx register initialization data.
+       */
+      uint32_t                  sqr[3];
+    } adc;
+#endif /* STM32_ADC_USE_ADC */
+#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
+    struct {
+      /**
+       * @brief   SDADC CR2 register initialization data.
+       * @note    Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL
+       *          and @p SDADC_CR2_JEXTEN can be specified in this field.
+       */
+      uint32_t                  cr2;
+      /**
+       * @brief   SDADC JCHGR register initialization data.
+       */
+      uint32_t                  jchgr;
+      /**
+       * @brief   SDADC CONFCHxR registers initialization data.
+       */
+      uint32_t                  confchr[2];
+    } sdadc;
+#endif /* STM32_ADC_USE_SDADC */
+  } u;
+} ADCConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+#if STM32_ADC_USE_SDADC
+  /**
+   * @brief   SDADC CR1 register initialization data.
+   */
+  uint32_t                  cr1;
+  /**
+   * @brief   SDADC CONFxR registers initialization data.
+   */
+  uint32_t                  confxr[3];
+#else /* !STM32_ADC_USE_SDADC */
+  uint32_t                  dummy;
+#endif /* !STM32_ADC_USE_SDADC */
+} ADCConfig;
+
+/**
+ * @brief   Structure representing an ADC driver.
+ */
+struct ADCDriver {
+  /**
+   * @brief Driver state.
+   */
+  adcstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const ADCConfig           *config;
+  /**
+   * @brief Current samples buffer pointer or @p NULL.
+   */
+  adcsample_t               *samples;
+  /**
+   * @brief Current samples buffer depth or @p 0.
+   */
+  size_t                    depth;
+  /**
+   * @brief Current conversion group pointer or @p NULL.
+   */
+  const ADCConversionGroup  *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+  ADC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
+  /**
+   * @brief   Pointer to the ADCx registers block.
+   */
+  ADC_TypeDef               *adc;
+#endif
+#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
+  /**
+   * @brief   Pointer to the SDADCx registers block.
+   */
+  SDADC_TypeDef             *sdadc;
+#endif
+  /**
+   * @brief   Pointer to associated DMA channel.
+   */
+  const stm32_dma_stream_t  *dmastp;
+  /**
+   * @brief   DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Sequences building helper macros for ADC
+ * @{
+ */
+/**
+ * @brief   Number of channels in a conversion sequence.
+ */
+#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
+#define ADC_SQR1_SQ13_N(n)      ((n) << 0)  /**< @brief 13th channel in seq.*/
+#define ADC_SQR1_SQ14_N(n)      ((n) << 5)  /**< @brief 14th channel in seq.*/
+#define ADC_SQR1_SQ15_N(n)      ((n) << 10) /**< @brief 15th channel in seq.*/
+#define ADC_SQR1_SQ16_N(n)      ((n) << 15) /**< @brief 16th channel in seq.*/
+
+#define ADC_SQR2_SQ7_N(n)       ((n) << 0)  /**< @brief 7th channel in seq. */
+#define ADC_SQR2_SQ8_N(n)       ((n) << 5)  /**< @brief 8th channel in seq. */
+#define ADC_SQR2_SQ9_N(n)       ((n) << 10) /**< @brief 9th channel in seq. */
+#define ADC_SQR2_SQ10_N(n)      ((n) << 15) /**< @brief 10th channel in seq.*/
+#define ADC_SQR2_SQ11_N(n)      ((n) << 20) /**< @brief 11th channel in seq.*/
+#define ADC_SQR2_SQ12_N(n)      ((n) << 25) /**< @brief 12th channel in seq.*/
+
+#define ADC_SQR3_SQ1_N(n)       ((n) << 0)  /**< @brief 1st channel in seq. */
+#define ADC_SQR3_SQ2_N(n)       ((n) << 5)  /**< @brief 2nd channel in seq. */
+#define ADC_SQR3_SQ3_N(n)       ((n) << 10) /**< @brief 3rd channel in seq. */
+#define ADC_SQR3_SQ4_N(n)       ((n) << 15) /**< @brief 4th channel in seq. */
+#define ADC_SQR3_SQ5_N(n)       ((n) << 20) /**< @brief 5th channel in seq. */
+#define ADC_SQR3_SQ6_N(n)       ((n) << 25) /**< @brief 6th channel in seq. */
+/** @} */
+
+/**
+ * @name    Sampling rate settings helper macros
+ * @{
+ */
+#define ADC_SMPR2_SMP_AN0(n)    ((n) << 0)  /**< @brief AN0 sampling time.  */
+#define ADC_SMPR2_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
+#define ADC_SMPR2_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
+#define ADC_SMPR2_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
+#define ADC_SMPR2_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
+#define ADC_SMPR2_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
+#define ADC_SMPR2_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
+#define ADC_SMPR2_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
+#define ADC_SMPR2_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
+#define ADC_SMPR2_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
+
+#define ADC_SMPR1_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
+#define ADC_SMPR1_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
+#define ADC_SMPR1_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
+#define ADC_SMPR1_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
+#define ADC_SMPR1_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
+#define ADC_SMPR1_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
+#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
+                                                 sampling time.             */
+#define ADC_SMPR1_SMP_VREF(n)   ((n) << 21) /**< @brief Voltage Reference
+                                                 sampling time.             */
+#define ADC_SMPR1_SMP_VBAT(n)   ((n) << 24) /**< @brief VBAT sampling time. */
+/** @} */
+
+/**
+ * @name    Sequences building helper macros for SDADC
+ * @{
+ */
+#define SDADC_JCHGR_CH(n)           (1U << (n))
+/** @} */
+
+/**
+ * @name    Channel configuration number helper macros for SDADC
+ * @{
+ */
+#define SDADC_CONFCHR1_CH0(n)       ((n) << 0)
+#define SDADC_CONFCHR1_CH1(n)       ((n) << 4)
+#define SDADC_CONFCHR1_CH2(n)       ((n) << 8)
+#define SDADC_CONFCHR1_CH3(n)       ((n) << 12)
+#define SDADC_CONFCHR1_CH4(n)       ((n) << 16)
+#define SDADC_CONFCHR1_CH5(n)       ((n) << 20)
+#define SDADC_CONFCHR1_CH6(n)       ((n) << 24)
+#define SDADC_CONFCHR1_CH7(n)       ((n) << 28)
+#define SDADC_CONFCHR2_CH8(n)       ((n) << 0)
+/** @} */
+
+/**
+ * @name    Configuration registers helper macros for SDADC
+ * @{
+ */
+#define SDADC_CONFR_OFFSET_MASK     (0xFFFU << 0)
+#define SDADC_CONFR_OFFSET(n)       ((n) << 0)
+#define SDADC_CONFR_GAIN_MASK       (7U << 20)
+#define SDADC_CONFR_GAIN_1X         (0U << 20)
+#define SDADC_CONFR_GAIN_2X         (1U << 20)
+#define SDADC_CONFR_GAIN_4X         (2U << 20)
+#define SDADC_CONFR_GAIN_8X         (3U << 20)
+#define SDADC_CONFR_GAIN_16X        (4U << 20)
+#define SDADC_CONFR_GAIN_32X        (5U << 20)
+#define SDADC_CONFR_GAIN_0P5X       (7U << 20)
+#define SDADC_CONFR_SE_MASK         (3U << 26)
+#define SDADC_CONFR_SE_DIFF         (0U << 26)
+#define SDADC_CONFR_SE_OFFSET       (1U << 26)
+#define SDADC_CONFR_SE_ZERO_VOLT    (3U << 26)
+#define SDADC_CONFR_COMMON_MASK     (3U << 30)
+#define SDADC_CONFR_COMMON_VSSSD    (0U << 30)
+#define SDADC_CONFR_COMMON_VDDSD2   (1U << 30)
+#define SDADC_CONFR_COMMON_VDDSD    (2U << 30)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#if STM32_ADC_USE_SDADC1 && !defined(__DOXYGEN__)
+extern ADCDriver SDADCD1;
+#endif
+
+#if STM32_ADC_USE_SDADC2 && !defined(__DOXYGEN__)
+extern ADCDriver SDADCD2;
+#endif
+
+#if STM32_ADC_USE_SDADC3 && !defined(__DOXYGEN__)
+extern ADCDriver SDADCD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adc_lld_init(void);
+  void adc_lld_start(ADCDriver *adcp);
+  void adc_lld_stop(ADCDriver *adcp);
+  void adc_lld_start_conversion(ADCDriver *adcp);
+  void adc_lld_stop_conversion(ADCDriver *adcp);
+  void adcSTM32Calibrate(ADCDriver *adcdp);
+#if STM32_ADC_USE_ADC
+  void adcSTM32EnableTSVREFE(void);
+  void adcSTM32DisableTSVREFE(void);
+  void adcSTM32EnableVBATE(void);
+  void adcSTM32DisableVBATE(void);
+#endif /* STM32_ADC_USE_ADC */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c b/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c
new file mode 100644
index 000000000..642f6f8c4
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c
@@ -0,0 +1,352 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F37x/ext_lld_isr.c
+ * @brief   STM32F37x EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if !defined(STM32_DISABLE_EXTI0_HANDLER)
+/**
+ * @brief   EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 0);
+  EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI1_HANDLER)
+/**
+ * @brief   EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 1);
+  EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI2_HANDLER)
+/**
+ * @brief   EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 2);
+  EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI3_HANDLER)
+/**
+ * @brief   EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 3);
+  EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI4_HANDLER)
+/**
+ * @brief   EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 4);
+  EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
+/**
+ * @brief   EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
+  EXTI->PR = pr;
+  if (pr & (1 << 5))
+    EXTD1.config->channels[5].cb(&EXTD1, 5);
+  if (pr & (1 << 6))
+    EXTD1.config->channels[6].cb(&EXTD1, 6);
+  if (pr & (1 << 7))
+    EXTD1.config->channels[7].cb(&EXTD1, 7);
+  if (pr & (1 << 8))
+    EXTD1.config->channels[8].cb(&EXTD1, 8);
+  if (pr & (1 << 9))
+    EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
+/**
+ * @brief   EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
+                   (1 << 15));
+  EXTI->PR = pr;
+  if (pr & (1 << 10))
+    EXTD1.config->channels[10].cb(&EXTD1, 10);
+  if (pr & (1 << 11))
+    EXTD1.config->channels[11].cb(&EXTD1, 11);
+  if (pr & (1 << 12))
+    EXTD1.config->channels[12].cb(&EXTD1, 12);
+  if (pr & (1 << 13))
+    EXTD1.config->channels[13].cb(&EXTD1, 13);
+  if (pr & (1 << 14))
+    EXTD1.config->channels[14].cb(&EXTD1, 14);
+  if (pr & (1 << 15))
+    EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI16_HANDLER)
+/**
+ * @brief   EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 16);
+  EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI17_HANDLER)
+/**
+ * @brief   EXTI[17] interrupt handler (RTC Alarm).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 17);
+  EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI18_HANDLER)
+/**
+ * @brief   EXTI[18] interrupt handler (USB Wakeup).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE8) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 18);
+  EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI19_HANDLER)
+/**
+ * @brief   EXTI[19] interrupt handler (Tamper TimeStamp).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 19);
+  EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI20_HANDLER)
+/**
+ * @brief   EXTI[20] interrupt handler (RTC Wakeup).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 20);
+  EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI21_22_HANDLER)
+/**
+ * @brief   EXTI[21]..EXTI[22] interrupt handler (COMP1, COMP2).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector140) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 21) | (1 << 22));
+  EXTI->PR = pr;
+  if (pr & (1 << 21))
+    EXTD1.config->channels[21].cb(&EXTD1, 21);
+  if (pr & (1 << 22))
+    EXTD1.config->channels[22].cb(&EXTD1, 22);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+  nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+  nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+  nvicEnableVector(EXTI2_TS_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+  nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+  nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+  nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+  nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+  nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+  nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+  nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+  nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+  nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+  nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+}
+
+/**
+ * @brief   Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+  nvicDisableVector(EXTI0_IRQn);
+  nvicDisableVector(EXTI1_IRQn);
+  nvicDisableVector(EXTI2_TS_IRQn);
+  nvicDisableVector(EXTI3_IRQn);
+  nvicDisableVector(EXTI4_IRQn);
+  nvicDisableVector(EXTI9_5_IRQn);
+  nvicDisableVector(EXTI15_10_IRQn);
+  nvicDisableVector(PVD_IRQn);
+  nvicDisableVector(RTC_Alarm_IRQn);
+  nvicDisableVector(USBWakeUp_IRQn);
+  nvicDisableVector(TAMPER_STAMP_IRQn);
+  nvicDisableVector(RTC_WKUP_IRQn);
+  nvicDisableVector(COMP_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F37x/ext_lld_isr.h b/os/hal/ports/STM32/STM32F37x/ext_lld_isr.h
index 088012dc0..088012dc0 100644
--- a/os/hal/platforms/STM32F37x/ext_lld_isr.h
+++ b/os/hal/ports/STM32/STM32F37x/ext_lld_isr.h
diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.c b/os/hal/ports/STM32/STM32F37x/hal_lld.c
new file mode 100644
index 000000000..a34b11546
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F37x/hal_lld.c
@@ -0,0 +1,193 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F37x/hal_lld.c
+ * @brief   STM32F37x HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the backup domain.
+ * @note    WARNING! Changing clock source impossible without resetting
+ *          of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+  /* Backup domain access enabled and left open.*/
+  PWR->CR |= PWR_CR_DBP;
+
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0;
+  }
+
+  /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+#if defined(STM32_LSE_BYPASS)
+  /* LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+  /* No LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                     /* Waits until LSE is stable.   */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+    /* Selects clock source.*/
+    RCC->BDCR |= STM32_RTCSEL;
+
+    /* RTC clock enabled.*/
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+  /* Reset of all peripherals.*/
+  rccResetAPB1(0xFFFFFFFF);
+  rccResetAPB2(0xFFFFFFFF);
+
+  /* PWR clock enabled.*/
+  rccEnablePWRInterface(FALSE);
+
+  /* Initializes the backup domain.*/
+  hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+  dmaInit();
+#endif
+
+  /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+}
+
+/**
+ * @brief   STM32 clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* HSI setup, it enforces the reset situation in order to handle possible
+     problems with JTAG probes and re-initializations.*/
+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;                                       /* Wait until HSI is stable.    */
+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
+  RCC->CFGR = 0;                            /* CFGR reset value.            */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;                                       /* Waits until HSI is selected. */
+
+#if STM32_HSE_ENABLED
+  /* HSE activation.*/
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+  /* No HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON;
+#endif
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;                                       /* Waits until HSE is stable.   */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                                       /* Waits until LSI is stable.   */
+#endif
+
+  /* Clock settings.*/
+  RCC->CFGR  = STM32_SDPRE     | STM32_MCOSEL    | STM32_USBPRE    |
+               STM32_PLLMUL    | STM32_PLLSRC    | STM32_ADCPRE    |
+               STM32_PPRE1     | STM32_PPRE2     | STM32_HPRE;
+  RCC->CFGR2 = STM32_PREDIV;
+  RCC->CFGR3 = STM32_USART3SW  | STM32_USART2SW  | STM32_I2C2SW    |
+               STM32_I2C1SW    | STM32_USART1SW;
+
+#if STM32_ACTIVATE_PLL
+  /* PLL activation.*/
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                                       /* Waits until PLL is stable.   */
+#endif
+
+  /* Flash setup and final clock selection.   */
+  FLASH->ACR = STM32_FLASHBITS;
+
+  /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+  /* Switches clock source.*/
+  RCC->CFGR |= STM32_SW;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;                                       /* Waits selection complete.    */
+#endif
+#endif /* !STM32_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.h b/os/hal/ports/STM32/STM32F37x/hal_lld.h
new file mode 100644
index 000000000..1135b2f3e
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F37x/hal_lld.h
@@ -0,0 +1,987 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F37x/hal_lld.h
+ * @brief   STM32F37x HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - STM32_LSECLK.
+ *          - STM32_LSEDRV.
+ *          - STM32_LSE_BYPASS (optionally).
+ *          - STM32_HSECLK.
+ *          - STM32_HSE_BYPASS (optionally).
+ *          .
+ *          One of the following macros must also be defined:
+ *          - STM32F37X for Analog & DSP devices.
+ *          .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+#define PLATFORM_NAME           "STM32F37x Analog & DSP"
+/** @} */
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX        72000000
+
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        32000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        1000000
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        1000000
+
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX         24000000
+
+/**
+ * @brief   Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN         1000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX        72000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN        16000000
+
+/**
+ * @brief   Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX         36000000
+
+/**
+ * @brief   Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX         72000000
+
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX        14000000
+
+/**
+ * @brief   Minimum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MIN        6000000
+
+/**
+ * @brief   Maximum SDADC clock frequency in fast mode.
+ */
+#define STM32_SDADCCLK_FAST_MAX 6000000
+
+/**
+ * @brief   Maximum SDADC clock frequency in slow mode.
+ */
+#define STM32_SDADCCLK_SLOW_MAX 1500000
+
+/**
+ * @brief   Minimum SDADC clock frequency.
+ */
+#define STM32_SDADCCLK_MIN      500000
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK            8000000     /**< High speed internal clock. */
+#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
+/** @} */
+
+/**
+ * @name    PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK          (7U << 5)   /**< PLS bits mask.             */
+#define STM32_PLS_LEV0          (0U << 5)   /**< PVD level 0.               */
+#define STM32_PLS_LEV1          (1U << 5)   /**< PVD level 1.               */
+#define STM32_PLS_LEV2          (2U << 5)   /**< PVD level 2.               */
+#define STM32_PLS_LEV3          (3U << 5)   /**< PVD level 3.               */
+#define STM32_PLS_LEV4          (4U << 5)   /**< PVD level 4.               */
+#define STM32_PLS_LEV5          (5U << 5)   /**< PVD level 5.               */
+#define STM32_PLS_LEV6          (6U << 5)   /**< PVD level 6.               */
+#define STM32_PLS_LEV7          (7U << 5)   /**< PVD level 7.               */
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI            (0U << 0)   /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1U << 0)   /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2U << 0)   /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_DIV1         (0U << 4)   /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8u << 4)   /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9U << 4)   /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10U << 4)  /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11U << 4)  /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12U << 4)  /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13U << 4)  /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14U << 4)  /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15U << 4)  /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE1_DIV1        (0U << 8)   /**< HCLK divided by 1.         */
+#define STM32_PPRE1_DIV2        (4U << 8)   /**< HCLK divided by 2.         */
+#define STM32_PPRE1_DIV4        (5U << 8)   /**< HCLK divided by 4.         */
+#define STM32_PPRE1_DIV8        (6U << 8)   /**< HCLK divided by 8.         */
+#define STM32_PPRE1_DIV16       (7U << 8)   /**< HCLK divided by 16.        */
+
+#define STM32_PPRE2_DIV1        (0U << 11)  /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4U << 11)  /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5U << 11)  /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6U << 11)  /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7U << 11)  /**< HCLK divided by 16.        */
+
+#define STM32_ADCPRE_DIV2       (0U << 14)  /**< PPRE2 divided by 2.        */
+#define STM32_ADCPRE_DIV4       (1U << 14)  /**< PPRE2 divided by 4.        */
+#define STM32_ADCPRE_DIV6       (2U << 14)  /**< PPRE2 divided by 6.        */
+#define STM32_ADCPRE_DIV8       (3U << 14)  /**< PPRE2 divided by 8.        */
+
+#define STM32_PLLSRC_HSI        (0U << 16)  /**< PLL clock source is HSI/2. */
+#define STM32_PLLSRC_HSE        (1U << 16)  /**< PLL clock source is
+                                                 HSE/PREDIV.                */
+
+#define STM32_USBPRE_DIV1P5     (0U << 22)  /**< USB clock is PLLCLK/1.5.   */
+#define STM32_USBPRE_DIV1       (1U << 22)  /**< USB clock is PLLCLK/1.     */
+
+#define STM32_MCOSEL_NOCLOCK    (0U << 24)  /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_LSI        (2U << 24)  /**< LSI clock on MCO pin.      */
+#define STM32_MCOSEL_LSE        (3U << 24)  /**< LSE clock on MCO pin.      */
+#define STM32_MCOSEL_SYSCLK     (4U << 24)  /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (5U << 24)  /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (6U << 24)  /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLLDIV2    (7U << 24)  /**< PLL/2 clock on MCO pin.    */
+
+#define STM32_SDPRE_DIV2        (16U << 27) /**< SYSCLK divided by 2.       */
+#define STM32_SDPRE_DIV4        (17U << 27) /**< SYSCLK divided by 4.       */
+#define STM32_SDPRE_DIV6        (18U << 27) /**< SYSCLK divided by 6.       */
+#define STM32_SDPRE_DIV8        (19U << 27) /**< SYSCLK divided by 8.       */
+#define STM32_SDPRE_DIV10       (20U << 27) /**< SYSCLK divided by 10.      */
+#define STM32_SDPRE_DIV12       (21U << 27) /**< SYSCLK divided by 12.      */
+#define STM32_SDPRE_DIV14       (22U << 27) /**< SYSCLK divided by 14.      */
+#define STM32_SDPRE_DIV16       (23U << 27) /**< SYSCLK divided by 16.      */
+#define STM32_SDPRE_DIV20       (24U << 27) /**< SYSCLK divided by 20.      */
+#define STM32_SDPRE_DIV24       (25U << 27) /**< SYSCLK divided by 24.      */
+#define STM32_SDPRE_DIV28       (26U << 27) /**< SYSCLK divided by 28.      */
+#define STM32_SDPRE_DIV32       (27U << 27) /**< SYSCLK divided by 32.      */
+#define STM32_SDPRE_DIV36       (28U << 27) /**< SYSCLK divided by 36.      */
+#define STM32_SDPRE_DIV40       (29U << 27) /**< SYSCLK divided by 40.      */
+#define STM32_SDPRE_DIV44       (30U << 27) /**< SYSCLK divided by 44.      */
+#define STM32_SDPRE_DIV48       (31U << 27) /**< SYSCLK divided by 48.      */
+/** @} */
+
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3U << 8)   /**< RTC clock source mask.     */
+#define STM32_RTCSEL_NOCLOCK    (0U << 8)   /**< No clock.                  */
+#define STM32_RTCSEL_LSE        (1U << 8)   /**< LSE used as RTC clock.     */
+#define STM32_RTCSEL_LSI        (2U << 8)   /**< LSI used as RTC clock.     */
+#define STM32_RTCSEL_HSEDIV     (3U << 8)   /**< HSE divided by 32 used as
+                                                 RTC clock.                 */
+/** @} */
+
+/**
+ * @name    RCC_CFGR2 register bits definitions
+ * @{
+ */
+#define STM32_PREDIV_MASK       (15U << 0)  /**< PREDIV divisor mask.       */
+/** @} */
+
+/**
+ * @name    RCC_CFGR3 register bits definitions
+ * @{
+ */
+#define STM32_USART1SW_MASK     (3U << 0)   /**< USART1 clock source mask. */
+#define STM32_USART1SW_PCLK     (0U << 0)   /**< USART1 clock is PCLK.     */
+#define STM32_USART1SW_SYSCLK   (1U << 0)   /**< USART1 clock is SYSCLK.   */
+#define STM32_USART1SW_LSE      (2U << 0)   /**< USART1 clock is LSE.      */
+#define STM32_USART1SW_HSI      (3U << 0)   /**< USART1 clock is HSI.      */
+#define STM32_I2C1SW_MASK       (1U << 4)   /**< I2C1 clock source mask.   */
+#define STM32_I2C1SW_HSI        (0U << 4)   /**< I2C1 clock is HSI.        */
+#define STM32_I2C1SW_SYSCLK     (1U << 4)   /**< I2C1 clock is SYSCLK.     */
+#define STM32_I2C2SW_MASK       (1U << 5)   /**< I2C2 clock source mask.   */
+#define STM32_I2C2SW_HSI        (0U << 5)   /**< I2C2 clock is HSI.        */
+#define STM32_I2C2SW_SYSCLK     (1U << 5)   /**< I2C2 clock is SYSCLK.     */
+#define STM32_USART2SW_MASK     (3U << 16)  /**< USART2 clock source mask. */
+#define STM32_USART2SW_PCLK     (0U << 16)  /**< USART2 clock is PCLK.     */
+#define STM32_USART2SW_SYSCLK   (1U << 16)  /**< USART2 clock is SYSCLK.   */
+#define STM32_USART2SW_LSE      (2U << 16)  /**< USART2 clock is LSE.      */
+#define STM32_USART2SW_HSI      (3U << 16)  /**< USART2 clock is HSI.      */
+#define STM32_USART3SW_MASK     (3U << 18)  /**< USART3 clock source mask. */
+#define STM32_USART3SW_PCLK     (0U << 18)  /**< USART3 clock is PCLK.     */
+#define STM32_USART3SW_SYSCLK   (1U << 18)  /**< USART3 clock is SYSCLK.   */
+#define STM32_USART3SW_LSE      (2U << 18)  /**< USART3 clock is LSE.      */
+#define STM32_USART3SW_HSI      (3U << 18)  /**< USART3 clock is HSI.      */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT                       FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE                    FALSE
+#endif
+
+/**
+ * @brief   Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                           STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief   Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED                   TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED                   TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED                   TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED                   FALSE
+#endif
+
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                            STM32_SW_PLL
+#endif
+
+/**
+ * @brief   Clock source for the PLL.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                        STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief   Crystal PLL pre-divider.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PREDIV_VALUE                  1
+#endif
+
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed range is 2...16.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE                  9
+#endif
+
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                          STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1                         STM32_PPRE1_DIV2
+#endif
+
+/**
+ * @brief   APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2                         STM32_PPRE2_DIV2
+#endif
+
+/**
+ * @brief   MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief   ADC prescaler value.
+ */
+#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADCPRE                        STM32_ADCPRE_DIV4
+#endif
+
+/**
+ * @brief   SDADC prescaler value.
+ */
+#if !defined(STM32_SDPRE) || defined(__DOXYGEN__)
+#define STM32_SDPRE                         STM32_SDPRE_DIV12
+#endif
+
+/**
+ * @brief   USART1 clock source.
+ */
+#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
+#define STM32_USART1SW                      STM32_USART1SW_PCLK
+#endif
+
+/**
+ * @brief   USART2 clock source.
+ */
+#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
+#define STM32_USART2SW                      STM32_USART2SW_PCLK
+#endif
+
+/**
+ * @brief   USART3 clock source.
+ */
+#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
+#define STM32_USART3SW                      STM32_USART3SW_PCLK
+#endif
+
+/**
+ * @brief   I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
+#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK
+#endif
+
+/**
+ * @brief   I2C2 clock source.
+ */
+#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
+#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK
+#endif
+
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                        STM32_RTCSEL_LSI
+#endif
+
+/**
+ * @brief   USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_REQUIRED            TRUE
+#endif
+
+/**
+ * @brief   USB prescaler initialization.
+ */
+#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
+#define STM32_USBPRE                        STM32_USBPRE_DIV1P5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F37x_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F37x_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_HSI
+#error "HSI not enabled, required by STM32_USART1SW"
+#endif
+
+#if STM32_USART2SW == STM32_USART2SW_HSI
+#error "HSI not enabled, required by STM32_USART2SW"
+#endif
+
+#if STM32_USART3SW == STM32_USART3SW_HSI
+#error "HSI not enabled, required by STM32_USART3SW"
+#endif
+
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#error "HSI not enabled, required by STM32_I2C1SW"
+#endif
+
+#if STM32_I2C2SW == STM32_I2C2SW_HSI
+#error "HSI not enabled, required by STM32_I2C2SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0)
+#error "STM32_LSECLK not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined"
+#endif
+
+#if (STM32_LSEDRV >> 3) > 3
+#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_LSE
+#error "LSE not enabled, required by STM32_USART1SW"
+#endif
+
+#if STM32_USART2SW == STM32_USART2SW_LSE
+#error "LSE not enabled, required by STM32_USART2SW"
+#endif
+
+#if STM32_USART3SW == STM32_USART3SW_LSE
+#error "LSE not enabled, required by STM32_USART3SW"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
+    STM32_USB_CLOCK_REQUIRED ||                                             \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+
+/* HSE prescaler setting check.*/
+#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
+#define STM32_PREDIV                ((STM32_PREDIV_VALUE - 1) << 0)
+#else
+#error "invalid STM32_PREDIV value specified"
+#endif
+
+/**
+ * @brief   PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PREDIV_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                  (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                  (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                  (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                  (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                  (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                  (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                  (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                  (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                  (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                  (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                (STM32_HSECLK / 32)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK                0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief   ADC frequency.
+ */
+#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_ADCCLK                (STM32_PCLK2 / 2)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
+#define STM32_ADCCLK                (STM32_PCLK2 / 4)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
+#define STM32_ADCCLK                (STM32_PCLK2 / 6)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
+#define STM32_ADCCLK                (STM32_PCLK2 / 8)
+#else
+#error "invalid STM32_ADCPRE value specified"
+#endif
+
+/* ADC maximum frequency check.*/
+#if STM32_ADCCLK > STM32_ADCCLK_MAX
+#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/* ADC minimum frequency check.*/
+#if STM32_ADCCLK < STM32_ADCCLK_MIN
+#error "STM32_ADCCLK exceeding minimum frequency (STM32_ADCCLK_MIN)"
+#endif
+
+/**
+ * @brief   SDADC frequency.
+ */
+#if (STM32_SDPRE == STM32_SDPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 2)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV4) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 4)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV6) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 6)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV8) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 8)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV10) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 10)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV12) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 12)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV14) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 14)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV16) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 16)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV20) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 20)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV24) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 24)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV28) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 28)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV32) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 32)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV36) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 36)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV40) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 40)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV44) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 44)
+#elif (STM32_SDPRE == STM32_SDPRE_DIV48) || defined(__DOXYGEN__)
+#define STM32_SDADCCLK              (STM32_SYSCLK / 48)
+#else
+#error "invalid STM32_SDPRE value specified"
+#endif
+
+/* SDADC maximum frequency check.*/
+#if STM32_SDADCCLK > STM32_SDADCCLK_FAST_MAX
+#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_FAST_MAX)"
+#endif
+
+/* SDADC minimum frequency check.*/
+#if STM32_SDADCCLK < STM32_SDADCCLK_MIN
+#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_MIN)"
+#endif
+
+/**
+ * @brief   I2C1 frequency.
+ */
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#define STM32_I2C1CLK               STM32_HSICLK
+#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
+#define STM32_I2C1CLK               STM32_SYSCLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief   I2C2 frequency.
+ */
+#if STM32_I2C2SW == STM32_I2C2SW_HSI
+#define STM32_I2C2CLK               STM32_HSICLK
+#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK
+#define STM32_I2C2CLK               STM32_SYSCLK
+#else
+#error "invalid source selected for I2C2 clock"
+#endif
+
+/**
+ * @brief   USART1 frequency.
+ */
+#if STM32_USART1SW == STM32_USART1SW_PCLK
+#define STM32_USART1CLK             STM32_PCLK2
+#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
+#define STM32_USART1CLK             STM32_SYSCLK
+#elif STM32_USART1SW == STM32_USART1SW_LSECLK
+#define STM32_USART1CLK             STM32_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_HSICLK
+#define STM32_USART1CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief   USART2 frequency.
+ */
+#if STM32_USART2SW == STM32_USART2SW_PCLK
+#define STM32_USART2CLK             STM32_PCLK1
+#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
+#define STM32_USART2CLK             STM32_SYSCLK
+#elif STM32_USART2SW == STM32_USART2SW_LSECLK
+#define STM32_USART2CLK             STM32_LSECLK
+#elif STM32_USART2SW == STM32_USART2SW_HSICLK
+#define STM32_USART2CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART2 clock"
+#endif
+
+/**
+ * @brief   USART3 frequency.
+ */
+#if STM32_USART3SW == STM32_USART3SW_PCLK
+#define STM32_USART3CLK             STM32_PCLK1
+#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
+#define STM32_USART3CLK             STM32_SYSCLK
+#elif STM32_USART3SW == STM32_USART3SW_LSECLK
+#define STM32_USART3CLK             STM32_LSECLK
+#elif STM32_USART3SW == STM32_USART3SW_HSICLK
+#define STM32_USART3CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART3 clock"
+#endif
+
+/**
+ * @brief   Timers 2, 3, 4, 5, 6, 7, 12, 13, 14, 18 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief   Timers 15, 16, 17, 19 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief   USB frequency.
+ */
+#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
+#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
+#define STM32_USBCLK                STM32_PLLCLKOUT
+#else
+#error "invalid STM32_USBPRE value specified"
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS             0x00000011
+#else
+#define STM32_FLASHBITS             0x00000012
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F37x/platform.mk b/os/hal/ports/STM32/STM32F37x/platform.mk
new file mode 100644
index 000000000..07dcf38af
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F37x/platform.mk
@@ -0,0 +1,31 @@
+# List of all the STM32F37x platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F37x/stm32_dma.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F37x/hal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F37x/adc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/can_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/ext_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F37x \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1
diff --git a/os/hal/ports/STM32/STM32F37x/stm32_dma.c b/os/hal/ports/STM32/STM32F37x/stm32_dma.c
new file mode 100644
index 000000000..4e9052ab1
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F37x/stm32_dma.c
@@ -0,0 +1,449 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F37x/stm32_dma.c
+ * @brief   DMA helper driver code.
+ *
+ * @addtogroup STM32F37x_DMA
+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a
+ *          shared resource, this driver allows to allocate and free DMA
+ *          streams at runtime in order to allow all the other device
+ *          drivers to coordinate the access to the resource.
+ * @note    The DMA ISR handlers are all declared into this module because
+ *          sharing, the various device drivers can associate a callback to
+ *          ISRs when allocating streams.
+ * @{
+ */
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA1_STREAMS_MASK     0x0000007F
+
+/**
+ * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA2_STREAMS_MASK     0x00000F80
+
+/**
+ * @brief   Post-reset value of the stream CCR register.
+ */
+#define STM32_DMA_CCR_RESET_VALUE   0x00000000
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ *          identifier and the involved physical registers.
+ * @note    Don't use this array directly, use the appropriate wrapper macros
+ *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
+ */
+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
+  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
+  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
+  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
+  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
+  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
+  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
+  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
+  {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
+  {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
+  {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
+  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
+  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
+};
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA ISR redirector type.
+ */
+typedef struct {
+  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
+  void                  *dma_param;     /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
+/**
+ * @brief   Mask of the allocated streams.
+ */
+static uint32_t dma_streams_mask;
+
+/**
+ * @brief   DMA IRQ redirectors.
+ */
+static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA1 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector6C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 0;
+  if (dma_isr_redir[0].dma_func)
+    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 4;
+  if (dma_isr_redir[1].dma_func)
+    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector74) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 8;
+  if (dma_isr_redir[2].dma_func)
+    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector78) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 12;
+  if (dma_isr_redir[3].dma_func)
+    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector7C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 16;
+  if (dma_isr_redir[4].dma_func)
+    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 6 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector80) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 20;
+  if (dma_isr_redir[5].dma_func)
+    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 7 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector84) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 24;
+  if (dma_isr_redir[6].dma_func)
+    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector120) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 0;
+  if (dma_isr_redir[7].dma_func)
+    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector124) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 4;
+  if (dma_isr_redir[8].dma_func)
+    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector128) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 8;
+  if (dma_isr_redir[9].dma_func)
+    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector12C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 12;
+  if (dma_isr_redir[10].dma_func)
+    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector130) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 16;
+  if (dma_isr_redir[11].dma_func)
+    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+  int i;
+
+  dma_streams_mask = 0;
+  for (i = 0; i < STM32_DMA_STREAMS; i++) {
+    _stm32_dma_streams[i].channel->CCR = 0;
+    dma_isr_redir[i].dma_func = NULL;
+  }
+  DMA1->IFCR = 0xFFFFFFFF;
+#if STM32_HAS_DMA2
+  DMA2->IFCR = 0xFFFFFFFF;
+#endif
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ * @pre     The stream must not be already in use or an error is returned.
+ * @post    The stream is allocated and the default ISR handler redirected
+ *          to the specified function.
+ * @post    The stream ISR vector is enabled and its priority configured.
+ * @post    The stream must be freed using @p dmaStreamRelease() before it can
+ *          be reused with another peripheral.
+ * @post    The stream is in its post-reset state.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] priority  IRQ priority mask for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              The operation status.
+ * @retval FALSE        no error, stream taken.
+ * @retval TRUE         error, stream already taken.
+ *
+ * @special
+ */
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                       uint32_t priority,
+                       stm32_dmaisr_t func,
+                       void *param) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Checks if the stream is already taken.*/
+  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
+    return TRUE;
+
+  /* Marks the stream as allocated.*/
+  dma_isr_redir[dmastp->selfindex].dma_func  = func;
+  dma_isr_redir[dmastp->selfindex].dma_param = param;
+  dma_streams_mask |= (1 << dmastp->selfindex);
+
+  /* Enabling DMA clocks required by the current streams set.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
+    rccEnableDMA1(FALSE);
+#if STM32_HAS_DMA2
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
+    rccEnableDMA2(FALSE);
+#endif
+
+  /* Putting the stream in a safe state.*/
+  dmaStreamDisable(dmastp);
+  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
+
+  /* Enables the associated IRQ vector if a callback is defined.*/
+  if (func != NULL)
+    nvicEnableVector(dmastp->vector, priority);
+
+  return FALSE;
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    The stream is again available.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Check if the streams is not taken.*/
+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+                "not allocated");
+
+  /* Disables the associated IRQ vector.*/
+  nvicDisableVector(dmastp->vector);
+
+  /* Marks the stream as not allocated.*/
+  dma_streams_mask &= ~(1 << dmastp->selfindex);
+
+  /* Shutting down clocks that are no more required, if any.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
+    rccDisableDMA1(FALSE);
+#if STM32_HAS_DMA2
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
+    rccDisableDMA2(FALSE);
+#endif
+}
+
+#endif /* STM32_DMA_REQUIRED */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F37x/stm32_dma.h b/os/hal/ports/STM32/STM32F37x/stm32_dma.h
new file mode 100644
index 000000000..e77b3ba77
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F37x/stm32_dma.h
@@ -0,0 +1,406 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F37x/stm32_dma.h
+ * @brief   DMA helper driver header.
+ * @note    This file requires definitions from the ST header file stm32f30x.h.
+ * @note    This driver uses the new naming convention used for the STM32F2xx
+ *          so the "DMA channels" are referred as "DMA streams".
+ *
+ * @addtogroup STM32F37x_DMA
+ * @{
+ */
+
+#ifndef _STM32_DMA_H_
+#define _STM32_DMA_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Total number of DMA streams.
+ * @note    This is the total number of streams among all the DMA units.
+ */
+#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
+#define STM32_DMA_STREAMS           12
+#else
+#define STM32_DMA_STREAMS           7
+#endif
+
+/**
+ * @brief   Mask of the ISR bits passed to the DMA callback functions.
+ */
+#define STM32_DMA_ISR_MASK          0x0F
+
+/**
+ * @brief   Returns the channel associated to the specified stream.
+ *
+ * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
+ * @param[in] c         a stream/channel association word, one channel per
+ *                      nibble, not associated channels must be set to 0xF
+ * @return              Always zero, in this platform there is no dynamic
+ *                      association between streams and channels.
+ */
+#define STM32_DMA_GETCHANNEL(n, c)  0
+
+/**
+ * @brief   Checks if a DMA priority is within the valid range.
+ * @param[in] prio      DMA priority
+ *
+ * @retval              The check result.
+ * @retval FALSE        invalid DMA priority.
+ * @retval TRUE         correct DMA priority.
+ */
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+
+/**
+ * @brief   Returns an unique numeric identifier for a DMA stream.
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              An unique numeric stream identifier.
+ */
+#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
+
+/**
+ * @brief   Returns a DMA stream identifier mask.
+ *
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              A DMA stream identifier mask.
+ */
+#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
+  (1 << STM32_DMA_STREAM_ID(dma, stream))
+
+/**
+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.
+ * @param[in] id        the stream numeric identifier
+ * @param[in] mask      the stream numeric identifiers mask
+ *
+ * @retval              The check result.
+ * @retval FALSE        id does not belong to the mask.
+ * @retval TRUE         id belongs to the mask.
+ */
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+
+/**
+ * @name    DMA streams identifiers
+ * @{
+ */
+/**
+ * @brief   Returns a pointer to a stm32_dma_stream_t structure.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @return              A pointer to the stm32_dma_stream_t constant structure
+ *                      associated to the DMA stream.
+ */
+#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
+
+#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
+#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
+#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
+#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
+#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
+#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
+#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
+#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(7)
+#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(8)
+#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(9)
+#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(10)
+#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(11)
+/** @} */
+
+/**
+ * @name    CR register constants common to all DMA types
+ * @{
+ */
+#define STM32_DMA_CR_EN             DMA_CCR_EN
+#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE
+#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE
+#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE
+#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
+#define STM32_DMA_CR_DIR_P2M        0
+#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR
+#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM
+#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC
+#define STM32_DMA_CR_PINC           DMA_CCR_PINC
+#define STM32_DMA_CR_MINC           DMA_CCR_MINC
+#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE
+#define STM32_DMA_CR_PSIZE_BYTE     0
+#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0
+#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1
+#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE
+#define STM32_DMA_CR_MSIZE_BYTE     0
+#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
+#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
+                                     STM32_DMA_CR_MSIZE_MASK)
+#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
+#define STM32_DMA_CR_PL(n)          ((n) << 12)
+/** @} */
+
+/**
+ * @name    CR register constants only found in enhanced DMA
+ * @{
+ */
+#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
+/** @} */
+
+/**
+ * @name    Status flags passed to the ISR callbacks
+ * @{
+ */
+#define STM32_DMA_ISR_FEIF          0
+#define STM32_DMA_ISR_DMEIF         0
+#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
+#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
+#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA stream descriptor structure.
+ */
+typedef struct {
+  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
+  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
+  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
+                                             register.                      */
+  uint8_t               selfindex;      /**< @brief Index to self in array. */
+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
+} stm32_dma_stream_t;
+
+/**
+ * @brief   STM32 DMA ISR function type.
+ *
+ * @param[in] p         parameter for the registered function
+ * @param[in] flags     pre-shifted content of the ISR register, the bits
+ *                      are aligned to bit zero
+ */
+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Associates a peripheral data register to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CPAR register
+ *
+ * @special
+ */
+#define dmaStreamSetPeripheral(dmastp, addr) {                              \
+  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Associates a memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CMAR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory0(dmastp, addr) {                                 \
+  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Sets the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] size      value to be written in the CNDTR register
+ *
+ * @special
+ */
+#define dmaStreamSetTransactionSize(dmastp, size) {                         \
+  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
+}
+
+/**
+ * @brief   Returns the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @return              The number of transfers to be performed.
+ *
+ * @special
+ */
+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
+
+/**
+ * @brief   Programs the stream mode settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register
+ *
+ * @special
+ */
+#define dmaStreamSetMode(dmastp, mode) {                                    \
+  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
+}
+
+/**
+ * @brief   DMA stream enable.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamEnable(dmastp) {                                           \
+  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
+}
+
+/**
+ * @brief   DMA stream disable.
+ * @details The function disables the specified stream and then clears any
+ *          pending interrupt.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @note    Interrupts enabling flags are set to zero after this call, see
+ *          bug 3607518.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamDisable(dmastp) {                                          \
+  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
+                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
+  dmaStreamClearInterrupt(dmastp);                                          \
+}
+
+/**
+ * @brief   DMA stream interrupt sources clear.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamClearInterrupt(dmastp) {                                   \
+  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
+}
+
+/**
+ * @brief   Starts a memory to memory operation using the specified stream.
+ * @note    The default transfer data mode is "byte to byte" but it can be
+ *          changed by specifying extra options in the @p mode parameter.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register, this value
+ *                      is implicitly ORed with:
+ *                      - @p STM32_DMA_CR_MINC
+ *                      - @p STM32_DMA_CR_PINC
+ *                      - @p STM32_DMA_CR_DIR_M2M
+ *                      - @p STM32_DMA_CR_EN
+ *                      .
+ * @param[in] src       source address
+ * @param[in] dst       destination address
+ * @param[in] n         number of data units to copy
+ */
+#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
+  dmaStreamSetPeripheral(dmastp, src);                                      \
+  dmaStreamSetMemory0(dmastp, dst);                                         \
+  dmaStreamSetTransactionSize(dmastp, n);                                   \
+  dmaStreamSetMode(dmastp, (mode) |                                         \
+                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
+                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
+}
+
+/**
+ * @brief   Polled wait for DMA transfer end.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ */
+#define dmaWaitCompletion(dmastp) {                                         \
+  while ((dmastp)->channel->CNDTR > 0)                                      \
+    ;                                                                       \
+  dmaStreamDisable(dmastp);                                                 \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dmaInit(void);
+  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                         uint32_t priority,
+                         stm32_dmaisr_t func,
+                         void *param);
+  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_DMA_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F37x/stm32_isr.h b/os/hal/ports/STM32/STM32F37x/stm32_isr.h
index 30d98163e..30d98163e 100644
--- a/os/hal/platforms/STM32F37x/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F37x/stm32_isr.h
diff --git a/os/hal/platforms/STM32F37x/stm32_rcc.h b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h
index 607d9d7bc..607d9d7bc 100644
--- a/os/hal/platforms/STM32F37x/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h
diff --git a/os/hal/ports/STM32/STM32F37x/stm32_registry.h b/os/hal/ports/STM32/STM32F37x/stm32_registry.h
new file mode 100644
index 000000000..61bde9281
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F37x/stm32_registry.h
@@ -0,0 +1,203 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F37x/stm32_registry.h
+ * @brief   STM32F37x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    STM32F37x capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    TRUE
+#define STM32_HAS_SDADC2                    TRUE
+#define STM32_HAS_SDADC3                    TRUE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             29
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_IS_CALENDAR               TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM5                      TRUE
+#define STM32_TIM5_IS_32BITS                TRUE
+#define STM32_TIM5_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM12                     TRUE
+#define STM32_TIM12_IS_32BITS               FALSE
+#define STM32_TIM12_CHANNELS                2
+
+#define STM32_HAS_TIM13                     TRUE
+#define STM32_TIM13_IS_32BITS               FALSE
+#define STM32_TIM13_CHANNELS                2
+
+#define STM32_HAS_TIM14                     TRUE
+#define STM32_TIM14_IS_32BITS               FALSE
+#define STM32_TIM14_CHANNELS                2
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM18                     TRUE
+#define STM32_TIM18_IS_32BITS               FALSE
+#define STM32_TIM18_CHANNELS                0
+
+#define STM32_HAS_TIM19                     TRUE
+#define STM32_TIM19_IS_32BITS               FALSE
+#define STM32_TIM19_CHANNELS                4
+
+#define STM32_HAS_TIM1                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/adc_lld.c b/os/hal/ports/STM32/STM32F4xx/adc_lld.c
new file mode 100644
index 000000000..2e3f27238
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/adc_lld.c
@@ -0,0 +1,418 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F4xx/adc_lld.c
+ * @brief   STM32F4xx/STM32F2xx ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define ADC1_DMA_CHANNEL                                                    \
+  STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
+
+#define ADC2_DMA_CHANNEL                                                    \
+  STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
+
+#define ADC3_DMA_CHANNEL                                                    \
+  STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/** @brief ADC2 driver identifier.*/
+#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
+ADCDriver ADCD2;
+#endif
+
+/** @brief ADC3 driver identifier.*/
+#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
+ADCDriver ADCD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC DMA ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    /* DMA, this could help only if the DMA tries to access an unmapped
+       address space or violates alignment rules.*/
+    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+  }
+  else {
+    /* It is possible that the conversion group has already be reset by the
+       ADC error handler, in this case this interrupt is spurious.*/
+    if (adcp->grpp != NULL) {
+      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+        /* Transfer complete processing.*/
+        _adc_isr_full_code(adcp);
+      }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 ||       \
+    defined(__DOXYGEN__)
+/**
+ * @brief   ADC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
+  uint32_t sr;
+
+  OSAL_IRQ_PROLOGUE();
+
+#if STM32_ADC_USE_ADC1
+  sr = ADC1->SR;
+  ADC1->SR = 0;
+  /* Note, an overflow may occur after the conversion ended before the driver
+     is able to stop the ADC, this is why the DMA channel is checked too.*/
+  if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
+    /* ADC overflow condition, this could happen only if the DMA is unable
+       to read data fast enough.*/
+    if (ADCD1.grpp != NULL)
+      _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+  }
+  /* TODO: Add here analog watchdog handling.*/
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_ADC2
+  sr = ADC2->SR;
+  ADC2->SR = 0;
+  /* Note, an overflow may occur after the conversion ended before the driver
+     is able to stop the ADC, this is why the DMA channel is checked too.*/
+  if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) {
+    /* ADC overflow condition, this could happen only if the DMA is unable
+       to read data fast enough.*/
+    if (ADCD2.grpp != NULL)
+      _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW);
+  }
+  /* TODO: Add here analog watchdog handling.*/
+#endif /* STM32_ADC_USE_ADC2 */
+
+#if STM32_ADC_USE_ADC3
+  sr = ADC3->SR;
+  ADC3->SR = 0;
+  /* Note, an overflow may occur after the conversion ended before the driver
+     is able to stop the ADC, this is why the DMA channel is checked too.*/
+  if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) {
+    /* ADC overflow condition, this could happen only if the DMA is unable
+       to read data fast enough.*/
+    if (ADCD3.grpp != NULL)
+      _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW);
+  }
+  /* TODO: Add here analog watchdog handling.*/
+#endif /* STM32_ADC_USE_ADC3 */
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adc = ADC1;
+  ADCD1.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
+  ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_ADC_USE_ADC2
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD2);
+  ADCD2.adc = ADC2;
+  ADCD2.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
+  ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_ADC_USE_ADC3
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD3);
+  ADCD3.adc = ADC3;
+  ADCD3.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
+  ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+#endif
+
+  /* The shared vector is initialized on driver initialization and never
+     disabled.*/
+  nvicEnableVector(ADC_IRQn, STM32_ADC_IRQ_PRIORITY);
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+  /* If in stopped state then enables the ADC and DMA clocks.*/
+  if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      bool b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+                            (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+      rccEnableADC1(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_ADC2
+    if (&ADCD2 == adcp) {
+      bool b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+                            (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
+      rccEnableADC2(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC2 */
+
+#if STM32_ADC_USE_ADC3
+    if (&ADCD3 == adcp) {
+      bool b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+                            (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
+      rccEnableADC3(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC3 */
+
+    /* This is a common register but apparently it requires that at least one
+       of the ADCs is clocked in order to allow writing, see bug 3575297.*/
+    ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) |
+               (STM32_ADC_ADCPRE << 16);
+
+    /* ADC initial setup, starting the analog part here in order to reduce
+       the latency when starting a conversion.*/
+    adcp->adc->CR1 = 0;
+    adcp->adc->CR2 = 0;
+    adcp->adc->CR2 = ADC_CR2_ADON;
+  }
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+  /* If in ready state then disables the ADC clock.*/
+  if (adcp->state == ADC_READY) {
+    dmaStreamRelease(adcp->dmastp);
+    adcp->adc->CR1 = 0;
+    adcp->adc->CR2 = 0;
+
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp)
+      rccDisableADC1(FALSE);
+#endif
+
+#if STM32_ADC_USE_ADC2
+    if (&ADCD2 == adcp)
+      rccDisableADC2(FALSE);
+#endif
+
+#if STM32_ADC_USE_ADC3
+    if (&ADCD3 == adcp)
+      rccDisableADC3(FALSE);
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+  uint32_t mode;
+  const ADCConversionGroup *grpp = adcp->grpp;
+
+  /* DMA setup.*/
+  mode = adcp->dmamode;
+  if (grpp->circular) {
+    mode |= STM32_DMA_CR_CIRC;
+    if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
+    }
+  }
+  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+                                            (uint32_t)adcp->depth);
+  dmaStreamSetMode(adcp->dmastp, mode);
+  dmaStreamEnable(adcp->dmastp);
+
+  /* ADC setup.*/
+  adcp->adc->SR    = 0;
+  adcp->adc->SMPR1 = grpp->smpr1;
+  adcp->adc->SMPR2 = grpp->smpr2;
+  adcp->adc->SQR1  = grpp->sqr1;
+  adcp->adc->SQR2  = grpp->sqr2;
+  adcp->adc->SQR3  = grpp->sqr3;
+
+  /* ADC configuration and start, the start is performed using the method
+     specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
+  adcp->adc->CR1   = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
+  if ((grpp->cr2 & ADC_CR2_SWSTART) != 0)
+    adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
+                                 ADC_CR2_DDS   | ADC_CR2_ADON;
+  else
+    adcp->adc->CR2 = grpp->cr2 |                 ADC_CR2_DMA |
+                                 ADC_CR2_DDS   | ADC_CR2_ADON;
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+  dmaStreamDisable(adcp->dmastp);
+  adcp->adc->CR1 = 0;
+  adcp->adc->CR2 = 0;
+  adcp->adc->CR2 = ADC_CR2_ADON;
+}
+
+/**
+ * @brief   Enables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ *          temperature sensor and internal reference voltage.
+ * @note    This is an STM32-only functionality.
+ */
+void adcSTM32EnableTSVREFE(void) {
+
+  ADC->CCR |= ADC_CCR_TSVREFE;
+}
+
+/**
+ * @brief   Disables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ *          temperature sensor and internal reference voltage.
+ * @note    This is an STM32-only functionality.
+ */
+void adcSTM32DisableTSVREFE(void) {
+
+  ADC->CCR &= ~ADC_CCR_TSVREFE;
+}
+
+/**
+ * @brief   Enables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note    This is an STM32-only functionality.
+ * @note    This function is meant to be called after @p adcStart().
+ */
+void adcSTM32EnableVBATE(void) {
+
+  ADC->CCR |= ADC_CCR_VBATE;
+}
+
+/**
+ * @brief   Disables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note    This is an STM32-only functionality.
+ * @note    This function is meant to be called after @p adcStart().
+ */
+void adcSTM32DisableVBATE(void) {
+
+  ADC->CCR &= ~ADC_CCR_VBATE;
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/adc_lld.h b/os/hal/ports/STM32/STM32F4xx/adc_lld.h
new file mode 100644
index 000000000..6b6530a61
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/adc_lld.h
@@ -0,0 +1,563 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F4xx/adc_lld.h
+ * @brief   STM32F4xx/STM32F2xx ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Minimum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MIN        600000
+
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#if defined(STM32F4XX) || defined(__DOXYGEN__)
+#define STM32_ADCCLK_MAX        36000000
+#else
+#define STM32_ADCCLK_MAX        30000000
+#endif
+/** @} */
+
+/**
+ * @name    Triggers selection
+ * @{
+ */
+#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 24) /**< @brief Trigger source.     */
+/** @} */
+
+/**
+ * @name    ADC clock divider settings
+ * @{
+ */
+#define ADC_CCR_ADCPRE_DIV2     0
+#define ADC_CCR_ADCPRE_DIV4     1
+#define ADC_CCR_ADCPRE_DIV6     2
+#define ADC_CCR_ADCPRE_DIV8     3
+/** @} */
+
+/**
+ * @name    Available analog channels
+ * @{
+ */
+#define ADC_CHANNEL_IN0         0   /**< @brief External analog input 0.    */
+#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
+#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
+#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
+#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
+#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
+#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
+#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
+#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
+#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
+#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
+#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
+#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
+#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
+#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
+#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
+#define ADC_CHANNEL_SENSOR      16  /**< @brief Internal temperature sensor.
+                                         @note Available onADC1 only.       */
+#define ADC_CHANNEL_VREFINT     17  /**< @brief Internal reference.
+                                         @note Available onADC1 only.       */
+#define ADC_CHANNEL_VBAT        18  /**< @brief VBAT.
+                                         @note Available onADC1 only.       */
+/** @} */
+
+/**
+ * @name    Sampling rates
+ * @{
+ */
+#define ADC_SAMPLE_3            0   /**< @brief 3 cycles sampling time.     */
+#define ADC_SAMPLE_15           1   /**< @brief 15 cycles sampling time.    */
+#define ADC_SAMPLE_28           2   /**< @brief 28 cycles sampling time.    */
+#define ADC_SAMPLE_56           3   /**< @brief 56 cycles sampling time.    */
+#define ADC_SAMPLE_84           4   /**< @brief 84 cycles sampling time.    */
+#define ADC_SAMPLE_112          5   /**< @brief 112 cycles sampling time.   */
+#define ADC_SAMPLE_144          6   /**< @brief 144 cycles sampling time.   */
+#define ADC_SAMPLE_480          7   /**< @brief 480 cycles sampling time.   */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   ADC common clock divider.
+ * @note    This setting is influenced by the VDDA voltage and other
+ *          external conditions, please refer to the datasheet for more
+ *          info.<br>
+ *          See section 5.3.20 "12-bit ADC characteristics".
+ */
+#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV2
+#endif
+
+/**
+ * @brief   ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1                  FALSE
+#endif
+
+/**
+ * @brief   ADC2 driver enable switch.
+ * @details If set to @p TRUE the support for ADC2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC2                  FALSE
+#endif
+
+/**
+ * @brief   ADC3 driver enable switch.
+ * @details If set to @p TRUE the support for ADC3 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC3                  FALSE
+#endif
+
+/**
+ * @brief   DMA stream used for ADC1 operations.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
+#endif
+
+/**
+ * @brief   DMA stream used for ADC2 operations.
+ */
+#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
+#endif
+
+/**
+ * @brief   DMA stream used for ADC3 operations.
+ */
+#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
+#endif
+
+/**
+ * @brief   ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   ADC2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC2_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   ADC3 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC3_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   ADC interrupt priority level setting.
+ * @note    This setting is shared among ADC1, ADC2 and ADC3 because
+ *          all ADCs share the same vector.
+ */
+#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_IRQ_PRIORITY              5
+#endif
+
+/**
+ * @brief   ADC1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
+#endif
+
+/**
+ * @brief   ADC2 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5
+#endif
+
+/**
+ * @brief   ADC3 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2
+#error "ADC2 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
+#error "ADC3 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
+#error "invalid DMA stream associated to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC2 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK)
+#error "invalid DMA stream associated to ADC2"
+#endif
+
+#if STM32_ADC_USE_ADC3 &&                                                   \
+    !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK)
+#error "invalid DMA stream associated to ADC3"
+#endif
+
+/* ADC clock related settings and checks.*/
+#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2
+#define STM32_ADCCLK                        (STM32_PCLK2 / 2)
+#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4
+#define STM32_ADCCLK                        (STM32_PCLK2 / 4)
+#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6
+#define STM32_ADCCLK                        (STM32_PCLK2 / 6)
+#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8
+#define STM32_ADCCLK                        (STM32_PCLK2 / 8)
+#else
+#error "invalid STM32_ADC_ADCPRE value specified"
+#endif
+
+#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX)
+#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief   Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief   Possible ADC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
+  ADC_ERR_OVERFLOW = 1                      /**< ADC overflow condition.    */
+} adcerror_t;
+
+/**
+ * @brief   Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief   ADC notification callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] buffer    pointer to the most recent samples data
+ * @param[in] n         number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief   ADC error callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] err       ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief   Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ *          operation.
+ * @note    The use of this configuration structure requires knowledge of
+ *          STM32 ADC cell registers interface, please refer to the STM32
+ *          reference manual for details.
+ */
+typedef struct {
+  /**
+   * @brief   Enables the circular buffer mode for the group.
+   */
+  bool                      circular;
+  /**
+   * @brief   Number of the analog channels belonging to the conversion group.
+   */
+  adc_channels_num_t        num_channels;
+  /**
+   * @brief   Callback function associated to the group or @p NULL.
+   */
+  adccallback_t             end_cb;
+  /**
+   * @brief   Error callback or @p NULL.
+   */
+  adcerrorcallback_t        error_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   ADC CR1 register initialization data.
+   * @note    All the required bits must be defined into this field except
+   *          @p ADC_CR1_SCAN that is enforced inside the driver.
+   */
+  uint32_t                  cr1;
+  /**
+   * @brief   ADC CR2 register initialization data.
+   * @note    All the required bits must be defined into this field except
+   *          @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
+   *          enforced inside the driver.
+   */
+  uint32_t                  cr2;
+  /**
+   * @brief   ADC SMPR1 register initialization data.
+   * @details In this field must be specified the sample times for channels
+   *          10...18.
+   */
+  uint32_t                  smpr1;
+  /**
+   * @brief   ADC SMPR2 register initialization data.
+   * @details In this field must be specified the sample times for channels
+   *          0...9.
+   */
+  uint32_t                  smpr2;
+  /**
+   * @brief   ADC SQR1 register initialization data.
+   * @details Conversion group sequence 13...16 + sequence length.
+   */
+  uint32_t                  sqr1;
+  /**
+   * @brief   ADC SQR2 register initialization data.
+   * @details Conversion group sequence 7...12.
+   */
+  uint32_t                  sqr2;
+  /**
+   * @brief   ADC SQR3 register initialization data.
+   * @details Conversion group sequence 1...6.
+   */
+  uint32_t                  sqr3;
+} ADCConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  uint32_t                  dummy;
+} ADCConfig;
+
+/**
+ * @brief   Structure representing an ADC driver.
+ */
+struct ADCDriver {
+  /**
+   * @brief Driver state.
+   */
+  adcstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const ADCConfig           *config;
+  /**
+   * @brief Current samples buffer pointer or @p NULL.
+   */
+  adcsample_t               *samples;
+  /**
+   * @brief Current samples buffer depth or @p 0.
+   */
+  size_t                    depth;
+  /**
+   * @brief Current conversion group pointer or @p NULL.
+   */
+  const ADCConversionGroup  *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+  ADC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the ADCx registers block.
+   */
+  ADC_TypeDef               *adc;
+  /**
+   * @brief Pointer to associated DMA channel.
+   */
+  const stm32_dma_stream_t  *dmastp;
+  /**
+   * @brief DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Sequences building helper macros
+ * @{
+ */
+/**
+ * @brief   Number of channels in a conversion sequence.
+ */
+#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
+
+#define ADC_SQR3_SQ1_N(n)       ((n) << 0)  /**< @brief 1st channel in seq. */
+#define ADC_SQR3_SQ2_N(n)       ((n) << 5)  /**< @brief 2nd channel in seq. */
+#define ADC_SQR3_SQ3_N(n)       ((n) << 10) /**< @brief 3rd channel in seq. */
+#define ADC_SQR3_SQ4_N(n)       ((n) << 15) /**< @brief 4th channel in seq. */
+#define ADC_SQR3_SQ5_N(n)       ((n) << 20) /**< @brief 5th channel in seq. */
+#define ADC_SQR3_SQ6_N(n)       ((n) << 25) /**< @brief 6th channel in seq. */
+
+#define ADC_SQR2_SQ7_N(n)       ((n) << 0)  /**< @brief 7th channel in seq. */
+#define ADC_SQR2_SQ8_N(n)       ((n) << 5)  /**< @brief 8th channel in seq. */
+#define ADC_SQR2_SQ9_N(n)       ((n) << 10) /**< @brief 9th channel in seq. */
+#define ADC_SQR2_SQ10_N(n)      ((n) << 15) /**< @brief 10th channel in seq.*/
+#define ADC_SQR2_SQ11_N(n)      ((n) << 20) /**< @brief 11th channel in seq.*/
+#define ADC_SQR2_SQ12_N(n)      ((n) << 25) /**< @brief 12th channel in seq.*/
+
+#define ADC_SQR1_SQ13_N(n)      ((n) << 0)  /**< @brief 13th channel in seq.*/
+#define ADC_SQR1_SQ14_N(n)      ((n) << 5)  /**< @brief 14th channel in seq.*/
+#define ADC_SQR1_SQ15_N(n)      ((n) << 10) /**< @brief 15th channel in seq.*/
+#define ADC_SQR1_SQ16_N(n)      ((n) << 15) /**< @brief 16th channel in seq.*/
+/** @} */
+
+/**
+ * @name    Sampling rate settings helper macros
+ * @{
+ */
+#define ADC_SMPR2_SMP_AN0(n)    ((n) << 0)  /**< @brief AN0 sampling time.  */
+#define ADC_SMPR2_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
+#define ADC_SMPR2_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
+#define ADC_SMPR2_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
+#define ADC_SMPR2_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
+#define ADC_SMPR2_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
+#define ADC_SMPR2_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
+#define ADC_SMPR2_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
+#define ADC_SMPR2_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
+#define ADC_SMPR2_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
+
+#define ADC_SMPR1_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
+#define ADC_SMPR1_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
+#define ADC_SMPR1_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
+#define ADC_SMPR1_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
+#define ADC_SMPR1_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
+#define ADC_SMPR1_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
+#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
+                                                 sampling time.             */
+#define ADC_SMPR1_SMP_VREF(n)   ((n) << 21) /**< @brief Voltage Reference
+                                                 sampling time.             */
+#define ADC_SMPR1_SMP_VBAT(n)   ((n) << 24) /**< @brief VBAT sampling time. */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD2;
+#endif
+
+#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adc_lld_init(void);
+  void adc_lld_start(ADCDriver *adcp);
+  void adc_lld_stop(ADCDriver *adcp);
+  void adc_lld_start_conversion(ADCDriver *adcp);
+  void adc_lld_stop_conversion(ADCDriver *adcp);
+  void adcSTM32EnableTSVREFE(void);
+  void adcSTM32DisableTSVREFE(void);
+  void adcSTM32EnableVBATE(void);
+  void adcSTM32DisableVBATE(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c
new file mode 100644
index 000000000..94bb0c57c
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c
@@ -0,0 +1,344 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F4xx/ext_lld_isr.c
+ * @brief   STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 0);
+  EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 1);
+  EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 2);
+  EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 3);
+  EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 4);
+  EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
+  EXTI->PR = pr;
+  if (pr & (1 << 5))
+    EXTD1.config->channels[5].cb(&EXTD1, 5);
+  if (pr & (1 << 6))
+    EXTD1.config->channels[6].cb(&EXTD1, 6);
+  if (pr & (1 << 7))
+    EXTD1.config->channels[7].cb(&EXTD1, 7);
+  if (pr & (1 << 8))
+    EXTD1.config->channels[8].cb(&EXTD1, 8);
+  if (pr & (1 << 9))
+    EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
+                   (1 << 15));
+  EXTI->PR = pr;
+  if (pr & (1 << 10))
+    EXTD1.config->channels[10].cb(&EXTD1, 10);
+  if (pr & (1 << 11))
+    EXTD1.config->channels[11].cb(&EXTD1, 11);
+  if (pr & (1 << 12))
+    EXTD1.config->channels[12].cb(&EXTD1, 12);
+  if (pr & (1 << 13))
+    EXTD1.config->channels[13].cb(&EXTD1, 13);
+  if (pr & (1 << 14))
+    EXTD1.config->channels[14].cb(&EXTD1, 14);
+  if (pr & (1 << 15))
+    EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 16);
+  EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[17] interrupt handler (RTC_ALARM).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 17);
+  EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[18] interrupt handler (OTG_FS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE8) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 18);
+  EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[19] interrupt handler (ETH_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector138) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 19);
+  EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(STM32F401xx)
+/**
+ * @brief   EXTI[20] interrupt handler (OTG_HS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector170) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 20);
+  EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[21] interrupt handler (TAMPER_STAMP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 21);
+  EXTD1.config->channels[21].cb(&EXTD1, 21);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* !defined(STM32F401xx) */
+
+/**
+ * @brief   EXTI[22] interrupt handler (RTC_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 22);
+  EXTD1.config->channels[22].cb(&EXTD1, 22);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+  nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+  nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+  nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+  nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+  nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+  nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+  nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+  nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+  nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+  nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+  nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+#if !defined(STM32F401xx)
+  nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+  nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY);
+#endif /* !defined(STM32F401xx) */
+  nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY);
+}
+
+/**
+ * @brief   Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+  nvicDisableVector(EXTI0_IRQn);
+  nvicDisableVector(EXTI1_IRQn);
+  nvicDisableVector(EXTI2_IRQn);
+  nvicDisableVector(EXTI3_IRQn);
+  nvicDisableVector(EXTI4_IRQn);
+  nvicDisableVector(EXTI9_5_IRQn);
+  nvicDisableVector(EXTI15_10_IRQn);
+  nvicDisableVector(PVD_IRQn);
+  nvicDisableVector(RTC_Alarm_IRQn);
+  nvicDisableVector(OTG_FS_WKUP_IRQn);
+  nvicDisableVector(ETH_WKUP_IRQn);
+#if !defined(STM32F401xx)
+  nvicDisableVector(OTG_HS_WKUP_IRQn);
+  nvicDisableVector(TAMP_STAMP_IRQn);
+#endif /* !defined(STM32F401xx) */
+  nvicDisableVector(RTC_WKUP_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F4xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h
index 33e8e0be1..33e8e0be1 100644
--- a/os/hal/platforms/STM32F4xx/ext_lld_isr.h
+++ b/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
new file mode 100644
index 000000000..7aeb67297
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -0,0 +1,252 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F4xx/hal_lld.c
+ * @brief   STM32F4xx/STM32F2xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the backup domain.
+ * @note    WARNING! Changing clock source impossible without resetting
+ *          of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+  /* Backup domain access enabled and left open.*/
+  PWR->CR |= PWR_CR_DBP;
+
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0;
+  }
+
+#if STM32_LSE_ENABLED
+#if defined(STM32_LSE_BYPASS)
+  /* LSE Bypass.*/
+  RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+  /* No LSE Bypass.*/
+  RCC->BDCR |= RCC_BDCR_LSEON;
+#endif
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                       /* Waits until LSE is stable.   */
+#endif
+
+#if HAL_USE_RTC
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+    /* Selects clock source.*/
+    RCC->BDCR |= STM32_RTCSEL;
+
+    /* RTC clock enabled.*/
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+#endif /* HAL_USE_RTC */
+
+#if STM32_BKPRAM_ENABLE
+  rccEnableBKPSRAM(false);
+
+  PWR->CSR |= PWR_CSR_BRE;
+  while ((PWR->CSR & PWR_CSR_BRR) == 0)
+    ;                                /* Waits until the regulator is stable */
+#else
+  PWR->CSR &= ~PWR_CSR_BRE;
+#endif /* STM32_BKPRAM_ENABLE */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+  /* Reset of all peripherals. AHB3 is not reseted because it could have
+     been initialized in the board initialization file (board.c).*/
+  rccResetAHB1(~0);
+  rccResetAHB2(~0);
+  rccResetAPB1(~RCC_APB1RSTR_PWRRST);
+  rccResetAPB2(~0);
+
+  /* PWR clock enabled.*/
+  rccEnablePWRInterface(FALSE);
+
+  /* Initializes the backup domain.*/
+  hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+  dmaInit();
+#endif
+
+  /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief   STM32F2xx clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* PWR clock enable.*/
+  RCC->APB1ENR = RCC_APB1ENR_PWREN;
+
+  /* PWR initialization.*/
+#if defined(STM32F4XX) || defined(__DOXYGEN__)
+  PWR->CR = STM32_VOS;
+#else
+  PWR->CR = 0;
+#endif
+
+  /* HSI setup, it enforces the reset situation in order to handle possible
+     problems with JTAG probes and re-initializations.*/
+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;                                       /* Wait until HSI is stable.    */
+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
+  RCC->CFGR = 0;                            /* CFGR reset value.            */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;                                       /* Waits until HSI is selected. */
+
+#if STM32_HSE_ENABLED
+  /* HSE activation.*/
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+  /* No HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON;
+#endif
+  while ((RCC->CR & RCC_CR_HSERDY) == 0)
+    ;                           /* Waits until HSE is stable.               */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                           /* Waits until LSI is stable.               */
+#endif
+
+#if STM32_ACTIVATE_PLL
+  /* PLL activation.*/
+  RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
+                 STM32_PLLM;
+  RCC->CR |= RCC_CR_PLLON;
+
+  /* Synchronization with voltage regulator stabilization.*/
+#if defined(STM32F4XX)
+  while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
+    ;                           /* Waits until power regulator is stable.   */
+
+#if STM32_OVERDRIVE_REQUIRED
+  /* Overdrive activation performed after activating the PLL in order to save
+     time as recommended in RM in "Entering Over-drive mode" paragraph.*/
+  PWR->CR |= PWR_CR_ODEN;
+  while (!(PWR->CSR & PWR_CSR_ODRDY))
+      ;
+  PWR->CR |= PWR_CR_ODSWEN;
+  while (!(PWR->CSR & PWR_CSR_ODSWRDY))
+      ;
+#endif /* STM32_OVERDRIVE_REQUIRED */
+#endif /* defined(STM32F4XX) */
+
+  /* Waiting for PLL lock.*/
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;
+#endif /* STM32_OVERDRIVE_REQUIRED */
+
+#if STM32_ACTIVATE_PLLI2S
+  /* PLLI2S activation.*/
+  RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
+  RCC->CR |= RCC_CR_PLLI2SON;
+
+  /* Waiting for PLL lock.*/
+  while (!(RCC->CR & RCC_CR_PLLI2SRDY))
+    ;
+#endif
+
+  /* Other clock-related settings (dividers, MCO etc).*/
+  RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
+              STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+
+  /* Flash setup.*/
+#if defined(STM32_USE_REVISION_A_FIX)
+  /* Some old revisions of F4x MCUs randomly crashes with compiler
+     optimizations enabled AND flash caches enabled. */
+  if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
+    FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
+  else
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
+                 FLASH_ACR_DCEN | STM32_FLASHBITS;
+#else
+  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
+               FLASH_ACR_DCEN | STM32_FLASHBITS;
+#endif
+
+  /* Switching to the configured clock source if it is different from MSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;
+#endif
+#endif /* STM32_NO_INIT */
+
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+}
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
new file mode 100644
index 000000000..c7f9ed864
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -0,0 +1,1393 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F4xx/hal_lld.h
+ * @brief   STM32F4xx/STM32F2xx HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - STM32_LSECLK.
+ *          - STM32_LSE_BYPASS (optionally).
+ *          - STM32_HSECLK.
+ *          - STM32_HSE_BYPASS (optionally).
+ *          - STM32_VDD (as hundredths of Volt).
+ *          .
+ *          One of the following macros must also be defined:
+ *          - STM32F2XX for High-performance STM32 F-2 devices.
+ *          - STM32F401xx for High-performance STM32 F-4 devices.
+ *          - STM32F40_41xxx for High-performance STM32 F-4 devices.
+ *          - STM32F427_437xx for High-performance STM32 F-4 devices.
+ *          - STM32F429_439xx for High-performance STM32 F-4 devices.
+ *          .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS TRUE
+
+/**
+ * @name    Platform identification macros
+ * @{
+ */
+#if defined(STM32F429_439xx) || defined(__DOXYGEN__)
+#define PLATFORM_NAME           "STM32F429/F439 High Performance with DSP and FPU"
+#define STM32F4XX
+
+#elif defined(STM32F427_437xx)
+#define PLATFORM_NAME           "STM32F427/F437 High Performance with DSP and FPU"
+#define STM32F4XX
+
+#elif defined(STM32F40_41xxx)
+#define PLATFORM_NAME           "STM32F407/F417 High Performance with DSP and FPU"
+#define STM32F4XX
+
+#elif defined(STM32F401xx)
+#define PLATFORM_NAME           "STM32F401 High Performance with DSP and FPU"
+#define STM32F4XX
+
+#elif defined(STM32F2XX)
+#define PLATFORM_NAME           "STM32F2xx High Performance"
+
+#else
+#error "STM32F2xx/F4xx device not specified"
+#endif
+/** @} */
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) ||                 \
+    defined(__DOXYGEN__)
+/**
+ * @brief   Absolute maximum system clock.
+ */
+#define STM32_SYSCLK_MAX        180000000
+
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        26000000
+
+/**
+ * @brief   Maximum HSE clock frequency using an external source.
+ */
+#define STM32_HSECLK_BYP_MAX    50000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        4000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_BYP_MIN    1000000
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        32768
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_BYP_MAX    1000000
+
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX         2100000
+
+/**
+ * @brief   Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN         950000
+
+/**
+ * @brief   Maximum PLLs VCO clock frequency.
+ */
+#define STM32_PLLVCO_MAX        432000000
+
+/**
+ * @brief   Maximum PLLs VCO clock frequency.
+ */
+#define STM32_PLLVCO_MIN        192000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX        180000000
+
+/**
+ * @brief   Minimum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN        24000000
+
+/**
+ * @brief   Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX         (STM32_PLLOUT_MAX /4)
+
+/**
+ * @brief   Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX         (STM32_PLLOUT_MAX / 2)
+
+/**
+ * @brief   Maximum SPI/I2S clock frequency.
+ */
+#define STM32_SPII2S_MAX        45000000
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F40_41xxx) || defined(__DOXYGEN__)
+#define STM32_SYSCLK_MAX        168000000
+#define STM32_HSECLK_MAX        26000000
+#define STM32_HSECLK_BYP_MAX    50000000
+#define STM32_HSECLK_MIN        4000000
+#define STM32_HSECLK_BYP_MIN    1000000
+#define STM32_LSECLK_MAX        32768
+#define STM32_LSECLK_BYP_MAX    1000000
+#define STM32_LSECLK_MIN        32768
+#define STM32_PLLIN_MAX         2100000
+#define STM32_PLLIN_MIN         950000
+#define STM32_PLLVCO_MAX        432000000
+#define STM32_PLLVCO_MIN        192000000
+#define STM32_PLLOUT_MAX        168000000
+#define STM32_PLLOUT_MIN        24000000
+#define STM32_PCLK1_MAX         42000000
+#define STM32_PCLK2_MAX         84000000
+#define STM32_SPII2S_MAX        42000000
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F401xx) || defined(__DOXYGEN__)
+#define STM32_SYSCLK_MAX        84000000
+#define STM32_HSECLK_MAX        26000000
+#define STM32_HSECLK_BYP_MAX    50000000
+#define STM32_HSECLK_MIN        4000000
+#define STM32_HSECLK_BYP_MIN    1000000
+#define STM32_LSECLK_MAX        32768
+#define STM32_LSECLK_BYP_MAX    1000000
+#define STM32_LSECLK_MIN        32768
+#define STM32_PLLIN_MAX         2100000
+#define STM32_PLLIN_MIN         950000
+#define STM32_PLLVCO_MAX        432000000
+#define STM32_PLLVCO_MIN        192000000
+#define STM32_PLLOUT_MAX        84000000
+#define STM32_PLLOUT_MIN        24000000
+#define STM32_PCLK1_MAX         42000000
+#define STM32_PCLK2_MAX         84000000
+#define STM32_SPII2S_MAX        42000000
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F2XX)
+#define STM32_SYSCLK_MAX        120000000
+#define STM32_HSECLK_MAX        26000000
+#define STM32_HSECLK_BYP_MAX    26000000
+#define STM32_HSECLK_MIN        1000000
+#define STM32_HSECLK_BYP_MIN    1000000
+#define STM32_LSECLK_MAX        32768
+#define STM32_LSECLK_BYP_MAX    1000000
+#define STM32_LSECLK_MIN        32768
+#define STM32_PLLIN_MAX         2000000
+#define STM32_PLLIN_MIN         950000
+#define STM32_PLLVCO_MAX        432000000
+#define STM32_PLLVCO_MIN        192000000
+#define STM32_PLLOUT_MAX        120000000
+#define STM32_PLLOUT_MIN        24000000
+#define STM32_PCLK1_MAX         30000000
+#define STM32_PCLK2_MAX         60000000
+#define STM32_SPII2S_MAX        30000000
+#endif /* defined(STM32F2XX) */
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK            16000000    /**< High speed internal clock. */
+#define STM32_LSICLK            32000       /**< Low speed internal clock.  */
+/** @} */
+
+/**
+ * @name    PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_VOS_SCALE3        (PWR_CR_VOS_0)
+#define STM32_VOS_SCALE2        (PWR_CR_VOS_1)
+#define STM32_VOS_SCALE1        (PWR_CR_VOS_1 | PWR_CR_VOS_0)
+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
+/** @} */
+
+/**
+ * @name    RCC_PLLCFGR register bits definitions
+ * @{
+ */
+#define STM32_PLLP_MASK			(3 << 16)	/**< PLLP mask.                 */
+#define STM32_PLLP_DIV2			(0 << 16)	/**< PLL clock divided by 2.    */
+#define STM32_PLLP_DIV4			(1 << 16)	/**< PLL clock divided by 4.    */
+#define STM32_PLLP_DIV6			(2 << 16)   /**< PLL clock divided by 6.    */
+#define STM32_PLLP_DIV8			(3 << 16)   /**< PLL clock divided by 8.    */
+
+#define STM32_PLLSRC_HSI        (0 << 22)   /**< PLL clock source is HSI.   */
+#define STM32_PLLSRC_HSE        (1 << 22)   /**< PLL clock source is HSE.   */
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_MASK           (3 << 0)    /**< SW mask.                   */
+#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_MASK         (15 << 4)   /**< HPRE mask.                 */
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE1_MASK        (7 << 10)	/**< PPRE1 mask.                */
+#define STM32_PPRE1_DIV1        (0 << 10)   /**< HCLK divided by 1.         */
+#define STM32_PPRE1_DIV2        (4 << 10)   /**< HCLK divided by 2.         */
+#define STM32_PPRE1_DIV4        (5 << 10)   /**< HCLK divided by 4.         */
+#define STM32_PPRE1_DIV8        (6 << 10)   /**< HCLK divided by 8.         */
+#define STM32_PPRE1_DIV16       (7 << 10)   /**< HCLK divided by 16.        */
+
+#define STM32_PPRE2_MASK        (7 << 13)	/**< PPRE2 mask.                */
+#define STM32_PPRE2_DIV1        (0 << 13)   /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4 << 13)   /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5 << 13)   /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6 << 13)   /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7 << 13)   /**< HCLK divided by 16.        */
+
+#define STM32_RTCPRE_MASK       (31 << 16)  /**< RTCPRE mask.               */
+
+#define STM32_MCO1SEL_MASK      (3 << 21)   /**< MCO1 mask.                 */
+#define STM32_MCO1SEL_HSI       (0 << 21)   /**< HSI clock on MCO1 pin.     */
+#define STM32_MCO1SEL_LSE       (1 << 21)   /**< LSE clock on MCO1 pin.     */
+#define STM32_MCO1SEL_HSE       (2 << 21)   /**< HSE clock on MCO1 pin.     */
+#define STM32_MCO1SEL_PLL       (3 << 21)   /**< PLL clock on MCO1 pin.     */
+
+#define STM32_I2SSRC_MASK       (1 << 23)   /**< I2CSRC mask.               */
+#define STM32_I2SSRC_PLLI2S     (0 << 23)   /**< I2SSRC is PLLI2S.          */
+#define STM32_I2SSRC_CKIN       (1 << 23)   /**< I2S_CKIN is PLLI2S.        */
+
+#define STM32_MCO1PRE_MASK      (7 << 24)   /**< MCO1PRE mask.              */
+#define STM32_MCO1PRE_DIV1      (0 << 24)   /**< MCO1 divided by 1.         */
+#define STM32_MCO1PRE_DIV2      (4 << 24)   /**< MCO1 divided by 2.         */
+#define STM32_MCO1PRE_DIV3      (5 << 24)   /**< MCO1 divided by 3.         */
+#define STM32_MCO1PRE_DIV4      (6 << 24)   /**< MCO1 divided by 4.         */
+#define STM32_MCO1PRE_DIV5      (7 << 24)   /**< MCO1 divided by 5.         */
+
+#define STM32_MCO2PRE_MASK      (7 << 27)   /**< MCO2PRE mask.              */
+#define STM32_MCO2PRE_DIV1      (0 << 27)   /**< MCO2 divided by 1.         */
+#define STM32_MCO2PRE_DIV2      (4 << 27)   /**< MCO2 divided by 2.         */
+#define STM32_MCO2PRE_DIV3      (5 << 27)   /**< MCO2 divided by 3.         */
+#define STM32_MCO2PRE_DIV4      (6 << 27)   /**< MCO2 divided by 4.         */
+#define STM32_MCO2PRE_DIV5      (7 << 27)   /**< MCO2 divided by 5.         */
+
+#define STM32_MCO2SEL_MASK      (3U << 30)  /**< MCO2 mask.                 */
+#define STM32_MCO2SEL_SYSCLK    (0U << 30)  /**< SYSCLK clock on MCO2 pin.  */
+#define STM32_MCO2SEL_PLLI2S    (1U << 30)  /**< PLLI2S clock on MCO2 pin.  */
+#define STM32_MCO2SEL_HSE       (2U << 30)  /**< HSE clock on MCO2 pin.     */
+#define STM32_MCO2SEL_PLL       (3U << 30)  /**< PLL clock on MCO2 pin.     */
+
+#define STM32_RTC_NOCLOCK       (0 << 8)    /**< No clock.                  */
+#define STM32_RTC_LSE           (1 << 8)    /**< LSE used as RTC clock.     */
+#define STM32_RTC_LSI           (2 << 8)    /**< LSI used as RTC clock.     */
+#define STM32_RTC_HSE           (3 << 8)    /**< HSE divided by programmable
+                                                 prescaler used as RTC clock*/
+
+/**
+ * @name    RCC_PLLI2SCFGR register bits definitions
+ * @{
+ */
+#define STM32_PLLI2SN_MASK      (511 << 6)  /**< PLLI2SN mask.              */
+#define STM32_PLLI2SR_MASK      (7 << 28)   /**< PLLI2SR mask.              */
+/** @} */
+
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC source mask.           */
+#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No RTC source.             */
+#define STM32_RTCSEL_LSE        (1 << 8)    /**< RTC source is LSE.         */
+#define STM32_RTCSEL_LSI        (2 << 8)    /**< RTC source is LSI.         */
+#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< RTC source is HSE divided. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT               FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE            FALSE
+#endif
+
+/**
+ * @brief   Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                   STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief   Enables the backup RAM regulator.
+ */
+#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__)
+#define STM32_BKPRAM_ENABLE         FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED           FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED           FALSE
+#endif
+
+/**
+ * @brief   USB/SDIO clock setting.
+ */
+#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_CLOCK48_REQUIRED      TRUE
+#endif
+
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 168MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                    STM32_SW_PLL
+#endif
+
+#if defined(STM32F4XX) || defined(__DOXYGEN__)
+/**
+ * @brief   Clock source for the PLLs.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 168MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief   PLLM divider value.
+ * @note    The allowed values are 2..63.
+ * @note    The default value is calculated for a 168MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLM_VALUE            8
+#endif
+
+/**
+ * @brief   PLLN multiplier value.
+ * @note    The allowed values are 192..432.
+ * @note    The default value is calculated for a 168MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLN_VALUE            336
+#endif
+
+/**
+ * @brief   PLLP divider value.
+ * @note    The allowed values are 2, 4, 6, 8.
+ * @note    The default value is calculated for a 168MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLP_VALUE            2
+#endif
+
+/**
+ * @brief   PLLQ multiplier value.
+ * @note    The allowed values are 2..15.
+ * @note    The default value is calculated for a 168MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLQ_VALUE            7
+#endif
+
+#else /* !defined(STM32F4XX) */
+/**
+ * @brief   Clock source for the PLLs.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 120MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief   PLLM divider value.
+ * @note    The allowed values are 2..63.
+ * @note    The default value is calculated for a 120MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLM_VALUE            8
+#endif
+
+/**
+ * @brief   PLLN multiplier value.
+ * @note    The allowed values are 192..432.
+ * @note    The default value is calculated for a 120MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLN_VALUE            240
+#endif
+
+/**
+ * @brief   PLLP divider value.
+ * @note    The allowed values are 2, 4, 6, 8.
+ * @note    The default value is calculated for a 120MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLP_VALUE            2
+#endif
+
+/**
+ * @brief   PLLQ multiplier value.
+ * @note    The allowed values are 2..15.
+ * @note    The default value is calculated for a 120MHz system clock from
+ *          an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLQ_VALUE            5
+#endif
+#endif /* !defined(STM32F4XX) */
+
+/**
+ * @brief   AHB prescaler value.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                  STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1                 STM32_PPRE1_DIV4
+#endif
+
+/**
+ * @brief   APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2                 STM32_PPRE2_DIV2
+#endif
+
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                STM32_RTCSEL_LSE
+#endif
+
+/**
+ * @brief   RTC HSE prescaler value.
+ */
+#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
+#define STM32_RTCPRE_VALUE          8
+#endif
+
+/**
+ * @brief   MC01 clock source value.
+ * @note    The default value outputs HSI clock on MC01 pin.
+ */
+#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
+#define STM32_MCO1SEL               STM32_MCO1SEL_HSI
+#endif
+
+/**
+ * @brief   MC01 prescaler value.
+ * @note    The default value outputs HSI clock on MC01 pin.
+ */
+#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
+#define STM32_MCO1PRE               STM32_MCO1PRE_DIV1
+#endif
+
+/**
+ * @brief   MC02 clock source value.
+ * @note    The default value outputs SYSCLK / 5 on MC02 pin.
+ */
+#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
+#define STM32_MCO2SEL               STM32_MCO2SEL_SYSCLK
+#endif
+
+/**
+ * @brief   MC02 prescaler value.
+ * @note    The default value outputs SYSCLK / 5 on MC02 pin.
+ */
+#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
+#define STM32_MCO2PRE               STM32_MCO2PRE_DIV5
+#endif
+
+/**
+ * @brief   I2S clock source.
+ */
+#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
+#define STM32_I2SSRC                STM32_I2SSRC_CKIN
+#endif
+
+/**
+ * @brief   PLLI2SN multiplier value.
+ * @note    The allowed values are 192..432.
+ */
+#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SN_VALUE         192
+#endif
+
+/**
+ * @brief   PLLI2SR multiplier value.
+ * @note    The allowed values are 2..7.
+ */
+#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SR_VALUE         5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if defined(STM32F4XX) || defined(__DOXYGEN__)
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F4xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"
+#endif
+
+#else /* !defined(STM32F4XX) */
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F2xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined"
+#endif
+#endif /* !defined(STM32F4XX) */
+
+/**
+ * @brief   Maximum frequency thresholds and wait states for flash access.
+ * @note    The values are valid for 2.7V to 3.6V supply range.
+ */
+#if defined(STM32F429_439xx) || defined(STM32F427_437xx) ||                 \
+    defined(STM32F40_41xxx) || defined(__DOXYGEN__)
+#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
+#define STM32_0WS_THRESHOLD         30000000
+#define STM32_1WS_THRESHOLD         60000000
+#define STM32_2WS_THRESHOLD         90000000
+#define STM32_3WS_THRESHOLD         120000000
+#define STM32_4WS_THRESHOLD         150000000
+#define STM32_5WS_THRESHOLD         180000000
+#define STM32_6WS_THRESHOLD         0
+#define STM32_7WS_THRESHOLD         0
+#define STM32_8WS_THRESHOLD         0
+#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
+#define STM32_0WS_THRESHOLD         24000000
+#define STM32_1WS_THRESHOLD         48000000
+#define STM32_2WS_THRESHOLD         72000000
+#define STM32_3WS_THRESHOLD         96000000
+#define STM32_4WS_THRESHOLD         120000000
+#define STM32_5WS_THRESHOLD         144000000
+#define STM32_6WS_THRESHOLD         168000000
+#define STM32_7WS_THRESHOLD         180000000
+#define STM32_8WS_THRESHOLD         0
+#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
+#define STM32_0WS_THRESHOLD         22000000
+#define STM32_1WS_THRESHOLD         44000000
+#define STM32_2WS_THRESHOLD         66000000
+#define STM32_3WS_THRESHOLD         88000000
+#define STM32_4WS_THRESHOLD         110000000
+#define STM32_5WS_THRESHOLD         132000000
+#define STM32_6WS_THRESHOLD         154000000
+#define STM32_7WS_THRESHOLD         176000000
+#define STM32_8WS_THRESHOLD         180000000
+#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
+#define STM32_0WS_THRESHOLD         20000000
+#define STM32_1WS_THRESHOLD         40000000
+#define STM32_2WS_THRESHOLD         60000000
+#define STM32_3WS_THRESHOLD         80000000
+#define STM32_4WS_THRESHOLD         100000000
+#define STM32_5WS_THRESHOLD         120000000
+#define STM32_6WS_THRESHOLD         140000000
+#define STM32_7WS_THRESHOLD         168000000
+#define STM32_8WS_THRESHOLD         0
+#else
+#error "invalid VDD voltage specified"
+#endif
+
+#elif defined(STM32F401xx)
+#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
+#define STM32_0WS_THRESHOLD         30000000
+#define STM32_1WS_THRESHOLD         60000000
+#define STM32_2WS_THRESHOLD         84000000
+#define STM32_3WS_THRESHOLD         0
+#define STM32_4WS_THRESHOLD         0
+#define STM32_5WS_THRESHOLD         0
+#define STM32_6WS_THRESHOLD         0
+#define STM32_7WS_THRESHOLD         0
+#define STM32_8WS_THRESHOLD         0
+#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
+#define STM32_0WS_THRESHOLD         24000000
+#define STM32_1WS_THRESHOLD         48000000
+#define STM32_2WS_THRESHOLD         72000000
+#define STM32_3WS_THRESHOLD         84000000
+#define STM32_4WS_THRESHOLD         0
+#define STM32_5WS_THRESHOLD         0
+#define STM32_6WS_THRESHOLD         0
+#define STM32_7WS_THRESHOLD         0
+#define STM32_8WS_THRESHOLD         0
+#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
+#define STM32_0WS_THRESHOLD         18000000
+#define STM32_1WS_THRESHOLD         36000000
+#define STM32_2WS_THRESHOLD         54000000
+#define STM32_3WS_THRESHOLD         72000000
+#define STM32_4WS_THRESHOLD         840000000
+#define STM32_5WS_THRESHOLD         0
+#define STM32_6WS_THRESHOLD         0
+#define STM32_7WS_THRESHOLD         0
+#define STM32_8WS_THRESHOLD         0
+#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
+#define STM32_0WS_THRESHOLD         16000000
+#define STM32_1WS_THRESHOLD         32000000
+#define STM32_2WS_THRESHOLD         48000000
+#define STM32_3WS_THRESHOLD         64000000
+#define STM32_4WS_THRESHOLD         800000000
+#define STM32_5WS_THRESHOLD         840000000
+#define STM32_6WS_THRESHOLD         0
+#define STM32_7WS_THRESHOLD         0
+#define STM32_8WS_THRESHOLD         0
+#else
+#error "invalid VDD voltage specified"
+#endif
+
+#else /* STM32F2XX */
+#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
+#define STM32_0WS_THRESHOLD         30000000
+#define STM32_1WS_THRESHOLD         60000000
+#define STM32_2WS_THRESHOLD         90000000
+#define STM32_3WS_THRESHOLD         120000000
+#define STM32_4WS_THRESHOLD         0
+#define STM32_5WS_THRESHOLD         0
+#define STM32_6WS_THRESHOLD         0
+#define STM32_7WS_THRESHOLD         0
+#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
+#define STM32_0WS_THRESHOLD         24000000
+#define STM32_1WS_THRESHOLD         48000000
+#define STM32_2WS_THRESHOLD         72000000
+#define STM32_3WS_THRESHOLD         96000000
+#define STM32_4WS_THRESHOLD         120000000
+#define STM32_5WS_THRESHOLD         0
+#define STM32_6WS_THRESHOLD         0
+#define STM32_7WS_THRESHOLD         0
+#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
+#define STM32_0WS_THRESHOLD         18000000
+#define STM32_1WS_THRESHOLD         36000000
+#define STM32_2WS_THRESHOLD         54000000
+#define STM32_3WS_THRESHOLD         72000000
+#define STM32_4WS_THRESHOLD         90000000
+#define STM32_5WS_THRESHOLD         108000000
+#define STM32_6WS_THRESHOLD         120000000
+#define STM32_7WS_THRESHOLD         0
+#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
+#define STM32_0WS_THRESHOLD         16000000
+#define STM32_1WS_THRESHOLD         32000000
+#define STM32_2WS_THRESHOLD         48000000
+#define STM32_3WS_THRESHOLD         64000000
+#define STM32_4WS_THRESHOLD         80000000
+#define STM32_5WS_THRESHOLD         96000000
+#define STM32_6WS_THRESHOLD         112000000
+#define STM32_7WS_THRESHOLD         120000000
+#else
+#error "invalid VDD voltage specified"
+#endif
+#endif /* STM32F2XX */
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) ||                                 \
+    ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) &&                                \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCO1SEL"
+#endif
+
+#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_MCO2SEL"
+#endif
+
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) &&                                \
+    (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_I2SSRC"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) ||                                 \
+    ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) &&                                \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCO1SEL"
+#endif
+
+#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) ||                                 \
+    ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) &&                                \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCO2SEL"
+#endif
+
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) &&                                \
+    (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_I2SSRC"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/**
+ * @brief   STM32_PLLM field.
+ */
+#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) ||                \
+    defined(__DOXYGEN__)
+#define STM32_PLLM                  (STM32_PLLM_VALUE << 0)
+#else
+#error "invalid STM32_PLLM_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLLs input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / STM32_PLLM_VALUE)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/*
+ * PLLs input frequency range check.
+ */
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/*
+ * PLL enable check.
+ */
+#if STM32_CLOCK48_REQUIRED ||                                               \
+    (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCO1SEL == STM32_MCO1SEL_PLL) ||                                 \
+    (STM32_MCO2SEL == STM32_MCO2SEL_PLL) ||                                 \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+
+/**
+ * @brief   STM32_PLLN field.
+ */
+#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) ||              \
+    defined(__DOXYGEN__)
+#define STM32_PLLN                  (STM32_PLLN_VALUE << 6)
+#else
+#error "invalid STM32_PLLN_VALUE value specified"
+#endif
+
+/**
+ * @brief   STM32_PLLP field.
+ */
+#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLP                  (0 << 16)
+#elif STM32_PLLP_VALUE == 4
+#define STM32_PLLP                  (1 << 16)
+#elif STM32_PLLP_VALUE == 6
+#define STM32_PLLP                  (2 << 16)
+#elif STM32_PLLP_VALUE == 8
+#define STM32_PLLP                  (3 << 16)
+#else
+#error "invalid STM32_PLLP_VALUE value specified"
+#endif
+
+/**
+ * @brief   STM32_PLLQ field.
+ */
+#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) ||                \
+    defined(__DOXYGEN__)
+#define STM32_PLLQ                  (STM32_PLLQ_VALUE << 24)
+#else
+#error "invalid STM32_PLLQ_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL VCO frequency.
+ */
+#define STM32_PLLVCO                (STM32_PLLCLKIN * STM32_PLLN_VALUE)
+
+/*
+ * PLL VCO frequency range check.
+ */
+#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLVCO / STM32_PLLP_VALUE)
+
+/*
+ * PLL output frequency range check.
+ */
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#elif (STM32_SW == STM32_SW_PLL)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/* Calculating VOS settings, it is different for each sub-platform.*/
+#if defined(STM32F429_439xx) || defined(STM32F427_437xx) ||                 \
+    defined(__DOXYGEN__)
+#if STM32_SYSCLK <= 120000000
+#define STM32_VOS                   STM32_VOS_SCALE3
+#define STM32_OVERDRIVE_REQUIRED    FALSE
+#elif STM32_SYSCLK <= 144000000
+#define STM32_VOS                   STM32_VOS_SCALE2
+#define STM32_OVERDRIVE_REQUIRED    FALSE
+#elif STM32_SYSCLK <= 168000000
+#define STM32_VOS                   STM32_VOS_SCALE1
+#define STM32_OVERDRIVE_REQUIRED    FALSE
+#else
+#define STM32_VOS                   STM32_VOS_SCALE1
+#define STM32_OVERDRIVE_REQUIRED    TRUE
+#endif
+
+#elif defined(STM32F40_41xxx)
+#if STM32_SYSCLK <= 144000000
+#define STM32_VOS                   STM32_VOS_SCALE2
+#else
+#define STM32_VOS                   STM32_VOS_SCALE1
+#endif
+#define STM32_OVERDRIVE_REQUIRED    FALSE
+
+#elif defined(STM32F401xx)
+#if STM32_SYSCLK <= 60000000
+#define STM32_VOS                   STM32_VOS_SCALE3
+#else
+#define STM32_VOS                   STM32_VOS_SCALE2
+#endif
+#define STM32_OVERDRIVE_REQUIRED    FALSE
+
+#else /* STM32F2XX */
+#define STM32_OVERDRIVE_REQUIRED    FALSE
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/*
+ * AHB frequency check.
+ */
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/*
+ * APB1 frequency check.
+ */
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/*
+ * APB2 frequency check.
+ */
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/*
+ * PLLI2S enable check.
+ */
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLLI2S       TRUE
+#else
+#define STM32_ACTIVATE_PLLI2S       FALSE
+#endif
+
+/**
+ * @brief   STM32_PLLI2SN field.
+ */
+#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) ||       \
+    defined(__DOXYGEN__)
+#define STM32_PLLI2SN               (STM32_PLLI2SN_VALUE << 6)
+#else
+#error "invalid STM32_PLLI2SN_VALUE value specified"
+#endif
+
+/**
+ * @brief   STM32_PLLI2SR field.
+ */
+#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) ||           \
+    defined(__DOXYGEN__)
+#define STM32_PLLI2SR               (STM32_PLLI2SR_VALUE << 28)
+#else
+#error "invalid STM32_PLLI2SR_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL VCO frequency.
+ */
+#define STM32_PLLI2SVCO             (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE)
+
+/*
+ * PLLI2S VCO frequency range check.
+ */
+#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) ||                                 \
+    (STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief   PLLI2S output clock frequency.
+ */
+#define STM32_PLLI2SCLKOUT          (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
+
+/**
+ * @brief   MCO1 divider clock.
+ */
+#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
+#define STM32_MCO1DIVCLK             STM32_HSICLK
+#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
+#define STM32_MCO1DIVCLK             STM32_LSECLK
+#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
+#define STM32_MCO1DIVCLK             STM32_HSECLK
+#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
+#define STM32_MCO1DIVCLK             STM32_PLLCLKOUT
+#else
+#error "invalid STM32_MCO1SEL value specified"
+#endif
+
+/**
+ * @brief   MCO1 output pin clock.
+ */
+#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCO1CLK                STM32_MCO1DIVCLK
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
+#define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 2)
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
+#define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 3)
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
+#define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 4)
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
+#define STM32_MCO1CLK                (STM32_MCO1DIVCLK / 5)
+#else
+#error "invalid STM32_MCO1PRE value specified"
+#endif
+
+/**
+ * @brief   MCO2 divider clock.
+ */
+#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
+#define STM32_MCO2DIVCLK             STM32_HSECLK
+#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
+#define STM32_MCO2DIVCLK             STM32_PLLCLKOUT
+#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2DIVCLK             STM32_SYSCLK
+#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
+#define STM32_MCO2DIVCLK             STM32_PLLI2S
+#else
+#error "invalid STM32_MCO2SEL value specified"
+#endif
+
+/**
+ * @brief   MCO2 output pin clock.
+ */
+#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCO2CLK                STM32_MCO2DIVCLK
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
+#define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 2)
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
+#define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 3)
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
+#define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 4)
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
+#define STM32_MCO2CLK                (STM32_MCO2DIVCLK / 5)
+#else
+#error "invalid STM32_MCO2PRE value specified"
+#endif
+
+/**
+ * @brief   RTC HSE divider setting.
+ */
+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) ||            \
+    defined(__DOXYGEN__)
+#define STM32_RTCPRE                (STM32_RTCPRE_VALUE << 16)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief   HSE divider toward RTC clock.
+ */
+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31))  ||           \
+    defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK             (STM32_HSECLK / STM32_RTCPRE_VALUE)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                0
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                STM32_HSEDIVCLK
+#else
+#error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief   48MHz frequency.
+ */
+#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
+#define STM32_PLL48CLK              (STM32_PLLVCO / STM32_PLLQ_VALUE)
+#else
+#define STM32_PLL48CLK              0
+#endif
+
+/**
+ * @brief   Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief   Timers 1, 8 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000000
+#elif STM32_HCLK <= STM32_1WS_THRESHOLD
+#define STM32_FLASHBITS             0x00000001
+#elif STM32_HCLK <= STM32_2WS_THRESHOLD
+#define STM32_FLASHBITS             0x00000002
+#elif STM32_HCLK <= STM32_3WS_THRESHOLD
+#define STM32_FLASHBITS             0x00000003
+#elif STM32_HCLK <= STM32_4WS_THRESHOLD
+#define STM32_FLASHBITS             0x00000004
+#elif STM32_HCLK <= STM32_5WS_THRESHOLD
+#define STM32_FLASHBITS             0x00000005
+#elif STM32_HCLK <= STM32_6WS_THRESHOLD
+#define STM32_FLASHBITS             0x00000006
+#elif STM32_HCLK <= STM32_7WS_THRESHOLD
+#define STM32_FLASHBITS             0x00000007
+#else
+#define STM32_FLASHBITS             0x00000008
+#endif
+
+/* There are differences in vector names in the various sub-families,
+   normalizing.*/
+#if 0
+#define TIM1_BRK_IRQn       TIM1_BRK_TIM9_IRQn
+#define TIM1_UP_IRQn        TIM1_UP_TIM10_IRQn
+#define TIM1_TRG_COM_IRQn   TIM1_TRG_COM_TIM11_IRQn
+#define TIM8_BRK_IRQn       TIM8_BRK_TIM12_IRQn
+#define TIM8_UP_IRQn        TIM8_UP_TIM13_IRQn
+#define TIM8_TRG_COM_IRQn   TIM8_TRG_COM_TIM14_IRQn
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk
new file mode 100644
index 000000000..c9b74b45c
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/platform.mk
@@ -0,0 +1,36 @@
+# List of all the STM32F2xx/STM32F4xx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/stm32_dma.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/adc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/can_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/ext_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/mac_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/sdc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
+ 			  ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/DACv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/OTGv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_dma.c b/os/hal/ports/STM32/STM32F4xx/stm32_dma.c
new file mode 100644
index 000000000..f64e34b4f
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_dma.c
@@ -0,0 +1,527 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F4xx/stm32_dma.c
+ * @brief   Enhanced DMA helper driver code.
+ *
+ * @addtogroup STM32F4xx_DMA
+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a
+ *          shared resource, this driver allows to allocate and free DMA
+ *          streams at runtime in order to allow all the other device
+ *          drivers to coordinate the access to the resource.
+ * @note    The DMA ISR handlers are all declared into this module because
+ *          sharing, the various device drivers can associate a callback to
+ *          ISRs when allocating streams.
+ * @{
+ */
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA1_STREAMS_MASK     0x000000FF
+
+/**
+ * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA2_STREAMS_MASK     0x0000FF00
+
+/**
+ * @brief   Post-reset value of the stream CR register.
+ */
+#define STM32_DMA_CR_RESET_VALUE    0x00000000
+
+/**
+ * @brief   Post-reset value of the stream FCR register.
+ */
+#define STM32_DMA_FCR_RESET_VALUE   0x00000021
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ *          identifier and the involved physical registers.
+ * @note    Don't use this array directly, use the appropriate wrapper macros
+ *          instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
+ */
+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
+  {DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn},
+  {DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn},
+  {DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn},
+  {DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn},
+  {DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn},
+  {DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn},
+  {DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn},
+  {DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn},
+  {DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn},
+  {DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn},
+  {DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn},
+  {DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn},
+  {DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn},
+  {DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn},
+  {DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn},
+  {DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn},
+};
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA ISR redirector type.
+ */
+typedef struct {
+  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
+  void                  *dma_param;     /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
+/**
+ * @brief   Mask of the allocated streams.
+ */
+static uint32_t dma_streams_mask;
+
+/**
+ * @brief   DMA IRQ redirectors.
+ */
+static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA1 stream 0 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector6C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA1->LIFCR = flags << 0;
+  if (dma_isr_redir[0].dma_func)
+    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;
+  DMA1->LIFCR = flags << 6;
+  if (dma_isr_redir[1].dma_func)
+    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector74) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA1->LIFCR = flags << 16;
+  if (dma_isr_redir[2].dma_func)
+    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector78) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;
+  DMA1->LIFCR = flags << 22;
+  if (dma_isr_redir[3].dma_func)
+    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector7C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA1->HIFCR = flags << 0;
+  if (dma_isr_redir[4].dma_func)
+    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector80) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;
+  DMA1->HIFCR = flags << 6;
+  if (dma_isr_redir[5].dma_func)
+    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 6 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector84) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA1->HIFCR = flags << 16;
+  if (dma_isr_redir[6].dma_func)
+    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 7 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorFC) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;
+  DMA1->HIFCR = flags << 22;
+  if (dma_isr_redir[7].dma_func)
+    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 0 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector120) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA2->LIFCR = flags << 0;
+  if (dma_isr_redir[8].dma_func)
+    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector124) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;
+  DMA2->LIFCR = flags << 6;
+  if (dma_isr_redir[9].dma_func)
+    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector128) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA2->LIFCR = flags << 16;
+  if (dma_isr_redir[10].dma_func)
+    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector12C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;
+  DMA2->LIFCR = flags << 22;
+  if (dma_isr_redir[11].dma_func)
+    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector130) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA2->HIFCR = flags << 0;
+  if (dma_isr_redir[12].dma_func)
+    dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector150) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;
+  DMA2->HIFCR = flags << 6;
+  if (dma_isr_redir[13].dma_func)
+    dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 6 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector154) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA2->HIFCR = flags << 16;
+  if (dma_isr_redir[14].dma_func)
+    dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 7 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector158) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;
+  DMA2->HIFCR = flags << 22;
+  if (dma_isr_redir[15].dma_func)
+    dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+  int i;
+
+  dma_streams_mask = 0;
+  for (i = 0; i < STM32_DMA_STREAMS; i++) {
+    _stm32_dma_streams[i].stream->CR = 0;
+    dma_isr_redir[i].dma_func = NULL;
+  }
+  DMA1->LIFCR = 0xFFFFFFFF;
+  DMA1->HIFCR = 0xFFFFFFFF;
+  DMA2->LIFCR = 0xFFFFFFFF;
+  DMA2->HIFCR = 0xFFFFFFFF;
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ * @pre     The stream must not be already in use or an error is returned.
+ * @post    The stream is allocated and the default ISR handler redirected
+ *          to the specified function.
+ * @post    The stream ISR vector is enabled and its priority configured.
+ * @post    The stream must be freed using @p dmaStreamRelease() before it can
+ *          be reused with another peripheral.
+ * @post    The stream is in its post-reset state.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] priority  IRQ priority mask for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              The operation status.
+ * @retval FALSE        no error, stream taken.
+ * @retval TRUE         error, stream already taken.
+ *
+ * @special
+ */
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                       uint32_t priority,
+                       stm32_dmaisr_t func,
+                       void *param) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Checks if the stream is already taken.*/
+  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
+    return TRUE;
+
+  /* Marks the stream as allocated.*/
+  dma_isr_redir[dmastp->selfindex].dma_func  = func;
+  dma_isr_redir[dmastp->selfindex].dma_param = param;
+  dma_streams_mask |= (1 << dmastp->selfindex);
+
+  /* Enabling DMA clocks required by the current streams set.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
+    rccEnableDMA1(FALSE);
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
+    rccEnableDMA2(FALSE);
+
+  /* Putting the stream in a safe state.*/
+  dmaStreamDisable(dmastp);
+  dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
+  dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
+
+  /* Enables the associated IRQ vector if a callback is defined.*/
+  if (func != NULL)
+    nvicEnableVector(dmastp->vector, priority);
+
+  return FALSE;
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    The stream is again available.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Check if the streams is not taken.*/
+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+                "not allocated");
+
+  /* Disables the associated IRQ vector.*/
+  nvicDisableVector(dmastp->vector);
+
+  /* Marks the stream as not allocated.*/
+  dma_streams_mask &= ~(1 << dmastp->selfindex);
+
+  /* Shutting down clocks that are no more required, if any.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
+    rccDisableDMA1(FALSE);
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
+    rccDisableDMA2(FALSE);
+}
+
+#endif /* STM32_DMA_REQUIRED */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_dma.h b/os/hal/ports/STM32/STM32F4xx/stm32_dma.h
new file mode 100644
index 000000000..cb0d01688
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_dma.h
@@ -0,0 +1,461 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F4xx/stm32_dma.h
+ * @brief   Enhanced-DMA helper driver header.
+ * @note    This file requires definitions from the ST STM32F4xx header file
+ *          stm32f4xx.h.
+ *
+ * @addtogroup STM32F4xx_DMA
+ * @{
+ */
+
+#ifndef _STM32_DMA_H_
+#define _STM32_DMA_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Total number of DMA streams.
+ * @note    This is the total number of streams among all the DMA units.
+ */
+#define STM32_DMA_STREAMS           16
+
+/**
+ * @brief   Mask of the ISR bits passed to the DMA callback functions.
+ */
+#define STM32_DMA_ISR_MASK          0x3D
+
+/**
+ * @brief   Returns the channel associated to the specified stream.
+ *
+ * @param[in] id        the unique numeric stream identifier
+ * @param[in] c         a stream/channel association word, one channel per
+ *                      nibble
+ * @return              Returns the channel associated to the stream.
+ */
+#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7)
+
+/**
+ * @brief   Checks if a DMA priority is within the valid range.
+ * @param[in] prio      DMA priority
+ *
+ * @retval              The check result.
+ * @retval FALSE        invalid DMA priority.
+ * @retval TRUE         correct DMA priority.
+ */
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+
+/**
+ * @brief   Returns an unique numeric identifier for a DMA stream.
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              An unique numeric stream identifier.
+ */
+#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream))
+
+/**
+ * @brief   Returns a DMA stream identifier mask.
+ *
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              A DMA stream identifier mask.
+ */
+#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
+  (1 << STM32_DMA_STREAM_ID(dma, stream))
+
+/**
+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.
+ * @param[in] id        the stream numeric identifier
+ * @param[in] mask      the stream numeric identifiers mask
+ *
+ * @retval              The check result.
+ * @retval FALSE        id does not belong to the mask.
+ * @retval TRUE         id belongs to the mask.
+ */
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+
+/**
+ * @name    DMA streams identifiers
+ * @{
+ */
+/**
+ * @brief   Returns a pointer to a stm32_dma_stream_t structure.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @return              A pointer to the stm32_dma_stream_t constant structure
+ *                      associated to the DMA stream.
+ */
+#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
+
+#define STM32_DMA1_STREAM0          STM32_DMA_STREAM(0)
+#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(1)
+#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(2)
+#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(3)
+#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(4)
+#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(5)
+#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(6)
+#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(7)
+#define STM32_DMA2_STREAM0          STM32_DMA_STREAM(8)
+#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(9)
+#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(10)
+#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(11)
+#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(12)
+#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(13)
+#define STM32_DMA2_STREAM6          STM32_DMA_STREAM(14)
+#define STM32_DMA2_STREAM7          STM32_DMA_STREAM(15)
+/** @} */
+
+/**
+ * @name    CR register constants common to all DMA types
+ * @{
+ */
+#define STM32_DMA_CR_EN             DMA_SxCR_EN
+#define STM32_DMA_CR_TEIE           DMA_SxCR_TEIE
+#define STM32_DMA_CR_HTIE           DMA_SxCR_HTIE
+#define STM32_DMA_CR_TCIE           DMA_SxCR_TCIE
+#define STM32_DMA_CR_DIR_MASK       DMA_SxCR_DIR
+#define STM32_DMA_CR_DIR_P2M        0
+#define STM32_DMA_CR_DIR_M2P        DMA_SxCR_DIR_0
+#define STM32_DMA_CR_DIR_M2M        DMA_SxCR_DIR_1
+#define STM32_DMA_CR_CIRC           DMA_SxCR_CIRC
+#define STM32_DMA_CR_PINC           DMA_SxCR_PINC
+#define STM32_DMA_CR_MINC           DMA_SxCR_MINC
+#define STM32_DMA_CR_PSIZE_MASK     DMA_SxCR_PSIZE
+#define STM32_DMA_CR_PSIZE_BYTE     0
+#define STM32_DMA_CR_PSIZE_HWORD    DMA_SxCR_PSIZE_0
+#define STM32_DMA_CR_PSIZE_WORD     DMA_SxCR_PSIZE_1
+#define STM32_DMA_CR_MSIZE_MASK     DMA_SxCR_MSIZE
+#define STM32_DMA_CR_MSIZE_BYTE     0
+#define STM32_DMA_CR_MSIZE_HWORD    DMA_SxCR_MSIZE_0
+#define STM32_DMA_CR_MSIZE_WORD     DMA_SxCR_MSIZE_1
+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
+                                     STM32_DMA_CR_MSIZE_MASK)
+#define STM32_DMA_CR_PL_MASK        DMA_SxCR_PL
+#define STM32_DMA_CR_PL(n)          ((n) << 16)
+/** @} */
+
+/**
+ * @name    CR register constants only found in STM32F2xx/STM32F4xx
+ * @{
+ */
+#define STM32_DMA_CR_DMEIE          DMA_SxCR_DMEIE
+#define STM32_DMA_CR_PFCTRL         DMA_SxCR_PFCTRL
+#define STM32_DMA_CR_PINCOS         DMA_SxCR_PINCOS
+#define STM32_DMA_CR_DBM            DMA_SxCR_DBM
+#define STM32_DMA_CR_CT             DMA_SxCR_CT
+#define STM32_DMA_CR_PBURST_MASK    DMA_SxCR_PBURST
+#define STM32_DMA_CR_PBURST_SINGLE  0
+#define STM32_DMA_CR_PBURST_INCR4   DMA_SxCR_PBURST_0
+#define STM32_DMA_CR_PBURST_INCR8   DMA_SxCR_PBURST_1
+#define STM32_DMA_CR_PBURST_INCR16  (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
+#define STM32_DMA_CR_MBURST_MASK    DMA_SxCR_MBURST
+#define STM32_DMA_CR_MBURST_SINGLE  0
+#define STM32_DMA_CR_MBURST_INCR4   DMA_SxCR_MBURST_0
+#define STM32_DMA_CR_MBURST_INCR8   DMA_SxCR_MBURST_1
+#define STM32_DMA_CR_MBURST_INCR16  (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
+#define STM32_DMA_CR_CHSEL_MASK     DMA_SxCR_CHSEL
+#define STM32_DMA_CR_CHSEL(n)       ((n) << 25)
+/** @} */
+
+/**
+ * @name    FCR register constants only found in STM32F2xx/STM32F4xx
+ * @{
+ */
+#define STM32_DMA_FCR_FEIE          DMA_SxFCR_FEIE
+#define STM32_DMA_FCR_FS_MASK       DMA_SxFCR_FS
+#define STM32_DMA_FCR_DMDIS         DMA_SxFCR_DMDIS
+#define STM32_DMA_FCR_FTH_MASK      DMA_SxFCR_FTH
+#define STM32_DMA_FCR_FTH_1Q        0
+#define STM32_DMA_FCR_FTH_HALF      DMA_SxFCR_FTH_0
+#define STM32_DMA_FCR_FTH_3Q        DMA_SxFCR_FTH_1
+#define STM32_DMA_FCR_FTH_FULL      (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)
+/** @} */
+
+/**
+ * @name    Status flags passed to the ISR callbacks
+ */
+#define STM32_DMA_ISR_FEIF          DMA_LISR_FEIF0
+#define STM32_DMA_ISR_DMEIF         DMA_LISR_DMEIF0
+#define STM32_DMA_ISR_TEIF          DMA_LISR_TEIF0
+#define STM32_DMA_ISR_HTIF          DMA_LISR_HTIF0
+#define STM32_DMA_ISR_TCIF          DMA_LISR_TCIF0
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA stream descriptor structure.
+ */
+typedef struct {
+  DMA_Stream_TypeDef    *stream;        /**< @brief Associated DMA stream.  */
+  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
+  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
+                                             register.                      */
+  uint8_t               selfindex;      /**< @brief Index to self in array. */
+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
+} stm32_dma_stream_t;
+
+/**
+ * @brief   STM32 DMA ISR function type.
+ *
+ * @param[in] p         parameter for the registered function
+ * @param[in] flags     pre-shifted content of the xISR register, the bits
+ *                      are aligned to bit zero
+ */
+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Associates a peripheral data register to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the PAR register
+ *
+ * @special
+ */
+#define dmaStreamSetPeripheral(dmastp, addr) {                              \
+  (dmastp)->stream->PAR  = (uint32_t)(addr);                                \
+}
+
+/**
+ * @brief   Associates a memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the M0AR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory0(dmastp, addr) {                                 \
+  (dmastp)->stream->M0AR  = (uint32_t)(addr);                               \
+}
+
+/**
+ * @brief   Associates an alternate memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the M1AR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory1(dmastp, addr) {                                 \
+  (dmastp)->stream->M1AR  = (uint32_t)(addr);                               \
+}
+
+/**
+ * @brief   Sets the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] size      value to be written in the CNDTR register
+ *
+ * @special
+ */
+#define dmaStreamSetTransactionSize(dmastp, size) {                         \
+  (dmastp)->stream->NDTR  = (uint32_t)(size);                               \
+}
+
+/**
+ * @brief   Returns the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @return              The number of transfers to be performed.
+ *
+ * @special
+ */
+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR))
+
+/**
+ * @brief   Programs the stream mode settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CR register
+ *
+ * @special
+ */
+#define dmaStreamSetMode(dmastp, mode) {                                    \
+  (dmastp)->stream->CR  = (uint32_t)(mode);                                 \
+}
+
+/**
+ * @brief   Programs the stream FIFO settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the FCR register
+ *
+ * @special
+ */
+#define dmaStreamSetFIFO(dmastp, mode) {                                    \
+  (dmastp)->stream->FCR = (uint32_t)(mode);                                 \
+}
+
+/**
+ * @brief   DMA stream enable.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamEnable(dmastp) {                                           \
+  (dmastp)->stream->CR |= STM32_DMA_CR_EN;                                  \
+}
+
+/**
+ * @brief   DMA stream disable.
+ * @details The function disables the specified stream, waits for the disable
+ *          operation to complete and then clears any pending interrupt.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @note    Interrupts enabling flags are set to zero after this call, see
+ *          bug 3607518.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamDisable(dmastp) {                                          \
+  (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE  |        \
+                            STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE |        \
+                            STM32_DMA_CR_EN);                               \
+  while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0)                     \
+    ;                                                                       \
+  dmaStreamClearInterrupt(dmastp);                                          \
+}
+
+/**
+ * @brief   DMA stream interrupt sources clear.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamClearInterrupt(dmastp) {                                   \
+  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
+}
+
+/**
+ * @brief   Starts a memory to memory operation using the specified stream.
+ * @note    The default transfer data mode is "byte to byte" but it can be
+ *          changed by specifying extra options in the @p mode parameter.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register, this value
+ *                      is implicitly ORed with:
+ *                      - @p STM32_DMA_CR_MINC
+ *                      - @p STM32_DMA_CR_PINC
+ *                      - @p STM32_DMA_CR_DIR_M2M
+ *                      - @p STM32_DMA_CR_EN
+ *                      .
+ * @param[in] src       source address
+ * @param[in] dst       destination address
+ * @param[in] n         number of data units to copy
+ */
+#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
+  dmaStreamSetPeripheral(dmastp, src);                                      \
+  dmaStreamSetMemory0(dmastp, dst);                                         \
+  dmaStreamSetTransactionSize(dmastp, n);                                   \
+  dmaStreamSetMode(dmastp, (mode) |                                         \
+                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
+                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
+}
+
+/**
+ * @brief   Polled wait for DMA transfer end.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ */
+#define dmaWaitCompletion(dmastp) {                                         \
+  while ((dmastp)->stream->NDTR > 0)                                        \
+    ;                                                                       \
+  dmaStreamDisable(dmastp);                                                 \
+}
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dmaInit(void);
+  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                         uint32_t priority,
+                         stm32_dmaisr_t func,
+                         void *param);
+  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_DMA_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
new file mode 100644
index 000000000..dc7fbd1ab
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
@@ -0,0 +1,171 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F4xx/stm32_isr.h
+ * @brief   ISR remapper driver header.
+ *
+ * @addtogroup STM32F4xx_ISR
+ * @{
+ */
+
+#ifndef _STM32_ISR_H_
+#define _STM32_ISR_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    ISR names and numbers remapping
+ * @{
+ */
+/*
+ * CAN units.
+ */
+#define STM32_CAN1_TX_HANDLER       Vector8C
+#define STM32_CAN1_RX0_HANDLER      Vector90
+#define STM32_CAN1_RX1_HANDLER      Vector94
+#define STM32_CAN1_SCE_HANDLER      Vector98
+#define STM32_CAN2_TX_HANDLER       Vector13C
+#define STM32_CAN2_RX0_HANDLER      Vector140
+#define STM32_CAN2_RX1_HANDLER      Vector144
+#define STM32_CAN2_SCE_HANDLER      Vector148
+
+#define STM32_CAN1_TX_NUMBER        19
+#define STM32_CAN1_RX0_NUMBER       20
+#define STM32_CAN1_RX1_NUMBER       21
+#define STM32_CAN1_SCE_NUMBER       22
+#define STM32_CAN2_TX_NUMBER        63
+#define STM32_CAN2_RX0_NUMBER       64
+#define STM32_CAN2_RX1_NUMBER       65
+#define STM32_CAN2_SCE_NUMBER       66
+
+/*
+ * I2C units.
+ */
+#define STM32_I2C1_EVENT_HANDLER    VectorBC
+#define STM32_I2C1_ERROR_HANDLER    VectorC0
+#define STM32_I2C1_EVENT_NUMBER     31
+#define STM32_I2C1_ERROR_NUMBER     32
+
+#define STM32_I2C2_EVENT_HANDLER    VectorC4
+#define STM32_I2C2_ERROR_HANDLER    VectorC8
+#define STM32_I2C2_EVENT_NUMBER     33
+#define STM32_I2C2_ERROR_NUMBER     34
+
+/*
+ * OTG units.
+ */
+#define STM32_OTG1_HANDLER          Vector14C
+#define STM32_OTG2_HANDLER          Vector174
+#define STM32_OTG2_EP1OUT_HANDLER   Vector168
+#define STM32_OTG2_EP1IN_HANDLER    Vector16C
+
+#define STM32_OTG1_NUMBER           67
+#define STM32_OTG2_NUMBER           77
+#define STM32_OTG2_EP1OUT_NUMBER    74
+#define STM32_OTG2_EP1IN_NUMBER     75
+
+/*
+ * SDIO unit.
+ */
+#define STM32_SDIO_HANDLER          Vector104
+
+#define STM32_SDIO_NUMBER           49
+
+/*
+ * TIM units.
+ */
+#define STM32_TIM1_UP_HANDLER       VectorA4
+#define STM32_TIM1_CC_HANDLER       VectorAC
+#define STM32_TIM2_HANDLER          VectorB0
+#define STM32_TIM3_HANDLER          VectorB4
+#define STM32_TIM4_HANDLER          VectorB8
+#define STM32_TIM5_HANDLER          Vector108
+#define STM32_TIM6_HANDLER          Vector118
+#define STM32_TIM7_HANDLER          Vector11C
+#define STM32_TIM8_UP_HANDLER       VectorF0
+#define STM32_TIM8_CC_HANDLER       VectorF8
+#define STM32_TIM9_HANDLER          VectorA0
+#define STM32_TIM11_HANDLER         VectorA8
+#define STM32_TIM12_HANDLER         VectorEC
+#define STM32_TIM14_HANDLER         VectorF4
+
+#define STM32_TIM1_UP_NUMBER        25
+#define STM32_TIM1_CC_NUMBER        27
+#define STM32_TIM2_NUMBER           28
+#define STM32_TIM3_NUMBER           29
+#define STM32_TIM4_NUMBER           30
+#define STM32_TIM5_NUMBER           50
+#define STM32_TIM6_NUMBER           54
+#define STM32_TIM7_NUMBER           55
+#define STM32_TIM8_UP_NUMBER        44
+#define STM32_TIM8_CC_NUMBER        46
+#define STM32_TIM9_NUMBER           24
+#define STM32_TIM11_NUMBER          26
+#define STM32_TIM12_NUMBER          43
+#define STM32_TIM14_NUMBER          45
+
+/*
+ * USART units.
+ */
+#define STM32_USART1_HANDLER        VectorD4
+#define STM32_USART2_HANDLER        VectorD8
+#define STM32_USART3_HANDLER        VectorDC
+#define STM32_UART4_HANDLER         Vector110
+#define STM32_UART5_HANDLER         Vector114
+#define STM32_USART6_HANDLER        Vector15C
+
+#define STM32_USART1_NUMBER         37
+#define STM32_USART2_NUMBER         38
+#define STM32_USART3_NUMBER         39
+#define STM32_UART4_NUMBER          52
+#define STM32_UART5_NUMBER          53
+#define STM32_USART6_NUMBER         71
+
+/*
+ * Ethernet
+ */
+#define ETH_IRQHandler          Vector134
+
+/** @} */
+
+
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#endif /* _STM32_ISR_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
index b2d45d5aa..b2d45d5aa 100644
--- a/os/hal/platforms/STM32F4xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
new file mode 100644
index 000000000..5d30f690a
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -0,0 +1,330 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F4xx/stm32_registry.h
+ * @brief   STM32F4xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    STM32F4xx capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC1_DMA_CHN                  0x00000000
+
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_ADC2_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC2_DMA_CHN                  0x00001100
+
+#define STM32_HAS_ADC3                      TRUE
+#define STM32_ADC3_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_ADC3_DMA_CHN                  0x00000022
+
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      TRUE
+#define STM32_CAN_MAX_FILTERS               28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      FALSE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  TRUE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      TRUE
+
+/* ETH attributes.*/
+#if !defined(STM32F401xx)
+#define STM32_HAS_ETH                       TRUE
+#else /* defined(STM32F401xx) */
+#define STM32_HAS_ETH                       FALSE
+#endif /* defined(STM32F401xx) */
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             23
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOH                     TRUE
+#if !defined(STM32F401xx)
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     TRUE
+#define STM32_HAS_GPIOI                     TRUE
+#else /* defined(STM32F401xx) */
+#define STM32_HAS_GPIOF                     FALSE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#endif /* defined(STM32F401xx) */
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+                                             STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C1_RX_DMA_CHN               0x00100001
+#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+                                             STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN               0x11000000
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+                                             STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C2_RX_DMA_CHN               0x00007700
+#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_I2C2_TX_DMA_CHN               0x70000000
+
+#define STM32_HAS_I2C3                      TRUE
+#define STM32_I2C3_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_I2C3_RX_DMA_CHN               0x00000300
+#define STM32_I2C3_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C3_TX_DMA_CHN               0x00030000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#if defined(STM32F4XX) || defined(__DOXYGEN__)
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#else
+#define STM32_RTC_HAS_SUBSECONDS            FALSE
+#endif
+#define STM32_RTC_IS_CALENDAR               TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      TRUE
+#define STM32_SDC_SDIO_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDIO_DMA_CHN              0x04004000
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI1_RX_DMA_CHN               0x00000303
+#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI1_TX_DMA_CHN               0x00303000
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI2_RX_DMA_CHN               0x00000000
+#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_TX_DMA_CHN               0x00000000
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\
+                                             STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI3_RX_DMA_CHN               0x00000000
+#define STM32_SPI3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+                                             STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI3_TX_DMA_CHN               0x00000000
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) ||                 \
+    defined(STM32F401xx)
+#define STM32_HAS_SPI4                      TRUE
+#define STM32_SPI4_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI4_RX_DMA_CHN               0x00005004
+#define STM32_SPI4_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI4_TX_DMA_CHN               0x00050040
+#else
+#define STM32_HAS_SPI4                      FALSE
+#endif
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
+#define STM32_HAS_SPI5                      TRUE
+#define STM32_SPI5_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |            \
+                                             STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI5_RX_DMA_CHN               0x00702000
+#define STM32_SPI5_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 4) |            \
+                                             STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI5_TX_DMA_CHN               0x07020000
+
+#define STM32_HAS_SPI6                      TRUE
+#define STM32_SPI6_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SPI6_RX_DMA_CHN               0x01000000
+#define STM32_SPI6_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SPI6_TX_DMA_CHN               0x00100000
+
+#else /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+#endif /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
+
+/* TIM attributes.*/
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 4
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM5                      TRUE
+#define STM32_TIM5_IS_32BITS                TRUE
+#define STM32_TIM5_CHANNELS                 4
+
+#if !defined(STM32F401xx)
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM8                      TRUE
+#define STM32_TIM8_IS_32BITS                FALSE
+#define STM32_TIM8_CHANNELS                 6
+
+#else /* defined(STM32F401xx) */
+#define STM32_HAS_TIM6                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#endif /* defined(STM32F401xx) */
+
+#define STM32_HAS_TIM9                      TRUE
+#define STM32_TIM9_IS_32BITS                FALSE
+#define STM32_TIM9_CHANNELS                 2
+
+#define STM32_HAS_TIM10                     TRUE
+#define STM32_TIM10_IS_32BITS               FALSE
+#define STM32_TIM10_CHANNELS                2
+
+#define STM32_HAS_TIM11                     TRUE
+#define STM32_TIM11_IS_32BITS               FALSE
+#define STM32_TIM11_CHANNELS                2
+
+#if !defined(STM32F401xx)
+#define STM32_HAS_TIM12                     TRUE
+#define STM32_TIM12_IS_32BITS               FALSE
+#define STM32_TIM12_CHANNELS                2
+
+#define STM32_HAS_TIM13                     TRUE
+#define STM32_TIM13_IS_32BITS               FALSE
+#define STM32_TIM13_CHANNELS                2
+
+#define STM32_HAS_TIM14                     TRUE
+#define STM32_TIM14_IS_32BITS               FALSE
+#define STM32_TIM14_CHANNELS                2
+
+#else /* defined(STM32F401xx) */
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#endif /* defined(STM32F401xx) */
+
+#define STM32_HAS_TIM15                     FALSE
+#define STM32_HAS_TIM16                     FALSE
+#define STM32_HAS_TIM17                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_USART1_RX_DMA_CHN             0x00400400
+#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_USART1_TX_DMA_CHN             0x40000000
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_USART2_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_USART2_RX_DMA_CHN             0x00400000
+#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)
+#define STM32_USART2_TX_DMA_CHN             0x04000000
+
+#if !defined(STM32F401xx)
+#define STM32_HAS_USART3                    TRUE
+#define STM32_USART3_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 1)
+#define STM32_USART3_RX_DMA_CHN             0x00000040
+#define STM32_USART3_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+                                             STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART3_TX_DMA_CHN             0x00074000
+
+#define STM32_HAS_UART4                     TRUE
+#define STM32_UART4_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_UART4_RX_DMA_CHN              0x00000400
+#define STM32_UART4_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_UART4_TX_DMA_CHN              0x00040000
+
+#define STM32_HAS_UART5                     TRUE
+#define STM32_UART5_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 0)
+#define STM32_UART5_RX_DMA_CHN              0x00000004
+#define STM32_UART5_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_UART5_TX_DMA_CHN              0x40000000
+
+#else /* defined(STM32F401xx) */
+#define STM32_HAS_USART3                    FALSE
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#endif /* defined(STM32F401xx) */
+
+#define STM32_HAS_USART6                    TRUE
+#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_USART6_RX_DMA_CHN             0x00000550
+#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\
+                                             STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART6_TX_DMA_CHN             0x55000000
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      TRUE
+#if !defined(STM32F401xx)
+#define STM32_HAS_OTG2                      TRUE
+#else /* defined(STM32F401xx) */
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F401xx) */
+/** @} */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L1xx/adc_lld.c b/os/hal/ports/STM32/STM32L1xx/adc_lld.c
new file mode 100644
index 000000000..1f4649c9c
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/adc_lld.c
@@ -0,0 +1,280 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32L1xx/adc_lld.c
+ * @brief   STM32L1xx ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC DMA ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    /* DMA, this could help only if the DMA tries to access an unmapped
+       address space or violates alignment rules.*/
+    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+  }
+  else {
+    /* It is possible that the conversion group has already be reset by the
+       ADC error handler, in this case this interrupt is spurious.*/
+    if (adcp->grpp != NULL) {
+      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+        /* Transfer complete processing.*/
+        _adc_isr_full_code(adcp);
+      }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief   ADC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector88) {
+  uint32_t sr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  sr = ADC1->SR;
+  ADC1->SR = 0;
+  /* Note, an overflow may occur after the conversion ended before the driver
+     is able to stop the ADC, this is why the DMA channel is checked too.*/
+  if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
+    /* ADC overflow condition, this could happen only if the DMA is unable
+       to read data fast enough.*/
+    if (ADCD1.grpp != NULL)
+      _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+  }
+  /* TODO: Add here analog watchdog handling.*/
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adc = ADC1;
+  ADCD1.dmastp  = STM32_DMA1_STREAM1;
+  ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+#endif
+
+  /* The shared vector is initialized on driver initialization and never
+     disabled.*/
+  nvicEnableVector(ADC1_IRQn, STM32_ADC_IRQ_PRIORITY);
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+  /* If in stopped state then enables the ADC and DMA clocks.*/
+  if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      bool b = dmaStreamAllocate(adcp->dmastp,
+                                 STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+                                 (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+                                 (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+      rccEnableADC1(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC1 */
+
+    /* ADC initial setup, starting the analog part here in order to reduce
+       the latency when starting a conversion.*/
+    adcp->adc->CR1 = 0;
+    adcp->adc->CR2 = 0;
+    adcp->adc->CR2 = ADC_CR2_ADON;
+  }
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+  /* If in ready state then disables the ADC clock and analog part.*/
+  if (adcp->state == ADC_READY) {
+    dmaStreamRelease(adcp->dmastp);
+    adcp->adc->CR1 = 0;
+    adcp->adc->CR2 = 0;
+
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp)
+      rccDisableADC1(FALSE);
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+  uint32_t mode;
+  const ADCConversionGroup *grpp = adcp->grpp;
+
+  /* DMA setup.*/
+  mode = adcp->dmamode;
+  if (grpp->circular) {
+    mode |= STM32_DMA_CR_CIRC;
+    if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
+      mode |= STM32_DMA_CR_HTIE;
+    }
+  }
+  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+                                            (uint32_t)adcp->depth);
+  dmaStreamSetMode(adcp->dmastp, mode);
+  dmaStreamEnable(adcp->dmastp);
+
+  /* ADC setup.*/
+  adcp->adc->SR    = 0;
+  adcp->adc->SMPR1 = grpp->smpr1;
+  adcp->adc->SMPR2 = grpp->smpr2;
+  adcp->adc->SMPR3 = grpp->smpr3;
+  adcp->adc->SQR1  = grpp->sqr1;
+  adcp->adc->SQR2  = grpp->sqr2;
+  adcp->adc->SQR3  = grpp->sqr3;
+  adcp->adc->SQR4  = grpp->sqr4;
+  adcp->adc->SQR5  = grpp->sqr5;
+
+  /* ADC configuration and start, the start is performed using the method
+     specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
+  adcp->adc->CR1   = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
+  if ((grpp->cr2 & ADC_CR2_SWSTART) != 0)
+    adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT  | ADC_CR2_DMA |
+                                 ADC_CR2_DDS   | ADC_CR2_ADON;
+  else
+    adcp->adc->CR2 = grpp->cr2 |                 ADC_CR2_DMA |
+                                 ADC_CR2_DDS   | ADC_CR2_ADON;
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+  dmaStreamDisable(adcp->dmastp);
+  adcp->adc->CR1 = 0;
+  adcp->adc->CR2 = 0;
+  adcp->adc->CR2 = ADC_CR2_ADON;
+}
+
+/**
+ * @brief   Enables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ *          temperature sensor and internal reference voltage.
+ * @note    This is an STM32-only functionality.
+ */
+void adcSTM32EnableTSVREFE(void) {
+
+  ADC->CCR |= ADC_CCR_TSVREFE;
+}
+
+/**
+ * @brief   Disables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ *          temperature sensor and internal reference voltage.
+ * @note    This is an STM32-only functionality.
+ */
+void adcSTM32DisableTSVREFE(void) {
+
+  ADC->CCR &= ~ADC_CCR_TSVREFE;
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L1xx/adc_lld.h b/os/hal/ports/STM32/STM32L1xx/adc_lld.h
new file mode 100644
index 000000000..c7bb73612
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/adc_lld.h
@@ -0,0 +1,480 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32L1xx/adc_lld.h
+ * @brief   STM32L1xx ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Triggers selection
+ * @{
+ */
+#define ADC_CR2_EXTSEL_SRC(n)   ((n) << 24) /**< @brief Trigger source.     */
+/** @} */
+
+/**
+ * @name    ADC clock divider settings
+ * @{
+ */
+#define ADC_CCR_ADCPRE_DIV1     0
+#define ADC_CCR_ADCPRE_DIV2     1
+#define ADC_CCR_ADCPRE_DIV4     2
+/** @} */
+
+/**
+ * @name    Available analog channels
+ * @{
+ */
+#define ADC_CHANNEL_IN0         0   /**< @brief External analog input 0.    */
+#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
+#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
+#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
+#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
+#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
+#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
+#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
+#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
+#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
+#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
+#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
+#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
+#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
+#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
+#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
+#define ADC_CHANNEL_SENSOR      16  /**< @brief Internal temperature sensor.*/
+#define ADC_CHANNEL_VREFINT     17  /**< @brief Internal reference.         */
+#define ADC_CHANNEL_IN18        18  /**< @brief External analog input 18.   */
+#define ADC_CHANNEL_IN19        19  /**< @brief External analog input 19.   */
+#define ADC_CHANNEL_IN20        20  /**< @brief External analog input 20.   */
+#define ADC_CHANNEL_IN21        21  /**< @brief External analog input 21.   */
+#define ADC_CHANNEL_IN22        22  /**< @brief External analog input 22.   */
+#define ADC_CHANNEL_IN23        23  /**< @brief External analog input 23.   */
+#define ADC_CHANNEL_IN24        24  /**< @brief External analog input 24.   */
+#define ADC_CHANNEL_IN25        25  /**< @brief External analog input 25.   */
+/** @} */
+
+/**
+ * @name    Sampling rates
+ * @{
+ */
+#define ADC_SAMPLE_4            0   /**< @brief 4 cycles sampling time.     */
+#define ADC_SAMPLE_9            1   /**< @brief 9 cycles sampling time.     */
+#define ADC_SAMPLE_16           2   /**< @brief 16 cycles sampling time.    */
+#define ADC_SAMPLE_24           3   /**< @brief 24 cycles sampling time.    */
+#define ADC_SAMPLE_48           4   /**< @brief 48 cycles sampling time.    */
+#define ADC_SAMPLE_96           5   /**< @brief 96 cycles sampling time.    */
+#define ADC_SAMPLE_192          6   /**< @brief 192 cycles sampling time.   */
+#define ADC_SAMPLE_384          7   /**< @brief 384 cycles sampling time.   */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1                  FALSE
+#endif
+
+/**
+ * @brief   ADC common clock divider.
+ * @note    This setting is influenced by the VDDA voltage and other
+ *          external conditions, please refer to the STM32L15x datasheet
+ *          for more info.<br>
+ *          See section 6.3.15 "12-bit ADC characteristics".
+ */
+#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV1
+#endif
+
+/**
+ * @brief   ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   ADC interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_IRQ_PRIORITY              5
+#endif
+
+/**
+ * @brief   ADC1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief   Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief   Possible ADC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
+  ADC_ERR_OVERFLOW = 1                      /**< ADC overflow condition.    */
+} adcerror_t;
+
+/**
+ * @brief   Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief   ADC notification callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] buffer    pointer to the most recent samples data
+ * @param[in] n         number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief   ADC error callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] err       ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief   Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ *          operation.
+ * @note    The use of this configuration structure requires knowledge of
+ *          STM32 ADC cell registers interface, please refer to the STM32
+ *          reference manual for details.
+ */
+typedef struct {
+  /**
+   * @brief   Enables the circular buffer mode for the group.
+   */
+  bool                      circular;
+  /**
+   * @brief   Number of the analog channels belonging to the conversion group.
+   */
+  adc_channels_num_t        num_channels;
+  /**
+   * @brief   Callback function associated to the group or @p NULL.
+   */
+  adccallback_t             end_cb;
+  /**
+   * @brief   Error callback or @p NULL.
+   */
+  adcerrorcallback_t        error_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   ADC CR1 register initialization data.
+   * @note    All the required bits must be defined into this field except
+   *          @p ADC_CR1_SCAN that is enforced inside the driver.
+   */
+  uint32_t                  cr1;
+  /**
+   * @brief   ADC CR2 register initialization data.
+   * @note    All the required bits must be defined into this field except
+   *          @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
+   *          enforced inside the driver.
+   */
+  uint32_t                  cr2;
+  /**
+   * @brief   ADC SMPR1 register initialization data.
+   * @details In this field must be specified the sample times for channels
+   *          20...25.
+   */
+  uint32_t                  smpr1;
+  /**
+   * @brief   ADC SMPR2 register initialization data.
+   * @details In this field must be specified the sample times for channels
+   *          10...19.
+   */
+  uint32_t                  smpr2;
+  /**
+   * @brief   ADC SMPR3 register initialization data.
+   * @details In this field must be specified the sample times for channels
+   *          0...9.
+   */
+  uint32_t                  smpr3;
+  /**
+   * @brief   ADC SQR1 register initialization data.
+   * @details Conversion group sequence 25...27 + sequence length.
+   */
+  uint32_t                  sqr1;
+  /**
+   * @brief   ADC SQR2 register initialization data.
+   * @details Conversion group sequence 19...24.
+   */
+  uint32_t                  sqr2;
+  /**
+   * @brief   ADC SQR3 register initialization data.
+   * @details Conversion group sequence 13...18.
+   */
+  uint32_t                  sqr3;
+  /**
+   * @brief   ADC SQR3 register initialization data.
+   * @details Conversion group sequence 7...12.
+   */
+  uint32_t                  sqr4;
+  /**
+   * @brief   ADC SQR3 register initialization data.
+   * @details Conversion group sequence 1...6.
+   */
+  uint32_t                  sqr5;
+} ADCConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  uint32_t                  dummy;
+} ADCConfig;
+
+/**
+ * @brief   Structure representing an ADC driver.
+ */
+struct ADCDriver {
+  /**
+   * @brief Driver state.
+   */
+  adcstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const ADCConfig           *config;
+  /**
+   * @brief Current samples buffer pointer or @p NULL.
+   */
+  adcsample_t               *samples;
+  /**
+   * @brief Current samples buffer depth or @p 0.
+   */
+  size_t                    depth;
+  /**
+   * @brief Current conversion group pointer or @p NULL.
+   */
+  const ADCConversionGroup  *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+  ADC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the ADCx registers block.
+   */
+  ADC_TypeDef               *adc;
+  /**
+   * @brief Pointer to associated DMA channel.
+   */
+  const stm32_dma_stream_t  *dmastp;
+  /**
+   * @brief DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Sequences building helper macros
+ * @{
+ */
+/**
+ * @brief   Number of channels in a conversion sequence.
+ */
+#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 20)
+
+#define ADC_SQR5_SQ1_N(n)       ((n) << 0)  /**< @brief 1st channel in seq. */
+#define ADC_SQR5_SQ2_N(n)       ((n) << 5)  /**< @brief 2nd channel in seq. */
+#define ADC_SQR5_SQ3_N(n)       ((n) << 10) /**< @brief 3rd channel in seq. */
+#define ADC_SQR5_SQ4_N(n)       ((n) << 15) /**< @brief 4th channel in seq. */
+#define ADC_SQR5_SQ5_N(n)       ((n) << 20) /**< @brief 5th channel in seq. */
+#define ADC_SQR5_SQ6_N(n)       ((n) << 25) /**< @brief 6th channel in seq. */
+
+#define ADC_SQR4_SQ7_N(n)       ((n) << 0)  /**< @brief 7th channel in seq. */
+#define ADC_SQR4_SQ8_N(n)       ((n) << 5)  /**< @brief 8th channel in seq. */
+#define ADC_SQR4_SQ9_N(n)       ((n) << 10) /**< @brief 9th channel in seq. */
+#define ADC_SQR4_SQ10_N(n)      ((n) << 15) /**< @brief 10th channel in seq.*/
+#define ADC_SQR4_SQ11_N(n)      ((n) << 20) /**< @brief 11th channel in seq.*/
+#define ADC_SQR4_SQ12_N(n)      ((n) << 25) /**< @brief 12th channel in seq.*/
+
+#define ADC_SQR3_SQ13_N(n)      ((n) << 0)  /**< @brief 13th channel in seq.*/
+#define ADC_SQR3_SQ14_N(n)      ((n) << 5)  /**< @brief 14th channel in seq.*/
+#define ADC_SQR3_SQ15_N(n)      ((n) << 10) /**< @brief 15th channel in seq.*/
+#define ADC_SQR3_SQ16_N(n)      ((n) << 15) /**< @brief 16th channel in seq.*/
+#define ADC_SQR3_SQ17_N(n)      ((n) << 20) /**< @brief 17th channel in seq.*/
+#define ADC_SQR3_SQ18_N(n)      ((n) << 25) /**< @brief 18th channel in seq.*/
+
+#define ADC_SQR2_SQ19_N(n)      ((n) << 0)  /**< @brief 19th channel in seq.*/
+#define ADC_SQR2_SQ20_N(n)      ((n) << 5)  /**< @brief 20th channel in seq.*/
+#define ADC_SQR2_SQ21_N(n)      ((n) << 10) /**< @brief 21th channel in seq.*/
+#define ADC_SQR2_SQ22_N(n)      ((n) << 15) /**< @brief 22th channel in seq.*/
+#define ADC_SQR2_SQ23_N(n)      ((n) << 20) /**< @brief 23th channel in seq.*/
+#define ADC_SQR2_SQ24_N(n)      ((n) << 25) /**< @brief 24th channel in seq.*/
+
+#define ADC_SQR1_SQ25_N(n)      ((n) << 0)  /**< @brief 25th channel in seq.*/
+#define ADC_SQR1_SQ26_N(n)      ((n) << 5)  /**< @brief 26th channel in seq.*/
+#define ADC_SQR1_SQ27_N(n)      ((n) << 10) /**< @brief 27th channel in seq.*/
+/** @} */
+
+/**
+ * @name    Sampling rate settings helper macros
+ * @{
+ */
+#define ADC_SMPR3_SMP_AN0(n)    ((n) << 0)  /**< @brief AN0 sampling time.  */
+#define ADC_SMPR3_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
+#define ADC_SMPR3_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
+#define ADC_SMPR3_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
+#define ADC_SMPR3_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
+#define ADC_SMPR3_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
+#define ADC_SMPR3_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
+#define ADC_SMPR3_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
+#define ADC_SMPR3_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
+#define ADC_SMPR3_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
+
+#define ADC_SMPR2_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
+#define ADC_SMPR2_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
+#define ADC_SMPR2_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
+#define ADC_SMPR2_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
+#define ADC_SMPR2_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
+#define ADC_SMPR2_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
+#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
+                                                 sampling time.             */
+#define ADC_SMPR2_SMP_VREF(n)   ((n) << 21) /**< @brief Voltage Reference
+                                                 sampling time.             */
+#define ADC_SMPR2_SMP_AN18(n)   ((n) << 24) /**< @brief AN18 sampling time. */
+#define ADC_SMPR2_SMP_AN19(n)   ((n) << 27) /**< @brief AN19 sampling time. */
+
+#define ADC_SMPR1_SMP_AN20(n)   ((n) << 0)  /**< @brief AN20 sampling time. */
+#define ADC_SMPR1_SMP_AN21(n)   ((n) << 3)  /**< @brief AN21 sampling time. */
+#define ADC_SMPR1_SMP_AN22(n)   ((n) << 6)  /**< @brief AN22 sampling time. */
+#define ADC_SMPR1_SMP_AN23(n)   ((n) << 9)  /**< @brief AN23 sampling time. */
+#define ADC_SMPR1_SMP_AN24(n)   ((n) << 12) /**< @brief AN24 sampling time. */
+#define ADC_SMPR1_SMP_AN25(n)   ((n) << 15) /**< @brief AN25 sampling time. */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adc_lld_init(void);
+  void adc_lld_start(ADCDriver *adcp);
+  void adc_lld_stop(ADCDriver *adcp);
+  void adc_lld_start_conversion(ADCDriver *adcp);
+  void adc_lld_stop_conversion(ADCDriver *adcp);
+  void adcSTM32EnableTSVREFE(void);
+  void adcSTM32DisableTSVREFE(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c
new file mode 100644
index 000000000..ebc556e6b
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c
@@ -0,0 +1,325 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32L1xx/ext_lld_isr.c
+ * @brief   STM32L1xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 0);
+  EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 1);
+  EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 2);
+  EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 3);
+  EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 4);
+  EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
+  EXTI->PR = pr;
+  if (pr & (1 << 5))
+    EXTD1.config->channels[5].cb(&EXTD1, 5);
+  if (pr & (1 << 6))
+    EXTD1.config->channels[6].cb(&EXTD1, 6);
+  if (pr & (1 << 7))
+    EXTD1.config->channels[7].cb(&EXTD1, 7);
+  if (pr & (1 << 8))
+    EXTD1.config->channels[8].cb(&EXTD1, 8);
+  if (pr & (1 << 9))
+    EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
+                   (1 << 15));
+  EXTI->PR = pr;
+  if (pr & (1 << 10))
+    EXTD1.config->channels[10].cb(&EXTD1, 10);
+  if (pr & (1 << 11))
+    EXTD1.config->channels[11].cb(&EXTD1, 11);
+  if (pr & (1 << 12))
+    EXTD1.config->channels[12].cb(&EXTD1, 12);
+  if (pr & (1 << 13))
+    EXTD1.config->channels[13].cb(&EXTD1, 13);
+  if (pr & (1 << 14))
+    EXTD1.config->channels[14].cb(&EXTD1, 14);
+  if (pr & (1 << 15))
+    EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 16);
+  EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[17] interrupt handler (RTC).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 17);
+  EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+  OSAL_IRQ_EPILOGUE();
+}
+/**
+ * @brief   EXTI[18] interrupt handler (USB_FS_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE8) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 18);
+  EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[19] interrupt handler (TAMPER_STAMP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 19);
+  EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[20] interrupt handler (RTC_WKUP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 20);
+  EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[21]...EXTI[22] interrupt handler (COMP).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector98) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 21) | (1 << 22));
+  EXTI->PR = pr;
+  if (pr & (1 << 21))
+    EXTD1.config->channels[21].cb(&EXTD1, 21);
+  if (pr & (1 << 22))
+    EXTD1.config->channels[22].cb(&EXTD1, 22);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+  nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+  nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+  nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+  nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+  nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+  nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+  nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+  nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+  nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+  nvicEnableVector(USB_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+  nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+  nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+  nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+}
+
+/**
+ * @brief   Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+  nvicDisableVector(EXTI0_IRQn);
+  nvicDisableVector(EXTI1_IRQn);
+  nvicDisableVector(EXTI2_IRQn);
+  nvicDisableVector(EXTI3_IRQn);
+  nvicDisableVector(EXTI4_IRQn);
+  nvicDisableVector(EXTI9_5_IRQn);
+  nvicDisableVector(EXTI15_10_IRQn);
+  nvicDisableVector(PVD_IRQn);
+  nvicDisableVector(RTC_Alarm_IRQn);
+  nvicDisableVector(USB_FS_WKUP_IRQn);
+  nvicDisableVector(TAMPER_STAMP_IRQn);
+  nvicDisableVector(RTC_WKUP_IRQn);
+  nvicDisableVector(COMP_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/platforms/STM32L1xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h
index 9ee4db42e..9ee4db42e 100644
--- a/os/hal/platforms/STM32L1xx/ext_lld_isr.h
+++ b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h
diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.c b/os/hal/ports/STM32/STM32L1xx/hal_lld.c
new file mode 100644
index 000000000..ece540b89
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.c
@@ -0,0 +1,223 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32L1xx/hal_lld.c
+ * @brief   STM32L1xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+/* TODO: LSEBYP like in F3.*/
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the backup domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+  /* Backup domain access enabled and left open.*/
+  PWR->CR |= PWR_CR_DBP;
+
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+    /* Backup domain reset.*/
+    RCC->CSR |= RCC_CSR_RTCRST;
+    RCC->CSR &= ~RCC_CSR_RTCRST;
+  }
+
+  /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+  RCC->CSR |= RCC_CSR_LSEON;
+  while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
+    ;                                     /* Waits until LSE is stable.   */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if ((RCC->CSR & RCC_CSR_RTCEN) == 0) {
+    /* Selects clock source.*/
+    RCC->CSR |= STM32_RTCSEL;
+
+    /* RTC clock enabled.*/
+    RCC->CSR |= RCC_CSR_RTCEN;
+  }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+  /* Reset of all peripherals.*/
+  rccResetAHB(~RCC_AHBRSTR_FLITFRST);
+  rccResetAPB1(~RCC_APB1RSTR_PWRRST);
+  rccResetAPB2(~0);
+
+  /* PWR clock enabled.*/
+  rccEnablePWRInterface(FALSE);
+
+  /* Initializes the backup domain.*/
+  hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+  dmaInit();
+#endif
+
+  /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief   STM32L1xx voltage, clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+#if defined(STM32L1XX_MD) || defined(__DOXYGEN__)
+/**
+ * @brief   Clocks and internal voltage initialization.
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* PWR clock enable.*/
+  RCC->APB1ENR = RCC_APB1ENR_PWREN;
+
+  /* Core voltage setup.*/
+  while ((PWR->CSR & PWR_CSR_VOSF) != 0)
+    ;                           /* Waits until regulator is stable.         */
+  PWR->CR = STM32_VOS;
+  while ((PWR->CSR & PWR_CSR_VOSF) != 0)
+    ;                           /* Waits until regulator is stable.         */
+
+  /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
+     always enabled because it is the fallback clock when PLL the fails.
+     Trim fields are not altered from reset values.*/
+  RCC->CFGR  = 0;
+  RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
+  RCC->CR    = RCC_CR_MSION;
+  while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+    ;                           /* Waits until MSI is stable.               */
+
+#if STM32_HSI_ENABLED
+  /* HSI activation.*/
+  RCC->CR |= RCC_CR_HSION;
+  while ((RCC->CR & RCC_CR_HSIRDY) == 0)
+    ;                           /* Waits until HSI is stable.               */
+#endif
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEBYP;
+#endif
+  /* HSE activation.*/
+  RCC->CR |= RCC_CR_HSEON;
+  while ((RCC->CR & RCC_CR_HSERDY) == 0)
+    ;                           /* Waits until HSE is stable.               */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                           /* Waits until LSI is stable.               */
+#endif
+
+#if STM32_LSE_ENABLED
+  /* LSE activation, have to unlock the register.*/
+  if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
+    PWR->CR |= PWR_CR_DBP;
+    RCC->CSR |= RCC_CSR_LSEON;
+    PWR->CR &= ~PWR_CR_DBP;
+  }
+  while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
+    ;                           /* Waits until LSE is stable.               */
+#endif
+
+#if STM32_ACTIVATE_PLL
+  /* PLL activation.*/
+  RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                           /* Waits until PLL is stable.               */
+#endif
+
+  /* Other clock-related settings (dividers, MCO etc).*/
+  RCC->CR   |= STM32_RTCPRE;
+  RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
+               STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+  RCC->CSR  |= STM32_RTCSEL;
+
+  /* Flash setup and final clock selection.*/
+#if defined(STM32_FLASHBITS1)
+  FLASH->ACR = STM32_FLASHBITS1;
+#endif
+#if defined(STM32_FLASHBITS2)
+  FLASH->ACR = STM32_FLASHBITS2;
+#endif
+
+  /* Switching to the configured clock source if it is different from MSI.*/
+#if (STM32_SW != STM32_SW_MSI)
+  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;
+#endif
+#endif /* STM32_NO_INIT */
+
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+}
+#else
+void stm32_clock_init(void) {}
+#endif
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.h b/os/hal/ports/STM32/STM32L1xx/hal_lld.h
new file mode 100644
index 000000000..0a81016f9
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.h
@@ -0,0 +1,836 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32L1xx/hal_lld.h
+ * @brief   STM32L1xx HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - STM32_LSECLK.
+ *          - STM32_HSECLK.
+ *          - STM32_HSE_BYPASS (optionally).
+ *          .
+ *          One of the following macros must also be defined:
+ *          - STM32L1XX_MD for Ultra Low Power Medium-density devices.
+ *          - STM32L1XX_MDP for Ultra Low Power Medium-density Plus devices.
+ *          - STM32L1XX_HD for Ultra Low Power High-density devices.
+ *          .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+#if defined(STM32L1XX_MD) || defined(__DOXYGEN__)
+#define PLATFORM_NAME           "STM32L1xx Ultra Low Power Medium Density"
+#define STM32L1XX
+
+#elif defined(STM32L1XX_MDP)
+#define PLATFORM_NAME           "STM32L1xx Ultra Low Power Medium Density Plus"
+#define STM32L1XX
+
+#elif defined(STM32L1XX_HD)
+#define PLATFORM_NAME           "STM32L1xx Ultra Low Power High Density"
+#define STM32L1XX
+
+#else
+#error "STM32L1xx device not specified"
+#endif
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK            16000000    /**< High speed internal clock. */
+#define STM32_LSICLK            38000       /**< Low speed internal clock.  */
+/** @} */
+
+/**
+ * @name    PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_VOS_MASK          (3 << 11)   /**< Core voltage mask.         */
+#define STM32_VOS_1P8           (1 << 11)   /**< Core voltage 1.8 Volts.    */
+#define STM32_VOS_1P5           (2 << 11)   /**< Core voltage 1.5 Volts.    */
+#define STM32_VOS_1P2           (3 << 11)   /**< Core voltage 1.2 Volts.    */
+
+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
+/** @} */
+
+/**
+ * @name    RCC_CR register bits definitions
+ * @{
+ */
+#define STM32_RTCPRE_MASK       (3 << 29)   /**< RTCPRE mask.               */
+#define STM32_RTCPRE_DIV2       (0 << 29)   /**< HSE divided by 2.          */
+#define STM32_RTCPRE_DIV4       (1 << 29)   /**< HSE divided by 4.          */
+#define STM32_RTCPRE_DIV8       (2 << 29)   /**< HSE divided by 2.          */
+#define STM32_RTCPRE_DIV16      (3 << 29)   /**< HSE divided by 16.         */
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_MSI            (0 << 0)    /**< SYSCLK source is MSI.      */
+#define STM32_SW_HSI            (1 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (2 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (3 << 0)    /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
+#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
+#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
+#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
+#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
+
+#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
+
+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
+#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
+
+#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_SYSCLK     (1 << 24)   /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (2 << 24)   /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_MSI        (3 << 24)   /**< MSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (4 << 24)   /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLL        (5 << 24)   /**< PLL clock on MCO pin.      */
+#define STM32_MCOSEL_LSI        (6 << 24)   /**< LSI clock on MCO pin.      */
+#define STM32_MCOSEL_LSE        (7 << 24)   /**< LSE clock on MCO pin.      */
+
+#define STM32_MCOPRE_DIV1       (0 << 28)   /**< MCO divided by 1.          */
+#define STM32_MCOPRE_DIV2       (1 << 28)   /**< MCO divided by 1.          */
+#define STM32_MCOPRE_DIV4       (2 << 28)   /**< MCO divided by 1.          */
+#define STM32_MCOPRE_DIV8       (3 << 28)   /**< MCO divided by 1.          */
+#define STM32_MCOPRE_DIV16      (4 << 28)   /**< MCO divided by 1.          */
+/** @} */
+
+/**
+ * @name    RCC_ICSCR register bits definitions
+ * @{
+ */
+#define STM32_MSIRANGE_MASK     (7 << 13)   /**< MSIRANGE field mask.       */
+#define STM32_MSIRANGE_64K      (0 << 13)   /**< 64kHz nominal.             */
+#define STM32_MSIRANGE_128K     (1 << 13)   /**< 128kHz nominal.            */
+#define STM32_MSIRANGE_256K     (2 << 13)   /**< 256kHz nominal.            */
+#define STM32_MSIRANGE_512K     (3 << 13)   /**< 512kHz nominal.            */
+#define STM32_MSIRANGE_1M       (4 << 13)   /**< 1MHz nominal.              */
+#define STM32_MSIRANGE_2M       (5 << 13)   /**< 2MHz nominal.              */
+#define STM32_MSIRANGE_4M       (6 << 13)   /**< 4MHz nominal               */
+/** @} */
+
+/**
+ * @name    RCC_CSR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 16)   /**< RTC source mask.           */
+#define STM32_RTCSEL_NOCLOCK    (0 << 16)   /**< No RTC source.             */
+#define STM32_RTCSEL_LSE        (1 << 16)   /**< RTC source is LSE.         */
+#define STM32_RTCSEL_LSI        (2 << 16)   /**< RTC source is LSI.         */
+#define STM32_RTCSEL_HSEDIV     (3 << 16)   /**< RTC source is HSE divided. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT               FALSE
+#endif
+
+/**
+ * @brief   Core voltage selection.
+ * @note    This setting affects all the performance and clock related
+ *          settings, the maximum performance is only obtainable selecting
+ *          the maximum voltage.
+ */
+#if !defined(STM32_VOS) || defined(__DOXYGEN__)
+#define STM32_VOS                   STM32_VOS_1P8
+#endif
+
+/**
+ * @brief   Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE            FALSE
+#endif
+
+/**
+ * @brief   Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                   STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief   Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED           FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED           FALSE
+#endif
+
+/**
+ * @brief   ADC clock setting.
+ */
+#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_ADC_CLOCK_ENABLED     TRUE
+#endif
+
+/**
+ * @brief   USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_ENABLED     TRUE
+#endif
+
+/**
+ * @brief   MSI frequency setting.
+ */
+#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
+#define STM32_MSIRANGE              STM32_MSIRANGE_2M
+#endif
+
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 32MHz system clock from
+ *          the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                    STM32_SW_PLL
+#endif
+
+/**
+ * @brief   Clock source for the PLL.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 32MHz system clock from
+ *          the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                STM32_PLLSRC_HSI
+#endif
+
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.
+ * @note    The default value is calculated for a 32MHz system clock from
+ *          the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE          6
+#endif
+
+/**
+ * @brief   PLL divider value.
+ * @note    The allowed values are 2, 3, 4.
+ * @note    The default value is calculated for a 32MHz system clock from
+ *          the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLDIV_VALUE          3
+#endif
+
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 32MHz system clock from
+ *          the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                  STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1                 STM32_PPRE1_DIV1
+#endif
+
+/**
+ * @brief   APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2                 STM32_PPRE2_DIV1
+#endif
+
+/**
+ * @brief   MCO clock source.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief   MCO divider setting.
+ */
+#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
+#define STM32_MCOPRE                STM32_MCOPRE_DIV1
+#endif
+
+/**
+ * @brief   RTC/LCD clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                STM32_RTCSEL_LSE
+#endif
+
+/**
+ * @brief   HSE divider toward RTC setting.
+ */
+#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
+#define STM32_RTCPRE                STM32_RTCPRE_DIV2
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32L1xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L1xx_MCUCONF not defined"
+#endif
+
+/* Voltage related limits.*/
+#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
+/**
+ * @brief   Maximum HSE clock frequency at current voltage setting.
+ */
+#define STM32_HSECLK_MAX            32000000
+
+/**
+ * @brief   Maximum SYSCLK clock frequency at current voltage setting.
+ */
+#define STM32_SYSCLK_MAX            32000000
+
+/**
+ * @brief   Maximum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MAX            96000000
+
+/**
+ * @brief   Minimum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MIN            6000000
+
+/**
+ * @brief   Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX             32000000
+
+/**
+ * @brief   Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX             32000000
+
+/**
+ * @brief   Maximum frequency not requiring a wait state for flash accesses.
+ */
+#define STM32_0WS_THRESHOLD         16000000
+
+/**
+ * @brief   HSI availability at current voltage settings.
+ */
+#define STM32_HSI_AVAILABLE         TRUE
+
+#elif STM32_VOS == STM32_VOS_1P5
+#define STM32_HSECLK_MAX            16000000
+#define STM32_SYSCLK_MAX            16000000
+#define STM32_PLLVCO_MAX            48000000
+#define STM32_PLLVCO_MIN            6000000
+#define STM32_PCLK1_MAX             16000000
+#define STM32_PCLK2_MAX             16000000
+#define STM32_0WS_THRESHOLD         8000000
+#define STM32_HSI_AVAILABLE         TRUE
+#elif STM32_VOS == STM32_VOS_1P2
+#define STM32_HSECLK_MAX            4000000
+#define STM32_SYSCLK_MAX            4000000
+#define STM32_PLLVCO_MAX            24000000
+#define STM32_PLLVCO_MIN            6000000
+#define STM32_PCLK1_MAX             4000000
+#define STM32_PCLK2_MAX             4000000
+#define STM32_0WS_THRESHOLD         2000000
+#define STM32_HSI_AVAILABLE         FALSE
+#else
+#error "invalid STM32_VOS value specified"
+#endif
+
+/* HSI related checks.*/
+#if STM32_HSI_ENABLED
+#if !STM32_HSI_AVAILABLE
+  #error "impossible to activate HSI under the current voltage settings"
+#endif
+#else /* !STM32_HSI_ENABLED */
+#if STM32_ADC_CLOCK_ENABLED ||                                              \
+    (STM32_SW == STM32_SW_HSI) ||                                           \
+    ((STM32_SW == STM32_SW_PLL) &&                                          \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI)) ||                                 \
+    (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLL) &&                                  \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "required HSI clock is not enabled"
+#endif
+#endif /* !STM32_HSI_ENABLED */
+
+/* HSE related checks.*/
+#if STM32_HSE_ENABLED
+#if STM32_HSECLK == 0
+#error "impossible to activate HSE"
+#endif
+#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"
+#endif
+#else /* !STM32_HSE_ENABLED */
+#if (STM32_SW == STM32_SW_HSE) ||                                           \
+    ((STM32_SW == STM32_SW_PLL) &&                                          \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE)) ||                                 \
+    (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLL) &&                                  \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE)) ||                                 \
+    (STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
+#error "required HSE clock is not enabled"
+#endif
+#endif /* !STM32_HSE_ENABLED */
+
+/* LSI related checks.*/
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+#if STM32_RTCCLK == STM32_LSICLK
+#error "required LSI clock is not enabled"
+#endif
+#endif /* !STM32_LSI_ENABLED */
+
+/* LSE related checks.*/
+#if STM32_LSE_ENABLED
+#if (STM32_LSECLK == 0)
+#error "impossible to activate LSE"
+#endif
+#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
+#error "STM32_LSECLK outside acceptable range (1...1000kHz)"
+#endif
+#else /* !STM32_LSE_ENABLED */
+#if STM32_RTCCLK == STM32_LSECLK
+#error "required LSE clock is not enabled"
+#endif
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL related checks.*/
+#if STM32_USB_CLOCK_ENABLED ||                                              \
+    (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLL) ||                                   \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+
+/**
+ * @brief   PLLMUL field.
+ */
+#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__)
+#define STM32_PLLMUL                (0 << 18)
+#elif STM32_PLLMUL_VALUE == 4
+#define STM32_PLLMUL                (1 << 18)
+#elif STM32_PLLMUL_VALUE == 6
+#define STM32_PLLMUL                (2 << 18)
+#elif STM32_PLLMUL_VALUE == 8
+#define STM32_PLLMUL                (3 << 18)
+#elif STM32_PLLMUL_VALUE == 12
+#define STM32_PLLMUL                (4 << 18)
+#elif STM32_PLLMUL_VALUE == 16
+#define STM32_PLLMUL                (5 << 18)
+#elif STM32_PLLMUL_VALUE == 24
+#define STM32_PLLMUL                (6 << 18)
+#elif STM32_PLLMUL_VALUE == 32
+#define STM32_PLLMUL                (7 << 18)
+#elif STM32_PLLMUL_VALUE == 48
+#define STM32_PLLMUL                (8 << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLLDIV field.
+ */
+#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLDIV                (1 << 22)
+#elif STM32_PLLDIV_VALUE == 3
+#define STM32_PLLDIV                (2 << 22)
+#elif STM32_PLLDIV_VALUE == 4
+#define STM32_PLLDIV                (3 << 22)
+#else
+#error "invalid STM32_PLLDIV_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN              STM32_HSECLK
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              STM32_HSICLK
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000)
+#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)"
+#endif
+
+/**
+ * @brief   PLL VCO frequency.
+ */
+#define STM32_PLLVCO                (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLVCO / STM32_PLLDIV_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000)
+#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)"
+#endif
+
+/**
+ * @brief   MSI frequency.
+ * @note    Values are taken from the STM8Lxx datasheet.
+ */
+#if STM32_MSIRANGE == STM32_MSIRANGE_64K
+#define STM32_MSICLK                65500
+#elif STM32_MSIRANGE == STM32_MSIRANGE_128K
+#define STM32_MSICLK                131000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_256K
+#define STM32_MSICLK                262000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_512K
+#define STM32_MSICLK                524000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
+#define STM32_MSICLK                1050000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
+#define STM32_MSICLK                2100000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
+#define STM32_MSICLK                4200000
+#else
+#error "invalid STM32_MSIRANGE value specified"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+#define STM32_SYSCLK                2100000
+#elif (STM32_SW == STM32_SW_MSI)
+#define STM32_SYSCLK                STM32_MSICLK
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#elif (STM32_SW == STM32_SW_PLL)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief   MCO divider clock.
+ */
+#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_MCODIVCLK             0
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI
+#define STM32_MCODIVCLK             STM32_HSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_MSI
+#define STM32_MCODIVCLK             STM32_MSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSE
+#define STM32_MCODIVCLK             STM32_HSECLK
+#elif STM32_MCOSEL == STM32_MCOSEL_PLL
+#define STM32_MCODIVCLK             STM32_PLLCLKOUT
+#elif STM32_MCOSEL == STM32_MCOSEL_LSI
+#define STM32_MCODIVCLK             STM32_LSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_LSE
+#define STM32_MCODIVCLK             STM32_LSECLK
+#else
+#error "invalid STM32_MCOSEL value specified"
+#endif
+
+/**
+ * @brief   MCO output pin clock.
+ */
+#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCOCLK                STM32_MCODIVCLK
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
+#define STM32_MCOCLK                (STM32_MCODIVCLK / 2)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
+#define STM32_MCOCLK                (STM32_MCODIVCLK / 4)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
+#define STM32_MCOCLK                (STM32_MCODIVCLK / 8)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
+#define STM32_MCOCLK                (STM32_MCODIVCLK / 16)
+#else
+#error "invalid STM32_MCOPRE value specified"
+#endif
+
+/**
+ * @brief   HSE divider toward RTC clock.
+ */
+#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK             (STM32_HSECLK / 2)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK             (STM32_HSECLK / 4)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK             (STM32_HSECLK / 8)
+#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK             (STM32_HSECLK / 16)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief   RTC/LCD clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                  0
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+#define STM32_RTCCLK                  STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                  STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                  STM32_HSEDIVCLK
+#else
+#error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief   ADC frequency.
+ */
+#define STM32_ADCCLK                STM32_HSICLK
+
+/**
+ * @brief   USB frequency.
+ */
+#define STM32_USBCLK                (STM32_PLLVCO / 2)
+
+/**
+ * @brief   Timers 2, 3, 4, 6, 7 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief   Timers 9, 10, 11 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS1            0x00000000
+#else
+#define STM32_FLASHBITS1            0x00000004
+#define STM32_FLASHBITS2            0x00000007
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/ports/STM32/STM32L1xx/platform.dox
index 879b164c9..879b164c9 100644
--- a/os/hal/platforms/STM32L1xx/platform.dox
+++ b/os/hal/ports/STM32/STM32L1xx/platform.dox
diff --git a/os/hal/ports/STM32/STM32L1xx/platform.mk b/os/hal/ports/STM32/STM32L1xx/platform.mk
new file mode 100644
index 000000000..adf6de40f
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/platform.mk
@@ -0,0 +1,28 @@
+# List of all the STM32L1xx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32L1xx/stm32_dma.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32L1xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32L1xx/adc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/ext_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
+ 			  ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32L1xx \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1
diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_dma.c b/os/hal/ports/STM32/STM32L1xx/stm32_dma.c
new file mode 100644
index 000000000..46faae429
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_dma.c
@@ -0,0 +1,343 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32L1xx/stm32_dma.c
+ * @brief   DMA helper driver code.
+ *
+ * @addtogroup STM32L1xx_DMA
+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a
+ *          shared resource, this driver allows to allocate and free DMA
+ *          streams at runtime in order to allow all the other device
+ *          drivers to coordinate the access to the resource.
+ * @note    The DMA ISR handlers are all declared into this module because
+ *          sharing, the various device drivers can associate a callback to
+ *          ISRs when allocating streams.
+ * @{
+ */
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA1_STREAMS_MASK     0x0000007F
+
+/**
+ * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA2_STREAMS_MASK     0x00000F80
+
+/**
+ * @brief   Post-reset value of the stream CCR register.
+ */
+#define STM32_DMA_CCR_RESET_VALUE   0x00000000
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ *          identifier and the involved physical registers.
+ * @note    Don't use this array directly, use the appropriate wrapper macros
+ *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
+ */
+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
+  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
+  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
+  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
+  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
+  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
+  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
+  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}
+};
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA ISR redirector type.
+ */
+typedef struct {
+  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
+  void                  *dma_param;     /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
+/**
+ * @brief   Mask of the allocated streams.
+ */
+static uint32_t dma_streams_mask;
+
+/**
+ * @brief   DMA IRQ redirectors.
+ */
+static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA1 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector6C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 0;
+  if (dma_isr_redir[0].dma_func)
+    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 4;
+  if (dma_isr_redir[1].dma_func)
+    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector74) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 8;
+  if (dma_isr_redir[2].dma_func)
+    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector78) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 12;
+  if (dma_isr_redir[3].dma_func)
+    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector7C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 16;
+  if (dma_isr_redir[4].dma_func)
+    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 6 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector80) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 20;
+  if (dma_isr_redir[5].dma_func)
+    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 7 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector84) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 24;
+  if (dma_isr_redir[6].dma_func)
+    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+  int i;
+
+  dma_streams_mask = 0;
+  for (i = 0; i < STM32_DMA_STREAMS; i++) {
+    _stm32_dma_streams[i].channel->CCR = 0;
+    dma_isr_redir[i].dma_func = NULL;
+  }
+  DMA1->IFCR = 0xFFFFFFFF;
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ * @pre     The stream must not be already in use or an error is returned.
+ * @post    The stream is allocated and the default ISR handler redirected
+ *          to the specified function.
+ * @post    The stream ISR vector is enabled and its priority configured.
+ * @post    The stream must be freed using @p dmaStreamRelease() before it can
+ *          be reused with another peripheral.
+ * @post    The stream is in its post-reset state.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] priority  IRQ priority mask for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              The operation status.
+ * @retval FALSE        no error, stream taken.
+ * @retval TRUE         error, stream already taken.
+ *
+ * @special
+ */
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                       uint32_t priority,
+                       stm32_dmaisr_t func,
+                       void *param) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Checks if the stream is already taken.*/
+  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
+    return TRUE;
+
+  /* Marks the stream as allocated.*/
+  dma_isr_redir[dmastp->selfindex].dma_func  = func;
+  dma_isr_redir[dmastp->selfindex].dma_param = param;
+  dma_streams_mask |= (1 << dmastp->selfindex);
+
+  /* Enabling DMA clocks required by the current streams set.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
+    rccEnableDMA1(FALSE);
+
+  /* Putting the stream in a safe state.*/
+  dmaStreamDisable(dmastp);
+  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
+
+  /* Enables the associated IRQ vector if a callback is defined.*/
+  if (func != NULL)
+    nvicEnableVector(dmastp->vector, priority);
+
+  return FALSE;
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    The stream is again available.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Check if the streams is not taken.*/
+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+                "not allocated");
+
+  /* Disables the associated IRQ vector.*/
+  nvicDisableVector(dmastp->vector);
+
+  /* Marks the stream as not allocated.*/
+  dma_streams_mask &= ~(1 << dmastp->selfindex);
+
+  /* Shutting down clocks that are no more required, if any.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
+    rccDisableDMA1(FALSE);
+}
+
+#endif /* STM32_DMA_REQUIRED */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_dma.h b/os/hal/ports/STM32/STM32L1xx/stm32_dma.h
new file mode 100644
index 000000000..3af798d0b
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_dma.h
@@ -0,0 +1,396 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32L1xx/stm32_dma.h
+ * @brief   DMA helper driver header.
+ * @note    This file requires definitions from the ST header file stm32l1xx.h.
+ * @note    This driver uses the new naming convention used for the STM32F2xx
+ *          so the "DMA channels" are referred as "DMA streams".
+ *
+ * @addtogroup STM32L1xx_DMA
+ * @{
+ */
+
+#ifndef _STM32_DMA_H_
+#define _STM32_DMA_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Total number of DMA streams.
+ * @note    This is the total number of streams among all the DMA units.
+ */
+#define STM32_DMA_STREAMS           7
+
+/**
+ * @brief   Mask of the ISR bits passed to the DMA callback functions.
+ */
+#define STM32_DMA_ISR_MASK          0x0F
+
+/**
+ * @brief   Returns the channel associated to the specified stream.
+ *
+ * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
+ * @param[in] c         a stream/channel association word, one channel per
+ *                      nibble, not associated channels must be set to 0xF
+ * @return              Always zero, in this platform there is no dynamic
+ *                      association between streams and channels.
+ */
+#define STM32_DMA_GETCHANNEL(n, c)  0
+
+/**
+ * @brief   Checks if a DMA priority is within the valid range.
+ * @param[in] prio      DMA priority
+ *
+ * @retval              The check result.
+ * @retval FALSE        invalid DMA priority.
+ * @retval TRUE         correct DMA priority.
+ */
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+
+/**
+ * @brief   Returns an unique numeric identifier for a DMA stream.
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              An unique numeric stream identifier.
+ */
+#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1)
+
+/**
+ * @brief   Returns a DMA stream identifier mask.
+ *
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              A DMA stream identifier mask.
+ */
+#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
+  (1 << STM32_DMA_STREAM_ID(dma, stream))
+
+/**
+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.
+ * @param[in] id        the stream numeric identifier
+ * @param[in] mask      the stream numeric identifiers mask
+ *
+ * @retval              The check result.
+ * @retval FALSE        id does not belong to the mask.
+ * @retval TRUE         id belongs to the mask.
+ */
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+
+/**
+ * @name    DMA streams identifiers
+ * @{
+ */
+/**
+ * @brief   Returns a pointer to a stm32_dma_stream_t structure.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @return              A pointer to the stm32_dma_stream_t constant structure
+ *                      associated to the DMA stream.
+ */
+#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
+
+#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
+#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
+#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
+#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
+#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
+#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
+#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
+/** @} */
+
+/**
+ * @name    CR register constants common to all DMA types
+ * @{
+ */
+#define STM32_DMA_CR_EN             DMA_CCR1_EN
+#define STM32_DMA_CR_TEIE           DMA_CCR1_TEIE
+#define STM32_DMA_CR_HTIE           DMA_CCR1_HTIE
+#define STM32_DMA_CR_TCIE           DMA_CCR1_TCIE
+#define STM32_DMA_CR_DIR_MASK       (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM)
+#define STM32_DMA_CR_DIR_P2M        0
+#define STM32_DMA_CR_DIR_M2P        DMA_CCR1_DIR
+#define STM32_DMA_CR_DIR_M2M        DMA_CCR1_MEM2MEM
+#define STM32_DMA_CR_CIRC           DMA_CCR1_CIRC
+#define STM32_DMA_CR_PINC           DMA_CCR1_PINC
+#define STM32_DMA_CR_MINC           DMA_CCR1_MINC
+#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR1_PSIZE
+#define STM32_DMA_CR_PSIZE_BYTE     0
+#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR1_PSIZE_0
+#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR1_PSIZE_1
+#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR1_MSIZE
+#define STM32_DMA_CR_MSIZE_BYTE     0
+#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR1_MSIZE_0
+#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR1_MSIZE_1
+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
+                                     STM32_DMA_CR_MSIZE_MASK)
+#define STM32_DMA_CR_PL_MASK        DMA_CCR1_PL
+#define STM32_DMA_CR_PL(n)          ((n) << 12)
+/** @} */
+
+/**
+ * @name    CR register constants only found in enhanced DMA
+ * @{
+ */
+#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
+/** @} */
+
+/**
+ * @name    Status flags passed to the ISR callbacks
+ * @{
+ */
+#define STM32_DMA_ISR_FEIF          0
+#define STM32_DMA_ISR_DMEIF         0
+#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
+#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
+#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA stream descriptor structure.
+ */
+typedef struct {
+  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
+  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
+  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
+                                             register.                      */
+  uint8_t               selfindex;      /**< @brief Index to self in array. */
+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
+} stm32_dma_stream_t;
+
+/**
+ * @brief   STM32 DMA ISR function type.
+ *
+ * @param[in] p         parameter for the registered function
+ * @param[in] flags     pre-shifted content of the ISR register, the bits
+ *                      are aligned to bit zero
+ */
+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Associates a peripheral data register to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CPAR register
+ *
+ * @special
+ */
+#define dmaStreamSetPeripheral(dmastp, addr) {                              \
+  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Associates a memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CMAR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory0(dmastp, addr) {                                 \
+  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Sets the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] size      value to be written in the CNDTR register
+ *
+ * @special
+ */
+#define dmaStreamSetTransactionSize(dmastp, size) {                         \
+  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
+}
+
+/**
+ * @brief   Returns the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @return              The number of transfers to be performed.
+ *
+ * @special
+ */
+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
+
+/**
+ * @brief   Programs the stream mode settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register
+ *
+ * @special
+ */
+#define dmaStreamSetMode(dmastp, mode) {                                    \
+  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
+}
+
+/**
+ * @brief   DMA stream enable.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamEnable(dmastp) {                                           \
+  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
+}
+
+/**
+ * @brief   DMA stream disable.
+ * @details The function disables the specified stream and then clears any
+ *          pending interrupt.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @note    Interrupts enabling flags are set to zero after this call, see
+ *          bug 3607518.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamDisable(dmastp) {                                          \
+  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
+                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
+  dmaStreamClearInterrupt(dmastp);                                          \
+}
+
+/**
+ * @brief   DMA stream interrupt sources clear.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamClearInterrupt(dmastp) {                                   \
+  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
+}
+
+/**
+ * @brief   Starts a memory to memory operation using the specified stream.
+ * @note    The default transfer data mode is "byte to byte" but it can be
+ *          changed by specifying extra options in the @p mode parameter.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register, this value
+ *                      is implicitly ORed with:
+ *                      - @p STM32_DMA_CR_MINC
+ *                      - @p STM32_DMA_CR_PINC
+ *                      - @p STM32_DMA_CR_DIR_M2M
+ *                      - @p STM32_DMA_CR_EN
+ *                      .
+ * @param[in] src       source address
+ * @param[in] dst       destination address
+ * @param[in] n         number of data units to copy
+ */
+#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
+  dmaStreamSetPeripheral(dmastp, src);                                      \
+  dmaStreamSetMemory0(dmastp, dst);                                         \
+  dmaStreamSetTransactionSize(dmastp, n);                                   \
+  dmaStreamSetMode(dmastp, (mode) |                                         \
+                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
+                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
+}
+
+/**
+ * @brief   Polled wait for DMA transfer end.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ */
+#define dmaWaitCompletion(dmastp) {                                         \
+  while ((dmastp)->channel->CNDTR > 0)                                      \
+    ;                                                                       \
+  dmaStreamDisable(dmastp);                                                 \
+}
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dmaInit(void);
+  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                         uint32_t priority,
+                         stm32_dmaisr_t func,
+                         void *param);
+  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_DMA_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_isr.h b/os/hal/ports/STM32/STM32L1xx/stm32_isr.h
new file mode 100644
index 000000000..f7f2d8d63
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_isr.h
@@ -0,0 +1,92 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32L1xx/stm32_isr.h
+ * @brief   ISR remapper driver header.
+ *
+ * @addtogroup STM32L1xx_ISR
+ * @{
+ */
+
+#ifndef _STM32_ISR_H_
+#define _STM32_ISR_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    ISR names and numbers remapping
+ * @{
+ */
+/*
+ * TIM units.
+ */
+#define STM32_TIM2_HANDLER          VectorB0
+#define STM32_TIM3_HANDLER          VectorB4
+#define STM32_TIM4_HANDLER          VectorB8
+#define STM32_TIM9_HANDLER          VectorA4
+
+#define STM32_TIM2_NUMBER           28
+#define STM32_TIM3_NUMBER           29
+#define STM32_TIM4_NUMBER           30
+#define STM32_TIM9_NUMBER           25
+
+/*
+ * USART units.
+ */
+#define STM32_USART1_HANDLER        VectorD4
+#define STM32_USART2_HANDLER        VectorD8
+#define STM32_USART3_HANDLER        VectorDC
+
+#define STM32_USART1_NUMBER         37
+#define STM32_USART2_NUMBER         38
+#define STM32_USART3_NUMBER         39
+
+/*
+ * USB units.
+ */
+#define STM32_USB1_HP_HANDLER       Vector8C
+#define STM32_USB1_LP_HANDLER       Vector30
+
+#define STM32_USB1_HP_NUMBER        19
+#define STM32_USB1_LP_NUMBER        20
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#endif /* _STM32_ISR_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
index 90cbd8fbe..90cbd8fbe 100644
--- a/os/hal/platforms/STM32L1xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
new file mode 100644
index 000000000..ab679e19f
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
@@ -0,0 +1,178 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32L1xx/stm32_registry.h
+ * @brief   STM32L1xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    STM32L1xx capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      FALSE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               0
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             23
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     FALSE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     TRUE
+#define STM32_HAS_GPIOI                     FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            FALSE
+#define STM32_RTC_IS_CALENDAR               TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      TRUE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                FALSE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM9                      TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM10                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM11                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM1                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM15                     FALSE
+#define STM32_HAS_TIM16                     FALSE
+#define STM32_HAS_TIM17                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+/** @} */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/common/ARMCMx/nvic.c b/os/hal/ports/common/ARMCMx/nvic.c
new file mode 100644
index 000000000..b469e7cf1
--- /dev/null
+++ b/os/hal/ports/common/ARMCMx/nvic.c
@@ -0,0 +1,88 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    common/ARMCMx/nvic.c
+ * @brief   Cortex-Mx NVIC support code.
+ *
+ * @addtogroup COMMON_ARMCMx_NVIC
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Sets the priority of an interrupt handler and enables it.
+ *
+ * @param[in] n         the interrupt number
+ * @param[in] prio      the interrupt priority
+ */
+void nvicEnableVector(uint32_t n, uint32_t prio) {
+
+  NVIC->IP[n]        = NVIC_PRIORITY_MASK(prio);
+  NVIC->ICPR[n >> 5] = 1 << (n & 0x1F);
+  NVIC->ISER[n >> 5] = 1 << (n & 0x1F);
+}
+
+/**
+ * @brief   Disables an interrupt handler.
+ *
+ * @param[in] n         the interrupt number
+ */
+void nvicDisableVector(uint32_t n) {
+
+  NVIC->ICER[n >> 5] = 1 << (n & 0x1F);
+  NVIC->IP[n]        = 0;
+}
+
+/**
+ * @brief   Changes the priority of a system handler.
+ *
+ * @param[in] handler   the system handler number
+ * @param[in] prio      the system handler priority
+ */
+void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
+
+  osalDbgCheck(handler <= 12);
+
+  SCB->SHP[handler] = NVIC_PRIORITY_MASK(prio);
+}
+
+/** @} */
diff --git a/os/hal/ports/common/ARMCMx/nvic.h b/os/hal/ports/common/ARMCMx/nvic.h
new file mode 100644
index 000000000..807bf230c
--- /dev/null
+++ b/os/hal/ports/common/ARMCMx/nvic.h
@@ -0,0 +1,87 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    common/ARMCMx/nvic.h
+ * @brief   Cortex-Mx NVIC support macros and structures.
+ *
+ * @addtogroup COMMON_ARMCMx_NVIC
+ * @{
+ */
+
+#ifndef _NVIC_H_
+#define _NVIC_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name System vectors numbers
+ * @{
+ */
+#define HANDLER_MEM_MANAGE      0       /**< MEM MANAGE vector id.          */
+#define HANDLER_BUS_FAULT       1       /**< BUS FAULT vector id.           */
+#define HANDLER_USAGE_FAULT     2       /**< USAGE FAULT vector id.         */
+#define HANDLER_RESERVED_3      3
+#define HANDLER_RESERVED_4      4
+#define HANDLER_RESERVED_5      5
+#define HANDLER_RESERVED_6      6
+#define HANDLER_SVCALL          7       /**< SVCALL vector id.              */
+#define HANDLER_DEBUG_MONITOR   8       /**< DEBUG MONITOR vector id.       */
+#define HANDLER_RESERVED_9      9
+#define HANDLER_PENDSV          10      /**< PENDSV vector id.              */
+#define HANDLER_SYSTICK         11      /**< SYS TCK vector id.             */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Priority level to priority mask conversion macro.
+ */
+#define NVIC_PRIORITY_MASK(prio) ((prio) << (8 - __NVIC_PRIO_BITS))
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void nvicEnableVector(uint32_t n, uint32_t prio);
+  void nvicDisableVector(uint32_t n);
+  void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _NVIC_H_ */
+
+/** @} */
diff --git a/os/hal/src/adc.c b/os/hal/src/adc.c
index d0e814ae2..e6d8d8075 100644
--- a/os/hal/src/adc.c
+++ b/os/hal/src/adc.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_ADC || defined(__DOXYGEN__)
@@ -81,11 +80,7 @@ void adcObjectInit(ADCDriver *adcp) {
   adcp->thread   = NULL;
 #endif /* ADC_USE_WAIT */
 #if ADC_USE_MUTUAL_EXCLUSION
-#if CH_USE_MUTEXES
-  chMtxInit(&adcp->mutex);
-#else
-  chSemInit(&adcp->semaphore, 1);
-#endif
+  osalMutexObjectInit(&adcp->mutex);
 #endif /* ADC_USE_MUTUAL_EXCLUSION */
 #if defined(ADC_DRIVER_EXT_INIT_HOOK)
   ADC_DRIVER_EXT_INIT_HOOK(adcp);
@@ -103,15 +98,15 @@ void adcObjectInit(ADCDriver *adcp) {
  */
 void adcStart(ADCDriver *adcp, const ADCConfig *config) {
 
-  chDbgCheck(adcp != NULL, "adcStart");
+  osalDbgCheck(adcp != NULL);
 
-  chSysLock();
-  chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY),
-              "adcStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY),
+                "invalid state");
   adcp->config = config;
   adc_lld_start(adcp);
   adcp->state = ADC_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -123,14 +118,14 @@ void adcStart(ADCDriver *adcp, const ADCConfig *config) {
  */
 void adcStop(ADCDriver *adcp) {
 
-  chDbgCheck(adcp != NULL, "adcStop");
+  osalDbgCheck(adcp != NULL);
 
-  chSysLock();
-  chDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY),
-              "adcStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((adcp->state == ADC_STOP) || (adcp->state == ADC_READY),
+                "invalid state");
   adc_lld_stop(adcp);
   adcp->state = ADC_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -154,9 +149,9 @@ void adcStartConversion(ADCDriver *adcp,
                         adcsample_t *samples,
                         size_t depth) {
 
-  chSysLock();
+  osalSysLock();
   adcStartConversionI(adcp, grpp, samples, depth);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -182,14 +177,13 @@ void adcStartConversionI(ADCDriver *adcp,
                          adcsample_t *samples,
                          size_t depth) {
 
-  chDbgCheckClassI();
-  chDbgCheck((adcp != NULL) && (grpp != NULL) && (samples != NULL) &&
-             ((depth == 1) || ((depth & 1) == 0)),
-             "adcStartConversionI");
-  chDbgAssert((adcp->state == ADC_READY) ||
-              (adcp->state == ADC_COMPLETE) ||
-              (adcp->state == ADC_ERROR),
-              "adcStartConversionI(), #1", "not ready");
+  osalDbgCheckClassI();
+  osalDbgCheck((adcp != NULL) && (grpp != NULL) && (samples != NULL) &&
+               ((depth == 1) || ((depth & 1) == 0)));
+  osalDbgAssert((adcp->state == ADC_READY) ||
+                (adcp->state == ADC_COMPLETE) ||
+                (adcp->state == ADC_ERROR),
+                "not ready");
 
   adcp->samples  = samples;
   adcp->depth    = depth;
@@ -210,19 +204,18 @@ void adcStartConversionI(ADCDriver *adcp,
  */
 void adcStopConversion(ADCDriver *adcp) {
 
-  chDbgCheck(adcp != NULL, "adcStopConversion");
+  osalDbgCheck(adcp != NULL);
 
-  chSysLock();
-  chDbgAssert((adcp->state == ADC_READY) ||
-              (adcp->state == ADC_ACTIVE),
-              "adcStopConversion(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((adcp->state == ADC_READY) || (adcp->state == ADC_ACTIVE),
+                "invalid state");
   if (adcp->state != ADC_READY) {
     adc_lld_stop_conversion(adcp);
     adcp->grpp  = NULL;
     adcp->state = ADC_READY;
     _adc_reset_s(adcp);
   }
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -237,12 +230,12 @@ void adcStopConversion(ADCDriver *adcp) {
  */
 void adcStopConversionI(ADCDriver *adcp) {
 
-  chDbgCheckClassI();
-  chDbgCheck(adcp != NULL, "adcStopConversionI");
-  chDbgAssert((adcp->state == ADC_READY) ||
-              (adcp->state == ADC_ACTIVE) ||
-              (adcp->state == ADC_COMPLETE),
-              "adcStopConversionI(), #1", "invalid state");
+  osalDbgCheckClassI();
+  osalDbgCheck(adcp != NULL);
+  osalDbgAssert((adcp->state == ADC_READY) ||
+                (adcp->state == ADC_ACTIVE) ||
+                (adcp->state == ADC_COMPLETE),
+                "invalid state");
 
   if (adcp->state != ADC_READY) {
     adc_lld_stop_conversion(adcp);
@@ -282,13 +275,11 @@ msg_t adcConvert(ADCDriver *adcp,
                  size_t depth) {
   msg_t msg;
 
-  chSysLock();
-  chDbgAssert(adcp->thread == NULL, "adcConvert(), #1", "already waiting");
+  osalSysLock();
+  osalDbgAssert(adcp->thread == NULL, "already waiting");
   adcStartConversionI(adcp, grpp, samples, depth);
-  adcp->thread = chThdSelf();
-  chSchGoSleepS(THD_STATE_SUSPENDED);
-  msg = chThdSelf()->p_u.rdymsg;
-  chSysUnlock();
+  msg = osalThreadSuspendS(&adcp->thread);
+  osalSysUnlock();
   return msg;
 }
 #endif /* ADC_USE_WAIT */
@@ -307,13 +298,9 @@ msg_t adcConvert(ADCDriver *adcp,
  */
 void adcAcquireBus(ADCDriver *adcp) {
 
-  chDbgCheck(adcp != NULL, "adcAcquireBus");
+  osalDbgCheck(adcp != NULL);
 
-#if CH_USE_MUTEXES
-  chMtxLock(&adcp->mutex);
-#elif CH_USE_SEMAPHORES
-  chSemWait(&adcp->semaphore);
-#endif
+  osalMutexLock(&adcp->mutex);
 }
 
 /**
@@ -327,14 +314,9 @@ void adcAcquireBus(ADCDriver *adcp) {
  */
 void adcReleaseBus(ADCDriver *adcp) {
 
-  chDbgCheck(adcp != NULL, "adcReleaseBus");
+  osalDbgCheck(adcp != NULL);
 
-#if CH_USE_MUTEXES
-  (void)adcp;
-  chMtxUnlock();
-#elif CH_USE_SEMAPHORES
-  chSemSignal(&adcp->semaphore);
-#endif
+  osalMutexUnlock(&adcp->mutex);
 }
 #endif /* ADC_USE_MUTUAL_EXCLUSION */
 
diff --git a/os/hal/src/can.c b/os/hal/src/can.c
index 3f1f7588f..92efdf7e7 100644
--- a/os/hal/src/can.c
+++ b/os/hal/src/can.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_CAN || defined(__DOXYGEN__)
@@ -74,14 +73,14 @@ void canObjectInit(CANDriver *canp) {
 
   canp->state    = CAN_STOP;
   canp->config   = NULL;
-  chSemInit(&canp->txsem, 0);
-  chSemInit(&canp->rxsem, 0);
-  chEvtInit(&canp->rxfull_event);
-  chEvtInit(&canp->txempty_event);
-  chEvtInit(&canp->error_event);
+  osalThreadQueueObjectInit(&canp->txqueue);
+  osalThreadQueueObjectInit(&canp->rxqueue);
+  osalEventObjectInit(&canp->rxfull_event);
+  osalEventObjectInit(&canp->txempty_event);
+  osalEventObjectInit(&canp->error_event);
 #if CAN_USE_SLEEP_MODE
-  chEvtInit(&canp->sleep_event);
-  chEvtInit(&canp->wakeup_event);
+  osalEventObjectInit(&canp->sleep_event);
+  osalEventObjectInit(&canp->wakeup_event);
 #endif /* CAN_USE_SLEEP_MODE */
 }
 
@@ -99,21 +98,21 @@ void canObjectInit(CANDriver *canp) {
  */
 void canStart(CANDriver *canp, const CANConfig *config) {
 
-  chDbgCheck(canp != NULL, "canStart");
+  osalDbgCheck(canp != NULL);
 
-  chSysLock();
-  chDbgAssert((canp->state == CAN_STOP) ||
-              (canp->state == CAN_STARTING) ||
-              (canp->state == CAN_READY),
-              "canStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((canp->state == CAN_STOP) ||
+                (canp->state == CAN_STARTING) ||
+                (canp->state == CAN_READY),
+                "invalid state");
   while (canp->state == CAN_STARTING)
-    chThdSleepS(1);
+    osalThreadSleepS(1);
   if (canp->state == CAN_STOP) {
     canp->config = config;
     can_lld_start(canp);
     canp->state = CAN_READY;
   }
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -125,17 +124,17 @@ void canStart(CANDriver *canp, const CANConfig *config) {
  */
 void canStop(CANDriver *canp) {
 
-  chDbgCheck(canp != NULL, "canStop");
+  osalDbgCheck(canp != NULL);
 
-  chSysLock();
-  chDbgAssert((canp->state == CAN_STOP) || (canp->state == CAN_READY),
-              "canStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((canp->state == CAN_STOP) || (canp->state == CAN_READY),
+                "invalid state");
   can_lld_stop(canp);
   canp->state  = CAN_STOP;
-  chSemResetI(&canp->rxsem, 0);
-  chSemResetI(&canp->txsem, 0);
-  chSchRescheduleS();
-  chSysUnlock();
+  osalThreadDequeueAllI(&canp->rxqueue, MSG_RESET);
+  osalThreadDequeueAllI(&canp->txqueue, MSG_RESET);
+  osalOsRescheduleS();
+  osalSysUnlock();
 }
 
 /**
@@ -153,9 +152,9 @@ void canStop(CANDriver *canp) {
  *                      - @a TIME_INFINITE no timeout.
  *                      .
  * @return              The operation result.
- * @retval RDY_OK       the frame has been queued for transmission.
- * @retval RDY_TIMEOUT  The operation has timed out.
- * @retval RDY_RESET    The driver has been stopped while waiting.
+ * @retval MSG_OK       the frame has been queued for transmission.
+ * @retval MSG_TIMEOUT  The operation has timed out.
+ * @retval MSG_RESET    The driver has been stopped while waiting.
  *
  * @api
  */
@@ -164,22 +163,22 @@ msg_t canTransmit(CANDriver *canp,
                   const CANTxFrame *ctfp,
                   systime_t timeout) {
 
-  chDbgCheck((canp != NULL) && (ctfp != NULL) && (mailbox <= CAN_TX_MAILBOXES),
-             "canTransmit");
+  osalDbgCheck((canp != NULL) && (ctfp != NULL) &&
+               (mailbox <= CAN_TX_MAILBOXES));
 
-  chSysLock();
-  chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
-              "canTransmit(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+                "invalid state");
   while ((canp->state == CAN_SLEEP) || !can_lld_is_tx_empty(canp, mailbox)) {
-    msg_t msg = chSemWaitTimeoutS(&canp->txsem, timeout);
-    if (msg != RDY_OK) {
-      chSysUnlock();
+    msg_t msg = osalThreadEnqueueTimeoutS(&canp->txqueue, timeout);
+    if (msg != MSG_OK) {
+      osalSysUnlock();
       return msg;
     }
   }
   can_lld_transmit(canp, mailbox, ctfp);
-  chSysUnlock();
-  return RDY_OK;
+  osalSysUnlock();
+  return MSG_OK;
 }
 
 /**
@@ -198,9 +197,9 @@ msg_t canTransmit(CANDriver *canp,
  *                      - @a TIME_INFINITE no timeout.
  *                      .
  * @return              The operation result.
- * @retval RDY_OK       a frame has been received and placed in the buffer.
- * @retval RDY_TIMEOUT  The operation has timed out.
- * @retval RDY_RESET    The driver has been stopped while waiting.
+ * @retval MSG_OK       a frame has been received and placed in the buffer.
+ * @retval MSG_TIMEOUT  The operation has timed out.
+ * @retval MSG_RESET    The driver has been stopped while waiting.
  *
  * @api
  */
@@ -209,22 +208,22 @@ msg_t canReceive(CANDriver *canp,
                  CANRxFrame *crfp,
                  systime_t timeout) {
 
-  chDbgCheck((canp != NULL) && (crfp != NULL) && (mailbox < CAN_RX_MAILBOXES),
-             "canReceive");
+  osalDbgCheck((canp != NULL) && (crfp != NULL) &&
+               (mailbox < CAN_RX_MAILBOXES));
 
-  chSysLock();
-  chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
-              "canReceive(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+                "invalid state");
   while ((canp->state == CAN_SLEEP) || !can_lld_is_rx_nonempty(canp, mailbox)) {
-    msg_t msg = chSemWaitTimeoutS(&canp->rxsem, timeout);
-    if (msg != RDY_OK) {
-      chSysUnlock();
+    msg_t msg = osalThreadEnqueueTimeoutS(&canp->rxqueue, timeout);
+    if (msg != MSG_OK) {
+      osalSysUnlock();
       return msg;
     }
   }
   can_lld_receive(canp, mailbox, crfp);
-  chSysUnlock();
-  return RDY_OK;
+  osalSysUnlock();
+  return MSG_OK;
 }
 
 #if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
@@ -242,18 +241,18 @@ msg_t canReceive(CANDriver *canp,
  */
 void canSleep(CANDriver *canp) {
 
-  chDbgCheck(canp != NULL, "canSleep");
+  osalDbgCheck(canp != NULL);
 
-  chSysLock();
-  chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
-              "canSleep(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+                "invalid state");
   if (canp->state == CAN_READY) {
     can_lld_sleep(canp);
     canp->state = CAN_SLEEP;
-    chEvtBroadcastI(&canp->sleep_event);
-    chSchRescheduleS();
+    osalEventBroadcastFlagsI(&canp->sleep_event, 0);
+    osalOsRescheduleS();
   }
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -265,18 +264,18 @@ void canSleep(CANDriver *canp) {
  */
 void canWakeup(CANDriver *canp) {
 
-  chDbgCheck(canp != NULL, "canWakeup");
+  osalDbgCheck(canp != NULL);
 
-  chSysLock();
-  chDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
-              "canWakeup(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((canp->state == CAN_READY) || (canp->state == CAN_SLEEP),
+                "invalid state");
   if (canp->state == CAN_SLEEP) {
     can_lld_wakeup(canp);
     canp->state = CAN_READY;
-    chEvtBroadcastI(&canp->wakeup_event);
-    chSchRescheduleS();
+    osalEventBroadcastFlagsI(&canp->wakeup_event, 0);
+    osalOsRescheduleS();
   }
-  chSysUnlock();
+  osalSysUnlock();
 }
 #endif /* CAN_USE_SLEEP_MODE */
 
diff --git a/os/hal/src/dac.c b/os/hal/src/dac.c
index 3ab09f27c..42521c107 100644
--- a/os/hal/src/dac.c
+++ b/os/hal/src/dac.c
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_DAC || defined(__DOXYGEN__)
@@ -78,11 +77,7 @@ void dacObjectInit(DACDriver *dacp) {
   dacp->thread = NULL;
 #endif /* DAC_USE_WAIT */
 #if DAC_USE_MUTUAL_EXCLUSION
-#if CH_USE_MUTEXES
-  chMtxInit(&dacp->mutex);
-#else
-  chSemInit(&dacp->semaphore, 1);
-#endif
+  osalMutexObjectInit(&dacp->mutex);
 #endif /* DAC_USE_MUTUAL_EXCLUSION */
 #if defined(DAC_DRIVER_EXT_INIT_HOOK)
   DAC_DRIVER_EXT_INIT_HOOK(dacp);
@@ -99,15 +94,18 @@ void dacObjectInit(DACDriver *dacp) {
  */
 void dacStart(DACDriver *dacp, const DACConfig *config) {
 
-  chDbgCheck((dacp != NULL) && (config != NULL), "dacStart");
+  osalDbgCheck((dacp != NULL) && (config != NULL));
+
+  osalSysLock();
+
+  osalDbgAssert((dacp->state == DAC_STOP) || (dacp->state == DAC_READY),
+                "invalid state");
 
-  chSysLock();
-  chDbgAssert((dacp->state == DAC_STOP) || (dacp->state == DAC_READY),
-              "dacStart(), #1", "invalid state");
   dacp->config = config;
   dac_lld_start(dacp);
   dacp->state = DAC_READY;
-  chSysUnlock();
+
+  osalSysUnlock();
 }
 
 /**
@@ -121,14 +119,17 @@ void dacStart(DACDriver *dacp, const DACConfig *config) {
  */
 void dacStop(DACDriver *dacp) {
 
-  chDbgCheck(dacp != NULL, "dacStop");
+  osalDbgCheck(dacp != NULL);
+
+  osalSysLock();
+
+  osalDbgAssert((dacp->state == DAC_STOP) || (dacp->state == DAC_READY),
+                "invalid state");
 
-  chSysLock();
-  chDbgAssert((dacp->state == DAC_STOP) || (dacp->state == DAC_READY),
-              "dacStop(), #1", "invalid state");
   dac_lld_stop(dacp);
   dacp->state = DAC_STOP;
-  chSysUnlock();
+
+  osalSysUnlock();
 }
 
 /**
@@ -152,9 +153,9 @@ void dacStartConversion(DACDriver *dacp,
                         const dacsample_t *samples,
                         size_t depth) {
 
-  chSysLock();
+  osalSysLock();
   dacStartConversionI(dacp, grpp, samples, depth);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -180,14 +181,13 @@ void dacStartConversionI(DACDriver *dacp,
                          const dacsample_t *samples,
                          size_t depth) {
 
-  chDbgCheckClassI();
-  chDbgCheck((dacp != NULL) && (grpp != NULL) && (samples != NULL) &&
-             ((depth == 1) || ((depth & 1) == 0)),
-             "dacStartConversionI");
-  chDbgAssert((dacp->state == DAC_READY) ||
-              (dacp->state == DAC_COMPLETE) ||
-              (dacp->state == DAC_ERROR),
-              "dacStartConversionI(), #1", "not ready");
+  osalDbgCheckClassI();
+  osalDbgCheck((dacp != NULL) && (grpp != NULL) && (samples != NULL) &&
+               ((depth == 1) || ((depth & 1) == 0)));
+  osalDbgAssert((dacp->state == DAC_READY) ||
+                (dacp->state == DAC_COMPLETE) ||
+                (dacp->state == DAC_ERROR),
+                "not ready");
 
   dacp->samples  = samples;
   dacp->depth    = depth;
@@ -208,19 +208,22 @@ void dacStartConversionI(DACDriver *dacp,
  */
 void dacStopConversion(DACDriver *dacp) {
 
-  chDbgCheck(dacp != NULL, "dacStopConversion");
+  osalDbgCheck(dacp != NULL);
+
+  osalSysLock();
+
+  osalDbgAssert((dacp->state == DAC_READY) ||
+                (dacp->state == DAC_ACTIVE),
+                "invalid state");
 
-  chSysLock();
-  chDbgAssert((dacp->state == DAC_READY) ||
-              (dacp->state == DAC_ACTIVE),
-              "dacStopConversion(), #1", "invalid state");
   if (dacp->state != DAC_READY) {
     dac_lld_stop_conversion(dacp);
     dacp->grpp  = NULL;
     dacp->state = DAC_READY;
     _dac_reset_s(dacp);
   }
-  chSysUnlock();
+
+  osalSysUnlock();
 }
 
 /**
@@ -235,12 +238,12 @@ void dacStopConversion(DACDriver *dacp) {
  */
 void dacStopConversionI(DACDriver *dacp) {
 
-  chDbgCheckClassI();
-  chDbgCheck(dacp != NULL, "dacStopConversionI");
-  chDbgAssert((dacp->state == DAC_READY) ||
-              (dacp->state == DAC_ACTIVE) ||
-              (dacp->state == DAC_COMPLETE),
-              "dacStopConversionI(), #1", "invalid state");
+  osalDbgCheckClassI();
+  osalDbgCheck(dacp != NULL);
+  osalDbgAssert((dacp->state == DAC_READY) ||
+                (dacp->state == DAC_ACTIVE) ||
+                (dacp->state == DAC_COMPLETE),
+                "invalid state");
 
   if (dacp->state != DAC_READY) {
     dac_lld_stop_conversion(dacp);
@@ -265,11 +268,11 @@ void dacStopConversionI(DACDriver *dacp) {
  * @param[in] depth     buffer depth (matrix rows number). The buffer depth
  *                      must be one or an even number.
  * @return              The operation result.
- * @retval RDY_OK       Conversion finished.
- * @retval RDY_RESET    The conversion has been stopped using
+ * @retval MSG_OK       Conversion finished.
+ * @retval MSG_RESET    The conversion has been stopped using
  *                      @p acdStopConversion() or @p acdStopConversionI(),
  *                      the result buffer may contain incorrect data.
- * @retval RDY_TIMEOUT  The conversion has been stopped because an hardware
+ * @retval MSG_TIMEOUT  The conversion has been stopped because an hardware
  *                      error.
  *
  * @api
@@ -280,12 +283,12 @@ msg_t dacConvert(DACDriver *dacp,
                  size_t depth) {
   msg_t msg;
 
-  chSysLock();
-  chDbgAssert(dacp->thread == NULL, "dacConvert(), #1", "already waiting");
+  osalSysLock();
+
   dacStartConversionI(dacp, grpp, samples, depth);
-  _dac_wait_s(dacp);
-  msg = chThdSelf()->p_u.rdymsg;
-  chSysUnlock();
+  msg = osalThreadSuspendS(&dacp->thread);
+
+  osalSysUnlock();
   return msg;
 }
 #endif /* DAC_USE_WAIT */
@@ -304,13 +307,9 @@ msg_t dacConvert(DACDriver *dacp,
  */
 void dacAcquireBus(DACDriver *dacp) {
 
-  chDbgCheck(dacp != NULL, "dacAcquireBus");
-
-#if CH_USE_MUTEXES
-  chMtxLock(&dacp->mutex);
-#elif CH_USE_SEMAPHORES
-  chSemWait(&dacp->semaphore);
-#endif
+  osalDbgCheck(dacp != NULL);
+	
+  osalMutexLock(&dacp->mutex);
 }
 
 /**
@@ -324,14 +323,9 @@ void dacAcquireBus(DACDriver *dacp) {
  */
 void dacReleaseBus(DACDriver *dacp) {
 
-  chDbgCheck(dacp != NULL, "dacReleaseBus");
-
-#if CH_USE_MUTEXES
-  (void)dacp;
-  chMtxUnlock();
-#elif CH_USE_SEMAPHORES
-  chSemSignal(&dacp->semaphore);
-#endif
+  osalDbgCheck(dacp != NULL);
+	
+  osalMutexUnlock(&dacp->mutex);
 }
 #endif /* DAC_USE_MUTUAL_EXCLUSION */
 
diff --git a/os/hal/src/ext.c b/os/hal/src/ext.c
index a0dc9f38e..81c92525a 100644
--- a/os/hal/src/ext.c
+++ b/os/hal/src/ext.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_EXT || defined(__DOXYGEN__)
@@ -88,15 +87,15 @@ void extObjectInit(EXTDriver *extp) {
  */
 void extStart(EXTDriver *extp, const EXTConfig *config) {
 
-  chDbgCheck((extp != NULL) && (config != NULL), "extStart");
+  osalDbgCheck((extp != NULL) && (config != NULL));
 
-  chSysLock();
-  chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE),
-              "extStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE),
+                "invalid state");
   extp->config = config;
   ext_lld_start(extp);
   extp->state = EXT_ACTIVE;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -108,14 +107,14 @@ void extStart(EXTDriver *extp, const EXTConfig *config) {
  */
 void extStop(EXTDriver *extp) {
 
-  chDbgCheck(extp != NULL, "extStop");
+  osalDbgCheck(extp != NULL);
 
-  chSysLock();
-  chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE),
-              "extStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE),
+                "invalid state");
   ext_lld_stop(extp);
   extp->state = EXT_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -129,16 +128,15 @@ void extStop(EXTDriver *extp) {
  */
 void extChannelEnable(EXTDriver *extp, expchannel_t channel) {
 
-  chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS),
-             "extChannelEnable");
+  osalDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS));
 
-  chSysLock();
-  chDbgAssert((extp->state == EXT_ACTIVE) &&
-              ((extp->config->channels[channel].mode &
-                EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED),
-              "extChannelEnable(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((extp->state == EXT_ACTIVE) &&
+                ((extp->config->channels[channel].mode &
+                  EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED),
+                "invalid state");
   extChannelEnableI(extp, channel);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -152,16 +150,15 @@ void extChannelEnable(EXTDriver *extp, expchannel_t channel) {
  */
 void extChannelDisable(EXTDriver *extp, expchannel_t channel) {
 
-  chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS),
-             "extChannelDisable");
+  osalDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS));
 
-  chSysLock();
-  chDbgAssert((extp->state == EXT_ACTIVE) &&
-              ((extp->config->channels[channel].mode &
-                EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED),
-              "extChannelDisable(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((extp->state == EXT_ACTIVE) &&
+                ((extp->config->channels[channel].mode &
+                  EXT_CH_MODE_EDGES_MASK) != EXT_CH_MODE_DISABLED),
+                "invalid state");
   extChannelDisableI(extp, channel);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -186,11 +183,11 @@ void extSetChannelModeI(EXTDriver *extp,
                         const EXTChannelConfig *extcp) {
   EXTChannelConfig *oldcp;
 
-  chDbgCheck((extp != NULL) && (channel < EXT_MAX_CHANNELS) &&
-             (extcp != NULL), "extSetChannelModeI");
+  osalDbgCheck((extp != NULL) &&
+               (channel < EXT_MAX_CHANNELS) &&
+               (extcp != NULL));
 
-  chDbgAssert(extp->state == EXT_ACTIVE,
-              "extSetChannelModeI(), #1", "invalid state");
+  osalDbgAssert(extp->state == EXT_ACTIVE, "invalid state");
 
   /* Note that here the access is enforced as non-const, known access
      violation.*/
diff --git a/os/hal/src/gpt.c b/os/hal/src/gpt.c
index eefeb8e32..52bf6610f 100644
--- a/os/hal/src/gpt.c
+++ b/os/hal/src/gpt.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_GPT || defined(__DOXYGEN__)
@@ -86,15 +85,15 @@ void gptObjectInit(GPTDriver *gptp) {
  */
 void gptStart(GPTDriver *gptp, const GPTConfig *config) {
 
-  chDbgCheck((gptp != NULL) && (config != NULL), "gptStart");
+  osalDbgCheck((gptp != NULL) && (config != NULL));
 
-  chSysLock();
-  chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY),
-              "gptStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY),
+              "invalid state");
   gptp->config = config;
   gpt_lld_start(gptp);
   gptp->state = GPT_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -106,22 +105,20 @@ void gptStart(GPTDriver *gptp, const GPTConfig *config) {
  */
 void gptStop(GPTDriver *gptp) {
 
-  chDbgCheck(gptp != NULL, "gptStop");
+  osalDbgCheck(gptp != NULL);
 
-  chSysLock();
-  chDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY),
-              "gptStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((gptp->state == GPT_STOP) || (gptp->state == GPT_READY),
+                "invalid state");
   gpt_lld_stop(gptp);
   gptp->state = GPT_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
  * @brief   Changes the interval of GPT peripheral.
  * @details This function changes the interval of a running GPT unit.
- * @pre     The GPT unit must have been activated using @p gptStart().
- * @pre     The GPT unit must have been running in continuous mode using
- *          @p gptStartContinuous().
+ * @pre     The GPT unit must be running in continuous mode.
  * @post    The GPT unit interval is changed to the new value.
  *
  * @param[in] gptp      pointer to a @p GPTDriver object
@@ -131,13 +128,13 @@ void gptStop(GPTDriver *gptp) {
  */
 void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval) {
 
-  chDbgCheck(gptp != NULL, "gptChangeInterval");
+  osalDbgCheck(gptp != NULL);
 
-  chSysLock();
-  chDbgAssert(gptp->state == GPT_CONTINUOUS,
-              "gptChangeInterval(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert(gptp->state == GPT_CONTINUOUS,
+                "invalid state");
   gptChangeIntervalI(gptp, interval);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -150,9 +147,9 @@ void gptChangeInterval(GPTDriver *gptp, gptcnt_t interval) {
  */
 void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval) {
 
-  chSysLock();
+  osalSysLock();
   gptStartContinuousI(gptp, interval);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -165,10 +162,10 @@ void gptStartContinuous(GPTDriver *gptp, gptcnt_t interval) {
  */
 void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval) {
 
-  chDbgCheckClassI();
-  chDbgCheck(gptp != NULL, "gptStartContinuousI");
-  chDbgAssert(gptp->state == GPT_READY,
-              "gptStartContinuousI(), #1", "invalid state");
+  osalDbgCheckClassI();
+  osalDbgCheck(gptp != NULL);
+  osalDbgAssert(gptp->state == GPT_READY,
+                "invalid state");
 
   gptp->state = GPT_CONTINUOUS;
   gpt_lld_start_timer(gptp, interval);
@@ -184,9 +181,9 @@ void gptStartContinuousI(GPTDriver *gptp, gptcnt_t interval) {
  */
 void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval) {
 
-  chSysLock();
+  osalSysLock();
   gptStartOneShotI(gptp, interval);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -199,10 +196,11 @@ void gptStartOneShot(GPTDriver *gptp, gptcnt_t interval) {
  */
 void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval) {
 
-  chDbgCheckClassI();
-  chDbgCheck(gptp != NULL, "gptStartOneShotI");
-  chDbgAssert(gptp->state == GPT_READY,
-              "gptStartOneShotI(), #1", "invalid state");
+  osalDbgCheckClassI();
+  osalDbgCheck(gptp != NULL);
+  osalDbgCheck(gptp->config->callback != NULL);
+  osalDbgAssert(gptp->state == GPT_READY,
+                "invalid state");
 
   gptp->state = GPT_ONESHOT;
   gpt_lld_start_timer(gptp, interval);
@@ -217,9 +215,9 @@ void gptStartOneShotI(GPTDriver *gptp, gptcnt_t interval) {
  */
 void gptStopTimer(GPTDriver *gptp) {
 
-  chSysLock();
+  osalSysLock();
   gptStopTimerI(gptp);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -231,11 +229,11 @@ void gptStopTimer(GPTDriver *gptp) {
  */
 void gptStopTimerI(GPTDriver *gptp) {
 
-  chDbgCheckClassI();
-  chDbgCheck(gptp != NULL, "gptStopTimerI");
-  chDbgAssert((gptp->state == GPT_READY) || (gptp->state == GPT_CONTINUOUS) ||
-              (gptp->state == GPT_ONESHOT),
-              "gptStopTimerI(), #1", "invalid state");
+  osalDbgCheckClassI();
+  osalDbgCheck(gptp != NULL);
+  osalDbgAssert((gptp->state == GPT_READY) || (gptp->state == GPT_CONTINUOUS) ||
+                (gptp->state == GPT_ONESHOT),
+                "invalid state");
 
   gptp->state = GPT_READY;
   gpt_lld_stop_timer(gptp);
@@ -255,8 +253,8 @@ void gptStopTimerI(GPTDriver *gptp) {
  */
 void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval) {
 
-  chDbgAssert(gptp->state == GPT_READY,
-              "gptPolledDelay(), #1", "invalid state");
+  osalDbgAssert(gptp->state == GPT_READY,
+                "invalid state");
 
   gptp->state = GPT_ONESHOT;
   gpt_lld_polled_delay(gptp, interval);
diff --git a/os/hal/src/hal.c b/os/hal/src/hal.c
index d7a088ec9..aa3eca165 100644
--- a/os/hal/src/hal.c
+++ b/os/hal/src/hal.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 /*===========================================================================*/
@@ -60,11 +59,12 @@
  */
 void halInit(void) {
 
+  /* Initializes the OS Abstraction Layer.*/
+  osalInit();
+
+  /* Platform low level initializations.*/
   hal_lld_init();
 
-#if HAL_USE_TM || defined(__DOXYGEN__)
-  tmInit();
-#endif
 #if HAL_USE_PAL || defined(__DOXYGEN__)
   palInit(&pal_default_config);
 #endif
@@ -74,9 +74,6 @@ void halInit(void) {
 #if HAL_USE_CAN || defined(__DOXYGEN__)
   canInit();
 #endif
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-  dacInit();
-#endif
 #if HAL_USE_EXT || defined(__DOXYGEN__)
   extInit();
 #endif
@@ -86,6 +83,9 @@ void halInit(void) {
 #if HAL_USE_I2C || defined(__DOXYGEN__)
   i2cInit();
 #endif
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+  i2sInit();
+#endif
 #if HAL_USE_ICU || defined(__DOXYGEN__)
   icuInit();
 #endif
@@ -119,79 +119,14 @@ void halInit(void) {
 #if HAL_USE_RTC || defined(__DOXYGEN__)
   rtcInit();
 #endif
+
   /* Board specific initialization.*/
   boardInit();
-}
-
-#if HAL_IMPLEMENTS_COUNTERS || defined(__DOXYGEN__)
-/**
- * @brief   Realtime window test.
- * @details This function verifies if the current realtime counter value
- *          lies within the specified range or not. The test takes care
- *          of the realtime counter wrapping to zero on overflow.
- * @note    When start==end then the function returns always true because the
- *          whole time range is specified.
- * @note    This is an optional service that could not be implemented in
- *          all HAL implementations.
- * @note    This function can be called from any context.
- *
- * @par Example 1
- * Example of a guarded loop using the realtime counter. The loop implements
- * a timeout after one second.
- * @code
- *   halrtcnt_t start = halGetCounterValue();
- *   halrtcnt_t timeout  = start + S2RTT(1);
- *   while (my_condition) {
- *     if (!halIsCounterWithin(start, timeout)
- *       return TIMEOUT;
- *     // Do something.
- *   }
- *   // Continue.
- * @endcode
- *
- * @par Example 2
- * Example of a loop that lasts exactly 50 microseconds.
- * @code
- *   halrtcnt_t start = halGetCounterValue();
- *   halrtcnt_t timeout  = start + US2RTT(50);
- *   while (halIsCounterWithin(start, timeout)) {
- *     // Do something.
- *   }
- *   // Continue.
- * @endcode
- *
- * @param[in] start     the start of the time window (inclusive)
- * @param[in] end       the end of the time window (non inclusive)
- * @retval TRUE         current time within the specified time window.
- * @retval FALSE        current time not within the specified time window.
- *
- * @special
- */
-bool_t halIsCounterWithin(halrtcnt_t start, halrtcnt_t end) {
-  halrtcnt_t now = halGetCounterValue();
-
-  return end > start ? (now >= start) && (now < end) :
-                       (now >= start) || (now < end);
-}
 
-/**
- * @brief   Polled delay.
- * @note    The real delays is always few cycles in excess of the specified
- *          value.
- * @note    This is an optional service that could not be implemented in
- *          all HAL implementations.
- * @note    This function can be called from any context.
- *
- * @param[in] ticks     number of ticks
- *
- * @special
- */
-void halPolledDelay(halrtcnt_t ticks) {
-  halrtcnt_t start = halGetCounterValue();
-  halrtcnt_t timeout  = start + (ticks);
-  while (halIsCounterWithin(start, timeout))
-    ;
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+  /* System tick service if the underlying OS requires it.*/
+  stInit();
+#endif
 }
-#endif /* HAL_IMPLEMENTS_COUNTERS */
 
 /** @} */
diff --git a/os/hal/src/hal_mmcsd.c b/os/hal/src/hal_mmcsd.c
new file mode 100644
index 000000000..b2cfb65a0
--- /dev/null
+++ b/os/hal/src/hal_mmcsd.c
@@ -0,0 +1,113 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    hal_mmcsd.c
+ * @brief   MMC/SD cards common code.
+ *
+ * @addtogroup MMCSD
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Gets a bit field from a words array.
+ * @note    The bit zero is the LSb of the first word.
+ *
+ * @param[in] data      pointer to the words array
+ * @param[in] end       bit offset of the last bit of the field, inclusive
+ * @param[in] start     bit offset of the first bit of the field, inclusive
+ *
+ * @return              The bits field value, left aligned.
+ *
+ * @notapi
+ */
+static uint32_t mmcsd_get_slice(uint32_t *data, uint32_t end, uint32_t start) {
+  unsigned startidx, endidx, startoff;
+  uint32_t endmask;
+
+  osalDbgCheck((end >= start) && ((end - start) < 32));
+
+  startidx = start / 32;
+  startoff = start % 32;
+  endidx   = end / 32;
+  endmask  = (1 << ((end % 32) + 1)) - 1;
+
+  /* One or two pieces?*/
+  if (startidx < endidx)
+    return (data[startidx] >> startoff) |               /* Two pieces case. */
+           ((data[endidx] & endmask) << (32 - startoff));
+  return (data[startidx] & endmask) >> startoff;        /* One piece case.  */
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Extract card capacity from a CSD.
+ * @details The capacity is returned as number of available blocks.
+ *
+ * @param[in] csd       the CSD record
+ *
+ * @return              The card capacity.
+ * @retval 0            CSD format error
+ */
+uint32_t mmcsdGetCapacity(uint32_t csd[4]) {
+
+  switch (csd[3] >> 30) {
+  uint32_t a, b, c;
+  case 0:
+    /* CSD version 1.0 */
+    a = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_SLICE);
+    b = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_MULT_SLICE);
+    c = mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_LEN_SLICE);
+    return (a + 1) << (b + 2) << (c - 9);       /* 2^9 == MMCSD_BLOCK_SIZE. */
+  case 1:
+    /* CSD version 2.0.*/
+    return 1024 * (mmcsd_get_slice(csd, MMCSD_CSD_20_C_SIZE_SLICE) + 1);
+  default:
+    /* Reserved value detected.*/
+    return 0;
+  }
+}
+
+#endif /* HAL_USE_MMC_SPI || HAL_USE_SDC */
+
+/** @} */
diff --git a/os/hal/src/hal_queues.c b/os/hal/src/hal_queues.c
new file mode 100644
index 000000000..dac58a155
--- /dev/null
+++ b/os/hal/src/hal_queues.c
@@ -0,0 +1,402 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    hal_queues.c
+ * @brief   I/O Queues code.
+ *
+ * @addtogroup io_queues
+ * @details Queues are mostly used in serial-like device drivers.
+ *          Serial device drivers are usually designed to have a lower side
+ *          (lower driver, it is usually an interrupt service routine) and an
+ *          upper side (upper driver, accessed by the application threads).<br>
+ *          There are several kind of queues:<br>
+ *          - <b>Input queue</b>, unidirectional queue where the writer is the
+ *            lower side and the reader is the upper side.
+ *          - <b>Output queue</b>, unidirectional queue where the writer is the
+ *            upper side and the reader is the lower side.
+ *          - <b>Full duplex queue</b>, bidirectional queue. Full duplex queues
+ *            are implemented by pairing an input queue and an output queue
+ *            together.
+ *          .
+ * @{
+ */
+
+#include "hal.h"
+
+#if !defined(_CHIBIOS_RT_) || !CH_CFG_USE_QUEUES || defined(__DOXYGEN__)
+
+/**
+ * @brief   Initializes an input queue.
+ * @details A Semaphore is internally initialized and works as a counter of
+ *          the bytes contained in the queue.
+ * @note    The callback is invoked from within the S-Locked system state,
+ *          see @ref system_states.
+ *
+ * @param[out] iqp      pointer to an @p input_queue_t structure
+ * @param[in] bp        pointer to a memory area allocated as queue buffer
+ * @param[in] size      size of the queue buffer
+ * @param[in] infy      pointer to a callback function that is invoked when
+ *                      data is read from the queue. The value can be @p NULL.
+ * @param[in] link      application defined pointer
+ *
+ * @init
+ */
+void iqObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size,
+                  qnotify_t infy, void *link) {
+
+  osalThreadQueueObjectInit(&iqp->q_waiting);
+  iqp->q_counter = 0;
+  iqp->q_buffer  = iqp->q_rdptr = iqp->q_wrptr = bp;
+  iqp->q_top     = bp + size;
+  iqp->q_notify  = infy;
+  iqp->q_link    = link;
+}
+
+/**
+ * @brief   Resets an input queue.
+ * @details All the data in the input queue is erased and lost, any waiting
+ *          thread is resumed with status @p Q_RESET.
+ * @note    A reset operation can be used by a low level driver in order to
+ *          obtain immediate attention from the high level layers.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ *
+ * @iclass
+ */
+void iqResetI(input_queue_t *iqp) {
+
+  osalDbgCheckClassI();
+
+  iqp->q_rdptr = iqp->q_wrptr = iqp->q_buffer;
+  iqp->q_counter = 0;
+  osalThreadDequeueAllI(&iqp->q_waiting, Q_RESET);
+}
+
+/**
+ * @brief   Input queue write.
+ * @details A byte value is written into the low end of an input queue.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @param[in] b         the byte value to be written in the queue
+ * @return              The operation status.
+ * @retval Q_OK         if the operation has been completed with success.
+ * @retval Q_FULL       if the queue is full and the operation cannot be
+ *                      completed.
+ *
+ * @iclass
+ */
+msg_t iqPutI(input_queue_t *iqp, uint8_t b) {
+
+  osalDbgCheckClassI();
+
+  if (iqIsFullI(iqp))
+    return Q_FULL;
+
+  iqp->q_counter++;
+  *iqp->q_wrptr++ = b;
+  if (iqp->q_wrptr >= iqp->q_top)
+    iqp->q_wrptr = iqp->q_buffer;
+
+  osalThreadDequeueNextI(&iqp->q_waiting, Q_OK);
+
+  return Q_OK;
+}
+
+/**
+ * @brief   Input queue read with timeout.
+ * @details This function reads a byte value from an input queue. If the queue
+ *          is empty then the calling thread is suspended until a byte arrives
+ *          in the queue or a timeout occurs.
+ * @note    The callback is invoked before reading the character from the
+ *          buffer or before entering the state @p THD_STATE_WTQUEUE.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              A byte value from the queue.
+ * @retval Q_TIMEOUT    if the specified time expired.
+ * @retval Q_RESET      if the queue has been reset.
+ *
+ * @api
+ */
+msg_t iqGetTimeout(input_queue_t *iqp, systime_t time) {
+  uint8_t b;
+
+  osalSysLock();
+  if (iqp->q_notify)
+    iqp->q_notify(iqp);
+
+  while (iqIsEmptyI(iqp)) {
+    msg_t msg;
+    if ((msg = osalThreadEnqueueTimeoutS(&iqp->q_waiting, time)) < Q_OK) {
+      osalSysUnlock();
+      return msg;
+    }
+  }
+
+  iqp->q_counter--;
+  b = *iqp->q_rdptr++;
+  if (iqp->q_rdptr >= iqp->q_top)
+    iqp->q_rdptr = iqp->q_buffer;
+
+  osalSysUnlock();
+  return b;
+}
+
+/**
+ * @brief   Input queue read with timeout.
+ * @details The function reads data from an input queue into a buffer. The
+ *          operation completes when the specified amount of data has been
+ *          transferred or after the specified timeout or if the queue has
+ *          been reset.
+ * @note    The function is not atomic, if you need atomicity it is suggested
+ *          to use a semaphore or a mutex for mutual exclusion.
+ * @note    The callback is invoked before reading each character from the
+ *          buffer or before entering the state @p THD_STATE_WTQUEUE.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @param[out] bp       pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred, the
+ *                      value 0 is reserved
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The number of bytes effectively transferred.
+ *
+ * @api
+ */
+size_t iqReadTimeout(input_queue_t *iqp, uint8_t *bp,
+                     size_t n, systime_t time) {
+  qnotify_t nfy = iqp->q_notify;
+  size_t r = 0;
+
+  osalDbgCheck(n > 0);
+
+  osalSysLock();
+  while (TRUE) {
+    if (nfy)
+      nfy(iqp);
+
+    while (iqIsEmptyI(iqp)) {
+      if (osalThreadEnqueueTimeoutS(&iqp->q_waiting, time) != Q_OK) {
+        osalSysUnlock();
+        return r;
+      }
+    }
+
+    iqp->q_counter--;
+    *bp++ = *iqp->q_rdptr++;
+    if (iqp->q_rdptr >= iqp->q_top)
+      iqp->q_rdptr = iqp->q_buffer;
+
+    osalSysUnlock(); /* Gives a preemption chance in a controlled point.*/
+    r++;
+    if (--n == 0)
+      return r;
+
+    osalSysLock();
+  }
+}
+
+/**
+ * @brief   Initializes an output queue.
+ * @details A Semaphore is internally initialized and works as a counter of
+ *          the free bytes in the queue.
+ * @note    The callback is invoked from within the S-Locked system state,
+ *          see @ref system_states.
+ *
+ * @param[out] oqp      pointer to an @p output_queue_t structure
+ * @param[in] bp        pointer to a memory area allocated as queue buffer
+ * @param[in] size      size of the queue buffer
+ * @param[in] onfy      pointer to a callback function that is invoked when
+ *                      data is written to the queue. The value can be @p NULL.
+ * @param[in] link      application defined pointer
+ *
+ * @init
+ */
+void oqObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size,
+                  qnotify_t onfy, void *link) {
+
+  osalThreadQueueObjectInit(&oqp->q_waiting);
+  oqp->q_counter = size;
+  oqp->q_buffer  = oqp->q_rdptr = oqp->q_wrptr = bp;
+  oqp->q_top     = bp + size;
+  oqp->q_notify  = onfy;
+  oqp->q_link    = link;
+}
+
+/**
+ * @brief   Resets an output queue.
+ * @details All the data in the output queue is erased and lost, any waiting
+ *          thread is resumed with status @p Q_RESET.
+ * @note    A reset operation can be used by a low level driver in order to
+ *          obtain immediate attention from the high level layers.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ *
+ * @iclass
+ */
+void oqResetI(output_queue_t *oqp) {
+
+  osalDbgCheckClassI();
+
+  oqp->q_rdptr = oqp->q_wrptr = oqp->q_buffer;
+  oqp->q_counter = qSizeI(oqp);
+  osalThreadDequeueAllI(&oqp->q_waiting, Q_RESET);
+}
+
+/**
+ * @brief   Output queue write with timeout.
+ * @details This function writes a byte value to an output queue. If the queue
+ *          is full then the calling thread is suspended until there is space
+ *          in the queue or a timeout occurs.
+ * @note    The callback is invoked after writing the character into the
+ *          buffer.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @param[in] b         the byte value to be written in the queue
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval Q_OK         if the operation succeeded.
+ * @retval Q_TIMEOUT    if the specified time expired.
+ * @retval Q_RESET      if the queue has been reset.
+ *
+ * @api
+ */
+msg_t oqPutTimeout(output_queue_t *oqp, uint8_t b, systime_t time) {
+
+  osalSysLock();
+  while (oqIsFullI(oqp)) {
+    msg_t msg;
+
+    if ((msg = osalThreadEnqueueTimeoutS(&oqp->q_waiting, time)) < Q_OK) {
+      osalSysUnlock();
+      return msg;
+    }
+  }
+
+  oqp->q_counter--;
+  *oqp->q_wrptr++ = b;
+  if (oqp->q_wrptr >= oqp->q_top)
+    oqp->q_wrptr = oqp->q_buffer;
+
+  if (oqp->q_notify)
+    oqp->q_notify(oqp);
+
+  osalSysUnlock();
+  return Q_OK;
+}
+
+/**
+ * @brief   Output queue read.
+ * @details A byte value is read from the low end of an output queue.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @return              The byte value from the queue.
+ * @retval Q_EMPTY      if the queue is empty.
+ *
+ * @iclass
+ */
+msg_t oqGetI(output_queue_t *oqp) {
+  uint8_t b;
+
+  osalDbgCheckClassI();
+
+  if (oqIsEmptyI(oqp))
+    return Q_EMPTY;
+
+  oqp->q_counter++;
+  b = *oqp->q_rdptr++;
+  if (oqp->q_rdptr >= oqp->q_top)
+    oqp->q_rdptr = oqp->q_buffer;
+
+  osalThreadDequeueNextI(&oqp->q_waiting, Q_OK);
+
+  return b;
+}
+
+/**
+ * @brief   Output queue write with timeout.
+ * @details The function writes data from a buffer to an output queue. The
+ *          operation completes when the specified amount of data has been
+ *          transferred or after the specified timeout or if the queue has
+ *          been reset.
+ * @note    The function is not atomic, if you need atomicity it is suggested
+ *          to use a semaphore or a mutex for mutual exclusion.
+ * @note    The callback is invoked after writing each character into the
+ *          buffer.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @param[out] bp       pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred, the
+ *                      value 0 is reserved
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The number of bytes effectively transferred.
+ *
+ * @api
+ */
+size_t oqWriteTimeout(output_queue_t *oqp, const uint8_t *bp,
+                      size_t n, systime_t time) {
+  qnotify_t nfy = oqp->q_notify;
+  size_t w = 0;
+
+  osalDbgCheck(n > 0);
+
+  osalSysLock();
+  while (TRUE) {
+    while (oqIsFullI(oqp)) {
+      if (osalThreadEnqueueTimeoutS(&oqp->q_waiting, time) != Q_OK) {
+        osalSysUnlock();
+        return w;
+      }
+    }
+    oqp->q_counter--;
+    *oqp->q_wrptr++ = *bp++;
+    if (oqp->q_wrptr >= oqp->q_top)
+      oqp->q_wrptr = oqp->q_buffer;
+
+    if (nfy)
+      nfy(oqp);
+
+    osalSysUnlock(); /* Gives a preemption chance in a controlled point.*/
+    w++;
+    if (--n == 0)
+      return w;
+    osalSysLock();
+  }
+}
+
+#endif /* !defined(_CHIBIOS_RT_) || !CH_USE_QUEUES */
+
+/** @} */
diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c
index 5ec7c284b..ba349457d 100644
--- a/os/hal/src/i2c.c
+++ b/os/hal/src/i2c.c
@@ -29,7 +29,6 @@
  * @addtogroup I2C
  * @{
  */
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_I2C || defined(__DOXYGEN__)
@@ -62,6 +61,7 @@
  * @init
  */
 void i2cInit(void) {
+
   i2c_lld_init();
 }
 
@@ -78,11 +78,7 @@ void i2cObjectInit(I2CDriver *i2cp) {
   i2cp->config = NULL;
 
 #if I2C_USE_MUTUAL_EXCLUSION
-#if CH_USE_MUTEXES
-  chMtxInit(&i2cp->mutex);
-#else
-  chSemInit(&i2cp->semaphore, 1);
-#endif /* CH_USE_MUTEXES */
+  osalMutexObjectInit(&i2cp->mutex);
 #endif /* I2C_USE_MUTUAL_EXCLUSION */
 
 #if defined(I2C_DRIVER_EXT_INIT_HOOK)
@@ -100,17 +96,15 @@ void i2cObjectInit(I2CDriver *i2cp) {
  */
 void i2cStart(I2CDriver *i2cp, const I2CConfig *config) {
 
-  chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart");
-  chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) ||
-              (i2cp->state == I2C_LOCKED),
-              "i2cStart(), #1",
-              "invalid state");
+  osalDbgCheck((i2cp != NULL) && (config != NULL));
+  osalDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) ||
+                (i2cp->state == I2C_LOCKED), "invalid state");
 
-  chSysLock();
+  osalSysLock();
   i2cp->config = config;
   i2c_lld_start(i2cp);
   i2cp->state = I2C_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -122,16 +116,14 @@ void i2cStart(I2CDriver *i2cp, const I2CConfig *config) {
  */
 void i2cStop(I2CDriver *i2cp) {
 
-  chDbgCheck(i2cp != NULL, "i2cStop");
-  chDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) ||
-              (i2cp->state == I2C_LOCKED),
-              "i2cStop(), #1",
-              "invalid state");
+  osalDbgCheck(i2cp != NULL);
+  osalDbgAssert((i2cp->state == I2C_STOP) || (i2cp->state == I2C_READY) ||
+                (i2cp->state == I2C_LOCKED), "invalid state");
 
-  chSysLock();
+  osalSysLock();
   i2c_lld_stop(i2cp);
   i2cp->state = I2C_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -144,7 +136,7 @@ void i2cStop(I2CDriver *i2cp) {
  */
 i2cflags_t i2cGetErrors(I2CDriver *i2cp) {
 
-  chDbgCheck(i2cp != NULL, "i2cGetErrors");
+  osalDbgCheck(i2cp != NULL);
 
   return i2c_lld_get_errors(i2cp);
 }
@@ -168,10 +160,10 @@ i2cflags_t i2cGetErrors(I2CDriver *i2cp) {
  *                      .
  *
  * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
+ * @retval MSG_OK       if the function succeeded.
+ * @retval MSG_RESET    if one or more I2C errors occurred, the errors can
  *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end.
+ * @retval MSG_TIMEOUT  if a timeout occurred before operation end.
  *
  * @api
  */
@@ -184,25 +176,23 @@ msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp,
                                systime_t timeout) {
   msg_t rdymsg;
 
-  chDbgCheck((i2cp != NULL) && (addr != 0) &&
-             (txbytes > 0) && (txbuf != NULL) &&
-             ((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))) &&
-             (timeout != TIME_IMMEDIATE),
-             "i2cMasterTransmitTimeout");
+  osalDbgCheck((i2cp != NULL) && (addr != 0) &&
+               (txbytes > 0) && (txbuf != NULL) &&
+               ((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))) &&
+               (timeout != TIME_IMMEDIATE));
 
-  chDbgAssert(i2cp->state == I2C_READY,
-              "i2cMasterTransmitTimeout(), #1", "not ready");
+  osalDbgAssert(i2cp->state == I2C_READY, "not ready");
 
-  chSysLock();
-  i2cp->errors = I2CD_NO_ERROR;
+  osalSysLock();
+  i2cp->errors = I2C_NO_ERROR;
   i2cp->state = I2C_ACTIVE_TX;
   rdymsg = i2c_lld_master_transmit_timeout(i2cp, addr, txbuf, txbytes,
                                            rxbuf, rxbytes, timeout);
-  if (rdymsg == RDY_TIMEOUT)
+  if (rdymsg == MSG_TIMEOUT)
     i2cp->state = I2C_LOCKED;
   else
     i2cp->state = I2C_READY;
-  chSysUnlock();
+  osalSysUnlock();
   return rdymsg;
 }
 
@@ -219,10 +209,10 @@ msg_t i2cMasterTransmitTimeout(I2CDriver *i2cp,
  *                      .
  *
  * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
+ * @retval MSG_OK       if the function succeeded.
+ * @retval MSG_RESET    if one or more I2C errors occurred, the errors can
  *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end.
+ * @retval MSG_TIMEOUT  if a timeout occurred before operation end.
  *
  * @api
  */
@@ -234,23 +224,21 @@ msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp,
 
   msg_t rdymsg;
 
-  chDbgCheck((i2cp != NULL) && (addr != 0) &&
-             (rxbytes > 0) && (rxbuf != NULL) &&
-             (timeout != TIME_IMMEDIATE),
-             "i2cMasterReceiveTimeout");
+  osalDbgCheck((i2cp != NULL) && (addr != 0) &&
+               (rxbytes > 0) && (rxbuf != NULL) &&
+               (timeout != TIME_IMMEDIATE));
 
-  chDbgAssert(i2cp->state == I2C_READY,
-              "i2cMasterReceive(), #1", "not ready");
+  osalDbgAssert(i2cp->state == I2C_READY, "not ready");
 
-  chSysLock();
-  i2cp->errors = I2CD_NO_ERROR;
+  osalSysLock();
+  i2cp->errors = I2C_NO_ERROR;
   i2cp->state = I2C_ACTIVE_RX;
   rdymsg = i2c_lld_master_receive_timeout(i2cp, addr, rxbuf, rxbytes, timeout);
-  if (rdymsg == RDY_TIMEOUT)
+  if (rdymsg == MSG_TIMEOUT)
     i2cp->state = I2C_LOCKED;
   else
     i2cp->state = I2C_READY;
-  chSysUnlock();
+  osalSysUnlock();
   return rdymsg;
 }
 
@@ -268,13 +256,9 @@ msg_t i2cMasterReceiveTimeout(I2CDriver *i2cp,
  */
 void i2cAcquireBus(I2CDriver *i2cp) {
 
-  chDbgCheck(i2cp != NULL, "i2cAcquireBus");
+  osalDbgCheck(i2cp != NULL);
 
-#if CH_USE_MUTEXES
-  chMtxLock(&i2cp->mutex);
-#elif CH_USE_SEMAPHORES
-  chSemWait(&i2cp->semaphore);
-#endif
+  osalMutexLock(&i2cp->mutex);
 }
 
 /**
@@ -288,13 +272,9 @@ void i2cAcquireBus(I2CDriver *i2cp) {
  */
 void i2cReleaseBus(I2CDriver *i2cp) {
 
-  chDbgCheck(i2cp != NULL, "i2cReleaseBus");
+  osalDbgCheck(i2cp != NULL);
 
-#if CH_USE_MUTEXES
-  chMtxUnlock();
-#elif CH_USE_SEMAPHORES
-  chSemSignal(&i2cp->semaphore);
-#endif
+  osalMutexUnlock(&i2cp->mutex);
 }
 #endif /* I2C_USE_MUTUAL_EXCLUSION */
 
diff --git a/os/hal/src/i2s.c b/os/hal/src/i2s.c
index e43d51ab2..e2b51ec98 100644
--- a/os/hal/src/i2s.c
+++ b/os/hal/src/i2s.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_I2S || defined(__DOXYGEN__)
@@ -86,15 +85,15 @@ void i2sObjectInit(I2SDriver *i2sp) {
  */
 void i2sStart(I2SDriver *i2sp, const I2SConfig *config) {
 
-  chDbgCheck((i2sp != NULL) && (config != NULL), "i2sStart");
+  osalDbgCheck((i2sp != NULL) && (config != NULL));
 
-  chSysLock();
-  chDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY),
-              "i2sStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY),
+                "invalid state");
   i2sp->config = config;
   i2s_lld_start(i2sp);
   i2sp->state = I2S_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -106,14 +105,14 @@ void i2sStart(I2SDriver *i2sp, const I2SConfig *config) {
  */
 void i2sStop(I2SDriver *i2sp) {
 
-  chDbgCheck(i2sp != NULL, "i2sStop");
+  osalDbgCheck(i2sp != NULL);
 
-  chSysLock();
-  chDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY),
-              "i2sStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY),
+                "invalid state");
   i2s_lld_stop(i2sp);
   i2sp->state = I2S_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -125,31 +124,12 @@ void i2sStop(I2SDriver *i2sp) {
  */
 void i2sStartExchange(I2SDriver *i2sp) {
 
-  chDbgCheck(i2sp != NULL "i2sStartExchange");
+  osalDbgCheck(i2sp != NULL);
 
-  chSysLock();
-  chDbgAssert(i2sp->state == I2S_READY,
-              "i2sStartExchange(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert(i2sp->state == I2S_READY, "not ready");
   i2sStartExchangeI(i2sp);
-  chSysUnlock();
-}
-
-/**
- * @brief   Starts a I2S data exchange in continuous mode.
- *
- * @param[in] i2sp      pointer to the @p I2SDriver object
- *
- * @api
- */
-void i2sStartExchangeContinuous(I2SDriver *i2sp) {
-
-  chDbgCheck(i2sp != NULL "i2sStartExchangeContinuous");
-
-  chSysLock();
-  chDbgAssert(i2sp->state == I2S_READY,
-              "i2sStartExchangeContinuous(), #1", "not ready");
-  i2sStartExchangeContinuousI(i2sp);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -163,15 +143,15 @@ void i2sStartExchangeContinuous(I2SDriver *i2sp) {
  */
 void i2sStopExchange(I2SDriver *i2sp) {
 
-  chDbgCheck((i2sp != NULL), "i2sStopExchange");
+  osalDbgCheck((i2sp != NULL));
 
-  chSysLock();
-  chDbgAssert((i2sp->state == I2S_READY) ||
-              (i2sp->state == I2S_ACTIVE) ||
-              (i2sp->state == I2S_COMPLETE),
-              "i2sStopExchange(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert((i2sp->state == I2S_READY) ||
+                (i2sp->state == I2S_ACTIVE) ||
+                (i2sp->state == I2S_COMPLETE),
+                "invalid state");
   i2sStopExchangeI(i2sp);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 #endif /* HAL_USE_I2S */
diff --git a/os/hal/src/icu.c b/os/hal/src/icu.c
index 65d5de907..291b6df9a 100644
--- a/os/hal/src/icu.c
+++ b/os/hal/src/icu.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_ICU || defined(__DOXYGEN__)
@@ -86,15 +85,15 @@ void icuObjectInit(ICUDriver *icup) {
  */
 void icuStart(ICUDriver *icup, const ICUConfig *config) {
 
-  chDbgCheck((icup != NULL) && (config != NULL), "icuStart");
+  osalDbgCheck((icup != NULL) && (config != NULL));
 
-  chSysLock();
-  chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY),
-              "icuStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY),
+                "invalid state");
   icup->config = config;
   icu_lld_start(icup);
   icup->state = ICU_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -106,14 +105,14 @@ void icuStart(ICUDriver *icup, const ICUConfig *config) {
  */
 void icuStop(ICUDriver *icup) {
 
-  chDbgCheck(icup != NULL, "icuStop");
+  osalDbgCheck(icup != NULL);
 
-  chSysLock();
-  chDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY),
-              "icuStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((icup->state == ICU_STOP) || (icup->state == ICU_READY),
+                "invalid state");
   icu_lld_stop(icup);
   icup->state = ICU_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -125,13 +124,13 @@ void icuStop(ICUDriver *icup) {
  */
 void icuEnable(ICUDriver *icup) {
 
-  chDbgCheck(icup != NULL, "icuEnable");
+  osalDbgCheck(icup != NULL);
 
-  chSysLock();
-  chDbgAssert(icup->state == ICU_READY, "icuEnable(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert(icup->state == ICU_READY, "invalid state");
   icu_lld_enable(icup);
   icup->state = ICU_WAITING;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -143,15 +142,15 @@ void icuEnable(ICUDriver *icup) {
  */
 void icuDisable(ICUDriver *icup) {
 
-  chDbgCheck(icup != NULL, "icuDisable");
+  osalDbgCheck(icup != NULL);
 
-  chSysLock();
-  chDbgAssert((icup->state == ICU_READY) || (icup->state == ICU_WAITING) ||
-              (icup->state == ICU_ACTIVE) || (icup->state == ICU_IDLE),
-              "icuDisable(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((icup->state == ICU_READY) || (icup->state == ICU_WAITING) ||
+                (icup->state == ICU_ACTIVE) || (icup->state == ICU_IDLE),
+                "invalid state");
   icu_lld_disable(icup);
   icup->state = ICU_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 #endif /* HAL_USE_ICU */
diff --git a/os/hal/src/mac.c b/os/hal/src/mac.c
deleted file mode 100644
index cb62db612..000000000
--- a/os/hal/src/mac.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    mac.c
- * @brief   MAC Driver code.
- *
- * @addtogroup MAC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#if MAC_USE_ZERO_COPY && !MAC_SUPPORTS_ZERO_COPY
-#error "MAC_USE_ZERO_COPY not supported by this implementation"
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   MAC Driver initialization.
- * @note    This function is implicitly invoked by @p halInit(), there is
- *          no need to explicitly initialize the driver.
- *
- * @init
- */
-void macInit(void) {
-
-  mac_lld_init();
-}
-
-/**
- * @brief   Initialize the standard part of a @p MACDriver structure.
- *
- * @param[out] macp     pointer to the @p MACDriver object
- *
- * @init
- */
-void macObjectInit(MACDriver *macp) {
-
-  macp->state  = MAC_STOP;
-  macp->config = NULL;
-  chSemInit(&macp->tdsem, 0);
-  chSemInit(&macp->rdsem, 0);
-#if MAC_USE_EVENTS
-  chEvtInit(&macp->rdevent);
-#endif
-}
-
-/**
- * @brief   Configures and activates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[in] config    pointer to the @p MACConfig object
- *
- * @api
- */
-void macStart(MACDriver *macp, const MACConfig *config) {
-
-  chDbgCheck((macp != NULL) && (config != NULL), "macStart");
-
-  chSysLock();
-  chDbgAssert(macp->state == MAC_STOP,
-              "macStart(), #1", "invalid state");
-  macp->config = config;
-  mac_lld_start(macp);
-  macp->state = MAC_ACTIVE;
-  chSysUnlock();
-}
-
-/**
- * @brief   Deactivates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @api
- */
-void macStop(MACDriver *macp) {
-
-  chDbgCheck(macp != NULL, "macStop");
-
-  chSysLock();
-  chDbgAssert((macp->state == MAC_STOP) || (macp->state == MAC_ACTIVE),
-              "macStop(), #1", "invalid state");
-  mac_lld_stop(macp);
-  macp->state = MAC_STOP;
-  chSysUnlock();
-}
-
-/**
- * @brief   Allocates a transmission descriptor.
- * @details One of the available transmission descriptors is locked and
- *          returned. If a descriptor is not currently available then the
- *          invoking thread is queued until one is freed.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] tdp      pointer to a @p MACTransmitDescriptor structure
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       the descriptor was obtained.
- * @retval RDY_TIMEOUT  the operation timed out, descriptor not initialized.
- *
- * @api
- */
-msg_t macWaitTransmitDescriptor(MACDriver *macp,
-                                MACTransmitDescriptor *tdp,
-                                systime_t time) {
-  msg_t msg;
-  systime_t now;
-
-  chDbgCheck((macp != NULL) && (tdp != NULL), "macWaitTransmitDescriptor");
-  chDbgAssert(macp->state == MAC_ACTIVE, "macWaitTransmitDescriptor(), #1",
-              "not active");
-
-  while (((msg = mac_lld_get_transmit_descriptor(macp, tdp)) != RDY_OK) &&
-         (time > 0)) {
-    chSysLock();
-    now = chTimeNow();
-    if ((msg = chSemWaitTimeoutS(&macp->tdsem, time)) == RDY_TIMEOUT) {
-      chSysUnlock();
-      break;
-    }
-    if (time != TIME_INFINITE)
-      time -= (chTimeNow() - now);
-    chSysUnlock();
-  }
-  return msg;
-}
-
-/**
- * @brief   Releases a transmit descriptor and starts the transmission of the
- *          enqueued data as a single frame.
- *
- * @param[in] tdp       the pointer to the @p MACTransmitDescriptor structure
- *
- * @api
- */
-void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) {
-
-  chDbgCheck((tdp != NULL), "macReleaseTransmitDescriptor");
-
-  mac_lld_release_transmit_descriptor(tdp);
-}
-
-/**
- * @brief   Waits for a received frame.
- * @details Stops until a frame is received and buffered. If a frame is
- *          not immediately available then the invoking thread is queued
- *          until one is received.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] rdp      pointer to a @p MACReceiveDescriptor structure
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       the descriptor was obtained.
- * @retval RDY_TIMEOUT  the operation timed out, descriptor not initialized.
- *
- * @api
- */
-msg_t macWaitReceiveDescriptor(MACDriver *macp,
-                               MACReceiveDescriptor *rdp,
-                               systime_t time) {
-  msg_t msg;
-  systime_t now;
-
-  chDbgCheck((macp != NULL) && (rdp != NULL), "macWaitReceiveDescriptor");
-  chDbgAssert(macp->state == MAC_ACTIVE, "macWaitReceiveDescriptor(), #1",
-              "not active");
-
-  while (((msg = mac_lld_get_receive_descriptor(macp, rdp)) != RDY_OK) &&
-         (time > 0)) {
-    chSysLock();
-    now = chTimeNow();
-    if ((msg = chSemWaitTimeoutS(&macp->rdsem, time)) == RDY_TIMEOUT) {
-      chSysUnlock();
-      break;
-    }
-    if (time != TIME_INFINITE)
-      time -= (chTimeNow() - now);
-    chSysUnlock();
-  }
-  return msg;
-}
-
-/**
- * @brief   Releases a receive descriptor.
- * @details The descriptor and its buffer are made available for more incoming
- *          frames.
- *
- * @param[in] rdp       the pointer to the @p MACReceiveDescriptor structure
- *
- * @api
- */
-void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) {
-
-  chDbgCheck((rdp != NULL), "macReleaseReceiveDescriptor");
-
-  mac_lld_release_receive_descriptor(rdp);
-}
-
-/**
- * @brief   Updates and returns the link status.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @return              The link status.
- * @retval TRUE         if the link is active.
- * @retval FALSE        if the link is down.
- *
- * @api
- */
-bool_t macPollLinkStatus(MACDriver *macp) {
-
-  chDbgCheck((macp != NULL), "macPollLinkStatus");
-  chDbgAssert(macp->state == MAC_ACTIVE, "macPollLinkStatus(), #1",
-              "not active");
-
-  return mac_lld_poll_link_status(macp);
-}
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/src/mmc_spi.c b/os/hal/src/mmc_spi.c
index fbdb92c03..4ffaecfd4 100644
--- a/os/hal/src/mmc_spi.c
+++ b/os/hal/src/mmc_spi.c
@@ -31,7 +31,6 @@
 
 #include <string.h>
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
@@ -49,23 +48,23 @@
 /*===========================================================================*/
 
 /* Forward declarations required by mmc_vmt.*/
-static bool_t mmc_read(void *instance, uint32_t startblk,
+static bool mmc_read(void *instance, uint32_t startblk,
                        uint8_t *buffer, uint32_t n);
-static bool_t mmc_write(void *instance, uint32_t startblk,
+static bool mmc_write(void *instance, uint32_t startblk,
                         const uint8_t *buffer, uint32_t n);
 
 /**
  * @brief   Virtual methods table.
  */
 static const struct MMCDriverVMT mmc_vmt = {
-  (bool_t (*)(void *))mmc_lld_is_card_inserted,
-  (bool_t (*)(void *))mmc_lld_is_write_protected,
-  (bool_t (*)(void *))mmcConnect,
-  (bool_t (*)(void *))mmcDisconnect,
+  (bool (*)(void *))mmc_lld_is_card_inserted,
+  (bool (*)(void *))mmc_lld_is_write_protected,
+  (bool (*)(void *))mmcConnect,
+  (bool (*)(void *))mmcDisconnect,
   mmc_read,
   mmc_write,
-  (bool_t (*)(void *))mmcSync,
-  (bool_t (*)(void *, BlockDeviceInfo *))mmcGetInfo
+  (bool (*)(void *))mmcSync,
+  (bool (*)(void *, BlockDeviceInfo *))mmcGetInfo
 };
 
 /**
@@ -100,7 +99,7 @@ static const uint8_t crc7_lookup_table[256] = {
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-static bool_t mmc_read(void *instance, uint32_t startblk,
+static bool mmc_read(void *instance, uint32_t startblk,
                 uint8_t *buffer, uint32_t n) {
 
   if (mmcStartSequentialRead((MMCDriver *)instance, startblk))
@@ -116,7 +115,7 @@ static bool_t mmc_read(void *instance, uint32_t startblk,
   return CH_SUCCESS;
 }
 
-static bool_t mmc_write(void *instance, uint32_t startblk,
+static bool mmc_write(void *instance, uint32_t startblk,
                  const uint8_t *buffer, uint32_t n) {
 
   if (mmcStartSequentialWrite((MMCDriver *)instance, startblk))
@@ -298,7 +297,7 @@ static uint8_t send_command_R3(MMCDriver *mmcp, uint8_t cmd, uint32_t arg,
  *
  * @notapi
  */
-static bool_t read_CxD(MMCDriver *mmcp, uint8_t cmd, uint32_t cxd[4]) {
+static bool read_CxD(MMCDriver *mmcp, uint8_t cmd, uint32_t cxd[4]) {
   unsigned i;
   uint8_t *bp, buf[16];
 
@@ -395,9 +394,9 @@ void mmcObjectInit(MMCDriver *mmcp) {
  */
 void mmcStart(MMCDriver *mmcp, const MMCConfig *config) {
 
-  chDbgCheck((mmcp != NULL) && (config != NULL), "mmcStart");
-  chDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE),
-              "mmcStart(), #1", "invalid state");
+  osalDbgCheck((mmcp != NULL) && (config != NULL));
+  osalDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE),
+                "invalid state");
 
   mmcp->config = config;
   mmcp->state = BLK_ACTIVE;
@@ -412,9 +411,9 @@ void mmcStart(MMCDriver *mmcp, const MMCConfig *config) {
  */
 void mmcStop(MMCDriver *mmcp) {
 
-  chDbgCheck(mmcp != NULL, "mmcStop");
-  chDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE),
-              "mmcStop(), #1", "invalid state");
+  osalDbgCheck(mmcp != NULL);
+  osalDbgAssert((mmcp->state == BLK_STOP) || (mmcp->state == BLK_ACTIVE),
+                "invalid state");
 
   spiStop(mmcp->config->spip);
   mmcp->state = BLK_STOP;
@@ -437,14 +436,14 @@ void mmcStop(MMCDriver *mmcp) {
  *
  * @api
  */
-bool_t mmcConnect(MMCDriver *mmcp) {
+bool mmcConnect(MMCDriver *mmcp) {
   unsigned i;
   uint8_t r3[4];
 
-  chDbgCheck(mmcp != NULL, "mmcConnect");
+  osalDbgCheck(mmcp != NULL);
 
-  chDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY),
-              "mmcConnect(), #1", "invalid state");
+  osalDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY),
+                "invalid state");
 
   /* Connection procedure in progress.*/
   mmcp->state = BLK_CONNECTING;
@@ -545,19 +544,19 @@ failed:
  *
  * @api
  */
-bool_t mmcDisconnect(MMCDriver *mmcp) {
+bool mmcDisconnect(MMCDriver *mmcp) {
 
-  chDbgCheck(mmcp != NULL, "mmcDisconnect");
+  osalDbgCheck(mmcp != NULL);
 
-  chSysLock();
-  chDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY),
-              "mmcDisconnect(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((mmcp->state == BLK_ACTIVE) || (mmcp->state == BLK_READY),
+                "invalid state");
   if (mmcp->state == BLK_ACTIVE) {
-    chSysUnlock();
+    osalSysUnlock();
     return CH_SUCCESS;
   }
   mmcp->state = BLK_DISCONNECTING;
-  chSysUnlock();
+  osalSysUnlock();
 
   /* Wait for the pending write operations to complete.*/
   spiStart(mmcp->config->spip, mmcp->config->hscfg);
@@ -580,11 +579,10 @@ bool_t mmcDisconnect(MMCDriver *mmcp) {
  *
  * @api
  */
-bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) {
+bool mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) {
 
-  chDbgCheck(mmcp != NULL, "mmcStartSequentialRead");
-  chDbgAssert(mmcp->state == BLK_READY,
-              "mmcStartSequentialRead(), #1", "invalid state");
+  osalDbgCheck(mmcp != NULL);
+  osalDbgAssert(mmcp->state == BLK_READY, "invalid state");
 
   /* Read operation in progress.*/
   mmcp->state = BLK_READING;
@@ -619,10 +617,10 @@ bool_t mmcStartSequentialRead(MMCDriver *mmcp, uint32_t startblk) {
  *
  * @api
  */
-bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) {
+bool mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) {
   int i;
 
-  chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialRead");
+  osalDbgCheck((mmcp != NULL) && (buffer != NULL));
 
   if (mmcp->state != BLK_READING)
     return CH_FAILED;
@@ -654,11 +652,11 @@ bool_t mmcSequentialRead(MMCDriver *mmcp, uint8_t *buffer) {
  *
  * @api
  */
-bool_t mmcStopSequentialRead(MMCDriver *mmcp) {
+bool mmcStopSequentialRead(MMCDriver *mmcp) {
   static const uint8_t stopcmd[] = {0x40 | MMCSD_CMD_STOP_TRANSMISSION,
                                     0, 0, 0, 0, 1, 0xFF};
 
-  chDbgCheck(mmcp != NULL, "mmcStopSequentialRead");
+  osalDbgCheck(mmcp != NULL);
 
   if (mmcp->state != BLK_READING)
     return CH_FAILED;
@@ -686,11 +684,10 @@ bool_t mmcStopSequentialRead(MMCDriver *mmcp) {
  *
  * @api
  */
-bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) {
+bool mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) {
 
-  chDbgCheck(mmcp != NULL, "mmcStartSequentialWrite");
-  chDbgAssert(mmcp->state == BLK_READY,
-              "mmcStartSequentialWrite(), #1", "invalid state");
+  osalDbgCheck(mmcp != NULL);
+  osalDbgAssert(mmcp->state == BLK_READY, "invalid state");
 
   /* Write operation in progress.*/
   mmcp->state = BLK_WRITING;
@@ -723,11 +720,11 @@ bool_t mmcStartSequentialWrite(MMCDriver *mmcp, uint32_t startblk) {
  *
  * @api
  */
-bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) {
+bool mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) {
   static const uint8_t start[] = {0xFF, 0xFC};
   uint8_t b[1];
 
-  chDbgCheck((mmcp != NULL) && (buffer != NULL), "mmcSequentialWrite");
+  osalDbgCheck((mmcp != NULL) && (buffer != NULL));
 
   if (mmcp->state != BLK_WRITING)
     return CH_FAILED;
@@ -759,10 +756,10 @@ bool_t mmcSequentialWrite(MMCDriver *mmcp, const uint8_t *buffer) {
  *
  * @api
  */
-bool_t mmcStopSequentialWrite(MMCDriver *mmcp) {
+bool mmcStopSequentialWrite(MMCDriver *mmcp) {
   static const uint8_t stop[] = {0xFD, 0xFF};
 
-  chDbgCheck(mmcp != NULL, "mmcStopSequentialWrite");
+  osalDbgCheck(mmcp != NULL);
 
   if (mmcp->state != BLK_WRITING)
     return CH_FAILED;
@@ -786,9 +783,9 @@ bool_t mmcStopSequentialWrite(MMCDriver *mmcp) {
  *
  * @api
  */
-bool_t mmcSync(MMCDriver *mmcp) {
+bool mmcSync(MMCDriver *mmcp) {
 
-  chDbgCheck(mmcp != NULL, "mmcSync");
+  osalDbgCheck(mmcp != NULL);
 
   if (mmcp->state != BLK_READY)
     return CH_FAILED;
@@ -816,9 +813,9 @@ bool_t mmcSync(MMCDriver *mmcp) {
  *
  * @api
  */
-bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip) {
+bool mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip) {
 
-  chDbgCheck((mmcp != NULL) && (bdip != NULL), "mmcGetInfo");
+  osalDbgCheck((mmcp != NULL) && (bdip != NULL));
 
   if (mmcp->state != BLK_READY)
     return CH_FAILED;
@@ -842,9 +839,9 @@ bool_t mmcGetInfo(MMCDriver *mmcp, BlockDeviceInfo *bdip) {
  *
  * @api
  */
-bool_t mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk) {
+bool mmcErase(MMCDriver *mmcp, uint32_t startblk, uint32_t endblk) {
 
-  chDbgCheck((mmcp != NULL), "mmcErase");
+  osalDbgCheck((mmcp != NULL));
 
   /* Erase operation in progress.*/
   mmcp->state = BLK_WRITING;
diff --git a/os/hal/src/mmcsd.c b/os/hal/src/mmcsd.c
deleted file mode 100644
index c83095981..000000000
--- a/os/hal/src/mmcsd.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    mmcsd.c
- * @brief   MMC/SD cards common code.
- *
- * @addtogroup MMCSD
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_MMC_SPI || HAL_USE_SDC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Gets a bit field from a words array.
- * @note    The bit zero is the LSb of the first word.
- *
- * @param[in] data      pointer to the words array
- * @param[in] end       bit offset of the last bit of the field, inclusive
- * @param[in] start     bit offset of the first bit of the field, inclusive
- *
- * @return              The bits field value, left aligned.
- *
- * @notapi
- */
-static uint32_t mmcsd_get_slice(uint32_t *data, uint32_t end, uint32_t start) {
-  unsigned startidx, endidx, startoff;
-  uint32_t endmask;
-
-  chDbgCheck((end >= start) && ((end - start) < 32), "mmcsd_get_slice");
-
-  startidx = start / 32;
-  startoff = start % 32;
-  endidx   = end / 32;
-  endmask  = (1 << ((end % 32) + 1)) - 1;
-
-  /* One or two pieces?*/
-  if (startidx < endidx)
-    return (data[startidx] >> startoff) |               /* Two pieces case. */
-           ((data[endidx] & endmask) << (32 - startoff));
-  return (data[startidx] & endmask) >> startoff;        /* One piece case.  */
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Extract card capacity from a CSD.
- * @details The capacity is returned as number of available blocks.
- *
- * @param[in] csd       the CSD record
- *
- * @return              The card capacity.
- * @retval 0            CSD format error
- */
-uint32_t mmcsdGetCapacity(uint32_t csd[4]) {
-
-  switch (csd[3] >> 30) {
-  uint32_t a, b, c;
-  case 0:
-    /* CSD version 1.0 */
-    a = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_SLICE);
-    b = mmcsd_get_slice(csd, MMCSD_CSD_10_C_SIZE_MULT_SLICE);
-    c = mmcsd_get_slice(csd, MMCSD_CSD_10_READ_BL_LEN_SLICE);
-    return (a + 1) << (b + 2) << (c - 9);       /* 2^9 == MMCSD_BLOCK_SIZE. */
-  case 1:
-    /* CSD version 2.0.*/
-    return 1024 * (mmcsd_get_slice(csd, MMCSD_CSD_20_C_SIZE_SLICE) + 1);
-  default:
-    /* Reserved value detected.*/
-    return 0;
-  }
-}
-
-#endif /* HAL_USE_MMC_SPI || HAL_USE_SDC */
-
-/** @} */
diff --git a/os/hal/src/pal.c b/os/hal/src/pal.c
index 4e6c63d5f..efebc1a94 100644
--- a/os/hal/src/pal.c
+++ b/os/hal/src/pal.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_PAL || defined(__DOXYGEN__)
@@ -69,8 +68,7 @@
  */
 ioportmask_t palReadBus(IOBus *bus) {
 
-  chDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH),
-             "palReadBus");
+  osalDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH));
 
   return palReadGroup(bus->portid, bus->mask, bus->offset);
 }
@@ -95,8 +93,7 @@ ioportmask_t palReadBus(IOBus *bus) {
  */
 void palWriteBus(IOBus *bus, ioportmask_t bits) {
 
-  chDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH),
-             "palWriteBus");
+  osalDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH));
 
   palWriteGroup(bus->portid, bus->mask, bus->offset, bits);
 }
@@ -119,8 +116,7 @@ void palWriteBus(IOBus *bus, ioportmask_t bits) {
  */
 void palSetBusMode(IOBus *bus, iomode_t mode) {
 
-  chDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH),
-             "palSetBusMode");
+  osalDbgCheck((bus != NULL) && (bus->offset < PAL_IOPORTS_WIDTH));
 
   palSetGroupMode(bus->portid, bus->mask, bus->offset, mode);
 }
diff --git a/os/hal/src/pwm.c b/os/hal/src/pwm.c
index c6843a928..dfbe32df3 100644
--- a/os/hal/src/pwm.c
+++ b/os/hal/src/pwm.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_PWM || defined(__DOXYGEN__)
@@ -91,16 +90,16 @@ void pwmObjectInit(PWMDriver *pwmp) {
  */
 void pwmStart(PWMDriver *pwmp, const PWMConfig *config) {
 
-  chDbgCheck((pwmp != NULL) && (config != NULL), "pwmStart");
+  osalDbgCheck((pwmp != NULL) && (config != NULL));
 
-  chSysLock();
-  chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY),
-              "pwmStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY),
+                "invalid state");
   pwmp->config = config;
   pwmp->period = config->period;
   pwm_lld_start(pwmp);
   pwmp->state = PWM_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -112,14 +111,14 @@ void pwmStart(PWMDriver *pwmp, const PWMConfig *config) {
  */
 void pwmStop(PWMDriver *pwmp) {
 
-  chDbgCheck(pwmp != NULL, "pwmStop");
+  osalDbgCheck(pwmp != NULL);
 
-  chSysLock();
-  chDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY),
-              "pwmStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((pwmp->state == PWM_STOP) || (pwmp->state == PWM_READY),
+                "invalid state");
   pwm_lld_stop(pwmp);
   pwmp->state = PWM_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -139,13 +138,12 @@ void pwmStop(PWMDriver *pwmp) {
  */
 void pwmChangePeriod(PWMDriver *pwmp, pwmcnt_t period) {
 
-  chDbgCheck(pwmp != NULL, "pwmChangePeriod");
+  osalDbgCheck(pwmp != NULL);
 
-  chSysLock();
-  chDbgAssert(pwmp->state == PWM_READY,
-              "pwmChangePeriod(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert(pwmp->state == PWM_READY, "invalid state");
   pwmChangePeriodI(pwmp, period);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -166,14 +164,12 @@ void pwmEnableChannel(PWMDriver *pwmp,
                       pwmchannel_t channel,
                       pwmcnt_t width) {
 
-  chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS),
-             "pwmEnableChannel");
+  osalDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS));
 
-  chSysLock();
-  chDbgAssert(pwmp->state == PWM_READY,
-              "pwmEnableChannel(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert(pwmp->state == PWM_READY, "not ready");
   pwm_lld_enable_channel(pwmp, channel, width);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -192,14 +188,12 @@ void pwmEnableChannel(PWMDriver *pwmp,
  */
 void pwmDisableChannel(PWMDriver *pwmp, pwmchannel_t channel) {
 
-  chDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS),
-             "pwmEnableChannel");
+  osalDbgCheck((pwmp != NULL) && (channel < PWM_CHANNELS));
 
-  chSysLock();
-  chDbgAssert(pwmp->state == PWM_READY,
-              "pwmDisableChannel(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert(pwmp->state == PWM_READY, "not ready");
   pwm_lld_disable_channel(pwmp, channel);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 #endif /* HAL_USE_PWM */
diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c
deleted file mode 100644
index e0a1c227b..000000000
--- a/os/hal/src/rtc.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-/*
-   Concepts and parts of this file have been contributed by Uladzimir Pylinsky
-   aka barthess.
- */
-
-/**
- * @file    rtc.c
- * @brief   RTC Driver code.
- *
- * @addtogroup RTC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   RTC Driver initialization.
- * @note    This function is implicitly invoked by @p halInit(), there is
- *          no need to explicitly initialize the driver.
- *
- * @init
- */
-void rtcInit(void) {
-
-  rtc_lld_init();
-}
-
-/**
- * @brief   Set current time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] timespec  pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec) {
-
-  chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcSetTime");
-
-  chSysLock();
-  rtcSetTimeI(rtcp, timespec);
-  chSysUnlock();
-}
-
-/**
- * @brief   Get current time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec) {
-
-  chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcGetTime");
-
-  chSysLock();
-  rtcGetTimeI(rtcp, timespec);
-  chSysUnlock();
-}
-
-#if (RTC_ALARMS > 0) || defined(__DOXYGEN__)
-/**
- * @brief   Set alarm time.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] alarm     alarm identifier
- * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL
- *
- * @api
- */
-void rtcSetAlarm(RTCDriver *rtcp,
-                 rtcalarm_t alarm,
-                 const RTCAlarm *alarmspec) {
-
-  chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS), "rtcSetAlarm");
-
-  chSysLock();
-  rtcSetAlarmI(rtcp, alarm, alarmspec);
-  chSysUnlock();
-}
-
-/**
- * @brief   Get current alarm.
- * @note    If an alarm has not been set then the returned alarm specification
- *          is not meaningful.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] alarm     alarm identifier
- * @param[out] alarmspec pointer to a @p RTCAlarm structure
- *
- * @api
- */
-void rtcGetAlarm(RTCDriver *rtcp,
-                 rtcalarm_t alarm,
-                 RTCAlarm *alarmspec) {
-
-  chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS) && (alarmspec != NULL),
-             "rtcGetAlarm");
-
-  chSysLock();
-  rtcGetAlarmI(rtcp, alarm, alarmspec);
-  chSysUnlock();
-}
-#endif /* RTC_ALARMS > 0 */
-
-#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__)
-/**
- * @brief   Enables or disables RTC callbacks.
- * @details This function enables or disables the callback, use a @p NULL
- *          pointer in order to disable it.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @param[in] callback  callback function pointer or @p NULL
- *
- * @api
- */
-void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback) {
-
-  chDbgCheck((rtcp != NULL), "rtcSetCallback");
-
-  chSysLock();
-  rtcSetCallbackI(rtcp, callback);
-  chSysUnlock();
-}
-#endif /* RTC_SUPPORTS_CALLBACKS */
-
-/**
- * @brief   Get current time in format suitable for usage in FatFS.
- *
- * @param[in] rtcp      pointer to RTC driver structure
- * @return              FAT time value.
- *
- * @api
- */
-uint32_t rtcGetTimeFat(RTCDriver *rtcp) {
-
-  chDbgCheck((rtcp != NULL), "rtcSetTime");
-  return rtc_lld_get_time_fat(rtcp);
-}
-
-#endif /* HAL_USE_RTC */
-
-/** @} */
diff --git a/os/hal/src/sdc.c b/os/hal/src/sdc.c
index f95331d44..d18f37b55 100644
--- a/os/hal/src/sdc.c
+++ b/os/hal/src/sdc.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_SDC || defined(__DOXYGEN__)
@@ -47,14 +46,14 @@
  * @brief   Virtual methods table.
  */
 static const struct SDCDriverVMT sdc_vmt = {
-  (bool_t (*)(void *))sdc_lld_is_card_inserted,
-  (bool_t (*)(void *))sdc_lld_is_write_protected,
-  (bool_t (*)(void *))sdcConnect,
-  (bool_t (*)(void *))sdcDisconnect,
-  (bool_t (*)(void *, uint32_t, uint8_t *, uint32_t))sdcRead,
-  (bool_t (*)(void *, uint32_t, const uint8_t *, uint32_t))sdcWrite,
-  (bool_t (*)(void *))sdcSync,
-  (bool_t (*)(void *, BlockDeviceInfo *))sdcGetInfo
+  (bool (*)(void *))sdc_lld_is_card_inserted,
+  (bool (*)(void *))sdc_lld_is_write_protected,
+  (bool (*)(void *))sdcConnect,
+  (bool (*)(void *))sdcDisconnect,
+  (bool (*)(void *, uint32_t, uint8_t *, uint32_t))sdcRead,
+  (bool (*)(void *, uint32_t, const uint8_t *, uint32_t))sdcWrite,
+  (bool (*)(void *))sdcSync,
+  (bool (*)(void *, BlockDeviceInfo *))sdcGetInfo
 };
 
 /*===========================================================================*/
@@ -67,37 +66,37 @@ static const struct SDCDriverVMT sdc_vmt = {
  * @param[in] sdcp      pointer to the @p SDCDriver object
  *
  * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
  *
  * @notapi
  */
-bool_t _sdc_wait_for_transfer_state(SDCDriver *sdcp) {
+bool _sdc_wait_for_transfer_state(SDCDriver *sdcp) {
   uint32_t resp[1];
 
   while (TRUE) {
     if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_SEND_STATUS,
                                    sdcp->rca, resp) ||
         MMCSD_R1_ERROR(resp[0]))
-      return CH_FAILED;
+      return HAL_FAILED;
     switch (MMCSD_R1_STS(resp[0])) {
     case MMCSD_STS_TRAN:
-      return CH_SUCCESS;
+      return HAL_SUCCESS;
     case MMCSD_STS_DATA:
     case MMCSD_STS_RCV:
     case MMCSD_STS_PRG:
 #if SDC_NICE_WAITING
-      chThdSleepMilliseconds(1);
+      osalThreadSleep(MS2ST(1));
 #endif
       continue;
     default:
       /* The card should have been initialized so any other state is not
          valid and is reported as an error.*/
-      return CH_FAILED;
+      return HAL_FAILED;
     }
   }
   /* If something going too wrong.*/
-  return CH_FAILED;
+  return HAL_FAILED;
 }
 
 /*===========================================================================*/
@@ -144,15 +143,15 @@ void sdcObjectInit(SDCDriver *sdcp) {
  */
 void sdcStart(SDCDriver *sdcp, const SDCConfig *config) {
 
-  chDbgCheck(sdcp != NULL, "sdcStart");
+  osalDbgCheck(sdcp != NULL);
 
-  chSysLock();
-  chDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE),
-              "sdcStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE),
+                "invalid state");
   sdcp->config = config;
   sdc_lld_start(sdcp);
   sdcp->state = BLK_ACTIVE;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -164,14 +163,14 @@ void sdcStart(SDCDriver *sdcp, const SDCConfig *config) {
  */
 void sdcStop(SDCDriver *sdcp) {
 
-  chDbgCheck(sdcp != NULL, "sdcStop");
+  osalDbgCheck(sdcp != NULL);
 
-  chSysLock();
-  chDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE),
-              "sdcStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((sdcp->state == BLK_STOP) || (sdcp->state == BLK_ACTIVE),
+                "invalid state");
   sdc_lld_stop(sdcp);
   sdcp->state = BLK_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -183,17 +182,17 @@ void sdcStop(SDCDriver *sdcp) {
  * @param[in] sdcp      pointer to the @p SDCDriver object
  *
  * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
  *
  * @api
  */
-bool_t sdcConnect(SDCDriver *sdcp) {
+bool sdcConnect(SDCDriver *sdcp) {
   uint32_t resp[1];
 
-  chDbgCheck(sdcp != NULL, "sdcConnect");
-  chDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY),
-              "mmcConnect(), #1", "invalid state");
+  osalDbgCheck(sdcp != NULL);
+  osalDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY),
+                "invalid state");
 
   /* Connection procedure in progress.*/
   sdcp->state = BLK_CONNECTING;
@@ -258,7 +257,7 @@ bool_t sdcConnect(SDCDriver *sdcp) {
       }
       if (++i >= SDC_INIT_RETRY)
         goto failed;
-      chThdSleepMilliseconds(10);
+      osalThreadSleep(MS2ST(10));
     }
   }
 
@@ -311,13 +310,13 @@ bool_t sdcConnect(SDCDriver *sdcp) {
 
   /* Initialization complete.*/
   sdcp->state = BLK_READY;
-  return CH_SUCCESS;
+  return HAL_SUCCESS;
 
   /* Connection failed, state reset to BLK_ACTIVE.*/
 failed:
   sdc_lld_stop_clk(sdcp);
   sdcp->state = BLK_ACTIVE;
-  return CH_FAILED;
+  return HAL_FAILED;
 }
 
 /**
@@ -326,36 +325,36 @@ failed:
  * @param[in] sdcp      pointer to the @p SDCDriver object
  *
  * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
  *
  * @api
  */
-bool_t sdcDisconnect(SDCDriver *sdcp) {
+bool sdcDisconnect(SDCDriver *sdcp) {
 
-  chDbgCheck(sdcp != NULL, "sdcDisconnect");
+  osalDbgCheck(sdcp != NULL);
 
-  chSysLock();
-  chDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY),
-              "sdcDisconnect(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((sdcp->state == BLK_ACTIVE) || (sdcp->state == BLK_READY),
+                "invalid state");
   if (sdcp->state == BLK_ACTIVE) {
-    chSysUnlock();
-    return CH_SUCCESS;
+    osalSysUnlock();
+    return HAL_SUCCESS;
   }
   sdcp->state = BLK_DISCONNECTING;
-  chSysUnlock();
+  osalSysUnlock();
 
   /* Waits for eventual pending operations completion.*/
   if (_sdc_wait_for_transfer_state(sdcp)) {
     sdc_lld_stop_clk(sdcp);
     sdcp->state = BLK_ACTIVE;
-    return CH_FAILED;
+    return HAL_FAILED;
   }
 
   /* Card clock stopped.*/
   sdc_lld_stop_clk(sdcp);
   sdcp->state = BLK_ACTIVE;
-  return CH_SUCCESS;
+  return HAL_SUCCESS;
 }
 
 /**
@@ -369,21 +368,20 @@ bool_t sdcDisconnect(SDCDriver *sdcp) {
  * @param[in] n         number of blocks to read
  *
  * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
  *
  * @api
  */
-bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk,
-               uint8_t *buf, uint32_t n) {
-  bool_t status;
+bool sdcRead(SDCDriver *sdcp, uint32_t startblk, uint8_t *buf, uint32_t n) {
+  bool status;
 
-  chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcRead");
-  chDbgAssert(sdcp->state == BLK_READY, "sdcRead(), #1", "invalid state");
+  osalDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0));
+  osalDbgAssert(sdcp->state == BLK_READY, "invalid state");
 
   if ((startblk + n - 1) > sdcp->capacity){
     sdcp->errors |= SDC_OVERFLOW_ERROR;
-    return CH_FAILED;
+    return HAL_FAILED;
   }
 
   /* Read operation in progress.*/
@@ -407,21 +405,21 @@ bool_t sdcRead(SDCDriver *sdcp, uint32_t startblk,
  * @param[in] n         number of blocks to write
  *
  * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
  *
  * @api
  */
-bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk,
-                const uint8_t *buf, uint32_t n) {
-  bool_t status;
+bool sdcWrite(SDCDriver *sdcp, uint32_t startblk,
+              const uint8_t *buf, uint32_t n) {
+  bool status;
 
-  chDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0), "sdcWrite");
-  chDbgAssert(sdcp->state == BLK_READY, "sdcWrite(), #1", "invalid state");
+  osalDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0));
+  osalDbgAssert(sdcp->state == BLK_READY, "invalid state");
 
   if ((startblk + n - 1) > sdcp->capacity){
     sdcp->errors |= SDC_OVERFLOW_ERROR;
-    return CH_FAILED;
+    return HAL_FAILED;
   }
 
   /* Write operation in progress.*/
@@ -445,14 +443,13 @@ bool_t sdcWrite(SDCDriver *sdcp, uint32_t startblk,
 sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp) {
   sdcflags_t flags;
 
-  chDbgCheck(sdcp != NULL, "sdcGetAndClearErrors");
-  chDbgAssert(sdcp->state == BLK_READY,
-              "sdcGetAndClearErrors(), #1", "invalid state");
+  osalDbgCheck(sdcp != NULL);
+  osalDbgAssert(sdcp->state == BLK_READY, "invalid state");
 
-  chSysLock();
+  osalSysLock();
   flags = sdcp->errors;
   sdcp->errors = SDC_NO_ERROR;
-  chSysUnlock();
+  osalSysUnlock();
   return flags;
 }
 
@@ -462,18 +459,18 @@ sdcflags_t sdcGetAndClearErrors(SDCDriver *sdcp) {
  * @param[in] sdcp      pointer to the @p SDCDriver object
  *
  * @return              The operation status.
- * @retval CH_SUCCESS   the operation succeeded.
- * @retval CH_FAILED    the operation failed.
+ * @retval HAL_SUCCESS  the operation succeeded.
+ * @retval HAL_FAILED   the operation failed.
  *
  * @api
  */
-bool_t sdcSync(SDCDriver *sdcp) {
-  bool_t result;
+bool sdcSync(SDCDriver *sdcp) {
+  bool result;
 
-  chDbgCheck(sdcp != NULL, "sdcSync");
+  osalDbgCheck(sdcp != NULL);
 
   if (sdcp->state != BLK_READY)
-    return CH_FAILED;
+    return HAL_FAILED;
 
   /* Synchronization operation in progress.*/
   sdcp->state = BLK_SYNCING;
@@ -492,22 +489,22 @@ bool_t sdcSync(SDCDriver *sdcp) {
  * @param[out] bdip     pointer to a @p BlockDeviceInfo structure
  *
  * @return              The operation status.
- * @retval CH_SUCCESS   the operation succeeded.
- * @retval CH_FAILED    the operation failed.
+ * @retval HAL_SUCCESS  the operation succeeded.
+ * @retval HAL_FAILED   the operation failed.
  *
  * @api
  */
-bool_t sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip) {
+bool sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip) {
 
-  chDbgCheck((sdcp != NULL) && (bdip != NULL), "sdcGetInfo");
+  osalDbgCheck((sdcp != NULL) && (bdip != NULL));
 
   if (sdcp->state != BLK_READY)
-    return CH_FAILED;
+    return HAL_FAILED;
 
   bdip->blk_num = sdcp->capacity;
   bdip->blk_size = MMCSD_BLOCK_SIZE;
 
-  return CH_SUCCESS;
+  return HAL_SUCCESS;
 }
 
 
@@ -519,16 +516,16 @@ bool_t sdcGetInfo(SDCDriver *sdcp, BlockDeviceInfo *bdip) {
  * @param[in] endblk    ending block number
  *
  * @return              The operation status.
- * @retval CH_SUCCESS   the operation succeeded.
- * @retval CH_FAILED    the operation failed.
+ * @retval HAL_SUCCESS  the operation succeeded.
+ * @retval HAL_FAILED   the operation failed.
  *
  * @api
  */
-bool_t sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk) {
+bool sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk) {
   uint32_t resp[1];
 
-  chDbgCheck((sdcp != NULL), "sdcErase");
-  chDbgAssert(sdcp->state == BLK_READY, "sdcErase(), #1", "invalid state");
+  osalDbgCheck((sdcp != NULL));
+  osalDbgAssert(sdcp->state == BLK_READY, "invalid state");
 
   /* Erase operation in progress.*/
   sdcp->state = BLK_WRITING;
@@ -542,17 +539,17 @@ bool_t sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk) {
   _sdc_wait_for_transfer_state(sdcp);
 
   if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_START,
-                                  startblk, resp) != CH_SUCCESS) ||
+                                  startblk, resp) != HAL_SUCCESS) ||
       MMCSD_R1_ERROR(resp[0]))
     goto failed;
 
   if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE_RW_BLK_END,
-                                  endblk, resp) != CH_SUCCESS) ||
+                                  endblk, resp) != HAL_SUCCESS) ||
       MMCSD_R1_ERROR(resp[0]))
     goto failed;
 
   if ((sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_ERASE,
-                                  0, resp) != CH_SUCCESS) ||
+                                  0, resp) != HAL_SUCCESS) ||
       MMCSD_R1_ERROR(resp[0]))
     goto failed;
 
@@ -563,11 +560,11 @@ bool_t sdcErase(SDCDriver *sdcp, uint32_t startblk, uint32_t endblk) {
   _sdc_wait_for_transfer_state(sdcp);
 
   sdcp->state = BLK_READY;
-  return CH_SUCCESS;
+  return HAL_SUCCESS;
 
 failed:
   sdcp->state = BLK_READY;
-  return CH_FAILED;
+  return HAL_FAILED;
 }
 
 #endif /* HAL_USE_SDC */
diff --git a/os/hal/src/serial.c b/os/hal/src/serial.c
index fdb802ccc..4b1fd17d5 100644
--- a/os/hal/src/serial.c
+++ b/os/hal/src/serial.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_SERIAL || defined(__DOXYGEN__)
@@ -54,44 +53,44 @@
 
 static size_t write(void *ip, const uint8_t *bp, size_t n) {
 
-  return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp,
-                          n, TIME_INFINITE);
+  return oqWriteTimeout(&((SerialDriver *)ip)->oqueue, bp,
+                        n, TIME_INFINITE);
 }
 
 static size_t read(void *ip, uint8_t *bp, size_t n) {
 
-  return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp,
-                         n, TIME_INFINITE);
+  return iqReadTimeout(&((SerialDriver *)ip)->iqueue, bp,
+                       n, TIME_INFINITE);
 }
 
 static msg_t put(void *ip, uint8_t b) {
 
-  return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, TIME_INFINITE);
+  return oqPutTimeout(&((SerialDriver *)ip)->oqueue, b, TIME_INFINITE);
 }
 
 static msg_t get(void *ip) {
 
-  return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, TIME_INFINITE);
+  return iqGetTimeout(&((SerialDriver *)ip)->iqueue, TIME_INFINITE);
 }
 
 static msg_t putt(void *ip, uint8_t b, systime_t timeout) {
 
-  return chOQPutTimeout(&((SerialDriver *)ip)->oqueue, b, timeout);
+  return oqPutTimeout(&((SerialDriver *)ip)->oqueue, b, timeout);
 }
 
 static msg_t gett(void *ip, systime_t timeout) {
 
-  return chIQGetTimeout(&((SerialDriver *)ip)->iqueue, timeout);
+  return iqGetTimeout(&((SerialDriver *)ip)->iqueue, timeout);
 }
 
 static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) {
 
-  return chOQWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, n, time);
+  return oqWriteTimeout(&((SerialDriver *)ip)->oqueue, bp, n, time);
 }
 
 static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) {
 
-  return chIQReadTimeout(&((SerialDriver *)ip)->iqueue, bp, n, time);
+  return iqReadTimeout(&((SerialDriver *)ip)->iqueue, bp, n, time);
 }
 
 static const struct SerialDriverVMT vmt = {
@@ -133,10 +132,10 @@ void sdInit(void) {
 void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify) {
 
   sdp->vmt = &vmt;
-  chEvtInit(&sdp->event);
+  osalEventObjectInit(&sdp->event);
   sdp->state = SD_STOP;
-  chIQInit(&sdp->iqueue, sdp->ib, SERIAL_BUFFERS_SIZE, inotify, sdp);
-  chOQInit(&sdp->oqueue, sdp->ob, SERIAL_BUFFERS_SIZE, onotify, sdp);
+  iqObjectInit(&sdp->iqueue, sdp->ib, SERIAL_BUFFERS_SIZE, inotify, sdp);
+  oqObjectInit(&sdp->oqueue, sdp->ob, SERIAL_BUFFERS_SIZE, onotify, sdp);
 }
 
 /**
@@ -151,15 +150,14 @@ void sdObjectInit(SerialDriver *sdp, qnotify_t inotify, qnotify_t onotify) {
  */
 void sdStart(SerialDriver *sdp, const SerialConfig *config) {
 
-  chDbgCheck(sdp != NULL, "sdStart");
+  osalDbgCheck(sdp != NULL);
 
-  chSysLock();
-  chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY),
-              "sdStart(), #1",
-              "invalid state");
+  osalSysLock();
+  osalDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY),
+                "invalid state");
   sd_lld_start(sdp, config);
   sdp->state = SD_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -173,18 +171,17 @@ void sdStart(SerialDriver *sdp, const SerialConfig *config) {
  */
 void sdStop(SerialDriver *sdp) {
 
-  chDbgCheck(sdp != NULL, "sdStop");
+  osalDbgCheck(sdp != NULL);
 
-  chSysLock();
-  chDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY),
-              "sdStop(), #1",
-              "invalid state");
+  osalSysLock();
+  osalDbgAssert((sdp->state == SD_STOP) || (sdp->state == SD_READY),
+                "invalid state");
   sd_lld_stop(sdp);
   sdp->state = SD_STOP;
-  chOQResetI(&sdp->oqueue);
-  chIQResetI(&sdp->iqueue);
-  chSchRescheduleS();
-  chSysUnlock();
+  oqResetI(&sdp->oqueue);
+  iqResetI(&sdp->iqueue);
+  osalOsRescheduleS();
+  osalSysUnlock();
 }
 
 /**
@@ -205,12 +202,12 @@ void sdStop(SerialDriver *sdp) {
  */
 void sdIncomingDataI(SerialDriver *sdp, uint8_t b) {
 
-  chDbgCheckClassI();
-  chDbgCheck(sdp != NULL, "sdIncomingDataI");
+  osalDbgCheckClassI();
+  osalDbgCheck(sdp != NULL);
 
-  if (chIQIsEmptyI(&sdp->iqueue))
+  if (iqIsEmptyI(&sdp->iqueue))
     chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
-  if (chIQPutI(&sdp->iqueue, b) < Q_OK)
+  if (iqPutI(&sdp->iqueue, b) < Q_OK)
     chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
 }
 
@@ -232,10 +229,10 @@ void sdIncomingDataI(SerialDriver *sdp, uint8_t b) {
 msg_t sdRequestDataI(SerialDriver *sdp) {
   msg_t  b;
 
-  chDbgCheckClassI();
-  chDbgCheck(sdp != NULL, "sdRequestDataI");
+  osalDbgCheckClassI();
+  osalDbgCheck(sdp != NULL);
 
-  b = chOQGetI(&sdp->oqueue);
+  b = oqGetI(&sdp->oqueue);
   if (b < Q_OK)
     chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
   return b;
diff --git a/os/hal/src/serial_usb.c b/os/hal/src/serial_usb.c
index ff6e94b07..7a9476250 100644
--- a/os/hal/src/serial_usb.c
+++ b/os/hal/src/serial_usb.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_SERIAL_USB || defined(__DOXYGEN__)
@@ -61,44 +60,44 @@ static cdc_linecoding_t linecoding = {
 
 static size_t write(void *ip, const uint8_t *bp, size_t n) {
 
-  return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp,
-                          n, TIME_INFINITE);
+  return oqWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp,
+                        n, TIME_INFINITE);
 }
 
 static size_t read(void *ip, uint8_t *bp, size_t n) {
 
-  return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp,
-                         n, TIME_INFINITE);
+  return iqReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp,
+                       n, TIME_INFINITE);
 }
 
 static msg_t put(void *ip, uint8_t b) {
 
-  return chOQPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, TIME_INFINITE);
+  return oqPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, TIME_INFINITE);
 }
 
 static msg_t get(void *ip) {
 
-  return chIQGetTimeout(&((SerialUSBDriver *)ip)->iqueue, TIME_INFINITE);
+  return iqGetTimeout(&((SerialUSBDriver *)ip)->iqueue, TIME_INFINITE);
 }
 
 static msg_t putt(void *ip, uint8_t b, systime_t timeout) {
 
-  return chOQPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, timeout);
+  return oqPutTimeout(&((SerialUSBDriver *)ip)->oqueue, b, timeout);
 }
 
 static msg_t gett(void *ip, systime_t timeout) {
 
-  return chIQGetTimeout(&((SerialUSBDriver *)ip)->iqueue, timeout);
+  return iqGetTimeout(&((SerialUSBDriver *)ip)->iqueue, timeout);
 }
 
 static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t time) {
 
-  return chOQWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp, n, time);
+  return oqWriteTimeout(&((SerialUSBDriver *)ip)->oqueue, bp, n, time);
 }
 
 static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t time) {
 
-  return chIQReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp, n, time);
+  return iqReadTimeout(&((SerialUSBDriver *)ip)->iqueue, bp, n, time);
 }
 
 static const struct SerialUSBDriverVMT vmt = {
@@ -109,9 +108,9 @@ static const struct SerialUSBDriverVMT vmt = {
 /**
  * @brief   Notification of data removed from the input queue.
  */
-static void inotify(GenericQueue *qp) {
+static void inotify(io_queue_t *qp) {
   size_t n, maxsize;
-  SerialUSBDriver *sdup = chQGetLink(qp);
+  SerialUSBDriver *sdup = qGetLink(qp);
 
   /* If the USB driver is not in the appropriate state then transactions
      must not be started.*/
@@ -124,15 +123,15 @@ static void inotify(GenericQueue *qp) {
      the available space.*/
   maxsize = sdup->config->usbp->epc[sdup->config->bulk_out]->out_maxsize;
   if (!usbGetReceiveStatusI(sdup->config->usbp, sdup->config->bulk_out) &&
-      ((n = chIQGetEmptyI(&sdup->iqueue)) >= maxsize)) {
-    chSysUnlock();
+      ((n = iqGetEmptyI(&sdup->iqueue)) >= maxsize)) {
+    osalSysUnlock();
 
     n = (n / maxsize) * maxsize;
     usbPrepareQueuedReceive(sdup->config->usbp,
                             sdup->config->bulk_out,
                             &sdup->iqueue, n);
 
-    chSysLock();
+    osalSysLock();
     usbStartReceiveI(sdup->config->usbp, sdup->config->bulk_out);
   }
 }
@@ -140,9 +139,9 @@ static void inotify(GenericQueue *qp) {
 /**
  * @brief   Notification of data inserted into the output queue.
  */
-static void onotify(GenericQueue *qp) {
+static void onotify(io_queue_t *qp) {
   size_t n;
-  SerialUSBDriver *sdup = chQGetLink(qp);
+  SerialUSBDriver *sdup = qGetLink(qp);
 
   /* If the USB driver is not in the appropriate state then transactions
      must not be started.*/
@@ -153,14 +152,14 @@ static void onotify(GenericQueue *qp) {
   /* If there is not an ongoing transaction and the output queue contains
      data then a new transaction is started.*/
   if (!usbGetTransmitStatusI(sdup->config->usbp, sdup->config->bulk_in) &&
-      ((n = chOQGetFullI(&sdup->oqueue)) > 0)) {
-    chSysUnlock();
+      ((n = oqGetFullI(&sdup->oqueue)) > 0)) {
+    osalSysUnlock();
 
     usbPrepareQueuedTransmit(sdup->config->usbp,
                              sdup->config->bulk_in,
                              &sdup->oqueue, n);
 
-    chSysLock();
+    osalSysLock();
     usbStartTransmitI(sdup->config->usbp, sdup->config->bulk_in);
   }
 }
@@ -191,10 +190,10 @@ void sduInit(void) {
 void sduObjectInit(SerialUSBDriver *sdup) {
 
   sdup->vmt = &vmt;
-  chEvtInit(&sdup->event);
+  osalEventObjectInit(&sdup->event);
   sdup->state = SDU_STOP;
-  chIQInit(&sdup->iqueue, sdup->ib, SERIAL_USB_BUFFERS_SIZE, inotify, sdup);
-  chOQInit(&sdup->oqueue, sdup->ob, SERIAL_USB_BUFFERS_SIZE, onotify, sdup);
+  iqObjectInit(&sdup->iqueue, sdup->ib, SERIAL_USB_BUFFERS_SIZE, inotify, sdup);
+  oqObjectInit(&sdup->oqueue, sdup->ob, SERIAL_USB_BUFFERS_SIZE, onotify, sdup);
 }
 
 /**
@@ -208,18 +207,17 @@ void sduObjectInit(SerialUSBDriver *sdup) {
 void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config) {
   USBDriver *usbp = config->usbp;
 
-  chDbgCheck(sdup != NULL, "sduStart");
+  osalDbgCheck(sdup != NULL);
 
-  chSysLock();
-  chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY),
-              "sduStart(), #1",
-              "invalid state");
+  osalSysLock();
+  osalDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY),
+                "invalid state");
   usbp->in_params[config->bulk_in - 1]   = sdup;
   usbp->out_params[config->bulk_out - 1] = sdup;
   usbp->in_params[config->int_in - 1]    = sdup;
   sdup->config = config;
   sdup->state = SDU_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -234,13 +232,12 @@ void sduStart(SerialUSBDriver *sdup, const SerialUSBConfig *config) {
 void sduStop(SerialUSBDriver *sdup) {
   USBDriver *usbp = sdup->config->usbp;
 
-  chDbgCheck(sdup != NULL, "sdStop");
+  osalDbgCheck(sdup != NULL);
 
-  chSysLock();
+  osalSysLock();
 
-  chDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY),
-              "sduStop(), #1",
-              "invalid state");
+  osalDbgAssert((sdup->state == SDU_STOP) || (sdup->state == SDU_READY),
+                "invalid state");
 
   /* Driver in stopped state.*/
   usbp->in_params[sdup->config->bulk_in - 1]   = NULL;
@@ -250,11 +247,11 @@ void sduStop(SerialUSBDriver *sdup) {
 
   /* Queues reset in order to signal the driver stop to the application.*/
   chnAddFlagsI(sdup, CHN_DISCONNECTED);
-  chIQResetI(&sdup->iqueue);
-  chOQResetI(&sdup->oqueue);
-  chSchRescheduleS();
+  iqResetI(&sdup->iqueue);
+  iqResetI(&sdup->oqueue);
+  osalOsRescheduleS();
 
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -267,8 +264,8 @@ void sduStop(SerialUSBDriver *sdup) {
 void sduConfigureHookI(SerialUSBDriver *sdup) {
   USBDriver *usbp = sdup->config->usbp;
 
-  chIQResetI(&sdup->iqueue);
-  chOQResetI(&sdup->oqueue);
+  iqResetI(&sdup->iqueue);
+  oqResetI(&sdup->oqueue);
   chnAddFlagsI(sdup, CHN_CONNECTED);
 
   /* Starts the first OUT transaction immediately.*/
@@ -292,7 +289,7 @@ void sduConfigureHookI(SerialUSBDriver *sdup) {
  * @retval TRUE         Message handled internally.
  * @retval FALSE        Message not handled.
  */
-bool_t sduRequestsHook(USBDriver *usbp) {
+bool sduRequestsHook(USBDriver *usbp) {
 
   if ((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) {
     switch (usbp->setup[1]) {
@@ -328,17 +325,17 @@ void sduDataTransmitted(USBDriver *usbp, usbep_t ep) {
   if (sdup == NULL)
     return;
 
-  chSysLockFromIsr();
+  osalSysLockFromISR();
   chnAddFlagsI(sdup, CHN_OUTPUT_EMPTY);
 
-  if ((n = chOQGetFullI(&sdup->oqueue)) > 0) {
+  if ((n = oqGetFullI(&sdup->oqueue)) > 0) {
     /* The endpoint cannot be busy, we are in the context of the callback,
        so it is safe to transmit without a check.*/
-    chSysUnlockFromIsr();
+    osalSysUnlockFromISR();
 
     usbPrepareQueuedTransmit(usbp, ep, &sdup->oqueue, n);
 
-    chSysLockFromIsr();
+    osalSysLockFromISR();
     usbStartTransmitI(usbp, ep);
   }
   else if ((usbp->epc[ep]->in_state->txsize > 0) &&
@@ -348,15 +345,15 @@ void sduDataTransmitted(USBDriver *usbp, usbep_t ep) {
        size. Otherwise the recipient may expect more data coming soon and
        not return buffered data to app. See section 5.8.3 Bulk Transfer
        Packet Size Constraints of the USB Specification document.*/
-    chSysUnlockFromIsr();
+    osalSysUnlockFromISR();
 
     usbPrepareQueuedTransmit(usbp, ep, &sdup->oqueue, 0);
 
-    chSysLockFromIsr();
+    osalSysLockFromISR();
     usbStartTransmitI(usbp, ep);
   }
 
-  chSysUnlockFromIsr();
+  osalSysUnlockFromISR();
 }
 
 /**
@@ -374,25 +371,25 @@ void sduDataReceived(USBDriver *usbp, usbep_t ep) {
   if (sdup == NULL)
     return;
 
-  chSysLockFromIsr();
+  osalSysLockFromISR();
   chnAddFlagsI(sdup, CHN_INPUT_AVAILABLE);
 
   /* Writes to the input queue can only happen when there is enough space
      to hold at least one packet.*/
   maxsize = usbp->epc[ep]->out_maxsize;
-  if ((n = chIQGetEmptyI(&sdup->iqueue)) >= maxsize) {
+  if ((n = iqGetEmptyI(&sdup->iqueue)) >= maxsize) {
     /* The endpoint cannot be busy, we are in the context of the callback,
        so a packet is in the buffer for sure.*/
-    chSysUnlockFromIsr();
+    osalSysUnlockFromISR();
 
     n = (n / maxsize) * maxsize;
     usbPrepareQueuedReceive(usbp, ep, &sdup->iqueue, n);
 
-    chSysLockFromIsr();
+    osalSysLockFromISR();
     usbStartReceiveI(usbp, ep);
   }
 
-  chSysUnlockFromIsr();
+  osalSysUnlockFromISR();
 }
 
 /**
diff --git a/os/hal/src/spi.c b/os/hal/src/spi.c
index 2dc0cc6ee..f47ed0527 100644
--- a/os/hal/src/spi.c
+++ b/os/hal/src/spi.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_SPI || defined(__DOXYGEN__)
@@ -78,11 +77,7 @@ void spiObjectInit(SPIDriver *spip) {
   spip->thread = NULL;
 #endif /* SPI_USE_WAIT */
 #if SPI_USE_MUTUAL_EXCLUSION
-#if CH_USE_MUTEXES
-  chMtxInit(&spip->mutex);
-#else
-  chSemInit(&spip->semaphore, 1);
-#endif
+  osalMutexObjectInit(&spip->mutex);
 #endif /* SPI_USE_MUTUAL_EXCLUSION */
 #if defined(SPI_DRIVER_EXT_INIT_HOOK)
   SPI_DRIVER_EXT_INIT_HOOK(spip);
@@ -99,15 +94,15 @@ void spiObjectInit(SPIDriver *spip) {
  */
 void spiStart(SPIDriver *spip, const SPIConfig *config) {
 
-  chDbgCheck((spip != NULL) && (config != NULL), "spiStart");
+  osalDbgCheck((spip != NULL) && (config != NULL));
 
-  chSysLock();
-  chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY),
-              "spiStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY),
+                "invalid state");
   spip->config = config;
   spi_lld_start(spip);
   spip->state = SPI_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -121,14 +116,14 @@ void spiStart(SPIDriver *spip, const SPIConfig *config) {
  */
 void spiStop(SPIDriver *spip) {
 
-  chDbgCheck(spip != NULL, "spiStop");
+  osalDbgCheck(spip != NULL);
 
-  chSysLock();
-  chDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY),
-              "spiStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((spip->state == SPI_STOP) || (spip->state == SPI_READY),
+                "invalid state");
   spi_lld_stop(spip);
   spip->state = SPI_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -140,12 +135,12 @@ void spiStop(SPIDriver *spip) {
  */
 void spiSelect(SPIDriver *spip) {
 
-  chDbgCheck(spip != NULL, "spiSelect");
+  osalDbgCheck(spip != NULL);
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiSelect(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
   spiSelectI(spip);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -158,12 +153,12 @@ void spiSelect(SPIDriver *spip) {
  */
 void spiUnselect(SPIDriver *spip) {
 
-  chDbgCheck(spip != NULL, "spiUnselect");
+  osalDbgCheck(spip != NULL);
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiUnselect(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
   spiUnselectI(spip);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -181,12 +176,12 @@ void spiUnselect(SPIDriver *spip) {
  */
 void spiStartIgnore(SPIDriver *spip, size_t n) {
 
-  chDbgCheck((spip != NULL) && (n > 0), "spiStartIgnore");
+  osalDbgCheck((spip != NULL) && (n > 0));
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiStartIgnore(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
   spiStartIgnoreI(spip, n);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -209,13 +204,12 @@ void spiStartIgnore(SPIDriver *spip, size_t n) {
 void spiStartExchange(SPIDriver *spip, size_t n,
                       const void *txbuf, void *rxbuf) {
 
-  chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL),
-             "spiStartExchange");
+  osalDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL));
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiStartExchange(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
   spiStartExchangeI(spip, n, txbuf, rxbuf);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -235,13 +229,12 @@ void spiStartExchange(SPIDriver *spip, size_t n,
  */
 void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf) {
 
-  chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL),
-             "spiStartSend");
+  osalDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL));
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiStartSend(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
   spiStartSendI(spip, n, txbuf);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -261,13 +254,12 @@ void spiStartSend(SPIDriver *spip, size_t n, const void *txbuf) {
  */
 void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf) {
 
-  chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL),
-             "spiStartReceive");
+  osalDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL));
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiStartReceive(), #1", "not ready");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
   spiStartReceiveI(spip, n, rxbuf);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 #if SPI_USE_WAIT || defined(__DOXYGEN__)
@@ -287,14 +279,14 @@ void spiStartReceive(SPIDriver *spip, size_t n, void *rxbuf) {
  */
 void spiIgnore(SPIDriver *spip, size_t n) {
 
-  chDbgCheck((spip != NULL) && (n > 0), "spiIgnoreWait");
+  osalDbgCheck((spip != NULL) && (n > 0));
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiIgnore(), #1", "not ready");
-  chDbgAssert(spip->config->end_cb == NULL, "spiIgnore(), #2", "has callback");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
+  osalDbgAssert(spip->config->end_cb == NULL, "has callback");
   spiStartIgnoreI(spip, n);
   _spi_wait_s(spip);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -318,16 +310,15 @@ void spiIgnore(SPIDriver *spip, size_t n) {
 void spiExchange(SPIDriver *spip, size_t n,
                  const void *txbuf, void *rxbuf) {
 
-  chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL) && (txbuf != NULL),
-             "spiExchange");
+  osalDbgCheck((spip != NULL) && (n > 0) &&
+               (rxbuf != NULL) && (txbuf != NULL));
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiExchange(), #1", "not ready");
-  chDbgAssert(spip->config->end_cb == NULL,
-              "spiExchange(), #2", "has callback");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
+  osalDbgAssert(spip->config->end_cb == NULL, "has callback");
   spiStartExchangeI(spip, n, txbuf, rxbuf);
   _spi_wait_s(spip);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -348,14 +339,14 @@ void spiExchange(SPIDriver *spip, size_t n,
  */
 void spiSend(SPIDriver *spip, size_t n, const void *txbuf) {
 
-  chDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL), "spiSend");
+  osalDbgCheck((spip != NULL) && (n > 0) && (txbuf != NULL));
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiSend(), #1", "not ready");
-  chDbgAssert(spip->config->end_cb == NULL, "spiSend(), #2", "has callback");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
+  osalDbgAssert(spip->config->end_cb == NULL, "has callback");
   spiStartSendI(spip, n, txbuf);
   _spi_wait_s(spip);
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -376,16 +367,14 @@ void spiSend(SPIDriver *spip, size_t n, const void *txbuf) {
  */
 void spiReceive(SPIDriver *spip, size_t n, void *rxbuf) {
 
-  chDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL),
-             "spiReceive");
+  osalDbgCheck((spip != NULL) && (n > 0) && (rxbuf != NULL));
 
-  chSysLock();
-  chDbgAssert(spip->state == SPI_READY, "spiReceive(), #1", "not ready");
-  chDbgAssert(spip->config->end_cb == NULL,
-              "spiReceive(), #2", "has callback");
+  osalSysLock();
+  osalDbgAssert(spip->state == SPI_READY, "not ready");
+  osalDbgAssert(spip->config->end_cb == NULL, "has callback");
   spiStartReceiveI(spip, n, rxbuf);
   _spi_wait_s(spip);
-  chSysUnlock();
+  osalSysUnlock();
 }
 #endif /* SPI_USE_WAIT */
 
@@ -403,13 +392,9 @@ void spiReceive(SPIDriver *spip, size_t n, void *rxbuf) {
  */
 void spiAcquireBus(SPIDriver *spip) {
 
-  chDbgCheck(spip != NULL, "spiAcquireBus");
+  osalDbgCheck(spip != NULL);
 
-#if CH_USE_MUTEXES
-  chMtxLock(&spip->mutex);
-#elif CH_USE_SEMAPHORES
-  chSemWait(&spip->semaphore);
-#endif
+  osalMutexLock(&spip->mutex);
 }
 
 /**
@@ -423,14 +408,9 @@ void spiAcquireBus(SPIDriver *spip) {
  */
 void spiReleaseBus(SPIDriver *spip) {
 
-  chDbgCheck(spip != NULL, "spiReleaseBus");
+  osalDbgCheck(spip != NULL);
 
-#if CH_USE_MUTEXES
-  (void)spip;
-  chMtxUnlock();
-#elif CH_USE_SEMAPHORES
-  chSemSignal(&spip->semaphore);
-#endif
+  osalMutexUnlock(&spip->mutex);
 }
 #endif /* SPI_USE_MUTUAL_EXCLUSION */
 
diff --git a/os/hal/src/st.c b/os/hal/src/st.c
new file mode 100644
index 000000000..afb4466fa
--- /dev/null
+++ b/os/hal/src/st.c
@@ -0,0 +1,136 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    st.c
+ * @brief   ST Driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   ST Driver initialization.
+ * @note    This function is implicitly invoked by @p halInit(), there is
+ *          no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void stInit(void) {
+
+  st_lld_init();
+}
+
+
+/**
+ * @brief   Starts the alarm.
+ * @note    Makes sure that no spurious alarms are triggered after
+ *          this call.
+ * @note    This functionality is only available in free running mode, the
+ *          behavior in periodic mode is undefined.
+ *
+ * @param[in] time      the time to be set for the first alarm
+ *
+ * @api
+ */
+void stStartAlarm(systime_t time) {
+
+  osalDbgAssert(stIsAlarmActive() == false, "already active");
+
+  st_lld_start_alarm(time);
+}
+
+/**
+ * @brief   Stops the alarm interrupt.
+ * @note    This functionality is only available in free running mode, the
+ *          behavior in periodic mode is undefined.
+ *
+ * @api
+ */
+void stStopAlarm(void) {
+
+  osalDbgAssert(stIsAlarmActive() != false, "not active");
+
+  st_lld_stop_alarm();
+}
+
+/**
+ * @brief   Sets the alarm time.
+ * @note    This functionality is only available in free running mode, the
+ *          behavior in periodic mode is undefined.
+ *
+ * @param[in] time      the time to be set for the next alarm
+ *
+ * @api
+ */
+void stSetAlarm(systime_t time) {
+
+  osalDbgAssert(stIsAlarmActive() != false, "not active");
+
+  st_lld_set_alarm(time);
+}
+
+/**
+ * @brief   Returns the current alarm time.
+ * @note    This functionality is only available in free running mode, the
+ *          behavior in periodic mode is undefined.
+ *
+ * @return              The currently set alarm time.
+ *
+ * @api
+ */
+systime_t stGetAlarm(void) {
+
+  osalDbgAssert(stIsAlarmActive() != false, "not active");
+
+  return st_lld_get_alarm();
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/os/hal/src/tm.c b/os/hal/src/tm.c
deleted file mode 100644
index 5b002cd90..000000000
--- a/os/hal/src/tm.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    tm.c
- * @brief   Time Measurement driver code.
- *
- * @addtogroup TM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_TM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Subsystem calibration value.
- */
-static halrtcnt_t measurement_offset;
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Starts a measurement.
- *
- * @param[in,out] tmp   pointer to a @p TimeMeasurement structure
- *
- * @notapi
- */
-static void tm_start(TimeMeasurement *tmp) {
-
-  tmp->last = halGetCounterValue();
-}
-
-/**
- * @brief   Stops a measurement.
- *
- * @param[in,out] tmp   pointer to a @p TimeMeasurement structure
- *
- * @notapi
- */
-static void tm_stop(TimeMeasurement *tmp) {
-
-  halrtcnt_t now = halGetCounterValue();
-  tmp->last = now - tmp->last - measurement_offset;
-  if (tmp->last > tmp->worst)
-      tmp->worst = tmp->last;
-  else if (tmp->last < tmp->best)
-      tmp->best = tmp->last;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes the Time Measurement unit.
- *
- * @init
- */
-void tmInit(void) {
-  TimeMeasurement tm;
-
-  /* Time Measurement subsystem calibration, it does a null measurement
-     and calculates the call overhead which is subtracted to real
-     measurements.*/
-  measurement_offset = 0;
-  tmObjectInit(&tm);
-  tmStartMeasurement(&tm);
-  tmStopMeasurement(&tm);
-  measurement_offset = tm.last;
-}
-
-/**
- * @brief   Initializes a @p TimeMeasurement object.
- *
- * @param[out] tmp      pointer to a @p TimeMeasurement structure
- *
- * @init
- */
-void tmObjectInit(TimeMeasurement *tmp) {
-
-  tmp->start = tm_start;
-  tmp->stop  = tm_stop;
-  tmp->last  = (halrtcnt_t)0;
-  tmp->worst = (halrtcnt_t)0;
-  tmp->best  = (halrtcnt_t)-1;
-}
-
-#endif /* HAL_USE_TM */
-
-/** @} */
diff --git a/os/hal/src/uart.c b/os/hal/src/uart.c
index 71869538d..a25b594aa 100644
--- a/os/hal/src/uart.c
+++ b/os/hal/src/uart.c
@@ -26,7 +26,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 #if HAL_USE_UART || defined(__DOXYGEN__)
@@ -92,16 +91,16 @@ void uartObjectInit(UARTDriver *uartp) {
  */
 void uartStart(UARTDriver *uartp, const UARTConfig *config) {
 
-  chDbgCheck((uartp != NULL) && (config != NULL), "uartStart");
+  osalDbgCheck((uartp != NULL) && (config != NULL));
 
-  chSysLock();
-  chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY),
-              "uartStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY),
+                "invalid state");
 
   uartp->config = config;
   uart_lld_start(uartp);
   uartp->state = UART_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -113,17 +112,17 @@ void uartStart(UARTDriver *uartp, const UARTConfig *config) {
  */
 void uartStop(UARTDriver *uartp) {
 
-  chDbgCheck(uartp != NULL, "uartStop");
+  osalDbgCheck(uartp != NULL);
 
-  chSysLock();
-  chDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY),
-              "uartStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((uartp->state == UART_STOP) || (uartp->state == UART_READY),
+                "invalid state");
 
   uart_lld_stop(uartp);
   uartp->state = UART_STOP;
   uartp->txstate = UART_TX_IDLE;
   uartp->rxstate = UART_RX_IDLE;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -139,18 +138,15 @@ void uartStop(UARTDriver *uartp) {
  */
 void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf) {
 
-  chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL),
-             "uartStartSend");
+  osalDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL));
              
-  chSysLock();
-  chDbgAssert(uartp->state == UART_READY,
-              "uartStartSend(), #1", "is active");
-  chDbgAssert(uartp->txstate != UART_TX_ACTIVE,
-              "uartStartSend(), #2", "tx active");
+  osalSysLock();
+  osalDbgAssert(uartp->state == UART_READY, "is active");
+  osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active");
 
   uart_lld_start_send(uartp, n, txbuf);
   uartp->txstate = UART_TX_ACTIVE;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -167,13 +163,10 @@ void uartStartSend(UARTDriver *uartp, size_t n, const void *txbuf) {
  */
 void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf) {
 
-  chDbgCheckClassI();
-  chDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL),
-             "uartStartSendI");
-  chDbgAssert(uartp->state == UART_READY,
-              "uartStartSendI(), #1", "is active");
-  chDbgAssert(uartp->txstate != UART_TX_ACTIVE,
-              "uartStartSendI(), #2", "tx active");
+  osalDbgCheckClassI();
+  osalDbgCheck((uartp != NULL) && (n > 0) && (txbuf != NULL));
+  osalDbgAssert(uartp->state == UART_READY, "is active");
+  osalDbgAssert(uartp->txstate != UART_TX_ACTIVE, "tx active");
 
   uart_lld_start_send(uartp, n, txbuf);
   uartp->txstate = UART_TX_ACTIVE;
@@ -194,10 +187,10 @@ void uartStartSendI(UARTDriver *uartp, size_t n, const void *txbuf) {
 size_t uartStopSend(UARTDriver *uartp) {
   size_t n;
 
-  chDbgCheck(uartp != NULL, "uartStopSend");
+  osalDbgCheck(uartp != NULL);
 
-  chSysLock();
-  chDbgAssert(uartp->state == UART_READY, "uartStopSend(), #1", "not active");
+  osalSysLock();
+  osalDbgAssert(uartp->state == UART_READY, "not active");
 
   if (uartp->txstate == UART_TX_ACTIVE) {
     n = uart_lld_stop_send(uartp);
@@ -205,7 +198,7 @@ size_t uartStopSend(UARTDriver *uartp) {
   }
   else
     n = 0;
-  chSysUnlock();
+  osalSysUnlock();
   return n;
 }
 
@@ -224,9 +217,9 @@ size_t uartStopSend(UARTDriver *uartp) {
  */
 size_t uartStopSendI(UARTDriver *uartp) {
 
-  chDbgCheckClassI();
-  chDbgCheck(uartp != NULL, "uartStopSendI");
-  chDbgAssert(uartp->state == UART_READY, "uartStopSendI(), #1", "not active");
+  osalDbgCheckClassI();
+  osalDbgCheck(uartp != NULL);
+  osalDbgAssert(uartp->state == UART_READY, "not active");
 
   if (uartp->txstate == UART_TX_ACTIVE) {
     size_t n = uart_lld_stop_send(uartp);
@@ -249,18 +242,15 @@ size_t uartStopSendI(UARTDriver *uartp) {
  */
 void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf) {
 
-  chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL),
-             "uartStartReceive");
+  osalDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL));
 
-  chSysLock();
-  chDbgAssert(uartp->state == UART_READY,
-              "uartStartReceive(), #1", "is active");
-  chDbgAssert(uartp->rxstate != UART_RX_ACTIVE,
-              "uartStartReceive(), #2", "rx active");
+  osalSysLock();
+  osalDbgAssert(uartp->state == UART_READY, "is active");
+  osalDbgAssert(uartp->rxstate != UART_RX_ACTIVE, "rx active");
 
   uart_lld_start_receive(uartp, n, rxbuf);
   uartp->rxstate = UART_RX_ACTIVE;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -277,13 +267,10 @@ void uartStartReceive(UARTDriver *uartp, size_t n, void *rxbuf) {
  */
 void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf) {
 
-  chDbgCheckClassI();
-  chDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL),
-             "uartStartReceiveI");
-  chDbgAssert(uartp->state == UART_READY,
-              "uartStartReceiveI(), #1", "is active");
-  chDbgAssert(uartp->rxstate != UART_RX_ACTIVE,
-              "uartStartReceiveI(), #2", "rx active");
+  osalDbgCheckClassI();
+  osalDbgCheck((uartp != NULL) && (n > 0) && (rxbuf != NULL));
+  osalDbgAssert(uartp->state == UART_READY, "is active");
+  osalDbgAssert(uartp->rxstate != UART_RX_ACTIVE, "rx active");
 
   uart_lld_start_receive(uartp, n, rxbuf);
   uartp->rxstate = UART_RX_ACTIVE;
@@ -304,11 +291,10 @@ void uartStartReceiveI(UARTDriver *uartp, size_t n, void *rxbuf) {
 size_t uartStopReceive(UARTDriver *uartp) {
   size_t n;
 
-  chDbgCheck(uartp != NULL, "uartStopReceive");
+  osalDbgCheck(uartp != NULL);
 
-  chSysLock();
-  chDbgAssert(uartp->state == UART_READY,
-              "uartStopReceive(), #1", "not active");
+  osalSysLock();
+  osalDbgAssert(uartp->state == UART_READY, "not active");
 
   if (uartp->rxstate == UART_RX_ACTIVE) {
     n = uart_lld_stop_receive(uartp);
@@ -316,7 +302,7 @@ size_t uartStopReceive(UARTDriver *uartp) {
   }
   else
     n = 0;
-  chSysUnlock();
+  osalSysUnlock();
   return n;
 }
 
@@ -335,10 +321,9 @@ size_t uartStopReceive(UARTDriver *uartp) {
  */
 size_t uartStopReceiveI(UARTDriver *uartp) {
 
-  chDbgCheckClassI();
-  chDbgCheck(uartp != NULL, "uartStopReceiveI");
-  chDbgAssert(uartp->state == UART_READY,
-              "uartStopReceiveI(), #1", "not active");
+  osalDbgCheckClassI();
+  osalDbgCheck(uartp != NULL);
+  osalDbgAssert(uartp->state == UART_READY, "not active");
 
   if (uartp->rxstate == UART_RX_ACTIVE) {
     size_t n = uart_lld_stop_receive(uartp);
diff --git a/os/hal/src/usb.c b/os/hal/src/usb.c
index b0a6390e7..9b292b7d9 100644
--- a/os/hal/src/usb.c
+++ b/os/hal/src/usb.c
@@ -28,9 +28,7 @@
 
 #include <string.h>
 
-#include "ch.h"
 #include "hal.h"
-#include "usb.h"
 
 #if HAL_USE_USB || defined(__DOXYGEN__)
 
@@ -79,7 +77,7 @@ static void set_address(USBDriver *usbp) {
  * @retval FALSE        Request not recognized by the handler or error.
  * @retval TRUE         Request handled.
  */
-static bool_t default_handler(USBDriver *usbp) {
+static bool default_handler(USBDriver *usbp) {
   const USBDescriptor *dp;
 
   /* Decoding the request.*/
@@ -261,17 +259,17 @@ void usbObjectInit(USBDriver *usbp) {
 void usbStart(USBDriver *usbp, const USBConfig *config) {
   unsigned i;
 
-  chDbgCheck((usbp != NULL) && (config != NULL), "usbStart");
+  osalDbgCheck((usbp != NULL) && (config != NULL));
 
-  chSysLock();
-  chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY),
-              "usbStart(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY),
+                "invalid state");
   usbp->config = config;
   for (i = 0; i <= USB_MAX_ENDPOINTS; i++)
     usbp->epc[i] = NULL;
   usb_lld_start(usbp);
   usbp->state = USB_READY;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -283,15 +281,15 @@ void usbStart(USBDriver *usbp, const USBConfig *config) {
  */
 void usbStop(USBDriver *usbp) {
 
-  chDbgCheck(usbp != NULL, "usbStop");
+  osalDbgCheck(usbp != NULL);
 
-  chSysLock();
-  chDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY) ||
-              (usbp->state == USB_SELECTED) || (usbp->state == USB_ACTIVE),
-              "usbStop(), #1", "invalid state");
+  osalSysLock();
+  osalDbgAssert((usbp->state == USB_STOP) || (usbp->state == USB_READY) ||
+                (usbp->state == USB_SELECTED) || (usbp->state == USB_ACTIVE),
+                "invalid state");
   usb_lld_stop(usbp);
   usbp->state = USB_STOP;
-  chSysUnlock();
+  osalSysUnlock();
 }
 
 /**
@@ -310,12 +308,11 @@ void usbStop(USBDriver *usbp) {
 void usbInitEndpointI(USBDriver *usbp, usbep_t ep,
                       const USBEndpointConfig *epcp) {
 
-  chDbgCheckClassI();
-  chDbgCheck((usbp != NULL) && (epcp != NULL), "usbInitEndpointI");
-  chDbgAssert(usbp->state == USB_ACTIVE,
-              "usbEnableEndpointI(), #1", "invalid state");
-  chDbgAssert(usbp->epc[ep] == NULL,
-              "usbEnableEndpointI(), #2", "already initialized");
+  osalDbgCheckClassI();
+  osalDbgCheck((usbp != NULL) && (epcp != NULL));
+  osalDbgAssert(usbp->state == USB_ACTIVE,
+                "invalid state");
+  osalDbgAssert(usbp->epc[ep] == NULL, "already initialized");
 
   /* Logically enabling the endpoint in the USBDriver structure.*/
   if (epcp->in_state != NULL)
@@ -343,10 +340,9 @@ void usbInitEndpointI(USBDriver *usbp, usbep_t ep,
 void usbDisableEndpointsI(USBDriver *usbp) {
   unsigned i;
 
-  chDbgCheckClassI();
-  chDbgCheck(usbp != NULL, "usbDisableEndpointsI");
-  chDbgAssert(usbp->state == USB_SELECTED,
-              "usbDisableEndpointsI(), #1", "invalid state");
+  osalDbgCheckClassI();
+  osalDbgCheck(usbp != NULL);
+  osalDbgAssert(usbp->state == USB_SELECTED, "invalid state");
 
   usbp->transmitting &= ~1;
   usbp->receiving    &= ~1;
@@ -424,7 +420,7 @@ void usbPrepareTransmit(USBDriver *usbp, usbep_t ep,
  * @special
  */
 void usbPrepareQueuedReceive(USBDriver *usbp, usbep_t ep,
-                             InputQueue *iqp, size_t n) {
+                             input_queue_t *iqp, size_t n) {
   USBOutEndpointState *osp = usbp->epc[ep]->out_state;
 
   osp->rxqueued           = TRUE;
@@ -450,7 +446,7 @@ void usbPrepareQueuedReceive(USBDriver *usbp, usbep_t ep,
  * @special
  */
 void usbPrepareQueuedTransmit(USBDriver *usbp, usbep_t ep,
-                              OutputQueue *oqp, size_t n) {
+                              output_queue_t *oqp, size_t n) {
   USBInEndpointState *isp = usbp->epc[ep]->in_state;
 
   isp->txqueued           = TRUE;
@@ -475,10 +471,10 @@ void usbPrepareQueuedTransmit(USBDriver *usbp, usbep_t ep,
  *
  * @iclass
  */
-bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep) {
+bool usbStartReceiveI(USBDriver *usbp, usbep_t ep) {
 
-  chDbgCheckClassI();
-  chDbgCheck(usbp != NULL, "usbStartReceiveI");
+  osalDbgCheckClassI();
+  osalDbgCheck(usbp != NULL);
 
   if (usbGetReceiveStatusI(usbp, ep))
     return TRUE;
@@ -502,10 +498,10 @@ bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep) {
  *
  * @iclass
  */
-bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep) {
+bool usbStartTransmitI(USBDriver *usbp, usbep_t ep) {
 
-  chDbgCheckClassI();
-  chDbgCheck(usbp != NULL, "usbStartTransmitI");
+  osalDbgCheckClassI();
+  osalDbgCheck(usbp != NULL);
 
   if (usbGetTransmitStatusI(usbp, ep))
     return TRUE;
@@ -527,10 +523,10 @@ bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep) {
  *
  * @iclass
  */
-bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep) {
+bool usbStallReceiveI(USBDriver *usbp, usbep_t ep) {
 
-  chDbgCheckClassI();
-  chDbgCheck(usbp != NULL, "usbStallReceiveI");
+  osalDbgCheckClassI();
+  osalDbgCheck(usbp != NULL);
 
   if (usbGetReceiveStatusI(usbp, ep))
     return TRUE;
@@ -551,10 +547,10 @@ bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep) {
  *
  * @iclass
  */
-bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep) {
+bool usbStallTransmitI(USBDriver *usbp, usbep_t ep) {
 
-  chDbgCheckClassI();
-  chDbgCheck(usbp != NULL, "usbStallTransmitI");
+  osalDbgCheckClassI();
+  osalDbgCheck(usbp != NULL);
 
   if (usbGetTransmitStatusI(usbp, ep))
     return TRUE;
@@ -646,9 +642,9 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
       /* Starts the transmit phase.*/
       usbp->ep0state = USB_EP0_TX;
       usbPrepareTransmit(usbp, 0, usbp->ep0next, usbp->ep0n);
-      chSysLockFromIsr();
+      osalSysLockFromISR();
       usbStartTransmitI(usbp, 0);
-      chSysUnlockFromIsr();
+      osalSysUnlockFromISR();
     }
     else {
       /* No transmission phase, directly receiving the zero sized status
@@ -656,9 +652,9 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
       usbp->ep0state = USB_EP0_WAITING_STS;
 #if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
       usbPrepareReceive(usbp, 0, NULL, 0);
-      chSysLockFromIsr();
+      osalSysLockFromISR();
       usbStartReceiveI(usbp, 0);
-      chSysUnlockFromIsr();
+      osalSysUnlockFromISR();
 #else
       usb_lld_end_setup(usbp, ep);
 #endif
@@ -670,9 +666,9 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
       /* Starts the receive phase.*/
       usbp->ep0state = USB_EP0_RX;
       usbPrepareReceive(usbp, 0, usbp->ep0next, usbp->ep0n);
-      chSysLockFromIsr();
+      osalSysLockFromISR();
       usbStartReceiveI(usbp, 0);
-      chSysUnlockFromIsr();
+      osalSysUnlockFromISR();
     }
     else {
       /* No receive phase, directly sending the zero sized status
@@ -680,9 +676,9 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
       usbp->ep0state = USB_EP0_SENDING_STS;
 #if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
       usbPrepareTransmit(usbp, 0, NULL, 0);
-      chSysLockFromIsr();
+      osalSysLockFromISR();
       usbStartTransmitI(usbp, 0);
-      chSysUnlockFromIsr();
+      osalSysUnlockFromISR();
 #else
       usb_lld_end_setup(usbp, ep);
 #endif
@@ -712,9 +708,9 @@ void _usb_ep0in(USBDriver *usbp, usbep_t ep) {
        transmitted.*/
     if ((usbp->ep0n < max) && ((usbp->ep0n % usbp->epc[0]->in_maxsize) == 0)) {
       usbPrepareTransmit(usbp, 0, NULL, 0);
-      chSysLockFromIsr();
+      osalSysLockFromISR();
       usbStartTransmitI(usbp, 0);
-      chSysUnlockFromIsr();
+      osalSysUnlockFromISR();
       usbp->ep0state = USB_EP0_WAITING_TX0;
       return;
     }
@@ -724,9 +720,9 @@ void _usb_ep0in(USBDriver *usbp, usbep_t ep) {
     usbp->ep0state = USB_EP0_WAITING_STS;
 #if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
     usbPrepareReceive(usbp, 0, NULL, 0);
-    chSysLockFromIsr();
+    osalSysLockFromISR();
     usbStartReceiveI(usbp, 0);
-    chSysUnlockFromIsr();
+    osalSysUnlockFromISR();
 #else
     usb_lld_end_setup(usbp, ep);
 #endif
@@ -768,9 +764,9 @@ void _usb_ep0out(USBDriver *usbp, usbep_t ep) {
     usbp->ep0state = USB_EP0_SENDING_STS;
 #if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
     usbPrepareTransmit(usbp, 0, NULL, 0);
-    chSysLockFromIsr();
+    osalSysLockFromISR();
     usbStartTransmitI(usbp, 0);
-    chSysUnlockFromIsr();
+    osalSysUnlockFromISR();
 #else
     usb_lld_end_setup(usbp, ep);
 #endif
diff --git a/os/hal/templates/adc_lld.c b/os/hal/templates/adc_lld.c
deleted file mode 100644
index e6826d9ed..000000000
--- a/os/hal/templates/adc_lld.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/adc_lld.c
- * @brief   ADC Driver subsystem low level driver source template.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ADC1 driver identifier.
- */
-#if PLATFORM_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if PLATFORM_ADC_USE_ADC1
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-#endif /* PLATFORM_ADC_USE_ADC1 */
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  if (adcp->state == ADC_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-
-    }
-#endif /* PLATFORM_ADC_USE_ADC1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  if (adcp->state == ADC_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-
-    }
-#endif /* PLATFORM_ADC_USE_ADC1 */
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-
-  (void)adcp;
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-  (void)adcp;
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/templates/adc_lld.h b/os/hal/templates/adc_lld.h
deleted file mode 100644
index c7b4ca9cf..000000000
--- a/os/hal/templates/adc_lld.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/adc_lld.h
- * @brief   ADC Driver subsystem low level driver header template.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(PLATFORM_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define PLATFORM_ADC_USE_ADC1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
-  ADC_ERR_OVERFLOW = 1                      /**< ADC overflow condition.    */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief   Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief   Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief   Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief   Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief   Waiting thread.
-   */
-  Thread                    *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the peripheral.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/can_lld.c b/os/hal/templates/can_lld.c
deleted file mode 100644
index d095a645e..000000000
--- a/os/hal/templates/can_lld.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/can_lld.c
- * @brief   CAN Driver subsystem low level driver source template.
- *
- * @addtogroup CAN
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   CAN1 driver identifier.
- */
-#if PLATFORM_CAN_USE_CAN1 || defined(__DOXYGEN__)
-CANDriver CAND1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level CAN driver initialization.
- *
- * @notapi
- */
-void can_lld_init(void) {
-
-#if PLATFORM_CAN_USE_CAN1
-  /* Driver initialization.*/
-  canObjectInit(&CAND1);
-#endif /* PLATFORM_CAN_USE_CAN1 */
-}
-
-/**
- * @brief   Configures and activates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_start(CANDriver *canp) {
-
-  if (canp->state == CAN_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_CAN_USE_CAN1
-    if (&CAND1 == canp) {
-
-    }
-#endif /* PLATFORM_CAN_USE_CAN1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the CAN peripheral.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_stop(CANDriver *canp) {
-
-  if (canp->state == CAN_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_CAN_USE_CAN1
-    if (&CAND1 == canp) {
-
-    }
-#endif /* PLATFORM_CAN_USE_CAN1 */
-  }
-}
-
-/**
- * @brief   Determines whether a frame can be transmitted.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return              The queue space availability.
- * @retval FALSE        no space in the transmit queue.
- * @retval TRUE         transmit slot available.
- *
- * @notapi
- */
-bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
-
-  (void)canp;
-
-  switch (mailbox) {
-  case CAN_ANY_MAILBOX:
-    return FALSE;
-  case 1:
-    return FALSE;
-  case 2:
-    return FALSE;
-  case 3:
-    return FALSE;
-  default:
-    return FALSE;
-  }
-}
-
-/**
- * @brief   Inserts a frame into the transmit queue.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] ctfp      pointer to the CAN frame to be transmitted
- * @param[in] mailbox   mailbox number,  @p CAN_ANY_MAILBOX for any mailbox
- *
- * @notapi
- */
-void can_lld_transmit(CANDriver *canp,
-                      canmbx_t mailbox,
-                      const CANTxFrame *ctfp) {
-
-  (void)canp;
-  (void)mailbox;
-  (void)ctfp;
-
-}
-
-/**
- * @brief   Determines whether a frame has been received.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- *
- * @return              The queue space availability.
- * @retval FALSE        no space in the transmit queue.
- * @retval TRUE         transmit slot available.
- *
- * @notapi
- */
-bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
-
-  (void)canp;
-  (void)mailbox;
-
-  switch (mailbox) {
-  case CAN_ANY_MAILBOX:
-    return FALSE;
-  case 1:
-    return FALSE;
-  case 2:
-    return FALSE;
-  default:
-    return FALSE;
-  }
-}
-
-/**
- * @brief   Receives a frame from the input queue.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
- * @param[out] crfp     pointer to the buffer where the CAN frame is copied
- *
- * @notapi
- */
-void can_lld_receive(CANDriver *canp,
-                     canmbx_t mailbox,
-                     CANRxFrame *crfp) {
-
-  (void)canp;
-  (void)mailbox;
-  (void)crfp;
-
-}
-
-#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
-/**
- * @brief   Enters the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_sleep(CANDriver *canp) {
-
-  (void)canp;
-
-}
-
-/**
- * @brief   Enforces leaving the sleep mode.
- *
- * @param[in] canp      pointer to the @p CANDriver object
- *
- * @notapi
- */
-void can_lld_wakeup(CANDriver *canp) {
-
-  (void)canp;
-
-}
-#endif /* CAN_USE_SLEEP_MODE */
-
-#endif /* HAL_USE_CAN */
-
-/** @} */
diff --git a/os/hal/templates/can_lld.h b/os/hal/templates/can_lld.h
deleted file mode 100644
index bfa9bb1e5..000000000
--- a/os/hal/templates/can_lld.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/can_lld.h
- * @brief   CAN Driver subsystem low level driver header template.
- *
- * @addtogroup CAN
- * @{
- */
-
-#ifndef _CAN_LLD_H_
-#define _CAN_LLD_H_
-
-#if HAL_USE_CAN || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   This switch defines whether the driver implementation supports
- *          a low power switch mode with automatic an wakeup feature.
- */
-#define CAN_SUPPORTS_SLEEP          TRUE
-
-/**
- * @brief   This implementation supports three transmit mailboxes.
- */
-#define CAN_TX_MAILBOXES            3
-
-/**
- * @brief   This implementation supports two receive mailboxes.
- */
-#define CAN_RX_MAILBOXES            2
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   CAN1 driver enable switch.
- * @details If set to @p TRUE the support for CAN1 is included.
- */
-#if !defined(PLATFORM_CAN_USE_CAN1) || defined(__DOXYGEN__)
-#define PLATFORM_CAN_USE_CAN1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
-#error "CAN sleep mode not supported in this architecture"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a transmission mailbox index.
- */
-typedef uint32_t canmbx_t;
-
-/**
- * @brief   CAN transmission frame.
- * @note    Accessing the frame data as word16 or word32 is not portable because
- *          machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
-  struct {
-    uint8_t                 DLC:4;          /**< @brief Data length.        */
-    uint8_t                 RTR:1;          /**< @brief Frame type.         */
-    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t              SID:11;         /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t              EID:29;         /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t                 data8[8];       /**< @brief Frame data.         */
-    uint16_t                data16[4];      /**< @brief Frame data.         */
-    uint32_t                data32[2];      /**< @brief Frame data.         */
-  };
-} CANTxFrame;
-
-/**
- * @brief   CAN received frame.
- * @note    Accessing the frame data as word16 or word32 is not portable because
- *          machine data endianness, it can be still useful for a quick filling.
- */
-typedef struct {
-  struct {
-    uint8_t                 DLC:4;          /**< @brief Data length.        */
-    uint8_t                 RTR:1;          /**< @brief Frame type.         */
-    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
-  };
-  union {
-    struct {
-      uint32_t              SID:11;         /**< @brief Standard identifier.*/
-    };
-    struct {
-      uint32_t              EID:29;         /**< @brief Extended identifier.*/
-    };
-  };
-  union {
-    uint8_t                 data8[8];       /**< @brief Frame data.         */
-    uint16_t                data16[4];      /**< @brief Frame data.         */
-    uint32_t                data32[2];      /**< @brief Frame data.         */
-  };
-} CANRxFrame;
-
-/**
- * @brief   CAN filter.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- * @note    It could not be present on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} CANFilter;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} CANConfig;
-
-/**
- * @brief   Structure representing an CAN driver.
- */
-typedef struct {
-  /**
-   * @brief   Driver state.
-   */
-  canstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const CANConfig           *config;
-  /**
-   * @brief   Transmission queue semaphore.
-   */
-  Semaphore                 txsem;
-  /**
-   * @brief   Receive queue semaphore.
-   */
-  Semaphore                 rxsem;
-  /**
-   * @brief   One or more frames become available.
-   * @note    After broadcasting this event it will not be broadcasted again
-   *          until the received frames queue has been completely emptied. It
-   *          is <b>not</b> broadcasted for each received frame. It is
-   *          responsibility of the application to empty the queue by
-   *          repeatedly invoking @p chReceive() when listening to this event.
-   *          This behavior minimizes the interrupt served by the system
-   *          because CAN traffic.
-   * @note    The flags associated to the listeners will indicate which
-   *          receive mailboxes become non-empty.
-   */
-  EventSource               rxfull_event;
-  /**
-   * @brief   One or more transmission mailbox become available.
-   * @note    The flags associated to the listeners will indicate which
-   *          transmit mailboxes become empty.
-   *
-   */
-  EventSource               txempty_event;
-  /**
-   * @brief   A CAN bus error happened.
-   * @note    The flags associated to the listeners will indicate the
-   *          error(s) that have occurred.
-   */
-  EventSource               error_event;
-#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
-  /**
-   * @brief   Entering sleep state event.
-   */
-  EventSource               sleep_event;
-  /**
-   * @brief   Exiting sleep state event.
-   */
-  EventSource               wakeup_event;
-#endif /* CAN_USE_SLEEP_MODE */
-  /* End of the mandatory fields.*/
-} CANDriver;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_CAN_USE_CAN1 && !defined(__DOXYGEN__)
-extern CANDriver CAND1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void can_lld_init(void);
-  void can_lld_start(CANDriver *canp);
-  void can_lld_stop(CANDriver *canp);
-  bool_t can_lld_is_tx_empty(CANDriver *canp,
-                             canmbx_t mailbox);
-  void can_lld_transmit(CANDriver *canp,
-                        canmbx_t mailbox,
-                        const CANTxFrame *crfp);
-  bool_t can_lld_is_rx_nonempty(CANDriver *canp,
-                                canmbx_t mailbox);
-  void can_lld_receive(CANDriver *canp,
-                       canmbx_t mailbox,
-                       CANRxFrame *ctfp);
-#if CAN_USE_SLEEP_MODE
-  void can_lld_sleep(CANDriver *canp);
-  void can_lld_wakeup(CANDriver *canp);
-#endif /* CAN_USE_SLEEP_MODE */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_CAN */
-
-#endif /* _CAN_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/dac_lld.c b/os/hal/templates/dac_lld.c
deleted file mode 100644
index d5ff63da2..000000000
--- a/os/hal/templates/dac_lld.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    STM32F37x/dac_lld.c
- * @brief   STM32F37x DAC subsystem low level driver source.
- *
- * @addtogroup DAC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#if !defined(DAC1)
-#define DAC1 DAC
-#define rccEnableDAC1 rccEnableDAC
-#define rccDisableDAC1 rccDisableDAC
-#endif
-
-#define DAC_CHN1_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_DAC_CHN1_DMA_STREAM,                            \
-                       STM32_DAC_CHN1_DMA_CHN)
-
-#define DAC_CHN2_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_DAC_CHN2_DMA_STREAM,                            \
-                       STM32_DAC_CHN2_DMA_CHN)
-           
-#define DAC_CHN3_DMA_CHANNEL                                                 \
-  STM32_DMA_GETCHANNEL(STM32_DAC_CHN3_DMA_STREAM,                            \
-                       STM32_DAC_CHN3_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief CHN1 driver identifier.*/
-#if STM32_DAC_USE_CHN1 || defined(__DOXYGEN__)
-DACDriver DACD1;
-#endif
-
-/** @brief CHN2 driver identifier.*/
-#if STM32_DAC_USE_CHN2 || defined(__DOXYGEN__)
-DACDriver DACD2;
-#endif
-
-/** @brief CHN3 driver identifier.*/
-#if STM32_DAC_USE_CHN3 || defined(__DOXYGEN__)
-DACDriver DACD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-
-/**
- * @brief   Shared end/half-of-tx service routine.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
-#if defined(STM32_DAC_DMA_ERROR_HOOK)
-  (void)dacp;
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    /* DMA errors handling.*/
-    _dac_isr_error_code(dacp);
-  }
-  else {
-    if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-      /* Half transfer processing.*/
-      _dac_isr_half_code(dacp);
-    }
-    if ((flags & STM32_DMA_ISR_TCIF) != 0) {
-      /* Transfer complete processing.*/
-      _dac_isr_full_code(dacp);
-    }
-  }
-#else
-  (void)dacp;
-  (void)flags;
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level DAC driver initialization.
- *
- * @notapi
- */
-void dac_lld_init(void) {
-
-#if STM32_DAC_USE_CHN1
-  dacObjectInit(&DACD1);
-  DACD1.dac     = DAC1;
-  DACD1.tim     = STM32_TIM6;
-  DACD1.irqprio = STM32_DAC_CHN1_IRQ_PRIORITY;
-  DACD1.dma     = STM32_DMA_STREAM(STM32_DAC_CHN1_DMA_STREAM);
-  DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN1_DMA_CHANNEL) |                  \
-                  STM32_DMA_CR_PL(STM32_DAC_CHN1_DMA_PRIORITY) |              \
-                  STM32_DMA_CR_DIR_M2P |                                      \
-                  STM32_DMA_CR_DMEIE |                                        \
-                  STM32_DMA_CR_TEIE |                                         \
-                  STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
-#endif
-
-#if STM32_DAC_USE_CHN2
-  dacObjectInit(&DACD2);
-  DACD2.dac     = DAC1;
-  DACD2.tim     = STM32_TIM7;
-  DACD2.irqprio = STM32_DAC_CHN2_IRQ_PRIORITY;
-  DACD2.dma     = STM32_DMA_STREAM(STM32_DAC_CHN2_DMA_STREAM);
-  DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN2_DMA_CHANNEL) |                  \
-                  STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) |              \
-                  STM32_DMA_CR_DIR_M2P |                                      \
-                  STM32_DMA_CR_DMEIE |                                        \
-                  STM32_DMA_CR_TEIE |                                         \
-                  STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
-#endif
-
-#if STM32_DAC_USE_CHN3
-  dacObjectInit(&DACD3);
-  DACD3.dac     = DAC2;
-  DACD3.tim     = STM32_TIM18;
-  DACD3.irqprio = STM32_DAC_CHN3_IRQ_PRIORITY;
-  DACD3.dma     = STM32_DMA_STREAM(STM32_DAC_CHN3_DMA_STREAM);
-  DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN3_DMA_CHANNEL) |                  \
-                  STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) |              \
-                  STM32_DMA_CR_DIR_M2P |                                      \
-                  STM32_DMA_CR_DMEIE |                                        \
-                  STM32_DMA_CR_TEIE |                                         \
-                  STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
-#endif
-}
-
-/**
- * @brief   Configures and activates the DAC peripheral.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_start(DACDriver *dacp) {
-  uint32_t arr, regshift, trgo, dataoffset;
-  bool_t b;
-  /* If in stopped state then enables the DAC and DMA clocks.*/
-  if (dacp->state == DAC_STOP) {
-#if STM32_DAC_USE_CHN1
-    if (&DACD1 == dacp) {
-      rccEnableDAC1(FALSE);
-      /* DAC1 CR data is at bits 0:15 */
-      regshift = 0;
-      dataoffset = 0;
-      /* Timer setup */
-      rccEnableTIM6(FALSE);
-      rccResetTIM6();
-      trgo = STM32_DAC_CR_TSEL_TIM6;
-    }
-#endif
-#if STM32_DAC_USE_CHN2
-    if (&DACD2 == dacp) {
-      rccEnableDAC1(FALSE);
-      /* DAC2 CR data is at bits 16:31 */
-      regshift = 16;
-      dataoffset = &dacp->dac->DHR12R2 - &dacp->dac->DHR12R1;
-      /* Timer setup */
-      rccEnableTIM7(FALSE);
-      rccResetTIM7();
-      trgo = STM32_DAC_CR_TSEL_TIM7;
-    }
-#endif
-#if STM32_DAC_USE_CHN3
-    if (&DACD3 == dacp) {
-      rccEnableDAC2(FALSE);
-      /* DAC3 CR data is at bits 0:15 */
-      regshift = 0;
-      dataoffset = 0;
-      /* Timer setup */
-      rccEnableTIM18(FALSE);
-      rccResetTIM18();
-      trgo = STM32_DAC_CR_TSEL_TIM18;
-    }
-#endif
-#if STM32_DAC_USE_CHN1 || STM32_DAC_USE_CHN2 || STM32_DAC_USE_CHN3
-    dacp->clock = STM32_TIMCLK1;
-    arr = (dacp->clock / dacp->config->frequency);
-    chDbgAssert((arr <= 0xFFFF),
-        "dac_lld_start(), #1", "invalid frequency");
-
-    /* Timer configuration.*/
-    dacp->tim->CR1  = 0;                        /* Initially stopped.   */
-    dacp->tim->PSC  = 0;                        /* Prescaler value.     */
-    dacp->tim->DIER = 0;
-    dacp->tim->ARR  = arr;
-    dacp->tim->EGR  = TIM_EGR_UG;               /* Update event.        */
-    dacp->tim->CR2  &= (uint16_t)~TIM_CR2_MMS;
-    dacp->tim->CR2  |= (uint16_t)TIM_CR2_MMS_1; /* Enable TRGO updates. */
-    dacp->tim->CNT  = 0;                        /* Reset counter.       */
-    dacp->tim->SR   = 0;                        /* Clear pending IRQs.  */
-    /* Update Event IRQ enabled. */
-    /* Timer start.*/
-    dacp->tim->CR1  = TIM_CR1_CEN;
-
-    /* DAC configuration */
-    dacp->dac->CR |= ( (dacp->dac->CR & ~STM32_DAC_CR_MASK) | \
-      (STM32_DAC_CR_EN | STM32_DAC_CR_DMAEN | dacp->config->cr_flags) ) << regshift;
-      
-    /* DMA setup. */
-    b = dmaStreamAllocate(dacp->dma,
-          dacp->irqprio,
-          (stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
-          (void *)dacp);
-    chDbgAssert(!b, "dac_lld_start(), #2", "stream already allocated");
-    switch (dacp->config->dhrm) {
-      /* Sets the DAC data register */
-      case DAC_DHRM_12BIT_RIGHT:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12R1 + dataoffset);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-        break;
-      case DAC_DHRM_12BIT_LEFT:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12L1 + dataoffset);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-        break;
-      case DAC_DHRM_8BIT_RIGHT:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8R1 + dataoffset);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-        break;
-#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2
-      case DAC_DHRM_12BIT_RIGHT_DUAL:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12RD);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-        break;
-      case DAC_DHRM_12BIT_LEFT_DUAL:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12LD);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-              STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-        break;
-      case DAC_DHRM_8BIT_RIGHT_DUAL:
-        dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8RD);
-        dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
-             STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-        break;
-#endif
-  }
-  
-  dacp->dac->CR |= trgo << regshift; /* Enable trigger */
-#endif
-  }
-}
-
-/**
- * @brief   Deactivates the DAC peripheral.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_stop(DACDriver *dacp) {
-
-  /* If in ready state then disables the DAC clock.*/
-  if (dacp->state == DAC_READY) {
-
-    /* DMA disable.*/
-    dmaStreamRelease(dacp->dma);
-
-#if STM32_DAC_USE_CHN1
-    if (&DACD1 == dacp) {
-      dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC1 disable.*/
-    }
-#endif
-#if STM32_DAC_USE_CHN2
-    if (&DACD2 == dacp) {
-      dacp->dac->CR &= ~STM32_DAC_CR_EN << 16; /* DAC1 disable.*/
-    }
-#endif
-#if STM32_DAC_USE_CHN3
-    if (&DACD3 == dacp) {
-      dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC2 disable.*/
-      rccDisableDAC2(FALSE); /* DAC Clock disable.*/
-    }
-#endif
-    dacp->tim->CR1 &= ~TIM_CR1_CEN; /* Disable associated timer */
-    dacp->state = DAC_STOP;
-
-    if (!(DAC1->CR & (STM32_DAC_CR_EN | STM32_DAC_CR_EN << 16))) {
-      /* DAC Clock disable only if all channels are off.*/
-      rccDisableDAC1(FALSE);
-    }
-  }
-}
-
-/**
- * @brief   Sends data over the DAC bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- *
- * @param[in] dacp      pointer to the @p DACDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void dac_lld_send(DACDriver *dacp) {
-  chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #1", 
-    "First buffer is NULL pointer");
-  dmaStreamSetMemory0(dacp->dma, dacp->config->buffer1);
-  dmaStreamSetTransactionSize(dacp->dma, dacp->config->buffers_size);
-  dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN);
-}
-
-void dac_lld_send_continuous(DACDriver *dacp){
-  chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #1", 
-    "First buffer is NULL pointer");
-  dmaStreamSetMemory0(dacp->dma, dacp->config->buffer1);
-  dmaStreamSetTransactionSize(dacp->dma, dacp->config->buffers_size);
-  dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN |                \
-                   STM32_DMA_CR_CIRC);
-}
-#if defined(STM32_ADVANCED_DMA) && STM32_ADVANCED_DMA
-void dac_lld_send_doublebuffer(DACDriver *dacp) {
-  chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #1", 
-    "First buffer is NULL pointer");
-  chDbgAssert(dacp->config->buffer1, "dac_lld_send_doublebuffer(), #2", 
-    "Second buffer is NULL pointer");
-  dmaStreamSetMemory0(dacp->dma, dacp->config->buffer1);
-  dmaStreamSetMemory1(dacp->dma, dacp->config->buffer2);
-  dmaStreamSetTransactionSize(dacp->dma, dacp->config->buffers_size);
-  dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN |               \
-                   STM32_DMA_CR_DBM);
-}
-#else
-void dac_lld_send_doublebuffer(DACDriver *dacp) { 
-  (void)dacp;
-  chDbgAssert(0, "dac_lld_send_doublebuffer(), #1", 
-    "This DMA mode is not supported by your hardware.");
-};
-#endif
-
-#endif /* HAL_USE_DAC */
-
-/** @} */
diff --git a/os/hal/templates/dac_lld.h b/os/hal/templates/dac_lld.h
deleted file mode 100644
index c9cb13fc6..000000000
--- a/os/hal/templates/dac_lld.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    STM32F37x/dac_lld.h
- * @brief   STM32F37x DAC subsystem low level driver header.
- *
- * @addtogroup DAC
- * @{
- */
-
-#ifndef _DAC_LLD_H_
-#define _DAC_LLD_H_
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   DAC1 driver enable switch.
- * @details If set to @p TRUE the support for DAC1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(PLATFORM_DAC_USE_DAC1) || defined(__DOXYGEN__)
-#define PLATFORM_DAC_USE_DAC1               FALSE
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DAC sample data type.
- */
-typedef uint16_t dacsample_t;
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t dac_channels_num_t;
-
-/**
- * @brief   Possible DAC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  DAC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
-  DAC_ERR_UNDERRUN = 1                      /**< ADC overflow condition.    */
-} dacerror_t;
-
-/**
- * @brief   Type of a structure representing an DAC driver.
- */
-typedef struct DACDriver DACDriver;
-
-/**
- * @brief   DAC notification callback type.
- *
- * @param[in] dacp      pointer to the @p DACDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*daccallback_t)(DACDriver *dacp, dacsample_t *buffer, size_t n);
-
-/**
- * @brief   DAC error callback type.
- *
- * @param[in] dacp      pointer to the @p DACDriver object triggering the
- *                      callback
- * @param[in] err       DAC error code
- */
-typedef void (*dacerrorcallback_t)(DACDriver *dacp, dacerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool_t                    circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  dac_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  daccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  dacerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-} DACConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} DACConfig;
-
-/**
- * @brief   Structure representing a DAC driver.
- */
-struct DACDriver {
-  /**
-   * @brief Driver state.
-   */
-  dacstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const DACConfig           *config;
-  /**
-   * @brief   Current samples buffer pointer or @p NULL.
-   */
-  const dacsample_t         *samples;
-  /**
-   * @brief   Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief   Current conversion group pointer or @p NULL.
-   */
-  const DACConversionGroup  *grpp;
-#if DAC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                    *thread;
-#endif /* DAC_USE_WAIT */
-#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* DAC_USE_MUTUAL_EXCLUSION */
-#if defined(DAC_DRIVER_EXT_FIELDS)
-  DAC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_DAC_USE_DAC1 && !defined(__DOXYGEN__)
-extern DACDriver DACD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dac_lld_init(void);
-  void dac_lld_start(DACDriver *dacp);
-  void dac_lld_stop(DACDriver *dacp);
-  void dac_lld_send(DACDriver *dacp);
-  void dac_lld_start_conversion(DACDriver *dacp);
-  void dac_lld_stop_conversion(DACDriver *dacp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_DAC */
-
-#endif /* _DAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/ext_lld.c b/os/hal/templates/ext_lld.c
deleted file mode 100644
index e6e79e952..000000000
--- a/os/hal/templates/ext_lld.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/ext_lld.c
- * @brief   EXT Driver subsystem low level driver source template.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXT1 driver identifier.
- */
-#if PLATFORM_EXT_USE_EXT1 || defined(__DOXYGEN__)
-EXTDriver EXTD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
-#if PLATFORM_EXT_USE_EXT1
-  /* Driver initialization.*/
-  extObjectInit(&EXTD1);
-#endif /* PLATFORM_EXT_USE_EXT1 */
-}
-
-/**
- * @brief   Configures and activates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
-
-  if (extp->state == EXT_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_EXT_USE_EXT1
-    if (&EXTD1 == extp) {
-
-    }
-#endif /* PLATFORM_EXT_USE_EXT1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-
-  if (extp->state == EXT_ACTIVE) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_EXT_USE_EXT1
-    if (&EXTD1 == extp) {
-
-    }
-#endif /* PLATFORM_EXT_USE_EXT1 */
-  }
-}
-
-/**
- * @brief   Enables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
-  (void)extp;
-  (void)channel;
-
-}
-
-/**
- * @brief   Disables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-
-  (void)extp;
-  (void)channel;
-
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/templates/ext_lld.h b/os/hal/templates/ext_lld.h
deleted file mode 100644
index ca020a7a6..000000000
--- a/os/hal/templates/ext_lld.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/ext_lld.h
- * @brief   EXT Driver subsystem low level driver header template.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_H_
-#define _EXT_LLD_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Available number of EXT channels.
- */
-#define EXT_MAX_CHANNELS    20
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   EXT driver enable switch.
- * @details If set to @p TRUE the support for EXT1 is included.
- */
-#if !defined(PLATFORM_EXT_USE_EXT1) || defined(__DOXYGEN__)
-#define PLATFORM_EXT_USE_EXT1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief   Type of an EXT generic notification callback.
- *
- * @param[in] extp      pointer to the @p EXPDriver object triggering the
- *                      callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief   Channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel mode.
-   */
-  uint32_t              mode;
-  /**
-   * @brief Channel callback.
-   * @details  In the STM32 implementation a @p NULL callback pointer is
-   *           valid and configures the channel as an event sources instead
-   *           of an interrupt source.
-   */
-  extcallback_t         cb;
-} EXTChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief Channel configurations.
-   */
-  EXTChannelConfig      channels[EXT_MAX_CHANNELS];
-  /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief   Structure representing an EXT driver.
- */
-struct EXTDriver {
-  /**
-   * @brief Driver state.
-   */
-  extstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const EXTConfig           *config;
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_EXT_USE_EXT1 && !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_init(void);
-  void ext_lld_start(EXTDriver *extp);
-  void ext_lld_stop(EXTDriver *extp);
-  void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
-  void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/gpt_lld.c b/os/hal/templates/gpt_lld.c
deleted file mode 100644
index 4f16b0239..000000000
--- a/os/hal/templates/gpt_lld.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/gpt_lld.c
- * @brief   GPT Driver subsystem low level driver source template.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   GPTD1 driver identifier.
- */
-#if PLATFORM_GPT_USE_GPT1 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if PLATFORM2_GPT_USE_TIM1
-  /* Driver initialization.*/
-  gptObjectInit(&GPTD1);
-#endif
-}
-
-/**
- * @brief   Configures and activates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-
-  if (gptp->state == GPT_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_GPT_USE_GPT1
-    if (&GPTD1 == gptp) {
-
-    }
-#endif /* PLATFORM_GPT_USE_GPT1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the GPT peripheral.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
-  if (gptp->state == GPT_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_GPT_USE_GPT1
-    if (&GPTD1 == gptp) {
-
-    }
-#endif /* PLATFORM_GPT_USE_GPT1 */
-  }
-}
-
-/**
- * @brief   Starts the timer in continuous mode.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
-  (void)gptp;
-  (void)interval;
-
-}
-
-/**
- * @brief   Stops the timer.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
-  (void)gptp;
-
-}
-
-/**
- * @brief   Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- *          in order to not have extra delays caused by interrupt servicing,
- *          this function is only recommended for short delays.
- *
- * @param[in] gptp      pointer to the @p GPTDriver object
- * @param[in] interval  time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
-  (void)gptp;
-  (void)interval;
-
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/os/hal/templates/gpt_lld.h b/os/hal/templates/gpt_lld.h
deleted file mode 100644
index 13251eb47..000000000
--- a/os/hal/templates/gpt_lld.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/gpt_lld.h
- * @brief   GPT Driver subsystem low level driver header template.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef _GPT_LLD_H_
-#define _GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   GPTD1 driver enable switch.
- * @details If set to @p TRUE the support for GPTD1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__)
-#define STM32_GPT_USE_TIM1                  FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief   GPT counter type.
- */
-typedef uint16_t gptcnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  gptfreq_t                 frequency;
-  /**
-   * @brief   Timer callback pointer.
-   * @note    This callback is invoked on GPT counter events.
-   */
-  gptcallback_t             callback;
-  /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief   Structure representing a GPT driver.
- */
-struct GPTDriver {
-  /**
-   * @brief Driver state.
-   */
-  gptstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const GPTConfig           *config;
-#if defined(GPT_DRIVER_EXT_FIELDS)
-  GPT_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Changes the interval of GPT peripheral.
- * @details This function changes the interval of a running GPT unit.
- * @pre     The GPT unit must have been activated using @p gptStart().
- * @pre     The GPT unit must have been running in continuous mode using
- *          @p gptStartContinuous().
- * @post    The GPT unit interval is changed to the new value.
- * @note    The function has effect at the next cycle start.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- * @param[in] interval  new cycle time in timer ticks
- * @notapi
- */
-#define gpt_lld_change_interval(gptp, interval) {                           \
-  (void)gptp;                                                               \
-  (void)interval;                                                           \
-}
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void gpt_lld_init(void);
-  void gpt_lld_start(GPTDriver *gptp);
-  void gpt_lld_stop(GPTDriver *gptp);
-  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
-  void gpt_lld_stop_timer(GPTDriver *gptp);
-  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* _GPT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/hal_lld.c b/os/hal/templates/hal_lld.c
deleted file mode 100644
index 68a1c02a0..000000000
--- a/os/hal/templates/hal_lld.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/hal_lld.c
- * @brief   HAL Driver subsystem low level driver source template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-}
-
-/**
- * @brief   Platform early initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function is meant to be invoked early during the system
- *          initialization, it is usually invoked from the file
- *          @p board.c.
- *
- * @special
- */
-void platform_early_init(void) {
-
-}
-
-/** @} */
diff --git a/os/hal/templates/hal_lld.h b/os/hal/templates/hal_lld.h
deleted file mode 100644
index 9fd763613..000000000
--- a/os/hal/templates/hal_lld.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/hal_lld.h
- * @brief   HAL subsystem low level driver header template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @name    Platform identification
- * @{
- */
-#define PLATFORM_NAME           ""
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(PLATFORM_MCUCONF)
-#error "Using a wrong mcuconf.h file, PLATFORM_MCUCONF not defined"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief   Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the current value of the system free running counter.
- * @note    This service is implemented by returning the content of the
- *          DWT_CYCCNT register.
- *
- * @return              The value of the system free running counter of
- *                      type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value()         0
-
-/**
- * @brief   Realtime counter frequency.
- * @note    The DWT_CYCCNT register is incremented directly by the system
- *          clock so this function returns STM32_HCLK.
- *
- * @return              The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency()     0
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/halconf.h b/os/hal/templates/halconf.h
deleted file mode 100644
index f879c03b3..000000000
--- a/os/hal/templates/halconf.h
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/halconf.h
- * @brief   HAL configuration header.
- * @details HAL configuration file, this file allows to enable or disable the
- *          various device drivers from your application. You may also use
- *          this file in order to override the device drivers default settings.
- *
- * @addtogroup HAL_CONF
- * @{
- */
-
-#ifndef _HALCONF_H_
-#define _HALCONF_H_
-
-#include "mcuconf.h"
-
-/**
- * @name    Drivers enable switches
- */
-/**
- * @brief   Enables the TM subsystem.
- */
-#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
-#define HAL_USE_TM                  TRUE
-#endif
-
-/**
- * @brief   Enables the PAL subsystem.
- */
-#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
-#define HAL_USE_PAL                 TRUE
-#endif
-
-/**
- * @brief   Enables the ADC subsystem.
- */
-#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
-#define HAL_USE_ADC                 TRUE
-#endif
-
-/**
- * @brief   Enables the CAN subsystem.
- */
-#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
-#define HAL_USE_CAN                 TRUE
-#endif
-
-/**
- * @brief   Enables the DAC subsystem.
- */
-#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
-#define HAL_USE_DAC                 TRUE
-#endif
-
-/**
- * @brief   Enables the EXT subsystem.
- */
-#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
-#define HAL_USE_EXT                 TRUE
-#endif
-
-/**
- * @brief   Enables the GPT subsystem.
- */
-#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
-#define HAL_USE_GPT                 TRUE
-#endif
-
-/**
- * @brief   Enables the I2C subsystem.
- */
-#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
-#define HAL_USE_I2C                 TRUE
-#endif
-
-/**
- * @brief   Enables the ICU subsystem.
- */
-#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
-#define HAL_USE_ICU                 TRUE
-#endif
-
-/**
- * @brief   Enables the MAC subsystem.
- */
-#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
-#define HAL_USE_MAC                 TRUE
-#endif
-
-/**
- * @brief   Enables the MMC_SPI subsystem.
- */
-#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
-#define HAL_USE_MMC_SPI             TRUE
-#endif
-
-/**
- * @brief   Enables the PWM subsystem.
- */
-#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
-#define HAL_USE_PWM                 TRUE
-#endif
-
-/**
- * @brief   Enables the RTC subsystem.
- */
-#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
-#define HAL_USE_RTC                 FALSE
-#endif
-
-/**
- * @brief   Enables the SDC subsystem.
- */
-#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
-#define HAL_USE_SDC                 TRUE
-#endif
-
-/**
- * @brief   Enables the SERIAL subsystem.
- */
-#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL              TRUE
-#endif
-
-/**
- * @brief   Enables the SERIAL over USB subsystem.
- */
-#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL_USB          TRUE
-#endif
-
-/**
- * @brief   Enables the SPI subsystem.
- */
-#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
-#define HAL_USE_SPI                 TRUE
-#endif
-
-/**
- * @brief   Enables the UART subsystem.
- */
-#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
-#define HAL_USE_UART                TRUE
-#endif
-
-/**
- * @brief   Enables the USB subsystem.
- */
-#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
-#define HAL_USE_USB                 TRUE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name ADC driver related setting
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Enables synchronous APIs.
- * @note    Disabling this option saves both code and data space.
- */
-#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
-#define ADC_USE_WAIT                TRUE
-#endif
-
-/**
- * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
- * @note    Disabling this option saves both code and data space.
- */
-#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
-#define ADC_USE_MUTUAL_EXCLUSION    TRUE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name CAN driver related setting
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Sleep mode related APIs inclusion switch.
- */
-#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
-#define CAN_USE_SLEEP_MODE          TRUE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name I2C driver related setting
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Enables the mutual exclusion APIs on the I2C bus.
- */
-#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
-#define I2C_USE_MUTUAL_EXCLUSION    TRUE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name MAC driver related setting
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Enables an event sources for incoming packets.
- */
-#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
-#define MAC_USE_ZERO_COPY           TRUE
-#endif
-
-/**
- * @brief   Enables an event sources for incoming packets.
- */
-#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
-#define MAC_USE_EVENTS              TRUE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name MMC_SPI driver related setting
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Delays insertions.
- * @details If enabled this options inserts delays into the MMC waiting
- *          routines releasing some extra CPU time for the threads with
- *          lower priority, this may slow down the driver a bit however.
- *          This option is recommended also if the SPI driver does not
- *          use a DMA channel and heavily loads the CPU.
- */
-#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
-#define MMC_NICE_WAITING            TRUE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name SDC driver related setting
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Number of initialization attempts before rejecting the card.
- * @note    Attempts are performed at 10mS intervals.
- */
-#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
-#define SDC_INIT_RETRY              100
-#endif
-
-/**
- * @brief   Include support for MMC cards.
- * @note    MMC support is not yet implemented so this option must be kept
- *          at @p FALSE.
- */
-#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
-#define SDC_MMC_SUPPORT             TRUE
-#endif
-
-/**
- * @brief   Delays insertions.
- * @details If enabled this options inserts delays into the MMC waiting
- *          routines releasing some extra CPU time for the threads with
- *          lower priority, this may slow down the driver a bit however.
- */
-#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
-#define SDC_NICE_WAITING            TRUE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name SERIAL driver related setting
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Default bit rate.
- * @details Configuration parameter, this is the baud rate selected for the
- *          default configuration.
- */
-#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
-#define SERIAL_DEFAULT_BITRATE      38400
-#endif
-
-/**
- * @brief   Serial buffers size.
- * @details Configuration parameter, you can change the depth of the queue
- *          buffers depending on the requirements of your application.
- * @note    The default is 64 bytes for both the transmission and receive
- *          buffers.
- */
-#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define SERIAL_BUFFERS_SIZE         16
-#endif
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name SERIAL_USB driver related setting
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Serial over USB buffers size.
- * @details Configuration parameter, the buffer size must be a multiple of
- *          the USB data endpoint maximum packet size.
- * @note    The default is 64 bytes for both the transmission and receive
- *          buffers.
- */
-#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define SERIAL_USB_BUFFERS_SIZE     64
-#endif
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name SPI driver related setting
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Enables synchronous APIs.
- * @note    Disabling this option saves both code and data space.
- */
-#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
-#define SPI_USE_WAIT                TRUE
-#endif
-
-/**
- * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
- * @note    Disabling this option saves both code and data space.
- */
-#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
-#define SPI_USE_MUTUAL_EXCLUSION    TRUE
-#endif
-/** @} */
-
-#endif /* _HALCONF_H_ */
-
-/** @} */
diff --git a/os/hal/templates/i2c_lld.c b/os/hal/templates/i2c_lld.c
deleted file mode 100644
index 318686b27..000000000
--- a/os/hal/templates/i2c_lld.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/i2c_lld.c
- * @brief   I2C Driver subsystem low level driver source template.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   I2C1 driver identifier.
- */
-#if PLATFORM_I2C_USE_I2C1 || defined(__DOXYGEN__)
-I2CDriver I2CD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-#if PLATFORM_I2C_USE_I2C1
-  i2cObjectInit(&I2CD1);
-#endif /* PLATFORM_I2C_USE_I2C1 */
-}
-
-/**
- * @brief   Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-
-  if (i2cp->state == I2C_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_I2C_USE_I2C1
-    if (&I2CD1 == i2cp) {
-
-    }
-#endif /* PLATFORM_I2C_USE_I2C1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the I2C peripheral.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
-  if (i2cp->state != I2C_STOP) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_I2C_USE_I2C1
-    if (&I2CD1 == i2cp) {
-
-    }
-#endif /* PLATFORM_I2C_USE_I2C1 */
-  }
-}
-
-/**
- * @brief   Receives data via the I2C bus as master.
- * @details Number of receiving bytes must be more than 1 on STM32F1x. This is
- *          hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                     uint8_t *rxbuf, size_t rxbytes,
-                                     systime_t timeout) {
-
-  (void)i2cp;
-  (void)addr;
-  (void)rxbuf;
-  (void)rxbytes;
-  (void)timeout;
-
-  return RDY_OK;
-}
-
-/**
- * @brief   Transmits data via the I2C bus as master.
- * @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
- *          This is hardware restriction.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- * @param[in] addr      slave device address
- * @param[in] txbuf     pointer to the transmit buffer
- * @param[in] txbytes   number of bytes to be transmitted
- * @param[out] rxbuf    pointer to the receive buffer
- * @param[in] rxbytes   number of bytes to be received
- * @param[in] timeout   the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if the function succeeded.
- * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
- *                      be retrieved using @p i2cGetErrors().
- * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
- *                      timeout the driver must be stopped and restarted
- *                      because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                      const uint8_t *txbuf, size_t txbytes,
-                                      uint8_t *rxbuf, size_t rxbytes,
-                                      systime_t timeout) {
-
-  (void)i2cp;
-  (void)addr;
-  (void)txbuf;
-  (void)txbytes;
-  (void)rxbuf;
-  (void)rxbytes;
-  (void)timeout;
-
-  return RDY_OK;
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/os/hal/templates/i2c_lld.h b/os/hal/templates/i2c_lld.h
deleted file mode 100644
index 83da65c11..000000000
--- a/os/hal/templates/i2c_lld.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/i2c_lld.h
- * @brief   I2C Driver subsystem low level driver header template.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   I2C1 driver enable switch.
- * @details If set to @p TRUE the support for I2C1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(PLATFORM_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define PLATFORM_I2C_USE_I2C1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type representing I2C address.
- */
-typedef uint16_t i2caddr_t;
-
-/**
- * @brief   Type of I2C Driver condition flags.
- */
-typedef uint32_t i2cflags_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
-  uint32_t                  dummy;
-} I2CConfig;
-
-/**
- * @brief   Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver {
-  /**
-   * @brief   Driver state.
-   */
-  i2cstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const I2CConfig           *config;
-  /**
-   * @brief   Error flags.
-   */
-  i2cflags_t                errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the bus.
-   */
-  Mutex                     mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore                 semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
-  I2C_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Get errors from I2C driver.
- *
- * @param[in] i2cp      pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-#if PLATFORM_I2C_USE_I2C1
-extern I2CDriver I2CD1;
-#endif
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void i2c_lld_init(void);
-  void i2c_lld_start(I2CDriver *i2cp);
-  void i2c_lld_stop(I2CDriver *i2cp);
-  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                        const uint8_t *txbuf, size_t txbytes,
-                                        uint8_t *rxbuf, size_t rxbytes,
-                                        systime_t timeout);
-  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
-                                       uint8_t *rxbuf, size_t rxbytes,
-                                       systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_I2C */
-
-#endif /* _I2C_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/icu_lld.c b/os/hal/templates/icu_lld.c
deleted file mode 100644
index 7685d39b9..000000000
--- a/os/hal/templates/icu_lld.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/icu_lld.c
- * @brief   ICU Driver subsystem low level driver source template.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   ICU1 driver identifier.
- */
-#if PLATFORM_ICU_USE_ICU1 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
-#if PLATFORM_ICU_USE_ICU1
-  /* Driver initialization.*/
-  icuObjectInit(&ICUD1);
-#endif /* PLATFORM_ICU_USE_ICU1 */
-}
-
-/**
- * @brief   Configures and activates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-
-  if (icup->state == ICU_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_ICU_USE_ICU1
-    if (&ICUD1 == icup) {
-
-    }
-#endif /* PLATFORM_ICU_USE_ICU1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the ICU peripheral.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
-  if (icup->state == ICU_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_ICU_USE_ICU1
-    if (&ICUD1 == icup) {
-
-    }
-#endif /* PLATFORM_ICU_USE_ICU1 */
-  }
-}
-
-/**
- * @brief   Enables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
-  (void)icup;
-
-}
-
-/**
- * @brief   Disables the input capture.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
-  (void)icup;
-
-}
-
-/**
- * @brief   Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- *          edge and the stop edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-icucnt_t icu_lld_get_width(ICUDriver *icup) {
-
-  (void)icup;
-
-  return 0;
-}
-
-/**
- * @brief   Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- *          edge and the next start edge.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- * @return              The number of ticks.
- *
- * @notapi
- */
-icucnt_t icu_lld_get_period(ICUDriver *icup) {
-
-  (void)icup;
-
-  return 0;
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/templates/icu_lld.h b/os/hal/templates/icu_lld.h
deleted file mode 100644
index 099601164..000000000
--- a/os/hal/templates/icu_lld.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
-   Concepts and parts of this file have been contributed by Fabio Utzig and
-   Xo Wang.
- */
-
-/**
- * @file    templates/icu_lld.h
- * @brief   ICU Driver subsystem low level driver header template.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ICU driver enable switch.
- * @details If set to @p TRUE the support for ICU1 is included.
- */
-#if !defined(PLATFORM_ICU_USE_ICU1) || defined(__DOXYGEN__)
-#define PLATFORM_ICU_USE_ICU1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief ICU driver mode.
- */
-typedef enum {
-  ICU_INPUT_ACTIVE_HIGH = 0,        /**< Trigger on rising edge.            */
-  ICU_INPUT_ACTIVE_LOW = 1,         /**< Trigger on falling edge.           */
-} icumode_t;
-
-/**
- * @brief   ICU frequency type.
- */
-typedef uint32_t icufreq_t;
-
-/**
- * @brief   ICU counter type.
- */
-typedef uint16_t icucnt_t;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief   Driver mode.
-   */
-  icumode_t                 mode;
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  icufreq_t                 frequency;
-  /**
-   * @brief   Callback for pulse width measurement.
-   */
-  icucallback_t             width_cb;
-  /**
-   * @brief   Callback for cycle period measurement.
-   */
-  icucallback_t             period_cb;
-  /**
-   * @brief   Callback for timer overflow.
-   */
-  icucallback_t             overflow_cb;
-  /* End of the mandatory fields.*/
-} ICUConfig;
-
-/**
- * @brief   Structure representing an ICU driver.
- */
-struct ICUDriver {
-  /**
-   * @brief Driver state.
-   */
-  icustate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const ICUConfig           *config;
-#if defined(ICU_DRIVER_EXT_FIELDS)
-  ICU_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_ICU_USE_ICU1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void icu_lld_init(void);
-  void icu_lld_start(ICUDriver *icup);
-  void icu_lld_stop(ICUDriver *icup);
-  void icu_lld_enable(ICUDriver *icup);
-  void icu_lld_disable(ICUDriver *icup);
-  icucnt_t icu_lld_get_width(ICUDriver *icup);
-  icucnt_t icu_lld_get_period(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/mac_lld.c b/os/hal/templates/mac_lld.c
deleted file mode 100644
index d4de2ce5c..000000000
--- a/os/hal/templates/mac_lld.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/mac_lld.c
- * @brief   MAC Driver subsystem low level driver source template.
- *
- * @addtogroup MAC
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-#include "mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief MAC1 driver identifier.
- */
-#if PLATFORM_MAC_USE_MAC1 || defined(__DOXYGEN__)
-MACDriver ETHD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level MAC initialization.
- *
- * @notapi
- */
-void mac_lld_init(void) {
-
-#if PLATFORM_MAC_USE_MAC1
-  /* Driver initialization.*/
-  macObjectInit(&MACD1);
-#endif /* PLATFORM_MAC_USE_MAC1 */
-}
-
-/**
- * @brief   Configures and activates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_start(MACDriver *macp) {
-
-  if (macp->state == MAC_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_MAC_USE_MAC1
-    if (&MACD1 == macp) {
-
-    }
-#endif /* PLATFORM_MAC_USE_MAC1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the MAC peripheral.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_stop(MACDriver *macp) {
-
-  if (macp->state == MAC_ACTIVE) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_MAC_USE_MAC1
-    if (&MACD1 == macp) {
-
-    }
-#endif /* PLATFORM_MAC_USE_MAC1 */
-  }
-}
-
-/**
- * @brief   Returns a transmission descriptor.
- * @details One of the available transmission descriptors is locked and
- *          returned.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] tdp      pointer to a @p MACTransmitDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                      MACTransmitDescriptor *tdp) {
-
-  (void)macp;
-  (void)tdp;
-
-  return RDY_OK;
-}
-
-/**
- * @brief   Releases a transmit descriptor and starts the transmission of the
- *          enqueued data as a single frame.
- *
- * @param[in] tdp       the pointer to the @p MACTransmitDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
-
-  (void)tdp;
-
-}
-
-/**
- * @brief   Returns a receive descriptor.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @param[out] rdp      pointer to a @p MACReceiveDescriptor structure
- * @return              The operation status.
- * @retval RDY_OK       the descriptor has been obtained.
- * @retval RDY_TIMEOUT  descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                     MACReceiveDescriptor *rdp) {
-
-  (void)macp;
-  (void)rdp;
-
-  return RDY_OK;
-}
-
-/**
- * @brief   Releases a receive descriptor.
- * @details The descriptor and its buffer are made available for more incoming
- *          frames.
- *
- * @param[in] rdp       the pointer to the @p MACReceiveDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
-
-  (void)rdp;
-
-}
-
-/**
- * @brief   Updates and returns the link status.
- *
- * @param[in] macp      pointer to the @p MACDriver object
- * @return              The link status.
- * @retval TRUE         if the link is active.
- * @retval FALSE        if the link is down.
- *
- * @notapi
- */
-bool_t mac_lld_poll_link_status(MACDriver *macp) {
-
-  (void)macp;
-
-  return FALSE;
-}
-
-/**
- * @brief   Writes to a transmit descriptor's stream.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf       pointer to the buffer containing the data to be
- *                      written
- * @param[in] size      number of bytes to be written
- * @return              The number of bytes written into the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if the maximum
- *                      frame size is reached.
- *
- * @notapi
- */
-size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                         uint8_t *buf,
-                                         size_t size) {
-
-  (void)tdp;
-  (void)buf;
-
-  return size;
-}
-
-/**
- * @brief   Reads from a receive descriptor's stream.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[in] buf       pointer to the buffer that will receive the read data
- * @param[in] size      number of bytes to be read
- * @return              The number of bytes read from the descriptor's
- *                      stream, this value can be less than the amount
- *                      specified in the parameter @p size if there are
- *                      no more bytes to read.
- *
- * @notapi
- */
-size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                       uint8_t *buf,
-                                       size_t size) {
-
-  (void)rdp;
-  (void)buf;
-
-  return size;
-}
-
-#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
-/**
- * @brief   Returns a pointer to the next transmit buffer in the descriptor
- *          chain.
- * @note    The API guarantees that enough buffers can be requested to fill
- *          a whole frame.
- *
- * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
- * @param[in] size      size of the requested buffer. Specify the frame size
- *                      on the first call then scale the value down subtracting
- *                      the amount of data already copied into the previous
- *                      buffers.
- * @param[out] sizep    pointer to variable receiving the buffer size, it is
- *                      zero when the last buffer has already been returned.
- *                      Note that a returned size lower than the amount
- *                      requested means that more buffers must be requested
- *                      in order to fill the frame data entirely.
- * @return              Pointer to the returned buffer.
- * @retval NULL         if the buffer chain has been entirely scanned.
- *
- * @notapi
- */
-uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
-                                          size_t size,
-                                          size_t *sizep) {
-
-  (void)tdp;
-  (void)size;
-  (void)sizep;
-
-  return NULL;
-}
-
-/**
- * @brief   Returns a pointer to the next receive buffer in the descriptor
- *          chain.
- * @note    The API guarantees that the descriptor chain contains a whole
- *          frame.
- *
- * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
- * @param[out] sizep    pointer to variable receiving the buffer size, it is
- *                      zero when the last buffer has already been returned.
- * @return              Pointer to the returned buffer.
- * @retval NULL         if the buffer chain has been entirely scanned.
- *
- * @notapi
- */
-const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
-                                               size_t *sizep) {
-
-  (void)rdp;
-  (void)sizep;
-
-  return NULL;
-}
-#endif /* MAC_USE_ZERO_COPY */
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/templates/mac_lld.h b/os/hal/templates/mac_lld.h
deleted file mode 100644
index ed278f514..000000000
--- a/os/hal/templates/mac_lld.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/mac_lld.h
- * @brief   MAC Driver subsystem low level driver header template.
- *
- * @addtogroup MAC
- * @{
- */
-
-#ifndef _MAC_LLD_H_
-#define _MAC_LLD_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   This implementation supports the zero-copy mode API.
- */
-#define MAC_SUPPORTS_ZERO_COPY              TRUE
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   MAC driver enable switch.
- * @details If set to @p TRUE the support for MAC1 is included.
- */
-#if !defined(PLATFORM_MAC_USE_MAC1) || defined(__DOXYGEN__)
-#define PLATFORM_MAC_USE_MAC1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief MAC address.
-   */
-  uint8_t               *mac_address;
-  /* End of the mandatory fields.*/
-} MACConfig;
-
-/**
- * @brief   Structure representing a MAC driver.
- */
-struct MACDriver {
-  /**
-   * @brief Driver state.
-   */
-  macstate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const MACConfig       *config;
-  /**
-   * @brief Transmit semaphore.
-   */
-  Semaphore             tdsem;
-  /**
-   * @brief Receive semaphore.
-   */
-  Semaphore             rdsem;
-#if MAC_USE_EVENTS || defined(__DOXYGEN__)
-  /**
-   * @brief Receive event.
-   */
-  EventSource           rdevent;
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/**
- * @brief   Structure representing a transmit descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current write offset.
-   */
-  size_t                    offset;
-  /**
-   * @brief Available space size.
-   */
-  size_t                    size;
-  /* End of the mandatory fields.*/
-} MACTransmitDescriptor;
-
-/**
- * @brief   Structure representing a receive descriptor.
- */
-typedef struct {
-  /**
-   * @brief Current read offset.
-   */
-  size_t                offset;
-  /**
-   * @brief Available data size.
-   */
-  size_t                size;
-  /* End of the mandatory fields.*/
-} MACReceiveDescriptor;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_MAC_USE_MAC1 && !defined(__DOXYGEN__)
-extern MACDriver ETHD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void mac_lld_init(void);
-  void mac_lld_start(MACDriver *macp);
-  void mac_lld_stop(MACDriver *macp);
-  msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
-                                        MACTransmitDescriptor *tdp);
-  void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
-  msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
-                                       MACReceiveDescriptor *rdp);
-  void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
-  bool_t mac_lld_poll_link_status(MACDriver *macp);
-  size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
-                                           uint8_t *buf,
-                                           size_t size);
-  size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
-                                         uint8_t *buf,
-                                         size_t size);
-#if MAC_USE_ZERO_COPY
-  uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
-                                            size_t size,
-                                            size_t *sizep);
-  const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
-                                                 size_t *sizep);
-#endif /* MAC_USE_ZERO_COPY */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _MAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/mcuconf.h b/os/hal/templates/mcuconf.h
deleted file mode 100644
index c5a797157..000000000
--- a/os/hal/templates/mcuconf.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * Platform drivers configuration.
- * The following settings override the default settings present in
- * the various device driver implementation headers.
- * Note that the settings for each driver only have effect if the whole
- * driver is enabled in halconf.h.
- */
-
-#define PLATFORM_MCUCONF
diff --git a/os/hal/templates/meta/driver.c b/os/hal/templates/meta/driver.c
deleted file mode 100644
index 6eb9caf0f..000000000
--- a/os/hal/templates/meta/driver.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    xxx.c
- * @brief   XXX Driver code.
- *
- * @addtogroup XXX
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_XXX || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local types.                                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   XXX Driver initialization.
- * @note    This function is implicitly invoked by @p halInit(), there is
- *          no need to explicitly initialize the driver.
- *
- * @init
- */
-void xxxInit(void) {
-
-  xxx_lld_init();
-}
-
-/**
- * @brief   Initializes the standard part of a @p XXXDriver structure.
- *
- * @param[out] xxxp     pointer to the @p XXXDriver object
- *
- * @init
- */
-void xxxObjectInit(XXXDriver *xxxp) {
-
-  xxxp->state  = XXX_STOP;
-  xxxp->config = NULL;
-}
-
-/**
- * @brief   Configures and activates the XXX peripheral.
- *
- * @param[in] xxxp      pointer to the @p XXXDriver object
- * @param[in] config    pointer to the @p XXXConfig object
- *
- * @api
- */
-void xxxStart(XXXDriver *xxxp, const XXXConfig *config) {
-
-  chDbgCheck((xxxp != NULL) && (config != NULL), "xxxStart");
-
-  chSysLock();
-  chDbgAssert((xxxp->state == XXX_STOP) || (xxxp->state == XXX_READY),
-              "xxxStart(), #1", "invalid state");
-  xxxp->config = config;
-  xxx_lld_start(xxxp);
-  xxxp->state = XXX_READY;
-  chSysUnlock();
-}
-
-/**
- * @brief   Deactivates the XXX peripheral.
- *
- * @param[in] xxxp      pointer to the @p XXXDriver object
- *
- * @api
- */
-void xxxStop(XXXDriver *xxxp) {
-
-  chDbgCheck(xxxp != NULL, "xxxStop");
-
-  chSysLock();
-  chDbgAssert((xxxp->state == XXX_STOP) || (xxxp->state == XXX_READY),
-              "xxxStop(), #1", "invalid state");
-  xxx_lld_stop(xxxp);
-  xxxp->state = XXX_STOP;
-  chSysUnlock();
-}
-
-#endif /* HAL_USE_XXX */
-
-/** @} */
diff --git a/os/hal/templates/meta/driver.h b/os/hal/templates/meta/driver.h
deleted file mode 100644
index 84b81e009..000000000
--- a/os/hal/templates/meta/driver.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    xxx.h
- * @brief   XXX Driver macros and structures.
- *
- * @addtogroup XXX
- * @{
- */
-
-#ifndef _XXX_H_
-#define _XXX_H_
-
-#if HAL_USE_XXX || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Driver state machine possible states.
- */
-typedef enum {
-  XXX_UNINIT = 0,                   /**< Not initialized.                   */
-  XXX_STOP = 1,                     /**< Stopped.                           */
-  XXX_READY = 2,                    /**< Ready.                             */
-} xxxstate_t;
-
-/**
- * @brief   Type of a structure representing a XXX driver.
- */
-typedef struct XXXDriver XXXDriver;
-
-#include "xxx_lld.h"
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void xxxInit(void);
-  void xxxObjectInit(XXXDriver *xxxp);
-  void xxxStart(XXXDriver *xxxp, const XXXConfig *config);
-  void xxxStop(XXXDriver *xxxp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_XXX */
-
-#endif /* _XXX_H_ */
-
-/** @} */
diff --git a/os/hal/templates/meta/driver_lld.c b/os/hal/templates/meta/driver_lld.c
deleted file mode 100644
index b01ef3fb6..000000000
--- a/os/hal/templates/meta/driver_lld.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/xxx_lld.c
- * @brief   XXX Driver subsystem low level driver source template.
- *
- * @addtogroup XXX
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_XXX || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   XXX1 driver identifier.
- */
-#if PLATFORM_XXX_USE_XXX1 || defined(__DOXYGEN__)
-XXXDriver XXXD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local types.                                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level XXX driver initialization.
- *
- * @notapi
- */
-void xxx_lld_init(void) {
-
-#if PLATFORM_XXX_USE_XXX1
-  /* Driver initialization.*/
-  xxxObjectInit(&XXXD1);
-#endif /* PLATFORM_XXX_USE_XXX1 */
-}
-
-/**
- * @brief   Configures and activates the XXX peripheral.
- *
- * @param[in] xxxp      pointer to the @p XXXDriver object
- *
- * @notapi
- */
-void xxx_lld_start(XXXDriver *xxxp) {
-
-  if (xxxp->state == XXX_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_XXX_USE_XXX1
-    if (&XXXD1 == xxxp) {
-
-    }
-#endif /* PLATFORM_XXX_USE_XXX1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the XXX peripheral.
- *
- * @param[in] xxxp      pointer to the @p XXXDriver object
- *
- * @notapi
- */
-void xxx_lld_stop(XXXDriver *xxxp) {
-
-  if (xxxp->state == XXX_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_XXX_USE_XXX1
-    if (&XXXD1 == xxxp) {
-
-    }
-#endif /* PLATFORM_XXX_USE_XXX1 */
-  }
-}
-
-#endif /* HAL_USE_XXX */
-
-/** @} */
diff --git a/os/hal/templates/meta/driver_lld.h b/os/hal/templates/meta/driver_lld.h
deleted file mode 100644
index bca5a521c..000000000
--- a/os/hal/templates/meta/driver_lld.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/xxx_lld.h
- * @brief   XXX Driver subsystem low level driver header template.
- *
- * @addtogroup XXX
- * @{
- */
-
-#ifndef _XXX_LLD_H_
-#define _XXX_LLD_H_
-
-#if HAL_USE_XXX || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   XXX driver enable switch.
- * @details If set to @p TRUE the support for XXX1 is included.
- */
-#if !defined(PLATFORM_XXX_USE_XXX1) || defined(__DOXYGEN__)
-#define PLATFORM_XXX_USE_XXX1             FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an XXX driver.
- */
-typedef struct XXXDriver XXXDriver;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-
-} XXXConfig;
-
-/**
- * @brief   Structure representing an XXX driver.
- */
-struct XXXDriver {
-  /**
-   * @brief Driver state.
-   */
-  xxxstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const XXXConfig           *config;
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_XXX_USE_XXX1 && !defined(__DOXYGEN__)
-extern XXXDriver XXXD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void xxx_lld_init(void);
-  void xxx_lld_start(XXXDriver *xxxp);
-  void xxx_lld_stop(XXXDriver *xxxp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_XXX */
-
-#endif /* _XXX_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/osal.c b/os/hal/templates/osal.c
new file mode 100644
index 000000000..4ccb1cc2e
--- /dev/null
+++ b/os/hal/templates/osal.c
@@ -0,0 +1,133 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    osal.c
+ * @brief   OSAL module code.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#include "osal.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Pointer to a halt error message.
+ * @note    The message is meant to be retrieved by the debugger after the
+ *          system halt caused by an unexpected error.
+ */
+const char *osal_halt_msg;
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   OSAL module initialization.
+ *
+ * @api
+ */
+void osalInit(void) {
+
+}
+
+/**
+ * @brief   System halt with error message.
+ *
+ * @param[in] reason    the halt message pointer
+ *
+ * @api
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak, noreturn))
+#endif
+void osalSysHalt(const char *reason) {
+
+  osalIsrDisable();
+  osal_halt_msg = reason;
+  while (1)
+    ;
+}
+
+/**
+ * @brief   Enqueues the caller thread.
+ * @details The caller thread is enqueued and put to sleep until it is
+ *          dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] time      the timeout in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state.
+ *                      - @a TIME_IMMEDIATE the thread is not enqueued and
+ *                        the function returns @p MSG_TIMEOUT as if a timeout
+ *                        occurred.
+ *                      .
+ * @return              The message from @p osalQueueWakeupOneI() or
+ *                      @p osalQueueWakeupAllI() functions.
+ * @retval RDY_TIMEOUT  if the thread has not been dequeued within the
+ *                      specified timeout or if the function has been
+ *                      invoked with @p TIME_IMMEDIATE as timeout
+ *                      specification.
+ *
+ * @sclass
+ */
+msg_t osalQueueGoSleepTimeoutS(threads_queue_t *tqp, systime_t time) {
+  msg_t msg;
+  virtual_timer_t vt;
+
+  void wakeup(void *p) {
+    osalSysLockFromISR();
+    osalThreadResumeI((thread_reference_t *)p, MSG_TIMEOUT);
+    osalSysUnlockFromISR();
+  }
+
+  if (TIME_IMMEDIATE == time)
+    return MSG_TIMEOUT;
+
+  tqp->tr = NULL;
+
+  if (TIME_INFINITE == time)
+   return osalThreadSuspendS(&tqp->tr);
+
+  osalVTSetI(&vt, time, wakeup, (void *)&tqp->tr);
+  msg = osalThreadSuspendS(&tqp->tr);
+  if (osalVTIsArmedI(&vt))
+    osalVTResetI(&vt);
+  return msg;
+}
+
+/** @} */
diff --git a/os/hal/templates/osal.h b/os/hal/templates/osal.h
new file mode 100644
index 000000000..c99fb44a3
--- /dev/null
+++ b/os/hal/templates/osal.h
@@ -0,0 +1,499 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    osal.h
+ * @brief   OSAL module header.
+ *
+ * @addtogroup OSAL
+ * @{
+ */
+
+#ifndef _OSAL_H_
+#define _OSAL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Common constants
+ * @{
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE                               0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                                (!FALSE)
+#endif
+
+#define OSAL_SUCCESS                        FALSE
+#define OSAL_FAILED                         TRUE
+/** @} */
+
+/**
+ * @name    Messages
+ * @{
+ */
+#define MSG_OK              0
+#define MSG_RESET           -1
+#define MSG_TIMEOUT         -2
+/** @} */
+
+/**
+ * @name    Special time constants
+ * @{
+ */
+#define TIME_IMMEDIATE      ((systime_t)0)
+#define TIME_INFINITE       ((systime_t)-1)
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a machine status register.
+ */
+typedef uint32_t osal_sts_t;
+
+/**
+ * @brief   Type of a message.
+ */
+typedef int32_t msg_t;
+
+/**
+ * @brief   Type of system time counter.
+ */
+typedef uint32_t systime_t;
+
+/**
+ * @brief   Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+
+/**
+ * @brief   Type of an event flags mask.
+ */
+typedef uint32_t eventflags_t;
+
+/**
+ * @brief   Type of an event flags object.
+ * @note    The content of this structure is not part of the API and should
+ *          not be relied upon. Implementers may define this structure in
+ *          an entirely different way.
+ * @note    Retrieval and clearing of the flags are not defined in this
+ *          API and are implementation-dependent.
+ */
+typedef struct {
+  volatile eventflags_t flags;      /**< @brief Flags stored into the
+                                                object.                     */
+} eventsource_t;
+
+/**
+ * @brief   Type of a mutex.
+ * @note    If the OS does not support mutexes or there is no OS then them
+ *          mechanism can be simulated.
+ */
+typedef uint32_t mutex_t;
+
+/**
+ * @brief   Type of a thread queue.
+ * @details A thread queue is a queue of sleeping threads, queued threads
+ *          can be dequeued one at time or all together.
+ * @note    In this implementation it is implemented as a single reference
+ *          because there are no real threads.
+ */
+typedef struct {
+  thread_reference_t    tr;
+} threads_queue_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Condition assertion.
+ * @details If the condition check fails then the OSAL panics with the
+ *          specified message and halts.
+ * @note    The condition is tested only if the @p OSAL_ENABLE_ASSERTIONS
+ *          switch is enabled.
+ * @note    The convention for the message is the following:<br>
+ *          @<function_name@>(), #@<assert_number@>
+ * @note    The remark string is not currently used except for putting a
+ *          comment in the code about the assertion.
+ *
+ * @param[in] c         the condition to be verified to be true
+ * @param[in] msg       the text message
+ * @param[in] remark    a remark string
+ *
+ * @api
+ */
+#define osalDbgAssert(c, msg, remark)
+
+/**
+ * @brief   Function parameters check.
+ * @details If the condition check fails then the OSAL panics and halts.
+ * @note    The condition is tested only if the @p OSAL_ENABLE_CHECKS switch
+ *          is enabled.
+ *
+ * @param[in] c         the condition to be verified to be true
+ *
+ * @api
+ */
+#define osalDbgCheck(c)
+
+/**
+ * @brief   I-Class state check.
+ * @note    Not implemented in this simplified OSAL.
+ */
+#define osalDbgCheckClassI()
+
+/**
+ * @brief   S-Class state check.
+ * @note    Not implemented in this simplified OSAL.
+ */
+#define osalDbgCheckClassS()
+
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers.
+ */
+#define OSAL_IRQ_PROLOGUE()
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers.
+ */
+#define OSAL_IRQ_EPILOGUE()
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @details This macro hides the details of an ISR function declaration.
+ *
+ * @param[in] id        a vector name as defined in @p vectors.s
+ */
+#define OSAL_IRQ_HANDLER(id) void id(void)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void osalInit(void);
+  void osalSysHalt(const char *reason);
+  msg_t osalQueueGoSleepTimeoutS(threads_queue_t *tqp, systime_t time);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Enters a critical zone from thread context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLock(void) {
+
+}
+
+/**
+ * @brief   Leaves a critical zone from thread context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlock(void) {
+
+}
+
+/**
+ * @brief   Enters a critical zone from ISR context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysLockFromISR(void) {
+
+}
+
+/**
+ * @brief   Leaves a critical zone from ISR context.
+ * @note    This function cannot be used for reentrant critical zones.
+ *
+ * @special
+ */
+static inline void osalSysUnlockFromISR(void) {
+
+}
+
+/**
+ * @brief   Enters a critical zone returning the previous machine status.
+ *
+ * @return  The previous status.
+ *
+ * @special
+ */
+static inline osal_sts_t osalSysGetStatusAndLock(void) {
+
+}
+
+/**
+ * @brief   Restores a machine status.
+ *
+ * @param[in] sts       the previous status. This value must be something
+ *                      returned by the function @p osalSysGetStatusAndLock().
+ *                      Arbitrary values are not allowed.
+ *
+ * @special
+ */
+static inline void osalSysSetStatus(osal_sts_t sts) {
+
+}
+
+/**
+ * @brief   Checks if a reschedule is required and performs it.
+ * @note    I-Class functions invoked from thread context must not reschedule
+ *          by themselves, an explicit reschedule using this function is
+ *          required in this scenario.
+ * @note    Not implemented in this simplified OSAL.
+ *
+ * @sclass
+ */
+static inline void osalOsRescheduleS(void) {
+
+}
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time      the delay in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE is allowed but interpreted as a
+ *                        normal time specification.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ *
+ * @sclass
+ */
+inline void osalThreadSleepS(systime_t time) {
+
+}
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time      the delay in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE is allowed but interpreted as a
+ *                        normal time specification.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ *
+ * @api
+ */
+void osalThreadSleep(systime_t time) {
+
+}
+
+/**
+ * @brief   Initializes an event flags object.
+ *
+ * @param[out] esp      pointer to the event flags object
+ *
+ * @init
+ */
+static inline void osalEventInit(eventsource_t *esp) {
+
+  osalDbgCheck(esp != NULL);
+
+  esp->flags = 0;
+}
+
+/**
+ * @brief   Add flags to an event source object.
+ *
+ * @param[in] esp       pointer to the event flags object
+ * @param[in] flags     flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlagsI(eventsource_t *esp,
+                                            eventflags_t flags) {
+
+  osalDbgCheck(esp != NULL);
+
+  esp->flags |= flags;
+}
+
+/**
+ * @brief   Add flags to an event source object.
+ *
+ * @param[in] esp       pointer to the event flags object
+ * @param[in] flags     flags to be ORed to the flags mask
+ *
+ * @iclass
+ */
+static inline void osalEventBroadcastFlags(eventsource_t *esp,
+                                           eventflags_t flags) {
+
+  osalDbgCheck(esp != NULL);
+
+  osalSysLock();
+  esp->flags |= flags;
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Returns the flags associated to the event object then clears them.
+ * @note    This function is not part of the OSAL API and is provided
+ *          exclusively as an example and for convenience.
+ *
+ * @param[in] esp       pointer to the event flags object
+ * @return              The flags.
+ *
+ * @iclass
+ */
+static inline eventflags_t osalEventGetAndClearFlagsI(eventsource_t *esp) {
+  eventflags_t flags;
+
+  osalDbgCheck(esp != NULL);
+
+  flags = esp->flags;
+  esp->flags = 0;
+  return flags;
+}
+
+/**
+ * @brief   Returns the flags associated to the event object and clears them.
+ * @note    This function is not part of the OSAL API and is provided
+ *          exclusively as an example and for convenience.
+ *
+ * @param[in] esp       pointer to the event flags object
+ * @return              The flags.
+ *
+ * @api
+ */
+static inline eventflags_t osalEventGetAndClearFlags(eventsource_t *esp) {
+  eventflags_t flags;
+
+  osalSysLock();
+  flags = osalEventGetAndClearFlagsI(esp);
+  osalSysUnlock();
+  return flags;
+}
+
+/**
+ * @brief   Initializes s @p mutex_t object.
+ *
+ * @param[out] mp       pointer to the @p mutex_t object
+ *
+ * @init
+ */
+static inline void osalMutexInit(mutex_t *mp) {
+
+  *mp = 0;
+}
+
+/*
+ * @brief   Locks the specified mutex.
+ * @post    The mutex is locked and inserted in the per-thread stack of owned
+ *          mutexes.
+ *
+ * @param[in,out] mp    pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexLock(mutex_t *mp) {
+
+  *mp = 1;
+}
+
+/**
+ * @brief   Unlocks the specified mutex.
+ * @note    The HAL guarantees to release mutex in reverse lock order. The
+ *          mutex being unlocked is guaranteed to be the last locked mutex
+ *          by the invoking thread.
+ *          The implementation can rely on this behavior and eventually
+ *          ignore the @p mp parameter which is supplied in order to support
+ *          those OSes not supporting a stack of the owned mutexes.
+ *
+ * @param[in,out] mp    pointer to the @p mutex_t object
+ *
+ * @api
+ */
+static inline void osalMutexUnlock(mutex_t *mp) {
+
+  *mp = 0;
+}
+
+/**
+ * @brief   Initializes a threads queue object.
+ *
+ * @param[out] tqp      pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void osalQueueInit(threads_queue_t *tqp) {
+
+}
+
+/**
+ * @brief   Dequeues and wakes up one thread from the queue, if any.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+static inline void osalQueueWakeupOneI(threads_queue_t *tqp, msg_t msg) {
+
+}
+
+/**
+ * @brief   Dequeues and wakes up all threads from the queue.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+static inline void osalQueueWakeupAllI(threads_queue_t *tqp, msg_t msg) {
+
+}
+
+#endif /* _OSAL_H_ */
+
+/** @} */
diff --git a/os/hal/templates/pal_lld.c b/os/hal/templates/pal_lld.c
deleted file mode 100644
index ac0bdca44..000000000
--- a/os/hal/templates/pal_lld.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/pal_lld.c
- * @brief   PAL subsystem low level driver template.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 I/O ports configuration.
- * @details Ports A-D(E, F, G, H) clocks enabled.
- *
- * @param[in] config    the STM32 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-  (void)config;
-
-}
-
-/**
- * @brief   Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- *
- * @param[in] port      the port identifier
- * @param[in] mask      the group mask
- * @param[in] mode      the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
-                           ioportmask_t mask,
-                           iomode_t mode) {
-
-  (void)port;
-  (void)mask;
-  (void)mode;
-
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/templates/pal_lld.h b/os/hal/templates/pal_lld.h
deleted file mode 100644
index e69c2ca2e..000000000
--- a/os/hal/templates/pal_lld.h
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/pal_lld.h
- * @brief   PAL subsystem low level driver header template.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes                                      */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* I/O Ports Types and constants.                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- *          system startup time in order to initialized the digital I/O
- *          subsystem. This represents only the initial setup, specific pads
- *          or whole ports can be reprogrammed at later time.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-
-} PALConfig;
-
-/**
- * @brief   Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief   Whole port mask.
- * @brief   This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief   Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief   Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief   Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- *          any assumption about it, use the provided macros when populating
- *          variables of this type.
- */
-typedef uint32_t ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers.                                                    */
-/*===========================================================================*/
-
-/**
- * @brief   First I/O port identifier.
- * @details Low level drivers can define multiple ports, it is suggested to
- *          use this naming convention.
- */
-#define IOPORT1         0
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as      */
-/* functions, if so please put them in pal_lld.c.                            */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PAL subsystem initialization.
- *
- * @param[in] config    architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief   Reads the physical I/O port states.
- *
- * @param[in] port      port identifier
- * @return              The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) 0
-
-/**
- * @brief   Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- *          value.
- *
- * @param[in] port      port identifier
- * @return              The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) 0
-
-/**
- * @brief   Writes a bits mask on a I/O port.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits)
-
-/**
- * @brief   Sets a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits)
-
-/**
- * @brief   Clears a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits)
-
-/**
- * @brief   Toggles a bits mask on a I/O port.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] bits      bits to be XORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_toggleport(port, bits)
-
-/**
- * @brief   Reads a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @return              The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset) 0
-
-/**
- * @brief   Writes a group of bits.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] bits      bits to be written. Values exceeding the group width
- *                      are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
-
-/**
- * @brief   Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- *          with the specified mode.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] mask      group mask
- * @param[in] offset    group bit offset within the port
- * @param[in] mode      group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
-  _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief   Reads a logical state from an I/O pad.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @return              The logical state.
- * @retval PAL_LOW      low logical state.
- * @retval PAL_HIGH     high logical state.
- *
- * @notapi
- */
-#define pal_lld_readpad(port, pad) PAL_LOW
-
-/**
- * @brief   Writes a logical state on an output pad.
- * @note    This function is not meant to be invoked directly by the
- *          application  code.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] bit       logical value, the value must be @p PAL_LOW or
- *                      @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit)
-
-/**
- * @brief   Sets a pad logical state to @p PAL_HIGH.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad)
-
-/**
- * @brief   Clears a pad logical state to @p PAL_LOW.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad)
-
-/**
- * @brief   Toggles a pad logical state.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad)
-
-/**
- * @brief   Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note    The @ref PAL provides a default software implementation of this
- *          functionality, implement this function if can optimize it by using
- *          special hardware functionalities or special coding.
- * @note    Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port      port identifier
- * @param[in] pad       pad number within the port
- * @param[in] mode      pad mode
- *
- * @notapi
- */
-#define pal_lld_setpadmode(port, pad, mode)
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _pal_lld_init(const PALConfig *config);
-  void _pal_lld_setgroupmode(ioportid_t port,
-                             ioportmask_t mask,
-                             iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/platform.mk b/os/hal/templates/platform.mk
deleted file mode 100644
index 80624fa14..000000000
--- a/os/hal/templates/platform.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# List of all the template platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/templates/hal_lld.c \
-              ${CHIBIOS}/os/hal/templates/adc_lld.c \
-              ${CHIBIOS}/os/hal/templates/can_lld.c \
-              ${CHIBIOS}/os/hal/templates/ext_lld.c \
-              ${CHIBIOS}/os/hal/templates/gpt_lld.c \
- 			  ${CHIBIOS}/os/hal/templates/i2c_lld.c \
-              ${CHIBIOS}/os/hal/templates/icu_lld.c \
-              ${CHIBIOS}/os/hal/templates/mac_lld.c \
-              ${CHIBIOS}/os/hal/templates/pal_lld.c \
-              ${CHIBIOS}/os/hal/templates/pwm_lld.c \
-              ${CHIBIOS}/os/hal/templates/sdc_lld.c \
-              ${CHIBIOS}/os/hal/templates/serial_lld.c \
-              ${CHIBIOS}/os/hal/templates/spi_lld.c \
-              ${CHIBIOS}/os/hal/templates/uart_lld.c \
-              ${CHIBIOS}/os/hal/templates/usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/templates
diff --git a/os/hal/templates/pwm_lld.c b/os/hal/templates/pwm_lld.c
deleted file mode 100644
index a38290334..000000000
--- a/os/hal/templates/pwm_lld.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/pwm_lld.c
- * @brief   PWM Driver subsystem low level driver source template.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   PWM1 driver identifier.
- */
-#if PLATFORM_PWM_USE_PWM1 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-#if PLATFORM_PWM_USE_PWM1
-  /* Driver initialization.*/
-  pwmObjectInit(&PWMD1);
-#endif /* PLATFORM_PWM_USE_PWM1 */
-}
-
-/**
- * @brief   Configures and activates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-
-  if (pwmp->state == PWM_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_PWM_USE_PWM1
-    if (&PWMD1 == pwmp) {
-
-    }
-#endif /* PLATFORM_PWM_USE_PWM1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the PWM peripheral.
- *
- * @param[in] pwmp      pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
-  if (pwmp->state == PWM_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_PWM_USE_PWM1
-    if (&PWMD1 == pwmp) {
-
-    }
-#endif /* PLATFORM_PWM_USE_PWM1 */
-  }
-}
-
-/**
- * @brief   Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- *          been activated using @p pwmStart().
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The PWM unit period is changed to the new value.
- * @note    The function has effect at the next cycle start.
- * @note    If a period is specified that is shorter than the pulse width
- *          programmed in one of the channels then the behavior is not
- *          guaranteed.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] period    new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
-
-  (void)pwmp;
-  (void)period;
-
-}
-
-/**
- * @brief   Enables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is active using the specified configuration.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width     PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t channel,
-                            pwmcnt_t width) {
-
-  (void)pwmp;
-  (void)channel;
-  (void)width;
-
-}
-
-/**
- * @brief   Disables a PWM channel.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- * @post    The channel is disabled and its output line returned to the
- *          idle state.
- * @note    Depending on the hardware implementation this function has
- *          effect starting on the next cycle (recommended implementation)
- *          or immediately (fallback implementation).
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-  (void)pwmp;
-  (void)channel;
-
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/templates/pwm_lld.h b/os/hal/templates/pwm_lld.h
deleted file mode 100644
index 46e357fd4..000000000
--- a/os/hal/templates/pwm_lld.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/pwm_lld.h
- * @brief   PWM Driver subsystem low level driver header template.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS                        4
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   PWM driver enable switch.
- * @details If set to @p TRUE the support for PWM1 is included.
- */
-#if !defined(PLATFORM_PWM_USE_PWM1) || defined(__DOXYGEN__)
-#define PLATFORM_PWM_USE_PWM1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief   PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief   PWM counter type.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief   PWM driver channel configuration structure.
- * @note    Some architectures may not be able to support the channel mode
- *          or the callback, in this case the fields are ignored.
- */
-typedef struct {
-  /**
-   * @brief Channel active logic level.
-   */
-  pwmmode_t                 mode;
-  /**
-   * @brief Channel callback pointer.
-   * @note  This callback is invoked on the channel compare event. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief   Timer clock in Hz.
-   * @note    The low level can use assertions in order to catch invalid
-   *          frequency specifications.
-   */
-  uint32_t                  frequency;
-  /**
-   * @brief   PWM period in ticks.
-   * @note    The low level can use assertions in order to catch invalid
-   *          period specifications.
-   */
-  pwmcnt_t                  period;
-  /**
-   * @brief Periodic callback pointer.
-   * @note  This callback is invoked on PWM counter reset. If set to
-   *        @p NULL then the callback is disabled.
-   */
-  pwmcallback_t             callback;
-  /**
-   * @brief Channels configurations.
-   */
-  PWMChannelConfig          channels[PWM_CHANNELS];
-  /* End of the mandatory fields.*/
-} PWMConfig;
-
-/**
- * @brief   Structure representing an PWM driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct PWMDriver {
-  /**
-   * @brief Driver state.
-   */
-  pwmstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const PWMConfig           *config;
-  /**
-   * @brief   Current PWM period in ticks.
-   */
-  pwmcnt_t                  period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
-  PWM_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns a PWM channel status.
- * @pre     The PWM unit must have been activated using @p pwmStart().
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- * @param[in] channel   PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-#define pwm_lld_is_channel_enabled(pwmp, channel) FALSE
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_PWM_USE_PWM1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void pwm_lld_init(void);
-  void pwm_lld_start(PWMDriver *pwmp);
-  void pwm_lld_stop(PWMDriver *pwmp);
-  void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
-  void pwm_lld_enable_channel(PWMDriver *pwmp,
-                              pwmchannel_t channel,
-                              pwmcnt_t width);
-  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/sdc_lld.c b/os/hal/templates/sdc_lld.c
deleted file mode 100644
index c0d311b87..000000000
--- a/os/hal/templates/sdc_lld.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/sdc_lld.c
- * @brief   SDC Driver subsystem low level driver source template.
- *
- * @addtogroup SDC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SDC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   SDCD1 driver identifier.
- */
-#if PLATFORM_SDC_USE_SDC1 || defined(__DOXYGEN__)
-SDCDriver SDCD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SDC driver initialization.
- *
- * @notapi
- */
-void sdc_lld_init(void) {
-
-  sdcObjectInit(&SDCD1);
-}
-
-/**
- * @brief   Configures and activates the SDC peripheral.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_start(SDCDriver *sdcp) {
-
-  if (sdcp->state == BLK_STOP) {
-
-  }
-}
-
-/**
- * @brief   Deactivates the SDC peripheral.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_stop(SDCDriver *sdcp) {
-
-  if (sdcp->state != BLK_STOP) {
-
-  }
-}
-
-/**
- * @brief   Starts the SDIO clock and sets it to init mode (400kHz or less).
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_start_clk(SDCDriver *sdcp) {
-
-  (void)sdcp;
-}
-
-/**
- * @brief   Sets the SDIO clock to data mode (25MHz or less).
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_set_data_clk(SDCDriver *sdcp) {
-
-  (void)sdcp;
-}
-
-/**
- * @brief   Stops the SDIO clock.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-void sdc_lld_stop_clk(SDCDriver *sdcp) {
-
-  (void)sdcp;
-}
-
-/**
- * @brief   Switches the bus to 4 bits mode.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] mode      bus mode
- *
- * @notapi
- */
-void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
-
-  (void)sdcp;
-
-  switch (mode) {
-  case SDC_MODE_1BIT:
-
-    break;
-  case SDC_MODE_4BIT:
- 
-    break;
-  case SDC_MODE_8BIT:
-
-    break;
-  }
-}
-
-/**
- * @brief   Sends an SDIO command with no response expected.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] cmd       card command
- * @param[in] arg       command argument
- *
- * @notapi
- */
-void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
-
-  (void)sdcp;
-  (void)cmd;
-  (void)arg;
-}
-
-/**
- * @brief   Sends an SDIO command with a short response expected.
- * @note    The CRC is not verified.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] cmd       card command
- * @param[in] arg       command argument
- * @param[out] resp     pointer to the response buffer (one word)
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                              uint32_t *resp) {
-
-  (void)sdcp;
-  (void)cmd;
-  (void)arg;
-  (void)resp;
-
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Sends an SDIO command with a short response expected and CRC.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] cmd       card command
- * @param[in] arg       command argument
- * @param[out] resp     pointer to the response buffer (one word)
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                  uint32_t *resp) {
-
-  (void)sdcp;
-  (void)cmd;
-  (void)arg;
-  (void)resp;
-
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Sends an SDIO command with a long response expected and CRC.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] cmd       card command
- * @param[in] arg       command argument
- * @param[out] resp     pointer to the response buffer (four words)
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                 uint32_t *resp) {
-
-  (void)sdcp;
-  (void)cmd;
-  (void)arg;
-  (void)resp;
-
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Reads one or more blocks.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to read
- * @param[out] buf      pointer to the read buffer
- * @param[in] n         number of blocks to read
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
-                    uint8_t *buf, uint32_t n) {
-
-  (void)sdcp;
-  (void)startblk;
-  (void)buf;
-  (void)n;
-
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Writes one or more blocks.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to write
- * @param[out] buf      pointer to the write buffer
- * @param[in] n         number of blocks to write
- *
- * @return              The operation status.
- * @retval CH_SUCCESS  operation succeeded.
- * @retval CH_FAILED    operation failed.
- *
- * @notapi
- */
-bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
-                     const uint8_t *buf, uint32_t n) {
-
-  (void)sdcp;
-  (void)startblk;
-  (void)buf;
-  (void)n;
-
-  return CH_SUCCESS;
-}
-
-/**
- * @brief   Waits for card idle condition.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @return              The operation status.
- * @retval CH_SUCCESS   the operation succeeded.
- * @retval CH_FAILED    the operation failed.
- *
- * @api
- */
-bool_t sdc_lld_sync(SDCDriver *sdcp) {
-
-  (void)sdcp;
- 
-  return CH_SUCCESS;
-}
-
-#endif /* HAL_USE_SDC */
-
-/** @} */
diff --git a/os/hal/templates/sdc_lld.h b/os/hal/templates/sdc_lld.h
deleted file mode 100644
index aa3c7effd..000000000
--- a/os/hal/templates/sdc_lld.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/sdc_lld.h
- * @brief   SDC Driver subsystem low level driver header template.
- *
- * @addtogroup SDC
- * @{
- */
-
-#ifndef _SDC_LLD_H_
-#define _SDC_LLD_H_
-
-#if HAL_USE_SDC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   SDC driver enable switch.
- * @details If set to @p TRUE the support for SDC1 is included.
- */
-#if !defined(PLATFORM_SDC_USE_SDC1) || defined(__DOXYGEN__)
-#define PLATFORM_SDC_USE_SDC1               TRUE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of SDIO bus mode.
- */
-typedef enum {
-  SDC_MODE_1BIT = 0,
-  SDC_MODE_4BIT,
-  SDC_MODE_8BIT
-} sdcbusmode_t;
-
-/**
- * @brief   Type of card flags.
- */
-typedef uint32_t sdcmode_t;
-
-/**
- * @brief   SDC Driver condition flags type.
- */
-typedef uint32_t sdcflags_t;
-
-/**
- * @brief   Type of a structure representing an SDC driver.
- */
-typedef struct SDCDriver SDCDriver;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} SDCConfig;
-
-/**
- * @brief   @p SDCDriver specific methods.
- */
-#define _sdc_driver_methods                                                 \
-  _mmcsd_block_device_methods
-
-/**
- * @extends MMCSDBlockDeviceVMT
- *
- * @brief   @p SDCDriver virtual methods table.
- */
-struct SDCDriverVMT {
-  _sdc_driver_methods
-};
-
-/**
- * @brief   Structure representing an SDC driver.
- */
-struct SDCDriver {
-  /**
-   * @brief Virtual Methods Table.
-   */
-  const struct SDCDriverVMT *vmt;
-  _mmcsd_block_device_data
-  /**
-   * @brief Current configuration data.
-   */
-  const SDCConfig           *config;
-  /**
-   * @brief Various flags regarding the mounted card.
-   */
-  sdcmode_t                 cardmode;
-  /**
-   * @brief Errors flags.
-   */
-  sdcflags_t                errors;
-  /**
-   * @brief Card RCA.
-   */
-  uint32_t                  rca;
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    R1 response utilities
- * @{
- */
-/**
- * @brief   Evaluates to @p TRUE if the R1 response contains error flags.
- *
- * @param[in] r1        the r1 response
- */
-#define MMCSD_R1_ERROR(r1)              (((r1) & MMCSD_R1_ERROR_MASK) != 0)
-
-/**
- * @brief   Returns the status field of an R1 response.
- *
- * @param[in] r1        the r1 response
- */
-#define MMCSD_R1_STS(r1)                (((r1) >> 9) & 15)
-
-/**
- * @brief   Evaluates to @p TRUE if the R1 response indicates a locked card.
- *
- * @param[in] r1        the r1 response
- */
-#define MMCSD_R1_IS_CARD_LOCKED(r1)     (((r1) >> 21) & 1)
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_SDC_USE_SDC1 && !defined(__DOXYGEN__)
-extern SDCDriver SDCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sdc_lld_init(void);
-  void sdc_lld_start(SDCDriver *sdcp);
-  void sdc_lld_stop(SDCDriver *sdcp);
-  void sdc_lld_start_clk(SDCDriver *sdcp);
-  void sdc_lld_set_data_clk(SDCDriver *sdcp);
-  void sdc_lld_stop_clk(SDCDriver *sdcp);
-  void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
-  void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
-  bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                uint32_t *resp);
-  bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                    uint32_t *resp);
-  bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
-                                   uint32_t *resp);
-  bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
-                      uint8_t *buf, uint32_t n);
-  bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
-                       const uint8_t *buf, uint32_t n);
-  bool_t sdc_lld_sync(SDCDriver *sdcp);
-  bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp);
-  bool_t sdc_lld_is_write_protected(SDCDriver *sdcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SDC */
-
-#endif /* _SDC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/serial_lld.c b/os/hal/templates/serial_lld.c
deleted file mode 100644
index d6b861c12..000000000
--- a/os/hal/templates/serial_lld.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/serial_lld.c
- * @brief   Serial Driver subsystem low level driver source template.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   SD1 driver identifier.
- */
-#if PLATFORM_SERIAL_USE_SD1 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Driver default configuration.
- */
-static const SerialConfig default_config = {
-  38400
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if PLATFORM_SERIAL_USE_SD1
-  /* Driver initialization.*/
-  sdObjectInit(&SD1);
-#endif /* PLATFORM_SERIAL_USE_SD1 */
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_SERIAL_USE_SD1
-    if (&SD1 == sdp) {
-
-    }
-#endif /* PLATFORM_SD_USE_SD1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_SERIAL_USE_SD1
-    if (&SD1 == sdp) {
-
-    }
-#endif /* PLATFORM_SERIAL_USE_SD1 */
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/templates/serial_lld.h b/os/hal/templates/serial_lld.h
deleted file mode 100644
index 0e019948d..000000000
--- a/os/hal/templates/serial_lld.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/serial_lld.h
- * @brief   Serial Driver subsystem low level driver header template.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   SD1 driver enable switch.
- * @details If set to @p TRUE the support for SD1 is included.
- */
-#if !defined(PLATFORM_SERIAL_USE_SD1) || defined(__DOXYGEN__)
-#define PLATFORM_SERIAL_USE_SD1             FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /* End of the mandatory fields.*/
-} SerialConfig;
-
-/**
- * @brief @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_SERIAL_USE_SD1 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/spi_lld.c b/os/hal/templates/spi_lld.c
deleted file mode 100644
index a53f1ef43..000000000
--- a/os/hal/templates/spi_lld.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/spi_lld.c
- * @brief   SPI Driver subsystem low level driver source template.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   SPI1 driver identifier.
- */
-#if PLATFORM_SPI_USE_SPI1 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if PLATFORM_SPI_USE_SPI1
-  /* Driver initialization.*/
-  spiObjectInit(&SPID1);
-#endif /* PLATFORM_SPI_USE_SPI1 */
-}
-
-/**
- * @brief   Configures and activates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
-  if (spip->state == SPI_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_SPI_USE_SPI1
-    if (&SPID1 == spip) {
-
-    }
-#endif /* PLATFORM_SPI_USE_SPI1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the SPI peripheral.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
-  if (spip->state == SPI_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_SPI_USE_SPI1
-    if (&SPID1 == spip) {
-
-    }
-#endif /* PLATFORM_SPI_USE_SPI1 */
-  }
-}
-
-/**
- * @brief   Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
-  (void)spip;
-
-}
-
-/**
- * @brief   Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
-  (void)spip;
-
-}
-
-/**
- * @brief   Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- *          idle words on the SPI bus and ignores the received data.
- * @post    At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
-  (void)spip;
-  (void)n;
-
-}
-
-/**
- * @brief   Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- *          operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to be exchanged
- * @param[in] txbuf     the pointer to the transmit buffer
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
-                      const void *txbuf, void *rxbuf) {
-
-  (void)spip;
-  (void)n;
-  (void)txbuf;
-  (void)rxbuf;
-
-}
-
-/**
- * @brief   Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
-  (void)spip;
-  (void)n;
-  (void)txbuf;
-
-}
-
-/**
- * @brief   Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post    At the end of the operation the configured callback is invoked.
- * @note    The buffers are organized as uint8_t arrays for data sizes below or
- *          equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] n         number of words to receive
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
-  (void)spip;
-  (void)n;
-  (void)rxbuf;
-
-}
-
-/**
- * @brief   Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- *          synchronization method. This function is useful when exchanging
- *          small amount of data on high speed channels, usually in this
- *          situation is much more efficient just wait for completion using
- *          polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip      pointer to the @p SPIDriver object
- * @param[in] frame     the data frame to send over the SPI bus
- * @return              The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
-  (void)spip;
-  (void)frame;
-
-  return 0;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/templates/spi_lld.h b/os/hal/templates/spi_lld.h
deleted file mode 100644
index 690054f43..000000000
--- a/os/hal/templates/spi_lld.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/spi_lld.h
- * @brief   SPI Driver subsystem low level driver header template.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   SPI driver enable switch.
- * @details If set to @p TRUE the support for SPI1 is included.
- */
-#if !defined(PLATFORM_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define PLATFORM_SPI_USE_SPI1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief   SPI notification callback type.
- *
- * @param[in] spip      pointer to the @p SPIDriver object triggering the
- *                      callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief Operation complete callback.
-   */
-  spicallback_t         end_cb;
-  /* End of the mandatory fields.*/
-} SPIConfig;
-
-/**
- * @brief   Structure representing an SPI driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct SPIDriver {
-  /**
-   * @brief Driver state.
-   */
-  spistate_t            state;
-  /**
-   * @brief Current configuration data.
-   */
-  const SPIConfig       *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief Waiting thread.
-   */
-  Thread                *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief Mutex protecting the bus.
-   */
-  Mutex                 mutex;
-#elif CH_USE_SEMAPHORES
-  Semaphore             semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
-  SPI_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void spi_lld_init(void);
-  void spi_lld_start(SPIDriver *spip);
-  void spi_lld_stop(SPIDriver *spip);
-  void spi_lld_select(SPIDriver *spip);
-  void spi_lld_unselect(SPIDriver *spip);
-  void spi_lld_ignore(SPIDriver *spip, size_t n);
-  void spi_lld_exchange(SPIDriver *spip, size_t n,
-                        const void *txbuf, void *rxbuf);
-  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
-  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/st_lld.c b/os/hal/templates/st_lld.c
new file mode 100644
index 000000000..6e77aa5fa
--- /dev/null
+++ b/os/hal/templates/st_lld.c
@@ -0,0 +1,67 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    PLATFORM/st_lld.c
+ * @brief   ST Driver subsystem low level driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void) {
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/os/hal/templates/st_lld.h b/os/hal/templates/st_lld.h
new file mode 100644
index 000000000..dd743af51
--- /dev/null
+++ b/os/hal/templates/st_lld.h
@@ -0,0 +1,141 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    PLATFORM/st_lld.h
+ * @brief   ST Driver subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ *          include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef _ST_LLD_H_
+#define _ST_LLD_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the time counter value.
+ *
+ * @return              The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+  return (systime_t)0;
+}
+
+/**
+ * @brief   Starts the alarm.
+ * @note    Makes sure that no spurious alarms are triggered after
+ *          this call.
+ *
+ * @param[in] time      the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t time) {
+
+  (void)time;
+}
+
+/**
+ * @brief   Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+}
+
+/**
+ * @brief   Sets the alarm time.
+ *
+ * @param[in] time      the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t time) {
+
+  (void)time;
+}
+
+/**
+ * @brief   Returns the current alarm time.
+ *
+ * @return              The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+  return (systime_t)0;
+}
+
+/**
+ * @brief   Determines if the alarm is active.
+ *
+ * @return              The alarm status.
+ * @retval false        if the alarm is not active.
+ * @retval true         is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+  return false;
+}
+
+#endif /* _ST_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/templates/uart_lld.c b/os/hal/templates/uart_lld.c
deleted file mode 100644
index cc6fc27d4..000000000
--- a/os/hal/templates/uart_lld.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/uart_lld.c
- * @brief   UART Driver subsystem low level driver source template.
- *
- * @addtogroup UART
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   UART1 driver identifier.
- */
-#if PLATFORM_UART_USE_UART1 || defined(__DOXYGEN__)
-UARTDriver UARTD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level UART driver initialization.
- *
- * @notapi
- */
-void uart_lld_init(void) {
-
-#if PLATFORM_UART_USE_UART1
-  /* Driver initialization.*/
-  uartObjectInit(&UARTD1);
-#endif /* PLATFORM_UART_USE_UART1 */
-}
-
-/**
- * @brief   Configures and activates the UART peripheral.
- *
- * @param[in] uartp      pointer to the @p UARTDriver object
- *
- * @notapi
- */
-void uart_lld_start(UARTDriver *uartp) {
-
-  if (uartp->state == UART_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_UART_USE_UART1
-    if (&UARTD1 == uartp) {
-
-    }
-#endif /* PLATFORM_UART_USE_UART1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the UART peripheral.
- *
- * @param[in] uartp      pointer to the @p UARTDriver object
- *
- * @notapi
- */
-void uart_lld_stop(UARTDriver *uartp) {
-
-  if (uartp->state == UART_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_UART_USE_UART1
-    if (&UARTD1 == uartp) {
-
-    }
-#endif /* PLATFORM_UART_USE_UART1 */
-  }
-}
-
-/**
- * @brief   Starts a transmission on the UART peripheral.
- * @note    The buffers are organized as uint8_t arrays for data sizes below
- *          or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] n         number of data frames to send
- * @param[in] txbuf     the pointer to the transmit buffer
- *
- * @notapi
- */
-void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
-
-  (void)uartp;
-  (void)n;
-  (void)txbuf;
-
-}
-
-/**
- * @brief   Stops any ongoing transmission.
- * @note    Stopping a transmission also suppresses the transmission callbacks.
- *
- * @param[in] uartp      pointer to the @p UARTDriver object
- *
- * @return              The number of data frames not transmitted by the
- *                      stopped transmit operation.
- *
- * @notapi
- */
-size_t uart_lld_stop_send(UARTDriver *uartp) {
-
-  (void)uartp;
-
-  return 0;
-}
-
-/**
- * @brief   Starts a receive operation on the UART peripheral.
- * @note    The buffers are organized as uint8_t arrays for data sizes below
- *          or equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- * @param[in] n         number of data frames to send
- * @param[out] rxbuf    the pointer to the receive buffer
- *
- * @notapi
- */
-void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
-
-  (void)uartp;
-  (void)n;
-  (void)rxbuf;
-
-}
-
-/**
- * @brief   Stops any ongoing receive operation.
- * @note    Stopping a receive operation also suppresses the receive callbacks.
- *
- * @param[in] uartp      pointer to the @p UARTDriver object
- *
- * @return              The number of data frames not received by the
- *                      stopped receive operation.
- *
- * @notapi
- */
-size_t uart_lld_stop_receive(UARTDriver *uartp) {
-
-  (void)uartp;
-
-  return 0;
-}
-
-#endif /* HAL_USE_UART */
-
-/** @} */
diff --git a/os/hal/templates/uart_lld.h b/os/hal/templates/uart_lld.h
deleted file mode 100644
index 6e34fa108..000000000
--- a/os/hal/templates/uart_lld.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/uart_lld.h
- * @brief   UART Driver subsystem low level driver header template.
- *
- * @addtogroup UART
- * @{
- */
-
-#ifndef _UART_LLD_H_
-#define _UART_LLD_H_
-
-#if HAL_USE_UART || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   UART driver enable switch.
- * @details If set to @p TRUE the support for UART1 is included.
- */
-#if !defined(PLATFORM_UART_USE_UART1) || defined(__DOXYGEN__)
-#define PLATFORM_UART_USE_UART1             FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   UART driver condition flags type.
- */
-typedef uint32_t uartflags_t;
-
-/**
- * @brief   Type of structure representing an UART driver.
- */
-typedef struct UARTDriver UARTDriver;
-
-/**
- * @brief   Generic UART notification callback type.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object
- */
-typedef void (*uartcb_t)(UARTDriver *uartp);
-
-/**
- * @brief   Character received UART notification callback type.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object triggering the
- *                      callback
- * @param[in] c         received character
- */
-typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
-
-/**
- * @brief   Receive error UART notification callback type.
- *
- * @param[in] uartp     pointer to the @p UARTDriver object triggering the
- *                      callback
- * @param[in] e         receive error mask
- */
-typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
-
-/**
- * @brief   Driver configuration structure.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-typedef struct {
-  /**
-   * @brief End of transmission buffer callback.
-   */
-  uartcb_t                  txend1_cb;
-  /**
-   * @brief Physical end of transmission callback.
-   */
-  uartcb_t                  txend2_cb;
-  /**
-   * @brief Receive buffer filled callback.
-   */
-  uartcb_t                  rxend_cb;
-  /**
-   * @brief Character received while out if the @p UART_RECEIVE state.
-   */
-  uartccb_t                 rxchar_cb;
-  /**
-   * @brief Receive error callback.
-   */
-  uartecb_t                 rxerr_cb;
-  /* End of the mandatory fields.*/
-} UARTConfig;
-
-/**
- * @brief   Structure representing an UART driver.
- * @note    Implementations may extend this structure to contain more,
- *          architecture dependent, fields.
- */
-struct UARTDriver {
-  /**
-   * @brief Driver state.
-   */
-  uartstate_t               state;
-  /**
-   * @brief Transmitter state.
-   */
-  uarttxstate_t             txstate;
-  /**
-   * @brief Receiver state.
-   */
-  uartrxstate_t             rxstate;
-  /**
-   * @brief Current configuration data.
-   */
-  const UARTConfig          *config;
-#if defined(UART_DRIVER_EXT_FIELDS)
-  UART_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_UART_USE_UART1 && !defined(__DOXYGEN__)
-extern UARTDriver UARTD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void uart_lld_init(void);
-  void uart_lld_start(UARTDriver *uartp);
-  void uart_lld_stop(UARTDriver *uartp);
-  void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
-  size_t uart_lld_stop_send(UARTDriver *uartp);
-  void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
-  size_t uart_lld_stop_receive(UARTDriver *uartp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_UART */
-
-#endif /* _UART_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/templates/usb_lld.c b/os/hal/templates/usb_lld.c
deleted file mode 100644
index 9a63b149c..000000000
--- a/os/hal/templates/usb_lld.c
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/usb_lld.c
- * @brief   USB Driver subsystem low level driver source template.
- *
- * @addtogroup USB
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   USB1 driver identifier.
- */
-#if PLATFORM_USB_USE_USB1 || defined(__DOXYGEN__)
-USBDriver USBD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EP0 state.
- * @note    It is an union because IN and OUT endpoints are never used at the
- *          same time for EP0.
- */
-static union {
-  /**
-   * @brief   IN EP0 state.
-   */
-  USBInEndpointState in;
-  /**
-   * @brief   OUT EP0 state.
-   */
-  USBOutEndpointState out;
-} ep0_state;
-
-/**
- * @brief   EP0 initialization structure.
- */
-static const USBEndpointConfig ep0config = {
-  USB_EP_MODE_TYPE_CTRL,
-  _usb_ep0setup,
-  _usb_ep0in,
-  _usb_ep0out,
-  0x40,
-  0x40,
-  &ep0_state.in,
-  &ep0_state.out
-};
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers and threads.                                    */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level USB driver initialization.
- *
- * @notapi
- */
-void usb_lld_init(void) {
-
-#if PLATFORM_USB_USE_USB1
-  /* Driver initialization.*/
-  usbObjectInit(&USBD1);
-#endif /* PLATFORM_USB_USE_USB1 */
-}
-
-/**
- * @brief   Configures and activates the USB peripheral.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_start(USBDriver *usbp) {
-
-  if (usbp->state == USB_STOP) {
-    /* Enables the peripheral.*/
-#if PLATFORM_USB_USE_USB1
-    if (&USBD1 == usbp) {
-
-    }
-#endif /* PLATFORM_USB_USE_USB1 */
-  }
-  /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief   Deactivates the USB peripheral.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_stop(USBDriver *usbp) {
-
-  if (usbp->state == USB_READY) {
-    /* Resets the peripheral.*/
-
-    /* Disables the peripheral.*/
-#if PLATFORM_USB_USE_USB1
-    if (&USBD1 == usbp) {
-
-    }
-#endif /* PLATFORM_USB_USE_USB1 */
-  }
-}
-
-/**
- * @brief   USB low level reset routine.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_reset(USBDriver *usbp) {
-
-  /* Post reset initialization.*/
-
-  /* EP0 initialization.*/
-  usbp->epc[0] = &ep0config;
-  usb_lld_init_endpoint(usbp, 0);
-}
-
-/**
- * @brief   Sets the USB address.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_set_address(USBDriver *usbp) {
-
-  (void)usbp;
-
-}
-
-/**
- * @brief   Enables an endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-}
-
-/**
- * @brief   Disables all the active endpoints except the endpoint zero.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_disable_endpoints(USBDriver *usbp) {
-
-  (void)usbp;
-
-}
-
-/**
- * @brief   Returns the status of an OUT endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED  The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE   The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-  return EP_STATUS_DISABLED;
-}
-
-/**
- * @brief   Returns the status of an IN endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED  The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE   The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-  return EP_STATUS_DISABLED;
-}
-
-/**
- * @brief   Reads a setup packet from the dedicated packet buffer.
- * @details This function must be invoked in the context of the @p setup_cb
- *          callback in order to read the received setup packet.
- * @pre     In order to use this function the endpoint must have been
- *          initialized as a control endpoint.
- * @post    The endpoint is ready to accept another packet.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @param[out] buf      buffer where to copy the packet data
- *
- * @notapi
- */
-void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
-
-  (void)usbp;
-  (void)ep;
-  (void)buf;
-
-}
-
-/**
- * @brief   Prepares for a receive operation.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-}
-
-/**
- * @brief   Prepares for a transmit operation.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-}
-
-/**
- * @brief   Starts a receive operation on an OUT endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-}
-
-/**
- * @brief   Starts a transmit operation on an IN endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-}
-
-/**
- * @brief   Brings an OUT endpoint in the stalled state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-}
-
-/**
- * @brief   Brings an IN endpoint in the stalled state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-}
-
-/**
- * @brief   Brings an OUT endpoint in the active state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-}
-
-/**
- * @brief   Brings an IN endpoint in the active state.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
-
-  (void)usbp;
-  (void)ep;
-
-}
-
-#endif /* HAL_USE_USB */
-
-/** @} */
diff --git a/os/hal/templates/usb_lld.h b/os/hal/templates/usb_lld.h
deleted file mode 100644
index 7dbf8b4b9..000000000
--- a/os/hal/templates/usb_lld.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    templates/usb_lld.h
- * @brief   USB Driver subsystem low level driver header template.
- *
- * @addtogroup USB
- * @{
- */
-
-#ifndef _USB_LLD_H_
-#define _USB_LLD_H_
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Maximum endpoint address.
- */
-#define USB_MAX_ENDPOINTS                   4
-
-/**
- * @brief   The address can be changed immediately upon packet reception.
- */
-#define USB_SET_ADDRESS_MODE                USB_EARLY_SET_ADDRESS
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   USB driver enable switch.
- * @details If set to @p TRUE the support for USB1 is included.
- */
-#if !defined(PLATFORM_USB_USE_USB1) || defined(__DOXYGEN__)
-#define PLATFORM_USB_USE_USB1               FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of an IN endpoint state structure.
- */
-typedef struct {
-  /**
-   * @brief   Buffer mode, queue or linear.
-   */
-  bool_t                        txqueued;
-  /**
-   * @brief   Requested transmit transfer size.
-   */
-  size_t                        txsize;
-  /**
-   * @brief   Transmitted bytes so far.
-   */
-  size_t                        txcnt;
-  union {
-    struct {
-      /**
-       * @brief   Pointer to the transmission linear buffer.
-       */
-      const uint8_t             *txbuf;
-    } linear;
-    struct {
-      /**
-       * @brief   Pointer to the output queue.
-       */
-      OutputQueue               *txqueue;
-    } queue;
-  } mode;
-} USBInEndpointState;
-
-/**
- * @brief   Type of an OUT endpoint state structure.
- */
-typedef struct {
-  /**
-   * @brief   Buffer mode, queue or linear.
-   */
-  bool_t                        rxqueued;
-  /**
-   * @brief   Requested receive transfer size.
-   */
-  size_t                        rxsize;
-  /**
-   * @brief   Received bytes so far.
-   */
-  size_t                        rxcnt;
-  union {
-    struct {
-      /**
-       * @brief   Pointer to the receive linear buffer.
-       */
-      uint8_t                   *rxbuf;
-    } linear;
-    struct {
-      /**
-       * @brief   Pointer to the input queue.
-       */
-      InputQueue               *rxqueue;
-    } queue;
-  } mode;
-} USBOutEndpointState;
-
-/**
- * @brief   Type of an USB endpoint configuration structure.
- * @note    Platform specific restrictions may apply to endpoints.
- */
-typedef struct {
-  /**
-   * @brief   Type and mode of the endpoint.
-   */
-  uint32_t                      ep_mode;
-  /**
-   * @brief   Setup packet notification callback.
-   * @details This callback is invoked when a setup packet has been
-   *          received.
-   * @post    The application must immediately call @p usbReadPacket() in
-   *          order to access the received packet.
-   * @note    This field is only valid for @p USB_EP_MODE_TYPE_CTRL
-   *          endpoints, it should be set to @p NULL for other endpoint
-   *          types.
-   */
-  usbepcallback_t               setup_cb;
-  /**
-   * @brief   IN endpoint notification callback.
-   * @details This field must be set to @p NULL if the IN endpoint is not
-   *          used.
-   */
-  usbepcallback_t               in_cb;
-  /**
-   * @brief   OUT endpoint notification callback.
-   * @details This field must be set to @p NULL if the OUT endpoint is not
-   *          used.
-   */
-  usbepcallback_t               out_cb;
-  /**
-   * @brief   IN endpoint maximum packet size.
-   * @details This field must be set to zero if the IN endpoint is not
-   *          used.
-   */
-  uint16_t                      in_maxsize;
-  /**
-   * @brief   OUT endpoint maximum packet size.
-   * @details This field must be set to zero if the OUT endpoint is not
-   *          used.
-   */
-  uint16_t                      out_maxsize;
-  /**
-   * @brief   @p USBEndpointState associated to the IN endpoint.
-   * @details This structure maintains the state of the IN endpoint.
-   */
-  USBInEndpointState            *in_state;
-  /**
-   * @brief   @p USBEndpointState associated to the OUT endpoint.
-   * @details This structure maintains the state of the OUT endpoint.
-   */
-  USBOutEndpointState           *out_state;
-  /* End of the mandatory fields.*/
-} USBEndpointConfig;
-
-/**
- * @brief   Type of an USB driver configuration structure.
- */
-typedef struct {
-  /**
-   * @brief   USB events callback.
-   * @details This callback is invoked when an USB driver event is registered.
-   */
-  usbeventcb_t                  event_cb;
-  /**
-   * @brief   Device GET_DESCRIPTOR request callback.
-   * @note    This callback is mandatory and cannot be set to @p NULL.
-   */
-  usbgetdescriptor_t            get_descriptor_cb;
-  /**
-   * @brief   Requests hook callback.
-   * @details This hook allows to be notified of standard requests or to
-   *          handle non standard requests.
-   */
-  usbreqhandler_t               requests_hook_cb;
-  /**
-   * @brief   Start Of Frame callback.
-   */
-  usbcallback_t                 sof_cb;
-  /* End of the mandatory fields.*/
-} USBConfig;
-
-/**
- * @brief   Structure representing an USB driver.
- */
-struct USBDriver {
-  /**
-   * @brief   Driver state.
-   */
-  usbstate_t                    state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const USBConfig               *config;
-  /**
-   * @brief   Bit map of the transmitting IN endpoints.
-   */
-  uint16_t                      transmitting;
-  /**
-   * @brief   Bit map of the receiving OUT endpoints.
-   */
-  uint16_t                      receiving;
-  /**
-   * @brief   Active endpoints configurations.
-   */
-  const USBEndpointConfig       *epc[USB_MAX_ENDPOINTS + 1];
-  /**
-   * @brief   Fields available to user, it can be used to associate an
-   *          application-defined handler to an IN endpoint.
-   * @note    The base index is one, the endpoint zero does not have a
-   *          reserved element in this array.
-   */
-  void                          *in_params[USB_MAX_ENDPOINTS];
-  /**
-   * @brief   Fields available to user, it can be used to associate an
-   *          application-defined handler to an OUT endpoint.
-   * @note    The base index is one, the endpoint zero does not have a
-   *          reserved element in this array.
-   */
-  void                          *out_params[USB_MAX_ENDPOINTS];
-  /**
-   * @brief   Endpoint 0 state.
-   */
-  usbep0state_t                 ep0state;
-  /**
-   * @brief   Next position in the buffer to be transferred through endpoint 0.
-   */
-  uint8_t                       *ep0next;
-  /**
-   * @brief   Number of bytes yet to be transferred through endpoint 0.
-   */
-  size_t                        ep0n;
-  /**
-   * @brief   Endpoint 0 end transaction callback.
-   */
-  usbcallback_t                 ep0endcb;
-  /**
-   * @brief   Setup packet buffer.
-   */
-  uint8_t                       setup[8];
-  /**
-   * @brief   Current USB device status.
-   */
-  uint16_t                      status;
-  /**
-   * @brief   Assigned USB address.
-   */
-  uint8_t                       address;
-  /**
-   * @brief   Current USB device configuration.
-   */
-  uint8_t                       configuration;
-#if defined(USB_DRIVER_EXT_FIELDS)
-  USB_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @brief   Returns the exact size of a receive transaction.
- * @details The received size can be different from the size specified in
- *          @p usbStartReceiveI() because the last packet could have a size
- *          different from the expected one.
- * @pre     The OUT endpoint must have been configured in transaction mode
- *          in order to use this function.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- * @return              Received data size.
- *
- * @notapi
- */
-#define usb_lld_get_transaction_size(usbp, ep)                              \
-  ((usbp)->epc[ep]->out_state->rxcnt)
-
-/**
- * @brief   Connects the USB device.
- *
- * @api
- */
-#define usb_lld_connect_bus(usbp)
-
-/**
- * @brief   Disconnect the USB device.
- *
- * @api
- */
-#define usb_lld_disconnect_bus(usbp)
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if PLATFORM_USB_USE_USB1 && !defined(__DOXYGEN__)
-extern USBDriver USBD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void usb_lld_init(void);
-  void usb_lld_start(USBDriver *usbp);
-  void usb_lld_stop(USBDriver *usbp);
-  void usb_lld_reset(USBDriver *usbp);
-  void usb_lld_set_address(USBDriver *usbp);
-  void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
-  void usb_lld_disable_endpoints(USBDriver *usbp);
-  usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
-  usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
-  void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
-  void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
-  void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
-  void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
-  void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
-  void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_USB */
-
-#endif /* _USB_LLD_H_ */
-
-/** @} */
diff --git a/os/kernel/include/ch.h b/os/kernel/include/ch.h
deleted file mode 100644
index db7c45501..000000000
--- a/os/kernel/include/ch.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ch.h
- * @brief   ChibiOS/RT main include file.
- * @details This header includes all the required kernel headers so it is the
- *          only kernel header you usually want to include in your application.
- *
- * @addtogroup kernel_info
- * @details Kernel related info.
- * @{
- */
-
-#ifndef _CH_H_
-#define _CH_H_
-
-/**
- * @brief   ChibiOS/RT identification macro.
- */
-#define _CHIBIOS_RT_
-
-/**
- * @brief   Kernel version string.
- */
-#define CH_KERNEL_VERSION       "2.7.0unstable"
-
-/**
- * @name    Kernel version
- * @{
- */
-/**
- * @brief   Kernel version major number.
- */
-#define CH_KERNEL_MAJOR         2
-
-/**
- * @brief   Kernel version minor number.
- */
-#define CH_KERNEL_MINOR         7
-
-/**
- * @brief   Kernel version patch number.
- */
-#define CH_KERNEL_PATCH         0
-/** @} */
-
-/**
- * @name    Common constants
- */
-/**
- * @brief   Generic 'false' boolean constant.
- */
-#if !defined(FALSE) || defined(__DOXYGEN__)
-#define FALSE                   0
-#endif
-
-/**
- * @brief   Generic 'true' boolean constant.
- */
-#if !defined(TRUE) || defined(__DOXYGEN__)
-#define TRUE                    (!FALSE)
-#endif
-
-/**
- * @brief   Generic success constant.
- * @details This constant is functionally equivalent to @p FALSE but more
- *          readable, it can be used as return value of all those functions
- *          returning a @p bool_t as a status indicator.
- */
-#if !defined(CH_SUCCESS) || defined(__DOXYGEN__)
-#define CH_SUCCESS              FALSE
-#endif
-
-/**
- * @brief   Generic failure constant.
- * @details This constant is functionally equivalent to @p TRUE but more
- *          readable, it can be used as return value of all those functions
- *          returning a @p bool_t as a status indicator.
- */
-#if !defined(CH_FAILED) || defined(__DOXYGEN__)
-#define CH_FAILED               TRUE
-#endif
-/** @} */
-
-#include "chconf.h"
-#include "chtypes.h"
-#include "chlists.h"
-#include "chcore.h"
-#include "chsys.h"
-#include "chvt.h"
-#include "chschd.h"
-#include "chsem.h"
-#include "chbsem.h"
-#include "chmtx.h"
-#include "chcond.h"
-#include "chevents.h"
-#include "chmsg.h"
-#include "chmboxes.h"
-#include "chmemcore.h"
-#include "chheap.h"
-#include "chmempools.h"
-#include "chthreads.h"
-#include "chdynamic.h"
-#include "chregistry.h"
-#include "chinline.h"
-#include "chqueues.h"
-#include "chstreams.h"
-#include "chfiles.h"
-#include "chdebug.h"
-
-#if !defined(__DOXYGEN__)
-extern WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE);
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _idle_thread(void *p);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CH_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chbsem.h b/os/kernel/include/chbsem.h
deleted file mode 100644
index 0cc6f8a95..000000000
--- a/os/kernel/include/chbsem.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chbsem.h
- * @brief   Binary semaphores structures and macros.
- *
- * @addtogroup binary_semaphores
- * @details Binary semaphores related APIs and services.
- *
- *          <h2>Operation mode</h2>
- *          Binary semaphores are implemented as a set of macros that use the
- *          existing counting semaphores primitives. The difference between
- *          counting and binary semaphores is that the counter of binary
- *          semaphores is not allowed to grow above the value 1. Repeated
- *          signal operation are ignored. A binary semaphore can thus have
- *          only two defined states:
- *          - <b>Taken</b>, when its counter has a value of zero or lower
- *            than zero. A negative number represent the number of threads
- *            queued on the binary semaphore.
- *          - <b>Not taken</b>, when its counter has a value of one.
- *          .
- *          Binary semaphores are different from mutexes because there is no
- *          the concept of ownership, a binary semaphore can be taken by a
- *          thread and signaled by another thread or an interrupt handler,
- *          mutexes can only be taken and released by the same thread. Another
- *          difference is that binary semaphores, unlike mutexes, do not
- *          implement the priority inheritance protocol.<br>
- *          In order to use the binary semaphores APIs the @p CH_USE_SEMAPHORES
- *          option must be enabled in @p chconf.h.
- * @{
- */
-
-#ifndef _CHBSEM_H_
-#define _CHBSEM_H_
-
-#if CH_USE_SEMAPHORES || defined(__DOXYGEN__)
-
-/**
- * @extends Semaphore
- *
- * @brief   Binary semaphore type.
- */
-typedef struct  {
-  Semaphore             bs_sem;
-} BinarySemaphore;
-
-/**
- * @brief   Data part of a static semaphore initializer.
- * @details This macro should be used when statically initializing a semaphore
- *          that is part of a bigger structure.
- *
- * @param[in] name      the name of the semaphore variable
- * @param[in] taken     the semaphore initial state
- */
-#define _BSEMAPHORE_DATA(name, taken)                                       \
-  {_SEMAPHORE_DATA(name.bs_sem, ((taken) ? 0 : 1))}
-
-/**
- * @brief   Static semaphore initializer.
- * @details Statically initialized semaphores require no explicit
- *          initialization using @p chBSemInit().
- *
- * @param[in] name      the name of the semaphore variable
- * @param[in] taken     the semaphore initial state
- */
-#define BSEMAPHORE_DECL(name, taken)                                        \
-  BinarySemaphore name = _BSEMAPHORE_DATA(name, taken)
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Initializes a binary semaphore.
- *
- * @param[out] bsp      pointer to a @p BinarySemaphore structure
- * @param[in] taken     initial state of the binary semaphore:
- *                      - @a FALSE, the initial state is not taken.
- *                      - @a TRUE, the initial state is taken.
- *                      .
- *
- * @init
- */
-#define chBSemInit(bsp, taken) chSemInit(&(bsp)->bs_sem, (taken) ? 0 : 1)
-
-/**
- * @brief   Wait operation on the binary semaphore.
- *
- * @param[in] bsp       pointer to a @p BinarySemaphore structure
- * @return              A message specifying how the invoking thread has been
- *                      released from the semaphore.
- * @retval RDY_OK       if the binary semaphore has been successfully taken.
- * @retval RDY_RESET    if the binary semaphore has been reset using
- *                      @p bsemReset().
- *
- * @api
- */
-#define chBSemWait(bsp) chSemWait(&(bsp)->bs_sem)
-
-/**
- * @brief   Wait operation on the binary semaphore.
- *
- * @param[in] bsp       pointer to a @p BinarySemaphore structure
- * @return              A message specifying how the invoking thread has been
- *                      released from the semaphore.
- * @retval RDY_OK       if the binary semaphore has been successfully taken.
- * @retval RDY_RESET    if the binary semaphore has been reset using
- *                      @p bsemReset().
- *
- * @sclass
- */
-#define chBSemWaitS(bsp) chSemWaitS(&(bsp)->bs_sem)
-
-/**
- * @brief   Wait operation on the binary semaphore.
- *
- * @param[in] bsp       pointer to a @p BinarySemaphore structure
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              A message specifying how the invoking thread has been
- *                      released from the semaphore.
- * @retval RDY_OK       if the binary semaphore has been successfully taken.
- * @retval RDY_RESET    if the binary semaphore has been reset using
- *                      @p bsemReset().
- * @retval RDY_TIMEOUT  if the binary semaphore has not been signaled or reset
- *                      within the specified timeout.
- *
- * @api
- */
-#define chBSemWaitTimeout(bsp, time) chSemWaitTimeout(&(bsp)->bs_sem, (time))
-
-/**
- * @brief   Wait operation on the binary semaphore.
- *
- * @param[in] bsp       pointer to a @p BinarySemaphore structure
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              A message specifying how the invoking thread has been
- *                      released from the semaphore.
- * @retval RDY_OK       if the binary semaphore has been successfully taken.
- * @retval RDY_RESET    if the binary semaphore has been reset using
- *                      @p bsemReset().
- * @retval RDY_TIMEOUT  if the binary semaphore has not been signaled or reset
- *                      within the specified timeout.
- *
- * @sclass
- */
-#define chBSemWaitTimeoutS(bsp, time) chSemWaitTimeoutS(&(bsp)->bs_sem, (time))
-
-/**
- * @brief   Reset operation on the binary semaphore.
- * @note    The released threads can recognize they were waked up by a reset
- *          rather than a signal because the @p bsemWait() will return
- *          @p RDY_RESET instead of @p RDY_OK.
- *
- * @param[in] bsp       pointer to a @p BinarySemaphore structure
- * @param[in] taken     new state of the binary semaphore
- *                      - @a FALSE, the new state is not taken.
- *                      - @a TRUE, the new state is taken.
- *                      .
- *
- * @api
- */
-#define chBSemReset(bsp, taken) chSemReset(&(bsp)->bs_sem, (taken) ? 0 : 1)
-
-/**
- * @brief   Reset operation on the binary semaphore.
- * @note    The released threads can recognize they were waked up by a reset
- *          rather than a signal because the @p bsemWait() will return
- *          @p RDY_RESET instead of @p RDY_OK.
- * @note    This function does not reschedule.
- *
- * @param[in] bsp       pointer to a @p BinarySemaphore structure
- * @param[in] taken     new state of the binary semaphore
- *                      - @a FALSE, the new state is not taken.
- *                      - @a TRUE, the new state is taken.
- *                      .
- *
- * @iclass
- */
-#define chBSemResetI(bsp, taken) chSemResetI(&(bsp)->bs_sem, (taken) ? 0 : 1)
-
-/**
- * @brief   Performs a signal operation on a binary semaphore.
- *
- * @param[in] bsp       pointer to a @p BinarySemaphore structure
- *
- * @api
- */
-#define chBSemSignal(bsp) {                                                 \
-  chSysLock();                                                              \
-  chBSemSignalI((bsp));                                                     \
-  chSchRescheduleS();                                                       \
-  chSysUnlock();                                                            \
-}
-
-/**
- * @brief   Performs a signal operation on a binary semaphore.
- * @note    This function does not reschedule.
- *
- * @param[in] bsp       pointer to a @p BinarySemaphore structure
- *
- * @iclass
- */
-#define chBSemSignalI(bsp) {                                                \
-  if ((bsp)->bs_sem.s_cnt < 1)                                              \
-    chSemSignalI(&(bsp)->bs_sem);                                           \
-}
-
-/**
- * @brief   Returns the binary semaphore current state.
- *
- * @param[in] bsp       pointer to a @p BinarySemaphore structure
- * @return              The binary semaphore current state.
- * @retval FALSE        if the binary semaphore is not taken.
- * @retval TRUE         if the binary semaphore is taken.
- *
- * @iclass
- */
-#define chBSemGetStateI(bsp) ((bsp)->bs_sem.s_cnt > 0 ? FALSE : TRUE)
-/** @} */
-
-#endif /* CH_USE_SEMAPHORES */
-
-#endif /* _CHBSEM_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chcond.h b/os/kernel/include/chcond.h
deleted file mode 100644
index 7557243cd..000000000
--- a/os/kernel/include/chcond.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-/*
-   Concepts and parts of this file have been contributed by Leon Woestenberg.
- */
-
-/**
- * @file    chcond.h
- * @brief   Condition Variables macros and structures.
- *
- * @addtogroup condvars
- * @{
- */
-
-#ifndef _CHCOND_H_
-#define _CHCOND_H_
-
-#if CH_USE_CONDVARS || defined(__DOXYGEN__)
-
-/*
- * Module dependencies check.
- */
-#if !CH_USE_MUTEXES
-#error "CH_USE_CONDVARS requires CH_USE_MUTEXES"
-#endif
-
-/**
- * @brief   CondVar structure.
- */
-typedef struct CondVar {
-  ThreadsQueue          c_queue;        /**< @brief CondVar threads queue.*/
-} CondVar;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void chCondInit(CondVar *cp);
-  void chCondSignal(CondVar *cp);
-  void chCondSignalI(CondVar *cp);
-  void chCondBroadcast(CondVar *cp);
-  void chCondBroadcastI(CondVar *cp);
-  msg_t chCondWait(CondVar *cp);
-  msg_t chCondWaitS(CondVar *cp);
-#if CH_USE_CONDVARS_TIMEOUT
-  msg_t chCondWaitTimeout(CondVar *cp, systime_t time);
-  msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @brief Data part of a static condition variable initializer.
- * @details This macro should be used when statically initializing a condition
- *          variable that is part of a bigger structure.
- *
- * @param[in] name      the name of the condition variable
- */
-#define _CONDVAR_DATA(name) {_THREADSQUEUE_DATA(name.c_queue)}
-
-/**
- * @brief Static condition variable initializer.
- * @details Statically initialized condition variables require no explicit
- *          initialization using @p chCondInit().
- *
- * @param[in] name      the name of the condition variable
- */
-#define CONDVAR_DECL(name) CondVar name = _CONDVAR_DATA(name)
-
-#endif /* CH_USE_CONDVARS */
-
-#endif /* _CHCOND_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chdebug.h b/os/kernel/include/chdebug.h
deleted file mode 100644
index 4477d3087..000000000
--- a/os/kernel/include/chdebug.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chdebug.h
- * @brief   Debug macros and structures.
- *
- * @addtogroup debug
- * @{
- */
-
-#ifndef _CHDEBUG_H_
-#define _CHDEBUG_H_
-
-#if CH_DBG_ENABLE_ASSERTS     || CH_DBG_ENABLE_CHECKS      ||               \
-    CH_DBG_ENABLE_STACK_CHECK || CH_DBG_SYSTEM_STATE_CHECK
-#define CH_DBG_ENABLED              TRUE
-#else
-#define CH_DBG_ENABLED              FALSE
-#endif
-
-#define __QUOTE_THIS(p) #p
-
-/*===========================================================================*/
-/**
- * @name    Debug related settings
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Trace buffer entries.
- */
-#ifndef CH_TRACE_BUFFER_SIZE
-#define CH_TRACE_BUFFER_SIZE        64
-#endif
-
-/**
- * @brief   Fill value for thread stack area in debug mode.
- */
-#ifndef CH_STACK_FILL_VALUE
-#define CH_STACK_FILL_VALUE         0x55
-#endif
-
-/**
- * @brief   Fill value for thread area in debug mode.
- * @note    The chosen default value is 0xFF in order to make evident which
- *          thread fields were not initialized when inspecting the memory with
- *          a debugger. A uninitialized field is not an error in itself but it
- *          better to know it.
- */
-#ifndef CH_THREAD_FILL_VALUE
-#define CH_THREAD_FILL_VALUE        0xFF
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* System state checker related code and variables.                          */
-/*===========================================================================*/
-
-#if !CH_DBG_SYSTEM_STATE_CHECK
-#define dbg_enter_lock()
-#define dbg_leave_lock()
-#define dbg_check_disable()
-#define dbg_check_suspend()
-#define dbg_check_enable()
-#define dbg_check_lock()
-#define dbg_check_unlock()
-#define dbg_check_lock_from_isr()
-#define dbg_check_unlock_from_isr()
-#define dbg_check_enter_isr()
-#define dbg_check_leave_isr()
-#define chDbgCheckClassI()
-#define chDbgCheckClassS()
-#else
-#define dbg_enter_lock() (dbg_lock_cnt = 1)
-#define dbg_leave_lock() (dbg_lock_cnt = 0)
-#endif
-
-/*===========================================================================*/
-/* Trace related structures and macros.                                      */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
-/**
- * @brief   Trace buffer record.
- */
-typedef struct {
-  systime_t             se_time;    /**< @brief Time of the switch event.   */
-  Thread                *se_tp;     /**< @brief Switched in thread.         */
-  void                  *se_wtobjp; /**< @brief Object where going to sleep.*/
-  uint8_t               se_state;   /**< @brief Switched out thread state.  */
-} ch_swc_event_t;
-
-/**
- * @brief   Trace buffer header.
- */
-typedef struct {
-  unsigned              tb_size;    /**< @brief Trace buffer size (entries).*/
-  ch_swc_event_t        *tb_ptr;    /**< @brief Pointer to the buffer front.*/
-  /** @brief Ring buffer.*/
-  ch_swc_event_t        tb_buffer[CH_TRACE_BUFFER_SIZE];
-} ch_trace_buffer_t;
-
-#if !defined(__DOXYGEN__)
-extern ch_trace_buffer_t dbg_trace_buffer;
-#endif
-
-#endif /* CH_DBG_ENABLE_TRACE */
-
-#if !CH_DBG_ENABLE_TRACE
-/* When the trace feature is disabled this function is replaced by an empty
-   macro.*/
-#define dbg_trace(otp)
-#endif
-
-/*===========================================================================*/
-/* Parameters checking related macros.                                       */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLE_CHECKS || defined(__DOXYGEN__)
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Function parameters check.
- * @details If the condition check fails then the kernel panics and halts.
- * @note    The condition is tested only if the @p CH_DBG_ENABLE_CHECKS switch
- *          is specified in @p chconf.h else the macro does nothing.
- *
- * @param[in] c         the condition to be verified to be true
- * @param[in] func      the undecorated function name
- *
- * @api
- */
-#if !defined(chDbgCheck)
-#define chDbgCheck(c, func) {                                               \
-  if (!(c))                                                                 \
-    chDbgPanic(__QUOTE_THIS(func)"()");                                     \
-}
-#endif /* !defined(chDbgCheck) */
-/** @} */
-#else /* !CH_DBG_ENABLE_CHECKS */
-#define chDbgCheck(c, func) {                                               \
-  (void)(c), (void)__QUOTE_THIS(func)"()";                                  \
-}
-#endif /* !CH_DBG_ENABLE_CHECKS */
-
-/*===========================================================================*/
-/* Assertions related macros.                                                */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLE_ASSERTS || defined(__DOXYGEN__)
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Condition assertion.
- * @details If the condition check fails then the kernel panics with the
- *          specified message and halts.
- * @note    The condition is tested only if the @p CH_DBG_ENABLE_ASSERTS switch
- *          is specified in @p chconf.h else the macro does nothing.
- * @note    The convention for the message is the following:<br>
- *          @<function_name@>(), #@<assert_number@>
- * @note    The remark string is not currently used except for putting a
- *          comment in the code about the assertion.
- *
- * @param[in] c         the condition to be verified to be true
- * @param[in] m         the text message
- * @param[in] r         a remark string
- *
- * @api
- */
-#if !defined(chDbgAssert)
-#define chDbgAssert(c, m, r) {                                              \
-  if (!(c))                                                                 \
-    chDbgPanic(m);                                                          \
-}
-#endif /* !defined(chDbgAssert) */
-/** @} */
-#else /* !CH_DBG_ENABLE_ASSERTS */
-#define chDbgAssert(c, m, r) {(void)(c);}
-#endif /* !CH_DBG_ENABLE_ASSERTS */
-
-/*===========================================================================*/
-/* Panic related macros.                                                     */
-/*===========================================================================*/
-
-#if !CH_DBG_ENABLED
-/* When the debug features are disabled this function is replaced by an empty
-   macro.*/
-#define chDbgPanic(msg) {}
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#if CH_DBG_SYSTEM_STATE_CHECK
-  extern cnt_t dbg_isr_cnt;
-  extern cnt_t dbg_lock_cnt;
-  void dbg_check_disable(void);
-  void dbg_check_suspend(void);
-  void dbg_check_enable(void);
-  void dbg_check_lock(void);
-  void dbg_check_unlock(void);
-  void dbg_check_lock_from_isr(void);
-  void dbg_check_unlock_from_isr(void);
-  void dbg_check_enter_isr(void);
-  void dbg_check_leave_isr(void);
-  void chDbgCheckClassI(void);
-  void chDbgCheckClassS(void);
-#endif
-#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
-  void _trace_init(void);
-  void dbg_trace(Thread *otp);
-#endif
-#if CH_DBG_ENABLED
-  extern const char *dbg_panic_msg;
-  void chDbgPanic(const char *msg);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHDEBUG_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chdynamic.h b/os/kernel/include/chdynamic.h
deleted file mode 100644
index 3ac79a5f4..000000000
--- a/os/kernel/include/chdynamic.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chdynamic.h
- * @brief   Dynamic threads macros and structures.
- *
- * @addtogroup dynamic_threads
- * @{
- */
-
-#ifndef _CHDYNAMIC_H_
-#define _CHDYNAMIC_H_
-
-#if CH_USE_DYNAMIC || defined(__DOXYGEN__)
-
-/*
- * Module dependencies check.
- */
-#if CH_USE_DYNAMIC && !CH_USE_WAITEXIT
-#error "CH_USE_DYNAMIC requires CH_USE_WAITEXIT"
-#endif
-#if CH_USE_DYNAMIC && !CH_USE_HEAP && !CH_USE_MEMPOOLS
-#error "CH_USE_DYNAMIC requires CH_USE_HEAP and/or CH_USE_MEMPOOLS"
-#endif
-
-/*
- * Dynamic threads APIs.
- */
-#ifdef __cplusplus
-extern "C" {
-#endif
-  Thread *chThdAddRef(Thread *tp);
-  void chThdRelease(Thread *tp);
-#if CH_USE_HEAP
-  Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size,
-                              tprio_t prio, tfunc_t pf, void *arg);
-#endif
-#if CH_USE_MEMPOOLS
-  Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio,
-                                    tfunc_t pf, void *arg);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_DYNAMIC */
-
-#endif /* _CHDYNAMIC_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chevents.h b/os/kernel/include/chevents.h
deleted file mode 100644
index d8bd269ea..000000000
--- a/os/kernel/include/chevents.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-/*
-   Concepts and parts of this file have been contributed by Scott (skute).
- */
-
-/**
- * @file    chevents.h
- * @brief   Events macros and structures.
- *
- * @addtogroup events
- * @{
- */
-
-#ifndef _CHEVENTS_H_
-#define _CHEVENTS_H_
-
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
-
-typedef struct EventListener EventListener;
-
-/**
- * @brief   Event Listener structure.
- */
-struct EventListener {
-  EventListener         *el_next;       /**< @brief Next Event Listener
-                                                    registered on the Event
-                                                    Source.                 */
-  Thread                *el_listener;   /**< @brief Thread interested in the
-                                                    Event Source.           */
-  eventmask_t           el_mask;        /**< @brief Event flags mask associated
-                                                    by the thread to the Event
-                                                    Source.                 */
-  flagsmask_t           el_flags;       /**< @brief Flags added to the listener
-                                                    by the event source.*/
-};
-
-/**
- * @brief   Event Source structure.
- */
-typedef struct EventSource {
-  EventListener         *es_next;       /**< @brief First Event Listener
-                                                    registered on the Event
-                                                    Source.                 */
-} EventSource;
-
-/**
- * @brief   Event Handler callback function.
- */
-typedef void (*evhandler_t)(eventid_t);
-
-/**
- * @brief   Data part of a static event source initializer.
- * @details This macro should be used when statically initializing an event
- *          source that is part of a bigger structure.
- * @param name the name of the event source variable
- */
-#define _EVENTSOURCE_DATA(name) {(void *)(&name)}
-
-/**
- * @brief   Static event source initializer.
- * @details Statically initialized event sources require no explicit
- *          initialization using @p chEvtInit().
- *
- * @param name          the name of the event source variable
- */
-#define EVENTSOURCE_DECL(name) EventSource name = _EVENTSOURCE_DATA(name)
-
-/**
- * @brief   All events allowed mask.
- */
-#define ALL_EVENTS      ((eventmask_t)-1)
-
-/**
- * @brief   Returns an event mask from an event identifier.
- */
-#define EVENT_MASK(eid) ((eventmask_t)(1 << (eid)))
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Registers an Event Listener on an Event Source.
- * @note    Multiple Event Listeners can use the same event identifier, the
- *          listener will share the callback function.
- *
- * @param[in] esp       pointer to the  @p EventSource structure
- * @param[out] elp      pointer to the @p EventListener structure
- * @param[in] eid       numeric identifier assigned to the Event Listener. The
- *                      identifier is used as index for the event callback
- *                      function.
- *                      The value must range between zero and the size, in bit,
- *                      of the @p eventid_t type minus one.
- *
- * @api
- */
-#define chEvtRegister(esp, elp, eid) \
-  chEvtRegisterMask(esp, elp, EVENT_MASK(eid))
-
-/**
- * @brief   Initializes an Event Source.
- * @note    This function can be invoked before the kernel is initialized
- *          because it just prepares a @p EventSource structure.
- *
- * @param[out] esp      pointer to the @p EventSource structure
- *
- * @init
- */
-#define chEvtInit(esp) \
-  ((esp)->es_next = (EventListener *)(void *)(esp))
-
-/**
- * @brief   Verifies if there is at least one @p EventListener registered.
- *
- * @param[in] esp       pointer to the @p EventSource structure
- *
- * @iclass
- */
-#define chEvtIsListeningI(esp) \
-  ((void *)(esp) != (void *)(esp)->es_next)
-
-/**
- * @brief   Signals all the Event Listeners registered on the specified Event
- *          Source.
- *
- * @param[in] esp       pointer to the @p EventSource structure
- *
- * @api
- */
-#define chEvtBroadcast(esp) chEvtBroadcastFlags(esp, 0)
-
-/**
- * @brief   Signals all the Event Listeners registered on the specified Event
- *          Source.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel. Note that
- *          interrupt handlers always reschedule on exit so an explicit
- *          reschedule must not be performed in ISRs.
- *
- * @param[in] esp       pointer to the @p EventSource structure
- *
- * @iclass
- */
-#define chEvtBroadcastI(esp) chEvtBroadcastFlagsI(esp, 0)
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void chEvtRegisterMask(EventSource *esp,
-                         EventListener *elp,
-                         eventmask_t mask);
-  void chEvtUnregister(EventSource *esp, EventListener *elp);
-  eventmask_t chEvtGetAndClearEvents(eventmask_t mask);
-  eventmask_t chEvtAddEvents(eventmask_t mask);
-  flagsmask_t chEvtGetAndClearFlags(EventListener *elp);
-  flagsmask_t chEvtGetAndClearFlagsI(EventListener *elp);
-  void chEvtSignal(Thread *tp, eventmask_t mask);
-  void chEvtSignalI(Thread *tp, eventmask_t mask);
-  void chEvtBroadcastFlags(EventSource *esp, flagsmask_t flags);
-  void chEvtBroadcastFlagsI(EventSource *esp, flagsmask_t flags);
-  void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask);
-#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT
-  eventmask_t chEvtWaitOne(eventmask_t mask);
-  eventmask_t chEvtWaitAny(eventmask_t mask);
-  eventmask_t chEvtWaitAll(eventmask_t mask);
-#endif
-#if CH_USE_EVENTS_TIMEOUT
-  eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time);
-  eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time);
-  eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#if !CH_OPTIMIZE_SPEED && CH_USE_EVENTS_TIMEOUT
-#define chEvtWaitOne(mask) chEvtWaitOneTimeout(mask, TIME_INFINITE)
-#define chEvtWaitAny(mask) chEvtWaitAnyTimeout(mask, TIME_INFINITE)
-#define chEvtWaitAll(mask) chEvtWaitAllTimeout(mask, TIME_INFINITE)
-#endif
-
-#endif /* CH_USE_EVENTS */
-
-#endif /* _CHEVENTS_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chfiles.h b/os/kernel/include/chfiles.h
deleted file mode 100644
index ad2974ad8..000000000
--- a/os/kernel/include/chfiles.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chfiles.h
- * @brief   Data files.
- * @details This header defines abstract interfaces useful to access generic
- *          data files in a standardized way.
- *
- * @addtogroup data_files
- * @details This module define an abstract interface for generic data files by
- *          extending the @p BaseSequentialStream interface. Note that no code
- *          is present, data files are just abstract interface-like structures,
- *          you should look at the systems as to a set of abstract C++ classes
- *          (even if written in C). This system has the advantage to make the
- *          access to streams independent from the implementation logic.<br>
- *          The data files interface can be used as base class for high level
- *          object types such as an API for a File System implementation.
- * @{
- */
-
-#ifndef _CHFILES_H_
-#define _CHFILES_H_
-
-/**
- * @brief   No error return code.
- */
-#define FILE_OK         0
-
-/**
- * @brief   Error code from the file stream methods.
- */
-#define FILE_ERROR      0xFFFFFFFFUL
-
-/**
- * @brief   File offset type.
- */
-typedef uint32_t fileoffset_t;
-
-/**
- * @brief   BaseFileStream specific methods.
- */
-#define _base_file_stream_methods                                           \
-  _base_sequential_stream_methods                                           \
-  /* File close method.*/                                                   \
-  uint32_t (*close)(void *instance);                                        \
-  /* Get last error code method.*/                                          \
-  int (*geterror)(void *instance);                                          \
-  /* File get size method.*/                                                \
-  fileoffset_t (*getsize)(void *instance);                                  \
-  /* File get current position method.*/                                    \
-  fileoffset_t (*getposition)(void *instance);                              \
-  /* File seek method.*/                                                    \
-  uint32_t (*lseek)(void *instance, fileoffset_t offset);
-
-/**
- * @brief   @p BaseFileStream specific data.
- * @note    It is empty because @p BaseFileStream is only an interface
- *          without implementation.
- */
-#define _base_file_stream_data                                              \
-  _base_sequential_stream_data
-
-/**
- * @extends BaseSequentialStreamVMT
- *
- * @brief   @p BaseFileStream virtual methods table.
- */
-struct BaseFileStreamVMT {
-  _base_file_stream_methods
-};
-
-/**
- * @extends BaseSequentialStream
- *
- * @brief   Base file stream class.
- * @details This class represents a generic file data stream.
- */
-typedef struct {
-  /** @brief Virtual Methods Table.*/
-  const struct BaseFileStreamVMT *vmt;
-  _base_file_stream_data
-} BaseFileStream;
-
-/**
- * @name    Macro Functions (BaseFileStream)
- * @{
- */
-/**
- * @brief   Base file Stream close.
- * @details The function closes a file stream.
- *
- * @param[in] ip        pointer to a @p BaseFileStream or derived class
- * @return              The operation status.
- * @retval FILE_OK      no error.
- * @retval FILE_ERROR   operation failed.
- *
- * @api
- */
-#define chFileStreamClose(ip) ((ip)->vmt->close(ip))
-
-/**
- * @brief   Returns an implementation dependent error code.
- *
- * @param[in] ip        pointer to a @p BaseFileStream or derived class
- * @return              Implementation dependent error code.
- *
- * @api
- */
-#define chFileStreamGetError(ip) ((ip)->vmt->geterror(ip))
-
-/**
- * @brief   Returns the current file size.
- *
- * @param[in] ip        pointer to a @p BaseFileStream or derived class
- * @return              The file size.
- *
- * @api
- */
-#define chFileStreamGetSize(ip) ((ip)->vmt->getsize(ip))
-
-/**
- * @brief   Returns the current file pointer position.
- *
- * @param[in] ip        pointer to a @p BaseFileStream or derived class
- * @return              The current position inside the file.
- *
- * @api
- */
-#define chFileStreamGetPosition(ip) ((ip)->vmt->getposition(ip))
-
-/**
- * @brief   Moves the file current pointer to an absolute position.
- *
- * @param[in] ip        pointer to a @p BaseFileStream or derived class
- * @param[in] offset    new absolute position
- * @return              The operation status.
- * @retval FILE_OK      no error.
- * @retval FILE_ERROR   operation failed.
- *
- * @api
- */
-#define chFileStreamSeek(ip, offset) ((ip)->vmt->lseek(ip, offset))
-/** @} */
-
-#endif /* _CHFILES_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chheap.h b/os/kernel/include/chheap.h
deleted file mode 100644
index 8a54d7290..000000000
--- a/os/kernel/include/chheap.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chheap.h
- * @brief   Heaps macros and structures.
- *
- * @addtogroup heaps
- * @{
- */
-
-#ifndef _CHHEAP_H_
-#define _CHHEAP_H_
-
-#if CH_USE_HEAP || defined(__DOXYGEN__)
-
-/*
- * Module dependencies check.
- */
-#if !CH_USE_MEMCORE && !CH_USE_MALLOC_HEAP
-#error "CH_USE_HEAP requires CH_USE_MEMCORE or CH_USE_MALLOC_HEAP"
-#endif
-
-#if !CH_USE_MUTEXES && !CH_USE_SEMAPHORES
-#error "CH_USE_HEAP requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES"
-#endif
-
-typedef struct memory_heap MemoryHeap;
-
-/**
- * @brief   Memory heap block header.
- */
-union heap_header {
-  stkalign_t align;
-  struct {
-    union {
-      union heap_header *next;      /**< @brief Next block in free list.    */
-      MemoryHeap        *heap;      /**< @brief Block owner heap.           */
-    } u;                            /**< @brief Overlapped fields.          */
-    size_t              size;       /**< @brief Size of the memory block.   */
-  } h;
-};
-
-/**
- * @brief   Structure describing a memory heap.
- */
-struct memory_heap {
-  memgetfunc_t          h_provider; /**< @brief Memory blocks provider for
-                                                this heap.                  */
-  union heap_header     h_free;     /**< @brief Free blocks list header.    */
-#if CH_USE_MUTEXES
-  Mutex                 h_mtx;      /**< @brief Heap access mutex.          */
-#else
-  Semaphore             h_sem;      /**< @brief Heap access semaphore.      */
-#endif
-};
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _heap_init(void);
-#if !CH_USE_MALLOC_HEAP
-  void chHeapInit(MemoryHeap *heapp, void *buf, size_t size);
-#endif
-  void *chHeapAlloc(MemoryHeap *heapp, size_t size);
-  void chHeapFree(void *p);
-  size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_HEAP */
-
-#endif /* _CHHEAP_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chinline.h b/os/kernel/include/chinline.h
deleted file mode 100644
index 46ac45a84..000000000
--- a/os/kernel/include/chinline.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chinline.h
- * @brief   Kernel inlined functions.
- * @details In this file there are a set of inlined functions if the
- *          @p CH_OPTIMIZE_SPEED is enabled.
- */
-
-#ifndef _CHINLINE_H_
-#define _CHINLINE_H_
-
-/* If the performance code path has been chosen then all the following
-   functions are inlined into the various kernel modules.*/
-#if CH_OPTIMIZE_SPEED
-static INLINE void prio_insert(Thread *tp, ThreadsQueue *tqp) {
-
-  Thread *cp = (Thread *)tqp;
-  do {
-    cp = cp->p_next;
-  } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio));
-  tp->p_next = cp;
-  tp->p_prev = cp->p_prev;
-  tp->p_prev->p_next = cp->p_prev = tp;
-}
-
-static INLINE void queue_insert(Thread *tp, ThreadsQueue *tqp) {
-
-  tp->p_next = (Thread *)tqp;
-  tp->p_prev = tqp->p_prev;
-  tp->p_prev->p_next = tqp->p_prev = tp;
-}
-
-static INLINE Thread *fifo_remove(ThreadsQueue *tqp) {
-  Thread *tp = tqp->p_next;
-
-  (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp;
-  return tp;
-}
-
-static INLINE Thread *lifo_remove(ThreadsQueue *tqp) {
-  Thread *tp = tqp->p_prev;
-
-  (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp;
-  return tp;
-}
-
-static INLINE Thread *dequeue(Thread *tp) {
-
-  tp->p_prev->p_next = tp->p_next;
-  tp->p_next->p_prev = tp->p_prev;
-  return tp;
-}
-
-static INLINE void list_insert(Thread *tp, ThreadsList *tlp) {
-
-  tp->p_next = tlp->p_next;
-  tlp->p_next = tp;
-}
-
-static INLINE Thread *list_remove(ThreadsList *tlp) {
-
-  Thread *tp = tlp->p_next;
-  tlp->p_next = tp->p_next;
-  return tp;
-}
-#endif /* CH_OPTIMIZE_SPEED */
-
-#endif /* _CHINLINE_H_ */
diff --git a/os/kernel/include/chlists.h b/os/kernel/include/chlists.h
deleted file mode 100644
index caf2560b4..000000000
--- a/os/kernel/include/chlists.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chlists.h
- * @brief   Thread queues/lists macros and structures.
- * @note    All the macros present in this module, while public, are not
- *          an OS API and should not be directly used in the user applications
- *          code.
- *
- * @addtogroup internals
- * @{
- */
-
-#ifndef _CHLISTS_H_
-#define _CHLISTS_H_
-
-typedef struct Thread Thread;
-
-/**
- * @brief   Threads queue initialization.
- *
- * @notapi
- */
-#define queue_init(tqp) ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp));
-
-/**
- * @brief   Threads list initialization.
- *
- * @notapi
- */
-#define list_init(tlp) ((tlp)->p_next = (Thread *)(tlp))
-
-/**
- * @brief   Evaluates to @p TRUE if the specified threads queue or list is
- * empty.
- *
- * @notapi
- */
-#define isempty(p)      ((p)->p_next == (Thread *)(p))
-
-/**
- * @brief   Evaluates to @p TRUE if the specified threads queue or list is
- *          not empty.
- *
- * @notapi
- */
-#define notempty(p)     ((p)->p_next != (Thread *)(p))
-
-/**
- * @brief   Data part of a static threads queue initializer.
- * @details This macro should be used when statically initializing a threads
- *          queue that is part of a bigger structure.
- *
- * @param[in] name      the name of the threads queue variable
- */
-#define _THREADSQUEUE_DATA(name) {(Thread *)&name, (Thread *)&name}
-
-/**
- * @brief   Static threads queue initializer.
- * @details Statically initialized threads queues require no explicit
- *          initialization using @p queue_init().
- *
- * @param[in] name      the name of the threads queue variable
- */
-#define THREADSQUEUE_DECL(name) ThreadsQueue name = _THREADSQUEUE_DATA(name)
-
-/**
- * @extends ThreadsList
- *
- * @brief   Generic threads bidirectional linked list header and element.
- */
-typedef struct {
-  Thread                *p_next;        /**< First @p Thread in the queue, or
-                                             @p ThreadQueue when empty.     */
-  Thread                *p_prev;        /**< Last @p Thread in the queue, or
-                                             @p ThreadQueue when empty.     */
-} ThreadsQueue;
-
-/**
- * @brief   Generic threads single link list, it works like a stack.
- */
-typedef struct {
-
-  Thread            *p_next;            /**< Last pushed @p Thread on the stack
-                                             list, or pointer to itself if
-                                             empty.                         */
-} ThreadsList;
-
-#if !CH_OPTIMIZE_SPEED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void prio_insert(Thread *tp, ThreadsQueue *tqp);
-  void queue_insert(Thread *tp, ThreadsQueue *tqp);
-  Thread *fifo_remove(ThreadsQueue *tqp);
-  Thread *lifo_remove(ThreadsQueue *tqp);
-  Thread *dequeue(Thread *tp);
-  void list_insert(Thread *tp, ThreadsList *tlp);
-  Thread *list_remove(ThreadsList *tlp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !CH_OPTIMIZE_SPEED */
-
-#endif /* _CHLISTS_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chmboxes.h b/os/kernel/include/chmboxes.h
deleted file mode 100644
index 85192e804..000000000
--- a/os/kernel/include/chmboxes.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmboxes.h
- * @brief   Mailboxes macros and structures.
- *
- * @addtogroup mailboxes
- * @{
- */
-
-#ifndef _CHMBOXES_H_
-#define _CHMBOXES_H_
-
-#if CH_USE_MAILBOXES || defined(__DOXYGEN__)
-
-/*
- * Module dependencies check.
- */
-#if !CH_USE_SEMAPHORES
-#error "CH_USE_MAILBOXES requires CH_USE_SEMAPHORES"
-#endif
-
-/**
- * @brief   Structure representing a mailbox object.
- */
-typedef struct {
-  msg_t                 *mb_buffer;     /**< @brief Pointer to the mailbox
-                                                    buffer.                 */
-  msg_t                 *mb_top;        /**< @brief Pointer to the location
-                                                    after the buffer.       */
-  msg_t                 *mb_wrptr;      /**< @brief Write pointer.          */
-  msg_t                 *mb_rdptr;      /**< @brief Read pointer.           */
-  Semaphore             mb_fullsem;     /**< @brief Full counter
-                                                    @p Semaphore.           */
-  Semaphore             mb_emptysem;    /**< @brief Empty counter
-                                                    @p Semaphore.           */
-} Mailbox;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n);
-  void chMBReset(Mailbox *mbp);
-  msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t timeout);
-  msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t timeout);
-  msg_t chMBPostI(Mailbox *mbp, msg_t msg);
-  msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t timeout);
-  msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t timeout);
-  msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg);
-  msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t timeout);
-  msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t timeout);
-  msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp);
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Returns the mailbox buffer size.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- *
- * @iclass
- */
-#define chMBSizeI(mbp)                                                      \
-        ((mbp)->mb_top - (mbp)->mb_buffer)
-
-/**
- * @brief   Returns the number of free message slots into a mailbox.
- * @note    Can be invoked in any system state but if invoked out of a locked
- *          state then the returned value may change after reading.
- * @note    The returned value can be less than zero when there are waiting
- *          threads on the internal semaphore.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @return              The number of empty message slots.
- *
- * @iclass
- */
-#define chMBGetFreeCountI(mbp) chSemGetCounterI(&(mbp)->mb_emptysem)
-
-/**
- * @brief   Returns the number of used message slots into a mailbox.
- * @note    Can be invoked in any system state but if invoked out of a locked
- *          state then the returned value may change after reading.
- * @note    The returned value can be less than zero when there are waiting
- *          threads on the internal semaphore.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @return              The number of queued messages.
- *
- * @iclass
- */
-#define chMBGetUsedCountI(mbp) chSemGetCounterI(&(mbp)->mb_fullsem)
-
-/**
- * @brief   Returns the next message in the queue without removing it.
- * @pre     A message must be waiting in the queue for this function to work
- *          or it would return garbage. The correct way to use this macro is
- *          to use @p chMBGetFullCountI() and then use this macro, all within
- *          a lock state.
- *
- * @iclass
- */
-#define chMBPeekI(mbp) (*(mbp)->mb_rdptr)
-/** @} */
-
-/**
- * @brief   Data part of a static mailbox initializer.
- * @details This macro should be used when statically initializing a
- *          mailbox that is part of a bigger structure.
- *
- * @param[in] name      the name of the mailbox variable
- * @param[in] buffer    pointer to the mailbox buffer area
- * @param[in] size      size of the mailbox buffer area
- */
-#define _MAILBOX_DATA(name, buffer, size) {                             \
-  (msg_t *)(buffer),                                                    \
-  (msg_t *)(buffer) + size,                                             \
-  (msg_t *)(buffer),                                                    \
-  (msg_t *)(buffer),                                                    \
-  _SEMAPHORE_DATA(name.mb_fullsem, 0),                                  \
-  _SEMAPHORE_DATA(name.mb_emptysem, size),                              \
-}
-
-/**
- * @brief   Static mailbox initializer.
- * @details Statically initialized mailboxes require no explicit
- *          initialization using @p chMBInit().
- *
- * @param[in] name      the name of the mailbox variable
- * @param[in] buffer    pointer to the mailbox buffer area
- * @param[in] size      size of the mailbox buffer area
- */
-#define MAILBOX_DECL(name, buffer, size)                                \
-  Mailbox name = _MAILBOX_DATA(name, buffer, size)
-
-#endif /* CH_USE_MAILBOXES */
-
-#endif /* _CHMBOXES_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chmemcore.h b/os/kernel/include/chmemcore.h
deleted file mode 100644
index 4f75bd043..000000000
--- a/os/kernel/include/chmemcore.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmemcore.h
- * @brief   Core memory manager macros and structures.
- *
- * @addtogroup memcore
- * @{
- */
-
-#ifndef _CHMEMCORE_H_
-#define _CHMEMCORE_H_
-
-/**
- * @brief   Memory get function.
- * @note    This type must be assignment compatible with the @p chMemAlloc()
- *          function.
- */
-typedef void *(*memgetfunc_t)(size_t size);
-
-/**
- * @name    Alignment support macros
- */
-/**
- * @brief   Alignment size constant.
- */
-#define MEM_ALIGN_SIZE      sizeof(stkalign_t)
-
-/**
- * @brief   Alignment mask constant.
- */
-#define MEM_ALIGN_MASK      (MEM_ALIGN_SIZE - 1)
-
-/**
- * @brief   Alignment helper macro.
- */
-#define MEM_ALIGN_PREV(p)   ((size_t)(p) & ~MEM_ALIGN_MASK)
-
-/**
- * @brief   Alignment helper macro.
- */
-#define MEM_ALIGN_NEXT(p)   MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK)
-
-/**
- * @brief   Returns whatever a pointer or memory size is aligned to
- *          the type @p align_t.
- */
-#define MEM_IS_ALIGNED(p)   (((size_t)(p) & MEM_ALIGN_MASK) == 0)
-/** @} */
-
-#if CH_USE_MEMCORE || defined(__DOXYGEN__)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _core_init(void);
-  void *chCoreAlloc(size_t size);
-  void *chCoreAllocI(size_t size);
-  size_t chCoreStatus(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_MEMCORE */
-
-#endif /* _CHMEMCORE_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chmempools.h b/os/kernel/include/chmempools.h
deleted file mode 100644
index 80d6eeaf2..000000000
--- a/os/kernel/include/chmempools.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmempools.h
- * @brief   Memory Pools macros and structures.
- *
- * @addtogroup pools
- * @{
- */
-
-#ifndef _CHMEMPOOLS_H_
-#define _CHMEMPOOLS_H_
-
-#if CH_USE_MEMPOOLS || defined(__DOXYGEN__)
-
-/**
- * @brief   Memory pool free object header.
- */
-struct pool_header {
-  struct pool_header    *ph_next;       /**< @brief Pointer to the next pool
-                                                    header in the list.     */
-};
-
-/**
- * @brief   Memory pool descriptor.
- */
-typedef struct {
-  struct pool_header    *mp_next;       /**< @brief Pointer to the header.  */
-  size_t                mp_object_size; /**< @brief Memory pool objects
-                                                    size.                   */
-  memgetfunc_t          mp_provider;    /**< @brief Memory blocks provider for
-                                                    this pool.              */
-} MemoryPool;
-
-/**
- * @brief   Data part of a static memory pool initializer.
- * @details This macro should be used when statically initializing a
- *          memory pool that is part of a bigger structure.
- *
- * @param[in] name      the name of the memory pool variable
- * @param[in] size      size of the memory pool contained objects
- * @param[in] provider  memory provider function for the memory pool
- */
-#define _MEMORYPOOL_DATA(name, size, provider)                              \
-  {NULL, size, provider}
-
-/**
- * @brief Static memory pool initializer in hungry mode.
- * @details Statically initialized memory pools require no explicit
- *          initialization using @p chPoolInit().
- *
- * @param[in] name the name of the memory pool variable
- * @param[in] size size of the memory pool contained objects
- * @param[in] provider memory provider function for the memory pool or @p NULL
- *                     if the pool is not allowed to grow automatically
- */
-#define MEMORYPOOL_DECL(name, size, provider)                               \
-  MemoryPool name = _MEMORYPOOL_DATA(name, size, provider)
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Adds an object to a memory pool.
- * @pre     The memory pool must be already been initialized.
- * @pre     The added object must be of the right size for the specified
- *          memory pool.
- * @pre     The added object must be memory aligned to the size of
- *          @p stkalign_t type.
- * @note    This function is just an alias for @p chPoolFree() and has been
- *          added for clarity.
- *
- * @param[in] mp        pointer to a @p MemoryPool structure
- * @param[in] objp      the pointer to the object to be added
- *
- * @api
- */
-#define chPoolAdd(mp, objp) chPoolFree(mp, objp)
-
-/**
- * @brief   Adds an object to a memory pool.
- * @pre     The memory pool must be already been initialized.
- * @pre     The added object must be of the right size for the specified
- *          memory pool.
- * @pre     The added object must be memory aligned to the size of
- *          @p stkalign_t type.
- * @note    This function is just an alias for @p chPoolFree() and has been
- *          added for clarity.
- *
- * @param[in] mp        pointer to a @p MemoryPool structure
- * @param[in] objp      the pointer to the object to be added
- *
- * @iclass
- */
-#define chPoolAddI(mp, objp) chPoolFreeI(mp, objp)
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider);
-  void chPoolLoadArray(MemoryPool *mp, void *p, size_t n);
-  void *chPoolAllocI(MemoryPool *mp);
-  void *chPoolAlloc(MemoryPool *mp);
-  void chPoolFreeI(MemoryPool *mp, void *objp);
-  void chPoolFree(MemoryPool *mp, void *objp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_MEMPOOLS */
-
-#endif /* _CHMEMPOOLS_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chmsg.h b/os/kernel/include/chmsg.h
deleted file mode 100644
index e613a6aad..000000000
--- a/os/kernel/include/chmsg.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmsg.h
- * @brief   Messages macros and structures.
- *
- * @addtogroup messages
- * @{
- */
-
-#ifndef _CHMSG_H_
-#define _CHMSG_H_
-
-#if CH_USE_MESSAGES || defined(__DOXYGEN__)
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Evaluates to TRUE if the thread has pending messages.
- *
- * @iclass
- */
-#define chMsgIsPendingI(tp) \
-        ((tp)->p_msgqueue.p_next != (Thread *)&(tp)->p_msgqueue)
-
-/**
- * @brief   Returns the message carried by the specified thread.
- * @pre     This function must be invoked immediately after exiting a call
- *          to @p chMsgWait().
- *
- * @param[in] tp        pointer to the thread
- * @return              The message carried by the sender.
- *
- * @api
- */
-#define chMsgGet(tp) ((tp)->p_msg)
-
-/**
- * @brief   Releases the thread waiting on top of the messages queue.
- * @pre     Invoke this function only after a message has been received
- *          using @p chMsgWait().
- *
- * @param[in] tp        pointer to the thread
- * @param[in] msg       message to be returned to the sender
- *
- * @sclass
- */
-#define chMsgReleaseS(tp, msg) chSchWakeupS(tp, msg)
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  msg_t chMsgSend(Thread *tp, msg_t msg);
-  Thread * chMsgWait(void);
-  void chMsgRelease(Thread *tp, msg_t msg);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_MESSAGES */
-
-#endif /* _CHMSG_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chmtx.h b/os/kernel/include/chmtx.h
deleted file mode 100644
index 124127a88..000000000
--- a/os/kernel/include/chmtx.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmtx.h
- * @brief   Mutexes macros and structures.
- *
- * @addtogroup mutexes
- * @{
- */
-
-#ifndef _CHMTX_H_
-#define _CHMTX_H_
-
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-
-/**
- * @brief   Mutex structure.
- */
-typedef struct Mutex {
-  ThreadsQueue          m_queue;    /**< @brief Queue of the threads sleeping
-                                                on this Mutex.              */
-  Thread                *m_owner;   /**< @brief Owner @p Thread pointer or
-                                                @p NULL.                    */
-  struct Mutex          *m_next;    /**< @brief Next @p Mutex into an
-                                                owner-list or @p NULL.      */
-} Mutex;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void chMtxInit(Mutex *mp);
-  void chMtxLock(Mutex *mp);
-  void chMtxLockS(Mutex *mp);
-  bool_t chMtxTryLock(Mutex *mp);
-  bool_t chMtxTryLockS(Mutex *mp);
-  Mutex *chMtxUnlock(void);
-  Mutex *chMtxUnlockS(void);
-  void chMtxUnlockAll(void);
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @brief   Data part of a static mutex initializer.
- * @details This macro should be used when statically initializing a mutex
- *          that is part of a bigger structure.
- *
- * @param[in] name      the name of the mutex variable
- */
-#define _MUTEX_DATA(name) {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL}
-
-/**
- * @brief   Static mutex initializer.
- * @details Statically initialized mutexes require no explicit initialization
- *          using @p chMtxInit().
- *
- * @param[in] name      the name of the mutex variable
- */
-#define MUTEX_DECL(name) Mutex name = _MUTEX_DATA(name)
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Returns @p TRUE if the mutex queue contains at least a waiting
- *          thread.
- *
- * @sclass
- */
-#define chMtxQueueNotEmptyS(mp) notempty(&(mp)->m_queue)
-/** @} */
-
-#endif /* CH_USE_MUTEXES */
-
-#endif /* _CHMTX_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chqueues.h b/os/kernel/include/chqueues.h
deleted file mode 100644
index 507f020d1..000000000
--- a/os/kernel/include/chqueues.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chqueues.h
- * @brief   I/O Queues macros and structures.
- *
- * @addtogroup io_queues
- * @{
- */
-
-#ifndef _CHQUEUES_H_
-#define _CHQUEUES_H_
-
-#if CH_USE_QUEUES || defined(__DOXYGEN__)
-
-/**
- * @name    Queue functions returned status value
- * @{
- */
-#define Q_OK            RDY_OK      /**< @brief Operation successful.       */
-#define Q_TIMEOUT       RDY_TIMEOUT /**< @brief Timeout condition.          */
-#define Q_RESET         RDY_RESET   /**< @brief Queue has been reset.       */
-#define Q_EMPTY         -3          /**< @brief Queue empty.                */
-#define Q_FULL          -4          /**< @brief Queue full,                 */
-/** @} */
-
-/**
- * @brief   Type of a generic I/O queue structure.
- */
-typedef struct GenericQueue GenericQueue;
-
-/** @brief Queue notification callback type.*/
-typedef void (*qnotify_t)(GenericQueue *qp);
-
-/**
- * @brief   Generic I/O queue structure.
- * @details This structure represents a generic Input or Output asymmetrical
- *          queue. The queue is asymmetrical because one end is meant to be
- *          accessed from a thread context, and thus can be blocking, the other
- *          end is accessible from interrupt handlers or from within a kernel
- *          lock zone (see <b>I-Locked</b> and <b>S-Locked</b> states in
- *          @ref system_states) and is non-blocking.
- */
-struct GenericQueue {
-  ThreadsQueue          q_waiting;  /**< @brief Queue of waiting threads.   */
-  size_t                q_counter;  /**< @brief Resources counter.          */
-  uint8_t               *q_buffer;  /**< @brief Pointer to the queue buffer.*/
-  uint8_t               *q_top;     /**< @brief Pointer to the first location
-                                                after the buffer.           */
-  uint8_t               *q_wrptr;   /**< @brief Write pointer.              */
-  uint8_t               *q_rdptr;   /**< @brief Read pointer.               */
-  qnotify_t             q_notify;   /**< @brief Data notification callback. */
-  void                  *q_link;    /**< @brief Application defined field.  */
-};
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Returns the queue's buffer size.
- *
- * @param[in] qp        pointer to a @p GenericQueue structure.
- * @return              The buffer size.
- *
- * @iclass
- */
-#define chQSizeI(qp) ((size_t)((qp)->q_top - (qp)->q_buffer))
-
-/**
- * @brief   Queue space.
- * @details Returns the used space if used on an input queue or the empty
- *          space if used on an output queue.
- *
- * @param[in] qp        pointer to a @p GenericQueue structure.
- * @return              The buffer space.
- *
- * @iclass
- */
-#define chQSpaceI(qp) ((qp)->q_counter)
-
-/**
- * @brief   Returns the queue application-defined link.
- * @note    This function can be called in any context.
- *
- * @param[in] qp        pointer to a @p GenericQueue structure.
- * @return              The application-defined link.
- *
- * @special
- */
-#define chQGetLink(qp) ((qp)->q_link)
-/** @} */
-
-/**
- * @extends GenericQueue
- *
- * @brief   Type of an input queue structure.
- * @details This structure represents a generic asymmetrical input queue.
- *          Writing to the queue is non-blocking and can be performed from
- *          interrupt handlers or from within a kernel lock zone (see
- *          <b>I-Locked</b> and <b>S-Locked</b> states in @ref system_states).
- *          Reading the queue can be a blocking operation and is supposed to
- *          be performed by a system thread.
- */
-typedef GenericQueue InputQueue;
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Returns the filled space into an input queue.
- *
- * @param[in] iqp       pointer to an @p InputQueue structure
- * @return              The number of full bytes in the queue.
- * @retval 0            if the queue is empty.
- *
- * @iclass
- */
-#define chIQGetFullI(iqp) chQSpaceI(iqp)
-
-/**
- * @brief   Returns the empty space into an input queue.
- *
- * @param[in] iqp       pointer to an @p InputQueue structure
- * @return              The number of empty bytes in the queue.
- * @retval 0            if the queue is full.
- *
- * @iclass
- */
-#define chIQGetEmptyI(iqp) (chQSizeI(iqp) - chQSpaceI(iqp))
-
-/**
- * @brief   Evaluates to @p TRUE if the specified input queue is empty.
- *
- * @param[in] iqp       pointer to an @p InputQueue structure.
- * @return              The queue status.
- * @retval FALSE        if the queue is not empty.
- * @retval TRUE         if the queue is empty.
- *
- * @iclass
- */
-#define chIQIsEmptyI(iqp) ((bool_t)(chQSpaceI(iqp) <= 0))
-
-/**
- * @brief   Evaluates to @p TRUE if the specified input queue is full.
- *
- * @param[in] iqp       pointer to an @p InputQueue structure.
- * @return              The queue status.
- * @retval FALSE        if the queue is not full.
- * @retval TRUE         if the queue is full.
- *
- * @iclass
- */
-#define chIQIsFullI(iqp) ((bool_t)(((iqp)->q_wrptr == (iqp)->q_rdptr) &&   \
-                                   ((iqp)->q_counter != 0)))
-
-/**
- * @brief   Input queue read.
- * @details This function reads a byte value from an input queue. If the queue
- *          is empty then the calling thread is suspended until a byte arrives
- *          in the queue.
- *
- * @param[in] iqp       pointer to an @p InputQueue structure
- * @return              A byte value from the queue.
- * @retval Q_RESET      if the queue has been reset.
- *
- * @api
- */
-#define chIQGet(iqp) chIQGetTimeout(iqp, TIME_INFINITE)
-/** @} */
-
-/**
- * @brief   Data part of a static input queue initializer.
- * @details This macro should be used when statically initializing an
- *          input queue that is part of a bigger structure.
- *
- * @param[in] name      the name of the input queue variable
- * @param[in] buffer    pointer to the queue buffer area
- * @param[in] size      size of the queue buffer area
- * @param[in] inotify   input notification callback pointer
- * @param[in] link      application defined pointer
- */
-#define _INPUTQUEUE_DATA(name, buffer, size, inotify, link) {               \
-  _THREADSQUEUE_DATA(name),                                                 \
-  0,                                                                        \
-  (uint8_t *)(buffer),                                                      \
-  (uint8_t *)(buffer) + (size),                                             \
-  (uint8_t *)(buffer),                                                      \
-  (uint8_t *)(buffer),                                                      \
-  (inotify),                                                                \
-  (link)                                                                    \
-}
-
-/**
- * @brief   Static input queue initializer.
- * @details Statically initialized input queues require no explicit
- *          initialization using @p chIQInit().
- *
- * @param[in] name      the name of the input queue variable
- * @param[in] buffer    pointer to the queue buffer area
- * @param[in] size      size of the queue buffer area
- * @param[in] inotify   input notification callback pointer
- * @param[in] link      application defined pointer
- */
-#define INPUTQUEUE_DECL(name, buffer, size, inotify, link)                  \
-  InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify, link)
-
-/**
- * @extends GenericQueue
- *
- * @brief   Type of an output queue structure.
- * @details This structure represents a generic asymmetrical output queue.
- *          Reading from the queue is non-blocking and can be performed from
- *          interrupt handlers or from within a kernel lock zone (see
- *          <b>I-Locked</b> and <b>S-Locked</b> states in @ref system_states).
- *          Writing the queue can be a blocking operation and is supposed to
- *          be performed by a system thread.
- */
-typedef GenericQueue OutputQueue;
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Returns the filled space into an output queue.
- *
- * @param[in] oqp       pointer to an @p OutputQueue structure
- * @return              The number of full bytes in the queue.
- * @retval 0            if the queue is empty.
- *
- * @iclass
- */
-#define chOQGetFullI(oqp) (chQSizeI(oqp) - chQSpaceI(oqp))
-
-/**
- * @brief   Returns the empty space into an output queue.
- *
- * @param[in] oqp       pointer to an @p OutputQueue structure
- * @return              The number of empty bytes in the queue.
- * @retval 0            if the queue is full.
- *
- * @iclass
- */
-#define chOQGetEmptyI(oqp) chQSpaceI(oqp)
-
-/**
- * @brief   Evaluates to @p TRUE if the specified output queue is empty.
- *
- * @param[in] oqp       pointer to an @p OutputQueue structure.
- * @return              The queue status.
- * @retval FALSE        if the queue is not empty.
- * @retval TRUE         if the queue is empty.
- *
- * @iclass
- */
-#define chOQIsEmptyI(oqp) ((bool_t)(((oqp)->q_wrptr == (oqp)->q_rdptr) &&   \
-                                    ((oqp)->q_counter != 0)))
-
-/**
- * @brief   Evaluates to @p TRUE if the specified output queue is full.
- *
- * @param[in] oqp       pointer to an @p OutputQueue structure.
- * @return              The queue status.
- * @retval FALSE        if the queue is not full.
- * @retval TRUE         if the queue is full.
- *
- * @iclass
- */
-#define chOQIsFullI(oqp) ((bool_t)(chQSpaceI(oqp) <= 0))
-
-/**
- * @brief   Output queue write.
- * @details This function writes a byte value to an output queue. If the queue
- *          is full then the calling thread is suspended until there is space
- *          in the queue.
- *
- * @param[in] oqp       pointer to an @p OutputQueue structure
- * @param[in] b         the byte value to be written in the queue
- * @return              The operation status.
- * @retval Q_OK         if the operation succeeded.
- * @retval Q_RESET      if the queue has been reset.
- *
- * @api
- */
-#define chOQPut(oqp, b) chOQPutTimeout(oqp, b, TIME_INFINITE)
- /** @} */
-
-/**
- * @brief   Data part of a static output queue initializer.
- * @details This macro should be used when statically initializing an
- *          output queue that is part of a bigger structure.
- *
- * @param[in] name      the name of the output queue variable
- * @param[in] buffer    pointer to the queue buffer area
- * @param[in] size      size of the queue buffer area
- * @param[in] onotify   output notification callback pointer
- * @param[in] link      application defined pointer
- */
-#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) {              \
-  _THREADSQUEUE_DATA(name),                                                 \
-  (size),                                                                   \
-  (uint8_t *)(buffer),                                                      \
-  (uint8_t *)(buffer) + (size),                                             \
-  (uint8_t *)(buffer),                                                      \
-  (uint8_t *)(buffer),                                                      \
-  (onotify),                                                                \
-  (link)                                                                    \
-}
-
-/**
- * @brief   Static output queue initializer.
- * @details Statically initialized output queues require no explicit
- *          initialization using @p chOQInit().
- *
- * @param[in] name      the name of the output queue variable
- * @param[in] buffer    pointer to the queue buffer area
- * @param[in] size      size of the queue buffer area
- * @param[in] onotify   output notification callback pointer
- * @param[in] link      application defined pointer
- */
-#define OUTPUTQUEUE_DECL(name, buffer, size, onotify, link)                 \
-  OutputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy,
-                void *link);
-  void chIQResetI(InputQueue *iqp);
-  msg_t chIQPutI(InputQueue *iqp, uint8_t b);
-  msg_t chIQGetTimeout(InputQueue *iqp, systime_t time);
-  size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp,
-                         size_t n, systime_t time);
-
-  void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy,
-                void *link);
-  void chOQResetI(OutputQueue *oqp);
-  msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time);
-  msg_t chOQGetI(OutputQueue *oqp);
-  size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp,
-                          size_t n, systime_t time);
-#ifdef __cplusplus
-}
-#endif
-#endif /* CH_USE_QUEUES */
-
-#endif /* _CHQUEUES_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chregistry.h b/os/kernel/include/chregistry.h
deleted file mode 100644
index 446de7aca..000000000
--- a/os/kernel/include/chregistry.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chregistry.h
- * @brief   Threads registry macros and structures.
- *
- * @addtogroup registry
- * @{
- */
-
-#ifndef _CHREGISTRY_H_
-#define _CHREGISTRY_H_
-
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
-
-/**
- * @brief   ChibiOS/RT memory signature record.
- */
-typedef struct {
-  char      ch_identifier[4];       /**< @brief Always set to "main".       */
-  uint8_t   ch_zero;                /**< @brief Must be zero.               */
-  uint8_t   ch_size;                /**< @brief Size of this structure.     */
-  uint16_t  ch_version;             /**< @brief Encoded ChibiOS/RT version. */
-  uint8_t   ch_ptrsize;             /**< @brief Size of a pointer.          */
-  uint8_t   ch_timesize;            /**< @brief Size of a @p systime_t.     */
-  uint8_t   ch_threadsize;          /**< @brief Size of a @p Thread struct. */
-  uint8_t   cf_off_prio;            /**< @brief Offset of @p p_prio field.  */
-  uint8_t   cf_off_ctx;             /**< @brief Offset of @p p_ctx field.   */
-  uint8_t   cf_off_newer;           /**< @brief Offset of @p p_newer field. */
-  uint8_t   cf_off_older;           /**< @brief Offset of @p p_older field. */
-  uint8_t   cf_off_name;            /**< @brief Offset of @p p_name field.  */
-  uint8_t   cf_off_stklimit;        /**< @brief Offset of @p p_stklimit
-                                                field.                      */
-  uint8_t   cf_off_state;           /**< @brief Offset of @p p_state field. */
-  uint8_t   cf_off_flags;           /**< @brief Offset of @p p_flags field. */
-  uint8_t   cf_off_refs;            /**< @brief Offset of @p p_refs field.  */
-  uint8_t   cf_off_preempt;         /**< @brief Offset of @p p_preempt
-                                                field.                      */
-  uint8_t   cf_off_time;            /**< @brief Offset of @p p_time field.  */
-} chdebug_t;
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Sets the current thread name.
- * @pre     This function only stores the pointer to the name if the option
- *          @p CH_USE_REGISTRY is enabled else no action is performed.
- *
- * @param[in] p         thread name as a zero terminated string
- *
- * @api
- */
-#define chRegSetThreadName(p) (currp->p_name = (p))
-
-/**
- * @brief   Returns the name of the specified thread.
- * @pre     This function only returns the pointer to the name if the option
- *          @p CH_USE_REGISTRY is enabled else @p NULL is returned.
- *
- * @param[in] tp        pointer to the thread
- *
- * @return              Thread name as a zero terminated string.
- * @retval NULL         if the thread name has not been set.
- */
-#define chRegGetThreadName(tp) ((tp)->p_name)
-/** @} */
-#else /* !CH_USE_REGISTRY */
-#define chRegSetThreadName(p)
-#define chRegGetThreadName(tp) NULL
-#endif /* !CH_USE_REGISTRY */
-
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
-/**
- * @brief   Removes a thread from the registry list.
- * @note    This macro is not meant for use in application code.
- *
- * @param[in] tp        thread to remove from the registry
- */
-#define REG_REMOVE(tp) {                                                    \
-  (tp)->p_older->p_newer = (tp)->p_newer;                                   \
-  (tp)->p_newer->p_older = (tp)->p_older;                                   \
-}
-
-/**
- * @brief   Adds a thread to the registry list.
- * @note    This macro is not meant for use in application code.
- *
- * @param[in] tp        thread to add to the registry
- */
-#define REG_INSERT(tp) {                                                    \
-  (tp)->p_newer = (Thread *)&rlist;                                         \
-  (tp)->p_older = rlist.r_older;                                            \
-  (tp)->p_older->p_newer = rlist.r_older = (tp);                            \
-}
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  extern ROMCONST chdebug_t ch_debug;
-  Thread *chRegFirstThread(void);
-  Thread *chRegNextThread(Thread *tp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CH_USE_REGISTRY */
-
-#endif /* _CHREGISTRY_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chschd.h b/os/kernel/include/chschd.h
deleted file mode 100644
index 37e457c31..000000000
--- a/os/kernel/include/chschd.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chschd.h
- * @brief   Scheduler macros and structures.
- *
- * @addtogroup scheduler
- * @{
- */
-
-#ifndef _CHSCHD_H_
-#define _CHSCHD_H_
-
-/**
- * @name    Wakeup status codes
- * @{
- */
-#define RDY_OK          0           /**< @brief Normal wakeup message.      */
-#define RDY_TIMEOUT     -1          /**< @brief Wakeup caused by a timeout
-                                         condition.                         */
-#define RDY_RESET       -2          /**< @brief Wakeup caused by a reset
-                                         condition.                         */
-/** @} */
-
-/**
- * @name    Priority constants
- * @{
- */
-#define NOPRIO          0           /**< @brief Ready list header priority. */
-#define IDLEPRIO        1           /**< @brief Idle thread priority.       */
-#define LOWPRIO         2           /**< @brief Lowest user priority.       */
-#define NORMALPRIO      64          /**< @brief Normal user priority.       */
-#define HIGHPRIO        127         /**< @brief Highest user priority.      */
-#define ABSPRIO         255         /**< @brief Greatest possible priority. */
-/** @} */
-
-/**
- * @name    Special time constants
- * @{
- */
-/**
- * @brief   Zero time specification for some functions with a timeout
- *          specification.
- * @note    Not all functions accept @p TIME_IMMEDIATE as timeout parameter,
- *          see the specific function documentation.
- */
-#define TIME_IMMEDIATE  ((systime_t)0)
-
-/**
- * @brief   Infinite time specification for all functions with a timeout
- *          specification.
- */
-#define TIME_INFINITE   ((systime_t)-1)
-/** @} */
-
-/**
- * @brief   Returns the priority of the first thread on the given ready list.
- *
- * @notapi
- */
-#define firstprio(rlp)  ((rlp)->p_next->p_prio)
-
-/**
- * @extends ThreadsQueue
- *
- * @brief   Ready list header.
- */
-#if !defined(PORT_OPTIMIZED_READYLIST_STRUCT) || defined(__DOXYGEN__)
-typedef struct {
-  ThreadsQueue          r_queue;    /**< @brief Threads queue.              */
-  tprio_t               r_prio;     /**< @brief This field must be
-                                                initialized to zero.        */
-  struct context        r_ctx;      /**< @brief Not used, present because
-                                                offsets.                    */
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
-  Thread                *r_newer;   /**< @brief Newer registry element.     */
-  Thread                *r_older;   /**< @brief Older registry element.     */
-#endif
-  /* End of the fields shared with the Thread structure.*/
-  Thread                *r_current; /**< @brief The currently running
-                                                thread.                     */
-} ReadyList;
-#endif /* !defined(PORT_OPTIMIZED_READYLIST_STRUCT) */
-
-#if !defined(PORT_OPTIMIZED_RLIST_EXT) && !defined(__DOXYGEN__)
-extern ReadyList rlist;
-#endif /* !defined(PORT_OPTIMIZED_RLIST_EXT) */
-
-/**
- * @brief   Current thread pointer access macro.
- * @note    This macro is not meant to be used in the application code but
- *          only from within the kernel, use the @p chThdSelf() API instead.
- * @note    It is forbidden to use this macro in order to change the pointer
- *          (currp = something), use @p setcurrp() instead.
- */
-#if !defined(PORT_OPTIMIZED_CURRP) || defined(__DOXYGEN__)
-#define currp rlist.r_current
-#endif /* !defined(PORT_OPTIMIZED_CURRP) */
-
-/**
- * @brief   Current thread pointer change macro.
- * @note    This macro is not meant to be used in the application code but
- *          only from within the kernel.
- *
- * @notapi
- */
-#if !defined(PORT_OPTIMIZED_SETCURRP) || defined(__DOXYGEN__)
-#define setcurrp(tp) (currp = (tp))
-#endif /* !defined(PORT_OPTIMIZED_SETCURRP) */
-
-/*
- * Scheduler APIs.
- */
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _scheduler_init(void);
-#if !defined(PORT_OPTIMIZED_READYI)
-  Thread *chSchReadyI(Thread *tp);
-#endif
-#if !defined(PORT_OPTIMIZED_GOSLEEPS)
-  void chSchGoSleepS(tstate_t newstate);
-#endif
-#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS)
-  msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time);
-#endif
-#if !defined(PORT_OPTIMIZED_WAKEUPS)
-  void chSchWakeupS(Thread *tp, msg_t msg);
-#endif
-#if !defined(PORT_OPTIMIZED_RESCHEDULES)
-  void chSchRescheduleS(void);
-#endif
-#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED)
-  bool_t chSchIsPreemptionRequired(void);
-#endif
-#if !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) || defined(__DOXYGEN__)
-  void chSchDoRescheduleBehind(void);
-#endif
-#if !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) || defined(__DOXYGEN__)
-  void chSchDoRescheduleAhead(void);
-#endif
-#if !defined(PORT_OPTIMIZED_DORESCHEDULE)
-  void chSchDoReschedule(void);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Determines if the current thread must reschedule.
- * @details This function returns @p TRUE if there is a ready thread with
- *          higher priority.
- *
- * @iclass
- */
-#if !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) || defined(__DOXYGEN__)
-#define chSchIsRescRequiredI() (firstprio(&rlist.r_queue) > currp->p_prio)
-#endif /* !defined(PORT_OPTIMIZED_ISRESCHREQUIREDI) */
-
-/**
- * @brief   Determines if yielding is possible.
- * @details This function returns @p TRUE if there is a ready thread with
- *          equal or higher priority.
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_CANYIELDS) || defined(__DOXYGEN__)
-#define chSchCanYieldS() (firstprio(&rlist.r_queue) >= currp->p_prio)
-#endif /* !defined(PORT_OPTIMIZED_CANYIELDS) */
-
-/**
- * @brief   Yields the time slot.
- * @details Yields the CPU control to the next thread in the ready list with
- *          equal or higher priority, if any.
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_DOYIELDS) || defined(__DOXYGEN__)
-#define chSchDoYieldS() {                                                   \
-  if (chSchCanYieldS())                                                     \
-    chSchDoRescheduleBehind();                                              \
-}
-#endif /* !defined(PORT_OPTIMIZED_DOYIELDS) */
-
-/**
- * @brief   Inline-able preemption code.
- * @details This is the common preemption code, this function must be invoked
- *          exclusively from the port layer.
- *
- * @special
- */
-#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
-#define chSchPreemption() {                                                 \
-  tprio_t p1 = firstprio(&rlist.r_queue);                                   \
-  tprio_t p2 = currp->p_prio;                                               \
-  if (currp->p_preempt) {                                                   \
-    if (p1 > p2)                                                            \
-      chSchDoRescheduleAhead();                                             \
-  }                                                                         \
-  else {                                                                    \
-    if (p1 >= p2)                                                           \
-      chSchDoRescheduleBehind();                                            \
-  }                                                                         \
-}
-#else /* CH_TIME_QUANTUM == 0 */
-#define chSchPreemption() {                                                 \
-  if (p1 >= p2)                                                             \
-    chSchDoRescheduleAhead();                                               \
-}
-#endif /* CH_TIME_QUANTUM == 0 */
-/** @} */
-
-#endif /* _CHSCHD_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chsem.h b/os/kernel/include/chsem.h
deleted file mode 100644
index b5036af7c..000000000
--- a/os/kernel/include/chsem.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chsem.h
- * @brief   Semaphores macros and structures.
- *
- * @addtogroup semaphores
- * @{
- */
-
-#ifndef _CHSEM_H_
-#define _CHSEM_H_
-
-#if CH_USE_SEMAPHORES || defined(__DOXYGEN__)
-
-/**
- * @brief   Semaphore structure.
- */
-typedef struct Semaphore {
-  ThreadsQueue          s_queue;    /**< @brief Queue of the threads sleeping
-                                                on this semaphore.          */
-  cnt_t                 s_cnt;      /**< @brief The semaphore counter.      */
-} Semaphore;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void chSemInit(Semaphore *sp, cnt_t n);
-  void chSemReset(Semaphore *sp, cnt_t n);
-  void chSemResetI(Semaphore *sp, cnt_t n);
-  msg_t chSemWait(Semaphore *sp);
-  msg_t chSemWaitS(Semaphore *sp);
-  msg_t chSemWaitTimeout(Semaphore *sp, systime_t time);
-  msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time);
-  void chSemSignal(Semaphore *sp);
-  void chSemSignalI(Semaphore *sp);
-  void chSemAddCounterI(Semaphore *sp, cnt_t n);
-#if CH_USE_SEMSW
-  msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @brief   Data part of a static semaphore initializer.
- * @details This macro should be used when statically initializing a semaphore
- *          that is part of a bigger structure.
- *
- * @param[in] name      the name of the semaphore variable
- * @param[in] n         the counter initial value, this value must be
- *                      non-negative
- */
-#define _SEMAPHORE_DATA(name, n) {_THREADSQUEUE_DATA(name.s_queue), n}
-
-/**
- * @brief   Static semaphore initializer.
- * @details Statically initialized semaphores require no explicit
- *          initialization using @p chSemInit().
- *
- * @param[in] name      the name of the semaphore variable
- * @param[in] n         the counter initial value, this value must be
- *                      non-negative
- */
-#define SEMAPHORE_DECL(name, n) Semaphore name = _SEMAPHORE_DATA(name, n)
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Decreases the semaphore counter.
- * @details This macro can be used when the counter is known to be positive.
- *
- * @iclass
- */
-#define chSemFastWaitI(sp)      ((sp)->s_cnt--)
-
-/**
- * @brief   Increases the semaphore counter.
- * @details This macro can be used when the counter is known to be not
- *          negative.
- *
- * @iclass
- */
-#define chSemFastSignalI(sp)    ((sp)->s_cnt++)
-
-/**
- * @brief   Returns the semaphore counter current value.
- *
- * @iclass
- */
-#define chSemGetCounterI(sp)    ((sp)->s_cnt)
-/** @} */
-
-#endif /* CH_USE_SEMAPHORES */
-
-#endif /* _CHSEM_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chsys.h b/os/kernel/include/chsys.h
deleted file mode 100644
index a1f59f38e..000000000
--- a/os/kernel/include/chsys.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chsys.h
- * @brief   System related macros and structures.
- *
- * @addtogroup system
- * @{
- */
-
-#ifndef _CHSYS_H_
-#define _CHSYS_H_
-
-/**
- * @name    Macro Functions
- * @{
- */
-#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__)
-/**
- * @brief   Returns a pointer to the idle thread.
- * @pre     In order to use this function the option @p CH_NO_IDLE_THREAD
- *          must be disabled.
- * @note    The reference counter of the idle thread is not incremented but
- *          it is not strictly required being the idle thread a static
- *          object.
- *
- * @return              Pointer to the idle thread.
- *
- * @api
- */
-#define chSysGetIdleThread() (rlist.r_queue.p_prev)
-#endif
-
-/**
- * @brief   Halts the system.
- * @details This function is invoked by the operating system when an
- *          unrecoverable error is detected, for example because a programming
- *          error in the application code that triggers an assertion while
- *          in debug mode.
- * @note    Can be invoked from any system state.
- *
- * @special
- */
-#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
-#define chSysHalt() port_halt()
-#else
-#define chSysHalt() {                                                       \
-  SYSTEM_HALT_HOOK();                                                       \
-  port_halt();                                                              \
-}
-#endif
-
-/**
- * @brief   Performs a context switch.
- * @note    Not a user function, it is meant to be invoked by the scheduler
- *          itself or from within the port layer.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- *
- * @special
- */
-#define chSysSwitch(ntp, otp) {                                             \
-  dbg_trace(otp);                                                           \
-  THREAD_CONTEXT_SWITCH_HOOK(ntp, otp);                                     \
-  port_switch(ntp, otp);                                                    \
-}
-
-/**
- * @brief   Raises the system interrupt priority mask to the maximum level.
- * @details All the maskable interrupt sources are disabled regardless their
- *          hardware priority.
- * @note    Do not invoke this API from within a kernel lock.
- *
- * @special
- */
-#define chSysDisable() {                                                    \
-  port_disable();                                                           \
-  dbg_check_disable();                                                      \
-}
-
-/**
- * @brief   Raises the system interrupt priority mask to system level.
- * @details The interrupt sources that should not be able to preempt the kernel
- *          are disabled, interrupt sources with higher priority are still
- *          enabled.
- * @note    Do not invoke this API from within a kernel lock.
- * @note    This API is no replacement for @p chSysLock(), the @p chSysLock()
- *          could do more than just disable the interrupts.
- *
- * @special
- */
-#define chSysSuspend() {                                                    \
-  port_suspend();                                                           \
-  dbg_check_suspend();                                                      \
-}
-
-/**
- * @brief   Lowers the system interrupt priority mask to user level.
- * @details All the interrupt sources are enabled.
- * @note    Do not invoke this API from within a kernel lock.
- * @note    This API is no replacement for @p chSysUnlock(), the
- *          @p chSysUnlock() could do more than just enable the interrupts.
- *
- * @special
- */
-#define chSysEnable() {                                                     \
-  dbg_check_enable();                                                       \
-  port_enable();                                                            \
-}
-
-/**
- * @brief   Enters the kernel lock mode.
- *
- * @special
- */
-#define chSysLock()  {                                                      \
-  port_lock();                                                              \
-  dbg_check_lock();                                                         \
-}
-
-/**
- * @brief   Leaves the kernel lock mode.
- *
- * @special
- */
-#define chSysUnlock() {                                                     \
-  dbg_check_unlock();                                                       \
-  port_unlock();                                                            \
-}
-
-/**
- * @brief   Enters the kernel lock mode from within an interrupt handler.
- * @note    This API may do nothing on some architectures, it is required
- *          because on ports that support preemptable interrupt handlers
- *          it is required to raise the interrupt mask to the same level of
- *          the system mutual exclusion zone.<br>
- *          It is good practice to invoke this API before invoking any I-class
- *          syscall from an interrupt handler.
- * @note    This API must be invoked exclusively from interrupt handlers.
- *
- * @special
- */
-#define chSysLockFromIsr() {                                                \
-  port_lock_from_isr();                                                     \
-  dbg_check_lock_from_isr();                                                \
-}
-
-/**
- * @brief   Leaves the kernel lock mode from within an interrupt handler.
- *
- * @note    This API may do nothing on some architectures, it is required
- *          because on ports that support preemptable interrupt handlers
- *          it is required to raise the interrupt mask to the same level of
- *          the system mutual exclusion zone.<br>
- *          It is good practice to invoke this API after invoking any I-class
- *          syscall from an interrupt handler.
- * @note    This API must be invoked exclusively from interrupt handlers.
- *
- * @special
- */
-#define chSysUnlockFromIsr() {                                              \
-  dbg_check_unlock_from_isr();                                              \
-  port_unlock_from_isr();                                                   \
-}
-/** @} */
-
-/**
- * @name    ISRs abstraction macros
- */
-/**
- * @brief   IRQ handler enter code.
- * @note    Usually IRQ handlers functions are also declared naked.
- * @note    On some architectures this macro can be empty.
- *
- * @special
- */
-#define CH_IRQ_PROLOGUE()                                                   \
-  PORT_IRQ_PROLOGUE();                                                      \
-  dbg_check_enter_isr();
-
-/**
- * @brief   IRQ handler exit code.
- * @note    Usually IRQ handlers function are also declared naked.
- * @note    This macro usually performs the final reschedule by using
- *          @p chSchIsPreemptionRequired() and @p chSchDoReschedule().
- *
- * @special
- */
-#define CH_IRQ_EPILOGUE()                                                   \
-  dbg_check_leave_isr();                                                    \
-  PORT_IRQ_EPILOGUE();
-
-/**
- * @brief   Standard normal IRQ handler declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- *
- * @special
- */
-#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id)
-/** @} */
-
-/**
- * @name    Fast ISRs abstraction macros
- */
-/**
- * @brief   Standard fast IRQ handler declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- * @note    Not all architectures support fast interrupts.
- *
- * @special
- */
-#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id)
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void chSysInit(void);
-  void chSysTimerHandlerI(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHSYS_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chthreads.h b/os/kernel/include/chthreads.h
deleted file mode 100644
index 07cdd23ff..000000000
--- a/os/kernel/include/chthreads.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chthreads.h
- * @brief   Threads macros and structures.
- *
- * @addtogroup threads
- * @{
- */
-
-#ifndef _CHTHREADS_H_
-#define _CHTHREADS_H_
-
-/**
- * @name    Thread states
- * @{
- */
-#define THD_STATE_READY         0   /**< @brief Waiting on the ready list.  */
-#define THD_STATE_CURRENT       1   /**< @brief Currently running.          */
-#define THD_STATE_SUSPENDED     2   /**< @brief Created in suspended state. */
-#define THD_STATE_WTSEM         3   /**< @brief Waiting on a semaphore.     */
-#define THD_STATE_WTMTX         4   /**< @brief Waiting on a mutex.         */
-#define THD_STATE_WTCOND        5   /**< @brief Waiting on a condition
-                                         variable.                          */
-#define THD_STATE_SLEEPING      6   /**< @brief Waiting in @p chThdSleep()
-                                         or @p chThdSleepUntil().           */
-#define THD_STATE_WTEXIT        7   /**< @brief Waiting in @p chThdWait().  */
-#define THD_STATE_WTOREVT       8   /**< @brief Waiting for an event.       */
-#define THD_STATE_WTANDEVT      9   /**< @brief Waiting for several events. */
-#define THD_STATE_SNDMSGQ       10  /**< @brief Sending a message, in queue.*/
-#define THD_STATE_SNDMSG        11  /**< @brief Sent a message, waiting
-                                         answer.                            */
-#define THD_STATE_WTMSG         12  /**< @brief Waiting for a message.      */
-#define THD_STATE_WTQUEUE       13  /**< @brief Waiting on an I/O queue.    */
-#define THD_STATE_FINAL         14  /**< @brief Thread terminated.          */
-
-/**
- * @brief   Thread states as array of strings.
- * @details Each element in an array initialized with this macro can be
- *          indexed using the numeric thread state values.
- */
-#define THD_STATE_NAMES                                                     \
-  "READY", "CURRENT", "SUSPENDED", "WTSEM", "WTMTX", "WTCOND", "SLEEPING",  \
-  "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", "SNDMSG", "WTMSG", "WTQUEUE", \
-  "FINAL"
-/** @} */
-
-/**
- * @name    Thread flags and attributes
- * @{
- */
-#define THD_MEM_MODE_MASK       3   /**< @brief Thread memory mode mask.    */
-#define THD_MEM_MODE_STATIC     0   /**< @brief Static thread.              */
-#define THD_MEM_MODE_HEAP       1   /**< @brief Thread allocated from a
-                                         Memory Heap.                       */
-#define THD_MEM_MODE_MEMPOOL    2   /**< @brief Thread allocated from a
-                                         Memory Pool.                       */
-#define THD_TERMINATE           4   /**< @brief Termination requested flag. */
-/** @} */
-
-/**
- * @extends ThreadsQueue
- *
- * @brief   Structure representing a thread.
- * @note    Not all the listed fields are always needed, by switching off some
- *          not needed ChibiOS/RT subsystems it is possible to save RAM space
- *          by shrinking the @p Thread structure.
- */
-struct Thread {
-  Thread                *p_next;    /**< @brief Next in the list/queue.     */
-  /* End of the fields shared with the ThreadsList structure. */
-  Thread                *p_prev;    /**< @brief Previous in the queue.      */
-  /* End of the fields shared with the ThreadsQueue structure. */
-  tprio_t               p_prio;     /**< @brief Thread priority.            */
-  struct context        p_ctx;      /**< @brief Processor context.          */
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
-  Thread                *p_newer;   /**< @brief Newer registry element.     */
-  Thread                *p_older;   /**< @brief Older registry element.     */
-#endif
-  /* End of the fields shared with the ReadyList structure. */
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
-  /**
-   * @brief Thread name or @p NULL.
-   */
-  const char            *p_name;
-#endif
-#if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-  /**
-   * @brief Thread stack boundary.
-   */
-  stkalign_t            *p_stklimit;
-#endif
-  /**
-   * @brief Current thread state.
-   */
-  tstate_t              p_state;
-  /**
-   * @brief Various thread flags.
-   */
-  tmode_t               p_flags;
-#if CH_USE_DYNAMIC || defined(__DOXYGEN__)
-  /**
-   * @brief References to this thread.
-   */
-  trefs_t               p_refs;
-#endif
-  /**
-   * @brief Number of ticks remaining to this thread.
-   */
-#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
-  tslices_t             p_preempt;
-#endif
-#if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__)
-  /**
-   * @brief Thread consumed time in ticks.
-   * @note  This field can overflow.
-   */
-  volatile systime_t    p_time;
-#endif
-  /**
-   * @brief State-specific fields.
-   * @note  All the fields declared in this union are only valid in the
-   *        specified state or condition and are thus volatile.
-   */
-  union {
-    /**
-     * @brief Thread wakeup code.
-     * @note  This field contains the low level message sent to the thread
-     *        by the waking thread or interrupt handler. The value is valid
-     *        after exiting the @p chSchWakeupS() function.
-     */
-    msg_t               rdymsg;
-    /**
-     * @brief Thread exit code.
-     * @note  The thread termination code is stored in this field in order
-     *        to be retrieved by the thread performing a @p chThdWait() on
-     *        this thread.
-     */
-    msg_t               exitcode;
-    /**
-     * @brief Pointer to a generic "wait" object.
-     * @note  This field is used to get a generic pointer to a synchronization
-     *        object and is valid when the thread is in one of the wait
-     *        states.
-     */
-    void                *wtobjp;
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
-    /**
-     * @brief Enabled events mask.
-     * @note  This field is only valid while the thread is in the
-     *        @p THD_STATE_WTOREVT or @p THD_STATE_WTANDEVT states.
-     */
-    eventmask_t         ewmask;
-#endif
-  }                     p_u;
-#if CH_USE_WAITEXIT || defined(__DOXYGEN__)
-  /**
-   * @brief Termination waiting list.
-   */
-  ThreadsList           p_waiting;
-#endif
-#if CH_USE_MESSAGES || defined(__DOXYGEN__)
-  /**
-   * @brief Messages queue.
-   */
-  ThreadsQueue          p_msgqueue;
-  /**
-   * @brief Thread message.
-   */
-  msg_t                 p_msg;
-#endif
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
-  /**
-   * @brief Pending events mask.
-   */
-  eventmask_t           p_epending;
-#endif
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  /**
-   * @brief List of the mutexes owned by this thread.
-   * @note  The list is terminated by a @p NULL in this field.
-   */
-  Mutex                 *p_mtxlist;
-  /**
-   * @brief Thread's own, non-inherited, priority.
-   */
-  tprio_t               p_realprio;
-#endif
-#if (CH_USE_DYNAMIC && CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
-  /**
-   * @brief Memory Pool where the thread workspace is returned.
-   */
-  void                  *p_mpool;
-#endif
-#if defined(THREAD_EXT_FIELDS)
-  /* Extra fields defined in chconf.h.*/
-  THREAD_EXT_FIELDS
-#endif
-};
-
-/**
- * @brief Thread function.
- */
-typedef msg_t (*tfunc_t)(void *);
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Returns a pointer to the current @p Thread.
- * @note    Can be invoked in any context.
- *
- * @special
- */
-#define chThdSelf() currp
-
-/**
- * @brief   Returns the current thread priority.
- * @note    Can be invoked in any context.
- *
- * @special
- */
-#define chThdGetPriority() (currp->p_prio)
-
-/**
- * @brief   Returns the number of ticks consumed by the specified thread.
- * @note    This function is only available when the
- *          @p CH_DBG_THREADS_PROFILING configuration option is enabled.
- * @note    Can be invoked in any context.
- *
- * @param[in] tp        pointer to the thread
- *
- * @special
- */
-#define chThdGetTicks(tp) ((tp)->p_time)
-
-/**
- * @brief   Returns the pointer to the @p Thread local storage area, if any.
- * @note    Can be invoked in any context.
- *
- * @special
- */
-#define chThdLS() (void *)(currp + 1)
-
-/**
- * @brief   Verifies if the specified thread is in the @p THD_STATE_FINAL state.
- * @note    Can be invoked in any context.
- *
- * @param[in] tp        pointer to the thread
- * @retval TRUE         thread terminated.
- * @retval FALSE        thread not terminated.
- *
- * @special
- */
-#define chThdTerminated(tp) ((tp)->p_state == THD_STATE_FINAL)
-
-/**
- * @brief   Verifies if the current thread has a termination request pending.
- * @note    Can be invoked in any context.
- *
- * @retval 0            termination request not pending.
- * @retval !0           termination request pending.
- *
- * @special
- */
-#define chThdShouldTerminate() (currp->p_flags & THD_TERMINATE)
-
-/**
- * @brief   Resumes a thread created with @p chThdCreateI().
- *
- * @param[in] tp        pointer to the thread
- *
- * @iclass
- */
-#define chThdResumeI(tp) chSchReadyI(tp)
-
-/**
- * @brief   Suspends the invoking thread for the specified time.
- *
- * @param[in] time      the delay in system ticks, the special values are
- *                      handled as follow:
- *                      - @a TIME_INFINITE the thread enters an infinite sleep
- *                        state.
- *                      - @a TIME_IMMEDIATE this value is not allowed.
- *                      .
- *
- * @sclass
- */
-#define chThdSleepS(time) chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time)
-
-/**
- * @brief   Delays the invoking thread for the specified number of seconds.
- * @note    The specified time is rounded up to a value allowed by the real
- *          system tick clock.
- * @note    The maximum specifiable value is implementation dependent.
- *
- * @param[in] sec       time in seconds, must be different from zero
- *
- * @api
- */
-#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec))
-
-/**
- * @brief   Delays the invoking thread for the specified number of
- *          milliseconds.
- * @note    The specified time is rounded up to a value allowed by the real
- *          system tick clock.
- * @note    The maximum specifiable value is implementation dependent.
- *
- * @param[in] msec      time in milliseconds, must be different from zero
- *
- * @api
- */
-#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec))
-
-/**
- * @brief   Delays the invoking thread for the specified number of
- *          microseconds.
- * @note    The specified time is rounded up to a value allowed by the real
- *          system tick clock.
- * @note    The maximum specifiable value is implementation dependent.
- *
- * @param[in] usec      time in microseconds, must be different from zero
- *
- * @api
- */
-#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec))
-/** @} */
-
-/*
- * Threads APIs.
- */
-#ifdef __cplusplus
-extern "C" {
-#endif
-  Thread *_thread_init(Thread *tp, tprio_t prio);
-#if CH_DBG_FILL_THREADS
-  void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v);
-#endif
-  Thread *chThdCreateI(void *wsp, size_t size,
-                       tprio_t prio, tfunc_t pf, void *arg);
-  Thread *chThdCreateStatic(void *wsp, size_t size,
-                            tprio_t prio, tfunc_t pf, void *arg);
-  tprio_t chThdSetPriority(tprio_t newprio);
-  Thread *chThdResume(Thread *tp);
-  void chThdTerminate(Thread *tp);
-  void chThdSleep(systime_t time);
-  void chThdSleepUntil(systime_t time);
-  void chThdYield(void);
-  void chThdExit(msg_t msg);
-  void chThdExitS(msg_t msg);
-#if CH_USE_WAITEXIT
-  msg_t chThdWait(Thread *tp);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHTHREADS_H_ */
-
-/** @} */
diff --git a/os/kernel/include/chvt.h b/os/kernel/include/chvt.h
deleted file mode 100644
index c1b246cd3..000000000
--- a/os/kernel/include/chvt.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chvt.h
- * @brief   Time macros and structures.
- *
- * @addtogroup time
- * @{
- */
-
-#ifndef _CHVT_H_
-#define _CHVT_H_
-
-/**
- * @name    Time conversion utilities
- * @{
- */
-/**
- * @brief   Seconds to system ticks.
- * @details Converts from seconds to system ticks number.
- * @note    The result is rounded upward to the next tick boundary.
- *
- * @param[in] sec       number of seconds
- * @return              The number of ticks.
- *
- * @api
- */
-#define S2ST(sec)                                                           \
-  ((systime_t)((sec) * CH_FREQUENCY))
-
-/**
- * @brief   Milliseconds to system ticks.
- * @details Converts from milliseconds to system ticks number.
- * @note    The result is rounded upward to the next tick boundary.
- *
- * @param[in] msec      number of milliseconds
- * @return              The number of ticks.
- *
- * @api
- */
-#define MS2ST(msec)                                                         \
-  ((systime_t)(((((uint32_t)(msec)) * ((uint32_t)CH_FREQUENCY) - 1UL) /     \
-                1000UL) + 1UL))
-
-/**
- * @brief   Microseconds to system ticks.
- * @details Converts from microseconds to system ticks number.
- * @note    The result is rounded upward to the next tick boundary.
- *
- * @param[in] usec      number of microseconds
- * @return              The number of ticks.
- *
- * @api
- */
-#define US2ST(usec)                                                         \
-  ((systime_t)(((((uint32_t)(usec)) * ((uint32_t)CH_FREQUENCY) - 1UL) /     \
-                1000000UL) + 1UL))
-/** @} */
-
-/**
- * @brief   Virtual Timer callback function.
- */
-typedef void (*vtfunc_t)(void *);
-
-/**
- * @brief   Virtual Timer structure type.
- */
-typedef struct VirtualTimer VirtualTimer;
-
-/**
- * @extends VTList
- *
- * @brief   Virtual Timer descriptor structure.
- */
-struct VirtualTimer {
-  VirtualTimer          *vt_next;   /**< @brief Next timer in the delta
-                                                list.                       */
-  VirtualTimer          *vt_prev;   /**< @brief Previous timer in the delta
-                                                list.                       */
-  systime_t             vt_time;    /**< @brief Time delta before timeout.  */
-  vtfunc_t              vt_func;    /**< @brief Timer callback function
-                                                pointer.                    */
-  void                  *vt_par;    /**< @brief Timer callback function
-                                                parameter.                  */
-};
-
-/**
- * @brief   Virtual timers list header.
- * @note    The delta list is implemented as a double link bidirectional list
- *          in order to make the unlink time constant, the reset of a virtual
- *          timer is often used in the code.
- */
-typedef struct {
-  VirtualTimer          *vt_next;   /**< @brief Next timer in the delta
-                                                list.                       */
-  VirtualTimer          *vt_prev;   /**< @brief Last timer in the delta
-                                                list.                       */
-  systime_t             vt_time;    /**< @brief Must be initialized to -1.  */
-  volatile systime_t    vt_systime; /**< @brief System Time counter.        */
-} VTList;
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Virtual timers ticker.
- * @note    The system lock is released before entering the callback and
- *          re-acquired immediately after. It is callback's responsibility
- *          to acquire the lock if needed. This is done in order to reduce
- *          interrupts jitter when many timers are in use.
- *
- * @iclass
- */
-#define chVTDoTickI() {                                                     \
-  vtlist.vt_systime++;                                                      \
-  if (&vtlist != (VTList *)vtlist.vt_next) {                                \
-    VirtualTimer *vtp;                                                      \
-                                                                            \
-    --vtlist.vt_next->vt_time;                                              \
-    while (!(vtp = vtlist.vt_next)->vt_time) {                              \
-      vtfunc_t fn = vtp->vt_func;                                           \
-      vtp->vt_func = (vtfunc_t)NULL;                                        \
-      vtp->vt_next->vt_prev = (void *)&vtlist;                              \
-      (&vtlist)->vt_next = vtp->vt_next;                                    \
-      chSysUnlockFromIsr();                                                 \
-      fn(vtp->vt_par);                                                      \
-      chSysLockFromIsr();                                                   \
-    }                                                                       \
-  }                                                                         \
-}
-
-/**
- * @brief   Returns @p TRUE if the specified timer is armed.
- *
- * @iclass
- */
-#define chVTIsArmedI(vtp) ((vtp)->vt_func != NULL)
-
-/**
- * @brief   Enables a virtual timer.
- * @note    The associated function is invoked from interrupt context.
- *
- * @param[out] vtp      the @p VirtualTimer structure pointer
- * @param[in] time      the number of ticks before the operation timeouts, the
- *                      special values are handled as follow:
- *                      - @a TIME_INFINITE is allowed but interpreted as a
- *                        normal time specification.
- *                      - @a TIME_IMMEDIATE this value is not allowed.
- *                      .
- * @param[in] vtfunc    the timer callback function. After invoking the
- *                      callback the timer is disabled and the structure can
- *                      be disposed or reused.
- * @param[in] par       a parameter that will be passed to the callback
- *                      function
- *
- * @api
- */
-#define chVTSet(vtp, time, vtfunc, par) {                                   \
-  chSysLock();                                                              \
-  chVTSetI(vtp, time, vtfunc, par);                                         \
-  chSysUnlock();                                                            \
-}
-
-/**
- * @brief   Disables a Virtual Timer.
- * @note    The timer is first checked and disabled only if armed.
- *
- * @param[in] vtp       the @p VirtualTimer structure pointer
- *
- * @api
- */
-#define chVTReset(vtp) {                                                    \
-  chSysLock();                                                              \
-  if (chVTIsArmedI(vtp))                                                    \
-    chVTResetI(vtp);                                                        \
-  chSysUnlock();                                                            \
-}
-
-/**
- * @brief   Current system time.
- * @details Returns the number of system ticks since the @p chSysInit()
- *          invocation.
- * @note    The counter can reach its maximum and then restart from zero.
- * @note    This function is designed to work with the @p chThdSleepUntil().
- *
- * @return              The system time in ticks.
- *
- * @api
- */
-#define chTimeNow() (vtlist.vt_systime)
-
-/**
- * @brief   Returns the elapsed time since the specified start time.
- *
- * @param[in] start     start time
- * @return              The elapsed time.
- *
- * @api
- */
-#define chTimeElapsedSince(start) (chTimeNow() - (start))
-
-/**
- * @brief   Checks if the current system time is within the specified time
- *          window.
- * @note    When start==end then the function returns always true because the
- *          whole time range is specified.
- *
- * @param[in] start     the start of the time window (inclusive)
- * @param[in] end       the end of the time window (non inclusive)
- * @retval TRUE         current time within the specified time window.
- * @retval FALSE        current time not within the specified time window.
- *
- * @api
- */
-#define chTimeIsWithin(start, end)                                          \
-  (chTimeElapsedSince(start) < ((end) - (start)))
-/** @} */
-
-extern VTList vtlist;
-
-/*
- * Virtual Timers APIs.
- */
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _vt_init(void);
-  void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par);
-  void chVTResetI(VirtualTimer *vtp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHVT_H_ */
-
-/** @} */
diff --git a/os/kernel/kernel.mk b/os/kernel/kernel.mk
deleted file mode 100644
index 3ebf2ed98..000000000
--- a/os/kernel/kernel.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-# List of all the ChibiOS/RT kernel files, there is no need to remove the files
-# from this list, you can disable parts of the kernel by editing chconf.h.
-KERNSRC = ${CHIBIOS}/os/kernel/src/chsys.c \
-          ${CHIBIOS}/os/kernel/src/chdebug.c \
-          ${CHIBIOS}/os/kernel/src/chlists.c \
-          ${CHIBIOS}/os/kernel/src/chvt.c \
-          ${CHIBIOS}/os/kernel/src/chschd.c \
-          ${CHIBIOS}/os/kernel/src/chthreads.c \
-          ${CHIBIOS}/os/kernel/src/chdynamic.c \
-          ${CHIBIOS}/os/kernel/src/chregistry.c \
-          ${CHIBIOS}/os/kernel/src/chsem.c \
-          ${CHIBIOS}/os/kernel/src/chmtx.c \
-          ${CHIBIOS}/os/kernel/src/chcond.c \
-          ${CHIBIOS}/os/kernel/src/chevents.c \
-          ${CHIBIOS}/os/kernel/src/chmsg.c \
-          ${CHIBIOS}/os/kernel/src/chmboxes.c \
-          ${CHIBIOS}/os/kernel/src/chqueues.c \
-          ${CHIBIOS}/os/kernel/src/chmemcore.c \
-          ${CHIBIOS}/os/kernel/src/chheap.c \
-          ${CHIBIOS}/os/kernel/src/chmempools.c
-
-# Required include directories
-KERNINC = ${CHIBIOS}/os/kernel/include
diff --git a/os/kernel/src/chcond.c b/os/kernel/src/chcond.c
deleted file mode 100644
index c217bf6fd..000000000
--- a/os/kernel/src/chcond.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-/*
-   Concepts and parts of this file have been contributed by Leon Woestenberg.
- */
-
-/**
- * @file    chcond.c
- * @brief   Condition Variables code.
- *
- * @addtogroup condvars Condition Variables
- * @details This module implements the Condition Variables mechanism. Condition
- *          variables are an extensions to the Mutex subsystem and cannot
- *          work alone.
- *          <h2>Operation mode</h2>
- *          The condition variable is a synchronization object meant to be
- *          used inside a zone protected by a @p Mutex. Mutexes and CondVars
- *          together can implement a Monitor construct.
- * @pre     In order to use the condition variable APIs the @p CH_USE_CONDVARS
- *          option must be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if (CH_USE_CONDVARS && CH_USE_MUTEXES) || defined(__DOXYGEN__)
-
-/**
- * @brief   Initializes s @p CondVar structure.
- *
- * @param[out] cp       pointer to a @p CondVar structure
- *
- * @init
- */
-void chCondInit(CondVar *cp) {
-
-  chDbgCheck(cp != NULL, "chCondInit");
-
-  queue_init(&cp->c_queue);
-}
-
-/**
- * @brief   Signals one thread that is waiting on the condition variable.
- *
- * @param[in] cp        pointer to the @p CondVar structure
- *
- * @api
- */
-void chCondSignal(CondVar *cp) {
-
-  chDbgCheck(cp != NULL, "chCondSignal");
-
-  chSysLock();
-  if (notempty(&cp->c_queue))
-    chSchWakeupS(fifo_remove(&cp->c_queue), RDY_OK);
-  chSysUnlock();
-}
-
-/**
- * @brief   Signals one thread that is waiting on the condition variable.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel. Note that
- *          interrupt handlers always reschedule on exit so an explicit
- *          reschedule must not be performed in ISRs.
- *
- * @param[in] cp        pointer to the @p CondVar structure
- *
- * @iclass
- */
-void chCondSignalI(CondVar *cp) {
-
-  chDbgCheckClassI();
-  chDbgCheck(cp != NULL, "chCondSignalI");
-
-  if (notempty(&cp->c_queue))
-    chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_OK;
-}
-
-/**
- * @brief   Signals all threads that are waiting on the condition variable.
- *
- * @param[in] cp        pointer to the @p CondVar structure
- *
- * @api
- */
-void chCondBroadcast(CondVar *cp) {
-
-  chSysLock();
-  chCondBroadcastI(cp);
-  chSchRescheduleS();
-  chSysUnlock();
-}
-
-/**
- * @brief   Signals all threads that are waiting on the condition variable.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel. Note that
- *          interrupt handlers always reschedule on exit so an explicit
- *          reschedule must not be performed in ISRs.
- *
- * @param[in] cp        pointer to the @p CondVar structure
- *
- * @iclass
- */
-void chCondBroadcastI(CondVar *cp) {
-
-  chDbgCheckClassI();
-  chDbgCheck(cp != NULL, "chCondBroadcastI");
-
-  /* Empties the condition variable queue and inserts all the Threads into the
-     ready list in FIFO order. The wakeup message is set to @p RDY_RESET in
-     order to make a chCondBroadcast() detectable from a chCondSignal().*/
-  while (cp->c_queue.p_next != (void *)&cp->c_queue)
-    chSchReadyI(fifo_remove(&cp->c_queue))->p_u.rdymsg = RDY_RESET;
-}
-
-/**
- * @brief   Waits on the condition variable releasing the mutex lock.
- * @details Releases the currently owned mutex, waits on the condition
- *          variable, and finally acquires the mutex again. All the sequence
- *          is performed atomically.
- * @pre     The invoking thread <b>must</b> have at least one owned mutex.
- *
- * @param[in] cp        pointer to the @p CondVar structure
- * @return              A message specifying how the invoking thread has been
- *                      released from the condition variable.
- * @retval RDY_OK       if the condvar has been signaled using
- *                      @p chCondSignal().
- * @retval RDY_RESET    if the condvar has been signaled using
- *                      @p chCondBroadcast().
- *
- * @api
- */
-msg_t chCondWait(CondVar *cp) {
-  msg_t msg;
-
-  chSysLock();
-  msg = chCondWaitS(cp);
-  chSysUnlock();
-  return msg;
-}
-
-/**
- * @brief   Waits on the condition variable releasing the mutex lock.
- * @details Releases the currently owned mutex, waits on the condition
- *          variable, and finally acquires the mutex again. All the sequence
- *          is performed atomically.
- * @pre     The invoking thread <b>must</b> have at least one owned mutex.
- *
- * @param[in] cp        pointer to the @p CondVar structure
- * @return              A message specifying how the invoking thread has been
- *                      released from the condition variable.
- * @retval RDY_OK       if the condvar has been signaled using
- *                      @p chCondSignal().
- * @retval RDY_RESET    if the condvar has been signaled using
- *                      @p chCondBroadcast().
- *
- * @sclass
- */
-msg_t chCondWaitS(CondVar *cp) {
-  Thread *ctp = currp;
-  Mutex *mp;
-  msg_t msg;
-
-  chDbgCheckClassS();
-  chDbgCheck(cp != NULL, "chCondWaitS");
-  chDbgAssert(ctp->p_mtxlist != NULL,
-              "chCondWaitS(), #1",
-              "not owning a mutex");
-
-  mp = chMtxUnlockS();
-  ctp->p_u.wtobjp = cp;
-  prio_insert(ctp, &cp->c_queue);
-  chSchGoSleepS(THD_STATE_WTCOND);
-  msg = ctp->p_u.rdymsg;
-  chMtxLockS(mp);
-  return msg;
-}
-
-#if CH_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__)
-/**
- * @brief   Waits on the condition variable releasing the mutex lock.
- * @details Releases the currently owned mutex, waits on the condition
- *          variable, and finally acquires the mutex again. All the sequence
- *          is performed atomically.
- * @pre     The invoking thread <b>must</b> have at least one owned mutex.
- * @pre     The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled
- *          in order to use this function.
- * @post    Exiting the function because a timeout does not re-acquire the
- *          mutex, the mutex ownership is lost.
- *
- * @param[in] cp        pointer to the @p CondVar structure
- * @param[in] time      the number of ticks before the operation timeouts, the
- *                      special values are handled as follow:
- *                      - @a TIME_INFINITE no timeout.
- *                      - @a TIME_IMMEDIATE this value is not allowed.
- *                      .
- * @return              A message specifying how the invoking thread has been
- *                      released from the condition variable.
- * @retval RDY_OK       if the condvar has been signaled using
- *                      @p chCondSignal().
- * @retval RDY_RESET    if the condvar has been signaled using
- *                      @p chCondBroadcast().
- * @retval RDY_TIMEOUT  if the condvar has not been signaled within the
- *                      specified timeout.
- *
- * @api
- */
-msg_t chCondWaitTimeout(CondVar *cp, systime_t time) {
-  msg_t msg;
-
-  chSysLock();
-  msg = chCondWaitTimeoutS(cp, time);
-  chSysUnlock();
-  return msg;
-}
-
-/**
- * @brief   Waits on the condition variable releasing the mutex lock.
- * @details Releases the currently owned mutex, waits on the condition
- *          variable, and finally acquires the mutex again. All the sequence
- *          is performed atomically.
- * @pre     The invoking thread <b>must</b> have at least one owned mutex.
- * @pre     The configuration option @p CH_USE_CONDVARS_TIMEOUT must be enabled
- *          in order to use this function.
- * @post    Exiting the function because a timeout does not re-acquire the
- *          mutex, the mutex ownership is lost.
- *
- * @param[in] cp        pointer to the @p CondVar structure
- * @param[in] time      the number of ticks before the operation timeouts, the
- *                      special values are handled as follow:
- *                      - @a TIME_INFINITE no timeout.
- *                      - @a TIME_IMMEDIATE this value is not allowed.
- *                      .
- * @return              A message specifying how the invoking thread has been
- *                      released from the condition variable.
- * @retval RDY_OK       if the condvar has been signaled using
- *                      @p chCondSignal().
- * @retval RDY_RESET    if the condvar has been signaled using
- *                      @p chCondBroadcast().
- * @retval RDY_TIMEOUT  if the condvar has not been signaled within the
- *                      specified timeout.
- *
- * @sclass
- */
-msg_t chCondWaitTimeoutS(CondVar *cp, systime_t time) {
-  Mutex *mp;
-  msg_t msg;
-
-  chDbgCheckClassS();
-  chDbgCheck((cp != NULL) && (time != TIME_IMMEDIATE), "chCondWaitTimeoutS");
-  chDbgAssert(currp->p_mtxlist != NULL,
-              "chCondWaitTimeoutS(), #1",
-              "not owning a mutex");
-
-  mp = chMtxUnlockS();
-  currp->p_u.wtobjp = cp;
-  prio_insert(currp, &cp->c_queue);
-  msg = chSchGoSleepTimeoutS(THD_STATE_WTCOND, time);
-  if (msg != RDY_TIMEOUT)
-    chMtxLockS(mp);
-  return msg;
-}
-#endif /* CH_USE_CONDVARS_TIMEOUT */
-
-#endif /* CH_USE_CONDVARS && CH_USE_MUTEXES */
-
-/** @} */
diff --git a/os/kernel/src/chdebug.c b/os/kernel/src/chdebug.c
deleted file mode 100644
index c69ce8f3f..000000000
--- a/os/kernel/src/chdebug.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chdebug.c
- * @brief   ChibiOS/RT Debug code.
- *
- * @addtogroup debug
- * @details Debug APIs and services:
- *          - Runtime system state and call protocol check. The following
- *            panic messages can be generated:
- *            - SV#1, misplaced @p chSysDisable().
- *            - SV#2, misplaced @p chSysSuspend()
- *            - SV#3, misplaced @p chSysEnable().
- *            - SV#4, misplaced @p chSysLock().
- *            - SV#5, misplaced @p chSysUnlock().
- *            - SV#6, misplaced @p chSysLockFromIsr().
- *            - SV#7, misplaced @p chSysUnlockFromIsr().
- *            - SV#8, misplaced @p CH_IRQ_PROLOGUE().
- *            - SV#9, misplaced @p CH_IRQ_EPILOGUE().
- *            - SV#10, misplaced I-class function.
- *            - SV#11, misplaced S-class function.
- *            .
- *          - Trace buffer.
- *          - Parameters check.
- *          - Kernel assertions.
- *          - Kernel panics.
- *          .
- * @note    Stack checks are not implemented in this module but in the port
- *          layer in an architecture-dependent way.
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* System state checker related code and variables.                          */
-/*===========================================================================*/
-
-#if CH_DBG_SYSTEM_STATE_CHECK || defined(__DOXYGEN__)
-
-/**
- * @brief   ISR nesting level.
- */
-cnt_t dbg_isr_cnt;
-
-/**
- * @brief   Lock nesting level.
- */
-cnt_t dbg_lock_cnt;
-
-/**
- * @brief   Guard code for @p chSysDisable().
- *
- * @notapi
- */
-void dbg_check_disable(void) {
-
-  if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0))
-    chDbgPanic("SV#1");
-}
-
-/**
- * @brief   Guard code for @p chSysSuspend().
- *
- * @notapi
- */
-void dbg_check_suspend(void) {
-
-  if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0))
-    chDbgPanic("SV#2");
-}
-
-/**
- * @brief   Guard code for @p chSysEnable().
- *
- * @notapi
- */
-void dbg_check_enable(void) {
-
-  if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0))
-    chDbgPanic("SV#3");
-}
-
-/**
- * @brief   Guard code for @p chSysLock().
- *
- * @notapi
- */
-void dbg_check_lock(void) {
-
-  if ((dbg_isr_cnt != 0) || (dbg_lock_cnt != 0))
-    chDbgPanic("SV#4");
-  dbg_enter_lock();
-}
-
-/**
- * @brief   Guard code for @p chSysUnlock().
- *
- * @notapi
- */
-void dbg_check_unlock(void) {
-
-  if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0))
-    chDbgPanic("SV#5");
-  dbg_leave_lock();
-}
-
-/**
- * @brief   Guard code for @p chSysLockFromIsr().
- *
- * @notapi
- */
-void dbg_check_lock_from_isr(void) {
-
-  if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0))
-    chDbgPanic("SV#6");
-  dbg_enter_lock();
-}
-
-/**
- * @brief   Guard code for @p chSysUnlockFromIsr().
- *
- * @notapi
- */
-void dbg_check_unlock_from_isr(void) {
-
-  if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt <= 0))
-    chDbgPanic("SV#7");
-  dbg_leave_lock();
-}
-
-/**
- * @brief   Guard code for @p CH_IRQ_PROLOGUE().
- *
- * @notapi
- */
-void dbg_check_enter_isr(void) {
-
-  port_lock_from_isr();
-  if ((dbg_isr_cnt < 0) || (dbg_lock_cnt != 0))
-    chDbgPanic("SV#8");
-  dbg_isr_cnt++;
-  port_unlock_from_isr();
-}
-
-/**
- * @brief   Guard code for @p CH_IRQ_EPILOGUE().
- *
- * @notapi
- */
-void dbg_check_leave_isr(void) {
-
-  port_lock_from_isr();
-  if ((dbg_isr_cnt <= 0) || (dbg_lock_cnt != 0))
-    chDbgPanic("SV#9");
-  dbg_isr_cnt--;
-  port_unlock_from_isr();
-}
-
-/**
- * @brief   I-class functions context check.
- * @details Verifies that the system is in an appropriate state for invoking
- *          an I-class API function. A panic is generated if the state is
- *          not compatible.
- *
- * @api
- */
-void chDbgCheckClassI(void) {
-
-  if ((dbg_isr_cnt < 0) || (dbg_lock_cnt <= 0))
-    chDbgPanic("SV#10");
-}
-
-/**
- * @brief   S-class functions context check.
- * @details Verifies that the system is in an appropriate state for invoking
- *          an S-class API function. A panic is generated if the state is
- *          not compatible.
- *
- * @api
- */
-void chDbgCheckClassS(void) {
-
-  if ((dbg_isr_cnt != 0) || (dbg_lock_cnt <= 0))
-    chDbgPanic("SV#11");
-}
-
-#endif /* CH_DBG_SYSTEM_STATE_CHECK */
-
-/*===========================================================================*/
-/* Trace related code and variables.                                         */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
-/**
- * @brief   Public trace buffer.
- */
-ch_trace_buffer_t dbg_trace_buffer;
-
-/**
- * @brief   Trace circular buffer subsystem initialization.
- * @note    Internal use only.
- */
-void _trace_init(void) {
-
-  dbg_trace_buffer.tb_size = CH_TRACE_BUFFER_SIZE;
-  dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0];
-}
-
-/**
- * @brief   Inserts in the circular debug trace buffer a context switch record.
- *
- * @param[in] otp       the thread being switched out
- *
- * @notapi
- */
-void dbg_trace(Thread *otp) {
-
-  dbg_trace_buffer.tb_ptr->se_time   = chTimeNow();
-  dbg_trace_buffer.tb_ptr->se_tp     = currp;
-  dbg_trace_buffer.tb_ptr->se_wtobjp = otp->p_u.wtobjp;
-  dbg_trace_buffer.tb_ptr->se_state  = (uint8_t)otp->p_state;
-  if (++dbg_trace_buffer.tb_ptr >=
-      &dbg_trace_buffer.tb_buffer[CH_TRACE_BUFFER_SIZE])
-    dbg_trace_buffer.tb_ptr = &dbg_trace_buffer.tb_buffer[0];
-}
-#endif /* CH_DBG_ENABLE_TRACE */
-
-/*===========================================================================*/
-/* Panic related code and variables.                                         */
-/*===========================================================================*/
-
-#if CH_DBG_ENABLED || defined(__DOXYGEN__)
-/**
- * @brief   Pointer to the panic message.
- * @details This pointer is meant to be accessed through the debugger, it is
- *          written once and then the system is halted.
- */
-const char *dbg_panic_msg;
-
-/**
- * @brief   Prints a panic message on the console and then halts the system.
- *
- * @param[in] msg       the pointer to the panic message string
- */
-void chDbgPanic(const char *msg) {
-
-  dbg_panic_msg = msg;
-  chSysHalt();
-}
-#endif /* CH_DBG_ENABLED */
-
-/** @} */
diff --git a/os/kernel/src/chdynamic.c b/os/kernel/src/chdynamic.c
deleted file mode 100644
index 632367ca1..000000000
--- a/os/kernel/src/chdynamic.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chdynamic.c
- * @brief   Dynamic threads code.
- *
- * @addtogroup dynamic_threads
- * @details Dynamic threads related APIs and services.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_DYNAMIC || defined(__DOXYGEN__)
-
-/**
- * @brief   Adds a reference to a thread object.
- * @pre     The configuration option @p CH_USE_DYNAMIC must be enabled in order
- *          to use this function.
- *
- * @param[in] tp        pointer to the thread
- * @return              The same thread pointer passed as parameter
- *                      representing the new reference.
- *
- * @api
- */
-Thread *chThdAddRef(Thread *tp) {
-
-  chSysLock();
-  chDbgAssert(tp->p_refs < 255, "chThdAddRef(), #1", "too many references");
-  tp->p_refs++;
-  chSysUnlock();
-  return tp;
-}
-
-/**
- * @brief   Releases a reference to a thread object.
- * @details If the references counter reaches zero <b>and</b> the thread
- *          is in the @p THD_STATE_FINAL state then the thread's memory is
- *          returned to the proper allocator.
- * @pre     The configuration option @p CH_USE_DYNAMIC must be enabled in order
- *          to use this function.
- * @note    Static threads are not affected.
- *
- * @param[in] tp        pointer to the thread
- *
- * @api
- */
-void chThdRelease(Thread *tp) {
-  trefs_t refs;
-
-  chSysLock();
-  chDbgAssert(tp->p_refs > 0, "chThdRelease(), #1", "not referenced");
-  refs = --tp->p_refs;
-  chSysUnlock();
-
-  /* If the references counter reaches zero and the thread is in its
-     terminated state then the memory can be returned to the proper
-     allocator. Of course static threads are not affected.*/
-  if ((refs == 0) && (tp->p_state == THD_STATE_FINAL)) {
-    switch (tp->p_flags & THD_MEM_MODE_MASK) {
-#if CH_USE_HEAP
-    case THD_MEM_MODE_HEAP:
-#if CH_USE_REGISTRY
-      REG_REMOVE(tp);
-#endif
-      chHeapFree(tp);
-      break;
-#endif
-#if CH_USE_MEMPOOLS
-    case THD_MEM_MODE_MEMPOOL:
-#if CH_USE_REGISTRY
-      REG_REMOVE(tp);
-#endif
-      chPoolFree(tp->p_mpool, tp);
-      break;
-#endif
-    }
-  }
-}
-
-#if CH_USE_HEAP || defined(__DOXYGEN__)
-/**
- * @brief   Creates a new thread allocating the memory from the heap.
- * @pre     The configuration options @p CH_USE_DYNAMIC and @p CH_USE_HEAP
- *          must be enabled in order to use this function.
- * @note    A thread can terminate by calling @p chThdExit() or by simply
- *          returning from its main function.
- * @note    The memory allocated for the thread is not released when the thread
- *          terminates but when a @p chThdWait() is performed.
- *
- * @param[in] heapp     heap from which allocate the memory or @p NULL for the
- *                      default heap
- * @param[in] size      size of the working area to be allocated
- * @param[in] prio      the priority level for the new thread
- * @param[in] pf        the thread function
- * @param[in] arg       an argument passed to the thread function. It can be
- *                      @p NULL.
- * @return              The pointer to the @p Thread structure allocated for
- *                      the thread into the working space area.
- * @retval NULL         if the memory cannot be allocated.
- *
- * @api
- */
-Thread *chThdCreateFromHeap(MemoryHeap *heapp, size_t size,
-                            tprio_t prio, tfunc_t pf, void *arg) {
-  void *wsp;
-  Thread *tp;
-
-  wsp = chHeapAlloc(heapp, size);
-  if (wsp == NULL)
-    return NULL;
-  
-#if CH_DBG_FILL_THREADS
-  _thread_memfill((uint8_t *)wsp,
-                  (uint8_t *)wsp + sizeof(Thread),
-                  CH_THREAD_FILL_VALUE);
-  _thread_memfill((uint8_t *)wsp + sizeof(Thread),
-                  (uint8_t *)wsp + size,
-                  CH_STACK_FILL_VALUE);
-#endif
-  
-  chSysLock();
-  tp = chThdCreateI(wsp, size, prio, pf, arg);
-  tp->p_flags = THD_MEM_MODE_HEAP;
-  chSchWakeupS(tp, RDY_OK);
-  chSysUnlock();
-  return tp;
-}
-#endif /* CH_USE_HEAP */
-
-#if CH_USE_MEMPOOLS || defined(__DOXYGEN__)
-/**
- * @brief   Creates a new thread allocating the memory from the specified
- *          memory pool.
- * @pre     The configuration options @p CH_USE_DYNAMIC and @p CH_USE_MEMPOOLS
- *          must be enabled in order to use this function.
- * @note    A thread can terminate by calling @p chThdExit() or by simply
- *          returning from its main function.
- * @note    The memory allocated for the thread is not released when the thread
- *          terminates but when a @p chThdWait() is performed.
- *
- * @param[in] mp        pointer to the memory pool object
- * @param[in] prio      the priority level for the new thread
- * @param[in] pf        the thread function
- * @param[in] arg       an argument passed to the thread function. It can be
- *                      @p NULL.
- * @return              The pointer to the @p Thread structure allocated for
- *                      the thread into the working space area.
- * @retval  NULL        if the memory pool is empty.
- *
- * @api
- */
-Thread *chThdCreateFromMemoryPool(MemoryPool *mp, tprio_t prio,
-                                  tfunc_t pf, void *arg) {
-  void *wsp;
-  Thread *tp;
-
-  chDbgCheck(mp != NULL, "chThdCreateFromMemoryPool");
-
-  wsp = chPoolAlloc(mp);
-  if (wsp == NULL)
-    return NULL;
-  
-#if CH_DBG_FILL_THREADS
-  _thread_memfill((uint8_t *)wsp,
-                  (uint8_t *)wsp + sizeof(Thread),
-                  CH_THREAD_FILL_VALUE);
-  _thread_memfill((uint8_t *)wsp + sizeof(Thread),
-                  (uint8_t *)wsp + mp->mp_object_size,
-                  CH_STACK_FILL_VALUE);
-#endif
-
-  chSysLock();
-  tp = chThdCreateI(wsp, mp->mp_object_size, prio, pf, arg);
-  tp->p_flags = THD_MEM_MODE_MEMPOOL;
-  tp->p_mpool = mp;
-  chSchWakeupS(tp, RDY_OK);
-  chSysUnlock();
-  return tp;
-}
-#endif /* CH_USE_MEMPOOLS */
-
-#endif /* CH_USE_DYNAMIC */
-
-/** @} */
diff --git a/os/kernel/src/chevents.c b/os/kernel/src/chevents.c
deleted file mode 100644
index c79c60e2b..000000000
--- a/os/kernel/src/chevents.c
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-/*
-   Concepts and parts of this file have been contributed by Scott (skute).
- */
-
-/**
- * @file    chevents.c
- * @brief   Events code.
- *
- * @addtogroup events
- * @details Event Flags, Event Sources and Event Listeners.
- *          <h2>Operation mode</h2>
- *          Each thread has a mask of pending event flags inside its @p Thread
- *          structure.
- *          Operations defined for event flags:
- *          - <b>Wait</b>, the invoking thread goes to sleep until a certain
- *            AND/OR combination of event flags becomes pending.
- *          - <b>Clear</b>, a mask of event flags is cleared from the pending
- *            events mask, the cleared event flags mask is returned (only the
- *            flags that were actually pending and then cleared).
- *          - <b>Signal</b>, an event mask is directly ORed to the mask of the
- *            signaled thread.
- *          - <b>Broadcast</b>, each thread registered on an Event Source is
- *            signaled with the event flags specified in its Event Listener.
- *          - <b>Dispatch</b>, an events mask is scanned and for each bit set
- *            to one an associated handler function is invoked. Bit masks are
- *            scanned from bit zero upward.
- *          .
- *          An Event Source is a special object that can be "broadcasted" by
- *          a thread or an interrupt service routine. Broadcasting an Event
- *          Source has the effect that all the threads registered on the
- *          Event Source will be signaled with an events mask.<br>
- *          An unlimited number of Event Sources can exists in a system and
- *          each thread can be listening on an unlimited number of
- *          them.
- * @pre     In order to use the Events APIs the @p CH_USE_EVENTS option must be
- *          enabled in @p chconf.h.
- * @post    Enabling events requires 1-4 (depending on the architecture)
- *          extra bytes in the @p Thread structure.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_EVENTS || defined(__DOXYGEN__)
-/**
- * @brief   Registers an Event Listener on an Event Source.
- * @details Once a thread has registered as listener on an event source it
- *          will be notified of all events broadcasted there.
- * @note    Multiple Event Listeners can specify the same bits to be ORed to
- *          different threads.
- *
- * @param[in] esp       pointer to the  @p EventSource structure
- * @param[out] elp      pointer to the @p EventListener structure
- * @param[in] mask      the mask of event flags to be ORed to the thread when
- *                      the event source is broadcasted
- *
- * @api
- */
-void chEvtRegisterMask(EventSource *esp, EventListener *elp, eventmask_t mask) {
-
-  chDbgCheck((esp != NULL) && (elp != NULL), "chEvtRegisterMask");
-
-  chSysLock();
-  elp->el_next     = esp->es_next;
-  esp->es_next     = elp;
-  elp->el_listener = currp;
-  elp->el_mask     = mask;
-  elp->el_flags    = 0;
-  chSysUnlock();
-}
-
-/**
- * @brief   Unregisters an Event Listener from its Event Source.
- * @note    If the event listener is not registered on the specified event
- *          source then the function does nothing.
- * @note    For optimal performance it is better to perform the unregister
- *          operations in inverse order of the register operations (elements
- *          are found on top of the list).
- *
- * @param[in] esp       pointer to the  @p EventSource structure
- * @param[in] elp       pointer to the @p EventListener structure
- *
- * @api
- */
-void chEvtUnregister(EventSource *esp, EventListener *elp) {
-  EventListener *p;
-
-  chDbgCheck((esp != NULL) && (elp != NULL), "chEvtUnregister");
-
-  p = (EventListener *)esp;
-  chSysLock();
-  while (p->el_next != (EventListener *)esp) {
-    if (p->el_next == elp) {
-      p->el_next = elp->el_next;
-      break;
-    }
-    p = p->el_next;
-  }
-  chSysUnlock();
-}
-
-/**
- * @brief   Clears the pending events specified in the mask.
- *
- * @param[in] mask      the events to be cleared
- * @return              The pending events that were cleared.
- *
- * @api
- */
-eventmask_t chEvtGetAndClearEvents(eventmask_t mask) {
-  eventmask_t m;
-
-  chSysLock();
-
-  m = currp->p_epending & mask;
-  currp->p_epending &= ~mask;
-
-  chSysUnlock();
-  return m;
-}
-
-/**
- * @brief   Adds (OR) a set of event flags on the current thread, this is
- *          @b much faster than using @p chEvtBroadcast() or @p chEvtSignal().
- *
- * @param[in] mask      the event flags to be added
- * @return              The current pending events mask.
- *
- * @api
- */
-eventmask_t chEvtAddEvents(eventmask_t mask) {
-
-  chSysLock();
-
-  mask = (currp->p_epending |= mask);
-
-  chSysUnlock();
-  return mask;
-}
-
-/**
- * @brief   Signals all the Event Listeners registered on the specified Event
- *          Source.
- * @details This function variants ORs the specified event flags to all the
- *          threads registered on the @p EventSource in addition to the event
- *          flags specified by the threads themselves in the
- *          @p EventListener objects.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel. Note that
- *          interrupt handlers always reschedule on exit so an explicit
- *          reschedule must not be performed in ISRs.
- *
- * @param[in] esp       pointer to the @p EventSource structure
- * @param[in] flags     the flags set to be added to the listener flags mask
- *
- * @iclass
- */
-void chEvtBroadcastFlagsI(EventSource *esp, flagsmask_t flags) {
-  EventListener *elp;
-
-  chDbgCheckClassI();
-  chDbgCheck(esp != NULL, "chEvtBroadcastMaskI");
-
-  elp = esp->es_next;
-  while (elp != (EventListener *)esp) {
-    elp->el_flags |= flags;
-    chEvtSignalI(elp->el_listener, elp->el_mask);
-    elp = elp->el_next;
-  }
-}
-
-/**
- * @brief   Returns the flags associated to an @p EventListener.
- * @details The flags are returned and the @p EventListener flags mask is
- *          cleared.
- *
- * @param[in] elp       pointer to the @p EventListener structure
- * @return              The flags added to the listener by the associated
- *                      event source.
- *
- * @api
- */
-flagsmask_t chEvtGetAndClearFlags(EventListener *elp) {
-  flagsmask_t flags;
-
-  chSysLock();
-
-  flags = elp->el_flags;
-  elp->el_flags = 0;
-
-  chSysUnlock();
-  return flags;
-}
-
-/**
- * @brief   Adds a set of event flags directly to specified @p Thread.
- *
- * @param[in] tp        the thread to be signaled
- * @param[in] mask      the event flags set to be ORed
- *
- * @api
- */
-void chEvtSignal(Thread *tp, eventmask_t mask) {
-
-  chDbgCheck(tp != NULL, "chEvtSignal");
-
-  chSysLock();
-  chEvtSignalI(tp, mask);
-  chSchRescheduleS();
-  chSysUnlock();
-}
-
-/**
- * @brief   Adds a set of event flags directly to specified @p Thread.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel. Note that
- *          interrupt handlers always reschedule on exit so an explicit
- *          reschedule must not be performed in ISRs.
- *
- * @param[in] tp        the thread to be signaled
- * @param[in] mask      the event flags set to be ORed
- *
- * @iclass
- */
-void chEvtSignalI(Thread *tp, eventmask_t mask) {
-
-  chDbgCheckClassI();
-  chDbgCheck(tp != NULL, "chEvtSignalI");
-
-  tp->p_epending |= mask;
-  /* Test on the AND/OR conditions wait states.*/
-  if (((tp->p_state == THD_STATE_WTOREVT) &&
-       ((tp->p_epending & tp->p_u.ewmask) != 0)) ||
-      ((tp->p_state == THD_STATE_WTANDEVT) &&
-       ((tp->p_epending & tp->p_u.ewmask) == tp->p_u.ewmask)))
-    chSchReadyI(tp)->p_u.rdymsg = RDY_OK;
-}
-
-/**
- * @brief   Signals all the Event Listeners registered on the specified Event
- *          Source.
- * @details This function variants ORs the specified event flags to all the
- *          threads registered on the @p EventSource in addition to the event
- *          flags specified by the threads themselves in the
- *          @p EventListener objects.
- *
- * @param[in] esp       pointer to the @p EventSource structure
- * @param[in] flags     the flags set to be added to the listener flags mask
- *
- * @api
- */
-void chEvtBroadcastFlags(EventSource *esp, flagsmask_t flags) {
-
-  chSysLock();
-  chEvtBroadcastFlagsI(esp, flags);
-  chSchRescheduleS();
-  chSysUnlock();
-}
-
-/**
- * @brief   Returns the flags associated to an @p EventListener.
- * @details The flags are returned and the @p EventListener flags mask is
- *          cleared.
- *
- * @param[in] elp       pointer to the @p EventListener structure
- * @return              The flags added to the listener by the associated
- *                      event source.
- *
- * @iclass
- */
-flagsmask_t chEvtGetAndClearFlagsI(EventListener *elp) {
-  flagsmask_t flags;
-
-  flags = elp->el_flags;
-  elp->el_flags = 0;
-
-  return flags;
-}
-
-/**
- * @brief   Invokes the event handlers associated to an event flags mask.
- *
- * @param[in] mask      mask of the event flags to be dispatched
- * @param[in] handlers  an array of @p evhandler_t. The array must have size
- *                      equal to the number of bits in eventmask_t.
- *
- * @api
- */
-void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask) {
-  eventid_t eid;
-
-  chDbgCheck(handlers != NULL, "chEvtDispatch");
-
-  eid = 0;
-  while (mask) {
-    if (mask & EVENT_MASK(eid)) {
-      chDbgAssert(handlers[eid] != NULL,
-                  "chEvtDispatch(), #1",
-                  "null handler");
-      mask &= ~EVENT_MASK(eid);
-      handlers[eid](eid);
-    }
-    eid++;
-  }
-}
-
-#if CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__)
-/**
- * @brief   Waits for exactly one of the specified events.
- * @details The function waits for one event among those specified in
- *          @p mask to become pending then the event is cleared and returned.
- * @note    One and only one event is served in the function, the one with the
- *          lowest event id. The function is meant to be invoked into a loop in
- *          order to serve all the pending events.<br>
- *          This means that Event Listeners with a lower event identifier have
- *          an higher priority.
- *
- * @param[in] mask      mask of the event flags that the function should wait
- *                      for, @p ALL_EVENTS enables all the events
- * @return              The mask of the lowest id served and cleared event.
- *
- * @api
- */
-eventmask_t chEvtWaitOne(eventmask_t mask) {
-  Thread *ctp = currp;
-  eventmask_t m;
-
-  chSysLock();
-
-  if ((m = (ctp->p_epending & mask)) == 0) {
-    ctp->p_u.ewmask = mask;
-    chSchGoSleepS(THD_STATE_WTOREVT);
-    m = ctp->p_epending & mask;
-  }
-  m &= -m;
-  ctp->p_epending &= ~m;
-
-  chSysUnlock();
-  return m;
-}
-
-/**
- * @brief   Waits for any of the specified events.
- * @details The function waits for any event among those specified in
- *          @p mask to become pending then the events are cleared and returned.
- *
- * @param[in] mask      mask of the event flags that the function should wait
- *                      for, @p ALL_EVENTS enables all the events
- * @return              The mask of the served and cleared events.
- *
- * @api
- */
-eventmask_t chEvtWaitAny(eventmask_t mask) {
-  Thread *ctp = currp;
-  eventmask_t m;
-
-  chSysLock();
-
-  if ((m = (ctp->p_epending & mask)) == 0) {
-    ctp->p_u.ewmask = mask;
-    chSchGoSleepS(THD_STATE_WTOREVT);
-    m = ctp->p_epending & mask;
-  }
-  ctp->p_epending &= ~m;
-
-  chSysUnlock();
-  return m;
-}
-
-/**
- * @brief   Waits for all the specified events.
- * @details The function waits for all the events specified in @p mask to
- *          become pending then the events are cleared and returned.
- *
- * @param[in] mask      mask of the event flags that the function should wait
- *                      for, @p ALL_EVENTS requires all the events
- * @return              The mask of the served and cleared events.
- *
- * @api
- */
-eventmask_t chEvtWaitAll(eventmask_t mask) {
-  Thread *ctp = currp;
-
-  chSysLock();
-
-  if ((ctp->p_epending & mask) != mask) {
-    ctp->p_u.ewmask = mask;
-    chSchGoSleepS(THD_STATE_WTANDEVT);
-  }
-  ctp->p_epending &= ~mask;
-
-  chSysUnlock();
-  return mask;
-}
-#endif /* CH_OPTIMIZE_SPEED || !CH_USE_EVENTS_TIMEOUT */
-
-#if CH_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__)
-/**
- * @brief   Waits for exactly one of the specified events.
- * @details The function waits for one event among those specified in
- *          @p mask to become pending then the event is cleared and returned.
- * @note    One and only one event is served in the function, the one with the
- *          lowest event id. The function is meant to be invoked into a loop in
- *          order to serve all the pending events.<br>
- *          This means that Event Listeners with a lower event identifier have
- *          an higher priority.
- *
- * @param[in] mask      mask of the event flags that the function should wait
- *                      for, @p ALL_EVENTS enables all the events
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The mask of the lowest id served and cleared event.
- * @retval 0            if the operation has timed out.
- *
- * @api
- */
-eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time) {
-  Thread *ctp = currp;
-  eventmask_t m;
-
-  chSysLock();
-
-  if ((m = (ctp->p_epending & mask)) == 0) {
-    if (TIME_IMMEDIATE == time) {
-      chSysUnlock();
-      return (eventmask_t)0;
-    }
-    ctp->p_u.ewmask = mask;
-    if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) {
-      chSysUnlock();
-      return (eventmask_t)0;
-    }
-    m = ctp->p_epending & mask;
-  }
-  m &= -m;
-  ctp->p_epending &= ~m;
-
-  chSysUnlock();
-  return m;
-}
-
-/**
- * @brief   Waits for any of the specified events.
- * @details The function waits for any event among those specified in
- *          @p mask to become pending then the events are cleared and
- *          returned.
- *
- * @param[in] mask      mask of the event flags that the function should wait
- *                      for, @p ALL_EVENTS enables all the events
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The mask of the served and cleared events.
- * @retval 0            if the operation has timed out.
- *
- * @api
- */
-eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time) {
-  Thread *ctp = currp;
-  eventmask_t m;
-
-  chSysLock();
-
-  if ((m = (ctp->p_epending & mask)) == 0) {
-    if (TIME_IMMEDIATE == time) {
-      chSysUnlock();
-      return (eventmask_t)0;
-    }
-    ctp->p_u.ewmask = mask;
-    if (chSchGoSleepTimeoutS(THD_STATE_WTOREVT, time) < RDY_OK) {
-      chSysUnlock();
-      return (eventmask_t)0;
-    }
-    m = ctp->p_epending & mask;
-  }
-  ctp->p_epending &= ~m;
-
-  chSysUnlock();
-  return m;
-}
-
-/**
- * @brief   Waits for all the specified events.
- * @details The function waits for all the events specified in @p mask to
- *          become pending then the events are cleared and returned.
- *
- * @param[in] mask      mask of the event flags that the function should wait
- *                      for, @p ALL_EVENTS requires all the events
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The mask of the served and cleared events.
- * @retval 0            if the operation has timed out.
- *
- * @api
- */
-eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time) {
-  Thread *ctp = currp;
-
-  chSysLock();
-
-  if ((ctp->p_epending & mask) != mask) {
-    if (TIME_IMMEDIATE == time) {
-      chSysUnlock();
-      return (eventmask_t)0;
-    }
-    ctp->p_u.ewmask = mask;
-    if (chSchGoSleepTimeoutS(THD_STATE_WTANDEVT, time) < RDY_OK) {
-      chSysUnlock();
-      return (eventmask_t)0;
-    }
-  }
-  ctp->p_epending &= ~mask;
-
-  chSysUnlock();
-  return mask;
-}
-#endif /* CH_USE_EVENTS_TIMEOUT */
-
-#endif /* CH_USE_EVENTS */
-
-/** @} */
diff --git a/os/kernel/src/chheap.c b/os/kernel/src/chheap.c
deleted file mode 100644
index 23bcff6b4..000000000
--- a/os/kernel/src/chheap.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chheap.c
- * @brief   Heaps code.
- *
- * @addtogroup heaps
- * @details Heap Allocator related APIs.
- *          <h2>Operation mode</h2>
- *          The heap allocator implements a first-fit strategy and its APIs
- *          are functionally equivalent to the usual @p malloc() and @p free()
- *          library functions. The main difference is that the OS heap APIs
- *          are guaranteed to be thread safe.<br>
- *          By enabling the @p CH_USE_MALLOC_HEAP option the heap manager
- *          will use the runtime-provided @p malloc() and @p free() as
- *          back end for the heap APIs instead of the system provided
- *          allocator.
- * @pre     In order to use the heap APIs the @p CH_USE_HEAP option must
- *          be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_HEAP || defined(__DOXYGEN__)
-
-#if !CH_USE_MALLOC_HEAP || defined(__DOXYGEN__)
-
-/*
- * Defaults on the best synchronization mechanism available.
- */
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-#define H_LOCK(h)       chMtxLock(&(h)->h_mtx)
-#define H_UNLOCK(h)     chMtxUnlock()
-#else
-#define H_LOCK(h)       chSemWait(&(h)->h_sem)
-#define H_UNLOCK(h)     chSemSignal(&(h)->h_sem)
-#endif
-
-/**
- * @brief   Default heap descriptor.
- */
-static MemoryHeap default_heap;
-
-/**
- * @brief   Initializes the default heap.
- *
- * @notapi
- */
-void _heap_init(void) {
-  default_heap.h_provider = chCoreAlloc;
-  default_heap.h_free.h.u.next = (union heap_header *)NULL;
-  default_heap.h_free.h.size = 0;
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  chMtxInit(&default_heap.h_mtx);
-#else
-  chSemInit(&default_heap.h_sem, 1);
-#endif
-}
-
-/**
- * @brief   Initializes a memory heap from a static memory area.
- * @pre     Both the heap buffer base and the heap size must be aligned to
- *          the @p stkalign_t type size.
- * @pre     In order to use this function the option @p CH_USE_MALLOC_HEAP
- *          must be disabled.
- *
- * @param[out] heapp    pointer to the memory heap descriptor to be initialized
- * @param[in] buf       heap buffer base
- * @param[in] size      heap size
- *
- * @init
- */
-void chHeapInit(MemoryHeap *heapp, void *buf, size_t size) {
-  union heap_header *hp;
-
-  chDbgCheck(MEM_IS_ALIGNED(buf) && MEM_IS_ALIGNED(size), "chHeapInit");
-
-  heapp->h_provider = (memgetfunc_t)NULL;
-  heapp->h_free.h.u.next = hp = buf;
-  heapp->h_free.h.size = 0;
-  hp->h.u.next = NULL;
-  hp->h.size = size - sizeof(union heap_header);
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-  chMtxInit(&heapp->h_mtx);
-#else
-  chSemInit(&heapp->h_sem, 1);
-#endif
-}
-
-/**
- * @brief   Allocates a block of memory from the heap by using the first-fit
- *          algorithm.
- * @details The allocated block is guaranteed to be properly aligned for a
- *          pointer data type (@p stkalign_t).
- *
- * @param[in] heapp     pointer to a heap descriptor or @p NULL in order to
- *                      access the default heap.
- * @param[in] size      the size of the block to be allocated. Note that the
- *                      allocated block may be a bit bigger than the requested
- *                      size for alignment and fragmentation reasons.
- * @return              A pointer to the allocated block.
- * @retval NULL         if the block cannot be allocated.
- *
- * @api
- */
-void *chHeapAlloc(MemoryHeap *heapp, size_t size) {
-  union heap_header *qp, *hp, *fp;
-
-  if (heapp == NULL)
-    heapp = &default_heap;
-
-  size = MEM_ALIGN_NEXT(size);
-  qp = &heapp->h_free;
-  H_LOCK(heapp);
-
-  while (qp->h.u.next != NULL) {
-    hp = qp->h.u.next;
-    if (hp->h.size >= size) {
-      if (hp->h.size < size + sizeof(union heap_header)) {
-        /* Gets the whole block even if it is slightly bigger than the
-           requested size because the fragment would be too small to be
-           useful.*/
-        qp->h.u.next = hp->h.u.next;
-      }
-      else {
-        /* Block bigger enough, must split it.*/
-        fp = (void *)((uint8_t *)(hp) + sizeof(union heap_header) + size);
-        fp->h.u.next = hp->h.u.next;
-        fp->h.size = hp->h.size - sizeof(union heap_header) - size;
-        qp->h.u.next = fp;
-        hp->h.size = size;
-      }
-      hp->h.u.heap = heapp;
-
-      H_UNLOCK(heapp);
-      return (void *)(hp + 1);
-    }
-    qp = hp;
-  }
-
-  H_UNLOCK(heapp);
-
-  /* More memory is required, tries to get it from the associated provider
-     else fails.*/
-  if (heapp->h_provider) {
-    hp = heapp->h_provider(size + sizeof(union heap_header));
-    if (hp != NULL) {
-      hp->h.u.heap = heapp;
-      hp->h.size = size;
-      hp++;
-      return (void *)hp;
-    }
-  }
-  return NULL;
-}
-
-#define LIMIT(p) (union heap_header *)((uint8_t *)(p) + \
-                                        sizeof(union heap_header) + \
-                                        (p)->h.size)
-
-/**
- * @brief   Frees a previously allocated memory block.
- *
- * @param[in] p         pointer to the memory block to be freed
- *
- * @api
- */
-void chHeapFree(void *p) {
-  union heap_header *qp, *hp;
-  MemoryHeap *heapp;
-
-  chDbgCheck(p != NULL, "chHeapFree");
-
-  hp = (union heap_header *)p - 1;
-  heapp = hp->h.u.heap;
-  qp = &heapp->h_free;
-  H_LOCK(heapp);
-
-  while (TRUE) {
-    chDbgAssert((hp < qp) || (hp >= LIMIT(qp)),
-                "chHeapFree(), #1",
-                "within free block");
-
-    if (((qp == &heapp->h_free) || (hp > qp)) &&
-        ((qp->h.u.next == NULL) || (hp < qp->h.u.next))) {
-      /* Insertion after qp.*/
-      hp->h.u.next = qp->h.u.next;
-      qp->h.u.next = hp;
-      /* Verifies if the newly inserted block should be merged.*/
-      if (LIMIT(hp) == hp->h.u.next) {
-        /* Merge with the next block.*/
-        hp->h.size += hp->h.u.next->h.size + sizeof(union heap_header);
-        hp->h.u.next = hp->h.u.next->h.u.next;
-      }
-      if ((LIMIT(qp) == hp)) {
-        /* Merge with the previous block.*/
-        qp->h.size += hp->h.size + sizeof(union heap_header);
-        qp->h.u.next = hp->h.u.next;
-      }
-      break;
-    }
-    qp = qp->h.u.next;
-  }
-
-  H_UNLOCK(heapp);
-  return;
-}
-
-/**
- * @brief   Reports the heap status.
- * @note    This function is meant to be used in the test suite, it should
- *          not be really useful for the application code.
- * @note    This function is not implemented when the @p CH_USE_MALLOC_HEAP
- *          configuration option is used (it always returns zero).
- *
- * @param[in] heapp     pointer to a heap descriptor or @p NULL in order to
- *                      access the default heap.
- * @param[in] sizep     pointer to a variable that will receive the total
- *                      fragmented free space
- * @return              The number of fragments in the heap.
- *
- * @api
- */
-size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) {
-  union heap_header *qp;
-  size_t n, sz;
-
-  if (heapp == NULL)
-    heapp = &default_heap;
-
-  H_LOCK(heapp);
-
-  sz = 0;
-  for (n = 0, qp = &heapp->h_free; qp->h.u.next; n++, qp = qp->h.u.next)
-    sz += qp->h.u.next->h.size;
-  if (sizep)
-    *sizep = sz;
-
-  H_UNLOCK(heapp);
-  return n;
-}
-
-#else /* CH_USE_MALLOC_HEAP */
-
-#include <stdlib.h>
-
-#if CH_USE_MUTEXES
-#define H_LOCK()        chMtxLock(&hmtx)
-#define H_UNLOCK()      chMtxUnlock()
-static Mutex            hmtx;
-#elif CH_USE_SEMAPHORES
-#define H_LOCK()        chSemWait(&hsem)
-#define H_UNLOCK()      chSemSignal(&hsem)
-static Semaphore        hsem;
-#endif
-
-void _heap_init(void) {
-
-#if CH_USE_MUTEXES
-  chMtxInit(&hmtx);
-#else
-  chSemInit(&hsem, 1);
-#endif
-}
-
-void *chHeapAlloc(MemoryHeap *heapp, size_t size) {
-  void *p;
-
-  chDbgCheck(heapp == NULL, "chHeapAlloc");
-
-  H_LOCK();
-  p = malloc(size);
-  H_UNLOCK();
-  return p;
-}
-
-void chHeapFree(void *p) {
-
-  chDbgCheck(p != NULL, "chHeapFree");
-
-  H_LOCK();
-  free(p);
-  H_UNLOCK();
-}
-
-size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) {
-
-  chDbgCheck(heapp == NULL, "chHeapStatus");
-
-  if (sizep)
-    *sizep = 0;
-  return 0;
-}
-
-#endif /* CH_USE_MALLOC_HEAP */
-
-#endif /* CH_USE_HEAP */
-
-/** @} */
diff --git a/os/kernel/src/chlists.c b/os/kernel/src/chlists.c
deleted file mode 100644
index 8ee309200..000000000
--- a/os/kernel/src/chlists.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chlists.c
- * @brief   Thread queues/lists code.
- *
- * @addtogroup internals
- * @details All the functions present in this module, while public, are not
- *          OS APIs and should not be directly used in the user applications
- *          code.
- * @{
- */
-#include "ch.h"
-
-#if !CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
-/**
- * @brief   Inserts a thread into a priority ordered queue.
- * @note    The insertion is done by scanning the list from the highest
- *          priority toward the lowest.
- *
- * @param[in] tp        the pointer to the thread to be inserted in the list
- * @param[in] tqp       the pointer to the threads list header
- *
- * @notapi
- */
-void prio_insert(Thread *tp, ThreadsQueue *tqp) {
-
-  /* cp iterates over the queue.*/
-  Thread *cp = (Thread *)tqp;
-  do {
-    /* Iterate to next thread in queue.*/
-    cp = cp->p_next;
-    /* Not end of queue? and cp has equal or higher priority than tp?.*/
-  } while ((cp != (Thread *)tqp) && (cp->p_prio >= tp->p_prio));
-  /* Insertion on p_prev.*/
-  tp->p_next = cp;
-  tp->p_prev = cp->p_prev;
-  tp->p_prev->p_next = cp->p_prev = tp;
-}
-
-/**
- * @brief   Inserts a Thread into a queue.
- *
- * @param[in] tp        the pointer to the thread to be inserted in the list
- * @param[in] tqp       the pointer to the threads list header
- *
- * @notapi
- */
-void queue_insert(Thread *tp, ThreadsQueue *tqp) {
-
-  tp->p_next = (Thread *)tqp;
-  tp->p_prev = tqp->p_prev;
-  tp->p_prev->p_next = tqp->p_prev = tp;
-}
-
-/**
- * @brief   Removes the first-out Thread from a queue and returns it.
- * @note    If the queue is priority ordered then this function returns the
- *          thread with the highest priority.
- *
- * @param[in] tqp       the pointer to the threads list header
- * @return              The removed thread pointer.
- *
- * @notapi
- */
-Thread *fifo_remove(ThreadsQueue *tqp) {
-  Thread *tp = tqp->p_next;
-
-  (tqp->p_next = tp->p_next)->p_prev = (Thread *)tqp;
-  return tp;
-}
-
-/**
- * @brief   Removes the last-out Thread from a queue and returns it.
- * @note    If the queue is priority ordered then this function returns the
- *          thread with the lowest priority.
- *
- * @param[in] tqp   the pointer to the threads list header
- * @return          The removed thread pointer.
- *
- * @notapi
- */
-Thread *lifo_remove(ThreadsQueue *tqp) {
-  Thread *tp = tqp->p_prev;
-
-  (tqp->p_prev = tp->p_prev)->p_next = (Thread *)tqp;
-  return tp;
-}
-
-/**
- * @brief   Removes a Thread from a queue and returns it.
- * @details The thread is removed from the queue regardless of its relative
- *          position and regardless the used insertion method.
- *
- * @param[in] tp        the pointer to the thread to be removed from the queue
- * @return              The removed thread pointer.
- *
- * @notapi
- */
-Thread *dequeue(Thread *tp) {
-
-  tp->p_prev->p_next = tp->p_next;
-  tp->p_next->p_prev = tp->p_prev;
-  return tp;
-}
-
-/**
- * @brief   Pushes a Thread on top of a stack list.
- *
- * @param[in] tp    the pointer to the thread to be inserted in the list
- * @param[in] tlp   the pointer to the threads list header
- *
- * @notapi
- */
-void list_insert(Thread *tp, ThreadsList *tlp) {
-
-  tp->p_next = tlp->p_next;
-  tlp->p_next = tp;
-}
-
-/**
- * @brief   Pops a Thread from the top of a stack list and returns it.
- * @pre     The list must be non-empty before calling this function.
- *
- * @param[in] tlp       the pointer to the threads list header
- * @return              The removed thread pointer.
- *
- * @notapi
- */
-Thread *list_remove(ThreadsList *tlp) {
-
-  Thread *tp = tlp->p_next;
-  tlp->p_next = tp->p_next;
-  return tp;
-}
-#endif /* CH_OPTIMIZE_SPEED */
-
-/** @} */
diff --git a/os/kernel/src/chmboxes.c b/os/kernel/src/chmboxes.c
deleted file mode 100644
index 6f09a8d26..000000000
--- a/os/kernel/src/chmboxes.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmboxes.c
- * @brief   Mailboxes code.
- *
- * @addtogroup mailboxes
- * @details Asynchronous messages.
- *          <h2>Operation mode</h2>
- *          A mailbox is an asynchronous communication mechanism.<br>
- *          Operations defined for mailboxes:
- *          - <b>Post</b>: Posts a message on the mailbox in FIFO order.
- *          - <b>Post Ahead</b>: Posts a message on the mailbox with urgent
- *            priority.
- *          - <b>Fetch</b>: A message is fetched from the mailbox and removed
- *            from the queue.
- *          - <b>Reset</b>: The mailbox is emptied and all the stored messages
- *            are lost.
- *          .
- *          A message is a variable of type msg_t that is guaranteed to have
- *          the same size of and be compatible with (data) pointers (anyway an
- *          explicit cast is needed).
- *          If larger messages need to be exchanged then a pointer to a
- *          structure can be posted in the mailbox but the posting side has
- *          no predefined way to know when the message has been processed. A
- *          possible approach is to allocate memory (from a memory pool for
- *          example) from the posting side and free it on the fetching side.
- *          Another approach is to set a "done" flag into the structure pointed
- *          by the message.
- * @pre     In order to use the mailboxes APIs the @p CH_USE_MAILBOXES option
- *          must be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_MAILBOXES || defined(__DOXYGEN__)
-/**
- * @brief   Initializes a Mailbox object.
- *
- * @param[out] mbp      the pointer to the Mailbox structure to be initialized
- * @param[in] buf       pointer to the messages buffer as an array of @p msg_t
- * @param[in] n         number of elements in the buffer array
- *
- * @init
- */
-void chMBInit(Mailbox *mbp, msg_t *buf, cnt_t n) {
-
-  chDbgCheck((mbp != NULL) && (buf != NULL) && (n > 0), "chMBInit");
-
-  mbp->mb_buffer = mbp->mb_wrptr = mbp->mb_rdptr = buf;
-  mbp->mb_top = &buf[n];
-  chSemInit(&mbp->mb_emptysem, n);
-  chSemInit(&mbp->mb_fullsem, 0);
-}
-
-/**
- * @brief   Resets a Mailbox object.
- * @details All the waiting threads are resumed with status @p RDY_RESET and
- *          the queued messages are lost.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- *
- * @api
- */
-void chMBReset(Mailbox *mbp) {
-
-  chDbgCheck(mbp != NULL, "chMBReset");
-
-  chSysLock();
-  mbp->mb_wrptr = mbp->mb_rdptr = mbp->mb_buffer;
-  chSemResetI(&mbp->mb_emptysem, mbp->mb_top - mbp->mb_buffer);
-  chSemResetI(&mbp->mb_fullsem, 0);
-  chSchRescheduleS();
-  chSysUnlock();
-}
-
-/**
- * @brief   Posts a message into a mailbox.
- * @details The invoking thread waits until a empty slot in the mailbox becomes
- *          available or the specified time runs out.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @param[in] msg       the message to be posted on the mailbox
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if a message has been correctly posted.
- * @retval RDY_RESET    if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT  if the operation has timed out.
- *
- * @api
- */
-msg_t chMBPost(Mailbox *mbp, msg_t msg, systime_t time) {
-  msg_t rdymsg;
-
-  chSysLock();
-  rdymsg = chMBPostS(mbp, msg, time);
-  chSysUnlock();
-  return rdymsg;
-}
-
-/**
- * @brief   Posts a message into a mailbox.
- * @details The invoking thread waits until a empty slot in the mailbox becomes
- *          available or the specified time runs out.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @param[in] msg       the message to be posted on the mailbox
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if a message has been correctly posted.
- * @retval RDY_RESET    if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT  if the operation has timed out.
- *
- * @sclass
- */
-msg_t chMBPostS(Mailbox *mbp, msg_t msg, systime_t time) {
-  msg_t rdymsg;
-
-  chDbgCheckClassS();
-  chDbgCheck(mbp != NULL, "chMBPostS");
-
-  rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time);
-  if (rdymsg == RDY_OK) {
-    *mbp->mb_wrptr++ = msg;
-    if (mbp->mb_wrptr >= mbp->mb_top)
-      mbp->mb_wrptr = mbp->mb_buffer;
-    chSemSignalI(&mbp->mb_fullsem);
-    chSchRescheduleS();
-  }
-  return rdymsg;
-}
-
-/**
- * @brief   Posts a message into a mailbox.
- * @details This variant is non-blocking, the function returns a timeout
- *          condition if the queue is full.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @param[in] msg       the message to be posted on the mailbox
- * @return              The operation status.
- * @retval RDY_OK       if a message has been correctly posted.
- * @retval RDY_TIMEOUT  if the mailbox is full and the message cannot be
- *                      posted.
- *
- * @iclass
- */
-msg_t chMBPostI(Mailbox *mbp, msg_t msg) {
-
-  chDbgCheckClassI();
-  chDbgCheck(mbp != NULL, "chMBPostI");
-
-  if (chSemGetCounterI(&mbp->mb_emptysem) <= 0)
-    return RDY_TIMEOUT;
-  chSemFastWaitI(&mbp->mb_emptysem);
-  *mbp->mb_wrptr++ = msg;
-  if (mbp->mb_wrptr >= mbp->mb_top)
-    mbp->mb_wrptr = mbp->mb_buffer;
-  chSemSignalI(&mbp->mb_fullsem);
-  return RDY_OK;
-}
-
-/**
- * @brief   Posts an high priority message into a mailbox.
- * @details The invoking thread waits until a empty slot in the mailbox becomes
- *          available or the specified time runs out.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @param[in] msg       the message to be posted on the mailbox
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if a message has been correctly posted.
- * @retval RDY_RESET    if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT  if the operation has timed out.
- *
- * @api
- */
-msg_t chMBPostAhead(Mailbox *mbp, msg_t msg, systime_t time) {
-  msg_t rdymsg;
-
-  chSysLock();
-  rdymsg = chMBPostAheadS(mbp, msg, time);
-  chSysUnlock();
-  return rdymsg;
-}
-
-/**
- * @brief   Posts an high priority message into a mailbox.
- * @details The invoking thread waits until a empty slot in the mailbox becomes
- *          available or the specified time runs out.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @param[in] msg       the message to be posted on the mailbox
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if a message has been correctly posted.
- * @retval RDY_RESET    if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT  if the operation has timed out.
- *
- * @sclass
- */
-msg_t chMBPostAheadS(Mailbox *mbp, msg_t msg, systime_t time) {
-  msg_t rdymsg;
-
-  chDbgCheckClassS();
-  chDbgCheck(mbp != NULL, "chMBPostAheadS");
-
-  rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time);
-  if (rdymsg == RDY_OK) {
-    if (--mbp->mb_rdptr < mbp->mb_buffer)
-      mbp->mb_rdptr = mbp->mb_top - 1;
-    *mbp->mb_rdptr = msg;
-    chSemSignalI(&mbp->mb_fullsem);
-    chSchRescheduleS();
-  }
-  return rdymsg;
-}
-
-/**
- * @brief   Posts an high priority message into a mailbox.
- * @details This variant is non-blocking, the function returns a timeout
- *          condition if the queue is full.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @param[in] msg       the message to be posted on the mailbox
- * @return              The operation status.
- * @retval RDY_OK       if a message has been correctly posted.
- * @retval RDY_TIMEOUT  if the mailbox is full and the message cannot be
- *                      posted.
- *
- * @iclass
- */
-msg_t chMBPostAheadI(Mailbox *mbp, msg_t msg) {
-
-  chDbgCheckClassI();
-  chDbgCheck(mbp != NULL, "chMBPostAheadI");
-
-  if (chSemGetCounterI(&mbp->mb_emptysem) <= 0)
-    return RDY_TIMEOUT;
-  chSemFastWaitI(&mbp->mb_emptysem);
-  if (--mbp->mb_rdptr < mbp->mb_buffer)
-    mbp->mb_rdptr = mbp->mb_top - 1;
-  *mbp->mb_rdptr = msg;
-  chSemSignalI(&mbp->mb_fullsem);
-  return RDY_OK;
-}
-
-/**
- * @brief   Retrieves a message from a mailbox.
- * @details The invoking thread waits until a message is posted in the mailbox
- *          or the specified time runs out.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @param[out] msgp     pointer to a message variable for the received message
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if a message has been correctly fetched.
- * @retval RDY_RESET    if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT  if the operation has timed out.
- *
- * @api
- */
-msg_t chMBFetch(Mailbox *mbp, msg_t *msgp, systime_t time) {
-  msg_t rdymsg;
-
-  chSysLock();
-  rdymsg = chMBFetchS(mbp, msgp, time);
-  chSysUnlock();
-  return rdymsg;
-}
-
-/**
- * @brief   Retrieves a message from a mailbox.
- * @details The invoking thread waits until a message is posted in the mailbox
- *          or the specified time runs out.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @param[out] msgp     pointer to a message variable for the received message
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval RDY_OK       if a message has been correctly fetched.
- * @retval RDY_RESET    if the mailbox has been reset while waiting.
- * @retval RDY_TIMEOUT  if the operation has timed out.
- *
- * @sclass
- */
-msg_t chMBFetchS(Mailbox *mbp, msg_t *msgp, systime_t time) {
-  msg_t rdymsg;
-
-  chDbgCheckClassS();
-  chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchS");
-
-  rdymsg = chSemWaitTimeoutS(&mbp->mb_fullsem, time);
-  if (rdymsg == RDY_OK) {
-    *msgp = *mbp->mb_rdptr++;
-    if (mbp->mb_rdptr >= mbp->mb_top)
-      mbp->mb_rdptr = mbp->mb_buffer;
-    chSemSignalI(&mbp->mb_emptysem);
-    chSchRescheduleS();
-  }
-  return rdymsg;
-}
-
-/**
- * @brief   Retrieves a message from a mailbox.
- * @details This variant is non-blocking, the function returns a timeout
- *          condition if the queue is empty.
- *
- * @param[in] mbp       the pointer to an initialized Mailbox object
- * @param[out] msgp     pointer to a message variable for the received message
- * @return              The operation status.
- * @retval RDY_OK       if a message has been correctly fetched.
- * @retval RDY_TIMEOUT  if the mailbox is empty and a message cannot be
- *                      fetched.
- *
- * @iclass
- */
-msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp) {
-
-  chDbgCheckClassI();
-  chDbgCheck((mbp != NULL) && (msgp != NULL), "chMBFetchI");
-
-  if (chSemGetCounterI(&mbp->mb_fullsem) <= 0)
-    return RDY_TIMEOUT;
-  chSemFastWaitI(&mbp->mb_fullsem);
-  *msgp = *mbp->mb_rdptr++;
-  if (mbp->mb_rdptr >= mbp->mb_top)
-    mbp->mb_rdptr = mbp->mb_buffer;
-  chSemSignalI(&mbp->mb_emptysem);
-  return RDY_OK;
-}
-#endif /* CH_USE_MAILBOXES */
-
-/** @} */
diff --git a/os/kernel/src/chmemcore.c b/os/kernel/src/chmemcore.c
deleted file mode 100644
index 0ff26bc76..000000000
--- a/os/kernel/src/chmemcore.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmemcore.c
- * @brief   Core memory manager code.
- *
- * @addtogroup memcore
- * @details Core Memory Manager related APIs and services.
- *          <h2>Operation mode</h2>
- *          The core memory manager is a simplified allocator that only
- *          allows to allocate memory blocks without the possibility to
- *          free them.<br>
- *          This allocator is meant as a memory blocks provider for the
- *          other allocators such as:
- *          - C-Runtime allocator (through a compiler specific adapter module).
- *          - Heap allocator (see @ref heaps).
- *          - Memory pools allocator (see @ref pools).
- *          .
- *          By having a centralized memory provider the various allocators
- *          can coexist and share the main memory.<br>
- *          This allocator, alone, is also useful for very simple
- *          applications that just require a simple way to get memory
- *          blocks.
- * @pre     In order to use the core memory manager APIs the @p CH_USE_MEMCORE
- *          option must be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_MEMCORE || defined(__DOXYGEN__)
-
-static uint8_t *nextmem;
-static uint8_t *endmem;
-
-/**
- * @brief   Low level memory manager initialization.
- *
- * @notapi
- */
-void _core_init(void) {
-#if CH_MEMCORE_SIZE == 0
-  extern uint8_t __heap_base__[];
-  extern uint8_t __heap_end__[];
-  nextmem = (uint8_t *)MEM_ALIGN_NEXT(__heap_base__);
-  endmem = (uint8_t *)MEM_ALIGN_PREV(__heap_end__);
-#else
-  static stkalign_t buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE];
-  nextmem = (uint8_t *)&buffer[0];
-  endmem = (uint8_t *)&buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE];
-#endif
-}
-
-/**
- * @brief   Allocates a memory block.
- * @details The size of the returned block is aligned to the alignment
- *          type so it is not possible to allocate less
- *          than <code>MEM_ALIGN_SIZE</code>.
- *
- * @param[in] size      the size of the block to be allocated
- * @return              A pointer to the allocated memory block.
- * @retval NULL         allocation failed, core memory exhausted.
- *
- * @api
- */
-void *chCoreAlloc(size_t size) {
-  void *p;
-
-  chSysLock();
-  p = chCoreAllocI(size);
-  chSysUnlock();
-  return p;
-}
-
-/**
- * @brief   Allocates a memory block.
- * @details The size of the returned block is aligned to the alignment
- *          type so it is not possible to allocate less than
- *          <code>MEM_ALIGN_SIZE</code>.
- *
- * @param[in] size      the size of the block to be allocated.
- * @return              A pointer to the allocated memory block.
- * @retval NULL         allocation failed, core memory exhausted.
- *
- * @iclass
- */
-void *chCoreAllocI(size_t size) {
-  void *p;
-
-  chDbgCheckClassI();
-
-  size = MEM_ALIGN_NEXT(size);
-  if ((size_t)(endmem - nextmem) < size)
-    return NULL;
-  p = nextmem;
-  nextmem += size;
-  return p;
-}
-
-/**
- * @brief   Core memory status.
- *
- * @return              The size, in bytes, of the free core memory.
- *
- * @api
- */
-size_t chCoreStatus(void) {
-
-  return (size_t)(endmem - nextmem);
-}
-#endif /* CH_USE_MEMCORE */
-
-/** @} */
diff --git a/os/kernel/src/chmempools.c b/os/kernel/src/chmempools.c
deleted file mode 100644
index 44faa057a..000000000
--- a/os/kernel/src/chmempools.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmempools.c
- * @brief   Memory Pools code.
- *
- * @addtogroup pools
- * @details Memory Pools related APIs and services.
- *          <h2>Operation mode</h2>
- *          The Memory Pools APIs allow to allocate/free fixed size objects in
- *          <b>constant time</b> and reliably without memory fragmentation
- *          problems.<br>
- *          Memory Pools do not enforce any alignment constraint on the
- *          contained object however the objects must be properly aligned
- *          to contain a pointer to void.
- * @pre     In order to use the memory pools APIs the @p CH_USE_MEMPOOLS option
- *          must be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_MEMPOOLS || defined(__DOXYGEN__)
-/**
- * @brief   Initializes an empty memory pool.
- *
- * @param[out] mp       pointer to a @p MemoryPool structure
- * @param[in] size      the size of the objects contained in this memory pool,
- *                      the minimum accepted size is the size of a pointer to
- *                      void.
- * @param[in] provider  memory provider function for the memory pool or
- *                      @p NULL if the pool is not allowed to grow
- *                      automatically
- *
- * @init
- */
-void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider) {
-
-  chDbgCheck((mp != NULL) && (size >= sizeof(void *)), "chPoolInit");
-
-  mp->mp_next = NULL;
-  mp->mp_object_size = size;
-  mp->mp_provider = provider;
-}
-
-/**
- * @brief   Loads a memory pool with an array of static objects.
- * @pre     The memory pool must be already been initialized.
- * @pre     The array elements must be of the right size for the specified
- *          memory pool.
- * @post    The memory pool contains the elements of the input array.
- *
- * @param[in] mp        pointer to a @p MemoryPool structure
- * @param[in] p         pointer to the array first element
- * @param[in] n         number of elements in the array
- *
- * @api
- */
-void chPoolLoadArray(MemoryPool *mp, void *p, size_t n) {
-
-  chDbgCheck((mp != NULL) && (n != 0), "chPoolLoadArray");
-
-  while (n) {
-    chPoolAdd(mp, p);
-    p = (void *)(((uint8_t *)p) + mp->mp_object_size);
-    n--;
-  }
-}
-
-/**
- * @brief   Allocates an object from a memory pool.
- * @pre     The memory pool must be already been initialized.
- *
- * @param[in] mp        pointer to a @p MemoryPool structure
- * @return              The pointer to the allocated object.
- * @retval NULL         if pool is empty.
- *
- * @iclass
- */
-void *chPoolAllocI(MemoryPool *mp) {
-  void *objp;
-
-  chDbgCheckClassI();
-  chDbgCheck(mp != NULL, "chPoolAllocI");
-
-  if ((objp = mp->mp_next) != NULL)
-    mp->mp_next = mp->mp_next->ph_next;
-  else if (mp->mp_provider != NULL)
-    objp = mp->mp_provider(mp->mp_object_size);
-  return objp;
-}
-
-/**
- * @brief   Allocates an object from a memory pool.
- * @pre     The memory pool must be already been initialized.
- *
- * @param[in] mp        pointer to a @p MemoryPool structure
- * @return              The pointer to the allocated object.
- * @retval NULL         if pool is empty.
- *
- * @api
- */
-void *chPoolAlloc(MemoryPool *mp) {
-  void *objp;
-
-  chSysLock();
-  objp = chPoolAllocI(mp);
-  chSysUnlock();
-  return objp;
-}
-
-/**
- * @brief   Releases an object into a memory pool.
- * @pre     The memory pool must be already been initialized.
- * @pre     The freed object must be of the right size for the specified
- *          memory pool.
- * @pre     The object must be properly aligned to contain a pointer to void.
- *
- * @param[in] mp        pointer to a @p MemoryPool structure
- * @param[in] objp      the pointer to the object to be released
- *
- * @iclass
- */
-void chPoolFreeI(MemoryPool *mp, void *objp) {
-  struct pool_header *php = objp;
-
-  chDbgCheckClassI();
-  chDbgCheck((mp != NULL) && (objp != NULL), "chPoolFreeI");
-
-  php->ph_next = mp->mp_next;
-  mp->mp_next = php;
-}
-
-/**
- * @brief   Releases an object into a memory pool.
- * @pre     The memory pool must be already been initialized.
- * @pre     The freed object must be of the right size for the specified
- *          memory pool.
- * @pre     The object must be properly aligned to contain a pointer to void.
- *
- * @param[in] mp        pointer to a @p MemoryPool structure
- * @param[in] objp      the pointer to the object to be released
- *
- * @api
- */
-void chPoolFree(MemoryPool *mp, void *objp) {
-
-  chSysLock();
-  chPoolFreeI(mp, objp);
-  chSysUnlock();
-}
-
-#endif /* CH_USE_MEMPOOLS */
-
-/** @} */
diff --git a/os/kernel/src/chmsg.c b/os/kernel/src/chmsg.c
deleted file mode 100644
index ad97da79c..000000000
--- a/os/kernel/src/chmsg.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmsg.c
- * @brief   Messages code.
- *
- * @addtogroup messages
- * @details Synchronous inter-thread messages APIs and services.
- *          <h2>Operation Mode</h2>
- *          Synchronous messages are an easy to use and fast IPC mechanism,
- *          threads can both act as message servers and/or message clients,
- *          the mechanism allows data to be carried in both directions. Note
- *          that messages are not copied between the client and server threads
- *          but just a pointer passed so the exchange is very time
- *          efficient.<br>
- *          Messages are scalar data types of type @p msg_t that are guaranteed
- *          to be size compatible with data pointers. Note that on some
- *          architectures function pointers can be larger that @p msg_t.<br>
- *          Messages are usually processed in FIFO order but it is possible to
- *          process them in priority order by enabling the
- *          @p CH_USE_MESSAGES_PRIORITY option in @p chconf.h.<br>
- * @pre     In order to use the message APIs the @p CH_USE_MESSAGES option
- *          must be enabled in @p chconf.h.
- * @post    Enabling messages requires 6-12 (depending on the architecture)
- *          extra bytes in the @p Thread structure.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_MESSAGES || defined(__DOXYGEN__)
-
-#if CH_USE_MESSAGES_PRIORITY
-#define msg_insert(tp, qp) prio_insert(tp, qp)
-#else
-#define msg_insert(tp, qp) queue_insert(tp, qp)
-#endif
-
-/**
- * @brief   Sends a message to the specified thread.
- * @details The sender is stopped until the receiver executes a
- *          @p chMsgRelease()after receiving the message.
- *
- * @param[in] tp        the pointer to the thread
- * @param[in] msg       the message
- * @return              The answer message from @p chMsgRelease().
- *
- * @api
- */
-msg_t chMsgSend(Thread *tp, msg_t msg) {
-  Thread *ctp = currp;
-
-  chDbgCheck(tp != NULL, "chMsgSend");
-
-  chSysLock();
-  ctp->p_msg = msg;
-  ctp->p_u.wtobjp = &tp->p_msgqueue;
-  msg_insert(ctp, &tp->p_msgqueue);
-  if (tp->p_state == THD_STATE_WTMSG)
-    chSchReadyI(tp);
-  chSchGoSleepS(THD_STATE_SNDMSGQ);
-  msg = ctp->p_u.rdymsg;
-  chSysUnlock();
-  return msg;
-}
-
-/**
- * @brief   Suspends the thread and waits for an incoming message.
- * @post    After receiving a message the function @p chMsgGet() must be
- *          called in order to retrieve the message and then @p chMsgRelease()
- *          must be invoked in order to acknowledge the reception and send
- *          the answer.
- * @note    If the message is a pointer then you can assume that the data
- *          pointed by the message is stable until you invoke @p chMsgRelease()
- *          because the sending thread is suspended until then.
- *
- * @return              A reference to the thread carrying the message.
- *
- * @api
- */
-Thread *chMsgWait(void) {
-  Thread *tp;
-
-  chSysLock();
-  if (!chMsgIsPendingI(currp))
-    chSchGoSleepS(THD_STATE_WTMSG);
-  tp = fifo_remove(&currp->p_msgqueue);
-  tp->p_state = THD_STATE_SNDMSG;
-  chSysUnlock();
-  return tp;
-}
-
-/**
- * @brief   Releases a sender thread specifying a response message.
- * @pre     Invoke this function only after a message has been received
- *          using @p chMsgWait().
- *
- * @param[in] tp        pointer to the thread
- * @param[in] msg       message to be returned to the sender
- *
- * @api
- */
-void chMsgRelease(Thread *tp, msg_t msg) {
-
-  chSysLock();
-  chDbgAssert(tp->p_state == THD_STATE_SNDMSG,
-              "chMsgRelease(), #1", "invalid state");
-  chMsgReleaseS(tp, msg);
-  chSysUnlock();
-}
-
-#endif /* CH_USE_MESSAGES */
-
-/** @} */
diff --git a/os/kernel/src/chmtx.c b/os/kernel/src/chmtx.c
deleted file mode 100644
index 84d7e53a6..000000000
--- a/os/kernel/src/chmtx.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chmtx.c
- * @brief   Mutexes code.
- *
- * @addtogroup mutexes
- * @details Mutexes related APIs and services.
- *
- *          <h2>Operation mode</h2>
- *          A mutex is a threads synchronization object that can be in two
- *          distinct states:
- *          - Not owned (unlocked).
- *          - Owned by a thread (locked).
- *          .
- *          Operations defined for mutexes:
- *          - <b>Lock</b>: The mutex is checked, if the mutex is not owned by
- *            some other thread then it is associated to the locking thread
- *            else the thread is queued on the mutex in a list ordered by
- *            priority.
- *          - <b>Unlock</b>: The mutex is released by the owner and the highest
- *            priority thread waiting in the queue, if any, is resumed and made
- *            owner of the mutex.
- *          .
- *          <h2>Constraints</h2>
- *          In ChibiOS/RT the Unlock operations are always performed in
- *          lock-reverse order. The unlock API does not even have a parameter,
- *          the mutex to unlock is selected from an internal, per-thread, stack
- *          of owned mutexes. This both improves the performance and is
- *          required for an efficient implementation of the priority
- *          inheritance mechanism.
- *
- *          <h2>The priority inversion problem</h2>
- *          The mutexes in ChibiOS/RT implements the <b>full</b> priority
- *          inheritance mechanism in order handle the priority inversion
- *          problem.<br>
- *          When a thread is queued on a mutex, any thread, directly or
- *          indirectly, holding the mutex gains the same priority of the
- *          waiting thread (if their priority was not already equal or higher).
- *          The mechanism works with any number of nested mutexes and any
- *          number of involved threads. The algorithm complexity (worst case)
- *          is N with N equal to the number of nested mutexes.
- * @pre     In order to use the mutex APIs the @p CH_USE_MUTEXES option
- *          must be enabled in @p chconf.h.
- * @post    Enabling mutexes requires 5-12 (depending on the architecture)
- *          extra bytes in the @p Thread structure.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_MUTEXES || defined(__DOXYGEN__)
-
-/**
- * @brief   Initializes s @p Mutex structure.
- *
- * @param[out] mp       pointer to a @p Mutex structure
- *
- * @init
- */
-void chMtxInit(Mutex *mp) {
-
-  chDbgCheck(mp != NULL, "chMtxInit");
-
-  queue_init(&mp->m_queue);
-  mp->m_owner = NULL;
-}
-
-/**
- * @brief   Locks the specified mutex.
- * @post    The mutex is locked and inserted in the per-thread stack of owned
- *          mutexes.
- *
- * @param[in] mp        pointer to the @p Mutex structure
- *
- * @api
- */
-void chMtxLock(Mutex *mp) {
-
-  chSysLock();
-
-  chMtxLockS(mp);
-
-  chSysUnlock();
-}
-
-/**
- * @brief   Locks the specified mutex.
- * @post    The mutex is locked and inserted in the per-thread stack of owned
- *          mutexes.
- *
- * @param[in] mp        pointer to the @p Mutex structure
- *
- * @sclass
- */
-void chMtxLockS(Mutex *mp) {
-  Thread *ctp = currp;
-
-  chDbgCheckClassS();
-  chDbgCheck(mp != NULL, "chMtxLockS");
-
-  /* Is the mutex already locked? */
-  if (mp->m_owner != NULL) {
-    /* Priority inheritance protocol; explores the thread-mutex dependencies
-       boosting the priority of all the affected threads to equal the priority
-       of the running thread requesting the mutex.*/
-    Thread *tp = mp->m_owner;
-    /* Does the running thread have higher priority than the mutex
-       owning thread? */
-    while (tp->p_prio < ctp->p_prio) {
-      /* Make priority of thread tp match the running thread's priority.*/
-      tp->p_prio = ctp->p_prio;
-      /* The following states need priority queues reordering.*/
-      switch (tp->p_state) {
-      case THD_STATE_WTMTX:
-        /* Re-enqueues the mutex owner with its new priority.*/
-        prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp);
-        tp = ((Mutex *)tp->p_u.wtobjp)->m_owner;
-        continue;
-#if CH_USE_CONDVARS |                                                       \
-    (CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY) |                     \
-    (CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY)
-#if CH_USE_CONDVARS
-      case THD_STATE_WTCOND:
-#endif
-#if CH_USE_SEMAPHORES && CH_USE_SEMAPHORES_PRIORITY
-      case THD_STATE_WTSEM:
-#endif
-#if CH_USE_MESSAGES && CH_USE_MESSAGES_PRIORITY
-      case THD_STATE_SNDMSGQ:
-#endif
-        /* Re-enqueues tp with its new priority on the queue.*/
-        prio_insert(dequeue(tp), (ThreadsQueue *)tp->p_u.wtobjp);
-        break;
-#endif
-      case THD_STATE_READY:
-#if CH_DBG_ENABLE_ASSERTS
-        /* Prevents an assertion in chSchReadyI().*/
-        tp->p_state = THD_STATE_CURRENT;
-#endif
-        /* Re-enqueues tp with its new priority on the ready list.*/
-        chSchReadyI(dequeue(tp));
-        break;
-      }
-      break;
-    }
-    /* Sleep on the mutex.*/
-    prio_insert(ctp, &mp->m_queue);
-    ctp->p_u.wtobjp = mp;
-    chSchGoSleepS(THD_STATE_WTMTX);
-    /* It is assumed that the thread performing the unlock operation assigns
-       the mutex to this thread.*/
-    chDbgAssert(mp->m_owner == ctp, "chMtxLockS(), #1", "not owner");
-    chDbgAssert(ctp->p_mtxlist == mp, "chMtxLockS(), #2", "not owned");
-  }
-  else {
-    /* It was not owned, inserted in the owned mutexes list.*/
-    mp->m_owner = ctp;
-    mp->m_next = ctp->p_mtxlist;
-    ctp->p_mtxlist = mp;
-  }
-}
-
-/**
- * @brief   Tries to lock a mutex.
- * @details This function attempts to lock a mutex, if the mutex is already
- *          locked by another thread then the function exits without waiting.
- * @post    The mutex is locked and inserted in the per-thread stack of owned
- *          mutexes.
- * @note    This function does not have any overhead related to the
- *          priority inheritance mechanism because it does not try to
- *          enter a sleep state.
- *
- * @param[in] mp        pointer to the @p Mutex structure
- * @return              The operation status.
- * @retval TRUE         if the mutex has been successfully acquired
- * @retval FALSE        if the lock attempt failed.
- *
- * @api
- */
-bool_t chMtxTryLock(Mutex *mp) {
-  bool_t b;
-
-  chSysLock();
-
-  b = chMtxTryLockS(mp);
-
-  chSysUnlock();
-  return b;
-}
-
-/**
- * @brief   Tries to lock a mutex.
- * @details This function attempts to lock a mutex, if the mutex is already
- *          taken by another thread then the function exits without waiting.
- * @post    The mutex is locked and inserted in the per-thread stack of owned
- *          mutexes.
- * @note    This function does not have any overhead related to the
- *          priority inheritance mechanism because it does not try to
- *          enter a sleep state.
- *
- * @param[in] mp        pointer to the @p Mutex structure
- * @return              The operation status.
- * @retval TRUE         if the mutex has been successfully acquired
- * @retval FALSE        if the lock attempt failed.
- *
- * @sclass
- */
-bool_t chMtxTryLockS(Mutex *mp) {
-
-  chDbgCheckClassS();
-  chDbgCheck(mp != NULL, "chMtxTryLockS");
-
-  if (mp->m_owner != NULL)
-    return FALSE;
-  mp->m_owner = currp;
-  mp->m_next = currp->p_mtxlist;
-  currp->p_mtxlist = mp;
-  return TRUE;
-}
-
-/**
- * @brief   Unlocks the next owned mutex in reverse lock order.
- * @pre     The invoking thread <b>must</b> have at least one owned mutex.
- * @post    The mutex is unlocked and removed from the per-thread stack of
- *          owned mutexes.
- *
- * @return              A pointer to the unlocked mutex.
- *
- * @api
- */
-Mutex *chMtxUnlock(void) {
-  Thread *ctp = currp;
-  Mutex *ump, *mp;
-
-  chSysLock();
-  chDbgAssert(ctp->p_mtxlist != NULL,
-              "chMtxUnlock(), #1",
-              "owned mutexes list empty");
-  chDbgAssert(ctp->p_mtxlist->m_owner == ctp,
-              "chMtxUnlock(), #2",
-              "ownership failure");
-  /* Removes the top Mutex from the Thread's owned mutexes list and marks it
-     as not owned.*/
-  ump = ctp->p_mtxlist;
-  ctp->p_mtxlist = ump->m_next;
-  /* If a thread is waiting on the mutex then the fun part begins.*/
-  if (chMtxQueueNotEmptyS(ump)) {
-    Thread *tp;
-
-    /* Recalculates the optimal thread priority by scanning the owned
-       mutexes list.*/
-    tprio_t newprio = ctp->p_realprio;
-    mp = ctp->p_mtxlist;
-    while (mp != NULL) {
-      /* If the highest priority thread waiting in the mutexes list has a
-         greater priority than the current thread base priority then the final
-         priority will have at least that priority.*/
-      if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio))
-        newprio = mp->m_queue.p_next->p_prio;
-      mp = mp->m_next;
-    }
-    /* Assigns to the current thread the highest priority among all the
-       waiting threads.*/
-    ctp->p_prio = newprio;
-    /* Awakens the highest priority thread waiting for the unlocked mutex and
-       assigns the mutex to it.*/
-    tp = fifo_remove(&ump->m_queue);
-    ump->m_owner = tp;
-    ump->m_next = tp->p_mtxlist;
-    tp->p_mtxlist = ump;
-    chSchWakeupS(tp, RDY_OK);
-  }
-  else
-    ump->m_owner = NULL;
-  chSysUnlock();
-  return ump;
-}
-
-/**
- * @brief   Unlocks the next owned mutex in reverse lock order.
- * @pre     The invoking thread <b>must</b> have at least one owned mutex.
- * @post    The mutex is unlocked and removed from the per-thread stack of
- *          owned mutexes.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel.
- *
- * @return              A pointer to the unlocked mutex.
- *
- * @sclass
- */
-Mutex *chMtxUnlockS(void) {
-  Thread *ctp = currp;
-  Mutex *ump, *mp;
-
-  chDbgCheckClassS();
-  chDbgAssert(ctp->p_mtxlist != NULL,
-              "chMtxUnlockS(), #1",
-              "owned mutexes list empty");
-  chDbgAssert(ctp->p_mtxlist->m_owner == ctp,
-              "chMtxUnlockS(), #2",
-              "ownership failure");
-
-  /* Removes the top Mutex from the owned mutexes list and marks it as not
-     owned.*/
-  ump = ctp->p_mtxlist;
-  ctp->p_mtxlist = ump->m_next;
-  /* If a thread is waiting on the mutex then the fun part begins.*/
-  if (chMtxQueueNotEmptyS(ump)) {
-    Thread *tp;
-
-    /* Recalculates the optimal thread priority by scanning the owned
-       mutexes list.*/
-    tprio_t newprio = ctp->p_realprio;
-    mp = ctp->p_mtxlist;
-    while (mp != NULL) {
-      /* If the highest priority thread waiting in the mutexes list has a
-         greater priority than the current thread base priority then the final
-         priority will have at least that priority.*/
-      if (chMtxQueueNotEmptyS(mp) && (mp->m_queue.p_next->p_prio > newprio))
-        newprio = mp->m_queue.p_next->p_prio;
-      mp = mp->m_next;
-    }
-    ctp->p_prio = newprio;
-    /* Awakens the highest priority thread waiting for the unlocked mutex and
-       assigns the mutex to it.*/
-    tp = fifo_remove(&ump->m_queue);
-    ump->m_owner = tp;
-    ump->m_next = tp->p_mtxlist;
-    tp->p_mtxlist = ump;
-    chSchReadyI(tp);
-  }
-  else
-    ump->m_owner = NULL;
-  return ump;
-}
-
-/**
- * @brief   Unlocks all the mutexes owned by the invoking thread.
- * @post    The stack of owned mutexes is emptied and all the found
- *          mutexes are unlocked.
- * @note    This function is <b>MUCH MORE</b> efficient than releasing the
- *          mutexes one by one and not just because the call overhead,
- *          this function does not have any overhead related to the priority
- *          inheritance mechanism.
- *
- * @api
- */
-void chMtxUnlockAll(void) {
-  Thread *ctp = currp;
-
-  chSysLock();
-  if (ctp->p_mtxlist != NULL) {
-    do {
-      Mutex *ump = ctp->p_mtxlist;
-      ctp->p_mtxlist = ump->m_next;
-      if (chMtxQueueNotEmptyS(ump)) {
-        Thread *tp = fifo_remove(&ump->m_queue);
-        ump->m_owner = tp;
-        ump->m_next = tp->p_mtxlist;
-        tp->p_mtxlist = ump;
-        chSchReadyI(tp);
-      }
-      else
-        ump->m_owner = NULL;
-    } while (ctp->p_mtxlist != NULL);
-    ctp->p_prio = ctp->p_realprio;
-    chSchRescheduleS();
-  }
-  chSysUnlock();
-}
-
-#endif /* CH_USE_MUTEXES */
-
-/** @} */
diff --git a/os/kernel/src/chqueues.c b/os/kernel/src/chqueues.c
deleted file mode 100644
index 871e499a0..000000000
--- a/os/kernel/src/chqueues.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chqueues.c
- * @brief   I/O Queues code.
- *
- * @addtogroup io_queues
- * @details ChibiOS/RT queues are mostly used in serial-like device drivers.
- *          The device drivers are usually designed to have a lower side
- *          (lower driver, it is usually an interrupt service routine) and an
- *          upper side (upper driver, accessed by the application threads).<br>
- *          There are several kind of queues:<br>
- *          - <b>Input queue</b>, unidirectional queue where the writer is the
- *            lower side and the reader is the upper side.
- *          - <b>Output queue</b>, unidirectional queue where the writer is the
- *            upper side and the reader is the lower side.
- *          - <b>Full duplex queue</b>, bidirectional queue. Full duplex queues
- *            are implemented by pairing an input queue and an output queue
- *            together.
- *          .
- * @pre     In order to use the I/O queues the @p CH_USE_QUEUES option must
- *          be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_QUEUES || defined(__DOXYGEN__)
-
-/**
- * @brief   Puts the invoking thread into the queue's threads queue.
- *
- * @param[out] qp       pointer to an @p GenericQueue structure
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              A message specifying how the invoking thread has been
- *                      released from threads queue.
- * @retval Q_OK         is the normal exit, thread signaled.
- * @retval Q_RESET      if the queue has been reset.
- * @retval Q_TIMEOUT    if the queue operation timed out.
- */
-static msg_t qwait(GenericQueue *qp, systime_t time) {
-
-  if (TIME_IMMEDIATE == time)
-    return Q_TIMEOUT;
-  currp->p_u.wtobjp = qp;
-  queue_insert(currp, &qp->q_waiting);
-  return chSchGoSleepTimeoutS(THD_STATE_WTQUEUE, time);
-}
-
-/**
- * @brief   Initializes an input queue.
- * @details A Semaphore is internally initialized and works as a counter of
- *          the bytes contained in the queue.
- * @note    The callback is invoked from within the S-Locked system state,
- *          see @ref system_states.
- *
- * @param[out] iqp      pointer to an @p InputQueue structure
- * @param[in] bp        pointer to a memory area allocated as queue buffer
- * @param[in] size      size of the queue buffer
- * @param[in] infy      pointer to a callback function that is invoked when
- *                      data is read from the queue. The value can be @p NULL.
- * @param[in] link      application defined pointer
- *
- * @init
- */
-void chIQInit(InputQueue *iqp, uint8_t *bp, size_t size, qnotify_t infy,
-              void *link) {
-
-  queue_init(&iqp->q_waiting);
-  iqp->q_counter = 0;
-  iqp->q_buffer = iqp->q_rdptr = iqp->q_wrptr = bp;
-  iqp->q_top = bp + size;
-  iqp->q_notify = infy;
-  iqp->q_link = link;
-}
-
-/**
- * @brief   Resets an input queue.
- * @details All the data in the input queue is erased and lost, any waiting
- *          thread is resumed with status @p Q_RESET.
- * @note    A reset operation can be used by a low level driver in order to
- *          obtain immediate attention from the high level layers.
- *
- * @param[in] iqp       pointer to an @p InputQueue structure
- *
- * @iclass
- */
-void chIQResetI(InputQueue *iqp) {
-
-  chDbgCheckClassI();
-
-  iqp->q_rdptr = iqp->q_wrptr = iqp->q_buffer;
-  iqp->q_counter = 0;
-  while (notempty(&iqp->q_waiting))
-    chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_RESET;
-}
-
-/**
- * @brief   Input queue write.
- * @details A byte value is written into the low end of an input queue.
- *
- * @param[in] iqp       pointer to an @p InputQueue structure
- * @param[in] b         the byte value to be written in the queue
- * @return              The operation status.
- * @retval Q_OK         if the operation has been completed with success.
- * @retval Q_FULL       if the queue is full and the operation cannot be
- *                      completed.
- *
- * @iclass
- */
-msg_t chIQPutI(InputQueue *iqp, uint8_t b) {
-
-  chDbgCheckClassI();
-
-  if (chIQIsFullI(iqp))
-    return Q_FULL;
-
-  iqp->q_counter++;
-  *iqp->q_wrptr++ = b;
-  if (iqp->q_wrptr >= iqp->q_top)
-    iqp->q_wrptr = iqp->q_buffer;
-
-  if (notempty(&iqp->q_waiting))
-    chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK;
-
-  return Q_OK;
-}
-
-/**
- * @brief   Input queue read with timeout.
- * @details This function reads a byte value from an input queue. If the queue
- *          is empty then the calling thread is suspended until a byte arrives
- *          in the queue or a timeout occurs.
- * @note    The callback is invoked before reading the character from the
- *          buffer or before entering the state @p THD_STATE_WTQUEUE.
- *
- * @param[in] iqp       pointer to an @p InputQueue structure
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              A byte value from the queue.
- * @retval Q_TIMEOUT    if the specified time expired.
- * @retval Q_RESET      if the queue has been reset.
- *
- * @api
- */
-msg_t chIQGetTimeout(InputQueue *iqp, systime_t time) {
-  uint8_t b;
-
-  chSysLock();
-  if (iqp->q_notify)
-    iqp->q_notify(iqp);
-
-  while (chIQIsEmptyI(iqp)) {
-    msg_t msg;
-    if ((msg = qwait((GenericQueue *)iqp, time)) < Q_OK) {
-      chSysUnlock();
-      return msg;
-    }
-  }
-
-  iqp->q_counter--;
-  b = *iqp->q_rdptr++;
-  if (iqp->q_rdptr >= iqp->q_top)
-    iqp->q_rdptr = iqp->q_buffer;
-
-  chSysUnlock();
-  return b;
-}
-
-/**
- * @brief   Input queue read with timeout.
- * @details The function reads data from an input queue into a buffer. The
- *          operation completes when the specified amount of data has been
- *          transferred or after the specified timeout or if the queue has
- *          been reset.
- * @note    The function is not atomic, if you need atomicity it is suggested
- *          to use a semaphore or a mutex for mutual exclusion.
- * @note    The callback is invoked before reading each character from the
- *          buffer or before entering the state @p THD_STATE_WTQUEUE.
- *
- * @param[in] iqp       pointer to an @p InputQueue structure
- * @param[out] bp       pointer to the data buffer
- * @param[in] n         the maximum amount of data to be transferred, the
- *                      value 0 is reserved
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The number of bytes effectively transferred.
- *
- * @api
- */
-size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp,
-                       size_t n, systime_t time) {
-  qnotify_t nfy = iqp->q_notify;
-  size_t r = 0;
-
-  chDbgCheck(n > 0, "chIQReadTimeout");
-
-  chSysLock();
-  while (TRUE) {
-    if (nfy)
-      nfy(iqp);
-
-    while (chIQIsEmptyI(iqp)) {
-      if (qwait((GenericQueue *)iqp, time) != Q_OK) {
-        chSysUnlock();
-        return r;
-      }
-    }
-
-    iqp->q_counter--;
-    *bp++ = *iqp->q_rdptr++;
-    if (iqp->q_rdptr >= iqp->q_top)
-      iqp->q_rdptr = iqp->q_buffer;
-
-    chSysUnlock(); /* Gives a preemption chance in a controlled point.*/
-    r++;
-    if (--n == 0)
-      return r;
-
-    chSysLock();
-  }
-}
-
-/**
- * @brief   Initializes an output queue.
- * @details A Semaphore is internally initialized and works as a counter of
- *          the free bytes in the queue.
- * @note    The callback is invoked from within the S-Locked system state,
- *          see @ref system_states.
- *
- * @param[out] oqp      pointer to an @p OutputQueue structure
- * @param[in] bp        pointer to a memory area allocated as queue buffer
- * @param[in] size      size of the queue buffer
- * @param[in] onfy      pointer to a callback function that is invoked when
- *                      data is written to the queue. The value can be @p NULL.
- * @param[in] link      application defined pointer
- *
- * @init
- */
-void chOQInit(OutputQueue *oqp, uint8_t *bp, size_t size, qnotify_t onfy,
-              void *link) {
-
-  queue_init(&oqp->q_waiting);
-  oqp->q_counter = size;
-  oqp->q_buffer = oqp->q_rdptr = oqp->q_wrptr = bp;
-  oqp->q_top = bp + size;
-  oqp->q_notify = onfy;
-  oqp->q_link = link;
-}
-
-/**
- * @brief   Resets an output queue.
- * @details All the data in the output queue is erased and lost, any waiting
- *          thread is resumed with status @p Q_RESET.
- * @note    A reset operation can be used by a low level driver in order to
- *          obtain immediate attention from the high level layers.
- *
- * @param[in] oqp       pointer to an @p OutputQueue structure
- *
- * @iclass
- */
-void chOQResetI(OutputQueue *oqp) {
-
-  chDbgCheckClassI();
-
-  oqp->q_rdptr = oqp->q_wrptr = oqp->q_buffer;
-  oqp->q_counter = chQSizeI(oqp);
-  while (notempty(&oqp->q_waiting))
-    chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_RESET;
-}
-
-/**
- * @brief   Output queue write with timeout.
- * @details This function writes a byte value to an output queue. If the queue
- *          is full then the calling thread is suspended until there is space
- *          in the queue or a timeout occurs.
- * @note    The callback is invoked after writing the character into the
- *          buffer.
- *
- * @param[in] oqp       pointer to an @p OutputQueue structure
- * @param[in] b         the byte value to be written in the queue
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The operation status.
- * @retval Q_OK         if the operation succeeded.
- * @retval Q_TIMEOUT    if the specified time expired.
- * @retval Q_RESET      if the queue has been reset.
- *
- * @api
- */
-msg_t chOQPutTimeout(OutputQueue *oqp, uint8_t b, systime_t time) {
-
-  chSysLock();
-  while (chOQIsFullI(oqp)) {
-    msg_t msg;
-
-    if ((msg = qwait((GenericQueue *)oqp, time)) < Q_OK) {
-      chSysUnlock();
-      return msg;
-    }
-  }
-
-  oqp->q_counter--;
-  *oqp->q_wrptr++ = b;
-  if (oqp->q_wrptr >= oqp->q_top)
-    oqp->q_wrptr = oqp->q_buffer;
-
-  if (oqp->q_notify)
-    oqp->q_notify(oqp);
-
-  chSysUnlock();
-  return Q_OK;
-}
-
-/**
- * @brief   Output queue read.
- * @details A byte value is read from the low end of an output queue.
- *
- * @param[in] oqp       pointer to an @p OutputQueue structure
- * @return              The byte value from the queue.
- * @retval Q_EMPTY      if the queue is empty.
- *
- * @iclass
- */
-msg_t chOQGetI(OutputQueue *oqp) {
-  uint8_t b;
-
-  chDbgCheckClassI();
-
-  if (chOQIsEmptyI(oqp))
-    return Q_EMPTY;
-
-  oqp->q_counter++;
-  b = *oqp->q_rdptr++;
-  if (oqp->q_rdptr >= oqp->q_top)
-    oqp->q_rdptr = oqp->q_buffer;
-
-  if (notempty(&oqp->q_waiting))
-    chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
-
-  return b;
-}
-
-/**
- * @brief   Output queue write with timeout.
- * @details The function writes data from a buffer to an output queue. The
- *          operation completes when the specified amount of data has been
- *          transferred or after the specified timeout or if the queue has
- *          been reset.
- * @note    The function is not atomic, if you need atomicity it is suggested
- *          to use a semaphore or a mutex for mutual exclusion.
- * @note    The callback is invoked after writing each character into the
- *          buffer.
- *
- * @param[in] oqp       pointer to an @p OutputQueue structure
- * @param[out] bp       pointer to the data buffer
- * @param[in] n         the maximum amount of data to be transferred, the
- *                      value 0 is reserved
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              The number of bytes effectively transferred.
- *
- * @api
- */
-size_t chOQWriteTimeout(OutputQueue *oqp, const uint8_t *bp,
-                        size_t n, systime_t time) {
-  qnotify_t nfy = oqp->q_notify;
-  size_t w = 0;
-
-  chDbgCheck(n > 0, "chOQWriteTimeout");
-
-  chSysLock();
-  while (TRUE) {
-    while (chOQIsFullI(oqp)) {
-      if (qwait((GenericQueue *)oqp, time) != Q_OK) {
-        chSysUnlock();
-        return w;
-      }
-    }
-    oqp->q_counter--;
-    *oqp->q_wrptr++ = *bp++;
-    if (oqp->q_wrptr >= oqp->q_top)
-      oqp->q_wrptr = oqp->q_buffer;
-
-    if (nfy)
-      nfy(oqp);
-
-    chSysUnlock(); /* Gives a preemption chance in a controlled point.*/
-    w++;
-    if (--n == 0)
-      return w;
-    chSysLock();
-  }
-}
-#endif  /* CH_USE_QUEUES */
-
-/** @} */
diff --git a/os/kernel/src/chregistry.c b/os/kernel/src/chregistry.c
deleted file mode 100644
index 645172833..000000000
--- a/os/kernel/src/chregistry.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chregistry.c
- * @brief   Threads registry code.
- *
- * @addtogroup registry
- * @details Threads Registry related APIs and services.
- *
- *          <h2>Operation mode</h2>
- *          The Threads Registry is a double linked list that holds all the
- *          active threads in the system.<br>
- *          Operations defined for the registry:
- *          - <b>First</b>, returns the first, in creation order, active thread
- *            in the system.
- *          - <b>Next</b>, returns the next, in creation order, active thread
- *            in the system.
- *          .
- *          The registry is meant to be mainly a debug feature, for example,
- *          using the registry a debugger can enumerate the active threads
- *          in any given moment or the shell can print the active threads
- *          and their state.<br>
- *          Another possible use is for centralized threads memory management,
- *          terminating threads can pulse an event source and an event handler
- *          can perform a scansion of the registry in order to recover the
- *          memory.
- * @pre     In order to use the threads registry the @p CH_USE_REGISTRY option
- *          must be enabled in @p chconf.h.
- * @{
- */
-#include "ch.h"
-
-#if CH_USE_REGISTRY || defined(__DOXYGEN__)
-
-#define _offsetof(st, m)                                                     \
-  ((size_t)((char *)&((st *)0)->m - (char *)0))
-
-/*
- * OS signature in ROM plus debug-related information.
- */
-ROMCONST chdebug_t ch_debug = {
-  "main",
-  (uint8_t)0,
-  (uint8_t)sizeof (chdebug_t),
-  (uint16_t)((CH_KERNEL_MAJOR << 11) |
-             (CH_KERNEL_MINOR << 6) |
-             (CH_KERNEL_PATCH) << 0),
-  (uint8_t)sizeof (void *),
-  (uint8_t)sizeof (systime_t),
-  (uint8_t)sizeof (Thread),
-  (uint8_t)_offsetof(Thread, p_prio),
-  (uint8_t)_offsetof(Thread, p_ctx),
-  (uint8_t)_offsetof(Thread, p_newer),
-  (uint8_t)_offsetof(Thread, p_older),
-  (uint8_t)_offsetof(Thread, p_name),
-#if CH_DBG_ENABLE_STACK_CHECK
-  (uint8_t)_offsetof(Thread, p_stklimit),
-#else
-  (uint8_t)0,
-#endif
-  (uint8_t)_offsetof(Thread, p_state),
-  (uint8_t)_offsetof(Thread, p_flags),
-#if CH_USE_DYNAMIC
-  (uint8_t)_offsetof(Thread, p_refs),
-#else
-  (uint8_t)0,
-#endif
-#if CH_TIME_QUANTUM > 0
-  (uint8_t)_offsetof(Thread, p_preempt),
-#else
-  (uint8_t)0,
-#endif
-#if CH_DBG_THREADS_PROFILING
-  (uint8_t)_offsetof(Thread, p_time)
-#else
-  (uint8_t)0
-#endif
-};
-
-/**
- * @brief   Returns the first thread in the system.
- * @details Returns the most ancient thread in the system, usually this is
- *          the main thread unless it terminated. A reference is added to the
- *          returned thread in order to make sure its status is not lost.
- * @note    This function cannot return @p NULL because there is always at
- *          least one thread in the system.
- *
- * @return              A reference to the most ancient thread.
- *
- * @api
- */
-Thread *chRegFirstThread(void) {
-  Thread *tp;
-
-  chSysLock();
-  tp = rlist.r_newer;
-#if CH_USE_DYNAMIC
-  tp->p_refs++;
-#endif
-  chSysUnlock();
-  return tp;
-}
-
-/**
- * @brief   Returns the thread next to the specified one.
- * @details The reference counter of the specified thread is decremented and
- *          the reference counter of the returned thread is incremented.
- *
- * @param[in] tp        pointer to the thread
- * @return              A reference to the next thread.
- * @retval NULL         if there is no next thread.
- *
- * @api
- */
-Thread *chRegNextThread(Thread *tp) {
-  Thread *ntp;
-
-  chSysLock();
-  ntp = tp->p_newer;
-  if (ntp == (Thread *)&rlist)
-    ntp = NULL;
-#if CH_USE_DYNAMIC
-  else {
-    chDbgAssert(ntp->p_refs < 255, "chRegNextThread(), #1",
-                "too many references");
-    ntp->p_refs++;
-  }
-#endif
-  chSysUnlock();
-#if CH_USE_DYNAMIC
-  chThdRelease(tp);
-#endif
-  return ntp;
-}
-
-#endif /* CH_USE_REGISTRY */
-
-/** @} */
diff --git a/os/kernel/src/chschd.c b/os/kernel/src/chschd.c
deleted file mode 100644
index 1106cf03f..000000000
--- a/os/kernel/src/chschd.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chschd.c
- * @brief   Scheduler code.
- *
- * @addtogroup scheduler
- * @details This module provides the default portable scheduler code,
- *          scheduler functions can be individually captured by the port
- *          layer in order to provide architecture optimized equivalents.
- *          When a function is captured its default code is not built into
- *          the OS image, the optimized version is included instead.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Ready list header.
- */
-#if !defined(PORT_OPTIMIZED_RLIST_VAR) || defined(__DOXYGEN__)
-ReadyList rlist;
-#endif /* !defined(PORT_OPTIMIZED_RLIST_VAR) */
-
-/**
- * @brief   Scheduler initialization.
- *
- * @notapi
- */
-void _scheduler_init(void) {
-
-  queue_init(&rlist.r_queue);
-  rlist.r_prio = NOPRIO;
-#if CH_USE_REGISTRY
-  rlist.r_newer = rlist.r_older = (Thread *)&rlist;
-#endif
-}
-
-/**
- * @brief   Inserts a thread in the Ready List.
- * @details The thread is positioned behind all threads with higher or equal
- *          priority.
- * @pre     The thread must not be already inserted in any list through its
- *          @p p_next and @p p_prev or list corruption would occur.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel. Note that
- *          interrupt handlers always reschedule on exit so an explicit
- *          reschedule must not be performed in ISRs.
- *
- * @param[in] tp        the thread to be made ready
- * @return              The thread pointer.
- *
- * @iclass
- */
-#if !defined(PORT_OPTIMIZED_READYI) || defined(__DOXYGEN__)
-Thread *chSchReadyI(Thread *tp) {
-  Thread *cp;
-
-  chDbgCheckClassI();
-
-  /* Integrity checks.*/
-  chDbgAssert((tp->p_state != THD_STATE_READY) &&
-              (tp->p_state != THD_STATE_FINAL),
-              "chSchReadyI(), #1",
-              "invalid state");
-
-  tp->p_state = THD_STATE_READY;
-  cp = (Thread *)&rlist.r_queue;
-  do {
-    cp = cp->p_next;
-  } while (cp->p_prio >= tp->p_prio);
-  /* Insertion on p_prev.*/
-  tp->p_next = cp;
-  tp->p_prev = cp->p_prev;
-  tp->p_prev->p_next = cp->p_prev = tp;
-  return tp;
-}
-#endif /* !defined(PORT_OPTIMIZED_READYI) */
-
-/**
- * @brief   Puts the current thread to sleep into the specified state.
- * @details The thread goes into a sleeping state. The possible
- *          @ref thread_states are defined into @p threads.h.
- *
- * @param[in] newstate  the new thread state
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_GOSLEEPS) || defined(__DOXYGEN__)
-void chSchGoSleepS(tstate_t newstate) {
-  Thread *otp;
-
-  chDbgCheckClassS();
-
-  (otp = currp)->p_state = newstate;
-#if CH_TIME_QUANTUM > 0
-  /* The thread is renouncing its remaining time slices so it will have a new
-     time quantum when it will wakeup.*/
-  otp->p_preempt = CH_TIME_QUANTUM;
-#endif
-  setcurrp(fifo_remove(&rlist.r_queue));
-  currp->p_state = THD_STATE_CURRENT;
-  chSysSwitch(currp, otp);
-}
-#endif /* !defined(PORT_OPTIMIZED_GOSLEEPS) */
-
-#if !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) || defined(__DOXYGEN__)
-/*
- * Timeout wakeup callback.
- */
-static void wakeup(void *p) {
-  Thread *tp = (Thread *)p;
-
-  chSysLockFromIsr();
-  switch (tp->p_state) {
-  case THD_STATE_READY:
-    /* Handling the special case where the thread has been made ready by
-       another thread with higher priority.*/
-    chSysUnlockFromIsr();
-    return;
-#if CH_USE_SEMAPHORES || CH_USE_QUEUES ||                                   \
-    (CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT)
-#if CH_USE_SEMAPHORES
-  case THD_STATE_WTSEM:
-    chSemFastSignalI((Semaphore *)tp->p_u.wtobjp);
-    /* Falls into, intentional. */
-#endif
-#if CH_USE_QUEUES
-  case THD_STATE_WTQUEUE:
-#endif
-#if CH_USE_CONDVARS && CH_USE_CONDVARS_TIMEOUT
-  case THD_STATE_WTCOND:
-#endif
-    /* States requiring dequeuing.*/
-    dequeue(tp);
-#endif
-  }
-  tp->p_u.rdymsg = RDY_TIMEOUT;
-  chSchReadyI(tp);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Puts the current thread to sleep into the specified state with
- *          timeout specification.
- * @details The thread goes into a sleeping state, if it is not awakened
- *          explicitly within the specified timeout then it is forcibly
- *          awakened with a @p RDY_TIMEOUT low level message. The possible
- *          @ref thread_states are defined into @p threads.h.
- *
- * @param[in] newstate  the new thread state
- * @param[in] time      the number of ticks before the operation timeouts, the
- *                      special values are handled as follow:
- *                      - @a TIME_INFINITE the thread enters an infinite sleep
- *                        state, this is equivalent to invoking
- *                        @p chSchGoSleepS() but, of course, less efficient.
- *                      - @a TIME_IMMEDIATE this value is not allowed.
- *                      .
- * @return              The wakeup message.
- * @retval RDY_TIMEOUT if a timeout occurs.
- *
- * @sclass
- */
-msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time) {
-
-  chDbgCheckClassS();
-
-  if (TIME_INFINITE != time) {
-    VirtualTimer vt;
-
-    chVTSetI(&vt, time, wakeup, currp);
-    chSchGoSleepS(newstate);
-    if (chVTIsArmedI(&vt))
-      chVTResetI(&vt);
-  }
-  else
-    chSchGoSleepS(newstate);
-  return currp->p_u.rdymsg;
-}
-#endif /* !defined(PORT_OPTIMIZED_GOSLEEPTIMEOUTS) */
-
-/**
- * @brief   Wakes up a thread.
- * @details The thread is inserted into the ready list or immediately made
- *          running depending on its relative priority compared to the current
- *          thread.
- * @pre     The thread must not be already inserted in any list through its
- *          @p p_next and @p p_prev or list corruption would occur.
- * @note    It is equivalent to a @p chSchReadyI() followed by a
- *          @p chSchRescheduleS() but much more efficient.
- * @note    The function assumes that the current thread has the highest
- *          priority.
- *
- * @param[in] ntp       the Thread to be made ready
- * @param[in] msg       message to the awakened thread
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_WAKEUPS) || defined(__DOXYGEN__)
-void chSchWakeupS(Thread *ntp, msg_t msg) {
-
-  chDbgCheckClassS();
-
-  ntp->p_u.rdymsg = msg;
-  /* If the waken thread has a not-greater priority than the current
-     one then it is just inserted in the ready list else it made
-     running immediately and the invoking thread goes in the ready
-     list instead.*/
-  if (ntp->p_prio <= currp->p_prio)
-    chSchReadyI(ntp);
-  else {
-    Thread *otp = chSchReadyI(currp);
-    setcurrp(ntp);
-    ntp->p_state = THD_STATE_CURRENT;
-    chSysSwitch(ntp, otp);
-  }
-}
-#endif /* !defined(PORT_OPTIMIZED_WAKEUPS) */
-
-/**
- * @brief   Performs a reschedule if a higher priority thread is runnable.
- * @details If a thread with a higher priority than the current thread is in
- *          the ready list then make the higher priority thread running.
- *
- * @sclass
- */
-#if !defined(PORT_OPTIMIZED_RESCHEDULES) || defined(__DOXYGEN__)
-void chSchRescheduleS(void) {
-
-  chDbgCheckClassS();
-
-  if (chSchIsRescRequiredI())
-    chSchDoRescheduleAhead();
-}
-#endif /* !defined(PORT_OPTIMIZED_RESCHEDULES) */
-
-/**
- * @brief   Evaluates if preemption is required.
- * @details The decision is taken by comparing the relative priorities and
- *          depending on the state of the round robin timeout counter.
- * @note    Not a user function, it is meant to be invoked by the scheduler
- *          itself or from within the port layer.
- *
- * @retval TRUE         if there is a thread that must go in running state
- *                      immediately.
- * @retval FALSE        if preemption is not required.
- *
- * @special
- */
-#if !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) || defined(__DOXYGEN__)
-bool_t chSchIsPreemptionRequired(void) {
-  tprio_t p1 = firstprio(&rlist.r_queue);
-  tprio_t p2 = currp->p_prio;
-#if CH_TIME_QUANTUM > 0
-  /* If the running thread has not reached its time quantum, reschedule only
-     if the first thread on the ready queue has a higher priority.
-     Otherwise, if the running thread has used up its time quantum, reschedule
-     if the first thread on the ready queue has equal or higher priority.*/
-  return currp->p_preempt ? p1 > p2 : p1 >= p2;
-#else
-  /* If the round robin preemption feature is not enabled then performs a
-     simpler comparison.*/
-  return p1 > p2;
-#endif
-}
-#endif /* !defined(PORT_OPTIMIZED_ISPREEMPTIONREQUIRED) */
-
-/**
- * @brief   Switches to the first thread on the runnable queue.
- * @details The current thread is positioned in the ready list behind all
- *          threads having the same priority. The thread regains its time
- *          quantum.
- * @note    Not a user function, it is meant to be invoked by the scheduler
- *          itself or from within the port layer.
- *
- * @special
- */
-#if !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) || defined(__DOXYGEN__)
-void chSchDoRescheduleBehind(void) {
-  Thread *otp;
-
-  otp = currp;
-  /* Picks the first thread from the ready queue and makes it current.*/
-  setcurrp(fifo_remove(&rlist.r_queue));
-  currp->p_state = THD_STATE_CURRENT;
-#if CH_TIME_QUANTUM > 0
-  otp->p_preempt = CH_TIME_QUANTUM;
-#endif
-  chSchReadyI(otp);
-  chSysSwitch(currp, otp);
-}
-#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULEBEHIND) */
-
-/**
- * @brief   Switches to the first thread on the runnable queue.
- * @details The current thread is positioned in the ready list ahead of all
- *          threads having the same priority.
- * @note    Not a user function, it is meant to be invoked by the scheduler
- *          itself or from within the port layer.
- *
- * @special
- */
-#if !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) || defined(__DOXYGEN__)
-void chSchDoRescheduleAhead(void) {
-  Thread *otp, *cp;
-
-  otp = currp;
-  /* Picks the first thread from the ready queue and makes it current.*/
-  setcurrp(fifo_remove(&rlist.r_queue));
-  currp->p_state = THD_STATE_CURRENT;
-
-  otp->p_state = THD_STATE_READY;
-  cp = (Thread *)&rlist.r_queue;
-  do {
-    cp = cp->p_next;
-  } while (cp->p_prio > otp->p_prio);
-  /* Insertion on p_prev.*/
-  otp->p_next = cp;
-  otp->p_prev = cp->p_prev;
-  otp->p_prev->p_next = cp->p_prev = otp;
-
-  chSysSwitch(currp, otp);
-}
-#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULEAHEAD) */
-
-/**
- * @brief   Switches to the first thread on the runnable queue.
- * @details The current thread is positioned in the ready list behind or
- *          ahead of all threads having the same priority depending on
- *          if it used its whole time slice.
- * @note    Not a user function, it is meant to be invoked by the scheduler
- *          itself or from within the port layer.
- *
- * @special
- */
-#if !defined(PORT_OPTIMIZED_DORESCHEDULE) || defined(__DOXYGEN__)
-void chSchDoReschedule(void) {
-
-#if CH_TIME_QUANTUM > 0
-  /* If CH_TIME_QUANTUM is enabled then there are two different scenarios to
-     handle on preemption: time quantum elapsed or not.*/
-  if (currp->p_preempt == 0) {
-    /* The thread consumed its time quantum so it is enqueued behind threads
-       with same priority level, however, it acquires a new time quantum.*/
-    chSchDoRescheduleBehind();
-  }
-  else {
-    /* The thread didn't consume all its time quantum so it is put ahead of
-       threads with equal priority and does not acquire a new time quantum.*/
-    chSchDoRescheduleAhead();
-  }
-#else /* !(CH_TIME_QUANTUM > 0) */
-  /* If the round-robin mechanism is disabled then the thread goes always
-     ahead of its peers.*/
-  chSchDoRescheduleAhead();
-#endif /* !(CH_TIME_QUANTUM > 0) */
-}
-#endif /* !defined(PORT_OPTIMIZED_DORESCHEDULE) */
-
-/** @} */
diff --git a/os/kernel/src/chsem.c b/os/kernel/src/chsem.c
deleted file mode 100644
index c9e429beb..000000000
--- a/os/kernel/src/chsem.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chsem.c
- * @brief   Semaphores code.
- *
- * @addtogroup semaphores
- * @details Semaphores related APIs and services.
- *
- *          <h2>Operation mode</h2>
- *          Semaphores are a flexible synchronization primitive, ChibiOS/RT
- *          implements semaphores in their "counting semaphores" variant as
- *          defined by Edsger Dijkstra plus several enhancements like:
- *          - Wait operation with timeout.
- *          - Reset operation.
- *          - Atomic wait+signal operation.
- *          - Return message from the wait operation (OK, RESET, TIMEOUT).
- *          .
- *          The binary semaphores variant can be easily implemented using
- *          counting semaphores.<br>
- *          Operations defined for semaphores:
- *          - <b>Signal</b>: The semaphore counter is increased and if the
- *            result is non-positive then a waiting thread is removed from
- *            the semaphore queue and made ready for execution.
- *          - <b>Wait</b>: The semaphore counter is decreased and if the result
- *            becomes negative the thread is queued in the semaphore and
- *            suspended.
- *          - <b>Reset</b>: The semaphore counter is reset to a non-negative
- *            value and all the threads in the queue are released.
- *          .
- *          Semaphores can be used as guards for mutual exclusion zones
- *          (note that mutexes are recommended for this kind of use) but
- *          also have other uses, queues guards and counters for example.<br>
- *          Semaphores usually use a FIFO queuing strategy but it is possible
- *          to make them order threads by priority by enabling
- *          @p CH_USE_SEMAPHORES_PRIORITY in @p chconf.h.
- * @pre     In order to use the semaphore APIs the @p CH_USE_SEMAPHORES
- *          option must be enabled in @p chconf.h.
- * @{
- */
-
-#include "ch.h"
-
-#if CH_USE_SEMAPHORES || defined(__DOXYGEN__)
-
-#if CH_USE_SEMAPHORES_PRIORITY
-#define sem_insert(tp, qp) prio_insert(tp, qp)
-#else
-#define sem_insert(tp, qp) queue_insert(tp, qp)
-#endif
-
-/**
- * @brief   Initializes a semaphore with the specified counter value.
- *
- * @param[out] sp       pointer to a @p Semaphore structure
- * @param[in] n         initial value of the semaphore counter. Must be
- *                      non-negative.
- *
- * @init
- */
-void chSemInit(Semaphore *sp, cnt_t n) {
-
-  chDbgCheck((sp != NULL) && (n >= 0), "chSemInit");
-
-  queue_init(&sp->s_queue);
-  sp->s_cnt = n;
-}
-
-/**
- * @brief   Performs a reset operation on the semaphore.
- * @post    After invoking this function all the threads waiting on the
- *          semaphore, if any, are released and the semaphore counter is set
- *          to the specified, non negative, value.
- * @note    The released threads can recognize they were waked up by a reset
- *          rather than a signal because the @p chSemWait() will return
- *          @p RDY_RESET instead of @p RDY_OK.
- *
- * @param[in] sp        pointer to a @p Semaphore structure
- * @param[in] n         the new value of the semaphore counter. The value must
- *                      be non-negative.
- *
- * @api
- */
-void chSemReset(Semaphore *sp, cnt_t n) {
-
-  chSysLock();
-  chSemResetI(sp, n);
-  chSchRescheduleS();
-  chSysUnlock();
-}
-
-/**
- * @brief   Performs a reset operation on the semaphore.
- * @post    After invoking this function all the threads waiting on the
- *          semaphore, if any, are released and the semaphore counter is set
- *          to the specified, non negative, value.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel. Note that
- *          interrupt handlers always reschedule on exit so an explicit
- *          reschedule must not be performed in ISRs.
- * @note    The released threads can recognize they were waked up by a reset
- *          rather than a signal because the @p chSemWait() will return
- *          @p RDY_RESET instead of @p RDY_OK.
- *
- * @param[in] sp        pointer to a @p Semaphore structure
- * @param[in] n         the new value of the semaphore counter. The value must
- *                      be non-negative.
- *
- * @iclass
- */
-void chSemResetI(Semaphore *sp, cnt_t n) {
-  cnt_t cnt;
-
-  chDbgCheckClassI();
-  chDbgCheck((sp != NULL) && (n >= 0), "chSemResetI");
-  chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
-              ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
-              "chSemResetI(), #1",
-              "inconsistent semaphore");
-
-  cnt = sp->s_cnt;
-  sp->s_cnt = n;
-  while (++cnt <= 0)
-    chSchReadyI(lifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_RESET;
-}
-
-/**
- * @brief   Performs a wait operation on a semaphore.
- *
- * @param[in] sp        pointer to a @p Semaphore structure
- * @return              A message specifying how the invoking thread has been
- *                      released from the semaphore.
- * @retval RDY_OK       if the thread has not stopped on the semaphore or the
- *                      semaphore has been signaled.
- * @retval RDY_RESET    if the semaphore has been reset using @p chSemReset().
- *
- * @api
- */
-msg_t chSemWait(Semaphore *sp) {
-  msg_t msg;
-
-  chSysLock();
-  msg = chSemWaitS(sp);
-  chSysUnlock();
-  return msg;
-}
-
-/**
- * @brief   Performs a wait operation on a semaphore.
- *
- * @param[in] sp        pointer to a @p Semaphore structure
- * @return              A message specifying how the invoking thread has been
- *                      released from the semaphore.
- * @retval RDY_OK       if the thread has not stopped on the semaphore or the
- *                      semaphore has been signaled.
- * @retval RDY_RESET    if the semaphore has been reset using @p chSemReset().
- *
- * @sclass
- */
-msg_t chSemWaitS(Semaphore *sp) {
-
-  chDbgCheckClassS();
-  chDbgCheck(sp != NULL, "chSemWaitS");
-  chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
-              ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
-              "chSemWaitS(), #1",
-              "inconsistent semaphore");
-
-  if (--sp->s_cnt < 0) {
-    currp->p_u.wtobjp = sp;
-    sem_insert(currp, &sp->s_queue);
-    chSchGoSleepS(THD_STATE_WTSEM);
-    return currp->p_u.rdymsg;
-  }
-  return RDY_OK;
-}
-
-/**
- * @brief   Performs a wait operation on a semaphore with timeout specification.
- *
- * @param[in] sp        pointer to a @p Semaphore structure
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              A message specifying how the invoking thread has been
- *                      released from the semaphore.
- * @retval RDY_OK       if the thread has not stopped on the semaphore or the
- *                      semaphore has been signaled.
- * @retval RDY_RESET    if the semaphore has been reset using @p chSemReset().
- * @retval RDY_TIMEOUT  if the semaphore has not been signaled or reset within
- *                      the specified timeout.
- *
- * @api
- */
-msg_t chSemWaitTimeout(Semaphore *sp, systime_t time) {
-  msg_t msg;
-
-  chSysLock();
-  msg = chSemWaitTimeoutS(sp, time);
-  chSysUnlock();
-  return msg;
-}
-
-/**
- * @brief   Performs a wait operation on a semaphore with timeout specification.
- *
- * @param[in] sp        pointer to a @p Semaphore structure
- * @param[in] time      the number of ticks before the operation timeouts,
- *                      the following special values are allowed:
- *                      - @a TIME_IMMEDIATE immediate timeout.
- *                      - @a TIME_INFINITE no timeout.
- *                      .
- * @return              A message specifying how the invoking thread has been
- *                      released from the semaphore.
- * @retval RDY_OK       if the thread has not stopped on the semaphore or the
- *                      semaphore has been signaled.
- * @retval RDY_RESET    if the semaphore has been reset using @p chSemReset().
- * @retval RDY_TIMEOUT  if the semaphore has not been signaled or reset within
- *                      the specified timeout.
- *
- * @sclass
- */
-msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time) {
-
-  chDbgCheckClassS();
-  chDbgCheck(sp != NULL, "chSemWaitTimeoutS");
-  chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
-              ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
-              "chSemWaitTimeoutS(), #1",
-              "inconsistent semaphore");
-
-  if (--sp->s_cnt < 0) {
-    if (TIME_IMMEDIATE == time) {
-      sp->s_cnt++;
-      return RDY_TIMEOUT;
-    }
-    currp->p_u.wtobjp = sp;
-    sem_insert(currp, &sp->s_queue);
-    return chSchGoSleepTimeoutS(THD_STATE_WTSEM, time);
-  }
-  return RDY_OK;
-}
-
-/**
- * @brief   Performs a signal operation on a semaphore.
- *
- * @param[in] sp        pointer to a @p Semaphore structure
- *
- * @api
- */
-void chSemSignal(Semaphore *sp) {
-
-  chDbgCheck(sp != NULL, "chSemSignal");
-  chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
-              ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
-              "chSemSignal(), #1",
-              "inconsistent semaphore");
-
-  chSysLock();
-  if (++sp->s_cnt <= 0)
-    chSchWakeupS(fifo_remove(&sp->s_queue), RDY_OK);
-  chSysUnlock();
-}
-
-/**
- * @brief   Performs a signal operation on a semaphore.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel. Note that
- *          interrupt handlers always reschedule on exit so an explicit
- *          reschedule must not be performed in ISRs.
- *
- * @param[in] sp    pointer to a @p Semaphore structure
- *
- * @iclass
- */
-void chSemSignalI(Semaphore *sp) {
-
-  chDbgCheckClassI();
-  chDbgCheck(sp != NULL, "chSemSignalI");
-  chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
-              ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
-              "chSemSignalI(), #1",
-              "inconsistent semaphore");
-
-  if (++sp->s_cnt <= 0) {
-    /* Note, it is done this way in order to allow a tail call on
-             chSchReadyI().*/
-    Thread *tp = fifo_remove(&sp->s_queue);
-    tp->p_u.rdymsg = RDY_OK;
-    chSchReadyI(tp);
-  }
-}
-
-/**
- * @brief   Adds the specified value to the semaphore counter.
- * @post    This function does not reschedule so a call to a rescheduling
- *          function must be performed before unlocking the kernel. Note that
- *          interrupt handlers always reschedule on exit so an explicit
- *          reschedule must not be performed in ISRs.
- *
- * @param[in] sp        pointer to a @p Semaphore structure
- * @param[in] n         value to be added to the semaphore counter. The value
- *                      must be positive.
- *
- * @iclass
- */
-void chSemAddCounterI(Semaphore *sp, cnt_t n) {
-
-  chDbgCheckClassI();
-  chDbgCheck((sp != NULL) && (n > 0), "chSemAddCounterI");
-  chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
-              ((sp->s_cnt < 0) && notempty(&sp->s_queue)),
-              "chSemAddCounterI(), #1",
-              "inconsistent semaphore");
-
-  while (n > 0) {
-    if (++sp->s_cnt <= 0)
-      chSchReadyI(fifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_OK;
-    n--;
-  }
-}
-
-#if CH_USE_SEMSW || defined(__DOXYGEN__)
-/**
- * @brief   Performs atomic signal and wait operations on two semaphores.
- * @pre     The configuration option @p CH_USE_SEMSW must be enabled in order
- *          to use this function.
- *
- * @param[in] sps       pointer to a @p Semaphore structure to be signaled
- * @param[in] spw       pointer to a @p Semaphore structure to wait on
- * @return              A message specifying how the invoking thread has been
- *                      released from the semaphore.
- * @retval RDY_OK       if the thread has not stopped on the semaphore or the
- *                      semaphore has been signaled.
- * @retval RDY_RESET    if the semaphore has been reset using @p chSemReset().
- *
- * @api
- */
-msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw) {
-  msg_t msg;
-
-  chDbgCheck((sps != NULL) && (spw != NULL), "chSemSignalWait");
-  chDbgAssert(((sps->s_cnt >= 0) && isempty(&sps->s_queue)) ||
-              ((sps->s_cnt < 0) && notempty(&sps->s_queue)),
-              "chSemSignalWait(), #1",
-              "inconsistent semaphore");
-  chDbgAssert(((spw->s_cnt >= 0) && isempty(&spw->s_queue)) ||
-              ((spw->s_cnt < 0) && notempty(&spw->s_queue)),
-              "chSemSignalWait(), #2",
-              "inconsistent semaphore");
-
-  chSysLock();
-  if (++sps->s_cnt <= 0)
-    chSchReadyI(fifo_remove(&sps->s_queue))->p_u.rdymsg = RDY_OK;
-  if (--spw->s_cnt < 0) {
-    Thread *ctp = currp;
-    sem_insert(ctp, &spw->s_queue);
-    ctp->p_u.wtobjp = spw;
-    chSchGoSleepS(THD_STATE_WTSEM);
-    msg = ctp->p_u.rdymsg;
-  }
-  else {
-    chSchRescheduleS();
-    msg = RDY_OK;
-  }
-  chSysUnlock();
-  return msg;
-}
-#endif /* CH_USE_SEMSW */
-
-#endif /* CH_USE_SEMAPHORES */
-
-/** @} */
diff --git a/os/kernel/src/chsys.c b/os/kernel/src/chsys.c
deleted file mode 100644
index a6f1d15ba..000000000
--- a/os/kernel/src/chsys.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chsys.c
- * @brief   System related code.
- *
- * @addtogroup system
- * @details System related APIs and services:
- *          - Initialization.
- *          - Locks.
- *          - Interrupt Handling.
- *          - Power Management.
- *          - Abnormal Termination.
- *          .
- * @{
- */
-
-#include "ch.h"
-
-#if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__)
-/**
- * @brief   Idle thread working area.
- */
-WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE);
-
-/**
- * @brief   This function implements the idle thread infinite loop.
- * @details The function puts the processor in the lowest power mode capable
- *          to serve interrupts.<br>
- *          The priority is internally set to the minimum system value so
- *          that this thread is executed only if there are no other ready
- *          threads in the system.
- *
- * @param[in] p the thread parameter, unused in this scenario
- */
-void _idle_thread(void *p) {
-
-  (void)p;
-  chRegSetThreadName("idle");
-  while (TRUE) {
-    port_wait_for_interrupt();
-    IDLE_LOOP_HOOK();
-  }
-}
-#endif /* CH_NO_IDLE_THREAD */
-
-/**
- * @brief   ChibiOS/RT initialization.
- * @details After executing this function the current instructions stream
- *          becomes the main thread.
- * @pre     Interrupts must be still disabled when @p chSysInit() is invoked
- *          and are internally enabled.
- * @post    The main thread is created with priority @p NORMALPRIO.
- * @note    This function has special, architecture-dependent, requirements,
- *          see the notes into the various port reference manuals.
- *
- * @special
- */
-void chSysInit(void) {
-  static Thread mainthread;
-#if CH_DBG_ENABLE_STACK_CHECK
-  extern stkalign_t __main_thread_stack_base__;
-#endif
-
-  port_init();
-  _scheduler_init();
-  _vt_init();
-#if CH_USE_MEMCORE
-  _core_init();
-#endif
-#if CH_USE_HEAP
-  _heap_init();
-#endif
-#if CH_DBG_ENABLE_TRACE
-  _trace_init();
-#endif
-
-  /* Now this instructions flow becomes the main thread.*/
-  setcurrp(_thread_init(&mainthread, NORMALPRIO));
-  currp->p_state = THD_STATE_CURRENT;
-#if CH_DBG_ENABLE_STACK_CHECK
-  /* This is a special case because the main thread Thread structure is not
-     adjacent to its stack area.*/
-  currp->p_stklimit = &__main_thread_stack_base__;
-#endif
-  chSysEnable();
-
-  /* Note, &ch_debug points to the string "main" if the registry is
-     active, else the parameter is ignored.*/
-  chRegSetThreadName((const char *)&ch_debug);
-
-#if !CH_NO_IDLE_THREAD
-  /* This thread has the lowest priority in the system, its role is just to
-     serve interrupts in its context while keeping the lowest energy saving
-     mode compatible with the system status.*/
-  chThdCreateStatic(_idle_thread_wa, sizeof(_idle_thread_wa), IDLEPRIO,
-                    (tfunc_t)_idle_thread, NULL);
-#endif
-}
-
-/**
- * @brief   Handles time ticks for round robin preemption and timer increments.
- * @details Decrements the remaining time quantum of the running thread
- *          and preempts it when the quantum is used up. Increments system
- *          time and manages the timers.
- * @note    The frequency of the timer determines the system tick granularity
- *          and, together with the @p CH_TIME_QUANTUM macro, the round robin
- *          interval.
- *
- * @iclass
- */
-void chSysTimerHandlerI(void) {
-
-  chDbgCheckClassI();
-
-#if CH_TIME_QUANTUM > 0
-  /* Running thread has not used up quantum yet? */
-  if (currp->p_preempt > 0)
-    /* Decrement remaining quantum.*/
-    currp->p_preempt--;
-#endif
-#if CH_DBG_THREADS_PROFILING
-  currp->p_time++;
-#endif
-  chVTDoTickI();
-#if defined(SYSTEM_TICK_EVENT_HOOK)
-  SYSTEM_TICK_EVENT_HOOK();
-#endif
-}
-
-/** @} */
diff --git a/os/kernel/src/chthreads.c b/os/kernel/src/chthreads.c
deleted file mode 100644
index 9f6973c90..000000000
--- a/os/kernel/src/chthreads.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chthreads.c
- * @brief   Threads code.
- *
- * @addtogroup threads
- * @details Threads related APIs and services.
- *
- *          <h2>Operation mode</h2>
- *          A thread is an abstraction of an independent instructions flow.
- *          In ChibiOS/RT a thread is represented by a "C" function owning
- *          a processor context, state informations and a dedicated stack
- *          area. In this scenario static variables are shared among all
- *          threads while automatic variables are local to the thread.<br>
- *          Operations defined for threads:
- *          - <b>Create</b>, a thread is started on the specified thread
- *            function. This operation is available in multiple variants,
- *            both static and dynamic.
- *          - <b>Exit</b>, a thread terminates by returning from its top
- *            level function or invoking a specific API, the thread can
- *            return a value that can be retrieved by other threads.
- *          - <b>Wait</b>, a thread waits for the termination of another
- *            thread and retrieves its return value.
- *          - <b>Resume</b>, a thread created in suspended state is started.
- *          - <b>Sleep</b>, the execution of a thread is suspended for the
- *            specified amount of time or the specified future absolute time
- *            is reached.
- *          - <b>SetPriority</b>, a thread changes its own priority level.
- *          - <b>Yield</b>, a thread voluntarily renounces to its time slot.
- *          .
- *          The threads subsystem is implicitly included in kernel however
- *          some of its part may be excluded by disabling them in @p chconf.h,
- *          see the @p CH_USE_WAITEXIT and @p CH_USE_DYNAMIC configuration
- *          options.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Initializes a thread structure.
- * @note    This is an internal functions, do not use it in application code.
- *
- * @param[in] tp        pointer to the thread
- * @param[in] prio      the priority level for the new thread
- * @return              The same thread pointer passed as parameter.
- *
- * @notapi
- */
-Thread *_thread_init(Thread *tp, tprio_t prio) {
-
-  tp->p_prio = prio;
-  tp->p_state = THD_STATE_SUSPENDED;
-  tp->p_flags = THD_MEM_MODE_STATIC;
-#if CH_TIME_QUANTUM > 0
-  tp->p_preempt = CH_TIME_QUANTUM;
-#endif
-#if CH_USE_MUTEXES
-  tp->p_realprio = prio;
-  tp->p_mtxlist = NULL;
-#endif
-#if CH_USE_EVENTS
-  tp->p_epending = 0;
-#endif
-#if CH_DBG_THREADS_PROFILING
-  tp->p_time = 0;
-#endif
-#if CH_USE_DYNAMIC
-  tp->p_refs = 1;
-#endif
-#if CH_USE_REGISTRY
-  tp->p_name = NULL;
-  REG_INSERT(tp);
-#endif
-#if CH_USE_WAITEXIT
-  list_init(&tp->p_waiting);
-#endif
-#if CH_USE_MESSAGES
-  queue_init(&tp->p_msgqueue);
-#endif
-#if CH_DBG_ENABLE_STACK_CHECK
-  tp->p_stklimit = (stkalign_t *)(tp + 1);
-#endif
-#if defined(THREAD_EXT_INIT_HOOK)
-  THREAD_EXT_INIT_HOOK(tp);
-#endif
-  return tp;
-}
-
-#if CH_DBG_FILL_THREADS || defined(__DOXYGEN__)
-/**
- * @brief   Memory fill utility.
- *
- * @param[in] startp    first address to fill
- * @param[in] endp      last address to fill +1
- * @param[in] v         filler value
- *
- * @notapi
- */
-void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v) {
-
-  while (startp < endp)
-    *startp++ = v;
-}
-#endif /* CH_DBG_FILL_THREADS */
-
-/**
- * @brief   Creates a new thread into a static memory area.
- * @details The new thread is initialized but not inserted in the ready list,
- *          the initial state is @p THD_STATE_SUSPENDED.
- * @post    The initialized thread can be subsequently started by invoking
- *          @p chThdResume(), @p chThdResumeI() or @p chSchWakeupS()
- *          depending on the execution context.
- * @note    A thread can terminate by calling @p chThdExit() or by simply
- *          returning from its main function.
- * @note    Threads created using this function do not obey to the
- *          @p CH_DBG_FILL_THREADS debug option because it would keep
- *          the kernel locked for too much time.
- *
- * @param[out] wsp      pointer to a working area dedicated to the thread stack
- * @param[in] size      size of the working area
- * @param[in] prio      the priority level for the new thread
- * @param[in] pf        the thread function
- * @param[in] arg       an argument passed to the thread function. It can be
- *                      @p NULL.
- * @return              The pointer to the @p Thread structure allocated for
- *                      the thread into the working space area.
- *
- * @iclass
- */
-Thread *chThdCreateI(void *wsp, size_t size,
-                     tprio_t prio, tfunc_t pf, void *arg) {
-  /* Thread structure is laid out in the lower part of the thread workspace.*/
-  Thread *tp = wsp;
-
-  chDbgCheckClassI();
-
-  chDbgCheck((wsp != NULL) && (size >= THD_WA_SIZE(0)) &&
-             (prio <= HIGHPRIO) && (pf != NULL),
-             "chThdCreateI");
-  SETUP_CONTEXT(wsp, size, pf, arg);
-  return _thread_init(tp, prio);
-}
-
-/**
- * @brief   Creates a new thread into a static memory area.
- * @note    A thread can terminate by calling @p chThdExit() or by simply
- *          returning from its main function.
- *
- * @param[out] wsp      pointer to a working area dedicated to the thread stack
- * @param[in] size      size of the working area
- * @param[in] prio      the priority level for the new thread
- * @param[in] pf        the thread function
- * @param[in] arg       an argument passed to the thread function. It can be
- *                      @p NULL.
- * @return              The pointer to the @p Thread structure allocated for
- *                      the thread into the working space area.
- *
- * @api
- */
-Thread *chThdCreateStatic(void *wsp, size_t size,
-                          tprio_t prio, tfunc_t pf, void *arg) {
-  Thread *tp;
-  
-#if CH_DBG_FILL_THREADS
-  _thread_memfill((uint8_t *)wsp,
-                  (uint8_t *)wsp + sizeof(Thread),
-                  CH_THREAD_FILL_VALUE);
-  _thread_memfill((uint8_t *)wsp + sizeof(Thread),
-                  (uint8_t *)wsp + size,
-                  CH_STACK_FILL_VALUE);
-#endif
-  chSysLock();
-  chSchWakeupS(tp = chThdCreateI(wsp, size, prio, pf, arg), RDY_OK);
-  chSysUnlock();
-  return tp;
-}
-
-/**
- * @brief   Changes the running thread priority level then reschedules if
- *          necessary.
- * @note    The function returns the real thread priority regardless of the
- *          current priority that could be higher than the real priority
- *          because the priority inheritance mechanism.
- *
- * @param[in] newprio   the new priority level of the running thread
- * @return              The old priority level.
- *
- * @api
- */
-tprio_t chThdSetPriority(tprio_t newprio) {
-  tprio_t oldprio;
-
-  chDbgCheck(newprio <= HIGHPRIO, "chThdSetPriority");
-
-  chSysLock();
-#if CH_USE_MUTEXES
-  oldprio = currp->p_realprio;
-  if ((currp->p_prio == currp->p_realprio) || (newprio > currp->p_prio))
-    currp->p_prio = newprio;
-  currp->p_realprio = newprio;
-#else
-  oldprio = currp->p_prio;
-  currp->p_prio = newprio;
-#endif
-  chSchRescheduleS();
-  chSysUnlock();
-  return oldprio;
-}
-
-/**
- * @brief   Resumes a suspended thread.
- * @pre     The specified thread pointer must refer to an initialized thread
- *          in the @p THD_STATE_SUSPENDED state.
- * @post    The specified thread is immediately started or put in the ready
- *          list depending on the relative priority levels.
- * @note    Use this function to start threads created with @p chThdCreateI().
- *
- * @param[in] tp        pointer to the thread
- * @return              The pointer to the thread.
- *
- * @api
- */
-Thread *chThdResume(Thread *tp) {
-
-  chSysLock();
-  chDbgAssert(tp->p_state == THD_STATE_SUSPENDED,
-              "chThdResume(), #1",
-              "thread not in THD_STATE_SUSPENDED state");
-  chSchWakeupS(tp, RDY_OK);
-  chSysUnlock();
-  return tp;
-}
-
-/**
- * @brief   Requests a thread termination.
- * @pre     The target thread must be written to invoke periodically
- *          @p chThdShouldTerminate() and terminate cleanly if it returns
- *          @p TRUE.
- * @post    The specified thread will terminate after detecting the termination
- *          condition.
- *
- * @param[in] tp        pointer to the thread
- *
- * @api
- */
-void chThdTerminate(Thread *tp) {
-
-  chSysLock();
-  tp->p_flags |= THD_TERMINATE;
-  chSysUnlock();
-}
-
-/**
- * @brief   Suspends the invoking thread for the specified time.
- *
- * @param[in] time      the delay in system ticks, the special values are
- *                      handled as follow:
- *                      - @a TIME_INFINITE the thread enters an infinite sleep
- *                        state.
- *                      - @a TIME_IMMEDIATE this value is not allowed.
- *                      .
- *
- * @api
- */
-void chThdSleep(systime_t time) {
-
-  chDbgCheck(time != TIME_IMMEDIATE, "chThdSleep");
-
-  chSysLock();
-  chThdSleepS(time);
-  chSysUnlock();
-}
-
-/**
- * @brief   Suspends the invoking thread until the system time arrives to the
- *          specified value.
- *
- * @param[in] time      absolute system time
- *
- * @api
- */
-void chThdSleepUntil(systime_t time) {
-
-  chSysLock();
-  if ((time -= chTimeNow()) > 0)
-    chThdSleepS(time);
-  chSysUnlock();
-}
-
-/**
- * @brief   Yields the time slot.
- * @details Yields the CPU control to the next thread in the ready list with
- *          equal priority, if any.
- *
- * @api
- */
-void chThdYield(void) {
-
-  chSysLock();
-  chSchDoYieldS();
-  chSysUnlock();
-}
-
-/**
- * @brief   Terminates the current thread.
- * @details The thread goes in the @p THD_STATE_FINAL state holding the
- *          specified exit status code, other threads can retrieve the
- *          exit status code by invoking the function @p chThdWait().
- * @post    Eventual code after this function will never be executed,
- *          this function never returns. The compiler has no way to
- *          know this so do not assume that the compiler would remove
- *          the dead code.
- *
- * @param[in] msg       thread exit code
- *
- * @api
- */
-void chThdExit(msg_t msg) {
-
-  chSysLock();
-  chThdExitS(msg);
-  /* The thread never returns here.*/
-}
-
-/**
- * @brief   Terminates the current thread.
- * @details The thread goes in the @p THD_STATE_FINAL state holding the
- *          specified exit status code, other threads can retrieve the
- *          exit status code by invoking the function @p chThdWait().
- * @post    Eventual code after this function will never be executed,
- *          this function never returns. The compiler has no way to
- *          know this so do not assume that the compiler would remove
- *          the dead code.
- *
- * @param[in] msg       thread exit code
- *
- * @sclass
- */
-void chThdExitS(msg_t msg) {
-  Thread *tp = currp;
-
-  tp->p_u.exitcode = msg;
-#if defined(THREAD_EXT_EXIT_HOOK)
-  THREAD_EXT_EXIT_HOOK(tp);
-#endif
-#if CH_USE_WAITEXIT
-  while (notempty(&tp->p_waiting))
-    chSchReadyI(list_remove(&tp->p_waiting));
-#endif
-#if CH_USE_REGISTRY
-  /* Static threads are immediately removed from the registry because
-     there is no memory to recover.*/
-  if ((tp->p_flags & THD_MEM_MODE_MASK) == THD_MEM_MODE_STATIC)
-    REG_REMOVE(tp);
-#endif
-  chSchGoSleepS(THD_STATE_FINAL);
-  /* The thread never returns here.*/
-  chDbgAssert(FALSE, "chThdExitS(), #1", "zombies apocalypse");
-}
-
-#if CH_USE_WAITEXIT || defined(__DOXYGEN__)
-/**
- * @brief   Blocks the execution of the invoking thread until the specified
- *          thread terminates then the exit code is returned.
- * @details This function waits for the specified thread to terminate then
- *          decrements its reference counter, if the counter reaches zero then
- *          the thread working area is returned to the proper allocator.<br>
- *          The memory used by the exited thread is handled in different ways
- *          depending on the API that spawned the thread:
- *          - If the thread was spawned by @p chThdCreateStatic() or by
- *            @p chThdCreateI() then nothing happens and the thread working
- *            area is not released or modified in any way. This is the
- *            default, totally static, behavior.
- *          - If the thread was spawned by @p chThdCreateFromHeap() then
- *            the working area is returned to the system heap.
- *          - If the thread was spawned by @p chThdCreateFromMemoryPool()
- *            then the working area is returned to the owning memory pool.
- *          .
- * @pre     The configuration option @p CH_USE_WAITEXIT must be enabled in
- *          order to use this function.
- * @post    Enabling @p chThdWait() requires 2-4 (depending on the
- *          architecture) extra bytes in the @p Thread structure.
- * @post    After invoking @p chThdWait() the thread pointer becomes invalid
- *          and must not be used as parameter for further system calls.
- * @note    If @p CH_USE_DYNAMIC is not specified this function just waits for
- *          the thread termination, no memory allocators are involved.
- *
- * @param[in] tp        pointer to the thread
- * @return              The exit code from the terminated thread.
- *
- * @api
- */
-msg_t chThdWait(Thread *tp) {
-  msg_t msg;
-
-  chDbgCheck(tp != NULL, "chThdWait");
-
-  chSysLock();
-  chDbgAssert(tp != currp, "chThdWait(), #1", "waiting self");
-#if CH_USE_DYNAMIC
-  chDbgAssert(tp->p_refs > 0, "chThdWait(), #2", "not referenced");
-#endif
-  if (tp->p_state != THD_STATE_FINAL) {
-    list_insert(currp, &tp->p_waiting);
-    chSchGoSleepS(THD_STATE_WTEXIT);
-  }
-  msg = tp->p_u.exitcode;
-  chSysUnlock();
-#if CH_USE_DYNAMIC
-  chThdRelease(tp);
-#endif
-  return msg;
-}
-#endif /* CH_USE_WAITEXIT */
-
-/** @} */
diff --git a/os/kernel/src/chvt.c b/os/kernel/src/chvt.c
deleted file mode 100644
index f2d6cd697..000000000
--- a/os/kernel/src/chvt.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    chvt.c
- * @brief   Time and Virtual Timers related code.
- *
- * @addtogroup time
- * @details Time and Virtual Timers related APIs and services.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Virtual timers delta list header.
- */
-VTList vtlist;
-
-/**
- * @brief   Virtual Timers initialization.
- * @note    Internal use only.
- *
- * @notapi
- */
-void _vt_init(void) {
-
-  vtlist.vt_next = vtlist.vt_prev = (void *)&vtlist;
-  vtlist.vt_time = (systime_t)-1;
-  vtlist.vt_systime = 0;
-}
-
-/**
- * @brief   Enables a virtual timer.
- * @note    The associated function is invoked from interrupt context.
- *
- * @param[out] vtp      the @p VirtualTimer structure pointer
- * @param[in] time      the number of ticks before the operation timeouts, the
- *                      special values are handled as follow:
- *                      - @a TIME_INFINITE is allowed but interpreted as a
- *                        normal time specification.
- *                      - @a TIME_IMMEDIATE this value is not allowed.
- *                      .
- * @param[in] vtfunc    the timer callback function. After invoking the
- *                      callback the timer is disabled and the structure can
- *                      be disposed or reused.
- * @param[in] par       a parameter that will be passed to the callback
- *                      function
- *
- * @iclass
- */
-void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par) {
-  VirtualTimer *p;
-
-  chDbgCheckClassI();
-  chDbgCheck((vtp != NULL) && (vtfunc != NULL) && (time != TIME_IMMEDIATE),
-             "chVTSetI");
-
-  vtp->vt_par = par;
-  vtp->vt_func = vtfunc;
-  p = vtlist.vt_next;
-  while (p->vt_time < time) {
-    time -= p->vt_time;
-    p = p->vt_next;
-  }
-
-  vtp->vt_prev = (vtp->vt_next = p)->vt_prev;
-  vtp->vt_prev->vt_next = p->vt_prev = vtp;
-  vtp->vt_time = time;
-  if (p != (void *)&vtlist)
-    p->vt_time -= time;
-}
-
-/**
- * @brief   Disables a Virtual Timer.
- * @note    The timer MUST be active when this function is invoked.
- *
- * @param[in] vtp       the @p VirtualTimer structure pointer
- *
- * @iclass
- */
-void chVTResetI(VirtualTimer *vtp) {
-
-  chDbgCheckClassI();
-  chDbgCheck(vtp != NULL, "chVTResetI");
-  chDbgAssert(vtp->vt_func != NULL,
-              "chVTResetI(), #1",
-              "timer not set or already triggered");
-
-  if (vtp->vt_next != (void *)&vtlist)
-    vtp->vt_next->vt_time += vtp->vt_time;
-  vtp->vt_prev->vt_next = vtp->vt_next;
-  vtp->vt_next->vt_prev = vtp->vt_prev;
-  vtp->vt_func = (vtfunc_t)NULL;
-}
-
-/** @} */
diff --git a/os/kernel/templates/chconf.h b/os/kernel/templates/chconf.h
deleted file mode 100644
index ae54d3edf..000000000
--- a/os/kernel/templates/chconf.h
+++ /dev/null
@@ -1,535 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    templates/chconf.h
- * @brief   Configuration file template.
- * @details A copy of this file must be placed in each project directory, it
- *          contains the application specific kernel settings.
- *
- * @addtogroup config
- * @details Kernel related settings and hooks.
- * @{
- */
-
-#ifndef _CHCONF_H_
-#define _CHCONF_H_
-
-/*===========================================================================*/
-/**
- * @name Kernel parameters and options
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   System tick frequency.
- * @details Frequency of the system timer that drives the system ticks. This
- *          setting also defines the system tick time unit.
- */
-#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
-#define CH_FREQUENCY                    1000
-#endif
-
-/**
- * @brief   Round robin interval.
- * @details This constant is the number of system ticks allowed for the
- *          threads before preemption occurs. Setting this value to zero
- *          disables the preemption for threads with equal priority and the
- *          round robin becomes cooperative. Note that higher priority
- *          threads can still preempt, the kernel is always preemptive.
- *
- * @note    Disabling the round robin preemption makes the kernel more compact
- *          and generally faster.
- */
-#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
-#define CH_TIME_QUANTUM                 20
-#endif
-
-/**
- * @brief   Managed RAM size.
- * @details Size of the RAM area to be managed by the OS. If set to zero
- *          then the whole available RAM is used. The core memory is made
- *          available to the heap allocator and/or can be used directly through
- *          the simplified core memory allocator.
- *
- * @note    In order to let the OS manage the whole RAM the linker script must
- *          provide the @p __heap_base__ and @p __heap_end__ symbols.
- * @note    Requires @p CH_USE_MEMCORE.
- */
-#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
-#define CH_MEMCORE_SIZE                 0
-#endif
-
-/**
- * @brief   Idle thread automatic spawn suppression.
- * @details When this option is activated the function @p chSysInit()
- *          does not spawn the idle thread automatically. The application has
- *          then the responsibility to do one of the following:
- *          - Spawn a custom idle thread at priority @p IDLEPRIO.
- *          - Change the main() thread priority to @p IDLEPRIO then enter
- *            an endless loop. In this scenario the @p main() thread acts as
- *            the idle thread.
- *          .
- * @note    Unless an idle thread is spawned the @p main() thread must not
- *          enter a sleep state.
- */
-#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
-#define CH_NO_IDLE_THREAD               FALSE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name Performance options
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   OS optimization.
- * @details If enabled then time efficient rather than space efficient code
- *          is used when two possible implementations exist.
- *
- * @note    This is not related to the compiler optimization options.
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
-#define CH_OPTIMIZE_SPEED               TRUE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name Subsystem options
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Threads registry APIs.
- * @details If enabled then the registry APIs are included in the kernel.
- *
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
-#define CH_USE_REGISTRY                 TRUE
-#endif
-
-/**
- * @brief   Threads synchronization APIs.
- * @details If enabled then the @p chThdWait() function is included in
- *          the kernel.
- *
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
-#define CH_USE_WAITEXIT                 TRUE
-#endif
-
-/**
- * @brief   Semaphores APIs.
- * @details If enabled then the Semaphores APIs are included in the kernel.
- *
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
-#define CH_USE_SEMAPHORES               TRUE
-#endif
-
-/**
- * @brief   Semaphores queuing mode.
- * @details If enabled then the threads are enqueued on semaphores by
- *          priority rather than in FIFO order.
- *
- * @note    The default is @p FALSE. Enable this if you have special requirements.
- * @note    Requires @p CH_USE_SEMAPHORES.
- */
-#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
-#define CH_USE_SEMAPHORES_PRIORITY      FALSE
-#endif
-
-/**
- * @brief   Atomic semaphore API.
- * @details If enabled then the semaphores the @p chSemSignalWait() API
- *          is included in the kernel.
- *
- * @note    The default is @p TRUE.
- * @note    Requires @p CH_USE_SEMAPHORES.
- */
-#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
-#define CH_USE_SEMSW                    TRUE
-#endif
-
-/**
- * @brief   Mutexes APIs.
- * @details If enabled then the mutexes APIs are included in the kernel.
- *
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
-#define CH_USE_MUTEXES                  TRUE
-#endif
-
-/**
- * @brief   Conditional Variables APIs.
- * @details If enabled then the conditional variables APIs are included
- *          in the kernel.
- *
- * @note    The default is @p TRUE.
- * @note    Requires @p CH_USE_MUTEXES.
- */
-#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
-#define CH_USE_CONDVARS                 TRUE
-#endif
-
-/**
- * @brief   Conditional Variables APIs with timeout.
- * @details If enabled then the conditional variables APIs with timeout
- *          specification are included in the kernel.
- *
- * @note    The default is @p TRUE.
- * @note    Requires @p CH_USE_CONDVARS.
- */
-#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
-#define CH_USE_CONDVARS_TIMEOUT         TRUE
-#endif
-
-/**
- * @brief   Events Flags APIs.
- * @details If enabled then the event flags APIs are included in the kernel.
- *
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
-#define CH_USE_EVENTS                   TRUE
-#endif
-
-/**
- * @brief   Events Flags APIs with timeout.
- * @details If enabled then the events APIs with timeout specification
- *          are included in the kernel.
- *
- * @note    The default is @p TRUE.
- * @note    Requires @p CH_USE_EVENTS.
- */
-#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
-#define CH_USE_EVENTS_TIMEOUT           TRUE
-#endif
-
-/**
- * @brief   Synchronous Messages APIs.
- * @details If enabled then the synchronous messages APIs are included
- *          in the kernel.
- *
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
-#define CH_USE_MESSAGES                 TRUE
-#endif
-
-/**
- * @brief   Synchronous Messages queuing mode.
- * @details If enabled then messages are served by priority rather than in
- *          FIFO order.
- *
- * @note    The default is @p FALSE. Enable this if you have special requirements.
- * @note    Requires @p CH_USE_MESSAGES.
- */
-#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
-#define CH_USE_MESSAGES_PRIORITY        FALSE
-#endif
-
-/**
- * @brief   Mailboxes APIs.
- * @details If enabled then the asynchronous messages (mailboxes) APIs are
- *          included in the kernel.
- *
- * @note    The default is @p TRUE.
- * @note    Requires @p CH_USE_SEMAPHORES.
- */
-#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
-#define CH_USE_MAILBOXES                TRUE
-#endif
-
-/**
- * @brief   I/O Queues APIs.
- * @details If enabled then the I/O queues APIs are included in the kernel.
- *
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
-#define CH_USE_QUEUES                   TRUE
-#endif
-
-/**
- * @brief   Core Memory Manager APIs.
- * @details If enabled then the core memory manager APIs are included
- *          in the kernel.
- *
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
-#define CH_USE_MEMCORE                  TRUE
-#endif
-
-/**
- * @brief   Heap Allocator APIs.
- * @details If enabled then the memory heap allocator APIs are included
- *          in the kernel.
- *
- * @note    The default is @p TRUE.
- * @note    Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
- *          @p CH_USE_SEMAPHORES.
- * @note    Mutexes are recommended.
- */
-#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
-#define CH_USE_HEAP                     TRUE
-#endif
-
-/**
- * @brief   C-runtime allocator.
- * @details If enabled the the heap allocator APIs just wrap the C-runtime
- *          @p malloc() and @p free() functions.
- *
- * @note    The default is @p FALSE.
- * @note    Requires @p CH_USE_HEAP.
- * @note    The C-runtime may or may not require @p CH_USE_MEMCORE, see the
- *          appropriate documentation.
- */
-#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
-#define CH_USE_MALLOC_HEAP              FALSE
-#endif
-
-/**
- * @brief   Memory Pools Allocator APIs.
- * @details If enabled then the memory pools allocator APIs are included
- *          in the kernel.
- *
- * @note    The default is @p TRUE.
- */
-#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
-#define CH_USE_MEMPOOLS                 TRUE
-#endif
-
-/**
- * @brief   Dynamic Threads APIs.
- * @details If enabled then the dynamic threads creation APIs are included
- *          in the kernel.
- *
- * @note    The default is @p TRUE.
- * @note    Requires @p CH_USE_WAITEXIT.
- * @note    Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
- */
-#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
-#define CH_USE_DYNAMIC                  TRUE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name Debug options
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Debug option, system state check.
- * @details If enabled the correct call protocol for system APIs is checked
- *          at runtime.
- *
- * @note    The default is @p FALSE.
- */
-#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK       FALSE
-#endif
-
-/**
- * @brief   Debug option, parameters checks.
- * @details If enabled then the checks on the API functions input
- *          parameters are activated.
- *
- * @note    The default is @p FALSE.
- */
-#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS            FALSE
-#endif
-
-/**
- * @brief   Debug option, consistency checks.
- * @details If enabled then all the assertions in the kernel code are
- *          activated. This includes consistency checks inside the kernel,
- *          runtime anomalies and port-defined checks.
- *
- * @note    The default is @p FALSE.
- */
-#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS           FALSE
-#endif
-
-/**
- * @brief   Debug option, trace buffer.
- * @details If enabled then the context switch circular trace buffer is
- *          activated.
- *
- * @note    The default is @p FALSE.
- */
-#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE             FALSE
-#endif
-
-/**
- * @brief   Debug option, stack checks.
- * @details If enabled then a runtime stack check is performed.
- *
- * @note    The default is @p FALSE.
- * @note    The stack check is performed in a architecture/port dependent way.
- *          It may not be implemented or some ports.
- * @note    The default failure mode is to halt the system with the global
- *          @p panic_msg variable set to @p NULL.
- */
-#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK       FALSE
-#endif
-
-/**
- * @brief   Debug option, stacks initialization.
- * @details If enabled then the threads working area is filled with a byte
- *          value when a thread is created. This can be useful for the
- *          runtime measurement of the used stack.
- *
- * @note    The default is @p FALSE.
- */
-#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS             FALSE
-#endif
-
-/**
- * @brief   Debug option, threads profiling.
- * @details If enabled then a field is added to the @p Thread structure that
- *          counts the system ticks occurred while executing the thread.
- *
- * @note    The default is @p TRUE.
- * @note    This debug option is defaulted to TRUE because it is required by
- *          some test cases into the test suite.
- */
-#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
-#define CH_DBG_THREADS_PROFILING        TRUE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name Kernel hooks
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Threads descriptor structure extension.
- * @details User fields added to the end of the @p Thread structure.
- */
-#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
-#define THREAD_EXT_FIELDS                                                   \
-  /* Add threads custom fields here.*/
-#endif
-
-/**
- * @brief   Threads initialization hook.
- * @details User initialization code added to the @p chThdInit() API.
- *
- * @note    It is invoked from within @p chThdInit() and implicitly from all
- *          the threads creation APIs.
- */
-#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
-#define THREAD_EXT_INIT_HOOK(tp) {                                          \
-  /* Add threads initialization code here.*/                                \
-}
-#endif
-
-/**
- * @brief   Threads finalization hook.
- * @details User finalization code added to the @p chThdExit() API.
- *
- * @note    It is inserted into lock zone.
- * @note    It is also invoked when the threads simply return in order to
- *          terminate.
- */
-#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
-#define THREAD_EXT_EXIT_HOOK(tp) {                                          \
-  /* Add threads finalization code here.*/                                  \
-}
-#endif
-
-/**
- * @brief   Context switch hook.
- * @details This hook is invoked just before switching between threads.
- */
-#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
-#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
-  /* System halt code here.*/                                               \
-}
-#endif
-
-/**
- * @brief   Idle Loop hook.
- * @details This hook is continuously invoked by the idle thread loop.
- */
-#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
-#define IDLE_LOOP_HOOK() {                                                  \
-  /* Idle loop code here.*/                                                 \
-}
-#endif
-
-/**
- * @brief   System tick event hook.
- * @details This hook is invoked in the system tick handler immediately
- *          after processing the virtual timers queue.
- */
-#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
-#define SYSTEM_TICK_EVENT_HOOK() {                                          \
-  /* System tick event code here.*/                                         \
-}
-#endif
-
-/**
- * @brief   System halt hook.
- * @details This hook is invoked in case to a system halting error before
- *          the system is halted.
- */
-#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
-#define SYSTEM_HALT_HOOK() {                                                \
-  /* System halt code here.*/                                               \
-}
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Port-specific settings (override port settings defaulted in chcore.h).    */
-/*===========================================================================*/
-
-#endif  /* _CHCONF_H_ */
-
-/** @} */
diff --git a/os/kernel/templates/chcore.c b/os/kernel/templates/chcore.c
deleted file mode 100644
index 7639d9dd7..000000000
--- a/os/kernel/templates/chcore.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    templates/chcore.c
- * @brief   Port related template code.
- * @details This file is a template of the system driver functions provided by
- *          a port. Some of the following functions may be implemented as
- *          macros in chcore.h if the implementer decides that there is an
- *          advantage in doing so, for example because performance concerns.
- *
- * @addtogroup core
- * @details Non portable code templates.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Port-related initialization code.
- * @note    This function is usually empty.
- */
-void port_init(void) {
-}
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform more
- *          actions.
- */
-void port_lock(void) {
-}
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform more
- *          actions.
- */
-void port_unlock(void) {
-}
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependent,
- *          in its simplest form it is void.
- */
-void port_lock_from_isr(void) {
-}
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- */
-void port_unlock_from_isr(void) {
-}
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Of course non-maskable interrupt sources are not included.
- */
-void port_disable(void) {
-}
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- * @note    Interrupt sources above kernel level remains enabled.
- */
-void port_suspend(void) {
-}
-
-/**
- * @brief   Enables all the interrupt sources.
- */
-void port_enable(void) {
-}
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- */
-void port_wait_for_interrupt(void) {
-}
-
-/**
- * @brief   Halts the system.
- * @details This function is invoked by the operating system when an
- *          unrecoverable error is detected (for example because a programming
- *          error in the application code that triggers an assertion while in
- *          debug mode).
- */
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-void port_switch(Thread *ntp, Thread *otp) {
-}
-
-/** @} */
diff --git a/os/kernel/templates/chcore.h b/os/kernel/templates/chcore.h
deleted file mode 100644
index f73b3b0c8..000000000
--- a/os/kernel/templates/chcore.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    templates/chcore.h
- * @brief   Port related template macros and structures.
- * @details This file is a template of the system driver macros provided by
- *          a port.
- *
- * @addtogroup core
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-/*===========================================================================*/
-/* Port constants.                                                           */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port macros.                                                              */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     0
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- *          This value can be zero on those architecture where there is a
- *          separate interrupt stack and the stack space between @p intctx and
- *          @p extctx is known to be zero.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK         0
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters.                                                  */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Unique macro for the implemented architecture.
- */
-#define CH_ARCHITECTURE_XXX
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            ""
-
-/**
- * @brief   Name of the architecture variant (optional).
- */
-#define CH_ARCHITECTURE_VARIANT_NAME    ""
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "GCC"
-
-/**
- * @brief   Port-specific information string.
- */
-#define CH_PORT_INFO                    ""
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Base type for stack and memory alignment.
- */
-typedef uint8_t stkalign_t;
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- */
-struct extctx {
-};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching.
- */
-struct intctx {
-};
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details This structure usually contains just the saved stack pointer
- *          defined as a pointer to a @p intctx structure.
- */
-struct context {
-  struct intctx *sp;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-}
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE()
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Fast IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- * @note    Not all architectures support fast interrupts, in this case this
- *          macro must be omitted.
- */
-#define PORT_FAST_IRQ_HANDLER(id) void id(void)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_init(void);
-  void port_lock(void);
-  void port_unlock(void);
-  void port_lock_from_isr(void);
-  void port_unlock_from_isr(void);
-  void port_disable(void);
-  void port_suspend(void);
-  void port_enable(void);
-  void port_wait_for_interrupt(void);
-  void port_halt(void);
-  void port_switch(Thread *ntp, Thread *otp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/kernel/templates/chtypes.h b/os/kernel/templates/chtypes.h
deleted file mode 100644
index 52efee447..000000000
--- a/os/kernel/templates/chtypes.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    templates/chtypes.h
- * @brief   System types template.
- * @details The types defined in this file may change depending on the target
- *          architecture. You may also try to optimize the size of the various
- *          types in order to privilege size or performance, be careful in
- *          doing so.
- *
- * @addtogroup types
- * @details System types and macros.
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#define __need_NULL
-#define __need_size_t
-#include <stddef.h>
-
-#if !defined(_STDINT_H) && !defined(__STDINT_H_)
-#include <stdint.h>
-#endif
-
-/**
- * @brief   Boolean, recommended the fastest signed.
- */
-typedef int32_t         bool_t;
-
-/**
- * @brief   Thread mode flags, uint8_t is ok.
- */
-typedef uint8_t         tmode_t;
-
-/**
- * @brief   Thread state, uint8_t is ok.
- */
-typedef uint8_t         tstate_t;
-
-/**
- * @brief   Thread references counter, uint8_t is ok.
- */
-typedef uint8_t         trefs_t;
-
-/**
- * @brief   Priority, use the fastest unsigned type.
- */
-typedef uint32_t        tprio_t;
-
-/**
- * @brief   Message, use signed pointer equivalent.
- */
-typedef int32_t         msg_t;
-
-/**
- * @brief   Event Id, use fastest signed.
- */
-typedef int32_t         eventid_t;
-
-/**
- * @brief   Event Mask, recommended fastest unsigned.
- */
-typedef uint32_t        eventmask_t;
-
-/**
- * @brief   System Time, recommended fastest unsigned.
- */
-typedef uint32_t        systime_t;
-
-/**
- * @brief   Counter, recommended fastest signed.
- */
-typedef int32_t         cnt_t;
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    This is required because some compilers require a custom keyword,
- *          usually this macro is just set to "const" for the GCC compiler.
- * @note    This macro is not used to place constants in different address
- *          spaces (like AVR requires for example) because it is assumed that
- *          a pointer to a ROMCONST constant is compatible with a pointer
- *          to a normal variable. It is just like the "const" keyword but
- *          requires that the constant is placed in ROM if the architecture
- *          supports it.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief   Packed structure modifier (before).
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/nil/include/nil.h b/os/nil/include/nil.h
new file mode 100644
index 000000000..161c79a6d
--- /dev/null
+++ b/os/nil/include/nil.h
@@ -0,0 +1,819 @@
+/*
+    Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio.
+
+    This file is part of Nil RTOS.
+
+    Nil RTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    Nil RTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    nil.h
+ * @brief   Nil RTOS main header file.
+ * @details This header includes all the required kernel headers so it is the
+ *          only header you usually need to include in your application.
+ *
+ * @addtogroup nil
+ * @{
+ */
+
+#ifndef _NIL_H_
+#define _NIL_H_
+
+typedef struct nil_thread thread_t;
+
+#include "nilconf.h"
+#include "niltypes.h"
+#include "nilcore.h"
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Nil RTOS identification
+ * @{
+ */
+#define _NIL_                           /**< @brief Nil RTOS identification.*/
+
+#define CH_KERNEL_VERSION      "0.1.0alpha"
+
+#define CH_KERNEL_MAJOR        0
+#define CH_KERNEL_MINOR        1
+#define CH_KERNEL_PATCH        0
+/** @} */
+
+/**
+ * @name    Wakeup messages
+ * @{
+ */
+#define MSG_OK                  0   /**< @brief Normal wakeup message.      */
+#define MSG_TIMEOUT             -1  /**< @brief Wake-up caused by a timeout
+                                         condition.                         */
+#define MSG_RESET               -2  /**< @brief Wake-up caused by a reset
+                                         condition.                         */
+/** @} */
+
+/**
+ * @name    Special time constants
+ * @{
+ */
+/**
+ * @brief   Zero time specification for some functions with a timeout
+ *          specification.
+ * @note    Not all functions accept @p TIME_IMMEDIATE as timeout parameter,
+ *          see the specific function documentation.
+ */
+#define TIME_IMMEDIATE          ((systime_t)-1)
+
+/**
+ * @brief   Infinite time specification for all functions with a timeout
+ *          specification.
+ */
+#define TIME_INFINITE           ((systime_t)0)
+/** @} */
+
+/**
+ * @name    Thread state related macros
+ * @{
+ */
+#define NIL_STATE_READY         0   /**< @brief Thread ready or executing.  */
+#define NIL_STATE_SLEEPING      1   /**< @brief Thread sleeping.            */
+#define NIL_STATE_SUSP          2   /**< @brief Thread suspended.           */
+#define NIL_STATE_WTSEM         3   /**< @brief Thread waiting on semaphore.*/
+#define NIL_STATE_WTOREVT       4   /**< @brief Thread waiting for events.  */
+#define NIL_THD_IS_READY(tr)    ((tr)->state == NIL_STATE_READY)
+#define NIL_THD_IS_SLEEPING(tr) ((tr)->state == NIL_STATE_SLEEPING)
+#define NIL_THD_IS_SUSP(tr)     ((tr)->state == NIL_STATE_SUSP)
+#define NIL_THD_IS_WTSEM(tr)    ((tr)->state == NIL_STATE_WTSEM)
+#define NIL_THD_IS_WTOREVT(tr)  ((tr)->state == NIL_STATE_WTOREVT)
+/** @} */
+
+/**
+ * @name    Events related macros
+ * @{
+ */
+/**
+ * @brief   All events allowed mask.
+ */
+#define ALL_EVENTS              ((eventmask_t)-1)
+
+/**
+ * @brief   Returns an event mask from an event identifier.
+ */
+#define EVENT_MASK(eid)         ((eventmask_t)(1 << (eid)))
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of user threads in the application.
+ * @note    This number is not inclusive of the idle thread which is
+ *          implicitly handled.
+ */
+#if !defined(NIL_CFG_NUM_THREADS) || defined(__DOXYGEN__)
+#define NIL_CFG_NUM_THREADS                 2
+#endif
+
+/**
+ * @brief   System time counter resolution.
+ * @note    Allowed values are 16 or 32 bits.
+ */
+#if !defined(NIL_CFG_ST_RESOLUTION) || defined(__DOXYGEN__)
+#define NIL_CFG_ST_RESOLUTION               32
+#endif
+
+/**
+ * @brief   System tick frequency.
+ * @note    This value together with the @p NIL_CFG_ST_RESOLUTION
+ *          option defines the maximum amount of time allowed for
+ *          timeouts.
+ */
+#if !defined(NIL_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
+#define NIL_CFG_ST_FREQUENCY                100
+#endif
+
+/**
+ * @brief   Time delta constant for the tick-less mode.
+ * @note    If this value is zero then the system uses the classic
+ *          periodic tick. This value represents the minimum number
+ *          of ticks that is safe to specify in a timeout directive.
+ *          The value one is not valid, timeouts are rounded up to
+ *          this value.
+ */
+#if !defined(NIL_CFG_ST_TIMEDELTA) || defined(__DOXYGEN__)
+#define NIL_CFG_ST_TIMEDELTA                0
+#endif
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(NIL_CFG_USE_EVENTS) || defined(__DOXYGEN__)
+#define NIL_CFG_USE_EVENTS                  TRUE
+#endif
+
+/**
+ * @brief   System assertions.
+ */
+#if !defined(NIL_CFG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define NIL_CFG_ENABLE_ASSERTS              FALSE
+#endif
+
+/**
+ * @brief   Stack check.
+ */
+#if !defined(NIL_CFG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define NIL_CFG_ENABLE_STACK_CHECK          FALSE
+#endif
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#if !defined(NIL_CFG_THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define NIL_CFG_THREAD_EXT_FIELDS
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if NIL_CFG_NUM_THREADS < 1
+#error "at least one thread must be defined"
+#endif
+
+#if NIL_CFG_NUM_THREADS > 12
+#error "Nil is not recommended for thread-intensive applications, consider" \
+       "ChibiOS/RT instead"
+#endif
+
+#if (NIL_CFG_ST_RESOLUTION != 16) && (NIL_CFG_ST_RESOLUTION != 32)
+#error "invalid NIL_CFG_ST_RESOLUTION specified, must be 16 or 32"
+#endif
+
+#if NIL_CFG_ST_FREQUENCY <= 0
+#error "invalid NIL_CFG_ST_FREQUENCY specified, must be greated than zero"
+#endif
+
+#if (NIL_CFG_ST_TIMEDELTA < 0) || (NIL_CFG_ST_TIMEDELTA == 1)
+#error "invalid NIL_CFG_ST_TIMEDELTA specified, must "                      \
+       "be zero or greater than one"
+#endif
+
+#if NIL_CFG_ENABLE_ASSERTS
+#define NIL_DBG_ENABLED                 TRUE
+#else
+#define NIL_DBG_ENABLED                 FALSE
+#endif
+
+/** Boundaries of the idle thread boundaries, only required if stack checking
+    is enabled.*/
+#if NIL_CFG_ENABLE_STACK_CHECK
+extern stkalign_t __main_thread_stack_base__, __main_thread_stack_end__;
+
+#define THD_IDLE_BASE                   (&__main_thread_stack_base__)
+#define THD_IDLE_END                    (&__main_thread_stack_end__)
+#else
+#define THD_IDLE_BASE                   NULL
+#define THD_IDLE_END                    NULL
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of internal context structure.
+ */
+typedef struct port_intctx intctx_t;
+
+/**
+ * @brief   Type of a structure representing a counting semaphore.
+ */
+typedef struct {
+  volatile cnt_t    cnt;        /**< @brief Semaphore counter.              */
+} semaphore_t;
+
+/**
+ * @brief Thread function.
+ */
+typedef void (*tfunc_t)(void *);
+
+/**
+ * @brief   Type of a structure representing a thread static configuration.
+ */
+typedef struct nil_thread_cfg thread_config_t;
+
+/**
+ * @brief   Type of a structure representing a thread.
+ */
+typedef struct nil_thread thread_t;
+
+/**
+ * @brief   Structure representing a thread static configuration.
+ */
+struct nil_thread_cfg {
+  stkalign_t        *wbase;     /**< @brief Thread working area base.       */
+  stkalign_t        *wend;      /**< @brief Thread working area end.        */
+  const char        *namep;     /**< @brief Thread name, for debugging.     */
+  tfunc_t           funcp;      /**< @brief Thread function.                */
+  void              *arg;       /**< @brief Thread function argument.       */
+};
+
+/**
+ * @brief   Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+
+/**
+ * @brief   Structure representing a thread.
+ */
+struct nil_thread {
+  intctx_t              *ctxp;  /**< @brief Pointer to internal context.    */
+  tstate_t              state;  /**< @brief Thread state.                   */
+  /* Note, the following union contains a pointer while the thread is in a
+     sleeping state (!NIL_THD_IS_READY()) else contains the wake-up message.*/
+  union {
+    msg_t               msg;    /**< @brief Wake-up message.                */
+    void                *p;     /**< @brief Generic pointer.                */
+    thread_reference_t  *trp;   /**< @brief Pointer to thread reference.    */
+    semaphore_t         *semp;  /**< @brief Pointer to semaphore.           */
+#if NIL_CFG_USE_EVENTS
+    eventmask_t         ewmask; /**< @brief Enabled events mask.            */
+#endif
+  } u1;
+  volatile systime_t    timeout;/**< @brief Timeout counter, zero
+                                            if disabled.                    */
+#if NIL_CFG_USE_EVENTS
+  eventmask_t           epmask; /**< @brief Pending events mask.            */
+#endif
+#if NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+  stkalign_t            *stklim;/**< @brief Thread stack boundary.          */
+#endif
+  /* Optional extra fields.*/
+  NIL_CFG_THREAD_EXT_FIELDS
+};
+
+/**
+ * @brief   System data structure.
+ * @note    This structure contain all the data areas used by the OS except
+ *          stacks.
+ */
+typedef struct {
+  /**
+   * @brief   Pointer to the running thread.
+   */
+  thread_t              *current;
+  /**
+   * @brief   Pointer to the next thread to be executed.
+   * @note    This pointer must point at the same thread pointed by @p currp
+   *          or to an higher priority thread if a switch is required.
+   */
+  thread_t              *next;
+#if NIL_CFG_ST_TIMEDELTA == 0 || defined(__DOXYGEN__)
+  /**
+   * @brief   System time.
+   */
+  systime_t             systime;
+#endif
+#if NIL_CFG_ST_TIMEDELTA > 0 || defined(__DOXYGEN__)
+  /**
+   * @brief   System time of the last tick event.
+   */
+  systime_t             lasttime;
+  /**
+   * @brief   Time of the next scheduled tick event.
+   */
+  systime_t             nexttime;
+#endif
+  /**
+   * @brief   Thread structures for all the defined threads.
+   */
+  thread_t              threads[NIL_CFG_NUM_THREADS + 1];
+#if NIL_DBG_ENABLED || defined(__DOXYGEN__)
+  /**
+   * @brief   Panic message.
+   * @note    This field is only present if some debug options have been
+   *          activated.
+   */
+  const char            *dbg_panic_msg;
+#endif
+} nil_system_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Threads tables definition macros
+ * @{
+ */
+/**
+ * @brief   Start of user threads table.
+ */
+#define THD_TABLE_BEGIN                                                     \
+  const thread_config_t nil_thd_configs[NIL_CFG_NUM_THREADS + 1] = {
+
+/**
+ * @brief   Entry of user threads table
+ */
+#define THD_TABLE_ENTRY(wap, name, funcp, arg)                              \
+  {wap, (wap) + sizeof (wap), name, funcp, arg},
+
+/**
+ * @brief   End of user threads table.
+ */
+#define THD_TABLE_END                                                       \
+  {THD_IDLE_BASE, THD_IDLE_END, "idle", 0, NULL}                            \
+};
+/** @} */
+
+/**
+ * @name    Working Areas and Alignment
+ */
+/**
+ * @brief   Enforces a correct alignment for a stack area size value.
+ *
+ * @param[in] n         the stack size to be aligned to the next stack
+ *                      alignment boundary
+ * @return              The aligned stack size.
+ *
+ * @api
+ */
+#define THD_ALIGN_STACK_SIZE(n)                                             \
+  ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
+
+/**
+ * @brief   Calculates the total Working Area size.
+ *
+ * @param[in] n         the stack size to be assigned to the thread
+ * @return              The total used memory in bytes.
+ *
+ * @api
+ */
+#define THD_WORKING_AREA_SIZE(n)                                            \
+  THD_ALIGN_STACK_SIZE(sizeof(thread_t) + PORT_WA_SIZE(n))
+
+/**
+ * @brief   Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ *          aligned as both position and size.
+ *
+ * @param[in] s         the name to be assigned to the stack array
+ * @param[in] n         the stack size to be assigned to the thread
+ *
+ * @api
+ */
+#define THD_WORKING_AREA(s, n)                                              \
+  stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof(stkalign_t)]
+/** @} */
+
+/**
+ * @name    Threads abstraction macros
+ */
+/**
+ * @brief   Thread declaration macro.
+ * @note    Thread declarations should be performed using this macro because
+ *          the port layer could define optimizations for thread functions.
+ */
+#define THD_FUNCTION(tname, arg) PORT_THD_FUNCTION(tname, arg)
+/** @} */
+
+/**
+ * @name    ISRs abstraction macros
+ */
+/**
+ * @brief   IRQ handler enter code.
+ * @note    Usually IRQ handlers functions are also declared naked.
+ * @note    On some architectures this macro can be empty.
+ *
+ * @special
+ */
+#define CH_IRQ_PROLOGUE() PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief   IRQ handler exit code.
+ * @note    Usually IRQ handlers function are also declared naked.
+ *
+ * @special
+ */
+#define CH_IRQ_EPILOGUE() PORT_IRQ_EPILOGUE()
+
+/**
+ * @brief   Standard normal IRQ handler declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ *
+ * @special
+ */
+#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name    Fast ISRs abstraction macros
+ */
+/**
+ * @brief   Standard fast IRQ handler declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ * @note    Not all architectures support fast interrupts.
+ *
+ * @special
+ */
+#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name    Time conversion utilities
+ * @{
+ */
+/**
+ * @brief   Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec       number of seconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define S2ST(sec)                                                           \
+  ((systime_t)((sec) * NIL_CFG_ST_FREQUENCY))
+
+/**
+ * @brief   Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec      number of milliseconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define MS2ST(msec)                                                         \
+  ((systime_t)(((((uint32_t)(msec)) *                                       \
+                 ((uint32_t)NIL_CFG_ST_FREQUENCY) - 1UL) / 1000UL) + 1UL))
+
+/**
+ * @brief   Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec      number of microseconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define US2ST(usec)                                                         \
+  ((systime_t)(((((uint32_t)(usec)) *                                       \
+                 ((uint32_t)NIL_CFG_ST_FREQUENCY) - 1UL) / 1000000UL) + 1UL))
+/** @} */
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Enters the kernel lock mode.
+ *
+ * @special
+ */
+#define chSysDisable() port_disable()
+
+/**
+ * @brief   Enters the kernel lock mode.
+ *
+ * @special
+ */
+#define chSysEnable() port_enable()
+
+/**
+ * @brief   Enters the kernel lock mode.
+ *
+ * @special
+ */
+#define chSysLock() port_lock()
+
+/**
+ * @brief   Leaves the kernel lock mode.
+ *
+ * @special
+ */
+#define chSysUnlock() port_unlock()
+
+/**
+ * @brief   Enters the kernel lock mode from within an interrupt handler.
+ * @note    This API may do nothing on some architectures, it is required
+ *          because on ports that support preemptable interrupt handlers
+ *          it is required to raise the interrupt mask to the same level of
+ *          the system mutual exclusion zone.<br>
+ *          It is good practice to invoke this API before invoking any I-class
+ *          syscall from an interrupt handler.
+ * @note    This API must be invoked exclusively from interrupt handlers.
+ *
+ * @special
+ */
+#define chSysLockFromISR() port_lock_from_isr()
+
+/**
+ * @brief   Leaves the kernel lock mode from within an interrupt handler.
+ *
+ * @note    This API may do nothing on some architectures, it is required
+ *          because on ports that support preemptable interrupt handlers
+ *          it is required to raise the interrupt mask to the same level of
+ *          the system mutual exclusion zone.<br>
+ *          It is good practice to invoke this API after invoking any I-class
+ *          syscall from an interrupt handler.
+ * @note    This API must be invoked exclusively from interrupt handlers.
+ *
+ * @special
+ */
+#define chSysUnlockFromISR() port_unlock_from_isr()
+
+/**
+ * @brief   Evaluates if a reschedule is required.
+ *
+ * @retval true         if there is a thread that must go in running state
+ *                      immediately.
+ * @retval false        if preemption is not required.
+ *
+ * @iclass
+ */
+#define chSchIsRescRequiredI() ((bool)(nil.current != nil.next))
+
+/**
+ * @brief   Returns a pointer to the current @p thread_t.
+ *
+ * @xclass
+ */
+#define chThdGetSelfX() nil.current
+
+/**
+ * @brief   Delays the invoking thread for the specified number of seconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system clock.
+ * @note    The maximum specified value is implementation dependent.
+ *
+ * @param[in] sec       time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec))
+
+/**
+ * @brief   Delays the invoking thread for the specified number of
+ *          milliseconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system clock.
+ * @note    The maximum specified value is implementation dependent.
+ *
+ * @param[in] msec      time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec))
+
+/**
+ * @brief   Delays the invoking thread for the specified number of
+ *          microseconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system clock.
+ * @note    The maximum specified value is implementation dependent.
+ *
+ * @param[in] usec      time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec))
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] timeout   the delay in system ticks
+ *
+ * @sclass
+ */
+#define chThdSleepS(timeout) chSchGoSleepTimeoutS(NIL_STATE_SLEEPING, timeout)
+
+/**
+ * @brief   Suspends the invoking thread until the system time arrives to the
+ *          specified value.
+ *
+ * @param[in] time      absolute system time
+ *
+ * @sclass
+ */
+#define chThdSleepUntilS(time)                                             \
+  chSchGoSleepTimeoutS(NIL_STATE_SLEEPING, (time) - chVTGetSystemTimeX())
+
+/**
+ * @brief   Initializes a semaphore with the specified counter value.
+ *
+ * @param[out] sp       pointer to a @p semaphore_t structure
+ * @param[in] n         initial value of the semaphore counter. Must be
+ *                      non-negative.
+ *
+ * @init
+ */
+#define chSemObjectInit(sp, n) ((sp)->cnt = n)
+
+/**
+ * @brief   Performs a wait operation on a semaphore.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval CH_MSG_OK   if the thread has not stopped on the semaphore or the
+ *                      semaphore has been signaled.
+ * @retval CH_MSG_RST  if the semaphore has been reset using @p chSemReset().
+ *
+ * @api
+ */
+#define chSemWait(sp) chSemWaitTimeout(sp, TIME_INFINITE)
+
+/**
+ * @brief   Performs a wait operation on a semaphore.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval CH_MSG_OK   if the thread has not stopped on the semaphore or the
+ *                      semaphore has been signaled.
+ * @retval CH_MSG_RST  if the semaphore has been reset using @p chSemReset().
+ *
+ * @sclass
+ */
+#define chSemWaitS(sp) chSemWaitTimeoutS(sp, TIME_INFINITE)
+
+/**
+ * @brief   Returns the semaphore counter current value.
+ *
+ * @iclass
+ */
+#define chSemGetCounterI(sp) ((sp)->cnt)
+
+/**
+ * @brief   Current system time.
+ * @details Returns the number of system ticks since the @p chSysInit()
+ *          invocation.
+ * @note    The counter can reach its maximum and then restart from zero.
+ * @note    This function can be called from any context but its atomicity
+ *          is not guaranteed on architectures whose word size is less than
+ *          @systime_t size.
+ *
+ * @return              The system time in ticks.
+ *
+ * @xclass
+ */
+#if NIL_CFG_ST_TIMEDELTA == 0 || defined(__DOXYGEN__)
+#define chVTGetSystemTimeX() (nil.systime)
+#else
+#define chVTGetSystemTimeX() port_timer_get_time()
+#endif
+
+/**
+ * @brief   Returns the elapsed time since the specified start time.
+ *
+ * @param[in] start     start time
+ * @return              The elapsed time.
+ *
+ * @xclass
+ */
+#define chVTTimeElapsedSinceX(start)                                        \
+  ((systime_t)(chVTGetSystemTimeX() - start))
+
+/**
+ * @brief   Checks if the specified time is within the specified time window.
+ * @note    When start==end then the function returns always true because the
+ *          whole time range is specified.
+ * @note    This function can be called from any context.
+ *
+ * @param[in] time      the time to be verified
+ * @param[in] start     the start of the time window (inclusive)
+ * @param[in] end       the end of the time window (non inclusive)
+ * @retval true         current time within the specified time window.
+ * @retval false        current time not within the specified time window.
+ *
+ * @xclass
+ */
+#define chVTIsTimeWithinX(time, start, end)                                 \
+  ((bool)((time) - (start) < (end) - (start)))
+
+/**
+ * @brief   Condition assertion.
+ * @details If the condition check fails then the kernel panics with a
+ *          message and halts.
+ * @note    The condition is tested only if the @p NIL_CFG_ENABLE_ASSERTS
+ *          switch is specified in @p nilconf.h else the macro does nothing.
+ * @note    The remark string is not currently used except for putting a
+ *          comment in the code about the assertion.
+ *
+ * @param[in] c         the condition to be verified to be true
+ * @param[in] r         a remark string
+ *
+ * @api
+ */
+#if !defined(chDbgAssert)
+#define chDbgAssert(c, r) do {                                              \
+  if (NIL_CFG_ENABLE_ASSERTS && !(c))                                       \
+    chSysHalt(__func__);                                                    \
+} while (0)
+#endif /* !defined(chDbgAssert) */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern nil_system_t nil;
+extern const thread_config_t nil_thd_configs[NIL_CFG_NUM_THREADS + 1];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chSysInit(void);
+  void chSysHalt(const char *reason);
+  void chSysTimerHandlerI(void);
+  syssts_t chSysGetStatusAndLockX(void);
+  void chSysRestoreStatusX(syssts_t sts);
+  thread_t *chSchReadyI(thread_t *tp, msg_t msg);
+  void chSchRescheduleS(void);
+  msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t timeout);
+  msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout);
+  void chThdResumeI(thread_reference_t *trp, msg_t msg);
+  void chThdSleep(systime_t time);
+  void chThdSleepUntil(systime_t time);
+  msg_t chSemWaitTimeout(semaphore_t *sp, systime_t time);
+  msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t time);
+  void chSemSignal(semaphore_t *sp);
+  void chSemSignalI(semaphore_t *sp);
+  void chSemReset(semaphore_t *sp, cnt_t n);
+  void chSemResetI(semaphore_t *sp, cnt_t n);
+  void chEvtSignal(thread_t *tp, eventmask_t mask);
+  void chEvtSignalI(thread_t *tp, eventmask_t mask);
+  eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t timeout);
+  eventmask_t chEvtWaitAnyTimeoutS(eventmask_t mask, systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _NIL_H_ */
+
+/** @} */
diff --git a/os/nil/nil.mk b/os/nil/nil.mk
new file mode 100644
index 000000000..51f0e8083
--- /dev/null
+++ b/os/nil/nil.mk
@@ -0,0 +1,5 @@
+# List of all the ChibiOS/NIL kernel files.
+KERNSRC = ${CHIBIOS}/os/nil/src/nil.c
+
+# Required include directories
+KERNINC = ${CHIBIOS}/os/nil/include
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f0xx.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f0xx.mk
new file mode 100644
index 000000000..6e63c076c
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f0xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/NIL Cortex-M0 STM32F0xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v6m.c
+          
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F0xx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk
new file mode 100644
index 000000000..742053e48
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/NIL Cortex-M3 STM32F1xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F1xx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
new file mode 100644
index 000000000..18df7e0a9
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/NIL Cortex-M4 STM32F30x port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F30x \
+          ${CHIBIOS}/os/nil/ports/ARMCMx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
new file mode 100644
index 000000000..710062615
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/NIL Cortex-M4 STM32F37x port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F37x \
+          ${CHIBIOS}/os/nil/ports/ARMCMx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk
new file mode 100644
index 000000000..6dacde089
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/NIL Cortex-M0 STM32F4xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v6m.c
+          
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F4xx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32l1xx.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32l1xx.mk
new file mode 100644
index 000000000..12894b1c0
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32l1xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/NIL Cortex-M4 STM32L1xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32L1xx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
new file mode 100644
index 000000000..d824fd260
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
@@ -0,0 +1,122 @@
+/*
+    ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/NIL.
+
+    ChibiOS/NIL is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/NIL is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/compilers/GCC/nilcoreasm_v6m.s
+ * @brief   ARMv6-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "nilconf.h"
+#include "nilcore.h"
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE   0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE    1
+#endif
+
+#if !defined(__DOXYGEN__)
+
+                .set    CONTEXT_OFFSET, 0
+                .set    SCB_ICSR, 0xE000ED04
+                .set    ICSR_PENDSVSET, 0x10000000
+                .set    ICSR_NMIPENDSET, 0x80000000
+
+                .cpu    cortex-m0
+                .fpu    softvfp
+
+                .thumb
+                .text
+
+/*--------------------------------------------------------------------------*
+ * Performs a context switch between two threads.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_switch
+_port_switch:
+                push    {r4, r5, r6, r7, lr}
+                mov     r4, r8
+                mov     r5, r9
+                mov     r6, r10
+                mov     r7, r11
+                push    {r4, r5, r6, r7}
+                mov r3, sp
+                str r3, [r1, #CONTEXT_OFFSET]
+                ldr r3, [r0, #CONTEXT_OFFSET]
+                mov sp, r3
+                pop     {r4, r5, r6, r7}
+                mov     r8, r4
+                mov     r9, r5
+                mov     r10, r6
+                mov     r11, r7
+                pop     {r4, r5, r6, r7, pc}
+
+/*--------------------------------------------------------------------------*
+ * Start a thread by invoking its work function.
+ *
+ * Threads execution starts here, the code leaves the system critical zone
+ * and then jumps into the thread function passed in register R4. The
+ * register R5 contains the thread parameter. The function chThdExit() is
+ * called on thread function return.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_thread_start
+_port_thread_start:
+                cpsie   i
+                mov     r0, r5
+                blx     r4
+                mov     r3, #0
+                bl      chSysHalt
+
+/*--------------------------------------------------------------------------*
+ * Post-IRQ switch code.
+ *
+ * Exception handlers return here for context switching.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_switch_from_isr
+_port_switch_from_isr:
+                bl      chSchRescheduleS
+                .globl  _port_exit_from_isr
+_port_exit_from_isr:
+                ldr     r2, .L2
+                ldr     r3, .L3
+                str     r3, [r2, #0]
+#if CORTEX_ALTERNATE_SWITCH
+                cpsie   i
+#endif
+.L1:            b       .L1
+
+                .align  2
+.L2:            .word   SCB_ICSR
+#if CORTEX_ALTERNATE_SWITCH
+.L3:            .word   ICSR_PENDSVSET
+#else
+.L3:            .word   ICSR_NMIPENDSET
+#endif
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
new file mode 100644
index 000000000..27e5fcc9e
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
@@ -0,0 +1,120 @@
+/*
+    ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/NIL.
+
+    ChibiOS/NIL is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/NIL is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+ * @brief   ARMv7-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "nilconf.h"
+#include "nilcore.h"
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE   0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE    1
+#endif
+
+#if !defined(__DOXYGEN__)
+
+                .set    CONTEXT_OFFSET, 0
+                .set    SCB_ICSR, 0xE000ED04
+                .set    ICSR_PENDSVSET, 0x10000000
+
+                .syntax unified
+                .cpu    cortex-m4
+#if CORTEX_USE_FPU
+                .fpu    fpv4-sp-d16
+#else
+                .fpu    softvfp
+#endif
+
+                .thumb
+                .text
+
+/*--------------------------------------------------------------------------*
+ * Performs a context switch between two threads.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_switch
+_port_switch:
+                push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+#if CORTEX_USE_FPU
+                vpush   {s16-s31}
+#endif
+                str     sp, [r1, #CONTEXT_OFFSET]
+                ldr     sp, [r0, #CONTEXT_OFFSET]
+#if CORTEX_USE_FPU
+                vpop    {s16-s31}
+#endif
+                pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+
+/*--------------------------------------------------------------------------*
+ * Start a thread by invoking its work function.
+ *
+ * Threads execution starts here, the code leaves the system critical zone
+ * and then jumps into the thread function passed in register R4. The
+ * register R5 contains the thread parameter. The function chThdExit() is
+ * called on thread function return.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_thread_start
+_port_thread_start:
+#if !CORTEX_SIMPLIFIED_PRIORITY
+                movs    r3, #0
+                msr     BASEPRI, r3
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+                cpsie   i
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+                mov     r0, r5
+                blx     r4
+                mov     r3, #0
+                bl      chSysHalt
+
+/*--------------------------------------------------------------------------*
+ * Post-IRQ switch code.
+ *
+ * Exception handlers return here for context switching.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_switch_from_isr
+_port_switch_from_isr:
+                bl      chSchRescheduleS
+                .globl  _port_exit_from_isr
+_port_exit_from_isr:
+#if CORTEX_SIMPLIFIED_PRIORITY
+                movw    r3, #:lower16:SCB_ICSR
+                movt    r3, #:upper16:SCB_ICSR
+                mov     r2, ICSR_PENDSVSET
+                str     r2, [r3, #0]
+                cpsie   i
+#else /* !CORTEX_SIMPLIFIED_PRIORITY */
+                svc     #0
+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
+.L1:            b       .L1
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h b/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h
new file mode 100644
index 000000000..cb0eda2d0
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h
@@ -0,0 +1,87 @@
+/*
+    ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/NIL.
+
+    ChibiOS/NIL is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/NIL is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/compilers/GCC/niltypes.h
+ * @brief   ARM Cortex-Mx port system types.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#ifndef _NILTYPES_H_
+#define _NILTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name    Common constants
+ */
+/**
+ * @brief   Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE                   0
+#endif
+
+/**
+ * @brief   Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                    (!FALSE)
+#endif
+/** @} */
+
+typedef uint32_t        syssts_t;       /**< System status word.            */
+typedef uint32_t        rtcnt_t;        /**< Realtime counter.              */
+typedef uint8_t         tstate_t;       /**< Thread state.                  */
+typedef int32_t         msg_t;          /**< Inter-thread message.          */
+typedef uint32_t        eventmask_t;    /**< Mask of event identifiers.     */
+typedef int32_t         cnt_t;          /**< Generic signed counter.        */
+typedef uint32_t        ucnt_t;         /**< Generic unsigned counter.      */
+
+/**
+ * @brief   ROM constant modifier.
+ * @note    It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief   Makes functions not inlineable.
+ * @note    If the compiler does not support such attribute then the
+ *          realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief   Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg)                                       \
+  __attribute__((noreturn)) void tname(void *arg)
+
+/**
+ * @brief   Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+#endif /* _NILTYPES_H_ */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore.c b/os/nil/ports/ARMCMx/nilcore.c
new file mode 100644
index 000000000..58b86e76b
--- /dev/null
+++ b/os/nil/ports/ARMCMx/nilcore.c
@@ -0,0 +1,55 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/nilcore.c
+ * @brief   ARM Cortex-Mx port code.
+ *
+ * @addtogroup ARMCMx_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore.h b/os/nil/ports/ARMCMx/nilcore.h
new file mode 100644
index 000000000..60202222a
--- /dev/null
+++ b/os/nil/ports/ARMCMx/nilcore.h
@@ -0,0 +1,245 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/nilcore.h
+ * @brief   ARM Cortex-Mx port macros and structures.
+ *
+ * @addtogroup ARMCMx_CORE
+ * @{
+ */
+
+#ifndef _NILCORE_H_
+#define _NILCORE_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief   Macro defining a generic ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM
+
+/* The following code is not processed when the file is included from an
+   asm module because those intrinsic macros are not necessarily defined
+   by the assembler too.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME              "GCC " __VERSION__
+
+#elif defined(__ICCARM__)
+#define PORT_COMPILER_NAME              "IAR"
+
+#elif defined(__CC_ARM)
+#define PORT_COMPILER_NAME              "RVCT"
+
+#else
+#error "unsupported compiler"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/** @} */
+
+/**
+ * @name    Cortex-M variants
+ * @{
+ */
+#define CORTEX_M0                       0   /**< @brief Cortex-M0 variant.  */
+#define CORTEX_M0PLUS                   1   /**< @brief Cortex-M0+ variant. */
+#define CORTEX_M1                       2   /**< @brief Cortex-M1 variant.  */
+#define CORTEX_M3                       3   /**< @brief Cortex-M3 variant.  */
+#define CORTEX_M4                       4   /**< @brief Cortex-M4 variant.  */
+/** @} */
+
+/* Inclusion of the Cortex-Mx implementation specific parameters.*/
+#include "cmparams.h"
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ *          @p nilcore_timer.h, if this option is enabled then the file
+ *          @p nilcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER              FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/*
+ * Inclusion of the appropriate CMSIS header for the selected device.
+ */
+#if CORTEX_MODEL == CORTEX_M0
+#include "core_cm0.h"
+#elif CORTEX_MODEL == CORTEX_M0PLUS
+#include "core_cm0plus.h"
+#elif CORTEX_MODEL == CORTEX_M3
+#include "core_cm3.h"
+#elif CORTEX_MODEL == CORTEX_M4
+#include "core_cm4.h"
+#else
+#error "unknown or unsupported Cortex-M model"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Type of system time.
+ */
+#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
+typedef uint32_t systime_t;
+#else
+typedef uint16_t systime_t;
+#endif
+
+/**
+ * @brief   Type of a generic ARM register.
+ */
+typedef void *regarm_t;
+
+/**
+ * @brief   Type of stack and memory alignment enforcement.
+ * @note    In this architecture the stack alignment is enforced to 64 bits,
+ *          32 bits alignment is supported by hardware but deprecated by ARM,
+ *          the implementation choice is to not offer the option.
+ */
+typedef uint64_t stkalign_t;
+
+/* The following declarations are there just for Doxygen documentation, the
+   real declarations are inside the sub-headers being specific for the
+   sub-architectures.*/
+#if defined(__DOXYGEN__)
+/**
+ * @brief   Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ *          preemption-capable interrupt handler.
+ * @note    It is implemented to match the Cortex-Mx exception context.
+ */
+struct port_extctx {};
+
+/**
+ * @brief   System saved context.
+ * @details This structure represents the inner stack frame during a context
+ *          switching.
+ */
+struct port_intctx {};
+#endif /* defined(__DOXYGEN__) */
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Total priority levels.
+ */
+#define CORTEX_PRIORITY_LEVELS          (1 << CORTEX_PRIORITY_BITS)
+
+/**
+ * @brief   Minimum priority level.
+ * @details This minimum priority level is calculated from the number of
+ *          priority bits supported by the specific Cortex-Mx implementation.
+ */
+#define CORTEX_MINIMUM_PRIORITY         (CORTEX_PRIORITY_LEVELS - 1)
+
+/**
+ * @brief   Maximum priority level.
+ * @details The maximum allowed priority level is always zero.
+ */
+#define CORTEX_MAXIMUM_PRIORITY         0
+
+/**
+ * @brief   Priority level verification macro.
+ */
+#define CORTEX_IS_VALID_PRIORITY(n)                                         \
+  (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
+
+/**
+ * @brief   Priority level verification macro.
+ */
+#define CORTEX_IS_VALID_KERNEL_PRIORITY(n)                                  \
+  (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
+
+/**
+ * @brief   Priority level to priority mask conversion macro.
+ */
+#define CORTEX_PRIO_MASK(n)                                                 \
+  ((n) << (8 - CORTEX_PRIORITY_BITS))
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/* Includes the sub-architecture-specific part.*/
+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M0PLUS) ||       \
+    (CORTEX_MODEL == CORTEX_M1)
+#include "nilcore_v6m.h"
+#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
+#include "nilcore_v7m.h"
+#endif
+
+#if !defined(_FROM_ASM_)
+
+#if NIL_CFG_ST_TIMEDELTA > 0
+#if !PORT_USE_ALT_TIMER
+#include "nilcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "nilcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* NIL_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _NILCORE_H_ */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_timer.h b/os/nil/ports/ARMCMx/nilcore_timer.h
new file mode 100644
index 000000000..a045ef544
--- /dev/null
+++ b/os/nil/ports/ARMCMx/nilcore_timer.h
@@ -0,0 +1,125 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/nilcore_timer.h
+ * @brief   System timer header file.
+ *
+ * @addtogroup ARMCMx_TIMER
+ * @{
+ */
+
+#ifndef _NILCORE_TIMER_H_
+#define _NILCORE_TIMER_H_
+
+/* This is the only header in the HAL designed to be include-able alone.*/
+#include "st.h"
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Starts the alarm.
+ * @note    Makes sure that no spurious alarms are triggered after
+ *          this call.
+ *
+ * @param[in] time      the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_start_alarm(systime_t time) {
+
+  stStartAlarm(time);
+}
+
+/**
+ * @brief   Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void port_timer_stop_alarm(void) {
+
+  stStopAlarm();
+}
+
+/**
+ * @brief   Sets the alarm time.
+ *
+ * @param[in] time      the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_set_alarm(systime_t time) {
+
+  stSetAlarm(time);
+}
+
+/**
+ * @brief   Returns the system time.
+ *
+ * @return              The system time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_time(void) {
+
+  return stGetCounter();
+}
+
+/**
+ * @brief   Returns the current alarm time.
+ *
+ * @return              The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_alarm(void) {
+
+  return stGetAlarm();
+}
+
+#endif /* _NILCORE_TIMER_H_ */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_v6m.c b/os/nil/ports/ARMCMx/nilcore_v6m.c
new file mode 100644
index 000000000..158e7d63d
--- /dev/null
+++ b/os/nil/ports/ARMCMx/nilcore_v6m.c
@@ -0,0 +1,144 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    nilcore_v6m.c
+ * @brief   ARMv6-M architecture port code.
+ *
+ * @addtogroup ARMCMx_V6M_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+/**
+ * @brief   NMI vector.
+ * @details The NMI vector is used for exception mode re-entering after a
+ *          context switch.
+ */
+void NMI_Handler(void) {
+
+  /* The port_extctx structure is pointed by the PSP register.*/
+  struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+  /* Discarding the current exception context and positioning the stack to
+     point to the real one.*/
+  ctxp++;
+
+  /* Writing back the modified PSP value.*/
+  __set_PSP((uint32_t)ctxp);
+
+  /* Restoring the normal interrupts status.*/
+  port_unlock_from_isr();
+}
+#endif /* !CORTEX_ALTERNATE_SWITCH */
+
+#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+/**
+ * @brief   PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ *          context switch.
+ */
+void PendSV_Handler(void) {
+
+  /* The port_extctx structure is pointed by the PSP register.*/
+  struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+  /* Discarding the current exception context and positioning the stack to
+     point to the real one.*/
+  ctxp++;
+
+  /* Writing back the modified PSP value.*/
+  __set_PSP((uint32_t)ctxp);
+}
+#endif /* CORTEX_ALTERNATE_SWITCH */
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   IRQ epilogue code.
+ *
+ * @param[in] lr        value of the @p LR register on ISR entry
+ */
+void _port_irq_epilogue(regarm_t lr) {
+
+  if (lr != (regarm_t)0xFFFFFFF1) {
+    struct port_extctx *ctxp;
+
+    port_lock_from_isr();
+
+    /* The extctx structure is pointed by the PSP register.*/
+    ctxp = (struct port_extctx *)__get_PSP();
+
+    /* Adding an artificial exception return context, there is no need to
+       populate it fully.*/
+    ctxp--;
+
+    /* Writing back the modified PSP value.*/
+    __set_PSP((uint32_t)ctxp);
+
+    /* Setting up a fake XPSR register value.*/
+    ctxp->xpsr = (regarm_t)0x01000000;
+
+    /* The exit sequence is different depending on if a preemption is
+       required or not.*/
+    if (chSchIsRescRequiredI()) {
+      /* Preemption is required we need to enforce a context switch.*/
+      ctxp->pc = (regarm_t)_port_switch_from_isr;
+    }
+    else {
+      /* Preemption not required, we just need to exit the exception
+         atomically.*/
+      ctxp->pc = (regarm_t)_port_exit_from_isr;
+    }
+
+    /* Note, returning without unlocking is intentional, this is done in
+       order to keep the rest of the context switch atomic.*/
+  }
+}
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_v6m.h b/os/nil/ports/ARMCMx/nilcore_v6m.h
new file mode 100644
index 000000000..0e73cdc34
--- /dev/null
+++ b/os/nil/ports/ARMCMx/nilcore_v6m.h
@@ -0,0 +1,398 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chcore_v6m.h
+ * @brief   ARMv6-M architecture port macros and structures.
+ *
+ * @addtogroup ARMCMx_V6M_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_V6M_H_
+#define _CHCORE_V6M_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Architecture and Compiler
+ * @{
+ */
+#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
+/**
+ * @brief   Macro defining the specific ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM_v6M
+
+/**
+ * @brief   Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME          "ARMv6-M"
+
+/**
+ * @brief   Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME          "Cortex-M0"
+
+#elif (CORTEX_MODEL == CORTEX_M0PLUS)
+#define PORT_ARCHITECTURE_ARM_v6M
+#define PORT_ARCHITECTURE_NAME          "ARMv6-M"
+#define PORT_CORE_VARIANT_NAME          "Cortex-M0+"
+#endif
+
+/**
+ * @brief   Port-specific information string.
+ */
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+#define PORT_INFO                       "Preemption through NMI"
+#else
+#define PORT_INFO                       "Preemption through PendSV"
+#endif
+/** @} */
+
+/**
+ * @brief   This port does not support a realtime counter.
+ */
+#define PORT_SUPPORTS_RT                FALSE
+
+/**
+ * @brief   PendSV priority level.
+ * @note    This priority is enforced to be equal to @p 0,
+ *          this handler always has the highest priority that cannot preempt
+ *          the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV          0
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ *          the idle thread should take no more space than those reserved
+ *          by @p PORT_INT_REQUIRED_STACK.
+ * @note    In this port it is set to 16 because the idle thread does have
+ *          a stack frame when compiling without optimizations. You may
+ *          reduce this value to zero when compiling with optimizations.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
+#define PORT_IDLE_THREAD_STACK_SIZE     16
+#endif
+
+/**
+ * @brief   Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ *          area size.
+ * @note    In this port this value is conservatively set to 32 because the
+ *          function @p chSchDoReschedule() can have a stack frame, especially
+ *          with compiler optimizations disabled. The value can be reduced
+ *          when compiler optimizations are enabled.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK)
+#define PORT_INT_REQUIRED_STACK         32
+#endif
+
+/**
+ * @brief   Enables the use of the WFI instruction in the idle thread loop.
+ */
+#if !defined(CORTEX_ENABLE_WFI_IDLE)
+#define CORTEX_ENABLE_WFI_IDLE          FALSE
+#endif
+
+/**
+ * @brief   Alternate preemption method.
+ * @details Activating this option will make the Kernel use the PendSV
+ *          handler for preemption instead of the NMI handler.
+ */
+#ifndef CORTEX_ALTERNATE_SWITCH
+#define CORTEX_ALTERNATE_SWITCH         FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/**
+ * @brief   Maximum usable priority for normal ISRs.
+ */
+#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+#define CORTEX_MAX_KERNEL_PRIORITY      1
+#else
+#define CORTEX_MAX_KERNEL_PRIORITY      0
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+
+ /* The documentation of the following declarations is in chconf.h in order
+    to not have duplicated structure names into the documentation.*/
+#if !defined(__DOXYGEN__)
+struct port_extctx {
+  regarm_t      r0;
+  regarm_t      r1;
+  regarm_t      r2;
+  regarm_t      r3;
+  regarm_t      r12;
+  regarm_t      lr_thd;
+  regarm_t      pc;
+  regarm_t      xpsr;
+};
+
+struct port_intctx {
+  regarm_t      r8;
+  regarm_t      r9;
+  regarm_t      r10;
+  regarm_t      r11;
+  regarm_t      r4;
+  regarm_t      r5;
+  regarm_t      r6;
+  regarm_t      r7;
+  regarm_t      lr;
+};
+#endif /* !defined(__DOXYGEN__) */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Platform dependent thread stack setup.
+ * @details This code usually setup the context switching frame represented
+ *          by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) {                             \
+  (tp)->ctxp = (struct port_intctx *)(((uint8_t *)(wend)) -                 \
+                                      sizeof(struct port_intctx));          \
+  (tp)->ctxp->r4 = (regarm_t)(pf);                                          \
+  (tp)->ctxp->r5 = (regarm_t)(arg);                                         \
+  (tp)->ctxp->lr = (regarm_t)(_port_thread_start);                          \
+}
+
+/**
+ * @brief   Computes the thread working area global size.
+ * @note    There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) +                       \
+                         sizeof(struct port_extctx) +                       \
+                         (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()                                                 \
+  regarm_t _saved_lr;                                                       \
+  asm volatile ("mov     %0, lr" : "=r" (_saved_lr) : : "memory")
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Fast IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ */
+#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) {                                             \
+  struct port_intctx *r13 = (struct port_intctx *)__get_PSP();              \
+  if ((stkalign_t *)(r13 - 1) < (otp)->stklim)                              \
+    chSysHalt("stack overflow");                                            \
+  _port_switch(ntp, otp);                                                   \
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _port_irq_epilogue(regarm_t lr);
+  void _port_switch_from_isr(void);
+  void _port_exit_from_isr(void);
+  void _port_switch(thread_t *ntp, thread_t *otp);
+  void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+  NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
+}
+
+/**
+ * @brief   Returns a word encoding the current interrupts status.
+ *
+ * @return              The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+  return __get_PRIMASK();
+}
+
+/**
+ * @brief   Checks the interrupt status.
+ *
+ * @param[in] sts       the interrupt status word
+ *
+ * @return              The interrupt status.
+ * @retvel false        the word specified a disabled interrupts status.
+ * @retvel true         the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+  return (sts & 1) == 0;
+}
+
+/**
+ * @brief   Determines the current execution context.
+ *
+ * @return              The execution context.
+ * @retval false        not running in ISR mode.
+ * @retval true         running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+  return (bool)((__get_IPSR() & 0x1FF) != 0);
+}
+
+/**
+ * @brief   Kernel-lock action.
+ * @details In this port this function disables interrupts globally.
+ */
+static inline void port_lock(void) {
+
+  __disable_irq();
+}
+
+/**
+ * @brief   Kernel-unlock action.
+ * @details In this port this function enables interrupts globally.
+ */
+static inline void port_unlock(void) {
+
+  __enable_irq();
+}
+
+/**
+ * @brief   Kernel-lock action from an interrupt handler.
+ * @details In this port this function disables interrupts globally.
+ * @note    Same as @p port_lock() in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+  port_lock();
+}
+
+/**
+ * @brief   Kernel-unlock action from an interrupt handler.
+ * @details In this port this function enables interrupts globally.
+ * @note    Same as @p port_lock() in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+  port_unlock();
+}
+
+/**
+ * @brief   Disables all the interrupt sources.
+ */
+static inline void port_disable(void) {
+
+  __disable_irq();
+}
+
+/**
+ * @brief   Disables the interrupt sources below kernel-level priority.
+ */
+static inline void port_suspend(void) {
+
+  __disable_irq();
+}
+
+/**
+ * @brief   Enables all the interrupt sources.
+ */
+static inline void port_enable(void) {
+
+  __enable_irq();
+}
+
+/**
+ * @brief   Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ *          The simplest implementation is an empty function or macro but this
+ *          would not take advantage of architecture-specific power saving
+ *          modes.
+ * @note    Implemented as an inlined @p WFI instruction.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+#if CORTEX_ENABLE_WFI_IDLE
+  __WFI;
+#endif
+}
+
+#endif /* _FROM_ASM_ */
+
+#endif /* _CHCORE_V6M_H_ */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_v7m.c b/os/nil/ports/ARMCMx/nilcore_v7m.c
new file mode 100644
index 000000000..ac059e38d
--- /dev/null
+++ b/os/nil/ports/ARMCMx/nilcore_v7m.c
@@ -0,0 +1,174 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    nilcore_v7m.c
+ * @brief   ARMv7-M architecture port code.
+ *
+ * @addtogroup ARMCMx_V7M_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+/**
+ * @brief   SVC vector.
+ * @details The SVC vector is used for exception mode re-entering after a
+ *          context switch.
+ * @note    The PendSV vector is only used in advanced kernel mode.
+ */
+void SVC_Handler(void) {
+
+  /* The port_extctx structure is pointed by the PSP register.*/
+  struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+  /* Discarding the current exception context and positioning the stack to
+     point to the real one.*/
+  ctxp++;
+
+#if CORTEX_USE_FPU
+  /* Restoring the special register FPCCR.*/
+  FPU->FPCCR = (uint32_t)ctxp->fpccr;
+  FPU->FPCAR = FPU->FPCAR + sizeof (struct port_extctx);
+#endif
+
+  /* Writing back the modified PSP value.*/
+  __set_PSP((uint32_t)ctxp);
+
+  /* Restoring the normal interrupts status.*/
+  port_unlock_from_isr();
+}
+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
+
+#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+/**
+ * @brief   PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ *          context switch.
+ * @note    The PendSV vector is only used in compact kernel mode.
+ */
+void PendSV_Handler(void) {
+
+  /* The port_extctx structure is pointed by the PSP register.*/
+  struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+  /* Discarding the current exception context and positioning the stack to
+     point to the real one.*/
+  ctxp++;
+
+#if CORTEX_USE_FPU
+  /* Restoring the special register FPCCR.*/
+  FPU->FPCCR = (uint32_t)ctxp->fpccr;
+  FPU->FPCAR = FPU->FPCAR + sizeof (struct port_extctx);
+#endif
+
+  /* Writing back the modified PSP value.*/
+  __set_PSP((uint32_t)ctxp);
+}
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Exception exit redirection to _port_switch_from_isr().
+ */
+void _port_irq_epilogue(void) {
+
+  port_lock_from_isr();
+  if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0) {
+
+    /* The port_extctx structure is pointed by the PSP register.*/
+    struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+    /* Adding an artificial exception return context, there is no need to
+       populate it fully.*/
+    ctxp--;
+
+    /* Writing back the modified PSP value.*/
+    __set_PSP((uint32_t)ctxp);
+
+    /* Setting up a fake XPSR register value.*/
+    ctxp->xpsr = (regarm_t)0x01000000;
+
+    /* The exit sequence is different depending on if a preemption is
+       required or not.*/
+    if (chSchIsRescRequiredI()) {
+      /* Preemption is required we need to enforce a context switch.*/
+      ctxp->pc = (regarm_t)_port_switch_from_isr;
+#if CORTEX_USE_FPU
+      /* Enforcing a lazy FPU state save by accessing the FPCSR register.*/
+      (void) __get_FPSCR();
+#endif
+    }
+    else {
+      /* Preemption not required, we just need to exit the exception
+         atomically.*/
+      ctxp->pc = (regarm_t)_port_exit_from_isr;
+    }
+
+#if CORTEX_USE_FPU
+    {
+      uint32_t fpccr;
+
+      /* Saving the special register SCB_FPCCR into the reserved offset of
+         the Cortex-M4 exception frame.*/
+      (ctxp + 1)->fpccr = (regarm_t)(fpccr = FPU->FPCCR);
+
+      /* Now the FPCCR is modified in order to not restore the FPU status
+         from the artificial return context.*/
+      FPU->FPCCR = fpccr | FPU_FPCCR_LSPACT_Msk;
+    }
+#endif
+
+    /* Note, returning without unlocking is intentional, this is done in
+       order to keep the rest of the context switch atomic.*/
+    return;
+  }
+  port_unlock_from_isr();
+}
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/nilcore_v7m.h b/os/nil/ports/ARMCMx/nilcore_v7m.h
new file mode 100644
index 000000000..ff2307495
--- /dev/null
+++ b/os/nil/ports/ARMCMx/nilcore_v7m.h
@@ -0,0 +1,554 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chcore_v7m.h
+ * @brief   ARMv7-M architecture port macros and structures.
+ *
+ * @addtogroup ARMCMx_V7M_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_V7M_H_
+#define _CHCORE_V7M_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Architecture and Compiler
+ * @{
+ */
+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
+/**
+ * @brief   Macro defining the specific ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM_v7M
+
+/**
+ * @brief   Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME          "ARMv7-M"
+
+/**
+ * @brief   Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME          "Cortex-M3"
+
+#elif (CORTEX_MODEL == CORTEX_M4)
+#define PORT_ARCHITECTURE_ARM_v7ME
+#define PORT_ARCHITECTURE_NAME          "ARMv7-ME"
+#if CORTEX_USE_FPU
+#define PORT_CORE_VARIANT_NAME          "Cortex-M4F"
+#else
+#define PORT_CORE_VARIANT_NAME          "Cortex-M4"
+#endif
+#endif
+
+/**
+ * @brief   Port-specific information string.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define PORT_INFO                       "Advanced kernel mode"
+#else
+#define PORT_INFO                       "Compact kernel mode"
+#endif
+/** @} */
+
+/**
+ * @brief   This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT                FALSE //TRUE
+
+/**
+ * @brief   Disabled value for BASEPRI register.
+ */
+#define CORTEX_BASEPRI_DISABLED         0
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ *          the idle thread should take no more space than those reserved
+ *          by @p PORT_INT_REQUIRED_STACK.
+ * @note    In this port it is set to 16 because the idle thread does have
+ *          a stack frame when compiling without optimizations. You may
+ *          reduce this value to zero when compiling with optimizations.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE     16
+#endif
+
+/**
+ * @brief   Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ *          area size.
+ * @note    In this port this value is conservatively set to 32 because the
+ *          function @p chSchDoReschedule() can have a stack frame, especially
+ *          with compiler optimizations disabled. The value can be reduced
+ *          when compiler optimizations are enabled.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK         32
+#endif
+
+/**
+ * @brief   Enables the use of the WFI instruction in the idle thread loop.
+ */
+#if !defined(CORTEX_ENABLE_WFI_IDLE)
+#define CORTEX_ENABLE_WFI_IDLE          FALSE
+#endif
+
+/**
+ * @brief   FPU support in context switch.
+ * @details Activating this option activates the FPU support in the kernel.
+ */
+#if !defined(CORTEX_USE_FPU)
+#define CORTEX_USE_FPU                  CORTEX_HAS_FPU
+#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
+/* This setting requires an FPU presence check in case it is externally
+   redefined.*/
+#error "the selected core does not have an FPU"
+#endif
+
+/**
+ * @brief   Simplified priority handling flag.
+ * @details Activating this option makes the Kernel work in compact mode.
+ *          In compact mode interrupts are disabled globally instead of
+ *          raising the priority mask to some intermediate level.
+ */
+#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
+#define CORTEX_SIMPLIFIED_PRIORITY      FALSE
+#endif
+
+/**
+ * @brief   SVCALL handler priority.
+ * @note    The default SVCALL handler priority is defaulted to
+ *          @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
+ *          @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
+ *          priority level.
+ */
+#if !defined(CORTEX_PRIORITY_SVCALL)
+#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1)
+#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
+/* If it is externally redefined then better perform a validity check on it.*/
+#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
+#endif
+
+/**
+ * @brief   NVIC VTOR initialization expression.
+ */
+#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
+#define CORTEX_VTOR_INIT                0x00000000
+#endif
+
+/**
+ * @brief   NVIC PRIGROUP initialization expression.
+ * @details The default assigns all available priority bits as preemption
+ *          priority with no sub-priority.
+ */
+#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
+#define CORTEX_PRIGROUP_INIT            (7 - CORTEX_PRIORITY_BITS)
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+/**
+ * @brief   Maximum usable priority for normal ISRs.
+ */
+#define CORTEX_MAX_KERNEL_PRIORITY      (CORTEX_PRIORITY_SVCALL + 1)
+
+/**
+ * @brief   BASEPRI level within kernel lock.
+ */
+#define CORTEX_BASEPRI_KERNEL                                               \
+  CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
+#else
+
+#define CORTEX_MAX_KERNEL_PRIORITY      0
+#endif
+
+/**
+ * @brief   PendSV priority level.
+ * @note    This priority is enforced to be equal to
+ *          @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
+ *          highest priority that cannot preempt the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV          CORTEX_MAX_KERNEL_PRIORITY
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* The documentation of the following declarations is in chconf.h in order
+   to not have duplicated structure names into the documentation.*/
+#if !defined(__DOXYGEN__)
+struct port_extctx {
+  regarm_t      r0;
+  regarm_t      r1;
+  regarm_t      r2;
+  regarm_t      r3;
+  regarm_t      r12;
+  regarm_t      lr_thd;
+  regarm_t      pc;
+  regarm_t      xpsr;
+#if CORTEX_USE_FPU
+  regarm_t      s0;
+  regarm_t      s1;
+  regarm_t      s2;
+  regarm_t      s3;
+  regarm_t      s4;
+  regarm_t      s5;
+  regarm_t      s6;
+  regarm_t      s7;
+  regarm_t      s8;
+  regarm_t      s9;
+  regarm_t      s10;
+  regarm_t      s11;
+  regarm_t      s12;
+  regarm_t      s13;
+  regarm_t      s14;
+  regarm_t      s15;
+  regarm_t      fpscr;
+  regarm_t      fpccr;
+#endif /* CORTEX_USE_FPU */
+};
+
+struct port_intctx {
+#if CORTEX_USE_FPU
+  regarm_t      s16;
+  regarm_t      s17;
+  regarm_t      s18;
+  regarm_t      s19;
+  regarm_t      s20;
+  regarm_t      s21;
+  regarm_t      s22;
+  regarm_t      s23;
+  regarm_t      s24;
+  regarm_t      s25;
+  regarm_t      s26;
+  regarm_t      s27;
+  regarm_t      s28;
+  regarm_t      s29;
+  regarm_t      s30;
+  regarm_t      s31;
+#endif /* CORTEX_USE_FPU */
+  regarm_t      r4;
+  regarm_t      r5;
+  regarm_t      r6;
+  regarm_t      r7;
+  regarm_t      r8;
+  regarm_t      r9;
+  regarm_t      r10;
+  regarm_t      r11;
+  regarm_t      lr;
+};
+#endif /* !defined(__DOXYGEN__) */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Platform dependent thread stack setup.
+ * @details This code usually setup the context switching frame represented
+ *          by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) {                             \
+  (tp)->ctxp = (struct port_intctx *)(((uint8_t *)(wend)) -                 \
+                                      sizeof(struct port_intctx));          \
+  (tp)->ctxp->r4 = (regarm_t)(pf);                                          \
+  (tp)->ctxp->r5 = (regarm_t)(arg);                                         \
+  (tp)->ctxp->lr = (regarm_t)(_port_thread_start);                          \
+}
+
+/**
+ * @brief   Computes the thread working area global size.
+ * @note    There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) +                       \
+                         sizeof(struct port_extctx) +                       \
+                         (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Fast IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ */
+#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) {                                             \
+  struct port_intctx *r13 = (struct port_intctx *)__get_PSP();              \
+  if ((stkalign_t *)(r13 - 1) < (otp)->stklim)                              \
+    chSysHalt("stack overflow");                                            \
+  _port_switch(ntp, otp);                                                   \
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _port_irq_epilogue(void);
+  void _port_switch(thread_t *ntp, thread_t *otp);
+  void _port_thread_start(void);
+  void _port_switch_from_isr(void);
+  void _port_exit_from_isr(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+  /* Initialization of the vector table and priority related settings.*/
+  SCB->VTOR = CORTEX_VTOR_INIT;
+
+  /* Initializing priority grouping.*/
+  NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
+
+  /* DWT cycle counter enable.*/
+  CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+  DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+
+  /* Initialization of the system vectors used by the port.*/
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);
+#endif
+  NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
+}
+
+/**
+ * @brief   Returns a word encoding the current interrupts status.
+ *
+ * @return              The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+  register uint32_t sts;
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  sts = __get_BASEPRI();
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+  sts = __get_PRIMASK();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+  return sts;
+}
+
+/**
+ * @brief   Checks the interrupt status.
+ *
+ * @param[in] sts       the interrupt status word
+ *
+ * @return              The interrupt status.
+ * @retvel false        the word specified a disabled interrupts status.
+ * @retvel true         the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  return sts == CORTEX_BASEPRI_DISABLED;
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+  return (sts & 1) == 0;
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief   Determines the current execution context.
+ *
+ * @return              The execution context.
+ * @retval false        not running in ISR mode.
+ * @retval true         running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+  return (bool)((__get_IPSR() & 0x1FF) != 0);
+}
+
+/**
+ * @brief   Kernel-lock action.
+ * @details In this port this function raises the base priority to kernel
+ *          level.
+ */
+static inline void port_lock(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+  __disable_irq();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief   Kernel-unlock action.
+ * @details In this port this function lowers the base priority to user
+ *          level.
+ */
+static inline void port_unlock(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  __set_BASEPRI(CORTEX_BASEPRI_DISABLED);
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+  __enable_irq();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief   Kernel-lock action from an interrupt handler.
+ * @details In this port this function raises the base priority to kernel
+ *          level.
+ * @note    Same as @p port_lock() in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+  port_lock();
+}
+
+/**
+ * @brief   Kernel-unlock action from an interrupt handler.
+ * @details In this port this function lowers the base priority to user
+ *          level.
+ * @note    Same as @p port_unlock() in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+  port_unlock();
+}
+
+/**
+ * @brief   Disables all the interrupt sources.
+ * @note    In this port it disables all the interrupt sources by raising
+ *          the priority mask to level 0.
+ */
+static inline void port_disable(void) {
+
+  __disable_irq();
+}
+
+/**
+ * @brief   Disables the interrupt sources below kernel-level priority.
+ * @note    Interrupt sources above kernel level remains enabled.
+ * @note    In this port it raises/lowers the base priority to kernel level.
+ */
+static inline void port_suspend(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);
+  __enable_irq();
+#else
+  __disable_irq();
+#endif
+}
+
+/**
+ * @brief   Enables all the interrupt sources.
+ * @note    In this port it lowers the base priority to user level.
+ */
+static inline void port_enable(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+  __set_BASEPRI(CORTEX_BASEPRI_DISABLED);
+#endif
+  __enable_irq();
+}
+
+/**
+ * @brief   Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ *          The simplest implementation is an empty function or macro but this
+ *          would not take advantage of architecture-specific power saving
+ *          modes.
+ * @note    Implemented as an inlined @p WFI instruction.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+#if CORTEX_ENABLE_WFI_IDLE
+  __WFI;
+#endif
+}
+
+/**
+ * @brief   Returns the current value of the realtime counter.
+ *
+ * @return              The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+  return DWT->CYCCNT;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CHCORE_V7M_H_ */
+
+/** @} */
diff --git a/os/nil/ports/AVR/compilers/GCC/niltypes.h b/os/nil/ports/AVR/compilers/GCC/niltypes.h
new file mode 100644
index 000000000..25d849d77
--- /dev/null
+++ b/os/nil/ports/AVR/compilers/GCC/niltypes.h
@@ -0,0 +1,87 @@
+/*
+    ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/NIL.
+
+    ChibiOS/NIL is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/NIL is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    AVR/compilers/GCC/niltypes.h
+ * @brief   AVR port system types.
+ *
+ * @addtogroup AVR_CORE
+ * @{
+ */
+
+#ifndef _NILTYPES_H_
+#define _NILTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name    Common constants
+ */
+/**
+ * @brief   Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE                   0
+#endif
+
+/**
+ * @brief   Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                    (!FALSE)
+#endif
+/** @} */
+
+typedef uint8_t         syssts_t;       /**< System status word.            */
+typedef uint16_t        rtcnt_t;        /**< Realtime counter.              */
+typedef uint8_t         tstate_t;       /**< Thread state.                  */
+typedef int16_t         msg_t;          /**< Inter-thread message.          */
+typedef uint8_t         eventmask_t;    /**< Mask of event identifiers.     */
+typedef int8_t          cnt_t;          /**< Generic signed counter.        */
+typedef uint8_t         ucnt_t;         /**< Generic unsigned counter.      */
+
+/**
+ * @brief   ROM constant modifier.
+ * @note    It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief   Makes functions not inlineable.
+ * @note    If the compiler does not support such attribute then the
+ *          realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief   Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg)                                       \
+  __attribute__((noreturn)) void tname(void *arg)
+
+/**
+ * @brief   Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+#endif /* _NILTYPES_H_ */
+
+/** @} */
diff --git a/os/nil/ports/AVR/nilcore.c b/os/nil/ports/AVR/nilcore.c
new file mode 100644
index 000000000..eb762b00b
--- /dev/null
+++ b/os/nil/ports/AVR/nilcore.c
@@ -0,0 +1,138 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    AVR/nilcore.c
+ * @brief   AVR port code.
+ *
+ * @addtogroup AVR_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ * @note    The function is declared as a weak symbol, it is possible to
+ *          redefine it in your application code.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((naked, weak))
+#endif
+void port_switch(Thread *ntp, Thread *otp) {
+
+  asm volatile ("push    r2");
+  asm volatile ("push    r3");
+  asm volatile ("push    r4");
+  asm volatile ("push    r5");
+  asm volatile ("push    r6");
+  asm volatile ("push    r7");
+  asm volatile ("push    r8");
+  asm volatile ("push    r9");
+  asm volatile ("push    r10");
+  asm volatile ("push    r11");
+  asm volatile ("push    r12");
+  asm volatile ("push    r13");
+  asm volatile ("push    r14");
+  asm volatile ("push    r15");
+  asm volatile ("push    r16");
+  asm volatile ("push    r17");
+  asm volatile ("push    r28");
+  asm volatile ("push    r29");
+
+  asm volatile ("movw    r30, r22");
+  asm volatile ("in      r0, 0x3d");
+  asm volatile ("std     Z+5, r0");
+  asm volatile ("in      r0, 0x3e");
+  asm volatile ("std     Z+6, r0");
+
+  asm volatile ("movw    r30, r24");
+  asm volatile ("ldd     r0, Z+5");
+  asm volatile ("out     0x3d, r0");
+  asm volatile ("ldd     r0, Z+6");
+  asm volatile ("out     0x3e, r0");
+
+  asm volatile ("pop     r29");
+  asm volatile ("pop     r28");
+  asm volatile ("pop     r17");
+  asm volatile ("pop     r16");
+  asm volatile ("pop     r15");
+  asm volatile ("pop     r14");
+  asm volatile ("pop     r13");
+  asm volatile ("pop     r12");
+  asm volatile ("pop     r11");
+  asm volatile ("pop     r10");
+  asm volatile ("pop     r9");
+  asm volatile ("pop     r8");
+  asm volatile ("pop     r7");
+  asm volatile ("pop     r6");
+  asm volatile ("pop     r5");
+  asm volatile ("pop     r4");
+  asm volatile ("pop     r3");
+  asm volatile ("pop     r2");
+  asm volatile ("ret");
+}
+
+/**
+ * @brief   Start a thread by invoking its work function.
+ * @details If the work function returns @p chThdExit() is automatically
+ *          invoked.
+ */
+void _port_thread_start(void) {
+
+  chSysUnlock();
+  asm volatile ("movw    r24, r4");
+  asm volatile ("movw    r30, r2");
+  asm volatile ("icall");
+  chSysHalt(0);
+}
+
+/** @} */
diff --git a/os/nil/ports/AVR/nilcore.h b/os/nil/ports/AVR/nilcore.h
new file mode 100644
index 000000000..6394eeb0b
--- /dev/null
+++ b/os/nil/ports/AVR/nilcore.h
@@ -0,0 +1,438 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    AVR/nilcore.h
+ * @brief   AVR port macros and structures.
+ *
+ * @addtogroup AVR_CORE
+ * @{
+ */
+
+#ifndef _NILCORE_H_
+#define _NILCORE_H_
+
+#include <avr/io.h>
+#include <avr/interrupt.h>
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief   Macro defining the port architecture.
+ */
+#define PORT_ARCHITECTURE_AVR
+
+/**
+ * @brief   Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME          "AVR"
+
+/**
+ * @brief   Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME          "MegaAVR"
+
+/**
+ * @brief   Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME              "GCC " __VERSION__
+
+#else
+#error "unsupported compiler"
+#endif
+
+/**
+ * @brief   Port-specific information string.
+ */
+#define PORT_INFO                       "16 bits code addressing"
+
+/**
+ * @brief   This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT                FALSE
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ *          the idle thread should take no more space than those reserved
+ *          by @p PORT_INT_REQUIRED_STACK.
+ * @note    In this port it is set to 8.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE     8
+#endif
+
+/**
+ * @brief   Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ *          area size.
+ * @note    In this port the default is 32 bytes per thread.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK         32
+#endif
+
+/**
+ * @brief   Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ *          @p nilcore_timer.h, if this option is enabled then the file
+ *          @p nilcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER              FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Type of system time.
+ */
+#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
+typedef uint32_t systime_t;
+#else
+typedef uint16_t systime_t;
+#endif
+
+/**
+ * @brief   Type of stack and memory alignment enforcement.
+ */
+typedef uint8_t stkalign_t;
+
+/**
+ * @brief   Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ *          preemption-capable interrupt handler.
+ */
+struct port_extctx {
+  uint8_t       _next;
+  uint8_t       r31;
+  uint8_t       r30;
+  uint8_t       r27;
+  uint8_t       r26;
+  uint8_t       r25;
+  uint8_t       r24;
+  uint8_t       r23;
+  uint8_t       r22;
+  uint8_t       r21;
+  uint8_t       r20;
+  uint8_t       r19;
+  uint8_t       r18;
+  uint8_t       sr;
+  uint8_t       r1;
+  uint8_t       r0;
+  uint16_t      pc;
+};
+
+/**
+ * @brief   System saved context.
+ * @details This structure represents the inner stack frame during a context
+ *          switching.
+ */
+struct port_intctx {
+  uint8_t       _next;
+  uint8_t       r29;
+  uint8_t       r28;
+  uint8_t       r17;
+  uint8_t       r16;
+  uint8_t       r15;
+  uint8_t       r14;
+  uint8_t       r13;
+  uint8_t       r12;
+  uint8_t       r11;
+  uint8_t       r10;
+  uint8_t       r9;
+  uint8_t       r8;
+  uint8_t       r7;
+  uint8_t       r6;
+  uint8_t       r5;
+  uint8_t       r4;
+  uint8_t       r3;
+  uint8_t       r2;
+  uint8_t       pcl;
+  uint8_t       pch;
+};
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Platform dependent thread stack setup.
+ * @details This code usually setup the context switching frame represented
+ *          by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) {                             \
+    (tp)->ctxp.sp = (struct port_intctx*)(((uint8_t *)(wend)) -             \
+                                           sizeof(struct port_intctx));     \
+    (tp)->ctxp.sp->r2  = (uint8_t)(pf);                                     \
+    (tp)->ctxp.sp->r3  = (uint8_t)((pf) >> 8);                              \
+    (tp)->ctxp.sp->r4  = (uint8_t)(arg);                                    \
+    (tp)->ctxp.sp->r5  = (uint8_t)((arg) >> 8);                             \
+    (tp)->ctxp.sp->pcl = (uint8_t)(_port_thread_start >> 8);                \
+    (tp)->ctxp.sp->pch = (uint8_t)_port_thread_start;                       \
+}
+
+/**
+ * @brief   Computes the thread working area global size.
+ * @note    There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) ((sizeof(struct port_intctx) - 1) +                 \
+                         (sizeof(struct port_extctx) - 1) +                 \
+                         (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ *          enabled to invoke system APIs.
+ * @note    This code tricks the compiler to save all the specified registers
+ *          by "touching" them.
+ */
+#define PORT_IRQ_PROLOGUE() {                                               \
+  asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24",            \
+                "r25", "r26", "r27", "r30", "r31");                         \
+}
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() chSchRescheduleS()
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) ISR(id)
+
+/**
+ * @brief   Fast IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) ISR(id)
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ */
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _port_irq_epilogue(void);
+  void _port_switch(thread_t *ntp, thread_t *otp);
+  void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+}
+
+/**
+ * @brief   Returns a word encoding the current interrupts status.
+ *
+ * @return              The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+  return 0;
+}
+
+/**
+ * @brief   Checks the interrupt status.
+ *
+ * @param[in] sts       the interrupt status word
+ *
+ * @return              The interrupt status.
+ * @retvel false        the word specified a disabled interrupts status.
+ * @retvel true         the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+  return false;
+}
+
+/**
+ * @brief   Determines the current execution context.
+ *
+ * @return              The execution context.
+ * @retval false        not running in ISR mode.
+ * @retval true         running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+  return false;
+}
+
+/**
+ * @brief   Kernel-lock action.
+ */
+static inline void port_lock(void) {
+
+  asm volatile ("cli" : : : "memory");
+}
+
+/**
+ * @brief   Kernel-unlock action.
+ */
+static inline void port_unlock(void) {
+
+  asm volatile ("sei" : : : "memory");
+}
+
+/**
+ * @brief   Kernel-lock action from an interrupt handler.
+ * @note    This function is empty in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+}
+
+/**
+ * @brief   Kernel-unlock action from an interrupt handler.
+ * @note    This function is empty in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+}
+
+/**
+ * @brief   Disables all the interrupt sources.
+ */
+static inline void port_disable(void) {
+
+  asm volatile ("cli" : : : "memory");
+}
+
+/**
+ * @brief   Disables the interrupt sources below kernel-level priority.
+ */
+static inline void port_suspend(void) {
+
+  asm volatile ("cli" : : : "memory");
+}
+
+/**
+ * @brief   Enables all the interrupt sources.
+ */
+static inline void port_enable(void) {
+
+  asm volatile ("sei" : : : "memory");
+}
+
+/**
+ * @brief   Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ *          The simplest implementation is an empty function or macro but this
+ *          would not take advantage of architecture-specific power saving
+ *          modes.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+  asm volatile ("sleep" : : : "memory");
+}
+
+/**
+ * @brief   Returns the current value of the realtime counter.
+ *
+ * @return              The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+  return 0;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module late inclusions.                                                   */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+
+#if NIL_CFG_ST_TIMEDELTA > 0
+#if !PORT_USE_ALT_TIMER
+#include "nilcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "nilcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* NIL_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _NILCORE_H_ */
+
+/** @} */
diff --git a/os/nil/ports/AVR/nilcore_timer.h b/os/nil/ports/AVR/nilcore_timer.h
new file mode 100644
index 000000000..0eadcf12a
--- /dev/null
+++ b/os/nil/ports/AVR/nilcore_timer.h
@@ -0,0 +1,129 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    AVR/nilcore_timer.h
+ * @brief   System timer header file.
+ *
+ * @addtogroup AVR_TIMER
+ * @{
+ */
+
+#ifndef _NILCORE_TIMER_H_
+#define _NILCORE_TIMER_H_
+
+/* This is the only header in the HAL designed to be include-able alone.*/
+/*#include "st.h"*/
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#error "tickless mode not yet implemented in AVR port"
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#if 0
+/**
+ * @brief   Starts the alarm.
+ * @note    Makes sure that no spurious alarms are triggered after
+ *          this call.
+ *
+ * @param[in] time      the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_start_alarm(systime_t time) {
+
+  stStartAlarm(time);
+}
+
+/**
+ * @brief   Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void port_timer_stop_alarm(void) {
+
+  stStopAlarm();
+}
+
+/**
+ * @brief   Sets the alarm time.
+ *
+ * @param[in] time      the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_set_alarm(systime_t time) {
+
+  stSetAlarm(time);
+}
+
+/**
+ * @brief   Returns the system time.
+ *
+ * @return              The system time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_time(void) {
+
+  return stGetCounter();
+}
+
+/**
+ * @brief   Returns the current alarm time.
+ *
+ * @return              The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_alarm(void) {
+
+  return stGetAlarm();
+}
+#endif
+
+#endif /* _NILCORE_TIMER_H_ */
+
+/** @} */
diff --git a/os/nil/src/nil.c b/os/nil/src/nil.c
new file mode 100644
index 000000000..789256127
--- /dev/null
+++ b/os/nil/src/nil.c
@@ -0,0 +1,760 @@
+/*
+    Nil RTOS - Copyright (C) 2012 Giovanni Di Sirio.
+
+    This file is part of Nil RTOS.
+
+    Nil RTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    Nil RTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    nil.c
+ * @brief   Nil RTOS main source file.
+ *
+ * @defgroup nil
+ * @details Nil RTOS services.
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   System data structures.
+ */
+nil_system_t nil;
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the kernel.
+ * @details Initializes the kernel structures, the current instructions flow
+ *          becomes the idle thread upon return. The idle thread must not
+ *          invoke any kernel primitive able to change state to not runnable.
+ * @note    This function assumes that the @p nil global variable has been
+ *          zeroed by the runtime environment. If this is not the case then
+ *          make sure to clear it before calling this function.
+ *
+ * @special
+ */
+void chSysInit(void) {
+  thread_t *tp;
+  const thread_config_t *tcp;
+
+  /* Port layer initialization.*/
+  port_init();
+
+  /* Iterates through the list of defined threads.*/
+  tp = &nil.threads[0];
+  tcp = nil_thd_configs;
+  while (tp < &nil.threads[NIL_CFG_NUM_THREADS]) {
+#if NIL_CFG_ENABLE_STACK_CHECK
+    tp->stklim  = (stkalign_t *)tcp->wbase;
+#endif
+
+    /* Port dependent thread initialization.*/
+    PORT_SETUP_CONTEXT(tp, tcp->wend, tcp->funcp, tcp->arg);
+
+    /* Initialization hook.*/
+#if defined(NIL_CFG_THREAD_EXT_INIT_HOOK)
+    NIL_CFG_THREAD_EXT_INIT_HOOK(tp);
+#endif
+
+    tp++, tcp++;
+  }
+
+#if NIL_CFG_ENABLE_STACK_CHECK
+  /* The idle thread is a special case because its stack is set up by the
+     runtime environment.*/
+  tp->stklim  = THD_IDLE_BASE;
+#endif
+
+  /* Runs the highest priority thread, the current one becomes the null
+     thread.*/
+  nil.current = nil.next = nil.threads;
+  port_switch(nil.current, tp);
+
+  /* Interrupts enabled for the idle thread.*/
+  chSysEnable();
+}
+
+/**
+ * @brief   Halts the system.
+ * @details This function is invoked by the operating system when an
+ *          unrecoverable error is detected, for example because a programming
+ *          error in the application code that triggers an assertion while
+ *          in debug mode.
+ * @note    Can be invoked from any system state.
+ *
+ * @special
+ */
+void chSysHalt(const char *reason) {
+
+  port_disable();
+
+#if NIL_DBG_ENABLED
+  nil.dbg_panic_msg = reason;
+#else
+  (void)reason;
+#endif
+
+#if defined(NIL_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+  NIL_CFG_SYSTEM_HALT_HOOK(reason);
+#endif
+
+  /* Harmless infinite loop.*/
+  while (true)
+    ;
+}
+
+/**
+ * @brief   Time management handler.
+ * @note    This handler has to be invoked by a periodic ISR in order to
+ *          reschedule the waiting threads.
+ *
+ * @iclass
+ */
+void chSysTimerHandlerI(void) {
+
+#if NIL_CFG_ST_TIMEDELTA == 0
+  thread_t *tp = &nil.threads[0];
+  nil.systime++;
+  do {
+    /* Is the thread in a wait state with timeout?.*/
+    if (tp->timeout > 0) {
+
+      chDbgAssert(!NIL_THD_IS_READY(tp), "is ready");
+
+     /* Did the timer reach zero?*/
+      if (--tp->timeout == 0) {
+        /* Timeout on semaphores requires a special handling because the
+           semaphore counter must be incremented.*/
+        if (NIL_THD_IS_WTSEM(tp))
+          tp->u1.semp->cnt++;
+        else if (NIL_THD_IS_SUSP(tp))
+          *tp->u1.trp = NULL;
+        chSchReadyI(tp, MSG_TIMEOUT);
+      }
+    }
+    /* Lock released in order to give a preemption chance on those
+       architectures supporting IRQ preemption.*/
+    chSysUnlockFromISR();
+    tp++;
+    chSysLockFromISR();
+  } while (tp < &nil.threads[NIL_CFG_NUM_THREADS]);
+#else
+  thread_t *tp = &nil.threads[0];
+  systime_t next = 0;
+
+  chDbgAssert(nil.nexttime == port_timer_get_alarm(), "time mismatch");
+
+  do {
+    /* Is the thread in a wait state with timeout?.*/
+    if (tp->timeout > 0) {
+
+      chDbgAssert(!NIL_THD_IS_READY(tp), "is ready");
+      chDbgAssert(tp->timeout >= nil.nexttime - nil.lasttime, "skipped one");
+
+      tp->timeout -= nil.nexttime - nil.lasttime;
+      if (tp->timeout == 0) {
+        /* Timeout on semaphores requires a special handling because the
+           semaphore counter must be incremented.*/
+        if (NIL_THD_IS_WTSEM(tp))
+          tp->u1.semp->cnt++;
+        else if (NIL_THD_IS_SUSP(tp))
+          *tp->u1.trp = NULL;
+        chSchReadyI(tp, MSG_TIMEOUT);
+      }
+      else {
+        if (tp->timeout <= next - 1)
+          next = tp->timeout;
+      }
+    }
+    /* Lock released in order to give a preemption chance on those
+       architectures supporting IRQ preemption.*/
+    chSysUnlockFromISR();
+    tp++;
+    chSysLockFromISR();
+  } while (tp < &nil.threads[NIL_CFG_NUM_THREADS]);
+  nil.lasttime = nil.nexttime;
+  if (next > 0) {
+    nil.nexttime += next;
+    port_timer_set_alarm(nil.nexttime);
+  }
+  else {
+    /* No tick event needed.*/
+    port_timer_stop_alarm();
+  }
+#endif
+}
+
+/**
+ * @brief   Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ *          from any context. Because its flexibility it is less efficient
+ *          than @p chSysLock() which is preferable when the calling context
+ *          is known.
+ * @post    The system is in a critical zone.
+ *
+ * @return              The previous system status, the encoding of this
+ *                      status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+syssts_t chSysGetStatusAndLockX(void)  {
+
+  syssts_t sts = port_get_irq_status();
+  if (port_irq_enabled(sts)) {
+    if (port_is_isr_context())
+      chSysLockFromISR();
+    else
+      chSysLock();
+  }
+  return sts;
+}
+
+/**
+ * @brief   Restores the specified execution status and leaves a critical zone.
+ * @note    A call to @p chSchRescheduleS() is automatically performed
+ *          if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts       the system status to be restored.
+ *
+ * @xclass
+ */
+void chSysRestoreStatusX(syssts_t sts) {
+
+  if (port_irq_enabled(sts)) {
+    if (port_is_isr_context())
+      chSysUnlockFromISR();
+    else {
+      chSchRescheduleS();
+      chSysUnlock();
+    }
+  }
+}
+
+/**
+ * @brief   Makes the specified thread ready for execution.
+ *
+ * @param[in] tp        pointer to the @p thread_t object
+ * @param[in] msg       the wakeup message
+ *
+ * @return              The same reference passed as parameter.
+ */
+thread_t *chSchReadyI(thread_t *tp, msg_t msg) {
+
+  chDbgAssert((tp >= nil.threads) &&
+              (tp < &nil.threads[NIL_CFG_NUM_THREADS]),
+              "pointer out of range");
+  chDbgAssert(!NIL_THD_IS_READY(tp), "already ready");
+  chDbgAssert(nil.next <= nil.current, "priority ordering");
+
+  tp->u1.msg = msg;
+  tp->state = NIL_STATE_READY;
+  tp->timeout = 0;
+  if (tp < nil.next)
+    nil.next = tp;
+  return tp;
+}
+
+/**
+ * @brief   Reschedules if needed.
+ *
+ * @sclass
+ */
+void chSchRescheduleS(void) {
+
+  if (chSchIsRescRequiredI()) {
+    thread_t *otp = nil.current;
+
+    nil.current = nil.next;
+#if defined(NIL_CFG_IDLE_LEAVE_HOOK)
+    if (otp == &nil.threads[NIL_CFG_NUM_THREADS]) {
+      NIL_CFG_IDLE_LEAVE_HOOK();
+    }
+#endif
+    port_switch(nil.next, otp);
+  }
+}
+
+/**
+ * @brief   Puts the current thread to sleep into the specified state with
+ *          timeout specification.
+ * @details The thread goes into a sleeping state, if it is not awakened
+ *          explicitly within the specified system time then it is forcibly
+ *          awakened with a @p NIL_MSG_TMO low level message.
+ *
+ * @param[in] newstate  the new thread state or a semaphore pointer
+ * @param[in] timeout   the number of ticks before the operation timeouts.
+ *                      the following special values are allowed:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The wakeup message.
+ * @retval NIL_MSG_TMO  if a timeout occurred.
+ *
+ * @sclass
+ */
+msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t timeout) {
+  thread_t *ntp, *otp = nil.current;
+
+  chDbgAssert(otp != &nil.threads[NIL_CFG_NUM_THREADS],
+               "idle cannot sleep");
+
+  /* Storing the wait object for the current thread.*/
+  otp->state = newstate;
+
+#if NIL_CFG_ST_TIMEDELTA > 0
+  if (timeout != TIME_INFINITE) {
+    systime_t abstime;
+
+    /* TIMEDELTA makes sure to have enough time to reprogram the timer
+       before the free-running timer counter reaches the selected timeout.*/
+    if (timeout < NIL_CFG_ST_TIMEDELTA)
+      timeout = NIL_CFG_ST_TIMEDELTA;
+
+    /* Absolute time of the timeout event.*/
+    abstime = chVTGetSystemTimeX() + timeout;
+
+    if (nil.lasttime == nil.nexttime) {
+      /* Special case, first thread asking for a timeout.*/
+      port_timer_start_alarm(abstime);
+      nil.nexttime = abstime;
+    }
+    else {
+      /* Special case, there are already other threads with a timeout
+         activated, evaluating the order.*/
+      if (chVTIsTimeWithinX(abstime, nil.lasttime, nil.nexttime)) {
+        port_timer_set_alarm(abstime);
+        nil.nexttime = abstime;
+      }
+    }
+
+    /* Timeout settings.*/
+    otp->timeout = abstime - nil.lasttime;
+  }
+#else
+
+  /* Timeout settings.*/
+  otp->timeout = timeout;
+#endif
+
+  /* Scanning the whole threads array.*/
+  ntp = nil.threads;
+  while (true) {
+    /* Is this thread ready to execute?*/
+    if (NIL_THD_IS_READY(ntp)) {
+      nil.current = nil.next = ntp;
+#if defined(NIL_CFG_IDLE_ENTER_HOOK)
+      if (ntp == &nil.threads[NIL_CFG_NUM_THREADS]) {
+        NIL_CFG_IDLE_ENTER_HOOK();
+      }
+#endif
+      port_switch(ntp, otp);
+      return nil.current->u1.msg;
+    }
+
+    /* Points to the next thread in lowering priority order.*/
+    ntp++;
+    chDbgAssert(ntp <= &nil.threads[NIL_CFG_NUM_THREADS],
+                "pointer out of range");
+  }
+}
+
+/**
+ * @brief   Sends the current thread sleeping and sets a reference variable.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The wake up message.
+ *
+ * @sclass
+ */
+msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) {
+
+  chDbgAssert(*trp == NULL, "not NULL");
+
+  *trp = nil.current;
+  nil.current->u1.trp = trp;
+  return chSchGoSleepTimeoutS(NIL_STATE_SUSP, timeout);
+}
+
+/**
+ * @brief   Wakes up a thread waiting on a thread reference object.
+ * @note    This function must not reschedule because it can be called from
+ *          ISR context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+void chThdResumeI(thread_reference_t *trp, msg_t msg) {
+
+  if (*trp != NULL) {
+    thread_reference_t tr = *trp;
+
+    chDbgAssert(NIL_THD_IS_SUSP(tr), "not suspended");
+
+    *trp = NULL;
+    chSchReadyI(tr, msg);
+  }
+}
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time      the delay in system ticks
+ *
+ * @api
+ */
+void chThdSleep(systime_t time) {
+
+  chSysLock();
+
+  chThdSleepS(time);
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Suspends the invoking thread until the system time arrives to the
+ *          specified value.
+ *
+ * @param[in] time      absolute system time
+ *
+ * @api
+ */
+void chThdSleepUntil(systime_t time) {
+
+  chSysLock();
+
+  chThdSleepUntilS(time);
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Performs a wait operation on a semaphore with timeout specification.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval NIL_MSG_OK   if the thread has not stopped on the semaphore or the
+ *                      semaphore has been signaled.
+ * @retval NIL_MSG_RST  if the semaphore has been reset using @p chSemReset().
+ * @retval NIL_MSG_TMO  if the semaphore has not been signaled or reset within
+ *                      the specified timeout.
+ *
+ * @api
+ */
+msg_t chSemWaitTimeout(semaphore_t *sp, systime_t timeout) {
+  msg_t msg;
+
+  chSysLock();
+
+  msg = chSemWaitTimeoutS(sp, timeout);
+
+  chSysUnlock();
+  return msg;
+}
+
+/**
+ * @brief   Performs a wait operation on a semaphore with timeout specification.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval NIL_MSG_OK   if the thread has not stopped on the semaphore or the
+ *                      semaphore has been signaled.
+ * @retval NIL_MSG_RST  if the semaphore has been reset using @p chSemReset().
+ * @retval NIL_MSG_TMO  if the semaphore has not been signaled or reset within
+ *                      the specified timeout.
+ *
+ * @sclass
+ */
+msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t timeout) {
+
+  /* Note, the semaphore counter is a volatile variable so accesses are
+     manually optimized.*/
+  cnt_t cnt = sp->cnt;
+  if (cnt <= 0) {
+    if (TIME_IMMEDIATE == timeout)
+      return MSG_TIMEOUT;
+    sp->cnt = cnt - 1;
+    nil.current->u1.semp = sp;
+    return chSchGoSleepTimeoutS(NIL_STATE_WTSEM, timeout);
+  }
+  sp->cnt = cnt - 1;
+  return MSG_OK;
+}
+
+/**
+ * @brief   Performs a signal operation on a semaphore.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp    pointer to a @p semaphore_t structure
+ *
+ * @api
+ */
+void chSemSignal(semaphore_t *sp) {
+
+  chSysLock();
+
+  chSemSignalI(sp);
+  chSchRescheduleS();
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Performs a signal operation on a semaphore.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp    pointer to a @p semaphore_t structure
+ *
+ * @iclass
+ */
+void chSemSignalI(semaphore_t *sp) {
+
+  if (++sp->cnt <= 0) {
+    thread_reference_t tr = nil.threads;
+    while (true) {
+      /* Is this thread waiting on this semaphore?*/
+      if (tr->u1.semp == sp) {
+
+        chDbgAssert(NIL_THD_IS_WTSEM(tr), "not waiting");
+
+        chSchReadyI(tr, MSG_OK);
+        return;
+      }
+      tr++;
+
+      chDbgAssert(tr < &nil.threads[NIL_CFG_NUM_THREADS],
+                  "pointer out of range");
+    }
+  }
+}
+
+/**
+ * @brief   Performs a reset operation on the semaphore.
+ * @post    After invoking this function all the threads waiting on the
+ *          semaphore, if any, are released and the semaphore counter is set
+ *          to the specified, non negative, value.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @param[in] n         the new value of the semaphore counter. The value must
+ *                      be non-negative.
+ *
+ * @api
+ */
+void chSemReset(semaphore_t *sp, cnt_t n) {
+
+  chSysLock();
+
+  chSemResetI(sp, n);
+  chSchRescheduleS();
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Performs a reset operation on the semaphore.
+ * @post    After invoking this function all the threads waiting on the
+ *          semaphore, if any, are released and the semaphore counter is set
+ *          to the specified, non negative, value.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @param[in] n         the new value of the semaphore counter. The value must
+ *                      be non-negative.
+ *
+ * @iclass
+ */
+void chSemResetI(semaphore_t *sp, cnt_t n) {
+  thread_t *tp;
+  cnt_t cnt;
+
+  cnt = sp->cnt;
+  sp->cnt = n;
+  tp = nil.threads;
+  while (cnt < 0) {
+    /* Is this thread waiting on this semaphore?*/
+    if (tp->u1.semp == sp) {
+
+      chDbgAssert(NIL_THD_IS_WTSEM(tp), "not waiting");
+
+      cnt++;
+      chSchReadyI(tp, MSG_RESET);
+    }
+    tp++;
+
+    chDbgAssert(tp < &nil.threads[NIL_CFG_NUM_THREADS],
+                "pointer out of range");
+  }
+}
+
+/**
+ * @brief   Adds a set of event flags directly to the specified @p thread_t.
+ *
+ * @param[in] tp        the thread to be signaled
+ * @param[in] mask      the event flags set to be ORed
+ *
+ * @api
+ */
+void chEvtSignal(thread_t *tp, eventmask_t mask) {
+
+  chSysLock();
+
+  chEvtSignalI(tp, mask);
+  chSchRescheduleS();
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Adds a set of event flags directly to the specified @p thread_t.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] tp        the thread to be signaled
+ * @param[in] mask      the event flags set to be ORed
+ *
+ * @iclass
+ */
+void chEvtSignalI(thread_t *tp, eventmask_t mask) {
+
+  tp->epmask |= mask;
+  if (NIL_THD_IS_WTOREVT(tp) && ((tp->epmask & tp->u1.ewmask) != 0))
+    chSchReadyI(tp, MSG_OK);
+}
+
+/**
+ * @brief   Waits for any of the specified events.
+ * @details The function waits for any event among those specified in
+ *          @p mask to become pending then the events are cleared and
+ *          returned.
+ *
+ * @param[in] mask      mask of the event flags that the function should wait
+ *                      for, @p ALL_EVENTS enables all the events
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The mask of the served and cleared events.
+ * @retval 0            if the operation has timed out.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t timeout) {
+  eventmask_t m;
+
+  chSysLock();
+
+  m = chEvtWaitAnyTimeoutS(mask, timeout);
+
+  chSysUnlock();
+  return m;
+}
+
+/**
+ * @brief   Waits for any of the specified events.
+ * @details The function waits for any event among those specified in
+ *          @p mask to become pending then the events are cleared and
+ *          returned.
+ *
+ * @param[in] mask      mask of the event flags that the function should wait
+ *                      for, @p ALL_EVENTS enables all the events
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The mask of the served and cleared events.
+ * @retval 0            if the operation has timed out.
+ *
+ * @sclass
+ */
+eventmask_t chEvtWaitAnyTimeoutS(eventmask_t mask, systime_t timeout) {
+  thread_t *ctp = nil.current;
+  eventmask_t m;
+
+  if ((m = (ctp->epmask & mask)) == 0) {
+    if (TIME_IMMEDIATE == timeout) {
+      chSysUnlock();
+      return (eventmask_t)0;
+    }
+    ctp->u1.ewmask = mask;
+    if (chSchGoSleepTimeoutS(NIL_STATE_WTOREVT, timeout) < MSG_OK) {
+      chSysUnlock();
+      return (eventmask_t)0;
+    }
+    m = ctp->epmask & mask;
+  }
+  ctp->epmask &= ~m;
+  return m;
+}
+
+/** @} */
diff --git a/os/nil/templates/nilcore.c b/os/nil/templates/nilcore.c
new file mode 100644
index 000000000..410765079
--- /dev/null
+++ b/os/nil/templates/nilcore.c
@@ -0,0 +1,55 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/nilcore.c
+ * @brief   Port code.
+ *
+ * @addtogroup NIL_CORE
+ * @{
+ */
+
+#include "nil.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/** @} */
diff --git a/os/nil/templates/nilcore.h b/os/nil/templates/nilcore.h
new file mode 100644
index 000000000..61df58bc9
--- /dev/null
+++ b/os/nil/templates/nilcore.h
@@ -0,0 +1,376 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/nilcore.h
+ * @brief   Port macros and structures.
+ *
+ * @addtogroup NIL_CORE
+ * @{
+ */
+
+#ifndef _NILCORE_H_
+#define _NILCORE_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief   Macro defining the port architecture.
+ */
+#define PORT_ARCHITECTURE_XXX
+
+/**
+ * @brief   Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME          "XXX"
+
+/**
+ * @brief   Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME          "XXXX-Y"
+
+/**
+ * @brief   Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME              "GCC " __VERSION__
+
+#else
+#error "unsupported compiler"
+#endif
+
+/**
+ * @brief   Port-specific information string.
+ */
+#define PORT_INFO                       "port description"
+
+/**
+ * @brief   This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT                FALSE
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ *          the idle thread should take no more space than those reserved
+ *          by @p PORT_INT_REQUIRED_STACK.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE     16
+#endif
+
+/**
+ * @brief   Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ *          area size.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK         32
+#endif
+
+/**
+ * @brief   Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ *          @p nilcore_timer.h, if this option is enabled then the file
+ *          @p nilcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER              FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Type of system time.
+ */
+#if (NIL_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
+typedef uint32_t systime_t;
+#else
+typedef uint16_t systime_t;
+#endif
+
+/**
+ * @brief   Type of stack and memory alignment enforcement.
+ */
+typedef uint64_t stkalign_t;
+
+/**
+ * @brief   Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ *          preemption-capable interrupt handler.
+ */
+struct port_extctx {
+
+};
+
+/**
+ * @brief   System saved context.
+ * @details This structure represents the inner stack frame during a context
+ *          switching.
+ */
+struct port_intctx {
+
+};
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Platform dependent thread stack setup.
+ * @details This code usually setup the context switching frame represented
+ *          by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wend, pf, arg) {                             \
+}
+
+/**
+ * @brief   Computes the thread working area global size.
+ * @note    There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) +                       \
+                         sizeof(struct port_extctx) +                       \
+                         (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Fast IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ */
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _port_irq_epilogue(void);
+  void _port_switch(thread_t *ntp, thread_t *otp);
+  void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+}
+
+/**
+ * @brief   Returns a word encoding the current interrupts status.
+ *
+ * @return              The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+  return 0;
+}
+
+/**
+ * @brief   Checks the interrupt status.
+ *
+ * @param[in] sts       the interrupt status word
+ *
+ * @return              The interrupt status.
+ * @retvel false        the word specified a disabled interrupts status.
+ * @retvel true         the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+  return false;
+}
+
+/**
+ * @brief   Determines the current execution context.
+ *
+ * @return              The execution context.
+ * @retval false        not running in ISR mode.
+ * @retval true         running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+  return false;
+}
+
+/**
+ * @brief   Kernel-lock action.
+ */
+static inline void port_lock(void) {
+
+}
+
+/**
+ * @brief   Kernel-unlock action.
+ */
+static inline void port_unlock(void) {
+
+}
+
+/**
+ * @brief   Kernel-lock action from an interrupt handler.
+ */
+static inline void port_lock_from_isr(void) {
+
+}
+
+/**
+ * @brief   Kernel-unlock action from an interrupt handler.
+ */
+static inline void port_unlock_from_isr(void) {
+
+}
+
+/**
+ * @brief   Disables all the interrupt sources.
+ */
+static inline void port_disable(void) {
+
+}
+
+/**
+ * @brief   Disables the interrupt sources below kernel-level priority.
+ */
+static inline void port_suspend(void) {
+
+}
+
+/**
+ * @brief   Enables all the interrupt sources.
+ */
+static inline void port_enable(void) {
+
+}
+
+/**
+ * @brief   Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ *          The simplest implementation is an empty function or macro but this
+ *          would not take advantage of architecture-specific power saving
+ *          modes.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+}
+
+/**
+ * @brief   Returns the current value of the realtime counter.
+ *
+ * @return              The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+  return 0;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module late inclusions.                                                   */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+
+#if NIL_CFG_ST_TIMEDELTA > 0
+#if !PORT_USE_ALT_TIMER
+#include "nilcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "nilcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* NIL_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _NILCORE_H_ */
+
+/** @} */
diff --git a/os/nil/templates/niltypes.h b/os/nil/templates/niltypes.h
new file mode 100644
index 000000000..c7d535a1a
--- /dev/null
+++ b/os/nil/templates/niltypes.h
@@ -0,0 +1,87 @@
+/*
+    ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/NIL.
+
+    ChibiOS/NIL is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/NIL is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/niltypes.h
+ * @brief   Port system types.
+ *
+ * @addtogroup NIL_CORE
+ * @{
+ */
+
+#ifndef _NILTYPES_H_
+#define _NILTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name    Common constants
+ */
+/**
+ * @brief   Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE                   0
+#endif
+
+/**
+ * @brief   Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                    (!FALSE)
+#endif
+/** @} */
+
+typedef uint32_t        syssts_t;       /**< System status word.            */
+typedef uint32_t        rtcnt_t;        /**< Realtime counter.              */
+typedef uint8_t         tstate_t;       /**< Thread state.                  */
+typedef int32_t         msg_t;          /**< Inter-thread message.          */
+typedef uint32_t        eventmask_t;    /**< Mask of event identifiers.     */
+typedef int32_t         cnt_t;          /**< Generic signed counter.        */
+typedef uint32_t        ucnt_t;         /**< Generic unsigned counter.      */
+
+/**
+ * @brief   ROM constant modifier.
+ * @note    It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief   Makes functions not inlineable.
+ * @note    If the compiler does not support such attribute then the
+ *          realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief   Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg)                                       \
+  __attribute__((noreturn)) void tname(void *arg)
+
+/**
+ * @brief   Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+#endif /* _NILTYPES_H_ */
+
+/** @} */
diff --git a/os/ports/GCC/ARM/AT91SAM7/armparams.h b/os/ports/GCC/ARM/AT91SAM7/armparams.h
deleted file mode 100644
index a8c2256a1..000000000
--- a/os/ports/GCC/ARM/AT91SAM7/armparams.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARM/AT91SAM7/armparams.h
- * @brief   ARM7 AT91SAM7 Specific Parameters.
- *
- * @defgroup ARM_AT91SAM7 AT91SAM7 Specific Parameters
- * @ingroup ARM_SPECIFIC
- * @details This file contains the ARM specific parameters for the
- *          AT91SAM7 platform.
- * @{
- */
-
-#ifndef _ARMPARAMS_H_
-#define _ARMPARAMS_H_
-
-/**
- * @brief   ARM core model.
- */
-#define ARM_CORE                ARM_CORE_ARM7TDMI
-
-/**
- * @brief   AT91SAM7-specific wait for interrupt.
- * @details This implementation writes 1 into the PMC_SCDR register.
- */
-#if !defined(port_wait_for_interrupt) || defined(__DOXYGEN__)
-#if ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() {                                         \
-  (*((volatile uint32_t *)0xFFFFFC04)) = 1;                                 \
-}
-#else
-#define port_wait_for_interrupt()
-#endif
-#endif
-
-#endif /* _ARMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7A3.ld b/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7A3.ld
deleted file mode 100644
index 9bca700e6..000000000
--- a/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7A3.ld
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * AT91SAM7A3 memory setup.
- */
-__und_stack_size__	= 0x0004;
-__abt_stack_size__	= 0x0004;
-__fiq_stack_size__	= 0x0010;
-__irq_stack_size__	= 0x0080;
-__svc_stack_size__	= 0x0004;
-__sys_stack_size__	= 0x0400;
-__stacks_total_size__	= __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;
-
-MEMORY
-{
-    flash : org = 0x100000, len = 256k
-    ram : org = 0x200020, len = 32k - 0x20
-}
-
-__ram_start__		= ORIGIN(ram);
-__ram_size__		= LENGTH(ram);
-__ram_end__		= __ram_start__ + __ram_size__;
-
-SECTIONS
-{
-	. = 0;
-
-	.text : ALIGN(16) SUBALIGN(16)
-	{
-        _text = .;
-        KEEP(*(vectors))
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.ctors)
-        *(.dtors)
-    } > flash
-
-    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}
-
-    __exidx_start = .;
-    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash
-    __exidx_end = .;
-
-    .eh_frame_hdr : {*(.eh_frame_hdr)}
-
-    .eh_frame : ONLY_IF_RO {*(.eh_frame)}
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .data :
-    {
-        _data = .;
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        _edata = .;
-    } > ram AT > flash
-
-    .bss :
-    {
-        _bss_start = .;
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        _bss_end = .;
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__              = _end;
-__heap_end__               = __ram_end__ - __stacks_total_size__;
-__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__;
diff --git a/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7S256.ld b/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7S256.ld
deleted file mode 100644
index 9af8083e8..000000000
--- a/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7S256.ld
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * AT91SAM7S256 memory setup.
- */
-__und_stack_size__	= 0x0004;
-__abt_stack_size__	= 0x0004;
-__fiq_stack_size__	= 0x0010;
-__irq_stack_size__	= 0x0080;
-__svc_stack_size__	= 0x0004;
-__sys_stack_size__	= 0x0400;
-__stacks_total_size__	= __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;
-
-MEMORY
-{
-    flash : org = 0x100000, len = 256k
-    ram : org = 0x200020, len = 64k - 0x20
-}
-
-__ram_start__		= ORIGIN(ram);
-__ram_size__		= LENGTH(ram);
-__ram_end__		= __ram_start__ + __ram_size__;
-
-SECTIONS
-{
-	. = 0;
-
-	.text : ALIGN(16) SUBALIGN(16)
-	{
-        _text = .;
-        KEEP(*(vectors))
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.ctors)
-        *(.dtors)
-    } > flash
-
-    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}
-
-    __exidx_start = .;
-    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash
-    __exidx_end = .;
-
-    .eh_frame_hdr : {*(.eh_frame_hdr)}
-
-    .eh_frame : ONLY_IF_RO {*(.eh_frame)}
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .data :
-    {
-        _data = .;
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        _edata = .;
-    } > ram AT > flash
-
-    .bss :
-    {
-        _bss_start = .;
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        _bss_end = .;
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__              = _end;
-__heap_end__               = __ram_end__ - __stacks_total_size__;
-__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__;
diff --git a/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7X256.ld b/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7X256.ld
deleted file mode 100644
index 855d2c486..000000000
--- a/os/ports/GCC/ARM/AT91SAM7/ld/AT91SAM7X256.ld
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * AT91SAM7X256 memory setup.
- */
-__und_stack_size__	= 0x0004;
-__abt_stack_size__	= 0x0004;
-__fiq_stack_size__	= 0x0010;
-__irq_stack_size__	= 0x0080;
-__svc_stack_size__	= 0x0004;
-__sys_stack_size__	= 0x0400;
-__stacks_total_size__	= __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;
-
-MEMORY
-{
-    flash : org = 0x100000, len = 256k
-    ram : org = 0x200020, len = 64k - 0x20
-}
-
-__ram_start__		= ORIGIN(ram);
-__ram_size__		= LENGTH(ram);
-__ram_end__		= __ram_start__ + __ram_size__;
-
-SECTIONS
-{
-	. = 0;
-
-	.text : ALIGN(16) SUBALIGN(16)
-	{
-        _text = .;
-        KEEP(*(vectors))
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.ctors)
-        *(.dtors)
-    } > flash
-
-    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}
-
-    __exidx_start = .;
-    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash
-    __exidx_end = .;
-
-    .eh_frame_hdr : {*(.eh_frame_hdr)}
-
-    .eh_frame : ONLY_IF_RO {*(.eh_frame)}
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .data :
-    {
-        _data = .;
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        _edata = .;
-    } > ram AT > flash
-
-    .bss :
-    {
-        _bss_start = .;
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        _bss_end = .;
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__              = _end;
-__heap_end__               = __ram_end__ - __stacks_total_size__;
-__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__;
diff --git a/os/ports/GCC/ARM/AT91SAM7/port.mk b/os/ports/GCC/ARM/AT91SAM7/port.mk
deleted file mode 100644
index 2cafd01aa..000000000
--- a/os/ports/GCC/ARM/AT91SAM7/port.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# List of the ChibiOS/RT ARM7 AT91SAM7 port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/ARM/chcore.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/ARM/crt0.s \
-          ${CHIBIOS}/os/ports/GCC/ARM/chcoreasm.s \
-          ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7/vectors.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/ARM \
-          ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7/ld
diff --git a/os/ports/GCC/ARM/AT91SAM7/vectors.s b/os/ports/GCC/ARM/AT91SAM7/vectors.s
deleted file mode 100644
index c9ab881ad..000000000
--- a/os/ports/GCC/ARM/AT91SAM7/vectors.s
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARM/AT91SAM7/vectors.s
- * @brief   Interrupt vectors for the AT91SAM7 family.
- *
- * @defgroup ARM_AT91SAM7_VECTORS AT91SAM7 Interrupt Vectors
- * @ingroup ARM_SPECIFIC
- * @details Interrupt vectors for the AT91SAM7 family.
- * @{
- */
-
-#if defined(__DOXYGEN__)
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-void _unhandled_exception(void) {}
-#endif
-
-#if !defined(__DOXYGEN__)
-
-.section vectors
-.code 32
-.balign 4
-/*
- * System entry points.
- */
-_start:
-        ldr     pc, _reset
-        ldr     pc, _undefined
-        ldr     pc, _swi
-        ldr     pc, _prefetch
-        ldr     pc, _abort
-        nop
-        ldr     pc, [pc,#-0xF20]        /* AIC - AIC_IVR */
-        ldr     pc, [pc,#-0xF20]        /* AIC - AIC_FVR */
-
-_reset:
-        .word   ResetHandler            /* In crt0.s */
-_undefined:
-        .word   UndHandler
-_swi:
-        .word   SwiHandler
-_prefetch:
-        .word   PrefetchHandler
-_abort:
-        .word   AbortHandler
-        .word   0
-        .word   0
-        .word   0
-
-.text
-.code 32
-.balign 4
-
-/*
- * Default exceptions handlers. The handlers are declared weak in order to be
- * replaced by the real handling code. Everything is defaulted to an infinite
- * loop.
- */
-.weak UndHandler
-UndHandler:
-
-.weak SwiHandler
-SwiHandler:
-
-.weak PrefetchHandler
-PrefetchHandler:
-
-.weak AbortHandler
-AbortHandler:
-
-.weak FiqHandler
-FiqHandler:
-
-.global _unhandled_exception
-_unhandled_exception:
-        b       _unhandled_exception
-
-#endif
-
-/** @} */
diff --git a/os/ports/GCC/ARM/AT91SAM7/wfi.h b/os/ports/GCC/ARM/AT91SAM7/wfi.h
deleted file mode 100644
index 1cb7e6f40..000000000
--- a/os/ports/GCC/ARM/AT91SAM7/wfi.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#ifndef _WFI_H_
-#define _WFI_H_
-
-#include "board.h"
-
-#ifndef port_wait_for_interrupt
-#if ENABLE_WFI_IDLE != 0
-#define port_wait_for_interrupt() {                                     \
-  AT91C_BASE_SYS->PMC_SCDR = AT91C_PMC_PCK;                             \
-}
-#else
-#define port_wait_for_interrupt()
-#endif
-#endif
-
-#endif /* _WFI_H_ */
diff --git a/os/ports/GCC/ARM/LPC214x/armparams.h b/os/ports/GCC/ARM/LPC214x/armparams.h
deleted file mode 100644
index d22063d36..000000000
--- a/os/ports/GCC/ARM/LPC214x/armparams.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARM/LPC214x/armparams.h
- * @brief   ARM7 LPC214x Specific Parameters.
- *
- * @defgroup ARM_LPC214x LPC214x Specific Parameters
- * @ingroup ARM_SPECIFIC
- * @details This file contains the ARM specific parameters for the
- *          LPC214x platform.
- * @{
- */
-
-#ifndef _ARMPARAMS_H_
-#define _ARMPARAMS_H_
-
-/**
- * @brief   ARM core model.
- */
-#define ARM_CORE                ARM_CORE_ARM7TDMI
-
-/**
- * @brief   LPC214x-specific wait for interrupt code.
- * @details This implementation writes 1 into the PCON register.
- */
-#if !defined(port_wait_for_interrupt) || defined(__DOXYGEN__)
-#if ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() {                                         \
-  (*((volatile uint32_t *)0xE01FC0C0)) = 1;                                 \
-}
-#else
-#define port_wait_for_interrupt()
-#endif
-#endif
-
-#endif /* _ARMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARM/LPC214x/ld/LPC2148.ld b/os/ports/GCC/ARM/LPC214x/ld/LPC2148.ld
deleted file mode 100644
index e3d284a89..000000000
--- a/os/ports/GCC/ARM/LPC214x/ld/LPC2148.ld
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC2148 memory setup.
- */
-__und_stack_size__	= 0x0004;
-__abt_stack_size__	= 0x0004;
-__fiq_stack_size__	= 0x0010;
-__irq_stack_size__	= 0x0080;
-__svc_stack_size__	= 0x0004;
-__sys_stack_size__	= 0x0400;
-__stacks_total_size__	= __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 512k - 12k
-    ram : org = 0x40000200, len = 32k - 0x200 - 288
-}
-
-__ram_start__       = ORIGIN(ram);
-__ram_size__        = LENGTH(ram);
-__ram_end__         = __ram_start__ + __ram_size__;
-__dma_start__       = 0x7FD00000;
-__dma_size__        = 8k;
-__dma_end__         = 0x7FD00000 + __dma_size__;
-
-SECTIONS
-{
-    . = 0;
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        _text = .;
-        KEEP(*(vectors))
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.ctors)
-        *(.dtors)
-    } > flash
-
-    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}
-
-    __exidx_start = .;
-    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash
-    __exidx_end = .;
-
-    .eh_frame_hdr : {*(.eh_frame_hdr)}
-
-    .eh_frame : ONLY_IF_RO {*(.eh_frame)}
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .data :
-    {
-        _data = .;
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        _edata = .;
-    } > ram AT > flash
-
-    .bss :
-    {
-        _bss_start = .;
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        _bss_end = .;
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end = .;
-
-__heap_base__		       = _end;
-__heap_end__		       = __ram_end__ - __stacks_total_size__;
-__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__;
diff --git a/os/ports/GCC/ARM/LPC214x/port.mk b/os/ports/GCC/ARM/LPC214x/port.mk
deleted file mode 100644
index 339f1d66a..000000000
--- a/os/ports/GCC/ARM/LPC214x/port.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# List of the ChibiOS/RT ARM7 LPC214x port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/ARM/chcore.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/ARM/crt0.s \
-          ${CHIBIOS}/os/ports/GCC/ARM/chcoreasm.s \
-          ${CHIBIOS}/os/ports/GCC/ARM/LPC214x/vectors.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/ARM \
-          ${CHIBIOS}/os/ports/GCC/ARM/LPC214x
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARM/LPC214x/ld
diff --git a/os/ports/GCC/ARM/LPC214x/vectors.s b/os/ports/GCC/ARM/LPC214x/vectors.s
deleted file mode 100644
index bd554d6b9..000000000
--- a/os/ports/GCC/ARM/LPC214x/vectors.s
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARM/LPC214x/vectors.s
- * @brief   Interrupt vectors for the LPC214x family.
- *
- * @defgroup ARM_LPC214x_VECTORS LPC214x Interrupt Vectors
- * @ingroup ARM_SPECIFIC
- * @details Interrupt vectors for the LPC214x family.
- * @{
- */
-
-#if defined(__DOXYGEN__)
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-void _unhandled_exception(void) {}
-#endif
-
-#if !defined(__DOXYGEN__)
-
-.section vectors
-.code 32
-.balign 4
-/*
- * System entry points.
- */
-_start:
-        ldr     pc, _reset
-        ldr     pc, _undefined
-        ldr     pc, _swi
-        ldr     pc, _prefetch
-        ldr     pc, _abort
-        nop
-        ldr     pc, [pc,#-0xFF0]        /* VIC - IRQ Vector Register */
-        ldr     pc, _fiq
-
-_reset:
-        .word   ResetHandler            /* In crt0.s */
-_undefined:
-        .word   UndHandler
-_swi:
-        .word   SwiHandler
-_prefetch:
-        .word   PrefetchHandler
-_abort:
-        .word   AbortHandler
-_fiq:
-        .word   FiqHandler
-        .word   0
-        .word   0
-
-/*
- * Default exceptions handlers. The handlers are declared weak in order to be
- * replaced by the real handling code. Everything is defaulted to an infinite
- * loop.
- */
-.weak UndHandler
-UndHandler:
-
-.weak SwiHandler
-SwiHandler:
-
-.weak PrefetchHandler
-PrefetchHandler:
-
-.weak AbortHandler
-AbortHandler:
-
-.weak FiqHandler
-FiqHandler:
-
-.global _unhandled_exception
-_unhandled_exception:
-        b       _unhandled_exception
-
-#endif
-
-/** @} */
diff --git a/os/ports/GCC/ARM/LPC214x/wfi.h b/os/ports/GCC/ARM/LPC214x/wfi.h
deleted file mode 100644
index 765e6499d..000000000
--- a/os/ports/GCC/ARM/LPC214x/wfi.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#ifndef _WFI_H_
-#define _WFI_H_
-
-#include "lpc214x.h"
-
-#ifndef port_wait_for_interrupt
-#if ENABLE_WFI_IDLE != 0
-#define port_wait_for_interrupt() {                                     \
-  PCON = 1;                                                             \
-}
-#else
-#define port_wait_for_interrupt()
-#endif
-#endif
-
-#endif /* _WFI_H_ */
diff --git a/os/ports/GCC/ARM/chcore.c b/os/ports/GCC/ARM/chcore.c
deleted file mode 100644
index 3c348c964..000000000
--- a/os/ports/GCC/ARM/chcore.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARM/chcore.c
- * @brief   ARM7/9 architecture port code.
- *
- * @addtogroup ARM_CORE
- * @{
- */
-
-#include "ch.h"
-
-/**
- * Halts the system.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/** @} */
diff --git a/os/ports/GCC/ARM/chcore.h b/os/ports/GCC/ARM/chcore.h
deleted file mode 100644
index d1b6a1e12..000000000
--- a/os/ports/GCC/ARM/chcore.h
+++ /dev/null
@@ -1,478 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARM/chcore.h
- * @brief   ARM7/9 architecture port macros and structures.
- *
- * @addtogroup ARM_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-/*===========================================================================*/
-/* Port constants.                                                           */
-/*===========================================================================*/
-
-/* Core variants identifiers.*/
-#define ARM_CORE_ARM7TDMI           7   /**< ARM77TDMI core identifier.     */
-#define ARM_CORE_ARM9               9   /**< ARM9 core identifier.          */
-
-/* Inclusion of the ARM implementation specific parameters.*/
-#include "armparams.h"
-
-/* ARM core check, only ARM7TDMI and ARM9 supported right now.*/
-#if (ARM_CORE == ARM_CORE_ARM7TDMI) || (ARM_CORE == ARM_CORE_ARM9)
-#else
-#error "unknown or unsupported ARM core"
-#endif
-
-/*===========================================================================*/
-/* Port statically derived parameters.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port macros.                                                              */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   If enabled allows the idle thread to enter a low power mode.
- */
-#ifndef ARM_ENABLE_WFI_IDLE
-#define ARM_ENABLE_WFI_IDLE             FALSE
-#endif
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Macro defining a generic ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM
-
-#if defined(__DOXYGEN__)
-/**
- * @brief   Macro defining the specific ARM architecture.
- * @note    This macro is for documentation only, the real name changes
- *          depending on the selected architecture, the possible names are:
- *          - CH_ARCHITECTURE_ARM7TDMI.
- *          - CH_ARCHITECTURE_ARM9.
- *          .
- */
-#define CH_ARCHITECTURE_ARMx
-
-/**
- * @brief   Name of the implemented architecture.
- * @note    The value is for documentation only, the real value changes
- *          depending on the selected architecture, the possible values are:
- *          - "ARM7".
- *          - "ARM9".
- *          .
- */
-#define CH_ARCHITECTURE_NAME            "ARMx"
-
-/**
- * @brief   Name of the architecture variant (optional).
- * @note    The value is for documentation only, the real value changes
- *          depending on the selected architecture, the possible values are:
- *          - "ARM7TDMI"
- *          - "ARM9"
- *          .
- */
-#define CH_CORE_VARIANT_NAME            "ARMxy"
-
-/**
- * @brief   Port-specific information string.
- * @note    The value is for documentation only, the real value changes
- *          depending on the selected options, the possible values are:
- *          - "Pure ARM"
- *          - "Pure THUMB"
- *          - "Interworking"
- *          .
- */
-#define CH_PORT_INFO                    "ARM|THUMB|Interworking"
-
-#elif ARM_CORE == ARM_CORE_ARM7TDMI
-#define CH_ARCHITECTURE_ARM7TDMI
-#define CH_ARCHITECTURE_NAME            "ARM7"
-#define CH_CORE_VARIANT_NAME            "ARM7TDMI"
-
-#elif ARM_MODEL == ARM_VARIANT_ARM9
-#define CH_ARCHITECTURE_ARM9
-#define CH_ARCHITECTURE_NAME            "ARM9"
-#define CH_CORE_VARIANT_NAME            "ARM9"
-#endif
-
-#if THUMB_PRESENT
-#if THUMB_NO_INTERWORKING
-#define CH_PORT_INFO                    "Pure THUMB mode"
-#else /* !THUMB_NO_INTERWORKING */
-#define CH_PORT_INFO                    "Interworking mode"
-#endif /* !THUMB_NO_INTERWORKING */
-#else /* !THUMB_PRESENT */
-#define CH_PORT_INFO                    "Pure ARM mode"
-#endif /* !THUMB_PRESENT */
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "GCC " __VERSION__
-
-/*===========================================================================*/
-/* Port implementation part (common).                                        */
-/*===========================================================================*/
-
-/**
- * @brief   32 bits stack and memory alignment enforcement.
- */
-typedef uint32_t stkalign_t;
-
-/**
- * @brief   Generic ARM register.
- */
-typedef void *regarm_t;
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- */
-struct extctx {
-  regarm_t      spsr_irq;
-  regarm_t      lr_irq;
-  regarm_t      r0;
-  regarm_t      r1;
-  regarm_t      r2;
-  regarm_t      r3;
-  regarm_t      r12;
-  regarm_t      lr_usr;
-};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching.
- */
-struct intctx {
-  regarm_t      r4;
-  regarm_t      r5;
-  regarm_t      r6;
-  regarm_t      r7;
-  regarm_t      r8;
-  regarm_t      r9;
-  regarm_t      r10;
-  regarm_t      r11;
-  regarm_t      lr;
-};
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- *          structure representing the stack pointer at context switch time.
- */
-struct context {
-  struct intctx *r13;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
-                                     wsize -                                \
-                                     sizeof(struct intctx));                \
-  tp->p_ctx.r13->r4 = pf;                                                   \
-  tp->p_ctx.r13->r5 = arg;                                                  \
-  tp->p_ctx.r13->lr = _port_thread_start;                                   \
-}
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- * @note    In this port it is set to 4 because the idle thread does have
- *          a stack frame when compiling without optimizations.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     4
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- *          This value can be zero on those architecture where there is a
- *          separate interrupt stack and the stack space between @p intctx and
- *          @p extctx is known to be zero.
- * @note    In this port 0x10 is a safe value, it can be reduced after careful
- *          analysis of the generated code.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK         0x10
-#endif
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- * @note    This macro has a different implementation depending if compiled in
- *          ARM or THUMB mode.
- * @note    The THUMB implementation starts with ARM code because interrupt
- *          vectors are always invoked in ARM mode regardless the bit 0
- *          value. The switch in THUMB mode is done in the function prologue so
- *          it is transparent to the user code.
- */
-#if !defined(PORT_IRQ_PROLOGUE)
-#ifdef THUMB
-#define PORT_IRQ_PROLOGUE() {                                               \
-  asm volatile (".code 32                               \n\t"               \
-                "stmfd   sp!, {r0-r3, r12, lr}          \n\t"               \
-                "add     r0, pc, #1                     \n\t"               \
-                "bx      r0                             \n\t"               \
-                ".code 16" : : : "memory");                                 \
-}
-#else /* !THUMB */
-#define PORT_IRQ_PROLOGUE() {                                               \
-  asm volatile ("stmfd    sp!, {r0-r3, r12, lr}" : : : "memory");           \
-}
-#endif /* !THUMB */
-#endif /* !defined(PORT_IRQ_PROLOGUE) */
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- * @note    This macro has a different implementation depending if compiled in
- *          ARM or THUMB mode.
- */
-#if !defined(PORT_IRQ_EPILOGUE)
-#ifdef THUMB
-#define PORT_IRQ_EPILOGUE() {                                               \
-  asm volatile ("ldr     r0, =_port_irq_common          \n\t"               \
-                "bx      r0" : : : "memory");                               \
-}
-#else /* !THUMB */
-#define PORT_IRQ_EPILOGUE() {                                               \
-  asm volatile ("b       _port_irq_common" : : : "memory");                 \
-}
-#endif /* !THUMB */
-#endif /* !defined(PORT_IRQ_EPILOGUE) */
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#if !defined(PORT_IRQ_HANDLER)
-#define PORT_IRQ_HANDLER(id) __attribute__((naked)) void id(void)
-#endif /* !defined(PORT_IRQ_HANDLER) */
-
-/**
- * @brief   Fast IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#if !defined(PORT_FAST_IRQ_HANDLER)
-#define PORT_FAST_IRQ_HANDLER(id)                                           \
-  __attribute__((interrupt("FIQ"))) void id(void)
-#endif /* !defined(PORT_FAST_IRQ_HANDLER) */
-
-/**
- * @brief   Port-related initialization code.
- * @note    This function is empty in this port.
- */
-#define port_init()
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform
- *          more actions.
- * @note    In this port it disables the IRQ sources and keeps FIQ sources
- *          enabled.
- */
-#ifdef THUMB
-#define port_lock() {                                                       \
-  asm volatile ("bl     _port_lock_thumb" : : : "r3", "lr", "memory");      \
-}
-#else /* !THUMB */
-#define port_lock() asm volatile ("msr     CPSR_c, #0x9F" : : : "memory")
-#endif /* !THUMB */
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform
- *          more actions.
- * @note    In this port it enables both the IRQ and FIQ sources.
- */
-#ifdef THUMB
-#define port_unlock() {                                                     \
-  asm volatile ("bl     _port_unlock_thumb" : : : "r3", "lr", "memory");    \
-}
-#else /* !THUMB */
-#define port_unlock() asm volatile ("msr     CPSR_c, #0x1F" : : : "memory")
-#endif /* !THUMB */
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependent,
- *          in its simplest form it is void.
- * @note    Empty in this port.
- */
-#define port_lock_from_isr()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- * @note    Empty in this port.
- */
-#define port_unlock_from_isr()
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Of course non-maskable interrupt sources are not included.
- * @note    In this port it disables both the IRQ and FIQ sources.
- * @note    Implements a workaround for spurious interrupts taken from the NXP
- *          LPC214x datasheet.
- */
-#ifdef THUMB
-#define port_disable() {                                                    \
-  asm volatile ("bl     _port_disable_thumb" : : : "r3", "lr", "memory");   \
-}
-#else /* !THUMB */
-#define port_disable() {                                                    \
-  asm volatile ("mrs     r3, CPSR                       \n\t"               \
-                "orr     r3, #0x80                      \n\t"               \
-                "msr     CPSR_c, r3                     \n\t"               \
-                "orr     r3, #0x40                      \n\t"               \
-                "msr     CPSR_c, r3" : : : "r3", "memory");                 \
-}
-#endif /* !THUMB */
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- * @note    Interrupt sources above kernel level remains enabled.
- * @note    In this port it disables the IRQ sources and enables the
- *          FIQ sources.
- */
-#ifdef THUMB
-#define port_suspend() {                                                    \
-  asm volatile ("bl     _port_suspend_thumb" : : : "r3", "lr", "memory");   \
-}
-#else /* !THUMB */
-#define port_suspend() asm volatile ("msr     CPSR_c, #0x9F" : : : "memory")
-#endif /* !THUMB */
-
-/**
- * @brief   Enables all the interrupt sources.
- * @note    In this port it enables both the IRQ and FIQ sources.
- */
-#ifdef THUMB
-#define port_enable() {                                                     \
-  asm volatile ("bl     _port_enable_thumb" : : : "r3", "lr", "memory");    \
-}
-#else /* !THUMB */
-#define port_enable() asm volatile ("msr     CPSR_c, #0x1F" : : : "memory")
-#endif /* !THUMB */
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- * @note    Implemented as inlined code for performance reasons.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#ifdef THUMB
-#if CH_DBG_ENABLE_STACK_CHECK
-#define port_switch(ntp, otp) {                                             \
-  register struct intctx *r13 asm ("r13");                                  \
-  if ((stkalign_t *)(r13 - 1) < otp->p_stklimit)                            \
-    chDbgPanic("stack overflow");                                           \
-  _port_switch_thumb(ntp, otp);                                             \
-}
-#else /* !CH_DBG_ENABLE_STACK_CHECK */
-#define port_switch(ntp, otp) _port_switch_thumb(ntp, otp)
-#endif /* !CH_DBG_ENABLE_STACK_CHECK */
-#else /* !THUMB */
-#if CH_DBG_ENABLE_STACK_CHECK
-#define port_switch(ntp, otp) {                                             \
-  register struct intctx *r13 asm ("r13");                                  \
-  if ((stkalign_t *)(r13 - 1) < otp->p_stklimit)                            \
-    chDbgPanic("stack overflow");                                           \
-  _port_switch_arm(ntp, otp);                                               \
-}
-#else /* !CH_DBG_ENABLE_STACK_CHECK */
-#define port_switch(ntp, otp) _port_switch_arm(ntp, otp)
-#endif /* !CH_DBG_ENABLE_STACK_CHECK */
-#endif /* !THUMB */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_halt(void);
-#ifdef THUMB
-  void _port_switch_thumb(Thread *ntp, Thread *otp);
-#else /* !THUMB */
-  void _port_switch_arm(Thread *ntp, Thread *otp);
-#endif /* !THUMB */
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARM/chcoreasm.s b/os/ports/GCC/ARM/chcoreasm.s
deleted file mode 100644
index 221ae4aec..000000000
--- a/os/ports/GCC/ARM/chcoreasm.s
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARM/chcoreasm.s
- * @brief   ARM7/9 architecture port low level code.
- *
- * @addtogroup ARM_CORE
- * @{
- */
-
-#include "chconf.h"
-
-#define FALSE 0
-#define TRUE 1
-
-#if !defined(__DOXYGEN__)
-
-.set    MODE_USR, 0x10
-.set    MODE_FIQ, 0x11
-.set    MODE_IRQ, 0x12
-.set    MODE_SVC, 0x13
-.set    MODE_ABT, 0x17
-.set    MODE_UND, 0x1B
-.set    MODE_SYS, 0x1F
-
-.equ    I_BIT, 0x80
-.equ    F_BIT, 0x40
-
-.text
-
-/*
- * Interrupt enable/disable functions, only present if there is THUMB code in
- * the system because those are inlined in ARM code.
- */
-#ifdef THUMB_PRESENT
-.balign 16
-.code 16
-.thumb_func
-.global _port_disable_thumb
-_port_disable_thumb:
-        mov     r3, pc
-        bx      r3
-.code 32
-        mrs     r3, CPSR
-        orr     r3, #I_BIT
-        msr     CPSR_c, r3
-        orr     r3, #F_BIT
-        msr     CPSR_c, r3
-        bx      lr
-
-.balign 16
-.code 16
-.thumb_func
-.global _port_suspend_thumb
-_port_suspend_thumb:
-.thumb_func
-.global _port_lock_thumb
-_port_lock_thumb:
-        mov     r3, pc
-        bx      r3
-.code 32
-        msr     CPSR_c, #MODE_SYS | I_BIT
-        bx      lr
-
-.balign 16
-.code 16
-.thumb_func
-.global _port_enable_thumb
-_port_enable_thumb:
-.thumb_func
-.global _port_unlock_thumb
-_port_unlock_thumb:
-        mov     r3, pc
-        bx      r3
-.code 32
-        msr     CPSR_c, #MODE_SYS
-        bx      lr
-
-#endif
-
-.balign 16
-#ifdef THUMB_PRESENT
-.code 16
-.thumb_func
-.global _port_switch_thumb
-_port_switch_thumb:
-        mov     r2, pc
-        bx      r2
-        // Jumps into _port_switch_arm in ARM mode
-#endif
-.code 32
-.global _port_switch_arm
-_port_switch_arm:
-#ifdef CH_CURRP_REGISTER_CACHE
-        stmfd   sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
-        str     sp, [r1, #12]
-        ldr     sp, [r0, #12]
-#ifdef THUMB_PRESENT
-        ldmfd   sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
-        bx      lr
-#else /* !THUMB_PRESENT */
-        ldmfd   sp!, {r4, r5, r6, r8, r9, r10, r11, pc}
-#endif /* !THUMB_PRESENT */
-#else /* !CH_CURRP_REGISTER_CACHE */
-        stmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-        str     sp, [r1, #12]
-        ldr     sp, [r0, #12]
-#ifdef THUMB_PRESENT
-        ldmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-        bx      lr
-#else /* !THUMB_PRESENT */
-        ldmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
-#endif /* !THUMB_PRESENT */
-#endif /* !CH_CURRP_REGISTER_CACHE */
-
-/*
- * Common exit point for all IRQ routines, it performs the rescheduling if
- * required.
- * System stack frame structure after a context switch in the
- * interrupt handler:
- *
- * High +------------+
- *      |   LR_USR   | -+
- *      |     R12    |  |
- *      |     R3     |  |
- *      |     R2     |  | External context: IRQ handler frame
- *      |     R1     |  |
- *      |     R0     |  |
- *      |     PC     |  |   (user code return address)
- *      |   PSR_USR  | -+   (user code status)
- *      |    ....    | <- chSchDoReschedule() stack frame, optimize it for space
- *      |     LR     | -+   (system code return address)
- *      |     R11    |  |
- *      |     R10    |  |
- *      |     R9     |  |
- *      |     R8     |  | Internal context: chSysSwitch() frame
- *      |    (R7)    |  |   (optional, see CH_CURRP_REGISTER_CACHE)
- *      |     R6     |  |
- *      |     R5     |  |
- * SP-> |     R4     | -+
- * Low  +------------+
- */
-.balign 16
-#ifdef THUMB_NO_INTERWORKING
-.code 16
-.thumb_func
-.globl _port_irq_common
-_port_irq_common:
-        bl      chSchIsPreemptionRequired
-        mov     lr, pc
-        bx      lr
-.code 32
-#else /* !THUMB_NO_INTERWORKING */
-.code 32
-.globl _port_irq_common
-_port_irq_common:
-        bl      chSchIsPreemptionRequired
-#endif /* !THUMB_NO_INTERWORKING */
-        cmp     r0, #0                          // Simply returns if a
-        ldmeqfd sp!, {r0-r3, r12, lr}           // reschedule is not
-        subeqs  pc, lr, #4                      // required.
-
-        // Saves the IRQ mode registers in the system stack.
-        ldmfd   sp!, {r0-r3, r12, lr}           // IRQ stack now empty.
-        msr     CPSR_c, #MODE_SYS | I_BIT
-        stmfd   sp!, {r0-r3, r12, lr}           // Registers on System Stack.
-        msr     CPSR_c, #MODE_IRQ | I_BIT
-        mrs     r0, SPSR
-        mov     r1, lr
-        msr     CPSR_c, #MODE_SYS | I_BIT
-        stmfd   sp!, {r0, r1}                   // Push R0=SPSR, R1=LR_IRQ.
-
-        // Context switch.
-#ifdef THUMB_NO_INTERWORKING
-        add     r0, pc, #1
-        bx      r0
-.code 16
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_lock
-#endif
-        bl      chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_unlock
-#endif
-        mov     lr, pc
-        bx      lr
-.code 32
-#else /* !THUMB_NO_INTERWORKING */
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_lock
-#endif
-        bl      chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_unlock
-#endif
-#endif /* !THUMB_NO_INTERWORKING */
-
-        // Re-establish the IRQ conditions again.
-        ldmfd   sp!, {r0, r1}                   // Pop R0=SPSR, R1=LR_IRQ.
-        msr     CPSR_c, #MODE_IRQ | I_BIT
-        msr     SPSR_fsxc, r0
-        mov     lr, r1
-        msr     CPSR_c, #MODE_SYS | I_BIT
-        ldmfd   sp!, {r0-r3, r12, lr}
-        msr     CPSR_c, #MODE_IRQ | I_BIT
-        subs    pc, lr, #4
-
-/*
- * Threads trampoline code.
- * NOTE: The threads always start in ARM mode and then switches to the
- * thread-function mode.
- */
-.balign 16
-.code 32
-.globl _port_thread_start
-_port_thread_start:
-#if CH_DBG_SYSTEM_STATE_CHECK
-        mov     r0, #0
-        ldr     r1, =dbg_lock_cnt
-        str     r0, [r1]
-#endif
-        msr     CPSR_c, #MODE_SYS
-#ifndef THUMB_NO_INTERWORKING
-        mov     r0, r5
-        mov     lr, pc
-        bx      r4
-        bl      chThdExit
-#else /* !THUMB_NO_INTERWORKING */
-        add     r0, pc, #1
-        bx      r0
-.code 16
-        mov     r0, r5
-        bl      jmpr4
-        bl      chThdExit
-jmpr4:
-        bx      r4
-#endif /* !THUMB_NO_INTERWORKING */
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/ARM/chtypes.h b/os/ports/GCC/ARM/chtypes.h
deleted file mode 100644
index 36bebf14f..000000000
--- a/os/ports/GCC/ARM/chtypes.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARM/chtypes.h
- * @brief   ARM7/9 architecture port system types.
- *
- * @addtogroup ARM_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint32_t        tprio_t;        /**< Thread priority.               */
-typedef int32_t         msg_t;          /**< Inter-thread message.          */
-typedef int32_t         eventid_t;      /**< Event Id.                      */
-typedef uint32_t        eventmask_t;    /**< Event mask.                    */
-typedef uint32_t        flagsmask_t;    /**< Event flags.                   */
-typedef uint32_t        systime_t;      /**< System time.                   */
-typedef int32_t         cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    It uses the "packed" GCC attribute.
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARM/crt0.s b/os/ports/GCC/ARM/crt0.s
deleted file mode 100644
index 74df7f74e..000000000
--- a/os/ports/GCC/ARM/crt0.s
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARM/crt0.s
- * @brief   Generic ARM7/9 startup file for ChibiOS/RT.
- *
- * @addtogroup ARM_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        .set    MODE_USR, 0x10
-        .set    MODE_FIQ, 0x11
-        .set    MODE_IRQ, 0x12
-        .set    MODE_SVC, 0x13
-        .set    MODE_ABT, 0x17
-        .set    MODE_UND, 0x1B
-        .set    MODE_SYS, 0x1F
-
-        .set    I_BIT, 0x80
-        .set    F_BIT, 0x40
-
-        .text
-        .code   32
-        .balign 4
-
-/*
- * Reset handler.
- */
-        .global ResetHandler
-ResetHandler:
-        /*
-         * Stack pointers initialization.
-         */
-        ldr     r0, =__ram_end__
-        /* Undefined */
-        msr     CPSR_c, #MODE_UND | I_BIT | F_BIT
-        mov     sp, r0
-        ldr     r1, =__und_stack_size__
-        sub     r0, r0, r1
-        /* Abort */
-        msr     CPSR_c, #MODE_ABT | I_BIT | F_BIT
-        mov     sp, r0
-        ldr     r1, =__abt_stack_size__
-        sub     r0, r0, r1
-        /* FIQ */
-        msr     CPSR_c, #MODE_FIQ | I_BIT | F_BIT
-        mov     sp, r0
-        ldr     r1, =__fiq_stack_size__
-        sub     r0, r0, r1
-        /* IRQ */
-        msr     CPSR_c, #MODE_IRQ | I_BIT | F_BIT
-        mov     sp, r0
-        ldr     r1, =__irq_stack_size__
-        sub     r0, r0, r1
-        /* Supervisor */
-        msr     CPSR_c, #MODE_SVC | I_BIT | F_BIT
-        mov     sp, r0
-        ldr     r1, =__svc_stack_size__
-        sub     r0, r0, r1
-        /* System */
-        msr     CPSR_c, #MODE_SYS | I_BIT | F_BIT
-        mov     sp, r0
-//        ldr     r1, =__sys_stack_size__
-//        sub     r0, r0, r1
-        /*
-         * Early initialization.
-         */
-#ifndef THUMB_NO_INTERWORKING
-        bl      __early_init
-#else
-        add     r0, pc, #1
-        bx      r0
-        .code   16
-        bl      __early_init
-        mov     r0, pc
-        bx      r0
-        .code   32
-#endif
-        /*
-         * Data initialization.
-         * NOTE: It assumes that the DATA size is a multiple of 4.
-         */
-        ldr     r1, =_textdata
-        ldr     r2, =_data
-        ldr     r3, =_edata
-dataloop:
-        cmp     r2, r3
-        ldrlo   r0, [r1], #4
-        strlo   r0, [r2], #4
-        blo     dataloop
-        /*
-         * BSS initialization.
-         * NOTE: It assumes that the BSS size is a multiple of 4.
-         */
-        mov     r0, #0
-        ldr     r1, =_bss_start
-        ldr     r2, =_bss_end
-bssloop:
-        cmp     r1, r2
-        strlo   r0, [r1], #4
-        blo     bssloop
-        /*
-         * Main program invocation.
-         */
-#ifdef THUMB_NO_INTERWORKING
-        add     r0, pc, #1
-        bx      r0
-        .code   16
-        bl      main
-        ldr     r1, =_main_exit_handler
-        bx      r1
-        .code   32
-#else
-        bl      main
-        b       _main_exit_handler
-#endif
-
-/*
- * Default main function exit handler.
- */
-        .weak   _main_exit_handler
-        .global _main_exit_handler
-_main_exit_handler:
-.loop:  b       .loop
-
-/*
- * Default early initialization code. It is declared weak in order to be
- * replaced by the real initialization code.
- * Early initialization is performed just after reset before BSS and DATA
- * segments initialization.
- */
-#ifdef THUMB_NO_INTERWORKING
-        .thumb_func
-        .code   16
-#endif
-        .weak   __early_init
-hwinit0:
-        bx      lr
-        .code   32
-#endif
-
-/** @} */
diff --git a/os/ports/GCC/ARM/port.dox b/os/ports/GCC/ARM/port.dox
deleted file mode 100644
index 5f866d2c2..000000000
--- a/os/ports/GCC/ARM/port.dox
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup ARM ARM7/9
- * @details ARM7/9 port for the GCC compiler.
- *
- * @section ARM_INTRO Introduction
- * The ARM7/9-GCC port supports the ARM7/9 core in the following three modes:
- * - <b>Pure ARM</b> mode, this is the preferred mode for code speed, this
- *   mode increases the memory footprint however. This mode is enabled when
- *   all the modules are compiled in ARM mode, see the Makefiles.
- * - <b>Pure THUMB</b> mode, this is the preferred mode for code size. In
- *   this mode the execution speed is slower than the ARM mode. This mode
- *   is enabled when all the modules are compiled in THUMB mode, see the
- *   Makefiles.
- * - <b>Interworking</b> mode, when in the system there are ARM modules mixed
- *   with THUMB modules then the interworking compiler option is enabled.
- *   This is usually the slowest mode and the code size is not as good as
- *   in pure THUMB mode.
- * .
- * @section ARM_STATES Mapping of the System States in the ARM7/9 port
- * The ChibiOS/RT logical system states are mapped as follow in the ARM7/9
- * port:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated, usually the CPU goes through several
- *   hardware states during the startup phase.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). In this state the CPU has both the interrupt sources
- *   (IRQ and FIQ) enabled and is running in ARM System Mode.
- * - <b>Suspended</b>. In this state the IRQ sources are disabled but the FIQ
- *   sources are served, the core is running in ARM System Mode.
- * - <b>Disabled</b>. Both the IRQ and FIQ sources are disabled, the core is
- *   running in ARM System Mode.
- * - <b>Sleep</b>. ARM7/9 cores does not have an explicit built-in low power
- *   mode but there are clock stop modes implemented in custom ways by the
- *   various silicon vendors. This state is implemented in each microcontroller
- *   support code in a different way, the core is running (or freezed...)
- *   in ARM System Mode.
- * - <b>S-Locked</b>. IRQ sources disabled, core running in ARM System Mode.
- * - <b>I-Locked</b>. IRQ sources disabled, core running in ARM IRQ Mode. Note
- *   that this state is not different from the SRI state in this port, the
- *   @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
- *   order to formally change state because this may change).
- * - <b>Serving Regular Interrupt</b>. IRQ sources disabled, core running in
- *   ARM IRQ Mode. See also the I-Locked state.
- * - <b>Serving Fast Interrupt</b>. IRQ and FIQ sources disabled, core running
- *   in ARM FIQ Mode.
- * - <b>Serving Non-Maskable Interrupt</b>. There are no asynchronous NMI
- *   sources in ARM7/9 architecture but synchronous SVC, ABT and UND exception
- *   handlers can be seen as belonging to this category.
- * - <b>Halted</b>. Implemented as an infinite loop after disabling both IRQ
- *   and FIQ sources. The ARM state is whatever the processor was running when
- *   @p chSysHalt() was invoked.
- * .
- * @section ARM_NOTES The ARM7/9 port notes
- * The ARM7/9 port is organized as follow:
- * - The @p main() function is invoked in system mode.
- * - Each thread has a private user/system stack, the system has a single
- *   interrupt stack where all the interrupts are processed.
- * - The threads are started in system mode.
- * - The threads code can run in system mode or user mode, however the
- *   code running in user mode cannot invoke the ChibiOS/RT APIs directly
- *   because privileged instructions are used inside.<br>
- *   The kernel APIs can be eventually invoked by using a SWI entry point
- *   that handles the switch in system mode and the return in user mode.
- * - Other modes are not preempt-able because the system code assumes the
- *   threads running in system mode. When running in supervisor or other
- *   modes make sure that the interrupts are globally disabled.
- * - Interrupts nesting is not supported in the ARM7/9 port because their
- *   implementation, even if possible, is not really efficient in this
- *   architecture.
- * - FIQ sources can preempt the kernel (by design) so it is not possible to
- *   invoke the kernel APIs from inside a FIQ handler. FIQ handlers are not
- *   affected by the kernel activity so there is not added jitter.
- * .
- * @section ARM_IH ARM7/9 Interrupt Handlers
- * In the current implementation the ARM7/9 Interrupt handlers do not save
- * function-saved registers so you need to make sure your code saves them
- * or does not use them (this happens because in the ARM7/9 port all the
- * OS interrupt handler functions are declared naked).<br>
- * Function-trashed registers (R0-R3, R12, LR, SR) are saved/restored by the
- * system macros @p CH_IRQ_PROLOGUE() and @p CH_IRQ_EPILOGUE().<br>
- * The easiest way to ensure this is to just invoke a normal function from
- * within the interrupt handler, the function code will save all the required
- * registers.<br>
- * Example:
- * @code
- * CH_IRQ_HANDLER(irq_handler) {
- *   CH_IRQ_PROLOGUE();
- *
- *   serve_interrupt();
- *
- *   VICVectAddr = 0; // This is LPC214x-specific.
- *   CH_IRQ_EPILOGUE();
- * }
- * @endcode
- * This is not a bug but an implementation choice, this solution allows to
- * have interrupt handlers compiled in thumb mode without have to use an
- * interworking mode (the mode switch is hidden in the macros), this
- * greatly improves code efficiency and size. You can look at the serial
- * driver for real examples of interrupt handlers.<br>
- * It is important that the serve_interrupt() interrupt function is not
- * inlined by the compiler into the ISR or the code could still modify
- * the unsaved registers, this can be accomplished using GCC by adding
- * the attribute "noinline" to the function:
- * @code
- * #if defined(__GNUC__)
- * __attribute__((noinline))
- * #endif
- * static void serve_interrupt(void) {
- * }
- * @endcode
- * Note that several commercial compilers support a GNU-like functions
- * attribute mechanism.<br>
- * Alternative ways are to use an appropriate pragma directive or disable
- * inlining optimizations in the modules containing the interrupt handlers.
- *
- * @ingroup gcc
- */
-
-/**
- * @defgroup ARM_CONF Configuration Options
- * @details ARM7/9 specific configuration options. The ARM7/9 port allows some
- * architecture-specific configurations settings that can be overridden by
- * redefining them in @p chconf.h. Usually there is no need to change the
- * default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
- *   by an interrupt handler between the @p extctx and @p intctx
- *   structures.<br>
- *   In practice this value is the stack space used by the chSchDoReschedule()
- *   stack frame.<br>
- *   This value can be affected by a variety of external things like compiler
- *   version, compiler options, kernel settings (speed/size) and so on.<br>
- *   The default for this value is @p 0x10 which should be a safe value, you
- *   can trim this down by defining the macro externally. This would save
- *   some valuable RAM space for each thread present in the system.<br>
- *   The default value is set into <b>./os/ports/GCC/ARM/chcore.h</b>.
- * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
- *   thread. Usually there is no need to change this value unless inserting
- *   code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
- * - @p ARM_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
- *   an implementation-specific clock stop mode from within the idle loop.
- *   This option is defaulted to FALSE because it can create problems with
- *   some debuggers. Setting this option to TRUE reduces the system power
- *   requirements.
- * .
- * @ingroup ARM
- */
-
-/**
- * @defgroup ARM_CORE Core Port Implementation
- * @details ARM7/9 specific port code, structures and macros.
- *
- * @ingroup ARM
- */
-
-/**
- * @defgroup ARM_STARTUP Startup Support
- * @details ARM7/9 startup code support. ChibiOS/RT provides its own generic
- * startup file for the ARM7/9 port. Of course it is not mandatory to use it
- * but care should be taken about the startup phase details.
- *
- * @section ARM_STARTUP_1 Startup Process
- * The startup process, as implemented, is the following:
- * -# The stacks are initialized by assigning them the sizes defined in the
- *    linker script (usually named @p ch.ld). Stack areas are allocated from
- *    the highest RAM location downward.
- * -# The ARM state is switched to System with both IRQ and FIQ sources
- *    disabled.
- * -# An early initialization routine @p hwinit0 is invoked, if the symbol is
- *    not defined then an empty default routine is executed (weak symbol).
- * -# DATA and BSS segments are initialized.
- * -# A late initialization routine @p hwinit1 is invoked, if the symbol not
- *    defined then an empty default routine is executed (weak symbol).<br>
- *    This late initialization function is also the proper place for a
- *    @a bootloader, if your application requires one.
- * -# The @p main() function is invoked with the parameters @p argc and @p argv
- *    set to zero.
- * -# Should the @p main() function return a branch is performed to the weak
- *    symbol _main_exit_handler. The default code is an endless empty loop.
- * .
- * @section ARM_STARTUP_2 Expected linker symbols
- * The startup code starts at the symbol @p ResetHandler and expects the
- * following symbols to be defined in the linker script:
- * - @p __ram_end__ RAM end location +1.
- * - @p __und_stack_size__ Undefined Instruction stack size.
- * - @p __abt_stack_size__ Memory Abort stack size.
- * - @p __fiq_stack_size__ FIQ service stack size.
- * - @p __irq_stack_size__ IRQ service stack size.
- * - @p __svc_stack_size__ SVC service stack size.
- * - @p __sys_stack_size__ System/User stack size. This is the stack area used
- *      by the @p main() function.
- * - @p _textdata address of the data segment source read only data.
- * - @p _data data segment start location.
- * - @p _edata data segment end location +1.
- * - @p _bss_start BSS start location.
- * - @p _bss_end BSS end location +1.
- * .
- * @ingroup ARM
- */
-
-/**
- * @defgroup ARM_SPECIFIC Specific Implementations
- * @details Platform-specific port code.
- *
- * @ingroup ARM
- */
diff --git a/os/ports/GCC/ARM/rules.mk b/os/ports/GCC/ARM/rules.mk
deleted file mode 100644
index 40fa8c9e2..000000000
--- a/os/ports/GCC/ARM/rules.mk
+++ /dev/null
@@ -1,220 +0,0 @@
-# ARM7/9 common makefile scripts and rules.
-
-# Output directory and files
-ifeq ($(BUILDDIR),)
-  BUILDDIR = build
-endif
-ifeq ($(BUILDDIR),.)
-  BUILDDIR = build
-endif
-OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
-           $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp
-
-# Automatic compiler options
-OPT = $(USE_OPT)
-COPT = $(USE_COPT)
-CPPOPT = $(USE_CPPOPT)
-ifeq ($(USE_LINK_GC),yes)
-  OPT += -ffunction-sections -fdata-sections
-endif
-
-# Source files groups and paths
-ifeq ($(USE_THUMB),yes)
-  TCSRC += $(CSRC)
-  TCPPSRC += $(CPPSRC)
-else
-  ACSRC += $(CSRC)
-  ACPPSRC += $(CPPSRC)
-endif
-ASRC	  = $(ACSRC)$(ACPPSRC)
-TSRC	  = $(TCSRC)$(TCPPSRC)
-SRCPATHS  = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
-
-# Various directories
-OBJDIR    = $(BUILDDIR)/obj
-LSTDIR    = $(BUILDDIR)/lst
-
-# Object files groups
-ACOBJS    = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
-ACPPOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
-TCOBJS    = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
-TCPPOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
-ASMOBJS   = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
-ASMXOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
-OBJS	  = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
-
-# Paths
-IINCDIR   = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
-LLIBDIR   = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
-
-# Macros
-DEFS      = $(DDEFS) $(UDEFS)
-ADEFS 	  = $(DADEFS) $(UADEFS)
-
-# Libs
-LIBS      = $(DLIBS) $(ULIBS)
-
-# Various settings
-MCFLAGS   = -mcpu=$(MCU)
-ODFLAGS	  = -x --syms
-ASFLAGS   = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
-ASXFLAGS  = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
-CFLAGS    = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
-CPPFLAGS  = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
-ifeq ($(USE_LINK_GC),yes)
-  LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR)
-else
-  LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR)
-endif
-
-# Thumb interwork enabled only if needed because it kills performance.
-ifneq ($(TSRC),)
-  CFLAGS   += -DTHUMB_PRESENT
-  CPPFLAGS += -DTHUMB_PRESENT
-  ASFLAGS  += -DTHUMB_PRESENT
-  ifneq ($(ASRC),)
-    # Mixed ARM and THUMB mode.
-    CFLAGS   += -mthumb-interwork
-    CPPFLAGS += -mthumb-interwork
-    ASFLAGS  += -mthumb-interwork
-    LDFLAGS  += -mthumb-interwork
-  else
-    # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
-    CFLAGS   += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
-    CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
-    ASFLAGS  += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
-    LDFLAGS  += -mno-thumb-interwork -mthumb
-  endif
-else
-  # Pure ARM mode
-  CFLAGS   += -mno-thumb-interwork
-  CPPFLAGS += -mno-thumb-interwork
-  ASFLAGS  += -mno-thumb-interwork
-  LDFLAGS  += -mno-thumb-interwork
-endif
-
-# Generate dependency information
-CFLAGS   += -MD -MP -MF .dep/$(@F).d
-CPPFLAGS += -MD -MP -MF .dep/$(@F).d
-
-# Paths where to search for sources
-VPATH     = $(SRCPATHS)
-
-#
-# Makefile rules
-#
-
-all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK
-
-MAKE_ALL_RULE_HOOK:
-
-$(OBJS): | $(BUILDDIR)
-
-$(BUILDDIR) $(OBJDIR) $(LSTDIR):
-ifneq ($(USE_VERBOSE_COMPILE),yes)
-	@echo Compiler Options
-	@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
-	@echo
-endif
-	mkdir -p $(OBJDIR)
-	mkdir -p $(LSTDIR)
-
-$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $<
-	@$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $<
-	@$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $<
-	@$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $<
-	@$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $<
-	@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
-endif
-
-$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo 
-	$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $<
-	@$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-%.elf: $(OBJS) $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
-else
-	@echo Linking $@
-	@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
-endif
-
-%.hex: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(HEX) $< $@
-else
-	@echo Creating $@
-	@$(HEX) $< $@
-endif
-
-%.bin: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(BIN) $< $@
-else
-	@echo Creating $@
-	@$(BIN) $< $@
-endif
-
-%.dmp: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(OD) $(ODFLAGS) $< > $@
-else
-	@echo Creating $@
-	@$(OD) $(ODFLAGS) $< > $@
-	@echo Done
-endif
-
-clean:
-	@echo Cleaning
-	-rm -fR .dep $(BUILDDIR)
-	@echo Done
-
-#
-# Include the dependency files, should be the last of the makefile
-#
--include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
-
-# *** EOF ***
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h
deleted file mode 100644
index d2a8fbf3a..000000000
--- a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC11xx/cmparams.h
- * @brief   ARM Cortex-M0 parameters for the LPC11xx.
- *
- * @defgroup ARMCMx_LPC11xx LPC11xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M0 specific parameters for the
- *          LPC11xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M0
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    2
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld
deleted file mode 100644
index 2201da1e9..000000000
--- a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC1114 memory setup.
- */
-__main_stack_size__     = 0x0200;
-__process_stack_size__  = 0x0200;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 32k
-    ram : org = 0x10000000, len = 8k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11C24.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11C24.ld
deleted file mode 100644
index a2360e6ad..000000000
--- a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11C24.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC11C24 memory setup.
- */
-__main_stack_size__     = 0x0200;
-__process_stack_size__  = 0x0200;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 32k
-    ram : org = 0x10000000, len = 8k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld
deleted file mode 100644
index d7030cb9a..000000000
--- a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC11U14 memory setup.
- */
-__main_stack_size__     = 0x0100;
-__process_stack_size__  = 0x0200;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 32k
-    ram : org = 0x10000000, len = 4k
-    usbram : org = 0x20004000, len = 2k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/port.mk b/os/ports/GCC/ARMCMx/LPC11xx/port.mk
deleted file mode 100644
index 8bfd25ad3..000000000
--- a/os/ports/GCC/ARMCMx/LPC11xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M0 LPC11xx port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx/ld
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/vectors.c b/os/ports/GCC/ARMCMx/LPC11xx/vectors.c
deleted file mode 100644
index 4ab02d632..000000000
--- a/os/ports/GCC/ARMCMx/LPC11xx/vectors.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC11xx/vectors.c
- * @brief   Interrupt vectors for the LPC11xx family.
- *
- * @defgroup ARMCMx_LPC11xx_VECTORS LPC11xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the LPC11xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[32];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-#endif
-
-/**
- * @brief   LPC11xx vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC122x/cmparams.h b/os/ports/GCC/ARMCMx/LPC122x/cmparams.h
deleted file mode 100644
index b70ce42a3..000000000
--- a/os/ports/GCC/ARMCMx/LPC122x/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC13xx/cmparams.h
- * @brief   ARM Cortex-M0 LPC122x Specific Parameters.
- *
- * @defgroup ARMCMx_LPC122x LPC122x Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M0 specific parameters for the
- *          LPC122x platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M0
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    2
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC122x/ld/LPC1227.ld b/os/ports/GCC/ARMCMx/LPC122x/ld/LPC1227.ld
deleted file mode 100644
index e1dfce0d4..000000000
--- a/os/ports/GCC/ARMCMx/LPC122x/ld/LPC1227.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC1227 memory setup.
- */
-__main_stack_size__     = 0x0200;
-__process_stack_size__  = 0x0200;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 128k
-    ram : org = 0x10000000, len = 8k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/LPC122x/port.mk b/os/ports/GCC/ARMCMx/LPC122x/port.mk
deleted file mode 100644
index 475861ee2..000000000
--- a/os/ports/GCC/ARMCMx/LPC122x/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M0 LPC122x port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC122x/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC122x
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC122x/ld
diff --git a/os/ports/GCC/ARMCMx/LPC122x/vectors.c b/os/ports/GCC/ARMCMx/LPC122x/vectors.c
deleted file mode 100644
index 39e4007a3..000000000
--- a/os/ports/GCC/ARMCMx/LPC122x/vectors.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC122x/vectors.c
- * @brief   Interrupt vectors for the LPC122x family.
- *
- * @defgroup ARMCMx_LPC122x_VECTORS LPC122x Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the LPC122x family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[32];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-#endif
-
-/**
- * @brief   LPC11xx vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h
deleted file mode 100644
index 6804ea993..000000000
--- a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC13xx/cmparams.h
- * @brief   ARM Cortex-M3 LPC13xx Specific Parameters.
- *
- * @defgroup ARMCMx_LPC13xx LPC13xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          LPC13xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    3
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld b/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld
deleted file mode 100644
index 2e0127af1..000000000
--- a/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC1343 memory setup.
- */
-__main_stack_size__     = 0x0200;
-__process_stack_size__  = 0x0200;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 32k
-    ram : org = 0x10000000, len = 8k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/port.mk b/os/ports/GCC/ARMCMx/LPC13xx/port.mk
deleted file mode 100644
index fa392c5d5..000000000
--- a/os/ports/GCC/ARMCMx/LPC13xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M0 LPC13xx port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx/ld
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/vectors.c b/os/ports/GCC/ARMCMx/LPC13xx/vectors.c
deleted file mode 100644
index 1537dc13f..000000000
--- a/os/ports/GCC/ARMCMx/LPC13xx/vectors.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC13xx/vectors.c
- * @brief   Interrupt vectors for the LPC13xx family.
- *
- * @defgroup ARMCMx_LPC13xx_VECTORS LPC13xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the LPC13xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[58];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-extern void VectorEC(void);
-extern void VectorF0(void);
-extern void VectorF4(void);
-extern void VectorF8(void);
-extern void VectorFC(void);
-extern void Vector100(void);
-extern void Vector104(void);
-extern void Vector108(void);
-extern void Vector10C(void);
-extern void Vector110(void);
-extern void Vector114(void);
-extern void Vector118(void);
-extern void Vector11C(void);
-extern void Vector120(void);
-extern void Vector124(void);
-#endif
-
-/**
- * @brief   LPC13xx vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC,
-    VectorC0,           VectorC4,           VectorC8,           VectorCC,
-    VectorD0,           VectorD4,           VectorD8,           VectorDC,
-    VectorE0,           VectorE4,           VectorE8,           VectorEC,
-    VectorF0,           VectorF4,           VectorF8,           VectorFC,
-    Vector100,          Vector104,          Vector108,          Vector10C,
-    Vector110,          Vector114,          Vector118,          Vector11C,
-    Vector120,          Vector124
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC17xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC17xx/cmparams.h
deleted file mode 100644
index 9483509dc..000000000
--- a/os/ports/GCC/ARMCMx/LPC17xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC17xx/cmparams.h
- * @brief   ARM Cortex-M3 LPC17xx Specific Parameters.
- *
- * @defgroup ARMCMx_LPC13xx LPC17xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          LPC17xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    3
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1766.ld b/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1766.ld
deleted file mode 100644
index 72105e3ee..000000000
--- a/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1766.ld
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC1766 memory setup.
- */
-__main_stack_size__     = 0x0200;
-__process_stack_size__  = 0x0200;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 256k
-    ram : org = 0x10000000, len = 32k
-    ramahb : org = 0x2007c000, len = 32k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    _etext = .;
-    _textdata = _etext;
-
-    .eth_ram (NOLOAD) :
-    {
-        . = ALIGN(4);
-        PROVIDE(_eth_ram_start = .);
-        *(.eth_ram)
-        . = ALIGN(4);
-        PROVIDE(_eth_ram_end = .);
-    } > ramahb
-    
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1769.ld b/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1769.ld
deleted file mode 100644
index 4cf748085..000000000
--- a/os/ports/GCC/ARMCMx/LPC17xx/ld/LPC1769.ld
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC1769 memory setup.
- */
-__main_stack_size__     = 0x0200;
-__process_stack_size__  = 0x0200;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 512k
-    ram : org = 0x10000000, len = 32k
-    ramahb : org = 0x2007c000, len = 32k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    _etext = .;
-    _textdata = _etext;
-    
-    .eth_ram (NOLOAD) :
-    {
-        . = ALIGN(4);
-        PROVIDE(_eth_ram_start = .);
-        *(.eth_ram)
-        . = ALIGN(4);
-        PROVIDE(_eth_ram_end = .);
-    } > ramahb
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/LPC17xx/port.mk b/os/ports/GCC/ARMCMx/LPC17xx/port.mk
deleted file mode 100644
index e98993ce2..000000000
--- a/os/ports/GCC/ARMCMx/LPC17xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M3 LPC17xx port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC17xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC17xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC17xx/ld
diff --git a/os/ports/GCC/ARMCMx/LPC17xx/vectors.c b/os/ports/GCC/ARMCMx/LPC17xx/vectors.c
deleted file mode 100644
index cc2d72133..000000000
--- a/os/ports/GCC/ARMCMx/LPC17xx/vectors.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC13xx/vectors.c
- * @brief   Interrupt vectors for the LPC17xx family.
- *
- * @defgroup ARMCMx_LPC17xx_VECTORS LPC17xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the LPC17xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[35];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-#endif
-
-/**
- * @brief   LPC17xx vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC,
-    VectorC0,           VectorC4,           VectorC8
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC43xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC43xx/cmparams.h
deleted file mode 100644
index d221a70f6..000000000
--- a/os/ports/GCC/ARMCMx/LPC43xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC43xx/cmparams.h
- * @brief   ARM Cortex-M4 LPC43xx Specific Parameters.
- *
- * @defgroup ARMCMx_LPC43xx LPC43xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- *          LPC43xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M4
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          TRUE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC43xx/ld/LPC4330_RAM_DEBUG.ld b/os/ports/GCC/ARMCMx/LPC43xx/ld/LPC4330_RAM_DEBUG.ld
deleted file mode 100644
index 888877191..000000000
--- a/os/ports/GCC/ARMCMx/LPC43xx/ld/LPC4330_RAM_DEBUG.ld
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC4330 ROMless memory setup.
- * Code runs from ram.
- */
-__main_stack_size__     = 0x0800;
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    ram     : org = 0x10000000, len = 128k
-    ram2    : org = 0x10080000, len = 72k
-    ramahb  : org = 0x20000000, len = 32k
-    ramahb2 : org = 0x20008000, len = 16k
-    ramahb3 : org = 0x2000C000, len = 16k
-}
-
-__ram_start__           = ORIGIN(ram2);
-__ram_size__            = LENGTH(ram2);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-    	__vectors_start = .;
-        KEEP(*(vectors))
-    } > ram
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > ram
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > ram
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > ram
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > ram
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > ram
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > ram
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > ram
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > ram
-
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram2
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram2 AT > ram
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram2    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/LPC43xx/port.mk b/os/ports/GCC/ARMCMx/LPC43xx/port.mk
deleted file mode 100644
index 7693bdf9a..000000000
--- a/os/ports/GCC/ARMCMx/LPC43xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M4 LPC43xx port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC43xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC43xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC43xx/ld
diff --git a/os/ports/GCC/ARMCMx/LPC43xx/vectors.c b/os/ports/GCC/ARMCMx/LPC43xx/vectors.c
deleted file mode 100644
index 87cb63c3e..000000000
--- a/os/ports/GCC/ARMCMx/LPC43xx/vectors.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC43xx/vectors.c
- * @brief   Interrupt vectors for the LPC43xx family.
- *
- * @defgroup ARMCMx_LPC43xx_VECTORS LPC43xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the LPC43xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[49];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-extern void VectorEC(void);
-extern void VectorF0(void);
-extern void VectorF4(void);
-extern void VectorF8(void);
-extern void VectorFC(void);
-extern void Vector100(void);
-extern void Vector104(void);
-extern void Vector108(void);
-extern void Vector10C(void);
-extern void Vector110(void);
-
-#endif
-
-/**
- * @brief   LPC17xx vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC,
-    VectorC0,           VectorC4,           VectorC8,           VectorCC,
-    VectorE0,           VectorE4,           VectorE8,           VectorEC,
-    VectorF0,           VectorF4,           VectorF8,           VectorFC,
-    Vector100,          Vector104,          Vector108,          Vector10C,
-    Vector110
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC8xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC8xx/cmparams.h
deleted file mode 100644
index da25ac6a2..000000000
--- a/os/ports/GCC/ARMCMx/LPC8xx/cmparams.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC8xx/cmparams.h
- * @brief   ARM Cortex-M0+ parameters for the LPC8xx.
- *
- * @defgroup ARMCMx_LPC8xx LPC8xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M0+ specific parameters for the
- *          LPC8xx platform.
- *          (Taken from the device header file where possible)
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-#include "LPC8xx.h"
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            __CORTEX_M
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          __MPU_PRESENT
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    __NVIC_PRIO_BITS
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld b/os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld
deleted file mode 100644
index df4106289..000000000
--- a/os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * LPC812 memory setup.
- */
-__main_stack_size__     = 0x0100;
-__process_stack_size__  = 0x0100;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 16k
-    ram : org = 0x10000000, len = 4k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/LPC8xx/port.mk b/os/ports/GCC/ARMCMx/LPC8xx/port.mk
deleted file mode 100644
index 9353ee68b..000000000
--- a/os/ports/GCC/ARMCMx/LPC8xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M0 LPC8xx port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC8xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC8xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC8xx/ld
diff --git a/os/ports/GCC/ARMCMx/LPC8xx/vectors.c b/os/ports/GCC/ARMCMx/LPC8xx/vectors.c
deleted file mode 100644
index f4685dae8..000000000
--- a/os/ports/GCC/ARMCMx/LPC8xx/vectors.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/LPC8xx/vectors.c
- * @brief   Interrupt vectors for the LPC8xx family.
- *
- * @defgroup ARMCMx_LPC8xx_VECTORS LPC8xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the LPC8xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[32];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void Vector10(void);
-extern void Vector14(void);
-extern void Vector18(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void Vector30(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-#endif
-
-/**
- * @brief   LPC8xx vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  Vector10,           Vector14,           Vector18,           Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  Vector30,           Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector14(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector18(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector30(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/SAM4L/cmparams.h b/os/ports/GCC/ARMCMx/SAM4L/cmparams.h
deleted file mode 100644
index 18553d53c..000000000
--- a/os/ports/GCC/ARMCMx/SAM4L/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/SAM4L/cmparams.h
- * @brief   ARM Cortex-M4 parameters for the ATSAM4L.
- *
- * @defgroup ARMCMx_SAM4L ATSAM4L Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- *          ATSAM4L platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M4
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/SAM4L/ld/ATSAM4LC4C.ld b/os/ports/GCC/ARMCMx/SAM4L/ld/ATSAM4LC4C.ld
deleted file mode 100644
index 93e37a0b8..000000000
--- a/os/ports/GCC/ARMCMx/SAM4L/ld/ATSAM4LC4C.ld
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ATSAM4LC4C memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 256k
-    ram : org = 0x20000000, len = 32k
-    ram2 : org = 0x21000000, len = 2k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/SAM4L/port.mk b/os/ports/GCC/ARMCMx/SAM4L/port.mk
deleted file mode 100644
index 296a45d45..000000000
--- a/os/ports/GCC/ARMCMx/SAM4L/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M4 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/SAM4L/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/SAM4L
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/SAM4L/ld
diff --git a/os/ports/GCC/ARMCMx/SAM4L/vectors.c b/os/ports/GCC/ARMCMx/SAM4L/vectors.c
deleted file mode 100644
index e7a3290ef..000000000
--- a/os/ports/GCC/ARMCMx/SAM4L/vectors.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/SAM4L/vectors.c
- * @brief   Interrupt vectors for the ATSAM4L family.
- *
- * @defgroup ARMCMx_SAM4L_VECTORS ATSAM4L Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the ATSAM4L family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[80];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void HFLASHC_Handler(void);
-extern void PDCA_0_Handler(void);
-extern void PDCA_1_Handler(void);
-extern void PDCA_2_Handler(void);
-extern void PDCA_3_Handler(void);
-extern void PDCA_4_Handler(void);
-extern void PDCA_5_Handler(void);
-extern void PDCA_6_Handler(void);
-extern void PDCA_7_Handler(void);
-extern void PDCA_8_Handler(void);
-extern void PDCA_9_Handler(void);
-extern void PDCA_10_Handler(void);
-extern void PDCA_11_Handler(void);
-extern void PDCA_12_Handler(void);
-extern void PDCA_13_Handler(void);
-extern void PDCA_14_Handler(void);
-extern void PDCA_15_Handler(void);
-extern void CRCCU_Handler(void);
-extern void USBC_Handler(void);
-extern void PEVC_TR_Handler(void);
-extern void PEVC_OV_Handler(void);
-extern void AESA_Handler(void);
-extern void PM_Handler(void);
-extern void SCIF_Handler(void);
-extern void FREQM_Handler(void);
-extern void GPIO_0_Handler(void);
-extern void GPIO_1_Handler(void);
-extern void GPIO_2_Handler(void);
-extern void GPIO_3_Handler(void);
-extern void GPIO_4_Handler(void);
-extern void GPIO_5_Handler(void);
-extern void GPIO_6_Handler(void);
-extern void GPIO_7_Handler(void);
-extern void GPIO_8_Handler(void);
-extern void GPIO_9_Handler(void);
-extern void GPIO_10_Handler(void);
-extern void GPIO_11_Handler(void);
-extern void BPM_Handler(void);
-extern void BSCIF_Handler(void);
-extern void AST_ALARM_Handler(void);
-extern void AST_PER_Handler(void);
-extern void AST_OVF_Handler(void);
-extern void AST_READY_Handler(void);
-extern void AST_CLKREADY_Handler(void);
-extern void WDT_Handler(void);
-extern void EIC_1_Handler(void);
-extern void EIC_2_Handler(void);
-extern void EIC_3_Handler(void);
-extern void EIC_4_Handler(void);
-extern void EIC_5_Handler(void);
-extern void EIC_6_Handler(void);
-extern void EIC_7_Handler(void);
-extern void EIC_8_Handler(void);
-extern void IISC_Handler(void);
-extern void SPI_Handler(void);
-extern void TC00_Handler(void);
-extern void TC01_Handler(void);
-extern void TC02_Handler(void);
-extern void TC010_Handler(void);
-extern void TC011_Handler(void);
-extern void TC012_Handler(void);
-extern void TWIM0_Handler(void);
-extern void TWIS0_Handler(void);
-extern void TWIM1_Handler(void);
-extern void TWIS1_Handler(void);
-extern void USART0_Handler(void);
-extern void USART1_Handler(void);
-extern void USART2_Handler(void);
-extern void USART3_Handler(void);
-extern void ADCIFE_Handler(void);
-extern void DACC_Handler(void);
-extern void ACIFC_Handler(void);
-extern void ABDACB_Handler(void);
-extern void TRNG_Handler(void);
-extern void PARC_Handler(void);
-extern void CATB_Handler(void);
-extern void Dummy_Handler(void);
-extern void TWIM2_Handler(void);
-extern void TWIM3_Handler(void);
-extern void LCDCA_Handler(void);
-#endif
-
-/**
- * @brief   STM32 vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    HFLASHC_Handler,    PDCA_0_Handler,     PDCA_1_Handler,     PDCA_2_Handler,
-    PDCA_3_Handler,	    PDCA_4_Handler,     PDCA_5_Handler,     PDCA_6_Handler,
-    PDCA_7_Handler,     PDCA_8_Handler,     PDCA_9_Handler,     PDCA_10_Handler,
-    PDCA_11_Handler,    PDCA_12_Handler,    PDCA_13_Handler,    PDCA_14_Handler,
-    PDCA_15_Handler,    CRCCU_Handler,      USBC_Handler,       PEVC_TR_Handler,
-    PEVC_OV_Handler,    AESA_Handler,       PM_Handler,         SCIF_Handler,
-    FREQM_Handler,      GPIO_0_Handler,     GPIO_1_Handler,     GPIO_2_Handler,
-    GPIO_3_Handler,     GPIO_4_Handler,     GPIO_5_Handler,     GPIO_6_Handler,
-    GPIO_7_Handler,     GPIO_8_Handler,     GPIO_9_Handler,     GPIO_10_Handler,
-    GPIO_11_Handler,    BPM_Handler,        BSCIF_Handler,      AST_ALARM_Handler,
-    AST_PER_Handler,    AST_OVF_Handler,    AST_READY_Handler,  AST_CLKREADY_Handler,
-    WDT_Handler,        EIC_1_Handler,      EIC_2_Handler,      EIC_3_Handler,
-    EIC_4_Handler,      EIC_5_Handler,      EIC_6_Handler,      EIC_7_Handler,
-    EIC_8_Handler,      IISC_Handler,       SPI_Handler,        TC00_Handler,
-    TC01_Handler,       TC02_Handler,       TC010_Handler,      TC011_Handler,
-    TC012_Handler,      TWIM0_Handler,      TWIS0_Handler,      TWIM1_Handler,
-    TWIS1_Handler,      USART0_Handler,     USART1_Handler,     USART2_Handler,
-    USART3_Handler,     ADCIFE_Handler,     DACC_Handler,       ACIFC_Handler,
-    ABDACB_Handler,     TRNG_Handler,       PARC_Handler,       CATB_Handler,
-    Dummy_Handler,      TWIM2_Handler,      TWIM3_Handler,      LCDCA_Handler
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HFLASHC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_0_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_1_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_2_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_3_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_4_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_5_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_6_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_7_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_8_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_9_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_10_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_11_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_12_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_13_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_14_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PDCA_15_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void CRCCU_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void USBC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PEVC_TR_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PEVC_OV_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void AESA_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PM_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void SCIF_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void FREQM_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_0_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_1_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_2_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_3_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_4_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_5_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_6_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_7_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_8_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_9_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_10_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void GPIO_11_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void BPM_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void BSCIF_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void AST_ALARM_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void AST_PER_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void AST_OVF_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void AST_READY_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void AST_CLKREADY_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void WDT_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void EIC_1_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void EIC_2_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void EIC_3_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void EIC_4_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void EIC_5_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void EIC_6_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void EIC_7_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void EIC_8_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void IISC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void SPI_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TC00_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TC01_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TC02_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TC010_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TC011_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TC012_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TWIM0_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TWIS0_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TWIM1_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TWIS1_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void USART0_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void USART1_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void USART2_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void USART3_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void ADCIFE_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void DACC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void ACIFC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void ABDACB_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TRNG_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void PARC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void CATB_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void Dummy_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TWIM2_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void TWIM3_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-void LCDCA_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h
deleted file mode 100644
index d94591461..000000000
--- a/os/ports/GCC/ARMCMx/STM32F0xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F0xx/cmparams.h
- * @brief   ARM Cortex-M0 parameters for the STM32F0xx.
- *
- * @defgroup ARMCMx_STM32F0xx STM32F0xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M0 specific parameters for the
- *          STM32F0xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M0
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    2
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F0xx/ld/STM32F051x8.ld b/os/ports/GCC/ARMCMx/STM32F0xx/ld/STM32F051x8.ld
deleted file mode 100644
index 562c9c06a..000000000
--- a/os/ports/GCC/ARMCMx/STM32F0xx/ld/STM32F051x8.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F051x8 memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 64k
-    ram : org = 0x20000000, len = 8k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F0xx/port.mk b/os/ports/GCC/ARMCMx/STM32F0xx/port.mk
deleted file mode 100644
index 5cb296a2b..000000000
--- a/os/ports/GCC/ARMCMx/STM32F0xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M0 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F0xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F0xx/ld
diff --git a/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c
deleted file mode 100644
index 5bd49cde8..000000000
--- a/os/ports/GCC/ARMCMx/STM32F0xx/vectors.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F0xx/vectors.c
- * @brief   Interrupt vectors for the STM32F0xx family.
- *
- * @defgroup ARMCMx_STM32F0xx_VECTORS STM32F0xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the STM32F0xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[32];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-#endif
-
-/**
- * @brief   STM32 vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h
deleted file mode 100644
index 6a7d9113b..000000000
--- a/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F1xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the STM32F1xx.
- *
- * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          STM32F1xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld
deleted file mode 100644
index 2016f66be..000000000
--- a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F100xB.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F100xB memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 128k
-    ram : org = 0x20000000, len = 8k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld
deleted file mode 100644
index 3c246ea3a..000000000
--- a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xB.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F103xB memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 128k
-    ram : org = 0x20000000, len = 20k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xD.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xD.ld
deleted file mode 100644
index c197c7a9f..000000000
--- a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xD.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F103xE memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 384k
-    ram : org = 0x20000000, len = 64k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld
deleted file mode 100644
index 2903199cb..000000000
--- a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xE.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F103xE memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 512k
-    ram : org = 0x20000000, len = 64k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld
deleted file mode 100644
index ca8fa93fa..000000000
--- a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F103xG.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F103xG memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 1m
-    ram : org = 0x20000000, len = 96k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld b/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld
deleted file mode 100644
index f251c8ebc..000000000
--- a/os/ports/GCC/ARMCMx/STM32F1xx/ld/STM32F107xC.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F107xC memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 256k
-    ram : org = 0x20000000, len = 64k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/port.mk b/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
deleted file mode 100644
index 1ba6c672e..000000000
--- a/os/ports/GCC/ARMCMx/STM32F1xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M3 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx/ld
diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c
deleted file mode 100644
index 3fe2ab33e..000000000
--- a/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F1xx/vectors.c
- * @brief   Interrupt vectors for the STM32F1xx family.
- *
- * @defgroup ARMCMx_STM32F1xx_VECTORS STM32F1xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the STM32F1xx family.
- *          One of the following macros must be defined on the
- *          compiler command line or in a file named <tt>board.h</tt>:
- *          - @p STM32F10X_LD
- *          - @p STM32F10X_LD_VL
- *          - @p STM32F10X_MD
- *          - @p STM32F10X_MD_VL
- *          - @p STM32F10X_HD
- *          - @p STM32F10X_XL
- *          - @p STM32F10X_CL
- *          .
- *          This is required in order to include a vectors table with
- *          the correct length for the specified STM32 model.
- * @{
- */
-
-#include "ch.h"
-
-#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) &&                  \
-    !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) &&                  \
-    !defined(STM32F10X_HD) && !defined(STM32F10X_XL) &&                     \
-    !defined(STM32F10X_CL)
-#include "board.h"
-#endif
-
-#if defined(STM32F10X_MD_VL) ||  defined(__DOXYGEN__)
-#define NUM_VECTORS     46
-#elif defined(STM32F10X_HD)  || defined(STM32F10X_XL)
-#define NUM_VECTORS     60
-#elif defined(STM32F10X_CL)
-#define NUM_VECTORS     68
-#else
-#define NUM_VECTORS     43
-#endif
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[NUM_VECTORS];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) ||                    \
-    defined(STM32F10X_XL)    || defined(STM32F10X_CL)
-extern void VectorEC(void);
-extern void VectorF0(void);
-extern void VectorF4(void);
-#endif
-#if defined(STM32F10X_HD)    || defined(STM32F10X_XL) || defined(STM32F10X_CL)
-extern void VectorF8(void);
-extern void VectorFC(void);
-extern void Vector100(void);
-extern void Vector104(void);
-extern void Vector108(void);
-extern void Vector10C(void);
-extern void Vector110(void);
-extern void Vector114(void);
-extern void Vector118(void);
-extern void Vector11C(void);
-extern void Vector120(void);
-extern void Vector124(void);
-extern void Vector128(void);
-extern void Vector12C(void);
-#endif
-#if defined(STM32F10X_CL)
-extern void Vector130(void);
-extern void Vector134(void);
-extern void Vector138(void);
-extern void Vector13C(void);
-extern void Vector140(void);
-extern void Vector144(void);
-extern void Vector148(void);
-extern void Vector14C(void);
-#endif
-#endif
-
-/**
- * @brief   STM32 vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC,
-    VectorC0,           VectorC4,           VectorC8,           VectorCC,
-    VectorD0,           VectorD4,           VectorD8,           VectorDC,
-    VectorE0,           VectorE4,           VectorE8,
-#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) ||                    \
-    defined(STM32F10X_XL)    || defined(STM32F10X_CL)
-    VectorEC,           VectorF0,           VectorF4,
-#endif
-#if defined(STM32F10X_HD)    || defined(STM32F10X_XL) || defined(STM32F10X_CL)
-    VectorF8,           VectorFC,           Vector100,          Vector104,
-    Vector108,          Vector10C,          Vector110,          Vector114,
-    Vector118,          Vector11C,          Vector120,          Vector124,
-    Vector128,          Vector12C,
-#endif
-#if defined(STM32F10X_CL)
-    Vector130,          Vector134,          Vector138,          Vector13C,
-    Vector140,          Vector144,          Vector148,          Vector14C
-#endif
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) ||                    \
-    defined(STM32F10X_XL)    || defined(STM32F10X_CL)
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
-#endif
-#if defined(STM32F10X_HD)    || defined(STM32F10X_XL) || defined(STM32F10X_CL)
-void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
-#endif
-#if defined(STM32F10X_CL)
-void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
-#endif
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F2xx/cmparams.h
deleted file mode 100644
index 3bb30ff07..000000000
--- a/os/ports/GCC/ARMCMx/STM32F2xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F2xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the STM32F2xx.
- *
- * @defgroup ARMCMx_STM32F2xx STM32F2xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- *          STM32F2xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F205xB.ld b/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F205xB.ld
deleted file mode 100644
index 8b56b6cfb..000000000
--- a/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F205xB.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F205xB memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 128k
-    ram : org = 0x20000000, len = 64k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F207xG.ld b/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F207xG.ld
deleted file mode 100644
index 8944217a6..000000000
--- a/os/ports/GCC/ARMCMx/STM32F2xx/ld/STM32F207xG.ld
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F207xG memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 1M
-    ram : org = 0x20000000, len = 112k
-    ethram : org = 0x2001C000, len = 16k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/port.mk b/os/ports/GCC/ARMCMx/STM32F2xx/port.mk
deleted file mode 100644
index 95104160c..000000000
--- a/os/ports/GCC/ARMCMx/STM32F2xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M3 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F2xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F2xx/ld
diff --git a/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c
deleted file mode 100644
index f516f1ab8..000000000
--- a/os/ports/GCC/ARMCMx/STM32F2xx/vectors.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F2xx/vectors.c
- * @brief   Interrupt vectors for the STM32F2xx family.
- *
- * @defgroup ARMCMx_STM32F2xx_VECTORS STM32F2xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the STM32F2xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[81];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-extern void VectorEC(void);
-extern void VectorF0(void);
-extern void VectorF4(void);
-extern void VectorF8(void);
-extern void VectorFC(void);
-extern void Vector100(void);
-extern void Vector104(void);
-extern void Vector108(void);
-extern void Vector10C(void);
-extern void Vector110(void);
-extern void Vector114(void);
-extern void Vector118(void);
-extern void Vector11C(void);
-extern void Vector120(void);
-extern void Vector124(void);
-extern void Vector128(void);
-extern void Vector12C(void);
-extern void Vector130(void);
-extern void Vector134(void);
-extern void Vector138(void);
-extern void Vector13C(void);
-extern void Vector140(void);
-extern void Vector144(void);
-extern void Vector148(void);
-extern void Vector14C(void);
-extern void Vector150(void);
-extern void Vector154(void);
-extern void Vector158(void);
-extern void Vector15C(void);
-extern void Vector160(void);
-extern void Vector164(void);
-extern void Vector168(void);
-extern void Vector16C(void);
-extern void Vector170(void);
-extern void Vector174(void);
-extern void Vector178(void);
-extern void Vector17C(void);
-extern void Vector180(void);
-#endif
-
-/**
- * @brief   STM32 vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC,
-    VectorC0,           VectorC4,           VectorC8,           VectorCC,
-    VectorD0,           VectorD4,           VectorD8,           VectorDC,
-    VectorE0,           VectorE4,           VectorE8,           VectorEC,
-    VectorF0,           VectorF4,           VectorF8,           VectorFC,
-    Vector100,          Vector104,          Vector108,          Vector10C,
-    Vector110,          Vector114,          Vector118,          Vector11C,
-    Vector120,          Vector124,          Vector128,          Vector12C,
-    Vector130,          Vector134,          Vector138,          Vector13C,
-    Vector140,          Vector144,          Vector148,          Vector14C,
-    Vector150,          Vector154,          Vector158,          Vector15C,
-    Vector160,          Vector164,          Vector168,          Vector16C,
-    Vector170,          Vector174,          Vector178,          Vector17C,
-    Vector180
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector150(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector154(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector158(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector15C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector160(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector164(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector168(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector16C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector170(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector174(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F3xx/cmparams.h
deleted file mode 100644
index dd829adb8..000000000
--- a/os/ports/GCC/ARMCMx/STM32F3xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F3xx/cmparams.h
- * @brief   ARM Cortex-M4 parameters for the STM32F3xx.
- *
- * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- *          STM32F3xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M4
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          TRUE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F303xC.ld b/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F303xC.ld
deleted file mode 100644
index 0e43d3561..000000000
--- a/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F303xC.ld
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F303xC memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 256k
-    ram : org = 0x20000000, len = 40k
-    ccmram : org = 0x10000000, len = 8k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld b/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld
deleted file mode 100644
index dc7bee377..000000000
--- a/os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F373xC memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 256k
-    ram : org = 0x20000000, len = 32k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/port.mk b/os/ports/GCC/ARMCMx/STM32F3xx/port.mk
deleted file mode 100644
index 09cc8dfd6..000000000
--- a/os/ports/GCC/ARMCMx/STM32F3xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M4 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F3xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F3xx/ld
diff --git a/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c
deleted file mode 100644
index 20de7cc18..000000000
--- a/os/ports/GCC/ARMCMx/STM32F3xx/vectors.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F3xx/vectors.c
- * @brief   Interrupt vectors for the STM32F3xx family.
- *
- * @defgroup ARMCMx_STM32F3xx_VECTORS STM32F3xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the STM32F3xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[82];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-extern void VectorEC(void);
-extern void VectorF0(void);
-extern void VectorF4(void);
-extern void VectorF8(void);
-extern void VectorFC(void);
-extern void Vector100(void);
-extern void Vector104(void);
-extern void Vector108(void);
-extern void Vector10C(void);
-extern void Vector110(void);
-extern void Vector114(void);
-extern void Vector118(void);
-extern void Vector11C(void);
-extern void Vector120(void);
-extern void Vector124(void);
-extern void Vector128(void);
-extern void Vector12C(void);
-extern void Vector130(void);
-extern void Vector134(void);
-extern void Vector138(void);
-extern void Vector13C(void);
-extern void Vector140(void);
-extern void Vector144(void);
-extern void Vector148(void);
-extern void Vector14C(void);
-extern void Vector150(void);
-extern void Vector154(void);
-extern void Vector158(void);
-extern void Vector15C(void);
-extern void Vector160(void);
-extern void Vector164(void);
-extern void Vector168(void);
-extern void Vector16C(void);
-extern void Vector170(void);
-extern void Vector174(void);
-extern void Vector178(void);
-extern void Vector17C(void);
-extern void Vector180(void);
-extern void Vector184(void);
-#endif
-
-/**
- * @brief   STM32 vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC,
-    VectorC0,           VectorC4,           VectorC8,           VectorCC,
-    VectorD0,           VectorD4,           VectorD8,           VectorDC,
-    VectorE0,           VectorE4,           VectorE8,           VectorEC,
-    VectorF0,           VectorF4,           VectorF8,           VectorFC,
-    Vector100,          Vector104,          Vector108,          Vector10C,
-    Vector110,          Vector114,          Vector118,          Vector11C,
-    Vector120,          Vector124,          Vector128,          Vector12C,
-    Vector130,          Vector134,          Vector138,          Vector13C,
-    Vector140,          Vector144,          Vector148,          Vector14C,
-    Vector150,          Vector154,          Vector158,          Vector15C,
-    Vector160,          Vector164,          Vector168,          Vector16C,
-    Vector170,          Vector174,          Vector178,          Vector17C,
-    Vector180,          Vector184
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector150(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector154(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector158(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector15C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector160(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector164(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector168(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector16C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector170(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector174(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector184(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h
deleted file mode 100644
index f4dab3e57..000000000
--- a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F4xx/cmparams.h
- * @brief   ARM Cortex-M4 parameters for the STM32F4xx.
- *
- * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- *          STM32F4xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M4
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          TRUE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld
deleted file mode 100644
index 008b0c5dd..000000000
--- a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F401xC memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 256k
-    ram : org = 0x20000000, len = 64k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld
deleted file mode 100644
index 8bc306e49..000000000
--- a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F405xG.ld
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F405xG memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 1M
-    ram : org = 0x20000000, len = 112k
-    ethram : org = 0x2001C000, len = 16k
-    ccmram : org = 0x10000000, len = 64k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld
deleted file mode 100644
index df96ad2b2..000000000
--- a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F407xG memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 1M
-    ram : org = 0x20000000, len = 112k
-    ethram : org = 0x2001C000, len = 16k
-    ccmram : org = 0x10000000, len = 64k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld
deleted file mode 100644
index 25a00c19f..000000000
--- a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG_CCM.ld
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F407xG memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 1M
-    ram : org = 0x20000000, len = 112k
-    ethram : org = 0x2001C000, len = 16k
-    ccmram : org = 0x10000000, len = 64k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ccmram
-
-    .ccm :
-    {
-        PROVIDE(_cmm_start = .);
-        . = ALIGN(4);
-        *(.ccm)
-        . = ALIGN(4);
-        *(.ccm.*)
-        . = ALIGN(4);
-        *(.bss.mainthread.*)
-        . = ALIGN(4);
-        *(.bss._idle_thread_wa)
-        . = ALIGN(4);
-        *(.bss.rlist)
-        . = ALIGN(4);
-        *(.bss.vtlist)
-        . = ALIGN(4);
-        *(.bss.endmem)
-        . = ALIGN(4);
-        *(.bss.nextmem)
-        . = ALIGN(4);
-        *(.bss.default_heap)
-        . = ALIGN(4);
-        PROVIDE(_cmm_end = .);
-    } > ccmram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F429xI.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F429xI.ld
deleted file mode 100644
index 77e796833..000000000
--- a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F429xI.ld
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32F429xI memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 2M
-    ram : org = 0x20000000, len = 192k
-    ccmram : org = 0x10000000, len = 64k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/port.mk b/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
deleted file mode 100644
index 743f825e9..000000000
--- a/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M4 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx/ld
diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c
deleted file mode 100644
index 9c7489473..000000000
--- a/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32F4xx/vectors.c
- * @brief   Interrupt vectors for the STM32F4xx family.
- *
- * @defgroup ARMCMx_STM32F4xx_VECTORS STM32F4xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the STM32F4xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[91];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-extern void VectorEC(void);
-extern void VectorF0(void);
-extern void VectorF4(void);
-extern void VectorF8(void);
-extern void VectorFC(void);
-extern void Vector100(void);
-extern void Vector104(void);
-extern void Vector108(void);
-extern void Vector10C(void);
-extern void Vector110(void);
-extern void Vector114(void);
-extern void Vector118(void);
-extern void Vector11C(void);
-extern void Vector120(void);
-extern void Vector124(void);
-extern void Vector128(void);
-extern void Vector12C(void);
-extern void Vector130(void);
-extern void Vector134(void);
-extern void Vector138(void);
-extern void Vector13C(void);
-extern void Vector140(void);
-extern void Vector144(void);
-extern void Vector148(void);
-extern void Vector14C(void);
-extern void Vector150(void);
-extern void Vector154(void);
-extern void Vector158(void);
-extern void Vector15C(void);
-extern void Vector160(void);
-extern void Vector164(void);
-extern void Vector168(void);
-extern void Vector16C(void);
-extern void Vector170(void);
-extern void Vector174(void);
-extern void Vector178(void);
-extern void Vector17C(void);
-extern void Vector180(void);
-extern void Vector184(void);
-extern void Vector188(void);
-extern void Vector18C(void);
-extern void Vector190(void);
-extern void Vector194(void);
-extern void Vector198(void);
-extern void Vector19C(void);
-extern void Vector1A0(void);
-extern void Vector1A4(void);
-extern void Vector1A8(void);
-#endif
-
-/**
- * @brief   STM32 vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC,
-    VectorC0,           VectorC4,           VectorC8,           VectorCC,
-    VectorD0,           VectorD4,           VectorD8,           VectorDC,
-    VectorE0,           VectorE4,           VectorE8,           VectorEC,
-    VectorF0,           VectorF4,           VectorF8,           VectorFC,
-    Vector100,          Vector104,          Vector108,          Vector10C,
-    Vector110,          Vector114,          Vector118,          Vector11C,
-    Vector120,          Vector124,          Vector128,          Vector12C,
-    Vector130,          Vector134,          Vector138,          Vector13C,
-    Vector140,          Vector144,          Vector148,          Vector14C,
-    Vector150,          Vector154,          Vector158,          Vector15C,
-    Vector160,          Vector164,          Vector168,          Vector16C,
-    Vector170,          Vector174,          Vector178,          Vector17C,
-    Vector180,          Vector184,          Vector188,          Vector18C,
-    Vector190,          Vector194,          Vector198,          Vector19C,
-    Vector1A0,          Vector1A4,          Vector1A8
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector150(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector154(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector158(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector15C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector160(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector164(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector168(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector16C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector170(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector174(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector184(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector188(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector18C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector190(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector194(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector198(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector19C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1A0(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1A4(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1A8(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h
deleted file mode 100644
index 67bbb5344..000000000
--- a/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32L1xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the STM32L1xx.
- *
- * @defgroup ARMCMx_STM32L1xx STM32L1xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          STM32L1xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/ld/STM32L152xB.ld b/os/ports/GCC/ARMCMx/STM32L1xx/ld/STM32L152xB.ld
deleted file mode 100644
index eb082a8a1..000000000
--- a/os/ports/GCC/ARMCMx/STM32L1xx/ld/STM32L152xB.ld
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * ST32L1152xB memory setup.
- */
-__main_stack_size__     = 0x0400;
-__process_stack_size__  = 0x0400;
-
-MEMORY
-{
-    flash : org = 0x08000000, len = 128k
-    ram : org = 0x20000000, len = 16k
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-
-ENTRY(ResetHandler)
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    startup : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text.startup.*)
-        *(.text)
-        *(.text.*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    .ARM.exidx : {
-        PROVIDE(__exidx_start = .);
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        PROVIDE(__exidx_end = .);
-     } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-    
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __main_stack_base__ = .;
-        . += __main_stack_size__;
-        . = ALIGN(8);
-        __main_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data)
-        . = ALIGN(4);
-        *(.data.*)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.bss)
-        . = ALIGN(4);
-        *(.bss.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-        PROVIDE(_bss_end = .);
-    } > ram    
-}
-
-PROVIDE(end = .);
-_end            = .;
-
-__heap_base__   = _end;
-__heap_end__    = __ram_end__;
diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/port.mk b/os/ports/GCC/ARMCMx/STM32L1xx/port.mk
deleted file mode 100644
index 93b177563..000000000
--- a/os/ports/GCC/ARMCMx/STM32L1xx/port.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M3 STM32L1xx port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
-          $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
-          ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
-
-PORTASM =
-
-PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
-          ${CHIBIOS}/os/ports/common/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx \
-          ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32L1xx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32L1xx/ld
diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c b/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c
deleted file mode 100644
index eaf7e0e9d..000000000
--- a/os/ports/GCC/ARMCMx/STM32L1xx/vectors.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/STM32L1xx/vectors.c
- * @brief   Interrupt vectors for the STM32 family.
- *
- * @defgroup ARMCMx_STM32L1xx_VECTORS STM32L1xx Interrupt Vectors
- * @ingroup ARMCMx_SPECIFIC
- * @details Interrupt vectors for the STM32L1xx family.
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Type of an IRQ vector.
- */
-typedef void  (*irq_vector_t)(void);
-
-/**
- * @brief   Type of a structure representing the whole vectors table.
- */
-typedef struct {
-  uint32_t      *init_stack;
-  irq_vector_t  reset_vector;
-  irq_vector_t  nmi_vector;
-  irq_vector_t  hardfault_vector;
-  irq_vector_t  memmanage_vector;
-  irq_vector_t  busfault_vector;
-  irq_vector_t  usagefault_vector;
-  irq_vector_t  vector1c;
-  irq_vector_t  vector20;
-  irq_vector_t  vector24;
-  irq_vector_t  vector28;
-  irq_vector_t  svcall_vector;
-  irq_vector_t  debugmonitor_vector;
-  irq_vector_t  vector34;
-  irq_vector_t  pendsv_vector;
-  irq_vector_t  systick_vector;
-  irq_vector_t  vectors[45];
-} vectors_t;
-
-#if !defined(__DOXYGEN__)
-extern uint32_t __main_stack_end__;
-extern void ResetHandler(void);
-extern void NMIVector(void);
-extern void HardFaultVector(void);
-extern void MemManageVector(void);
-extern void BusFaultVector(void);
-extern void UsageFaultVector(void);
-extern void Vector1C(void);
-extern void Vector20(void);
-extern void Vector24(void);
-extern void Vector28(void);
-extern void SVCallVector(void);
-extern void DebugMonitorVector(void);
-extern void Vector34(void);
-extern void PendSVVector(void);
-extern void SysTickVector(void);
-extern void Vector40(void);
-extern void Vector44(void);
-extern void Vector48(void);
-extern void Vector4C(void);
-extern void Vector50(void);
-extern void Vector54(void);
-extern void Vector58(void);
-extern void Vector5C(void);
-extern void Vector60(void);
-extern void Vector64(void);
-extern void Vector68(void);
-extern void Vector6C(void);
-extern void Vector70(void);
-extern void Vector74(void);
-extern void Vector78(void);
-extern void Vector7C(void);
-extern void Vector80(void);
-extern void Vector84(void);
-extern void Vector88(void);
-extern void Vector8C(void);
-extern void Vector90(void);
-extern void Vector94(void);
-extern void Vector98(void);
-extern void Vector9C(void);
-extern void VectorA0(void);
-extern void VectorA4(void);
-extern void VectorA8(void);
-extern void VectorAC(void);
-extern void VectorB0(void);
-extern void VectorB4(void);
-extern void VectorB8(void);
-extern void VectorBC(void);
-extern void VectorC0(void);
-extern void VectorC4(void);
-extern void VectorC8(void);
-extern void VectorCC(void);
-extern void VectorD0(void);
-extern void VectorD4(void);
-extern void VectorD8(void);
-extern void VectorDC(void);
-extern void VectorE0(void);
-extern void VectorE4(void);
-extern void VectorE8(void);
-extern void VectorEC(void);
-extern void VectorF0(void);
-#endif /* !defined(__DOXYGEN__) */
-
-/**
- * @brief   STM32L1xx vectors table.
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((section("vectors")))
-#endif
-vectors_t _vectors = {
-  &__main_stack_end__,ResetHandler,       NMIVector,          HardFaultVector,
-  MemManageVector,    BusFaultVector,     UsageFaultVector,   Vector1C,
-  Vector20,           Vector24,           Vector28,           SVCallVector,
-  DebugMonitorVector, Vector34,           PendSVVector,       SysTickVector,
-  {
-    Vector40,           Vector44,           Vector48,           Vector4C,
-    Vector50,           Vector54,           Vector58,           Vector5C,
-    Vector60,           Vector64,           Vector68,           Vector6C,
-    Vector70,           Vector74,           Vector78,           Vector7C,
-    Vector80,           Vector84,           Vector88,           Vector8C,
-    Vector90,           Vector94,           Vector98,           Vector9C,
-    VectorA0,           VectorA4,           VectorA8,           VectorAC,
-    VectorB0,           VectorB4,           VectorB8,           VectorBC,
-    VectorC0,           VectorC4,           VectorC8,           VectorCC,
-    VectorD0,           VectorD4,           VectorD8,           VectorDC,
-    VectorE0,           VectorE4,           VectorE8,           VectorEC,
-    VectorF0
-  }
-};
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (TRUE)
-    ;
-}
-
-void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
-void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
-void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
-void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
-void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/chcore.c b/os/ports/GCC/ARMCMx/chcore.c
deleted file mode 100644
index cd78a287f..000000000
--- a/os/ports/GCC/ARMCMx/chcore.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/chcore.c
- * @brief   ARM Cortex-Mx port code.
- *
- * @addtogroup ARMCMx_CORE
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Halts the system.
- * @note    The function is declared as a weak symbol, it is possible
- *          to redefine it in your application code.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h
deleted file mode 100644
index 5ab33f607..000000000
--- a/os/ports/GCC/ARMCMx/chcore.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/chcore.h
- * @brief   ARM Cortex-Mx port macros and structures.
- *
- * @addtogroup ARMCMx_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-/*===========================================================================*/
-/* Port constants (common).                                                  */
-/*===========================================================================*/
-
-/* Added to make the header stand-alone when included from asm.*/
-#ifndef FALSE
-#define FALSE       0
-#endif
-#ifndef TRUE
-#define TRUE        (!FALSE)
-#endif
-
-#define CORTEX_M0                       0   /**< @brief Cortex-M0 variant.  */
-#define CORTEX_M1                       1   /**< @brief Cortex-M1 variant.  */
-#define CORTEX_M3                       3   /**< @brief Cortex-M3 variant.  */
-#define CORTEX_M4                       4   /**< @brief Cortex-M4 variant.  */
-
-/* Inclusion of the Cortex-Mx implementation specific parameters.*/
-#include "cmparams.h"
-
-/* Cortex model check, only M0 and M3 supported right now.*/
-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) ||           \
-    (CORTEX_MODEL == CORTEX_M4)
-#elif (CORTEX_MODEL == CORTEX_M1)
-#warning "untested Cortex-M model"
-#else
-#error "unknown or unsupported Cortex-M model"
-#endif
-
-/**
- * @brief   Total priority levels.
- */
-#define CORTEX_PRIORITY_LEVELS          (1 << CORTEX_PRIORITY_BITS)
-
-/**
- * @brief   Minimum priority level.
- * @details This minimum priority level is calculated from the number of
- *          priority bits supported by the specific Cortex-Mx implementation.
- */
-#define CORTEX_MINIMUM_PRIORITY         (CORTEX_PRIORITY_LEVELS - 1)
-
-/**
- * @brief   Maximum priority level.
- * @details The maximum allowed priority level is always zero.
- */
-#define CORTEX_MAXIMUM_PRIORITY         0
-
-/*===========================================================================*/
-/* Port macros (common).                                                     */
-/*===========================================================================*/
-
-/**
- * @brief   Priority level verification macro.
- */
-#define CORTEX_IS_VALID_PRIORITY(n)                                         \
-  (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
-
-/**
- * @brief   Priority level verification macro.
- */
-#define CORTEX_IS_VALID_KERNEL_PRIORITY(n)                                  \
-  (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
-
-/**
- * @brief   Priority level to priority mask conversion macro.
- */
-#define CORTEX_PRIORITY_MASK(n)                                             \
-  ((n) << (8 - CORTEX_PRIORITY_BITS))
-
-/*===========================================================================*/
-/* Port configurable parameters (common).                                    */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port derived parameters (common).                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port exported info (common).                                              */
-/*===========================================================================*/
-
-/**
- * @brief   Macro defining a generic ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "GCC " __VERSION__
-
-/*===========================================================================*/
-/* Port implementation part (common).                                        */
-/*===========================================================================*/
-
-/* Includes the sub-architecture-specific part.*/
-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
-#include "chcore_v6m.h"
-#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
-#include "chcore_v7m.h"
-#endif
-
-#if !defined(_FROM_ASM_)
-
-#include "nvic.h"
-
-/* The following declarations are there just for Doxygen documentation, the
-   real declarations are inside the sub-headers.*/
-#if defined(__DOXYGEN__)
-
-/**
- * @brief   Stack and memory alignment enforcement.
- * @note    In this architecture the stack alignment is enforced to 64 bits,
- *          32 bits alignment is supported by hardware but deprecated by ARM,
- *          the implementation choice is to not offer the option.
- */
-typedef uint64_t stkalign_t;
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- * @note    It is implemented to match the Cortex-Mx exception context.
- */
-struct extctx {};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching.
- */
-struct intctx {};
-
-#endif /* defined(__DOXYGEN__) */
-
-/**
- * @brief   Excludes the default @p chSchIsPreemptionRequired()implementation.
- */
-#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED
-
-#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
-/**
- * @brief   Inline-able version of this kernel function.
- */
-#define chSchIsPreemptionRequired()                                         \
-  (currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio :           \
-                      firstprio(&rlist.r_queue) >= currp->p_prio)
-#else /* CH_TIME_QUANTUM == 0 */
-#define chSchIsPreemptionRequired()                                         \
-  (firstprio(&rlist.r_queue) > currp->p_prio)
-#endif /* CH_TIME_QUANTUM == 0 */
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c
deleted file mode 100644
index 599164612..000000000
--- a/os/ports/GCC/ARMCMx/chcore_v6m.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/chcore_v6m.c
- * @brief   ARMv6-M architecture port code.
- *
- * @addtogroup ARMCMx_V6M_CORE
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* Port interrupt handlers.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   System Timer vector.
- * @details This interrupt is used as system tick.
- * @note    The timer must be initialized in the startup code.
- */
-CH_IRQ_HANDLER(SysTickVector) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-/**
- * @brief   NMI vector.
- * @details The NMI vector is used for exception mode re-entering after a
- *          context switch.
- */
-void NMIVector(void) {
-  register struct extctx *ctxp;
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");
-  ctxp++;
-  asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");
-  port_unlock_from_isr();
-}
-#endif /* !CORTEX_ALTERNATE_SWITCH */
-
-#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-/**
- * @brief   PendSV vector.
- * @details The PendSV vector is used for exception mode re-entering after a
- *          context switch.
- */
-void PendSVVector(void) {
-  register struct extctx *ctxp;
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");
-  ctxp++;
-  asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");
-}
-#endif /* CORTEX_ALTERNATE_SWITCH */
-
-/*===========================================================================*/
-/* Port exported functions.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   IRQ epilogue code.
- *
- * @param[in] lr        value of the @p LR register on ISR entry
- */
-void _port_irq_epilogue(regarm_t lr) {
-
-  if (lr != (regarm_t)0xFFFFFFF1) {
-    register struct extctx *ctxp;
-
-    port_lock_from_isr();
-    /* Adding an artificial exception return context, there is no need to
-       populate it fully.*/
-    asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");
-    ctxp--;
-    asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");
-    ctxp->xpsr = (regarm_t)0x01000000;
-
-    /* The exit sequence is different depending on if a preemption is
-       required or not.*/
-    if (chSchIsPreemptionRequired()) {
-      /* Preemption is required we need to enforce a context switch.*/
-      ctxp->pc = (void *)_port_switch_from_isr;
-    }
-    else {
-      /* Preemption not required, we just need to exit the exception
-         atomically.*/
-      ctxp->pc = (void *)_port_exit_from_isr;
-    }
-
-    /* Note, returning without unlocking is intentional, this is done in
-       order to keep the rest of the context switch atomic.*/
-  }
-}
-
-/**
- * @brief   Post-IRQ switch code.
- * @details The switch is performed in thread context then an NMI exception
- *          is enforced in order to return to the exact point before the
- *          preemption.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void _port_switch_from_isr(void) {
-
-  dbg_check_lock();
-  chSchDoReschedule();
-  dbg_check_unlock();
-  asm volatile ("_port_exit_from_isr:" : : : "memory");
-#if CORTEX_ALTERNATE_SWITCH
-  SCB_ICSR = ICSR_PENDSVSET;
-  port_unlock();
-#else
-  SCB_ICSR = ICSR_NMIPENDSET;
-#endif
-  /* The following loop should never be executed, the exception will kick in
-     immediately.*/
-  while (TRUE)
-    ;
-}
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void _port_switch(Thread *ntp, Thread *otp) {
-  register struct intctx *r13 asm ("r13");
-
-  asm volatile ("push    {r4, r5, r6, r7, lr}                   \n\t"
-                "mov     r4, r8                                 \n\t"
-                "mov     r5, r9                                 \n\t"
-                "mov     r6, r10                                \n\t"
-                "mov     r7, r11                                \n\t"
-                "push    {r4, r5, r6, r7}" : : : "memory");
-
-  otp->p_ctx.r13 = r13;
-  r13 = ntp->p_ctx.r13;
-
-  asm volatile ("pop     {r4, r5, r6, r7}                       \n\t"
-                "mov     r8, r4                                 \n\t"
-                "mov     r9, r5                                 \n\t"
-                "mov     r10, r6                                \n\t"
-                "mov     r11, r7                                \n\t"
-                "pop     {r4, r5, r6, r7, pc}" : : "r" (r13) : "memory");
-}
-
-/**
- * @brief   Start a thread by invoking its work function.
- * @details If the work function returns @p chThdExit() is automatically
- *          invoked.
- */
-void _port_thread_start(void) {
-
-  chSysUnlock();
-  asm volatile ("mov     r0, r5                                 \n\t"
-                "blx     r4                                     \n\t"
-                "bl      chThdExit");
-}
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h
deleted file mode 100644
index 30791f792..000000000
--- a/os/ports/GCC/ARMCMx/chcore_v6m.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/chcore_v6m.h
- * @brief   ARMv6-M architecture port macros and structures.
- *
- * @addtogroup ARMCMx_V6M_CORE
- * @{
- */
-
-#ifndef _CHCORE_V6M_H_
-#define _CHCORE_V6M_H_
-
-/*===========================================================================*/
-/* Port constants.                                                           */
-/*===========================================================================*/
-
-/**
- * @brief   PendSV priority level.
- * @note    This priority is enforced to be equal to @p 0,
- *          this handler always has the highest priority that cannot preempt
- *          the kernel.
- */
-#define CORTEX_PRIORITY_PENDSV          0
-
-/*===========================================================================*/
-/* Port macros.                                                              */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- * @note    In this port it is set to 16 because the idle thread does have
- *          a stack frame when compiling without optimizations. You may
- *          reduce this value to zero when compiling with optimizations.
- */
-#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
-#define PORT_IDLE_THREAD_STACK_SIZE     16
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- * @note    In this port this value is conservatively set to 64 because the
- *          function @p chSchDoReschedule() can have a stack frame, especially
- *          with compiler optimizations disabled. The value can be reduced
- *          when compiler optimizations are enabled.
- */
-#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK         64
-#endif
-
-/**
- * @brief   Enables the use of the WFI instruction in the idle thread loop.
- */
-#if !defined(CORTEX_ENABLE_WFI_IDLE)
-#define CORTEX_ENABLE_WFI_IDLE          FALSE
-#endif
-
-/**
- * @brief   SYSTICK handler priority.
- * @note    The default SYSTICK handler priority is calculated as the priority
- *          level in the middle of the numeric priorities range.
- */
-#if !defined(CORTEX_PRIORITY_SYSTICK)
-#define CORTEX_PRIORITY_SYSTICK         (CORTEX_PRIORITY_LEVELS >> 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
-
-/**
- * @brief   Alternate preemption method.
- * @details Activating this option will make the Kernel use the PendSV
- *          handler for preemption instead of the NMI handler.
- */
-#ifndef CORTEX_ALTERNATE_SWITCH
-#define CORTEX_ALTERNATE_SWITCH         FALSE
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   Maximum usable priority for normal ISRs.
- */
-#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-#define CORTEX_MAX_KERNEL_PRIORITY      1
-#else
-#define CORTEX_MAX_KERNEL_PRIORITY      0
-#endif
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Macro defining the specific ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM_v6M
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "ARMv6-M"
-
-/**
- * @brief   Name of the architecture variant.
- */
-#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
-#define CH_CORE_VARIANT_NAME            "Cortex-M0"
-#elif (CORTEX_MODEL == CORTEX_M1)
-#define CH_CORE_VARIANT_NAME            "Cortex-M1"
-#endif
-
-/**
- * @brief   Port-specific information string.
- */
-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-#define CH_PORT_INFO                    "Preemption through NMI"
-#else
-#define CH_PORT_INFO                    "Preemption through PendSV"
-#endif
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-/**
- * @brief   Generic ARM register.
- */
-typedef void *regarm_t;
-
- /* The documentation of the following declarations is in chconf.h in order
-    to not have duplicated structure names into the documentation.*/
-#if !defined(__DOXYGEN__)
-
-typedef uint64_t stkalign_t __attribute__ ((aligned (8)));
-
-struct extctx {
-  regarm_t      r0;
-  regarm_t      r1;
-  regarm_t      r2;
-  regarm_t      r3;
-  regarm_t      r12;
-  regarm_t      lr_thd;
-  regarm_t      pc;
-  regarm_t      xpsr;
-};
-
-struct intctx {
-  regarm_t      r8;
-  regarm_t      r9;
-  regarm_t      r10;
-  regarm_t      r11;
-  regarm_t      r4;
-  regarm_t      r5;
-  regarm_t      r6;
-  regarm_t      r7;
-  regarm_t      lr;
-};
-
-#endif /* !defined(__DOXYGEN__) */
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- *          structure representing the stack pointer at context switch time.
- */
-struct context {
-  struct intctx *r13;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
-                                     wsize -                                \
-                                     sizeof(struct intctx));                \
-  tp->p_ctx.r13->r4 = (void *)(pf);                                         \
-  tp->p_ctx.r13->r5 = (void *)(arg);                                        \
-  tp->p_ctx.r13->lr = (void *)(_port_thread_start);                         \
-}
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()                                                 \
-  regarm_t _saved_lr;                                                       \
-  asm volatile ("mov     %0, lr" : "=r" (_saved_lr) : : "memory")
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Fast IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_FAST_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Port-related initialization code.
- */
-#define port_init() {                                                       \
-  SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \
-  nvicSetSystemHandlerPriority(HANDLER_PENDSV,                              \
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,                             \
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \
-}
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform
- *          more actions.
- */
-#define port_lock() asm volatile ("cpsid   i" : : : "memory")
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform
- *          more actions.
- */
-#define port_unlock() asm volatile ("cpsie   i" : : : "memory")
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependent,
- *          in its simplest form it is void.
- * @note    Same as @p port_lock() in this port.
- */
-#define port_lock_from_isr() port_lock()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- * @note    Same as @p port_lock() in this port.
- */
-#define port_unlock_from_isr() port_unlock()
-
-/**
- * @brief   Disables all the interrupt sources.
- */
-#define port_disable() asm volatile ("cpsid   i" : : : "memory")
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- */
-#define port_suspend() asm volatile ("cpsid   i" : : : "memory")
-
-/**
- * @brief   Enables all the interrupt sources.
- */
-#define port_enable() asm volatile ("cpsie   i" : : : "memory")
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- * @note    Implemented as an inlined @p WFI instruction.
- */
-#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() asm volatile ("wfi" : : : "memory")
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-#else
-#define port_switch(ntp, otp) {                                             \
-  register struct intctx *r13 asm ("r13");                                  \
-  if ((stkalign_t *)(r13 - 1) < otp->p_stklimit)                            \
-    chDbgPanic("stack overflow");                                           \
-  _port_switch(ntp, otp);                                                   \
-}
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_halt(void);
-  void _port_irq_epilogue(regarm_t lr);
-  void _port_switch_from_isr(void);
-  void _port_exit_from_isr(void);
-  void _port_switch(Thread *ntp, Thread *otp);
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_V6M_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c
deleted file mode 100644
index ad92a9f07..000000000
--- a/os/ports/GCC/ARMCMx/chcore_v7m.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/chcore_v7m.c
- * @brief   ARMv7-M architecture port code.
- *
- * @addtogroup ARMCMx_V7M_CORE
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* Port interrupt handlers.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   System Timer vector.
- * @details This interrupt is used as system tick.
- * @note    The timer must be initialized in the startup code.
- */
-CH_IRQ_HANDLER(SysTickVector) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief   SVC vector.
- * @details The SVC vector is used for exception mode re-entering after a
- *          context switch.
- * @note    The PendSV vector is only used in advanced kernel mode.
- */
-void SVCallVector(void) {
-  struct extctx *ctxp;
-
-  /* Current PSP value.*/
-  asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp++;
-
-#if CORTEX_USE_FPU
-  /* Restoring the special register SCB_FPCCR.*/
-  SCB_FPCCR = (uint32_t)ctxp->fpccr;
-  SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx);
-#endif
-  asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");
-  port_unlock_from_isr();
-}
-#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
-
-#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief   PendSV vector.
- * @details The PendSV vector is used for exception mode re-entering after a
- *          context switch.
- * @note    The PendSV vector is only used in compact kernel mode.
- */
-void PendSVVector(void) {
-  struct extctx *ctxp;
-
-  /* Current PSP value.*/
-  asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp++;
-
-#if CORTEX_USE_FPU
-  /* Restoring the special register SCB_FPCCR.*/
-  SCB_FPCCR = (uint32_t)ctxp->fpccr;
-  SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx);
-#endif
-  asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");
-}
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/*===========================================================================*/
-/* Port exported functions.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   Port-related initialization code.
- */
-void _port_init(void) {
-
-  /* Initialization of the vector table and priority related settings.*/
-  SCB_VTOR = CORTEX_VTOR_INIT;
-  SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT);
-
-  /* Initialization of the system vectors used by the port.*/
-  nvicSetSystemHandlerPriority(HANDLER_SVCALL,
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
-  nvicSetSystemHandlerPriority(HANDLER_PENDSV,
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
-}
-
-#if !CH_OPTIMIZE_SPEED
-void _port_lock(void) {
-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;
-  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");
-}
-
-void _port_unlock(void) {
-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;
-  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");
-}
-#endif
-
-/**
- * @brief   Exception exit redirection to _port_switch_from_isr().
- */
-void _port_irq_epilogue(void) {
-
-  port_lock_from_isr();
-  if ((SCB_ICSR & ICSR_RETTOBASE) != 0) {
-    struct extctx *ctxp;
-
-    /* Current PSP value.*/
-    asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");
-
-    /* Adding an artificial exception return context, there is no need to
-       populate it fully.*/
-    ctxp--;
-    asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");
-    ctxp->xpsr = (regarm_t)0x01000000;
-
-    /* The exit sequence is different depending on if a preemption is
-       required or not.*/
-    if (chSchIsPreemptionRequired()) {
-      /* Preemption is required we need to enforce a context switch.*/
-      ctxp->pc = (void *)_port_switch_from_isr;
-#if CORTEX_USE_FPU
-      /* Triggering a lazy FPU state save.*/
-      asm volatile ("vmrs    APSR_nzcv, FPSCR" : : : "memory");
-#endif
-    }
-    else {
-      /* Preemption not required, we just need to exit the exception
-         atomically.*/
-      ctxp->pc = (void *)_port_exit_from_isr;
-    }
-
-#if CORTEX_USE_FPU
-    {
-      uint32_t fpccr;
-
-      /* Saving the special register SCB_FPCCR into the reserved offset of
-         the Cortex-M4 exception frame.*/
-      (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR);
-
-      /* Now the FPCCR is modified in order to not restore the FPU status
-         from the artificial return context.*/
-      SCB_FPCCR = fpccr | FPCCR_LSPACT;
-    }
-#endif
-
-    /* Note, returning without unlocking is intentional, this is done in
-       order to keep the rest of the context switch atomic.*/
-    return;
-  }
-  port_unlock_from_isr();
-}
-
-/**
- * @brief   Post-IRQ switch code.
- * @details Exception handlers return here for context switching.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void _port_switch_from_isr(void) {
-
-  dbg_check_lock();
-  chSchDoReschedule();
-  dbg_check_unlock();
-  asm volatile ("_port_exit_from_isr:" : : : "memory");
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-  asm volatile ("svc     #0");
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-  SCB_ICSR = ICSR_PENDSVSET;
-  port_unlock();
-  while (TRUE)
-    ;
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-}
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void _port_switch(Thread *ntp, Thread *otp) {
-
-  asm volatile ("push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}"
-                : : : "memory");
-#if CORTEX_USE_FPU
-  asm volatile ("vpush   {s16-s31}" : : : "memory");
-#endif
-
-  asm volatile ("str     sp, [%1, #12]                          \n\t"
-                "ldr     sp, [%0, #12]" : : "r" (ntp), "r" (otp));
-
-#if CORTEX_USE_FPU
-  asm volatile ("vpop    {s16-s31}" : : : "memory");
-#endif
-  asm volatile ("pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}"
-                : : : "memory");
-}
-
-/**
- * @brief   Start a thread by invoking its work function.
- * @details If the work function returns @p chThdExit() is automatically
- *          invoked.
- */
-void _port_thread_start(void) {
-
-  chSysUnlock();
-  asm volatile ("mov     r0, r5                                 \n\t"
-                "blx     r4                                     \n\t"
-                "bl      chThdExit");
-}
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h
deleted file mode 100644
index ee1e37731..000000000
--- a/os/ports/GCC/ARMCMx/chcore_v7m.h
+++ /dev/null
@@ -1,525 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/chcore_v7m.h
- * @brief   ARMv7-M architecture port macros and structures.
- *
- * @addtogroup ARMCMx_V7M_CORE
- * @{
- */
-
-#ifndef _CHCORE_V7M_H_
-#define _CHCORE_V7M_H_
-
-/*===========================================================================*/
-/* Port constants.                                                           */
-/*===========================================================================*/
-
-/**
- * @brief   Disabled value for BASEPRI register.
- */
-#define CORTEX_BASEPRI_DISABLED         0
-
-/*===========================================================================*/
-/* Port macros.                                                              */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- * @note    In this port it is set to 16 because the idle thread does have
- *          a stack frame when compiling without optimizations. You may
- *          reduce this value to zero when compiling with optimizations.
- */
-#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
-#define PORT_IDLE_THREAD_STACK_SIZE     16
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- * @note    In this port this value is conservatively set to 64 because the
- *          function @p chSchDoReschedule() can have a stack frame, especially
- *          with compiler optimizations disabled. The value can be reduced
- *          when compiler optimizations are enabled.
- */
-#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK         64
-#endif
-
-/**
- * @brief   Enables the use of the WFI instruction in the idle thread loop.
- */
-#if !defined(CORTEX_ENABLE_WFI_IDLE)
-#define CORTEX_ENABLE_WFI_IDLE          FALSE
-#endif
-
-/**
- * @brief   SYSTICK handler priority.
- * @note    The default SYSTICK handler priority is calculated as the priority
- *          level in the middle of the numeric priorities range.
- */
-#if !defined(CORTEX_PRIORITY_SYSTICK)
-#define CORTEX_PRIORITY_SYSTICK         (CORTEX_PRIORITY_LEVELS >> 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
-
-/**
- * @brief   FPU support in context switch.
- * @details Activating this option activates the FPU support in the kernel.
- */
-#if !defined(CORTEX_USE_FPU)
-#define CORTEX_USE_FPU                  CORTEX_HAS_FPU
-#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
-/* This setting requires an FPU presence check in case it is externally
-   redefined.*/
-#error "the selected core does not have an FPU"
-#endif
-
-/**
- * @brief   Simplified priority handling flag.
- * @details Activating this option makes the Kernel work in compact mode.
- */
-#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
-#define CORTEX_SIMPLIFIED_PRIORITY      FALSE
-#endif
-
-/**
- * @brief   SVCALL handler priority.
- * @note    The default SVCALL handler priority is defaulted to
- *          @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
- *          @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
- *          priority level.
- */
-#if !defined(CORTEX_PRIORITY_SVCALL)
-#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
-#endif
-
-/**
- * @brief   NVIC VTOR initialization expression.
- */
-#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
-#define CORTEX_VTOR_INIT                0x00000000
-#endif
-
-/**
- * @brief   NVIC PRIGROUP initialization expression.
- * @details The default assigns all available priority bits as preemption
- *          priority with no sub-priority.
- */
-#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
-#define CORTEX_PRIGROUP_INIT            (7 - CORTEX_PRIORITY_BITS)
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters.                                                  */
-/*===========================================================================*/
-
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief   Maximum usable priority for normal ISRs.
- */
-#define CORTEX_MAX_KERNEL_PRIORITY      (CORTEX_PRIORITY_SVCALL + 1)
-
-/**
- * @brief   BASEPRI level within kernel lock.
- * @note    In compact kernel mode this constant value is enforced to zero.
- */
-#define CORTEX_BASEPRI_KERNEL                                               \
-  CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY)
-#else
-
-#define CORTEX_MAX_KERNEL_PRIORITY      1
-#define CORTEX_BASEPRI_KERNEL           0
-#endif
-
-/**
- * @brief   PendSV priority level.
- * @note    This priority is enforced to be equal to
- *          @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
- *          highest priority that cannot preempt the kernel.
- */
-#define CORTEX_PRIORITY_PENDSV          CORTEX_MAX_KERNEL_PRIORITY
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
-/**
- * @brief   Macro defining the specific ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM_v7M
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "ARMv7-M"
-
-/**
- * @brief   Name of the architecture variant.
- */
-#define CH_CORE_VARIANT_NAME            "Cortex-M3"
-
-#elif (CORTEX_MODEL == CORTEX_M4)
-#define CH_ARCHITECTURE_ARM_v7ME
-#define CH_ARCHITECTURE_NAME            "ARMv7-ME"
-#if CORTEX_USE_FPU
-#define CH_CORE_VARIANT_NAME            "Cortex-M4F"
-#else
-#define CH_CORE_VARIANT_NAME            "Cortex-M4"
-#endif
-#endif
-
-/**
- * @brief   Port-specific information string.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define CH_PORT_INFO                    "Advanced kernel mode"
-#else
-#define CH_PORT_INFO                    "Compact kernel mode"
-#endif
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-/**
- * @brief   Generic ARM register.
- */
-typedef void *regarm_t;
-
-/* The documentation of the following declarations is in chconf.h in order
-   to not have duplicated structure names into the documentation.*/
-#if !defined(__DOXYGEN__)
-
-typedef uint64_t stkalign_t __attribute__ ((aligned (8)));
-
-struct extctx {
-  regarm_t      r0;
-  regarm_t      r1;
-  regarm_t      r2;
-  regarm_t      r3;
-  regarm_t      r12;
-  regarm_t      lr_thd;
-  regarm_t      pc;
-  regarm_t      xpsr;
-#if CORTEX_USE_FPU
-  regarm_t      s0;
-  regarm_t      s1;
-  regarm_t      s2;
-  regarm_t      s3;
-  regarm_t      s4;
-  regarm_t      s5;
-  regarm_t      s6;
-  regarm_t      s7;
-  regarm_t      s8;
-  regarm_t      s9;
-  regarm_t      s10;
-  regarm_t      s11;
-  regarm_t      s12;
-  regarm_t      s13;
-  regarm_t      s14;
-  regarm_t      s15;
-  regarm_t      fpscr;
-  regarm_t      fpccr;
-#endif /* CORTEX_USE_FPU */
-};
-
-struct intctx {
-#if CORTEX_USE_FPU
-  regarm_t      s16;
-  regarm_t      s17;
-  regarm_t      s18;
-  regarm_t      s19;
-  regarm_t      s20;
-  regarm_t      s21;
-  regarm_t      s22;
-  regarm_t      s23;
-  regarm_t      s24;
-  regarm_t      s25;
-  regarm_t      s26;
-  regarm_t      s27;
-  regarm_t      s28;
-  regarm_t      s29;
-  regarm_t      s30;
-  regarm_t      s31;
-#endif /* CORTEX_USE_FPU */
-  regarm_t      r4;
-  regarm_t      r5;
-  regarm_t      r6;
-  regarm_t      r7;
-  regarm_t      r8;
-  regarm_t      r9;
-  regarm_t      r10;
-  regarm_t      r11;
-  regarm_t      lr;
-};
-
-#endif /* !defined(__DOXYGEN__) */
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- *          structure representing the stack pointer at context switch time.
- */
-struct context {
-  struct intctx *r13;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
-                                     wsize -                                \
-                                     sizeof(struct intctx));                \
-  tp->p_ctx.r13->r4 = (void *)(pf);                                         \
-  tp->p_ctx.r13->r5 = (void *)(arg);                                        \
-  tp->p_ctx.r13->lr = (void *)(_port_thread_start);                         \
-}
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Fast IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_FAST_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Port-related initialization code.
- */
-#define port_init() _port_init()
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform
- *          more actions.
- * @note    In this port this it raises the base priority to kernel level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
-#define port_lock() {                                                       \
-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;                 \
-  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");            \
-}
-#else /* !CH_OPTIMIZE_SPEED */
-#define port_lock() {                                                       \
-  asm volatile ("bl      _port_lock" : : : "r3", "lr", "memory");           \
-}
-#endif /* !CH_OPTIMIZE_SPEED */
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_lock() asm volatile ("cpsid   i" : : : "memory")
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform
- *          more actions.
- * @note    In this port this it lowers the base priority to user level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
-#define port_unlock() {                                                     \
-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;               \
-  asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");            \
-}
-#else /* !CH_OPTIMIZE_SPEED */
-#define port_unlock() {                                                     \
-  asm volatile ("bl      _port_unlock" : : : "r3", "lr", "memory");         \
-}
-#endif /* !CH_OPTIMIZE_SPEED */
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_unlock() asm volatile ("cpsie   i" : : : "memory")
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependent,
- *          in its simplest form it is void.
- * @note    Same as @p port_lock() in this port.
- */
-#define port_lock_from_isr() port_lock()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- * @note    Same as @p port_unlock() in this port.
- */
-#define port_unlock_from_isr() port_unlock()
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Of course non-maskable interrupt sources are not included.
- * @note    In this port it disables all the interrupt sources by raising
- *          the priority mask to level 0.
- */
-#define port_disable() asm volatile ("cpsid   i" : : : "memory")
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- * @note    Interrupt sources above kernel level remains enabled.
- * @note    In this port it raises/lowers the base priority to kernel level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_suspend() {                                                    \
-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;                 \
-  asm volatile ("msr     BASEPRI, %0                    \n\t"               \
-                "cpsie   i" : : "r" (tmp) : "memory");                      \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_suspend() asm volatile ("cpsid   i" : : : "memory")
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Enables all the interrupt sources.
- * @note    In this port it lowers the base priority to user level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_enable() {                                                     \
-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;               \
-  asm volatile ("msr     BASEPRI, %0                    \n\t"               \
-                "cpsie   i" : : "r" (tmp) : "memory");                      \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_enable() asm volatile ("cpsie   i" : : : "memory")
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- * @note    Implemented as an inlined @p WFI instruction.
- */
-#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() {                                         \
-  asm volatile ("wfi" : : : "memory");                                      \
-}
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-#else
-#define port_switch(ntp, otp) {                                             \
-  register struct intctx *r13 asm ("r13");                                  \
-  if ((stkalign_t *)(r13 - 1) < otp->p_stklimit)                            \
-    chDbgPanic("stack overflow");                                           \
-  _port_switch(ntp, otp);                                                   \
-}
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_halt(void);
-  void _port_init(void);
-  void _port_irq_epilogue(void);
-  void _port_switch_from_isr(void);
-  void _port_exit_from_isr(void);
-  void _port_switch(Thread *ntp, Thread *otp);
-  void _port_thread_start(void);
-#if !CH_OPTIMIZE_SPEED
-  void _port_lock(void);
-  void _port_unlock(void);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_V7M_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/chtypes.h b/os/ports/GCC/ARMCMx/chtypes.h
deleted file mode 100644
index 5116a79a7..000000000
--- a/os/ports/GCC/ARMCMx/chtypes.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/ARMCMx/chtypes.h
- * @brief   ARM Cortex-Mx port system types.
- *
- * @addtogroup ARMCMx_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint32_t        tprio_t;        /**< Thread priority.               */
-typedef int32_t         msg_t;          /**< Inter-thread message.          */
-typedef int32_t         eventid_t;      /**< Event Id.                      */
-typedef uint32_t        eventmask_t;    /**< Event mask.                    */
-typedef uint32_t        flagsmask_t;    /**< Event flags.                   */
-typedef uint32_t        systime_t;      /**< System time.                   */
-typedef int32_t         cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    It uses the "packed" GCC attribute.
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-/**
- * @brief   Packed variable specifier.
- */
-#define PACKED_VAR __attribute__((packed))
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/crt0.c b/os/ports/GCC/ARMCMx/crt0.c
deleted file mode 100644
index 5151de43e..000000000
--- a/os/ports/GCC/ARMCMx/crt0.c
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    ARMCMx/crt0.c
- * @brief   Generic ARMvx-M (Cortex-M0/M1/M3/M4) startup file for ChibiOS/RT.
- *
- * @addtogroup ARMCMx_STARTUP
- * @{
- */
-
-#include <stdint.h>
-
-#if !defined(FALSE)
-#define FALSE       0
-#endif
-
-#if !defined(TRUE)
-#define TRUE        (!FALSE)
-#endif
-
-#define SCB_CPACR               *((uint32_t *)0xE000ED88U)
-#define SCB_FPCCR               *((uint32_t *)0xE000EF34U)
-#define SCB_FPDSCR              *((uint32_t *)0xE000EF3CU)
-#define FPCCR_ASPEN             (0x1U << 31)
-#define FPCCR_LSPEN             (0x1U << 30)
-
-typedef void (*funcp_t)(void);
-typedef funcp_t * funcpp_t;
-
-#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
-
-/*
- * Area fill code, it is a macro because here functions cannot be called
- * until stacks are initialized.
- */
-#define fill32(start, end, filler) {                                        \
-  uint32_t *p1 = start;                                                     \
-  uint32_t *p2 = end;                                                       \
-  while (p1 < p2)                                                           \
-    *p1++ = filler;                                                         \
-}
-
-/*===========================================================================*/
-/**
- * @name    Startup settings
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Control special register initialization value.
- * @details The system is setup to run in privileged mode using the PSP
- *          stack (dual stack mode).
- */
-#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
-#define CRT0_CONTROL_INIT           0x00000002
-#endif
-
-/**
- * @brief   Stack segments initialization switch.
- */
-#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
-#define CRT0_STACKS_FILL_PATTERN    0x55555555
-#endif
-
-/**
- * @brief   Stack segments initialization switch.
- */
-#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
-#define CRT0_INIT_STACKS            TRUE
-#endif
-
-/**
- * @brief   DATA segment initialization switch.
- */
-#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
-#define CRT0_INIT_DATA              TRUE
-#endif
-
-/**
- * @brief   BSS segment initialization switch.
- */
-#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
-#define CRT0_INIT_BSS               TRUE
-#endif
-
-/**
- * @brief   Constructors invocation switch.
- */
-#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
-#define CRT0_CALL_CONSTRUCTORS      TRUE
-#endif
-
-/**
- * @brief   Destructors invocation switch.
- */
-#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
-#define CRT0_CALL_DESTRUCTORS       TRUE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name    Symbols from the scatter file
- */
-/*===========================================================================*/
-
-/**
- * @brief   Main stack lower boundary.
- * @details This symbol must be exported by the linker script and represents
- *          the main stack lower boundary.
- */
-extern uint32_t __main_stack_base__;
-
-/**
- *
- * @brief   Main stack initial position.
- * @details This symbol must be exported by the linker script and represents
- *          the main stack initial position.
- */
-extern uint32_t __main_stack_end__;
-
-/**
- * @brief   Process stack lower boundary.
- * @details This symbol must be exported by the linker script and represents
- *          the process stack lower boundary.
- */
-extern uint32_t __process_stack_base__;
-
-/**
- * @brief   Process stack initial position.
- * @details This symbol must be exported by the linker script and represents
- *          the process stack initial position.
- */
-extern uint32_t __process_stack_end__;
-
-/**
- * @brief   ROM image of the data segment start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _textdata;
-
-/**
- * @brief   Data segment start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _data;
-
-/**
- * @brief   Data segment end.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _edata;
-
-/**
- * @brief   BSS segment start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _bss_start;
-
-/**
- * @brief   BSS segment end.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _bss_end;
-
-/**
- * @brief   Constructors table start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __init_array_start;
-
-/**
- * @brief   Constructors table end.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __init_array_end;
-
-/**
- * @brief   Destructors table start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __fini_array_start;
-
-/**
- * @brief   Destructors table end.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __fini_array_end;
-
-/** @} */
-
-/**
- * @brief   Application @p main() function.
- */
-extern void main(void);
-
-/**
- * @brief   Early initialization.
- * @details This hook is invoked immediately after the stack initialization
- *          and before the DATA and BSS segments initialization. The
- *          default behavior is to do nothing.
- * @note    This function is a weak symbol.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void __early_init(void) {}
-
-/**
- * @brief   Late initialization.
- * @details This hook is invoked after the DATA and BSS segments
- *          initialization and before any static constructor. The
- *          default behavior is to do nothing.
- * @note    This function is a weak symbol.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void __late_init(void) {}
-
-/**
- * @brief   Default @p main() function exit handler.
- * @details This handler is invoked or the @p main() function exit. The
- *          default behavior is to enter an infinite loop.
- * @note    This function is a weak symbol.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak, naked))
-#endif
-void _default_exit(void) {
-  while (1)
-    ;
-}
-
-/**
- * @brief   Reset vector.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void ResetHandler(void) {
-  uint32_t psp, reg;
-
-  /* Process Stack initialization, it is allocated starting from the
-     symbol __process_stack_end__ and its lower limit is the symbol
-     __process_stack_base__.*/
-  asm volatile ("cpsid   i");
-  psp = SYMVAL(__process_stack_end__);
-  asm volatile ("msr     PSP, %0" : : "r" (psp));
-
-#if CORTEX_USE_FPU
-  /* Initializing the FPU context save in lazy mode.*/
-  SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
-
-  /* CP10 and CP11 set to full access.*/
-  SCB_CPACR |= 0x00F00000;
-
-  /* FPSCR and FPDSCR initially zero.*/
-  reg = 0;
-  asm volatile ("vmsr    FPSCR, %0" : : "r" (reg) : "memory");
-  SCB_FPDSCR = reg;
-
-  /* CPU mode initialization, enforced FPCA bit.*/
-  reg = CRT0_CONTROL_INIT | 4;
-#else
-  /* CPU mode initialization.*/
-  reg = CRT0_CONTROL_INIT;
-#endif
-  asm volatile ("msr     CONTROL, %0" : : "r" (reg));
-  asm volatile ("isb");
-
-#if CRT0_INIT_STACKS
-  /* Main and Process stacks initialization.*/
-  fill32(&__main_stack_base__,
-         &__main_stack_end__,
-         CRT0_STACKS_FILL_PATTERN);
-  fill32(&__process_stack_base__,
-         &__process_stack_end__,
-         CRT0_STACKS_FILL_PATTERN);
-#endif
-
-  /* Early initialization hook invocation.*/
-  __early_init();
-
-#if CRT0_INIT_DATA
-  /* DATA segment initialization.*/
-  {
-    uint32_t *tp, *dp;
-
-    tp = &_textdata;
-    dp = &_data;
-    while (dp < &_edata)
-      *dp++ = *tp++;
-  }
-#endif
-
-#if CRT0_INIT_BSS
-  /* BSS segment initialization.*/
-  fill32(&_bss_start, &_bss_end, 0);
-#endif
-
-  /* Late initialization hook invocation.*/
-  __late_init();
-
-#if CRT0_CALL_CONSTRUCTORS
-  /* Constructors invocation.*/
-  {
-    funcpp_t fpp = &__init_array_start;
-    while (fpp < &__init_array_end) {
-      (*fpp)();
-      fpp++;
-    }
-  }
-#endif
-
-  /* Invoking application main() function.*/
-  main();
-
-#if CRT0_CALL_DESTRUCTORS
-  /* Destructors invocation.*/
-  {
-    funcpp_t fpp = &__fini_array_start;
-    while (fpp < &__fini_array_end) {
-      (*fpp)();
-      fpp++;
-    }
-  }
-#endif
-
-  /* Invoking the exit handler.*/
-  _default_exit();
-}
-
-/** @} */
diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox
deleted file mode 100644
index 4f209e654..000000000
--- a/os/ports/GCC/ARMCMx/port.dox
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup ARMCMx ARM Cortex-Mx
- * @details ARM Cortex-Mx port for the GCC compiler.
- *
- * @section ARMCMx_INTRO Introduction
- * This port supports all the cores implementing the ARMv6-M and ARMv7-M
- * architectures.
- *
- * @section ARMCMx_MODES Kernel Modes
- * The Cortex-Mx port supports two distinct kernel modes:
- * - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
- *   interrupt sources with priorities below or equal to the
- *   @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
- *   the kernel critical sections and can be used for fast interrupts.
- *   This mode is not available in the ARMv6-M architecture which does not
- *   support priority masking.
- * - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
- *   in a simplified way, all interrupt sources are disabled when the kernel
- *   enters into a critical zone and re-enabled on exit. This is simple and
- *   adequate for most applications, this mode results in a more compact and
- *   faster kernel.
- * .
- * The selection of the mode is performed using the port configuration option
- * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
- * interrupts there are no other differences between the two modes. The
- * kernel API is exactly the same.
- *
- * @section ARMCMx_STATES_A System logical states in Compact Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
- * Kernel mode:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). In this state interrupts are enabled. The processor
- *   is running in thread-privileged mode.
- * - <b>Suspended</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in thread-privileged mode. In this
- *   mode this state is not different from the <b>Disabled</b> state.
- * - <b>Disabled</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in thread-privileged mode. In this
- *   mode this state is not different from the <b>Suspended</b> state.
- * - <b>Sleep</b>. This state is entered with the execution of the specific
- *   instruction @p <b>wfi</b>.
- * - <b>S-Locked</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in thread-privileged mode.
- * - <b>I-Locked</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in exception-privileged mode.
- * - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
- *   not globally masked but only interrupts with higher priority can preempt
- *   the current handler. The processor is running in exception-privileged
- *   mode.
- * - <b>Serving Fast Interrupt</b>. Not implemented in compact kernel mode.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
- *   asynchronous NMI vector and several synchronous fault vectors that can
- *   be considered belonging to this category.
- * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
- *   the maskable interrupt sources. The ARM state is whatever the processor
- *   was running when @p chSysHalt() was invoked.
- *
- * @section ARMCMx_STATES_B System logical states in Advanced Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the
- * Advanced Kernel mode:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
- *   set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
- *   processor is running in thread-privileged mode.
- * - <b>Suspended</b>. In this state the interrupt sources are not globally
- *   masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- *   masking any interrupt source with lower or equal priority. The processor
- *   is running in thread-privileged mode.
- * - <b>Disabled</b>. Interrupt sources are globally masked. The processor
- *   is running in thread-privileged mode.
- * - <b>Sleep</b>. This state is entered with the execution of the specific
- *   instruction @p <b>wfi</b>.
- * - <b>S-Locked</b>. In this state the interrupt sources are not globally
- *   masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- *   masking any interrupt source with lower or equal priority. The processor
- *   is running in thread-privileged mode.
- * - <b>I-Locked</b>. In this state the interrupt sources are not globally
- *   masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- *   masking any interrupt source with lower or equal priority. The processor
- *   is running in exception-privileged mode.
- * - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
- *   not globally masked but only interrupts with higher priority can preempt
- *   the current handler. The processor is running in exception-privileged
- *   mode.
- * - <b>Serving Fast Interrupt</b>. Fast interrupts are defined as interrupt
- *   sources having higher priority level than the kernel
- *   (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to
- *   the I-Locked state because fast interrupts can preempt the kernel
- *   critical zone.<br>
- *   This state is not implemented in the ARMv6-M implementation because
- *   priority masking is not present in this architecture.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
- *   asynchronous NMI vector and several synchronous fault vectors that can
- *   be considered belonging to this category.
- * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
- *   the maskable interrupt sources. The ARM state is whatever the processor
- *   was running when @p chSysHalt() was invoked.
- * .
- * @section ARMCMx_NOTES ARM Cortex-Mx/GCC port notes
- * The ARM Cortex-Mx port is organized as follow:
- * - The @p main() function is invoked in thread-privileged mode.
- * - Each thread has a private process stack, the system has a single main
- *   stack where all the interrupts and exceptions are processed.
- * - The threads are started in thread-privileged mode.
- * - Interrupt nesting and the other advanced core/NVIC features are supported.
- * - The Cortex-Mx port is perfectly generic, support for more devices can be
- *   easily added by adding a subdirectory under <tt>./os/ports/GCC/ARMCMx</tt>
- *   and giving it the name of the new device, then copy the files from another
- *   device into the new directory and customize them for the new device.
- * .
- * @ingroup gcc
- */
-
-/**
- * @defgroup ARMCMx_CONF Configuration Options
- * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some
- * architecture-specific configurations settings that can be overridden
- * by redefining them in @p chconf.h. Usually there is no need to change
- * the default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
- *   by an interrupt handler between the @p extctx and @p intctx
- *   structures.
- * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
- *   thread. Usually there is no need to change this value unless inserting
- *   code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
- * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
- * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
- * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
- *   @p <b>wfi</b> instruction from within the idle loop. This option is
- *   defaulted to FALSE because it can create problems with some debuggers.
- *   Setting this option to TRUE reduces the system power requirements.
- * .
- * @section ARMCMx_CONF_1 ARMv6-M specific options
- * The following options are specific for the ARMv6-M architecture:
- * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
- *   exception instead of NMI as preemption handler.
- * .
- * @section ARMCMx_CONF_2 ARMv7-M specific options
- * The following options are specific for the ARMv6-M architecture:
- * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
- * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
- *   mode.
- * .
- * @ingroup ARMCMx
- */
-
-/**
- * @defgroup ARMCMx_CORE Core Port Implementation
- * @details ARM Cortex-Mx specific port code, structures and macros.
- *
- * @ingroup ARMCMx
- */
-
-/**
- * @defgroup ARMCMx_V6M_CORE ARMv6-M Specific Implementation
- * @details ARMv6-M specific port code, structures and macros.
- *
- * @ingroup ARMCMx_CORE
- */
-
-/**
- * @defgroup ARMCMx_V7M_CORE ARMv7-M Specific Implementation
- * @details ARMv7-M specific port code, structures and macros.
- *
- * @ingroup ARMCMx_CORE
- */
-
-/**
- * @defgroup ARMCMx_STARTUP Startup Support
- * @details ChibiOS/RT provides its own generic startup file for the ARM
- * Cortex-Mx port.
- * Of course it is not mandatory to use it but care should be taken about the
- * startup phase details.
- *
- * @section ARMCMx_STARTUP_1 Startup Process
- * The startup process, as implemented, is the following:
- * -# Interrupts are masked globally.
- * -# The two stacks are initialized by assigning them the sizes defined in
- *    the linker script (also known as scatter file).
- * -# The CPU state is switched to Privileged and the PSP stack is used.
- * -# An early initialization routine @p __early_init() is invoked, if the
- *    symbol is not defined then an empty default routine is executed
- *    (weak symbol).
- * -# DATA and BSS segments are initialized.
- * -# Constructors are invoked.
- * -# The @p main() function is invoked with no parameters.
- * -# Destructors are invoked.
- * -# A branch is performed to the weak symbol @p _default_exit(). The
- *    default code is an endless empty loop.
- * .
- * @section ARMCMx_STARTUP_2 Expected linker symbols
- * The startup code starts at the symbol @p ResetHandler and expects the
- * following symbols to be defined in the linker script:
- * - @p __ram_end__, end of RAM.
- * - @p __main_stack_base__, main stack lower boundary.
- * - @p __main_stack_end__, main stack initial position.
- * - @p __process_stack_base__, process stack lower boundary.
- * - @p __process_stack_end__, process stack initial position.
- * - @p _textdata, address of the data segment source read only data.
- * - @p _data, start of the data segment.
- * - @p _edata, end of the data segment end location.
- * - @p _bss_start, start of the BSS.
- * - @p _bss_end, end of the BSS segment.
- * - @p __init_array_start, start of the constructors array.
- * - @p __init_array_end, end of the constructors array.
- * - @p __fini_array_start, start of the destructors array.
- * - @p __fini_array_end, end of the destructors array.
- * .
- * Additionally the kernel expects the following symbols:
- * - @p __main_thread_stack_base__, this symbol is required when the
- *   stack checking is enabled (<tt>CH_DBG_ENABLE_STACK_CHECK==TRUE</tt>),
- *   it is an alias of @p __process_stack_base__ in this port.
- * - @p __heap_base__ and @p __heap_end__, those symbols are required
- *   if the memory core manager is enabled (<tt>CH_USE_MEMCORE==TRUE</tt>)
- *   with a default core size set to zero (<tt>CH_MEMCORE_SIZE==0</tt>).
- * .
- * @ingroup ARMCMx
- */
-
-/**
- * @defgroup ARMCMx_SPECIFIC Specific Implementations
- * @details Platform-specific port code.
- *
- * @ingroup ARMCMx
- */
diff --git a/os/ports/GCC/ARMCMx/rules.mk b/os/ports/GCC/ARMCMx/rules.mk
deleted file mode 100644
index 33531d201..000000000
--- a/os/ports/GCC/ARMCMx/rules.mk
+++ /dev/null
@@ -1,220 +0,0 @@
-# ARM Cortex-Mx common makefile scripts and rules.
-
-# Output directory and files
-ifeq ($(BUILDDIR),)
-  BUILDDIR = build
-endif
-ifeq ($(BUILDDIR),.)
-  BUILDDIR = build
-endif
-OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
-           $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp
-
-# Automatic compiler options
-OPT = $(USE_OPT)
-COPT = $(USE_COPT)
-CPPOPT = $(USE_CPPOPT)
-ifeq ($(USE_LINK_GC),yes)
-  OPT += -ffunction-sections -fdata-sections -fno-common
-endif
-
-# Source files groups and paths
-ifeq ($(USE_THUMB),yes)
-  TCSRC += $(CSRC)
-  TCPPSRC += $(CPPSRC)
-else
-  ACSRC += $(CSRC)
-  ACPPSRC += $(CPPSRC)
-endif
-ASRC	  = $(ACSRC)$(ACPPSRC)
-TSRC	  = $(TCSRC)$(TCPPSRC)
-SRCPATHS  = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
-
-# Various directories
-OBJDIR    = $(BUILDDIR)/obj
-LSTDIR    = $(BUILDDIR)/lst
-
-# Object files groups
-ACOBJS    = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
-ACPPOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
-TCOBJS    = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
-TCPPOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
-ASMOBJS   = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
-ASMXOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
-OBJS	  = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
-
-# Paths
-IINCDIR   = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
-LLIBDIR   = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
-
-# Macros
-DEFS      = $(DDEFS) $(UDEFS)
-ADEFS 	  = $(DADEFS) $(UADEFS)
-
-# Libs
-LIBS      = $(DLIBS) $(ULIBS)
-
-# Various settings
-MCFLAGS   = -mcpu=$(MCU)
-ODFLAGS	  = -x --syms
-ASFLAGS   = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
-ASXFLAGS  = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
-CFLAGS    = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
-CPPFLAGS  = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
-ifeq ($(USE_LINK_GC),yes)
-  LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR)
-else
-  LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR)
-endif
-
-# Thumb interwork enabled only if needed because it kills performance.
-ifneq ($(TSRC),)
-  CFLAGS   += -DTHUMB_PRESENT
-  CPPFLAGS += -DTHUMB_PRESENT
-  ASFLAGS  += -DTHUMB_PRESENT
-  ifneq ($(ASRC),)
-    # Mixed ARM and THUMB mode.
-    CFLAGS   += -mthumb-interwork
-    CPPFLAGS += -mthumb-interwork
-    ASFLAGS  += -mthumb-interwork
-    LDFLAGS  += -mthumb-interwork
-  else
-    # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
-    CFLAGS   += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
-    CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
-    ASFLAGS  += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
-    LDFLAGS  += -mno-thumb-interwork -mthumb
-  endif
-else
-  # Pure ARM mode
-  CFLAGS   += -mno-thumb-interwork
-  CPPFLAGS += -mno-thumb-interwork
-  ASFLAGS  += -mno-thumb-interwork
-  LDFLAGS  += -mno-thumb-interwork
-endif
-
-# Generate dependency information
-CFLAGS   += -MD -MP -MF .dep/$(@F).d
-CPPFLAGS += -MD -MP -MF .dep/$(@F).d
-
-# Paths where to search for sources
-VPATH     = $(SRCPATHS)
-
-#
-# Makefile rules
-#
-
-all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK
-
-MAKE_ALL_RULE_HOOK:
-
-$(OBJS): | $(BUILDDIR)
-
-$(BUILDDIR) $(OBJDIR) $(LSTDIR):
-ifneq ($(USE_VERBOSE_COMPILE),yes)
-	@echo Compiler Options
-	@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
-	@echo
-endif
-	mkdir -p $(OBJDIR)
-	mkdir -p $(LSTDIR)
-
-$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
-endif
-
-$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo 
-	$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
-endif
-
-%.elf: $(OBJS) $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
-else
-	@echo Linking $@
-	@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
-endif
-
-%.hex: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(HEX) $< $@
-else
-	@echo Creating $@
-	@$(HEX) $< $@
-endif
-
-%.bin: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(BIN) $< $@
-else
-	@echo Creating $@
-	@$(BIN) $< $@
-endif
-
-%.dmp: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(OD) $(ODFLAGS) $< > $@
-else
-	@echo Creating $@
-	@$(OD) $(ODFLAGS) $< > $@
-	@echo Done
-endif
-
-clean:
-	@echo Cleaning
-	-rm -fR .dep $(BUILDDIR)
-	@echo Done
-
-#
-# Include the dependency files, should be the last of the makefile
-#
--include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
-
-# *** EOF ***
diff --git a/os/ports/GCC/AVR/chcore.c b/os/ports/GCC/AVR/chcore.c
deleted file mode 100644
index d7a33ecad..000000000
--- a/os/ports/GCC/AVR/chcore.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    AVR/chcore.c
- * @brief   AVR architecture port code.
- *
- * @addtogroup AVR_CORE
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- * @note    The function is declared as a weak symbol, it is possible to
- *          redefine it in your application code.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked, weak))
-#endif
-void port_switch(Thread *ntp, Thread *otp) {
-
-  asm volatile ("push    r2");
-  asm volatile ("push    r3");
-  asm volatile ("push    r4");
-  asm volatile ("push    r5");
-  asm volatile ("push    r6");
-  asm volatile ("push    r7");
-  asm volatile ("push    r8");
-  asm volatile ("push    r9");
-  asm volatile ("push    r10");
-  asm volatile ("push    r11");
-  asm volatile ("push    r12");
-  asm volatile ("push    r13");
-  asm volatile ("push    r14");
-  asm volatile ("push    r15");
-  asm volatile ("push    r16");
-  asm volatile ("push    r17");
-  asm volatile ("push    r28");
-  asm volatile ("push    r29");
-
-  asm volatile ("movw    r30, r22");
-  asm volatile ("in      r0, 0x3d");
-  asm volatile ("std     Z+5, r0");
-  asm volatile ("in      r0, 0x3e");
-  asm volatile ("std     Z+6, r0");
-
-  asm volatile ("movw    r30, r24");
-  asm volatile ("ldd     r0, Z+5");
-  asm volatile ("out     0x3d, r0");
-  asm volatile ("ldd     r0, Z+6");
-  asm volatile ("out     0x3e, r0");
-
-  asm volatile ("pop     r29");
-  asm volatile ("pop     r28");
-  asm volatile ("pop     r17");
-  asm volatile ("pop     r16");
-  asm volatile ("pop     r15");
-  asm volatile ("pop     r14");
-  asm volatile ("pop     r13");
-  asm volatile ("pop     r12");
-  asm volatile ("pop     r11");
-  asm volatile ("pop     r10");
-  asm volatile ("pop     r9");
-  asm volatile ("pop     r8");
-  asm volatile ("pop     r7");
-  asm volatile ("pop     r6");
-  asm volatile ("pop     r5");
-  asm volatile ("pop     r4");
-  asm volatile ("pop     r3");
-  asm volatile ("pop     r2");
-  asm volatile ("ret");
-}
-
-/**
- * @brief   Halts the system.
- * @details This function is invoked by the operating system when an
- *          unrecoverable error is detected (for example because a programming
- *          error in the application code that triggers an assertion while in
- *          debug mode).
- * @note    The function is declared as a weak symbol, it is possible to
- *          redefine it in your application code.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/**
- * @brief   Start a thread by invoking its work function.
- * @details If the work function returns @p chThdExit() is automatically
- *          invoked.
- */
-void _port_thread_start(void) {
-
-  chSysUnlock();
-  asm volatile ("movw    r24, r4");
-  asm volatile ("movw    r30, r2");
-  asm volatile ("icall");
-  asm volatile ("call    chThdExit");
-}
-
-/** @} */
diff --git a/os/ports/GCC/AVR/chcore.h b/os/ports/GCC/AVR/chcore.h
deleted file mode 100644
index 203c6886f..000000000
--- a/os/ports/GCC/AVR/chcore.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    AVR/chcore.h
- * @brief   AVR architecture port macros and structures.
- *
- * @addtogroup AVR_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-#include <avr/io.h>
-#include <avr/interrupt.h>
-
-#if CH_DBG_ENABLE_STACK_CHECK
-#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port"
-#endif
-
-/**
- * @brief   If enabled allows the idle thread to enter a low power mode.
- */
-#ifndef ENABLE_WFI_IDLE
-#define ENABLE_WFI_IDLE                 0
-#endif
-
-/**
- * @brief   Macro defining the AVR architecture.
- */
-#define CH_ARCHITECTURE_AVR
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "AVR"
-
-/**
- * @brief   Name of the architecture variant (optional).
- */
-#define CH_CORE_VARIANT_NAME            "MegaAVR"
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "GCC " __VERSION__
-
-/**
- * @brief   Port-specific information string.
- */
-#define CH_PORT_INFO                    "None"
-
-/**
- * @brief   8 bits stack and memory alignment enforcement.
- */
-typedef uint8_t stkalign_t;
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- * @note    The field @p _next is not part of the context, it represents the
- *          offset of the structure relative to the stack pointer.
- */
-struct extctx {
-  uint8_t       _next;
-  uint8_t       r31;
-  uint8_t       r30;
-  uint8_t       r27;
-  uint8_t       r26;
-  uint8_t       r25;
-  uint8_t       r24;
-  uint8_t       r23;
-  uint8_t       r22;
-  uint8_t       r21;
-  uint8_t       r20;
-  uint8_t       r19;
-  uint8_t       r18;
-  uint8_t       sr;
-  uint8_t       r1;
-  uint8_t       r0;
-  uint16_t      pc;
-};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching.
- * @note    The field @p _next is not part of the context, it represents the
- *          offset of the structure relative to the stack pointer.
- */
-struct intctx {
-  uint8_t       _next;
-  uint8_t       r29;
-  uint8_t       r28;
-  uint8_t       r17;
-  uint8_t       r16;
-  uint8_t       r15;
-  uint8_t       r14;
-  uint8_t       r13;
-  uint8_t       r12;
-  uint8_t       r11;
-  uint8_t       r10;
-  uint8_t       r9;
-  uint8_t       r8;
-  uint8_t       r7;
-  uint8_t       r6;
-  uint8_t       r5;
-  uint8_t       r4;
-  uint8_t       r3;
-  uint8_t       r2;
-  uint8_t       pcl;
-  uint8_t       pch;
-};
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details In the AVR port this structure just holds a pointer to the
- *          @p intctx structure representing the stack pointer at the time
- *          of the context switch.
- */
-struct context {
-  struct intctx *sp;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  tp->p_ctx.sp = (struct intctx*)((uint8_t *)workspace + wsize  -           \
-                                  sizeof(struct intctx));                   \
-  tp->p_ctx.sp->r2  = (int)pf;                                              \
-  tp->p_ctx.sp->r3  = (int)pf >> 8;                                         \
-  tp->p_ctx.sp->r4  = (int)arg;                                             \
-  tp->p_ctx.sp->r5  = (int)arg >> 8;                                        \
-  tp->p_ctx.sp->pcl = (int)_port_thread_start >> 8;                         \
-  tp->p_ctx.sp->pch = (int)_port_thread_start;                              \
-}
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- * @note    In this port it is set to 8.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     8
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- *          This value can be zero on those architecture where there is a
- *          separate interrupt stack and the stack space between @p intctx and
- *          @p extctx is known to be zero.
- * @note    In this port the default is 32 bytes per thread.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK     32
-#endif
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   (sizeof(struct intctx) - 1) +            \
-                                   (sizeof(struct extctx) - 1) +            \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- * @note    This code tricks the compiler to save all the specified registers
- *          by "touching" them.
- */
-#define PORT_IRQ_PROLOGUE() {                                               \
-  asm ("" : : : "r18", "r19", "r20", "r21", "r22", "r23", "r24",            \
-                "r25", "r26", "r27", "r30", "r31");                         \
-}
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() {                                               \
-  dbg_check_lock();                                                         \
-  if (chSchIsPreemptionRequired())                                          \
-    chSchDoReschedule();                                                    \
-  dbg_check_unlock();                                                       \
-}
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) ISR(id)
-
-/**
- * @brief   Port-related initialization code.
- * @note    This function is empty in this port.
- */
-#define port_init()
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform more
- *          actions.
- * @note    Implemented as global interrupt disable.
- */
-#define port_lock() asm volatile ("cli" : : : "memory")
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform more
- *          actions.
- * @note    Implemented as global interrupt enable.
- */
-#define port_unlock() asm volatile ("sei" : : : "memory")
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependent,
- *          in its simplest form it is void.
- * @note    This function is empty in this port.
- */
-#define port_lock_from_isr()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- * @note    This function is empty in this port.
- */
-#define port_unlock_from_isr()
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Of course non-maskable interrupt sources are not included.
- * @note    Implemented as global interrupt disable.
- */
-#define port_disable() asm volatile ("cli" : : : "memory")
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- * @note    Interrupt sources above kernel level remains enabled.
- * @note    Same as @p port_disable() in this port, there is no difference
- *          between the two states.
- */
-#define port_suspend() asm volatile ("cli" : : : "memory")
-
-/**
- * @brief   Enables all the interrupt sources.
- * @note    Implemented as global interrupt enable.
- */
-#define port_enable() asm volatile ("sei" : : : "memory")
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- * @note    This port function is implemented as inlined code for performance
- *          reasons.
- */
-#if ENABLE_WFI_IDLE != 0
-#define port_wait_for_interrupt() {                                         \
-  asm volatile ("sleep" : : : "memory");                                    \
-}
-#else
-#define port_wait_for_interrupt()
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_switch(Thread *ntp, Thread *otp);
-  void port_halt(void);
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/AVR/chtypes.h b/os/ports/GCC/AVR/chtypes.h
deleted file mode 100644
index 59d896af4..000000000
--- a/os/ports/GCC/AVR/chtypes.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    AVR/chtypes.h
- * @brief   AVR architecture port system types.
- *
- * @addtogroup AVR_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint8_t         tprio_t;        /**< Thread priority.               */
-typedef int16_t         msg_t;          /**< Inter-thread message.          */
-typedef uint8_t         eventid_t;      /**< Event Id.                      */
-typedef uint8_t         eventmask_t;    /**< Event mask.                    */
-typedef uint8_t         flagsmask_t;    /**< Event flags.                   */
-typedef uint16_t        systime_t;      /**< System time.                   */
-typedef int8_t          cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    It uses the "packed" GCC attribute.
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/AVR/port.dox b/os/ports/GCC/AVR/port.dox
deleted file mode 100644
index 002a37bbc..000000000
--- a/os/ports/GCC/AVR/port.dox
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup AVR MegaAVR
- * @details AVR port for the GCC compiler.
- *
- * @section AVR_STATES Mapping of the System States in the AVR port
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the AVR
- * port:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). Interrupts are enabled.
- * - <b>Suspended</b>. Interrupts are disabled.
- * - <b>Disabled</b>. Interrupts are disabled. This state is equivalent to the
- *   Suspended state because there are no fast interrupts in this architecture.
- * - <b>Sleep</b>. This state is entered with the execution of the specific
- *   instruction @p <b>sleep</b>.
- * - <b>S-Locked</b>. Interrupts are disabled.
- * - <b>I-Locked</b>. This state is equivalent to the SRI state, the
- *   @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
- *   order to formally change state because this may change).
- * - <b>Serving Regular Interrupt</b>. Normal interrupt service code.
- * - <b>Serving Fast Interrupt</b>. Not present in this architecture.
- * - <b>Serving Non-Maskable Interrupt</b>. Not present in this architecture.
- * - <b>Halted</b>. Implemented as an infinite loop with interrupts disabled.
- * .
- * @section AVR_NOTES The AVR port notes
- * - The AVR does not have a dedicated interrupt stack, make sure to reserve
- *   enough stack space for interrupts in each thread stack. This can be done
- *   by modifying the @p INT_REQUIRED_STACK macro into
- *   <b>./ports/AVR/chcore.h</b>.
- * .
- * @ingroup gcc
- */
-
-/**
- * @defgroup AVR_CONF Configuration Options
- * @details AVR Configuration Options. The AVR port allows some
- * architecture-specific configurations settings that can be overridden
- * by redefining them in @p chconf.h. Usually there is no need to change
- * the default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space
- *   used by the interrupt handlers.<br>
- *   The default for this value is @p 32, this space is allocated for each
- *   thread so be careful in order to not waste precious RAM space.
- * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
- *   thread. Usually there is no need to change this value unless inserting
- *   code in the IDLE thread hook macro.
- * .
- * @ingroup AVR
- */
-
-/**
- * @defgroup AVR_CORE Core Port Implementation
- * @details AVR specific port code, structures and macros.
- *
- * @ingroup AVR
- */
-
- /**
- * @defgroup AVR_STARTUP Startup Support
- * @details ChibiOS/RT doed not provide startup files for the AVR, there
- * are no special startup requirement so the normal toolchain-provided
- * startup files can be used.
- *
- * @ingroup AVR
- */
diff --git a/os/ports/GCC/AVR/port.mk b/os/ports/GCC/AVR/port.mk
deleted file mode 100644
index 7cafb56b2..000000000
--- a/os/ports/GCC/AVR/port.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-# List of the ChibiOS/RT AVR port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/AVR/chcore.c
-
-PORTASM = 
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/AVR
diff --git a/os/ports/GCC/MSP430/chcore.h b/os/ports/GCC/MSP430/chcore.h
deleted file mode 100644
index 22dde173d..000000000
--- a/os/ports/GCC/MSP430/chcore.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    MSP430/chcore.h
- * @brief   MSP430 architecture port macros and structures.
- *
- * @addtogroup MSP430_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-#include <iomacros.h>
-#include <isr_compat.h>
-
-#if CH_DBG_ENABLE_STACK_CHECK
-#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port"
-#endif
-
-/**
- * @brief   Enables the use of a wait state in the idle thread loop.
- */
-#ifndef ENABLE_WFI_IDLE
-#define ENABLE_WFI_IDLE                 0
-#endif
-
-/**
- * @brief   Macro defining the MSP430 architecture.
- */
-#define CH_ARCHITECTURE_MSP430
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "MSP430"
-
-/**
- * @brief   Name of the architecture variant (optional).
- */
-#define CH_CORE_VARIANT_NAME            "MSP430"
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "GCC " __VERSION__
-
-/**
- * @brief   Port-specific information string.
- */
-#define CH_PORT_INFO                    "None"
-
-/**
- * @brief   16 bits stack and memory alignment enforcement.
- */
-typedef uint16_t stkalign_t;
-
-/**
- * @brief   Generic MSP430 register.
- */
-typedef void *regmsp_t;
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- */
-struct extctx {
-  regmsp_t      r12;
-  regmsp_t      r13;
-  regmsp_t      r14;
-  regmsp_t      r15;
-  regmsp_t      sr;
-  regmsp_t      pc;
-};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching.
- */
-struct intctx {
-  regmsp_t      r4;
-  regmsp_t      r5;
-  regmsp_t      r6;
-  regmsp_t      r7;
-  regmsp_t      r8;
-  regmsp_t      r9;
-  regmsp_t      r10;
-  regmsp_t      r11;
-  regmsp_t      pc;
-};
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details This structure usually contains just the saved stack pointer
- *          defined as a pointer to a @p intctx structure.
- */
-struct context {
-  struct intctx *sp;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace +                   \
-                                   wsize -                                  \
-                                   sizeof(struct intctx));                  \
-  tp->p_ctx.sp->r10 = pf;                                                   \
-  tp->p_ctx.sp->r11 = arg;                                                  \
-  tp->p_ctx.sp->pc = _port_thread_start;                                    \
-}
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     0
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- *          This value can be zero on those architecture where there is a
- *          separate interrupt stack and the stack space between @p intctx and
- *          @p extctx is known to be zero.
- * @note    In this port the default is 32 bytes per thread.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK         32
-#endif
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() {                                               \
-  dbg_check_lock();                                                         \
-  if (chSchIsPreemptionRequired())                                          \
-    chSchDoReschedule();                                                    \
-  dbg_check_unlock();                                                       \
-}
-
-#define ISRNAME(pre, id) pre##id
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) ISR(id, ISRNAME(vect, id))
-
-/**
- * @brief   Port-related initialization code.
- * @note    This function is empty in this port.
- */
-#define port_init()
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform more
- *          actions.
- * @note    Implemented as global interrupt disable.
- */
-#define port_lock() asm volatile ("dint" : : : "memory")
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform more
- *          actions.
- * @note    Implemented as global interrupt enable.
- */
-#define port_unlock() asm volatile ("eint" : : : "memory")
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependen#define PORT_IRQ_EPILOGUE() {                                           \
-  if (chSchIsPreemptionRequired())                                      \
-    chSchDoReschedule();                                                \
-}
- *          t,
- *          in its simplest form it is void.
- * @note    This function is empty in this port.
- */
-#define port_lock_from_isr()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- * @note    This function is empty in this port.
- */
-#define port_unlock_from_isr()
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Of course non-maskable interrupt sources are not included.
- * @note    Implemented as global interrupt disable.
- */
-#define port_disable() asm volatile ("dint" : : : "memory")
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- * @note    Interrupt sources above kernel level remains enabled.
- * @note    Same as @p port_disable() in this port, there is no difference
- *          between the two states.
- */
-#define port_suspend() asm volatile ("dint" : : : "memory")
-
-/**
- * @brief   Enables all the interrupt sources.
- * @note    Implemented as global interrupt enable.
- */
-#define port_enable() asm volatile ("eint" : : : "memory")
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- * @note    This port function is implemented as inlined code for performance
- *          reasons.
- * @note    The port code does not define a low power mode, this macro has to
- *          be defined externally. The default implementation is a "nop", not
- *          a real low power mode.
- */
-#if ENABLE_WFI_IDLE != 0
-#ifndef port_wait_for_interrupt
-#define port_wait_for_interrupt() {                                         \
-  asm volatile ("nop" : : : "memory");                                      \
-}
-#endif
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Wrapper of the assembler @p _port_switch() function.
- */
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-
-/**
- * @brief   Wrapper of the assembler @p _port_halt() function.
- */
-#define port_halt() _port_halt()
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _port_switch(Thread *ntp, Thread *otp);
-  void _port_halt(void);
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/MSP430/chcoreasm.s b/os/ports/GCC/MSP430/chcoreasm.s
deleted file mode 100644
index 8c42d0856..000000000
--- a/os/ports/GCC/MSP430/chcoreasm.s
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#include "chconf.h"
-
-#define FALSE 0
-#define TRUE 1
-
-        .text
-        .p2align 1, 0
-        .weak   _port_switch
-_port_switch:
-        push    r11
-        push    r10
-        push    r9
-        push    r8
-        push    r7
-        push    r6
-        push    r5
-        push    r4
-        mov r1, 6(r14)
-        mov 6(r15), r1
-        pop     r4
-        pop     r5
-        pop     r6
-        pop     r7
-        pop     r8
-        pop     r9
-        pop     r10
-        pop     r11
-        ret
-
-        .p2align 1, 0
-        .weak   _port_thread_start
-_port_thread_start:
-#if CH_DBG_SYSTEM_STATE_CHECK
-        call    #dbg_check_unlock
-#endif
-        eint
-        mov     r11, r15
-        call    r10
-        call    #chThdExit
-        ; Falls into _port_halt
-
-        .p2align 1, 0
-        .weak   _port_halt
-_port_halt:
-        dint
-.L1:    jmp     .L1
diff --git a/os/ports/GCC/MSP430/chtypes.h b/os/ports/GCC/MSP430/chtypes.h
deleted file mode 100644
index 84ced2aaf..000000000
--- a/os/ports/GCC/MSP430/chtypes.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    MSP430/chtypes.h
- * @brief   MSP430 architecture port system types.
- *
- * @addtogroup MSP430_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint16_t        tprio_t;        /**< Thread priority.               */
-typedef int16_t         msg_t;          /**< Inter-thread message.          */
-typedef int16_t         eventid_t;      /**< Event Id.                      */
-typedef uint16_t        eventmask_t;    /**< Event mask.                    */
-typedef uint16_t        flagsmask_t;    /**< Event flags.                   */
-typedef uint16_t        systime_t;      /**< System time.                   */
-typedef int16_t         cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    It uses the "packed" GCC attribute.
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/MSP430/port.dox b/os/ports/GCC/MSP430/port.dox
deleted file mode 100644
index 8f316d0c4..000000000
--- a/os/ports/GCC/MSP430/port.dox
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup MSP430 MSP430
- * @details MSP430 port for the GCC compiler.
- *
- * @section MSP430_INTRO Introduction
- * This port supports all the cores implementing the MSP430 architecture.
- *
- * @section MSP430_STATES Mapping of the System States in the MSP430 port
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the MSP430
- * port:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). Interrupts are enabled.
- * - <b>Suspended</b>. Interrupts are disabled.
- * - <b>Disabled</b>. Interrupts are disabled. This state is equivalent to the
- *   Suspended state because there are no fast interrupts in this architecture.
- * - <b>Sleep</b>. Not yet implemented.
- * - <b>S-Locked</b>. Interrupts are disabled.
- * - <b>I-Locked</b>. This state is equivalent to the SRI state, the
- *   @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
- *   order to formally change state because this may change).
- * - <b>Serving Regular Interrupt</b>. Normal interrupt service code.
- * - <b>Serving Fast Interrupt</b>. Not present in this architecture.
- * - <b>Serving Non-Maskable Interrupt</b>. The MSP430 has several non
- *   maskable interrupt sources that can be associated to this state.
- * - <b>Halted</b>. Implemented as an infinite loop with interrupts disabled.
- * .
- * @section MSP430_NOTES The MSP430 port notes
- * - The MSP430 does not have a dedicated interrupt stack, make sure to reserve
- *   enough stack space for interrupts in each thread stack. This can be done
- *   by modifying the @p INT_REQUIRED_STACK configuration options.
- * - The state of the hardware multiplier is not saved in the thread context,
- *   make sure to use it in <b>Suspended</b> state (interrupts masked).
- * - The port code does not define the switch to a low power mode for the
- *   idle thread because the MSP430 has several low power modes. You can
- *   select the proper low power mode for you application by defining the
- *   macro @p port_wait_for_interrupt().
- * .
- * @ingroup gcc
- */
-
-/**
- * @defgroup MSP430_CONF Configuration Options
- * @details MSP430 Configuration Options. The MSP430 port allows some
- * architecture-specific configurations settings that can be overridden
- * by redefining them in @p chconf.h. Usually there is no need to change
- * the default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space
- *   used by the interrupt handlers.<br>
- *   The default for this value is @p 32, this space is allocated for each
- *   thread so be careful in order to not waste precious RAM space.
- * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
- *   thread. Usually there is no need to change this value unless inserting
- *   code in the IDLE thread hook macro.
- * .
- * @ingroup MSP430
- */
-
-/**
- * @defgroup MSP430_CORE Core Port Implementation
- * @details MSP430 specific port code, structures and macros.
- *
- * @ingroup MSP430
- */
-
- /**
- * @defgroup MSP430_STARTUP Startup Support
- * @details ChibiOS/RT doed not provide startup files for the MSP430, there
- * are no special startup requirement so the normal toolchain-provided
- * startup files can be used.
- *
- * @ingroup MSP430
- */
diff --git a/os/ports/GCC/MSP430/port.mk b/os/ports/GCC/MSP430/port.mk
deleted file mode 100644
index 8291fa9d9..000000000
--- a/os/ports/GCC/MSP430/port.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-# List of the ChibiOS/RT MSP430 port files.
-PORTSRC =
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/MSP430/chcoreasm.s 
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/MSP430
diff --git a/os/ports/GCC/MSP430/rules.mk b/os/ports/GCC/MSP430/rules.mk
deleted file mode 100644
index e5df10916..000000000
--- a/os/ports/GCC/MSP430/rules.mk
+++ /dev/null
@@ -1,87 +0,0 @@
-# MSP430 makefile scripts and rules.
-
-# Automatic compiler options
-OPT = $(USE_OPT)
-COPT = $(USE_COPT)
-CPPOPT = $(USE_CPPOPT)
-ifeq ($(USE_LINK_GC),yes)
-  OPT += -ffunction-sections -fdata-sections
-endif
-
-# Source files groups
-SRC	     = $(CSRC)$(CPPSRC)
-
-# Object files groups
-COBJS   = $(CSRC:.c=.o)
-CPPOBJS = $(CPPSRC:.cpp=.o)
-ASMOBJS = $(ASMSRC:.s=.o)
-OBJS	= $(ASMOBJS) $(COBJS) $(CPPOBJS)
-
-# Paths
-IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
-LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
-
-# Macros
-DEFS    = $(DDEFS) $(UDEFS)
-ADEFS   = $(DADEFS) $(UADEFS)
-
-# Libs
-LIBS    = $(DLIBS) $(ULIBS)
-
-MCFLAGS = -mmcu=$(MCU)
-ODFLAGS	= -x --syms
-ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS)
-CPFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS)
-ifeq ($(LINK_GC),yes)
-  LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR)
-else
-  LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR)
-endif
-
-# Generate dependency information
-CPFLAGS += -MD -MP -MF .dep/$(@F).d
-
-#
-# Makefile rules
-#
-all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp MAKE_ALL_RULE_HOOK
-
-MAKE_ALL_RULE_HOOK:
-
-$(CPPOBJS) : %.o : %.cpp
-	@echo
-	$(CPPC) -c $(CPPFLAGS) -I . $(IINCDIR) $< -o $@
-
-$(COBJS) : %.o : %.c
-	@echo
-	$(CC) -c $(CPFLAGS) -I . $(IINCDIR) $< -o $@
-
-$(ASMOBJS) : %.o : %.s
-	@echo
-	$(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@
-
-%elf: $(OBJS)
-	@echo
-	$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
-
-%hex: %elf
-	$(HEX) $< $@
-
-%bin: %elf
-	$(BIN) $< $@
-
-%dmp: %elf
-	$(OD) $(ODFLAGS) $< > $@
-
-clean:
-	-rm -f $(OBJS)
-	-rm -f $(CSRC:.c=.lst) $(CPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst)
-	-rm -f $(PROJECT).elf $(PROJECT).dmp $(PROJECT).map $(PROJECT).hex $(PROJECT).bin
-	-rm -fR .dep
-
-#
-# Include the dependency files, should be the last of the makefile
-#
--include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
-
-# *** EOF ***
diff --git a/os/ports/GCC/PPC/SPC560BCxx/bam.s b/os/ports/GCC/PPC/SPC560BCxx/bam.s
deleted file mode 100644
index f62c854dd..000000000
--- a/os/ports/GCC/PPC/SPC560BCxx/bam.s
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560BCxx/bam.s
- * @brief   SPC560BCxx boot assistant record.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* BAM record.*/
-        .section    .bam, "ax"
-        .long       0x015A0000
-        .long       _reset_address
-
-        .align      2
-        .globl      _reset_address
-        .type       _reset_address, @function
-_reset_address:
-        bl          _coreinit
-        bl          _ivinit
-
-        b           _boot_address
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560BCxx/core.s b/os/ports/GCC/PPC/SPC560BCxx/core.s
deleted file mode 100644
index e4de3d453..000000000
--- a/os/ports/GCC/PPC/SPC560BCxx/core.s
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560BCxx/core.s
- * @brief   e200z0 core configuration.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-/**
- * @name    BUCSR registers definitions
- * @{
- */
-#define BUCSR_BPEN              0x00000001
-#define BUCSR_BALLOC_BFI        0x00000200
-/** @} */
-
-/**
- * @name    BUCSR default settings
- * @{
- */
-#define BUCSR_DEFAULT           (BUCSR_BPEN | BUCSR_BALLOC_BFI)
-/** @} */
-
-/**
- * @name   MSR register definitions
- * @{
- */
-#define MSR_WE                  0x00040000
-#define MSR_CE                  0x00020000
-#define MSR_EE                  0x00008000
-#define MSR_PR                  0x00004000
-#define MSR_ME                  0x00001000
-#define MSR_DE                  0x00000200
-#define MSR_IS                  0x00000020
-#define MSR_DS                  0x00000010
-#define MSR_RI                  0x00000002
-/** @} */
-
-/**
- * @name   MSR default settings
- * @{
- */
-#define MSR_DEFAULT             (MSR_WE | MSR_CE | MSR_ME)
-/** @} */
-
-#if !defined(__DOXYGEN__)
-
-        .section    .coreinit, "ax"
-
-        .align      2
-        .globl      _coreinit
-        .type       _coreinit, @function
-_coreinit:
-        /*
-         * RAM clearing, this device requires a write to all RAM location in
-         * order to initialize the ECC detection hardware, this is going to
-         * slow down the startup but there is no way around.
-         */
-        xor         %r0, %r0, %r0
-        xor         %r1, %r1, %r1
-        xor         %r2, %r2, %r2
-        xor         %r3, %r3, %r3
-        xor         %r4, %r4, %r4
-        xor         %r5, %r5, %r5
-        xor         %r6, %r6, %r6
-        xor         %r7, %r7, %r7
-        xor         %r8, %r8, %r8
-        xor         %r9, %r9, %r9
-        xor         %r10, %r10, %r10
-        xor         %r11, %r11, %r11
-        xor         %r12, %r12, %r12
-        xor         %r13, %r13, %r13
-        xor         %r14, %r14, %r14
-        xor         %r15, %r15, %r15
-        xor         %r16, %r16, %r16
-        xor         %r17, %r17, %r17
-        xor         %r18, %r18, %r18
-        xor         %r19, %r19, %r19
-        xor         %r20, %r20, %r20
-        xor         %r21, %r21, %r21
-        xor         %r22, %r22, %r22
-        xor         %r23, %r23, %r23
-        xor         %r24, %r24, %r24
-        xor         %r25, %r25, %r25
-        xor         %r26, %r26, %r26
-        xor         %r27, %r27, %r27
-        xor         %r28, %r28, %r28
-        xor         %r29, %r29, %r29
-        xor         %r30, %r30, %r30
-        xor         %r31, %r31, %r31
-        lis         %r4, __ram_start__@h
-        ori         %r4, %r4, __ram_start__@l
-        lis         %r5, __ram_end__@h
-        ori         %r5, %r5, __ram_end__@l
-.cleareccloop:
-        cmpl        %cr0, %r4, %r5
-        bge         %cr0, .cleareccend
-        stmw        %r16, 0(%r4)
-        addi        %r4, %r4, 64
-        b           .cleareccloop
-.cleareccend:
-
-        /*
-         * Branch prediction enabled.
-         */
-        li          %r3, BUCSR_DEFAULT
-        mtspr       1013, %r3       /* BUCSR */
-
-        blr
-
-        /*
-         * Exception vectors initialization.
-         */
-        .global     _ivinit
-        .type       _ivinit, @function
-_ivinit:
-        /* MSR initialization.*/
-        lis         %r3, MSR_DEFAULT@h
-        ori         %r3, %r3, MSR_DEFAULT@l
-        mtMSR       %r3
-
-        /* IVPR initialization.*/
-        lis         %r3, __ivpr_base__@h
-        ori         %r3, %r3, __ivpr_base__@l
-        mtIVPR      %r3
-
-        blr
-
-        .section    .ivors, "ax"
-
-        .globl      IVORS
-IVORS:
-IVOR0:  b           IVOR0
-        .align      4
-IVOR1:  b           _IVOR1
-        .align      4
-IVOR2:  b           _IVOR2
-        .align      4
-IVOR3:  b           _IVOR3
-        .align      4
-IVOR4:  b           _IVOR4
-        .align      4
-IVOR5:  b           _IVOR5
-        .align      4
-IVOR6:  b           _IVOR6
-        .align      4
-IVOR7:  b           _IVOR7
-        .align      4
-IVOR8:  b           _IVOR8
-        .align      4
-IVOR9:  b           _IVOR9
-        .align      4
-IVOR10: b           _IVOR10
-        .align      4
-IVOR11: b           _IVOR11
-        .align      4
-IVOR12: b           _IVOR12
-        .align      4
-IVOR13: b           _IVOR13
-        .align      4
-IVOR14: b           _IVOR14
-        .align      4
-IVOR15: b           _IVOR15
-
-        .section    .handlers, "ax"
-
-        /*
-         * Unhandled exceptions handler.
-         */
-        .weak       _IVOR0,  _IVOR1,  _IVOR2,  _IVOR3,  _IVOR4,  _IVOR5
-        .weak       _IVOR6,  _IVOR7,  _IVOR8,  _IVOR9,  _IVOR10, _IVOR11
-        .weak       _IVOR12, _IVOR13, _IVOR14, _IVOR15
-        .weak       _unhandled_exception
-_IVOR0:
-_IVOR1:
-_IVOR2:
-_IVOR3:
-_IVOR5:
-_IVOR6:
-_IVOR7:
-_IVOR8:
-_IVOR9:
-_IVOR11:
-_IVOR12:
-_IVOR13:
-_IVOR14:
-_IVOR15:
-        .type       _unhandled_exception, @function
-_unhandled_exception:
-        b           _unhandled_exception
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B44.ld b/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B44.ld
deleted file mode 100644
index d9f9e82b4..000000000
--- a/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B44.ld
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC560B44 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 384k
-    dataflash : org = 0x00800000, len = 64k
-    ram       : org = 0x40000000, len = 28k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x00000800);
-        KEEP(*(.vectors))
-        /* Note, have to waste the first 4KB because the IVPR register
-           requires an alignment of 4KB and the first 4KB cannot be used,
-           IVOR0 would conflict with the BAM word. Applications could
-           allocate code or data in the first 4KB by using special sections.*/
-        . = ALIGN(0x00001000);
-        __ivpr_base__ = .;
-        KEEP(*(.ivors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B50.ld b/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B50.ld
deleted file mode 100644
index a68cb1ec4..000000000
--- a/os/ports/GCC/PPC/SPC560BCxx/ld/SPC560B50.ld
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC560B50 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 512k
-    dataflash : org = 0x00800000, len = 64k
-    ram       : org = 0x40000000, len = 32k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x00000800);
-        KEEP(*(.vectors))
-        /* Note, have to waste the first 4KB because the IVPR register
-           requires an alignment of 4KB and the first 4KB cannot be used,
-           IVOR0 would conflict with the BAM word. Applications could
-           allocate code or data in the first 4KB by using special sections.*/
-        . = ALIGN(0x00001000);
-        __ivpr_base__ = .;
-        KEEP(*(.ivors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC560BCxx/port.mk b/os/ports/GCC/PPC/SPC560BCxx/port.mk
deleted file mode 100644
index c798e2886..000000000
--- a/os/ports/GCC/PPC/SPC560BCxx/port.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of the ChibiOS/RT SPC560BCxx port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/bam.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/core.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/vectors.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/crt0.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/ld
diff --git a/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h b/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h
deleted file mode 100644
index 5d4d9a37e..000000000
--- a/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560BCxx/ppcparams.h
- * @brief   PowerPC parameters for the SPC560B/Cxx.
- *
- * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters
- * @ingroup PPC_SPECIFIC
- * @details This file contains the PowerPC specific parameters for the
- *          SPC560BCxx platform.
- * @{
- */
-
-#ifndef _PPCPARAMS_H_
-#define _PPCPARAMS_H_
-
-/**
- * @brief   PPC core model.
- */
-#define PPC_VARIANT                 PPC_VARIANT_e200z0
-
-/**
- * @brief   Number of writable bits in IVPR register.
- */
-#define PPC_IVPR_BITS               20
-
-/**
- * @brief   IVORx registers support.
- */
-#define PPC_SUPPORTS_IVORS          FALSE
-
-/**
- * @brief   Book E instruction set support.
- */
-#define PPC_SUPPORTS_BOOKE          FALSE
-
-/**
- * @brief   VLE instruction set support.
- */
-#define PPC_SUPPORTS_VLE            TRUE
-
-/**
- * @brief   Supports VLS Load/Store Multiple Volatile instructions.
- */
-#define PPC_SUPPORTS_VLE_MULTI      TRUE
-
-/**
- * @brief   Supports the decrementer timer.
- */
-#define PPC_SUPPORTS_DECREMENTER    FALSE
-
-#endif /* _PPCPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560BCxx/vectors.h b/os/ports/GCC/PPC/SPC560BCxx/vectors.h
deleted file mode 100644
index 4a54e0f70..000000000
--- a/os/ports/GCC/PPC/SPC560BCxx/vectors.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560BCxx/vectors.h
- * @brief   ISR vector module header.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/*===========================================================================*/
-/* Module constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of ISR vectors available.
- */
-#define VECTORS_NUMBER                      217
-
-/*===========================================================================*/
-/* Module pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-#if !defined(__DOXYGEN__)
-extern uint32_t _vectors[VECTORS_NUMBER];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _unhandled_irq(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !defined(_FROM_ASM_) */
-
-#endif /* _OSAL_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560BCxx/vectors.s b/os/ports/GCC/PPC/SPC560BCxx/vectors.s
deleted file mode 100644
index 1ed6ddde3..000000000
--- a/os/ports/GCC/PPC/SPC560BCxx/vectors.s
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560BCxx/vectors.s
- * @brief   SPC560BCxx vectors table.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* Software vectors table. The vectors are accessed from the IVOR4
-           handler only. In order to declare an interrupt handler just create
-           a function withe the same name of a vector, the symbol will
-           override the weak symbol declared here.*/
-        .section    .vectors, "ax"
-        .align		4
-        .globl      _vectors
-_vectors:
-        .long       vector0,    vector1,    vector2,    vector3
-        .long       vector4,    vector5,    vector6,    vector7
-        .long       vector8,    vector9,    vector10,   vector11
-        .long       vector12,   vector13,   vector14,   vector15
-        .long       vector16,   vector17,   vector18,   vector19
-        .long       vector20,   vector21,   vector22,   vector23
-        .long       vector24,   vector25,   vector26,   vector27
-        .long       vector28,   vector29,   vector30,   vector31
-        .long       vector32,   vector33,   vector34,   vector35
-        .long       vector36,   vector37,   vector38,   vector39
-        .long       vector40,   vector41,   vector42,   vector43
-        .long       vector44,   vector45,   vector46,   vector47
-        .long       vector48,   vector49,   vector50,   vector51
-        .long       vector52,   vector53,   vector54,   vector55
-        .long       vector56,   vector57,   vector58,   vector59
-        .long       vector60,   vector61,   vector62,   vector63
-        .long       vector64,   vector65,   vector66,   vector67
-        .long       vector68,   vector69,   vector70,   vector71
-        .long       vector72,   vector73,   vector74,   vector75
-        .long       vector76,   vector77,   vector78,   vector79
-        .long       vector80,   vector81,   vector82,   vector83
-        .long       vector84,   vector85,   vector86,   vector87
-        .long       vector88,   vector89,   vector90,   vector91
-        .long       vector92,   vector93,   vector94,   vector95
-        .long       vector96,   vector97,   vector98,   vector99
-        .long       vector100,  vector101,  vector102,  vector103
-        .long       vector104,  vector105,  vector106,  vector107
-        .long       vector108,  vector109,  vector110,  vector111
-        .long       vector112,  vector113,  vector114,  vector115
-        .long       vector116,  vector117,  vector118,  vector119
-        .long       vector120,  vector121,  vector122,  vector123
-        .long       vector124,  vector125,  vector126,  vector127
-        .long       vector128,  vector129,  vector130,  vector131
-        .long       vector132,  vector133,  vector134,  vector135
-        .long       vector136,  vector137,  vector138,  vector139
-        .long       vector140,  vector141,  vector142,  vector143
-        .long       vector144,  vector145,  vector146,  vector147
-        .long       vector148,  vector149,  vector150,  vector151
-        .long       vector152,  vector153,  vector154,  vector155
-        .long       vector156,  vector157,  vector158,  vector159
-        .long       vector160,  vector161,  vector162,  vector163
-        .long       vector164,  vector165,  vector166,  vector167
-        .long       vector168,  vector169,  vector170,  vector171
-        .long       vector172,  vector173,  vector174,  vector175
-        .long       vector176,  vector177,  vector178,  vector179
-        .long       vector180,  vector181,  vector182,  vector183
-        .long       vector184,  vector185,  vector186,  vector187
-        .long       vector188,  vector189,  vector190,  vector191
-        .long       vector192,  vector193,  vector194,  vector195
-        .long       vector196,  vector197,  vector198,  vector199
-        .long       vector200,  vector201,  vector202,  vector203
-        .long       vector204,  vector205,  vector206,  vector207
-        .long       vector208,  vector209,  vector210,  vector211
-        .long       vector212,  vector213,  vector214,  vector215
-        .long       vector216
-
-        .text
-        .align      2
-        
-        .weak       vector0,    vector1,    vector2,    vector3
-        .weak       vector4,    vector5,    vector6,    vector7
-        .weak       vector8,    vector9,    vector10,   vector11
-        .weak       vector12,   vector13,   vector14,   vector15
-        .weak       vector16,   vector17,   vector18,   vector19
-        .weak       vector20,   vector21,   vector22,   vector23
-        .weak       vector24,   vector25,   vector26,   vector27
-        .weak       vector28,   vector29,   vector30,   vector31
-        .weak       vector32,   vector33,   vector34,   vector35
-        .weak       vector36,   vector37,   vector38,   vector39
-        .weak       vector40,   vector41,   vector42,   vector43
-        .weak       vector44,   vector45,   vector46,   vector47
-        .weak       vector48,   vector49,   vector50,   vector51
-        .weak       vector52,   vector53,   vector54,   vector55
-        .weak       vector56,   vector57,   vector58,   vector59
-        .weak       vector60,   vector61,   vector62,   vector63
-        .weak       vector64,   vector65,   vector66,   vector67
-        .weak       vector68,   vector69,   vector70,   vector71
-        .weak       vector72,   vector73,   vector74,   vector75
-        .weak       vector76,   vector77,   vector78,   vector79
-        .weak       vector80,   vector81,   vector82,   vector83
-        .weak       vector84,   vector85,   vector86,   vector87
-        .weak       vector88,   vector89,   vector90,   vector91
-        .weak       vector92,   vector93,   vector94,   vector95
-        .weak       vector96,   vector97,   vector98,   vector99
-        .weak       vector100,  vector101,  vector102,  vector103
-        .weak       vector104,  vector105,  vector106,  vector107
-        .weak       vector108,  vector109,  vector110,  vector111
-        .weak       vector112,  vector113,  vector114,  vector115
-        .weak       vector116,  vector117,  vector118,  vector119
-        .weak       vector120,  vector121,  vector122,  vector123
-        .weak       vector124,  vector125,  vector126,  vector127
-        .weak       vector128,  vector129,  vector130,  vector131
-        .weak       vector132,  vector133,  vector134,  vector135
-        .weak       vector136,  vector137,  vector138,  vector139
-        .weak       vector140,  vector141,  vector142,  vector143
-        .weak       vector144,  vector145,  vector146,  vector147
-        .weak       vector148,  vector149,  vector150,  vector151
-        .weak       vector152,  vector153,  vector154,  vector155
-        .weak       vector156,  vector157,  vector158,  vector159
-        .weak       vector160,  vector161,  vector162,  vector163
-        .weak       vector164,  vector165,  vector166,  vector167
-        .weak       vector168,  vector169,  vector170,  vector171
-        .weak       vector172,  vector173,  vector174,  vector175
-        .weak       vector176,  vector177,  vector178,  vector179
-        .weak       vector180,  vector181,  vector182,  vector183
-        .weak       vector184,  vector185,  vector186,  vector187
-        .weak       vector188,  vector189,  vector190,  vector191
-        .weak       vector192,  vector193,  vector194,  vector195
-        .weak       vector196,  vector197,  vector198,  vector199
-        .weak       vector200,  vector201,  vector202,  vector203
-        .weak       vector204,  vector205,  vector206,  vector207
-        .weak       vector208,  vector209,  vector210,  vector211
-        .weak       vector212,  vector213,  vector214,  vector215
-        .weak       vector216
-
-vector0:
-vector1:
-vector2:
-vector3:
-vector4:
-vector5:
-vector6:
-vector7:
-vector8:
-vector9:
-vector10:
-vector11:
-vector12:
-vector13:
-vector14:
-vector15:
-vector16:
-vector17:
-vector18:
-vector19:
-vector20:
-vector21:
-vector22:
-vector23:
-vector24:
-vector25:
-vector26:
-vector27:
-vector28:
-vector29:
-vector30:
-vector31:
-vector32:
-vector33:
-vector34:
-vector35:
-vector36:
-vector37:
-vector38:
-vector39:
-vector40:
-vector41:
-vector42:
-vector43:
-vector44:
-vector45:
-vector46:
-vector47:
-vector48:
-vector49:
-vector50:
-vector51:
-vector52:
-vector53:
-vector54:
-vector55:
-vector56:
-vector57:
-vector58:
-vector59:
-vector60:
-vector61:
-vector62:
-vector63:
-vector64:
-vector65:
-vector66:
-vector67:
-vector68:
-vector69:
-vector70:
-vector71:
-vector72:
-vector73:
-vector74:
-vector75:
-vector76:
-vector77:
-vector78:
-vector79:
-vector80:
-vector81:
-vector82:
-vector83:
-vector84:
-vector85:
-vector86:
-vector87:
-vector88:
-vector89:
-vector90:
-vector91:
-vector92:
-vector93:
-vector94:
-vector95:
-vector96:
-vector97:
-vector98:
-vector99:
-vector100:
-vector101:
-vector102:
-vector103:
-vector104:
-vector105:
-vector106:
-vector107:
-vector108:
-vector109:
-vector110:
-vector111:
-vector112:
-vector113:
-vector114:
-vector115:
-vector116:
-vector117:
-vector118:
-vector119:
-vector120:
-vector121:
-vector122:
-vector123:
-vector124:
-vector125:
-vector126:
-vector127:
-vector128:
-vector129:
-vector130:
-vector131:
-vector132:
-vector133:
-vector134:
-vector135:
-vector136:
-vector137:
-vector138:
-vector139:
-vector140:
-vector141:
-vector142:
-vector143:
-vector144:
-vector145:
-vector146:
-vector147:
-vector148:
-vector149:
-vector150:
-vector151:
-vector152:
-vector153:
-vector154:
-vector155:
-vector156:
-vector157:
-vector158:
-vector159:
-vector160:
-vector161:
-vector162:
-vector163:
-vector164:
-vector165:
-vector166:
-vector167:
-vector168:
-vector169:
-vector170:
-vector171:
-vector172:
-vector173:
-vector174:
-vector175:
-vector176:
-vector177:
-vector178:
-vector179:
-vector180:
-vector181:
-vector182:
-vector183:
-vector184:
-vector185:
-vector186:
-vector187:
-vector188:
-vector189:
-vector190:
-vector191:
-vector192:
-vector193:
-vector194:
-vector195:
-vector196:
-vector197:
-vector198:
-vector199:
-vector200:
-vector201:
-vector202:
-vector203:
-vector204:
-vector205:
-vector206:
-vector207:
-vector208:
-vector209:
-vector210:
-vector211:
-vector212:
-vector213:
-vector214:
-vector215:
-vector216:
-
-        .weak       _unhandled_irq
-        .type       _unhandled_irq, @function
-_unhandled_irq:
-         b          _unhandled_irq
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Bxx/bam.s b/os/ports/GCC/PPC/SPC560Bxx/bam.s
deleted file mode 100644
index a9e6c5e92..000000000
--- a/os/ports/GCC/PPC/SPC560Bxx/bam.s
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Bxx/bam.s
- * @brief   SPC560Bxx boot assistant record.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* BAM record.*/
-        .section    .bam, "ax"
-        .long       0x015A0000
-        .long       _reset_address
-
-        .align      2
-        .globl      _reset_address
-        .type       _reset_address, @function
-_reset_address:
-        bl          _coreinit
-        bl          _ivinit
-
-        b           _boot_address
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Bxx/core.s b/os/ports/GCC/PPC/SPC560Bxx/core.s
deleted file mode 100644
index b4a676e5a..000000000
--- a/os/ports/GCC/PPC/SPC560Bxx/core.s
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Bxx/core.s
- * @brief   e200z0 core configuration.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-/**
- * @name    BUCSR registers definitions
- * @{
- */
-#define BUCSR_BPEN              0x00000001
-#define BUCSR_BALLOC_BFI        0x00000200
-/** @} */
-
-/**
- * @name    BUCSR default settings
- * @{
- */
-#define BUCSR_DEFAULT           (BUCSR_BPEN | BUCSR_BALLOC_BFI)
-/** @} */
-
-/**
- * @name   MSR register definitions
- * @{
- */
-#define MSR_WE                  0x00040000
-#define MSR_CE                  0x00020000
-#define MSR_EE                  0x00008000
-#define MSR_PR                  0x00004000
-#define MSR_ME                  0x00001000
-#define MSR_DE                  0x00000200
-#define MSR_IS                  0x00000020
-#define MSR_DS                  0x00000010
-#define MSR_RI                  0x00000002
-/** @} */
-
-/**
- * @name   MSR default settings
- * @{
- */
-#define MSR_DEFAULT             (MSR_WE | MSR_CE | MSR_ME)
-/** @} */
-
-#if !defined(__DOXYGEN__)
-
-        .section    .coreinit, "ax"
-
-        .align      2
-        .globl      _coreinit
-        .type       _coreinit, @function
-_coreinit:
-        /*
-         * RAM clearing, this device requires a write to all RAM location in
-         * order to initialize the ECC detection hardware, this is going to
-         * slow down the startup but there is no way around.
-         */
-        xor         %r0, %r0, %r0
-        xor         %r1, %r1, %r1
-        xor         %r2, %r2, %r2
-        xor         %r3, %r3, %r3
-        xor         %r4, %r4, %r4
-        xor         %r5, %r5, %r5
-        xor         %r6, %r6, %r6
-        xor         %r7, %r7, %r7
-        xor         %r8, %r8, %r8
-        xor         %r9, %r9, %r9
-        xor         %r10, %r10, %r10
-        xor         %r11, %r11, %r11
-        xor         %r12, %r12, %r12
-        xor         %r13, %r13, %r13
-        xor         %r14, %r14, %r14
-        xor         %r15, %r15, %r15
-        xor         %r16, %r16, %r16
-        xor         %r17, %r17, %r17
-        xor         %r18, %r18, %r18
-        xor         %r19, %r19, %r19
-        xor         %r20, %r20, %r20
-        xor         %r21, %r21, %r21
-        xor         %r22, %r22, %r22
-        xor         %r23, %r23, %r23
-        xor         %r24, %r24, %r24
-        xor         %r25, %r25, %r25
-        xor         %r26, %r26, %r26
-        xor         %r27, %r27, %r27
-        xor         %r28, %r28, %r28
-        xor         %r29, %r29, %r29
-        xor         %r30, %r30, %r30
-        xor         %r31, %r31, %r31
-        lis         %r4, __ram_start__@h
-        ori         %r4, %r4, __ram_start__@l
-        lis         %r5, __ram_end__@h
-        ori         %r5, %r5, __ram_end__@l
-.cleareccloop:
-        cmpl        %cr0, %r4, %r5
-        bge         %cr0, .cleareccend
-        stmw        %r16, 0(%r4)
-        addi        %r4, %r4, 64
-        b           .cleareccloop
-.cleareccend:
-
-        /*
-         * Branch prediction enabled.
-         */
-        li          %r3, BUCSR_DEFAULT
-        mtspr       1013, %r3       /* BUCSR */
-
-        blr
-
-        /*
-         * Exception vectors initialization.
-         */
-        .global     _ivinit
-        .type       _ivinit, @function
-_ivinit:
-        /* MSR initialization.*/
-        lis         %r3, MSR_DEFAULT@h
-        ori         %r3, %r3, MSR_DEFAULT@l
-        mtMSR       %r3
-
-        /* IVPR initialization.*/
-        lis         %r3, __ivpr_base__@h
-        ori         %r3, %r3, __ivpr_base__@l
-        mtIVPR      %r3
-
-        blr
-
-        .section    .ivors, "ax"
-
-        .globl      IVORS
-IVORS:
-IVOR0:  b           IVOR0
-        .align      4
-IVOR1:  b           _IVOR1
-        .align      4
-IVOR2:  b           _IVOR2
-        .align      4
-IVOR3:  b           _IVOR3
-        .align      4
-IVOR4:  b           _IVOR4
-        .align      4
-IVOR5:  b           _IVOR5
-        .align      4
-IVOR6:  b           _IVOR6
-        .align      4
-IVOR7:  b           _IVOR7
-        .align      4
-IVOR8:  b           _IVOR8
-        .align      4
-IVOR9:  b           _IVOR9
-        .align      4
-IVOR10: b           _IVOR10
-        .align      4
-IVOR11: b           _IVOR11
-        .align      4
-IVOR12: b           _IVOR12
-        .align      4
-IVOR13: b           _IVOR13
-        .align      4
-IVOR14: b           _IVOR14
-        .align      4
-IVOR15: b           _IVOR15
-
-        .section    .handlers, "ax"
-
-        /*
-         * Unhandled exceptions handler.
-         */
-        .weak       _IVOR0,  _IVOR1,  _IVOR2,  _IVOR3,  _IVOR4,  _IVOR5
-        .weak       _IVOR6,  _IVOR7,  _IVOR8,  _IVOR9,  _IVOR10, _IVOR11
-        .weak       _IVOR12, _IVOR13, _IVOR14, _IVOR15
-        .weak       _unhandled_exception
-_IVOR0:
-_IVOR1:
-_IVOR2:
-_IVOR3:
-_IVOR5:
-_IVOR6:
-_IVOR7:
-_IVOR8:
-_IVOR9:
-_IVOR11:
-_IVOR12:
-_IVOR13:
-_IVOR14:
-_IVOR15:
-        .type       _unhandled_exception, @function
-_unhandled_exception:
-        b           _unhandled_exception
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Bxx/ld/SPC560B64.ld b/os/ports/GCC/PPC/SPC560Bxx/ld/SPC560B64.ld
deleted file mode 100644
index 1dcb66737..000000000
--- a/os/ports/GCC/PPC/SPC560Bxx/ld/SPC560B64.ld
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC560B64 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 1536k
-    dataflash : org = 0x00800000, len = 64k
-    ram       : org = 0x40000000, len = 96k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x00000800);
-        KEEP(*(.vectors))
-        /* Note, have to waste the first 4KB because the IVPR register
-           requires an alignment of 4KB and the first 4KB cannot be used,
-           IVOR0 would conflict with the BAM word. Applications could
-           allocate code or data in the first 4KB by using special sections.*/
-        . = ALIGN(0x00001000);
-        __ivpr_base__ = .;
-        KEEP(*(.ivors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC560Bxx/port.mk b/os/ports/GCC/PPC/SPC560Bxx/port.mk
deleted file mode 100644
index c009da3bf..000000000
--- a/os/ports/GCC/PPC/SPC560Bxx/port.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of the ChibiOS/RT SPC560Bxx port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Bxx/bam.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560Bxx/core.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560Bxx/vectors.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/crt0.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560Bxx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Bxx/ld
diff --git a/os/ports/GCC/PPC/SPC560Bxx/ppcparams.h b/os/ports/GCC/PPC/SPC560Bxx/ppcparams.h
deleted file mode 100644
index 552099b31..000000000
--- a/os/ports/GCC/PPC/SPC560Bxx/ppcparams.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Bxx/ppcparams.h
- * @brief   PowerPC parameters for the SPC560B/Cxx.
- *
- * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters
- * @ingroup PPC_SPECIFIC
- * @details This file contains the PowerPC specific parameters for the
- *          SPC560BCxx platform.
- * @{
- */
-
-#ifndef _PPCPARAMS_H_
-#define _PPCPARAMS_H_
-
-/**
- * @brief   PPC core model.
- */
-#define PPC_VARIANT                 PPC_VARIANT_e200z0
-
-/**
- * @brief   Number of writable bits in IVPR register.
- */
-#define PPC_IVPR_BITS               20
-
-/**
- * @brief   IVORx registers support.
- */
-#define PPC_SUPPORTS_IVORS          FALSE
-
-/**
- * @brief   Book E instruction set support.
- */
-#define PPC_SUPPORTS_BOOKE          FALSE
-
-/**
- * @brief   VLE instruction set support.
- */
-#define PPC_SUPPORTS_VLE            TRUE
-
-/**
- * @brief   Supports VLS Load/Store Multiple Volatile instructions.
- */
-#define PPC_SUPPORTS_VLE_MULTI      TRUE
-
-/**
- * @brief   Supports the decrementer timer.
- */
-#define PPC_SUPPORTS_DECREMENTER    FALSE
-
-#endif /* _PPCPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Bxx/vectors.h b/os/ports/GCC/PPC/SPC560Bxx/vectors.h
deleted file mode 100644
index 9c240749b..000000000
--- a/os/ports/GCC/PPC/SPC560Bxx/vectors.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Bxx/vectors.h
- * @brief   ISR vector module header.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/*===========================================================================*/
-/* Module constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of ISR vectors available.
- */
-#define VECTORS_NUMBER                      234
-
-/*===========================================================================*/
-/* Module pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-#if !defined(__DOXYGEN__)
-extern uint32_t _vectors[VECTORS_NUMBER];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _unhandled_irq(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !defined(_FROM_ASM_) */
-
-#endif /* _OSAL_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Bxx/vectors.s b/os/ports/GCC/PPC/SPC560Bxx/vectors.s
deleted file mode 100644
index ba82ba799..000000000
--- a/os/ports/GCC/PPC/SPC560Bxx/vectors.s
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Bxx/vectors.s
- * @brief   SPC560Bxx vectors table.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* Software vectors table. The vectors are accessed from the IVOR4
-           handler only. In order to declare an interrupt handler just create
-           a function withe the same name of a vector, the symbol will
-           override the weak symbol declared here.*/
-        .section    .vectors, "ax"
-        .align      4
-        .globl      _vectors
-_vectors:
-        .long       vector0,    vector1,    vector2,    vector3
-        .long       vector4,    vector5,    vector6,    vector7
-        .long       vector8,    vector9,    vector10,   vector11
-        .long       vector12,   vector13,   vector14,   vector15
-        .long       vector16,   vector17,   vector18,   vector19
-        .long       vector20,   vector21,   vector22,   vector23
-        .long       vector24,   vector25,   vector26,   vector27
-        .long       vector28,   vector29,   vector30,   vector31
-        .long       vector32,   vector33,   vector34,   vector35
-        .long       vector36,   vector37,   vector38,   vector39
-        .long       vector40,   vector41,   vector42,   vector43
-        .long       vector44,   vector45,   vector46,   vector47
-        .long       vector48,   vector49,   vector50,   vector51
-        .long       vector52,   vector53,   vector54,   vector55
-        .long       vector56,   vector57,   vector58,   vector59
-        .long       vector60,   vector61,   vector62,   vector63
-        .long       vector64,   vector65,   vector66,   vector67
-        .long       vector68,   vector69,   vector70,   vector71
-        .long       vector72,   vector73,   vector74,   vector75
-        .long       vector76,   vector77,   vector78,   vector79
-        .long       vector80,   vector81,   vector82,   vector83
-        .long       vector84,   vector85,   vector86,   vector87
-        .long       vector88,   vector89,   vector90,   vector91
-        .long       vector92,   vector93,   vector94,   vector95
-        .long       vector96,   vector97,   vector98,   vector99
-        .long       vector100,  vector101,  vector102,  vector103
-        .long       vector104,  vector105,  vector106,  vector107
-        .long       vector108,  vector109,  vector110,  vector111
-        .long       vector112,  vector113,  vector114,  vector115
-        .long       vector116,  vector117,  vector118,  vector119
-        .long       vector120,  vector121,  vector122,  vector123
-        .long       vector124,  vector125,  vector126,  vector127
-        .long       vector128,  vector129,  vector130,  vector131
-        .long       vector132,  vector133,  vector134,  vector135
-        .long       vector136,  vector137,  vector138,  vector139
-        .long       vector140,  vector141,  vector142,  vector143
-        .long       vector144,  vector145,  vector146,  vector147
-        .long       vector148,  vector149,  vector150,  vector151
-        .long       vector152,  vector153,  vector154,  vector155
-        .long       vector156,  vector157,  vector158,  vector159
-        .long       vector160,  vector161,  vector162,  vector163
-        .long       vector164,  vector165,  vector166,  vector167
-        .long       vector168,  vector169,  vector170,  vector171
-        .long       vector172,  vector173,  vector174,  vector175
-        .long       vector176,  vector177,  vector178,  vector179
-        .long       vector180,  vector181,  vector182,  vector183
-        .long       vector184,  vector185,  vector186,  vector187
-        .long       vector188,  vector189,  vector190,  vector191
-        .long       vector192,  vector193,  vector194,  vector195
-        .long       vector196,  vector197,  vector198,  vector199
-        .long       vector200,  vector201,  vector202,  vector203
-        .long       vector204,  vector205,  vector206,  vector207
-        .long       vector208,  vector209,  vector210,  vector211
-        .long       vector212,  vector213,  vector214,  vector215
-        .long       vector216,  vector217,  vector218,  vector219
-        .long       vector220,  vector221,  vector222,  vector223
-        .long       vector224,  vector225,  vector226,  vector227
-        .long       vector228,  vector229,  vector230,  vector231
-        .long       vector232,  vector233
-
-        .text
-        .align      2
-        
-        .weak       vector0,    vector1,    vector2,    vector3
-        .weak       vector4,    vector5,    vector6,    vector7
-        .weak       vector8,    vector9,    vector10,   vector11
-        .weak       vector12,   vector13,   vector14,   vector15
-        .weak       vector16,   vector17,   vector18,   vector19
-        .weak       vector20,   vector21,   vector22,   vector23
-        .weak       vector24,   vector25,   vector26,   vector27
-        .weak       vector28,   vector29,   vector30,   vector31
-        .weak       vector32,   vector33,   vector34,   vector35
-        .weak       vector36,   vector37,   vector38,   vector39
-        .weak       vector40,   vector41,   vector42,   vector43
-        .weak       vector44,   vector45,   vector46,   vector47
-        .weak       vector48,   vector49,   vector50,   vector51
-        .weak       vector52,   vector53,   vector54,   vector55
-        .weak       vector56,   vector57,   vector58,   vector59
-        .weak       vector60,   vector61,   vector62,   vector63
-        .weak       vector64,   vector65,   vector66,   vector67
-        .weak       vector68,   vector69,   vector70,   vector71
-        .weak       vector72,   vector73,   vector74,   vector75
-        .weak       vector76,   vector77,   vector78,   vector79
-        .weak       vector80,   vector81,   vector82,   vector83
-        .weak       vector84,   vector85,   vector86,   vector87
-        .weak       vector88,   vector89,   vector90,   vector91
-        .weak       vector92,   vector93,   vector94,   vector95
-        .weak       vector96,   vector97,   vector98,   vector99
-        .weak       vector100,  vector101,  vector102,  vector103
-        .weak       vector104,  vector105,  vector106,  vector107
-        .weak       vector108,  vector109,  vector110,  vector111
-        .weak       vector112,  vector113,  vector114,  vector115
-        .weak       vector116,  vector117,  vector118,  vector119
-        .weak       vector120,  vector121,  vector122,  vector123
-        .weak       vector124,  vector125,  vector126,  vector127
-        .weak       vector128,  vector129,  vector130,  vector131
-        .weak       vector132,  vector133,  vector134,  vector135
-        .weak       vector136,  vector137,  vector138,  vector139
-        .weak       vector140,  vector141,  vector142,  vector143
-        .weak       vector144,  vector145,  vector146,  vector147
-        .weak       vector148,  vector149,  vector150,  vector151
-        .weak       vector152,  vector153,  vector154,  vector155
-        .weak       vector156,  vector157,  vector158,  vector159
-        .weak       vector160,  vector161,  vector162,  vector163
-        .weak       vector164,  vector165,  vector166,  vector167
-        .weak       vector168,  vector169,  vector170,  vector171
-        .weak       vector172,  vector173,  vector174,  vector175
-        .weak       vector176,  vector177,  vector178,  vector179
-        .weak       vector180,  vector181,  vector182,  vector183
-        .weak       vector184,  vector185,  vector186,  vector187
-        .weak       vector188,  vector189,  vector190,  vector191
-        .weak       vector192,  vector193,  vector194,  vector195
-        .weak       vector196,  vector197,  vector198,  vector199
-        .weak       vector200,  vector201,  vector202,  vector203
-        .weak       vector204,  vector205,  vector206,  vector207
-        .weak       vector208,  vector209,  vector210,  vector211
-        .weak       vector212,  vector213,  vector214,  vector215
-        .weak       vector216,  vector217,  vector218,  vector219
-        .weak       vector220,  vector221,  vector222,  vector223
-        .weak       vector224,  vector225,  vector226,  vector227
-        .weak       vector228,  vector229,  vector230,  vector231
-        .weak       vector232,  vector233
-
-vector0:
-vector1:
-vector2:
-vector3:
-vector4:
-vector5:
-vector6:
-vector7:
-vector8:
-vector9:
-vector10:
-vector11:
-vector12:
-vector13:
-vector14:
-vector15:
-vector16:
-vector17:
-vector18:
-vector19:
-vector20:
-vector21:
-vector22:
-vector23:
-vector24:
-vector25:
-vector26:
-vector27:
-vector28:
-vector29:
-vector30:
-vector31:
-vector32:
-vector33:
-vector34:
-vector35:
-vector36:
-vector37:
-vector38:
-vector39:
-vector40:
-vector41:
-vector42:
-vector43:
-vector44:
-vector45:
-vector46:
-vector47:
-vector48:
-vector49:
-vector50:
-vector51:
-vector52:
-vector53:
-vector54:
-vector55:
-vector56:
-vector57:
-vector58:
-vector59:
-vector60:
-vector61:
-vector62:
-vector63:
-vector64:
-vector65:
-vector66:
-vector67:
-vector68:
-vector69:
-vector70:
-vector71:
-vector72:
-vector73:
-vector74:
-vector75:
-vector76:
-vector77:
-vector78:
-vector79:
-vector80:
-vector81:
-vector82:
-vector83:
-vector84:
-vector85:
-vector86:
-vector87:
-vector88:
-vector89:
-vector90:
-vector91:
-vector92:
-vector93:
-vector94:
-vector95:
-vector96:
-vector97:
-vector98:
-vector99:
-vector100:
-vector101:
-vector102:
-vector103:
-vector104:
-vector105:
-vector106:
-vector107:
-vector108:
-vector109:
-vector110:
-vector111:
-vector112:
-vector113:
-vector114:
-vector115:
-vector116:
-vector117:
-vector118:
-vector119:
-vector120:
-vector121:
-vector122:
-vector123:
-vector124:
-vector125:
-vector126:
-vector127:
-vector128:
-vector129:
-vector130:
-vector131:
-vector132:
-vector133:
-vector134:
-vector135:
-vector136:
-vector137:
-vector138:
-vector139:
-vector140:
-vector141:
-vector142:
-vector143:
-vector144:
-vector145:
-vector146:
-vector147:
-vector148:
-vector149:
-vector150:
-vector151:
-vector152:
-vector153:
-vector154:
-vector155:
-vector156:
-vector157:
-vector158:
-vector159:
-vector160:
-vector161:
-vector162:
-vector163:
-vector164:
-vector165:
-vector166:
-vector167:
-vector168:
-vector169:
-vector170:
-vector171:
-vector172:
-vector173:
-vector174:
-vector175:
-vector176:
-vector177:
-vector178:
-vector179:
-vector180:
-vector181:
-vector182:
-vector183:
-vector184:
-vector185:
-vector186:
-vector187:
-vector188:
-vector189:
-vector190:
-vector191:
-vector192:
-vector193:
-vector194:
-vector195:
-vector196:
-vector197:
-vector198:
-vector199:
-vector200:
-vector201:
-vector202:
-vector203:
-vector204:
-vector205:
-vector206:
-vector207:
-vector208:
-vector209:
-vector210:
-vector211:
-vector212:
-vector213:
-vector214:
-vector215:
-vector216:
-vector217:
-vector218:
-vector219:
-vector220:
-vector221:
-vector222:
-vector223:
-vector224:
-vector225:
-vector226:
-vector227:
-vector228:
-vector229:
-vector230:
-vector231:
-vector232:
-vector233:
-
-        .weak       _unhandled_irq
-        .type       _unhandled_irq, @function
-_unhandled_irq:
-         b          _unhandled_irq
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Dxx/bam.s b/os/ports/GCC/PPC/SPC560Dxx/bam.s
deleted file mode 100644
index 28792c3c3..000000000
--- a/os/ports/GCC/PPC/SPC560Dxx/bam.s
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Dxx/bam.s
- * @brief   SPC560Dxx boot assistant record.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* BAM record.*/
-        .section    .bam, "ax"
-        .long       0x015A0000
-        .long       _reset_address
-
-        .align      2
-        .globl      _reset_address
-        .type       _reset_address, @function
-_reset_address:
-        bl          _coreinit
-        bl          _ivinit
-
-        b           _boot_address
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Dxx/core.s b/os/ports/GCC/PPC/SPC560Dxx/core.s
deleted file mode 100644
index 434f96fa3..000000000
--- a/os/ports/GCC/PPC/SPC560Dxx/core.s
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Dxx/core.s
- * @brief   e200z0 core configuration.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-/**
- * @name    BUCSR registers definitions
- * @{
- */
-#define BUCSR_BPEN              0x00000001
-#define BUCSR_BALLOC_BFI        0x00000200
-/** @} */
-
-/**
- * @name    BUCSR default settings
- * @{
- */
-#define BUCSR_DEFAULT           (BUCSR_BPEN | BUCSR_BALLOC_BFI)
-/** @} */
-
-/**
- * @name   MSR register definitions
- * @{
- */
-#define MSR_WE                  0x00040000
-#define MSR_CE                  0x00020000
-#define MSR_EE                  0x00008000
-#define MSR_PR                  0x00004000
-#define MSR_ME                  0x00001000
-#define MSR_DE                  0x00000200
-#define MSR_IS                  0x00000020
-#define MSR_DS                  0x00000010
-#define MSR_RI                  0x00000002
-/** @} */
-
-/**
- * @name   MSR default settings
- * @{
- */
-#define MSR_DEFAULT             (MSR_WE | MSR_CE | MSR_ME)
-/** @} */
-
-#if !defined(__DOXYGEN__)
-
-        .section    .coreinit, "ax"
-
-        .align      2
-        .globl      _coreinit
-        .type       _coreinit, @function
-_coreinit:
-        /*
-         * RAM clearing, this device requires a write to all RAM location in
-         * order to initialize the ECC detection hardware, this is going to
-         * slow down the startup but there is no way around.
-         */
-        xor         %r0, %r0, %r0
-        xor         %r1, %r1, %r1
-        xor         %r2, %r2, %r2
-        xor         %r3, %r3, %r3
-        xor         %r4, %r4, %r4
-        xor         %r5, %r5, %r5
-        xor         %r6, %r6, %r6
-        xor         %r7, %r7, %r7
-        xor         %r8, %r8, %r8
-        xor         %r9, %r9, %r9
-        xor         %r10, %r10, %r10
-        xor         %r11, %r11, %r11
-        xor         %r12, %r12, %r12
-        xor         %r13, %r13, %r13
-        xor         %r14, %r14, %r14
-        xor         %r15, %r15, %r15
-        xor         %r16, %r16, %r16
-        xor         %r17, %r17, %r17
-        xor         %r18, %r18, %r18
-        xor         %r19, %r19, %r19
-        xor         %r20, %r20, %r20
-        xor         %r21, %r21, %r21
-        xor         %r22, %r22, %r22
-        xor         %r23, %r23, %r23
-        xor         %r24, %r24, %r24
-        xor         %r25, %r25, %r25
-        xor         %r26, %r26, %r26
-        xor         %r27, %r27, %r27
-        xor         %r28, %r28, %r28
-        xor         %r29, %r29, %r29
-        xor         %r30, %r30, %r30
-        xor         %r31, %r31, %r31
-        lis         %r4, __ram_start__@h
-        ori         %r4, %r4, __ram_start__@l
-        lis         %r5, __ram_end__@h
-        ori         %r5, %r5, __ram_end__@l
-.cleareccloop:
-        cmpl        %cr0, %r4, %r5
-        bge         %cr0, .cleareccend
-        stmw        %r16, 0(%r4)
-        addi        %r4, %r4, 64
-        b           .cleareccloop
-.cleareccend:
-
-        /*
-         * Branch prediction enabled.
-         */
-        li          %r3, BUCSR_DEFAULT
-        mtspr       1013, %r3       /* BUCSR */
-
-        blr
-
-        /*
-         * Exception vectors initialization.
-         */
-        .global     _ivinit
-        .type       _ivinit, @function
-_ivinit:
-        /* MSR initialization.*/
-        lis         %r3, MSR_DEFAULT@h
-        ori         %r3, %r3, MSR_DEFAULT@l
-        mtMSR       %r3
-
-        /* IVPR initialization.*/
-        lis         %r3, __ivpr_base__@h
-        ori         %r3, %r3, __ivpr_base__@l
-        mtIVPR      %r3
-
-        blr
-
-        .section    .ivors, "ax"
-
-        .globl      IVORS
-IVORS:
-IVOR0:  b           IVOR0
-        .align      4
-IVOR1:  b           _IVOR1
-        .align      4
-IVOR2:  b           _IVOR2
-        .align      4
-IVOR3:  b           _IVOR3
-        .align      4
-IVOR4:  b           _IVOR4
-        .align      4
-IVOR5:  b           _IVOR5
-        .align      4
-IVOR6:  b           _IVOR6
-        .align      4
-IVOR7:  b           _IVOR7
-        .align      4
-IVOR8:  b           _IVOR8
-        .align      4
-IVOR9:  b           _IVOR9
-        .align      4
-IVOR10: b           _IVOR10
-        .align      4
-IVOR11: b           _IVOR11
-        .align      4
-IVOR12: b           _IVOR12
-        .align      4
-IVOR13: b           _IVOR13
-        .align      4
-IVOR14: b           _IVOR14
-        .align      4
-IVOR15: b           _IVOR15
-
-        .section    .handlers, "ax"
-
-        /*
-         * Unhandled exceptions handler.
-         */
-        .weak       _IVOR0,  _IVOR1,  _IVOR2,  _IVOR3,  _IVOR4,  _IVOR5
-        .weak       _IVOR6,  _IVOR7,  _IVOR8,  _IVOR9,  _IVOR10, _IVOR11
-        .weak       _IVOR12, _IVOR13, _IVOR14, _IVOR15
-        .weak       _unhandled_exception
-_IVOR0:
-_IVOR1:
-_IVOR2:
-_IVOR3:
-_IVOR5:
-_IVOR6:
-_IVOR7:
-_IVOR8:
-_IVOR9:
-_IVOR11:
-_IVOR12:
-_IVOR13:
-_IVOR14:
-_IVOR15:
-        .type       _unhandled_exception, @function
-_unhandled_exception:
-        b           _unhandled_exception
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D30.ld b/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D30.ld
deleted file mode 100644
index 8689f134e..000000000
--- a/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D30.ld
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC560D30 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 128k
-    dataflash : org = 0x00800000, len = 64k
-    ram       : org = 0x40000000, len = 12k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x00000800);
-        KEEP(*(.vectors))
-        /* Note, have to waste the first 4KB because the IVPR register
-           requires an alignment of 4KB and the first 4KB cannot be used,
-           IVOR0 would conflict with the BAM word. Applications could
-           allocate code or data in the first 4KB by using special sections.*/
-        . = ALIGN(0x00001000);
-        __ivpr_base__ = .;
-        KEEP(*(.ivors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D40.ld b/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D40.ld
deleted file mode 100644
index 6f8e23516..000000000
--- a/os/ports/GCC/PPC/SPC560Dxx/ld/SPC560D40.ld
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC560D40 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 256k
-    dataflash : org = 0x00800000, len = 64k
-    ram       : org = 0x40000000, len = 16k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x00000800);
-        KEEP(*(.vectors))
-        /* Note, have to waste the first 4KB because the IVPR register
-           requires an alignment of 4KB and the first 4KB cannot be used,
-           IVOR0 would conflict with the BAM word. Applications could
-           allocate code or data in the first 4KB by using special sections.*/
-        . = ALIGN(0x00001000);
-        __ivpr_base__ = .;
-        KEEP(*(.ivors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC560Dxx/port.mk b/os/ports/GCC/PPC/SPC560Dxx/port.mk
deleted file mode 100644
index e0756b8c2..000000000
--- a/os/ports/GCC/PPC/SPC560Dxx/port.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of the ChibiOS/RT SPC560Dxx port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx/bam.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx/core.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx/vectors.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/crt0.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Dxx/ld
diff --git a/os/ports/GCC/PPC/SPC560Dxx/ppcparams.h b/os/ports/GCC/PPC/SPC560Dxx/ppcparams.h
deleted file mode 100644
index 965db510d..000000000
--- a/os/ports/GCC/PPC/SPC560Dxx/ppcparams.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Dxx/ppcparams.h
- * @brief   PowerPC parameters for the SPC560B/Cxx.
- *
- * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters
- * @ingroup PPC_SPECIFIC
- * @details This file contains the PowerPC specific parameters for the
- *          SPC560BCxx platform.
- * @{
- */
-
-#ifndef _PPCPARAMS_H_
-#define _PPCPARAMS_H_
-
-/**
- * @brief   PPC core model.
- */
-#define PPC_VARIANT                 PPC_VARIANT_e200z0
-
-/**
- * @brief   Number of writable bits in IVPR register.
- */
-#define PPC_IVPR_BITS               20
-
-/**
- * @brief   IVORx registers support.
- */
-#define PPC_SUPPORTS_IVORS          FALSE
-
-/**
- * @brief   Book E instruction set support.
- */
-#define PPC_SUPPORTS_BOOKE          FALSE
-
-/**
- * @brief   VLE instruction set support.
- */
-#define PPC_SUPPORTS_VLE            TRUE
-
-/**
- * @brief   Supports VLS Load/Store Multiple Volatile instructions.
- */
-#define PPC_SUPPORTS_VLE_MULTI      TRUE
-
-/**
- * @brief   Supports the decrementer timer.
- */
-#define PPC_SUPPORTS_DECREMENTER    FALSE
-
-#endif /* _PPCPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Dxx/vectors.h b/os/ports/GCC/PPC/SPC560Dxx/vectors.h
deleted file mode 100644
index 4cc1b47ce..000000000
--- a/os/ports/GCC/PPC/SPC560Dxx/vectors.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Dxx/vectors.h
- * @brief   ISR vector module header.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/*===========================================================================*/
-/* Module constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of ISR vectors available.
- */
-#define VECTORS_NUMBER                      155
-
-/*===========================================================================*/
-/* Module pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-#if !defined(__DOXYGEN__)
-extern uint32_t _vectors[VECTORS_NUMBER];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _unhandled_irq(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !defined(_FROM_ASM_) */
-
-#endif /* _OSAL_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Dxx/vectors.s b/os/ports/GCC/PPC/SPC560Dxx/vectors.s
deleted file mode 100644
index 2536e51ce..000000000
--- a/os/ports/GCC/PPC/SPC560Dxx/vectors.s
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Dxx/vectors.s
- * @brief   SPC560Dxx vectors table.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* Software vectors table. The vectors are accessed from the IVOR4
-           handler only. In order to declare an interrupt handler just create
-           a function withe the same name of a vector, the symbol will
-           override the weak symbol declared here.*/
-        .section    .vectors, "ax"
-        .align		4
-        .globl      _vectors
-_vectors:
-        .long       vector0,    vector1,    vector2,    vector3
-        .long       vector4,    vector5,    vector6,    vector7
-        .long       vector8,    vector9,    vector10,   vector11
-        .long       vector12,   vector13,   vector14,   vector15
-        .long       vector16,   vector17,   vector18,   vector19
-        .long       vector20,   vector21,   vector22,   vector23
-        .long       vector24,   vector25,   vector26,   vector27
-        .long       vector28,   vector29,   vector30,   vector31
-        .long       vector32,   vector33,   vector34,   vector35
-        .long       vector36,   vector37,   vector38,   vector39
-        .long       vector40,   vector41,   vector42,   vector43
-        .long       vector44,   vector45,   vector46,   vector47
-        .long       vector48,   vector49,   vector50,   vector51
-        .long       vector52,   vector53,   vector54,   vector55
-        .long       vector56,   vector57,   vector58,   vector59
-        .long       vector60,   vector61,   vector62,   vector63
-        .long       vector64,   vector65,   vector66,   vector67
-        .long       vector68,   vector69,   vector70,   vector71
-        .long       vector72,   vector73,   vector74,   vector75
-        .long       vector76,   vector77,   vector78,   vector79
-        .long       vector80,   vector81,   vector82,   vector83
-        .long       vector84,   vector85,   vector86,   vector87
-        .long       vector88,   vector89,   vector90,   vector91
-        .long       vector92,   vector93,   vector94,   vector95
-        .long       vector96,   vector97,   vector98,   vector99
-        .long       vector100,  vector101,  vector102,  vector103
-        .long       vector104,  vector105,  vector106,  vector107
-        .long       vector108,  vector109,  vector110,  vector111
-        .long       vector112,  vector113,  vector114,  vector115
-        .long       vector116,  vector117,  vector118,  vector119
-        .long       vector120,  vector121,  vector122,  vector123
-        .long       vector124,  vector125,  vector126,  vector127
-        .long       vector128,  vector129,  vector130,  vector131
-        .long       vector132,  vector133,  vector134,  vector135
-        .long       vector136,  vector137,  vector138,  vector139
-        .long       vector140,  vector141,  vector142,  vector143
-        .long       vector144,  vector145,  vector146,  vector147
-        .long       vector148,  vector149,  vector150,  vector151
-        .long       vector152,  vector153,  vector154
-
-        .text
-        .align      2
-        
-        .weak       vector0,    vector1,    vector2,    vector3
-        .weak       vector4,    vector5,    vector6,    vector7
-        .weak       vector8,    vector9,    vector10,   vector11
-        .weak       vector12,   vector13,   vector14,   vector15
-        .weak       vector16,   vector17,   vector18,   vector19
-        .weak       vector20,   vector21,   vector22,   vector23
-        .weak       vector24,   vector25,   vector26,   vector27
-        .weak       vector28,   vector29,   vector30,   vector31
-        .weak       vector32,   vector33,   vector34,   vector35
-        .weak       vector36,   vector37,   vector38,   vector39
-        .weak       vector40,   vector41,   vector42,   vector43
-        .weak       vector44,   vector45,   vector46,   vector47
-        .weak       vector48,   vector49,   vector50,   vector51
-        .weak       vector52,   vector53,   vector54,   vector55
-        .weak       vector56,   vector57,   vector58,   vector59
-        .weak       vector60,   vector61,   vector62,   vector63
-        .weak       vector64,   vector65,   vector66,   vector67
-        .weak       vector68,   vector69,   vector70,   vector71
-        .weak       vector72,   vector73,   vector74,   vector75
-        .weak       vector76,   vector77,   vector78,   vector79
-        .weak       vector80,   vector81,   vector82,   vector83
-        .weak       vector84,   vector85,   vector86,   vector87
-        .weak       vector88,   vector89,   vector90,   vector91
-        .weak       vector92,   vector93,   vector94,   vector95
-        .weak       vector96,   vector97,   vector98,   vector99
-        .weak       vector100,  vector101,  vector102,  vector103
-        .weak       vector104,  vector105,  vector106,  vector107
-        .weak       vector108,  vector109,  vector110,  vector111
-        .weak       vector112,  vector113,  vector114,  vector115
-        .weak       vector116,  vector117,  vector118,  vector119
-        .weak       vector120,  vector121,  vector122,  vector123
-        .weak       vector124,  vector125,  vector126,  vector127
-        .weak       vector128,  vector129,  vector130,  vector131
-        .weak       vector132,  vector133,  vector134,  vector135
-        .weak       vector136,  vector137,  vector138,  vector139
-        .weak       vector140,  vector141,  vector142,  vector143
-        .weak       vector144,  vector145,  vector146,  vector147
-        .weak       vector148,  vector149,  vector150,  vector151
-        .weak       vector152,  vector153,  vector154
-
-vector0:
-vector1:
-vector2:
-vector3:
-vector4:
-vector5:
-vector6:
-vector7:
-vector8:
-vector9:
-vector10:
-vector11:
-vector12:
-vector13:
-vector14:
-vector15:
-vector16:
-vector17:
-vector18:
-vector19:
-vector20:
-vector21:
-vector22:
-vector23:
-vector24:
-vector25:
-vector26:
-vector27:
-vector28:
-vector29:
-vector30:
-vector31:
-vector32:
-vector33:
-vector34:
-vector35:
-vector36:
-vector37:
-vector38:
-vector39:
-vector40:
-vector41:
-vector42:
-vector43:
-vector44:
-vector45:
-vector46:
-vector47:
-vector48:
-vector49:
-vector50:
-vector51:
-vector52:
-vector53:
-vector54:
-vector55:
-vector56:
-vector57:
-vector58:
-vector59:
-vector60:
-vector61:
-vector62:
-vector63:
-vector64:
-vector65:
-vector66:
-vector67:
-vector68:
-vector69:
-vector70:
-vector71:
-vector72:
-vector73:
-vector74:
-vector75:
-vector76:
-vector77:
-vector78:
-vector79:
-vector80:
-vector81:
-vector82:
-vector83:
-vector84:
-vector85:
-vector86:
-vector87:
-vector88:
-vector89:
-vector90:
-vector91:
-vector92:
-vector93:
-vector94:
-vector95:
-vector96:
-vector97:
-vector98:
-vector99:
-vector100:
-vector101:
-vector102:
-vector103:
-vector104:
-vector105:
-vector106:
-vector107:
-vector108:
-vector109:
-vector110:
-vector111:
-vector112:
-vector113:
-vector114:
-vector115:
-vector116:
-vector117:
-vector118:
-vector119:
-vector120:
-vector121:
-vector122:
-vector123:
-vector124:
-vector125:
-vector126:
-vector127:
-vector128:
-vector129:
-vector130:
-vector131:
-vector132:
-vector133:
-vector134:
-vector135:
-vector136:
-vector137:
-vector138:
-vector139:
-vector140:
-vector141:
-vector142:
-vector143:
-vector144:
-vector145:
-vector146:
-vector147:
-vector148:
-vector149:
-vector150:
-vector151:
-vector152:
-vector153:
-vector154:
-
-        .weak       _unhandled_irq
-        .type       _unhandled_irq, @function
-_unhandled_irq:
-         b          _unhandled_irq
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Pxx/bam.s b/os/ports/GCC/PPC/SPC560Pxx/bam.s
deleted file mode 100644
index d1feed8d3..000000000
--- a/os/ports/GCC/PPC/SPC560Pxx/bam.s
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Pxx/bam.s
- * @brief   SPC560Pxx boot assistant record.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* BAM record.*/
-        .section    .bam, "ax"
-        .long       0x015A0000
-        .long       _reset_address
-
-        .align      2
-        .globl      _reset_address
-        .type       _reset_address, @function
-_reset_address:
-        bl          _coreinit
-        bl          _ivinit
-
-        b           _boot_address
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Pxx/core.s b/os/ports/GCC/PPC/SPC560Pxx/core.s
deleted file mode 100644
index 43d145ddd..000000000
--- a/os/ports/GCC/PPC/SPC560Pxx/core.s
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Pxx/core.s
- * @brief   e200z0 core configuration.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-/**
- * @name    BUCSR registers definitions
- * @{
- */
-#define BUCSR_BPEN              0x00000001
-#define BUCSR_BALLOC_BFI        0x00000200
-/** @} */
-
-/**
- * @name    BUCSR default settings
- * @{
- */
-#define BUCSR_DEFAULT           (BUCSR_BPEN | BUCSR_BALLOC_BFI)
-/** @} */
-
-/**
- * @name   MSR register definitions
- * @{
- */
-#define MSR_WE                  0x00040000
-#define MSR_CE                  0x00020000
-#define MSR_EE                  0x00008000
-#define MSR_PR                  0x00004000
-#define MSR_ME                  0x00001000
-#define MSR_DE                  0x00000200
-#define MSR_IS                  0x00000020
-#define MSR_DS                  0x00000010
-#define MSR_RI                  0x00000002
-/** @} */
-
-/**
- * @name   MSR default settings
- * @{
- */
-#define MSR_DEFAULT             (MSR_WE | MSR_CE | MSR_ME)
-/** @} */
-
-#if !defined(__DOXYGEN__)
-
-        .section    .coreinit, "ax"
-
-        .align      2
-        .globl      _coreinit
-        .type       _coreinit, @function
-_coreinit:
-        /*
-         * RAM clearing, this device requires a write to all RAM location in
-         * order to initialize the ECC detection hardware, this is going to
-         * slow down the startup but there is no way around.
-         */
-        xor         %r0, %r0, %r0
-        xor         %r1, %r1, %r1
-        xor         %r2, %r2, %r2
-        xor         %r3, %r3, %r3
-        xor         %r4, %r4, %r4
-        xor         %r5, %r5, %r5
-        xor         %r6, %r6, %r6
-        xor         %r7, %r7, %r7
-        xor         %r8, %r8, %r8
-        xor         %r9, %r9, %r9
-        xor         %r10, %r10, %r10
-        xor         %r11, %r11, %r11
-        xor         %r12, %r12, %r12
-        xor         %r13, %r13, %r13
-        xor         %r14, %r14, %r14
-        xor         %r15, %r15, %r15
-        xor         %r16, %r16, %r16
-        xor         %r17, %r17, %r17
-        xor         %r18, %r18, %r18
-        xor         %r19, %r19, %r19
-        xor         %r20, %r20, %r20
-        xor         %r21, %r21, %r21
-        xor         %r22, %r22, %r22
-        xor         %r23, %r23, %r23
-        xor         %r24, %r24, %r24
-        xor         %r25, %r25, %r25
-        xor         %r26, %r26, %r26
-        xor         %r27, %r27, %r27
-        xor         %r28, %r28, %r28
-        xor         %r29, %r29, %r29
-        xor         %r30, %r30, %r30
-        xor         %r31, %r31, %r31
-        lis         %r4, __ram_start__@h
-        ori         %r4, %r4, __ram_start__@l
-        lis         %r5, __ram_end__@h
-        ori         %r5, %r5, __ram_end__@l
-.cleareccloop:
-        cmpl        %cr0, %r4, %r5
-        bge         %cr0, .cleareccend
-        stmw        %r16, 0(%r4)
-        addi        %r4, %r4, 64
-        b           .cleareccloop
-.cleareccend:
-
-        /*
-         * Branch prediction enabled.
-         */
-        li          %r3, BUCSR_DEFAULT
-        mtspr       1013, %r3       /* BUCSR */
-
-        blr
-
-        /*
-         * Exception vectors initialization.
-         */
-        .global     _ivinit
-        .type       _ivinit, @function
-_ivinit:
-        /* MSR initialization.*/
-        lis         %r3, MSR_DEFAULT@h
-        ori         %r3, %r3, MSR_DEFAULT@l
-        mtMSR       %r3
-
-        /* IVPR initialization.*/
-        lis         %r3, __ivpr_base__@h
-        ori         %r3, %r3, __ivpr_base__@l
-        mtIVPR      %r3
-
-        blr
-
-        .section    .ivors, "ax"
-
-        .globl      IVORS
-IVORS:
-IVOR0:  b           IVOR0
-        .align      4
-IVOR1:  b           _IVOR1
-        .align      4
-IVOR2:  b           _IVOR2
-        .align      4
-IVOR3:  b           _IVOR3
-        .align      4
-IVOR4:  b           _IVOR4
-        .align      4
-IVOR5:  b           _IVOR5
-        .align      4
-IVOR6:  b           _IVOR6
-        .align      4
-IVOR7:  b           _IVOR7
-        .align      4
-IVOR8:  b           _IVOR8
-        .align      4
-IVOR9:  b           _IVOR9
-        .align      4
-IVOR10: b           _IVOR10
-        .align      4
-IVOR11: b           _IVOR11
-        .align      4
-IVOR12: b           _IVOR12
-        .align      4
-IVOR13: b           _IVOR13
-        .align      4
-IVOR14: b           _IVOR14
-        .align      4
-IVOR15: b           _IVOR15
-
-        .section    .handlers, "ax"
-
-        /*
-         * Unhandled exceptions handler.
-         */
-        .weak       _IVOR0,  _IVOR1,  _IVOR2,  _IVOR3,  _IVOR4,  _IVOR5
-        .weak       _IVOR6,  _IVOR7,  _IVOR8,  _IVOR9,  _IVOR10, _IVOR11
-        .weak       _IVOR12, _IVOR13, _IVOR14, _IVOR15
-        .weak       _unhandled_exception
-_IVOR0:
-_IVOR1:
-_IVOR2:
-_IVOR3:
-_IVOR5:
-_IVOR6:
-_IVOR7:
-_IVOR8:
-_IVOR9:
-_IVOR11:
-_IVOR12:
-_IVOR13:
-_IVOR14:
-_IVOR15:
-        .type       _unhandled_exception, @function
-_unhandled_exception:
-        b           _unhandled_exception
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P44.ld b/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P44.ld
deleted file mode 100644
index 5365b725e..000000000
--- a/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P44.ld
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC560P44 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 384k
-    dataflash : org = 0x00800000, len = 64k
-    ram       : org = 0x40000000, len = 36k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x00000800);
-        KEEP(*(.vectors))
-        /* Note, have to waste the first 64KB because the IVPR register
-           requires an alignment of 64KB and the first 64KB cannot be used,
-           IVOR0 would conflict with the BAM word. Applications could
-           allocate code or data in the first 64KB by using special sections.*/
-        . = ALIGN(0x00010000);
-        __ivpr_base__ = .;
-        KEEP(*(.ivors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P50.ld b/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P50.ld
deleted file mode 100644
index c47e70e06..000000000
--- a/os/ports/GCC/PPC/SPC560Pxx/ld/SPC560P50.ld
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC560P44 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 512k
-    dataflash : org = 0x00800000, len = 64k
-    ram       : org = 0x40000000, len = 40k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x00000800);
-        KEEP(*(.vectors))
-        /* Note, have to waste the first 64KB because the IVPR register
-           requires an alignment of 64KB and the first 64KB cannot be used,
-           IVOR0 would conflict with the BAM word. Applications could
-           allocate code or data in the first 64KB by using special sections.*/
-        . = ALIGN(0x00010000);
-        __ivpr_base__ = .;
-        KEEP(*(.ivors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC560Pxx/port.mk b/os/ports/GCC/PPC/SPC560Pxx/port.mk
deleted file mode 100644
index 112728112..000000000
--- a/os/ports/GCC/PPC/SPC560Pxx/port.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of the ChibiOS/RT SPC560Pxx port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx/bam.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx/core.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx/vectors.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/crt0.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/PPC/SPC560Pxx/ld
diff --git a/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h b/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h
deleted file mode 100644
index febb90017..000000000
--- a/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Pxx/ppcparams.h
- * @brief   PowerPC parameters for the SPC560Pxx.
- *
- * @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters
- * @ingroup PPC_SPECIFIC
- * @details This file contains the PowerPC specific parameters for the
- *          SPC560Pxx platform.
- * @{
- */
-
-#ifndef _PPCPARAMS_H_
-#define _PPCPARAMS_H_
-
-/**
- * @brief   PPC core model.
- */
-#define PPC_VARIANT                 PPC_VARIANT_e200z0
-
-/**
- * @brief   Number of writable bits in IVPR register.
- */
-#define PPC_IVPR_BITS               16
-
-/**
- * @brief   IVORx registers support.
- */
-#define PPC_SUPPORTS_IVORS          FALSE
-
-/**
- * @brief   Book E instruction set support.
- */
-#define PPC_SUPPORTS_BOOKE          FALSE
-
-/**
- * @brief   VLE instruction set support.
- */
-#define PPC_SUPPORTS_VLE            TRUE
-
-/**
- * @brief   Supports VLS Load/Store Multiple Volatile instructions.
- */
-#define PPC_SUPPORTS_VLE_MULTI      TRUE
-
-/**
- * @brief   Supports the decrementer timer.
- */
-#define PPC_SUPPORTS_DECREMENTER    FALSE
-
-#endif /* _PPCPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Pxx/vectors.h b/os/ports/GCC/PPC/SPC560Pxx/vectors.h
deleted file mode 100644
index fc2f6e47c..000000000
--- a/os/ports/GCC/PPC/SPC560Pxx/vectors.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Pxx/vectors.h
- * @brief   ISR vector module header.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/*===========================================================================*/
-/* Module constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of ISR vectors available.
- */
-#define VECTORS_NUMBER                      261
-
-/*===========================================================================*/
-/* Module pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-#if !defined(__DOXYGEN__)
-extern uint32_t _vectors[VECTORS_NUMBER];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _unhandled_irq(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !defined(_FROM_ASM_) */
-
-#endif /* _OSAL_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC560Pxx/vectors.s b/os/ports/GCC/PPC/SPC560Pxx/vectors.s
deleted file mode 100644
index 8fcbb27d9..000000000
--- a/os/ports/GCC/PPC/SPC560Pxx/vectors.s
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC560Pxx/vectors.s
- * @brief   SPC560Pxx vectors table.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* Software vectors table. The vectors are accessed from the IVOR4
-           handler only. In order to declare an interrupt handler just create
-           a function withe the same name of a vector, the symbol will
-           override the weak symbol declared here.*/
-        .section    .vectors, "ax"
-        .align		4
-        .globl      _vectors
-_vectors:
-        .long       vector0,    vector1,    vector2,    vector3
-        .long       vector4,    vector5,    vector6,    vector7
-        .long       vector8,    vector9,    vector10,   vector11
-        .long       vector12,   vector13,   vector14,   vector15
-        .long       vector16,   vector17,   vector18,   vector19
-        .long       vector20,   vector21,   vector22,   vector23
-        .long       vector24,   vector25,   vector26,   vector27
-        .long       vector28,   vector29,   vector30,   vector31
-        .long       vector32,   vector33,   vector34,   vector35
-        .long       vector36,   vector37,   vector38,   vector39
-        .long       vector40,   vector41,   vector42,   vector43
-        .long       vector44,   vector45,   vector46,   vector47
-        .long       vector48,   vector49,   vector50,   vector51
-        .long       vector52,   vector53,   vector54,   vector55
-        .long       vector56,   vector57,   vector58,   vector59
-        .long       vector60,   vector61,   vector62,   vector63
-        .long       vector64,   vector65,   vector66,   vector67
-        .long       vector68,   vector69,   vector70,   vector71
-        .long       vector72,   vector73,   vector74,   vector75
-        .long       vector76,   vector77,   vector78,   vector79
-        .long       vector80,   vector81,   vector82,   vector83
-        .long       vector84,   vector85,   vector86,   vector87
-        .long       vector88,   vector89,   vector90,   vector91
-        .long       vector92,   vector93,   vector94,   vector95
-        .long       vector96,   vector97,   vector98,   vector99
-        .long       vector100,  vector101,  vector102,  vector103
-        .long       vector104,  vector105,  vector106,  vector107
-        .long       vector108,  vector109,  vector110,  vector111
-        .long       vector112,  vector113,  vector114,  vector115
-        .long       vector116,  vector117,  vector118,  vector119
-        .long       vector120,  vector121,  vector122,  vector123
-        .long       vector124,  vector125,  vector126,  vector127
-        .long       vector128,  vector129,  vector130,  vector131
-        .long       vector132,  vector133,  vector134,  vector135
-        .long       vector136,  vector137,  vector138,  vector139
-        .long       vector140,  vector141,  vector142,  vector143
-        .long       vector144,  vector145,  vector146,  vector147
-        .long       vector148,  vector149,  vector150,  vector151
-        .long       vector152,  vector153,  vector154,  vector155
-        .long       vector156,  vector157,  vector158,  vector159
-        .long       vector160,  vector161,  vector162,  vector163
-        .long       vector164,  vector165,  vector166,  vector167
-        .long       vector168,  vector169,  vector170,  vector171
-        .long       vector172,  vector173,  vector174,  vector175
-        .long       vector176,  vector177,  vector178,  vector179
-        .long       vector180,  vector181,  vector182,  vector183
-        .long       vector184,  vector185,  vector186,  vector187
-        .long       vector188,  vector189,  vector190,  vector191
-        .long       vector192,  vector193,  vector194,  vector195
-        .long       vector196,  vector197,  vector198,  vector199
-        .long       vector200,  vector201,  vector202,  vector203
-        .long       vector204,  vector205,  vector206,  vector207
-        .long       vector208,  vector209,  vector210,  vector211
-        .long       vector212,  vector213,  vector214,  vector215
-        .long       vector216,  vector217,  vector218,  vector219
-        .long       vector220,  vector221,  vector222,  vector223
-        .long       vector224,  vector225,  vector226,  vector227
-        .long       vector228,  vector229,  vector230,  vector231
-        .long       vector232,  vector233,  vector234,  vector235
-        .long       vector236,  vector237,  vector238,  vector239
-        .long       vector240,  vector241,  vector242,  vector243
-        .long       vector244,  vector245,  vector246,  vector247
-        .long       vector248,  vector249,  vector250,  vector251
-        .long       vector252,  vector253,  vector254,  vector255
-        .long       vector256,  vector257,  vector258,  vector259
-        .long       vector260
-
-        .text
-        .align      2
-        
-        .weak       vector0,    vector1,    vector2,    vector3
-        .weak       vector4,    vector5,    vector6,    vector7
-        .weak       vector8,    vector9,    vector10,   vector11
-        .weak       vector12,   vector13,   vector14,   vector15
-        .weak       vector16,   vector17,   vector18,   vector19
-        .weak       vector20,   vector21,   vector22,   vector23
-        .weak       vector24,   vector25,   vector26,   vector27
-        .weak       vector28,   vector29,   vector30,   vector31
-        .weak       vector32,   vector33,   vector34,   vector35
-        .weak       vector36,   vector37,   vector38,   vector39
-        .weak       vector40,   vector41,   vector42,   vector43
-        .weak       vector44,   vector45,   vector46,   vector47
-        .weak       vector48,   vector49,   vector50,   vector51
-        .weak       vector52,   vector53,   vector54,   vector55
-        .weak       vector56,   vector57,   vector58,   vector59
-        .weak       vector60,   vector61,   vector62,   vector63
-        .weak       vector64,   vector65,   vector66,   vector67
-        .weak       vector68,   vector69,   vector70,   vector71
-        .weak       vector72,   vector73,   vector74,   vector75
-        .weak       vector76,   vector77,   vector78,   vector79
-        .weak       vector80,   vector81,   vector82,   vector83
-        .weak       vector84,   vector85,   vector86,   vector87
-        .weak       vector88,   vector89,   vector90,   vector91
-        .weak       vector92,   vector93,   vector94,   vector95
-        .weak       vector96,   vector97,   vector98,   vector99
-        .weak       vector100,  vector101,  vector102,  vector103
-        .weak       vector104,  vector105,  vector106,  vector107
-        .weak       vector108,  vector109,  vector110,  vector111
-        .weak       vector112,  vector113,  vector114,  vector115
-        .weak       vector116,  vector117,  vector118,  vector119
-        .weak       vector120,  vector121,  vector122,  vector123
-        .weak       vector124,  vector125,  vector126,  vector127
-        .weak       vector128,  vector129,  vector130,  vector131
-        .weak       vector132,  vector133,  vector134,  vector135
-        .weak       vector136,  vector137,  vector138,  vector139
-        .weak       vector140,  vector141,  vector142,  vector143
-        .weak       vector144,  vector145,  vector146,  vector147
-        .weak       vector148,  vector149,  vector150,  vector151
-        .weak       vector152,  vector153,  vector154,  vector155
-        .weak       vector156,  vector157,  vector158,  vector159
-        .weak       vector160,  vector161,  vector162,  vector163
-        .weak       vector164,  vector165,  vector166,  vector167
-        .weak       vector168,  vector169,  vector170,  vector171
-        .weak       vector172,  vector173,  vector174,  vector175
-        .weak       vector176,  vector177,  vector178,  vector179
-        .weak       vector180,  vector181,  vector182,  vector183
-        .weak       vector184,  vector185,  vector186,  vector187
-        .weak       vector188,  vector189,  vector190,  vector191
-        .weak       vector192,  vector193,  vector194,  vector195
-        .weak       vector196,  vector197,  vector198,  vector199
-        .weak       vector200,  vector201,  vector202,  vector203
-        .weak       vector204,  vector205,  vector206,  vector207
-        .weak       vector208,  vector209,  vector210,  vector211
-        .weak       vector212,  vector213,  vector214,  vector215
-        .weak       vector216,  vector217,  vector218,  vector219
-        .weak       vector220,  vector221,  vector222,  vector223
-        .weak       vector224,  vector225,  vector226,  vector227
-        .weak       vector228,  vector229,  vector230,  vector231
-        .weak       vector232,  vector233,  vector234,  vector235
-        .weak       vector236,  vector237,  vector238,  vector239
-        .weak       vector240,  vector241,  vector242,  vector243
-        .weak       vector244,  vector245,  vector246,  vector247
-        .weak       vector248,  vector249,  vector250,  vector251
-        .weak       vector252,  vector253,  vector254,  vector255
-        .weak       vector256,  vector257,  vector258,  vector259
-        .weak       vector260
-
-vector0:
-vector1:
-vector2:
-vector3:
-vector4:
-vector5:
-vector6:
-vector7:
-vector8:
-vector9:
-vector10:
-vector11:
-vector12:
-vector13:
-vector14:
-vector15:
-vector16:
-vector17:
-vector18:
-vector19:
-vector20:
-vector21:
-vector22:
-vector23:
-vector24:
-vector25:
-vector26:
-vector27:
-vector28:
-vector29:
-vector30:
-vector31:
-vector32:
-vector33:
-vector34:
-vector35:
-vector36:
-vector37:
-vector38:
-vector39:
-vector40:
-vector41:
-vector42:
-vector43:
-vector44:
-vector45:
-vector46:
-vector47:
-vector48:
-vector49:
-vector50:
-vector51:
-vector52:
-vector53:
-vector54:
-vector55:
-vector56:
-vector57:
-vector58:
-vector59:
-vector60:
-vector61:
-vector62:
-vector63:
-vector64:
-vector65:
-vector66:
-vector67:
-vector68:
-vector69:
-vector70:
-vector71:
-vector72:
-vector73:
-vector74:
-vector75:
-vector76:
-vector77:
-vector78:
-vector79:
-vector80:
-vector81:
-vector82:
-vector83:
-vector84:
-vector85:
-vector86:
-vector87:
-vector88:
-vector89:
-vector90:
-vector91:
-vector92:
-vector93:
-vector94:
-vector95:
-vector96:
-vector97:
-vector98:
-vector99:
-vector100:
-vector101:
-vector102:
-vector103:
-vector104:
-vector105:
-vector106:
-vector107:
-vector108:
-vector109:
-vector110:
-vector111:
-vector112:
-vector113:
-vector114:
-vector115:
-vector116:
-vector117:
-vector118:
-vector119:
-vector120:
-vector121:
-vector122:
-vector123:
-vector124:
-vector125:
-vector126:
-vector127:
-vector128:
-vector129:
-vector130:
-vector131:
-vector132:
-vector133:
-vector134:
-vector135:
-vector136:
-vector137:
-vector138:
-vector139:
-vector140:
-vector141:
-vector142:
-vector143:
-vector144:
-vector145:
-vector146:
-vector147:
-vector148:
-vector149:
-vector150:
-vector151:
-vector152:
-vector153:
-vector154:
-vector155:
-vector156:
-vector157:
-vector158:
-vector159:
-vector160:
-vector161:
-vector162:
-vector163:
-vector164:
-vector165:
-vector166:
-vector167:
-vector168:
-vector169:
-vector170:
-vector171:
-vector172:
-vector173:
-vector174:
-vector175:
-vector176:
-vector177:
-vector178:
-vector179:
-vector180:
-vector181:
-vector182:
-vector183:
-vector184:
-vector185:
-vector186:
-vector187:
-vector188:
-vector189:
-vector190:
-vector191:
-vector192:
-vector193:
-vector194:
-vector195:
-vector196:
-vector197:
-vector198:
-vector199:
-vector200:
-vector201:
-vector202:
-vector203:
-vector204:
-vector205:
-vector206:
-vector207:
-vector208:
-vector209:
-vector210:
-vector211:
-vector212:
-vector213:
-vector214:
-vector215:
-vector216:
-vector217:
-vector218:
-vector219:
-vector220:
-vector221:
-vector222:
-vector223:
-vector224:
-vector225:
-vector226:
-vector227:
-vector228:
-vector229:
-vector230:
-vector231:
-vector232:
-vector233:
-vector234:
-vector235:
-vector236:
-vector237:
-vector238:
-vector239:
-vector240:
-vector241:
-vector242:
-vector243:
-vector244:
-vector245:
-vector246:
-vector247:
-vector248:
-vector249:
-vector250:
-vector251:
-vector252:
-vector253:
-vector254:
-vector255:
-vector256:
-vector257:
-vector258:
-vector259:
-vector260:
-
-        .weak       _unhandled_irq
-        .type       _unhandled_irq, @function
-_unhandled_irq:
-         b          _unhandled_irq
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC563Mxx/bam.s b/os/ports/GCC/PPC/SPC563Mxx/bam.s
deleted file mode 100644
index 19ce1e014..000000000
--- a/os/ports/GCC/PPC/SPC563Mxx/bam.s
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC563Mxx/bam.s
- * @brief   SPC563Mxx boot assistant record.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* BAM record.*/
-        .section    .bam, "ax"
-#if PPC_USE_VLE
-        .long       0x015A0000
-#else
-        .long       0x005A0000
-#endif
-        .long       _reset_address
-
-        .align      2
-        .globl      _reset_address
-        .type       _reset_address, @function
-_reset_address:
-        bl          _coreinit
-        bl          _ivinit
-
-        b           _boot_address
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC563Mxx/core.s b/os/ports/GCC/PPC/SPC563Mxx/core.s
deleted file mode 100644
index a1b3ca37b..000000000
--- a/os/ports/GCC/PPC/SPC563Mxx/core.s
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC563Mxx/core.s
- * @brief   e200z3 core configuration.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-/**
- * @name    BUCSR registers definitions
- * @{
- */
-#define BUCSR_BPEN              0x00000001
-#define BUCSR_BALLOC_BFI        0x00000200
-/** @} */
-
-/**
- * @name    BUCSR default settings
- * @{
- */
-#define BUCSR_DEFAULT           (BUCSR_BPEN | BUCSR_BALLOC_BFI)
-/** @} */
-
-/**
- * @name   MSR register definitions
- * @{
- */
-#define MSR_UCLE                0x04000000
-#define MSR_SPE                 0x02000000
-#define MSR_WE                  0x00040000
-#define MSR_CE                  0x00020000
-#define MSR_EE                  0x00008000
-#define MSR_PR                  0x00004000
-#define MSR_FP                  0x00002000
-#define MSR_ME                  0x00001000
-#define MSR_FE0                 0x00000800
-#define MSR_DE                  0x00000200
-#define MSR_FE1                 0x00000100
-#define MSR_IS                  0x00000020
-#define MSR_DS                  0x00000010
-#define MSR_RI                  0x00000002
-/** @} */
-
-/**
- * @name   MSR default settings
- * @{
- */
-#define MSR_DEFAULT             (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
-/** @} */
-
-#if !defined(__DOXYGEN__)
-
-        .section    .coreinit, "ax"
-
-        .align      2
-        .globl      _coreinit
-        .type       _coreinit, @function
-_coreinit:
-
-        /*
-         * RAM clearing, this device requires a write to all RAM location in
-         * order to initialize the ECC detection hardware, this is going to
-         * slow down the startup but there is no way around.
-         */
-        xor         %r0, %r0, %r0
-        xor         %r1, %r1, %r1
-        xor         %r2, %r2, %r2
-        xor         %r3, %r3, %r3
-        xor         %r4, %r4, %r4
-        xor         %r5, %r5, %r5
-        xor         %r6, %r6, %r6
-        xor         %r7, %r7, %r7
-        xor         %r8, %r8, %r8
-        xor         %r9, %r9, %r9
-        xor         %r10, %r10, %r10
-        xor         %r11, %r11, %r11
-        xor         %r12, %r12, %r12
-        xor         %r13, %r13, %r13
-        xor         %r14, %r14, %r14
-        xor         %r15, %r15, %r15
-        xor         %r16, %r16, %r16
-        xor         %r17, %r17, %r17
-        xor         %r18, %r18, %r18
-        xor         %r19, %r19, %r19
-        xor         %r20, %r20, %r20
-        xor         %r21, %r21, %r21
-        xor         %r22, %r22, %r22
-        xor         %r23, %r23, %r23
-        xor         %r24, %r24, %r24
-        xor         %r25, %r25, %r25
-        xor         %r26, %r26, %r26
-        xor         %r27, %r27, %r27
-        xor         %r28, %r28, %r28
-        xor         %r29, %r29, %r29
-        xor         %r30, %r30, %r30
-        xor         %r31, %r31, %r31
-        lis         %r4, __ram_start__@h
-        ori         %r4, %r4, __ram_start__@l
-        lis         %r5, __ram_end__@h
-        ori         %r5, %r5, __ram_end__@l
-.cleareccloop:
-        cmpl        %cr0, %r4, %r5
-        bge         %cr0, .cleareccend
-        stmw        %r16, 0(%r4)
-        addi        %r4, %r4, 64
-        b           .cleareccloop
-.cleareccend:
-
-        /*
-         * Branch prediction enabled.
-         */
-        li          %r3, BUCSR_DEFAULT
-        mtspr       1013, %r3       /* BUCSR */
-
-        blr
-
-        /*
-         * Exception vectors initialization.
-         */
-        .global     _ivinit
-        .type       _ivinit, @function
-_ivinit:
-        /* MSR initialization.*/
-        lis         %r3, MSR_DEFAULT@h
-        ori         %r3, %r3, MSR_DEFAULT@l
-        mtMSR       %r3
-
-        /* IVPR initialization.*/
-        lis         %r3, __ivpr_base__@h
-        ori         %r3, %r3, __ivpr_base__@l
-        mtIVPR      %r3
-
-        /* IVORs initialization.*/
-        lis         %r3, _unhandled_exception@h
-        ori         %r3, %r3, _unhandled_exception@l
-
-        mtspr       400, %r3        /* IVOR0-15 */
-        mtspr       401, %r3
-        mtspr       402, %r3
-        mtspr       403, %r3
-        mtspr       404, %r3
-        mtspr       405, %r3
-        mtspr       406, %r3
-        mtspr       407, %r3
-        mtspr       408, %r3
-        mtspr       409, %r3
-        mtspr       410, %r3
-        mtspr       411, %r3
-        mtspr       412, %r3
-        mtspr       413, %r3
-        mtspr       414, %r3
-        mtspr       415, %r3
-        mtspr       528, %r3        /* IVOR32-34 */
-        mtspr       529, %r3
-        mtspr       530, %r3
-
-        blr
-
-        .section    .handlers, "ax"
-
-        /*
-         * Unhandled exceptions handler.
-         */
-        .weak       _unhandled_exception
-        .type       _unhandled_exception, @function
-_unhandled_exception:
-        b           _unhandled_exception
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld b/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld
deleted file mode 100644
index e5cb128f3..000000000
--- a/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC563M64 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 1536k
-    ram   : org = 0x40000000, len = 94k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        __ivpr_base__ = .;
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.crt0))
-        KEEP(*(.handlers))
-        . = ALIGN(0x800);
-        KEEP(*(.vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC563Mxx/port.mk b/os/ports/GCC/PPC/SPC563Mxx/port.mk
deleted file mode 100644
index 5f5a1b309..000000000
--- a/os/ports/GCC/PPC/SPC563Mxx/port.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of the ChibiOS/RT SPC563Mxx port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/bam.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/core.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/vectors.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/crt0.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/ld
diff --git a/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h b/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h
deleted file mode 100644
index 94aa98ffd..000000000
--- a/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC563Mxx/ppcparams.h
- * @brief   PowerPC parameters for the SPC563Mxx.
- *
- * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters
- * @ingroup PPC_SPECIFIC
- * @details This file contains the PowerPC specific parameters for the
- *          SPC563Mxx platform.
- * @{
- */
-
-#ifndef _PPCPARAMS_H_
-#define _PPCPARAMS_H_
-
-/**
- * @brief   PPC core model.
- */
-#define PPC_VARIANT                 PPC_VARIANT_e200z3
-
-/**
- * @brief   Number of writable bits in IVPR register.
- */
-#define PPC_IVPR_BITS               16
-
-/**
- * @brief   IVORx registers support.
- */
-#define PPC_SUPPORTS_IVORS          TRUE
-
-/**
- * @brief   Book E instruction set support.
- */
-#define PPC_SUPPORTS_BOOKE          TRUE
-
-/**
- * @brief   VLE instruction set support.
- */
-#define PPC_SUPPORTS_VLE            TRUE
-
-/**
- * @brief   Supports VLS Load/Store Multiple Volatile instructions.
- */
-#define PPC_SUPPORTS_VLE_MULTI      TRUE
-
-/**
- * @brief   Supports the decrementer timer.
- */
-#define PPC_SUPPORTS_DECREMENTER    TRUE
-
-#endif /* _PPCPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC563Mxx/vectors.h b/os/ports/GCC/PPC/SPC563Mxx/vectors.h
deleted file mode 100644
index 9d6d744f6..000000000
--- a/os/ports/GCC/PPC/SPC563Mxx/vectors.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC563Mxx/vectors.h
- * @brief   ISR vector module header.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/*===========================================================================*/
-/* Module constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of ISR vectors available.
- */
-#define VECTORS_NUMBER                      360
-
-/*===========================================================================*/
-/* Module pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-#if !defined(__DOXYGEN__)
-extern uint32_t _vectors[VECTORS_NUMBER];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _unhandled_irq(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !defined(_FROM_ASM_) */
-
-#endif /* _OSAL_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC563Mxx/vectors.s b/os/ports/GCC/PPC/SPC563Mxx/vectors.s
deleted file mode 100644
index dc4cbdfef..000000000
--- a/os/ports/GCC/PPC/SPC563Mxx/vectors.s
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC563Mxx/vectors.s
- * @brief   SPC563Mxx vectors table.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* Software vectors table. The vectors are accessed from the IVOR4
-           handler only. In order to declare an interrupt handler just create
-           a function withe the same name of a vector, the symbol will
-           override the weak symbol declared here.*/
-        .section    .vectors, "ax"
-        .align		4
-        .globl      _vectors
-_vectors:
-        .long       vector0,    vector1,    vector2,    vector3
-        .long       vector4,    vector5,    vector6,    vector7
-        .long       vector8,    vector9,    vector10,   vector11
-        .long       vector12,   vector13,   vector14,   vector15
-        .long       vector16,   vector17,   vector18,   vector19
-        .long       vector20,   vector21,   vector22,   vector23
-        .long       vector24,   vector25,   vector26,   vector27
-        .long       vector28,   vector29,   vector30,   vector31
-        .long       vector32,   vector33,   vector34,   vector35
-        .long       vector36,   vector37,   vector38,   vector39
-        .long       vector40,   vector41,   vector42,   vector43
-        .long       vector44,   vector45,   vector46,   vector47
-        .long       vector48,   vector49,   vector50,   vector51
-        .long       vector52,   vector53,   vector54,   vector55
-        .long       vector56,   vector57,   vector58,   vector59
-        .long       vector60,   vector61,   vector62,   vector63
-        .long       vector64,   vector65,   vector66,   vector67
-        .long       vector68,   vector69,   vector70,   vector71
-        .long       vector72,   vector73,   vector74,   vector75
-        .long       vector76,   vector77,   vector78,   vector79
-        .long       vector80,   vector81,   vector82,   vector83
-        .long       vector84,   vector85,   vector86,   vector87
-        .long       vector88,   vector89,   vector90,   vector91
-        .long       vector92,   vector93,   vector94,   vector95
-        .long       vector96,   vector97,   vector98,   vector99
-        .long       vector100,  vector101,  vector102,  vector103
-        .long       vector104,  vector105,  vector106,  vector107
-        .long       vector108,  vector109,  vector110,  vector111
-        .long       vector112,  vector113,  vector114,  vector115
-        .long       vector116,  vector117,  vector118,  vector119
-        .long       vector120,  vector121,  vector122,  vector123
-        .long       vector124,  vector125,  vector126,  vector127
-        .long       vector128,  vector129,  vector130,  vector131
-        .long       vector132,  vector133,  vector134,  vector135
-        .long       vector136,  vector137,  vector138,  vector139
-        .long       vector140,  vector141,  vector142,  vector143
-        .long       vector144,  vector145,  vector146,  vector147
-        .long       vector148,  vector149,  vector150,  vector151
-        .long       vector152,  vector153,  vector154,  vector155
-        .long       vector156,  vector157,  vector158,  vector159
-        .long       vector160,  vector161,  vector162,  vector163
-        .long       vector164,  vector165,  vector166,  vector167
-        .long       vector168,  vector169,  vector170,  vector171
-        .long       vector172,  vector173,  vector174,  vector175
-        .long       vector176,  vector177,  vector178,  vector179
-        .long       vector180,  vector181,  vector182,  vector183
-        .long       vector184,  vector185,  vector186,  vector187
-        .long       vector188,  vector189,  vector190,  vector191
-        .long       vector192,  vector193,  vector194,  vector195
-        .long       vector196,  vector197,  vector198,  vector199
-        .long       vector200,  vector201,  vector202,  vector203
-        .long       vector204,  vector205,  vector206,  vector207
-        .long       vector208,  vector209,  vector210,  vector211
-        .long       vector212,  vector213,  vector214,  vector215
-        .long       vector216,  vector217,  vector218,  vector219
-        .long       vector220,  vector221,  vector222,  vector223
-        .long       vector224,  vector225,  vector226,  vector227
-        .long       vector228,  vector229,  vector230,  vector231
-        .long       vector232,  vector233,  vector234,  vector235
-        .long       vector236,  vector237,  vector238,  vector239
-        .long       vector240,  vector241,  vector242,  vector243
-        .long       vector244,  vector245,  vector246,  vector247
-        .long       vector248,  vector249,  vector250,  vector251
-        .long       vector252,  vector253,  vector254,  vector255
-        .long       vector256,  vector257,  vector258,  vector259
-        .long       vector260,  vector261,  vector262,  vector263
-        .long       vector264,  vector265,  vector266,  vector267
-        .long       vector268,  vector269,  vector270,  vector271
-        .long       vector272,  vector273,  vector274,  vector275
-        .long       vector276,  vector277,  vector278,  vector279
-        .long       vector280,  vector281,  vector282,  vector283
-        .long       vector284,  vector285,  vector286,  vector287
-        .long       vector288,  vector289,  vector290,  vector291
-        .long       vector292,  vector293,  vector294,  vector295
-        .long       vector296,  vector297,  vector298,  vector299
-        .long       vector300,  vector301,  vector302,  vector303
-        .long       vector304,  vector305,  vector306,  vector307
-        .long       vector308,  vector309,  vector310,  vector311
-        .long       vector312,  vector313,  vector314,  vector315
-        .long       vector316,  vector317,  vector318,  vector319
-        .long       vector320,  vector321,  vector322,  vector323
-        .long       vector324,  vector325,  vector326,  vector327
-        .long       vector328,  vector329,  vector330,  vector331
-        .long       vector332,  vector333,  vector334,  vector335
-        .long       vector336,  vector337,  vector338,  vector339
-        .long       vector340,  vector341,  vector342,  vector343
-        .long       vector344,  vector345,  vector346,  vector347
-        .long       vector348,  vector349,  vector350,  vector351
-        .long       vector352,  vector353,  vector354,  vector355
-        .long       vector356,  vector357,  vector358,  vector359
-
-        .text
-        .align      2
-        
-        .weak       vector0,    vector1,    vector2,    vector3
-        .weak       vector4,    vector5,    vector6,    vector7
-        .weak       vector8,    vector9,    vector10,   vector11
-        .weak       vector12,   vector13,   vector14,   vector15
-        .weak       vector16,   vector17,   vector18,   vector19
-        .weak       vector20,   vector21,   vector22,   vector23
-        .weak       vector24,   vector25,   vector26,   vector27
-        .weak       vector28,   vector29,   vector30,   vector31
-        .weak       vector32,   vector33,   vector34,   vector35
-        .weak       vector36,   vector37,   vector38,   vector39
-        .weak       vector40,   vector41,   vector42,   vector43
-        .weak       vector44,   vector45,   vector46,   vector47
-        .weak       vector48,   vector49,   vector50,   vector51
-        .weak       vector52,   vector53,   vector54,   vector55
-        .weak       vector56,   vector57,   vector58,   vector59
-        .weak       vector60,   vector61,   vector62,   vector63
-        .weak       vector64,   vector65,   vector66,   vector67
-        .weak       vector68,   vector69,   vector70,   vector71
-        .weak       vector72,   vector73,   vector74,   vector75
-        .weak       vector76,   vector77,   vector78,   vector79
-        .weak       vector80,   vector81,   vector82,   vector83
-        .weak       vector84,   vector85,   vector86,   vector87
-        .weak       vector88,   vector89,   vector90,   vector91
-        .weak       vector92,   vector93,   vector94,   vector95
-        .weak       vector96,   vector97,   vector98,   vector99
-        .weak       vector100,  vector101,  vector102,  vector103
-        .weak       vector104,  vector105,  vector106,  vector107
-        .weak       vector108,  vector109,  vector110,  vector111
-        .weak       vector112,  vector113,  vector114,  vector115
-        .weak       vector116,  vector117,  vector118,  vector119
-        .weak       vector120,  vector121,  vector122,  vector123
-        .weak       vector124,  vector125,  vector126,  vector127
-        .weak       vector128,  vector129,  vector130,  vector131
-        .weak       vector132,  vector133,  vector134,  vector135
-        .weak       vector136,  vector137,  vector138,  vector139
-        .weak       vector140,  vector141,  vector142,  vector143
-        .weak       vector144,  vector145,  vector146,  vector147
-        .weak       vector148,  vector149,  vector150,  vector151
-        .weak       vector152,  vector153,  vector154,  vector155
-        .weak       vector156,  vector157,  vector158,  vector159
-        .weak       vector160,  vector161,  vector162,  vector163
-        .weak       vector164,  vector165,  vector166,  vector167
-        .weak       vector168,  vector169,  vector170,  vector171
-        .weak       vector172,  vector173,  vector174,  vector175
-        .weak       vector176,  vector177,  vector178,  vector179
-        .weak       vector180,  vector181,  vector182,  vector183
-        .weak       vector184,  vector185,  vector186,  vector187
-        .weak       vector188,  vector189,  vector190,  vector191
-        .weak       vector192,  vector193,  vector194,  vector195
-        .weak       vector196,  vector197,  vector198,  vector199
-        .weak       vector200,  vector201,  vector202,  vector203
-        .weak       vector204,  vector205,  vector206,  vector207
-        .weak       vector208,  vector209,  vector210,  vector211
-        .weak       vector212,  vector213,  vector214,  vector215
-        .weak       vector216,  vector217,  vector218,  vector219
-        .weak       vector220,  vector221,  vector222,  vector223
-        .weak       vector224,  vector225,  vector226,  vector227
-        .weak       vector228,  vector229,  vector230,  vector231
-        .weak       vector232,  vector233,  vector234,  vector235
-        .weak       vector236,  vector237,  vector238,  vector239
-        .weak       vector240,  vector241,  vector242,  vector243
-        .weak       vector244,  vector245,  vector246,  vector247
-        .weak       vector248,  vector249,  vector250,  vector251
-        .weak       vector252,  vector253,  vector254,  vector255
-        .weak       vector256,  vector257,  vector258,  vector259
-        .weak       vector260,  vector261,  vector262,  vector263
-        .weak       vector264,  vector265,  vector266,  vector267
-        .weak       vector268,  vector269,  vector270,  vector271
-        .weak       vector272,  vector273,  vector274,  vector275
-        .weak       vector276,  vector277,  vector278,  vector279
-        .weak       vector280,  vector281,  vector282,  vector283
-        .weak       vector284,  vector285,  vector286,  vector287
-        .weak       vector288,  vector289,  vector290,  vector291
-        .weak       vector292,  vector293,  vector294,  vector295
-        .weak       vector296,  vector297,  vector298,  vector299
-        .weak       vector300,  vector301,  vector302,  vector303
-        .weak       vector304,  vector305,  vector306,  vector307
-        .weak       vector308,  vector309,  vector310,  vector311
-        .weak       vector312,  vector313,  vector314,  vector315
-        .weak       vector316,  vector317,  vector318,  vector319
-        .weak       vector320,  vector321,  vector322,  vector323
-        .weak       vector324,  vector325,  vector326,  vector327
-        .weak       vector328,  vector329,  vector330,  vector331
-        .weak       vector332,  vector333,  vector334,  vector335
-        .weak       vector336,  vector337,  vector338,  vector339
-        .weak       vector340,  vector341,  vector342,  vector343
-        .weak       vector344,  vector345,  vector346,  vector347
-        .weak       vector348,  vector349,  vector350,  vector351
-        .weak       vector352,  vector353,  vector354,  vector355
-        .weak       vector356,  vector357,  vector358,  vector359
-
-vector0:
-vector1:
-vector2:
-vector3:
-vector4:
-vector5:
-vector6:
-vector7:
-vector8:
-vector9:
-vector10:
-vector11:
-vector12:
-vector13:
-vector14:
-vector15:
-vector16:
-vector17:
-vector18:
-vector19:
-vector20:
-vector21:
-vector22:
-vector23:
-vector24:
-vector25:
-vector26:
-vector27:
-vector28:
-vector29:
-vector30:
-vector31:
-vector32:
-vector33:
-vector34:
-vector35:
-vector36:
-vector37:
-vector38:
-vector39:
-vector40:
-vector41:
-vector42:
-vector43:
-vector44:
-vector45:
-vector46:
-vector47:
-vector48:
-vector49:
-vector50:
-vector51:
-vector52:
-vector53:
-vector54:
-vector55:
-vector56:
-vector57:
-vector58:
-vector59:
-vector60:
-vector61:
-vector62:
-vector63:
-vector64:
-vector65:
-vector66:
-vector67:
-vector68:
-vector69:
-vector70:
-vector71:
-vector72:
-vector73:
-vector74:
-vector75:
-vector76:
-vector77:
-vector78:
-vector79:
-vector80:
-vector81:
-vector82:
-vector83:
-vector84:
-vector85:
-vector86:
-vector87:
-vector88:
-vector89:
-vector90:
-vector91:
-vector92:
-vector93:
-vector94:
-vector95:
-vector96:
-vector97:
-vector98:
-vector99:
-vector100:
-vector101:
-vector102:
-vector103:
-vector104:
-vector105:
-vector106:
-vector107:
-vector108:
-vector109:
-vector110:
-vector111:
-vector112:
-vector113:
-vector114:
-vector115:
-vector116:
-vector117:
-vector118:
-vector119:
-vector120:
-vector121:
-vector122:
-vector123:
-vector124:
-vector125:
-vector126:
-vector127:
-vector128:
-vector129:
-vector130:
-vector131:
-vector132:
-vector133:
-vector134:
-vector135:
-vector136:
-vector137:
-vector138:
-vector139:
-vector140:
-vector141:
-vector142:
-vector143:
-vector144:
-vector145:
-vector146:
-vector147:
-vector148:
-vector149:
-vector150:
-vector151:
-vector152:
-vector153:
-vector154:
-vector155:
-vector156:
-vector157:
-vector158:
-vector159:
-vector160:
-vector161:
-vector162:
-vector163:
-vector164:
-vector165:
-vector166:
-vector167:
-vector168:
-vector169:
-vector170:
-vector171:
-vector172:
-vector173:
-vector174:
-vector175:
-vector176:
-vector177:
-vector178:
-vector179:
-vector180:
-vector181:
-vector182:
-vector183:
-vector184:
-vector185:
-vector186:
-vector187:
-vector188:
-vector189:
-vector190:
-vector191:
-vector192:
-vector193:
-vector194:
-vector195:
-vector196:
-vector197:
-vector198:
-vector199:
-vector200:
-vector201:
-vector202:
-vector203:
-vector204:
-vector205:
-vector206:
-vector207:
-vector208:
-vector209:
-vector210:
-vector211:
-vector212:
-vector213:
-vector214:
-vector215:
-vector216:
-vector217:
-vector218:
-vector219:
-vector220:
-vector221:
-vector222:
-vector223:
-vector224:
-vector225:
-vector226:
-vector227:
-vector228:
-vector229:
-vector230:
-vector231:
-vector232:
-vector233:
-vector234:
-vector235:
-vector236:
-vector237:
-vector238:
-vector239:
-vector240:
-vector241:
-vector242:
-vector243:
-vector244:
-vector245:
-vector246:
-vector247:
-vector248:
-vector249:
-vector250:
-vector251:
-vector252:
-vector253:
-vector254:
-vector255:
-vector256:
-vector257:
-vector258:
-vector259:
-vector260:
-vector261:
-vector262:
-vector263:
-vector264:
-vector265:
-vector266:
-vector267:
-vector268:
-vector269:
-vector270:
-vector271:
-vector272:
-vector273:
-vector274:
-vector275:
-vector276:
-vector277:
-vector278:
-vector279:
-vector280:
-vector281:
-vector282:
-vector283:
-vector284:
-vector285:
-vector286:
-vector287:
-vector288:
-vector289:
-vector290:
-vector291:
-vector292:
-vector293:
-vector294:
-vector295:
-vector296:
-vector297:
-vector298:
-vector299:
-vector300:
-vector301:
-vector302:
-vector303:
-vector304:
-vector305:
-vector306:
-vector307:
-vector308:
-vector309:
-vector310:
-vector311:
-vector312:
-vector313:
-vector314:
-vector315:
-vector316:
-vector317:
-vector318:
-vector319:
-vector320:
-vector321:
-vector322:
-vector323:
-vector324:
-vector325:
-vector326:
-vector327:
-vector328:
-vector329:
-vector330:
-vector331:
-vector332:
-vector333:
-vector334:
-vector335:
-vector336:
-vector337:
-vector338:
-vector339:
-vector340:
-vector341:
-vector342:
-vector343:
-vector344:
-vector345:
-vector346:
-vector347:
-vector348:
-vector349:
-vector350:
-vector351:
-vector352:
-vector353:
-vector354:
-vector355:
-vector356:
-vector357:
-vector358:
-vector359:
-
-        .weak       _unhandled_irq
-        .type       _unhandled_irq, @function
-_unhandled_irq:
-         b          _unhandled_irq
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC564Axx/bam.s b/os/ports/GCC/PPC/SPC564Axx/bam.s
deleted file mode 100644
index 316724abf..000000000
--- a/os/ports/GCC/PPC/SPC564Axx/bam.s
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC564Axx/bam.s
- * @brief   SPC564Axx boot assistant record.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* BAM record.*/
-        .section    .bam, "ax"
-#if PPC_USE_VLE
-        .long       0x015A0000
-#else
-        .long       0x005A0000
-#endif
-        .long       _reset_address
-
-        .align      2
-        .globl      _reset_address
-        .type       _reset_address, @function
-_reset_address:
-        bl          _coreinit
-        bl          _ivinit
-
-        b           _boot_address
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC564Axx/core.s b/os/ports/GCC/PPC/SPC564Axx/core.s
deleted file mode 100644
index bd6ad0fed..000000000
--- a/os/ports/GCC/PPC/SPC564Axx/core.s
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC564Axx/core.s
- * @brief   e200z4 core configuration.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-/**
- * @name   MASx registers definitions
- * @{
- */
-#define MAS0_TBLMAS_TBL         0x10000000
-#define MAS0_ESEL_MASK          0x000F0000
-#define MAS0_ESEL(n)            ((n) << 16)
-
-#define MAS1_VALID              0x80000000
-#define MAS1_IPROT              0x40000000
-#define MAS1_TID_MASK           0x00FF0000
-#define MAS1_TS                 0x00001000
-#define MAS1_TSISE_MASK         0x00000F80
-#define MAS1_TSISE_1K           0x00000000
-#define MAS1_TSISE_2K           0x00000080
-#define MAS1_TSISE_4K           0x00000100
-#define MAS1_TSISE_8K           0x00000180
-#define MAS1_TSISE_16K          0x00000200
-#define MAS1_TSISE_32K          0x00000280
-#define MAS1_TSISE_64K          0x00000300
-#define MAS1_TSISE_128K         0x00000380
-#define MAS1_TSISE_256K         0x00000400
-#define MAS1_TSISE_512K         0x00000480
-#define MAS1_TSISE_1M           0x00000500
-#define MAS1_TSISE_2M           0x00000580
-#define MAS1_TSISE_4M           0x00000600
-#define MAS1_TSISE_8M           0x00000680
-#define MAS1_TSISE_16M          0x00000700
-#define MAS1_TSISE_32M          0x00000780
-#define MAS1_TSISE_64M          0x00000800
-#define MAS1_TSISE_128M         0x00000880
-#define MAS1_TSISE_256M         0x00000900
-#define MAS1_TSISE_512M         0x00000980
-#define MAS1_TSISE_1G           0x00000A00
-#define MAS1_TSISE_2G           0x00000A80
-#define MAS1_TSISE_4G           0x00000B00
-
-#define MAS2_EPN_MASK           0xFFFFFC00
-#define MAS2_EPN(n)             ((n) & MAS2_EPN_MASK)
-#define MAS2_EBOOK              0x00000000
-#define MAS2_VLE                0x00000020
-#define MAS2_W                  0x00000010
-#define MAS2_I                  0x00000008
-#define MAS2_M                  0x00000004
-#define MAS2_G                  0x00000002
-#define MAS2_E                  0x00000001
-
-#define MAS3_RPN_MASK           0xFFFFFC00
-#define MAS3_RPN(n)             ((n) & MAS3_RPN_MASK)
-#define MAS3_U0                 0x00000200
-#define MAS3_U1                 0x00000100
-#define MAS3_U2                 0x00000080
-#define MAS3_U3                 0x00000040
-#define MAS3_UX                 0x00000020
-#define MAS3_SX                 0x00000010
-#define MAS3_UW                 0x00000008
-#define MAS3_SW                 0x00000004
-#define MAS3_UR                 0x00000002
-#define MAS3_SR                 0x00000001
-/** @} */
-
-/**
- * @name    BUCSR registers definitions
- * @{
- */
-#define BUCSR_BPEN              0x00000001
-#define BUCSR_BPRED_MASK        0x00000006
-#define BUCSR_BPRED_0           0x00000000
-#define BUCSR_BPRED_1           0x00000002
-#define BUCSR_BPRED_2           0x00000004
-#define BUCSR_BPRED_3           0x00000006
-#define BUCSR_BALLOC_MASK       0x00000030
-#define BUCSR_BALLOC_0          0x00000000
-#define BUCSR_BALLOC_1          0x00000010
-#define BUCSR_BALLOC_2          0x00000020
-#define BUCSR_BALLOC_3          0x00000030
-#define BUCSR_BALLOC_BFI        0x00000200
-/** @} */
-
-/**
- * @name    TLB default settings
- * @{
- */
-#define TLB0_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
-#define TLB0_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
-#define TLB0_MAS2               (MAS2_EPN(0x40000000) | MAS2_VLE)
-#define TLB0_MAS3               (MAS3_RPN(0x40000000) |                     \
-                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
-                                 MAS3_UR | MAS3_SR)
-
-#define TLB1_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
-#define TLB1_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
-#define TLB1_MAS2               (MAS2_EPN(0x00000000) | MAS2_VLE)
-#define TLB1_MAS3               (MAS3_RPN(0x00000000) |                     \
-                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
-                                 MAS3_UR | MAS3_SR)
-
-#define TLB2_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
-#define TLB2_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
-#define TLB2_MAS2               (MAS2_EPN(0xC3F00000) | MAS2_I)
-#define TLB2_MAS3               (MAS3_RPN(0xC3F00000) |                     \
-                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
-
-#define TLB3_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
-#define TLB3_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
-#define TLB3_MAS2               (MAS2_EPN(0xFFE00000) | MAS2_I)
-#define TLB3_MAS3               (MAS3_RPN(0xFFE00000) |                     \
-                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
-
-#define TLB4_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
-#define TLB4_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
-#define TLB4_MAS2               (MAS2_EPN(0xFFF00000) | MAS2_I)
-#define TLB4_MAS3               (MAS3_RPN(0xFFF00000) |                     \
-                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
-/** @} */
-
-/**
- * @name    LICSR1 registers definitions
- * @{
- */
-#define LICSR1_ICE              0x00000001
-#define LICSR1_ICINV            0x00000002
-#define LICSR1_ICORG            0x00000010
-/** @} */
-
-/**
- * @name    BUCSR default settings
- * @{
- */
-#define BUCSR_DEFAULT           (BUCSR_BPEN | BUCSR_BPRED_0 |               \
-                                 BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
-/** @} */
-
-/**
- * @name    LICSR1 default settings
- * @{
- */
-#define LICSR1_DEFAULT          (LICSR1_ICE | LICSR1_ICORG)
-/** @} */
-
-/**
- * @name   MSR register definitions
- * @{
- */
-#define MSR_UCLE                0x04000000
-#define MSR_SPE                 0x02000000
-#define MSR_WE                  0x00040000
-#define MSR_CE                  0x00020000
-#define MSR_EE                  0x00008000
-#define MSR_PR                  0x00004000
-#define MSR_FP                  0x00002000
-#define MSR_ME                  0x00001000
-#define MSR_FE0                 0x00000800
-#define MSR_DE                  0x00000200
-#define MSR_FE1                 0x00000100
-#define MSR_IS                  0x00000020
-#define MSR_DS                  0x00000010
-#define MSR_RI                  0x00000002
-/** @} */
-
-/**
- * @name   MSR default settings
- * @{
- */
-#define MSR_DEFAULT             (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
-/** @} */
-
-#if !defined(__DOXYGEN__)
-
-        .section    .coreinit, "ax"
-
-        .align      2
-_ramcode:
-        tlbwe
-        isync
-        blr
-
-        .align      2
-        .globl      _coreinit
-        .type       _coreinit, @function
-_coreinit:
-        /*
-         * Invalidating all TLBs except TLB1.
-         */
-        lis         %r3, 0
-        mtspr       625, %r3        /* MAS1 */
-        mtspr       626, %r3        /* MAS2 */
-        mtspr       627, %r3        /* MAS3 */
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-
-        /*
-         * TLB0 allocated to internal RAM.
-         */
-        lis         %r3, TLB0_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB0_MAS1@h
-        ori         %r3, %r3, TLB0_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB0_MAS2@h
-        ori         %r3, %r3, TLB0_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB0_MAS3@h
-        ori         %r3, %r3, TLB0_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        tlbwe
-
-        /*
-         * TLB2 allocated to internal Peripherals Bridge A.
-         */
-        lis         %r3, TLB2_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB2_MAS1@h
-        ori         %r3, %r3, TLB2_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB2_MAS2@h
-        ori         %r3, %r3, TLB2_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB2_MAS3@h
-        ori         %r3, %r3, TLB2_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        tlbwe
-
-        /*
-         * TLB3 allocated to internal Peripherals Bridge B.
-         */
-        lis         %r3, TLB3_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB3_MAS1@h
-        ori         %r3, %r3, TLB3_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB3_MAS2@h
-        ori         %r3, %r3, TLB3_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB3_MAS3@h
-        ori         %r3, %r3, TLB3_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        tlbwe
-
-        /*
-         * TLB4 allocated to on-platform peripherals.
-         */
-        lis         %r3, TLB4_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB4_MAS1@h
-        ori         %r3, %r3, TLB4_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB4_MAS2@h
-        ori         %r3, %r3, TLB4_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB4_MAS3@h
-        ori         %r3, %r3, TLB4_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        tlbwe
-
-        /*
-         * RAM clearing, this device requires a write to all RAM location in
-         * order to initialize the ECC detection hardware, this is going to
-         * slow down the startup but there is no way around.
-         */
-        xor         %r0, %r0, %r0
-        xor         %r1, %r1, %r1
-        xor         %r2, %r2, %r2
-        xor         %r3, %r3, %r3
-        xor         %r4, %r4, %r4
-        xor         %r5, %r5, %r5
-        xor         %r6, %r6, %r6
-        xor         %r7, %r7, %r7
-        xor         %r8, %r8, %r8
-        xor         %r9, %r9, %r9
-        xor         %r10, %r10, %r10
-        xor         %r11, %r11, %r11
-        xor         %r12, %r12, %r12
-        xor         %r13, %r13, %r13
-        xor         %r14, %r14, %r14
-        xor         %r15, %r15, %r15
-        xor         %r16, %r16, %r16
-        xor         %r17, %r17, %r17
-        xor         %r18, %r18, %r18
-        xor         %r19, %r19, %r19
-        xor         %r20, %r20, %r20
-        xor         %r21, %r21, %r21
-        xor         %r22, %r22, %r22
-        xor         %r23, %r23, %r23
-        xor         %r24, %r24, %r24
-        xor         %r25, %r25, %r25
-        xor         %r26, %r26, %r26
-        xor         %r27, %r27, %r27
-        xor         %r28, %r28, %r28
-        xor         %r29, %r29, %r29
-        xor         %r30, %r30, %r30
-        xor         %r31, %r31, %r31
-        lis         %r4, __ram_start__@h
-        ori         %r4, %r4, __ram_start__@l
-        lis         %r5, __ram_end__@h
-        ori         %r5, %r5, __ram_end__@l
-.cleareccloop:
-        cmpl        %cr0, %r4, %r5
-        bge         %cr0, .cleareccend
-        stmw        %r16, 0(%r4)
-        addi        %r4, %r4, 64
-        b           .cleareccloop
-.cleareccend:
-
-        /*
-         * *Finally* the TLB1 is re-allocated to flash, note, the final phase
-         * is executed from RAM.
-         */
-        lis         %r3, TLB1_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB1_MAS1@h
-        ori         %r3, %r3, TLB1_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB1_MAS2@h
-        ori         %r3, %r3, TLB1_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB1_MAS3@h
-        ori         %r3, %r3, TLB1_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        mflr        %r4
-        lis         %r6, _ramcode@h
-        ori         %r6, %r6, _ramcode@l
-        lis         %r7, 0x40010000@h
-        mtctr       %r7
-        lwz         %r3, 0(%r6)
-        stw         %r3, 0(%r7)
-        lwz         %r3, 4(%r6)
-        stw         %r3, 4(%r7)
-        lwz         %r3, 8(%r6)
-        stw         %r3, 8(%r7)
-        bctrl
-        mtlr        %r4
-
-        /*
-         * Branch prediction enabled.
-         */
-        li          %r3, BUCSR_DEFAULT
-        mtspr       1013, %r3       /* BUCSR */
-
-        /*
-         * Cache invalidated and then enabled.
-         */
-        li          %r3, LICSR1_ICINV
-        mtspr       1011, %r3       /* LICSR1 */
-.inv:   mfspr       %r3, 1011       /* LICSR1 */
-        andi.       %r3, %r3, LICSR1_ICINV
-        bne         .inv
-        lis         %r3, LICSR1_DEFAULT@h
-        ori         %r3, %r3, LICSR1_DEFAULT@l
-        mtspr       1011, %r3       /* LICSR1 */
-
-        blr
-
-        /*
-         * Exception vectors initialization.
-         */
-        .global     _ivinit
-        .type       _ivinit, @function
-_ivinit:
-        /* MSR initialization.*/
-        lis         %r3, MSR_DEFAULT@h
-        ori         %r3, %r3, MSR_DEFAULT@l
-        mtMSR       %r3
-
-        /* IVPR initialization.*/
-        lis         %r3, __ivpr_base__@h
-        ori         %r3, %r3, __ivpr_base__@l
-        mtIVPR      %r3
-
-        /* IVORs initialization.*/
-        lis         %r3, _unhandled_exception@h
-        ori         %r3, %r3, _unhandled_exception@l
-
-        mtspr       400, %r3        /* IVOR0-15 */
-        mtspr       401, %r3
-        mtspr       402, %r3
-        mtspr       403, %r3
-        mtspr       404, %r3
-        mtspr       405, %r3
-        mtspr       406, %r3
-        mtspr       407, %r3
-        mtspr       408, %r3
-        mtspr       409, %r3
-        mtspr       410, %r3
-        mtspr       411, %r3
-        mtspr       412, %r3
-        mtspr       413, %r3
-        mtspr       414, %r3
-        mtspr       415, %r3
-        mtspr       528, %r3        /* IVOR32-34 */
-        mtspr       529, %r3
-        mtspr       530, %r3
-
-        blr
-
-        .section    .handlers, "ax"
-
-        /*
-         * Unhandled exceptions handler.
-         */
-        .weak       _unhandled_exception
-        .type       _unhandled_exception, @function
-_unhandled_exception:
-        b           _unhandled_exception
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A70.ld b/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A70.ld
deleted file mode 100644
index 5d37dc11b..000000000
--- a/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A70.ld
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC564A70 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 2M
-    ram   : org = 0x40000000, len = 128k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        __ivpr_base__ = .;
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.crt0))
-        KEEP(*(.handlers))
-        . = ALIGN(0x800);
-        KEEP(*(.vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A80.ld b/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A80.ld
deleted file mode 100644
index 7ee528a05..000000000
--- a/os/ports/GCC/PPC/SPC564Axx/ld/SPC564A80.ld
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC564A80 memory setup.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash : org = 0x00000000, len = 4M
-    ram   : org = 0x40000000, len = 192k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        __ivpr_base__ = .;
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.crt0))
-        KEEP(*(.handlers))
-        . = ALIGN(0x800);
-        KEEP(*(.vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC564Axx/port.mk b/os/ports/GCC/PPC/SPC564Axx/port.mk
deleted file mode 100644
index 81422d7c6..000000000
--- a/os/ports/GCC/PPC/SPC564Axx/port.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of the ChibiOS/RT SPC564Axx port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx/bam.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx/core.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx/vectors.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/crt0.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/PPC/SPC564Axx/ld
diff --git a/os/ports/GCC/PPC/SPC564Axx/ppcparams.h b/os/ports/GCC/PPC/SPC564Axx/ppcparams.h
deleted file mode 100644
index 4525b168c..000000000
--- a/os/ports/GCC/PPC/SPC564Axx/ppcparams.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC564Axx/ppcparams.h
- * @brief   PowerPC parameters for the SPC564Axx.
- *
- * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters
- * @ingroup PPC_SPECIFIC
- * @details This file contains the PowerPC specific parameters for the
- *          SPC564Axx platform.
- * @{
- */
-
-#ifndef _PPCPARAMS_H_
-#define _PPCPARAMS_H_
-
-/**
- * @brief   PPC core model.
- */
-#define PPC_VARIANT                 PPC_VARIANT_e200z4
-
-/**
- * @brief   IVORx registers support.
- */
-#define PPC_SUPPORTS_IVORS          TRUE
-
-/**
- * @brief   Book E instruction set support.
- */
-#define PPC_SUPPORTS_BOOKE          TRUE
-
-/**
- * @brief   VLE instruction set support.
- */
-#define PPC_SUPPORTS_VLE            TRUE
-
-/**
- * @brief   Supports VLS Load/Store Multiple Volatile instructions.
- */
-#define PPC_SUPPORTS_VLE_MULTI      TRUE
-
-/**
- * @brief   Supports the decrementer timer.
- */
-#define PPC_SUPPORTS_DECREMENTER    TRUE
-
-#endif /* _PPCPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC564Axx/vectors.h b/os/ports/GCC/PPC/SPC564Axx/vectors.h
deleted file mode 100644
index 2e8ab38a1..000000000
--- a/os/ports/GCC/PPC/SPC564Axx/vectors.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC564Axx/vectors.h
- * @brief   ISR vector module header.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/*===========================================================================*/
-/* Module constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of ISR vectors available.
- */
-#define VECTORS_NUMBER                      486
-
-/*===========================================================================*/
-/* Module pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-#if !defined(__DOXYGEN__)
-extern uint32_t _vectors[VECTORS_NUMBER];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _unhandled_irq(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !defined(_FROM_ASM_) */
-
-#endif /* _OSAL_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC564Axx/vectors.s b/os/ports/GCC/PPC/SPC564Axx/vectors.s
deleted file mode 100644
index 7ac668d35..000000000
--- a/os/ports/GCC/PPC/SPC564Axx/vectors.s
+++ /dev/null
@@ -1,782 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC564Axx/vectors.s
- * @brief   SPC564Axx vectors table.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* Software vectors table. The vectors are accessed from the IVOR4
-           handler only. In order to declare an interrupt handler just create
-           a function withe the same name of a vector, the symbol will
-           override the weak symbol declared here.*/
-        .section    .vectors, "ax"
-        .align		4
-        .globl      _vectors
-_vectors:
-        .long       vector0,    vector1,    vector2,    vector3
-        .long       vector4,    vector5,    vector6,    vector7
-        .long       vector8,    vector9,    vector10,   vector11
-        .long       vector12,   vector13,   vector14,   vector15
-        .long       vector16,   vector17,   vector18,   vector19
-        .long       vector20,   vector21,   vector22,   vector23
-        .long       vector24,   vector25,   vector26,   vector27
-        .long       vector28,   vector29,   vector30,   vector31
-        .long       vector32,   vector33,   vector34,   vector35
-        .long       vector36,   vector37,   vector38,   vector39
-        .long       vector40,   vector41,   vector42,   vector43
-        .long       vector44,   vector45,   vector46,   vector47
-        .long       vector48,   vector49,   vector50,   vector51
-        .long       vector52,   vector53,   vector54,   vector55
-        .long       vector56,   vector57,   vector58,   vector59
-        .long       vector60,   vector61,   vector62,   vector63
-        .long       vector64,   vector65,   vector66,   vector67
-        .long       vector68,   vector69,   vector70,   vector71
-        .long       vector72,   vector73,   vector74,   vector75
-        .long       vector76,   vector77,   vector78,   vector79
-        .long       vector80,   vector81,   vector82,   vector83
-        .long       vector84,   vector85,   vector86,   vector87
-        .long       vector88,   vector89,   vector90,   vector91
-        .long       vector92,   vector93,   vector94,   vector95
-        .long       vector96,   vector97,   vector98,   vector99
-        .long       vector100,  vector101,  vector102,  vector103
-        .long       vector104,  vector105,  vector106,  vector107
-        .long       vector108,  vector109,  vector110,  vector111
-        .long       vector112,  vector113,  vector114,  vector115
-        .long       vector116,  vector117,  vector118,  vector119
-        .long       vector120,  vector121,  vector122,  vector123
-        .long       vector124,  vector125,  vector126,  vector127
-        .long       vector128,  vector129,  vector130,  vector131
-        .long       vector132,  vector133,  vector134,  vector135
-        .long       vector136,  vector137,  vector138,  vector139
-        .long       vector140,  vector141,  vector142,  vector143
-        .long       vector144,  vector145,  vector146,  vector147
-        .long       vector148,  vector149,  vector150,  vector151
-        .long       vector152,  vector153,  vector154,  vector155
-        .long       vector156,  vector157,  vector158,  vector159
-        .long       vector160,  vector161,  vector162,  vector163
-        .long       vector164,  vector165,  vector166,  vector167
-        .long       vector168,  vector169,  vector170,  vector171
-        .long       vector172,  vector173,  vector174,  vector175
-        .long       vector176,  vector177,  vector178,  vector179
-        .long       vector180,  vector181,  vector182,  vector183
-        .long       vector184,  vector185,  vector186,  vector187
-        .long       vector188,  vector189,  vector190,  vector191
-        .long       vector192,  vector193,  vector194,  vector195
-        .long       vector196,  vector197,  vector198,  vector199
-        .long       vector200,  vector201,  vector202,  vector203
-        .long       vector204,  vector205,  vector206,  vector207
-        .long       vector208,  vector209,  vector210,  vector211
-        .long       vector212,  vector213,  vector214,  vector215
-        .long       vector216,  vector217,  vector218,  vector219
-        .long       vector220,  vector221,  vector222,  vector223
-        .long       vector224,  vector225,  vector226,  vector227
-        .long       vector228,  vector229,  vector230,  vector231
-        .long       vector232,  vector233,  vector234,  vector235
-        .long       vector236,  vector237,  vector238,  vector239
-        .long       vector240,  vector241,  vector242,  vector243
-        .long       vector244,  vector245,  vector246,  vector247
-        .long       vector248,  vector249,  vector250,  vector251
-        .long       vector252,  vector253,  vector254,  vector255
-        .long       vector256,  vector257,  vector258,  vector259
-        .long       vector260,  vector261,  vector262,  vector263
-        .long       vector264,  vector265,  vector266,  vector267
-        .long       vector268,  vector269,  vector270,  vector271
-        .long       vector272,  vector273,  vector274,  vector275
-        .long       vector276,  vector277,  vector278,  vector279
-        .long       vector280,  vector281,  vector282,  vector283
-        .long       vector284,  vector285,  vector286,  vector287
-        .long       vector288,  vector289,  vector290,  vector291
-        .long       vector292,  vector293,  vector294,  vector295
-        .long       vector296,  vector297,  vector298,  vector299
-        .long       vector300,  vector301,  vector302,  vector303
-        .long       vector304,  vector305,  vector306,  vector307
-        .long       vector308,  vector309,  vector310,  vector311
-        .long       vector312,  vector313,  vector314,  vector315
-        .long       vector316,  vector317,  vector318,  vector319
-        .long       vector320,  vector321,  vector322,  vector323
-        .long       vector324,  vector325,  vector326,  vector327
-        .long       vector328,  vector329,  vector330,  vector331
-        .long       vector332,  vector333,  vector334,  vector335
-        .long       vector336,  vector337,  vector338,  vector339
-        .long       vector340,  vector341,  vector342,  vector343
-        .long       vector344,  vector345,  vector346,  vector347
-        .long       vector348,  vector349,  vector350,  vector351
-        .long       vector352,  vector353,  vector354,  vector355
-        .long       vector356,  vector357,  vector358,  vector359
-        .long       vector360,  vector361,  vector362,  vector363
-        .long       vector364,  vector365,  vector366,  vector367
-        .long       vector368,  vector369,  vector370,  vector371
-        .long       vector372,  vector373,  vector374,  vector375
-        .long       vector376,  vector377,  vector378,  vector379
-        .long       vector380,  vector381,  vector382,  vector383
-        .long       vector384,  vector385,  vector386,  vector387
-        .long       vector388,  vector389,  vector390,  vector391
-        .long       vector392,  vector393,  vector394,  vector395
-        .long       vector396,  vector397,  vector398,  vector399
-        .long       vector400,  vector401,  vector402,  vector403
-        .long       vector404,  vector405,  vector406,  vector407
-        .long       vector408,  vector409,  vector410,  vector411
-        .long       vector412,  vector413,  vector414,  vector415
-        .long       vector416,  vector417,  vector418,  vector419
-        .long       vector420,  vector421,  vector422,  vector423
-        .long       vector424,  vector425,  vector426,  vector427
-        .long       vector428,  vector429,  vector430,  vector431
-        .long       vector432,  vector433,  vector434,  vector435
-        .long       vector436,  vector437,  vector438,  vector439
-        .long       vector440,  vector441,  vector442,  vector443
-        .long       vector444,  vector445,  vector446,  vector447
-        .long       vector448,  vector449,  vector450,  vector451
-        .long       vector452,  vector453,  vector454,  vector455
-        .long       vector456,  vector457,  vector458,  vector459
-        .long       vector460,  vector461,  vector462,  vector463
-        .long       vector464,  vector465,  vector466,  vector467
-        .long       vector468,  vector469,  vector470,  vector471
-        .long       vector472,  vector473,  vector474,  vector475
-        .long       vector476,  vector477,  vector478,  vector479
-        .long       vector480,  vector481,  vector482,  vector483
-        .long       vector484,  vector485
-
-        .text
-        .align      2
-        
-        .weak       vector0,    vector1,    vector2,    vector3
-        .weak       vector4,    vector5,    vector6,    vector7
-        .weak       vector8,    vector9,    vector10,   vector11
-        .weak       vector12,   vector13,   vector14,   vector15
-        .weak       vector16,   vector17,   vector18,   vector19
-        .weak       vector20,   vector21,   vector22,   vector23
-        .weak       vector24,   vector25,   vector26,   vector27
-        .weak       vector28,   vector29,   vector30,   vector31
-        .weak       vector32,   vector33,   vector34,   vector35
-        .weak       vector36,   vector37,   vector38,   vector39
-        .weak       vector40,   vector41,   vector42,   vector43
-        .weak       vector44,   vector45,   vector46,   vector47
-        .weak       vector48,   vector49,   vector50,   vector51
-        .weak       vector52,   vector53,   vector54,   vector55
-        .weak       vector56,   vector57,   vector58,   vector59
-        .weak       vector60,   vector61,   vector62,   vector63
-        .weak       vector64,   vector65,   vector66,   vector67
-        .weak       vector68,   vector69,   vector70,   vector71
-        .weak       vector72,   vector73,   vector74,   vector75
-        .weak       vector76,   vector77,   vector78,   vector79
-        .weak       vector80,   vector81,   vector82,   vector83
-        .weak       vector84,   vector85,   vector86,   vector87
-        .weak       vector88,   vector89,   vector90,   vector91
-        .weak       vector92,   vector93,   vector94,   vector95
-        .weak       vector96,   vector97,   vector98,   vector99
-        .weak       vector100,  vector101,  vector102,  vector103
-        .weak       vector104,  vector105,  vector106,  vector107
-        .weak       vector108,  vector109,  vector110,  vector111
-        .weak       vector112,  vector113,  vector114,  vector115
-        .weak       vector116,  vector117,  vector118,  vector119
-        .weak       vector120,  vector121,  vector122,  vector123
-        .weak       vector124,  vector125,  vector126,  vector127
-        .weak       vector128,  vector129,  vector130,  vector131
-        .weak       vector132,  vector133,  vector134,  vector135
-        .weak       vector136,  vector137,  vector138,  vector139
-        .weak       vector140,  vector141,  vector142,  vector143
-        .weak       vector144,  vector145,  vector146,  vector147
-        .weak       vector148,  vector149,  vector150,  vector151
-        .weak       vector152,  vector153,  vector154,  vector155
-        .weak       vector156,  vector157,  vector158,  vector159
-        .weak       vector160,  vector161,  vector162,  vector163
-        .weak       vector164,  vector165,  vector166,  vector167
-        .weak       vector168,  vector169,  vector170,  vector171
-        .weak       vector172,  vector173,  vector174,  vector175
-        .weak       vector176,  vector177,  vector178,  vector179
-        .weak       vector180,  vector181,  vector182,  vector183
-        .weak       vector184,  vector185,  vector186,  vector187
-        .weak       vector188,  vector189,  vector190,  vector191
-        .weak       vector192,  vector193,  vector194,  vector195
-        .weak       vector196,  vector197,  vector198,  vector199
-        .weak       vector200,  vector201,  vector202,  vector203
-        .weak       vector204,  vector205,  vector206,  vector207
-        .weak       vector208,  vector209,  vector210,  vector211
-        .weak       vector212,  vector213,  vector214,  vector215
-        .weak       vector216,  vector217,  vector218,  vector219
-        .weak       vector220,  vector221,  vector222,  vector223
-        .weak       vector224,  vector225,  vector226,  vector227
-        .weak       vector228,  vector229,  vector230,  vector231
-        .weak       vector232,  vector233,  vector234,  vector235
-        .weak       vector236,  vector237,  vector238,  vector239
-        .weak       vector240,  vector241,  vector242,  vector243
-        .weak       vector244,  vector245,  vector246,  vector247
-        .weak       vector248,  vector249,  vector250,  vector251
-        .weak       vector252,  vector253,  vector254,  vector255
-        .weak       vector256,  vector257,  vector258,  vector259
-        .weak       vector260,  vector261,  vector262,  vector263
-        .weak       vector264,  vector265,  vector266,  vector267
-        .weak       vector268,  vector269,  vector270,  vector271
-        .weak       vector272,  vector273,  vector274,  vector275
-        .weak       vector276,  vector277,  vector278,  vector279
-        .weak       vector280,  vector281,  vector282,  vector283
-        .weak       vector284,  vector285,  vector286,  vector287
-        .weak       vector288,  vector289,  vector290,  vector291
-        .weak       vector292,  vector293,  vector294,  vector295
-        .weak       vector296,  vector297,  vector298,  vector299
-        .weak       vector300,  vector301,  vector302,  vector303
-        .weak       vector304,  vector305,  vector306,  vector307
-        .weak       vector308,  vector309,  vector310,  vector311
-        .weak       vector312,  vector313,  vector314,  vector315
-        .weak       vector316,  vector317,  vector318,  vector319
-        .weak       vector320,  vector321,  vector322,  vector323
-        .weak       vector324,  vector325,  vector326,  vector327
-        .weak       vector328,  vector329,  vector330,  vector331
-        .weak       vector332,  vector333,  vector334,  vector335
-        .weak       vector336,  vector337,  vector338,  vector339
-        .weak       vector340,  vector341,  vector342,  vector343
-        .weak       vector344,  vector345,  vector346,  vector347
-        .weak       vector348,  vector349,  vector350,  vector351
-        .weak       vector352,  vector353,  vector354,  vector355
-        .weak       vector356,  vector357,  vector358,  vector359
-        .weak       vector360,  vector361,  vector362,  vector363
-        .weak       vector364,  vector365,  vector366,  vector367
-        .weak       vector368,  vector369,  vector370,  vector371
-        .weak       vector372,  vector373,  vector374,  vector375
-        .weak       vector376,  vector377,  vector378,  vector379
-        .weak       vector380,  vector381,  vector382,  vector383
-        .weak       vector384,  vector385,  vector386,  vector387
-        .weak       vector388,  vector389,  vector390,  vector391
-        .weak       vector392,  vector393,  vector394,  vector395
-        .weak       vector396,  vector397,  vector398,  vector399
-        .weak       vector400,  vector401,  vector402,  vector403
-        .weak       vector404,  vector405,  vector406,  vector407
-        .weak       vector408,  vector409,  vector410,  vector411
-        .weak       vector412,  vector413,  vector414,  vector415
-        .weak       vector416,  vector417,  vector418,  vector419
-        .weak       vector420,  vector421,  vector422,  vector423
-        .weak       vector424,  vector425,  vector426,  vector427
-        .weak       vector428,  vector429,  vector430,  vector431
-        .weak       vector432,  vector433,  vector434,  vector435
-        .weak       vector436,  vector437,  vector438,  vector439
-        .weak       vector440,  vector441,  vector442,  vector443
-        .weak       vector444,  vector445,  vector446,  vector447
-        .weak       vector448,  vector449,  vector450,  vector451
-        .weak       vector452,  vector453,  vector454,  vector455
-        .weak       vector456,  vector457,  vector458,  vector459
-        .weak       vector460,  vector461,  vector462,  vector463
-        .weak       vector464,  vector465,  vector466,  vector467
-        .weak       vector468,  vector469,  vector470,  vector471
-        .weak       vector472,  vector473,  vector474,  vector475
-        .weak       vector476,  vector477,  vector478,  vector479
-        .weak       vector480,  vector481,  vector482,  vector483
-        .weak       vector484,  vector485
-
-vector0:
-vector1:
-vector2:
-vector3:
-vector4:
-vector5:
-vector6:
-vector7:
-vector8:
-vector9:
-vector10:
-vector11:
-vector12:
-vector13:
-vector14:
-vector15:
-vector16:
-vector17:
-vector18:
-vector19:
-vector20:
-vector21:
-vector22:
-vector23:
-vector24:
-vector25:
-vector26:
-vector27:
-vector28:
-vector29:
-vector30:
-vector31:
-vector32:
-vector33:
-vector34:
-vector35:
-vector36:
-vector37:
-vector38:
-vector39:
-vector40:
-vector41:
-vector42:
-vector43:
-vector44:
-vector45:
-vector46:
-vector47:
-vector48:
-vector49:
-vector50:
-vector51:
-vector52:
-vector53:
-vector54:
-vector55:
-vector56:
-vector57:
-vector58:
-vector59:
-vector60:
-vector61:
-vector62:
-vector63:
-vector64:
-vector65:
-vector66:
-vector67:
-vector68:
-vector69:
-vector70:
-vector71:
-vector72:
-vector73:
-vector74:
-vector75:
-vector76:
-vector77:
-vector78:
-vector79:
-vector80:
-vector81:
-vector82:
-vector83:
-vector84:
-vector85:
-vector86:
-vector87:
-vector88:
-vector89:
-vector90:
-vector91:
-vector92:
-vector93:
-vector94:
-vector95:
-vector96:
-vector97:
-vector98:
-vector99:
-vector100:
-vector101:
-vector102:
-vector103:
-vector104:
-vector105:
-vector106:
-vector107:
-vector108:
-vector109:
-vector110:
-vector111:
-vector112:
-vector113:
-vector114:
-vector115:
-vector116:
-vector117:
-vector118:
-vector119:
-vector120:
-vector121:
-vector122:
-vector123:
-vector124:
-vector125:
-vector126:
-vector127:
-vector128:
-vector129:
-vector130:
-vector131:
-vector132:
-vector133:
-vector134:
-vector135:
-vector136:
-vector137:
-vector138:
-vector139:
-vector140:
-vector141:
-vector142:
-vector143:
-vector144:
-vector145:
-vector146:
-vector147:
-vector148:
-vector149:
-vector150:
-vector151:
-vector152:
-vector153:
-vector154:
-vector155:
-vector156:
-vector157:
-vector158:
-vector159:
-vector160:
-vector161:
-vector162:
-vector163:
-vector164:
-vector165:
-vector166:
-vector167:
-vector168:
-vector169:
-vector170:
-vector171:
-vector172:
-vector173:
-vector174:
-vector175:
-vector176:
-vector177:
-vector178:
-vector179:
-vector180:
-vector181:
-vector182:
-vector183:
-vector184:
-vector185:
-vector186:
-vector187:
-vector188:
-vector189:
-vector190:
-vector191:
-vector192:
-vector193:
-vector194:
-vector195:
-vector196:
-vector197:
-vector198:
-vector199:
-vector200:
-vector201:
-vector202:
-vector203:
-vector204:
-vector205:
-vector206:
-vector207:
-vector208:
-vector209:
-vector210:
-vector211:
-vector212:
-vector213:
-vector214:
-vector215:
-vector216:
-vector217:
-vector218:
-vector219:
-vector220:
-vector221:
-vector222:
-vector223:
-vector224:
-vector225:
-vector226:
-vector227:
-vector228:
-vector229:
-vector230:
-vector231:
-vector232:
-vector233:
-vector234:
-vector235:
-vector236:
-vector237:
-vector238:
-vector239:
-vector240:
-vector241:
-vector242:
-vector243:
-vector244:
-vector245:
-vector246:
-vector247:
-vector248:
-vector249:
-vector250:
-vector251:
-vector252:
-vector253:
-vector254:
-vector255:
-vector256:
-vector257:
-vector258:
-vector259:
-vector260:
-vector261:
-vector262:
-vector263:
-vector264:
-vector265:
-vector266:
-vector267:
-vector268:
-vector269:
-vector270:
-vector271:
-vector272:
-vector273:
-vector274:
-vector275:
-vector276:
-vector277:
-vector278:
-vector279:
-vector280:
-vector281:
-vector282:
-vector283:
-vector284:
-vector285:
-vector286:
-vector287:
-vector288:
-vector289:
-vector290:
-vector291:
-vector292:
-vector293:
-vector294:
-vector295:
-vector296:
-vector297:
-vector298:
-vector299:
-vector300:
-vector301:
-vector302:
-vector303:
-vector304:
-vector305:
-vector306:
-vector307:
-vector308:
-vector309:
-vector310:
-vector311:
-vector312:
-vector313:
-vector314:
-vector315:
-vector316:
-vector317:
-vector318:
-vector319:
-vector320:
-vector321:
-vector322:
-vector323:
-vector324:
-vector325:
-vector326:
-vector327:
-vector328:
-vector329:
-vector330:
-vector331:
-vector332:
-vector333:
-vector334:
-vector335:
-vector336:
-vector337:
-vector338:
-vector339:
-vector340:
-vector341:
-vector342:
-vector343:
-vector344:
-vector345:
-vector346:
-vector347:
-vector348:
-vector349:
-vector350:
-vector351:
-vector352:
-vector353:
-vector354:
-vector355:
-vector356:
-vector357:
-vector358:
-vector359:
-vector360:
-vector361:
-vector362:
-vector363:
-vector364:
-vector365:
-vector366:
-vector367:
-vector368:
-vector369:
-vector370:
-vector371:
-vector372:
-vector373:
-vector374:
-vector375:
-vector376:
-vector377:
-vector378:
-vector379:
-vector380:
-vector381:
-vector382:
-vector383:
-vector384:
-vector385:
-vector386:
-vector387:
-vector388:
-vector389:
-vector390:
-vector391:
-vector392:
-vector393:
-vector394:
-vector395:
-vector396:
-vector397:
-vector398:
-vector399:
-vector400:
-vector401:
-vector402:
-vector403:
-vector404:
-vector405:
-vector406:
-vector407:
-vector408:
-vector409:
-vector410:
-vector411:
-vector412:
-vector413:
-vector414:
-vector415:
-vector416:
-vector417:
-vector418:
-vector419:
-vector420:
-vector421:
-vector422:
-vector423:
-vector424:
-vector425:
-vector426:
-vector427:
-vector428:
-vector429:
-vector430:
-vector431:
-vector432:
-vector433:
-vector434:
-vector435:
-vector436:
-vector437:
-vector438:
-vector439:
-vector440:
-vector441:
-vector442:
-vector443:
-vector444:
-vector445:
-vector446:
-vector447:
-vector448:
-vector449:
-vector450:
-vector451:
-vector452:
-vector453:
-vector454:
-vector455:
-vector456:
-vector457:
-vector458:
-vector459:
-vector460:
-vector461:
-vector462:
-vector463:
-vector464:
-vector465:
-vector466:
-vector467:
-vector468:
-vector469:
-vector470:
-vector471:
-vector472:
-vector473:
-vector474:
-vector475:
-vector476:
-vector477:
-vector478:
-vector479:
-vector480:
-vector481:
-vector482:
-vector483:
-vector484:
-vector485:
-
-        .weak       _unhandled_irq
-        .type       _unhandled_irq, @function
-_unhandled_irq:
-         b          _unhandled_irq
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC56ELxx/bam.s b/os/ports/GCC/PPC/SPC56ELxx/bam.s
deleted file mode 100644
index 623428ce3..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/bam.s
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-    2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC56ELxx/bam.s
- * @brief   SPC56ELxx boot assistant record.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* BAM record.*/
-        .section    .bam, "ax"
-#if PPC_USE_VLE
-        .long       0x015A0000
-#else
-        .long       0x005A0000
-#endif
-        .long       _reset_address
-
-        .align      2
-        .globl      _reset_address
-        .type       _reset_address, @function
-_reset_address:
-        bl          _coreinit
-        bl          _ivinit
-
-        b           _boot_address
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC56ELxx/core.s b/os/ports/GCC/PPC/SPC56ELxx/core.s
deleted file mode 100644
index 0675cd20d..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/core.s
+++ /dev/null
@@ -1,535 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC56ELxx/core.s
- * @brief   e200z4 core configuration.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-/**
- * @name   MASx registers definitions
- * @{
- */
-#define MAS0_TBLMAS_TBL         0x10000000
-#define MAS0_ESEL_MASK          0x000F0000
-#define MAS0_ESEL(n)            ((n) << 16)
-
-#define MAS1_VALID              0x80000000
-#define MAS1_IPROT              0x40000000
-#define MAS1_TID_MASK           0x00FF0000
-#define MAS1_TS                 0x00001000
-#define MAS1_TSISE_MASK         0x00000F80
-#define MAS1_TSISE_1K           0x00000000
-#define MAS1_TSISE_2K           0x00000080
-#define MAS1_TSISE_4K           0x00000100
-#define MAS1_TSISE_8K           0x00000180
-#define MAS1_TSISE_16K          0x00000200
-#define MAS1_TSISE_32K          0x00000280
-#define MAS1_TSISE_64K          0x00000300
-#define MAS1_TSISE_128K         0x00000380
-#define MAS1_TSISE_256K         0x00000400
-#define MAS1_TSISE_512K         0x00000480
-#define MAS1_TSISE_1M           0x00000500
-#define MAS1_TSISE_2M           0x00000580
-#define MAS1_TSISE_4M           0x00000600
-#define MAS1_TSISE_8M           0x00000680
-#define MAS1_TSISE_16M          0x00000700
-#define MAS1_TSISE_32M          0x00000780
-#define MAS1_TSISE_64M          0x00000800
-#define MAS1_TSISE_128M         0x00000880
-#define MAS1_TSISE_256M         0x00000900
-#define MAS1_TSISE_512M         0x00000980
-#define MAS1_TSISE_1G           0x00000A00
-#define MAS1_TSISE_2G           0x00000A80
-#define MAS1_TSISE_4G           0x00000B00
-
-#define MAS2_EPN_MASK           0xFFFFFC00
-#define MAS2_EPN(n)             ((n) & MAS2_EPN_MASK)
-#define MAS2_EBOOK              0x00000000
-#define MAS2_VLE                0x00000020
-#define MAS2_W                  0x00000010
-#define MAS2_I                  0x00000008
-#define MAS2_M                  0x00000004
-#define MAS2_G                  0x00000002
-#define MAS2_E                  0x00000001
-
-#define MAS3_RPN_MASK           0xFFFFFC00
-#define MAS3_RPN(n)             ((n) & MAS3_RPN_MASK)
-#define MAS3_U0                 0x00000200
-#define MAS3_U1                 0x00000100
-#define MAS3_U2                 0x00000080
-#define MAS3_U3                 0x00000040
-#define MAS3_UX                 0x00000020
-#define MAS3_SX                 0x00000010
-#define MAS3_UW                 0x00000008
-#define MAS3_SW                 0x00000004
-#define MAS3_UR                 0x00000002
-#define MAS3_SR                 0x00000001
-/** @} */
-
-/**
- * @name    BUCSR registers definitions
- * @{
- */
-#define BUCSR_BPEN              0x00000001
-#define BUCSR_BPRED_MASK        0x00000006
-#define BUCSR_BPRED_0           0x00000000
-#define BUCSR_BPRED_1           0x00000002
-#define BUCSR_BPRED_2           0x00000004
-#define BUCSR_BPRED_3           0x00000006
-#define BUCSR_BALLOC_MASK       0x00000030
-#define BUCSR_BALLOC_0          0x00000000
-#define BUCSR_BALLOC_1          0x00000010
-#define BUCSR_BALLOC_2          0x00000020
-#define BUCSR_BALLOC_3          0x00000030
-#define BUCSR_BALLOC_BFI        0x00000200
-/** @} */
-
-/**
- * @name    LICSR1 registers definitions
- * @{
- */
-#define LICSR1_ICE              0x00000001
-#define LICSR1_ICINV            0x00000002
-#define LICSR1_ICORG            0x00000010
-/** @} */
-
-/**
- * @name    TLB default settings
- * @{
- */
-#define TLB0_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
-#define TLB0_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
-#define TLB0_MAS2               (MAS2_EPN(0x00000000) | MAS2_VLE)
-#define TLB0_MAS3               (MAS3_RPN(0x00000000) |                     \
-                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
-                                 MAS3_UR | MAS3_SR)
-
-#define TLB1_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
-#define TLB1_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_128K)
-#define TLB1_MAS2               (MAS2_EPN(0x40000000) | MAS2_VLE)
-#define TLB1_MAS3               (MAS3_RPN(0x40000000) |                     \
-                                 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
-                                 MAS3_UR | MAS3_SR)
-
-#define TLB2_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
-#define TLB2_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
-#define TLB2_MAS2               (MAS2_EPN(0xC3F00000) | MAS2_I)
-#define TLB2_MAS3               (MAS3_RPN(0xC3F00000) |                     \
-                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
-
-#define TLB3_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
-#define TLB3_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
-#define TLB3_MAS2               (MAS2_EPN(0xFFE00000) | MAS2_I)
-#define TLB3_MAS3               (MAS3_RPN(0xFFE00000) |                     \
-                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
-
-#define TLB4_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
-#define TLB4_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
-#define TLB4_MAS2               (MAS2_EPN(0x8FF00000) | MAS2_I)
-#define TLB4_MAS3               (MAS3_RPN(0x8FF00000) |                     \
-                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
-
-#define TLB5_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
-#define TLB5_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
-#define TLB5_MAS2               (MAS2_EPN(0xFFF00000) | MAS2_I)
-#define TLB5_MAS3               (MAS3_RPN(0xFFF00000) |                     \
-                                 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
-/** @} */
-
-/**
- * @name    BUCSR default settings
- * @{
- */
-#define BUCSR_DEFAULT           (BUCSR_BPEN | BUCSR_BPRED_0 |               \
-                                 BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
-/** @} */
-
-/**
- * @name    LICSR1 default settings
- * @{
- */
-#define LICSR1_DEFAULT          (LICSR1_ICE | LICSR1_ICORG)
-/** @} */
-
-/**
- * @name   MSR register definitions
- * @{
- */
-#define MSR_UCLE                0x04000000
-#define MSR_SPE                 0x02000000
-#define MSR_WE                  0x00040000
-#define MSR_CE                  0x00020000
-#define MSR_EE                  0x00008000
-#define MSR_PR                  0x00004000
-#define MSR_FP                  0x00002000
-#define MSR_ME                  0x00001000
-#define MSR_FE0                 0x00000800
-#define MSR_DE                  0x00000200
-#define MSR_FE1                 0x00000100
-#define MSR_IS                  0x00000020
-#define MSR_DS                  0x00000010
-#define MSR_RI                  0x00000002
-/** @} */
-
-/**
- * @name   MSR default settings
- * @{
- */
-#define MSR_DEFAULT             (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
-/** @} */
-
-#if !defined(__DOXYGEN__)
-
-        .section    .coreinit, "ax"
-
-        .align      2
-_ramcode:
-        tlbwe
-        isync
-        blr
-
-        .align      2
-        .globl      _coreinit
-        .type       _coreinit, @function
-_coreinit:
-        /*
-         * Invalidating all TLBs except TLB0.
-         */
-        lis         %r3, 0
-        mtspr       625, %r3        /* MAS1 */
-        mtspr       626, %r3        /* MAS2 */
-        mtspr       627, %r3        /* MAS3 */
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-        lis         %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
-        mtspr       624, %r3        /* MAS0 */
-        tlbwe
-
-        /*
-         * TLB1 allocated to internal RAM.
-         */
-        lis         %r3, TLB1_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB1_MAS1@h
-        ori         %r3, %r3, TLB1_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB1_MAS2@h
-        ori         %r3, %r3, TLB1_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB1_MAS3@h
-        ori         %r3, %r3, TLB1_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        tlbwe
-
-        /*
-         * TLB2 allocated to internal Peripherals Bridge A.
-         */
-        lis         %r3, TLB2_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB2_MAS1@h
-        ori         %r3, %r3, TLB2_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB2_MAS2@h
-        ori         %r3, %r3, TLB2_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB2_MAS3@h
-        ori         %r3, %r3, TLB2_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        tlbwe
-
-        /*
-         * TLB3 allocated to internal Peripherals Bridge B.
-         */
-        lis         %r3, TLB3_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB3_MAS1@h
-        ori         %r3, %r3, TLB3_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB3_MAS2@h
-        ori         %r3, %r3, TLB3_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB3_MAS3@h
-        ori         %r3, %r3, TLB3_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        tlbwe
-
-        /*
-         * TLB4 allocated to on-platform peripherals.
-         */
-        lis         %r3, TLB4_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB4_MAS1@h
-        ori         %r3, %r3, TLB4_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB4_MAS2@h
-        ori         %r3, %r3, TLB4_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB4_MAS3@h
-        ori         %r3, %r3, TLB4_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        tlbwe
-
-        /*
-         * TLB5 allocated to on-platform peripherals.
-         */
-        lis         %r3, TLB5_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB5_MAS1@h
-        ori         %r3, %r3, TLB5_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB5_MAS2@h
-        ori         %r3, %r3, TLB5_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB5_MAS3@h
-        ori         %r3, %r3, TLB5_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        tlbwe
-
-        /*
-         * RAM clearing, this device requires a write to all RAM location in
-         * order to initialize the ECC detection hardware, this is going to
-         * slow down the startup but there is no way around.
-         */
-        xor         %r0, %r0, %r0
-        xor         %r1, %r1, %r1
-        xor         %r2, %r2, %r2
-        xor         %r3, %r3, %r3
-        xor         %r4, %r4, %r4
-        xor         %r5, %r5, %r5
-        xor         %r6, %r6, %r6
-        xor         %r7, %r7, %r7
-        xor         %r8, %r8, %r8
-        xor         %r9, %r9, %r9
-        xor         %r10, %r10, %r10
-        xor         %r11, %r11, %r11
-        xor         %r12, %r12, %r12
-        xor         %r13, %r13, %r13
-        xor         %r14, %r14, %r14
-        xor         %r15, %r15, %r15
-        xor         %r16, %r16, %r16
-        xor         %r17, %r17, %r17
-        xor         %r18, %r18, %r18
-        xor         %r19, %r19, %r19
-        xor         %r20, %r20, %r20
-        xor         %r21, %r21, %r21
-        xor         %r22, %r22, %r22
-        xor         %r23, %r23, %r23
-        xor         %r24, %r24, %r24
-        xor         %r25, %r25, %r25
-        xor         %r26, %r26, %r26
-        xor         %r27, %r27, %r27
-        xor         %r28, %r28, %r28
-        xor         %r29, %r29, %r29
-        xor         %r30, %r30, %r30
-        xor         %r31, %r31, %r31
-        lis         %r4, __ram_start__@h
-        ori         %r4, %r4, __ram_start__@l
-        lis         %r5, __ram_end__@h
-        ori         %r5, %r5, __ram_end__@l
-.cleareccloop:
-        cmpl        %cr0, %r4, %r5
-        bge         %cr0, .cleareccend
-        stmw        %r16, 0(%r4)
-        addi        %r4, %r4, 64
-        b           .cleareccloop
-.cleareccend:
-
-        /*
-         * Special function registers clearing, required in order to avoid
-         * possible problems with lockstep mode.
-         */
-        mtcrf       0xFF, %r31
-        mtspr       9, %r31         /* CTR     */
-        mtspr       22, %r31        /* DEC     */
-        mtspr       26, %r31        /* SRR0-1  */
-        mtspr       27, %r31
-        mtspr       54, %r31        /* DECAR   */
-        mtspr       58, %r31        /* CSRR0-1 */
-        mtspr       59, %r31
-        mtspr       61, %r31        /* DEAR    */
-        mtspr       256, %r31       /* USPRG0  */
-        mtspr       272, %r31       /* SPRG1-7 */
-        mtspr       273, %r31
-        mtspr       274, %r31
-        mtspr       275, %r31
-        mtspr       276, %r31
-        mtspr       277, %r31
-        mtspr       278, %r31
-        mtspr       279, %r31
-        mtspr       285, %r31       /* TBU     */
-        mtspr       284, %r31       /* TBL     */
-#if 0
-        mtspr       318, %r31       /* DVC1-2  */
-        mtspr       319, %r31
-#endif
-        mtspr       562, %r31       /* DBCNT */
-        mtspr       570, %r31       /* MCSRR0  */
-        mtspr       571, %r31       /* MCSRR1  */
-        mtspr       604, %r31       /* SPRG8-9 */
-        mtspr       605, %r31
-
-        /*
-         * *Finally* the TLB0 is re-allocated to flash, note, the final phase
-         * is executed from RAM.
-         */
-        lis         %r3, TLB0_MAS0@h
-        mtspr       624, %r3        /* MAS0 */
-        lis         %r3, TLB0_MAS1@h
-        ori         %r3, %r3, TLB0_MAS1@l
-        mtspr       625, %r3        /* MAS1 */
-        lis         %r3, TLB0_MAS2@h
-        ori         %r3, %r3, TLB0_MAS2@l
-        mtspr       626, %r3        /* MAS2 */
-        lis         %r3, TLB0_MAS3@h
-        ori         %r3, %r3, TLB0_MAS3@l
-        mtspr       627, %r3        /* MAS3 */
-        mflr        %r4
-        lis         %r6, _ramcode@h
-        ori         %r6, %r6, _ramcode@l
-        lis         %r7, 0x40010000@h
-        mtctr       %r7
-        lwz         %r3, 0(%r6)
-        stw         %r3, 0(%r7)
-        lwz         %r3, 4(%r6)
-        stw         %r3, 4(%r7)
-        lwz         %r3, 8(%r6)
-        stw         %r3, 8(%r7)
-        bctrl
-        mtlr        %r4
-
-        /*
-         * Branch prediction enabled.
-         */
-        li          %r3, BUCSR_DEFAULT
-        mtspr       1013, %r3       /* BUCSR */
-
-        /*
-         * Cache invalidated and then enabled.
-         */
-        li          %r3, LICSR1_ICINV
-        mtspr       1011, %r3       /* LICSR1 */
-.inv:   mfspr       %r3, 1011       /* LICSR1 */
-        andi.       %r3, %r3, LICSR1_ICINV
-        bne         .inv
-        lis         %r3, LICSR1_DEFAULT@h
-        ori         %r3, %r3, LICSR1_DEFAULT@l
-        mtspr       1011, %r3       /* LICSR1 */
-
-        blr
-
-        /*
-         * Exception vectors initialization.
-         */
-        .global     _ivinit
-        .type       _ivinit, @function
-_ivinit:
-        /* MSR initialization.*/
-        lis         %r3, MSR_DEFAULT@h
-        ori         %r3, %r3, MSR_DEFAULT@l
-        mtMSR       %r3
-
-        /* IVPR initialization.*/
-        lis         %r3, __ivpr_base__@h
-        ori         %r3, %r3, __ivpr_base__@l
-        mtIVPR      %r3
-
-        /* IVORs initialization.*/
-        lis         %r3, _unhandled_exception@h
-        ori         %r3, %r3, _unhandled_exception@l
-
-        mtspr       400, %r3        /* IVOR0-15 */
-        mtspr       401, %r3
-        mtspr       402, %r3
-        mtspr       403, %r3
-        mtspr       404, %r3
-        mtspr       405, %r3
-        mtspr       406, %r3
-        mtspr       407, %r3
-        mtspr       408, %r3
-        mtspr       409, %r3
-        mtspr       410, %r3
-        mtspr       411, %r3
-        mtspr       412, %r3
-        mtspr       413, %r3
-        mtspr       414, %r3
-        mtspr       415, %r3
-        mtspr       528, %r3        /* IVOR32-34 */
-        mtspr       529, %r3
-        mtspr       530, %r3
-
-        blr
-
-        .section    .handlers, "ax"
-
-        /*
-         * Unhandled exceptions handler.
-         */
-        .weak       _unhandled_exception
-        .type       _unhandled_exception, @function
-_unhandled_exception:
-        b           _unhandled_exception
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld
deleted file mode 100644
index 274bbb59c..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC56EL54 memory setup in LSM mode.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 768k
-    ram       : org = 0x40000000, len = 128k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        __ivpr_base__ = .;
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x800);
-        KEEP(*(.vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld
deleted file mode 100644
index 7ad744f0f..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC56EL60 memory setup in LSM mode.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 1M
-    ram       : org = 0x40000000, len = 128k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        __ivpr_base__ = .;
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x800);
-        KEEP(*(.vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld
deleted file mode 100644
index 4bc6eba19..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * SPC56EL70 memory setup in LSM mode.
- */
-__irq_stack_size__      = 0x0000; /* Not yet used.*/
-__process_stack_size__  = 0x0800;
-
-MEMORY
-{
-    flash     : org = 0x00000000, len = 2M
-    ram       : org = 0x40000000, len = 192k
-}
-
-ENTRY(_reset_address)
-
-/*
- * Derived constants.
- */
-__flash_size__          = LENGTH(flash);
-__flash_start__         = ORIGIN(flash);
-__flash_end__           = ORIGIN(flash) + LENGTH(flash);
-
-__ram_size__            = LENGTH(ram);
-__ram_start__           = ORIGIN(ram);
-__ram_end__             = ORIGIN(ram) + LENGTH(ram);
-
-SECTIONS
-{
-    . = ORIGIN(flash);
-    .boot : ALIGN(16) SUBALIGN(16)
-    {
-        __ivpr_base__ = .;
-        KEEP(*(.bam))
-        KEEP(*(.coreinit))
-        KEEP(*(.handlers))
-        KEEP(*(.crt0))
-        . = ALIGN(0x800);
-        KEEP(*(.vectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text_vle : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text_vle)
-        *(.text_vle.*)
-        *(.gnu.linkonce.t_vle.*)
-    } > flash
-
-    .text : ALIGN(16) SUBALIGN(16)
-    {
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-    } > flash
-
-    .rodata : ALIGN(16) SUBALIGN(16)
-    {
-        *(.glue_7t)
-        *(.glue_7)
-        *(.gcc*)
-        *(.rodata)
-        *(.rodata.*)
-        *(.rodata1)
-    } > flash
-
-    .sdata2 : ALIGN(16) SUBALIGN(16)
-    {
-        __sdata2_start__ = . + 0x8000;
-        *(.sdata2)
-        *(.sdata2.*)
-        *(.gnu.linkonce.s2.*)
-        *(.sbss2)
-        *(.sbss2.*)
-        *(.gnu.linkonce.sb2.*)
-    } > flash
-
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .romdata : ALIGN(16) SUBALIGN(16)
-    {
-        __romdata_start__ = .;
-    } > flash
-
-    .stacks :
-    {
-        . = ALIGN(8);
-        __irq_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(8);
-        __irq_stack_end__ = .;
-        __process_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __process_stack_size__;
-        . = ALIGN(8);
-        __process_stack_end__ = .;
-        __main_thread_stack_end__ = .;
-    } > ram
-
-    .data : AT(__romdata_start__)
-    {
-        . = ALIGN(4);
-        __data_start__ = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        __sdata_start__ = . + 0x8000;
-        *(.sdata)
-        *(.sdata.*)
-        *(.gnu.linkonce.s.*)
-        __data_end__ = .;
-    } > ram
-
-    .sbss :
-    {
-        __bss_start__ = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.gnu.linkonce.sb.*)
-        *(.scommon)
-    } > ram
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > ram
-
-    __heap_base__   = __bss_end__;
-    __heap_end__    = __ram_end__;
-}
diff --git a/os/ports/GCC/PPC/SPC56ELxx/port.mk b/os/ports/GCC/PPC/SPC56ELxx/port.mk
deleted file mode 100644
index 5a81771db..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/port.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# List of the ChibiOS/RT SPC56ELxx port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/bam.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/core.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/vectors.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
-          ${CHIBIOS}/os/ports/GCC/PPC/crt0.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
-          ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx
-
-PORTLD  = ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/ld
diff --git a/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h b/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h
deleted file mode 100644
index c09b0b875..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC56ELxx/ppcparams.h
- * @brief   PowerPC parameters for the SPC56ELxx.
- *
- * @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters
- * @ingroup PPC_SPECIFIC
- * @details This file contains the PowerPC specific parameters for the
- *          SPC56ELxx platform.
- * @{
- */
-
-#ifndef _PPCPARAMS_H_
-#define _PPCPARAMS_H_
-
-/**
- * @brief   PPC core model.
- */
-#define PPC_VARIANT                 PPC_VARIANT_e200z4
-
-/**
- * @brief   Number of writable bits in IVPR register.
- */
-#define PPC_IVPR_BITS               16
-
-/**
- * @brief   IVORx registers support.
- */
-#define PPC_SUPPORTS_IVORS          TRUE
-
-/**
- * @brief   Book E instruction set support.
- */
-#define PPC_SUPPORTS_BOOKE          TRUE
-
-/**
- * @brief   VLE instruction set support.
- */
-#define PPC_SUPPORTS_VLE            TRUE
-
-/**
- * @brief   Supports VLS Load/Store Multiple Volatile instructions.
- */
-#define PPC_SUPPORTS_VLE_MULTI      TRUE
-
-/**
- * @brief   Supports the decrementer timer.
- */
-#define PPC_SUPPORTS_DECREMENTER    TRUE
-
-#endif /* _PPCPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC56ELxx/vectors.h b/os/ports/GCC/PPC/SPC56ELxx/vectors.h
deleted file mode 100644
index 628b075b5..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/vectors.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC56ELxx/vectors.h
- * @brief   ISR vector module header.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/*===========================================================================*/
-/* Module constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of ISR vectors available.
- */
-#define VECTORS_NUMBER                      256
-
-/*===========================================================================*/
-/* Module pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Module macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-#if !defined(__DOXYGEN__)
-extern uint32_t _vectors[VECTORS_NUMBER];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _unhandled_irq(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !defined(_FROM_ASM_) */
-
-#endif /* _OSAL_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC56ELxx/vectors.s b/os/ports/GCC/PPC/SPC56ELxx/vectors.s
deleted file mode 100644
index 22a35f1d5..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/vectors.s
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    SPC56ELxx/vectors.s
- * @brief   SPC56ELxx vectors table.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#if !defined(__DOXYGEN__)
-
-        /* Software vectors table. The vectors are accessed from the IVOR4
-           handler only. In order to declare an interrupt handler just create
-           a function withe the same name of a vector, the symbol will
-           override the weak symbol declared here.*/
-        .section    .vectors, "ax"
-        .align		4
-        .globl      _vectors
-_vectors:
-        .long       vector0,    vector1,    vector2,    vector3
-        .long       vector4,    vector5,    vector6,    vector7
-        .long       vector8,    vector9,    vector10,   vector11
-        .long       vector12,   vector13,   vector14,   vector15
-        .long       vector16,   vector17,   vector18,   vector19
-        .long       vector20,   vector21,   vector22,   vector23
-        .long       vector24,   vector25,   vector26,   vector27
-        .long       vector28,   vector29,   vector30,   vector31
-        .long       vector32,   vector33,   vector34,   vector35
-        .long       vector36,   vector37,   vector38,   vector39
-        .long       vector40,   vector41,   vector42,   vector43
-        .long       vector44,   vector45,   vector46,   vector47
-        .long       vector48,   vector49,   vector50,   vector51
-        .long       vector52,   vector53,   vector54,   vector55
-        .long       vector56,   vector57,   vector58,   vector59
-        .long       vector60,   vector61,   vector62,   vector63
-        .long       vector64,   vector65,   vector66,   vector67
-        .long       vector68,   vector69,   vector70,   vector71
-        .long       vector72,   vector73,   vector74,   vector75
-        .long       vector76,   vector77,   vector78,   vector79
-        .long       vector80,   vector81,   vector82,   vector83
-        .long       vector84,   vector85,   vector86,   vector87
-        .long       vector88,   vector89,   vector90,   vector91
-        .long       vector92,   vector93,   vector94,   vector95
-        .long       vector96,   vector97,   vector98,   vector99
-        .long       vector100,  vector101,  vector102,  vector103
-        .long       vector104,  vector105,  vector106,  vector107
-        .long       vector108,  vector109,  vector110,  vector111
-        .long       vector112,  vector113,  vector114,  vector115
-        .long       vector116,  vector117,  vector118,  vector119
-        .long       vector120,  vector121,  vector122,  vector123
-        .long       vector124,  vector125,  vector126,  vector127
-        .long       vector128,  vector129,  vector130,  vector131
-        .long       vector132,  vector133,  vector134,  vector135
-        .long       vector136,  vector137,  vector138,  vector139
-        .long       vector140,  vector141,  vector142,  vector143
-        .long       vector144,  vector145,  vector146,  vector147
-        .long       vector148,  vector149,  vector150,  vector151
-        .long       vector152,  vector153,  vector154,  vector155
-        .long       vector156,  vector157,  vector158,  vector159
-        .long       vector160,  vector161,  vector162,  vector163
-        .long       vector164,  vector165,  vector166,  vector167
-        .long       vector168,  vector169,  vector170,  vector171
-        .long       vector172,  vector173,  vector174,  vector175
-        .long       vector176,  vector177,  vector178,  vector179
-        .long       vector180,  vector181,  vector182,  vector183
-        .long       vector184,  vector185,  vector186,  vector187
-        .long       vector188,  vector189,  vector190,  vector191
-        .long       vector192,  vector193,  vector194,  vector195
-        .long       vector196,  vector197,  vector198,  vector199
-        .long       vector200,  vector201,  vector202,  vector203
-        .long       vector204,  vector205,  vector206,  vector207
-        .long       vector208,  vector209,  vector210,  vector211
-        .long       vector212,  vector213,  vector214,  vector215
-        .long       vector216,  vector217,  vector218,  vector219
-        .long       vector220,  vector221,  vector222,  vector223
-        .long       vector224,  vector225,  vector226,  vector227
-        .long       vector228,  vector229,  vector230,  vector231
-        .long       vector232,  vector233,  vector234,  vector235
-        .long       vector236,  vector237,  vector238,  vector239
-        .long       vector240,  vector241,  vector242,  vector243
-        .long       vector244,  vector245,  vector246,  vector247
-        .long       vector248,  vector249,  vector250,  vector251
-        .long       vector252,  vector253,  vector254,  vector255
-
-        .text
-        .align      2
-        
-        .weak       vector0,    vector1,    vector2,    vector3
-        .weak       vector4,    vector5,    vector6,    vector7
-        .weak       vector8,    vector9,    vector10,   vector11
-        .weak       vector12,   vector13,   vector14,   vector15
-        .weak       vector16,   vector17,   vector18,   vector19
-        .weak       vector20,   vector21,   vector22,   vector23
-        .weak       vector24,   vector25,   vector26,   vector27
-        .weak       vector28,   vector29,   vector30,   vector31
-        .weak       vector32,   vector33,   vector34,   vector35
-        .weak       vector36,   vector37,   vector38,   vector39
-        .weak       vector40,   vector41,   vector42,   vector43
-        .weak       vector44,   vector45,   vector46,   vector47
-        .weak       vector48,   vector49,   vector50,   vector51
-        .weak       vector52,   vector53,   vector54,   vector55
-        .weak       vector56,   vector57,   vector58,   vector59
-        .weak       vector60,   vector61,   vector62,   vector63
-        .weak       vector64,   vector65,   vector66,   vector67
-        .weak       vector68,   vector69,   vector70,   vector71
-        .weak       vector72,   vector73,   vector74,   vector75
-        .weak       vector76,   vector77,   vector78,   vector79
-        .weak       vector80,   vector81,   vector82,   vector83
-        .weak       vector84,   vector85,   vector86,   vector87
-        .weak       vector88,   vector89,   vector90,   vector91
-        .weak       vector92,   vector93,   vector94,   vector95
-        .weak       vector96,   vector97,   vector98,   vector99
-        .weak       vector100,  vector101,  vector102,  vector103
-        .weak       vector104,  vector105,  vector106,  vector107
-        .weak       vector108,  vector109,  vector110,  vector111
-        .weak       vector112,  vector113,  vector114,  vector115
-        .weak       vector116,  vector117,  vector118,  vector119
-        .weak       vector120,  vector121,  vector122,  vector123
-        .weak       vector124,  vector125,  vector126,  vector127
-        .weak       vector128,  vector129,  vector130,  vector131
-        .weak       vector132,  vector133,  vector134,  vector135
-        .weak       vector136,  vector137,  vector138,  vector139
-        .weak       vector140,  vector141,  vector142,  vector143
-        .weak       vector144,  vector145,  vector146,  vector147
-        .weak       vector148,  vector149,  vector150,  vector151
-        .weak       vector152,  vector153,  vector154,  vector155
-        .weak       vector156,  vector157,  vector158,  vector159
-        .weak       vector160,  vector161,  vector162,  vector163
-        .weak       vector164,  vector165,  vector166,  vector167
-        .weak       vector168,  vector169,  vector170,  vector171
-        .weak       vector172,  vector173,  vector174,  vector175
-        .weak       vector176,  vector177,  vector178,  vector179
-        .weak       vector180,  vector181,  vector182,  vector183
-        .weak       vector184,  vector185,  vector186,  vector187
-        .weak       vector188,  vector189,  vector190,  vector191
-        .weak       vector192,  vector193,  vector194,  vector195
-        .weak       vector196,  vector197,  vector198,  vector199
-        .weak       vector200,  vector201,  vector202,  vector203
-        .weak       vector204,  vector205,  vector206,  vector207
-        .weak       vector208,  vector209,  vector210,  vector211
-        .weak       vector212,  vector213,  vector214,  vector215
-        .weak       vector216,  vector217,  vector218,  vector219
-        .weak       vector220,  vector221,  vector222,  vector223
-        .weak       vector224,  vector225,  vector226,  vector227
-        .weak       vector228,  vector229,  vector230,  vector231
-        .weak       vector232,  vector233,  vector234,  vector235
-        .weak       vector236,  vector237,  vector238,  vector239
-        .weak       vector240,  vector241,  vector242,  vector243
-        .weak       vector244,  vector245,  vector246,  vector247
-        .weak       vector248,  vector249,  vector250,  vector251
-        .weak       vector252,  vector253,  vector254,  vector255
-
-vector0:
-vector1:
-vector2:
-vector3:
-vector4:
-vector5:
-vector6:
-vector7:
-vector8:
-vector9:
-vector10:
-vector11:
-vector12:
-vector13:
-vector14:
-vector15:
-vector16:
-vector17:
-vector18:
-vector19:
-vector20:
-vector21:
-vector22:
-vector23:
-vector24:
-vector25:
-vector26:
-vector27:
-vector28:
-vector29:
-vector30:
-vector31:
-vector32:
-vector33:
-vector34:
-vector35:
-vector36:
-vector37:
-vector38:
-vector39:
-vector40:
-vector41:
-vector42:
-vector43:
-vector44:
-vector45:
-vector46:
-vector47:
-vector48:
-vector49:
-vector50:
-vector51:
-vector52:
-vector53:
-vector54:
-vector55:
-vector56:
-vector57:
-vector58:
-vector59:
-vector60:
-vector61:
-vector62:
-vector63:
-vector64:
-vector65:
-vector66:
-vector67:
-vector68:
-vector69:
-vector70:
-vector71:
-vector72:
-vector73:
-vector74:
-vector75:
-vector76:
-vector77:
-vector78:
-vector79:
-vector80:
-vector81:
-vector82:
-vector83:
-vector84:
-vector85:
-vector86:
-vector87:
-vector88:
-vector89:
-vector90:
-vector91:
-vector92:
-vector93:
-vector94:
-vector95:
-vector96:
-vector97:
-vector98:
-vector99:
-vector100:
-vector101:
-vector102:
-vector103:
-vector104:
-vector105:
-vector106:
-vector107:
-vector108:
-vector109:
-vector110:
-vector111:
-vector112:
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-vector114:
-vector115:
-vector116:
-vector117:
-vector118:
-vector119:
-vector120:
-vector121:
-vector122:
-vector123:
-vector124:
-vector125:
-vector126:
-vector127:
-vector128:
-vector129:
-vector130:
-vector131:
-vector132:
-vector133:
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-vector138:
-vector139:
-vector140:
-vector141:
-vector142:
-vector143:
-vector144:
-vector145:
-vector146:
-vector147:
-vector148:
-vector149:
-vector150:
-vector151:
-vector152:
-vector153:
-vector154:
-vector155:
-vector156:
-vector157:
-vector158:
-vector159:
-vector160:
-vector161:
-vector162:
-vector163:
-vector164:
-vector165:
-vector166:
-vector167:
-vector168:
-vector169:
-vector170:
-vector171:
-vector172:
-vector173:
-vector174:
-vector175:
-vector176:
-vector177:
-vector178:
-vector179:
-vector180:
-vector181:
-vector182:
-vector183:
-vector184:
-vector185:
-vector186:
-vector187:
-vector188:
-vector189:
-vector190:
-vector191:
-vector192:
-vector193:
-vector194:
-vector195:
-vector196:
-vector197:
-vector198:
-vector199:
-vector200:
-vector201:
-vector202:
-vector203:
-vector204:
-vector205:
-vector206:
-vector207:
-vector208:
-vector209:
-vector210:
-vector211:
-vector212:
-vector213:
-vector214:
-vector215:
-vector216:
-vector217:
-vector218:
-vector219:
-vector220:
-vector221:
-vector222:
-vector223:
-vector224:
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-vector226:
-vector227:
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-vector229:
-vector230:
-vector231:
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-vector233:
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-vector240:
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-vector248:
-vector249:
-vector250:
-vector251:
-vector252:
-vector253:
-vector254:
-vector255:
-
-        .weak       _unhandled_irq
-        .type       _unhandled_irq, @function
-_unhandled_irq:
-         b          _unhandled_irq
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/chcore.c b/os/ports/GCC/PPC/chcore.c
deleted file mode 100644
index 4644376cf..000000000
--- a/os/ports/GCC/PPC/chcore.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    PPC/chcore.c
- * @brief   PowerPC architecture port code.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Kernel port layer initialization.
- * @details IVOR4 and IVOR10 initialization.
- */
-void port_init(void) {
-#if PPC_SUPPORTS_IVORS
-    /* The CPU supports IVOR registers, the kernel requires IVOR4 and IVOR10
-       and the initialization is performed here.*/
-    asm volatile ("li          %%r3, _IVOR4@l       \t\n"
-                  "mtIVOR4     %%r3                 \t\n"
-                  "li          %%r3, _IVOR10@l      \t\n"
-                  "mtIVOR10    %%r3" : : : "memory");
-#endif
-}
-
-/**
- * @brief   Halts the system.
- * @details This function is invoked by the operating system when an
- *          unrecoverable error is detected (for example because a programming
- *          error in the application code that triggers an assertion while
- *          in debug mode).
- */
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void port_dummy1(void) {
-
-  asm (".global _port_switch");
-  asm ("_port_switch:");
-  asm ("subi        %sp, %sp, 80");     /* Size of the intctx structure.    */
-  asm ("mflr        %r0");
-  asm ("stw         %r0, 84(%sp)");     /* LR into the caller frame.        */
-  asm ("mfcr        %r0");
-  asm ("stw         %r0, 0(%sp)");      /* CR.                              */
-  asm ("stmw        %r14, 4(%sp)");     /* GPR14...GPR31.                   */
-  
-  asm ("stw         %sp, 12(%r4)");     /* Store swapped-out stack.         */
-  asm ("lwz         %sp, 12(%r3)");     /* Load swapped-in stack.           */
-  
-  asm ("lmw         %r14, 4(%sp)");     /* GPR14...GPR31.                   */
-  asm ("lwz         %r0, 0(%sp)");      /* CR.                              */
-  asm ("mtcr        %r0");
-  asm ("lwz         %r0, 84(%sp)");     /* LR from the caller frame.        */
-  asm ("mtlr        %r0");
-  asm ("addi        %sp, %sp, 80");     /* Size of the intctx structure.    */
-  asm ("blr");
-}
-
-/**
- * @brief   Start a thread by invoking its work function.
- * @details If the work function returns @p chThdExit() is automatically
- *          invoked.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void port_dummy2(void) {
-
-  asm (".global _port_thread_start");
-  asm ("_port_thread_start:");
-  chSysUnlock();
-  asm ("mr          %r3, %r31");        /* Thread parameter.                */
-  asm ("mtctr       %r30");
-  asm ("bctrl");                        /* Invoke thread function.          */
-  asm ("bl          chThdExit");        /* Thread termination on exit.      */
-}
-
-/** @} */
diff --git a/os/ports/GCC/PPC/chcore.h b/os/ports/GCC/PPC/chcore.h
deleted file mode 100644
index b689026e5..000000000
--- a/os/ports/GCC/PPC/chcore.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    PPC/chcore.h
- * @brief   PowerPC architecture port macros and structures.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-#if CH_DBG_ENABLE_STACK_CHECK
-#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port"
-#endif
-
-/*===========================================================================*/
-/* Port constants (common).                                                  */
-/*===========================================================================*/
-
-/* Added to make the header stand-alone when included from asm.*/
-#ifndef FALSE
-#define FALSE       0
-#endif
-#ifndef TRUE
-#define TRUE        (!FALSE)
-#endif
-
-/**
- * @name    Supported core variants
- * @{
- */
-#define PPC_VARIANT_e200z0              200
-#define PPC_VARIANT_e200z3              203
-#define PPC_VARIANT_e200z4              204
-/** @} */
-
-#include "vectors.h"
-#include "ppcparams.h"
-
-/*===========================================================================*/
-/* Port macros (common).                                                     */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters (common).                                    */
-/*===========================================================================*/
-
-/**
- * @brief   Use VLE instruction set.
- * @note    This parameter is usually set in the Makefile.
- */
-#if !defined(PPC_USE_VLE)
-#define PPC_USE_VLE                     TRUE
-#endif
-
-/**
- * @brief   Enables the use of the @p WFI instruction.
- */
-#if !defined(PPC_ENABLE_WFI_IDLE)
-#define PPC_ENABLE_WFI_IDLE             FALSE
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters (common).                                         */
-/*===========================================================================*/
-
-#if PPC_USE_VLE && !PPC_SUPPORTS_VLE
-#error "the selected MCU does not support VLE instructions set"
-#endif
-
-#if !PPC_USE_VLE && !PPC_SUPPORTS_BOOKE
-#error "the selected MCU does not support BookE instructions set"
-#endif
-
-/*===========================================================================*/
-/* Port exported info (common).                                              */
-/*===========================================================================*/
-
-/**
- * @brief   Unique macro for the implemented architecture.
- */
-#define CH_ARCHITECTURE_PPC
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "Power Architecture"
-
-/**
- * @brief   Name of the architecture variant.
- */
-#if (PPC_VARIANT == PPC_VARIANT_e200z0) || defined(__DOXYGEN__)
-#define CH_CORE_VARIANT_NAME            "e200z0"
-#elif PPC_VARIANT == PPC_VARIANT_e200z3
-#define CH_CORE_VARIANT_NAME            "e200z3"
-#elif PPC_VARIANT == PPC_VARIANT_e200z4
-#define CH_CORE_VARIANT_NAME            "e200z4"
-#else
-#error "unknown or unsupported PowerPC variant specified"
-#endif
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "GCC " __VERSION__
-
-/**
- * @brief   Port-specific information string.
- */
-#if PPC_USE_VLE
-#define CH_PORT_INFO                    "VLE mode"
-#else
-#define CH_PORT_INFO                    "Book-E mode"
-#endif
-
-/*===========================================================================*/
-/* Port implementation part (common).                                        */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-/**
- * @brief   Base type for stack and memory alignment.
- */
-typedef struct {
-  uint8_t a[8];
-} stkalign_t __attribute__((aligned(8)));
-
-/**
- * @brief   Generic PPC register.
- */
-typedef void *regppc_t;
-
-/**
- * @brief   Mandatory part of a stack frame.
- */
-struct eabi_frame {
-  regppc_t      slink;          /**< Stack back link.                       */
-  regppc_t      shole;          /**< Stack hole for LR storage.             */
-};
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- * @note    R2 and R13 are not saved because those are assumed to be immutable
- *          during the system life cycle.
- */
-struct extctx {
-  struct eabi_frame frame;
-  /* Start of the e_stmvsrrw frame (offset 8).*/
-  regppc_t      pc;
-  regppc_t      msr;
-  /* Start of the e_stmvsprw frame (offset 16).*/
-  regppc_t      cr;
-  regppc_t      lr;
-  regppc_t      ctr;
-  regppc_t      xer;
-  /* Start of the e_stmvgprw frame (offset 32).*/
-  regppc_t      r0;
-  regppc_t      r3;
-  regppc_t      r4;
-  regppc_t      r5;
-  regppc_t      r6;
-  regppc_t      r7;
-  regppc_t      r8;
-  regppc_t      r9;
-  regppc_t      r10;
-  regppc_t      r11;
-  regppc_t      r12;
-  regppc_t      padding;
- };
-
- /**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching.
- * @note    R2 and R13 are not saved because those are assumed to be immutable
- *          during the system life cycle.
- * @note    LR is stored in the caller contex so it is not present in this
- *          structure.
- */
-struct intctx {
-  regppc_t      cr;                 /* Part of it is not volatile...        */
-  regppc_t      r14;
-  regppc_t      r15;
-  regppc_t      r16;
-  regppc_t      r17;
-  regppc_t      r18;
-  regppc_t      r19;
-  regppc_t      r20;
-  regppc_t      r21;
-  regppc_t      r22;
-  regppc_t      r23;
-  regppc_t      r24;
-  regppc_t      r25;
-  regppc_t      r26;
-  regppc_t      r27;
-  regppc_t      r28;
-  regppc_t      r29;
-  regppc_t      r30;
-  regppc_t      r31;
-  regppc_t      padding;
-};
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details This structure usually contains just the saved stack pointer
- *          defined as a pointer to a @p intctx structure.
- */
-struct context {
-  struct intctx *sp;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  uint8_t *sp = (uint8_t *)workspace + wsize - sizeof(struct eabi_frame);   \
-  ((struct eabi_frame *)sp)->slink = 0;                                     \
-  ((struct eabi_frame *)sp)->shole = _port_thread_start;                    \
-  tp->p_ctx.sp = (struct intctx *)(sp - sizeof(struct intctx));             \
-  tp->p_ctx.sp->r31 = arg;                                                  \
-  tp->p_ctx.sp->r30 = pf;                                                   \
-}
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     32
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK         256
-#endif
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE()
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @details Implemented as global interrupt disable.
- */
-#define port_lock() asm volatile ("wrteei  0" : : : "memory")
-
-/**
- * @details Implemented as global interrupt enable.
- */
-#define port_unlock() asm volatile("wrteei  1" : : : "memory")
-
-/**
- * @details Implemented as global interrupt disable.
- */
-#define port_lock_from_isr() /*asm ("wrteei  0")*/
-
-/**
- * @details Implemented as global interrupt enable.
- */
-#define port_unlock_from_isr() /*asm ("wrteei  1")*/
-
-/**
- * @details Implemented as global interrupt disable.
- */
-#define port_disable() asm volatile ("wrteei  0" : : : "memory")
-
-/**
- * @details Same as @p port_disable() in this port, there is no difference
- *          between the two states.
- */
-#define port_suspend() asm volatile ("wrteei  0" : : : "memory")
-
-/**
- * @details Implemented as global interrupt enable.
- */
-#define port_enable() asm volatile ("wrteei  1" : : : "memory")
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-#else
-#define port_switch(ntp, otp) {                                             \
-  register struct intctx *sp asm ("%r1");                                   \
-  if ((stkalign_t *)(sp - 1) < otp->p_stklimit)                             \
-    chDbgPanic("stack overflow");                                           \
-  _port_switch(ntp, otp);                                                   \
-}
-#endif
-
-/**
- * @brief   Writes to a special register.
- *
- * @param[in] spr       special register number
- * @param[in] val       value to be written
- */
-#define port_mtspr(spr, val)                                                \
-  asm volatile ("mtspr %0,%1" : : "n" (spr), "r" (val))
-
-/**
- * @details This port function is implemented as inlined code for performance
- *          reasons.
- */
-#if PPC_ENABLE_WFI_IDLE
-#if !defined(port_wait_for_interrupt)
-#define port_wait_for_interrupt() {                                         \
-  asm volatile ("wait" : : : "memory");                                     \
-}
-#endif
-#else
-#define port_wait_for_interrupt()
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_init(void);
-  void port_halt(void);
-  void _port_switch(Thread *ntp, Thread *otp);
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/chtypes.h b/os/ports/GCC/PPC/chtypes.h
deleted file mode 100644
index 37f4419f6..000000000
--- a/os/ports/GCC/PPC/chtypes.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    PPC/chtypes.h
- * @brief   PowerPC architecture port system types.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-/*
- * Derived generic types.
- */
-typedef volatile int8_t     vint8_t;        /**< Volatile signed 8 bits.    */
-typedef volatile uint8_t    vuint8_t;       /**< Volatile unsigned 8 bits.  */
-typedef volatile int16_t    vint16_t;       /**< Volatile signed 16 bits.   */
-typedef volatile uint16_t   vuint16_t;      /**< Volatile unsigned 16 bits. */
-typedef volatile int32_t    vint32_t;       /**< Volatile signed 32 bits.   */
-typedef volatile uint32_t   vuint32_t;      /**< Volatile unsigned 32 bits. */
-
-/*
- * Kernel types.
- */
-typedef bool                bool_t;         /**< Fast boolean type.         */
-typedef uint8_t             tmode_t;        /**< Thread flags.              */
-typedef uint8_t             tstate_t;       /**< Thread state.              */
-typedef uint8_t             trefs_t;        /**< Thread references counter. */
-typedef uint8_t             tslices_t;      /**< Thread time slices counter.*/
-typedef uint32_t            tprio_t;        /**< Thread priority.           */
-typedef int32_t             msg_t;          /**< Inter-thread message.      */
-typedef int32_t             eventid_t;      /**< Event Id.                  */
-typedef uint32_t            eventmask_t;    /**< Event mask.                */
-typedef uint32_t            flagsmask_t;    /**< Event flags.               */
-typedef uint32_t            systime_t;      /**< System time.               */
-typedef int32_t             cnt_t;          /**< Resources counter.         */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    It uses the "packed" GCC attribute.
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/ivor.s b/os/ports/GCC/PPC/ivor.s
deleted file mode 100644
index 46dc66bf5..000000000
--- a/os/ports/GCC/PPC/ivor.s
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    PPC/ivor.s
- * @brief   Kernel ISRs.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-/*
- * Imports the PPC configuration headers.
- */
-#define _FROM_ASM_
-#include "chconf.h"
-#include "chcore.h"
-
-#if !defined(__DOXYGEN__)
-        /*
-         * INTC registers address.
-         */
-        .equ  INTC_IACKR, 0xfff48010
-        .equ  INTC_EOIR,  0xfff48018
-
-        .section    .handlers, "ax"
-
-#if PPC_SUPPORTS_DECREMENTER
-        /*
-         * _IVOR10 handler (Book-E decrementer).
-         */
-        .align      4
-        .globl      _IVOR10
-        .type       _IVOR10, @function
-_IVOR10:
-        /* Creation of the external stack frame (extctx structure).*/
-        stwu        %sp, -80(%sp)           /* Size of the extctx structure.*/
-#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
-        e_stmvsrrw  8(%sp)                  /* Saves PC, MSR.               */
-        e_stmvsprw  16(%sp)                 /* Saves CR, LR, CTR, XER.      */
-        e_stmvgprw  32(%sp)                 /* Saves GPR0, GPR3...GPR12.    */
-#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
-        stw         %r0, 32(%sp)            /* Saves GPR0.                  */
-        mfSRR0      %r0
-        stw         %r0, 8(%sp)             /* Saves PC.                    */
-        mfSRR1      %r0
-        stw         %r0, 12(%sp)            /* Saves MSR.                   */
-        mfCR        %r0
-        stw         %r0, 16(%sp)            /* Saves CR.                    */
-        mfLR        %r0
-        stw         %r0, 20(%sp)            /* Saves LR.                    */
-        mfCTR       %r0
-        stw         %r0, 24(%sp)            /* Saves CTR.                   */
-        mfXER       %r0
-        stw         %r0, 28(%sp)            /* Saves XER.                   */
-        stw         %r3, 36(%sp)            /* Saves GPR3...GPR12.          */
-        stw         %r4, 40(%sp)
-        stw         %r5, 44(%sp)
-        stw         %r6, 48(%sp)
-        stw         %r7, 52(%sp)
-        stw         %r8, 56(%sp)
-        stw         %r9, 60(%sp)
-        stw         %r10, 64(%sp)
-        stw         %r11, 68(%sp)
-        stw         %r12, 72(%sp)
-#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
-
-        /* Reset DIE bit in TSR register.*/
-        lis         %r3, 0x0800             /* DIS bit mask.                */
-        mtspr       336, %r3                /* TSR register.                */
-
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl          dbg_check_enter_isr
-        bl          dbg_check_lock_from_isr
-#endif
-        bl          chSysTimerHandlerI
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl          dbg_check_unlock_from_isr
-        bl          dbg_check_leave_isr
-#endif
-
-        /* System tick handler invocation.*/
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl          dbg_check_lock
-#endif
-        bl          chSchIsPreemptionRequired
-        cmpli       cr0, %r3, 0
-        beq         cr0, _ivor_exit
-        bl          chSchDoReschedule
-        b           _ivor_exit
-#endif /* PPC_SUPPORTS_DECREMENTER */
-
-        /*
-         * _IVOR4 handler (Book-E external interrupt).
-         */
-        .align      4
-        .globl      _IVOR4
-        .type       _IVOR4, @function
-_IVOR4:
-        /* Creation of the external stack frame (extctx structure).*/
-        stwu        %sp, -80(%sp)           /* Size of the extctx structure.*/
-#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
-        e_stmvsrrw  8(%sp)                  /* Saves PC, MSR.               */
-        e_stmvsprw  16(%sp)                 /* Saves CR, LR, CTR, XER.      */
-        e_stmvgprw  32(%sp)                 /* Saves GPR0, GPR3...GPR12.    */
-#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
-        stw         %r0, 32(%sp)            /* Saves GPR0.                  */
-        mfSRR0      %r0
-        stw         %r0, 8(%sp)             /* Saves PC.                    */
-        mfSRR1      %r0
-        stw         %r0, 12(%sp)            /* Saves MSR.                   */
-        mfCR        %r0
-        stw         %r0, 16(%sp)            /* Saves CR.                    */
-        mfLR        %r0
-        stw         %r0, 20(%sp)            /* Saves LR.                    */
-        mfCTR       %r0
-        stw         %r0, 24(%sp)            /* Saves CTR.                   */
-        mfXER       %r0
-        stw         %r0, 28(%sp)            /* Saves XER.                   */
-        stw         %r3, 36(%sp)            /* Saves GPR3...GPR12.          */
-        stw         %r4, 40(%sp)
-        stw         %r5, 44(%sp)
-        stw         %r6, 48(%sp)
-        stw         %r7, 52(%sp)
-        stw         %r8, 56(%sp)
-        stw         %r9, 60(%sp)
-        stw         %r10, 64(%sp)
-        stw         %r11, 68(%sp)
-        stw         %r12, 72(%sp)
-#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
-
-        /* Software vector address from the INTC register.*/
-        lis         %r3, INTC_IACKR@h
-        ori         %r3, %r3, INTC_IACKR@l  /* IACKR register address.      */
-        lwz         %r3, 0(%r3)             /* IACKR register value.        */
-        lwz         %r3, 0(%r3)
-        mtCTR       %r3                     /* Software handler address.    */
-
-#if PPC_USE_IRQ_PREEMPTION
-        /* Allows preemption while executing the software handler.*/
-        wrteei      1
-#endif
-
-        /* Exectes the software handler.*/
-        bctrl
-
-#if PPC_USE_IRQ_PREEMPTION
-        /* Prevents preemption again.*/
-        wrteei      0
-#endif
-
-        /* Informs the INTC that the interrupt has been served.*/
-        mbar        0
-        lis         %r3, INTC_EOIR@h
-        ori         %r3, %r3, INTC_EOIR@l
-        stw         %r3, 0(%r3)             /* Writing any value should do. */
-
-        /* Verifies if a reschedule is required.*/
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl          dbg_check_lock
-#endif
-        bl          chSchIsPreemptionRequired
-        cmpli       cr0, %r3, 0
-        beq         cr0, _ivor_exit
-        bl          chSchDoReschedule
-
-        /* Context restore.*/
-        .globl      _ivor_exit
-_ivor_exit:
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl          dbg_check_unlock
-#endif
-#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
-        e_lmvgprw   32(%sp)                 /* Restores GPR0, GPR3...GPR12. */
-        e_lmvsprw   16(%sp)                 /* Restores CR, LR, CTR, XER.   */
-        e_lmvsrrw   8(%sp)                  /* Restores PC, MSR.            */
-#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
-        lwz         %r3, 36(%sp)            /* Restores GPR3...GPR12.       */
-        lwz         %r4, 40(%sp)
-        lwz         %r5, 44(%sp)
-        lwz         %r6, 48(%sp)
-        lwz         %r7, 52(%sp)
-        lwz         %r8, 56(%sp)
-        lwz         %r9, 60(%sp)
-        lwz         %r10, 64(%sp)
-        lwz         %r11, 68(%sp)
-        lwz         %r12, 72(%sp)
-        lwz         %r0, 8(%sp)
-        mtSRR0      %r0                     /* Restores PC.                 */
-        lwz         %r0, 12(%sp)
-        mtSRR1      %r0                     /* Restores MSR.                */
-        lwz         %r0, 16(%sp)
-        mtCR        %r0                     /* Restores CR.                 */
-        lwz         %r0, 20(%sp)
-        mtLR        %r0                     /* Restores LR.                 */
-        lwz         %r0, 24(%sp)
-        mtCTR       %r0                     /* Restores CTR.                */
-        lwz         %r0, 28(%sp)
-        mtXER       %r0                     /* Restores XER.                */
-        lwz         %r0, 32(%sp)            /* Restores GPR0.               */
-#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
-        addi        %sp, %sp, 80            /* Back to the previous frame.  */
-        rfi
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/port.dox b/os/ports/GCC/PPC/port.dox
deleted file mode 100644
index 9ea2c0449..000000000
--- a/os/ports/GCC/PPC/port.dox
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup PPC Power Architecture
- * @details Power Architecture port for the GCC compiler.
- *
- * @section PPC_INTRO Introduction
- * This port supports cores implementing a 32 bits Power Architecture.
- *
- * @section PPC_STATES Mapping of the System States in the Power Architecture port
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the
- * PowerPC port:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). Interrupts are enabled.
- * - <b>Suspended</b>. Interrupts are disabled.
- * - <b>Disabled</b>. Interrupts are disabled. This state is equivalent to the
- *   Suspended state because there are no fast interrupts in this architecture.
- * - <b>Sleep</b>. This state is entered with the execution of the specific
- *   instruction @p <b>wait</b>.
- * - <b>S-Locked</b>. Interrupts are disabled.
- * - <b>I-Locked</b>. This state is equivalent to the SRI state, the
- *   @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
- *   order to formally change state because this may change).
- * - <b>Serving Regular Interrupt</b>. Normal interrupt service code.
- * - <b>Serving Fast Interrupt</b>. Not present in this architecture.
- * - <b>Serving Non-Maskable Interrupt</b>. The PowerPC has several non
- *   maskable interrupt sources that can be associated to this state.
- * - <b>Halted</b>. Implemented as an infinite loop with interrupts disabled.
- * .
- * @section PPC_NOTES The PowerPC port notes
- * The PowerPC port is organized as follow:
- * - The @p main() function is invoked in privileged mode.
- * - Each thread has a private stack with extra storage for interrupts
- *   servicing.
- * - The Book-E Decrementer Timer, mapped on IVOR10, is used for system tick.
- * - Interrupt nesting is not currently supported.
- * .
- * @ingroup gcc
- */
-
-/**
- * @defgroup PPC_CONF Configuration Options
- * @details PowerPC Configuration Options. The PowerPC port allows some
- * architecture-specific configurations settings that can be overridden by
- * redefining them in @p chconf.h. Usually there is no need to change the
- * default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
- *   by an interrupt handler between the @p extctx and @p intctx
- *   structures.
- *   The default for this value is @p 128 bytes, this space is allocated for
- *   each thread so be careful in order to not waste precious RAM space.
- * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
- *   thread. Usually there is no need to change this value unless inserting
- *   code in the IDLE thread hook macro.
- * - @p ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the @p <b>wait</b>
- *   instruction from within the idle loop. This is defaulted to 0 because
- *   it can create problems with some debuggers. Setting this option to 1
- *   reduces the system power requirements.
- * .
- * @ingroup PPC
- */
-
-/**
- * @defgroup PPC_CORE Core Port Implementation
- * @brief PowerPC specific port code, structures and macros.
- *
- * @ingroup PPC
- */
-
-/**
- * @defgroup PPC_STARTUP Startup Support
- * @brief 
- * @details PPC startup code support. ChibiOS/RT provides its own generic
- * startup file for the PowerPC port.
- * Of course it is not mandatory to use it but care should be taken about the
- * startup phase details.
- *
- * @section PPC_STARTUP_1 Startup Process
- * The startup process, as implemented, is the following:
- * -# The stacks pointer is initialized into the area defined in the linker
- *    script.
- * -# The IVPR register is setup according to the linker script.
- * -# The R2 and R13 registers are set to pointer to the SDA areas according
- *    to the EABI specification.
- * -# An early initialization routine @p hwinit0 is invoked, if the symbol is
- *    not defined then an empty default routine is executed (weak symbol).
- * -# DATA and BSS segments are initialized.
- * -# A late initialization routine @p hwinit1 is invoked, if the symbol not
- *    defined then an empty default routine is executed (weak symbol).<br>
- *    This late initialization function is also the proper place for a
- *    @a bootloader, if your application requires one.
- * -# The @p main() function is invoked with the parameters @p argc and @p argv
- *    set to zero.
- * -# Should the @p main() function return a branch is performed to the weak
- *    symbol @p _main_exit_handler. The default code is an endless empty loop.
- * .
- * @section PPC_STARTUP_2 Expected linker symbols
- * The startup code starts at the symbol @p _boot_address and expects the
- * following symbols to be defined in the linker script:
- * - @p __ram_end__ RAM end location +1.
- * - @p __sdata2_start__ small constants data area
- * - @p __sdata_start__ small variables data area
- * - @p __romdata_start__ address of the data segment source read only data.
- * - @p __data_start__ data segment start location.
- * - @p __data_end__ data segment end location +1.
- * - @p __bss_start__ BSS start location.
- * - @p __bss_end__ BSS end location +1.
- * - @p __ivpr_base__ IVPR register initialization address.
- * .
- * @ingroup PPC
- */
-
-/**
- * @defgroup PPC_SPECIFIC Specific Implementations
- * @details Platform-specific port code.
- *
- * @ingroup PPC
- */
diff --git a/os/ports/GCC/PPC/rules.mk b/os/ports/GCC/PPC/rules.mk
deleted file mode 100644
index 555a6f46b..000000000
--- a/os/ports/GCC/PPC/rules.mk
+++ /dev/null
@@ -1,195 +0,0 @@
-# PPC makefile scripts and rules.
-
-# Output directory and files
-ifeq ($(BUILDDIR),)
-  BUILDDIR = build
-endif
-ifeq ($(BUILDDIR),.)
-  BUILDDIR = build
-endif
-OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
-           $(BUILDDIR)/$(PROJECT).mot $(BUILDDIR)/$(PROJECT).bin \
-           $(BUILDDIR)/$(PROJECT).dmp
-
-# Automatic compiler options
-OPT = $(USE_OPT)
-COPT = $(USE_COPT)
-CPPOPT = $(USE_CPPOPT)
-ifeq ($(USE_LINK_GC),yes)
-  OPT += -ffunction-sections -fdata-sections
-endif
-
-# VLE option handling.
-ifeq ($(USE_VLE),yes)
-  DDEFS += -DPPC_USE_VLE=1
-  DADEFS += -DPPC_USE_VLE=1
-  MCU += -mvle
-else
-  DDEFS += -DPPC_USE_VLE=0
-  DADEFS += -DPPC_USE_VLE=0
-endif
-
-# Source files groups and paths
-SRC	      = $(CSRC)$(CPPSRC)
-SRCPATHS  = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC)))
-
-# Various directories
-OBJDIR    = $(BUILDDIR)/obj
-LSTDIR    = $(BUILDDIR)/lst
-
-# Object files groups
-COBJS     = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o)))
-CPPOBJS   = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o)))
-ASMOBJS   = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
-ASMXOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
-OBJS	  = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS)
-
-# Paths
-IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
-LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
-
-# Macros
-DEFS    = $(DDEFS) $(UDEFS)
-ADEFS   = $(DADEFS) $(UADEFS)
-
-# Libs
-LIBS    = $(DLIBS) $(ULIBS)
-
-# Various settings
-MCFLAGS   = -mcpu=$(MCU)
-ODFLAGS	  = -x --syms
-ASFLAGS   = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
-ASXFLAGS  = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
-CFLAGS    = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
-CPPFLAGS  = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
-ifeq ($(USE_LINK_GC),yes)
-GCLDFLAGS = ,--gc-sections
-else
-GCLDFLAGS =
-endif
-ifneq ($(USE_LDOPT),)
-XLDFLAGS  =,$(USE_LDOPT)
-else
-XLDFLAGS  =
-endif
-LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch$(GCLDFLAGS)$(XLDFLAGS) $(LLIBDIR)
-
-# Generate dependency information
-CFLAGS   += -MD -MP -MF .dep/$(@F).d
-CPPFLAGS += -MD -MP -MF .dep/$(@F).d
-
-# Paths where to search for sources
-VPATH     = $(SRCPATHS)
-
-#
-# Makefile rules
-#
-
-all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK
-
-MAKE_ALL_RULE_HOOK:
-
-$(OBJS): | $(BUILDDIR)
-
-$(BUILDDIR) $(OBJDIR) $(LSTDIR):
-ifneq ($(USE_VERBOSE_COMPILE),yes)
-	@echo Compiler Options
-	@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
-	@echo
-endif
-	mkdir -p $(OBJDIR)
-	mkdir -p $(LSTDIR)
-
-$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
-endif
-
-$(COBJS) : $(OBJDIR)/%.o : %.c Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
-endif
-
-$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
-endif
-
-$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo 
-	$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
-else
-	@echo Compiling $(<F)
-	@$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
-endif
-
-%.elf: $(OBJS) $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	@echo
-	$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
-else
-	@echo Linking $@
-	@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
-endif
-
-%.hex: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(HEX) $< $@
-else
-	@echo Creating $@
-	@$(HEX) $< $@
-endif
-
-%.mot: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(MOT) $< $@
-else
-	@echo Creating $@
-	@$(MOT) $< $@
-endif
-
-%.bin: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(BIN) $< $@
-else
-	@echo Creating $@
-	@$(BIN) $< $@
-endif
-
-%.dmp: %.elf $(LDSCRIPT)
-ifeq ($(USE_VERBOSE_COMPILE),yes)
-	$(OD) $(ODFLAGS) $< > $@
-else
-	@echo Creating $@
-	@$(OD) $(ODFLAGS) $< > $@
-	@echo
-	@$(SZ) $<
-	@echo
-	@echo Done
-endif
-
-clean:
-	@echo Cleaning
-	-rm -fR .dep $(BUILDDIR)
-	@echo
-	@echo Done
-
-#
-# Include the dependency files, should be the last of the makefile
-#
--include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
-
-# *** EOF ***
diff --git a/os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld b/os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld
deleted file mode 100644
index 87ea5bb93..000000000
--- a/os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*
- * R5F562N8xxxx memory setup (code executed from RAM)
- */
-__user_stack_size__     = 0x0; /* not used */
-__irq_stack_size__      = 0x0400;
-
-MEMORY
-{
-    ramjumps : org = 0x00000000, len = 0x20
-    flash :    org = 0x00000020, len = 64k-0x20
-    ram :      org = 0x00010000, len = 32k
-    fvectors : org = 0xFFFFFF80, len = 0x80
-}
-
-__ram_start__           = ORIGIN(ram);
-__ram_size__            = LENGTH(ram);
-__ram_end__             = __ram_start__ + __ram_size__;
-__flash_start__         = ORIGIN(flash);
-__flash_size__          = LENGTH(flash);
-
-SECTIONS
-{
-    . = 0;
-    _text = .;
-
-    ramjumps : ALIGN(4)
-    {
-        KEEP(*(.ramjumps))
-    } > ramjumps
-
-    rvectors : ALIGN(4)
-    {
-        KEEP(*(.rvectors))
-    } > flash
-
-    constructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE(__init_array_end = .);
-    } > flash
-
-    destructors : ALIGN(4) SUBALIGN(4)
-    {
-        PROVIDE(__fini_array_start = .);
-        KEEP(*(.fini_array))
-        KEEP(*(SORT(.fini_array.*)))
-        PROVIDE(__fini_array_end = .);
-    } > flash
-
-    .text : ALIGN(4)
-    {
-/*        KEEP(*(.text.startup.*))*/
-        *(.text P .stub .text.* .gnu.linkonce.t.*)
-        *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)
-        *(.rodata1)
-    } > flash
-/*
-    .eh_frame_hdr :
-    {
-        *(.eh_frame_hdr)
-    } > flash
-
-    .eh_frame : ONLY_IF_RO
-    {
-        *(.eh_frame)
-    } > flash
-
-    .textalign : ONLY_IF_RO
-    {
-        . = ALIGN(8);
-    } > flash
-*/
-    . = ALIGN(4);
-    _etext = .;
-    _textdata = _etext;
-
-    .noinit (NOLOAD) :
-    {
-    } > ram
-
-    .stacks :
-    {
-        . = ALIGN(4);
-        __user_stack_base__ = .;
-        . += __user_stack_size__;
-        . = ALIGN(4);
-        __user_stack_end__ = .;
-        __irq_stack_base__ = .;
-        __main_thread_stack_base__ = .;
-        . += __irq_stack_size__;
-        . = ALIGN(4);
-        __main_thread_stack_end__ = .;
-        PROVIDE(__irq_stack_end__ = .);
-    } > ram
-
-    .data :
-    {
-        . = ALIGN(4);
-        PROVIDE(_data = .);
-        *(.data D .data.* .gnu.linkonce.d.*)
-        . = ALIGN(4);
-        *(.data1)
-        . = ALIGN(4);
-        *(.ramtext)
-        . = ALIGN(4);
-        *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)
-        . = ALIGN(4);
-        PROVIDE(_edata = .);
-/*    } > flash*/
-    } > ram AT > flash
-
-    .bss :
-    {
-        . = ALIGN(4);
-        PROVIDE(_bss_start = .);
-        *(.sbss .sbss.*)
-        *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)
-        . = ALIGN(4);
-        *(COMMON)
-        . = ALIGN(4);
-
-        . = ALIGN(32);
-        *(.etherdesc)
-        PROVIDE(_bss_end = .);
-    } > ram
-
-    PROVIDE(end = .);
-    _end             = .;
-
-    ___heap_base__   = _end;
-    ___heap_end__    = __ram_end__;
-
-    fvectors : ALIGN(4)
-    {
-        KEEP(*(.fvectors))
-    } > fvectors
-
-}
diff --git a/os/ports/GCC/RX/RX62N/rxparams.h b/os/ports/GCC/RX/RX62N/rxparams.h
deleted file mode 100644
index 26843f63d..000000000
--- a/os/ports/GCC/RX/RX62N/rxparams.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-
-                                      ---
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes ChibiOS/RT, without being obliged to provide
-    the source code for any proprietary components. See the file exception.txt
-    for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file    GCC/RX/RX62N/rxparams.h
- * @brief   Renesas RX parameters for the RX62N.
- *
- * @defgroup RX_RX62N Specific Parameters
- * @ingroup RX_SPECIFIC
- * @details This file contains the RX specific parameters for the
- *          RX62N platform.
- * @{
- */
-
-#ifndef _RXPARAMS_H_
-#define _RXPARAMS_H_
-
-/**
- * @brief   RX core model.
- */
-#define RX_MODEL                RX62N
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define RX_HAS_MPU              TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define RX_HAS_FPU              TRUE
-
-#endif /* _RXPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/RX/RX62N/vectors.c b/os/ports/GCC/RX/RX62N/vectors.c
deleted file mode 100644
index 1ea079dc0..000000000
--- a/os/ports/GCC/RX/RX62N/vectors.c
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    GCC/RX/RX62N/vectors.c
- * @brief   Interrupt vectors for the RX family.
- *
- * @defgroup RX_RX62N_VECTORS RX62N Interrupt Vectors
- * @ingroup RX_SPECIFIC
- * @details Interrupt vectors for the RX family.
- * @{
- */
-#include "ch.h"
-#include "hal.h"
-
-
-/**
- * @brief   Unhandled exceptions handler.
- * @details Any undefined exception vector points to this function by default.
- *          This function simply stops the system into an infinite loop.
- *
- * @notapi
- */
-#if !defined(__DOXYGEN__)
-__attribute__ ((naked))
-#endif
-void _unhandled_exception(void) {
-
-  while (1);
-}
-
-#if !defined(__DOXYGEN__)
-/* hardware vectors */
-extern void ResetHandler(void);
-void NMIHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void UndefHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void FPUHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void SVHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-/* relocatable vectors */
-void Excep_BRK(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_BUSERR(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_FCU_FCUERR(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_FCU_FRDYI(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_ICU_SWINT(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_CMTU0_CMT0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_CMTU0_CMT1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_CMTU1_CMT2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_CMTU1_CMT3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_ETHER_EINT(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_USB0_D0FIFO0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_USB0_D1FIFO0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_USB0_USBI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_USB1_D0FIFO1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_USB1_D1FIFO1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_USB1_USBI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RSPI0_SPEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RSPI0_SPRI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RSPI0_SPTI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RSPI0_SPII0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RSPI1_SPEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RSPI1_SPRI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RSPI1_SPTI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RSPI1_SPII1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_CAN0_ERS0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_CAN0_RXF0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_CAN0_TXF0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_CAN0_RXM0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_CAN0_TXM0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RTC_PRD(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RTC_CUP(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ11(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ12(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ13(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ14(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_IRQ15(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_USB_USBR0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_USB_USBR1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RTC_ALM(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_WDT_WOVI(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_AD0_ADI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_AD1_ADI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_S12AD_ADI12(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU0_TGIA0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU0_TGIB0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU0_TGIC0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU0_TGID0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU0_TCIV0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU0_TGIE0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU0_TGIF0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU1_TGIA1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU1_TGIB1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU1_TCIV1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU1_TCIU1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU2_TGIA2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU2_TGIB2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU2_TCIV2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU2_TCIU2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU3_TGIA3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU3_TGIB3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU3_TGIC3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU3_TGID3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU3_TCIV3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU4_TGIA4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU4_TGIB4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU4_TGIC4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU4_TGID4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU4_TCIV4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU5_TCIU5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU5_TCIV5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU5_TCIW5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU6_TGIA6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU6_TGIB6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU6_TGIC6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU6_TGID6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU6_TCIV6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU6_TGIE6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU6_TGIF6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU7_TGIA7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU7_TGIB7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU7_TCIV7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU7_TCIU7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU8_TGIA8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU8_TGIB8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU8_TCIV8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU8_TCIU8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU9_TGIA9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU9_TGIB9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU9_TGIC9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU9_TGID9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU9_TCIV9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU10_TGIA10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU10_TGIB10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU10_TGIC10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU10_TGID10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU10_TCIV10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU11_TCIU11(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU11_TCIV11(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_MTU11_TCIW11(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_POE_OEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_POE_OEI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_POE_OEI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_POE_OEI4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR0_CMI0A(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR0_CMI0B(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR0_OV0I(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR1_CMI1A(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR1_CMI1B(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR1_OV1I(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR2_CMI2A(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR2_CMI2B(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR2_OV2I(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR3_CMI3A(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR3_CMI3B(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_TMR3_OV3I(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_DMACA_DMAC0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_DMACA_DMAC1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_DMACA_DMAC2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_DMACA_DMAC3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_EXDMAC_DMAC0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_EXDMAC_DMAC1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI0_ERI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI0_RXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI0_TXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI0_TEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI1_ERI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI1_RXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI1_TXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI1_TEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI2_ERI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI2_RXI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI2_TXI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI2_TEI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI3_ERI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI3_RXI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI3_TXI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI3_TEI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI5_ERI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI5_RXI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI5_TXI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI5_TEI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI6_ERI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI6_RXI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI6_TXI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_SCI6_TEI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RIIC0_EEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RIIC0_RXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RIIC0_TXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RIIC0_TEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RIIC1_EEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RIIC1_RXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RIIC1_TXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-void Excep_RIIC1_TEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
-#endif
-
-#if defined(RAMRUN)
-__attribute__((naked,section(".ramjumps")))
-void ramjumps(void)
-{
-  asm volatile ("bra.a _ResetHandler\n\t\
-                 bra.a _NMIHandler\n\t\
-                 bra.a _UndefHandler\n\t\
-                 bra.a _FPUHandler\n\t\
-                 bra.a _SVHandler\n\t");
-}
-#endif
-
-const unsigned long _hardwareVectors[] __attribute__ ((section (".fvectors"))) = {
-/* 0xFFFFFF80 - reserved */
-    0, 0, 0, 0,
-    0, 0, 0, 0,
-    0, 0, 0, 0,
-    0, 0, 0, 0,
-    0, 0, 0, 0,
-/* 0xFFFFFFD0 - Supervisor Instruction */
-    16,
-/* 0xFFFFFFD4 - reserved */
-    0, 0,
-/* 0xFFFFFFDC  Undefined Instruction */
-    8,
-/* 0xFFFFFFE0 - reserved */
-    0,
-/* 0xFFFFFFE4 - Floating Point */
-    12,
-/* 0xFFFFFFE8 - reserved */
-    0, 0, 0, 0,
-/* 0xFFFFFFF8 - NMI */
-    4,
-/* 0xFFFFFFFC - RESET */
-    0
-};
-
-void (*_relocatableVectors[256])(void) __attribute__ ((section (".rvectors"))) = {
-  Excep_BRK,                   // 0
-  _unhandled_exception,        // 1
-  _unhandled_exception,        // 2
-  _unhandled_exception,        // 3
-  _unhandled_exception,        // 4
-  _unhandled_exception,        // 5
-  _unhandled_exception,        // 6
-  _unhandled_exception,        // 7
-  _unhandled_exception,        // 8
-  _unhandled_exception,        // 9
-  _unhandled_exception,        // 10
-  _unhandled_exception,        // 11
-  _unhandled_exception,        // 12
-  _unhandled_exception,        // 13
-  _unhandled_exception,        // 14
-  _unhandled_exception,        // 15
-  Excep_BUSERR,                // 16
-  _unhandled_exception,        // 17
-  _unhandled_exception,        // 18
-  _unhandled_exception,        // 19
-  _unhandled_exception,        // 20
-  Excep_FCU_FCUERR,            // 21
-  _unhandled_exception,        // 22
-  Excep_FCU_FRDYI,             // 23
-  _unhandled_exception,        // 24
-  _unhandled_exception,        // 25
-  _unhandled_exception,        // 26
-  Excep_ICU_SWINT,             // 27
-  Excep_CMTU0_CMT0,            // 28
-  Excep_CMTU0_CMT1,            // 29
-  Excep_CMTU1_CMT2,            // 30
-  Excep_CMTU1_CMT3,            // 31
-  Excep_ETHER_EINT,            // 32
-  _unhandled_exception,        // 33
-  _unhandled_exception,        // 34
-  _unhandled_exception,        // 35
-  Excep_USB0_D0FIFO0,          // 36
-  Excep_USB0_D1FIFO0,          // 37
-  Excep_USB0_USBI0,            // 38
-  _unhandled_exception,        // 39
-  Excep_USB1_D0FIFO1,          // 40
-  Excep_USB1_D1FIFO1,          // 41
-  Excep_USB1_USBI1,            // 42
-  _unhandled_exception,        // 43
-  Excep_RSPI0_SPEI0,           // 44
-  Excep_RSPI0_SPRI0,           // 45
-  Excep_RSPI0_SPTI0,           // 46
-  Excep_RSPI0_SPII0,           // 47
-  Excep_RSPI1_SPEI1,           // 48
-  Excep_RSPI1_SPRI1,           // 49
-  Excep_RSPI1_SPTI1,           // 50
-  Excep_RSPI1_SPII1,           // 51
-  _unhandled_exception,        // 52
-  _unhandled_exception,        // 53
-  _unhandled_exception,        // 54
-  _unhandled_exception,        // 55
-  Excep_CAN0_ERS0,             // 56
-  Excep_CAN0_RXF0,             // 57
-  Excep_CAN0_TXF0,             // 58
-  Excep_CAN0_RXM0,             // 59
-  Excep_CAN0_TXM0,             // 60
-  _unhandled_exception,        // 61
-  Excep_RTC_PRD,               // 62
-  Excep_RTC_CUP,               // 63
-  Excep_IRQ0,                  // 64
-  Excep_IRQ1,                  // 65
-  Excep_IRQ2,                  // 66
-  Excep_IRQ3,                  // 67
-  Excep_IRQ4,                  // 68
-  Excep_IRQ5,                  // 69
-  Excep_IRQ6,                  // 70
-  Excep_IRQ7,                  // 71
-  Excep_IRQ8,                  // 72
-  Excep_IRQ9,                  // 73
-  Excep_IRQ10,                 // 74
-  Excep_IRQ11,                 // 75
-  Excep_IRQ12,                 // 76
-  Excep_IRQ13,                 // 77
-  Excep_IRQ14,                 // 78
-  Excep_IRQ15,                 // 79
-  _unhandled_exception,        // 80
-  _unhandled_exception,        // 81
-  _unhandled_exception,        // 82
-  _unhandled_exception,        // 83
-  _unhandled_exception,        // 84
-  _unhandled_exception,        // 85
-  _unhandled_exception,        // 86
-  _unhandled_exception,        // 87
-  _unhandled_exception,        // 88
-  _unhandled_exception,        // 89
-  Excep_USB_USBR0,             // 90
-  Excep_USB_USBR1,             // 91
-  Excep_RTC_ALM,               // 92
-  _unhandled_exception,        // 93
-  _unhandled_exception,        // 94
-  _unhandled_exception,        // 95
-  Excep_WDT_WOVI,              // 96
-  _unhandled_exception,        // 97
-  Excep_AD0_ADI0,              // 98
-  Excep_AD1_ADI1,              // 99
-  _unhandled_exception,        // 100
-  _unhandled_exception,        // 101
-  Excep_S12AD_ADI12,           // 102
-  _unhandled_exception,        // 103
-  _unhandled_exception,        // 104
-  _unhandled_exception,        // 105
-  _unhandled_exception,        // 106
-  _unhandled_exception,        // 107
-  _unhandled_exception,        // 108
-  _unhandled_exception,        // 109
-  _unhandled_exception,        // 110
-  _unhandled_exception,        // 111
-  _unhandled_exception,        // 112
-  _unhandled_exception,        // 113
-  Excep_MTU0_TGIA0,            // 114
-  Excep_MTU0_TGIB0,            // 115
-  Excep_MTU0_TGIC0,            // 116
-  Excep_MTU0_TGID0,            // 117
-  Excep_MTU0_TCIV0,            // 118
-  Excep_MTU0_TGIE0,            // 119
-  Excep_MTU0_TGIF0,            // 120
-  Excep_MTU1_TGIA1,            // 121
-  Excep_MTU1_TGIB1,            // 122
-  Excep_MTU1_TCIV1,            // 123
-  Excep_MTU1_TCIU1,            // 124
-  Excep_MTU2_TGIA2,            // 125
-  Excep_MTU2_TGIB2,            // 126
-  Excep_MTU2_TCIV2,            // 127
-  Excep_MTU2_TCIU2,            // 128
-  Excep_MTU3_TGIA3,            // 129
-  Excep_MTU3_TGIB3,            // 130
-  Excep_MTU3_TGIC3,            // 131
-  Excep_MTU3_TGID3,            // 132
-  Excep_MTU3_TCIV3,            // 133
-  Excep_MTU4_TGIA4,            // 134
-  Excep_MTU4_TGIB4,            // 135
-  Excep_MTU4_TGIC4,            // 136
-  Excep_MTU4_TGID4,            // 137
-  Excep_MTU4_TCIV4,            // 138
-  Excep_MTU5_TCIU5,            // 139
-  Excep_MTU5_TCIV5,            // 140
-  Excep_MTU5_TCIW5,            // 141
-  Excep_MTU6_TGIA6,            // 142
-  Excep_MTU6_TGIB6,            // 143
-  Excep_MTU6_TGIC6,            // 144
-  Excep_MTU6_TGID6,            // 145
-  Excep_MTU6_TCIV6,            // 146
-  Excep_MTU6_TGIE6,            // 147
-  Excep_MTU6_TGIF6,            // 148
-  Excep_MTU7_TGIA7,            // 149
-  Excep_MTU7_TGIB7,            // 150
-  Excep_MTU7_TCIV7,            // 151
-  Excep_MTU7_TCIU7,            // 152
-  Excep_MTU8_TGIA8,            // 153
-  Excep_MTU8_TGIB8,            // 154
-  Excep_MTU8_TCIV8,            // 155
-  Excep_MTU8_TCIU8,            // 156
-  Excep_MTU9_TGIA9,            // 157
-  Excep_MTU9_TGIB9,            // 158
-  Excep_MTU9_TGIC9,            // 159
-  Excep_MTU9_TGID9,            // 160
-  Excep_MTU9_TCIV9,            // 161
-  Excep_MTU10_TGIA10,          // 162
-  Excep_MTU10_TGIB10,          // 163
-  Excep_MTU10_TGIC10,          // 164
-  Excep_MTU10_TGID10,          // 165
-  Excep_MTU10_TCIV10,          // 166
-  Excep_MTU11_TCIU11,          // 167
-  Excep_MTU11_TCIV11,          // 168
-  Excep_MTU11_TCIW11,          // 169
-  Excep_POE_OEI1,              // 170
-  Excep_POE_OEI2,              // 171
-  Excep_POE_OEI3,              // 172
-  Excep_POE_OEI4,              // 173
-  Excep_TMR0_CMI0A,            // 174
-  Excep_TMR0_CMI0B,            // 175
-  Excep_TMR0_OV0I,             // 176
-  Excep_TMR1_CMI1A,            // 177
-  Excep_TMR1_CMI1B,            // 178
-  Excep_TMR1_OV1I,             // 179
-  Excep_TMR2_CMI2A,            // 180
-  Excep_TMR2_CMI2B,            // 181
-  Excep_TMR2_OV2I,             // 182
-  Excep_TMR3_CMI3A,            // 183
-  Excep_TMR3_CMI3B,            // 184
-  Excep_TMR3_OV3I,             // 185
-  _unhandled_exception,        // 186
-  _unhandled_exception,        // 187
-  _unhandled_exception,        // 188
-  _unhandled_exception,        // 189
-  _unhandled_exception,        // 190
-  _unhandled_exception,        // 191
-  _unhandled_exception,        // 192
-  _unhandled_exception,        // 193
-  _unhandled_exception,        // 194
-  _unhandled_exception,        // 195
-  _unhandled_exception,        // 196
-  _unhandled_exception,        // 197
-  Excep_DMACA_DMAC0,           // 198
-  Excep_DMACA_DMAC1,           // 199
-  Excep_DMACA_DMAC2,           // 200
-  Excep_DMACA_DMAC3,           // 201
-  Excep_EXDMAC_DMAC0,          // 202
-  Excep_EXDMAC_DMAC1,          // 203
-  _unhandled_exception,        // 204
-  _unhandled_exception,        // 205
-  _unhandled_exception,        // 206
-  _unhandled_exception,        // 207
-  _unhandled_exception,        // 208
-  _unhandled_exception,        // 209
-  _unhandled_exception,        // 210
-  _unhandled_exception,        // 211
-  _unhandled_exception,        // 212
-  _unhandled_exception,        // 213
-  Excep_SCI0_ERI0,             // 214
-  Excep_SCI0_RXI0,             // 215
-  Excep_SCI0_TXI0,             // 216
-  Excep_SCI0_TEI0,             // 217
-  Excep_SCI1_ERI1,             // 218
-  Excep_SCI1_RXI1,             // 219
-  Excep_SCI1_TXI1,             // 220
-  Excep_SCI1_TEI1,             // 221
-  Excep_SCI2_ERI2,             // 222
-  Excep_SCI2_RXI2,             // 223
-  Excep_SCI2_TXI2,             // 224
-  Excep_SCI2_TEI2,             // 225
-  Excep_SCI3_ERI3,             // 226
-  Excep_SCI3_RXI3,             // 227
-  Excep_SCI3_TXI3,             // 228
-  Excep_SCI3_TEI3,             // 229
-  _unhandled_exception,        // 230
-  _unhandled_exception,        // 231
-  _unhandled_exception,        // 232
-  _unhandled_exception,        // 233
-  Excep_SCI5_ERI5,             // 234
-  Excep_SCI5_RXI5,             // 235
-  Excep_SCI5_TXI5,             // 236
-  Excep_SCI5_TEI5,             // 237
-  Excep_SCI6_ERI6,             // 238
-  Excep_SCI6_RXI6,             // 239
-  Excep_SCI6_TXI6,             // 240
-  Excep_SCI6_TEI6,             // 241
-  _unhandled_exception,        // 242
-  _unhandled_exception,        // 243
-  _unhandled_exception,        // 244
-  _unhandled_exception,        // 245
-  Excep_RIIC0_EEI0,            // 246
-  Excep_RIIC0_RXI0,            // 247
-  Excep_RIIC0_TXI0,            // 248
-  Excep_RIIC0_TEI0,            // 249
-  Excep_RIIC1_EEI1,            // 250
-  Excep_RIIC1_RXI1,            // 251
-  Excep_RIIC1_TXI1,            // 252
-  Excep_RIIC1_TEI1,            // 253
-  _unhandled_exception,        // 254
-  _unhandled_exception,        // 255
-};
-
-/** @} */
diff --git a/os/ports/GCC/RX/chcore.c b/os/ports/GCC/RX/chcore.c
deleted file mode 100644
index 004fdf36e..000000000
--- a/os/ports/GCC/RX/chcore.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-
-                                      ---
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes ChibiOS/RT, without being obliged to provide
-    the source code for any proprietary components. See the file exception.txt
-    for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file    GCC/RX/chcore.c
- * @brief   Renesas RX architecture port code.
- *
- * @addtogroup RX_CORE
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief RX initialization code.
- *
- * @note This function is usually empty.
- */
-void port_init(void){
-}
-
-/**
- * @brief Disables all the interrupt sources.
- *
- * @note Of course non maskable interrupt sources are not included.
- */
-void port_disable() {
-
-  asm volatile ("clrpsw  I                                          \n\t");
-}
-
-/**
- * @brief Disables the interrupt sources that are not supposed to preempt the kernel.
- */
-void port_suspend(void) {
-
-  asm volatile ("clrpsw  I                                          \n\t");
-}
-
-/**
- * @brief Enables all the interrupt sources.
- */
-void port_enable(void) {
-
-  asm volatile ("setpsw  I                                          \n\t");
-}
-
-/**
- * @brief Check if interrupts are enabled.
- */
-bool_t port_enabled(void) {
-  uint32_t psw;
-
-  asm volatile("mvfc     PSW,%0                                     \n\t"
-    : "=r" (psw) : : );
-  return psw & (1<<16) ? true : false;
-}
-
-/**
- * @brief   Halts the system.
- * @details This function is invoked by the operating system when an
- *          unrecoverable error is detected (for example because a programming
- *          error in the application code that triggers an assertion while in
- *          debug mode).
- * @note    The function is declared as a weak symbol, it is possible to
- *          redefine it in your application code.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/**
- * @brief Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- * is responsible for the context switch between 2 threads.
- *
- * @param ntp the thread to be switched in
- * @param otp the thread to be switched out
- * @note The implementation of this code affects <b>directly</b> the context
- *       switch performance so optimize here as much as you can.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked, weak))
-#endif
-void port_switch(Thread *ntp, Thread *otp) {
-/*
-  register struct intctx *sp asm ("sp");
-  asm volatile ("pushm   r6-r13                                     \n\t");
-  otp->p_ctx.sp = sp;
-  sp = ntp->p_ctx.sp;
-  asm volatile ("popm    r6-r13                                     \n\t");
-*/
-#if !defined(CH_CURRP_REGISTER_CACHE)
-  asm volatile ("pushm   r6-r13                                     \n\t"
-                "mov.l   r0,12[r2]                                  \n\t"
-                "mov.l   12[r1],r0                                  \n\t"
-                "popm    r6-r13                                     \n\t");
-#else
-  asm volatile ("pushm   r6-r12                                     \n\t"
-                "mov     r0,12[r2]                                  \n\t"
-                "mov     12[r1],r0                                  \n\t"
-                "popm    r6-r12                                     \n\t");
-#endif
-  asm volatile ("rts                                                \n\t");
-}
-
-/**
- * @brief   Start a thread by invoking its work function.
- * @details If the work function returns @p chThdExit() is automatically
- *          invoked.
- */
-void _port_thread_start(void) {
-
-  chSysUnlock();
-  asm volatile ("mov.l   r11,r1                                     \n\t"
-                "jsr     r12                                        \n\t"
-                "bsr     _chThdExit                                 \n\t");
-}
-
-/** @} */
diff --git a/os/ports/GCC/RX/chcore.h b/os/ports/GCC/RX/chcore.h
deleted file mode 100644
index 849f2fcca..000000000
--- a/os/ports/GCC/RX/chcore.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-
-                                      ---
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes ChibiOS/RT, without being obliged to provide
-    the source code for any proprietary components. See the file exception.txt
-    for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file    RX/chcore.h
- * @brief   Renesas RX port macros and structures.
- *
- * @addtogroup RX_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-/*===========================================================================*/
-/* Port constants.                                                           */
-/*===========================================================================*/
-
-/* Inclusion of the RX implementation specific parameters.*/
-#include "rxparams.h"
-
-/* RX model check, only RX62N is supported right now.*/
-#if (RX_MODEL == RX62N)
-#else
-#error "unknown or unsupported RX model"
-#endif
-
-/*===========================================================================*/
-/* Port statically derived parameters.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port macros.                                                              */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * If enabled allows the idle thread to enter a low power mode.
- */
-#ifndef RX_ENABLE_WFI_IDLE
-#define RX_ENABLE_WFI_IDLE              FALSE
-#endif
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-/**
- * Macro defining a generic RX architecture.
- */
-#define CH_ARCHITECTURE_RX
-
-/**
- * @brief   Name of the implemented architecture.
- * @note    The value is for documentation only, the real value changes
- *          depending on the selected architecture, the possible values are:
- *          - "ARM7".
- *          - "ARM9".
- *          .
- */
-#define CH_ARCHITECTURE_NAME            "RX"
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "GCC " __VERSION__
-
-/*===========================================================================*/
-/* Port implementation part (common).                                        */
-/*===========================================================================*/
-
-/**
- * @brief   32 bits stack and memory alignment enforcement.
- */
-typedef uint32_t stkalign_t;
-
-/**
- * @brief   Generic RX register.
- */
-typedef void *regrx_t;
-
-/**
- * @brief Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- * preemption-capable interrupt handler. These registers are caller-saved in GCC.
- */
-struct extctx {
-#if defined(RX_USE_FPU)
-    regrx_t     fpsw;
-#endif
-    regrx_t     acc_hi;
-    regrx_t     acc_lo;
-    regrx_t     r1;
-    regrx_t     r2;
-    regrx_t     r3;
-    regrx_t     r4;
-    regrx_t     r5;
-    regrx_t     r14;
-    regrx_t     r15;
-    regrx_t     psw;
-    regrx_t     pc;
-};
-
-/**
- * @brief System saved context.
- * @details This structure represents the inner stack frame during a context
- * switching. These registers are callee-saved in GCC.
- */
-struct intctx {
-    regrx_t     r6;
-    regrx_t     r7;
-    regrx_t     r8;
-    regrx_t     r9;
-    regrx_t     r10;
-    regrx_t     r11;
-    regrx_t     r12;
-#ifndef CH_CURRP_REGISTER_CACHE
-/* -mint-register=1 - reserves R13 */
-    regrx_t     r13;
-#else
-#warning CH_CURRP_REGISTER_CACHE feature is not tested.
-#endif
-    regrx_t     pc;
-};
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- *          structure representing the stack pointer at context switch time.
- */
-struct context {
-  struct intctx *sp;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                            \
-    tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace +                   \
-                    wsize -    sizeof(struct intctx));                        \
-    tp->p_ctx.sp->r11 = arg;                                                  \
-    tp->p_ctx.sp->r12 = pf;                                                   \
-    tp->p_ctx.sp->pc = _port_thread_start;                                    \
-}
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     20
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- *          This value can be zero on those architecture where there is a
- *          separate interrupt stack and the stack space between @p intctx and
- *          @p extctx is known to be zero.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-/*#define PORT_INT_REQUIRED_STACK 64*/
-#define PORT_INT_REQUIRED_STACK 256
-#endif
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                           \
-                                   sizeof(struct intctx) +                    \
-                                   sizeof(struct extctx) +                    \
-                                  (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#if !defined(RX_USE_FPU)
-#define PORT_IRQ_PROLOGUE() {                                                 \
-    asm volatile ("pushm   r14-r15                                  \n\t"     \
-                  "pushm   r1-r5                                    \n\t"     \
-                  "mvfaclo r1                                       \n\t"     \
-                  "push    r1                                       \n\t"     \
-                  "mvfachi r1                                       \n\t"     \
-                  "push    r1                                       \n\t");   \
-}
-#else
-#define PORT_IRQ_PROLOGUE() {                                                 \
-    asm volatile ("pushm   r14-r15                                  \n\t"     \
-                  "pushm   r1-r5                                    \n\t"     \
-                  "mvfaclo r1                                       \n\t"     \
-                  "push    r1                                       \n\t"     \
-                  "mvfachi r1                                       \n\t"     \
-                  "push    r1                                       \n\t"     \
-                  "pushc   FPSW                                     \n\t");   \
-}
-#endif
-/* #define PORT_IRQ_PROLOGUE() */
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#if !defined(RX_USE_FPU)
-#define PORT_IRQ_EPILOGUE() {                                                 \
-    dbg_check_lock();                                                         \
-    if (chSchIsPreemptionRequired()) {                                        \
-      asm volatile ("mvtipl  #0                                     \n\t");   \
-      chSchDoReschedule();                                                    \
-    }                                                                         \
-    dbg_check_unlock();                                                       \
-    asm volatile ("pop     r1                                       \n\t"     \
-                  "mvtachi r1                                       \n\t"     \
-                  "pop     r1                                       \n\t"     \
-                  "mvtaclo r1                                       \n\t"     \
-                  "popm    r1-r5                                    \n\t"     \
-                  "popm    r14-r15                                  \n\t"     \
-                  "rte                                              \n\t");   \
-}
-#else
-#define PORT_IRQ_EPILOGUE() {                                                 \
-    dbg_check_lock();                                                         \
-    if (chSchIsPreemptionRequired()) {                                        \
-      asm volatile ("mvtipl  #0                                     \n\t");   \
-      chSchDoReschedule();                                                    \
-    }                                                                         \
-    asm volatile ("popc    FPSW                                     \n\t"     \
-                  "pop     r1                                       \n\t"     \
-                  "mvtachi r1                                       \n\t"     \
-                  "pop     r1                                       \n\t"     \
-                  "mvtaclo r1                                       \n\t"     \
-                  "popm    r1-r5                                    \n\t"     \
-                  "popm    r14-r15                                  \n\t"     \
-                  "rte                                              \n\t");   \
-}
-#endif
-
-/**
- * IRQ handler function declaration.
- * @note @p id can be a function name or a vector number depending on the
- *       port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void __attribute__((naked)) id(void)
-
-/**
- * @brief Kernel-unlock action.
- * @details Usually this function just disables interrupts but may perform more
- * actions.
- */
-#define port_lock() asm volatile ("clrpsw    I                      \n\t")
-
-/**
- * @brief Kernel-unlock action.
- * @details Usually this function just disables interrupts but may perform more
- * actions.
- */
-#define port_unlock() asm volatile ("setpsw  I                      \n\t")
-
-/**
- * @brief Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- * interrupt handlers. The implementation is architecture dependent, in its
- * simplest form it is void.
- */
-#define port_lock_from_isr()
-
-/**
- * @brief Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- * handlers. The implementation is architecture dependent, in its simplest form
- * it is void.
- */
-#define port_unlock_from_isr()
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- * @note    This port function is implemented as inlined code for performance
- *          reasons.
- */
-#if RX_ENABLE_WFI_IDLE == TRUE
-#define port_wait_for_interrupt() {                                           \
-  asm volatile ("wait");                                                      \
-}
-#else
-#define port_wait_for_interrupt()
-#endif
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_init(void);
-  void port_disable(void);
-  void port_suspend(void);
-  void port_enable(void);
-  bool_t port_enabled(void);
-  void port_halt(void);
-  void port_switch(Thread *ntp, Thread *otp);
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/RX/chtypes.h b/os/ports/GCC/RX/chtypes.h
deleted file mode 100644
index 35a21e13d..000000000
--- a/os/ports/GCC/RX/chtypes.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-
-                                      ---
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes ChibiOS/RT, without being obliged to provide
-    the source code for any proprietary components. See the file exception.txt
-    for full details of how and when the exception can be applied.
-*/
-
-/**
- * @file    RX/chtypes.h
- * @brief   RX architecture port system types.
- *
- * @addtogroup RX_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint32_t        tprio_t;        /**< Thread priority.               */
-typedef int32_t         msg_t;          /**< Inter-thread message.          */
-typedef int32_t         eventid_t;      /**< Event Id.                      */
-typedef uint32_t        eventmask_t;    /**< Event mask.                    */
-typedef uint32_t        flagsmask_t;    /**< Event flags.                   */
-typedef uint32_t        systime_t;      /**< System time.                   */
-typedef int32_t         cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    It uses the "packed" GCC attribute.
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/RX/crt0.c b/os/ports/GCC/RX/crt0.c
deleted file mode 100644
index 13d823df7..000000000
--- a/os/ports/GCC/RX/crt0.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RX/crt0.c
- * @brief   Generic RX600 startup file for ChibiOS/RT.
- *
- * @addtogroup RX_STARTUP
- * @{
- */
-
-#include "ch.h"
-
-typedef void (*funcp_t)(void);
-typedef funcp_t * funcpp_t;
-extern void (*_relocatableVectors[256])(void) __attribute__ ((section (".rvectors")));
-extern void __early_init(void);
-
-#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
-
-/*===========================================================================*/
-/**
- * @name    Startup settings
- * @{
- */
-/*===========================================================================*/
-
-/**
- * @brief   Stack segments initialization switch.
- */
-#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
-#define CRT0_STACKS_FILL_PATTERN    0x55555555
-#endif
-
-/**
- * @brief   Stack segments initialization switch.
- */
-#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
-#define CRT0_INIT_STACKS            TRUE
-#endif
-
-/**
- * @brief   DATA segment initialization switch.
- */
-#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
-#define CRT0_INIT_DATA              TRUE
-#endif
-
-/**
- * @brief   BSS segment initialization switch.
- */
-#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
-#define CRT0_INIT_BSS               TRUE
-#endif
-
-/**
- * @brief   Constructors invocation switch.
- */
-#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
-#define CRT0_CALL_CONSTRUCTORS      FALSE
-#endif
-
-/**
- * @brief   Destructors invocation switch.
- */
-#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
-#define CRT0_CALL_DESTRUCTORS       FALSE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/**
- * @name    Symbols from the scatter file
- */
-/*===========================================================================*/
-
-/**
- * @brief   Main stack lower boundary.
- * @details This symbol must be exported by the linker script and represents
- *          the main stack lower boundary.
- */
-extern uint32_t __user_stack_base__;
-
-/**
- *
- * @brief   Main stack initial position.
- * @details This symbol must be exported by the linker script and represents
- *          the main stack initial position.
- */
-extern uint32_t __user_stack_end__;
-
-/**
- * @brief   Process stack lower boundary.
- * @details This symbol must be exported by the linker script and represents
- *          the process stack lower boundary.
- */
-extern uint32_t __irq_stack_base__;
-
-/**
- * @brief   Process stack initial position.
- * @details This symbol must be exported by the linker script and represents
- *          the process stack initial position.
- */
-extern uint32_t __irq_stack_end__;
-
-/**
- * @brief   ROM image of the data segment start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _textdata;
-
-/**
- * @brief   Data segment start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _data;
-
-/**
- * @brief   Data segment end.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _edata;
-
-/**
- * @brief   BSS segment start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _bss_start;
-
-/**
- * @brief   BSS segment end.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern uint32_t _bss_end;
-
-/**
- * @brief   Constructors table start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __init_array_start;
-
-/**
- * @brief   Constructors table end.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __init_array_end;
-
-/**
- * @brief   Destructors table start.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __fini_array_start;
-
-/**
- * @brief   Destructors table end.
- * @pre     The symbol must be aligned to a 32 bits boundary.
- */
-extern funcp_t __fini_array_end;
-
-/** @} */
-
-/**
- * @brief   Application @p main() function.
- */
-extern void main(void);
-
-/**
- * @brief   Early initialization.
- * @details This hook is invoked immediately after the stack initialization
- *          and before the DATA and BSS segments initialization. The
- *          default behavior is to do nothing.
- * @note    This function is a weak symbol.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void __early_init(void) {}
-
-/**
- * @brief   Late initialization.
- * @details This hook is invoked after the DATA and BSS segments
- *          initialization and before any static constructor. The
- *          default behavior is to do nothing.
- * @note    This function is a weak symbol.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void __late_init(void) {}
-
-/**
- * @brief   Default @p main() function exit handler.
- * @details This handler is invoked or the @p main() function exit. The
- *          default behavior is to enter an infinite loop.
- * @note    This function is a weak symbol.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak, naked))
-#endif
-void _default_exit(void) {
-  while (1)
-    ;
-}
-
-/**
- * @brief   Reset vector.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((naked))
-#endif
-void ResetHandler(void) {
-
-  /* Disable interrupts, ipl=0, supervisor mode, select USP stack */
-  asm volatile ("mvtc     #0x00000000, PSW");
-
-  /* Set interrupt stack pointer */
-  asm volatile ("mvtc     #__irq_stack_end__, ISP");
-  /* Set relocatable vectors base */
-  asm volatile ("mvtc     #__relocatableVectors, INTB");
-
-  __early_init();
-
-#if RX_USE_FPU
-  asm volatile ("mvtc     #0x100, FPSW");
-#endif
-
-#if defined(CRT0_INIT_STACKS)
-  /* Stack initialization.*/
-  asm volatile ("mov      %0, R2" : : "i" (CRT0_STACKS_FILL_PATTERN));
-  asm volatile ("mov      #__irq_stack_base__, R1");
-  asm volatile ("mov      #__irq_stack_end__-__irq_stack_base__, R3");
-  asm volatile ("sstr.b");
-#endif
-
-  /* copy initialized data */
-#if defined(CRT0_INIT_DATA)
-  asm volatile ("mov      #_data, R1");
-  asm volatile ("mov      #_textdata, R2");
-  asm volatile ("mov      #_edata-_data, R3");
-  asm volatile ("smovf");
-#endif
-
-#if defined(CRT0_INIT_BSS)
-  /* clear bss section */
-  asm volatile ("mov      #0, R2");
-  asm volatile ("mov      #_bss_start, R1");
-  asm volatile ("mov      #_bss_end-_bss_start, R3");
-  asm volatile ("sstr.b");
-#endif
-
-#if CRT0_CALL_CONSTRUCTORS
-  /* Constructors invocation.*/
-  {
-    funcpp_t fpp = &__init_array_start;
-    while (fpp < &__init_array_end) {
-      (*fpp)();
-      fpp++;
-    }
-  }
-#endif
-
-  /* Enable interrupts */
-  asm volatile ("setpsw   I");
-
-  /* Invoking application main() function.*/
-  main();
-
-
-#if CRT0_CALL_DESTRUCTORS
-  /* Destructors invocation.*/
-  {
-    funcpp_t fpp = &__fini_array_start;
-    while (fpp < &__fini_array_end) {
-      (*fpp)();
-      fpp++;
-    }
-  }
-#endif
-
-  /* Invoking the exit handler.*/
-  _default_exit();
-}
-
-/** @} */
diff --git a/os/ports/GCC/SIMIA32/chcore.c b/os/ports/GCC/SIMIA32/chcore.c
deleted file mode 100644
index c8f0f36f4..000000000
--- a/os/ports/GCC/SIMIA32/chcore.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @addtogroup SIMIA32_CORE
- * @{
- */
-
-#include <stdlib.h>
-
-#include "ch.h"
-#include "hal.h"
-
-/**
- * Performs a context switch between two threads.
- * @param otp the thread to be switched out
- * @param ntp the thread to be switched in
- */
-__attribute__((used))
-static void __dummy(Thread *ntp, Thread *otp) {
-  (void)ntp; (void)otp;
-
-  asm volatile (
-#if defined(WIN32)
-                ".globl @port_switch@8                          \n\t"
-                "@port_switch@8:"
-#elif defined(__APPLE__)
-                ".globl _port_switch                            \n\t"
-                "_port_switch:"
-#else
-                ".globl port_switch                             \n\t"
-                "port_switch:"
-#endif
-                "push    %ebp                                   \n\t"
-                "push    %esi                                   \n\t"
-                "push    %edi                                   \n\t"
-                "push    %ebx                                   \n\t"
-                "movl    %esp, 12(%edx)                         \n\t"
-                "movl    12(%ecx), %esp                         \n\t"
-                "pop     %ebx                                   \n\t"
-                "pop     %edi                                   \n\t"
-                "pop     %esi                                   \n\t"
-                "pop     %ebp                                   \n\t"
-                "ret");
-}
-
-/**
- * Halts the system. In this implementation it just exits the simulation.
- */
-__attribute__((fastcall))
-void port_halt(void) {
-
-  exit(2);
-}
-
-/**
- * @brief   Start a thread by invoking its work function.
- * @details If the work function returns @p chThdExit() is automatically
- *          invoked.
- */
-__attribute__((cdecl, noreturn))
-void _port_thread_start(msg_t (*pf)(void *), void *p) {
-
-  chSysUnlock();
-  chThdExit(pf(p));
-  while(1);
-}
-
-/** @} */
diff --git a/os/ports/GCC/SIMIA32/chcore.h b/os/ports/GCC/SIMIA32/chcore.h
deleted file mode 100644
index 5161688da..000000000
--- a/os/ports/GCC/SIMIA32/chcore.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @addtogroup SIMIA32_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-#if CH_DBG_ENABLE_STACK_CHECK
-#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port"
-#endif
-
-/**
- * Macro defining the a simulated architecture into x86.
- */
-#define CH_ARCHITECTURE_SIMIA32
-
-/**
- * Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "Simulator"
-
-/**
- * @brief   Name of the architecture variant (optional).
- */
-#define CH_CORE_VARIANT_NAME            "x86 (integer only)"
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "GCC " __VERSION__
-
-/**
- * @brief   Port-specific information string.
- */
-#define CH_PORT_INFO                    "No preemption"
-
-/**
- * 16 bytes stack alignment.
- */
-typedef struct {
-  uint8_t a[16];
-} stkalign_t __attribute__((aligned(16)));
-
-/**
- * Generic x86 register.
- */
-typedef void *regx86;
-
-/**
- * Interrupt saved context.
- * This structure represents the stack frame saved during a preemption-capable
- * interrupt handler.
- */
-struct extctx {
-};
-
-/**
- * System saved context.
- * @note In this demo the floating point registers are not saved.
- */
-struct intctx {
-  regx86  ebx;
-  regx86  edi;
-  regx86  esi;
-  regx86  ebp;
-  regx86  eip;
-};
-
-/**
- * Platform dependent part of the @p Thread structure.
- * This structure usually contains just the saved stack pointer defined as a
- * pointer to a @p intctx structure.
- */
-struct context {
-  struct intctx volatile *esp;
-};
-
-#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a)
-
-/* Darwin requires the stack to be aligned to a 16-byte boundary at
- * the time of a call instruction (in case the called function needs
- * to save MMX registers). This aligns to 'mod' module 16, so that we'll end
- * up with the right alignment after pushing the args. */
-#define AALIGN(p, mask, mod) p = (void *)((((uintptr_t)(p) - mod) & ~mask) + mod)
-
-/**
- * Platform dependent part of the @p chThdCreateI() API.
- * This code usually setup the context switching frame represented by a
- * @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                      \
-  uint8_t *esp = (uint8_t *)workspace + wsize;                          \
-  APUSH(esp, 0);                                                        \
-  uint8_t *savebp = esp;                                                \
-  AALIGN(esp, 15, 8);                                                   \
-  APUSH(esp, arg);                                                      \
-  APUSH(esp, pf);                                                       \
-  APUSH(esp, 0);                                                        \
-  esp -= sizeof(struct intctx);                                         \
-  ((struct intctx *)esp)->eip = _port_thread_start;                     \
-  ((struct intctx *)esp)->ebx = 0;                                      \
-  ((struct intctx *)esp)->edi = 0;                                      \
-  ((struct intctx *)esp)->esi = 0;                                      \
-  ((struct intctx *)esp)->ebp = savebp;                                 \
-  tp->p_ctx.esp = (struct intctx *)esp;                                 \
-}
-
-/**
- * Stack size for the system idle thread.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     256
-#endif
-
-/**
- * Per-thread stack overhead for interrupts servicing, it is used in the
- * calculation of the correct working area size.
- * It requires stack space because the simulated "interrupt handlers" can
- * invoke host library functions inside so it better have a lot of space.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK         16384
-#endif
-
-/**
- * Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
- /**
-  * Computes the thread working area global size.
-  */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                     \
-                                   sizeof(void *) * 4 +                 \
-                                   sizeof(struct intctx) +              \
-                                   sizeof(struct extctx) +              \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * Macro used to allocate a thread working area aligned as both position and
- * size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * IRQ prologue code, inserted at the start of all IRQ handlers enabled to
- * invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to
- * invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE()
-
-/**
- * IRQ handler function declaration.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * Simulator initialization.
- */
-#define port_init()
-
-/**
- * Does nothing in this simulator.
- */
-#define port_lock() asm volatile("nop")
-
-/**
- * Does nothing in this simulator.
- */
-#define port_unlock() asm volatile("nop")
-
-/**
- * Does nothing in this simulator.
- */
-#define port_lock_from_isr()
-
-/**
- * Does nothing in this simulator.
- */
-#define port_unlock_from_isr()
-
-/**
- * Does nothing in this simulator.
- */
-#define port_disable()
-
-/**
- * Does nothing in this simulator.
- */
-#define port_suspend()
-
-/**
- * Does nothing in this simulator.
- */
-#define port_enable()
-
-/**
- * In the simulator this does a polling pass on the simulated interrupt
- * sources.
- */
-#define port_wait_for_interrupt() ChkIntSources()
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  __attribute__((fastcall)) void port_switch(Thread *ntp, Thread *otp);
-  __attribute__((fastcall)) void port_halt(void);
-  __attribute__((cdecl, noreturn)) void _port_thread_start(msg_t (*pf)(void *),
-                                                           void *p);
-  void ChkIntSources(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/SIMIA32/chtypes.h b/os/ports/GCC/SIMIA32/chtypes.h
deleted file mode 100644
index b10eed325..000000000
--- a/os/ports/GCC/SIMIA32/chtypes.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint32_t        tprio_t;        /**< Thread priority.               */
-typedef int32_t         msg_t;          /**< Inter-thread message.          */
-typedef int32_t         eventid_t;      /**< Event Id.                      */
-typedef uint32_t        eventmask_t;    /**< Event mask.                    */
-typedef uint32_t        flagsmask_t;    /**< Event flags.                   */
-typedef uint32_t        systime_t;      /**< System time.                   */
-typedef int32_t         cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    It uses the "packed" GCC attribute.
- */
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
diff --git a/os/ports/GCC/SIMIA32/port.mk b/os/ports/GCC/SIMIA32/port.mk
deleted file mode 100644
index 8f053abc4..000000000
--- a/os/ports/GCC/SIMIA32/port.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-# List of the ChibiOS/RT SIMIA32 port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/SIMIA32/chcore.c
-
-PORTASM = 
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/SIMIA32
diff --git a/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h b/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h
deleted file mode 100644
index 4283ae860..000000000
--- a/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/LPC11xx/cmparams.h
- * @brief   ARM Cortex-M0 parameters for the LPC11xx.
- *
- * @defgroup IAR_ARMCMx_LPC11xx LPC11xx Specific Parameters
- * @ingroup IAR_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M0 specific parameters for the
- *          LPC11xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M0
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    2
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/LPC11xx/vectors.s b/os/ports/IAR/ARMCMx/LPC11xx/vectors.s
deleted file mode 100644
index 633313f52..000000000
--- a/os/ports/IAR/ARMCMx/LPC11xx/vectors.s
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-        MODULE  ?vectors
-
-        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
-        PRESERVE8
-
-        SECTION IRQSTACK:DATA:NOROOT(3)
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        PUBLIC  __vector_table
-
-        DATA
-
-__vector_table:
-        DCD     SFE(IRQSTACK)
-        DCD     __iar_program_start
-        DCD     NMIVector
-        DCD     HardFaultVector
-        DCD     MemManageVector
-        DCD     BusFaultVector
-        DCD     UsageFaultVector
-        DCD     Vector1C
-        DCD     Vector20
-        DCD     Vector24
-        DCD     Vector28
-        DCD     SVCallVector
-        DCD     DebugMonitorVector
-        DCD     Vector34
-        DCD     PendSVVector
-        DCD     SysTickVector
-        DCD     Vector40
-        DCD     Vector44
-        DCD     Vector48
-        DCD     Vector4C
-        DCD     Vector50
-        DCD     Vector54
-        DCD     Vector58
-        DCD     Vector5C
-        DCD     Vector60
-        DCD     Vector64
-        DCD     Vector68
-        DCD     Vector6C
-        DCD     Vector70
-        DCD     Vector74
-        DCD     Vector78
-        DCD     Vector7C
-        DCD     Vector80
-        DCD     Vector84
-        DCD     Vector88
-        DCD     Vector8C
-        DCD     Vector90
-        DCD     Vector94
-        DCD     Vector98
-        DCD     Vector9C
-        DCD     VectorA0
-        DCD     VectorA4
-        DCD     VectorA8
-        DCD     VectorAC
-        DCD     VectorB0
-        DCD     VectorB4
-        DCD     VectorB8
-        DCD     VectorBC
-
-/*
- * Default interrupt handlers.
- */
-        PUBWEAK NMIVector
-        PUBWEAK HardFaultVector
-        PUBWEAK MemManageVector
-        PUBWEAK BusFaultVector
-        PUBWEAK UsageFaultVector
-        PUBWEAK Vector1C
-        PUBWEAK Vector20
-        PUBWEAK Vector24
-        PUBWEAK Vector28
-        PUBWEAK SVCallVector
-        PUBWEAK DebugMonitorVector
-        PUBWEAK Vector34
-        PUBWEAK PendSVVector
-        PUBWEAK SysTickVector
-        PUBWEAK Vector40
-        PUBWEAK Vector44
-        PUBWEAK Vector48
-        PUBWEAK Vector4C
-        PUBWEAK Vector50
-        PUBWEAK Vector54
-        PUBWEAK Vector58
-        PUBWEAK Vector5C
-        PUBWEAK Vector60
-        PUBWEAK Vector64
-        PUBWEAK Vector68
-        PUBWEAK Vector6C
-        PUBWEAK Vector70
-        PUBWEAK Vector74
-        PUBWEAK Vector78
-        PUBWEAK Vector7C
-        PUBWEAK Vector80
-        PUBWEAK Vector84
-        PUBWEAK Vector88
-        PUBWEAK Vector8C
-        PUBWEAK Vector90
-        PUBWEAK Vector94
-        PUBWEAK Vector98
-        PUBWEAK Vector9C
-        PUBWEAK VectorA0
-        PUBWEAK VectorA4
-        PUBWEAK VectorA8
-        PUBWEAK VectorAC
-        PUBWEAK VectorB0
-        PUBWEAK VectorB4
-        PUBWEAK VectorB8
-        PUBWEAK VectorBC
-        PUBLIC  _unhandled_exception
-
-        SECTION .text:CODE:REORDER(1)
-        THUMB
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-_unhandled_exception
-        b       _unhandled_exception
-
-        END
diff --git a/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h b/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h
deleted file mode 100644
index 5019bacda..000000000
--- a/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/LPC13xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the LPC13xx.
- *
- * @defgroup IAR_ARMCMx_LPC13xx LPC13xx Specific Parameters
- * @ingroup IAR_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          LPC13xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    3
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/LPC13xx/vectors.s b/os/ports/IAR/ARMCMx/LPC13xx/vectors.s
deleted file mode 100644
index 21ea588c3..000000000
--- a/os/ports/IAR/ARMCMx/LPC13xx/vectors.s
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-        MODULE  ?vectors
-
-        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
-        PRESERVE8
-
-        SECTION IRQSTACK:DATA:NOROOT(3)
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        PUBLIC  __vector_table
-
-        DATA
-
-__vector_table:
-        DCD     SFE(IRQSTACK)
-        DCD     __iar_program_start
-        DCD     NMIVector
-        DCD     HardFaultVector
-        DCD     MemManageVector
-        DCD     BusFaultVector
-        DCD     UsageFaultVector
-        DCD     Vector1C
-        DCD     Vector20
-        DCD     Vector24
-        DCD     Vector28
-        DCD     SVCallVector
-        DCD     DebugMonitorVector
-        DCD     Vector34
-        DCD     PendSVVector
-        DCD     SysTickVector
-        DCD     Vector40
-        DCD     Vector44
-        DCD     Vector48
-        DCD     Vector4C
-        DCD     Vector50
-        DCD     Vector54
-        DCD     Vector58
-        DCD     Vector5C
-        DCD     Vector60
-        DCD     Vector64
-        DCD     Vector68
-        DCD     Vector6C
-        DCD     Vector70
-        DCD     Vector74
-        DCD     Vector78
-        DCD     Vector7C
-        DCD     Vector80
-        DCD     Vector84
-        DCD     Vector88
-        DCD     Vector8C
-        DCD     Vector90
-        DCD     Vector94
-        DCD     Vector98
-        DCD     Vector9C
-        DCD     VectorA0
-        DCD     VectorA4
-        DCD     VectorA8
-        DCD     VectorAC
-        DCD     VectorB0
-        DCD     VectorB4
-        DCD     VectorB8
-        DCD     VectorBC
-        DCD     VectorC0
-        DCD     VectorC4
-        DCD     VectorC8
-        DCD     VectorCC
-        DCD     VectorD0
-        DCD     VectorD4
-        DCD     VectorD8
-        DCD     VectorDC
-        DCD     VectorE0
-        DCD     VectorE4
-        DCD     VectorE8
-        DCD     VectorEC
-        DCD     VectorF0
-        DCD     VectorF4
-        DCD     VectorF8
-        DCD     VectorFC
-        DCD     Vector100
-        DCD     Vector104
-        DCD     Vector108
-        DCD     Vector10C
-        DCD     Vector110
-        DCD     Vector114
-        DCD     Vector118
-        DCD     Vector11C
-        DCD     Vector120
-        DCD     Vector124
-
-/*
- * Default interrupt handlers.
- */
-        PUBWEAK NMIVector
-        PUBWEAK HardFaultVector
-        PUBWEAK MemManageVector
-        PUBWEAK BusFaultVector
-        PUBWEAK UsageFaultVector
-        PUBWEAK Vector1C
-        PUBWEAK Vector20
-        PUBWEAK Vector24
-        PUBWEAK Vector28
-        PUBWEAK SVCallVector
-        PUBWEAK DebugMonitorVector
-        PUBWEAK Vector34
-        PUBWEAK PendSVVector
-        PUBWEAK SysTickVector
-        PUBWEAK Vector40
-        PUBWEAK Vector44
-        PUBWEAK Vector48
-        PUBWEAK Vector4C
-        PUBWEAK Vector50
-        PUBWEAK Vector54
-        PUBWEAK Vector58
-        PUBWEAK Vector5C
-        PUBWEAK Vector60
-        PUBWEAK Vector64
-        PUBWEAK Vector68
-        PUBWEAK Vector6C
-        PUBWEAK Vector70
-        PUBWEAK Vector74
-        PUBWEAK Vector78
-        PUBWEAK Vector7C
-        PUBWEAK Vector80
-        PUBWEAK Vector84
-        PUBWEAK Vector88
-        PUBWEAK Vector8C
-        PUBWEAK Vector90
-        PUBWEAK Vector94
-        PUBWEAK Vector98
-        PUBWEAK Vector9C
-        PUBWEAK VectorA0
-        PUBWEAK VectorA4
-        PUBWEAK VectorA8
-        PUBWEAK VectorAC
-        PUBWEAK VectorB0
-        PUBWEAK VectorB4
-        PUBWEAK VectorB8
-        PUBWEAK VectorBC
-        PUBWEAK VectorC0
-        PUBWEAK VectorC4
-        PUBWEAK VectorC8
-        PUBWEAK VectorCC
-        PUBWEAK VectorD0
-        PUBWEAK VectorD4
-        PUBWEAK VectorD8
-        PUBWEAK VectorDC
-        PUBWEAK VectorE0
-        PUBWEAK VectorE4
-        PUBWEAK VectorE8
-        PUBWEAK VectorEC
-        PUBWEAK VectorF0
-        PUBWEAK VectorF4
-        PUBWEAK VectorF8
-        PUBWEAK VectorFC
-        PUBWEAK Vector100
-        PUBWEAK Vector104
-        PUBWEAK Vector108
-        PUBWEAK Vector10C
-        PUBWEAK Vector110
-        PUBWEAK Vector114
-        PUBWEAK Vector118
-        PUBWEAK Vector11C
-        PUBWEAK Vector120
-        PUBWEAK Vector124
-        PUBLIC  _unhandled_exception
-
-        SECTION .text:CODE:REORDER(1)
-        THUMB
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-VectorC0
-VectorC4
-VectorC8
-VectorCC
-VectorD0
-VectorD4
-VectorD8
-VectorDC
-VectorE0
-VectorE4
-VectorE8
-VectorEC
-VectorF0
-VectorF4
-VectorF8
-VectorFC
-Vector100
-Vector104
-Vector108
-Vector10C
-Vector110
-Vector114
-Vector118
-Vector11C
-Vector120
-Vector124
-_unhandled_exception
-        b       _unhandled_exception
-
-        END
diff --git a/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h
deleted file mode 100644
index 4f44a6827..000000000
--- a/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/STM32F1xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the STM32F1xx.
- *
- * @defgroup IAR_ARMCMx_STM32F1xx STM32F1xx Specific Parameters
- * @ingroup IAR_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          STM32F1xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s b/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s
deleted file mode 100644
index 1d660d55d..000000000
--- a/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) &&                  \
-    !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) &&                  \
-    !defined(STM32F10X_HD) && !defined(STM32F10X_XL) &&                     \
-    !defined(STM32F10X_CL)
-#define _FROM_ASM_
-#include "board.h"
-#endif
-
-        MODULE  ?vectors
-
-        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
-        PRESERVE8
-
-        SECTION IRQSTACK:DATA:NOROOT(3)
-        SECTION .intvec:CODE:NOROOT(3)
-
-        EXTERN  __iar_program_start
-        PUBLIC  __vector_table
-
-        DATA
-
-__vector_table:
-        DCD     SFE(IRQSTACK)
-        DCD     __iar_program_start
-        DCD     NMIVector
-        DCD     HardFaultVector
-        DCD     MemManageVector
-        DCD     BusFaultVector
-        DCD     UsageFaultVector
-        DCD     Vector1C
-        DCD     Vector20
-        DCD     Vector24
-        DCD     Vector28
-        DCD     SVCallVector
-        DCD     DebugMonitorVector
-        DCD     Vector34
-        DCD     PendSVVector
-        DCD     SysTickVector
-        DCD     Vector40
-        DCD     Vector44
-        DCD     Vector48
-        DCD     Vector4C
-        DCD     Vector50
-        DCD     Vector54
-        DCD     Vector58
-        DCD     Vector5C
-        DCD     Vector60
-        DCD     Vector64
-        DCD     Vector68
-        DCD     Vector6C
-        DCD     Vector70
-        DCD     Vector74
-        DCD     Vector78
-        DCD     Vector7C
-        DCD     Vector80
-        DCD     Vector84
-        DCD     Vector88
-        DCD     Vector8C
-        DCD     Vector90
-        DCD     Vector94
-        DCD     Vector98
-        DCD     Vector9C
-        DCD     VectorA0
-        DCD     VectorA4
-        DCD     VectorA8
-        DCD     VectorAC
-        DCD     VectorB0
-        DCD     VectorB4
-        DCD     VectorB8
-        DCD     VectorBC
-        DCD     VectorC0
-        DCD     VectorC4
-        DCD     VectorC8
-        DCD     VectorCC
-        DCD     VectorD0
-        DCD     VectorD4
-        DCD     VectorD8
-        DCD     VectorDC
-        DCD     VectorE0
-        DCD     VectorE4
-        DCD     VectorE8
-#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) ||                    \
-    defined(STM32F10X_XL)    || defined(STM32F10X_CL)
-        DCD     VectorEC
-        DCD     VectorF0
-        DCD     VectorF4
-#endif
-#if defined(STM32F10X_HD)    || defined(STM32F10X_XL) || defined(STM32F10X_CL)
-        DCD     VectorF8
-        DCD     VectorFC
-        DCD     Vector100
-        DCD     Vector104
-        DCD     Vector108
-        DCD     Vector10C
-        DCD     Vector110
-        DCD     Vector114
-        DCD     Vector118
-        DCD     Vector11C
-        DCD     Vector120
-        DCD     Vector124
-        DCD     Vector128
-        DCD     Vector12C
-#endif
-#if defined(STM32F10X_CL)
-        DCD     Vector130
-        DCD     Vector134
-        DCD     Vector138
-        DCD     Vector13C
-        DCD     Vector140
-        DCD     Vector144
-        DCD     Vector148
-        DCD     Vector14C
-#endif
-
-/*
- * Default interrupt handlers.
- */
-        PUBWEAK NMIVector
-        PUBWEAK HardFaultVector
-        PUBWEAK MemManageVector
-        PUBWEAK BusFaultVector
-        PUBWEAK UsageFaultVector
-        PUBWEAK Vector1C
-        PUBWEAK Vector20
-        PUBWEAK Vector24
-        PUBWEAK Vector28
-        PUBWEAK SVCallVector
-        PUBWEAK DebugMonitorVector
-        PUBWEAK Vector34
-        PUBWEAK PendSVVector
-        PUBWEAK SysTickVector
-        PUBWEAK Vector40
-        PUBWEAK Vector44
-        PUBWEAK Vector48
-        PUBWEAK Vector4C
-        PUBWEAK Vector50
-        PUBWEAK Vector54
-        PUBWEAK Vector58
-        PUBWEAK Vector5C
-        PUBWEAK Vector60
-        PUBWEAK Vector64
-        PUBWEAK Vector68
-        PUBWEAK Vector6C
-        PUBWEAK Vector70
-        PUBWEAK Vector74
-        PUBWEAK Vector78
-        PUBWEAK Vector7C
-        PUBWEAK Vector80
-        PUBWEAK Vector84
-        PUBWEAK Vector88
-        PUBWEAK Vector8C
-        PUBWEAK Vector90
-        PUBWEAK Vector94
-        PUBWEAK Vector98
-        PUBWEAK Vector9C
-        PUBWEAK VectorA0
-        PUBWEAK VectorA4
-        PUBWEAK VectorA8
-        PUBWEAK VectorAC
-        PUBWEAK VectorB0
-        PUBWEAK VectorB4
-        PUBWEAK VectorB8
-        PUBWEAK VectorBC
-        PUBWEAK VectorC0
-        PUBWEAK VectorC4
-        PUBWEAK VectorC8
-        PUBWEAK VectorCC
-        PUBWEAK VectorD0
-        PUBWEAK VectorD4
-        PUBWEAK VectorD8
-        PUBWEAK VectorDC
-        PUBWEAK VectorE0
-        PUBWEAK VectorE4
-        PUBWEAK VectorE8
-        PUBWEAK VectorEC
-        PUBWEAK VectorF0
-        PUBWEAK VectorF4
-        PUBWEAK VectorF8
-        PUBWEAK VectorFC
-        PUBWEAK Vector100
-        PUBWEAK Vector104
-        PUBWEAK Vector108
-        PUBWEAK Vector10C
-        PUBWEAK Vector110
-        PUBWEAK Vector114
-        PUBWEAK Vector118
-        PUBWEAK Vector11C
-        PUBWEAK Vector120
-        PUBWEAK Vector124
-        PUBWEAK Vector128
-        PUBWEAK Vector12C
-        PUBWEAK Vector130
-        PUBWEAK Vector134
-        PUBWEAK Vector138
-        PUBWEAK Vector13C
-        PUBWEAK Vector140
-        PUBWEAK Vector144
-        PUBWEAK Vector148
-        PUBWEAK Vector14C
-        PUBLIC  _unhandled_exception
-
-        SECTION .text:CODE:REORDER(1)
-        THUMB
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-VectorC0
-VectorC4
-VectorC8
-VectorCC
-VectorD0
-VectorD4
-VectorD8
-VectorDC
-VectorE0
-VectorE4
-VectorE8
-VectorEC
-VectorF0
-VectorF4
-VectorF8
-VectorFC
-Vector100
-Vector104
-Vector108
-Vector10C
-Vector110
-Vector114
-Vector118
-Vector11C
-Vector120
-Vector124
-Vector128
-Vector12C
-Vector130
-Vector134
-Vector138
-Vector13C
-Vector140
-Vector144
-Vector148
-Vector14C
-_unhandled_exception
-        b       _unhandled_exception
-
-        END
diff --git a/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h
deleted file mode 100644
index 2d56050c2..000000000
--- a/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/STM32F4xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the STM32F4xx.
- *
- * @defgroup IAR_ARMCMx_STM32F4xx STM32F4xx Specific Parameters
- * @ingroup IAR_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- *          STM32F4xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M4
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          TRUE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s b/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s
deleted file mode 100644
index 3021cd421..000000000
--- a/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-        MODULE  ?vectors
-
-        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
-        PRESERVE8
-
-        SECTION IRQSTACK:DATA:NOROOT(3)
-        SECTION .intvec:CODE:NOROOT(3)
-
-        EXTERN  __iar_program_start
-        PUBLIC  __vector_table
-
-        DATA
-
-__vector_table:
-        DCD     SFE(IRQSTACK)
-        DCD     __iar_program_start
-        DCD     NMIVector
-        DCD     HardFaultVector
-        DCD     MemManageVector
-        DCD     BusFaultVector
-        DCD     UsageFaultVector
-        DCD     Vector1C
-        DCD     Vector20
-        DCD     Vector24
-        DCD     Vector28
-        DCD     SVCallVector
-        DCD     DebugMonitorVector
-        DCD     Vector34
-        DCD     PendSVVector
-        DCD     SysTickVector
-        DCD     Vector40
-        DCD     Vector44
-        DCD     Vector48
-        DCD     Vector4C
-        DCD     Vector50
-        DCD     Vector54
-        DCD     Vector58
-        DCD     Vector5C
-        DCD     Vector60
-        DCD     Vector64
-        DCD     Vector68
-        DCD     Vector6C
-        DCD     Vector70
-        DCD     Vector74
-        DCD     Vector78
-        DCD     Vector7C
-        DCD     Vector80
-        DCD     Vector84
-        DCD     Vector88
-        DCD     Vector8C
-        DCD     Vector90
-        DCD     Vector94
-        DCD     Vector98
-        DCD     Vector9C
-        DCD     VectorA0
-        DCD     VectorA4
-        DCD     VectorA8
-        DCD     VectorAC
-        DCD     VectorB0
-        DCD     VectorB4
-        DCD     VectorB8
-        DCD     VectorBC
-        DCD     VectorC0
-        DCD     VectorC4
-        DCD     VectorC8
-        DCD     VectorCC
-        DCD     VectorD0
-        DCD     VectorD4
-        DCD     VectorD8
-        DCD     VectorDC
-        DCD     VectorE0
-        DCD     VectorE4
-        DCD     VectorE8
-        DCD     VectorEC
-        DCD     VectorF0
-        DCD     VectorF4
-        DCD     VectorF8
-        DCD     VectorFC
-        DCD     Vector100
-        DCD     Vector104
-        DCD     Vector108
-        DCD     Vector10C
-        DCD     Vector110
-        DCD     Vector114
-        DCD     Vector118
-        DCD     Vector11C
-        DCD     Vector120
-        DCD     Vector124
-        DCD     Vector128
-        DCD     Vector12C
-        DCD     Vector130
-        DCD     Vector134
-        DCD     Vector138
-        DCD     Vector13C
-        DCD     Vector140
-        DCD     Vector144
-        DCD     Vector148
-        DCD     Vector14C
-        DCD     Vector150
-        DCD     Vector154
-        DCD     Vector158
-        DCD     Vector15C
-        DCD     Vector160
-        DCD     Vector164
-        DCD     Vector168
-        DCD     Vector16C
-        DCD     Vector170
-        DCD     Vector174
-        DCD     Vector178
-        DCD     Vector17C
-        DCD     Vector180
-        DCD     Vector184
-
-/*
- * Default interrupt handlers.
- */
-        PUBWEAK NMIVector
-        PUBWEAK HardFaultVector
-        PUBWEAK MemManageVector
-        PUBWEAK BusFaultVector
-        PUBWEAK UsageFaultVector
-        PUBWEAK Vector1C
-        PUBWEAK Vector20
-        PUBWEAK Vector24
-        PUBWEAK Vector28
-        PUBWEAK SVCallVector
-        PUBWEAK DebugMonitorVector
-        PUBWEAK Vector34
-        PUBWEAK PendSVVector
-        PUBWEAK SysTickVector
-        PUBWEAK Vector40
-        PUBWEAK Vector44
-        PUBWEAK Vector48
-        PUBWEAK Vector4C
-        PUBWEAK Vector50
-        PUBWEAK Vector54
-        PUBWEAK Vector58
-        PUBWEAK Vector5C
-        PUBWEAK Vector60
-        PUBWEAK Vector64
-        PUBWEAK Vector68
-        PUBWEAK Vector6C
-        PUBWEAK Vector70
-        PUBWEAK Vector74
-        PUBWEAK Vector78
-        PUBWEAK Vector7C
-        PUBWEAK Vector80
-        PUBWEAK Vector84
-        PUBWEAK Vector88
-        PUBWEAK Vector8C
-        PUBWEAK Vector90
-        PUBWEAK Vector94
-        PUBWEAK Vector98
-        PUBWEAK Vector9C
-        PUBWEAK VectorA0
-        PUBWEAK VectorA4
-        PUBWEAK VectorA8
-        PUBWEAK VectorAC
-        PUBWEAK VectorB0
-        PUBWEAK VectorB4
-        PUBWEAK VectorB8
-        PUBWEAK VectorBC
-        PUBWEAK VectorC0
-        PUBWEAK VectorC4
-        PUBWEAK VectorC8
-        PUBWEAK VectorCC
-        PUBWEAK VectorD0
-        PUBWEAK VectorD4
-        PUBWEAK VectorD8
-        PUBWEAK VectorDC
-        PUBWEAK VectorE0
-        PUBWEAK VectorE4
-        PUBWEAK VectorE8
-        PUBWEAK VectorEC
-        PUBWEAK VectorF0
-        PUBWEAK VectorF4
-        PUBWEAK VectorF8
-        PUBWEAK VectorFC
-        PUBWEAK Vector100
-        PUBWEAK Vector104
-        PUBWEAK Vector108
-        PUBWEAK Vector10C
-        PUBWEAK Vector110
-        PUBWEAK Vector114
-        PUBWEAK Vector118
-        PUBWEAK Vector11C
-        PUBWEAK Vector120
-        PUBWEAK Vector124
-        PUBWEAK Vector128
-        PUBWEAK Vector12C
-        PUBWEAK Vector130
-        PUBWEAK Vector134
-        PUBWEAK Vector138
-        PUBWEAK Vector13C
-        PUBWEAK Vector140
-        PUBWEAK Vector144
-        PUBWEAK Vector148
-        PUBWEAK Vector14C
-        PUBWEAK Vector150
-        PUBWEAK Vector154
-        PUBWEAK Vector158
-        PUBWEAK Vector15C
-        PUBWEAK Vector160
-        PUBWEAK Vector164
-        PUBWEAK Vector168
-        PUBWEAK Vector16C
-        PUBWEAK Vector170
-        PUBWEAK Vector174
-        PUBWEAK Vector178
-        PUBWEAK Vector17C
-        PUBWEAK Vector180
-        PUBWEAK Vector184
-        PUBLIC  _unhandled_exception
-
-        SECTION .text:CODE:REORDER(1)
-        THUMB
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-VectorC0
-VectorC4
-VectorC8
-VectorCC
-VectorD0
-VectorD4
-VectorD8
-VectorDC
-VectorE0
-VectorE4
-VectorE8
-VectorEC
-VectorF0
-VectorF4
-VectorF8
-VectorFC
-Vector100
-Vector104
-Vector108
-Vector10C
-Vector110
-Vector114
-Vector118
-Vector11C
-Vector120
-Vector124
-Vector128
-Vector12C
-Vector130
-Vector134
-Vector138
-Vector13C
-Vector140
-Vector144
-Vector148
-Vector14C
-Vector150
-Vector154
-Vector158
-Vector15C
-Vector160
-Vector164
-Vector168
-Vector16C
-Vector170
-Vector174
-Vector178
-Vector17C
-Vector180
-Vector184
-_unhandled_exception
-        b       _unhandled_exception
-
-        END
diff --git a/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h
deleted file mode 100644
index 9cd591e03..000000000
--- a/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/STM32L1xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the STM32L1xx.
- *
- * @defgroup IAR_ARMCMx_STM32L1xx STM32L1xx Specific Parameters
- * @ingroup IAR_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          STM32L1xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s b/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s
deleted file mode 100644
index 85f9d390f..000000000
--- a/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#if !defined(STM32L1XX_MD)
-#define _FROM_ASM_
-#include "board.h"
-#endif
-
-        MODULE  ?vectors
-
-        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
-        PRESERVE8
-
-        SECTION IRQSTACK:DATA:NOROOT(3)
-        SECTION .intvec:CODE:NOROOT(3)
-
-        EXTERN  __iar_program_start
-        PUBLIC  __vector_table
-
-        DATA
-
-__vector_table:
-        DCD     SFE(IRQSTACK)
-        DCD     __iar_program_start
-        DCD     NMIVector
-        DCD     HardFaultVector
-        DCD     MemManageVector
-        DCD     BusFaultVector
-        DCD     UsageFaultVector
-        DCD     Vector1C
-        DCD     Vector20
-        DCD     Vector24
-        DCD     Vector28
-        DCD     SVCallVector
-        DCD     DebugMonitorVector
-        DCD     Vector34
-        DCD     PendSVVector
-        DCD     SysTickVector
-        DCD     Vector40
-        DCD     Vector44
-        DCD     Vector48
-        DCD     Vector4C
-        DCD     Vector50
-        DCD     Vector54
-        DCD     Vector58
-        DCD     Vector5C
-        DCD     Vector60
-        DCD     Vector64
-        DCD     Vector68
-        DCD     Vector6C
-        DCD     Vector70
-        DCD     Vector74
-        DCD     Vector78
-        DCD     Vector7C
-        DCD     Vector80
-        DCD     Vector84
-        DCD     Vector88
-        DCD     Vector8C
-        DCD     Vector90
-        DCD     Vector94
-        DCD     Vector98
-        DCD     Vector9C
-        DCD     VectorA0
-        DCD     VectorA4
-        DCD     VectorA8
-        DCD     VectorAC
-        DCD     VectorB0
-        DCD     VectorB4
-        DCD     VectorB8
-        DCD     VectorBC
-        DCD     VectorC0
-        DCD     VectorC4
-        DCD     VectorC8
-        DCD     VectorCC
-        DCD     VectorD0
-        DCD     VectorD4
-        DCD     VectorD8
-        DCD     VectorDC
-        DCD     VectorE0
-        DCD     VectorE4
-        DCD     VectorE8
-        DCD     VectorEC
-        DCD     VectorF0
-
-/*
- * Default interrupt handlers.
- */
-        PUBWEAK NMIVector
-        PUBWEAK HardFaultVector
-        PUBWEAK MemManageVector
-        PUBWEAK BusFaultVector
-        PUBWEAK UsageFaultVector
-        PUBWEAK Vector1C
-        PUBWEAK Vector20
-        PUBWEAK Vector24
-        PUBWEAK Vector28
-        PUBWEAK SVCallVector
-        PUBWEAK DebugMonitorVector
-        PUBWEAK Vector34
-        PUBWEAK PendSVVector
-        PUBWEAK SysTickVector
-        PUBWEAK Vector40
-        PUBWEAK Vector44
-        PUBWEAK Vector48
-        PUBWEAK Vector4C
-        PUBWEAK Vector50
-        PUBWEAK Vector54
-        PUBWEAK Vector58
-        PUBWEAK Vector5C
-        PUBWEAK Vector60
-        PUBWEAK Vector64
-        PUBWEAK Vector68
-        PUBWEAK Vector6C
-        PUBWEAK Vector70
-        PUBWEAK Vector74
-        PUBWEAK Vector78
-        PUBWEAK Vector7C
-        PUBWEAK Vector80
-        PUBWEAK Vector84
-        PUBWEAK Vector88
-        PUBWEAK Vector8C
-        PUBWEAK Vector90
-        PUBWEAK Vector94
-        PUBWEAK Vector98
-        PUBWEAK Vector9C
-        PUBWEAK VectorA0
-        PUBWEAK VectorA4
-        PUBWEAK VectorA8
-        PUBWEAK VectorAC
-        PUBWEAK VectorB0
-        PUBWEAK VectorB4
-        PUBWEAK VectorB8
-        PUBWEAK VectorBC
-        PUBWEAK VectorC0
-        PUBWEAK VectorC4
-        PUBWEAK VectorC8
-        PUBWEAK VectorCC
-        PUBWEAK VectorD0
-        PUBWEAK VectorD4
-        PUBWEAK VectorD8
-        PUBWEAK VectorDC
-        PUBWEAK VectorE0
-        PUBWEAK VectorE4
-        PUBWEAK VectorE8
-        PUBWEAK VectorEC
-        PUBWEAK VectorF0
-        PUBLIC  _unhandled_exception
-
-        SECTION .text:CODE:REORDER(1)
-        THUMB
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-VectorC0
-VectorC4
-VectorC8
-VectorCC
-VectorD0
-VectorD4
-VectorD8
-VectorDC
-VectorE0
-VectorE4
-VectorE8
-VectorEC
-VectorF0
-_unhandled_exception
-        b       _unhandled_exception
-
-        END
diff --git a/os/ports/IAR/ARMCMx/chcore.c b/os/ports/IAR/ARMCMx/chcore.c
deleted file mode 100644
index e89084c97..000000000
--- a/os/ports/IAR/ARMCMx/chcore.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/chcore.c
- * @brief   ARM Cortex-Mx port code.
- *
- * @addtogroup IAR_ARMCMx_CORE
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Halts the system.
- * @note    The function is declared as a weak symbol, it is possible
- *          to redefine it in your application code.
- */
-#if !defined(__DOXYGEN__)
-__weak
-#endif
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/chcore.h b/os/ports/IAR/ARMCMx/chcore.h
deleted file mode 100644
index 0ea154f00..000000000
--- a/os/ports/IAR/ARMCMx/chcore.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/chcore.h
- * @brief   ARM Cortex-Mx port macros and structures.
- *
- * @addtogroup IAR_ARMCMx_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-/*===========================================================================*/
-/* Port constants (common).                                                  */
-/*===========================================================================*/
-
-/* Added to make the header stand-alone when included from asm.*/
-#ifndef FALSE
-#define FALSE       0
-#endif
-#ifndef TRUE
-#define TRUE        (!FALSE)
-#endif
-
-#define CORTEX_M0                       0   /**< @brief Cortex-M0 variant.  */
-#define CORTEX_M1                       1   /**< @brief Cortex-M1 variant.  */
-#define CORTEX_M3                       3   /**< @brief Cortex-M3 variant.  */
-#define CORTEX_M4                       4   /**< @brief Cortex-M4 variant.  */
-
-/* Inclusion of the Cortex-Mx implementation specific parameters.*/
-#include "cmparams.h"
-
-/* Cortex model check, only M0 and M3 supported right now.*/
-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) ||           \
-    (CORTEX_MODEL == CORTEX_M4)
-#elif (CORTEX_MODEL == CORTEX_M1)
-#error "untested Cortex-M model"
-#else
-#error "unknown or unsupported Cortex-M model"
-#endif
-
-/**
- * @brief   Total priority levels.
- */
-#define CORTEX_PRIORITY_LEVELS          (1 << CORTEX_PRIORITY_BITS)
-
-/**
- * @brief   Minimum priority level.
- * @details This minimum priority level is calculated from the number of
- *          priority bits supported by the specific Cortex-Mx implementation.
- */
-#define CORTEX_MINIMUM_PRIORITY         (CORTEX_PRIORITY_LEVELS - 1)
-
-/**
- * @brief   Maximum priority level.
- * @details The maximum allowed priority level is always zero.
- */
-#define CORTEX_MAXIMUM_PRIORITY         0
-
-/*===========================================================================*/
-/* Port macros (common).                                                     */
-/*===========================================================================*/
-
-/**
- * @brief   Priority level verification macro.
- */
-#define CORTEX_IS_VALID_PRIORITY(n)                                         \
-  (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
-
-/**
- * @brief   Priority level verification macro.
- */
-#define CORTEX_IS_VALID_KERNEL_PRIORITY(n)                                  \
-  (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
-
-/**
- * @brief   Priority level to priority mask conversion macro.
- */
-#define CORTEX_PRIORITY_MASK(n)                                             \
-  ((n) << (8 - CORTEX_PRIORITY_BITS))
-
-/*===========================================================================*/
-/* Port configurable parameters (common).                                    */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port derived parameters (common).                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port exported info (common).                                              */
-/*===========================================================================*/
-
-/**
- * @brief   Macro defining a generic ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "IAR"
-
-/*===========================================================================*/
-/* Port implementation part (common).                                        */
-/*===========================================================================*/
-
-/* Includes the sub-architecture-specific part.*/
-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
-#include "chcore_v6m.h"
-#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
-#include "chcore_v7m.h"
-#endif
-
-#if !defined(_FROM_ASM_)
-
-#include <intrinsics.h>
-#include "nvic.h"
-
-/* The following declarations are there just for Doxygen documentation, the
-   real declarations are inside the sub-headers.*/
-#if defined(__DOXYGEN__)
-
-/**
- * @brief   Stack and memory alignment enforcement.
- * @note    In this architecture the stack alignment is enforced to 64 bits,
- *          32 bits alignment is supported by hardware but deprecated by ARM,
- *          the implementation choice is to not offer the option.
- */
-typedef uint64_t stkalign_t;
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- * @note    It is implemented to match the Cortex-Mx exception context.
- */
-struct extctx {};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching.
- */
-struct intctx {};
-
-#endif /* defined(__DOXYGEN__) */
-
-/**
- * @brief   Excludes the default @p chSchIsPreemptionRequired()implementation.
- */
-#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED
-
-#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
-/**
- * @brief   Inline-able version of this kernel function.
- */
-#define chSchIsPreemptionRequired()                                         \
-  (currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio :           \
-                      firstprio(&rlist.r_queue) >= currp->p_prio)
-#else /* CH_TIME_QUANTUM == 0 */
-#define chSchIsPreemptionRequired()                                         \
-  (firstprio(&rlist.r_queue) > currp->p_prio)
-#endif /* CH_TIME_QUANTUM == 0 */
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.c b/os/ports/IAR/ARMCMx/chcore_v6m.c
deleted file mode 100644
index 5a3c8ca0c..000000000
--- a/os/ports/IAR/ARMCMx/chcore_v6m.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/chcore_v6m.c
- * @brief   ARMv6-M architecture port code.
- *
- * @addtogroup IAR_ARMCMx_V6M_CORE
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* Port interrupt handlers.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   System Timer vector.
- * @details This interrupt is used as system tick.
- * @note    The timer must be initialized in the startup code.
- */
-CH_IRQ_HANDLER(SysTickVector) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-/**
- * @brief   NMI vector.
- * @details The NMI vector is used for exception mode re-entering after a
- *          context switch.
- */
-void NMIVector(void) {
-  register struct extctx *ctxp;
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp = (struct extctx *)__get_PSP();
-  ctxp++;
-  __set_PSP((unsigned long)ctxp);
-  port_unlock_from_isr();
-}
-#endif /* !CORTEX_ALTERNATE_SWITCH */
-
-#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-/**
- * @brief   PendSV vector.
- * @details The PendSV vector is used for exception mode re-entering after a
- *          context switch.
- */
-void PendSVVector(void) {
-  register struct extctx *ctxp;
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp = (struct extctx *)__get_PSP();
-  ctxp++;
-  __set_PSP((unsigned long)ctxp);
-}
-#endif /* CORTEX_ALTERNATE_SWITCH */
-
-/*===========================================================================*/
-/* Port exported functions.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   IRQ epilogue code.
- *
- * @param[in] lr        value of the @p LR register on ISR entry
- */
-void _port_irq_epilogue(regarm_t lr) {
-
-  if (lr != (regarm_t)0xFFFFFFF1) {
-    register struct extctx *ctxp;
-
-    port_lock_from_isr();
-    /* Adding an artificial exception return context, there is no need to
-       populate it fully.*/
-    ctxp = (struct extctx *)__get_PSP();
-    ctxp--;
-    __set_PSP((unsigned long)ctxp);
-    ctxp->xpsr = (regarm_t)0x01000000;
-
-    /* The exit sequence is different depending on if a preemption is
-       required or not.*/
-    if (chSchIsPreemptionRequired()) {
-      /* Preemption is required we need to enforce a context switch.*/
-      ctxp->pc = (regarm_t)_port_switch_from_isr;
-    }
-    else {
-      /* Preemption not required, we just need to exit the exception
-         atomically.*/
-      ctxp->pc = (regarm_t)_port_exit_from_isr;
-    }
-
-    /* Note, returning without unlocking is intentional, this is done in
-       order to keep the rest of the context switch atomic.*/
-  }
-}
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h
deleted file mode 100644
index d1d5caeb6..000000000
--- a/os/ports/IAR/ARMCMx/chcore_v6m.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/chcore_v6m.h
- * @brief   ARMv6-M architecture port macros and structures.
- *
- * @addtogroup IAR_ARMCMx_V6M_CORE
- * @{
- */
-
-#ifndef _CHCORE_V6M_H_
-#define _CHCORE_V6M_H_
-
-/*===========================================================================*/
-/* Port constants.                                                           */
-/*===========================================================================*/
-
-/**
- * @brief   PendSV priority level.
- * @note    This priority is enforced to be equal to @p 0,
- *          this handler always has the highest priority that cannot preempt
- *          the kernel.
- */
-#define CORTEX_PRIORITY_PENDSV          0
-
-/*===========================================================================*/
-/* Port macros.                                                              */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- * @note    In this port it is set to 16 because the idle thread does have
- *          a stack frame when compiling without optimizations. You may
- *          reduce this value to zero when compiling with optimizations.
- */
-#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
-#define PORT_IDLE_THREAD_STACK_SIZE     16
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- * @note    In this port this value is conservatively set to 32 because the
- *          function @p chSchDoReschedule() can have a stack frame, especially
- *          with compiler optimizations disabled. The value can be reduced
- *          when compiler optimizations are enabled.
- */
-#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK         32
-#endif
-
-/**
- * @brief   Enables the use of the WFI instruction in the idle thread loop.
- */
-#if !defined(CORTEX_ENABLE_WFI_IDLE)
-#define CORTEX_ENABLE_WFI_IDLE          FALSE
-#endif
-
-/**
- * @brief   SYSTICK handler priority.
- * @note    The default SYSTICK handler priority is calculated as the priority
- *          level in the middle of the numeric priorities range.
- */
-#if !defined(CORTEX_PRIORITY_SYSTICK)
-#define CORTEX_PRIORITY_SYSTICK         (CORTEX_PRIORITY_LEVELS >> 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
-
-/**
- * @brief   Alternate preemption method.
- * @details Activating this option will make the Kernel use the PendSV
- *          handler for preemption instead of the NMI handler.
- */
-#ifndef CORTEX_ALTERNATE_SWITCH
-#define CORTEX_ALTERNATE_SWITCH         FALSE
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   Maximum usable priority for normal ISRs.
- */
-#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-#define CORTEX_MAX_KERNEL_PRIORITY      1
-#else
-#define CORTEX_MAX_KERNEL_PRIORITY      0
-#endif
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Macro defining the specific ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM_v6M
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "ARMv6-M"
-
-/**
- * @brief   Name of the architecture variant.
- */
-#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
-#define CH_CORE_VARIANT_NAME            "Cortex-M0"
-#elif (CORTEX_MODEL == CORTEX_M1)
-#define CH_CORE_VARIANT_NAME            "Cortex-M1"
-#endif
-
-/**
- * @brief   Port-specific information string.
- */
-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-#define CH_PORT_INFO                    "Preemption through NMI"
-#else
-#define CH_PORT_INFO                    "Preemption through PendSV"
-#endif
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-/**
- * @brief   Generic ARM register.
- */
-typedef void *regarm_t;
-
-/**
- * @brief   Stack and memory alignment enforcement.
- * @note    In this architecture the stack alignment is enforced to 64 bits,
- *          32 bits alignment is supported by hardware but deprecated by ARM,
- *          the implementation choice is to not offer the option.
- */
-typedef uint64_t stkalign_t;
-
- /* The documentation of the following declarations is in chconf.h in order
-    to not have duplicated structure names into the documentation.*/
-#if !defined(__DOXYGEN__)
-
-struct extctx {
-  regarm_t      r0;
-  regarm_t      r1;
-  regarm_t      r2;
-  regarm_t      r3;
-  regarm_t      r12;
-  regarm_t      lr_thd;
-  regarm_t      pc;
-  regarm_t      xpsr;
-};
-
-struct intctx {
-  regarm_t      r8;
-  regarm_t      r9;
-  regarm_t      r10;
-  regarm_t      r11;
-  regarm_t      r4;
-  regarm_t      r5;
-  regarm_t      r6;
-  regarm_t      r7;
-  regarm_t      lr;
-};
-
-#endif /* !defined(__DOXYGEN__) */
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- *          structure representing the stack pointer at context switch time.
- */
-struct context {
-  struct intctx *r13;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
-                                     wsize -                                \
-                                     sizeof(struct intctx));                \
-  tp->p_ctx.r13->r4 = (regarm_t)pf;                                         \
-  tp->p_ctx.r13->r5 = (regarm_t)arg;                                        \
-  tp->p_ctx.r13->lr = (regarm_t)_port_thread_start;                         \
-}
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__get_LR()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Fast IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_FAST_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Port-related initialization code.
- */
-#define port_init() {                                                       \
-  SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \
-  nvicSetSystemHandlerPriority(HANDLER_PENDSV,                              \
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,                             \
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \
-}
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform
- *          more actions.
- */
-#define port_lock() __disable_interrupt()
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform
- *          more actions.
- */
-#define port_unlock() __enable_interrupt()
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependent,
- *          in its simplest form it is void.
- * @note    Same as @p port_lock() in this port.
- */
-#define port_lock_from_isr() port_lock()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- * @note    Same as @p port_lock() in this port.
- */
-#define port_unlock_from_isr() port_unlock()
-
-/**
- * @brief   Disables all the interrupt sources.
- */
-#define port_disable() __disable_interrupt()
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- */
-#define port_suspend() __disable_interrupt()
-
-/**
- * @brief   Enables all the interrupt sources.
- */
-#define port_enable() __enable_interrupt()
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- * @note    Implemented as an inlined @p WFI instruction.
- */
-#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() asm ("wfi")
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-#else
-#define port_switch(ntp, otp) {                                             \
-  if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \
-    chDbgPanic("stack overflow");                                           \
-  _port_switch(ntp, otp);                                                   \
-}
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_halt(void);
-  void _port_irq_epilogue(regarm_t lr);
-  void _port_switch_from_isr(void);
-  void _port_exit_from_isr(void);
-  void _port_switch(Thread *ntp, Thread *otp);
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_V6M_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.c b/os/ports/IAR/ARMCMx/chcore_v7m.c
deleted file mode 100644
index c9d45b1a6..000000000
--- a/os/ports/IAR/ARMCMx/chcore_v7m.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/chcore_v7m.c
- * @brief   ARMv7-M architecture port code.
- *
- * @addtogroup IAR_ARMCMx_V7M_CORE
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* Port interrupt handlers.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   System Timer vector.
- * @details This interrupt is used as system tick.
- * @note    The timer must be initialized in the startup code.
- */
-CH_IRQ_HANDLER(SysTickVector) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief   SVC vector.
- * @details The SVC vector is used for exception mode re-entering after a
- *          context switch.
- * @note    The PendSV vector is only used in advanced kernel mode.
- */
-void SVCallVector(void) {
-  struct extctx *ctxp;
-
-  /* Current PSP value.*/
-  ctxp = (struct extctx *)__get_PSP();
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp++;
-
-#if CORTEX_USE_FPU
-  /* Restoring the special register SCB_FPCCR.*/
-  SCB_FPCCR = (uint32_t)ctxp->fpccr;
-  SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx);
-#endif
-  __set_PSP((unsigned long)ctxp);
-  port_unlock_from_isr();
-}
-#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
-
-#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief   PendSV vector.
- * @details The PendSV vector is used for exception mode re-entering after a
- *          context switch.
- * @note    The PendSV vector is only used in compact kernel mode.
- */
-void PendSVVector(void) {
-  struct extctx *ctxp;
-
-  /* Current PSP value.*/
-  ctxp = (struct extctx *)__get_PSP();
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp++;
-
-#if CORTEX_USE_FPU
-  /* Restoring the special register SCB_FPCCR.*/
-  SCB_FPCCR = (uint32_t)ctxp->fpccr;
-  SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx);
-#endif
-  __set_PSP((unsigned long)ctxp);
-}
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/*===========================================================================*/
-/* Port exported functions.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   Port-related initialization code.
- */
-void _port_init(void) {
-
-  /* Initialization of the vector table and priority related settings.*/
-  SCB_VTOR = CORTEX_VTOR_INIT;
-  SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT);
-
-#if CORTEX_USE_FPU
-  {
-    /* Initializing the FPU context save in lazy mode.*/
-    SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
-
-    /* CP10 and CP11 set to full access.*/
-    SCB_CPACR |= 0x00F00000;
-
-    /* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/
-    __set_CONTROL(__get_CONTROL() | 4);
-
-    /* FPSCR and FPDSCR initially zero.*/
-    __set_FPSCR(0);
-    SCB_FPDSCR = 0;
-  }
-#endif
-
-  /* Initialization of the system vectors used by the port.*/
-  nvicSetSystemHandlerPriority(HANDLER_SVCALL,
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
-  nvicSetSystemHandlerPriority(HANDLER_PENDSV,
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
-}
-
-/**
- * @brief   Exception exit redirection to _port_switch_from_isr().
- */
-void _port_irq_epilogue(void) {
-
-  port_lock_from_isr();
-  if ((SCB_ICSR & ICSR_RETTOBASE) != 0) {
-    struct extctx *ctxp;
-
-    /* Current PSP value.*/
-    ctxp = (struct extctx *)__get_PSP();
-
-    /* Adding an artificial exception return context, there is no need to
-       populate it fully.*/
-    ctxp--;
-    __set_PSP((unsigned long)ctxp);
-    ctxp->xpsr = (regarm_t)0x01000000;
-
-    /* The exit sequence is different depending on if a preemption is
-       required or not.*/
-    if (chSchIsPreemptionRequired()) {
-      /* Preemption is required we need to enforce a context switch.*/
-      ctxp->pc = (regarm_t)_port_switch_from_isr;
-#if CORTEX_USE_FPU
-      /* Triggering a lazy FPU state save.*/
-      (void)__get_FPSCR();
-#endif
-    }
-    else {
-      /* Preemption not required, we just need to exit the exception
-         atomically.*/
-      ctxp->pc = (regarm_t)_port_exit_from_isr;
-    }
-
-#if CORTEX_USE_FPU
-    {
-      uint32_t fpccr;
-
-      /* Saving the special register SCB_FPCCR into the reserved offset of
-         the Cortex-M4 exception frame.*/
-      (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR);
-
-      /* Now the FPCCR is modified in order to not restore the FPU status
-         from the artificial return context.*/
-      SCB_FPCCR = fpccr | FPCCR_LSPACT;
-    }
-#endif
-
-    /* Note, returning without unlocking is intentional, this is done in
-       order to keep the rest of the context switch atomic.*/
-    return;
-  }
-  port_unlock_from_isr();
-}
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.h b/os/ports/IAR/ARMCMx/chcore_v7m.h
deleted file mode 100644
index 112c52a35..000000000
--- a/os/ports/IAR/ARMCMx/chcore_v7m.h
+++ /dev/null
@@ -1,504 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/chcore_v7m.h
- * @brief   ARMv7-M architecture port macros and structures.
- *
- * @addtogroup IAR_ARMCMx_V7M_CORE
- * @{
- */
-
-#ifndef _CHCORE_V7M_H_
-#define _CHCORE_V7M_H_
-
-/*===========================================================================*/
-/* Port constants.                                                           */
-/*===========================================================================*/
-
-/**
- * @brief   Disabled value for BASEPRI register.
- */
-#define CORTEX_BASEPRI_DISABLED         0
-
-/*===========================================================================*/
-/* Port macros.                                                              */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- * @note    In this port it is set to 16 because the idle thread does have
- *          a stack frame when compiling without optimizations. You may
- *          reduce this value to zero when compiling with optimizations.
- */
-#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
-#define PORT_IDLE_THREAD_STACK_SIZE     16
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- * @note    In this port this value is conservatively set to 32 because the
- *          function @p chSchDoReschedule() can have a stack frame, especially
- *          with compiler optimizations disabled. The value can be reduced
- *          when compiler optimizations are enabled.
- */
-#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK         32
-#endif
-
-/**
- * @brief   Enables the use of the WFI instruction in the idle thread loop.
- */
-#if !defined(CORTEX_ENABLE_WFI_IDLE)
-#define CORTEX_ENABLE_WFI_IDLE          FALSE
-#endif
-
-/**
- * @brief   SYSTICK handler priority.
- * @note    The default SYSTICK handler priority is calculated as the priority
- *          level in the middle of the numeric priorities range.
- */
-#if !defined(CORTEX_PRIORITY_SYSTICK)
-#define CORTEX_PRIORITY_SYSTICK         (CORTEX_PRIORITY_LEVELS >> 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
-
-/**
- * @brief   FPU support in context switch.
- * @details Activating this option activates the FPU support in the kernel.
- */
-#if !defined(CORTEX_USE_FPU)
-#define CORTEX_USE_FPU                  CORTEX_HAS_FPU
-#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
-/* This setting requires an FPU presence check in case it is externally
-   redefined.*/
-#error "the selected core does not have an FPU"
-#endif
-
-/**
- * @brief   Simplified priority handling flag.
- * @details Activating this option makes the Kernel work in compact mode.
- */
-#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
-#define CORTEX_SIMPLIFIED_PRIORITY      FALSE
-#endif
-
-/**
- * @brief   SVCALL handler priority.
- * @note    The default SVCALL handler priority is defaulted to
- *          @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
- *          @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
- *          priority level.
- */
-#if !defined(CORTEX_PRIORITY_SVCALL)
-#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
-#endif
-
-/**
- * @brief   NVIC VTOR initialization expression.
- */
-#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
-#define CORTEX_VTOR_INIT                0x00000000
-#endif
-
-/**
- * @brief   NVIC PRIGROUP initialization expression.
- * @details The default assigns all available priority bits as preemption
- *          priority with no sub-priority.
- */
-#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
-#define CORTEX_PRIGROUP_INIT            (7 - CORTEX_PRIORITY_BITS)
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters.                                                  */
-/*===========================================================================*/
-
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief   Maximum usable priority for normal ISRs.
- */
-#define CORTEX_MAX_KERNEL_PRIORITY      (CORTEX_PRIORITY_SVCALL + 1)
-
-/**
- * @brief   BASEPRI level within kernel lock.
- * @note    In compact kernel mode this constant value is enforced to zero.
- */
-#define CORTEX_BASEPRI_KERNEL                                               \
-  CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY)
-#else
-
-#define CORTEX_MAX_KERNEL_PRIORITY      1
-#define CORTEX_BASEPRI_KERNEL           0
-#endif
-
-/**
- * @brief   PendSV priority level.
- * @note    This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,
- *          this handler always have the highest priority that cannot preempt
- *          the kernel.
- */
-#define CORTEX_PRIORITY_PENDSV          CORTEX_BASEPRI_KERNEL
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
-/**
- * @brief   Macro defining the specific ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM_v7M
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "ARMv7-M"
-
-/**
- * @brief   Name of the architecture variant.
- */
-#define CH_CORE_VARIANT_NAME            "Cortex-M3"
-
-#elif (CORTEX_MODEL == CORTEX_M4)
-#define CH_ARCHITECTURE_ARM_v7ME
-#define CH_ARCHITECTURE_NAME            "ARMv7-ME"
-#if CORTEX_USE_FPU
-#define CH_CORE_VARIANT_NAME            "Cortex-M4F"
-#else
-#define CH_CORE_VARIANT_NAME            "Cortex-M4"
-#endif
-#endif
-
-/**
- * @brief   Port-specific information string.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define CH_PORT_INFO                    "Advanced kernel mode"
-#else
-#define CH_PORT_INFO                    "Compact kernel mode"
-#endif
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-/**
- * @brief   Generic ARM register.
- */
-typedef void *regarm_t;
-
-/**
- * @brief   Stack and memory alignment enforcement.
- * @note    In this architecture the stack alignment is enforced to 64 bits,
- *          32 bits alignment is supported by hardware but deprecated by ARM,
- *          the implementation choice is to not offer the option.
- */
-typedef uint64_t stkalign_t;
-
-/* The documentation of the following declarations is in chconf.h in order
-   to not have duplicated structure names into the documentation.*/
-#if !defined(__DOXYGEN__)
-
-struct extctx {
-  regarm_t      r0;
-  regarm_t      r1;
-  regarm_t      r2;
-  regarm_t      r3;
-  regarm_t      r12;
-  regarm_t      lr_thd;
-  regarm_t      pc;
-  regarm_t      xpsr;
-#if CORTEX_USE_FPU
-  regarm_t      s0;
-  regarm_t      s1;
-  regarm_t      s2;
-  regarm_t      s3;
-  regarm_t      s4;
-  regarm_t      s5;
-  regarm_t      s6;
-  regarm_t      s7;
-  regarm_t      s8;
-  regarm_t      s9;
-  regarm_t      s10;
-  regarm_t      s11;
-  regarm_t      s12;
-  regarm_t      s13;
-  regarm_t      s14;
-  regarm_t      s15;
-  regarm_t      fpscr;
-  regarm_t      fpccr;
-#endif /* CORTEX_USE_FPU */
-};
-
-struct intctx {
-#if CORTEX_USE_FPU
-  regarm_t      s16;
-  regarm_t      s17;
-  regarm_t      s18;
-  regarm_t      s19;
-  regarm_t      s20;
-  regarm_t      s21;
-  regarm_t      s22;
-  regarm_t      s23;
-  regarm_t      s24;
-  regarm_t      s25;
-  regarm_t      s26;
-  regarm_t      s27;
-  regarm_t      s28;
-  regarm_t      s29;
-  regarm_t      s30;
-  regarm_t      s31;
-#endif /* CORTEX_USE_FPU */
-  regarm_t      r4;
-  regarm_t      r5;
-  regarm_t      r6;
-  regarm_t      r7;
-  regarm_t      r8;
-  regarm_t      r9;
-  regarm_t      r10;
-  regarm_t      r11;
-  regarm_t      lr;
-};
-
-#endif /* !defined(__DOXYGEN__) */
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- *          structure representing the stack pointer at context switch time.
- */
-struct context {
-  struct intctx *r13;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
-                                     wsize -                                \
-                                     sizeof(struct intctx));                \
-  tp->p_ctx.r13->r4 = (regarm_t)pf;                                         \
-  tp->p_ctx.r13->r5 = (regarm_t)arg;                                        \
-  tp->p_ctx.r13->lr = (regarm_t)_port_thread_start;                         \
-}
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Fast IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_FAST_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Port-related initialization code.
- */
-#define port_init() _port_init()
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform
- *          more actions.
- * @note    In this port this it raises the base priority to kernel level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_lock() __set_BASEPRI(CORTEX_BASEPRI_KERNEL)
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_lock() __disable_interrupt()
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform
- *          more actions.
- * @note    In this port this it lowers the base priority to user level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_unlock() __set_BASEPRI(CORTEX_BASEPRI_DISABLED)
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_unlock() __enable_interrupt()
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependent,
- *          in its simplest form it is void.
- * @note    Same as @p port_lock() in this port.
- */
-#define port_lock_from_isr() port_lock()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- * @note    Same as @p port_unlock() in this port.
- */
-#define port_unlock_from_isr() port_unlock()
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Of course non-maskable interrupt sources are not included.
- * @note    In this port it disables all the interrupt sources by raising
- *          the priority mask to level 0.
- */
-#define port_disable() __disable_interrupt()
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- * @note    Interrupt sources above kernel level remains enabled.
- * @note    In this port it raises/lowers the base priority to kernel level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_suspend() {                                                    \
-  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);                                     \
-  __enable_interrupt();                                                     \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_suspend() __disable_interrupt()
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Enables all the interrupt sources.
- * @note    In this port it lowers the base priority to user level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_enable() {                                                     \
-  __set_BASEPRI(CORTEX_BASEPRI_DISABLED);                                   \
-  __enable_interrupt();                                                     \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_enable() __enable_interrupt()
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- * @note    Implemented as an inlined @p WFI instruction.
- */
-#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() asm ("wfi")
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-#else
-#define port_switch(ntp, otp) {                                             \
-  if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \
-    chDbgPanic("stack overflow");                                           \
-  _port_switch(ntp, otp);                                                   \
-}
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_halt(void);
-  void _port_init(void);
-  void _port_irq_epilogue(void);
-  void _port_switch_from_isr(void);
-  void _port_exit_from_isr(void);
-  void _port_switch(Thread *ntp, Thread *otp);
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_V7M_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s
deleted file mode 100644
index d2149ea59..000000000
--- a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-        MODULE  ?chcoreasm_v6m
-
-        AAPCS INTERWORK, VFP_COMPATIBLE
-        PRESERVE8
-
-/*
- * Imports the Cortex-Mx configuration headers.
- */
-#define _FROM_ASM_
-#include "chconf.h"
-#include "chcore.h"
-
-CONTEXT_OFFSET  SET     12
-SCB_ICSR        SET     0xE000ED04
-
-        SECTION .text:CODE:NOROOT(2)
-
-        EXTERN  chThdExit
-        EXTERN  chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-        EXTERN  dbg_check_unlock
-        EXTERN  dbg_check_lock
-#endif
-
-        THUMB
-
-/*
- * Performs a context switch between two threads.
- */
-        PUBLIC _port_switch
-_port_switch:
-        push    {r4, r5, r6, r7, lr}
-        mov     r4, r8
-        mov     r5, r9
-        mov     r6, r10
-        mov     r7, r11
-        push    {r4, r5, r6, r7}
-        mov     r3, sp
-        str     r3, [r1, #CONTEXT_OFFSET]
-        ldr     r3, [r0, #CONTEXT_OFFSET]
-        mov     sp, r3
-        pop     {r4, r5, r6, r7}
-        mov     r8, r4
-        mov     r9, r5
-        mov     r10, r6
-        mov     r11, r7
-        pop     {r4, r5, r6, r7, pc}
-
-/*
- * Start a thread by invoking its work function.
- * If the work function returns @p chThdExit() is automatically invoked.
- */
-        PUBLIC  _port_thread_start
-_port_thread_start:
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_unlock
-#endif
-        cpsie   i
-        mov     r0, r5
-        blx     r4
-        bl      chThdExit
-
-/*
- * Post-IRQ switch code.
- * Exception handlers return here for context switching.
- */
-        PUBLIC  _port_switch_from_isr
-        PUBLIC  _port_exit_from_isr
-_port_switch_from_isr:
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_lock
-#endif
-        bl      chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_unlock
-#endif
-_port_exit_from_isr:
-        ldr     r2, =SCB_ICSR
-        movs    r3, #128
-#if CORTEX_ALTERNATE_SWITCH
-        lsls    r3, r3, #21
-        str     r3, [r2, #0]
-        cpsie   i
-#else
-        lsls    r3, r3, #24
-        str     r3, [r2, #0]
-#endif
-waithere:
-        b       waithere
-
-        END
diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v7m.s b/os/ports/IAR/ARMCMx/chcoreasm_v7m.s
deleted file mode 100644
index ca077431d..000000000
--- a/os/ports/IAR/ARMCMx/chcoreasm_v7m.s
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-        MODULE  ?chcoreasm_v7m
-
-        AAPCS INTERWORK, VFP_COMPATIBLE
-        PRESERVE8
-
-/*
- * Imports the Cortex-Mx configuration headers.
- */
-#define _FROM_ASM_
-#include "chconf.h"
-#include "chcore.h"
-
-CONTEXT_OFFSET  SET 12
-SCB_ICSR        SET 0xE000ED04
-ICSR_PENDSVSET  SET 0x10000000
-
-        SECTION .text:CODE:NOROOT(2)
-
-        EXTERN  chThdExit
-        EXTERN  chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-        EXTERN  dbg_check_unlock
-        EXTERN  dbg_check_lock
-#endif
-
-        THUMB
-
-/*
- * Performs a context switch between two threads.
- */
-        PUBLIC _port_switch
-_port_switch:
-        push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-#if CORTEX_USE_FPU
-        vpush   {s16-s31}
-#endif
-        str     sp, [r1, #CONTEXT_OFFSET]
-        ldr     sp, [r0, #CONTEXT_OFFSET]
-#if CORTEX_USE_FPU
-        vpop    {s16-s31}
-#endif
-        pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}
-
-/*
- * Start a thread by invoking its work function.
- * If the work function returns @p chThdExit() is automatically invoked.
- */
-        PUBLIC  _port_thread_start
-_port_thread_start:
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_unlock
-#endif
-#if CORTEX_SIMPLIFIED_PRIORITY
-        cpsie   i
-#else
-        movs    r3, #CORTEX_BASEPRI_DISABLED
-        msr     BASEPRI, r3
-#endif
-        mov     r0, r5
-        blx     r4
-        bl      chThdExit
-
-/*
- * Post-IRQ switch code.
- * Exception handlers return here for context switching.
- */
-        PUBLIC  _port_switch_from_isr
-        PUBLIC  _port_exit_from_isr
-_port_switch_from_isr:
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_lock
-#endif
-        bl      chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-        bl      dbg_check_unlock
-#endif
-_port_exit_from_isr:
-#if CORTEX_SIMPLIFIED_PRIORITY
-        mov     r3, #LWRD SCB_ICSR
-        movt    r3, #HWRD SCB_ICSR
-        mov	r2, #ICSR_PENDSVSET
-        str	r2, [r3]
-        cpsie   i
-.L3:    b       .L3
-#else
-        svc     #0
-#endif
-
-        END
diff --git a/os/ports/IAR/ARMCMx/chtypes.h b/os/ports/IAR/ARMCMx/chtypes.h
deleted file mode 100644
index d2a55bbfe..000000000
--- a/os/ports/IAR/ARMCMx/chtypes.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/ARMCMx/chtypes.h
- * @brief   ARM Cortex-Mx port system types.
- *
- * @addtogroup IAR_ARMCMx_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint32_t        tprio_t;        /**< Thread priority.               */
-typedef int32_t         msg_t;          /**< Inter-thread message.          */
-typedef int32_t         eventid_t;      /**< Event Id.                      */
-typedef uint32_t        eventmask_t;    /**< Event mask.                    */
-typedef uint32_t        flagsmask_t;    /**< Event flags.                   */
-typedef uint32_t        systime_t;      /**< System time.                   */
-typedef int32_t         cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_STRUCT
-
-/**
- * @brief   Packed structure modifier (before).
- */
-#define PACK_STRUCT_BEGIN __packed
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-/**
- * @brief   Packed variable specifier.
- */
-#define PACKED_VAR __packed
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/ARMCMx/cstartup.s b/os/ports/IAR/ARMCMx/cstartup.s
deleted file mode 100644
index 3ee52d0a1..000000000
--- a/os/ports/IAR/ARMCMx/cstartup.s
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-        MODULE  ?cstartup
-
-CONTROL_MODE_PRIVILEGED SET 0
-CONTROL_MODE_UNPRIVILEGED SET 1
-CONTROL_USE_MSP SET 0
-CONTROL_USE_PSP SET 2
-
-        AAPCS INTERWORK, VFP_COMPATIBLE, ROPI
-        PRESERVE8
-
-        SECTION .intvec:CODE:NOROOT(3)
-
-        SECTION CSTACK:DATA:NOROOT(3)
-        PUBLIC  __main_thread_stack_base__
-__main_thread_stack_base__:
-        PUBLIC  __heap_end__
-__heap_end__:
-
-        SECTION SYSHEAP:DATA:NOROOT(3)
-        PUBLIC  __heap_base__
-__heap_base__:
-
-        PUBLIC  __iar_program_start
-        EXTERN  __vector_table
-        EXTWEAK __iar_init_core
-        EXTWEAK __iar_init_vfp
-        EXTERN  __cmain
-
-        SECTION .text:CODE:REORDER(2)
-        REQUIRE __vector_table
-        THUMB
-__iar_program_start:
-        cpsid   i
-        ldr     r0, =SFE(CSTACK)
-        msr     PSP, r0
-        movs    r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
-        msr     CONTROL, r0
-        isb
-        bl      __early_init
-        bl      __iar_init_core
-        bl      __iar_init_vfp
-        b       __cmain
-
-        PUBWEAK __early_init
-__early_init:
-        bx      lr
-
-        END
diff --git a/os/ports/IAR/ARMCMx/port.dox b/os/ports/IAR/ARMCMx/port.dox
deleted file mode 100644
index 5336c14cf..000000000
--- a/os/ports/IAR/ARMCMx/port.dox
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup IAR_ARMCMx ARM Cortex-Mx
- * @details ARM Cortex-Mx port for the IAR compiler.
- 
- * @section IAR_ARMCMx_INTRO Introduction
- * This port supports all the cores implementing the ARMv6-M and ARMv7-M
- * architectures.
- *
- * @section IAR_ARMCMx_MODES Kernel Modes
- * The Cortex-Mx port supports two distinct kernel modes:
- * - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
- *   interrupt sources with priorities below or equal to the
- *   @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
- *   the kernel critical sections and can be used for fast interrupts.
- *   This mode is not available in the ARMv6-M architecture which does not
- *   support priority masking.
- * - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
- *   in a simplified way, all interrupt sources are disabled when the kernel
- *   enters into a critical zone and re-enabled on exit. This is simple and
- *   adequate for most applications, this mode results in a more compact and
- *   faster kernel.
- * .
- * The selection of the mode is performed using the port configuration option
- * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
- * interrupts there are no other differences between the two modes. The
- * kernel API is exactly the same.
- *
- * @section IAR_ARMCMx_STATES_A System logical states in Compact Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
- * Kernel mode:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). In this state interrupts are enabled. The processor
- *   is running in thread-privileged mode.
- * - <b>Suspended</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in thread-privileged mode. In this
- *   mode this state is not different from the <b>Disabled</b> state.
- * - <b>Disabled</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in thread-privileged mode. In this
- *   mode this state is not different from the <b>Suspended</b> state.
- * - <b>Sleep</b>. This state is entered with the execution of the specific
- *   instruction @p <b>wfi</b>.
- * - <b>S-Locked</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in thread-privileged mode.
- * - <b>I-Locked</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in exception-privileged mode.
- * - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
- *   not globally masked but only interrupts with higher priority can preempt
- *   the current handler. The processor is running in exception-privileged
- *   mode.
- * - <b>Serving Fast Interrupt</b>. Not implemented in compact kernel mode.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
- *   asynchronous NMI vector and several synchronous fault vectors that can
- *   be considered belonging to this category.
- * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
- *   the maskable interrupt sources. The ARM state is whatever the processor
- *   was running when @p chSysHalt() was invoked.
- *
- * @section IAR_ARMCMx_STATES_B System logical states in Advanced Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the
- * Advanced Kernel mode:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
- *   set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
- *   processor is running in thread-privileged mode.
- * - <b>Suspended</b>. In this state the interrupt sources are not globally
- *   masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- *   masking any interrupt source with lower or equal priority. The processor
- *   is running in thread-privileged mode.
- * - <b>Disabled</b>. Interrupt sources are globally masked. The processor
- *   is running in thread-privileged mode.
- * - <b>Sleep</b>. This state is entered with the execution of the specific
- *   instruction @p <b>wfi</b>.
- * - <b>S-Locked</b>. In this state the interrupt sources are not globally
- *   masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- *   masking any interrupt source with lower or equal priority. The processor
- *   is running in thread-privileged mode.
- * - <b>I-Locked</b>. In this state the interrupt sources are not globally
- *   masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- *   masking any interrupt source with lower or equal priority. The processor
- *   is running in exception-privileged mode.
- * - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
- *   not globally masked but only interrupts with higher priority can preempt
- *   the current handler. The processor is running in exception-privileged
- *   mode.
- * - <b>Serving Fast Interrupt</b>. Fast interrupts are defined as interrupt
- *   sources having higher priority level than the kernel
- *   (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to
- *   the I-Locked state because fast interrupts can preempt the kernel
- *   critical zone.<br>
- *   This state is not implemented in the ARMv6-M implementation because
- *   priority masking is not present in this architecture.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
- *   asynchronous NMI vector and several synchronous fault vectors that can
- *   be considered belonging to this category.
- * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
- *   the maskable interrupt sources. The ARM state is whatever the processor
- *   was running when @p chSysHalt() was invoked.
- * .
- * @section IAR_ARMCMx_NOTES ARM Cortex-Mx/IAR port notes
- * The ARM Cortex-Mx port is organized as follow:
- * - The @p main() function is invoked in thread-privileged mode.
- * - Each thread has a private process stack, the system has a single main
- *   stack where all the interrupts and exceptions are processed.
- * - The threads are started in thread-privileged mode.
- * - Interrupt nesting and the other advanced core/NVIC features are supported.
- * - The Cortex-Mx port is perfectly generic, support for more devices can be
- *   easily added by adding a subdirectory under <tt>./os/ports/IAR/ARMCMx</tt>
- *   and giving it the name of the new device, then copy the files from another
- *   device into the new directory and customize them for the new device.
- * .
- * @ingroup iar
- */
-
-/**
- * @defgroup IAR_ARMCMx_CONF Configuration Options
- * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some
- * architecture-specific configurations settings that can be overridden
- * by redefining them in @p chconf.h. Usually there is no need to change
- * the default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
- *   by an interrupt handler between the @p extctx and @p intctx
- *   structures.
- * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
- *   thread. Usually there is no need to change this value unless inserting
- *   code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
- * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
- * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
- * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
- *   @p <b>wfi</b> instruction from within the idle loop. This option is
- *   defaulted to FALSE because it can create problems with some debuggers.
- *   Setting this option to TRUE reduces the system power requirements.
- * .
- * @section IAR_ARMCMx_CONF_1 ARMv6-M specific options
- * The following options are specific for the ARMv6-M architecture:
- * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
- *   exception instead of NMI as preemption handler.
- * .
- * @section IAR_ARMCMx_CONF_2 ARMv7-M specific options
- * The following options are specific for the ARMv6-M architecture:
- * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
- * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
- *   mode.
- * .
- * @ingroup IAR_ARMCMx
- */
-
-/**
- * @defgroup IAR_ARMCMx_CORE Core Port Implementation
- * @details ARM Cortex-Mx specific port code, structures and macros.
- *
- * @ingroup IAR_ARMCMx
- */
-
-/**
- * @defgroup IAR_ARMCMx_V6M_CORE ARMv6-M Specific Implementation
- * @details ARMv6-M specific port code, structures and macros.
- *
- * @ingroup IAR_ARMCMx_CORE
- */
-
-/**
- * @defgroup IAR_ARMCMx_V7M_CORE ARMv7-M Specific Implementation
- * @details ARMv7-M specific port code, structures and macros.
- *
- * @ingroup IAR_ARMCMx_CORE
- */
-
-/**
- * @defgroup IAR_ARMCMx_STARTUP Startup Support
- * @details ChibiOS/RT provides its own generic startup file for the ARM
- * Cortex-Mx port.
- * Of course it is not mandatory to use it but care should be taken about the
- * startup phase details.
- *
- * @section IAR_ARMCMx_STARTUP_1 Startup Process
- * The startup process, as implemented, is the following:
- * -# Interrupts are masked globally.
- * -# The two stacks are initialized by assigning them the sizes defined in the
- *    linker script (usually named @p ch.icf).
- * -# The CPU state is switched to Privileged and the PSP stack is used.
- * -# An early initialization routine @p __early_init() is invoked, if the
- *    symbol is not defined then an empty default routine is executed
- *    (weak symbol).
- * -# Control is passed to the C runtime entry point @p __cmain that performs
- *    the required initializations before invoking the @p main() function.
- * .
- * @ingroup IAR_ARMCMx
- */
-
-/**
- * @defgroup IAR_ARMCMx_NVIC NVIC Support
- * @details ARM Cortex-Mx NVIC support.
- *
- * @ingroup IAR_ARMCMx
- */
-
-/**
- * @defgroup IAR_ARMCMx_SPECIFIC Specific Implementations
- * @details Platform-specific port code.
- *
- * @ingroup IAR_ARMCMx
- */
diff --git a/os/ports/IAR/STM8/chcore.c b/os/ports/IAR/STM8/chcore.c
deleted file mode 100644
index 020c1cfb0..000000000
--- a/os/ports/IAR/STM8/chcore.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    cosmic/STM8/chcore.c
- * @brief   STM8 (Cosmic) architecture port code.
- *
- * @addtogroup STM8_COSMIC_CORE
- * @{
- */
-
-#include "ch.h"
-
-__tiny ReadyList rlist;
-
-/**
- * @brief   Thread start code.
- */
-__task void _port_thread_start(void) {
-  chSysUnlock();
-  asm("popw x");
-}
-
-/**
- * @brief   Halts the system.
- * @details This function is invoked by the operating system when an
- *          unrecoverable error is detected (for example because a programming
- *          error in the application code that triggers an assertion while in
- *          debug mode).
- */
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/** @} */
diff --git a/os/ports/IAR/STM8/chcore.h b/os/ports/IAR/STM8/chcore.h
deleted file mode 100644
index 29bf5087c..000000000
--- a/os/ports/IAR/STM8/chcore.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    cosmic/STM8/chcore.h
- * @brief   STM8 (Cosmic) architecture port macros and structures.
- *
- * @addtogroup STM8_COSMIC_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-#if CH_DBG_ENABLE_STACK_CHECK
-#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port"
-#endif
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Enables the use of the WFI instruction in the idle thread loop.
- */
-#ifndef STM8_ENABLE_WFI_IDLE
-#define STM8_ENABLE_WFI_IDLE            FALSE
-#endif
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Unique macro for the implemented architecture.
- */
-#define CH_ARCHITECTURE_STM8
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "STM8"
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "IAR"
-
-/**
- * @brief   Port-specific information string.
- */
-#define CH_PORT_INFO                    "None"
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Base type for stack alignment.
- * @note    No alignment constraints so uint8_t.
- */
-typedef uint8_t stkalign_t;
-
-/**
- * @brief   Generic STM8 function pointer.
- * @note    It is used to allocate the proper size for return addresses in
- *          context-related structures.
- */
-typedef void (*stm8func_t)(void);
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- * @note    The structure requires one dummy field at its start because the
- *          stack is handled as preincremented/postdecremented.
- */
-struct extctx {
-  uint8_t       _next;
-  uint16_t      w3;
-  uint16_t      w2;
-  uint16_t      w1;
-  uint16_t      w0;
-  uint8_t       cc;
-  uint8_t       a;
-  uint16_t      x;
-  uint16_t      y;
-  uint8_t       pce;
-  uint8_t       pch;
-  uint8_t       pcl;
-};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching..
- * @note    The structure requires one dummy field at its start because the
- *          stack is handled as preincremented/postdecremented.
- */
-struct intctx {
-  uint8_t       _next;
-  uint16_t      w7;
-  uint16_t      w6;
-  uint16_t      w5;
-  uint16_t      w4;
-  stm8func_t    pc;             /* Function pointer sized return address.   */
-};
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details This structure usually contains just the saved stack pointer
- *          defined as a pointer to a @p intctx structure.
- */
-struct context {
-  struct intctx *sp;
-};
-
-/**
- * @brief   Start context.
- * @details This context is the stack organization for the trampoline code
- *          @p _port_thread_start().
- */
-struct stm8_startctx {
-  uint8_t       saved_vreg[8];  // saved virtual registers to restore
-  uint8_t       _next;
-  stm8func_t    ts;             /* Trampoline address.                      */
-  void          *arg;           /* Thread argument.                         */
-  stm8func_t    pc;             /* Thread function address.                 */
-  stm8func_t    ret;            /* chThdExit() address.                     */
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  struct stm8_startctx *scp;                                                \
-  scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize -             \
-                                 sizeof(struct stm8_startctx));             \
-  scp->ts   = (stm8func_t)_port_thread_start;                               \
-  scp->arg  = (void *)arg;                                                  \
-  scp->pc   = (stm8func_t)pf;                                               \
-  scp->ret  = (stm8func_t)chThdExit;                                        \
-  tp->p_ctx.sp = (struct intctx *)scp;                                      \
-}
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     0
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This is a safe value, you may trim it down after reading the
- *          right size in the map file.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK         48
-#endif
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   (sizeof(struct intctx) - 1) +            \
-                                   (sizeof(struct extctx) - 1) +            \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() {                                               \
-  dbg_check_lock();                                                         \
-  if (chSchIsPreemptionRequired())                                          \
-    chSchDoReschedule();                                                    \
-  dbg_check_unlock();                                                       \
-}
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id)                                                \
-  _Pragma(VECTOR_ID((id)+2)) __interrupt void vector##id(void)
-
-/**
- * @brief   Port-related initialization code.
- * @note    None in this port.
- */
-#define port_init()
-
-/**
- * @brief   Kernel-lock action.
- * @note    Implemented as global interrupts disable.
- */
-#define port_lock() asm("sim")
-
-/**
- * @brief   Kernel-unlock action.
- * @note    Implemented as global interrupts enable.
- */
-#define port_unlock() asm("rim")
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @note    This function is empty in this port.
- */
-#define port_lock_from_isr()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @note    This function is empty in this port.
- */
-#define port_unlock_from_isr()
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Implemented as global interrupts disable.
- * @note    Of course non-maskable interrupt sources are not included.
- */
-#define port_disable() asm("sim")
-
-/**
- * @brief   Disables the interrupt sources that are not supposed to preempt
- *          the kernel.
- * @note    Same as @p port_disable() in this port, there is no difference
- *          between the two states.
- */
-#define port_suspend() asm("sim")
-
-/**
- * @brief   Enables all the interrupt sources.
- * @note    Implemented as global interrupt enable.
- */
-#define port_enable() asm("rim")
-
-/**
- * @brief   Enters an architecture-dependent halt mode.
- * @note    Implemented with the specific "wfi" instruction.
- */
-#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() asm("wfi")
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    Implemented as a call to a low level assembler routine.
- *
- * @param ntp   the thread to be switched in
- * @param otp   the thread to be switched out
- */
-#define port_switch(ntp, otp) _port_switch(otp)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _port_switch(Thread *otp);
-  __task void _port_thread_start(void);
-  void port_halt(void);
-#ifdef __cplusplus
-}
-#endif
-
-/*===========================================================================*/
-/* Scheduler captured code.                                                  */
-/*===========================================================================*/
-
-#define PORT_OPTIMIZED_RLIST_VAR
-#define PORT_OPTIMIZED_RLIST_EXT
-#define PORT_OPTIMIZED_READYLIST_STRUCT
-
-typedef struct {
-  ThreadsQueue          r_queue;
-  tprio_t               r_prio;
-  Thread                *r_current;
-#if CH_USE_REGISTRY
-  Thread                *r_newer;
-  Thread                *r_older;
-#endif
-  /* End of the fields shared with the Thread structure.*/
-#if CH_TIME_QUANTUM > 0
-  cnt_t                 r_preempt;
-#endif
-} ReadyList;
-
-extern __tiny ReadyList rlist;
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/STM8/chcore_stm8.s b/os/ports/IAR/STM8/chcore_stm8.s
deleted file mode 100644
index 6dc719c5c..000000000
--- a/os/ports/IAR/STM8/chcore_stm8.s
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-; Get definitions for virtual registers used by the compiler
-#include "vregs.inc"
-
-	SECTION .near_func.text:code
-	EXTERN rlist
-
-/*
- * Performs a context switch between two threads.
- */
-        PUBLIC _port_switch
-_port_switch:
-	push    ?b8
-	push    ?b9
-	push    ?b10
-	push    ?b11
-	push    ?b12
-	push    ?b13
-	push    ?b14
-	push    ?b15
-
-	ldw     y,sp
-	ldw     (5,x),y
-	ldw     x, rlist + 5
-	ldw     x,(5,x)
-	ldw     sp,x
-
-	pop     ?b15
-	pop     ?b14
-	pop     ?b13
-	pop     ?b12
-	pop     ?b11
-	pop     ?b10
-	pop     ?b9
-	pop     ?b8
-	ret
-
-        END
diff --git a/os/ports/IAR/STM8/chtypes.h b/os/ports/IAR/STM8/chtypes.h
deleted file mode 100644
index f418256e1..000000000
--- a/os/ports/IAR/STM8/chtypes.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    IAR/STM8/chtypes.h
- * @brief   STM8 (IAR) port system types.
- *
- * @addtogroup STM8_IAR_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint8_t         tprio_t;        /**< Thread priority.               */
-typedef int16_t         msg_t;          /**< Inter-thread message.          */
-typedef int8_t          eventid_t;      /**< Event Id.                      */
-typedef uint8_t         eventmask_t;    /**< Event mask.                    */
-typedef uint8_t         flagsmask_t;    /**< Event flags.                   */
-typedef uint16_t        systime_t;      /**< System time.                   */
-typedef int8_t          cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    Uses the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_STRUCT
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/IAR/STM8/port.dox b/os/ports/IAR/STM8/port.dox
deleted file mode 100644
index c0eb35cdd..000000000
--- a/os/ports/IAR/STM8/port.dox
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup STM8_IAR STM8
- * @details STM8 port for the Cosmic C compiler.
- *
- * @section STM8_IAR_INTRO Introduction
- * This port supports all STM8 8 bits MCUs.
- *
- * @section STM8_IAR_STATES Mapping of the System States in the STM8 port
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8
- * port:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). Interrupts are enabled.
- * - <b>Suspended</b>. Interrupts are disabled.
- * - <b>Disabled</b>. Interrupts are disabled. This state is equivalent to the
- *   Suspended state because there are no fast interrupts in this architecture.
- * - <b>Sleep</b>. Implemented with "wait" instruction insertion in the idle
- *   loop.
- * - <b>S-Locked</b>. Interrupts are disabled.
- * - <b>I-Locked</b>. This state is equivalent to the SRI state, the
- *   @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
- *   order to formally change state because this may change).
- * - <b>Serving Regular Interrupt</b>. Normal interrupt service code.
- * - <b>Serving Fast Interrupt</b>. Not present in this architecture.
- * - <b>Serving Non-Maskable Interrupt</b>. The STM8 ha non
- *   maskable interrupt sources that can be associated to this state.
- * - <b>Halted</b>. Implemented as an infinite loop with interrupts disabled.
- * .
- * @section STM8_IAR_NOTES The STM8 port notes
- * - The STM8 does not have a dedicated interrupt stack, make sure to reserve
- *     enough stack space for interrupts in each thread stack. This can be done
- *     by modifying the @p INT_REQUIRED_STACK macro into
- *     <b>./os/ports/IAR/STM8/chcore.h</b>.
- * - The kernel currently supports only the small memory model so the
- *   kernel files should be loaded in the first 64K. Note that this is not
- *   a problem because upper addresses can be used by the user code, the
- *   kernel can context switch code running there.
- * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported
- *   because the missing support of the @p inline "C" keyword in the
- *   compiler.
- * .
- * @ingroup iar
- */
-
-/**
- * @defgroup STM8_IAR_CONF Configuration Options
- * @details STM8 Configuration Options. The STM8 port allows some
- * architecture-specific configurations settings that can be overridden
- * by redefining them in @p chconf.h. Usually there is no need to change
- * the default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space
- *   used by the interrupt handlers.<br>
- *   The default for this value is @p 48, this space is allocated for each
- *   thread so be careful in order to not waste precious RAM space.
- * .
- * @ingroup STM8_IAR
- */
-
-/**
- * @defgroup STM8_IAR_CORE Core Port Implementation
- * @details STM8 specific port code, structures and macros.
- *
- * @ingroup STM8_IAR
- */
-
- /**
- * @defgroup STM8_IAR_STARTUP Startup Support
- * @details ChibiOS/RT doed not provide startup files for the STM8, there
- * are no special startup requirement so the normal toolchain-provided
- * startup files can be used.
- *
- * @ingroup STM8_IAR
- */
diff --git a/os/ports/RC/STM8/chcore.c b/os/ports/RC/STM8/chcore.c
deleted file mode 100644
index 1b4c1d0a4..000000000
--- a/os/ports/RC/STM8/chcore.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RC/STM8/chcore.c
- * @brief   STM8 (Raisonance) architecture port code.
- *
- * @addtogroup STM8_RAISONANCE_CORE
- * @{
- */
-#pragma SRC("tmp.asm")
-
-#include "ch.h"
-
-page0 ReadyList rlist;
-
-/**
- * @brief   Performs a context switch between two threads.
- *
- * @param otp   the thread to be switched out
- */
-void _port_switch(Thread *otp) {
-
-  (void)otp;
-  /* Asm because unoptimal code would generated by using _getSP_().*/
-#pragma ASM
-        LDW     Y,SP                ; old context pointer
-        LDW     (5,X),Y             ; SP saved in otp->p_ctx.sp
-        LDW     X,rlist + 5         ; r_current (currp) field
-        LDW     X,(5,X)             ; currp->p_ctx.sp
-        LDW     SP,X                ; new context pointer
-#pragma ENDASM
-}
-
-/**
- * @brief   Thread start code.
- */
-void _port_thread_start(void) {
-
-  chSysUnlock();
-#pragma ASM
-        POPW    X
-#pragma ENDASM
-}
-
-/**
- * @brief   Halts the system.
- * @details This function is invoked by the operating system when an
- *          unrecoverable error is detected (for example because a programming
- *          error in the application code that triggers an assertion while in
- *          debug mode).
- */
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/** @} */
diff --git a/os/ports/RC/STM8/chcore.h b/os/ports/RC/STM8/chcore.h
deleted file mode 100644
index 716c8ff74..000000000
--- a/os/ports/RC/STM8/chcore.h
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RC/STM8/chcore.h
- * @brief   STM8 (Raisonance) architecture port macros and structures.
- *
- * @addtogroup STM8_RAISONANCE_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-#include <intrins.h>
-
-#if CH_DBG_ENABLE_STACK_CHECK
-#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port"
-#endif
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Enables the use of the WFI instruction in the idle thread loop.
- */
-#ifndef STM8_ENABLE_WFI_IDLE
-#define STM8_ENABLE_WFI_IDLE            FALSE
-#endif
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Unique macro for the implemented architecture.
- */
-#define CH_ARCHITECTURE_STM8
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "STM8"
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "Raisonance"
-
-/**
- * @brief   Port-specific information string.
- */
-#define CH_PORT_INFO                    "None"
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Base type for stack alignment.
- * @note    No alignment constraints so uint8_t.
- */
-typedef uint8_t stkalign_t;
-
-/**
- * @brief   Generic STM8 function pointer.
- * @note    It is used to allocate the proper size for return addresses in
- *          context-related structures.
- */
-typedef void (*stm8func_t)(void);
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- * @note    The structure requires one dummy field at its start because the
- *          stack is handled as preincremented/postdecremented.
- */
-struct extctx {
-  uint8_t       _next;
-  uint16_t      cx;
-  uint16_t      bx;
-  uint8_t       cc;
-  uint8_t       a;
-  uint16_t      x;
-  uint16_t      y;
-  uint8_t       pce;
-  uint8_t       pch;
-  uint8_t       pcl;
-};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching..
- * @note    The structure requires one dummy field at its start because the
- *          stack is handled as preincremented/postdecremented.
- */
-struct intctx {
-  uint8_t       _next;
-  stm8func_t    pc;             /* Function pointer sized return address.   */
-};
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details This structure usually contains just the saved stack pointer
- *          defined as a pointer to a @p intctx structure.
- */
-struct context {
-  struct intctx *sp;
-};
-
-/**
- * @brief   Start context.
- * @details This context is the stack organization for the trampoline code
- *          @p _port_thread_start().
- */
-struct stm8_startctx {
-  uint8_t       _next;
-  stm8func_t    ts;             /* Trampoline address.                      */
-  void          *arg;           /* Thread argument.                         */
-  stm8func_t    pc;             /* Thread function address.                 */
-  stm8func_t    ret;            /* chThdExit() address.                     */
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  struct stm8_startctx *scp;                                                \
-  scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize -             \
-                                 sizeof(struct stm8_startctx));             \
-  scp->ts   = _port_thread_start;                                           \
-  scp->arg  = arg;                                                          \
-  scp->pc   = (stm8func_t)pf;                                               \
-  scp->ret  = (stm8func_t)chThdExit;                                        \
-  tp->p_ctx.sp = (struct intctx *)scp;                                      \
-}
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     0
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This is a safe value, you may trim it down after reading the
- *          right size in the map file.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK         48
-#endif
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   (sizeof(struct intctx) - 1) +            \
-                                   (sizeof(struct extctx) - 1) +            \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE() {                                               \
-}
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() {                                               \
-  dbg_check_lock();                                                         \
-  if (chSchIsPreemptionRequired())                                          \
-    chSchDoReschedule();                                                    \
-  dbg_check_unlock();                                                       \
-}
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void vector##id(void) interrupt id
-
-/**
- * @brief   Port-related initialization code.
- * @note    None in this port.
- */
-#define port_init()
-
-/**
- * @brief   Kernel-lock action.
- * @note    Implemented as global interrupts disable.
- */
-#define port_lock() _sim_()
-
-/**
- * @brief   Kernel-unlock action.
- * @note    Implemented as global interrupts enable.
- */
-#define port_unlock() _rim_()
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @note    This function is empty in this port.
- */
-#define port_lock_from_isr()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @note    This function is empty in this port.
- */
-#define port_unlock_from_isr()
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Implemented as global interrupts disable.
- * @note    Of course non-maskable interrupt sources are not included.
- */
-#define port_disable() _sim_()
-
-/**
- * @brief   Disables the interrupt sources that are not supposed to preempt
- *          the kernel.
- * @note    Same as @p port_disable() in this port, there is no difference
- *          between the two states.
- */
-#define port_suspend() _sim_()
-
-/**
- * @brief   Enables all the interrupt sources.
- * @note    Implemented as global interrupt enable.
- */
-#define port_enable() _rim_()
-
-/**
- * @brief   Enters an architecture-dependent halt mode.
- * @note    Implemented with the specific "wfi" instruction.
- */
-#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() _wfi_()
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    Implemented as a call to a low level assembler routine.
- *
- * @param ntp   the thread to be switched in
- * @param otp   the thread to be switched out
- */
-#define port_switch(ntp, otp) _port_switch(otp)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _port_switch(Thread *otp);
-  void _port_thread_start(void);
-  void port_halt(void);
-#ifdef __cplusplus
-}
-#endif
-
-/*===========================================================================*/
-/* Scheduler captured code.                                                  */
-/*===========================================================================*/
-
-#define PORT_OPTIMIZED_RLIST_VAR
-#define PORT_OPTIMIZED_RLIST_EXT
-#define PORT_OPTIMIZED_READYLIST_STRUCT
-
-typedef struct {
-  ThreadsQueue          r_queue;
-  tprio_t               r_prio;
-  Thread                *r_current;
-#if CH_USE_REGISTRY
-  Thread                *r_newer;
-  Thread                *r_older;
-#endif
-  /* End of the fields shared with the Thread structure.*/
-#if CH_TIME_QUANTUM > 0
-  cnt_t                 r_preempt;
-#endif
-} ReadyList;
-
-page0 extern ReadyList rlist;
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/RC/STM8/chtypes.h b/os/ports/RC/STM8/chtypes.h
deleted file mode 100644
index ffc972f14..000000000
--- a/os/ports/RC/STM8/chtypes.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RC/STM8/chtypes.h
- * @brief   STM8 (Raisonance) port system types.
- *
- * @addtogroup STM8_RAISONANCE_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-
-typedef unsigned char   uint8t;         /**< C99-style boolean.             */
-typedef unsigned char   uint8_t;        /**< C99-style 8 bits unsigned.     */
-typedef signed char     int8_t;         /**< C99-style 8 bits signed.       */
-typedef unsigned int    uint16_t;       /**< C99-style 16 bits unsigned.    */
-typedef signed int      int16_t;        /**< C99-style 16 bits signed.      */
-typedef unsigned long   uint32_t;       /**< C99-style 32 bits unsigned.    */
-typedef signed long     int32_t;        /**< C99-style 32 bits signed.      */
-typedef uint8_t         uint_fast8_t;   /**< C99-style 8 bits unsigned.     */
-typedef uint16_t        uint_fast16_t;  /**< C99-style 16 bits unsigned.    */
-typedef uint32_t        uint_fast32_t;  /**< C99-style 32 bits unsigned.    */
-
-#if !defined(false) || defined(__DOXYGEN__)
-#define false           0
-#endif
-
-#if !defined(true) || defined(__DOXYGEN__)
-#define true            (!false)
-#endif
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint8_t         tprio_t;        /**< Thread priority.               */
-typedef int16_t         msg_t;          /**< Inter-thread message.          */
-typedef int8_t          eventid_t;      /**< Event Id.                      */
-typedef uint8_t         eventmask_t;    /**< Event mask.                    */
-typedef uint8_t         flagsmask_t;    /**< Event flags.                   */
-typedef uint16_t        systime_t;      /**< System time.                   */
-typedef int8_t          cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    Uses the "const" keyword in this port.
- */
-#define ROMCONST code
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_STRUCT
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/RC/STM8/port.dox b/os/ports/RC/STM8/port.dox
deleted file mode 100644
index 8dc4ba259..000000000
--- a/os/ports/RC/STM8/port.dox
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup STM8_RAISONANCE STM8
- * @details STM8 port for the Raisonance C compiler.
- *
- * @section STM8_RAISONANCE_INTRO Introduction
- * This port supports all STM8 8 bits MCUs.
- *
- * @section STM8_RAISONANCE_STATES Mapping of the System States in the STM8 port
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8
- * port:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). Interrupts are enabled.
- * - <b>Suspended</b>. Interrupts are disabled.
- * - <b>Disabled</b>. Interrupts are disabled. This state is equivalent to the
- *   Suspended state because there are no fast interrupts in this architecture.
- * - <b>Sleep</b>. Implemented with "wait" instruction insertion in the idle
- *   loop.
- * - <b>S-Locked</b>. Interrupts are disabled.
- * - <b>I-Locked</b>. This state is equivalent to the SRI state, the
- *   @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
- *   order to formally change state because this may change).
- * - <b>Serving Regular Interrupt</b>. Normal interrupt service code.
- * - <b>Serving Fast Interrupt</b>. Not present in this architecture.
- * - <b>Serving Non-Maskable Interrupt</b>. The STM8 ha non
- *   maskable interrupt sources that can be associated to this state.
- * - <b>Halted</b>. Implemented as an infinite loop with interrupts disabled.
- * .
- * @section STM8_RAISONANCE_NOTES The STM8 port notes
- * - The STM8 does not have a dedicated interrupt stack, make sure to reserve
- *     enough stack space for interrupts in each thread stack. This can be done
- *     by modifying the @p INT_REQUIRED_STACK macro into
- *     <b>./os/ports/RC/STM8/chcore.h</b>.
- * - The kernel currently supports only the small memory model so the
- *   kernel files should be loaded in the first 64K. Note that this is not
- *   a problem because upper addresses can be used by the user code, the
- *   kernel can context switch code running there.
- * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported
- *   because the missing support of the @p inline "C" keyword in the
- *   compiler.
- * .
- * @ingroup raisonance
- */
-
-/**
- * @defgroup STM8_RAISONANCE_CONF Configuration Options
- * @details STM8 Configuration Options. The STM8 port allows some
- * architecture-specific configurations settings that can be overridden
- * by redefining them in @p chconf.h. Usually there is no need to change
- * the default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space
- *   used by the interrupt handlers.<br>
- *   The default for this value is @p 48, this space is allocated for each
- *   thread so be careful in order to not waste precious RAM space.
- * .
- * @ingroup STM8_RAISONANCE
- */
-
-/**
- * @defgroup STM8_RAISONANCE_CORE Core Port Implementation
- * @details STM8 specific port code, structures and macros.
- *
- * @ingroup STM8_RAISONANCE
- */
-
- /**
- * @defgroup STM8_RAISONANCE_STARTUP Startup Support
- * @details ChibiOS/RT doed not provide startup files for the STM8, there
- * are no special startup requirement so the normal toolchain-provided
- * startup files can be used.
- *
- * @ingroup STM8_RAISONANCE
- */
diff --git a/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h b/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h
deleted file mode 100644
index e60e06771..000000000
--- a/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/LPC11xx/cmparams.h
- * @brief   ARM Cortex-M0 parameters for the LPC11xx.
- *
- * @defgroup RVCT_ARMCMx_LPC11xx LPC11xx Specific Parameters
- * @ingroup RVCT_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M0 specific parameters for the
- *          LPC11xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M0
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    2
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s b/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s
deleted file mode 100644
index 0c08b902c..000000000
--- a/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-                PRESERVE8
-
-                AREA    RESET, DATA, READONLY
-
-                IMPORT  __initial_msp
-                IMPORT  Reset_Handler
-                EXPORT  __Vectors
-
-__Vectors
-                DCD     __initial_msp
-                DCD     Reset_Handler
-                DCD     NMIVector
-                DCD     HardFaultVector
-                DCD     MemManageVector
-                DCD     BusFaultVector
-                DCD     UsageFaultVector
-                DCD     Vector1C
-                DCD     Vector20
-                DCD     Vector24
-                DCD     Vector28
-                DCD     SVCallVector
-                DCD     DebugMonitorVector
-                DCD     Vector34
-                DCD     PendSVVector
-                DCD     SysTickVector
-                DCD     Vector40
-                DCD     Vector44
-                DCD     Vector48
-                DCD     Vector4C
-                DCD     Vector50
-                DCD     Vector54
-                DCD     Vector58
-                DCD     Vector5C
-                DCD     Vector60
-                DCD     Vector64
-                DCD     Vector68
-                DCD     Vector6C
-                DCD     Vector70
-                DCD     Vector74
-                DCD     Vector78
-                DCD     Vector7C
-                DCD     Vector80
-                DCD     Vector84
-                DCD     Vector88
-                DCD     Vector8C
-                DCD     Vector90
-                DCD     Vector94
-                DCD     Vector98
-                DCD     Vector9C
-                DCD     VectorA0
-                DCD     VectorA4
-                DCD     VectorA8
-                DCD     VectorAC
-                DCD     VectorB0
-                DCD     VectorB4
-                DCD     VectorB8
-                DCD     VectorBC
-
-                AREA    |.text|, CODE, READONLY
-                THUMB
-
-/*
- * Default interrupt handlers.
- */
-                EXPORT  _unhandled_exception
-_unhandled_exception PROC 
-                EXPORT  NMIVector               [WEAK]
-                EXPORT  HardFaultVector         [WEAK]
-                EXPORT  MemManageVector         [WEAK]
-                EXPORT  BusFaultVector          [WEAK]
-                EXPORT  UsageFaultVector        [WEAK]
-                EXPORT  Vector1C                [WEAK]
-                EXPORT  Vector20                [WEAK]
-                EXPORT  Vector24                [WEAK]
-                EXPORT  Vector28                [WEAK]
-                EXPORT  SVCallVector            [WEAK]
-                EXPORT  DebugMonitorVector      [WEAK]
-                EXPORT  Vector34                [WEAK]
-                EXPORT  PendSVVector            [WEAK]
-                EXPORT  SysTickVector           [WEAK]
-                EXPORT  Vector40                [WEAK]
-                EXPORT  Vector44                [WEAK]
-                EXPORT  Vector48                [WEAK]
-                EXPORT  Vector4C                [WEAK]
-                EXPORT  Vector50                [WEAK]
-                EXPORT  Vector54                [WEAK]
-                EXPORT  Vector58                [WEAK]
-                EXPORT  Vector5C                [WEAK]
-                EXPORT  Vector60                [WEAK]
-                EXPORT  Vector64                [WEAK]
-                EXPORT  Vector68                [WEAK]
-                EXPORT  Vector6C                [WEAK]
-                EXPORT  Vector70                [WEAK]
-                EXPORT  Vector74                [WEAK]
-                EXPORT  Vector78                [WEAK]
-                EXPORT  Vector7C                [WEAK]
-                EXPORT  Vector80                [WEAK]
-                EXPORT  Vector84                [WEAK]
-                EXPORT  Vector88                [WEAK]
-                EXPORT  Vector8C                [WEAK]
-                EXPORT  Vector90                [WEAK]
-                EXPORT  Vector94                [WEAK]
-                EXPORT  Vector98                [WEAK]
-                EXPORT  Vector9C                [WEAK]
-                EXPORT  VectorA0                [WEAK]
-                EXPORT  VectorA4                [WEAK]
-                EXPORT  VectorA8                [WEAK]
-                EXPORT  VectorAC                [WEAK]
-                EXPORT  VectorB0                [WEAK]
-                EXPORT  VectorB4                [WEAK]
-                EXPORT  VectorB8                [WEAK]
-                EXPORT  VectorBC                [WEAK]
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-                b       _unhandled_exception
-                ENDP
-
-                END
diff --git a/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h b/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h
deleted file mode 100644
index 76cfe70e1..000000000
--- a/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/LPC13xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the LPC13xx.
- *
- * @defgroup RVCT_ARMCMx_LPC13xx LPC13xx Specific Parameters
- * @ingroup RVCT_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          LPC13xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    3
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s b/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s
deleted file mode 100644
index dd027d879..000000000
--- a/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-                PRESERVE8
-
-                AREA    RESET, DATA, READONLY
-
-                IMPORT  __initial_msp
-                IMPORT  Reset_Handler
-                EXPORT  __Vectors
-
-__Vectors
-                DCD     __initial_msp
-                DCD     Reset_Handler
-                DCD     NMIVector
-                DCD     HardFaultVector
-                DCD     MemManageVector
-                DCD     BusFaultVector
-                DCD     UsageFaultVector
-                DCD     Vector1C
-                DCD     Vector20
-                DCD     Vector24
-                DCD     Vector28
-                DCD     SVCallVector
-                DCD     DebugMonitorVector
-                DCD     Vector34
-                DCD     PendSVVector
-                DCD     SysTickVector
-                DCD     Vector40
-                DCD     Vector44
-                DCD     Vector48
-                DCD     Vector4C
-                DCD     Vector50
-                DCD     Vector54
-                DCD     Vector58
-                DCD     Vector5C
-                DCD     Vector60
-                DCD     Vector64
-                DCD     Vector68
-                DCD     Vector6C
-                DCD     Vector70
-                DCD     Vector74
-                DCD     Vector78
-                DCD     Vector7C
-                DCD     Vector80
-                DCD     Vector84
-                DCD     Vector88
-                DCD     Vector8C
-                DCD     Vector90
-                DCD     Vector94
-                DCD     Vector98
-                DCD     Vector9C
-                DCD     VectorA0
-                DCD     VectorA4
-                DCD     VectorA8
-                DCD     VectorAC
-                DCD     VectorB0
-                DCD     VectorB4
-                DCD     VectorB8
-                DCD     VectorBC
-                DCD     VectorC0
-                DCD     VectorC4
-                DCD     VectorC8
-                DCD     VectorCC
-                DCD     VectorD0
-                DCD     VectorD4
-                DCD     VectorD8
-                DCD     VectorDC
-                DCD     VectorE0
-                DCD     VectorE4
-                DCD     VectorE8
-                DCD     VectorEC
-                DCD     VectorF0
-                DCD     VectorF4
-                DCD     VectorF8
-                DCD     VectorFC
-                DCD     Vector100
-                DCD     Vector104
-                DCD     Vector108
-                DCD     Vector10C
-                DCD     Vector110
-                DCD     Vector114
-                DCD     Vector118
-                DCD     Vector11C
-                DCD     Vector120
-                DCD     Vector124
-
-                AREA    |.text|, CODE, READONLY
-                THUMB
-
-/*
- * Default interrupt handlers.
- */
-                EXPORT  _unhandled_exception
-_unhandled_exception PROC 
-                EXPORT  NMIVector               [WEAK]
-                EXPORT  HardFaultVector         [WEAK]
-                EXPORT  MemManageVector         [WEAK]
-                EXPORT  BusFaultVector          [WEAK]
-                EXPORT  UsageFaultVector        [WEAK]
-                EXPORT  Vector1C                [WEAK]
-                EXPORT  Vector20                [WEAK]
-                EXPORT  Vector24                [WEAK]
-                EXPORT  Vector28                [WEAK]
-                EXPORT  SVCallVector            [WEAK]
-                EXPORT  DebugMonitorVector      [WEAK]
-                EXPORT  Vector34                [WEAK]
-                EXPORT  PendSVVector            [WEAK]
-                EXPORT  SysTickVector           [WEAK]
-                EXPORT  Vector40                [WEAK]
-                EXPORT  Vector44                [WEAK]
-                EXPORT  Vector48                [WEAK]
-                EXPORT  Vector4C                [WEAK]
-                EXPORT  Vector50                [WEAK]
-                EXPORT  Vector54                [WEAK]
-                EXPORT  Vector58                [WEAK]
-                EXPORT  Vector5C                [WEAK]
-                EXPORT  Vector60                [WEAK]
-                EXPORT  Vector64                [WEAK]
-                EXPORT  Vector68                [WEAK]
-                EXPORT  Vector6C                [WEAK]
-                EXPORT  Vector70                [WEAK]
-                EXPORT  Vector74                [WEAK]
-                EXPORT  Vector78                [WEAK]
-                EXPORT  Vector7C                [WEAK]
-                EXPORT  Vector80                [WEAK]
-                EXPORT  Vector84                [WEAK]
-                EXPORT  Vector88                [WEAK]
-                EXPORT  Vector8C                [WEAK]
-                EXPORT  Vector90                [WEAK]
-                EXPORT  Vector94                [WEAK]
-                EXPORT  Vector98                [WEAK]
-                EXPORT  Vector9C                [WEAK]
-                EXPORT  VectorA0                [WEAK]
-                EXPORT  VectorA4                [WEAK]
-                EXPORT  VectorA8                [WEAK]
-                EXPORT  VectorAC                [WEAK]
-                EXPORT  VectorB0                [WEAK]
-                EXPORT  VectorB4                [WEAK]
-                EXPORT  VectorB8                [WEAK]
-                EXPORT  VectorBC                [WEAK]
-                EXPORT  VectorC0                [WEAK]
-                EXPORT  VectorC4                [WEAK]
-                EXPORT  VectorC8                [WEAK]
-                EXPORT  VectorCC                [WEAK]
-                EXPORT  VectorD0                [WEAK]
-                EXPORT  VectorD4                [WEAK]
-                EXPORT  VectorD8                [WEAK]
-                EXPORT  VectorDC                [WEAK]
-                EXPORT  VectorE0                [WEAK]
-                EXPORT  VectorE4                [WEAK]
-                EXPORT  VectorE8                [WEAK]
-                EXPORT  VectorEC                [WEAK]
-                EXPORT  VectorF0                [WEAK]
-                EXPORT  VectorF4                [WEAK]
-                EXPORT  VectorF8                [WEAK]
-                EXPORT  VectorFC                [WEAK]
-                EXPORT  Vector100               [WEAK]
-                EXPORT  Vector104               [WEAK]
-                EXPORT  Vector108               [WEAK]
-                EXPORT  Vector10C               [WEAK]
-                EXPORT  Vector110               [WEAK]
-                EXPORT  Vector114               [WEAK]
-                EXPORT  Vector118               [WEAK]
-                EXPORT  Vector11C               [WEAK]
-                EXPORT  Vector120               [WEAK]
-                EXPORT  Vector124               [WEAK]
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-VectorC0
-VectorC4
-VectorC8
-VectorCC
-VectorD0
-VectorD4
-VectorD8
-VectorDC
-VectorE0
-VectorE4
-VectorE8
-VectorEC
-VectorF0
-VectorF4
-VectorF8
-VectorFC
-Vector100
-Vector104
-Vector108
-Vector10C
-Vector110
-Vector114
-Vector118
-Vector11C
-Vector120
-Vector124
-                b       _unhandled_exception
-                ENDP
-
-                END
diff --git a/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h b/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h
deleted file mode 100644
index b1057616f..000000000
--- a/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/STM32F1xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the STM32F1xx.
- *
- * @defgroup RVCT_ARMCMx_STM32F1xx STM32F1xx Specific Parameters
- * @ingroup RVCT_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          STM32F1xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          FALSE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s b/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s
deleted file mode 100644
index f3a303543..000000000
--- a/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) &&                  \
-    !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) &&                  \
-    !defined(STM32F10X_HD) && !defined(STM32F10X_XL) &&                     \
-    !defined(STM32F10X_CL)
-#define _FROM_ASM_
-#include "board.h"
-#endif
-
-                PRESERVE8
-
-                AREA    RESET, DATA, READONLY
-
-                IMPORT  __initial_msp
-                IMPORT  Reset_Handler
-                EXPORT  __Vectors
-
-__Vectors
-                DCD     __initial_msp
-                DCD     Reset_Handler
-                DCD     NMIVector
-                DCD     HardFaultVector
-                DCD     MemManageVector
-                DCD     BusFaultVector
-                DCD     UsageFaultVector
-                DCD     Vector1C
-                DCD     Vector20
-                DCD     Vector24
-                DCD     Vector28
-                DCD     SVCallVector
-                DCD     DebugMonitorVector
-                DCD     Vector34
-                DCD     PendSVVector
-                DCD     SysTickVector
-                DCD     Vector40
-                DCD     Vector44
-                DCD     Vector48
-                DCD     Vector4C
-                DCD     Vector50
-                DCD     Vector54
-                DCD     Vector58
-                DCD     Vector5C
-                DCD     Vector60
-                DCD     Vector64
-                DCD     Vector68
-                DCD     Vector6C
-                DCD     Vector70
-                DCD     Vector74
-                DCD     Vector78
-                DCD     Vector7C
-                DCD     Vector80
-                DCD     Vector84
-                DCD     Vector88
-                DCD     Vector8C
-                DCD     Vector90
-                DCD     Vector94
-                DCD     Vector98
-                DCD     Vector9C
-                DCD     VectorA0
-                DCD     VectorA4
-                DCD     VectorA8
-                DCD     VectorAC
-                DCD     VectorB0
-                DCD     VectorB4
-                DCD     VectorB8
-                DCD     VectorBC
-                DCD     VectorC0
-                DCD     VectorC4
-                DCD     VectorC8
-                DCD     VectorCC
-                DCD     VectorD0
-                DCD     VectorD4
-                DCD     VectorD8
-                DCD     VectorDC
-                DCD     VectorE0
-                DCD     VectorE4
-                DCD     VectorE8
-#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) ||                    \
-    defined(STM32F10X_XL)    || defined(STM32F10X_CL)
-                DCD     VectorEC
-                DCD     VectorF0
-                DCD     VectorF4
-#endif
-#if defined(STM32F10X_HD)    || defined(STM32F10X_XL) || defined(STM32F10X_CL)
-                DCD     VectorF8
-                DCD     VectorFC
-                DCD     Vector100
-                DCD     Vector104
-                DCD     Vector108
-                DCD     Vector10C
-                DCD     Vector110
-                DCD     Vector114
-                DCD     Vector118
-                DCD     Vector11C
-                DCD     Vector120
-                DCD     Vector124
-                DCD     Vector128
-                DCD     Vector12C
-#endif
-#if defined(STM32F10X_CL)
-                DCD     Vector130
-                DCD     Vector134
-                DCD     Vector138
-                DCD     Vector13C
-                DCD     Vector140
-                DCD     Vector144
-                DCD     Vector148
-                DCD     Vector14C
-#endif
-
-                AREA    |.text|, CODE, READONLY
-                THUMB
-
-/*
- * Default interrupt handlers.
- */
-                EXPORT  _unhandled_exception
-_unhandled_exception PROC 
-                EXPORT  NMIVector               [WEAK]
-                EXPORT  HardFaultVector         [WEAK]
-                EXPORT  MemManageVector         [WEAK]
-                EXPORT  BusFaultVector          [WEAK]
-                EXPORT  UsageFaultVector        [WEAK]
-                EXPORT  Vector1C                [WEAK]
-                EXPORT  Vector20                [WEAK]
-                EXPORT  Vector24                [WEAK]
-                EXPORT  Vector28                [WEAK]
-                EXPORT  SVCallVector            [WEAK]
-                EXPORT  DebugMonitorVector      [WEAK]
-                EXPORT  Vector34                [WEAK]
-                EXPORT  PendSVVector            [WEAK]
-                EXPORT  SysTickVector           [WEAK]
-                EXPORT  Vector40                [WEAK]
-                EXPORT  Vector44                [WEAK]
-                EXPORT  Vector48                [WEAK]
-                EXPORT  Vector4C                [WEAK]
-                EXPORT  Vector50                [WEAK]
-                EXPORT  Vector54                [WEAK]
-                EXPORT  Vector58                [WEAK]
-                EXPORT  Vector5C                [WEAK]
-                EXPORT  Vector60                [WEAK]
-                EXPORT  Vector64                [WEAK]
-                EXPORT  Vector68                [WEAK]
-                EXPORT  Vector6C                [WEAK]
-                EXPORT  Vector70                [WEAK]
-                EXPORT  Vector74                [WEAK]
-                EXPORT  Vector78                [WEAK]
-                EXPORT  Vector7C                [WEAK]
-                EXPORT  Vector80                [WEAK]
-                EXPORT  Vector84                [WEAK]
-                EXPORT  Vector88                [WEAK]
-                EXPORT  Vector8C                [WEAK]
-                EXPORT  Vector90                [WEAK]
-                EXPORT  Vector94                [WEAK]
-                EXPORT  Vector98                [WEAK]
-                EXPORT  Vector9C                [WEAK]
-                EXPORT  VectorA0                [WEAK]
-                EXPORT  VectorA4                [WEAK]
-                EXPORT  VectorA8                [WEAK]
-                EXPORT  VectorAC                [WEAK]
-                EXPORT  VectorB0                [WEAK]
-                EXPORT  VectorB4                [WEAK]
-                EXPORT  VectorB8                [WEAK]
-                EXPORT  VectorBC                [WEAK]
-                EXPORT  VectorC0                [WEAK]
-                EXPORT  VectorC4                [WEAK]
-                EXPORT  VectorC8                [WEAK]
-                EXPORT  VectorCC                [WEAK]
-                EXPORT  VectorD0                [WEAK]
-                EXPORT  VectorD4                [WEAK]
-                EXPORT  VectorD8                [WEAK]
-                EXPORT  VectorDC                [WEAK]
-                EXPORT  VectorE0                [WEAK]
-                EXPORT  VectorE4                [WEAK]
-                EXPORT  VectorE8                [WEAK]
-                EXPORT  VectorEC                [WEAK]
-                EXPORT  VectorF0                [WEAK]
-                EXPORT  VectorF4                [WEAK]
-                EXPORT  VectorF8                [WEAK]
-                EXPORT  VectorFC                [WEAK]
-                EXPORT  Vector100               [WEAK]
-                EXPORT  Vector104               [WEAK]
-                EXPORT  Vector108               [WEAK]
-                EXPORT  Vector10C               [WEAK]
-                EXPORT  Vector110               [WEAK]
-                EXPORT  Vector114               [WEAK]
-                EXPORT  Vector118               [WEAK]
-                EXPORT  Vector11C               [WEAK]
-                EXPORT  Vector120               [WEAK]
-                EXPORT  Vector124               [WEAK]
-                EXPORT  Vector128               [WEAK]
-                EXPORT  Vector12C               [WEAK]
-                EXPORT  Vector130               [WEAK]
-                EXPORT  Vector134               [WEAK]
-                EXPORT  Vector138               [WEAK]
-                EXPORT  Vector13C               [WEAK]
-                EXPORT  Vector140               [WEAK]
-                EXPORT  Vector144               [WEAK]
-                EXPORT  Vector148               [WEAK]
-                EXPORT  Vector14C               [WEAK]
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-VectorC0
-VectorC4
-VectorC8
-VectorCC
-VectorD0
-VectorD4
-VectorD8
-VectorDC
-VectorE0
-VectorE4
-VectorE8
-VectorEC
-VectorF0
-VectorF4
-VectorF8
-VectorFC
-Vector100
-Vector104
-Vector108
-Vector10C
-Vector110
-Vector114
-Vector118
-Vector11C
-Vector120
-Vector124
-Vector128
-Vector12C
-Vector130
-Vector134
-Vector138
-Vector13C
-Vector140
-Vector144
-Vector148
-Vector14C
-                b       _unhandled_exception
-                ENDP
-
-                END
diff --git a/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h b/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h
deleted file mode 100644
index 8c040789f..000000000
--- a/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/STM32F4xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the STM32F4xx.
- *
- * @defgroup RVCT_ARMCMx_STM32F4xx STM32F4xx Specific Parameters
- * @ingroup RVCT_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- *          STM32F4xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M4
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          TRUE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s b/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s
deleted file mode 100644
index 6a912c5af..000000000
--- a/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#if !defined(STM32F4XX)
-#define _FROM_ASM_
-#include "board.h"
-#endif
-
-                PRESERVE8
-
-                AREA    RESET, DATA, READONLY
-
-                IMPORT  __initial_msp
-                IMPORT  Reset_Handler
-                EXPORT  __Vectors
-
-__Vectors
-                DCD     __initial_msp
-                DCD     Reset_Handler
-                DCD     NMIVector
-                DCD     HardFaultVector
-                DCD     MemManageVector
-                DCD     BusFaultVector
-                DCD     UsageFaultVector
-                DCD     Vector1C
-                DCD     Vector20
-                DCD     Vector24
-                DCD     Vector28
-                DCD     SVCallVector
-                DCD     DebugMonitorVector
-                DCD     Vector34
-                DCD     PendSVVector
-                DCD     SysTickVector
-                DCD     Vector40
-                DCD     Vector44
-                DCD     Vector48
-                DCD     Vector4C
-                DCD     Vector50
-                DCD     Vector54
-                DCD     Vector58
-                DCD     Vector5C
-                DCD     Vector60
-                DCD     Vector64
-                DCD     Vector68
-                DCD     Vector6C
-                DCD     Vector70
-                DCD     Vector74
-                DCD     Vector78
-                DCD     Vector7C
-                DCD     Vector80
-                DCD     Vector84
-                DCD     Vector88
-                DCD     Vector8C
-                DCD     Vector90
-                DCD     Vector94
-                DCD     Vector98
-                DCD     Vector9C
-                DCD     VectorA0
-                DCD     VectorA4
-                DCD     VectorA8
-                DCD     VectorAC
-                DCD     VectorB0
-                DCD     VectorB4
-                DCD     VectorB8
-                DCD     VectorBC
-                DCD     VectorC0
-                DCD     VectorC4
-                DCD     VectorC8
-                DCD     VectorCC
-                DCD     VectorD0
-                DCD     VectorD4
-                DCD     VectorD8
-                DCD     VectorDC
-                DCD     VectorE0
-                DCD     VectorE4
-                DCD     VectorE8
-                DCD     VectorEC
-                DCD     VectorF0
-                DCD     VectorF4
-                DCD     VectorF8
-                DCD     VectorFC
-                DCD     Vector100
-                DCD     Vector104
-                DCD     Vector108
-                DCD     Vector10C
-                DCD     Vector110
-                DCD     Vector114
-                DCD     Vector118
-                DCD     Vector11C
-                DCD     Vector120
-                DCD     Vector124
-                DCD     Vector128
-                DCD     Vector12C
-                DCD     Vector130
-                DCD     Vector134
-                DCD     Vector138
-                DCD     Vector13C
-                DCD     Vector140
-                DCD     Vector144
-                DCD     Vector148
-                DCD     Vector14C
-                DCD     Vector150
-                DCD     Vector154
-                DCD     Vector158
-                DCD     Vector15C
-                DCD     Vector160
-                DCD     Vector164
-                DCD     Vector168
-                DCD     Vector16C
-                DCD     Vector170
-                DCD     Vector174
-                DCD     Vector178
-                DCD     Vector17C
-                DCD     Vector180
-                DCD     Vector184
-
-                AREA    |.text|, CODE, READONLY
-                THUMB
-
-/*
- * Default interrupt handlers.
- */
-                EXPORT  _unhandled_exception
-_unhandled_exception PROC 
-                EXPORT  NMIVector               [WEAK]
-                EXPORT  HardFaultVector         [WEAK]
-                EXPORT  MemManageVector         [WEAK]
-                EXPORT  BusFaultVector          [WEAK]
-                EXPORT  UsageFaultVector        [WEAK]
-                EXPORT  Vector1C                [WEAK]
-                EXPORT  Vector20                [WEAK]
-                EXPORT  Vector24                [WEAK]
-                EXPORT  Vector28                [WEAK]
-                EXPORT  SVCallVector            [WEAK]
-                EXPORT  DebugMonitorVector      [WEAK]
-                EXPORT  Vector34                [WEAK]
-                EXPORT  PendSVVector            [WEAK]
-                EXPORT  SysTickVector           [WEAK]
-                EXPORT  Vector40                [WEAK]
-                EXPORT  Vector44                [WEAK]
-                EXPORT  Vector48                [WEAK]
-                EXPORT  Vector4C                [WEAK]
-                EXPORT  Vector50                [WEAK]
-                EXPORT  Vector54                [WEAK]
-                EXPORT  Vector58                [WEAK]
-                EXPORT  Vector5C                [WEAK]
-                EXPORT  Vector60                [WEAK]
-                EXPORT  Vector64                [WEAK]
-                EXPORT  Vector68                [WEAK]
-                EXPORT  Vector6C                [WEAK]
-                EXPORT  Vector70                [WEAK]
-                EXPORT  Vector74                [WEAK]
-                EXPORT  Vector78                [WEAK]
-                EXPORT  Vector7C                [WEAK]
-                EXPORT  Vector80                [WEAK]
-                EXPORT  Vector84                [WEAK]
-                EXPORT  Vector88                [WEAK]
-                EXPORT  Vector8C                [WEAK]
-                EXPORT  Vector90                [WEAK]
-                EXPORT  Vector94                [WEAK]
-                EXPORT  Vector98                [WEAK]
-                EXPORT  Vector9C                [WEAK]
-                EXPORT  VectorA0                [WEAK]
-                EXPORT  VectorA4                [WEAK]
-                EXPORT  VectorA8                [WEAK]
-                EXPORT  VectorAC                [WEAK]
-                EXPORT  VectorB0                [WEAK]
-                EXPORT  VectorB4                [WEAK]
-                EXPORT  VectorB8                [WEAK]
-                EXPORT  VectorBC                [WEAK]
-                EXPORT  VectorC0                [WEAK]
-                EXPORT  VectorC4                [WEAK]
-                EXPORT  VectorC8                [WEAK]
-                EXPORT  VectorCC                [WEAK]
-                EXPORT  VectorD0                [WEAK]
-                EXPORT  VectorD4                [WEAK]
-                EXPORT  VectorD8                [WEAK]
-                EXPORT  VectorDC                [WEAK]
-                EXPORT  VectorE0                [WEAK]
-                EXPORT  VectorE4                [WEAK]
-                EXPORT  VectorE8                [WEAK]
-                EXPORT  VectorEC                [WEAK]
-                EXPORT  VectorF0                [WEAK]
-                EXPORT  VectorF4                [WEAK]
-                EXPORT  VectorF8                [WEAK]
-                EXPORT  VectorFC                [WEAK]
-                EXPORT  Vector100               [WEAK]
-                EXPORT  Vector104               [WEAK]
-                EXPORT  Vector108               [WEAK]
-                EXPORT  Vector10C               [WEAK]
-                EXPORT  Vector110               [WEAK]
-                EXPORT  Vector114               [WEAK]
-                EXPORT  Vector118               [WEAK]
-                EXPORT  Vector11C               [WEAK]
-                EXPORT  Vector120               [WEAK]
-                EXPORT  Vector124               [WEAK]
-                EXPORT  Vector128               [WEAK]
-                EXPORT  Vector12C               [WEAK]
-                EXPORT  Vector130               [WEAK]
-                EXPORT  Vector134               [WEAK]
-                EXPORT  Vector138               [WEAK]
-                EXPORT  Vector13C               [WEAK]
-                EXPORT  Vector140               [WEAK]
-                EXPORT  Vector144               [WEAK]
-                EXPORT  Vector148               [WEAK]
-                EXPORT  Vector14C               [WEAK]
-                EXPORT  Vector150               [WEAK]
-                EXPORT  Vector154               [WEAK]
-                EXPORT  Vector158               [WEAK]
-                EXPORT  Vector15C               [WEAK]
-                EXPORT  Vector160               [WEAK]
-                EXPORT  Vector164               [WEAK]
-                EXPORT  Vector168               [WEAK]
-                EXPORT  Vector16C               [WEAK]
-                EXPORT  Vector170               [WEAK]
-                EXPORT  Vector174               [WEAK]
-                EXPORT  Vector178               [WEAK]
-                EXPORT  Vector17C               [WEAK]
-                EXPORT  Vector180               [WEAK]
-                EXPORT  Vector184               [WEAK]
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-VectorC0
-VectorC4
-VectorC8
-VectorCC
-VectorD0
-VectorD4
-VectorD8
-VectorDC
-VectorE0
-VectorE4
-VectorE8
-VectorEC
-VectorF0
-VectorF4
-VectorF8
-VectorFC
-Vector100
-Vector104
-Vector108
-Vector10C
-Vector110
-Vector114
-Vector118
-Vector11C
-Vector120
-Vector124
-Vector128
-Vector12C
-Vector130
-Vector134
-Vector138
-Vector13C
-Vector140
-Vector144
-Vector148
-Vector14C
-Vector150
-Vector154
-Vector158
-Vector15C
-Vector160
-Vector164
-Vector168
-Vector16C
-Vector170
-Vector174
-Vector178
-Vector17C
-Vector180
-Vector184
-                b       _unhandled_exception
-                ENDP
-
-                END
diff --git a/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h b/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h
deleted file mode 100644
index 61916a722..000000000
--- a/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/STM32L1xx/cmparams.h
- * @brief   ARM Cortex-M3 parameters for the STM32L1xx.
- *
- * @defgroup RVCT_ARMCMx_STM32L1xx STM32L1xx Specific Parameters
- * @ingroup RVCT_ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M3 specific parameters for the
- *          STM32L1xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M3
-
-/**
- * @brief   Systick unit presence.
- */
-#define CORTEX_HAS_ST           TRUE
-
-/**
- * @brief   Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU          TRUE
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          FALSE
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s b/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s
deleted file mode 100644
index da0f368c0..000000000
--- a/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#if !defined(STM32L1XX_MD)
-#define _FROM_ASM_
-#include "board.h"
-#endif
-
-                PRESERVE8
-
-                AREA    RESET, DATA, READONLY
-
-                IMPORT  __initial_msp
-                IMPORT  Reset_Handler
-                EXPORT  __Vectors
-
-__Vectors
-                DCD     __initial_msp
-                DCD     Reset_Handler
-                DCD     NMIVector
-                DCD     HardFaultVector
-                DCD     MemManageVector
-                DCD     BusFaultVector
-                DCD     UsageFaultVector
-                DCD     Vector1C
-                DCD     Vector20
-                DCD     Vector24
-                DCD     Vector28
-                DCD     SVCallVector
-                DCD     DebugMonitorVector
-                DCD     Vector34
-                DCD     PendSVVector
-                DCD     SysTickVector
-                DCD     Vector40
-                DCD     Vector44
-                DCD     Vector48
-                DCD     Vector4C
-                DCD     Vector50
-                DCD     Vector54
-                DCD     Vector58
-                DCD     Vector5C
-                DCD     Vector60
-                DCD     Vector64
-                DCD     Vector68
-                DCD     Vector6C
-                DCD     Vector70
-                DCD     Vector74
-                DCD     Vector78
-                DCD     Vector7C
-                DCD     Vector80
-                DCD     Vector84
-                DCD     Vector88
-                DCD     Vector8C
-                DCD     Vector90
-                DCD     Vector94
-                DCD     Vector98
-                DCD     Vector9C
-                DCD     VectorA0
-                DCD     VectorA4
-                DCD     VectorA8
-                DCD     VectorAC
-                DCD     VectorB0
-                DCD     VectorB4
-                DCD     VectorB8
-                DCD     VectorBC
-                DCD     VectorC0
-                DCD     VectorC4
-                DCD     VectorC8
-                DCD     VectorCC
-                DCD     VectorD0
-                DCD     VectorD4
-                DCD     VectorD8
-                DCD     VectorDC
-                DCD     VectorE0
-                DCD     VectorE4
-                DCD     VectorE8
-                DCD     VectorEC
-                DCD     VectorF0
-
-                AREA    |.text|, CODE, READONLY
-                THUMB
-
-/*
- * Default interrupt handlers.
- */
-                EXPORT  _unhandled_exception
-_unhandled_exception PROC 
-                EXPORT  NMIVector               [WEAK]
-                EXPORT  HardFaultVector         [WEAK]
-                EXPORT  MemManageVector         [WEAK]
-                EXPORT  BusFaultVector          [WEAK]
-                EXPORT  UsageFaultVector        [WEAK]
-                EXPORT  Vector1C                [WEAK]
-                EXPORT  Vector20                [WEAK]
-                EXPORT  Vector24                [WEAK]
-                EXPORT  Vector28                [WEAK]
-                EXPORT  SVCallVector            [WEAK]
-                EXPORT  DebugMonitorVector      [WEAK]
-                EXPORT  Vector34                [WEAK]
-                EXPORT  PendSVVector            [WEAK]
-                EXPORT  SysTickVector           [WEAK]
-                EXPORT  Vector40                [WEAK]
-                EXPORT  Vector44                [WEAK]
-                EXPORT  Vector48                [WEAK]
-                EXPORT  Vector4C                [WEAK]
-                EXPORT  Vector50                [WEAK]
-                EXPORT  Vector54                [WEAK]
-                EXPORT  Vector58                [WEAK]
-                EXPORT  Vector5C                [WEAK]
-                EXPORT  Vector60                [WEAK]
-                EXPORT  Vector64                [WEAK]
-                EXPORT  Vector68                [WEAK]
-                EXPORT  Vector6C                [WEAK]
-                EXPORT  Vector70                [WEAK]
-                EXPORT  Vector74                [WEAK]
-                EXPORT  Vector78                [WEAK]
-                EXPORT  Vector7C                [WEAK]
-                EXPORT  Vector80                [WEAK]
-                EXPORT  Vector84                [WEAK]
-                EXPORT  Vector88                [WEAK]
-                EXPORT  Vector8C                [WEAK]
-                EXPORT  Vector90                [WEAK]
-                EXPORT  Vector94                [WEAK]
-                EXPORT  Vector98                [WEAK]
-                EXPORT  Vector9C                [WEAK]
-                EXPORT  VectorA0                [WEAK]
-                EXPORT  VectorA4                [WEAK]
-                EXPORT  VectorA8                [WEAK]
-                EXPORT  VectorAC                [WEAK]
-                EXPORT  VectorB0                [WEAK]
-                EXPORT  VectorB4                [WEAK]
-                EXPORT  VectorB8                [WEAK]
-                EXPORT  VectorBC                [WEAK]
-                EXPORT  VectorC0                [WEAK]
-                EXPORT  VectorC4                [WEAK]
-                EXPORT  VectorC8                [WEAK]
-                EXPORT  VectorCC                [WEAK]
-                EXPORT  VectorD0                [WEAK]
-                EXPORT  VectorD4                [WEAK]
-                EXPORT  VectorD8                [WEAK]
-                EXPORT  VectorDC                [WEAK]
-                EXPORT  VectorE0                [WEAK]
-                EXPORT  VectorE4                [WEAK]
-                EXPORT  VectorE8                [WEAK]
-                EXPORT  VectorEC                [WEAK]
-                EXPORT  VectorF0                [WEAK]
-
-NMIVector
-HardFaultVector
-MemManageVector
-BusFaultVector
-UsageFaultVector
-Vector1C
-Vector20
-Vector24
-Vector28
-SVCallVector
-DebugMonitorVector
-Vector34
-PendSVVector
-SysTickVector
-Vector40
-Vector44
-Vector48
-Vector4C
-Vector50
-Vector54
-Vector58
-Vector5C
-Vector60
-Vector64
-Vector68
-Vector6C
-Vector70
-Vector74
-Vector78
-Vector7C
-Vector80
-Vector84
-Vector88
-Vector8C
-Vector90
-Vector94
-Vector98
-Vector9C
-VectorA0
-VectorA4
-VectorA8
-VectorAC
-VectorB0
-VectorB4
-VectorB8
-VectorBC
-VectorC0
-VectorC4
-VectorC8
-VectorCC
-VectorD0
-VectorD4
-VectorD8
-VectorDC
-VectorE0
-VectorE4
-VectorE8
-VectorEC
-VectorF0
-                b       _unhandled_exception
-                ENDP
-
-                END
diff --git a/os/ports/RVCT/ARMCMx/chcore.c b/os/ports/RVCT/ARMCMx/chcore.c
deleted file mode 100644
index cb5993577..000000000
--- a/os/ports/RVCT/ARMCMx/chcore.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/chcore.c
- * @brief   ARM Cortex-Mx port code.
- *
- * @addtogroup RVCT_ARMCMx_CORE
- * @{
- */
-
-#include "ch.h"
-
-/**
- * @brief   Halts the system.
- * @note    The function is declared as a weak symbol, it is possible
- *          to redefine it in your application code.
- */
-#if !defined(__DOXYGEN__)
-__attribute__((weak))
-#endif
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcore.h b/os/ports/RVCT/ARMCMx/chcore.h
deleted file mode 100644
index 5ba5a1eb5..000000000
--- a/os/ports/RVCT/ARMCMx/chcore.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/chcore.h
- * @brief   ARM Cortex-Mx port macros and structures.
- *
- * @addtogroup RVCT_ARMCMx_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-/*===========================================================================*/
-/* Port constants (common).                                                  */
-/*===========================================================================*/
-
-/* Added to make the header stand-alone when included from asm.*/
-#ifndef FALSE
-#define FALSE       0
-#endif
-#ifndef TRUE
-#define TRUE        (!FALSE)
-#endif
-
-#define CORTEX_M0                       0   /**< @brief Cortex-M0 variant.  */
-#define CORTEX_M1                       1   /**< @brief Cortex-M1 variant.  */
-#define CORTEX_M3                       3   /**< @brief Cortex-M3 variant.  */
-#define CORTEX_M4                       4   /**< @brief Cortex-M4 variant.  */
-
-/* Inclusion of the Cortex-Mx implementation specific parameters.*/
-#include "cmparams.h"
-
-/* Cortex model check, only M0 and M3 supported right now.*/
-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) ||           \
-    (CORTEX_MODEL == CORTEX_M4)
-#elif (CORTEX_MODEL == CORTEX_M1)
-#error "untested Cortex-M model"
-#else
-#error "unknown or unsupported Cortex-M model"
-#endif
-
-/**
- * @brief   Total priority levels.
- */
-#define CORTEX_PRIORITY_LEVELS          (1 << CORTEX_PRIORITY_BITS)
-
-/**
- * @brief   Minimum priority level.
- * @details This minimum priority level is calculated from the number of
- *          priority bits supported by the specific Cortex-Mx implementation.
- */
-#define CORTEX_MINIMUM_PRIORITY         (CORTEX_PRIORITY_LEVELS - 1)
-
-/**
- * @brief   Maximum priority level.
- * @details The maximum allowed priority level is always zero.
- */
-#define CORTEX_MAXIMUM_PRIORITY         0
-
-/*===========================================================================*/
-/* Port macros (common).                                                     */
-/*===========================================================================*/
-
-/**
- * @brief   Priority level verification macro.
- */
-#define CORTEX_IS_VALID_PRIORITY(n)                                         \
-  (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
-
-/**
- * @brief   Priority level verification macro.
- */
-#define CORTEX_IS_VALID_KERNEL_PRIORITY(n)                                  \
-  (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
-
-/**
- * @brief   Priority level to priority mask conversion macro.
- */
-#define CORTEX_PRIORITY_MASK(n)                                             \
-  ((n) << (8 - CORTEX_PRIORITY_BITS))
-
-/*===========================================================================*/
-/* Port configurable parameters (common).                                    */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port derived parameters (common).                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port exported info (common).                                              */
-/*===========================================================================*/
-
-/**
- * @brief   Macro defining a generic ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "RVCT"
-
-/*===========================================================================*/
-/* Port implementation part (common).                                        */
-/*===========================================================================*/
-
-/* Includes the sub-architecture-specific part.*/
-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
-#include "chcore_v6m.h"
-#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
-#include "chcore_v7m.h"
-#endif
-
-#if !defined(_FROM_ASM_)
-
-#include "nvic.h"
-
-/* The following declarations are there just for Doxygen documentation, the
-   real declarations are inside the sub-headers.*/
-#if defined(__DOXYGEN__)
-
-/**
- * @brief   Stack and memory alignment enforcement.
- * @note    In this architecture the stack alignment is enforced to 64 bits,
- *          32 bits alignment is supported by hardware but deprecated by ARM,
- *          the implementation choice is to not offer the option.
- */
-typedef uint64_t stkalign_t;
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- * @note    It is implemented to match the Cortex-Mx exception context.
- */
-struct extctx {};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching.
- */
-struct intctx {};
-
-#endif /* defined(__DOXYGEN__) */
-
-/**
- * @brief   Excludes the default @p chSchIsPreemptionRequired()implementation.
- */
-#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED
-
-#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
-/**
- * @brief   Inline-able version of this kernel function.
- */
-#define chSchIsPreemptionRequired()                                         \
-  (currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio :           \
-                      firstprio(&rlist.r_queue) >= currp->p_prio)
-#else /* CH_TIME_QUANTUM == 0 */
-#define chSchIsPreemptionRequired()                                         \
-  (firstprio(&rlist.r_queue) > currp->p_prio)
-#endif /* CH_TIME_QUANTUM == 0 */
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.c b/os/ports/RVCT/ARMCMx/chcore_v6m.c
deleted file mode 100644
index d8183cdd4..000000000
--- a/os/ports/RVCT/ARMCMx/chcore_v6m.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/chcore_v6m.c
- * @brief   ARMv6-M architecture port code.
- *
- * @addtogroup RVCT_ARMCMx_V6M_CORE
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* Port interrupt handlers.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   System Timer vector.
- * @details This interrupt is used as system tick.
- * @note    The timer must be initialized in the startup code.
- */
-CH_IRQ_HANDLER(SysTickVector) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-/**
- * @brief   NMI vector.
- * @details The NMI vector is used for exception mode re-entering after a
- *          context switch.
- */
-void NMIVector(void) {
-  register struct extctx *ctxp;
-  register uint32_t psp __asm("psp");
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp = (struct extctx *)psp;
-  ctxp++;
-  psp = (uint32_t)ctxp;
-  port_unlock_from_isr();
-}
-#endif /* !CORTEX_ALTERNATE_SWITCH */
-
-#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-/**
- * @brief   PendSV vector.
- * @details The PendSV vector is used for exception mode re-entering after a
- *          context switch.
- */
-void PendSVVector(void) {
-  register struct extctx *ctxp;
-  register uint32_t psp __asm("psp");
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp = (struct extctx *)psp;
-  ctxp++;
-  psp = (uint32_t)ctxp;
-}
-#endif /* CORTEX_ALTERNATE_SWITCH */
-
-/*===========================================================================*/
-/* Port exported functions.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   IRQ epilogue code.
- *
- * @param[in] lr        value of the @p LR register on ISR entry
- */
-void _port_irq_epilogue(regarm_t lr) {
-
-  if (lr != (regarm_t)0xFFFFFFF1) {
-    register struct extctx *ctxp;
-    register uint32_t psp __asm("psp");
-
-    port_lock_from_isr();
-    /* Adding an artificial exception return context, there is no need to
-       populate it fully.*/
-    ctxp = (struct extctx *)psp;
-    ctxp--;
-    psp = (uint32_t)ctxp;
-    ctxp->xpsr = (regarm_t)0x01000000;
-
-    /* The exit sequence is different depending on if a preemption is
-       required or not.*/
-    if (chSchIsPreemptionRequired()) {
-      /* Preemption is required we need to enforce a context switch.*/
-      ctxp->pc = (regarm_t)_port_switch_from_isr;
-    }
-    else {
-      /* Preemption not required, we just need to exit the exception
-         atomically.*/
-      ctxp->pc = (regarm_t)_port_exit_from_isr;
-    }
-
-    /* Note, returning without unlocking is intentional, this is done in
-       order to keep the rest of the context switch atomic.*/
-  }
-}
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h
deleted file mode 100644
index 2ed119dd3..000000000
--- a/os/ports/RVCT/ARMCMx/chcore_v6m.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/chcore_v6m.h
- * @brief   ARMv6-M architecture port macros and structures.
- *
- * @addtogroup RVCT_ARMCMx_V6M_CORE
- * @{
- */
-
-#ifndef _CHCORE_V6M_H_
-#define _CHCORE_V6M_H_
-
-/*===========================================================================*/
-/* Port constants.                                                           */
-/*===========================================================================*/
-
-/**
- * @brief   PendSV priority level.
- * @note    This priority is enforced to be equal to @p 0,
- *          this handler always has the highest priority that cannot preempt
- *          the kernel.
- */
-#define CORTEX_PRIORITY_PENDSV          0
-
-/*===========================================================================*/
-/* Port macros.                                                              */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- * @note    In this port it is set to 16 because the idle thread does have
- *          a stack frame when compiling without optimizations. You may
- *          reduce this value to zero when compiling with optimizations.
- */
-#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
-#define PORT_IDLE_THREAD_STACK_SIZE     16
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- * @note    In this port this value is conservatively set to 32 because the
- *          function @p chSchDoReschedule() can have a stack frame, especially
- *          with compiler optimizations disabled. The value can be reduced
- *          when compiler optimizations are enabled.
- */
-#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK         32
-#endif
-
-/**
- * @brief   Enables the use of the WFI instruction in the idle thread loop.
- */
-#if !defined(CORTEX_ENABLE_WFI_IDLE)
-#define CORTEX_ENABLE_WFI_IDLE          FALSE
-#endif
-
-/**
- * @brief   SYSTICK handler priority.
- * @note    The default SYSTICK handler priority is calculated as the priority
- *          level in the middle of the numeric priorities range.
- */
-#if !defined(CORTEX_PRIORITY_SYSTICK)
-#define CORTEX_PRIORITY_SYSTICK         (CORTEX_PRIORITY_LEVELS >> 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
-
-/**
- * @brief   Alternate preemption method.
- * @details Activating this option will make the Kernel use the PendSV
- *          handler for preemption instead of the NMI handler.
- */
-#ifndef CORTEX_ALTERNATE_SWITCH
-#define CORTEX_ALTERNATE_SWITCH         FALSE
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   Maximum usable priority for normal ISRs.
- */
-#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-#define CORTEX_MAX_KERNEL_PRIORITY      1
-#else
-#define CORTEX_MAX_KERNEL_PRIORITY      0
-#endif
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Macro defining the specific ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM_v6M
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "ARMv6-M"
-
-/**
- * @brief   Name of the architecture variant.
- */
-#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
-#define CH_CORE_VARIANT_NAME            "Cortex-M0"
-#elif (CORTEX_MODEL == CORTEX_M1)
-#define CH_CORE_VARIANT_NAME            "Cortex-M1"
-#endif
-
-/**
- * @brief   Port-specific information string.
- */
-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-#define CH_PORT_INFO                    "Preemption through NMI"
-#else
-#define CH_PORT_INFO                    "Preemption through PendSV"
-#endif
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-/**
- * @brief   Generic ARM register.
- */
-typedef void *regarm_t;
-
-/**
- * @brief   Stack and memory alignment enforcement.
- * @note    In this architecture the stack alignment is enforced to 64 bits,
- *          32 bits alignment is supported by hardware but deprecated by ARM,
- *          the implementation choice is to not offer the option.
- */
-typedef uint64_t stkalign_t;
-
- /* The documentation of the following declarations is in chconf.h in order
-    to not have duplicated structure names into the documentation.*/
-#if !defined(__DOXYGEN__)
-
-struct extctx {
-  regarm_t      r0;
-  regarm_t      r1;
-  regarm_t      r2;
-  regarm_t      r3;
-  regarm_t      r12;
-  regarm_t      lr_thd;
-  regarm_t      pc;
-  regarm_t      xpsr;
-};
-
-struct intctx {
-  regarm_t      r8;
-  regarm_t      r9;
-  regarm_t      r10;
-  regarm_t      r11;
-  regarm_t      r4;
-  regarm_t      r5;
-  regarm_t      r6;
-  regarm_t      r7;
-  regarm_t      lr;
-};
-
-#endif /* !defined(__DOXYGEN__) */
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- *          structure representing the stack pointer at context switch time.
- */
-struct context {
-  struct intctx *r13;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
-                                     wsize -                                \
-                                     sizeof(struct intctx));                \
-  tp->p_ctx.r13->r4 = (regarm_t)pf;                                         \
-  tp->p_ctx.r13->r5 = (regarm_t)arg;                                        \
-  tp->p_ctx.r13->lr = (regarm_t)_port_thread_start;                         \
-}
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__return_address()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Fast IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_FAST_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Port-related initialization code.
- */
-#define port_init() {                                                       \
-  SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \
-  nvicSetSystemHandlerPriority(HANDLER_PENDSV,                              \
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,                             \
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \
-}
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform
- *          more actions.
- */
-#define port_lock() __disable_irq()
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform
- *          more actions.
- */
-#define port_unlock() __enable_irq()
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependent,
- *          in its simplest form it is void.
- * @note    Same as @p port_lock() in this port.
- */
-#define port_lock_from_isr() port_lock()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- * @note    Same as @p port_lock() in this port.
- */
-#define port_unlock_from_isr() port_unlock()
-
-/**
- * @brief   Disables all the interrupt sources.
- */
-#define port_disable() __disable_irq()
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- */
-#define port_suspend() __disable_irq()
-
-/**
- * @brief   Enables all the interrupt sources.
- */
-#define port_enable() __enable_irq()
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- * @note    Implemented as an inlined @p WFI instruction.
- */
-#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() __wfi()
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-#else
-#define port_switch(ntp, otp) {                                             \
-  uint8_t *r13 = (uint8_t *)__current_sp();                                 \
-  if ((stkalign_t *)(r13 - sizeof(struct intctx)) < otp->p_stklimit)        \
-    chDbgPanic("stack overflow");                                           \
-  _port_switch(ntp, otp);                                                   \
-}
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_halt(void);
-  void _port_irq_epilogue(regarm_t lr);
-  void _port_switch_from_isr(void);
-  void _port_exit_from_isr(void);
-  void _port_switch(Thread *ntp, Thread *otp);
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_V6M_H_ */
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.c b/os/ports/RVCT/ARMCMx/chcore_v7m.c
deleted file mode 100644
index 9912e3cb2..000000000
--- a/os/ports/RVCT/ARMCMx/chcore_v7m.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/chcore_v7m.c
- * @brief   ARMv7-M architecture port code.
- *
- * @addtogroup RVCT_ARMCMx_V7M_CORE
- * @{
- */
-
-#include "ch.h"
-
-/*===========================================================================*/
-/* Port interrupt handlers.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   System Timer vector.
- * @details This interrupt is used as system tick.
- * @note    The timer must be initialized in the startup code.
- */
-CH_IRQ_HANDLER(SysTickVector) {
-
-  CH_IRQ_PROLOGUE();
-
-  chSysLockFromIsr();
-  chSysTimerHandlerI();
-  chSysUnlockFromIsr();
-
-  CH_IRQ_EPILOGUE();
-}
-
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief   SVC vector.
- * @details The SVC vector is used for exception mode re-entering after a
- *          context switch.
- * @note    The PendSV vector is only used in advanced kernel mode.
- */
-void SVCallVector(void) {
-  struct extctx *ctxp;
-  register uint32_t psp __asm("psp");
-
-  /* Current PSP value.*/
-  ctxp = (struct extctx *)psp;
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp++;
-
-#if CORTEX_USE_FPU
-  /* Restoring the special register SCB_FPCCR.*/
-  SCB_FPCCR = (uint32_t)ctxp->fpccr;
-  SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx);
-#endif
-  psp = (uint32_t)ctxp;
-  port_unlock_from_isr();
-}
-#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
-
-#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief   PendSV vector.
- * @details The PendSV vector is used for exception mode re-entering after a
- *          context switch.
- * @note    The PendSV vector is only used in compact kernel mode.
- */
-void PendSVVector(void) {
-  struct extctx *ctxp;
-  register uint32_t psp __asm("psp");
-
-  /* Current PSP value.*/
-  ctxp = (struct extctx *)psp;
-
-  /* Discarding the current exception context and positioning the stack to
-     point to the real one.*/
-  ctxp++;
-
-#if CORTEX_USE_FPU
-  /* Restoring the special register SCB_FPCCR.*/
-  SCB_FPCCR = (uint32_t)ctxp->fpccr;
-  SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx);
-#endif
-  psp = (uint32_t)ctxp;
-}
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/*===========================================================================*/
-/* Port exported functions.                                                  */
-/*===========================================================================*/
-
-/**
- * @brief   Port-related initialization code.
- */
-void _port_init(void) {
-
-  /* Initialization of the vector table and priority related settings.*/
-  SCB_VTOR = CORTEX_VTOR_INIT;
-  SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT);
-
-#if CORTEX_USE_FPU
-  {
-    register uint32_t control __asm("control");
-    register uint32_t fpscr __asm("fpscr");
-
-    /* Initializing the FPU context save in lazy mode.*/
-    SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
-
-    /* CP10 and CP11 set to full access in the startup code.*/
-/*    SCB_CPACR |= 0x00F00000;*/
-
-    /* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/
-    control |= 4;
-
-    /* FPSCR and FPDSCR initially zero.*/
-    fpscr = 0;
-    SCB_FPDSCR = 0;
-  }
-#endif
-
-  /* Initialization of the system vectors used by the port.*/
-  nvicSetSystemHandlerPriority(HANDLER_SVCALL,
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
-  nvicSetSystemHandlerPriority(HANDLER_PENDSV,
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
-  nvicSetSystemHandlerPriority(HANDLER_SYSTICK,
-    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
-}
-
-/**
- * @brief   Exception exit redirection to _port_switch_from_isr().
- */
-void _port_irq_epilogue(void) {
-
-  port_lock_from_isr();
-  if ((SCB_ICSR & ICSR_RETTOBASE) != 0) {
-    struct extctx *ctxp;
-    register uint32_t psp __asm("psp");
-
-    /* Current PSP value.*/
-    ctxp = (struct extctx *)psp;
-
-    /* Adding an artificial exception return context, there is no need to
-       populate it fully.*/
-    ctxp--;
-    psp = (uint32_t)ctxp;
-    ctxp->xpsr = (regarm_t)0x01000000;
-
-    /* The exit sequence is different depending on if a preemption is
-       required or not.*/
-    if (chSchIsPreemptionRequired()) {
-#if CORTEX_USE_FPU
-      /* Triggering a lazy FPU state save.*/
-      register uint32_t fpscr __asm("fpscr");
-      ctxp->r0 = (regarm_t)fpscr;
-#endif
-      /* Preemption is required we need to enforce a context switch.*/
-      ctxp->pc = (regarm_t)_port_switch_from_isr;
-    }
-    else {
-      /* Preemption not required, we just need to exit the exception
-         atomically.*/
-      ctxp->pc = (regarm_t)_port_exit_from_isr;
-    }
-
-#if CORTEX_USE_FPU
-    {
-      uint32_t fpccr;
-
-      /* Saving the special register SCB_FPCCR into the reserved offset of
-         the Cortex-M4 exception frame.*/
-      (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR);
-
-      /* Now the FPCCR is modified in order to not restore the FPU status
-         from the artificial return context.*/
-      SCB_FPCCR = fpccr | FPCCR_LSPACT;
-    }
-#endif
-
-    /* Note, returning without unlocking is intentional, this is done in
-       order to keep the rest of the context switch atomic.*/
-    return;
-  }
-  port_unlock_from_isr();
-}
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h
deleted file mode 100644
index 677a4dfc0..000000000
--- a/os/ports/RVCT/ARMCMx/chcore_v7m.h
+++ /dev/null
@@ -1,512 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/chcore_v7m.h
- * @brief   ARMv7-M architecture port macros and structures.
- *
- * @addtogroup RVCT_ARMCMx_V7M_CORE
- * @{
- */
-
-#ifndef _CHCORE_V7M_H_
-#define _CHCORE_V7M_H_
-
-/*===========================================================================*/
-/* Port constants.                                                           */
-/*===========================================================================*/
-
-/**
- * @brief   Disabled value for BASEPRI register.
- */
-#define CORTEX_BASEPRI_DISABLED         0
-
-/*===========================================================================*/
-/* Port macros.                                                              */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- * @note    In this port it is set to 16 because the idle thread does have
- *          a stack frame when compiling without optimizations. You may
- *          reduce this value to zero when compiling with optimizations.
- */
-#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
-#define PORT_IDLE_THREAD_STACK_SIZE     16
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- *          area size.
- * @note    In this port this value is conservatively set to 32 because the
- *          function @p chSchDoReschedule() can have a stack frame, especially
- *          with compiler optimizations disabled. The value can be reduced
- *          when compiler optimizations are enabled.
- */
-#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK         32
-#endif
-
-/**
- * @brief   Enables the use of the WFI instruction in the idle thread loop.
- */
-#if !defined(CORTEX_ENABLE_WFI_IDLE)
-#define CORTEX_ENABLE_WFI_IDLE          FALSE
-#endif
-
-/**
- * @brief   SYSTICK handler priority.
- * @note    The default SYSTICK handler priority is calculated as the priority
- *          level in the middle of the numeric priorities range.
- */
-#if !defined(CORTEX_PRIORITY_SYSTICK)
-#define CORTEX_PRIORITY_SYSTICK         (CORTEX_PRIORITY_LEVELS >> 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
-
-/**
- * @brief   FPU support in context switch.
- * @details Activating this option activates the FPU support in the kernel.
- */
-#if !defined(CORTEX_USE_FPU)
-#define CORTEX_USE_FPU                  CORTEX_HAS_FPU
-#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
-/* This setting requires an FPU presence check in case it is externally
-   redefined.*/
-#error "the selected core does not have an FPU"
-#endif
-
-/**
- * @brief   Simplified priority handling flag.
- * @details Activating this option makes the Kernel work in compact mode.
- */
-#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
-#define CORTEX_SIMPLIFIED_PRIORITY      FALSE
-#endif
-
-/**
- * @brief   SVCALL handler priority.
- * @note    The default SVCALL handler priority is defaulted to
- *          @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
- *          @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
- *          priority level.
- */
-#if !defined(CORTEX_PRIORITY_SVCALL)
-#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1)
-#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
-#endif
-
-/**
- * @brief   NVIC VTOR initialization expression.
- */
-#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
-#define CORTEX_VTOR_INIT                0x00000000
-#endif
-
-/**
- * @brief   NVIC PRIGROUP initialization expression.
- * @details The default assigns all available priority bits as preemption
- *          priority with no sub-priority.
- */
-#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
-#define CORTEX_PRIGROUP_INIT            (7 - CORTEX_PRIORITY_BITS)
-#endif
-
-/*===========================================================================*/
-/* Port derived parameters.                                                  */
-/*===========================================================================*/
-
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-/**
- * @brief   Maximum usable priority for normal ISRs.
- */
-#define CORTEX_MAX_KERNEL_PRIORITY      (CORTEX_PRIORITY_SVCALL + 1)
-
-/**
- * @brief   BASEPRI level within kernel lock.
- * @note    In compact kernel mode this constant value is enforced to zero.
- */
-#define CORTEX_BASEPRI_KERNEL                                               \
-  CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY)
-#else
-
-#define CORTEX_MAX_KERNEL_PRIORITY      1
-#define CORTEX_BASEPRI_KERNEL           0
-#endif
-
-/**
- * @brief   PendSV priority level.
- * @note    This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,
- *          this handler always have the highest priority that cannot preempt
- *          the kernel.
- */
-#define CORTEX_PRIORITY_PENDSV          CORTEX_BASEPRI_KERNEL
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
-/**
- * @brief   Macro defining the specific ARM architecture.
- */
-#define CH_ARCHITECTURE_ARM_v7M
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "ARMv7-M"
-
-/**
- * @brief   Name of the architecture variant.
- */
-#define CH_CORE_VARIANT_NAME            "Cortex-M3"
-
-#elif (CORTEX_MODEL == CORTEX_M4)
-#define CH_ARCHITECTURE_ARM_v7ME
-#define CH_ARCHITECTURE_NAME            "ARMv7-ME"
-#if CORTEX_USE_FPU
-#define CH_CORE_VARIANT_NAME            "Cortex-M4F"
-#else
-#define CH_CORE_VARIANT_NAME            "Cortex-M4"
-#endif
-#endif
-
-/**
- * @brief   Port-specific information string.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define CH_PORT_INFO                    "Advanced kernel mode"
-#else
-#define CH_PORT_INFO                    "Compact kernel mode"
-#endif
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-#if !defined(_FROM_ASM_)
-
-/**
- * @brief   Generic ARM register.
- */
-typedef void *regarm_t;
-
-/**
- * @brief   Stack and memory alignment enforcement.
- * @note    In this architecture the stack alignment is enforced to 64 bits,
- *          32 bits alignment is supported by hardware but deprecated by ARM,
- *          the implementation choice is to not offer the option.
- */
-typedef uint64_t stkalign_t;
-
-/* The documentation of the following declarations is in chconf.h in order
-   to not have duplicated structure names into the documentation.*/
-#if !defined(__DOXYGEN__)
-
-struct extctx {
-  regarm_t      r0;
-  regarm_t      r1;
-  regarm_t      r2;
-  regarm_t      r3;
-  regarm_t      r12;
-  regarm_t      lr_thd;
-  regarm_t      pc;
-  regarm_t      xpsr;
-#if CORTEX_USE_FPU
-  regarm_t      s0;
-  regarm_t      s1;
-  regarm_t      s2;
-  regarm_t      s3;
-  regarm_t      s4;
-  regarm_t      s5;
-  regarm_t      s6;
-  regarm_t      s7;
-  regarm_t      s8;
-  regarm_t      s9;
-  regarm_t      s10;
-  regarm_t      s11;
-  regarm_t      s12;
-  regarm_t      s13;
-  regarm_t      s14;
-  regarm_t      s15;
-  regarm_t      fpscr;
-  regarm_t      fpccr;
-#endif /* CORTEX_USE_FPU */
-};
-
-struct intctx {
-#if CORTEX_USE_FPU
-  regarm_t      s16;
-  regarm_t      s17;
-  regarm_t      s18;
-  regarm_t      s19;
-  regarm_t      s20;
-  regarm_t      s21;
-  regarm_t      s22;
-  regarm_t      s23;
-  regarm_t      s24;
-  regarm_t      s25;
-  regarm_t      s26;
-  regarm_t      s27;
-  regarm_t      s28;
-  regarm_t      s29;
-  regarm_t      s30;
-  regarm_t      s31;
-#endif /* CORTEX_USE_FPU */
-  regarm_t      r4;
-  regarm_t      r5;
-  regarm_t      r6;
-  regarm_t      r7;
-  regarm_t      r8;
-  regarm_t      r9;
-  regarm_t      r10;
-  regarm_t      r11;
-  regarm_t      lr;
-};
-
-#endif /* !defined(__DOXYGEN__) */
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details In this port the structure just holds a pointer to the @p intctx
- *          structure representing the stack pointer at context switch time.
- */
-struct context {
-  struct intctx *r13;
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
-                                     wsize -                                \
-                                     sizeof(struct intctx));                \
-  tp->p_ctx.r13->r4 = (regarm_t)pf;                                         \
-  tp->p_ctx.r13->r5 = (regarm_t)arg;                                        \
-  tp->p_ctx.r13->lr = (regarm_t)_port_thread_start;                         \
-}
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   sizeof(struct intctx) +                  \
-                                   sizeof(struct extctx) +                  \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Fast IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_FAST_IRQ_HANDLER(id) void id(void)
-
-/**
- * @brief   Port-related initialization code.
- */
-#define port_init() _port_init()
-
-/**
- * @brief   Kernel-lock action.
- * @details Usually this function just disables interrupts but may perform
- *          more actions.
- * @note    In this port this it raises the base priority to kernel level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_lock() {                                                       \
-  register uint32_t basepri __asm("basepri");                               \
-  basepri = CORTEX_BASEPRI_KERNEL;                                          \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_lock() __disable_irq()
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Kernel-unlock action.
- * @details Usually this function just enables interrupts but may perform
- *          more actions.
- * @note    In this port this it lowers the base priority to user level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_unlock() {                                                     \
-  register uint32_t basepri __asm("basepri");                               \
-  basepri = CORTEX_BASEPRI_DISABLED;                                        \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_unlock() __enable_irq()
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @details This function is invoked before invoking I-class APIs from
- *          interrupt handlers. The implementation is architecture dependent,
- *          in its simplest form it is void.
- * @note    Same as @p port_lock() in this port.
- */
-#define port_lock_from_isr() port_lock()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @details This function is invoked after invoking I-class APIs from interrupt
- *          handlers. The implementation is architecture dependent, in its
- *          simplest form it is void.
- * @note    Same as @p port_unlock() in this port.
- */
-#define port_unlock_from_isr() port_unlock()
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Of course non-maskable interrupt sources are not included.
- * @note    In this port it disables all the interrupt sources by raising
- *          the priority mask to level 0.
- */
-#define port_disable() __disable_irq()
-
-/**
- * @brief   Disables the interrupt sources below kernel-level priority.
- * @note    Interrupt sources above kernel level remains enabled.
- * @note    In this port it raises/lowers the base priority to kernel level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_suspend() {                                                    \
-  register uint32_t basepri __asm("basepri");                               \
-  basepri = CORTEX_BASEPRI_KERNEL;                                          \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_suspend() __disable_irq()
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Enables all the interrupt sources.
- * @note    In this port it lowers the base priority to user level.
- */
-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
-#define port_enable() {                                                     \
-  register uint32_t basepri __asm("basepri");                               \
-  basepri = CORTEX_BASEPRI_DISABLED;                                        \
-  __enable_irq();                                                           \
-}
-#else /* CORTEX_SIMPLIFIED_PRIORITY */
-#define port_enable() __enable_irq()
-#endif /* CORTEX_SIMPLIFIED_PRIORITY */
-
-/**
- * @brief   Enters an architecture-dependent IRQ-waiting mode.
- * @details The function is meant to return when an interrupt becomes pending.
- *          The simplest implementation is an empty function or macro but this
- *          would not take advantage of architecture-specific power saving
- *          modes.
- * @note    Implemented as an inlined @p WFI instruction.
- */
-#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() __wfi()
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    The implementation of this code affects <b>directly</b> the context
- *          switch performance so optimize here as much as you can.
- *
- * @param[in] ntp       the thread to be switched in
- * @param[in] otp       the thread to be switched out
- */
-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
-#define port_switch(ntp, otp) _port_switch(ntp, otp)
-#else
-#define port_switch(ntp, otp) {                                             \
-  uint8_t *r13 = (uint8_t *)__current_sp();                                 \
-  if ((stkalign_t *)(r13 - sizeof(struct intctx)) < otp->p_stklimit)        \
-    chDbgPanic("stack overflow");                                           \
-  _port_switch(ntp, otp);                                                   \
-}
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void port_halt(void);
-  void _port_init(void);
-  void _port_irq_epilogue(void);
-  void _port_switch_from_isr(void);
-  void _port_exit_from_isr(void);
-  void _port_switch(Thread *ntp, Thread *otp);
-  void _port_thread_start(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FROM_ASM_ */
-
-#endif /* _CHCORE_V7M_H_ */
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
deleted file mode 100644
index 282ac547d..000000000
--- a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/*
- * Imports the Cortex-Mx configuration headers.
- */
-#define _FROM_ASM_
-#include "chconf.h"
-#include "chcore.h"
-
-CONTEXT_OFFSET  EQU     12
-SCB_ICSR        EQU     0xE000ED04
-
-                PRESERVE8
-                THUMB
-                AREA    |.text|, CODE, READONLY
-
-                IMPORT  chThdExit
-                IMPORT  chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-                IMPORT  dbg_check_unlock
-                IMPORT  dbg_check_lock
-#endif
-
-/*
- * Performs a context switch between two threads.
- */
-                EXPORT _port_switch
-_port_switch    PROC
-                push    {r4, r5, r6, r7, lr}
-                mov     r4, r8
-                mov     r5, r9
-                mov     r6, r10
-                mov     r7, r11
-                push    {r4, r5, r6, r7}
-                mov     r3, sp
-                str     r3, [r1, #CONTEXT_OFFSET]
-                ldr     r3, [r0, #CONTEXT_OFFSET]
-                mov     sp, r3
-                pop     {r4, r5, r6, r7}
-                mov     r8, r4
-                mov     r9, r5
-                mov     r10, r6
-                mov     r11, r7
-                pop     {r4, r5, r6, r7, pc}
-                ENDP
-
-/*
- * Start a thread by invoking its work function.
- * If the work function returns @p chThdExit() is automatically invoked.
- */
-                EXPORT  _port_thread_start
-_port_thread_start PROC
-#if CH_DBG_SYSTEM_STATE_CHECK
-                bl      dbg_check_unlock
-#endif
-                cpsie   i
-                mov     r0, r5
-                blx     r4
-                bl      chThdExit
-                ENDP
-
-/*
- * Post-IRQ switch code.
- * Exception handlers return here for context switching.
- */
-                EXPORT  _port_switch_from_isr
-                EXPORT  _port_exit_from_isr
-_port_switch_from_isr PROC
-#if CH_DBG_SYSTEM_STATE_CHECK
-                bl      dbg_check_lock
-#endif
-                bl      chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-                bl      dbg_check_unlock
-#endif
-_port_exit_from_isr
-                ldr     r2, =SCB_ICSR
-                movs    r3, #128
-#if CORTEX_ALTERNATE_SWITCH
-                lsls    r3, r3, #21
-                str     r3, [r2, #0]
-                cpsie   i
-#else
-                lsls    r3, r3, #24
-                str     r3, [r2, #0]
-#endif
-waithere        b       waithere
-                ENDP
-
-                END
diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s
deleted file mode 100644
index e9404daba..000000000
--- a/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/*
- * Imports the Cortex-Mx configuration headers.
- */
-#define _FROM_ASM_
-#include "chconf.h"
-#include "chcore.h"
-
-CONTEXT_OFFSET  EQU     12
-SCB_ICSR        EQU     0xE000ED04
-ICSR_PENDSVSET  EQU     0x10000000
-
-                PRESERVE8
-                THUMB
-                AREA    |.text|, CODE, READONLY
-
-                IMPORT  chThdExit
-                IMPORT  chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-                IMPORT  dbg_check_unlock
-                IMPORT  dbg_check_lock
-#endif
-
-/*
- * Performs a context switch between two threads.
- */
-                EXPORT _port_switch
-_port_switch    PROC
-                push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-#if CORTEX_USE_FPU
-                vpush   {s16-s31}
-#endif
-                str     sp, [r1, #CONTEXT_OFFSET]                          
-                ldr     sp, [r0, #CONTEXT_OFFSET]
-#if CORTEX_USE_FPU
-                vpop    {s16-s31}
-#endif
-                pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}
-                ENDP
-
-/*
- * Start a thread by invoking its work function.
- * If the work function returns @p chThdExit() is automatically invoked.
- */
-                EXPORT  _port_thread_start
-_port_thread_start PROC
-#if CH_DBG_SYSTEM_STATE_CHECK
-                bl      dbg_check_unlock
-#endif
-#if CORTEX_SIMPLIFIED_PRIORITY
-                cpsie   i
-#else
-                movs    r3, #CORTEX_BASEPRI_DISABLED
-                msr     BASEPRI, r3
-#endif
-                mov     r0, r5
-                blx     r4
-                bl      chThdExit
-                ENDP
-
-/*
- * Post-IRQ switch code.
- * Exception handlers return here for context switching.
- */
-                EXPORT  _port_switch_from_isr
-                EXPORT  _port_exit_from_isr
-_port_switch_from_isr PROC
-#if CH_DBG_SYSTEM_STATE_CHECK
-                bl      dbg_check_lock
-#endif
-                bl      chSchDoReschedule
-#if CH_DBG_SYSTEM_STATE_CHECK
-                bl      dbg_check_unlock
-#endif
-_port_exit_from_isr
-#if CORTEX_SIMPLIFIED_PRIORITY
-                mov     r3, #SCB_ICSR :AND: 0xFFFF
-                movt    r3, #SCB_ICSR :SHR: 16
-                mov     r2, #ICSR_PENDSVSET
-                str     r2, [r3, #0]
-                cpsie   i
-waithere        b       waithere
-#else
-                svc     #0
-#endif
-                ENDP
-
-                END
diff --git a/os/ports/RVCT/ARMCMx/chtypes.h b/os/ports/RVCT/ARMCMx/chtypes.h
deleted file mode 100644
index ec76fd523..000000000
--- a/os/ports/RVCT/ARMCMx/chtypes.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    RVCT/ARMCMx/chtypes.h
- * @brief   ARM Cortex-Mx port system types.
- *
- * @addtogroup RVCT_ARMCMx_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint32_t        tprio_t;        /**< Thread priority.               */
-typedef int32_t         msg_t;          /**< Inter-thread message.          */
-typedef int32_t         eventid_t;      /**< Event Id.                      */
-typedef uint32_t        eventmask_t;    /**< Event mask.                    */
-typedef uint32_t        flagsmask_t;    /**< Event flags.                   */
-typedef uint32_t        systime_t;      /**< System time.                   */
-typedef int32_t         cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE __inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    It is set to use the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_STRUCT
-
-/**
- * @brief   Packed structure modifier (before).
- */
-#define PACK_STRUCT_BEGIN __packed
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-/**
- * @brief   Packed variable specifier.
- */
-#define PACKED_VAR __packed
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/RVCT/ARMCMx/cstartup.s b/os/ports/RVCT/ARMCMx/cstartup.s
deleted file mode 100644
index e0c6b85ee..000000000
--- a/os/ports/RVCT/ARMCMx/cstartup.s
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-;/* <<< Use Configuration Wizard in Context Menu >>> */
-
-;// <h> Main Stack Configuration (IRQ Stack)
-;//   <o> Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;// </h>
-main_stack_size EQU     0x00000400
-
-;// <h> Process Stack Configuration
-;//   <o> Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;// </h>
-proc_stack_size EQU     0x00000400
-
-;// <h> C-runtime heap size
-;//   <o> C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8>
-;// </h>
-heap_size       EQU     0x00000400
-
-                AREA    MSTACK, NOINIT, READWRITE, ALIGN=3
-main_stack_mem  SPACE   main_stack_size
-                EXPORT  __initial_msp
-__initial_msp
-
-                AREA    CSTACK, NOINIT, READWRITE, ALIGN=3
-__main_thread_stack_base__
-                EXPORT  __main_thread_stack_base__
-proc_stack_mem  SPACE   proc_stack_size
-                EXPORT  __initial_sp
-__initial_sp
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   heap_size
-__heap_limit
-
-CONTROL_MODE_PRIVILEGED     EQU     0
-CONTROL_MODE_UNPRIVILEGED   EQU     1
-CONTROL_USE_MSP             EQU     0
-CONTROL_USE_PSP             EQU     2
-
-                PRESERVE8
-                THUMB
-
-                AREA    |.text|, CODE, READONLY
-
-/*
- * Reset handler.
- */
-                IMPORT  __main
-                EXPORT  Reset_Handler
-Reset_Handler   PROC
-                cpsid   i
-                ldr     r0, =__initial_sp
-                msr     PSP, r0
-                movs    r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP
-                msr     CONTROL, r0
-                isb
-                bl      __early_init
-
-                IF      {CPU} = "Cortex-M4.fp"
-                LDR     R0, =0xE000ED88           ; Enable CP10,CP11
-                LDR     R1, [R0]
-                ORR     R1, R1, #(0xF << 20)
-                STR     R1, [R0]
-                ENDIF
-
-                ldr     r0, =__main
-                bx      r0
-                ENDP
-
-__early_init    PROC
-                EXPORT  __early_init            [WEAK]
-                bx      lr
-                ENDP
-
-                ALIGN
-
-/*
- * User Initial Stack & Heap.
- */
-                IF      :DEF:__MICROLIB
-                
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-                ldr     r0, =Heap_Mem
-                ldr     r1, =(proc_stack_mem + proc_stack_size)
-                ldr     r2, =(Heap_Mem + heap_size)
-                ldr     r3, =proc_stack_mem
-                bx      lr
-
-                ALIGN
-
-                ENDIF
-
-                END
diff --git a/os/ports/RVCT/ARMCMx/port.dox b/os/ports/RVCT/ARMCMx/port.dox
deleted file mode 100644
index 66f9ec23f..000000000
--- a/os/ports/RVCT/ARMCMx/port.dox
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup RVCT_ARMCMx ARM Cortex-Mx
- * @details ARM Cortex-Mx port for the RVCT compiler.
- 
- * @section RVCT_ARMCMx_INTRO Introduction
- * This port supports all the cores implementing the ARMv6-M and ARMv7-M
- * architectures.
- *
- * @section RVCT_ARMCMx_MODES Kernel Modes
- * The Cortex-Mx port supports two distinct kernel modes:
- * - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
- *   interrupt sources with priorities below or equal to the
- *   @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
- *   the kernel critical sections and can be used for fast interrupts.
- *   This mode is not available in the ARMv6-M architecture which does not
- *   support priority masking.
- * - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
- *   in a simplified way, all interrupt sources are disabled when the kernel
- *   enters into a critical zone and re-enabled on exit. This is simple and
- *   adequate for most applications, this mode results in a more compact and
- *   faster kernel.
- * .
- * The selection of the mode is performed using the port configuration option
- * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
- * interrupts there are no other differences between the two modes. The
- * kernel API is exactly the same.
- *
- * @section RVCT_ARMCMx_STATES_A System logical states in Compact Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
- * Kernel mode:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). In this state interrupts are enabled. The processor
- *   is running in thread-privileged mode.
- * - <b>Suspended</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in thread-privileged mode. In this
- *   mode this state is not different from the <b>Disabled</b> state.
- * - <b>Disabled</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in thread-privileged mode. In this
- *   mode this state is not different from the <b>Suspended</b> state.
- * - <b>Sleep</b>. This state is entered with the execution of the specific
- *   instruction @p <b>wfi</b>.
- * - <b>S-Locked</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in thread-privileged mode.
- * - <b>I-Locked</b>. In this state the interrupt sources are globally
- *   disabled. The processor is running in exception-privileged mode.
- * - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
- *   not globally masked but only interrupts with higher priority can preempt
- *   the current handler. The processor is running in exception-privileged
- *   mode.
- * - <b>Serving Fast Interrupt</b>. Not implemented in compact kernel mode.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
- *   asynchronous NMI vector and several synchronous fault vectors that can
- *   be considered belonging to this category.
- * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
- *   the maskable interrupt sources. The ARM state is whatever the processor
- *   was running when @p chSysHalt() was invoked.
- *
- * @section RVCT_ARMCMx_STATES_B System logical states in Advanced Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the
- * Advanced Kernel mode:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
- *   set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
- *   processor is running in thread-privileged mode.
- * - <b>Suspended</b>. In this state the interrupt sources are not globally
- *   masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- *   masking any interrupt source with lower or equal priority. The processor
- *   is running in thread-privileged mode.
- * - <b>Disabled</b>. Interrupt sources are globally masked. The processor
- *   is running in thread-privileged mode.
- * - <b>Sleep</b>. This state is entered with the execution of the specific
- *   instruction @p <b>wfi</b>.
- * - <b>S-Locked</b>. In this state the interrupt sources are not globally
- *   masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- *   masking any interrupt source with lower or equal priority. The processor
- *   is running in thread-privileged mode.
- * - <b>I-Locked</b>. In this state the interrupt sources are not globally
- *   masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
- *   masking any interrupt source with lower or equal priority. The processor
- *   is running in exception-privileged mode.
- * - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
- *   not globally masked but only interrupts with higher priority can preempt
- *   the current handler. The processor is running in exception-privileged
- *   mode.
- * - <b>Serving Fast Interrupt</b>. Fast interrupts are defined as interrupt
- *   sources having higher priority level than the kernel
- *   (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to
- *   the I-Locked state because fast interrupts can preempt the kernel
- *   critical zone.<br>
- *   This state is not implemented in the ARMv6-M implementation because
- *   priority masking is not present in this architecture.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
- *   asynchronous NMI vector and several synchronous fault vectors that can
- *   be considered belonging to this category.
- * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
- *   the maskable interrupt sources. The ARM state is whatever the processor
- *   was running when @p chSysHalt() was invoked.
- * .
- * @section RVCT_ARMCMx_NOTES ARM Cortex-Mx/RVCT port notes
- * The ARM Cortex-Mx port is organized as follow:
- * - The @p main() function is invoked in thread-privileged mode.
- * - Each thread has a private process stack, the system has a single main
- *   stack where all the interrupts and exceptions are processed.
- * - The threads are started in thread-privileged mode.
- * - Interrupt nesting and the other advanced core/NVIC features are supported.
- * - The Cortex-Mx port is perfectly generic, support for more devices can be
- *   easily added by adding a subdirectory under <tt>./os/ports/RVCT/ARMCMx</tt>
- *   and giving it the name of the new device, then copy the files from another
- *   device into the new directory and customize them for the new device.
- * - The free uVision is not able to handle scatter files, the following
- *   options are required in the project options under "Preprocesso symbols"
- *   in order to use the unused RAM as heap automatically:
- *   <tt>__heap_base__=Image$$RW_IRAM1$$ZI$$Limit
- *   __heap_end__=Image$$RW_IRAM2$$Base</tt>
- * .
- * @ingroup rvct
- */
-
-/**
- * @defgroup RVCT_ARMCMx_CONF Configuration Options
- * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some
- * architecture-specific configurations settings that can be overridden
- * by redefining them in @p chconf.h. Usually there is no need to change
- * the default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
- *   by an interrupt handler between the @p extctx and @p intctx
- *   structures.
- * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
- *   thread. Usually there is no need to change this value unless inserting
- *   code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
- * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
- * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
- * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
- *   @p <b>wfi</b> instruction from within the idle loop. This option is
- *   defaulted to FALSE because it can create problems with some debuggers.
- *   Setting this option to TRUE reduces the system power requirements.
- * .
- * @section RVCT_ARMCMx_CONF_1 ARMv6-M specific options
- * The following options are specific for the ARMv6-M architecture:
- * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
- *   exception instead of NMI as preemption handler.
- * .
- * @section RVCT_ARMCMx_CONF_2 ARMv7-M specific options
- * The following options are specific for the ARMv6-M architecture:
- * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
- * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
- *   mode.
- * .
- * @ingroup RVCT_ARMCMx
- */
-
-/**
- * @defgroup RVCT_ARMCMx_CORE Core Port Implementation
- * @details ARM Cortex-Mx specific port code, structures and macros.
- *
- * @ingroup RVCT_ARMCMx
- */
-
-/**
- * @defgroup RVCT_ARMCMx_V6M_CORE ARMv6-M Specific Implementation
- * @details ARMv6-M specific port code, structures and macros.
- *
- * @ingroup RVCT_ARMCMx_CORE
- */
-
-/**
- * @defgroup RVCT_ARMCMx_V7M_CORE ARMv7-M Specific Implementation
- * @details ARMv7-M specific port code, structures and macros.
- *
- * @ingroup RVCT_ARMCMx_CORE
- */
-
-/**
- * @defgroup RVCT_ARMCMx_STARTUP Startup Support
- * @details ChibiOS/RT provides its own generic startup file for the ARM
- * Cortex-Mx port.
- * Of course it is not mandatory to use it but care should be taken about the
- * startup phase details.
- *
- * @section RVCT_ARMCMx_STARTUP_1 Startup Process
- * The startup process, as implemented, is the following:
- * -# Interrupts are masked globally.
- * -# The two stacks are initialized by assigning them the sizes defined in
- *    <tt>cstartup.s</tt> file and accessible through the configuration wizard.
- * -# The CPU state is switched to Privileged and the PSP stack is used.
- * -# An early initialization routine @p __early_init() is invoked, if the
- *    symbol is not defined then an empty default routine is executed
- *    (weak symbol).
- * -# Control is passed to the C runtime entry point @p __main that performs
- *    the required initializations before invoking the @p main() function.
- * .
- * @ingroup RVCT_ARMCMx
- */
-
-/**
- * @defgroup RVCT_ARMCMx_NVIC NVIC Support
- * @details ARM Cortex-Mx NVIC support.
- *
- * @ingroup RVCT_ARMCMx
- */
-
-/**
- * @defgroup RVCT_ARMCMx_SPECIFIC Specific Implementations
- * @details Platform-specific port code.
- *
- * @ingroup RVCT_ARMCMx
- */
diff --git a/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h b/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h
deleted file mode 100644
index 5fd6ff4af..000000000
--- a/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* ---------------------------------------------------------------------- 
-* Copyright (C) 2010 ARM Limited. All rights reserved. 
-* 
-* $Date:        11. November 2010  
-* $Revision: 	V1.0.2  
-* 
-* Project: 	    CMSIS DSP Library 
-* Title:	    arm_common_tables.h 
-* 
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
-* 
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.0.2 2010/11/11 
-*    Documentation updated.  
-* 
-* Version 1.0.1 2010/10/05  
-*    Production release and review comments incorporated. 
-* 
-* Version 1.0.0 2010/09/20  
-*    Production release and review comments incorporated. 
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-extern const q31_t realCoefAQ31[1024];
-extern const q31_t realCoefBQ31[1024];
-extern const float32_t twiddleCoef[6144];
-extern const q31_t twiddleCoefQ31[6144];
-extern const q15_t twiddleCoefQ15[6144];
-
-#endif /*  ARM_COMMON_TABLES_H */
diff --git a/os/ports/common/ARMCMx/CMSIS/include/arm_math.h b/os/ports/common/ARMCMx/CMSIS/include/arm_math.h
deleted file mode 100644
index 266dbfc91..000000000
--- a/os/ports/common/ARMCMx/CMSIS/include/arm_math.h
+++ /dev/null
@@ -1,7578 +0,0 @@
-/* ----------------------------------------------------------------------   
- * Copyright (C) 2010-2011 ARM Limited. All rights reserved.   
- *   
- * $Date:        15. February 2012  
- * $Revision: 	V1.1.0  
- *   
- * Project: 	    CMSIS DSP Library   
- * Title:	     	arm_math.h
- *   
- * Description:	 Public header file for CMSIS DSP Library
- *   
- * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
- *  
- * Version 1.1.0 2012/02/15 
- *    Updated with more optimizations, bug fixes and minor API changes.  
- *  
- * Version 1.0.10 2011/7/15 
- *    Big Endian support added and Merged M0 and M3/M4 Source code.  
- *   
- * Version 1.0.3 2010/11/29  
- *    Re-organized the CMSIS folders and updated documentation.   
- *    
- * Version 1.0.2 2010/11/11   
- *    Documentation updated.    
- *   
- * Version 1.0.1 2010/10/05    
- *    Production release and review comments incorporated.   
- *   
- * Version 1.0.0 2010/09/20    
- *    Production release and review comments incorporated.   
- * -------------------------------------------------------------------- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * <b>Introduction</b>
-   *
-   * This user manual describes the CMSIS DSP software library, 
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:  
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values. 
-   *
-   * <b>Pre-processor Macros</b> 
-   * 
-   * Each library project have differant pre-processor macros. 
-   * 
-   * - UNALIGNED_SUPPORT_DISABLE: 
-   * 
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access    
-   * 
-   * - ARM_MATH_BIG_ENDIAN: 
-   * 
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. 
-   * 
-   * - ARM_MATH_MATRIX_CHECK: 
-   * 
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices 
-   * 
-   * - ARM_MATH_ROUNDING: 
-   * 
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on cortex-M0 target.
-   * 
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries 
-   *
-   * <b>Toolchain Support</b>
-   *
-   * The library has been developed and tested with MDK-ARM version 4.23. 
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * <b>Using the Library</b>
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
-   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
-   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
-   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
-   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
-   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single 
-   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. 
-   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or 
-   * ARM_MATH_CM0 depending on the target processor in the application.
-   *
-   * <b>Examples</b>
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * <b>Building the Library</b>
-   *
-   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
-   * - arm_cortexM0b_math.uvproj
-   * - arm_cortexM0l_math.uvproj
-   * - arm_cortexM3b_math.uvproj
-   * - arm_cortexM3l_math.uvproj  
-   * - arm_cortexM4b_math.uvproj
-   * - arm_cortexM4l_math.uvproj
-   * - arm_cortexM4bf_math.uvproj
-   * - arm_cortexM4lf_math.uvproj
-   *
-   *
-   * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above.
-   *
-   * <b>Copyright Notice</b>
-   *
-   * Copyright (C) 2010 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* CHIBIOS FIX BEGIN */
-#include "board.h"
-#if defined(STM32F4XX)
-#define ARM_MATH_CM4
-#define __FPU_PRESENT 1
-#elif (defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) ||                    \
-       defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) ||                    \
-       defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                       \
-       defined(STM32F10X_CL))
-#define ARM_MATH_CM3
-#elif defined(STM32F0XX)
-#define ARM_MATH_CM0
-#endif
-/* CHIBIOS FIX END */
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined (ARM_MATH_CM4)
-#include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
-#include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-#include "core_cm0.h"
-#else
-#include "ARMCM4.h"
-#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef	__cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31 			(0x100)
-#define DELTA_Q15 			0x5
-#define INDEX_MASK 			0x0000003F
-#ifndef PI
-#define PI					3.14159265358979f
-#endif
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define TABLE_SIZE			256
-#define TABLE_SPACING_Q31	0x800000
-#define TABLE_SPACING_Q15	0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING			0xB60B61
-
-  /**
-   * @brief Macro for Unaligned Support
-   */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-    #define ALIGN4
-#else
-  #if defined  (__GNUC__)
-    #define ALIGN4 __attribute__((aligned(4)))
-  #else
-    #define ALIGN4 __align(4)
-  #endif
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-  } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#if defined  (__GNUC__)
-  #define __SIMD32(addr)         (*( int32_t **) & (addr))
-  #define  _SIMD32_OFFSET(addr)  (*( int32_t * )   (addr))
-#else
-  #define __SIMD32(addr)         (*(__packed                    int32_t **) & (addr))
-  #define  _SIMD32_OFFSET(addr)  (*(__packed                    int32_t * )   (addr))
-#endif 
-
-  #define __SIMD64(addr)  (*(int64_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
-                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
-                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-#endif
-
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  __STATIC_INLINE q31_t clip_q63_to_q31(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  __STATIC_INLINE q15_t clip_q63_to_q15(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  __STATIC_INLINE q7_t clip_q31_to_q7(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  __STATIC_INLINE q15_t clip_q31_to_q15(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  __STATIC_INLINE q63_t mult32x64(
-  q63_t x,
-  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-
-#if defined (ARM_MATH_CM0) && defined ( __CC_ARM   )
-#define __CLZ __clz
-#endif
-
-#if defined (ARM_MATH_CM0) && defined ( __TASKING__ )
-/* No need to redefine __CLZ */
-#endif
-
-#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) )
-
-  __STATIC_INLINE  uint32_t __CLZ(q31_t data);
-
-
-  __STATIC_INLINE uint32_t __CLZ(q31_t data)
-  {
-    uint32_t count = 0;
-    uint32_t mask = 0x80000000;
-
-    while((data & mask) == 0)
-    {
-      count += 1u;
-      mask = mask >> 1u;
-    }
-
-    return (count);
-
-  }
-
-#endif
-
-  /**
-   * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
-   */
-
-  __STATIC_INLINE uint32_t arm_recip_q31(
-  q31_t in,
-  q31_t * dst,
-  q31_t * pRecipTable)
-  {
-
-    uint32_t out, tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if(in > 0)
-    {
-      signBits = __CLZ(in) - 1;
-    }
-    else
-    {
-      signBits = __CLZ(-in) - 1;
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t) (in >> 24u);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-    {
-      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
-      tempVal = 0x7FFFFFFF - tempVal;
-      /*      1.31 with exp 1 */
-      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
-      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-
-  }
-
-  /**
-   * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
-   */
-  __STATIC_INLINE uint32_t arm_recip_q15(
-  q15_t in,
-  q15_t * dst,
-  q15_t * pRecipTable)
-  {
-
-    uint32_t out = 0, tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if(in > 0)
-    {
-      signBits = __CLZ(in) - 17;
-    }
-    else
-    {
-      signBits = __CLZ(-in) - 17;
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = in >> 8;
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0; i < 2; i++)
-    {
-      tempVal = (q15_t) (((q31_t) in * out) >> 15);
-      tempVal = 0x7FFF - tempVal;
-      /*      1.15 with exp 1 */
-      out = (q15_t) (((q31_t) out * tempVal) >> 14);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-
-  }
-
-
-  /*
-   * @brief C custom defined intrinisic function for only M0 processors
-   */
-#if defined(ARM_MATH_CM0)
-
-  __STATIC_INLINE q31_t __SSAT(
-  q31_t x,
-  uint32_t y)
-  {
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++)
-    {
-      posMax = posMax * 2;
-    }
-
-    if(x > 0)
-    {
-      posMax = (posMax - 1);
-
-      if(x > posMax)
-      {
-        x = posMax;
-      }
-    }
-    else
-    {
-      negMin = -posMax;
-
-      if(x < negMin)
-      {
-        x = negMin;
-      }
-    }
-    return (x);
-
-
-  }
-
-#endif /* end of ARM_MATH_CM0 */
-
-
-
-  /*
-   * @brief C custom defined intrinsic function for M3 and M0 processors
-   */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __QADD8(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q7_t r, s, t, u;
-
-    r = (q7_t) x;
-    s = (q7_t) y;
-
-    r = __SSAT((q31_t) (r + s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
-    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
-    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
-
-    sum =
-      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
-      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __QSUB8(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s, t, u;
-
-    r = (q7_t) x;
-    s = (q7_t) y;
-
-    r = __SSAT((r - s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
-    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
-    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
-
-    sum =
-      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
-                                                                0x000000FF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __QADD16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = __SSAT(r + s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SHADD16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) + (s >> 1));
-    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __QSUB16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = __SSAT(r - s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SHSUB16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t diff;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) - (s >> 1));
-    s = (((x >> 17) - (y >> 17)) << 16);
-
-    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return diff;
-  }
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __QASX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum =
-      ((sum +
-        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SHASX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) - (y >> 17));
-    s = (((x >> 17) + (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __QSAX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum =
-      ((sum +
-        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SHSAX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) + (y >> 17));
-    s = (((x >> 17) - (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SMUSDX(
-  q31_t x,
-  q31_t y)
-  {
-
-    return ((q31_t) (((short) x * (short) (y >> 16)) -
-                     ((short) (x >> 16) * (short) y)));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SMUADX(
-  q31_t x,
-  q31_t y)
-  {
-
-    return ((q31_t) (((short) x * (short) (y >> 16)) +
-                     ((short) (x >> 16) * (short) y)));
-  }
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __QADD(
-  q31_t x,
-  q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x + y);
-  }
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __QSUB(
-  q31_t x,
-  q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x - y);
-  }
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SMLAD(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
-            ((short) x * (short) y));
-  }
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SMLADX(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y)) +
-            ((short) x * (short) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SMLSDX(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum - ((short) (x >> 16) * (short) (y)) +
-            ((short) x * (short) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  __STATIC_INLINE q63_t __SMLALD(
-  q31_t x,
-  q31_t y,
-  q63_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
-            ((short) x * (short) y));
-  }
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  __STATIC_INLINE q63_t __SMLALDX(
-  q31_t x,
-  q31_t y,
-  q63_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) y)) +
-      ((short) x * (short) (y >> 16));
-  }
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SMUAD(
-  q31_t x,
-  q31_t y)
-  {
-
-    return (((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SMUSD(
-  q31_t x,
-  q31_t y)
-  {
-
-    return (-((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-
-  /*
-   * @brief C custom defined SXTB16 for M3 and M0 processors
-   */
-  __STATIC_INLINE q31_t __SXTB16(
-  q31_t x)
-  {
-
-    return ((((x << 24) >> 24) & 0x0000FFFF) |
-            (((x << 8) >> 8) & 0xFFFF0000));
-  }
-
-
-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in] *S points to an instance of the Q7 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] *S points to an instance of the Q7 FIR structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed.
-   * @return none
-   */
-  void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in] *S points to an instance of the Q15 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * <code>numTaps</code> is not a supported value.
-   */
-
-  arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in] *S points to an instance of the Q31 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] *S points to an instance of the Q31 FIR structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return 		none.
-   */
-  void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in] *S points to an instance of the floating-point FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return    	none.
-   */
-  void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q15;
-
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-
-
-  } arm_biquad_casd_df1_inst_f32;
-
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages      number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift);
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q31;
-
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA  points to the first input matrix structure
-   * @param[in]       *pSrcB  points to the second input matrix structure
-   * @param[out]      *pDst   points to output matrix structure
-   * @param[in]		  *pState points to the array for storing intermediate results  
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[in]  scale scale factor
-   * @param[out] *pDst points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData);
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData);
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
-#ifdef ARM_MATH_CM0
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];       /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;               /**< The proportional gain. */
-    float32_t Ki;               /**< The integral gain. */
-    float32_t Kd;               /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] *S      points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @return none
-   */
-
-  void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S);
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the q15 PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t *pData;   /**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t *pData;                /**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q15;
-
-  /**
-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
-  } arm_cfft_radix2_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc);
-
-  /**
-   * @brief Processing function for the Q15 CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc);
-
-  /**
-   * @brief Initialization function for the Q15 CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-
-  arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Initialization function for the Q15 CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-
-  arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the Q31 CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc);
-
-  /**
-   * @brief  Initialization function for the Q31 CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-
-  arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-  q31_t * pSrc);
-
-  /**
-   * @brief  Initialization function for the Radix-2 Q31 CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-
-  arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-
-
-  /**
-   * @brief Processing function for the floating-point CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief  Initialization function for the floating-point CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-
-  arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the floating-point CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief  Initialization function for the floating-point CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-
-  arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-
-
-  /*----------------------------------------------------------------------
-   *		Internal functions prototypes FFT function
-   ----------------------------------------------------------------------*/
-
-  /**
-   * @brief  Core function for the floating-point CFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to the twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_f32(
-  float32_t * pSrc,
-  uint16_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier);
-
-  /**
-   * @brief  Core function for the floating-point CIFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @param[in]      onebyfftLen      value of 1/fftLen.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_inverse_f32(
-  float32_t * pSrc,
-  uint16_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier,
-  float32_t onebyfftLen);
-
-  /**
-   * @brief  In-place bit reversal function.
-   * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.
-   * @param[in]      fftSize      length of the FFT.
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
-   * @param[in]      *pBitRevTab  points to the bit reversal table.
-   * @return none.
-   */
-
-  void arm_bitreversal_f32(
-  float32_t * pSrc,
-  uint16_t fftSize,
-  uint16_t bitRevFactor,
-  uint16_t * pBitRevTab);
-
-  /**
-   * @brief  Core function for the Q31 CFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to Twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint32_t twidCoefModifier);
-
-  /**
-   * @brief  Core function for the f32 FFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of f32 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef        	  points to Twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix2_butterfly_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier);
-
-        /**  
-	 * @brief  Core function for the Radix-2 Q31 CFFT butterfly process. 
-	 * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type. 
-	 * @param[in]      fftLen           length of the FFT. 
-	 * @param[in]      *pCoef         	points to Twiddle coefficient buffer.
-	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
-	 * @return none. 
-	 */
-
-  void arm_radix2_butterfly_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint16_t twidCoefModifier);
-
-        /**  
-	 * @brief  Core function for the Radix-2 Q15 CFFT butterfly process. 
-	 * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type. 
-	 * @param[in]      fftLen           length of the FFT. 
-	 * @param[in]      *pCoef           points to Twiddle coefficient buffer.
-	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
-	 * @return none. 
-	 */
-
-  void arm_radix2_butterfly_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pCoef,
-  uint16_t twidCoefModifier);
-
-        /**  
-	 * @brief  Core function for the Radix-2 Q15 CFFT Inverse butterfly process. 
-	 * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type. 
-	 * @param[in]      fftLen           length of the FFT. 
-	 * @param[in]      *pCoef       	points to Twiddle coefficient buffer.
-	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
-	 * @return none. 
-	 */
-
-  void arm_radix2_butterfly_inverse_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pCoef,
-  uint16_t twidCoefModifier);
-
-        /**  
-	 * @brief  Core function for the Radix-2 Q31 CFFT Inverse butterfly process. 
-	 * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type. 
-	 * @param[in]      fftLen           length of the FFT. 
-	 * @param[in]      *pCoef         	points to Twiddle coefficient buffer.
-	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
-	 * @return none. 
-	 */
-
-  void arm_radix2_butterfly_inverse_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint16_t twidCoefModifier);
-
-  /**
-   * @brief  Core function for the f32 IFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of f32 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef        	  points to Twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @param[in]		 onebyfftLen	  1/fftLenfth
-   * @return none.
-   */
-
-  void arm_radix2_butterfly_inverse_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier,
-  float32_t onebyfftLen);
-
-                                                                /**
-   * @brief  Core function for the Q31 CIFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_inverse_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint32_t twidCoefModifier);
-
-  /**
-   * @brief  In-place bit reversal function.
-   * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.
-   * @param[in]      fftLen       length of the FFT.
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
-   * @param[in]      *pBitRevTab  points to bit reversal table.
-   * @return none.
-   */
-
-  void arm_bitreversal_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  uint16_t bitRevFactor,
-  uint16_t * pBitRevTab);
-
-  /**
-   * @brief  Core function for the Q15 CFFT butterfly process.
-   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_q15(
-  q15_t * pSrc16,
-  uint32_t fftLen,
-  q15_t * pCoef16,
-  uint32_t twidCoefModifier);
-
-
-  /**
-   * @brief  Core function for the Q15 CIFFT butterfly process.
-   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_inverse_q15(
-  q15_t * pSrc16,
-  uint32_t fftLen,
-  q15_t * pCoef16,
-  uint32_t twidCoefModifier);
-
-  /**
-   * @brief  In-place bit reversal function.
-   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.
-   * @param[in]      fftLen       length of the FFT.
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
-   * @param[in]      *pBitRevTab  points to bit reversal table.
-   * @return none.
-   */
-
-  void arm_bitreversal_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  uint16_t bitRevFactor,
-  uint16_t * pBitRevTab);
-
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  /**
-   * @brief Processing function for the Q15 RFFT/RIFFT.
-   * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.
-   * @param[in]  *pSrc points to the input buffer.
-   * @param[out] *pDst points to the output buffer.
-   * @return none.
-   */
-
-  void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst);
-
-  /**
-   * @brief  Initialization function for the Q15 RFFT/RIFFT.
-   * @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.
-   * @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in]      fftLenReal     length of the FFT.
-   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
-   */
-
-  arm_status arm_rfft_init_q15(
-  arm_rfft_instance_q15 * S,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the Q31 RFFT/RIFFT.
-   * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.
-   * @param[in]  *pSrc points to the input buffer.
-   * @param[out] *pDst points to the output buffer.
-   * @return none.
-   */
-
-  void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst);
-
-  /**
-   * @brief  Initialization function for the Q31 RFFT/RIFFT.
-   * @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.
-   * @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.
-   * @param[in]      fftLenReal     length of the FFT.
-   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
-   */
-
-  arm_status arm_rfft_init_q31(
-  arm_rfft_instance_q31 * S,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  /**
-   * @brief  Initialization function for the floating-point RFFT/RIFFT.
-   * @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.
-   * @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in]     fftLenReal     length of the FFT.
-   * @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
-   */
-
-  arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the floating-point RFFT/RIFFT.
-   * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.
-   * @param[in]  *pSrc points to the input buffer.
-   * @param[out] *pDst points to the output buffer.
-   * @return none.
-   */
-
-  void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    float32_t normalize;                /**< normalizing factor. */
-    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;              /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize);
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q31_t normalize;                    /**< normalizing factor. */
-    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize);
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q15_t normalize;                    /**< normalizing factor. */
-    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize);
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer);
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scale scale factor to be applied
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_f32(
-  float32_t * pSrc,
-  float32_t scale,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q7(
-  q7_t * pSrc,
-  q7_t scaleFract,
-  int8_t shift,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q15(
-  q15_t * pSrc,
-  q15_t scaleFract,
-  int8_t shift,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q31(
-  q31_t * pSrc,
-  q31_t scaleFract,
-  int8_t shift,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t blockSize,
-  float32_t * result);
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  uint32_t blockSize,
-  q31_t * result);
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q7(
-  q7_t * pSrc,
-  int8_t shiftBits,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q15(
-  q15_t * pSrc,
-  int8_t shiftBits,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q31(
-  q31_t * pSrc,
-  int8_t shiftBits,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_f32(
-  float32_t * pSrc,
-  float32_t offset,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q7(
-  q7_t * pSrc,
-  q7_t offset,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q15(
-  q15_t * pSrc,
-  q15_t offset,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q31(
-  q31_t * pSrc,
-  q31_t offset,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-  /**
-   * @brief  Copies the elements of a floating-point vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q7 vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q15 vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q31 vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-  /**
-   * @brief  Fills a constant value into a floating-point vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-/**  
- * @brief Convolution of floating-point sequences.  
- * @param[in] *pSrcA points to the first input sequence.  
- * @param[in] srcALen length of the first input sequence.  
- * @param[in] *pSrcB points to the second input sequence.  
- * @param[in] srcBLen length of the second input sequence.  
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
- * @return none.  
- */
-
-  void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-  
-  /**   
-   * @brief Convolution of Q15 sequences.   
-   * @param[in] *pSrcA points to the first input sequence.   
-   * @param[in] srcALen length of the first input sequence.   
-   * @param[in] *pSrcB points to the second input sequence.   
-   * @param[in] srcBLen length of the second input sequence.   
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.   
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
-   * @return none.   
-   */
-
-
-  void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**  
- * @brief Convolution of Q15 sequences.  
- * @param[in] *pSrcA points to the first input sequence.  
- * @param[in] srcALen length of the first input sequence.  
- * @param[in] *pSrcB points to the second input sequence.  
- * @param[in] srcBLen length of the second input sequence.  
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
- * @return none.  
- */
-
-  void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
-   * @return none.   
-   */
-
-  void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-    /**   
-   * @brief Convolution of Q7 sequences.   
-   * @param[in] *pSrcA points to the first input sequence.   
-   * @param[in] srcALen length of the first input sequence.   
-   * @param[in] *pSrcB points to the second input sequence.   
-   * @param[in] srcBLen length of the second input sequence.   
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.   
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
-   * @return none.   
-   */
-
-  void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-    /**   
-   * @brief Partial convolution of Q15 sequences.   
-   * @param[in]       *pSrcA points to the first input sequence.   
-   * @param[in]       srcALen length of the first input sequence.   
-   * @param[in]       *pSrcB points to the second input sequence.   
-   * @param[in]       srcBLen length of the second input sequence.   
-   * @param[out]      *pDst points to the block of output data   
-   * @param[in]       firstIndex is the first output sample to start with.   
-   * @param[in]       numPoints is the number of output points to be computed.   
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
-   */
-
-  arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q15(
-				        q15_t * pSrcA,
-				       uint32_t srcALen,
-				        q15_t * pSrcB,
-				       uint32_t srcBLen,
-				       q15_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
-   */
-
-  arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**   
-   * @brief Partial convolution of Q7 sequences   
-   * @param[in]       *pSrcA points to the first input sequence.   
-   * @param[in]       srcALen length of the first input sequence.   
-   * @param[in]       *pSrcB points to the second input sequence.   
-   * @param[in]       srcBLen length of the second input sequence.   
-   * @param[out]      *pDst points to the block of output data   
-   * @param[in]       firstIndex is the first output sample to start with.   
-   * @param[in]       numPoints is the number of output points to be computed.   
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
-   */
-
-  arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                      /**< decimation factor. */
-    uint16_t numTaps;               /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                          /**< decimation factor. */
-    uint16_t numTaps;                   /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_f32;
-
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift);
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages. 
-   * @param[in] *pState points to the state buffer.  The array is of length numStages. 
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] *pState points to the state buffer.   The array is of length numStages.
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
- * @param[in] *pState points to the state buffer.  The array is of length numStages.
- * @return none.
- */
-
-  void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
-  void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return    none.
-   */
-
-  void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-
-  } arm_lms_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] *S points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that control filter coefficient updates. */
-    float32_t energy;    /**< saves previous frame energy. */
-    float32_t x0;        /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;   /**< bit shift applied to coefficients. */
-    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
-    q15_t energy;        /**< saves previous frame energy. */
-    q15_t x0;            /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-   /**   
-   * @brief Correlation of Q15 sequences   
-   * @param[in] *pSrcA points to the first input sequence.   
-   * @param[in] srcALen length of the first input sequence.   
-   * @param[in] *pSrcB points to the second input sequence.   
-   * @param[in] srcBLen length of the second input sequence.   
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.   
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @return none.   
-   */
-  void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q15(
-			       q15_t * pSrcA,
-			      uint32_t srcALen,
-			       q15_t * pSrcB,
-			      uint32_t srcBLen,
-			      q15_t * pDst);
-
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @return none.
-   */
-
-  void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-
- /**   
-   * @brief Correlation of Q7 sequences.   
-   * @param[in] *pSrcA points to the first input sequence.   
-   * @param[in] srcALen length of the first input sequence.   
-   * @param[in] *pSrcB points to the second input sequence.   
-   * @param[in] srcBLen length of the second input sequence.   
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.   
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
-   * @return none.   
-   */
-
-  void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /*
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta    input value in degrees 
-   * @param[out] *pSinVal points to the processed sine output. 
-   * @param[out] *pCosVal points to the processed cos output. 
-   * @return none.
-   */
-
-  void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCcosVal);
-
-  /*
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees 
-   * @param[out] *pSinVal points to the processed sine output. 
-   * @param[out] *pCosVal points to the processed cosine output. 
-   * @return none.
-   */
-
-  void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control 
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   * 
-   * \par 
-   * \image html PID.gif "Proportional Integral Derivative Controller" 
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.  
-   * The proportional value determines the reaction to the current error, 
-   * the integral value determines the reaction based on the sum of recent errors, 
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure 
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. 
-   * A separate instance structure must be defined for each PID Controller. 
-   * There are separate instance structure declarations for each of the 3 supported data types. 
-   * 
-   * \par Reset Functions 
-   * There is also an associated reset function for each data type which clears the state array. 
-   *
-   * \par Initialization Functions 
-   * There is also an associated initialization function for each data type. 
-   * The initialization function performs the following operations: 
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.   
-   * 
-   * \par 
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
-   *
-   * \par Fixed-Point Behavior 
-   * Care must be taken when using the fixed-point versions of the PID Controller functions. 
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. 
-   * Refer to the function specific documentation below for usage guidelines. 
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   */
-
-
-  __STATIC_INLINE float32_t arm_pid_f32(
-  arm_pid_instance_f32 * S,
-  float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b> 
-   * \par 
-   * The function is implemented using an internal 64-bit accumulator. 
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. 
-   * Thus, if the accumulator result overflows it wraps around rather than clip. 
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. 
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
-   */
-
-  __STATIC_INLINE q31_t arm_pid_q31(
-  arm_pid_instance_q31 * S,
-  q31_t in)
-  {
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b> 
-   * \par 
-   * The function is implemented using a 64-bit internal accumulator. 
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. 
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. 
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. 
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. 
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-
-  __STATIC_INLINE q15_t arm_pid_q15(
-  arm_pid_instance_q15 * S,
-  q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-    /* Implementation of PID controller */
-
-#ifdef ARM_MATH_CM0
-
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-#else
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD(S->A0, in);
-
-#endif
-
-#ifdef ARM_MATH_CM0
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-
-#else
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc);
-
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  *src points to the instance of the input floating-point matrix structure.
-   * @param[out] *dst points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-
-  arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * src,
-  arm_matrix_instance_f32 * dst);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   */
-
-  __STATIC_INLINE void arm_clarke_f32(
-  float32_t Ia,
-  float32_t Ib,
-  float32_t * pIalpha,
-  float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta =
-      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-
-  }
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-  __STATIC_INLINE void arm_clarke_q31(
-  q31_t Ia,
-  q31_t Ib,
-  q31_t * pIalpha,
-  q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out]  *pDst    output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   * 
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   */
-
-
-  __STATIC_INLINE void arm_inv_clarke_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pIa,
-  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
-
-  }
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version 
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-
-  __STATIC_INLINE void arm_inv_clarke_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pIa,
-  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out] *pDst     output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents 
-   * from the stationary to the moving reference frame and control the spatial relationship between 
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the 
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,  
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the 
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output	rotor reference frame d
-   * @param[out]      *pIq   points to output	rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-
-  __STATIC_INLINE void arm_park_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pId,
-  float32_t * pIq,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-
-  }
-
-  /**
-   * @brief  Park transform for Q31 version 
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output rotor reference frame d
-   * @param[out]      *pIq   points to output rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-
-
-  __STATIC_INLINE void arm_park_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pId,
-  q31_t * pIq,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,  
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the 
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   */
-
-  __STATIC_INLINE void arm_inv_park_f32(
-  float32_t Id,
-  float32_t Iq,
-  float32_t * pIalpha,
-  float32_t * pIbeta,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for	Q31 version 
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-
-  __STATIC_INLINE void arm_inv_park_q31(
-  q31_t Id,
-  q31_t Iq,
-  q31_t * pIalpha,
-  q31_t * pIbeta,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par 
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   * 
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table 
-   * if x is below input range and returns last value of table if x is above range.  
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
-   * @param[in] x input sample to process
-   * @return y processed output sample.
-   *
-   */
-
-  __STATIC_INLINE float32_t arm_linear_interp_f32(
-  arm_linear_interp_instance_f32 * S,
-  float32_t x)
-  {
-
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t *pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (x - S->x1) / xSpacing;
-
-    if(i < 0)
-    {
-      /* Iniatilize output for below specified range as least output value of table */
-      y = pYData[0];
-    }
-    /* CHIBIOS FIX BEGIN */
-    else if(i >= (int32_t)S->nValues)
-    /* CHIBIOS FIX END */
-    {
-      /* Iniatilize output for above specified range as last output value of table */
-      y = pYData[S->nValues - 1];
-    }
-    else
-    {
-      /* Calculation of nearest input values */
-      x0 = S->x1 + i * xSpacing;
-      x1 = S->x1 + (i + 1) * xSpacing;
-
-      /* Read of nearest output values */
-      y0 = pYData[i];
-      y1 = pYData[i + 1];
-
-      /* Calculation of output */
-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-  }
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-
-
-  __STATIC_INLINE q31_t arm_linear_interp_q31(
-  q31_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20);
-    /* CHIBIOS FIX BEGIN */
-    if(index >= ((int32_t)nValues - 1))
-    /* CHIBIOS FIX END */
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if(index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-
-      /* 20 bits for the fractional part */
-      /* shift left by 11 to keep fract in 1.31 format */
-      fract = (x & 0x000FFFFF) << 11;
-
-      /* Read two nearest output values from the index in 1.31(q31) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-      /* Convert y to 1.31 format */
-      return (y << 1u);
-
-    }
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12. 
-   *
-   */
-
-
-  __STATIC_INLINE q15_t arm_linear_interp_q15(
-  q15_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20u);
-
-    /* CHIBIOS FIX BEGIN */
-    if(index >= ((int32_t)nValues - 1))
-    /* CHIBIOS FIX END */
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if(index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-      y = ((q63_t) y0 * (0xFFFFF - fract));
-
-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-      y += ((q63_t) y1 * (fract));
-
-      /* convert y to 1.15 format */
-      return (y >> 20);
-    }
-
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-
-
-  __STATIC_INLINE q7_t arm_linear_interp_q7(
-  q7_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20u);
-
-    /* CHIBIOS FIX BEGIN */
-    if(index >= ((int32_t)nValues - 1))
-    /* CHIBIOS FIX END */
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if(index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index and are in 1.7(q7) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-      y = ((y0 * (0xFFFFF - fract)));
-
-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-      y += (y1 * fract);
-
-      /* convert y to 1.7(q7) format */
-      return (y >> 20u);
-
-    }
-
-  }
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  sin(x).
-   */
-
-  float32_t arm_sin_f32(
-  float32_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q31_t arm_sin_q31(
-  q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q15_t arm_sin_q15(
-  q15_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  cos(x).
-   */
-
-  float32_t arm_cos_f32(
-  float32_t x);
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q31_t arm_cos_q31(
-  q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q15_t arm_cos_q15(
-  q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.  
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in     input value.
-   * @param[out] *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-
-  __STATIC_INLINE arm_status arm_sqrt_f32(
-  float32_t in,
-  float32_t * pOut)
-  {
-    if(in > 0)
-    {
-
-//    #if __FPU_USED
-    #if (__FPU_USED == 1) && defined ( __CC_ARM   )
-        *pOut = __sqrtf(in);
-    #elif (__FPU_USED == 1) && defined ( __TMS_740 )
-        *pOut = __builtin_sqrtf(in);
-    #else
-        *pOut = sqrtf(in);
-    #endif
-
-      return (ARM_MATH_SUCCESS);
-    }
-    else
-    {
-      *pOut = 0.0f;
-      return (ARM_MATH_ARGUMENT_ERROR);
-    }
-
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out]  *pOut square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut);
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out]  *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-
-
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-
-  __STATIC_INLINE void arm_circularWrite_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const int32_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  __STATIC_INLINE void arm_circularRead_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  int32_t * dst,
-  int32_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (int32_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value  */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-
-  __STATIC_INLINE void arm_circularWrite_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q15_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  __STATIC_INLINE void arm_circularRead_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q15_t * dst,
-  q15_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (q15_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-
-  __STATIC_INLINE void arm_circularWrite_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q7_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  __STATIC_INLINE void arm_circularRead_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q7_t * dst,
-  q7_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (q7_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult);
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult);
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult);
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *result is output pointer
-   * @param[in]  index is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * result,
-  uint32_t * index);
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-  void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
-   * @param[out]      *pDst points to the Q31 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return none. 
-   */
-  void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
-   * @param[out]      *pDst points to the Q15 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return          none
-   */
-  void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
-   * @param[out]      *pDst points to the Q7 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return          none
-   */
-  void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.  
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate.
-  * @param[in] Y interpolation coordinate.
-  * @return out interpolated value.
-  */
-
-
-  __STATIC_INLINE float32_t arm_bilinear_interp_f32(
-  const arm_bilinear_interp_instance_f32 * S,
-  float32_t X,
-  float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
-       || yIndex > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  __STATIC_INLINE q31_t arm_bilinear_interp_q31(
-  arm_bilinear_interp_instance_q31 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20u);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20u);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return (acc << 2u);
-
-  }
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  __STATIC_INLINE q15_t arm_bilinear_interp_q15(
-  arm_bilinear_interp_instance_q15 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return (acc >> 36);
-
-  }
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  __STATIC_INLINE q7_t arm_bilinear_interp_q7(
-  arm_bilinear_interp_instance_q7 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return (acc >> 40);
-
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-
-
-
-
-
-
-#ifdef	__cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-
-/**
- *
- * End of file.
- */
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h
deleted file mode 100644
index 0d7cfd85e..000000000
--- a/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h
+++ /dev/null
@@ -1,667 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V3.01
- * @date     13. March 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM0_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h
deleted file mode 100644
index cf92fb7fe..000000000
--- a/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h
+++ /dev/null
@@ -1,778 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V3.01
- * @date     22. March 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x01)                                /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-#if (__VTOR_PRESENT == 1)
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-#else
-       uint32_t RESERVED0;
-#endif
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0+ system interrupts */
-  else {
-    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts   */
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h
deleted file mode 100644
index db1716ad9..000000000
--- a/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h
+++ /dev/null
@@ -1,1612 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V3.01
- * @date     22. March 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM3_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h
deleted file mode 100644
index 024302e4a..000000000
--- a/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h
+++ /dev/null
@@ -1,1757 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V3.01
- * @date     22. March 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM4_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
-  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h
deleted file mode 100644
index b5140073f..000000000
--- a/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h
+++ /dev/null
@@ -1,649 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4_simd.h
- * @brief    CMSIS Cortex-M4 SIMD Header File
- * @version  V3.01
- * @date     06. March 2012
- *
- * @note
- * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_iar.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_ccs.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h b/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h
deleted file mode 100644
index 585d2bb56..000000000
--- a/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h
+++ /dev/null
@@ -1,620 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V3.01
- * @date     06. March 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-/* CHIBIOS FIX BEGIN */
-#else
-  (void)fpscr;
-/* CHIBIOS FIX END */
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h b/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h
deleted file mode 100644
index 624c175fd..000000000
--- a/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h
+++ /dev/null
@@ -1,618 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V3.01
- * @date     06. March 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-
-  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
-  return(op1);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint8_t result;
-
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint16_t result;
-
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint8_t result;
-
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
diff --git a/os/ports/common/ARMCMx/CMSIS/readme.txt b/os/ports/common/ARMCMx/CMSIS/readme.txt
deleted file mode 100644
index 6e2172455..000000000
--- a/os/ports/common/ARMCMx/CMSIS/readme.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-CMSIS is Copyright (C) 2011 ARM Limited. All rights reserved.  
-
-This directory contains only part of the CMSIS package. If you need the whole
-package please download it from:
-
-http://www.onarm.com
diff --git a/os/ports/common/ARMCMx/nvic.c b/os/ports/common/ARMCMx/nvic.c
deleted file mode 100644
index 3cf80fbfc..000000000
--- a/os/ports/common/ARMCMx/nvic.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    common/ARMCMx/nvic.c
- * @brief   Cortex-Mx NVIC support code.
- *
- * @addtogroup COMMON_ARMCMx_NVIC
- * @{
- */
-
-#include "ch.h"
-#include "nvic.h"
-
-/**
- * @brief   Sets the priority of an interrupt handler and enables it.
- * @note    The parameters are not tested for correctness.
- *
- * @param[in] n         the interrupt number
- * @param[in] prio      the interrupt priority mask
- */
-void nvicEnableVector(uint32_t n, uint32_t prio) {
-  unsigned sh = (n & 3) << 3;
-
-  NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
-  NVIC_ICPR(n >> 5) = 1 << (n & 0x1F);
-  NVIC_ISER(n >> 5) = 1 << (n & 0x1F);
-}
-
-/**
- * @brief   Disables an interrupt handler.
- * @note    The parameters are not tested for correctness.
- *
- * @param[in] n         the interrupt number
- */
-void nvicDisableVector(uint32_t n) {
-  unsigned sh = (n & 3) << 3;
-
-  NVIC_ICER(n >> 5) = 1 << (n & 0x1F);
-  NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh);
-}
-
-/**
- * @brief   Changes the priority of a system handler.
- * @note    The parameters are not tested for correctness.
- *
- * @param[in] handler   the system handler number
- * @param[in] prio      the system handler priority mask
- */
-void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
-  unsigned sh = (handler & 3) * 8;
-
-  SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) &
-                           ~(0xFF << sh)) | (prio << sh);
-}
-
-/** @} */
diff --git a/os/ports/common/ARMCMx/nvic.h b/os/ports/common/ARMCMx/nvic.h
deleted file mode 100644
index 5ebff94cd..000000000
--- a/os/ports/common/ARMCMx/nvic.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    common/ARMCMx/nvic.h
- * @brief   Cortex-Mx NVIC support macros and structures.
- *
- * @addtogroup COMMON_ARMCMx_NVIC
- * @{
- */
-
-#ifndef _NVIC_H_
-#define _NVIC_H_
-
-/**
- * @name System vector numbers
- * @{
- */
-#define HANDLER_MEM_MANAGE      0       /**< MEM MANAGE vector id.          */
-#define HANDLER_BUS_FAULT       1       /**< BUS FAULT vector id.           */
-#define HANDLER_USAGE_FAULT     2       /**< USAGE FAULT vector id.         */
-#define HANDLER_RESERVED_3      3
-#define HANDLER_RESERVED_4      4
-#define HANDLER_RESERVED_5      5
-#define HANDLER_RESERVED_6      6
-#define HANDLER_SVCALL          7       /**< SVCALL vector id.              */
-#define HANDLER_DEBUG_MONITOR   8       /**< DEBUG MONITOR vector id.       */
-#define HANDLER_RESERVED_9      9
-#define HANDLER_PENDSV          10      /**< PENDSV vector id.              */
-#define HANDLER_SYSTICK         11      /**< SYS TCK vector id.             */
-/** @} */
-
-typedef volatile uint8_t IOREG8;        /**< 8 bits I/O register type.      */
-typedef volatile uint32_t IOREG32;      /**< 32 bits I/O register type.     */
-
-/**
- * @brief NVIC ITCR register.
- */
-#define NVIC_ITCR               (*((IOREG32 *)0xE000E004U))
-
-/**
- * @brief Structure representing the SYSTICK I/O space.
- */
-typedef struct {
-  IOREG32       CSR;
-  IOREG32       RVR;
-  IOREG32       CVR;
-  IOREG32       CBVR;
-} CMx_ST;
-
-/**
- * @brief SYSTICK peripheral base address.
- */
-#define STBase                  ((CMx_ST *)0xE000E010U)
-#define ST_CSR                  (STBase->CSR)
-#define ST_RVR                  (STBase->RVR)
-#define ST_CVR                  (STBase->CVR)
-#define ST_CBVR                 (STBase->CBVR)
-
-#define CSR_ENABLE_MASK         (0x1U << 0)
-#define ENABLE_OFF_BITS         (0U << 0)
-#define ENABLE_ON_BITS          (1U << 0)
-#define CSR_TICKINT_MASK        (0x1U << 1)
-#define   TICKINT_DISABLED_BITS (0U << 1)
-#define   TICKINT_ENABLED_BITS  (1U << 1)
-#define CSR_CLKSOURCE_MASK      (0x1U << 2)
-#define   CLKSOURCE_EXT_BITS    (0U << 2)
-#define   CLKSOURCE_CORE_BITS   (1U << 2)
-#define CSR_COUNTFLAG_MASK      (0x1U << 16)
-
-#define RVR_RELOAD_MASK         (0xFFFFFFU << 0)
-
-#define CVR_CURRENT_MASK        (0xFFFFFFU << 0)
-
-#define CBVR_TENMS_MASK         (0xFFFFFFU << 0)
-#define CBVR_SKEW_MASK          (0x1U << 30)
-#define CBVR_NOREF_MASK         (0x1U << 31)
-
-/**
- * @brief Structure representing the NVIC I/O space.
- */
-typedef struct {
-  IOREG32       ISER[8];
-  IOREG32       unused1[24];
-  IOREG32       ICER[8];
-  IOREG32       unused2[24];
-  IOREG32       ISPR[8];
-  IOREG32       unused3[24];
-  IOREG32       ICPR[8];
-  IOREG32       unused4[24];
-  IOREG32       IABR[8];
-  IOREG32       unused5[56];
-  IOREG32       IPR[60];
-  IOREG32       unused6[644];
-  IOREG32       STIR;
-} CMx_NVIC;
-
-/**
- * @brief NVIC peripheral base address.
- */
-#define NVICBase                ((CMx_NVIC *)0xE000E100U)
-#define NVIC_ISER(n)            (NVICBase->ISER[n])
-#define NVIC_ICER(n)            (NVICBase->ICER[n])
-#define NVIC_ISPR(n)            (NVICBase->ISPR[n])
-#define NVIC_ICPR(n)            (NVICBase->ICPR[n])
-#define NVIC_IABR(n)            (NVICBase->IABR[n])
-#define NVIC_IPR(n)             (NVICBase->IPR[n])
-#define NVIC_STIR               (NVICBase->STIR)
-
-/**
- * @brief Structure representing the System Control Block I/O space.
- */
-typedef struct {
-  IOREG32       CPUID;
-  IOREG32       ICSR;
-  IOREG32       VTOR;
-  IOREG32       AIRCR;
-  IOREG32       SCR;
-  IOREG32       CCR;
-  IOREG32       SHPR[3];
-  IOREG32       SHCSR;
-  IOREG32       CFSR;
-  IOREG32       HFSR;
-  IOREG32       DFSR;
-  IOREG32       MMFAR;
-  IOREG32       BFAR;
-  IOREG32       AFSR;
-  IOREG32       PFR[2];
-  IOREG32       DFR;
-  IOREG32       ADR;
-  IOREG32       MMFR[4];
-  IOREG32       SAR[5];
-  IOREG32       unused1[5];
-  IOREG32       CPACR;
-} CMx_SCB;
-
-/**
- * @brief SCB peripheral base address.
- */
-#define SCBBase                 ((CMx_SCB *)0xE000ED00U)
-#define SCB_CPUID               (SCBBase->CPUID)
-#define SCB_ICSR                (SCBBase->ICSR)
-#define SCB_VTOR                (SCBBase->VTOR)
-#define SCB_AIRCR               (SCBBase->AIRCR)
-#define SCB_SCR                 (SCBBase->SCR)
-#define SCB_CCR                 (SCBBase->CCR)
-#define SCB_SHPR(n)             (SCBBase->SHPR[n])
-#define SCB_SHCSR               (SCBBase->SHCSR)
-#define SCB_CFSR                (SCBBase->CFSR)
-#define SCB_HFSR                (SCBBase->HFSR)
-#define SCB_DFSR                (SCBBase->DFSR)
-#define SCB_MMFAR               (SCBBase->MMFAR)
-#define SCB_BFAR                (SCBBase->BFAR)
-#define SCB_AFSR                (SCBBase->AFSR)
-#define SCB_PFR(n)              (SCBBase->PFR[n])
-#define SCB_DFR                 (SCBBase->DFR)
-#define SCB_ADR                 (SCBBase->ADR)
-#define SCB_MMFR(n)             (SCBBase->MMFR[n])
-#define SCB_SAR(n)              (SCBBase->SAR[n])
-#define SCB_CPACR               (SCBBase->CPACR)
-
-#define ICSR_VECTACTIVE_MASK    (0x1FFU << 0)
-#define ICSR_RETTOBASE          (0x1U << 11)
-#define ICSR_VECTPENDING_MASK   (0x1FFU << 12)
-#define ICSR_ISRPENDING         (0x1U << 22)
-#define ICSR_ISRPREEMPT         (0x1U << 23)
-#define ICSR_PENDSTCLR          (0x1U << 25)
-#define ICSR_PENDSTSET          (0x1U << 26)
-#define ICSR_PENDSVCLR          (0x1U << 27)
-#define ICSR_PENDSVSET          (0x1U << 28)
-#define ICSR_NMIPENDSET         (0x1U << 31)
-
-#define AIRCR_VECTKEY           0x05FA0000U
-#define AIRCR_PRIGROUP_MASK     (0x7U << 8)
-#define AIRCR_PRIGROUP(n)       ((n) << 8)
-
-/**
- * @brief Structure representing the FPU I/O space.
- */
-typedef struct {
-  IOREG32       unused1[1];
-  IOREG32       FPCCR;
-  IOREG32       FPCAR;
-  IOREG32       FPDSCR;
-  IOREG32       MVFR0;
-  IOREG32       MVFR1;
-} CMx_FPU;
-
-/**
- * @brief FPU peripheral base address.
- */
-#define FPUBase                 ((CMx_FPU *)0xE000EF30U)
-#define SCB_FPCCR               (FPUBase->FPCCR)
-#define SCB_FPCAR               (FPUBase->FPCAR)
-#define SCB_FPDSCR              (FPUBase->FPDSCR)
-#define SCB_MVFR0               (FPUBase->MVFR0)
-#define SCB_MVFR1               (FPUBase->MVFR1)
-
-#define FPCCR_ASPEN             (0x1U << 31)
-#define FPCCR_LSPEN             (0x1U << 30)
-#define FPCCR_MONRDY            (0x1U << 8)
-#define FPCCR_BFRDY             (0x1U << 6)
-#define FPCCR_MMRDY             (0x1U << 5)
-#define FPCCR_HFRDY             (0x1U << 4)
-#define FPCCR_THREAD            (0x1U << 3)
-#define FPCCR_USER              (0x1U << 1)
-#define FPCCR_LSPACT            (0x1U << 0)
-
-#define FPDSCR_AHP              (0x1U << 26)
-#define FPDSCR_DN               (0x1U << 25)
-#define FPDSCR_FZ               (0x1U << 24)
-#define FPDSCR_RMODE(n)         ((n##U) << 22)
-
-/**
- * @brief Structure representing the SCS I/O space.
- */
-typedef struct {
-  IOREG32       DHCSR;
-  IOREG32       DCRSR;
-  IOREG32       DCRDR;
-  IOREG32       DEMCR;
-} CMx_SCS;
-
-/**
- * @brief SCS peripheral base address.
- */
-#define SCSBase                 ((CMx_SCS *)0xE000EDF0U)
-#define SCS_DHCSR               (SCSBase->DHCSR)
-#define SCS_DCRSR               (SCSBase->DCRSR)
-#define SCS_DCRDR               (SCSBase->DCRDR)
-#define SCS_DEMCR               (SCSBase->DEMCR)
-
-#define SCS_DEMCR_TRCENA        (0x1U << 24)
-
-/**
- * @brief Structure representing the DWT I/O space.
- */
-typedef struct {
-  IOREG32       CTRL;
-  IOREG32       CYCCNT;
-  IOREG32       CPICNT;
-  IOREG32       EXCCNT;
-  IOREG32       SLEEPCNT;
-  IOREG32       LSUCNT;
-  IOREG32       FOLDCNT;
-  IOREG32       PCSR;
-} CMx_DWT;
-
-/**
- * @brief DWT peripheral base address.
- */
-#define DWTBase                 ((CMx_DWT *)0xE0001000U)
-#define DWT_CTRL                (DWTBase->CTRL)
-#define DWT_CYCCNT              (DWTBase->CYCCNT)
-#define DWT_CPICNT              (DWTBase->CPICNT)
-#define DWT_EXCCNT              (DWTBase->EXCCNT)
-#define DWT_SLEEPCNT            (DWTBase->SLEEPCNT)
-#define DWT_LSUCNT              (DWTBase->LSUCNT)
-#define DWT_FOLDCNT             (DWTBase->FOLDCNT)
-#define DWT_PCSR                (DWTBase->PCSR)
-
-#define DWT_CTRL_CYCCNTENA      (0x1U << 0)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void nvicEnableVector(uint32_t n, uint32_t prio);
-  void nvicDisableVector(uint32_t n);
-  void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NVIC_H_ */
-
-/** @} */
diff --git a/os/ports/common/ARMCMx/port.dox b/os/ports/common/ARMCMx/port.dox
deleted file mode 100644
index abb6a42e7..000000000
--- a/os/ports/common/ARMCMx/port.dox
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup COMMON_ARMCMx ARM Cortex-Mx Common Code
- * @ingroup port_common
- */
- 
-/**
- * @defgroup COMMON_ARMCMx_NVIC NVIC Support
- * @details ARM Cortex-Mx NVIC support.
- *
- * @ingroup COMMON_ARMCMx
- */
-
- /** @} */
- 
diff --git a/os/ports/cosmic/STM8/chcore.c b/os/ports/cosmic/STM8/chcore.c
deleted file mode 100644
index 69fce38de..000000000
--- a/os/ports/cosmic/STM8/chcore.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    cosmic/STM8/chcore.c
- * @brief   STM8 (Cosmic) architecture port code.
- *
- * @addtogroup STM8_COSMIC_CORE
- * @{
- */
-
-#include "ch.h"
-
-@tiny ReadyList rlist;
-
-/**
- * @brief   Performs a context switch between two threads.
- *
- * @param otp   the thread to be switched out
- */
-void _port_switch(Thread *otp) {
-
-  _asm("        xref    _rlist          \n"
-       "        ldw     y,sp            \n"
-       "        ldw     (5,x),y         \n"
-       "        ldw     x,_rlist+5      \n"
-       "        ldw     x,(5,x)         \n"
-       "        ldw     sp,x            \n", otp);
-}
-
-/**
- * @brief   Thread start code.
- */
-void _port_thread_start(void) {
-
-  chSysUnlock();
-  _asm("        popw    x               \n");
-}
-
-/**
- * @brief   Halts the system.
- * @details This function is invoked by the operating system when an
- *          unrecoverable error is detected (for example because a programming
- *          error in the application code that triggers an assertion while in
- *          debug mode).
- */
-void port_halt(void) {
-
-  port_disable();
-  while (TRUE) {
-  }
-}
-
-/** @} */
diff --git a/os/ports/cosmic/STM8/chcore.h b/os/ports/cosmic/STM8/chcore.h
deleted file mode 100644
index 2cb5ddeeb..000000000
--- a/os/ports/cosmic/STM8/chcore.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    cosmic/STM8/chcore.h
- * @brief   STM8 (Cosmic) architecture port macros and structures.
- *
- * @addtogroup STM8_COSMIC_CORE
- * @{
- */
-
-#ifndef _CHCORE_H_
-#define _CHCORE_H_
-
-#if CH_DBG_ENABLE_STACK_CHECK
-#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port"
-#endif
-
-/*===========================================================================*/
-/* Port configurable parameters.                                             */
-/*===========================================================================*/
-
-/**
- * @brief   Enables the use of the WFI instruction in the idle thread loop.
- */
-#ifndef STM8_ENABLE_WFI_IDLE
-#define STM8_ENABLE_WFI_IDLE            FALSE
-#endif
-
-/*===========================================================================*/
-/* Port exported info.                                                       */
-/*===========================================================================*/
-
-/**
- * @brief   Unique macro for the implemented architecture.
- */
-#define CH_ARCHITECTURE_STM8
-
-/**
- * @brief   Name of the implemented architecture.
- */
-#define CH_ARCHITECTURE_NAME            "STM8"
-
-/**
- * @brief   Name of the compiler supported by this port.
- */
-#define CH_COMPILER_NAME                "Cosmic"
-
-/**
- * @brief   Port-specific information string.
- */
-#define CH_PORT_INFO                    "None"
-
-/*===========================================================================*/
-/* Port implementation part.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Base type for stack alignment.
- * @note    No alignment constraints so uint8_t.
- */
-typedef uint8_t stkalign_t;
-
-/**
- * @brief   Generic STM8 function pointer.
- * @note    It is used to allocate the proper size for return addresses in
- *          context-related structures.
- */
-typedef void (*stm8func_t)(void);
-
-/**
- * @brief   Interrupt saved context.
- * @details This structure represents the stack frame saved during a
- *          preemption-capable interrupt handler.
- * @note    The structure requires one dummy field at its start because the
- *          stack is handled as preincremented/postdecremented.
- */
-struct extctx {
-  uint8_t       _next;
-  uint8_t       c_lreg[4];
-  uint8_t       c_y[3];
-  uint8_t       c_x[3];
-  uint8_t       cc;
-  uint8_t       a;
-  uint16_t      x;
-  uint16_t      y;
-  uint8_t       pce;
-  uint8_t       pch;
-  uint8_t       pcl;
-};
-
-/**
- * @brief   System saved context.
- * @details This structure represents the inner stack frame during a context
- *          switching..
- * @note    The structure requires one dummy field at its start because the
- *          stack is handled as preincremented/postdecremented.
- */
-struct intctx {
-  uint8_t       _next;
-  stm8func_t    pc;             /* Function pointer sized return address.   */
-};
-
-/**
- * @brief   Platform dependent part of the @p Thread structure.
- * @details This structure usually contains just the saved stack pointer
- *          defined as a pointer to a @p intctx structure.
- */
-struct context {
-  struct intctx *sp;
-};
-
-/**
- * @brief   Start context.
- * @details This context is the stack organization for the trampoline code
- *          @p _port_thread_start().
- */
-struct stm8_startctx {
-  uint8_t       _next;
-  stm8func_t    ts;             /* Trampoline address.                      */
-  void          *arg;           /* Thread argument.                         */
-  stm8func_t    pc;             /* Thread function address.                 */
-  stm8func_t    ret;            /* chThdExit() address.                     */
-};
-
-/**
- * @brief   Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- *          by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
-  struct stm8_startctx *scp;                                                \
-  scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize -             \
-                                 sizeof(struct stm8_startctx));             \
-  scp->ts   = _port_thread_start;                                           \
-  scp->arg  = arg;                                                          \
-  scp->pc   = (stm8func_t)pf;                                               \
-  scp->ret  = (stm8func_t)chThdExit;                                        \
-  tp->p_ctx.sp = (struct intctx *)scp;                                      \
-}
-
-/**
- * @brief   Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- *          the idle thread should take no more space than those reserved
- *          by @p PORT_INT_REQUIRED_STACK.
- */
-#ifndef PORT_IDLE_THREAD_STACK_SIZE
-#define PORT_IDLE_THREAD_STACK_SIZE     0
-#endif
-
-/**
- * @brief   Per-thread stack overhead for interrupts servicing.
- * @details This is a safe value, you may trim it down after reading the
- *          right size in the map file.
- */
-#ifndef PORT_INT_REQUIRED_STACK
-#define PORT_INT_REQUIRED_STACK         48
-#endif
-
-/**
- * @brief   Enforces a correct alignment for a stack area size value.
- */
-#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
-
-/**
- * @brief   Computes the thread working area global size.
- */
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
-                                   (sizeof(struct intctx) - 1) +            \
-                                   (sizeof(struct extctx) - 1) +            \
-                                   (n) + (PORT_INT_REQUIRED_STACK))
-
-/**
- * @brief   Static working area allocation.
- * @details This macro is used to allocate a static thread working area
- *          aligned as both position and size.
- */
-#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-
-/**
- * @brief   IRQ prologue code.
- * @details This macro must be inserted at the start of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_PROLOGUE()
-
-/**
- * @brief   IRQ epilogue code.
- * @details This macro must be inserted at the end of all IRQ handlers
- *          enabled to invoke system APIs.
- */
-#define PORT_IRQ_EPILOGUE() {                                               \
-  dbg_check_lock();                                                         \
-  if (chSchIsPreemptionRequired())                                          \
-    chSchDoReschedule();                                                    \
-  dbg_check_unlock();                                                       \
-}
-
-/**
- * @brief   IRQ handler function declaration.
- * @note    @p id can be a function name or a vector number depending on the
- *          port implementation.
- */
-#define PORT_IRQ_HANDLER(id) @far @interrupt @svlreg void vector##id(void)
-
-/**
- * @brief   Port-related initialization code.
- * @note    None in this port.
- */
-#define port_init()
-
-/**
- * @brief   Kernel-lock action.
- * @note    Implemented as global interrupts disable.
- */
-#define port_lock() _asm("sim")
-
-/**
- * @brief   Kernel-unlock action.
- * @note    Implemented as global interrupts enable.
- */
-#define port_unlock() _asm("rim")
-
-/**
- * @brief   Kernel-lock action from an interrupt handler.
- * @note    This function is empty in this port.
- */
-#define port_lock_from_isr()
-
-/**
- * @brief   Kernel-unlock action from an interrupt handler.
- * @note    This function is empty in this port.
- */
-#define port_unlock_from_isr()
-
-/**
- * @brief   Disables all the interrupt sources.
- * @note    Implemented as global interrupts disable.
- * @note    Of course non-maskable interrupt sources are not included.
- */
-#define port_disable() _asm("sim")
-
-/**
- * @brief   Disables the interrupt sources that are not supposed to preempt
- *          the kernel.
- * @note    Same as @p port_disable() in this port, there is no difference
- *          between the two states.
- */
-#define port_suspend() _asm("sim")
-
-/**
- * @brief   Enables all the interrupt sources.
- * @note    Implemented as global interrupt enable.
- */
-#define port_enable() _asm("rim")
-
-/**
- * @brief   Enters an architecture-dependent halt mode.
- * @note    Implemented with the specific "wfi" instruction.
- */
-#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() _asm("wfi")
-#else
-#define port_wait_for_interrupt()
-#endif
-
-/**
- * @brief   Performs a context switch between two threads.
- * @details This is the most critical code in any port, this function
- *          is responsible for the context switch between 2 threads.
- * @note    Implemented as a call to a low level assembler routine.
- *
- * @param ntp   the thread to be switched in
- * @param otp   the thread to be switched out
- */
-#define port_switch(ntp, otp) _port_switch(otp)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void _port_switch(Thread *otp);
-  void _port_thread_start(void);
-  void port_halt(void);
-#ifdef __cplusplus
-}
-#endif
-
-/*===========================================================================*/
-/* Scheduler captured code.                                                  */
-/*===========================================================================*/
-
-#define PORT_OPTIMIZED_RLIST_VAR
-#define PORT_OPTIMIZED_RLIST_EXT
-#define PORT_OPTIMIZED_READYLIST_STRUCT
-
-typedef struct {
-  ThreadsQueue          r_queue;
-  tprio_t               r_prio;
-  Thread                *r_current;
-#if CH_USE_REGISTRY
-  Thread                *r_newer;
-  Thread                *r_older;
-#endif
-  /* End of the fields shared with the Thread structure.*/
-#if CH_TIME_QUANTUM > 0
-  cnt_t                 r_preempt;
-#endif
-} ReadyList;
-
-@tiny extern ReadyList rlist;
-
-#endif /* _CHCORE_H_ */
-
-/** @} */
diff --git a/os/ports/cosmic/STM8/chtypes.h b/os/ports/cosmic/STM8/chtypes.h
deleted file mode 100644
index efd25964e..000000000
--- a/os/ports/cosmic/STM8/chtypes.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    cosmic/STM8/chtypes.h
- * @brief   STM8 (Cosmic) port system types.
- *
- * @addtogroup STM8_COSMIC_CORE
- * @{
- */
-
-#ifndef _CHTYPES_H_
-#define _CHTYPES_H_
-
-#include <stddef.h>
-
-typedef unsigned char   uint8t;         /**< C99-style boolean.             */
-typedef unsigned char   uint8_t;        /**< C99-style 8 bits unsigned.     */
-typedef signed char     int8_t;         /**< C99-style 8 bits signed.       */
-typedef unsigned int    uint16_t;       /**< C99-style 16 bits unsigned.    */
-typedef signed int      int16_t;        /**< C99-style 16 bits signed.      */
-typedef unsigned long   uint32_t;       /**< C99-style 32 bits unsigned.    */
-typedef signed long     int32_t;        /**< C99-style 32 bits signed.      */
-typedef uint8_t         uint_fast8_t;   /**< C99-style 8 bits unsigned.     */
-typedef uint16_t        uint_fast16_t;  /**< C99-style 16 bits unsigned.    */
-typedef uint32_t        uint_fast32_t;  /**< C99-style 32 bits unsigned.    */
-
-#if !defined(false) || defined(__DOXYGEN__)
-#define false           0
-#endif
-
-#if !defined(true) || defined(__DOXYGEN__)
-#define true            (!false)
-#endif
-
-typedef bool            bool_t;         /**< Fast boolean type.             */
-typedef uint8_t         tmode_t;        /**< Thread flags.                  */
-typedef uint8_t         tstate_t;       /**< Thread state.                  */
-typedef uint8_t         trefs_t;        /**< Thread references counter.     */
-typedef uint8_t         tslices_t;      /**< Thread time slices counter.    */
-typedef uint8_t         tprio_t;        /**< Thread priority.               */
-typedef int16_t         msg_t;          /**< Inter-thread message.          */
-typedef int8_t          eventid_t;      /**< Event Id.                      */
-typedef uint8_t         eventmask_t;    /**< Event mask.                    */
-typedef uint8_t         flagsmask_t;    /**< Event flags.                   */
-typedef uint16_t        systime_t;      /**< System time.                   */
-typedef int8_t          cnt_t;          /**< Resources counter.             */
-
-/**
- * @brief   Inline function modifier.
- */
-#define INLINE @inline
-
-/**
- * @brief   ROM constant modifier.
- * @note    Uses the "const" keyword in this port.
- */
-#define ROMCONST const
-
-/**
- * @brief   Packed structure modifier (within).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_STRUCT
-
-/**
- * @brief   Packed structure modifier (before).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_BEGIN
-
-/**
- * @brief   Packed structure modifier (after).
- * @note    Empty in this port.
- */
-#define PACK_STRUCT_END
-
-#endif /* _CHTYPES_H_ */
-
-/** @} */
diff --git a/os/ports/cosmic/STM8/port.dox b/os/ports/cosmic/STM8/port.dox
deleted file mode 100644
index f19f26cb2..000000000
--- a/os/ports/cosmic/STM8/port.dox
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup STM8_COSMIC STM8
- * @details STM8 port for the Cosmic C compiler.
- *
- * @section STM8_COSMIC_INTRO Introduction
- * This port supports all STM8 8 bits MCUs.
- *
- * @section STM8_COSMIC_STATES Mapping of the System States in the STM8 port
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8
- * port:
- * - <b>Init</b>. This state is represented by the startup code and the
- *   initialization code before @p chSysInit() is executed. It has not a
- *   special hardware state associated.
- * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). Interrupts are enabled.
- * - <b>Suspended</b>. Interrupts are disabled.
- * - <b>Disabled</b>. Interrupts are disabled. This state is equivalent to the
- *   Suspended state because there are no fast interrupts in this architecture.
- * - <b>Sleep</b>. Implemented with "wait" instruction insertion in the idle
- *   loop.
- * - <b>S-Locked</b>. Interrupts are disabled.
- * - <b>I-Locked</b>. This state is equivalent to the SRI state, the
- *   @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
- *   order to formally change state because this may change).
- * - <b>Serving Regular Interrupt</b>. Normal interrupt service code.
- * - <b>Serving Fast Interrupt</b>. Not present in this architecture.
- * - <b>Serving Non-Maskable Interrupt</b>. The STM8 ha non
- *   maskable interrupt sources that can be associated to this state.
- * - <b>Halted</b>. Implemented as an infinite loop with interrupts disabled.
- * .
- * @section STM8_COSMIC_NOTES The STM8 port notes
- * - The STM8 does not have a dedicated interrupt stack, make sure to reserve
- *     enough stack space for interrupts in each thread stack. This can be done
- *     by modifying the @p INT_REQUIRED_STACK macro into
- *     <b>./os/ports/cosmic/STM8/chcore.h</b>.
- * - The kernel currently supports only the small memory model so the
- *   kernel files should be loaded in the first 64K. Note that this is not
- *   a problem because upper addresses can be used by the user code, the
- *   kernel can context switch code running there.
- * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported
- *   because the missing support of the @p inline "C" keyword in the
- *   compiler.
- * .
- * @ingroup cosmic
- */
-
-/**
- * @defgroup STM8_COSMIC_CONF Configuration Options
- * @details STM8 Configuration Options. The STM8 port allows some
- * architecture-specific configurations settings that can be overridden
- * by redefining them in @p chconf.h. Usually there is no need to change
- * the default values.
- * - @p INT_REQUIRED_STACK, this value represent the amount of stack space
- *   used by the interrupt handlers.<br>
- *   The default for this value is @p 48, this space is allocated for each
- *   thread so be careful in order to not waste precious RAM space.
- * .
- * @ingroup STM8_COSMIC
- */
-
-/**
- * @defgroup STM8_COSMIC_CORE Core Port Implementation
- * @details STM8 specific port code, structures and macros.
- *
- * @ingroup STM8_COSMIC
- */
-
- /**
- * @defgroup STM8_COSMIC_STARTUP Startup Support
- * @details ChibiOS/RT doed not provide startup files for the STM8, there
- * are no special startup requirement so the normal toolchain-provided
- * startup files can be used.
- *
- * @ingroup STM8_COSMIC
- */
diff --git a/os/ports/ports.dox b/os/ports/ports.dox
deleted file mode 100644
index e2f834441..000000000
--- a/os/ports/ports.dox
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup ports Ports
- * This section describes the technical details of the various supported
- * ChibiOS/RT ports.
- */
-
-/**
- * @defgroup port_common Common Code
- * Code common to all compilers.
- *
- * @ingroup ports
- */
-
-/**
- * @defgroup gcc GCC Ports
- * Ports for the GCC compiler or derivatives.
- *
- * @ingroup ports
- */
-
-/**
- * @defgroup iar IAR Ports
- * Ports for the IAR compiler.
- *
- * @ingroup ports
- */
-
-/**
- * @defgroup rvct RVCT Ports
- * Ports for the RVCT compiler.
- *
- * @ingroup ports
- */
-
-/**
- * @defgroup cosmic Cosmic Compiler Ports
- * Ports for the Compiler compiler.
- *
- * @ingroup ports
- */
-
-/**
- * @defgroup raisonance Raisonance Compiler Ports
- * Ports for the Raisonance compiler.
- *
- * @ingroup ports
- */
diff --git a/os/readme.txt b/os/readme.txt
new file mode 100644
index 000000000..46ff6c7e0
--- /dev/null
+++ b/os/readme.txt
@@ -0,0 +1,29 @@
+*****************************************************************************
+*** ChibiOS products directory organization                               ***
+*****************************************************************************
+
+--{root}                - Distribution directory.
+  +--os/                - ChibiOS products, this directory.
+  |  +--rt/             - ChibiOS/RT product.
+  |  |  +--include/     - RT kernel headers.
+  |  |  +--src/         - RT kernel sources.
+  |  |  +--templates/   - RT kernel port template files.
+  |  |  +--ports/       - RT kernel port files.
+  |  |  +--osal/        - RT kernel OSAL module for HAL interface.
+  |  +--nil/            - ChibiOS/NIL product.
+  |  |  +--include/     - Nil kernel headers.
+  |  |  +--src/         - Nil kernel sources.
+  |  |  +--templates/   - Nil kernel port template files.
+  |  |  +--ports/       - Nil kernel port files.
+  |  |  +--osal/        - Nil kernel OSAL module for HAL interface.
+  |  +--hal/            - ChibiOS/HAL product.
+  |  |  +--include/     - HAL high level headers.
+  |  |  +--src/         - HAL high level sources.
+  |  |  +--templates/   - HAL port template files.
+  |  |  +--ports/       - HAL port files (low level drivers implementations).
+  |  |  +--boards/      - HAL board files.
+  |  +--common/         - Files used by multiple ChibiOS products.
+  |  |  +--ports        - Common port files for various architectures and
+  |  |                    compilers.
+  |  +--various/        - Various portable support files.
+  |  +--ext/            - Vendor files used by ChibiOS products.
diff --git a/os/rt/include/ch.h b/os/rt/include/ch.h
new file mode 100644
index 000000000..bd8fe92d3
--- /dev/null
+++ b/os/rt/include/ch.h
@@ -0,0 +1,99 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ch.h
+ * @brief   ChibiOS/RT main include file.
+ * @details This header includes all the required kernel headers so it is the
+ *          only kernel header you usually want to include in your application.
+ *
+ * @addtogroup kernel_info
+ * @details Kernel related info.
+ * @{
+ */
+
+#ifndef _CH_H_
+#define _CH_H_
+
+/**
+ * @brief   ChibiOS/RT identification macro.
+ */
+#define _CHIBIOS_RT_
+
+/**
+ * @brief   Kernel version string.
+ */
+#define CH_KERNEL_VERSION       "3.0.0dev"
+
+/**
+ * @name    Kernel version
+ * @{
+ */
+/**
+ * @brief   Kernel version major number.
+ */
+#define CH_KERNEL_MAJOR         3
+
+/**
+ * @brief   Kernel version minor number.
+ */
+#define CH_KERNEL_MINOR         0
+
+/**
+ * @brief   Kernel version patch number.
+ */
+#define CH_KERNEL_PATCH         0
+/** @} */
+
+/* Required forward declaration, knowledge of this type is required by all
+   modules.*/
+typedef struct thread thread_t;
+
+/* Core headers.*/
+#include "chtypes.h"
+#include "chconf.h"
+#include "chcore.h"
+#include "chdebug.h"
+#include "chtm.h"
+#include "chstats.h"
+#include "chschd.h"
+#include "chsys.h"
+#include "chvt.h"
+#include "chthreads.h"
+
+/* Optional subsystems headers.*/
+#include "chregistry.h"
+#include "chsem.h"
+#include "chbsem.h"
+#include "chmtx.h"
+#include "chcond.h"
+#include "chevents.h"
+#include "chmsg.h"
+#include "chmboxes.h"
+#include "chmemcore.h"
+#include "chheap.h"
+#include "chmempools.h"
+#include "chdynamic.h"
+#include "chqueues.h"
+#include "chstreams.h"
+
+#endif /* _CH_H_ */
+
+/** @} */
diff --git a/os/rt/include/chbsem.h b/os/rt/include/chbsem.h
new file mode 100644
index 000000000..6a5397e8e
--- /dev/null
+++ b/os/rt/include/chbsem.h
@@ -0,0 +1,312 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chbsem.h
+ * @brief   Binary semaphores structures and macros.
+ *
+ * @addtogroup binary_semaphores
+ * @details Binary semaphores related APIs and services.
+ *
+ *          <h2>Operation mode</h2>
+ *          Binary semaphores are implemented as a set of macros that use the
+ *          existing counting semaphores primitives. The difference between
+ *          counting and binary semaphores is that the counter of binary
+ *          semaphores is not allowed to grow above the value 1. Repeated
+ *          signal operation are ignored. A binary semaphore can thus have
+ *          only two defined states:
+ *          - <b>Taken</b>, when its counter has a value of zero or lower
+ *            than zero. A negative number represent the number of threads
+ *            queued on the binary semaphore.
+ *          - <b>Not taken</b>, when its counter has a value of one.
+ *          .
+ *          Binary semaphores are different from mutexes because there is no
+ *          the concept of ownership, a binary semaphore can be taken by a
+ *          thread and signaled by another thread or an interrupt handler,
+ *          mutexes can only be taken and released by the same thread. Another
+ *          difference is that binary semaphores, unlike mutexes, do not
+ *          implement the priority inheritance protocol.<br>
+ *          In order to use the binary semaphores APIs the @p CH_CFG_USE_SEMAPHORES
+ *          option must be enabled in @p chconf.h.
+ * @{
+ */
+
+#ifndef _CHBSEM_H_
+#define _CHBSEM_H_
+
+#if CH_CFG_USE_SEMAPHORES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @extends semaphore_t
+ *
+ * @brief   Binary semaphore type.
+ */
+typedef struct  {
+  semaphore_t           bs_sem;
+} binary_semaphore_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Data part of a static semaphore initializer.
+ * @details This macro should be used when statically initializing a semaphore
+ *          that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the semaphore variable
+ * @param[in] taken     the semaphore initial state
+ */
+#define _BSEMAPHORE_DATA(name, taken)                                       \
+  {_SEMAPHORE_DATA(name.bs_sem, ((taken) ? 0 : 1))}
+
+/**
+ * @brief   Static semaphore initializer.
+ * @details Statically initialized semaphores require no explicit
+ *          initialization using @p chBSemInit().
+ *
+ * @param[in] name      the name of the semaphore variable
+ * @param[in] taken     the semaphore initial state
+ */
+#define BSEMAPHORE_DECL(name, taken)                                        \
+    binary_semaphore_t name = _BSEMAPHORE_DATA(name, taken)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes a binary semaphore.
+ *
+ * @param[out] bsp      pointer to a @p binary_semaphore_t structure
+ * @param[in] taken     initial state of the binary semaphore:
+ *                      - @a false, the initial state is not taken.
+ *                      - @a true, the initial state is taken.
+ *                      .
+ *
+ * @init
+ */
+static inline void chBSemObjectInit(binary_semaphore_t *bsp, bool taken) {
+
+  chSemObjectInit(&bsp->bs_sem, taken ? 0 : 1);
+}
+
+/**
+ * @brief   Wait operation on the binary semaphore.
+ *
+ * @param[in] bsp       pointer to a @p binary_semaphore_t structure
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval RDY_OK       if the binary semaphore has been successfully taken.
+ * @retval RDY_RESET    if the binary semaphore has been reset using
+ *                      @p bsemReset().
+ *
+ * @api
+ */
+static inline msg_t chBSemWait(binary_semaphore_t *bsp) {
+
+  return chSemWait(&bsp->bs_sem);
+}
+
+/**
+ * @brief   Wait operation on the binary semaphore.
+ *
+ * @param[in] bsp       pointer to a @p binary_semaphore_t structure
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval RDY_OK       if the binary semaphore has been successfully taken.
+ * @retval RDY_RESET    if the binary semaphore has been reset using
+ *                      @p bsemReset().
+ *
+ * @sclass
+ */
+static inline msg_t chBSemWaitS(binary_semaphore_t *bsp) {
+
+  chDbgCheckClassS();
+
+  return chSemWaitS(&bsp->bs_sem);
+}
+
+/**
+ * @brief   Wait operation on the binary semaphore.
+ *
+ * @param[in] bsp       pointer to a @p binary_semaphore_t structure
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval RDY_OK       if the binary semaphore has been successfully taken.
+ * @retval RDY_RESET    if the binary semaphore has been reset using
+ *                      @p bsemReset().
+ * @retval RDY_TIMEOUT  if the binary semaphore has not been signaled or reset
+ *                      within the specified timeout.
+ *
+ * @sclass
+ */
+static inline msg_t chBSemWaitTimeoutS(binary_semaphore_t *bsp,
+                                       systime_t time) {
+
+  chDbgCheckClassS();
+
+  return chSemWaitTimeoutS(&bsp->bs_sem, time);
+}
+
+/**
+ * @brief   Wait operation on the binary semaphore.
+ *
+ * @param[in] bsp       pointer to a @p binary_semaphore_t structure
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval RDY_OK       if the binary semaphore has been successfully taken.
+ * @retval RDY_RESET    if the binary semaphore has been reset using
+ *                      @p bsemReset().
+ * @retval RDY_TIMEOUT  if the binary semaphore has not been signaled or reset
+ *                      within the specified timeout.
+ *
+ * @api
+ */
+static inline msg_t chBSemWaitTimeout(binary_semaphore_t *bsp,
+                                      systime_t time) {
+
+  return chSemWaitTimeout(&bsp->bs_sem, time);
+}
+
+/**
+ * @brief   Reset operation on the binary semaphore.
+ * @note    The released threads can recognize they were waked up by a reset
+ *          rather than a signal because the @p bsemWait() will return
+ *          @p RDY_RESET instead of @p RDY_OK.
+ * @note    This function does not reschedule.
+ *
+ * @param[in] bsp       pointer to a @p binary_semaphore_t structure
+ * @param[in] taken     new state of the binary semaphore
+ *                      - @a false, the new state is not taken.
+ *                      - @a true, the new state is taken.
+ *                      .
+ *
+ * @iclass
+ */
+static inline void chBSemResetI(binary_semaphore_t *bsp, bool taken) {
+
+  chDbgCheckClassI();
+
+  chSemResetI(&bsp->bs_sem, taken ? 0 : 1);
+}
+
+/**
+ * @brief   Reset operation on the binary semaphore.
+ * @note    The released threads can recognize they were waked up by a reset
+ *          rather than a signal because the @p bsemWait() will return
+ *          @p RDY_RESET instead of @p RDY_OK.
+ *
+ * @param[in] bsp       pointer to a @p binary_semaphore_t structure
+ * @param[in] taken     new state of the binary semaphore
+ *                      - @a false, the new state is not taken.
+ *                      - @a true, the new state is taken.
+ *                      .
+ *
+ * @api
+ */
+static inline void chBSemReset(binary_semaphore_t *bsp, bool taken) {
+
+  chSemReset(&bsp->bs_sem, taken ? 0 : 1);
+}
+
+/**
+ * @brief   Performs a signal operation on a binary semaphore.
+ * @note    This function does not reschedule.
+ *
+ * @param[in] bsp       pointer to a @p binary_semaphore_t structure
+ *
+ * @iclass
+ */
+static inline void chBSemSignalI(binary_semaphore_t *bsp) {
+
+  chDbgCheckClassI();
+
+  if (bsp->bs_sem.s_cnt < 1)
+    chSemSignalI(&bsp->bs_sem);
+}
+
+/**
+ * @brief   Performs a signal operation on a binary semaphore.
+ *
+ * @param[in] bsp       pointer to a @p binary_semaphore_t structure
+ *
+ * @api
+ */
+static inline void chBSemSignal(binary_semaphore_t *bsp) {
+
+  chSysLock();
+  chBSemSignalI(bsp);
+  chSchRescheduleS();
+  chSysUnlock();
+}
+
+/**
+ * @brief   Returns the binary semaphore current state.
+ *
+ * @param[in] bsp       pointer to a @p binary_semaphore_t structure
+ * @return              The binary semaphore current state.
+ * @retval false        if the binary semaphore is not taken.
+ * @retval true         if the binary semaphore is taken.
+ *
+ * @iclass
+ */
+static inline bool chBSemGetStateI(binary_semaphore_t *bsp) {
+
+  chDbgCheckClassI();
+
+  return bsp->bs_sem.s_cnt > 0 ? false : true;
+}
+
+#endif /* CH_CFG_USE_SEMAPHORES */
+
+#endif /* _CHBSEM_H_ */
+
+/** @} */
diff --git a/os/rt/include/chcond.h b/os/rt/include/chcond.h
new file mode 100644
index 000000000..802d59d3a
--- /dev/null
+++ b/os/rt/include/chcond.h
@@ -0,0 +1,117 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/*
+   Concepts and parts of this file have been contributed by Leon Woestenberg.
+ */
+
+/**
+ * @file    chcond.h
+ * @brief   Condition Variables macros and structures.
+ *
+ * @addtogroup condvars
+ * @{
+ */
+
+#ifndef _CHCOND_H_
+#define _CHCOND_H_
+
+#if CH_CFG_USE_CONDVARS || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !CH_CFG_USE_MUTEXES
+#error "CH_CFG_USE_CONDVARS requires CH_CFG_USE_MUTEXES"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   condition_variable_t structure.
+ */
+typedef struct condition_variable {
+  threads_queue_t       c_queue;            /**< @brief Condition variable
+                                                 threads queue.             */
+} condition_variable_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief Data part of a static condition variable initializer.
+ * @details This macro should be used when statically initializing a condition
+ *          variable that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the condition variable
+ */
+#define _CONDVAR_DATA(name) {_threads_queue_t_DATA(name.c_queue)}
+
+/**
+ * @brief Static condition variable initializer.
+ * @details Statically initialized condition variables require no explicit
+ *          initialization using @p chCondInit().
+ *
+ * @param[in] name      the name of the condition variable
+ */
+#define CONDVAR_DECL(name) condition_variable_t name = _CONDVAR_DATA(name)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chCondObjectInit(condition_variable_t *cp);
+  void chCondSignal(condition_variable_t *cp);
+  void chCondSignalI(condition_variable_t *cp);
+  void chCondBroadcast(condition_variable_t *cp);
+  void chCondBroadcastI(condition_variable_t *cp);
+  msg_t chCondWait(condition_variable_t *cp);
+  msg_t chCondWaitS(condition_variable_t *cp);
+#if CH_CFG_USE_CONDVARS_TIMEOUT
+  msg_t chCondWaitTimeout(condition_variable_t *cp, systime_t time);
+  msg_t chCondWaitTimeoutS(condition_variable_t *cp, systime_t time);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_CONDVARS */
+
+#endif /* _CHCOND_H_ */
+
+/** @} */
diff --git a/os/rt/include/chdebug.h b/os/rt/include/chdebug.h
new file mode 100644
index 000000000..44f44116f
--- /dev/null
+++ b/os/rt/include/chdebug.h
@@ -0,0 +1,237 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chdebug.h
+ * @brief   Debug macros and structures.
+ *
+ * @addtogroup debug
+ * @{
+ */
+
+#ifndef _CHDEBUG_H_
+#define _CHDEBUG_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Debug related settings
+ * @{
+ */
+/**
+ * @brief   Trace buffer entries.
+ */
+#ifndef CH_DBG_TRACE_BUFFER_SIZE
+#define CH_DBG_TRACE_BUFFER_SIZE            64
+#endif
+
+/**
+ * @brief   Fill value for thread stack area in debug mode.
+ */
+#ifndef CH_DBG_STACK_FILL_VALUE
+#define CH_DBG_STACK_FILL_VALUE             0x55
+#endif
+
+/**
+ * @brief   Fill value for thread area in debug mode.
+ * @note    The chosen default value is 0xFF in order to make evident which
+ *          thread fields were not initialized when inspecting the memory with
+ *          a debugger. A uninitialized field is not an error in itself but it
+ *          better to know it.
+ */
+#ifndef CH_DBG_THREAD_FILL_VALUE
+#define CH_DBG_THREAD_FILL_VALUE            0xFF
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if CH_DBG_ENABLE_ASSERTS     || CH_DBG_ENABLE_CHECKS      ||               \
+    CH_DBG_ENABLE_STACK_CHECK || CH_DBG_SYSTEM_STATE_CHECK
+#define CH_DBG_ENABLED              TRUE
+#else
+#define CH_DBG_ENABLED              FALSE
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
+/**
+ * @brief   Trace buffer record.
+ */
+typedef struct {
+  /**
+   * @brief   Time of the switch event.
+   */
+  systime_t             se_time;
+  /**
+   * @brief   Switched in thread.
+   */
+  thread_t              *se_tp;
+  /**
+   * @brief   Object where going to sleep.
+   */
+  void                  *se_wtobjp;
+  /**
+   * @brief   Switched out thread state.
+   */
+  uint8_t               se_state;
+} ch_swc_event_t;
+
+/**
+ * @brief   Trace buffer header.
+ */
+typedef struct {
+  /**
+   * @brief   Trace buffer size (entries).
+   */
+  unsigned              tb_size;
+  /**
+   * @brief   Pointer to the buffer front.
+   */
+  ch_swc_event_t        *tb_ptr;
+  /**
+   * @brief   Ring buffer.
+   */
+  ch_swc_event_t        tb_buffer[CH_DBG_TRACE_BUFFER_SIZE];
+} ch_trace_buffer_t;
+#endif /* CH_DBG_ENABLE_TRACE */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+#if CH_DBG_SYSTEM_STATE_CHECK
+#define _dbg_enter_lock() (ch.dbg_lock_cnt = 1)
+#define _dbg_leave_lock() (ch.dbg_lock_cnt = 0)
+#endif
+
+/* When the state checker feature is disabled then the following functions
+   are replaced by an empty macro.*/
+#if !CH_DBG_SYSTEM_STATE_CHECK
+#define _dbg_enter_lock()
+#define _dbg_leave_lock()
+#define _dbg_check_disable()
+#define _dbg_check_suspend()
+#define _dbg_check_enable()
+#define _dbg_check_lock()
+#define _dbg_check_unlock()
+#define _dbg_check_lock_from_isr()
+#define _dbg_check_unlock_from_isr()
+#define _dbg_check_enter_isr()
+#define _dbg_check_leave_isr()
+#define chDbgCheckClassI()
+#define chDbgCheckClassS()
+#endif
+
+/* When the trace feature is disabled this function is replaced by an empty
+   macro.*/
+#if !CH_DBG_ENABLE_TRACE
+#define _dbg_trace(otp)
+#endif
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Function parameters check.
+ * @details If the condition check fails then the kernel panics and halts.
+ * @note    The condition is tested only if the @p CH_DBG_ENABLE_CHECKS switch
+ *          is specified in @p chconf.h else the macro does nothing.
+ *
+ * @param[in] c         the condition to be verified to be true
+ *
+ * @api
+ */
+#if !defined(chDbgCheck)
+#define chDbgCheck(c) do {                                                  \
+  if (CH_DBG_ENABLE_CHECKS && !(c))                                         \
+    chSysHalt(__func__);                                                    \
+} while (0)
+#endif /* !defined(chDbgCheck) */
+
+/**
+ * @brief   Condition assertion.
+ * @details If the condition check fails then the kernel panics with a
+ *          message and halts.
+ * @note    The condition is tested only if the @p CH_DBG_ENABLE_ASSERTS switch
+ *          is specified in @p chconf.h else the macro does nothing.
+ * @note    The remark string is not currently used except for putting a
+ *          comment in the code about the assertion.
+ *
+ * @param[in] c         the condition to be verified to be true
+ * @param[in] r         a remark string
+ *
+ * @api
+ */
+#if !defined(chDbgAssert)
+#define chDbgAssert(c, r) do {                                              \
+  if (CH_DBG_ENABLE_ASSERTS && !(c))                                        \
+    chSysHalt(__func__);                                                    \
+} while (0)
+#endif /* !defined(chDbgAssert) */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+  void _dbg_check_disable(void);
+  void _dbg_check_suspend(void);
+  void _dbg_check_enable(void);
+  void _dbg_check_lock(void);
+  void _dbg_check_unlock(void);
+  void _dbg_check_lock_from_isr(void);
+  void _dbg_check_unlock_from_isr(void);
+  void _dbg_check_enter_isr(void);
+  void _dbg_check_leave_isr(void);
+  void chDbgCheckClassI(void);
+  void chDbgCheckClassS(void);
+#endif
+#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
+  void _trace_init(void);
+  void _dbg_trace(thread_t *otp);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* _CHDEBUG_H_ */
+
+/** @} */
diff --git a/os/rt/include/chdynamic.h b/os/rt/include/chdynamic.h
new file mode 100644
index 000000000..cb72bb244
--- /dev/null
+++ b/os/rt/include/chdynamic.h
@@ -0,0 +1,96 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chdynamic.h
+ * @brief   Dynamic threads macros and structures.
+ *
+ * @addtogroup dynamic_threads
+ * @{
+ */
+
+#ifndef _CHDYNAMIC_H_
+#define _CHDYNAMIC_H_
+
+#if CH_CFG_USE_DYNAMIC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Module dependencies check.
+ */
+#if CH_CFG_USE_DYNAMIC && !CH_CFG_USE_WAITEXIT
+#error "CH_CFG_USE_DYNAMIC requires CH_CFG_USE_WAITEXIT"
+#endif
+#if CH_CFG_USE_DYNAMIC && !CH_CFG_USE_HEAP && !CH_CFG_USE_MEMPOOLS
+#error "CH_CFG_USE_DYNAMIC requires CH_CFG_USE_HEAP and/or CH_CFG_USE_MEMPOOLS"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*
+ * Dynamic threads APIs.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+  thread_t *chThdAddRef(thread_t *tp);
+  void chThdRelease(thread_t *tp);
+#if CH_CFG_USE_HEAP
+  thread_t *chThdCreateFromHeap(memory_heap_t *heapp, size_t size,
+                                tprio_t prio, tfunc_t pf, void *arg);
+#endif
+#if CH_CFG_USE_MEMPOOLS
+  thread_t *chThdCreateFromMemoryPool(memory_pool_t *mp, tprio_t prio,
+                                      tfunc_t pf, void *arg);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_DYNAMIC */
+
+#endif /* _CHDYNAMIC_H_ */
+
+/** @} */
diff --git a/os/rt/include/chevents.h b/os/rt/include/chevents.h
new file mode 100644
index 000000000..e15d0e6cb
--- /dev/null
+++ b/os/rt/include/chevents.h
@@ -0,0 +1,240 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/*
+   Concepts and parts of this file have been contributed by Scott (skute).
+ */
+
+/**
+ * @file    chevents.h
+ * @brief   Events macros and structures.
+ *
+ * @addtogroup events
+ * @{
+ */
+
+#ifndef _CHEVENTS_H_
+#define _CHEVENTS_H_
+
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+typedef struct event_listener event_listener_t;
+
+/**
+ * @brief   Event Listener structure.
+ */
+struct event_listener {
+  event_listener_t      *el_next;       /**< @brief Next Event Listener
+                                                    registered on the event
+                                                    source.                 */
+  thread_t              *el_listener;   /**< @brief Thread interested in the
+                                                    event source.           */
+  eventmask_t           el_mask;        /**< @brief Event identifiers mask. */
+  eventflags_t          el_flags;       /**< @brief Flags added to the listener
+                                                    by the event source.*/
+};
+
+/**
+ * @brief   Event Source structure.
+ */
+typedef struct event_source {
+  event_listener_t      *es_next;       /**< @brief First Event Listener
+                                                    registered on the Event
+                                                    Source.                 */
+} event_source_t;
+
+/**
+ * @brief   Event Handler callback function.
+ */
+typedef void (*evhandler_t)(eventid_t);
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   All events allowed mask.
+ */
+#define ALL_EVENTS      ((eventmask_t)-1)
+
+/**
+ * @brief   Returns an event mask from an event identifier.
+ */
+#define EVENT_MASK(eid) ((eventmask_t)(1 << (eid)))
+
+/**
+ * @brief   Data part of a static event source initializer.
+ * @details This macro should be used when statically initializing an event
+ *          source that is part of a bigger structure.
+ * @param name the name of the event source variable
+ */
+#define _EVENTSOURCE_DATA(name) {(void *)(&name)}
+
+/**
+ * @brief   Static event source initializer.
+ * @details Statically initialized event sources require no explicit
+ *          initialization using @p chEvtInit().
+ *
+ * @param name          the name of the event source variable
+ */
+#define EVENTSOURCE_DECL(name) event_source_t name = _EVENTSOURCE_DATA(name)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chEvtRegisterMask(event_source_t *esp,
+                         event_listener_t *elp,
+                         eventmask_t mask);
+  void chEvtUnregister(event_source_t *esp, event_listener_t *elp);
+  eventmask_t chEvtGetAndClearEvents(eventmask_t mask);
+  eventmask_t chEvtAddEvents(eventmask_t mask);
+  eventflags_t chEvtGetAndClearFlags(event_listener_t *elp);
+  eventflags_t chEvtGetAndClearFlagsI(event_listener_t *elp);
+  void chEvtSignal(thread_t *tp, eventmask_t mask);
+  void chEvtSignalI(thread_t *tp, eventmask_t mask);
+  void chEvtBroadcastFlags(event_source_t *esp, eventflags_t flags);
+  void chEvtBroadcastFlagsI(event_source_t *esp, eventflags_t flags);
+  void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask);
+#if CH_CFG_OPTIMIZE_SPEED || !CH_CFG_USE_EVENTS_TIMEOUT
+  eventmask_t chEvtWaitOne(eventmask_t mask);
+  eventmask_t chEvtWaitAny(eventmask_t mask);
+  eventmask_t chEvtWaitAll(eventmask_t mask);
+#endif
+#if CH_CFG_USE_EVENTS_TIMEOUT
+  eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time);
+  eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time);
+  eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#if !CH_CFG_OPTIMIZE_SPEED && CH_CFG_USE_EVENTS_TIMEOUT
+#define chEvtWaitOne(mask) chEvtWaitOneTimeout(mask, TIME_INFINITE)
+#define chEvtWaitAny(mask) chEvtWaitAnyTimeout(mask, TIME_INFINITE)
+#define chEvtWaitAll(mask) chEvtWaitAllTimeout(mask, TIME_INFINITE)
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes an Event Source.
+ * @note    This function can be invoked before the kernel is initialized
+ *          because it just prepares a @p event_source_t structure.
+ *
+ * @param[in] esp       pointer to the @p event_source_t structure
+ *
+ * @init
+ */
+static inline void chEvtObjectInit(event_source_t *esp) {
+
+  esp->es_next = (event_listener_t *)(void *)esp;
+}
+
+/**
+ * @brief   Registers an Event Listener on an Event Source.
+ * @note    Multiple Event Listeners can use the same event identifier, the
+ *          listener will share the callback function.
+ *
+ * @param[in] esp       pointer to the  @p event_source_t structure
+ * @param[out] elp      pointer to the @p event_listener_t structure
+ * @param[in] eid       numeric identifier assigned to the Event Listener. The
+ *                      identifier is used as index for the event callback
+ *                      function.
+ *                      The value must range between zero and the size, in bit,
+ *                      of the @p eventid_t type minus one.
+ *
+ * @api
+ */
+static inline void chEvtRegister(event_source_t *esp,
+                                 event_listener_t *elp,
+                                 eventid_t eid) {
+
+  chEvtRegisterMask(esp, elp, EVENT_MASK(eid));
+}
+
+/**
+ * @brief   Verifies if there is at least one @p event_listener_t registered.
+ *
+ * @param[in] esp       pointer to the @p event_source_t structure
+ *
+ * @iclass
+ */
+static inline bool chEvtIsListeningI(event_source_t *esp) {
+
+  return (bool)((void *)esp != (void *)esp->es_next);
+}
+
+/**
+ * @brief   Signals all the Event Listeners registered on the specified Event
+ *          Source.
+ *
+ * @param[in] esp       pointer to the @p event_source_t structure
+ *
+ * @api
+ */
+static inline void chEvtBroadcast(event_source_t *esp) {
+
+  chEvtBroadcastFlags(esp, 0);
+}
+
+/**
+ * @brief   Signals all the Event Listeners registered on the specified Event
+ *          Source.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] esp       pointer to the @p event_source_t structure
+ *
+ * @iclass
+ */
+static inline void chEvtBroadcastI(event_source_t *esp) {
+
+  chEvtBroadcastFlagsI(esp, 0);
+}
+
+#endif /* CH_CFG_USE_EVENTS */
+
+#endif /* _CHEVENTS_H_ */
+
+/** @} */
diff --git a/os/rt/include/chheap.h b/os/rt/include/chheap.h
new file mode 100644
index 000000000..73e0d4148
--- /dev/null
+++ b/os/rt/include/chheap.h
@@ -0,0 +1,119 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chheap.h
+ * @brief   Heaps macros and structures.
+ *
+ * @addtogroup heaps
+ * @{
+ */
+
+#ifndef _CHHEAP_H_
+#define _CHHEAP_H_
+
+#if CH_CFG_USE_HEAP || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !CH_CFG_USE_MEMCORE
+#error "CH_CFG_USE_HEAP requires CH_CFG_USE_MEMCORE"
+#endif
+
+#if !CH_CFG_USE_MUTEXES && !CH_CFG_USE_SEMAPHORES
+#error "CH_CFG_USE_HEAP requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a memory heap.
+ */
+typedef struct memory_heap memory_heap_t;
+
+/**
+ * @brief   Memory heap block header.
+ */
+union heap_header {
+  stkalign_t align;
+  struct {
+    union {
+      union heap_header *next;      /**< @brief Next block in free list.    */
+      memory_heap_t     *heap;      /**< @brief Block owner heap.           */
+    } u;                            /**< @brief Overlapped fields.          */
+    size_t              size;       /**< @brief Size of the memory block.   */
+  } h;
+};
+
+/**
+ * @brief   Structure describing a memory heap.
+ */
+struct memory_heap {
+  memgetfunc_t          h_provider; /**< @brief Memory blocks provider for
+                                                this heap.                  */
+  union heap_header     h_free;     /**< @brief Free blocks list header.    */
+#if CH_CFG_USE_MUTEXES
+  mutex_t               h_mtx;      /**< @brief Heap access mutex.          */
+#else
+  semaphore_t           h_sem;      /**< @brief Heap access semaphore.      */
+#endif
+};
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _heap_init(void);
+  void chHeapObjectInit(memory_heap_t *heapp, void *buf, size_t size);
+  void *chHeapAlloc(memory_heap_t *heapp, size_t size);
+  void chHeapFree(void *p);
+  size_t chHeapStatus(memory_heap_t *heapp, size_t *sizep);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_HEAP */
+
+#endif /* _CHHEAP_H_ */
+
+/** @} */
diff --git a/os/rt/include/chmboxes.h b/os/rt/include/chmboxes.h
new file mode 100644
index 000000000..8d1dedfd1
--- /dev/null
+++ b/os/rt/include/chmboxes.h
@@ -0,0 +1,200 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmboxes.h
+ * @brief   Mailboxes macros and structures.
+ *
+ * @addtogroup mailboxes
+ * @{
+ */
+
+#ifndef _CHMBOXES_H_
+#define _CHMBOXES_H_
+
+#if CH_CFG_USE_MAILBOXES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !CH_CFG_USE_SEMAPHORES
+#error "CH_CFG_USE_MAILBOXES requires CH_CFG_USE_SEMAPHORES"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Structure representing a mailbox object.
+ */
+typedef struct {
+  msg_t                 *mb_buffer;     /**< @brief Pointer to the mailbox
+                                                    buffer.                 */
+  msg_t                 *mb_top;        /**< @brief Pointer to the location
+                                                    after the buffer.       */
+  msg_t                 *mb_wrptr;      /**< @brief Write pointer.          */
+  msg_t                 *mb_rdptr;      /**< @brief Read pointer.           */
+  semaphore_t           mb_fullsem;     /**< @brief Full counter
+                                                    @p semaphore_t.         */
+  semaphore_t           mb_emptysem;    /**< @brief Empty counter
+                                                    @p semaphore_t.         */
+} mailbox_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Data part of a static mailbox initializer.
+ * @details This macro should be used when statically initializing a
+ *          mailbox that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the mailbox variable
+ * @param[in] buffer    pointer to the mailbox buffer area
+ * @param[in] size      size of the mailbox buffer area
+ */
+#define _MAILBOX_DATA(name, buffer, size) {                             \
+  (msg_t *)(buffer),                                                    \
+  (msg_t *)(buffer) + size,                                             \
+  (msg_t *)(buffer),                                                    \
+  (msg_t *)(buffer),                                                    \
+  _SEMAPHORE_DATA(name.mb_fullsem, 0),                                  \
+  _SEMAPHORE_DATA(name.mb_emptysem, size),                              \
+}
+
+/**
+ * @brief   Static mailbox initializer.
+ * @details Statically initialized mailboxes require no explicit
+ *          initialization using @p chMBInit().
+ *
+ * @param[in] name      the name of the mailbox variable
+ * @param[in] buffer    pointer to the mailbox buffer area
+ * @param[in] size      size of the mailbox buffer area
+ */
+#define MAILBOX_DECL(name, buffer, size)                                \
+  mailbox_t name = _MAILBOX_DATA(name, buffer, size)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chMBObjectInit(mailbox_t *mbp, msg_t *buf, cnt_t n);
+  void chMBReset(mailbox_t *mbp);
+  msg_t chMBPost(mailbox_t *mbp, msg_t msg, systime_t timeout);
+  msg_t chMBPostS(mailbox_t *mbp, msg_t msg, systime_t timeout);
+  msg_t chMBPostI(mailbox_t *mbp, msg_t msg);
+  msg_t chMBPostAhead(mailbox_t *mbp, msg_t msg, systime_t timeout);
+  msg_t chMBPostAheadS(mailbox_t *mbp, msg_t msg, systime_t timeout);
+  msg_t chMBPostAheadI(mailbox_t *mbp, msg_t msg);
+  msg_t chMBFetch(mailbox_t *mbp, msg_t *msgp, systime_t timeout);
+  msg_t chMBFetchS(mailbox_t *mbp, msg_t *msgp, systime_t timeout);
+  msg_t chMBFetchI(mailbox_t *mbp, msg_t *msgp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the mailbox buffer size.
+ *
+ * @param[in] mbp       the pointer to an initialized mailbox_t object
+ *
+ * @iclass
+ */
+static inline size_t chMBSizeI(mailbox_t *mbp) {
+
+  return (size_t)(mbp->mb_top - mbp->mb_buffer);
+}
+
+/**
+ * @brief   Returns the number of free message slots into a mailbox.
+ * @note    Can be invoked in any system state but if invoked out of a locked
+ *          state then the returned value may change after reading.
+ * @note    The returned value can be less than zero when there are waiting
+ *          threads on the internal semaphore.
+ *
+ * @param[in] mbp       the pointer to an initialized mailbox_t object
+ * @return              The number of empty message slots.
+ *
+ * @iclass
+ */
+static inline cnt_t chMBGetFreeCountI(mailbox_t *mbp) {
+
+  chDbgCheckClassI();
+
+  return chSemGetCounterI(&mbp->mb_emptysem);
+}
+
+/**
+ * @brief   Returns the number of used message slots into a mailbox.
+ * @note    Can be invoked in any system state but if invoked out of a locked
+ *          state then the returned value may change after reading.
+ * @note    The returned value can be less than zero when there are waiting
+ *          threads on the internal semaphore.
+ *
+ * @param[in] mbp       the pointer to an initialized mailbox_t object
+ * @return              The number of queued messages.
+ *
+ * @iclass
+ */
+static inline cnt_t chMBGetUsedCountI(mailbox_t *mbp) {
+
+  chDbgCheckClassI();
+
+  return chSemGetCounterI(&mbp->mb_fullsem);
+}
+
+/**
+ * @brief   Returns the next message in the queue without removing it.
+ * @pre     A message must be waiting in the queue for this function to work
+ *          or it would return garbage. The correct way to use this macro is
+ *          to use @p chMBGetFullCountI() and then use this macro, all within
+ *          a lock state.
+ *
+ * @iclass
+ */
+static inline cnt_t chMBPeekI(mailbox_t *mbp) {
+
+  chDbgCheckClassI();
+
+  return *mbp->mb_rdptr;
+}
+
+#endif /* CH_CFG_USE_MAILBOXES */
+
+#endif /* _CHMBOXES_H_ */
+
+/** @} */
diff --git a/os/rt/include/chmemcore.h b/os/rt/include/chmemcore.h
new file mode 100644
index 000000000..314e94365
--- /dev/null
+++ b/os/rt/include/chmemcore.h
@@ -0,0 +1,114 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmemcore.h
+ * @brief   Core memory manager macros and structures.
+ *
+ * @addtogroup memcore
+ * @{
+ */
+
+#ifndef _CHMEMCORE_H_
+#define _CHMEMCORE_H_
+
+#if CH_CFG_USE_MEMCORE || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Memory get function.
+ * @note    This type must be assignment compatible with the @p chMemAlloc()
+ *          function.
+ */
+typedef void *(*memgetfunc_t)(size_t size);
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Alignment support macros
+ */
+/**
+ * @brief   Alignment size constant.
+ */
+#define MEM_ALIGN_SIZE      sizeof(stkalign_t)
+
+/**
+ * @brief   Alignment mask constant.
+ */
+#define MEM_ALIGN_MASK      (MEM_ALIGN_SIZE - 1)
+
+/**
+ * @brief   Alignment helper macro.
+ */
+#define MEM_ALIGN_PREV(p)   ((size_t)(p) & ~MEM_ALIGN_MASK)
+
+/**
+ * @brief   Alignment helper macro.
+ */
+#define MEM_ALIGN_NEXT(p)   MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK)
+
+/**
+ * @brief   Returns whatever a pointer or memory size is aligned to
+ *          the type @p align_t.
+ */
+#define MEM_IS_ALIGNED(p)   (((size_t)(p) & MEM_ALIGN_MASK) == 0)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _core_init(void);
+  void *chCoreAlloc(size_t size);
+  void *chCoreAllocI(size_t size);
+  size_t chCoreStatus(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_MEMCORE */
+
+#endif /* _CHMEMCORE_H_ */
+
+/** @} */
diff --git a/os/rt/include/chmempools.h b/os/rt/include/chmempools.h
new file mode 100644
index 000000000..85b94fc73
--- /dev/null
+++ b/os/rt/include/chmempools.h
@@ -0,0 +1,169 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmempools.h
+ * @brief   Memory Pools macros and structures.
+ *
+ * @addtogroup pools
+ * @{
+ */
+
+#ifndef _CHMEMPOOLS_H_
+#define _CHMEMPOOLS_H_
+
+#if CH_CFG_USE_MEMPOOLS || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+#if !CH_CFG_USE_MEMCORE
+#error "CH_CFG_USE_MEMPOOLS requires CH_CFG_USE_MEMCORE"
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Memory pool free object header.
+ */
+struct pool_header {
+  struct pool_header    *ph_next;       /**< @brief Pointer to the next pool
+                                                    header in the list.     */
+};
+
+/**
+ * @brief   Memory pool descriptor.
+ */
+typedef struct {
+  struct pool_header    *mp_next;       /**< @brief Pointer to the header.  */
+  size_t                mp_object_size; /**< @brief Memory pool objects
+                                                    size.                   */
+  memgetfunc_t          mp_provider;    /**< @brief Memory blocks provider
+                                                    for this pool.          */
+} memory_pool_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Data part of a static memory pool initializer.
+ * @details This macro should be used when statically initializing a
+ *          memory pool that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the memory pool variable
+ * @param[in] size      size of the memory pool contained objects
+ * @param[in] provider  memory provider function for the memory pool
+ */
+#define _MEMORYPOOL_DATA(name, size, provider)                              \
+  {NULL, size, provider}
+
+/**
+ * @brief Static memory pool initializer in hungry mode.
+ * @details Statically initialized memory pools require no explicit
+ *          initialization using @p chPoolInit().
+ *
+ * @param[in] name the name of the memory pool variable
+ * @param[in] size size of the memory pool contained objects
+ * @param[in] provider memory provider function for the memory pool or @p NULL
+ *                     if the pool is not allowed to grow automatically
+ */
+#define MEMORYPOOL_DECL(name, size, provider)                               \
+  memory_pool_t name = _MEMORYPOOL_DATA(name, size, provider)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chPoolObjectInit(memory_pool_t *mp, size_t size, memgetfunc_t provider);
+  void chPoolLoadArray(memory_pool_t *mp, void *p, size_t n);
+  void *chPoolAllocI(memory_pool_t *mp);
+  void *chPoolAlloc(memory_pool_t *mp);
+  void chPoolFreeI(memory_pool_t *mp, void *objp);
+  void chPoolFree(memory_pool_t *mp, void *objp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Adds an object to a memory pool.
+ * @pre     The memory pool must be already been initialized.
+ * @pre     The added object must be of the right size for the specified
+ *          memory pool.
+ * @pre     The added object must be memory aligned to the size of
+ *          @p stkalign_t type.
+ * @note    This function is just an alias for @p chPoolFree() and has been
+ *          added for clarity.
+ *
+ * @param[in] mp        pointer to a @p memory_pool_t structure
+ * @param[in] objp      the pointer to the object to be added
+ *
+ * @api
+ */
+static inline void chPoolAdd(memory_pool_t *mp, void *objp) {
+
+  chPoolFree(mp, objp);
+}
+
+/**
+ * @brief   Adds an object to a memory pool.
+ * @pre     The memory pool must be already been initialized.
+ * @pre     The added object must be of the right size for the specified
+ *          memory pool.
+ * @pre     The added object must be memory aligned to the size of
+ *          @p stkalign_t type.
+ * @note    This function is just an alias for @p chPoolFree() and has been
+ *          added for clarity.
+ *
+ * @param[in] mp        pointer to a @p memory_pool_t structure
+ * @param[in] objp      the pointer to the object to be added
+ *
+ * @iclass
+ */
+static inline void chPoolAddI(memory_pool_t *mp, void *objp) {
+
+  chDbgCheckClassI();
+
+  chPoolFreeI(mp, objp);
+}
+
+#endif /* CH_CFG_USE_MEMPOOLS */
+
+#endif /* _CHMEMPOOLS_H_ */
+
+/** @} */
diff --git a/os/rt/include/chmsg.h b/os/rt/include/chmsg.h
new file mode 100644
index 000000000..ff07edfb3
--- /dev/null
+++ b/os/rt/include/chmsg.h
@@ -0,0 +1,120 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmsg.h
+ * @brief   Messages macros and structures.
+ *
+ * @addtogroup messages
+ * @{
+ */
+
+#ifndef _CHMSG_H_
+#define _CHMSG_H_
+
+#if CH_CFG_USE_MESSAGES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  msg_t chMsgSend(thread_t *tp, msg_t msg);
+  thread_t * chMsgWait(void);
+  void chMsgRelease(thread_t *tp, msg_t msg);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/**
+ * @brief   Evaluates to @p true if the thread has pending messages.
+ *
+ * @iclass
+ */
+static inline bool chMsgIsPendingI(thread_t *tp) {
+
+  chDbgCheckClassI();
+
+  return (bool)(tp->p_msgqueue.p_next != (thread_t *)&tp->p_msgqueue);
+}
+
+/**
+ * @brief   Returns the message carried by the specified thread.
+ * @pre     This function must be invoked immediately after exiting a call
+ *          to @p chMsgWait().
+ *
+ * @param[in] tp        pointer to the thread
+ * @return              The message carried by the sender.
+ *
+ * @api
+ */
+static inline msg_t chMsgGet(thread_t *tp) {
+
+  return tp->p_msg;
+}
+
+/**
+ * @brief   Releases the thread waiting on top of the messages queue.
+ * @pre     Invoke this function only after a message has been received
+ *          using @p chMsgWait().
+ *
+ * @param[in] tp        pointer to the thread
+ * @param[in] msg       message to be returned to the sender
+ *
+ * @sclass
+ */
+static inline void chMsgReleaseS(thread_t *tp, msg_t msg) {
+
+  chDbgCheckClassS();
+
+  chSchWakeupS(tp, msg);
+}
+
+#endif /* CH_CFG_USE_MESSAGES */
+
+#endif /* _CHMSG_H_ */
+
+/** @} */
diff --git a/os/rt/include/chmtx.h b/os/rt/include/chmtx.h
new file mode 100644
index 000000000..9a7f2163d
--- /dev/null
+++ b/os/rt/include/chmtx.h
@@ -0,0 +1,151 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmtx.h
+ * @brief   Mutexes macros and structures.
+ *
+ * @addtogroup mutexes
+ * @{
+ */
+
+#ifndef _CHMTX_H_
+#define _CHMTX_H_
+
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a mutex structure.
+ */
+typedef struct mutex mutex_t;
+
+/**
+ * @brief   Mutex structure.
+ */
+struct mutex {
+  threads_queue_t       m_queue;    /**< @brief Queue of the threads sleeping
+                                                on this mutex.              */
+  thread_t              *m_owner;   /**< @brief Owner @p thread_t pointer or
+                                                @p NULL.                    */
+  mutex_t               *m_next;    /**< @brief Next @p mutex_t into an
+                                                owner-list or @p NULL.      */
+#if CH_CFG_USE_MUTEXES_RECURSIVE || defined(__DOXYGEN__)
+  cnt_t                 m_cnt;      /**< @brief Mutex recursion counter.    */
+#endif
+};
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Data part of a static mutex initializer.
+ * @details This macro should be used when statically initializing a mutex
+ *          that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the mutex variable
+ */
+#if CH_CFG_USE_MUTEXES_RECURSIVE || defined(__DOXYGEN__)
+#define _MUTEX_DATA(name) {_threads_queue_t_DATA(name.m_queue), NULL, NULL, 0}
+#else
+#define _MUTEX_DATA(name) {_threads_queue_t_DATA(name.m_queue), NULL, NULL}
+#endif
+
+/**
+ * @brief   Static mutex initializer.
+ * @details Statically initialized mutexes require no explicit initialization
+ *          using @p chMtxInit().
+ *
+ * @param[in] name      the name of the mutex variable
+ */
+#define MUTEX_DECL(name) mutex_t name = _MUTEX_DATA(name)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chMtxObjectInit(mutex_t *mp);
+  void chMtxLock(mutex_t *mp);
+  void chMtxLockS(mutex_t *mp);
+  bool chMtxTryLock(mutex_t *mp);
+  bool chMtxTryLockS(mutex_t *mp);
+  void chMtxUnlock(mutex_t *mp);
+  void chMtxUnlockS(mutex_t *mp);
+  void chMtxUnlockAll(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns @p true if the mutex queue contains at least a waiting
+ *          thread.
+ *
+ * @deprecated
+ * @sclass
+ */
+static inline bool chMtxQueueNotEmptyS(mutex_t *mp) {
+
+  chDbgCheckClassS();
+
+  return queue_notempty(&mp->m_queue);
+}
+
+/**
+ * @brief   Returns the next mutex in the mutexes stack of the current thread.
+ *
+ * @return              A pointer to the next mutex in the stack.
+ * @retval NULL         if the stack is empty.
+ *
+ * @sclass
+ */
+static inline mutex_t *chMtxGetNextMutexS(void) {
+
+  return chThdGetSelfX()->p_mtxlist;
+}
+
+#endif /* CH_CFG_USE_MUTEXES */
+
+#endif /* _CHMTX_H_ */
+
+/** @} */
diff --git a/os/rt/include/chqueues.h b/os/rt/include/chqueues.h
new file mode 100644
index 000000000..1cf778d3f
--- /dev/null
+++ b/os/rt/include/chqueues.h
@@ -0,0 +1,431 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chqueues.h
+ * @brief   I/O Queues macros and structures.
+ *
+ * @addtogroup io_queues
+ * @{
+ */
+
+#ifndef _CHQUEUES_H_
+#define _CHQUEUES_H_
+
+#if CH_CFG_USE_QUEUES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Queue functions returned status value
+ * @{
+ */
+#define Q_OK            MSG_OK      /**< @brief Operation successful.       */
+#define Q_TIMEOUT       MSG_TIMEOUT /**< @brief Timeout condition.          */
+#define Q_RESET         MSG_RESET   /**< @brief Queue has been reset.       */
+#define Q_EMPTY         -3          /**< @brief Queue empty.                */
+#define Q_FULL          -4          /**< @brief Queue full,                 */
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a generic I/O queue structure.
+ */
+typedef struct io_queue io_queue_t;
+
+/** @brief Queue notification callback type.*/
+typedef void (*qnotify_t)(io_queue_t *qp);
+
+/**
+ * @brief   Generic I/O queue structure.
+ * @details This structure represents a generic Input or Output asymmetrical
+ *          queue. The queue is asymmetrical because one end is meant to be
+ *          accessed from a thread context, and thus can be blocking, the other
+ *          end is accessible from interrupt handlers or from within a kernel
+ *          lock zone (see <b>I-Locked</b> and <b>S-Locked</b> states in
+ *          @ref system_states) and is non-blocking.
+ */
+struct io_queue {
+  threads_queue_t       q_waiting;  /**< @brief Queue of waiting threads.   */
+  size_t                q_counter;  /**< @brief Resources counter.          */
+  uint8_t               *q_buffer;  /**< @brief Pointer to the queue buffer.*/
+  uint8_t               *q_top;     /**< @brief Pointer to the first location
+                                                after the buffer.           */
+  uint8_t               *q_wrptr;   /**< @brief Write pointer.              */
+  uint8_t               *q_rdptr;   /**< @brief Read pointer.               */
+  qnotify_t             q_notify;   /**< @brief Data notification callback. */
+  void                  *q_link;    /**< @brief Application defined field.  */
+};
+
+/**
+ * @extends io_queue_t
+ *
+ * @brief   Type of an input queue structure.
+ * @details This structure represents a generic asymmetrical input queue.
+ *          Writing to the queue is non-blocking and can be performed from
+ *          interrupt handlers or from within a kernel lock zone (see
+ *          <b>I-Locked</b> and <b>S-Locked</b> states in @ref system_states).
+ *          Reading the queue can be a blocking operation and is supposed to
+ *          be performed by a system thread.
+ */
+typedef io_queue_t input_queue_t;
+
+/**
+ * @extends io_queue_t
+ *
+ * @brief   Type of an output queue structure.
+ * @details This structure represents a generic asymmetrical output queue.
+ *          Reading from the queue is non-blocking and can be performed from
+ *          interrupt handlers or from within a kernel lock zone (see
+ *          <b>I-Locked</b> and <b>S-Locked</b> states in @ref system_states).
+ *          Writing the queue can be a blocking operation and is supposed to
+ *          be performed by a system thread.
+ */
+typedef io_queue_t output_queue_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Data part of a static input queue initializer.
+ * @details This macro should be used when statically initializing an
+ *          input queue that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the input queue variable
+ * @param[in] buffer    pointer to the queue buffer area
+ * @param[in] size      size of the queue buffer area
+ * @param[in] inotify   input notification callback pointer
+ * @param[in] link      application defined pointer
+ */
+#define _INPUTQUEUE_DATA(name, buffer, size, inotify, link) {               \
+  _threads_queue_t_DATA(name),                                              \
+  0,                                                                        \
+  (uint8_t *)(buffer),                                                      \
+  (uint8_t *)(buffer) + (size),                                             \
+  (uint8_t *)(buffer),                                                      \
+  (uint8_t *)(buffer),                                                      \
+  (inotify),                                                                \
+  (link)                                                                    \
+}
+
+/**
+ * @brief   Static input queue initializer.
+ * @details Statically initialized input queues require no explicit
+ *          initialization using @p chIQInit().
+ *
+ * @param[in] name      the name of the input queue variable
+ * @param[in] buffer    pointer to the queue buffer area
+ * @param[in] size      size of the queue buffer area
+ * @param[in] inotify   input notification callback pointer
+ * @param[in] link      application defined pointer
+ */
+#define INPUTQUEUE_DECL(name, buffer, size, inotify, link)                  \
+  input_queue_t name = _INPUTQUEUE_DATA(name, buffer, size, inotify, link)
+
+/**
+ * @brief   Data part of a static output queue initializer.
+ * @details This macro should be used when statically initializing an
+ *          output queue that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the output queue variable
+ * @param[in] buffer    pointer to the queue buffer area
+ * @param[in] size      size of the queue buffer area
+ * @param[in] onotify   output notification callback pointer
+ * @param[in] link      application defined pointer
+ */
+#define _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) {              \
+  _threads_queue_t_DATA(name),                                              \
+  (size),                                                                   \
+  (uint8_t *)(buffer),                                                      \
+  (uint8_t *)(buffer) + (size),                                             \
+  (uint8_t *)(buffer),                                                      \
+  (uint8_t *)(buffer),                                                      \
+  (onotify),                                                                \
+  (link)                                                                    \
+}
+
+/**
+ * @brief   Static output queue initializer.
+ * @details Statically initialized output queues require no explicit
+ *          initialization using @p chOQInit().
+ *
+ * @param[in] name      the name of the output queue variable
+ * @param[in] buffer    pointer to the queue buffer area
+ * @param[in] size      size of the queue buffer area
+ * @param[in] onotify   output notification callback pointer
+ * @param[in] link      application defined pointer
+ */
+#define OUTPUTQUEUE_DECL(name, buffer, size, onotify, link)                 \
+  output_queue_t name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link)
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Returns the queue's buffer size.
+ *
+ * @param[in] qp        pointer to a @p io_queue_t structure.
+ * @return              The buffer size.
+ *
+ * @iclass
+ */
+#define chQSizeI(qp) ((size_t)((qp)->q_top - (qp)->q_buffer))
+
+/**
+ * @brief   Queue space.
+ * @details Returns the used space if used on an input queue or the empty
+ *          space if used on an output queue.
+ *
+ * @param[in] qp        pointer to a @p io_queue_t structure.
+ * @return              The buffer space.
+ *
+ * @iclass
+ */
+#define chQSpaceI(qp) ((qp)->q_counter)
+
+/**
+ * @brief   Returns the queue application-defined link.
+ *
+ * @param[in] qp        pointer to a @p io_queue_t structure.
+ * @return              The application-defined link.
+ *
+ * @xclass
+ */
+#define chQGetLinkX(qp) ((qp)->q_link)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chIQObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size,
+                      qnotify_t infy, void *link);
+  void chIQResetI(input_queue_t *iqp);
+  msg_t chIQPutI(input_queue_t *iqp, uint8_t b);
+  msg_t chIQGetTimeout(input_queue_t *iqp, systime_t time);
+  size_t chIQReadTimeout(input_queue_t *iqp, uint8_t *bp,
+                         size_t n, systime_t time);
+
+  void chOQObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size,
+                      qnotify_t onfy, void *link);
+  void chOQResetI(output_queue_t *oqp);
+  msg_t chOQPutTimeout(output_queue_t *oqp, uint8_t b, systime_t time);
+  msg_t chOQGetI(output_queue_t *oqp);
+  size_t chOQWriteTimeout(output_queue_t *oqp, const uint8_t *bp,
+                          size_t n, systime_t time);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the filled space into an input queue.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @return              The number of full bytes in the queue.
+ * @retval 0            if the queue is empty.
+ *
+ * @iclass
+ */
+static inline size_t chIQGetFullI(input_queue_t *iqp) {
+
+  chDbgCheckClassI();
+
+  return (size_t)chQSpaceI(iqp);
+}
+
+/**
+ * @brief   Returns the empty space into an input queue.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @return              The number of empty bytes in the queue.
+ * @retval 0            if the queue is full.
+ *
+ * @iclass
+ */
+static inline size_t chIQGetEmptyI(input_queue_t *iqp) {
+
+  chDbgCheckClassI();
+
+  return (size_t)(chQSizeI(iqp) - chQSpaceI(iqp));
+}
+
+/**
+ * @brief   Evaluates to @p true if the specified input queue is empty.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure.
+ * @return              The queue status.
+ * @retval false        if the queue is not empty.
+ * @retval true         if the queue is empty.
+ *
+ * @iclass
+ */
+static inline bool chIQIsEmptyI(input_queue_t *iqp) {
+
+  chDbgCheckClassI();
+
+  return (bool)(chQSpaceI(iqp) <= 0);
+}
+
+/**
+ * @brief   Evaluates to @p true if the specified input queue is full.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure.
+ * @return              The queue status.
+ * @retval false        if the queue is not full.
+ * @retval true         if the queue is full.
+ *
+ * @iclass
+ */
+static inline bool chIQIsFullI(input_queue_t *iqp) {
+
+  chDbgCheckClassI();
+
+  return (bool)((iqp->q_wrptr == iqp->q_rdptr) && (iqp->q_counter != 0));
+}
+
+/**
+ * @brief   Input queue read.
+ * @details This function reads a byte value from an input queue. If the queue
+ *          is empty then the calling thread is suspended until a byte arrives
+ *          in the queue.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @return              A byte value from the queue.
+ * @retval Q_RESET      if the queue has been reset.
+ *
+ * @api
+ */
+static inline msg_t chIQGet(input_queue_t *iqp) {
+
+  return chIQGetTimeout(iqp, TIME_INFINITE);
+}
+
+/**
+ * @brief   Returns the filled space into an output queue.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @return              The number of full bytes in the queue.
+ * @retval 0            if the queue is empty.
+ *
+ * @iclass
+ */
+static inline size_t chOQGetFullI(output_queue_t *oqp) {
+
+  chDbgCheckClassI();
+
+  return (size_t)(chQSizeI(oqp) - chQSpaceI(oqp));
+}
+
+/**
+ * @brief   Returns the empty space into an output queue.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @return              The number of empty bytes in the queue.
+ * @retval 0            if the queue is full.
+ *
+ * @iclass
+ */
+static inline size_t chOQGetEmptyI(output_queue_t *oqp) {
+
+  chDbgCheckClassI();
+
+  return (size_t)chQSpaceI(oqp);
+}
+
+/**
+ * @brief   Evaluates to @p true if the specified output queue is empty.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure.
+ * @return              The queue status.
+ * @retval false        if the queue is not empty.
+ * @retval true         if the queue is empty.
+ *
+ * @iclass
+ */
+static inline bool chOQIsEmptyI(output_queue_t *oqp) {
+
+  chDbgCheckClassI();
+
+  return (bool)((oqp->q_wrptr == oqp->q_rdptr) && (oqp->q_counter != 0));
+}
+
+/**
+ * @brief   Evaluates to @p true if the specified output queue is full.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure.
+ * @return              The queue status.
+ * @retval false        if the queue is not full.
+ * @retval true         if the queue is full.
+ *
+ * @iclass
+ */
+static inline bool chOQIsFullI(output_queue_t *oqp) {
+
+  chDbgCheckClassI();
+
+  return (bool)(chQSpaceI(oqp) <= 0);
+}
+
+/**
+ * @brief   Output queue write.
+ * @details This function writes a byte value to an output queue. If the queue
+ *          is full then the calling thread is suspended until there is space
+ *          in the queue.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @param[in] b         the byte value to be written in the queue
+ * @return              The operation status.
+ * @retval Q_OK         if the operation succeeded.
+ * @retval Q_RESET      if the queue has been reset.
+ *
+ * @api
+ */
+static inline msg_t chOQPut(output_queue_t *oqp, uint8_t b) {
+
+  return chOQPutTimeout(oqp, b, TIME_INFINITE);
+}
+
+#endif /* CH_CFG_USE_QUEUES */
+
+#endif /* _CHQUEUES_H_ */
+
+/** @} */
diff --git a/os/rt/include/chregistry.h b/os/rt/include/chregistry.h
new file mode 100644
index 000000000..e4cbb0d68
--- /dev/null
+++ b/os/rt/include/chregistry.h
@@ -0,0 +1,167 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chregistry.h
+ * @brief   Threads registry macros and structures.
+ *
+ * @addtogroup registry
+ * @{
+ */
+
+#ifndef _CHREGISTRY_H_
+#define _CHREGISTRY_H_
+
+#if CH_CFG_USE_REGISTRY || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ChibiOS/RT memory signature record.
+ */
+typedef struct {
+  char      ch_identifier[4];       /**< @brief Always set to "main".       */
+  uint8_t   ch_zero;                /**< @brief Must be zero.               */
+  uint8_t   ch_size;                /**< @brief Size of this structure.     */
+  uint16_t  ch_version;             /**< @brief Encoded ChibiOS/RT version. */
+  uint8_t   ch_ptrsize;             /**< @brief Size of a pointer.          */
+  uint8_t   ch_timesize;            /**< @brief Size of a @p systime_t.     */
+  uint8_t   ch_threadsize;          /**< @brief Size of a @p thread_t.      */
+  uint8_t   cf_off_prio;            /**< @brief Offset of @p p_prio field.  */
+  uint8_t   cf_off_ctx;             /**< @brief Offset of @p p_ctx field.   */
+  uint8_t   cf_off_newer;           /**< @brief Offset of @p p_newer field. */
+  uint8_t   cf_off_older;           /**< @brief Offset of @p p_older field. */
+  uint8_t   cf_off_name;            /**< @brief Offset of @p p_name field.  */
+  uint8_t   cf_off_stklimit;        /**< @brief Offset of @p p_stklimit
+                                                field.                      */
+  uint8_t   cf_off_state;           /**< @brief Offset of @p p_state field. */
+  uint8_t   cf_off_flags;           /**< @brief Offset of @p p_flags field. */
+  uint8_t   cf_off_refs;            /**< @brief Offset of @p p_refs field.  */
+  uint8_t   cf_off_preempt;         /**< @brief Offset of @p p_preempt
+                                                field.                      */
+  uint8_t   cf_off_time;            /**< @brief Offset of @p p_time field.  */
+} chdebug_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Removes a thread from the registry list.
+ * @note    This macro is not meant for use in application code.
+ *
+ * @param[in] tp        thread to remove from the registry
+ */
+#define REG_REMOVE(tp) {                                                    \
+  (tp)->p_older->p_newer = (tp)->p_newer;                                   \
+  (tp)->p_newer->p_older = (tp)->p_older;                                   \
+}
+
+/**
+ * @brief   Adds a thread to the registry list.
+ * @note    This macro is not meant for use in application code.
+ *
+ * @param[in] tp        thread to add to the registry
+ */
+#define REG_INSERT(tp) {                                                    \
+  (tp)->p_newer = (thread_t *)&ch.rlist;                                    \
+  (tp)->p_older = ch.rlist.r_older;                                         \
+  (tp)->p_older->p_newer = ch.rlist.r_older = (tp);                         \
+}
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  extern ROMCONST chdebug_t ch_debug;
+  thread_t *chRegFirstThread(void);
+  thread_t *chRegNextThread(thread_t *tp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Sets the current thread name.
+ * @pre     This function only stores the pointer to the name if the option
+ *          @p CH_CFG_USE_REGISTRY is enabled else no action is performed.
+ *
+ * @param[in] p         thread name as a zero terminated string
+ *
+ * @api
+ */
+static inline void chRegSetThreadName(const char *name) {
+
+#if CH_CFG_USE_REGISTRY
+  currp->p_name = name;
+#else
+  (void)name;
+#endif
+}
+
+/**
+ * @brief   Returns the name of the specified thread.
+ * @pre     This function only returns the pointer to the name if the option
+ *          @p CH_CFG_USE_REGISTRY is enabled else @p NULL is returned.
+ *
+ * @param[in] tp        pointer to the thread
+ *
+ * @return              Thread name as a zero terminated string.
+ * @retval NULL         if the thread name has not been set.
+ *
+ * @iclass
+ */
+static inline const char *chRegGetThreadNameI(thread_t *tp) {
+
+  chDbgCheckClassI();
+
+#if CH_CFG_USE_REGISTRY
+  return tp->p_name;
+#else
+  (void)tp;
+  return NULL;
+#endif
+}
+
+#endif /* CH_CFG_USE_REGISTRY */
+
+#endif /* _CHREGISTRY_H_ */
+
+/** @} */
diff --git a/os/rt/include/chschd.h b/os/rt/include/chschd.h
new file mode 100644
index 000000000..a89c49161
--- /dev/null
+++ b/os/rt/include/chschd.h
@@ -0,0 +1,607 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chschd.h
+ * @brief   Scheduler macros and structures.
+ *
+ * @addtogroup scheduler
+ * @{
+ */
+
+#ifndef _CHSCHD_H_
+#define _CHSCHD_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Wakeup status codes
+ * @{
+ */
+#define MSG_OK          0           /**< @brief Normal wakeup message.      */
+#define MSG_TIMEOUT     -1          /**< @brief Wakeup caused by a timeout
+                                         condition.                         */
+#define MSG_RESET       -2          /**< @brief Wakeup caused by a reset
+                                         condition.                         */
+/** @} */
+
+/**
+ * @name    Priority constants
+ * @{
+ */
+#define NOPRIO          0           /**< @brief Ready list header priority. */
+#define IDLEPRIO        1           /**< @brief Idle thread priority.       */
+#define LOWPRIO         2           /**< @brief Lowest user priority.       */
+#define NORMALPRIO      64          /**< @brief Normal user priority.       */
+#define HIGHPRIO        127         /**< @brief Highest user priority.      */
+#define ABSPRIO         255         /**< @brief Greatest possible priority. */
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @extends threads_queue_t
+ *
+ * @brief   Type of a thread structure.
+ */
+typedef struct thread thread_t;
+
+/**
+ * @extends threads_list_t
+ *
+ * @brief   Type of a generic threads bidirectional linked list header and element.
+ */
+typedef struct {
+  thread_t              *p_next;    /**< @brief Next in the list/queue.     */
+  thread_t              *p_prev;    /**< @brief Previous in the queue.      */
+} threads_queue_t;
+
+/**
+ * @brief   Type of a generic threads single link list, it works like a stack.
+ */
+typedef struct {
+  thread_t              *p_next;    /**< @brief Next in the list/queue.     */
+} threads_list_t;
+
+/**
+ * @extends threads_queue_t
+ *
+ * @brief   Ready list header.
+ */
+typedef struct {
+  threads_queue_t       r_queue;    /**< @brief Threads queue.              */
+  tprio_t               r_prio;     /**< @brief This field must be
+                                                initialized to zero.        */
+  struct context        r_ctx;      /**< @brief Not used, present because
+                                                offsets.                    */
+#if CH_CFG_USE_REGISTRY || defined(__DOXYGEN__)
+  thread_t              *r_newer;   /**< @brief Newer registry element.     */
+  thread_t              *r_older;   /**< @brief Older registry element.     */
+#endif
+  /* End of the fields shared with the thread_t structure.*/
+  thread_t              *r_current; /**< @brief The currently running
+                                                thread.                     */
+} ready_list_t;
+
+/**
+ * @brief   Structure representing a thread.
+ * @note    Not all the listed fields are always needed, by switching off some
+ *          not needed ChibiOS/RT subsystems it is possible to save RAM space
+ *          by shrinking this structure.
+ */
+struct thread {
+  thread_t              *p_next;    /**< @brief Next in the list/queue.     */
+  /* End of the fields shared with the threads_list_t structure.*/
+  thread_t              *p_prev;    /**< @brief Previous in the queue.      */
+  /* End of the fields shared with the threads_queue_t structure.*/
+  tprio_t               p_prio;     /**< @brief Thread priority.            */
+  struct context        p_ctx;      /**< @brief Processor context.          */
+#if CH_CFG_USE_REGISTRY || defined(__DOXYGEN__)
+  thread_t              *p_newer;   /**< @brief Newer registry element.     */
+  thread_t              *p_older;   /**< @brief Older registry element.     */
+#endif
+  /* End of the fields shared with the ReadyList structure. */
+#if CH_CFG_USE_REGISTRY || defined(__DOXYGEN__)
+  /**
+   * @brief Thread name or @p NULL.
+   */
+  const char            *p_name;
+#endif
+#if CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+  /**
+   * @brief Thread stack boundary.
+   */
+  stkalign_t            *p_stklimit;
+#endif
+  /**
+   * @brief Current thread state.
+   */
+  tstate_t              p_state;
+  /**
+   * @brief Various thread flags.
+   */
+  tmode_t               p_flags;
+#if CH_CFG_USE_DYNAMIC || defined(__DOXYGEN__)
+  /**
+   * @brief References to this thread.
+   */
+  trefs_t               p_refs;
+#endif
+  /**
+   * @brief Number of ticks remaining to this thread.
+   */
+#if (CH_CFG_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
+  tslices_t             p_preempt;
+#endif
+#if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__)
+  /**
+   * @brief Thread consumed time in ticks.
+   * @note  This field can overflow.
+   */
+  volatile systime_t    p_time;
+#endif
+  /**
+   * @brief State-specific fields.
+   * @note  All the fields declared in this union are only valid in the
+   *        specified state or condition and are thus volatile.
+   */
+  union {
+    /**
+     * @brief Thread wakeup code.
+     * @note  This field contains the low level message sent to the thread
+     *        by the waking thread or interrupt handler. The value is valid
+     *        after exiting the @p chSchWakeupS() function.
+     */
+    msg_t               rdymsg;
+    /**
+     * @brief Thread exit code.
+     * @note  The thread termination code is stored in this field in order
+     *        to be retrieved by the thread performing a @p chThdWait() on
+     *        this thread.
+     */
+    msg_t               exitcode;
+    /**
+     * @brief Pointer to a generic "wait" object.
+     * @note  This field is used to get a generic pointer to a synchronization
+     *        object and is valid when the thread is in one of the wait
+     *        states.
+     */
+    void                *wtobjp;
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
+    /**
+     * @brief Enabled events mask.
+     * @note  This field is only valid while the thread is in the
+     *        @p CH_STATE_WTOREVT or @p CH_STATE_WTANDEVT states.
+     */
+    eventmask_t         ewmask;
+#endif
+  }                     p_u;
+#if CH_CFG_USE_WAITEXIT || defined(__DOXYGEN__)
+  /**
+   * @brief Termination waiting list.
+   */
+  threads_list_t        p_waiting;
+#endif
+#if CH_CFG_USE_MESSAGES || defined(__DOXYGEN__)
+  /**
+   * @brief Messages queue.
+   */
+  threads_queue_t       p_msgqueue;
+  /**
+   * @brief Thread message.
+   */
+  msg_t                 p_msg;
+#endif
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
+  /**
+   * @brief Pending events mask.
+   */
+  eventmask_t           p_epending;
+#endif
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+  /**
+   * @brief List of the mutexes owned by this thread.
+   * @note  The list is terminated by a @p NULL in this field.
+   */
+  struct mutex          *p_mtxlist;
+  /**
+   * @brief Thread's own, non-inherited, priority.
+   */
+  tprio_t               p_realprio;
+#endif
+#if (CH_CFG_USE_DYNAMIC && CH_CFG_USE_MEMPOOLS) || defined(__DOXYGEN__)
+  /**
+   * @brief Memory Pool where the thread workspace is returned.
+   */
+  void                  *p_mpool;
+#endif
+#if CH_DBG_STATISTICS || defined(__DOXYGEN__)
+  time_measurement_t    p_stats;
+#endif
+#if defined(CH_CFG_THREAD_EXTRA_FIELDS)
+  /* Extra fields defined in chconf.h.*/
+  CH_CFG_THREAD_EXTRA_FIELDS
+#endif
+};
+
+/**
+ * @brief   Type of a Virtual Timer callback function.
+ */
+typedef void (*vtfunc_t)(void *);
+
+/**
+ * @brief   Type of a Virtual Timer structure.
+ */
+typedef struct virtual_timer virtual_timer_t;
+
+/**
+ * @extends virtual_timers_list_t
+ *
+ * @brief   Virtual Timer descriptor structure.
+ */
+struct virtual_timer {
+  virtual_timer_t       *vt_next;   /**< @brief Next timer in the list.     */
+  virtual_timer_t       *vt_prev;   /**< @brief Previous timer in the list. */
+  systime_t             vt_delta;   /**< @brief Time delta before timeout.  */
+  vtfunc_t              vt_func;    /**< @brief Timer callback function
+                                                pointer.                    */
+  void                  *vt_par;    /**< @brief Timer callback function
+                                                parameter.                  */
+};
+
+/**
+ * @brief   Virtual timers list header.
+ * @note    The timers list is implemented as a double link bidirectional list
+ *          in order to make the unlink time constant, the reset of a virtual
+ *          timer is often used in the code.
+ */
+typedef struct {
+  virtual_timer_t       *vt_next;   /**< @brief Next timer in the delta
+                                                list.                       */
+  virtual_timer_t       *vt_prev;   /**< @brief Last timer in the delta
+                                                list.                       */
+  systime_t             vt_delta;   /**< @brief Must be initialized to -1.  */
+#if CH_CFG_ST_TIMEDELTA == 0 || defined(__DOXYGEN__)
+  volatile systime_t    vt_systime; /**< @brief System Time counter.        */
+#endif
+#if CH_CFG_ST_TIMEDELTA > 0 || defined(__DOXYGEN__)
+  /**
+   * @brief   System time of the last tick event.
+   */
+  systime_t             vt_lasttime;/**< @brief System time of the last
+                                                tick event.                 */
+#endif
+} virtual_timers_list_t;
+
+/**
+ * @brief   System data structure.
+ * @note    This structure contain all the data areas used by the OS except
+ *          stacks.
+ */
+typedef struct ch_system {
+  /**
+   * @brief   Ready list header.
+   */
+  ready_list_t          rlist;
+  /**
+   * @brief   Virtual timers delta list header.
+   */
+  virtual_timers_list_t vtlist;
+#if CH_CFG_USE_TM || defined(__DOXYGEN__)
+  /**
+   * @brief   Measurement calibration value.
+   */
+  rtcnt_t               measurement_offset;
+#endif
+#if CH_DBG_STATISTICS || defined(__DOXYGEN__)
+  /**
+   * @brief   Global kernel statistics.
+   */
+  kernel_stats_t        kernel_stats;
+#endif
+#if CH_DBG_ENABLED || defined(__DOXYGEN__)
+  /**
+   * @brief   Pointer to the panic message.
+   * @details This pointer is meant to be accessed through the debugger, it is
+   *          written once and then the system is halted.
+   * @note    Accesses to this pointer must never be optimized out so the
+   *          field itself is declared volatile.
+   */
+  const char            * volatile dbg_panic_msg;
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK || defined(__DOXYGEN__)
+  /**
+   * @brief   ISR nesting level.
+   */
+  cnt_t                 dbg_isr_cnt;
+  /**
+   * @brief   Lock nesting level.
+   */
+  cnt_t                 dbg_lock_cnt;
+#endif
+#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
+  /**
+   * @brief   Public trace buffer.
+   */
+  ch_trace_buffer_t     dbg_trace_buffer;
+#endif
+} ch_system_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the priority of the first thread on the given ready list.
+ *
+ * @notapi
+ */
+#define firstprio(rlp)  ((rlp)->p_next->p_prio)
+
+/**
+ * @brief   Current thread pointer access macro.
+ * @note    This macro is not meant to be used in the application code but
+ *          only from within the kernel, use the @p chThdSelf() API instead.
+ * @note    It is forbidden to use this macro in order to change the pointer
+ *          (currp = something), use @p setcurrp() instead.
+ */
+#define currp ch.rlist.r_current
+
+/**
+ * @brief   Current thread pointer change macro.
+ * @note    This macro is not meant to be used in the application code but
+ *          only from within the kernel.
+ *
+ * @notapi
+ */
+#define setcurrp(tp) (currp = (tp))
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern ch_system_t ch;
+#endif
+
+/*
+ * Scheduler APIs.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _scheduler_init(void);
+  thread_t *chSchReadyI(thread_t *tp);
+  void chSchGoSleepS(tstate_t newstate);
+  msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time);
+  void chSchWakeupS(thread_t *tp, msg_t msg);
+  void chSchRescheduleS(void);
+  bool chSchIsPreemptionRequired(void);
+  void chSchDoRescheduleBehind(void);
+  void chSchDoRescheduleAhead(void);
+  void chSchDoReschedule(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+ /**
+  * @brief   Threads list initialization.
+  *
+  * @notapi
+  */
+ static inline void list_init(threads_list_t *tlp) {
+
+   tlp->p_next = (thread_t *)tlp;
+ }
+
+ /**
+  * @brief   Evaluates to @p true if the specified threads list is empty.
+  *
+  * @notapi
+  */
+ static inline bool list_isempty(threads_list_t *tlp) {
+
+   return (bool)(tlp->p_next == (thread_t *)tlp);
+ }
+
+ /**
+  * @brief   Evaluates to @p true if the specified threads list is not empty.
+  *
+  * @notapi
+  */
+ static inline bool list_notempty(threads_list_t *tlp) {
+
+   return (bool)(tlp->p_next != (thread_t *)tlp);
+ }
+
+ /**
+  * @brief   Threads queue initialization.
+  *
+  * @notapi
+  */
+ static inline void queue_init(threads_queue_t *tqp) {
+
+   tqp->p_next = tqp->p_prev = (thread_t *)tqp;
+ }
+
+ /**
+  * @brief   Evaluates to @p true if the specified threads queue is empty.
+  *
+  * @notapi
+  */
+ static inline bool queue_isempty(threads_queue_t *tqp) {
+
+   return (bool)(tqp->p_next == (thread_t *)tqp);
+ }
+
+ /**
+  * @brief   Evaluates to @p true if the specified threads queue is not empty.
+  *
+  * @notapi
+  */
+ static inline bool queue_notempty(threads_queue_t *tqp) {
+
+   return (bool)(tqp->p_next != (thread_t *)tqp);
+ }
+
+ /* If the performance code path has been chosen then all the following
+    functions are inlined into the various kernel modules.*/
+ #if CH_CFG_OPTIMIZE_SPEED
+ static inline void list_insert(thread_t *tp, threads_list_t *tlp) {
+
+   tp->p_next = tlp->p_next;
+   tlp->p_next = tp;
+ }
+
+ static inline thread_t *list_remove(threads_list_t *tlp) {
+
+   thread_t *tp = tlp->p_next;
+   tlp->p_next = tp->p_next;
+   return tp;
+ }
+
+ static inline void queue_prio_insert(thread_t *tp, threads_queue_t *tqp) {
+
+   thread_t *cp = (thread_t *)tqp;
+   do {
+     cp = cp->p_next;
+   } while ((cp != (thread_t *)tqp) && (cp->p_prio >= tp->p_prio));
+   tp->p_next = cp;
+   tp->p_prev = cp->p_prev;
+   tp->p_prev->p_next = cp->p_prev = tp;
+ }
+
+ static inline void queue_insert(thread_t *tp, threads_queue_t *tqp) {
+
+   tp->p_next = (thread_t *)tqp;
+   tp->p_prev = tqp->p_prev;
+   tp->p_prev->p_next = tqp->p_prev = tp;
+ }
+
+ static inline thread_t *queue_fifo_remove(threads_queue_t *tqp) {
+   thread_t *tp = tqp->p_next;
+
+   (tqp->p_next = tp->p_next)->p_prev = (thread_t *)tqp;
+   return tp;
+ }
+
+ static inline thread_t *queue_lifo_remove(threads_queue_t *tqp) {
+   thread_t *tp = tqp->p_prev;
+
+   (tqp->p_prev = tp->p_prev)->p_next = (thread_t *)tqp;
+   return tp;
+ }
+
+ static inline thread_t *queue_dequeue(thread_t *tp) {
+
+   tp->p_prev->p_next = tp->p_next;
+   tp->p_next->p_prev = tp->p_prev;
+   return tp;
+ }
+#endif /* CH_CFG_OPTIMIZE_SPEED */
+
+/**
+ * @brief   Determines if the current thread must reschedule.
+ * @details This function returns @p true if there is a ready thread with
+ *          higher priority.
+ *
+ * @iclass
+ */
+static inline bool chSchIsRescRequiredI(void) {
+
+  chDbgCheckClassI();
+
+  return firstprio(&ch.rlist.r_queue) > currp->p_prio;
+}
+
+/**
+ * @brief   Determines if yielding is possible.
+ * @details This function returns @p true if there is a ready thread with
+ *          equal or higher priority.
+ *
+ * @sclass
+ */
+static inline bool chSchCanYieldS(void) {
+
+  chDbgCheckClassI();
+
+  return firstprio(&ch.rlist.r_queue) >= currp->p_prio;
+}
+
+/**
+ * @brief   Yields the time slot.
+ * @details Yields the CPU control to the next thread in the ready list with
+ *          equal or higher priority, if any.
+ *
+ * @sclass
+ */
+static inline void chSchDoYieldS(void) {
+
+  chDbgCheckClassS();
+
+  if (chSchCanYieldS())
+    chSchDoRescheduleBehind();
+}
+
+/**
+ * @brief   Inline-able preemption code.
+ * @details This is the common preemption code, this function must be invoked
+ *          exclusively from the port layer.
+ *
+ * @special
+ */
+static inline void chSchPreemption(void) {
+  tprio_t p1 = firstprio(&ch.rlist.r_queue);
+  tprio_t p2 = currp->p_prio;
+
+#if CH_CFG_TIME_QUANTUM > 0
+  if (currp->p_preempt) {
+    if (p1 > p2)
+      chSchDoRescheduleAhead();
+  }
+  else {
+    if (p1 >= p2)
+      chSchDoRescheduleBehind();
+  }
+#else /* CH_CFG_TIME_QUANTUM == 0 */
+  if (p1 >= p2)
+    chSchDoRescheduleAhead();
+#endif /* CH_CFG_TIME_QUANTUM == 0 */
+}
+
+#endif /* _CHSCHD_H_ */
+
+/** @} */
diff --git a/os/rt/include/chsem.h b/os/rt/include/chsem.h
new file mode 100644
index 000000000..21ee14293
--- /dev/null
+++ b/os/rt/include/chsem.h
@@ -0,0 +1,154 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chsem.h
+ * @brief   Semaphores macros and structures.
+ *
+ * @addtogroup semaphores
+ * @{
+ */
+
+#ifndef _CHSEM_H_
+#define _CHSEM_H_
+
+#if CH_CFG_USE_SEMAPHORES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Semaphore structure.
+ */
+typedef struct semaphore {
+  threads_queue_t       s_queue;    /**< @brief Queue of the threads sleeping
+                                                on this semaphore.          */
+  cnt_t                 s_cnt;      /**< @brief The semaphore counter.      */
+} semaphore_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Data part of a static semaphore initializer.
+ * @details This macro should be used when statically initializing a semaphore
+ *          that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the semaphore variable
+ * @param[in] n         the counter initial value, this value must be
+ *                      non-negative
+ */
+#define _SEMAPHORE_DATA(name, n) {_threads_queue_t_DATA(name.s_queue), n}
+
+/**
+ * @brief   Static semaphore initializer.
+ * @details Statically initialized semaphores require no explicit
+ *          initialization using @p chSemInit().
+ *
+ * @param[in] name      the name of the semaphore variable
+ * @param[in] n         the counter initial value, this value must be
+ *                      non-negative
+ */
+#define SEMAPHORE_DECL(name, n) semaphore_t name = _SEMAPHORE_DATA(name, n)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chSemObjectInit(semaphore_t *sp, cnt_t n);
+  void chSemReset(semaphore_t *sp, cnt_t n);
+  void chSemResetI(semaphore_t *sp, cnt_t n);
+  msg_t chSemWait(semaphore_t *sp);
+  msg_t chSemWaitS(semaphore_t *sp);
+  msg_t chSemWaitTimeout(semaphore_t *sp, systime_t time);
+  msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t time);
+  void chSemSignal(semaphore_t *sp);
+  void chSemSignalI(semaphore_t *sp);
+  void chSemAddCounterI(semaphore_t *sp, cnt_t n);
+  msg_t chSemSignalWait(semaphore_t *sps, semaphore_t *spw);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Decreases the semaphore counter.
+ * @details This macro can be used when the counter is known to be positive.
+ *
+ * @iclass
+ */
+static inline void chSemFastWaitI(semaphore_t *sp) {
+
+  chDbgCheckClassI();
+
+  sp->s_cnt--;
+}
+
+/**
+ * @brief   Increases the semaphore counter.
+ * @details This macro can be used when the counter is known to be not
+ *          negative.
+ *
+ * @iclass
+ */
+static inline void chSemFastSignalI(semaphore_t *sp) {
+
+  chDbgCheckClassI();
+
+  sp->s_cnt++;
+}
+
+/**
+ * @brief   Returns the semaphore counter current value.
+ *
+ * @iclass
+ */
+static inline cnt_t chSemGetCounterI(semaphore_t *sp) {
+
+  chDbgCheckClassI();
+
+  return sp->s_cnt;
+}
+
+#endif /* CH_CFG_USE_SEMAPHORES */
+
+#endif /* _CHSEM_H_ */
+
+/** @} */
diff --git a/os/rt/include/chstats.h b/os/rt/include/chstats.h
new file mode 100644
index 000000000..b6e131141
--- /dev/null
+++ b/os/rt/include/chstats.h
@@ -0,0 +1,106 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chstats.h
+ * @brief   Statistics module macros and structures.
+ *
+ * @addtogroup statistics
+ * @{
+ */
+
+#ifndef _CHSTATS_H_
+#define _CHSTATS_H_
+
+#if CH_DBG_STATISTICS || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+#if !CH_CFG_USE_TM
+#error "CH_DBG_STATISTICS requires CH_CFG_USE_TM"
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a kernel statistics structure.
+ */
+typedef struct {
+  ucnt_t                n_irq;      /**< @brief Number of IRQs.             */
+  ucnt_t                n_ctxswc;   /**< @brief Number of context switches. */
+  time_measurement_t    m_crit_thd; /**< @brief Measurement of threads
+                                                critical zones duration.    */
+  time_measurement_t    m_crit_isr; /**< @brief Measurement of ISRs critical
+                                                zones duration.             */
+} kernel_stats_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _stats_init(void);
+  void _stats_increase_irq(void);
+  void _stats_ctxswc(thread_t *ntp, thread_t *otp);
+  void _stats_start_measure_crit_thd(void);
+  void _stats_stop_measure_crit_thd(void);
+  void _stats_start_measure_crit_isr(void);
+  void _stats_stop_measure_crit_isr(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#else /* !CH_DBG_STATISTICS */
+
+/* Stub functions for when the statistics module is disabled. */
+#define _stats_increase_irq()
+#define _stats_ctxswc(old, new)
+#define _stats_start_measure_crit_thd()
+#define _stats_stop_measure_crit_thd()
+#define _stats_start_measure_crit_isr()
+#define _stats_stop_measure_crit_isr()
+
+#endif /* !CH_DBG_STATISTICS */
+
+#endif /* _CHSTATS_H_ */
+
+/** @} */
diff --git a/os/kernel/include/chstreams.h b/os/rt/include/chstreams.h
index b9c40cac2..b9c40cac2 100644
--- a/os/kernel/include/chstreams.h
+++ b/os/rt/include/chstreams.h
diff --git a/os/rt/include/chsys.h b/os/rt/include/chsys.h
new file mode 100644
index 000000000..6c2d61684
--- /dev/null
+++ b/os/rt/include/chsys.h
@@ -0,0 +1,366 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chsys.h
+ * @brief   System related macros and structures.
+ *
+ * @addtogroup system
+ * @{
+ */
+
+#ifndef _CHSYS_H_
+#define _CHSYS_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    ISRs abstraction macros
+ */
+/**
+ * @brief   IRQ handler enter code.
+ * @note    Usually IRQ handlers functions are also declared naked.
+ * @note    On some architectures this macro can be empty.
+ *
+ * @special
+ */
+#define CH_IRQ_PROLOGUE()                                                   \
+  PORT_IRQ_PROLOGUE();                                                      \
+  _stats_increase_irq();                                                    \
+  _dbg_check_enter_isr()
+
+/**
+ * @brief   IRQ handler exit code.
+ * @note    Usually IRQ handlers function are also declared naked.
+ * @note    This macro usually performs the final reschedule by using
+ *          @p chSchIsPreemptionRequired() and @p chSchDoReschedule().
+ *
+ * @special
+ */
+#define CH_IRQ_EPILOGUE()                                                   \
+  _dbg_check_leave_isr();                                                   \
+  PORT_IRQ_EPILOGUE()
+
+/**
+ * @brief   Standard normal IRQ handler declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ *
+ * @special
+ */
+#define CH_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name    Fast ISRs abstraction macros
+ */
+/**
+ * @brief   Standard fast IRQ handler declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ * @note    Not all architectures support fast interrupts.
+ *
+ * @special
+ */
+#define CH_FAST_IRQ_HANDLER(id) PORT_FAST_IRQ_HANDLER(id)
+/** @} */
+
+/**
+ * @name    Time conversion utilities for the realtime counter
+ * @{
+ */
+/**
+ * @brief   Seconds to realtime counter.
+ * @details Converts from seconds to realtime counter cycles.
+ * @note    The macro assumes that @p freq >= @p 1.
+ *
+ * @param[in] freq      clock frequency, in Hz, of the realtime counter
+ * @param[in] sec       number of seconds
+ * @return              The number of cycles.
+ *
+ * @api
+ */
+#define S2RTC(freq, sec) ((freq) * (sec))
+
+/**
+ * @brief   Milliseconds to realtime counter.
+ * @details Converts from milliseconds to realtime counter cycles.
+ * @note    The result is rounded upward to the next millisecond boundary.
+ * @note    The macro assumes that @p freq >= @p 1000.
+ *
+ * @param[in] freq      clock frequency, in Hz, of the realtime counter
+ * @param[in] msec      number of milliseconds
+ * @return              The number of cycles.
+ *
+ * @api
+ */
+#define MS2RTC(freq, msec) (rtcnt_t)((((freq) + 999UL) / 1000UL) * (msec))
+
+/**
+ * @brief   Microseconds to realtime counter.
+ * @details Converts from microseconds to realtime counter cycles.
+ * @note    The result is rounded upward to the next microsecond boundary.
+ * @note    The macro assumes that @p freq >= @p 1000000.
+ *
+ * @param[in] freq      clock frequency, in Hz, of the realtime counter
+ * @param[in] usec      number of microseconds
+ * @return              The number of cycles.
+ *
+ * @api
+ */
+#define US2RTC(freq, usec) (rtcnt_t)((((freq) + 999999UL) / 1000000UL) * (usec))
+
+/**
+ * @brief   Realtime counter cycles to seconds.
+ * @details Converts from realtime counter cycles number to seconds.
+ * @note    The result is rounded up to the next second boundary.
+ * @note    The macro assumes that @p freq >= @p 1.
+ *
+ * @param[in] freq      clock frequency, in Hz, of the realtime counter
+ * @param[in] n         number of cycles
+ * @return              The number of seconds.
+ *
+ * @api
+ */
+#define RTC2S(freq, n) ((((n) - 1UL) / (freq)) + 1UL)
+
+/**
+ * @brief   Realtime counter cycles to milliseconds.
+ * @details Converts from realtime counter cycles number to milliseconds.
+ * @note    The result is rounded up to the next millisecond boundary.
+ * @note    The macro assumes that @p freq >= @p 1000.
+ *
+ * @param[in] freq      clock frequency, in Hz, of the realtime counter
+ * @param[in] n         number of cycles
+ * @return              The number of milliseconds.
+ *
+ * @api
+ */
+#define RTC2MS(freq, n) ((((n) - 1UL) / ((freq) / 1000UL)) + 1UL)
+
+/**
+ * @brief   Realtime counter cycles to microseconds.
+ * @details Converts from realtime counter cycles number to microseconds.
+ * @note    The result is rounded up to the next microsecond boundary.
+ * @note    The macro assumes that @p freq >= @p 1000000.
+ *
+ * @param[in] freq      clock frequency, in Hz, of the realtime counter
+ * @param[in] n         number of cycles
+ * @return              The number of microseconds.
+ *
+ * @api
+ */
+#define RTC2US(freq, n) ((((n) - 1UL) / ((freq) / 1000000UL)) + 1UL)
+/** @} */
+
+/**
+ * @brief   Returns the current value of the system real time counter.
+ * @note    This function is only available if the port layer supports the
+ *          option @p PORT_SUPPORTS_RT.
+ *
+ * @return              The value of the system realtime counter of
+ *                      type rtcnt_t.
+ *
+ * @xclass
+ */
+#if PORT_SUPPORTS_RT || defined(__DOXYGEN__)
+#define chSysGetRealtimeCounterX() (rtcnt_t)port_rt_get_counter_value()
+#endif
+
+/**
+ * @brief   Performs a context switch.
+ * @note    Not a user function, it is meant to be invoked by the scheduler
+ *          itself or from within the port layer.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ *
+ * @special
+ */
+#define chSysSwitch(ntp, otp) {                                             \
+                                                                            \
+  _dbg_trace(otp);                                                          \
+  _stats_ctxswc(ntp, otp);                                                  \
+  CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp);                                     \
+  port_switch(ntp, otp);                                                    \
+}
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chSysInit(void);
+  void chSysHalt(const char *reason);
+  void chSysTimerHandlerI(void);
+  syssts_t chSysGetStatusAndLockX(void);
+  void chSysRestoreStatusX(syssts_t sts);
+#if PORT_SUPPORTS_RT
+  bool chSysIsCounterWithinX(rtcnt_t cnt, rtcnt_t start, rtcnt_t end);
+  void chSysPolledDelayX(rtcnt_t cycles);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Raises the system interrupt priority mask to the maximum level.
+ * @details All the maskable interrupt sources are disabled regardless their
+ *          hardware priority.
+ * @note    Do not invoke this API from within a kernel lock.
+ *
+ * @special
+ */
+static inline void chSysDisable(void) {
+
+  port_disable();
+  _dbg_check_disable();
+}
+
+/**
+ * @brief   Raises the system interrupt priority mask to system level.
+ * @details The interrupt sources that should not be able to preempt the kernel
+ *          are disabled, interrupt sources with higher priority are still
+ *          enabled.
+ * @note    Do not invoke this API from within a kernel lock.
+ * @note    This API is no replacement for @p chSysLock(), the @p chSysLock()
+ *          could do more than just disable the interrupts.
+ *
+ * @special
+ */
+static inline void chSysSuspend(void) {
+
+  port_suspend();
+  _dbg_check_suspend();
+}
+
+/**
+ * @brief   Lowers the system interrupt priority mask to user level.
+ * @details All the interrupt sources are enabled.
+ * @note    Do not invoke this API from within a kernel lock.
+ * @note    This API is no replacement for @p chSysUnlock(), the
+ *          @p chSysUnlock() could do more than just enable the interrupts.
+ *
+ * @special
+ */
+static inline void chSysEnable(void) {
+
+  _dbg_check_enable();
+  port_enable();
+}
+
+/**
+ * @brief   Enters the kernel lock mode.
+ *
+ * @special
+ */
+static inline void chSysLock(void)  {
+
+  port_lock();
+  _stats_start_measure_crit_thd();
+  _dbg_check_lock();
+}
+
+/**
+ * @brief   Leaves the kernel lock mode.
+ *
+ * @special
+ */
+static inline void chSysUnlock(void) {
+
+  _dbg_check_unlock();
+  _stats_stop_measure_crit_thd();
+
+  /* The following condition can be triggered by the use of i-class functions
+     in a critical section not followed by a chSchResceduleS(), this means
+     that the current thread has a lower priority than the next thread in
+     the ready list.*/
+  chDbgAssert(ch.rlist.r_current->p_prio >= ch.rlist.r_queue.p_next->p_prio,
+              "priority violation, missing reschedule");
+
+  port_unlock();
+}
+
+/**
+ * @brief   Enters the kernel lock mode from within an interrupt handler.
+ * @note    This API may do nothing on some architectures, it is required
+ *          because on ports that support preemptable interrupt handlers
+ *          it is required to raise the interrupt mask to the same level of
+ *          the system mutual exclusion zone.<br>
+ *          It is good practice to invoke this API before invoking any I-class
+ *          syscall from an interrupt handler.
+ * @note    This API must be invoked exclusively from interrupt handlers.
+ *
+ * @special
+ */
+static inline void chSysLockFromISR(void) {
+
+  port_lock_from_isr();
+  _stats_start_measure_crit_isr();
+  _dbg_check_lock_from_isr();
+}
+
+/**
+ * @brief   Leaves the kernel lock mode from within an interrupt handler.
+ *
+ * @note    This API may do nothing on some architectures, it is required
+ *          because on ports that support preemptable interrupt handlers
+ *          it is required to raise the interrupt mask to the same level of
+ *          the system mutual exclusion zone.<br>
+ *          It is good practice to invoke this API after invoking any I-class
+ *          syscall from an interrupt handler.
+ * @note    This API must be invoked exclusively from interrupt handlers.
+ *
+ * @special
+ */
+static inline void chSysUnlockFromISR(void) {
+
+  _dbg_check_unlock_from_isr();
+  _stats_stop_measure_crit_isr();
+  port_unlock_from_isr();
+}
+
+#endif /* _CHSYS_H_ */
+
+/** @} */
diff --git a/os/rt/include/chthreads.h b/os/rt/include/chthreads.h
new file mode 100644
index 000000000..ef83fc963
--- /dev/null
+++ b/os/rt/include/chthreads.h
@@ -0,0 +1,380 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chthreads.h
+ * @brief   Threads module macros and structures.
+ *
+ * @addtogroup threads
+ * @{
+ */
+
+#ifndef _CHTHREADS_H_
+#define _CHTHREADS_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Thread states
+ * @{
+ */
+#define CH_STATE_READY          0   /**< @brief Waiting on the ready list.  */
+#define CH_STATE_CURRENT        1   /**< @brief Currently running.          */
+#define CH_STATE_WTSTART        2   /**< @brief Created but not started.    */
+#define CH_STATE_SUSPENDED      3   /**< @brief Created in suspended state. */
+#define CH_STATE_QUEUED         4   /**< @brief Waiting on an I/O queue.    */
+#define CH_STATE_WTSEM          5   /**< @brief Waiting on a semaphore.     */
+#define CH_STATE_WTMTX          6   /**< @brief Waiting on a mutex.         */
+#define CH_STATE_WTCOND         7   /**< @brief Waiting on a condition
+                                         variable.                          */
+#define CH_STATE_SLEEPING       8   /**< @brief Waiting in @p chThdSleep()
+                                         or @p chThdSleepUntil().           */
+#define CH_STATE_WTEXIT         9   /**< @brief Waiting in @p chThdWait().  */
+#define CH_STATE_WTOREVT        10  /**< @brief Waiting for an event.       */
+#define CH_STATE_WTANDEVT       11  /**< @brief Waiting for several events. */
+#define CH_STATE_SNDMSGQ        12  /**< @brief Sending a message, in queue.*/
+#define CH_STATE_SNDMSG         13  /**< @brief Sent a message, waiting
+                                         answer.                            */
+#define CH_STATE_WTMSG          14  /**< @brief Waiting for a message.      */
+#define CH_STATE_FINAL          15  /**< @brief Thread terminated.          */
+
+/**
+ * @brief   Thread states as array of strings.
+ * @details Each element in an array initialized with this macro can be
+ *          indexed using the numeric thread state values.
+ */
+#define CH_STATE_NAMES                                                     \
+  "READY", "WTSTART", "CURRENT", "SUSPENDED", "QUEUED", "WTSEM", "WTMTX",  \
+  "WTCOND", "SLEEPING", "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ",        \
+  "SNDMSG", "WTMSG", "FINAL"
+/** @} */
+
+/**
+ * @name    Thread flags and attributes
+ * @{
+ */
+#define CH_FLAG_MODE_MASK       3   /**< @brief Thread memory mode mask.    */
+#define CH_FLAG_MODE_STATIC     0   /**< @brief Static thread.              */
+#define CH_FLAG_MODE_HEAP       1   /**< @brief Thread allocated from a
+                                         Memory Heap.                       */
+#define CH_FLAG_MODE_MEMPOOL    2   /**< @brief Thread allocated from a
+                                         Memory Pool.                       */
+#define CH_FLAG_TERMINATE       4   /**< @brief Termination requested flag. */
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a thread reference.
+ */
+typedef thread_t * thread_reference_t;
+
+/**
+ * @brief   Thread function.
+ */
+typedef msg_t (*tfunc_t)(void *);
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Working Areas and Alignment
+ */
+/**
+ * @brief   Enforces a correct alignment for a stack area size value.
+ *
+ * @param[in] n         the stack size to be aligned to the next stack
+ *                      alignment boundary
+ * @return              The aligned stack size.
+ *
+ * @api
+ */
+#define THD_ALIGN_STACK_SIZE(n)                                             \
+  ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
+
+/**
+ * @brief   Calculates the total Working Area size.
+ *
+ * @param[in] n         the stack size to be assigned to the thread
+ * @return              The total used memory in bytes.
+ *
+ * @api
+ */
+#define THD_WORKING_AREA_SIZE(n)                                            \
+  THD_ALIGN_STACK_SIZE(sizeof(thread_t) + PORT_WA_SIZE(n))
+
+/**
+ * @brief   Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ *          aligned as both position and size.
+ *
+ * @param[in] s         the name to be assigned to the stack array
+ * @param[in] n         the stack size to be assigned to the thread
+ *
+ * @api
+ */
+#define THD_WORKING_AREA(s, n)                                              \
+  stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof(stkalign_t)]
+/** @} */
+
+/**
+ * @name    Threads abstraction macros
+ */
+/**
+ * @brief   Thread declaration macro.
+ * @note    Thread declarations should be performed using this macro because
+ *          the port layer could define optimizations for thread functions.
+ */
+#define THD_FUNCTION(tname, arg) PORT_THD_FUNCTION(tname, arg)
+/** @} */
+
+/**
+ * @name    Threads queues
+ */
+/**
+ * @brief   Data part of a static threads queue object initializer.
+ * @details This macro should be used when statically initializing a threads
+ *          queue that is part of a bigger structure.
+ *
+ * @param[in] name      the name of the threads queue variable
+ */
+#define _threads_queue_t_DATA(name) {(thread_t *)&name, (thread_t *)&name}
+
+/**
+ * @brief   Static threads queue object initializer.
+ * @details Statically initialized threads queues require no explicit
+ *          initialization using @p queue_init().
+ *
+ * @param[in] name      the name of the threads queue variable
+ */
+#define threads_queue_t_DECL(name)                                          \
+  threads_queue_t name = _threads_queue_t_DATA(name)
+/** @} */
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Delays the invoking thread for the specified number of seconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system tick clock.
+ * @note    The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] sec       time in seconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepSeconds(sec) chThdSleep(S2ST(sec))
+
+/**
+ * @brief   Delays the invoking thread for the specified number of
+ *          milliseconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system tick clock.
+ * @note    The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] msec      time in milliseconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec))
+
+/**
+ * @brief   Delays the invoking thread for the specified number of
+ *          microseconds.
+ * @note    The specified time is rounded up to a value allowed by the real
+ *          system tick clock.
+ * @note    The maximum specifiable value is implementation dependent.
+ *
+ * @param[in] usec      time in microseconds, must be different from zero
+ *
+ * @api
+ */
+#define chThdSleepMicroseconds(usec) chThdSleep(US2ST(usec))
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+   thread_t *_thread_init(thread_t *tp, tprio_t prio);
+#if CH_DBG_FILL_THREADS
+  void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v);
+#endif
+  thread_t *chThdCreateI(void *wsp, size_t size,
+                         tprio_t prio, tfunc_t pf, void *arg);
+  thread_t *chThdCreateStatic(void *wsp, size_t size,
+                              tprio_t prio, tfunc_t pf, void *arg);
+  thread_t *chThdStart(thread_t *tp);
+  tprio_t chThdSetPriority(tprio_t newprio);
+  msg_t chThdSuspendS(thread_reference_t *trp);
+  msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout);
+  void chThdResumeI(thread_reference_t *trp, msg_t msg);
+  void chThdResumeS(thread_reference_t *trp, msg_t msg);
+  void chThdResume(thread_reference_t *trp, msg_t msg);
+  msg_t chThdEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout);
+  void chThdDequeueNextI(threads_queue_t *tqp, msg_t msg);
+  void chThdDequeueAllI(threads_queue_t *tqp, msg_t msg);
+  void chThdTerminate(thread_t *tp);
+  void chThdSleep(systime_t time);
+  void chThdSleepUntil(systime_t time);
+  void chThdYield(void);
+  void chThdExit(msg_t msg);
+  void chThdExitS(msg_t msg);
+#if CH_CFG_USE_WAITEXIT
+  msg_t chThdWait(thread_t *tp);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+ /**
+  * @brief   Returns a pointer to the current @p thread_t.
+  *
+  * @xclass
+  */
+static inline thread_t *chThdGetSelfX(void) {
+
+  return ch.rlist.r_current;
+}
+
+/**
+ * @brief   Returns the current thread priority.
+ * @note    Can be invoked in any context.
+ *
+ * @xclass
+ */
+static inline tprio_t chThdGetPriorityX(void) {
+
+  return chThdGetSelfX()->p_prio;
+}
+
+/**
+ * @brief   Returns the number of ticks consumed by the specified thread.
+ * @note    This function is only available when the
+ *          @p CH_DBG_THREADS_PROFILING configuration option is enabled.
+ *
+ * @param[in] tp        pointer to the thread
+ *
+ * @xclass
+ */
+#if CH_DBG_THREADS_PROFILING || defined(__DOXYGEN__)
+static inline systime_t chThdGetTicksX(thread_t *tp) {
+
+  return tp->p_time;
+}
+#endif
+
+/**
+ * @brief   Verifies if the specified thread is in the @p CH_STATE_FINAL state.
+ *
+ * @param[in] tp        pointer to the thread
+ * @retval true         thread terminated.
+ * @retval false        thread not terminated.
+ *
+ * @xclass
+ */
+static inline bool chThdTerminatedX(thread_t *tp) {
+
+  return (bool)(tp->p_state == CH_STATE_FINAL);
+}
+
+/**
+ * @brief   Verifies if the current thread has a termination request pending.
+ *
+ * @retval true         termination request pending.
+ * @retval false        termination request not pending.
+ *
+ * @xclass
+ */
+static inline bool chThdShouldTerminateX(void) {
+
+  return (bool)((chThdGetSelfX()->p_flags & CH_FLAG_TERMINATE) != 0);
+}
+
+/**
+ * @brief   Resumes a thread created with @p chThdCreateI().
+ *
+ * @param[in] tp        pointer to the thread
+ *
+ * @iclass
+ */
+static inline thread_t *chThdStartI(thread_t *tp) {
+
+  chDbgAssert(tp->p_state == CH_STATE_WTSTART, "wrong state");
+
+  return chSchReadyI(tp);
+}
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time      the delay in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ *
+ * @sclass
+ */
+static inline void chThdSleepS(systime_t time) {
+
+  chDbgCheck(time != TIME_IMMEDIATE);
+
+  chSchGoSleepTimeoutS(CH_STATE_SLEEPING, time);
+}
+
+/**
+ * @brief   Initializes a threads queue object.
+ *
+ * @param[out] tqp      pointer to the threads queue object
+ *
+ * @init
+ */
+static inline void chThdQueueObjectInit(threads_queue_t *tqp) {
+
+  queue_init(tqp);
+}
+
+#endif /* _CHTHREADS_H_ */
+
+/** @} */
diff --git a/os/rt/include/chtm.h b/os/rt/include/chtm.h
new file mode 100644
index 000000000..f85b68ca8
--- /dev/null
+++ b/os/rt/include/chtm.h
@@ -0,0 +1,100 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chtm.h
+ * @brief   Time Measurement module macros and structures.
+ *
+ * @addtogroup time_measurement
+ * @{
+ */
+
+#ifndef _CHTM_H_
+#define _CHTM_H_
+
+#if CH_CFG_USE_TM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !PORT_SUPPORTS_RT
+#error "CH_CFG_USE_TM requires PORT_SUPPORTS_RT"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a Time Measurement object.
+ * @note    The maximum measurable time period depends on the implementation
+ *          of the realtime counter and its clock frequency.
+ * @note    The measurement is not 100% cycle-accurate, it can be in excess
+ *          of few cycles depending on the compiler and target architecture.
+ * @note    Interrupts can affect measurement if the measurement is performed
+ *          with interrupts enabled.
+ */
+typedef struct {
+  rtcnt_t               best;           /**< @brief Best measurement.       */
+  rtcnt_t               worst;          /**< @brief Worst measurement.      */
+  rtcnt_t               last;           /**< @brief Last measurement.       */
+  ucnt_t                n;              /**< @brief Number of measurements. */
+  rttime_t              cumulative;     /**< @brief Cumulative measurement. */
+} time_measurement_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _tm_init(void);
+  void chTMObjectInit(time_measurement_t *tmp);
+  NOINLINE void chTMStartMeasurementX(time_measurement_t *tmp);
+  NOINLINE void chTMStopMeasurementX(time_measurement_t *tmp);
+  NOINLINE void chTMChainMeasurementToX(time_measurement_t *tmp1,
+                                        time_measurement_t *tmp2);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_TM */
+
+#endif /* _CHTM_H_ */
+
+/** @} */
diff --git a/os/rt/include/chvt.h b/os/rt/include/chvt.h
new file mode 100644
index 000000000..471ba22ee
--- /dev/null
+++ b/os/rt/include/chvt.h
@@ -0,0 +1,495 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chvt.h
+ * @brief   Time and Virtual Timers module macros and structures.
+ *
+ * @addtogroup time
+ * @{
+ */
+
+#ifndef _CHVT_H_
+#define _CHVT_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Special time constants
+ * @{
+ */
+/**
+ * @brief   Zero time specification for some functions with a timeout
+ *          specification.
+ * @note    Not all functions accept @p TIME_IMMEDIATE as timeout parameter,
+ *          see the specific function documentation.
+ */
+#define TIME_IMMEDIATE  ((systime_t)0)
+
+/**
+ * @brief   Infinite time specification for all functions with a timeout
+ *          specification.
+ * @note    Not all functions accept @p TIME_INFINITE as timeout parameter,
+ *          see the specific function documentation.
+ */
+#define TIME_INFINITE   ((systime_t)-1)
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if (CH_CFG_ST_RESOLUTION != 16) && (CH_CFG_ST_RESOLUTION != 32)
+#error "invalid CH_CFG_ST_RESOLUTION specified, must be 16 or 32"
+#endif
+
+#if CH_CFG_ST_FREQUENCY <= 0
+#error "invalid CH_CFG_ST_FREQUENCY specified, must be greated than zero"
+#endif
+
+#if (CH_CFG_ST_TIMEDELTA < 0) || (CH_CFG_ST_TIMEDELTA == 1)
+#error "invalid CH_CFG_ST_TIMEDELTA specified, must "                       \
+       "be zero or greater than one"
+#endif
+
+#if (CH_CFG_ST_TIMEDELTA > 0) && (CH_CFG_TIME_QUANTUM > 0)
+#error "CH_CFG_TIME_QUANTUM not supported in tickless mode"
+#endif
+
+#if (CH_CFG_ST_TIMEDELTA > 0) && CH_DBG_THREADS_PROFILING
+#error "CH_DBG_THREADS_PROFILING not supported in tickless mode"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Time conversion utilities
+ * @{
+ */
+/**
+ * @brief   Seconds to system ticks.
+ * @details Converts from seconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] sec       number of seconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define S2ST(sec)                                                           \
+  ((systime_t)((uint32_t)(sec) * (uint32_t)CH_CFG_ST_FREQUENCY))
+
+/**
+ * @brief   Milliseconds to system ticks.
+ * @details Converts from milliseconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] msec      number of milliseconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define MS2ST(msec)                                                         \
+  ((systime_t)(((((uint32_t)(msec)) *                                       \
+                 ((uint32_t)CH_CFG_ST_FREQUENCY) - 1UL) / 1000UL) + 1UL))
+
+/**
+ * @brief   Microseconds to system ticks.
+ * @details Converts from microseconds to system ticks number.
+ * @note    The result is rounded upward to the next tick boundary.
+ *
+ * @param[in] usec      number of microseconds
+ * @return              The number of ticks.
+ *
+ * @api
+ */
+#define US2ST(usec)                                                         \
+  ((systime_t)(((((uint32_t)(usec)) *                                       \
+                 ((uint32_t)CH_CFG_ST_FREQUENCY) - 1UL) / 1000000UL) + 1UL))
+
+/**
+ * @brief   System ticks to seconds.
+ * @details Converts from system ticks number to seconds.
+ * @note    The result is rounded up to the next second boundary.
+ *
+ * @param[in] n         number of system ticks
+ * @return              The number of seconds.
+ *
+ * @api
+ */
+#define ST2S(n) ((((n) - 1UL) / CH_CFG_ST_FREQUENCY) + 1UL)
+
+/**
+ * @brief   System ticks to milliseconds.
+ * @details Converts from system ticks number to milliseconds.
+ * @note    The result is rounded up to the next millisecond boundary.
+ *
+ * @param[in] n         number of system ticks
+ * @return              The number of milliseconds.
+ *
+ * @api
+ */
+#define ST2MS(n) ((((n) - 1UL) / (CH_CFG_ST_FREQUENCY / 1000UL)) + 1UL)
+
+/**
+ * @brief   System ticks to microseconds.
+ * @details Converts from system ticks number to microseconds.
+ * @note    The result is rounded up to the next microsecond boundary.
+ *
+ * @param[in] n         number of system ticks
+ * @return              The number of microseconds.
+ *
+ * @api
+ */
+#define ST2US(n) ((((n) - 1UL) / (CH_CFG_ST_FREQUENCY / 1000000UL)) + 1UL)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*
+ * Virtual Timers APIs.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _vt_init(void);
+  void chVTDoSetI(virtual_timer_t *vtp, systime_t delay,
+                  vtfunc_t vtfunc, void *par);
+  void chVTDoResetI(virtual_timer_t *vtp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes a @p virtual_timer_t object.
+ * @note    Initializing a timer object is not strictly required because
+ *          the function @p chVTSetI() initializes the object too. This
+ *          function is only useful if you need to perform a @p chVTIsArmed()
+ *          check before calling @p chVTSetI().
+ *
+ * @param[out] vtp      the @p virtual_timer_t structure pointer
+ *
+ * @init
+ */
+static inline void chVTObjectInit(virtual_timer_t *vtp) {
+
+  vtp->vt_func = NULL;
+}
+
+/**
+ * @brief   Current system time.
+ * @details Returns the number of system ticks since the @p chSysInit()
+ *          invocation.
+ * @note    The counter can reach its maximum and then restart from zero.
+ * @note    This function can be called from any context but its atomicity
+ *          is not guaranteed on architectures whose word size is less than
+ *          @systime_t size.
+ *
+ * @return              The system time in ticks.
+ *
+ * @xclass
+ */
+static inline systime_t chVTGetSystemTimeX(void) {
+
+#if CH_CFG_ST_TIMEDELTA == 0
+  return ch.vtlist.vt_systime;
+#else /* CH_CFG_ST_TIMEDELTA > 0 */
+  return port_timer_get_time();
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+}
+
+/**
+ * @brief   Current system time.
+ * @details Returns the number of system ticks since the @p chSysInit()
+ *          invocation.
+ * @note    The counter can reach its maximum and then restart from zero.
+ *
+ * @return              The system time in ticks.
+ *
+ * @api
+ */
+static inline systime_t chVTGetSystemTime(void) {
+  systime_t systime;
+
+  chSysLock();
+  systime = chVTGetSystemTimeX();
+  chSysUnlock();
+  return systime;
+}
+
+/**
+ * @brief   Returns the elapsed time since the specified start time.
+ *
+ * @param[in] start     start time
+ * @return              The elapsed time.
+ *
+ * @xclass
+ */
+static inline systime_t chVTTimeElapsedSinceX(systime_t start) {
+
+  return chVTGetSystemTimeX() - start;
+}
+
+/**
+ * @brief   Checks if the specified time is within the specified time window.
+ * @note    When start==end then the function returns always true because the
+ *          whole time range is specified.
+ * @note    This function can be called from any context.
+ *
+ * @param[in] time      the time to be verified
+ * @param[in] start     the start of the time window (inclusive)
+ * @param[in] end       the end of the time window (non inclusive)
+ * @retval true         current time within the specified time window.
+ * @retval false        current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool chVTIsTimeWithinX(systime_t time,
+                                     systime_t start,
+                                     systime_t end) {
+
+  return (bool)(time - start < end - start);
+}
+
+/**
+ * @brief   Checks if the current system time is within the specified time
+ *          window.
+ * @note    When start==end then the function returns always true because the
+ *          whole time range is specified.
+ *
+ * @param[in] start     the start of the time window (inclusive)
+ * @param[in] end       the end of the time window (non inclusive)
+ * @retval true         current time within the specified time window.
+ * @retval false        current time not within the specified time window.
+ *
+ * @xclass
+ */
+static inline bool chVTIsSystemTimeWithinX(systime_t start, systime_t end) {
+
+  chDbgCheckClassI();
+
+  return chVTIsTimeWithinX(chVTGetSystemTimeX(), start, end);
+}
+
+/**
+ * @brief   Checks if the current system time is within the specified time
+ *          window.
+ * @note    When start==end then the function returns always true because the
+ *          whole time range is specified.
+ *
+ * @param[in] start     the start of the time window (inclusive)
+ * @param[in] end       the end of the time window (non inclusive)
+ * @retval true         current time within the specified time window.
+ * @retval false        current time not within the specified time window.
+ *
+ * @api
+ */
+static inline bool chVTIsSystemTimeWithin(systime_t start, systime_t end) {
+
+  return chVTIsTimeWithinX(chVTGetSystemTime(), start, end);
+}
+
+/**
+ * @brief   Returns @p true if the specified timer is armed.
+ * @pre     The timer must have been initialized using @p chVTObjectInit()
+ *          or @p chVTDoSetI().
+ *
+ * @param[in] vtp       the @p virtual_timer_t structure pointer
+ * @return              true if the timer is armed.
+ *
+ * @iclass
+ */
+static inline bool chVTIsArmedI(virtual_timer_t *vtp) {
+
+  chDbgCheckClassI();
+
+  return (bool)(vtp->vt_func != NULL);
+}
+
+/**
+ * @brief   Disables a Virtual Timer.
+ * @note    The timer is first checked and disabled only if armed.
+ * @pre     The timer must have been initialized using @p chVTObjectInit()
+ *          or @p chVTDoSetI().
+ *
+ * @param[in] vtp       the @p virtual_timer_t structure pointer
+ *
+ * @iclass
+ */
+static inline void chVTResetI(virtual_timer_t *vtp) {
+
+  if (chVTIsArmedI(vtp))
+    chVTDoResetI(vtp);
+}
+
+/**
+ * @brief   Disables a Virtual Timer.
+ * @note    The timer is first checked and disabled only if armed.
+ * @pre     The timer must have been initialized using @p chVTObjectInit()
+ *          or @p chVTDoSetI().
+ *
+ * @param[in] vtp       the @p virtual_timer_t structure pointer
+ *
+ * @api
+ */
+static inline void chVTReset(virtual_timer_t *vtp) {
+
+  chSysLock();
+  chVTResetI(vtp);
+  chSysUnlock();
+}
+
+/**
+ * @brief   Enables a virtual timer.
+ * @details If the virtual timer was already enabled then it is re-enabled
+ *          using the new parameters.
+ * @pre     The timer must have been initialized using @p chVTObjectInit()
+ *          or @p chVTDoSetI().
+ *
+ * @param[in] vtp       the @p virtual_timer_t structure pointer
+ * @param[in] delay     the number of ticks before the operation timeouts, the
+ *                      special values are handled as follow:
+ *                      - @a TIME_INFINITE is allowed but interpreted as a
+ *                        normal time specification.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ * @param[in] vtfunc    the timer callback function. After invoking the
+ *                      callback the timer is disabled and the structure can
+ *                      be disposed or reused.
+ * @param[in] par       a parameter that will be passed to the callback
+ *                      function
+ *
+ * @iclass
+ */
+static inline void chVTSetI(virtual_timer_t *vtp, systime_t delay,
+                            vtfunc_t vtfunc, void *par) {
+
+  chVTResetI(vtp);
+  chVTDoSetI(vtp, delay, vtfunc, par);
+}
+
+/**
+ * @brief   Enables a virtual timer.
+ * @details If the virtual timer was already enabled then it is re-enabled
+ *          using the new parameters.
+ * @pre     The timer must have been initialized using @p chVTObjectInit()
+ *          or @p chVTDoSetI().
+ *
+ * @param[in] vtp       the @p virtual_timer_t structure pointer
+ * @param[in] delay     the number of ticks before the operation timeouts, the
+ *                      special values are handled as follow:
+ *                      - @a TIME_INFINITE is allowed but interpreted as a
+ *                        normal time specification.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ * @param[in] vtfunc    the timer callback function. After invoking the
+ *                      callback the timer is disabled and the structure can
+ *                      be disposed or reused.
+ * @param[in] par       a parameter that will be passed to the callback
+ *                      function
+ *
+ * @api
+ */
+static inline void chVTSet(virtual_timer_t *vtp, systime_t delay,
+                           vtfunc_t vtfunc, void *par) {
+
+  chSysLock();
+  chVTSetI(vtp, delay, vtfunc, par);
+  chSysUnlock();
+}
+
+/**
+ * @brief   Virtual timers ticker.
+ * @note    The system lock is released before entering the callback and
+ *          re-acquired immediately after. It is callback's responsibility
+ *          to acquire the lock if needed. This is done in order to reduce
+ *          interrupts jitter when many timers are in use.
+ *
+ * @iclass
+ */
+static inline void chVTDoTickI(void) {
+
+  chDbgCheckClassI();
+
+#if CH_CFG_ST_TIMEDELTA == 0
+  ch.vtlist.vt_systime++;
+  if (&ch.vtlist != (virtual_timers_list_t *)ch.vtlist.vt_next) {
+    virtual_timer_t *vtp;
+
+    --ch.vtlist.vt_next->vt_delta;
+    while (!(vtp = ch.vtlist.vt_next)->vt_delta) {
+      vtfunc_t fn = vtp->vt_func;
+      vtp->vt_func = (vtfunc_t)NULL;
+      vtp->vt_next->vt_prev = (virtual_timer_t *)&ch.vtlist;
+      ch.vtlist.vt_next = vtp->vt_next;
+      chSysUnlockFromISR();
+      fn(vtp->vt_par);
+      chSysLockFromISR();
+    }
+  }
+#else /* CH_CFG_ST_TIMEDELTA > 0 */
+  virtual_timer_t *vtp;
+  systime_t now = chVTGetSystemTimeX();
+  systime_t delta = now - ch.vtlist.vt_lasttime;
+
+  while ((vtp = ch.vtlist.vt_next)->vt_delta <= delta) {
+    delta -= vtp->vt_delta;
+    ch.vtlist.vt_lasttime += vtp->vt_delta;
+    vtfunc_t fn = vtp->vt_func;
+    vtp->vt_func = (vtfunc_t)NULL;
+    vtp->vt_next->vt_prev = (virtual_timer_t *)&ch.vtlist;
+    ch.vtlist.vt_next = vtp->vt_next;
+    chSysUnlockFromISR();
+    fn(vtp->vt_par);
+    chSysLockFromISR();
+  }
+  if (&ch.vtlist == (virtual_timers_list_t *)ch.vtlist.vt_next) {
+    /* The list is empty, no tick event needed so the alarm timer
+       is stopped.*/
+    port_timer_stop_alarm();
+  }
+  else {
+    /* Updating the alarm to the next deadline.*/
+    port_timer_set_alarm(now + vtp->vt_delta);
+  }
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+}
+
+#endif /* _CHVT_H_ */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/chcore.c b/os/rt/ports/ARMCMx/chcore.c
new file mode 100644
index 000000000..c66ce160c
--- /dev/null
+++ b/os/rt/ports/ARMCMx/chcore.c
@@ -0,0 +1,55 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/chcore.c
+ * @brief   ARM Cortex-Mx port code.
+ *
+ * @addtogroup ARMCMx_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/chcore.h b/os/rt/ports/ARMCMx/chcore.h
new file mode 100644
index 000000000..0e5ed6933
--- /dev/null
+++ b/os/rt/ports/ARMCMx/chcore.h
@@ -0,0 +1,255 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/chcore.h
+ * @brief   ARM Cortex-Mx port macros and structures.
+ *
+ * @addtogroup ARMCMx_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_H_
+#define _CHCORE_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief   Macro defining a generic ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM
+
+/* The following code is not processed when the file is included from an
+   asm module because those intrinsic macros are not necessarily defined
+   by the assembler too.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME              "GCC " __VERSION__
+
+#elif defined(__ICCARM__)
+#define PORT_COMPILER_NAME              "IAR"
+
+#elif defined(__CC_ARM)
+#define PORT_COMPILER_NAME              "RVCT"
+
+#else
+#error "unsupported compiler"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/** @} */
+
+/**
+ * @name    Cortex-M variants
+ * @{
+ */
+#define CORTEX_M0                       0   /**< @brief Cortex-M0 variant.  */
+#define CORTEX_M0PLUS                   1   /**< @brief Cortex-M0+ variant. */
+#define CORTEX_M1                       2   /**< @brief Cortex-M1 variant.  */
+#define CORTEX_M3                       3   /**< @brief Cortex-M3 variant.  */
+#define CORTEX_M4                       4   /**< @brief Cortex-M4 variant.  */
+/** @} */
+
+/* Inclusion of the Cortex-Mx implementation specific parameters.*/
+#include "cmparams.h"
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ *          @p chcore_timer.h, if this option is enabled then the file
+ *          @p chcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER              FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/*
+ * Inclusion of the appropriate CMSIS header for the selected device.
+ */
+#if CORTEX_MODEL == CORTEX_M0
+#include "core_cm0.h"
+#elif CORTEX_MODEL == CORTEX_M0PLUS
+#include "core_cm0plus.h"
+#elif CORTEX_MODEL == CORTEX_M3
+#include "core_cm3.h"
+#elif CORTEX_MODEL == CORTEX_M4
+#include "core_cm4.h"
+#else
+#error "unknown or unsupported Cortex-M model"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Type of system time.
+ */
+#if (CH_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
+typedef uint32_t systime_t;
+#else
+typedef uint16_t systime_t;
+#endif
+
+/**
+ * @brief   Type of a generic ARM register.
+ */
+typedef void *regarm_t;
+
+/**
+ * @brief   Type of stack and memory alignment enforcement.
+ * @note    In this architecture the stack alignment is enforced to 64 bits,
+ *          32 bits alignment is supported by hardware but deprecated by ARM,
+ *          the implementation choice is to not offer the option.
+ */
+typedef uint64_t stkalign_t;
+
+/* The following declarations are there just for Doxygen documentation, the
+   real declarations are inside the sub-headers being specific for the
+   sub-architectures.*/
+#if defined(__DOXYGEN__)
+/**
+ * @brief   Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ *          preemption-capable interrupt handler.
+ * @note    It is implemented to match the Cortex-Mx exception context.
+ */
+struct port_extctx {};
+
+/**
+ * @brief   System saved context.
+ * @details This structure represents the inner stack frame during a context
+ *          switching.
+ */
+struct port_intctx {};
+#endif /* defined(__DOXYGEN__) */
+
+/**
+ * @brief   Platform dependent part of the @p thread_t structure.
+ * @details In this port the structure just holds a pointer to the
+ *          @p port_intctx structure representing the stack pointer
+ *          at context switch time.
+ */
+struct context {
+  struct port_intctx *r13;
+};
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Total priority levels.
+ */
+#define CORTEX_PRIORITY_LEVELS          (1 << CORTEX_PRIORITY_BITS)
+
+/**
+ * @brief   Minimum priority level.
+ * @details This minimum priority level is calculated from the number of
+ *          priority bits supported by the specific Cortex-Mx implementation.
+ */
+#define CORTEX_MINIMUM_PRIORITY         (CORTEX_PRIORITY_LEVELS - 1)
+
+/**
+ * @brief   Maximum priority level.
+ * @details The maximum allowed priority level is always zero.
+ */
+#define CORTEX_MAXIMUM_PRIORITY         0
+
+/**
+ * @brief   Priority level verification macro.
+ */
+#define CORTEX_IS_VALID_PRIORITY(n)                                         \
+  (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
+
+/**
+ * @brief   Priority level verification macro.
+ */
+#define CORTEX_IS_VALID_KERNEL_PRIORITY(n)                                  \
+  (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
+
+/**
+ * @brief   Priority level to priority mask conversion macro.
+ */
+#define CORTEX_PRIO_MASK(n)                                                 \
+  ((n) << (8 - CORTEX_PRIORITY_BITS))
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/* Includes the sub-architecture-specific part.*/
+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M0PLUS) ||       \
+    (CORTEX_MODEL == CORTEX_M1)
+#include "chcore_v6m.h"
+#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
+#include "chcore_v7m.h"
+#endif
+
+#if !defined(_FROM_ASM_)
+
+#if CH_CFG_ST_TIMEDELTA > 0
+#if !PORT_USE_ALT_TIMER
+#include "chcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "chcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CHCORE_H_ */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/chcore_timer.h b/os/rt/ports/ARMCMx/chcore_timer.h
new file mode 100644
index 000000000..8df7ac97e
--- /dev/null
+++ b/os/rt/ports/ARMCMx/chcore_timer.h
@@ -0,0 +1,125 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chcore_timer.h
+ * @brief   System timer header file.
+ *
+ * @addtogroup ARMCMx_TIMER
+ * @{
+ */
+
+#ifndef _CHCORE_TIMER_H_
+#define _CHCORE_TIMER_H_
+
+/* This is the only header in the HAL designed to be include-able alone.*/
+#include "st.h"
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Starts the alarm.
+ * @note    Makes sure that no spurious alarms are triggered after
+ *          this call.
+ *
+ * @param[in] time      the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_start_alarm(systime_t time) {
+
+  stStartAlarm(time);
+}
+
+/**
+ * @brief   Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void port_timer_stop_alarm(void) {
+
+  stStopAlarm();
+}
+
+/**
+ * @brief   Sets the alarm time.
+ *
+ * @param[in] time      the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_set_alarm(systime_t time) {
+
+  stSetAlarm(time);
+}
+
+/**
+ * @brief   Returns the system time.
+ *
+ * @return              The system time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_time(void) {
+
+  return stGetCounter();
+}
+
+/**
+ * @brief   Returns the current alarm time.
+ *
+ * @return              The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_alarm(void) {
+
+  return stGetAlarm();
+}
+
+#endif /* _CHCORE_TIMER_H_ */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/chcore_v6m.c b/os/rt/ports/ARMCMx/chcore_v6m.c
new file mode 100644
index 000000000..9548c2a8e
--- /dev/null
+++ b/os/rt/ports/ARMCMx/chcore_v6m.c
@@ -0,0 +1,144 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chcore_v6m.c
+ * @brief   ARMv6-M architecture port code.
+ *
+ * @addtogroup ARMCMx_V6M_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+/**
+ * @brief   NMI vector.
+ * @details The NMI vector is used for exception mode re-entering after a
+ *          context switch.
+ */
+void NMI_Handler(void) {
+
+  /* The port_extctx structure is pointed by the PSP register.*/
+  struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+  /* Discarding the current exception context and positioning the stack to
+     point to the real one.*/
+  ctxp++;
+
+  /* Writing back the modified PSP value.*/
+  __set_PSP((uint32_t)ctxp);
+
+  /* Restoring the normal interrupts status.*/
+  port_unlock_from_isr();
+}
+#endif /* !CORTEX_ALTERNATE_SWITCH */
+
+#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+/**
+ * @brief   PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ *          context switch.
+ */
+void PendSV_Handler(void) {
+
+  /* The port_extctx structure is pointed by the PSP register.*/
+  struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+  /* Discarding the current exception context and positioning the stack to
+     point to the real one.*/
+  ctxp++;
+
+  /* Writing back the modified PSP value.*/
+  __set_PSP((uint32_t)ctxp);
+}
+#endif /* CORTEX_ALTERNATE_SWITCH */
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   IRQ epilogue code.
+ *
+ * @param[in] lr        value of the @p LR register on ISR entry
+ */
+void _port_irq_epilogue(regarm_t lr) {
+
+  if (lr != (regarm_t)0xFFFFFFF1) {
+    struct port_extctx *ctxp;
+
+    port_lock_from_isr();
+
+    /* The extctx structure is pointed by the PSP register.*/
+    ctxp = (struct port_extctx *)__get_PSP();
+
+    /* Adding an artificial exception return context, there is no need to
+       populate it fully.*/
+    ctxp--;
+
+    /* Writing back the modified PSP value.*/
+    __set_PSP((uint32_t)ctxp);
+
+    /* Setting up a fake XPSR register value.*/
+    ctxp->xpsr = (regarm_t)0x01000000;
+
+    /* The exit sequence is different depending on if a preemption is
+       required or not.*/
+    if (chSchIsPreemptionRequired()) {
+      /* Preemption is required we need to enforce a context switch.*/
+      ctxp->pc = (regarm_t)_port_switch_from_isr;
+    }
+    else {
+      /* Preemption not required, we just need to exit the exception
+         atomically.*/
+      ctxp->pc = (regarm_t)_port_exit_from_isr;
+    }
+
+    /* Note, returning without unlocking is intentional, this is done in
+       order to keep the rest of the context switch atomic.*/
+  }
+}
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/chcore_v6m.h b/os/rt/ports/ARMCMx/chcore_v6m.h
new file mode 100644
index 000000000..7e74df03f
--- /dev/null
+++ b/os/rt/ports/ARMCMx/chcore_v6m.h
@@ -0,0 +1,406 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chcore_v6m.h
+ * @brief   ARMv6-M architecture port macros and structures.
+ *
+ * @addtogroup ARMCMx_V6M_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_V6M_H_
+#define _CHCORE_V6M_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Architecture and Compiler
+ * @{
+ */
+#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
+/**
+ * @brief   Macro defining the specific ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM_v6M
+
+/**
+ * @brief   Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME          "ARMv6-M"
+
+/**
+ * @brief   Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME          "Cortex-M0"
+
+#elif (CORTEX_MODEL == CORTEX_M0PLUS)
+#define PORT_ARCHITECTURE_ARM_v6M
+#define PORT_ARCHITECTURE_NAME          "ARMv6-M"
+#define PORT_CORE_VARIANT_NAME          "Cortex-M0+"
+#endif
+
+/**
+ * @brief   Port-specific information string.
+ */
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+#define PORT_INFO                       "Preemption through NMI"
+#else
+#define PORT_INFO                       "Preemption through PendSV"
+#endif
+/** @} */
+
+/**
+ * @brief   This port does not support a realtime counter.
+ */
+#define PORT_SUPPORTS_RT                FALSE
+
+/**
+ * @brief   PendSV priority level.
+ * @note    This priority is enforced to be equal to @p 0,
+ *          this handler always has the highest priority that cannot preempt
+ *          the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV          0
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ *          the idle thread should take no more space than those reserved
+ *          by @p PORT_INT_REQUIRED_STACK.
+ * @note    In this port it is set to 16 because the idle thread does have
+ *          a stack frame when compiling without optimizations. You may
+ *          reduce this value to zero when compiling with optimizations.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
+#define PORT_IDLE_THREAD_STACK_SIZE     16
+#endif
+
+/**
+ * @brief   Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ *          area size.
+ * @note    In this port this value is conservatively set to 64 because the
+ *          function @p chSchDoReschedule() can have a stack frame, especially
+ *          with compiler optimizations disabled. The value can be reduced
+ *          when compiler optimizations are enabled.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK)
+#define PORT_INT_REQUIRED_STACK         64
+#endif
+
+/**
+ * @brief   Enables the use of the WFI instruction in the idle thread loop.
+ */
+#if !defined(CORTEX_ENABLE_WFI_IDLE)
+#define CORTEX_ENABLE_WFI_IDLE          FALSE
+#endif
+
+/**
+ * @brief   Alternate preemption method.
+ * @details Activating this option will make the Kernel use the PendSV
+ *          handler for preemption instead of the NMI handler.
+ */
+#ifndef CORTEX_ALTERNATE_SWITCH
+#define CORTEX_ALTERNATE_SWITCH         FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/**
+ * @brief   Maximum usable priority for normal ISRs.
+ */
+#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+#define CORTEX_MAX_KERNEL_PRIORITY      1
+#else
+#define CORTEX_MAX_KERNEL_PRIORITY      0
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+
+ /* The documentation of the following declarations is in chconf.h in order
+    to not have duplicated structure names into the documentation.*/
+#if !defined(__DOXYGEN__)
+struct port_extctx {
+  regarm_t      r0;
+  regarm_t      r1;
+  regarm_t      r2;
+  regarm_t      r3;
+  regarm_t      r12;
+  regarm_t      lr_thd;
+  regarm_t      pc;
+  regarm_t      xpsr;
+};
+
+struct port_intctx {
+  regarm_t      r8;
+  regarm_t      r9;
+  regarm_t      r10;
+  regarm_t      r11;
+  regarm_t      r4;
+  regarm_t      r5;
+  regarm_t      r6;
+  regarm_t      r7;
+  regarm_t      lr;
+};
+#endif /* !defined(__DOXYGEN__) */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ *          by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) {                 \
+  (tp)->p_ctx.r13 = (struct port_intctx *)((uint8_t *)(workspace) +         \
+                                           (wsize) -                        \
+                                           sizeof(struct port_intctx));     \
+  (tp)->p_ctx.r13->r4 = (regarm_t)(pf);                                     \
+  (tp)->p_ctx.r13->r5 = (regarm_t)(arg);                                    \
+  (tp)->p_ctx.r13->lr = (regarm_t)(_port_thread_start);                     \
+}
+
+/**
+ * @brief   Computes the thread working area global size.
+ * @note    There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) +                       \
+                         sizeof(struct port_extctx) +                       \
+                         (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_IRQ_PROLOGUE()                                                 \
+  regarm_t _saved_lr = (regarm_t)__builtin_return_address(0)
+#elif defined(__ICCARM__)
+#define PORT_IRQ_PROLOGUE()                                                 \
+  regarm_t _saved_lr = (regarm_t)__get_LR()
+#elif defined(__CC_ARM)
+#define PORT_IRQ_PROLOGUE()                                                 \
+  regarm_t _saved_lr = (regarm_t)__return_address()
+#endif
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Fast IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ */
+#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) {                                             \
+  struct port_intctx *r13 = (struct port_intctx *)__get_PSP();              \
+  if ((stkalign_t *)(r13 - 1) < (otp)->p_stklimit)                          \
+    chSysHalt("stack overflow");                                            \
+  _port_switch(ntp, otp);                                                   \
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _port_irq_epilogue(regarm_t lr);
+  void _port_switch(thread_t *ntp, thread_t *otp);
+  void _port_thread_start(void);
+  void _port_switch_from_isr(void);
+  void _port_exit_from_isr(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+  NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
+}
+
+/**
+ * @brief   Returns a word encoding the current interrupts status.
+ *
+ * @return              The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+  return __get_PRIMASK();
+}
+
+/**
+ * @brief   Checks the interrupt status.
+ *
+ * @param[in] sts       the interrupt status word
+ *
+ * @return              The interrupt status.
+ * @retvel false        the word specified a disabled interrupts status.
+ * @retvel true         the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+  return (sts & 1) == 0;
+}
+
+/**
+ * @brief   Determines the current execution context.
+ *
+ * @return              The execution context.
+ * @retval false        not running in ISR mode.
+ * @retval true         running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+  return (bool)((__get_IPSR() & 0x1FF) != 0);
+}
+
+/**
+ * @brief   Kernel-lock action.
+ * @details In this port this function disables interrupts globally.
+ */
+static inline void port_lock(void) {
+
+  __disable_irq();
+}
+
+/**
+ * @brief   Kernel-unlock action.
+ * @details In this port this function enables interrupts globally.
+ */
+static inline void port_unlock(void) {
+
+  __enable_irq();
+}
+
+/**
+ * @brief   Kernel-lock action from an interrupt handler.
+ * @details In this port this function disables interrupts globally.
+ * @note    Same as @p port_lock() in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+  port_lock();
+}
+
+/**
+ * @brief   Kernel-unlock action from an interrupt handler.
+ * @details In this port this function enables interrupts globally.
+ * @note    Same as @p port_lock() in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+  port_unlock();
+}
+
+/**
+ * @brief   Disables all the interrupt sources.
+ */
+static inline void port_disable(void) {
+
+  __disable_irq();
+}
+
+/**
+ * @brief   Disables the interrupt sources below kernel-level priority.
+ */
+static inline void port_suspend(void) {
+
+  __disable_irq();
+}
+
+/**
+ * @brief   Enables all the interrupt sources.
+ */
+static inline void port_enable(void) {
+
+  __enable_irq();
+}
+
+/**
+ * @brief   Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ *          The simplest implementation is an empty function or macro but this
+ *          would not take advantage of architecture-specific power saving
+ *          modes.
+ * @note    Implemented as an inlined @p WFI instruction.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+#if CORTEX_ENABLE_WFI_IDLE
+  __WFI();
+#endif
+}
+
+#endif /* _FROM_ASM_ */
+
+#endif /* _CHCORE_V6M_H_ */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/chcore_v7m.c b/os/rt/ports/ARMCMx/chcore_v7m.c
new file mode 100644
index 000000000..29add3fb1
--- /dev/null
+++ b/os/rt/ports/ARMCMx/chcore_v7m.c
@@ -0,0 +1,174 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chcore_v7m.c
+ * @brief   ARMv7-M architecture port code.
+ *
+ * @addtogroup ARMCMx_V7M_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+/**
+ * @brief   SVC vector.
+ * @details The SVC vector is used for exception mode re-entering after a
+ *          context switch.
+ * @note    The PendSV vector is only used in advanced kernel mode.
+ */
+void SVC_Handler(void) {
+
+  /* The port_extctx structure is pointed by the PSP register.*/
+  struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+  /* Discarding the current exception context and positioning the stack to
+     point to the real one.*/
+  ctxp++;
+
+#if CORTEX_USE_FPU
+  /* Restoring the special register FPCCR.*/
+  FPU->FPCCR = (uint32_t)ctxp->fpccr;
+  FPU->FPCAR = FPU->FPCAR + sizeof (struct port_extctx);
+#endif
+
+  /* Writing back the modified PSP value.*/
+  __set_PSP((uint32_t)ctxp);
+
+  /* Restoring the normal interrupts status.*/
+  port_unlock_from_isr();
+}
+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
+
+#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+/**
+ * @brief   PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ *          context switch.
+ * @note    The PendSV vector is only used in compact kernel mode.
+ */
+void PendSV_Handler(void) {
+
+  /* The port_extctx structure is pointed by the PSP register.*/
+  struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+  /* Discarding the current exception context and positioning the stack to
+     point to the real one.*/
+  ctxp++;
+
+#if CORTEX_USE_FPU
+  /* Restoring the special register FPCCR.*/
+  FPU->FPCCR = (uint32_t)ctxp->fpccr;
+  FPU->FPCAR = FPU->FPCAR + sizeof (struct port_extctx);
+#endif
+
+  /* Writing back the modified PSP value.*/
+  __set_PSP((uint32_t)ctxp);
+}
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Exception exit redirection to _port_switch_from_isr().
+ */
+void _port_irq_epilogue(void) {
+
+  port_lock_from_isr();
+  if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0) {
+
+    /* The port_extctx structure is pointed by the PSP register.*/
+    struct port_extctx *ctxp = (struct port_extctx *)__get_PSP();
+
+    /* Adding an artificial exception return context, there is no need to
+       populate it fully.*/
+    ctxp--;
+
+    /* Writing back the modified PSP value.*/
+    __set_PSP((uint32_t)ctxp);
+
+    /* Setting up a fake XPSR register value.*/
+    ctxp->xpsr = (regarm_t)0x01000000;
+
+    /* The exit sequence is different depending on if a preemption is
+       required or not.*/
+    if (chSchIsPreemptionRequired()) {
+      /* Preemption is required we need to enforce a context switch.*/
+      ctxp->pc = (regarm_t)_port_switch_from_isr;
+#if CORTEX_USE_FPU
+      /* Enforcing a lazy FPU state save by accessing the FPCSR register.*/
+      (void) __get_FPSCR();
+#endif
+    }
+    else {
+      /* Preemption not required, we just need to exit the exception
+         atomically.*/
+      ctxp->pc = (regarm_t)_port_exit_from_isr;
+    }
+
+#if CORTEX_USE_FPU
+    {
+      uint32_t fpccr;
+
+      /* Saving the special register SCB_FPCCR into the reserved offset of
+         the Cortex-M4 exception frame.*/
+      (ctxp + 1)->fpccr = (regarm_t)(fpccr = FPU->FPCCR);
+
+      /* Now the FPCCR is modified in order to not restore the FPU status
+         from the artificial return context.*/
+      FPU->FPCCR = fpccr | FPU_FPCCR_LSPACT_Msk;
+    }
+#endif
+
+    /* Note, returning without unlocking is intentional, this is done in
+       order to keep the rest of the context switch atomic.*/
+    return;
+  }
+  port_unlock_from_isr();
+}
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/chcore_v7m.h b/os/rt/ports/ARMCMx/chcore_v7m.h
new file mode 100644
index 000000000..db8d71d92
--- /dev/null
+++ b/os/rt/ports/ARMCMx/chcore_v7m.h
@@ -0,0 +1,555 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chcore_v7m.h
+ * @brief   ARMv7-M architecture port macros and structures.
+ *
+ * @addtogroup ARMCMx_V7M_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_V7M_H_
+#define _CHCORE_V7M_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Architecture and Compiler
+ * @{
+ */
+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
+/**
+ * @brief   Macro defining the specific ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM_v7M
+
+/**
+ * @brief   Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME          "ARMv7-M"
+
+/**
+ * @brief   Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME          "Cortex-M3"
+
+#elif (CORTEX_MODEL == CORTEX_M4)
+#define PORT_ARCHITECTURE_ARM_v7ME
+#define PORT_ARCHITECTURE_NAME          "ARMv7-ME"
+#if CORTEX_USE_FPU
+#define PORT_CORE_VARIANT_NAME          "Cortex-M4F"
+#else
+#define PORT_CORE_VARIANT_NAME          "Cortex-M4"
+#endif
+#endif
+
+/**
+ * @brief   Port-specific information string.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define PORT_INFO                       "Advanced kernel mode"
+#else
+#define PORT_INFO                       "Compact kernel mode"
+#endif
+/** @} */
+
+/**
+ * @brief   This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT                TRUE
+
+/**
+ * @brief   Disabled value for BASEPRI register.
+ */
+#define CORTEX_BASEPRI_DISABLED         0
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ *          the idle thread should take no more space than those reserved
+ *          by @p PORT_INT_REQUIRED_STACK.
+ * @note    In this port it is set to 16 because the idle thread does have
+ *          a stack frame when compiling without optimizations. You may
+ *          reduce this value to zero when compiling with optimizations.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE     16
+#endif
+
+/**
+ * @brief   Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ *          area size.
+ * @note    In this port this value is conservatively set to 64 because the
+ *          function @p chSchDoReschedule() can have a stack frame, especially
+ *          with compiler optimizations disabled. The value can be reduced
+ *          when compiler optimizations are enabled.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK         64
+#endif
+
+/**
+ * @brief   Enables the use of the WFI instruction in the idle thread loop.
+ */
+#if !defined(CORTEX_ENABLE_WFI_IDLE)
+#define CORTEX_ENABLE_WFI_IDLE          FALSE
+#endif
+
+/**
+ * @brief   FPU support in context switch.
+ * @details Activating this option activates the FPU support in the kernel.
+ */
+#if !defined(CORTEX_USE_FPU)
+#define CORTEX_USE_FPU                  CORTEX_HAS_FPU
+#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
+/* This setting requires an FPU presence check in case it is externally
+   redefined.*/
+#error "the selected core does not have an FPU"
+#endif
+
+/**
+ * @brief   Simplified priority handling flag.
+ * @details Activating this option makes the Kernel work in compact mode.
+ *          In compact mode interrupts are disabled globally instead of
+ *          raising the priority mask to some intermediate level.
+ */
+#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
+#define CORTEX_SIMPLIFIED_PRIORITY      FALSE
+#endif
+
+/**
+ * @brief   SVCALL handler priority.
+ * @note    The default SVCALL handler priority is defaulted to
+ *          @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
+ *          @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
+ *          priority level.
+ */
+#if !defined(CORTEX_PRIORITY_SVCALL)
+#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1)
+#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
+/* If it is externally redefined then better perform a validity check on it.*/
+#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
+#endif
+
+/**
+ * @brief   NVIC VTOR initialization expression.
+ */
+#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
+#define CORTEX_VTOR_INIT                0x00000000
+#endif
+
+/**
+ * @brief   NVIC PRIGROUP initialization expression.
+ * @details The default assigns all available priority bits as preemption
+ *          priority with no sub-priority.
+ */
+#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
+#define CORTEX_PRIGROUP_INIT            (7 - CORTEX_PRIORITY_BITS)
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+/**
+ * @brief   Maximum usable priority for normal ISRs.
+ */
+#define CORTEX_MAX_KERNEL_PRIORITY      (CORTEX_PRIORITY_SVCALL + 1)
+
+/**
+ * @brief   BASEPRI level within kernel lock.
+ */
+#define CORTEX_BASEPRI_KERNEL                                               \
+  CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
+#else
+
+#define CORTEX_MAX_KERNEL_PRIORITY      0
+#endif
+
+/**
+ * @brief   PendSV priority level.
+ * @note    This priority is enforced to be equal to
+ *          @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
+ *          highest priority that cannot preempt the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV          CORTEX_MAX_KERNEL_PRIORITY
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* The documentation of the following declarations is in chconf.h in order
+   to not have duplicated structure names into the documentation.*/
+#if !defined(__DOXYGEN__)
+struct port_extctx {
+  regarm_t      r0;
+  regarm_t      r1;
+  regarm_t      r2;
+  regarm_t      r3;
+  regarm_t      r12;
+  regarm_t      lr_thd;
+  regarm_t      pc;
+  regarm_t      xpsr;
+#if CORTEX_USE_FPU
+  regarm_t      s0;
+  regarm_t      s1;
+  regarm_t      s2;
+  regarm_t      s3;
+  regarm_t      s4;
+  regarm_t      s5;
+  regarm_t      s6;
+  regarm_t      s7;
+  regarm_t      s8;
+  regarm_t      s9;
+  regarm_t      s10;
+  regarm_t      s11;
+  regarm_t      s12;
+  regarm_t      s13;
+  regarm_t      s14;
+  regarm_t      s15;
+  regarm_t      fpscr;
+  regarm_t      fpccr;
+#endif /* CORTEX_USE_FPU */
+};
+
+struct port_intctx {
+#if CORTEX_USE_FPU
+  regarm_t      s16;
+  regarm_t      s17;
+  regarm_t      s18;
+  regarm_t      s19;
+  regarm_t      s20;
+  regarm_t      s21;
+  regarm_t      s22;
+  regarm_t      s23;
+  regarm_t      s24;
+  regarm_t      s25;
+  regarm_t      s26;
+  regarm_t      s27;
+  regarm_t      s28;
+  regarm_t      s29;
+  regarm_t      s30;
+  regarm_t      s31;
+#endif /* CORTEX_USE_FPU */
+  regarm_t      r4;
+  regarm_t      r5;
+  regarm_t      r6;
+  regarm_t      r7;
+  regarm_t      r8;
+  regarm_t      r9;
+  regarm_t      r10;
+  regarm_t      r11;
+  regarm_t      lr;
+};
+#endif /* !defined(__DOXYGEN__) */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ *          by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) {                 \
+  (tp)->p_ctx.r13 = (struct port_intctx *)((uint8_t *)(workspace) +         \
+                                           (wsize) -                        \
+                                           sizeof(struct port_intctx));     \
+  (tp)->p_ctx.r13->r4 = (regarm_t)(pf);                                     \
+  (tp)->p_ctx.r13->r5 = (regarm_t)(arg);                                    \
+  (tp)->p_ctx.r13->lr = (regarm_t)(_port_thread_start);                     \
+}
+
+/**
+ * @brief   Computes the thread working area global size.
+ * @note    There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) +                       \
+                         sizeof(struct port_extctx) +                       \
+                         (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Fast IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ */
+#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) {                                             \
+  struct port_intctx *r13 = (struct port_intctx *)__get_PSP();              \
+  if ((stkalign_t *)(r13 - 1) < (otp)->p_stklimit)                          \
+    chSysHalt("stack overflow");                                            \
+  _port_switch(ntp, otp);                                                   \
+}
+#endif
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _port_irq_epilogue(void);
+  void _port_switch(thread_t *ntp, thread_t *otp);
+  void _port_thread_start(void);
+  void _port_switch_from_isr(void);
+  void _port_exit_from_isr(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+  /* Initialization of the vector table and priority related settings.*/
+  SCB->VTOR = CORTEX_VTOR_INIT;
+
+  /* Initializing priority grouping.*/
+  NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
+
+  /* DWT cycle counter enable.*/
+  CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+  DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+
+  /* Initialization of the system vectors used by the port.*/
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);
+#endif
+  NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
+}
+
+/**
+ * @brief   Returns a word encoding the current interrupts status.
+ *
+ * @return              The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+  uint32_t sts;
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  sts = __get_BASEPRI();
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+  sts = __get_PRIMASK();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+  return sts;
+}
+
+/**
+ * @brief   Checks the interrupt status.
+ *
+ * @param[in] sts       the interrupt status word
+ *
+ * @return              The interrupt status.
+ * @retvel false        the word specified a disabled interrupts status.
+ * @retvel true         the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  return sts == CORTEX_BASEPRI_DISABLED;
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+  return (sts & 1) == 0;
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief   Determines the current execution context.
+ *
+ * @return              The execution context.
+ * @retval false        not running in ISR mode.
+ * @retval true         running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+
+  return (bool)((__get_IPSR() & 0x1FF) != 0);
+}
+
+/**
+ * @brief   Kernel-lock action.
+ * @details In this port this function raises the base priority to kernel
+ *          level.
+ */
+static inline void port_lock(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+  __disable_irq();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief   Kernel-unlock action.
+ * @details In this port this function lowers the base priority to user
+ *          level.
+ */
+static inline void port_unlock(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY
+  __set_BASEPRI(CORTEX_BASEPRI_DISABLED);
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+  __enable_irq();
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+}
+
+/**
+ * @brief   Kernel-lock action from an interrupt handler.
+ * @details In this port this function raises the base priority to kernel
+ *          level.
+ * @note    Same as @p port_lock() in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+  port_lock();
+}
+
+/**
+ * @brief   Kernel-unlock action from an interrupt handler.
+ * @details In this port this function lowers the base priority to user
+ *          level.
+ * @note    Same as @p port_unlock() in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+  port_unlock();
+}
+
+/**
+ * @brief   Disables all the interrupt sources.
+ * @note    In this port it disables all the interrupt sources by raising
+ *          the priority mask to level 0.
+ */
+static inline void port_disable(void) {
+
+  __disable_irq();
+}
+
+/**
+ * @brief   Disables the interrupt sources below kernel-level priority.
+ * @note    Interrupt sources above kernel level remains enabled.
+ * @note    In this port it raises/lowers the base priority to kernel level.
+ */
+static inline void port_suspend(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);
+  __enable_irq();
+#else
+  __disable_irq();
+#endif
+}
+
+/**
+ * @brief   Enables all the interrupt sources.
+ * @note    In this port it lowers the base priority to user level.
+ */
+static inline void port_enable(void) {
+
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+  __set_BASEPRI(CORTEX_BASEPRI_DISABLED);
+#endif
+  __enable_irq();
+}
+
+/**
+ * @brief   Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ *          The simplest implementation is an empty function or macro but this
+ *          would not take advantage of architecture-specific power saving
+ *          modes.
+ * @note    Implemented as an inlined @p WFI instruction.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+#if CORTEX_ENABLE_WFI_IDLE
+  __WFI();
+#endif
+}
+
+/**
+ * @brief   Returns the current value of the realtime counter.
+ *
+ * @return              The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+  return DWT->CYCCNT;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CHCORE_V7M_H_ */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s
new file mode 100644
index 000000000..f745d82e6
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s
@@ -0,0 +1,140 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    compilers/GCC/chcoreasm_v6m.s
+ * @brief   ARMv6-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE   0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE    1
+#endif
+
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+                .set    CONTEXT_OFFSET, 12
+                .set    SCB_ICSR, 0xE000ED04
+                .set    ICSR_PENDSVSET, 0x10000000
+                .set    ICSR_NMIPENDSET, 0x80000000
+
+                .cpu    cortex-m0
+                .fpu    softvfp
+
+                .thumb
+                .text
+
+/*--------------------------------------------------------------------------*
+ * Performs a context switch between two threads.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_switch
+_port_switch:
+                push    {r4, r5, r6, r7, lr}
+                mov     r4, r8
+                mov     r5, r9
+                mov     r6, r10
+                mov     r7, r11
+                push    {r4, r5, r6, r7}
+                mov r3, sp
+                str r3, [r1, #CONTEXT_OFFSET]
+                ldr r3, [r0, #CONTEXT_OFFSET]
+                mov sp, r3
+                pop     {r4, r5, r6, r7}
+                mov     r8, r4
+                mov     r9, r5
+                mov     r10, r6
+                mov     r11, r7
+                pop     {r4, r5, r6, r7, pc}
+
+/*--------------------------------------------------------------------------*
+ * Start a thread by invoking its work function.
+ *
+ * Threads execution starts here, the code leaves the system critical zone
+ * and then jumps into the thread function passed in register R4. The
+ * register R5 contains the thread parameter. The function chThdExit() is
+ * called on thread function return.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_thread_start
+_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+                bl      _stats_stop_measure_crit_thd
+#endif
+                cpsie   i
+                mov     r0, r5
+                blx     r4
+                bl      chThdExit
+
+/*--------------------------------------------------------------------------*
+ * Post-IRQ switch code.
+ *
+ * Exception handlers return here for context switching.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_switch_from_isr
+_port_switch_from_isr:
+#if CH_DBG_STATISTICS
+                bl      _stats_start_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      _dbg_check_lock
+#endif
+                bl      chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+                bl      _stats_stop_measure_crit_thd
+#endif
+                .globl  _port_exit_from_isr
+_port_exit_from_isr:
+                ldr     r2, .L2
+                ldr     r3, .L3
+                str     r3, [r2, #0]
+#if CORTEX_ALTERNATE_SWITCH
+                cpsie   i
+#endif
+.L1:            b       .L1
+
+                .align  2
+.L2:            .word   SCB_ICSR
+#if CORTEX_ALTERNATE_SWITCH
+.L3:            .word   ICSR_PENDSVSET
+#else
+.L3:            .word   ICSR_NMIPENDSET
+#endif
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
new file mode 100644
index 000000000..36567e0b4
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
@@ -0,0 +1,138 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    compilers/GCC/chcoreasm_v7m.s
+ * @brief   ARMv7-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE   0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE    1
+#endif
+
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+                .set    CONTEXT_OFFSET, 12
+                .set    SCB_ICSR, 0xE000ED04
+                .set    ICSR_PENDSVSET, 0x10000000
+
+                .syntax unified
+                .cpu    cortex-m4
+#if CORTEX_USE_FPU
+                .fpu    fpv4-sp-d16
+#else
+                .fpu    softvfp
+#endif
+
+                .thumb
+                .text
+
+/*--------------------------------------------------------------------------*
+ * Performs a context switch between two threads.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_switch
+_port_switch:
+                push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+#if CORTEX_USE_FPU
+                vpush   {s16-s31}
+#endif
+                str     sp, [r1, #CONTEXT_OFFSET]
+                ldr     sp, [r0, #CONTEXT_OFFSET]
+#if CORTEX_USE_FPU
+                vpop    {s16-s31}
+#endif
+                pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+
+/*--------------------------------------------------------------------------*
+ * Start a thread by invoking its work function.
+ *
+ * Threads execution starts here, the code leaves the system critical zone
+ * and then jumps into the thread function passed in register R4. The
+ * register R5 contains the thread parameter. The function chThdExit() is
+ * called on thread function return.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_thread_start
+_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+                bl      _stats_stop_measure_crit_thd
+#endif
+#if !CORTEX_SIMPLIFIED_PRIORITY
+                movs    r3, #0
+                msr     BASEPRI, r3
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+                cpsie   i
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+                mov     r0, r5
+                blx     r4
+                bl      chThdExit
+
+/*--------------------------------------------------------------------------*
+ * Post-IRQ switch code.
+ *
+ * Exception handlers return here for context switching.
+ *--------------------------------------------------------------------------*/
+                .thumb_func
+                .globl  _port_switch_from_isr
+_port_switch_from_isr:
+#if CH_DBG_STATISTICS
+                bl      _stats_start_measure_crit_thd
+#endif
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      _dbg_check_lock
+#endif
+                bl      chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      _dbg_check_unlock
+#endif
+#if CH_DBG_STATISTICS
+                bl      _stats_stop_measure_crit_thd
+#endif
+                .globl  _port_exit_from_isr
+_port_exit_from_isr:
+#if CORTEX_SIMPLIFIED_PRIORITY
+                movw    r3, #:lower16:SCB_ICSR
+                movt    r3, #:upper16:SCB_ICSR
+                mov     r2, ICSR_PENDSVSET
+                str     r2, [r3, #0]
+                cpsie   i
+#else /* !CORTEX_SIMPLIFIED_PRIORITY */
+                svc     #0
+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
+.L1:            b       .L1
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h b/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h
new file mode 100644
index 000000000..e6f7b21e1
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h
@@ -0,0 +1,111 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/compilers/GCC/chtypes.h
+ * @brief   ARM Cortex-Mx port system types.
+ *
+ * @addtogroup ARMCMx_GCC_CORE
+ * @{
+ */
+
+#ifndef _CHTYPES_H_
+#define _CHTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name    Common constants
+ */
+/**
+ * @brief   Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE               0
+#endif
+
+/**
+ * @brief   Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                (!FALSE)
+#endif
+/** @} */
+
+/**
+ * @name    Derived generic types
+ * @{
+ */
+typedef volatile int8_t     vint8_t;        /**< Volatile signed 8 bits.    */
+typedef volatile uint8_t    vuint8_t;       /**< Volatile unsigned 8 bits.  */
+typedef volatile int16_t    vint16_t;       /**< Volatile signed 16 bits.   */
+typedef volatile uint16_t   vuint16_t;      /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t    vint32_t;       /**< Volatile signed 32 bits.   */
+typedef volatile uint32_t   vuint32_t;      /**< Volatile unsigned 32 bits. */
+/** @} */
+
+/**
+ * @name    Kernel types
+ * @{
+ */
+typedef uint32_t            rtcnt_t;        /**< Realtime counter.          */
+typedef uint64_t            rttime_t;       /**< Realtime accumulator.      */
+typedef uint32_t            syssts_t;       /**< System status word.        */
+typedef uint8_t             tmode_t;        /**< Thread flags.              */
+typedef uint8_t             tstate_t;       /**< Thread state.              */
+typedef uint8_t             trefs_t;        /**< Thread references counter. */
+typedef uint8_t             tslices_t;      /**< Thread time slices counter.*/
+typedef uint32_t            tprio_t;        /**< Thread priority.           */
+typedef int32_t             msg_t;          /**< Inter-thread message.      */
+typedef int32_t             eventid_t;      /**< Numeric event identifier.  */
+typedef uint32_t            eventmask_t;    /**< Mask of event identifiers. */
+typedef uint32_t            eventflags_t;   /**< Mask of event flags.       */
+typedef int32_t             cnt_t;          /**< Generic signed counter.    */
+typedef uint32_t            ucnt_t;         /**< Generic unsigned counter.  */
+/** @} */
+
+/**
+ * @brief   ROM constant modifier.
+ * @note    It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief   Makes functions not inlineable.
+ * @note    If the compiler does not support such attribute then the
+ *          realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief   Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) msg_t tname(void *arg)
+
+/**
+ * @brief   Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+#endif /* _CHTYPES_H_ */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f0xx.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f0xx.mk
new file mode 100644
index 000000000..43131fc6b
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f0xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/RT Cortex-M0 STM32F0xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v6m.c
+          
+PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F0xx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk
new file mode 100644
index 000000000..6317c2e0b
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f1xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/RT Cortex-M3 STM32F1xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F1xx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
new file mode 100644
index 000000000..e3d87f411
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/RT Cortex-M4 STM32F30x port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F30x \
+          ${CHIBIOS}/os/rt/ports/ARMCMx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
new file mode 100644
index 000000000..4b38231bb
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/RT Cortex-M4 STM32F37x port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F37x \
+          ${CHIBIOS}/os/rt/ports/ARMCMx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk
new file mode 100644
index 000000000..9d168c2d8
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/RT Cortex-M4 STM32F4xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F4xx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32l1xx.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32l1xx.mk
new file mode 100644
index 000000000..812c0d24c
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32l1xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/RT Cortex-M3 STM32L1xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32L1xx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s b/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s
new file mode 100644
index 000000000..81f61214a
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s
@@ -0,0 +1,130 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    compilers/IAR/chcoreasm_v6m.s
+ * @brief   ARMv6-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_IAR_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE   0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE    1
+#endif
+
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+        MODULE  ?chcoreasm_v6m
+
+        AAPCS INTERWORK, VFP_COMPATIBLE
+        PRESERVE8
+
+CONTEXT_OFFSET  SET     12
+SCB_ICSR        SET     0xE000ED04
+
+        SECTION .text:CODE:NOROOT(2)
+
+        EXTERN  chThdExit
+        EXTERN  chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+        EXTERN  dbg_check_unlock
+        EXTERN  dbg_check_lock
+#endif
+
+        THUMB
+
+/*
+ * Performs a context switch between two threads.
+ */
+        PUBLIC _port_switch
+_port_switch:
+        push    {r4, r5, r6, r7, lr}
+        mov     r4, r8
+        mov     r5, r9
+        mov     r6, r10
+        mov     r7, r11
+        push    {r4, r5, r6, r7}
+        mov     r3, sp
+        str     r3, [r1, #CONTEXT_OFFSET]
+        ldr     r3, [r0, #CONTEXT_OFFSET]
+        mov     sp, r3
+        pop     {r4, r5, r6, r7}
+        mov     r8, r4
+        mov     r9, r5
+        mov     r10, r6
+        mov     r11, r7
+        pop     {r4, r5, r6, r7, pc}
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+        PUBLIC  _port_thread_start
+_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl      dbg_check_unlock
+#endif
+        cpsie   i
+        mov     r0, r5
+        blx     r4
+        bl      chThdExit
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+        PUBLIC  _port_switch_from_isr
+        PUBLIC  _port_exit_from_isr
+_port_switch_from_isr:
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl      dbg_check_lock
+#endif
+        bl      chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl      dbg_check_unlock
+#endif
+_port_exit_from_isr:
+        ldr     r2, =SCB_ICSR
+        movs    r3, #128
+#if CORTEX_ALTERNATE_SWITCH
+        lsls    r3, r3, #21
+        str     r3, [r2, #0]
+        cpsie   i
+#else
+        lsls    r3, r3, #24
+        str     r3, [r2, #0]
+#endif
+waithere:
+        b       waithere
+
+        END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s b/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s
new file mode 100644
index 000000000..6a83a8f3d
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s
@@ -0,0 +1,128 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    compilers/IAR/chcoreasm_v7m.s
+ * @brief   ARMv7-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_IAR_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE   0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE    1
+#endif
+
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+        MODULE  ?chcoreasm_v7m
+
+        AAPCS INTERWORK, VFP_COMPATIBLE
+        PRESERVE8
+
+CONTEXT_OFFSET  SET 12
+SCB_ICSR        SET 0xE000ED04
+ICSR_PENDSVSET  SET 0x10000000
+
+        SECTION .text:CODE:NOROOT(2)
+
+        EXTERN  chThdExit
+        EXTERN  chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+        EXTERN  dbg_check_unlock
+        EXTERN  dbg_check_lock
+#endif
+
+        THUMB
+
+/*
+ * Performs a context switch between two threads.
+ */
+        PUBLIC _port_switch
+_port_switch:
+        push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+#if CORTEX_USE_FPU
+        vpush   {s16-s31}
+#endif
+        str     sp, [r1, #CONTEXT_OFFSET]
+        ldr     sp, [r0, #CONTEXT_OFFSET]
+#if CORTEX_USE_FPU
+        vpop    {s16-s31}
+#endif
+        pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+        PUBLIC  _port_thread_start
+_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl      dbg_check_unlock
+#endif
+#if CORTEX_SIMPLIFIED_PRIORITY
+        cpsie   i
+#else
+        movs    r3, #CORTEX_BASEPRI_DISABLED
+        msr     BASEPRI, r3
+#endif
+        mov     r0, r5
+        blx     r4
+        bl      chThdExit
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+        PUBLIC  _port_switch_from_isr
+        PUBLIC  _port_exit_from_isr
+_port_switch_from_isr:
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl      dbg_check_lock
+#endif
+        bl      chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl      dbg_check_unlock
+#endif
+_port_exit_from_isr:
+#if CORTEX_SIMPLIFIED_PRIORITY
+        mov     r3, #LWRD SCB_ICSR
+        movt    r3, #HWRD SCB_ICSR
+        mov	r2, #ICSR_PENDSVSET
+        str	r2, [r3]
+        cpsie   i
+.L3:    b       .L3
+#else
+        svc     #0
+#endif
+
+        END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h b/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h
new file mode 100644
index 000000000..386d7203b
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h
@@ -0,0 +1,111 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/compilers/IAR/chtypes.h
+ * @brief   ARM Cortex-Mx port system types.
+ *
+ * @addtogroup ARMCMx_IAR_CORE
+ * @{
+ */
+
+#ifndef _CHTYPES_H_
+#define _CHTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name    Common constants
+ */
+/**
+ * @brief   Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE               0
+#endif
+
+/**
+ * @brief   Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                (!FALSE)
+#endif
+/** @} */
+
+/**
+ * @name    Derived generic types
+ * @{
+ */
+typedef volatile int8_t     vint8_t;        /**< Volatile signed 8 bits.    */
+typedef volatile uint8_t    vuint8_t;       /**< Volatile unsigned 8 bits.  */
+typedef volatile int16_t    vint16_t;       /**< Volatile signed 16 bits.   */
+typedef volatile uint16_t   vuint16_t;      /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t    vint32_t;       /**< Volatile signed 32 bits.   */
+typedef volatile uint32_t   vuint32_t;      /**< Volatile unsigned 32 bits. */
+/** @} */
+
+/**
+ * @name    Kernel types
+ * @{
+ */
+typedef uint32_t            rtcnt_t;        /**< Realtime counter.          */
+typedef uint64_t            rttime_t;       /**< Realtime accumulator.      */
+typedef uint32_t            syssts_t;       /**< System status word.        */
+typedef uint8_t             tmode_t;        /**< Thread flags.              */
+typedef uint8_t             tstate_t;       /**< Thread state.              */
+typedef uint8_t             trefs_t;        /**< Thread references counter. */
+typedef uint8_t             tslices_t;      /**< Thread time slices counter.*/
+typedef uint32_t            tprio_t;        /**< Thread priority.           */
+typedef int32_t             msg_t;          /**< Inter-thread message.      */
+typedef int32_t             eventid_t;      /**< Numeric event identifier.  */
+typedef uint32_t            eventmask_t;    /**< Mask of event identifiers. */
+typedef uint32_t            eventflags_t;   /**< Mask of event flags.       */
+typedef int32_t             cnt_t;          /**< Generic signed counter.    */
+typedef uint32_t            ucnt_t;         /**< Generic unsigned counter.  */
+/** @} */
+
+/**
+ * @brief   ROM constant modifier.
+ * @note    It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief   Makes functions not inlineable.
+ * @note    If the compiler does not support such attribute then the
+ *          realtime counter precision could be degraded.
+ */
+#define NOINLINE
+
+/**
+ * @brief   Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) msg_t tname(void *arg)
+
+/**
+ * @brief   Packed variable specifier.
+ */
+#define PACKED_VAR __packed
+
+#endif /* _CHTYPES_H_ */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s
new file mode 100644
index 000000000..15b0fb4c3
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s
@@ -0,0 +1,127 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    compilers/RVCT/chcoreasm_v6m.s
+ * @brief   ARMv6-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_RVCT_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE   0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE    1
+#endif
+
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+CONTEXT_OFFSET  EQU     12
+SCB_ICSR        EQU     0xE000ED04
+
+                PRESERVE8
+                THUMB
+                AREA    |.text|, CODE, READONLY
+
+                IMPORT  chThdExit
+                IMPORT  chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                IMPORT  dbg_check_unlock
+                IMPORT  dbg_check_lock
+#endif
+
+/*
+ * Performs a context switch between two threads.
+ */
+                EXPORT _port_switch
+_port_switch    PROC
+                push    {r4, r5, r6, r7, lr}
+                mov     r4, r8
+                mov     r5, r9
+                mov     r6, r10
+                mov     r7, r11
+                push    {r4, r5, r6, r7}
+                mov     r3, sp
+                str     r3, [r1, #CONTEXT_OFFSET]
+                ldr     r3, [r0, #CONTEXT_OFFSET]
+                mov     sp, r3
+                pop     {r4, r5, r6, r7}
+                mov     r8, r4
+                mov     r9, r5
+                mov     r10, r6
+                mov     r11, r7
+                pop     {r4, r5, r6, r7, pc}
+                ENDP
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+                EXPORT  _port_thread_start
+_port_thread_start PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_unlock
+#endif
+                cpsie   i
+                mov     r0, r5
+                blx     r4
+                bl      chThdExit
+                ENDP
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+                EXPORT  _port_switch_from_isr
+                EXPORT  _port_exit_from_isr
+_port_switch_from_isr PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_lock
+#endif
+                bl      chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_unlock
+#endif
+_port_exit_from_isr
+                ldr     r2, =SCB_ICSR
+                movs    r3, #128
+#if CORTEX_ALTERNATE_SWITCH
+                lsls    r3, r3, #21
+                str     r3, [r2, #0]
+                cpsie   i
+#else
+                lsls    r3, r3, #24
+                str     r3, [r2, #0]
+#endif
+waithere        b       waithere
+                ENDP
+
+                END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s
new file mode 100644
index 000000000..254624708
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s
@@ -0,0 +1,126 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    compilers/RVCT/chcoreasm_v7m.s
+ * @brief   ARMv7-M architecture port low level code.
+ *
+ * @addtogroup ARMCMx_RVCT_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE   0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE    1
+#endif
+
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+
+CONTEXT_OFFSET  EQU     12
+SCB_ICSR        EQU     0xE000ED04
+ICSR_PENDSVSET  EQU     0x10000000
+
+                PRESERVE8
+                THUMB
+                AREA    |.text|, CODE, READONLY
+
+                IMPORT  chThdExit
+                IMPORT  chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                IMPORT  dbg_check_unlock
+                IMPORT  dbg_check_lock
+#endif
+
+/*
+ * Performs a context switch between two threads.
+ */
+                EXPORT _port_switch
+_port_switch    PROC
+                push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+#if CORTEX_USE_FPU
+                vpush   {s16-s31}
+#endif
+                str     sp, [r1, #CONTEXT_OFFSET]                          
+                ldr     sp, [r0, #CONTEXT_OFFSET]
+#if CORTEX_USE_FPU
+                vpop    {s16-s31}
+#endif
+                pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+                ENDP
+
+/*
+ * Start a thread by invoking its work function.
+ * If the work function returns @p chThdExit() is automatically invoked.
+ */
+                EXPORT  _port_thread_start
+_port_thread_start PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_unlock
+#endif
+#if CORTEX_SIMPLIFIED_PRIORITY
+                cpsie   i
+#else
+                movs    r3, #CORTEX_BASEPRI_DISABLED
+                msr     BASEPRI, r3
+#endif
+                mov     r0, r5
+                blx     r4
+                bl      chThdExit
+                ENDP
+
+/*
+ * Post-IRQ switch code.
+ * Exception handlers return here for context switching.
+ */
+                EXPORT  _port_switch_from_isr
+                EXPORT  _port_exit_from_isr
+_port_switch_from_isr PROC
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_lock
+#endif
+                bl      chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+                bl      dbg_check_unlock
+#endif
+_port_exit_from_isr
+#if CORTEX_SIMPLIFIED_PRIORITY
+                mov     r3, #SCB_ICSR :AND: 0xFFFF
+                movt    r3, #SCB_ICSR :SHR: 16
+                mov     r2, #ICSR_PENDSVSET
+                str     r2, [r3, #0]
+                cpsie   i
+waithere        b       waithere
+#else
+                svc     #0
+#endif
+                ENDP
+
+                END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h b/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h
new file mode 100644
index 000000000..3fe32d065
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h
@@ -0,0 +1,111 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ARMCMx/compilers/RVCT/chtypes.h
+ * @brief   ARM Cortex-Mx port system types.
+ *
+ * @addtogroup ARMCMx_RVCT_CORE
+ * @{
+ */
+
+#ifndef _CHTYPES_H_
+#define _CHTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name    Common constants
+ */
+/**
+ * @brief   Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE               0
+#endif
+
+/**
+ * @brief   Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                (!FALSE)
+#endif
+/** @} */
+
+/**
+ * @name    Derived generic types
+ * @{
+ */
+typedef volatile int8_t     vint8_t;        /**< Volatile signed 8 bits.    */
+typedef volatile uint8_t    vuint8_t;       /**< Volatile unsigned 8 bits.  */
+typedef volatile int16_t    vint16_t;       /**< Volatile signed 16 bits.   */
+typedef volatile uint16_t   vuint16_t;      /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t    vint32_t;       /**< Volatile signed 32 bits.   */
+typedef volatile uint32_t   vuint32_t;      /**< Volatile unsigned 32 bits. */
+/** @} */
+
+/**
+ * @name    Kernel types
+ * @{
+ */
+typedef uint32_t            rtcnt_t;        /**< Realtime counter.          */
+typedef uint64_t            rttime_t;       /**< Realtime accumulator.      */
+typedef uint32_t            syssts_t;       /**< System status word.        */
+typedef uint8_t             tmode_t;        /**< Thread flags.              */
+typedef uint8_t             tstate_t;       /**< Thread state.              */
+typedef uint8_t             trefs_t;        /**< Thread references counter. */
+typedef uint8_t             tslices_t;      /**< Thread time slices counter.*/
+typedef uint32_t            tprio_t;        /**< Thread priority.           */
+typedef int32_t             msg_t;          /**< Inter-thread message.      */
+typedef int32_t             eventid_t;      /**< Numeric event identifier.  */
+typedef uint32_t            eventmask_t;    /**< Mask of event identifiers. */
+typedef uint32_t            eventflags_t;   /**< Mask of event flags.       */
+typedef int32_t             cnt_t;          /**< Generic signed counter.    */
+typedef uint32_t            ucnt_t;         /**< Generic unsigned counter.  */
+/** @} */
+
+/**
+ * @brief   ROM constant modifier.
+ * @note    It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief   Makes functions not inlineable.
+ * @note    If the compiler does not support such attribute then the
+ *          realtime counter precision could be degraded.
+ */
+#define NOINLINE
+
+/**
+ * @brief   Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) msg_t tname(void *arg)
+
+/**
+ * @brief   Packed variable specifier.
+ */
+#define PACKED_VAR __packed
+
+#endif /* _CHTYPES_H_ */
+
+/** @} */
diff --git a/os/rt/ports/e200/chcore.c b/os/rt/ports/e200/chcore.c
new file mode 100644
index 000000000..a74c76cad
--- /dev/null
+++ b/os/rt/ports/e200/chcore.c
@@ -0,0 +1,107 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    PPC/chcore.c
+ * @brief   PowerPC architecture port code.
+ *
+ * @addtogroup PPC_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((naked))
+#endif
+void port_dummy1(void) {
+
+  asm (".global _port_switch");
+  asm ("_port_switch:");
+  asm ("subi        %sp, %sp, 80");     /* Size of the intctx structure.    */
+  asm ("mflr        %r0");
+  asm ("stw         %r0, 84(%sp)");     /* LR into the caller frame.        */
+  asm ("mfcr        %r0");
+  asm ("stw         %r0, 0(%sp)");      /* CR.                              */
+  asm ("stmw        %r14, 4(%sp)");     /* GPR14...GPR31.                   */
+  
+  asm ("stw         %sp, 12(%r4)");     /* Store swapped-out stack.         */
+  asm ("lwz         %sp, 12(%r3)");     /* Load swapped-in stack.           */
+  
+  asm ("lmw         %r14, 4(%sp)");     /* GPR14...GPR31.                   */
+  asm ("lwz         %r0, 0(%sp)");      /* CR.                              */
+  asm ("mtcr        %r0");
+  asm ("lwz         %r0, 84(%sp)");     /* LR from the caller frame.        */
+  asm ("mtlr        %r0");
+  asm ("addi        %sp, %sp, 80");     /* Size of the intctx structure.    */
+  asm ("blr");
+}
+
+/**
+ * @brief   Start a thread by invoking its work function.
+ * @details If the work function returns @p chThdExit() is automatically
+ *          invoked.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((naked))
+#endif
+void port_dummy2(void) {
+
+  asm (".global _port_thread_start");
+  asm ("_port_thread_start:");
+  chSysUnlock();
+  asm ("mr          %r3, %r31");        /* Thread parameter.                */
+  asm ("mtctr       %r30");
+  asm ("bctrl");                        /* Invoke thread function.          */
+  asm ("bl          chThdExit");        /* Thread termination on exit.      */
+}
+
+/** @} */
diff --git a/os/rt/ports/e200/chcore.h b/os/rt/ports/e200/chcore.h
new file mode 100644
index 000000000..0255a0f1d
--- /dev/null
+++ b/os/rt/ports/e200/chcore.h
@@ -0,0 +1,550 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    PPC/chcore.h
+ * @brief   PowerPC architecture port macros and structures.
+ *
+ * @addtogroup PPC_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_H_
+#define _CHCORE_H_
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief   Macro defining an PPC architecture.
+ */
+#define PORT_ARCHITECTURE_PPC
+
+/**
+ * @brief   Macro defining the specific PPC architecture.
+ */
+#define PORT_ARCHITECTURE_PPC_E200
+
+/**
+ * @brief   Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME          "Power Architecture"
+
+/**
+ * @brief   Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME              "GCC " __VERSION__
+
+#else
+#error "unsupported compiler"
+#endif
+/** @} */
+
+/**
+ * @name    E200 core variants
+ * @{
+ */
+#define PPC_VARIANT_e200z0              200
+#define PPC_VARIANT_e200z2              202
+#define PPC_VARIANT_e200z3              203
+#define PPC_VARIANT_e200z4              204
+/** @} */
+
+/* Inclusion of the PPC implementation specific parameters.*/
+#include "ppcparams.h"
+#include "vectors.h"
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ *          the idle thread should take no more space than those reserved
+ *          by @p PORT_INT_REQUIRED_STACK.
+ * @note    In this port it is set to 32 because the idle thread does have
+ *          a stack frame when compiling without optimizations. You may
+ *          reduce this value to zero when compiling with optimizations.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE     32
+#endif
+
+/**
+ * @brief   Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ *          area size.
+ * @note    In this port this value is conservatively is set to 256 because
+ *          there is no separate interrupts stack (yet).
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK         256
+#endif
+
+/**
+ * @brief   Use VLE instruction set.
+ * @note    This parameter is usually set in the Makefile.
+ */
+#if !defined(PPC_USE_VLE)
+#define PPC_USE_VLE                     TRUE
+#endif
+
+/**
+ * @brief   Enables the use of the @p WFI instruction.
+ */
+#if !defined(PPC_ENABLE_WFI_IDLE)
+#define PPC_ENABLE_WFI_IDLE             FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if PPC_USE_VLE && !PPC_SUPPORTS_VLE
+#error "the selected MCU does not support VLE instructions set"
+#endif
+
+#if !PPC_USE_VLE && !PPC_SUPPORTS_BOOKE
+#error "the selected MCU does not support BookE instructions set"
+#endif
+
+/**
+ * @brief   Name of the architecture variant.
+ */
+#if (PPC_VARIANT == PPC_VARIANT_e200z0) || defined(__DOXYGEN__)
+#define PORT_CORE_VARIANT_NAME          "e200z0"
+#elif PPC_VARIANT == PPC_VARIANT_e200z2
+#define PORT_CORE_VARIANT_NAME          "e200z2"
+#elif PPC_VARIANT == PPC_VARIANT_e200z3
+#define PORT_CORE_VARIANT_NAME          "e200z3"
+#elif PPC_VARIANT == PPC_VARIANT_e200z4
+#define PORT_CORE_VARIANT_NAME          "e200z4"
+#else
+#error "unknown or unsupported PowerPC variant specified"
+#endif
+
+/**
+ * @brief   Port-specific information string.
+ */
+#if PPC_USE_VLE
+#define PORT_INFO                       "VLE mode"
+#else
+#define PORT_INFO                       "Book-E mode"
+#endif
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Type of system time.
+ */
+#if (CH_CFG_ST_RESOLUTION == 32) || defined(__DOXYGEN__)
+typedef uint32_t systime_t;
+#else
+typedef uint16_t systime_t;
+#endif
+
+/**
+ * @brief   Type of stack and memory alignment enforcement.
+ * @note    In this architecture the stack alignment is enforced to 64 bits.
+ */
+typedef uint64_t stkalign_t;
+
+/**
+ * @brief   Generic PPC register.
+ */
+typedef void *regppc_t;
+
+/**
+ * @brief   Mandatory part of a stack frame.
+ */
+struct port_eabi_frame {
+  uint32_t      slink;          /**< Stack back link.                       */
+  uint32_t      shole;          /**< Stack hole for LR storage.             */
+};
+
+/**
+ * @brief   Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ *          preemption-capable interrupt handler.
+ * @note    R2 and R13 are not saved because those are assumed to be immutable
+ *          during the system life cycle.
+ */
+struct port_extctx {
+  struct port_eabi_frame frame;
+  /* Start of the e_stmvsrrw frame (offset 8).*/
+  regppc_t      pc;
+  regppc_t      msr;
+  /* Start of the e_stmvsprw frame (offset 16).*/
+  regppc_t      cr;
+  regppc_t      lr;
+  regppc_t      ctr;
+  regppc_t      xer;
+  /* Start of the e_stmvgprw frame (offset 32).*/
+  regppc_t      r0;
+  regppc_t      r3;
+  regppc_t      r4;
+  regppc_t      r5;
+  regppc_t      r6;
+  regppc_t      r7;
+  regppc_t      r8;
+  regppc_t      r9;
+  regppc_t      r10;
+  regppc_t      r11;
+  regppc_t      r12;
+  regppc_t      padding;
+ };
+
+/**
+ * @brief   System saved context.
+ * @details This structure represents the inner stack frame during a context
+ *          switching.
+ * @note    R2 and R13 are not saved because those are assumed to be immutable
+ *          during the system life cycle.
+ * @note    LR is stored in the caller contex so it is not present in this
+ *          structure.
+ */
+struct port_intctx {
+  regppc_t      cr;                 /* Part of it is not volatile...        */
+  regppc_t      r14;
+  regppc_t      r15;
+  regppc_t      r16;
+  regppc_t      r17;
+  regppc_t      r18;
+  regppc_t      r19;
+  regppc_t      r20;
+  regppc_t      r21;
+  regppc_t      r22;
+  regppc_t      r23;
+  regppc_t      r24;
+  regppc_t      r25;
+  regppc_t      r26;
+  regppc_t      r27;
+  regppc_t      r28;
+  regppc_t      r29;
+  regppc_t      r30;
+  regppc_t      r31;
+  regppc_t      padding;
+};
+
+/**
+ * @brief   Platform dependent part of the @p Thread structure.
+ * @details This structure usually contains just the saved stack pointer
+ *          defined as a pointer to a @p port_intctx structure.
+ */
+struct context {
+  struct port_intctx *sp;
+};
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ *          by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, workspace, wsize, pf, arg) {                 \
+  uint8_t *sp = (uint8_t *)(workspace) +                                    \
+                           (wsize) -                                        \
+                           sizeof(struct port_eabi_frame);                  \
+  ((struct port_eabi_frame *)sp)->slink = 0;                                \
+  ((struct port_eabi_frame *)sp)->shole = (uint32_t)_port_thread_start;     \
+  (tp)->p_ctx.sp = (struct port_intctx *)(sp - sizeof(struct port_intctx)); \
+  (tp)->p_ctx.sp->r31 = (regppc_t)(arg);                                    \
+  (tp)->p_ctx.sp->r30 = (regppc_t)(pf);                                     \
+}
+
+/**
+ * @brief   Computes the thread working area global size.
+ * @note    There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) +                       \
+                         sizeof(struct port_extctx) +                       \
+                         (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE()
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Fast IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ */
+#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) {                                             \
+  register struct port_intctx *sp asm ("%r1");                              \
+  if ((stkalign_t *)(sp - 1) < otp->p_stklimit)                             \
+    chDbgPanic("stack overflow");                                           \
+  _port_switch(ntp, otp);                                                   \
+}
+#endif
+
+/**
+ * @brief   Writes to a special register.
+ *
+ * @param[in] spr       special register number
+ * @param[in] val       value to be written, must be an automatic variable
+ */
+#define port_write_spr(spr, val)                                            \
+  asm volatile ("mtspr   %[p0], %[p1]" : : [p0] "n" (spr), [p1] "r" (val))
+
+/**
+ * @brief   Writes to a special register.
+ *
+ * @param[in] spr       special register number
+ * @param[in] val       returned value, must be an automatic variable
+ */
+#define port_read_spr(spr, val)                                             \
+  asm volatile ("mfspr   %[p0], %[p1]" : [p0] "=r" (val) : [p1] "n" (spr))
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _port_switch(thread_t *ntp, thread_t *otp);
+  void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief   Kernel port layer initialization.
+ * @details IVOR4 and IVOR10 initialization.
+ */
+static inline void port_init(void) {
+  uint32_t n;
+
+  /* Initializing the SPRG0 register to zero, it is required for interrupts
+     handling.*/
+  n = 0;
+  port_write_spr(272, n);
+
+#if PPC_SUPPORTS_IVORS
+  /* The CPU supports IVOR registers, the kernel requires IVOR4 and IVOR10
+     and the initialization is performed here.*/
+  asm volatile ("li          %%r3, _IVOR4@l       \t\n"
+                "mtIVOR4     %%r3                 \t\n"
+                "li          %%r3, _IVOR10@l      \t\n"
+                "mtIVOR10    %%r3" : : : "r3", "memory");
+#endif
+
+  /* Interrupt controller initialization.*/
+  intc_init();
+}
+
+/**
+ * @brief   Returns a word encoding the current interrupts status.
+ *
+ * @return              The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+  uint32_t sts;
+
+  asm volatile ("mfmsr   %[p0]" : [p0] "=r" (sts) :);
+  return sts;
+}
+
+/**
+ * @brief   Checks the interrupt status.
+ *
+ * @param[in] sts       the interrupt status word
+ *
+ * @return              The interrupt status.
+ * @retvel false        the word specified a disabled interrupts status.
+ * @retvel true         the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+  return (bool)((sts & (1 << 15)) != 0);
+}
+
+/**
+ * @brief   Determines the current execution context.
+ *
+ * @return              The execution context.
+ * @retval false        not running in ISR mode.
+ * @retval true         running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+  uint32_t sprg0;
+
+  /* The SPRG0 register is increased before entering interrupt handlers and
+     decreased at the end.*/
+  port_read_spr(272, sprg0);
+  return (bool)(sprg0 > 0);
+}
+
+/**
+ * @brief   Kernel-lock action.
+ * @note    Implemented as global interrupt disable.
+ */
+static inline void port_lock(void) {
+
+  asm volatile ("wrteei  0" : : : "memory");
+}
+
+/**
+ * @brief   Kernel-unlock action.
+ * @note    Implemented as global interrupt enable.
+ */
+static inline void port_unlock(void) {
+
+  asm volatile("wrteei  1" : : : "memory");
+}
+
+/**
+ * @brief   Kernel-lock action from an interrupt handler.
+ * @note    Implementation not needed.
+ */
+static inline void port_lock_from_isr(void) {
+
+}
+
+/**
+ * @brief   Kernel-unlock action from an interrupt handler.
+ * @note    Implementation not needed.
+ */
+static inline void port_unlock_from_isr(void) {
+
+}
+
+/**
+ * @brief   Disables all the interrupt sources.
+ * @note    Implemented as global interrupt disable.
+ */
+static inline void port_disable(void) {
+
+  asm volatile ("wrteei  0" : : : "memory");
+}
+
+/**
+ * @brief   Disables the interrupt sources below kernel-level priority.
+ * @note    Same as @p port_disable() in this port, there is no difference
+ *          between the two states.
+ */
+static inline void port_suspend(void) {
+
+  asm volatile ("wrteei  0" : : : "memory");
+}
+
+/**
+ * @brief   Enables all the interrupt sources.
+ * @note    Implemented as global interrupt enable.
+ */
+static inline void port_enable(void) {
+
+  asm volatile ("wrteei  1" : : : "memory");
+}
+
+/**
+ * @brief   Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ *          The simplest implementation is an empty function or macro but this
+ *          would not take advantage of architecture-specific power saving
+ *          modes.
+ * @note    Implemented as an inlined @p wait instruction.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+#if PPC_ENABLE_WFI_IDLE
+  asm volatile ("wait" : : : "memory");
+#endif
+}
+
+/**
+ * @brief   Returns the current value of the realtime counter.
+ *
+ * @return              The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+
+  return 0;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CHCORE_H_ */
+
+/** @} */
diff --git a/os/rt/ports/e200/compilers/GCC/chtypes.h b/os/rt/ports/e200/compilers/GCC/chtypes.h
new file mode 100644
index 000000000..074d33c14
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/chtypes.h
@@ -0,0 +1,106 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    PPC/chtypes.h
+ * @brief   PowerPC architecture port system types.
+ *
+ * @addtogroup PPC_CORE
+ * @{
+ */
+
+#ifndef _CHTYPES_H_
+#define _CHTYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name    Common constants
+ */
+/**
+ * @brief   Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE               0
+#endif
+
+/**
+ * @brief   Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE                (!FALSE)
+#endif
+/** @} */
+
+/**
+ * @name    Derived generic types
+ * @{
+ */
+typedef volatile int8_t     vint8_t;        /**< Volatile signed 8 bits.    */
+typedef volatile uint8_t    vuint8_t;       /**< Volatile unsigned 8 bits.  */
+typedef volatile int16_t    vint16_t;       /**< Volatile signed 16 bits.   */
+typedef volatile uint16_t   vuint16_t;      /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t    vint32_t;       /**< Volatile signed 32 bits.   */
+typedef volatile uint32_t   vuint32_t;      /**< Volatile unsigned 32 bits. */
+/** @} */
+
+/**
+ * @name    Kernel types
+ * @{
+ */
+typedef uint32_t            rtcnt_t;        /**< Realtime counter.          */
+typedef uint64_t            rttime_t;       /**< Realtime accumulator.      */
+typedef uint32_t            syssts_t;       /**< System status word.        */
+typedef uint8_t             tmode_t;        /**< Thread flags.              */
+typedef uint8_t             tstate_t;       /**< Thread state.              */
+typedef uint8_t             trefs_t;        /**< Thread references counter. */
+typedef uint8_t             tslices_t;      /**< Thread time slices counter.*/
+typedef uint32_t            tprio_t;        /**< Thread priority.           */
+typedef int32_t             msg_t;          /**< Inter-thread message.      */
+typedef int32_t             eventid_t;      /**< Numeric event identifier.  */
+typedef uint32_t            eventmask_t;    /**< Mask of event identifiers. */
+typedef uint32_t            eventflags_t;   /**< Mask of event flags.       */
+typedef int32_t             cnt_t;          /**< Generic signed counter.    */
+typedef uint32_t            ucnt_t;         /**< Generic unsigned counter.  */
+/** @} */
+
+/**
+ * @brief   ROM constant modifier.
+ * @note    It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief   Makes functions not inlineable.
+ * @note    If the compiler does not support such attribute then the
+ *          realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief   Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) msg_t tname(void *arg)
+
+#endif /* _CHTYPES_H_ */
+
+/** @} */
diff --git a/os/rt/ports/e200/compilers/GCC/ivor.s b/os/rt/ports/e200/compilers/GCC/ivor.s
new file mode 100644
index 000000000..ae478b49f
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/ivor.s
@@ -0,0 +1,252 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    ivor.s
+ * @brief   Kernel ISRs.
+ *
+ * @addtogroup PPC_CORE
+ * @{
+ */
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE   0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE    1
+#endif
+
+/*
+ * Imports the PPC configuration headers.
+ */
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
+
+#if !defined(__DOXYGEN__)
+        /*
+         * INTC registers address.
+         */
+        .equ  INTC_IACKR, 0xfff48010
+        .equ  INTC_EOIR,  0xfff48018
+
+        .section    .handlers, "ax"
+
+#if PPC_SUPPORTS_DECREMENTER
+        /*
+         * _IVOR10 handler (Book-E decrementer).
+         */
+        .align      4
+        .globl      _IVOR10
+        .type       _IVOR10, @function
+_IVOR10:
+        /* Saving the external context (port_extctx structure).*/
+        stwu        %sp, -80(%sp)
+#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
+        e_stmvsrrw  8(%sp)                  /* Saves PC, MSR.               */
+        e_stmvsprw  16(%sp)                 /* Saves CR, LR, CTR, XER.      */
+        e_stmvgprw  32(%sp)                 /* Saves GPR0, GPR3...GPR12.    */
+#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
+        stw         %r0, 32(%sp)            /* Saves GPR0.                  */
+        mfSRR0      %r0
+        stw         %r0, 8(%sp)             /* Saves PC.                    */
+        mfSRR1      %r0
+        stw         %r0, 12(%sp)            /* Saves MSR.                   */
+        mfCR        %r0
+        stw         %r0, 16(%sp)            /* Saves CR.                    */
+        mfLR        %r0
+        stw         %r0, 20(%sp)            /* Saves LR.                    */
+        mfCTR       %r0
+        stw         %r0, 24(%sp)            /* Saves CTR.                   */
+        mfXER       %r0
+        stw         %r0, 28(%sp)            /* Saves XER.                   */
+        stw         %r3, 36(%sp)            /* Saves GPR3...GPR12.          */
+        stw         %r4, 40(%sp)
+        stw         %r5, 44(%sp)
+        stw         %r6, 48(%sp)
+        stw         %r7, 52(%sp)
+        stw         %r8, 56(%sp)
+        stw         %r9, 60(%sp)
+        stw         %r10, 64(%sp)
+        stw         %r11, 68(%sp)
+        stw         %r12, 72(%sp)
+#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
+
+        /* Increasing the SPGR0 register.*/
+        mfspr       %r0, 272
+        eaddi       %r0, %r0, 1
+        mtspr       272, %r0
+
+        /* Reset DIE bit in TSR register.*/
+        lis         %r3, 0x0800             /* DIS bit mask.                */
+        mtspr       336, %r3                /* TSR register.                */
+
+#if PPC_USE_IRQ_PREEMPTION
+        /* Allows preemption while executing the software handler.*/
+        wrteei      1
+#endif
+
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl          dbg_check_enter_isr
+        bl          dbg_check_lock_from_isr
+#endif
+        /* System tick handler invocation.*/
+        bl          chSysTimerHandlerI
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl          dbg_check_unlock_from_isr
+        bl          dbg_check_leave_isr
+#endif
+
+#if PPC_USE_IRQ_PREEMPTION
+        /* Prevents preemption again.*/
+        wrteei      0
+#endif
+
+        /* Jumps to the common IVOR epilogue code.*/
+        b           _ivor_exit
+#endif /* PPC_SUPPORTS_DECREMENTER */
+
+        /*
+         * _IVOR4 handler (Book-E external interrupt).
+         */
+        .align      4
+        .globl      _IVOR4
+        .type       _IVOR4, @function
+_IVOR4:
+        /* Saving the external context (port_extctx structure).*/
+        stwu        %sp, -80(%sp)
+#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
+        e_stmvsrrw  8(%sp)                  /* Saves PC, MSR.               */
+        e_stmvsprw  16(%sp)                 /* Saves CR, LR, CTR, XER.      */
+        e_stmvgprw  32(%sp)                 /* Saves GPR0, GPR3...GPR12.    */
+#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
+        stw         %r0, 32(%sp)            /* Saves GPR0.                  */
+        mfSRR0      %r0
+        stw         %r0, 8(%sp)             /* Saves PC.                    */
+        mfSRR1      %r0
+        stw         %r0, 12(%sp)            /* Saves MSR.                   */
+        mfCR        %r0
+        stw         %r0, 16(%sp)            /* Saves CR.                    */
+        mfLR        %r0
+        stw         %r0, 20(%sp)            /* Saves LR.                    */
+        mfCTR       %r0
+        stw         %r0, 24(%sp)            /* Saves CTR.                   */
+        mfXER       %r0
+        stw         %r0, 28(%sp)            /* Saves XER.                   */
+        stw         %r3, 36(%sp)            /* Saves GPR3...GPR12.          */
+        stw         %r4, 40(%sp)
+        stw         %r5, 44(%sp)
+        stw         %r6, 48(%sp)
+        stw         %r7, 52(%sp)
+        stw         %r8, 56(%sp)
+        stw         %r9, 60(%sp)
+        stw         %r10, 64(%sp)
+        stw         %r11, 68(%sp)
+        stw         %r12, 72(%sp)
+#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
+
+        /* Increasing the SPGR0 register.*/
+        mfspr       %r0, 272
+        eaddi       %r0, %r0, 1
+        mtspr       272, %r0
+
+        /* Software vector address from the INTC register.*/
+        lis         %r3, INTC_IACKR@h
+        ori         %r3, %r3, INTC_IACKR@l  /* IACKR register address.      */
+        lwz         %r3, 0(%r3)             /* IACKR register value.        */
+        lwz         %r3, 0(%r3)
+        mtCTR       %r3                     /* Software handler address.    */
+
+#if PPC_USE_IRQ_PREEMPTION
+        /* Allows preemption while executing the software handler.*/
+        wrteei      1
+#endif
+
+        /* Exectes the software handler.*/
+        bctrl
+
+#if PPC_USE_IRQ_PREEMPTION
+        /* Prevents preemption again.*/
+        wrteei      0
+#endif
+
+        /* Informs the INTC that the interrupt has been served.*/
+        mbar        0
+        lis         %r3, INTC_EOIR@h
+        ori         %r3, %r3, INTC_EOIR@l
+        stw         %r3, 0(%r3)             /* Writing any value should do. */
+
+        /* Common IVOR epilogue code, context restore.*/
+        .globl      _ivor_exit
+_ivor_exit:
+        /* Decreasing the SPGR0 register.*/
+        mfspr       %r0, 272
+        eaddi       %r0, %r0, -1
+        mtspr       272, %r0
+
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl          dbg_check_lock
+#endif
+        bl          chSchIsPreemptionRequired
+        cmpli       cr0, %r3, 0
+        beq         cr0, .noresch
+        bl          chSchDoReschedule
+.noresch:
+#if CH_DBG_SYSTEM_STATE_CHECK
+        bl          dbg_check_unlock
+#endif
+
+        /* Restoring the external context.*/
+#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
+        e_lmvgprw   32(%sp)                 /* Restores GPR0, GPR3...GPR12. */
+        e_lmvsprw   16(%sp)                 /* Restores CR, LR, CTR, XER.   */
+        e_lmvsrrw   8(%sp)                  /* Restores PC, MSR.            */
+#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
+        lwz         %r3, 36(%sp)            /* Restores GPR3...GPR12.       */
+        lwz         %r4, 40(%sp)
+        lwz         %r5, 44(%sp)
+        lwz         %r6, 48(%sp)
+        lwz         %r7, 52(%sp)
+        lwz         %r8, 56(%sp)
+        lwz         %r9, 60(%sp)
+        lwz         %r10, 64(%sp)
+        lwz         %r11, 68(%sp)
+        lwz         %r12, 72(%sp)
+        lwz         %r0, 8(%sp)
+        mtSRR0      %r0                     /* Restores PC.                 */
+        lwz         %r0, 12(%sp)
+        mtSRR1      %r0                     /* Restores MSR.                */
+        lwz         %r0, 16(%sp)
+        mtCR        %r0                     /* Restores CR.                 */
+        lwz         %r0, 20(%sp)
+        mtLR        %r0                     /* Restores LR.                 */
+        lwz         %r0, 24(%sp)
+        mtCTR       %r0                     /* Restores CTR.                */
+        lwz         %r0, 28(%sp)
+        mtXER       %r0                     /* Restores XER.                */
+        lwz         %r0, 32(%sp)            /* Restores GPR0.               */
+#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
+        addi        %sp, %sp, 80            /* Back to the previous frame.  */
+        rfi
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/rt/ports/e200/compilers/GCC/mk/port_spc560bcxx.mk b/os/rt/ports/e200/compilers/GCC/mk/port_spc560bcxx.mk
new file mode 100644
index 000000000..cdd0b9c0e
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/mk/port_spc560bcxx.mk
@@ -0,0 +1,14 @@
+# List of the ChibiOS/RT e200z0 SPC560BCxx port files.
+PORTSRC = ${CHIBIOS}/os/rt/ports/e200/chcore.c
+          
+PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560BCxx/boot.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \
+          $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s
+
+PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
+          ${CHIBIOS}/os/common/ports/e200/devices/SPC560BCxx \
+          ${CHIBIOS}/os/rt/ports/e200 \
+          ${CHIBIOS}/os/rt/ports/e200/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
diff --git a/os/rt/ports/e200/compilers/GCC/mk/port_spc560bxx.mk b/os/rt/ports/e200/compilers/GCC/mk/port_spc560bxx.mk
new file mode 100644
index 000000000..c1b8447cf
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/mk/port_spc560bxx.mk
@@ -0,0 +1,14 @@
+# List of the ChibiOS/RT e200z0 SPC560Bxx port files.
+PORTSRC = ${CHIBIOS}/os/rt/ports/e200/chcore.c
+          
+PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Bxx/boot.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \
+          $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s
+
+PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
+          ${CHIBIOS}/os/common/ports/e200/devices/SPC560Bxx \
+          ${CHIBIOS}/os/rt/ports/e200 \
+          ${CHIBIOS}/os/rt/ports/e200/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
diff --git a/os/rt/ports/e200/compilers/GCC/mk/port_spc560dxx.mk b/os/rt/ports/e200/compilers/GCC/mk/port_spc560dxx.mk
new file mode 100644
index 000000000..9959e375c
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/mk/port_spc560dxx.mk
@@ -0,0 +1,14 @@
+# List of the ChibiOS/RT e200z0 SPC560Dxx port files.
+PORTSRC = ${CHIBIOS}/os/rt/ports/e200/chcore.c
+          
+PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Dxx/boot.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \
+          $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s
+
+PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
+          ${CHIBIOS}/os/common/ports/e200/devices/SPC560Dxx \
+          ${CHIBIOS}/os/rt/ports/e200 \
+          ${CHIBIOS}/os/rt/ports/e200/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
diff --git a/os/rt/ports/e200/compilers/GCC/mk/port_spc560pxx.mk b/os/rt/ports/e200/compilers/GCC/mk/port_spc560pxx.mk
new file mode 100644
index 000000000..e9d078aff
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/mk/port_spc560pxx.mk
@@ -0,0 +1,14 @@
+# List of the ChibiOS/RT e200z0 SPC560Pxx port files.
+PORTSRC = ${CHIBIOS}/os/rt/ports/e200/chcore.c
+          
+PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC560Pxx/boot.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \
+          $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s
+
+PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
+          ${CHIBIOS}/os/common/ports/e200/devices/SPC560Pxx \
+          ${CHIBIOS}/os/rt/ports/e200 \
+          ${CHIBIOS}/os/rt/ports/e200/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
diff --git a/os/rt/ports/e200/compilers/GCC/mk/port_spc563mxx.mk b/os/rt/ports/e200/compilers/GCC/mk/port_spc563mxx.mk
new file mode 100644
index 000000000..02b8069ad
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/mk/port_spc563mxx.mk
@@ -0,0 +1,14 @@
+# List of the ChibiOS/RT e200z3 SPC563Mxx port files.
+PORTSRC = ${CHIBIOS}/os/rt/ports/e200/chcore.c
+          
+PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC563Mxx/boot.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \
+          $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s
+
+PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
+          ${CHIBIOS}/os/common/ports/e200/devices/SPC563Mxx \
+          ${CHIBIOS}/os/rt/ports/e200 \
+          ${CHIBIOS}/os/rt/ports/e200/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
diff --git a/os/rt/ports/e200/compilers/GCC/mk/port_spc564axx.mk b/os/rt/ports/e200/compilers/GCC/mk/port_spc564axx.mk
new file mode 100644
index 000000000..8364e0ce8
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/mk/port_spc564axx.mk
@@ -0,0 +1,14 @@
+# List of the ChibiOS/RT e200z4 SPC564Axx port files.
+PORTSRC = ${CHIBIOS}/os/rt/ports/e200/chcore.c
+          
+PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC564Axx/boot.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \
+          $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s
+
+PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
+          ${CHIBIOS}/os/common/ports/e200/devices/SPC564Axx \
+          ${CHIBIOS}/os/rt/ports/e200 \
+          ${CHIBIOS}/os/rt/ports/e200/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
diff --git a/os/rt/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk b/os/rt/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk
new file mode 100644
index 000000000..4a951d1c2
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk
@@ -0,0 +1,14 @@
+# List of the ChibiOS/RT e200z4 SPC56ECxx port files.
+PORTSRC = ${CHIBIOS}/os/rt/ports/e200/chcore.c
+          
+PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC56ECxx/boot.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \
+          $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s
+
+PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
+          ${CHIBIOS}/os/common/ports/e200/devices/SPC56ECxx \
+          ${CHIBIOS}/os/rt/ports/e200 \
+          ${CHIBIOS}/os/rt/ports/e200/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
diff --git a/os/rt/ports/e200/compilers/GCC/mk/port_spc56elxx.mk b/os/rt/ports/e200/compilers/GCC/mk/port_spc56elxx.mk
new file mode 100644
index 000000000..adf2d5cb8
--- /dev/null
+++ b/os/rt/ports/e200/compilers/GCC/mk/port_spc56elxx.mk
@@ -0,0 +1,14 @@
+# List of the ChibiOS/RT e200z4 SPC56ELxx port files.
+PORTSRC = ${CHIBIOS}/os/rt/ports/e200/chcore.c
+          
+PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC56ELxx/boot.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \
+          $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \
+          $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s
+
+PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \
+          ${CHIBIOS}/os/common/ports/e200/devices/SPC56ELxx \
+          ${CHIBIOS}/os/rt/ports/e200 \
+          ${CHIBIOS}/os/rt/ports/e200/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld
diff --git a/os/kernel/kernel.dox b/os/rt/rt.dox
index 05753a8f6..05753a8f6 100644
--- a/os/kernel/kernel.dox
+++ b/os/rt/rt.dox
diff --git a/os/rt/rt.mk b/os/rt/rt.mk
new file mode 100644
index 000000000..55a189f75
--- /dev/null
+++ b/os/rt/rt.mk
@@ -0,0 +1,24 @@
+# List of all the ChibiOS/RT kernel files, there is no need to remove the files
+# from this list, you can disable parts of the kernel by editing chconf.h.
+KERNSRC = ${CHIBIOS}/os/rt/src/chsys.c \
+          ${CHIBIOS}/os/rt/src/chdebug.c \
+          ${CHIBIOS}/os/rt/src/chtm.c \
+          ${CHIBIOS}/os/rt/src/chstats.c \
+          ${CHIBIOS}/os/rt/src/chschd.c \
+          ${CHIBIOS}/os/rt/src/chvt.c \
+          ${CHIBIOS}/os/rt/src/chthreads.c \
+          ${CHIBIOS}/os/rt/src/chdynamic.c \
+          ${CHIBIOS}/os/rt/src/chregistry.c \
+          ${CHIBIOS}/os/rt/src/chsem.c \
+          ${CHIBIOS}/os/rt/src/chmtx.c \
+          ${CHIBIOS}/os/rt/src/chcond.c \
+          ${CHIBIOS}/os/rt/src/chevents.c \
+          ${CHIBIOS}/os/rt/src/chmsg.c \
+          ${CHIBIOS}/os/rt/src/chmboxes.c \
+          ${CHIBIOS}/os/rt/src/chqueues.c \
+          ${CHIBIOS}/os/rt/src/chmemcore.c \
+          ${CHIBIOS}/os/rt/src/chheap.c \
+          ${CHIBIOS}/os/rt/src/chmempools.c
+
+# Required include directories
+KERNINC = ${CHIBIOS}/os/rt/include
diff --git a/os/rt/src/chcond.c b/os/rt/src/chcond.c
new file mode 100644
index 000000000..f56f508b0
--- /dev/null
+++ b/os/rt/src/chcond.c
@@ -0,0 +1,310 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/*
+   Concepts and parts of this file have been contributed by Leon Woestenberg.
+ */
+
+/**
+ * @file    chcond.c
+ * @brief   Condition Variables code.
+ *
+ * @addtogroup condition variables Condition Variables
+ * @details This module implements the Condition Variables mechanism. Condition
+ *          variables are an extensions to the mutex subsystem and cannot
+ *          work alone.
+ *          <h2>Operation mode</h2>
+ *          The condition variable is a synchronization object meant to be
+ *          used inside a zone protected by a mutex. Mutexes and condition
+ *          variables together can implement a Monitor construct.
+ * @pre     In order to use the condition variable APIs the @p CH_CFG_USE_CONDVARS
+ *          option must be enabled in @p chconf.h.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_CONDVARS || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes s @p condition_variable_t structure.
+ *
+ * @param[out] cp       pointer to a @p condition_variable_t structure
+ *
+ * @init
+ */
+void chCondObjectInit(condition_variable_t *cp) {
+
+  chDbgCheck(cp != NULL);
+
+  queue_init(&cp->c_queue);
+}
+
+/**
+ * @brief   Signals one thread that is waiting on the condition variable.
+ *
+ * @param[in] cp        pointer to the @p condition_variable_t structure
+ *
+ * @api
+ */
+void chCondSignal(condition_variable_t *cp) {
+
+  chDbgCheck(cp != NULL);
+
+  chSysLock();
+  if (queue_notempty(&cp->c_queue))
+    chSchWakeupS(queue_fifo_remove(&cp->c_queue), MSG_OK);
+  chSysUnlock();
+}
+
+/**
+ * @brief   Signals one thread that is waiting on the condition variable.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] cp        pointer to the @p condition_variable_t structure
+ *
+ * @iclass
+ */
+void chCondSignalI(condition_variable_t *cp) {
+
+  chDbgCheckClassI();
+  chDbgCheck(cp != NULL);
+
+  if (queue_notempty(&cp->c_queue)) {
+    thread_t *tp = queue_fifo_remove(&cp->c_queue);
+    tp->p_u.rdymsg = MSG_OK;
+    chSchReadyI(tp);
+  }
+}
+
+/**
+ * @brief   Signals all threads that are waiting on the condition variable.
+ *
+ * @param[in] cp        pointer to the @p condition_variable_t structure
+ *
+ * @api
+ */
+void chCondBroadcast(condition_variable_t *cp) {
+
+  chSysLock();
+  chCondBroadcastI(cp);
+  chSchRescheduleS();
+  chSysUnlock();
+}
+
+/**
+ * @brief   Signals all threads that are waiting on the condition variable.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] cp        pointer to the @p condition_variable_t structure
+ *
+ * @iclass
+ */
+void chCondBroadcastI(condition_variable_t *cp) {
+
+  chDbgCheckClassI();
+  chDbgCheck(cp != NULL);
+
+  /* Empties the condition variable queue and inserts all the threads into the
+     ready list in FIFO order. The wakeup message is set to @p MSG_RESET in
+     order to make a chCondBroadcast() detectable from a chCondSignal().*/
+  while (cp->c_queue.p_next != (void *)&cp->c_queue)
+    chSchReadyI(queue_fifo_remove(&cp->c_queue))->p_u.rdymsg = MSG_RESET;
+}
+
+/**
+ * @brief   Waits on the condition variable releasing the mutex lock.
+ * @details Releases the currently owned mutex, waits on the condition
+ *          variable, and finally acquires the mutex again. All the sequence
+ *          is performed atomically.
+ * @pre     The invoking thread <b>must</b> have at least one owned mutex.
+ *
+ * @param[in] cp        pointer to the @p condition_variable_t structure
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the condition variable.
+ * @retval MSG_OK       if the condition variable has been signaled using
+ *                      @p chCondSignal().
+ * @retval MSG_RESET    if the condition variable has been signaled using
+ *                      @p chCondBroadcast().
+ *
+ * @api
+ */
+msg_t chCondWait(condition_variable_t *cp) {
+  msg_t msg;
+
+  chSysLock();
+  msg = chCondWaitS(cp);
+  chSysUnlock();
+  return msg;
+}
+
+/**
+ * @brief   Waits on the condition variable releasing the mutex lock.
+ * @details Releases the currently owned mutex, waits on the condition
+ *          variable, and finally acquires the mutex again. All the sequence
+ *          is performed atomically.
+ * @pre     The invoking thread <b>must</b> have at least one owned mutex.
+ *
+ * @param[in] cp        pointer to the @p condition_variable_t structure
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the condition variable.
+ * @retval MSG_OK       if the condition variable has been signaled using
+ *                      @p chCondSignal().
+ * @retval MSG_RESET    if the condition variable has been signaled using
+ *                      @p chCondBroadcast().
+ *
+ * @sclass
+ */
+msg_t chCondWaitS(condition_variable_t *cp) {
+  thread_t *ctp = currp;
+  mutex_t *mp;
+  msg_t msg;
+
+  chDbgCheckClassS();
+  chDbgCheck(cp != NULL);
+  chDbgAssert(ctp->p_mtxlist != NULL, "not owning a mutex");
+
+  mp = chMtxGetNextMutexS();
+  chMtxUnlockS(mp);
+  ctp->p_u.wtobjp = cp;
+  queue_prio_insert(ctp, &cp->c_queue);
+  chSchGoSleepS(CH_STATE_WTCOND);
+  msg = ctp->p_u.rdymsg;
+  chMtxLockS(mp);
+  return msg;
+}
+
+#if CH_CFG_USE_CONDVARS_TIMEOUT || defined(__DOXYGEN__)
+/**
+ * @brief   Waits on the condition variable releasing the mutex lock.
+ * @details Releases the currently owned mutex, waits on the condition
+ *          variable, and finally acquires the mutex again. All the sequence
+ *          is performed atomically.
+ * @pre     The invoking thread <b>must</b> have at least one owned mutex.
+ * @pre     The configuration option @p CH_CFG_USE_CONDVARS_TIMEOUT must be enabled
+ *          in order to use this function.
+ * @post    Exiting the function because a timeout does not re-acquire the
+ *          mutex, the mutex ownership is lost.
+ *
+ * @param[in] cp        pointer to the @p condition_variable_t structure
+ * @param[in] time      the number of ticks before the operation timeouts, the
+ *                      special values are handled as follow:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the condition variable.
+ * @retval MSG_OK       if the condition variable has been signaled using
+ *                      @p chCondSignal().
+ * @retval MSG_RESET    if the condition variable has been signaled using
+ *                      @p chCondBroadcast().
+ * @retval MSG_TIMEOUT  if the condition variable has not been signaled within
+ *                      the specified timeout.
+ *
+ * @api
+ */
+msg_t chCondWaitTimeout(condition_variable_t *cp, systime_t time) {
+  msg_t msg;
+
+  chSysLock();
+  msg = chCondWaitTimeoutS(cp, time);
+  chSysUnlock();
+  return msg;
+}
+
+/**
+ * @brief   Waits on the condition variable releasing the mutex lock.
+ * @details Releases the currently owned mutex, waits on the condition
+ *          variable, and finally acquires the mutex again. All the sequence
+ *          is performed atomically.
+ * @pre     The invoking thread <b>must</b> have at least one owned mutex.
+ * @pre     The configuration option @p CH_CFG_USE_CONDVARS_TIMEOUT must be enabled
+ *          in order to use this function.
+ * @post    Exiting the function because a timeout does not re-acquire the
+ *          mutex, the mutex ownership is lost.
+ *
+ * @param[in] cp        pointer to the @p condition_variable_t structure
+ * @param[in] time      the number of ticks before the operation timeouts, the
+ *                      special values are handled as follow:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the condition variable.
+ * @retval MSG_OK       if the condition variable has been signaled using
+ *                      @p chCondSignal().
+ * @retval MSG_RESET    if the condition variable has been signaled using
+ *                      @p chCondBroadcast().
+ * @retval MSG_TIMEOUT  if the condition variable has not been signaled within
+ *                      the specified timeout.
+ *
+ * @sclass
+ */
+msg_t chCondWaitTimeoutS(condition_variable_t *cp, systime_t time) {
+  mutex_t *mp;
+  msg_t msg;
+
+  chDbgCheckClassS();
+  chDbgCheck((cp != NULL) && (time != TIME_IMMEDIATE));
+  chDbgAssert(currp->p_mtxlist != NULL, "not owning a mutex");
+
+  mp = chMtxGetNextMutexS();
+  chMtxUnlockS(mp);
+  currp->p_u.wtobjp = cp;
+  queue_prio_insert(currp, &cp->c_queue);
+  msg = chSchGoSleepTimeoutS(CH_STATE_WTCOND, time);
+  if (msg != MSG_TIMEOUT)
+    chMtxLockS(mp);
+  return msg;
+}
+#endif /* CH_CFG_USE_CONDVARS_TIMEOUT */
+
+#endif /* CH_CFG_USE_CONDVARS */
+
+/** @} */
diff --git a/os/rt/src/chdebug.c b/os/rt/src/chdebug.c
new file mode 100644
index 000000000..696a293cd
--- /dev/null
+++ b/os/rt/src/chdebug.c
@@ -0,0 +1,247 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chdebug.c
+ * @brief   ChibiOS/RT Debug code.
+ *
+ * @addtogroup debug
+ * @details Debug APIs and services:
+ *          - Runtime system state and call protocol check. The following
+ *            panic messages can be generated:
+ *            - SV#1, misplaced @p chSysDisable().
+ *            - SV#2, misplaced @p chSysSuspend()
+ *            - SV#3, misplaced @p chSysEnable().
+ *            - SV#4, misplaced @p chSysLock().
+ *            - SV#5, misplaced @p chSysUnlock().
+ *            - SV#6, misplaced @p chSysLockFromIsr().
+ *            - SV#7, misplaced @p chSysUnlockFromIsr().
+ *            - SV#8, misplaced @p CH_IRQ_PROLOGUE().
+ *            - SV#9, misplaced @p CH_IRQ_EPILOGUE().
+ *            - SV#10, misplaced I-class function.
+ *            - SV#11, misplaced S-class function.
+ *            .
+ *          - Trace buffer.
+ *          - Parameters check.
+ *          - Kernel assertions.
+ *          - Kernel panics.
+ *          .
+ * @note    Stack checks are not implemented in this module but in the port
+ *          layer in an architecture-dependent way.
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+#if CH_DBG_SYSTEM_STATE_CHECK || defined(__DOXYGEN__)
+/**
+ * @brief   Guard code for @p chSysDisable().
+ *
+ * @notapi
+ */
+void _dbg_check_disable(void) {
+
+  if ((ch.dbg_isr_cnt != 0) || (ch.dbg_lock_cnt != 0))
+    chSysHalt("SV#1");
+}
+
+/**
+ * @brief   Guard code for @p chSysSuspend().
+ *
+ * @notapi
+ */
+void _dbg_check_suspend(void) {
+
+  if ((ch.dbg_isr_cnt != 0) || (ch.dbg_lock_cnt != 0))
+    chSysHalt("SV#2");
+}
+
+/**
+ * @brief   Guard code for @p chSysEnable().
+ *
+ * @notapi
+ */
+void _dbg_check_enable(void) {
+
+  if ((ch.dbg_isr_cnt != 0) || (ch.dbg_lock_cnt != 0))
+    chSysHalt("SV#3");
+}
+
+/**
+ * @brief   Guard code for @p chSysLock().
+ *
+ * @notapi
+ */
+void _dbg_check_lock(void) {
+
+  if ((ch.dbg_isr_cnt != 0) || (ch.dbg_lock_cnt != 0))
+    chSysHalt("SV#4");
+  _dbg_enter_lock();
+}
+
+/**
+ * @brief   Guard code for @p chSysUnlock().
+ *
+ * @notapi
+ */
+void _dbg_check_unlock(void) {
+
+  if ((ch.dbg_isr_cnt != 0) || (ch.dbg_lock_cnt <= 0))
+    chSysHalt("SV#5");
+  _dbg_leave_lock();
+}
+
+/**
+ * @brief   Guard code for @p chSysLockFromIsr().
+ *
+ * @notapi
+ */
+void _dbg_check_lock_from_isr(void) {
+
+  if ((ch.dbg_isr_cnt <= 0) || (ch.dbg_lock_cnt != 0))
+    chSysHalt("SV#6");
+  _dbg_enter_lock();
+}
+
+/**
+ * @brief   Guard code for @p chSysUnlockFromIsr().
+ *
+ * @notapi
+ */
+void _dbg_check_unlock_from_isr(void) {
+
+  if ((ch.dbg_isr_cnt <= 0) || (ch.dbg_lock_cnt <= 0))
+    chSysHalt("SV#7");
+  _dbg_leave_lock();
+}
+
+/**
+ * @brief   Guard code for @p CH_IRQ_PROLOGUE().
+ *
+ * @notapi
+ */
+void _dbg_check_enter_isr(void) {
+
+  port_lock_from_isr();
+  if ((ch.dbg_isr_cnt < 0) || (ch.dbg_lock_cnt != 0))
+    chSysHalt("SV#8");
+  ch.dbg_isr_cnt++;
+  port_unlock_from_isr();
+}
+
+/**
+ * @brief   Guard code for @p CH_IRQ_EPILOGUE().
+ *
+ * @notapi
+ */
+void _dbg_check_leave_isr(void) {
+
+  port_lock_from_isr();
+  if ((ch.dbg_isr_cnt <= 0) || (ch.dbg_lock_cnt != 0))
+    chSysHalt("SV#9");
+  ch.dbg_isr_cnt--;
+  port_unlock_from_isr();
+}
+
+/**
+ * @brief   I-class functions context check.
+ * @details Verifies that the system is in an appropriate state for invoking
+ *          an I-class API function. A panic is generated if the state is
+ *          not compatible.
+ *
+ * @api
+ */
+void chDbgCheckClassI(void) {
+
+  if ((ch.dbg_isr_cnt < 0) || (ch.dbg_lock_cnt <= 0))
+    chSysHalt("SV#10");
+}
+
+/**
+ * @brief   S-class functions context check.
+ * @details Verifies that the system is in an appropriate state for invoking
+ *          an S-class API function. A panic is generated if the state is
+ *          not compatible.
+ *
+ * @api
+ */
+void chDbgCheckClassS(void) {
+
+  if ((ch.dbg_isr_cnt != 0) || (ch.dbg_lock_cnt <= 0))
+    chSysHalt("SV#11");
+}
+
+#endif /* CH_DBG_SYSTEM_STATE_CHECK */
+
+#if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)
+/**
+ * @brief   Trace circular buffer subsystem initialization.
+ * @note    Internal use only.
+ */
+void _trace_init(void) {
+
+  ch.dbg_trace_buffer.tb_size = CH_DBG_TRACE_BUFFER_SIZE;
+  ch.dbg_trace_buffer.tb_ptr = &ch.dbg_trace_buffer.tb_buffer[0];
+}
+
+/**
+ * @brief   Inserts in the circular debug trace buffer a context switch record.
+ *
+ * @param[in] otp       the thread being switched out
+ *
+ * @notapi
+ */
+void _dbg_trace(thread_t *otp) {
+
+  ch.dbg_trace_buffer.tb_ptr->se_time   = chVTGetSystemTimeX();
+  ch.dbg_trace_buffer.tb_ptr->se_tp     = currp;
+  ch.dbg_trace_buffer.tb_ptr->se_wtobjp = otp->p_u.wtobjp;
+  ch.dbg_trace_buffer.tb_ptr->se_state  = (uint8_t)otp->p_state;
+  if (++ch.dbg_trace_buffer.tb_ptr >=
+      &ch.dbg_trace_buffer.tb_buffer[CH_DBG_TRACE_BUFFER_SIZE])
+    ch.dbg_trace_buffer.tb_ptr = &ch.dbg_trace_buffer.tb_buffer[0];
+}
+#endif /* CH_DBG_ENABLE_TRACE */
+
+/** @} */
diff --git a/os/rt/src/chdynamic.c b/os/rt/src/chdynamic.c
new file mode 100644
index 000000000..5dbea6c7e
--- /dev/null
+++ b/os/rt/src/chdynamic.c
@@ -0,0 +1,228 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chdynamic.c
+ * @brief   Dynamic threads code.
+ *
+ * @addtogroup dynamic_threads
+ * @details Dynamic threads related APIs and services.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_DYNAMIC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Adds a reference to a thread object.
+ * @pre     The configuration option @p CH_CFG_USE_DYNAMIC must be enabled in order
+ *          to use this function.
+ *
+ * @param[in] tp        pointer to the thread
+ * @return              The same thread pointer passed as parameter
+ *                      representing the new reference.
+ *
+ * @api
+ */
+thread_t *chThdAddRef(thread_t *tp) {
+
+  chSysLock();
+  chDbgAssert(tp->p_refs < 255, "too many references");
+  tp->p_refs++;
+  chSysUnlock();
+  return tp;
+}
+
+/**
+ * @brief   Releases a reference to a thread object.
+ * @details If the references counter reaches zero <b>and</b> the thread
+ *          is in the @p CH_STATE_FINAL state then the thread's memory is
+ *          returned to the proper allocator.
+ * @pre     The configuration option @p CH_CFG_USE_DYNAMIC must be enabled in order
+ *          to use this function.
+ * @note    Static threads are not affected.
+ *
+ * @param[in] tp        pointer to the thread
+ *
+ * @api
+ */
+void chThdRelease(thread_t *tp) {
+  trefs_t refs;
+
+  chSysLock();
+  chDbgAssert(tp->p_refs > 0, "not referenced");
+  refs = --tp->p_refs;
+  chSysUnlock();
+
+  /* If the references counter reaches zero and the thread is in its
+     terminated state then the memory can be returned to the proper
+     allocator. Of course static threads are not affected.*/
+  if ((refs == 0) && (tp->p_state == CH_STATE_FINAL)) {
+    switch (tp->p_flags & CH_FLAG_MODE_MASK) {
+#if CH_CFG_USE_HEAP
+    case CH_FLAG_MODE_HEAP:
+#if CH_CFG_USE_REGISTRY
+      REG_REMOVE(tp);
+#endif
+      chHeapFree(tp);
+      break;
+#endif
+#if CH_CFG_USE_MEMPOOLS
+    case CH_FLAG_MODE_MEMPOOL:
+#if CH_CFG_USE_REGISTRY
+      REG_REMOVE(tp);
+#endif
+      chPoolFree(tp->p_mpool, tp);
+      break;
+#endif
+    }
+  }
+}
+
+#if CH_CFG_USE_HEAP || defined(__DOXYGEN__)
+/**
+ * @brief   Creates a new thread allocating the memory from the heap.
+ * @pre     The configuration options @p CH_CFG_USE_DYNAMIC and @p CH_CFG_USE_HEAP
+ *          must be enabled in order to use this function.
+ * @note    A thread can terminate by calling @p chThdExit() or by simply
+ *          returning from its main function.
+ * @note    The memory allocated for the thread is not released when the thread
+ *          terminates but when a @p chThdWait() is performed.
+ *
+ * @param[in] heapp     heap from which allocate the memory or @p NULL for the
+ *                      default heap
+ * @param[in] size      size of the working area to be allocated
+ * @param[in] prio      the priority level for the new thread
+ * @param[in] pf        the thread function
+ * @param[in] arg       an argument passed to the thread function. It can be
+ *                      @p NULL.
+ * @return              The pointer to the @p thread_t structure allocated for
+ *                      the thread into the working space area.
+ * @retval NULL         if the memory cannot be allocated.
+ *
+ * @api
+ */
+thread_t *chThdCreateFromHeap(memory_heap_t *heapp, size_t size,
+                              tprio_t prio, tfunc_t pf, void *arg) {
+  void *wsp;
+  thread_t *tp;
+
+  wsp = chHeapAlloc(heapp, size);
+  if (wsp == NULL)
+    return NULL;
+  
+#if CH_DBG_FILL_THREADS
+  _thread_memfill((uint8_t *)wsp,
+                  (uint8_t *)wsp + sizeof(thread_t),
+                  CH_DBG_THREAD_FILL_VALUE);
+  _thread_memfill((uint8_t *)wsp + sizeof(thread_t),
+                  (uint8_t *)wsp + size,
+                  CH_DBG_STACK_FILL_VALUE);
+#endif
+  
+  chSysLock();
+  tp = chThdCreateI(wsp, size, prio, pf, arg);
+  tp->p_flags = CH_FLAG_MODE_HEAP;
+  chSchWakeupS(tp, MSG_OK);
+  chSysUnlock();
+  return tp;
+}
+#endif /* CH_CFG_USE_HEAP */
+
+#if CH_CFG_USE_MEMPOOLS || defined(__DOXYGEN__)
+/**
+ * @brief   Creates a new thread allocating the memory from the specified
+ *          memory pool.
+ * @pre     The configuration options @p CH_CFG_USE_DYNAMIC and @p CH_CFG_USE_MEMPOOLS
+ *          must be enabled in order to use this function.
+ * @note    A thread can terminate by calling @p chThdExit() or by simply
+ *          returning from its main function.
+ * @note    The memory allocated for the thread is not released when the thread
+ *          terminates but when a @p chThdWait() is performed.
+ *
+ * @param[in] mp        pointer to the memory pool object
+ * @param[in] prio      the priority level for the new thread
+ * @param[in] pf        the thread function
+ * @param[in] arg       an argument passed to the thread function. It can be
+ *                      @p NULL.
+ * @return              The pointer to the @p thread_t structure allocated for
+ *                      the thread into the working space area.
+ * @retval  NULL        if the memory pool is empty.
+ *
+ * @api
+ */
+thread_t *chThdCreateFromMemoryPool(memory_pool_t *mp, tprio_t prio,
+                                    tfunc_t pf, void *arg) {
+  void *wsp;
+  thread_t *tp;
+
+  chDbgCheck(mp != NULL);
+
+  wsp = chPoolAlloc(mp);
+  if (wsp == NULL)
+    return NULL;
+  
+#if CH_DBG_FILL_THREADS
+  _thread_memfill((uint8_t *)wsp,
+                  (uint8_t *)wsp + sizeof(thread_t),
+                  CH_DBG_THREAD_FILL_VALUE);
+  _thread_memfill((uint8_t *)wsp + sizeof(thread_t),
+                  (uint8_t *)wsp + mp->mp_object_size,
+                  CH_DBG_STACK_FILL_VALUE);
+#endif
+
+  chSysLock();
+  tp = chThdCreateI(wsp, mp->mp_object_size, prio, pf, arg);
+  tp->p_flags = CH_FLAG_MODE_MEMPOOL;
+  tp->p_mpool = mp;
+  chSchWakeupS(tp, MSG_OK);
+  chSysUnlock();
+  return tp;
+}
+#endif /* CH_CFG_USE_MEMPOOLS */
+
+#endif /* CH_CFG_USE_DYNAMIC */
+
+/** @} */
diff --git a/os/rt/src/chevents.c b/os/rt/src/chevents.c
new file mode 100644
index 000000000..389e2505b
--- /dev/null
+++ b/os/rt/src/chevents.c
@@ -0,0 +1,575 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/*
+   Concepts and parts of this file have been contributed by Scott (skute).
+ */
+
+/**
+ * @file    chevents.c
+ * @brief   Events code.
+ *
+ * @addtogroup events
+ * @details Event Flags, Event Sources and Event Listeners.
+ *          <h2>Operation mode</h2>
+ *          Each thread has a mask of pending event flags inside its
+ *          @p thread_t structure.
+ *          Operations defined for event flags:
+ *          - <b>Wait</b>, the invoking thread goes to sleep until a certain
+ *            AND/OR combination of event flags becomes pending.
+ *          - <b>Clear</b>, a mask of event flags is cleared from the pending
+ *            events mask, the cleared event flags mask is returned (only the
+ *            flags that were actually pending and then cleared).
+ *          - <b>Signal</b>, an event mask is directly ORed to the mask of the
+ *            signaled thread.
+ *          - <b>Broadcast</b>, each thread registered on an Event Source is
+ *            signaled with the event flags specified in its Event Listener.
+ *          - <b>Dispatch</b>, an events mask is scanned and for each bit set
+ *            to one an associated handler function is invoked. Bit masks are
+ *            scanned from bit zero upward.
+ *          .
+ *          An Event Source is a special object that can be "broadcasted" by
+ *          a thread or an interrupt service routine. Broadcasting an Event
+ *          Source has the effect that all the threads registered on the
+ *          Event Source will be signaled with an events mask.<br>
+ *          An unlimited number of Event Sources can exists in a system and
+ *          each thread can be listening on an unlimited number of
+ *          them.
+ * @pre     In order to use the Events APIs the @p CH_CFG_USE_EVENTS option must be
+ *          enabled in @p chconf.h.
+ * @post    Enabling events requires 1-4 (depending on the architecture)
+ *          extra bytes in the @p thread_t structure.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_EVENTS || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Registers an Event Listener on an Event Source.
+ * @details Once a thread has registered as listener on an event source it
+ *          will be notified of all events broadcasted there.
+ * @note    Multiple Event Listeners can specify the same bits to be ORed to
+ *          different threads.
+ *
+ * @param[in] esp       pointer to the  @p event_source_t structure
+ * @param[in] elp       pointer to the @p event_listener_t structure
+ * @param[in] mask      the mask of event flags to be ORed to the thread when
+ *                      the event source is broadcasted
+ *
+ * @api
+ */
+void chEvtRegisterMask(event_source_t *esp,
+                       event_listener_t *elp,
+                       eventmask_t mask) {
+
+  chDbgCheck((esp != NULL) && (elp != NULL));
+
+  chSysLock();
+  elp->el_next     = esp->es_next;
+  esp->es_next     = elp;
+  elp->el_listener = currp;
+  elp->el_mask     = mask;
+  elp->el_flags    = 0;
+  chSysUnlock();
+}
+
+/**
+ * @brief   Unregisters an Event Listener from its Event Source.
+ * @note    If the event listener is not registered on the specified event
+ *          source then the function does nothing.
+ * @note    For optimal performance it is better to perform the unregister
+ *          operations in inverse order of the register operations (elements
+ *          are found on top of the list).
+ *
+ * @param[in] esp       pointer to the  @p event_source_t structure
+ * @param[in] elp       pointer to the @p event_listener_t structure
+ *
+ * @api
+ */
+void chEvtUnregister(event_source_t *esp, event_listener_t *elp) {
+  event_listener_t *p;
+
+  chDbgCheck((esp != NULL) && (elp != NULL));
+
+  p = (event_listener_t *)esp;
+  chSysLock();
+  while (p->el_next != (event_listener_t *)esp) {
+    if (p->el_next == elp) {
+      p->el_next = elp->el_next;
+      break;
+    }
+    p = p->el_next;
+  }
+  chSysUnlock();
+}
+
+/**
+ * @brief   Clears the pending events specified in the mask.
+ *
+ * @param[in] mask      the events to be cleared
+ * @return              The pending events that were cleared.
+ *
+ * @api
+ */
+eventmask_t chEvtGetAndClearEvents(eventmask_t mask) {
+  eventmask_t m;
+
+  chSysLock();
+
+  m = currp->p_epending & mask;
+  currp->p_epending &= ~mask;
+
+  chSysUnlock();
+  return m;
+}
+
+/**
+ * @brief   Adds (OR) a set of event flags on the current thread, this is
+ *          @b much faster than using @p chEvtBroadcast() or @p chEvtSignal().
+ *
+ * @param[in] mask      the event flags to be added
+ * @return              The current pending events mask.
+ *
+ * @api
+ */
+eventmask_t chEvtAddEvents(eventmask_t mask) {
+
+  chSysLock();
+
+  mask = (currp->p_epending |= mask);
+
+  chSysUnlock();
+  return mask;
+}
+
+/**
+ * @brief   Signals all the Event Listeners registered on the specified Event
+ *          Source.
+ * @details This function variants ORs the specified event flags to all the
+ *          threads registered on the @p event_source_t in addition to the
+ *          event flags specified by the threads themselves in the
+ *          @p event_listener_t objects.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] esp       pointer to the @p event_source_t structure
+ * @param[in] flags     the flags set to be added to the listener flags mask
+ *
+ * @iclass
+ */
+void chEvtBroadcastFlagsI(event_source_t *esp, eventflags_t flags) {
+  event_listener_t *elp;
+
+  chDbgCheckClassI();
+  chDbgCheck(esp != NULL);
+
+  elp = esp->es_next;
+  while (elp != (event_listener_t *)esp) {
+    elp->el_flags |= flags;
+    chEvtSignalI(elp->el_listener, elp->el_mask);
+    elp = elp->el_next;
+  }
+}
+
+/**
+ * @brief   Returns the flags associated to an @p event_listener_t.
+ * @details The flags are returned and the @p event_listener_t flags mask is
+ *          cleared.
+ *
+ * @param[in] elp       pointer to the @p event_listener_t structure
+ * @return              The flags added to the listener by the associated
+ *                      event source.
+ *
+ * @api
+ */
+eventflags_t chEvtGetAndClearFlags(event_listener_t *elp) {
+  eventflags_t flags;
+
+  chSysLock();
+
+  flags = elp->el_flags;
+  elp->el_flags = 0;
+
+  chSysUnlock();
+  return flags;
+}
+
+/**
+ * @brief   Adds a set of event flags directly to the specified @p thread_t.
+ *
+ * @param[in] tp        the thread to be signaled
+ * @param[in] mask      the event flags set to be ORed
+ *
+ * @api
+ */
+void chEvtSignal(thread_t *tp, eventmask_t mask) {
+
+  chDbgCheck(tp != NULL);
+
+  chSysLock();
+  chEvtSignalI(tp, mask);
+  chSchRescheduleS();
+  chSysUnlock();
+}
+
+/**
+ * @brief   Adds a set of event flags directly to the specified @p thread_t.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] tp        the thread to be signaled
+ * @param[in] mask      the event flags set to be ORed
+ *
+ * @iclass
+ */
+void chEvtSignalI(thread_t *tp, eventmask_t mask) {
+
+  chDbgCheckClassI();
+  chDbgCheck(tp != NULL);
+
+  tp->p_epending |= mask;
+  /* Test on the AND/OR conditions wait states.*/
+  if (((tp->p_state == CH_STATE_WTOREVT) &&
+       ((tp->p_epending & tp->p_u.ewmask) != 0)) ||
+      ((tp->p_state == CH_STATE_WTANDEVT) &&
+       ((tp->p_epending & tp->p_u.ewmask) == tp->p_u.ewmask))) {
+    tp->p_u.rdymsg = MSG_OK;
+    chSchReadyI(tp);
+  }
+}
+
+/**
+ * @brief   Signals all the Event Listeners registered on the specified Event
+ *          Source.
+ * @details This function variants ORs the specified event flags to all the
+ *          threads registered on the @p event_source_t in addition to the
+ *          event flags specified by the threads themselves in the
+ *          @p event_listener_t objects.
+ *
+ * @param[in] esp       pointer to the @p event_source_t structure
+ * @param[in] flags     the flags set to be added to the listener flags mask
+ *
+ * @api
+ */
+void chEvtBroadcastFlags(event_source_t *esp, eventflags_t flags) {
+
+  chSysLock();
+  chEvtBroadcastFlagsI(esp, flags);
+  chSchRescheduleS();
+  chSysUnlock();
+}
+
+/**
+ * @brief   Returns the flags associated to an @p event_listener_t.
+ * @details The flags are returned and the @p event_listener_t flags mask is
+ *          cleared.
+ *
+ * @param[in] elp       pointer to the @p event_listener_t structure
+ * @return              The flags added to the listener by the associated
+ *                      event source.
+ *
+ * @iclass
+ */
+eventflags_t chEvtGetAndClearFlagsI(event_listener_t *elp) {
+  eventflags_t flags;
+
+  flags = elp->el_flags;
+  elp->el_flags = 0;
+
+  return flags;
+}
+
+/**
+ * @brief   Invokes the event handlers associated to an event flags mask.
+ *
+ * @param[in] mask      mask of the event flags to be dispatched
+ * @param[in] handlers  an array of @p evhandler_t. The array must have size
+ *                      equal to the number of bits in eventmask_t.
+ *
+ * @api
+ */
+void chEvtDispatch(const evhandler_t *handlers, eventmask_t mask) {
+  eventid_t eid;
+
+  chDbgCheck(handlers != NULL);
+
+  eid = 0;
+  while (mask) {
+    if (mask & EVENT_MASK(eid)) {
+      chDbgAssert(handlers[eid] != NULL, "null handler");
+      mask &= ~EVENT_MASK(eid);
+      handlers[eid](eid);
+    }
+    eid++;
+  }
+}
+
+#if CH_CFG_OPTIMIZE_SPEED || !CH_CFG_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__)
+/**
+ * @brief   Waits for exactly one of the specified events.
+ * @details The function waits for one event among those specified in
+ *          @p mask to become pending then the event is cleared and returned.
+ * @note    One and only one event is served in the function, the one with the
+ *          lowest event id. The function is meant to be invoked into a loop in
+ *          order to serve all the pending events.<br>
+ *          This means that Event Listeners with a lower event identifier have
+ *          an higher priority.
+ *
+ * @param[in] mask      mask of the event flags that the function should wait
+ *                      for, @p ALL_EVENTS enables all the events
+ * @return              The mask of the lowest id served and cleared event.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitOne(eventmask_t mask) {
+  thread_t *ctp = currp;
+  eventmask_t m;
+
+  chSysLock();
+
+  if ((m = (ctp->p_epending & mask)) == 0) {
+    ctp->p_u.ewmask = mask;
+    chSchGoSleepS(CH_STATE_WTOREVT);
+    m = ctp->p_epending & mask;
+  }
+  m &= -m;
+  ctp->p_epending &= ~m;
+
+  chSysUnlock();
+  return m;
+}
+
+/**
+ * @brief   Waits for any of the specified events.
+ * @details The function waits for any event among those specified in
+ *          @p mask to become pending then the events are cleared and returned.
+ *
+ * @param[in] mask      mask of the event flags that the function should wait
+ *                      for, @p ALL_EVENTS enables all the events
+ * @return              The mask of the served and cleared events.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAny(eventmask_t mask) {
+  thread_t *ctp = currp;
+  eventmask_t m;
+
+  chSysLock();
+
+  if ((m = (ctp->p_epending & mask)) == 0) {
+    ctp->p_u.ewmask = mask;
+    chSchGoSleepS(CH_STATE_WTOREVT);
+    m = ctp->p_epending & mask;
+  }
+  ctp->p_epending &= ~m;
+
+  chSysUnlock();
+  return m;
+}
+
+/**
+ * @brief   Waits for all the specified events.
+ * @details The function waits for all the events specified in @p mask to
+ *          become pending then the events are cleared and returned.
+ *
+ * @param[in] mask      mask of the event flags that the function should wait
+ *                      for, @p ALL_EVENTS requires all the events
+ * @return              The mask of the served and cleared events.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAll(eventmask_t mask) {
+  thread_t *ctp = currp;
+
+  chSysLock();
+
+  if ((ctp->p_epending & mask) != mask) {
+    ctp->p_u.ewmask = mask;
+    chSchGoSleepS(CH_STATE_WTANDEVT);
+  }
+  ctp->p_epending &= ~mask;
+
+  chSysUnlock();
+  return mask;
+}
+#endif /* CH_CFG_OPTIMIZE_SPEED || !CH_CFG_USE_EVENTS_TIMEOUT */
+
+#if CH_CFG_USE_EVENTS_TIMEOUT || defined(__DOXYGEN__)
+/**
+ * @brief   Waits for exactly one of the specified events.
+ * @details The function waits for one event among those specified in
+ *          @p mask to become pending then the event is cleared and returned.
+ * @note    One and only one event is served in the function, the one with the
+ *          lowest event id. The function is meant to be invoked into a loop
+ *          in order to serve all the pending events.<br>
+ *          This means that Event Listeners with a lower event identifier have
+ *          an higher priority.
+ *
+ * @param[in] mask      mask of the event flags that the function should wait
+ *                      for, @p ALL_EVENTS enables all the events
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The mask of the lowest id served and cleared event.
+ * @retval 0            if the operation has timed out.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitOneTimeout(eventmask_t mask, systime_t time) {
+  thread_t *ctp = currp;
+  eventmask_t m;
+
+  chSysLock();
+
+  if ((m = (ctp->p_epending & mask)) == 0) {
+    if (TIME_IMMEDIATE == time) {
+      chSysUnlock();
+      return (eventmask_t)0;
+    }
+    ctp->p_u.ewmask = mask;
+    if (chSchGoSleepTimeoutS(CH_STATE_WTOREVT, time) < MSG_OK) {
+      chSysUnlock();
+      return (eventmask_t)0;
+    }
+    m = ctp->p_epending & mask;
+  }
+  m &= -m;
+  ctp->p_epending &= ~m;
+
+  chSysUnlock();
+  return m;
+}
+
+/**
+ * @brief   Waits for any of the specified events.
+ * @details The function waits for any event among those specified in
+ *          @p mask to become pending then the events are cleared and
+ *          returned.
+ *
+ * @param[in] mask      mask of the event flags that the function should wait
+ *                      for, @p ALL_EVENTS enables all the events
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The mask of the served and cleared events.
+ * @retval 0            if the operation has timed out.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAnyTimeout(eventmask_t mask, systime_t time) {
+  thread_t *ctp = currp;
+  eventmask_t m;
+
+  chSysLock();
+
+  if ((m = (ctp->p_epending & mask)) == 0) {
+    if (TIME_IMMEDIATE == time) {
+      chSysUnlock();
+      return (eventmask_t)0;
+    }
+    ctp->p_u.ewmask = mask;
+    if (chSchGoSleepTimeoutS(CH_STATE_WTOREVT, time) < MSG_OK) {
+      chSysUnlock();
+      return (eventmask_t)0;
+    }
+    m = ctp->p_epending & mask;
+  }
+  ctp->p_epending &= ~m;
+
+  chSysUnlock();
+  return m;
+}
+
+/**
+ * @brief   Waits for all the specified events.
+ * @details The function waits for all the events specified in @p mask to
+ *          become pending then the events are cleared and returned.
+ *
+ * @param[in] mask      mask of the event flags that the function should wait
+ *                      for, @p ALL_EVENTS requires all the events
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The mask of the served and cleared events.
+ * @retval 0            if the operation has timed out.
+ *
+ * @api
+ */
+eventmask_t chEvtWaitAllTimeout(eventmask_t mask, systime_t time) {
+  thread_t *ctp = currp;
+
+  chSysLock();
+
+  if ((ctp->p_epending & mask) != mask) {
+    if (TIME_IMMEDIATE == time) {
+      chSysUnlock();
+      return (eventmask_t)0;
+    }
+    ctp->p_u.ewmask = mask;
+    if (chSchGoSleepTimeoutS(CH_STATE_WTANDEVT, time) < MSG_OK) {
+      chSysUnlock();
+      return (eventmask_t)0;
+    }
+  }
+  ctp->p_epending &= ~mask;
+
+  chSysUnlock();
+  return mask;
+}
+#endif /* CH_CFG_USE_EVENTS_TIMEOUT */
+
+#endif /* CH_CFG_USE_EVENTS */
+
+/** @} */
diff --git a/os/rt/src/chheap.c b/os/rt/src/chheap.c
new file mode 100644
index 000000000..5e1e20c3c
--- /dev/null
+++ b/os/rt/src/chheap.c
@@ -0,0 +1,276 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chheap.c
+ * @brief   Heaps code.
+ *
+ * @addtogroup heaps
+ * @details Heap Allocator related APIs.
+ *          <h2>Operation mode</h2>
+ *          The heap allocator implements a first-fit strategy and its APIs
+ *          are functionally equivalent to the usual @p malloc() and @p free()
+ *          library functions. The main difference is that the OS heap APIs
+ *          are guaranteed to be thread safe.<br>
+ * @pre     In order to use the heap APIs the @p CH_CFG_USE_HEAP option must
+ *          be enabled in @p chconf.h.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_HEAP || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*
+ * Defaults on the best synchronization mechanism available.
+ */
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+#define H_LOCK(h)       chMtxLock(&(h)->h_mtx)
+#define H_UNLOCK(h)     chMtxUnlock(&(h)->h_mtx)
+#else
+#define H_LOCK(h)       chSemWait(&(h)->h_sem)
+#define H_UNLOCK(h)     chSemSignal(&(h)->h_sem)
+#endif
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Default heap descriptor.
+ */
+static memory_heap_t default_heap;
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the default heap.
+ *
+ * @notapi
+ */
+void _heap_init(void) {
+  default_heap.h_provider = chCoreAlloc;
+  default_heap.h_free.h.u.next = (union heap_header *)NULL;
+  default_heap.h_free.h.size = 0;
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+  chMtxObjectInit(&default_heap.h_mtx);
+#else
+  chSemObjectInit(&default_heap.h_sem, 1);
+#endif
+}
+
+/**
+ * @brief   Initializes a memory heap from a static memory area.
+ * @pre     Both the heap buffer base and the heap size must be aligned to
+ *          the @p stkalign_t type size.
+ *
+ * @param[out] heapp    pointer to the memory heap descriptor to be initialized
+ * @param[in] buf       heap buffer base
+ * @param[in] size      heap size
+ *
+ * @init
+ */
+void chHeapObjectInit(memory_heap_t *heapp, void *buf, size_t size) {
+  union heap_header *hp;
+
+  chDbgCheck(MEM_IS_ALIGNED(buf) && MEM_IS_ALIGNED(size));
+
+  heapp->h_provider = (memgetfunc_t)NULL;
+  heapp->h_free.h.u.next = hp = buf;
+  heapp->h_free.h.size = 0;
+  hp->h.u.next = NULL;
+  hp->h.size = size - sizeof(union heap_header);
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+  chMtxObjectInit(&heapp->h_mtx);
+#else
+  chSemObjectInit(&heapp->h_sem, 1);
+#endif
+}
+
+/**
+ * @brief   Allocates a block of memory from the heap by using the first-fit
+ *          algorithm.
+ * @details The allocated block is guaranteed to be properly aligned for a
+ *          pointer data type (@p stkalign_t).
+ *
+ * @param[in] heapp     pointer to a heap descriptor or @p NULL in order to
+ *                      access the default heap.
+ * @param[in] size      the size of the block to be allocated. Note that the
+ *                      allocated block may be a bit bigger than the requested
+ *                      size for alignment and fragmentation reasons.
+ * @return              A pointer to the allocated block.
+ * @retval NULL         if the block cannot be allocated.
+ *
+ * @api
+ */
+void *chHeapAlloc(memory_heap_t *heapp, size_t size) {
+  union heap_header *qp, *hp, *fp;
+
+  if (heapp == NULL)
+    heapp = &default_heap;
+
+  size = MEM_ALIGN_NEXT(size);
+  qp = &heapp->h_free;
+  H_LOCK(heapp);
+
+  while (qp->h.u.next != NULL) {
+    hp = qp->h.u.next;
+    if (hp->h.size >= size) {
+      if (hp->h.size < size + sizeof(union heap_header)) {
+        /* Gets the whole block even if it is slightly bigger than the
+           requested size because the fragment would be too small to be
+           useful.*/
+        qp->h.u.next = hp->h.u.next;
+      }
+      else {
+        /* Block bigger enough, must split it.*/
+        fp = (void *)((uint8_t *)(hp) + sizeof(union heap_header) + size);
+        fp->h.u.next = hp->h.u.next;
+        fp->h.size = hp->h.size - sizeof(union heap_header) - size;
+        qp->h.u.next = fp;
+        hp->h.size = size;
+      }
+      hp->h.u.heap = heapp;
+
+      H_UNLOCK(heapp);
+      return (void *)(hp + 1);
+    }
+    qp = hp;
+  }
+
+  H_UNLOCK(heapp);
+
+  /* More memory is required, tries to get it from the associated provider
+     else fails.*/
+  if (heapp->h_provider) {
+    hp = heapp->h_provider(size + sizeof(union heap_header));
+    if (hp != NULL) {
+      hp->h.u.heap = heapp;
+      hp->h.size = size;
+      hp++;
+      return (void *)hp;
+    }
+  }
+  return NULL;
+}
+
+#define LIMIT(p) (union heap_header *)((uint8_t *)(p) + \
+                                        sizeof(union heap_header) + \
+                                        (p)->h.size)
+
+/**
+ * @brief   Frees a previously allocated memory block.
+ *
+ * @param[in] p         pointer to the memory block to be freed
+ *
+ * @api
+ */
+void chHeapFree(void *p) {
+  union heap_header *qp, *hp;
+  memory_heap_t *heapp;
+
+  chDbgCheck(p != NULL);
+
+  hp = (union heap_header *)p - 1;
+  heapp = hp->h.u.heap;
+  qp = &heapp->h_free;
+  H_LOCK(heapp);
+
+  while (true) {
+    chDbgAssert((hp < qp) || (hp >= LIMIT(qp)), "within free block");
+
+    if (((qp == &heapp->h_free) || (hp > qp)) &&
+        ((qp->h.u.next == NULL) || (hp < qp->h.u.next))) {
+      /* Insertion after qp.*/
+      hp->h.u.next = qp->h.u.next;
+      qp->h.u.next = hp;
+      /* Verifies if the newly inserted block should be merged.*/
+      if (LIMIT(hp) == hp->h.u.next) {
+        /* Merge with the next block.*/
+        hp->h.size += hp->h.u.next->h.size + sizeof(union heap_header);
+        hp->h.u.next = hp->h.u.next->h.u.next;
+      }
+      if ((LIMIT(qp) == hp)) {
+        /* Merge with the previous block.*/
+        qp->h.size += hp->h.size + sizeof(union heap_header);
+        qp->h.u.next = hp->h.u.next;
+      }
+      break;
+    }
+    qp = qp->h.u.next;
+  }
+
+  H_UNLOCK(heapp);
+  return;
+}
+
+/**
+ * @brief   Reports the heap status.
+ * @note    This function is meant to be used in the test suite, it should
+ *          not be really useful for the application code.
+ *
+ * @param[in] heapp     pointer to a heap descriptor or @p NULL in order to
+ *                      access the default heap.
+ * @param[in] sizep     pointer to a variable that will receive the total
+ *                      fragmented free space
+ * @return              The number of fragments in the heap.
+ *
+ * @api
+ */
+size_t chHeapStatus(memory_heap_t *heapp, size_t *sizep) {
+  union heap_header *qp;
+  size_t n, sz;
+
+  if (heapp == NULL)
+    heapp = &default_heap;
+
+  H_LOCK(heapp);
+
+  sz = 0;
+  for (n = 0, qp = &heapp->h_free; qp->h.u.next; n++, qp = qp->h.u.next)
+    sz += qp->h.u.next->h.size;
+  if (sizep)
+    *sizep = sz;
+
+  H_UNLOCK(heapp);
+  return n;
+}
+
+#endif /* CH_CFG_USE_HEAP */
+
+/** @} */
diff --git a/os/rt/src/chmboxes.c b/os/rt/src/chmboxes.c
new file mode 100644
index 000000000..8e9e2bb40
--- /dev/null
+++ b/os/rt/src/chmboxes.c
@@ -0,0 +1,398 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmboxes.c
+ * @brief   Mailboxes code.
+ *
+ * @addtogroup mailboxes
+ * @details Asynchronous messages.
+ *          <h2>Operation mode</h2>
+ *          A mailbox is an asynchronous communication mechanism.<br>
+ *          Operations defined for mailboxes:
+ *          - <b>Post</b>: Posts a message on the mailbox in FIFO order.
+ *          - <b>Post Ahead</b>: Posts a message on the mailbox with urgent
+ *            priority.
+ *          - <b>Fetch</b>: A message is fetched from the mailbox and removed
+ *            from the queue.
+ *          - <b>Reset</b>: The mailbox is emptied and all the stored messages
+ *            are lost.
+ *          .
+ *          A message is a variable of type msg_t that is guaranteed to have
+ *          the same size of and be compatible with (data) pointers (anyway an
+ *          explicit cast is needed).
+ *          If larger messages need to be exchanged then a pointer to a
+ *          structure can be posted in the mailbox but the posting side has
+ *          no predefined way to know when the message has been processed. A
+ *          possible approach is to allocate memory (from a memory pool for
+ *          example) from the posting side and free it on the fetching side.
+ *          Another approach is to set a "done" flag into the structure pointed
+ *          by the message.
+ * @pre     In order to use the mailboxes APIs the @p CH_CFG_USE_MAILBOXES option
+ *          must be enabled in @p chconf.h.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_MAILBOXES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes a @p mailbox_t object.
+ *
+ * @param[out] mbp      the pointer to the @p mailbox_t structure to be
+ *                      initialized
+ * @param[in] buf       pointer to the messages buffer as an array of @p msg_t
+ * @param[in] n         number of elements in the buffer array
+ *
+ * @init
+ */
+void chMBObjectInit(mailbox_t *mbp, msg_t *buf, cnt_t n) {
+
+  chDbgCheck((mbp != NULL) && (buf != NULL) && (n > 0));
+
+  mbp->mb_buffer = mbp->mb_wrptr = mbp->mb_rdptr = buf;
+  mbp->mb_top = &buf[n];
+  chSemObjectInit(&mbp->mb_emptysem, n);
+  chSemObjectInit(&mbp->mb_fullsem, 0);
+}
+
+/**
+ * @brief   Resets a @p mailbox_t object.
+ * @details All the waiting threads are resumed with status @p MSG_RESET and
+ *          the queued messages are lost.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ *
+ * @api
+ */
+void chMBReset(mailbox_t *mbp) {
+
+  chDbgCheck(mbp != NULL);
+
+  chSysLock();
+  mbp->mb_wrptr = mbp->mb_rdptr = mbp->mb_buffer;
+  chSemResetI(&mbp->mb_emptysem, mbp->mb_top - mbp->mb_buffer);
+  chSemResetI(&mbp->mb_fullsem, 0);
+  chSchRescheduleS();
+  chSysUnlock();
+}
+
+/**
+ * @brief   Posts a message into a mailbox.
+ * @details The invoking thread waits until a empty slot in the mailbox becomes
+ *          available or the specified time runs out.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ * @param[in] msg       the message to be posted on the mailbox
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if a message has been correctly posted.
+ * @retval MSG_RESET    if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT  if the operation has timed out.
+ *
+ * @api
+ */
+msg_t chMBPost(mailbox_t *mbp, msg_t msg, systime_t time) {
+  msg_t rdymsg;
+
+  chSysLock();
+  rdymsg = chMBPostS(mbp, msg, time);
+  chSysUnlock();
+  return rdymsg;
+}
+
+/**
+ * @brief   Posts a message into a mailbox.
+ * @details The invoking thread waits until a empty slot in the mailbox becomes
+ *          available or the specified time runs out.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ * @param[in] msg       the message to be posted on the mailbox
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if a message has been correctly posted.
+ * @retval MSG_RESET    if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT  if the operation has timed out.
+ *
+ * @sclass
+ */
+msg_t chMBPostS(mailbox_t *mbp, msg_t msg, systime_t time) {
+  msg_t rdymsg;
+
+  chDbgCheckClassS();
+  chDbgCheck(mbp != NULL);
+
+  rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time);
+  if (rdymsg == MSG_OK) {
+    *mbp->mb_wrptr++ = msg;
+    if (mbp->mb_wrptr >= mbp->mb_top)
+      mbp->mb_wrptr = mbp->mb_buffer;
+    chSemSignalI(&mbp->mb_fullsem);
+    chSchRescheduleS();
+  }
+  return rdymsg;
+}
+
+/**
+ * @brief   Posts a message into a mailbox.
+ * @details This variant is non-blocking, the function returns a timeout
+ *          condition if the queue is full.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ * @param[in] msg       the message to be posted on the mailbox
+ * @return              The operation status.
+ * @retval MSG_OK       if a message has been correctly posted.
+ * @retval MSG_TIMEOUT  if the mailbox is full and the message cannot be
+ *                      posted.
+ *
+ * @iclass
+ */
+msg_t chMBPostI(mailbox_t *mbp, msg_t msg) {
+
+  chDbgCheckClassI();
+  chDbgCheck(mbp != NULL);
+
+  if (chSemGetCounterI(&mbp->mb_emptysem) <= 0)
+    return MSG_TIMEOUT;
+  chSemFastWaitI(&mbp->mb_emptysem);
+  *mbp->mb_wrptr++ = msg;
+  if (mbp->mb_wrptr >= mbp->mb_top)
+    mbp->mb_wrptr = mbp->mb_buffer;
+  chSemSignalI(&mbp->mb_fullsem);
+  return MSG_OK;
+}
+
+/**
+ * @brief   Posts an high priority message into a mailbox.
+ * @details The invoking thread waits until a empty slot in the mailbox becomes
+ *          available or the specified time runs out.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ * @param[in] msg       the message to be posted on the mailbox
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if a message has been correctly posted.
+ * @retval MSG_RESET    if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT  if the operation has timed out.
+ *
+ * @api
+ */
+msg_t chMBPostAhead(mailbox_t *mbp, msg_t msg, systime_t time) {
+  msg_t rdymsg;
+
+  chSysLock();
+  rdymsg = chMBPostAheadS(mbp, msg, time);
+  chSysUnlock();
+  return rdymsg;
+}
+
+/**
+ * @brief   Posts an high priority message into a mailbox.
+ * @details The invoking thread waits until a empty slot in the mailbox becomes
+ *          available or the specified time runs out.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ * @param[in] msg       the message to be posted on the mailbox
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if a message has been correctly posted.
+ * @retval MSG_RESET    if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT  if the operation has timed out.
+ *
+ * @sclass
+ */
+msg_t chMBPostAheadS(mailbox_t *mbp, msg_t msg, systime_t time) {
+  msg_t rdymsg;
+
+  chDbgCheckClassS();
+  chDbgCheck(mbp != NULL);
+
+  rdymsg = chSemWaitTimeoutS(&mbp->mb_emptysem, time);
+  if (rdymsg == MSG_OK) {
+    if (--mbp->mb_rdptr < mbp->mb_buffer)
+      mbp->mb_rdptr = mbp->mb_top - 1;
+    *mbp->mb_rdptr = msg;
+    chSemSignalI(&mbp->mb_fullsem);
+    chSchRescheduleS();
+  }
+  return rdymsg;
+}
+
+/**
+ * @brief   Posts an high priority message into a mailbox.
+ * @details This variant is non-blocking, the function returns a timeout
+ *          condition if the queue is full.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ * @param[in] msg       the message to be posted on the mailbox
+ * @return              The operation status.
+ * @retval MSG_OK       if a message has been correctly posted.
+ * @retval MSG_TIMEOUT  if the mailbox is full and the message cannot be
+ *                      posted.
+ *
+ * @iclass
+ */
+msg_t chMBPostAheadI(mailbox_t *mbp, msg_t msg) {
+
+  chDbgCheckClassI();
+  chDbgCheck(mbp != NULL);
+
+  if (chSemGetCounterI(&mbp->mb_emptysem) <= 0)
+    return MSG_TIMEOUT;
+  chSemFastWaitI(&mbp->mb_emptysem);
+  if (--mbp->mb_rdptr < mbp->mb_buffer)
+    mbp->mb_rdptr = mbp->mb_top - 1;
+  *mbp->mb_rdptr = msg;
+  chSemSignalI(&mbp->mb_fullsem);
+  return MSG_OK;
+}
+
+/**
+ * @brief   Retrieves a message from a mailbox.
+ * @details The invoking thread waits until a message is posted in the mailbox
+ *          or the specified time runs out.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ * @param[out] msgp     pointer to a message variable for the received message
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if a message has been correctly fetched.
+ * @retval MSG_RESET    if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT  if the operation has timed out.
+ *
+ * @api
+ */
+msg_t chMBFetch(mailbox_t *mbp, msg_t *msgp, systime_t time) {
+  msg_t rdymsg;
+
+  chSysLock();
+  rdymsg = chMBFetchS(mbp, msgp, time);
+  chSysUnlock();
+  return rdymsg;
+}
+
+/**
+ * @brief   Retrieves a message from a mailbox.
+ * @details The invoking thread waits until a message is posted in the mailbox
+ *          or the specified time runs out.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ * @param[out] msgp     pointer to a message variable for the received message
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval MSG_OK       if a message has been correctly fetched.
+ * @retval MSG_RESET    if the mailbox has been reset while waiting.
+ * @retval MSG_TIMEOUT  if the operation has timed out.
+ *
+ * @sclass
+ */
+msg_t chMBFetchS(mailbox_t *mbp, msg_t *msgp, systime_t time) {
+  msg_t rdymsg;
+
+  chDbgCheckClassS();
+  chDbgCheck((mbp != NULL) && (msgp != NULL));
+
+  rdymsg = chSemWaitTimeoutS(&mbp->mb_fullsem, time);
+  if (rdymsg == MSG_OK) {
+    *msgp = *mbp->mb_rdptr++;
+    if (mbp->mb_rdptr >= mbp->mb_top)
+      mbp->mb_rdptr = mbp->mb_buffer;
+    chSemSignalI(&mbp->mb_emptysem);
+    chSchRescheduleS();
+  }
+  return rdymsg;
+}
+
+/**
+ * @brief   Retrieves a message from a mailbox.
+ * @details This variant is non-blocking, the function returns a timeout
+ *          condition if the queue is empty.
+ *
+ * @param[in] mbp       the pointer to an initialized @p mailbox_t object
+ * @param[out] msgp     pointer to a message variable for the received message
+ * @return              The operation status.
+ * @retval MSG_OK       if a message has been correctly fetched.
+ * @retval MSG_TIMEOUT  if the mailbox is empty and a message cannot be
+ *                      fetched.
+ *
+ * @iclass
+ */
+msg_t chMBFetchI(mailbox_t *mbp, msg_t *msgp) {
+
+  chDbgCheckClassI();
+  chDbgCheck((mbp != NULL) && (msgp != NULL));
+
+  if (chSemGetCounterI(&mbp->mb_fullsem) <= 0)
+    return MSG_TIMEOUT;
+  chSemFastWaitI(&mbp->mb_fullsem);
+  *msgp = *mbp->mb_rdptr++;
+  if (mbp->mb_rdptr >= mbp->mb_top)
+    mbp->mb_rdptr = mbp->mb_buffer;
+  chSemSignalI(&mbp->mb_emptysem);
+  return MSG_OK;
+}
+#endif /* CH_CFG_USE_MAILBOXES */
+
+/** @} */
diff --git a/os/rt/src/chmemcore.c b/os/rt/src/chmemcore.c
new file mode 100644
index 000000000..d5e7ed79c
--- /dev/null
+++ b/os/rt/src/chmemcore.c
@@ -0,0 +1,153 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmemcore.c
+ * @brief   Core memory manager code.
+ *
+ * @addtogroup memcore
+ * @details Core Memory Manager related APIs and services.
+ *          <h2>Operation mode</h2>
+ *          The core memory manager is a simplified allocator that only
+ *          allows to allocate memory blocks without the possibility to
+ *          free them.<br>
+ *          This allocator is meant as a memory blocks provider for the
+ *          other allocators such as:
+ *          - C-Runtime allocator (through a compiler specific adapter module).
+ *          - Heap allocator (see @ref heaps).
+ *          - Memory pools allocator (see @ref pools).
+ *          .
+ *          By having a centralized memory provider the various allocators
+ *          can coexist and share the main memory.<br>
+ *          This allocator, alone, is also useful for very simple
+ *          applications that just require a simple way to get memory
+ *          blocks.
+ * @pre     In order to use the core memory manager APIs the @p CH_CFG_USE_MEMCORE
+ *          option must be enabled in @p chconf.h.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_MEMCORE || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+static uint8_t *nextmem;
+static uint8_t *endmem;
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level memory manager initialization.
+ *
+ * @notapi
+ */
+void _core_init(void) {
+#if CH_CFG_MEMCORE_SIZE == 0
+  extern uint8_t __heap_base__[];
+  extern uint8_t __heap_end__[];
+
+  nextmem = (uint8_t *)MEM_ALIGN_NEXT(__heap_base__);
+  endmem = (uint8_t *)MEM_ALIGN_PREV(__heap_end__);
+#else
+  static stkalign_t buffer[MEM_ALIGN_NEXT(CH_CFG_MEMCORE_SIZE)/MEM_ALIGN_SIZE];
+
+  nextmem = (uint8_t *)&buffer[0];
+  endmem = (uint8_t *)&buffer[MEM_ALIGN_NEXT(CH_CFG_MEMCORE_SIZE)/MEM_ALIGN_SIZE];
+#endif
+}
+
+/**
+ * @brief   Allocates a memory block.
+ * @details The size of the returned block is aligned to the alignment
+ *          type so it is not possible to allocate less
+ *          than <code>MEM_ALIGN_SIZE</code>.
+ *
+ * @param[in] size      the size of the block to be allocated
+ * @return              A pointer to the allocated memory block.
+ * @retval NULL         allocation failed, core memory exhausted.
+ *
+ * @api
+ */
+void *chCoreAlloc(size_t size) {
+  void *p;
+
+  chSysLock();
+  p = chCoreAllocI(size);
+  chSysUnlock();
+  return p;
+}
+
+/**
+ * @brief   Allocates a memory block.
+ * @details The size of the returned block is aligned to the alignment
+ *          type so it is not possible to allocate less than
+ *          <code>MEM_ALIGN_SIZE</code>.
+ *
+ * @param[in] size      the size of the block to be allocated.
+ * @return              A pointer to the allocated memory block.
+ * @retval NULL         allocation failed, core memory exhausted.
+ *
+ * @iclass
+ */
+void *chCoreAllocI(size_t size) {
+  void *p;
+
+  chDbgCheckClassI();
+
+  size = MEM_ALIGN_NEXT(size);
+  if ((size_t)(endmem - nextmem) < size)
+    return NULL;
+  p = nextmem;
+  nextmem += size;
+  return p;
+}
+
+/**
+ * @brief   Core memory status.
+ *
+ * @return              The size, in bytes, of the free core memory.
+ *
+ * @api
+ */
+size_t chCoreStatus(void) {
+
+  return (size_t)(endmem - nextmem);
+}
+#endif /* CH_CFG_USE_MEMCORE */
+
+/** @} */
diff --git a/os/rt/src/chmempools.c b/os/rt/src/chmempools.c
new file mode 100644
index 000000000..d92ea7517
--- /dev/null
+++ b/os/rt/src/chmempools.c
@@ -0,0 +1,194 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmempools.c
+ * @brief   Memory Pools code.
+ *
+ * @addtogroup pools
+ * @details Memory Pools related APIs and services.
+ *          <h2>Operation mode</h2>
+ *          The Memory Pools APIs allow to allocate/free fixed size objects in
+ *          <b>constant time</b> and reliably without memory fragmentation
+ *          problems.<br>
+ *          Memory Pools do not enforce any alignment constraint on the
+ *          contained object however the objects must be properly aligned
+ *          to contain a pointer to void.
+ * @pre     In order to use the memory pools APIs the @p CH_CFG_USE_MEMPOOLS option
+ *          must be enabled in @p chconf.h.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_MEMPOOLS || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes an empty memory pool.
+ *
+ * @param[out] mp       pointer to a @p memory_pool_t structure
+ * @param[in] size      the size of the objects contained in this memory pool,
+ *                      the minimum accepted size is the size of a pointer to
+ *                      void.
+ * @param[in] provider  memory provider function for the memory pool or
+ *                      @p NULL if the pool is not allowed to grow
+ *                      automatically
+ *
+ * @init
+ */
+void chPoolObjectInit(memory_pool_t *mp, size_t size, memgetfunc_t provider) {
+
+  chDbgCheck((mp != NULL) && (size >= sizeof(void *)));
+
+  mp->mp_next = NULL;
+  mp->mp_object_size = size;
+  mp->mp_provider = provider;
+}
+
+/**
+ * @brief   Loads a memory pool with an array of static objects.
+ * @pre     The memory pool must be already been initialized.
+ * @pre     The array elements must be of the right size for the specified
+ *          memory pool.
+ * @post    The memory pool contains the elements of the input array.
+ *
+ * @param[in] mp        pointer to a @p memory_pool_t structure
+ * @param[in] p         pointer to the array first element
+ * @param[in] n         number of elements in the array
+ *
+ * @api
+ */
+void chPoolLoadArray(memory_pool_t *mp, void *p, size_t n) {
+
+  chDbgCheck((mp != NULL) && (n != 0));
+
+  while (n) {
+    chPoolAdd(mp, p);
+    p = (void *)(((uint8_t *)p) + mp->mp_object_size);
+    n--;
+  }
+}
+
+/**
+ * @brief   Allocates an object from a memory pool.
+ * @pre     The memory pool must be already been initialized.
+ *
+ * @param[in] mp        pointer to a @p memory_pool_t structure
+ * @return              The pointer to the allocated object.
+ * @retval NULL         if pool is empty.
+ *
+ * @iclass
+ */
+void *chPoolAllocI(memory_pool_t *mp) {
+  void *objp;
+
+  chDbgCheckClassI();
+  chDbgCheck(mp != NULL);
+
+  if ((objp = mp->mp_next) != NULL)
+    mp->mp_next = mp->mp_next->ph_next;
+  else if (mp->mp_provider != NULL)
+    objp = mp->mp_provider(mp->mp_object_size);
+  return objp;
+}
+
+/**
+ * @brief   Allocates an object from a memory pool.
+ * @pre     The memory pool must be already been initialized.
+ *
+ * @param[in] mp        pointer to a @p memory_pool_t structure
+ * @return              The pointer to the allocated object.
+ * @retval NULL         if pool is empty.
+ *
+ * @api
+ */
+void *chPoolAlloc(memory_pool_t *mp) {
+  void *objp;
+
+  chSysLock();
+  objp = chPoolAllocI(mp);
+  chSysUnlock();
+  return objp;
+}
+
+/**
+ * @brief   Releases an object into a memory pool.
+ * @pre     The memory pool must be already been initialized.
+ * @pre     The freed object must be of the right size for the specified
+ *          memory pool.
+ * @pre     The object must be properly aligned to contain a pointer to void.
+ *
+ * @param[in] mp        pointer to a @p memory_pool_t structure
+ * @param[in] objp      the pointer to the object to be released
+ *
+ * @iclass
+ */
+void chPoolFreeI(memory_pool_t *mp, void *objp) {
+  struct pool_header *php = objp;
+
+  chDbgCheckClassI();
+  chDbgCheck((mp != NULL) && (objp != NULL));
+
+  php->ph_next = mp->mp_next;
+  mp->mp_next = php;
+}
+
+/**
+ * @brief   Releases an object into a memory pool.
+ * @pre     The memory pool must be already been initialized.
+ * @pre     The freed object must be of the right size for the specified
+ *          memory pool.
+ * @pre     The object must be properly aligned to contain a pointer to void.
+ *
+ * @param[in] mp        pointer to a @p memory_pool_t structure
+ * @param[in] objp      the pointer to the object to be released
+ *
+ * @api
+ */
+void chPoolFree(memory_pool_t *mp, void *objp) {
+
+  chSysLock();
+  chPoolFreeI(mp, objp);
+  chSysUnlock();
+}
+
+#endif /* CH_CFG_USE_MEMPOOLS */
+
+/** @} */
diff --git a/os/rt/src/chmsg.c b/os/rt/src/chmsg.c
new file mode 100644
index 000000000..335b46c61
--- /dev/null
+++ b/os/rt/src/chmsg.c
@@ -0,0 +1,151 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmsg.c
+ * @brief   Messages code.
+ *
+ * @addtogroup messages
+ * @details Synchronous inter-thread messages APIs and services.
+ *          <h2>Operation Mode</h2>
+ *          Synchronous messages are an easy to use and fast IPC mechanism,
+ *          threads can both act as message servers and/or message clients,
+ *          the mechanism allows data to be carried in both directions. Note
+ *          that messages are not copied between the client and server threads
+ *          but just a pointer passed so the exchange is very time
+ *          efficient.<br>
+ *          Messages are scalar data types of type @p msg_t that are guaranteed
+ *          to be size compatible with data pointers. Note that on some
+ *          architectures function pointers can be larger that @p msg_t.<br>
+ *          Messages are usually processed in FIFO order but it is possible to
+ *          process them in priority order by enabling the
+ *          @p CH_CFG_USE_MESSAGES_PRIORITY option in @p chconf.h.<br>
+ * @pre     In order to use the message APIs the @p CH_CFG_USE_MESSAGES option
+ *          must be enabled in @p chconf.h.
+ * @post    Enabling messages requires 6-12 (depending on the architecture)
+ *          extra bytes in the @p thread_t structure.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_MESSAGES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+#if CH_CFG_USE_MESSAGES_PRIORITY
+#define msg_insert(tp, qp) prio_insert(tp, qp)
+#else
+#define msg_insert(tp, qp) queue_insert(tp, qp)
+#endif
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Sends a message to the specified thread.
+ * @details The sender is stopped until the receiver executes a
+ *          @p chMsgRelease()after receiving the message.
+ *
+ * @param[in] tp        the pointer to the thread
+ * @param[in] msg       the message
+ * @return              The answer message from @p chMsgRelease().
+ *
+ * @api
+ */
+msg_t chMsgSend(thread_t *tp, msg_t msg) {
+  thread_t *ctp = currp;
+
+  chDbgCheck(tp != NULL);
+
+  chSysLock();
+  ctp->p_msg = msg;
+  ctp->p_u.wtobjp = &tp->p_msgqueue;
+  msg_insert(ctp, &tp->p_msgqueue);
+  if (tp->p_state == CH_STATE_WTMSG)
+    chSchReadyI(tp);
+  chSchGoSleepS(CH_STATE_SNDMSGQ);
+  msg = ctp->p_u.rdymsg;
+  chSysUnlock();
+  return msg;
+}
+
+/**
+ * @brief   Suspends the thread and waits for an incoming message.
+ * @post    After receiving a message the function @p chMsgGet() must be
+ *          called in order to retrieve the message and then @p chMsgRelease()
+ *          must be invoked in order to acknowledge the reception and send
+ *          the answer.
+ * @note    If the message is a pointer then you can assume that the data
+ *          pointed by the message is stable until you invoke @p chMsgRelease()
+ *          because the sending thread is suspended until then.
+ *
+ * @return              A reference to the thread carrying the message.
+ *
+ * @api
+ */
+thread_t *chMsgWait(void) {
+  thread_t *tp;
+
+  chSysLock();
+  if (!chMsgIsPendingI(currp))
+    chSchGoSleepS(CH_STATE_WTMSG);
+  tp = queue_fifo_remove(&currp->p_msgqueue);
+  tp->p_state = CH_STATE_SNDMSG;
+  chSysUnlock();
+  return tp;
+}
+
+/**
+ * @brief   Releases a sender thread specifying a response message.
+ * @pre     Invoke this function only after a message has been received
+ *          using @p chMsgWait().
+ *
+ * @param[in] tp        pointer to the thread
+ * @param[in] msg       message to be returned to the sender
+ *
+ * @api
+ */
+void chMsgRelease(thread_t *tp, msg_t msg) {
+
+  chSysLock();
+  chDbgAssert(tp->p_state == CH_STATE_SNDMSG, "invalid state");
+  chMsgReleaseS(tp, msg);
+  chSysUnlock();
+}
+
+#endif /* CH_CFG_USE_MESSAGES */
+
+/** @} */
diff --git a/os/rt/src/chmtx.c b/os/rt/src/chmtx.c
new file mode 100644
index 000000000..45e884204
--- /dev/null
+++ b/os/rt/src/chmtx.c
@@ -0,0 +1,501 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chmtx.c
+ * @brief   Mutexes code.
+ *
+ * @addtogroup mutexes
+ * @details Mutexes related APIs and services.
+ *
+ *          <h2>Operation mode</h2>
+ *          A mutex is a threads synchronization object that can be in two
+ *          distinct states:
+ *          - Not owned (unlocked).
+ *          - Owned by a thread (locked).
+ *          .
+ *          Operations defined for mutexes:
+ *          - <b>Lock</b>: The mutex is checked, if the mutex is not owned by
+ *            some other thread then it is associated to the locking thread
+ *            else the thread is queued on the mutex in a list ordered by
+ *            priority.
+ *          - <b>Unlock</b>: The mutex is released by the owner and the highest
+ *            priority thread waiting in the queue, if any, is resumed and made
+ *            owner of the mutex.
+ *          .
+ *          <h2>Constraints</h2>
+ *          In ChibiOS/RT the Unlock operations must always be performed
+ *          in lock-reverse order. This restriction both improves the
+ *          performance and is required for an efficient implementation
+ *          of the priority inheritance mechanism.<br>
+ *          Operating under this restriction also ensures that deadlocks
+ *          are no possible.
+ *
+ *          <h2>Recursive mode</h2>
+ *          By default mutexes are not recursive, this mean that it is not
+ *          possible to take a mutex already owned by the same thread.
+ *          It is possible to enable the recursive behavior by enabling the
+ *          option @p CH_CFG_USE_MUTEXES_RECURSIVE.
+ *
+ *          <h2>The priority inversion problem</h2>
+ *          The mutexes in ChibiOS/RT implements the <b>full</b> priority
+ *          inheritance mechanism in order handle the priority inversion
+ *          problem.<br>
+ *          When a thread is queued on a mutex, any thread, directly or
+ *          indirectly, holding the mutex gains the same priority of the
+ *          waiting thread (if their priority was not already equal or higher).
+ *          The mechanism works with any number of nested mutexes and any
+ *          number of involved threads. The algorithm complexity (worst case)
+ *          is N with N equal to the number of nested mutexes.
+ * @pre     In order to use the mutex APIs the @p CH_CFG_USE_MUTEXES option
+ *          must be enabled in @p chconf.h.
+ * @post    Enabling mutexes requires 5-12 (depending on the architecture)
+ *          extra bytes in the @p thread_t structure.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes s @p mutex_t structure.
+ *
+ * @param[out] mp       pointer to a @p mutex_t structure
+ *
+ * @init
+ */
+void chMtxObjectInit(mutex_t *mp) {
+
+  chDbgCheck(mp != NULL);
+
+  queue_init(&mp->m_queue);
+  mp->m_owner = NULL;
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+  mp->m_cnt = 0;
+#endif
+}
+
+/**
+ * @brief   Locks the specified mutex.
+ * @post    The mutex is locked and inserted in the per-thread stack of owned
+ *          mutexes.
+ *
+ * @param[in] mp        pointer to the @p mutex_t structure
+ *
+ * @api
+ */
+void chMtxLock(mutex_t *mp) {
+
+  chSysLock();
+
+  chMtxLockS(mp);
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Locks the specified mutex.
+ * @post    The mutex is locked and inserted in the per-thread stack of owned
+ *          mutexes.
+ *
+ * @param[in] mp        pointer to the @p mutex_t structure
+ *
+ * @sclass
+ */
+void chMtxLockS(mutex_t *mp) {
+  thread_t *ctp = currp;
+
+  chDbgCheckClassS();
+  chDbgCheck(mp != NULL);
+
+  /* Is the mutex already locked? */
+  if (mp->m_owner != NULL) {
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+
+    chDbgAssert(mp->m_cnt >= 1, "counter is not positive");
+
+    /* If the mutex is already owned by this thread, the counter is increased
+       and there is no need of more actions.*/
+    if (mp->m_owner == ctp)
+      mp->m_cnt++;
+    else {
+#endif
+      /* Priority inheritance protocol; explores the thread-mutex dependencies
+         boosting the priority of all the affected threads to equal the
+         priority of the running thread requesting the mutex.*/
+      thread_t *tp = mp->m_owner;
+
+      /* Does the running thread have higher priority than the mutex
+         owning thread? */
+      while (tp->p_prio < ctp->p_prio) {
+        /* Make priority of thread tp match the running thread's priority.*/
+        tp->p_prio = ctp->p_prio;
+
+        /* The following states need priority queues reordering.*/
+        switch (tp->p_state) {
+        case CH_STATE_WTMTX:
+          /* Re-enqueues the mutex owner with its new priority.*/
+          queue_prio_insert(queue_dequeue(tp),
+                            (threads_queue_t *)tp->p_u.wtobjp);
+          tp = ((mutex_t *)tp->p_u.wtobjp)->m_owner;
+          continue;
+  #if CH_CFG_USE_CONDVARS |                                                       \
+      (CH_CFG_USE_SEMAPHORES && CH_CFG_USE_SEMAPHORES_PRIORITY) |                     \
+      (CH_CFG_USE_MESSAGES && CH_CFG_USE_MESSAGES_PRIORITY)
+  #if CH_CFG_USE_CONDVARS
+        case CH_STATE_WTCOND:
+  #endif
+  #if CH_CFG_USE_SEMAPHORES && CH_CFG_USE_SEMAPHORES_PRIORITY
+        case CH_STATE_WTSEM:
+  #endif
+  #if CH_CFG_USE_MESSAGES && CH_CFG_USE_MESSAGES_PRIORITY
+        case CH_STATE_SNDMSGQ:
+  #endif
+          /* Re-enqueues tp with its new priority on the queue.*/
+          queue_prio_insert(queue_dequeue(tp),
+                            (threads_queue_t *)tp->p_u.wtobjp);
+          break;
+  #endif
+        case CH_STATE_READY:
+  #if CH_DBG_ENABLE_ASSERTS
+          /* Prevents an assertion in chSchReadyI().*/
+          tp->p_state = CH_STATE_CURRENT;
+  #endif
+          /* Re-enqueues tp with its new priority on the ready list.*/
+          chSchReadyI(queue_dequeue(tp));
+          break;
+        }
+        break;
+      }
+
+      /* Sleep on the mutex.*/
+      queue_prio_insert(ctp, &mp->m_queue);
+      ctp->p_u.wtobjp = mp;
+      chSchGoSleepS(CH_STATE_WTMTX);
+
+      /* It is assumed that the thread performing the unlock operation assigns
+         the mutex to this thread.*/
+      chDbgAssert(mp->m_owner == ctp, "not owner");
+      chDbgAssert(ctp->p_mtxlist == mp, "not owned");
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+      chDbgAssert(mp->m_cnt == 1, "counter is not one");
+    }
+#endif
+  }
+  else {
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+    chDbgAssert(mp->m_cnt == 0, "counter is not zero");
+
+    mp->m_cnt++;
+#endif
+    /* It was not owned, inserted in the owned mutexes list.*/
+    mp->m_owner = ctp;
+    mp->m_next = ctp->p_mtxlist;
+    ctp->p_mtxlist = mp;
+  }
+}
+
+/**
+ * @brief   Tries to lock a mutex.
+ * @details This function attempts to lock a mutex, if the mutex is already
+ *          locked by another thread then the function exits without waiting.
+ * @post    The mutex is locked and inserted in the per-thread stack of owned
+ *          mutexes.
+ * @note    This function does not have any overhead related to the
+ *          priority inheritance mechanism because it does not try to
+ *          enter a sleep state.
+ *
+ * @param[in] mp        pointer to the @p mutex_t structure
+ * @return              The operation status.
+ * @retval true         if the mutex has been successfully acquired
+ * @retval false        if the lock attempt failed.
+ *
+ * @api
+ */
+bool chMtxTryLock(mutex_t *mp) {
+  bool b;
+
+  chSysLock();
+
+  b = chMtxTryLockS(mp);
+
+  chSysUnlock();
+  return b;
+}
+
+/**
+ * @brief   Tries to lock a mutex.
+ * @details This function attempts to lock a mutex, if the mutex is already
+ *          taken by another thread then the function exits without waiting.
+ * @post    The mutex is locked and inserted in the per-thread stack of owned
+ *          mutexes.
+ * @note    This function does not have any overhead related to the
+ *          priority inheritance mechanism because it does not try to
+ *          enter a sleep state.
+ *
+ * @param[in] mp        pointer to the @p mutex_t structure
+ * @return              The operation status.
+ * @retval true         if the mutex has been successfully acquired
+ * @retval false        if the lock attempt failed.
+ *
+ * @sclass
+ */
+bool chMtxTryLockS(mutex_t *mp) {
+
+  chDbgCheckClassS();
+  chDbgCheck(mp != NULL);
+
+  if (mp->m_owner != NULL) {
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+
+    chDbgAssert(mp->m_cnt >= 1, "counter is not positive");
+
+    if (mp->m_owner == currp) {
+      mp->m_cnt++;
+      return true;
+    }
+#endif
+    return false;
+  }
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+
+  chDbgAssert(mp->m_cnt == 0, "counter is not zero");
+
+  mp->m_cnt++;
+#endif
+  mp->m_owner = currp;
+  mp->m_next = currp->p_mtxlist;
+  currp->p_mtxlist = mp;
+  return true;
+}
+
+/**
+ * @brief   Unlocks the next owned mutex in reverse lock order.
+ * @pre     The invoking thread <b>must</b> have at least one owned mutex.
+ * @post    The mutex is unlocked and removed from the per-thread stack of
+ *          owned mutexes.
+ *
+ * @param[in] mp        pointer to the @p mutex_t structure
+ *
+ * @api
+ */
+void chMtxUnlock(mutex_t *mp) {
+  thread_t *ctp = currp;
+  mutex_t *lmp;
+
+  chDbgCheck(mp != NULL);
+
+  chSysLock();
+
+  chDbgAssert(ctp->p_mtxlist != NULL, "owned mutexes list empty");
+  chDbgAssert(ctp->p_mtxlist->m_owner == ctp, "ownership failure");
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+  chDbgAssert(mp->m_cnt >= 1, "counter is not positive");
+
+  if (--mp->m_cnt == 0) {
+#endif
+
+    chDbgAssert(ctp->p_mtxlist == mp, "not next in list");
+
+    /* Removes the top mutex from the thread's owned mutexes list and marks
+       it as not owned. Note, it is assumed to be the same mutex passed as
+       parameter of this function.*/
+    ctp->p_mtxlist = mp->m_next;
+
+    /* If a thread is waiting on the mutex then the fun part begins.*/
+    if (chMtxQueueNotEmptyS(mp)) {
+      thread_t *tp;
+
+      /* Recalculates the optimal thread priority by scanning the owned
+         mutexes list.*/
+      tprio_t newprio = ctp->p_realprio;
+      lmp = ctp->p_mtxlist;
+      while (lmp != NULL) {
+        /* If the highest priority thread waiting in the mutexes list has a
+           greater priority than the current thread base priority then the
+           final priority will have at least that priority.*/
+        if (chMtxQueueNotEmptyS(lmp) && (lmp->m_queue.p_next->p_prio > newprio))
+          newprio = lmp->m_queue.p_next->p_prio;
+        lmp = lmp->m_next;
+      }
+
+      /* Assigns to the current thread the highest priority among all the
+         waiting threads.*/
+      ctp->p_prio = newprio;
+
+      /* Awakens the highest priority thread waiting for the unlocked mutex and
+         assigns the mutex to it.*/
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+      mp->m_cnt = 1;
+#endif
+      tp = queue_fifo_remove(&mp->m_queue);
+      mp->m_owner = tp;
+      mp->m_next = tp->p_mtxlist;
+      tp->p_mtxlist = mp;
+      chSchWakeupS(tp, MSG_OK);
+    }
+    else
+      mp->m_owner = NULL;
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+  }
+#endif
+
+  chSysUnlock();
+}
+
+/**
+ * @brief   Unlocks the next owned mutex in reverse lock order.
+ * @pre     The invoking thread <b>must</b> have at least one owned mutex.
+ * @post    The mutex is unlocked and removed from the per-thread stack of
+ *          owned mutexes.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel.
+ *
+ * @param[in] mp        pointer to the @p mutex_t structure
+ *
+ * @sclass
+ */
+void chMtxUnlockS(mutex_t *mp) {
+  thread_t *ctp = currp;
+  mutex_t *lmp;
+
+  chDbgCheckClassS();
+  chDbgCheck(mp != NULL);
+
+  chDbgAssert(ctp->p_mtxlist != NULL, "owned mutexes list empty");
+  chDbgAssert(ctp->p_mtxlist->m_owner == ctp, "ownership failure");
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+  chDbgAssert(mp->m_cnt >= 1, "counter is not positive");
+
+  if (--mp->m_cnt == 0) {
+#endif
+
+    chDbgAssert(ctp->p_mtxlist == mp, "not next in list");
+
+    /* Removes the top mutex from the thread's owned mutexes list and marks
+       it as not owned. Note, it is assumed to be the same mutex passed as
+       parameter of this function.*/
+    ctp->p_mtxlist = mp->m_next;
+
+    /* If a thread is waiting on the mutex then the fun part begins.*/
+    if (chMtxQueueNotEmptyS(mp)) {
+      thread_t *tp;
+
+      /* Recalculates the optimal thread priority by scanning the owned
+         mutexes list.*/
+      tprio_t newprio = ctp->p_realprio;
+      lmp = ctp->p_mtxlist;
+      while (lmp != NULL) {
+        /* If the highest priority thread waiting in the mutexes list has a
+           greater priority than the current thread base priority then the
+           final priority will have at least that priority.*/
+        if (chMtxQueueNotEmptyS(lmp) && (lmp->m_queue.p_next->p_prio > newprio))
+          newprio = lmp->m_queue.p_next->p_prio;
+        lmp = lmp->m_next;
+      }
+
+      /* Assigns to the current thread the highest priority among all the
+         waiting threads.*/
+      ctp->p_prio = newprio;
+
+      /* Awakens the highest priority thread waiting for the unlocked mutex and
+         assigns the mutex to it.*/
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+      mp->m_cnt = 1;
+#endif
+      tp = queue_fifo_remove(&mp->m_queue);
+      mp->m_owner = tp;
+      mp->m_next = tp->p_mtxlist;
+      tp->p_mtxlist = mp;
+      chSchReadyI(tp);
+    }
+    else
+      mp->m_owner = NULL;
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+  }
+#endif
+}
+
+/**
+ * @brief   Unlocks all the mutexes owned by the invoking thread.
+ * @post    The stack of owned mutexes is emptied and all the found
+ *          mutexes are unlocked.
+ * @note    This function is <b>MUCH MORE</b> efficient than releasing the
+ *          mutexes one by one and not just because the call overhead,
+ *          this function does not have any overhead related to the priority
+ *          inheritance mechanism.
+ *
+ * @api
+ */
+void chMtxUnlockAll(void) {
+  thread_t *ctp = currp;
+
+  chSysLock();
+  if (ctp->p_mtxlist != NULL) {
+    do {
+      mutex_t *mp = ctp->p_mtxlist;
+      ctp->p_mtxlist = mp->m_next;
+      if (chMtxQueueNotEmptyS(mp)) {
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+        mp->m_cnt = 1;
+#endif
+        thread_t *tp = queue_fifo_remove(&mp->m_queue);
+        mp->m_owner = tp;
+        mp->m_next = tp->p_mtxlist;
+        tp->p_mtxlist = mp;
+        chSchReadyI(tp);
+      }
+      else {
+#if CH_CFG_USE_MUTEXES_RECURSIVE
+        mp->m_cnt = 0;
+#endif
+        mp->m_owner = NULL;
+      }
+    } while (ctp->p_mtxlist != NULL);
+    ctp->p_prio = ctp->p_realprio;
+    chSchRescheduleS();
+  }
+  chSysUnlock();
+}
+
+#endif /* CH_CFG_USE_MUTEXES */
+
+/** @} */
diff --git a/os/rt/src/chqueues.c b/os/rt/src/chqueues.c
new file mode 100644
index 000000000..c0b0f8256
--- /dev/null
+++ b/os/rt/src/chqueues.c
@@ -0,0 +1,427 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chqueues.c
+ * @brief   I/O Queues code.
+ *
+ * @addtogroup io_queues
+ * @details ChibiOS/RT queues are mostly used in serial-like device drivers.
+ *          The device drivers are usually designed to have a lower side
+ *          (lower driver, it is usually an interrupt service routine) and an
+ *          upper side (upper driver, accessed by the application threads).<br>
+ *          There are several kind of queues:<br>
+ *          - <b>Input queue</b>, unidirectional queue where the writer is the
+ *            lower side and the reader is the upper side.
+ *          - <b>Output queue</b>, unidirectional queue where the writer is the
+ *            upper side and the reader is the lower side.
+ *          - <b>Full duplex queue</b>, bidirectional queue. Full duplex queues
+ *            are implemented by pairing an input queue and an output queue
+ *            together.
+ *          .
+ * @pre     In order to use the I/O queues the @p CH_CFG_USE_QUEUES option must
+ *          be enabled in @p chconf.h.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_QUEUES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes an input queue.
+ * @details A Semaphore is internally initialized and works as a counter of
+ *          the bytes contained in the queue.
+ * @note    The callback is invoked from within the S-Locked system state,
+ *          see @ref system_states.
+ *
+ * @param[out] iqp      pointer to an @p input_queue_t structure
+ * @param[in] bp        pointer to a memory area allocated as queue buffer
+ * @param[in] size      size of the queue buffer
+ * @param[in] infy      pointer to a callback function that is invoked when
+ *                      data is read from the queue. The value can be @p NULL.
+ * @param[in] link      application defined pointer
+ *
+ * @init
+ */
+void chIQObjectInit(input_queue_t *iqp, uint8_t *bp, size_t size,
+                    qnotify_t infy, void *link) {
+
+  chThdQueueObjectInit(&iqp->q_waiting);
+  iqp->q_counter = 0;
+  iqp->q_buffer = iqp->q_rdptr = iqp->q_wrptr = bp;
+  iqp->q_top = bp + size;
+  iqp->q_notify = infy;
+  iqp->q_link = link;
+}
+
+/**
+ * @brief   Resets an input queue.
+ * @details All the data in the input queue is erased and lost, any waiting
+ *          thread is resumed with status @p Q_RESET.
+ * @note    A reset operation can be used by a low level driver in order to
+ *          obtain immediate attention from the high level layers.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ *
+ * @iclass
+ */
+void chIQResetI(input_queue_t *iqp) {
+
+  chDbgCheckClassI();
+
+  iqp->q_rdptr = iqp->q_wrptr = iqp->q_buffer;
+  iqp->q_counter = 0;
+  chThdDequeueAllI(&iqp->q_waiting, Q_RESET);
+}
+
+/**
+ * @brief   Input queue write.
+ * @details A byte value is written into the low end of an input queue.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @param[in] b         the byte value to be written in the queue
+ * @return              The operation status.
+ * @retval Q_OK         if the operation has been completed with success.
+ * @retval Q_FULL       if the queue is full and the operation cannot be
+ *                      completed.
+ *
+ * @iclass
+ */
+msg_t chIQPutI(input_queue_t *iqp, uint8_t b) {
+
+  chDbgCheckClassI();
+
+  if (chIQIsFullI(iqp))
+    return Q_FULL;
+
+  iqp->q_counter++;
+  *iqp->q_wrptr++ = b;
+  if (iqp->q_wrptr >= iqp->q_top)
+    iqp->q_wrptr = iqp->q_buffer;
+
+  chThdDequeueNextI(&iqp->q_waiting, Q_OK);
+
+  return Q_OK;
+}
+
+/**
+ * @brief   Input queue read with timeout.
+ * @details This function reads a byte value from an input queue. If the queue
+ *          is empty then the calling thread is suspended until a byte arrives
+ *          in the queue or a timeout occurs.
+ * @note    The callback is invoked before reading the character from the
+ *          buffer or before entering the state @p CH_STATE_WTQUEUE.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              A byte value from the queue.
+ * @retval Q_TIMEOUT    if the specified time expired.
+ * @retval Q_RESET      if the queue has been reset.
+ *
+ * @api
+ */
+msg_t chIQGetTimeout(input_queue_t *iqp, systime_t time) {
+  uint8_t b;
+
+  chSysLock();
+  if (iqp->q_notify)
+    iqp->q_notify(iqp);
+
+  while (chIQIsEmptyI(iqp)) {
+    msg_t msg;
+    if ((msg = chThdEnqueueTimeoutS(&iqp->q_waiting, time)) < Q_OK) {
+      chSysUnlock();
+      return msg;
+    }
+  }
+
+  iqp->q_counter--;
+  b = *iqp->q_rdptr++;
+  if (iqp->q_rdptr >= iqp->q_top)
+    iqp->q_rdptr = iqp->q_buffer;
+
+  chSysUnlock();
+  return b;
+}
+
+/**
+ * @brief   Input queue read with timeout.
+ * @details The function reads data from an input queue into a buffer. The
+ *          operation completes when the specified amount of data has been
+ *          transferred or after the specified timeout or if the queue has
+ *          been reset.
+ * @note    The function is not atomic, if you need atomicity it is suggested
+ *          to use a semaphore or a mutex for mutual exclusion.
+ * @note    The callback is invoked before reading each character from the
+ *          buffer or before entering the state @p CH_STATE_WTQUEUE.
+ *
+ * @param[in] iqp       pointer to an @p input_queue_t structure
+ * @param[out] bp       pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred, the
+ *                      value 0 is reserved
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The number of bytes effectively transferred.
+ *
+ * @api
+ */
+size_t chIQReadTimeout(input_queue_t *iqp, uint8_t *bp,
+                       size_t n, systime_t time) {
+  qnotify_t nfy = iqp->q_notify;
+  size_t r = 0;
+
+  chDbgCheck(n > 0);
+
+  chSysLock();
+  while (true) {
+    if (nfy)
+      nfy(iqp);
+
+    while (chIQIsEmptyI(iqp)) {
+      if (chThdEnqueueTimeoutS(&iqp->q_waiting, time) != Q_OK) {
+        chSysUnlock();
+        return r;
+      }
+    }
+
+    iqp->q_counter--;
+    *bp++ = *iqp->q_rdptr++;
+    if (iqp->q_rdptr >= iqp->q_top)
+      iqp->q_rdptr = iqp->q_buffer;
+
+    chSysUnlock(); /* Gives a preemption chance in a controlled point.*/
+    r++;
+    if (--n == 0)
+      return r;
+
+    chSysLock();
+  }
+}
+
+/**
+ * @brief   Initializes an output queue.
+ * @details A Semaphore is internally initialized and works as a counter of
+ *          the free bytes in the queue.
+ * @note    The callback is invoked from within the S-Locked system state,
+ *          see @ref system_states.
+ *
+ * @param[out] oqp      pointer to an @p output_queue_t structure
+ * @param[in] bp        pointer to a memory area allocated as queue buffer
+ * @param[in] size      size of the queue buffer
+ * @param[in] onfy      pointer to a callback function that is invoked when
+ *                      data is written to the queue. The value can be @p NULL.
+ * @param[in] link      application defined pointer
+ *
+ * @init
+ */
+void chOQObjectInit(output_queue_t *oqp, uint8_t *bp, size_t size,
+                    qnotify_t onfy, void *link) {
+
+  chThdQueueObjectInit(&oqp->q_waiting);
+  oqp->q_counter = size;
+  oqp->q_buffer = oqp->q_rdptr = oqp->q_wrptr = bp;
+  oqp->q_top = bp + size;
+  oqp->q_notify = onfy;
+  oqp->q_link = link;
+}
+
+/**
+ * @brief   Resets an output queue.
+ * @details All the data in the output queue is erased and lost, any waiting
+ *          thread is resumed with status @p Q_RESET.
+ * @note    A reset operation can be used by a low level driver in order to
+ *          obtain immediate attention from the high level layers.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ *
+ * @iclass
+ */
+void chOQResetI(output_queue_t *oqp) {
+
+  chDbgCheckClassI();
+
+  oqp->q_rdptr = oqp->q_wrptr = oqp->q_buffer;
+  oqp->q_counter = chQSizeI(oqp);
+  chThdDequeueAllI(&oqp->q_waiting, Q_RESET);
+}
+
+/**
+ * @brief   Output queue write with timeout.
+ * @details This function writes a byte value to an output queue. If the queue
+ *          is full then the calling thread is suspended until there is space
+ *          in the queue or a timeout occurs.
+ * @note    The callback is invoked after writing the character into the
+ *          buffer.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @param[in] b         the byte value to be written in the queue
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval Q_OK         if the operation succeeded.
+ * @retval Q_TIMEOUT    if the specified time expired.
+ * @retval Q_RESET      if the queue has been reset.
+ *
+ * @api
+ */
+msg_t chOQPutTimeout(output_queue_t *oqp, uint8_t b, systime_t time) {
+
+  chSysLock();
+  while (chOQIsFullI(oqp)) {
+    msg_t msg;
+
+    if ((msg = chThdEnqueueTimeoutS(&oqp->q_waiting, time)) < Q_OK) {
+      chSysUnlock();
+      return msg;
+    }
+  }
+
+  oqp->q_counter--;
+  *oqp->q_wrptr++ = b;
+  if (oqp->q_wrptr >= oqp->q_top)
+    oqp->q_wrptr = oqp->q_buffer;
+
+  if (oqp->q_notify)
+    oqp->q_notify(oqp);
+
+  chSysUnlock();
+  return Q_OK;
+}
+
+/**
+ * @brief   Output queue read.
+ * @details A byte value is read from the low end of an output queue.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @return              The byte value from the queue.
+ * @retval Q_EMPTY      if the queue is empty.
+ *
+ * @iclass
+ */
+msg_t chOQGetI(output_queue_t *oqp) {
+  uint8_t b;
+
+  chDbgCheckClassI();
+
+  if (chOQIsEmptyI(oqp))
+    return Q_EMPTY;
+
+  oqp->q_counter++;
+  b = *oqp->q_rdptr++;
+  if (oqp->q_rdptr >= oqp->q_top)
+    oqp->q_rdptr = oqp->q_buffer;
+
+  chThdDequeueNextI(&oqp->q_waiting, Q_OK);
+
+  return b;
+}
+
+/**
+ * @brief   Output queue write with timeout.
+ * @details The function writes data from a buffer to an output queue. The
+ *          operation completes when the specified amount of data has been
+ *          transferred or after the specified timeout or if the queue has
+ *          been reset.
+ * @note    The function is not atomic, if you need atomicity it is suggested
+ *          to use a semaphore or a mutex for mutual exclusion.
+ * @note    The callback is invoked after writing each character into the
+ *          buffer.
+ *
+ * @param[in] oqp       pointer to an @p output_queue_t structure
+ * @param[out] bp       pointer to the data buffer
+ * @param[in] n         the maximum amount of data to be transferred, the
+ *                      value 0 is reserved
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The number of bytes effectively transferred.
+ *
+ * @api
+ */
+size_t chOQWriteTimeout(output_queue_t *oqp, const uint8_t *bp,
+                        size_t n, systime_t time) {
+  qnotify_t nfy = oqp->q_notify;
+  size_t w = 0;
+
+  chDbgCheck(n > 0);
+
+  chSysLock();
+  while (true) {
+    while (chOQIsFullI(oqp)) {
+      if (chThdEnqueueTimeoutS(&oqp->q_waiting, time) != Q_OK) {
+        chSysUnlock();
+        return w;
+      }
+    }
+    oqp->q_counter--;
+    *oqp->q_wrptr++ = *bp++;
+    if (oqp->q_wrptr >= oqp->q_top)
+      oqp->q_wrptr = oqp->q_buffer;
+
+    if (nfy)
+      nfy(oqp);
+
+    chSysUnlock(); /* Gives a preemption chance in a controlled point.*/
+    w++;
+    if (--n == 0)
+      return w;
+    chSysLock();
+  }
+}
+#endif  /* CH_CFG_USE_QUEUES */
+
+/** @} */
diff --git a/os/rt/src/chregistry.c b/os/rt/src/chregistry.c
new file mode 100644
index 000000000..685d0c109
--- /dev/null
+++ b/os/rt/src/chregistry.c
@@ -0,0 +1,175 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chregistry.c
+ * @brief   Threads registry code.
+ *
+ * @addtogroup registry
+ * @details Threads Registry related APIs and services.
+ *
+ *          <h2>Operation mode</h2>
+ *          The Threads Registry is a double linked list that holds all the
+ *          active threads in the system.<br>
+ *          Operations defined for the registry:
+ *          - <b>First</b>, returns the first, in creation order, active thread
+ *            in the system.
+ *          - <b>Next</b>, returns the next, in creation order, active thread
+ *            in the system.
+ *          .
+ *          The registry is meant to be mainly a debug feature, for example,
+ *          using the registry a debugger can enumerate the active threads
+ *          in any given moment or the shell can print the active threads
+ *          and their state.<br>
+ *          Another possible use is for centralized threads memory management,
+ *          terminating threads can pulse an event source and an event handler
+ *          can perform a scansion of the registry in order to recover the
+ *          memory.
+ * @pre     In order to use the threads registry the @p CH_CFG_USE_REGISTRY
+ *          option must be enabled in @p chconf.h.
+ * @{
+ */
+#include "ch.h"
+
+#if CH_CFG_USE_REGISTRY || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+#define _offsetof(st, m)                                                    \
+  ((size_t)((char *)&((st *)0)->m - (char *)0))
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/*
+ * OS signature in ROM plus debug-related information.
+ */
+ROMCONST chdebug_t ch_debug = {
+  "main",
+  (uint8_t)0,
+  (uint8_t)sizeof (chdebug_t),
+  (uint16_t)((CH_KERNEL_MAJOR << 11) |
+             (CH_KERNEL_MINOR << 6) |
+             (CH_KERNEL_PATCH) << 0),
+  (uint8_t)sizeof (void *),
+  (uint8_t)sizeof (systime_t),
+  (uint8_t)sizeof (thread_t),
+  (uint8_t)_offsetof(thread_t, p_prio),
+  (uint8_t)_offsetof(thread_t, p_ctx),
+  (uint8_t)_offsetof(thread_t, p_newer),
+  (uint8_t)_offsetof(thread_t, p_older),
+  (uint8_t)_offsetof(thread_t, p_name),
+#if CH_DBG_ENABLE_STACK_CHECK
+  (uint8_t)_offsetof(thread_t, p_stklimit),
+#else
+  (uint8_t)0,
+#endif
+  (uint8_t)_offsetof(thread_t, p_state),
+  (uint8_t)_offsetof(thread_t, p_flags),
+#if CH_CFG_USE_DYNAMIC
+  (uint8_t)_offsetof(thread_t, p_refs),
+#else
+  (uint8_t)0,
+#endif
+#if CH_CFG_TIME_QUANTUM > 0
+  (uint8_t)_offsetof(thread_t, p_preempt),
+#else
+  (uint8_t)0,
+#endif
+#if CH_DBG_THREADS_PROFILING
+  (uint8_t)_offsetof(thread_t, p_time)
+#else
+  (uint8_t)0
+#endif
+};
+
+/**
+ * @brief   Returns the first thread in the system.
+ * @details Returns the most ancient thread in the system, usually this is
+ *          the main thread unless it terminated. A reference is added to the
+ *          returned thread in order to make sure its status is not lost.
+ * @note    This function cannot return @p NULL because there is always at
+ *          least one thread in the system.
+ *
+ * @return              A reference to the most ancient thread.
+ *
+ * @api
+ */
+thread_t *chRegFirstThread(void) {
+  thread_t *tp;
+
+  chSysLock();
+  tp = ch.rlist.r_newer;
+#if CH_CFG_USE_DYNAMIC
+  tp->p_refs++;
+#endif
+  chSysUnlock();
+  return tp;
+}
+
+/**
+ * @brief   Returns the thread next to the specified one.
+ * @details The reference counter of the specified thread is decremented and
+ *          the reference counter of the returned thread is incremented.
+ *
+ * @param[in] tp        pointer to the thread
+ * @return              A reference to the next thread.
+ * @retval NULL         if there is no next thread.
+ *
+ * @api
+ */
+thread_t *chRegNextThread(thread_t *tp) {
+  thread_t *ntp;
+
+  chSysLock();
+  ntp = tp->p_newer;
+  if (ntp == (thread_t *)&ch.rlist)
+    ntp = NULL;
+#if CH_CFG_USE_DYNAMIC
+  else {
+    chDbgAssert(ntp->p_refs < 255, "too many references");
+    ntp->p_refs++;
+  }
+#endif
+  chSysUnlock();
+#if CH_CFG_USE_DYNAMIC
+  chThdRelease(tp);
+#endif
+  return ntp;
+}
+
+#endif /* CH_CFG_USE_REGISTRY */
+
+/** @} */
diff --git a/os/rt/src/chschd.c b/os/rt/src/chschd.c
new file mode 100644
index 000000000..acf65fb85
--- /dev/null
+++ b/os/rt/src/chschd.c
@@ -0,0 +1,521 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chschd.c
+ * @brief   Scheduler code.
+ *
+ * @addtogroup scheduler
+ * @details This module provides the default portable scheduler code.
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   System data structures.
+ */
+ch_system_t ch;
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Scheduler initialization.
+ *
+ * @notapi
+ */
+void _scheduler_init(void) {
+
+  queue_init(&ch.rlist.r_queue);
+  ch.rlist.r_prio = NOPRIO;
+#if CH_CFG_USE_REGISTRY
+  ch.rlist.r_newer = ch.rlist.r_older = (thread_t *)&ch.rlist;
+#endif
+}
+
+#if !CH_CFG_OPTIMIZE_SPEED || defined(__DOXYGEN__)
+/**
+ * @brief   Inserts a thread into a priority ordered queue.
+ * @note    The insertion is done by scanning the list from the highest
+ *          priority toward the lowest.
+ *
+ * @param[in] tp        the pointer to the thread to be inserted in the list
+ * @param[in] tqp       the pointer to the threads list header
+ *
+ * @notapi
+ */
+void queue_prio_insert(thread_t *tp, threads_queue_t *tqp) {
+
+  /* cp iterates over the queue.*/
+  thread_t *cp = (thread_t *)tqp;
+  do {
+    /* Iterate to next thread in queue.*/
+    cp = cp->p_next;
+    /* Not end of queue? and cp has equal or higher priority than tp?.*/
+  } while ((cp != (thread_t *)tqp) && (cp->p_prio >= tp->p_prio));
+  /* Insertion on p_prev.*/
+  tp->p_next = cp;
+  tp->p_prev = cp->p_prev;
+  tp->p_prev->p_next = cp->p_prev = tp;
+}
+
+/**
+ * @brief   Inserts a thread into a queue.
+ *
+ * @param[in] tp        the pointer to the thread to be inserted in the list
+ * @param[in] tqp       the pointer to the threads list header
+ *
+ * @notapi
+ */
+void queue_insert(thread_t *tp, threads_queue_t *tqp) {
+
+  tp->p_next = (thread_t *)tqp;
+  tp->p_prev = tqp->p_prev;
+  tp->p_prev->p_next = tqp->p_prev = tp;
+}
+
+/**
+ * @brief   Removes the first-out thread from a queue and returns it.
+ * @note    If the queue is priority ordered then this function returns the
+ *          thread with the highest priority.
+ *
+ * @param[in] tqp       the pointer to the threads list header
+ * @return              The removed thread pointer.
+ *
+ * @notapi
+ */
+thread_t *queue_fifo_remove(threads_queue_t *tqp) {
+  thread_t *tp = tqp->p_next;
+
+  (tqp->p_next = tp->p_next)->p_prev = (thread_t *)tqp;
+  return tp;
+}
+
+/**
+ * @brief   Removes the last-out thread from a queue and returns it.
+ * @note    If the queue is priority ordered then this function returns the
+ *          thread with the lowest priority.
+ *
+ * @param[in] tqp   the pointer to the threads list header
+ * @return          The removed thread pointer.
+ *
+ * @notapi
+ */
+thread_t *queue_lifo_remove(threads_queue_t *tqp) {
+  thread_t *tp = tqp->p_prev;
+
+  (tqp->p_prev = tp->p_prev)->p_next = (thread_t *)tqp;
+  return tp;
+}
+
+/**
+ * @brief   Removes a thread from a queue and returns it.
+ * @details The thread is removed from the queue regardless of its relative
+ *          position and regardless the used insertion method.
+ *
+ * @param[in] tp        the pointer to the thread to be removed from the queue
+ * @return              The removed thread pointer.
+ *
+ * @notapi
+ */
+thread_t *queue_dequeue(thread_t *tp) {
+
+  tp->p_prev->p_next = tp->p_next;
+  tp->p_next->p_prev = tp->p_prev;
+  return tp;
+}
+
+/**
+ * @brief   Pushes a thread_t on top of a stack list.
+ *
+ * @param[in] tp    the pointer to the thread to be inserted in the list
+ * @param[in] tlp   the pointer to the threads list header
+ *
+ * @notapi
+ */
+void list_insert(thread_t *tp, threads_list_t *tlp) {
+
+  tp->p_next = tlp->p_next;
+  tlp->p_next = tp;
+}
+
+/**
+ * @brief   Pops a thread from the top of a stack list and returns it.
+ * @pre     The list must be non-empty before calling this function.
+ *
+ * @param[in] tlp       the pointer to the threads list header
+ * @return              The removed thread pointer.
+ *
+ * @notapi
+ */
+thread_t *list_remove(threads_list_t *tlp) {
+
+  thread_t *tp = tlp->p_next;
+  tlp->p_next = tp->p_next;
+  return tp;
+}
+#endif /* CH_CFG_OPTIMIZE_SPEED */
+
+/**
+ * @brief   Inserts a thread in the Ready List.
+ * @details The thread is positioned behind all threads with higher or equal
+ *          priority.
+ * @pre     The thread must not be already inserted in any list through its
+ *          @p p_next and @p p_prev or list corruption would occur.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] tp        the thread to be made ready
+ * @return              The thread pointer.
+ *
+ * @iclass
+ */
+thread_t *chSchReadyI(thread_t *tp) {
+  thread_t *cp;
+
+  chDbgCheckClassI();
+  chDbgCheck(tp != NULL);
+  chDbgAssert((tp->p_state != CH_STATE_READY) &&
+              (tp->p_state != CH_STATE_FINAL),
+              "invalid state");
+
+  tp->p_state = CH_STATE_READY;
+  cp = (thread_t *)&ch.rlist.r_queue;
+  do {
+    cp = cp->p_next;
+  } while (cp->p_prio >= tp->p_prio);
+  /* Insertion on p_prev.*/
+  tp->p_next = cp;
+  tp->p_prev = cp->p_prev;
+  tp->p_prev->p_next = cp->p_prev = tp;
+  return tp;
+}
+
+/**
+ * @brief   Puts the current thread to sleep into the specified state.
+ * @details The thread goes into a sleeping state. The possible
+ *          @ref thread_states are defined into @p threads.h.
+ *
+ * @param[in] newstate  the new thread state
+ *
+ * @sclass
+ */
+void chSchGoSleepS(tstate_t newstate) {
+  thread_t *otp;
+
+  chDbgCheckClassS();
+
+  (otp = currp)->p_state = newstate;
+#if CH_CFG_TIME_QUANTUM > 0
+  /* The thread is renouncing its remaining time slices so it will have a new
+     time quantum when it will wakeup.*/
+  otp->p_preempt = CH_CFG_TIME_QUANTUM;
+#endif
+  setcurrp(queue_fifo_remove(&ch.rlist.r_queue));
+#if defined(CH_CFG_IDLE_ENTER_HOOK)
+  if (currp->p_prio == IDLEPRIO) {
+    CH_CFG_IDLE_ENTER_HOOK();
+  }
+#endif
+  currp->p_state = CH_STATE_CURRENT;
+  chSysSwitch(currp, otp);
+}
+
+/*
+ * Timeout wakeup callback.
+ */
+static void wakeup(void *p) {
+  thread_t *tp = (thread_t *)p;
+
+  chSysLockFromISR();
+  switch (tp->p_state) {
+  case CH_STATE_READY:
+    /* Handling the special case where the thread has been made ready by
+       another thread with higher priority.*/
+    chSysUnlockFromISR();
+    return;
+  case CH_STATE_SUSPENDED:
+    *(thread_reference_t *)tp->p_u.wtobjp = NULL;
+    break;
+#if CH_CFG_USE_SEMAPHORES
+  case CH_STATE_WTSEM:
+    chSemFastSignalI((semaphore_t *)tp->p_u.wtobjp);
+    /* Falls into, intentional. */
+#endif
+#if CH_CFG_USE_CONDVARS && CH_CFG_USE_CONDVARS_TIMEOUT
+  case CH_STATE_WTCOND:
+#endif
+  case CH_STATE_QUEUED:
+    /* States requiring dequeuing.*/
+    queue_dequeue(tp);
+  }
+  tp->p_u.rdymsg = MSG_TIMEOUT;
+  chSchReadyI(tp);
+  chSysUnlockFromISR();
+}
+
+/**
+ * @brief   Puts the current thread to sleep into the specified state with
+ *          timeout specification.
+ * @details The thread goes into a sleeping state, if it is not awakened
+ *          explicitly within the specified timeout then it is forcibly
+ *          awakened with a @p MSG_TIMEOUT low level message. The possible
+ *          @ref thread_states are defined into @p threads.h.
+ *
+ * @param[in] newstate  the new thread state
+ * @param[in] time      the number of ticks before the operation timeouts, the
+ *                      special values are handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state, this is equivalent to invoking
+ *                        @p chSchGoSleepS() but, of course, less efficient.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ * @return              The wakeup message.
+ * @retval MSG_TIMEOUT  if a timeout occurs.
+ *
+ * @sclass
+ */
+msg_t chSchGoSleepTimeoutS(tstate_t newstate, systime_t time) {
+
+  chDbgCheckClassS();
+
+  if (TIME_INFINITE != time) {
+    virtual_timer_t vt;
+
+    chVTDoSetI(&vt, time, wakeup, currp);
+    chSchGoSleepS(newstate);
+    if (chVTIsArmedI(&vt))
+      chVTDoResetI(&vt);
+  }
+  else
+    chSchGoSleepS(newstate);
+  return currp->p_u.rdymsg;
+}
+
+/**
+ * @brief   Wakes up a thread.
+ * @details The thread is inserted into the ready list or immediately made
+ *          running depending on its relative priority compared to the current
+ *          thread.
+ * @pre     The thread must not be already inserted in any list through its
+ *          @p p_next and @p p_prev or list corruption would occur.
+ * @note    It is equivalent to a @p chSchReadyI() followed by a
+ *          @p chSchRescheduleS() but much more efficient.
+ * @note    The function assumes that the current thread has the highest
+ *          priority.
+ *
+ * @param[in] ntp       the thread to be made ready
+ * @param[in] msg       the wakeup message
+ *
+ * @sclass
+ */
+void chSchWakeupS(thread_t *ntp, msg_t msg) {
+
+  chDbgCheckClassS();
+
+  /* Storing the message to be retrieved by the target thread when it will
+     restart execution.*/
+  ntp->p_u.rdymsg = msg;
+
+  /* If the waken thread has a not-greater priority than the current
+     one then it is just inserted in the ready list else it made
+     running immediately and the invoking thread goes in the ready
+     list instead.*/
+  if (ntp->p_prio <= currp->p_prio) {
+    chSchReadyI(ntp);
+  }
+  else {
+    thread_t *otp = chSchReadyI(currp);
+    setcurrp(ntp);
+#if defined(CH_CFG_IDLE_LEAVE_HOOK)
+  if (otp->p_prio == IDLEPRIO) {
+    CH_CFG_IDLE_LEAVE_HOOK();
+  }
+#endif
+    ntp->p_state = CH_STATE_CURRENT;
+    chSysSwitch(ntp, otp);
+  }
+}
+
+/**
+ * @brief   Performs a reschedule if a higher priority thread is runnable.
+ * @details If a thread with a higher priority than the current thread is in
+ *          the ready list then make the higher priority thread running.
+ *
+ * @sclass
+ */
+void chSchRescheduleS(void) {
+
+  chDbgCheckClassS();
+
+  if (chSchIsRescRequiredI())
+    chSchDoRescheduleAhead();
+}
+
+/**
+ * @brief   Evaluates if preemption is required.
+ * @details The decision is taken by comparing the relative priorities and
+ *          depending on the state of the round robin timeout counter.
+ * @note    Not a user function, it is meant to be invoked by the scheduler
+ *          itself or from within the port layer.
+ *
+ * @retval true         if there is a thread that must go in running state
+ *                      immediately.
+ * @retval false        if preemption is not required.
+ *
+ * @special
+ */
+bool chSchIsPreemptionRequired(void) {
+  tprio_t p1 = firstprio(&ch.rlist.r_queue);
+  tprio_t p2 = currp->p_prio;
+#if CH_CFG_TIME_QUANTUM > 0
+  /* If the running thread has not reached its time quantum, reschedule only
+     if the first thread on the ready queue has a higher priority.
+     Otherwise, if the running thread has used up its time quantum, reschedule
+     if the first thread on the ready queue has equal or higher priority.*/
+  return currp->p_preempt ? p1 > p2 : p1 >= p2;
+#else
+  /* If the round robin preemption feature is not enabled then performs a
+     simpler comparison.*/
+  return p1 > p2;
+#endif
+}
+
+/**
+ * @brief   Switches to the first thread on the runnable queue.
+ * @details The current thread is positioned in the ready list behind all
+ *          threads having the same priority. The thread regains its time
+ *          quantum.
+ * @note    Not a user function, it is meant to be invoked by the scheduler
+ *          itself or from within the port layer.
+ *
+ * @special
+ */
+void chSchDoRescheduleBehind(void) {
+  thread_t *otp;
+
+  otp = currp;
+  /* Picks the first thread from the ready queue and makes it current.*/
+  setcurrp(queue_fifo_remove(&ch.rlist.r_queue));
+#if defined(CH_CFG_IDLE_LEAVE_HOOK)
+  if (otp->p_prio == IDLEPRIO) {
+    CH_CFG_IDLE_LEAVE_HOOK();
+  }
+#endif
+  currp->p_state = CH_STATE_CURRENT;
+#if CH_CFG_TIME_QUANTUM > 0
+  otp->p_preempt = CH_CFG_TIME_QUANTUM;
+#endif
+  chSchReadyI(otp);
+  chSysSwitch(currp, otp);
+}
+
+/**
+ * @brief   Switches to the first thread on the runnable queue.
+ * @details The current thread is positioned in the ready list ahead of all
+ *          threads having the same priority.
+ * @note    Not a user function, it is meant to be invoked by the scheduler
+ *          itself or from within the port layer.
+ *
+ * @special
+ */
+void chSchDoRescheduleAhead(void) {
+  thread_t *otp, *cp;
+
+  otp = currp;
+  /* Picks the first thread from the ready queue and makes it current.*/
+  setcurrp(queue_fifo_remove(&ch.rlist.r_queue));
+#if defined(CH_CFG_IDLE_LEAVE_HOOK)
+  if (otp->p_prio == IDLEPRIO) {
+    CH_CFG_IDLE_LEAVE_HOOK();
+  }
+#endif
+  currp->p_state = CH_STATE_CURRENT;
+
+  otp->p_state = CH_STATE_READY;
+  cp = (thread_t *)&ch.rlist.r_queue;
+  do {
+    cp = cp->p_next;
+  } while (cp->p_prio > otp->p_prio);
+  /* Insertion on p_prev.*/
+  otp->p_next = cp;
+  otp->p_prev = cp->p_prev;
+  otp->p_prev->p_next = cp->p_prev = otp;
+
+  chSysSwitch(currp, otp);
+}
+
+/**
+ * @brief   Switches to the first thread on the runnable queue.
+ * @details The current thread is positioned in the ready list behind or
+ *          ahead of all threads having the same priority depending on
+ *          if it used its whole time slice.
+ * @note    Not a user function, it is meant to be invoked by the scheduler
+ *          itself or from within the port layer.
+ *
+ * @special
+ */
+void chSchDoReschedule(void) {
+
+#if CH_CFG_TIME_QUANTUM > 0
+  /* If CH_CFG_TIME_QUANTUM is enabled then there are two different scenarios
+     to handle on preemption: time quantum elapsed or not.*/
+  if (currp->p_preempt == 0) {
+    /* The thread consumed its time quantum so it is enqueued behind threads
+       with same priority level, however, it acquires a new time quantum.*/
+    chSchDoRescheduleBehind();
+  }
+  else {
+    /* The thread didn't consume all its time quantum so it is put ahead of
+       threads with equal priority and does not acquire a new time quantum.*/
+    chSchDoRescheduleAhead();
+  }
+#else /* !(CH_CFG_TIME_QUANTUM > 0) */
+  /* If the round-robin mechanism is disabled then the thread goes always
+     ahead of its peers.*/
+  chSchDoRescheduleAhead();
+#endif /* !(CH_CFG_TIME_QUANTUM > 0) */
+}
+
+/** @} */
diff --git a/os/rt/src/chsem.c b/os/rt/src/chsem.c
new file mode 100644
index 000000000..22e4413b6
--- /dev/null
+++ b/os/rt/src/chsem.c
@@ -0,0 +1,401 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chsem.c
+ * @brief   Semaphores code.
+ *
+ * @addtogroup semaphores
+ * @details Semaphores related APIs and services.
+ *
+ *          <h2>Operation mode</h2>
+ *          Semaphores are a flexible synchronization primitive, ChibiOS/RT
+ *          implements semaphores in their "counting semaphores" variant as
+ *          defined by Edsger Dijkstra plus several enhancements like:
+ *          - Wait operation with timeout.
+ *          - Reset operation.
+ *          - Atomic wait+signal operation.
+ *          - Return message from the wait operation (OK, RESET, TIMEOUT).
+ *          .
+ *          The binary semaphores variant can be easily implemented using
+ *          counting semaphores.<br>
+ *          Operations defined for semaphores:
+ *          - <b>Signal</b>: The semaphore counter is increased and if the
+ *            result is non-positive then a waiting thread is removed from
+ *            the semaphore queue and made ready for execution.
+ *          - <b>Wait</b>: The semaphore counter is decreased and if the result
+ *            becomes negative the thread is queued in the semaphore and
+ *            suspended.
+ *          - <b>Reset</b>: The semaphore counter is reset to a non-negative
+ *            value and all the threads in the queue are released.
+ *          .
+ *          Semaphores can be used as guards for mutual exclusion zones
+ *          (note that mutexes are recommended for this kind of use) but
+ *          also have other uses, queues guards and counters for example.<br>
+ *          Semaphores usually use a FIFO queuing strategy but it is possible
+ *          to make them order threads by priority by enabling
+ *          @p CH_CFG_USE_SEMAPHORES_PRIORITY in @p chconf.h.
+ * @pre     In order to use the semaphore APIs the @p CH_CFG_USE_SEMAPHORES
+ *          option must be enabled in @p chconf.h.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_SEMAPHORES || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+#if CH_CFG_USE_SEMAPHORES_PRIORITY
+#define sem_insert(tp, qp) prio_insert(tp, qp)
+#else
+#define sem_insert(tp, qp) queue_insert(tp, qp)
+#endif
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes a semaphore with the specified counter value.
+ *
+ * @param[out] sp       pointer to a @p semaphore_t structure
+ * @param[in] n         initial value of the semaphore counter. Must be
+ *                      non-negative.
+ *
+ * @init
+ */
+void chSemObjectInit(semaphore_t *sp, cnt_t n) {
+
+  chDbgCheck((sp != NULL) && (n >= 0));
+
+  queue_init(&sp->s_queue);
+  sp->s_cnt = n;
+}
+
+/**
+ * @brief   Performs a reset operation on the semaphore.
+ * @post    After invoking this function all the threads waiting on the
+ *          semaphore, if any, are released and the semaphore counter is set
+ *          to the specified, non negative, value.
+ * @note    The released threads can recognize they were waked up by a reset
+ *          rather than a signal because the @p chSemWait() will return
+ *          @p MSG_RESET instead of @p MSG_OK.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @param[in] n         the new value of the semaphore counter. The value must
+ *                      be non-negative.
+ *
+ * @api
+ */
+void chSemReset(semaphore_t *sp, cnt_t n) {
+
+  chSysLock();
+  chSemResetI(sp, n);
+  chSchRescheduleS();
+  chSysUnlock();
+}
+
+/**
+ * @brief   Performs a reset operation on the semaphore.
+ * @post    After invoking this function all the threads waiting on the
+ *          semaphore, if any, are released and the semaphore counter is set
+ *          to the specified, non negative, value.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ * @note    The released threads can recognize they were waked up by a reset
+ *          rather than a signal because the @p chSemWait() will return
+ *          @p MSG_RESET instead of @p MSG_OK.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @param[in] n         the new value of the semaphore counter. The value must
+ *                      be non-negative.
+ *
+ * @iclass
+ */
+void chSemResetI(semaphore_t *sp, cnt_t n) {
+  cnt_t cnt;
+
+  chDbgCheckClassI();
+  chDbgCheck((sp != NULL) && (n >= 0));
+  chDbgAssert(((sp->s_cnt >= 0) && queue_isempty(&sp->s_queue)) ||
+              ((sp->s_cnt < 0) && queue_notempty(&sp->s_queue)),
+              "inconsistent semaphore");
+
+  cnt = sp->s_cnt;
+  sp->s_cnt = n;
+  while (++cnt <= 0)
+    chSchReadyI(queue_lifo_remove(&sp->s_queue))->p_u.rdymsg = MSG_RESET;
+}
+
+/**
+ * @brief   Performs a wait operation on a semaphore.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval MSG_OK       if the thread has not stopped on the semaphore or the
+ *                      semaphore has been signaled.
+ * @retval MSG_RESET    if the semaphore has been reset using @p chSemReset().
+ *
+ * @api
+ */
+msg_t chSemWait(semaphore_t *sp) {
+  msg_t msg;
+
+  chSysLock();
+  msg = chSemWaitS(sp);
+  chSysUnlock();
+  return msg;
+}
+
+/**
+ * @brief   Performs a wait operation on a semaphore.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval MSG_OK       if the thread has not stopped on the semaphore or the
+ *                      semaphore has been signaled.
+ * @retval MSG_RESET    if the semaphore has been reset using @p chSemReset().
+ *
+ * @sclass
+ */
+msg_t chSemWaitS(semaphore_t *sp) {
+
+  chDbgCheckClassS();
+  chDbgCheck(sp != NULL);
+  chDbgAssert(((sp->s_cnt >= 0) && queue_isempty(&sp->s_queue)) ||
+              ((sp->s_cnt < 0) && queue_notempty(&sp->s_queue)),
+              "inconsistent semaphore");
+
+  if (--sp->s_cnt < 0) {
+    currp->p_u.wtobjp = sp;
+    sem_insert(currp, &sp->s_queue);
+    chSchGoSleepS(CH_STATE_WTSEM);
+    return currp->p_u.rdymsg;
+  }
+  return MSG_OK;
+}
+
+/**
+ * @brief   Performs a wait operation on a semaphore with timeout specification.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval MSG_OK       if the thread has not stopped on the semaphore or the
+ *                      semaphore has been signaled.
+ * @retval MSG_RESET    if the semaphore has been reset using @p chSemReset().
+ * @retval MSG_TIMEOUT  if the semaphore has not been signaled or reset within
+ *                      the specified timeout.
+ *
+ * @api
+ */
+msg_t chSemWaitTimeout(semaphore_t *sp, systime_t time) {
+  msg_t msg;
+
+  chSysLock();
+  msg = chSemWaitTimeoutS(sp, time);
+  chSysUnlock();
+  return msg;
+}
+
+/**
+ * @brief   Performs a wait operation on a semaphore with timeout specification.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @param[in] time      the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_IMMEDIATE immediate timeout.
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval MSG_OK       if the thread has not stopped on the semaphore or the
+ *                      semaphore has been signaled.
+ * @retval MSG_RESET    if the semaphore has been reset using @p chSemReset().
+ * @retval MSG_TIMEOUT  if the semaphore has not been signaled or reset within
+ *                      the specified timeout.
+ *
+ * @sclass
+ */
+msg_t chSemWaitTimeoutS(semaphore_t *sp, systime_t time) {
+
+  chDbgCheckClassS();
+  chDbgCheck(sp != NULL);
+  chDbgAssert(((sp->s_cnt >= 0) && queue_isempty(&sp->s_queue)) ||
+              ((sp->s_cnt < 0) && queue_notempty(&sp->s_queue)),
+              "inconsistent semaphore");
+
+  if (--sp->s_cnt < 0) {
+    if (TIME_IMMEDIATE == time) {
+      sp->s_cnt++;
+      return MSG_TIMEOUT;
+    }
+    currp->p_u.wtobjp = sp;
+    sem_insert(currp, &sp->s_queue);
+    return chSchGoSleepTimeoutS(CH_STATE_WTSEM, time);
+  }
+  return MSG_OK;
+}
+
+/**
+ * @brief   Performs a signal operation on a semaphore.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ *
+ * @api
+ */
+void chSemSignal(semaphore_t *sp) {
+
+  chDbgCheck(sp != NULL);
+  chDbgAssert(((sp->s_cnt >= 0) && queue_isempty(&sp->s_queue)) ||
+              ((sp->s_cnt < 0) && queue_notempty(&sp->s_queue)),
+              "inconsistent semaphore");
+
+  chSysLock();
+  if (++sp->s_cnt <= 0)
+    chSchWakeupS(queue_fifo_remove(&sp->s_queue), MSG_OK);
+  chSysUnlock();
+}
+
+/**
+ * @brief   Performs a signal operation on a semaphore.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp    pointer to a @p semaphore_t structure
+ *
+ * @iclass
+ */
+void chSemSignalI(semaphore_t *sp) {
+
+  chDbgCheckClassI();
+  chDbgCheck(sp != NULL);
+  chDbgAssert(((sp->s_cnt >= 0) && queue_isempty(&sp->s_queue)) ||
+              ((sp->s_cnt < 0) && queue_notempty(&sp->s_queue)),
+              "inconsistent semaphore");
+
+  if (++sp->s_cnt <= 0) {
+    /* Note, it is done this way in order to allow a tail call on
+             chSchReadyI().*/
+    thread_t *tp = queue_fifo_remove(&sp->s_queue);
+    tp->p_u.rdymsg = MSG_OK;
+    chSchReadyI(tp);
+  }
+}
+
+/**
+ * @brief   Adds the specified value to the semaphore counter.
+ * @post    This function does not reschedule so a call to a rescheduling
+ *          function must be performed before unlocking the kernel. Note that
+ *          interrupt handlers always reschedule on exit so an explicit
+ *          reschedule must not be performed in ISRs.
+ *
+ * @param[in] sp        pointer to a @p semaphore_t structure
+ * @param[in] n         value to be added to the semaphore counter. The value
+ *                      must be positive.
+ *
+ * @iclass
+ */
+void chSemAddCounterI(semaphore_t *sp, cnt_t n) {
+
+  chDbgCheckClassI();
+  chDbgCheck((sp != NULL) && (n > 0));
+  chDbgAssert(((sp->s_cnt >= 0) && queue_isempty(&sp->s_queue)) ||
+              ((sp->s_cnt < 0) && queue_notempty(&sp->s_queue)),
+              "inconsistent semaphore");
+
+  while (n > 0) {
+    if (++sp->s_cnt <= 0)
+      chSchReadyI(queue_fifo_remove(&sp->s_queue))->p_u.rdymsg = MSG_OK;
+    n--;
+  }
+}
+
+/**
+ * @brief   Performs atomic signal and wait operations on two semaphores.
+ *
+ * @param[in] sps       pointer to a @p semaphore_t structure to be signaled
+ * @param[in] spw       pointer to a @p semaphore_t structure to wait on
+ * @return              A message specifying how the invoking thread has been
+ *                      released from the semaphore.
+ * @retval MSG_OK       if the thread has not stopped on the semaphore or the
+ *                      semaphore has been signaled.
+ * @retval MSG_RESET    if the semaphore has been reset using @p chSemReset().
+ *
+ * @api
+ */
+msg_t chSemSignalWait(semaphore_t *sps, semaphore_t *spw) {
+  msg_t msg;
+
+  chDbgCheck((sps != NULL) && (spw != NULL));
+  chDbgAssert(((sps->s_cnt >= 0) && queue_isempty(&sps->s_queue)) ||
+              ((sps->s_cnt < 0) && queue_notempty(&sps->s_queue)),
+              "inconsistent semaphore");
+  chDbgAssert(((spw->s_cnt >= 0) && queue_isempty(&spw->s_queue)) ||
+              ((spw->s_cnt < 0) && queue_notempty(&spw->s_queue)),
+              "inconsistent semaphore");
+
+  chSysLock();
+  if (++sps->s_cnt <= 0)
+    chSchReadyI(queue_fifo_remove(&sps->s_queue))->p_u.rdymsg = MSG_OK;
+  if (--spw->s_cnt < 0) {
+    thread_t *ctp = currp;
+    sem_insert(ctp, &spw->s_queue);
+    ctp->p_u.wtobjp = spw;
+    chSchGoSleepS(CH_STATE_WTSEM);
+    msg = ctp->p_u.rdymsg;
+  }
+  else {
+    chSchRescheduleS();
+    msg = MSG_OK;
+  }
+  chSysUnlock();
+  return msg;
+}
+
+#endif /* CH_CFG_USE_SEMAPHORES */
+
+/** @} */
diff --git a/os/rt/src/chstats.c b/os/rt/src/chstats.c
new file mode 100644
index 000000000..653d8da77
--- /dev/null
+++ b/os/rt/src/chstats.c
@@ -0,0 +1,122 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chstats.c
+ * @brief   Statistics module code.
+ *
+ * @addtogroup statistics
+ * @details Statistics services.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_DBG_STATISTICS || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the statistics module.
+ *
+ * @init
+ */
+void _stats_init(void) {
+
+  ch.kernel_stats.n_irq = 0;
+  ch.kernel_stats.n_ctxswc = 0;
+  chTMObjectInit(&ch.kernel_stats.m_crit_thd);
+  chTMObjectInit(&ch.kernel_stats.m_crit_isr);
+}
+
+/**
+ * @brief   Increases the IRQ counter.
+ */
+void _stats_increase_irq(void) {
+
+  ch.kernel_stats.n_irq++;
+}
+
+/**
+ * @brief   Updates context switch related statistics.
+ */
+void _stats_ctxswc(thread_t *ntp, thread_t *otp) {
+
+  ch.kernel_stats.n_ctxswc++;
+  chTMChainMeasurementToX(&otp->p_stats, &ntp->p_stats);
+}
+
+/**
+ * @brief   Starts the measurement of a thread critical zone.
+ */
+void _stats_start_measure_crit_thd(void) {
+
+  chTMStartMeasurementX(&ch.kernel_stats.m_crit_thd);
+}
+
+/**
+ * @brief   Stops the measurement of a thread critical zone.
+ */
+void _stats_stop_measure_crit_thd(void) {
+
+  chTMStopMeasurementX(&ch.kernel_stats.m_crit_thd);
+}
+
+/**
+ * @brief   Starts the measurement of an ISR critical zone.
+ */
+void _stats_start_measure_crit_isr(void) {
+
+  chTMStartMeasurementX(&ch.kernel_stats.m_crit_isr);
+}
+
+/**
+ * @brief   Stops the measurement of an ISR critical zone.
+ */
+void _stats_stop_measure_crit_isr(void) {
+
+  chTMStopMeasurementX(&ch.kernel_stats.m_crit_isr);
+}
+
+#endif /* CH_DBG_STATISTICS */
+
+/** @} */
diff --git a/os/rt/src/chsys.c b/os/rt/src/chsys.c
new file mode 100644
index 000000000..f7fd6766b
--- /dev/null
+++ b/os/rt/src/chsys.c
@@ -0,0 +1,303 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chsys.c
+ * @brief   System related code.
+ *
+ * @addtogroup system
+ * @details System related APIs and services:
+ *          - Initialization.
+ *          - Locks.
+ *          - Interrupt Handling.
+ *          - Power Management.
+ *          - Abnormal Termination.
+ *          - Realtime counter.
+ *          .
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+#if !CH_CFG_NO_IDLE_THREAD || defined(__DOXYGEN__)
+/**
+ * @brief   Idle thread working area.
+ */
+static THD_WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE);
+#endif /* CH_CFG_NO_IDLE_THREAD */
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+#if !CH_CFG_NO_IDLE_THREAD || defined(__DOXYGEN__)
+/**
+ * @brief   This function implements the idle thread infinite loop.
+ * @details The function puts the processor in the lowest power mode capable
+ *          to serve interrupts.<br>
+ *          The priority is internally set to the minimum system value so
+ *          that this thread is executed only if there are no other ready
+ *          threads in the system.
+ *
+ * @param[in] p the thread parameter, unused in this scenario
+ */
+static void _idle_thread(void *p) {
+
+  (void)p;
+  chRegSetThreadName("idle");
+  while (true) {
+    port_wait_for_interrupt();
+    CH_CFG_IDLE_LOOP_HOOK();
+  }
+}
+#endif /* CH_CFG_NO_IDLE_THREAD */
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   ChibiOS/RT initialization.
+ * @details After executing this function the current instructions stream
+ *          becomes the main thread.
+ * @pre     Interrupts must be still disabled when @p chSysInit() is invoked
+ *          and are internally enabled.
+ * @post    The main thread is created with priority @p NORMALPRIO.
+ * @note    This function has special, architecture-dependent, requirements,
+ *          see the notes into the various port reference manuals.
+ *
+ * @special
+ */
+void chSysInit(void) {
+  static thread_t mainthread;
+#if CH_DBG_ENABLE_STACK_CHECK
+  extern stkalign_t __main_thread_stack_base__;
+#endif
+
+  port_init();
+  _scheduler_init();
+  _vt_init();
+#if CH_CFG_USE_TM
+  _tm_init();
+#endif
+#if CH_CFG_USE_MEMCORE
+  _core_init();
+#endif
+#if CH_CFG_USE_HEAP
+  _heap_init();
+#endif
+#if CH_DBG_STATISTICS
+  _stats_init();
+#endif
+#if CH_DBG_ENABLE_TRACE
+  _trace_init();
+#endif
+
+#if !CH_CFG_NO_IDLE_THREAD
+  /* Now this instructions flow becomes the main thread.*/
+  setcurrp(_thread_init(&mainthread, NORMALPRIO));
+#else
+  /* Now this instructions flow becomes the main thread.*/
+  setcurrp(_thread_init(&mainthread, IDLEPRIO));
+#endif
+
+  currp->p_state = CH_STATE_CURRENT;
+#if CH_DBG_ENABLE_STACK_CHECK
+  /* This is a special case because the main thread thread_t structure is not
+     adjacent to its stack area.*/
+  currp->p_stklimit = &__main_thread_stack_base__;
+#endif
+  chSysEnable();
+
+  /* Note, &ch_debug points to the string "main" if the registry is
+     active, else the parameter is ignored.*/
+  chRegSetThreadName((const char *)&ch_debug);
+
+#if !CH_CFG_NO_IDLE_THREAD
+  /* This thread has the lowest priority in the system, its role is just to
+     serve interrupts in its context while keeping the lowest energy saving
+     mode compatible with the system status.*/
+  chThdCreateStatic(_idle_thread_wa, sizeof(_idle_thread_wa), IDLEPRIO,
+                    (tfunc_t)_idle_thread, NULL);
+#endif
+}
+
+/**
+ * @brief   Halts the system.
+ * @details This function is invoked by the operating system when an
+ *          unrecoverable error is detected, for example because a programming
+ *          error in the application code that triggers an assertion while
+ *          in debug mode.
+ * @note    Can be invoked from any system state.
+ *
+ * @special
+ */
+void chSysHalt(const char *reason) {
+
+  port_disable();
+
+#if CH_DBG_ENABLED
+  ch.dbg_panic_msg = reason;
+#else
+  (void)reason;
+#endif
+
+#if defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+  CH_CFG_SYSTEM_HALT_HOOK(reason);
+#endif
+
+  /* Harmless infinite loop.*/
+  while (true)
+    ;
+}
+
+/**
+ * @brief   Handles time ticks for round robin preemption and timer increments.
+ * @details Decrements the remaining time quantum of the running thread
+ *          and preempts it when the quantum is used up. Increments system
+ *          time and manages the timers.
+ * @note    The frequency of the timer determines the system tick granularity
+ *          and, together with the @p CH_CFG_TIME_QUANTUM macro, the round robin
+ *          interval.
+ *
+ * @iclass
+ */
+void chSysTimerHandlerI(void) {
+
+  chDbgCheckClassI();
+
+#if CH_CFG_TIME_QUANTUM > 0
+  /* Running thread has not used up quantum yet? */
+  if (currp->p_preempt > 0)
+    /* Decrement remaining quantum.*/
+    currp->p_preempt--;
+#endif
+#if CH_DBG_THREADS_PROFILING
+  currp->p_time++;
+#endif
+  chVTDoTickI();
+#if defined(CH_CFG_SYSTEM_TICK_HOOK)
+  CH_CFG_SYSTEM_TICK_HOOK();
+#endif
+}
+
+/**
+ * @brief   Returns the execution status and enters a critical zone.
+ * @details This functions enters into a critical zone and can be called
+ *          from any context. Because its flexibility it is less efficient
+ *          than @p chSysLock() which is preferable when the calling context
+ *          is known.
+ * @post    The system is in a critical zone.
+ *
+ * @return              The previous system status, the encoding of this
+ *                      status word is architecture-dependent and opaque.
+ *
+ * @xclass
+ */
+syssts_t chSysGetStatusAndLockX(void) {
+
+  syssts_t sts = port_get_irq_status();
+  if (port_irq_enabled(sts)) {
+    if (port_is_isr_context())
+      chSysLockFromISR();
+    else
+      chSysLock();
+  }
+  return sts;
+}
+
+/**
+ * @brief   Restores the specified execution status and leaves a critical zone.
+ * @note    A call to @p chSchRescheduleS() is automatically performed
+ *          if exiting the critical zone and if not in ISR context.
+ *
+ * @param[in] sts       the system status to be restored.
+ *
+ * @xclass
+ */
+void chSysRestoreStatusX(syssts_t sts) {
+
+  if (port_irq_enabled(sts)) {
+    if (port_is_isr_context())
+      chSysUnlockFromISR();
+    else {
+      chSchRescheduleS();
+      chSysUnlock();
+    }
+  }
+}
+
+#if PORT_SUPPORTS_RT || defined(__DOXYGEN__)
+/**
+ * @brief   Realtime window test.
+ * @details This function verifies if the current realtime counter value
+ *          lies within the specified range or not. The test takes care
+ *          of the realtime counter wrapping to zero on overflow.
+ * @note    When start==end then the function returns always true because the
+ *          whole time range is specified.
+ * @note    This function is only available if the port layer supports the
+ *          option @p PORT_SUPPORTS_RT.
+ *
+ * @param[in] cnt       the counter value to be tested
+ * @param[in] start     the start of the time window (inclusive)
+ * @param[in] end       the end of the time window (non inclusive)
+ * @retval true         current time within the specified time window.
+ * @retval false        current time not within the specified time window.
+ *
+ * @xclass
+ */
+bool chSysIsCounterWithinX(rtcnt_t cnt, rtcnt_t start, rtcnt_t end) {
+
+  return end > start ? (cnt >= start) && (cnt < end) :
+                       (cnt >= start) || (cnt < end);
+}
+
+/**
+ * @brief   Polled delay.
+ * @note    The real delay is always few cycles in excess of the specified
+ *          value.
+ * @note    This function is only available if the port layer supports the
+ *          option @p PORT_SUPPORTS_RT.
+ *
+ * @param[in] cycles    number of cycles
+ *
+ * @xclass
+ */
+void chSysPolledDelayX(rtcnt_t cycles) {
+  rtcnt_t start = chSysGetRealtimeCounterX();
+  rtcnt_t end  = start + cycles;
+  while (chSysIsCounterWithinX(chSysGetRealtimeCounterX(), start, end))
+    ;
+}
+#endif /* PORT_SUPPORTS_RT */
+
+/** @} */
diff --git a/os/rt/src/chthreads.c b/os/rt/src/chthreads.c
new file mode 100644
index 000000000..c10ccb70c
--- /dev/null
+++ b/os/rt/src/chthreads.c
@@ -0,0 +1,645 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chthreads.c
+ * @brief   Threads code.
+ *
+ * @addtogroup threads
+ * @details Threads related APIs and services.
+ *
+ *          <h2>Operation mode</h2>
+ *          A thread is an abstraction of an independent instructions flow.
+ *          In ChibiOS/RT a thread is represented by a "C" function owning
+ *          a processor context, state informations and a dedicated stack
+ *          area. In this scenario static variables are shared among all
+ *          threads while automatic variables are local to the thread.<br>
+ *          Operations defined for threads:
+ *          - <b>Create</b>, a thread is started on the specified thread
+ *            function. This operation is available in multiple variants,
+ *            both static and dynamic.
+ *          - <b>Exit</b>, a thread terminates by returning from its top
+ *            level function or invoking a specific API, the thread can
+ *            return a value that can be retrieved by other threads.
+ *          - <b>Wait</b>, a thread waits for the termination of another
+ *            thread and retrieves its return value.
+ *          - <b>Resume</b>, a thread created in suspended state is started.
+ *          - <b>Sleep</b>, the execution of a thread is suspended for the
+ *            specified amount of time or the specified future absolute time
+ *            is reached.
+ *          - <b>SetPriority</b>, a thread changes its own priority level.
+ *          - <b>Yield</b>, a thread voluntarily renounces to its time slot.
+ *          .
+ *          The threads subsystem is implicitly included in kernel however
+ *          some of its part may be excluded by disabling them in @p chconf.h,
+ *          see the @p CH_CFG_USE_WAITEXIT and @p CH_CFG_USE_DYNAMIC configuration
+ *          options.
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes a thread structure.
+ * @note    This is an internal functions, do not use it in application code.
+ *
+ * @param[in] tp        pointer to the thread
+ * @param[in] prio      the priority level for the new thread
+ * @return              The same thread pointer passed as parameter.
+ *
+ * @notapi
+ */
+thread_t *_thread_init(thread_t *tp, tprio_t prio) {
+
+  tp->p_prio = prio;
+  tp->p_state = CH_STATE_WTSTART;
+  tp->p_flags = CH_FLAG_MODE_STATIC;
+#if CH_CFG_TIME_QUANTUM > 0
+  tp->p_preempt = CH_CFG_TIME_QUANTUM;
+#endif
+#if CH_CFG_USE_MUTEXES
+  tp->p_realprio = prio;
+  tp->p_mtxlist = NULL;
+#endif
+#if CH_CFG_USE_EVENTS
+  tp->p_epending = 0;
+#endif
+#if CH_DBG_THREADS_PROFILING
+  tp->p_time = 0;
+#endif
+#if CH_CFG_USE_DYNAMIC
+  tp->p_refs = 1;
+#endif
+#if CH_CFG_USE_REGISTRY
+  tp->p_name = NULL;
+  REG_INSERT(tp);
+#endif
+#if CH_CFG_USE_WAITEXIT
+  list_init(&tp->p_waiting);
+#endif
+#if CH_CFG_USE_MESSAGES
+  queue_init(&tp->p_msgqueue);
+#endif
+#if CH_DBG_ENABLE_STACK_CHECK
+  tp->p_stklimit = (stkalign_t *)(tp + 1);
+#endif
+#if CH_DBG_STATISTICS || defined(__DOXYGEN__)
+  chTMObjectInit(&tp->p_stats);
+  chTMStartMeasurementX(&tp->p_stats);
+#endif
+#if defined(CH_CFG_THREAD_INIT_HOOK)
+  CH_CFG_THREAD_INIT_HOOK(tp);
+#endif
+  return tp;
+}
+
+#if CH_DBG_FILL_THREADS || defined(__DOXYGEN__)
+/**
+ * @brief   Memory fill utility.
+ *
+ * @param[in] startp    first address to fill
+ * @param[in] endp      last address to fill +1
+ * @param[in] v         filler value
+ *
+ * @notapi
+ */
+void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v) {
+
+  while (startp < endp)
+    *startp++ = v;
+}
+#endif /* CH_DBG_FILL_THREADS */
+
+/**
+ * @brief   Creates a new thread into a static memory area.
+ * @details The new thread is initialized but not inserted in the ready list,
+ *          the initial state is @p CH_STATE_WTSTART.
+ * @post    The initialized thread can be subsequently started by invoking
+ *          @p chThdStart(), @p chThdStartI() or @p chSchWakeupS()
+ *          depending on the execution context.
+ * @note    A thread can terminate by calling @p chThdExit() or by simply
+ *          returning from its main function.
+ * @note    Threads created using this function do not obey to the
+ *          @p CH_DBG_FILL_THREADS debug option because it would keep
+ *          the kernel locked for too much time.
+ *
+ * @param[out] wsp      pointer to a working area dedicated to the thread stack
+ * @param[in] size      size of the working area
+ * @param[in] prio      the priority level for the new thread
+ * @param[in] pf        the thread function
+ * @param[in] arg       an argument passed to the thread function. It can be
+ *                      @p NULL.
+ * @return              The pointer to the @p thread_t structure allocated for
+ *                      the thread into the working space area.
+ *
+ * @iclass
+ */
+thread_t *chThdCreateI(void *wsp, size_t size,
+                     tprio_t prio, tfunc_t pf, void *arg) {
+  /* The thread structure is laid out in the lower part of the thread
+     workspace.*/
+  thread_t *tp = wsp;
+
+  chDbgCheckClassI();
+  chDbgCheck((wsp != NULL) && (size >= THD_WORKING_AREA_SIZE(0)) &&
+             (prio <= HIGHPRIO) && (pf != NULL));
+
+  PORT_SETUP_CONTEXT(tp, wsp, size, pf, arg);
+  return _thread_init(tp, prio);
+}
+
+/**
+ * @brief   Creates a new thread into a static memory area.
+ * @note    A thread can terminate by calling @p chThdExit() or by simply
+ *          returning from its main function.
+ *
+ * @param[out] wsp      pointer to a working area dedicated to the thread stack
+ * @param[in] size      size of the working area
+ * @param[in] prio      the priority level for the new thread
+ * @param[in] pf        the thread function
+ * @param[in] arg       an argument passed to the thread function. It can be
+ *                      @p NULL.
+ * @return              The pointer to the @p thread_t structure allocated for
+ *                      the thread into the working space area.
+ *
+ * @api
+ */
+thread_t *chThdCreateStatic(void *wsp, size_t size,
+                            tprio_t prio, tfunc_t pf, void *arg) {
+  thread_t *tp;
+  
+#if CH_DBG_FILL_THREADS
+  _thread_memfill((uint8_t *)wsp,
+                  (uint8_t *)wsp + sizeof(thread_t),
+                  CH_DBG_THREAD_FILL_VALUE);
+  _thread_memfill((uint8_t *)wsp + sizeof(thread_t),
+                  (uint8_t *)wsp + size,
+                  CH_DBG_STACK_FILL_VALUE);
+#endif
+  chSysLock();
+  chSchWakeupS(tp = chThdCreateI(wsp, size, prio, pf, arg), MSG_OK);
+  chSysUnlock();
+  return tp;
+}
+
+/**
+ * @brief   Resumes a thread created with @p chThdCreateI().
+ *
+ * @param[in] tp        pointer to the thread
+ *
+ * @api
+ */
+thread_t *chThdStart(thread_t *tp) {
+
+  chSysLock();
+  tp = chThdStartI(tp);
+  chSysUnlock();
+  return tp;
+}
+
+/**
+ * @brief   Changes the running thread priority level then reschedules if
+ *          necessary.
+ * @note    The function returns the real thread priority regardless of the
+ *          current priority that could be higher than the real priority
+ *          because the priority inheritance mechanism.
+ *
+ * @param[in] newprio   the new priority level of the running thread
+ * @return              The old priority level.
+ *
+ * @api
+ */
+tprio_t chThdSetPriority(tprio_t newprio) {
+  tprio_t oldprio;
+
+  chDbgCheck(newprio <= HIGHPRIO);
+
+  chSysLock();
+#if CH_CFG_USE_MUTEXES
+  oldprio = currp->p_realprio;
+  if ((currp->p_prio == currp->p_realprio) || (newprio > currp->p_prio))
+    currp->p_prio = newprio;
+  currp->p_realprio = newprio;
+#else
+  oldprio = currp->p_prio;
+  currp->p_prio = newprio;
+#endif
+  chSchRescheduleS();
+  chSysUnlock();
+  return oldprio;
+}
+
+/**
+ * @brief   Requests a thread termination.
+ * @pre     The target thread must be written to invoke periodically
+ *          @p chThdShouldTerminate() and terminate cleanly if it returns
+ *          @p true.
+ * @post    The specified thread will terminate after detecting the termination
+ *          condition.
+ *
+ * @param[in] tp        pointer to the thread
+ *
+ * @api
+ */
+void chThdTerminate(thread_t *tp) {
+
+  chSysLock();
+  tp->p_flags |= CH_FLAG_TERMINATE;
+  chSysUnlock();
+}
+
+/**
+ * @brief   Suspends the invoking thread for the specified time.
+ *
+ * @param[in] time      the delay in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ *
+ * @api
+ */
+void chThdSleep(systime_t time) {
+
+  chSysLock();
+  chThdSleepS(time);
+  chSysUnlock();
+}
+
+/**
+ * @brief   Suspends the invoking thread until the system time arrives to the
+ *          specified value.
+ *
+ * @param[in] time      absolute system time
+ *
+ * @api
+ */
+void chThdSleepUntil(systime_t time) {
+
+  chSysLock();
+  if ((time -= chVTGetSystemTimeX()) > 0)
+    chThdSleepS(time);
+  chSysUnlock();
+}
+
+/**
+ * @brief   Yields the time slot.
+ * @details Yields the CPU control to the next thread in the ready list with
+ *          equal priority, if any.
+ *
+ * @api
+ */
+void chThdYield(void) {
+
+  chSysLock();
+  chSchDoYieldS();
+  chSysUnlock();
+}
+
+/**
+ * @brief   Terminates the current thread.
+ * @details The thread goes in the @p CH_STATE_FINAL state holding the
+ *          specified exit status code, other threads can retrieve the
+ *          exit status code by invoking the function @p chThdWait().
+ * @post    Eventual code after this function will never be executed,
+ *          this function never returns. The compiler has no way to
+ *          know this so do not assume that the compiler would remove
+ *          the dead code.
+ *
+ * @param[in] msg       thread exit code
+ *
+ * @api
+ */
+void chThdExit(msg_t msg) {
+
+  chSysLock();
+  chThdExitS(msg);
+  /* The thread never returns here.*/
+}
+
+/**
+ * @brief   Terminates the current thread.
+ * @details The thread goes in the @p CH_STATE_FINAL state holding the
+ *          specified exit status code, other threads can retrieve the
+ *          exit status code by invoking the function @p chThdWait().
+ * @post    Eventual code after this function will never be executed,
+ *          this function never returns. The compiler has no way to
+ *          know this so do not assume that the compiler would remove
+ *          the dead code.
+ *
+ * @param[in] msg       thread exit code
+ *
+ * @sclass
+ */
+void chThdExitS(msg_t msg) {
+  thread_t *tp = currp;
+
+  tp->p_u.exitcode = msg;
+#if defined(CH_CFG_THREAD_EXIT_HOOK)
+  CH_CFG_THREAD_EXIT_HOOK(tp);
+#endif
+#if CH_CFG_USE_WAITEXIT
+  while (list_notempty(&tp->p_waiting))
+    chSchReadyI(list_remove(&tp->p_waiting));
+#endif
+#if CH_CFG_USE_REGISTRY
+  /* Static threads are immediately removed from the registry because
+     there is no memory to recover.*/
+  if ((tp->p_flags & CH_FLAG_MODE_MASK) == CH_FLAG_MODE_STATIC)
+    REG_REMOVE(tp);
+#endif
+  chSchGoSleepS(CH_STATE_FINAL);
+  /* The thread never returns here.*/
+  chDbgAssert(false, "zombies apocalypse");
+}
+
+#if CH_CFG_USE_WAITEXIT || defined(__DOXYGEN__)
+/**
+ * @brief   Blocks the execution of the invoking thread until the specified
+ *          thread terminates then the exit code is returned.
+ * @details This function waits for the specified thread to terminate then
+ *          decrements its reference counter, if the counter reaches zero then
+ *          the thread working area is returned to the proper allocator.<br>
+ *          The memory used by the exited thread is handled in different ways
+ *          depending on the API that spawned the thread:
+ *          - If the thread was spawned by @p chThdCreateStatic() or by
+ *            @p chThdCreateI() then nothing happens and the thread working
+ *            area is not released or modified in any way. This is the
+ *            default, totally static, behavior.
+ *          - If the thread was spawned by @p chThdCreateFromHeap() then
+ *            the working area is returned to the system heap.
+ *          - If the thread was spawned by @p chThdCreateFromMemoryPool()
+ *            then the working area is returned to the owning memory pool.
+ *          .
+ * @pre     The configuration option @p CH_CFG_USE_WAITEXIT must be enabled in
+ *          order to use this function.
+ * @post    Enabling @p chThdWait() requires 2-4 (depending on the
+ *          architecture) extra bytes in the @p thread_t structure.
+ * @post    After invoking @p chThdWait() the thread pointer becomes invalid
+ *          and must not be used as parameter for further system calls.
+ * @note    If @p CH_CFG_USE_DYNAMIC is not specified this function just waits for
+ *          the thread termination, no memory allocators are involved.
+ *
+ * @param[in] tp        pointer to the thread
+ * @return              The exit code from the terminated thread.
+ *
+ * @api
+ */
+msg_t chThdWait(thread_t *tp) {
+  msg_t msg;
+
+  chDbgCheck(tp != NULL);
+
+  chSysLock();
+  chDbgAssert(tp != currp, "waiting self");
+#if CH_CFG_USE_DYNAMIC
+  chDbgAssert(tp->p_refs > 0, "not referenced");
+#endif
+  if (tp->p_state != CH_STATE_FINAL) {
+    list_insert(currp, &tp->p_waiting);
+    chSchGoSleepS(CH_STATE_WTEXIT);
+  }
+  msg = tp->p_u.exitcode;
+  chSysUnlock();
+#if CH_CFG_USE_DYNAMIC
+  chThdRelease(tp);
+#endif
+  return msg;
+}
+#endif /* CH_CFG_USE_WAITEXIT */
+
+/**
+ * @brief   Sends the current thread sleeping and sets a reference variable.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @return              The wake up message.
+ *
+ * @sclass
+ */
+msg_t chThdSuspendS(thread_reference_t *trp) {
+  thread_t *tp = chThdGetSelfX();
+
+  chDbgAssert(*trp == NULL, "not NULL");
+
+  *trp = tp;
+  tp->p_u.wtobjp = &trp;
+  chSchGoSleepS(CH_STATE_SUSPENDED);
+  return chThdGetSelfX()->p_msg;
+}
+
+/**
+ * @brief   Sends the current thread sleeping and sets a reference variable.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] timeout   the timeout in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state.
+ *                      - @a TIME_IMMEDIATE the thread is not enqueued and
+ *                        the function returns @p MSG_TIMEOUT as if a timeout
+ *                        occurred.
+ *                      .
+ * @return              The wake up message.
+ * @retval MSG_TIMEOUT  if the operation timed out.
+ *
+ * @sclass
+ */
+msg_t chThdSuspendTimeoutS(thread_reference_t *trp, systime_t timeout) {
+  thread_t *tp = chThdGetSelfX();
+
+  chDbgAssert(*trp == NULL, "not NULL");
+
+  if (TIME_IMMEDIATE == timeout)
+    return MSG_TIMEOUT;
+
+  *trp = tp;
+  tp->p_u.wtobjp = &trp;
+  return chSchGoSleepTimeoutS(CH_STATE_SUSPENDED, timeout);
+}
+
+/**
+ * @brief   Wakes up a thread waiting on a thread reference object.
+ * @note    This function must not reschedule because it can be called from
+ *          ISR context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+void chThdResumeI(thread_reference_t *trp, msg_t msg) {
+
+  if (*trp != NULL) {
+    thread_t *tp = *trp;
+
+    chDbgAssert(tp->p_state == CH_STATE_SUSPENDED,
+                "not THD_STATE_SUSPENDED");
+
+    *trp = NULL;
+    tp->p_u.rdymsg = msg;
+    chSchReadyI(tp);
+  }
+}
+
+/**
+ * @brief   Wakes up a thread waiting on a thread reference object.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+void chThdResumeS(thread_reference_t *trp, msg_t msg) {
+
+  if (*trp != NULL) {
+    thread_t *tp = *trp;
+
+    chDbgAssert(tp->p_state == CH_STATE_SUSPENDED,
+                "not THD_STATE_SUSPENDED");
+
+    *trp = NULL;
+    chSchWakeupS(tp, msg);
+  }
+}
+
+/**
+ * @brief   Wakes up a thread waiting on a thread reference object.
+ * @note    This function must reschedule, it can only be called from thread
+ *          context.
+ *
+ * @param[in] trp       a pointer to a thread reference object
+ * @param[in] msg       the message code
+ *
+ * @api
+ */
+void chThdResume(thread_reference_t *trp, msg_t msg) {
+
+  chSysLock();
+  chThdResumeS(trp, msg);
+  chSysUnlock();
+}
+
+/**
+ * @brief   Enqueues the caller thread on a threads queue object.
+ * @details The caller thread is enqueued and put to sleep until it is
+ *          dequeued or the specified timeouts expires.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] timeout   the timeout in system ticks, the special values are
+ *                      handled as follow:
+ *                      - @a TIME_INFINITE the thread enters an infinite sleep
+ *                        state.
+ *                      - @a TIME_IMMEDIATE the thread is not enqueued and
+ *                        the function returns @p MSG_TIMEOUT as if a timeout
+ *                        occurred.
+ *                      .
+ * @return              The message from @p osalQueueWakeupOneI() or
+ *                      @p osalQueueWakeupAllI() functions.
+ * @retval MSG_TIMEOUT  if the thread has not been dequeued within the
+ *                      specified timeout or if the function has been
+ *                      invoked with @p TIME_IMMEDIATE as timeout
+ *                      specification.
+ *
+ * @sclass
+ */
+msg_t chThdEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) {
+
+  if (TIME_IMMEDIATE == timeout)
+    return MSG_TIMEOUT;
+
+  queue_insert(currp, tqp);
+  return chSchGoSleepTimeoutS(CH_STATE_QUEUED, timeout);
+}
+
+/**
+ * @brief   Dequeues and wakes up one thread from the threads queue object,
+ *          if any.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+void chThdDequeueNextI(threads_queue_t *tqp, msg_t msg) {
+
+  if (queue_notempty(tqp)) {
+    thread_t *tp = queue_fifo_remove(tqp);
+
+    chDbgAssert(tp->p_state == CH_STATE_QUEUED,
+                "not CH_STATE_QUEUED");
+
+    tp->p_u.rdymsg = msg;
+    chSchReadyI(tp);
+  }
+}
+
+/**
+ * @brief   Dequeues and wakes up all threads from the threads queue object.
+ *
+ * @param[in] tqp       pointer to the threads queue object
+ * @param[in] msg       the message code
+ *
+ * @iclass
+ */
+void chThdDequeueAllI(threads_queue_t *tqp, msg_t msg) {
+
+  while (queue_notempty(tqp)) {
+    thread_t *tp = queue_fifo_remove(tqp);
+
+    chDbgAssert(tp->p_state == CH_STATE_QUEUED,
+                "not CH_STATE_QUEUED");
+
+    tp->p_u.rdymsg = msg;
+    chSchReadyI(tp);
+  }
+}
+
+/** @} */
diff --git a/os/rt/src/chtm.c b/os/rt/src/chtm.c
new file mode 100644
index 000000000..c001dd7e3
--- /dev/null
+++ b/os/rt/src/chtm.c
@@ -0,0 +1,155 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chtm.c
+ * @brief   Time Measurement module code.
+ *
+ * @addtogroup time_measurement
+ * @details Time Measurement APIs and services.
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_TM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+static inline void tm_stop(time_measurement_t *tmp,
+                           rtcnt_t now,
+                           rtcnt_t offset) {
+
+  tmp->n++;
+  tmp->last = now - tmp->last - offset;
+  tmp->cumulative += (rttime_t)tmp->last;
+  if (tmp->last > tmp->worst)
+    tmp->worst = tmp->last;
+  else if (tmp->last < tmp->best)
+    tmp->best = tmp->last;
+}
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the time measurement unit.
+ *
+ * @init
+ */
+void _tm_init(void) {
+  time_measurement_t tm;
+
+  /* Time Measurement subsystem calibration, it does a null measurement
+     and calculates the call overhead which is subtracted to real
+     measurements.*/
+  ch.measurement_offset = 0;
+  chTMObjectInit(&tm);
+  chTMStartMeasurementX(&tm);
+  chTMStopMeasurementX(&tm);
+  ch.measurement_offset = tm.last;
+}
+
+/**
+ * @brief   Initializes a @p TimeMeasurement object.
+ *
+ * @param[out] tmp      pointer to a @p TimeMeasurement structure
+ *
+ * @init
+ */
+void chTMObjectInit(time_measurement_t *tmp) {
+
+  tmp->best       = (rtcnt_t)-1;
+  tmp->worst      = (rtcnt_t)0;
+  tmp->last       = (rtcnt_t)0;
+  tmp->n          = (ucnt_t)0;
+  tmp->cumulative = (rttime_t)0;
+}
+
+/**
+ * @brief   Starts a measurement.
+ * @pre     The @p time_measurement_t structure must be initialized.
+ *
+ * @param[in,out] tmp   pointer to a @p TimeMeasurement structure
+ *
+ * @xclass
+ */
+NOINLINE void chTMStartMeasurementX(time_measurement_t *tmp) {
+
+  tmp->last = chSysGetRealtimeCounterX();
+}
+
+/**
+ * @brief   Stops a measurement.
+ * @pre     The @p time_measurement_t structure must be initialized.
+ *
+ * @param[in,out] tmp   pointer to a @p time_measurement_t structure
+ *
+ * @xclass
+ */
+NOINLINE void chTMStopMeasurementX(time_measurement_t *tmp) {
+
+  tm_stop(tmp, chSysGetRealtimeCounterX(), ch.measurement_offset);
+}
+
+/**
+ * @brief   Stops a measurement and chains to the next one using the same time
+ *          stamp.
+ *
+ * @param[in,out] tmp1  pointer to the @p time_measurement_t structure to be
+ *                      stopped
+ * @param[in,out] tmp2  pointer to the @p time_measurement_t structure to be
+ *                      started
+ *
+ *
+ * @xclass
+ */
+NOINLINE void chTMChainMeasurementToX(time_measurement_t *tmp1,
+                                      time_measurement_t *tmp2) {
+
+  /* Starts new measurement.*/
+  tmp2->last = chSysGetRealtimeCounterX();
+
+  /* Stops previous measurement using the same time stamp.*/
+  tm_stop(tmp1, tmp2->last, 0);
+}
+
+#endif /* CH_CFG_USE_TM */
+
+/** @} */
diff --git a/os/rt/src/chvt.c b/os/rt/src/chvt.c
new file mode 100644
index 000000000..d20e20d91
--- /dev/null
+++ b/os/rt/src/chvt.c
@@ -0,0 +1,191 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chvt.c
+ * @brief   Time and Virtual Timers module code.
+ *
+ * @addtogroup time
+ * @details Time and Virtual Timers related APIs and services.
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Virtual Timers initialization.
+ * @note    Internal use only.
+ *
+ * @notapi
+ */
+void _vt_init(void) {
+
+  ch.vtlist.vt_next = ch.vtlist.vt_prev = (void *)&ch.vtlist;
+  ch.vtlist.vt_delta = (systime_t)-1;
+#if CH_CFG_ST_TIMEDELTA == 0
+  ch.vtlist.vt_systime = 0;
+#else /* CH_CFG_ST_TIMEDELTA > 0 */
+  ch.vtlist.vt_lasttime = 0;
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+}
+
+/**
+ * @brief   Enables a virtual timer.
+ * @details The timer is enabled and programmed to trigger after the delay
+ *          specified as parameter.
+ * @pre     The timer must not be already armed before calling this function.
+ * @note    The callback function is invoked from interrupt context.
+ *
+ * @param[out] vtp      the @p virtual_timer_t structure pointer
+ * @param[in] delay     the number of ticks before the operation timeouts, the
+ *                      special values are handled as follow:
+ *                      - @a TIME_INFINITE is allowed but interpreted as a
+ *                        normal time specification.
+ *                      - @a TIME_IMMEDIATE this value is not allowed.
+ *                      .
+ * @param[in] vtfunc    the timer callback function. After invoking the
+ *                      callback the timer is disabled and the structure can
+ *                      be disposed or reused.
+ * @param[in] par       a parameter that will be passed to the callback
+ *                      function
+ *
+ * @iclass
+ */
+void chVTDoSetI(virtual_timer_t *vtp, systime_t delay,
+                vtfunc_t vtfunc, void *par) {
+  virtual_timer_t *p;
+
+  chDbgCheckClassI();
+  chDbgCheck((vtp != NULL) && (vtfunc != NULL) && (delay != TIME_IMMEDIATE));
+
+  vtp->vt_par = par;
+  vtp->vt_func = vtfunc;
+  p = ch.vtlist.vt_next;
+
+#if CH_CFG_ST_TIMEDELTA > 0 || defined(__DOXYGEN__)
+  {
+    systime_t now = port_timer_get_time();
+
+    /* If the requested delay is lower than the minimum safe delta then it
+       is raised to the minimum safe value.*/
+    if (delay < CH_CFG_ST_TIMEDELTA)
+      delay = CH_CFG_ST_TIMEDELTA;
+
+    if (&ch.vtlist == (virtual_timers_list_t *)p) {
+      /* The delta list is empty, the current time becomes the new
+         delta list base time.*/
+      ch.vtlist.vt_lasttime = now;
+      port_timer_start_alarm(ch.vtlist.vt_lasttime + delay);
+    }
+    else {
+      /* Now the delay is calculated as delta from the last tick interrupt
+         time.*/
+      delay += now - ch.vtlist.vt_lasttime;
+
+      /* If the specified delay is closer in time than the first element
+         in the delta list then it becomes the next alarm event in time.*/
+      if (delay < p->vt_delta)
+        port_timer_set_alarm(ch.vtlist.vt_lasttime + delay);
+    }
+  }
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+
+  /* The delta list is scanned in order to find the correct position for
+     this timer. */
+  while (p->vt_delta < delay) {
+    delay -= p->vt_delta;
+    p = p->vt_next;
+  }
+
+  /* The timer is inserted in the delta list.*/
+  vtp->vt_prev = (vtp->vt_next = p)->vt_prev;
+  vtp->vt_prev->vt_next = p->vt_prev = vtp;
+  vtp->vt_delta = delay
+
+  /* Special case when the timer is in last position in the list, the
+     value in the header must be restored.*/;
+  p->vt_delta -= delay;
+  ch.vtlist.vt_delta = (systime_t)-1;
+}
+
+/**
+ * @brief   Disables a Virtual Timer.
+ * @pre     The timer must be in armed state before calling this function.
+ *
+ * @param[in] vtp       the @p virtual_timer_t structure pointer
+ *
+ * @iclass
+ */
+void chVTDoResetI(virtual_timer_t *vtp) {
+
+  chDbgCheckClassI();
+  chDbgCheck(vtp != NULL);
+  chDbgAssert(vtp->vt_func != NULL, "timer not set or already triggered");
+
+  /* Removing the element from the delta list.*/
+  vtp->vt_next->vt_delta += vtp->vt_delta;
+  vtp->vt_prev->vt_next = vtp->vt_next;
+  vtp->vt_next->vt_prev = vtp->vt_prev;
+  vtp->vt_func = (vtfunc_t)NULL;
+
+  /* The above code changes the value in the header when the removed element
+     is the last of the list, restoring it.*/
+  ch.vtlist.vt_delta = (systime_t)-1;
+
+#if CH_CFG_ST_TIMEDELTA > 0 || defined(__DOXYGEN__)
+  {
+    if (&ch.vtlist == (virtual_timers_list_t *)ch.vtlist.vt_next) {
+      /* Just removed the last element in the list, alarm timer stopped.*/
+      port_timer_stop_alarm();
+    }
+    else {
+      /* The alarm is set to the next element in the delta list.*/
+      port_timer_set_alarm(ch.vtlist.vt_lasttime +
+                           ch.vtlist.vt_next->vt_delta);
+    }
+  }
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+}
+
+/** @} */
diff --git a/os/rt/templates/chconf.h b/os/rt/templates/chconf.h
new file mode 100644
index 000000000..09b91db5c
--- /dev/null
+++ b/os/rt/templates/chconf.h
@@ -0,0 +1,497 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    templates/chconf.h
+ * @brief   Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ *          contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   System time counter resolution.
+ * @note    Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION                32
+
+/**
+ * @brief   System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ *          setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY                 10000
+
+/**
+ * @brief   Time delta constant for the tick-less mode.
+ * @note    If this value is zero then the system uses the classic
+ *          periodic tick. This value represents the minimum number
+ *          of ticks that is safe to specify in a timeout directive.
+ *          The value one is not valid, timeouts are rounded up to
+ *          this value.
+ */
+#define CH_CFG_ST_TIMEDELTA                 2
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ *          threads before preemption occurs. Setting this value to zero
+ *          disables the preemption for threads with equal priority and the
+ *          round robin becomes cooperative. Note that higher priority
+ *          threads can still preempt, the kernel is always preemptive.
+ * @note    Disabling the round robin preemption makes the kernel more compact
+ *          and generally faster.
+ * @note    The round robin preemption is not supported in tickless mode and
+ *          must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM                 0
+
+/**
+ * @brief   Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ *          then the whole available RAM is used. The core memory is made
+ *          available to the heap allocator and/or can be used directly through
+ *          the simplified core memory allocator.
+ *
+ * @note    In order to let the OS manage the whole RAM the linker script must
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note    Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE                 0
+
+/**
+ * @brief   Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ *          does not spawn the idle thread. The application @p main()
+ *          function becomes the idle thread and must implement an
+ *          infinite loop. */
+#define CH_CFG_NO_IDLE_THREAD               FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ *          is used when two possible implementations exist.
+ *
+ * @note    This is not related to the compiler optimization options.
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED               TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM                       TRUE
+
+/**
+ * @brief   Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY                 TRUE
+
+/**
+ * @brief   Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT                 TRUE
+
+/**
+ * @brief   Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES               TRUE
+
+/**
+ * @brief   Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ *          priority rather than in FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special
+ *          requirements.
+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE
+
+/**
+ * @brief   Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES                  TRUE
+
+/**
+ * @brief   Enables recursive behavior on mutexes.
+ * @note    Recursive mutexes are heavier and have an increased
+ *          memory footprint.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE
+
+/**
+ * @brief   Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS                 TRUE
+
+/**
+ * @brief   Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ *          specification are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS                   TRUE
+
+/**
+ * @brief   Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ *          are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE
+
+/**
+ * @brief   Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES                 TRUE
+
+/**
+ * @brief   Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ *          FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special
+ *          requirements.
+ * @note    Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE
+
+/**
+ * @brief   Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ *          included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES                TRUE
+
+/**
+ * @brief   I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES                   TRUE
+
+/**
+ * @brief   Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE                  TRUE
+
+/**
+ * @brief   Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ *          @p CH_CFG_USE_SEMAPHORES.
+ * @note    Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP                     TRUE
+
+/**
+ * @brief   Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS                 TRUE
+
+/**
+ * @brief   Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_WAITEXIT.
+ * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC                  TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Debug option, kernel statistics.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS                   FALSE
+
+/**
+ * @brief   Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ *          at runtime.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK           FALSE
+
+/**
+ * @brief   Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ *          parameters are activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS                FALSE
+
+/**
+ * @brief   Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ *          activated. This includes consistency checks inside the kernel,
+ *          runtime anomalies and port-defined checks.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS               FALSE
+
+/**
+ * @brief   Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ *          activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE                 FALSE
+
+/**
+ * @brief   Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note    The default is @p FALSE.
+ * @note    The stack check is performed in a architecture/port dependent way.
+ *          It may not be implemented or some ports.
+ * @note    The default failure mode is to halt the system with the global
+ *          @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK           FALSE
+
+/**
+ * @brief   Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ *          value when a thread is created. This can be useful for the
+ *          runtime measurement of the used stack.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS                 FALSE
+
+/**
+ * @brief   Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ *          counts the system ticks occurred while executing the thread.
+ *
+ * @note    The default is @p FALSE.
+ * @note    This debug option is not currently compatible with the
+ *          tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING            FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS                                          \
+  /* Add threads custom fields here.*/
+
+/**
+ * @brief   Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
+ *          the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \
+  /* Add threads initialization code here.*/                                \
+}
+
+/**
+ * @brief   Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note    It is inserted into lock zone.
+ * @note    It is also invoked when the threads simply return in order to
+ *          terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \
+  /* Add threads finalization code here.*/                                  \
+}
+
+/**
+ * @brief   Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
+  /* System halt code here.*/                                               \
+}
+
+/**
+ * @brief   Idle thread enter hook.
+ * @note    This hook is invoked within a critical zone, no OS functions
+ *          should be invoked from here.
+ * @note    This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() {                                         \
+}
+
+/**
+ * @brief   Idle thread leave hook.
+ * @note    This hook is invoked within a critical zone, no OS functions
+ *          should be invoked from here.
+ * @note    This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() {                                         \
+}
+
+/**
+ * @brief   Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() {                                           \
+  /* Idle loop code here.*/                                                 \
+}
+
+/**
+ * @brief   System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ *          after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \
+  /* System tick event code here.*/                                         \
+}
+
+/**
+ * @brief   System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ *          the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \
+  /* System halt code here.*/                                               \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
+/*===========================================================================*/
+
+#endif  /* _CHCONF_H_ */
+
+/** @} */
diff --git a/os/rt/templates/chcore.c b/os/rt/templates/chcore.c
new file mode 100644
index 000000000..1f7db903c
--- /dev/null
+++ b/os/rt/templates/chcore.c
@@ -0,0 +1,134 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/chcore.c
+ * @brief   Port related template code.
+ * @details This file is a template of the system driver functions provided by
+ *          a port. Some of the following functions may be implemented as
+ *          macros in chcore.h if the implementer decides that there is an
+ *          advantage in doing so, for example because performance concerns.
+ *
+ * @addtogroup core
+ * @details Non portable code templates.
+ * @{
+ */
+
+#include "ch.h"
+
+/**
+ * @brief   Port-related initialization code.
+ * @note    This function is usually empty.
+ */
+void port_init(void) {
+}
+
+/**
+ * @brief   Kernel-lock action.
+ * @details Usually this function just disables interrupts but may perform more
+ *          actions.
+ */
+void port_lock(void) {
+}
+
+/**
+ * @brief   Kernel-unlock action.
+ * @details Usually this function just enables interrupts but may perform more
+ *          actions.
+ */
+void port_unlock(void) {
+}
+
+/**
+ * @brief   Kernel-lock action from an interrupt handler.
+ * @details This function is invoked before invoking I-class APIs from
+ *          interrupt handlers. The implementation is architecture dependent,
+ *          in its simplest form it is void.
+ */
+void port_lock_from_isr(void) {
+}
+
+/**
+ * @brief   Kernel-unlock action from an interrupt handler.
+ * @details This function is invoked after invoking I-class APIs from interrupt
+ *          handlers. The implementation is architecture dependent, in its
+ *          simplest form it is void.
+ */
+void port_unlock_from_isr(void) {
+}
+
+/**
+ * @brief   Disables all the interrupt sources.
+ * @note    Of course non-maskable interrupt sources are not included.
+ */
+void port_disable(void) {
+}
+
+/**
+ * @brief   Disables the interrupt sources below kernel-level priority.
+ * @note    Interrupt sources above kernel level remains enabled.
+ */
+void port_suspend(void) {
+}
+
+/**
+ * @brief   Enables all the interrupt sources.
+ */
+void port_enable(void) {
+}
+
+/**
+ * @brief   Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ *          The simplest implementation is an empty function or macro but this
+ *          would not take advantage of architecture-specific power saving
+ *          modes.
+ */
+void port_wait_for_interrupt(void) {
+}
+
+/**
+ * @brief   Halts the system.
+ * @details This function is invoked by the operating system when an
+ *          unrecoverable error is detected (for example because a programming
+ *          error in the application code that triggers an assertion while in
+ *          debug mode).
+ */
+void port_halt(void) {
+
+  port_disable();
+  while (TRUE) {
+  }
+}
+
+/**
+ * @brief   Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ *          is responsible for the context switch between 2 threads.
+ * @note    The implementation of this code affects <b>directly</b> the context
+ *          switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp       the thread to be switched in
+ * @param[in] otp       the thread to be switched out
+ */
+void port_switch(thread_t *ntp, thread_t *otp) {
+}
+
+/** @} */
diff --git a/os/rt/templates/chcore.h b/os/rt/templates/chcore.h
new file mode 100644
index 000000000..c993c724e
--- /dev/null
+++ b/os/rt/templates/chcore.h
@@ -0,0 +1,213 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/chcore.h
+ * @brief   Port related template macros and structures.
+ * @details This file is a template of the system driver macros provided by
+ *          a port.
+ *
+ * @addtogroup core
+ * @{
+ */
+
+#ifndef _CHCORE_H_
+#define _CHCORE_H_
+
+/*===========================================================================*/
+/* Port constants.                                                           */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port macros.                                                              */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port configurable parameters.                                             */
+/*===========================================================================*/
+
+/**
+ * @brief   Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ *          the idle thread should take no more space than those reserved
+ *          by @p PORT_INT_REQUIRED_STACK.
+ */
+#ifndef PORT_IDLE_THREAD_STACK_SIZE
+#define PORT_IDLE_THREAD_STACK_SIZE     0
+#endif
+
+/**
+ * @brief   Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ *          area size.
+ *          This value can be zero on those architecture where there is a
+ *          separate interrupt stack and the stack space between @p intctx and
+ *          @p extctx is known to be zero.
+ */
+#ifndef PORT_INT_REQUIRED_STACK
+#define PORT_INT_REQUIRED_STACK         0
+#endif
+
+/*===========================================================================*/
+/* Port derived parameters.                                                  */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port exported info.                                                       */
+/*===========================================================================*/
+
+/**
+ * @brief   Unique macro for the implemented architecture.
+ */
+#define CH_ARCHITECTURE_XXX
+
+/**
+ * @brief   Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME            ""
+
+/**
+ * @brief   Name of the architecture variant (optional).
+ */
+#define CH_ARCHITECTURE_VARIANT_NAME    ""
+
+/**
+ * @brief   Name of the compiler supported by this port.
+ */
+#define CH_COMPILER_NAME                "GCC"
+
+/**
+ * @brief   Port-specific information string.
+ */
+#define CH_PORT_INFO                    ""
+
+/*===========================================================================*/
+/* Port implementation part.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Base type for stack and memory alignment.
+ */
+typedef uint8_t stkalign_t;
+
+/**
+ * @brief   Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ *          preemption-capable interrupt handler.
+ */
+struct extctx {
+};
+
+/**
+ * @brief   System saved context.
+ * @details This structure represents the inner stack frame during a context
+ *          switching.
+ */
+struct intctx {
+};
+
+/**
+ * @brief   Platform dependent part of the @p thread_t structure.
+ * @details This structure usually contains just the saved stack pointer
+ *          defined as a pointer to a @p intctx structure.
+ */
+struct context {
+  struct intctx *sp;
+};
+
+/**
+ * @brief   Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ *          by an @p intctx structure.
+ */
+#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
+}
+
+/**
+ * @brief   Enforces a correct alignment for a stack area size value.
+ */
+#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
+
+/**
+ * @brief   Computes the thread working area global size.
+ */
+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(thread_t) +                       \
+                                   sizeof(struct intctx) +                  \
+                                   sizeof(struct extctx) +                  \
+                                   (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief   Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ *          aligned as both position and size.
+ */
+#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
+
+/**
+ * @brief   IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief   IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ *          enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE()
+
+/**
+ * @brief   IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) void id(void)
+
+/**
+ * @brief   Fast IRQ handler function declaration.
+ * @note    @p id can be a function name or a vector number depending on the
+ *          port implementation.
+ * @note    Not all architectures support fast interrupts, in this case this
+ *          macro must be omitted.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) void id(void)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void port_init(void);
+  void port_lock(void);
+  void port_unlock(void);
+  void port_lock_from_isr(void);
+  void port_unlock_from_isr(void);
+  void port_disable(void);
+  void port_suspend(void);
+  void port_enable(void);
+  void port_wait_for_interrupt(void);
+  void port_halt(void);
+  void port_switch(thread_t *ntp, thread_t *otp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CHCORE_H_ */
+
+/** @} */
diff --git a/os/rt/templates/chtypes.h b/os/rt/templates/chtypes.h
new file mode 100644
index 000000000..d13e837c4
--- /dev/null
+++ b/os/rt/templates/chtypes.h
@@ -0,0 +1,97 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/chtypes.h
+ * @brief   System types template.
+ * @details The types defined in this file may change depending on the target
+ *          architecture. You may also try to optimize the size of the various
+ *          types in order to privilege size or performance, be careful in
+ *          doing so.
+ *
+ * @addtogroup types
+ * @details System types and macros.
+ * @{
+ */
+
+#ifndef _CHTYPES_H_
+#define _CHTYPES_H_
+
+#define __need_NULL
+#define __need_size_t
+#include <stddef.h>
+
+#if !defined(_STDINT_H) && !defined(__STDINT_H_)
+#include <stdint.h>
+#endif
+
+/**
+ * @brief   Thread mode flags, uint8_t is ok.
+ */
+typedef uint8_t         tmode_t;
+
+/**
+ * @brief   Thread state, uint8_t is ok.
+ */
+typedef uint8_t         tstate_t;
+
+/**
+ * @brief   Thread references counter, uint8_t is ok.
+ */
+typedef uint8_t         trefs_t;
+
+/**
+ * @brief   Priority, use the fastest unsigned type.
+ */
+typedef uint32_t        tprio_t;
+
+/**
+ * @brief   Message, use signed pointer equivalent.
+ */
+typedef int32_t         msg_t;
+
+/**
+ * @brief   Numeric event identifier, use fastest signed.
+ */
+typedef int32_t         eventid_t;
+
+/**
+ * @brief   Mask of event identifiers, recommended fastest unsigned.
+ */
+typedef uint32_t        eventmask_t;
+
+/**
+ * @brief   Mask of event flags, recommended fastest unsigned.
+ */
+typedef uint32_t        eventflags_t;
+
+/**
+ * @brief   System Time, recommended fastest unsigned.
+ */
+typedef uint32_t        systime_t;
+
+/**
+ * @brief   Counter, recommended fastest signed.
+ */
+typedef int32_t         cnt_t;
+
+#endif /* _CHTYPES_H_ */
+
+/** @} */
diff --git a/os/rt/templates/module.c b/os/rt/templates/module.c
new file mode 100644
index 000000000..6a93bf4aa
--- /dev/null
+++ b/os/rt/templates/module.c
@@ -0,0 +1,81 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chXxx.c
+ * @brief   XXX module code.
+ *
+ * @addtogroup XXX
+ * @{
+ */
+
+#include "ch.h"
+
+#if CH_CFG_USE_XXX || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   XXX Module initialization.
+ * @note    This function is implicitly invoked on system initialization,
+ *          there is no need to explicitly initialize the module.
+ *
+ * @notapi
+ */
+void _xxx_init(void) {
+
+}
+
+/**
+ * @brief   Initializes a @p xxx_t object.
+ *
+ * @param[out] xxxp     pointer to the @p xxx_t object
+ *
+ * @init
+ */
+void chXxxObjectInit(xxx_t *xxxp) {
+
+}
+
+#endif /* CH_CFG_USE_XXX */
+
+/** @} */
diff --git a/os/rt/templates/module.h b/os/rt/templates/module.h
new file mode 100644
index 000000000..261311f84
--- /dev/null
+++ b/os/rt/templates/module.h
@@ -0,0 +1,77 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    chXxx.h
+ * @brief   XXX Module macros and structures.
+ *
+ * @addtogroup XXX
+ * @{
+ */
+
+#ifndef _CHXXX_H_
+#define _CHXXX_H_
+
+#include "ch.h"
+
+#if CH_CFG_USE_XXX || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void chXxxInit(void);
+  void chXxxObjectInit(xxx_t *xxxp);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
+#endif /* CH_CFG_USE_XXX */
+
+#endif /* _CHXXX_H_ */
+
+/** @} */
diff --git a/os/various/chprintf.c b/os/various/chprintf.c
index 8c709bc4f..78453f52b 100644
--- a/os/various/chprintf.c
+++ b/os/various/chprintf.c
@@ -112,7 +112,7 @@ static char *ftoa(char *p, double num) {
 void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
   char *p, *s, c, filler;
   int i, precision, width;
-  bool_t is_long, left_align;
+  bool is_long, left_align;
   long l;
 #if CHPRINTF_USE_FLOAT
   float f;
diff --git a/os/various/chprintf.h b/os/various/chprintf.h
index 3444f216f..591f98130 100644
--- a/os/various/chprintf.h
+++ b/os/various/chprintf.h
@@ -66,7 +66,7 @@ extern "C" {
  *
  * @api
  */
-static INLINE void chprintf(BaseSequentialStream *chp, const char *fmt, ...) {
+static inline void chprintf(BaseSequentialStream *chp, const char *fmt, ...) {
   va_list ap;
 
   va_start(ap, fmt);
diff --git a/os/various/chrtclib.c b/os/various/chrtclib.c
index 9d3f4eb0c..f8a6a86ff 100644
--- a/os/various/chrtclib.c
+++ b/os/various/chrtclib.c
@@ -33,15 +33,10 @@
 
 #include "chrtclib.h"
 
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
-#if (defined(STM32F4XX) || defined(STM32F2XX) || defined(STM32L1XX) ||        \
-     defined(STM32F30X) || defined(STM32F37X) ||                              \
-     defined(STM32F1XX) || defined(STM32F10X_MD) || defined(STM32F10X_LD) ||  \
-     defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(STM32F0XX) ||  \
-     defined(LPC122X) || defined(LPC17XX) || defined(__DOXYGEN__))
-#if STM32_RTC_IS_CALENDAR || LPC17xx_RTC_IS_CALENDAR
-
+#if (defined(STM32F4XX) || defined(STM32F2XX) || defined(STM32L1XX) || \
+     defined(STM32F30X) || defined(STM32F37X) || \
+     defined(STM32F1XX) || defined(STM32F10X_MD) || defined(STM32F10X_LD) || \
+     defined(STM32F10X_HD) || defined(LPC122X) || defined(__DOXYGEN__))
 #if STM32_RTC_IS_CALENDAR
 /**
  * @brief   Converts from STM32 BCD to canonicalized time format.
@@ -139,47 +134,6 @@ static void stm32_rtc_tm2bcd(struct tm *timp, RTCTime *timespec) {
   timespec->tv_time |= ((v / 10) << RTC_TR_ST_OFFSET) & RTC_TR_ST;
   timespec->tv_time |= (v % 10) << RTC_TR_SU_OFFSET;
 }
-#endif
-
-#if LPC17xx_RTC_IS_CALENDAR
-/**
- * @brief   Converts from LPC17xx RTC format to canonicalized time format.
- *
- * @param[out] timp     pointer to a @p tm structure as defined in time.h
- * @param[in] timespec  pointer to a @p RTCTime structure
- *
- * @notapi
- */
-static void lpc17xx_rtc_format2tm(struct tm *timp, RTCTime *timespec) {
-  timp->tm_sec  = timespec->sec;
-  timp->tm_min  = timespec->min;
-  timp->tm_hour = timespec->hour;
-  timp->tm_mday = timespec->dom;
-  timp->tm_mon  = timespec->month - 1;
-  timp->tm_year = timespec->year - 1900;
-  timp->tm_wday = timespec->dow;
-  timp->tm_yday = timespec->doy - 1;
-}
-
-/**
- * @brief   Converts from LPC17xx RTC format to canonicalized time format.
- *
- * @param[out] timp     pointer to a @p tm structure as defined in time.h
- * @param[in] timespec  pointer to a @p RTCTime structure
- *
- * @notapi
- */
-static void lpc17xx_rtc_tm2format(struct tm *timp, RTCTime *timespec) {
-  timespec->sec   = timp->tm_sec;
-  timespec->min   = timp->tm_min;
-  timespec->hour  = timp->tm_hour;
-  timespec->dom   = timp->tm_mday;
-  timespec->month = timp->tm_mon + 1;
-  timespec->year  = timp->tm_year + 1900;
-  timespec->dow   = timp->tm_wday;
-  timespec->doy   = timp->tm_yday + 1;
-}
-#endif
 
 /**
  * @brief   Gets raw time from RTC and converts it to canonicalized format.
@@ -190,7 +144,6 @@ static void lpc17xx_rtc_tm2format(struct tm *timp, RTCTime *timespec) {
  * @api
  */
 void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) {
-#if STM32_RTC_IS_CALENDAR
 #if STM32_RTC_HAS_SUBSECONDS
   RTCTime timespec = {0,0,FALSE,0};
 #else
@@ -199,14 +152,6 @@ void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) {
 
   rtcGetTime(rtcp, &timespec);
   stm32_rtc_bcd2tm(timp, &timespec);
-#endif
-
-#if LPC17xx_RTC_IS_CALENDAR
-  RTCTime timespec;
-
-  rtcGetTime(rtcp, &timespec);
-  lpc17xx_rtc_format2tm(timp, &timespec);
-#endif
 }
 
 /**
@@ -218,7 +163,6 @@ void rtcGetTimeTm(RTCDriver *rtcp, struct tm *timp) {
  * @api
  */
 void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp) {
-#if STM32_RTC_IS_CALENDAR
 #if STM32_RTC_HAS_SUBSECONDS
   RTCTime timespec = {0,0,FALSE,0};
 #else
@@ -227,14 +171,6 @@ void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp) {
 
   stm32_rtc_tm2bcd(timp, &timespec);
   rtcSetTime(rtcp, &timespec);
-#endif
-
-#if LPC17xx_RTC_IS_CALENDAR
-  RTCTime timespec;
-
-  lpc17xx_rtc_tm2format(timp, &timespec);
-  rtcSetTime(rtcp, &timespec);
-#endif
 }
 
 /**
@@ -246,7 +182,6 @@ void rtcSetTimeTm(RTCDriver *rtcp, struct tm *timp) {
  * @api
  */
 time_t rtcGetTimeUnixSec(RTCDriver *rtcp) {
-#if STM32_RTC_IS_CALENDAR
 #if STM32_RTC_HAS_SUBSECONDS
   RTCTime timespec = {0,0,FALSE,0};
 #else
@@ -258,16 +193,6 @@ time_t rtcGetTimeUnixSec(RTCDriver *rtcp) {
   stm32_rtc_bcd2tm(&timp, &timespec);
 
   return mktime(&timp);
-#endif
-
-#if LPC17xx_RTC_IS_CALENDAR
-  RTCTime timespec;
-  struct tm timp;
-
-  rtcGetTime(rtcp, &timespec);
-  lpc17xx_rtc_format2tm(&timp, &timespec);
-  return mktime(&timp);
-#endif
 }
 
 /**
@@ -280,7 +205,6 @@ time_t rtcGetTimeUnixSec(RTCDriver *rtcp) {
  * @api
  */
 void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec) {
-#if STM32_RTC_IS_CALENDAR
 #if STM32_RTC_HAS_SUBSECONDS
   RTCTime timespec = {0,0,FALSE,0};
 #else
@@ -291,16 +215,6 @@ void rtcSetTimeUnixSec(RTCDriver *rtcp, time_t tv_sec) {
   localtime_r(&tv_sec, &timp);
   stm32_rtc_tm2bcd(&timp, &timespec);
   rtcSetTime(rtcp, &timespec);
-#endif
-
-#if LPC17xx_RTC_IS_CALENDAR
-  RTCTime timespec;
-  struct tm timp;
-
-  localtime_r(&tv_sec, &timp);
-  lpc17xx_rtc_tm2format(&timp, &timespec);
-  rtcSetTime(rtcp, &timespec);
-#endif
 }
 
 /**
@@ -439,9 +353,7 @@ uint32_t rtcGetTimeFatFromCounter(RTCDriver *rtcp) {
 
   return fattime;
 }
-#endif /* STM32_RTC_IS_CALENDAR  || LPC17xx_RTC_IS_CALENDAR */
+#endif /* STM32_RTC_IS_CALENDAR */
 #endif /* (defined(STM32F4XX) || defined(STM32F2XX) || defined(STM32L1XX) || defined(STM32F1XX)) */
 
-#endif /* HAL_USE_RTC */
-
 /** @} */
diff --git a/os/various/chrtclib.h b/os/various/chrtclib.h
index daf53ec85..895abc1a7 100644
--- a/os/various/chrtclib.h
+++ b/os/various/chrtclib.h
@@ -31,8 +31,6 @@
 
 #include <time.h>
 
-#if HAL_USE_RTC || defined(__DOXYGEN__)
-
 /*===========================================================================*/
 /* External declarations.                                                    */
 /*===========================================================================*/
@@ -52,8 +50,6 @@ extern "C" {
 }
 #endif
 
-#endif /* HAL_USE_RTC */
-
 #endif /* CHRTCLIB_H_ */
 
 /** @} */
diff --git a/os/various/cpp_wrappers/ch.cpp b/os/various/cpp_wrappers/ch.cpp
index 5f2621a61..32e22ad9d 100644
--- a/os/various/cpp_wrappers/ch.cpp
+++ b/os/various/cpp_wrappers/ch.cpp
@@ -92,7 +92,7 @@ namespace chibios_rt {
   void Timer::resetI() {
 
     if (chVTIsArmedI(&timer_ref))
-      chVTResetI(&timer_ref);
+      chVTDoResetI(&timer_ref);
   }
 
   bool Timer::isArmedI(void) {
diff --git a/os/various/devices_lib/accel/lis302dl.c b/os/various/devices_lib/accel/lis302dl.c
index 14e2a0ad1..77c2566ad 100644
--- a/os/various/devices_lib/accel/lis302dl.c
+++ b/os/various/devices_lib/accel/lis302dl.c
@@ -22,7 +22,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 #include "lis302dl.h"
 
@@ -81,7 +80,7 @@ void lis302dlWriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) {
   default:
     /* Reserved register must not be written, according to the datasheet
        this could permanently damage the device.*/
-    chDbgAssert(FALSE, "lis302dlWriteRegister(), #1", "reserved register");
+    osalDbgAssert(FALSE, "reserved register");
   case LIS302DL_WHO_AM_I:
   case LIS302DL_HP_FILTER_RESET:
   case LIS302DL_STATUS_REG:
diff --git a/os/various/devices_lib/accel/lis302dl.dox b/os/various/devices_lib/accel/lis302dl.dox
index 7b9530f10..02f51606a 100644
--- a/os/various/devices_lib/accel/lis302dl.dox
+++ b/os/various/devices_lib/accel/lis302dl.dox
@@ -1,17 +1,21 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
 
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
+    This file is part of ChibiOS/RT.
 
-        http://www.apache.org/licenses/LICENSE-2.0
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
 
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
 /**
diff --git a/os/various/evtimer.c b/os/various/evtimer.c
index a077529da..38c8cb872 100644
--- a/os/various/evtimer.c
+++ b/os/various/evtimer.c
@@ -25,40 +25,61 @@
 #include "ch.h"
 #include "evtimer.h"
 
+/*===========================================================================*/
+/* Module local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions.                                                   */
+/*===========================================================================*/
+
 static void tmrcb(void *p) {
-  EvTimer *etp = p;
+  event_timer_t *etp = p;
 
-  chSysLockFromIsr();
+  chSysLockFromISR();
   chEvtBroadcastI(&etp->et_es);
-  chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp);
-  chSysUnlockFromIsr();
+  chVTDoSetI(&etp->et_vt, etp->et_interval, tmrcb, etp);
+  chSysUnlockFromISR();
 }
 
+/*===========================================================================*/
+/* Module exported functions.                                                */
+/*===========================================================================*/
+
 /**
- * @brief Starts the timer
- * @details If the timer was already running then the function has no effect.
+ * @brief Initializes an @p event_timer_t structure.
  *
- * @param etp pointer to an initialized @p EvTimer structure.
+ * @param[out] etp      the @p event_timer_t structure to be initialized
+ * @param[in] time      the interval in system ticks
  */
-void evtStart(EvTimer *etp) {
-
-  chSysLock();
+void evtObjectInit(event_timer_t *etp, systime_t time) {
 
-  if (!chVTIsArmedI(&etp->et_vt))
-    chVTSetI(&etp->et_vt, etp->et_interval, tmrcb, etp);
-
-  chSysUnlock();
+  chEvtObjectInit(&etp->et_es);
+  chVTObjectInit(&etp->et_vt);
+  etp->et_interval = time;
 }
 
 /**
- * @brief Stops the timer.
- * @details If the timer was already stopped then the function has no effect.
+ * @brief   Starts the timer
+ * @details If the timer was already running then the function has no effect.
  *
- * @param etp pointer to an initialized @p EvTimer structure.
+ * @param[in] etp       pointer to an initialized @p event_timer_t structure.
  */
-void evtStop(EvTimer *etp) {
+void evtStart(event_timer_t *etp) {
 
-  chVTReset(&etp->et_vt);
+  chVTSet(&etp->et_vt, etp->et_interval, tmrcb, etp);
 }
 
 /** @} */
diff --git a/os/various/evtimer.h b/os/various/evtimer.h
index 613c688a6..bb67691ba 100644
--- a/os/various/evtimer.h
+++ b/os/various/evtimer.h
@@ -25,42 +25,68 @@
 #ifndef _EVTIMER_H_
 #define _EVTIMER_H_
 
+/*===========================================================================*/
+/* Module constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
 
 /*
  * Module dependencies check.
  */
-#if !CH_USE_EVENTS
-#error "Event Timers require CH_USE_EVENTS"
+#if !CH_CFG_USE_EVENTS
+#error "Event Timers require CH_CFG_USE_EVENTS"
 #endif
 
+/*===========================================================================*/
+/* Module data structures and types.                                         */
+/*===========================================================================*/
+
 /**
- * @brief Event timer structure.
+ * @brief   Type of a event timer structure.
  */
 typedef struct {
-  VirtualTimer  et_vt;
-  EventSource   et_es;
-  systime_t     et_interval;
-} EvTimer;
+  virtual_timer_t       et_vt;
+  event_source_t        et_es;
+  systime_t             et_interval;
+} event_timer_t;
+
+/*===========================================================================*/
+/* Module macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-  void evtStart(EvTimer *etp);
-  void evtStop(EvTimer *etp);
+  void evtObjectInit(event_timer_t *etp, systime_t time);
+  void evtStart(event_timer_t *etp);
 #ifdef __cplusplus
 }
 #endif
 
+/*===========================================================================*/
+/* Module inline functions.                                                  */
+/*===========================================================================*/
+
 /**
- * @brief Initializes an @p EvTimer structure.
+ * @brief   Stops the timer.
+ * @details If the timer was already stopped then the function has no effect.
  *
- * @param etp the EvTimer structure to be initialized
- * @param time the interval in system ticks
+ * @param[in] etp       pointer to an initialized @p event_timer_t structure.
  */
-#define evtInit(etp, time) {                                            \
-  chEvtInit(&(etp)->et_es);                                             \
-  (etp)->et_vt.vt_func = NULL;                                          \
-  (etp)->et_interval = (time);                                          \
+static inline void vevtStop(event_timer_t *etp) {
+
+  chVTReset(&etp->et_vt);
 }
 
 #endif /* _EVTIMER_H_ */
diff --git a/os/various/fatfs_bindings/fatfs.mk b/os/various/fatfs_bindings/fatfs.mk
deleted file mode 100644
index 682091e00..000000000
--- a/os/various/fatfs_bindings/fatfs.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-# FATFS files.
-FATFSSRC = ${CHIBIOS}/os/various/fatfs_bindings/fatfs_diskio.c \
-           ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \
-           ${CHIBIOS}/ext/fatfs/src/ff.c \
-           ${CHIBIOS}/ext/fatfs/src/option/ccsbcs.c
-
-FATFSINC = ${CHIBIOS}/ext/fatfs/src
diff --git a/os/various/fatfs_bindings/fatfs_diskio.c b/os/various/fatfs_bindings/fatfs_diskio.c
deleted file mode 100644
index c724fa5f9..000000000
--- a/os/various/fatfs_bindings/fatfs_diskio.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*-----------------------------------------------------------------------*/
-/* Low level disk I/O module skeleton for FatFs     (C)ChaN, 2007        */
-/*-----------------------------------------------------------------------*/
-/* This is a stub disk I/O module that acts as front end of the existing */
-/* disk I/O modules and attach it to FatFs module with common interface. */
-/*-----------------------------------------------------------------------*/
-
-#include "ch.h"
-#include "hal.h"
-#include "ffconf.h"
-#include "diskio.h"
-
-#if HAL_USE_MMC_SPI && HAL_USE_SDC
-#error "cannot specify both MMC_SPI and SDC drivers"
-#endif
-
-#if HAL_USE_MMC_SPI
-extern MMCDriver MMCD1;
-#elif HAL_USE_SDC
-extern SDCDriver SDCD1;
-#else
-#error "MMC_SPI or SDC driver must be specified"
-#endif
-
-#if HAL_USE_RTC
-#include "chrtclib.h"
-extern RTCDriver RTCD1;
-#endif
-
-/*-----------------------------------------------------------------------*/
-/* Correspondence between physical drive number and physical drive.      */
-
-#define MMC     0
-#define SDC     0
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Inidialize a Drive                                                    */
-
-DSTATUS disk_initialize (
-    BYTE drv                /* Physical drive nmuber (0..) */
-)
-{
-  DSTATUS stat;
-
-  switch (drv) {
-#if HAL_USE_MMC_SPI
-  case MMC:
-    stat = 0;
-    /* It is initialized externally, just reads the status.*/
-    if (blkGetDriverState(&MMCD1) != BLK_READY)
-      stat |= STA_NOINIT;
-    if (mmcIsWriteProtected(&MMCD1))
-      stat |=  STA_PROTECT;
-    return stat;
-#else
-  case SDC:
-    stat = 0;
-    /* It is initialized externally, just reads the status.*/
-    if (blkGetDriverState(&SDCD1) != BLK_READY)
-      stat |= STA_NOINIT;
-    if (sdcIsWriteProtected(&SDCD1))
-      stat |=  STA_PROTECT;
-    return stat;
-#endif
-  }
-  return STA_NODISK;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Return Disk Status                                                    */
-
-DSTATUS disk_status (
-    BYTE drv        /* Physical drive nmuber (0..) */
-)
-{
-  DSTATUS stat;
-
-  switch (drv) {
-#if HAL_USE_MMC_SPI
-  case MMC:
-    stat = 0;
-    /* It is initialized externally, just reads the status.*/
-    if (blkGetDriverState(&MMCD1) != BLK_READY)
-      stat |= STA_NOINIT;
-    if (mmcIsWriteProtected(&MMCD1))
-      stat |= STA_PROTECT;
-    return stat;
-#else
-  case SDC:
-    stat = 0;
-    /* It is initialized externally, just reads the status.*/
-    if (blkGetDriverState(&SDCD1) != BLK_READY)
-      stat |= STA_NOINIT;
-    if (sdcIsWriteProtected(&SDCD1))
-      stat |= STA_PROTECT;
-    return stat;
-#endif
-  }
-  return STA_NODISK;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Sector(s)                                                        */
-
-DRESULT disk_read (
-    BYTE drv,        /* Physical drive nmuber (0..) */
-    BYTE *buff,        /* Data buffer to store read data */
-    DWORD sector,    /* Sector address (LBA) */
-    BYTE count        /* Number of sectors to read (1..255) */
-)
-{
-  switch (drv) {
-#if HAL_USE_MMC_SPI
-  case MMC:
-    if (blkGetDriverState(&MMCD1) != BLK_READY)
-      return RES_NOTRDY;
-    if (mmcStartSequentialRead(&MMCD1, sector))
-      return RES_ERROR;
-    while (count > 0) {
-      if (mmcSequentialRead(&MMCD1, buff))
-        return RES_ERROR;
-      buff += MMCSD_BLOCK_SIZE;
-      count--;
-    }
-    if (mmcStopSequentialRead(&MMCD1))
-        return RES_ERROR;
-    return RES_OK;
-#else
-  case SDC:
-    if (blkGetDriverState(&SDCD1) != BLK_READY)
-      return RES_NOTRDY;
-    if (sdcRead(&SDCD1, sector, buff, count))
-      return RES_ERROR;
-    return RES_OK;
-#endif
-  }
-  return RES_PARERR;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Write Sector(s)                                                       */
-
-#if _READONLY == 0
-DRESULT disk_write (
-    BYTE drv,            /* Physical drive nmuber (0..) */
-    const BYTE *buff,    /* Data to be written */
-    DWORD sector,        /* Sector address (LBA) */
-    BYTE count            /* Number of sectors to write (1..255) */
-)
-{
-  switch (drv) {
-#if HAL_USE_MMC_SPI
-  case MMC:
-    if (blkGetDriverState(&MMCD1) != BLK_READY)
-        return RES_NOTRDY;
-    if (mmcIsWriteProtected(&MMCD1))
-        return RES_WRPRT;
-    if (mmcStartSequentialWrite(&MMCD1, sector))
-        return RES_ERROR;
-    while (count > 0) {
-        if (mmcSequentialWrite(&MMCD1, buff))
-            return RES_ERROR;
-        buff += MMCSD_BLOCK_SIZE;
-        count--;
-    }
-    if (mmcStopSequentialWrite(&MMCD1))
-        return RES_ERROR;
-    return RES_OK;
-#else
-  case SDC:
-    if (blkGetDriverState(&SDCD1) != BLK_READY)
-      return RES_NOTRDY;
-    if (sdcWrite(&SDCD1, sector, buff, count))
-      return RES_ERROR;
-    return RES_OK;
-#endif
-  }
-  return RES_PARERR;
-}
-#endif /* _READONLY */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Miscellaneous Functions                                               */
-
-DRESULT disk_ioctl (
-    BYTE drv,        /* Physical drive nmuber (0..) */
-    BYTE ctrl,        /* Control code */
-    void *buff        /* Buffer to send/receive control data */
-)
-{
-  switch (drv) {
-#if HAL_USE_MMC_SPI
-  case MMC:
-    switch (ctrl) {
-    case CTRL_SYNC:
-        return RES_OK;
-    case GET_SECTOR_SIZE:
-        *((WORD *)buff) = MMCSD_BLOCK_SIZE;
-        return RES_OK;
-#if _USE_ERASE
-    case CTRL_ERASE_SECTOR:
-        mmcErase(&MMCD1, *((DWORD *)buff), *((DWORD *)buff + 1));
-        return RES_OK;
-#endif
-    default:
-        return RES_PARERR;
-    }
-#else
-  case SDC:
-    switch (ctrl) {
-    case CTRL_SYNC:
-        return RES_OK;
-    case GET_SECTOR_COUNT:
-        *((DWORD *)buff) = mmcsdGetCardCapacity(&SDCD1);
-        return RES_OK;
-    case GET_SECTOR_SIZE:
-        *((WORD *)buff) = MMCSD_BLOCK_SIZE;
-        return RES_OK;
-    case GET_BLOCK_SIZE:
-        *((DWORD *)buff) = 256; /* 512b blocks in one erase block */
-        return RES_OK;
-#if _USE_ERASE
-    case CTRL_ERASE_SECTOR:
-        sdcErase(&SDCD1, *((DWORD *)buff), *((DWORD *)buff + 1));
-        return RES_OK;
-#endif
-    default:
-        return RES_PARERR;
-    }
-#endif
-  }
-  return RES_PARERR;
-}
-
-DWORD get_fattime(void) {
-#if HAL_USE_RTC
-    return rtcGetTimeFat(&RTCD1);
-#else
-    return ((uint32_t)0 | (1 << 16)) | (1 << 21); /* wrong but valid time */
-#endif
-}
-
-
-
diff --git a/os/various/fatfs_bindings/fatfs_syscall.c b/os/various/fatfs_bindings/fatfs_syscall.c
deleted file mode 100644
index a42cbcffb..000000000
--- a/os/various/fatfs_bindings/fatfs_syscall.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*------------------------------------------------------------------------*/
-/* Sample code of OS dependent controls for FatFs R0.08b                  */
-/* (C)ChaN, 2011                                                          */
-/*------------------------------------------------------------------------*/
-
-#include "ch.h"
-#include "ff.h"
-
-#if _FS_REENTRANT
-/*------------------------------------------------------------------------*/
-/* Static array of Synchronization Objects                                */
-/*------------------------------------------------------------------------*/
-static Semaphore ff_sem[_VOLUMES];
-
-/*------------------------------------------------------------------------*/
-/* Create a Synchronization Object                                        */
-/*------------------------------------------------------------------------*/
-int ff_cre_syncobj(BYTE vol, _SYNC_t *sobj) {
-
-  *sobj = &ff_sem[vol];
-  chSemInit(*sobj, 1);
-  return TRUE;
-}
-
-/*------------------------------------------------------------------------*/
-/* Delete a Synchronization Object                                        */
-/*------------------------------------------------------------------------*/
-int ff_del_syncobj(_SYNC_t sobj) {
-
-  chSemReset(sobj, 0);
-  return TRUE;
-}
-
-/*------------------------------------------------------------------------*/
-/* Request Grant to Access the Volume                                     */
-/*------------------------------------------------------------------------*/
-int ff_req_grant(_SYNC_t sobj) {
-
-  msg_t msg = chSemWaitTimeout(sobj, (systime_t)_FS_TIMEOUT);
-  return msg == RDY_OK;
-}
-
-/*------------------------------------------------------------------------*/
-/* Release Grant to Access the Volume                                     */
-/*------------------------------------------------------------------------*/
-void ff_rel_grant(_SYNC_t sobj) {
-
-  chSemSignal(sobj);
-}
-#endif /* _FS_REENTRANT */
-
-#if _USE_LFN == 3	/* LFN with a working buffer on the heap */
-/*------------------------------------------------------------------------*/
-/* Allocate a memory block                                                */
-/*------------------------------------------------------------------------*/
-void *ff_memalloc(UINT size) {
-
-  return chHeapAlloc(NULL, size);
-}
-
-/*------------------------------------------------------------------------*/
-/* Free a memory block                                                    */
-/*------------------------------------------------------------------------*/
-void ff_memfree(void *mblock) {
-
-  chHeapFree(mblock);
-}
-#endif /* _USE_LFN == 3 */
diff --git a/os/various/fatfs_bindings/readme.txt b/os/various/fatfs_bindings/readme.txt
deleted file mode 100644
index 8735cce54..000000000
--- a/os/various/fatfs_bindings/readme.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-This directory contains the ChibiOS/RT "official" bindings with the FatFS
-library by ChaN: http://elm-chan.org
-
-In order to use FatFS within ChibiOS/RT project, unzip FatFS under
-./ext/fatfs then include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk
-in your makefile.
diff --git a/os/various/lwip_bindings/arch/cc.h b/os/various/lwip_bindings/arch/cc.h
deleted file mode 100644
index 87e900272..000000000
--- a/os/various/lwip_bindings/arch/cc.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
- * **** This file incorporates work covered by the following copyright and ****
- * **** permission notice:                                                 ****
- *
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-#ifndef __CC_H__
-#define __CC_H__
-
-#include <ch.h>
-
-typedef uint8_t         u8_t;
-typedef int8_t          s8_t;
-typedef uint16_t        u16_t;
-typedef int16_t         s16_t;
-typedef uint32_t        u32_t;
-typedef int32_t         s32_t;
-typedef uint32_t        mem_ptr_t;
-
-#define LWIP_PLATFORM_DIAG(x)
-#define LWIP_PLATFORM_ASSERT(x) {                                       \
-  chSysHalt();                                                          \
-}
-
-#define BYTE_ORDER LITTLE_ENDIAN
-#define LWIP_PROVIDE_ERRNO
-
-#endif /* __CC_H__ */
diff --git a/os/various/lwip_bindings/arch/perf.h b/os/various/lwip_bindings/arch/perf.h
deleted file mode 100644
index 81ef4673b..000000000
--- a/os/various/lwip_bindings/arch/perf.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
- * **** This file incorporates work covered by the following copyright and ****
- * **** permission notice:                                                 ****
- *
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-#ifndef __PERF_H__
-#define __PERF_H__
-
-#define PERF_START
-#define PERF_STOP(x)
-
-#endif /* __PERF_H__ */
diff --git a/os/various/lwip_bindings/arch/sys_arch.c b/os/various/lwip_bindings/arch/sys_arch.c
deleted file mode 100644
index 57ed14124..000000000
--- a/os/various/lwip_bindings/arch/sys_arch.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
- * **** This file incorporates work covered by the following copyright and ****
- * **** permission notice:                                                 ****
- *
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-// see http://lwip.wikia.com/wiki/Porting_for_an_OS for instructions
-
-#include "ch.h"
-
-#include "lwip/opt.h"
-#include "lwip/mem.h"
-#include "lwip/sys.h"
-#include "lwip/stats.h"
-
-#include "arch/cc.h"
-#include "arch/sys_arch.h"
-
-void sys_init(void) {
-
-}
-
-err_t sys_sem_new(sys_sem_t *sem, u8_t count) {
-
-  *sem = chHeapAlloc(NULL, sizeof(Semaphore));
-  if (*sem == 0) {
-    SYS_STATS_INC(sem.err);
-    return ERR_MEM;
-  }
-  else {
-    chSemInit(*sem, (cnt_t)count);
-    SYS_STATS_INC_USED(sem);
-    return ERR_OK;
-  }
-}
-
-void sys_sem_free(sys_sem_t *sem) {
-
-  chHeapFree(*sem);
-  *sem = SYS_SEM_NULL;
-  SYS_STATS_DEC(sem.used);
-}
-
-void sys_sem_signal(sys_sem_t *sem) {
-
-  chSemSignal(*sem);
-}
-
-/* CHIBIOS FIX: specific variant of this call to be called from within
-   a lock.*/
-void sys_sem_signal_S(sys_sem_t *sem) {
-
-  chSemSignalI(*sem);
-  chSchRescheduleS();
-}
-
-u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) {
-  systime_t time, tmo;
-
-  chSysLock();
-  tmo = timeout > 0 ? (systime_t)timeout : TIME_INFINITE;
-  time = chTimeNow();
-  if (chSemWaitTimeoutS(*sem, tmo) != RDY_OK)
-    time = SYS_ARCH_TIMEOUT;
-  else
-    time = chTimeNow() - time;
-  chSysUnlock();
-  return time;
-}
-
-int sys_sem_valid(sys_sem_t *sem) {
-  return *sem != SYS_SEM_NULL;
-}
-
-// typically called within lwIP after freeing a semaphore
-// to make sure the pointer is not left pointing to invalid data
-void sys_sem_set_invalid(sys_sem_t *sem) {
-  *sem = SYS_SEM_NULL;
-}
-
-err_t sys_mbox_new(sys_mbox_t *mbox, int size) {
-  
-  *mbox = chHeapAlloc(NULL, sizeof(Mailbox) + sizeof(msg_t) * size);
-  if (*mbox == 0) {
-    SYS_STATS_INC(mbox.err);
-    return ERR_MEM;
-  }
-  else {
-    chMBInit(*mbox, (void *)(((uint8_t *)*mbox) + sizeof(Mailbox)), size);
-    SYS_STATS_INC(mbox.used);
-    return ERR_OK;
-  }
-}
-
-void sys_mbox_free(sys_mbox_t *mbox) {
-
-  if (chMBGetUsedCountI(*mbox) != 0) {
-    // If there are messages still present in the mailbox when the mailbox
-    // is deallocated, it is an indication of a programming error in lwIP
-    // and the developer should be notified.
-    SYS_STATS_INC(mbox.err);
-    chMBReset(*mbox);
-  }
-  chHeapFree(*mbox);
-  *mbox = SYS_MBOX_NULL;
-  SYS_STATS_DEC(mbox.used);
-}
-
-void sys_mbox_post(sys_mbox_t *mbox, void *msg) {
-
-  chMBPost(*mbox, (msg_t)msg, TIME_INFINITE);
-}
-
-err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) {
-
-  if (chMBPost(*mbox, (msg_t)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) {
-    SYS_STATS_INC(mbox.err);
-    return ERR_MEM;
-  }
-  return ERR_OK;
-}
-
-u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) {
-  systime_t time, tmo;
-
-  chSysLock();
-  tmo = timeout > 0 ? (systime_t)timeout : TIME_INFINITE;
-  time = chTimeNow();
-  if (chMBFetchS(*mbox, (msg_t *)msg, tmo) != RDY_OK)
-    time = SYS_ARCH_TIMEOUT;
-  else
-    time = chTimeNow() - time;
-  chSysUnlock();
-  return time;
-}
-
-u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) {
-
-  if (chMBFetch(*mbox, (msg_t *)msg, TIME_IMMEDIATE) == RDY_TIMEOUT)
-    return SYS_MBOX_EMPTY;
-  return 0;
-}
-
-int sys_mbox_valid(sys_mbox_t *mbox) {
-  return *mbox != SYS_MBOX_NULL;
-}
-
-// typically called within lwIP after freeing an mbox
-// to make sure the pointer is not left pointing to invalid data
-void sys_mbox_set_invalid(sys_mbox_t *mbox) {
-  *mbox = SYS_MBOX_NULL;
-}
-
-sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread,
-                            void *arg, int stacksize, int prio) {
-
-  size_t wsz;
-  void *wsp;
-
-  (void)name;
-  wsz = THD_WA_SIZE(stacksize);
-  wsp = chCoreAlloc(wsz);
-  if (wsp == NULL)
-    return NULL;
-  return (sys_thread_t)chThdCreateStatic(wsp, wsz, prio, (tfunc_t)thread, arg);
-}
-
-sys_prot_t sys_arch_protect(void) {
-
-  chSysLock();
-  return 0;
-}
-
-void sys_arch_unprotect(sys_prot_t pval) {
-
-  (void)pval;
-  chSysUnlock();
-}
-
-u32_t sys_now(void) {
-
-#if CH_FREQUENCY == 1000
-  return (u32_t)chTimeNow();
-#elif (CH_FREQUENCY / 1000) >= 1 && (CH_FREQUENCY % 1000) == 0
-  return ((u32_t)chTimeNow() - 1) / (CH_FREQUENCY / 1000) + 1;
-#elif (1000 / CH_FREQUENCY) >= 1 && (1000 % CH_FREQUENCY) == 0
-  return ((u32_t)chTimeNow() - 1) * (1000 / CH_FREQUENCY) + 1;
-#else
-  return (u32_t)(((u64_t)(chTimeNow() - 1) * 1000) / CH_FREQUENCY) + 1;
-#endif
-}
diff --git a/os/various/lwip_bindings/arch/sys_arch.h b/os/various/lwip_bindings/arch/sys_arch.h
deleted file mode 100644
index 6c10607f7..000000000
--- a/os/various/lwip_bindings/arch/sys_arch.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
- * **** This file incorporates work covered by the following copyright and ****
- * **** permission notice:                                                 ****
- *
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-#include <ch.h>
-
-#ifndef __SYS_ARCH_H__
-#define __SYS_ARCH_H__
-
-typedef Semaphore *     sys_sem_t;
-typedef Mailbox *       sys_mbox_t;
-typedef Thread *        sys_thread_t;
-typedef int             sys_prot_t;
-
-#define SYS_MBOX_NULL   (Mailbox *)0
-#define SYS_THREAD_NULL (Thread *)0
-#define SYS_SEM_NULL    (Semaphore *)0
-
-/* let sys.h use binary semaphores for mutexes */
-#define LWIP_COMPAT_MUTEX 1
-
-#endif /* __SYS_ARCH_H__ */
diff --git a/os/various/lwip_bindings/lwip.mk b/os/various/lwip_bindings/lwip.mk
deleted file mode 100644
index afaaf1454..000000000
--- a/os/various/lwip_bindings/lwip.mk
+++ /dev/null
@@ -1,54 +0,0 @@
-# List of the required lwIP files.
-LWIP = 	${CHIBIOS}/ext/lwip
-
-LWBINDSRC = \
-        $(CHIBIOS)/os/various/lwip_bindings/lwipthread.c \
-        $(CHIBIOS)/os/various/lwip_bindings/arch/sys_arch.c
-
-LWNETIFSRC = \
-        ${LWIP}/src/netif/etharp.c
-
-LWCORESRC = \
-        ${LWIP}/src/core/dhcp.c \
-        ${LWIP}/src/core/dns.c \
-        ${LWIP}/src/core/init.c \
-        ${LWIP}/src/core/mem.c \
-        ${LWIP}/src/core/memp.c \
-        ${LWIP}/src/core/netif.c \
-        ${LWIP}/src/core/pbuf.c \
-        ${LWIP}/src/core/raw.c \
-        ${LWIP}/src/core/stats.c \
-        ${LWIP}/src/core/sys.c \
-        ${LWIP}/src/core/tcp.c \
-        ${LWIP}/src/core/tcp_in.c \
-        ${LWIP}/src/core/tcp_out.c \
-        ${LWIP}/src/core/udp.c
-
-LWIPV4SRC = \
-        ${LWIP}/src/core/ipv4/autoip.c \
-        ${LWIP}/src/core/ipv4/icmp.c \
-        ${LWIP}/src/core/ipv4/igmp.c \
-        ${LWIP}/src/core/ipv4/inet.c \
-        ${LWIP}/src/core/ipv4/inet_chksum.c \
-        ${LWIP}/src/core/ipv4/ip.c \
-        ${LWIP}/src/core/ipv4/ip_addr.c \
-        ${LWIP}/src/core/ipv4/ip_frag.c \
-        ${LWIP}/src/core/def.c \
-        ${LWIP}/src/core/timers.c
-
-LWAPISRC = \
-        ${LWIP}/src/api/api_lib.c \
-        ${LWIP}/src/api/api_msg.c \
-        ${LWIP}/src/api/err.c \
-        ${LWIP}/src/api/netbuf.c \
-        ${LWIP}/src/api/netdb.c \
-        ${LWIP}/src/api/netifapi.c \
-        ${LWIP}/src/api/sockets.c \
-        ${LWIP}/src/api/tcpip.c
-
-LWSRC = $(LWBINDSRC) $(LWNETIFSRC) $(LWCORESRC) $(LWIPV4SRC) $(LWAPISRC)
-
-LWINC = \
-        $(CHIBIOS)/os/various/lwip_bindings \
-        ${LWIP}/src/include \
-        ${LWIP}/src/include/ipv4
diff --git a/os/various/lwip_bindings/lwipthread.c b/os/various/lwip_bindings/lwipthread.c
deleted file mode 100644
index 38ef8cfd2..000000000
--- a/os/various/lwip_bindings/lwipthread.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-/*
- * **** This file incorporates work covered by the following copyright and ****
- * **** permission notice:                                                 ****
- *
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-/**
- * @file lwipthread.c
- * @brief LWIP wrapper thread code.
- * @addtogroup LWIP_THREAD
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-#include "evtimer.h"
-
-#include "lwipthread.h"
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-#include <lwip/stats.h>
-#include <lwip/snmp.h>
-#include <lwip/tcpip.h>
-#include "netif/etharp.h"
-#include "netif/ppp_oe.h"
-
-#define PERIODIC_TIMER_ID       1
-#define FRAME_RECEIVED_ID       2
-
-/**
- * Stack area for the LWIP-MAC thread.
- */
-WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE);
-
-/*
- * Initialization.
- */
-static void low_level_init(struct netif *netif) {
-  /* set MAC hardware address length */
-  netif->hwaddr_len = ETHARP_HWADDR_LEN;
-
-  /* maximum transfer unit */
-  netif->mtu = 1500;
-
-  /* device capabilities */
-  /* don't set NETIF_FLAG_ETHARP if this device is not an Ethernet one */
-  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
-
-  /* Do whatever else is needed to initialize interface. */
-}
-
-/*
- * Transmits a frame.
- */
-static err_t low_level_output(struct netif *netif, struct pbuf *p) {
-  struct pbuf *q;
-  MACTransmitDescriptor td;
-
-  (void)netif;
-  if (macWaitTransmitDescriptor(&ETHD1, &td, MS2ST(LWIP_SEND_TIMEOUT)) != RDY_OK)
-    return ERR_TIMEOUT;
-
-#if ETH_PAD_SIZE
-  pbuf_header(p, -ETH_PAD_SIZE);        /* drop the padding word */
-#endif
-
-  /* Iterates through the pbuf chain. */
-  for(q = p; q != NULL; q = q->next)
-    macWriteTransmitDescriptor(&td, (uint8_t *)q->payload, (size_t)q->len);
-  macReleaseTransmitDescriptor(&td);
-
-#if ETH_PAD_SIZE
-  pbuf_header(p, ETH_PAD_SIZE);         /* reclaim the padding word */
-#endif
-
-  LINK_STATS_INC(link.xmit);
-
-  return ERR_OK;
-}
-
-/*
- * Receives a frame.
- */
-static struct pbuf *low_level_input(struct netif *netif) {
-  MACReceiveDescriptor rd;
-  struct pbuf *p, *q;
-  u16_t len;
-
-  (void)netif;
-  if (macWaitReceiveDescriptor(&ETHD1, &rd, TIME_IMMEDIATE) == RDY_OK) {
-    len = (u16_t)rd.size;
-
-#if ETH_PAD_SIZE
-    len += ETH_PAD_SIZE;        /* allow room for Ethernet padding */
-#endif
-
-    /* We allocate a pbuf chain of pbufs from the pool. */
-    p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
-
-    if (p != NULL) {
-
-#if ETH_PAD_SIZE
-      pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
-#endif
-
-      /* Iterates through the pbuf chain. */
-      for(q = p; q != NULL; q = q->next)
-        macReadReceiveDescriptor(&rd, (uint8_t *)q->payload, (size_t)q->len);
-      macReleaseReceiveDescriptor(&rd);
-
-#if ETH_PAD_SIZE
-      pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
-#endif
-
-      LINK_STATS_INC(link.recv);
-    }
-    else {
-      macReleaseReceiveDescriptor(&rd);
-      LINK_STATS_INC(link.memerr);
-      LINK_STATS_INC(link.drop);
-    }
-    return p;
-  }
-  return NULL;
-}
-
-/*
- * Initialization.
- */
-static err_t ethernetif_init(struct netif *netif) {
-#if LWIP_NETIF_HOSTNAME
-  /* Initialize interface hostname */
-  netif->hostname = "lwip";
-#endif /* LWIP_NETIF_HOSTNAME */
-
-  /*
-   * Initialize the snmp variables and counters inside the struct netif.
-   * The last argument should be replaced with your link speed, in units
-   * of bits per second.
-   */
-  NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LWIP_LINK_SPEED);
-
-  netif->state = NULL;
-  netif->name[0] = LWIP_IFNAME0;
-  netif->name[1] = LWIP_IFNAME1;
-  /* We directly use etharp_output() here to save a function call.
-   * You can instead declare your own function an call etharp_output()
-   * from it if you have to do some checks before sending (e.g. if link
-   * is available...) */
-  netif->output = etharp_output;
-  netif->linkoutput = low_level_output;
-
-  /* initialize the hardware */
-  low_level_init(netif);
-
-  return ERR_OK;
-}
-
-/**
- * @brief LWIP handling thread.
- *
- * @param[in] p pointer to a @p lwipthread_opts structure or @p NULL
- * @return The function does not return.
- */
-msg_t lwip_thread(void *p) {
-  EvTimer evt;
-  EventListener el0, el1;
-  struct ip_addr ip, gateway, netmask;
-  static struct netif thisif;
-  static const MACConfig mac_config = {thisif.hwaddr};
-
-  chRegSetThreadName("lwipthread");
-
-  /* Initializes the thing.*/
-  tcpip_init(NULL, NULL);
-
-  /* TCP/IP parameters, runtime or compile time.*/
-  if (p) {
-    struct lwipthread_opts *opts = p;
-    unsigned i;
-
-    for (i = 0; i < 6; i++)
-      thisif.hwaddr[i] = opts->macaddress[i];
-    ip.addr = opts->address;
-    gateway.addr = opts->gateway;
-    netmask.addr = opts->netmask;
-  }
-  else {
-    thisif.hwaddr[0] = LWIP_ETHADDR_0;
-    thisif.hwaddr[1] = LWIP_ETHADDR_1;
-    thisif.hwaddr[2] = LWIP_ETHADDR_2;
-    thisif.hwaddr[3] = LWIP_ETHADDR_3;
-    thisif.hwaddr[4] = LWIP_ETHADDR_4;
-    thisif.hwaddr[5] = LWIP_ETHADDR_5;
-    LWIP_IPADDR(&ip);
-    LWIP_GATEWAY(&gateway);
-    LWIP_NETMASK(&netmask);
-  }
-  macStart(&ETHD1, &mac_config);
-  netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input);
-
-  netif_set_default(&thisif);
-  netif_set_up(&thisif);
-
-  /* Setup event sources.*/
-  evtInit(&evt, LWIP_LINK_POLL_INTERVAL);
-  evtStart(&evt);
-  chEvtRegisterMask(&evt.et_es, &el0, PERIODIC_TIMER_ID);
-  chEvtRegisterMask(macGetReceiveEventSource(&ETHD1), &el1, FRAME_RECEIVED_ID);
-  chEvtAddEvents(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID);
-
-  /* Goes to the final priority after initialization.*/
-  chThdSetPriority(LWIP_THREAD_PRIORITY);
-
-  while (TRUE) {
-    eventmask_t mask = chEvtWaitAny(ALL_EVENTS);
-    if (mask & PERIODIC_TIMER_ID) {
-      bool_t current_link_status = macPollLinkStatus(&ETHD1);
-      if (current_link_status != netif_is_link_up(&thisif)) {
-        if (current_link_status)
-          tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up,
-                                     &thisif, 0);
-        else
-          tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down,
-                                     &thisif, 0);
-      }
-    }
-    if (mask & FRAME_RECEIVED_ID) {
-      struct pbuf *p;
-      while ((p = low_level_input(&thisif)) != NULL) {
-        struct eth_hdr *ethhdr = p->payload;
-        switch (htons(ethhdr->type)) {
-        /* IP or ARP packet? */
-        case ETHTYPE_IP:
-        case ETHTYPE_ARP:
-#if PPPOE_SUPPORT
-        /* PPPoE packet? */
-        case ETHTYPE_PPPOEDISC:
-        case ETHTYPE_PPPOE:
-#endif /* PPPOE_SUPPORT */
-          /* full packet send to tcpip_thread to process */
-          if (thisif.input(p, &thisif) == ERR_OK)
-            break;
-          LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
-        default:
-          pbuf_free(p);
-        }
-      }
-    }
-  }
-  return 0;
-}
-
-/** @} */
diff --git a/os/various/lwip_bindings/lwipthread.h b/os/various/lwip_bindings/lwipthread.h
deleted file mode 100644
index fe4de2870..000000000
--- a/os/various/lwip_bindings/lwipthread.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file lwipthread.h
- * @brief LWIP wrapper thread macros and structures.
- * @addtogroup LWIP_THREAD
- * @{
- */
-
-#ifndef _LWIPTHREAD_H_
-#define _LWIPTHREAD_H_
-
-#include <lwip/opt.h>
-
-/** @brief MAC thread priority.*/
-#ifndef LWIP_THREAD_PRIORITY
-#define LWIP_THREAD_PRIORITY                LOWPRIO
-#endif
-
-/** @brief MAC thread stack size. */
-#if !defined(LWIP_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
-#define LWIP_THREAD_STACK_SIZE              512
-#endif
-
-/** @brief Link poll interval. */
-#if !defined(LWIP_LINK_POLL_INTERVAL) || defined(__DOXYGEN__)
-#define LWIP_LINK_POLL_INTERVAL             S2ST(5)
-#endif
-
-/** @brief IP Address. */
-#if !defined(LWIP_IPADDR) || defined(__DOXYGEN__)
-#define LWIP_IPADDR(p)                      IP4_ADDR(p, 192, 168, 1, 20)
-#endif
-
-/** @brief IP Gateway. */
-#if !defined(LWIP_GATEWAY) || defined(__DOXYGEN__)
-#define LWIP_GATEWAY(p)                     IP4_ADDR(p, 192, 168, 1, 1)
-#endif
-
-/** @brief IP netmask. */
-#if !defined(LWIP_NETMASK) || defined(__DOXYGEN__)
-#define LWIP_NETMASK(p)                     IP4_ADDR(p, 255, 255, 255, 0)
-#endif
-
-/** @brief Transmission timeout. */
-#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__)
-#define LWIP_SEND_TIMEOUT                   50
-#endif
-
-/** @brief Link speed. */
-#if !defined(LWIP_LINK_SPEED) || defined(__DOXYGEN__)
-#define LWIP_LINK_SPEED                     100000000
-#endif
-
-/** @brief MAC Address byte 0. */
-#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__)
-#define LWIP_ETHADDR_0                      0xC2
-#endif
-
-/** @brief MAC Address byte 1. */
-#if !defined(LWIP_ETHADDR_1) || defined(__DOXYGEN__)
-#define LWIP_ETHADDR_1                      0xAF
-#endif
-
-/** @brief MAC Address byte 2. */
-#if !defined(LWIP_ETHADDR_2) || defined(__DOXYGEN__)
-#define LWIP_ETHADDR_2                      0x51
-#endif
-
-/** @brief MAC Address byte 3. */
-#if !defined(LWIP_ETHADDR_3) || defined(__DOXYGEN__)
-#define LWIP_ETHADDR_3                      0x03
-#endif
-
-/** @brief MAC Address byte 4. */
-#if !defined(LWIP_ETHADDR_4) || defined(__DOXYGEN__)
-#define LWIP_ETHADDR_4                      0xCF
-#endif
-
-/** @brief MAC Address byte 5. */
-#if !defined(LWIP_ETHADDR_5) || defined(__DOXYGEN__)
-#define LWIP_ETHADDR_5                      0x46
-#endif
-
-/** @brief Interface name byte 0. */
-#if !defined(LWIP_IFNAME0) || defined(__DOXYGEN__)
-#define LWIP_IFNAME0                        'm'
-#endif
-
-/** @brief Interface name byte 1. */
-#if !defined(LWIP_IFNAME1) || defined(__DOXYGEN__)
-#define LWIP_IFNAME1                        's'
-#endif
-
-/**
- * @brief Runtime TCP/IP settings.
- */
-struct lwipthread_opts {
-  uint8_t       *macaddress;
-  uint32_t      address;
-  uint32_t      netmask;
-  uint32_t      gateway;
-};
-
-extern WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE);
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  msg_t lwip_thread(void *p);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _LWIPTHREAD_H_ */
-
-/** @} */
diff --git a/os/various/lwip_bindings/readme.txt b/os/various/lwip_bindings/readme.txt
deleted file mode 100644
index 8a7a89e8c..000000000
--- a/os/various/lwip_bindings/readme.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-This directory contains the ChibiOS/RT "official" bindings with the lwIP
-TCP/IP stack: http://savannah.nongnu.org/projects/lwip
-
-In order to use FatFS within ChibiOS/RT project, unzip FatFS under
-./ext/lwip-1.4.0 then include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk
-in your makefile.
diff --git a/os/various/memstreams.c b/os/various/memstreams.c
index 11dd5b8ac..f7ba8b813 100644
--- a/os/various/memstreams.c
+++ b/os/various/memstreams.c
@@ -67,10 +67,10 @@ static msg_t put(void *ip, uint8_t b) {
   MemoryStream *msp = ip;
 
   if (msp->size - msp->eos <= 0)
-    return RDY_RESET;
+    return MSG_RESET;
   *(msp->buffer + msp->eos) = b;
   msp->eos += 1;
-  return RDY_OK;
+  return MSG_OK;
 }
 
 static msg_t get(void *ip) {
@@ -78,7 +78,7 @@ static msg_t get(void *ip) {
   MemoryStream *msp = ip;
 
   if (msp->eos - msp->offset <= 0)
-    return RDY_RESET;
+    return MSG_RESET;
   b = *(msp->buffer + msp->offset);
   msp->offset += 1;
   return b;
diff --git a/os/various/shell.c b/os/various/shell.c
index 839a4d16f..3aeb1e10a 100644
--- a/os/various/shell.c
+++ b/os/various/shell.c
@@ -32,7 +32,7 @@
 /**
  * @brief   Shell termination event source.
  */
-EventSource shell_terminated;
+event_source_t shell_terminated;
 
 static char *_strtok(char *str, const char *delim, char **saveptr) {
   char *token;
@@ -73,15 +73,15 @@ static void cmd_info(BaseSequentialStream *chp, int argc, char *argv[]) {
   }
 
   chprintf(chp, "Kernel:       %s\r\n", CH_KERNEL_VERSION);
-#ifdef CH_COMPILER_NAME
-  chprintf(chp, "Compiler:     %s\r\n", CH_COMPILER_NAME);
+#ifdef PORT_COMPILER_NAME
+  chprintf(chp, "Compiler:     %s\r\n", PORT_COMPILER_NAME);
 #endif
-  chprintf(chp, "Architecture: %s\r\n", CH_ARCHITECTURE_NAME);
-#ifdef CH_CORE_VARIANT_NAME
-  chprintf(chp, "Core Variant: %s\r\n", CH_CORE_VARIANT_NAME);
+  chprintf(chp, "Architecture: %s\r\n", PORT_ARCHITECTURE_NAME);
+#ifdef PORT_CORE_VARIANT_NAME
+  chprintf(chp, "Core Variant: %s\r\n", PORT_CORE_VARIANT_NAME);
 #endif
-#ifdef CH_PORT_INFO
-  chprintf(chp, "Port Info:    %s\r\n", CH_PORT_INFO);
+#ifdef PORT_INFO
+  chprintf(chp, "Port Info:    %s\r\n", PORT_INFO);
 #endif
 #ifdef PLATFORM_NAME
   chprintf(chp, "Platform:     %s\r\n", PLATFORM_NAME);
@@ -103,7 +103,7 @@ static void cmd_systime(BaseSequentialStream *chp, int argc, char *argv[]) {
     usage(chp, "systime");
     return;
   }
-  chprintf(chp, "%lu\r\n", (unsigned long)chTimeNow());
+  chprintf(chp, "%lu\r\n", (unsigned long)chVTGetSystemTime());
 }
 
 /**
@@ -115,7 +115,7 @@ static ShellCommand local_commands[] = {
   {NULL, NULL}
 };
 
-static bool_t cmdexec(const ShellCommand *scp, BaseSequentialStream *chp,
+static bool cmdexec(const ShellCommand *scp, BaseSequentialStream *chp,
                       char *name, int argc, char *argv[]) {
 
   while (scp->sc_name != NULL) {
@@ -133,10 +133,8 @@ static bool_t cmdexec(const ShellCommand *scp, BaseSequentialStream *chp,
  *
  * @param[in] p         pointer to a @p BaseSequentialStream object
  * @return              Termination reason.
- * @retval RDY_OK       terminated by command.
- * @retval RDY_RESET    terminated by reset condition on the I/O channel.
- *
- * @notapi
+ * @retval MSG_OK       terminated by command.
+ * @retval MSG_RESET    terminated by reset condition on the I/O channel.
  */
 static msg_t shell_thread(void *p) {
   int n;
@@ -191,7 +189,7 @@ static msg_t shell_thread(void *p) {
       }
     }
   }
-  shellExit(RDY_OK);
+  shellExit(MSG_OK);
   /* Never executed, silencing a warning.*/
   return 0;
 }
@@ -203,7 +201,7 @@ static msg_t shell_thread(void *p) {
  */
 void shellInit(void) {
 
-  chEvtInit(&shell_terminated);
+  chEvtObjectInit(&shell_terminated);
 }
 
 /**
@@ -226,7 +224,7 @@ void shellExit(msg_t msg) {
 
 /**
  * @brief   Spawns a new shell.
- * @pre     @p CH_USE_HEAP and @p CH_USE_DYNAMIC must be enabled.
+ * @pre     @p CH_CFG_USE_HEAP and @p CH_CFG_USE_DYNAMIC must be enabled.
  *
  * @param[in] scp       pointer to a @p ShellConfig object
  * @param[in] size      size of the shell working area to be allocated
@@ -236,8 +234,8 @@ void shellExit(msg_t msg) {
  *
  * @api
  */
-#if CH_USE_HEAP && CH_USE_DYNAMIC
-Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) {
+#if CH_CFG_USE_HEAP && CH_CFG_USE_DYNAMIC
+thread_t *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) {
 
   return chThdCreateFromHeap(NULL, size, prio, shell_thread, (void *)scp);
 }
@@ -254,8 +252,8 @@ Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) {
  *
  * @api
  */
-Thread *shellCreateStatic(const ShellConfig *scp, void *wsp,
-                          size_t size, tprio_t prio) {
+thread_t *shellCreateStatic(const ShellConfig *scp, void *wsp,
+                            size_t size, tprio_t prio) {
 
   return chThdCreateStatic(wsp, size, prio, shell_thread, (void *)scp);
 }
@@ -272,7 +270,7 @@ Thread *shellCreateStatic(const ShellConfig *scp, void *wsp,
  *
  * @api
  */
-bool_t shellGetLine(BaseSequentialStream *chp, char *line, unsigned size) {
+bool shellGetLine(BaseSequentialStream *chp, char *line, unsigned size) {
   char *p = line;
 
   while (TRUE) {
diff --git a/os/various/shell.h b/os/various/shell.h
index ef2676a74..d7a7dbc60 100644
--- a/os/various/shell.h
+++ b/os/various/shell.h
@@ -63,7 +63,7 @@ typedef struct {
 } ShellConfig;
 
 #if !defined(__DOXYGEN__)
-extern EventSource shell_terminated;
+extern event_source_t shell_terminated;
 #endif
 
 #ifdef __cplusplus
@@ -71,10 +71,10 @@ extern "C" {
 #endif
   void shellInit(void);
   void shellExit(msg_t msg);
-  Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio);
-  Thread *shellCreateStatic(const ShellConfig *scp, void *wsp,
-                            size_t size, tprio_t prio);
-  bool_t shellGetLine(BaseSequentialStream *chp, char *line, unsigned size);
+  thread_t *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio);
+  thread_t *shellCreateStatic(const ShellConfig *scp, void *wsp,
+                              size_t size, tprio_t prio);
+  bool shellGetLine(BaseSequentialStream *chp, char *line, unsigned size);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/various/syscalls.c b/os/various/syscalls.c
index f19f733c7..41c04bac1 100644
--- a/os/various/syscalls.c
+++ b/os/various/syscalls.c
@@ -65,11 +65,6 @@
 #include "hal.h"
 #endif
 
-#ifndef __errno_r
-#include <sys/reent.h>
-#define __errno_r(reent) reent->_errno
-#endif
-
 /***************************************************************************/
 
 int _read_r(struct _reent *r, int file, char * ptr, int len)
@@ -134,10 +129,10 @@ int _close_r(struct _reent *r, int file)
 
 caddr_t _sbrk_r(struct _reent *r, int incr)
 {
-#if CH_USE_MEMCORE
+#if CH_CFG_USE_MEMCORE
   void *p;
 
-  chDbgCheck(incr > 0, "_sbrk_r");
+  chDbgCheck(incr > 0);
 
   p = chCoreAlloc((size_t)incr);
   if (p == NULL) {
diff --git a/os/various/usb_msc.c b/os/various/usb_msc.c
deleted file mode 100644
index 61f4202d3..000000000
--- a/os/various/usb_msc.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*-*
- * @file    usb_msc.c
- * @brief   USB Mass Storage Class code.
- *
- * @addtogroup USB_MSC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#include "usb_msc.h"
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Zero-filled constant buffer.
- */
-static const uint8_t zerobuf[4] = {0, 0, 0, 0};
-
-/**
- * @brief   Answer to the INQUIRY command.
- */
-static const uint8_t scsi_inquiry_data[] = {
-  0x00,             /* Direct Access Device.      */
-  0x80,             /* RMB = 1: Removable Medium. */
-  0x02,             /* ISO, ECMA, ANSI = 2.       */
-  0x00,             /* UFI response format.       */
-
-  36 - 4,           /* Additional Length.         */
-  0x00,
-  0x00,
-  0x00,
-  /* Vendor Identification */
-  'C', 'h', 'i', 'b', 'i', 'O', 'S', ' ',
-  /* Product Identification */
-  'S', 'D', ' ', 'F', 'l', 'a', 's', 'h',
-  ' ', 'D', 'i', 's', 'k', ' ', ' ', ' ',
-  /* Product Revision Level */
-  '1', '.', '0', ' '
-};
-
-/**
- * @brief   Generic buffer.
- */
-uint8_t buf[16];
-
-/*===========================================================================*/
-/* MMC interface code.                                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* SCSI emulation code.                                                      */
-/*===========================================================================*/
-
-static uint8_t scsi_read_format_capacities(uint32_t *nblocks,
-                                           uint32_t *secsize) {
-
-  *nblocks = 1024;
-  *secsize = 512;
-  return 3; /* No Media.*/
-}
-
-/*===========================================================================*/
-/* Mass Storage Class related code.                                          */
-/*===========================================================================*/
-
-/**
- * @brief   MSC state machine current state.
- */
-static mscstate_t msc_state;
-
-/**
- * @brief   Received CBW.
- */
-static msccbw_t CBW;
-
-/**
- * @brief   CSW to be transmitted.
- */
-static msccsw_t CSW;
-
-/**
- * @brief   MSC state machine initialization.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- */
-static void msc_reset(USBDriver *usbp) {
-
-  msc_state = MSC_IDLE;
-  chSysLockFromIsr();
-  usbStartReceiveI(usbp, MSC_DATA_OUT_EP, (uint8_t *)&CBW, sizeof CBW);
-  chSysUnlockFromIsr();
-}
-
-static void msc_transmit(USBDriver *usbp, const uint8_t *p, size_t n) {
-
-  if (n > CBW.dCBWDataTransferLength)
-    n = CBW.dCBWDataTransferLength;
-  CSW.dCSWDataResidue = CBW.dCBWDataTransferLength - (uint32_t)n;
-  chSysLockFromIsr();
-  usbStartTransmitI(usbp, MSC_DATA_IN_EP, p, n);
-  chSysUnlockFromIsr();
-}
-
-static void msc_sendstatus(USBDriver *usbp) {
-
-  msc_state = MSC_SENDING_CSW;
-  chSysLockFromIsr();
-  usbStartTransmitI(usbp, MSC_DATA_IN_EP, (uint8_t *)&CSW, sizeof CSW);
-  chSysUnlockFromIsr();
-}
-
-static bool_t msc_decode(USBDriver *usbp) {
-  uint32_t nblocks, secsize;
-
-  switch (CBW.CBWCB[0]) {
-  case SCSI_REQUEST_SENSE:
-    break;
-  case SCSI_INQUIRY:
-    msc_transmit(usbp, (uint8_t *)&scsi_inquiry_data,
-                 sizeof scsi_inquiry_data);
-    CSW.bCSWStatus = MSC_CSW_STATUS_PASSED;
-    break;
-  case SCSI_READ_FORMAT_CAPACITIES:
-    buf[8]  = scsi_read_format_capacities(&nblocks, &secsize);
-    buf[0]  = buf[1] = buf[2] = 0;
-    buf[3]  = 8;
-    buf[4]  = (uint8_t)(nblocks >> 24);
-    buf[5]  = (uint8_t)(nblocks >> 16);
-    buf[6]  = (uint8_t)(nblocks >> 8);
-    buf[7]  = (uint8_t)(nblocks >> 0);
-    buf[9]  = (uint8_t)(secsize >> 16);
-    buf[10] = (uint8_t)(secsize >> 8);
-    buf[11] = (uint8_t)(secsize >> 0);
-    msc_transmit(usbp, buf, 12);
-    CSW.bCSWStatus = MSC_CSW_STATUS_PASSED;
-    break;
-  default:
-    return TRUE;
-  }
-  return FALSE;
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Default requests hook.
- * @details The application must use this function as callback for the
- *          messages hook.
- *          The following requests are emulated:
- *          - MSC_GET_MAX_LUN_COMMAND.
- *          - MSC_MASS_STORAGE_RESET_COMMAND.
- *          .
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @return              The hook status.
- * @retval TRUE         Message handled internally.
- * @retval FALSE        Message not handled.
- */
-bool_t mscRequestsHook(USBDriver *usbp) {
-
-  if ((usbp->setup[0] & (USB_RTYPE_TYPE_MASK | USB_RTYPE_RECIPIENT_MASK)) ==
-       (USB_RTYPE_TYPE_CLASS | USB_RTYPE_RECIPIENT_INTERFACE)) {
-    switch (usbp->setup[1]) {
-    case MSC_GET_MAX_LUN_COMMAND:
-      usbSetupTransfer(usbp, (uint8_t *)zerobuf, 1, NULL);
-      return TRUE;
-    case MSC_MASS_STORAGE_RESET_COMMAND:
-      msc_reset(usbp);
-      usbSetupTransfer(usbp, NULL, 0, NULL);
-      return TRUE;
-    default:
-      return FALSE;
-    }
-  }
-  return FALSE;
-}
-
-/**
- * @brief   Default data transmitted callback.
- * @details The application must use this function as callback for the IN
- *          data endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- */
-void mscDataTransmitted(USBDriver *usbp, usbep_t ep) {
-
-  switch (msc_state) {
-  case MSC_DATA_IN:
-    CSW.dCSWSignature = MSC_CSW_SIGNATURE;
-    CSW.dCSWTag = CBW.dCBWTag;
-    chSysLockFromIsr();
-    usbStartTransmitI(usbp, ep, (uint8_t *)&CSW, sizeof CSW);
-    chSysUnlockFromIsr();
-    msc_state = MSC_SENDING_CSW;
-    break;
-  case MSC_SENDING_CSW:
-    chSysLockFromIsr();
-    usbStartReceiveI(usbp, MSC_DATA_OUT_EP, (uint8_t *)&CBW, sizeof CBW);
-    chSysUnlockFromIsr();
-    msc_state = MSC_IDLE;
-    break;
-  default:
-    ;
-  }
-}
-
-/**
- * @brief   Default data received callback.
- * @details The application must use this function as callback for the OUT
- *          data endpoint.
- *
- * @param[in] usbp      pointer to the @p USBDriver object
- * @param[in] ep        endpoint number
- */
-void mscDataReceived(USBDriver *usbp, usbep_t ep) {
-  size_t n;
-
-  n = usbGetReceiveTransactionSizeI(usbp, ep);
-  switch (msc_state) {
-  case MSC_IDLE:
-    if ((n != sizeof(msccbw_t)) || (CBW.dCBWSignature != MSC_CBW_SIGNATURE))
-      goto stall_out; /* 6.6.1 */
-
-    /* Decoding SCSI command.*/
-    if (msc_decode(usbp)) {
-      if (CBW.dCBWDataTransferLength == 0) {
-        CSW.bCSWStatus = MSC_CSW_STATUS_FAILED;
-        CSW.dCSWDataResidue = 0;
-        msc_sendstatus(usbp);
-        return;
-      }
-      goto stall_both;
-    }
-
-    /* Commands with zero transfer length, 5.1.*/
-    if (CBW.dCBWDataTransferLength == 0) {
-      msc_sendstatus(usbp);
-      return;
-    }
-
-    /* Transfer direction.*/
-    if (CBW.bmCBWFlags & 0x80) {
-      /* IN, Device to Host.*/
-      msc_state = MSC_DATA_IN;
-    }
-    else {
-      /* OUT, Host to Device.*/
-      msc_state = MSC_DATA_OUT;
-    }
-    break;
-  case MSC_DATA_OUT:
-    break;
-  default:
-    ;
-  }
-  return;
-stall_out:
-  msc_state = MSC_ERROR;
-  chSysLockFromIsr();
-  usbStallReceiveI(usbp, ep);
-  chSysUnlockFromIsr();
-  return;
-stall_both:
-  msc_state = MSC_ERROR;
-  chSysLockFromIsr();
-  usbStallTransmitI(usbp, ep);
-  usbStallReceiveI(usbp, ep);
-  chSysUnlockFromIsr();
-  return;
-}
-
-/** @} */
diff --git a/os/various/usb_msc.h b/os/various/usb_msc.h
deleted file mode 100644
index 5e5a80c1f..000000000
--- a/os/various/usb_msc.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/*-*
- * @file    usb_msc.h
- * @brief   USB Mass Storage Class header.
- *
- * @addtogroup USB_MSC
- * @{
- */
-
-#ifndef _USB_MSC_H_
-#define _USB_MSC_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-#define MSC_CBW_SIGNATURE               0x43425355
-#define MSC_CSW_SIGNATURE               0x53425355
-
-#define MSC_GET_MAX_LUN_COMMAND         0xFE
-#define MSC_MASS_STORAGE_RESET_COMMAND  0xFF
-
-#define MSC_CSW_STATUS_PASSED           0
-#define MSC_CSW_STATUS_FAILED           1
-#define MSC_CSW_STATUS_PHASE_ERROR      2
-
-
-#define SCSI_FORMAT_UNIT            0x04
-#define SCSI_INQUIRY                0x12
-#define SCSI_MODE_SELECT6           0x15
-#define SCSI_MODE_SELECT10          0x55
-#define SCSI_MODE_SENSE6            0x1A
-#define SCSI_MODE_SENSE10           0x5A
-#define SCSI_ALLOW_MEDIUM_REMOVAL   0x1E
-#define SCSI_READ6                  0x08
-#define SCSI_READ10                 0x28
-#define SCSI_READ12                 0xA8
-#define SCSI_READ16                 0x88
-
-#define SCSI_READ_CAPACITY10        0x25
-#define SCSI_READ_CAPACITY16        0x9E
-
-#define SCSI_REQUEST_SENSE          0x03
-#define SCSI_START_STOP_UNIT        0x1B
-#define SCSI_TEST_UNIT_READY        0x00
-#define SCSI_WRITE6                 0x0A
-#define SCSI_WRITE10                0x2A
-#define SCSI_WRITE12                0xAA
-#define SCSI_WRITE16                0x8A
-
-#define SCSI_VERIFY10               0x2F
-#define SCSI_VERIFY12               0xAF
-#define SCSI_VERIFY16               0x8F
-
-#define SCSI_SEND_DIAGNOSTIC        0x1D
-#define SCSI_READ_FORMAT_CAPACITIES 0x23
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Endpoint number for bulk IN.
- */
-#if !defined(MSC_DATA_IN_EP) || defined(__DOXYGEN__)
-#define MSC_DATA_IN_EP          1
-#endif
-
-/**
- * @brief   Endpoint number for bulk OUT.
- */
-#if !defined(MSC_DATA_OUT_EP) || defined(__DOXYGEN__)
-#define MSC_DATA_OUT_EP         2
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Type of the MSC possible states.
- */
-typedef enum {
-  MSC_IDLE = 0,
-  MSC_DATA_OUT,
-  MSC_DATA_IN,
-  MSC_SENDING_CSW,
-  MSC_ERROR
-} mscstate_t;
-
-/**
- * @brief   CBW structure.
- */
-struct CBW {
-  uint32_t          dCBWSignature;
-  uint32_t          dCBWTag;
-  uint32_t          dCBWDataTransferLength;
-  uint8_t           bmCBWFlags;
-  uint8_t           bCBWLUN;
-  uint8_t           bCBWCBLength;
-  uint8_t           CBWCB[16];
-};
-
-/**
- * @brief   CSW structure.
- */
-struct CSW {
-  uint32_t          dCSWSignature;
-  uint32_t          dCSWTag;
-  uint32_t          dCSWDataResidue;
-  uint8_t           bCSWStatus;
-};
-
-/**
- * @brief   Type of a CBW structure.
- */
-typedef struct CBW msccbw_t;
-
-/**
- * @brief   Type of a CSW structure.
- */
-typedef struct CSW msccsw_t;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  bool_t mscRequestsHook(USBDriver *usbp);
-  void mscDataTransmitted(USBDriver *usbp, usbep_t ep);
-  void mscDataReceived(USBDriver *usbp, usbep_t ep);
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _USB_MSC_H_ */
-
-/** @} */
diff --git a/os/various/various.dox b/os/various/various.dox
index 488031886..57c37829c 100644
--- a/os/various/various.dox
+++ b/os/various/various.dox
@@ -1,17 +1,21 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
 
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
+    This file is part of ChibiOS/RT.
 
-        http://www.apache.org/licenses/LICENSE-2.0
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
 
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
 /**